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3.3V PCIe Gen1�5 Clock Generator Family
9FGL02x1/04x1/06x1/08x1 Datasheet
Description
The 9FGL02x1/04x1/06x1/08x1 devices comprise a family of 3.3V PCIe Gen1�5 clock generators. There are 2, 4, 6 and 8 outputs versions available and each differential output has a dedicated OE# pin supporting PCIe CLKREQ# functionality.
PCIe Clocking Architectures
Common Clocked (CC) Independent Reference (IR) with and without spread spectrum
(SRIS, SRNS)
Typical Applications
Servers/High-Performance Computing nVME Storage Networking Accelerators Industrial Control
Output Features
2, 4, 6, or 8 100MHz PCIe output pairs One 3.3V LVCMOS REF output with Wake-On-LAN (WOL)
support See AN-891 for easy AC-coupling to other logic families
Key Specifications
90fs RMS typical jitter (PCIe Gen5 CC) < 50ps cycle-to-cycle jitter on differential outputs < 50ps output-to-output skew on differential outputs �0ppm synthesis error on differential outputs
Features
Integrated terminations for 100 and 85 systems save 4 resistors per output
112�206 mW typical power consumption (at 3.3V) VDDIO rail allows 35% power savings at optional 1.05V
(9FGL06 and 9FGL08 only)
Devices contain default configuration; SMBus not required SMBus-selectable features allows optimization to customer
requirements:
� Input polarity and pull-up/pull-downs � Output slew rate and amplitude � Output impedance (33, 85 or 100) for each output
Contact factory for customized default configurations 25MHz input frequency OE# pins support PCIe CLKREQ# function Pin-selectable SRnS 0%, CC 0% and CC/SRIS -0.5% spread SMBus-selectable CC/SRIS -0.25% spread Clean switching between the CC/SRIS spread settings DIF outputs blocked until PLL is locked; clean system start-up 2 selectable SMBus addresses Space saving packages:
� 4 � 4 mm 24-VFQFPN (9FGL02x1) � 5 � 5 mm 32-VFQFPN (9FGL04x1) � 5 � 5 mm 40-VFQFPN (9FGL06x1) � 6 � 6 mm 48-VFQFPN (9FGL08x1)
Block Diagram
vOE(n:0)# XIN/CLKIN_25
X2
vS ADR ^vSS_EN_tri ^CKPWRGD_PD# SDATA_3.3
SCLK_3.3
VDDREF
VDDO/
VDDA VDDXTAL VDDDIG VDDIO
n+1
Control Logic
SS C Capable
PLL
GNDXTAL GNDDIG GND EPAD GNDREF
REF3.3 DIFn# DIFn
2 to 8 outputs
DIF0# DIF0
�2020 Renesas Electronics Corporation
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9FGL02x1/04x1/06x1/08x1 Datasheet
Contents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 PCIe Clocking Architectures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Output Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Key Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
9FGL02x1 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 9FGL04x1 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 9FGL06x1 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 9FGL08x1 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Test Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Alternate Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Crystal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 General SMBus Serial Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
How to Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 How to Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Package Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Marking Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9FGL02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9FGL04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9FGL06 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9FGL08 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
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9FGL02x1/04x1/06x1/08x1 Datasheet
Pin Assignments
9FGL02x1 Pin Assignment
Figure 1. Pin Assignments for 4 � 4 mm 24-VFQFPN Package � Top View
GNDXTAL ^vSS_EN_tri ^CKPWRGD_PD# GND VDD3.3 vOE1#
XIN/CLKIN_25 1 X2 2
VDDXTAL3.3 3 vSADR/REF3.3 4
GNDREF 5 GNDDIG 6
24 23 22 21 20 19
9FGL0241C 9FGL0251C EPAD is GND
18 DIF1# 17 DIF1 16 VDDA3.3 15 GNDA 14 DIF0#
13 DIF0
7 8 9 10 11 12
VDDDIG3.3 SCLK_3.3
SDATA_3.3 GND
VDD3.3 vOE0 #
24-VFQFPN, 4 x 4 mm, 0.5mm pitch
^ prefix indicates internal 120kOhm pull-up resistor v prefix indicates internal 120kOhm pull-down resistor ^v prefix indicates internal 120kOhm pull-up and pull-down resistors
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9FGL02x1/04x1/06x1/08x1 Datasheet
9FGL04x1 Pin Assignment
Figure 2. Pin Assignments for 5 � 5 mm 32-VFQFPN Package � Top View
^vSS_EN_tri ^CKPWRGD_PD# GND vOE3# DIF3# DIF3 GND VDDO3.3
GNDXTAL 1 XIN/CLKIN_25 2
X2 3 VDDXTAL3.3 4 VDDREF3.3 5 vSADR/REF3.3 6
GNDREF 7 GNDDIG 8
32 31 30 29 28 27 26 25
9FGL0441C 9FGL0451C EPAD is GND
9 10 11 12 13 14 15 16
24 vOE2# 23 DIF2# 22 DIF2 21 VDDA3.3 20 GNDA 19 DIF1# 18 DIF1 17 vOE1#
VDDDIG3.3 SCLK_3.3
SDATA_3.3 vOE0# DIF0 DIF0# GND
VDDO3.3
32-VFQFPN, 5 x 5 mm, 0.5mm pitch
^ prefix indicates internal 120kOhm pull-up resistor v prefix indicates internal 120kOhm pull-down resistor ^v prefix indicates internal 120kOhm pull-up and pull-down resistors
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9FGL02x1/04x1/06x1/08x1 Datasheet
9FGL06x1 Pin Assignment
Figure 3. Pin Assignments for 5 � 5 mm 40-VFQFPN Package � Top View
^CKPWRGD_PD# VDDIO vOE5# DIF5# DIF5 vOE4# DIF4# DIF4 VDDIO VDD3.3
40 39 38 37 36 35 34 33 32 31
^vSS_EN_tri 1
30 vOE3#
XIN/CLKIN_25 2
29 DIF3#
X2 3
28 DIF3
VDDXTAL3.3 4 VDDREF3.3 5 vSADR/REF3.3 6
NC 7
9FGL0641C 9FGL0651C EPAD is GND
27 VDDIO 26 VDDA3.3 25 NC 24 vOE2#
GNDDIG 8
23 DIF2#
SCLK_3.3 9
22 DIF2
SDATA_3.3 10
21 vOE1#
11 12 13 14 15 16 17 18 19 20
VDDDIG3.3 VDDIO vOE0# DIF0 DIF0# VDD3.3 VDDIO DIF1 DIF1# NC
40-VFQFPN, 5 x 5 mm, 0.4mm pitch
^ prefix indicates internal 120kOhm pull-up resistor v prefix indicates internal 120kOhm pull-down resistor ^v prefix indicates internal 120kOhm pull-up and pull-down resistors
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9FGL02x1/04x1/06x1/08x1 Datasheet
9FGL08x1 Pin Assignment
Figure 4. Pin Assignments for 6 � 6 mm 48-VFQFPN Package � Top View
^CKPWRGD_PD# VDDIO vOE7# DIF7# DIF7 vOE6# DIF6# DIF6 GND VDDIO VDD3.3 vOE5#
^vSS_EN_tri 1 GNDXTAL 2
XIN/CLKIN_25 3 X2 4
VDDXTAL3.3 5 VDDREF3.3 6 vSADR/REF3.3 7
GNDREF 8 GNDDIG 9 SCLK_3.3 10 SDATA_3.3 11 VDDDIG3.3 12
48 47 46 45 44 43 42 41 40 39 38 37
9FGL0841C 9FGL0851C EPAD is GND
13 14 15 16 17 18 19 20 21 22 23 24
36 DIF5# 35 DIF5 34 vOE4# 33 DIF4# 32 DIF4 31 VDDIO 30 VDDA3.3 29 GNDA 28 vOE3# 27 DIF3# 26 DIF3 25 vOE2#
VDDIO vOE0#
DIF0 DIF0# vOE1#
DIF1 DIF1# VDD3.3 VDDIO GND
DIF2 DIF2#
48-VFQFPN, 6 x 6 mm, 0.4mm pitch
^ prefix indicates internal pull-up resistor v prefix indicates internal pull-down resistor ^v prefix indicates internal pull-up and pull-down resistors
Pin Descriptions
Table 1. Pin Descriptions
Name
Type
Description
Input notifies device to sample latched inputs and start up
^CKPWRGD_PD#
Input
on first high assertion. Low enters Power Down Mode, subsequent high assertions exit Power Down Mode. This
pin has internal pull-up resistor.
^vSS_EN_tri
Latched In
Latched select input to select spread spectrum amount at initial power up. See Spread Selection table.
DIF0
Output Differential true clock output.
DIF0#
Output Differential complementary clock output.
DIF1
Output Differential true clock output.
9FGL08x1 9FGL06x1 9FGL04x1 9FGL02x1 Pin No. Pin No. Pin No. Pin No.
48
40
31
22
1
1
32
23
15
14
13
13
16
15
14
14
18
18
18
17
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Table 1. Pin Descriptions (Cont.)
Name
DIF1# DIF2 DIF2# DIF3 DIF3# DIF4 DIF4# DIF5 DIF5# DIF6 DIF6# DIF7 DIF7# EPAD GND GND GNDA GNDDIG GNDREF GNDXTAL NC SCLK_3.3 SDATA_3.3 VDD3.3 VDD3.3 VDDA3.3 VDDDIG3.3 VDDIO VDDIO VDDIO VDDIO VDDIO VDDREF3.3 VDDXTAL3.3
Type
Description
Output Output Output Output Output Output Output Output Output Output Output Output Output GND GND GND GND GND GND GND
-- Input I/O Power Power Power Power Power Power Power Power Power Power Power
Differential complementary clock output. Differential true clock output. Differential complementary clock output. Differential true clock output. Differential complementary clock output. Differential true clock output. Differential complementary clock output. Differential true clock output. Differential complementary clock output. Differential true clock output. Differential complementary clock output. Differential true clock output. Differential complementary clock output. Connect to ground. Ground pin. Ground pin. Ground pin for the PLL core. Ground pin for digital circuitry. Ground pin for the REF outputs. GND for XTAL. No connect. Clock pin of SMBus circuitry, 3.3V tolerant. Data pin for SMBus circuitry, 3.3V tolerant. Power supply, nominally 3.3V. Power supply, nominally 3.3V. 3.3V power for the PLL core. 3.3V digital power (dirty power). Power supply for differential outputs. Power supply for differential outputs. Power supply for differential outputs. Power supply for differential outputs. Power supply for differential outputs. Power supply for REF output, nominally 3.3V. Power supply for XTAL, nominally 3.3V.
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9FGL02x1/04x1/06x1/08x1 Datasheet
9FGL08x1 9FGL06x1 9FGL04x1 9FGL02x1 Pin No. Pin No. Pin No. Pin No.
19
19
19
18
23
22
22
--
24
23
23
--
26
28
27
--
27
29
28
--
32
33
--
--
33
34
--
--
35
36
--
--
36
37
--
--
41
--
--
--
42
--
--
--
44
--
--
--
45
--
--
--
49
41
33
25
22
EPAD
15
10
40
EPAD 26, 30
21
29
EPAD
20
15
9
8
8
6
8
--
7
5
2
EPAD
1
24
--
7, 25
--
--
10
9
10
8
11
10
11
9
20
16
16
11
38
31
25
20
30
26
21
16
12
11
9
7
13
12
--
--
21
17
--
--
31
27
--
--
39
32
--
--
47
39
--
--
6
5
5
--
5
4
4
3
November 17, 2020
9FGL02x1/04x1/06x1/08x1 Datasheet
Table 1. Pin Descriptions (Cont.)
Name vOE0# vOE1# vOE2# vOE3# vOE4# vOE5# vOE6# vOE7# vSADR/REF3.3
X2 XIN/CLKIN_25
Type
Description
Active low input for enabling output 0. This pin has an Input internal pull-down.
1 = disable output, 0 = enable output.
Active low input for enabling output 1. This pin has an Input internal pull-down.
1 = disable output, 0 = enable output.
Active low input for enabling output 2. This pin has an Input internal pull-down.
1 = disable output, 0 = enable output.
Active low input for enabling output 3. This pin has an Input internal pull-down.
1 = disable output, 0 = enable output.
Active low input for enabling output 4. This pin has an Input internal pull-down.
1 = disable output, 0 = enable output.
Active low input for enabling output 5. This pin has an Input internal pull-down.
1 = disable output, 0 = enable output.
Active low input for enabling output 6. This pin has an Input internal pull-down.
1 = disable output, 0 = enable output.
Active low input for enabling output 7. This pin has an Input internal pull-down.
1 = disable output, 0 = enable output.
Latched I/O
Latch to select SMBus Address/3.3V LVCMOS copy of X1/REFIN pin.
Output Crystal output.
Input Crystal input or Reference Clock input, nominally 25MHz.
9FGL08x1 9FGL06x1 9FGL04x1 9FGL02x1 Pin No. Pin No. Pin No. Pin No.
14
13
12
12
17
21
17
19
25
24
24
--
28
30
29
--
34
35
--
--
37
38
--
--
43
--
--
--
46
--
--
--
7
6
6
4
4
3
3
2
3
2
2
1
Table 2. Spread Selection
^vSS_EN_tri Pin 0 --
M (VDD/2) 1
B1[4:3] 00 01 10 11
Spread% 0
-0.25 0
-0.50
Note PCIe SRNS mode. PCIe Common Clock or SRIS mode. PCIe Common Clock or SRIS mode. PCIe Common Clock or SRIS mode.
If SRnS mode is desired, power up with ^vSS_EN_tri = '0'. Do not attempt to switch to the other modes via SMBus control in Byte 1 or a system reset will be required. If Common Clock (CC) or SRIS mode is desired, power up with ^vSS_EN_tri at either 'M' or '1'. The desired spread spectrum amount can then be selected via Byte 1 without a requiring a system reset. Once 'M' or '1' is latched at power up, do not attempt to enter SRnS mode or a system reset will be required.
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9FGL02x1/04x1/06x1/08x1 Datasheet
Absolute Maximum Ratings
The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the device. Functional operation of the 9FGL02x1/04x1/06x1/08x1 at absolute maximum ratings is not implied. Exposure to absolute maximum rating conditions may affect device reliability.
Table 3. Absolute Maximum Ratings
Parameter
Symbol
Conditions
Supply Voltage Input Voltage Input High Voltage, SMBus Storage Temperature Junction Temperature Input ESD Protection
VDDx VIN VIHSMB Ts Tj ESD prot
SMBus clock and data pins. Human Body Model.
1 Guaranteed by design and characterization, not 100% tested in production. 2 Operation under these conditions is neither implied nor guaranteed. 3 Not to exceed 4.6V.
Minimum Maximum Units Notes
-0.5
4.6
V 1,2
-0.5
VDD + 0.5 V
1,3
3.9
V
1
-65
150
�C
1
125
�C
1
2500
V
1
Thermal Characteristics
Table 4. Thermal Characteristics
Parameter
9FGL02 Thermal Resistance
9FGL04 Thermal Resistance
9FGL06 Thermal Resistance
Symbol
JC Jb JA0 JA1 JA3 JA5 JC Jb JA0 JA1 JA3 JA5 JC Jb JA0 JA1 JA3 JA5
Conditions
Junction to case. Junction to base. Junction to air, still air. Junction to air, 1 m/s air flow. Junction to air, 3 m/s air flow. Junction to air, 5 m/s air flow. Junction to case. Junction to base. Junction to air, still air. Junction to air, 1 m/s air flow. Junction to air, 3 m/s air flow. Junction to air, 5 m/s air flow. Junction to case. Junction to base. Junction to air, still air. Junction to air, 1 m/s air flow. Junction to air, 3 m/s air flow. Junction to air, 5 m/s air flow.
Package NLG24 NLG32 NDG40
Typical Values
62 5.4 50 43 39 38 42 2.4 39 33 28 27 42 2.4 39 33 28 27
Units
�C/W �C/W �C/W �C/W �C/W �C/W �C/W �C/W �C/W �C/W �C/W �C/W �C/W �C/W �C/W �C/W �C/W �C/W
Notes
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
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9FGL02x1/04x1/06x1/08x1 Datasheet
Table 4. Thermal Characteristics (Cont.)
Parameter
Symbol
JC
Jb
9FGL08 Thermal
JA0
Resistance
JA1
JA3
JA5
1 EPAD soldered to board.
Conditions Junction to case. Junction to base. Junction to air, still air. Junction to air, 1 m/s air flow. Junction to air, 3 m/s air flow. Junction to air, 5 m/s air flow.
Package NDG48
Typical Values 33 2.1 37 30 27 26
Units �C/W �C/W �C/W �C/W �C/W �C/W
Notes 1 1 1 1 1 1
Electrical Characteristics
TA = TAMB. Supply voltages per normal operation conditions; see Test Loads for loading conditions. Table 5. SMBus Parameters
Parameter
Symbol
Conditions
SMBus Input Low Voltage SMBus Input High Voltage SMBus Output Low Voltage
SMBus Sink Current Nominal Bus Voltage SCLK/SDATA Rise Time SCLK/SDATA Fall Time SMBus Operating Frequency
VILSMB VIHSMB VOLSMB IPULLUP VDDSMB tRSMB tFSMB fSMB
VDDSMB = 3.3V. VDDSMB = 3.3V. At IPULLUP. At VOL.
(Max. VIL - 0.15V) to (Min. VIH + 0.15V). (Min. VIH + 0.15V) to (Max. VIL - 0.15V). SMBus operating frequency.
1 Guaranteed by design and characterization, not 100% tested in production. 2 The device must be powered up for the SMBus to function.
Minimum Typical Maximum Units Notes
0.8
V
2.1
3.6
V
0.4
V
4
mA
2.7
3.6
V
1000
ns
1
300
ns
1
500
kHz 2
Table 6. Input/Supply/Common Parameters � Normal Operating Conditions
Parameter
Symbol
Conditions
Minimum Typical
Supply Voltage
IO Supply Voltage Ambient Operating
Temperature
VDDxxx
Supply voltage for core, analog and single-ended LVCMOS outputs.
VDDIO Supply voltage for differential low power outputs.
TAMB Industrial range.
3.135 0.9975
-40
3.3 1.05�3.3
25
Input High Voltage Input Low Voltage Input High Voltage Input Mid Voltage Input Low Voltage
VIH Single-ended inputs, except SMBus. VIL
VIHtri
VIMtri
Single-ended tri-level inputs ('_tri' suffix).
VILtri
0.75 x VDDx -0.3
0.8 x VDDx 0.4 x VDDx 0.5 x VDDx
-0.3
Maximum
3.465 3.465
85 VDDx + 0.3 0.25 x VDDx VDDx + 0.3 0.6 x VDDx 0.20 x VDDx
Units
V V �C V V V V V
Notes
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9FGL02x1/04x1/06x1/08x1 Datasheet
Table 6. Input/Supply/Common Parameters � Normal Operating Conditions (Cont.)
Parameter
Symbol
Conditions
Input Current
IIN Single-ended inputs, VIN = GND, VIN = VDD.
Single-ended inputs.
IINP
VIN = 0V; inputs with internal pull-up resistors. VIN = VDD; inputs with internal pull-down
resistors.
Input Frequency Pin Inductance Capacitance
CLK Stabilization
FIN Lpin CIN COUT
tSTAB
XTAL or X1 input.
Logic inputs, except DIF_IN. Output pin capacitance. From VDD power-up and after input clock stabilization or deassertion of PD# to 1st clock.
SS Modulation Frequency
OE# Latency
fMOD Triangular modulation. DIF start after OE# assertion.
tLATOE# DIF stop after OE# deassertion.
Tdrive_PD#
tDRVPD DIF output enable after PD# de-assertion.
Fall Time
tF Fall time of single-ended control inputs.
Rise Time
tR Rise time of single-ended control inputs.
1 Guaranteed by design and characterization, not 100% tested in production. 2 Control input must be monotonic from 20% to 80% of input swing. 3 Time from deassertion until outputs are > 200mV. 4 Contact the factory for other frequencies.
Minimum -5 -50
1.5
30 1
Typical -0.05
7 25
0.3 31.6
2
Maximum 5
Units Notes A
50
A
MHz 4
7
nH
1
5
pF
1
6
pF
1
1.8
ms 1,2
33
kHz 1
3
clocks 1,3
300
s 1,3
5
ns 1,2
5
ns 1,2
Table 7. Differential Low-Power HCSL Outputs
Parameter
Symbol
Conditions
Minimum Typical Maximum Units Notes
Slew Rate
Scope averaging on, fast setting.
2
Trf
Scope averaging, slow setting.
1
Crossing Voltage (abs) Vcross_abs Scope averaging off.
250
Crossing Voltage (var)
-Vcross Scope averaging off.
9FGL0xxx devices have 0 ppm
Avg. Clock Period Accuracy TPERIOD_AVG synthesis error. The maximum occurs
0
with -0.5% SSC.
Absolute Period
TPERIOD_ABS
Includes jitter and spread spectrum modulation.
9.95
Jitter, Cycle to Cycle Voltage High
Voltage Low
tjcyc-cyc
VHIGH Statistical measurement on
660
single-ended signal using
VLOW
oscilloscope math function (scope averaging on).
-150
2.7
4
V/ns 2,3
1.9
3
V/ns 2,3
409
550
mV 1,4,5
14
140
mV 1,4,9
0
+2500 ppm 2,10,12,13
10 10.0503 ns
2,6
16
50
ps
2
761
850
mV
1
-7
150
mV
1
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9FGL02x1/04x1/06x1/08x1 Datasheet
Table 7. Differential Low-Power HCSL Outputs (Cont.)
Parameter
Symbol
Conditions
Minimum Typical Maximum Units Notes
Absolute Maximum Voltage
VMIN
Measurement on single-ended signal
819
1150 mV 1,7,15
using absolute value (scope
Absolute Minimum Voltage
VMAX
averaging off).
-300
-46
1,8,15
Duty Cycle Slew Rate Matching
tDC
Trf
Single-ended measurement.
45
49
6
55
%
2
20
%
1,14
Skew, Output to Output
tsk3
Averaging on, VT = 50%.
12
50
ps
2
1 Measured from single-ended waveform. 2 Measured from differential waveform. 3 Measured from -150 mV to +150 mV on the differential waveform (derived from REFCLK+ minus REFCLK-). The signal must be monotonic through
the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing. 4 Measured at crossing point where the instantaneous voltage value of the rising edge of REFCLK+ equals the falling edge of REFCLK-. 5 Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this
measurement. 6 Defines as the absolute minimum or maximum instantaneous period. This includes cycle to cycle jitter, relative ppm tolerance, and spread spectrum
modulation. 7 Defined as the maximum instantaneous voltage including overshoot. 8 Defined as the minimum instantaneous voltage including undershoot. 9 Defined as the total variation of all crossing voltages of Rising REFCLK+ and Falling REFCLK-. This is the maximum allowed variance in VCROSS
for any particular system. 10 Refer to Section 8.6.2 of the PCI Express Base Specification, Revision 5.0 for information regarding PPM considerations. 11 System board compliance measurements must use the test load. REFCLK+ and REFCLK- are to be measured at the load capacitors CL.
Single-ended probes must be used for measurements requiring single ended measurements. Either single-ended probes with math or differential probe can be used for differential measurements. Test load CL = 2pF. 12 PCIe Gen1 through Gen4 specify �300ppm frequency tolerances. PCIe Gen5 reduces the allowable tolerance to �100ppm without spread spectrum. 13 "ppm" refers to parts per million and is a DC absolute period accuracy specification. 1ppm is 1/1,000,000th of 100.000000MHz exactly or 100Hz. For 100ppm, then we have an error budget of 100Hz/ppm � 100ppm = 10kHz. The period is to be measured with a frequency counter with measurement window set to 100ms or greater. The �100ppm applies to systems that do not employ Spread Spectrum clocking, or that use common clock source. For systems employing Spread Spectrum clocking, there is an additional 2,500ppm nominal shift in maximum period resulting from the 0.5% down spread resulting in a maximum average period specification of +2,600ppm for Common Clock architectures. Separate Reference Clock architectures may have a lower allowed spread percentage. 14 Matching applies to rising edge rate for REFCLK+ and falling edge rate for REFCLK-. It is measured using a �75 mV window centered on the median cross point where REFCLK+ rising meets REFCLK- falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The Rise Edge Rate of REFCLK+ should be compared to the Fall Edge Rate of REFCLK-; the maximum allowed difference should not exceed 20% of the slowest edge rate. 15 At default SMBus amplitude settings.
Table 8. 12kHz�20MHz Phase Jitter of Differential Outputs
Parameter
Symbol
Conditions
Phase Jitter, 12kHz�20MHz
tjph12k20M
Differential outputs when device is set to PCIe SRnS mode (Byte1[4:3] = 00).
Minimum Typical Maximum Units
1.9
2
ps (rms)
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9FGL02x1/04x1/06x1/08x1 Datasheet
Table 9. Current Consumption � 9FGL02
Parameter
Symbol
Conditions
Minimum Typical Maximum Units Notes
Operating Supply Current
Wake-on-LAN Current (Power down state and
Byte 3, bit 5 = '1')
Power Down Current (Power down state and
Byte 3, bit 5 = '0')
IDDAOP IDDOP IDDAPD IDDPD IDDAPD IDDPD
VDDA, all outputs active at 100MHz. All VDD, except VDDA, all outputs active at100MHz. VDDA, DIF outputs off, REF output running. All VDD, except VDDA, DIF outputs off, REF output running. VDDA, all outputs off.
All VDD, except VDDA, all outputs off.
13
17
mA
18
23
mA
0.9
1.5 mA 1
5.7
8
mA 1
0.9
1.5 mA
1.7
2.5 mA
1 This is the current required to have the REF output running in Wake-on-LAN mode (Byte 3, bit 5 = 1).
Table 10. Current Consumption � 9FGL04
Parameter
Symbol
Conditions
Minimum Typical Maximum Units Notes
Operating Supply Current
Wake-on-LAN Current (Power down state and
Byte 3, bit 5 = '1')
Power Down Current (Power down state and
Byte 3, bit 5 = '0')
IDDAOP IDDOP IDDAPD IDDPD IDDAPD IDDPD
VDDA, all outputs active at 100MHz. All other VDD, except VDDA, all outputs active at100MHz. VDDA, DIF outputs off, REF output running. All other VDD, except VDDA, DIF outputs off, REF output running. VDDA, all outputs off.
All other VDD, except VDDA, all outputs off.
13
17
mA
30
39
mA
0.9
1.5 mA 1
5.9
8.0 mA 1
0.9
1.5 mA
1.5
2.5 mA
1 This is the current required to have the REF output running in Wake-on-LAN mode (Byte 3, bit 5 = 1).
Table 11. Current Consumption � 9FGL06
Parameter
Operating Supply Current
Wake-on-LAN Current (Power down state and
Byte 3, bit 5 = '1')
Symbol
Conditions
Minimum Typical Maximum Units Notes
IDDAOP IDDOP
VDDA, all outputs active at 100MHz. All VDD, except VDDA and VDDIO, all outputs active at100MHz.
14
17
mA
16
20
mA
IDDIOOP IDDAPD IDDPD
VDDIO, all outputs active at100MHz. VDDA, DIF outputs off, REF output running. All VDD, except VDDA and VDDIO, DIF outputs off, REF output running.
27
32
mA
0.9
1.5 mA 1
6
8
mA 1
IDDIOOP VDDIO, DIF outputs off, REF output running.
0.04 0.05 mA 1
�2020 Renesas Electronics Corporation
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9FGL02x1/04x1/06x1/08x1 Datasheet
Table 11. Current Consumption � 9FGL06
Parameter
Power Down Current (Power down state and
Byte 3, bit 5 = '0')
Symbol
Conditions
IDDAPD IDDPD
VDDA, all outputs off. All VDD, except VDDA and VDDIO, all outputs off.
IDDIOOP VDDIO, all outputs off.
Minimum Typical Maximum Units Notes
0.9
1.5 mA
1.8
2.5 mA
0.04 0.08 mA
1 This is the current required to have the REF output running in Wake-on-LAN mode (Byte 3, bit 5 = 1).
Table 12. Current Consumption � 9FGL08
Parameter
Symbol
Conditions
Minimum Typical Maximum Units Notes
Operating Supply Current
Wake-on-LAN Current (Power down state and
Byte 3, bit 5 = '1')
Power Down Current (Power down state and
Byte 3, bit 5 = '0')
IDDAOP IDDOP
VDDA, all outputs active at 100MHz. All VDD, except VDDA and VDDIO, all outputs active at100MHz.
IDDIOOP IDDAPD IDDPD
VDDIO, all outputs active at100MHz. VDDA, DIF outputs off, REF output running. All VDD, except VDDA and VDDIO, DIF outputs off, REF output running.
IDDIOOP IDDAPD IDDPD
VDDIO, DIF outputs off, REF output running. VDDA, all outputs off. All VDD, except VDDA and VDDIO, all outputs off.
IDDIOOP VDDIO, all outputs off.
14
19
mA
18
24
mA
30
37
mA
0.9
1.5 mA 1
5.2
8
mA 1
0.04
0.1 mA 1
0.9
1.5 mA
1.7
2.3 mA
0.04
0.1 mA
1 This is the current required to have the REF output running in Wake-on-LAN mode (Byte 3, bit 5 = 1).
Table 13. PCIe Phase Jitter of Differential Outputs TAMB = over the specified operating range. Supply voltages per normal operation conditions. See Test Loads for loading conditions.
Parameter
PCIe Phase Jitter (Common Clocked
Architecture)
PCIe Phase Jitter (SRIS Architecture)
Symbol
Conditions
Minimum
tjphPCIeG1-CC tjphPCIeG2-CC
PCIe Gen1 (2.5 GT/s) PCIe Gen2 Hi Band (5.0 GT/s) PCIe Gen2 Lo Band (5.0 GT/s)
tjphPCIeG3-CC tjphPCIeG4-CC tjphPCIeG5-CC tjphPCIeG1-SRIS tjphPCIeG2-SRIS tjphPCIeG3-SRIS tjphPCIeG4-SRIS tjphPCIeG5-SRIS
PCIe Gen3 (8.0 GT/s) PCIe Gen4 (16.0 GT/s) PCIe Gen5 (32.0 GT/s) PCIe Gen1 (2.5 GT/s) PCIe Gen2 (5.0 GT/s) PCIe Gen3 (8.0 GT/s) PCIe Gen4 (16.0 GT/s) PCIe Gen5 (32.0 GT/s)
Typical 18 0.9 0.4 0.25 0.25 0.09 4 0.8 0.3 0.3 0.15
Maximum Limit Units Notes
28
86 ps (p-p) 1,2,7
1.6
3 ps (RMS) 1,2,7
0.6
3.1 ps (RMS) 1,2,
0.4
1 ps (RMS) 1,2,3,7
0.4
0.5 ps (RMS) 1,2,3,4,7
0.11 0.15 ps (RMS) 1,2,3,5,7
6
ps (RMS) 1,2,6,8
1.1
ps (RMS) 1,2,6,8
0.4 N/A ps (RMS) 1,2,6,8
0.35
ps (RMS) 1,2,6,8
0.19
ps (RMS) 1,2,6,8
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9FGL02x1/04x1/06x1/08x1 Datasheet
1 The REFCLK jitter is measured after applying the filter functions found in PCI Express Base Specification 5.0, Revision 1.0. See the Test Loads section of the data sheet for the exact measurement setup. Values for the Common Clock architecture are calculated for CC/SRIS spread off and spread on at -0.5%. SRIS values are calculated for CC/SRIS spread off and spread on at -0.3%. If oscilloscope data is used, equipment noise is removed from all results.
2 Jitter measurements shall be made with a capture of at least 100,000 clock cycles captured by a real-time oscilloscope (RTO) with a sample rate of 20 GS/s or greater. Broadband oscilloscope noise must be minimized in the measurement. The measured PP jitter is used (no extrapolation) for RTO measurements. Alternately, jitter measurements may be used with a Phase Noise Analyzer (PNA) extending (flat) and integrating and folding the frequency content up to an offset from the carrier frequency of at least 200MHz (at 300MHz absolute frequency) below the Nyquist frequency. For PNA measurements for the 2.5 GT/s data rate, the RMS jitter is converted to peak to peak jitter using a multiplication factor of 8.83. In the case where real-time oscilloscope and PNA measurements have both been done and produce different results, the RTO result must be used.
3 SSC spurs from the fundamental and harmonics are removed up to a cutoff frequency of 2MHz taking care to minimize removal of any non-SSC content.
4 Note that 0.7ps RMS is to be used in channel simulations to account for additional noise in a real system. 5 Note that 0.25ps RMS is to be used in channel simulations to account for additional noise in a real system. 6 While the PCI Express Base Specification 5.0, Revision 1.0 provides the filters necessary to calculate SRIS jitter values, it does not provide
specification limits, hence the N/A in the "Limit" column. SRIS values are informative only. In general, a clock operating in an SRIS system must be twice as good as a clock operating in a Common Clock system. For RMS values, twice as good is equivalent to dividing the CC value by 2. An additional consideration is the value for which to divide by 2. The conservative approach is to divide the ref clock jitter limit, and the case can be made for dividing the channel simulation values by 2, if the ref clock is close to the Tx clock input. An example for Gen4 is as follows. A "rule-of-thumb" SRIS limit would be either 0.5ps RMS/2 = 0.35ps RMS, or 0.7ps RMS/2 = 0.5ps RMS. 7 Calculated for Byte1[4:3] spread settings of 01, 10 and 11. 8 Calculated for Byte1[4:3] spread settings of 01, and 10.
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9FGL02x1/04x1/06x1/08x1 Datasheet
Table 14. REF Output
Parameter
Symbol
Conditions
Minimum Typical Maximum Units Notes
Long Accuracy Clock Period High Output Voltage Low Output Voltage
Rise/Fall Slew Rate
Duty Cycle Jitter, Cycle to Cycle
Noise Floor Jitter, Phase
ppm Tperiod VHIGH VLOW
trf1
trf1
trf1
trf1 dt1X tjcyc-cyc tjdBc1k tjdBc10k
tjphREF
See Tperiod min-max values. REF output. IOH = -2mA. IOL = 2mA. Byte 3 = 1F, VOH = 0.8 � VDD, VOL = 0.2 � VDD. Byte 3 = 5F, VOH = 0.8 � VDD, VOL = 0.2 � VDD. Byte 3 = 9F, VOH = 0.8 � VDD, VOL = 0.2 � VDD. Byte 3 = DF, VOH = 0.8 � VDD, VOL = 0.2 � VDD. VT = VDD/2 V. VT = VDD/2 V. 1kHz offset. 10kHz offset to Nyquist. 12kHz to 5MHz, DIF SSC off. 12kHz to 5MHz, DIF SSC on.
0
ppm 1,2
40
ns
2
0.8 x VDDREF
V
0.2 x VDDREF
V
0.5
0.9
1.5
V/ns
1
1.0
1.5
2.5
V/ns 1,3
1.5
2.1
3.1
V/ns
1
2.0
2.7
3.8
V/ns
1
45
49.7
55
%
1,4
35
125
ps
1,4
-145
-135
dBc 1,4
-150
-140
dBc 1,4
0.13
0.3
ps (rms) 1,4
1.4
1.5
ps (rms) 1,4,5
1 Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is trimmed to 25.00MHz. 3 Default SMBus value. 4 When driven by a crystal. 5 Does not apply to the 9FGL06x1 devices.
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9FGL02x1/04x1/06x1/08x1 Datasheet
Power Management
Table 15. Power Management 3
Differential Output
CKPWRGD_PD# 0 1 1 1
SMBus OE bit X 1 1 0
OEx# Pin X 0 1 X
True O/P Low 1 Running
Disabled 1 Disabled 1
Comp. O/P Low 1 Running
Disabled 1 Disabled 1
REF Hi-Z 2 Running Running Disabled 4
1 The output state is set by B11[1:0] (Low/Low default). 2 REF is Hi-Z until the 1st assertion of CKPWRGD_PD# high. After this, when CKPWRG_PD# is low, REF is disabled unless Byte3[5] = 1, in which
case REF is running. 3 Input polarities defined at default values. 4 See SMBus description for Byte 3, bit 4.
Table 16. SMBus Address Selection
State of SADR on first application of CKPWRGD_PD#
SADR 0 1
Address 1101000 1101010
+ Read/Write Bit X X
Test Loads
Figure 5. Single-ended Output Test Load
L
DUT
REFCLK
Zo
Rs
Test Point
CL
Table 17. Terminations for Single-ended Output
Clock Source N/A
Device Under Test (DUT) 9FGL0nxx
Rs () 33
Zo () 50
L (cm) 12.7
CL (pF) 4.7
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Figure 6. Test Load for AC/DC Measurements
CK+ DUT
CK-
L Zo (differential)
CL
Test Points for High Impedance
Probe
CL
9FGL02x1/04x1/06x1/08x1 Datasheet
Table 18. Terminations for AC/DC Measurements
Clock Source N/A N/A
Device Under Test (DUT) 9FGL0x41 9FGL0x51
Rs () Internal Internal
Zo () 100 85
Figure 7. Test Setup for PCIe Clock Phase Jitter Measurements
Oscillocope (20GS/s)
L
CKIN+ CK+ DUT
Zo (differential)
Coax Cables
CKIN- CK-
0.1uF
SMA Connectors
50
50
Table 19. Terminations for PCIe Clock Phase Jitter Measurements
Clock Source N/A N/A
Device Under Test (DUT) 9FGL0x41 9FGL0x51
Rs () Internal Internal
Zo () 100 85
L (cm) 12.7 12.7
L (cm) 12.7 12.7
CL (pF) 2 2
CL (pF) N/A N/A
Alternate Terminations
The 9FGL family can easily drive LVPECL, LVDS, and CML logic. See "AN-891 Driving LVPECL, LVDS, and CML Logic with IDT's "Universal" Low-Power HCSL Outputs" for details.
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Crystal Characteristics
Table 20. Recommended Crystal Characteristics
Parameter Frequency1 Resonance Mode Frequency Tolerance @ 25�C Frequency Stability, reference at 25�C over operating temperature range Temperature Range (industrial) Temperature Range (commercial) Equivalent Series Resistance (ESR) Shunt Capacitance (CO) Load Capacitance (CL) Drive Level Aging per year
1 When driven by an external oscillator via the XIN/CLKIN_25 pin, X2 should be floating.
9FGL02x1/04x1/06x1/08x1 Datasheet
Value 25
Fundamental �20 �20
-40 to +85 0 to +70
50 7 8 0.1 �5
Units MHz -- ppm maximum ppm maximum �C �C maximum pF maximum pF maximum mW maximum ppm maximum
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9FGL02x1/04x1/06x1/08x1 Datasheet
General SMBus Serial Interface Information
How to Write Controller (host) sends a start bit Controller (host) sends the write address Renesas clock will acknowledge Controller (host) sends the beginning byte location = N Renesas clock will acknowledge Controller (host) sends the byte count = X Renesas clock will acknowledge Controller (host) starts sending Byte N through Byte N+X-1 Renesas clock will acknowledge each byte one at a time Controller (host) sends a stop bit
Index Block Write Operation
Controller (Host)
T
starT bit
Slave Address
WR
WRite
Beginning Byte = N
Data Byte Count = X
Beginning Byte N
O O O
Byte N + X - 1
P
stoP bit
X Byte
Renesas (Slave/Receiver)
ACK ACK ACK ACK
O O O ACK
Note: Address is latched on SADR pin.
How to Read Controller (host) will send a start bit Controller (host) sends the write address Renesas clock will acknowledge Controller (host) sends the beginning byte location = N Renesas clock will acknowledge Controller (host) will send a separate start bit Controller (host) sends the read address Renesas clock will acknowledge Renesas clock will send the data byte count = X Renesas clock sends Byte N+X-1 Renesas clock sends Byte 0 through Byte X (if X(H) was
written to Byte 8) Controller (host) will need to acknowledge each byte Controller (host) will send a not acknowledge bit Controller (host) will send a stop bit
Index Block Read Operation
Controller (Host)
T
starT bit
Slave Address
WR
WRite
Beginning Byte = N
RT
Repeat starT
Slave Address
RD
ReaD
Renesas
ACK ACK
ACK
ACK
ACK
O O O
N
Not acknowledge
P
stoP bit
X Byte
Data Byte Count=X
Beginning Byte N
O O O
Byte N + X - 1
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9FGL02x1/04x1/06x1/08x1 Datasheet
Table 21. Byte 0: Output Enable Register
Byte 01
Control Function
Type
0
1
9FGL08 Name
9FGL08 Default
9FGL06 Name
9FGL06 Default
9FGL04 Name
9FGL04 Default
9FGL02 Name
9FGL02 Default
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable
RW
RW
RW
RW
RW
RW
RW
RW
See B11[1:0]
OE# Pin Controls Output
OE7
OE6
OE5
OE4
OE3
OE2
OE1
OE0
1
1
1
1
1
1
1
1
OE5
OE4
Reserved
OE3
OE2
OE1
Reserved
OE0
1
1
x
1
1
1
x
1
Reserved
Reserved
Reserved
Reserved
OE3
OE2
OE1
OE0
x
x
x
x
1
1
1
1
Reserved
Reserved
Reserved
Reserved
Reserved
OE1
OE0
Reserved
x
x
x
x
x
1
1
x
1 A low on these bits will override the OE# pin and force the differential output to the state indicated by B11[1:0] (Low/Low default)
Table 22. Byte 1: Spread Spectrum with VHIGH Control Register
Byte 1
Bit7
Bit6
Bit5
Bit4
Bit3
Control Function
Type 0
1
Name Default
SS Enable SS Enable Readback Bit1 Readback Bit0
Enable software control of spread
spectrum
SS Software Control Bit1
SS Software Control Bit0
R
R
See Spread Selection table
RW
RW1
RW1
SS controlled by latch (B1[7:6])
Values in B1[4:3] control SS amount
See Spread Selection table
SSENRB1 Latch
SSENRB1 Latch
SSEN_SWCNTRL SSENSW1
0
0
SSENSW0 0
1 See notes on Spread Selection table. B1[5] must be set to a 1 in order to use B1[4:3].
Bit2 Reserved
x
Bit1
Controls Output Amplitude
RW
00 = 0.6V
Bit0
RW 10 = 0.75V
01 = 0.68V 11 = 0.85V
AMPLITUDE 1 AMPLITUDE 0
1
0
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Table 23. Byte 2: DIF Slew Selection Register
Byte 2
Control Function
Type
0
1
9FGL08 Name
9FGL08 Default
9FGL06 Name
9FGL06 Default
9FGL04 Name
9FGL04 Default
9FGL02 Name
9FGL02 Default
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Select fast or Select fast or Select fast or Select fast or Select fast or Select fast or Select fast or Select fast or slow slew rate slow slew rate slow slew rate slow slew rate slow slew rate slow slew rate slow slew rate slow slew rate
RW
RW
RW
RW
RW
RW
RW
RW
Slow Slew Rate
Fast Setting
DIF7_slew DIF6_slew DIF5_slew DIF4_slew DIF3_slew DIF2_slew DIF1_slew DIF0_slew
1
1
1
1
1
1
1
1
DIF5_slew DIF4_slew
Reserved
DIF3_slew DIF2_slew DIF1_slew
Reserved
DIF0_slew
1
1
x
1
1
1
x
1
Reserved
Reserved
Reserved
Reserved
DIF3_slew DIF2_slew
DIF1_slew
DIF0_slew
x
x
x
x
1
1
1
1
Reserved
Reserved
Reserved
Reserved
Reserved
DIF1_slew
DIF0_slew
Reserved
x
x
x
x
x
1
1
x
1 See Differential Low-Power HCSL Outputs table for slew rates.
Table 24. Byte 3: REF Slew Rate Control Register
Byte 3 Control Function Type
0
1
Name Default
Bit7
Bit6
Bit5
Bit4
Slew Rate Control
RW
RW
00 = Slowest 10 = Fast
01 = Slow 11 = Fastest
REF Slew Rate [1:0]
0
1
Wake-on-Lan Enable for REF
RW
REF disabled in Power Down
REF runs in Power Down
REF Power Down Function
0
REF Output Enable RW
Disabled1
Enabled
REF OE 1
Bit3 Reserved
x
1 The disabled state depends on Byte11[1:0]. '00' = Low, '01'= HiZ, '10' = Low, '11' = High.
Bit2 Reserved
x
Bit1 Reserved
x
Bit0 Reserved
x
Byte 4 is Reserved
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Table 25. Byte 5: Revision and Vendor ID Register
Byte 5
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Control Function
Revision ID
VENDOR ID
Type
R
R
R
R
R
R
R
R
0 C rev = 0010
1
0001 = Renesas
Name
RID3
RID2
RID1
RID0
VID3
VID2
VID1
VID0
Table 26. Byte 6: Device Type/Device ID Register
Byte 6
Bit7
Bit6
Bit5
Bit4
Control Function
Device Type
Type
R
R
R
R
0
00 = FGL 1
Name Device Type1 Device Type0 Device ID5 Device ID4
Bit3
Bit2
Device ID
R
R
9FGL08 = 0b00100 9FGL06 = 0b00110 9FGL04 = 0b00100 9FGL02 = 0b00010
Device ID3 Device ID2
Bit1 R
Device ID1
Bit0 R
Device ID0
Table 27. Byte 7: Byte Count Register
Byte 7
Control Function
Type 0 1
Name Default
Bit7 Reserved
x
Bit6 Reserved
x
Bit5 Reserved
x
Bit4
Bit3
Bit2
Bit1
Bit0
Byte Count Programming
RW
RW
RW
RW
RW
Writing to this register will configure how many bytes will be read back.
BC4
BC3
BC2
BC1
BC0
0
1
0
0
0
Bytes 8 and 9 are Reserved
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Table 28. Byte 10: PLL MN Enable, PD_Restore Register
Byte 10 Control Function Type
0 1
Name
Default
Bit7
Bit6
M/N Programming Enable
RW
Restore Default Config. In PD
RW
M/N Prog. Disabled Clear Config in PD
M/N Prog. Enabled Keep Config in PD
PLL M/N En 0
Power-Down (PD) Restore
1
Bit5 Reserved
x
Bit4 Reserved
x
Bit3 Reserved
x
Bit2 Reserved
x
Bit1 Reserved
x
Bit0 Reserved
x
Table 29. Byte 11: Stop State Control Register
Byte 11
Control Function
Type 0 1
Name Default
Bit7 Reserved
x
Bit6 Reserved
x
Bit5 Reserved
x
Bit4 Reserved
x
Bit3 Reserved
x
Bit2 Reserved
x
Bit1
Bit0
True/Complement DIF Output Disable State
RW
RW
00 = Low/Low 01 = HiZ/HiZ
10 = High/Low 11 = Low/High
STP[1] 0
STP[0] 0
Table 30. Byte 12: Impedance Control Register 1
Byte 12
Control Function
Type
0
1
9FGL08 Name
9FGL08 Default
9FGL06 Name
9FGL06 Default
9FGL04 Name
Bit7
Bit6
Output impedance control [1:0]
RW
RW
DIF3_imp[1] DIF3_imp[0]
DIF2_imp[1] DIF2_imp[0]
DIF1_imp[1] DIF1_imp[0]
Bit5
Bit4
Bit3
Bit2
Output impedance control [1:0]
RW
RW
Output impedance control [1:0]
RW
RW
00 = 33ohm DIF Zout, 01 = 85ohm DIF Zout 10 = 100ohm DIF Zout, 11 = Reserved
DIF2_imp[1] DIF2_imp[0] DIF1_imp[1] DIF1_imp[0]
9FGL0841 defaults to 0b10101010 9FGL0851 defaults to 0b01010101
DIF1_imp[1] DIF1_imp[0] Reserved
Reserved
9FGL0641 defaults to 0b1010xx10 9FGL0651 defaults to 0b0101xx01
Reserved
Reserved DIF0_imp[1] DIF0_imp[0]
Bit1
Bit0
Output impedance control [1:0]
RW
RW
DIF0_imp[1] DIF0_imp[0]
DIF0_imp[1] DIF0_imp[0]
Reserved
Reserved
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Table 30. Byte 12: Impedance Control Register 1 (Cont.)
Byte 12
9FGL04 Default
9FGL02 Name
9FGL02 Default
Bit7
Bit6
DIF0_imp[1] DIF0_imp[0]
Bit5
Bit4
Bit3
Bit2
9FGL0441 defaults to 0b10xx10xx 9FGL0451 defaults to 0b01xx01xx
Reserved
Reserved
Reserved
Reserved
9FGL0241 defaults to 0b10xxxxxx 9FGL0251 defaults to 0b01xxxxxx
Bit1 Reserved
Bit0 Reserved
Table 31. Byte 13: Impedance Control Register 2
Byte 13
Control Function
Type
0
1
9FGL08 Name
9FGL08 Default
9FGL06 Name
9FGL06 Default
9FGL04 Name
9FGL04 Default
9FGL02 Name
9FGL02 Default
Bit7
Bit6
Output impedance control [1:0]
RW
RW
DIF7_imp[1] DIF7_imp[0]
DIF5_imp[1] DIF5_imp[0]
Reserved
Reserved
Reserved
Reserved
Bit5
Bit4
Bit3
Bit2
Output impedance control [1:0]
RW
RW
Output impedance control [1:0]
RW
RW
00 = 33ohm DIF Zout, 01 = 85ohm DIF Zout 10 = 100ohm DIF Zout, 11 = Reserved
DIF6_imp[1] DIF6_imp[0] DIF5_imp[1] DIF5_imp[0]
9FGL0841 defaults to 0hAA 9FGL0851 defaults to 0h55
DIF4_imp[1] DIF4_imp[0] Reserved
Reserved
9FGL0641 defaults to 0b1010xx10 9FGL0651 defaults to 0b0101xx01
DIF3_imp[1] DIF3_imp[0] DIF2_imp[1] DIF2_imp[0]
9FGL0441 defaults to 0bxx1010xx 9FGL0451 defaults to 0bxx0101xx
Reserved
Reserved DIF1_imp[1] DIF1_imp[0]
9FGL0241 defaults to 0bxxxx10xx 9FGL0251 defaults to 0bxxxx01xx
Bit1
Bit0
Output impedance control [1:0]
RW
RW
DIF4_imp[1] DIF4_imp[0]
DIF3 Zout
DIF3 Zout
Reserved
Reserved
Reserved
Reserved
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Table 32. Byte 14: Pull-up Pull-down Control Register 1
Byte 14
Control Function
Type
0
1
9FGL08 Name
9FGL08 Default
9FGL06 Name
9FGL06 Default
9FGL04 Name
9FGL04 Default
9FGL02 Name
9FGL02 Default
Bit7
Bit6
Pull-up(pu)/ Pull-down(pd) control
RW 00 = None
10 = pu
RW 01 = pd 11 = pu+pd
Bit5
Bit4
Pull-up(pd)/ Pull-down(pd) control
RW 00 = None
10 = pu
RW 01 = pd 11 = pu+pd
Bit3
Bit2
Pull-up(pd)/ Pull-down(pd) control
RW 00 = None
10 = pu
RW 01 = pd 11 = pu+pd
Bit1
Bit0
Pull-up(pd)/ Pull-down(pd) control
RW 00 = None
10 = pu
RW 01 = pd 11 = pu+pd
OE3_pu/pd[1] OE3_pu/pd[0] OE2_pu/pd[1] OE2_pu/pd[0] OE1_pu/pd[1] OE1_pu/pd[0] OE0_pu/pd[1] OE0_pu/pd[0]
0
1
0
1
0
1
0
1
OE2_pu/pd[1] OE2_pu/pd[0] OE1_pu/pd[1] OE1_pu/pd[0] Reserved
Reserved OE0_pu/pd[1] OE0_pu/pd[0]
0
1
0
1
x
x
0
1
OE1_pu/pd[1] OE1_pu/pd[0] Reserved
Reserved OE0_pu/pd[1] OE0_pu/pd[0] Reserved
Reserved
0
1
x
x
0
1
x
x
OE0_pu/pd[1] OE0_pu/pd[0] Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0
1
x
x
x
x
x
x
Table 33. Byte 15: Pull-up Pull-down Control Register 2
Byte 15
Control Function
Type
0
1
9FGL08 Name
9FGL08 Default
9FGL06 Name
9FGL06 Default
9FGL04 Name
Bit7
Bit6
Pull-up(pd)/ Pull-down(pd) control
RW
RW
00 = None 10 = pu
01 = pd 11 = pu+pd
Bit5
Bit4
Pull-up(pd)/ Pull-down(pd) control
RW
RW
00 = None 10 = pu
01 = pd 11 = pu+pd
Bit3
Bit2
Pull-up(pd)/ Pull-down(pd) control
RW
RW
00 = None 10 = pu
01 = pd 11 = pu+pd
Bit1
Bit0
Pull-up(pd)/ Pull-down(pd) control
RW
RW
00 = None 10 = pu
01 = pd 11 = pu+pd
OE7_pu/pd[1] OE7_pu/pd0] OE6_pu/pd[1] OE6_pu/pd[0] OE5_pu/pd[1] OE5_pu/pd[0] OE4_pu/pd[1] OE4_pu/pd[0]
0
1
0
1
0
1
0
1
OE5_pu/pd[1] OE5_pu/pd[0] OE4_pu/pd[1] OE4_pu/pd[0] Reserved
Reserved OE3_pu/pd[1] OE3_pu/pd[0]
0
1
0
1
0
1
0
1
Reserved
Reserved OE3_pu/pd[1] OE3_pu/pd[0] OE2_pu/pd[1] OE2_pu/pd[0] Reserved
Reserved
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Table 33. Byte 15: Pull-up Pull-down Control Register 2 (Cont.)
Byte 15
9FGL04 Default
9FGL02 Name
9FGL02 Default
Bit7 0
Reserved 0
Bit6 1
Reserved 1
Bit5 0
Reserved 0
Bit4
Bit3
Bit2
1
0
1
Reserved OE1_pu/pd[1] OE1_pu/pd[0]
1
0
1
Bit1 0
Reserved 0
Bit0 1
Reserved 1
Table 34. Byte 16: Pull-up Pull-down Control Register 3
Byte 16
Control Function
Type 0 1
Bit7 Reserved
Bit6 Reserved
Bit5 Reserved
Bit4 Reserved
Name
Default
0
0
1
0
Bit3 Reserved
0
Bit2 Reserved
1
Bit1
Bit0
Pull-up(pd)/ Pull-down(pd) control
RW
RW
00 = None
01 = pd
10 = pu
11 = pu+pd
CKPWRGD_ CKPWRGD_ PD_pu/pd[1] PD_pu/pd[0]
1
0
Byte 17 is Reserved
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Table 35. Byte 18: Polarity Control Register 2
Byte 18
Control Function
Type
0
1
9FGL08 Name
9FGL08 Default
9FGL06 Name
9FGL06 Default
9FGL04 Name
9FGL04 Default
9FGL02 Name
9FGL02 Default
Bit7
Sets OE pin polarity RW
Bit6
Sets OE pin polarity RW
Bit5
Bit4
Bit3
Bit2
Sets OE pin Sets OE pin Sets OE pin Sets OE pin
polarity
polarity
polarity
polarity
RW
RW
RW
RW
Output enabled when OE pin is low
Output enabled when OE pin is high
Bit1
Sets OE pin polarity RW
Bit0
Sets OE pin polarity RW
OE7_polarity OE6_polarity OE5_polarity OE4_polarity OE3_polarity OE2_polarity OE1_polarity OE0_polarity
0
0
0
0
0
0
0
0
OE5_polarity OE4_polarity Reserved OE3_polarity OE2_polarity OE1_polarity Reserved OE0_polarity
0
0
0
0
0
0
0
0
Reserved OE3_polarity OE2_polarity Reserved OE1_polarity Reserved OE0_polarity Reserved
0
0
0
0
0
0
0
0
Reserved
Reserved OE1_polarity Reserved OE0_polarity Reserved
Reserved
Reserved
0
0
0
0
0
0
0
0
Table 36. Byte 19: Polarity Control Register 1
Byte 19
Bit7
Bit6
Bit5
Bit4
Control Function
Type
0
Reserved
Reserved
Reserved
Reserved
1
Name
Default
0
0
0
0
Bit3 Reserved
0
Bit2 Reserved
0
Bit1 Reserved
0
Bit0
Sets CKPWRGD_ PD polarity
RW
Power Down when Low
Power Down when High
CKPWRGD_ PD_polarity
0
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Package Outline Drawings
The package outline drawings are appended at the end of this document and are accessible from the link below. The package information is the most current data available.
9FGL02: www.idt.com/document/psc/nlnlg24p1-package-outline-40-x-40-mm-body-05-mm-pitch-qfn-epad-size-245-x-245-mm
9FGL04: www.idt.com/document/psc/32-vfqfpn-package-outline-drawing-50-x-50-x-090-mm-body-epad-315-x-315-mm-nlg32p1
9FGL06: www.idt.com/document/psc/ndndg40-package-outline-50-x-50-mm-bodyepad-350mm-sq-040-mm-pitch-qfn
9FGL08: www.idt.com/document/psc/48-vfqfpn-package-outline-drawing-60-x-60-x-090-mm-body-epad-42-x-42-mm-040mm-pitch-ndg48p2
Marking Diagrams
9FGL02
Line 1:"LOT" denotes the lot number. Line 2: truncated part number. Line 3: "YYWW" is the last two digits of the year and the work week the part was assembled.
9FGL04
Lines 1 and 2: truncated part number Line 3: "YYWW" is the last two digits of the year and the work week the part was assembled. Line 4: "COO" denotes country of origin. Line 5: "LOT" denotes the lot number.
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9FGL06
9FGL02x1/04x1/06x1/08x1 Datasheet
Lines 1 and 2: truncated part number Line 3: "YYWW" is the last two digits of the year and the work week the part was assembled. Line 4: "COO" denotes country of origin. Line 5: "LOT" denotes the lot number.
9FGL08
Lines 1 and 2: truncated part number Line 3: "YYWW" is the last two digits of the year and the work week the part was assembled. Line 4: "COO" denotes country of origin. Line 5: "LOT" denotes the lot number.
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Ordering Information
Table 37. Ordering Information
Number of Output
Orderable Part
Clock Outputs Impedance
Number
9FGL0241CKILF 100
9FGL0241CKILFT 2
9FGL0251CKILF 85
9FGL0251CKILFT 9FGL0441CKILF 100 9FGL0441CKILFT 4 9FGL0451CKILF 85 9FGL0451CKILFT 9FGL0641CKILF 100 9FGL0641CKILFT 6 9FGL0651CKILF 85 9FGL0651CKILFT 9FGL0841CKILF 100 9FGL0841CKILFT 8 9FGL0851CKILF 85 9FGL0851CKILFT
Package 24-VFQFPN 32-VFQFPN 40-VFQFPN 48-VFQFPN
Temperature Range
Part Number Suffix and Shipping Method
None = Trays
-40�C to +85�C "T" = Tape and Reel, Pin 1 Orientation: EIA-481C (see Table 38 for more details)
"C" is the device revision designator (will not correlate with the datasheet revision). "LF" denotes Pb-free configuration, RoHS compliant.
Table 38. Pin 1 Orientation in Tape and Reel Packaging
Part Number Suffix
Pin 1 Orientation
Illustration
Correct Pin 1 ORIENTATION
CARRIER TAPE TOPSIDE (Round Sprocket Holes)
T
Quadrant 1 (EIA-481-C)
USER DIRECTION OF FEED
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Revision History
Revision Date November 17, 2020
October 10, 2019
Description of Change
Updated DIF5# pin numbers for 9FGL06x1. Rebranded to Renesas.
Initial release.
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(Rev.1.0 Mar 2020)
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