LTC6994-6994-1-6994-2 (Rev. C)
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LTC6994-6994-1-6994-2 (Rev. C)
TimerBlox, Delay Block, Debouncer
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FEATURES n Delay Range: 1�s to 33.6 Seconds n Configured with 1 to 3 Resistors n Delay Max Error: � <2.3% for Delay > 512�s � <3.4% for Delay of 8�s to 512�s � <5.1% for Delay of 1�s to 8�s n Delay One or Both Rising/Falling Edges n 2.25V to 5.5V Single Supply Operation n 70�A Supply Current at 10�s Delay n 500�s Start-Up Time n CMOS Output Driver Sources/Sinks 20mA n �55�C to 125�C Operating Temperature Range n Available in Low Profile (1mm) SOT-23 (ThinSOTTM) and 2mm � 3mm DFN n AEC-Q100 Qualified for Automotive Applications APPLICATIONS n Noise Discriminators/Pulse Qualifiers n Delay Matching n Switch Debouncing n High Vibration, High Acceleration Environments n Portable and Battery-Powered Equipment All registered trademarks and trademarks are the property of their respective owners. LTC6994-1/LTC6994-2 TimerBlox: Delay Block/ Debouncer DESCRIPTION The LTC�6994 is a programmable delay block with a range of 1�s to 33.6 seconds. The LTC6994 is part of the TimerBlox� family of versatile silicon timing devices. A single resistor, RSET, programs an internal master oscillator frequency, setting the LTC6994's time base. The input-to-output delay is determined by this master oscil- lator and an internal clock divider, NDIV, programmable to eight settings from 1 to 221: tDELAY = NDIV � RSET 50k � 1�s, NDIV = 1, 8, 64,...,221 The output (OUT) follows the input (IN) after delaying the rising and/or falling transitions. The LTC6994-1 will delay the rising or falling edge. The LTC6994-2 will delay both transitions, and adds the option to invert the output. DEVICE DELAY FUNCTION LTC6994-1 or LTC6994-2 or The LTC6994 also offers the ability to dynamically adjust the delay time via a separate control voltage. For easy configuration of the LTC6994, use the TimerBlox LTC6994: Delay Web-Based Design Tool. TYPICAL APPLICATION Noise Discriminator NOISY INPUT IN OUT LTC6994-2 GND V+ QUALIFIED OUTPUT 3.3V 0.1�F SET RSET 75k DIV 699412 TA01a IN 2V/DIV OUT 2V/DIV 1.5�s 1.5�s 20�s/DIV 699412 TA01b Rev. C Document Feedback For more information www.analog.com 1 LTC6994-1/LTC6994-2 ABSOLUTE MAXIMUM RATINGS (Note 1) Supply Voltage (V+) to GND.........................................6V Maximum Voltage on Any Pin .................................. (GND � 0.3V) VPIN (V+ + 0.3V) Operating Temperature Range (Note 2) LTC6994C.............................................�40�C to 85�C LTC6994I..............................................�40�C to 85�C LTC6994H........................................... �40�C to 125�C LTC6994MP........................................ �55�C to 125�C Specified Temperature Range (Note 3) LTC6994C................................................. 0�C to 70�C LTC6994I..............................................�40�C to 85�C LTC6994H........................................... �40�C to 125�C LTC6994MP........................................ �55�C to 125�C Junction Temperature............................................ 150�C Storage Temperature Range................... �65�C to 150�C Lead Temperature (Soldering, 10 sec) S6 Package........................................................ 300�C PIN CONFIGURATION V+ 1 DIV 2 SET 3 TOP VIEW 7 6 OUT 5 GND 4 IN DCB PACKAGE 6-LEAD (2mm � 3mm) PLASTIC DFN TJMAX = 150�C, JA = 64�C/W, JC = 10.6�C/W EXPOSED PAD (PIN 7) CONNECTED TO GND, PCB CONNECTION OPTIONAL TOP VIEW IN 1 GND 2 SET 3 6 OUT 5 V+ 4 DIV S6 PACKAGE 6-LEAD PLASTIC TSOT-23 TJMAX = 150�C, JA = 192�C/W, JC = 51�C/W ORDER INFORMATION Lead Free Finish TAPE AND REEL (MINI) TAPE AND REEL PART MARKING LTC6994CDCB-1#TRMPBF LTC6994CDCB-1#TRPBF LFCT LTC6994IDCB-1#TRMPBF LTC6994IDCB-1#TRPBF LFCT LTC6994HDCB-1#TRMPBF LTC6994HDCB-1#TRPBF LFCT LTC6994CS6-1#TRMPBF LTC6994CS6-1#TRPBF LTFCV LTC6994IS6-1#TRMPBF LTC6994IS6-1#TRPBF LTFCV LTC6994HS6-1#TRMPBF LTC6994HS6-1#TRPBF LTFCV LTC6994CDCB-2#TRMPBF LTC6994CDCB-2#TRPBF LFCW LTC6994IDCB-2#TRMPBF LTC6994IDCB-2#TRPBF LFCW LTC6994HDCB-2#TRMPBF LTC6994HDCB-2#TRPBF LFCW LTC6994CS6-2#TRMPBF LTC6994CS6-2#TRPBF LTFCX LTC6994IS6-2#TRMPBF LTC6994IS6-2#TRPBF LTFCX LTC6994HS6-2#TRMPBF LTC6994HS6-2#TRPBF LTFCX LTC6994MPS6-1#TRMPBF LTC6994MPS6-1#TRPBF LTFCV LTC6994MPS6-2#TRMPBF LTC6994MPS6-2#TRPBF LTFCX PACKAGE DESCRIPTION 6-Lead (2mm x 3mm) Plastic DFN 6-Lead (2mm x 3mm) Plastic DFN 6-Lead (2mm x 3mm) Plastic DFN 6-Lead Plastic TSOT-23 6-Lead Plastic TSOT-23 6-Lead Plastic TSOT-23 6-Lead (2mm x 3mm) Plastic DFN 6-Lead (2mm x 3mm) Plastic DFN 6-Lead (2mm x 3mm) Plastic DFN 6-Lead Plastic TSOT-23 6-Lead Plastic TSOT-23 6-Lead Plastic TSOT-23 6-Lead Plastic TSOT-23 6-Lead Plastic TSOT-23 SPECIFIED TEMPERATURE RANGE 0�C to 70�C �40�C to 85�C �40�C to 125�C 0�C to 70�C �40�C to 85�C �40�C to 125�C 0�C to 70�C �40�C to 85�C �40�C to 125�C 0�C to 70�C �40�C to 85�C �40�C to 125�C �55�C to 125�C �55�C to 125�C Rev. C 2 For more information www.analog.com LTC6994-1/LTC6994-2 ORDER INFORMATION Lead Free Finish AUTOMOTIVE PRODUCTS** TAPE AND REEL (MINI) TAPE AND REEL PART MARKING PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE LTC6994IS6-1#WTRMPBF LTC6994IS6-1#WTRPBF LTFCV 6-Lead Plastic TSOT-23 �40�C to 85�C LTC6994HS6-1#WTRMPBF LTC6994HS6-1#WTRPBF LTFCV 6-Lead Plastic TSOT-23 �40�C to 125�C LTC6994IS6-2#WTRMPBF LTC6994IS6-2#WTRPBF LTFCX 6-Lead Plastic TSOT-23 �40�C to 85�C LTC6994HS6-2#WTRMPBF LTC6994HS6-2#WTRPBF LTFCX 6-Lead Plastic TSOT-23 �40�C to 125�C Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. **Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating (teNmDIpVe=ra1tutore2r2a1n),geR,SEoTth=er5w0kisteos8p0e0cki,ficRaLtOioADns=a5rke,aCtLTOAAD= 25�C. = 5pF Test conditions are V+ = unless otherwise noted. 2.25V to 5.5V, IN = 0V, DIVCODE = 0 to 15 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS tDELAY tDELAY Delay Time Delay Accuracy (Note 4) NDIV 512 1� 33.55 sec �1.7 �2.3 % l �3.0 % 8 NDIV 64 �2.4 �3.4 % l �4.4 % NDIV = 1 �3.8 �5.1 % l �6.2 % tDELAY/T Delay Drift Over Temperature Delay Change With Supply Delay Jitter (Note 10) tS Delay Change Settling Time (Note 9) NDIV 512 NDIV 64 NDIV 512 8 NDIV 64 NDIV = 1 V+ = 4.5V to 5.5V V+ = 2.25V to 4.5V V+ = 4.5V to 5.5V V+ = 2.7V to 4.5V V+ = 2.25V to 2.7V V+ = 5.5V V+ = 2.25V NDIV = 8 NDIV = 64 NDIV = 512 NDIV = 4096 tMASTER = tDELAY/NDIV l �0.006 l �0.008 l �0.6 �0.2 l �0.4 �0.1 l �0.9 �0.2 l �0.7 �0.2 0.4 l �1.1 �0.1 0.9 1.0 0.5 0.20 0.05 0.20 0.03 6 � tMASTER %/�C %/�C % % % % % %P-P %P-P %P-P %P-P %P-P %P-P �s Rev. C For more information www.analog.com 3 LTC6994-1/LTC6994-2 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating (teNmDIpVe=ra1tutore2r2a1n),geR,SEoTth=er5w0kisteos8p0e0cki,ficRaLtOioADns=a5rke,aCtLTOAAD= 25�C. = 5pF Test conditions are V+ = unless otherwise noted. 2.25V to 5.5V, IN = 0V, DIVCODE = 0 to 15 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Power Supply V+ Operating Supply Voltage Range l 2.25 5.5 V IS(IDLE) Power-On Reset Voltage Supply Current (Idle) l RL = , RSET = 50k, NDIV 64 V+ = 5.5V l V+ = 2.25V l RL = , RSET = 50k, NDIV 512 V+ = 5.5V V+ = 2.25V l l RL = , RSET = 800k, NDIV 64 V+ = 5.5V V+ = 2.25V l l RL = , RSET = 800k, NDIV 512 V+ = 5.5V V+ = 2.25V l l 1.95 V 165 200 �A 125 160 �A 135 175 �A 105 140 �A 70 110 �A 60 95 �A 65 100 �A 55 90 �A Analog Inputs VSET VSET/T RSET VDIV VDIV/V+ Voltage at SET Pin VSET Drift Over Temperature Frequency-Setting Resistor DIV Pin Voltage DIV Pin Valid Code Range (Note 5) DIV Pin Input Current Deviation from Ideal VDIV/V+ = (DIVCODE + 0.5)/16 l 0.97 1.00 1.03 V l �75 �V/�C l 50 l 0 800 k V+ V l �1.5 % l �10 nA Digital I/O VIH VIL IOUT(MAX) VOH IN Pin Input Capacitance IN Pin Input Current High Level IN Pin Input Voltage Low Level IN Pin Input Voltage Output Current High Level Output Voltage (Note 7) IN = 0V to V+ (Note 6) (Note 6) V+ = 2.7V to 5.5V V+ = 5.5V V+ = 3.3V V+ = 2.25V VOL Low Level Output Voltage (Note 7) V+ = 5.5V V+ = 3.3V V+ = 2.25V tPD tWIDTH Propagation Delay Minimum Recognized Input Pulse Width V+ = 5.5V V+ = 3.3V V+ = 2.25V V+ = 3.3V 2.5 pF l 0.7 � V+ l �10 nA V 0.3 � V+ V �20 mA IOUT = �1mA l 5.45 5.48 V IOUT = �16mA l 4.84 5.15 V IOUT = �1mA l 3.24 3.27 V IOUT = �10mA l 2.75 2.99 V IOUT = �1mA l 2.17 2.21 V IOUT = �8mA l 1.58 1.88 V IOUT = 1mA l IOUT = 16mA l 0.02 0.04 V 0.26 0.54 V IOUT = 1mA l IOUT = 10mA l 0.03 0.05 V 0.22 0.46 V IOUT = 1mA l IOUT = 8mA l 0.03 0.07 V 0.26 0.54 V 10 ns 14 ns 24 ns 5 ns Rev. C 4 For more information www.analog.com LTC6994-1/LTC6994-2 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating (teNmDIpVe=ra1tutore2r2a1n),geR,SEoTth=er5w0kisteos8p0e0cki,ficRaLtOioADns=a5rke,aCtLTOAAD= 25�C. = 5pF Test conditions are V+ = unless otherwise noted. 2.25V to 5.5V, IN = 0V, DIVCODE = 0 to 15 SYMBOL tr PARAMETER Output Rise Time (Note 8) tf Output Fall Time (Note 8) CONDITIONS V+ = 5.5V V+ = 3.3V V+ = 2.25V V+ = 5.5V V+ = 3.3V V+ = 2.25V MIN TYP MAX UNITS 1.1 ns 1.7 ns 2.7 ns 1.0 ns 1.6 ns 2.4 ns Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC6994C is guaranteed functional over the operating temperature range of �40�C to 85�C. Note 3: The LTC6994C is guaranteed to meet specified performance from 0�C to 70�C. The LTC6994C is designed, characterized and expected to meet specified performance from �40�C to 85�C but it is not tested or QA sampled at these temperatures. The LTC6994I is guaranteed to meet specified performance from �40�C to 85�C. The LTC6994H is guaranteed to meet specified performance from �40�C to 125�C. The LTC6994MP is guaranteed to meet specified performance from �55�C to 125�C. Note 4: Delay accuracy is defined as the deviation from the tDELAY equation, assuming RSET is used to program the delay. Note 5: See Operation section, Table 1 and Figure 2 for a full explanation of how the DIV pin voltage selects the value of DIVCODE. Note 6: The IN pin has hysteresis to accommodate slow rising or falling signals. The threshold voltages are proportional to V+. Typical values can be estimated at any supply voltage using: VIN(RISING) 0.55 � V+ + 185mV and VIN(FALLING) 0.48 � V+ � 155mV Note 7: To conform to the Logic IC Standard, current out of a pin is arbitrarily given a negative value. Note 8: Output rise and fall times are measured between the 10% and the 90% power supply levels with 5pF output load. These specifications are based on characterization. Note 9: Settling time is the amount of time required for the output to settle within �1% of the final delay after a 0.5� or 2� change in ISET. Note 10: Jitter is the ratio of the deviation of the programmed delay to the mean of the delay. This specification is based on characterization and is not 100% tested. Rev. C For more information www.analog.com 5 DRIFT (%) DRIFT (%) DRIFT (%) DRIFT (%) DRIFT (%) DRIFT (%) DRIFT (%) DRIFT (%) DRIFT (%) LTC6994-1/LTC6994-2 TYPICAL PERFORMANCE CHARACTERISTICS V+ = 3.3V, RSET = 200k and TA = 25�C unless otherwise noted. Delay Drift vs Temperature (NDIV 64) 1.5 RSET = 50k 3 PARTS 1.0 Delay Drift vs Temperature (NDIV 64) 1.5 RSET = 200k 3 PARTS 1.0 0.5 0.5 0 0 �0.5 �0.5 �1.0 �1.0 �1.5 �50 �25 0 25 50 75 TEMPERATURE (�C) 100 125 699412 G01 Delay Drift vs Temperature (NDIV 512) 1.5 RSET = 50k 3 PARTS 1.0 �1.5 �50 �25 0 25 50 75 TEMPERATURE (�C) 100 125 699412 G02 Delay Drift vs Temperature (NDIV 512) 1.5 RSET = 200k 3 PARTS 1.0 0.5 0.5 0 0 �0.5 �0.5 �1.0 �1.0 �1.5 �50 �25 0 25 50 75 TEMPERATURE (�C) 100 125 699412 G04 Delay Drift vs Supply Voltage (NDIV = 1) 1.0 RISING EDGE DELAY 0.8 REFERENCED TO V+ = 4V 0.6 0.4 0.2 0 �0.2 �0.4 �0.6 RSET = 50k �0.8 RSET = 200k RSET = 800k �1.0 2 3 4 5 6 SUPPLY (V) 699412 G07 �1.5 �50 �25 0 25 50 75 TEMPERATURE (�C) 100 125 699412 G05 Delay Drift vs Supply Voltage (NDIV = 1) 1.0 FALLING EDGE DELAY 0.8 REFERENCED TO V+ = 4V 0.6 0.4 0.2 0 �0.2 �0.4 �0.6 RSET = 50k �0.8 RSET = 200k RSET = 800k �1.0 2 3 4 5 6 SUPPLY (V) 699412 G08 6 For more information www.analog.com Delay Drift vs Temperature (NDIV 64) 1.5 RSET = 800k 3 PARTS 1.0 0.5 0 �0.5 �1.0 �1.5 �50 �25 0 25 50 75 TEMPERATURE (�C) 100 125 699412 G03 Delay Drift vs Temperature (NDIV 512) 1.5 RSET = 800k 3 PARTS 1.0 0.5 0 �0.5 �1.0 �1.5 �50 �25 0 25 50 75 TEMPERATURE (�C) 100 125 699412 G06 Delay Drift vs Supply Voltage (NDIV > 1) 1.0 REFERENCED TO V+ = 4V 0.8 0.6 0.4 0.2 0 �0.2 �0.4 �0.6 RSET = 50k, NDIV = 8 �0.8 RSET = 50k TO 800k, NDIV 512 RSET = 800k, NDIV = 8 �1.0 2 3 4 5 6 SUPPLY (V) 699412 G09 Rev. C LTC6994-1/LTC6994-2 ERROR (%) ERROR (%) ERROR (%) TYPICAL PERFORMANCE CHARACTERISTICS V+ = 3.3V, RSET = 200k and TA = 25�C unless otherwise noted. Delay Error vs RSET (NDIV = 1) 5 RISING EDGE DELAY 4 3 PARTS 3 2 1 0 �1 �2 �3 �4 �5 50 100 200 400 RSET (k) 800 699412 G10 Delay Error vs RSET (8 NDIV 64) 5 3 PARTS 4 3 2 1 0 �1 �2 �3 �4 �5 50 100 200 400 RSET (k) 800 699412 G11 Delay Error vs RSET (NDIV 512) 5 3 PARTS 4 3 2 1 0 �1 �2 �3 �4 �5 50 100 200 400 RSET (k) 800 699412 G12 ERROR (%) ERROR (%) ERROR (%) Delay Error vs RSET (NDIV =1) 5 FALLING EDGE DELAY 4 3 PARTS 3 2 1 0 �1 �2 �3 �4 �5 50 100 200 400 RSET (k) 800 699412 G13 VSET Drift vs ISET 1.0 0.8 0.6 0.4 0.2 0 �0.2 �0.4 �0.6 �0.8 �1.0 0 REFERENCED TO ISET = 10�A 5 10 15 20 ISET (�A) 699412 G16 Delay Error vs DIVCODE 5 LTC6994-1 4 RSET = 50k 3 3 PARTS 2 1 0 �1 �2 RISING EDGE �3 DELAY �4 FALLING EDGE DELAY �5 0 2 4 6 8 10 12 14 DIVCODE 699412 G14 VSET Drift vs Supply Voltage 1.0 0.8 0.6 0.4 0.2 0 �0.2 �0.4 �0.6 �0.8 �1.0 2 REFERENCED TO V+ = 4V 3 4 5 6 SUPPLY (V) 699412 G17 For more information www.analog.com Delay Error vs DIVCODE 5 LTC6994-1 4 RSET = 800k 3 3 PARTS 2 1 0 �1 �2 RISING EDGE �3 DELAY FALLING EDGE DELAY �4 �5 0 2 4 6 8 10 12 14 DIVCODE 699412 G15 VSET vs Temperature 1.020 3 PARTS 1.015 1.010 1.005 1.000 0.995 0.990 0.985 0.980 �50 �25 0 25 50 75 TEMPERATURE (�C) 100 125 699412 G18 Rev. C 7 VSET (mV) DRIFT (mV) VSET (V) LTC6994-1/LTC6994-2 TYPICAL PERFORMANCE CHARACTERISTICS V+ = 3.3V, RSET = 200k and TA = 25�C unless otherwise noted. NUMBER OF UNITS Typical VSET Distribution 250 2 LOTS DFN AND SOT-23 200 1274 UNITS 150 100 50 0 0.98 0.988 0.996 1.004 VSET (V) 1.012 1.02 699412 G19 POWER SUPPLY CURRENT (�A) Supply Current vs Supply Voltage 300 LTC6994-1 IS(ACTIVE) MEASURED 250 WITH fIN = 1/(2 � tDELAY) RSET = 50k, �1, ACTIVE 200 RSET = 50k, �1, IDLE 150 RSET = 100k, �8, ACTIVE 100 RSET = 100k, �8, IDLE 50 CLOAD = 5pF RLOAD = 0 2 3 RSET = 800k, �512 4 5 6 SUPPLY VOLTAGE (V) 699412 G20 POWER SUPPLY CURRENT (�A) Supply Current vs Temperature 250 LTC6994-1 IS(ACTIVE) MEASURED 200 WITH fIN = 1/(2 � tDELAY) RSET = 50k, �1, ACTIVE 150 RSET = 50k, �1, IDLE RSET = 100k, �8, ACTIVE 100 RSET = 100k, �8, IDLE 50 RSET = 800k, �512 CLOAD = 5pF RLOAD = 0 �50 �25 0 25 50 75 TEMPERATURE (�C) 100 125 699412 G21 POWER SUPPLY CURRENT (�A) Supply Current vs IN Pin Voltage 250 200 5V IN FALLING 150 3.3V IN FALLING 100 5V IN RISING 3.3V IN RISING 50 CLOAD = 5pF RLOAD = 0 0 0.2 0.4 0.6 VIN/V+ (V/V) 0.8 1.0 699412 G22 IN Threshold Voltage vs Supply Voltage 3.5 3.0 POSITIVE GOING 2.5 2.0 NEGATIVE GOING 1.5 1.0 0.5 0 2 3 4 5 6 SUPPLY VOLTAGE (V) 699412 G25 IN PIN VOLTAGE (V) 8 JITTER (%P-P) POWER SUPPLY CURRENT (�A) Supply Current vs tDELAY (5V) 250 ACTIVE CURRENT MEASURED USING LTC6994-1 WITH 200 fIN = 1/(2 � tDELAY) �1 �8 150 100 50 V+ = 5V CLOAD = 5pF RLOAD = 0 0.001 0.01 0.1 1 tDELAY (ms) ACTIVE IDLE 10 100 699412 G23 POWER SUPPLY CURRENT (�A) Supply Current vs tDELAY (2.5V) 250 ACTIVE CURRENT MEASURED USING LTC6994-1 WITH 200 fIN = 1/(2 � tDELAY) 150 �1 �8 100 50 V+ = 2.5V CLOAD = 5pF RLOAD = 0 0.001 0.01 0.1 1 tDELAY (ms) ACTIVE IDLE 10 100 699412 G24 Peak-to-Peak Jitter vs tDELAY 1.2 PEAK-TO-PEAK �1, 5.5V 1.0 tDELAY VARIATION MEASURED OVER 30s INTERVALS 0.8 0.6 �1, 2.25V 0.4 0.2 0 0.001 �8, 5.5V �512 �8, 2.25V �64 0.01 0.1 1 tDELAY (ms) �4096 10 100 699412 G26 ISET (�A) Typical ISET Current Limit vs V+ 1000 SET PIN SHORTED TO GND 800 600 400 200 0 2 3 4 5 6 SUPPLY VOLTAGE (V) 699412 G27 Rev. C For more information www.analog.com LTC6994-1/LTC6994-2 PROPAGATION DELAY (ns) RISE/FALL TIME (ns) OUTPUT RESISTANCE () TYPICAL PERFORMANCE CHARACTERISTICS V+ = 3.3V, RSET = 200k and TA = 25�C unless otherwise noted. Input Propagation Delay (tPD) vs Supply Voltage 25 CLOAD = 5pF Rise and Fall Time vs Supply Voltage 3.0 CLOAD = 5pF 20 2.5 2.0 15 tRISE 1.5 10 tFALL 1.0 5 0.5 0 2 3 4 5 6 SUPPLY VOLTAGE (V) 699412 G28 0 2 3 4 5 6 SUPPLY VOLTAGE (V) 699412 G29 Output Resistance vs Supply Voltage 50 45 40 35 OUTPUT SOURCING CURRENT 30 25 20 15 OUTPUT SINKING CURRENT 10 5 0 2 3 4 5 6 SUPPLY VOLTAGE (V) 699412 G30 Start-Up, RSET = 800k (LTC6994-1) Start-Up, RSET = 50k (LTC6994-2, POL = 1) V+ 2V/DIV IN 2V/DIV OUT 2V/DIV V+ = 2.5V 7.2ms 1ms/DIV 699412 G31 V+ 2V/DIV IN 2V/DIV OUT 2V/DIV V+ = 2.5V 500�s 100�s/DIV 699412 G32 Rev. C For more information www.analog.com 9 LTC6994-1/LTC6994-2 PIN FUNCTIONS (DCB/S6) V+ (Pin 1/Pin 5): Supply Voltage (2.25V to 5.5V). This supply should be kept free from noise and ripple. It should be bypassed directly to the GND pin with a 0.1�F capacitor. DIV (Pin 2/Pin 4): Programmable Divider and Polarity Input. The DIV pin voltage (VDIV) is internally converted into a 4-bit result (DIVCODE). VDIV may be generated by a resistor divider between V+ and GND. Use 1% resistors to ensure an accurate result. The DIV pin and resistors should be shielded from the OUT pin or any other traces that have fast edges. Limit the capacitance on the DIV pin to less than 100pF so that VDIV settles quickly. The MSB of DIVCODE (POL) selects the delay functionality. For the LTC6994-1, POL = 0 will delay the rising transition and POL = 1 will delay the falling transition. For the LTC69942, both transitions are delayed so POL = 1 can be used to invert the output. SET (Pin 3/Pin 3): Delay Setting Input. The voltage on the SET pin (VSET) is regulated to 1V above GND. The amount of current sourced from the SET pin (ISET) programs the master oscillator frequency. The ISET current range is 1.25�A to 20�A. The delayed output transition will be not occur if ISET drops below approximately 500nA. Once ISET increases above 500nA the delayed edge will transition. A resistor connected between SET and GND is the most accurate way to set the delay. For best performance, use a precision metal or thin film resistor of 0.5% or better tolerance and 50ppm/�C or better temperature coefficient. For lower accuracy applications an inexpensive 1% thick film resistor may be used. Limit the capacitance on the SET pin to less than 10pF to minimize jitter and ensure stability. Capacitance less than 100pF maintains the stability of the feedback circuit regulating the VSET voltage. IN (Pin 4/Pin 1): Logic Input. Depending on the version and POL bit setting, rising or falling edges on IN will propagate to OUT after a programmable delay. The LTC6994-1 will delay only the rising or falling edge. The LTC6994-2 will delay both edges. GND (Pin 5/Pin 2): Ground. Tie to a low inductance ground plane for best performance. OUT (Pin 6/Pin 6): Output. The OUT pin swings from GND to V+ with an output resistance of approximately 30. When driving an LED or other low impedance load a series output resistor should be used to limit source/ sink current to 20mA. V+ IN OUT LTC6994 GND V+ SET RSET DIV 699412 PF V+ C1 0.1�F R1 R2 Rev. C 10 For more information www.analog.com BLOCK DIAGRAM (S6 package pin numbers shown) LTC6994-1/LTC6994-2 5 V+ R1 POL 4 DIV 4-BIT A/D CONVERTER DIGITAL FILTER R2 IN 1 INPUT BUFFER MASTER OSCILLATOR tMASTER = 1�s 50k � VSET ISET MCLK PROGRAMMABLE DIVIDER �1, 8, 64, 512, 4096, 215, 218, 221 EDGECONTROLLED DELAY LOGIC OUTPUT OUT POLARITY 6 (LTC6994-2) HALT OSCILLATOR POR IF ISET < 500nA ISET +� � + VSET = 1V SET 3 ISET RSET 1V GND 2 699412 BD For more information www.analog.com Rev. C 11 LTC6994-1/LTC6994-2 OPERATION The LTC6994 is built around a master oscillator with a 1�s minimum period. The oscillator is controlled by the SET pin current (ISET) and voltage (VSET), with a 1�s/50k conversion factor that is accurate to �1.7% under typical conditions. tMASTER = 1�s 50k � VSET ISET A feedback loop maintains VSET at 1V �30mV, leaving ISET as the primary means of controlling the input-to-output delay. The simplest way to generate ISET is to connect a resistor (RSET) between SET and GND, such that ISET = VSET/RSET. The master oscillator equation reduces to: tMASTER = 1�s � R SET 50k From this equation, it is clear that VSET drift will not affect the input-to-output delay when using a single program resistor (RSET). Error sources are limited to RSET tolerance and the inherent accuracy tDELAY of the LTC6994. RSET may range from 50k to 800k (equivalent to ISET between 1.25�A and 20�A). When the input makes a transition that will be delayed (as determined by the part version and POL bit setting), the master oscillator is enabled to time the delay. When the desired duration is reached, the output is allowed to transition. The LTC6994 also includes a programmable frequency divider which can further divide the frequency by 1, 8, 64, 512, 4096, 215, 218 or 221. This extends the delay duration by those same factors. The divider ratio NDIV is set by a resistor divider attached to the DIV pin. tDELAY = NDIV 50k � VSET ISET � 1�s With RSET in place of VSET/ISET the equation reduces to: tDELAY = NDIV � RSET 50k � 1�s DIVCODE The DIV pin connects to an internal, V+ referenced 4-bit A/D converter that determines the DIVCODE value. DIVCODE programs two settings on the LTC6994: 1. DIVCODE determines the frequency divider setting, NDIV. 2. The DIVCODE MSB is the POL bit, and configures a different polarity setting on the two versions. a. LTC6994-1: POL selects rising or falling-edge delays. POL = 0 will delay rising-edge transitions. POL = 1 will delay falling-edge transitions. b. LTC6994-2: POL selects the output inversion. POL = 1 inverts the output signal. VDIV may be generated by a resistor divider between V+ and GND as shown in Figure 1. 2.25V TO 5.5V V+ LTC6994 R1 DIV R2 GND 699412 F01 Figure 1. Simple Technique for Setting DIVCODE Table 1 offers recommended 1% resistor values that accurately produce the correct voltage division as well as the corresponding NDIV and POL values for the recommended resistor pairs. Other values may be used as long as: 1. The VDIV/V+ ratio is accurate to �1.5% (including resistor tolerances and temperature effects) 2. The driving impedance (R1||R2) does not exceed 500k. Rev. C 12 For more information www.analog.com LTC6994-1/LTC6994-2 OPERATION If the voltage is generated by other means (i.e., the output of a DAC) it must track the V+ supply voltage. The last column in Table 1 shows the ideal ratio of VDIV to the supply voltage, which can also be calculated as: VDIV V+ = DIVCODE + 0.5 16 � 1.5% For example, if the supply is 3.3V and the desired DIVCODE is 4, VDIV = 0.281 � 3.3V = 928mV � 50mV. Figure 2 illustrates the information in Table 1, showing that NDIV is symmetric around the DIVCODE midpoint. Table 1. DIVCODE Programming DIVCODE POL NDIV 0 0 1 1 0 8 2 0 64 3 0 512 4 0 4,096 5 0 32,768 6 0 262,144 7 0 2,097,152 8 1 2,097,152 9 1 262,144 10 1 32,768 11 1 4,096 12 1 512 13 1 64 14 1 8 15 1 1 Recommended tDELAY 1�s to 16�s 8�s to 128�s 64�s to 1.024ms 512�s to 8.192ms 4.096ms to 65.54ms 32.77ms to 524.3ms 262.1ms to 4.194sec 2.097sec to 33.55sec 2.097sec to 33.55sec 262.1ms to 4.194sec 32.77ms to 524.3ms 4.096ms to 65.54ms 512�s to 8.192ms 64�s to 1.024ms 8�s to 128�s 1�s to 16�s R1 (k) Open 976 976 1000 1000 1000 1000 1000 887 681 523 392 280 182 102 Short R2 (k) Short 102 182 280 392 523 681 887 1000 1000 1000 1000 1000 976 976 Open VDIV/V+ 0.03125 �0.015 0.09375 �0.015 0.15625 �0.015 0.21875 �0.015 0.28125 �0.015 0.34375 �0.015 0.40625 �0.015 0.46875 �0.015 0.53125 �0.015 0.59375 �0.015 0.65625 �0.015 0.71875 �0.015 0.78125 �0.015 0.84375 �0.015 0.90625 �0.015 0.96875 �0.015 tDELAY (ms) 10000 1000 100 10 1 0.1 0.01 0 0.001 0V POL BIT = 0 78 POL BIT = 1 6 9 5 10 4 11 3 12 2 13 1 14 0.5� V+ INCREASING VDIV 15 V+ 699412 F02 Figure 2. Delay Range and POL Bit vs DIVCODE For more information www.analog.com Rev. C 13 LTC6994-1/LTC6994-2 OPERATION Edge-Controlled Delay The LTC6994 is a programmable delay or pulse qualifier. It can perform noise filtering, which distinguishes it from a delay line (which simply delays all input transitions). When the voltage on the LTC6994 input pin (IN) transitions low or high, the LTC6994 can delay the corresponding output transition by any time from 1�s to 33.6 seconds. LTC6994-1 Functionality Figures 3 details the basic operation of the LTC6994-1 when configured to delay rising edge transitions (POL=0). A rising edge on the IN pin initiates the timing. OUT remains low for the duration of tDELAY. If IN stays high then OUT will transition high after this time. If the input doesn't remain high long enough for OUT to transition high then the timing will restart on each successive rising edge. In this way, the LTC6994-1 can serve as a pulse qualifier, filtering out noisy or short signals. On a falling edge at the input, the output will follow immediately (after a short propagation delay tPD).Note that the output pulse width may be extremely short if IN falls immediately after OUT rises. Figure 4 details the operation of the LTC6994-1 when configured to delay falling edges (POL = 1). IN tPD OUT tDELAY tWIDTH tPD tPD tPD tPD tDELAY tDELAY tPD 699412 F03 Figure 3. Rising-Edge Delayed Timing Diagram (LTC6994-1, POL = 0) IN tPD OUT tDELAY tPD tPD tPD tDELAY tWIDTH tPD tDELAY tPD 699412 F04 Figure 4. Falling-Edge Delayed Timing Diagram (LTC6994-1, POL = 1) Rev. C 14 For more information www.analog.com LTC6994-1/LTC6994-2 OPERATION LTC6994-2 Functionality Figures 5 details the basic operation of the LTC6994-2 when configured for noninverting operation (POL = 0). As before, a rising edge on the IN pin initiates the timing and, if IN remains high, OUT will transition high after tDELAY. Unlike the LTC6994-1, falling edges are delayed in the same way. When IN transitions low, OUT will follow after tDELAY. If the input doesn't remain high or low long enough for OUT to follow, the timing will restart on the next transition. Also unlike the LTC6994-1, the output pulse width can never be less than tDELAY. Therefore, the LTC6994-2 can generate pulses with a defined minimum width. Figure 6 details the operation of the LTC6994-2 when the output is inverted (POL = 1). IN tPD OUT tDELAY tPD tDELAY tPD tPD tDELAY tWIDTH tPD tDELAY 699412 F05 Figure 5. Both Edges Delayed Timing Diagram (LTC6994-2, POL = 0) tWIDTH IN tPD tPD tPD tPD tPD OUT 699412 F06 tDELAY tDELAY tDELAY tDELAY Figure 6. Both Edges Delayed (Inverting) Timing Diagram (LTC6994-2, POL = 1) For more information www.analog.com Rev. C 15 LTC6994-1/LTC6994-2 OPERATION Changing DIVCODE After Start-Up Following start-up, the A/D converter will continue monitoring VDIV for changes. Changes to DIVCODE will be recognized slowly, as the LTC6994 places a priority on eliminating any "wandering" in the DIVCODE. The typical delay depends on the difference between the old and new DIVCODE settings and is proportional to the master oscillator period. tDIVCODE = 16 � (DIVCODE + 6) � tMASTER A change in DIVCODE will not be recognized until it is stable, and will not pass through intermediate codes. A digital filter is used to guarantee the DIVCODE has settled to a new value before making changes to the output. However, if the delay timing is active during the transition, the actual delay can take on a value between the two settings. DIV 500mV/DIV IN 2V/DIV 4�s OUT 2V/DIV 512�s 256�s LTC6994-1 V+ = 3.3V RSET = 200k 500�s/DIV 699412 F07a Figure 7a. DIVCODE Change from 0 to 2 DIV 500mV/DIV 512�s IN 2V/DIV 256�s 4�s OUT 2V/DIV LTC6994-1 V+ = 3.3V RSET = 200k 500�s/DIV 699412 F07b Figure 7b. DIVCODE Change from 2 to 0 Start-Up Time When power is first applied, the power-on reset (POR) circuit will initiate the start-up time, tSTART. The OUT pin is held low during this time and the IN pin has no control over the output. The typical value for tSTART ranges from 0.5ms to 8ms depending on the master oscillator frequency (independent of NDIV): tSTART(TYP) = 500 � tMASTER During start-up, the DIV pin A/D converter must determine the correct DIVCODE before the LTC6994 can respond to an input. The start-up time may increase if the supply or DIV pin voltages are not stable. For this reason, it is recommended to minimize the capacitance on the DIV pin so it will properly track V+. Less than 100pF will not extend the start-up time. At the end of tSTART the DIVCODE and IN pin settings are recognized, and the state of the IN pin is transferred to the output (without additional delay). If IN is high at the end of tSTART, OUT will go high. Otherwise OUT will remain low. The LTC6994-2 with POL = 1 is the exception because it inverts the signal. At this point, the LTC6994 is ready to respond to rising/falling edges on the input. V+ IN tSTART (IN IGNORED) tPD IF IN = 1 AT END OF tSTART* OUT IF IN = 0 AT END OF tSTART* *LTC6994-2 WITH POL = 1 INVERTS THE OUTPUT 699412 F08 Figure 8. Start-Up Timing Diagram Rev. C 16 For more information www.analog.com LTC6994-1/LTC6994-2 APPLICATIONS INFORMATION Basic Operation The simplest and most accurate method to program the LTC6994 is to use a single resistor, RSET, between the SET and GND pins. The design procedure is a 3-step process. Alternatively, Linear Technology offers the easy-to-use TimerBlox Designer tool to quickly design any LTC6994 based circuit. Use the free TimerBlox LTC6994: Delay Web-Based Design Tool. Step 1: Select the LTC6994 Version and POL Bit Setting. Choose LTC6994-1 to delay one (rising or falling) input transition. The POL bit then defines which edge is to be delayed. POL = 0 delays rising edges. POL = 1 delays falling edges. Choose LTC6994-2 to delay rising and falling edges. Set POL = 0 for normal operation, or POL = 1 to invert the output. Step 2: Select the NDIV Frequency Divider Value. Select the standard resistor value closest to the calculated value. Example: Design a circuit to delay falling edges by tDELAY = 100�s with minimum power consumption. Step 1: Select the LTC6994 Version and POL Bit Setting. To delay negative transitions, choose the LTC6994-1 with POL = 1. Step 2: Select the NDIV Frequency Divider Value. Choose an NDIV value that meets the requirements of Equation (1), using tDELAY = 100�s: 6.25 NDIV 100 Potential settings for NDIV include 8 and 64. NDIV = 8 is the best choice, as it minimizes supply current by using a large RSET resistor. POL = 1 and NDIV = 8 requires DIVCODE = 14. Using Table 1, choose R1 = 102k and R2 = 976k values to program DIVCODE = 14. As explained earlier, the voltage on the DIV pin sets the DIVCODE which determines both the POL bit and the NDIV value. For a given delay time (tDELAY), NDIV should be selected to be within the following range: tDELAY 16�s NDIV tDELAY 1�s (1) To minimize supply current, choose the lowest NDIV value. However, in some cases a higher value for NDIV will provide better accuracy (see Electrical Characteristics). Table 1 can also be used to select the appropriate NDIV values for the desired tDELAY. With POL already chosen, this completes the selection of DIVCODE. Use Table 1 to select the proper resistor divider or VDIV/V+ ratio to apply to the DIV pin. Step 3: Calculate and Select RSET. The final step is to calculate the correct value for RSET using the following equation: Step 3: Select RSET. Calculate the correct value for RSET using Equation (2). RSET = 50k 1�s � 100�s 8 = 625k Since 625k is not available as a standard 1% resistor, substitute 619k if a �0.97% shift in tDELAY is acceptable. Otherwise, select a parallel or series pair of resistors such as 309k and 316k to attain a more precise resistance. The completed design is shown in Figure 9. IN OUT LTC6994-1 GND V+ SET DIV RSET 625k 2.25V TO 5.5V 0.1�F R1 102k DIVCODE = 14 R2 976k 699412 F09 RSET = 50k 1�s � tDELAY NDIV Figure 9. 100�s Negative-Edge Delay (2) Rev. C For more information www.analog.com 17 LTC6994-1/LTC6994-2 APPLICATIONS INFORMATION Voltage-Controlled Delay With one additional resistor, the LTC6994 output delay can be manipulated by an external voltage. As shown in Figure 10, voltage VCTRL sources/sinks a current through RMOD to vary the ISET current, which in turn modulates the delay as described in Equation (3): tDELAY = NDIV � RMOD 50k � 1+ 1�s RMOD � VCTRL (3) RSET VSET IN OUT LTC6994 GND V+ RMOD VCTRL SET DIV RSET V+ C1 0.1�F R1 R2 699412 F10 Figure 10. Voltage-Controlled Delay Digital Delay Control The control voltage can be generated by a DAC (digital-toanalog converter), resulting in a digitally-controlled delay. Many DACs allow for the use of an external reference. If such a DAC is used to provide the VCTRL voltage, the VSET dependency can be eliminated by buffering VSET and using it as the DAC's reference voltage, as shown in Figure 11. The DAC's output voltage now tracks any VSET variation and eliminates it as an error source. The SET pin cannot be tied directly to the reference input of the DAC because the current drawn by the DAC's REF input would affect the delay. ISET Extremes (Master Oscillator Frequency Extremes) When operating with ISET outside of the recommended 1.25�A to 20�A range, the master oscillator operates outside of the 62.5kHz to 1MHz range in which it is most accurate. The oscillator will still function with reduced accuracy for ISET < 1.25�A. At approximately 500nA, the oscillator will stop. Under this condition, the delay timing can still be initiated, but will not terminate until ISET increases and the master oscillator starts again. At the other extreme, it is not recommended to operate the master oscillator beyond 2MHz because the accuracy of the DIV pin ADC will suffer. 18 V+ 0.1�F 1/2 LTC6078 IN OUT LTC6994 GND V+ SET DIV V+ C1 0.1�F R1 R2 � + 0.1�F V+ 699412 F11 DIN VCC REF RMOD tDELAY = NDIV � RMOD 50k 1�s � 1+ RMOD RSET � DIN 4096 DIN = 0 TO 4095 �P CLK LTC1659 VOUT CS/LD GND RSET Figure 11. Digitally Controlled Delay For more information www.analog.com Rev. C LTC6994-1/LTC6994-2 APPLICATIONS INFORMATION Settling Time Following a 2� or 0.5� step change in ISET, the output delay takes approximately six master clock cycles (6 � tMASTER) to settle to within 1% of the final value. An example is shown in Figure 12, using the circuit in Figure 10. VCTRL 2V/DIV IN 5V/DIV OUT 5V/DIV DELAY 2�s/DIV LTC6994-1 V+ = 3.3V DIVCODE = 0 RSET = 200k RMOD = 464k tOUT = 3�s AND 6�s 20�s/DIV 699412 F12 Figure 12. Typical Settling Time Coupling Error The current sourced by the SET pin is used to bias the internal master oscillator. The LTC6994 responds to changes in ISET almost immediately, which provides excellent settling time. However, this fast response also makes the SET pin sensitive to coupling from digital signals, such as the IN input. Even an excellent layout will allow some coupling between IN and SET. Additional error is included in the specified accuracy for NDIV = 1 to account for this. Figure 13 shows that �1 supply variation is dependent on coupling from rising or falling inputs. A very poor layout can actually degrade performance further. The PCB layout should avoid routing SET next to IN (or any other fast-edge, wide-swing signal). DRIFT (%) 1.0 0.8 0.6 FALLING EDGE DELAY 0.4 0.2 0 �0.2 RISING EDGE DELAY �0.4 �0.6 �0.8 RSET = 50k NDIV = 1 �1.0 2 3 4 5 6 SUPPLY (V) 699412 F13 Figure 13. Delay Drift vs Supply Voltage For more information www.analog.com Rev. C 19 LTC6994-1/LTC6994-2 APPLICATIONS INFORMATION Power Supply Current The Electrical Characteristics table specifies the supply current while the part is idle (waiting for an input transition). IS(IDLE) varies with the programmed tDELAY and the supply voltage, as described by the equations in Table 2, valid for both the LTC6994-1 and LTC6994-2. Table 2. Approximate Idle Supply Current Equations CONDITION TYPICAL IS(IDLE) NDIV 64 ( ) V + � NDIV � 7pF + 4pF tDELAY V+ + 500k + 2.2 �ISET + 50�A NDIV 512 V+ � NDIV � tDELAY 7pF + V+ 500k + 1.8 � ISET + 50�A When an input transition starts the delay timing circuity, the instantaneous supply current increases to IS(ACTIVE). IS(ACTIVE) = IS(IDLE) + IS(ACTIVE) IS(ACTIVE) can be estimated using the equations in Table3, assuming a periodic input with frequency fIN. The equations assume the input pulse width is greater than tDELAY; otherwise, the output will not transition (and the increase in supply current will be less). Table 3. Active Increase in Supply Current CONDITION NDIV 64 NDIV 512 DEVICE LTC6994-1 LTC6994-2 Either Version TYPICAL IS(ACTIVE)* fIN � V+ � (NDIV � 5pF + 18pF + CLOAD) fIN � V+ � (NDIV � 10pF + 22pF + CLOAD) fIN � V+ � CLOAD *Ignoring resistive loads (assumes RLOAD = ) Figures 14 and 15 show how the supply current increases from IS(IDLE) as the input frequency increases. At higher NDIV settings, the increase in active current is smaller. POWER SUPPLY CURRENT (�A) POWER SUPPLY CURRENT (�A) 250 V+ = 3.3V INPUT PULSE WIDTH = 1.1 � tDELAY 200 �1, RSET = 50k 150 �8, RSET = 50k �1, RSET = 100k 100 �1, RSET = 800k 50 CLOAD = 5pF RLOAD = 0 "IDLE" 0.2 0.4 0.6 fIN � tDELAY 0.8 1.0 699412 F14 Figure 14. IS(ACTIVE) vs Input Frequency, LTC6994-1 250 V+ = 3.3V fIN < 1/(2 � tDELAY) TO ALLOW RISING AND FALLING DELAYS TO REACH THE OUTPUT 200 �1, RSET = 50k 150 �8, RSET = 50k 100 �1, RSET = 100k �1, RSET = 800k 50 CLOAD = 5pF RLOAD = 0 "IDLE" 0.1 0.2 0.3 fIN � tDELAY 0.4 0.5 699412 F15 Figure 15. IS(ACTIVE) vs Input Frequency, LTC6994-2 Rev. C 20 For more information www.analog.com LTC6994-1/LTC6994-2 APPLICATIONS INFORMATION Supply Bypassing and PCB Layout Guidelines The LTC6994 is an accurate monostable multivibrator when used in the appropriate manner. The part is simple to use and by following a few rules, the expected performance is easily achieved. Adequate supply bypassing and proper PCB layout are important to ensure this. Figure 16 shows example PCB layouts for both the SOT-23 and DCB packages using 0603 sized passive components. The layouts assume a two layer board with a ground plane layer beneath and around the LTC6994. These layouts are a guide and need not be followed exactly. 1. Connect the bypass capacitor, C1, directly to the V+ and GND pins using a low inductance path. The connection from C1 to the V+ pin is easily done directly on the top layer. For the DCB package, C1's connection to GND is also simply done on the top layer. For the SOT-23, OUT can be routed through the C1 pads to allow a good C1 GND connection. If the PCB design rules do not allow that, C1's GND connection can be accomplished through multiple vias to the ground plane. Multiple vias for both the GND pin connection to the ground plane and the C1 connection to the ground plane are recommended to minimize the inductance. Capacitor C1 should be a 0.1�F ceramic capacitor. 2. Place all passive components on the top side of the board. This minimizes trace inductance. 3. Place RSET as close as possible to the SET pin and make a direct, short connection. The SET pin is a current summing node and currents injected into this pin directly modulate the output delay. Having a short connection minimizes the exposure to signal pickup. 4. Connect RSET directly to the GND pin. Using a long path or vias to the ground plane will not have a significant affect on accuracy, but a direct, short connection is recommended and easy to apply. 5. Use a ground trace to shield the SET pin. This provides another layer of protection from radiated signals. 6. Place R1 and R2 close to the DIV pin. A direct, short connection to the DIV pin minimizes the external signal coupling. IN OUT LTC6994 GND V+ SET DIV RSET C1 0.1�F V+ R1 R2 R1 R2 V+ C1 V+ OUT DIV GND SET IN RSET IN GND SET RSET C1 V+ OUT V+ DIV R1 R2 699412 F16 DCB PACKAGE TSOT-23 PACKAGE Figure 16. Supply Bypassing and PCB Layout For more information www.analog.com Rev. C 21 LTC6994-1/LTC6994-2 TYPICAL APPLICATIONS Delayed One-Shot IN IN OUT LTC6994-1 5V GND V+ 0.1�F TRIG OUT LTC6993-1 GND V+ SET DIV 604k SET DIV 121k DELAYED PULSE OUT 5V 1M 0.1�F 392k tRISE_DELAY = 50ms tONESHOT = 10ms IN OUT DELAY 50ms SHOT 10ms DELAY SHOT 699412 TA02 Pulse Stretcher IN IN OUT LTC6994-1 GND V+ 787k SET DIV tMIN = 1ms OUT V+ 0.1�F 182k 976k OUTPUT PULSE DURATION = tPULSE_IN + 1ms IN OUT tMIN tMIN 699412 TA03 Rev. C 22 For more information www.analog.com TYPICAL APPLICATIONS V+ LTC6994-1/LTC6994-2 Switch/Relay Debouncer OR V+ IN OUT OUT LTC6994-2 CHATTER STABLE GND V+ SET DIV 154k t = 100ms 0.1�F V+ OR 1M CHATTER STABLE 523k 699412 TA04 OUTPUT GOES TO SAME FINAL LEVEL OF INPUT AFTER STABLE FOR 100ms Edge Chatter Filter IN IN OUT LTC6994-2 GND V+ SET DIV 499k 10�s OUT V+ 0.1�F INPUT MUST BE STABLE FOR AT LEAST 10�s IN OUT 10�s 10�s NORMAL 10�s NOISY EDGES 10�s 699412 TA05 For more information www.analog.com Rev. C 23 LTC6994-1/LTC6994-2 TYPICAL APPLICATIONS LOAD LOW IN LOAD HIGH Crossover Gate--Break-Before-Make Interval Timer IN OUT LTC6994-1 GND V+ FALLING DELAYED 0.1�F SET DIV 787k tDELAY = 1ms V+ 100k P TP0610 V+ 100k LOAD VLOAD V+/2 442k IN OUT LTC6994-1 GND V+ RISING DELAYED 0.1�F SET DIV 787k tDELAY = 1ms 100k N 2N7000 V+ 100k 699412 TA06 IN V+ V+ OFF OFF OFF VLOAD GND 1ms OFF INTERVAL AT EACH TRANSITION Rev. C 24 For more information www.analog.com LTC6994-1/LTC6994-2 PACKAGE DESCRIPTION DCB Package 6-Lead Plastic DFN (2mm � 3mm) (Reference LTC DWG # 05-08-1715 Rev A) 0.70 �0.05 3.55 �0.05 1.65 �0.05 (2 SIDES) 2.15 �0.05 PACKAGE OUTLINE 0.25 � 0.05 0.50 BSC 1.35 �0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 2.00 �0.10 (2 SIDES) R = 0.115 R = 0.05 TYP TYP 4 0.40 � 0.10 6 3.00 �0.10 1.65 � 0.10 (2 SIDES) (2 SIDES) PIN 1 BAR TOP MARK (SEE NOTE 6) 0.200 REF 0.75 �0.05 0.00 � 0.05 PIN 1 NOTCH R0.20 OR 0.25 � 45� CHAMFER 3 1 (DCB6) DFN 0405 0.25 � 0.05 0.50 BSC 1.35 �0.10 (2 SIDES) BOTTOM VIEW--EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (TBD) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE For more information www.analog.com Rev. C 25 LTC6994-1/LTC6994-2 PACKAGE DESCRIPTION S6 Package 6-Lead Plastic TSOT-23 (Reference LTC DWG # 05-08-1636) 0.62 0.95 MAX REF 1.22 REF 2.90 BSC (NOTE 4) 3.85 MAX 2.62 REF 1.4 MIN 2.80 BSC 1.50 � 1.75 (NOTE 4) PIN ONE ID RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR 0.20 BSC DATUM `A' 0.95 BSC 0.80 � 0.90 1.00 MAX 0.30 � 0.50 REF 0.09 � 0.20 NOTE: (NOTE 3) 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 6. JEDEC PACKAGE REFERENCE IS MO-193 1.90 BSC 0.30 � 0.45 6 PLCS (NOTE 3) 0.01 � 0.10 S6 TSOT-23 0302 REV B Rev. C 26 For more information www.analog.com LTC6994-1/LTC6994-2 REVISION HISTORY REV DATE DESCRIPTION A 7/11 Revised the Description section. Added text to Basic Operation paragraph in the Applications Information section. B 1/12 Added MP-Grade. Corrected sizing of the Typical Performance Characteristics curves G31 and G32. C 11/19 Added AEC-Q100 Qualified Note to Front Page Added W Grade Order Information PAGE NUMBER 1 16 1, 2, 4 8 1 3 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license Fisogrrmanoterdebiynfimorpmlicaattionnowr wotwhe.arwniasleougn.cdoermany patent or patent rights of Analog Devices. Rev. C 27 LTC6994-1/LTC6994-2 TYPICAL APPLICATION Press-and-Hold (0.3s to 4s) Delay Timer V+ ACTIVE HIGH IN OUT 100k LTC6994-1 GND V+ SET DIV RSET 576k OUT V+ 1M 0.1�F 681k BOUNCE tDELAY 3s IN HOLD IN V+ 100k ACTIVE LOW IN OUT LTC6994-1 GND V+ SET DIV RSET 576k tDELAY 3s BOUNCE OUT V+ 681k 0.1�F 1M HOLD OUT DELAY OUT DELAY 699412 TA07 RSET (k) = 190 � tDELAY (SECONDS) RELATED PARTS PART NUMBER LTC1799 LTC6900 LTC6906/LTC6907 LTC6930 LTC6990 LTC6991 LTC6992 LTC6993 DESCRIPTION 1MHz to 33MHz ThinSOT Silicon Oscillator 1MHz to 20MHz ThinSOT Silicon Oscillator 10kHz to 1MHz or 40kHz ThinSOT Silicon Oscillator Fixed Frequency Oscillator, 32.768kHz to 8.192MHz TimerBlox: Voltage-Controlled Silicon Oscillator TimerBlox: Resettable Low Frequency Oscillator TimerBlox: Voltage-Controlled Pulse Width Modulator (PWM) TimerBlox: Monostable Pulse Generator (One-Shot) COMMENTS Wide Frequency Range Low Power, Wide Frequency Range Micropower, ISUPPLY = 35�A at 400kHz 0.09% Accuracy, 110�s Start-Up Time, 105�A at 32kHz Fixed-Frequency or Voltage-Controlled Operation Clock Periods up to 9.5 hours Simple PWM with Wide Frequency Range Resistor-Programmable Pulse Width of 1�s to 34s 28 For more information www.analog.com Rev. C 11/19 www.analog.com ANALOG DEVICES, INC. 2010�2019