ZC706 Evaluation Board for the Zynq-7000 XC7Z045 SoC User Guide (UG954)
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ZC706 Evaluation Board for the Zynq-7000 XC7Z045 SoC User Guide (UG954)
Describes the ZC706 evaluation board for the XC7Z045 SoC which provides a hardware environment for developing and evaluating designs targeting the Zynq®-7000 XC7Z045-2FFG900C.
UG954, Zynq-7000, XC7Z045, SoC, eval board, eval bd, board, evaluation
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ZC706 Evaluation Board for the Zynq-7000 XC7Z045 SoC
User Guide
UG954 (v1.8) August 6, 2019
Notice of Disclaimer The information disclosed to you hereunder (the "Materials") is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of Xilinx's limited warranty, please refer to Xilinx's Terms of Sale which can be viewed at www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in such critical applications, please refer to Xilinx's Terms of Sale which can be viewed at www.xilinx.com/legal.htm#tos. AUTOMOTIVE APPLICATIONS DISCLAIMER AUTOMOTIVE PRODUCTS (IDENTIFIED AS "XA" IN THE PART NUMBER) ARE NOT WARRANTED FOR USE IN THE DEPLOYMENT OF AIRBAGS OR FOR USE IN APPLICATIONS THAT AFFECT CONTROL OF A VEHICLE ("SAFETY APPLICATION") UNLESS THERE IS A SAFETY CONCEPT OR REDUNDANCY FEATURE CONSISTENT WITH THE ISO 26262 AUTOMOTIVE SAFETY STANDARD ("SAFETY DESIGN"). CUSTOMER SHALL, PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE PRODUCTS, THOROUGHLY TEST SUCH SYSTEMS FOR SAFETY PURPOSES. USE OF PRODUCTS IN A SAFETY APPLICATION WITHOUT A SAFETY DESIGN IS FULLY AT THE RISK OF CUSTOMER, SUBJECT ONLY TO APPLICABLE LAWS AND REGULATIONS GOVERNING LIMITATIONS ON PRODUCT LIABILITY. � Copyright 2012�2019 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.
Revision History
The following table shows the revision history for this document.
Date
10/08/2012 11/21/2012
Version
1.0 1.1
Revision
Initial Xilinx release. Added additional user LED in ZC706 Evaluation Board Features section, Table 1-1, User I/O section, Figure 1-26, and Table 1-28. In Table 1-1, added fan sink information and updated notes for 10/100/1000 Ethernet PHY, user pushbuttons, user DIP switch, and FPGA PROG pushbutton. Added Encryption Key Backup Circuit section. Updated second paragraph in DDR3 SODIMM Memory (PL) section. Updated second paragraph in SD Card Interface section. Updated Table 1-11. Added U53 information to first paragraph in HDMI Video Output section. Added fourth bullet to Real Time Clock (RTC) section. Updated Figure 1-24. Added pin A17 to Table 1-28. Updated Figure 1-33. Replaced UCF in Appendix C. Added additional reference to Additional Resources.
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Date
04/24/2013
07/31/2013 04/28/2015 09/10/2015 03/29/2016 07/01/2018 08/06/2019
Version
1.2
1.3 1.4 1.5 1.6 1.7 1.8
Revision
Chapter 1, ZC706 Evaluation Board Features: Table 1-1 feature descriptions are now linked to their respective sections in the book. Figure 1-3, Figure 1-34, and Figure 1-35 were replaced. Table 1-2 was removed because it was a duplicate of Table 1-11. Table 1-2: Switch SW11 Configuration Option Settings was added. FMC Connector JTAG Bypass, page 35 was updated. Default lane size information below Figure 1-18 was changed. Figure 1-19 PCI Express Lane Size Select Jumper J19 was added. The names of pins 18 and 19 changed in Table 1-17. The address of I2C bus PMBUS_DATA/CLOCK changed in Table 1-25. Reference designator DS35 was added to Table 1-27. Callout numbers in the User I/O, page 59 section are now linked to Table 1-1. SW13 information was added to the section User Pushbuttons, page 61. In Table 1-33, J5 pin H22 changed to XC7Z045 (U1) pin AH26 and H23 changed to AH27. The section ZC706 Board Power System, page 74 was added. Voltage levels were changed in VADJ Voltage Control, page 81. Table 1-37 was modified and Table 1-38 was added. Appendix A, Default Switch and Jumper Settings: The SW11 selection in Table A-1 changed. Appendix F, Regulatory and Compliance Information: A link to the master answer record was added. Updated Table 1-22. Replaced the master User Constraints File (UCF) list in Appendix C, Xilinx Constraints File with the master Xilinx Design Constraints (XDC) list. Updated references throughout the document. Updated "LMZ22000 Family Regulator Description" to LMZ31500 and LMZ31700 Family Regulator Description. Updated Table 1-4, Table 1-7, Table 1-13, Table 1-23, Table 1-28 through Table 1-30, Table 1-32 through Table 1-34, Table 1-36, and Table A-2. Added Figure A-1. Updated Appendix C, Xilinx Constraints File. Updated J48 header jumper setting (third row in Table 1-7). Updated value of C6 in Figure 1-33 from 270 pF to 5600 pF.
Editorial updates only. No technical content updates. Updated Figure 1-27 from VADJ to VCC1V5_PL. Appendix F, Regulatory and Compliance Information: An updated link to the master answer record was added.
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Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Chapter 1: ZC706 Evaluation Board Features
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
ZC706 Evaluation Board Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Discharge Caution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Feature Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Zynq-7000 XC7Z045 SoC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Device Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Encryption Key Backup Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 I/O Voltage Rails . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
DDR3 SODIMM Memory (PL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 DDR3 Component Memory (PS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Quad-SPI Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 USB 2.0 ULPI Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 SD Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Programmable Logic JTAG Programming Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Programmable Logic JTAG Select Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 FMC Connector JTAG Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 System Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Programmable User Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 User SMA Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Processing System Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 GTX SMA Clock (SMA_MGT_REFCLK_P and SMA_MGT_REFCLK_N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Jitter Attenuated Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 GTX Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 PCI Express Endpoint Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 SFP/SFP+ Module Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 10/100/1000 Mb/s Tri-Speed Ethernet PHY (PS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Ethernet PHY Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 USB-to-UART Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 HDMI Video Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Real Time Clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Status and User LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Ethernet PHY User LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 User I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 User LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 User Pushbuttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 GPIO DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
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User PMOD GPIO Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Power On/Off Slide Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Program_B Pushbutton . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 PS Power-On and System Reset Pushbuttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 FPGA Mezzanine (FMC) Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 HPC Connector J37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 LPC Connector J5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 ZC706 Board Power System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 UCD90120A Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 LMZ31500 and LMZ31700 Family Regulator Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 XADC Power System Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 VADJ Voltage Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 SoC Programmable Logic (PL) Voltage Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Monitoring Voltage and Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Cooling Fan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 XADC Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Appendix A: Default Switch and Jumper Settings
Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Jumpers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Appendix B: VITA 57.1 FMC Connector Pinouts
Appendix C: Xilinx Constraints File
Appendix D: Board Setup
Installing the ZC706 Board in a PC Chassis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Appendix E: Board Specifications
Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Environmental . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 Humidity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 Operating Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
Appendix F: Regulatory and Compliance Information
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Declaration of Conformity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 CE Directives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 CE Standards. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Electromagnetic Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
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Appendix G: Additional Resources
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Solution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
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Chapter 1
ZC706 Evaluation Board Features
Overview
The ZC706 evaluation board for the XC7Z045 SoC provides a hardware environment for developing and evaluating designs targeting the Zynq�-7000 XC7Z045-2FFG900C SoC. The ZC706 evaluation board provides features common to many embedded processing systems, including DDR3 SODIMM and component memory, a four-lane PCI Express� interface, an Ethernet PHY, general purpose I/O, and two UART interfaces. Other features can be supported using VITA-57 FPGA mezzanine cards (FMC) attached to the low pin count (LPC) FMC and high pin count (HPC) FMC connectors.
ZC706 Evaluation Board Features
The ZC706 evaluation board features are listed in here. Detailed information for each feature is provided in Feature Descriptions starting on page 15.
� Zynq-7000 XC7Z045-2FFG900C SoC � 1 GB DDR3 memory SODIMM on the programmable logic (PL) side � 1 GB DDR3 component memory (four [256 Mb x 8] devices) on the processing system
(PS) side � Two 128 Mb Quad-SPI (QSPI) flash memory (Dual Quad-SPI) � USB 2.0 ULPI (UTMI+ low pin interface) transceiver with micro-B USB connector � Secure Digital (SD) connector � USB JTAG interface via Digilent module with micro-B USB connector � Clock sources:
� Fixed 200 MHz LVDS oscillator (differential) � I2C programmable LVDS oscillator (differential) � Fixed 33.33 MHz LVCMOS oscillator (single-ended) � Subminiature version A (SMA) connectors (differential) � SMA connectors for GTX transceiver clocking (differential)
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� GTX transceivers
� FMC HPC connector (eight GTX transceivers) � FMC LPC connector (one GTX transceiver) � SMA connectors (one pair each for TX, RX and REFCLK) � PCI Express (four lanes) � Small form-factor pluggable plus (SFP+) connector � Ethernet PHY RGMII interface � PCI Express endpoint connectivity
� Gen1 4-lane (x4) � Gen2 4-lane (x4) � SFP+ Connector
� Ethernet PHY RGMII interface with RJ-45 connector
� USB-to-UART bridge with mini-B USB connector
� HDMI codec with HDMI connector
� I2C bus
� I2C bus multiplexed to:
� Si570 user clock � ADV7511 HDMI codec � M24C08 EEPROM (1 kB) � 1-to-16 TCA6416APWR port expander � DDR3 SODIMM � RTC-8564JE real time clock � FMC HPC connector � FMC LPC connector � PMBUS data/clock � Status LEDs:
� Ethernet status � TI Power Good � Linear Power Good � PS DDR3 Component Vtt Good � PL DDR3 SODIMM Vtt Good
Overview
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Overview
� FMC Power Good � 12V Input Power On � FPGA INIT � FPGA DONE � User I/O: � Four (PL) user LEDs � Three (PL) user pushbuttons � One (PL) user DIP switch (4-pole) � Two Dual row Pmod GPIO headers � SoC PS Reset Pushbuttons: � SRST_B PS reset button � POR_B PS reset button � VITA 57.1 FMC HPC connector � VITA 57.1 FMC LPC connector � Power on/off slide switch � Program_B pushbutton � Power management with PMBus voltage and current monitoring through TI power controller � Dual 12-bit 1 MSPS XADC analog-to-digital front end � Configuration options: � Dual Quad-SPI flash memory � USB JTAG configuration port (Digilent module) � Platform cable header JTAG configuration port � 20-pin PL PJTAG header
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Block Diagram
The ZC706 evaluation board block diagram is shown in Figure 1-1.
X-Ref Target - Figure 1-1
Dual Quad-SPI Flash Memory
Page 21
JTAG Module and
JTAG Header
Page 16
DDR3 Memory 4 x 256 Mb x 8
SDRAM
Pages 17-20
DDR3 SODIMM
Page 23
Clock and Reset/POR Pushbuttons
Pages 15, 34
USB UART and
Connector
Page 40
Overview
PCIe x 4-Lane
Page 42
SD Card Connector
Page 22
FMC HPC Connector
Pages 24-27
FMC LPC Connector
Page 28
Processing System
U1 Zync-7000 AP SoC XC7Z045-2FFG900C
Programmable Logic
ARM PJTAG Header
Page 39
Switches LEDs and Pushbuttons Page 38
I2C Real Time
Clock Page 37
I2C Multiplexer and
I2C EEPROM Page 36
Mechanicals Page 58
10/100/1,000 Ethernet PHY (RGMII only)
Page 29, 30
USB 2.0 ULPI Transceiver
and Connector
Page 31
HDMI Codec and
Connector
Pages 32, 33
Configurable Clocks
Page 34
Note: Page numbers reference the page number of schematic 0381513.
XADC Header
Page 35
Figure 1-1: ZC706 Evaluation Board Block Diagram
UG954_c1_01_1002012
Board Layout
Figure 1-3 shows the ZC706 evaluation board. Each numbered feature that is referenced in Figure 1-3 is described in Table 1-1 with a link to detailed information provided under Feature Descriptions starting on page 15.
Note: The image in Figure 1-3 is for reference only and might not reflect the current revision of the
board.
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Discharge Caution
Discharge Caution
CAUTION! ESD can damage electronic components when they are improperly handled, and can result in total or intermittent failures. Always follow ESD-prevention procedures when removing and replacing components.
To prevent ESD damage:
� Use an ESD wrist or ankle strap and ensure that it makes skin contact. Connect the equipment end of the strap to an unpainted metal surface on the chassis.
� Avoid touching the adapter against your clothing. The wrist strap protects components from ESD on the body only.
� Handle the adapter by its bracket or edges only. Avoid touching the printed circuit board or the connectors.
� Put the adapter down only on an antistatic surface such as the bag supplied in your kit.
� If you are returning the adapter to Xilinx Product Support, place it back in its antistatic bag immediately.
� If a wrist strap is not available, ground yourself by touching the metal chassis before handling the adapter or any other part of the computer/server.
X-Ref Target - Figure 1-2
1 GB DDR3 Memory (SODIMM)
FMC Connector (HPC)
10/100/1000 Ethernet Interface
Differential Clock GTP SMA Clock
XADC Header
User Switches, Buttons, and LEDs
HDMI Video Interface
Artix-7 FPGA XC7A200T-2FBG676C
SD Card Interface
128 Mb Quad SPI Flash Memory
4-lane PCI Express Edge Connector
LCD Display (2 line x 16 characters)
1 KB EEPROM (I2C) I2C Bus Switch
DIP Switch SW1 Config
USB-to-UART Bridge
JTAG Interface micro-B USB Connector
Figure 1-2: AC701 Board Block Diagram
SFP+ Single Cage
UG952_c1_01_101512
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X-Ref Target - Figure 1-3
Round callout references a component 00 on the front side of the board
30 35 36
14 20
37
7
4
3
Square callout references a component 00 on the back side of the board
22
31
33
27 5 25
38
17
6
34
9
10
32
29
24
19
2
21
11 15
1 16
12
26 8
28
18 23
13
Figure 1-3: ZC706 Evaluation Board Component Locations Table 1-1: ZC706 Evaluation Board Component Descriptions
Callout
Feature
Notes
1
Zynq-7000 XC7Z045 SoC, page 15
Zynq-7000 SoC with fan sink
XC7Z045T-2FFG900C with Radian INC3001-7_1.5BU_LI98 fan sink
2
DDR3 SODIMM Memory (PL), page 19
DDR3 SODIMM Memory Socket (J1)
Micron MT8JTF12864HZ-1G6G1
3
DDR3 Component Memory (PS), page 23
Micron MT41J256M8HX-15E
DDR3 Memory 1GB (4x256M U2-U5)
4
Quad-SPI Flash Memory, page 26
Dual Quad-SPI Flash (128Mb) (U58-U59)
Spansion S25FL128SAGMFIR01
5
SD Card Interface, page 31
SD Card Interface Connector (J30)
Molex 67840-8001
6
USB 2.0 ULPI Transceiver, page 29
Digilent USB JTAG Module
USB JTAG Interface w/Micro-B Connector (U30)
7
System Clock, page 36
System Clock, 2.5V LVDS (U64)
SiTime SIT9102-243N25E200.0000
UG954_c1_02_042114
Schematic 0381513 Page Number
23 17-20
21 22 16 34
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Table 1-1: ZC706 Evaluation Board Component Descriptions (Cont'd)
Callout
Feature
Notes
8
Programmable User Clock, page 37
Silicon Labs SI570BAB0000544DG,
I2C Prog. User Clock 3.3V LVDS (U37, bottom of default 156.250 MHz
board)
9
User SMA Clock Source, page 38
Rosenberger 32K10K-400L5
User Differential SMA Clock P/N (J67/J68)
10
GTX SMA Clock (SMA_MGT_REFCLK_P and
Rosenberger 32K10K-400L5
SMA_MGT_REFCLK_N), page 39
GTX Differential SMA Clock P/N (J36/J31)
11
Jitter Attenuated Clock, page 40
Silicon Labs SI5324C-C-GM
Jitter Attenuated Clock (U60, bottom of board)
12
GTX Transceivers, page 41
GTX Transceivers
Embedded within SoC U1
13
PCI Express Endpoint Connectivity, page 46
4-lane card edge connector
PCI Express Connector (P4)
14
SFP/SFP+ Module Connector, page 48
SFP/SFP+ Module Connector (P2)
Molex 74441-0010
15
10/100/1000 Mb/s Tri-Speed Ethernet PHY
Marvell 88E1116RA0-NNC1C000
(PS), page 49
RGMII only 10/100/1000 Mb/s Ethernet PHY w/RJ45 (U51, P3)
16
GTX Differential SMA TX and RX P/N
(J35/J34and J32/J33)
Rosenberger 32K10K-400L5
17
USB-to-UART Bridge, page 51
Silicon Labs CP2103GM bridge
USB-to-UART Bridge with Mini-B Connector
(U52, J21)
18
HDMI Video Output, page 52
Analog Devices ADV7511KSTZ-P,
HDMI Controller (U53), HDMI Video Connector Molex 500254-1927,
(P1)
19
USB 2.0 ULPI Transceiver, page 29
SMSC USB3320C-EZK
USB 2.0 ULPI Controller w/ Micro-B Connector (U12, J2)
20
I2C Bus, page 55
I2C Bus MUX (U65, bottom of board)
TI PCA9548ARGER
21
Ethernet PHY User LEDs, page 59
Ethernet PHY Status LEDs (DS28-DS30)
EPHY status LED, GREEN single-stack
22
User LEDs, page 60
User LEDs (DS8-DS10, DS35)
GPIO LEDs, GREEN 0603
23
User Pushbuttons, page 61
E-Switch TL3301EF100QG in Left,
User pushbuttons, active-High (SW7, 9, 8)
Center, Right pattern
Schematic 0381513 Page Number
34 44 44 43 8 42 41
29
44 40
32, 33
31 36 29 38 38
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Table 1-1: ZC706 Evaluation Board Component Descriptions (Cont'd)
Callout
Feature
Notes
24
GPIO DIP Switch, page 62
GPIO DIP Switch (SW12)
4-pole C&K SDA04H1SBD
25
ARM� core PJTAG Header (J64)
2x10 0.1inch male header, Samtec TST-110-01-G-D
26
User PMOD GPIO Headers, page 62
PMOD Headers (J57, J58)
2x6 0.1 inch male header
27
Power On/Off Slide Switch, page 64
Power On/Off Switch (SW1)
C&K 1201M2S3AQE2
28
Program_B Pushbutton, page 65
FPGA PROG pushbutton (SW10)
E-Switch TL3301EF100QG
29
SoC MIO Config. DIP Switch (SW11)
5-pole DPDT CTS 206-125
30
HPC Connector J37, page 67
FMC HPC connector (J37)
Samtec ASP_134486_01
31
LPC Connector J5, page 71
FMC LPC connector (J5)
Samtec ASP_134603_01
32
Power Management, page 79
TI UCD90120ARGC in conjunction
Power Management System (top and bottom of w/various regulators
board)
33
XADC Analog-to-Digital Converter, page 85 2x10 0.1inch male header, Samtec
XADC Connector (J63)
TST-110-01-G-D
34
Programmable Logic JTAG Select Switch,
page 33
JTAG Configuration DIP Switch (SW4)
2-pole C&K SDA02H1SBD
35
JTAG Flying Lead Header (J62)
2x10 0.1inch male header, Samtec TST-110-01-G-D
36
2x5 shrouded PMBus connector J4
ASSMAN HW10G-0202
37
2x7 2mm shrouded JTAG cable connector J3 MOLEX 87832-1420
38
12V power input 2x6 connector J22
MOLEX-39-30-1060
Notes: 1. Jumper header locations are identified in Appendix A, Default Switch and Jumper Settings.
Schematic 0381513 Page Number
38 39 37, 39
48
38 15 24-27
28
48-57
35
16
16 48 16 48
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Feature Descriptions
Feature Descriptions
Detailed information for each feature shown in Figure 1-3 and listed in Table 1-1 is provided in this section.
Zynq-7000 XC7Z045 SoC
[Figure 1-3, callout 1] The ZC706 evaluation board is populated with the Zynq-7000 XC7Z045-2FFG900C SoC. The XC7Z045 SoC consists of an integrated processing system (PS) and programmable logic (PL), on a single die. The high-level block diagram is shown in Figure 1-4.
X-Ref Target - Figure 1-4
Processing System (PS)
Memory Interfaces
Programmable Logic (PL)
Input Output Peripherals
(IOP)
High-Bandwidth AMBA� AXI Interfaces
Application Processor Unit (APU)
Interconnect
Common Peripherals
Custom Peripherals
Common Accelerators Custom Accelerators
Figure 1-4: High-Level Block Diagram
UG954_c1_03_100112
The PS integrates two ARM� CortexTM-A9 MPCoreTM application processors, AMBA� interconnect, internal memories, external memory interfaces, and peripherals including USB, Ethernet, SPI, SD/SDIO, I2C, CAN, UART, and GPIO. The PS runs independently of the PL and boots at power-up or reset.
A system level block diagram is shown in Figure 1-5.
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Feature Descriptions
X-Ref Target - Figure 1-5
Zynq-7000 AP SoC
I/O Peripherals
USB
Processing System
Clock Generation
Reset
USB
GigE GigE SD SDIO SD SDIO GPIO UART UART CAN CAN I2C I2C SPI SPI
2x USB 2x GigE 2x SD IRQ
Central Interconnect
MIO
Memory Interfaces
SRAM/ NOR
ONFI 1.0 NAND
Q-SPI CTRL
SWDT
TTC
SystemLevel Control Regs
DMA 8 Channel
Application Processor Unit
FPU and NEON Engine
MMU
ARM Cortex-A9 CPU
32 KB I-Cache
32 KB D-Cache
FPU and NEON Engine
MMU
ARM Cortex-A9 CPU
32 KB I-Cache
32 KB D-Cache
GIC
Snoop Controller, AWDT, Timer
512 KB L2 Cache & Controller
OCM
256 K
Interconnect SRAM
CoreSight Components
DAP DevC
Memory Interfaces DDR2/3, LPDDR2 Controller
Programmable Logic to Memory Interconnect
EMIO
XADC 12-Bit ADC
General-Purpose Ports
DMA IRQ Sync
Config AES/ SHA
High-Performance Ports
Programmable Logic
Notes: 1) Arrow direction shows control (master to slave) 2) Data flows in both directions: AXI 32-Bit/64-Bit, AXI 64-Bit, AXI 32-Bit, AHB 32-Bit, APB 32-Bit, Custom
ACP
SelectIO Resources
Figure 1-5: Zynq-7000 Block Diagram
UG954_c1_04_100112
For additional information on Zynq-7000 SoC devices, see Zynq-7000 SoC Overview (DS190) and Zynq-7000 SoC Technical Reference Manual (UG585).
Device Configuration
the Zynq-7000 XC7Z045 SoC uses a multi-stage boot process that supports both a non-secure and a secure boot. The PS is the master of the boot and configuration process. For a secure boot, the PL must be powered on to enable the use of the security block located within the PL, which provides 256-bit AES and SHA decryption/authentication.
The ZC706 evaluation board supports these configuration options:
� PS Configuration: Quad-SPI flash memory � PS Configuration: Processor System Boot from SD Card (J30)
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Feature Descriptions
� PL Configuration: USB JTAG configuration port (Digilent module U30)
� PL Configuration: Platform cable header J3 and flying lead header J62 JTAG configuration ports
TIP: Designs using serial configuration based on Quad-SPI flash memory can take advantage of low-cost commodity SPI flash memory.
The JTAG configuration option is selected by setting SW11 (PS) as shown in Table 1-2 and SW4 (PL) as described in Programmable Logic JTAG Programming Options, page 33. SW11 is callout 29 in Figure 1-3.
Table 1-2: Switch SW11 Configuration Option Settings
Boot Mode
JTAG mode(1) Independent JTAG mode QSPI mode SD mode MIO configuration pin
SW11.1
0 1 0 0 MIO2
SW11.2
0 0 0 0 MIO3
SW11.3
0 0 0 1 MIO4
SW11.4
0 0 1 1 MIO5
SW11.5
0 0 0 0 MIO6
Notes: 1. Default switch setting
For more information about Zynq-7000 SoC configuration settings, see Zynq-7000 SoC Technical Reference Manual (UG585).
Encryption Key Backup Circuit
The XC7Z045 SoC U1 implements bitstream encryption key technology. The ZC706 board provides the encryption key backup battery circuit shown in Figure 1-6. The Seiko TS518FE rechargeable 1.5V lithium button-type battery B2 is soldered to the board with the positive output connected to the XC7Z045 SoC U1 VCCBATT pin P9. The battery supply current IBATT specification is 150 nA max when board power is off. B2 is charged from the VCCAUX 1.8V rail through a series diode with a typical forward voltage drop of 0.38V and 4.7 K current limit resistor. The nominal charging voltage is 1.42V.
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Feature Descriptions
X-Ref Target - Figure 1-6
D7 40V 200 mW
NC 1
3
VCCAUX
BAS40-04
To XC7Z045 AP SoC
U1 Pin P9 (VCCBATT)
FPGA_VBATT
B2
2 R9 4.70K 1% 1/16W
1 +
Lithium Battery Seiko TS518SE_FL35E 1.5V 2
GND
UG954_c1_05_041113
Figure 1-6: Encryption Key Backup Circuit
I/O Voltage Rails
There are eleven I/O banks available on the XC7Z045 SoC. The voltages applied to the XC7Z045 SoC I/O banks used by the ZC706 evaluation board are listed in Table 1-3.
Table 1-3: I/O Voltage Rails
XC7Z045 (U1) Bank
Net Name
PL Bank 0
VCC3V3_FPGA
PL Bank 9
PL Bank 10 PL Bank 11 PL Bank 12 PL Bank 13 PL Bank 33 PL Bank 34 PL Bank 35
VADJ_FPGA VCC1V5_PL
Voltage
Connected To
3.3V 2.5V 1.5V
SoC Configuration Bank 0 PMOD, USER_SMA_CLOCK, SM_FAN, REC_CLOCK, SFP_TX_DISABLE FMC_LPC, PL_JTAG,GPIO FMC_HPC, GPIO_LED, HDMI FMC_LPC, HDMI FMC_HPC, HDMI PL_DDR3_D[31:0] PL_DDR3_A, SYSCLK PL_DDR3_D[63:32], XADC
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Feature Descriptions
Table 1-3: I/O Voltage Rails (Cont'd)
XC7Z045 (U1) Bank
PS Bank 500
PS Bank 501
PS Bank 502
Net Name
VCCP1V8
Voltage
Connected To
1.8V
QSPI0,QSPI1 PHY_IF,SDIO_IF,USB_IF PS_DDR3_IF
Notes: 1. The ZC706 evaluation board is shipped with VADJ set to 2.5V.
DDR3 SODIMM Memory (PL)
[Figure 1-3, callout 2]
The memory module at J1 is a 1 GB DDR3 small outline dual-inline memory module (SODIMM). It provides volatile synchronous dynamic random access memory (SDRAM) for storing user code and data.
� Part number: MT8JTF12864HZ-1G6G1 (Micron Technology)
� Supply voltage: 1.5V
� Datapath width: 64 bits
� Data rate: Up to 1,600 MT/s
The ZC706 XC7Z045 SoC PL DDR interface performance is documented in the Zynq-7000 SoC (Z-7030, 035, 045, and Z-7100): DC and AC Switching Characteristics Data Sheet (DS191)[Ref 2].
The DDR3 interface is implemented across the PL-side I/O banks. Bank 33 and bank 35 have a dedicated DCI VRP/N resistor connection. An external 0.75V reference VTTREF_SODIMM is provided for data interface banks. Any interface connected to these banks that requires the VTTREF voltage must use this FPGA voltage reference. The connections between the DDR3 memory and the SoC are listed in Table 1-4.
Table 1-4: DDR3 SODIMM Socket J1 Connections to the XC7Z045 SoC
XC7Z045 (U1) Pin
Net Name
I/O Standard
DDR3 SODIMM Memory J1
Pin Number
Pin Name
E10
PL_DDR3_A0
SSTL15
98
A0
B9
PL_DDR3_A1
SSTL15
97
A1
E11
PL_DDR3_A2
SSTL15
96
A2
A9
PL_DDR3_A3
SSTL15
95
A3
D11
PL_DDR3_A4
SSTL15
92
A4
B6
PL_DDR3_A5
SSTL15
91
A5
F9
PL_DDR3_A6
SSTL15
90
A6
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Table 1-4: DDR3 SODIMM Socket J1 Connections to the XC7Z045 SoC (Cont'd)
XC7Z045 (U1) Pin
E8 B10 J8 D6 B7 H12 A10 G11 C6 F8 H7 A7 L1 L2 K5 J4 K1 L3 J5 K6 G6 H4 H6 H3 G1 H2 G5 G4 E2 E3 D4 E5 F4 F3 D1
Net Name
PL_DDR3_A7 PL_DDR3_A8 PL_DDR3_A9 PL_DDR3_A10 PL_DDR3_A11 PL_DDR3_A12 PL_DDR3_A13 PL_DDR3_A14 PL_DDR3_A15 PL_DDR3_BA0 PL_DDR3_BA1 PL_DDR3_BA2 PL_DDR3_D0 PL_DDR3_D1 PL_DDR3_D2 PL_DDR3_D3 PL_DDR3_D4 PL_DDR3_D5 PL_DDR3_D6 PL_DDR3_D7 PL_DDR3_D8 PL_DDR3_D9 PL_DDR3_D10 PL_DDR3_D11 PL_DDR3_D12 PL_DDR3_D13 PL_DDR3_D14 PL_DDR3_D15 PL_DDR3_D16 PL_DDR3_D17 PL_DDR3_D18 PL_DDR3_D19 PL_DDR3_D20 PL_DDR3_D21 PL_DDR3_D22
I/O Standard
SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15
DDR3 SODIMM Memory J1
Pin Number
Pin Name
86
A7
89
A8
85
A9
107
A10/AP
84
A11
83
A12_BC_N
119
A13
80
A14
78
A15
109
BA0
108
BA1
79
BA2
5
DQ0
7
DQ1
15
DQ2
17
DQ3
4
DQ4
6
DQ5
16
DQ6
18
DQ7
21
DQ8
23
DQ9
33
DQ10
35
DQ11
22
DQ12
24
DQ13
34
DQ14
36
DQ15
39
DQ16
41
DQ17
51
DQ18
53
DQ19
40
DQ20
42
DQ21
50
DQ22
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Table 1-4: DDR3 SODIMM Socket J1 Connections to the XC7Z045 SoC (Cont'd)
XC7Z045 (U1) Pin
D3 A2 B2 B4 B5 A3 B1 C1 C4 K10 L9 K12 J9 K11 L10 J10 L7 F14 F15 F13 G16 G15 E12 D13 E13 D15 E15 D16 E16 C17 B16 D14 B17 B12 C12
Net Name
PL_DDR3_D23 PL_DDR3_D24 PL_DDR3_D25 PL_DDR3_D26 PL_DDR3_D27 PL_DDR3_D28 PL_DDR3_D29 PL_DDR3_D30 PL_DDR3_D31 PL_DDR3_D32 PL_DDR3_D33 PL_DDR3_D34 PL_DDR3_D35 PL_DDR3_D36 PL_DDR3_D37 PL_DDR3_D38 PL_DDR3_D39 PL_DDR3_D40 PL_DDR3_D41 PL_DDR3_D42 PL_DDR3_D43 PL_DDR3_D44 PL_DDR3_D45 PL_DDR3_D46 PL_DDR3_D47 PL_DDR3_D48 PL_DDR3_D49 PL_DDR3_D50 PL_DDR3_D51 PL_DDR3_D52 PL_DDR3_D53 PL_DDR3_D54 PL_DDR3_D55 PL_DDR3_D56 PL_DDR3_D57
I/O Standard
SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15
DDR3 SODIMM Memory J1
Pin Number
Pin Name
52
DQ23
57
DQ24
59
DQ25
67
DQ26
69
DQ27
56
DQ28
58
DQ29
68
DQ30
70
DQ31
129
DQ32
131
DQ33
141
DQ34
143
DQ35
130
DQ36
132
DQ37
140
DQ38
142
DQ39
147
DQ40
149
DQ41
157
DQ42
159
DQ43
146
DQ44
148
DQ45
158
DQ46
160
DQ47
163
DQ48
165
DQ49
175
DQ50
177
DQ51
164
DQ52
166
DQ53
174
DQ54
176
DQ55
181
DQ56
183
DQ57
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Table 1-4: DDR3 SODIMM Socket J1 Connections to the XC7Z045 SoC (Cont'd)
XC7Z045 (U1) Pin
A12 A14 A13 B11 C14 B14 J3 F2 E1 C2 L12 G14 C16 C11 K2 K3 H1 J1 D5 E6 A4 A5 K8 L8 F12 G12 E17 F17 A15 B15 G7 C9 G17 J11 H8
Net Name
PL_DDR3_D58 PL_DDR3_D59 PL_DDR3_D60 PL_DDR3_D61 PL_DDR3_D62 PL_DDR3_D63 PL_DDR3_DM0 PL_DDR3_DM1 PL_DDR3_DM2 PL_DDR3_DM3 PL_DDR3_DM4 PL_DDR3_DM5 PL_DDR3_DM6 PL_DDR3_DM7 PL_DDR3_DQS0_N PL_DDR3_DQS0_P PL_DDR3_DQS1_N PL_DDR3_DQS1_P PL_DDR3_DQS2_N PL_DDR3_DQS2_P PL_DDR3_DQS3_N PL_DDR3_DQS3_P PL_DDR3_DQS4_N PL_DDR3_DQS4_P PL_DDR3_DQS5_N PL_DDR3_DQS5_P PL_DDR3_DQS6_N PL_DDR3_DQS6_P PL_DDR3_DQS7_N PL_DDR3_DQS7_P PL_DDR3_ODT0 PL_DDR3_ODT1 PL_DDR3_RESET_B PL_DDR3_S0_B PL_DDR3_S1_B
I/O Standard
SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 DIFF_SSTL15 DIFF_SSTL15 DIFF_SSTL15 DIFF_SSTL15 DIFF_SSTL15 DIFF_SSTL15 DIFF_SSTL15 DIFF_SSTL15 DIFF_SSTL15 DIFF_SSTL15 DIFF_SSTL15 DIFF_SSTL15 DIFF_SSTL15 DIFF_SSTL15 DIFF_SSTL15 DIFF_SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 SSTL15
DDR3 SODIMM Memory J1
Pin Number
Pin Name
191
DQ58
193
DQ59
180
DQ60
182
DQ61
192
DQ62
194
DQ63
11
DM0
28
DM1
46
DM2
63
DM3
136
DM4
153
DM5
170
DM6
187
DM7
10
DQS0_N
12
DQS0_P
27
DQS1_N
29
DQS1_P
45
DQS2_N
47
DQS2_P
62
DQS3_N
64
DQS3_P
135
DQS4_N
137
DQS4_P
152
DQS5_N
154
DQS5_P
169
DQS6_N
171
DQS6_P
186
DQS7_N
188
DQS7_P
116
ODT0
120
ODT1
30
RESET_B
114
S0_B
121
S1_B
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Table 1-4: DDR3 SODIMM Socket J1 Connections to the XC7Z045 SoC (Cont'd)
XC7Z045 (U1) Pin
Net Name
M10
F7 E7 H11 D10 C7 F10 G10 D8 D9
PL_DDR3_TEMP_EVE NT
PL_DDR3_WE_B PL_DDR3_CAS_B PL_DDR3_RAS_B PL_DDR3_CKE0 PL_DDR3_CKE1 PL_DDR3_CLK0_N PL_DDR3_CLK0_P PL_DDR3_CLK1_N PL_DDR3_CLK1_P
I/O Standard
SSTL15
SSTL15 SSTL15 SSTL15 SSTL15 SSTL15 DIFF_SSTL15 DIFF_SSTL15 DIFF_SSTL15 DIFF_SSTL15
DDR3 SODIMM Memory J1
Pin Number
Pin Name
198
EVENT_B
113
WE_B
115
CAS_B
110
RAS_B
73
CKE0
74
CKE1
103
CK0_N
101
CK0_P
104
CK1_N
102
CK1_P
The ZC706 DDR3 SODIMM interface adheres to the constraints guidelines documented in the "Dynamic Memory" section of the Zynq-7000 SoC PCB Design and Pin Planning Guide (UG933). The ZC706 DDR3 SODIMM interface is a 40 impedance implementation. For more details, see the MT8JTF12864HZ-1G6G1 data sheet [Ref 35].
DDR3 Component Memory (PS)
[Figure 1-3, callout 3]
The 1 GB, 32-bit wide DDR3 component memory system is comprised of four SDRAMs at U2-U5. This memory system is connected to the XC7Z045 SoC Processing System (PS) memory interface bank 502.
� Part number: MT41J256M8HX-15E (Micron Technology)
� Configuration: 2Gb: 256 Mb x 8
� Supply voltage: 1.5V
� Datapath width: 32 bits
� Data rate: Up to 1,333 MT/s
The ZC706 XC7Z045 SoC PS DDR Bank 502 interface performance is documented in the Zynq-7000 SoC (Z-7030, 035, 045, and Z-7100): DC and AC Switching Characteristics Data Sheet (DS191)[Ref 2].
The DDR3 0.75V VTT termination voltage is sourced from linear regulator U27. The connections between the DDR3 component memory and XC7Z045 SoC bank 502 are listed in Table 1-5.
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Table 1-5: DDR3 Component Memory Connections to the XC7Z045 SoC
XC7Z045 (U1) Pin
Net Name
Component Memory
Pin Number
Pin Name
E26
PS_DDR3_DQ0
B3
DQ0
A25
PS_DDR3_DQ1
C7
DQ1
E27
PS_DDR3_DQ2
C2
E25
PS_DDR3_DQ3
C8
DQ2 DQ3
D26
PS_DDR3_DQ4
E3
DQ4
B25
PS_DDR3_DQ5
E8
DQ5
D25
PS_DDR3_DQ6
D2
B27
PS_DDR3_DQ7
E7
A27
PS_DDR3_DQ8
B3
DQ6 DQ7 DQ8
A28
PS_DDR3_DQ9
C7
DQ9
A29
PS_DDR3_DQ10
C2
DQ10
C28
PS_DDR3_DQ11
C8
D30
PS_DDR3_DQ12
E3
DQ11 DQ12
A30
PS_DDR3_DQ13
E8
DQ13
D29
PS_DDR3_DQ14
D2
DQ14
D28
PS_DDR3_DQ15
E7
H27
PS_DDR3_DQ16
B3
G27
PS_DDR3_DQ17
C7
DQ15 DQ16 DQ17
H28
PS_DDR3_DQ18
C2
DQ18
E28
PS_DDR3_DQ19
C8
DQ19
E30
PS_DDR3_DQ20
E3
F28
PS_DDR3_DQ21
E8
DQ20 DQ21
G30
PS_DDR3_DQ22
D2
DQ22
F30
PS_DDR3_DQ23
E7
DQ23
K27
PS_DDR3_DQ24
B3
J30
PS_DDR3_DQ25
C7
J28
PS_DDR3_DQ26
C2
DQ24 DQ25 DQ26
J29
PS_DDR3_DQ27
C8
DQ27
K30
PS_DDR3_DQ28
E3
DQ28
M29 L30 M30
PS_DDR3_DQ29
E8
PS_DDR3_DQ30
D2
PS_DDR3_DQ31
E7
DQ29 DQ30 DQ31
C27
PS_DDR3_DM0
B7
DM0
C26
PS_DDR3_DQS0_P
C3
DQS0_P
Ref. Des.
U2 U2 U2 U2 U2 U2 U2 U2 U3 U3 U3 U3 U3 U3 U3 U3 U4 U4 U4 U4 U4 U4 U4 U4 U5 U5 U5 U5 U5 U5 U5 U5 U2 U2
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Table 1-5: DDR3 Component Memory Connections to the XC7Z045 SoC (Cont'd)
XC7Z045 (U1) Pin
B26 B30 C29 B29 H29 G29 F29 K28 L28 L29 L25 K26 L27 G25 J26 G24 H26 K22 F27 J23 G26 H24 K23 H23 J24 M27 M26 M25 K25 J25 M22 N23 M24 N24 F25
Net Name
PS_DDR3_DQS0_N PS_DDR3_DM1
PS_DDR3_DQS1_P PS_DDR3_DQS1_N
PS_DDR3_DM2 PS_DDR3_DQS2_P PS_DDR3_DQS2_N
PS_DDR3_DM3 PS_DDR3_DQS3_P PS_DDR3_DQS3_N
PS_DDR3_A0 PS_DDR3_A1 PS_DDR3_A2 PS_DDR3_A3 PS_DDR3_A4 PS_DDR3_A5 PS_DDR3_A6 PS_DDR3_A7 PS_DDR3_A8 PS_DDR3_A9 PS_DDR3_A10 PS_DDR3_A11 PS_DDR3_A12 PS_DDR3_A13 PS_DDR3_A14 PS_DDR3_BA0 PS_DDR3_BA1 PS_DDR3_BA2 PS_DDR3_CLK_P PS_DDR3_CLK_N PS_DDR3_CKE PS_DDR3_WE_B PS_DDR3_CAS_B PS_DDR3_RAS_B PS_DDR3_RESET_B
Component Memory
Pin Number
Pin Name
Ref. Des.
D3
DQS0_N
U2
B7
DM1
U3
C3
DQS1_P
U3
D3
DQS1_N
U3
B7
DM2
U4
C3
DQS2_P
U4
D3
DQS2_N
U4
B7
DM3
U5
C3
DQS3_P
U5
D3
DQS3_N
U5
K3
A0
U2, U3, U4, U5
L7
A1
U2, U3, U4, U5
L3
A2
U2, U3, U4, U5
K2
A3
U2, U3, U4, U5
L8
A4
U2, U3, U4, U5
L2
A5
U2, U3, U4, U5
M8
A6
U2, U3, U4, U5
M2
A7
U2, U3, U4, U5
N8
A8
U2, U3, U4, U5
M3
A9
U2, U3, U4, U5
H7
A10
U2, U3, U4, U5
M7
A11
U2, U3, U4, U5
K7
A12
U2, U3, U4, U5
N3
A13
U2, U3, U4, U5
N7
A14
U2, U3, U4, U5
J2
BA0
U2, U3, U4, U5
K8
BA1
U2, U3, U4, U5
J3
BA2
U2, U3, U4, U5
F7
CK
U2, U3, U4, U5
G7
CK_B
U2, U3, U4, U5
G9
CKE
U2, U3, U4, U5
H3
WE_B
U2, U3, U4, U5
G3
CAS_B
U2, U3, U4, U5
F3
RAS_B
U2, U3, U4, U5
N2
RESET_B
U2, U3, U4, U5
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Table 1-5: DDR3 Component Memory Connections to the XC7Z045 SoC (Cont'd)
XC7Z045 (U1) Pin
N22 L23 N21 M21 L22 L24
Net Name
PS_DDR3_CS_B PS_DDR3_ODT
PS_VRN PS_VRP VTTVREF_PS VTTVREF_PS
Component Memory
Pin Number
Pin Name
Ref. Des.
H2
CS_B
U2, U3, U4, U5
G1
ODT
U2, U3, U4, U5
The ZC706 DDR3 component interface adheres to the constraints guidelines documented in the DDR3 Design Guidelines section of Zynq-7000 SoC PCB Design and Pin Planning Guide (UG933). The ZC706 DDR3 component interface is a 40 impedance implementation. For more details, see the MT41J256M8HX-15E data sheet [Ref 35].
Quad-SPI Flash Memory
[Figure 1-3, callout 4]
The Quad-SPI flash memory located at U58 and U59 provides 2 x 128 Mb of nonvolatile storage that can be used for configuration and data storage.
� Part number: S25FL128SAGMFIR01 (Spansion) � Supply voltage: 1.8V � Datapath width: 4 bits � Data rate: Various depending on Single/Dual/Quad mode
The connections between the SPI flash memory and the XC7Z045 SoC are listed in Table 1-6.
Table 1-6: Quad-SPI Flash Memory Connections to the XC7Z045 SoC
XC7Z045 (U1)
Pin Name
PS_MIO6
Bank Pin Number
500
D24
Schematic Net Name
QSPI0_CLK
Quad-SPI Flash Memory
Pin Number Pin Name
16
C
PS_MIO5
500
C24
QSPI0_IO3
1
DQ3_HOLD_B
PS_MIO4
500
E23
QSPI0_IO2
9
WP_B
PS_MIO3
500
C23
QSPI0_IO1
8
DQ1
PS_MIO2
500
F23
QSPI0_IO0
15
DQ0
PS_MIO1
500
D23
QSPI0_CS_B
7
S_B
PS_MIO9
500
A24
QSPI1_CLK
16
C
QSPI Device MIO Select Ref. Des. Header
U58
J74.2
U58
J73.2
U58
J72.2
U58
J71.2
U58
J70.2
U58
N/A
U59
N/A
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Table 1-6: Quad-SPI Flash Memory Connections to the XC7Z045 SoC (Cont'd)
XC7Z045 (U1)
Pin Name
PS_MIO13
Bank Pin Number
500
F22
PS_MIO12
500
E21
PS_MIO11
500
A23
PS_MIO10
500
E22
PS_MIO0
500
F24
Schematic Net Name
QSPI1_IO3 QSPI1_IO2 QSPI1_IO1 QSPI1_IO0 QSPI1_CS_B
Quad-SPI Flash Memory
Pin Number Pin Name
1
DQ3_HOLD_B
9
WP_B
8
DQ1
15
DQ0
7
S_B
QSPI Device MIO Select Ref. Des. Header
U59
N/A
U59
N/A
U59
N/A
U59
N/A
U59
N/A
The configuration section of the Zynq-7000 SoC Technical Reference Manual UG585, provides details on using the Quad-SPI flash memory.
Figure 1-7 shows the connections of the linear Quad-SPI flash memory on the ZC706 evaluation board. For more details, see the Spansion S25FL128SAGMFIR01 data sheet [Ref 17].
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X-Ref Target - Figure 1-7
VCCP1V8
VCC3V3_PS
VCCP1V8
C39
1 0.1UF 2 25V
X5R
GND
QSPI0_IO3
QSPI0_CS_B QSPI0_IO1
1 R207
330 1/10W 2 5%
1 R531
0 1/10W 2 5%
1 R527
DNP DNP 2 DNP
1 R528
DNP DNP 2 DNP
S25FL128SAGMFIR01
NC NC NC NC
1 2 3 4 5 6 7 8
DQ3_HOLD_B
C
VCC
DQ0
NC0
NC7
NC1
NC6
NC2
NC5
NC3
NC4
S_B
VSS
DQ1 DQ2_VPP_WP_B
16 15 14 13 12 11 10 9
NC NC NC
U58
SO16_50P300X413
GND
VCCP1V8
VCC3V3_PS
VCCP1V8
C40
1 0.1UF
2 25V X5R
1 R208
330 1/10W 2 5%
1 R532
0 1/10W 2 5%
1 R530
DNP DNP 2 DNP
1 R529
DNP DNP 2 DNP
QSPI1_IO3
QSPI1_CS_B QSPI1_IO1
S25FL128SAGMFIR01
1 DQ3_HOLD_B
C 16
2 VCC
DQ0 15
NC
3 NC0
NC7 14
NC
4 NC1
NC6 13 NC
NC
5 NC2
NC5 12 NC
NC
6 NC3
NC4 11 NC
7 S_B
VSS 10
8 DQ1 DQ2_VPP_WP_B 9
U59
SO16_50P300X413
GND
Figure 1-7: 128 Mb Quad-SPI Flash Memory
Feature Descriptions
C714
1 0.1UF 2 25V
X5R GND
QSPI0_CLK QSPI0_IO0
QSPI0_IO2
C715
1 0.1UF 2 25V
X5R
QSPI1_CLK QSPI1_IO0
QSPI1_IO2
UG954_c1_06_073013
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USB 2.0 ULPI Transceiver
[Figure 1-3, callout 19]
The ZC706 evaluation board uses a Standard Microsystems Corporation USB3320 USB 2.0 ULPI Transceiver at U12 to support a USB connection to the host computer. A USB cable is supplied in the ZC706 evaluation kit (Standard-A connector to host computer, Micro-B connector to ZC706 evaluation board connector J2). The USB3320 is a high-speed USB 2.0 PHY supporting the UTMI+ low pin interface (ULPI) interface standard. The ULPI standard defines the interface between the USB controller IP and the PHY device which drives the physical USB bus. Use of the ULPI standard reduces the interface pin count between the USB controller IP and the PHY device.
The USB3320 is clocked by a 24 MHz crystal. Consult the SMSC USB3320 data sheet for clocking mode details [Ref 18].
The interface to the USB3320 transceiver is implemented through the IP in the XC7Z045 SoC Processor System.
Table 1-7 describes the jumper settings for the USB 2.0 circuit. Bold text identifies the default OTG mode settings.
Table 1-7: USB Jumper Settings
Header Function
Shunt Position
Notes
J11 USB PHY reset Shunt ON = USB PHY reset
Clean reset requires external
Shunt OFF = USB PHY normal operation debouncing
J10 VBUS 5V Supply Shunt ON = Host or OTG mode Shunt OFF = Device mode
J48 RVBUS select
Position 1�2 = Device mode only (10 K) Overvoltage protection Position 2�3 = OTG or Host mode (1 K)
J50 CVBUS select
Position 1-2 = OTG and Device mode 1 F VBUS load capacitance Position 2-3 = Host mode 120 F
J49 Cable ID select Position 1-2 = A/B cable detect Position 2-3 = ID not used
Used in OTG mode
J51 USB Micro-B
Position 1-2 = Shield connected to GND Position 2-3 = Shield floating
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The connections between the USB Micro-B connector at J2 and the PHY at U12 are listed in Table 1-8.
Table 1-8: USB Connector Pin Assignments and Signal Definitions Between J2 and U12
USB Connector J1
Pin Name
Net Name
Description
USB3320 (U12) Pin
1
VBUS USB_VBUS_SEL
+5V from host system
22
2
D_N
USB_D_N
3
D_P
USB_D_P
5
GND
GND
Bidirectional differential serial data (N-side)
19
Bidirectional differential serial data (P-side)
18
Signal ground
33
The connections between the USB 2.0 PHY at U12 and the XC7Z045 SoC are listed in Table 1-9.
Table 1-9: USB 2.0 ULPI Transceiver Connections to the XC7Z045 SoC
Pin Name
PS_MIO36
XC7Z045 (U1) Bank
501
Pin Number
H17
Schematic Net Name
USB_CLKOUT
PS_MIO31
501
H21
USB_NXT
PS_MIO32
501
K17
USB_DATA0
PS_MIO33
501
G22
USB_DATA1
PS_MIO34
501
K18
USB_DATA2
PS_MIO35
501
G21
USB_DATA3
PS_MIO28
501
L17
USB_DATA4
PS_MIO37
501
B21
USB_DATA5
PS_MIO38
501
PS_MIO39
501
PS_MIO30
501
PS_MIO29
501
PS_MIO7
500
A20
USB_DATA6
F18
USB_DATA7
L18
USB_STP
E8
USB_DIR
D5
USB_RESET_B_AND
USB3320 (U12) Pin
1 2 3 4 5 6 7 9 10 13 29 31 27 (via AND gate U13)
For additional information on the Zynq-7000 SoC device USB controllers, see Zynq-7000 SoC Overview (DS190) and Zynq-7000 SoC Technical Reference Manual (UG585).
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Figure 1-8 shows the USB 2.0 ULPI transceiver circuitry. Note that the shield for the USB Micro-B connector (J2) can be tied to GND by a jumper on header J51 pins 1�2 (default). The USB shield can optionally be connected through a capacitor to GND by installing a capacitor (body size 0402) at location C335 and jumping pins 2-3 on header J51.
X-Ref Target - Figure 1-8
8 USB_CLKOUT 8 USB_NXT 8 USB_DATA0 8 USB_DATA1 8 USB_DATA2 8 USB_DATA3 8 USB_DATA4
2 PLACES VCCMIO
C70
C71
C74 1 1 1
0.1UF
25V
2
2
2
3 PLACES
GND USB3320_QFN32
1 CLKOUT_1 2 NXT_2 3 DATA0_3 4 DATA1_4 5 DATA2_5 6 DATA3_6 7 DATA4_7 8 REFSEL0_8
VCCP1V8
U12
8 USB_DATA5 USB_DATA6
8 USB_DATA7
8
9 DATA5_9 10 DATA6_10 11 REFSEL1_11 NC 12 NC_12 13 DATA7_13 14 REFSEL2_14 NC 15 SPK_L_15 NC 16 SPK_R_16
VDDIO_32 32 DIR_31 31
VDD18_30 30 STP_29 29
VDD18_28 28 RESETB_27 27 REFCLK_26 26
XO_2525
USB_DIR
9
USB_STP
9
USB_RESET_B
31
1 R178 8.06K 1/10W 2 1% 1 2 3
C496 1
R403 1
18PF 50V
2
1.0M
NPO
1/10W
5% 2
GND
X2
12 24.000MHZ
1 C497
18PF
2
50V
NPO
GND
RBIAS_23 24 ID_23 23
VBUS_22 22 VBAT_21 21 VDD33_P 20
DM_1919 DP_18 18 CPEN33_17 17
USB_ID 31
GND
USB_D_N USB_D_P
USB_VDD33 27
31 31 1
2
C209
2.2UF 6.3V
VCC5V0
1 C72
0.1UF
2
25V
GND
CTR_GND_33 33
GND
USB_VBUS_SEL
USB3320_QFN32 GND
R267 1
10.0K 1/10W
2
1 R359
1.00K 2 1/16W
USB_VBUS_SEL
L11
FERRITE-220
1
2
C447 1
1
5.6UF
10V
2
2
1
2
FERRITE-220
L12
GND
1 2
GND
C380
1UF 16V X5R
J50 1 2 3
CVBUS Select: 1-2: OTG Mode 2-3: Host Mode
1
C484
120UF
20V
2
TANT
GND
C75 27
0.1UF 27 25V
USB_D_N USB_D_P
SHLD1 6
SHLD2 7
SHLD3 8
SHLD4 9
ZX62D_AB_5P8 1
VBUS 2
D_N 3
D_P 4
ID 5 GND
J2
11 SHLD6
10 SHLD5
2
J49
1
2 USB_ID
3 USB_VDD33
27 GND 27
1-2 = A/B CABLE DETECT 2-3 = ID NOT USED
1
J51
VCC3V3
R389 1
261 1/10W
2
DS25
2
1
LED-RED-SMT
J48
1-2 = DEVICE MODE 2-3 = HOST OR OTG MODE
USB HOST POWER
MIC2025_SOP8
NC
1342 EGNFLNNCG1D
OONUUICTTN2128756
NC
U22
GND
SOP127P500X600_8
J10
1
ON = HOST OR OTG MODE
2
OFF = DEVICE MODE
VCC5V0
1 C76 1
0.1UF
2
25V
2
C469
150UF 10V TANT
GND
GND
3
1
2
C335
DNP
GND
UG954_c1_07_041113
Figure 1-8: USB 2.0 ULPI Transceiver
SD Card Interface
[Figure 1-3, callout 5]
The ZC706 evaluation board includes a secure digital input/output (SDIO) interface to provide user-logic access to general purpose nonvolatile SDIO memory cards and peripherals. Information for the SD I/O card specification can be found at the SanDisk and SD card websites [Ref 19], [Ref 20].
The SDIO signals are connected to XC7Z045 SoC PS bank 501 which has its VCCMIO set to 1.8V. A MAX13035E high-speed logic-level translator (U11) is used between XC7Z045 SoC 1.8V PS bank 501 and the 3.3V SD card connector (J30).
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Figure 1-9 shows the connections of the SD card interface on the ZC706 evaluation board.
X-Ref Target - Figure 1-9
VCCP1V8
VCC3V3_PS
1 R28 1 R29
4.7 K 4.7 K 1/10W 1/10W 2 5% 2 5%
1
C41
0.1 F
2
25V
X5R
GND
22 SDIO_CD_DAT3 22 SDIO_CMD
22 SDIO_CLK
22 SDIO_DAT0 22 SDIO_DAT1 22 SDIO_DAT2
8 SDIO_SDDET 8 SDIO_SDWP
67840-8001
1 2 3 4 5 6 7 8 9
10 11 12
CD_DAT3
CMD
VSS1
VDD
CLK
VSS2
DAT0
DAT1
IOGND2
DAT2
IOGND1
GNDTAB4
DETECT
GNDTAB3
PROTECT
GNDTAB2
DETECT_PROTECT GNDTAB1
18 17 16 15 14 13
J30 GND
GND
UG954_c1_08_041113
Figure 1-9: SD Card Interface
Table 1-10 lists the SD card interface connections to the XC7Z045 SoC
Table 1-10: SDIO Connections to the XC7Z045 SoC
XC7Z045 (U1) Pin
Pin Name
PS_MIO15
Bank
500
Pin Number
C22
Schematic Net Name
SDIO_SDWP
Level Shifter (U11) SDIO Connector (J30)
1.8V Side 3.3V Side
Pin
Pin
N/A
N/A
Pin Number
11
Pin Name
PROTECT
PS_MIO14
500
B22
SDIO_SDDET
N/A
N/A
10
DETECT
PS_MIO41
501
J18
SDIO_CMD_LS
4
20
2
CMD
PS_MIO40
501
B20
SDIO_CLK_LS
9
19
5
CLK
PS_MIO44
501
E20
SDIO_DAT2_LS
1
23
9
DAT2
PS_MIO43
501
E18
SDIO_DAT1_LS
7
16
8
DAT1
PS_MIO42
501
D20
SDIO_DAT0_LS
6
18
7
DAT0
PS_MIO45
501
H18
SDIO_CD_DAT3_LS
3
22
1
CD_DAT3
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Programmable Logic JTAG Programming Options
[Figure 1-3, callout 6] The ZC706 evaluation board JTAG chain is shown in Figure 1-10.
X-Ref Target - Figure 1-10
J3
JTAG Header
TDO TDI
U30
JTAG Module
TDO TDI
J62
JTAG Header
TDO TDI
U45 U46 U47
3:1 Analog Switch
SPST Bus Switch U32
N.C. J37 FMC HPC Connector
TDI TDO
SPST Bus Switch U31
N.C. J5
FMC LPC Connector
TDI TDO
3.3V 3.3V
U10
SN74AVC2T245 and
SN74LV541APWR Buffers
TDI
TDO
ON
12
SW4
Figure 1-10: JTAG Chain Block Diagram
U1 Zynq-7000 XC7Z045 AP SoC TDI TDO
UG954_c1_09_041113
Programmable Logic JTAG Select Switch
[Figure 1-3, callout 35]
The PL JTAG chain can be programmed by three different methods made available through a 3-to-1 analog switch (U45, U46, and U47) controlled by a 2-position DIP switch at SW4.
Figure 1-11 shows the JTAG analog switches and DIP switch SW4.
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X-Ref Target - Figure 1-11
VCC3V3
To J3 Parallel Cable or Platform Cable
(14 pins)
14PIN_JTAG_TDI 14PIN_JTAG_TMS 14PIN_JTAG_TCK
To U30 USB-to-JTAG Digilent bridge
DIGILENT_TDI DIGILENT_TMS DIGILENT_TCK
To J62 Parallel Cable
(20 Pins)
20PIN_JTAG_TDI 20PIN_JTAG_TMS 20PIN_JTAG_TCK
U45
TS5A3359 SP3T
ANALOG SWITCH
IN1
6
IN2
5
1 NO0
2 NO1
COM 7
3 NO2
4 GND
V+ 8
U46
TS5A3359 SP3T
ANALOG SWITCH
IN1
6
IN2
5
1 NO0
2 NO1
COM 7
3 NO2
4 GND
V+ 8
VCC3V3
43
SW4 SDA02H1SBD
JTAG_SEL_1 JTAG_SEL_2
R20 4.7k 0.1 W 5%
R21 4.7k 0.1 W 5%
12
GND
U47
TS5A3359
SP3T
ANALOG SWITCH
IN1
6
IN2
5
1 NO0
2 NO1 3 NO2
COM 7
4 GND
V+ 8
JTAG_TDI JTAG_TMS JTAG_TCK
Figure 1-11: PL JTAG Programming Source Analog Switch
UG954_c1_10_041113
DIP switch SW4[1:2] setting 10 selects the 14-pin header J3 for configuration using either a Parallel Cable IV (PC4) or Platform Cable USB II. DIP switch SW4 setting 01 selects the USB-to-JTAG Digilent bridge U30 for configuration over a Standard-A to Micro-B USB cable. DIP switch SW4 setting 11 selects the JTAG 20-pin header at J62. The four JTAG signals TDI, TDO, TCK, and TMS would be connected to J62 through flying leads from a JTAG cable. The 3-to-1 analog switch settings are shown in Table 1-11.
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Table 1-11: Switch SW4 Configuration Option Settings
Configuration Source
None Cable Connector J3(2) Digilent USB-to-JTAG interface U30 JTAG (flying lead) Header J62
DIP Switch SW4
Switch 1(1) JTAG_SEL_1
Switch 2(1) JTAG_SEL_2
0
0
1
0
0
1
1
1
Notes: 1. 0 = open, 1 = closed 2. Default switch setting
FMC Connector JTAG Bypass
When an FPGA mezzanine card (FMC) is attached to HPC J37 or LPC J5 it is automatically added to the JTAG chain through electronically controlled single-pole single-throw (SPST) switches U32 and U31 respectively. The SPST switches are normally closed and transition to an open state when an FMC is attached. Switch U32 adds an attached FMC to the JTAG chain as determined by the FMC_HPC_PRSNT_M2C_B signal. Switch U31 adds an attached FMC to the JTAG chain as determined by the FMC_LPC_PRSNT_M2C_B signal. The attached FMC card must implement a TDI-to-TDO connection through a device or bypass jumper for the JTAG chain to be completed to the SoC U1.
The JTAG connectivity on the ZC706 board allows a host computer to download bitstreams to the SoC using the Xilinx� iMPACT software. In addition, the JTAG connector allows debug tools such as the Vivado serial I/O analyzer or a software debugger to access the SoC. The iMPACT software tool can also indirectly program the linear QSPI flash memory. To accomplish this, the iMPACT software configures the SoC with a temporary design to access and program the QSPI memory device.
Clock Generation
[Figure 1-3, callouts 7, 8, and 9]
The ZC706 evaluation board provides four clock sources for the XC7Z045 SoC. Table 1-12 lists the source devices for each clock.
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Table 1-12: ZC706 Evaluation Board Clock Sources
Clock Name
System Clock User Clock
Clock Source
U64 U37
Description
SiT9102 2.5V LVDS 200 MHz fixed-frequency oscillator (SiTime). See System Clock, page 36. Si570 3.3V LVDS I2C programmable oscillator, 156.250 MHz default (Silicon Labs). See Programmable User Clock, page 37.
User SMA Clock
J67(P), J68(N)
User clock input SMAs, limit input swing voltage to VADJ_FPGA setting (1.8V, 2.5V, 3.3V). See User SMA Clock Source, page 38.
PS Clock
U24
SIT8103 1.8V single-ended CMOS 33.3333 MHz fixed frequency oscillator (SiTime). See Processing System Clock Source, page 39.
GTX SMA REF Clock
J36(P), J31(N)
User clock input SMAs. See GTX SMA Clock (SMA_MGT_REFCLK_P and SMA_MGT_REFCLK_N), page 39.
Jitter Attenuated Clock
U60
Si5324C LVDS precision clock multiplier/jitter attenuator (Silicon Labs). See Jitter Attenuated Clock, page 40.
Table 1-13 lists the pin-to-pin connections from each clock source to the XC7Z045 SoC.
Table 1-13: Clock Connections, Source to XC7Z045 SoC
Clock Source Pin
Net Name
U64.5
SYSCLK_N
U64.4
SYSCLK_P
U37.5
USRCLK_N
U37.4
USRCLK_P
J67.1
USER_SMA_CLOCK_P
J68.1
USER_SMA_CLOCK_N
J24.3
PS_CLK
J36.1
SMA_MGT_REFCLK_P
J31.1
SMA_MGT_REFCLK_N
U60.29
SI5324_OUT_C_N
U60.28
SI5324_OUT_C_P
U60.17
REC_CLOCK_C_N
U60.16
REC_CLOCK_C_P
U60.3
SI5324_INT_ALM_LS
U60.1
SI5324_RST_LS
I/O Standard
LVDS LVDS LVDS_25 LVDS_25 LVDS_25 LVDS_25 NA(1) NA(1) NA(1) NA(1) NA(1) LVDS_25 LVDS_25 LVCMOS25 LVCMOS25
Notes: 1. PS-side and GTX nets do not have an assigned I/O standard.
XC7Z045 (U1) Pin
G9 H9 AG14 AF14 AD18 AD19 A22 (Bank 500) W8 W7 AC7 AC8 AE20 AD20 AJ25 W23
System Clock
[Figure 1-3, callout 7]
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The system clock source is an LVDS 200 MHz oscillator at U64. It is wired to a multi-region clock capable (MRCC) input on programmable logic (PL) bank 34. The signal pair is named SYSCLK_P and SYSCLK_N and each signal is connected to U1 (pins H9 and G9, respectively) on the XC7Z045 SoC.
� Oscillator: SiTime SiT9102AI-243N25E200.00000 (200 MHz)
� Frequency tolerance: 50 ppm
� LVDS Differential Output
The system clock circuit is shown in Figure 1-12.
X-Ref Target - Figure 1-12
1 C89 0.1 �F 10V
2 X5R
VCC2V5
U64
SIT9102 200 MHz Oscillator
1 2 3
OE NC GND
VCC OUT_B
OUT
6 5 4
SYSCLK_N
1 R322 100
2 1/20W 5% SYSCLK_P
GND
Figure 1-12: System Clock Source For more details, see the SiTime SiT9102 data sheet [Ref 21].
UG954_c1_11_041113
Programmable User Clock
[Figure 1-3, callout 8]
The ZC706 evaluation board has a programmable low-jitter 3.3V LVDS differential oscillator (U37) connected to the MRCC inputs of bank 10. This USRCLK_P and USRCLK_N clock signal pair is connected to XC7Z045 SoC U1 pins AF14 and AG14, respectively. On power-up the user clock defaults to an output frequency of 156.250 MHz. User applications can change the output frequency within the range of 10 MHz to 810 MHz through an I2C interface. Power cycling the ZC706 evaluation board reverts the user clock to the default frequency of 156.250 MHz.
� Programmable Oscillator: Silicon Labs Si570BAB0000544DG (10 MHz�810 MHz)
� Frequency tolerance: 50 ppm
� LVDS Differential Output
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The user clock circuit is shown in Figure 1-13.
X-Ref Target - Figure 1-13
VCC3V3
1 R37 4.7K
2 1/10W 5%
U37
Si570
Programmable
Oscillator
1 NC 2 OE
VDD 6
USRCLK SFP SDA USRCLK SFP SCL
7 8
SDA OUT_BSCL OUT+
5 4
3 GND
VCC3V3
1 C348 0.01 F 25V
2 X7R
GND
1 R323 100
2 1/20W 5%
USRCLK N USRCLK P
GND
10 MHz-810 MHz 50PPM
Figure 1-13: User Clock Source
UG954_c1_12_041113
See the Silicon Labs Si570 data sheet [Ref 22].
User SMA Clock Source
The ZC706 board provides a pair of SMAs for differential user clock input into PL Bank 9 (see Figure 1-14). The P-side SMA J67 signal USER_SMA_CLOCK_P is connected to U1 pin AD18, with the N-side SMA J68 signal USER_SMA_CLOCK_N connected to U1 pin AD19. Bank 9 Vcco is VADJ_FPGA, a variable voltage (1.8V, 2.5V, 3.3V) depending on the ZC706 FMC interface banks voltage. The USER_SMA_CLOCK input voltage swing should not exceed the board VADJ_FPGA voltage setting.
X-Ref Target - Figure 1-14
UG954_c1_13_041113
Figure 1-14: User SMA Clock
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Processing System Clock Source
The Processing System (PS) clock source is a 1.8V LVCMOS single-ended fixed 33.33333 MHz oscillator at U24. It is wired to PS bank 500, pin A22 (PS_CLK), on the XC7Z045 SoC.
� Oscillator: SiTime SiT8103AC-23-18E-33.33333 (33.3 MHz) � Frequency tolerance: 50 ppm � Single-ended output
The system clock circuit is shown in Figure 1-15.
X-Ref Target - Figure 1-15
VCCP1V8
1 R38 4.7K
2 1/10W 5%
U24
SiT8103
Oscillator
33.33333 MHz
50 PPM
1 OE
VCC 4
VCCP1V8
1 C349
2
0.01 F 25V X7R
GND
GND
2 GND OUT 3
12
R173 24.9 1/10W 1%
PS CLK
UG954_c1_14_041113
Figure 1-15: Processing System Clock Source
For more details, see the SiTime SiT8103 data sheet [Ref 21].
GTX SMA Clock (SMA_MGT_REFCLK_P and SMA_MGT_REFCLK_N)
[Figure 1-3, callout 10]
The ZC706 board includes a pair of SMA connectors for a GTX clock wired to GTX Quad bank 111. This differential clock has signal names SMA_MGT_REFCLK_P and SMA_REFCLK_N, which are connected to SoC U1 pins W8 and W7 respectively.
� External user-provided GTX reference clock on SMA input connectors � Differential Input
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Figure 1-16 shows this AC-coupled clock circuit.
X-Ref Target - Figure 1-16
J36
SMA Connector
C145
SMA_MGT_REFCLK_C_P
SMA_MGT_REFCLK_P
0.01 F 25V X7R
J31
SMA Connector
GND
C144
SMA_MGT_REFCLK_C_N
SMA_MGT_REFCLK_N
0.01 F 25V X7R
GND
Figure 1-16: GTX SMA Clock Source
UG954_c1_15_041113
Jitter Attenuated Clock
[Figure 1-3, callout 11]
The ZC706 board includes a Silicon Labs Si5324 jitter attenuator U60 on the back side of the board. SoC user logic can implement a clock recovery circuit and then output this clock to a differential I/O pair on I/O bank 9 (REC_CLOCK_C_P, SoC U1 pin AD20 and REC_CLOCK_C_N, SoC U1 pin AE20) for jitter attenuation. The jitter attenuated clock (Si5324_OUT_C_P, Si5324_OUT_C_N) is then routed as a reference clock to GTX Quad 110 inputs MGTREFCLK1P (SoC U1 pin AC8) and MGTREFCLK1N (SoC U1 pin AC7).
The primary purpose of this clock is to support CPRI/OBSAI applications that perform clock recovery from a user-supplied SFP/SFP+ module and use the jitter attenuated recovered clock to drive the reference clock inputs of a GTX transceiver. The jitter attenuated clock circuit is shown in Figure 1-17.
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X-Ref Target - Figure 1-17
X4
114.285 MHz
20 ppm
2 GND1
XA 1
4 GND2
XB 3
SI5324_VCC
U60
Si5324C-C-GM
Clock Multiplier/
Jitter Attenuator
5 VDD1
NC1 2 NC
10 VDD2
NC2 9 NC
32 VDD3
NC3 14 NC
SI5324_XTAL_XA
6 XA
NC4 30 NC
SI5324_XTAL_XB
7 XB
NC5 33 NC CKOUT1_N 29 SI5324_OUT_N
GND REC_CLOCK_C_P
R251 REC_CLOCK_C_N 100
SI5324_INT_ALM
SI5324_RST
C138 0.1 F 25V X5R
REC_CLOCK_P
0.1W 1%
REC_CLOCK_N
CKOUT1_P 28 SI5324_OUT_P
16 CKIN1_P
35 CKOUT2_P
NC
CKOUT2_N 34 NC 17 CKIN1_N
C141 0.1 F 25V X5R
NC 12 CKIN2_P NC 13 CKIN2_N
GNDPAD 37
3 INT_C1B
CMODE 36
NC 4 C2B
SDI 27
NC
NC 11 RATE0
SDA_SDO 23
NC 15 RATE1
SCL 22
NC 18 LOL 19 GND3 20 GND4 1 RST_B
21 CS_CA
A0 24 A1 31 A2_SS 31 GND1 9 GND2 31
R89
4.7 K 5%
GND
GND
Figure 1-17: Jitter Attenuated Clock See the Silicon Labs Si5324 data sheet [Ref 22].
C137 0.1 F 25V X5R
SI5324_OUT_C_N SI5324_OUT_C_P C136 0.1 F 25V X5R
RTC SI5324_SDA RTC SI5324_SCL
UG954_c1_16_041113
GTX Transceivers
[Figure 1-3, callout 12]
The ZC706 board provides access to 16 GTX transceivers:
� Four of the GTX transceivers are wired to the PCI Express x4 endpoint edge connector (P4) fingers
� Eight of the GTX transceivers are wired to the FMC HPC connector (J37) � One GTX transceiver is wired to the FMC LPC connector (J5) � One GTX transceiver is wired to SMA connectors (RX: J32, J33 TX: J35, J34) � One GTX transceiver is wired to the SFP/SFP+ Module connector (P2)
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� One GTX transceiver is unused and is wired in a capacitively coupled TX-to-RX loopback configuration
The GTX transceivers in Zynq-7000 series SoCs are grouped into four channels described as Quads. The reference clock for a Quad can be sourced from the Quad above or Quad below the GTX Quad of interest. There are four GTX Quads on the ZC706 board with connectivity as shown here:
� Quad 109: � MGTREFCLK0 - FMC_HPC_GBTCLK0_M2C clock � MGTREFCLK1 - not connected � Contains 4 GTX transceivers allocated to FMC_HPC_DP[3:0]_C2M_P/N
� Quad 110: � MGTREFCLK0 - FMC_HPC_GBTCLK1_M2C clock � MGTREFCLK1 - SI5324_OUT_C_P/N jitter attenuator clock � Contains 4 GTX transceivers allocated to FMC_HPC_DP[7:4]_C2M_P/N
� Quad 111: � MGTREFCLK0 - FMC_LPC_GBTCLK0_M2C_C_P/N � MGTREFCLK1 - SMA_MGT_REFCLK_P/N SMA GTX clock input � Contains 1 GTX transceiver allocated to FMC_LPC_DP0_C2M_P/N � Contains 1 GTX transceiver allocated to SMA_MGT_TX_P/N and RX_P/N SMA connectors � Contains 1 GTX transceiver allocated to SFP_TX and _RX_P/N SFP/SFP+ connector � Contains 1 GTX transceiver which is unused and is wired in TX-to-RX loopback configuration
� Quad 112: � MGTREFCLK0 - PCIE_CLK_Q0_P/N PCIe edge connector clock � MGTREFCLK1 - not connected � Contains 4 GTX transceivers allocated to PCIe lanes 0-3
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Table 1-15 lists the GTX Banks 109 and 110 interface connections between the SoC U1 and FMC HPC connector J37.
Table 1-14: SoC GTX Banks 109 and 110 Interface Connections to FMC HPC J37
Transceiver Bank
SoC U1 Pin
Number
SoC U1 Pin Name
Schematic Net Name
Connected Connected
Pin
Device
AK10
MGTPTXP0_109
FMC_HPC_DP0_C2M_P
C2
AK9
MGTPTXN0_109
FMC_HPC_DP0_C2M_N
C3
AH10
MGTPRXP0_109
FMC_HPC_DP0_M2C_P
C6
AH9
MGTPRXN0_109
FMC_HPC_DP0_M2C_N
C7
AK6
MGTPTXP1_109
FMC_HPC_DP1_C2M_P
A22
AK5
MGTPTXN1_109
FMC_HPC_DP1_C2M_N
A23
AJ8
MGTPRXP1_109
FMC_HPC_DP1_M2C_P
A2
AJ7
MGTPRXN1_109
FMC_HPC_DP1_M2C_N
A3
AJ4 AJ3 GTX_BANK_109 AG8
MGTPTXP2_109 MGTPTXN2_109 MGTPRXP2_109
FMC_HPC_DP2_C2M_P FMC_HPC_DP2_C2M_N FMC_HPC_DP2_M2C_P
A26
FMC HPC
A27
J37
A6
AG7
MGTPRXN2_109
FMC_HPC_DP2_M2C_N
A7
AK2
MGTPTXP3_109
FMC_HPC_DP3_C2M_P
A30
AK1
MGTPTXN3_109
FMC_HPC_DP3_C2M_N
A31
AE8
MGTPRXP3_109
FMC_HPC_DP3_M2C_P
A10
AE7 AD10 AD9
MGTPRXN3_109 MGTREFCLK0P_109 MGTREFCLK0N_109
FMC_HPC_DP3_M2C_N
A11
FMC_HPC_GBTCLK0_M2C_C_P (1) D4
FMC_HPC_GBTCLK0_M2C_C_N (1) D5
AF10
MGTREFCLK1P_109 NC
NA
NA
AF9
MGTREFCLK1N_109 NC
NA
NA
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Table 1-14: SoC GTX Banks 109 and 110 Interface Connections to FMC HPC J37 (Cont'd)
Transceiver Bank
GTX_BANK_110
SoC U1 Pin
Number
AH2 AH1 AH6 AH5 AF2 AF1 AG4 AG3 AE4 AE3 AF6 AF5 AD2 AD1 AD6 AD5 AA8 AA7 AC8 AC7
SoC U1 Pin Name
MGTPTXP0_110 MGTPTXN0_110 MGTPRXP0_110 MGTPRXN0_110 MGTPTXP1_110 MGTPTXN1_110 MGTPRXP1_110 MGTPRXN1_110 MGTPTXP2_110 MGTPTXN2_110 MGTPRXP2_110 MGTPRXN2_110 MGTPTXP3_110 MGTPTXN3_110 MGTPRXP3_110 MGTPRXN3_110 MGTREFCLK0P_110 MGTREFCLK0N_110 MGTREFCLK1P_110 MGTREFCLK1N_110
Schematic Net Name
FMC_HPC_DP4_C2M_P FMC_HPC_DP4_C2M_N FMC_HPC_DP4_M2C_P FMC_HPC_DP4_M2C_N FMC_HPC_DP5_C2M_P FMC_HPC_DP5_C2M_N FMC_HPC_DP5_M2C_P FMC_HPC_DP5_M2C_N FMC_HPC_DP6_C2M_P FMC_HPC_DP6_C2M_N FMC_HPC_DP6_M2C_P FMC_HPC_DP6_M2C_N FMC_HPC_DP7_C2M_P FMC_HPC_DP7_C2M_N FMC_HPC_DP7_M2C_P FMC_HPC_DP7_M2C_N FMC_HPC_GBTCLK1_M2C_P (1) FMC_HPC_GBTCLK1_M2C_N (1) SI5324_OUT_C_P (2) SI5324_OUT_C_N (2)
Connected Connected
Pin
Device
A34
A35
A14
A15
A38
A39
A18
A19
B36
FMC HPC
B37
J37
B16
B17
B32
B33
B12
B13
B20
B21
28
SI5324C
29
U60
Notes: 1. SoC U1 GTX input clock nets are capacitively coupled to the FMC HPC J37 pins. 2. SoC U1 GTX input clock nets are capacitively coupled to the SI5324C Recovery Clock U60 output pins.
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Table 1-15 lists the GTX Bank interface connections between the SoC U1 and FMC LPC connector J5.
Table 1-15: SoC GTX Bank 111 Interface Connections to FMC LPC J5
Transceiver Bank
GTX_BANK_11 1
SoC U1 Pin Number
SoC U1 Pin Name
AB2
MGTPTXP0_111
AB1
MGTPTXN0_111
AC4
MGTPRXP0_111
AC3
MGTPRXN0_111
Y2
MGTPTXP1_111
Y1
MGTPTXN1_111
AB6
MGTPRXP1_111
AB5
MGTPRXN1_111
W4
MGTPTXP2_111
W3
MGTPTXN2_111
Y6
MGTPRXP2_111
Y5
MGTPRXN2_111
V2
MGTPTXP3_111
V1
MGTPTXN3_111
AA4
MGTPRXP3_111
AA3
MGTPRXN3_111
U8
MGTREFCLK0P_111
U7
MGTREFCLK0N_111
W8
MGTREFCLK1P_111
W7
MGTREFCLK1N_111
Schematic Net Name
Connected Connected
Pin
Device
FMC_LPC_DP0_C2M_P
C2
FMC_LPC_DP0_C2M_N FMC_LPC_DP0_M2C_P
C3
FMC LPC
C6
J5
FMC_LPC_DP0_M2C_N
C7
SMA_MGT_TX_P
J35.1
SMA_MGT_TX_N SMA_MGT_RX_P (2)
J34.1 J32.1
GTX TX/RX SMA
SMA_MGT_RX_N (2)
J33.1
SFP_TX_P
18
SFP_TX_N SFP_RX_P
19
SFP+
13
Conn. P2
SFP_RX_N
12
(capacitively coupled to AA4) (Cooperatively coupled to AA3) See Pin V2 loopback See Pin V1 loopback
U1.AA4 U1.AA3 U1.V2 U1.V1
SoC U1 GTX Loopback
FMC_LPC_GBTCLK0_M2C_C_P (1) D4 FMC_LPC_GBTCLK0_M2C_C_N (1) D5
FMC LPC J5
SMA_MGT_REFCLK_P (2) SMA_MGT_REFCLK_N (2)
J36.1 J31.1
GTX REFCLK SMA
Notes: 1. SoC U1 GTX input clock nets are capacitively coupled to the FMC LPC J5 pins. 2. SoC U1 GTX input nets are capacitively coupled to the RX and MGT_REFCLK SMA pins.
For additional information on Zynq-7000 GTX transceivers, see 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476).
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PCI Express Endpoint Connectivity
[Figure 1-3, callout 13]
The 4-lane PCI Express edge connector performs data transfers at the rate of 2.5 GT/s for a Gen1 application and 5.0 GT/s for a Gen2 application. The PCIe transmit and receive signal data paths have a characteristic impedance of 85 �10%. The PCIe clock is routed as a 100 differential pair.
The XC7Z045-2FFG900C SoC (-2 speed grade) included with the ZC706 board supports up to Gen2 x4.
The PCIe clock is input from the edge connector. It is AC coupled to the SoC through the MGTREFCLK0 pins of Quad 112. PCIE_CLK_Q0_P is connected to SoC U1 pin N8, and the _N net is connected to pin N7. The PCI Express clock circuit is shown in Figure 1-18.
X-Ref Target - Figure 1-18
P4 PCI Express Eight-Lane
Edge connector
OE GND A12 REFCLK+ A13 REFCLK- A14
A15 GND
PCIE_CLK_Q0_C_P
C352 0.01F 25V X7R
PCIE_CLK_Q0_P
PCIE_CLK_Q0_C_N
PCIE_CLK_Q0_N
GND
C353 0.01F 25V X7R
UG954_c1_17_041113
Figure 1-18: PCI Express Clock
PCIe lane width/size is selected by jumper J19 (Figure 1-18). The default lane size selection is 4-lane (J19 pins 3 and 4 jumpered).
X-Ref Target - Figure 1-19
PCIE_PRSNT_X1 1 J19 2
PCIE_PRSNT_X4 3
4
PCIE_PRSNT_B
UG954_c1_18_041113
Figure 1-19: PCI Express Lane Size Select Jumper J19
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Table 1-18 lists the GTX Bank 112 interface connections between the SoC U1 and PCIe 4-lane connector P4.
Table 1-16: SoC GTX Bank 112 Interface Connections to PCIe 4-Lane Connector P4
Transceiver Bank
GTX_BANK_112
SoC U1 Pin Number
T2 T1 V6 V5 R4 R3 U4 U3 P2 P1 T6 T5 N4 N3 P6 P5 N8 N7 R8 R7
SoC U1 Pin Name
MGTPTXP0_112 MGTPTXN0_112 MGTPRXP0_112 MGTPRXN0_112 MGTPTXP1_112 MGTPTXN1_112 MGTPRXP1_112 MGTPRXN1_112 MGTPTXP2_112 MGTPTXN2_112 MGTPRXP2_112 MGTPRXN2_112 MGTPTXP3_112 MGTPTXN3_112 MGTPRXP3_112 MGTPRXN3_112 MGTREFCLK0P_112 MGTREFCLK0N_112 MGTREFCLK1P_112 MGTREFCLK1N_112
Schematic Net Name
PCIe 4-Lane Conn. P4 Pin Number
PCIE_TX3_P
A29 (1)
PCIE_TX3_N
A30 (1)
PCIE_RX3_P
B27
PCIE_RX3_N
B28
PCIE_TX2_P
A25 (1)
PCIE_TX2_N
A26 (1)
PCIE_RX2_P
B23
PCIE_RX2_N
B24
PCIE_TX1_P
A21 (1)
PCIE_TX1_N
A22 (1)
PCIE_RX1_P
B19
PCIE_RX1_N
B20
PCIE_TX0_P
A16 (1)
PCIE_TX0_N
A17 (1)
PCIE_RX0_P
B14
PCIE_RX0_N
B15
PCIE_CLK_QO_P
A13 (1)
PCIE_CLK_QO_N
A14 (1)
NC
NA
NC
NA
Notes: 1. PCIE_TXn_P/N and PCIE_CLK_Q0_P/N are capacitively coupled to the PCIe edge connector P4.
For additional information about Zynq-7000 PCIe functionality, see 7 Series FPGAs Integrated Block for PCI Express Product Guide for Vivado Design Suite (PG054). Additional information about the PCI Express standard is available [Ref 23].
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SFP/SFP+ Module Connector
[Figure 1-3, callout 14]
The ZC706 board contains a small form-factor pluggable (SFP/SFP+) connector and cage assembly P2 that accepts SFP or SFP+ modules. Figure 1-20 shows the SFP/SFP+ module connector circuitry.
X-Ref Target - Figure 1-20
C198 22F
VCC3V3
VCC3V3
L6 4.7H 3.0 A
L7 4.7H 3.0 A
P2
SFP+ Module Connector 74441-0010
C134 0.1F
C199 22F
GND
SFP_VCCR 15 SFP_VCCT 16
C135
10
0.1F
11
14
1
17
20
21
22
23
24
25
26
27
28
29
30
31
32
VCCR VCCT
VEER_1 VEER_2 VEER_3 VEET_1
RD_N 12 RD_P 13
SFP_RX_N SFP_RX_P
TD_P 18 SFP_TX_P
19 SFP_TX_N TD_N
SDA 4 SFP_IIC_SDA
SCL 5 SFP_IIC_SCL
R84 4.7K
VEET_2 TX_FAULT 2
VEET_3 TX_DISABLE
3
GND1
GND2 MOD_ABS 6
SFP_TX_FAULT SFP_TX_DISABLE_TRANS SFP_MOD_DETECT
VCC3V3
R83
R85
4.7K 4.7K
R86 4.7K
J22 1 J21 1
GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 GND11
LOS 8
SFP_LOS
J17 2 1 HDR_1X2
SFP Enable
3
GND
Q12 NDS331N 460 mW
1 SFP_TX_DISABLE
2
J20 1 HDR_1X1
GND12
RS1 9 SFP_RS1
VCC3V3
VCC3V3
GND
RS0 7 SFP_RS0
R87 4.7K
HDR_1X3
J38 J39
1
1
2
2
3
3
R88 4.7K
GND 1-2: FULL BW RX 2-3: LOW BW RX
GND 1-2: FULL BW TX 2-3: LOW BW TX
Figure 1-20: SFP+ Module Connector
UG954_c1_19_041113
Table 1-17 lists the SFP+ module RX and TX connections to the SoC.
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Table 1-17: SoC U1 to SFP+ Module Connections
SoC (U1) Pin
Schematic Net name
Y5 Y6 W4 W3 AA18
SFP_RX_N SFP_RX_P SFP_TX_P SFP_TX_N SFP_TX_DISABLE_TRANS
SFP+ Module (P2)
Pin
Name
12
RD_N
13
RD_P
18
TD_P
19
TD_N
3
TX_DISABLE
Table 1-18 lists the SFP+ module control and status connections to the SoC.
Table 1-18: SFP+ Module Control and Status Connections
SFP Control/ Status Signal
SFP_TX_FAULT
Test Point J23
SFP_TX_DISABLE
Jumper 17
SFP_MOD_DETECT Test Point J24
SFP_RS0
Jumper 56
SFP_RS1
Jumper 55
SFP_LOS
Test Point J25
Board Connection
High = Fault Low = Normal operation
Off = SFP Disabled On = SFP enabled High = Module not present Low = Module present Jumper pins 1-2 = Full RX bandwidth Jumper pins 2-3 = Reduced RX bandwidth Jumper pins 1-2 = Full TX bandwidth Jumper pins 2-3 = Reduced TX bandwidth High = Loss of receiver signal Low = Normal operation
For additional information about the enhanced Small Form Factor Pluggable (SFP+) module, see the SFF-8431 specification [Ref 24].
10/100/1000 Mb/s Tri-Speed Ethernet PHY (PS)
[Figure 1-3, callout 15]
The ZC706 evaluation board uses the Marvell Alaska PHY device (88E1116R) at U51 for Ethernet communications at 10 Mb/s, 100 Mb/s, or 1000 Mb/s. The board supports RGMII mode only. The PHY connection to a user-provided Ethernet cable is through a Halo HFJ11-1G01E RJ-45 connector (P3) with built-in magnetics.
On power-up, or on reset, the PHY is configured to operate in RGMII mode with PHY address 0b00111 using the settings shown in Table 1-19. These settings can be overwritten via software commands passed over the MDIO interface.
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Table 1-19: Board Connections for PHY Configuration Pins
U51 Pin
CONFIG (64)
Setting
VCCP1V8
Configuration
PHYAD[1]=1 PHYAD[0]=1
CONFIG1 (1)
PHY_LED0
PHYAD[3]=0 PHYAD[2]=1
GND
ENA_XC=0
PHYAD[4]=0
CONFIG2 (2)
PHY_LED0
ENA_XC=0
PHYAD[4]=1
VCCP1V8
ENA_XC=1
PHYAD[4]=1
GND
RGMII_TX=0 RGMII_RX=0
CONFIG3 (3)
PHY_LED0 PHY_LED1 VCCP1V8
RGMII_TX=0 RGMII_TX=1 RGMII_TX=1
RGMII_RX=1 RGMII_RX=0 RGMII_RX=1
The Ethernet connections from the XC7Z045 SoC at U1 to the 88E1116R PHY device at U51 are listed in Table 1-20.
Table 1-20: Ethernet Connections, XC7Z045 SoC to the PHY Device
XC7Z045 (U1) Pin
Pin Name
PS_MIO53
Bank
501
Pin Number
C18
Schematic Net Name
PHY_MDIO
M88E1116R PHY U51
Pin
Name
45
MDIO
PS_MIO52
501
D19
PHY_MDC
48
MDC
PS_MIO16
501
L19
PHY_TX_CLK
60
TX_CLK
PS_MIO21
501
J19
PHY_TX_CTRL
63
TX_CTRL
PS_MIO20
501
M20
PHY_TXD3
62
TXD3
PS_MIO19
501
PS_MIO18
501
PS_MIO17
501
PS_MIO22
501
PS_MIO27
501
J20
PHY_TXD2
61
K20
PHY_TXD1
59
K21
PHY_TXD0
58
L20
PHY_RX_CLK
53
G20
PHY_RX_CTRL
49
TXD2 TXD1 TXD0 RX_CLK RX_CTRL
PS_MIO26
501
M17
PHY_RXD3
55
RXD3
PS_MIO25
501
G19
PHY_RXD2
54
RXD2
PS_MIO24
501
M19
PHY_RXD1
51
RXD1
PS_MIO23
501
J21
PHY_RXD0
50
RXD0
Ethernet PHY Clock Source
A 25.00 MHz 50 ppm crystal at X1 is the clock source for the 881116R PHY at U51. Figure 1-21 shows the clock source.
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X-Ref Target - Figure 1-21
C495 18 pF 50V NPO
21
X1
25.00 MHz
1
50 PPM
R355 NC 3
4
DNP
2
C494 18 pF 50V
NC 2
1
NPO
21
PHY XTAL OUT PHY XTAL IN
GND
UG954_c1_20_041113
Figure 1-21: Ethernet PHY Clock Source
The data sheet can be obtained under NDA with Marvell. Contact information can be found at their website [Ref 25].
For additional information on the Zynq-7000 SoC device gigabit Ethernet controller, see Zynq-7000 SoC Overview (DS190) and Zynq-7000 SoC Technical Reference Manual (UG585).
USB-to-UART Bridge
[Figure 1-3, callout 17]
The ZC706 evaluation board contains a Silicon Labs CP2103GM USB-to-UART bridge device (U52) which allows a connection to a host computer with a USB port. The USB cable is supplied in the ZC706 evaluation kit (Standard-A end to host computer, Type Mini-B end to ZC706 evaluation board connector J21). The CP2103GM is powered by the USB 5V provided by the host PC when the USB cable is plugged into the USB port on the ZC706 evaluation board.
The CP2013GM TX and RX pins are wired to the UART_1 IP block within the XC7Z045 SoC PS I/O Peripherals set. The XC7Z045 SoC supports the USB-to-UART bridge using two signal pins: Transmit (TX) and Receive (RX).
Silicon Labs provides royalty-free Virtual COM Port (VCP) drivers for the host computer. These drivers permit the CP2103GM USB-to-UART bridge to appear as a COM port to communications application software (for example, TeraTerm or HyperTerm) that runs on the host computer. The VCP device drivers must be installed on the host PC prior to establishing communications with the ZC706 evaluation board.
The USB Connector pin assignments and signal definitions between J21 and U52 are listed in Table 1-21.
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Table 1-21: USB Connector J21 Pin Assignments and Signal Definitions
USB Connector (J21)
Pin
Name
Net Name
Description
1 VBUS
USB_UART_VBUS +5V VBUS Powered
2 D_N 3 D_P
USB_UART_D_N USB_UART_D_P
Bidirectional differential serial data (N-side) Bidirectional differential serial data (P-side)
5 GND
USB_UART_GND
Signal ground
CP2103GM (U52)
Pin Name
7 REGIN 8 VBUS 4 D� 3 D+ 2 GND1 29 CNR_GND
Table 1-22 lists the USB connections between the XC7Z045 SoC PS Bank 501 and the CP2103 UART bridge.
Table 1-22: XC7Z045 SoC to CP2103 Connections
Pin Name
PS_MIO48 PS_MIO49
Bank
501 501
XC7045 SoC (U1)
PIN Function Direction
C19
TX
Output
D18
RX
Input
IOSTANDARD
LVCMOS18 LVCMOS18
Schematic Net Name
USB_UART_RX USB_UART_TX
CP2103GM Device (U52)
PIN Function Direction
24
RXD
Input
25
TXD
Output
Refer to the Silicon Labs website for technical information on the CP2103GM and the VCP drivers [Ref 22].
For additional information on the Zynq-7000 SoC device UART controller, see Zynq-7000 SoC Overview (DS190) and Zynq-7000 SoC Technical Reference Manual (UG585).
HDMI Video Output
[Figure 1-3, callout 18]
The ZC706 evaluation board provides a high-definition multimedia interface (HDMI�) video output using an Analog Devices ADV7511KSTZ-P HDMI transmitter at U53. The HDMI transmitter U53 is connected to the XC7Z045 SoC PL-side banks 12 and 13 and its output is provided on a Molex 500254-1927 HDMI type-A receptacle at P1. The ADV7511 supports 1080P 60Hz, YCbCr 4:4:4 encoding via 24-bit input data mapping.
The ZC706 evaluation board supports the following HDMI device interfaces:
� 24 data lines � Independent VSYNC, HSYNC � Single-ended input CLK � Interrupt Out pin to XC7Z045 SoC
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� I2C � SPDIF Figure 1-22 shows the HDMI codec circuit.
X-Ref Target - Figure 1-22
VCC3V3
VADJ
VCC2V5
R163 2.43 K
1
1/10W
1% 2
HDMI_INT
IIC_SCL_HDMI IIC_SDA_HDMI HDMI_VSYNC HDMI_HSYNC
HDMI_CLK
HDMI_HEAC_C_N
1 R164
2.43 K
1
R165 2.43K 2
1/10W 1%
U53
1/10W 2 1%
ADV7511
45 38 55 56
2 98
INT PD SCL SDA
VSYNC HSYNC
CEC_CLK SPDIF_OUT
50 46
HDMI_SPDIF_OUT
R172 24.9
1/10W 1%
79 CLK
30 HPD
HDMI_PLVDD HDMI_AVDD
To HDMI Connector
HDMI_D35 HDMI_D34 HDMI_D33 HDMI_D32 HDMI_D31 HDMI_D30 HDMI_D28 HDMI_D28
HDMI_D23 HDMI_D22 HDMI_D21 HDMI_D20 HDMI_D19 HDMI_D18 HDMI_D17 HDMI_D16
HDMI_D11 HDMI_D10 HDMI_D9 HDMI_D8 HDMI_D7 HDMI_D6 HDMI_D5 HDMI_D4
HDMI_DE
HDMI_SPDIF
57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 78 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96
D35 D34 D33 D32 D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
PVDD1 PVDD2 PVDD3
21 24 25
AVDD1 AVDD2 AVDD3
29 34 41
DVDD1 DVDD2 DVDD3 DVDD4 DVDD5
76
77
49 19 1
DVDD_3V 47
BGVDD 26
TX0_P TX0_N TX1_P TX1_N TX2_P TX2_N TXC_P TXC_N
36 35 40 39 43 42 33 32
97 DE 10 SPDIF
DDCSDA
54 53
DDCSCL
3 4 5 6 7 8 9
DSD0 DSD1 DSD2 DSD3 DSD4 DSD5 DSD_CLK
HEAC_P HEAC_N
52 51
CEC 48
11 MCLK
12 13 14 15 16 17
I2S0 I2S1 I2S2 I2S3 SCLK LRCLK
1 2 28 R_EXT
R158 887 1/10W 1%
GND1 GND2
99 100
GND3 GND4
18 20
GND5 GND6 GND7 GND8 GND9 GND10 GND11
22 23 27 31 37
44 75
HDMI_AVDD
HDMI_DVDD
HDMI_DVDD_3V HDMI_PLVDD
HDMI_D0_P HDMI_D0_N HDMI_D1_P HDMI_D1_N HDMI_D2_P HDMI_D2_N HDMI_CLK_P HDMI_CLK_N HDMI_DDCSDA HDMI_DDCSCL HDMI_HEAC_P HDMI_HEAC_N HDMI_CEC
GND
GND
Figure 1-22: HDMI Codec Circuit
U50
SIT8102 12.00000 MHZ
50 PPM
4 VCC
OE 1
3 OUT
GND 2
C88
0.1F 25V X5R
1 2
GND
GND
To HDMI Connector
UG954_c1_21_041113
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Table 1-23 lists the connections between the codec and the XC7Z045 SoC.
Table 1-23: XC7Z045 SoC U1 to HDMI Codec Connections (ADV7511)
XC7Z045 (U1) Pin
Net Name
U24 T22 R23 AA25 AE28 T23 AB25 T27 AD26 AB26 AA28 AC26 AE30 Y25 AA29 AD30 Y28 AF28 V22 AA27 U22 N28 V21 AC22 V24 R22 U21 P28 AC23 AC21 AB22
HDMI_R_D4 HDMI_R_D5 HDMI_R_D6 HDMI_R_D7 HDMI_R_D8 HDMI_R_D9 HDMI_R_D10 HDMI_R_D11 HDMI_R_D16 HDMI_R_D17 HDMI_R_D18 HDMI_R_D19 HDMI_R_D20 HDMI_R_D21 HDMI_R_D22 HDMI_R_D23 HDMI_R_D28 HDMI_R_D29 HDMI_R_D30 HDMI_R_D31 HDMI_R_D32 HDMI_R_D33 HDMI_R_D34 HDMI_R_D35 HDMI_R_DE HDMI_R_HSYNC HDMI_R_VSYNC HDMI_R_CLK HDMI_INT HDMI_R_SPDIF HDMI_SPDIF_OUT_LS
I/O Standard
LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25
ADV7511 (U53)
Pin Number
Pin Name
92
D4
91
D5
90
D6
89
D7
88
D8
87
D9
86
D10
85
D11
80
D16
78
D17
74
D18
73
D19
72
D20
71
D21
70
D22
69
D23
64
D28
63
D29
62
D30
61
D31
60
D32
59
D33
58
D34
57
D35
97
DE
98
HSYNC
2
VSYNC
79
CLK
45
INT
10
SPDIF
46
SPDIF_OUT
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Table 1-24 lists the connections between the codec and the HDMI receptacle P1.
Table 1-24: ADV7511 to HDMI Receptacle Connections
ADV7511 (U53)
36 35 40 39 43 42 33 32 54 53 52 51 48
Net Name
HDMI_D0_P HDMI_D0_N HDMI_D1_P HDMI_D1_N HDMI_D2_P HDMI_D2_N HDMI_CLK_P HDMI_CLK_N HDMI_DDCSDA HDMI_DDCSCL HDMI_HEAC_P HDMI_HEAC_N HDMI_CEC
HDMI Receptacle P1 Pin
7 9 4 6 1 3 10 12 16 15 14 19 13
Information about the ADV7511KSTZ-P is available on the Analog Devices website [Ref 26].
For additional information about HDMI IP options, see the LogiCORE IP DisplayPort Product Guide for Vivado Design Suite (PG064).
I2C Bus
[Figure 1-3, callout 20]
The ZC706 evaluation board implements two I2C ports on the XC7Z045 SoC. The PL-side I2C port (IIC_SDA and _SCL_MAIN) is routed to level shifter U87. The PS-side I2C port (PS_SDA and _SCL_MAIN) is routed to level shifter U88. The "output" side of the two level shifters are wired to the common I2C bus IIC_SDA and _SCL_MAIN which is connected to TI Semiconductor PCA9548 1-to-8 channel I2C bus switch (U65). The bus switch can operated at speeds up to 400 kHz.
IMPORTANT: The PCA9548 U65 RESET_B pin 24 is connected to FPGA U1 bank 501 pin F20 via level-shifter U25. FPGA pin F20 net IIC_MUX_RESET_B_LS must be driven High to enable I2C bus transactions with the devices connected to U65.
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The ZC706 evaluation board I2C bus topology is shown in Figure 1-23.
X-Ref Target - Figure 1-23
U1 XC7Z045 AP SoC
PL Bank 10 (2.5V)
U1 XC7Z045 AP SoC
PS Bank 501 (1.8V)
VADJ 2.5V U87
3.3 V
PCA9517 I2C
Level Shifter
IIC_SCL/SDA_MAIN A
B IIC_SDA/SCL_MAIN
VCCMIO_PS 1.8V U88
3.3 V
PCA9517 I2C
Level Shifter
PS_SDA/SCL_MAIN A
B
U65 PCA9548 12C 1-to-8 Bus Switch
CH0 - USRCLK_SFP_SDA/SCL CH1 - IIC_SDA/SCL_HDMI CH2 - EEPROM_IIC_SDA/SCL CH3 - PORT_EXPANDER_SDA/SCL CH4 - IIC_RTC_SDA/SCL CH5 - FMC_HPC_IIC_SDA/SCL CH6 - FMC_LPC_IIC_SDA/SCL CH7 - PMBUS_DATA/CLK
UG954_c1_22_04113
Figure 1-23: I2C Bus Topology
User applications that communicate with devices on one of the downstream I2C buses must first set up a path to the desired bus through the U65 bus switch at I2C address 0x74 (0b01110100). Table 1-25 lists the address for each bus.
Table 1-25: I2C Bus Addresses
Device
I2C Switch Position
PCA9548 8-Channel bus switch
NA
Si570 clock
0
ADV7511 HDMI
1
I2C EEPROM
2
I2C port expander and DDR3 SODIMM
3
I2C real time clock and Si5324 clock
4
FMC HPC
5
FMC LPC
6
UCD90120A pmbus
7
I2C Address
0b1110100 0b1011101 0b1010000 0b0111001 0b1010100 0b0100001 0b1010000 0b0011000 0b1010001 0b1101000 0bxxxxx00 0bxxxxx00 0b1100101
Device
PCA9548 U65 Si570 U37
SFP+ Conn. P2 ADV7511 U53
M24C08 U9 Port Expander U16
DDR3 SODIMM J1
RTC8564JE U26 SI5324 U60 FMC HPC J37 FMC LPC J5
UCD90120A U48
Information about the PCA9548 is available on the TI Semiconductor website at [Ref 27].
For additional information on the Zynq-7000 SoC device I2C controller, see Zynq-7000 SoC Overview (DS190) and Zynq-7000 SoC Technical Reference Manual (UG585).
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Real Time Clock (RTC)
The Epson RTC-8564JE (U26) is an I2C bus interface real-time clock that has a built-in 32.768 KHz oscillator with these features: � Frequency output options: 32.768 KHz, 1,024 Hz, 32 Hz or 1 Hz � Calendar output functions: Year, month, day, weekday, hour, minute and second � Clock counter, alarm and fixed-cycle timer interrupt functions � Back-up battery B3 Panasonic ML621S/DN, 3.0V rechargeable cell Programming information for the RTC-8564JE is available in the RTC-8564JE/NB Application Manual [Ref 30]. Figure 1-24 shows the real time clock circuit.
X-Ref Target - Figure 1-24
VADJ
VCC3V3
VCC2V5
IIC_RTC_SDA IIC_RTC_SCL IIC_RTC_IRQ_1_B
U26
R270 10.0 K
RTC-8564JE
1
0.1W
Real Time Clock
Module
7 SDA
6 SCL
10 INT
VCC 16 CLKOE 15 CLKOUT 14
GND 13
J60 YELLOW
GND
D4 BAT54T1G 30V 400 mW
D5 BAT54T1G 30V 400 mW
D6
BAT54T1G
1 R501 4.7 K
30V 400 mW 0.1WW
2
C350 0.01F 25V X7R
GND
B3 Panasonic ML621S/DN 3V
GND
UG954_c1_23_041113
Figure 1-24: Real Time Clock Circuit Real time clock connections to the XC7Z045 SoC and the PCA9548 8-Channel bus switch are listed in Table 1-26. Refer to Table 1-25 for the RTC I2C address.
Table 1-26: Real Time Clock Connections
RTC-8564JE (U16) Pin Net Name
6
IIC_RTC_SCL
Connects To
U65.11 (PCA9548 SC4)
7
IIC_RTC_SDA
U65.10 (PCA9548 SD4)
10
IIC_RTC_IRQ_1_B U1.AA17 (XC7Z045 SoC PL BANK 10)
Information about the RTC-8564JE is available at the Epson Electronics America website [Ref 31].
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Status and User LEDs
Table 1-27 defines the status and user LEDs.
Table 1-27: Status LEDs
Reference Designator
Net Name
DS1
POR
DS2
FPGA_INIT_B
DS3 DS8 DS9 DS10 DS11 DS13 DS15 DS16 DS20 DS21 DS22 DS23 DS24
DONE GPIO_LED_LEFT GPIO_LED_CENTER GPIO_LED_RIGHT VCCINT VCC1V5_PL VADJ_FPGA VCC3V3_FPGA PS_DDR_LINEAR_PG SODIMM_DDR_LINEAR_PG VCC12_P PWRCTL1_FMC_PG_C2M CTRL1_PWRGOOD
DS25 DS26
U22_FLG LINEAR_POWER_GOOD
DS27 DS28 DS29 DS30 DS35
VCCAUX PHY_LED0 PHY_LED1 PHY_LED2 GPIO_LED_0
LED Color
Description
RED GRN/RED
GRN GRN GRN GRN GRN GRN GRN GRN GRN GRN GRN GRN GRN
RED GRN
GRN GRN GRN GRN GRN
Processor System Power-ON reset is active Green: FPGA initialization was successful Red: FPGA initialization is in progress FPGA bit file download is complete Geographically LEFT located user LED Geographically CENTER located user LED Geographically RIGHT located user LED VCCINT voltage on indicator VCC1V5_PL voltage on indicator VADJ_FPGA voltage on indicator VCC3V3 voltage on indicator VTTDDR_PS voltage on indicator VTTDDR_SODIMM voltage on indicator VCC12_P voltage on indicator FMC power good INDICATOR Power Controller controlled voltage regulator outputs are all their minimum "good" threshold USB 2.0 MOSFET power switch fault MGTAVCC, MGTAVTT, MGTVCCAUX voltage regulator outputs are all their minimum "good" threshold VCCAUX voltage on indicator Ethernet PHY LED0 Ethernet PHY LED1 Ethernet PHY LED2 General Purpose user LED
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Ethernet PHY User LEDs
[Figure 1-3, callout 21]
The three Ethernet PHY user LEDs shown in Figure 1-25 are located near the RJ45 Ethernet jack P3. The on/off state for each LED is software dependent and has no specific meaning at Ethernet PHY power on.
Refer to the Marvell 881116R Alaska Gigabit Ethernet transceiver data sheet for details concerning the use of the Ethernet PHY user LEDs. They are referred to in the data sheet as LED0, LED1, and LED2. See the data sheet and other product information for the Marvell 881116R Alaska Gigabit Ethernet Transceiver [Ref 25].
X-Ref Target - Figure 1-25
VCC3V3
VCC3V3
VCC3V3
388 261 0.1W
DS28
387 261 0.1W
DS29
386 261 0.1W
DS30
3
PHY LED 0 1 2
Q6 NDS331N 460 mW
PHY LED1
3 1
2
Q5 NDS331N 460 mW
3
PHY LED 2 1 2
Q4 NDS331N 460 mW
GND
GND
Figure 1-25: Ethernet PHY User LEDs
GND
UG954_c1_24_041113
User I/O
[Figure 1-3, callout 22�24]
The ZC706 evaluation board provides the following user and general purpose I/O capabilities:
� Four user LEDs (callout 22) � GPIO_LED_LEFT DS8, GPIO_LED_CENTER DS9, GPIO_LED_RIGHT DS10, GPIO_LED_0 DS35
� Three user pushbuttons (callout 23) � GPIO_SW_LEFT SW7, GPIO_SW_CENTER SW9, GPIO_SW_RIGHT SW8
� PL CPU reset pushbutton � PL_CPU_RESET SW13
� 4-position user DIP Switch (callout 24)
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� GPIO_DIP_SW[3:0] SW12 � Two user GPIO male pin headers (callout 26) � 2 x 6 0.1 in. pitch PMOD1 J57 � 2 x 6 0.1 in. pitch PMOD2 J58
User LEDs
[Figure 1-3, callout 22]
The ZC706 evaluation board supports four user LEDs connected to XC7Z045 SoC Banks 11, 33, and 35. Figure 1-26 shows the user LED circuits.
X-Ref Target - Figure 1-26
VCC3V3
VCC3V3
VCC3V3
VCC3V3
2 DS8
1
2 DS9
1
2 DS10
1
2 DS35
1
2
1 3
1 GPIO_LED_ 2
LEFT
R390
2
261
0.1W
1
1% 3
Q7
NDS331N 460 mW
1
GPIO_LED_ 2 CENTER
R391
2
261
0.1W
1
1% 3
Q8
NDS331N 460 mW
1
GPIO_LED_ 2 RIGHT
R392
2
261
0.1W
1
1% 3
Q9
NDS331N 460 mW
1
GPIO_LED_0 2
R544 261 0.1W 1%
Q30 NDS331N 460 mW
GND
GND
GND
GND
UG954_c1_25_041113
Figure 1-26: User LEDs
Table 1-28 lists the user LED connections to XC7Z045 SoC U1.
Table 1-28: User LED Connections to XC7Z045 SoC U1
XC7Z045 SoC (U1) Pin
Y21
Net Name
GPIO_LED_LEFT
I/O Standard
LVCMOS25
G2
GPIO_LED_CENTER
LVCMOS25
W21
GPIO_LED_RIGHT
LVCMOS25
A17
GPIO_LED_0
LVCMOS25
LED Reference
DS8 DS9 DS10 DS35
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User Pushbuttons
[Figure 1-3, callout 23] Figure 1-27 shows the user pushbutton circuits.
X-Ref Target - Figure 1-27
SW7 GPIO_SW_LEFT 4
3
R66 4.7 k 0.1 W 5%
VADJ 1 GPIO_SW_CENTER 2
SW9 4
3
VCC1V5_PL
SW8
1
GPIO_SW_RIGHT 4
2
3
R72 4.7 k 0.1 W 5%
R67 4.7 k 0.1 W 5%
GND
GND
PL_CPU_RESET
SW13 1
3
R516 1.00K 1/16 W 1%
VCC1V5_PL
1 2
GND
GND
Figure 1-27: User Pushbuttons Table 1-29 lists the user pushbutton connections to XC7Z045 SoC U1.
VADJ 1 2
X22404-022719
Table 1-29: User Pushbutton Connections to XC7Z045 SoC U1
XC7Z045 SoC (U1) Pin
AK25
Net Name
GPIO_SW_LEFT
I/O Standard
LVCMOS25
K15
GPIO_SW_CENTER
LVCMOS15
R27
GPIO_SW_RIGHT
LVCMOS25
A8
PL_CPU_RESET
LVCMOS15
Pushbutton Reference
SW7 SW9 SW8 SW13
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GPIO DIP Switch
Figure 1-28 shows the GPIO DIP switch circuit.
X-Ref Target - Figure 1-28
SW12
VADJ
GPIO_DIP_SW0
1
8
GPIO_DIP_SW1
2
7
GPIO_DIP_SW2
3
6
GPIO_DIP_SW3
4
5
1
1
R69 4.7 k
R71
4.7 kSDA02H1SBD
0.1 W
0.1 W
1
R68 2
5% 1
R70 2
5%
4.7 k
4.7 k
0.1 W
0.1 W
5% 2
5% 2
GND
UG954_c1_27_041113
Figure 1-28: GPIO DIP Switch
Table 1-30 lists the GPIO DIP switch connections to XC7Z045 SoC U1.
Table 1-30: GPIO DIP Switch Connections to XC7Z045 SoC at U1
XC7Z045 S0C (U1) Pin
AB17
Net Name
GPIO_DIP_SW0
I/O Standard
LVCMOS25
DIP Switch SW12 Pin
1
AC16
GPIO_DIP_SW1
LVCMOS25
2
AC17
GPIO_DIP_SW2
LVCMOS25
3
AJ13
GPIO_DIP_SW3
LVCMOS25
4
User PMOD GPIO Headers
[Figure 1-3, callout 26]
The ZC706 evaluation board GPIO 2 x 6 male headers J57 and J58 support Digilent Pmod Peripheral Modules. J57 pins (IIC_PMOD_[0:7]) are connected to the TI TCA6416APWR I2C expansion port device U16. J58 pins (PMOD1_[0:7]) are connected to the TI TXS0108E 3.3V-to-VADJ level-shifter U40.
See the Digilent website for information on Digilent Pmod Peripheral Modules [Ref 36].
Information about the TCA641APWR and TXS0108E devices is available at the Texas Instruments website [Ref 27].
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Figure 1-29 shows the user GPIO male pin header circuits.
X-Ref Target - Figure 1-29
VCC3V3_PS
VCC3V3_PS
C97 1 1 C96
0.1UF
0.1UF
10V 2 2 10V
X5R
X5R
IIC_PMOD_0 1 IIC_PMOD_1 3 IIC_PMOD_2 5
IICPMOD_3 7
J57
2 IIC_PMOD_4 4 IIC_PMOD_5 6 IIC_PMOD_6 8 IIC_PMOD_7
R330 1 1 R65
GND
0
4.7
TCA6416APWR
1/10W 5%
22
1/10W 5%
24 VCCP
2 VCCI PORT_EXPANDER_DDR3_SDA 23 SDA PORT_EXPANDER_DDR3_SCL 22 SCL
21 ADDR
3 RESET_B
P00 P01 P02 P03 P04 P05 P06 P07
4 5 6 7 8 9 10 11
IIC_PMOD_0 IIC_PMOD_1 IIC_PMOD_2 IIC_PMOD_3 IIC_PMOD_4 IIC_PMOD_5 IIC_PMOD_6 IIC_PMOD_7
GND
1 R310
DNP DNP 2 DNP
NC 1 INT_B
P10 P11 P12 P13
13 14 15 16
FMC_VADJ_ON_R_B FMC_LPC_PRSNT_M2C_B FMC_HPC_PRSNT_M2C_B FMC_HPC_PG_M2C
12 GND
P14 P15
17 18
XADC_MUX_ADDR0 XADC_MUX_ADDR1
P16 P17
19 20
XADC_MUX_ADDR2 PL_PWR_ON_R
9
10
11
12
HDR_2X6 VCC3V3_PS
GND
PMOD1_0_LS PMOD1_1_LS PMOD1_2_LS PMOD1_3_LS PMOD1_4_LS PMOD1_5_LS PMOD1_6_LS PMOD1_7_LS
GND VADJ
U16 TCA6416APWR
VCC3V3
C105
0.1UF 1
10V 2 X5R
GND
TXS0108E
2 1 3 4 5 6 7 8 9 10
VCCA A1 A2 A3 A4 A5 A6 A7 A8 OE
C104
1 0.1UF 2 10V
X5R
GND
VCCB B1 B2 B3 B4 B5 B6 B7 B8
GND
19 20 18 17 16 15 14 13 12 11
PMOD1_0 PMOD1_1 PMOD1_2 PMOD1_3 PMOD1_4 PMOD1_5 PMOD1_6 PMOD1_7
J58
PMOD1_0 1
2 PMOD1_4
PMOD1_1 3
4 PMOD1_5
PMOD1_2 5 PMOD1_3 7
6 PMOD1_6 8 PMOD1_7
9
10
11
12
GND
HDR_2X6 VCC3V3
GND
U40
TSSOP_20
GND
Figure 1-29: User GPIO Headers
UG954_c1_28_031715
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Table 1-31 lists the GPIO Header connections to XC7Z045 SoC U1.
Table 1-31: GPIO Header Connections to XC7Z045 SoC at U1
TCA6416APWR (U16) PORT: Pin
P00:4 P01:5 P02:6 P03:7 P04:8 P05:9 P06:10 P07:11 XC7Z045 SoC (U1) Pin AJ21 AK21 AB21 AB16 Y20 AA20 AC18 AC19
Net Name
IIC_PMOD_0 IIC_PMOD_1 IIC_PMOD_2 IIC_PMOD_3 IIC_PMOD_4 IIC_PMOD_5 IIC_PMOD_6 IIC_PMOD_7 Net Name PMOD1_0 PMOD1_1 PMOD1_2 PMOD1_3 PMOD1_4 PMOD1_5 PMOD1_6 PMOD1_7
GPIO Header J57 Pin
J57.1 J57.3 J57.5 J57.7 J57.2 J57.4 J57.6 J57.8 GPIO Header J58 Pin J58.1 J58.3 J58.5 J58.7 J58.2 J58.4 J58.6 J58.8
See Zynq-7000 SoC Technical Reference Manual (UG585) for information about the PS PJTAG functionality.
Switches
The ZC706 evaluation board includes a power and a configuration (PL PROG_B) switch:
� Power On/Off slide switch SW1 (callout 27) � SW10 (FPGA_PROG_B), active-Low pushbutton (callout 28) � PS System Reset Pushbuttons
Power On/Off Slide Switch
[Figure 1-3, callout 27]
The ZC706 evaluation board power switch is SW1. Sliding the switch actuator from the Off to On position applies 12V power from J22 a 6-pin mini-fit connector. Green LED DS22 illuminates when the ZC706 evaluation board power is on. See Power Management for details on the onboard power system.
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CAUTION! Do NOT plug a PC ATX power supply 6-pin connector into J22 on the ZC706 Evaluation Board. The ATX 6-pin connector has a different pinout than J22. Connecting an ATX 6-pin connector into J22 will damage the ZC706 Evaluation Board and void the board warranty.
The ZC706 evaluation kit provides the adapter cable shown in Figure 1-30 for powering the ZC706 board from the ATX power supply 4-pin peripheral connector. The Xilinx part number for this cable is 2600304, and is equivalent to Sourcegate Technologies part number AZCBL-WH-1109-RA4. For information on ordering this cable, see [Ref 37].
X-Ref Target - Figure 1-30
To ATX 4-Pin Peripheral Power Connector
To J22 on ZC706 Board
UG954_c1_29_041113
Figure 1-30: ATX Power Supply Adapter Cable Figure 1-31 shows the power connector J22, power switch SW1 and indicator LED DS22.
X-Ref Target - Figure 1-31
J22
12V 12V N/C N/C COM COM
1 4 2 5 3 6
VCC12_P_IN INPUT_GND
SW1 2
5
1 3 4 6
C319 1F 25V
U18 50 1
3
VCC12_P
8 1 2
7 6 5
1 C568 330 F 25V
2 1
2
R171 2.15k .1W 1%
DS22
INPUT_GND
GND
GND
UG954_c1_30_041113
Figure 1-31: Power On/Off Switch SW1
Program_B Pushbutton
[Figure 1-3, callout 28]
Switch SW10 grounds the XC7Z045 SoC PROG_B pin when pressed. This action clears the programmable logic configuration. The FPGA_PROG_B signal is connected to XC7Z045 SoC U1 pin Y9.
See 7 Series FPGAs Configuration User Guide, (UG470) for further details on configuring the 7 series FPGAs.
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Figure 1-32 shows SW10.
X-Ref Target - Figure 1-32
VCC3V3
FPGA_PROG B
R73
4.7 k
0.1 W
5%
SW10
2
4
1
3
GND
UG954_c1_31_041113
Figure 1-32: PROG_B Pushbutton SW10
PS Power-On and System Reset Pushbuttons
Figure 1-33 shows the reset circuitry for the processing system.
X-Ref Target - Figure 1-33
VCC3V3_PS VCC3V3 VCCP1V8 VCCP1V8
R261 10.0 K
0.1W 1%
VCCP1V8
VCCP1V8
R262 10.0 K
0.1W
1%
R263 R176 R177
10.0 K 8.06 K 8.06 K
0.1W 0.1W 0.1W
1%
1%
1%
SW2 2
PS_POR_B 1
SW3 2
PS_SRST_B 1
J7
R256 10.0 K
0.1W
1%
R264 10.0
0.1W
1%
U8
MAX16025
Dual Voltage Monitor
and Sequencer
2 IN1
3 IN2
6 EN1
7 EN2
13 MR_B
4 TOL
9 TH0
8 TH1
VCC 1
RST_B 12 OUT1 11 OUT2 10 CDLY1 16 CDLY2 15
CRESET 14 EPAD 17 GND 5
R149 249 0.1W
1%
DS1
R265 10.0 K
0.1W 1%
R266 10.0 K
0.1W
1%
PS_POR_B_SW
J44 1
2
3
PS_SRST_B_SW
1
J43
PS_POR_B PS_SRST_B
23
C7 0.1 �f
25V X5R
C8 DNP DNP
xxx
C6 5600 pF 25V X5R
GND
GND
GND
C8 = DNP, SRST delay = 35 �S C6 = 5600 pF, POR delay = 22.4 mS
UG954_c1_32_032916
Figure 1-33: PS Power On and System Reset Circuitry
Depressing and then releasing pushbutton SW1 causes PS_POR_B_SW to strobe low.
PS_POR_B: This reset is used to hold the PS in reset until all PS power supplies are at the required voltage levels. It must be held Low through PS power-up. PS_POR_B should be generated by the power supply power-good signal.
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Depressing and then releasing pushbutton SW3 causes PS_SRST_B_SW (connected to the XC7Z045 SoC U1 dedicated PS Bank 500 pin D21) to strobe low.
PS_SRST_B: This reset is used to force a system reset. It can be tied or pulled High, and can be High during the PS supply power ramps.
See Zynq-7000 SoC Technical Reference Manual (UG585) for information concerning the resets.
FPGA Mezzanine (FMC) Card Interface
[Figure 1-3, callout 30 and 31]
The ZC706 evaluation board supports the VITA 57.1 FPGA Mezzanine Card (FMC) specification by providing subset implementations of the high pin count (HPC) connector at J37 and low pin count (LPC) version at J5. Both connectors use a 10 x 40 form factor. The HPC connector is populated with 400 pins, while the LPC connector is partially populated with 160 pins. The connectors are keyed so that a mezzanine card, when installed in either of these FMC connectors on the ZC706 evaluation board, faces away from the ZC706 board.
Connector Type:
� Samtec SEAF Series, 1.27 mm (0.050 in) pitch. Mates with SEAM series connector
More information about SEAF series connectors is available at the Samtec website [Ref 32]. More information about the VITA 57.1 FMC specification is available at the VITA FMC Marketing Alliance website [Ref 38].
HPC Connector J37
[Figure 1-3, callout 30]
The 400-pin HPC connector defined by the FMC specification (Figure B-2, page 93) provides connectivity for up to:
� 160 single-ended or 80 differential user-defined signals � 10 GTX transceivers � 2 GTX clocks � 4 differential clocks � 159 ground and 15 power connections
The connections between the HPC connector at J37 and SoC U1 (Table 1-32) implements a subset of this connectivity:
� 34 differential user-defined pairs (34 LA pairs, LA00�LA33)
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� 8 GTX transceivers � 2 GTX clocks � 2 differential clocks � 159 ground and 15 power connections The ZC706 board VADJ voltage for the J37 and J5 connectors is determined by the FMC VADJ power sequencing logic described in the Power Management, page 79.
Note: HPC FMC (J37) GA0 = GA1 = 0 = GND. Table 1-32 shows the J37 HPC FMC to SoC U1 connections.
Table 1-32: J37 HPC FMC Connections to XC7Z045 SoC U1
J37 FMC HPC Pin
A2 A3 A6 A7 A10 A11 A14 A15 A18 A19 A22 A23 A26 A27 A30 A31 A34 A35 A38 A39 C2 C3 C6 C7 C10 C11
Net Name
FMC_HPC_DP1_M2C_P FMC_HPC_DP1_M2C_N FMC_HPC_DP2_M2C_P FMC_HPC_DP2_M2C_N FMC_HPC_DP3_M2C_P FMC_HPC_DP3_M2C_N FMC_HPC_DP4_M2C_P FMC_HPC_DP4_M2C_N FMC_HPC_DP5_M2C_P FMC_HPC_DP5_M2C_N FMC_HPC_DP1_C2M_P FMC_HPC_DP1_C2M_N FMC_HPC_DP2_C2M_P FMC_HPC_DP2_C2M_N FMC_HPC_DP3_C2M_P FMC_HPC_DP3_C2M_N FMC_HPC_DP4_C2M_P FMC_HPC_DP4_C2M_N FMC_HPC_DP5_C2M_P FMC_HPC_DP5_C2M_N FMC_HPC_DP0_C2M_P FMC_HPC_DP0_C2M_N FMC_HPC_DP0_M2C_P FMC_HPC_DP0_M2C_N
FMC_HPC_LA06_P FMC_HPC_LA06_N
I/O Standard
XC7Z045 (U1) Pin
(1)
AJ8
(1)
AJ7
(1)
AG8
(1)
AG7
(1)
AE8
(1)
AE7
(1)
AH6
(1)
AH5
(1)
AG4
(1)
AG3
(1)
AK6
(1)
AK5
(1)
AJ4
(1)
AJ3
(1)
AK2
(1)
AK1
(1)
AH2
(1)
AH1
(1)
AF2
(1)
AF1
(1)
AK10
(1)
AK9
(1)
AH10
(1)
AH9
LVCMOS25 AG22
LVCMOS25 AH22
J37 FMC HPC Pin
B1 B4 B5 B8 B9 B12 B13 B16 B17 B20 B21 B24 B25 B28 B29 B32 B33 B36 B37 B40 D1 D4 D5 D8 D9 D11
Net Name
NC NC NC NC NC FMC_HPC_DP7_M2C_P FMC_HPC_DP7_M2C_N FMC_HPC_DP6_M2C_P FMC_HPC_DP6_M2C_N FMC_HPC_GBTCLK1_M2C_P FMC_HPC_GBTCLK1_M2C_N NC NC NC NC FMC_HPC_DP7_C2M_P FMC_HPC_DP7_C2M_N FMC_HPC_DP6_C2M_P FMC_HPC_DP6_C2M_N NC PWRCTL1_FMC_PG_C2M FMC_HPC_GBTCLK0_M2C_P FMC_HPC_GBTCLK0_M2C_N FMC_HPC_LA01_CC_P FMC_HPC_LA01_CC_N FMC_HPC_LA05_P
I/O Standard
XC7Z045 (U1) Pin
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
(1)
AD6
(1)
AD5
(1)
AF6
(1)
AF5
(1)
AA8
(1)
AA7
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
(1)
AD2
(1)
AD1
(1)
AE4
(1)
AE3
N/A
N/A
LVCMOS25 AB20
(1)
AD10
(1)
AD9
LVCMOS25 AG21
LVCMOS25 AH21
LVCMOS25 AH23
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Table 1-32: J37 HPC FMC Connections to XC7Z045 SoC U1 (Cont'd)
J37 FMC HPC Pin
C14 C15 C18 C19 C22 C23 C26 C27 C30 C31 C34 C35 C37 C39
Net Name
FMC_HPC_LA10_P FMC_HPC_LA10_N FMC_HPC_LA14_P FMC_HPC_LA14_N FMC_HPC_LA18_CC_P FMC_HPC_LA18_CC_N FMC_HPC_LA27_P FMC_HPC_LA27_N FMC_HPC_IIC_SCL FMC_HPC_IIC_SDA
GA0 = 0 = GND VCC12_P VCC12_P VCC3V3
I/O Standard
LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25
N/A N/A N/A N/A N/A N/A
XC7Z045 (U1) Pin
AG24 AG25 AC24 AD24 W25 W26 V28 V29 U65.13 U65.12 N/A N/A N/A N/A
J37 FMC HPC Pin
D12 D14 D15 D17 D18 D20 D21 D23 D24 D26 D27 D29 D30 D31 D32 D33 D34 D35 D36 D38 D40
Net Name
FMC_HPC_LA05_N FMC_HPC_LA09_P FMC_HPC_LA09_N FMC_HPC_LA13_P FMC_HPC_LA13_N FMC_HPC_LA17_CC_P FMC_HPC_LA17_CC_N FMC_HPC_LA23_P FMC_HPC_LA23_N FMC_HPC_LA26_P FMC_HPC_LA26_N FMC_HPC_TCK_BUF
FMC_TDI_BUF FMC_HPC_TDO_FMC_LPC_TDI
VCC3V3 FMC_HPC_TMS_BUF
NC GA1 = 0 = GND
VCC3V3 VCC3V3 VCC3V3
I/O Standard
XC7Z045 (U1) Pin
LVCMOS25 AH24
LVCMOS25 AD21
LVCMOS25 AE21
LVCMOS25 AA22
LVCMOS25 AA23
LVCMOS25
V23
LVCMOS25
W24
LVCMOS25
P25
LVCMOS25
P26
LVCMOS25
R28
LVCMOS25
T28
N/A
U23.15
N/A
U23.18
N/A
U32.2
N/A
N/A
N/A
U23.17
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
E2
NC
E3
NC
E6
NC
E7
NC
E9
NC
E10
NC
E12
NC
E13
NC
E15
NC
E16
NC
E18
NC
E19
NC
E21
NC
E22
NC
E24
NC
E25
NC
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
N/A
F1
N/A
F4
N/A
F5
N/A
F7
N/A
F8
N/A
F10
N/A
F11
N/A
F13
N/A
F14
N/A
F16
N/A
F17
N/A
F19
N/A
F20
N/A
F22
N/A
F23
N/A
F25
FMC_HPC_PG_M2C NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
U16.16 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
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Table 1-32: J37 HPC FMC Connections to XC7Z045 SoC U1 (Cont'd)
J37 FMC HPC Pin
E27 E28 E30 E31 E33 E34 E36 E37 E39
Net Name
NC NC NC NC NC NC NC NC VADJ
I/O Standard
XC7Z045 (U1) Pin
J37 FMC HPC Pin
N/A
N/A
F26
N/A
N/A
F28
N/A
N/A
F29
N/A
N/A
F31
N/A
N/A
F32
N/A
N/A
F34
N/A
N/A
F35
N/A
N/A
F37
N/A
N/A
F38
F40
Net Name
NC NC NC NC NC NC NC NC NC VADJ
I/O Standard
XC7Z045 (U1) Pin
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
G2
FMC_HPC_CLK1_M2C_P LVCMOS25
U26
H1
G3
FMC_HPC_CLK1_M2C_N LVCMOS25
U27
H2
G6
FMC_HPC_LA00_CC_P LVCMOS25
AF20
H4
G7
FMC_HPC_LA00_CC_N LVCMOS25 AG20
H5
G9
FMC_HPC_LA03_P
LVCMOS25 AH19
H7
G10
FMC_HPC_LA03_N
LVCMOS25
AJ19
H8
G12
FMC_HPC_LA08_P
LVCMOS25
AF19
H10
G13
FMC_HPC_LA08_N
LVCMOS25 AG19
H11
G15
FMC_HPC_LA12_P
LVCMOS25
AF23
H13
G16
FMC_HPC_LA12_N
LVCMOS25
AF24
H14
G18
FMC_HPC_LA16_P
LVCMOS25 AA24
H16
G19
FMC_HPC_LA16_N
LVCMOS25
AB24
H17
G21
FMC_HPC_LA20_P
LVCMOS25
U25
H19
G22
FMC_HPC_LA20_N
LVCMOS25
V26
H20
G24
FMC_HPC_LA22_P
LVCMOS25
V27
H22
G25
FMC_HPC_LA22_N
LVCMOS25
W28
H23
G27
FMC_HPC_LA25_P
LVCMOS25
T29
H25
G28
FMC_HPC_LA25_N
LVCMOS25
U29
H26
G30
FMC_HPC_LA29_P
LVCMOS25
R25
H28
G31
FMC_HPC_LA29_N
LVCMOS25
R26
H29
G33
FMC_HPC_LA31_P
LVCMOS25
N29
H31
G34
FMC_HPC_LA31_N
LVCMOS25
P29
H32
G36
FMC_HPC_LA33_P
LVCMOS25
N26
H34
G37
FMC_HPC_LA33_N
LVCMOS25
N27
H35
G39
VADJ
N/A
N/A
H37
H38
H40
NC FMC_HPC_PRSNT_M2C_B FMC_HPC_CLK0_M2C_P FMC_HPC_CLK0_M2C_N
FMC_HPC_LA02_P FMC_HPC_LA02_N FMC_HPC_LA04_P FMC_HPC_LA04_N FMC_HPC_LA07_P FMC_HPC_LA07_N FMC_HPC_LA11_P FMC_HPC_LA11_N FMC_HPC_LA15_P FMC_HPC_LA15_N FMC_HPC_LA19_P FMC_HPC_LA19_N FMC_HPC_LA21_P FMC_HPC_LA21_N FMC_HPC_LA24_P FMC_HPC_LA24_N FMC_HPC_LA28_P FMC_HPC_LA28_N FMC_HPC_LA30_P FMC_HPC_LA30_N FMC_HPC_LA32_P FMC_HPC_LA32_N
VADJ
N/A N/A LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 N/A
N/A U16.15 AE22 AF22 AK17 AK18
AJ20 AK20 AJ23 AJ24 AD23 AE23 Y22 Y23 T24 T25 W29 W30 T30 U30 P30 R30 P23 P24 P21 R21 N/A
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Table 1-32: J37 HPC FMC Connections to XC7Z045 SoC U1 (Cont'd)
J37 FMC HPC Pin
Net Name
I/O Standard
XC7Z045 (U1) Pin
J37 FMC HPC Pin
Net Name
I/O Standard
XC7Z045 (U1) Pin
J2
NC
N/A
N/A
K1
NC
J3
NC
N/A
N/A
K4
NC
J6
NC
N/A
N/A
K5
NC
J7
NC
N/A
N/A
K7
NC
J9
NC
N/A
N/A
K8
NC
J10
NC
N/A
N/A
K10
NC
J12
NC
N/A
N/A
K11
NC
J13
NC
N/A
N/A
K13
NC
J15
NC
N/A
N/A
K14
NC
J16
NC
N/A
N/A
K16
NC
J18
NC
N/A
N/A
K17
NC
J19
NC
N/A
N/A
K19
NC
J21
NC
N/A
N/A
K20
NC
J22
NC
N/A
N/A
K22
NC
J24
NC
N/A
N/A
K23
NC
J25
NC
N/A
N/A
K25
NC
J27
NC
N/A
N/A
K26
NC
J28
NC
N/A
N/A
K28
NC
J30
NC
N/A
N/A
K29
NC
J31
NC
N/A
N/A
K31
NC
J33
NC
N/A
N/A
K32
NC
J34
NC
N/A
N/A
K34
NC
J36
NC
N/A
N/A
K35
NC
J37
NC
N/A
N/A
K37
NC
J39
NC
N/A
N/A
K38
NC
K40
NC
Notes: 1. No I/O standards are associated with MGT connections.
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
LPC Connector J5
[Figure 1-3, callout 31]
The 160-pin LPC connector defined by the FMC specification (Figure B-1, page 92) provides connectivity for up to:
� 68 single-ended or 34 differential user-defined signals � 1 GTX transceiver
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� 1 GTX clock � 2 differential clocks � 61 ground and 10 power connections
The connections between the HPC connector at J5 and SoC U1 implements a subset of this connectivity:
� 34 differential user-defined pairs (34 LA pairs, LA00�LA33) � 1 GTX transceiver � 1 GTX clock � 2 differential clocks � 61 ground and 9 power connections Note: LPC FMC (J5) GA0 = GA1 = 0 = GND.
Table 1-33 shows the FMC LPC connections between J5 and XC7Z045 SoC U1.
Table 1-33: J5 LPC FMC Connections to SoC U1
J5 FMC LPC Pin
C2 C3 C6 C7 C10 C11 C14 C15 C18 C19 C22 C23 C26 C27 C30 C31 C34 C35 C37 C39
Net Name
FMC_LPC_DP0_C2M_P FMC_LPC_DP0_C2M_N FMC_LPC_DP0_M2C_P FMC_LPC_DP0_M2C_N
FMC_LPC_LA06_P FMC_LPC_LA06_N FMC_LPC_LA10_P FMC_LPC_LA10_N FMC_LPC_LA14_P FMC_LPC_LA14_N FMC_LPC_LA18_CC_P FMC_LPC_LA18_CC_N FMC_LPC_LA27_P FMC_LPC_LA27_N FMC_LPC_IIC_SCL FMC_LPC_IIC_SDA GA0 = 0 = GND
VCC12_P VCC12_P VCC3V3
I/O Standard
XC7Z045 (U1) Pin
J5 FMC LPC Pin
Net Name
I/O Standard
XC7Z045 (U1) Pin
(1)
AB2
D1
PWRCTL1_FMC_PG_C2M
LVCMOS25 AB20
(1)
AB1
D4
FMC_LPC_GBTCLK0_M2C_P
(1)
U8
(1)
AC4
D5
FMC_LPC_GBTCLK0_M2C_N
(1)
U7
(1)
AC3
D8
FMC_LPC_LA01_CC_P
LVCMOS25 AF15
LVCMOS25 AB12
D9
FMC_LPC_LA01_CC_N
LVCMOS25 AG15
LVCMOS25 AC12 D11
FMC_LPC_LA05_P
LVCMOS25 AE16
LVCMOS25 AC14 D12
FMC_LPC_LA05_N
LVCMOS25 AE15
LVCMOS25 AC13 D14
FMC_LPC_LA09_P
LVCMOS25 AH14
LVCMOS25 AF18 D15
FMC_LPC_LA09_N
LVCMOS25 AH13
LVCMOS25 AF17 D17
FMC_LPC_LA13_P
LVCMOS25 AH17
LVCMOS25 AE27 D18
FMC_LPC_LA13_N
LVCMOS25 AH16
LVCMOS25 AF27 D20
FMC_LPC_LA17_CC_P
LVCMOS25 AB27
LVCMOS25 AJ28
D21
FMC_LPC_LA17_CC_N
LVCMOS25 AC27
LVCMOS25 AJ29
D23
FMC_LPC_LA23_P
LVCMOS25 AJ26
N/A
U65.15 D24
FMC_LPC_LA23_N
LVCMOS25 AK26
N/A
U65.14 D26
FMC_LPC_LA26_P
LVCMOS25 AJ30
N/A
N/A
D27
FMC_LPC_LA26_N
LVCMOS25 AK30
N/A
N/A
D29
FMC_LPC_TCK_BUF
N/A
U23.14
N/A
N/A
D30 FMC_HPC_TDO_FMC_LPC_TDI
N/A
U31.1
N/A
N/A
D31
FMC_LPC_TDO_FPGA_TDI
N/A
U31.2
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Table 1-33: J5 LPC FMC Connections to SoC U1 (Cont'd)
J5 FMC LPC Pin
Net Name
I/O Standard
XC7Z045 (U1) Pin
J5 FMC LPC Pin
D32
D33
D34
D35
D36
D38
D40
Net Name
VCC3V3 FMC_LPC_TMS_BUF
NC GA1 = 0 = GND
VCC3V3 VCC3V3 VCC3V3
I/O Standard
XC7Z045 (U1) Pin
N/A
N/A
N/A
U23.16
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
G2
FMC_LPC_CLK1_M2C_P LVCMOS25 AC28
H1
G3
FMC_LPC_CLK1_M2C_N LVCMOS25 AD28
H2
G6
FMC_LPC_LA00_CC_P
LVCMOS25 AE13
H4
G7
FMC_LPC_LA00_CC_N
LVCMOS25 AF13
H5
G9
FMC_LPC_LA03_P
LVCMOS25 AG12
H7
G10
FMC_LPC_LA03_N
LVCMOS25 AH12
H8
G12
FMC_LPC_LA08_P
LVCMOS25 AD14 H10
G13
FMC_LPC_LA08_N
LVCMOS25 AD13 H11
G15
FMC_LPC_LA12_P
LVCMOS25 AD16 H13
G16
FMC_LPC_LA12_N
LVCMOS25 AD15 H14
G18
FMC_LPC_LA16_P
LVCMOS25 AE18 H16
G19
FMC_LPC_LA16_N
LVCMOS25 AE17 H17
G21
FMC_LPC_LA20_P
LVCMOS25 AG26 H19
G22
FMC_LPC_LA20_N
LVCMOS25 AG27 H20
G24
FMC_LPC_LA22_P
LVCMOS25 AK27 H22
G25
FMC_LPC_LA22_N
LVCMOS25 AK28 H23
G27
FMC_LPC_LA25_P
LVCMOS25 AF29 H25
G28
FMC_LPC_LA25_N
LVCMOS25 AG29 H26
G30
FMC_LPC_LA29_P
LVCMOS25 AE25 H28
G31
FMC_LPC_LA29_N
LVCMOS25 AF25 H29
G33
FMC_LPC_LA31_P
LVCMOS25 AC29 H31
G34
FMC_LPC_LA31_N
LVCMOS25 AD29 H32
G36
FMC_LPC_LA33_P
LVCMOS25 Y30
H34
G37
FMC_LPC_LA33_N
LVCMOS25 AA30 H35
G39
VADJ
N/A
N/A
H37
H38
H40
Notes: 1. No I/O standards are associated with MGT connections.
NC FMC_LPC_PRSNT_M2C_B FMC_LPC_CLK0_M2C_P FMC_LPC_CLK0_M2C_N
FMC_LPC_LA02_P FMC_LPC_LA02_N FMC_LPC_LA04_P FMC_LPC_LA04_N FMC_LPC_LA07_P FMC_LPC_LA07_N FMC_LPC_LA11_P FMC_LPC_LA11_N FMC_LPC_LA15_P FMC_LPC_LA15_N FMC_LPC_LA19_P FMC_LPC_LA19_N FMC_LPC_LA21_P FMC_LPC_LA21_N FMC_LPC_LA24_P FMC_LPC_LA24_N FMC_LPC_LA28_P FMC_LPC_LA28_N FMC_LPC_LA30_P FMC_LPC_LA30_N FMC_LPC_LA32_P FMC_LPC_LA32_N
VADJ
LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25
N/A
U16.14 AG17 AG16 AE12 AF12 AJ15 AK15 AA15 AA14 AJ16 AK16 AB15 AB14 AH26 AH27 AH28 AH29 AF30 AG30 AD25 AE26 AB29 AB30 Y26 Y27 N/A
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ZC706 Board Power System
The ZC706 board hosts a power system based on the Texas Instruments (TI) UCD90120A power supply sequencer and monitor, and the LMZ31500 and LMZ31700 family voltage regulators.
UCD90120A Description
The UCD90120A is a 12-rail PMBus/I2C addressable power-supply sequencer and monitor. The device integrates a 12-bit ADC for monitoring up to 12 power-supply voltage inputs. Twenty-six GPIO pins can be used for power supply enables, power-on reset signals, external interrupts, cascading, or other system functions. Twelve of these pins offer pulse width modulation (PWM) functionality. Using these pins, the UCD90120A offers support for margining and general purpose PWM functions.
The TI Fusion Digital PowerTM designer software is provided for device configuration. This PC-based graphical user interface (GUI) offers an intuitive interface for configuring, storing, and monitoring all system operating parameters.
LMZ31500 and LMZ31700 Family Regulator Description
The LMZ31520 SIMPLE SWITCHER� power module is a step-down DC-DC solution capable of driving up to 20A load. The LMZ31520 module can accept an input voltage rail between 3V and 14.5V and deliver an adjustable and highly accurate output voltage as low as 0.6V.
The LMZ31506 SIMPLE SWITCHER� power module is a step-down DC-DC solution capable of driving up to 6A load. The LMZ31506 module can accept an input voltage rail between 3V and 14.5V and deliver an adjustable and highly accurate output voltage as low as 0.6V. In older documentation this regulator was known as the TI TPS84621.
The LMZ31710 SIMPLE SWITCHER� power module is a step-down DC-DC solution capable of driving up to 10A load. The LMZ31710 module can accept an input voltage rail between 4.5V and 17V and deliver an adjustable and highly accurate output voltage as low as 0.6V.
These modules only requires two external resistors plus external capacitors to provide a complete power solution. These modules offer the following protection features: thermal shutdown, programmable input under-voltage lockout, output over-voltage protection, short-circuits protection, output current limit, and each allows startup into a pre-biased output.
The LMZ31710 sync input allows synchronization over the 200 kHz to 1,200 kHz switching frequency range and up to six modules can be connected in parallel for higher load currents.
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Table 1-34 shows the ZC706 board TI power system configuration for controller U48.
Table 1-34: ZC706 TI Controller U48 Power System Configuration
Sequencer
U48 PMBus Addr 101 5 Rails
Schematic Page
Page Contents
49 UCD90120A
Net Name
50 Addr 101, Rail 1 VCCINT
51 Addr 101, Rail 2 VCCAUX, VCC1V8
52 Addr 101, Rail 3 VCC1V5_PL
53 Addr 101, Rail 4 VADJ_FPGA,VADJ
54 Addr 101, Rail 5 VCC3V3_FPGA,VCC3V3
Regulator Type, U# Voltage Current
LMZ31520 U42(1) LMZ31710 U98(2) LMZ31506 U85(3) LMZ31506 U86(2) LMZ31710 U15(4)
1.0V
16A
1.8V
10A
1.5V
6A
2.5V
6A
3.3V
10A
Notes:
ZC706 boards prior to Rev. 2.0 implemented different voltage regulators for VCCINT, VCCAUX/VCC1V8, VCC1V5_PL, VADJ_FPGA/VADJ and VCC3V3_FPGA/VCC3V3. Refer to UG954 v1.3 and earlier, and to the schematic for the particular version of the ZC706 board prior to Rev. 2.0. Notes on ZC706 boards prior to Rev. 2.0:
1. VCCINT is implemented utilizing 2xLMZ22008 8A components (U42, U43) in parallel which provides 16A capability. 2. The 1.8V rails are supplied from a LMZ22010 10A component (U98). 3. VCC1V5_PL and the 2.5V rails are supplied from TPS84621 6A components (U85, U86). 4. The 3.3V rails are supplied from a LMZ22010 10A component (U15).
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Figure 1-34 shows the power system for UCD90120A U48 controller.
X-Ref Target - Figure 1-34
UCD90120A Controller U48
GPIO (out) Rail Enable PWM Margin
FPWM (out) ADC (in) Current Sense ADC (in) Voltage Sense
GPIO (out) Low Pwr Select
GPIO (out) FPWM (out)
ADC (in) ADC (in)
Rail Enable PWM Margin Current Sense Voltage Sense
GPIO (out) FPWM (out)
ADC (in) ADC (in)
Rail Enable PWM Margin Current Sense Voltage Sense
GPIO (out) FPWM (out)
ADC (in) ADC (in)
Rail Enable PWM Margin Current Sense Voltage Sense
VCCINT 1.0V Nom.
12V Input
Filter
LMZ31520
Vin
U42 Bulk Filter Caps
EN Vfb
FB
Vout
Low Power || Radj
Low = 1.0V (Default)
High = 0.9V Input VCCAUX 1.8V Nom.
Filter
LMZ31710
Vin
U98
Bulk Filter Caps
EN Vfb
FB
Vout
Input VCC1V5_PL 1.5V Nom.
Filter
LMZ31506
Vin
U85 Bulk Filter Caps
EN Vfb
FB
Vout
Input VADJ_FPGA 2.5V Nom.
Filter
LMZ31506
Vin
U86 Bulk Filter Caps
EN Vfb
FB
Vout
FMC_ADJ_SEL[1:0]
[ 1 0 ] 00 01 10 11
GPIO (out)
FMC_ADJ_SEL[1:0]
U66
I0B
I1B I2B
YB
I3B
S[1:0]
GPIO (out) FPWM (out)
ADC (in) ADC (in)
Rail Enable PWM Margin Current Sense Voltage Sense
Dual 4-to-1 Mux
Input VCC3V3 FPGA 3.3V Nom.
Filter
LMZ31710
Vin
U15
Bulk Filter Caps
EN Vfb
FB
Vout
VCCINT 1.0V Sense Connected at Point of Load
VCC1V8 1.8V VCCAUX 1.8V Sense Connected at Point of Load
VCC1V5_PL 1.5V Sense Connected at Point of Load
VADDJ 2.5V VADJ_FPGA 2.5V Sense Connected at Point of Load
VCC3V3 3.3V VCC3V3 FPGA 3.3V Sense Connected at Point of Load
Notes: 1. Capacitors labeled Cf are bulk filter capacitors. 2. Voltage Sense is connected a point of load.
Figure 1-34: ZC706 TI UCD90120A Controller U48 Power System
UG954_c1_33_041615
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The LMZ31520, LMZ31506, and LMZ31710 adjustable voltage regulators have their output voltage set through an external resistor. The regulator topology on the ZC706 board permits the TI UCD90120A module to monitor rail voltage and current. Voltage margining at +5% and -5% is also implemented.
Each voltage regulator's external VOUT setting resistor is calculated and implemented as if the regulator is stand-alone. The TI UCD90120A module has two ADC inputs allocated per voltage rail, one input for the remote voltage sense connection, the other for the current sense resistor op amp output voltage connection. The TI UCD90120A ADC full scale input is 2.5V. The remote voltage feedback is scaled to approximately 2V if it exceeds 2V, that is, the VCCO_VADJ rail for the 2.5V and 3.3V modes, and the FPGA_3V3 rail also at 3.3V are resistor-attenuated to scale the remotely sensed voltage at a ratio of 0.606 to give approximately 2V at the ADC input pin for a 3.3V remote sense value. Rails below 2V are not scaled.
Each rail's current sense op amp has its gain set to provide approximately 2V maximum at the TI UCD90120A ADC input pin when the rail current is at its expected maximum current level, as can be seen in the U48 controller power system figure (Figure 1-34).
The TI UCD90120A module has an assignable group of GPIO pins with PWM capability. Each controller "channel" has a PWM GPIO pin wired to the associated voltage regulator VADJ pin. The external VOUT setting resistor is also wired to this pin. The PWM GPIO pin is configured in 3-state mode. This pin is not driven unless a Margin command is executed. The Margin command is available within the TI Fusion Digital PowerTM designer software.
During the margin-High or Low operation, the PWM GPIO pin drives a voltage into the voltage regulator VADJ pin, which causes a slight voltage change resulting in the regulator VOUT moving to the margin +5% or -5% voltage commanded.
XADC Power System Measurement
The ZC706 board XADC interface includes power system voltage and current measuring capability. The VCCINT and VCCAUX rail voltages are measured using the XADC internal voltage measurement capability. Other rails are measured through an external Analog Devices ADG707BRU multiplexer U6. Each rail has a separate TI INA333 op amp strapped across its series current sense resistor Kelvin terminals. This op amp has its gain adjusted to give approximately 1V at the expected full scale current value for the rail.
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Figure 1-35 shows the XADC external MUX block diagram.
X-Ref Target - Figure 1-35
Notes: 1. _XADC_P/N = Remote Voltage Sense 2. _XADC_CS_P/N = Current Sense From OP Amp
VCC3V3_FPGA_SENSE_P VCC3V3_FPGA_XADC_P
3.01K
U1
ADIP L13
AD1N K13
XC7Z045
Bank 35
U16
P14 17 A0 P15 18 A1 P16 19 A2
49.9 10PF 49.9
TCA6416APWR 12C Port Expander
U6
ADG707BRU
S1A/B VCCINT_XADC_CS_P/N
S2A/B VCCAUX_XADC_CS_P/N
S3A/B VCC1V5_PL_XADC_P/N
VCC1V5_PL_XADC_CS_P/N
DA
S4A/B
VADJ_FPGA_XADC_P/N
DB
S5A/B
VADJ_FPGA_XADC_CS_P/N S6A/B
VCC3V3_PL_XADC_P/N S7A/B
A[2:0]
VCC3V3_PL_XADC_CS_P/N S8A/B
Scaled to 0.75V
VCC3V3_FPGA_SENSE_N
1.00K
VCC3V3_FPGA_SENSE_P
GND
VCC3V3_FPGA_XADC_P
VADJ 2.5V Scaled to 0.625V
VCC3V3_FPGA_SENSE_N
3.01K 1.00K
VCC3V3_FPGA_SENSE_P
GND
VCC3V3_FPGA_XADC_P
3.3 Scaled to 0.825V
VCC3V3_FPGA_SENSE_N
3.01K 1.00K
GND
UG954_c1_34_041113
Figure 1-35: XADC External MUX Block Diagram
See Table 1-35 which lists the ZC706 XADC power system voltage and current measurement details for the external MUX U6.
Table 1-35: XADC Measurements through MUX U6
Meas. Type
V I
Rail Name
VCCINT VCCINT CS
Current Range
Isense Op Amp
Reference Designator
Gain
Vo Range
NA
NA
NA
NA
0A-8A
U69
20
0V-0.8V
V
VCCAUX
NA
NA
I
VCCAUX CS
0A-4A
U68
NA
NA
50
0V-1V
V
VCC1V5_PL
NA VCC1V5_PL REMOTE SENSE DIVIDED
TO DELIVER 0.75V ON
VCC1V5_PL_XADC_P
I
VCC1V5_PL CS 0A-2A
U67
100
0V-1V
Schematic Net Name
XADC INTERNAL VCCINT_XADC_CS_P VCCINT_XADC_CS_N
XADC INTERNAL VCCAUX_XADC_CS_P VCCAUX_XADC_CS_N VCC1V5_PL_XADC_P VCC1V5_PL_SENSE_N
8-to-1 MUX U6
Pin Pin MUX A[2:0] Num Name
NA NA
NA
19 S1A
000
11 S1B
NA NA
NA
20 S2A
001
10 S2B
21 S3A
010
9 S3B
VCC1V5_PL_XADC_CS_P
22 S4A
011
VCC1V5_PL_XADC_CS_N
8 S4B
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Table 1-35: XADC Measurements through MUX U6 (Cont'd)
Meas. Type
V
I
Rail Name VADJ_FPGA VADJ_FPGA CS
Current Range
Isense Op Amp
Reference Designator
Gain
Vo Range
NA
VADJ_FPGA 2.5V REMOTE SENSE
DIVIDED TO DELIVER 0.625V ON
VADJ_FPGA_XADC_P
0A-2A
U70
100
0V-1V
V
VCC3V3_FPGA
NA
VCC3V3_FPGA REMOTE SENSE
DIVIDED TO DELIVER 0.825V ON
VCC3V3_FPGA_XADC_P
I
VCC3V3_FPGA CS 0A-2A
U97
100
0V-1V
Schematic Net Name
VADJ_FPGA_XADC_P VADJ_FPGA_SENSE_N
8-to-1 MUX U6
Pin Pin MUX A[2:0] Num Name
23 S5A
100
7 S5B
VADJ_FPGA_XADC_CS_P 24 S6A
101
VADJ_FPGA_XADC_CS_N
6 S6B
VCC3V3_FPGA_XADC_P
25 S7A
110
VCC3V3_FPGA_SENSE_N
5 S7B
VCC3V3_FPGA_XADC_CS_P 26 S8A
111
VCC3V3_FPGA_XADC_CS_N 4 S8B
Power Management
[Figure 1-3, callout 32]
The ZC706 board uses power regulators and a PMBus-compliant system controller from Texas Instruments to supply core and auxiliary voltages. The Texas Instruments Fusion Digital Power graphical user interface is used to monitor the voltage and current levels of the board power modules.
The PCB layout and power system design meet the recommended criteria described in Zynq-7000 SoC PCB Design and Pin Planning Guide (UG933).
The ZC706 evaluation board power distribution diagram is shown in Figure 1-36.
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X-Ref Target - Figure 1-36
12V PWR Jack J22
p. 48
Power Controller 1
PMBus 0x65
U48
p. 49
Note: Page numbers reference the pages on schematic 0381513
Switching Module
VCCINT 1.00V @ 16A
U42
p. 50
Switching Module
VCC1V8/VCCAUX 1.8V @ 10A
U98
p. 51
Switching Module
VCC1V5_PL 1.5V @ 6A
U85
p. 52
Switching Module
VADJ/VADJ _FPGA 2.5V @ 6A
U96
p. 53
Linear Regulator
MGTAVCC 1.0V @ 3A
U93
p. 57
Linear Regulator
MGTAVTT 1.2V @ 3A
U94
p. 57
Switching Module
VCC3V3/VCC3V3_FPGA 3.3V @ 10A
U15
p. 54
Switching Dual
VCCPINT 1.0V @ 1.5A
U104
p. 55
Switching Dual
VCC1V5_PS 1.5V @ 2.5A
U104
p. 55
Switching Dual
VCCP1V8 1.8V @ 1.5A
U105
p. 55
Switching Dual
VCC3V3_PS 3.3V @ 2.5A
U105
p. 55
Switching Regulator
VCC5V0 5.0V @ 2A
U44
p. 56
Linear Regulator
MGTVCCAUX 1.8V @ 3A
U95
p. 57
Linear Regulator
VCC2V5 2.5V @ 1.5A
U19
p. 57
Linear Regulator
VCCAUX_IO 2.0V @ 3A
U92
p. 57
Source/Sink Regulator
VTTDDR_PL 0.75V @ 3A
U28
p. 56
Source/Sink Regulator
VTTDDR_PS 0.75V @ 0.5A (3A Max)
U27
p. 56
Linear Regulator
V33D_CTL1 3.3V @ 0.25A
U20
p. 49
UG954_c1_35_031615
Figure 1-36: Onboard Power Regulators
The ZC706 evaluation board uses power regulators and PMBus compliant PWM system controllers from Texas Instruments to supply the core and auxiliary voltages listed in Table 1-36.
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Table 1-36: Onboard Power System Devices
Device Type
Reference Designator
Description
UCD90120A
U48
PMBus Controller, PMBus Addr = 101
LMZ31520RLG(1)(6)
U42
16A 0.6 - 3.6V Adj. Switching Regulator
LMZ31710RVQ(7)
U98
10A 0.6V - 5.5V Adj. Switching Regulator
LMZ31506RUQ
U85
6A 0.6V - 5.5V Adj. Switching Regulator
LMZ31506RUQ
U86
6A 0.6V - 5.5V Adj. Switching Regulator
LMZ31710RVQ(7)
U15
10A 0.6V - 5.5V Adj. Switching Regulator
Power Rail Net Name
VCCINT(2) VCCAUX (3) VCC1V5_PL VADJ_FPGA (4) VCC3V3_FPGA (5)
Power Rail Schematic
Voltage
Page
49
1.00V
50
1.80V
51
1.50V
52
2.50V
53
3.30V
54
TPS54291PWP (Dual Output)
U104
2.5A 0.8V - 10V Adj. Switching Regulator 2.5A 0.8V - 10V Adj. Switching Regulator
VCCPINT VCC1V5_PS
1.00V
55
1.50V
55
TPS54291PWP (Dual Output)
U105
2.5A 0.8V - 10V Adj. Switching Regulator 2.5A 0.8V - 10V Adj. Switching Regulator
VCCP1V8 VCC3V3_PS
1.80V
55
3.30V
55
TPS51200DR
U27
3A Push/Pull Tracking Regulator
VTTDDR_PS
0.75V
56
TPS51200DR
U28
3A Push/Pull Tracking Regulator
VTTDDR_SODIMM 0.75V
56
TPS74901RGW
U92
3A 0.8V - 3.6V Adj. Linear Regulator
VCCAUX_IO
2.00V
57
TPS74901RGW
U93
3A 0.8V - 3.6V Adj. Linear Regulator
MGTAVCC
1.00V
57
TPS74901RGW
U94
3A 0.8V - 3.6V Adj. Linear Regulator
MGTAVTT
1.20V
57
TPS74901RGW
U95
3A 0.8V - 3.6V Adj. Linear Regulator
MGTVCCAUX
1.80V
57
TL1963A
U19
1.5A 1.21V - 3.3V Adj. Linear Regulator
VCC2V5
2.50V
57
TPS79433
U20
0.25A 3.3V Fixed Linear Regulator
V33D_CTL1
3.30V
49
LMZ31704RVQ(8)
U44
2A 0.6V - 5.5V Adj. Switching Regulator
VCC5V0
5.00V
56
Notes: 1. VCCINT max. current is 16A 2. VCCBRAM 1.0V is also sourced from the Vccint rail 3. VCC1V8 1.80V is also sourced from the Vccaux rail 4. VADJ (1.80V/2.50V/3.30V) for the FMC connectors is also sourced from the Vadj_fpga rail 5. VCC3V3 3.30V is also sourced from the Vcc3v3_fpga rail 6. Paralleled dual LMZ22008TZ (U42/U43) 8A 0.8V - 6V Adj. Switching Regulators on ZC706 board versions prior to Rev. 2.0 7. LMZ22010TZ (U98 VCCAUX, U15 VCC3V3_FPGA) 10A 0.8 - 6V Adj. Switching Regulators on ZC706 board versions prior to Rev.
2.0 8. LMZ12002TZ U44 2A 0.8 - 6V Adj. Switching Regulator on ZC706 board versions prior to Rev. 2.0
VADJ Voltage Control
The VADJ rail is set to 2.5V. When the ZC706 evaluation board is powered on, the state of the FMC_VADJ_ON_B signal wired to header J18 is sampled by the TI UCD90120A controller U48. If a jumper is installed on J18 signal FMC_VADJ_ON_B is held Low, and the TI controller U48 energizes the VADJ rail at power on.
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Because the rail turn on decision is made at power on time based on the presence of the J18 jumper, removing the jumper at J18 after the board is powered up does not affect the 2.5V power delivered to the VADJ rail and it remains on.
A jumper installed at J18 is the default setting.
In this mode the user can control when to turn on VADJ and to which voltage level (1.8V, 2.5V, 3.3V). With VADJ off the XC7Z045 SoC still configures and has access to the TI controller PMBUS along with the FMC_VADJ_ON_B signal. The combination of these allows the user to develop code to command the VADJ rail to be set to something other than the default setting of 2.5V. Once the new VADJ voltage level has been programmed into TI controller U48, the FMC_VADJ_ON_B signal can be driven low by the user logic and the VADJ rail comes up at the new VADJ voltage level. Installing a jumper at J18 after a ZC706 board powers up in the VADJ off (no jumper on J18 at ZC706 power up) mode turns on the VADJ rail.
The FMC_VADJ_ON_B signal is connected to the TCA6416APWR I2C port expander U16 pin 13 (see Figure 1-29). The XC7Z045 SoC is thus able to drive the FMC_VADJ_ON_B signal by writing to the I�C port expander U16.
The I2C port expander IIC_PORT_EXPANDER SDA/SCL bus is wired to the PCA9548ARGER I2C U65 bus switch (see I2C Bus, page 55).
Documentation describing PMBUS programming for the UCD90120A power controller is available at the website [Ref 27].
SoC Programmable Logic (PL) Voltage Control
All PL and PS power rails are enabled by default. When the ZC706 board is powered on, the state of the PL_PWR_ON signal wired to 2-pin header J66 is sampled by the TI UCD90120A controller U48. If a jumper is not installed on J66, signal PL_PWR_ON is held high, and the TI controller U48 energizes all the PL and PS power rails.
Because the rail turn on decision is made at power on time based on the presence of the J66 jumper, installing the jumper at J66 after the board is powered up does not affect power delivered to the any PS or PL rails, all rails remain on.
A jumper not installed at J66 is the default setting.
If a jumper is installed on J66 when the ZC706 board is powered on, signal PL_PWR_ON is held low, and the ZC706 board does not energize the PL side power rails at power on.
Monitoring Voltage and Current
Voltage and current monitoring and control are available for selected power rails through Texas Instruments' Fusion Digital Power Designer graphical user interface. The onboard TI power controller (U48 at address 101) is accessed through the PMBus connector J4, which is provided for use with the TI USB Interface Adapter PMBus pod (TI part number EVM USB-TO-GPIO), which can be ordered from the Texas Instruments website [Ref 28] and
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associated TI Fusion Digital Power Designer GUI (downloadable from the TI site [Ref 29]. This is the simplest and most convenient way to monitor the voltage and current values for the power rails listed in Table 1-37.
In the table, the Power Good (PG) On Threshold is the setpoint at or above which the particular rail is deemed "good". The PG Off Threshold is the setpoint at or below which the particular rail is no longer deemed "good". The controller internally OR's these per rail PG conditions together and drives an output PG pin high only if all active rail PG states are "good". The On and Off Delay and parameters are relative to when the board power on-off slide switch SW12 is turned on and off.
Table 1-37 Power Rail Specifications for UCD90120A PMBus controller at Address 101 defines the voltage and current values for each power rail controlled by the UCD90120A U48.
IMPORTANT: In Table 1-37, the values defined in the Shutdown columns are the voltage and current thresholds that cause the regulator to shut down if the value is exceeded.
Table 1-37: Power Rail Specifications for UCD90120A PMBus Controller at Address 101
Device
UCD90120A U48
Address
101d 1 2 3 4 5
Rail
VCCINT VCCAUX VCC1V5_PL VADJ_FPGA VCC3V3_FPGA
Nominal Voltage
Power Good
On
Power Good Off
Turn On Delay (ms)(2)
1.000 0.900 0.850 0.0
1.800 1.620 1.530 5.0
1.500 1.350 1.275 5.0
2.500 2.250 2.125 5.0
3.300 2.970 2.805 5.0
Turn Off Delay (ms)
25.0 20.0 10.0 5.0 15.0
Shutdown(1)
Over Over Voltage Current
1.150 11.50
2.070
6.91
1.725
3.50
2.875
3.50
3.795
6.91
Notes: 1. The values defined in these columns are the voltage and current thresholds that cause the regulator to shut down if the value
is exceeded. 2. See Table 1-39 for rail turn on dependency details.
The ZC706 power system rail turn on timing is not strictly controlled through the Turn On Delay shown in Table 1-37. The Table 1-37 Turn On Delay delay values are applied after the preceding rail has reached 90% of its nominal voltage. See Table 1-38 for rail turn on dependency details.
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Table 1-38: Power Rail Sequence On Dependencies for UCD90120A PMBus Controller at Address 101
Device
Address
1 2
Rail
VCCINT VCCAUX
Nominal Voltage
1.000
1.800
Turn On Order
1 2
Turn On Timing
Turn on at board power-on 5ms after VCCINT hits 90%
UCD90120A 101d 5 VCC3V3_FPGA
3.300
3
5ms after VCCAUX hits 90%
3 VCC1V5_PL
1.500
4
5ms after VCC3V3 hits 90%
4 VADJ_FPGA
2.500
5
5ms after VCC1V5_PL hits 90%
Cooling Fan
The XC7Z045 SoC cooling fan connector is shown in Figure 1-37.
X-Ref Target - Figure 1-37
VCC12_P
Keyed Fan Header
22_11_2032 1
2
1 R279
10.0K 1/10W 2 1%
3
1 2
R278
J61 VADJ
10.0K
1 D1
1/10W
DL4148 1%
100V
2 460MW
R369 1
1.00K
1/16W 1% 2
2 4
Q1
1 R190
4.75K 1/10W 2 1%
SM FAN PWM
1
1.3W NDT3055L
3
SM FAN TACH
2 D2
MM3Z2V7B 2.7V 1 460MW
GND
GND
UG954_c1_36_073013
Figure 1-37: Cooling Fan Circuit
When VADJ is modified from a default of 2.5V to 1.8V or a lower VADJ setting, the SoC U1 cooling fan turns off. Transistor Q1 is used to switch on the fan and has a max VGS of 2V, hence the fan is not guaranteed to work at 1.8V or lower VADJ, setting. See [Ref 16].
The fan turns on when the ZC706 is powered up due to pull-up resistor R369. The SM_FAN_PWM and SM_FAN_TACH signals are wired to XC7Z045 SoC U1 pins AB19 and
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AA19 respectively, enabling the user to implement their own fan speed control IP in the SoC PL logic.
More information about the power system components used by the ZC706 evaluation board are available from the Texas Instruments digital power website [Ref 33].
XADC Analog-to-Digital Converter
[Figure 1-3, callout 33]
The XC7Z045 SoC provides an Analog Front End XADC block. The XADC block includes a dual 12-bit, 1 MSPS Analog-to-Digital Convertor (ADC) and on-chip sensors. See 7 Series FPGAs and Zynq-7000 SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide (UG480) for details on the capabilities of the analog front end. Figure 1-38 shows the XADC block diagram.
X-Ref Target - Figure 1-38
U1
XC7Z020 AP SoC
VCCADC
GNDADC
VCCAUX Ferrite Bead
To J54 XADC_VCC
100 nF Close to Package Pins
XADC_AGND
1 J53
XADC_VCC Header J40
2
1.8V 150 mV max
U14
3
ADP123
Out
In
Gnd
10 F
10 F
XADC_VCC5V0 To Header J63 Ferrite Bead VCC5V0
J14
XADC_AGND
XADC_AGND
To Header
J63
To Header J63 U38
XADC_VREF (1.25V) REF3012
Out
In
1 J52
Gnd
VREFP XADC_VREFP 2
10 F
1 J54 2
3 XADC_VCC
Dual Use IO (Analog/Digital)
100
1 nF
100 100
1 nF
100
VREFN VAUX0P VP VAUX0N VN VAUX8P DXP VAUX8N DXN
100 nF 3
Close to Package Pins
XADC_AGND
Ferrite Bead
100 1 nF 100
XADC_AGND
To Header
J63
Star Grid Connection
J12
J13 GND
UG8954_c1_37_041715
Figure 1-38: XADC Block Diagram
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Feature Descriptions
The ZC706 evaluation board supports both the internal XC7Z045 SoC sensor measurements and the external measurement capabilities of the XADC. Internal measurements of the die temperature, VCCINT, VCCAUX, and VCCBRAM are available.
Jumper J52 can be used to select either an external voltage reference (VREF) or on-chip voltage reference for the analog-to-digital converter.
For external measurements an XADC header (J63) is provided. This header can be used to provide analog inputs to the XC7Z045 SoC's dedicated VP/VN channel, and to the VAUXP[0]/VAUXN[0], VAUXP[8]/VAUXN[8] auxiliary analog input channels. Simultaneous sampling of Channel 0 and Channel 8 is supported.
A user-provided analog signal multiplexer card can be used to sample additional external analog inputs using the 4 GPIO pins available on the XADC header as multiplexer address lines. Figure 1-39 shows the XADC header connections.
X-Ref Target - Figure 1-39
XADC_VCC5V0 VCC1V5_PL
XADC_VN XADC_VAUX0P
XADC_VAUX8N XADC_DXP XADC_VREF
XADC_GPIO_1 XADC_GPIO_3
J63
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
XADC_VP
XADC_VAUX0N XADC_VAUX8P
XADC_DXN XADC_VCC_HEADER
XADC_GPIO_0 XADC_GPIO_2
XADC_AGND
GND XADC_AGND
UG954_c1_38_041113
Figure 1-39: XADC Header (J63)
Table 1-39 describes the XADC header J40 pin functions.
Table 1-39: XADC Header J63 Pinout
Net Name
VN, VP XADC_VAUX0P, N
J63 Pin Number
1, 2
3, 6
Description
Dedicated analog input channel for the XADC. Auxiliary analog input channel 0. Also supports use as I/O inputs when anti alias capacitor is not present.
XADC_VAUX8N, P
7, 8
Auxiliary analog input channel 8. Also supports use as I/O inputs when anti alias capacitor is not present.
DXP, DXN
9, 12
Access to thermal diode.
XADC_AGND
4, 5, 10 Analog ground reference.
XADC_VREF XADC_VCC5V0 XADC_VCC_HEADER
VCC1V5_PL
11
1.25V reference from the board.
13
Filtered 5V supply from board.
14
Analog 1.8V supply for XADC.
15
VCCO supply for bank which is the source of DIO pins.
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Feature Descriptions
Table 1-39: XADC Header J63 Pinout (Cont'd)
Net Name
GND
J63 Pin Number
16
Description
Digital Ground (board) Reference
XADC_GPIO_3, 2, 1, 0
19, 20, 17, 18
Digital I/O. These pins should come from the same bank. These IOs should not be shared with other functions because they are required to support three-state operation.
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Appendix A
Default Switch and Jumper Settings
The default switch and jumper settings for the ZC706 evaluation board are provided in this appendix.
Switches
[Figure 1-3, callout 24]
Default switch settings are listed in Table A-1. The locations of the ZC706 jumper headers called out in Table A-2 are shown in Figure A-1.
Table A-1: Default Switch Settings
Switch
Function
SW1 SW4
SW11
SW12
Board main power On-Off Slide Switch 2-pole SPST DIP Switch, JTAG mode select signals JTAG_SEL_[1:2] 5-pole DPDT DIP Switch, PS Boot Mode select signals MIO[6:2]_SELECT 4-pole SPST DIP Switch, user signals GPIO_DIP_SW[0:3], poles [1:4]
Default
Selects
OFF
Delivered in OFF position
10
JTAG = cable connector J3
Figure 1-3 Callout
27
34
All Down JTAG flat cable header J3
29
All OFF All = 0 (4.7K p/d to GND)
24
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Jumpers
Jumpers
[Figure 1-3, callout 24] Default jumper positions are listed in Table A-2.
Table A-2: Default Jumper Settings
Jumper Callout
Jumper
Function
Default Jumper Position
Option Selected
HDR_1 X 2
1
J6
SoC U1 Bank 0 CFGBVS pin V9 logic 0/1 Select
(call out #1 applies to this, too):
J65 J65 is an INIT_B (pin 1) and DONE (pin 2) test
header
OPEN OPEN
CFGBVS pin V9 = 1 N/A
2
J7
U8 MAX16025 POR Device Reset MR_B pin 13 logic
OPEN
U8 MR_B pin 13 = 1
0/1 Select
3
J8
JTAG Header J62 pin 2 can be connected to 3.3V
OPEN
J62 pin 2 is NC
4
J9
U51 Ethernet PHY CONFIG2 pin 2 1K pull-down to
1-2
U51 pin 2 CONFIG2 = 0
logic 0 (GND)
5
J10 U12 USB3320 2.0 Host/OTG or Device Select
Header
1-2
HOST source VBUS power
(from U22)
6
J11 U12 USB3320 2.0 RESET Header
OPEN
U12 not held in RESET
7
J12 U38 REF3012 VREF XADC_AGND-to-GND L3
inductor bypass
OPEN
L3 not bypassed
8
J13 U38 REF3012 VREF XADC_AGND-to-GND Select
Header
1-2
XADC_AGND connected to
GND
9
J14 XADC circuit VCC5V0 sources XADC_VCC5V0 Select
1-2
XADC_VCC5V0 = filtered
Header
(L1) VCC5V0
10
J15 ARM PJTAG Header J64 pin 2 can be connected to
OPEN
J64 pin 2 is NC
VADJ
11
J17 SPF+ P2 pin 3 SFP_TX_DISABLE_TRANS logic 0/1
Select Header
OPEN
SPF+ P2 SFP TX is enabled (P2 pin 3 = 1)
12
J18 FMC_VADJ_ON_B Select Header
1-2
FMC VADJ enabled (U48
UCD90120A pin 37 = logic
0)
13
J19 PCIe� Lane Width Select Header
3-4
4-Lane PCIe selected
14
J66 PL_PWR_ON Header
OPEN
PL Power enabled (U48 UCD90120A pin 24 = logic 1)
15
J69 XADC Power System Vccint CS OpAmp U69 Gain
Select Header
OPEN
U69 Current Sense OpAmp Gain = 10
16
J70 MIO Select Header MIO2 (Note: DIP SW11 pole 1
affects this signal)
1-2
QSPI0_IO0 = MIO2_SELECT
17
J71 MIO Select Header MIO3 (Note: DIP SW11 pole 2
affects this signal)
1-2
QSPI0_IO1 = MIO3_SELECT
Schematic 0381513
Page
3 3 15 16
31 31 35 35 35 39 41 49
42 49
45 15 15
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Jumpers
Table A-2: Default Jumper Settings (Cont'd)
Jumper Callout
18 19 20
21 22 23 24 25
26 27 28 29 30 31 32 33 34
Jumper
J72 J73 J74
J43 J44 J45 J46 J47
J48 J49 J50 J51 J52 J53 J54 J55 J56
Function
Default Jumper Position
Option Selected
MIO Select Header MIO4 (Note: DIP SW11 pole 3 affects this signal) MIO Select Header MIO5 (Note: DIP SW11 pole 4 affects this signal) MIO Select Header MIO6 (Note: DIP SW11 pole 5 affects this signal)
HDR_1 X 3 PS_SRST_B Select Header
PS_POR_B Select Header
U51 Ethernet PHY CONFIG3 pin 3 1K pull-up to 1.8V or 1 K pull-down to GND Select Header U51 Ethernet PHY CONFIG2 pin 2 tie to 1.8V or LED0 Select Header U51 Ethernet PHY CONFIG3 pin 3 LED1 or LED0 Select Header
U12 USB3320 2.0 MODE Select Header USB 2.0 Micro-B connector J2 ID pin 4 function Select Header USB_VBUS_SEL 1uF/120 uF capacitor to GND Select Header USB 2.0 Micro-B connector J2 ID shield pins connection Select Header XADC_VREFP source Select Header XADC_VCC source Select Header U38 REF3012 VREF Vin Select Header
SPF+ P2 SFP_RS1 BW Select Header SPF+ P2 SFP_RS0 BW Select Header
1-2 1-2 1-2
1-2 1-2 1-2 OPEN OPEN
2-3 1-2 2-3 1-2 1-2 1-2 2-3 2-3 2-3
QSPI0_IO4 = MIO2_SELECT
QSPI0_IO5 = MIO2_SELECT
QSPI0_CLK = MIO6_SELECT
PS_SRST_B = PS_SRST_B_SW (MAX16025 U8 pin 10) PS_POR_B = PS_POR_B_SW (MAX16025 U8 pin 11) U51 pin 3 CONFIG3 = 1 (p/u to 1.8V) J9 sets U51 pin 2 CONFIG2 condition No connection to LED0 or LED1, J45 sets U51 pin 3 CONFIG3 condition HOST/OTG Mode selected J2 ID pin 4 connected to USB3320 U12 pin 23 ID USB_VBUS_SEL net has 120 uF to GND J2 shield pins to GND
XADC_VREFP = XADC_VREF XADC_VCC = VCCAUX 1.8V U38 powered by XADC_VCC (U14 1.85V) LOW BW TX selected LOW BW RX selected
Schematic 0381513
Page
15 15 15
15 15 29 29 29
31 31 31 31 35 35 35 41 41
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X-Ref Target - Figure A-1
Jumpers
34
33
3
11
24 25 23
4
21
22
16
10
17
18
19
20
15 2
32 13
7
1
8
31 9 30
Figure A-1: ZC706 Jumper Header Locations
12 14
5
29
26 28
6
27
UG954_aA_01_042415
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Appendix B
VITA 57.1 FMC Connector Pinouts
Figure B-1 shows the pinout of the FPGA mezzanine card (FMC) low pin count (LPC) connector defined by the VITA 57.1 FMC specification. For a description of how the ZC706 evaluation board implements the FMC specification, see FPGA Mezzanine (FMC) Card Interface, page 67 and LPC Connector J5, page 71.
X-Ref Target - Figure B-1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
K
J
H
G
F
E
D
C
B
A
NC
NC
VREF_A_M2C
GND
NC
NC
PG_C2M
GND
NC
NC
NC
NC
PRSNT_M2C_L CLK1_M2C_P
NC
NC
GND
DP0_C2M_P
NC
NC
NC
NC
GND
CLK1_M2C_N
NC
NC
GND
DP0_C2M_N
NC
NC
NC
NC
CLK0_M2C_P
GND
NC
NC
GBTCLK0_M2C_P
GND
NC
NC
NC
NC
CLK0_M2C_N
GND
NC
NC
GBTCLK0_M2C_N
GND
NC
NC
NC
NC
GND
LA00_P_CC
NC
NC
GND
DP0_M2C_P
NC
NC
NC
NC
LA02_P
LA00_N_CC
NC
NC
GND
DP0_M2C_N
NC
NC
NC
NC
LA02_N
GND
NC
NC
LA01_P_CC
GND
NC
NC
NC
NC
GND
LA03_P
NC
NC
LA01_N_CC
GND
NC
NC
NC
NC
LA04_P
LA03_N
NC
NC
GND
LA06_P
NC
NC
NC
NC
LA04_N
GND
NC
NC
LA05_P
LA06_N
NC
NC
NC
NC
GND
LA08_P
NC
NC
LA05_N
GND
NC
NC
NC
NC
LA07_P
LA08_N
NC
NC
GND
GND
NC
NC
NC
NC
LA07_N
GND
NC
NC
LA09_P
LA10_P
NC
NC
NC
NC
GND
LA12_P
NC
NC
LA09_N
LA10_N
NC
NC
NC
NC
LA11_P
LA12_N
NC
NC
GND
GND
NC
NC
NC
NC
LA11_N
GND
NC
NC
LA13_P
GND
NC
NC
NC
NC
GND
LA16_P
NC
NC
LA13_N
LA14_P
NC
NC
NC
NC
LA15_P
LA16_N
NC
NC
GND
LA14_N
NC
NC
NC
NC
LA15_N
GND
NC
NC
LA17_P_CC
GND
NC
NC
NC
NC
GND
LA20_P
NC
NC
LA17_N_CC
GND
NC
NC
NC
NC
LA19_P
LA20_N
NC
NC
GND
LA18_P_CC
NC
NC
NC
NC
LA19_N
GND
NC
NC
LA23_P
LA18_N_CC
NC
NC
NC
NC
GND
LA22_P
NC
NC
LA23_N
GND
NC
NC
NC
NC
LA21_P
LA22_N
NC
NC
GND
GND
NC
NC
NC
NC
LA21_N
GND
NC
NC
LA26_P
LA27_P
NC
NC
NC
NC
GND
LA25_P
NC
NC
LA26_N
LA27_N
NC
NC
NC
NC
LA24_P
LA25_N
NC
NC
GND
GND
NC
NC
NC
NC
LA24_N
GND
NC
NC
TCK
GND
NC
NC
NC
NC
GND
LA29_P
NC
NC
TDI
SCL
NC
NC
NC
NC
LA28_P
LA29_N
NC
NC
TDO
SDA
NC
NC
NC
NC
LA28_N
GND
NC
NC
3P3VAUX
GND
NC
NC
NC
NC
GND
LA31_P
NC
NC
TMS
GND
NC
NC
NC
NC
LA30_P
LA31_N
NC
NC
TRST_L
GA0
NC
NC
NC
NC
LA30_N
GND
NC
NC
GA1
12P0V
NC
NC
NC
NC
GND
LA33_P
NC
NC
3P3V
GND
NC
NC
NC
NC
LA32_P
LA33_N
NC
NC
GND
12P0V
NC
NC
NC
NC
LA32_N
GND
NC
NC
3P3V
GND
NC
NC
NC
NC
GND
VADJ
NC
NC
GND
3P3V
NC
NC
NC
NC
VADJ
GND
NC
NC
3P3V
GND
NC
NC
UG954_aB_01_100112
Figure B-1: FMC LPC Connector Pinout
Figure B-2 shows the pinout of the FPGA mezzanine card (FMC) high pin count (HPC) connector defined by the VITA 57.1 FMC specification. For a description of how the ZC706 evaluation board implements the FMC specification, see FPGA Mezzanine (FMC) Card Interface, page 67 and HPC Connector J37, page 67.
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X-Ref Target - Figure B-2
K
1 VREF_B_M2C
2
GND
3
GND
4 CLK2_M2C_P
5 CLK2_M2C_N
6
GND
7
HA02_P
8
HA02_N
9
GND
10
HA06_P
11
HA06_N
12
GND
13
HA10_P
14
HA10_N
15
GND
16
HA17_P_CC
17
HA17_N_CC
18
GND
19
HA21_P
20
HA21_N
21
GND
22
HA23_P
23
HA23_N
24
GND
25
HB00_P_CC
26
HB00_N_CC
27
GND
28
HB06_P_CC
29
HB06_N_CC
30
GND
31
HB10_P
32
HB10_N
33
GND
34
HB14_P
35
HB14_N
36
GND
37
HB17_P_CC
38
HB17_N_CC
39
GND
40
VIO_B_M2C
J GND CLK3_M2C_P CLK3_M2C_N GND GND HA03_P HA03_N GND HA07_P HA07_N GND HA11_P HA11_N GND HA14_P HA14_N GND HA18_P HA18_N GND HA22_P HA22_N GND HB01_P HB01_N GND HB07_P HB07_N GND HB11_P HB11_N GND HB15_P HB15_N GND HB18_P HB18_N GND VIO_B_M2C GND
H VREF_A_M2C PRSNT_M2C_L
GND CLK0_M2C_P CLK0_M2C_N
GND LA02_P LA02_N
GND LA04_P LA04_N
GND LA07_P LA07_N
GND LA11_P LA11_N
GND LA15_P LA15_N
GND LA19_P LA19_N
GND LA21_P LA21_N
GND LA24_P LA24_N
GND LA28_P LA28_N
GND LA30_P LA30_N
GND LA32_P LA32_N
GND VADJ
G GND CLK1_M2C_P CLK1_M2C_N GND GND LA00_P_CC LA00_N_CC GND LA03_P LA03_N GND LA08_P LA08_N GND LA12_P LA12_N GND LA16_P LA16_N GND LA20_P LA20_N GND LA22_P LA22_N GND LA25_P LA25_N GND LA29_P LA29_N GND LA31_P LA31_N GND LA33_P LA33_N GND VADJ GND
F PG_M2C
GND GND HA00_P_CC HA00_N_CC GND HA04_P HA04_N GND HA08_P HA08_N GND HA12_P HA12_N GND HA15_P HA15_N GND HA19_P HA19_N GND HB02_P HB02_N GND HB04_P HB04_N GND HB08_P HB08_N GND HB12_P HB12_N GND HB16_P HB16_N GND HB20_P HB20_N GND VADJ
E GND HA01_P_CC HA01_N_CC GND GND HA05_P HA05_N GND HA09_P HA09_N GND HA13_P HA13_N GND HA16_P HA16_N GND HA20_P HA20_N GND HB03_P HB03_N GND HB05_P HB05_N GND HB09_P HB09_N GND HB13_P HB13_N GND HB19_P HB19_N GND HB21_P HB21_N GND VADJ GND
D PG_C2M
GND GND GBTCLK0_M2C_P GBTCLK0_M2C_N GND GND LA01_P_CC LA01_N_CC GND LA05_P LA05_N GND LA09_P LA09_N GND LA13_P LA13_N GND LA17_P_CC LA17_N_CC GND LA23_P LA23_N GND LA26_P LA26_N GND TCK TDI TDO 3P3VAUX TMS TRST_L GA1 3P3V GND 3P3V GND 3P3V
C GND DP0_C2M_P DP0_C2M_N GND GND DP0_M2C_P DP0_M2C_N GND GND LA06_P LA06_N GND GND LA10_P LA10_N GND GND LA14_P LA14_N GND GND LA18_P_CC LA18_N_CC GND GND LA27_P LA27_N GND GND SCL SDA GND GND GA0 12P0V GND 12P0V GND 3P3V GND
B RES1 GND GND DP9_M2C_P DP9_M2C_N GND GND DP8_M2C_P DP8_M2C_N GND GND DP7_M2C_P DP7_M2C_N GND GND DP6_M2C_P DP6_M2C_N GND GND GBTCLK1_M2C_P GBTCLK1_M2C_N GND GND DP9_C2M_P DP9_C2M_N GND GND DP8_C2M_P DP8_C2M_N GND GND DP7_C2M_P DP7_C2M_N GND GND DP6_C2M_P DP6_C2M_N GND GND RES0
A GND DP1_M2C_P DP1_M2C_N GND GND DP2_M2C_P DP2_M2C_N GND GND DP3_M2C_P DP3_M2C_N GND GND DP4_M2C_P DP4_M2C_N GND GND DP5_M2C_P DP5_M2C_N GND GND DP1_C2M_P DP1_C2M_N GND GND DP2_C2M_P DP2_C2M_N GND GND DP3_C2M_P DP3_C2M_N GND GND DP4_C2M_P DP4_C2M_N GND GND DP5_C2M_P DP5_C2M_N GND
UG954_aB_02_100112
Figure B-2: FMC HPC Connector Pinout
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Appendix C
Xilinx Constraints File
The Xilinx Design Constraints (XDC) template for the ZC706 board provides for designs targeting the ZC706 evaluation board. Net names in the constraints correlate with net names on the latest ZC706 evaluation board schematic. Users must identify the appropriate pins and replace the net names with net names in the user RTL. See Vivado Design Suite User Guide: Using Constraints (UG903) for more information.
The FMC connectors J37 and J5 are connected to 2.5V VADJ banks. Because different FMC cards implement different circuitry, the FMC bank I/O standards must be uniquely defined by each customer.
Note: Refer to the Board Files area of the documentation tab on the Xilinx Zynq-7000 SoC ZC706
Evaluation Kit product page (www.xilinx.com/zc706) for the latest xdc constraints file.
Refer to the Zynq-7000 SoC ZC706 Evaluation Kit - Known Issues and Release Notes Master Answer Record concerning the CE requirements for the PC Test Environment:
Zynq-7000 SoC ZC706 Master Answer Record 51899
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Appendix D
Board Setup
Installing the ZC706 Board in a PC Chassis
Installation of the ZC706 board inside a computer chassis is required when developing or testing PCI Express� functionality.
When the ZC706 board is used inside a computer chassis (that is, plugged in to the PCIe� slot), power is provided from the ATX power supply 4-pin peripheral connector through the ATX adapter cable shown in Figure D-1 to J22 on the ZC706 board. The Xilinx part number for this cable is 2600304, and is equivalent to Sourcegate Technologies part number AZCBL-WH-1109-RA4. For information on ordering this cable, see [Ref 37].
X-Ref Target - Figure D-1
To ATX 4-Pin Peripheral Power Connector
To J22 on ZC706 Board
Figure D-1: ATX Power Supply Adapter Cable To install the ZC706 board in a PC chassis:
UG954_aD_01_100212
1. On the ZC706 board, remove all six rubber feet and standoffs and the PCIe bracket. The standoffs and feet are affixed to the board by screws on the top side of the board. Remove all six screws.
2. Re-attach the PCIe bracket to the ZC706 board using two of the previously removed screws.
3. Power down the host computer and remove the power cord from the PC.
4. Open the PC chassis following the instructions provided with the PC.
5. Select a vacant PCIe expansion slot and remove the expansion cover (at the back of the chassis) by removing the screws on the top and bottom of the cover.
6. Plug the ZC706 board into the PCIe connector at this slot and secure its PCIe bracket to the chassis with a screw at the top of the bracket.
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Installing the ZC706 Board in a PC Chassis
7. The ZC706 board is taller than standard PCIe cards. Ensure that the height of the card is free of obstructions.
8. Connect the ATX power supply to the ZC706 board using the ATX power supply adapter cable as shown in Figure D-1:
a. Plug the 6-pin 2 x 3 Molex connector on the adapter cable into J22 on the ZC706 board.
b. Plug the 4-pin 1 x 4 peripheral power connector from the ATX power supply into the 4-pin adapter cable connector.
9. Slide the ZC706 board power switch SW1 to the ON position. The PC can now be powered on.
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Appendix E
Board Specifications
Dimensions
Height 5.5 inch (14.0 cm) Length 10.5 inch (26.7 cm) Note: The ZC706 board height exceeds the standard 4.376 inch (11.15 cm) height of a PCI Express
card.
Environmental
Temperature
Operating: 0�C to +45�C Storage: �25�C to +60�C
Humidity
10% to 90% non-condensing
Operating Voltage
+12 VDC
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Appendix F
Regulatory and Compliance Information
Overview
This product is designed and tested to conform to the European Union directives and standards described in this section. Refer to the Zynq-7000 SoC ZC706 Evaluation Kit - Known Issues and Release Notes Master Answer Record concerning the CE requirements for the PC Test Environment: Zynq-7000 SoC ZC706 Master Answer Record 51899
Declaration of Conformity
The Zynq-7000 SoC ZC706 Evaluation Kit CE Declaration of Conformity is online.
CE Directives
2006/95/EC, Low Voltage Directive (LVD) 2004/108/EC, Electromagnetic Compatibility (EMC) Directive
CE Standards
EN standards are maintained by the European Committee for Electrotechnical Standardization (CENELEC). IEC standards are maintained by the International Electrotechnical Commission (IEC).
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Electromagnetic Compatibility
EN 55022:2010, Information Technology Equipment Radio Disturbance Characteristics � Limits and Methods of Measurement EN 55024:2010, Information Technology Equipment Immunity Characteristics � Limits and Methods of Measurement This is a Class A product. In a domestic environment, this product can cause radio interference, in which case the user might be required to take adequate measures.
Safety
IEC 60950-1:2005, Information technology equipment � Safety, Part 1: General requirements EN 60950-1:2006, Information technology equipment � Safety, Part 1: General requirements
Markings
In August of 2005, the European Union (EU) implemented the EU WEEE Directive 2002/96/EC and later the WEEE Recast Directive 2012/19/EU requiring Producers of electronic and electrical equipment (EEE) to manage and finance the collection, reuse, recycling and to appropriately treat WEEE that the Producer places on the EU market after August 13, 2005. The goal of this directive is to minimize the volume of electrical and electronic waste disposal and to encourage re-use and recycling at the end of life. Xilinx has met its national obligations to the EU WEEE Directive by registering in those countries to which Xilinx is an importer. Xilinx has also elected to join WEEE Compliance Schemes in some countries to help manage customer returns at end-of-life. If you have purchased Xilinx-branded electrical or electronic products in the EU and are intending to discard these products at the end of their useful life, please do not dispose of them with your other household or municipal waste. Xilinx has labeled its branded electronic products with the WEEE Symbol to alert our customers that products bearing this label should not be disposed of in a landfill or with municipal or household waste in the EU.
This product complies with Directive 2002/95/EC on the restriction of hazardous substances (RoHS) in electrical and electronic equipment.
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In August of 2005, the European Union (EU) implemented the EU WEEE Directive 2002/96/EC and later the WEEE Recast Directive 2012/19/EU requiring Producers of electronic and electrical equipment (EEE) to manage and finance the collection, reuse, recycling and to appropriately treat WEEE that the Producer places on the EU market after August 13, 2005. The goal of this directive is to minimize the volume of electrical and electronic waste disposal and to encourage re-use and recycling at the end of life. Xilinx has met its national obligations to the EU WEEE Directive by registering in those countries to which Xilinx is an importer. Xilinx has also elected to join WEEE Compliance Schemes in some countries to help manage customer returns at end-of-life. If you have purchased Xilinx-branded electrical or electronic products in the EU and are intending to discard these products at the end of their useful life, please do not dispose of them with your other household or municipal waste. Xilinx has labeled its branded electronic products with the WEEE Symbol to alert our customers that products bearing this label should not be disposed of in a landfill or with municipal or household waste in the EU.
This product complies with CE Directives 2006/95/EC, Low Voltage Directive (LVD) and 2004/108/EC, Electromagnetic Compatibility (EMC) Directive.
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Appendix G
Additional Resources
Xilinx Resources
For support resources such as Answers, Documentation, Downloads, and Forums, see the Xilinx Support website. For continual updates, add the Answer Record to your myAlerts.
Solution Centers
See the Xilinx Solution Centers for support on devices, software tools, and intellectual property at all stages of the design cycle. Topics include design assistance, advisories, and troubleshooting tips.
References
The most up to date information related to the ZC706 board, its documentation, and schematics, are available on the following websites. The Xilinx Zynq-7000 SoC ZC706 Evaluation Kit product page:
www.xilinx.com/zc706 The Zynq-7000 SoC ZC706 Evaluation Kit - Known Issues and Release Notes Master Answer Record is Zynq-7000 SoC ZC706 Master Answer Record 51899. These Xilinx documents provide supplemental material useful with this guide: 1. Zynq-7000 SoC Overview (DS190) 2. Zynq-7000 SoC (Z-7030, 035, 045, and Z-7100): DC and AC Switching Characteristics
(DS191) 3. LogiCORE IP DisplayPort Product Guide for Vivado Design Suite (PG064)
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References
4. LogiCORE IP Tri-Mode Ethernet MAC Product Guide for Vivado Design Suite (PG051) 5. 7 Series FPGAs Memory Resources User Guide (UG473) 6. 7 Series FPGAs Configuration User Guide (UG470) 7. 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476) 8. 7 Series FPGAs Integrated Block for PCI Express Product Guide for Vivado Design Suite
(PG054) 9. 7 Series FPGAs and Zynq-7000 SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital
Converter User Guide (UG480) 10. Zynq-7000 SoC Technical Reference Manual (UG585) 11. 7 Series FPGAs Memory Interface Solutions User Guide (UG586) 12. Zynq-7000 SoC Packaging and Pinout Product Specification (UG865) 13. AMS101 Evaluation Card User Guide (UG886) 14. Vivado Design Suite User Guide: Using Constraints (UG903) 15. Zynq-7000 SoC PCB Design and Pin Planning Guide (UG933) 16. Answer Record AR#61712
Other documents associated with Xilinx devices, design tools, intellectual property, boards, and kits are available at the Xilinx documentation website at:
www.xilinx.com/support/documentation/index
Documents associated with other devices used by the ZC706 evaluation board are available at these vendor websites:
17. Spansion Inc.: www.spansion.com (S25FL128SAGMFIR01)
18. Standard Microsystems Corporation: www.smsc.com/ (USB3320)
19. SanDisk: www.sandisk.com 20. SD Association: www.sdcard.org. 21. SiTime: www.sitime.com
(SiT9102) 22. Silicon Labs: www.silabs.com
(Si570, Si5324C) 23. PCI Express� standard: www.pcisig.com/specifications 24. SFF-8431 specification: ftp.seagate.com/sff 25. Marvell Semiconductor: www.marvell.com, www.marvell.com/transceivers/alaska-gbe
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References
26. Analog Devices: www.analog.com/en/index.html (ADP 123, ADV7511KSTZ-P)
27. Texas Instruments: www.ti.com, www.ti.com/fusiondocs (UCD90120A, LMZ31506, LMZ31520, LMZ31710, LMZ31704, TPS54291PWP, TPS51200DR, PCA9548, TCA641APWR, TXS0108E)
28. Texas Instruments: www.ti.com/xilinx_usb (to order EVM USB-TO-GPIO)
29. Texas Instruments: www.ti.com/fusion-gui (to download FUSION_DIGITAL_POWER_DESIGNER)
30. RTC-8564JE/NB Application Manual: www.epsondevice.com/docs/qd/en/DownloadServlet?id=ID000498
31. Epson Electronics America: www.eea.epson.com. (RTC-8564JE)
32. Samtec: www.samtec.com. (SEAF series connectors)
33. Texas Instruments digital power: www.ti.com/ww/en/analog/digital-power/index.html
34. Maxim Integrated: www.maximintegrated.com (Maxim MAX13035E)
35. Micron Technology: www.micron.com (MT8JTF12864HZ-1G6G1, MT41J256M8HX-15E)
36. Digilent: www.digilentinc.com (Pmod Peripheral Modules)
37. Sourcegate Technologies: www.sourcegate.net. To order the custom Sourcegate cable, contact Sourcegate at, +65 6483 2878 for price and availability.
Note: The Xilinx ATX cable part number 2600304 is manufactured by Sourcegate Technologies
and is equivalent to the Sourcegate Technologies part number AZCBL-WH-11009. Sourcegate only manufactures the latest revision. This is a custom cable and cannot be ordered from the Sourcegate website.
38. VITA FMC Marketing Alliance: www.vita.com (FPGA Mezzanine Card (FMC) VITA 57.1 specification)
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