Intel Agilex™ Device Data Sheet
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Intel Agilex™ Device Data Sheet
The Intel Agilex device data sheet covers the electrical characteristics, switching characteristics, configuration specifications, and timing specifications for Intel Agilex devices.
specifications, electrical, switching, configuration, I/O timing, data sheet, Intel Agilex
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Intel� AgilexTM Device Data Sheet Subscribe Send Feedback DS-1060 | 2021.10.26 Latest document on the web: PDF | HTML Contents Contents Intel� AgilexTM Device Data Sheet............................................................................................................................................... 3 Electrical Characteristics...................................................................................................................................................... 5 Operating Conditions.................................................................................................................................................. 5 Switching Characteristics....................................................................................................................................................27 Core Performance Specifications.................................................................................................................................28 Periphery Performance Specifications.......................................................................................................................... 38 E-Tile Transceiver Performance Specifications...............................................................................................................46 P-Tile Transceiver Performance Specifications............................................................................................................... 50 R-Tile Transceiver Performance Specifications...............................................................................................................55 F-Tile Transceiver Performance Specifications............................................................................................................... 62 HPS Performance Specifications................................................................................................................................. 77 Configuration Specifications.............................................................................................................................................. 112 General Configuration Timing Specifications............................................................................................................... 112 POR Specifications..................................................................................................................................................113 External Configuration Clock Source Requirements......................................................................................................114 JTAG Configuration Timing.......................................................................................................................................114 AS Configuration Timing.......................................................................................................................................... 116 Avalon Streaming (Avalon-ST) Configuration Timing....................................................................................................118 Configuration Bit Stream Sizes................................................................................................................................. 120 I/O Timing......................................................................................................................................................................120 Programmable IOE Delay..................................................................................................................................................121 Glossary.........................................................................................................................................................................121 Document Revision History for the Intel Agilex Device Data Sheet..........................................................................................125 Intel� AgilexTM Device Data Sheet 2 Send Feedback DS-1060 | 2021.10.26 Send Feedback Intel� AgilexTM Device Data Sheet This data sheet describes the electrical characteristics, switching characteristics, configuration specifications, and timing for Intel� AgilexTM devices. Until the data sheet status for a device reaches Final, the specifications are subject to change at any time and at Intel's discretion. Table 1. Data Sheet Status for Intel Agilex Devices (F-Series) Device AGF 012/014 E-Tile & P-Tile AGF 012/014 E-Tile & P-Tile AGF 022/027 E-Tile & P-Tile AGF 019/023 E-Tile & P-Tile AGF 006/008 F-Tile AGF 006/008/012/014/019/022/023/027 F-Tile AGF 019/022/023/027 F-Tile Tile R24A R24B R25A R25A R16A R24C R31C Package Final Final Final Preliminary Advance Advance Advance Status Table 2. Data Sheet Status for Intel Agilex Devices (I-Series) Device Tile AGI 019/023 R-Tile & F-Tile R18A AGI 022/027 R-Tile & F-Tile R29A AGI 022/027 R-Tile & F-Tile R31A AGI 019/022/023/027 F-Tile R31B Package Advance Advance Advance Advance Status Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2015 Registered Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 The following descriptors designate the status level currently applicable to the relevant variant: � Advance: These are target specifications based on simulation. � Preliminary: These specifications are based on simulation, early validation, and/or early characterization data. � Final: These are production specifications based on silicon validation and/or characterization. Table 3. Intel Agilex Device Grades, Core Speed Grades, and Power Options Supported For specification status, see the Data Sheet Status table Device Grade Speed Grade and Power Option Supported Extended �E1V (fastest) �E2V �E3V �E3E �E4X �E4F Industrial �I1V �I2V �I3V �I3E The suffix after the speed grade denotes the power options offered in Intel Agilex devices. � V--standard power (VID) � E--lower power (VID) � X--lowest power (VID) � F--fixed voltage Related Information Package and Thermal Resistance website Intel� AgilexTM Device Data Sheet 4 Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Electrical Characteristics The following sections describe the operating conditions and power consumption of Intel Agilex devices. Operating Conditions Intel Agilex devices are rated according to a set of defined parameters. To maintain the highest possible performance and reliability of the Intel Agilex devices, you must consider the operating requirements described in this section. Absolute Maximum Ratings This section defines the maximum operating conditions for Intel Agilex devices. The values are based on experiments conducted with the devices and theoretical modeling of breakdown and damage mechanisms. The functional operation of the device is not implied for these conditions. Caution: Conditions outside the range listed in the following table may cause permanent damage to the device. Additionally, device operation at the absolute maximum ratings for extended periods of time may have adverse effects on the device. Table 4. Absolute Maximum Rating for Intel Agilex Devices For specification status, see the Data Sheet Status table Symbol Description Condition VCC VCCP Core voltage power supply -- Periphery circuitry power -- supply VCCPT Power supply for I/O PLL -- and I/O pre-driver VCCR_CORE VCCH CRAM power supply Transceiver digital power supply -- E-tile and P-tile devices VCCH_SDM SDM block transceiver digital power sense E-tile and P-tile devices VCCIO_PIO_SDM SDM block I/O bank power -- sense of bank 3A Minimum �0.5 �0.5 �0.5 �0.5 �0.5 �0.5 �0.5 Maximum 1.14 1.14 2.08 1.64 1.21 1.21 2.01 Unit V V V V V V V continued... Send Feedback Intel� AgilexTM Device Data Sheet 5 Symbol VCCIO_SDM VCCL_SDM VCCFUSEWR_SDM VCCPLLDIG_SDM VCCPLL_SDM VCCBAT VCCADC VCCIO_PIO VCCA_PLL VCCRT_GXE VCC_HSSI_GXE VCCRTPLL_GXE VCCH_GXE VCCCLK_GXE VCCRT_GXP VCC_HSSI_GXP VCCFUSE_GXP Description Condition SDM block configuration -- pins power supply SDM block core voltage -- power supply SDM block fuse writing -- power supply SDM block PLL digital -- power supply SDM block PLL analog -- power supply Battery back-up power -- supply (For design security volatile key register) ADC voltage sensor power -- supply I/O bank power supply -- I/O clock network power -- supply Transceiver power supply E-tile devices E-tile digital signal power supply E-tile devices Transceiver PLL power supply E-tile devices Analog power supply E-tile devices LVPECL REFCLK power supply E-tile devices Transceiver power supply P-tile devices P-tile digital signal power supply P-tile devices P-tile efuse power supply P-tile devices Intel� AgilexTM Device Data Sheet 6 Minimum �0.5 �0.5 �0.5 �0.5 �0.5 �0.5 �0.5 �0.5 �0.5 �0.5 �0.5 �0.5 �0.5 �0.5 �0.5 �0.5 �0.5 Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Maximum 2.08 1.07 2.4 1.07 2.08 2.08 2.08 2.01 1.64 1.21 1.21 1.21 1.47 3.41 1.21 1.21 1.21 Unit V V V V V V V V V V V V V V V V V continued... Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Symbol VCCCLK_GXP VCCH_GXP VCCEHT_GXR VCCERT_GXR VCCED_GXR VCCE_PLL_GXR VCCE_DTS_GXR VCCCLK_GXR VCCHFUSE_GXR VCC_HSSI_GXR VCCERT1_FHT_GXF VCCERT2_FHT_GXF VCCEHT_FHT_GXF VCCERT_FGT_GXF VCCH_FGT_GXF VCCERT_GXF_COMBINE VCCL_HPS VCCPLLDIG_HPS Description Condition P-tile I/O buffer power supply P-tile devices High voltage power for transceiver P-tile devices Transceiver analog high voltage power R-tile devices Transceiver analog power supply R-tile devices Transceiver digital power supply R-tile devices PLLs power supply R-tile devices DTS power supply R-tile devices Reference clock power supply R-tile devices R-tile efuse power supply R-tile devices Digital signal power supply R-tile devices FHT analog core supply 1 F-tile devices FHT analog core supply 2 F-tile devices FHT high voltage power supply for analog circuit F-tile devices FGT analog core supply F-tile devices FGT analog I/O power supply F-tile devices Combined analog core supply F-tile devices HPS core voltage and -- periphery circuitry power supply HPS PLL digital power -- supply Send Feedback Minimum �0.5 �0.5 1.75 0.97 0.87 0.98 0.98 0.97 0.97 0.87 0.975 0.975 1.47 0.97 1.746 0.975 �0.5 �0.5 Maximum 2.46 2.46 1.85 1.03 0.93 1.02 1.02 1.03 1.03 0.93 1.33 1.33 1.99 1.34 2.41 1.33 1.21 1.21 Unit V V V V V V V V V V V V V V V V V V continued... Intel� AgilexTM Device Data Sheet 7 Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Symbol VCCPLL_HPS VCCIO_HPS VI IOUT (1) (2) Description HPS PLL analog power supply HPS I/O buffers power supply DC input voltage DC output current per pin Condition -- -- VCCIO_PIO = 1.2 V VCCIO_PIO = 1.5 V VCCIO_SDM, VCCIO_HPS = 1.8 V VCCIO_PIO = 1.2 V, 1.5 V (3) Minimum �0.5 �0.5 �0.3 0 �0.3 �15 Maximum 2.08 2.08 1.56 1.7 2.19 15 Unit V V V V V mA VCCIO_SDM, VCCIO_HPS = 1.8 �20 20 mA V (4) TJ Absolute junction -- temperature �55 125 �C TSTG Storage temperature -- �55 150 �C Maximum Allowed Overshoot and Undershoot Voltage During transitions, input signals may overshoot to the voltage listed in the following tables and undershoot to �1.1 V when using VCCIO_HPS/ VCCIO_SDM of 1.8 V and �0.3 V when using VCCIO_PIO of 1.2 V for input currents less than 100 mA and periods shorter than 20 ns. (1) Total current per I/O bank must not exceed 100 mA. (2) Applies to all I/O standards and settings supported by I/O banks, including single-ended and differential I/Os. (3) The maximum current allowed through any GPIO bank pin when the device is not turned on or during power-up/power-down conditions is 10 mA. Pin voltage during these conditions should not exceed 1.2 V or the VCCIO_PIO supply rail of the bank where the I/O pin resides in, whichever is the lower voltage. (4) The maximum current allowed through any HPS/SDM pin when the device is not turned on or during power-up/power-down conditions is 10 mA. Pin voltage during these conditions should not exceed VCCIO_HPS or VCCIO_SDM supply rail of the bank where the I/O pin resides in. Intel� AgilexTM Device Data Sheet 8 Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Table 5. Vi (AC) Table 6. Vi (AC) No overshooting beyond 1.7 V and undershooting below 0 V is allowed when using VCCIO_PIO = 1.5 V. The maximum allowed overshoot duration is specified as a percentage of high time (calculated as ([delta T]/T) � 100) over the lifetime of the device. A DC signal is equivalent to 100% duty cycle. Maximum Allowed Overshoot During Transitions for Intel Agilex Devices (for 1.2 V I/O in GPIO Bank) This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime. For specification status, see the Data Sheet Status table Symbol Description Condition (V) AC input voltage VCCIO_PIO + 0.30 VCCIO_PIO + 0.35 VCCIO_PIO + 0.40 VCCIO_PIO + 0.45 VCCIO_PIO + 0.50 > VCCIO_PIO + 0.50 Overshoot Duration as % at TJ = 100�C 100 37 9 3 1 No overshoot allowed Unit % % % % % % Maximum Allowed Overshoot During Transitions for Intel Agilex Devices (for 1.8 V I/O in HPS and SDM I/O Banks) This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime. For specification status, see the Data Sheet Status table Symbol Description Condition (V) AC input voltage VCCIO_SDM + 0.30, VCCIO_HPS + 0.30 VCCIO_SDM + 0.35, VCCIO_HPS + 0.35 VCCIO_SDM + 0.40, VCCIO_HPS + 0.40 VCCIO_SDM + 0.45, VCCIO_HPS + 0.45 Overshoot Duration as % at TJ = 100�C 100 60 30 20 Unit % % % % continued... Send Feedback Intel� AgilexTM Device Data Sheet 9 Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Symbol Description Condition (V) VCCIO_SDM + 0.50, VCCIO_HPS + 0.50 VCCIO_SDM + 0.55, VCCIO_HPS + 0.55 >VCCIO_SDM + 0.55, >VCCIO_HPS + 0.55 Overshoot Duration as % at TJ = 100�C 10 6 No overshoot allowed Unit % % % Figure 1. For example, when using 1.2 V I/O standard with 1.26 V VCCIO_PIO, a signal that overshoots to 1.71 V can only be at 1.71 V for ~3% over the lifetime of the device. For an overshoot of 1.56 V, the percentage of high time for the overshoot can be as high as 100% over the lifetime of the device. Intel Agilex Devices Overshoot Duration Example (for 1.2 V GPIO Bank at VCCIO_PIO = 1.26 V) 1.76 V 1.56 V 1.2 V DT T Recommended Operating Conditions This section lists the functional operation limits for the AC and DC parameters for Intel Agilex devices. Intel� AgilexTM Device Data Sheet 10 Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Recommended Operating Conditions Table 7. Recommended Operating Conditions for Intel Agilex Devices This table lists the steady-state voltage values expected for Intel Agilex devices. Power supply ramps must all be strictly monotonic, without plateaus. For specification status, see the Data Sheet Status table Symbol VCC Description Core voltage power supply Condition SmartVID(6) : �1V, � 2V, �3V, �3E, �4X VCCP Periphery circuitry power supply Fixed voltage: �4F SmartVID(6): �1V, � 2V, �3V, �3E, �4X Fixed voltage: �4F VCCPT Power supply for I/O -- PLL and I/O pre-driver VCCR_CORE VCCH CRAM power supply Advanced interface bus (AIB) power supply -- E-tile and P-tile devices R-tile and F-tile devices VCCH_SDM VCCIO_PIO_SDM (8) SDM block transceiver -- digital power sense SDM block I/O bank power sense of Bank 3A 1.5 V Minimum(5) (Typical) � 3% 0.776 (Typical) � 3% 0.776 1.71 1.14 0.87 0.776 0.87 1.455 Typical 0.70 � 0.90(7) 0.8 0.70 � 0.90(7) 0.8 1.8 1.2 0.9 0.8 0.9 1.5 Maximum(5) (Typical) + 3% 0.824 (Typical) + 3% 0.824 1.89 1.26 0.93 0.824 0.93 1.545 Unit V V V V V V V V V V continued... (5) This value describes the required voltage measured between the PCB power and ground ball during normal device operation. The voltage ripple includes both regulator DC ripple and the dynamic noise. (6) The use of Power Management Bus (PMBus*) voltage regulator dedicated to Intel Agilex SmartVID devices is mandatory. The PMBus voltage regulator and Intel Agilex SmartVID devices are connected via PMBus. (7) The typical value is based on the SmartVID programmed value. Send Feedback Intel� AgilexTM Device Data Sheet 11 Symbol VCCIO_SDM VCCL_SDM VCCFUSEWR_SDM VCCPLLDIG_SDM VCCPLL_SDM VCCBAT (9) IBAT (10) VCCADC Description Condition 1.2 V SDM block -- configuration pins power supply SDM block core -- voltage power supply SDM block fuse writing -- power supply SDM block PLL digital -- power supply SDM block PLL analog -- power supply Battery back-up power -- supply (For design security volatile key register) Battery back-up power supply (For design security volatile key register) VCCBAT = 1.2 V ADC voltage sensor -- power supply Minimum(5) 1.14 1.71 0.776 1.75 0.776 1.71 1 -- 1.71 Typical 1.2 1.8 0.8 1.8 0.8 1.8 -- -- 1.8 Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Maximum(5) 1.26 1.89 0.824 1.85 0.824 1.89 1.8 Unit V V V V V V V 200 nA 1.89 V continued... (5) This value describes the required voltage measured between the PCB power and ground ball during normal device operation. The voltage ripple includes both regulator DC ripple and the dynamic noise. (8) Must be powered up with the same voltage level as VCCIO_PIO_3A. Must be supplied at 1.2 V when using Avalon�-ST �16/�32 configuration schemes. (9) You need to always power up VCCBAT. If you do not use the design security feature in Intel Agilex devices, connect VCCBAT to a 1.8 V power supply. (10) At 25 �C. This supply current specification does not apply to �E4F speed grade and power option device. Intel� AgilexTM Device Data Sheet 12 Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Symbol VCCIO_PIO VCCA_PLL VI (11) VO TJ tRAMP (13) (14) Description Condition I/O bank power supply 1.5 V 1.2 V I/O clock network -- power supply DC input voltage Output voltage VCCIO_PIO = 1.2 V VCCIO_PIO = 1.5 V VCCIO_SDM = 1.8 V VCCIO_HPS = 1.8 V VCCIO_PIO = 1.2 V, 1.5 V Operating junction temperature VCCIO_SDM = 1.8 V VCCIO_HPS = 1.8 V Extended Industrial Power supply ramp time Standard POR Minimum(5) 1.455 1.14 1.14 �0.3 0 �0.3 �0.3 0 0 0 0 �40(12) 200 s Typical 1.5 1.2 1.2 -- -- -- -- -- -- -- -- -- -- Maximum(5) 1.545 1.26 1.26 VCCIO_PIO + 0.3 1.7 VCCIO_SDM + 0.3 VCCIO_HPS + 0.3 VCCIO_PIO VCCIO_SDM VCCIO_HPS 100 100 100 ms Unit V V V V V V V V V V �C �C -- (5) This value describes the required voltage measured between the PCB power and ground ball during normal device operation. The voltage ripple includes both regulator DC ripple and the dynamic noise. (11) This value applies to both input and tri-stated output configuration. Pin voltage should not be externally pulled higher than the maximum value. (12) E-tile supports an operating temperature range of �40�C to 100�C. However, the E-tile transceivers may experience a higher error rate from �40�C to �20�C because of the calibration procedure when starting at a low temperature. Therefore, the recommended operating temperature range for E-tile protocol-compliant transceiver links is �20�C to 100�C. The maximum temperature ramp rate is 2�C per minute. (13) tRAMP is the ramp time of each individual power supply, not the ramp time of all combined power supplies. (14) To support AS fast mode, all power supplies to the Intel Agilex device must be fully ramped-up within 10 ms to the recommended operating conditions. Send Feedback Intel� AgilexTM Device Data Sheet 13 Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Transceiver Power Supply Operating Conditions Table 8. E-Tile Transceiver Power Supply Operating Conditions for Intel Agilex Devices For specification status, see the Data Sheet Status table Symbol VCCRT_GXE (15) Description Transceiver power supply Typical DC Level (V) 0.9 Recommended DC Setpoint (% of Vnominal) Recommended VR Ripple (% of Vnominal) Recommended AC Transient (% of Vnominal) Maximum (DC Setpoint + Ripple + AC Transient) (% of Vnominal) � 0.5% � 2.5% � 3% VCC_HSSI_GXE E-tile digital signal 0.9 power supply VCCRTPLL_GXE (15) Transceiver PLL 0.9 power supply � 0.5% � 0.5% � 2.5% � 2.5% � 3% � 3% VCCH_GXE Analog power 1.1 � 0.5% � 0.5% � 2% � 3% supply VCCCLK_GXE LVPECL REFCLK 2.5 power supply � 0.5% � 0.5% � 3.5% � 5% Unit V V V V V Table 9. P-Tile Transceiver Power Supply Operating Conditions for Intel Agilex Devices The specifications below should be met at the board vias directly connected to the package power balls. Place the VR sense point in the FPGA pinfield (in the package shadow), as close as possible to the corresponding package power balls. For these rails, measure the output voltage at this remote sense location. For specification status, see the Data Sheet Status table Symbol VCCRT_GXP Description Transceiver power supply Typical DC Level (V) 0.9 Recommended DC Setpoint (% of Vnominal) Recommended VR Ripple (% of Vnominal) Recommended AC Transient (% of Vnominal) Maximum (DC Setpoint + Ripple + AC Transient) (% of Vnominal) � 0.5% � 2.5% � 3% VCC_HSSI_GXP P-tile digital signal 0.9 power supply � 0.5% � 2.5% � 3% Unit V V continued... (15) The difference between VCCRT/VCCRTPLL and VCCH should be no less than 200 mV. Intel� AgilexTM Device Data Sheet 14 Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Symbol VCCFUSE_GXP VCCCLK_GXP (16) VCCH_GXP (16) Description P-tile efuse power supply Typical DC Level (V) 0.9 Recommended DC Recommended VR Setpoint (% of Ripple (% of Vnominal) Vnominal) Recommended AC Transient (% of Vnominal) Maximum (DC Setpoint + Ripple + AC Transient) (% of Vnominal) � 0.5% � 2.5% � 3% P-tile I/O buffer 1.8 power supply � 0.5% � 0.5% � 2% � 3% High voltage power 1.8 for transceiver � 0.5% � 0.5% � 2% � 3% Table 10. R-Tile Transceiver Power Supply Operating Conditions for Intel Agilex Devices For specification status, see the Data Sheet Status table Symbol VCCH_GXR[L,R] (17) Description Transceiver analog high voltage power Typical DC Level (V) Recommended DC Recommended VR Setpoint (% of Ripple (% of Vnominal) Vnominal) Recommended AC Transient (% of Vnominal) Maximum (DC Setpoint + Ripple + AC Transient) (% of Vnominal) 1.8 �0.8% �2% �2.8% VCCRT_GXR[L,R] Transceiver analog 1 power supply �0.5% �2.5% �3% VCCED_GXR[L,R] Transceiver digital 0.9 power supply �0.8% �2.5% �3.3% VCCE_PLL_GXR[L,R] PLLs power supply 1 VCCE_DTS_GXR[L,R] DTS power supply 1 VCCCLK_GXR[L,R] (17) Reference clock 1 power supply �0.5% �0.5% �0.5% �1.5% �1.5% �2.5% �2% �2% �3% VCCHFUSE_GXR R-tile efuse power 1 supply �0.5% �2.5% �3% VCC_HSSI_GXR Digital signal power 0.9 supply �0.8% �2.5% �3.3% (16) Follow the more stringent tolerance range for the voltage rails connecting multiple power supplies. (17) Follow the more stringent tolerance range for the voltage rails connecting multiple power supplies. Unit V V V Unit V V V V V V V V Send Feedback Intel� AgilexTM Device Data Sheet 15 Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Table 11. F-Tile Transceiver Power Supply Operating Conditions for Intel Agilex Devices For specification status, see the Data Sheet Status table Symbol Description Typical DC Level (V) Recommended DC Recommended VR Setpoint (% of Ripple (% of Vnominal) Vnominal) Recommended AC Transient (% of Vnominal) Maximum (DC Setpoint + Ripple + AC Transient) (% of Vnominal) VCC_HSSI_GXF F-tile digital signal 0.8 power supply �0.5% �0.5% �2.5% �3% VCCFUSECORE_GXF F-tile fuse writing 1 power supply �0.5% �4.5% �5% VCCFUSEWR_GXF F-tile efuse power 1 supply �0.5% �4.5% �5% VCCCLK_GXF Reference clock 1.8 power supply VCCERT1_FHT_GXF (18) FHT analog core 1 supply 1 VCCERT2_FHT_GXF (19) FHT analog core 1 supply 2 VCCEHT_FHT_GXF (20) FHT high voltage 1.5 power supply for analog circuit VCCERT_FGT_GXF (21) FGT analog core 1 supply alone �0.5% �0.5% �0.5% �0.5% �0.5% �0.5% �0.5% �0.5% �0.5% �0.5% �2% �1.5% �1.5% +1%/�1.5% �1.5% �3% �2.5% �2.5% +2%/�2.5% �3% FGT analog core 1 supply when combined with �0.5% �0.5% �1.5% �2.5% Unit V V V V V V V V V continued... (18) HF noise requires AC 10 mVpp above 1 MHz; switching regulator ripple switching frequency: <500 kHz, ripple: 5 mVpp. (19) HF noise requires AC 30 mVpp above 1 MHz; switching regulator ripple switching frequency: <500 kHz, ripple: 5 mVpp. (20) HF noise requires AC 30 mVpp above 1 MHz; switching regulator ripple switching frequency: <500 kHz, ripple: 7 mVpp. (21) HF noise requires AC 30 mVpp above 1 MHz; switching regulator ripple: 5mVpp. Intel� AgilexTM Device Data Sheet 16 Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Symbol VCCH_FGT_GXF (21) Description VCCERT1_FHT_GX and VCCERT2_FHT_GXF 1 V supply FGT analog I/O power supply Typical DC Level (V) Recommended DC Recommended VR Setpoint (% of Ripple (% of Vnominal) Vnominal) Recommended AC Transient (% of Vnominal) Maximum (DC Setpoint + Ripple + AC Transient) (% of Vnominal) 1.8 �0.5% 5 mV �1.5% �3% Unit V Related Information AN 910: Intel Agilex Power Distribution Network Design Guidelines Provides the PCB design guidelines. HPS Power Supply Operating Conditions Table 12. HPS Power Supply Operating Conditions for Intel Agilex Devices This table lists the steady-state voltage and current values expected for Intel Agilex system-on-a-chip (SoC) devices with ARM-based hard processor system (HPS). Power supply ramps must all be strictly monotonic, without plateaus. Refer to the Recommended Operating Conditions for Intel Agilex Devices table for the steady-state voltage values expected from the FPGA portion of the Intel Agilex SoC devices. For specification status, see the Data Sheet Status table Symbol VCCL_HPS VCCPLLDIG_HPS Description Condition HPS core voltage and periphery circuitry power supply Performance boost, fixed voltage: �1V SmartVID: �1V, �2V, � 3V, �3E (22) Fixed voltage: �4F, � 4X HPS PLL digital power supply (can be connected to VCCL_HPS) Performance boost, fixed voltage: �1V Minimum (Typical) � 3% (Typical) � 3% 0.776 (Typical) � 3% Typical 0.95 0.70 � 0.90 0.8 0.95 Maximum (Typical) + 3% (Typical) + 3% 0.824 (Typical) + 3% Unit V V V V continued... (22) The use of Power Management Bus (PMBus) voltage regulator dedicated to Intel Agilex SmartVID devices is mandatory. The PMBus voltage regulator and Intel Agilex SmartVID devices are connected via PMBus. Send Feedback Intel� AgilexTM Device Data Sheet 17 Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Symbol VCCPLL_HPS VCCIO_HPS Description Condition SmartVID: �1V, �2V, � 3V, �3E (22) Fixed voltage: �4F, � 4X HPS PLL analog power 1.8 V supply HPS I/O buffers power 1.8 V supply Minimum (Typical) � 3% 0.776 1.71 1.71 Typical 0.70 � 0.90 0.8 1.8 1.8 Maximum (Typical) + 3% 0.824 1.89 1.89 Unit V V V V Related Information � Recommended Operating Conditions on page 11 Provides the steady-state voltage values for the FPGA portion of the device. � HPS Clock Performance on page 78 DC Characteristics Supply Current and Power Consumption Intel offers two ways to estimate power for your design--the Intel FPGA Power and Thermal Calculator (PTC) and the Intel Quartus� Prime Power Analyzer feature. Use the PTC before you start your design to estimate the supply current for your design. The PTC provides a magnitude estimate of the device power because these currents vary greatly with the usage of the resources. The Intel Quartus Prime Power Analyzer provides better quality estimates based on the specifics of the design after you complete place-and-route. The Power Analyzer can apply a combination of user-entered, simulation-derived, and estimated signal activities that, when combined with detailed circuit models, yield very accurate power estimates. Intel� AgilexTM Device Data Sheet 18 Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 I/O Pin Leakage Current Table 13. I/O Pin Leakage Current for Intel Agilex Devices (for GPIO Bank) For specification status, see the Data Sheet Status table Symbol Description Condition Min II Input pin VI = 0 V to VCCIO_PIO (MAX) �360 IOZ Tri-stated I/O pin VO = 0 V to VCCIO_PIO (MAX) �360 Max 360 360 Table 14. I/O Pin Leakage Current for Intel Agilex Devices (for HPS and SDM I/O Banks) For specification status, see the Data Sheet Status table Symbol Description Condition Min Max II Input or tri-stated I/O pin VI, VO = 0 V 0.015 6 VI, VO = VCCIO_HPS (MAX), 0.01 1 VCCIO_SDM (MAX) Bus Hold Specifications The bus-hold trip points are based on calculated input voltages from the JEDEC* standard. Table 15. Bus Hold Parameters for Intel Agilex Devices (for GPIO Bank) For specification status, see the Data Sheet Status table Parameter Symbol Condition Bus-hold, low, sustaining current Bus-hold, high, sustaining current ISUSL ISUSH VIN > VIL (max) VIN < VIH (min) Min 50 �50 VCCIO_PIO (V) 1.2 Max -- -- Unit �A �A Unit �A �A Unit �A �A continued... Send Feedback Intel� AgilexTM Device Data Sheet 19 Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Parameter Symbol Condition Bus-hold, low, overdrive current Bus-hold, high, overdrive current Bus-hold trip point IODL IODH VTRIP 0 V < VIN < VCCIO_PIO 0 V < VIN < VCCIO_PIO -- Min -- VCCIO_PIO (V) 1.2 Max 1,400 -- �1,400 0.33 � VCCIO_PIO 0.67 � VCCIO_PIO Unit �A �A V OCT Calibration Accuracy Specifications If you enable on-chip termination (OCT) calibration, calibration is automatically performed at power up for I/Os connected to the calibration block. Table 16. OCT Calibration Accuracy Specifications for Intel Agilex Devices (for GPIO Bank) Calibration accuracy for the calibrated on-chip series termination (RS OCT) and on-chip parallel termination (RT OCT) are applicable at the moment of calibration. When process, voltage, and temperature (PVT) conditions change after calibration, the tolerance may change. These specifications require RZQ reference accuracy of 240 �1%. For specification status, see the Data Sheet Status table Symbol 34- and 40- RS 50- and 60- RT Description Condition (V) Internal series termination with calibration (34- and 40- setting) VCCIO_PIO = 1.2 Internal parallel termination with calibration (50- and 60- setting) SSTL-12 and HSTL-12 I/O standards POD12 I/O standard Calibration Accuracy �20 �10 to +60 �15 Unit % % % Intel� AgilexTM Device Data Sheet 20 Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 OCT Without Calibration Resistance Tolerance Specifications Table 17. OCT Without Calibration Resistance Tolerance Specifications for Intel Agilex Devices (for GPIO Bank) This table lists the Intel Agilex GPIO OCT without calibration resistance tolerance to PVT changes. For specification status, see the Data Sheet Status table Symbol 34- and 40- RS 100- RD Description Internal series termination without calibration (34- and 40- setting) Internal differential termination (100- setting) Condition (V) VCCIO_PIO = 1.2 VCCIO_PIO = 1.5 VCCIO_PIO = 1.2 Calibration Accuracy �30 to +60 �40 �40 Unit % % % Pin Capacitance Table 18. CIO Pin Capacitance for Intel Agilex Devices (for GPIO Bank) For specification status, see the Data Sheet Status table Symbol Description Input/output capacitance of I/O pins Maximum 2.6(23) Unit pF Internal Weak Pull-Up Resistor All I/O pins in GPIO bank have an option to enable weak pull-up when using 1.2 V LVCMOS I/O standard. For SDM and HPS, the configuration I/O and peripheral I/O are supported with weak pull-up and weak pull-down options. Table 19. Internal Weak Pull-Up Resistor Values for Intel Agilex Devices (for GPIO Bank) For specification status, see the Data Sheet Status table Symbol Description Condition (V) Min Typ RPU Value of the I/O pin VCCIO_PIO = 1.2 �5% 0.5 2.5 pull-up resistor before and during configuration, as well Max 15 Unit k (23) This value refers to die-level pin capacitance without the device package. Send Feedback Intel� AgilexTM Device Data Sheet 21 Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Symbol Description as user mode if you have enabled the programmable pull-up resistor option. Condition (V) Min Typ Max Unit Table 20. Internal Weak Pull-Up and Weak Pull-Down Resistor Values for Intel Agilex Devices (for HPS and SDM I/O Banks) For specification status, see the Data Sheet Status table Symbol Description Condition (V) Min Typ Max Unit 20 k RPU, 20 k RPD Value of the I/O pin VCCIO_SDM = 1.8 �5%, 15 20 25 k pull-up and pull-down VCCIO_HPS = 1.8 �5% resistor during user mode if you have enabled the programmable pull-up or pull-down resistor option. 50 k RPU, 50 k RPD Value of the I/O pin VCCIO_SDM = 1.8 �5%, 37.5 50 62.5 k pull-up and pull-down VCCIO_HPS = 1.8 �5% resistor during user mode if you have enabled the programmable pull-up or pull-down resistor option. 80 k RPU, 80 k RPD Value of the I/O pin VCCIO_SDM = 1.8 �5%, 60 pull-up and pull-down VCCIO_HPS = 1.8 �5% resistor during user mode if you have enabled the programmable pull-up or pull-down resistor option. 80 100 k Related Information Intel Agilex Device Family Pin Connection Guidelines Provides more information about the pins that support internal weak pull-up and internal weak pull-down features. Intel� AgilexTM Device Data Sheet 22 Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Hysteresis Specifications for Schmitt Trigger Input Table 21. Hysteresis Specifications for Schmitt Trigger Input for Intel Agilex Devices (for HPS I/O Bank) Intel Agilex devices support Schmitt trigger input on HPS I/O bank. A Schmitt trigger feature introduces hysteresis to the input signal for improved noise immunity, especially for signal with slow edge rate. For specification status, see the Data Sheet Status table Symbol VHYS Description Condition Hysteresis for Schmitt VCCIO_HPS = 1.8 V trigger input Min 180 Typ 250 Max 350 Unit mV I/O Standard Specifications Tables in this section list the input voltage (VIH and VIL), output voltage (VOH and VOL), and current drive characteristics (IOH and IOL) for various I/O standards supported by Intel Agilex devices. For minimum voltage values, use the minimum VCCIO_PIO values. For maximum voltage values, use the maximum VCCIO_PIO values. You must perform timing closure analysis to determine the maximum achievable frequency for general purpose I/O standards. Related Information Recommended Operating Conditions on page 11 Single-Ended I/O Standards Specifications Table 22. Single-Ended I/O Standards Specifications for Intel Agilex Devices (for GPIO Bank) For specification status, see the Data Sheet Status table I/O Standard Min VCCIO_PIO (V) Typ Max Min VIL (V) Max Min VIH (V) Max 1.2 V LVCMOS 1.14 1.2 1.26 �0.3 0.35 � 0.65 � VCCIO_PIO + 0.3 VCCIO_PIO VCCIO_PIO VOL (V)(24) Max 0.25 � VCCIO_PIO VOH (V)(24) Min 0.75 � VCCIO_PIO (24) Applicable to test condition of IOH and IOL at 2 mA. Send Feedback Intel� AgilexTM Device Data Sheet 23 Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Table 23. Single-Ended I/O Standards Specifications for Intel Agilex Devices (for HPS and SDM I/O Banks) For specification status, see the Data Sheet Status table I/O Standard VCCIO_HPS, VCCIO_SDM (V) VIL (V) VIH (V) VOL (V) VOH (V) IOL (mA)(25) Min Typ Max Min Max Min Max Max Min Max 1.8 V 1.71 1.8 1.89 �0.3 0.35 � 0.65 � VCCIO_HPS + 0.4 VCCIO_HPS � 8 LVCMOS VCCIO_HPS, VCCIO_HPS, 0.3, 0.4, 0.35 � 0.65 � VCCIO_SDM + VCCIO_SDM � VCCIO_SDM VCCIO_SDM 0.3 0.4 IOH (mA)(25) Min �8 Single-Ended SSTL, HSTL, HSUL, and POD I/O Reference Voltage Specifications Table 24. Single-Ended SSTL, HSTL, HSUL, and POD I/O Reference Voltage Specifications for Intel Agilex Devices (for GPIO Bank) For specification status, see the Data Sheet Status table I/O Standard Min VCCIO_PIO (V) Typ Max Min VREF (V) Typ Max Min VTT (V) Typ Max SSTL-12 HSTL-12 HSUL-12 POD12 1.14 1.2 1.26 0.49 � 0.5 � VCCIO_PIO 0.51 � 0.475 � 0.5 � VCCIO_PIO 0.525 � VCCIO_PIO VCCIO_PIO VCCIO_PIO VCCIO_PIO 1.14 1.2 1.26 0.47 � 0.5 � VCCIO_PIO 0.53 � 0.475 � 0.5 � VCCIO_PIO 0.525 � VCCIO_PIO VCCIO_PIO VCCIO_PIO VCCIO_PIO 1.14 1.2 1.26 0.49 � 0.5 � VCCIO_PIO 0.51 � -- -- -- VCCIO_PIO VCCIO_PIO 1.14 1.2 1.26 -- Internally -- calibrated -- VCCIO_PIO -- (25) To meet the IOH and IOL specifications, you must set the current strength settings accordingly. For example, to meet the 1.8 V LVCMOS specification (8 mA), you should set the current strength settings to 8 mA. Setting at lower current strength may not meet the IOH and IOL specifications in the data sheet. Intel� AgilexTM Device Data Sheet 24 Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications Table 25. Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications for Intel Agilex Devices (for GPIO Bank) For specification status, see the Data Sheet Status table I/O Standard VIL(DC) (V) Max VIH(DC) (V) Min VIL(AC) (V) Max VIH(AC) (V) Min SSTL-12 HSTL-12 HSUL-12 POD12(26) VREF � 0.075 VREF � 0.080 VREF � 0.100 VREF � 0.055 VREF + 0.075 VREF + 0.080 VREF + 0.100 VREF + 0.055 VREF � 0.100 VREF � 0.150 VREF � 0.135 VREF � 0.070 VREF + 0.100 VREF + 0.150 VREF + 0.135 VREF + 0.070 Note: For output voltage swing calculation example, refer to the Intel Agilex General Purpose I/O and LVDS SERDES User Guide. Related Information 1.2 V I/O Interface Voltage Level Compatibility section, Intel Agilex General Purpose I/O and LVDS SERDES User Guide Provides output voltage swing calculation examples. (26) This specification is defined over internal Vref range from 0.6 � VCCIO_PIO to 0.92 � VCCIO_PIO. Send Feedback Intel� AgilexTM Device Data Sheet 25 Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Differential SSTL, HSTL, and HSUL I/O Standards Specifications Table 26. Differential SSTL, HSTL, and HSUL I/O Standards Specifications for Intel Agilex Devices (for GPIO Bank) For specification status, see the Data Sheet Status table I/O Standard VCCIO_PIO (V) VILdiff(DC) VIHdiff(DC) VILdiff(AC) VIHdiff(AC) (V) (V) (V) (V) VIX(AC) (V) VOX(AC) (V) Min Typ Max Max Min Max Min Min Typ Max Min Typ Max SSTL-12 1.14 1.2 1.26 �0.15 0.15 �0.2 0.2 0.5 � 0.5 � 0.5 � 0.5 � 0.5 � 0.5 � VCCIO_PIO � 0.12 VCCIO_PIO VCCIO_PIO + 0.12 VCCIO_PIO � 0.12 VCCIO_PIO VCCIO_PIO + 0.12 HSTL-12 1.14 1.2 1.26 �0.16 0.16 �0.3 0.3 0.5 � 0.5 � 0.5 � 0.5 � 0.5 � 0.5 � VCCIO_PIO � 0.12 VCCIO_PIO VCCIO_PIO + 0.12 VCCIO_PIO � 0.12 VCCIO_PIO VCCIO_PIO + 0.12 HSUL-12 1.14 1.2 1.26 �0.2 0.2 �0.27 0.27 0.5 � 0.5 � 0.5 � 0.5 � 0.5 � 0.5 � VCCIO_PIO � 0.12 VCCIO_PIO VCCIO_PIO + 0.12 VCCIO_PIO � 0.12 VCCIO_PIO VCCIO_PIO + 0.12 Differential POD I/O Standards Specifications Table 27. Differential POD I/O Standards Specifications for Intel Agilex Devices (for GPIO Bank) For specification status, see the Data Sheet Status table I/O Standard Min VCCIO_PIO (V) Typ Max VILdiff(DC) (V) Max VIHdiff(DC) (V) Min VILdiff(AC) (V) Max VIHdiff(AC) (V) Min POD12 1.14 1.2 1.26 �0.11 0.11 �0.14 0.14 VIX(AC) (%)(27) Max 25 (27) Percentage of P-leg and N-leg crossing relative to the midpoint of P-leg and N-leg signal swings. Intel� AgilexTM Device Data Sheet 26 Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Differential I/O Standards Specifications Table 28. I/O Standard True Differenti al Signaling (Transmi tter & Receiver) (30) Differential I/O Standards Specifications for Intel Agilex Devices (for GPIO Bank) For specification status, see the Data Sheet Status table VCCIO_PIO (V) Min Typ Max VID (mV) Min Max Min VICM(DC) (V) Conditio n Max VOD (V)(28) (29) Min Typ Max 1.455 1.5 1.545 200 600 0.3 Data rate <0.9 0.247 -- 0.454 700 100 600 0.9 Mbps 1.4 100 600 0.9 Data rate 1.4 >700 Mbps True 1.14 1.2 1.26 200 600 0.3 Data rate <0.9 -- -- -- Differenti 700 al 100 600 0.9 Mbps 1.1 Signaling (Receiver 100 600 0.9 Data rate 1.1 only)(30) >700 Mbps Switching Characteristics This section provides the performance characteristics of Intel Agilex core and periphery blocks. Min VOCM (V)(28) Typ Max 0.99 1.1 1.21 -- -- -- (28) RL range: 90 RL 110 . (29) The specification is only applicable to default VOD and pre-emphasis setting. (30) The True Differential Signaling input buffer is supported on 1.2 V and 1.5 V VCCIO_PIO bank. The maximum input voltage driven into the True Differential Signaling input buffer must not exceed VICM(max) + VID(max)/2. Send Feedback Intel� AgilexTM Device Data Sheet 27 Core Performance Specifications Clock Tree Specifications Table 29. Clock Tree Performance for Intel Agilex Devices For specification status, see the Data Sheet Status table Parameter Performance �1V, �2V Programmable clock routing 1,000 �3V, �3E, �4F, �4X 780 I/O PLL Specifications Table 30. I/O PLL Specifications for Intel Agilex Devices For specification status, see the Data Sheet Status table Symbol Parameter Condition Min Typ fIN Input clock frequency �1V �2V 10 -- 10 -- �3V, �3E 10 -- �4F, �4X 10 -- fINPFD Input clock frequency -- to the PFD 10 -- fVCO I/O PLL VCO operating �1V range �2V 600 -- 600 -- �3V, �3E 600 -- �4F, �4X 600 -- Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Unit MHz Max 1,100(31) 900(31) 750(31) 650(31) 325 1,600 1,434 1,250 1,067 Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz continued... (31) This specification is limited by the I/O maximum frequency. The maximum achievable I/O frequency is different for each I/O standard and is dependent on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system. Intel� AgilexTM Device Data Sheet 28 Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Symbol fCLBW tEINDUTY fOUT fOUT_EXT tOUTDUTY tFCOMP (33) fDYCONFIGCLK tLOCK Parameter Condition I/O PLL closed-loop bandwidth I/O bank I/O PLL Fabric-feeding I/O PLL Input clock or external -- feedback clock input duty cycle Output frequency for internal clock (C counter) �1V �2V �3V, �3E �4F, �4X Output frequency for �1V external clock output �2V �3V, �3E �4F, �4X Duty cycle for dedicated external clock output (when set to 50%) fOUT_EXT < 300 MHz fOUT_EXT 300 MHz External feedback -- clock compensation time Dynamic configuration -- clock for mgmt_clk Time required to lock -- from end-of-device configuration or deassertion of areset Min 0.5 1 40 -- -- -- -- -- -- -- -- 45 40/45 (32) -- -- -- Typ -- -- -- -- -- -- -- -- -- -- -- 50 50 -- -- -- Max 10 10 60 1,100 900 750 650 800 717 625 500 55 55 (32)/60 5 100 1 Unit MHz MHz % MHz MHz MHz MHz MHz MHz MHz MHz % % ns MHz ms continued... (32) To achieve 5% duty cycle for fOUT_EXT 300 MHz, you only can use tx_outclk port from the LVDS SERDES Intel FPGA IP. Refer to the Intel Agilex Clocking and PLL User Guide for the detail design guidelines. (33) Not applicable for fabric-feeding I/O PLL. Send Feedback Intel� AgilexTM Device Data Sheet 29 Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Symbol tDLOCK tPLL_PSERR tARESET tINCCJ tREFPJ tREFPN Parameter Condition Time required to lock -- dynamically (after switchover or reconfiguring any nonpost-scale counters/ delays) Accuracy of PLL phase -- shift Minimum pulse width -- on the areset signal Input clock cycle-tocyle jitter Reference phase jitter (rms)(35) fREF < 100 MHz (34) fREF 100 MHz (34) Carrier frequency: 100 MHz with integrated bandwidth of 10 kHz to 50 MHz Reference phase noise(36) (35) 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz Min -- -- 10 -- -- -- -- -- -- -- -- -- -- Typ -- -- -- -- -- -- -- -- -- -- -- -- -- Max 1 �50 -- 750 0.15 1.42 �90 �100 �110 �120 �130 �138 �142 Unit ms ps ns ps (p-p) UI (p-p) ps dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz continued... (34) fREF is fIN/N, specification applies when N = 1. (35) Requirement for Advanced Interface Bus (AIB), High Bandwidth Memory (HBM) Interface, Mobile Industry Processor Interface (MIPI), DDR4 protocol, and LVDS applications only. (36) The phase noise numbers in the table above are the maximum acceptable phase noise values measured at a carrier frequency of 100 MHz. To calculate the phase noise requirement at any other frequency, use the formula: REFCLK phase noise at f (MHz) = REFCLK phase noise at 100 MHz + (20 � log10 (f/100)). Intel� AgilexTM Device Data Sheet 30 Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Symbol tOUTPJ_DC (33) (37) tOUTCCJ_DC (33) (37) tOUTPJ_IO (38) (37) tOUTCCJ_IO (38) (37) tCASC_OUTPJ_DC (33) Parameter Condition 100 MHz Period jitter for dedicated clock output fOUT < 100 MHz (34) fOUT 100 MHz (34) Cycle-to-cycle jitter for dedicated clock output fOUT < 100 MHz (34) fOUT 100 MHz (34) Period jitter for clock output on the regular I/O fOUT < 100 MHz (34) fOUT 100 MHz (34) Cycle-to-cycle jitter for clock output on the regular I/O fOUT < 100 MHz (34) fOUT 100 MHz (34) Period jitter for dedicated clock output in cascaded PLLs fOUT < 100 MHz (34) fOUT 100 MHz (34) Min -- -- -- -- -- -- -- -- -- -- -- Typ -- -- -- -- -- -- -- -- -- -- -- Max �144 17.5 175 17.5 175 60 600 60 600 17.5 175 Unit dBc/Hz mUI (p-p) ps (p-p) mUI (p-p) ps (p-p) mUI (p-p) ps (p-p) mUI (p-p) ps (p-p) mUI (p-p) ps (p-p) Related Information � Memory Output Clock Jitter Specifications on page 46 Provides more information about the external memory interface clock output jitter specifications. � Intel Agilex Clocking and PLL User Guide Provides the recommended spread-spectrum clock profile and design guidelines to achieve 5% duty cycle using the LVDS SERDES Intel FPGA IP. (37) This jitter specification does not include the effect of spread-spectrum clock. The magnitude of jitter deterioration is largely depend on the spread-spectrum clock profile used. Refer to the Intel Agilex Clocking and PLL User Guide for the recommended spreadspectrum clock profile. (38) External memory interface clock output jitter specifications use a different measurement method, which are available in the Memory Output Clock Jitter Specifications for Intel Agilex Devices table. Send Feedback Intel� AgilexTM Device Data Sheet 31 Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 DSP Block Specifications Table 31. DSP Block Performance Specifications for Intel Agilex Devices For specification status, see the Data Sheet Status table Mode Performance �1V �2V �3V, �3E Fixed-point 18 � 19 900 771 676 multiplication mode Fixed-point 27 � 27 900 771 676 multiplication mode(39) Fixed-point 18 � 19 900 771 676 multiplier adder mode(39) Fixed-point 18 � 19 900 771 676 multiplier adder summed with 36-bit input mode(39) Fixed-point four 9 � 9 900 771 676 multiplier adder mode(39) Fixed-point 18 � 19 900 771 676 systolic mode Fixed-point 18 � 19 900 771 676 complex multiplication mode FP32 floating-point 750 579 507 multiplication mode FP32 floating-point adder 750 579 507 or subtract mode �4F, �4X 600 600 600 600 600 600 600 475 475 Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz continued... (39) When Chainout is enabled but systolic registers are not used, the performance specifications for the following speed grades are as follows: � �1V: 675 MHz � �2V: 578 MHz � �3V and �3E: 507 MHz � �4F and �4X: 450 MHz Intel� AgilexTM Device Data Sheet 32 Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Mode FP32 floating-point multiplier adder or subtract mode FP32 floating-point multiplier accumulate mode Addition or subtraction of two FP16 floating-point multiplication mode Sum/sub of two FP16 multiplications with FP32 (addition/subtraction) Sum/sub of two FP16 multiplications with accumulation (addition/ subtraction) FP32 floating-point complex multiplication FP32 floating-point vector dot product FP16 floating-point complex multiplication FP16 floating-point vector dot product �1V 750 750 750 750 750 750 750 750 750 �2V 579 Performance �3V, �3E 507 579 507 579 507 579 507 579 507 579 507 579 507 579 507 579 507 �4F, �4X 475 475 475 475 475 475 475 475 475 Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz Memory Block Specifications To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL and set to 50% output duty cycle. Use the Intel Quartus Prime software to report timing for the memory block clocking schemes. When you use the error detection cyclical redundancy check (CRC) feature, there is no degradation in fMAX. Send Feedback Intel� AgilexTM Device Data Sheet 33 Table 32. Memory Block Performance Specifications for Intel Agilex Devices For specification status, see the Data Sheet Status table Memory Mode Performance �1V �2V �3V, �3E MLAB Single-port RAM/ROM 1,000 782 667 Simple dual-port RAM M20K Block(40) Simple dual-port RAM with read-during-write option Single-port RAM/ROM Simple dual-port RAM 630 1,000 (HS) 850 (LP) 510 782 (HS) 664 (LP) 460 667 (HS) 567 (LP) Simple dual-port RAM, coherent read enabled 1,000 (HS) 850 (LP) 782 (HS) 664 (LP) 667 (HS) 567 (LP) Single-port RAM with the read-during-write option set to Old Data Simple dual-port RAM with the read-duringwrite option set to Old Data 800 (HS) 680 (LP) 640 (HS) 540 (LP) 560 (HS) 476 (LP) Simple dual-port RAM with ECC enabled, 512 � 32 600 (HS) 500 (LP) 480 (HS) 400 (LP) 420 (HS) 357 (LP) Simple dual-port RAM with ECC, optional pipeline registers enabled, 512 � 32 1,000 (HS) 850 (LP) 782 (HS) 664 (LP) 667 (HS) 567 (LP) Dual-port ROM True dual-port RAM 600 (HS) 500 (HS) 420 (HS) Simple quad-port RAM 600 (HS) 480 (HS) 420 (HS) eSRAM Simple dual-port 750 640 500 Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 �4F, �4X 600 330 600 (HS) 510 (LP) 600 (HS) 510 (LP) 480 (HS) 410 (LP) 360 (HS) 300 (LP) 600 (HS) 510 (LP) 360 (HS) 360 (HS) 500 Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz (40) For M20K block, timing/power optimization feature is available. The available options are High Speed (HS) and Low Power (LP). For details on this timing/power optimization feature, refer to the Agilex Embedded Memory User Guide. Intel� AgilexTM Device Data Sheet 34 Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Local Temperature Sensor Specifications Table 33. Local Temperature Sensor Specifications for Intel Agilex Devices For specification status, see the Data Sheet Status table Description Local Temperature Sensor Temperature Range �40 to 125�C(42) Accuracy �5�C Sampling Rate(41) 1 KSPS Conversion Time < 1 ms Remote Temperature Diode Specifications Note the following for the remote temperature diode specifications: � The temperature diode characteristics in this table target for three-currents temperature sensing chip implementation. The characteristics can also apply to two-currents temperature sensing chip implementation. � Absolute accuracy is dependent on third-party external diode ADC and integration specifics. Table 34. Remote Temperature Diode Specifications for Intel Agilex Devices (Core Fabric TSD) For specification status, see the Data Sheet Status table Description Min Typ Max Ibias, diode source current Vbias, voltage across diode Series resistance Diode ideality factor 10 0.43 -- -- -- -- -- 1.006(43) 170 0.75 <3 -- Unit A V -- (41) The read out is subject to the SDM mailbox activity status. (42) Temperature range refers to junction temperature. (43) When using lower injection current (two-currents) implementation, the ideality factor is 1.009. Send Feedback Intel� AgilexTM Device Data Sheet 35 Table 35. Remote Temperature Diode Specifications for Intel Agilex Devices (E-Tile TSD) For specification status, see the Data Sheet Status table Description Min Typ Max Ibias, diode source current 10 -- 170 Vbias, voltage across diode 0.56 -- 0.82 Series resistance -- -- <2 Diode ideality factor -- 1.005 -- Table 36. Remote Temperature Diode Specifications for Intel Agilex Devices (P-Tile TSD) For specification status, see the Data Sheet Status table Description Min Typ Max Ibias, diode source current Vbias, voltage across diode Series resistance Diode ideality factor 10 0.56 -- -- -- -- -- 1.0108(44) 170 0.87 <10 -- Table 37. Remote Temperature Diode Specifications for Intel Agilex Devices (R-Tile TSD) For specification status, see the Data Sheet Status table Description Min Typ Max Ibias, diode source current 20 Vbias, voltage across diode 0.5 Series resistance -- Diode ideality factor -- -- -- -- 1.000(45) 170 0.78 <10 -- Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Unit A V -- Unit A V -- Unit A V -- (44) When using lower injection current (two-currents) implementation, the ideality factor is 1.03. (45) When using lower injection current (two-currents) implementation, the ideality factor is 1.008. Intel� AgilexTM Device Data Sheet 36 Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Table 38. Remote Temperature Diode Specifications for Intel Agilex Devices (F-Tile TSD) For specification status, see the Data Sheet Status table Description Min Typ Max Ibias, diode source current 20 Vbias, voltage across diode 0.5 Series resistance -- Diode ideality factor -- -- -- -- 1.002(46) 170 0.78 <10 -- Voltage Sensor Specifications Table 39. Voltage Sensor Specifications for Intel Agilex Devices For specification status, see the Data Sheet Status table Parameter Minimum Resolution -- Sampling rate(47) -- Input capacitance -- Voltage sensor accuracy, Vin range: 0 V to 1.1 V(48) -- Unipolar Input Mode Input signal range for -- Vsigp Common mode voltage on -- Vsign Input signal range for -- Vsigp � Vsign Typical 7 -- -- -- -- -- -- Maximum -- 1 40 �3.5 1.35 0.25 1.1 Unit A V -- Unit Bit KSPS pF % V V V (46) When using lower injection current (two-currents) implementation, the ideality factor is 1.016. (47) The read out is subject to the SDM mailbox activity status. (48) For 1.8 V channel 3, 4, 5, and 9, the accuracy is �4.5%. Send Feedback Intel� AgilexTM Device Data Sheet 37 Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Periphery Performance Specifications This section describes the periphery performance, LVDS SERDES, and external memory interface. Actual achievable frequency depends on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system. LVDS SERDES Specifications Table 40. LVDS SERDES Specifications for Intel Agilex Devices LVDS serializer/deserializer (SERDES) block supports SERDES factor J = 3 to 10. DDR registers support SERDES factor J = 1 to 2. You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew margin, transmitter channel-to-channel skew, and receiver sampling margin to determine the leftover timing margin. For specification status, see the Data Sheet Status table Paramet Symbol Conditio er n �1 Speed Grade Min Typ Max �2 Speed Grade Min Typ Max Clock fHSCLK_in Clock 10 frequen (input boost cy clock factor W frequen = 1 to cy) True 40(49) Differen tial I/O Standar ds -- 800 10 -- 700 fHSCLK_in Clock 10 (input boost clock factor W frequen = 1 to cy) 40(49) Single- Ended -- 625 10 -- 625 �3 Speed Grade Min Typ Max 10 -- 625 10 -- 525 �4 Speed Grade Min Typ Max 10 -- 625 Unit MHz 10 -- 525 MHz continued... (49) Clock Boost Factor (W) is the ratio between the input data rate and the input clock rate. Intel� AgilexTM Device Data Sheet 38 Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Paramet Symbol Conditio er n I/O Standar ds fHSCLK_O -- UT (output clock frequen cy) Transmit ter True Differen tial I/O Standar ds fHSDR (data rate)(51) SERDES factor J = 4 to 10(52) (53) (54) SERDES factor J = 3(52) (53) (54) �1 Speed Grade Min Typ Max -- -- 800(50) 150 -- 1,600 150 -- 1,200 �2 Speed Grade Min Typ Max -- -- 700(50) 150 -- 1,434 150 -- 1,076 �3 Speed Grade Min Typ Max -- -- 625(50) 150 -- 1,250 150 -- 938 �4 Speed Grade Min Typ Max Unit -- -- 625(50) MHz 150 -- 1,000 Mbps 150 -- 600 Mbps continued... (50) This is achieved by using the PHY clock network. (51) Requires package skew compensation with PCB trace length. (52) The Fmax specification is based on the fast clock used for serial data. The interface Fmax is also dependent on the parallel clock domain which is design dependent and requires timing analysis. (53) The VCC and VCCP must be on a combined power layer and a maximum load of 5 pF for chip-to-chip interface. (54) The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource that you use. The I/O differential buffer and serializer do not have a minimum toggle rate. Send Feedback Intel� AgilexTM Device Data Sheet 39 Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Paramet Symbol Conditio er n SERDES factor J = 2, uses DDR register s SERDES factor J = 1, uses DDR register s tx Jitter True Differen tial I/O Standar ds Total jitter for data rate, 600 Mbps � 1.6 Gbps Total jitter for data rate, < 600 Mbps tDUTY (56) TX output clock duty cycle for �1 Speed Grade Min Typ Max 150 -- 840(55) 150 -- 420(55) 1,600 Mbps: 160 1,434 Mbps: 200 1,250 Mbps: 250 1,000 Mbps: 300 800 Mbps: 320 600 Mbps: 340 -- -- 0.21 45 50 55 �2 Speed Grade Min Typ Max 150 -- (55) 150 -- (55) 1,434 Mbps: 200 1,250 Mbps: 250 1,000 Mbps: 300 800 Mbps: 320 600 Mbps: 340 -- -- 0.21 45 50 55 �3 Speed Grade Min Typ Max 150 -- (55) 150 -- (55) 1,250 Mbps: 250 1,000 Mbps: 300 800 Mbps: 320 600 Mbps: 340 -- -- 0.21 45 50 55 �4 Speed Grade Min Typ Max 150 -- (55) Unit Mbps 150 -- (55) Mbps 1,000 Mbps: 300 ps 800 Mbps: 320 600 Mbps: 340 -- -- 0.21 UI 45 50 55 % continued... (55) The maximum ideal data rate is the SERDES factor (J) � the PLL maximum output frequency (fOUT) provided you can close the design timing and the signal integrity meets the interface requirements. (56) Not applicable for DIVCLK = 1. Intel� AgilexTM Device Data Sheet 40 Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Paramet Symbol Conditio er n Differen tial I/O Standar ds tRISE & tFALL (53) (57) True Differen tial I/O Standar ds TCCS (51) (56) True Differen tial I/O Standar ds Receiver True Differen tial I/O Standar ds fHSDRDPA (data rate) SERDES factor J = 4 to 10(52) (53) (54) SERDES factor J = 3(52) (53) (54) fHSDR (data rate) (without DPA)(51) SERDES factor J = 3 to 10 SERDES factor J = 2, uses �1 Speed Grade Min Typ Max -- -- 160 -- -- 330 150 -- 1,600 150 -- 1,200 (54) -- (58) (54) -- (55) �2 Speed Grade Min Typ Max -- -- 180 -- -- 330 150 -- 1,434 150 -- 1,076 (54) -- (58) (54) -- (55) �3 Speed Grade Min Typ Max -- -- 200 -- -- 330 150 -- 1,250 150 -- 938 (54) -- (58) (54) -- (55) �4 Speed Grade Min Typ Max Unit -- -- 220 ps -- -- 330 ps 150 -- 1,000 Mbps 150 -- 600 Mbps (54) -- (58) Mbps (54) -- (55) Mbps continued... (57) This applies to default pre-emphasis and VOD settings only. (58) You can estimate the achievable maximum data rate for non-DPA mode by performing link timing closure analysis. You must consider the board skew margin, transmitter delay margin, and receiver sampling margin to determine the maximum data rate supported. Send Feedback Intel� AgilexTM Device Data Sheet 41 Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Paramet Symbol Conditio er n DPA (FIFO mode) DPA (soft CDR mode) DDR register s SERDES factor J = 1, uses DDR register s DPA run -- length DPA run length SGMII/ GbE protocol All other protocol s Soft CDR mode Non DPA mode Soft- -- CDR ppm toleranc e Samplin -- g Window �1 Speed Grade Min Typ Max (54) -- (55) -- -- 10,000 -- -- 5 -- �300 -- 50 data transitio n per 208 UI -- 300 -- -- 330 �2 Speed Grade Min Typ Max (54) -- (55) -- -- 10,000 -- -- 5 -- �300 -- 50 data transitio n per 208 UI -- 300 -- -- 330 �3 Speed Grade Min Typ Max (54) -- (55) -- -- 10,000 -- -- 5 -- �300 -- 50 data transitio n per 208 UI -- 300 -- -- 330 �4 Speed Grade Min Typ Max (54) -- (55) -- -- 10,000 -- -- 5 -- �300 -- 50 data transitio n per 208 UI -- 300 -- -- 330 Unit Mbps UI UI -- ppm ps Intel� AgilexTM Device Data Sheet 42 Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 DPA Lock Time Specifications Table 41. DPA Lock Time Specifications for Intel Agilex Devices The DPA lock time is for one channel. One data transition is defined as a 0-to-1 or 1- to-0 transition. For specification status, see the Data Sheet Status table Standard Training Pattern Number of Data Transitions in One Repetition of the Training Pattern SPI-4 00000000001111111111 2 Parallel Rapid I/O 00001111 2 10010000 4 Miscellaneous 10101010 8 01010101 8 Number of Repetitions per 256 Data Transitions(59) 128 128 64 32 32 Maximum Data Transition 768 768 768 768 768 (59) This is the number of repetitions for the stated training pattern to achieve the 256 data transitions. Send Feedback Intel� AgilexTM Device Data Sheet 43 Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications Figure 2. LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications for a Data Rate Equal to 1.6 Gbps 25 8.5 Jitter Amplitude(UI) 0.22 0.1 Table 42. F1 F2 F3 F4 F1 F2 F3 F4 Jitter Frequency (Hz) LVDS SERDES Soft-CDR Sinusoidal Jitter Mask Values for a Data Rate Equal to 1.6 Gbps For specification status, see the Data Sheet Status table Parameter Jitter Frequency (Hz) Sinusoidal Jitter (UI) 10,000 25 17,565 25 1,493,000 0.22 50,000,000 0.22 Intel� AgilexTM Device Data Sheet 44 Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Figure 3. LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications for a Data Rate Less than 1.6 Gbps Sinusoidal Jitter Amplitude 20db/dec 0.1 UI P-P baud/1667 20 MHz Frequency Memory Standards Supported Table 43. Memory Standards Supported by Intel Agilex Devices This table lists the overall capability of External Memory Interface supported by Intel Agilex Devices. For specific details, refer to the External Memory Interface Spec Estimator. For specification status, see the Data Sheet Status table DDR4 SDRAM QDR IV SRAM DDR4 SDRAM Memory Standard Controller Type Hard memory controller Soft memory controller HPS hard memory controller 1,600 1,066 1,600 Maximum Frequency (MHz) Send Feedback Intel� AgilexTM Device Data Sheet 45 Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Related Information External Memory Interface Spec Estimator Provides the specific details of the memory standards supported. DLL Range Specifications Table 44. DLL Frequency Range Specifications for Intel Agilex Devices For specification status, see the Data Sheet Status table Parameter Performance (for All Speed Grades) DLL operating frequency range 600 � 1,600 DLL reference clock input Minimum 600 Unit MHz MHz Memory Output Clock Jitter Specifications The clock jitter specification applies to the memory output clock pins clocked by an I/O PLL, or generated using differential signal-splitter and double data I/O circuits clocked by a PLL output routed on a PHY clock network as specified. Intel recommends using PHY clock networks for better jitter performance. The memory clock output jitter is within the JEDEC specifications when the phase jitter (integration bandwidth 10 kHz to 50 MHz) of the input clock is not more than 20 ps peak-to-peak, or 1.42 ps RMS at 1e-12 BER and 1.22 ps at 1e-16 BER. E-Tile Transceiver Performance Specifications This section provides E-tile transceiver specifications and timing for Intel Agilex devices. E-Tile Transceiver Performance Table 45. E-Tile Transmitter and Receiver Data Rate Performance Specifications For specification status, see the Data Sheet Status table Symbol/Description Condition Transceiver Speed Grade Supported data rate(60) NRZ PAM4 �1 28.9 57.8(61) �2 28.3 56 �3 17.4 32 Unit Gbps Gbps Intel� AgilexTM Device Data Sheet 46 Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 E-Tile Transceiver Reference Clock Specifications Table 46. E-Tile Reference Clock LVPECL DC Electrical Characteristics For specification status, see the Data Sheet Status table Symbol Refclk Parameter Min Typ VTT Termination voltage (2.5 V 0.4 0.5 compliant) Termination voltage (3.3 V 1.04 1.3 compliant) RTT Termination resistor 40 50 VDIFF Differential voltage 0.4 0.8 VCM Input common mode VDIFF/2 -- voltage (2.5 V compliant, no internal termination resistor) Input common mode voltage (2.5 V compliant, internal termination resistor) VCCCLK_GXE � 1.6 VCCCLK_GXE � 1.3 Input common mode VDIFF/2 -- voltage (3.3 V compliant, no internal termination resistor) Input common mode 1.4 2 voltage (3.3 V compliant, internal termination resistor) Max 0.6 1.56 60 1.2 VCCCLK_GXE � VDIFF/2 VCCCLK_GXE � 1.0 VCCCLK_GXE � VDIFF/2 2.6 Unit V V V V V V V (60) The supported data rate is for chip-to-chip and backplane links. (61) Two channels are combined to support up to 57.8 Gbps. Send Feedback Intel� AgilexTM Device Data Sheet 47 Table 47. E-Tile Reference Clock Electrical and Jitter Requirements For specification status, see the Data Sheet Status table Parameter Condition Min Frequency -- 125 Frequency tolerance -- �100 Clock duty cycle -- 45 Rise/Fall times 20% to 80% 40 Phase jitter 12 kHz to 20 MHz -- Phase noise(62) 10 kHz -- 100 kHz -- 500 kHz -- 3 MHz -- 10 MHz -- 20 MHz -- Typ 156.25 -- 50 -- 0.375 -- -- -- -- -- -- E-Tile Transmitter Specifications Table 48. E-Tile Transmitter Specifications For specification status, see the Data Sheet Status table Symbol/Description Condition Min Transmitter differential No precursor/postcursor -- output voltage peak-to- de-emphasis peak Transmitter common mode -- voltage Typ 0.965 VCCRT_GXE/2 Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Max 700 100 55 300 0.5 �130 �138 �138 �140 �144 �146 Unit MHz ppm % ps ps rms dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz Max -- Unit V V (62) The phase noise numbers in this table are the maximum acceptable phase noise values measured at a carrier frequency of 156.25 MHz. To calculate the phase noise requirement at any other frequency, use the formula: REFCLK phase noise at f (MHz) = REFCLK phase noise at 156.25 MHz + 20*log10(f/156.25). Intel� AgilexTM Device Data Sheet 48 Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 E-Tile Receiver Specifications Table 49. E-Tile Receiver Specifications For specification status, see the Data Sheet Status table Symbol/Description Condition Min Absolute VMAX for a NRZ -- receiver pin PAM4 -- Maximum peak-to-peak -- differential input voltage VID (diff p-p) before/after device configuration VCM (Internal AC coupled)(63) Receiver run length(64) NRZ PAM4 -- GND GND + 0.3 -- DC input impedance -- 40 DC differential input -- 80 impedance Powered down DC input impedance Receiver pin impedance when the receiver termination is powered down 100k Differential termination From DC to 100 MHz 80 PPM tolerance Allowed frequency -- mismatch between REFCLK and RX data Typ VCCH_GXE + 0.3 VCCH_GXE 1.2 -- -- -- -- 100 -- 100 -- Max -- -- VCCH_GXE VCCH_GXE � 0.3 100(65) 60 120 -- 120 750 Unit V V V V V symbols ppm (63) This value uses internal AC coupling. External coupling capacitors are required beyond the range mentioned in this table. (64) No additional transition density requirements apply. (65) The incoming data must be statistically DC-balanced. Send Feedback Intel� AgilexTM Device Data Sheet 49 Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 P-Tile Transceiver Performance Specifications This section provides P-tile transceiver specifications and timing for Intel Agilex devices. P-Tile Transceiver Performance Table 50. P-Tile Transmitter and Receiver Data Rate Performance For specification status, see the Data Sheet Status table Symbol/Description Condition Gen 1 Gen 2 Supported data rate PCIe* 2.5 5 Gen 3 8 Gen 4 16 Table 51. P-Tile PLLA Performance For specification status, see the Data Sheet Status table Symbol/Description Condition Min VCO frequency -- -- PLL bandwidth (BWTX- PCIe 2.5 GT/s 1.5 PKG_PLL1)(66) PCIe 5.0 GT/s 8 PLL bandwidth (BWTX- PCIe 5.0 GT/s 5 PKG_PLL2)(66) PLL peaking (PKGTX-PLL1) PCIe 2.5 GT/s -- PCIe 5.0 GT/s -- PLL peaking (PKGTX- PCIe 5.0 GT/s 1 PLL2)(66) Transceiver Speed Grade Typ 5 -- -- -- -- -- -- Max -- 22 16 16 3 3 -- Unit Gbps Unit GHz MHz MHz MHz dB dB dB (66) The Tx PLL bandwidth must lie between the minimum and maximum ranges given in this table. PLL peaking must lie below the value in this table. Note that the PLL bandwidth extends from zero up to the values specified in this table. The PLL bandwidth is defined at the point where its transfer function crosses the �3 dB point. Intel� AgilexTM Device Data Sheet 50 Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Table 52. P-Tile PLLB Performance For specification status, see the Data Sheet Status table Symbol/Description Condition Min VCO frequency -- -- PLL bandwidth (BWTX- PCIe 8.0 GT/s 2 PKG_PLL1)(67) PCIe 16.0 GT/s 2 PLL bandwidth (BWTX- PCIe 8.0 GT/s 2 PKG_PLL2)(67) PCIe 16.0 GT/s 2 PLL peaking (PKGTX- PCIe 8.0 GT/s -- PLL1)(67) PCIe 16.0 GT/s -- PLL peaking (PKGTX- PCIe 8.0 GT/s -- PLL2)(67) PCIe 16.0 GT/s -- P-Tile Transceiver Reference Clock Specifications Table 53. P-Tile Reference Clock Specifications For specification status, see the Data Sheet Status table Symbol/Description Condition Min Supported I/O standards -- Input reference clock -- frequency(68) 99.97 Transceiver Speed Grade Typ 8 -- -- -- -- -- -- -- -- All Transceiver Speed Grades Typ HCSL 100 Max -- 4 4 5 5 2 2 1 1 Max 100.03 Unit GHz MHz MHz MHz MHz dB dB dB dB Unit -- MHz continued... (67) The Tx PLL bandwidth must lie between the minimum and maximum ranges given in this table. PLL peaking must lie below the value in this table. Note that the PLL bandwidth extends from zero up to the values specified in this table. The PLL bandwidth is defined at the point where its transfer function crosses the �3 dB point. Send Feedback Intel� AgilexTM Device Data Sheet 51 Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Symbol/Description Condition Rising edge rate(69) Falling edge rate(69) Duty cycle Spread-spectrum modulating clock frequency Spread-spectrum downspread Absolute VMAX Absolute VMIN Peak-to-peak differential input voltage VICM (DC coupled) Cycle to cycle jitter (TCCJITTER)(70) TSSC-MAX-PERIOD-SLEW PCIe PCIe PCIe -- -- -- -- -- HCSL I/O standard for PCIe reference clock PCIe Max SSC df/dt Min 0.6 0.6 40 30 �0.5 -- -- 300 250 -- -- Related Information � PCI Express Base Specification Revision 3.0 � PCI Express Base Specification Revision 4.0 All Transceiver Speed Grades Typ -- -- -- -- -- -- -- -- -- -- -- Max 4 4 60 33 0 1.15 �0.3 1,500 550 150 1,250 Unit V/ns V/ns % kHz % V V mV mV ps ppm/s (68) This number is with spread spectrum clocking (SSC) turned off. For systems with spread spectrum clocking, follow the specifications in Section 8.6.3 Data Rate Independent Refclk Parameters in the PCI Express* Base Specification Revision 4.0. (69) Measured from �150 mV to +150 mV on the differential waveform. The 300 mV measurement window is centered on the differential zero crossing. (70) For common reference clock architecture, follow the jitter limit specified in the PCI Express* Card Electromechanical Specification for 2.5 GT/s, Section 4.3.7 Refclk Specifications for 5.0 GT/s and Section 4.3.8 Refclk Specifications for 8.0 GT/s in the PCI Express Base Specification Revision 3.0, and Section 8.6 Refclk Specifications for 16.0 GT/s in the PCI Express Base Specification Revision 4.0. Intel� AgilexTM Device Data Sheet 52 Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 P-Tile Transmitter Specifications Table 54. P-Tile Transmitter Specifications For specification status, see the Data Sheet Status table Symbol/Description Condition Min Supported I/O standards PCIe Differential on-chip PCIe 80 termination resistors Differential peak-to-peak PCIe 2.5 GT/s 800 voltage for full swing PCIe 5.0 GT/s 800 PCIe 8.0 GT/s 800 PCIe 16.0 GT/s 800 Differential peak-to-peak PCIe 8.0 GT/s and 16.0 250 voltage during EIEOS GT/s Lane-to-lane output skew PCIe 2.5 GT/s -- PCIe 5.0 GT/s -- PCIe 8.0 GT/s -- PCIe 16.0 GT/s -- P-Tile Receiver Specifications Table 55. P-Tile Receiver Specifications For specification status, see the Data Sheet Status table Symbol/Description Condition Min Supported I/O standards PCIe Peak-to-peak differential input voltage VID (diff p-p) PCIe 2.5 GT/s(71) PCIe 5.0 GT/s(71) 175(72) 100(72) All Transceiver Speed Grades Typ High Speed Differential I/O -- -- -- -- -- -- -- -- -- -- All Transceiver Speed Grades Typ High Speed Differential I/O -- -- Send Feedback Max 120 1,100 1,100 1,100 1,100 -- 2.5 2 1.5 1.25 Unit -- mV mV mV mV mV ns ns ns ns Max 1,200 1,200 Unit -- mV mV continued... Intel� AgilexTM Device Data Sheet 53 Symbol/Description Condition Differential on-chip termination resistors RESREF(74) RREF PCIe 8.0 GT/s PCIe 16.0 GT/s -- -- -- Min 25(72) 15(72) 80 167.3 2.772 Related Information PCI Express Base Specification Revision 4.0 All Transceiver Speed Grades Typ -- -- -- 169 2.8 Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Max --(73) --(73) 120 170.7 2.828 Unit mV mV k (71) Voltage shown for PCIe 2.5 GT/s and 5.0 GT/s are at the package pins (TP2). (72) For PCIe at 2.5 GT/s and 5 GT/s, the VID is measured at TP2, which is the accessible test point at the device under test. For PCIe 8.0 GT/s and 16.0 GT/s, the VID is measured at TP2P. TP2P defines a reference point that comprehends the effects of the behavioral Rx package plus Rx equalization and represents the only location where a meaningful eye height and eye width limits can be defined. (73) The maximum eye height value depends on the transmitter launch voltage maximum value. Refer to the PCIe Express Base Specification Rev. 4.0 for the generator (TX) launch voltage value. (74) Connecting RESREF at 169 calibrates PCIe channel on-chip termination to 85 . Intel� AgilexTM Device Data Sheet 54 Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 R-Tile Transceiver Performance Specifications R-Tile Transceiver Performance Table 56. R-Tile Transmitter and Receiver Data Rate Performance for Intel Agilex Devices For specification status, see the Data Sheet Status table Symbol/ Condition Descriptio n Transceiver Speed Grade �1 �2 Gen1 Gen2 Gen3 Gen4 Gen5 Gen1 Gen2 Gen3 Supported data rate PCIe CXL 2.5 5 8 16 32 2.5 5 8 -- -- 8 16 32 -- -- -- Gen4 16 -- Table 57. R-Tile Slow PLL Performance for Intel Agilex Devices For specification status, see the Data Sheet Status table Symbol/Description Condition All Transceiver Speed Grades Min Typ VCO frequency PCIe -- 10 CXL -- -- PLL bandwidth (BWTXPKG_PLL1)(75) PCIe 2.5 GT/s PCIe 5.0 GT/s 1.5 -- 8 -- CXL 2.5 GT/s -- -- CXL 5.0 GT/s -- -- PLL bandwidth BWTXPKG_PLL2)(75) PCIe 2.5 GT/s PCIe 5.0 GT/s -- -- 5 -- Max -- -- 22 16 -- -- -- 16 Gen5 32 -- Unit Gbps Gbps Unit GHz GHz MHz MHz MHz MHz MHz MHz continued... (75) The Tx PLL bandwidth must lie between the minimum and maximum ranges given in this table. PLL peaking must lie below the value in this table. Note that the PLL bandwidth extends from zero up to the values specified in this table. The PLL bandwidth is defined at the point where its transfer function crosses the �3 dB point. Send Feedback Intel� AgilexTM Device Data Sheet 55 Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Symbol/Description Condition PLL peaking (PKGTXPLL1)(75) PLL peaking (PKGTXPLL2)(75) CXL 2.5 GT/s CXL 5.0 GT/s PCIe 2.5 GT/s PCIe 5.0 GT/s CXL 2.5 GT/s CXL 5.0 GT/s PCIe 2.5 GT/s PCIe 5.0 GT/s CXL 2.5 GT/s CXL 5.0 GT/s Min -- -- -- -- -- -- -- 1 -- -- All Transceiver Speed Grades Typ -- -- -- -- -- -- -- -- -- -- Table 58. R-Tile Fast PLL Performance for Intel Agilex Devices For specification status, see the Data Sheet Status table Symbol/Description Condition All Transceiver Speed Grades Min Typ VCO frequency PCIe -- 16 CXL -- 16 PLL bandwidth (BWTX- PCIe 8.0 GT/s 0.5 -- PKG_PLL1)(76) PCIe 16.0 GT/s 0.5 -- PCIe 32.0 GT/s 0.5 -- CXL 8.0 GT/s 0.5 -- Max -- -- 3 3 -- -- -- -- -- -- Max -- -- 4 4 1.8 4 Unit MHz MHz dB dB dB dB dB dB dB dB Unit GHz GHz MHz MHz MHz MHz continued... (76) The Tx PLL bandwidth must lie between the minimum and maximum ranges given in this table. PLL peaking must lie below the value in this table. Note that the PLL bandwidth extends from zero up to the values specified in this table. The PLL bandwidth is defined at the point where its transfer function crosses the �3 dB point. Intel� AgilexTM Device Data Sheet 56 Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Symbol/Description Condition PLL bandwidth (BWTXPKG_PLL2)(76) PLL peaking (PKGTXPLL1)(76) PLL peaking (PKGTXPLL2)(76) CXL 16.0 GT/s CXL 32.0 GT/s PCIe 8.0 GT/s PCIe 16.0 GT/s PCIe 32.0 GT/s CXL 8.0 GT/s CXL 16.0 GT/s CXL 32.0 GT/s PCIe 8.0 GT/s PCIe 16.0 GT/s PCIe 32.0 GT/s CXL 8.0 GT/s CXL 16.0 GT/s CXL 32.0 GT/s PCIe 8.0 GT/s PCIe 16.0 GT/s PCIe 32.0 GT/s CXL 8.0 GT/s CXL 16.0 GT/s CXL 32.0 GT/s Min 0.5 0.5 0.5 0.5 -- 0.5 0.5 -- -- -- -- -- -- -- -- -- -- -- -- -- All Transceiver Speed Grades Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max 4 1.8 5 5 -- 5 5 -- 2 2 2 2 2 2 1 1 -- 1 1 -- Unit MHz MHz MHz MHz -- MHz MHz -- dB dB dB dB dB dB dB dB -- dB dB -- Send Feedback Intel� AgilexTM Device Data Sheet 57 Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 R-Tile Transceiver Reference Clock Specifications Table 59. R-Tile Reference Clock Specifications for Intel Agilex Devices For specification status, see the Data Sheet Status table Symbol/Description Condition All Transceiver Speed Grades Min Typ Supported I/O standards PCIe HCSL CXL HCSL Refclk frequency for devices that support 32.0 GT/s(77) Rising edge rate(78) PCIe CXL PCIe 99.99 100 99.99 100 0.6 -- Falling edge rate(78) CXL PCIe 0.6 -- 0.6 -- CXL 0.6 -- Duty cycle PCIe 40 -- CXL 40 -- Absolute VMAX PCIe CXL -- -- -- -- Absolute VMIN PCIe CXL -- -- -- -- Peak-to-peak differential input voltage PCIe CXL 300 -- 300 -- Max 100.01 100.01 4 4 4 4 60 60 1.15 1.15 �0.3 �0.3 1,450 1,450 Unit -- -- MHz MHz V/ns V/ns V/ns V/ns % % V V V V mV mV continued... (77) This number is with spread-spectrum clocking (SSC) turned off. For systems with spread spectrum clocking, follow the specifications in Section 8.6 Refclk Specifications of PCI Express Base Specification Revision 5.0 Version 1.0. (78) Measured from �150 mV to +150 mV on the differential waveform. The 300 mV measurement window is centered on the differential zero crossing. Intel� AgilexTM Device Data Sheet 58 Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Symbol/Description Condition Vcross PCIe CXL Cycle-to-cycle jitter (TCCJITTER)(79) PCIe CXL Spread-spectrum modulating clock frequency PCIe CXL SSC deviation for devices that support 32.0 GT/s and SRIS when operating in SRIS mode at all speeds PCIe CXL TSSC-MAX-PERIOD-SLEW Max SSC df/dt for PCIe Max SSC df/dt for CXL Min 250 250 -- -- 30 30 �0.3 �0.3 -- -- All Transceiver Speed Grades Typ -- -- -- -- -- -- -- -- -- -- Related Information PCI Express Base Specification Revision 5.0 R-Tile Transmitter Specifications Table 60. R-Tile Transmitter Specifications for Intel Agilex Devices For specification status, see the Data Sheet Status table Symbol/Description Condition All Transceiver Speed Grades Min Typ Supported I/O standards PCIe High-Speed Differential I/O CXL High-Speed Differential I/O Max 550 550 150 150 33 33 0 0 1,250 1,250 Max Unit mV mV ps ps kHz kHz % % ppm/�s ppm/�s Unit -- -- continued... (79) For common reference clock architecture, you must meet the jitter limit specified in Section 8.6 Refclk Specifications of PCI Express Base Specification Revision 5.0 Version 1.0. Send Feedback Intel� AgilexTM Device Data Sheet 59 Symbol/Description Condition Differential on-chip termination resistors Differential peak-to-peak voltage for full swing Differential peak-to-peak voltage during EIEOS Lane-to-lane output skew PCIe CXL PCIe 2.5 GT/s PCIe 5.0 GT/s PCIe 8.0 GT/s PCIe 16.0 GT/s PCIe 32.0 GT/s CXL 8.0 GT/s CXL 16.0 GT/s CXL 32.0 GT/s PCIe 8.0 GT/s, 16.0 GT/s, and 32.0 GT/s CXL 8.0 GT/s, 16.0 GT/s, and 32.0 GT/s PCIe 2.5 GT/s PCIe 5.0 GT/s PCIe 8.0 GT/s PCIe 16.0 GT/s PCIe 32.0 GT/s CXL 8.0 GT/s CXL 16.0 GT/s CXL 32.0 GT/s Min 80 80 800 800 800 800 800 800 800 800 250 250 -- -- -- -- -- -- -- -- All Transceiver Speed Grades Typ 100 100 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Max 120 120 1,200 1,200 1,300 1,300 1,300 1,300 1,300 1,300 -- -- 2.5 2 1.5 1.25 1.25 1.5 1.25 1.25 Unit mV mV mV mV mV mV mV mV mV mV ns ns ns ns ns ns ns ns Intel� AgilexTM Device Data Sheet 60 Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 R-Tile Receiver Specifications Table 61. R-Tile Receiver Specifications for Intel Agilex Devices For specification status, see the Data Sheet Status table Symbol/Description Condition All Transceiver Speed Grades Min Typ Supported I/O standards PCIe High-Speed Differential I/O CXL Peak-to-peak differential input voltage VID (diff p-p) PCIe 2.5 GT/s(80) PCIe 5.0 GT/s(80) PCIe 8.0 GT/s(80) PCIe 16.0 GT/s(80) PCIe 32.0 GT/s(80) CXL 8.0 GT/s(80) CXL 16.0 GT/s(80) CXL 32.0 GT/s(80) High-Speed Differential I/O 175 -- 100 -- 25 -- 15 -- 15 -- 25 -- 15 -- 15 -- Differential on-chip termination resistors RCOMP PCIe CXL PCIe (81) CXL(81) 80 100 80 100 148.5 150 148.5 150 Max 1,200 1,200 1,200 800 800 1,200 800 800 120 120 151.5 151.5 Unit -- -- mVPP mVPP mVPP mVPP mVPP mVPP mVPP mVPP (80) For PCIe at 2.5 GT/s and 5 GT/s, VID is measured at TP2, which is the accessible test point at the device under test. For PCIe and CXL 8.0 GT/s, 16.0 GT/s and 32.0 GT/s, VID is measured at TP2P. TP2P defines a reference point that comprehends the effects of the behavioral Rx package plus Rx equalization and represents the only location where a meaningful eye height and eye width limits can be defined. (81) Connecting RCOMP at 150 calibrates PCIe and CXL channel on-chip termination to 100 . Send Feedback Intel� AgilexTM Device Data Sheet 61 Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 F-Tile Transceiver Performance Specifications F-Tile Transceiver Performance Table 62. F-Tile FHT Transmitter and Receiver Data Rate Performance for Intel Agilex Devices For specification status, see the Data Sheet Status table Symbol/Description Condition Transceiver Speed Grade �1 �2 �3 Supported data rate NRZ 24�29, 48�58 24�29 24�29 PAM4 48�58, 96�116 48�58 48�58 Table 63. F-Tile FGT Transmitter and Receiver Data Rate Performance for Intel Agilex Devices For specification status, see the Data Sheet Status table Symbol/Description Condition Transceiver Speed Grade �1 �2 �3 Supported data rate NRZ 1�32 1�32 1�17.4 PAM4 20�58.125 20�58.125 20�32 F-Tile Transceiver Reference Clock Specifications Table 64. F-Tile FHT Reference Clock Requirements for Intel Agilex Devices For specification status, see the Data Sheet Status table Parameter Description Condition Min Typical Frequency Reference clock -- frequency 100 100 156.25 Frequency accuracy Frequency accuracy of -- the reference clock, including temperature variability, aging, and initial variation -- -- Max 200 �100 Unit Gbps Gbps Unit Gbps Gbps Unit MHz ppm continued... Intel� AgilexTM Device Data Sheet 62 Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Parameter Description Condition Single sideband phase noise Measured SSB phase noise must be smaller than phase noise mask(82) 10 kHz 100 kHz 500 kHz 3 MHz 10 MHz 20 MHz 1 GHz Integrated RMS jitter Integrated over 10 -- kHz � 20 MHz, include spurious Min -- -- -- -- -- -- -- -- Typical �130 �138 �138 �140 �144 �146 �146 (83) -- Table 65. F-Tile FHT Reference Clocks Input Specifications for Intel Agilex Devices For specification status, see the Data Sheet Status table Parameter Description Condition Min Typical TREF-DUTY TREF-RISE/FALL Duty cycle -- Rising and falling edge 20% � 80% rate 45 50 40 -- TREF-SINGLEEND-SKEW Skew between -- REFCLKP and REFCLKN -- -- ZREF-SINGLEEND-DC Reference clock input -- impedance � terminated mode 40 50 VREFIN-SE-PP Input reference clock -- single-ended peak-topeak voltage 200 -- Max -- -- -- -- -- -- -- 522 Max 55 300 5 60 510 Unit dB dB dB dB dB dB dB fs Unit % ps ps mV continued... (82) Add an offset of 20 � log10(Fclk/156.25 MHz) dB to mask values, where Fclk is reference clock frequency. (83) The phase noise mask requirement between 20 MHz and 1 GHz excludes any harmonics power of the fundamental clock. Send Feedback Intel� AgilexTM Device Data Sheet 63 Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Parameter VREFIN-CM-AC VREFIN-IL-DC VREFIN-IH-DC Description Condition Input reference clock -- common-mode voltage when ACcoupled on board Input reference clock -- input low voltage when DC-coupled on board Input reference clock -- input high voltage when DC-coupled on board Min 0.1 -- Typical Set on-chip -- -- Table 66. F-Tile FGT Reference Clock Input Specifications for Intel Agilex Devices For specification status, see the Data Sheet Status table Parameter FREF Description Reference clock operating frequency Condition -- Min 100(84) Typical -- TREF-DUTY TREF-RISE/FALL Duty cycle -- Rising and falling edge 20% � 80% rate 45 50 -- -- TREF-SINGLEEND-SKEW Skew between -- REFCLKP and REFCLKN -- -- ZREF-DIFF-DC Reference clock -- differential input impedance � terminated mode 80 100 VREFIN-DIFF-AC Input reference clock -- differential peak-topeak voltage when AC-coupled on board 0.6 1.2 Max -- 0.9 Max 380 55 0.15 50 120 1.7 Unit -- V V Unit MHz % TREF ps Vpp-diff continued... (84) This value is 100 MHz for down SSC (Spread Spectrum Clocking) clocking. This value can also be 25 MHz for HDMI rate of less than 1 Gbps. Intel� AgilexTM Device Data Sheet 64 Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Parameter VREFIN-IL-DC VREFIN-IH-DC PNREF-SSB VREFIN-RJ-RMS VREFIN-PPM-ERROR Description Condition Input reference clock -- input low voltage when DC-coupled on board Input reference clock -- input high voltage when DC-coupled on board Reference clock measured single sideband phase noise mask including spurs must be smaller than phase noise mask(85) 10 kHz 100 kHz 500 kHz 3 MHz 10 MHz 20 MHz 1 GHz RMS jitter integrated -- from 10 kHz � 20 MHz including spurs Reference clock -- frequency error Min �0.15 0.66 -- -- -- -- -- -- -- -- �350 + SSC Typical 0 0.7 �130 �138 �138 �140 �144 �146 �146 -- -- Max 0.15 0.85 -- -- -- -- -- -- -- 522 +350 + SSC Table 67. F-Tile FGT Reference Clock Output Driver Specifications for Intel Agilex Devices For specification status, see the Data Sheet Status table Parameter Description Condition Min Typical FREF_OUT Reference clock -- operating frequency 25 -- TREF-DUTY_OUT TREF-RISE_OUT/FALL_OUT Duty cycle -- Rising and falling edge 20% � 80% rate 45 50 -- -- Max 800 55 0.15 (85) Add an offset of 20 � log10(Fcc/Hzlk/156.25 MHz) dB to mask values, where Fclk is reference clock frequency. Unit V V dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz fs ppm Unit MHz % TREF continued... Send Feedback Intel� AgilexTM Device Data Sheet 65 Parameter TREF-SINGLEEND-SKEW ZREF-DIFF-DC_OUT VREFIN-DIFF-AC_OUT VREFIN-CM-OUT Description Skew between -- REFCLKP and REFCLKN Reference clock -- differential output impedance � terminated mode Output reference clock -- differential peak to peak voltage when AC-coupled on board Output reference clock -- common-mode Condition Min -- 80 0.9 0.45 F-Tile Transmitter Specifications Table 68. F-Tile FHT Transmitter Electrical Specifications For specification status, see the Data Sheet Status table Parameter Symbol Description Output eye specifications VTX-DIFF-PKPK Transmit amplitude (low frequency) VTX-DEEMP_STEP Transmit tap resolution for c(0), c(1), and c(�1) Transmit tap resolution for c(�2) TTX-SLEW TTX-DJ TTX-RJ Rise/fall time Even-odd jitter J3u(86) JRMS(86) Min 800 0.5 0.5 8 -- -- -- (86) CDR bandwidth is at 4 MHz. Intel� AgilexTM Device Data Sheet 66 Typical -- 100 1 0.5 Typical -- -- -- -- -- -- -- Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Max 50 120 Unit ps 1.1 Vpp-diff 0.55 V Max 1,200 5 2.5 -- 0.025 0.106 0.023 Unit mVdiff-pkpk % % ps UIpkpk UIpkpk UIRMS continued... Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Parameter Transmitter DC impedance Symbol ZTX-DIFF-DC ZTX-CM-DC Transmitter return loss ZRL-DIFF-DC ZRL-DIFF-NYQ ZRL-CMN Electrical idle VTX-IDLE VCM-DELTA-SQUELCH TTX-IDLE-LATENCY Description Transmitter output differential DC impedance 100 W mode while configured Transmitter output common-mode DC impedance Transmitter differential DC return loss Transmitter differential return loss at Nyquist frequency (FBAUD/2) Transmitter commonmode return loss below 10 GHz Idle output voltage Maximum commonmode step entering/ exiting squelch mode Latency entering/ exiting idle (cold boot) Power state cycle (reestablish CM) Table 69. F-Tile FGT Transmitter Electrical Specifications For specification status, see the Data Sheet Status table Parameter Symbol Description Output eye specifications VTX-DIFF-PKPK Back-porch transmit amplitude VTX-EYE-PKPK Transmit eye voltage opening VTX-DEEMP_STEP Transmit tap resolution Min 80 20 -- -- -- -- -- -- -- Min 300 300 -- Send Feedback Typical 100 25 -- -- -- -- -- -- -- Typical -- -- -- Max 120 30 �14.5 �8 �6 50 100 28 5 Unit W W dB dB dB mVpkpk mV ms �s Max 1,050 1,051 2 Unit mVdiff-pkpk mVdiff-pkpk % continued... Intel� AgilexTM Device Data Sheet 67 Parameter Symbol DTX-N+2-DEEMP DTX-N+1-DEEMP DTX-N-1-DEEMP TTX-SLEW TTX-DJ TTX-RJ TTX-TJ Transmitter DC impedance ZTX-DIFF-DC ZTX-CM-DC Transmitter return loss ZRL-DIFF-DC ZRL-DIFF-NYQ Description N+2 precursor tap deemphasis N+1 precursor tap deemphasis N-1 postcursor tap deemphasis Rise/fall time at 20%� 80% Transmit deterministic jitter at 25 Gbps Transmit total peakpeak random jitter(87) Transmit total peakpeak jitter (TTX-TJ = TTX-DDJ + TTX-PJ + TTXRJ)(87) Transmitter output differential DC impedance 100 W mode while configured(88) Transmitter output common-mode DC impedance Transmitter differential DC return loss Transmitter differential return loss at Nyquist frequency (FBAUD/2) Min 0 0 0 10 -- -- -- 80 20 -- -- Typical -- -- -- -- -- -- -- 100 25 -- -- (87) Assume a 1st order high-pass jitter measurement filter with a cutoff of Fbaud/Fgpll = Ngpll. (88) TX pins are driven to 0 V before mode configuration. Intel� AgilexTM Device Data Sheet 68 Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Max 2.5 4.5 6.5 20 0.15 0.15 0.28 Unit dB dB dB ps UIpkpk UIpkpk UIpkpk 120 W 30 W 12 dB �6 dB continued... Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Parameter Electrical idle Symbol ZRL-CMN VTX-IDLE VCM-DELTA-SQUELCH TTX-IDLE-LATENCY Receiver detect VTX-RCV-DETECT Lane-to-lane output -- skew -- Description Transmitter commonmode return loss below 10 GHz Idle output voltage Maximum commonmode step entering/ exiting squelch mode Latency entering/ exiting idle (cold boot), power state cycle (re-establish CM) Voltage change allowed during receiver detection Lane count 8 Lane count = 16 F-Tile Receiver Specifications Table 70. F-Tile FHT Receiver Electrical Specifications For specification status, see the Data Sheet Status table Parameter Symbol Description Receiver input eye specifications VRX-DIFF-PKPK Receiver input differential peak-topeak voltage VRX-CM-DC Receiver input DC common-mode voltage(89) VRX-MAX Receiver input maximum voltage Min -- -- -- -- -- -- -- Min Closed eye 100 -- Typical -- -- -- -- -- -- -- Typical -- 750 -- (89) Referenced to RX GND. This specification is also supported before mode configuration. Send Feedback Max �6 20 100 8 600 2 UI + 200 ps 2 UI + 300 ps Unit dB mVpkpk mV �s mV ps ps Max 1,200 900 1,200 Unit mVdiff-pkpk mV mV continued... Intel� AgilexTM Device Data Sheet 69 Parameter Symbol VRX-MIN TRX-DDJ TRX-RJ TRX-PJ Equalizer specifications Receiver return loss TRX-TJ FPPM-OFFSET ZRL-DIFF-DC ZRL-DIFF-NYQ ZRL-CM Receiver DC impedance RDIFF-DC RCM-DC Description Receiver input minimum voltage Receive input signal data dependent jitter (inter-symbol interference) Receive input random jitter Receive input periodic jitter (at high frequency) Receive input total jitter (DDJ + RJ + PJ) Tolerable data frequency offset Receiver differential DC return loss Receiver differential return loss at Nyquist frequency (FBAUD/2) Receiver commonmode return loss below 10 GHz DC differential receive impedance DC common-mode receive impedance Min �200 -- -- -- -- �200 -- -- -- 80 20 Typical -- -- -- -- -- -- -- -- -- 100 25 Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Max -- 1 Unit mV UIpkpk 0.15 0.05 1 200 �10 �6 �6 120 30 UIpkpk UIpkpk UIpkpk ppm dB dB dB W W Intel� AgilexTM Device Data Sheet 70 Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Table 71. F-Tile FGT Receiver Electrical Specifications For specification status, see the Data Sheet Status table Parameter Symbol Description Receiver input eye specifications VRX-DIFF-PKPK Receiver input differential peak-topeak voltage VRX-MAX Receiver input maximum voltage(90) VRX-MIN Receiver input minimum voltage(90) VRX-CM-DC Receiver input DC common-mode voltage(91) TRX-RJ Receive input random jitter TRX-PJ Receive input periodic jitter (at high frequency) Insertion loss specifications IINS-LOSS-56Gb/s Insertion loss at 56 Gbps PAM42/BER <10�4 IINS-LOSS-53Gb/s Insertion loss at 53 Gbps PAM42/BER <10�4 IINS-LOSS-30Gb/s Insertion loss at 32 Gbps NRZ(93) /BER <10�12 Min -- -- �0.3 0 -- -- -- 5(92) -- Typical -- -- -- -- -- -- -- -- -- Max 1,200 1 -- 700 0.15 0.05 30 -- 30 Unit mVdiff-pkpk V V mV UIpkpk UIpkpk dB dB dB continued... (90) VRX_MAX and VRX_MIN are before and after configuration. (91) The specified common-mode range is supported when the receiver is powered and configured, powered and unconfigured, or unpowered. This specification is also supported before mode configuration. If squelch detect is used, receiver DC input common-mode voltage should be within 200 mV to 300 mV. Otherwise, use AC coupling capacitors on board. (92) The minimum insertion loss specification assumes a PAM4 transmitter with 800 mVppd. For transmitters with output amplitude adjustment capabilities and can reduce output amplitude to below 800 mVppd, this minimum insertion loss can be further relaxed. Send Feedback Intel� AgilexTM Device Data Sheet 71 Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Parameter Symbol IINS-LOSS-25Gb/s Receiver return loss ZRL-DIFF-DC ZRL-DIFF-NYQ ZRL-CM Receiver DC impedance Receiver signal detection(94) RDIFF-DC RCM-DC VIDLE-THRESH Description Insertion loss at 25.78125 Gbps NRZ(93)/ BER <10�12 Receiver differential DC return loss Receiver differential return loss at Nyquist frequency (FBAUD/2) Receiver commonmode return loss below 10 GHz DC differential receive impedance DC common-mode receive impedance Receiver signal detect input voltage threshold F-Tile Electrical Compliance Table 72. F-Tile FHT Electrical Compliance List For specification status, see the Data Sheet Status table Specification/Clause Protocol IEEE 802.3bs 120D/120E 400GAUI-4 200GAUI-2 200GAUI-4 Min -- -- -- -- 80 20 75 Typical -- -- -- -- 100 25 120 PAM4 PAM4 PAM4 Encoding Max 30 �12 �6 �6 120 30 175 Unit dB dB dB dB W W mVdiff-pkpk 106.25 106.25 53.125 Lane Rate (Gbps) continued... (93) 2COM compliant package and channel. (94) Receiver signal detection values in this table are applicable to PCIe and similar standards, such as SATA, where a clock pattern like PCIe EIEOS 500 MHz clock pattern is used. Intel� AgilexTM Device Data Sheet 72 Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Specification/Clause IEEE 802.3cd 135G/135F IEEE 802.3cd 109A/109B IEEE 802.3ck 163/162 CEI 4.0/5.0 Protocol 100GAUI-1 100GAUI-2 100GAUI-4 50GAUI-1 50GAUI-2 25GAUI-1 400GBASE-KR4/CR4 200GBASE-KR2/CR2 100GBASE-KR/CR OIF-CEI-112G XSR/VSR/MR/LR OIF-CEI-56G VSR/MR OIF-CEI-28G VSR/SR/MR OIF-25G Table 73. F-Tile FGT Electrical Compliance List For specification status, see the Data Sheet Status table Specification/Clause Protocol IEEE 802.3bs 120D/120E 400GAUI-8 400GAUI-16 200GAUI-4 200GAUI-8 IEEE 802.3cd 135G/135F 100GAUI-2 100GAUI-4 50GAUI-1 50GAUI-2 PAM4 PAM4 NRZ PAM4 NRZ NRZ PAM4 PAM4 PAM4 PAM4 PAM4 NRZ NRZ Encoding PAM4 NRZ PAM4 NRZ PAM4 NRZ PAM4 NRZ Encoding Send Feedback Lane Rate (Gbps) 106.25 53.125 25.78125 53.125 25.78125 25.78125 106.25 106.25 106.25 96 � 116 48 � 58 24 � 29 24 � 29 Lane Rate (Gbps) 53.125 26.5625 53.125 26.5625 53.125 25.78125 53.125 26.5625 continued... Intel� AgilexTM Device Data Sheet 73 Specification/Clause IEEE 802.3cd 109A/109B IEEE 802.3cd 137/136 IEEE 802.3bj/bm 93 IEEE 802.3bj/bm 92 IEEE 802.3bj/ba 85 IEEE 802.3bj/ba 84 IEEE 802.3ap 2007 IEEE 802.3ap 2008 IEEE 802.3by 111/110 CEI 4.0 G.709 G.sup56 G.sup43 G.sup58 Protocol 25GAUI-1 200GBASE-KR4/CR4 100GBASE-KR2/CR2 50GBASE-KR/CR 100GBASE-KR4 100GBASE-CR4 40GBASE-KR4 40GBASE-CR4 10GBASE-KR/CR 10GBASE-KX4 25GBASE-KR/CR CEI-56G VSR/MR/LR CEI-28G VSR/SR/MR IOF-CEI-25G LR CEI-11G SR/MR/LR CEI-6G SR/LR OTU0 OTU1 OTU1e OTU2/2e OTU2f OTU2r OTU3 OTU4(OTL4.4) OTU4(OTL4.10) Intel� AgilexTM Device Data Sheet 74 NRZ PAM4 PAM4 PAM4 NRZ NRZ NRZ NRZ NRZ NRZ NRZ PAM4 NRZ NRZ NRZ NRZ NRZ NRZ NRZ NRZ NRZ NRZ NRZ NRZ NRZ Encoding Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Lane Rate (Gbps) 25.78125 53.125 53.125 53.125 25.78125 25.78125 10.3125 10.3125 10.3125 10.3125 25.78125 36 � 58 19.9 � 28.1 19.9 � 28.1 9.95 � 11.2 4.976 � 6.375 1.327451 2.666057 11.049107 10.709225/11.095728 11.317642 12.639086 4x10.754603 4x27.952493 10x11.180997 continued... Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Specification/Clause G.709.1 G.709, G.709.4 PCIE BASE 4.0 SMPTE 259M SMPTE 292M SMPTE 372M SMPTE ST 2081 SMPTE ST 2082 CPRI V7.0 Protocol 100G FlexO-SR (FOIC1.4) 100G FlexO-SR (FOIC1.2) 100G FlexO-SR (FOIC2.4) 100G FlexO-SR (FOIC4.8) OTU25u OTU25 OTU50u (OTU50u.2-RS) OTU50u (OTU50u.1-RS) OTU50 (OTU50.2-RS) OTU50 PCIE SDI CPRI Send Feedback NRZ PAM4 PAM4 PAM4 NRZ NRZ NRZ PAM4 NRZ PAM4 NRZ NRZ NRZ NRZ NRZ NRZ NRZ NRZ NRZ NRZ NRZ NRZ NRZ NRZ NRZ Encoding Lane Rate (Gbps) 4x27.952369 2x55.904737 4x55.904737 8x55.904737 25.781651 27.952.493 2x26.562.914 53.125827 2x27.952493 55.904987 2.5, 5, 8, 16 0.27 1.485/1.483516484 2.97/2.967032967 5.94/5.934065934 11.88/11.868131868 1.2288 2.4576 3.072 4.9152 6.144 8.11008 9.8304 10.1376 12.16512 continued... Intel� AgilexTM Device Data Sheet 75 Specification/Clause JESD204A JESD204B JESD204C DP 2.0 Protocol JESD204A JESD204B JESD204C DisplayPort 2.0 FC-PI-2 FC-PI-5 10GFC FC-PI-5 FC-PI-6 FC-PI-7 Serial ATA revision 3.0 T10/BSR INCITS 519 IEEE 802.3av IEEE 802.3ah Fiber Channel Sata Gen 1, 2, 3 SAS 1, 2, 3, 4 10G-EPON 1G-EPON (95) JESD204B supports up to 19 Gbps. Intel� AgilexTM Device Data Sheet 76 NRZ NRZ NRZ NRZ NRZ NRZ NRZ NRZ NRZ NRZ NRZ NRZ NRZ NRZ NRZ NRZ NRZ NRZ PAM4 NRZ NRZ NRZ NRZ Encoding Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Lane Rate (Gbps) 24.33024 3.125 12.5(95) 28.9 1.62 2.7 5.4 8.1 10 13.5 20 1.0625 2.125 4.25 8.5 10.52 14.025 28.05 57.8 1, 3, 6 3, 6, 12, 22.5 10 1 continued... Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Specification/Clause G.984 CEI-6G-SR CEI-11G-SR CEI-11G-SR+ OIF-28G MR (OIF-CEI3.0) OIF-CEI 56G PAM4-MR JESD204C HDMI1.0-1.2a HDMI1.3-1.3a HDMI2.0-2.0b SFF8431 ITU-T G.8261 and G.8262 InfiniBandTM Architecture Specification RapidIOTM Interconnect Specification GPON Interlaken Protocol SerialLite IV HDMI SFP+ SyncE InfiniBand SRIO NRZ NRZ NRZ NRZ NRZ PAM4 NRZ NRZ NRZ NRZ NRZ NRZ/PAM4 NRZ NRZ Encoding Lane Rate (Gbps) 1.25, 2.5, 10.3 6.25 10.3125 12.5 25.78125 53.125 32 4.95 10.2 18 9.8304 � 12.5 10, 25, 50 5, 10, 14.062, 25.78125 1.25, 2.5, 3.125, 6.25, 10.3125 HPS Performance Specifications This section provides hard processor system (HPS) specifications and timing for Intel Agilex devices. Send Feedback Intel� AgilexTM Device Data Sheet 77 Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 HPS Clock Performance Table 74. Maximum HPS Clock Frequencies for Intel Agilex Devices For specification status, see the Data Sheet Status table Performance VCCL_HPS (V) MPU Frequency (MHz) L3 Frequency (MHz) (l3_main_free_clk ) MPFE Frequency (MHz) �1 speed grade Fixed: 0.95 1,500 400 400 667 SmartVID 1,350 400 400 667 �2 speed grade SmartVID 1,200 400 334 600 �3 speed grade SmartVID 1,000 400 300 534 �4 speed grade Fixed: 0.8 1,000 400 267 467 Rate Quarter Half Quarter Half Quarter Half Quarter Half Quarter Half Related Information External Memory Interface Spec Estimator Provides the specific details of the maximum allowed SDRAM operating frequency. HPS Internal Oscillator Frequency Table 75. HPS Internal Oscillator Frequency for Intel Agilex Devices For specification status, see the Data Sheet Status table Description Min Typ Internal oscillator frequency 150 300 Max 400 DDR Clock (MHz) DDR (Mb/s per pin) 1,600 1,333 1,600 1,333 1,333 1,200 1,200 1,067 1,067 933 3,200 2,666 3,200 2,666 2,666 2,400 2,400 2,133 2,133 1,866 Unit MHz Intel� AgilexTM Device Data Sheet 78 Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 HPS PLL Specifications Table 76. HPS PLL Input Requirements for Intel Agilex Devices The main HPS PLL receives its clock signals from the HPS_OSC_CLK pin. Refer to the Intel Agilex Device Family Pin Connection Guidelines for information about assigning this pin. For specification status, see the Data Sheet Status table Description Clock input range Clock input accuracy Clock input duty cycle Min 25 -- 45 Typ -- -- 50 Max 125 50 55 Unit MHz ppm % Table 77. HPS PLL Performance for Intel Agilex Devices For specification status, see the Data Sheet Status table Description Min Main PLL VCO output -- Peripheral PLL VCO output -- h2f_user0_clk(96) -- h2f_user1_clk(96) -- Max 3,000 3,000 500 500 Unit MHz MHz MHz MHz Related Information Intel Agilex Device Family Pin Connection Guidelines Provides more information about the HPS_OSC_CLK pin assignment. (96) The HPS PLL provides this clock to the FPGA fabric. Send Feedback Intel� AgilexTM Device Data Sheet 79 HPS Cold Reset Table 78. HPS Cold Reset for Intel Agilex Devices For specification status, see the Data Sheet Status table Symbol Description Min tRST0 Minimum time for 3 HPS_COLD_nRESET asserted(97) HPS SPI Timing Characteristics Table 79. SPI Master Timing Requirements for Intel Agilex Devices You can adjust the input delay timing by programming the rx_sample_dly register. For specification status, see the Data Sheet Status table Symbol Tspi_ref_clk Description The period of the SPI internal reference clock, sourced from l4_main_clk Min 2.5 Typ -- Tclk SPIM_CLK clock period 16.67 -- Tdutycycle SPIM_CLK duty cycle 45 50 Tck_jitter SPIM_CLK output jitter -- -- Tdio Master-out slave-in �3 -- (MOSI) output skew Tdssfrst (98) SPI_SS_N asserted to first (1.5 � Tclk) � 2 -- SPIM_CLK edge Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Max -- Unit ms Max -- -- 55 2 2 -- Unit ns ns % % ns ns continued... (97) HPS_COLD_nRESET may be ignored if HPS is not running or if the device is being configured. (98) SPI_SS_N behavior differs depending on Motorola SPI, TI SSP, or Microwire operational mode. Intel� AgilexTM Device Data Sheet 80 Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Symbol Tdsslst (98) Tsu (99) Th (99) Description Last SPIM_CLK edge to SPI_SS_N deasserted SPIM_MISO setup time with respect to SPIM_CLK capture edge Input hold in respect to SPIM_CLK capture edge Min Tclk � 2 5.0 � (rx_sample_dly � Tspi_ref_clk)(100) 1.3 + (rx_sample_dly � Tspi_ref_clk) Typ -- -- -- Max -- -- -- Unit ns ns ns (99) The capture edge differs depending on the operational mode. For Motorola SPI, the capture edge can be the rising or falling edge depending on the scpol register bit; for TI SSP, the capture edge is the falling edge; for Microwire, the capture edge is the rising edge. (100) Valid values of rx_sample_dly range from 1 to 64 (units are in Tspi_ref_clk steps). Send Feedback Intel� AgilexTM Device Data Sheet 81 Figure 4. SPI Master Output Timing Diagram scph* = 0 Tdssfrst SPI_SS SPI_CLK (scpol = 0) SPI_CLK (scpol = 1) SPI_MOSI OUT0 SPI_MISO Tdio (max) Tdio (min) OUT1 scph* = 1 Tdssfrst SPI_SS SPI_CLK (scpol = 0) SPI_CLK (scpol = 1) SPI_MOSI OUT0 SPI_MISO Tdio (max) Tdio (min) OUT1 *Serial clock phase configuration bit, in the SPI controller's CTRLR0 register Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Tdsslst OUTn Tdsslst OUTn Intel� AgilexTM Device Data Sheet 82 Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Figure 5. SPI Master Input Timing Diagram scph* = 0 SPI_SS SPI_CLK (scpol = 0) SPI_CLK (scpol = 1) SPI_MOSI SPI_MISO IN0 IN1 Tsu Th INn scph* = 1 SPI_SS SPI_CLK (scpol = 0) SPI_CLK (scpol = 1) SPI_MOSI SPI_MISO IN0 IN1 Tsu Th INn *Serial clock phase configuration bit, in the SPI controller's CTRLR0 register Send Feedback Intel� AgilexTM Device Data Sheet 83 Table 80. SPI Slave Timing Requirements for Intel Agilex Devices For specification status, see the Data Sheet Status table Symbol Description Min Tspi_ref_clk The period of the SPI 2.5 internal reference clock, sourced from l4_main_clk Tclk Tdutycycle Td SPIM_CLK clock period SPIM_CLK duty cycle Master-in slave-out (MISO) output skew 30 45 (2 � Tspi_ref_clk) + 3 Tsu Master-out slave-in 4 (MOSI) setup time Th Master-out slave-in 9 (MOSI) hold time Tsuss SPI_SS_N asserted to first SPIM_CLK edge Tspi_ref_clk + 4.2 Thss Last SPIM_CLK edge to SPI_SS_N deasserted Tspi_ref_clk + 4.2 Typ -- -- 50 -- -- -- -- -- Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Max -- -- 55 (3 � Tspi_ref_clk) + 11 -- -- -- -- Unit ns ns % ns ns ns ns ns Intel� AgilexTM Device Data Sheet 84 Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Figure 6. SPI Slave Output Timing Diagram scph* = 0 SPI_SS SPI_CLK (scpol = 0) SPI_CLK (scpol = 1) Td (max) Td (min) SPI_MISO OUT0 OUT1 OUTn SPI_MOSI scph* = 1 SPI_SS SPI_CLK (scpol = 0) SPI_CLK (scpol = 1) Td (max) Td (min) SPI_MISO OUT0 OUT1 OUTn SPI_MOSI *Serial clock phase configuration bit, in the SPI controller's CTRLR0 register Send Feedback Intel� AgilexTM Device Data Sheet 85 Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Figure 7. SPI Slave Input Timing Diagram scph* = 0 Tsuss SPI_SS Thss SPI_CLK (scpol = 0) SPI_CLK (scpol = 1) SPI_MISO SPI_MOSI IN0 IN1 Ts Th INn scph* = 1 Tsuss SPI_SS Thss SPI_CLK (scpol = 0) SPI_CLK (scpol = 1) SPI_MISO SPI_MOSI IN0 IN1 Ts Th INn *Serial clock phase configuration bit, in the SPI controller's CTRLR0 register Intel� AgilexTM Device Data Sheet 86 Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 HPS SD/MMC Timing Characteristics Table 81. HPS Secure Digital (SD)/MultiMediaCard (MMC) Timing Requirements for Intel Agilex Devices These timings apply to SD, MMC, and embedded MMC (eMMC) cards operating at 1.8 V. For specification status, see the Data Sheet Status table Symbol Description Min Tsdmmc_cclk SDMMC_CCLK clock period (Identification mode) 2,500 SDMMC_CCLK clock period 40 (SDR12) SDMMC_CCLK clock period 20 (SDR25) Tdutycycle SDMMC_CCLK duty cycle 45 Tsdmmc_cclk_jitter SDMMC_CCLK output jitter -- Tsdmmc_clk Internal reference clock 5 before division by 4 Td SDMMC_CMD/ �0.5 + Tsdmmc_clk � SDMMC_DATA[7:0] output drvsel/2 delay(101) Tsu SDMMC_CMD/ 6 � (Tsdmmc_clk � SDMMC_DATA[7:0] input smplsel/2) setup(102) Th SDMMC_CMD/ 0.5 + (Tsdmmc_clk � SDMMC_DATA[7:0] input smplsel/2) hold(102) Typ -- -- -- 50 -- -- -- -- -- Max -- -- -- 55 2 -- 2.5 + (Tsdmmc_clk � drvsel/2) -- -- Unit ns ns ns % % ns ns ns ns None of the HPS I/Os supports 3 V mode, while SD/MMC cards must operate at 3 V at power on. eMMC devices can operate at 1.8 V at power on. (101) When the drvsel bitfield in the sdmmc register is set to 3 (in the system manager) and the reference clock (sdmmc_clk) is 200 MHz for example, the output delay time is 7.5 to 10.5 ns. (102) When the smplsel bitfield in the sdmmc register is set to 2 (in the system manager) and the reference clock (sdmmc_clk) is 200 MHz for example, the setup time is 1 ns and the hold time is 5.5 ns. Send Feedback Intel� AgilexTM Device Data Sheet 87 Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Note: Figure 8. SD cards power up at 3 V. To support SD, your design must include a level shifter between the SD card and the HPS SD/MMC interface. SD/MMC Timing Diagram SDMMC_CCLK SDMMC_CMD and SDMMC_DATA (Out) SDMMC_CMD and SDMMC_DATA (In) Td Command/Data Out TSU Th Command/Data In HPS USB UPLI Timing Characteristics Table 82. HPS USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) Low Pin Interface (ULPI) Timing Requirements for Intel Agilex Devices For specification status, see the Data Sheet Status table Symbol Description Min Typ Max Unit Tusb_clk USB_CLK clock period -- 16.667 -- ns Td Clock to USB_STP/ 2 -- 7 ns USB_DATA[7:0] output delay Tsu Setup time for USB_DIR/ 4 -- -- ns USB_NXT/USB_DATA[7:0] Th Hold time for USB_DIR/ 4 -- -- ns USB_NXT/USB_DATA[7:0] Intel� AgilexTM Device Data Sheet 88 Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Figure 9. USB ULPI Timing Diagram USB_CLK USB_STP USB_DATA[7:0] USB_DIR and USB_NXT Td To PHY From PHY TSU Th Note: The USB interface supports single data rate (SDR) timing only. HPS Ethernet Media Access Controller (EMAC) Timing Characteristics Table 83. Reduced Gigabit Media Independent Interface (RGMII) TX Timing Requirements for Intel Agilex Devices For specification status, see the Data Sheet Status table Symbol Description Min Typ Max Unit Tclk (1000Base-T) TX_CLK clock period -- 8 -- ns Tclk (100Base-T) TX_CLK clock period -- 40 -- ns Tclk (10Base-T) TX_CLK clock period -- 400 -- ns Tdutycycle (1000Base-T) TX_CLK duty cycle 45 50 55 % Tdutycycle (10/100Base-T) TX_CLK duty cycle 40 50 60 % Td (103) (104) TXD/TX_CTL to TX_CLK �0.5 -- 0.5 ns output skew (103) Rise and fall times depend on the I/O standard, drive strength, and loading. Intel recommends simulating your configuration. (104) If you connect a PHY that does not implement clock-to-data skew, you can delay TX_CLK by 1.5--2.0 ns with the HPS I/O programmable delay, to meet the PHY's 1-ns data-to-clock skew requirement. Send Feedback Intel� AgilexTM Device Data Sheet 89 Figure 10. RGMII TX Timing Diagram TX_CLK TX_D[3:0] TX_CTL D0 Td Table 84. RGMII RX Timing Requirements for Intel Agilex Devices For specification status, see the Data Sheet Status table Symbol Description Min Tclk (1000Base-T) RX_CLK clock period -- Tclk (100Base-T) RX_CLK clock period -- Tclk (10Base-T) RX_CLK clock period -- Tdutycycle (1000Base-T) RX_CLK duty cycle 45 Tdutycycle (10/100Base-T) RX_CLK duty cycle 40 Tsu RX_D/RX_CTL to RX_CLK 1 setup time Th (105) RX_CLK to RX_D/RX_CTL 1 hold time Typ 8 40 400 50 50 -- -- Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 D1 Max -- -- -- 55 60 -- -- Unit ns ns ns % % ns ns (105) If you connect a PHY that does not implement clock-to-data skew, you can meet the HPS EMAC's 1 ns setup time by delaying RX_CLK by 1.5-2 ns, using the HPS I/O programmable delay. Intel� AgilexTM Device Data Sheet 90 Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Figure 11. RGMII RX Timing Diagram RX_CLK RX_D[3:0] RX_CTL TSU Th D0 D1 Table 85. Reduced Media Independent Interface (RMII) Clock Timing Requirements for Intel Agilex Devices For specification status, see the Data Sheet Status table Symbol Description Min Typ Max Tclk REF_CLK clock period, -- 20 -- sourced by HPS TX_CLK REF_CLK clock period, -- 20 -- sourced by external clock source Tdutycycle_int Clock duty cycle, REF_CLK 35 50 65 sourced by TX_CLK Tdutycycle_ext Clock duty cycle, REF_CLK 35 50 65 sourced by external clock source Table 86. RMII TX Timing Requirements for Intel Agilex Devices For specification status, see the Data Sheet Status table Symbol Description Min Typ Td TX_CLK to TXD/TX_CTL 2 -- output data delay Max 10 Unit ns ns % % Unit ns Send Feedback Intel� AgilexTM Device Data Sheet 91 Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Figure 12. RMII TX Timing Diagram Reference Clock (RX_CLK) (1) TX_D[1:0] D0 D1 Td TX_CTL Note: 1. For RMII mode, RX_CLK is always used as the reference clock. Refer to the HPS-to-PHY Interface Diagram in the Intel Agilex Hard Processor System Technical Reference Manual for example system-level topologies. Table 87. RMII RX Timing Requirements for Intel Agilex Devices For specification status, see the Data Sheet Status table Symbol Description Min Typ Tsu RX_D/RX_CTL setup time 2 -- Th RX_D/RX_CTL hold time 1 -- Figure 13. RMII RX Timing Diagram Reference Clock (RX_CLK) (1) Max -- -- Unit ns ns TSU Th RX_D[1:0] D0 D1 RX_CTL Note: 1. For RMII mode, RX_CLK is always used as the reference clock. Refer to the HPS-to-PHY Interface Diagram in the Intel Agilex Hard Processor System Technical Reference Manual for example system-level topologies. Intel� AgilexTM Device Data Sheet 92 Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Table 88. Management Data Input/Output (MDIO) Timing Requirements for Intel Agilex Devices For specification status, see the Data Sheet Status table Symbol Description Min Typ Max Tclk MDC clock period 400 -- -- Td MDC to MDIO output data 10 -- 300 delay Tsu Setup time for MDIO data 10 -- -- Th Hold time for MDIO data 0 -- -- Figure 14. MDIO Timing Diagram MDC MDIO_OUT Td Dout0 Dout1 MDIO_IN TSU Th Din0 Related Information HPS-to-PHY Interface Diagrams section, Intel Agilex Hard Processor System Technical Reference Manual Provides the example system-level topologies. Unit ns ns ns ns Send Feedback Intel� AgilexTM Device Data Sheet 93 Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 HPS I2C Timing Characteristics Table 89. HPS I2C Timing Requirements for Intel Agilex Devices For specification status, see the Data Sheet Status table Symbol Description Standard Mode Min Max Tclk Tclk_jitter THIGH (106) TLOW (109) TSU;DAT THD;DAT (112) Serial clock (SCL) clock period I2C clock output jitter SCL high period SCL low period Setup time for serial data line (SDA) data to SCL Hold time for SCL to SDA data 10 -- 4(107) 4.7(110) 0.25 0 -- 2 -- -- -- 3.15 Min 2.5 Fast Mode Max -- -- 2 0.6(108) -- 1.3(111) -- 0.1 -- 0 0.6 Unit s % s s s s continued... (106) You can adjust Thigh using the ic_ss_scl_hcnt or ic_fs_scl_hcnt register. (107) The recommended minimum setting for ic_ss_scl_hcnt is 428. Refer to the SCL_High_time equation in the Intel Agilex Hard Processor System Technical Reference Manual. (108) The recommended minimum setting for ic_fs_scl_hcnt is 75. Refer to the SCL_High_time equation in the Intel Agilex Hard Processor System Technical Reference Manual. (109) You can adjust Tlow using the ic_ss_scl_lcnt or ic_fs_scl_lcnt register. (110) The recommended minimum setting for ic_ss_scl_lcnt is 464. Refer to the SCL_Low_time equation in the Intel Agilex Hard Processor System Technical Reference Manual. (111) The recommended minimum setting for ic_fs_scl_lcnt is 163. Refer to the SCL_Low_time equation in the Intel Agilex Hard Processor System Technical Reference Manual. (112) THD;DAT is affected by the rise and fall time. Intel� AgilexTM Device Data Sheet 94 Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Symbol Description TVD;DAT and TVD;ACK (113) TSU;STA THD;STA TSU;STO TBUF Tscl:r (116) Tscl:f (116) Tsda:r (116) Tsda:f (116) SCL to SDA output data delay Setup time for a repeated start condition Hold time for a repeated start condition Setup time for a stop condition SDA high pulse duration between STOP and START SCL rise time SCL fall time SDA rise time SDA fall time Standard Mode Min Max -- 3.45(114) 4.7 -- 4 -- 4 -- 4.7 -- -- 1,000 -- 300 -- 1,000 -- 300 Min -- Fast Mode Max 0.9(115) 0.6 -- 0.6 -- 0.6 -- 1.3 -- 20 300 6.54 300 20 300 6.54 300 Unit s s s s s ns ns ns ns (113) TVD;DAT and TVD;ACK are affected by the rise and fall time, as well as the SDA hold time (set by adjusting the ic_sda_hold register). (114) Use maximum SDA_HOLD = 240 to be within the specification. (115) Use maximum SDA_HOLD = 60 to be within the specification. (116) Rise and fall time parameters vary depending on external factors such as the characteristics of the I/O driver, pull-up resistor value, and total capacitance on the transmission line. Send Feedback Intel� AgilexTM Device Data Sheet 95 Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Figure 15. I2C Timing Diagram tf tr tSU;DAT SDA 70% 30% tf tHD;DAT tr tHIGH tVD;DAT SCL 70% 30% tHD;STA Tclk tLOW SDA tSU;STA SCL tHD;STA tBUF 70% 30% tVD;ACK tSU;STO 70% 30% Related Information Clock Synchronization section, Intel Agilex Hard Processor System Technical Reference Manual Provides the SCL high and low time equations. Intel� AgilexTM Device Data Sheet 96 Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 HPS NAND Timing Characteristics Table 90. HPS NAND ONFI 1.0 Timing Requirements for Intel Agilex Devices For specification status, see the Data Sheet Status table Symbol TWP (117) TWH (117) TRP (117) TREH (117) TCLS (117) TCLH (117) TCS (117) TCH (117) TALS (117) TALH (117) TDS (117) TDH (117) TWB (117) TCEA Description Write enable pulse width Write enable hold time Read enable pulse width Read enable hold time Command latch enable to write enable setup time Command latch enable to write enable hold time Chip enable to write enable setup time Chip enable to write enable hold time Address latch enable to write enable setup time Address latch enable to write enable hold time Data to write enable setup time Data to write enable hold time Write enable high to R/B low Chip enable to data access time Min 10 7 10 7 10 5 15 5 10 5 7 5 -- -- Max -- -- -- -- -- -- -- -- -- -- -- -- 200 100 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns continued... (117) This timing is software programmable. Refer to the NAND Flash Controller chapter in the Intel Agilex Hard Processor System Technical Reference Manual for more information about software-programmable timing in the NAND flash controller. Send Feedback Intel� AgilexTM Device Data Sheet 97 TREA TRHZ TRR Symbol Description Read enable to data access time Read enable to data high impedance Ready to read enable low Figure 16. NAND Command Latch Timing Diagram CLE CE WE ALE IO0-7 R/B Min -- -- 20 Max 40 200 -- tCLS tCLH tCS tCH tWP tALS tALH tDS tDH Command tWB Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Unit ns ns ns Intel� AgilexTM Device Data Sheet 98 Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Figure 17. NAND Address Latch Timing Diagram CLE CE WE ALE IO0-7 tCLS tCS tWP tWH tALS tALH tDS tDH Address Send Feedback Intel� AgilexTM Device Data Sheet 99 Figure 18. NAND Data Output Cycle Timing Diagram CLE CE tWP tWP WE tWH ALE tALS tDS tDH IOx DOUT 0 Figure 19. NAND Data Input Cycle Timing Diagram tCEA CE tRP RE tREH tRR R/B tREA tRHZ IOx DIN 0 tDS tDH DOUT 1 tRP tREA tRHZ DIN 1 Intel� AgilexTM Device Data Sheet 100 Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 tCLH tCH tWP tDS tDH DOUT n tRP tREA tRHZ DIN n Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Figure 20. NAND Data Input Timing Diagram for Extended Data Output (EDO) Cycle CE tRP RE tREH tRR R/B tREA tREA IOx DIN 0 DIN 1 tCEA tRHZ DIN n Send Feedback Intel� AgilexTM Device Data Sheet 101 Figure 21. NAND Read Status Timing Diagram CLE tCLS tCLH tCS tCH CE WE tWP RE tDS tDH IO0-7 70h Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 tCEA tRHZ Status tREA Intel� AgilexTM Device Data Sheet 102 Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Figure 22. NAND Read Status Enhanced Timing Diagram CLE tCLS tCLH tCS CE tWP WE tALH tALtSWP tWH ALE RE tDS tDH IO0-7 78h R1 R2 tCH tALH R3 tCEA tREA tRHZ Status Send Feedback Intel� AgilexTM Device Data Sheet 103 Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 HPS Trace Timing Characteristics Table 91. Trace Timing Requirements for Intel Agilex Devices To increase the trace bandwidth, Intel recommends routing the trace interface to the FPGA in the HPS Platform Designer component. The FPGA trace interface offers a 64-bit single data rate path that can be converted to double data rate to minimize FPGA I/O usage. Depending on the trace module that you connect to the HPS trace interface, you may need to include board termination to achieve the maximum sampling speed possible. Refer to your trace module data sheet for termination recommendations. Most trace modules implement programmable clock and data skew, to improve trace data timing margins. Alternatively, you can change the clock-to-data timing relationship with the HPS programmable I/O delay. For specification status, see the Data Sheet Status table Symbol Description Min Tclk Tclk_jitter Tdutycycle Trace clock period Trace clock output jitter Trace clock maximum duty cycle 6.667 -- 45 Td Tclk to D0�D15 output data �0.5 delay Typ -- -- 50 -- Max -- 2 55 1.3 Unit ns % % ns Figure 23. Trace Timing Diagram Clock (DDR) Trace Data (DDR) Td Intel� AgilexTM Device Data Sheet 104 Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 HPS GPIO Interface The general-purpose I/O (GPIO) interface has debounce circuitry included to remove signal glitches. The debounce clock frequency ranges from 125 Hz to 32 kHz. The minimum pulse width is 1 debounce clock cycle and the minimum detectable GPIO pulse width is 62.5 �s (at 32 kHz). If the external signal is driven into the GPIO for less than one clock cycle, the external signal is filtered. If the external signal is between one and two clock cycles, the external signal may or may not be filtered depending on the phase of the signal. If the external signal is more than two clock cycles, the external signal is not filtered. HPS JTAG Timing Characteristics Table 92. HPS JTAG Timing Requirements for Intel Agilex Devices For specification status, see the Data Sheet Status table Symbol Description Min tJCP tJCH tJCL tJPSU (TDI) tJPSU (TMS) tJPH tJPCO tJPZX TCK clock period TCK clock high time TCK clock low time TDI JTAG port setup time TMS JTAG port setup time JTAG port hold time JTAG port clock to output JTAG port high impedance to valid output 41.66 20 20 5 5 0.5 0 -- tJPXZ JTAG port valid output to -- high impedance Typ -- -- -- -- -- -- -- -- -- Max -- -- -- -- -- -- 8 10 10 Unit ns ns ns ns ns ns ns ns ns Send Feedback Intel� AgilexTM Device Data Sheet 105 Figure 24. HPS JTAG Timing Diagram TMS TDI tJCP tJCH tJCL TCK tJPZX TDO tJPSU tJPH tJPCO tJPXZ HPS Programmable I/O Timing Characteristics Table 93. HPS Programmable I/O Delay (Output Path) for Intel Agilex Device For specification status, see the Data Sheet Status table Name output_val_en output_val Description Min ZERO_CHAIN_DEL 0 0 Intrinsic I/O delay. -- AY Bypasses the delay chain CHAIN_DELAY 1 0 Intrinsic I/O delay -- + Minimum + 0 � Chain Delay ONE_CHAIN_DELA 1 1 Intrinsic I/O delay -- Y + Minimum + 1 � Chain Delay TWO_CHAIN_DELA 1 2 Intrinsic I/O delay -- Y + Minimum + 2 � Chain Delay THREE_CHAIN_DEL 1 3 Intrinsic I/O delay -- AY + Minimum + 3 � Chain Delay FOUR_CHAIN_DEL 1 4 Intrinsic I/O delay -- AY + Minimum + 4 � Chain Delay Typ 0 0 422 518 607 705 Intel� AgilexTM Device Data Sheet 106 Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Max -- -- -- -- -- -- Unit ps ps ps ps ps ps continued... Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Name output_val_en FIVE_CHAIN_DELA 1 Y output_val 5 SIX_CHAIN_DELAY 1 6 SEVEN_CHAIN_DEL 1 7 AY EIGHT_CHAIN_DEL 1 8 AY NINE_CHAIN_DELA 1 9 Y TEN_CHAIN_DELAY 1 10 ELEVEN_CHAIN_DE 1 LAY TWELVE_CHAIN_D 1 ELAY THIRTEEN_CHAIN_ 1 DELAY FOURTEEN_CHAIN 1 _DELAY FIFTEEN_CHAIN_D 1 ELAY -- 1 -- 2 11 12 13 14 15 [16:30] -- Description Intrinsic I/O delay + Minimum + 5 � Chain Delay Intrinsic I/O delay + Minimum + 6 � Chain Delay Intrinsic I/O delay + Minimum + 7 � Chain Delay Intrinsic I/O delay + Minimum + 8 � Chain Delay Intrinsic I/O delay + Minimum + 9 � Chain Delay Intrinsic I/O delay + Minimum + 10 � Chain Delay Intrinsic I/O delay + Minimum + 11 � Chain Delay Intrinsic I/O delay + Minimum + 12 � Chain Delay Intrinsic I/O delay + Minimum + 13 � Chain Delay Intrinsic I/O delay + Minimum + 14 � Chain Delay Intrinsic I/O delay + Minimum + 15 � Chain Delay INVALID INVALID Min -- -- -- -- -- -- -- -- -- -- -- -- -- Send Feedback Typ 786 874 955 1,042 1,126 1,214 1,296 1,382 1,462 1,552 1,626 -- -- Max -- -- -- -- -- -- -- -- -- -- -- -- -- Unit ps ps ps ps ps ps ps ps ps ps ps -- -- continued... Intel� AgilexTM Device Data Sheet 107 Name output_val_en -- 3 SIXTEEN_CHAIN_D 3 ELAY output_val [0:15] 16 SEVENTEEN_CHAIN 3 17 _DELAY EIGHTEEN_CHAIN_ 3 18 DELAY NINETEEN_CHAIN_ 3 19 DELAY TWENTY_CHAIN_D 3 20 ELAY TWENTYONE_CHAI 3 21 N_DELAY TWENTYTWO_CHAI 3 22 N_DELAY TWENTYTHREE_CH 3 23 AIN_DELAY TWENTYFOUR_CHA 3 24 IN_DELAY TWENTYFIVE_CHAI 3 25 N_DELAY TWENTYSIX_CHAIN 3 26 _DELAY Description INVALID Intrinsic I/O delay + Minimum + 16 � Chain Delay Intrinsic I/O delay + Minimum + 17 � Chain Delay Intrinsic I/O delay + Minimum + 18 � Chain Delay Intrinsic I/O delay + Minimum + 19 � Chain Delay Intrinsic I/O delay + Minimum + 20 � Chain Delay Intrinsic I/O delay + Minimum + 21 � Chain Delay Intrinsic I/O delay + Minimum + 22 � Chain Delay Intrinsic I/O delay + Minimum + 23 � Chain Delay Intrinsic I/O delay + Minimum + 24 � Chain Delay Intrinsic I/O delay + Minimum + 25 � Chain Delay Intrinsic I/O delay + Minimum + 26 � Chain Delay Min -- -- -- -- -- -- -- -- -- -- -- -- Intel� AgilexTM Device Data Sheet 108 Typ -- 1,798 1,885 1,967 2,054 2,137 2,222 2,305 2,395 2,475 2,564 2,644 Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Max -- -- -- -- -- -- -- -- -- -- -- -- Unit -- ps ps ps ps ps ps ps ps ps ps ps continued... Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Name output_val_en TWENTYSEVEN_CH 3 AIN_DELAY output_val 27 TWENTYEIGHT_CH 3 28 AIN_DELAY TWENTYNINE_CHA 3 29 IN_DELAY THIRTY_CHAIN_DE 3 30 LAY Description Intrinsic I/O delay + Minimum + 27 � Chain Delay Intrinsic I/O delay + Minimum + 28 � Chain Delay Intrinsic I/O delay + Minimum + 29 � Chain Delay Intrinsic I/O delay + Minimum + 30 � Chain Delay Min -- -- -- -- Table 94. HPS Programmable I/O Delay (Input Path) for Intel Agilex Device For specification status, see the Data Sheet Status table Name input_val_en input_val Description Min ZERO_CHAIN_DEL 0 0 Intrinsic I/O delay. -- AY Bypasses the delay chain CHAIN_DELAY 1 0 Intrinsic I/O delay -- + Minimum + 0 � Chain Delay ONE_CHAIN_DELA 1 1 Intrinsic I/O delay -- Y + Minimum + 1 � Chain Delay TWO_CHAIN_DELA 1 2 Intrinsic I/O delay -- Y + Minimum + 2 � Chain Delay THREE_CHAIN_DEL 1 3 Intrinsic I/O delay -- AY + Minimum + 3 � Chain Delay FOUR_CHAIN_DEL 1 4 Intrinsic I/O delay -- AY + Minimum + 4 � Chain Delay Typ 2,732 2,808 2,901 2,979 Typ 0 0 422 518 607 705 Send Feedback Max -- -- -- -- Unit ps ps ps ps Max -- -- -- -- -- -- Unit ps ps ps ps ps ps continued... Intel� AgilexTM Device Data Sheet 109 Name input_val_en FIVE_CHAIN_DELA 1 Y input_val 5 SIX_CHAIN_DELAY 1 6 SEVEN_CHAIN_DEL 1 7 AY EIGHT_CHAIN_DEL 1 8 AY NINE_CHAIN_DELA 1 9 Y TEN_CHAIN_DELAY 1 10 ELEVEN_CHAIN_DE 1 LAY TWELVE_CHAIN_D 1 ELAY THIRTEEN_CHAIN_ 1 DELAY FOURTEEN_CHAIN 1 _DELAY FIFTEEN_CHAIN_D 1 ELAY -- 1 -- 2 11 12 13 14 15 [16:30] -- Description Intrinsic I/O delay + Minimum + 5 � Chain Delay Intrinsic I/O delay + Minimum + 6 � Chain Delay Intrinsic I/O delay + Minimum + 7 � Chain Delay Intrinsic I/O delay + Minimum + 8 � Chain Delay Intrinsic I/O delay + Minimum + 9 � Chain Delay Intrinsic I/O delay + Minimum + 10 � Chain Delay Intrinsic I/O delay + Minimum + 11 � Chain Delay Intrinsic I/O delay + Minimum + 12 � Chain Delay Intrinsic I/O delay + Minimum + 13 � Chain Delay Intrinsic I/O delay + Minimum + 14 � Chain Delay Intrinsic I/O delay + Minimum + 15 � Chain Delay INVALID INVALID Min -- -- -- -- -- -- -- -- -- -- -- -- -- Intel� AgilexTM Device Data Sheet 110 Typ 786 874 955 1,042 1,126 1,214 1,296 1,382 1,462 1,552 1,626 -- -- Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Max -- -- -- -- -- -- -- -- -- -- -- -- -- Unit ps ps ps ps ps ps ps ps ps ps ps -- -- continued... Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Name input_val_en -- 3 SIXTEEN_CHAIN_D 3 ELAY input_val [0:15] 16 SEVENTEEN_CHAIN 3 17 _DELAY EIGHTEEN_CHAIN_ 3 18 DELAY NINETEEN_CHAIN_ 3 19 DELAY TWENTY_CHAIN_D 3 20 ELAY TWENTYONE_CHAI 3 21 N_DELAY TWENTYTWO_CHAI 3 22 N_DELAY TWENTYTHREE_CH 3 23 AIN_DELAY TWENTYFOUR_CHA 3 24 IN_DELAY TWENTYFIVE_CHAI 3 25 N_DELAY TWENTYSIX_CHAIN 3 26 _DELAY Description INVALID Intrinsic I/O delay + Minimum + 16 � Chain Delay Intrinsic I/O delay + Minimum + 17 � Chain Delay Intrinsic I/O delay + Minimum + 18 � Chain Delay Intrinsic I/O delay + Minimum + 19 � Chain Delay Intrinsic I/O delay + Minimum + 20 � Chain Delay Intrinsic I/O delay + Minimum + 21 � Chain Delay Intrinsic I/O delay + Minimum + 22 � Chain Delay Intrinsic I/O delay + Minimum + 23 � Chain Delay Intrinsic I/O delay + Minimum + 24 � Chain Delay Intrinsic I/O delay + Minimum + 25 � Chain Delay Intrinsic I/O delay + Minimum + 26 � Chain Delay Min -- -- -- -- -- -- -- -- -- -- -- -- Send Feedback Typ -- 1,798 1,885 1,967 2,054 2,137 2,222 2,305 2,395 2,475 2,564 2,644 Max -- -- -- -- -- -- -- -- -- -- -- -- Unit -- ps ps ps ps ps ps ps ps ps ps ps continued... Intel� AgilexTM Device Data Sheet 111 Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Name input_val_en TWENTYSEVEN_CH 3 AIN_DELAY input_val 27 TWENTYEIGHT_CH 3 28 AIN_DELAY TWENTYNINE_CHA 3 29 IN_DELAY THIRTY_CHAIN_DE 3 30 LAY Description Intrinsic I/O delay + Minimum + 27 � Chain Delay Intrinsic I/O delay + Minimum + 28 � Chain Delay Intrinsic I/O delay + Minimum + 29 � Chain Delay Intrinsic I/O delay + Minimum + 30 � Chain Delay Min -- -- -- -- Typ 2,732 2,808 2,901 2,979 Max -- -- -- -- Unit ps ps ps ps You can program the number of delay steps by adjusting the I/O Delay register (io0_delay through io47_delay for I/Os 0 through 47). Configuration Specifications General Configuration Timing Specifications Table 95. tCF12ST1 tCF02ST0 General Configuration Timing Specifications for Intel Agilex Devices For specification status, see the Data Sheet Status table Symbol Description Requirement Min nCONFIG high to nSTATUS high -- nCONFIG low to nSTATUS low -- (security features not enabled) nCONFIG low to nSTATUS low -- (security features enabled) Max 20 400 TBD(118) Unit ms ms ms continued... (118) The maximum time is longer if you enable the security features. The security features and specification will be available in a future release. Intel� AgilexTM Device Data Sheet 112 Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Symbol Description tST0 tCD2UM (119) tST12CF0 tST02CF1 nSTATUS low pulse during configuration error CONF_DONE high to user mode Minimum time to drive nCONFIG from high to low after nSTATUS transitions from low to high Minimum time to drive nCONFIG from low to high after nSTATUS transitions from high to low Figure 25. General Configuration Timing Diagram Reconfiguration Triggered tST02CF1 Reconfiguration nCONFIG nSTATUS CONF_DONE INIT_DONE Configuration_State User Mode Device Clean Idle tCF12ST1 Configuration Min 0.5 -- 0 0 Requirement Max 10 5 -- -- Unit ms ms ms ms tST0 tST12CF0 tCF02ST0 Configuration Error tCD2UM Recovered Reconfiguration Err Configuration Fail Device Clean Idle Configuration Initialization User Mode POR Specifications Power-on reset (POR) delay is defined as the delay between the time when all the power supplies monitored by the POR circuitry reach the minimum recommended operating voltage to the time when the nSTATUS is released high and your device is ready to begin configuration. (119) This specification is the initialization time that indicates the time from CONF_DONE signal goes high to INIT_DONE signal goes high. Send Feedback Intel� AgilexTM Device Data Sheet 113 Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Table 96. POR Delay Specification for Intel Agilex Devices For specification status, see the Data Sheet Status table POR Delay Minimum AS (Normal mode), AVST �8, AVST �16, AVST �32 11.5 AS (Fast mode) 1.5 Maximum 20.2 7.6 External Configuration Clock Source Requirements Table 97. External Configuration Clock Source (OSC_CLK_1) Clock Input Requirements For specification status, see the Data Sheet Status table Description Clock input frequency(120) Clock input peak-to-peak period jitter tolerance External Clock Source Powered by VCCIO_SDM Min -- Typ 25/100/125 -- Clock input duty cycle 45 50 Max 2 55 JTAG Configuration Timing Table 98. tJCP tJCH JTAG Timing Parameters and Values for Intel Agilex Devices For specification status, see the Data Sheet Status table Symbol Description Requirement Minimum TCK clock period 30 TCK clock high time 14 Maximum -- -- Unit ms ms Unit MHz % % Unit ns ns continued... (120) The acceptable clock frequencies are 25 MHz, 100 MHz, and 125 MHz only. You must match the external configuration clock frequency on the OSC_CLK_1 pin to the configuration clock source assignment in the Intel Quartus Prime software. Other frequencies in the range are not supported. Intel� AgilexTM Device Data Sheet 114 Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Symbol tJCL tJPSU (TDI) (121) tJPSU (TMS) (121) tJPH (121) tJPCO tJPZX tJPXZ Description TCK clock low time TDI JTAG port setup time TMS JTAG port setup time JTAG port hold time JTAG port clock to output JTAG port high impedance to valid output JTAG port valid output to high impedance Minimum 14 2 3 5 -- -- Requirement Maximum -- -- -- -- 7(122) 14 -- 14 Figure 26. JTAG Timing Diagram TMS TDI tJCP tJCH tJCL TCK tJPZX TDO tJPSU tJPH tJPCO tJPXZ Unit ns ns ns ns ns ns ns (121) For boundary-scan testing, the TMS and TDI JTAG ports minimum setup time and hold time are 7 ns. (122) Capacitance loading at 10 pF. Send Feedback Intel� AgilexTM Device Data Sheet 115 Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 AS Configuration Timing Table 99. AS Timing Parameters for Intel Agilex Devices Intel recommends performing trace length matching for nCSO and AS_DATA pins to AS_CLK to minimize the skew. The maximum tolerance for skew between nCSO and AS_CLK is recommended to be less than 200 ps. The tolerance for skew between AS_CLK to AS_DATA must be within �200 ps. For specification status, see the Data Sheet Status table Symbol Tclk (123) Tdutycycle Tdcsfrs Tdcslst Description AS_CLK clock period AS_CLK duty cycle AS_nCSO[3:0] asserted to first AS_CLK edge Last AS_CLK edge to AS_nCSO[3:0] deasserted Minimum -- 45 8.5(124) 6.8(124) Typical 6.02 50 -- -- Maximum -- 55 -- -- Unit ns % ns ns continued... (123) AS_CLK fMAX has dependency on the maximum board loading. For AS single device configuration or AS using multiple serial flash devices configuration, use the equations in Tdo and Text_delay notes to ensure your board has sufficient timing margin to meet flash setup/hold time specifications and Intel Agilex AS timing specifications in the Intel Agilex Device Datasheet. For AS using multiple serial flash devices, refer to the Intel Agilex Configuration User Guide for the recommended AS_CLK frequency and maximum board loading. (124) AS operating at maximum clock frequency = 166 MHz. The delay is larger when operating at AS clock frequency lower than 166 MHz. Intel� AgilexTM Device Data Sheet 116 Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Symbol Tdo (125) Text_delay (126) (127) Tdcsb2b Description AS_DATA[3:0] output delay Total external propagation delay on AS signals Minimum delay of slave select deassertion between two back-to-back transfers Minimum �0.6 0 62 Figure 27. AS Configuration Serial Output Timing Diagram nCSO T T dcsfrs do (min) Tdo (max) AS_CLK AS_DATA OUT0 Typical -- -- -- OUT1 Maximum 0.6 13.5 -- Tdcslst OUTn Unit ns ns ns (125) Load capacitance for DCLK = 12 pF and AS_DATA = 27 pF. Intel recommends obtaining the Tdo for a given link (including receiver, transmission lines, connectors, termination resistors, and other components) through IBIS or HSPIC simulation. To analyze flash setup time, � Tsu = Tclk/2 - Tdo(max) + Tbd_clk � Tbd_data(max) � Tho = Tclk/2 + Tdo(min) � Tbd_clk + Tbd_data(min) (126) Text_delay = Tbd_clk + Tco + Tbd_data + Tadd � Tbd_clk: Propagation delay for AS_CLK between FPGA and flash device. � Tco: Output hold time and clock low to output valid of flash device. This delay must be used to ensure Text_delay is within the minimum and maximum specification values. � Tbd_data: Propagation delay for AS_DATA bus between FPGA and flash device. � Tadd: Propagation delay for active/passive components on AS_DATA interfaces. (127) Text_delay specification is based on AS_CLK = 166 MHz. The value can be larger at lower AS_CLK frequency. For more details, refer to the Intel Agilex Configuration User Guide. Send Feedback Intel� AgilexTM Device Data Sheet 117 Figure 28. AS Configuration Serial Input Timing Diagram nCSO AS_CLK AS_DATA Text_delay IN0 IN1 Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Tdcsb2b INn Related Information Intel Agilex Configuration User Guide Provides more information about AS_CLK. Avalon Streaming (Avalon-ST) Configuration Timing Table 100. Avalon-ST Timing Parameters for x8, �16, and �32 Configurations in Intel Agilex Devices For specification status, see the Data Sheet Status table Symbol Description Minimum tACLKH tACLKL tACLKP tADSU (128) AVST_CLK high time 3.6 AVST_CLK low time 3.6 AVST_CLK period 8 AVST_DATA setup time before rising 2.1 edge of AVST_CLK Unit ns ns ns ns continued... (128) Data sampled by the FPGA (sink) at the next rising clock edge. Intel� AgilexTM Device Data Sheet 118 Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 tADH (128) tAVSU tAVDH Symbol Description AVST_DATA hold time after rising edge of AVST_CLK AVST_VALID setup time before rising edge of AVST_CLK AVST_VALID hold time after rising edge of AVST_CLK Figure 29. Avalon-ST Configuration Timing Diagram tACLKP tACLKH tACLKL AVSTx8_CLK or AVST_CLK AVST_READY or AVSTx8_READY tAVSU tAVDH AVSTx8_VALID or AVST_VALID AVSTx8_DATA[7:0] AVST_DATA[15:0] AVST_data[31:0]] tADSU tADH data0 data1 data2 data3 Minimum 0.1 2.1 0 must deassert within 6 cycles Unit ns ns ns Send Feedback Intel� AgilexTM Device Data Sheet 119 Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Configuration Bit Stream Sizes Table 101. Configuration Bit Stream Sizes for Intel Agilex Devices Configuration bit stream sizes shown in this table are based on worst-case scenarios. The sizes are typically substantially smaller because of the use of the Intel bit stream compression. The Intel bit stream compression efficiency has dependency on your design complexity. For specification status, see the Data Sheet Status table Variant AGF 006, AGF 008 AGF 012, AGF 014 AGF 019, AGF 023, AGI 019, AGI 023 AGF 022, AGF 027, AGI 022, AGI 027 Compressed Configuration Bit Stream Size (Mbits) 238 511 628 928 I/O Timing I/O timing data is typically used prior to designing the FPGA to get an estimate of the timing budget as part of the timing analysis. You may generate the I/O timing report manually using the Timing Analyzer. The Intel Quartus Prime Timing Analyzer provides a more accurate and precise I/O timing data based on the specifics of the design after you complete place-and-route. Related Information AN 775: I/O Timing Information Generation Guidelines Provides the techniques to generate I/O timing information using the Intel Quartus Prime software. Intel� AgilexTM Device Data Sheet 120 Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Programmable IOE Delay Table 102. Programmable IOE Delay for Intel Agilex Devices For specification status, see the Data Sheet Status table Parameter Maximum Offset Minimum Offset Fast Model Extended, Industrial Input Delay Chain 63 (INPUT_DELAY_CH AIN) 0 1.474 Output Delay Chain 15 (OUTPUT_DELAY_C HAIN) 0 0.356 Glossary Table 103. Glossary Term Differential I/O Standards Receiver Input Waveforms Single-Ended Waveform VID VCM Differential Waveform VID Transmitter Output Waveforms �E1, �I1 2.324 0.552 Slow Model �E2, �I2 2.631 0.629 Definition Positive Channel (p) = VIH Negative Channel (n) = VIL Ground p - n = 0 V VID �E3, �I3V 3.343 0.808 Unit ns ns continued... Send Feedback Intel� AgilexTM Device Data Sheet 121 Term fHSCLK fHSDR fHSDRDPA J (SERDES factor) JTAG Timing Specifications Intel� AgilexTM Device Data Sheet 122 Single-Ended Waveform VOD VCM Definition Positive Channel (p) = VOH Negative Channel (n) = VOL Ground Differential Waveform VOD p - n = 0 V VOD I/O PLL input clock frequency. LVDS SERDES block--maximum/minimum LVDS data transfer rate (fHSDR = 1/TUI), non-DPA. LVDS SERDES block--maximum/minimum LVDS data transfer rate (fHSDRDPA = 1/TUI), DPA. LVDS SERDES block--deserialization factor (width of parallel data bus). JTAG Timing Specifications: TMS TDI tJCP t JCH t JCL tJPSU TCK tJPZX tJPCO TDO tJPH tJPXZ Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 continued... Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Term RL Sampling window (SW) Definition Receiver differential input discrete resistor (external to the Intel Agilex device). Timing Diagram--the period of time during which the data must be valid in order to capture it correctly. The setup and hold times determine the ideal strobe position in the sampling window, as shown: Bit Time Single-ended voltage referenced I/O standard tC TCCS (channel-to-channel-skew) tDUTY tFALL tINCCJ tOUTPJ_IO 0.5 x TCCS RSKM Sampling Window RSKM 0.5 x TCCS (SW) The JEDEC standard for the SSTL and HSTL I/O defines both the AC and DC input signal values. The AC values indicate the voltage levels at which the receiver must meet its timing specifications. The DC values indicate the voltage levels at which the final logic state of the receiver is unambiguously defined. After the receiver input has crossed the AC value, the receiver changes to the new logic state. The new logic state is then maintained as long as the input stays beyond the DC threshold. This approach is intended to provide predictable receiver timing in the presence of input waveform ringing. Single-Ended Voltage Referenced I/O Standard V CCIO V OH V IH(AC) V IH(DC) V REF V IL(DC) V IL(AC) V OL V SS High-speed receiver/transmitter input and output clock period. The timing difference between the fastest and slowest output edges, including the tCO variation and clock skew, across channels driven by the same PLL. The clock is included in the TCCS measurement (refer to the Timing Diagram figure under SW in this table). LVDS SERDES block--duty cycle on high-speed transmitter output clock. Signal high-to-low transition time (80�20%). Cycle-to-cycle jitter tolerance on the PLL clock input. Period jitter on the GPIO driven by a PLL. continued... Send Feedback Intel� AgilexTM Device Data Sheet 123 Term tOUTPJ_DC tRISE Timing Unit Interval (TUI) VCM(DC) VICM VICM(DC) VID VDIF(AC) VDIF(DC) VIH VIH(AC) VIH(DC) VIL VIL(AC) VIL(DC) VOCM VOD VSWING VOX VIX(AC) W Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Definition Period jitter on the dedicated clock output driven by a PLL. Signal low-to-high transition time (20�80%). The timing budget allowed for skew, propagation delays, and the data sampling window. (TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = tC/w). DC Common mode input voltage. Input Common mode voltage--the common mode of the differential signal at the receiver. VCM(DC) DC Common mode input voltage. Input differential voltage swing--the difference in voltage between the positive and complementary conductors of a differential transmission at the receiver. AC differential input voltage--minimum AC input differential voltage required for switching. DC differential input voltage--minimum DC input differential voltage required for switching. Voltage input high--the minimum positive voltage applied to the input which is accepted by the device as a logic high. High-level AC input voltage. High-level DC input voltage. Voltage input low--the maximum positive voltage applied to the input which is accepted by the device as a logic low. Low-level AC input voltage. Low-level DC input voltage. Output Common mode voltage--the common mode of the differential signal at the transmitter. Output differential voltage swing--the difference in voltage between the positive and complementary conductors of a differential transmission line at the transmitter. Differential input voltage. Output differential cross point voltage. VIX Input differential cross point voltage. LVDS SERDES block--Clock Boost Factor. Intel� AgilexTM Device Data Sheet 124 Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Document Revision History for the Intel Agilex Device Data Sheet Document Version 2021.10.26 Changes � Updated the Data Sheet Status for Intel Agilex Devices (F-Series) table. -- Updated status for AGF 012/014 R24A package. -- Updated status for AGF 022/027 R25A package. -- Added AGF 012/014 R24B package. -- Added AGF 019/023 R25A, R24C, and R31C packages. � Added AGI 019/023 R18A and R31B packages in the Data Sheet Status for Intel Agilex Devices (I-Series) table. � Updated the Absolute Maximum Rating for Intel Agilex Devices table. -- Updated footnotes for IOUT condition. -- Changed symbol from VCCEH_FGT_GXF to VCCH_FGT_GXF. � Updated the Recommended Operating Conditions for Intel Agilex Devices table. -- Added IBAT specifications. -- Updated VI and VO specifications. � Added footnote to VCCCLK_GXP and VCCH_GXP in the P-Tile Transceiver Power Supply Operating Conditions for Intel Agilex Devices table. � Updated the R-Tile Transceiver Power Supply Operating Conditions for Intel Agilex Devices table. -- Updated symbol from VCCEHT_GXR[L,R] to VCCH_GXR[L,R]. -- Updated symbol from VCCERT_GXR[L,R] to VCCRT_GXR[L,R]. -- Updated specifications for VCCH_GXR[L,R], VCCED_GXR[L,R], VCCCLK_GXR[L,R], and VCC_HSSI_GXR. -- Added footnote to VCCH_GXR[L,R] and VCCCLK_GXR[L,R]. � Updated descriptions in the Internal Weak Pull-Up Resistor section. � Added VIL (min) and VIH (max) in the Single-Ended I/O Standards Specifications for Intel Agilex Devices (for HPS and SDM I/O Banks) table. � Added footnotes to tREFPJ and tREFPN in the I/O PLL Specifications for Intel Agilex Devices table. � Updated descriptions in the Remote Temperature Diode Specifications section. � Added the following tables: -- Remote Temperature Diode Specifications for Intel Agilex Devices (R-Tile TSD) -- Remote Temperature Diode Specifications for Intel Agilex Devices (F-Tile TSD) � Removed the reference to rate support and combined the following tables into one table: Memory Standards Supported by Intel Agilex Devices -- Memory Standards Supported by the Hard Memory Controller for Intel Agilex Devices -- Memory Standards Supported by the Soft Memory Controller for Intel Agilex Devices -- Memory Standards Supported by the HPS Hard Memory Controller for Intel Agilex Devices � Added footnote to FREF in the F-Tile FGT Reference Clock Input Specifications for Intel Agilex Devices table. � Updated ZREF-DIFF-DC_OUT and VREFIN-DIFF-AC_OUT descriptions in the F-Tile FGT Reference Clock Output Driver Specifications for Intel Agilex Devices table. continued... Send Feedback Intel� AgilexTM Device Data Sheet 125 Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Document Version Changes � Updated the F-Tile FHT Transmitter Electrical Specifications table. -- Updated TTX-DJ specification. -- Removed NGPLL specification. � Updated the F-Tile FGT Transmitter Electrical Specifications table. -- Updated VTX-DIFF-PKPK description. -- Added VTX-EYE-PKPK specifications. -- Removed NGPLL-PAM and NGPLL-NRZ specifications. � Updated the F-Tile FHT Receiver Electrical Specifications table. -- Added VRX-MAX and VRX-MIN specifications. -- Removed NGPLL specification. � Updated the F-Tile FGT Receiver Electrical Specifications table. -- Added VRX-MIN specifications. -- Updated footnote to VRX-MAX, VRX-CM-DC, and VIDLE-THRESH. -- Removed NGPLL-PAM and NGPLL-NRZ specifications. � Updated the F-Tile FHT Electrical Compliance List table. -- Removed IEEE 802.3cd 137/136, IEEE 802.3bj/bm 93, IEEE 802.3bj/bm 92, and IEEE 802.3by 111/110 specifications. -- Updated the protocols for CEI 4.0/5.0 specification. � Updated the F-Tile FGT Electrical Compliance List table. -- Updated specifications for SDI, JESD204A, JESD204B, JESD204C, Fiber Channel, Interlaken, and HDMI protocols. -- Added specifications for GPON protocol. � Updated tCF02ST0 to add specifications when security features enabled in the General Configuration Timing Specifications for Intel Agilex Devices table. continued... Intel� AgilexTM Device Data Sheet 126 Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Document Version 2021.06.02 Changes � Updated the description for Tdo in the AS Timing Parameters for Intel Agilex Devices table. � Updated the Configuration Bit Stream Sizes for Intel Agilex Devices table. -- Added table description. -- Added specifications for AGF 019, AGF 023, AGI 019, and AGI 023 devices. -- Updated specifications for AGF 012, AGF 014, AGF 022, AGF 027, AGI 022, and AGI 027 devices. � Updated the Programmable IOE Delay for Intel Agilex Devices table. -- Added Industrial grade and updated the fast model specifications. -- Added �E1, �I1, �I2, and �I3V speed grades, and updated the slow model specifications. � Updated the Data Sheet Status for Intel Agilex Devices (F-Series) table. -- Removed R17A and R20A packages. -- Added AGF 006 and AGF 008 devices for R24C package. � Added support for �E4X speed grade in the Intel Agilex Device Grades, Core Speed Grades, and Power Options Supported table. � Updated the Absolute Maximum Rating for Intel Agilex Devices table. -- Updated the maximum specifications for VCCR_CORE and VCCA_PLL. -- Removed VCCIO3V_GXB, VI (for VCCIO3V_GXB), VCC_HSSI_GXB, VCCH_GXB, VCCT_GXB, and VCCR_GXB specifications. -- Added R-tile specifications: VCCEHT_GXR, VCCERT_GXR, VCCED_GXR, VCCE_PLL_GXR, VCCE_DTS_GXR, VCCCLK_GXR, VCCHFUSE_GXR, and VCC_HSSI_GXR. -- Added F-tile specifications: VCCERT1_FHT_GXF, VCCERT2_FHT_GXF, VCCEHT_FHT_GXF, VCCERT_FGT_GXF, VCCEH_FGT_GXF, and VCCERT_GXF_COMBINE. � Updated the Recommended Operating Conditions for Intel Agilex Devices table. -- Added specifications for �4X speed grade for VCC and VCCP. -- Removed VCCH and VCCH_SDM specifications for H-tile and P-tile devices. -- Removed VCCIO3V_GXB and VI (for VCCIO3V_GXB) specifications. -- Added VCCH specifications for R-tile and F-tile devices. -- Removed condition for VCCH_SDM. � Updated the HPS Power Supply Operating Conditions for Intel Agilex Devices table. -- Added specifications for �4X speed grade for VCCL_HPS and VCCPLLDIG_HPS. -- Added footnote for VCCL_HPS and VCCPLLDIG_HPS. � Updated specifications for 34- and 40- RS in the OCT Calibration Accuracy Specifications for Intel Agilex Devices (for GPIO Bank) table. � Updated VID and VICM(DC) specifications in the Differential I/O Standards Specifications for Intel Agilex Devices (for GPIO Bank) table. � Added specifications for �4X speed grade in the Clock Tree Performance for Intel Agilex Devices table. � Updated the I/O PLL Specifications for Intel Agilex Devices table. -- Added specifications for �4X speed grade for fIN, fVCO, fOUT, and fOUT_EXT. -- Updated tOUTDUTY specifications. -- Updated footnote for tOUTPJ_DC, tOUTCCJ_DC, tOUTPJ_IO, and tOUTCCJ_IO. continued... Send Feedback Intel� AgilexTM Device Data Sheet 127 Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Document Version Changes � Updated the DSP Block Performance Specifications for Intel Agilex Devices table. -- Added specifications for �4X speed grade. -- Added footnote for Fixed-point 18 � 19 multiplier adder summed with 36-bit input mode -- Updated the modes as FP32 floating-point vector dot product and FP16 floating-point vector dot product. -- Added the following modes: � Sum/sub of two FP16 multiplications with FP32 (addition/subtraction) � Sum/sub of two FP16 multiplications with accumulation (addition/subtraction) � Added specifications for �4X speed grade in the Memory Block Performance Specifications for Intel Agilex Devices table. � Added footnote to Sampling Rate in the Local Temperature Sensor Specifications for Intel Agilex Devices table. � Removed description on H-tile in the Remote Temperature Diode Specifications section. � Updated the Voltage Sensor Specifications for Intel Agilex Devices table. -- Added footnote to Sampling Rate and Voltage sensor accuracy. -- Removed Differential non-linearity (DNL) and Integral non-linearity (INL) specifications. � Updated the description for the Memory Standards Supported by the Soft Memory Controller for Intel Agilex Devices table. � Updated MPU frequency specifications in the Maximum HPS Clock Frequencies for Intel Agilex Devices table. � Added the HPS Cold Reset for Intel Agilex Devices table. � Updated Tsu specification in the SPI Master Timing Requirements for Intel Agilex Devices table. � Updated Tsuss and Thss specifications in the SPI Slave Timing Requirements for Intel Agilex Devices table. � Updated Td specifications in the HPS Secure Digital (SD)/MultiMediaCard (MMC) Timing Requirements for Intel Agilex Devices table. � Updated Th specification in the HPS USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) Low Pin Interface (ULPI) Timing Requirements for Intel Agilex Devices table. � Updated footnotes for THIGH and TLOW specifications in the HPS I2C Timing Requirements for Intel Agilex Devices table. � Updated Td specifications in the Trace Timing Requirements for Intel Agilex Devices table. � Updated tJPH specification in the HPS JTAG Timing Requirements for Intel Agilex Devices table. � Updated typical specifications in the HPS Programmable I/O Delay (Output Path) for Intel Agilex Device and HPS Programmable I/O Delay (Input Path) for Intel Agilex Device tables. � Added tST12CF0 and tST02CF1 specifications in the General Configuration Timing Specifications for Intel Agilex Devices table. � Added General Configuration Timing Diagram. � Updated the AS Timing Parameters for Intel Agilex Devices table. -- Updated table description. -- Updated Tclk, Tdcsfrs, Tdcslst, Tdo, Text_delay, and Tdcsb2b specifications. -- Updated footnote for Text_delay. � Updated tADH specification in the Avalon-ST Timing Parameters for x8, �16, and �32 Configurations in Intel Agilex Devices table. � Updated the Configuration Bit Stream Sizes for Intel Agilex Devices table. -- Removed AGF 004 device. -- Updated specifications for AGF 006 device. continued... Intel� AgilexTM Device Data Sheet 128 Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Document Version 2021.01.07 Changes � Added R-tile and F-tile specifications. Added the following tables/sections: -- R-Tile Transceiver Power Supply Operating Conditions for Intel Agilex Devices table -- F-Tile Transceiver Power Supply Operating Conditions for Intel Agilex Devices table -- R-Tile Transceiver Performance Specifications section -- F-Tile Transceiver Performance Specifications section � Removed H-Tile specifications. The following tables/section are removed: -- H-Tile Transceiver Power Supply Operating Conditions for Intel Agilex Devices -- Remote Temperature Diode Specifications for Intel Agilex Devices (H-Tile TSD) -- H-Tile Transceiver Performance Specifications � Removed the following tables for 3 V I/O banks: -- Maximum Allowed Overshoot During Transitions for Intel Agilex Devices (for 3 V I/O Bank) -- I/O Pin Leakage Current for Intel Agilex Devices (for 3 V I/O Bank) -- Bus Hold Parameters for Intel Agilex Devices (for 3 V I/O Bank) -- OCT Without Calibration Resistance Tolerance Specifications for Intel Agilex Devices (for 3 V I/O Bank) -- Pin Capacitance for Intel Agilex Devices (for 3 V I/O Bank) -- Internal Weak Pull-Up Resistor Values for Intel Agilex Devices (for 3 V I/O Bank) -- Single-Ended I/O Standards Specifications for Intel Agilex Devices (for 3 V I/O Bank) � Updated the Data Sheet Status for Intel Agilex Devices tables. � Updated table title from Intel Agilex Device Grades and Speed Grades Supported to Intel Agilex Device Grades, Core Speed Grades, and Power Options Supported. � Added VCCIO3V_GXB, VI (for VCCIO3V_GXB), VCC_HSSI_GXB, VCCH_GXB, VCCT_GXB, and VCCR_GXB specifications in the Absolute Maximum Rating for Intel Agilex Devices table. � Updated the description in the Maximum Allowed Overshoot and Undershoot Voltage section. � Updated the figure title to Intel Agilex Devices Overshoot Duration Example (for 1.2 V GPIO Bank at VCCIO_PIO = 1.26 V). � Updated the Recommended Operating Conditions for Intel Agilex Devices table. -- Updated VCC and VCCP specifications. -- Updated description for VCCH. -- Added VCCH and VCCH_SDM specifications for H-tile and P-tile devices. -- Updated note to VCCBAT. -- Added VCCIO3V_GXB and VI (for VCCIO3V_GXB) specifications. -- Updated the minimum specification for tRAMP. � Added the H-Tile Transceiver Power Supply Operating Conditions for Intel Agilex Devices table. � Updated VCCL_HPS and VCCPLLDIG_HPS specifications in the HPS Power Supply Operating Conditions for Intel Agilex Devices table. � Updated the specifications in the I/O Pin Leakage Current for Intel Agilex Devices (For GPIO Bank) table. � Updated the specifications in the Bus Hold Parameters for Intel Agilex Devices (For GPIO Bank) table. continued... Send Feedback Intel� AgilexTM Device Data Sheet 129 Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Document Version Changes � Added specifications for 100- RD for VCCIO_PIO = 1.2 V in the OCT Without Calibration Resistance Tolerance Specifications for Intel Agilex Devices (For GPIO Bank) table. � Updated the specifications in the Pin Capacitance for Intel Agilex Devices table. � Updated the specifications in the Internal Weak Pull-Up Resistor Values for Intel Agilex Devices (For GPIO Bank) table. � Updated the Single-Ended I/O Standards Specifications for Intel Agilex Devices (For GPIO Bank) table. -- Removed note to 1.2 V LVCMOS in the Single-Ended I/O Standards Specifications for Intel Agilex Devices (for GPIO Bank) table. -- Added VOL and VOH specifications. � Added the following tables for HPS, SDM, and 3 V I/O banks: -- Maximum Allowed Overshoot During Transitions for Intel Agilex Devices (for 3 V I/O Bank) -- I/O Pin Leakage Current for Intel Agilex Devices (for HPS and SDM I/O Bank) -- I/O Pin Leakage Current for Intel Agilex Devices (for 3 V I/O Bank) -- Bus Hold Parameters for Intel Agilex Devices (for 3 V I/O Bank) -- OCT Without Calibration Resistance Tolerance Specifications for Intel Agilex Devices (for 3 V I/O Bank) -- Pin Capacitance for Intel Agilex Devices (for 3 V I/O Bank) -- Internal Weak Pull-Up and Weak Pull-Down Resistor Values for Intel Agilex Devices (for HPS and SDM I/O Banks) -- Internal Weak Pull-Up Resistor Values for Intel Agilex Devices (for 3 V I/O Bank) -- Hysteresis Specifications for Schmitt Trigger Input for Intel Agilex Devices (for HPS I/O Bank) -- Single-Ended I/O Standards Specifications for Intel Agilex Devices (for HPS and SDM I/O Banks) -- Single-Ended I/O Standards Specifications for Intel Agilex Devices (for 3 V I/O Bank) � Updated specification for �1 speed grade in the Clock Tree Performance for Intel Agilex Devices table. � Updated the I/O PLL Specifications for Intel Agilex Devices table. -- Updated fIN, fVCO, and fOUT specifications for �4F speed grade. -- Updated fOUT_EXT specifications for �2, �3, and �4 speed grades. -- Added tINCCJ specifications. -- Added note to tOUTPJ_DC, tOUTCCJ_DC, tOUTPJ_IO, and tOUTCCJ_IO. -- Updated condition for tOUTPJ_DC, tOUTCCJ_DC, tOUTPJ_IO, tOUTCCJ_IO, and tCASC_OUTPJ_DC. � Updated the description in the Remote Temperature Diode Specifications section. � Updated Ibias, Vbias, and diode ideality factor specifications in the Remote Temperature Diode Specifications for Intel Agilex Devices (E-Tile TSD) table. � Added the Remote Temperature Diode Specifications for Intel Agilex Devices (H-Tile TSD) table. � Updated the Voltage Sensor Specifications for Intel Agilex Devices table. -- Updated voltage sensor accuracy Vin range and specifications. -- Updated Unipolar Input Mode specifications. � Updated tx Jitter for data rate 600 Mbps � 1.6 Gbps in the LVDS SERDES Specifications for Intel Agilex Devices table. � Updated the jitter amplitude in the LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications for a Data Rate Equal to 1.6 Gbps diagram. � Updated the sinusoidal jitter for F3 and F4 in the LVDS SERDES Soft-CDR Sinusoidal Jitter Mask Values for a Data Rate Equal to 1.6 Gbps table. � Removed RLDRAM 3 specifications from the Memory Standards Supported by the Soft Memory Controller for Intel Agilex Devices table. continued... Intel� AgilexTM Device Data Sheet 130 Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Document Version Changes � Updated the E-Tile Receiver Specifications table. -- Updated absolute VMAX for a receiver pin specifications. -- Changed from VICM (AC coupled) to VCM (Internal AC coupled) and updated the specifications. � Updated the P-Tile PLLA Performance table. -- Added PLL bandwidth (BWTX-PKG_PLL1) and PLL peaking (PKGTX-PLL1) specifications for PCIe 5.0 GT/s. -- Updated PLL peaking (PKGTX-PLL2) specifications. -- Added note on PLL bandwidth and PLL peaking. � Updated the P-Tile PLLB Performance table. -- Added PLL bandwidth (BWTX-PKG_PLL2) and PLL peaking (PKGTX-PLL2) specifications. -- Added note on PLL bandwidth and PLL peaking. � Updated the P-Tile Reference Clock Specifications table. -- Updated notes to Input reference clock frequency and TCCJITTER. -- Added conditions for Rising edge rate, Falling edge rate, Duty cycle, VICM, TCCJITTER, and TSSC-MAX-PERIOD-SLEW parameters. -- Updated spread-spectrum downspread, absolute VMAX, and absolute VMIN specifications. � Added condition for differential on-chip termination resistors parameter in the P-Tile Transmitter Specifications table. � Updated the P-Tile Receiver Specifications table. -- Updated VID (diff p-p) specifications for PCIe 16.0 GT/s. -- Removed VICM (AC coupled) specifications. -- Added RREF specifications. � Added H-Tile Transceiver Performance Specifications section. � Updated fixed VCCL_HPS and MPU frequency for �1 speed grade in the Maximum HPS Clock Frequencies for Intel Agilex Devices table. � Updated the internal oscillator frequency in the HPS Internal Oscillator Frequency for Intel Agilex Devices table. � Added the HPS JTAG Timing Diagram. � Updated the HPS Programmable I/O Delay (Output Path) for Intel Agilex Device and HPS Programmable I/O Delay (Input Path) for Intel Agilex Device tables. � Removed note to tCF12ST1 in the General Configuration Timing Specifications for Intel Agilex Devices table. � Updated the POR Delay Specification for Intel Agilex Devices table. � Updated the description for clock input peak-to-peak period jitter tolerance parameter in the External Configuration Clock Source (OSC_CLK_1) Clock Input Requirements table. � Added notes to tJPSU (TDI), tJPSU (TMS), tJPH, and tJPCO in the JTAG Timing Parameters and Values for Intel Agilex Devices table. � Updated the AS Timing Parameters for Intel Agilex Devices table. -- Updated the note to Tdo. -- Updated Tdcsb2b specification. � Updated the AS Configuration Serial Input Timing Diagram to include Tdcsb2b. � Removed Maximum Configuration Time Estimation specifications. continued... Send Feedback Intel� AgilexTM Device Data Sheet 131 Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Document Version 2020.06.30 2020.05.14 2020.03.18 Changes � Updated the Recommended Operating Conditions for Intel Agilex Devices table. -- Added note to VCCIO_PIO_SDM. -- Removed the note on HPS_PORSEL from tRAMP. HPS_PORSEL pin is not available for Intel Agilex devices. � Added note to Text_delay in the AS Timing Parameters for Intel Agilex Devices table. � Removed SD/MMC configuration mode specifications in the following tables: -- POR Delay Specification for Intel Agilex Devices -- Maximum Configuration Time Estimation for Intel Agilex Devices Updated VCCFUSEWR_SDM specifications in the Recommended Operating Conditions for Intel Agilex Devices table. � Added the Absolute Maximum Rating for Intel Agilex Devices table. � Added Maximum Allowed Overshoot and Undershoot Voltage section. � Updated the Recommended Operating Conditions for Intel Agilex Devices table. -- Updated the typical values for VCC and VCCP. -- Added VCCR_CORE specifications. -- Updated description for VCCPT and VCCIO_PIO_SDM. -- Updated VCCFUSEWR_SDM and VI specifications. -- Updated VCCA_PLL specifications and description. -- Added a note for TJ minimum specifications for Industrial. -- Updated tRAMP minimum specification. � Updated the E-Tile Transceiver Power Supply Operating Conditions table. -- Updated VCCCLK_GXE for maximum DC level. -- Updated VCCCLK_GXE for recommended AC transient level. -- Updated wording for all recommended DC values from % of DC level to % of Vnominal. � Updated wording for all recommended DC values from % of DC level to % of Vnominal in the P-Tile Transceiver Power Supply Operating Conditions. � Updated the E-Tile Transmitter and Receiver Data Rate Performance Specifications table with the transceiver speed grades for the NRZ and PAM4 supported data rates. � Updated the transmitter differential output voltage peak-to-peak typical value in the E-Tile Transmitter Specifications table. � Updated the E-tile Receiver Specifications table: -- Added the absolute Vmax for a receiver pin specification -- Added the maximum peak-to-peak differential input voltage VID (diff p-p) before/after device configuration specification -- Added VICM (AC coupled) specification -- Removed the electrical idle detection voltage specification � Updated P-Tile Transceiver Performance: -- Added supported data rate for Gen1, Gen 2, Gen 3, and Gen 4 in the P-Tile Transmitter and Receiver Data Rate Performance table. -- Removed the maximum VCO frequency value and replaced it with a typical value in the P-Tile PLLA Performance table. -- Removed the maximum VCO frequency value and replaced it with a typical value in the P-Tile PLLB Performance table. continued... Intel� AgilexTM Device Data Sheet 132 Send Feedback Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Document Version Changes � Updated P-Tile Transmitter Specifications: -- Added PCIe condition for Supported I/O Standards. -- Removed VOCM (AC Coupled). � Updated P-Tile Receiver Specifications: -- Added PCIe condition for Supported I/O Standards. -- Added PCIe 8.0 GT/s and 16.0 GT/s specifications for the peak-to-peak differential input voltage VID (diff p-p) and added corresponding notes. -- Updated RESREF specification. Added a note to the RESREF specification. � Updated VCCL_HPS and VCCPLLDIG_HPS specifications for SmartVID in the HPS Power Supply Operating Conditions for Intel Agilex Devices table. � Changed Early Power Estimator (EPE) to Intel FPGA Power and Thermal Calculator. � Added a note to 1.2 V LVCMOS in the Single-Ended I/O Standards Specifications for Intel Agilex Devices table. � Added a note in the Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications for Intel Agilex Devices table. � Updated the Differential I/O Standards Specifications for Intel Agilex Devices table. -- Updated I/O standard name from "1.5 V True Differential Signaling" to "True Differential Signaling (Transmitter & Receiver)". -- Added specifications for True Differential Signaling (Receiver only). -- Updated note to True Differential Signaling. � Updated the I/O PLL Specifications for Intel Agilex Devices table. -- Added notes for tFCOMP, tOUTPJ_DC, and tOUTCCJ_DC. -- Removed tINCCJ specifications. -- Added tREFPJ and tREFPN specifications. -- Updated tOUTPJ_DC, tOUTCCJ_DC, tOUTPJ_IO, tOUTCCJ_IO, and tCASC_OUTPJ_DC specifications. � Added a note for fixed-point 27 � 27 multiplication mode in the DSP Block Performance Specifications for Intel Agilex Devices table. � Updated the Memory Block Performance Specifications for Intel Agilex Devices table. -- Updated the specifications for MLAB memory. -- Updated the specifications for M20K block and added low power (LP) specifications. � Updated the specifications in the Remote Temperature Diode Specifications for Intel Agilex Devices (Core Fabric TSD) table. � Added the Remote Temperature Diode Specifications for Intel Agilex Devices (P-Tile TSD) table. � Updated the LVDS SERDES Specifications for Intel Agilex Devices table. -- Updated the tx Jitter - True Differential I/O Standards specifications for �4 speed grade. -- Removed global, regional, or local in clock routing resource. � Updated the DPA Lock Time Specifications for Intel Agilex Devices table. -- Updated the description of the table. -- Updated the maximum data transition from 960 to 768. � Updated the jitter requirements in the Memory Output Clock Jitter Specifications section. � Updated the specifications in the Maximum HPS Clock Frequencies for Intel Agilex Devices table. � Updated the HPS Programmable I/O Delay (Output Path) for Intel Agilex Device and HPS Programmable I/O Delay (Input Path) for Intel Agilex Device tables. continued... Send Feedback Intel� AgilexTM Device Data Sheet 133 Intel� AgilexTM Device Data Sheet DS-1060 | 2021.10.26 Document Version 2019.12.18 2019.04.02 Changes � Updated the following diagrams: -- USB ULPI Timing Diagram -- RGMII TX Timing Diagram -- RMII TX Timing Diagram -- RMII RX Timing Diagram � Updated tST0 and tCD2UM specifications in the General Configuration Timing Specifications for Intel Agilex Devices table. � Added notes to Tclk and Tdo specifications in the AS Timing Parameters for Intel Agilex Devices table. � Updated tADSU and tAVSU specifications in the Avalon-ST Timing Parameters for �8, �16, and �32 Configurations in Intel Agilex Devices table. � Added the following tables: -- Configuration Bit Stream Sizes for Intel Agilex Devices -- Maximum Configuration Time Estimation for Intel Agilex Devices -- Programmable IOE Delay for Intel Agilex Devices Updated the I/O PLL Specifications for Intel Agilex Devices table. � Removed scanclk from fDYCONFIGCLK parameter. � Corrected the maximum specification for fDYCONFIGCLK from 200 MHz to 100 MHz. Initial release. Intel� AgilexTM Device Data Sheet 134 Send Feedback