Instruction Set Table 2 (Dual/Quad SPI Instructions,3-Byte Address Mode) . ... IO0 and IO1 are used for Standard and Dual SPI instructions. 2.
w25q256jv spi revi 10232018 plus
W25Q256JV
3V 256M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI
For Industrial & Industrial Plus Grade
Publication Release Date: October 23, 2018 Revision I
W25Q256JV
Table of Contents
1. GENERAL DESCRIPTIONS............................................................................................................. 5 2. FEATURES ....................................................................................................................................... 5 3. PACKAGE TYPES AND PIN CONFIGURATIONS........................................................................... 6
3.1 Pad Configuration WSON 8x6-mm, WFLGA 6x5-mm ......................................................... 6 3.2 Pad Description WSON 8x6-mm, WFLGA 6x5-mm ............................................................ 6 3.3 Pin Configuration SOIC 300-mil ........................................................................................... 7 3.4 Pin Description SOIC 300-mil ............................................................................................... 7 3.5 Ball Configuration TFBGA 8x6-mm (5x5 or 6x4 Ball Array) ................................................. 8 3.6 Ball Description TFBGA 8x6-mm ......................................................................................... 8 4. PIN DESCRIPTIONS ........................................................................................................................ 9 4.1 Chip Select (/CS) .................................................................................................................. 9 4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3)..................................... 9 4.3 Write Protect (/WP) .............................................................................................................. 9 4.4 HOLD (/HOLD) ..................................................................................................................... 9 4.5 Serial Clock (CLK) ................................................................................................................ 9 4.6 Reset (/RESET)(1) ................................................................................................................. 9 5. BLOCK DIAGRAM .......................................................................................................................... 10 6. FUNCTIONAL DESCRIPTIONS ..................................................................................................... 11 6.1 SPI Operations ................................................................................................................... 11
6.1.1 Standard SPI Instructions .....................................................................................................11 6.1.2 Dual SPI Instructions ............................................................................................................11 6.1.3 Quad SPI Instructions...........................................................................................................11 6.1.4 3-Byte / 4-Byte Address Modes ............................................................................................12 6.1.5 Software Reset & Hardware /RESET pin..............................................................................12 6.2 Write Protection .................................................................................................................. 13 7. STATUS AND CONFIGURATION REGISTERS ............................................................................ 14 7.1 Status Registers ................................................................................................................. 14 7.1.1 Erase/Write In Progress (BUSY) Status Only ................................................................14 7.1.2 Write Enable Latch (WEL) Status Only ..........................................................................14 7.1.3 Block Protect Bits (BP3, BP2, BP1, BP0) Volatile/Non-Volatile Writable .......................15 7.1.4 Top/Bottom Block Protect (TB) Volatile/Non-Volatile Writable .......................................15 7.1.5 Complement Protect (CMP) Volatile/Non-Volatile Writable............................................15 7.1.1 Status Register Protect (SRP, SRL) Volatile/Non-Volatile Writable ...............................16 7.1.2 Erase/Program Suspend Status (SUS) Status Only.......................................................17 7.1.3 Security Register Lock Bits (LB3, LB2, LB1) Volatile/Non-Volatile OTP Writable ..........17 7.1.4 Quad Enable (QE) Volatile/Non-Volatile Writable ..........................................................17
- 1 -
W25Q256JV
7.1.5 Current Address Mode (ADS) Status Only .....................................................................18 7.1.6 Power-Up Address Mode (ADP) Non-Volatile Writable ..................................................18 7.1.7 Write Protect Selection (WPS) Volatile/Non-Volatile Writable .......................................18 7.1.8 Output Driver Strength (DRV1, DRV0) Volatile/Non-Volatile Writable ...........................19 7.1.9 Reserved Bits Non Functional........................................................................................19 7.1.10 W25Q256JV Status Register Memory Protection (WPS = 0, CMP = 0).............................20 7.1.11 W25Q256JV Status Register Memory Protection (WPS = 0, CMP = 1).............................21 7.1.12 W25Q256JV Individual Block Memory Protection (WPS=1) ..............................................22 7.2 Extended Address Register Volatile Writable Only ...................................................... 23
8. INSTRUCTIONS ............................................................................................................................. 24
8.1 Device ID and Instruction Set Tables ................................................................................. 24 8.1.1 Manufacturer and Device Identification ................................................................................24 8.1.2 Instruction Set Table 1 (Standard/Dual/Quad SPI, 3-Byte Address Mode)(1) .......................25 8.1.3 Instruction Set Table 2 (Dual/Quad SPI Instructions,3-Byte Address Mode) .......................26 8.1.4 Instruction Set Table 3 (Standard SPI, 4-Byte Address Mode)(1)..........................................27 8.1.5 Instruction Set Table 4 (Dual/Quad SPI Instructions, 4-Byte Address Mode) ......................28
8.2 Instruction Descriptions ...................................................................................................... 30 8.2.1 Write Enable (06h) ...............................................................................................................30 8.2.2 Write Enable for Volatile Status Register (50h) ....................................................................30 8.2.3 Write Disable (04h)...............................................................................................................31 Figure 7. Write Disable Instruction for SPI Mode..............................................................................31 8.2.4 Read Status Register-1 (05h), Status Register-2 (35h) & Status Register-3 (15h) ..............31 8.2.5 Write Status Register-1 (01h), Status Register-2 (31h) & Status Register-3 (11h) ..............32 8.2.6 Read Extended Address Register (C8h) ..............................................................................34 8.2.7 Write Extended Address Register (C5h) ..............................................................................35 8.2.8 Enter 4-Byte Address Mode (B7h)........................................................................................36 8.2.9 Exit 4-Byte Address Mode (E9h) ..........................................................................................36 8.2.10 Read Data (03h) .................................................................................................................37 8.2.11 Read Data with 4-Byte Address (13h) ................................................................................38 8.2.12 Fast Read (0Bh) .................................................................................................................39 8.2.13 Fast Read with 4-Byte Address (0Ch) ................................................................................40 8.2.14 Fast Read Dual Output (3Bh) .............................................................................................41 8.2.15 Fast Read Dual Output with 4-Byte Address (3Ch) ............................................................42 8.2.16 Fast Read Quad Output (6Bh)............................................................................................43 8.2.17 Fast Read Quad Output with 4-Byte Address (6Ch)...........................................................44 8.2.18 Fast Read Dual I/O (BBh)...................................................................................................45 8.2.19 Fast Read Dual I/O with 4-Byte Address (BCh)..................................................................46 8.2.20 Fast Read Quad I/O (EBh) .................................................................................................47 8.2.21 Fast Read Quad I/O with 4-Byte Address (ECh) ................................................................48 8.2.22 Set Burst with Wrap (77h) ..................................................................................................49 8.2.23 Page Program (02h) ...........................................................................................................50 8.2.24 Page Program with 4-Byte Address (12h) ..........................................................................51
Publication Release Date: October 23, 2018
- 2 -
Revision I
W25Q256JV
8.2.25 8.2.26 8.2.27 8.2.28 8.2.29 8.2.30 8.2.31 8.2.32 8.2.33 8.2.34 8.2.35 8.2.36 8.2.37 8.2.38 8.2.39 8.2.40 8.2.41 8.2.42 8.2.43 8.2.44 8.2.45 8.2.46 8.2.47 8.2.48 8.2.49 8.2.50 8.2.51
Quad Input Page Program (32h) ........................................................................................52 Quad Input Page Program with 4-Byte Address (34h) .......................................................53 Sector Erase (20h) .............................................................................................................54 Sector Erase with 4-Byte Address (21h).............................................................................55 32KB Block Erase (52h) .....................................................................................................56 64KB Block Erase (D8h).....................................................................................................57 64KB Block Erase with 4-Byte Address (DCh) ...................................................................58 Chip Erase (C7h / 60h).......................................................................................................59 Erase / Program Suspend (75h) .........................................................................................60 Erase / Program Resume (7Ah) .........................................................................................61 Power-down (B9h) ..............................................................................................................62 Release Power-down / Device ID (ABh) .............................................................................63 Read Manufacturer / Device ID (90h) .................................................................................64 Read Manufacturer / Device ID Dual I/O (92h) ...................................................................65 Read Manufacturer / Device ID Quad I/O (94h) .................................................................66 Read Unique ID Number (4Bh)...........................................................................................67 Read JEDEC ID (9Fh) ........................................................................................................68 Read SFDP Register (5Ah) ................................................................................................69 Erase Security Registers (44h)...........................................................................................70 Program Security Registers (42h) ......................................................................................71 Read Security Registers (48h) ...........................................................................................72 Individual Block/Sector Lock (36h) .....................................................................................73 Individual Block/Sector Unlock (39h) ..................................................................................74 Read Block/Sector Lock (3Dh) ...........................................................................................75 Global Block/Sector Lock (7Eh)..........................................................................................76 Global Block/Sector Unlock (98h).......................................................................................76 Enable Reset (66h) and Reset Device (99h) ......................................................................77
9. ELECTRICAL CHARACTERISTICS............................................................................................... 78 9.1 Absolute Maximum Ratings (1) .......................................................................................... 78
9.2 Operating Ranges............................................................................................................... 78
9.3 Power-up Power-down Timing and Requirements ............................................................. 79
9.4 DC Electrical Characteristics .............................................................................................. 80
9.5 AC Measurement Conditions.............................................................................................. 81 9.6 AC Electrical Characteristics(6) ........................................................................................... 82 9.7 AC Electrical Characteristics (cont'd) .............................................................................. 83
9.8 Serial Output Timing ........................................................................................................... 84
9.9 Serial Input Timing.............................................................................................................. 84
9.1 /WP Timing......................................................................................................................... 84
9.2 PACKAGE SPECIFICATIONs ............................................................................................ 85
9.3 8-Pad WFLGA 6x5-mm (Package Code M)....................................................................... 85
9.4 8-Pad WSON 8x6-mm (Package Code E) ......................................................................... 86
- 3 -
W25Q256JV
9.5 16-Pin SOIC 300-mil (Package Code F) ............................................................................ 87 9.6 24-Ball TFBGA 8x6-mm (Package Code B, 5x5-1 Ball Array) ........................................... 88 9.7 24-Ball TFBGA 8x6-mm (Package Code C, 6x4 Ball Array) .............................................. 89 9.8 Ordering Information........................................................................................................... 90 9.9 Valid Part Numbers and Top Side Marking ........................................................................ 91 10. REVISION IISTORY ....................................................................................................................... 93
Publication Release Date: October 23, 2018
- 4 -
Revision I
W25Q256JV
1. GENERAL DESCRIPTIONS
The W25Q256JV (256M-bit) Serial Flash memory provides a storage solution for systems with limited space, pins and power. The 25Q series offers flexibility and performance well beyond ordinary Serial Flash devices. They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI (XIP) and storing voice, text and data. The device operates on a single 2.7V to 3.6V power supply with current consumption as low as 1µA for power-down. All devices are offered in space-saving packages.
The W25Q256JV array is organized into 131,072 programmable pages of 256-bytes each. Up to 256 bytes can be programmed at a time. Pages can be erased in groups of 16 (4KB sector erase), groups of 128 (32KB block erase), groups of 256 (64KB block erase) or the entire chip (chip erase). The W25Q256JV has 8,192 erasable sectors and 512 erasable blocks respectively. The small 4KB sectors allow for greater flexibility in applications that require data and parameter storage.
The W25Q256JV supports the standard Serial Peripheral Interface (SPI), Dual/Quad I/O SPI: Serial Clock, Chip Select, Serial Data I/O0 (DI), I/O1 (DO), I/O2, and I/O3. SPI clock frequencies of W25Q256JV of up to 133MHz are supported allowing equivalent clock rates of 266MHz (133MHz x 2) for Dual I/O and 532MHz (133MHz x 4) for Quad I/O when using the Fast Read Dual/Quad I/O. These transfer rates can outperform standard Asynchronous 8 and 16-bit Parallel Flash memories.
Additionally, the device supports JEDEC standard manufacturer and device ID and SFDP Register, a 64bit Unique Serial Number and three 256-bytes Security Registers.
2. FEATURES
New Family of SpiFlash Memories W25Q256JV: 256M-bit / 32M-byte Standard SPI: CLK, /CS, DI, DO Dual SPI: CLK, /CS, IO0, IO1, Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3 3 or 4-Byte Addressing Mode Software & Hardware Reset(1)
Highest Performance Serial Flash 133MHz Standard/Dual/Quad SPI clocks 266/532MHz equivalent Dual/Quad SPI 66MB/S continuous data transfer rate Min. 100K Program-Erase cycles per sector More than 20-year data retention
Efficient "Continuous Read" Quad Peripheral Interface Allows true XIP (execute in place) operation Outperforms X16 Parallel Flash
Low Power, Wide Temperature Range Single 2.7 to 3.6V supply <1µA Power-down (typ.) -40°C to +85°C operating range -40°C to +105°C operating range
Flexible Architecture with 4KB sectors Uniform Sector/Block Erase (4K/32K/64K-Byte) Program 1 to 256 byte per programmable page Erase/Program Suspend & Resume
Advanced Security Features Software and Hardware Write-Protect Power Supply Lock-Down Special OTP protection Top/Bottom, Complement array protection Individual Block/Sector array protection 64-Bit Unique ID for each device Discoverable Parameters (SFDP) Register 3X256-Bytes Security Registers with OTP locks Volatile & Non-volatile Status Register Bits
Space Efficient Packaging(2) 8-pad WSON 8x6-mm 8-pad WFLGA 6x5-mm 16-pin SOIC 300-mil (additional /Reset pin) 24-ball TFBGA 8x6-mm(additional /Reset pin) Contact Winbond for KGD and other options
Note: 1. Hardware /RESET pin is only available on TFBGA or SOIC16 packages 2. Please contact Winbond for other packages.
- 5 -
W25Q256JV
3. PACKAGE TYPES AND PIN CONFIGURATIONS
3.1 Pad Configuration WSON 8x6-mm, WFLGA 6x5-mm
Top View
/CS DO (IO1) /WP (IO2)
18 27 36
VCC
/HOLD or /RESET (IO3) CLK
GND
45
DI (IO0)
Figure 1a. W25Q256JV Pad Assignments, 8-pad WSON 8x6-mm (Package Code E & M)
3.2 Pad Description WSON 8x6-mm, WFLGA 6x5-mm
PAD NO.
PAD NAME
I/O
FUNCTION
1
/CS
I
Chip Select Input
2
DO (IO1)
I/O
Data Output (Data Input Output 1)(1)
3
/WP (IO2)
I/O
Write Protect Input ( Data Input Output 2)(2)
4
GND
Ground
5
DI (IO0)
I/O
Data Input (Data Input Output 0)(1)
6
CLK
I
Serial Clock Input
7
/HOLD or /RESET (IO3)
I/O
Hold or Reset Input (Data Input Output 3)(2)
8
VCC
Power Supply
Notes:
1. IO0 and IO1 are used for Standard and Dual SPI instructions 2. IO0 IO3 are used for Quad SPI instructions, /HOLD (or /RESET) function is only available for Standard/Dual SPI.
Publication Release Date: October 23, 2018
- 6 -
Revision I
3.3 Pin Configuration SOIC 300-mil
W25Q256JV
Figure 1b. W25Q256JV Pin Assignments, 16-pin SOIC 300-mil (Package Code F)
3.4 Pin Description SOIC 300-mil
PIN NO.
PIN NAME
I/O
FUNCTION
1
/HOLD or
I/O
Hold or Reset Input (Data Input Output 3)(2)
/RESET (IO3)
2
VCC
Power Supply
3
/RESET
I
Reset Input(3)
4
N/C
No Connect
5
N/C
No Connect
6
N/C
No Connect
7
/CS
I
Chip Select Input
8
DO (IO1)
I/O
Data Output (Data Input Output 1)(1)
9
/WP (IO2)
I/O
Write Protect Input (Data Input Output 2)(2)
10
GND
Ground
11
N/C
No Connect
12
N/C
No Connect
13
N/C
No Connect
14
N/C
No Connect
15
DI (IO0)
I/O
Data Input (Data Input Output 0)(1)
16
CLK
I
Serial Clock Input
Notes: 1. IO0 and IO1 are used for Standard and Dual SPI instructions. 2. IO0 IO3 are used for Quad SPI instructions, /HOLD (or /RESET) function is only available for Standard/Dual SPI. 3. The /RESET pin is a dedicated hardware reset pin regardless of device settings or operation states. If the hardware reset function is not used, this pin can be left floating or connected to VCC in the system.
- 7 -
W25Q256JV
3.5 Ball Configuration TFBGA 8x6-mm (5x5 or 6x4 Ball Array)
Top View
Top View
A2
A3
A4
A5
NC
NC /RESET NC
B1
B2
B3
B4
B5
NC
CLK
GND
VCC
NC
C1
C2
C3
C4
C5
NC
/CS
NC /WP (IO2) NC
D1
D2
D3
D4
D5
NC DO(IO1) DI(IO0) /HOLD(IO3) NC
E1
E2
E3
E4
E5
NC
NC
NC
NC
NC
A1
A2
A3
A4
NC
NC
NC /RESET
B1
B2
B3
B4
NC
CLK
GND
VCC
C1
C2
C3
C4
NC
/CS
NC /WP (IO2)
D1
D2
D3
D4
NC DO(IO1) DI(IO0) /HOLD(IO3)
E1
E2
E3
E4
NC
NC
NC
NC
F1
F2
F3
F4
NC
NC
NC
NC
Package Code B
Package Code C
Figure 1c. W25Q256JV Ball Assignments, 24-ball TFBGA 6x8-mm (Package Code B & C)
3.6 Ball Description TFBGA 8x6-mm
BALL NO.
PIN NAME
I/O
FUNCTION
A4
/RESET
I
Reset Input(3)
B2
CLK
I
Serial Clock Input
B3
GND
Ground
B4
VCC
Power Supply
C2
/CS
I
Chip Select Input
C4
/WP (IO2)
I/O Write Protect Input (Data Input Output 2)(2)
D2
DO (IO1)
I/O Data Output (Data Input Output 1)(1)
D3
DI (IO0)
I/O
Data Input (Data Input Output 0)(1)
D4
/HOLD (IO3)
I/O Hold or Reset Input (Data Input Output 3)(2)
Multiple
NC
No Connect
Notes:
1. IO0 and IO1 are used for Standard and Dual SPI instructions 2. IO0 IO3 are used for Quad SPI instructions, /HOLD (or /RESET) function is only available for Standard/Dual SPI.
3. The /RESET pin is a dedicated hardware reset pin regardless of device settings or operation states. If the hardware reset function is not used, this pin can be left floating or connected to VCC in the system
Publication Release Date: October 23, 2018
- 8 -
Revision I
W25Q256JV
4. PIN DESCRIPTIONS
4.1 Chip Select (/CS)
The SPI Chip Select (/CS) pin enables and disables device operation. When /CS is high the device is deselected and the Serial Data Output (DO, or IO0, IO1, IO2, IO3) pins are at high impedance. When deselected, the devices power consumption will be at standby levels unless an internal erase, program or write status register cycle is in progress. When /CS is brought low the device will be selected, power consumption will increase to active levels and instructions can be written to and data read from the device. After power-up, /CS must transition from high to low before a new instruction will be accepted. The /CS input must track the VCC supply level at power-up and power-down (see "Write Protection" and Figure 58). If needed a pull-up resistor on the /CS pin can be used to accomplish this.
4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3)
The W25Q256JV supports standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions use the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to read data or status from the device on the falling edge of CLK.
Dual and Quad SPI instructions use the bidirectional IO pins to serially write instructions, addresses or data to the device on the rising edge of CLK and read data or status from the device on the falling edge of CLK. Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be set. When QE=1, the /WP pin becomes IO2 and the /HOLD pin becomes IO3.
4.3 Write Protect (/WP)
The Write Protect (/WP) pin can be used to prevent the Status Register from being written. Used in conjunction with the Status Register's Block Protect (CMP, SEC, TB, BP2, BP1 and BP0) bits and Status Register Protect (SRP) bits, a portion as small as a 4KB sector or the entire memory array can be hardware protected. The /WP pin is active low.
4.4 HOLD (/HOLD)
The /HOLD pin allows the device to be paused while it is actively selected. When /HOLD is brought low, while /CS is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be ignored (don't care). When /HOLD is brought high, device operation can resume. The /HOLD function can be useful when multiple devices are sharing the same SPI signals. The /HOLD pin is active low. When the QE bit of Status Register-2 is set for Quad I/O, the /HOLD pin function is not available since this pin is used for IO3. See Figure 1a-c for the pin configuration of Quad I/O operation.
4.5 Serial Clock (CLK)
The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See SPI Operations")
4.6 Reset (/RESET)(1)
A dedicated hardware /RESET pin is available on SOIC-16 and TFBGA packages. When it's driven low for a minimum period of ~1µS, this device will terminate any external or internal operations and return to its power-on state. Note: Hardware /RESET pin is available on SOIC-16 or TFBGA; please contact Winbond for this package.
- 9 -
5. BLOCK DIAGRAM
W25Q256JV
Figure 2. W25Q256JV Serial Flash Memory Block Diagram
- 10 -
Publication Release Date: October 23, 2018 Revision I
W25Q256JV
6. FUNCTIONAL DESCRIPTIONS 6.1 SPI Operations
Hardware Reset
Power Up
Device Initialization & Status Register Refresh
( Non- Volatile Cells)
ADP = 0
ADP bit value
ADP = 1
3- Byte Address
Standard SPI Dual SPI Quad SPI
Enable 4- Byte (B7h) Disable 4- Byte (E9h)
4- Byte Address
Standard SPI Dual SPI Quad SPI
SPI Reset (66 h + 99h)
Figure 3. W25Q256JV Serial Flash Memory Operation Diagram
6.1.1 Standard SPI Instructions The W25Q256JV is accessed through an SPI compatible bus consisting of four signals: Serial Clock (CLK), Chip Select (/CS), Serial Data Input (DI) and Serial Data Output (DO). Standard SPI instructions use the DI input pin to serially write instructions, addresses or data to the device on the rising edge of CLK. The DO output pin is used to read data or status from the device on the falling edge of CLK.
SPI bus operation Mode 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and Mode 3 concerns the normal state of the CLK signal when the SPI bus master is in standby and data is not being transferred to the Serial Flash. For Mode 0, the CLK signal is normally low on the falling and rising edges of /CS. For Mode 3, the CLK signal is normally high on the falling and rising edges of /CS.
6.1.2 Dual SPI Instructions The W25Q256JV supports Dual SPI operation when using instructions such as "Fast Read Dual Output (3Bh)" and "Fast Read Dual I/O (BBh)". These instructions allow data to be transferred to or from the device at two to three times the rate of ordinary Serial Flash devices. The Dual SPI Read instructions are ideal for quickly downloading code to RAM upon power-up (code-shadowing) or for executing non-speedcritical code directly from the SPI bus (XIP). When using Dual SPI instructions, the DI and DO pins become bidirectional I/O pins: IO0 and IO1.
6.1.3 Quad SPI Instructions The W25Q256JV supports Quad SPI operation when using instructions such as "Fast Read Quad Output (6Bh)", and "Fast Read Quad I/O (EBh)". These instructions allow data to be transferred to or from the device four to six times the rate of ordinary Serial Flash. The Quad Read instructions offer a significant improvement in random access transfer rates allowing fast code-shadowing to RAM or execution directly from the SPI bus (XIP). When using Quad SPI instructions the DI and DO pins become bidirectional IO0 and IO1, and the /WP and /HOLD pins become IO2 and IO3 respectively. Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be set.
- 11 -
W25Q256JV
6.1.4 3-Byte / 4-Byte Address Modes The W25Q256JV provides two Address Modes that can be used to specify any byte of data in the memory array. The 3-Byte Address Mode is backward compatible to older generations of serial flash memory that only support up to 128M-bit data. To address the 256M-bit or more data in 3-Byte Address Mode, Extended Address Register must be used in addition to the 3-Byte addresses. 4-Byte Address Mode is designed to support Serial Flash Memory devices from 256M-bit to 32G-bit. The extended Address Register is not necessary when the 4-Byte Address Mode is enabled. Upon power up, the W25Q256JV can operate in either 3-Byte Address Mode or 4-Byte Address Mode, depending on the Non-Volatile Status Register Bit ADP (S17) setting. If ADP=0, the device will operate in 3-Byte Address Mode; if ADP=1, the device will operate in 4-Byte Address Mode. The factory default value for ADP is 0. To switch between the 3-Byte or 4-Byte Address Modes, "Enter 4-Byte Mode (B7h)" or "Exit 4-Byte Mode (E9h)" instructions must be used. The current address mode is indicated by the Status Register Bit ADS (S16). W25Q256JV also supports a set of basic SPI instructions which requires dedicated 4-Byte address regardless the device Address Mode setting. Please refer to Instruction Set Table 2 for details.
6.1.5 Software Reset & Hardware /RESET pin
The W25Q256JV can be reset to the initial power-on state by a software Reset sequence in SPI mode. This sequence must include two consecutive commands: Enable Reset (66h) & Reset (99h). If the command sequence is successfully accepted, the device will take approximately 30uS (tRST) to reset. No command will be accepted during the reset period.
For the SOIC-16 and TFBGA package, W25Q256JV provides a dedicated /RESET pin. Drive the /RESET pin low for a minimum period of ~1us (tRESET*) will reset the device to its initial power-on state.
Hardware /RESET pin has the highest priority among all the input signals. Drive /RESET low for a minimum period of ~1us (tRESET*) will interrupt any on-going external/internal operations, regardless the status of other SPI signals (/CS, CLK, IOs).
Note: 1.While a faster /RESET pulse (as short as a few hundred nanoseconds) will often reset the device, a
1us minimum pulse is recommended to ensure reliable operation. 2.There is an internal pull-up resistor for the dedicated /RESET pin on the SOIC-16 package. If the reset
function is not used, this pin can be left floating in the system.
- 12 -
Publication Release Date: October 23, 2018 Revision I
W25Q256JV
6.2 Write Protection
Applications that use non-volatile memory must take into consideration the possibility of noise and other adverse system conditions that may compromise data integrity. To address this concern, the W25Q256JV provides several means to protect the data from inadvertent writes.
Device resets when VCC is below threshold Time delay write disable after Power-up Write enable/disable instructions and automatic write disable after erase or program Software and Hardware (/WP pin) write protection using Status Registers Additional Individual Block/Sector Locks for array protection Write Protection using Power-down instruction Lock Down write protection for Status Register until the next power-up One Time Program (OTP) write protection for array and Security Registers using Status Register*
* Note: This feature is available upon special order. Please contact Winbond for details.
Upon power-up or at power-down, the W25Q256JV will maintain a reset condition while VCC is below the threshold value of VWI, (See Power-up Timing and Voltage Levels and Figure 43). While reset, all operations are disabled and no instructions are recognized. During power-up and after the VCC voltage exceeds VWI, all program and erase related instructions are further disabled for a time delay of tPUW. This includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase and the Write Status Register instructions. Note that the chip select pin (/CS) must track the VCC supply level at power-up until the VCC-min level and tVSL time delay is reached, and it must also track the VCC supply level at powerdown to prevent adverse command sequence. If needed, a pull-up resistor on /CS pin can be used to accomplish this. After power-up the device is automatically placed in a write-disabled state with the Status Register Write Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page Program, Sector Erase, Block Erase, Chip Erase or Write Status Register instruction will be accepted. After completing a program, erase or write instruction the Write Enable Latch (WEL) is automatically cleared to a writedisabled state of 0. Software controlled write protection is facilitated using the Write Status Register instruction and setting the Status Register Protect (SRP, SRL) and Block Protect (CMP, TB, BP[3:0]) bits. These settings allow a portion or the entire memory array to be configured as read only. Used in conjunction with the Write Protect (/WP) pin, changes to the Status Register can be enabled or disabled under hardware control. See Status Register section for further information. Additionally, the Power-down instruction offers an extra level of write protection as all instructions are ignored except for the Release Power-down instruction.
The W25Q256JV also provides another Write Protect method using the Individual Block Locks. Each 64KB block (except the top and bottom blocks, total of 510 blocks) and each 4KB sector within the top/bottom blocks (total of 32 sectors) are equipped with an Individual Block Lock bit. When the lock bit is 0, the corresponding sector or block can be erased or programmed; when the lock bit is set to 1, Erase or Program commands issued to the corresponding sector or block will be ignored. When the device is powered on, all Individual Block Lock bits will be 1, so the entire memory array is protected from Erase/Program. An "Individual Block Unlock (39h)" instruction must be issued to unlock any specific sector or block. The WPS bit in Status Register-3 is used to decide which Write Protect scheme should be used. When WPS=0 (factory default), the device will only utilize CMP, TB, BP[3:0] bits to protect specific areas of the array; when WPS=1, the device will utilize the Individual Block Locks for write protection.
- 13 -
W25Q256JV
7. STATUS AND CONFIGURATION REGISTERS
Three Status and Configuration Registers are provided for W25Q256JV. The Read Status Register-1/2/3 instructions can be used to provide status on the availability of the flash memory array, whether the device is write enabled or disabled, the state of write protection, Quad SPI setting, Security Register lock status, Erase/Program Suspend status, output driver strength, power-up and current Address Mode. The Write Status Register instruction can be used to configure the device write protection features, Quad SPI setting, Security Register OTP locks functions, output driver strength and power-up Address Mode. Write access to the Status Register is controlled by the state of the non-volatile Status Register Lock bits (SRL), and the Write Enable instruction.
7.1 Status Registers
Status Register Protect (Volatile/Non-Volatile Writable)
Top/Bottom Protect Bit (Volatile/Non-Volatile Writable)
Block Protect Bits (Volatile/Non-Volatile Writable)
Write Enable Latch (Status-Only)
Erase/Write Isn Progress (Status-Only)
s
S 7 SRP
S6 S5 S4 S3 S2 S1 S0 TB BP3 BP2 BP1 BP0 WEL BUSY
Figure 4a. Status Register-1
7.1.1 Erase/Write In Progress (BUSY) Status Only
BUSY is a read only bit in the status register (S0) that is set to a 1 state when the device is executing a Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register or Erase/Program Security Register instruction. During this time the device will ignore further instructions except for the Read Status Register and Erase/Program Suspend instruction (see tW, tPP, tSE, tBE, and tCE in AC Characteristics). When the program, erase or write status/security register instruction has completed, the BUSY bit will be cleared to a 0 state indicating the device is ready for further instructions.
7.1.2 Write Enable Latch (WEL) Status Only
Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to 1 after executing a Write Enable Instruction. The WEL status bit is cleared to 0 when the device is write disabled. A write disable state occurs upon power-up or after any of the following instructions: Write Disable, Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Erase Security Register and Program Security Register.
- 14 -
Publication Release Date: October 23, 2018 Revision I
W25Q256JV
7.1.3 Block Protect Bits (BP3, BP2, BP1, BP0) Volatile/Non-Volatile Writable The Block Protect Bits (BP3, BP2, BP1, BP0) are non-volatile read/write bits in the status register (S5, S4, S3, and S2) that provide Write Protection control and status. Block Protect bits can be set using the Write Status Register Instruction (see tW in AC characteristics). All, none or a portion of the memory array can be protected from Program and Erase instructions (see Status Register Memory Protection table). The factory default setting for the Block Protection Bits is 0, none of the array protected. 7.1.4 Top/Bottom Block Protect (TB) Volatile/Non-Volatile Writable The non-volatile Top/Bottom bit (TB) controls if the Block Protect Bits (BP3, BP2, BP1, BP0) protect from the Top (TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table. The factory default setting is TB=0. The TB bit can be set with the Write Status Register Instruction depending on the state of the WEL bits. 7.1.5 Complement Protect (CMP) Volatile/Non-Volatile Writable The Complement Protect bit (CMP) is a non-volatile read/write bit in the status register (S14). It is used in conjunction with TB, BP3, BP2, BP1 and BP0 bits to provide more flexibility for the array protection. Once CMP is set to 1, previous array protection set by TB, BP3, BP2, BP1 and BP0 will be reversed. For instance, when CMP=0, a top 64KB block can be protected while the rest of the array is not; when CMP=1, the top 64KB block will become unprotected while the rest of the array become read-only. Please refer to the Status Register Memory Protection table for details. The default setting is CMP=0.
- 15 -
W25Q256JV
7.1.1 Status Register Protect (SRP, SRL) Volatile/Non-Volatile Writable
Three Status and Configuration Registers are provided for W25Q256JV. The Read Status Register-1/2/3 instructions can be used to provide status on the availability of the flash memory array, whether the device is write enabled or disabled, the state of write protection, Quad SPI setting, Security Register lock status, Erase/Program Suspend status, and output driver strength, The Write Status Register instruction can be used to configure the device write protection features, Quad SPI setting, Security Register OTP locks, output driver. Write access to the Status Register is controlled by the state of the non-volatile Status Register Protect bits (SRP, SRL), the Write Enable instruction, and during Standard/Dual SPI operations, the /WP pin.
Status SRL SRP /WP Register
Description
0
0
X
Software Protection
/WP pin has no control. The Status register can be written to after a Write Enable instruction, WEL=1. [Factory Default]
0
1
0
Hardware Protected
When /WP pin is low the Status Register locked and cannot be written to.
0
1
1
Hardware Unprotected
When /WP pin is high the Status register is unlocked and can be written to after a Write Enable instruction, WEL=1.
1
X
X
Power Supply Status Register is protected and cannot be written to again until
Lock-Down
the next power-down, power-up cycle.(1)
1
X
X
One Time Program(2)
Status Register is permanently protected and cannot be written to. (enabled by adding prefix command AAh, 55h)
1. When SRL =1, a power-down, power-up cycle will change SRL =0 state. 2. Please contact Winbond for details regarding the special instruction sequence.
- 16 -
Publication Release Date: October 23, 2018 Revision I
W25Q256JV
S15 S14 S13 S12 S11 S10 S9 S8
SUS CMP LB3 LB2 LB1 (R) QE SRL Suspend Status
(Status-Only) Complement Protect (Volatile/Non-Volatile Writable) Security Register Lock Bits (Volatile/Non-Volatile OTP Writable)
Reserved Quad Enable (Volatile/Non-Volatile Writable) Status Register Protect 1 (Volatile/Non-Volatile Writable)
Figure 4b. Status Register-2
7.1.2 Erase/Program Suspend Status (SUS) Status Only The Suspend Status bit is a read only bit in the status register (S15) that is set to 1 after executing a Erase/Program Suspend (75h) instruction. The SUS status bit is cleared to 0 by Erase/Program Resume (7Ah) instruction as well as a power-down, power-up cycle.
7.1.3 Security Register Lock Bits (LB3, LB2, LB1) Volatile/Non-Volatile OTP Writable The Security Register Lock Bits (LB3, LB2, LB1) are non-volatile One Time Program (OTP) bits in Status Register (S13, S12, S11) that provide the write protect control and status to the Security Registers. The default state of LB3-1 is 0, Security Registers are unlocked. LB3-1 can be set to 1 individually using the Write Status Register instruction. LB3-1 are One Time Programmable (OTP), once it's set to 1, the corresponding 256-Byte Security Register will become read-only permanently. 7.1.4 Quad Enable (QE) Volatile/Non-Volatile Writable The Quad Enable (QE) bit is a non-volatile read/write bit in the status register (S9) that enables Quad SPI operation. When the QE bit is set to a 0 state (factory default for part numbers with ordering options "IM" & "JM"), the /HOLD are enabled, the device operates in Standard/Dual SPI modes. When the QE bit is set to a 1 (factory fixed default for part numbers with ordering options "IQ" & "JQ"), the Quad IO2 and IO3 pins are enabled, and /HOLD function is disabled, the device operates in Standard/Dual/Quad SPI modes.
- 17 -
W25Q256JV
Reserved
Output Driver Strength
(Volatile/Non-Volatile Writable)
S23 S22 S21 S20 S19 S18 S17 S16 (R) DRV1 DRV0 (R) (R) WPS ADP ADS
Reserved
Write Protect Selection
(Volatile/Non-Volatile Writable)
Power Up Address Mode
(Non-Volatile Writable)
Current Address Mode
(Status-Only)
Figure 4c. Status Register-3
7.1.5 Current Address Mode (ADS) Status Only
The Current Address Mode bit is a read only bit in the Status Register-3 that indicates which address mode the device is currently operating in. When ADS=0, the device is in the 3-Byte Address Mode, when ADS=1, the device is in the 4-Byte Address Mode.
7.1.6 Power-Up Address Mode (ADP) Non-Volatile Writable
The ADP bit is a non-volatile bit that determines the initial address mode when the device is powered on or reset. This bit is only used during the power on or device reset initialization period, and it is only writable by the non-volatile Write Status sequence (06h + 11h). When ADP=0 (factory default), the device will power up into 3-Byte Address Mode, the Extended Address Register must be used to access memory regions beyond 128Mb. When ADP=1, the device will power up into 4-Byte Address Mode directly.
7.1.7 Write Protect Selection (WPS) Volatile/Non-Volatile Writable
The WPS bit is used to select which Write Protect scheme should be used. When WPS=0, the device will use the combination of CMP, TB, BP[3:0] bits to protect a specific area of the memory array. When WPS=1, the device will utilize the Individual Block Locks to protect any individual sector or blocks. The default value for all Individual Block Lock bits is 1 upon device power on or after reset.
- 18 -
Publication Release Date: October 23, 2018 Revision I
W25Q256JV
7.1.8 Output Driver Strength (DRV1, DRV0) Volatile/Non-Volatile Writable
The DRV1 & DRV0 bits are used to determine the output driver strength for the Read operations.
DRV1, DRV0
Driver Strength
0, 0
100%
0, 1
75%
1, 0
50%
1, 1
25% (default setting)
7.1.9 Reserved Bits Non Functional
There are a few reserved Status Register bits that may be read out as a "0" or "1". It is recommended to ignore the values of those bits. During a "Write Status Register" instruction, the Reserved Bits can be written as "0", but there will not be any effects.
- 19 -
W25Q256JV
7.1.10 W25Q256JV Status Register Memory Protection (WPS = 0, CMP = 0)
STATUS REGISTER(1) TB BP3 BP2 BP1 BP0
X
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
1
1
1
0
1
0
0
0
0
1
0
0
1
W25Q256JV (256M-BIT / 32M-BYTE) MEMORY PROTECTION(2)
PROTECTED BLOCK(S)
PROTECTED ADDRESSES
PROTECTED DENSITY
PROTECTED PORTION
NONE
NONE
NONE
NONE
511
01FF0000h - 01FFFFFFh
64KB
Upper 1/512
510 thru 511
01FE0000h - 01FFFFFFh
128KB
Upper 1/256
508 thru 511
01FC0000h - 01FFFFFFh
256KB
Upper 1/128
504 thru 511
01F80000h - 01FFFFFFh
512KB
Upper 1/64
496 thru 511
01F00000h - 01FFFFFFh
1MB
Upper 1/32
480 thru 511
01E00000h - 01FFFFFFh
2MB
Upper 1/16
448 thru 511
01C00000h - 01FFFFFFh
4MB
Upper 1/8
384 thru 511
01800000h - 01FFFFFFh
8MB
Upper 1/4
256 thru 511
01000000h - 01FFFFFFh
16MB
Upper 1/2
1
0
0
0
1
1
0
0
1
0
1
0
0
1
1
1
0
1
0
0
1
0
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
0
0
0
1
1
0
0
1
X
1
1
0
X
X
1
X
1
X
0 0 thru 1 0 thru 3 0 thru 7 0 thru 15 0 thru 31 0 thru 63 0 thru 127 0 thru 255 0 thru 511 0 thru 511
00000000h - 0000FFFFh 00000000h - 0001FFFFh 00000000h - 0003FFFFh 00000000h - 0007FFFFh 00000000h - 000FFFFFh 00000000h - 001FFFFFh 00000000h - 003FFFFFh 00000000h - 007FFFFFh 00000000h - 00FFFFFFh 00000000h - 01FFFFFFh 00000000h - 01FFFFFFh
64KB 128KB 256KB 512KB 1MB 2MB 4MB 8MB 16MB 32MB 32MB
Lower 1/512 Lower 1/256 Lower 1/128 Lower 1/64 Lower 1/32 Lower 1/16
Lower 1/8 Lower 1/4 Lower 1/2
ALL ALL
Notes: 1. X = don't care 2. If any Erase or Program command specifies a memory region that contains protected data portion, this command will be ignored.
- 20 -
Publication Release Date: October 23, 2018 Revision I
W25Q256JV
7.1.11 W25Q256JV Status Register Memory Protection (WPS = 0, CMP = 1)
STATUS REGISTER(1) TB BP3 BP2 BP1 BP0
X
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
1
1
1
0
1
0
0
0
0
1
0
0
1
W25Q256JV (256M-BIT / 32M-BYTE) MEMORY PROTECTION(2)
PROTECTED BLOCK(S)
PROTECTED ADDRESSES
PROTECTED DENSITY
PROTECTED PORTION
ALL
00000000h - 01FFFFFFh
ALL
ALL
0 thru 510
00000000h - 01FEFFFFh
32,704KB
Lower 511/512
0 thru 509
00000000h - 01FDFFFFh
32,640KB
Lower 255/256
0 thru 507
00000000h - 01FBFFFFh
32,512KB
Lower 127/128
0 thru 503
00000000h - 01F7FFFFh
32,256KB
Lower 63/64
0 thru 495
00000000h - 01EFFFFFh
31MB
Lower 31/32
0 thru 479
00000000h - 01DFFFFFh
30MB
Lower 15/16
0 thru 447
00000000h - 01BFFFFFh
28MB
Lower 7/8
0 thru 383
00000000h - 017FFFFFh
24MB
Lower 3/4
0 thru 255
00000000h - 00FFFFFFh
16MB
Lower 1/2
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
X
1
X
1
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
0
0
0
0
0
1
1
0
X
X
1
X
1 thru 511 2 thru 511 4 thru 511 8 thru 511 16 thru 511 32 thru 511 64 thru 511 128 thru 511 256 thru 511
NONE NONE
00010000h - 01FFFFFFh 00020000h - 01FFFFFFh 00040000h - 01FFFFFFh 00080000h - 01FFFFFFh 00100000h - 01FFFFFFh 00200000h - 01FFFFFFh 00400000h - 01FFFFFFh 00800000h - 01FFFFFFh 01000000h - 01FFFFFFh
NONE NONE
32,704KB 32,640KB 32,512KB 32,256KB
31MB 30MB 28MB 24MB 16MB NONE NONE
Upper 511/512 Upper 255/256 Upper 127/128
Upper 63/64 Upper 31/32 Upper 15/16
Upper 7/8 Upper 3/4 Upper 1/2
NONE NONE
Notes: 1. X = don't care 2. If any Erase or Program command specifies a memory region that contains protected data portion, this command will be ignored.
- 21 -
W25Q256JV
7.1.12 W25Q256JV Individual Block Memory Protection (WPS=1)
Sector 15 (4KB) Sector 14 (4KB)
Block 511 (64KB)
Sector 1 (4KB) Sector 0 (4KB)
Block 510 (64KB)
Block 1 (64KB)
Sector 15 (4KB) Sector 14 (4KB)
Individual Block Locks: 32 Sectors (Top/Bottom)
510 Blocks
Individual Block Lock: 36h + Address
Individual Block Unlock: 39h + Address
Read Block Lock: 3Dh + Address
Global Block Lock: 7Eh
Global Block Unlock: 98h
Block 0 (64KB)
Sector 1 (4KB) Sector 0 (4KB)
Figure 4d. Individual Block/Sector Locks
Notes: 1. Individual Block/Sector protection is only valid when WPS=1. 2. All individual block/sector lock bits are set to 1 by default after power up, all memory array is protected.
- 22 -
Publication Release Date: October 23, 2018 Revision I
W25Q256JV
7.2 Extended Address Register Volatile Writable Only
In addition to the Status Registers, W25Q256JV provides a volatile Extended Address Register which consists of the 4th byte of memory address. The Extended Address Register is used only when the device is operating in the 3-Byte Address Mode (ADS=0). The lower 128Mb memory array (00000000h 00FFFFFFh) is selected when A24=0, all instructions with 3-Byte addresses will be executed within that region. When A24=1, the upper 128Mb memory array (01000000h 01FFFFFFh) will be selected.
If the device powers up with ADP bit set to 1, or an "Enter 4-Byte Address Mode (B7h)" instruction is issued, the device will require 4-Byte address input for all address related instructions, and the Extended Address Register setting will be ignored. However, any command with 4-byte address input will replace the Extended Address Register Bits (A31-A24) with new settings.
Upon power up or after the execution of a Software/Hardware Reset, the Extended Address Register values will be cleared to 0.
Reserved for higher densities
512Mb ~ 32Gb (Volatile Writable Only)
Address Bit #24 A24=0: Select lower 128Mb A24=1: Select upper 128Mb
(Volatile Writable Only)
EA7 EA6 EA5 EA4 EA3 EA2 EA1 EA0 A31 A30 A29 A28 A27 A26 A25 A24
Figure 4e. Extended Address Register
- 23 -
W25Q256JV
8. INSTRUCTIONS
The Standard/Dual/Quad SPI instruction set of the W25Q256JV consists of 48 basic instructions that are fully controlled through the SPI bus (see Instruction Set Table1-4). Instructions are initiated with the falling edge of Chip Select (/CS). The first byte of data clocked into the DI input provides the instruction code. Data on the DI input is sampled on the rising edge of clock with most significant bit (MSB) first.
Instructions vary in length from a single byte to several bytes and may be followed by address bytes, data bytes, dummy bytes (don't care), and in some cases, a combination. Instructions are completed with the rising edge of edge /CS. Clock relative timing diagrams for each instruction are included in Figures 5 through 57. All read instructions can be completed after any clocked bit. However, all instructions that Write, Program or Erase must complete on a byte boundary (/CS driven high after a full 8-bits have been clocked) otherwise the instruction will be ignored. This feature further protects the device from inadvertent writes. Additionally, while the memory is being programmed or erased, or when the Status Register is being written, all instructions except for Read Status Register will be ignored until the program or erase cycle has completed.
8.1 Device ID and Instruction Set Tables 8.1.1 Manufacturer and Device Identification
MANUFACTURER ID Winbond Serial Flash
(MF7 - MF0) EFh
Device ID Instruction W25Q256JV-IQ/JQ W25Q256JV-IM*/JM*
(ID7 - ID0) ABh, 90h, 92h, 94h 18h 18h
(ID15 - ID0) 9Fh 4019h 7019h
Note: For DTR, QPI supporting, please refer to W25Q256JV DTR datasheet.
- 24 -
Publication Release Date: October 23, 2018 Revision I
W25Q256JV
8.1.2 Instruction Set Table 1 (Standard/Dual/Quad SPI, 3-Byte Address Mode)(1)
Data Input Output
Byte 1
Byte 2
Number of Clock(1-1-1) Write Enable Volatile SR Write Enable Write Disable
8
8
06h
50h
04h
Release Power-down / ID Manufacturer/Device ID JEDEC ID Read Unique ID
ABh 90h 9Fh 4Bh
Dummy Dummy (MF7-MF0) Dummy
Read Data Read Data with 4-Byte Address
03h
A23-A16
13h
A31-A24
Fast Read Fast Read with 4-Byte Address
0Bh
A23-A16
0Ch
A31-A24
Page Program Page Program with 4-Byte Address
02h
A23-A16
12h
A31-A24
Sector Erase (4KB)
20h
Sector Erase (4KB) with 4-Byte Address 21h
Block Erase (32KB)
52h
Block Erase (64KB)
D8h
Block Erase (64KB) with 4-Byte Address DCh
Chip Erase
C7h/60h
Read Status Register-1
05h
Write Status Register-1(4)
01h
Read Status Register-2
35h
Write Status Register-2
31h
Read Status Register-3
15h
Write Status Register-3
11h
Read Extended Addr. Reg.
C8h
Write Extended Addr. Reg.
C5h
A23-A16 A31-A24 A23-A16 A23-A16 A31-A24
(S7-S0)(2) (S7-S0)(4) (S15-S8)(2) (S15-S8) (S23-S16)(2) (S23-S16) (EA7-EA0)(2) (EA7-EA0)
Read SFDP Register Erase Security Register(5) Program Security Register(5) Read Security Register(5)
5Ah
A23-A16
44h
A23-A16
42h
A23-A16
48h
A23-A16
Global Block Lock Global Block Unlock Read Block Lock Individual Block Lock Individual Block Unlock
7Eh
98h
3Dh
A23-A16
36h
A23-A16
39h
A23-A16
Erase / Program Suspend
75h
Erase / Program Resume
7Ah
Power-down
B9h
Enter 4-Byte Address Mode
B7h
Exit 4-Byte Address Mode
E9h
Enable Reset
66h
Reset Device
99h
Byte 3 8
Dummy Dummy (ID15-ID8) Dummy A15-A8 A23-A16 A15-A8 A23-A16 A15-A8 A23-A16 A15-A8 A23-A16 A15-A8 A15-A8 A23-A16
A15-A8 A15-A8 A15-A8 A15-A8
A15-A8 A15-A8 A15-A8
Byte 4 8
Dummy 00h
(ID7-ID0) Dummy A7-A0 A15-A8 A7-A0 A15-A8 A7-A0 A15-A8 A7-A0 A15-A8 A7-A0 A7-A0 A15-A8
A7-A0 A7-A0 A7-A0 A7-A0
A7-A0 A7-A0 A7-A0
Byte 5 8
Byte 6 8
(ID7-ID0)(2) (MF7-MF0)
(ID7-ID0)
Dummy (D7-D0) A7-A0 Dummy A7-A0 D7-D0 A7-A0
(UID63-0)
(D7-D0) (D7-D0) Dummy D7-D0(3) D7-D0
A7-A0
A7-A0
Dummy
D7-D0 Dummy
(D7-D0)
D7-D0(3) (D7-D0)
(L7-L0)
Byte 7 8
(D7-D0) D7-D0(3)
- 25 -
W25Q256JV
8.1.3 Instruction Set Table 2 (Dual/Quad SPI Instructions,3-Byte Address Mode)
Data Input Output
Number of Clock(1-1-2)
Fast Read Dual Output Fast Read Dual Output with 4-Byte Address Number of Clock(1-2-2)
Mftr./Device ID Dual I/O
Fast Read Dual I/O Fast Read Dual I/O with 4-Byte Address Number of Clock(1-1-4) Quad Input Page Program Quad Page Program with 4-Byte Address Fast Read Quad Output
Number of Clock(1-1-4)
Fast Read Quad Output with 4-Byte Address
Number of Clock(1-4-4)
Mftr./Device ID Quad I/O
Fast Read Quad I/O Fast Read Quad I/O with 4-Byte Address Set Burst with Wrap
Byte 1 8
3Bh
Byte 2 8
A23-A16
Byte 3 8
A15-A8
Byte 4 8
A7-A0
Byte 5 8
Dummy
Byte 6 4
(D7-D0)(7)
Byte 7 4 ...
3Ch A31-A24 A23-A16 A15-A8
A7-A0
Dummy
Dummy
8 92h BBh BCh
4 A23-A16 A23-A16
4 A15-A8 A15-A8
A31-A24 A23-A16
4 0 A7-A0 A15-A8
4 Dummy(11) Dummy(11)
A7-A0
4 (MF7-MF0)
(D7-D0) Dummy(11)
4 (ID7-ID0)
... (D7-D0)
8
8
8
8
2
2
2
32h
A23-A16 A15-A8
A7-A0
(D7-D0)(9)
(D7-D0)(3)
...
34h A31-A24 A23-A16 A15-A8
6Bh A23-A16 A15-A8
8
8
8
A7-A0 8
A7-A0 Dummy
8
D7-D0 Dummy
2
... Dummy
2
6Ch A31-A24 A23-A16 A15-A8
A7-A0
Dummy
Dummy
8 94h EBh ECh
2 A23-A16 A23-A16
2 A15-A8 A15-A8
A31-A24 A23-A16
2 0 A7-A0 A15-A8
2 Dummy(11) Dummy(11)
A7-A0f
2 Dummy Dummy Dummy(11)
2 Dummy Dummy Dummy
77h
Dummy Dummy Dummy
W7-W0
Byte 8 4
Byte 9 4
(D7-D0)(7)
...
4
4
...
2
2
... Dummy
2
(D7-D0)(9) 2
Dummy
Dummy
2 (MF7-MF0)
(D7-D0) Dummy
2 (ID7-ID0)
... (D7-D0)
Byte 10 4
4
2
... 2 (D7-D0)(9) 2
...
- 26 -
Publication Release Date: October 23, 2018 Revision I
W25Q256JV
8.1.4 Instruction Set Table 3 (Standard SPI, 4-Byte Address Mode)(1)
Data Input Output
Byte 1
Number of Clock(1-1-1)
8
Write Enable
06h
Volatile SR Write Enable
50h
Write Disable
04h
Release Power-down / ID Manufacturer/Device ID JEDEC ID Read Unique ID
ABh 90h 9Fh 4Bh
Read Data
03h
Read Data with 4-Byte Address
13h
Fast Read
0Bh
Fast Read with 4-Byte Address
0Ch
Page Program
02h
Page Program with 4-Byte Address
12h
Sector Erase (4KB) Sector Erase (4KB) with 4-Byte Address Block Erase (32KB) Block Erase (64KB) Block Erase (64KB) with 4-Byte Address Chip Erase
20h 21h 52h D8h DCh C7h/60h
Read Status Register-1
05h
Write Status Register-1(4)
01h
Read Status Register-2
35h
Write Status Register-2
31h
Read Status Register-3
15h
Write Status Register-3
11h
Read Extended Addr. Reg.
C8h
Write Extended Addr. Reg.
C5h
Read SFDP Register
5Ah
Erase Security Register(5)
44h
Program Security Register(5)
42h
Read Security Register(5)
48h
Global Block Lock
7Eh
Global Block Unlock
98h
Read Block Lock
3Dh
Individual Block Lock
36h
Individual Block Unlock
39h
Erase / Program Suspend
75h
Erase / Program Resume
7Ah
Power-down
B9h
Enter 4-Byte Address Mode
B7h
Exit 4-Byte Address Mode
E9h
Enable Reset
66h
Reset Device
99h
Byte 2 8
Dummy Dummy (MF7-MF0) Dummy A31-A24 A31-A24 A31-A24 A31-A24 A31-A24 A31-A24 A31-A24 A31-A24 A31-A24 A31-A24 A31-A24
(S7-S0)(2) (S7-S0)(4) (S15-S8)(2) (S15-S8) (S23-S16)(2) (S23-S16) (EA7-EA0)(2) (EA7-EA0) A23-A16 A31-A24 A31-A24 A31-A24
A31-A24 A31-A24 A31-A24
Byte 3 8
Dummy Dummy (ID15-ID8) Dummy A23-A16 A23-A16 A23-A16 A23-A16 A23-A16 A23-A16 A23-A16 A23-A16 A23-A16 A23-A16 A23-A16
A15-A8 A23-A16 A23-A16 A23-A16
A23-A16 A23-A16 A23-A16
Byte 4 8
Dummy 00h
(ID7-ID0) Dummy A15-A8 A15-A8 A15-A8 A15-A8 A15-A8 A15-A8 A15-A8 A15-A8 A15-A8 A15-A8 A15-A8
A7-A0 A15-A8 A15-A8 A15-A8
A15-A8 A15-A8 A15-A8
Byte 5 8
(ID7-ID0)(2) (MF7-MF0)
Dummy A7-A0 A7-A0 A7-A0 A7-A0 A7-A0 A7-A0 A7-A0 A7-A0 A7-A0 A7-A0 A7-A0
Dummy A7-A0 A7-A0 A7-A0
A7-A0 A7-A0 A7-A0
Byte 6 8
Byte 7 8
(ID7-ID0)
Dummy (D7-D0) (D7-D0) Dummy Dummy D7-D0 D7-D0
(UID63-0)
(D7-D0) (D7-D0) D7-D0(3) D7-D0(3)
(D7-D0)
D7-D0 Dummy
D7-D0(3) (D7-D0)
(L7-L0)
- 27 -
W25Q256JV
8.1.5 Instruction Set Table 4 (Dual/Quad SPI Instructions, 4-Byte Address Mode)
Data Input Output Number of Clock(1-1-2) Fast Read Dual Output Fast Read Dual Output with 4-Byte Address
Number of Clock(1-2-2)
Mftr./Device ID Dual I/O Fast Read Dual I/O Fast Read Dual I/O with 4-Byte Address
Number of Clock(1-1-4)
Quad Input Page Program Quad Page Program with 4-Byte Address Fast Read Quad Output Fast Read Quad Output with 4-Byte Address
Number of Clock(1-4-4)
Mftr./Device ID Quad I/O Fast Read Quad I/O Fast Read Quad I/O with 4-Byte Address Set Burst with Wrap
Byte 1 8
3Bh
Byte 2 8
A31-A24
3Ch A31-A24
8 92h BBh
4 A31-A24 A31-A24
BCh A31-A24
8
8
32h
A31-A24
34h
A31-A24
6Bh A31-A24
6Ch A31-A24
8 94h EBh
2 A31-A24 A31-A24
ECh 77h
A31-A24 Dummy
Byte 3 8
A23-A16
A23-A16 4
A23-A16 A23-A16
A23-A16 8
A23-A16
A23-A16 A23-A16
A23-A16 2
A23-A16 A23-A16
A23-A16 Dummy
Byte 4 8
A15-A8
A15-A8 4
A15-A8 A15-A8
A15-A8 8
A15-A8
A15-A8 A15-A8
A15-A8 2
A15-A8 A15-A8
A15-A8 Dummy
Byte 5 8
A7-A0
Byte 6 8
Dummy
Byte 7 4
(D7-D0,...)(7)
Byte 8 4
Byte9
A7-A0
Dummy (D7-D0,...)(7)
4 00 A7-A0
4
4
Dummy(11) Dummy(11)
(MF7-MF0) (D7-D0)
4 (ID7-ID0)
A7-A0
Dummy(11) (D7-D0)
8
4
4
4
A7-A0
(D7-D0)(9) (D7-D0)(3)..
A7-A0 A7-A0 A7-A0
D7-D0 Dummy Dummy
D7-D0 Dummy Dummy
D7-D0 (D7-D0)(9) (D7-D0)(9)
D7-D0
2 00 A7-A0
2 Dummy(11) Dummy(11)
4 Dummy Dummy
2 (MF7-MF0)
(D7-D0)
2 (ID7-ID0)
A7-A0 Dummy
Dummy(11) W7-W0
Dummy
(D7-D0)
- 28 -
Publication Release Date: October 23, 2018 Revision I
W25Q256JV
Notes:
1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis "( )" indicate data output from the device on either 1, 2 or 4 IO pins.
2. The Status Register contents and Device ID will repeat continuously until /CS terminates the instruction.
3. At least one byte of data input is required for Page Program, Quad Page Program and Program Security Registers, up to 256 bytes of data input. If more than 256 bytes of data are sent to the device, the addressing will wrap to the beginning of the page and overwrite previously sent data.
4. Write Status Register-1 (01h) can also be used to program Status Register-1&2, see section 8.2.5.
5. Security Register Address: Security Register 1: A23-16 = 00h; A15-8 = 10h; A7-0 = byte address Security Register 2: A23-16 = 00h; A15-8 = 20h; A7-0 = byte address Security Register 3: A23-16 = 00h; A15-8 = 30h; A7-0 = byte address
6. Dual SPI address input format: IO0 = A22, A20, A18, A16, A14, A12, A10, A8 A6, A4, A2, A0, M6, M4, M2, M0 IO1 = A23, A21, A19, A17, A15, A13, A11, A9 A7, A5, A3, A1, M7, M5, M3, M1
7. Dual SPI data output format: IO0 = (D6, D4, D2, D0) IO1 = (D7, D5, D3, D1)
8. Quad SPI address input format: IO0 = A20, A16, A12, A8, A4, A0, M4, M0 IO1 = A21, A17, A13, A9, A5, A1, M5, M1 IO2 = A22, A18, A14, A10, A6, A2, M6, M2 IO3 = A23, A19, A15, A11, A7, A3, M7, M3
Set Burst with Wrap input format: IO0 = x, x, x, x, x, x, W4, x IO1 = x, x, x, x, x, x, W5, x IO2 = x, x, x, x, x, x, W6, x IO3 = x, x, x, x, x, x, x, x
9. Quad SPI data input/output format: IO0 = (D4, D0, .....) IO1 = (D5, D1, .....) IO2 = (D6, D2, .....) IO3 = (D7, D3, .....)
10. Fast Read Quad I/O data output format: IO0 = (x, x, x, x, D4, D0, D4, D0) IO1 = (x, x, x, x, D5, D1, D5, D1) IO2 = (x, x, x, x, D6, D2, D6, D2) IO3 = (x, x, x, x, D7, D3, D7, D3)
11. The first dummy is M7-M0 should be set to Fxh
- 29 -
W25Q256JV
8.2 Instruction Descriptions
8.2.1 Write Enable (06h) The Write Enable instruction (Figure 5) sets the Write Enable Latch (WEL) bit in the Status Register to a 1. The WEL bit must be set prior to every Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register and Erase/Program Security Registers instruction. The Write Enable instruction is entered by driving /CS low, shifting the instruction code "06h" into the Data Input (DI) pin on the rising edge of CLK, and then driving /CS high.
/CS CLK
Mode 3 Mode 0
DI (IO0)
DO (IO1)
0 1 2 3 4 5 6 7 Mode 3 Mode 0
Instruction (06h)
High Impedance
Figure 5. Write Enable Instruction
8.2.2 Write Enable for Volatile Status Register (50h) The non-volatile Status Register bits described in section 7.1 can also be written to as volatile bits. This gives more flexibility to change the system configuration and memory protection schemes quickly without waiting for the typical non-volatile bit write cycles or affecting the endurance of the Status Register nonvolatile bits. To write the volatile values into the Status Register bits, the Write Enable for Volatile Status Register (50h) instruction must be issued prior to a Write Status Register (01h) instruction. Write Enable for Volatile Status Register instruction (Figure 6) will not set the Write Enable Latch (WEL) bit, it is only valid for the Write Status Register instruction to change the volatile Status Register bit values.
/CS CLK
Mode 3 Mode 0
DI (IO0)
DO (IO1)
0 1 2 3 4 5 6 7 Mode 3 Mode 0
Instruction (50h)
High Impedance
Figure 6. Write Enable for Volatile Status Register Instruction
- 30 -
Publication Release Date: October 23, 2018 Revision I
W25Q256JV
8.2.3 Write Disable (04h)
The Write Disable instruction (Figure 7) resets the Write Enable Latch (WEL) bit in the Status Register to a 0. The Write Disable instruction is entered by driving /CS low, shifting the instruction code "04h" into the DI pin and then driving /CS high. Note that the WEL bit is automatically reset after Power-up and upon completion of the Write Status Register, Erase/Program Security Registers, Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase and Reset instructions.
/CS CLK
Mode 3 Mode 0
DI (IO0)
01234567 Instruction (04h)
DO (IO1)
High Impedance
Figure 7. Write Disable Instruction for SPI Mode
Mode 3 Mode 0
8.2.4 Read Status Register-1 (05h), Status Register-2 (35h) & Status Register-3 (15h)
The Read Status Register instructions allow the 8-bit Status Registers to be read. The instruction is entered by driving /CS low and shifting the instruction code "05h" for Status Register-1, "35h" for Status Register-2 or "15h" for Status Register-3 into the DI pin on the rising edge of CLK. The status register bits are then shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first as shown in Figure 8. Refer to section 7.1 for Status Register descriptions.
The Read Status Register instruction may be used at any time, even while a Program, Erase or Write Status Register cycle is in progress. This allows the BUSY status bit to be checked to determine when the cycle is complete and if the device can accept another instruction. The Status Register can be read continuously, as shown in Figure 8. The instruction is completed by driving /CS high.
/CS
CLK
DI (IO0)
DO (IO1)
Mode 3 Mode 0
0123456 Instruction (05h/35h/15h)
* = MSB
High Impedance
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Status Register-1/2/3 out
Status Register-1/2/3 out
76543210765432107
*
*
Figure 8. Read Status Register Instruction
- 31 -
W25Q256JV
8.2.5 Write Status Register-1 (01h), Status Register-2 (31h) & Status Register-3 (11h)
The Write Status Register instruction allows the Status Registers to be written. The writable Status Register bits include: TB, BP[3:0] in Status Register-1; CMP, LB[3:1], QE, SRL in Status Register-2;, DRV1, DRV0, WPS & ADP in Status Register-3. All other Status Register bit locations are read-only and will not be affected by the Write Status Register instruction. LB[3:1] are non-volatile OTP bits, once it is set to 1, it cannot be cleared to 0.
To write non-volatile Status Register bits, a standard Write Enable (06h) instruction must previously have been executed for the device to accept the Write Status Register instruction (Status Register bit WEL must equal 1). Once write enabled, the instruction is entered by driving /CS low, sending the instruction code "01h/31h/11h", and then writing the status register data byte as illustrated in Figure 9a.
To write volatile Status Register bits, a Write Enable for Volatile Status Register (50h) instruction must have been executed prior to the Write Status Register instruction (Status Register bit WEL remains 0). However, SRL and LB[3:1] cannot be changed from "1" to "0" because of the OTP protection for these bits. Upon power off or the execution of a Software/Hardware Reset, the volatile Status Register bit values will be lost, and the non-volatile Status Register bit values will be restored.
During non-volatile Status Register write operation (06h combined with 01h/31h/11h), after /CS is driven high, the self-timed Write Status Register cycle will commence for a time duration of tW (See AC Characteristics). While the Write Status Register cycle is in progress, the Read Status Register instruction may still be accessed to check the status of the BUSY bit. The BUSY bit is a 1 during the Write Status Register cycle and a 0 when the cycle is finished and ready to accept other instructions again. After the Write Status Register cycle has finished, the Write Enable Latch (WEL) bit in the Status Register will be cleared to 0.
During volatile Status Register write operation (50h combined with 01h/31h/11h), after /CS is driven high, the Status Register bits will be refreshed to the new values within the time period of tSHSL2 (See AC Characteristics). BUSY bit will remain 0 during the Status Register bit refresh period.
Refer to section 7.1 for Status Register descriptions.
/CS
Mode 3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Mode 3
CLK Mode 0
Mode 0
DI (IO0)
Instruction (01h/31h/11h)
Register-1/2/3 in
76543210
*
DO (IO1)
* = MSB
High Impedance
Figure 9a. Write Status Register-1/2/3 Instruction
- 32 -
Publication Release Date: October 23, 2018 Revision I
W25Q256JV
The W25Q256JV is also backward compatible to Winbond's previous generations of serial flash memories, in which the Status Register-1&2 can be written using a single "Write Status Register-1 (01h)" command. To complete the Write Status Register-1&2 instruction, the /CS pin must be driven high after the sixteenth bit of data that is clocked in as shown in Figure 9b. If /CS is driven high after the eighth clock, the Write Status Register-1 (01h) instruction will only program the Status Register-1, the Status Register-2 will not be affected (Previous generations will clear CMP and QE bits).
/CS
CLK
Mode 3 Mode 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Mode 3 Mode 0
DI (IO0)
DO (IO1)
* = MSB
Instruction (01h)
Status Register 1 in
Status Register 2 in
7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8
*
*
High Impedance
Figure 9b. Write Status Register-1/2 Instruction
- 33 -
W25Q256JV
8.2.6 Read Extended Address Register (C8h) When the device is in the 3-Byte Address Mode, the Extended Address Register is used as the 4th address byte A[31:24] to access memory regions beyond 128Mb. The Read Extended Address Register instruction is entered by driving /CS low and shifting the instruction code "C8h" into the DI pin on the rising edge of CLK. The Extended Address Register bits are then shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first as shown in Figure 10.
When the device is in the 4-Byte Address Mode, the Extended Address Register is not used.
/CS
CLK
Mode 3 Mode 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
DI (IO0)
DO (IO1)
* = MSB
Instruction (C8h) High Impedance
Extended Addr. Reg. Out
Extended Addr. Reg. Out
76543210765432107
*
*
Figure 10a. Read Extended Address Register Instruction
- 34 -
Publication Release Date: October 23, 2018 Revision I
W25Q256JV
8.2.7 Write Extended Address Register (C5h) The Extended Address Register is a volatile register that stores the 4th byte address (A31-A24) when the device is operating in the 3-Byte Address Mode (ADS=0). To write the Extended Address Register bits, a Write Enable (06h) instruction must previously have been executed for the device to accept the Write Extended Address Register instruction (Status Register bit WEL must equal 1). Once write enabled, the instruction is entered by driving /CS low, sending the instruction code "C5h", and then writing the Extended Address Register data byte as illustrated in Figure 11.
Upon power up or the execution of a Software/Hardware Reset, the Extended Address Register bit values will be cleared to 0.
The Extended Address Register is only effective when the device is in the 3-Byte Address Mode. When the device operates in the 4-Byte Address Mode (ADS=1), any command with address input of A31-A24 will replace the Extended Address Register values. It is recommended to check and update the Extended Address Register if necessary when the device is switched from 4-Byte to 3-Byte Address Mode.
/CS
CLK
DI (IO0)
DO (IO1)
Mode 3
0
Mode 0
* = MSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Instruction (C5h)
Ext. Add. Reg in
76543210
*
High Impedance
Mode 3 Mode 0
Figure 11. Write Extended Address Register Instruction
- 35 -
W25Q256JV
8.2.8 Enter 4-Byte Address Mode (B7h) The Enter 4-Byte Address Mode instruction (Figure 12) will allow 32-bit address (A31-A0) to be used to access the memory array beyond 128Mb. The Enter 4-Byte Address Mode instruction is entered by driving /CS low, shifting the instruction code "B7h" into the DI pin and then driving /CS high.
/CS CLK
Mode 3 Mode 0
DI (IO0)
DO (IO1)
01234567
Mode 3 Mode 0
Instruction (B7h)
High Impedance
Figure 12. Enter 4-Byte Address Mode instruction
8.2.9 Exit 4-Byte Address Mode (E9h)
In order to be backward compatible, the Exit 4-Byte Address Mode instruction (Figure 13) will only allow 24-bit address (A23-A0) to be used to access the memory array up to 128Mb. The Extended Address Register must be used to access the memory array beyond 128Mb. The Exit 4-Byte Address Mode instruction is entered by driving /CS low, shifting the instruction code "E9h" into the DI pin and then driving /CS high.
/CS CLK
Mode 3 Mode 0
DI (IO0)
DO (IO1)
0 1 2 3 4 5 6 7 Mode 3 Mode 0
Instruction (E9h)
High Impedance
Figure 13. Exit 4-Byte Address Mode instruction
- 36 -
Publication Release Date: October 23, 2018 Revision I
W25Q256JV
8.2.10 Read Data (03h) The Read Data instruction allows one or more data bytes to be sequentially read from the memory. The instruction is initiated by driving the /CS pin low and then shifting the instruction code "03h" followed by a 32/24-bit address (A31/A23-A0) into the DI pin. The code and address bits are latched on the rising edge of the CLK pin. After the address is received, the data byte of the addressed memory location will be shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first. The address is automatically incremented to the next higher address after each byte of data is shifted out allowing for a continuous stream of data. This means that the entire memory can be accessed with a single instruction as long as the clock continues. The instruction is completed by driving /CS high.
The Read Data instruction sequence is shown in Figure 14. If a Read Data instruction is issued while an Erase, Program or Write cycle is in process (BUSY=1) the instruction is ignored and will not have any effects on the current cycle. The Read Data instruction allows clock rates from D.C. to a maximum of fR (see AC Electrical Characteristics).
The Read Data (03h) instruction is only supported in Standard SPI mode.
/CS
CLK
DI (IO0) DO (IO1)
Mode 3
0
Mode 0
* = MSB
1 2 3 4 5 6 7 8 9 10
28 29 30 31 32 33 34 35 36 37 38 39
Instruction (03h)
24-Bit Address
23 22 21
*
High Impedance
3210
Data Out 1 765432107
*
Figure 14. Read Data Instruction 32-Bit Address is required when the device is operating in 4-Byte Address Mode
- 37 -
W25Q256JV
8.2.11 Read Data with 4-Byte Address (13h) The Read Data with 4-Byte Address instruction is similar to the Read Data (03h) instruction. Instead of 24bit address, 32-bit address is needed following the instruction code 13h. No matter the device is operating in 3-Byte Address Mode or 4-byte Address Mode, the Read Data with 4-Byte Address instruction will always require 32-bit address to access the entire 256Mb memory.
The Read Data with 4-Byte Address instruction sequence is shown in Figure 15. If this instruction is issued while an Erase, Program or Write cycle is in process (BUSY=1) the instruction is ignored and will not have any effects on the current cycle. The Read Data with 4-Byte Address instruction allows clock rates from D.C. to a maximum of fR (see AC Electrical Characteristics).
The Read Data with 4-Byte Address (13h) instruction is only supported in Standard SPI mode.
/CS
CLK
DI (IO0)
DO (IO1)
Mode 3
0
Mode 0
* = MSB
1 2 3 4 5 6 7 8 9 10
36 37 38 39 40 41 42 43 44 45 46 47
Instruction (13h)
32-Bit Address
31 30 29
*
High Impedance
3210
Data Out 1 765432107
*
Figure 15. Read Data with 4-Byte Address Instruction
- 38 -
Publication Release Date: October 23, 2018 Revision I
W25Q256JV
8.2.12 Fast Read (0Bh) The Fast Read instruction is similar to the Read Data instruction except that it can operate at the highest possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight "dummy" clocks after the 24/32-bit address as shown in Figure 16. The dummy clocks allow the devices internal circuits additional time for setting up the initial address. During the dummy clocks the data value on the DO pin is a "don't care".
/CS
CLK
DI (IO0) DO (IO1) /CS
CLK
DI (IO0) DO (IO1)
Mode 3 Mode 0
0 1 2 3 4 5 6 7 8 9 10
28 29 30 31
Instruction (0Bh)
24-Bit Address
23 22 21
*
High Impedance
3210
* = MSB
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Dummy Clocks 0
High Impedance
Data Out 1
Data Out 2
76543210765432107
*
*
Figure 16. Fast Read Instruction 32-Bit Address is required when the device is operating in 4-Byte Address Mode
- 39 -
W25Q256JV
8.2.13 Fast Read with 4-Byte Address (0Ch) The Fast Read with 4-Byte Address instruction is similar to the Fast Read instruction except that it requires 32-bit address instead of 24-bit address. No matter the device is operating in 3-Byte Address Mode or 4-byte Address Mode, the Read Data with 4-Byte Address instruction will always require 32-bit address to access the entire 256Mb memory.
The Fast Read with 4-Byte Address (0Ch) instruction is only supported in Standard SPI mode.
/CS
CLK
DI (IO0) DO (IO1)
/CS
CLK
DI (IO0) DO (IO1)
Mode 3 Mode 0
0 1 2 3 4 5 6 7 8 9 10
36 37 38 39
Instruction (0Ch)
32-Bit Address
31 30 29
*
High Impedance
3210
* = MSB
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
Dummy Clocks 0
High Impedance
Data Out 1
Data Out 2
76543210765432107
*
*
Figure 18. Fast Read with 4-Byte Address Instruction
- 40 -
Publication Release Date: October 23, 2018 Revision I
W25Q256JV
8.2.14 Fast Read Dual Output (3Bh) The Fast Read Dual Output (3Bh) instruction is similar to the standard Fast Read (0Bh) instruction except that data is output on two pins; IO0 and IO1. This allows data to be transferred at twice the rate of standard SPI devices. The Fast Read Dual Output instruction is ideal for quickly downloading code from Flash to RAM upon power-up or for applications that cache code-segments to RAM for execution.
Similar to the Fast Read instruction, the Fast Read Dual Output instruction can operate at the highest possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight "dummy" clocks after the 24/32-bit address as shown in Figure 19. The dummy clocks allow the device's internal circuits additional time for setting up the initial address. The input data during the dummy clocks is "don't care". However, the IO0 pin should be high-impedance prior to the falling edge of the first data out clock.
/CS
CLK
DI (IO0) DO (IO1) /CS
CLK
DI (IO0) DO (IO1)
Mode 3 Mode 0
0 1 2 3 4 5 6 7 8 9 10
28 29 30 31
Instruction (3Bh)
24-Bit Address
23 22 21
*
High Impedance
3210
* = MSB
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Dummy Clocks
IO0 switches from Input to Output
0
64206420642064206
High Impedance
75317531753175317
* Data Out 1
* Data Out 2
* Data Out 3
* Data Out 4
Figure 19. Fast Read Dual Output Instruction 32-Bit Address is required when the device is operating in 4-Byte Address Mode
- 41 -
W25Q256JV
8.2.15 Fast Read Dual Output with 4-Byte Address (3Ch) The Fast Read Dual Output with 4-Byte Address instruction is similar to the Fast Read Dual Output instruction except that it requires 32-bit address instead of 24-bit address. No matter the device is operating in 3-Byte Address Mode or 4-byte Address Mode, the Fast Read Dual Output with 4-Byte Address instruction will always require 32-bit address to access the entire 256Mb memory.
The Fast Read Dual Output with 4-Byte Address (3Ch) instruction is only supported in Standard SPI mode.
/CS
CLK
DI (IO0) DO (IO1) /CS
CLK
DI (IO0)
Mode 3 Mode 0
0 1 2 3 4 5 6 7 8 9 10
36 37 38 39
Instruction (3Ch)
32-Bit Address
31 30 29
*
High Impedance
3210
* = MSB
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
Dummy Clocks
IO0 switches from Input to Output
0
64206420642064206
DO (IO1)
High Impedance
75317531753175317
* Data Out 1
* Data Out 2
* Data Out 3
* Data Out 4
Figure 20. Fast Read Dual Output with 4-Byte Address Instruction
- 42 -
Publication Release Date: October 23, 2018 Revision I
W25Q256JV
8.2.16 Fast Read Quad Output (6Bh)
The Fast Read Quad Output (6Bh) instruction is similar to the Fast Read Dual Output (3Bh) instruction except that data is output on four pins, IO0, IO1, IO2, and IO3. The Quad Enable (QE) bit in Status Register-2 must be set to 1 before the device will accept the Fast Read Quad Output Instruction. The Fast Read Quad Output Instruction allows data to be transferred at four times the rate of standard SPI devices.
The Fast Read Quad Output instruction can operate at the highest possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight "dummy" clocks after the 24/32-bit address as shown in Figure 21. The dummy clocks allow the device's internal circuits additional time for setting up the initial address. The input data during the dummy clocks is "don't care". However, the IO pins should be high-impedance prior to the falling edge of the first data out clock.
/CS CLK
IO0 IO1 IO2 IO3
/CS CLK
IO0 IO1 IO2 IO3
Mode 3 Mode 0
0 1 2 3 4 5 6 7 8 9 10
28 29 30 31
Instruction (6Bh)
24-Bit Address
23 22 21
* High Impedance
3210
High Impedance
High Impedance
* = MSB
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy Clocks 0
High Impedance High Impedance High Impedance
IO0 switches from Input to Output 404040404
515151515
626262626
737373737 Byte 1 Byte 2 Byte 3 Byte 4
Figure 21. Fast Read Quad Output Instruction 32-Bit Address is required when the device is operating in 4-Byte Address Mode
- 43 -
W25Q256JV
8.2.17 Fast Read Quad Output with 4-Byte Address (6Ch) The Fast Read Quad Output with 4-Byte Address instruction is similar to the Fast Read Quad Output instruction except that it requires 32-bit address instead of 24-bit address. No matter the device is operating in 3-Byte Address Mode or 4-byte Address Mode, the Fast Read Quad Output with 4-Byte Address instruction will always require 32-bit address to access the entire 256Mb memory.
The Fast Read Quad Output with 4-Byte Address (6Ch) instruction is only supported in Standard SPI mode.
/CS CLK
IO0 IO1 IO2 IO3
/CS CLK
IO0 IO1 IO2 IO3
Mode 3 Mode 0
0 1 2 3 4 5 6 7 8 9 10
36 37 38 39
Instruction (6Ch)
32-Bit Address
31 30 29
* High Impedance
3210
High Impedance
High Impedance
* = MSB
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Dummy Clocks 0
High Impedance High Impedance High Impedance
IO0 switches from Input to Output 404040404
515151515
626262626
737373737 Byte 1 Byte 2 Byte 3 Byte 4
Figure 22. Fast Read Quad Output with 4-Byte Address Instruction
- 44 -
Publication Release Date: October 23, 2018 Revision I
W25Q256JV
8.2.18 Fast Read Dual I/O (BBh) The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining two IO pins, IO0 and IO1. It is similar to the Fast Read Dual Output (3Bh) instruction but with the capability to input the Address bits (A23/A31-0) two bits per clock. This reduced instruction overhead may allow for code execution (XIP) directly from the Dual SPI in some applications.
Similar to the Fast Read Dual Output (3Bh) instruction, the Fast Read Dual I/O instruction can operate at the highest possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding four "dummy" clocks after the 24/32-bit address as shown in Figure 23. The dummy clocks allow the device's internal circuits additional time for setting up the initial address. The input data during the dummy clocks is "don't care". However, the IO0 pin should be high-impedance prior to the falling edge of the first data out clock.
/CS CLK
Mode 3 Mode 0
DI (IO0)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Instruction (BBh)
A23-16
A15-8
A7-0
M7-0
22 20 18 16 14 12 10 8 6 4 2 0 6 4 2 0
DO (IO1)
/CS
CLK
DI (IO0)
* = MSB
23 21 19 17 15 13 11 9 7 5 3 1 7 5 3 1
*
*
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
IOs switch from Input to Output 064206420642064206
DO (IO1)
175317531753175317
* Byte 1
* Byte 2
* Byte 3
* Byte 4
Figure 23a. Fast Read Dual I/O (M7-M0 should be set to Fxh) 32-Bit Address is required when the device is operating in 4-Byte Address Mode
- 45 -
W25Q256JV
8.2.19 Fast Read Dual I/O with 4-Byte Address (BCh) The Fast Read Dual I/O with 4-Byte Address instruction is similar to the Fast Read Dual I/O instruction except that it requires 32-bit address instead of 24-bit address. No matter the device is operating in 3-Byte Address Mode or 4-byte Address Mode, the Fast Read Dual I/O with 4-Byte Address instruction will always require 32-bit address to access the entire 256Mb memory.
The Fast Read Dual I/O with 4-Byte Address (BCh) instruction is only supported in Standard SPI mode.
/CS CLK
Mode 3 Mode 0
DI (IO0)
0 1 2 3 4 5 6 7 8 9 10
21 22 23 24 25 26 27
Instruction (BCh)
32-Bit Address
M7-0
30 28 26
4206420
DO (IO1)
/CS
CLK
DI (IO0)
* = MSB
31 29 27
*
5317531
*
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
IOs switch from Input to Output 064206420642064206
DO (IO1)
175317531753175317
* Byte 1
* Byte 2
* Byte 3
* Byte 4
Figure 25a. Fast Read Dual I/O w/ 4-Byte Addr. (M7-M0 shuld set to Fxh, SPI Mode only)
- 46 -
Publication Release Date: October 23, 2018 Revision I
W25Q256JV
8.2.20 Fast Read Quad I/O (EBh) The Fast Read Quad I/O (EBh) instruction is similar to the Fast Read Dual I/O (BBh) instruction except that address and data bits are input and output through four pins IO0, IO1, IO2 and IO3 and four Dummy clocks are required in SPI mode prior to the data output. The Quad I/O dramatically reduces instruction overhead allowing faster random access for code execution (XIP) directly from the Quad SPI. The Quad Enable bit (QE) of Status Register-2 must be set to enable the Fast Read Quad I/O Instruction.
/CS CLK
Mode 3 Mode 0
IO0 IO1 IO2 IO3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Instruction (EBh)
A23-16 A15-8 20 16 12 8
A7-0 40
M7-0 40
Dummy Dummy 4
IOs switch from Input to Output
0404
21 17 13 9 5 1 5 1
51515
22 18 14 10 6 2 6 2
62626
23 19 15 11 7 3 7 3
73 Byte 1
73 Byte 2
7 Byte 3
Figure 26a. Fast Read Quad I/O (M7-M0 should be set to Fxh) 32-Bit Address is required when the device is operating in 4-Byte Address Mode
Fast Read Quad I/O with "8/16/32/64-Byte Wrap Around" in Standard SPI mode
The Fast Read Quad I/O instruction can also be used to access a specific portion within a page by issuing a "Set Burst with Wrap" (77h) command prior to EBh. The "Set Burst with Wrap" (77h) command can either enable or disable the "Wrap Around" feature for the following EBh commands. When "Wrap Around" is enabled, the data being accessed can be limited to either an 8, 16, 32 or 64-byte section of a 256-byte page. The output data starts at the initial address specified in the instruction, once it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around to the beginning boundary automatically until /CS is pulled high to terminate the command.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands.
The "Set Burst with Wrap" instruction allows three "Wrap Bits", W6-4 to be set. The W4 bit is used to enable or disable the "Wrap Around" operation while W6-5 are used to specify the length of the wrap around section within a page. Refer to section 8.2.24 for detail descriptions.
- 47 -
W25Q256JV
8.2.21 Fast Read Quad I/O with 4-Byte Address (ECh) The Fast Read Quad I/O with 4-Byte Address instruction is similar to the Fast Read Dual I/O instruction except that it requires 32-bit address instead of 24-bit address. No matter the device is operating in 3-Byte Address Mode or 4-byte Address Mode, the Fast Read Quad I/O with 4-Byte Address instruction will always require 32-bit address to access the entire 256Mb memory.
The Fast Read Quad I/O with 4-Byte Address (ECh) instruction is only supported in Standard SPI mode.
/CS CLK
Mode 3 Mode 0
IO0 IO1 IO2 IO3
0123456789
14 15 16 17 18 19 20 21 22 23 24 25
Instruction (ECh)
32-Bit Address
M7-0 Dummy Dummy
IOs switch from Input to Output
28 24
4040
40404
29 25
5151
51515
30 26
6262
62626
31 27
7373
73 Byte 1
73 Byte 2
7 Byte 3
Figure 28. Fast Read Quad I/O w/ 4-Byte Addr. (M7-M0 should be set to Fxh)
Fast Read Quad I/O with "8/16/32/64-Byte Wrap Around" in Standard SPI mode
The Fast Read Quad I/O instruction can also be used to access a specific portion within a page by issuing a "Set Burst with Wrap" (77h) command prior to ECh. The "Set Burst with Wrap" (77h) command can either enable or disable the "Wrap Around" feature for the following ECh commands. When "Wrap Around" is enabled, the data being accessed can be limited to either an 8, 16, 32 or 64-byte section of a 256-byte page. The output data starts at the initial address specified in the instruction, once it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around to the beginning boundary automatically until /CS is pulled high to terminate the command.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands.
The "Set Burst with Wrap" instruction allows three "Wrap Bits", W6-4 to be set. The W4 bit is used to enable or disable the "Wrap Around" operation while W6-5 are used to specify the length of the wrap around section within a page. Refer to section 8.2.24 for detail descriptions.
- 48 -
Publication Release Date: October 23, 2018 Revision I
W25Q256JV
8.2.22 Set Burst with Wrap (77h)
The Set Burst with Wrap (77h) instruction is used in conjunction with "Fast Read Quad I/O" and "Word Read Quad I/O" instructions to access a fixed length of 8/16/32/64-byte section within a 256-byte page. Certain applications can benefit from this feature and improve the overall system code execution performance.
Similar to a Quad I/O instruction, the Set Burst with Wrap instruction is initiated by driving the /CS pin low and then shifting the instruction code "77h" followed by 24/32 dummy bits and 8 "Wrap Bits", W7-0. The instruction sequence is shown in Figure 28. Wrap bit W7 and the lower nibble W3-0 are not used.
W6, W5
0 0 0 1 1 0 1 1
W4 = 0
Wrap Around
Wrap Length
Yes
8-byte
Yes
16-byte
Yes
32-byte
Yes
64-byte
W4 =1 (DEFAULT)
Wrap Around Wrap Length
No
N/A
No
N/A
No
N/A
No
N/A
Once W6-4 is set by a Set Burst with Wrap instruction, all the following "Fast Read Quad I/O" instructions will use the W6-4 setting to access the 8/16/32/64-byte section within any page. To exit the "Wrap Around" function and return to normal read operation, another Set Burst with Wrap instruction should be issued to set W4 = 1. The default value of W4 upon power on or after a software/hardware reset is 1.
/CS CLK
Mode 3 Mode 0
IO0 IO1 IO2 IO3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Mode 3
Instruction (77h)
don't care
don't care
don't care
Wrap Bit
Mode 0
X X X X X X w4 X
X X X X X X w5 X
X X X X X X w6 X
XXXXXXXX
Figure 28. Set Burst with Wrap Instruction 32-Bit dummy bits are required when the device is operating in 4-Byte Address Mode
- 49 -
W25Q256JV
8.2.23 Page Program (02h)
The Page Program instruction allows from one byte to 256 bytes (a page) of data to be programmed at previously erased (FFh) memory locations. A Write Enable instruction must be executed before the device will accept the Page Program Instruction (Status Register bit WEL= 1). The instruction is initiated by driving the /CS pin low then shifting the instruction code "02h" followed by a 24/32-bit address (A23/A31A0) and at least one data byte, into the DI pin. The /CS pin must be held low for the entire length of the instruction while data is being sent to the device. The Page Program instruction sequence is shown in Figure 32.
If an entire 256 byte page is to be programmed, the last address byte (the 8 least significant address bits) should be set to 0. If the last address byte is not zero, and the number of clocks exceeds the remaining page length, the addressing will wrap to the beginning of the page. In some cases, less than 256 bytes (a partial page) can be programmed without having any effect on other bytes within the same page. One condition to perform a partial page program is that the number of clocks cannot exceed the remaining page length. If more than 256 bytes are sent to the device the addressing will wrap to the beginning of the page and overwrite previously sent data.
As with the write and erase instructions, the /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the Page Program instruction will not be executed. After /CS is driven high, the self-timed Page Program instruction will commence for a time duration of tpp (See AC Characteristics). While the Page Program cycle is in progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the Page Program cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. After the Page Program cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Page Program instruction will not be executed if the addressed page is protected by the Block Protect (CMP, TB, BP3, BP2, BP1, and BP0) bits or the Individual Block/Sector Locks.
/CS
CLK
Mode 3 Mode 0
0 1 2 3 4 5 6 7 8 9 10
28 29 30 31 32 33 34 35 36 37 38 39
DI (IO0)
/CS
* = MSB
Instruction (02h)
24-Bit Address
Data Byte 1
23 22 21
*
321076543210
*
2072 2073 2074 2075 2076 2077 2078 2079
CLK
DI (IO0)
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Data Byte 2
Data Byte 3
07654321076543210
*
*
Data Byte 256
76543210
*
Mode 3 Mode 0
Figure 32. Page Program Instruction 32-Bit Address is required when the device is operating in 4-Byte Address Mode
- 50 -
Publication Release Date: October 23, 2018 Revision I
W25Q256JV
8.2.24 Page Program with 4-Byte Address (12h) The Page Program with 4-Byte Address instruction is similar to the Page Program instruction except that it requires 32-bit address instead of 24-bit address. No matter the device is operating in 3-Byte Address Mode or 4-byte Address Mode, the Page Program with 4-Byte Address instruction will always require 32bit address to access the entire 256Mb memory.
/CS
CLK
Mode 3 Mode 0
0 1 2 3 4 5 6 7 8 9 10
36 37 38 39 40 41 42 43 44 45 46 47
DI (IO0)
/CS
* = MSB
Instruction (12h)
32-Bit Address
Data Byte 1
31 30 29
*
321076543210
*
2080 2081 2082 2083 2084 2085 2086 2087
CLK
DI (IO0)
47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
Data Byte 2
Data Byte 3
07654321076543210
*
*
Data Byte 256
76543210
*
Mode 3 Mode 0
Figure 33. Page Program with 4-Byte Addr.
- 51 -
W25Q256JV
8.2.25 Quad Input Page Program (32h)
The Quad Page Program instruction allows up to 256 bytes of data to be programmed at previously erased (FFh) memory locations using four pins: IO0, IO1, IO2, and IO3. The Quad Page Program can improve performance for PROM Programmer and applications that have slow clock speeds <5MHz. Systems with faster clock speed will not realize much benefit for the Quad Page Program instruction since the inherent page program time is much greater than the time it take to clock-in the data.
To use Quad Page Program the Quad Enable (QE) bit in Status Register-2 must be set to 1. A Write Enable instruction must be executed before the device will accept the Quad Page Program instruction (Status Register-1, WEL=1). The instruction is initiated by driving the /CS pin low then shifting the instruction code "32h" followed by a 24/32-bit address (A23/A31-A0) and at least one data byte, into the IO pins. The /CS pin must be held low for the entire length of the instruction while data is being sent to the device. All other functions of Quad Page Program are identical to standard Page Program. The Quad Page Program instruction sequence is shown in Figure 34.
/CS CLK
Mode 3 Mode 0
0 1 2 3 4 5 6 7 8 9 10
28 29 30 31
Instruction (32h)
24-Bit Address
IO0
23 22 21
3210
*
IO1
IO2
IO3
* = MSB
/CS
536 537 538 539 540 541 542 543
CLK IO0
31 32 33 34 35 36 37
Byte 1 Byte 2 Byte 3 0404040
Byte 253
40
Byte 254
40
Byte 255
40
Byte 256
40
IO1
515151
51515151
IO2
626262
62626262
IO3
737373
***
73737373
****
Figure 34. Quad Input Page Program Instruction 32-Bit Address is required when the device is operating in 4-Byte Address Mode
Mode 3 Mode 0
- 52 -
Publication Release Date: October 23, 2018 Revision I
W25Q256JV
8.2.26 Quad Input Page Program with 4-Byte Address (34h)
The Quad Input Page Program with 4-Byte Address instruction is similar to the Quad Input Page Program instruction except that it requires 32-bit address instead of 24-bit address. No matter the device is operating in 3-Byte Address Mode or 4-byte Address Mode, the Quad Input Page Program with 4-Byte Address instruction will always require 32-bit address to access the entire 256Mb memory.
/CS CLK
Mode 3 Mode 0
IO0 IO1
0 1 2 3 4 5 6 7 8 9 10
36 37 38 39
Instruction (34h)
32-Bit Address
31 30 29
*
3210
IO2
IO3
* = MSB
/CS
544 545 546 547 548 549 550 551
CLK
IO0 IO1 IO2 IO3
39 40 41 42 43 44 45
Byte 1 Byte 2 Byte 3 0404040
Byte 253
40
Byte 254
40
Byte 255
40
Byte 256
40
515151
51515151
626262
62626262
737373
***
73737373
****
Figure 35. Quad Input Page Program with 4-Byte Addr.
Mode 3 Mode 0
- 53 -
W25Q256JV
8.2.27 Sector Erase (20h)
The Sector Erase instruction sets all memory within a specified sector (4K-bytes) to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Sector Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code "20h" followed a 24/32-bit sector address (A23/A31-A0). The Sector Erase instruction sequence is shown in Figure 36.
The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the Sector Erase instruction will not be executed. After /CS is driven high, the self-timed Sector Erase instruction will commence for a time duration of tSE (See AC Characteristics). While the Sector Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the Sector Erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. After the Sector Erase cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Sector Erase instruction will not be executed if the addressed page is protected by the Block Protect (CMP, TB, BP3, BP2, BP1, and BP0) bits or the Individual Block/Sector Locks.
/CS
CLK
DI (IO0)
DO (IO1)
Mode 3
0
Mode 0
* = MSB
123456789
29 30 31
Instruction (20h)
24-Bit Address
23 22
*
High Impedance
210
Mode 3 Mode 0
Figure 36. Sector Erase Instruction 32-Bit Address is required when the device is operating in 4-Byte Address Mode
- 54 -
Publication Release Date: October 23, 2018 Revision I
W25Q256JV
8.2.28 Sector Erase with 4-Byte Address (21h)
The Sector Erase with 4-Byte Address instruction is similar to the Sector Erase instruction except that it requires 32-bit address instead of 24-bit address. No matter the device is operating in 3-Byte Address Mode or 4-byte Address Mode, the Sector Erase with 4-Byte Address instruction will always require 32-bit address to access the entire 256Mb memory.
/CS
CLK
DI (IO0)
DO (IO1)
Mode 3
0
Mode 0
* = MSB
123456789
37 38 39
Instruction (21h)
32-Bit Address
31 30
*
High Impedance
210
Mode 3 Mode 0
Figure 37. Sector Erase with 4-Byte Address Instruction
- 55 -
W25Q256JV
8.2.29 32KB Block Erase (52h)
The Block Erase instruction sets all memory within a specified block (32K-bytes) to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Block Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code "52h" followed a 24/32-bit block address (A23/A31-A0). The Block Erase instruction sequence is shown in Figure 38.
The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the Block Erase instruction will not be executed. After /CS is driven high, the self-timed Block Erase instruction will commence for a time duration of tBE1 (See AC Characteristics). While the Block Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. After the Block Erase cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase instruction will not be executed if the addressed page is protected by the Block Protect (CMP, TB, BP3, BP2, BP1, and BP0) bits or the Individual Block/Sector Locks.
/CS
CLK
DI (IO0)
DO (IO1)
Mode 3
0
Mode 0
* = MSB
123456789
29 30 31
Instruction (52h)
24-Bit Address
23 22
*
High Impedance
210
Mode 3 Mode 0
Figure 38a. 32KB Block Erase Instruction 32-Bit Address is required when the device is operating in 4-Byte Address Mode
- 56 -
Publication Release Date: October 23, 2018 Revision I
W25Q256JV
8.2.30 64KB Block Erase (D8h)
The Block Erase instruction sets all memory within a specified block (64K-bytes) to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Block Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code "D8h" followed a 24/32-bit block address (A23/A31-A0). The Block Erase instruction sequence is shown in Figure 33a & 33b.
The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the Block Erase instruction will not be executed. After /CS is driven high, the self-timed Block Erase instruction will commence for a time duration of tBE (See AC Characteristics). While the Block Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. After the Block Erase cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase instruction will not be executed if the addressed page is protected by the Block Protect (CMP, TB, BP3, BP2, BP1, and BP0) bits or the Individual Block/Sector Locks.
/CS
CLK
DI (IO0)
DO (IO1)
Mode 3
0
Mode 0
* = MSB
123456789
29 30 31
Instruction (D8h)
24-Bit Address
23 22
*
High Impedance
210
Mode 3 Mode 0
Figure 39. 64KB Block Erase Instruction 32-Bit Address is required when the device is operating in 4-Byte Address Mode
- 57 -
W25Q256JV
8.2.31 64KB Block Erase with 4-Byte Address (DCh) The 64KB Block Erase with 4-Byte Address instruction is similar to the 64KB Block Erase instruction except that it requires 32-bit address instead of 24-bit address. No matter the device is operating in 3-Byte Address Mode or 4-byte Address Mode, the 64KB Block Erase with 4-Byte Address instruction will always require 32-bit address to access the entire 256Mb memory.
/CS
CLK
DI (IO0)
DO (IO1)
Mode 3
0
Mode 0
* = MSB
123456789
37 38 39
Instruction (DCh)
32-Bit Address
31 30
*
High Impedance
210
Mode 3 Mode 0
Figure 40. 64KB Block Erase with 4-Byte Address Instruction
- 58 -
Publication Release Date: October 23, 2018 Revision I
W25Q256JV
8.2.32 Chip Erase (C7h / 60h) The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Chip Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code "C7h" or "60h". The Chip Erase instruction sequence is shown in Figure 41.
The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Chip Erase instruction will not be executed. After /CS is driven high, the self-timed Chip Erase instruction will commence for a time duration of tCE (See AC Characteristics). While the Chip Erase cycle is in progress, the Read Status Register instruction may still be accessed to check the status of the BUSY bit. The BUSY bit is a 1 during the Chip Erase cycle and becomes a 0 when finished and the device is ready to accept other instructions again. After the Chip Erase cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Chip Erase instruction will not be executed if any memory region is protected by the Block Protect (CMP, TB, BP3, BP2, BP1, and BP0) bits or the Individual Block/Sector Locks.
/CS
CLK
Mode 3 Mode 0
DI (IO0)
DO (IO1)
01234567
Mode 3 Mode 0
Instruction (C7h/60h)
High Impedance
Figure 41. Chip Erase Instruction Sequence Diagram
- 59 -
W25Q256JV
8.2.33 Erase / Program Suspend (75h)
The Erase/Program Suspend instruction "75h", allows the system to interrupt a Sector or Block Erase operation or a Page Program operation and then read from or program/erase data to, any other sectors or blocks. The Erase/Program Suspend instruction sequence is shown in Figure 42.
The Write Status Register instruction (01h) and Erase instructions (20h, 52h, D8h, C7h, 60h, 44h) are not allowed during Erase Suspend. Erase Suspend is valid only during the Sector or Block erase operation. If written during the Chip Erase operation, the Erase Suspend instruction is ignored. The Write Status Register instruction (01h) and Program instructions (02h, 32h, 42h) are not allowed during Program Suspend. Program Suspend is valid only during the Page Program or Quad Page Program operation.
The Erase/Program Suspend instruction "75h" will be accepted by the device only if the SUS bit in the Status Register equals to 0 and the BUSY bit equals to 1 while a Sector or Block Erase or a Page Program operation is on-going. If the SUS bit equals to 1 or the BUSY bit equals to 0, the Suspend instruction will be ignored by the device. A maximum of time of "tSUS" (See AC Characteristics) is required to suspend the erase or program operation. The BUSY bit in the Status Register will be cleared from 1 to 0 within "tSUS" and the SUS bit in the Status Register will be set from 0 to 1 immediately after Erase/Program Suspend. For a previously resumed Erase/Program operation, it is also required that the Suspend instruction "75h" is not issued earlier than a minimum of time of "tSUS" following the preceding Resume instruction "7Ah".
Unexpected power off during the Erase/Program suspend state will reset the device and release the suspend state. SUS bit in the Status Register will also reset to 0. The data within the page, sector or block that was being suspended may become corrupted. It is recommended for the user to implement system design techniques against the accidental power interruption and preserve data integrity during erase/program suspend state.
/CS
CLK
Mode 3 Mode 0
DI (IO0)
DO (IO1)
01234567 Instruction (75h)
High Impedance
tSUS
Figure 42. Erase/Program Suspend Instruction
Mode 3 Mode 0
Accept instructions
- 60 -
Publication Release Date: October 23, 2018 Revision I
W25Q256JV
8.2.34 Erase / Program Resume (7Ah)
The Erase/Program Resume instruction "7Ah" must be written to resume the Sector or Block Erase operation or the Page Program operation after an Erase/Program Suspend. The Resume instruction "7Ah" will be accepted by the device only if the SUS bit in the Status Register equals to 1 and the BUSY bit equals to 0. After issued the SUS bit will be cleared from 1 to 0 immediately, the BUSY bit will be set from 0 to 1 within 200ns and the Sector or Block will complete the erase operation or the page will complete the program operation. If the SUS bit equals to 0 or the BUSY bit equals to 1, the Resume instruction "7Ah" will be ignored by the device. The Erase/Program Resume instruction sequence is shown in Figure 43.
Resume instruction is ignored if the previous Erase/Program Suspend operation was interrupted by unexpected power off. It is also required that a subsequent Erase/Program Suspend instruction not to be issued within a minimum of time of "tSUS" following a previous Resume instruction.
/CS
CLK
Mode 3 Mode 0
DI (IO0)
01234567 Instruction (7Ah)
Mode 3 Mode 0
Resume previously suspended Program or Erase
Figure 43. Erase/Program Resume Instruction
- 61 -
W25Q256JV
8.2.35 Power-down (B9h)
Although the standby current during normal operation is relatively low, standby current can be further reduced with the Power-down instruction. The lower power consumption makes the Power-down instruction especially useful for battery powered applications (See ICC1 and ICC2 in AC Characteristics). The instruction is initiated by driving the /CS pin low and shifting the instruction code "B9h" as shown in Figure 44.
The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Power-down instruction will not be executed. After /CS is driven high, the power-down state will entered within the time duration of tDP (See AC Characteristics). While in the power-down state only the Release Power-down / Device ID (ABh) instruction, which restores the device to normal operation, will be recognized. All other instructions are ignored. This includes the Read Status Register instruction, which is always available during normal operation. Ignoring all but one instruction makes the Power Down state a useful condition for securing maximum write protection. The device always powers-up in the normal operation with the standby current of ICC1.
/CS
CLK
Mode 3 Mode 0
DI (IO0)
01234567 Instruction (B9h)
tDP Mode 3
Mode 0
Stand-by current
Power-down current
Figure 44. Deep Power-down Instruction
- 62 -
Publication Release Date: October 23, 2018 Revision I
W25Q256JV
8.2.36 Release Power-down / Device ID (ABh)
The Release from Power-down / Device ID instruction is a multi-purpose instruction. It can be used to release the device from the power-down state, or obtain the devices electronic identification (ID) number.
To release the device from the power-down state, the instruction is issued by driving the /CS pin low, shifting the instruction code "ABh" and driving /CS high as shown in Figure 45. Release from power-down will take the time duration of tRES1 (See AC Characteristics) before the device will resume normal operation and other instructions are accepted. The /CS pin must remain high during the tRES1 time duration.
When used only to obtain the Device ID while not in the power-down state, the instruction is initiated by driving the /CS pin low and shifting the instruction code "ABh" followed by 3-dummy bytes. The Device ID bits are then shifted out on the falling edge of CLK with most significant bit (MSB) first. The Device ID values for the W25Q256JV is listed in Manufacturer and Device Identification table. The Device ID can be read continuously. The instruction is completed by driving /CS high.
When used to release the device from the power-down state and obtain the Device ID, the instruction is the same as previously described, and shown in Figure 45, except that after /CS is driven high it must remain high for a time duration of tRES2 (See AC Characteristics). After this time duration the device will resume normal operation and other instructions will be accepted. If the Release from Power-down / Device ID instruction is issued while an Erase, Program or Write cycle is in process (when BUSY equals 1) the instruction is ignored and will not have any effects on the current cycle.
/CS
CLK
Mode 3 Mode 0
DI (IO0)
01234567 Instruction (ABh)
tRES1
Mode 3 Mode 0
Power-down current Stand-by current
Figure 45a. Release Power-down Instruction
/CS
CLK
DI (IO0)
DO (IO1)
Mode 3
0
Mode 0
* = MSB
123456789
29 30 31 32 33 34 35 36 37 38
Instruction (ABh)
3 Dummy Bytes
Mode 3 Mode 0 tRES2
23 22
*
High Impedance
210
Device ID
76543210
*
Power-down current
Stand-by current
Figure 45b. Release Power-down / Device ID Instruction
- 63 -
W25Q256JV
8.2.37 Read Manufacturer / Device ID (90h)
The Read Manufacturer/Device ID instruction is an alternative to the Release from Power-down / Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID.
The Read Manufacturer/Device ID instruction is very similar to the Release from Power-down / Device ID instruction. The instruction is initiated by driving the /CS pin low and shifting the instruction code "90h" followed by a 24-bit address (A23-A0) of 000000h. After which, the Manufacturer ID for Winbond (EFh) and the Device ID are shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in Figure 46. The Device ID values for the W25Q256JV are listed in Manufacturer and Device Identification table. The instruction is completed by driving /CS high.
/CS
CLK
DI (IO0) DO (IO1)
/CS
CLK
Mode 3 Mode 0
0 1 2 3 4 5 6 7 8 9 10
28 29 30 31
Instruction (90h)
Address (000000h)
23 22 21
*
High Impedance
3210
* = MSB
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
Mode 3 Mode 0
DI (IO0)
0
DO (IO1)
Manufacturer ID (EFh)
76543210
*
Device ID
Figure 46. Read Manufacturer / Device ID Instruction
- 64 -
Publication Release Date: October 23, 2018 Revision I
W25Q256JV
8.2.38 Read Manufacturer / Device ID Dual I/O (92h)
The Read Manufacturer / Device ID Dual I/O instruction is an alternative to the Read Manufacturer / Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID at 2x speed.
The Read Manufacturer / Device ID Dual I/O instruction is similar to the Fast Read Dual I/O instruction. The instruction is initiated by driving the /CS pin low and shifting the instruction code "92h" followed by a 24/32-bit address (A23/A31-A0) of 000000h, but with the capability to input the Address bits two bits per clock. After which, the Manufacturer ID for Winbond (EFh) and the Device ID are shifted out 2 bits per clock on the falling edge of CLK with most significant bits (MSB) first as shown in Figure 47. The Device ID values for the W25Q256JV are listed in Manufacturer and Device Identification table. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving /CS high.
/CS CLK
Mode 3 Mode 0
DI (IO0)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Instruction (92h)
A23-16
A15-8
A7-0 (00h)
M7-0
6420642064206420
DO (IO1)
* = MSB
High Impedance
7531753175317531
*
*
*
*
/CS
CLK
DI (IO0) DO (IO1)
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
IOs switch from Input to Output 06420642064206420
17531753175317531
* MFR ID
* Device ID
* MFR ID (repeat)
* Device ID (repeat)
Mode 3 Mode 0
Figure 47. Read Manufacturer / Device ID Dual I/O Instruction
Note:
32-Bit Address is required when the device is operating in 4-Byte Address Mode
The "Continuous Read Mode" bits M(7-0) must be set to Fxh to be compatible with Fast Read Dual I/O instruction.
- 65 -
W25Q256JV
8.2.39 Read Manufacturer / Device ID Quad I/O (94h)
The Read Manufacturer / Device ID Quad I/O instruction is an alternative to the Read Manufacturer / Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID at 4x speed.
The Read Manufacturer / Device ID Quad I/O instruction is similar to the Fast Read Quad I/O instruction. The instruction is initiated by driving the /CS pin low and shifting the instruction code "94h" followed by a four clock dummy cycles and then a 24/32-bit address (A23/A31-A0) of 000000h, but with the capability to input the Address bits four bits per clock. After which, the Manufacturer ID for Winbond (EFh) and the Device ID are shifted out four bits per clock on the falling edge of CLK with most significant bit (MSB) first as shown in Figure 48. The Device ID values for the W25Q256JV are listed in Manufacturer and Device Identification table. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving /CS high.
/CS CLK
Mode 3 Mode 0
IO0 IO1 IO2 IO3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Instruction (94h)
High Impedance High Impedance High Impedance
A23-16 40
A15-8 40
A7-0 (00h)
40
M7-0 40
Dummy Dummy 4
IOs switch from Input to Output
040
51515151
5151
62626262
6262
73737373
7373 MFR ID Device ID
/CS CLK
23 24 25 26 27 28 29 30
Mode 3 Mode 0
IO0
040404040
IO1
151515151
IO2
262626262
IO3
373737373
MFR ID Device ID MFR ID Device ID
(repeat) (repeat) (repeat) (repeat)
Figure 48. Read Manufacturer / Device ID Quad I/O Instruction
Note:
32-Bit Address is required when the device is operating in 4-Byte Address Mode
The "Continuous Read Mode" bits M(7-0) must be set to Fxh to be compatible with Fast Read Quad I/O instruction.
- 66 -
Publication Release Date: October 23, 2018 Revision I
W25Q256JV
8.2.40 Read Unique ID Number (4Bh) The Read Unique ID Number instruction accesses a factory-set read-only 64-bit number that is unique to each W25Q256JV device. The ID number can be used in conjunction with user software methods to help prevent copying or cloning of a system. The Read Unique ID instruction is initiated by driving the /CS pin low and shifting the instruction code "4Bh" followed by a four bytes of dummy clocks. After which, the 64bit ID is shifted out on the falling edge of CLK as shown in Figure 49.
/CS CLK
Mode 3 Mode 0
DI (IO0)
DO (IO1)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Instruction (4Bh)
Dummy Byte 1
Dummy Byte 2
High Impedance
/CS
CLK
DI (IO0) DO (IO1)
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
Dummy Byte 3
Dummy Byte 4
* = MSB
High Impedance
63 62 61
210
* 64-bit Unique Serial Number
100 101 102
Mode 3 Mode 0
Figure 49. Read Unique ID Number Instruction 5 Dummy Bytes are required when the device is operating in 4-Byte Address Mode
- 67 -
W25Q256JV
8.2.41 Read JEDEC ID (9Fh)
For compatibility reasons, the W25Q256JV provides several instructions to electronically determine the identity of the device. The Read JEDEC ID instruction is compatible with the JEDEC standard for SPI compatible serial memories that was adopted in 2003. The instruction is initiated by driving the /CS pin low and shifting the instruction code "9Fh". The JEDEC assigned Manufacturer ID byte for Winbond (EFh) and two Device ID bytes, Memory Type (ID15-ID8) and Capacity (ID7-ID0) are then shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in Figure 50. For memory type and capacity values refer to Manufacturer and Device Identification table.
/CS
CLK
DI (IO0) DO (IO1)
/CS
CLK
Mode 3 Mode 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Instruction (9Fh)
* = MSB
High Impedance
Manufacturer ID (EFh)
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Mode 3 Mode 0
DI (IO0)
DO (IO1)
Memory Type ID15-8
Capacity ID7-0
7654321076543210
*
*
Figure 50. Read JEDEC ID Instruction
- 68 -
Publication Release Date: October 23, 2018 Revision I
W25Q256JV
8.2.42 Read SFDP Register (5Ah) The W25Q256JV features a 256-Byte Serial Flash Discoverable Parameter (SFDP) register that contains information about device configurations, available instructions and other features. The SFDP parameters are stored in one or more Parameter Identification (PID) tables. Currently only one PID table is specified, but more may be added in the future. The Read SFDP Register instruction is compatible with the SFDP standard initially established in 2010 for PC and other applications, as well as the JEDEC standard JESD216 that is published in 2011. Most Winbond SpiFlash Memories shipped after June 2011 (date code 1124 and beyond) support the SFDP feature as specified in the applicable datasheet.
The Read SFDP instruction is initiated by driving the /CS pin low and shifting the instruction code "5Ah" followed by a 24-bit address (A23-A0)(1) into the DI pin. Eight "dummy" clocks are also required before the SFDP register contents are shifted out on the falling edge of the 40th CLK with most significant bit (MSB) first as shown in Figure 51. For SFDP register values and descriptions, please refer to the Winbond Application Note for SFDP Definition Table.
Note: 1. A23-A8 = 0; A7-A0 are used to define the starting byte address for the 256-Byte SFDP Register.
/CS CLK
Mode 3 Mode 0
DI (IO0)
DO (IO1)
0 1 2 3 4 5 6 7 8 9 10
28 29 30 31
Instruction (5Ah)
24-Bit Address
23 22 21
*
High Impedance
3210
/CS
CLK
DI (IO0) DO (IO1)
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Dummy Byte
076543210
High Impedance
* = MSB
Data Out 1
Data Out 2
76543210765432107
*
*
Figure 51. Read SFDP Register Instruction Sequence Diagram Only 24-Bit Address is required when the device is operating in either 3-Byte or 4-Byte Address Mode
- 69 -
W25Q256JV
8.2.43 Erase Security Registers (44h)
The W25Q256JV offers three 256-byte Security Registers which can be erased and programmed individually. These registers may be used by the system manufacturers to store security and other important information separately from the main memory array.
The Erase Security Register instruction is similar to the Sector Erase instruction. A Write Enable instruction must be executed before the device will accept the Erase Security Register Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code "44h" followed by a 24/32-bit address (A23/A31-A0) to erase one of the three security registers.
ADDRESS Security Register #1 Security Register #2 Security Register #3
{A23/A31}-16 00h/0000h 00h/0000h 00h/0000h
A15-12 0 0 0 1 0 0 1 0 0 0 1 1
A11-8 0 0 0 0 0 0 0 0 0 0 0 0
A7-0 Don't Care Don't Care Don't Care
The Erase Security Register instruction sequence is shown in Figure 52. The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the instruction will not be executed. After /CS is driven high, the self-timed Erase Security Register operation will commence for a time duration of tSE (See AC Characteristics). While the Erase Security Register cycle is in progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. After the Erase Security Register cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Security Register Lock Bits (LB3-1) in the Status Register-2 can be used to OTP protect the security registers. Once a lock bit is set to 1, the corresponding security register will be permanently locked, Erase Security Register instruction to that register will be ignored (Refer to section 7.1.8 for detail descriptions).
/CS
CLK
DI (IO0)
DO (IO1)
Mode 3
0
Mode 0
* = MSB
123456789
29 30 31
Instruction (44h)
24-Bit Address
23 22
*
High Impedance
210
Mode 3 Mode 0
Figure 52. Erase Security Registers Instruction 32-Bit Address is required when the device is operating in 4-Byte Address Mode
- 70 -
Publication Release Date: October 23, 2018 Revision I
W25Q256JV
8.2.44 Program Security Registers (42h)
The Program Security Register instruction is similar to the Page Program instruction. It allows from one byte to 256 bytes of security register data to be programmed at previously erased (FFh) memory locations. A Write Enable instruction must be executed before the device will accept the Program Security Register Instruction (Status Register bit WEL= 1). The instruction is initiated by driving the /CS pin low then shifting the instruction code "42h" followed by a 24/32-bit address (A23/A31-A0) and at least one data byte, into the DI pin. The /CS pin must be held low for the entire length of the instruction while data is being sent to the device.
ADDRESS Security Register #1 Security Register #2 Security Register #3
{A23/A31}-16 00h/0000h 00h/0000h 00h/0000h
A15-12 0 0 0 1 0 0 1 0 0 0 1 1
A11-8 0 0 0 0 0 0 0 0 0 0 0 0
A7-0 Byte Address Byte Address Byte Address
The Program Security Register instruction sequence is shown in Figure 53. The Security Register Lock Bits (LB3-1) in the Status Register-2 can be used to OTP protect the security registers. Once a lock bit is set to 1, the corresponding security register will be permanently locked, Program Security Register instruction to that register will be ignored (See 7.1.8, 8.2.25 for detail descriptions).
/CS
CLK
Mode 3 Mode 0
0 1 2 3 4 5 6 7 8 9 10
28 29 30 31 32 33 34 35 36 37 38 39
DI (IO0)
/CS
* = MSB
Instruction (42h)
24-Bit Address
Data Byte 1
23 22 21
*
321076543210
*
2072 2073 2074 2075 2076 2077 2078 2079
CLK
DI (IO0)
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Data Byte 2
Data Byte 3
07654321076543210
*
*
Data Byte 256
76543210
*
Mode 3 Mode 0
Figure 53. Program Security Registers Instruction 32-Bit Address is required when the device is operating in 4-Byte Address Mode
- 71 -
W25Q256JV
8.2.45 Read Security Registers (48h)
The Read Security Register instruction is similar to the Fast Read instruction and allows one or more data bytes to be sequentially read from one of the four security registers. The instruction is initiated by driving the /CS pin low and then shifting the instruction code "48h" followed by a 24/32-bit address (A23/A31-A0) and eight "dummy" clocks into the DI pin. The code and address bits are latched on the rising edge of the CLK pin. After the address is received, the data byte of the addressed memory location will be shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first. The byte address is automatically incremented to the next byte address after each byte of data is shifted out. Once the byte address reaches the last byte of the register (byte address FFh), it will reset to address 00h, the first byte of the register, and continue to increment. The instruction is completed by driving /CS high. The Read Security Register instruction sequence is shown in Figure 54. If a Read Security Register instruction is issued while an Erase, Program or Write cycle is in process (BUSY=1) the instruction is ignored and will not have any effects on the current cycle. The Read Security Register instruction allows clock rates from D.C. to a maximum of FR (see AC Electrical Characteristics).
ADDRESS Security Register #1 Security Register #2 Security Register #3
{A23/A31}-16 00h/0000h 00h/0000h 00h/0000h
A15-12 0 0 0 1 0 0 1 0 0 0 1 1
A11-8 0 0 0 0 0 0 0 0 0 0 0 0
A7-0 Byte Address Byte Address Byte Address
/CS
CLK
DI (IO0) DO (IO1) /CS
CLK
DI (IO0) DO (IO1)
Mode 3 Mode 0
0 1 2 3 4 5 6 7 8 9 10
28 29 30 31
Instruction (48h)
24-Bit Address
23 22 21
*
High Impedance
3210
* = MSB
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Dummy Byte
076543210
High Impedance
Data Out 1
Data Out 2
76543210765432107
*
*
Figure 54. Read Security Registers Instruction 32-Bit Address is required when the device is operating in 4-Byte Address Mode
- 72 -
Publication Release Date: October 23, 2018 Revision I
W25Q256JV
8.2.46 Individual Block/Sector Lock (36h)
The Individual Block/Sector Lock provides an alternative way to protect the memory array from adverse Erase/Program. In order to use the Individual Block/Sector Locks, the WPS bit in Status Register-3 must be set to 1. If WPS=0, the write protection will be determined by the combination of CMP, TB, BP[3:0] bits in the Status Registers. The Individual Block/Sector Lock bits are volatile bits. The default values after device power up or after a Reset are 1, so the entire memory array is being protected.
To lock a specific block or sector as illustrated in Figure 4d, an Individual Block/Sector Lock command must be issued by driving /CS low, shifting the instruction code "36h" into the Data Input (DI) pin on the rising edge of CLK, followed by a 24/32-bit address and then driving /CS high.
/CS
CLK
DI (IO0)
DO (IO1)
Mode 3
0
Mode 0
* = MSB
123456789
29 30 31
Instruction (36h)
24-Bit Address
23 22
*
High Impedance
210
Mode 3 Mode 0
Figure 55. Individual Block/Sector Lock Instruction 32-Bit Address is required when the device is operating in 4-Byte Address Mode
- 73 -
W25Q256JV
8.2.47 Individual Block/Sector Unlock (39h)
The Individual Block/Sector Lock provides an alternative way to protect the memory array from adverse Erase/Program. In order to use the Individual Block/Sector Locks, the WPS bit in Status Register-3 must be set to 1. If WPS=0, the write protection will be determined by the combination of CMP, TB, BP[3:0] bits in the Status Registers. The Individual Block/Sector Lock bits are volatile bits. The default values after device power up or after a Reset are 1, so the entire memory array is being protected.
To unlock a specific block or sector as illustrated in Figure 4d, an Individual Block/Sector Unlock command must be issued by driving /CS low, shifting the instruction code "39h" into the Data Input (DI) pin on the rising edge of CLK, followed by a 24/32-bit address and then driving /CS high.
/CS
CLK
DI (IO0)
DO (IO1)
Mode 3
0
Mode 0
* = MSB
123456789
29 30 31
Instruction (39h)
24-Bit Address
23 22
*
High Impedance
210
Mode 3 Mode 0
Figure 56. Individual Block Unlock Instruction 32-Bit Address is required when the device is operating in 4-Byte Address Mode
- 74 -
Publication Release Date: October 23, 2018 Revision I
W25Q256JV
8.2.48 Read Block/Sector Lock (3Dh) The Individual Block/Sector Lock provides an alternative way to protect the memory array from adverse Erase/Program. In order to use the Individual Block/Sector Locks, the WPS bit in Status Register-3 must be set to 1. If WPS=0, the write protection will be determined by the combination of CMP, TB, BP[3:0] bits in the Status Registers. The Individual Block/Sector Lock bits are volatile bits. The default values after device power up or after a Reset are 1, so the entire memory array is being protected.
To read out the lock bit value of a specific block or sector as illustrated in Figure 4d, a Read Block/Sector Lock command must be issued by driving /CS low, shifting the instruction code "3Dh" into the Data Input (DI) pin on the rising edge of CLK, followed by a 24/32-bit address. The Block/Sector Lock bit value will be shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first as shown in Figure 57. If the least significant bit (LSB) is 1, the corresponding block/sector is locked; if LSB=0, the corresponding block/sector is unlocked, Erase/Program operation can be performed.
/CS
CLK
DI (IO0)
DO (IO1)
Mode 3
0
Mode 0
* = MSB
1 2 3 4 5 6 7 8 9 10
28 29 30 31 32 33 34 35 36 37 38 39
Instruction (3Dh)
24-Bit Address
23 22 21
*
High Impedance
3210
Lock Value Out XXXXXXX0
*
Mode 3 Mode 0
Figure 57. Read Block Lock Instruction 32-Bit Address is required when the device is operating in 4-Byte Address Mode
- 75 -
W25Q256JV
8.2.49 Global Block/Sector Lock (7Eh)
All Block/Sector Lock bits can be set to 1 by the Global Block/Sector Lock instruction. The command must be issued by driving /CS low, shifting the instruction code "7Eh" into the Data Input (DI) pin on the rising edge of CLK, and then driving /CS high.
/CS CLK
Mode 3 Mode 0
DI (IO0)
DO (IO1)
0 1 2 3 4 5 6 7 Mode 3 Mode 0
Instruction (7Eh)
High Impedance
Figure 58. Global Block Lock Instruction for SPI
8.2.50 Global Block/Sector Unlock (98h)
All Block/Sector Lock bits can be set to 0 by the Global Block/Sector Unlock instruction. The command must be issued by driving /CS low, shifting the instruction code "98h" into the Data Input (DI) pin on the rising edge of CLK, and then driving /CS high.
/CS CLK
Mode 3 Mode 0
DI (IO0)
DO (IO1)
01234567
Instruction (98h)
Mode 3 Mode 0
High Impedance
Figure 59. Global Block Unlock Instruction
- 76 -
Publication Release Date: October 23, 2018 Revision I
W25Q256JV
8.2.51 Enable Reset (66h) and Reset Device (99h)
Because of the small package and the limitation on the number of pins, the W25Q256JV provide a software Reset instruction instead of a dedicated RESET pin. Once the Reset instruction is accepted, any on-going internal operations will be terminated and the device will return to its default power-on state and lose all the current volatile settings, such as Volatile Status Register bits, Write Enable Latch (WEL) status, Program/Erase Suspend status, Read parameter setting (P7-P0), Continuous Read Mode bit setting (M7-M0) and Wrap Bit setting (W6-W4).
"Enable Reset (66h)" and "Reset (99h)" instructions can be issued in SPI. To avoid accidental reset, both instructions must be issued in sequence. Any other commands other than "Reset (99h)" after the "Enable Reset (66h)" command will disable the "Reset Enable" state. A new sequence of "Enable Reset (66h)" and "Reset (99h)" is needed to reset the device. Once the Reset command is accepted by the device, the device will take approximately tRST=30us to reset. During this period, no command will be accepted.
Data corruption may happen if there is an on-going or suspended internal Erase or Program operation when Reset command sequence is accepted by the device. It is recommended to check the BUSY bit and the SUS bit in Status Register before issuing the Reset command sequence.
/CS
CLK
Mode 3 Mode 0
DI (IO0)
DO (IO1)
01234567 Instruction (66h)
Mode 3 Mode 0
01234567
Mode 3 Mode 0
Instruction (99h)
High Impedance Figure 60. Enable Reset and Reset Instruction Sequence
- 77 -
W25Q256JV
9. ELECTRICAL CHARACTERISTICS
9.1 Absolute Maximum Ratings (1)
PARAMETERS Supply Voltage Voltage Applied to Any Pin
SYMBOL VCC VIO
Transient Voltage on any Pin
VIOT
Storage Temperature Lead Temperature Electrostatic Discharge Voltage
TSTG TLEAD VESD
CONDITIONS
Relative to Ground <20nS Transient Relative to Ground
Human Body Model(3)
RANGE 0.6 to +4.6 0.6 to VCC+0.4
2.0 to VCC+2.0
65 to +150 See Note (2) 2000 to +2000
UNIT V V
V
°C °C V
Notes:
1. This device has been designed and tested for the specified operation ranges. Proper operation outside of these levels is not guaranteed. Exposure to absolute maximum ratings may affect device reliability. Exposure beyond absolute maximum ratings may cause permanent damage.
2. Compliant with JEDEC Standard J-STD-20C for small body Sn-Pb or Pb-free (Green) assembly and the European directive on restrictions on hazardous substances (RoHS) 2002/95/EU.
3. JEDEC Std JESD22-A114A (C1=100pF, R1=1500 ohms, R2=500 ohms).
9.2 Operating Ranges
PARAMETER
SYMBOL CONDITIONS
Supply Voltage(1)
Ambient Temperature, Operating
VCC TA
FR = 133MHz, FR = 104MHz, Industrial Industrial Plus
fR = 50MHz fR = 50MHz
SPEC
MIN MAX
3.0
3.6
2.7
3.0
40 +85
40 +105
UNIT
V V °C °C
Note:
1. VCC voltage during Read can operate across the min and max range but should not exceed ±10% of the programming (erase/write) voltage.
- 78 -
Publication Release Date: October 23, 2018 Revision I
W25Q256JV
9.3 Power-up Power-down Timing and Requirements
PARAMETER
VCC (min) to /CS Low Time Delay Before Write Instruction Write Inhibit Threshold Voltage
SYMBOL
tVSL(1) tPUW(1) VWI(1)
SPEC MIN 20
5 1.0
MAX 2.0
Note: 1. These parameters are characterized only.
UNIT
µs ms V
VCC VCC (max)
Program, Erase and Write Instructions are ignored /CS must track VCC
VCC (min) VWI
Reset State
tVSL
Read Instructions Allowed
tPUW
Device is fully Accessible
VCC
Figure 65a. Power-up Timing and Voltage Levels
/CS must track VCC during VCC Ramp Up/Down
Time
/CS
Figure 65b. Power-up, Power-Down Requirement
Time
- 79 -
W25Q256JV
9.4 DC Electrical Characteristics
PARAMETER
Input Capacitance Output Capacitance
SYMBOL CONDITIONS
CIN(1) Cout(1)
VIN = 0V VOUT = 0V
SPEC
MIN
TYP
MAX
6
8
Input Leakage
ILI
±2
I/O Leakage
ILO
±2
Standby Current
ICC1
/CS = VCC, VIN = GND or VCC
10
60
Power-down Current
ICC2
/CS = VCC, VIN = GND or VCC
1
20
Current Read Data / Dual /Quad 50MHz(2)
ICC3
C = 0.1 VCC / 0.9 VCC DO = Open
8
15
Current Read Data /
Dual Output Read/Quad Output Read 104MHz(2)
ICC3
C = 0.1 VCC / 0.9 VCC DO = Open
12
20
Current Write Status Register
ICC4
/CS = VCC
20
25
Current Page Program ICC5
/CS = VCC
20
25
Current Sector/Block Erase
ICC6
/CS = VCC
20
25
Current Chip Erase
ICC7
/CS = VCC
20
25
Input Low Voltage
VIL
0.5
VCC x 0.3
Input High Voltage
VIH
VCC x 0.7
VCC + 0.4
Output Low Voltage
VOL
IOL = 100 µA
0.2
Output High Voltage
VOH
IOH = 100 µA
VCC 0.2
Notes: 1. Tested on sample basis and specified through design and characterization data. TA = 25° C, VCC = 3.0V. 2. Checker Board Pattern.
UNIT
pF pF µA µA µA
µA
mA
mA
mA mA mA mA V V V V
- 80 -
Publication Release Date: October 23, 2018 Revision I
W25Q256JV
9.5 AC Measurement Conditions
PARAMETER
Load Capacitance Input Rise and Fall Times Input Pulse Voltages Input Timing Reference Voltages Output Timing Reference Voltages
SYMBOL
CL TR, TF
VIN
IN
OUT
Note: 1. Output Hi-Z is defined as the point where data out is no longer driven.
SPEC
MIN
MAX
30
5
0.1 VCC to 0.9 VCC
0.3 VCC to 0.7 VCC
0.5 VCC to 0.5 VCC
Input Levels
Input and Output Timing Reference Levels
0.9 VCC 0.1 VCC
0.5 VCC
Figure 66. AC Measurement I/O Waveform
UNIT
pF ns V V V
- 81 -
W25Q256JV
9.6 AC Electrical Characteristics(6)
DESCRIPTION
SYMBOL
Clock frequency except for Read Data (03h) & DTR instructions (3.0V-3.6V) Clock frequency except for Read Data (03h) & DTR instructions( 2.7V-3.0V) Clock frequency for Read Data instruction (03h) Clock High, Low Time for all instructions except for Read Data (03h) Clock High, Low Time for Read Data (03h) instruction Clock Rise Time peak to peak Clock Fall Time peak to peak /CS Active Setup Time relative to CLK /CS Not Active Hold Time relative to CLK Data In Setup Time Data In Hold Time /CS Active Hold Time relative to CLK /CS Not Active Setup Time relative to CLK /CS Deselect Time (During Read) /CS Deselect Time (During Erase or Program or Write) Output Disable Time Clock Low to Output Valid Output Hold Time
FR
FR
fR tCLH, tCLL(1) tCRLH, tCRLL(1) tCLCH(2) tCHCL(2) tSLCH tCHSL tDVCH tCHDX tCHSH tSHCH tSHSL1 tSHSL2 tSHQZ(2) tCLQV1 tCLQX
SPEC
ALT
UNIT
MIN
TYP MAX
fC1
D.C.
133
MHz
fC1
D.C.
D.C.
45%PC
104
MHz
50
MHz
ns
45%PC
0.1
0.1
tCSS
3
3
tDSU
1
tDH
3
3
3
tCSH
10
tCSH
50
tDIS
tV1
tHO
1.5
ns
V/ns
V/ns
ns
ns
ns
ns
ns
ns
ns
ns
7
ns
6
ns
ns
Continued next page
- 82 -
Publication Release Date: October 23, 2018 Revision I
W25Q256JV
9.7 AC Electrical Characteristics (cont'd)
DESCRIPTION
SPEC
SYMBOL ALT MIN TYP
MAX
Write Protect Setup Time Before /CS Low
tWHSL(3)
20
Write Protect Hold Time After /CS High
tSHWL(3)
100
/CS High to Power-down Mode
tDP(2)
3
/CS High to Standby Mode without ID Read
tRES1(2)
3
/CS High to Standby Mode with ID Read
tRES2(2)
1.8
/CS High to next Instruction after Suspend
tSUS(2)
20
/CS High to next Instruction after Reset
tRST(2)
30
/RESET pin Low period to reset the device
tRESET(2)
1(4)
Write Status Register Time
tW
10
15
UNIT
ns ns µs µs µs µs µs µs ms
Page Program Time Sector Erase Time (4KB) Block Erase Time (32KB) Block Erase Time (64KB) Chip Erase Time
tPP
0.4
3
ms
tSE
50
400
ms
tBE1
120
1,600
ms
tBE2
150
2,000
ms
tCE
80
400
s
Notes: 1. 2. 3. 4.
5. 6.
Clock high + Clock low must be less than or equal to Pc. Pc = 1/fc(max.) Value guaranteed by design and/or characterization, not 100% tested in production. Only applicable as a constraint for a Write Status Register instruction when SRP=1. It is possible to reset the device with shorter tRESET (as short as a few hundred ns), a 1us minimum is recommended to ensure reliable operation. Tested on sample basis and specified through design and characterization data. TA = 25° C, VCC = 3.0V 4-bytes address alignment for Quad Read: read address start from A1,A0=0,0
- 83 -
W25Q256JV
9.8 Serial Output Timing
/CS
CLK
tCLQX IO output
tCLQV tCLQX
MSB OUT
9.9 Serial Input Timing
tCLQV
/CS tCHSL
CLK
IO input
tSLCH
tDVCH
MSB IN
9.1 /WP Timing
/CS tWHSL
/WP
tCHDX
tCLH tCLL LSB OUT
tSHQZ
tCHSH
tSHSL tSHCH
tCLCH
LSB IN
tCHCL
tSHWL
CLK
IO input
Write Status Register is allowed
Write Status Register is not allowed
- 84 -
Publication Release Date: October 23, 2018 Revision I
9.2 PACKAGE SPECIFICATIONs 9.3 8-Pad WFLGA 6x5-mm (Package Code M)
W25Q256JV
Symbol
A b D D2 E E2 e L y D3 E3
Min
0.70 0.35 5.90 3.30 4.90 4.20
0.55 --0.35 0.35
Millimeters
Nom
Max
0.75
0.80
0.40
0.45
6.00
6.10
3.40
3.50
5.00
5.10
4.30
4.40
1.27 BSC
0.60
0.65
---
0.08
0.40
0.45
0.40
0.45
Min
0.0275 0.0137 0.2322 0.1300 0.1929 0.1673
0.0216 ---
0.0138 0.0138
Inches Nom
0.0295 0.0157 0.2362 0.1339 0.1968 0.1692 0.050 BSC 0.0236
--0.0157 0.0157
Max
0.0314 0.0177 0.2401 0.1378 0.2007 0.1712
0.0255 0.0031 0.0177 0.0177
- 85 -
9.4 8-Pad WSON 8x6-mm (Package Code E)
W25Q256JV
SYMBOL
A A1 b C D D2 E E2 e L y
MILLIMETERS
Min
Nom
Max
0.70
0.75
0.80
0.00
0.02
0.05
0.35
0.40
0.48
---
0.20 Ref.
---
7.90
8.00
8.10
3.35
3.40
3.45
5.90
6.00
6.10
4.25
4.30
4.35
1.27 BSC
0.45
0.50
0.55
0.00
---
0.05
Min
0.028 0.000 0.014
--0.311 0.132 0.232 0.167
0.018 0.000
INCHES Nom
0.030 0.001 0.016 0.008 Ref. 0.315 0.134 0.236 0.169 0.050 BSC 0.020
---
Max
0.031 0.002 0.019
--0.319 0.136 0.240 0.171
0.022 0.002
- 86 -
Publication Release Date: October 23, 2018 Revision I
9.5 16-Pin SOIC 300-mil (Package Code F)
W25Q256JV
Symbol
A A1 A2 b C D E E1 e L y
Min
2.36 0.10 --0.33 0.18 10.08 10.01 7.39
0.38 --0°
Millimeters Nom
2.49 --2.31 0.41 0.23 10.31 10.31 7.49 1.27 BSC 0.81 -----
Max
2.64 0.30 --0.51 0.28 10.49 10.64 7.59
1.27 0.076
8°
Min
0.093 0.004
--0.013 0.007 0.397 0.394 0.291
0.015 --0°
Inches Nom
0.098 ---
0.091 0.016 0.009 0.406 0.406 0.295 0.050 BSC 0.032
-----
Max
0.104 0.012
--0.020 0.011 0.413 0.419 0.299
0.050 0.003
8°
- 87 -
W25Q256JV
9.6 24-Ball TFBGA 8x6-mm (Package Code B, 5x5-1 Ball Array)
Note: Ball land: 0.45mm. Ball Opening: 0.35mm PCB ball land suggested <= 0.35mm
Symbol
A A1 A2 b D D1 E E1 SE SD e ccc
Min
--0.26 --0.35 7.90
5.90
---
Millimeters Nom
--0.31 0.85 0.40 8.00 4.00 BSC 6.00 4.00 BSC 1.00 TYP 1.00 TYP 1.00 BSC ---
Max
1.20 0.36 --0.45 8.10
6.10
0.10
Min
--0.010
--0.014 0.311
0.232
---
Inches Nom
--0.012 0.033 0.016 0.315 0.157 BSC 0.236 0.157 BSC 0.039 TYP 0.039 TYP 0.039 BSC
---
Max
0.047 0.014
--0.018 0.319
0.240
0.0039
- 88 -
Publication Release Date: October 23, 2018 Revision I
W25Q256JV
9.7 24-Ball TFBGA 8x6-mm (Package Code C, 6x4 Ball Array)
Note: Ball land: 0.45mm. Ball Opening: 0.35mm PCB ball land suggested <= 0.35mm
Symbol
A A1 b D D1 E E1 e ccc
Min
--0.25 0.35 7.95
5.95
---
Millimeters Nom
--0.30 0.40 8.00 5.00 BSC 6.00 3.00 BSC 1.00 BSC ---
Max
1.20 0.35 0.45 8.05
6.05
0.10
Min
--0.010 0.014 0.313
0.234
---
Inches Nom
--0.012 0.016 0.315 0.197 BSC 0.236 0.118 BSC 0.039 BSC
---
Max
0.047 0.014 0.018 0.317
0.238
0.039
- 89 -
9.8 Ordering Information
W25Q256JV
W = Winbond
W(1) 25Q 256J V x I(1)
25Q = SpiFlash Serial Flash Memory with 4KB sectors, Dual/Quad I/O 256J = 256M-bit
V = 2.7V to 3.6V
F = 16-pin SOIC 300-mil E = 8-pad WSON 8x6mm B = 24-ball TFBGA 8x6-mm (5x5 ball array)
M = 8-pad WFLGA 6x5-mm C = 24-ball TFBGA 8x6-mm (6x4 ball array)
I = Industrial (-40°C to +85°C)
(2,3)
J = Industrial Plus (-40°C to +105°C)
Q(4) = Green Package (Lead-free, RoHS Compliant, Halogen-free (TBBA), Antimony-Oxide-free Sb2O3) with QE = 1 (fixed) in Status register-2. Backward compatible to FV family.
M(5) = Green Package (Lead-free, RoHS Compliant, Halogen-free (TBBA), Antimony-Oxide-free Sb2O3) with QE = 0 (programmable) in Status register-2. New device ID is used to identify JV family
Notes: 1. The "W" prefix and the Temperature designator "I" are not included on the part marking. 2. Standard bulk shipments are in Tube (shape E). Please specify alternate packing method, such as Tape and Reel (shape T) or Tray (shape S), when placing orders. 3. For shipments with special order options, please contact Winbond. 4. /HOLD function is disabled to support Standard, Dual and Quad I/O without user setting. 5. For DTR, QPI supporting, please refer to W25Q256JV DTR datasheet
- 90 -
Publication Release Date: October 23, 2018 Revision I
W25Q256JV
9.9 Valid Part Numbers and Top Side Marking
The following table provides the valid part numbers for the W25Q256JV SpiFlash Memory. Please contact Winbond for specific availability by density and package type. Winbond SpiFlash memories use a 12-digit Product Number for ordering. However, due to limited space, the Top Side Marking on all packages uses an abbreviated 10-digit number.
W25Q256JV-IQ/JQ valid part numbers:
PACKAGE TYPE
F SOIC-16 300mil
M WFLGA-8 6x5-mm
E WSON-8 8x6mm
B(1) TFBGA-24 8x6mm (5x5-1 Ball Array)
C(1) TFBGA-24 8x6mm
(6x4 Ball Array)
DENSITY 256M-bit 256M-bit 256M-bit 256M-bit
256M-bit
PRODUCT NUMBER W25Q256JVFIQ W25Q256JVMIQ W25Q256JVEIQ
W25Q256JVBIQ
TOP SIDE MARKING 25Q256JVFQ TBD 25Q256JVEQ
25Q256JVBQ
W25Q256JVCIQ
25Q256JVCQ
PACKAGE TYPE
F SOIC-16 300mil
M WFLGA-8 6x5-mm
E WSON-8 8x6mm
B(1) TFBGA-24 8x6mm (5x5-1 Ball Array)
C(1) TFBGA-24 8x6mm
(6x4 Ball Array)
DENSITY 256M-bit 256M-bit 256M-bit 256M-bit
256M-bit
PRODUCT NUMBER W25Q256JVFJQ W25Q256JVMJQ W25Q256JVEJQ
W25Q256JVBJQ
TOP SIDE MARKING Q256JVFJQ TBD Q256JVEJQ
Q256JVBJQ
W25Q256JVCJQ
Q256JVCJQ
Continued next page
- 91 -
W25Q256JV
W25Q256JV-IM/JM(2,3) valid part numbers:
PACKAGE TYPE
F SOIC-16 300mil
M WFLGA-8 6x5-mm
E WSON-8 8x6mm
B(1) TFBGA-24 8x6mm (5x5-1 Ball Array)
C(1) TFBGA-24 8x6mm
(6x4 Ball Array)
DENSITY 256M-bit 256M-bit 256M-bit 256M-bit
256M-bit
PRODUCT NUMBER W25Q256JVFIM W25Q256JVMIM W25Q256JVEIM W25Q256JVBIM
W25Q256JVCIM
TOP SIDE MARKING 25Q256JVFM TBD 25Q256JVEM 25Q256JVBM
25Q256JVCM
PACKAGE TYPE
F SOIC-16 300mil
M WFLGA-8 6x5-mm
E WSON-8 8x6mm
B(1) TFBGA-24 8x6mm (5x5-1 Ball Array)
C(1) TFBGA-24 8x6mm
(6x4 Ball Array)
DENSITY 256M-bit 256M-bit 256M-bit 256M-bit
256M-bit
PRODUCT NUMBER W25Q256JVFJM W25Q256JVMJM W25Q256JVEJM
W25Q256JVBJM
TOP SIDE MARKING Q256JVFJM TBD Q256JVEJM
Q256JVBJM
W25Q256JVCJM
Q256JVCJM
Note: 1. These package types are special order, please contact Winbond for more information. 2. For WSON packages, the package type ZP and ZE is not used in the top side marking.
3. For DTR, QPI supporting with ordering options "IM" & "JM", please refer to W25Q256JV DTR datasheet.
- 92 -
Publication Release Date: October 23, 2018 Revision I
W25Q256JV
10. REVISION IISTORY
VERSION A B
DATE 04/01/2013 09/20/2016
C
10/14/2016
D
11/30/2016
E
02/10/2017
PAGE
27 44 6
F
05/11/2017
G
08/03/2017
5 90-91
11
26
H
10/17/2018
80
82-83
5-6,85,90-91
I
10/23/2018 5-6,85,90-91
DESCRIPTION New Create Preliminary
Removed "preliminary"
Updated instruction set table 03h
Updated 6Ch waveform
Updated WSON 8X6 PIN3
Updated /WP information Updated notice for Reset pin Updated W25Q256JV-IM order information
Updated Quad SPI instruction description
Added industrial plus Updated 3Ch clock number Added ICC3(typ.) vale Updated tSLC, tCHSL, tDVCH, and tPP(typ.) value Added WSON 6X5 information
Modify WSON 6X5 to WFLGA 6X5
Trademarks
Winbond and SpiFlash are trademarks of Winbond Electronics Corporation. All other marks are the property of their respective owner.
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Furthermore, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
Information in this document is provided solely in connection with Winbond products. Winbond reserves the right to make changes, corrections, modifications or improvements to this document and the products and services described herein at any time, without notice.
- 93 -
Microsoft Word 2013 Microsoft Word 2013