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Data Sheet FEATURES Supports multiband wireless applications 3 bypassable, complex data input channels per RF DAC 1.54 GSPS maximum complex input data rate per input channel 1 independent NCO per input channel Proprietary, low spurious and distortion design 2-tone intermodulation distortion (IMD) = -83 dBc at 1.8 GHz, -7 dBFS/tone RF output Spurious free dynamic range (SFDR) <-80 dBc at 1.8 GHz, -7 dBFS RF output Flexible 8-lane, 15.4 Gbps JESD204B interface Supports single-band and multiband use cases Supports 12-bit high density mode for increased data throughput Multiple chip synchronization Supports JESD204B Subclass 1 Selectable interpolation filter for a complete set of input data rates 1×, 2×, 3×, 4×, 6×, and 8× configurable data channel interpolation 1×, 2×, 4×, 6×, 8×, and 12× configurable final interpolation Final 48-bit NCO that operates at the DAC rate to support frequency synthesis up to 6 GHz Transmit enable function allows extra power saving and downstream circuitry protection High performance, low noise PLL clock multiplier Supports 12.6 GSPS DAC update rate Observation ADC clock driver with selectable divide ratios Low power 2.55 W at 12 GSPS, dual channel mode 10 mm × 10 mm, 144-ball BGA_ED with metal enhanced thermal lid, 0.80 mm pitch APPLICATIONS Wireless communications infrastructure Multiband base station radios Microwave/E-band backhaul systems Instrumentation, automatic test equipment (ATE) Radars and jammers Dual, 16-Bit, 12.6 GSPS RF DAC with Channelizers AD9172 GENERAL DESCRIPTION The AD9172 is a high performance, dual, 16-bit digital-to-analog converter (DAC) that supports DAC sample rates to 12.6 GSPS. The device features an 8-lane, 15 Gbps JESD204B data input port, a high performance, on-chip DAC clock multiplier, and digital signal processing capabilities targeted at single-band and multiband direct to radio frequency (RF) wireless applications. The AD9172 features three complex data input channels per RF DAC that are bypassable. Each data input channel includes a configurable gain stage, an interpolation filter, and a channel numerically controlled oscillator (NCO) for flexible, multiband frequency planning. The device supports up to a 1.5 GSPS complex data rate per input channel and is capable of aggregating multiple complex input data streams up to a maximum complex data rate of 1.5 GSPS. Additionally, the AD9172 supports ultrawide bandwidth modes bypassing the channelizers to provide maximum data rates of up to 3.08 GSPS (with 16-bit resolution) and 4.1 GSPS (with 12-bit resolution). The AD9172 is available in a 144-ball BGA_ED package. PRODUCT HIGHLIGHTS 1. Supports single-band and multiband wireless applications with three bypassable complex data input channels per RF DAC at a maximum complex input data rate of 1.5 GSPS. One independent NCO per input channel. 2. Ultrawide bandwidth channel bypass modes supporting up to 3 GSPS data rates with 16-bit resolution and 4 GSPS with 12-bit resolution. 3. Low power dual converter decreases the amount of power consumption needed in high bandwidth and multichannel applications. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. 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Technical Support www.analog.com AD9172 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 3 Functional Block Diagram .............................................................. 4 Specifications..................................................................................... 5 DC Specifications ......................................................................... 5 Digital Specifications ................................................................... 6 Maximum DAC Sampling Rate Specifications......................... 6 Power Supply DC Specifications ................................................ 7 Serial Port and CMOS Pin Specifications ............................... 10 Digital Input Data Timing Specifications ............................... 11 JESD204B Interface Electrical and Speed Specifications ...... 12 Input Data Rates and Signal Bandwidth Specifications ........ 13 AC Specifications........................................................................ 14 Absolute Maximum Ratings.......................................................... 16 Reflow Profile.............................................................................. 16 Thermal Characteristics ............................................................ 16 ESD Caution................................................................................ 16 Pin Configuration and Function Descriptions........................... 17 Typical Performance Characteristics ........................................... 20 Terminology .................................................................................... 27 Theory of Operation ...................................................................... 28 Serial Port Operation ..................................................................... 30 Data Format ................................................................................ 30 Serial Port Pin Descriptions...................................................... 30 Data Sheet Serial Port Options..................................................................... 30 JESD204B Serial Data Interface.................................................... 32 JESD204B Overview .................................................................. 32 Physical Layer ............................................................................. 35 Data Link Layer .......................................................................... 38 Syncing LMFC Signals............................................................... 40 Transport Layer .......................................................................... 46 JESD204B Test Modes ............................................................... 47 JESD204B Error Monitoring..................................................... 48 Digital Datapath ............................................................................. 51 Total Datapath Interpolation .................................................... 51 Channel Digital Datapath ......................................................... 53 Main Digital Datapath ............................................................... 56 Interrupt Request Operation ........................................................ 62 Interrupt Service Routine.......................................................... 62 Applications Information .............................................................. 63 Hardware Considerations ......................................................... 63 Analog Interface Considerations.................................................. 66 DAC Input Clock Configurations ............................................ 66 Clock Output Driver .................................................................. 68 Analog Outputs .......................................................................... 68 Start-Up Sequence .......................................................................... 69 Register Summary .......................................................................... 76 Register Details ............................................................................... 84 Outline Dimensions ..................................................................... 145 Ordering Guide ........................................................................ 145 Rev. B | Page 2 of 145 Data Sheet REVISION HISTORY 8/2019--Rev. A to Rev. B Deleted Figure 31; Renumbered Sequentially .............................24 Added Figure 31 and Figure 32; Renumbered Sequentially ......24 Changes to Figure 68 and Table 37 ...............................................54 Changes to Figure 69 ......................................................................55 Change to Table 43..........................................................................58 Changes to Figure 74 ......................................................................59 Deleted Figure 85 ............................................................................66 Added Figure 85 ..............................................................................66 Changes to Table 54 ........................................................................72 Changes to Table 55 ........................................................................73 Changes to Register 0x114, Register 0x115, and Register 0x117, Table 60.............................................................................................95 Changes to Register 0x118 to Register 0x125, Table 60 .............96 Changes to Register 0x126 to Register 0x12C, Table 60 ............97 Changes to Register 0x12D to Register 0x12F, Table 60 ............98 Changes to Register 0x132 to Register 0x135, Table 60 .............99 Changes to Register 0x136 to Register 0x13C, Table 60 ..........100 Changes to Register 0x13D to Register 0x143, Table 60 ..........101 Changes to Register 0x144 to Register 0x147, Table 60 ...........102 AD9172 5/2019--Rev. 0 to Rev. A Changes to Noise Spectral Density Parameters, Table 9............14 Changes to L12 Pin Description, Table 12...................................18 Changes to Table 17 ........................................................................32 Changes to SYSREF± Sampling Section ......................................40 Changes to Subclass 1 Section.......................................................41 Change to SPI_CHIPGRADE Register, Table 59........................75 Change to DATAPATH_NCO_SYNC_CFG Register, Table 59.............................................................................................78 Change to SPI_CHIPGRADE Register, Table 60........................83 Change to DATAPATH_NCO_SYNC_CFG Register, Table 60...........................................................................................103 Changes to Ordering Guide.........................................................144 6/2017--Revision 0: Initial Version Rev. B | Page 3 of 145 AD9172 FUNCTIONAL BLOCK DIAGRAM SERDIN0± SERDIN7± SYNCOUT0± SYNCOUT1± CHANNEL 0 GAIN N CHANNEL 1 GAIN N CHANNEL 2 GAIN N SERDES JESD204B CHANNEL 3 GAIN N CHANNEL 4 GAIN N CHANNEL 5 GAIN N NCO NCO NCO NCO NCO NCO Data Sheet PA PROTECT M RAMP UP/DOWN GAIN NCO AD9172 DAC 0 DAC0± PA PROTECT M RAMP UP/DOWN GAIN NCO DAC 1 DAC1± SYNCHRONIZATION LOGIC RESET VREF CLOCK DISTRIBUTION AND CONTROL LOGIC SPI DAC ALIGN DETECT CLOCK RECEIVER CLOCK DIVIDER ÷1, ÷2, ÷3, ÷4 PLL ÷1, ÷2, ÷3 CLOCK DRIVER CLOCK RECEIVER IRQ0 IRQ1 TXEN0 TXEN1 ISET SDIO SDO CS SCLK SYSREF+ SYSREF CLKOUT+ CLKOUT CLKIN+ CLKIN 15453-001 Figure 1. Rev. B | Page 4 of 145 Data Sheet AD9172 SPECIFICATIONS DC SPECIFICATIONS AVDD1.0 = 1.0 V, AVDD1.8 = 1.8 V, DVDD1.0 = 1.0 V, DVDD1.8 = 1.8 V, SVDD1.0 = 1.0 V, and DAC output full-scale current (IOUTFS) = 20 mA, unless otherwise noted. For the minimum and maximum values, TJ = -40°C to +118°C. For the typical values, TA = 25°C, which corresponds to TJ = 51°C. Table 1. Parameter RESOLUTION ACCURACY Integral Nonlinearity (INL) Differential Nonlinearity (DNL) ANALOG OUTPUTS (DAC0+, DAC0-, DAC1+, DAC1-) Gain Error (with Internal ISET Reference) Full-Scale Output Current Minimum Maximum Common-Mode Voltage Differential Impedance DAC DEVICE CLOCK INPUT (CLKIN+, CLKIN-) Differential Input Power Minimum Maximum Differential Input Impedance1 Common-Mode Voltage CLOCK OUTPUT DRIVER (CLKOUT+, CLKOUT-) Differential Output Power Minimum Maximum Differential Output Impedance Common-Mode Voltage Output Frequency TEMPERATURE DRIFT Gain REFERENCE Internal Reference Voltage ANALOG SUPPLY VOLTAGES AVDD1.0 AVDD1.8 DIGITAL SUPPLY VOLTAGES DVDD1.0 DAVDD1.0 DVDD1.8 SERIALIZER/DESERIALIZER (SERDES) SUPPLY VOLTAGES SVDD1.0 Test Conditions/Comments RSET = 5 k RSET = 5 k RLOAD = 100 differential on-chip AC-coupled Min Typ Max Unit 16 Bit ±7 LSB ±7 LSB ±15 % 14.2 16 23.6 26 0 100 17.8 mA 28.8 mA V 0 dBm 6 dBm 100 0.5 V AC-coupled -9 0 100 0.5 727.5 dBm dBm V 3000 MHz 10 ppm/°C 0.495 V 0.95 1.0 1.71 1.8 1.05 V 1.89 V 0.95 1.0 0.95 1.0 1.71 1.8 1.05 V 1.05 V 1.89 V 0.95 1.0 1.05 V 1 See the DAC Input Clock Configurations section for more details. Rev. B | Page 5 of 145 AD9172 Data Sheet DIGITAL SPECIFICATIONS AVDD1.0 = 1.0 V, AVDD1.8 = 1.8 V, DVDD1.0 = 1.0 V, DVDD1.8 = 1.8 V, SVDD1.0 = 1.0 V, and DAC output full-scale current (IOUTFS) = 20 mA, unless otherwise noted. For the minimum and maximum values, TJ = -40°C to +118°C. For the typical values, TA = +25°C, which corresponds to TJ = 51°C. Table 2. Parameter DAC UPDATE RATE Minimum Maximum1 Adjusted2 DAC PHASE-LOCKED LOOP (PLL) VOLTAGE CONTROLLED OSCILLATOR (VCO) FREQUENCY RANGES VCO Output Divide by 1 VCO Output Divide by 2 VCO Output Divide by 3 PHASE FREQUENCY DETECT INPUT FREQUENCY RANGES 9.96 GHz VCO Frequency 10.87 GHz VCO Frequency < 9.96 GHz or VCO Frequency > 10.87 GHz DAC DEVICE CLOCK INPUT (CLKIN+, CLKIN-) FREQUENCY RANGES PLL Off PLL On Test Conditions/Comments 16-bit resolution, with interpolation 16-bit resolution, no interpolation 16-bit resolution, with interpolation 16-bit resolution, no interpolation M divider set to divide by 1 M divider set to divide by 2 M divider set to divide by 3 M divider set to divide by 4 Min Typ 12.6 6.16 1.575 6.16 8.74 4.37 2.91 25 25 2.91 25 50 75 100 Max Unit 2.91 GSPS GSPS GSPS GSPS GSPS 12.42 6.21 4.14 GSPS GSPS GSPS 225 MHz 770 MHz 12.6 GHz 770 MHz 1540 MHz 2310 MHz 3080 MHz 1 The maximum DAC update rate varies depending on the selected JESD204B mode and the lane rate for the given configuration used. The maximum DAC rate according to lane rate and voltage supply levels is listed in Table 3. 2 The adjusted DAC update rate is calculated as fDAC, divided by the minimum required interpolation factor for a given mode or the maximum channel data rate for a given mode. Different modes have different maximum DAC update rates, minimum interpolation factors, and maximum channel data rates, as shown in Table 13. MAXIMUM DAC SAMPLING RATE SPECIFICATIONS AVDD1.0 = 1.0 V, AVDD1.8 = 1.8 V, DVDD1.0 = 1.0 V, DVDD1.8 = 1.8 V, SVDD1.0 = 1.0 V, and DAC output full-scale current (IOUTFS) = 20 mA, unless otherwise noted. For the minimum and maximum values, TJ = -40°C to +118°C. For the typical values, TA = 25°C, which corresponds to TJ = 51°C. Table 3. Parameter MAXIMUM DAC UPDATE RATE SVDD1.0 = 1.0 V ± 5% SVDD1.0 = 1.0 V ± 2.5% Test Conditions/Comments Lane rate > 11 Gbps Lane rate 11 Gbps Lane rate > 11 Gbps Lane rate 11 Gbps1 Min Typ 11.67 12.37 11.79 12.6 Max Unit GSPS GSPS GSPS GSPS 1 If using the on-chip PLL, the maximum DAC speed is limited to the maximum PLL speed of 12.42 GSPS, as listed in Table 2. Rev. B | Page 6 of 145 Data Sheet AD9172 POWER SUPPLY DC SPECIFICATIONS AVDD1.0 = 1.0 V, AVDD1.8 = 1.8 V, DVDD1.0 = 1.0 V, DVDD1.8 = 1.8 V, SVDD1.0 = 1.0 V, and DAC output full-scale current (IOUTFS) = 20 mA, unless otherwise noted. For the minimum and maximum values, TJ = -40°C to +118°C. For the typical values, TA = 25°C, which corresponds to TJ = 51°C. Table 4. Parameter DUAL-LINK MODES Mode 1 (L = 2, M = 4, NP = 16, N = 16) AVDD1.0 AVDD1.8 DVDD1.0 DVDD1.8 SVDD1.0 Total Power Dissipation Mode 4 (L = 4, M = 4, NP = 16, N = 16) AVDD1.0 AVDD1.8 DVDD1.0 DVDD1.8 SVDD1.0 Total Power Dissipation Mode 0 (L = 1, M = 2, NP = 16, N = 16) AVDD1.0 AVDD1.8 DVDD1.0 DVDD1.8 SVDD1.0 Total Power Dissipation Mode 3 (L = 2, M = 2, NP = 16, N = 16) AVDD1.0 AVDD1.8 DVDD1.0 Test Conditions/Comments Min Typ 11.7965 GSPS DAC rate, 184.32 MHz PLL reference clock, 32× total interpolation (4×, 8×), 40 MHz tone at -3 dBFS, channel gain = -6 dB, channel NCOs = ±150 MHz, main NCO = 2 GHz, SYNCOUTx± in LVDS mode All supply levels set to nominal values All supply levels set to 5% tolerance Combined current consumption with the DAVDD1.0 supply All supply levels set to nominal values All supplies at 5% tolerance 725 775 110 1270 1350 35 All supply levels set to nominal values All supplies at 5% tolerance 11.7965 GSPS DAC rate, 491.52 MHz PLL reference clock, 24× total interpolation (3×, 8×), 40 MHz tone at -3 dBFS, channel gain = -6 dB, channel NCOs = ±150 MHz, main NCO = 2 GHz, SYNCOUTx± in LVDS mode Combined current consumption with the DAVDD1.0 supply 5.89824 GSPS DAC rate, 184.32 MHz PLL reference clock, 16× total interpolation (2×, 8×), 40 MHz tone at -3 dBFS, channel NCO disabled, main NCO = 1.8425 GHz, SYNCOUTx± in LVDS mode All supply levels set to nominal values All supplies at 5% tolerance Combined current consumption with the DAVDD1.0 supply All supply levels set to nominal values All supplies at 5% tolerance 11.7965 GSPS DAC rate, 184.32 MHz PLL reference clock, 24× total interpolation (3×, 8×), 40 MHz tone at -3 dBFS, channel NCO disabled, main NCO = 2.655 GHz, SYNCOUTx± in LVDS mode All supply levels set to nominal values All supplies at 5% tolerance Combined current consumption with the DAVDD1.0 supply All supply levels set to nominal values All supplies at 5% tolerance 290 305 2.55 725 110 1340 35 425 2.75 400 425 110 625 670 35 175 1.45 725 775 110 1175 1250 Max Unit 1020 mA 1120 mA 130 mA 1670 mA 1850 mA 50 mA 510 mA 560 mA 3.38 W mA mA mA mA mA W 670 mA 745 mA 130 mA 960 mA 1070 mA 50 mA 340 mA 2.15 W mA mA mA mA mA Rev. B | Page 7 of 145 AD9172 Data Sheet Parameter DVDD1.8 SVDD1.0 Total Power Dissipation Mode 9 (L = 4, M = 2, NP = 16, N = 16) AVDD1.0 AVDD1.8 DVDD1.0 DVDD1.8 SVDD1.0 Total Power Dissipation Mode 2 (L = 3, M = 6, NP = 16, N = 16) AVDD1.0 AVDD1.8 DVDD1.0 DVDD1.8 SVDD1.0 Total Power Dissipation SINGLE-LINK MODES Mode 20 (L = 8, M = 1, NP = 16, N = 16) AVDD1.0 AVDD1.8 DVDD1.0 DVDD1.8 SVDD1.0 Total Power Dissipation Mode 12 (L = 8, M = 2, NP = 12, N = 12) AVDD1.0 AVDD1.8 Test Conditions/Comments All supply levels set to nominal values All supplies at 5% tolerance Min Typ 35 245 250 2.4 12 GSPS DAC rate, 187.5 MHz PLL reference clock, 8× total interpolation (1×, 8×), 10 MHz tone at-3 dBFS, channel NCO disabled, main NCO = 3.072 GHz, SYNCOUTx± in LVDS mode All supply levels set to nominal values All supplies at 5% tolerance Combined current consumption with the DAVDD1.0 supply All supply levels set to nominal values All supplies at 5% tolerance All supply levels set to nominal values All supplies at 5% tolerance 740 785 110 1170 1250 35 530 550 2.7 12 GSPS DAC rate, 375 MHz PLL reference clock, 48× total interpolation (6×, 8×), 30 MHz tone at -3 dBFS, channel gain = -11 dB, channel NCOs = 20 MHz, main NCO = 2.1 GHz All supply levels set to nominal values All supplies at 5% tolerance Combined current consumption with the DAVDD1.0 supply All supply levels set to nominal values All supplies at 5% tolerance All supply levels set to nominal values All supplies at 5% tolerance 735 785 110 1370 1460 35 410 430 2.77 6 GSPS DAC rate, 187.5 MHz PLL reference clock, 1× total interpolation (1×, 1×), 1.8 GHz tone at -3 dBFS, channel and main NCOs disabled All supply levels set to nominal values 400 All supplies at 5% tolerance 430 75 Combined current consumption with the DAVDD1.0 supply All supply levels set to nominal values 400 All supplies at 5% tolerance 420 35 All supply levels set to nominal values 525 All supplies at 5% tolerance 550 1.5 4 GSPS DAC rate, 187.5 MHz PLL reference clock, 1× total interpolation (1×, 1×), 1 GHz tone at -3 dBFS, channel and main NCOs disabled All supply levels set to nominal values 300 All supplies at 5% tolerance 315 75 Max Unit mA mA mA W 1030 mA 1135 mA 130 mA 1580 mA 1740 mA 50 mA 840 mA 910 mA 3.63 W 1030 mA 1135 mA 130 mA mA 1800 mA 1980 mA 50 mA 680 mA 755 mA 3.69 W 670 mA 745 mA 100 mA 700 mA 810 mA 50 mA 820 mA 880 mA 2.34 W 550 mA 620 mA 100 mA Rev. B | Page 8 of 145 Data Sheet Parameter Test Conditions/Comments Min Typ DVDD1.0 Combined current consumption with the DAVDD1.0 supply All supply levels set to nominal values 325 All supplies at 5% tolerance 340 DVDD1.8 35 SVDD1.0 All supply levels set to nominal values 525 All supplies at 5% tolerance 550 Total Power 1.32 Dissipation DUAL-LINK, MODE 3 (NCO 6 GSPS DAC rate, 300 MHz PLL reference clock, 8× total interpolation (1×, 8×), ONLY, SINGLE-CHANNEL no input tone (dc internal level = 0x50FF), channel NCO = 40 MHz, main NCO MODE, NO SERDES) = 1.8425 GHz Mode 3 AVDD1.0 All supply levels set to nominal values 410 All supplies at 5% tolerance 435 AVDD1.8 110 DVDD1.0 Combined current consumption with the DAVDD1.0 supply All supply levels set to nominal values 500 All supplies at 5% tolerance 515 DVDD1.8 0.3 SVDD1.0 All supply levels set to nominal values 5 All supplies at 5% tolerance 3 Total Power 1.1 Dissipation DUAL-LINK, MODE 4 (NCO ONLY, DUAL-CHANNEL MODE, NO SERDES) 12 GSPS DAC rate, 500 MHz PLL reference clock, 32× total interpolation (4×, 8×), no input tone (dc internal level = 0x2AFF), channel NCOs = ±150 MHz, main NCO = 2 GHz Mode 4 AVDD1.0 All supply levels set to nominal values 750 All supplies at 5% tolerance 790 AVDD1.8 110 DVDD1.0 Combined current consumption with the DAVDD1.0 supply All supply levels set to nominal values 1200 All supplies at 5% tolerance 1300 DVDD1.8 0.3 SVDD1.0 5 Total Power 2.2 Dissipation AD9172 Max Unit 630 mA 725 mA 50 mA 820 mA 880 mA 2.15 W 660 mA 750 mA 130 mA 780 mA 950 mA 1 mA 100 mA 120 mA 1.671 W 1030 mA 1130 mA 130 mA 1590 mA 1750 mA 1 mA 100 mA 2.851 W Rev. B | Page 9 of 145 AD9172 Data Sheet SERIAL PORT AND CMOS PIN SPECIFICATIONS AVDD1.0 = 1.0 V, AVDD1.8 = 1.8 V, DVDD1.0 = 1.0 V, DVDD1.8 = 1.8 V, SVDD1.0 = 1.0 V, and DAC output full-scale current (IOUTFS) = 20 mA, unless otherwise noted. For the minimum and maximum values, TJ = -40°C to +118°C. For the typical values, TA = 25°C, which corresponds to TJ = 51°C. Table 5. Parameter WRITE OPERATION Maximum SCLK Clock Rate SCLK Clock High SCLK Clock Low SDIO to SCLK Setup Time SCLK to SDIO Hold Time CS to SCLK Setup Time SCLK to CS Hold Time READ OPERATION SCLK Clock Rate SCLK Clock High SCLK Clock Low SDIO to SCLK Setup Time SCLK to SDIO Hold Time CS to SCLK Setup Time SCLK to SDIO Data Valid Time SCLK to SDO Data Valid Time CS to SDIO Output Valid to High-Z CS to SDO Output Valid to High-Z INPUTS (SDIO, SCLK, CS, RESET, TXEN0, and TXEN1) Voltage Input High Low Current Input High Low OUTPUTS (SDIO, SDO) Voltage Output High 0 mA load 4 mA load Low 0 mA load 4 mA load Current Output High Low INTERRUPT OUTPUTS (IRQ0, IRQ1) Voltage Output High Low Symbol fSCLK, 1/tSCLK tPWH tPWL tDS tDH tS tH fSCLK, 1/tSCLK tPWH tPWL tDS tDH tS tDV tDV Test Comments/Conditions See Figure 45 SCLK = 20 MHz SCLK = 20 MHz See Figure 44 Not shown in Figure 44 or Figure 45 Not shown in Figure 44 or Figure 45 Min Typ Max Unit 80 MHz 5.03 ns 1.6 ns 1.154 ns 0.577 ns 1.036 ns -5.3 ps 5.03 1.6 1.158 0.537 1.036 9.6 13.7 5.4 9.59 48.58 MHz ns ns ns ns ns ns ns ns ns VIH 1.48 V VIL 0.425 V IIH ±100 nA IIL ±100 nA VOH 1.69 V 1.52 V VOL 0.045 V 0.175 V IOH 4 mA IOL 4 mA VOH 1.71 V VOL 0.075 V Rev. B | Page 10 of 145 Data Sheet AD9172 DIGITAL INPUT DATA TIMING SPECIFICATIONS AVDD1.0 = 1.0 V, AVDD1.8 = 1.8 V, DVDD1.0 = 1.0 V, DVDD1.8 = 1.8 V, SVDD1.0 = 1.0 V, and DAC output full-scale current (IOUTFS) = 20 mA, unless otherwise noted. For the minimum and maximum values, TJ = -40°C to +118°C. For the typical values, TA = 25°C, which corresponds to TJ = 51°C. Table 6. Parameter Test Conditions/Comments Min Typ Max Unit LATENCY1 Channel Interpolation Factor, Main LMFC_VAR_x = 12, LMFC_DELAY_x = 12, unless otherwise Datapath Interpolation Factor noted 1×, 1×2 JESD204B Mode 10,3 Mode 183 420 DAC clock cycle JESD204B Mode 11, Mode 19 440 DAC clock cycle JESD204B Mode 12, Mode 19 590 DAC clock cycle JESD204B Mode 203 700 DAC clock cycle JESD204B Mode 21 750 DAC clock cycle 1×, 2×2 JESD204B Mode 83 670 DAC clock cycle JESD204B Mode 9 700 DAC clock cycle 1×, 4×2 JESD204B Mode 83 1090 DAC clock cycle JESD204B Mode 9 1140 DAC clock cycle 1×, 6×2 JESD204B Mode 83 1460 DAC clock cycle JESD204B Mode 9 1530 DAC clock cycle 1×, 8×2 JESD204B Mode 3 1390 DAC clock cycle JESD204B Mode 83 1820 DAC clock cycle JESD204B Mode 9 1920 DAC clock cycle 1×, 12×2 JESD204B Mode 83 2700 DAC clock cycle JESD204B Mode 9 2840 DAC clock cycle 2×, 6×2 JESD204B Mode 3, Mode 4 1970 DAC clock cycle JESD204B Mode 5 1770 DAC clock cycle 2×, 8×2 JESD204B Mode 0 2020 DAC clock cycle JESD204B Mode 3, Mode 4 2500 DAC clock cycle 3×, 6×2 JESD204B Mode 3, Mode 4 2880 DAC clock cycle JESD204B Mode 5, Mode 6 2630 DAC clock cycle 3×, 8×2 JESD204B Mode 3, Mode 4 3310 DAC clock cycle JESD204B Mode 5, Mode 6 2980 DAC clock cycle 4×, 6×2 JESD204B Mode 0, Mode 1, Mode 2 2410 DAC clock cycle 4×, 8×2 JESD204B Mode 0, Mode 1, Mode 2 3090 DAC clock cycle 6×, 6×2 JESD204B Mode 0, Mode 1, Mode 2 3190 DAC clock cycle 6×, 8×2 JESD204B Mode 0, Mode 1, Mode 2 4130 DAC clock cycle 8×, 6×2 JESD204B Mode 7 3300 DAC clock cycle 8×, 8×2 JESD204B Mode 7 4270 DAC clock cycle DETERMINISTIC LATENCY Fixed 13 PCLK4 Variable 2 PCLK cycles SYSREF± TO LMFC DELAY 0 DAC clock cycles 1 Total latency (or pipeline delay) through the device is calculated as follows: total latency = interface latency + fixed latency + variable latency + pipeline delay. 2 The first value listed in this specification is the channel interpolation factor, and the second value is the main datapath interpolation factor. 3 LMFC_VAR_x = 7 and LMFC_DELAY_x = 4 4 PCLK is the internal processing clock for the AD9172 and equals the lane rate ÷ 40. Rev. B | Page 11 of 145 AD9172 Data Sheet JESD204B INTERFACE ELECTRICAL AND SPEED SPECIFICATIONS AVDD1.0 = 1.0 V, AVDD1.8 = 1.8 V, DVDD1.0 = 1.0 V, DVDD1.8 = 1.8 V, SVDD1.0 = 1.0 V, and DAC output full-scale current (IOUTFS) = 20 mA, unless otherwise noted. For the minimum and maximum values, TJ = -40°C to +118°C. For the typical values, TA = 25°C, which corresponds to TJ = 51°C. Table 7. Parameter JESD204B SERIAL INTERFACE RATE (SERIAL LANE RATE) JESD204B DATA INPUTS Input Leakage Current Logic High Logic Low Unit Interval Common-Mode Voltage Differential Voltage Differential Impedance SYSREF± INPUT Differential Impedance DIFFERENTIAL OUTPUTS (SYNCOUT0±, SYNCOUT1±)1 Output Differential Voltage Output Offset Voltage SINGLE-ENDED OUTPUTS (SYNCOUT0±, SYNCOUT1±) Output Voltage High Low Current Output High Low Symbol Test Conditions/Comments Min Typ Max Unit 3 15.4 Gbps UI VRCM R_VDIFF ZRDIFF TA = 25°C Input level = 1.0 V ± 0.25 V Input level = 0 V AC-coupled At dc 10 µA -4 µA 333 66.7 ps -0.05 +1.1 V 110 1050 mV 80 100 120 100 Driving 100 differential load VOD 320 390 460 mV VOS 1.08 1.12 1.15 V Driving 100 differential load VOH 1.69 V VOL 0.045 V IOH 0 mA IOL 0 mA 1 IEEE Standard 1596.3 LVDS compatible. Rev. B | Page 12 of 145 Data Sheet AD9172 INPUT DATA RATES AND SIGNAL BANDWIDTH SPECIFICATIONS AVDD1.0 = 1.0 V, AVDD1.8 = 1.8 V, DVDD1.0 = 1.0 V, DVDD1.8 = 1.8 V, SVDD1.0 = 1.0 V, and DAC output full-scale current (IOUTFS) = 20 mA, unless otherwise noted. For the minimum and maximum values, TJ = -40°C to +118°C. For the typical values, TA = 25°C, which corresponds to TJ = 51°C. Table 8. Parameter1 INPUT DATA RATE PER INPUT CHANNEL COMPLEX SIGNAL BANDWIDTH PER INPUT CHANNEL MAXIMUM NCO CLOCK RATE Channel NCO Main NCO MAXIMUM NCO SHIFT FREQUENCY RANGE Channel NCO Main NCO MAXIMUM FREQUENCY SPACING ACROSS INPUT CHANNELS Test Conditions/Comments Channel datapaths bypassed (1× interpolation), single-DAC mode, 16-bit resolution Channel datapaths bypassed (1× interpolation), dual DAC mode, 16-bit resolution Channel datapaths bypassed (1× interpolation), dual DAC mode, 12-bit resolution 1 complex channel enabled 2 complex channels enabled 3 complex channels enabled 1 complex channel enabled (0.8 × fDATA) 2 complex channels enabled (0.8 × fDATA) 3 complex channels enabled (0.8 × fDATA) Channel summing node = 1.575 GHz, channel interpolation rate > 1× fDAC = 12.6 GHz, main interpolation rate > 1× Maximum NCO output frequency × 0.8 Min Typ Max Unit 6160 MSPS 3080 MSPS 4100 MSPS 1540 770 385 MSPS MSPS MSPS -770 -6.3 1232 MHz 616 MHz 308 MHz 1540 MHz 12.6 GHz +770 MHz +6.3 GHz 1232 MHz 1 Values listed for these parameters are the maximum possible when considering all JESD204B modes of operation. Some modes are more limiting, based on other parameters. Rev. B | Page 13 of 145 AD9172 Data Sheet AC SPECIFICATIONS AVDD1.0 = 1.0 V, AVDD1.8 = 1.8 V, DVDD1.0 = 1.0 V, DVDD1.8 = 1.8 V, SVDD1.0 = 1.0 V, and DAC output full-scale current (IOUTFS) = 20 mA, unless otherwise noted. For the minimum and maximum, TJ = -40°C to +118°C. For the typical values, TA = 25°C, which corresponds to TJ = 51°C. Table 9. Parameter SPURIOUS-FREE DYNAMIC RANGE (SFDR) Single Tone, fDAC = 12000 MSPS, Mode 1 (L = 2, M = 4) fOUT = 100 MHz fOUT = 500 MHz fOUT = 950 MHz fOUT = 1840 MHz fOUT = 2650 MHz fOUT = 3700 MHz Single Tone, fDAC = 6000 MSPS, Mode 0 (L = 1, M = 2) fOUT = 100 MHz fOUT = 500 MHz fOUT = 950 MHz fOUT = 1840 MHz fOUT = 2650 MHz Single Tone, fDAC = 3000 MSPS, Mode 10 (L = 8, M = 2) fOUT = 100 MHz fOUT = 500 MHz fOUT = 950 MHz Single-Band Application--Band 3 (1805 MHz to 1880 MHz) SFDR Harmonics In-Band Digital Predistortion (DPD) Band Second Harmonic Third Harmonic Fourth and Fifth Harmonic SFDR Nonharmonics In-Band DPD Band ADJACENT CHANNEL LEAKAGE RATIO 4C-WCDMA fDAC = 1200 MSPS, Mode 1 (L = 2, M = 4) fDAC = 6000 MSPS, Mode 0 (L = 1, M = 2) THIRD-ORDER INTERMODULATION DISTORTION fDAC = 12000 MSPS, Mode 1 (L = 2, M = 4) fDAC = 6000 MSPS, Mode 0 (L = 1, M = 2) Test Conditions/Comments -7 dBFS, shuffle enabled -7 dBFS, shuffle enabled -7 dBFS, shuffle enabled Mode 0, 2× to 8×, fDAC = 6000 MSPS, 368.64 MHz reference clock -7 dBFS, shuffle enabled DPD bandwidth = data rate × 0.8 -7 dBFS, shuffle enabled -1 dBFS digital backoff fOUT = 1840 MHz fOUT = 2650 MHz fOUT = 3500 MHz fOUT = 1840 MHz fOUT = 2650 MHz Two-tone test, -7 dBFS/tone, 1 MHz spacing fOUT = 1840 MHz fOUT = 2650 MHz fOUT = 3700 MHz fOUT = 1840 MHz fOUT = 2650 MHz Min Typ Max Unit -81 dBc -80 dBc -75 dBc -80 dBc -75 dBc -67 dBc -85 dBc -85 dBc -78 dBc -75 dBc -69 dBc -87 dBc -84 dBc -81 dBc -82 dBc -80 dBc -82 dBc -80 dBc -95 dBc -74 dBc -74 dBc -70 dBc -68 dBc -66 dBc -71 dBc -66 dBc -83 dBc -85 dBc -77 dBc -74 dBc -72 dBc Rev. B | Page 14 of 145 Data Sheet AD9172 Parameter NOISE SPECTRAL DENSITY (NSD) Single Tone, fDAC = 12000 MSPS fOUT = 200 MHz fOUT = 500 MHz fOUT = 950 MHz fOUT = 1850 MHz fOUT = 2150 MHz Single Tone, fDAC = 6000 MSPS fOUT = 200 MHz fOUT = 500 MHz fOUT = 950 MHz fOUT = 1850 MHz fOUT = 2150 MHz Single Tone, fDAC = 3000 MSPS fOUT = 200 MHz fOUT = 500 MHz fOUT = 950 MHz SINGLE-SIDEBAND PHASE NOISE OFFSET 1 kHz 10 kHz 100 kHz 600 kHz 1.2 MHz 1.8 MHz 6 MHz DAC TO DAC OUTPUT ISOLATION Dual Band--fDAC = 12000 MSPS, Mode 1 (L = 2, M = 4) Test Conditions/Comments 0 dBFS, NSD measurement taken at 10% away from fOUT, shuffle on Min Typ Max Unit -163 -163 -162 -160 -158 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz -164 -163 -161 -157 -155 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz Loop filter component values according to Figure 86 are as follows: C1 = 22 nF, R1 = 232 , C2 = 2.4 nF, C3 = 33 nF; PFD frequency = 500 MHz, fOUT = 1.8 GHz, fDAC = 12 GHz Taken using the AD9172-FMC-EBZ evaluation board -163 -159 -155 dBc/Hz dBc/Hz dBc/Hz -97 -105 -114 -126 -133 -137 -148 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz fOUT = 1840 MHz fOUT = 2650 MHz fOUT = 3700 MHz -77 dB -70 dB -68 dB Rev. B | Page 15 of 145 AD9172 ABSOLUTE MAXIMUM RATINGS Table 10. Parameter ISET, FILT_COARSE, FILT_BYP, FILT_VCM SERDINx± SYNCOUT0±, SYNCOUT1±, RESET, TXEN0, TXEN1, IRQ0, IRQ1, CS, SCLK, SDIO, SDO DAC0±, DAC1±, CLKIN±, CLKOUT±, FILT_FINE SYSREF± AVDD1.0, DVDD1.0, SVDD1.0 to GND AVDD1.8, DVDD1.8 to GND Maximum Junction Temperature (TJ)1 Storage Temperature Range Reflow Rating -0.3 V to AVDD1.8 + 0.3 V -0.2 V to SVDD1.0 + 0.2 V -0.3 V to DVDD1.8 + 0.3 V -0.2 V to AVDD1.0 + 0.2 V -0.2 V to DVDD1.0 + 0.2 V -0.2 V to +1.2 V -0.3 V to 2.2 V 118°C -65°C to +150°C 260°C 1 Some operating modes of the device may cause the device to approach or exceed the maximum junction temperature during operation at supported ambient temperatures. Removal of heat from the device may require additional measures such as active airflow, heat sinks, or other measures. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. REFLOW PROFILE The AD9172 reflow profile is in accordance with the JEDEC JESD20 criteria for Pb-free devices. The maximum reflow temperature is 260°C. Data Sheet THERMAL CHARACTERISTICS Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. JA is the natural convection junction to ambient thermal resistance measured in a one cubic foot sealed enclosure. JC is the junction to case thermal resistance. Thermal resistances and thermal characterization parameters are specified vs. the number of PCB layers in different airflow velocities (in m/sec). The use of appropriate thermal management techniques is recommended to ensure that the maximum junction temperature does not exceed the limits shown in Table 10. Use the values in Table 11 in compliance with JEDEC 51-12. Table 11. Simulated Thermal Resistance vs. PCB Layers1 Airflow Velocity PCB Type (m/sec) JA JC_TOP JC_BOT Unit JEDEC 0.0 2s2p 1.0 Board 2.5 25.3 2.43 3.04 °C/W 22.6 N/A N/A °C/W 21.0 N/A N/A °C/W 12-Layer 0.0 PCB2 1.0 15.4 2.4 2.6 °C/W 13.1 N/A N/A °C/W 2.5 11.6 N/A N/A °C/W 1 N/A means not applicable. 2 Non JEDEC thermal resistance. 3 1SOP PCB with no vias in PCB. 4 1SOP PCB with 7 × 7 standard JEDEC vias. ESD CAUTION Rev. B | Page 16 of 145 Data Sheet AD9172 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 A GND SERDIN7+ SERDIN6+ SERDIN5+ SERDIN4+ GND GND SERDIN3+ SERDIN2+ SERDIN1+ SERDIN0+ GND B GND SERDIN7 SERDIN6 SERDIN5 SERDIN4 GND GND SERDIN3 SERDIN2 SERDIN1 SERDIN0 GND C SVDD1.0 SVDD1.0 GND GND SVDD1.0 DVDD1.8 SVDD1.0 SVDD1.0 GND GND SVDD1.0 SVDD1.0 D SYNCOUT1+ SYNCOUT1 DVDD1.8 TXEN1 GND SVDD1.0 GND TXEN0 IRQ0 DVDD1.8 SYNCOUT0 SYNCOUT0+ E DNC DNC DVDD1.8 SDO SCLK CS SDIO RESET IRQ1 DVDD1.8 DNC DNC F GND GND GND DAVDD1.0 DVDD1.0 DVDD1.0 DVDD1.0 DVDD1.0 DAVDD1.0 GND GND GND G GND GND GND GND GND GND GND GND GND GND H SYSREF+ SYSREF AVDD1.0 AVDD1.0 FILT_ AVDD1.0 FILT_FINE COARSE AVDD1.0 AVDD1.0 AVDD1.0 GND GND J GND DNC GND GND GND AVDD1.0 FILT_BYP GND GND GND GND GND CLKIN CLKIN+ K CLKOUT+ GND AVDD1.8 DNC AVDD1.8 FILT_VCM AVDD1.8 GND GND AVDD1.8 GND GND L CLKOUT GND AVDD1.8 GND GND AVDD1.8 AVDD1.8 GND GND AVDD1.8 GND ISET M GND AVDD1.0 GND DAC1+ DAC1 GND GND DAC0 DAC0+ GND AVDD1.0 GND 15453-002 GROUND 1.0V ANALOG SUPPLY 1.8V ANALOG SUPPLY DNC = DO NOT CONNECT SERDES INPUT SYSREF±/SYNCOUTx± 1.0V SERDES SUPPLY 1.0V DIGITAL SUPPLY 1.0V D/A SUPPLY 1.8V DIGITAL SUPPLY DAC PLL LOOP FILTER PINS DAC RF OUTPUTS RF CLOCK PINS Figure 2. Pin Configuration CMOS I/O REFERENCE Table 12. Pin Function Descriptions Pin No. 1.0 V Supply H3, H4, H5, H8 to H10, J6, M2, M11 F5 to F8 F4, F9 C1, C2, C5, C7, C8, C11, C12, D6 1.8 V Supply K3, K5, K7, K10, L3, L6, L7, L10 C6, D3, D10, E3, E10 Mnemonic Description AVDD1.0 DVDD1.0 DAVDD1.0 SVDD1.0 1.0 V Clock and Analog Supplies. These pins supply the clock receivers, clock distribution, the on-chip DAC clock multiplier, and the DAC analog core. Clean power supply rail sources are required on these pins. 1.0 V Digital Supplies. These pins supply power to the DAC digital circuitry. Clean power supply rail sources are required on these pins. 1.0 V Digital to Analog Supplies. These pins can share a supply rail with the DVDD1.0 supply (electrically connected) but must have separate supply plane and decoupling capacitors for the PCB layout to improve isolation for these two pins. Clean power supply rail sources are required on these pins. 1.0 V SERDES Supplies to the JESD204B Data Interface. Clean power supply rail sources are required on these pins. AVDD1.8 DVDD1.8 1.8 V Analog Supplies to the On-Chip DAC Clock Multiplier and the DAC Analog Core. Clean power supply rail sources are required on these pins. 1.8 V Digital Supplies to the JESD204B Data Interface and the Other Input/Output Circuitry, Such as the Serial Port Interface (SPI). Clean power supply rail sources are required on these pins. Rev. B | Page 17 of 145 AD9172 Data Sheet Pin No. Ground A1, A6, A7, A12, B1, B6, B7, B12, C3, C4, C9, C10, D5, D7, F1 to F3, F10 to F12, G1 to G12, H11, J1, J3 to J5, J8 to J11, K2, K8, K9, K11, K12, L2, L4, L5, L8, L9, L11, M1, M3, M6, M7, M10, M12 RF Clock J12 H12 K1 L1 System Reference H1 H2 On-Chip DAC PLL Loop Filter H6 H7 J7 K6 SERDES Data Bits A2 B2 A3 B3 A4 B4 A5 B5 A8 B8 A9 B9 A10 B10 A11 B11 Sync Output D12 D11 D1 D2 Mnemonic GND CLKIN+ CLKIN- CLKOUT+ CLKOUT- SYSREF+ SYSREF- FILT_FINE FILT_COARSE FILT_BYP FILT_VCM SERDIN7+ SERDIN7- SERDIN6+ SERDIN6- SERDIN5+ SERDIN5- SERDIN4+ SERDIN4- SERDIN3+ SERDIN3- SERDIN2+ SERDIN2- SERDIN1+ SERDIN1- SERDIN0+ SERDIN0- SYNCOUT0+ SYNCOUT0- SYNCOUT1+ SYNCOUT1- Description Device Common Ground. Positive Device Clock Input. This pin is the clock input for the on-chip DAC clock multiplier, REFCLK, when the DAC PLL is on. This pin is also the clock input for the DAC sample clock or device clock (DACCLK) when the DAC PLL is off. AC couple this input. There is an internal 100 resistor between this pin and CLKIN-. Negative Device Clock Input. Positive Device Clock Output. This pin is the clock output of a divided down DACCLK and is available with the DAC PLL on and off. The divide down ratios are by 1, 2, or 4. Negative Device Clock Output. Positive System Reference Input. It is recommended to ac couple this pin, but dc coupling is also acceptable. See the SYSREF± specifications for the dc common-mode voltage. Negative System Reference Input. It is recommended to ac couple this pin, but dc coupling is also acceptable. See the SYSREF± specifications for the dc common-mode voltage. On-Chip DAC Clock Multiplier and PLL Fine Loop Filter Input. On-Chip DAC Clock Multiplier and PLL Coarse Loop Filter Input. On-Chip DAC Clock Multiplier and LDO Bypass. On-Chip DAC Clock Multiplier and VCO Common-Mode Input. SERDES Data Bit 7, Positive. SERDES Data Bit 7, Negative. SERDES Data Bit 6, Positive. SERDES Data Bit 6, Negative. SERDES Data Bit 5, Positive. SERDES Data Bit 5, Negative. SERDES Data Bit 4, Positive. SERDES Data Bit 4, Negative. SERDES Data Bit 3, Positive. SERDES Data Bit 3, Negative. SERDES Data Bit 2, Positive. SERDES Data Bit 2, Negative. SERDES Data Bit 1, Positive. SERDES Data Bit 1, Negative. SERDES Data Bit 0, Positive. SERDES Data Bit 0, Negative. Positive Sync (Active Low) Output Signal, Channel Link 0. This pin is LVDS or CMOS selectable. Negative Sync (Active Low) Output Signal, Channel Link 0. This pin is LVDS or CMOS selectable. Positive Sync (Active Low) Output Signal, Channel Link 1. This pin is LVDS or CMOS selectable. Negative Sync (Active Low) Output Signal, Channel Link 1. This pin is LVDS or CMOS selectable. Rev. B | Page 18 of 145 Data Sheet Pin No. Serial Port Interface E4 E7 E5 E6 E8 Interrupt Request D9 E9 CMOS Input/Outputs D8 D4 DAC Analog Outputs M9 M8 M4 M5 Reference L12 Do Not Connect E1, E2, E11, E12, J2, K4 AD9172 Mnemonic Description SDO SDIO SCLK CS RESET Serial Port Data Output (CMOS Levels with Respect to DVDD1.8). Serial Port Data Input/Output (CMOS Levels with Respect to DVDD1.8). Serial Port Clock Input (CMOS Levels with Respect to DVDD1.8). Serial Port Chip Select, Active Low (CMOS Levels with Respect to DVDD1.8). Reset, Active Low (CMOS Levels with Respect to DVDD1.8). IRQ0 Interrupt Request 0. This pin is an open-drain, active low output (CMOS levels with respect to DVDD1.8). Connect a pull-up resistor to DVDD1.8 to prevent this pin from floating when inactive. IRQ1 Interrupt Request 1. This pin is an open-drain, active low output (CMOS levels with respect to DVDD1.8). Connect a pull-up resistor to DVDD1.8 to prevent this pin from floating when inactive. TXEN0 TXEN1 Transmit Enable for DAC0. The CMOS levels are determined with respect to DVDD1.8. Transmit Enable for DAC1. The CMOS levels are determined with respect to DVDD1.8. DAC0+ DAC0- DAC1+ DAC1- DAC0 Positive Current Output. DAC0 Negative Current Output. DAC1 Positive Current Output. DAC1 Negative Current Output. ISET Device Bias Current Setting Pin. Connect a 5 k resistor from this pin to GND, preferably with <0.1% tolerance and <±25 ppm/°C temperature coefficient. DNC Do Not Connect. Do not connect to these pins. Rev. B | Page 19 of 145 AD9172 TYPICAL PERFORMANCE CHARACTERISTICS 0 0dBFS 7dBFS 12dBFS 20 17dBFS 40 SFDR (dBc) 60 80 100 15453-103 120 0 500 1000 1500 2000 2500 3000 3500 fOUT (MHz) Figure 3. Second Harmonic (SFDR) vs. fOUT over Digital Scale (Mode 0), 6 GHz DAC Sample Rate, Channel Interpolation 2×, Main Interpolation 8× 0 0dBFS 7dBFS 12dBFS 20 17dBFS 40 SFDR (dBc) 60 80 100 15453-104 120 0 500 1000 1500 2000 2500 3000 3500 fOUT (MHz) Figure 4. Third Harmonic (SFDR) vs. fOUT over Digital Scale (Mode 0), 6 GHz DAC Sample Rate, Channel Interpolation 2×, Main Interpolation 8× SFDR (dBc) 0 0dBFS 10 7dBFS 12dBFS 20 17dBFS 30 40 50 60 70 80 90 100 0 500 1000 1500 2000 2500 3000 3500 fOUT (MHz) Figure 5. Worst Harmonic (SFDR) vs. fOUT over Digital Scale (Mode 0), 6 GHz DAC Sample Rate, Channel Interpolation 2×, Main Interpolation 8× 15453-105 WORST SPUR (dBc) SFDR (dBc) SFDR (dBc) Data Sheet 15453-106 0 0dBFS 7dBFS 12dBFS 20 17dBFS 40 60 80 100 120 0 1000 2000 3000 4000 fOUT (MHz) 5000 6000 7000 Figure 6. Second Harmonic (SFDR) vs. fOUT over Digital Scale (Mode 1), 12 GHz DAC Sample Rate, Channel Interpolation 4×, Main Interpolation 8× 0 0dBFS 7dBFS 20 12dBFS 17dBFS 40 60 80 100 120 0 1000 2000 3000 4000 fOUT (MHz) 5000 6000 7000 Figure 7. Third Harmonic (SFDR) vs. fOUT over Digital Scale (Mode 1), 12 GHz DAC Sample Rate, Channel Interpolation 4×, Main Interpolation 8× 0 20 MODE MODE MODE MODE 1: 1: 1: 1: ffffDDDDAAAACCCC = = = = 2949.12MHz 9830.4MHz 5898.24MHz 11796.48MHz MODE MODE MODE MODE 2: 2: 2: 2: ffffDDDDAAAACCCC = = = = 2949.12MHz 9830.4MHz 5898.24MHz 11796.48MHz 40 MODE MODE MODE 9: 9: 9: fffDDDAAACCC = = = 2949.12MHz 9830.4MHz 5898.24MHz 60 80 100 0 1000 2000 3000 4000 fOUT (MHz) 5000 6000 Figure 8. Worst Spur vs. fOUT over fDAC (All Modes), 0 dB Digital Scale 15453-107 15453-108 Rev. B | Page 20 of 145 Data Sheet 0 0dBFS 7dBFS 12dBFS 20 17dBFS 40 SFDR (dBc) 60 80 100 120 0 1000 2000 3000 4000 fOUT (MHz) 5000 6000 7000 Figure 9. Second Harmonic (SFDR) vs. fOUT over Digital Scale (Mode 2), 12 GHz DAC Sample Rate, Channel Interpolation 4×, Main Interpolation 8× 0 0dBFS 7dBFS 20 12dBFS 17dBFS 40 SFDR (dBc) 60 80 100 120 140 0 1000 2000 3000 4000 fOUT (MHz) 5000 6000 7000 Figure 10. Third Harmonic (SFDR) vs. fOUT over Digital Scale (Mode 2), 12 GHz DAC Sample Rate, Channel Interpolation 4×, Main Interpolation 8× 0 0dBFS 10 7dBFS 12dBFS 17dBFS 20 30 40 50 60 70 80 15453-111 90 0 1000 2000 3000 4000 fOUT (MHz) 5000 6000 7000 Figure 11. Worst Harmonic (SFDR) vs. fOUT over Digital Scale (Mode 2), 12 GHz DAC Sample Rate, Channel Interpolation 4×, Main Interpolation 8× SFDR (dBc) 15453-110 SFDR (dBc) 15453-109 SFDR (dBc) AD9172 0 0dBFS 7dBFS 12dBFS 20 17dBFS 40 60 80 100 15453-112 120 0 500 1000 1500 fOUT (MHz) 2000 Figure 12. Second Harmonic (SFDR) vs. fOUT over Digital Scale (Mode 12), 4 GHz DAC Sample Rate, Channel Interpolation 1×, Main Interpolation 1×, 12-Bit Resolution 0 0dBFS 7dBFS 12dBFS 20 17dBFS 40 60 80 100 15453-113 120 0 500 1000 1500 fOUT (MHz) 2000 Figure 13. Third Harmonic (SFDR) vs. fOUT over Digital Scale (Mode 12), 4 GHz DAC Sample Rate, Channel Interpolation 1×, Main Interpolation 1×, 12-Bit Resolution 0 0dBFS 10 7dBFS 12dBFS 17dBFS 20 30 40 SFDR (dBc) 50 60 70 80 90 15453-114 100 0 500 1000 1500 fOUT (MHz) 2000 Figure 14. Worst Harmonic (SFDR) vs. fOUT over Digital Scale (Mode 12), 4 GHz DAC Sample Rate, Channel Interpolation 1×, Main Interpolation 1×, 12-Bit Resolution Rev. B | Page 21 of 145 AD9172 SFDR (dBc) SFDR (dBc) 0 0dBFS 7dBFS 12dBFS 20 17dBFS 40 60 80 100 15453-115 120 0 1000 2000 3000 4000 fOUT (MHz) 5000 6000 7000 Figure 15. Second Harmonic (SFDR) vs. fOUT over Digital Scale (Mode 9), 12 GHz DAC Sample Rate, Channel Interpolation 1×, Main Interpolation 8× 0 0dBFS 7dBFS 12dBFS 20 17dBFS 40 60 80 100 15453-116 120 0 1000 2000 3000 4000 fOUT (MHz) 5000 6000 7000 Figure 16. Third Harmonic (SFDR) vs. fOUT over Digital Scale (Mode 9), 12 GHz DAC Sample Rate, Channel Interpolation 1×, Main Interpolation 8× 0 7dBFS 12dBFS 17dBFS 20 20dBFS 40 IMD3 (dBc) 60 80 100 15453-117 120 0 500 1000 1500 2000 2500 3000 fOUT (MHz) Figure 17. IMD3 vs. fOUT over Digital Scale (Mode 0) 6 GHz DAC Sample Rate, Channel Interpolation 2×, Main Interpolation 8×, 1 MHz Tone Spacing Data Sheet 0 fDAC = 2949.12MHz 10 fDAC = 5898.24MHz 20 30 IMD3 (dBc) 40 50 60 70 80 15453-118 90 100 0 200 400 600 800 1000 1200 1400 fOUT (MHz) Figure 18. IMD3 vs. fOUT over fDAC (Mode 0), Channel Interpolation 2×, Main Interpolation 8×, 1 MHz Tone Spacing 0 7dBFS 10 12dBFS 17dBFS 20dBFS 20 30 IMD3 (dBc) 40 50 60 70 80 90 15453-119 100 0 1000 2000 3000 4000 fOUT (MHz) 5000 6000 7000 Figure 19. IMD3 vs. fOUT over Digital Scale (Mode 1), 12 GHz DAC Sample Rate, Channel Interpolation 4×, Main Interpolation 8×, 1 MHz Tone Spacing 0 fDAC = 2949.12MHz 10 fDAC = 5898.24MHz fDAC = 9830.4MHz 20 fDAC = 11796.48MHz 30 IMD3 (dBc) 40 50 60 70 80 90 15453-120 100 0 1000 2000 3000 4000 fOUT (MHz) 5000 6000 7000 Figure 20. IMD3 vs. fOUT over fDAC (Mode 1), Channel Interpolation 4×, Main Interpolation 8×, 1 MHz Tone Spacing, -7 dB Digital Scale Rev. B | Page 22 of 145 Data Sheet 0 7dBFS 10 12dBFS 17dBFS 20 20dBFS 30 IMD3 (dBc) 40 50 60 70 80 90 15453-121 100 1000 2000 3000 4000 fOUT (MHz) 5000 6000 7000 Figure 21. IMD3 vs. fOUT over Digital Scale (Mode 2), 12 GHz DAC Sample Rate, Channel Interpolation 4×, Main Interpolation 8×, 1 MHz Tone Spacing 0 fDAC = 2949.12MHz 0 fDAC = 5898.24MHz 10 fDAC = 9830.4MHz fDAC = 11796.48MHz 20 30 IMD3 (dBc) 40 50 60 70 80 90 100 0 1000 2000 3000 4000 fOUT (MHz) 5000 6000 7000 Figure 22. IMD3 vs. fOUT over fDAC (Mode 2), Channel Interpolation 4×, Main Interpolation 8×, 1 MHz Tone Spacing 0 7dBFS 12dBFS 17dBFS 20 20dBFS 40 IMD3 (dBc) 60 80 100 120 0 500 1000 1500 fOUT (MHz) 2000 Figure 23. IMD3 vs. fOUT over Digital Scale (Mode 12), 4 GHz DAC Sample Rate, Channel Interpolation 1×, Main Interpolation 1×, 1 MHz Tone Spacing, 12-Bit Resolution 15453-123 NSD (dBc/Hz) 15453-122 NSD (dBc/Hz) AD9172 0 7dBFS 10 12dBFS 17dBFS 20dBFS 20 30 IMD3 (dBc) 40 50 60 70 80 90 15453-124 100 0 1000 2000 3000 4000 fOUT (MHz) 5000 6000 7000 Figure 24. IMD3 vs. fOUT over Digital Scale (Mode 9), 12 GHz DAC Sample Rate, Channel Interpolation 1×, Main Interpolation 8×, 1 MHz Tone Spacing 130 135 SHUFFLE OFF SHUFFLE ON 140 145 150 155 160 165 15453-201 170 0 500 1000 1500 2000 2500 fOUT (MHz) Figure 25. Single-Tone NSD Measured at 70 MHz vs. fOUT, 11796.48 MHz fDAC, 16-Bit Resolution, Shuffle Off vs. Shuffle On 130 135 fDAC = 5898.24MHz fDAC = 9830.4MHz fDAC = 11796.48MHz 140 145 150 155 160 165 15453-202 170 0 500 1000 1500 2000 2500 fOUT (MHz) Figure 26. Single-Tone NSD Measured at 70 MHz vs. fOUT over fDAC, 16-Bit Resolution, Shuffle On Rev. B | Page 23 of 145 AD9172 130 135 140 fDAC = 5898.24MHz fDAC = 9830.4MHz fDAC = 11796.48MHz NSD (dBc/Hz) 145 150 155 160 165 15453-203 170 0 500 1000 1500 2000 2500 fOUT (MHz) Figure 27. Single-Tone NSD Measured at 10% Offset from fOUT vs. fOUT over fDAC, 16-Bit Resolution, Shuffle On 130 135 SHUFFLE OFF SHUFFLE ON 140 NSD (dBc/Hz) 145 150 155 160 165 170 0 500 1000 1500 2000 2500 fOUT (MHz) Figure 28. Single-Tone NSD Measured at 70 MHz vs fOUT, 11796.48 MHz fDAC, 12-Bit Resolution, Shuffle Off vs. Shuffle On 130 135 140 fDAC = 5898.24MHz fDAC = 9830.4MHz fDAC = 11796.48MHz 145 150 155 160 165 170 0 500 1000 1500 2000 2500 fOUT (MHz) Figure 29. Single-Tone NSD Measured at 70 MHz vs. fOUT over fDAC, 12-Bit Resolution, Shuffle On 15453-205 SSB PHASE NOISE (dBc) 15453-304 SSB PHASE NOISE (dBc) Data Sheet 130 135 140 fDAC = 5898.24MHz fDAC = 9830.4MHz fDAC = 11796.48MHz 145 150 155 160 165 15453-206 170 0 500 1000 1500 2000 2500 fOUT (MHz) Figure 30. Single-Tone NSD Measured at 10% Offset from fOUT vs. fOUT over fDAC, 12-Bit Resolution, Shuffle On 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 10 PLL OFF (DIRECT CLOCK) PLL ON (PFD = 122.88MHz) PLL ON (PFD = 245.76MHz) PLL ON (PFD = 368.64MHz) PLL ON (PFD = 491.52MHz) 100 1k 10k 100k 1M FREQUENCY OFFSET (Hz) 10M 100M 15453-100 Figure 31. Single-Sideband (SSB) Phase Noise vs. Offset over fOUT, over PFD Frequency, fDAC = 12 GHz, fOUT = 1.8 GHz, PLL On, PLL Reference Clock = 500 MHz 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 10 fOUT = 900MHz fOUT = 1.8GHz fOUT = 3.6GHz 100 1k 10k 100k 1M FREQUENCY OFFSET (Hz) 10M 100M 15453-101 Figure 32. SSB Phase Noise vs. Frequency Offset over fOUT, fDAC = 12 GHz, Direct Clock (PLL Off) Rev. B | Page 24 of 145 Data Sheet 16-BIT DNL (LSB) 16-BIT INL (LSB) 6 DAC1 DAC0 5 4 3 2 1 0 1 0 10000 20000 30000 40000 50000 60000 70000 CODE Figure 33. DNL, IOUTFS = 26 mA, 16-Bit Resolution 5 DAC1 4 DAC0 3 2 1 0 1 2 3 4 5 0 10000 20000 30000 40000 50000 60000 70000 CODE Figure 34. INL, IOUTFS = 26 mA, 16-Bit Resolution 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0.5 1.0 0 DAC1 DAC0 10000 20000 30000 40000 Code 50000 60000 Figure 35. DNL, IOUTFS = 20 mA, 16-Bit Resolution 70000 16-BIT DNL (LSB) 15453-210 16-BIT INL (LSB) 15453-209 16-BIT DNL (LSB) 15453-208 16-BIT INL (LSB) AD9172 15453-211 5 DAC1 DAC0 4 3 2 1 0 1 2 3 4 0 10000 20000 30000 40000 CODE 50000 60000 70000 Figure 36. INL, IOUTFS = 20 mA, 16-Bit Resolution 2.5 DAC1 DAC0 2.0 1.5 1.0 0.5 0 0.5 1.0 0 10000 20000 30000 40000 50000 60000 70000 Figure 37. DNL, IOUTFS = 15.6 mA, 16-Bit Resolution 4 DAC1 DAC0 3 2 1 0 1 2 3 0 10000 20000 30000 40000 CODE 50000 60000 70000 Figure 38. INL, IOUTFS = 15.6 mA, 16-Bit Resolution 15453-212 15453-213 Rev. B | Page 25 of 145 12-BIT DNL (LSB) 15453-214 12-BIT INL (LSB) 15453-215 AD9172 0.15 0.11 DAC1 DAC0 0.07 0.03 0.01 0.05 0.09 0.13 0 500 1000 1500 2000 2500 3000 3500 4000 4500 CODE Figure 39. DNL, IOUTFS = 20 mA, 12-Bit Resolution Data Sheet 0.20 0.15 0.10 0.05 0 0.05 0.10 0.15 0.20 0.25 0.30 0 DAC1 DAC0 500 1000 1500 2000 2500 3000 3500 4000 4500 CODE Figure 40. INL, IOUTFS = 20 mA, 12-Bit Resolution Rev. B | Page 26 of 145 Data Sheet TERMINOLOGY Integral Nonlinearity (INL) INL is the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. Differential Nonlinearity (DNL) DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. Offset Error Offset error is the deviation of the output current from the ideal value of 0 mA. For DACx+, a 0 mA output is expected when all inputs are set to 0. For DACx-, a 0 mA output is expected when all inputs are set to 1. Gain Error Gain error is the difference between the actual and ideal output span. The actual span is determined by the difference between the output when the input is at its minimum code and the output when the input is at its maximum code. Output Compliance Range The output compliance range is the range of allowable voltages at the output of a current output DAC. Operation beyond the maximum compliance limits can cause either output stage saturation or breakdown, resulting in nonlinear performance. Temperature Drift Temperature drift is specified as the maximum change from the ambient (25°C) value to the value at either TMIN or TMAX. For offset and gain drift, the drift is reported in ppm of full-scale range (FSR) per degree Celsius. For reference drift, the drift is reported in ppm per degree Celsius. Settling Time Settling time is the time required for the output to reach and remain within a specified error band around its final value, measured from the start of the output transition. Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels, between the peak amplitude of the output signal and the peak spurious signal within the dc to Nyquist frequency of the DAC. Typically, energy in this band is rejected by the interpolation filters. This specification, therefore, defines how well the interpolation filters work and the effect of other parasitic coupling paths on the DAC output. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels. AD9172 Interpolation Filter If the digital inputs to the DAC are sampled at a multiple rate of the interpolation rate (fDATA), a digital filter can be constructed that has a sharp transition band near fDATA/2. Images that typically appear around the output data rate (fDAC) can be greatly suppressed. Channel Datapath The channel datapath, sometimes referred to as channelizers, are the complex data channel datapaths, before the summing node in the chip, that can be used or bypassed depending on the mode of operation chosen. When these channelizers are in use, complex data input is required. The channel datapaths include independently controlled optional gain stages and channel NCOs per channel. There is also a selectable channel interpolation block that is configurable (same setting for all channel interpolation blocks) depending on the mode of operation chosen. Main Datapath The main datapath refers to the portion of the digital datapath after the summing node in the chip, up to each of the main DAC analog cores. Each of these main datapaths includes an optional PA protection block with a feed forward to the ramp up/down gain stage block for muting the DAC outputs before damaging a power amplifier in the transmit path. There is a selectable main interpolation block that is configurable (same setting for both main interpolation blocks) depending on the mode of operation chosen. Each main datapath also contains an individually programmable main NCO per main DAC datapath that can be optionally used depending on the mode of operation. Adjacent Channel Leakage Ratio (ACLR) ACLR is the ratio in decibels relative to the carrier (dBc) between the measured power within a channel relative to its adjacent channel. Adjusted DAC Update Rate The adjusted DAC update rate is the DAC update rate divided by the smallest interpolating factor. For clarity on DACs with multiple interpolating factors, the adjusted DAC update rate for each interpolating factor may be given. Physical (PHY) Lane Physical Lane x refers to SERDINx±. Logical Lane Logical Lane x refers to physical lanes after optionally being remapped by the crossbar block (Register 0x308 to Register 0x30B). Link Lane Link Lane x refers to logical lanes considered per link. When paging Link 0 (Register 0x300[2] = 0), Link Lane x = Logical Lane x. When paging Link 1 (Register 0x300[2] = 1, dual link only), Link Lane x = Logical Lane x + 4. Rev. B | Page 27 of 145 AD9172 THEORY OF OPERATION The AD9172 is a 16-bit, dual RF DAC with a high speed JESD204B SERDES interface, compliant with Subclass 0 and Subclass 1 operation. Figure 1 shows a functional block diagram of the AD9172. Each DAC core has three individually bypassable channelizers that support up to 1.5 GSPS of complex data rate input per channel. Eight high speed serial lanes carry data at a maximum of 15 Gbps to the channel datapaths. The JESD204B interface supports both single-link and dual-link modes of operation, depending on the selected mode configuration. Compared to either LVDS or CMOS interfaces, the SERDES interface simplifies pin count, board layout, and input clock requirements to the device. The clock for the input data is derived from the DAC clock, or device clock (required by the JESD204B specification). This device clock can be sourced with a PLL reference clock used by the on-chip PLL to generate a DAC clock, or a high fidelity, direct external DAC sampling clock. The device can be configured to operate in one-, two-, three-, four-, or eight-lane per link modes, depending on the required input data rate. The digital datapath of the AD9172 offers bypassable (1×) interpolation modes for both the channel datapaths and the main datapaths. Additionally, depending on the selected mode, there are also 2×, 3×, 4×, 6×, and 8× interpolation options for the channel datapaths, and 2×, 4×, 6×, 8×, and 12× interpolation options for the main datapaths. See Table 13 for a summary of the various JESD204B modes available, as well as the respective interpolation options. For each of the channel digital datapaths (when not using 1× interpolation for the channel), there are individually programmable gain stages and NCO blocks available. The NCO blocks have a 48-bit modulus NCO option to enable digital frequency shifts of signals with near infinite precision. The NCO can operate alone in NCO only mode using a programmable dc value input via Data Sheet the SPI or with digital data from the SERDES interface and digital datapath. At the end of the three channelizer datapaths, there is a summation node that combines the three channel datapaths together at a maximum of 1.5 GSPS to then pass along to each of the main DAC datapaths for further digital feature options. Each of the main DAC datapaths contain an optional power amplifier (PA) protection block, a main datapath interpolation block, a main NCO with an optional modulus feature, and a ramp-up/ramp-down gain block that is fed by the PA protection block. Additionally, there is an optional calibration tone feature, as well as four modulator switch modes that are part of the main NCO block. The AD9172 is capable of multichip synchronization that can both synchronize multiple DACs and establish a constant and deterministic latency (latency locking) path for the DACs. The latency for each of the DACs remains constant to within several DAC clock cycles from link establishment to link establishment. An external alignment signal (SYSREF±) makes the AD9172 JESD204B Subclass 1 compliant. Several modes of SYSREF± signal handling are available for use in the system. An SPI configures the various functional blocks and monitors their statuses. The various functional blocks and the data interface must be set up in a specific sequence for proper operation (see the Start-Up Sequence section). Simple SPI initialization routines set up the JESD204B link and are included in the evaluation board package. This data sheet describes the various blocks of the AD9172 in detail. Descriptions of the JESD204B interface, control parameters, and various registers to set up and monitor the device are provided. The recommended start-up routine reliably sets up the data link. Rev. B | Page 28 of 145 Data Sheet AD9172 Table 13. JESD204B Supported Operating Modes and Interpolation Combinations JESD204B Operation Modes Channel Datapath Application Link Modes JESD204B Lanes Modes per Link Channels per DAC Maximum Channel Data Rate (MSPS)1 Channel Interpolations Single-Channel, 375 MHz (N = 16 Bits) Single, 0 dual 1 1 385 2× 4×, 6× Dual-Channel, 375 MHz (N = 16 Bits) Single, 1 dual 2 2 385 4×, 6× Triple-Channel, 375 MHz (N = 16 Bits) Single, 2 dual 3 3 385 4×, 6× Single Channel, Single, 5 500 MHz (N = 12 dual Bits, NP = 12 Bits) 1 1 513 2× 3× Dual Channel, 500 MHz Single, 6 (N = 12 Bits, NP = dual 12 Bits) 2 2 513 3× Single Channel, 750 MHz (N = 16 Bits) Single, 3 dual 2 1 770 1× 2×, 3× Dual Channel, 750 MHz Single, 4 (N = 16 Bits) dual 4 2 770 2×, 3× 385 4× Dual Channel, 187 MHz Single, 7 (N = 16 Bits) dual 1 2 192.5 8× Single Channel, Single, 8, 9 4 1 1500 MHz, Dual Tx dual Cable (N = 16 Bits) 1540 1× Wideband, 3 GHz Single 10, 11 8 1 (N = 16 Bits, NP = 16 Bits) 3080 1× Wideband, 4 GHz Single 12 8 1 (N = 12 Bits, NP = 12 Bits) 4100 1× 3 GHz, Real DAC (N = Single, 18, 19 4 1 16 Bits, NP = 16 Bits) dual 3080 1× 6 GHz, Real DAC (N = Single 20, 21 8 1 16 Bits, NP = 16 Bits) 6160 1× Main DAC Datapath Main Datapath Interpolations 8× 6×, 8× 6×, 8× Maximum DAC Rate (GSPS)2 6.16 12.6 12.6 6×, 8× 12.6 6× 6.16 6×, 8× 12.6 6×, 8× 12.6 8× 6.16 6×, 8× 12.6 6×, 8× 12.6 8× 12.6 6×, 8× 12.6 2×, 4×, 6×, 8×, 12.6 12× 1× 3.08 1× 4.1 1× 3.08 1× 6.16 1 The maximum data rate is calculated based on a maximum lane rate as listed in Table 7. The data rate is calculated based on the formula lane rate = (10/8) × NP × data rate × (M/L), where the NP, M, and L values depend on the selected mode. 2 The maximum DAC rate per mode depends on the voltage tolerance as well as the lane rate for a given configuration, as listed in Table 3. The maximum possible lane rate is according to Table 7. Rev. B | Page 29 of 145 AD9172 SERIAL PORT OPERATION The serial port is a flexible, synchronous serial communications port that allows easy interfacing with many industry-standard microcontrollers and microprocessors. The serial input/output is compatible with most synchronous transfer formats, including both the Motorola, Inc., SPI and Intel® SSR protocols. The interface allows read and write access to all registers that configure the AD9172. MSB first or LSB first transfer formats are supported. The serial port interface can be configured as a 4-wire interface or a 3-wire interface in which the input and output share a single pin input/output (SDIO). SDO E4 SDIO E7 SCLK E5 CS E6 SPI PORT 15453-009 Figure 41. Serial Port Interface Pins (144-Ball BGA_ED) There are two phases to a communication cycle with the AD9172. Phase 1 is the instruction cycle (the writing of an instruction byte into the device), coincident with the first 16 SCLK rising edges. The instruction word provides the serial port controller with information regarding the data transfer cycle, Phase 2 of the communication cycle. The Phase 1 instruction word defines whether the upcoming data transfer is a read or write, along with the starting register address for the following data transfer. A logic high on the CS pin followed by a logic low resets the serial port timing to the initial state of the instruction cycle. From this state, the next 16 rising SCLK edges represent the instruction bits of the current input/output operation. The remaining SCLK edges are for Phase 2 of the communication cycle. Phase 2 is the actual data transfer between the device and the system controller. Phase 2 of the communication cycle is a transfer of one or more data bytes. Eight × N SCLK cycles are required to transfer N bytes during the transfer cycle. Registers change immediately upon writing to the last bit of each transfer byte, except for the FTW and NCO phase offsets, which change only when the frequency tuning word load request bit (DDSM_FTW_LOAD_REQ or DDSC_FTW_LOAD_REQ) is set. DATA FORMAT The instruction byte contains the information shown in Table 14. Table 14. Serial Port Instruction Word I15 (MSB) I[14:0] R/W A[14:0] Data Sheet R/W, Bit 15 of the instruction word, determines whether a read or a write data transfer occurs after the instruction word write. Logic 1 indicates a read operation, and Logic 0 indicates a write operation. A14 to A0, Bit I14 to Bit I0 of the instruction word, determine the register that is accessed during the data transfer portion of the communication cycle. For multibyte transfers, A[14:0] is the starting address. The remaining register addresses are generated by the device based on the address increment bit. If the address increment bits are set high (Register 0x000, Bit 5 and Bit 2), multibyte SPI writes start on A[14:0] and increment by 1 every eight bits sent/received. If the address increment bits are set to 0, the address decrements by 1 every eight bits. SERIAL PORT PIN DESCRIPTIONS Serial Clock (SCLK) The serial clock pin synchronizes data to and from the device and runs the internal state machines. The maximum frequency of SCLK is 80 MHz. All data input is registered on the rising edge of SCLK. All data is driven out on the falling edge of SCLK. Chip Select (CS) An active low input starts and gates a communication cycle. CS allows more than one device to be used on the same serial communications lines. The SDIO pin goes to a high impedance state when this input is high. During the communication cycle, the chip select must stay low. Serial Data Input/Output (SDIO) This pin is a bidirectional data line. In 4-wire mode, this pin acts as the data input and SDO acts as the data output. SERIAL PORT OPTIONS The serial port can support both MSB first and LSB first data formats. This functionality is controlled by the LSB first bit (Register 0x000, Bit 6 and Bit 1). The default is MSB first (LSBFIRST bit = 0). When the LSB first bits = 0 (MSB first), the instruction and data bits must be written from MSB to LSB. R/W is followed by A[14:0] as the instruction word, and D[7:0] is the data-word. When the LSB first bits = 1 (LSB first), the opposite is true. A[0:14] is followed by R/W, which is subsequently followed by D[0:7]. The serial port supports a 3-wire or 4-wire interface. When the SDO active bits = 1 (Register 0x000, Bit 4 and Bit 3), a 4-wire interface with a separate input pin (SDIO) and output pin (SDO) is used. When the SDO active bits = 0, the SDO pin is unused and the SDIO pin is used for both the input and the output. Rev. B | Page 30 of 145 Data Sheet Multibyte data transfers can be performed as well by holding the CS pin low for multiple data transfer cycles (eight SCLKs) after the first data transfer word following the instruction cycle. The first eight SCLKs following the instruction cycle read from or write to the register provided in the instruction cycle. For each additional eight SCLK cycles, the address is either incremented or decremented and the read/write occurs on the new register. The direction of the address can be set using ADDRINC or ADDRINC_M (Register 0x000, Bit 5 and Bit 2). When ADDRINC or ADDRINC_M is 1, the multicycle addresses are incremented. When ADDRINC or ADDRINC_M is 0, the addresses are decremented. A new write cycle can always be initiated by bringing CS high and then low again. To prevent confusion and to ensure consistency between devices, the chip tests the first nibble following the address phase, ignoring the second nibble. This test is completed independently from the LSB first bits and ensures that there are extra clock cycles following the soft reset bits (Register 0x000, Bit 0 and Bit 7). This test of the first nibble only applies when writing to Register 0x000. AD9172 15453-010 CS SCLK INSTRUCTION CYCLE DATA TRANSFER CYCLE SDIO R/W A14 A13 A3 A2 A1 A0 D7N D6N D5N D30 D20 D10 D00 Figure 42. Serial Register Interface Timing, MSB First, Register 0x000, Bit 6 and Bit 1 = 0 DATA TRANSFER CYCLE 15453-011 Figure 43. Serial Register Interface Timing, LSB First, Register 0x000, Bit 6 and Bit 1 = 1 CS SCLK SDIO tDV DATA BIT n DATA BIT n 1 Figure 44. Timing Diagram for Serial Port Register Read 15453-012 CS SCLK SDIO tS tH tPWH tPWL tDS tDH INSTRUCTION BIT 15 INSTRUCTION BIT 14 INSTRUCTION BIT 0 Figure 45. Timing Diagram for Serial Port Register Write 15453-013 Rev. B | Page 31 of 145 AD9172 Data Sheet JESD204B SERIAL DATA INTERFACE JESD204B OVERVIEW The AD9172 has eight JESD204B data ports that receive data. The eight JESD204B ports can be configured as part of a single or dual JESD204B link that uses a single system reference (SYSREF±) and device clock (CLKIN±). The JESD204B serial interface hardware consists of three layers: the physical layer, the data link layer, and the transport layer. These sections of the hardware are described in subsequent sections, including information for configuring every aspect of the interface. Figure 46 shows the communication layers implemented in the AD9172 serial data interface to recover the clock and deserialize, descramble, and deframe the data before it is sent to each of the digital signal processing channelizers of the device. The physical layer establishes a reliable channel between the transmitter (Tx) and the receiver (Rx), and the data link layer is responsible for unpacking the data into octets and descrambling the data. The transport layer receives the descrambled JESD204B frames and converts them to DAC samples. A number of JESD204B parameters (L, F, K, M, N, NP, S, HD) define how the data is packed and tell the device how to turn the serial data into samples. These parameters are defined in detail in the Transport Layer section. The AD9172 also has a descrambling option (see the Descrambler section for more information). The AD9172 has the ability to use 12-bit packing mode (NP = 12, N = 11 or 12) to increase the maximum data rate achievable by this device for applications that do not require 16-bit resolution capabilities. The AD9172 has multiple single-link and dual-link mode options available for various application purposes. These modes and their respective JESD204B link parameters are described in Table 15 and Table 16. There are different interpolation combinations available for the channel and main datapaths, as well as whether single-link and dual-link options are available SYNCOUT0± SYNCOUT1± SERDIN0± PHYSICAL LAYER DESERIALIZER DATA LINK LAYER SERDIN7± DESERIALIZER QBD/ DESCRAMBLER depending on which JESD204B mode is chosen. Table 13 lists the possible link and interpolation combinations available. The AD9172 has two DAC outputs; however, for the purposes of complex signal processing on chip, the converter count, represented by the M JESD204B parameter, reflects the number of complex subchannels of data required per link when using a total interpolation greater than 1×. The number of complex subchannels of data per link required to be sent to the device also depends on the number of channelizers being used, based on the mode of operation chosen. If the channelizer datapaths are bypassed (channel interpolation is set to 1×) and the main datapath interpolation is set to 1×, the converter count (M) reflects the number of real converters per link being used in the mode of operation; in this case, complex data is not required. For a particular JESD204B mode of operation, the following relationships exist: Total Interpolation = Channel Interpolation × Main Interpolation Data Rate = DAC Rate/Total Interpolation Lane Rate = (M/L) × NP × (10/8) × Data Rate where: Lane Rate must be between 3 Gbps and 15 Gbps. M, L, and NP are JESD204B link parameters for the chosen JESD204B operating mode. Achieving and recovering synchronization of the lanes is important. To simplify the interface to the transmitter, the AD9172 designates a master synchronization signal for each JESD204B link. The SYNCOUT0± and SYNCOUT1± pins are used as the master signal for all lanes on each link. If any lane in a link loses synchronization, a resynchronization request is sent to the transmitter via the synchronization signal of the link. The transmitter stops sending data and instead sends synchronization characters to all lanes in that link until resynchronization is achieved. TRANSPORT LAYER FRAME TO SAMPLES I DATA[15:0] Q DATA[15:0] COMPLEX DATA PER CHANNELIZER 15453-014 SYSREF± Figure 46. Functional Block Diagram of Serial Link Receiver Rev. B | Page 32 of 145 Data Sheet AD9172 Table 15. Single-Link JESD204B Operating Modes Single-Link JESD204B Modes Parameter 0 1 2 3 4 5 6 7 8 9 10 11 12 18 19 20 21 L (Lane Count) 1 2 3 2 4 1 2 1 4 4 8 8 8 4 4 8 8 M (Converter Count) 2 4 6 2 4 2 4 4 2 2 2 2 2 1 1 1 1 F (Octets per Frame per Lane) 4 4 4 2 2 3 3 8 1 2 1 2 3 1 2 1 2 S (Samples per Converter per Frame) 1 1 1 1 1 1 1 1 1 2 2 4 8 2 4 4 8 NP (Total Number of Bits per Sample) 16 16 16 16 16 12 12 16 16 16 16 16 12 16 16 16 16 N (Converter Resolution) 16 16 16 16 16 12 12 16 16 16 16 16 12 16 16 16 16 K (Frames per Multiframe) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 HD (High Density User Data Format) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Table 16. Dual-Link JESD204B Operating Modes Dual-Link JESD204B Modes Parameter 0 1 2 3 4 5 6 7 8 9 18 19 L (Lane Count) 1 2 3 2 4 1 2 1 4 4 4 4 M (Converter Count) 2 4 6 2 4 2 4 4 2 2 1 1 F (Octets per Frame per Lane) 4 4 4 2 2 3 3 8 1 2 1 2 S (Samples per Converter per Frame) 1 1 1 1 1 1 1 1 1 2 2 4 NP (Total Number of Bits per Sample) 16 16 16 16 16 12 12 16 16 16 16 16 N (Converter Resolution) 16 16 16 16 16 12 12 16 16 16 16 16 K (Frames per Multiframe) 32 32 32 32 32 32 32 32 32 32 32 32 HD (High Density User Data Format) 1 1 1 1 1 1 1 1 1 1 1 1 Table 17. Data Structure per Lane for F = 1 JESD204B Operating Modes1 JESD204B Mode and Parameters Link Logical Lane L = 4, M = 4, S = 1, NP = 16, N = 16 Lane 0 Mode 8: N = 16 Mode 13: N = 112 Lane 1 Lane 2 Lane 3 Mode 10 (L = 8, M = 2, S = 2, NP = 16, N = 16) Lane 0 Lane 1 Lane 2 Lane 3 Lane 4 Lane 5 Lane 6 Lane 7 Mode 18 (L = 4, M = 1, S = 2, NP = 16, N = 16) Lane 0 Lane 1 Lane 2 Lane 3 Mode 20 (L = 8, M = 1, S = 4, NP = 16, N = 16) Lane 0 Lane 1 Lane 2 Lane 3 Lane 4 Lane 5 Lane 6 Lane 7 1 Mx is the converter number and Sy is the sample number. For example, M0S0 means Converter 0, Sample 0. 2 Generate 11 bit resolution data and set Bits[4:0] to 0 for the full 16-bit data packing (NP). Frame 0, Octet 0 M0S0[15:8] M0S0[7:0] M1S0[15:8] M1S0[7:0] M0S0[15:8] M0S0[7:0] M0S1[15:8] M0S1[7:0] M1S0[15:8] M1S0[7:0] M1S1[15:8] M1S1[7:0] M0S0[15:8] M0S0[7:0] M0S1[15:8] M0S1[7:0] M0S0[15:8] M0S0[7:0] M0S1[15:8] M0S1[7:0] M0S2[15:8] M0S2[7:0] M0S3[15:8] M0S3[7:0] Rev. B | Page 33 of 145 Frame 1, Octet 0 M0S1[15:8] M0S1[7:0] M1S1[15:8] M1S1[7:0] M0S2[15:8] M0S2[7:0] M0S3[15:8] M0S3[7:0] M1S2[15:8] M1S2[7:0] M1S3[15:8] M1S3[7:0] M0S2[15:8] M0S2[7:0] M0S3[15:8] M0S3[7:0] M0S4[15:8] M0S4[7:0] M0S5[15:8] M0S5[7:0] M0S6[15:8] M0S6[7:0] M0S7[15:8] M0S7[7:0] AD9172 Data Sheet Table 18. Data Structure per Lane for F = 2 JESD204B Operating Modes1 Frame 0 JESD204B Mode and Parameters Link Logical Lane Octet 0 Octet 1 Mode 3 (L = 2, M = 2, S = 1, NP = 16, N = 16) Lane 0 M0S0[15:8] M0S0[7:0] Lane 1 M1S0[15:8] M1S0[7:0] Mode 4 (L = 4, M = 4, S = 1, NP = 16, N = 16) Lane 0 M0S0[15:8] M0S0[7:0] Lane 1 M1S0[15:8] M1S0[7:0] Lane 2 M2S0[15:8] M2S0[7:0] Lane 3 M3S0[15:8] M3S0[7:0] Mode 9 (L = 4, M = 2, S = 2, NP = 16, N = 16) Lane 0 M0S0[15:8] M0S0[7:0] Lane 1 M0S1[15:8] M0S1[7:0] Lane 2 M1S0[15:8] M1S0[7:0] Lane 3 M1S1[15:8] M1S1[7:0] Mode 11 (L = 8, M = 2, S = 4, NP = 16, N = 16) Lane 0 M0S0[15:8] M0S0[7:0] Lane 1 M0S1[15:8] M0S1[7:0] Lane 2 M0S2[15:8] M0S2[7:0] Lane 3 M0S3[15:8] M0S3[7:0] Lane 4 M1S0[15:8] M1S0[7:0] Lane 5 M1S1[15:8] M1S1[7:0] Lane 6 M1S2[15:8] M1S2[7:0] Lane 7 M1S3[15:8] M1S3[7:0] Mode 19 (L = 4, M = 1, S = 4, NP = 16, N = 16) Lane 0 M0S0[15:8] M0S0[7:0] Lane 1 M0S1[15:8] M0S1[7:0] Lane 2 M0S2[15:8] M0S2[7:0] Lane 3 M0S3[15:8] M0S3[7:0] Mode 21 (L = 8, M = 1, S = 8, NP = 16, N = 16) Lane 0 M0S0[15:8] M0S0[7:0] Lane 1 M0S1[15:8] M0S1[7:0] Lane 2 M0S2[15:8] M0S2[7:0] Lane 3 M0S3[15:8] M0S3[7:0] Lane 4 M0S4[15:8] M0S4[7:0] Lane 5 M0S5[15:8] M0S5[7:0] Lane 6 M0S6[15:8] M0S6[7:0] Lane 7 M0S7[15:8] M0S7[7:0] 1 Mx is the converter number and Sy is the sample number. For example, M0S0 means Converter 0, Sample 0. Frame 1 Octet 0 Octet 2 M0S1[15:8] M0S1[7:0] M1S1[15:8] M1S1[7:0] M0S1[15:8] M0S1[7:0] M1S1[15:8] M1S1[7:0] M2S1[15:8] M2S1[7:0] M3S1[15:8] M3S1[7:0] M0S2[15:8] M0S2[7:0] M0S3[15:8] M0S3[7:0] M1S2[15:8] M1S2[7:0] M1S3[15:8] M1S3[7:0] M0S4[15:8] M0S4[7:0] M0S5[15:8] M0S5[7:0] M0S6[15:8] M0S6[7:0] M0S7[15:8] M0S7[7:0] M1S4[15:8] M1S4[7:0] M1S5[15:8] M1S5[7:0] M1S6[15:8] M1S6[7:0] M1S7[15:8] M1S7[7:0] M0S4[15:8] M0S4[7:0] M0S5[15:8] M0S5[7:0] M0S6[15:8] M0S6[7:0] M0S7[15:8] M0S7[7:0] M0S8[15:8] M0S8[7:0] M0S9[15:8] M0S9[7:0] M0S10[15:8] M0S10[7:0] M0S11[15:8] M0S11[7:0] M0S12[15:8] M0S12[7:0] M0S13[15:8] M0S13[7:0] M0S14[15:8] M0S14[7:0] M0S15[15:8] M0S15[7:0] Table 19. Data Structure per Lane for F = 3 JESD204B Operating Modes1 JESD204B Mode and Parameters Mode 5 (L = 1, M = 2, S = 1, NP = 12, N = 12) Mode 6 (L = 2, M = 4, S = 1, NP = 12, N = 12) Mode 12 (L = 8, M = 2, S = 8, NP = 12, N = 12) Link Logical Lane Lane 0 Lane 0 Lane 1 Lane 0 Lane 1 Lane 2 Lane 3 Lane 4 Lane 5 Lane 6 Lane 7 Octet 0 Nibble 0 Nibble1 M0S0[11:8] M0S0[7:4] M0S0[11:8] M2S0[11:8] M0S0[11:8] M0S2[11:8] M0S4[11:8] M0S6[11:8] M1S0[11:8] M1S2[11:8] M1S4[11:8] M1S6[11:8] M0S0[7:4] M2S0[7:4] M0S0[7:4] M0S2[7:4] M0S4[7:4] M0S6[7:4] M1S0[7:4] M1S2[7:4] M1S4[7:4] M1S6[7:4] Frame 0 Octet 1 Nibble 0 Nibble1 M0S0[3:0] M1S0[11:8] Octet 2 Nibble 0 Nibble1 M1S0[7:4] M1S0[3:0] M0S0[3:0] M2S0[3:0] M0S0[3:0] M0S2[3:0] M0S4[3:0] M0S6[3:0] M1S0[3:0] M1S2[3:0] M1S4[3:0] M1S6[3:0] M1S0[11:8] M3S0[11:8] M0S1[11:8] M0S3[11:8] M0S5[11:8] M0S7[11:8] M1S1[11:8] M1S3[11:8] M1S5[11:8] M1S7[11:8] M1S0[7:4] M3S0[7:4] M0S1[7:4] M0S3[7:4] M0S5[7:4] M0S7[7:4] M1S1[7:4] M1S3[7:4] M1S5[7:4] M1S7[7:4] M1S0[3:0] M3S0[3:0] M0S1[3:0] M0S3[3:0] M0S5[3:0] M0S7[3:0] M1S1[3:0] M1S3[3:0] M1S5[3:0] M1S7[3:0] 1 Mx is the converter number and Sy is the sample number. For example, M0S0 means Converter 0, Sample 0. Rev. B | Page 34 of 145 Data Sheet AD9172 Table 20. Data Structure per Lane for F = 4 JESD204B Operating Modes1 JESD204B Mode and Parameters Link Logical Lane Octet 0 Frame 0 Octet 1 Octet 2 Mode 0 (L = 1, M = 2, S = 1, Lane 0 NP = 16, N = 16) M0S0[15:8] M0S0[7:0] M1S0[15:8] Mode 1 (L = 2, M = 4, S = 1, Lane 0 NP = 16, N = 16) Lane 1 M0S0[15:8] M0S0[7:0] M1S0[15:8] M2S0[15:8] M2S0[7:0] M3S0[15:8] Mode 2 (L = 3, M = 6, S = 1, Lane 0 NP = 16, N = 16) Lane 1 M0S0[15:8] M2S0[15:8] M0S0[7:0] M1S0[15:8] M2S0[7:0] M3S0[15:8] Lane 2 M4S0[15:8] M4S0[7:0] M5S0[15:8] Octet 3 M1S0[7:0] M1S0[7:0] M3S0[7:0] M1S0[7:0] M3S0[7:0] M5S0[7:0] Octet 0 M0S1[15:8] M0S1[15:8] M2S1[15:8] M0S1[15:8] M2S1[15:8] M4S1[15:8] Frame 1 Octet 1 Octet 2 M0S1[7:0] M1S1[15:8] M0S1[7:0] M2S1[7:0] M0S1[7:0] M2S1[7:0] M4S1[7:0] M1S1[15:8] M3S1[15:8] M1S1[15:8] M3S1[15:8] M5S1[15:8] Octet 3 M1S1[7:0] M1S1[7:0] M3S1[7:0] M1S1[7:0] M3S1[7:0] M5S1[7:0] 1 Mx is the converter number and Sy is the sample number. For example, M0S0 means Converter 0, Sample 0. Table 21. Data Structure per Lane for F = 8 JESD204B Operating Modes1 JESD204B Mode and Parameters Mode 7 (L = 1, M = 4, S = 1, NP = 16, N = 16) Link Logical Lane Octet 0 Octet 1 Lane 0 M0S0[15:8] M0S0[7:0] Octet 2 M1S0[15:8] Frame 0 Octet 3 Octet 4 M1S0[7:0] M2S0[15:8] Octet 5 M2S0[7:0] Octet 6 M3S0[15:8] 1 Mx is the converter number and Sy is the sample number. For example, M0S0 means Converter 0, Sample 0. Octet 7 M3S0[7:0] PHYSICAL LAYER The physical layer of the JESD204B interface, hereafter referred to as the deserializer, has eight identical channels. Each channel consists of the termination, an equalizer, a clock and data recovery (CDR) circuit, and the 1:40 demux function (see Figure 47). DESERIALIZER SERDINx± TERMINATION EQUALIZER CDR 1:40 SPI CONTROL FROM SERDES PLL Figure 47. Deserializer Block Diagram JESD204B data is input to the AD9172 via the SERDINx± differential input pins, per the JESD204B specification. Interface Power-Up and Input Termination Before using the JESD204B interface, it must be powered up by setting Register 0x200, Bit 0 = 0. In addition, each physical lane (PHY) that is not being used (SERDINx±) must be powered down. To do so, set the corresponding Bit x for Physical Lane x in Register 0x201 to 0 if the physical lane is being used, and to 1 if it is not being used. The AD9172 autocalibrates the input termination to 50 . This calibration routine is performed automatically when the JESD204B interface blocks are configured and does not require any additional SPI register writes. 15453-015 AMPLITUDE (mV) 15453-016 Receiver Eye Mask The AD9172 is compatible with the JESD204B specification regarding the receiver eye mask and is capable of capturing data that complies with the mask in Figure 48. Figure 48 shows the receiver eye normalized to the data rate interval. The AD9172 also supports an increased insertion loss limit, as defined in the Equalization section. RECEIVER EYE MASK 525 55 0 55 525 0 0.35 0.5 0.65 1.00 TIME (UI) Figure 48. Receiver Eye Mask Rev. B | Page 35 of 145 AD9172 Data Sheet Clock Relationships The following clocks rates are used throughout the rest of the JESD204B section. The relationship between any of the clocks can be derived from the following equations: Data Rate = DAC Rate/Total Interpolation Lane Rate = (M/L) × NP × (10/8) × Data Rate Byte Rate = Lane Rate/10 This relationship comes from 8-bit/10-bit encoding, where each byte is represented by 10 bits. PCLK Rate = Byte Rate/4 The processing clock is used for a quad-byte decoder. Frame Rate = Byte Rate/F where F is defined as octets per frame per lane. PCLK Factor = Frame Rate/PCLK Rate = 4/F where: M is the JESD204B parameter for converters per link. L is the JESD204B parameter for lanes per link. F is the JESD204B parameter for octets per frame per lane. NP is the JESD204B parameter for the total number of bits per sample. SERDES PLL Functional Overview of the SERDES PLL The independent SERDES PLL uses integer N techniques to achieve clock synthesis. The entire SERDES PLL is integrated on chip, including the VCO and the loop filter. The SERDES PLL is capable of providing quadrature clocks to allow a wide range of data rates (3 Gbps to 15 Gbps) with no gaps. These clocks are the input to the CDR block that is described in the Clock and Data Recovery section. The reference clock to the SERDES PLL is always running at a frequency, fREF, that is equal to 1/40 of the lane rate (PCLK rate). For more information about the SERDES circuitry setup and relevant register writes, see the Start-Up Sequence section. The SERDES PLL block automatically tunes to the appropriate divider range for the lane rate based on the SERDES mode being used. It takes the DAC clock generated by either the DAC PLL, if in use, or from the direct clock being sourced at the CLKIN± pins, divides the DAC clock frequency by 4, and uses the JESD204B parameters corresponding to the mode and interpolation values programmed in Register 0x110 and Register 0x111 to determine the proper dividers for generating the PCLK frequency (lane rate ÷ 40), as shown in Figure 49. Confirm that the SERDES PLL is working by reading Register 0x281. If Register 0x281, Bit 0 = 1, the SERDES PLL has locked. JESD204B MODE (REGISTER 0x110, BITS[4:0]) DATAPATH INTERPOLATION (REGISTER 0x111, BITS[7:4]) CHANNEL INTERPOLATION (REGISTER 0x111, BITS[3:0]) DIRECT DAC CLOCK DAC PLL CLOCK SERDES PLL ÷4 PCLK GENERATOR WITH INTERNAL VCO LANE RATES 3Gbps TO 15.4Gbps CDR HALF RATE CLOCKS Figure 49. SERDES PLL Synthesizer Block Diagram Including VCO Divider Block 15453-017 Rev. B | Page 36 of 145 INSERTION LOSS (dB) 15453-018 ATTENUATION (dB) Data Sheet Clock and Data Recovery The deserializer is equipped with a CDR circuit. Instead of recovering the clock from the JESD204B serial lanes, the CDR recovers the clocks from the SERDES PLL. The CDR circuit synchronizes the phase used to sample the data on each serial lane independently. This independent phase adjustment per serial interface ensures accurate data sampling and eases the implementation of multiple serial interfaces on a PCB. Power-Down Unused PHYs Note that any unused physical and enabled lanes consume extra power unnecessarily. Each lane that is not being used (SERDINx±) must be powered off by writing a 1 to the corresponding bit of PHY_PD (Register 0x201). Equalization To compensate for signal integrity distortions for each PHY channel due to PCB trace length and impedance, the AD9172 employs an easy to use, low power equalizer on each JESD204B channel. The AD9172 equalizers operating at the maximum lane rate of 15 Gbps can compensate for up to 16 dB of insertion loss. This equalizer performance is shown in Figure 50 for 15 Gbps, near the maximum baud rate for the AD9172. The channel must also meet the insertion loss deviation requirement of the JESD204B specification (less than 1.5 dB from 50 MHz to 0.75 times the baud rate). EXAMPLE OF JESD204B COMPLIANT CHANNEL MINIMUM ALLOWED CHANNEL LOSS (JESD204B SPEC) EXAMPLE OF AD9172 COMPATIBLE CHANNEL MINIMUM ALLOWED CHANNEL LOSS AD9172 3.75 7.5 11.25 FREQUENCY (GHz) Figure 50. Insertion Loss Allowed To ensure the AD9172 compensates for the amount of insertion loss in the system, set the equalizer block appropriately. Table 22 shows the settings for the equalizer boost, equalizer gain, and feedback controls, depending on the level of insertion loss in the system. The equalizer boost setting is programmed for each PHY lane (2-bit control for each) being used in Register 0x240 and Register 0x241. Similarly, the equalizer gain settings are programmed for each PHY lane (2-bit control for each) used in Register 0x242 and Register 0x243. The feedback control is programmed per PHY lane (5-bit control for each, one control per register) in Register 0x244 to Register 0x24B. AD9172 Table 22. Equalizer Register Control Settings per PHY Control Insertion Loss 11 dB >11 dB Equalizer Boost 0x02 0x03 Equalizer Gain 0x01 0x03 Feedback 0x1F 0x1F Figure 51 and Figure 52 are provided as points of reference for hardware designers and show the insertion loss for various lengths of well laid out stripline and microstrip transmission lines, respectively. See the Hardware Considerations section for specific layout recommendations for the JESD204B channel. 15453-019 STRIPLINE = 6" STRIPLINE = 10" STRIPLINE = 15" STRIPLINE = 20" STRIPLINE = 25" STRIPLINE = 30" Figure 51. Insertion Loss of 50 Striplines on FR4 6" MICROSTRIP 10" MICROSTRIP 15" MICROSTRIP 20" MICROSTRIP 25" MICROSTRIP 30" MICROSTRIP FREQUENCY (GHz) Figure 52. Insertion Loss of 50 Microstrips on FR4 15453-020 Rev. B | Page 37 of 145 AD9172 DATA LINK LAYER The data link layer of the AD9172 JESD204B interface accepts the deserialized data from the PHYs and deframes and descrambles them so that data octets are presented to the transport layer to be put into DAC samples. The architecture of the data link layer is shown in Figure 53. The data link layer consists of a synchronization FIFO for each lane, a crossbar switch, a deframer, and a descrambler. The AD9172 can operate as a single-link or dual-link high speed JESD204B serial data interface. All eight lanes of the JESD204B interface handle link layer communications such as code group synchronization (CGS), frame alignment, and frame synchronization. Data Sheet The AD9172 decodes 8-bit/10-bit control characters, allowing marking of the start and end of the frame and alignment between serial lanes. Each AD9172 serial interface link can issue a synchronization request by setting its SYNCOUTx± signals low. The synchronization protocol follows Section 4.9 of the JESD204B standard. When a stream of four consecutive /K/ symbols is received, the AD9172 deactivates the synchronization request by setting the SYNCOUTx± signals high at the next internal LMFC rising edge. Then, the AD9172 waits for the transmitter to issue an initial lane alignment sequence (ILAS). During the ILAS, all lanes are aligned using the /A/ to /R/ character transition as described in theJESD204B Serial Link Establishment section. Elastic buffers hold early arriving lane data until the alignment character of the latest lane arrives. At this point, the buffers for all lanes are released and all lanes are aligned (see Figure 54). SYNCOUTx± LANE 0 DESERIALIZED AND DESCRAMBLED DATA LANE 0 DATA CLOCK SERDIN0± FIFO LANE 7 DESERIALIZED AND DESCRAMBLED DATA LANE 7 DATA CLOCK SERDIN7± FIFO DATA LINK LAYER QUAD-BYTE DEFRAMER QBD CROSSBAR SWITCH LANE 0 OCTETS LANE 7 OCTETS 8-BIT/10-BIT DECODE DESCRAMBLE 15453-021 SYSREF± PCLK SPI CONTROL SYSTEM CLOCK PHASE DETECT Figure 53. Data Link Layer Block Diagram L RECEIVE LANES (EARLIEST ARRIVAL) K K K R D D DDARQC C DDARDD L RECEIVE LANES (LATEST ARRIVAL) K K K K K K K R D D DDARQC C DDARDD 0 CHARACTER ELASTIC BUFFER DELAY OF LATEST ARRIVAL 4 CHARACTER ELASTIC BUFFER DELAY OF EARLIEST ARRIVAL L ALIGNED RECEIVE LANES K K K K K K K R D D DDARQC C K = K28.5 CODE GROUP SYNCHRONIZATION COMMA CHARACTER A = K28.3 LANE ALIGNMENT SYMBOL F = K28.7 FRAME ALIGNMENT SYMBOL R = K28.0 START OF MULTIFRAME Q = K28.4 START OF LINK CONFIGURATION DATA C = JESD204x LINK CONFIGURATION PARAMETERS D = Dx.y DATA SYMBOL Figure 54. Lane Alignment During ILAS DDARDD 15453-022 Rev. B | Page 38 of 145 Data Sheet AD9172 JESD204B Serial Link Establishment A brief summary of the high speed serial link establishment process for Subclass 1 is provided. See Section 5.3.3 of the JESD204B specification document for complete details. Step 1--Code Group Synchronization Each receiver must locate /K/ (K28.5) characters in its input data stream. After four consecutive /K/ characters are detected on all link lanes, the receiver block deasserts the SYNCOUTx± signals to the transmitter block at the receiver LMFC edge. The transmitter captures the change in the SYNCOUTx± signals and at a future transmitter LMFC rising edge, starts the ILAS. Step 2--Initial Lane Alignment Sequence The main purposes of this phase are to align all the lanes of the link and to verify the parameters of the link. Before the link is established, write each of the link parameters to the receiver device to designate how data is sent to the receiver block. The ILAS consists of four or more multiframes. The last character of each multiframe is a multiframe alignment character, /A/. The first, third, and fourth multiframes are populated with predetermined data values. Note that Section 8.2 of the JESD204B specifications document describes the data ramp that is expected during the ILAS. The deframer uses the final /A/ of each lane to align the ends of the multiframes within the receiver. The second multiframe contains an /R/ (K.28.0), /Q/ (K.28.4), and then data corresponding to the link parameters. Additional multiframes can be added to the ILAS if needed by the receiver. By default, the AD9172 uses four multiframes in the ILAS (this can be changed in Register 0x478). If using Subclass 1, exactly four multiframes must be used. After the last /A/ character of the last ILAS, multiframe data begins streaming. The receiver adjusts the position of the /A/ character such that it aligns with the internal LMFC of the receiver at this point. Step 3--Data Streaming In this phase, data is streamed from the transmitter block to the receiver block. Optionally, data can be scrambled. Scrambling does not start until the first octet following the ILAS. The receiver block processes and monitors the data it receives for errors, including the following: · Bad running disparity (8-bit/10-bit error) · Not in table (8-bit/10-bit error) · Unexpected control character · Bad ILAS · Interlane skew error (through character replacement) If any of these errors exist, they are reported back to the transmitter in one of the following ways (see the JESD204B Error Monitoring section for details): · SYNCOUTx± signal assertion: resynchronization (SYNCOUTx± signals pulled low) is requested at each error for the last two errors. For the first three errors, an optional resynchronization request can be asserted when the error counter reaches a set error threshold. · For the first three errors, each multiframe with an error in it causes a small pulse on the respective SYNCOUTx± pins. · Errors can optionally trigger an interrupt request (IRQ) event, which can be sent to the transmitter. For more information about the various test modes for verifying the link integrity, see the JESD204B Test Modes section. Lane First In/First Out (FIFO) The FIFOs in front of the crossbar switch and deframer synchronize the samples sent on the high speed serial data interface with the deframer clock by adjusting the phase of the incoming data. The FIFO absorbs timing variations between the data source and the deframer; this allows up to two PCLK cycles of drift from the transmitter. The FIFO_STATUS_REG_0 register and FIFO_STATUS_REG_1 register (Register 0x30C and Register 0x30D, respectively) can be monitored to identify whether the FIFOs are full or empty. Lane FIFO IRQ An aggregate lane FIFO error bit is also available as an IRQ event. Use Register 0x020, Bit 2 to enable the lane FIFO error bit, and then use Register 0x024, Bit 2 to read back its status and reset the IRQ signal. See the Interrupt Request Operation section for more information. Crossbar Switch Register 0x308 to Register 0x30B allow arbitrary mapping of physical lanes (SERDINx±) to logical lanes used by the SERDES deframers. Table 23. Crossbar Registers Address Bits Logical Lane 0x308 [2:0] SRC_LANE0 0x308 [5:3] SRC_LANE1 0x309 [2:0] SRC_LANE2 0x309 [5:3] SRC_LANE3 0x30A [2:0] SRC_LANE4 0x30A [5:3] SRC_LANE5 0x30B [2:0] SRC_LANE6 0x30B [5:3] SRC_LANE7 Write each SRC_LANEy with the number (x) of the desired physical lane (SERDINx±) from which to obtain data. By default, all logical lanes use the corresponding physical lane as their data source. For example, by default, SRC_LANE0 = 0; therefore, Logical Lane 0 obtains data from Physical Lane 0 Rev. B | Page 39 of 145 AD9172 (SERDIN0±). To use SERDIN4± as the source for Logical Lane 0 instead, the user must write SRC_LANE0 = 4. Lane Inversion Register 0x334 allows inversion of desired logical lanes, which can be used to ease routing of the SERDINx± signals. For each Logical Lane x, set Bit x of Register 0x334 to 1 to invert it. Deframer The AD9172 consists of two quad-byte deframers (QBDs) paged by the LINK_PAGE control in Register 0x300, Bit 2. The deframer accepts the 8-bit/10-bit encoded data from the deserializer (via the crossbar switch), decodes it, and descrambles it into JESD204B frames before passing it to the transport layer to be converted to DAC samples. The deframer processes four symbols (or octets) per processing clock (PCLK) cycle. The deframer uses the JESD204B parameters that the user has programmed into the register map to identify how the data is packed, and unpacks it. The JESD204B parameters are described in detail in the Transport Layer section; many of the parameters are also needed in the transport layer to convert JESD204B frames into samples. Descrambler The AD9172 provides an optional descrambler block using a self synchronous descrambler with the following polynomial: 1 + x14 + x15. Enabling data scrambling reduces spectral peaks that are produced when the same data octets repeat from frame to frame. It also makes the spectrum data independent so that possible frequency selective effects on the electrical interface do not cause data dependent errors. Descrambling of the data is enabled by setting the SCR bit (Register 0x453, Bit 7) to 1. SYNCING LMFC SIGNALS The AD9172 requires a synchronization (sync) to align the LMFC and other internal clocks before the SERDES links are brought online. The synchronization is a one-shot sync, where the synchronization process begins on the next edge of the alignment signal following the assertion of the SYSREF_MODE_ ONESHOT control in Register 0x03A, Bit 1. In Subclass 1, the SYSREF± rising edge acts as the alignment edge; in Subclass 0, an internal processing clock acts as the alignment edge. When a sync has completed, the SYNC_ROTATION_DONE (Register 0x03A, Bit 4) bit is asserted and remains asserted until another sync is requested. After a synchronization occurs, the JESD204B link can be enabled. In Subclass 1, the latency of the JESD204B system is deterministic and allows synchronization across multiple devices, if desired. Data Sheet SYSREF± Signal The SYSREF± signal is a differential source synchronous input that synchronizes the LMFC signals in both the transmitter and receiver in a JESD204B Subclass 1 system to achieve deterministic latency. The SYSREF± signal is a rising edge sensitive signal that is sampled by the device clock rising edge. It is best practice that the device clock and SYSREF± signals be generated by the same source, such as the HMC7044 clock generator, so that the phase alignment between the signals is fixed. When designing for optimum deterministic latency operation, consider the timing distribution skew of the SYSREF± signal in a multipoint link system (multichip). The AD9172 supports a periodic SYSREF± signal. The periodicity can be continuous, strobed, or gapped periodic. The SYSREF± signal can be dc-coupled with a common-mode voltage of 0.6 V to 2.2 V and differential swing of 200 mV p-p to 1 V p-p. When dccoupled, a small amount of common-mode current (up to 0.3 mA) is drawn from the SYSREF± pins. See Figure 55 and Figure 56 for the SYSREF± internal circuit for dc-coupled and ac-coupled configurations. Ensure that the SYSREF_INPUTMODE bit (Register 0x084, Bit 6) is set to 1, dc-coupled, to prevent overstress on the SYSREF± receiver pins. DC SYSREF± MODE SYSREF+ SYSREF 240F 104 100 10.3k 10.3k 104 130k VCM 130k 15453-138 240F Figure 55. DC-Coupled SYSREF± Receiver Circuitry AC SYSREF± MODE SYSREF+ SYSREF 240F 104 10.3k 100 10.3k 130k 130k VCM 104 240F Figure 56. AC-Coupled SYSREF± Receiver Circuitry 15453-139 To avoid this common-mode current draw, the SYSREF± receiver can be ac-coupled using a 50% duty cycle periodic SYSREF± signal with ac coupling capacitors. If ac-coupled, the ac coupling capacitors combine with the resistors shown in Figure 56 to make a high-pass filter with an RC time constant of = RC. Select C such that > 4/SYSREF± frequency. In addition, the edge rate must be sufficiently fast to allow SYSREF± sampling clocks to correctly sample the rising SYSREF± edge before the next sample clock. Rev. B | Page 40 of 145 Data Sheet When ac coupling the SYSREF± inputs, ensure that the SYSREF_INPUTMODE bit (Register 0x084, Bit 6) is set to 0, ac-coupled, to enable the internal receiver biasing circuitry and prevent overstress on the SYSREF± receiver pins. AC coupling allows a differential voltage swing from 200 mV to 1 V on the SYSREF± pins. SYSREF± Sampling The SYSREF± signal is sampled by a divide by 4 version of the DAC clock. Therefore, the minimum pulse width of the SYSREF± signal must exceed 4 DAC clock periods to ensure accurate sampling. The delay between the SYSREF± and DAC clock input signal does not need to be timing constrained. By default, the first SYSREF± rising edge at the SYSREF± inputs that is detected after asserting the SYSREF_MODE_ONESHOT bit (Register 0x03A, Bit 1) begins the synchronization and aligns the internal LMFC signal with the sampled SYSREF± edge. Register 0x036 (SYSREF_COUNT) indicates how many captured SYSREF± edges are ignored after the SYSREF_MODE_ ONESHOT bit is asserted before the synchronization takes place. For example, if SYSREF_COUNT is set to 3, the AD9172 does not sync after the SYSREF_MODE_ONESHOT bit is asserted until the arrival of the 4th SYSREF± edge. SYSREF± Jitter IRQ In Subclass 1, after the one-shot synchronization occurs, the SYSREF± signal is monitored to ensure that the subsequent SYSREF± edges do not deviate from the internal LMFC clock by more than a target amount. Register 0x039 (SYSREF_ERR_WINDOW) indicates the size of the error window allowed, in DAC clock units. If a SYSREF± edge varies from the internal LMFC clock by more than the number of DAC clock units set in SYSREF_ERR_WINDOW, the IRQ_SYSREF_JITTER is asserted. Table 24. SYSREF± Jitter Window Tolerance SYSREF± Jitter Window SYSREF_ERR_WINDOW Tolerance (DAC Clock Cycles) (Register 0x039, Bits[5:0])1 ±½ 0x00 ±4 0x04 ±8 0x08 ±12 0x0C ±16 0x10 ±20 0x14 +24 0x18 ±28 0x1C 1 The two least significant digits are ignored because the SYSREF± signal is sampled with a divide by 4 version of the DAC clock. As a result, the jitter window is set by this divide by 4 clock rather than the DAC clock. It is recommended that at least a four-DAC clock SYSREF± jitter window be chosen. AD9172 The IRQ_SYSREF_JITTER can be configured as described in the Interrupt Request Operation section to indicate the SYSREF± signal has varied, and to request the SPI sequence for a sync be performed again. Sync Procedure The procedure for enabling the sync is as follows: 1. Set up the DAC and the SERDES PLL, and enable the CDR (see the Start-Up Sequence section). 2. Set Register 0x03B to 0xF1 to enable the synchronization circuitry. If using the soft on/off feature, set Register 0x03B to 0xF3 to ramp the datapath data before and after the synchronization. 3. If Subclass 1, configure the SYSREF± settings as follows: a. Set Register 0x039 (SYSREF± jitter window). See Table 24 for settings. b. Set Register 0x036 = SYSREF_COUNT; leave as 0 to bypass. 4. Perform a one-shot sync. a. Set Register 0x03A = 0x00. Clear one-shot mode if already enabled. b. Set Register 0x03A = 0x02. Enable one-shot sync mode. 5. If Subclass 1, send a SYSREF± edge. If pulse counting, multiple SYSREF± edges are required. Sending SYSREF± edges triggers the synchronization. 6. Read back the SYNC_ROTATION_DONE bit (Register 0x03A, Bit 4) to confirm the rotation occurred. Resynchronizing LMFC Signals If desired, the sync procedure can be repeated to realign the LMFC clock to the reference signal by repeating Step 2 to Step 6, described in the Sync Procedure section. When the one-shot sync is triggered (writing Register 0x03A = 0x02), the SYNCOUTx± signals deassert to drop the JESD204B links and reassert the links after the rotation completes. Deterministic Latency JESD204B systems contain various clock domains distributed throughout. Data traversing from one clock domain to a different clock domain can lead to ambiguous delays in the JESD204B link. These ambiguities lead to nonrepeatable latencies across the link from power cycle to power cycle with each new link establishment. Section 6 of the JESD204B specification addresses the issue of deterministic latency with mechanisms defined as Subclass 1 and Subclass 2. The AD9172 supports JESD204B Subclass 0 and Subclass 1 operation, but not Subclass 2. Write the subclass to Register 0x458, Bits[7:5]. Rev. B | Page 41 of 145 AD9172 Data Sheet Subclass 0 This mode gives deterministic latency to within several PCLK cycles. It does not require any signal on the SYSREF± pins, which can be left disconnected. Subclass 0 still requires that all lanes arrive within the same LMFC cycle and the dual DACs must be synchronized to each other. Subclass 1 This mode gives deterministic latency and allows the link to synchronize within a few DAC clock cycles. Across the full operating range, for both supply and temperature, it is within ±2.5 DAC clock periods for a 6 GHz DAC clock rate or ±4 DAC clock periods for a 12.6 GHz DAC clock rate. If the supply and the temperature stability are maintained, the link can be synchronized to within ±1.5 DAC clock periods for a 6 GHz DAC clock rate or ±2.5 DAC clock periods for a 12.6 GHz DAC clock rate. Achieving this latency requires an external, low jitter SYSREF± signal that is accurately phase aligned to the DAC clock. Deterministic Latency Requirements Several key factors are required for achieving deterministic latency in a JESD204B Subclass 1 system, as follows: The SYSREF± signal distribution skew within the system must be less than the desired uncertainty. The total latency variation across all lanes, links, and devices must be 12 PCLK periods, which includes both variable delays and the variation in fixed delays from lane to lane, link to link, and device to device in the system. LINK DELAY = DELAYFIXED + DELAYVARIABLE LOGIC DEVICE (JESD204B Tx) CHANNEL JESD204B Rx LMFC POWER CYCLE VARIANCE DATA AT Tx INPUT ILAS DATA ALIGNED DATA AT Rx OUTPUT ILAS DATA FIXED DELAY VARIABLE DELAY Figure 57. JESD204B Link Delay = Fixed Delay + Variable Delay 15453-023 Rev. B | Page 42 of 145 Data Sheet AD9172 Link Delay The link delay of a JESD204B system is the sum of the fixed and variable delays from the transmitter, channel, and receiver as shown in Figure 57. For proper functioning, all lanes on a link must be read during the same LMFC period. Section 6.1 of the JESD204B specification states that the LMFC period must be larger than the maximum link delay. For the AD9172, this is not necessarily the case; instead, the AD9172 use a local LMFC for each link (LMFCRx) that can be delayed from the SYSREF± aligned LMFC. Because the LMFC is periodic, this delay can account for any amount of fixed delay. As a result, the LMFC period must only be larger than the variation in the link delays, and the AD9172 can achieve proper performance with a smaller total latency. Figure 58 and Figure 59 show a case where the link delay is greater than an LMFC period. Note that it can be accommodated by delaying LMFCRx. POWER CYCLE VARIANCE LMFC 15453-024 ALIGNED DATA ILAS EARLY ARRIVING LMFC REFERENCE DATA LATE ARRIVING LMFC REFERENCE Figure 58. Link Delay > LMFC Period Example POWER CYCLE VARIANCE LMFC ALIGNED DATA ILAS DATA LMFCRX LMFC_DELAY LMFC REFERENCE FOR ALL POWER CYCLES FRAME CLOCK Figure 59. LMFC_DELAY_x to Compensate for Link Delay > LMFC The method to select the LMFCDel (Register 0x304) and LMFCVar (Register 0x306) variables is described in the Link Delay Setup Example, with Known Delays section and the Link Delay Setup Example, Without Known Delay section. Note that the setting for LMFCDel must not equal or exceed the number of PCLK cycles per LMFC period in the current mode. Similarly, LMFCVar must not exceed the number of PCLK cycles per LMFC period in the current mode or be set to <12 (whichever value is smaller). Setting LMFCDel appropriately ensures that all the corresponding data samples arrive in the same LMFC period. Then, LMFCVar is written into the receive buffer delay (RBD) to absorb all link delay variation. This write ensures that all data samples arrived before reading. By setting these to fixed values across runs and devices, deterministic latency is achieved. The RBD described in the JESD204B specification takes values from one frame clock cycle to /K/ frame clock cycles, and the RBD of the AD9172 takes values from 0 PCLK cycle to 12 PCLK cycles. As a result, up to 12 PCLK cycles of total delay variation can be absorbed. LMFCVar and LMFCDel are both in PCLK cycles. The PCLK factor, or number of frame clock cycles per 15453-025 PCLK cycle, is equal to 4/f. For more information on this relationship, see the Clock Relationships section. Two examples follow that show how to determine LMFCVar and LMFCDel. After they are calculated, write LMFCDel into Register 0x304 for all devices in the system, and write LMFCVar to Register 0x306 for all devices in the system. Link Delay Setup Example, with Known Delays All the known system delays can be used to calculate LMFCVar and LMFCDel. The example shown in Figure 60 is demonstrated in the following steps. Note that this example is in Subclass 1 to achieve deterministic latency, and the example uses the case for F = 2; therefore, the number of PCLK cycles per multiframe = 16. Because PCBFixed << PCLK Period, PCBFixed is negligible in this example and not included in the calculations. 1. Find the receiver delays using Table 6. RxFixed = 13 PCLK cycles RxVar = 2 PCLK cycles 2. Find the transmitter delays. The equivalent table in the example JESD204B core (implemented on a GTH or GTX gigabit transceiver on a Virtex-6 FPGA) states that the delay is 56 ± 2 byte clock cycles. 3. Because the PCLK rate = ByteRate/4 as described in the Clock Relationships section, the transmitter delays in PCLK cycles are calculated as follows: TxFixed = 54/4 = 13.5 PCLK cycles TxVar = 4/4 = 1 PCLK cycle 4. Calculate MinDelayLane as follows: MinDelayLane = floor(RxFixed + TxFixed + PCBFixed) = floor(13 + 13.5 + 0) = floor(26.5) MinDelayLane = 26 5. Calculate MaxDelayLane as follows: MaxDelayLane = ceiling(RxFixed + RxVar + TxFixed + TxVar + PCBFixed)) = ceiling(13 + 2 + 13.5 + 1 + 0) = ceiling(29.5) MaxDelayLane = 30 6. Calculate LMFCVar as follows: LMFCVar = (MaxDelay + 1) - (MinDelay - 1) = (30 + 1) - (26 - 1) = 31 - 25 LMFCVar = 6 PCLK cycles 7. Calculate LMFCDel as follows: LMFCDel = (MinDelay - 1) % (PCLKsperMF) = ((26 - 1)) % 16 = 25 % 16 LMFCDel = 9 PCLK cycles Write LMFCDel to Register 0x304 for all devices in the system. Write LMFCVar to Register 0x306 for all devices in the system. Rev. B | Page 43 of 145 AD9172 Data Sheet LMFC PCLK FRAME CLOCK DATA AT Tx FRAMER ALIGNED LANE DATA AT Rx DEFRAMER OUTPUT LMFCRX ILAS ILAS DATA Tx VAR Rx VAR DELAY DELAY PCB FIXED DELAY DATA LMFC DELAY = 26 FRAME CLOCK CYCLES 15453-026 TOTAL FIXED LATENCY = 30 PCLK CYCLES Figure 60. LMFC Delay Calculation Example TOTAL VARIABLE LATENCY = 4 PCLK CYCLES Link Delay Setup Example, Without Known Delay If the system delays are not known, the AD9172 can read back the link latency between LMFCRX for each link (with the LMFCDel setting subtracted out) and the SYSREF± aligned LMFC. This information is then used to calculate LMFCVar and LMFCDel. Figure 62 shows how DYN_LINK_LATENCY_0 (Register 0x302) provides a readback showing the delay (in PCLK cycles) between LMFCRX minus the LMFC_DELAY_x (fixed delay) setting set in the SPI at that time and the transition from the ILAS to the first data sample. By repeatedly power cycling and taking this measurement, the minimum and maximum delays across power cycles can be determined and used to calculate LMFCVar and LMFCDel. In Figure 62, for Link A, Link B, and Link C, the system containing the AD9172 (including the transmitter) is power cycled and configured 20 times. The AD9172 is configured as described in the Sync Procedure section. Because the purpose of this exercise is to determine LMFCDel and LMFCVar, the LMFCDel value is programmed to 0 and the DYN_LINK_ LATENCY_0 value is read from Register 0x302. The variation in the link latency over the 20 runs is shown in Figure 62, described as follows: Link A gives readbacks of 6, 7, 0, and 1. Note that the set of recorded delay values rolls over the edge of a multiframe at the boundary of K/PCLK factor = 8. Add the number of PCLK cycles per multiframe = 8 to the readback values of 0 and 1 because they rolled over the edge of the multiframe. Delay values range from 6 to 9. Link B gives delay values from 5 to 7. Link C gives delay values from 4 to 7. The example shown in Figure 62 is demonstrated in the following steps. Note that this example is in Subclass 1 to achieve deterministic latency, and the example uses the case for F = 1; therefore, the number of PCLK cycles per multiframe = 8. 1. Calculate the minimum of all delay measurements across all power cycles, links, and devices as follows: MinDelay = min(all Delay values) = 4 2. Calculate the maximum of all delay measurements across all power cycles, links, and devices as follows: MaxDelay = max(all Delay values) = 9 3. Set LFMCVar to the maximum of 12 PCLK cycles. If latency is required to be minimized for a given application, calculate the total delay variation (with 2 PCLK cycles of guard band on each end) across all power cycles, links, and devices as follows: LMFCVar = (MaxDelay + 2) - (MinDelay - 2) = (9 + 2) - (4 - 2) = 11 - 2 = 9 PCLK cycles 4. Calculate the minimum delay in PCLK cycles (with 2 PCLK cycles of guard band) across all power cycles, links, and devices as follows: LMFCDel = (MinDelay 2) % (PCLKsperMF) = (4 - 2) % 8 = 2 % 8 = 2 PCLK cycles 5. Write LMFCDel to Register 0x304 for all devices in the system. Write LMFCVar to Register 0x306 for all devices in the system. Rev. B | Page 44 of 145 Data Sheet SYSREF± LMFCRX ALIGNED DATA ILAS DATA DYN_LINK_LATENCY Figure 61. DYN_LINK_LATENCY_x Illustration 15453-027 AD9172 LMFC PCLK FRAME CLOCK DYN_LINK_LATENCY_x 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 ALIGNED DATA (LINK A) ILAS DATA ALIGNED DATA (LINK B) ILAS DATA ALIGNED DATA (LINK C) ILAS DATA LMFCRX DETERMINISTICALLY DELAYED DATA LMFC_DELAY = 6 (FRAME CLOCK CYCLES) ILAS LMFC_VAR = 7 (PCLK CYCLES) Figure 62. Multilink Synchronization Settings, Derived Method Example DATA 15453-028 LANE 0 OCTETS LANE 3 OCTETS PCLK_0 SPI CONTROL LANE 4 OCTETS LANE 7 OCTETS PCLK_1 SPI CONTROL TRANSPORT LAYER (QBD) DELAY BUFFER 0 F2S_0 DAC A_I0[15:0] DAC A_Q0[15:0] PCLK_0 TO PCLK_1 FIFO DELAY BUFFER 1 F2S_1 DAC B_I0[15:0] DAC B_Q0[15:0] Figure 63. Transport Layer Block Diagram 15453-029 Rev. B | Page 45 of 145 AD9172 TRANSPORT LAYER The transport layer receives the descrambled JESD204B frames and converts them to DAC samples based on the programmed JESD204B parameters shown in Table 25. The device parameters are defined in Table 26. Table 25. JESD204B Transport Layer Parameters Parameter Description F Number of octets per frame per lane: 1, 2, 3, 4 or 8. K Number of frames per multiframe: K = 32. L Number of lanes per converter device (per link), as follows: 1, 2, 3, 4 or 8. M Number of converters per device (per link), as follows: For real data modes, M is the number of real data converters (if total interpolation is 1×). For complex data modes, M is the number of complex data subchannels. S Number of samples per converter, per frame: 1, 2, 4 or 8. Data Sheet Table 26. JESD204B Device Parameters Parameter Description CF Number of control words per device clock per link. Not supported, must be 0. CS Number of control bits per conversion sample. Not supported, must be 0. HD High density user data format. This parameter is always set to 1. N Converter resolution. N' (or NP) Total number of bits per sample. Certain combinations of these parameters are supported by the AD9172. See Table 28 and Table 29 for a list of supported singlelink and dual-link modes, respectively. Table 28 and Table 29 lists the JESD204B parameters for each of the modes. Table 27 lists JESD204B parameters that have fixed values. Table 27. JESD204B Parameters with Fixed Values Parameter Value K 32 CF 0 HD 1 CS 0 Table 28. Single-Link JESD204B Operating Modes Single-Link JESD204B Modes Parameter 0 1 2 3 4 5 6 7 8 9 10 11 12 18 19 20 21 L (Lane Count) 1 2 3 2 4 1 2 1 4 4 8 8 8 4 4 8 8 M (Converter Count) 2 4 6 2 4 2 4 4 2 2 2 2 2 1 1 1 1 F (Octets per Frame per Lane) 4 4 4 2 2 3 3 8 1 2 1 2 3 1 2 1 2 S (Samples per Converter per Frame) 1 1 1 1 1 1 1 1 1 2 2 4 8 2 4 4 8 NP (Total Number of Bits per Sample) 16 16 16 16 16 12 12 16 16 16 16 16 12 16 16 16 16 N (Converter Resolution) 16 16 16 16 16 12 12 16 16 16 16 16 12 16 16 16 16 Table 29. Dual-Link JESD204B Operating Modes Dual-Link JESD204B Modes Parameter 0 1 2 3 4 5 6 7 8 9 18 19 L (Lane Count) 1 2 3 2 4 1 2 1 4 4 4 4 M (Converter Count) 2 4 6 2 4 2 4 4 2 2 1 1 F (Octets per Frame per Lane) 4 4 4 2 2 3 3 8 1 2 1 2 S (Samples per Converter per Frame) 1 1 1 1 1 1 1 1 1 2 2 4 NP (Total number of Bits per Sample) 16 16 16 16 16 12 12 16 16 16 16 16 N (Converter Resolution) 16 16 16 16 16 12 12 16 16 16 16 16 Rev. B | Page 46 of 145 Data Sheet AD9172 Configuration Parameters The AD9172 modes refer to the link configuration parameters for L, K, M, N, NP, S, and F. Table 30 provides the description and addresses for these settings. Table 30. Configuration Parameters JESD204B Setting Description L - 1 Number of lanes minus 1. F - 1 K - 1 M - 1 Number of ((octets per frame) per lane) minus 1. Number of frames per multiframe minus 1. Number of converters minus 1. N - 1 Converter bit resolution minus 1. NP - 1 Bit packing per sample minus 1. S - 1 HD Number of ((samples per converter) per frame) minus 1. High density format. Set to 1. DID BID LID0 JESDV Device ID. Match the device ID sent by the transmitter. Bank ID. Match the bank ID sent by the transmitter. Lane ID for Lane 0. Match the Lane ID sent by the transmitter on Logical Lane 0. JESD204x version. Match the version sent by the transmitter (0x0 = JESD204A, 0x1 = JESD204B). Address Register 0x453, Bits[4:0] Register 0x454, Bits[7:0] Register 0x455, Bits[4:0] Register 0x456, Bits[7:0] Register 0x457, Bits[4:0] Register 0x458, Bits[4:0] Register 0x459, Bits[4:0] Register 0x45A, Bit 7 Register 0x450, Bits[7:0] Register 0x451, Bits[7:0] Register 0x452, Bits[4:0] Register 0x459, Bits[7:5] The AD9172 truncates the output of the main digital datapath to the value of N bits for the selected mode, which is then sent to the DAC core. It is possible to send the value of NP number of bits worth of data with the lower NP - N LSBs padded as 0s, or to send the full NP number of bits data across the SERDES lanes. In either case, the lower NP - N LSBs are truncated prior to the DAC core. Data Flow Through the JESD204B Receiver The link configuration parameters determine how the serial bits on the JESD204B receiver interface are deframed and passed on to the DACs as data samples. Deskewing and Enabling Logical Lanes After proper configuration, the logical lanes are automatically deskewed. All logical lanes are enabled or not based on the number of lanes for the mode setting chosen in Register 0x110, Bits[4:0]. The physical lanes are all powered up by default. To disable power to physical lanes that are not being used, set Bit x in Register 0x201 to 1 to disable Physical Lane x, and keep it at 0 to enable it. The logical lanes must be enabled and deskewed on a per link basis using the LINK_PAGE control (Register 0x300, Bit 2). Set Bit x in Register 0x46C to 1 to deskew Link Logical Lane x for the selected link page. JESD204B TEST MODES PHY PRBS Testing The JESD204B receiver on the AD9172 includes a PRBS pattern checker on the back end of its physical layer. This functionality enables bit error rate (BER) testing of each physical lane of the JESD204B link. The PHY PRBS pattern checker does not require that the JESD204B link be established. It can synchronize with a PRBS7, PRBS15, or PRBS31 data pattern. PRBS pattern verification can be performed on multiple lanes at once. The error counts for failing lanes are reported for one JESD204B lane at a time. The process for performing PRBS testing on the AD9172 is as follows: 1. Start sending a PRBS7, PRBS15, or PRBS31 pattern from the JESD204B transmitter. 2. Select and write the appropriate PRBS pattern to Register 0x316, Bits[3:2], as shown in Table 31. 3. Enable the PHY test for all lanes being tested by writing to PHY_TEST_EN (Register 0x315). Each bit of Register 0x315 enables the PRBS test for the corresponding lane. For example, writing a 1 to Bit 0 enables the PRBS test for Physical Lane 0. 4. Toggle PHY_TEST_RESET (Register 0x316, Bit 0) from 0 to 1 then back to 0. 5. Set PHY_PRBS_TEST_THRESHOLD_xBITS (Bits[23:0], Register 0x319 to Register 0x317) as desired. 6. Write a 0 and then a 1 to PHY_TEST_START (Register 0x316, Bit 1). The rising edge of PHY_TEST_START starts the test. a. (Optional) In some cases, it may be necessary to repeat Step 4 at this point. Toggle PHY_TEST_RESET (Register 0x316, Bit 0) from 0 to 1, then back to 0. 7. Wait 500 ms. 8. Stop the test by writing PHY_TEST_START (Register 0x316, Bit 1) = 0. 9. Read the PRBS test results. a. Each bit of PHY_PRBS_PASS (Register 0x31D) corresponds to one SERDES lane (0 = fail, 1 = pass). b. The number of PRBS errors seen on each failing lane can be read by writing the lane number to check (0 to 7) in PHY_SRC_ERR_CNT (Register 0x316, Bits[6:4]) and reading the PHY_PRBS_ERR_CNT_xBITS (Register 0x31A to Register 0x31C). The maximum error count is 224 - 1. If all bits of Register 0x31A to Register 0x31C are high, the maximum error count on the selected lane is exceeded. Table 31. PHY PRBS Pattern Selection PHY_PRBS_PAT_SEL Setting (Register 0x316, Bits[3:2]) 0b00 (default) 0b01 0b10 PRBS Pattern PRBS7 PRBS15 PRBS31 Rev. B | Page 47 of 145 AD9172 Data Sheet Transport Layer Testing 2. Set SEL_IF_PARDATAINV_DES_RC_CH bits The JESD204B receiver in the AD9172 supports the short transport layer (STPL) test as described in the JESD204B standard. Use this test to verify the data mapping between the JESD204B transmitter and receiver. To perform this test, this function must be implemented and enabled in the logic device. Before running the test on the receiver side, the link must be established and running without errors. The STPL test ensures that each sample from each converter is mapped appropriately according to the number of converters (M) and the number of samples per converter (S). As specified in the JESD204B standard, the converter manufacturer specifies the test samples that are transmitted. Each sample must have a unique value. For example, if M = 2 and S = 2, four unique samples are transmitted repeatedly until the test is stopped. The expected sample must be programmed into the device and the expected sample is compared to the received sample one sample at a time until all are tested. The process for performing this test on the AD9172 is described as follows: (Register 0x234, Bits[7:0]) to 0 to make sure lanes not inverted. 3. Enable the loop back test for all lanes being tested by writing to EN_LBT_DES_RC_CH (Register 0x250). Each bit of Register 0x250 enables the loop back test for the corresponding lane. For example, writing a 1 to Bit 0 enables the test for Physical Lane 0. 4. For halfrate, set EN_LBT_HALFRATE_DES_RC (Register 0x251, Bit 1) to 1; otherwise, set it to 0. 5. Toggle INIT_LBT_SYNC_DES_RC (Register 0x251, Bit 0) from 0 to 1 then back to 0. 6. Refer to the PHY PRBS Testing section for information on how to run a PRBS7 check. Repeated CGS and ILAS Test As per Section 5.3.3.8.2 of the JESD204B specification, the AD9172 can check that a constant stream of /K28.5/ characters is being received, or that CGS followed by a constant stream of ILAS is being received. 1. Synchronize the JESD204B link. 2. Enable the STPL test at the JESD204B Tx. 3. Depending on JESD204B case, there may be up to six complex subchannels (M = 6), and each frame may contain up to eight samples (S = 8). Configure the SHORT_TPL_ REF_SP_MSB bits (Register 0x32E) and the SHORT_TPL_ REF_SP_LSB bits (Register 0x32D) to match one of the samples for one converter within one frame. For N = 12 modes, the expected sample value is multiplied by 16. 4. Set SHORT_TPL_M_SEL (Register 0x32C, Bits[3:2]) to select the channel. 5. Set SHORT_TPL_IQ_SAMPLE_SEL (Register 0x32F, Bit 6) to select the I or Q subchannel. 6. Set SHORT_TPL_SP_SEL (Register 0x32C, Bits[7:4]) to select the sample within one frame for the selected . 7. Set SHORT_TPL_TEST_EN (Register 0x32C, Bit 0) to 1. To run a repeated CGS test, send a constant stream of /K28.5/ characters to the AD9172 SERDES inputs. Next, set up the device and enable the links. Ensure that the /K28.5/ characters are being received by verifying that SYNCOUT± is deasserted and that CGS has passed for all enabled link lanes by reading Register 0x470. To run the CGS followed by a repeated ILAS sequence test, follow the procedure to set up the links, but before performing the last write (enabling the links), enable the ILAS test mode by writing a 1 to Register 0x477, Bit 7. Then, enable the links. When the device recognizes four CGS characters on each lane, it deasserts the SYNCOUTx±. At this point, the transmitter starts sending a repeated ILAS sequence. Read Register 0x473 to verify that the initial lane synchronization has passed for all enabled link lanes. 8. Set SHORT_TPL_TEST_RESET (Register 0x32C, Bit 1) to 1, then back to 0. 9. Wait for the desired time. The desired time is calculated as 1/(sample rate × BER). For example, given a bit error rate of BER = 1 × 10-10 and a sample rate = 1 GSPS, the desired time = 10 sec. Then, set SHORT_TPL_TEST_EN to 0. 10. Read the test result at SHORT_TPL_FAIL (Register 0x32F, Bit 0). JESD204B ERROR MONITORING Disparity, Not in Table, and Unexpected Control (K) Character Errors As per Section 7.6 of the JESD204B specification, the AD9172 can detect disparity errors, not in table (NIT) errors, and unexpected control character errors, and can optionally issue a sync request and reinitialize the link when errors occur. 11. Choose another sample for the same or another M to continue with the test, until all samples for both converters from one frame are verified. Several other interpretations of the JESD204B specification are noted in this section. When three NIT errors are injected to one lane and QUAL_RDERR (Register 0x476, Bit 4) = 1, the readback Internal Loop Back Test The AD9172 integrates one internal PRBS generator that can be used to test the JESD204B PHYs without an external SERDES signal input. The process for performing internal loopback testing on the AD9172 is as follows: 1. Set the EQ_BOOST_PHYx bits (Register 0x240, Bits[7:0] and Register 0x241, Bit[7:0]) to 0. values of the bad disparity error (BDE) count register is 1. Reporting of disparity errors that occur at the same character position of an NIT error is disabled. No such disabling is performed for the disparity errors in the characters after an NIT error. Therefore, it is expected behavior that an NIT error may result in a BDE error. Rev. B | Page 48 of 145 Data Sheet Checking Error Counts The error count can be checked for disparity errors, NIT errors, and unexpected control character errors. The error counts are on a per lane and per error type basis. Each error type and lane has a register dedicated to it. To check the error count, the following steps must be performed: 1. Choose and enable which errors to monitor by selecting them in Register 0x480, Bits[5:3] to Register 0x487, Bits[5:3]. Unexpected K (UEK) character, BDE, and NIT error monitoring can be selected for each lane by writing a 1 to the appropriate bit, as described in Table 60. These bits are enabled by default. 2. The corresponding error counter reset bits are in Register 0x480, Bits[2:0] to Register 0x487, Bits[2:0]. Write a 1 to the corresponding bit to reset that error counter. 3. Registers 0x488, Bits[2:0] to Register 0x48F, Bits[2:0] have the terminal count hold indicator for each error counter. If this flag is enabled, when the terminal error count of 0xFF is reached, the counter ceases counting and holds that value until reset. Otherwise, it wraps to 0x00 and continues counting. Select the desired behavior and program the corresponding register bits per lane. Check for Error Count Over Threshold To check for the error count over threshold, follow these steps: 1. Define the error counter threshold. The error counter threshold can be set to a user defined value in Register 0x47C, or left to the default value of 0xFF. When the error threshold is reached, an IRQ is generated, SYNCOUTx± is asserted, or both, depending on the mask register settings. This one error threshold is used for all three types of errors (UEK, NIT, and BDE). 2. Set the SYNC_ASSERT_MASK bits. The SYNCOUTx± assertion behavior is set in Register 0x47D, Bits[2:0]. By default, when any error counter of any lane is equal to the threshold, it asserts SYNCOUTx± (Register 0x47D, Bits[2:0] = 0b111). When setting the SYNC_ASSERT_MASK bits, LINK_PAGE (Register 0x300, Bit 2) must be set to 1. 3. Read the error count reached indicator. Each error counter has a terminal count reached indicator, per lane. This indicator is set to 1 when the terminal count of an error counter for a particular lane is reached. These status bits are located in Register 0x490, Bits[2:0] to Register 0x497, Bits[2:0]. Bit 3 can be read back to indicate whether a particular lane is active. AD9172 Error Counter and IRQ Control For error counter and IRQ control, follow these steps: 1. Enable the interrupts. Enable the JESD204B interrupts. The interrupts for the UEK, NIT, and BDE error counters are in Register 0x4B8, Bits[7:5]. There are other interrupts to monitor when bringing up the link, such as lane deskewing, initial lane sync, good check sum, frame sync, code group sync (Register 0x4B8, Bits[4:0], and configuration mismatch (Register 0x4B9, Bit 0). These bits are off by default but can be enabled by writing 0b1 to the corresponding bit. 2. Read the JESD204B interrupt status. The interrupt status bits are in Register 0x4BA, Bits[7:0] and Register 0x4BB, Bit 0, with the status bit position corresponding to the enable bit position. 3. It is recommended to enable all interrupts that are planned to be used prior to bringing up the JESD204B link. When the link is up, the interrupts can be reset and then used to monitor the link status. Monitoring Errors via SYNCOUTx± When one or more disparity, NIT, or unexpected control character errors occur, the error is reported on the SYNCOUTx± pin as per Section 7.6 of the JESD204B specification. The JESD204B specification states that the SYNCOUTx± signal is asserted for exactly two frame periods when an error occurs. For the AD9172, the width of the SYNCOUTx± pulse can be programmed to ½, 1, or 2 PCLK cycles. The settings to achieve a SYNCOUTx± pulse of two frame clock cycles are given in Table 32. Table 32. Setting SYNCOUTx± Error Pulse Duration PCLK Factor F (Frames/PCLK) SYNC_ERR_DUR (Register 0x312, Bits[7:4]) Setting1 1 4 0 (default) 2 2 1 3 1.5 2 4 1 2 8 0.5 4 1 These register settings assert the SYNCOUTx± signal for two frame clock cycle pulse widths. Unexpected Control Character, NIT, Disparity IRQs For UEK character, NIT, and disparity errors, error count over the threshold events are available as IRQ events. Enable these events by writing to Register 0x4B8, Bits[7:5]. The IRQ event status can be read at Register 0x4BA, Bits[7:5] after the IRQs are enabled. See the Error Counter and IRQ Control section for information on resetting the IRQ. See the Interrupt Request Operation section for more information on IRQs. Rev. B | Page 49 of 145 AD9172 Errors Requiring Reinitializing A link reinitialization automatically occurs when four invalid disparity characters or four NIT characters are received as per Section 7.1 of the JESD204B specification. When a link reinitialization occurs, the resync request is at least five frames and nine octets long. The user can optionally reinitialize the link when the error count for disparity errors, NIT errors, or UEK character errors reaches a programmable error threshold. The process to enable the reinitialization feature for certain error types is as follows: 1. Choose and enable which errors to monitor by selecting them in Register 0x480, Bits[5:3] to Register 0x487, Bits[5:3]. UEK, BDE, and NIT error monitoring can be selected for each lane by writing a 1 to the appropriate bit, as described in Table 33. These are enabled by default. 2. Write a 0 to the corresponding bit to Register 0x480, Bits[2:0] to Register 0x487, Bits[2:0] to take counter out of reset. 3. Enable the sync assertion mask for each type of error by writing to SYNC_ASSERT_MASK (Register 0x47D, Bits[2:0]) according to Table 33. 4. Program the desired error counter threshold into ERRORTHRES (Register 0x47C). 5. For each error type enabled in the SYNC_ASSERT_MASK register, if the error counter on any lane reaches the programmed threshold, SYNCOUTx± falls, issuing a sync request. Note that all error counts are reset when a link reinitialization occurs. The IRQ does not reset and must be reset manually. Table 33. Sync Assertion Mask (SYNC_ASSERT_MASK) Addr. Bit No. Bit Name Description 0x47D 2 BDE Set to 1 to assert SYNCOUTx± if the disparity error count reaches the threshold 1 NIT Set to 1 to assert SYNCOUTx± if the NIT error count reaches the threshold 0 UEK Set to 1 to assert SYNCOUTx± if the UEK character error count reaches the threshold CGS, Frame Sync, Checksum, and ILAS Monitoring Register 0x470 to Register 0x473 can be monitored to verify that each stage of the JESD204B link establishment has occurred. Data Sheet Bit x of CODE_GRP_SYNC (Register 0x470) is high if Link Lane x received at least four K28.5 characters and passed code group synchronization. Bit x of FRAME_SYNC (Register 0x471) is high if Link Lane x completed initial frame synchronization. Bit x of GOOD_CHECKSUM (Register 0x472) is high if the checksum sent over the lane matches the sum of the JESD204B parameters sent over the lane during ILAS for Link Lane x. The parameters can be added either by summing the individual fields in registers or summing the packed register. The calculated checksums are the lower eight bits of the sum of the following fields: DID, BID, LID, SCR, L - 1, F - 1, K - 1, M - 1, N - 1, SUBCLASSV, NP - 1, JESDV, S - 1, and HD. Bit x of INIT_LANE_SYNC (Register 0x473) is high if Link Lane x passed the initial lane alignment sequence. CGS, Frame Sync, Checksum, and ILAS IRQs Fail signals for CGS, frame sync, checksum, and ILAS are available as IRQ events. Enable them by writing to Register 0x4B8, Bits[3:0]. The IRQ event status can be read at Register 0x4BA, Bits[3:0] after the IRQs are enabled. Write a 1 to Register 0x4BA, Bit 0 to reset the CGS IRQ. Write a 1 to Register 0x4BA, Bit 1 to reset the frame sync IRQ. Write a 1 to Register 0x4BA, Bit 2 to reset the checksum IRQ. Write a 1 to Register 0x4BA, Bit 3 to reset the ILAS IRQ. See the Interrupt Request Operation section for more information. Configuration Mismatch IRQ The AD9172 has a configuration mismatch flag that is available as an IRQ event. Use Register 0x4B9, Bit 0 to enable the mismatch flag (it is enabled by default), and then use Register 0x4BB, Bit 0 to read back its status and reset the IRQ signal. See the Interrupt Request Operation section for more information. The configuration mismatch event flag is high when the link configuration settings (in Register 0x450 to Register 0x45D) do not match the JESD204B settings received by the device (Register 0x400 to Register 0x40D). This function is different from the good checksum flags in Register 0x472. The good checksum flags ensure that the transmitted checksum matches a calculated checksum based on the transmitted settings. The configuration mismatch event ensures that the transmitted settings match the configured settings. Rev. B | Page 50 of 145 Data Sheet DIGITAL DATAPATH The full digital datapath of the AD9172 consists of channel datapaths that are bypassable, as well as a main DAC datapath leading up to the analog DAC core. There is a variety of different digital feature blocks available within each of the channel and main DAC datapaths. TOTAL DATAPATH INTERPOLATION The AD9172 contains two separate blocks of interpolation: one block is located in each of the channelizer datapaths, and a second interpolation stage is located in the main DAC datapath. The total interpolation for the chip can be determined by multiplying the channel interpolation factor by the main datapath interpolation factor. The relationship between the DAC sample rate and input data rate is shown in the following equation: Total Interpolation = Channel Interpolation × Main Interpolation fDATA = fDAC/(Channel Interpolation × Main Interpolation) Each of the various cascaded half-band filters has 80% signal bandwidth capabilities. Therefore, if using interpolation (not bypass or 1× total interpolation for both channel and main datapaths), the available signal bandwidth (BW) with respect to the input data rate is calculated as follows: Signal BW = 0.8 × (fDATA/2) where the total interpolation > 1. Signal BW = (fDATA /2) where the total interpolation = 1. The interpolation values are programmed as shown in the Table 34. Table 34. Interpolation Factor Register Settings Main Datapath, Interpolation Register 0x111, Factor Bits[7:4] Channel Datapath, Register 0x111, Bits[3:0] 1× 0x1 0x1 2× 0x2 0x2 3× Not applicable 0x3 4× 0x4 0x4 6× 0x6 0x6 8× 0x8 0x8 12× 0xC Not applicable Table 35. Interpolation Modes and Useable Bandwidth Available Signal Total Interpolation Bandwidth fDATA 1× (Bypass) fDATA/2 fDAC 2×, 4×, 6×, 8×, 12×, 16×, 18×, 24×, 32×, 36×, 48×, 64× 80% × fDATA /2 fDAC/total interpolation AD9172 Filter Performance The interpolation filters interpolate between existing data in such a way that they minimize changes in the incoming data while suppressing the creation of interpolation images. The usable bandwidth, as shown in Table 35, is defined as the frequency band over which the filters have a pass-band ripple of less than ±0.001 dB and an image rejection of greater than 85 dB. Conceptual drawings that shows the relative bandwidth of each of the filters are shown in Figure 64 and Figure 65. The maximum pass-band amplitude of all filters is the same; they are different in the illustration to improve understanding. 1× (MAX DAC = 6GHz) 2× (MAX DAC = 3GHz) 4× (MAX DAC = 6GHz) 6× (MAX DAC = 9GHz) FILTER RESPONSE 15453-030 3500 2500 1500 500 500 1500 2500 3500 4500 5500 FREQUENCY (MHz) Figure 64. Band Responses of Total Interpolation Rates for 1×, 2×, 4×, and 6× at Each Respective Maximum Achievable DAC Rate 8× 12× 16× 18× 24× 32× 36× 48× 64× FILTER RESPONSE 15453-031 1000 750 500 250 0 250 500 750 1000 FREQUENCY (MHz) Figure 65. Band Responses of Total Interpolation Rates for 8×, 12×, 16×, 18×, 24×, 32×, 36×, 48×, and 64× at a 12 GHz DAC Rate Rev. B | Page 51 of 145 AD9172 Data Sheet NCO Only Mode The AD9172 is capable of operating in a mode with only the NCO enabled. In this mode, a single-tone sine wave is generated using a programmable internal dc amplitude level that is injected into the NCO block to modulate the data into a single tone. This internal dc level is injected into either the channel or main datapaths through various controls, as shown in Figure 66. Mode 3 and Mode 4 can be used to generate a single-channel or dual channel NCO only mode of operation, respectively. It is not necessary to bring up the JESD204B link in this mode. This mode is a useful option to bring up a transmitter radio signal chain without requiring a digital data source, because the device generates the NCO data internally. This mode can also be used in applications where a sine wave is all that is required, such as in a local oscillator application. There is an additional optional calibration NCO block that can be used CHANNEL GAIN DDSM_EN_CAL_ACC REG 0x1E6, BIT 2 as part of the initial system calibration without needing to reprogram the final main datapath NCO to the final system configuration. This feature is discussed in more detail in the Calibration NCO section. When the NCO test mode is enabled, the data source of the digital datapath is the dc test data word, meaning that the JESD204B link can be brought up and data can be transferred to the device over the link, but the data is not presented to the DAC when in this test mode. Connection to the SERDES data source is only achieved by disabling this test mode. The SPI control bit for this test mode can be set on the fly, but because disabling the mode and switching to the SERDES datapath normally requires the lanes and/or interpolation mode to also be set, on the fly setting or resetting of the NCO only mode control bit is normally not practical. CALIBRATION 32-BIT NCO REG 0x1E2 TO REG 0x1E5 MAIN 48-BIT NCO REG 0x114 TO REG 0x119 N CHANNEL GAIN N CHANNEL GAIN N DC AMPLITUDE LEVEL (REG 0x148 TO REG 0x149) NCO DDSC_EN_DC_INPUT REG 0x130, BIT 0 NCO + DDSC_EN_DC_INPUT REG 0x130, BIT 0 NCO DDSC_EN_DC_INPUT REG 0x130, BIT 0 DDSM_EN_CAL_FREQ_TUNING REG 0x1E6, BIT 0 PA PROTECT M NCO DDSM_EN_CAL_DC_INPUT REG 0x1E6, BIT 1 RAMP UP/DOWN GAIN DAC CORE Figure 66. DC Amplitude Injection for NCO Only Mode Block Diagram 15453-148 Rev. B | Page 52 of 145 Data Sheet CHANNEL DIGITAL DATAPATH 1× DIGITAL GAIN 2× 2× 2× 3× NCO DIGITAL GAIN 2× 2× 2× 3× NCO DIGITAL GAIN 2× 2× 2× 3× NCO AD9172 TO MAIN DAC DIGITAL DATAPATH JESD204B INTERFACE 15453-033 Figure 67. Block Diagram of the Channel Digital Datapath per the Main DAC Output Each main DAC output has three optional channelizers, or channel datapaths, that are selected based on the JESD204B mode selected. The channel datapaths also have the option to be bypassed (1× interpolation selected), which bypasses all of the digital features included in each channelizer. Each channelizer consists of a digital gain stage, complex interpolation block, and complex 48-bit NCO with modulus. The interpolation selection is the same for all three channelizers; however, the gain stage and complex NCO values can all be independently configured. The controls for these blocks are paged by the channel paging mask in the CHANNEL_PAGE bits (Register 0x008, Bits[5:0]), as described in Table 36. Each bit of the page mask corresponds to a channel datapath. These channels can be paged individually to set the values for each channel uniquely, or can be paged simultaneously to set all channels to the same value for the control being configured. Table 36. Channel Page Mask CHANNEL_PAGE (Register 0x008, Bits[5:0]) Channel Paged 0x01 (Bit 0) Channel 0 0x02 (Bit 1) Channel 1 0x04 (Bit 2) Channel 2 0x08 (Bit 3) Channel 3 0x10 (Bit 4) Channel 4 0x20 (Bit 5) Channel 5 Channel Datapath Updated Channel 0 of DAC0 Channel 1 of DAC0 Channel 2 of DAC0 Channel 0 of DAC1 Channel 1 of DAC1 Channel 2 of DAC1 Digital Gain The AD9172 has individual channel gain controls that allow unique gain scaling capabilities for each complex data input channel. The gain code for each channel is 12-bit resolution, located in Register 0x146 and Register 0x147, and can be calculated by the following formula: 0 Gain (212 - 1)/211 - dB < dBGain +6.018 dB Gain = Gain Code × (1/2048) dBGain = 20 × log10 (Gain) Gain Code = 2048 × Gain = 211 ×10(dBGain/20) The gain code control (CHNL_GAIN) is paged with the channel page mask (CHANNEL_PAGE) in Register 0x008, Bits[5:0]. The digital gain feature is available in all modes, except when 1× channel interpolation is used because the channel datapaths are bypassed in that mode. The summing node that combines the three channels may clip the summed signals if the combined amplitude is too large. For example, if all three channels are being used and all three data streams are >1/3 full-scale amplitude, clipping may occur. The sum of the data values when any number of channels is used must be between -215 and +215. Each of the digital blocks in the channels is described in more detail in the following sections. Rev. B | Page 53 of 145 AD9172 Data Sheet Channel Interpolation The channel interpolation options available are bypass (1×), 2×, 3×, 4×, 6×, and 8×. Each of the half-band filters used for interpolation has 80% bandwidths with 85 dB of stop band rejection. The channel half-band cascaded configuration is shown in Figure 68, with each of the useable bandwidths of the channel interpolation filters listed in Table 37. 15453-034 HB0 HB1 2× 2× HB2 TB0 2× 3× Figure 68. Channel Interpolation Half-Band Filter Block Diagram Table 37. Channel Interpolation Useable Bandwidths and Rejection Half-Band Filter Bandwidth (×fIN_FILTER) (%) Stop Band Rejection (dB) HB0 80 85 TB0 54 85 HB1 40 85 HB2 27 85 1 fIN_FILTER is the frequency at the input of the half-band filter. Channel Digital Modulation The AD9172 has digital modulation features to modulate the baseband quadrature signal to a desired frequency. There are two stages of complex digital modulation available in the AD9172: channel modulation and main modulation. Each main DAC has three channels, each with its own NCO, that can individually modulate the data from each channel with a unique frequency and phase offset. The AD9172 is equipped with several NCO modes. The default NCO is a 48-bit, integer NCO. There is an additional modulus option for each channel NCO where the A/B ratio of the dual modulus NCO allows the output frequency to be synthesized with very fine precision. NCO mode is selected as shown in Table 38. These controls are paged per the channel page masks in the CHANNEL_PAGE bits (Register 0x008, Bits[5:0]). Table 38. Channel Modulation Mode Selection Modulation Type Modulation Mode Register 0x130, Register 0x130, Bit 6 Bit 2 None 0b0 0b0 48-Bit Integer NCO 0b1 0b0 48-Bit Dual Modulus NCO 0b1 0b1 The channel NCO blocks also contain sideband selection controls as well as options for how the FTW and phase offset controls are updated. Calculate the phase offset word control as follows: -180° Degrees Offset +180° Degrees Offset = 180° × (DDSC_NCO_PHASE_OFFSET/215) where DDSC_NCO_PHASE_OFFSET is a 16-bit twos complement value programmed in the registers listed in Table 39. Table 39. Channel NCO Phase Offset Registers Address Value Description 0x138 DDSC_NCO_PHASE_OFFSET[7:0] 8 LSBs of phase offset 0x139 DDSC_NCO_PHASE_OFFSET[15:8] 8 MSBs of phase offset 48-Bit Dual Modulus NCO The 48-bit dual modulation mode uses an NCO, a phase shifter, and a complex modulator to modulate the signal by a programmable carrier signal, as shown in Figure 69. This configuration allows output signals to be placed anywhere in the output spectrum up to ±fNCO/2 with very fine frequency resolution. The NCO produces a quadrature carrier to translate the input signal to a new center frequency. A quadrature carrier is a pair of sinusoidal waveforms of the same frequency, offset 90° from each other. The frequency of the quadrature carrier is set via a FTW. The quadrature carrier is mixed with the I and Q data and then summed into the I and Q datapaths, as shown in Figure 69. Integer NCO Mode The channel 48-bit NCOs can be used as integer NCOs. The FTW for the channel NCOs depends on the speed at which the channel NCO block is running (fNCO), which is the same rate as the summing node (maximum of 1.5 GSPS) and can be calculated by using the following formulas: fNCO = fDATA × Channel Interpolation or fNCO = fDAC/Main Interpolation = fSUMMING_NODE The FTWs for each individual channel can be programmed separately and are calculated by using the following formula: -fNCO/2 fCARRIER < +fNCO/2 DDSC_FTW = (fCARRIER/fNCO) × 248 where DDSC_FTW is a 48-bit, twos complement number. The frequency tuning word is set as shown in Table 40. Table 40. Channel NCO FTW Registers Address Value Description 0x132 DDSC_FTW[7:0] 8 LSBs of FTW 0x133 DDSC_FTW[15:8] Next 8 bits of FTW 0x134 DDSC_FTW[23:16] Next 8 bits of FTW 0x135 DDSC_FTW[31:24] Next 8 bits of FTW 0x136 DDSC_FTW[39:32] Next 8 bits of FTW 0x137 DDSC_FTW[47:40] 8 MSBs of FTW Rev. B | Page 54 of 145 Data Sheet Unlike other registers, the FTW registers are not updated immediately upon writing. Instead, the FTW registers update on the rising edge of DDSC_FTW_LOAD_REQ (Register 0x131, Bit 0). After an update request, DDSC_FTW_LOAD_ACK (Register 0x131, Bit 1) must be high to acknowledge that the FTW has updated. The DDSC_SEL_SIDEBAND bit (Register 0x130, Bit 1 = 0b1) is a convenience bit that can be set to use the lower sideband modulation result, which is equivalent to flipping the sign of the FTW. I DATA INTERPOLATION DDSC_FTW[47:0] DDSC_NCO_PHASE_OFFSET [15:0] COS(n + ) NCO SIN(n + ) 1 DDSC_SEL_SIDEBAND 01 + OUT_I OUT_Q 15453-035 Q DATA INTERPOLATION Figure 69. NCO Modulator Block Diagram Channel Modulus NCO Mode (Direct Digital Synthesis (DDS)) Each of the channel 48-bit NCOs can also be used in a dual modulus mode to create fractional frequencies beyond the 48-bit accuracy. The modulus mode is enabled by programming the DDSC_MODULUS_EN bit in the DDSC_DATAPATH_CFG register to 1 (Register 0x130, Bit 2 = 0b1). The frequency ratio for the programmable modulus direct digital synthesis (DDS) is very similar to that of the typical accumulator-based DDS. The only difference is that N is not required to be a power of two for the programmable modulus, but can be an arbitrary integer. In practice, hardware constraints place limits on the range of values for N. As a result, the modulus extends the use of the NCO to applications that require exact rational frequency synthesis. The underlying function of the programmable modulus technique is to alter the accumulator modulus. Implementation of the programmable modulus function within the AD9172 is such that the fraction, M/N, is expressible by the following equation. Note that the form of the equation implies a compound frequency tuning word with X representing the integer part and A/B representing the fractional part. AD9172 fCARRIER f NCO = M N = X+ A B 248 where: X is programmed in Register 0x132 to Register 0x137. A is programmed in Register 0x140 to Register 0x145. B is programmed in Register 0x13A to Register 0x13F. Programmable Modulus Example Consider the case in which fNCO = 1500 MHz and the desired value of fCARRIER is 150 MHz. This scenario synthesizes an output frequency that is not a power of two submultiple of the sample rate, namely fCARRIER = (1/10) fNCO, which is not possible with a typical accumulator-based DDS. The frequency ratio, fCARRIER/fDAC, leads directly to M and N, which are determined by reducing the fraction (150,000,000/1,500,000,000) to its lowest terms, that is, M/N = 150,000,000/1,500,000,000 = 1/10 Therefore, M = 1 and N = 10. After calculation, X = 28,147,497,671,065, A = 3, and B = 5. Programming these values into the registers for X, A, and B (X is programmed in Register 0x132 to Register 0x137 for DDSC_ FTWx, B is programmed in Register 0x13A to Register 0x13F for DDSC_ACC_MODULUSx, and A is programmed in Register 0x140 to Register 0x145 for DDSC_ACC_DELTAx) causes the NCO to produce an output frequency of exactly 150 MHz given a 1500 MHz sampling clock. For more details, refer to the AN-953 Application Note. NCO Reset Resetting the NCO can be useful when determining the start time and phase of the NCO. The NCO can be reset by several different methods, including a SPI write or by the SYSREF± signal. Channel Summing Node The channel datapaths all combine at the summing node junction before continuing on to the main DAC datapath. The summation of any number of channels being used must not exceed the ±215 value range to avoid clipping of the data signal into the main datapath. The maximum data rate for each channel when the channel interpolation is >1× is limited by the summing node junction maximum speed of 1.5 GSPS. If the channel datapaths are bypassed (channel interpolation is 1×), the summing node block is also bypassed, as shown in Figure 67. Rev. B | Page 55 of 145 AD9172 MAIN DIGITAL DATAPATH Data Sheet FROM CHANNELIZER SUMMING NODE 1× RAMP UP/DOWN GAIN PA PROTECTION 2× 2× 2× 3× NCO Figure 70. Block Diagram of the Main Digital Datapath per Main DAC Output TO ANALOG DAC CORE 15453-036 Each main DAC digital datapath consists of a power amplifier (PA) protection block, a complex main datapath interpolation block, a 48-bit complex main datapath NCO, and a ramp-up/ ramp-down gain block. The main DAC datapaths also have the option to be bypassed (1× interpolation selected), which bypasses all of the complex digital features included the main digital datapath. The interpolation selection is set the same for all main datapaths; however, the PA protection block and complex NCO values can all be independently configured. The controls for these blocks are paged by the main DAC datapath paging mask, MAINDAC_PAGE (Register 0x008, Bits[7:6]), as listed in Table 41. Each bit of the page mask corresponds to a main DAC datapath. These datapaths can be paged individually to set the values for each DAC uniquely or can be paged simultaneously to set all channels to the same value for the control being configured. Table 41. Main DAC Datapath Page Mask MAINDAC_PAGE (Register 0x008, Bits[7:6]) DAC Paged DAC Datapath Updated 0x40 (Bit 6) DAC0 DAC0 0x80 (Bit 7) DAC1 DAC1 Each of the digital blocks in the main datapaths is described in more detail in the following sections. Downstream Protection (PA Protection) The AD9172 has several blocks designed to protect the PA of the system, as well as other downstream blocks, by preventing transients out of the DAC outputs. The DAC output can be triggered to turn on and off by the following signals, shown in Figure 71: · PDP_PROTECT. This signal asserts when the calculated digital vector power exceeds a programmable threshold. · INTERFACE_PROTECT. This signal asserts when certain JESD204B errors occur. · SPI_PROTECT. This signal asserts when the user writes the SPI trigger register control. · BSM_PROTECT. This signal asserts and the blanking state machine (BSM) module flushes the datapath on the rising edge of the TXEN0 or TXEN1 signals, which may come from a SPI write or the external TXEN0 or TXEN1 pin. The flags of these events can also be routed out on the pins of IRQ (IRQ0 and IRQ1) to shut down other external downstream components. The DAC output on/off is implemented through a feedforward trigger signal to the ramp-up/ramp-down digital gain block at the end of the main digital datapath, before the analog DAC core, which allows the DAC to be turned on or off gradually with the ramp on/off block. Rev. B | Page 56 of 145 Data Sheet CHANNEL SUMMER CHANNEL DATAPATHS BYPASSED + RAMP UP/DOWN GAIN M NCO DAC CORE AD9172 15453-037 PDP (LONG/SHORT) PDP_PROTECT ERROR TRIGGER JESD204B INTERFACE_PROTECT SOURCE ERRORS SPI_PROTECT SPI TXEN0/TXEN1 PIN SPI_TXEN TXEN BSM BSM_PROTECT FLUSH DATAPATH ENA_SPI_TXEN Figure 71. Block Diagram of Downstream Protection Triggers DATAPATH DATA SAMPLES I2 + Q2 SHORT_PA_THRESHOLD IRQ0/IRQ1 PIN SHORT AVERAGE FILTER (2.6ns, 1.0µs) AT 12GHz LONG AVERAGE FILTER (1.0µs, 1.0ms) AT 12GHz LONG_PDP_PROTECT/ SHORT_PDP_PROTECT 15453-038 LONG_PA_THRESHOLD Figure 72. PDP Block Diagram Power Detection and Protection (PDP) Block The PDP block detects the average power of the DAC input signal and prevents overrange signals from being passed to the next stage, which may potentially cause destructive breakdown on power sensitive devices, such as PAs. The protection function provides a signal, PDP_PROTECT, that can shut down the DAC outputs or be routed externally to shut down a PA. The PDP block uses a separate path with a shorter latency than the datapath to ensure that PDP_PROTECT is triggered before the overrange signal reaches the analog DAC cores (except when the total interpolation is 1×). The sum of the I2 and Q2 are calculated as a representation of the input signal power (only the top six MSBs of data samples are used). The calculated sample power numbers are accumulated through a moving average filter with an output that is the average of the input signal power in a certain number of samples. There are two types of average filters with different lengths: the short filter detects pulses with high power in the digital domain and the long filter detects high power in the digital domain, which lasts longer than the thermal constant of the PA. When the output of the averaging filter is larger than the threshold, the internal signal, PDP_PROTECT, goes high, which can optionally be configured to trigger an IRQ flag and turn off the DAC output through the ramp-up/ramp-down. The PDP block is configured as shown in Figure 72. The long and short averaging time is configured by the LONG_ PA_AVG_TIME (Register 0x585, Bits [3:0]) and the SHORT_ PA_AVG_TIME (Register 0x58A, Bits [1:0]) controls. Use the following calculations to determine the average window size times: Length of long average window = 2LONG_PP_AVG_TIME + 9 Length of short average window = 2SHORT_PA_AVG_TIME Rev. B | Page 57 of 145 AD9172 When the average calculation value exceeds a specified threshold, the ramp-down signal is triggered to ramp down the output. The thresholds for the long and short average options are programmed in the registers listed in Table 42, along with their respective detected power calculation readbacks. Table 42. PDP Threshold and Power Calculation Controls Register Bits Control 0x583 [7:0] LONG_PA_THRESHOLD[7:0] 0x584 [4:0] LONG_PA_THRESHOLD[12:8] 0x586 [7:0] LONG_PA_POWER[7:0] 0x587 [4:0] LONG_PA_POWER[12:8] 0x588 [7:0] SHORT_PA_THRESHOLD[7:0] 0x589 [4:0] SHORT_PA_THRESHOLD[12:8] 0x58B [7:0] SHORT_PA_POWER[7:0] 0x58C [4:0] SHORT_PA_POWER[12:8] Main Datapath Interpolation The main digital datapath interpolation options available are bypass (1×), 2×, 4×, 6×, 8× and 12×. Each of the half-band filters used for interpolation have 80% bandwidths with 85 dB of stop band rejection. The channel half-band cascaded configuration is shown in Figure 73, with each of the useable bandwidths of the channel interpolation filters listed in Table 43. 15453-039 HB3 2× HB4 2× TB1 3× HB5 2× Figure 73. Main Datapath Interpolation Half-Band Filter Block Diagram Table 43. Main Datapath Interpolation Useable Bandwidths and Rejection Half-Band Filter Bandwidth (×fIN_FILTER) Stop Band Rejection (dB) HB3 80% 85 HB4 40% 85 TB1 27% 85 HB5 20% 85 Main Digital Modulation The AD9172 has digital modulation features to modulate the baseband quadrature signal to a desired frequency. There are two stages of complex digital modulation available in the AD9172; channel modulation and main modulation. Each main DAC has a final main NCO that can individually modulate each main DAC datapath with a unique frequency and phase offset. The AD9172 is equipped with several NCO modes. The default NCO is a 48-bit, integer NCO. There is an additional modulus option for each main DAC datapath NCO where the A/B ratio of the dual modulus NCO allows the output frequency to be synthesized with very fine precision. NCO mode is selected as shown in Table 44. These controls are paged per the main DAC page masks, MAINDAC_PAGE (Register 0x008, Bits [7:6]). Data Sheet Table 44. Main Modulation Mode Selection Modulation Type Modulation Mode Register 0x112, Register 0x112, Bit 3 Bit 2 None 0b0 0b0 48-Bit Integer NCO 0b1 0b0 48-Bit Dual Modulus NCO 0b1 0b1 The main NCO blocks also contain sideband selection controls as well as options for how the FTW and phase offset controls are updated. Calculate the phase offset word control as follows: -180° Degrees Offset +180° Degrees Offset = 180° × (DDSM_NCO_PHASE_OFFSET/215) where DDSM_NCO_PHASE_OFFSET is a 16-bit twos complement value programmed in the registers listed in Table 45. Table 45. Main Datapath NCO Phase Offset Registers Address Value Description 0x11C DDSM_NCO_PHASE_OFFSET[7:0] 8 LSBs of phase offset 0x11D DDSM_NCO_PHASE_OFFSET [15:8] 8 MSBs of phase offset 48-Bit Dual Modulus NCO This modulation mode uses an NCO, a phase shifter, and a complex modulator to modulate the signal by a programmable carrier signal, as shown in Figure 69. This configuration allows output signals to be placed anywhere in the output spectrum up to ±fNCO/2 with very fine frequency resolution. The NCO produces a quadrature carrier to translate the input signal to a new center frequency. A quadrature carrier is a pair of sinusoidal waveforms of the same frequency, offset 90° from each other. The frequency of the quadrature carrier is set via a FTW. The quadrature carrier is mixed with the I and Q data and then summed into the I and Q datapaths, as shown in Figure 69. Integer NCO Mode The channel 48-bit NCOs can be used as integer NCOs. The FTW for the channel NCOs depends on the speed at which the main NCO block is running (fDAC), which is the same rate as the DAC sample rate (12.6 GSPS, maximum) and can be calculated by using the following formula: fDAC = fDATA × Channel Interpolation × Main Interpolation The FTWs for each individual channel can be programmed separately and are calculated using the following formula: -fDAC/2 fCARRIER < +fDAC/2 DDSM_FTW = (fCARRIER/fDAC) × 248 where DDSM_FTW is a 48-bit, twos complement number. Rev. B | Page 58 of 145 Data Sheet The frequency tuning word is set as shown in Table 46. Table 46. Main Datapath NCO FTW Registers Address Value Description 0x114 DDSM_FTW[7:0] 8 LSBs of FTW 0x115 DDSM_FTW[15:8] Next 8 bits of FTW 0x116 DDSM_FTW[23:16] Next 8 bits of FTW 0x117 DDSM_FTW[31:24] Next 8 bits of FTW 0x118 DDSM_FTW[39:32] Next 8 bits of FTW 0x119 DDSM_FTW[47:40] 8 MSBs of FTW Unlike other registers, the FTW registers are not updated immediately upon writing. Instead, the FTW registers update on the rising edge of DDSM_FTW_LOAD_REQ (Register 0x113, Bit 0). After an update request, DDSM_FTW_LOAD_ACK (Register 0x113, Bit 1) must be high to acknowledge that the FTW updated. The DDSM_SEL_SIDEBAND bit (Register 0x112, Bit 1 = 0b1) is a convenience bit that can be set to use the lower sideband modulation result, which is equivalent to flipping the sign of the FTW. I DATA INTERPOLATION DDSM_FTW[47:0] DDSM_NCO_PHASE_OFFSET [15:0] COS(n + ) NCO SIN(n + ) 1 DDSM_SEL_SIDEBAND 01 + OUT_I OUT_Q Q DATA INTERPOLATION Figure 74. NCO Modulator Block Diagram Main Datapath Modulus NCO Mode (Direct Digital Synthesis (DDS)) Each of the main datapath 48-bit NCOs can also be used in a dual modulus mode to create fractional frequencies beyond the 48-bit accuracy. The modulus mode is enabled by programming the DDSM_MODULUS_EN bit in the DDSM_DATAPATH_ CFG register to 1 (Register 0x112, Bit 2 = 0b1). The frequency ratio for the programmable modulus DDS is very similar to that of the typical accumulator based DDS. The only difference is that N is not required to be a power of two for the programmable modulus, but can be an arbitrary integer. In practice, hardware constraints place limits on the range of values for N. As a result, the modulus extends the use of the NCO to applications that require exact rational frequency synthesis. The underlying function of the programmable modulus technique is to alter the accumulator modulus. 15453-040 AD9172 Implementation of the programmable modulus function within the AD9172 is such that the fraction, M/N, is expressible by the following equation. Note that the form of the equation implies a compound frequency tuning word with X representing the integer part and A/B representing the fractional part. fCARRIER f DAC = M N = X+ A B 248 where: X is programmed in Register 0x114 to Register 0x119. A is programmed in Register 0x12A to Register 0x12F. B is programmed in Register 0x124 to Register 0x129. Programmable Modulus Example Consider the case in which fDAC = 12 GHz and the desired value of fCARRIER is 1.2 GHz. This scenario synthesizes an output frequency that is not a power of two submultiple of the sample rate, namely fCARRIER = (1/10) fNCO, which is not possible with a typical accumulator based DDS. The frequency ratio, fCARRIER/fDAC, leads directly to M and N, which are determined by reducing the fraction (1,200,000,000/12,000,000,000) to its lowest terms, that is, M/N = 1,200,000,000/12,000,000,000 = 1/10 Therefore, M = 1 and N = 10. After calculation, X = 28,147,497,671,065, A = 3, and B = 5. Programming these values into the registers for X, A, and B (X is programmed in Register 0x114 to Register 0x119 for DDSM_ FTWx, B is programmed in Register 0x124 to Register 0x129 for DDSM_ACC_MODULUSx, and A is programmed in Register 0x12A to Register 0x12F for DDSM_ACC_DELTAx) causes the NCO to produce an output frequency of exactly 1.2 GHz given a 12 GHz sampling clock. For more details, refer to the AN-953 Application Note. NCO Reset Resetting the NCO can be useful when determining the start time and phase of the NCO. The NCO can be reset by several different methods, including via an SPI write or by the SYSREF± signal. Calibration NCO There is an additional 32-bit calibration NCO option as part of the main DAC NCO block, shown in Figure 66. Register 0x1E6, Bit 0 controls whether the 32-bit calibration NCO is in use in the main datapath, or if the normal 48-bit main NCO is used. First, enable the calibration NCO accumulator by setting Register 0x1E6, Bit 2 = 1. Then, program the calibration NCO FTW in Register 0x1E2 to Register 0x1E5 and update the FTW to take effect by toggling Register 0x113, Bit 0 from 0 to 1. Select the calibration NCO to be used instead of the main NCO by setting Register 0x1E6, Bit 0 = 1 If using the calibration NCO along with the internal dc amplitude level, enable the dc amplitude injection feature by setting Register 0x1E6, Bit 1 = 1. Rev. B | Page 59 of 145 AD9172 Data Sheet Modulator Switch The final DAC NCO block has an added functionality of a modulator switch that allows the user to select the desired outputs of the NCO block. There are four mode functionalities available, as shown in Figure 75 to Figure 78. Some modes bypass the main datapath NCO for each DAC and use the DAC0 I DATA DAC0 Q DATA NCO DAC1 I DATA DAC1 Q DATA NCO complex I and Q data from each datapath, whereas other modes only use the I data output from each of the main datapath NCO blocks and select which DAC is used to output the data. These modes are programmed in Register 0x112, Bits[5:4] and are paged by the MAINDAC_PAGE register control. DAC0 NCO REAL DATA TO DAC0 CORE DAC0 MOD SWITCH MODE DAC1 MOD SWITCH MODE DAC1 NCO REAL DATA TO DAC1 CORE 15453-041 DAC0 I DATA DAC0 Q DATA DAC1 I DATA DAC1 Q DATA DAC0 I DATA DAC0 Q DATA Figure 75. Mode 0--DAC0 = I0, DAC1 = I1 NCO ÷2 ÷2 NCO SUM OF I DATA TO DAC0 CORE DAC0 MOD SWITCH MODE DAC1 MOD SWITCH MODE SUM OF Q DATA TO DAC1 CORE Figure 76. Mode 1--DAC0 = I0 + I1, DAC1 = Q0 + Q1 NCO DAC0 I DATA TO DAC0 CORE 15453-042 DAC0 MOD SWITCH MODE DAC1 MOD SWITCH MODE DAC1 I DATA DAC1 Q DATA DAC0 I DATA DAC0 Q DATA 15453-043 NCO DAC0 Q DATA TO DAC1 CORE Figure 77. Mode 2--DAC0 = I0, DAC1 = Q0 NCO ÷2 SUM OF NCOs REAL DATA TO DAC0 CORE DAC1 I DATA DAC1 Q DATA NCO ZERO DATA DAC0 MOD SWITCH MODE DAC1 MOD SWITCH MODE NO DATA TO DAC1 CORE 15453-044 Figure 78. Mode 3--DAC0 = I0 + I1, DAC1 = 0 Rev. B | Page 60 of 145 Data Sheet Ramp Up/Down Gain In each of the main datapaths, the ramp-up and ramp-down gain block is immediately before the digital datapath enters the analog DAC core for decoding. This block works in conjunction with the power detection and protection (PDP) block to protect any downstream components from large power peaks or long, high average power. Various trigger signals can be configured in the PA protection block to trigger a gain ramp-down to mute the data being transmitted out of the DAC, as shown in Figure 71. The ramp-up and ramp-down steps can be configured via the SPI in Register 0x580, Bits[2:0]. The equation for the ramp-up and ramp-down occurs in 32 steps over 2(CODE + 8) DAC clock periods. This control can be configured individually for each of the DAC ramp blocks via the MAINDAC_PAGE control in Register 0x008. AD9172 After the data is ramped down from one of the triggers, it can be ramped back up in two of the following ways after the error condition is cleared. If the SPI protection control bit triggered the interrupt for a ramp-down, the SPI is then also used to ramp the data back up by toggling Register 0x582, Bit 7 from 0 to 1, and then back to 0. Additionally, an option exists to mute the digital data during a digital clock rotation if the ROTATE_SOFT_OFF_EN control in Register 0x581, Bit 2 is set to 1. When this bit is set, the synchronization logic rotation triggers the DAC ramp-down block, rotates the digital clocks, and ramps back up. These actions only occur if Bit 1 of the ROTATION_MODE control in Register 0x03B is set to 1 to enable a datapath clock rotation when the synchronization logic rotates. Rev. B | Page 61 of 145 AD9172 Data Sheet INTERRUPT REQUEST OPERATION The AD9172 provides an interrupt request output signal (IRQ) on Ball D9 (IRQ0) and Ball E9 (IRQ1) that can be used to notify an external host processor of significant device events. The IRQ output can be switched between the IRQ0 pin or the IRQ1 pin by setting the corresponding bit for the IRQ signal in Register 0x028, Register 0x029, Register 0x02A, and Register 0x02B. Upon assertion of the interrupt, query the device to determine the precise event that occurred. The IRQx pins are open-drain, active low outputs. Pull the IRQx pins high, external to the device. These pins can be tied to the interrupt pins of other devices with open-drain outputs to wire; OR these pins together. Figure 79 shows a simplified block diagram of how the IRQx blocks works. If IRQ_EN is low, the INTERRUPT_SOURCE signal is set to 0. If IRQ_EN is high, any rising edge of EVENT causes the INTERRUPT_SOURCE signal to be set high. If any INTERRUPT_SOURCE signal is high, the IRQx pin is pulled low. INTERRUPT_SOURCE can be reset to 0 by either an IRQ_RESET signal or a DEVICE_RESET signal. Depending on the STATUS_MODE signal, EVENT_STATUS reads back an event signal or an INTERRUPT_SOURCE signal. The AD9172 has several IRQ register blocks that can monitor up to 86 events, depending on the device configuration. Certain details vary by IRQ register block, as described in Table 47. Table 48 shows the source registers of the IRQ_EN, IRQ_RESET, and STATUS_MODE signals in Figure 79, as well as the address where EVENT_STATUS is read back. Table 47. IRQ Register Block Details Register Block Event Reported EVENT_STATUS 0x020 to 0x27 Per chip INTERRUPT_SOURCE if IRQ is enabled; if not, it is an event 0x4B8 to 0x4BB; Per link and INTERRUPT_SOURCE if IRQ is 0x470 to 0x473 lane enabled; if not, 0 INTERRUPT SERVICE ROUTINE Interrupt request management starts by selecting the set of event flags that require host intervention or monitoring. Enable the events that require host action so that the host is notified when they occur. For events requiring host intervention upon IRQ activation, run the following routine to clear an interrupt request: 1. Read the status of the event flag bits that are being monitored. 2. Disable the interrupt by writing 0 to IRQ_EN. 3. Read the event source. 4. Perform any actions that may be required to clear the cause of the event. In many cases, no specific actions may be required. 5. Verify that the event source is functioning as expected. 6. Clear the interrupt by writing 1 to IRQ_RESET. 7. Enable the interrupt by writing 1 to IRQ_EN. 0 EVENT_STATUS 1 STATUS_MODE IRQ IRQ_EN 1 INTERRUPT_SOURCE EVENT 0 IRQ_EN OTHER INTERRUPT SOURCES IRQ_RESET DEVICE_RESET 15453-045 Figure 79. Simplified Schematic of IRQx Circuitry Table 48. IRQ Register Block Address of IRQ Signal Details Address of IRQ Signals1 Register Block IRQ_EN IRQ_RESET STATUS_MODE 0x020 to 0x023 0x020 to 0x023; R/W per chip 0x024 to 0x027; per chip STATUS_MODE= IRQ_EN 0x4B8 to 0x4BB 0x4B8, 0x4B9; W per error type 0x4BA, 0x4BB; W per error type Not applicable, STATUS_MODE = 1 0x470 to 0x473 0x470 to 0x473; W per error type 0x470 to 0x473; W per link Not applicable, STATUS_MODE = 1 1 R is read, W is write, and R/W is read/write. EVENT_STATUS 0x024 to 0x027; R per chip 0x4BA, 0x4BB; W per chip 0x470 to 0x473; W per link Rev. B | Page 62 of 145 Data Sheet APPLICATIONS INFORMATION HARDWARE CONSIDERATIONS Power Supply Recommendations All the AD9172 supply domains must remain as noise free as possible for the best operation. Power supply noise has a frequency component that affects performance, and is specified in V rms. An LC filter on the output of the power supply is recommended to attenuate the noise, and must be placed as close to the AD9172 as possible. The AVDD1.0 supply, which supplies the clock receiver and DAC analog core circuitry, and the AVDD1.8 supply, which powers the DAC output and DAC PLL blocks, are the most noise sensitive supplies on the device. It is highly recommended that AVDD1.0 and AVDD1.8 be supplied separately with ultralow noise regulators, such as the ADP1763 and ADM7154 or better to achieve the best phase noise performance possible. Noisier regulators impose phase noise onto the DAC output. The DVDD1.0 supply provides power to the digital datapath blocks and the SVDD1.0 supply powers the SERDES circuitry on the chip. The DVDD1.8 supply powers circuitry blocks related to the SPI, SYNCOUTx± transmitter, SYSREF receiver, IRQx, RESET, and TXENx circuitry. Take note of the maximum power consumption numbers shown in Table 4 to ensure the power supply design can tolerate temperature and IC process variation extremes. The amount of current drawn is dependent on the chosen use cases, and specifications are provided for several use cases to illustrate examples and contributions from individual blocks, and to assist in calculating the maximum required current per supply. Another consideration for the power supply design is peak current handling capability. The AD9172 draws more current in the main digital supply when synthesizing a signal with significant amplitude variations, such as a modulated signal, as compared to when in idle mode or synthesizing a dc signal. Therefore, the power supply must be able to supply current quickly to accommodate burst signals such as GSM, TDMA, or other signals that have an on or off time domain response. Because the amount of current variation depends on the signals used, it is best to perform lab testing first to establish ranges. A typical difference can be several hundred milliamperes. Power and Ground Planes Solid ground planes are recommended to avoid ground loops and to provide a solid, uninterrupted ground reference for the high speed transmission lines that require controlled impedances. It is recommended that power planes be stacked between ground layers for high frequency filtering. Doing so adds extra filtering and isolation between power supply domains in addition to the decoupling capacitors. AD9172 Do not use segmented power planes as a reference for controlled impedances unless the entire length of the controlled impedance trace traverses across only a single segmented plane. These and additional guidelines for the topology of high speed transmission lines are described in the JESD204B Serial Interface Inputs (SERDIN0± to SERDIN7±) section. For some applications, where highest performance and higher output frequencies are required, the choice of PCB materials significantly impacts results. For example, materials such as polyimide or materials from the Rogers Corporation can be used, for example, to improve tolerance to high temperatures and improve performance. Rogers 4350 material is used for the top three layers in some of the evaluation board designs: between the top signal layer and the ground layer below it. JESD204B Serial Interface Inputs (SERDIN0± to SERDIN7±) When considering the layout of the JESD204B serial interface transmission lines, there are many factors to consider to maintain optimal link performance. Among these factors are insertion loss, return loss, signal skew, and the topology of the differential traces. Insertion Loss The JESD204B specification limits the amount of insertion loss allowed in the transmission channel (see Figure 50). The AD9172 equalization circuitry allows significantly more loss in the channel than is required by the JESD204B specification. It is still important that the designer of the PCB minimize the amount of insertion loss by adhering to the following guidelines: · Keep the differential traces short by placing the AD9172 as close to the transmitting logic device as possible and routing the trace as directly as possible between the devices. · Route the differential pairs on a single plane using a solid ground plane as a reference. It is recommended to route the SERDES lanes on the same layer as the AD9172 to avoid vias being used in the SERDES lanes. · Use a PCB material with a low dielectric constant (<4) to minimize loss, if possible. When choosing between the stripline and microstrip techniques, keep in mind the following considerations: stripline has less loss (see Figure 51 and Figure 52) and emits less EMI, but requires the use of vias that can add complexity to the task of controlling the impedance; whereas microstrip is easier to implement (if the component placement and density allow routing on the top layer) and eases the task of controlling the impedance. Rev. B | Page 63 of 145 AD9172 Data Sheet 15453-047 If using the top layer of the PCB is problematic or the advantages of stripline are desirable, follow these recommendations: Minimize the number of vias. If possible, use blind vias to eliminate via stub effects and use microvias to minimize via inductance. If using standard vias, use the maximum via length to minimize the stub size. For example, on an 8-layer board, use Layer 7 for the stripline pair (see Figure 80). For each via pair, place a pair of ground vias adjacent to them to minimize the impedance discontinuity (see Figure 80). LAYER 1 LAYER 2 LAYER 3 LAYER 4 LAYER 5 ADD GROUND VIAS DIFF STANDARD VIA DIFF+ GND y y y LAYER 6 LAYER 7 GND 15453-046 LAYER 8 MINIMIZE STUB EFFECT Figure 80. Minimizing Stub Effect and Adding Ground Vias for Differential Stripline Traces Return Loss complex. However, follow the 10 mm guideline for length matching. The AD9172 can handle more skew than the 85% UI due to the 6 PCLK buffer in the JESD204B receiver, but matching the channel lengths as close as possible is still recommended. Topology Structure the differential SERDINx± pairs to achieve 50 to ground for each half of the pair. Stripline vs. microstrip tradeoffs are described in the Insertion Loss section. In either case, it is important to keep these transmission lines separated from potential noise sources, such as high speed digital signals and noisy supplies. If using stripline differential traces, route them using a coplanar method, with both traces on the same layer. Although this method does not offer more noise immunity than the broadside routing method (traces routed on adjacent layers), it is easier to route and manufacture so that the impedance continuity is maintained. Broadside vs. coplanar differential Tx lines are shown in Figure 81. Tx DIFF A Tx DIFF B Tx ACTIVE Tx Tx Tx DIFF A DIFF B ACTIVE The JESD204B specification limits the amount of return loss allowed in a converter device and a logic device but does not specify return loss for the channel. However, make every effort to maintain a continuous impedance on the transmission line between the transmitting logic device and the AD9172. Minimizing the use of vias, or eliminating them entirely, reduces one of the primary sources for impedance mismatches on a transmission line (see the Insertion Loss section). Maintain a solid reference beneath (for microstrip) or above and below (for stripline) the differential traces to ensure continuity in the impedance of the transmission line. If the stripline technique is used, follow the guidelines listed in the Insertion Loss section to minimize impedance mismatches and stub effects. Another primary source for impedance mismatch is at either end of the transmission line, where care must be taken to match the impedance of the termination to that of the transmission line. The AD9172 handles this matching internally with a calibrated termination scheme for the receiving end of the line. See the Interface Power-Up and Input Termination section for details on this circuit and the calibration routine. Signal Skew BROADSIDE DIFFERENTIAL Tx LINES COPLANAR DIFFERENTIAL Tx LINES Figure 81. Broadside vs. Coplanar Differential Stripline Routing Techniques When considering the trace width vs. copper weight and thickness, the speed of the interface must be considered. At multigigabit speeds, the skin effect of the conducting material confines the current flow to the surface. Maximize the surface area of the conductor by making the trace width wider to reduce the losses. Additionally, loosely couple differential traces to accommodate the wider trace widths. This coupling helps reduce the crosstalk and minimize the impedance mismatch when the traces must separate to accommodate components, vias, connectors, or other routing obstacles. Tightly coupled vs. loosely coupled differential traces are shown in Figure 82. Tx Tx DIFF A DIFF B Tx DIFF A Tx DIFF B 15453-048 TIGHTLY COUPLED DIFFERENTIAL Tx LINES LOOSELY COUPLED DIFFERENTIAL Tx LINES Figure 82. Tightly Coupled vs. Loosely Coupled Differential Traces There are many sources for signal skew, but the two sources to consider when laying out a PCB are interconnect skew within a single JESD204B link and skew between multiple JESD204B links. In each case, keeping the channel lengths matched to within 10 mm (calculated by 12.5 mm × (12.5 Gbps/15 Gbps)) is adequate for operating the JESD204B link at speeds of up to 15 Gbps. This amount of channel length match is equivalent to about 85% UI on the AD9172 evaluation board. Managing the AC Coupling Capacitors The AD9172 requires that the JESD204B input signals be ac-coupled to the source. These capacitors must be 100 nF and placed as close as possible to the transmitting logic device. To minimize the impedance mismatch at the pads, select the package size of the capacitor so that the pad size on the PCB matches the trace width as closely as possible. interconnect skew within a single link is straightforward. Managing multiple links across multiple devices is more Rev. B | Page 64 of 145 Data Sheet SYNCOUT±, SYSREF±, and CLK± Signals The SYSREF± signal on the AD9172 is a low speed, LVDS, differential signal. The SYNCOUTx± signals are LVDS or CMOS selectable. When LVDS mode is selected, use controlled impedance traces routed as 100 differential impedance and 50 to ground when routing these signals. As with the SERDIN0± to SERDIN7± data pairs, it is important to keep these signals separated from potential noise sources, such as high speed digital signals and noisy supplies. Separate the AD9172 SYNCOUTx± signal from other noisy signals because noise on the SYNCOUTx± may be interpreted as a request for /K/ characters. It is important to keep similar trace lengths for the CLK± and SYSREF± signals from the clock source to each of the devices on either end of the JESD204B links (see Figure 83). If using a clock chip that can tightly control the phase of CLK± and SYSREF±, the trace length matching requirements are greatly reduced. Tx DEVICE LANE 0 LANE 1 LANE N 1 LANE N Rx DEVICE SYSREF± SYSREF± CLOCK SOURCE (AD9516-1, ADCLK925) DEVICE CLOCK DEVICE CLOCK SYSREF± TRACE LENGTH SYSREF± TRACE LENGTH DEVICE CLOCK TRACE LENGTH DEVICE CLOCK TRACE LENGTH Figure 83. SYSREF± Signal and Device Clock Trace Length 15453-049 Rev. B | Page 65 of 145 AD9172 Data Sheet ANALOG INTERFACE CONSIDERATIONS DAC INPUT CLOCK CONFIGURATIONS The AD9172 DAC sample clock or device clock (DACCLK) can be sourced directly through CLKIN± (Pin H12 and Pin J12) or by using the on-chip, integrated, integer PLL VCO with the same CLKIN± differential input serving as the reference. Clock multiplying employs the on-chip DAC PLL that accepts a reference clock operating at a submultiple of the desired DACCLK rate. The PLL then multiplies the reference clock up to the desired DACCLK frequency, which generates all the clocks within the AD9172, as shown in Figure 86. The AD9172 contains a low jitter, differential clock receiver that is capable of interfacing directly to a differential or single-ended clock source. Because the input is self biased with a nominal impedance of 100 , it is recommended that the clock source be ac-coupled to the CLKIN± input pins. Improved phase noise performance can be achieved with a higher clock input level. The quality of the clock source, as well as its interface to the AD9172 clock input, directly impacts ac performance. Select the phase noise and spur characteristics of the clock source to meet the target application requirements. TO DAC0 DUTY CYCLE RESTORE/CROSS CONTROL CLK+ 50 50 CLK + 170k 170k CLOCK/ PLL MUX TO PLL REFERENCE INPUT FROM PLL CLOCK/ PLL MUX OPTIMIZED INPUT BIAS DUTY CYCLE RESTORE/CROSS CONTROL TO DAC1 15453-050 Figure 84. Clock Receiver Input Simplified Equivalent Circuit 0 PLL OFF (DIRECT CLOCK) PLL ON (PFD = 491.52MHz) 20 40 PHASE NOISE (dBc) 60 80 100 120 140 160 15453-102 180 10 100 1k 10k 100k 1M 10M 100M FREQUENCY OFFSET (Hz) Figure 85. Phase Noise vs. Frequency Offset; Direct Clock and PLL Phase Noise, 12 GHz DAC Sample Rate, 1.65 GHz Output Frequency Rev. B | Page 66 of 145 Data Sheet AD9172 DAC On-Chip PLL over temperature. Set the PLL filter bandwidth such that the When using the on-chip PLL, the predivider setting is selected (via Register 0x793, Bits[1:0]) to divide the clock receiver frequency internally to be within the range of 25 MHz to in-band noise of the PLL intersects with the open-loop noise of the VCO, minimizing the contribution of both to the overall noise. 770 MHz for the phase frequency detector (PFD) circuitry The DAC PLL uses an integer type synthesizer to achieve the block input. DAC sampling clock. The relation between DAC clock and the The AD9172 DAC VCO operates over a frequency range of reference clock is as follows: 8.74 GHz to 12.4 GHz. Enable the DAC PLL synthesizer by fDAC = (8 × N × fREF)/M/(Register 0x094, Bits[1:0] + 1) setting Register 0x095, Bit 0 to 0. The DAC clock rate is user configurable to be the VCO frequency (8.74 GHz to 12.4 GHz), the VCO frequency divided by 2 (4.37 GHz to 6.2 GHz), or the VCO frequency divided by 3 (2.92 GHz to 4.1 GHz) by setting Register 0x094, Bits[1:0]. See the Startup sequence section for instructions on how to program the PLL. where: fDAC is the desired DAC clock rate. N is the VCO feedback divider ratio, ranging from 2 to 50. fREF is the reference clock. M is the reference clock divider ratio; the valid values for reference clock divider (predivider) are 1, 2, 3, or 4 by setting The AD9172 DAC PLL requires an external loop filter. The Register 0x793, Bits[1:0]. recommended filter is a standard passive filter, as shown in Figure 86. The user can customize the filter according to the PFD frequency, reference clock phase noise, and DAC output phase noise requirements. For lowest jitter applications, use the highest possible PFD frequency to minimize the contribution of in-band noise from the PLL. However, when operating with a The VCO automatic calibration is triggered by the falling edge of Register 0x792, Bit 1 transitioning from a logic high to logic low. A lock detector bit (Register 0x7B5, Bit 0) is provided to indicate that the DAC PLL achieved lock. If Register 0x7B5, Bit 0 = 1, the PLL has locked. VCO frequency from 9.96 GHz to 10.87 GHz, set the PFD frequency to less than 225 MHz to ensure optimized stability OFF-CHIP FILTER FILT_VCM C1 PFD CHARGE PUMP R1 C2 FILT_FINE C3 PCB FILT_COARSE REG 0x799, BITS[5:0] N = 2 TO 50 REG 0x793, BITS[1:0] M = 1, 2, 3, 4 ÷M CLK RCVR ÷N ÷8 REG 0x799, BITS[7:6] L = 1, 2, 3, 4 ÷L VCO REG 0x094, BITS[1:0] DAC ÷3 REG 0x095, BIT 0 ÷2 DACCLK CLKIN+ CLKIN CLK DRIVER CLKOUT+ CLKOUT+ PCB 15453-051 Figure 86. DAC PLL and Clock Path Block Diagram Rev. B | Page 67 of 145 AD9172 Data Sheet CLOCK OUTPUT DRIVER The AD9172 is capable of generating and outputting a high performance divide down clock that can be used to clock a companion analog-to-digital converter (ADC). The integer clock divider supports divide ratios 1, 2, 3, and 4 and can be programmed by Register 0x799, Bits[7:6] to set the desired output frequency. The output frequency ranges from 727.5 MHz to 3 GHz. ANALOG OUTPUTS The AD9172 provides complementary current outputs, DAC0± and DAC1±. Figure 87 shows an equivalent output circuit for the DAC. The AD9172 features an internal 100 termination resistor (RINT) that eliminates the need to terminate the DAC current output externally on the PCB board. Two RF chokes, one for each DAC output leg, are required to provide a dc current path for the DAC output. The value of the choke depends on the desired output frequency range. In general, a larger choke provides a lower cutoff output frequency. A 2:1 balun is recommended to transform the differential DAC output to a single-ended signal. IOUTFS is the full-scale current of each of the two DAC outputs. It is an 8-bit value stored in Register 0x05A. The full-scale current of the DAC is typically 19.531 mA. The DAC full-scale current can be adjusted from 15.625 mA to 25.977 mA by programming the appropriate value in Register 0x05A. IOUTFS = 15.625 mA + FSC_CTRL × (25/256) (mA) The example shown in Figure 87 can be modeled as a pair of dc current sources that source half of the IOUTFS current to each output. This differential ac current source models the signal (that is, a digital code) dependent nature of the DAC output. The ac differential current measured at DACx+ and DACx- is as follows: IAC_DIFF (mA) = DACCODE/DACCODEMAX × IOUTFS × RINT(RLOAD + RINT) where: DACCODE = 0 to 65,535 (decimal). RLOAD is the load impedance seen on DACx+ and DACx-. DAC DC IOUTFS/2 RF CHOKE BALUN 50 AC IAC 50 DACx+ DACx 2:1 100:50 50 LOAD DC IOUTFS/2 RF CHOKE 15453-052 IOUTFS = 15.625mA TO 25.977mA Figure 87. Equivalent DAC Output Circuit and Recommended DAC Output Network Rev. B | Page 68 of 145 Data Sheet START-UP SEQUENCE Several steps are required to program the AD9172 to the proper operating state after the device is powered up. This sequence is divided into several steps, and is listed in Table 49 to Table 58, along with an explanation of the purpose of each step. Private AD9172 registers are reserved but must be written for proper operation. Blank cells or cells with a variable or bit field name (in all capital letters) in Table 49 to Table 58 indicate that the value depends on the result as described in the Description column. Table 49. Power-Up and Required Register Writes R/W Register Bits Value Description W 0x000 [7:0] 0x81 Soft reset. W 0x000 [7:0] 0x3C Release reset and set to 4-wire SPI (optional; leave at the default of the 3-wire SPI). W 0x091 [7:0] 0x00 Power up clock receiver. W 0x206 [7:0] 0x01 Take PHYs out of reset. W 0x705 [7:0] 0x01 Enable boot loader. W 0x090 [7:0] 0x00 Power on DACs and bias circuitry. Table 50. DAC PLL Configuration R/W Register Bits Value W 0x095 [7:0] 0x00 or 0x01 W 0x790 W 0x791 [7:0] 0xFF or 0x00 [7:0] 0x1F or 0x00 W 0x796 [7:0] 0xE5 W 0x7A0 [7:0] 0xBC W 0x794 [5:0] DACPLL_CP W 0x797 [7:0] 0x10 W 0x797 [7:0] 0x20 W 0x798 [7:0] 0x10 W 0x7A2 [7:0] 0x7F Pause W 0x799 [7:6] ADC_CLK_DIVIDER W 0x793 [5:0] N_DIVIDER [7:2] 0x06 [1:0] M_DIVIDER-1 Description Bypass PLL. Set to 0x00 to use internal DAC PLL. If the user plans to supply the DAC clock directly, set this register to 0x01 and execute the following two register writes; then, skip the remaining writes in this table. Write this register to 0xFF if bypassing the PLL (Register 0x095 = 0x01). If using the PLL, write this register to 0x00. Write this register to 0xFF if bypassing the PLL (Register 0x095 = 0x01) and then skip the remaining register writes in this table and continue to Table 51. If using the PLL, write this register to 0x00 as well as the remainder of the register writes in this table. DAC PLL required write. DAC PLL required write. Set DAC PLL charge pump current. The recommended setting is 0x08, but can range from 0x04 to 0x10 for different phase noise performance targets. DAC PLL required write. DAC PLL required write. DAC PLL required write. DAC PLL required write. Wait 100 ms. DAC PLL divider settings. ADC driver/clock output divide ratio. 0b00 = ÷1. 0b01 = ÷2. 0b10 = ÷3. 0b11 = ÷4. Programmable N divider. N_DIVIDER = (fDAC × M_DIVIDER)/(8 × reference clock). DAC PLL divider settings. Keep default value for these bits. Programmable predivider M_DIVIDER-1 (in n - 1 notation). The relevant calculation is as follows: PFD Frequency = reference clock/M_DIVIDER, where 25 MHz PFD frequency 770 MHz. If 9.96 GHz PLL VCO frequency 10.87 GHz, must keep 25 MHz PFD frequency 225 MHz. 0b00 = ÷1. 0b01 = ÷2. 0b10 = ÷3. 0b11 = ÷4. Rev. B | Page 69 of 145 AD9172 Data Sheet R/W Register Bits Value Description W 0x094 [7:2] 0x00 Keep default value for these bits. 1 PLL_VCO_DIV3_EN Enable PLL output clock to be divided by 3. If this bit is set to 1, DAC clock = PLL VCO frequency/3. 0 PLL_VCO_DIV2_EN Enable PLL output clock to be divided by 2. Either this bit or Bit 1 in this register can be set to 1, but both bits cannot be set at the same time (there is no divide by 6 option). 0b0: DAC clock = PLL VCO frequency. 0b1: DAC clock = PLL VCO frequency/2. W 0x792 [7:0] 0x02 Reset VCO. W 0x792 [7:0] 0x00 Pause Wait 100 ms for PLL to lock. R 0x7B5 0 0b1 Ensure PLL is locked by reading back a value of 1 for bit 0 of this register. Table 51. Delay Lock Loop (DLL) Configuration R/W Register Bits Value Description W 0x0C0 [7:0] 0x00 Power-up delay line. W 0x0DB [7:0] 0x00 W 0x0DB [7:0] 0x01 Update DLL settings to circuitry. W 0x0DB [7:0] 0x00 W 0x0C1 [7:0] 0x68 or 0x48 Set DLL search mode. If fDAC is < 4.5 GHz, set this register to 0x48. Otherwise, set this register to 0x68. W 0x0C1 [7:0] 0x69 or 0x49 Set DLL search mode. If fDAC is < 4.5 GHz, set this register to 0x49. Otherwise, set this register to 0x69. W 0x0C7 [7:0] 0x01 Enable DLL read status. R 0x0C3 0 0b1 Ensure DLL is locked by reading back a value of 1 for Bit 0 of this register. Table 52. Calibration R/W Register W 0x050 W 0x061 W 0x051 W 0x051 W 0x081 Bits Value [7:0] 0x2A [7:0] 0x68 [7:0] 0x82 [7:0] 0x83 [7:0] 0x03 Description Optimized calibration setting register write. Required calibration control register write. Optimized calibration setting register write. Required calibration control register write. Required calibration control register write. Table 53. JESD204B Mode Setup R/W Register Bits Value W 0x100 [7:0] 0x00 W 0x110 [5:0] JESD_MODE W 0x111 [7:4] DP_INTERP_MODE [3:0] CH_INTERP_MODE W 0x084 6 SYSREF_INPUTMODE W 0x312 0 SYSREF_PD [7:4] Description Power up digital datapath clocks when internal clocks are stable. Bit 5 of the JESD_MODE bit field determines whether the device is operating in single link or dual link modes. 0 = single-link mode; 1 = dual-link mode. Bits[4:0] determine the SERDES JESD204B mode of operation chosen from the appropriate single-link or dual-link modes in Table 15 or Table 16. Main datapath interpolation mode. The valid interpolation options for this control is based on the JESD_MODE selected in Register 0x110. Bit 7 of Register 0x110 equals 1 if the JESD_MODE, DP_INTERP_MODE, and CH_INTERP_MODE settings are not a valid combination. Channel datapath interpolation mode. The valid interpolation options for this control is based on the JESD_MODE selected in Register 0x110. Bit 7 of Register 0x110 equals 1 if the JESD_MODE, DP_INTERP_MODE, and CH_INTERP_MODE settings are not a valid combination. SYSREF± signal input mode selection. 0b0 = ac-coupled. 0b1 = dc-coupled. If using Subclass 0, this bit can be set to 1 to power down the SYSREF± receiver. If using Subclass 1, keep at the default of 0. Set SYNCOUTx± error duration, depending on the selected mode. Rev. B | Page 70 of 145 Data Sheet R/W Register Bits Value W 0x300 3 LINK_MODE 2 0b0 [1:0] LINK_EN W 0x475 W 0x453 [7:0] 0x09 7 SCR W 0x458 W 0x475 W 0x300 [4:0] L-1 [7:5] SUBCLASSV [4:0] NP-1 [7:0] 0x01 3 LINK_MODE 2 0b1 W 0x475 W 0x453 [1:0] 0b00 [7:0] 0x09 7 SCR W 0x458 W 0x475 [4:0] L-1 [7:5] SUBCLASSV [4:0] NP-1 [7:0] 0x01 AD9172 Description Corresponds to the mode selection made in Register 0x110. 0b0 = single-link mode. 0b1 = dual-link mode. Select Link 0 for setup. This bit selects the link QBD being paged. 0b0 = Link 0 (QBD0). 0b1 = Link 1 (QBD1). Enables the links. 0b01 = single-link mode. 0b11 = dual link mode. Soft reset the JESD204B quad-byte deframer. Set scrambling option for SERDES data. 0 = disable scrambling. 1 = enable scrambling. Write the L value (in n - 1 notation) for the selected JESD_MODE. For Subclass 0, set this bit to 0. For Subclass 1, set this bit to 1. Write the NP value (in n - 1 notation) for the selected JESD_MODE. Bring the JESD204B quad-byte deframer out of reset. If running in dual link mode, repeat writes for Link 1 as follows. If running in single-link mode, skip the remaining steps in this table. Corresponds to the mode selection made in Register 0x110. 0b0 = single-link mode. 0b1 = dual link mode. Select Link 1 for setup. This bit selects which link QBD is being paged. 0b0 = Link 0 (QBD0). 0b1 = Link 1 (QBD1). Keep links disabled until end of routine. Soft reset the JESD204B quad-byte deframer. Set scrambling option for SERDES data. 0 = disable scrambling. 1 = enable scrambling. Write the L value (in n - 1 notation) for the selected JESD_MODE. For Subclass 0, set this bit to 0. For Subclass 1, set this bit to 1. Write the NP value (in n - 1 notation) for the selected JESD_MODE. Bring the JESD204B quad-byte deframer out of reset. Rev. B | Page 71 of 145 AD9172 Data Sheet Table 54 lists optional registers to configure the channel datapaths if they are being configured for a specific application. If the channel datapaths are bypassed (CH_INTERP_MODE = 1 for 1× channel interpolation), Table 54 can be skipped in the start-up sequence. Table 54. Channel Datapath Setup: Digital Gain and Channel NCOs R/W Register Bits Value Description W 0x008 [5:0] CHANNEL_PAGE. Select the channels to be programmed at the same time (or repeat this block for each channel to independently program values). Bit x of this control corresponds to the Channel x datapath. W 0x146 [7:0] CHNL_GAIN[7:0]. Write LSBs of channel digital gain. Configure digital gain for selected channels in Paging Register 0x008. Calculation: CHNL_GAIN = 211 × 10(dBGain/20) where dBGain is the gain value in dB for the channel gain desired. W 0x147 [7:0] CHNL_GAIN[11:8]. Write MSBs of channel digital gain. Calculations shown in Register 0x146. W 0x130 6 Enable NCO for selected channels in paging Register 0x008. 0b0 = disable NCO. 0b1 = enable NCO. 2 Enable NCO modulus for selected channels in paging Register 0x008. 0b0 = disable NCO modulus. 0b1 = enable NCO modulus. 1 Select sideband from modulation result. 0b0 = upper sideband. 0b1 = lower sideband (spectral flip). 0 If dc test mode or NCO test mode is desired, set this bit to 1 to enable the test tone generation. Otherwise, set this bit to the default value of 0. Integer NCO mode calculation: DDSC_FTW = (fCARRIER/fNCO) × 248, where fNCO = fDATA/CH_INTERP_MODE. W 0x132 [7:0] Write DDSC_FTW[7:0]. W 0x133 [7:0] Write DDSC_FTW[15:8]. W 0x134 [7:0] Write DDSC_FTW[23:16]. W 0x135 [7:0] Write DDSC_FTW[31:24]. W 0x136 [7:0] Write DDSC_FTW[39:32]. W 0x137 [7:0] Write DDSC_FTW[47:40]. W 0x138 [7:0] Write DDSC_NCO_PHASE_OFFSET[7:0]. Calculation: DDSC_NCO_PHASE_OFFSET = (Degrees Offset/180) × 215. W 0x139 [7:0] Write DDSC_NCO_PHASE_OFFSET[15:8]. If using NCO modulus mode, also program modulus parameters. If not, skip this section. For modulus NCO mode: (fCARRIER/fNCO) = (X + (A/B))/248 where DDSC_ACC_DELTA = A, DDSC_ACC_MODULUS = B, and DDSC_FTW = X. W 0x13A [7:0] Write DDSC_ACC_MODULUS[7:0]. W 0x13B [7:0] Write DDSC_ACC_MODULUS[15:8]. W 0x13C [7:0] Write DDSC_ACC_MODULUS[23:16]. W 0x13D [7:0] Write DDSC_ACC_MODULUS[31:24]. W 0x13E [7:0] Write DDSC_ACC_MODULUS[39:32]. W 0x13F [7:0] Write DDSC_ACC_MODULUS[47:40]. W 0x140 [7:0] Write DDSC_ACC_DELTA[7:0]. W 0x141 [7:0] Write DDSC_ACC_DELTA[15:8]. W 0x142 [7:0] Write DDSC_ACC_DELTA[23:16]. W 0x143 [7:0] Write DDSC_ACC_DELTA[31:24]. W 0x144 [7:0] Write DDSC_ACC_DELTA[39:32]. W 0x145 [7:0] Write DDSC_ACC_DELTA[47:40]. W 0x131 0 0b1 Update all NCO phase and FTW words. Rev. B | Page 72 of 145 Data Sheet AD9172 Table 55 lists optional registers to configure the main DAC datapaths if they are being configured for a specific application. If the main DAC datapaths are bypassed (DP_INTERP_MODE = 1 for 1× channel interpolation), Table 55 can be skipped in the start-up sequence. Table 55. Main DAC Datapath Setup: PA Protect and Main NCOs R/W Register Bits Value Description W 0x008 [7:6] MAINDAC_PAGE. Select the main DAC datapath to be programmed at the same time (or repeat this block for each DAC datapath to independently program values). Bit x of this control corresponds to the DAC x datapath. W 0x112 3 Enable NCO for selected channels in paging Register 0x008. 0b0 = disable NCO. 0b1 = enable NCO. 2 Enable NCO modulus for selected channels in paging Register 0x008. 0b0 = disable NCO modulus. 0b1 = enable NCO modulus. 1 Select sideband from modulation result. 0b0 = upper sideband. 0b1 = lower sideband (spectral flip). 0 Set this bit to 0. Integer NCO mode calculation: DDSM_FTW = (fCARRIER/fDAC) × 248. W 0x114 [7:0] Write DDSM_FTW[7:0]. W 0x115 [7:0] Write DDSM_FTW[15:8]. W 0x116 [7:0] Write DDSM_FTW[23:16]. W 0x117 [7:0] Write DDSM_FTW[31:24]. W 0x118 [7:0] Write DDSM_FTW[39:32]. W 0x119 [7:0] Write DDSM_FTW[47:40]. W 0x11C [7:0] Write DDSM_NCO_PHASE_OFFSET[7:0]. Calculation: DDSM_NCO_PHASE_OFFSET = (degrees offset/180) × 215. W 0x11D [7:0] Write DDSM_NCO_PHASE_OFFSET[15:8]. If using NCO modulus mode, also program modulus parameters. If not, skip this section. For modulus NCO mode: (fCARRIER/fDAC) = (X + (A/B))/248, where DDSM_ACC_DELTA = A, DDSM_ACC_MODULUS = B, and DDSM_FTW = X. W 0x124 [7:0] Write DDSM_ACC_MODULUS[7:0]. W 0x125 [7:0] Write DDSM_ACC_MODULUS[15:8]. W 0x126 [7:0] Write DDSM_ACC_MODULUS[23:16]. W 0x127 [7:0] Write DDSM_ACC_MODULUS[31:24]. W 0x128 [7:0] Write DDSM_ACC_MODULUS[39:32]. W 0x129 [7:0] Write DDSM_ACC_MODULUS[47:40]. W 0x12A [7:0] Write DDSM_ACC_DELTA[7:0]. W 0x12B [7:0] Write DDSM_ACC_DELTA[15:8]. W 0x12C [7:0] Write DDSM_ACC_DELTA[23:16]. W 0x12D [7:0] Write DDSM_ACC_DELTA[31:24]. W 0x12E [7:0] Write DDSM_ACC_DELTA[39:32]. W 0x12F [7:0] Write DDSM_ACC_DELTA[47:40]. W 0x113 0 0b1 Update all NCO phase and FTW words. Rev. B | Page 73 of 145 AD9172 Data Sheet Table 56. JESD204B SERDES Required Interface Setup R/W Register Bits Value Description W 0x240 [7:0] 0xAA or 0xFF EQ settings determined by amount of insertion loss according to Table 22. For insertion loss 11 dB, set to 0xAA; otherwise, set to 0xFF. W 0x241 [7:0] 0xAA or 0xFF EQ settings determined by amount of insertion loss according to Table 22. For insertion loss 11 dB, set to 0xAA; otherwise, set to 0xFF. W 0x242 [7:0] 0x55 or 0xFF EQ settings determined by amount of insertion loss according to Table 22. For insertion loss 11 dB, set to 0x55; otherwise, set to 0xFF. W 0x243 [7:0] 0x55 or 0xFF EQ settings determined by amount of insertion loss according to Table 22. For insertion loss 11 dB, set to 0x55; otherwise, set to 0xFF. W 0x244 [7:0] 0x1F EQ settings. W 0x245 [7:0] 0x1F EQ settings. W 0x246 [7:0] 0x1F EQ settings. W 0x247 [7:0] 0x1F EQ settings. W 0x248 [7:0] 0x1F EQ settings. W 0x249 [7:0] 0x1F EQ settings. W 0x24A [7:0] 0x1F EQ settings. W 0x24B [7:0] 0x1F EQ settings. W 0x201 [7:0] Power down unused PHYs. Bit x corresponds to SERDINx± pin power-down. W 0x203 If in single-link mode, set to 0x01. If in dual-link mode and using both SYNCOUTx± signals, set to 0x00. 1 0b0 Power up SYNCOUT0± driver by setting this bit to 0. 0 Power up SYNCOUT1± driver by setting this bit to 0 if using dual link and both SYNCOUTx± signals. W 0x253 [7:0] 0x01 Set SYNCOUT0± to be LVDS output. For CMOS output on SYNCOUT0+, set Bit 0 to 0. W 0x254 [7:0] 0x01 Set SYNCOUT1± to be LVDS output. For CMOS output on SYNCOUT1+, set Bit 0 to 0. W 0x210 [7:0] 0x16 SERDES required register write. W 0x216 [7:0] 0x05 SERDES required register write. W 0x212 [7:0] 0xFF SERDES required register write. W 0x212 [7:0] 0x00 SERDES required register write. W 0x210 [7:0] 0x87 SERDES required register write. W 0x216 [7:0] 0x11 SERDES required register write. W 0x213 [7:0] 0x01 SERDES required register write. W 0x213 [7:0] 0x00 SERDES required register write. W 0x200 [7:0] 0x00 Power up the SERDES circuitry blocks. Pause Wait 100 ms. W 0x210 [7:0] 0x86 SERDES required register write. W 0x216 [7:0] 0x40 SERDES required register write. W 0x213 [7:0] 0x01 SERDES required register write. W 0x213 [7:0] 0x00 SERDES required register write. W 0x210 [7:0] 0x86 SERDES required register write. W 0x216 [7:0] 0x00 SERDES required register write. W 0x213 [7:0] 0x01 SERDES required register write. W 0x213 [7:0] 0x00 SERDES required register write. W 0x210 [7:0] 0x87 SERDES required register write. W 0x216 [7:0] 0x01 SERDES required register write. W 0x213 [7:0] 0x01 SERDES required register write. W 0x213 [7:0] 0x00 SERDES required register write. W 0x280 [7:0] 0x05 SERDES required register write. W 0x280 [7:0] 0x01 Start up SERDES PLL circuitry blocks and initiate SERDES PLL calibration. R 0x281 0 0b1 Ensure Bit 0 of this register reads back 1 to indicate the SERDSES PLL is locked. Rev. B | Page 74 of 145 Data Sheet AD9172 Crossbar mapping writes the SERDINx input pin that is the source for each given logical lane in these registers. A value of x corresponds to mapping data from the SERDINx± pin to the logical lane of the control bit field. These values in Table 57 vary with different PCB layout routing. Table 57. Transport Layer Setup, Synchronization, and Enable Links R/W Register Bits Value Description W 0x308 [7:0] Crossbar setup. Program the physical lane value that is providing data (the source) for each of the logical lanes. [5:3] = Logical Lane 1 source, [2:0] = Logical Lane 0 source. W 0x309 [7:0] [5:3] = Logical Lane 3 source, [2:0] = Logical Lane 2 source. W 0x30A [7:0] [5:3] = Logical Lane 5 source, [2:0] = Logical Lane 4 source. W 0x30B [7:0] [5:3] = Logical Lane 7 source, [2:0] = Logical Lane 6 source. W 0x306 [7:0] 0x0C If operating in Subclass 0, this register write is not needed. W 0x307 [7:0] 0x0C If operating in Subclass 0, this register write is not needed. W 0x304 [7:0] If operating in Subclass 0, this register write is not needed. For Subclass 1, these values must be determined by following one of the deterministic latency methods (with or without known delays), as mentioned in the Link Delay section. W 0x305 [7:0] If operating in Subclass 0, this register write is not needed. For Subclass 1, these values must be determined by following one of the deterministic latency methods (with or without known delays), as mentioned in the Link Delay section. W 0x03B [7:0] 0xF1 Enable the sync logic, and set the rotation mode to reset the synchronization logic upon a sync reset trigger. W 0x03A [7:0] 0x02 Set up sync for one-shot sync mode. SYSREF± If operating in Subclass 1, send SYSREF± pulse edges to the device for synchronization alignment. W 0x300 3 LINK_MODE Corresponds to the mode selection made in Register 0x110. 0b0 = single-link mode. 0b1 = dual-link mode. 2 0b0 Select Link 0 for setup. This bit selects which link QBD is being paged. 0b0 = Link 0 (QBD0). 0b1 = Link 1 (QBD1). [1:0] LINK_EN Enables the links. 0b01 = single-link mode 0b11 = dual-link mode. Table 58. Cleanup Registers R/W Register Bits Value W 0x085 [7:0] 0x13 W 0x1DE [7:0] 0x00 W 0x008 [7:0] 0xC0 W 0x596 [7:0] 0x0C Description Set to the default register value. Disable analog SPI. To debug and continue readback capability, write 0x03. Page all main DACs for TXEN control update. SPI turn on TXENx feature. Rev. B | Page 75 of 145 AD9172 Data Sheet REGISTER SUMMARY Table 59. Register Summary Reg Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW 0x000 SPI_INTFCONFA SOFTRESET_ M LSBFIRST_M ADDRINC_M SDOACTIVE_M SDOACTIVE ADDRINC LSBFIRST SOFTRESET 0x00 R/W 0x001 SPI_INTFCONFB SINGLEINS CSSTALL RESERVED 0x00 R/W 0x003 SPI_CHIPTYPE CHIP_TYPE 0x04 R 0x004 SPI_PRODIDL PROD_ID[7:0] 0x72 R 0x005 SPI_PRODIDH PROD_ID[15:8] 0x91 R 0x006 SPI_CHIPGRADE PROD_GRADE DEV_REVISION 0x04 R 0x008 SPI_PAGEINDX MAINDAC_PAGE CHANNEL_PAGE 0xFF R/W 0x00A SPI_ SCRATCHPAD SCRATCHPAD 0x00 R/W 0x010 CHIP_ID_L CHIP_ID[7:0] 0x00 R 0x011 CHIP_ID_M1 CHIP_ID[15:8] 0x00 R 0x012 CHIP_ID_M2 CHIP_ID[23:16] 0x00 R 0x013 CHIP_ID_H CHIP_ID[31:24] 0x00 R 0x020 IRQ_ENABLE RESERVED EN_SYSREF_ JITTER EN_DATA_ READY EN_LANE_ EN_PRBSQ EN_PRBSI FIFO 0x00 R/W 0x021 IRQ_ENABLE0 RESERVED EN_DAC0_ CAL_DONE RESERVED EN_ PAERR0 0x00 R/W 0x022 IRQ_ENABLE1 RESERVED EN_DAC1_ CAL_DONE RESERVED EN_ PAERR1 0x00 R/W 0x023 IRQ_ENABLE2 RESERVED EN_DLL_LOST EN_DLL_ LOCK RESERVED EN_PLL_ LOST EN_PLL_ LOCK 0x00 R/W 0x024 IRQ_STATUS RESERVED IRQ_SYSREF_ JITTER IRQ_DATA_ READY IRQ_ LANE_ FIFO IRQ_PRBSQ IRQ_PRBSI 0x00 R/W 0x025 IRQ_STATUS0 RESERVED IRQ_DAC0_ CAL_DONE RESERVED IRQ_ PAERR0 0x00 R/W 0x026 IRQ_STATUS1 RESERVED IRQ_DAC1_ CAL_DONE RESERVED IRQ_ PAERR1 0x00 R/W 0x027 IRQ_STATUS2 RESERVED IRQ_DLL_LOST IRQ_DLL_ LOCK RESERVED IRQ_PLL_ LOST IRQ_PLL_ LOCK 0x00 R/W 0x028 IRQ_OUTPUT_M UX RESERVED MUX_ SYSREF_ JITTER MUX_ DATA_ READY MUX_ MUX_ LANE_FIFO PRBSQ MUX_ PRBSI 0x00 R/W 0x029 IRQ_OUTPUT_ MUX0 RESERVED MUX_ DAC0_ CAL_DONE RESERVED MUX_ PAERR0 0x00 R/W 0x02A IRQ_OUTPUT_ MUX1 RESERVED MUX_DAC1 _CAL_ DONE RESERVED MUX_ PAERR1 0x00 R/W 0x02B IRQ_OUTPUT_ MUX2 RESERVED MUX_DLL_ LOST MUX_DLL_ LOCK RESERVED MUX_PLL_ MUX_PLL_ 0x00 R/W LOST LOCK 0x02C IRQ_STATUS_ ALL RESERVED IRQ_ STATUS_ ALL 0x00 R/W 0x036 SYSREF_COUNT SYSREF_COUNT 0x00 R/W 0x039 SYSREF_ERR_ WINDOW RESERVED SYSREF_ERR_WINDOW 0x00 R/W 0x03A SYSREF__MODE RESERVED SYNC_ ROTATION_ DONE RESERVED SYSREF_ MODE_ ONESHOT RESERVED 0x10 R/W 0x03B ROTATION_ MODE SYNCLOGIC_ EN RESERVED PERIODIC_ RST_EN NCORST_ AFTER_ROT_ EN RESERVED ROTATION_MODE 0xB0 R/W 0x03F TX_ENABLE RESERVED TXEN_DATAPATH_DAC1 TXEN_ DATAPATH_ DAC0 RESERVED 0x00 R/W 0x050 CAL_CLK_DIV RESERVED CAL_CLK_DIV 0x28 R/W 0x051 CAL_CTRL CAL_CTRL0 RESERVED CAL_CTRL1 CAL_START 0x82 R/W 0x052 CAL_STAT RESERVED CAL_ ACTIVE CAL_FAIL_ CAL_ SEARCH FINISH 0x00 R/W 0x059 FSC0 RESERVED FSC_CTRL[1:0] 0xA0 R/W 0x05A FSC1 FSC_CTRL[9:2] 0x28 R/W 0x061 CAL_DEBUG0 RESERVED CAL_CTRL2 CAL_CTRL3 RESERVED CAL_CTRL4 RESERVED 0x60 R/W 0x081 CLK_CTRL RESERVED CAL_CLK_ PD1 CAL_CLK_ PD0 0x00 R/W 0x083 NVM_CTRL0 NVM_CTRL0A RESERVED NVM_CTRL0B 0x02 R/W Rev. B | Page 76 of 145 Data Sheet AD9172 Reg 0x084 Name SYSREF_CTRL 0x085 NVM_CTRL1 0x08D 0x08F ADC_CLK_ CTRL0 ADC_CLK_ CTRL2 0x090 0x091 DAC_ POWERDOWN ACLK_CTRL 0x094 PLL_CLK_DIV 0x095 PLL_BYPASS 0x09A 0x0C0 0x0C1 NVM_CTRL DELAY_LINE_ PD DLL_CTRL0 0x0C3 DLL_STATUS 0x0C7 DLL_READ 0x0CC 0x0CD 0x0DB DLL_FINE_ DELAY0 DLL_FINE_ DELAY1 DLL_UPDATE 0x100 DIG_RESET 0x110 JESD_MODE 0x111 0x112 INTRP_MODE DDSM_ DATAPATH_ CFG 0x113 DDSM_FTW_ UPDATE 0x114 0x115 0x116 0x117 0x118 0x119 0x11C 0x11D 0x124 0x125 0x126 0x127 0x128 0x129 0x12A 0x12B DDSM_FTW0 DDSM_FTW1 DDSM_FTW2 DDSM_FTW3 DDSM_FTW4 DDSM_FTW5 DDSM_PHASE_ OFFSET0 DDSM_PHASE_ OFFSET1 DDSM_ACC_ MODULUS0 DDSM_ACC_ MODULUS1 DDSM_ACC_ MODULUS2 DDSM_ACC_ MODULUS3 DDSM_ACC_ MODULUS4 DDSM_ACC_ MODULUS5 DDSM_ACC_ DELTA0 DDSM_ACC_ DELTA1 Bit 7 RESERVED RESERVED Bit 6 SYSREF_ INPUTMODE Bit 5 NVM_CTRL1A Bit 4 RESERVED Bit 3 RESERVED Bit 2 Bit 1 RESERVED NVM_ CTRL1B CLKOUT_SWING Bit 0 Reset RW SYSREF_PD 0x00 R/W NVM_ CTRL1C 0x13 R/W 0x00 R/W RESERVED RESERVED DAC_PD1 PD_ CLKOUT_ DRIVER DAC_PD0 0x00 R/W 0x03 R/W PD_BGR RESERVED RESERVED RESERVED RESERVED DLL_CTRL0B RESERVED DLL_CTRL0A PLL_VCO_ DIV3_EN ACLK_ POWERDOWN PLL_VCO_ DIV2_EN PLL_ BYPASS RESERVED DLL_PD 0x01 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x31 R/W DLL_CTRL1C RESERVED DLL_CTRL1B DLL_CTRL1A RESERVED RESERVED RESERVED DLL_FINE_DELAY0 DLL_ ENABLE 0x70 R/W DLL_LOCK 0x00 R/W DLL_ READ_EN 0x00 R/W 0x00 R/W RESERVED DLL_FINE_DELAY1 0x00 R/W RESERVED DLL_ DELAY_ UPDATE 0x00 R/W RESERVED DIG_ 0x01 R/W DATAPATH_ PD MODE_NOT_ COM_SYNC IN_TABLE JESD_MODE 0x20 R/W DP_INTERP_MODE CH_INTERP_MODE 0x84 R/W RESERVED DDSM_MODE DDSM_ NCO_EN DDSM_ DDSM_SEL EN_SYNC_ 0x01 R/W MODULUS _SIDEBAND ALL_CHNL_ _EN NCO_ RESETS RESERVED DDSM_FTW_REQ_MODE RESERVED DDSM_FTW DDSM_ DDSM_ 0x00 R/W _LOAD_ FTW_ FTW_ SYSREF LOAD_ACK LOAD_REQ DDSM_FTW[7:0] 0x00 R/W DDSM_FTW[15:8] 0x00 R/W DDSM_FTW[23:16] 0x00 R/W DDSM_FTW[31:24] 0x00 R/W DDSM_FTW[39:32] 0x00 R/W DDSM_FTW[47:40] 0x00 R/W DDSM_NCO_PHASE_OFFSET[7:0] 0x00 R/W DDSM_NCO_PHASE_OFFSET[15:8] 0x00 R/W DDSM_ACC_MODULUS[7:0] 0x00 R/W DDSM_ACC_MODULUS[15:8] 0x00 R/W DDSM_ACC_MODULUS[23:16] 0x00 R/W DDSM_ACC_MODULUS[31:24] 0x00 R/W DDSM_ACC_MODULUS[39:32] 0x00 R/W DDSM_ACC_MODULUS[47:40] 0x00 R/W DDSM_ACC_DELTA[7:0] 0x00 R/W DDSM_ACC_DELTA[15:8] 0x00 R/W Rev. B | Page 77 of 145 AD9172 Data Sheet Reg 0x12C 0x12D 0x12E 0x12F 0x130 0x131 0x132 0x133 0x134 0x135 0x136 0x137 0x138 0x139 0x13A 0x13B 0x13C 0x13D 0x13E 0x13F 0x140 0x141 0x142 0x143 0x144 0x145 0x146 0x147 0x148 0x149 0x14B 0x14C 0x14D 0x14E 0x151 0x1DE 0x1E2 0x1E3 0x1E4 0x1E5 0x1E6 Name DDSM_ACC_ DELTA2 DDSM_ACC_ DELTA3 DDSM_ACC_ DELTA4 DDSM_ACC_ DELTA5 DDSC_ DATAPATH_ CFG DDSC_FTW_ UPDATE Bit 7 RESERVED Bit 6 DDSC_NCO _EN Bit 5 RESERVED Bit 4 Bit 3 DDSM_ACC_DELTA[23:16] DDSM_ACC_DELTA[31:24] DDSM_ACC_DELTA[39:32] DDSM_ACC_DELTA[47:40] RESERVED DDSC_FTW0 DDSC_FTW1 DDSC_FTW2 DDSC_FTW3 DDSC_FTW4 DDSC_FTW5 DDSC_PHASE_ OFFSET0 DDSC_PHASE_ OFFSET1 DDSC_ACC_ MODULUS0 DDSC_ACC_ MODULUS1 DDSC_ACC_ MODULUS2 DDSC_ACC_ MODULUS3 DDSC_ACC_ MODULUS4 DDSC_ACC_ MODULUS5 DDSC_ACC_ DELTA0 DDSC_ACC_ DELTA1 DDSC_ACC_ DELTA2 DDSC_ACC_ DELTA3 DDSC_ACC_ DELTA4 DDSC_ACC_ DELTA5 CHNL_GAIN0 CHNL_GAIN1 DC_CAL_TONE0 DC_CAL_TONE1 PRBS PRBS_ERROR_I PRBS_ERROR_Q PRBS_CHANSEL DECODE_MODE SPI_ENABLE DDSM_CAL_ FTW0 DDSM_CAL_ FTW1 DDSM_CAL_ FTW2 DDSM_CAL_ FTW3 DDSM_CAL_ MODE_DEF DDSC_FTW[7:0] DDSC_FTW[15:8] DDSC_FTW[23:16] DDSC_FTW[31:24] DDSC_FTW[39:32] DDSC_FTW[47:40] DDSC_NCO_PHASE_OFFSET[7:0] DDSC_NCO_PHASE_OFFSET[15:8] DDSC_ACC_MODULUS[7:0] DDSC_ACC_MODULUS[15:8] DDSC_ACC_MODULUS[23:16] DDSC_ACC_MODULUS[31:24] DDSC_ACC_MODULUS[39:32] DDSC_ACC_MODULUS[47:40] DDSC_ACC_DELTA[7:0] DDSC_ACC_DELTA[15:8] DDSC_ACC_DELTA[23:16] DDSC_ACC_DELTA[31:24] DDSC_ACC_DELTA[39:32] DDSC_ACC_DELTA[47:40] PRBS_GOOD_ PRBS_ Q GOOD_I RESERVED RESERVED RESERVED CHNL_GAIN[7:0] DC_TEST_INPUT_AMPLITUDE[7:0] DC_TEST_INPUT_AMPLITUDE[15:8] PRBS_INV_Q PRBS_INV_I PRBS_COUNT_I PRBS_COUNT_Q RESERVED MSB_MODE RESERVED DDSM_CAL_FTW[7:0] DDSM_CAL_FTW[15:8] DDSM_CAL_FTW[23:16] DDSM_CAL_FTW[31:24] RESERVED Bit 2 Bit 1 Bit 0 DDSC_ MODULUS_ EN DDSC_FTW _LOAD_ SYSREF DDSC_ SEL_ SIDEBAND DDSC_ FTW_ LOAD_ACK DDSC_EN_ DC_INPUT DDSC_ FTW_ LOAD_REQ CHNL_GAIN[11:8] PRBS_ MODE PRBS_ RESET PRBS_EN PRBS_CHANSEL RESERVED SPI_EN1 SPI_EN0 DDSM_EN_ CAL_ACC DDSM_EN_ CAL_DC_ INPUT DDSM_EN_ CAL_FREQ_ TUNE Reset RW 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x08 R/W 0x00 R/W 0x00 R/W 0x10 R/W 0x00 R 0x00 R 0x07 R/W 0x00 R/W 0x03 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W Rev. B | Page 78 of 145 Data Sheet AD9172 Reg Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW 0x1E7 DATAPATH_ NCO_ SYNC_CFG RESERVED ALL_NCO_ SYNC_ACK START_ NCO_ SYNC 0x00 R/W 0x200 MASTER_PD RESERVED SERDES_ MASTER_ PD 0x01 R/W 0x201 PHY_PD PHY_PD 0xEE R/W 0x203 GENERIC_PD RESERVED PD_ PD_ 0x01 R/W SYNCOUT0 SYNCOUT1 0x206 CDR_RESET RESERVED CDR_PHY_ 0x00 R/W RESET 0x210 CBUS_ADDR SERDES_CBUS_ADDR 0x00 R/W 0x212 CBUS_ WRSTROBE_ PHY SERDES_CBUS_WR0 0x00 R/W 0x213 CBUS_ WRSTROBE_ OTHER RESERVED SERDES_ 0x00 R/W CBUS_WR1 0x216 CBUS_WDATA SERDES_CBUS_DATA 0x00 R/W 0x234 CDR_ BITINVERSE SEL_IF_PARDATAINV_DES_RC_CH 0x66 R/W 0x240 EQ_BOOST_ PHY_3_0 EQ_BOOST_PHY3 EQ_BOOST_PHY2 EQ_BOOST_PHY1 EQ_BOOST_PHY0 0xFF R/W 0x241 EQ_BOOST_ PHY_7_4 EQ_BOOST_PHY7 EQ_BOOST_PHY6 EQ_BOOST_PHY5 EQ_BOOST_PHY4 0xFF R/W 0x242 EQ_GAIN_PHY_ 3_0 EQ_GAIN_PHY3 EQ_GAIN_PHY2 EQ_GAIN_PHY1 EQ_GAIN_PHY0 0xFF R/W 0x243 EQ_GAIN_PHY_ 7_4 EQ_GAIN_PHY7 EQ_GAIN_PHY6 EQ_GAIN_PHY5 EQ_GAIN_PHY4 0xFF R/W 0x244 EQ_FB_PHY_0 RESERVED EQ_PHY_0 0x19 R/W 0x245 EQ_FB_PHY_1 RESERVED EQ_PHY1 0x19 R/W 0x246 EQ_FB_PHY_2 RESERVED EQ_PHY2 0x19 R/W 0x247 EQ_FB_PHY_3 RESERVED EQ_PHY3 0x19 R/W 0x248 EQ_FB_PHY_4 RESERVED EQ_PHY4 0x19 R/W 0x249 EQ_FB_PHY_5 RESERVED EQ_PHY5 0x19 R/W 0x24A EQ_FB_PHY_6 RESERVED EQ_PHY6 0x19 R/W 0x24B EQ_FB_PHY_7 RESERVED EQ_PHY7 0x19 R/W 0x250 LBT_REG_ CNTRL_0 EN_LBT_DES_RC_CH 0x00 R/W 0x251 LBT_REG_ CNTRL_1 RESERVED EN_LBT_ INIT_LBT_ 0x02 R/W HALFRATE SYNC_DES_ _DES_RC RC 0x253 SYNCOUT0_ CTRL RESERVED SEL_ 0x00 R/W SYNCOUT0_ MODE 0x254 SYNCOUT1_ CTRL RESERVED SEL_ 0x00 R/W SYNCOUT1_ MODE 0x280 PLL_ENABLE_ CTRL RESERVED LOLSTICKY CLEAR_ LCPLL_RC LDSYNTH_ LCPLL_RC SERDES_ PLL_ STARTUP 0x01 R/W 0x281 PLL_STATUS RESERVED SERDES_ PLL_ LOCK 0x00 R 0x300 GENERAL_JRX_ CTRL_0 RESERVED LINK_ MODE LINK_PAGE LINK_EN 0x00 R/W 0x302 DYN_LINK_ LATENCY_0 RESERVED DYN_LINK_LATENCY_0 0x00 R 0x303 DYN_LINK_ LATENCY_1 RESERVED DYN_LINK_LATENCY_1 0x00 R 0x304 LMFC_DELAY_0 RESERVED LMFC_DELAY_0 0x00 R/W 0x305 LMFC_DELAY_1 RESERVED LMFC_DELAY_1 0x00 R/W 0x306 LMFC_VAR_0 RESERVED LMFC_VAR_0 0x3F R/W 0x307 LMFC_VAR_1 RESERVED LMFC_VAR_1 0x3F R/W 0x308 XBAR_LN_0_1 RESERVED LOGICAL_LANE1_SRC LOGICAL_LANE0_SRC 0x08 R/W 0x309 XBAR_LN_2_3 RESERVED LOGICAL_LANE3_SRC LOGICAL_LANE2_SRC 0x1A R/W 0x30A XBAR_LN_4_5 RESERVED LOGICAL_LANE5_SRC LOGICAL_LANE4_SRC 0x2C R/W 0x30B XBAR_LN_6_7 RESERVED LOGICAL_LANE7_SRC LOGICAL_LANE6_SRC 0x3E R/W 0x30C FIFO_STATUS_ REG_0 LANE_FIFO_FULL 0x00 R Rev. B | Page 79 of 145 AD9172 Data Sheet Reg Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW 0x30D FIFO_STATUS_ REG_1 LANE_FIFO_EMPTY 0x00 R 0x311 SYNCOUT_ GEN_0 RESERVED EOMF_ MASK_1 EOMF_ MASK_0 EOF_ MASK_1 EOF_ MASK_0 0x00 R/W 0x312 SYNCOUT_ GEN_1 SYNC_ERR_DUR RESERVED 0x00 R/W 0x315 PHY_PRBS_ TEST_EN PHY_TEST_EN 0x00 R/W 0x316 PHY_ PRBS_TEST_ CTRL RESERVED PHY_SRC_ERR_CNT PHY_PRBS_PAT_SEL PHY_TEST_ PHY_TEST_ 0x00 R/W START RESET 0x317 PHY_ PRBS_TEST_ THRESHOLD_ LOBITS PHY_PRBS_THRESHOLD_LOBITS 0x00 R/W 0x318 PHY_ PRBS_TEST_ THRESHOLD_ MIDBITS PHY_PRBS_THRESHOLD_MIDBITS 0x00 R/W 0x319 PHY_ PRBS_TEST_ THRESHOLD_ HIBITS PHY_PRBS_THRESHOLD_HIBITS 0x00 R/W 0x31A PHY_ PRBS_TEST_ ERRCNT_LOBITS PHY_PRBS_ERR_CNT_LOBITS 0x00 R 0x31B PHY_PRBS_ TEST_ ERRCNT_ MIDBITS PHY_PRBS_ERR_CNT_MIDBITS 0x00 R 0x31C PHY_ PRBS_TEST_ ERRCNT_HIBITS PHY_PRBS_ERR_CNT_HIBITS 0x00 R 0x31D PHY_ PRBS_TEST_ STATUS PHY_PRBS_PASS 0xFF R 0x31E PHY_DATA_ SNAPSHOT_ CTRL RESERVED PHY_ GRAB_ MODE PHY_GRAB_ 0x00 R/W DATA 0x31F PHY_ SNAPSHOT_ DATA_BYTE0 PHY_SNAPSHOT_DATA_BYTE0 0x00 R 0x320 PHY_ SNAPSHOT_ DATA_BYTE1 PHY_SNAPSHOT_DATA_BYTE1 0x00 R 0x321 PHY_ SNAPSHOT_ DATA_BYTE2 PHY_SNAPSHOT_DATA_BYTE2 0x00 R 0x322 PHY_ SNAPSHOT_ DATA_BYTE3 PHY_SNAPSHOT_DATA_BYTE3 0x00 R 0x323 PHY_ SNAPSHOT_ DATA_BYTE4 PHY_SNAPSHOT_DATA_BYTE4 0x00 R 0x32C SHORT_TPL_ TEST_0 SHORT_TPL_SP_SEL SHORT_TPL_M_SEL SHORT_ TPL_TEST_ RESET SHORT_ TPL_ TEST_EN 0x00 R/W 0x32D SHORT_TPL_ TEST_1 SHORT_TPL_REF_SP_LSB 0x00 R/W 0x32E SHORT_TPL_ TEST_2 SHORT_TPL_REF_SP_MSB 0x00 R/W 0x32F SHORT_TPL_ TEST_3 RESERVED SHORT_TPL_ IQ_SAMPLE_ SEL RESERVED SHORT_ TPL_FAIL 0x00 R/W 0x334 JESD_BIT_ INVERSE_CTRL JESD_BIT_INVERSE 0x00 R/W 0x400 DID_REG DID_RD 0x00 R 0x401 BID_REG BID_RD 0x00 R 0x402 LID0_REG RESERVED ADJDIR_RD PHADJ_RD LL_LID0 0x00 R 0x403 SCR_L_REG SCR_RD RESERVED L_RD-1 0x00 R 0x404 F_REG F_RD-1 0x00 R 0x405 K_REG RESERVED K_RD-1 0x00 R 0x406 M_REG M_RD-1 0x00 R 0x407 CS_N_REG CS_RD RESERVED N_RD-1 0x00 R Rev. B | Page 80 of 145 Data Sheet Reg 0x408 0x409 0x40A 0x40B 0x40C 0x40D 0x40E 0x412 0x415 0x416 0x41A 0x41D 0x41E 0x422 0x425 0x426 0x42A 0x42D 0x42E 0x432 0x435 0x436 0x43A 0x43D 0x43E 0x442 0x445 0x446 0x450 0x451 0x452 0x453 0x454 0x455 0x456 0x457 0x458 0x459 0x45A 0x45B 0x45C 0x45D 0x46C 0x46D 0x46E 0x46F 0x470 0x471 0x472 Name NP_REG S_REG HD_CF_REG RES1_REG RES2_REG CHECKSUM0_ REG COMPSUM0_ REG LID1_REG CHECKSUM1_ REG COMPSUM1_ REG LID2_REG CHECKSUM2_ REG COMPSUM2_ REG LID3_REG CHECKSUM3_ REG COMPSUM3_ REG LID4_REG CHECKSUM4_ REG COMPSUM4_ REG LID5_REG CHECKSUM5_ REG COMPSUM5_ REG LID6_REG CHECKSUM6_ REG COMPSUM6_ REG LID7_REG CHECKSUM7_ REG COMPSUM7_ REG ILS_DID ILS_BID ILS_LID0 ILS_SCR_L ILS_F ILS_K ILS_M ILS_CS_N ILS_NP ILS_S ILS_HD_CF ILS_RES1 ILS_RES2 ILS_CHECKSUM LANE_DESKEW BAD_DISPARITY NOT_IN_TABLE UNEXPECTED_ KCHAR CODE_GRP_ SYNC FRAME_SYNC GOOD_ CHECKSUM Bit 7 HD_RD RESERVED SCR HD ILD7 BDE7 NIT7 UEK7 CGS7 FS7 CKS7 Bit 6 Bit 5 SUBCLASSV_RD JESDV_RD-1 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED ADJDIR PHADJ RESERVED RESERVED CS RESERVED SUBCLASSV JESDV RESERVED ILD6 BDE6 NIT6 UEK6 CGS6 FS6 CKS6 ILD5 BDE5 NIT5 UEK5 CGS5 FS5 CKS5 Bit 4 Bit 3 RES1_RD RES2_RD LL_FCHK0 LL_FCMP0 LL_FCHK1 LL_FCMP1 LL_FCHK2 LL_FCMP2 LL_FCHK3 LL_FCMP3 LL_FCHK4 LL_FCMP4 LL_FCHK5 LL_FCMP5 LL_FCHK6 LL_FCMP6 LL_FCHK7 LL_FCMP7 DID BID F-1 M-1 ILD4 BDE4 NIT4 UEK4 RES1 RES2 FCHK0 ILD3 BDE3 NIT3 UEK3 CGS4 CGS3 FS4 CKS4 FS3 CKS3 Rev. B | Page 81 of 145 Bit 2 NP_RD-1 S_RD-1 CF_RD Bit 1 LL_LID1 LL_LID2 LL_LID3 LL_LID4 LL_LID5 LL_LID6 LL_LID7 LID0 L-1 K-1 N-1 NP-1 S-1 CF ILD2 BDE2 NIT2 UEK2 CGS2 FS2 CKS2 ILD1 BDE1 NIT1 UEK1 CGS1 FS1 CKS1 Bit 0 ILD0 BDE0 NIT0 UEK0 CGS0 FS0 CKS0 AD9172 Reset RW 0x00 R 0x00 R 0x00 R 0x00 R 0x00 R 0x00 R 0x00 R 0x00 R 0x00 R 0x00 R 0x00 R 0x00 R 0x00 R 0x00 R 0x00 R 0x00 R 0x00 R 0x00 R 0x00 R 0x00 R 0x00 R 0x00 R 0x00 R 0x00 R 0x00 R 0x00 R 0x00 R 0x00 R 0x00 R/W 0x00 R/W 0x00 R/W 0x87 R/W 0x00 R/W 0x1F R/W 0x01 R/W 0x0F R/W 0x0F R/W 0x01 R/W 0x80 R 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R 0x00 R 0x00 R 0x00 R 0x00 R 0x00 R 0x00 R AD9172 Data Sheet Reg 0x473 0x475 0x476 0x477 0x478 0x47C 0x47D 0x480 0x481 0x482 0x483 0x484 0x485 0x486 0x487 0x488 0x489 0x48A 0x48B 0x48C 0x48D 0x48E 0x48F 0x490 0x491 0x492 0x493 0x494 0x495 0x496 0x497 0x4B0 0x4B1 0x4B2 0x4B3 0x4B4 0x4B5 0x4B6 0x4B7 0x4B8 0x4B9 0x4BA 0x4BB 0x4BC 0x580 0x581 0x582 0x583 0x584 0x585 Name INIT_LANE_ SYNC CTRLREG0 CTRLREG1 CTRLREG2 KVAL ERRORTHRES SYNC_ASSERT_ MASK ECNT_CTRL0 ECNT_CTRL1 ECNT_CTRL2 ECNT_CTRL3 ECNT_CTRL4 ECNT_CTRL5 ECNT_CTRL6 ECNT_CTRL7 ECNT_TCH0 ECNT_TCH1 ECNT_TCH2 ECNT_TCH3 ECNT_TCH4 ECNT_TCH5 ECNT_TCH6 ECNT_TCH7 ECNT_STAT0 ECNT_STAT1 ECNT_STAT2 ECNT_STAT3 ECNT_STAT4 ECNT_STAT5 ECNT_STAT6 ECNT_STAT7 LINK_STATUS0 LINK_STATUS1 LINK_STATUS2 LINK_STATUS3 LINK_STATUS4 LINK_STATUS5 LINK_STATUS6 LINK_STATUS7 JESD_IRQ_ ENABLEA JESD_IRQ_ ENABLEB JESD_IRQ_ STATUSA JESD_IRQ_ STATUSB IRQ_OUTPUT_ MUX_JESD BE_SOFT_OFF_ GAIN_CTRL BE_SOFT_OFF_ ENABLE BE_SOFT_ON_ ENABLE LONG_PA_ THRES_LSB LONG_PA_ THRES_MSB LONG_PA_ CONTROL Bit 7 ILS7 Bit 6 ILS6 Bit 5 ILS5 Bit 4 ILS4 Bit 3 ILS3 Bit 2 ILS2 Bit 1 ILS1 Bit 0 ILS0 Reset RW 0x00 R ILS_MODE RESERVED RESERVED RESERVED REPDATATEST RESERVED SOFTRST QUAL_RDERR QUETESTERR KSYNC ETH AR_ECNTR FORCESYNCREQ RESERVED REPL_FRM_ 0x01 R/W ENA RESERVED FCHK_N 0x14 R/W RESERVED 0x00 R/W 0x01 R/W 0xFF R/W SYNC_ASSERT_MASK 0x07 R/W RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED BDE0 BDE1 BDE2 BDE3 BDE4 BDE5 BDE6 BDE7 EN_BDE NIT0 NIT1 NIT2 NIT3 NIT4 NIT5 NIT6 NIT7 EN_NIT RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED UEK0 UEK1 UEK2 UEK3 UEK4 UEK5 UEK6 UEK7 EN_UEK ECNT_ENA0 ECNT_ENA1 ECNT_ENA2 ECNT_ENA3 ECNT_ENA4 ECNT_ENA5 ECNT_ENA6 ECNT_ENA7 ILD0 ILD1 ILD2 ILD3 ILD4 ILD5 ILD6 ILD7 EN_ILD LANE_ENA0 LANE_ENA1 LANE_ENA2 LANE_ENA3 LANE_ENA4 LANE_ENA5 LANE_ENA6 LANE_ENA7 ILS0 ILS1 ILS2 ILS3 ILS4 ILS5 ILS6 ILS7 EN_ILS CKS0 CKS1 CKS2 CKS3 CKS4 CKS5 CKS6 CKS7 EN_CKS ECNT_RST0 ECNT_RST1 ECNT_RST2 ECNT_RST3 ECNT_RST4 ECNT_RST5 ECNT_RST6 ECNT_RST7 ECNT_TCH0 ECNT_TCH1 ECNT_TCH2 ECNT_TCH3 ECNT_TCH4 ECNT_TCH5 ECNT_TCH6 ECNT_TCH7 ECNT_TCR0 ECNT_TCR1 ECNT_TCR2 ECNT_TCR3 ECNT_TCR4 ECNT_TCR5 ECNT_TCR6 ECNT_TCR7 FS0 FS1 FS2 FS3 FS4 FS5 FS6 FS7 EN_FS CGS0 CGS1 CGS2 CGS3 CGS4 CGS5 CGS6 CGS7 EN_CGS 0x3F R/W 0x3F R/W 0x3F R/W 0x3F R/W 0x3F R/W 0x3F R/W 0x3F R/W 0x3F R/W 0x07 R/W 0x07 R/W 0x07 R/W 0x07 R/W 0x07 R/W 0x07 R/W 0x07 R/W 0x07 R/W 0x00 R 0x00 R 0x00 R 0x00 R 0x00 R 0x00 R 0x00 R 0x00 R 0x00 R 0x00 R 0x00 R 0x00 R 0x00 R 0x00 R 0x00 R 0x00 R 0x00 R/W RESERVED EN_ILAS 0x00 R/W IRQ_BDE IRQ_NIT IRQ_UEK IRQ_ILD IRQ_ILS IRQ_CKS IRQ_FS IRQ_CGS 0x00 R/W RESERVED IRQ_ILAS 0x00 R/W BE_SOFT_OFF _GAIN_EN ENA_SHORT_ PAERR_ SOFTOFF SPI_SOFT_ ON_EN ENA_LONG_ PAERR_ SOFTOFF LONG_ LEVEL_ SOFTON_EN RESERVED RESERVED RESERVED MUX_JESD_ 0x00 R/W IRQ BE_GAIN_RAMP_RATE 0x00 R/W ENA_JESD_ ERR_ SOFTOFF ROTATE_ SOFT_OFF_ EN RESERVED TXEN_SOF T_OFF_EN SPI_SOFT_ OFF_EN 0xC6 R/W 0x40 R/W LONG_PA_THRESHOLD[7:0] 0x00 R/W RESERVED LONG_PA_THRESHOLD[12:8] 0x00 R/W LONG_PA_ ENABLE RESERVED LONG_PA_AVG_TIME 0x00 R/W Rev. B | Page 82 of 145 Data Sheet AD9172 Reg 0x586 0x587 0x588 0x589 0x58A 0x58B 0x58C 0x58D 0x596 0x597 0x598 0x599 0x705 0x790 0x791 0x792 0x793 0x794 0x795 0x796 0x797 0x798 0x799 0x7A0 0x7A2 0x7B5 Name LONG_PA_ POWER_LSB LONG_PA_ POWER_MSB SHORT_PA_ THRES_LSB SHORT_PA_ THRES_MSB SHORT_PA_ CONTROL SHORT_PA_ POWER_LSB SHORT_PA_ POWER_MSB TXEN_SM_0 BLANKING_ CTRL JESD_PA_INT0 JESD_PA_INT1 TXEN_FLUSH_ CTRL0 NVM_LOADER_ EN DACPLL_ PDCTRL0 DACPLL_ PDCTRL1 DACPLL_CTRL0 DACPLL_CTRL1 DACPLL_CTRL2 DACPLL_CTRL3 DACPLL_CTRL4 DACPLL_CTRL5 DACPLL_CTRL6 DACPLL_CTRL7 DACPLL_CTRL9 DACPLL_ CTRL10 PLL_STATUS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 LONG_PA_POWER[7:0] Bit 2 Bit 1 Bit 0 RESERVED LONG_PA_POWER[12:8] SHORT_PA_THRESHOLD[7:0] RESERVED SHORT_PA_THRESHOLD[12:8] SHORT_PA_ ENABLE RESERVED SHORT_PA_POWER[7:0] SHORT_PA_AVG_TIME RESERVED SHORT_PA_POWER[12:8] PLL_PD5 RESERVED RESERVED SPI_TXEN JESD_PA_INT_CNTRL[7:0] RESERVED RESERVED RESERVED PLL_PD4 PLL_PD3 ENA_SPI_ TXEN PLL_PD2 ENA_ TXENSM RESERVED PLL_PD1 JESD_PA_ INT_ CNTRL[8] SPI_FLUSH_ EN NVM_BLR_ EN PLL_PD0 RESERVED PLL_PD10 PLL_PD9 PLL_PD8 PLL_PD7 PLL_PD6 RESERVED RESERVED RESERVED RESERVED PLL_CTRL0 RESERVED RESERVED PLL_CTRL3 ADC_CLK_DIVIDER RESERVED D_EN_VAR_ FINE_PRE RESERVED D_REGULATOR_CAL_WAIT D_CAL_ RESET D_RESET_ VCO_DIV M_DIVIDER-1 DACPLL_CP D_CP_CALBITS RESERVED PLL_CTRL1 PLL_CTRL2 N_DIVIDER RESERVED D_EN_VAR_ COARSE_ PRE RESERVED D_VCO_CAL_WAIT D_VCO_CAL_CYCLES RESERVED RESERVED PLL_LOCK Reset RW 0x00 R 0x00 R 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R 0x00 R 0x50 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x01 R/W 0x00 R/W 0x02 R/W 0x00 R/W 0x02 R/W 0x18 R/W 0x04 R/W 0x08 R/W 0xD2 R/W 0x20 R/W 0x1C R/W 0x08 R/W 0x90 R/W 0x35 R/W 0x00 R Rev. B | Page 83 of 145 AD9172 Data Sheet REGISTER DETAILS Table 60. Register Details Addr. Name 0x000 SPI_INTFCONFA Bits Bit Name 7 SOFTRESET_M 6 LSBFIRST_M 5 ADDRINC_M 4 SDOACTIVE_M 3 SDOACTIVE 2 ADDRINC 1 LSBFIRST 0 SOFTRESET 0x001 SPI_INTFCONFB 7 SINGLEINS 6 CSSTALL 0x003 0x004 0x005 0x006 SPI_CHIPTYPE SPI_PRODIDL SPI_PRODIDH SPI_CHIPGRADE 0x008 SPI_PAGEINDX [5:0] RESERVED [7:0] CHIP_TYPE [7:0] PROD_ID[7:0] [7:0] PROD_ID[15:8] [7:4] PROD_GRADE [3:0] DEV_REVISION [7:6] MAINDAC_PAGE [5:0] CHANNEL_PAGE 0x00A 0x010 0x011 0x012 0x013 SPI_SCRATCHPAD CHIP_ID_L CHIP_ID_M1 CHIP_ID_M2 CHIP_ID_H [7:0] SCRATCHPAD [7:0] CHIP_ID[7:0] [7:0] CHIP_ID[15:8] [7:0] CHIP_ID[23:16] [7:0] CHIP_ID[31:24] Settings 1 0 1 0 1 0 1 0 0 1 Description Soft reset (mirror). Set this bit to mirror Bit 0. LSB first (mirror). Set this bit to mirror Bit 1. Address increment (mirror). Set this bit to mirror Bit 2. SDO active (mirror). Set this bit to mirror Bit 3. SDO active. Enables 4-wire SPI bus mode. Address increment. When set, this bit causes incrementing streaming addresses; otherwise, descending addresses are generated. Streaming addresses are incremented. Streaming addresses are decremented. LSB first. When set, this bit causes SPI input and output data to be oriented as LSB first. If this bit is clear, data is oriented as MSB first. Shift LSB in first. Shift MSB in first. Soft reset. This bit automatically clears to 0 after performing a reset operation. Setting this bit initiates a reset. This bit autoclears after the soft reset is complete. Pulse the soft reset line. Reset the soft reset line. Single instruction. Perform single transfers. Perform multiple transfers. CS stalling. Disable CS stalling. Enable CS stalling. Reserved. Chip type. Product ID. Product ID. Product grade. Device revision. Sets the main DAC paging. Each high bit in this field pages a DAC starting at the LSB. Both main DACs can be paged and programmed at the same time if desired. Sets channel paging. Each high bit in this field pages a complex channel starting at the LSB. Multiple channels can be paged and programmed at a time if desired. Scratch pad read/write register. Chip ID serial number. Chip ID serial number. Chip ID serial number. Chip ID serial number. Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x4 0x72 0x91 0x0 0x4 0x3 0x3F 0x0 0x0 0x0 0x0 0x0 Access R R R R R/W R/W R/W R/W R/W R/W R/W R R R R R R/W R/W R/W R R R R Rev. B | Page 84 of 145 Data Sheet Addr. Name 0x020 IRQ_ENABLE 0x021 IRQ_ENABLE0 0x022 IRQ_ENABLE1 0x023 IRQ_ENABLE2 0x024 IRQ_STATUS AD9172 Bits Bit Name Settings Description Reset [7:5] RESERVED Reserved. 0x0 4 EN_SYSREF_JITTER Enable SYSREF± jitter interrupt. 0x0 3 EN_DATA_READY Enable JESD204B receiver ready 0x0 (JRX_DATA_READY) low interrupt. 2 EN_LANE_FIFO Enable lane FIFO overflow/underflow 0x0 interrupt. 1 EN_PRBSQ Enable PRBS imaginary error interrupt. 0x0 0 EN_PRBSI Enable PRBS real error interrupt. 0x0 [7:4] RESERVED Reserved. 0x0 3 EN_DAC0_CAL_ DONE Enable DAC0 calibration complete interrupt. 0x0 [2:1] RESERVED Reserved. 0x0 0 EN_PAERR0 Enable PA protection error interrupt for 0x0 DAC0. [7:4] RESERVED Reserved. 0x0 3 EN_DAC1_CAL_ DONE Enable DAC1 calibration complete interrupt. 0x0 [2:1] RESERVED Reserved. 0x0 0 EN_PAERR1 Enable PA protection error interrupt for 0x0 DAC1. [7:6] RESERVED Reserved. 0x0 5 EN_DLL_LOST Enable DLL lock lost interrupt. 0x0 4 EN_DLL_LOCK Enable DLL lock interrupt. 0x0 [3:2] RESERVED Reserved. 0x0 1 EN_PLL_LOST Enable PLL lock lost interrupt. 0x0 0 EN_PLL_LOCK Enable PLL lock interrupt. 0x0 [7:5] RESERVED Reserved. 0x0 4 IRQ_SYSREF_JITTER SYSREF± jitter too large. If EN_SYSREF_JITTER 0x0 is low, IRQ_SYSREF_JITTER shows the current status. If EN_SYSREF_JITTER is high, IRQ_SYSREF_JITTER latches and pulls the IRQx pin low (x = the MUX_SYSREF_JITTER setting). Writing a 1 to IRQ_SYSREF_JITTER when latched clears the bit. 3 IRQ_DATA_READY JESD204x receiver data ready is low. If 0x0 EN_DATA_READY is low, IRQ_DATA_READY shows the current status. If EN_DATA_ READY is high, IRQ_DATA_READY latches and pulls the IRQx pin low (x = MUX_ DATA_READY setting). Writing a 1 to IRQ_ DATA_READY when latched clears the bit. 2 IRQ_LANE_FIFO Lane FIFO overflow/underflow. If EN_ 0x0 LANE_FIFO is low, IRQ_LANE_FIFO shows the current status. If EN_LANE_FIFO is high, IRQ_LANE_FIFO latches and pulls the IRQx pin low (x = MUX_LANE_FIFO setting). Writing a 1 to IRQ_LANE_FIFO when latched clears the bit. 1 IRQ_PRBSQ DAC1 PRBS error. If EN_PRBSQ is low, 0x0 IRQ_PRBSQ shows the current status. If EN_PRBSQ is high, IRQ_PRBSQ latches and pulls the IRQx pin low (x = MUX_PRBSQ setting). Writing a 1 to IRQ_PRBSQ when latched clears the bit. Access R R/W R/W R/W R/W R/W R R/W R/W R/W R R/W R/W R/W R R/W R/W R/W R/W R/W R R/W R/W R/W R/W Rev. B | Page 85 of 145 AD9172 Addr. Name 0x025 IRQ_STATUS0 0x026 IRQ_STATUS1 0x027 IRQ_STATUS2 Data Sheet Bits Bit Name 0 IRQ_PRBSI [7:4] RESERVED 3 IRQ_DAC0_CAL_ DONE [2:1] RESERVED 0 IRQ_PAERR0 [7:4] RESERVED 3 IRQ_DAC1_CAL_ DONE [2:1] RESERVED 0 IRQ_PAERR1 [7:6] RESERVED 5 IRQ_DLL_LOST 4 IRQ_DLL_LOCK [3:2] RESERVED 1 IRQ_PLL_LOST Settings Description DAC0 PRBS error. If EN_PRBSI is low, IRQ_ PRBSI shows the current status. If EN_PRBSI is high, IRQ_PRBSI latches and pulls the IRQx pin low (x = MUX_PRBSI setting). Writing a 1 to IRQ_PRBSI when latched clears the bit. Reserved. DAC0 calibration done. If EN_DAC0_CAL_ DONE is low, IRQ_DAC0_CAL_DONE shows the current status. If EN_DAC0_CAL_DONE is high, IRQ_DAC0_CAL_DONE latches and pulls the IRQx pin low (x = MUX_DAC0_ CAL_DONE setting). Writing a 1 to IRQ_ DAC0_CAL_DONE when latched clears the bit. Reserved. DAC0 PA error. If EN_PAERR0 is low, IRQ_ PAERR0 shows the current status. If EN_ PAERR0 is high, IRQ_PAERR0 latches and pulls the IRQx pin low (x = MUX_PAERR0 setting). Writing a 1 to IRQ_PAERR0 when latched clears the bit. Reserved. DAC1 calibration done. If EN_DAC0_CAL_ DONE is low, IRQ_DAC1_CAL_DONE shows the current status. If EN_DAC1_CAL_DONE is high, IRQ_DAC1_CAL_DONE latches and pulls the IRQx pin low (x = MUX_DAC1_ CAL_DONE setting). Writing a 1 to IRQ_ DAC1_CAL_DONE when latched clears the bit. Reserved. DAC1 PA error. If EN_PAERR1 is low, IRQ_ PAERR1 shows the current status. If EN_ PAERR1 is high, IRQ_PAERR1 latches and pulls the IRQx pin low (x = MUX_PAERR1 setting). Writing a 1 to IRQ_PAERR1 when latched clears the bit. Reserved. DLL lost. If EN_DLL_LOST is low, IRQ_DLL_ LOST shows the current status. If EN_DLL_ LOST is high, IRQ_DLL_LOST latches and pulls the IRQx pin low (x = MUX_DLL_LOST setting). Writing a 1 to IRQ_DLL_LOST when latched clears the bit. DLL locked. If EN_DLL_LOCK is low, IRQ_ DLL_LOCK shows current status. If EN_DLL_ LOCK is high, IRQ_DLL_LOCK latches and pulls the IRQx pin low (x = MUX_DLL_LOCK setting). Writing a 1 to IRQ_DLL_LOCK when latched clears the bit. Reserved. DAC PLL lock lost. If EN_PLL_LOST is low, IRQ_PLL_LOST shows the current status. If EN_PLL_LOST is high, IRQ_PLL_LOST latches and pulls the IRQx pin low (x = MUX_PLL_ LOST setting). Writing a 1 to IRQ_PLL_ LOST when latched clears the bit. Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R/W R R/W R/W R/W R R/W R/W R/W R R/W R/W R/W R/W Rev. B | Page 86 of 145 Data Sheet AD9172 Addr. Name Bits 0 0x028 IRQ_OUTPUT_MUX [7:5] 4 3 2 1 0 0x029 IRQ_OUTPUT_MUX0 [7:4] 3 [2:1] 0 0x02A IRQ_OUTPUT_MUX1 [7:4] 3 [2:1] Bit Name IRQ_PLL_LOCK RESERVED MUX_SYSREF_ JITTER MUX_DATA_READY MUX_LANE_FIFO MUX_PRBSQ MUX_PRBSI RESERVED MUX_DAC0_CAL_ DONE RESERVED MUX_PAERR0 RESERVED MUX_DAC1_CAL_ DONE RESERVED Settings 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Description DAC PLL locked. If EN_PLL_LOCK is low, IRQ_ PLL_LOCK shows the current status. If EN_ PLL_LOCK is high, IRQ_PLL_LOCK latches and pulls the IRQx pin low (x = MUX_PLL_ LOCK setting). Writing a 1 to IRQ_PLL_LOCK when latched clears the bit. Reserved. If EN_SYSREF_JITTER is set, this control chooses the IRQx output pin on which the event is triggered. Route IRQ trigger signal to the IRQ0 pin. Route IRQ trigger signal to the IRQ1 pin. If EN_DATA_READY is set, this control chooses the IRQx output pin on which the event is triggered. Route IRQ trigger signal to the IRQ0 pin. Route IRQ trigger signal to the IRQ1 pin. If EN_LANE_FIFO is set, this control chooses the IRQx output pin on which the event is triggered. Route IRQ trigger signal to the IRQ0 pin. Route IRQ trigger signal to the IRQ1 pin. If EN_PRBSQ is set, this control chooses the IRQx output pin on which the event is triggered. Route IRQ trigger signal to the IRQ0 pin. Route IRQ trigger signal to the IRQ1 pin. If EN_PRBSI is set, this control chooses the IRQx output pin on which the event is triggered. Route IRQ trigger signal to the IRQ0 pin. Route IRQ trigger signal to the IRQ1 pin. Reserved. If EN_DAC0_CAL_DONE is set, this control chooses the IRQx output pin on which the event is triggered. Route IRQ trigger signal to the IRQ0 pin. Route IRQ trigger signal to the IRQ1 pin. Reserved. If EN_PAERR0 is set, this control chooses the IRQx output pin on which the event is triggered. Route IRQ trigger signal to the IRQ0 pin. Route IRQ trigger signal to the IRQ1 pin. Reserved. If EN_DAC1_CAL_DONE is set, this control chooses the IRQx output pin on which the event is triggered. Route IRQ trigger signal to the IRQ0 pin. Route IRQ trigger signal to the IRQ1 pin. Reserved. Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R/W R R/W R/W R/W R/W R/W R R/W R/W R/W R R/W R/W Rev. B | Page 87 of 145 AD9172 Data Sheet Addr. Name Bits 0 0x02B IRQ_OUTPUT_MUX2 [7:6] 5 4 [3:2] 1 0 0x02C IRQ_STATUS_ALL [7:1] 0 0x036 SYSREF_COUNT [7:0] 0x039 SYSREF_ERR_ 7 WINDOW [6:0] 0x03A SYSREF_MODE [7:5] 4 [3:2] 1 0 0x03B ROTATION_MODE 7 Bit Name MUX_PAERR1 RESERVED MUX_DLL_LOST MUX_DLL_LOCK RESERVED MUX_PLL_LOST MUX_PLL_LOCK RESERVED IRQ_STATUS_ALL SYSREF_COUNT RESERVED SYSREF_ERR_ WINDOW RESERVED SYNC_ROTATION_ DONE RESERVED SYSREF_MODE_ ONESHOT RESERVED SYNCLOGIC_EN Settings 0 1 0 1 0 1 0 1 0 1 Description If EN_PAERR1 is set, this control chooses the IRQx output pin on which the event is triggered. Route IRQ trigger signal to the IRQ0 pin. Route IRQ trigger signal to the IRQ1 pin. Reserved. If EN_DLL_LOST is set, this control chooses the IRQx output pin on which the event is triggered. Route IRQ trigger signal to the IRQ0 pin. Route IRQ trigger signal to the IRQ1 pin. If EN_DLL_LOCK is set, this control chooses the IRQx output pin on which the event is triggered. Route IRQ trigger signal to the IRQ0 pin. Route IRQ trigger signal to the IRQ1 pin. Reserved. If EN_PLL_LOST is set, this control chooses the IRQx pin on which the event is triggered. Route IRQ trigger signal to the IRQ0 pin. Route IRQ trigger signal to the IRQ1 pin. If EN_PLL_LOCK is set, this control chooses the IRQx pin on which the event is triggered. Route IRQ trigger signal to the IRQ0 pin. Route IRQ trigger signal to the IRQ1 pin. Reserved. This bit is an OR of all the bits in Register 0x24 to Register 0x27. Writing a one to this bit clears any latched IRQx signals in Register 0x24 to Register 0x27. Number of rising SYSREF± edges to ignore before synchronization (pulse counting mode). Reserved. Amount of jitter allowed on the SYSREF± input. SYSREF± jitter variations larger than this trigger an interrupt. Units are in DAC clocks. Reserved. Synchronization logic rotation complete flag. Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x1 Reserved. 0x0 Enable one-shot synchronization rotation 0x0 mode. 00 Monitor mode. Status/error flag for IRQ_ SYSREF_JITTER is 1 if the SYSREF± edge is outside the error window (Register 0x039, Bits[6:0]). 01 Perform a single synchronization on the next SYSREF±, then switch to monitor mode. Reserved. 0x0 This bit must always be set to 1 (default) for 0x1 both Subclass 0 and Subclass 1 operations. Rev. B | Page 88 of 145 Access R/W R R/W R/W R/W R/W R/W R R/W R/W R R/W R R R R/W R/W R/W Data Sheet Addr. Name 0x03F TX_ENABLE 0x050 CAL_CLK_DIV 0x051 CAL_CTRL AD9172 Bits Bit Name Settings Description Reset 6 RESERVED Reserved. For proper operation, write this 0x0 bit to a 1. 5 PERIODIC_RST_EN Synchronization required setting. Always 0x1 set this bit to 1 for both Subclass 0 and Subclass 1 operation. 4 NCORST_AFTER_ ROT_EN Set this bit to 1 to reset all NCOs after digital 0x1 reset or synchronization rotation. Either this control or the START_NCO_SYNC bit (Register 0x1E7, Bit 0) can be used to reset all the NCOs (main and channel datapaths). [3:2] RESERVED Reserved. 0x0 [1:0] ROTATION_MODE Selects the circuitry to be reset when a 0x0 synchronization rotation occurs. Certain bits being set to 1 determine the actions taken when a synchronization rotation is per- formed. Bit 0 corresponds to a SERDES clock reset and realignment. Bit 1 corresponds to a datapath soft off/on gain, which must only be used if PA protection is in use. If PA protection is not used, set Bit 1 to 0. 0 No action, with either the SERDES clocks or the datapath, occurs when a synchro- nization rotation occurs. 1 The links drop and the SERDES clocks are reset. It is recommended to set this bit high so that when a synchronization rotation is performed, the SERDES clocks realign properly. 10 The datapath automatically uses the soft on/off functionality to turn on and off the datapath stream during a synchronization rotation to avoid corrupted data from being transmitted. Only use this feature if the PA protection block is in use. 11 Both the SERDES clock reset and datapath soft on/off feature are enabled. [7:6] RESERVED Reserved. 0x0 5 TXEN_DATAPATH_ DAC1 Selects whether the datapath of DAC1 is 0x0 muted when the TXEN1 pin is brought low. 0 Datapath output is normal. 1 If TXEN1 = 0, the datapath output is immediately zeroed. If TXEN1 = 1, the datapath outputs normal operation. 4 TXEN_DATAPATH_ DAC0 Selects whether the datapath of DAC0 is 0x0 muted when the TXEN0 pin is brought low. 0 Datapath output is normal. 1 If TXEN0 = 0, the datapath output is immediately zeroed. If TXEN0 = 1, the datapath outputs normal operation. [3:0] RESERVED Reserved. 0x0 [7:4] RESERVED Reserved 0x2 [3:0] CAL_CLK_DIV Calibration register control. Set these bits 0x8 to 0xA for optimized calibration setting. 7 CAL_CTRL0 Calibration setting. Set this bit to 1. 0x1 0 Reset the calibration engine. 1 Enable the calibration routine. Access R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W Rev. B | Page 89 of 145 AD9172 Addr. Name 0x052 CAL_STAT 0x059 FSC0 0x05A FSC1 0x061 CAL_DEBUG0 0x081 CLK_CTRL 0x083 NVM_CTRL0 Data Sheet Bits Bit Name Settings Description Reset [6:3] RESERVED Reserved. 0x0 [2:1] CAL_CTRL1 Calibration mode selection. Set this bit 0x1 field to 1 for optimized calibration mode. Paged by the MAINDAC_PAGE bits in Register 0x008. 1 Set calibration control setting. 0 CAL_START Start calibration. After starting calibration, do 0x0 not write to any register from Register 0x051 to Register 0x061 until Register 0x052, Bit 2 reads low (indicating that the calibration is no longer active). Paged by the MAINDAC_ PAGE bits in Register 0x008. [7:3] RESERVED Reserved. 0x0 2 CAL_ACTIVE Calibration active status flag. A readback of 0x0 1 indicates the calibration routine is still in progress. This control is paged by the MAINDAC_PAGE bits in Register 0x008. 1 CAL_FAIL_SEARCH Calibration failure flag. A readback of 1 0x0 indicates the calibration routine failed and is possibly not valid. This control is paged by the MAINDAC_PAGE bits in Register 0x008. 0 CAL_FINISH Calibration complete flag. A readback of 1 0x0 indicates the calibration completed. This control is paged by the MAINDAC_PAGE bits in Register 0x008. [7:2] RESERVED Reserved. 0xA [1:0] FSC_CTRL[1:0] Sets the full-scale current control. This 0x0 control is paged by the MAINDAC_PAGE bits in Register 0x008. Full-scale current = 15.6 mA + FSC_CTRL × (25/256) (mA). [7:0] FSC_CTRL[9:2] Sets the full-scale current control. This control is paged by the MAINDAC_PAGE bits in Register 0x008. Full-scale current = 15.6 mA + FSC_CTRL × (25/256) (mA). 0x28 7 RESERVED Reserved. 0x0 6 CAL_CTRL2 Calibration control. Set this bit to 1 for 0x1 optimized calibration setting. 5 CAL_CTRL3 Calibration control. Set this bit to 1 for 0x1 optimized calibration setting. 4 RESERVED Reserved. 0x0 3 CAL_CTRL4 Calibration control. Set this bit to 1 for 0x0 optimized calibration setting. [2:0] RESERVED Reserved. 0x0 [7:2] RESERVED Reserved. 0x0 1 CAL_CLK_PD1 After the calibration is complete for DAC1 0x0 (Register 0x052, Bit 0 = 1), set this bit high to power down the calibration clock. 0 CAL_CLK_PD0 After the calibration is complete for DAC0 0x0 (Register 0x052, Bit 0 = 1), set this bit high to power down the calibration clock. 7 NVM_CTRL0A NVM register control for the ring oscillator. 0x0 [6:2] RESERVED Reserved. 0x0 [1:0] NVM_CTRL0B NVM register control for the ring oscillator. 0x2 00 Divide by 8. 01 Divide by 16. 10 Divide by 32. 11 Divide by 64. Rev. B | Page 90 of 145 Access R/W R/W R/W R/W R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W Data Sheet AD9172 Addr. Name Bits 0x084 SYSREF_CTRL 7 6 [5:1] 0 0x085 NVM_CTRL1 7 [6:4] [3:2] 1 0 0x08D ADC_CLK_CTRL0 [7:5] [4:0] 0x08F ADC_CLK_CTRL2 [7:1] 0 0x090 DAC_POWERDOWN [7:2] 1 0 0x091 ACLK_CTRL [7:1] 0 0x094 PLL_CLK_DIV [7:2] 1 Bit Name RESERVED SYSREF_ INPUTMODE RESERVED SYSREF_PD Settings 0 1 0 1 RESERVED NVM_CTRL1A RESERVED NVM_CTRL1B NVM_CTRL1C RESERVED CLKOUT_SWING RESERVED PD_CLKOUT_ DRIVER RESERVED DAC_PD1 0 1 DAC_PD0 0 1 RESERVED ACLK_ POWERDOWN RESERVED PLL_VCO_DIV3_EN Description Reserved. Sets the input mode type for the SYSREF± pins. AC couple SYSREF±. DC couple SYSREF±. Reserved. Power down the SYSREF± receiver and synchronization circuitry. If using Subclass 0, set this bit to 1 because the SYSREF± pins are not used. SYSREF± receiver is powered on. SYSREF± receiver is powered down. Reserved. NVM control. Set this control to 1 at the start of the configuration sequence (as shown in the Start-Up Sequence section) and set to 0 at the end of the start-up routine when no longer programming the device. Reserved. NVM control. Set this control to 1 at the start of the configuration sequence (as shown in the Start-Up Sequence section) and set to 0 at the end of the start-up routine when no longer programming the device. NVM control. Set this control to 0 at the start of the configuration sequence (as shown in the Start-Up Sequence section) and set to 1 at the end of the start-up routine when no longer programming the device. Reserved. Controls the swing level of the ADC clock driver. Note that swing can be negative (inverts clock). The calculation for Code 0 to Code 9 is as follows: ADC driver swing = 993 mV - CLKOUT_ SWING × 77 mV. The calculation for Code 10 to Code 19 is as follows: ADC driver swing = (20 - CLKOUT_SWING × 77 mV) - 1 V. Reserved. Powers down the CLKOUT± output driver. Reset 0x0 0x0 0x0 0x0 0x0 0x1 0x0 0x1 0x1 0x0 0x0 0x0 0x0 Reserved. 0x0 Powers down DAC1. 0x1 Power up DAC1. Power down DAC1. Powers down DAC0. 0x1 Power up DAC0. Power down DAC0. Reserved. 0x0 Analog clock receiver power-down. 0x1 Reserved. 0x0 Enable PLL output clock divide by 3. 0x0 Rev. B | Page 91 of 145 Access R/W R/W R/W R/W R R/W R R/W R/W R R/W R R/W R R/W R/W R/W R/W R R/W AD9172 Data Sheet Addr. Name Bits Bit Name Settings Description Reset 0 PLL_VCO_DIV2_EN Enable PLL output clock divide by 2. 0x0 0 DAC clock = PLL VCO clock frequency. 1 DAC clock = PLL VCO clock frequency ÷ 2. 0x095 PLL_BYPASS [7:1] RESERVED Reserved. 0x0 0 PLL_BYPASS Enable direct clocking (bypassing the PLL 0x0 clock). 0 Use the internal PLL to generate the DAC clock. 1 Bypass the PLL and directly clock with the DAC clock frequency. 0x09A NVM_CTRL 7 PD_BGR Bias power-down. Set this bit to 1 to power 0x0 down the internal bias. [6:0] RESERVED Reserved. 0x0 0x0C0 DELAY_LINE_PD [7:6] RESERVED Reserved. 0x0 5 DLL_CTRL0B DLL control. Set this bit to 0 to power up 0x1 the delay line during the device configuration sequence. 4 DLL_CTRL0A DLL control. Set this bit to 0 to power up 0x1 the delay line during the device configuration sequence. [3:1] RESERVED Reserved. 0x0 0 DLL_PD Power down delay line. Set this bit to 0 to 0x1 power up the delay line during the device configuration sequence. 0 Power up and enable the delay line. 1 Power down and bypass the delay line. 0x0C1 DLL_CTRL0 [7:6] DLL_CTRL1C DAC control setting. Set this control to 1 0x1 for optimal performance. 5 DLL_CTRL1B DLL control search mode. If the DAC 0x1 frequency is <4.5 GHz, set this bit to 0; otherwise, set this bit to 1. [4:3] DLL_CTRL1A DLL control search direction. Set this 0x2 control to 1 for optimal performance. [2:1] RESERVED Reserved. 0x0 0 DLL_ENABLE DLL controller enable. 0x0 0 Disable DLL. 1 Enable DLL. 0x0C3 DLL_STATUS [7:1] RESERVED Reserved. 0x0 0 DLL_LOCK DLL lock indicator. This control reads back 0x0 1 if the DLL locks. 0x0C7 DLL_READ [7:1] RESERVED Reserved. 0x0 0 DLL_READ_EN Enable DLL readback status. A transition of 0x0 0 to 1 updates the lock status bit readback in Register 0x0C3. 0x0CC DLL_FINE_DELAY0 [7:6] RESERVED Reserved. 0x0 [5:0] DLL_FINE_DELAY0 DLL delay control. 0x0 0x0CD DLL_FINE_DELAY1 [7:6] RESERVED Reserved. 0x0 [5:0] DLL_FINE_DELAY1 DLL delay control. 0x0 0x0DB DLL_UPDATE [7:1] RESERVED Reserved. 0x0 0 DLL_DELAY_ UPDATE DLL update control. A transition from 0 to 1 0x0 updates the DLL circuitry with the current register control settings. Access R/W R R/W R/W R/W R R/W R/W R R/W R/W R/W R/W R R/W R R R R/W R R/W R R/W R R/W Rev. B | Page 92 of 145 Data Sheet AD9172 Addr. Name Bits Bit Name Settings Description Reset 0x100 DIG_RESET [7:1] RESERVED Reserved. 0x0 0 DIG_DATAPATH_PD Holds all digital logic (SERDES digital, 0x1 digital clock generation, and digital datapath) in reset until clock tree is stable. 0 Normal operating mode. 1 Holds the digital logic in reset. Must be released (set to 0) after clocks to the chip are stable (PLL and DLL blocks are locked) to use the digital datapath. 0x110 JESD_MODE 7 MODE_NOT_IN_ TABLE Programmed JESD204B mode and interpola- 0x0 tion mode combination is not valid. Select a different combination. 6 COM_SYNC Combine the SYNCOUTx± signals in dual 0x0 link case. [5:0] JESD_MODE Sets the JESD204B mode configuration. See Table 13 for the JESD204B supported operating modes and compatible interpolation rates. Bit 5 of this control determines single link (set to 0) or dual link (set to 1). Bits[4:0] set the desired JESD204B mode according to Table 13. 0x20 0x111 INTRP_MODE [7:4] DP_INTERP_MODE Sets main datapath interpolation rate. See 0x8 Table 13 for the JESD204B supported operating modes and compatible JESD204B modes and channel interpolation rates. 0x1 1×. 0x2 2×. 0x4 4×. 0x6 6×. 0x8 8×. 0xC 12×. [3:0] CH_INTERP_MODE Sets channel interpolation rate. See Table 13 0x4 for the JESD204B supported operating modes and compatible JESD204B modes and main datapath interpolation rates. 0x1 1×. 0x2 2×. 0x3 3×. 0x4 4×. 0x6 6×. 0x8 8×. 0x112 DDSM_DATAPATH_ [7:6] RESERVED CFG [5:4] DDSM_MODE Reserved. 0x0 Modulator switch mode selection. This 0x0 control chooses the mode of operation for the main datapath NCO being configured. This control is paged by the MAINDAC_ PAGE bits in Register 0x008. 00 DAC0 = I0; DAC1 = I1. 01 DAC0 = I0 + I1; DAC1 = Q0 + Q1. 10 DAC0 = I0; DAC1 = Q0. 11 DAC0 = I0 + I1; DAC1 = 0. Access R R/W R R/W R/W R/W R/W R R/W Rev. B | Page 93 of 145 AD9172 Addr. Name 0x113 DDSM_FTW_ UPDATE Data Sheet Bits Bit Name Settings Description Reset 3 DDSM_NCO_EN Main datapath modulation enable. If the 0x0 JESD204B mode chosen is a complex mode (main datapath interpolation >1×), this bit must be set to 1 for each main datapath being used. If no modulation is desired, set the FTW to be 0. This control is paged by the MAINDAC_PAGE bits in Register 0x008. 0 Disable main datapath NCO. 1 Enable main datapath NCO. 2 DDSM_ MODULUS_EN Enable main datapath modulus DDS. This 0x0 control is paged by the MAINDAC_PAGE bits in Register 0x008. 0 Disable modulus DDS. 1 Enable modulus DDS. 1 DDSM_SEL_ SIDEBAND Selects upper or lower sideband from 0x0 modulation result. This control is paged by the MAINDAC_PAGE bits in Register 0x008. 0 Use upper sideband. 1 Use lower sideband = spectral flip. 0 EN_SYNC_ALL_ CHNL_NCO_RESETS Selects the signal channel NCOS used for 0x1 resets and FTW updates. This control is paged by the MAINDAC_PAGE bits in Register 0x008. 0 Channel NCOs reset or update their FTW based on channel NCO update requests. 1 Channel NCOs reset or update their FTW based on main datapath NCO update requests. 7 RESERVED Reserved. 0x0 [6:4] DDSM_FTW_REQ_ MODE Frequency tuning word automatic update 0x0 mode. This control is paged by the MAINDAC_PAGE bits in Register 0x008. 000 No automatic requests are generated when the FTW registers are written. 001 Automatically generates a DDSM_FTW_ LOAD_REQ after DDSM_FTW Bits[7:0] are written. 010 Automatically generates a DDSM_FTW_ LOAD_REQ after DDSM_FTW Bits[15:8] are written. 011 Automatically generates a DDSM_FTW_ LOAD_REQ after DDSM_FTW Bits[23:16] are written. 100 Automatically generates a DDSM_FTW_ LOAD_REQ after DDSM_FTW Bits[31:24] are written. 101 Automatically generate a DDSM_FTW_ LOAD_REQ after DDSM_FTW Bits[39:32] is written. 110 Automatically generates a DDSM_FTW_ LOAD_REQ after DDSM_FTW Bits[47:40] are written. 3 RESERVED Reserved. 0x0 Access R/W R/W R/W R/W R R/W R Rev. B | Page 94 of 145 Data Sheet Addr. Name 0x114 DDSM_FTW0 0x115 DDSM_FTW1 0x116 DDSM_FTW2 AD9172 Bits Bit Name Settings Description Reset 2 DDSM_FTW_ LOAD_SYSREF Uses the next rising edge of SYSREF± to 0x0 trigger FTW load and reset. This bit also loads the calibration tone FTW, as well as the main NCO FTW on a rising edge detection. This control is paged by the MAINDAC_PAGE bits in Register 0x008. 1 DDSM_FTW_ LOAD_ACK Frequency tuning word update acknow- 0x0 ledge. This bit reads back 1 if the FTW and phase offset word is loaded properly. This control is paged by the MAINDAC_PAGE bits in Register 0x008. 0 FTW is not loaded. 1 FTW is loaded. 0 DDSM_FTW_ LOAD_REQ Frequency tuning word update request 0x0 from the SPI. This bit also loads the calibra- tion tone FTW, as well as the main NCO FTW on a rising edge detection. This control is paged by the MAINDAC_PAGE bits in Register 0x008. 0 Clear DDSM_FTW_LOAD_ACK. 1 0 to 1 transition loads the FTW. [7:0] DDSM_FTW[7:0] Sets the main datapath NCO FTW. If 0x0 DDSM_MODULUS_EN is low, the main datapath NCO frequency = fDAC × (DDSM_ FTW/248). If DDSM_MODULUS_EN is high, the main datapath NCO frequency = fDAC × (DDSM_FTW + DDSM_ACC_DELTA/DDSM_ ACC_MODULUS)/248. DDSM_ACC_DELTA must be >0. DDSM_ACC_DELTA must be >DDSM_ACC_MODULUS. This control is paged by the MAINDAC_PAGE bits in Register 0x008. [7:0] DDSM_FTW[15:8] Sets the main datapath NCO FTW. If 0x0 DDSM_MODULUS_EN is low, the main datapath NCO frequency = fDAC × (DDSM_ FTW/248. If DDSM_MODULUS_EN is high, the main datapath NCO frequency = fDAC × (DDSM_FTW + DDSM_ACC_DELTA/DDSM_ ACC_MODULUS)/248. DDSM_ACC_DELTA must be > 0. DDSM_ACC_DELTA must be > DDSM_ACC_MODULUS. This control is paged by the MAINDAC_PAGE bits in Register 0x008. [7:0] DDSM_FTW[23:16] Sets the main datapath NCO FTW. If 0x0 DDSM_MODULUS_EN is low, the main datapath NCO frequency = fDAC × (DDSM_ FTW/248. If DDSM_MODULUS_EN is high, the main datapath NCO frequency = fDAC × (DDSM_FTW + DDSM_ACC_DELTA/DDSM_ ACC_MODULUS)/248. DDSM_ACC_DELTA must be > 0. DDSM_ACC_DELTA must be > DDSM_ACC_MODULUS. This control is paged by the MAINDAC_PAGE bits in Register 0x008. Access R/W R R/W R/W R/W R/W Rev. B | Page 95 of 145 AD9172 Addr. Name 0x117 DDSM_FTW3 0x118 DDSM_FTW4 0x119 DDSM_FTW5 0x11C DDSM_PHASE_ OFFSET0 0x11D DDSM_PHASE_ OFFSET1 0x124 DDSM_ACC_ MODULUS0 0x125 DDSM_ACC_ MODULUS1 Data Sheet Bits Bit Name Settings Description Reset [7:0] DDSM_FTW[31:24] Sets the main datapath NCO FTW. If 0x0 DDSM_MODULUS_EN is low, the main datapath NCO frequency = fDAC × (DDSM_ FTW/248. If DDSM_MODULUS_EN is high, the main datapath NCO frequency = fDAC × (DDSM_FTW + DDSM_ACC_DELTA/DDSM_ ACC_MODULUS)/248. DDSM_ACC_DELTA must be > 0. DDSM_ACC_DELTA must be > DDSM_ACC_MODULUS. This control is paged by the MAINDAC_PAGE bits in Register 0x008. [7:0] DDSM_FTW[39:32] Sets the main datapath NCO FTW. If 0x0 DDSM_MODULUS_EN is low, the main datapath NCO frequency = fDAC × (DDSM_ FTW/248. If DDSM_MODULUS_EN is high, the main datapath NCO frequency = fDAC × (DDSM_FTW + DDSM_ACC_DELTA/DDSM_ ACC_MODULUS)/248. DDSM_ACC_DELTA must be > 0. DDSM_ACC_DELTA must be > DDSM_ACC_MODULUS. This control is paged by the MAINDAC_PAGE bits in Register 0x008. [7:0] DDSM_FTW[47:40] Sets the main datapath NCO FTW. If 0x0 DDSM_MODULUS_EN is low, the main datapath NCO frequency = fDAC × (DDSM_ FTW/248. If DDSM_MODULUS_EN is high, the main datapath NCO frequency = fDAC × (DDSM_FTW + DDSM_ACC_DELTA/DDSM_ ACC_MODULUS)/248. DDSM_ACC_DELTA must be > 0. DDSM_ACC_DELTA must be > DDSM_ACC_MODULUS. This control is paged by the MAINDAC_PAGE bits in Register 0x008. [7:0] DDSM_NCO_ PHASE_OFFSET[7:0] Sets main datapath NCO phase offset. Code is 0x0 in 16-bit, twos complement format. Degrees offset = 180 × (code/215). This control is paged by the MAINDAC_PAGE bits in Register 0x008. [7:0] DDSM_NCO_ PHASE_ OFFSET[15:8] Sets main datapath NCO phase offset. Code is 0x0 in 16-bit, twos complement format. Degrees offset = 180 × (code/215). This control is paged by the MAINDAC_PAGE bits in Register 0x008. [7:0] DDSM_ACC_ MODULUS[7:0] Sets DDSM_ACC_MODULUS. If DDSM_ 0x0 MODULUS_EN is high, the main datapath NCO frequency = fDAC × (DDSM_FTW + DDSM_ACC_DELTA/DDSM_ACC_MODULUS)/ 248. DDSM_ACC_DELTA must be > 0. DDSM_ ACC_DELTA must be > DDSM_ACC_ MODULUS. This control is paged by the MAINDAC_PAGE bits in Register 0x008. [7:0] DDSM_ACC_ MODULUS[15:8] Sets DDSM_ACC_MODULUS. If DDSM_ 0x0 MODULUS_EN is high, the main datapath NCO frequency = fDAC × (DDSM_FTW + DDSM_ACC_DELTA/DDSM_ACC_MODULUS)/ 248. DDSM_ACC_DELTA must be > 0. DDSM_ ACC_DELTA must be > DDSM_ACC_ MODULUS. This control is paged by the MAINDAC_PAGE bits in Register 0x008. Access R/W R/W R/W R/W R/W R/W R/W Rev. B | Page 96 of 145 Data Sheet AD9172 Addr. Name Bits 0x126 DDSM_ACC_ [7:0] MODULUS2 0x127 DDSM_ACC_ [7:0] MODULUS3 0x128 DDSM_ACC_ [7:0] MODULUS4 0x129 DDSM_ACC_ [7:0] MODULUS5 0x12A DDSM_ACC_DELTA0 [7:0] 0x12B DDSM_ACC_DELTA1 [7:0] 0x12C DDSM_ACC_DELTA2 [7:0] Bit Name DDSM_ACC_ MODULUS[23:16] DDSM_ACC_ MODULUS[31:24] DDSM_ACC_ MODULUS[39:32] DDSM_ACC_ MODULUS[47:40] DDSM_ACC_ DELTA[7:0] DDSM_ACC_ DELTA[15:8] DDSM_ACC_ DELTA[23:16] Settings Description Sets DDSM_ACC_MODULUS. If DDSM_ MODULUS_EN is high, the main datapath NCO frequency = fDAC × (DDSM_FTW + DDSM_ACC_DELTA/DDSM_ACC_MODULUS)/ 248. DDSM_ACC_DELTA must be > 0. DDSM_ ACC_DELTA must be > DDSM_ACC_ MODULUS. This control is paged by the MAINDAC_PAGE bits in Register 0x008. Sets DDSM_ACC_MODULUS. If DDSM_ MODULUS_EN is high, the main datapath NCO frequency = fDAC × (DDSM_FTW + DDSM_ACC_DELTA/DDSM_ACC_MODULUS)/ 248. DDSM_ACC_DELTA must be > 0. DDSM_ ACC_DELTA must be > DDSM_ACC_ MODULUS. This control is paged by the MAINDAC_PAGE bits in Register 0x008. Sets DDSM_ACC_MODULUS. If DDSM_ MODULUS_EN is high, the main datapath NCO frequency = fDAC × (DDSM_FTW + DDSM_ACC_DELTA/DDSM_ACC_MODULUS)/ 248. DDSM_ACC_DELTA must be > 0. DDSM_ ACC_DELTA must be > DDSM_ACC_ MODULUS. This control is paged by the MAINDAC_PAGE bits in Register 0x008. Sets DDSM_ACC_MODULUS. If DDSM_ MODULUS_EN is high, the main datapath NCO frequency = fDAC × (DDSM_FTW + DDSM_ACC_DELTA/DDSM_ACC_MODULUS)/ 248. DDSM_ACC_DELTA must be > 0. DDSM_ ACC_DELTA must be > DDSM_ACC_ MODULUS. This control is paged by the MAINDAC_PAGE bits in Register 0x008. Sets DDSM_ACC_DELTA. If DDSM_ MODULUS_EN is high, main datapath NCO frequency = fDAC × (DDSM_FTW + DDSM_ ACC_DELTA/DDSM_ACC_MODULUS)/248. DDSM_ACC_DELTA must be > 0. DDSM_ ACC_DELTA must be > DDSM_ACC_ MODULUS. This control is paged by the MAINDAC_PAGE bits in Register 0x008. Sets DDSM_ACC_DELTA. If DDSM_ MODULUS_EN is high, main datapath NCO frequency = fDAC × (DDSM_FTW + DDSM_ ACC_DELTA/DDSM_ACC_MODULUS)/248. DDSM_ACC_DELTA must be > 0. DDSM_ ACC_DELTA must be > DDSM_ACC_ MODULUS. This control is paged by the MAINDAC_PAGE bits in Register 0x008. Sets DDSM_ACC_DELTA. If DDSM_ MODULUS_EN is high, main datapath NCO frequency = fDAC × (DDSM_FTW + DDSM_ ACC_DELTA/DDSM_ACC_MODULUS)/248. DDSM_ACC_DELTA must be > 0. DDSM_ ACC_DELTA must be > DDSM_ACC_ MODULUS. This control is paged by the MAINDAC_PAGE bits in Register 0x008. Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R/W R/W R/W R/W R/W R/W R/W Rev. B | Page 97 of 145 AD9172 Data Sheet Addr. Name Bits 0x12D DDSM_ACC_DELTA3 [7:0] 0x12E DDSM_ACC_DELTA4 [7:0] 0x12F DDSM_ACC_DELTA5 [7:0] 0x130 DDSC_DATAPATH_ 7 CFG 6 [5:3] 2 1 0 0x131 DDSC_FTW_UPDATE [7:3] 2 Bit Name DDSM_ACC_ DELTA[31:24] DDSM_ACC_ DELTA[39:32] DDSM_ACC_ DELTA[47:40] RESERVED DDSC_NCO_EN RESERVED DDSC_MODULUS_ EN DDSC_SEL_ SIDEBAND DDSC_EN_DC_ INPUT RESERVED DDSC_FTW_ LOAD_SYSREF Settings 0 1 0 1 0 1 0 1 Description Sets DDSM_ACC_DELTA. If DDSM_ MODULUS_EN is high, main datapath NCO frequency = fDAC × (DDSM_FTW + DDSM_ ACC_DELTA/DDSM_ACC_MODULUS)/248. DDSM_ACC_DELTA must be > 0. DDSM_ ACC_DELTA must be > DDSM_ACC_ MODULUS. This control is paged by the MAINDAC_PAGE bits in Register 0x008. Sets DDSM_ACC_DELTA. If DDSM_ MODULUS_EN is high, main datapath NCO frequency = fDAC × (DDSM_FTW + DDSM_ ACC_DELTA/DDSM_ACC_MODULUS)/248. DDSM_ACC_DELTA must be > 0. DDSM_ ACC_DELTA must be > DDSM_ACC_ MODULUS. This control is paged by the MAINDAC_PAGE bits in Register 0x008. Sets DDSM_ACC_DELTA. If DDSM_ MODULUS_EN is high, main datapath NCO frequency = fDAC × (DDSM_FTW + DDSM_ ACC_DELTA/DDSM_ACC_MODULUS)/248. DDSM_ACC_DELTA must be > 0. DDSM_ ACC_DELTA must be > DDSM_ACC_ MODULUS. This control is paged by the MAINDAC_PAGE bits in Register 0x008. Reserved. Channel datapath modulation enable. If the JESD204B mode chosen is a complex mode (channel interpolation >1×), this bit must be set to 1 for each channel datapath being used. If no modulation is desired, set the FTW to 0. This control is paged by the CHANNEL_PAGE bits in Register 0x008. Disable channel NCO. Enable channel NCO. Reserved. Enable channel modulus DDS. This control is paged by the CHANNEL_PAGE bits in Register 0x008. Disable modulus DDS. Enable modulus DDS. Selects upper or lower sideband from modulation result. This control is paged by the CHANNEL_PAGE bits in Register 0x008. Use upper sideband. Use lower sideband = spectral flip. Enable test tone generation by sending dc to input level to channel DDS. Set the amplitude in the DC_TEST_INPUT_ AMPLITUDE control (Register 0x148 and Register 0x149). This control is paged by the CHANNEL_PAGE bits in Register 0x008. Disable test tone generation. Enable test tone generation. Reserved. Use next rising edge of SYSREF± to trigger FTW load and reset. This control is paged by the CHANNEL_PAGE bits in Register 0x008. Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R/W R/W R/W R R/W R/W R/W R/W R/W R R/W Rev. B | Page 98 of 145 Data Sheet Addr. Name 0x132 DDSC_FTW0 0x133 DDSC_FTW1 0x134 DDSC_FTW2 0x135 DDSC_FTW3 AD9172 Bits Bit Name Settings Description 1 DDSC_FTW_ LOAD_ACK Frequency tuning word update acknowledge bit. This bit reads back 1 if the FTW and phase offset word is loaded properly. This control is paged by the CHANNEL_ PAGE bits in Register 0x008. 0 FTW is not loaded. 1 FTW is loaded. 0 DDSC_FTW_ LOAD_REQ Frequency tuning word update request from the SPI. This control is paged by the CHANNEL_PAGE bits in Register 0x008. 0 No FTW update. 1 0 to 1 transition loads the FTW. [7:0] DDSC_FTW[7:0] Sets the channel datapath NCO FTW. If DDSC_MODULUS_EN is low, the main datapath NCO frequency = fDAC × (DDSC_ FTW/248). If DDSC_MODULUS_EN is high, main datapath NCO frequency = fDAC × (DDSC_FTW + DDSC_ACC_DELTA/DDSC_ ACC_MODULUS)/248. DDSC_ACC_DELTA must be > 0. DDSC_ACC_DELTA must be > DDSC_ACC_MODULUS. This control is paged by the CHANNEL_PAGE bits in Register 0x008. [7:0] DDSC_FTW[15:8] Sets the channel datapath NCO FTW. If DDSC_MODULUS_EN is low, the main datapath NCO frequency = fDAC × (DDSC_ FTW/248). If DDSC_MODULUS_EN is high, main datapath NCO frequency = fDAC × (DDSC_FTW + DDSC_ACC_DELTA/DDSC_ ACC_MODULUS)/248. DDSC_ACC_DELTA must be > 0. DDSC_ACC_DELTA must be > DDSC_ACC_MODULUS. This control is paged by the CHANNEL_PAGE bits in Register 0x008. [7:0] DDSC_FTW[23:16] Sets the channel datapath NCO FTW. If DDSC_MODULUS_EN is low, the main datapath NCO frequency = fDAC × (DDSC_ FTW/248). If DDSC_MODULUS_EN is high, main datapath NCO frequency = fDAC × (DDSC_FTW + DDSC_ACC_DELTA/DDSC_ ACC_MODULUS)/248. DDSC_ACC_DELTA must be > 0. DDSC_ACC_DELTA must be > DDSC_ACC_MODULUS. This control is paged by the CHANNEL_PAGE bits in Register 0x008. [7:0] DDSC_FTW[31:24] Sets the channel datapath NCO FTW. If DDSC_MODULUS_EN is low, the main datapath NCO frequency = fDAC × (DDSC_ FTW/248). If DDSC_MODULUS_EN is high, main datapath NCO frequency = fDAC × (DDSC_FTW + DDSC_ACC_DELTA/DDSC_ ACC_MODULUS)/248. DDSC_ACC_DELTA must be > 0. DDSC_ACC_DELTA must be > DDSC_ACC_MODULUS. This control is paged by the CHANNEL_PAGE bits in Register 0x008. Reset 0x0 0x0 0x0 0x0 0x0 0x0 Access R R/W R/W R/W R/W R/W Rev. B | Page 99 of 145 AD9172 Addr. Name 0x136 DDSC_FTW4 0x137 DDSC_FTW5 0x138 DDSC_PHASE_ OFFSET0 0x139 DDSC_PHASE_ OFFSET1 0x13A DDSC_ACC_ MODULUS0 0x13B DDSC_ACC_ MODULUS1 0x13C DDSC_ACC_ MODULUS2 Data Sheet Bits Bit Name Settings Description Reset [7:0] DDSC_FTW[39:32] Sets the channel datapath NCO FTW. If 0x0 DDSC_MODULUS_EN is low, the main datapath NCO frequency = fDAC × (DDSC_ FTW/248). If DDSC_MODULUS_EN is high, main datapath NCO frequency = fDAC × (DDSC_FTW + DDSC_ACC_DELTA/DDSC_ ACC_MODULUS)/248. DDSC_ACC_DELTA must be > 0. DDSC_ACC_DELTA must be > DDSC_ACC_MODULUS. This control is paged by the CHANNEL_PAGE bits in Register 0x008. [7:0] DDSC_FTW[47:40] Sets the channel datapath NCO FTW. If 0x0 DDSC_MODULUS_EN is low, the main datapath NCO frequency = fDAC × (DDSC_ FTW/248). If DDSC_MODULUS_EN is high, main datapath NCO frequency = fDAC × (DDSC_FTW + DDSC_ACC_DELTA/DDSC_ ACC_MODULUS)/248. DDSC_ACC_DELTA must be > 0. DDSC_ACC_DELTA must be > DDSC_ACC_MODULUS. This control is paged by the CHANNEL_PAGE bits in Register 0x008. [7:0] DDSC_NCO_ PHASE_OFFSET[7:0] Sets the channel NCO phase offset. Code is in 0x0 16-bit, twos complement format. Degrees offset = 180 × (code/215). This control is paged by the CHANNEL_PAGE bits in Register 0x008. [7:0] DDSC_NCO_ PHASE_ OFFSET[15:8] Sets the channel NCO phase offset. Code is in 0x0 16-bit, twos complement format. Degrees offset = 180 × (code/215). This control is paged by the CHANNEL_PAGE bits in Register 0x008. [7:0] DDSC_ACC_ MODULUS[7:0] Sets DDSC_ACC_MODULUS. If DDSC_ 0x0 MODULUS_EN is high, the main datapath NCO frequency = fDAC × (DDSC_FTW + DDSC_ ACC_DELTA/DDSC_ACC_MODULUS)/248. DDSC_ACC_DELTA must be > 0. DDSC_ACC_ DELTA must be > DDSC_ACC_MODULUS. This control is paged by the CHANNEL_ PAGE bits in Register 0x008. [7:0] DDSC_ACC_ MODULUS[15:8] Sets DDSC_ACC_MODULUS. If DDSC_ 0x0 MODULUS_EN is high, the main datapath NCO frequency = fDAC × (DDSC_FTW + DDSC_ ACC_DELTA/DDSC_ACC_MODULUS)/248. DDSC_ACC_DELTA must be > 0. DDSC_ACC_ DELTA must be > DDSC_ACC_MODULUS. This control is paged by the CHANNEL_ PAGE bits in Register 0x008. [7:0] DDSC_ACC_ MODULUS[23:16] Sets DDSC_ACC_MODULUS. If DDSC_ 0x0 MODULUS_EN is high, the main datapath NCO frequency = fDAC × (DDSC_FTW + DDSC_ ACC_DELTA/DDSC_ACC_MODULUS)/248. DDSC_ACC_DELTA must be > 0. DDSC_ACC_ DELTA must be > DDSC_ACC_MODULUS. This control is paged by the CHANNEL_ PAGE bits in Register 0x008. Access R/W R/W R/W R/W R/W R/W R/W Rev. B | Page 100 of 145 Data Sheet AD9172 Addr. Name Bits 0x13D DDSC_ACC_ [7:0] MODULUS3 0x13E DDSC_ACC_ [7:0] MODULUS4 0x13F DDSC_ACC_ [7:0] MODULUS5 0x140 DDSC_ACC_DELTA0 [7:0] 0x141 DDSC_ACC_ [7:0] DELTA1 0x142 DDSC_ACC_DELTA2 [7:0] 0x143 DDSC_ACC_DELTA3 [7:0] Bit Name DDSC_ACC_ MODULUS[31:24] DDSC_ACC_ MODULUS[39:32] DDSC_ACC_ MODULUS[47:40] DDSC_ACC_ DELTA[7:0] DDSC_ACC_ DELTA[15:8] DDSC_ACC_ DELTA[23:16] DDSC_ACC_ DELTA[31:24] Settings Description Sets DDSC_ACC_MODULUS. If DDSC_ MODULUS_EN is high, the main datapath NCO frequency = fDAC × (DDSC_FTW + DDSC_ ACC_DELTA/DDSC_ACC_MODULUS)/248. DDSC_ACC_DELTA must be > 0. DDSC_ACC_ DELTA must be > DDSC_ACC_MODULUS. This control is paged by the CHANNEL_ PAGE bits in Register 0x008. Sets DDSC_ACC_MODULUS. If DDSC_ MODULUS_EN is high, the main datapath NCO frequency = fDAC × (DDSC_FTW + DDSC_ ACC_DELTA/DDSC_ACC_MODULUS)/248. DDSC_ACC_DELTA must be > 0. DDSC_ACC_ DELTA must be > DDSC_ACC_MODULUS. This control is paged by the CHANNEL_ PAGE bits in Register 0x008. Sets DDSC_ACC_MODULUS. If DDSC_ MODULUS_EN is high, the main datapath NCO frequency = fDAC × (DDSC_FTW + DDSC_ ACC_DELTA/DDSC_ACC_MODULUS)/248. DDSC_ACC_DELTA must be > 0. DDSC_ACC_ DELTA must be > DDSC_ACC_MODULUS. This control is paged by the CHANNEL_ PAGE bits in Register 0x008. Sets DDSC_ACC_DELTA. If DDSC_ MODULUS_EN is high, the main datapath NCO frequency = fDAC × (DDSC_FTW + DDSC_ ACC_DELTA/DDSC_ACC_MODULUS)/248. DDSC_ACC_DELTA must be > 0. DDSC_ ACC_DELTA must be > DDSC_ACC_ MODULUS. This control is paged by the CHANNEL_PAGE bits in Register 0x008. Sets DDSC_ACC_DELTA. If DDSC_ MODULUS_EN is high, the main datapath NCO frequency = fDAC × (DDSC_FTW + DDSC_ ACC_DELTA/DDSC_ACC_MODULUS)/248. DDSC_ACC_DELTA must be > 0. DDSC_ ACC_DELTA must be > DDSC_ACC_ MODULUS. This control is paged by the CHANNEL_PAGE bits in Register 0x008. Sets DDSC_ACC_DELTA. If DDSC_ MODULUS_EN is high, the main datapath NCO frequency = fDAC × (DDSC_FTW + DDSC_ ACC_DELTA/DDSC_ACC_MODULUS)/248. DDSC_ACC_DELTA must be > 0. DDSC_ ACC_DELTA must be > DDSC_ACC_ MODULUS. This control is paged by the CHANNEL_PAGE bits in Register 0x008. Sets DDSC_ACC_DELTA. If DDSC_ MODULUS_EN is high, the main datapath NCO frequency = fDAC × (DDSC_FTW + DDSC_ ACC_DELTA/DDSC_ACC_MODULUS)/248. DDSC_ACC_DELTA must be > 0. DDSC_ ACC_DELTA must be > DDSC_ACC_ MODULUS. This control is paged by the CHANNEL_PAGE bits in Register 0x008. Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R/W R/W R/W R/W R/W R/W R/W Rev. B | Page 101 of 145 AD9172 Data Sheet Addr. 0x144 0x145 0x146 0x147 0x148 0x149 0x14B Name Bits DDSC_ACC_DELTA4 [7:0] DDSC_ACC_DELTA5 [7:0] CHNL_GAIN0 [7:0] CHNL_GAIN1 [7:4] [3:0] DC_CAL_TONE0 [7:0] DC_CAL_TONE1 [7:0] PRBS 7 6 5 4 3 2 Bit Name DDSC_ACC_ DELTA[39:32] DDSC_ACC_ DELTA[47:40] CHNL_GAIN[7:0] RESERVED CHNL_GAIN[11:8] DC_TEST_INPUT_ AMPLITUDE[7:0] DC_TEST_INPUT_ AMPLITUDE[15:8] PRBS_GOOD_Q PRBS_GOOD_I RESERVED PRBS_INV_Q PRBS_INV_I PRBS_MODE Settings 1 0 0 1 0 1 0 1 0 1 Description Sets DDSC_ACC_DELTA. If DDSC_ MODULUS_EN is high, the main datapath NCO frequency = fDAC × (DDSC_FTW + DDSC_ ACC_DELTA/DDSC_ACC_MODULUS)/248. DDSC_ACC_DELTA must be > 0. DDSC_ ACC_DELTA must be > DDSC_ACC_ MODULUS. This control is paged by the CHANNEL_PAGE bits in Register 0x008. Sets DDSC_ACC_DELTA. If DDSC_ MODULUS_EN is high, the main datapath NCO frequency = fDAC × (DDSC_FTW + DDSC_ ACC_DELTA/DDSC_ACC_MODULUS)/248. DDSC_ACC_DELTA must be > 0. DDSC_ ACC_DELTA must be > DDSC_ACC_ MODULUS. This control is paged by the CHANNEL_PAGE bits in Register 0x008. Sets the scalar channel gain value. This control is paged by the CHANNEL_PAGE bits in Register 0x008. Channel gain = CHNL_GAIN/211. Reserved. Sets the scalar channel gain value. This control is paged by the CHANNEL_PAGE bits in Register 0x008. Channel gain = CHNL_GAIN/211. DC test tone amplitude. This amplitude goes to both I and Q paths. Set these bits to 0x7FFF for a full-scale tone and ensure DDSC_EN_DC_INPUT in Register 0x130 Bit 0 is set to 1. This control is paged by the CHANNEL_PAGE control in Register 0x008. DC test tone amplitude. This amplitude goes to both I and Q paths. Set to 0x7FFF for a full-scale tone and ensure that DDSC_ EN_DC_INPUT (Register 0x130, Bit 0) is set to 1. This control is paged by the CHANNEL_ PAGE bits in Register 0x008. DAC1 good data indicator. Correct PRBS sequence detected. Incorrect sequence detected. Sticky; reset to 1 by PRBS_RESET. DAC0 good data indicator. Incorrect sequence detected. Sticky; reset to 1 by PRBS_RESET. Correct PRBS sequence detected. Reserved. DAC1 data inversion. Expect normal data. Expect inverted data. DAC0 data inversion. Expect normal data. Expect inverted data. Select which PRBS polynomial is used for the datapath PRBS test. 7-bit: x7 + x6 + 1. 15-bit: x15 + x14 + 1. Reset 0x0 0x0 0x0 0x0 0x8 0x0 0x0 0x0 0x0 0x0 0x1 0x0 0x0 Access R/W R/W R/W R R/W R/W R/W R R R R/W R/W R/W Rev. B | Page 102 of 145 Data Sheet AD9172 Addr. Name Bits Bit Name 1 PRBS_RESET 0 PRBS_EN 0x14C 0x14D 0x14E PRBS_ERROR_I PRBS_ERROR_Q PRBS_CHANSEL [7:0] PRBS_COUNT_I [7:0] PRBS_COUNT_Q [7:3] RESERVED [2:0] PRBS_CHANSEL 0x151 DECODE_MODE [7:6] RESERVED [5:4] MSB_MODE [3:0] RESERVED 0x1DE SPI_ENABLE [7:2] RESERVED 1 SPI_EN1 0 SPI_EN0 0x1E2 DDSM_CAL_FTW0 [7:0] DDSM_CAL_ FTW[7:0] 0x1E3 DDSM_CAL_FTW1 [7:0] DDSM_CAL_ FTW[15:8] 0x1E4 DDSM_CAL_FTW2 [7:0] DDSM_CAL_ FTW[23:16] 0x1E5 DDSM_CAL_FTW3 [7:0] DDSM_CAL_ FTW[31:24] 0x1E6 DDSM_CAL_ MODE_DEF [7:3] RESERVED 2 DDSM_EN_CAL_ ACC Settings 0 1 0 1 0 1 2 3 4 5 6 0 1 Description Reset error counters. Normal operation. Reset counters. Enable PRBS checker. Disable. Enable. DAC0 PRBS error count. DAC1 PRBS error count. Reserved. Selects the channel to which the PRBS_ GOOD_x and PRBS_COUNT_x bit field readbacks correspond. Select Channel 0 for PRBS_COUNT_x and PRBS_GOOD_x (Channel 0, DAC0). Select Channel 1 for PRBS_COUNT_x and PRBS_GOOD_x (Channel 1, DAC0). Select Channel 2 for PRBS_COUNT_x and PRBS_GOOD_x (Channel 2, DAC0). Select Channel 3 for PRBS_COUNT_x and PRBS_GOOD_x (Channel 0, DAC1). Select Channel 4 for PRBS_COUNT_x and PRBS_GOOD_x (Channel 1, DAC1). Select Channel 5 for PRBS_COUNT_x and PRBS_GOOD_x (Channel 2, DAC1). OR all channels for PRBS_GOOD_x, sum all channels for PRBS_COUNT_x. Reserved. MSB shuffling control. Reserved. Reserved. Enable SPI control. Enable SPI control. FTW of the calibration accumulator. This control is paged by the MAINDAC_PAGE bits in Register 0x008. FTW of the calibration accumulator. This control is paged by the MAINDAC_PAGE bits in Register 0x008. FTW of the calibration accumulator. This control is paged by the MAINDAC_PAGE bits in Register 0x008. FTW of the calibration accumulator. This control is paged by the MAINDAC_PAGE bits in Register 0x008. Reserved. Enable clock calibration accumulator. This bit must be first set high, and then must load the calibration FTW into Register 0x1E2 to Register 0x1E5 to take effect. This control is paged by the MAINDAC_PAGE bits in Register 0x008. Disabled (does not clock the calibration frequency accumulator). Enables (turns on the clock to the calibration frequency accumulator). Reset 0x0 0x0 0x0 0x0 0x0 0x7 0x0 0x0 0x0 0x0 0x1 0x1 0x0 0x0 0x0 0x0 0x0 0x0 Access R/W R/W R R R R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R R/W Rev. B | Page 103 of 145 AD9172 Data Sheet Addr. Name 0x1E7 DATAPATH_NCO_ SYNC_CFG 0x200 MASTER_PD 0x201 PHY_PD 0x203 GENERIC_PD 0x206 CDR_RESET 0x210 CBUS_ADDR Bits Bit Name 1 DDSM_EN_CAL_ DC_INPUT 0 DDSM_EN_CAL_ FREQ_TUNE [7:2] RESERVED Settings 0 1 0 1 Description Enable dc input to calibration DDS. This control is paged by the MAINDAC_PAGE bits in Register 0x008. Mux in datapath signal to the input of the final DDS. Mux in dc to the input of the final DDS. Enable tuning of the signal to calibration frequency for DAC0 only. This control is paged by the MAINDAC_PAGE bits in Register 0x008. Disable calibration frequency tuning. Enable calibration frequency tuning. Reserved. Reset 0x0 0x0 0x0 1 ALL_NCO_SYNC_ ACK 0 START_NCO_SYNC [7:1] RESERVED 0 SERDES_MASTER_ PD [7:0] PHY_PD [7:2] RESERVED 1 PD_SYNCOUT0 0 1 0 PD_SYNCOUT1 0 1 [7:1] RESERVED 0 CDR_PHY_RESET [7:0] SERDES_CBUS_ ADDR Acknowledge signal that all the active NCOs 0x0 are loaded. This bit is the acknowledge indicator for both the START_NCO_SYNC bit (Bit 0 of this register) and the NCORST_ AFTER_ROT_EN bit (Register 0x03B, Bit 4) method of resetting the NCOs. This control is paged by the MAINDAC_PAGE bits in Register 0x008. Used to start the sync of the NCOs on a 0x0 rising edge of the SPI bit or SYSREF± signal, depending on which is chosen as the update trigger. Upon receiving a trigger, the FTWs are loaded first, and then a synchronization occurs. This control is paged by the MAINDAC_PAGE bits in Register 0x008. Reserved. 0x0 Powers down the entire JESD204B Rx 0x1 analog (all eight channels and bias). SPI override to power down the individual 0xEE PHYs. Bit 0 controls the SERDIN0± PHY. Bit 1 controls the SERDIN1± PHY. Bit 2 controls the SERDIN2± PHY. Bit 3 controls the SERDIN3± PHY. Bit 4 controls the SERDIN4± PHY. Bit 5 controls the SERDIN5± PHY. Bit 6 controls the SERDIN6± PHY. Bit 7 controls the SERDIN7± PHY. Reserved. 0x0 Powers down the SYNCOUT0± driver. 0x0 Enables the SYNCOUT0± output pins. Powers down the SYNCOUT0± output pins. Powers down the SYNCOUT1± driver. 0x1 Enables the SYNCOUT1± output pins. Powers down the SYNCOUT1± output pins. Reserved. 0x0 PHY reset control bit. Set this bit to 1 to 0x0 take the PHYs out of reset during device operation. SERDES configuration control register to 0x0 set SERDES configuration address controls. Access R/W R/W R R R/W R R/W R/W R R/W R/W R R/W R/W Rev. B | Page 104 of 145 Data Sheet AD9172 Addr. 0x212 0x213 0x216 0x240 0x234 0x241 0x242 Name Bits CBUS_WRSTROBE_ [7:0] PHY CBUS_WRSTROBE_ [7:1] OTHER 0 CBUS_WDATA [7:0] EQ_BOOST_PHY_ [7:6] 3_0 [5:4] [3:2] [1:0] CDR_BITINVERSE EQ_BOOST_PHY_ [7:6] 7_4 [5:4] [3:2] [1:0] EQ_GAIN_PHY_3_0 [7:6] [5:4] Bit Name SERDES_CBUS_ WR0 Settings RESERVED SERDES_CBUS_ WR1 SERDES_CBUS_ DATA EQ_BOOST_PHY3 10 11 EQ_BOOST_PHY2 10 11 EQ_BOOST_PHY1 10 11 EQ_BOOST_PHY0 10 11 SEL_IF_ PARDATAINV_DES_ RC_CH 0 1 EQ_BOOST_PHY7 10 11 EQ_BOOST_PHY6 10 11 EQ_BOOST_PHY5 10 11 EQ_BOOST_PHY4 10 11 EQ_GAIN_PHY3 01 11 EQ_GAIN_PHY2 01 11 Description SERDES configuration control register to commit the SERDES configuration controls written. Reserved. SERDES configuration control register to commit the SERDES configuration controls written. SERDES configuration control register to set the SERDES configuration control data. Equalizer setting for PHY 3 based on insertion loss of the system. Insertion loss 11 dB. Insertion loss > 11 dB. Equalizer setting for PHY 2 based on insertion loss of the system. Insertion loss 11 dB. Insertion loss > 11 dB. Equalizer setting for PHY 1 based on insertion loss of the system. Insertion loss 11 dB. Insertion loss > 11 dB. Equalizer setting for PHY 0 based on insertion loss of the system. Insertion loss 11 dB. Insertion loss > 11 dB. Output data inversion bit controls. Set Bit x corresponding to PHY x to invert the bit polarity. Not inverted. Inverted. Equalizer setting for PHY 7 based on insertion loss of the system. Insertion loss 11 dB. Insertion loss > 11 dB. Equalizer setting for PHY 6 based on insertion loss of the system. Insertion loss 11 dB. Insertion loss > 11 dB. Equalizer setting for PHY 5 based on insertion loss of the system. Insertion loss 11 dB. Insertion loss > 11 dB. Equalizer setting for PHY 4 based on insertion loss of the system. Insertion loss 11 dB. Insertion loss > 11 dB. Equalizer gain for PHY 3 based on insertion loss of the system. Insertion loss 11 dB. Insertion loss > 11 dB. Equalizer gain for PHY 2 based on insertion loss of the system. Insertion loss 11 dB. Insertion loss > 11 dB. Reset 0x0 0x0 0x0 0x0 0x3 0x3 0x3 0x3 0x66 0x3 0x3 0x3 0x3 0x3 0x3 Access R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev. B | Page 105 of 145 AD9172 Data Sheet Addr. Name Bits [3:2] [1:0] 0x243 EQ_GAIN_PHY_7_4 [7:6] [5:4] [3:2] [1:0] 0x244 EQ_FB_PHY_0 [7:5] [4:0] 0x245 EQ_FB_PHY_1 [7:5] [4:0] 0x246 EQ_FB_PHY_2 [7:5] [4:0] 0x247 EQ_FB_PHY_3 [7:5] [4:0] 0x248 EQ_FB_PHY_4 [7:5] [4:0] 0x249 EQ_FB_PHY_5 [7:5] [4:0] 0x24A EQ_FB_PHY_6 [7:5] [4:0] 0x24B EQ_FB_PHY_7 [7:5] [4:0] 0x250 LBT_REG_CNTRL_0 [7:0] 0x251 LBT_REG_CNTRL_1 [7:2] Bit Name EQ_GAIN_PHY1 EQ_GAIN_PHY0 EQ_GAIN_PHY7 EQ_GAIN_PHY6 EQ_GAIN_PHY5 EQ_GAIN_PHY4 RESERVED EQ_PHY_0 RESERVED EQ_PHY1 RESERVED EQ_PHY2 RESERVED EQ_PHY3 RESERVED EQ_PHY4 RESERVED EQ_PHY5 RESERVED EQ_PHY6 RESERVED EQ_PHY7 EN_LBT_DES_RC_ CH RESERVED Settings 01 11 01 11 01 11 01 11 01 11 01 11 Description Equalizer gain for PHY 1 based on insertion loss of the system. Insertion loss 11 dB. Insertion loss > 11 dB. Equalizer gain for PHY 0 based on insertion loss of the system. Insertion loss 11 dB. Insertion loss > 11 dB. Equalizer gain for PHY 7 based on insertion loss of the system. Insertion loss 11 dB. Insertion loss > 11 dB. Equalizer gain for PHY 6 based on insertion loss of the system. Insertion loss 11 dB. Insertion loss > 11 dB. Equalizer gain for PHY 5 based on insertion loss of the system. Insertion loss 11 dB. Insertion loss > 11 dB. Equalizer gain for PHY 4 based on insertion loss of the system. Insertion loss 11 dB. Insertion loss > 11 dB. Reserved. SERDES equalizer setting for PHY0. Set this control to 0x1F for optimal performance. Reserved. SERDES equalizer setting for PHY1. Set this control to 0x1F for optimal performance. Reserved. SERDES equalizer setting for PHY2. Set this control to 0x1F for optimal performance. Reserved. SERDES equalizer setting for PHY3. Set this control to 0x1F for optimal performance. Reserved. SERDES equalizer setting for PHY4. Set this control to 0x1F for optimal performance. Reserved. SERDES equalizer setting for PHY5. Set this control to 0x1F for optimal performance. Reserved. SERDES equalizer setting for PHY6. Set this control to 0x1F for optimal performance. Reserved. SERDES equalizer setting for PHY7. Set this control to 0x1F for optimal performance. Enable loopback test for desired physical lanes per PHY, with Bit x corresponding to PHY x. Reserved. Reset 0x3 0x3 0x3 0x3 0x3 0x3 0x0 0x19 0x0 0x19 0x0 0x19 0x0 0x19 0x0 0x19 0x0 0x19 0x0 0x19 0x0 0x19 0x0 0x0 Access R/W R/W R/W R/W R/W R/W R R/W R R/W R R/W R R/W R R/W R R/W R R/W R R/W R/W R Rev. B | Page 106 of 145 Data Sheet AD9172 Addr. Name Bits Bit Name Settings Description Reset 1 EN_LBT_ HALFRATE_DES_RC Enables half rate mode for the loopback 0x1 test. If this bit is set to 1, the output data rate = 2× the input clock frequency. If this bit is set to 0, the output data rate = the input clock frequency. 0 INIT_LBT_SYNC_ DES_RC Initiate the loopback test by toggling this 0x0 bit from 0 to 1, then back to 0. 0x253 SYNCOUT0_CTRL [7:1] RESERVED Reserved. 0x0 0 SEL_SYNCOUT0_ MODE 0 This control determines the output driver 0x0 mode for the SYNCOUT0± pin operation. Both SYNCOUT0± and SYNCOUT1± must be set to the same mode of operation. SYNCOUT0± is set to CMOS output. 1 SYNCOUT0± is set to LVDS output. 0x254 SYNCOUT1_CTRL [7:1] RESERVED Reserved. 0x0 0 SEL_SYNCOUT1_ MODE 0 This control determines the output driver 0x0 mode for the SYNCOUT1± pin operation. Both SYNCOUT0± and SYNCOUT1± must be set to the same mode of operation. SYNCOUT1± is set to CMOS output. 1 SYNCOUT1± is set to LVDS output. 0x280 PLL_ENABLE_CTRL [7:3] RESERVED Reserved. 0x0 2 LOLSTICKYCLEAR_ Clears out loss of lock bit. 0x0 LCPLL_RC 1 LDSYNTH_LCPLL_ RC Pulse high to start VCO calibration (without 0x0 restarting the regulator or remeasuring the temperature). 0 SERDES_PLL_ STARTUP SERDES circuitry blocks are powered off 0x1 when this bit is set to 0. Set this bit to 1 at the end of the SERDES configuration writes. When this bit is set to 1, it powers up the SERDES PLL blocks and starts the LDO and calibration routine to lock the PLL automatically to the appropriate lane rate based on the JESD204B mode and interpolation options programmed in the device. The SERDES_PLL_LOCK bit (Register 0x281, Bit 0) reads 1 when the PLL achieves lock. 0x281 PLL_STATUS [7:1] RESERVED Reserved. 0x0 0 SERDES_PLL_LOCK PLL is locked when this bit is high. 0x0 0x300 GENERAL_JRX_ CTRL_0 [7:4] RESERVED 3 LINK_MODE Reserved. 0x0 Reads back 0 when in single-link mode and 0x0 1 when in dual-link mode. 2 LINK_PAGE Link paging. This bit selects which link 0x0 register map is used. This paging affects Register 0x400 to Register 0x4BB. 0 Page QBD0 for Link 0. 1 Page QBD1 for Link 1. [1:0] LINK_EN These bits bring up the JESD204B digital Rx 0x0 when all link parameters are programmed and all clocks are ready. Bit 0 applies to Link 0, whereas Bit 1 applies to Link 1. Link 1 is only available in dual-link mode. Access R/W R/W R/W R/W R/W R/W R R/W R/W R/W R R R R/W R/W R/W Rev. B | Page 107 of 145 AD9172 Addr. 0x302 Name DYN_LINK_ LATENCY_0 0x303 DYN_LINK_ LATENCY_1 0x304 LMFC_DELAY_0 0x305 LMFC_DELAY_1 0x306 LMFC_VAR_0 0x307 LMFC_VAR_1 0x308 XBAR_LN_0_1 0x309 XBAR_LN_2_3 Data Sheet Bits Bit Name Settings Description Reset [7:6] RESERVED Reserved. 0x0 [5:0] DYN_LINK_ LATENCY_0 Dynamic link latency, Link 0. Latency 0x0 between the LMFC Rx for Link 0 and the last arriving LMFC boundary in units of PCLK cycles. [7:6] RESERVED Reserved. 0x0 [5:0] DYN_LINK_ LATENCY_1 Dynamic link latency, Link 1. Latency 0x0 between the LMFC Rx for Link 1 and the last arriving LMFC boundary in units of PCLK cycles. [7:6] RESERVED Reserved. 0x0 [5:0] LMFC_DELAY_0 LMFC delay, Link 0. Delay from the LMFC to 0x0 the LMFC Rx for Link 0 in units of PCLK cycles. [7:6] RESERVED Reserved. 0x0 [5:0] LMFC_DELAY_1 LMFC delay, Link 1. Delay from the LMFC to 0x0 the LMFC Rx for Link 1 in units of PCLK cycles. [7:6] RESERVED Reserved. 0x0 [5:0] LMFC_VAR_0 Variable delay buffer, Link 0. These bits set when data is read from a buffer to be consistent across links and power cycles (in units of PCLK cycles). The maximum value is 0xC. 0x3F [7:6] RESERVED Reserved. 0x0 [5:0] LMFC_VAR_1 Variable delay buffer, Link 1. These bits set when data is read from a buffer to be consistent across links and power cycles (in units of PCLK cycles). The maximum value is 0xC. 0x3F [7:6] RESERVED Reserved. 0x0 [5:3] LOGICAL_LANE1_ SRC Logical Lane 1 source. These bits select a 0x1 physical lane to be mapped onto Logical Lane 1. 000 Data is from SERDIN0±. 001 Data is from SERDIN1±. 010 Data is from SERDIN2±. 011 Data is from SERDIN3±. 100 Data is from SERDIN4±. 101 Data is from SERDIN5±. 110 Data is from SERDIN6±. 111 Data is from SERDIN7±. [2:0] LOGICAL_LANE0_ SRC Logical Lane 0 source. These bits select a 0x0 physical lane to be mapped onto Logical Lane 0. 000 Data is from SERDIN0±. 001 Data is from SERDIN1±. 010 Data is from SERDIN2±. 011 Data is from SERDIN3±. 100 Data is from SERDIN4±. 101 Data is from SERDIN5±. 110 Data is from SERDIN6±. 111 Data is from SERDIN7±. [7:6] RESERVED Reserved. 0x0 [5:3] LOGICAL_LANE3_ SRC Logical Lane 3 source. These bits select a 0x3 physical lane to be mapped onto Logical Lane 3. 000 Data is from SERDIN0±. 001 Data is from SERDIN1±. 010 Data is from SERDIN2±. Rev. B | Page 108 of 145 Access R R R R R R/W R R/W R R/W R R/W R R/W R/W R R/W Data Sheet Addr. Name 0x30A XBAR_LN_4_5 0x30B XBAR_LN_6_7 AD9172 Bits Bit Name Settings Description 011 Data is from SERDIN3±. 100 Data is from SERDIN4±. 101 Data is from SERDIN5±. 110 Data is from SERDIN6±. 111 Data is from SERDIN7±. [2:0] LOGICAL_LANE2_ SRC Logical Lane 2 source. These bits select a physical lane to be mapped onto Logical Lane 2. 000 Data is from SERDIN0±. 001 Data is from SERDIN1±. 010 Data is from SERDIN2±. 011 Data is from SERDIN3±. 100 Data is from SERDIN4±. 101 Data is from SERDIN5±. 110 Data is from SERDIN6±. 111 Data is from SERDIN7±. [7:6] RESERVED Reserved. [5:3] LOGICAL_LANE5_ SRC Logical Lane 5 source. These bits select a physical lane to be mapped onto Logical Lane 5. 000 Data is from SERDIN0±. 001 Data is from SERDIN1±. 010 Data is from SERDIN2±. 011 Data is from SERDIN3±. 100 Data is from SERDIN4±. 101 Data is from SERDIN5±. 110 Data is from SERDIN6±. 111 Data is from SERDIN7±. [2:0] LOGICAL_LANE4_ SRC Logical Lane 4 source. These bits select a physical lane to be mapped onto Logical Lane 4. 000 Data is from SERDIN0±. 001 Data is from SERDIN1±. 010 Data is from SERDIN2±. 011 Data is from SERDIN3±. 100 Data is from SERDIN4±. 101 Data is from SERDIN5±. 110 Data is from SERDIN6±. 111 Data is from SERDIN7±. [7:6] RESERVED Reserved. [5:3] LOGICAL_LANE7_ SRC Logical Lane 7 source. These bits select a physical lane to be mapped onto Logical Lane 7. 000 Data is from SERDIN0±. 001 Data is from SERDIN1±. 010 Data is from SERDIN2±. 011 Data is from SERDIN3±. 100 Data is from SERDIN4±. 101 Data is from SERDIN5±. 110 Data is from SERDIN6±. 111 Data is from SERDIN7±. Reset 0x2 0x0 0x5 0x4 0x0 0x7 Access R/W R R/W R/W R R/W Rev. B | Page 109 of 145 AD9172 Data Sheet Addr. Name Bits [2:0] 0x30C FIFO_STATUS_REG_0 [7:0] 0x30D FIFO_STATUS_REG_1 [7:0] 0x311 SYNCOUT_GEN_0 [7:4] 3 2 1 0 0x312 SYNCOUT_GEN_1 [7:4] [3:0] 0x315 PHY_PRBS_TEST_EN [7:0] 0x316 PHY_PRBS_TEST_ 7 CTRL [6:4] Bit Name LOGICAL_LANE6_ SRC LANE_FIFO_FULL LANE_FIFO_EMPTY RESERVED EOMF_MASK_1 EOMF_MASK_0 EOF_MASK_1 EOF_MASK_0 SYNC_ERR_DUR RESERVED PHY_TEST_EN RESERVED PHY_SRC_ERR_CNT Settings 000 001 010 011 100 101 110 111 0 1 0 1 0 1 0 1 0 1 000 001 010 011 100 Description Logical Lane 6 source. These bits select a physical lane to be mapped onto Logical Lane 6. Data is from SERDIN0±. Data is from SERDIN1±. Data is from SERDIN2±. Data is from SERDIN3±. Data is from SERDIN4±. Data is from SERDIN5±. Data is from SERDIN6±. Data is from SERDIN7±. Bit x corresponds to FIFO full flag for data from SERDINx±. Bit x corresponds to FIFO empty flag for data from SERDINx±. Reserved. Mask end of multiframe (EOMF) from QBD1. Assert SYNCOUT1± based on the loss of the multiframe synchronization. Do not assert SYNCOUT1± on loss of multiframe. Assert SYNCOUT1± on loss of multiframe. Mask EOMF from QBD0. Assert SYNCOUT0± based on the loss of the multiframe synchronization. Do not assert SYNCOUT0± on loss of multiframe. Assert SYNCOUT0± on loss of multiframe. Mask EOF from QBD1. Assert SYNCOUT1± based on loss of frame synchronization. Do not assert SYNCOUT1± on loss of frame. Assert SYNCOUT1± on loss of frame. Mask EOF from QBD0. Assert SYNCOUT0± based on loss of frame synchronization. Do not assert SYNCOUT0± on loss of frame. Assert SYNCOUT0± on loss of frame. Duration of SYNCOUTx± low for the purposes of the synchronization error report. Duration = (0.5 + code) PCLK cycles. To most closely match the specified value, set these bits as close as possible to f/2 PCLK cycles. These bits are shared between SYNCOUT0± and SYNCOUT1±. Reserved. Enable PHY BER by ungating the clocks. PHY test disable. PHY test enable. Reserved. Report Lane 0 error count. Report Lane 1 error count. Report Lane 2 error count. Report Lane 3 error count. Report Lane 4 error count. Reset 0x6 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Rev. B | Page 110 of 145 Access R/W R R R R/W R/W R/W R/W R/W R/W R/W R R/W Data Sheet AD9172 Addr. Name Bits [3:2] 1 0 0x317 0x318 0x319 PHY_PRBS_TEST_ [7:0] THRESHOLD_ LOBITS PHY_PRBS_TEST_ [7:0] THRESHOLD_ MIDBITS PHY_PRBS_TEST_ [7:0] THRESHOLD_HIBITS 0x31A PHY_PRBS_TEST_ [7:0] ERRCNT_LOBITS 0x31B PHY_PRBS_TEST_ [7:0] ERRCNT_MIDBITS 0x31C PHY_PRBS_TEST_ [7:0] ERRCNT_HIBITS 0x31D PHY_PRBS_TEST_ [7:0] STATUS 0x31E PHY_DATA_ [7:2] SNAPSHOT_CTRL 1 0 0x31F 0x320 0x321 0x322 0x323 0x32C PHY_SNAPSHOT_ [7:0] DATA_BYTE0 PHY_SNAPSHOT_ [7:0] DATA_BYTE1 PHY_SNAPSHOT_ [7:0] DATA_BYTE2 PHY_SNAPSHOT_ [7:0] DATA_BYTE3 PHY_SNAPSHOT_ [7:0] DATA_BYTE4 SHORT_TPL_TEST_0 [7:4] Bit Name PHY_PRBS_PAT_SEL PHY_TEST_START PHY_TEST_RESET Settings 101 110 111 00 01 10 11 0 1 0 1 PHY_PRBS_ THRESHOLD_ LOBITS PHY_PRBS_ THRESHOLD_ MIDBITS PHY_PRBS_ THRESHOLD_ HIBITS PHY_PRBS_ERR_ CNT_LOBITS PHY_PRBS_ERR_ CNT_MIDBITS PHY_PRBS_ERR_ CNT_HIBITS PHY_PRBS_PASS RESERVED PHY_GRAB_MODE 0 1 PHY_GRAB_DATA PHY_SNAPSHOT_ DATA_BYTE0 PHY_SNAPSHOT_ DATA_BYTE1 PHY_SNAPSHOT_ DATA_BYTE2 PHY_SNAPSHOT_ DATA_BYTE3 PHY_SNAPSHOT_ DATA_BYTE4 SHORT_TPL_SP_ SEL 0000 0001 0010 0011 Description Report Lane 5 error count. Report Lane 6 error count. Report Lane 7 error count. Select PRBS pattern for PHY BER test. PRBS7. PRBS15. PRBS31. Not used. Starts and stops the PHY PRBS test. Test not started. Test started. Resets PHY PRBS test state machine and error counters. Not reset. Reset. Bits[7:0] of the 24-bit threshold value to set the error flag for the PHY PRBS test. Reset 0x0 0x0 0x0 0x0 Bits[15:8] of the 24-bit threshold value to 0x0 set the error flag for the PHY PRBS test. Bits[23:16] of the 24-bit threshold value to 0x0 set the error flag for the PHY PRBS test. Bits[7:0] of the 24-bit reported PHY BER 0x0 error count from the selected lane. Bits[15:8] of the 24-bit reported PHY BER 0x0 error count from the selected lane. Bits[23:16] of the 24-bit reported PHY BER 0x0 error count from the selected lane. Reports PHY BER pass/fail for each lane. 0xFF Bit x is high when Lane x passes. Reserved. 0x0 This bit determines whether to use the 0x0 trigger to grab data. Grab data when PHY_GRAB_DATA is set. Grab data upon bit error. Transitioning this bit from 0 to 1 causes the 0x0 logic to store current receive data from one lane. Current data received. Represents 0x0 PHY_SNAPSHOT_DATA[7:0]. Current data received. Represents 0x0 PHY_SNAPSHOT_DATA[15:8]. Current data received. Represents 0x0 PHY_SNAPSHOT_DATA[23:16]. Current data received. Represents 0x0 PHY_SNAPSHOT_DATA[31:24]. Current data received. Represents 0x0 PHY_SNAPSHOT_DATA[39:32]. Short transport layer sample select. Selects 0x0 which sample to check from a specific DAC. Sample 0. Sample 1. Sample 2. Sample 3. Rev. B | Page 111 of 145 Access R/W R/W R/W R/W R/W R/W R R R R R R/W R/W R R R R R R/W AD9172 Data Sheet Addr. Name Bits [3:2] 1 0 0x32D SHORT_TPL_TEST_1 [7:0] 0x32E SHORT_TPL_TEST_2 [7:0] 0x32F SHORT_TPL_TEST_3 7 6 [5:1] 0 0x334 JESD_BIT_INVERSE_ [7:0] CTRL Bit Name SHORT_TPL_M_SEL SHORT_TPL_TEST_ RESET SHORT_TPL_TEST_ EN SHORT_TPL_REF_ SP_LSB SHORT_TPL_REF_ SP_MSB RESERVED SHORT_TPL_IQ_ SAMPLE_SEL RESERVED SHORT_TPL_FAIL JESD_BIT_INVERSE Settings 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 00 01 10 0 1 0 1 0 1 0 1 Description Sample 4. Sample 5. Sample 6. Sample 7. Sample 8. Sample 9. Sample 10. Sample 11. Sample 12. Sample 13. Sample 14. Sample 15. Short transport layer test channel select. Select which channel of the DAC to check. Channel 0. Channel 1. Channel 2. Short transport layer test reset. Resets the result of short transport layer test. Not reset. Reset. Short transport layer test enable. Enable short transport layer test. Disable. Enable. Short transport layer reference sample, LSB. This bit field is the lower eight bits of the expected DAC sample during the short transport layer test and is used to compare with the received sample at the JESD204B Rx output. Short transport layer test reference sample, MSB. This bit field is the upper eight bits of the expected DAC sample during the short transport layer test and is used to compare with the received sample at the JESD204B Rx output. Reserved. Selects I or Q of the DAC to check the testing of the short transport layer. Select I data to test. Select Q data to test. Reserved. Short transport layer test fail. This bit shows if the selected DAC sample matches the expected sample for the short transport layer test. If they match, the test passes; otherwise, the test fails. Test pass. Test fail. Logical lane invert. Each bit of this control inverses the JESD204B deserialized data from one specific JESD204B Rx PHY. Set Bit x high to invert the JESD204B deserialized data on Logical Lane x. Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R/W R/W R/W R/W R/W R/W R/W R R/W Rev. B | Page 112 of 145 Data Sheet Addr. Name 0x400 DID_REG 0x401 BID_REG 0x402 LID0_REG 0x403 SCR_L_REG 0x404 F_REG 0x405 K_REG 0x406 M_REG 0x407 CS_N_REG 0x408 NP_REG AD9172 Bits Bit Name [7:0] DID_RD [7:0] BID_RD 7 RESERVED 6 ADJDIR_RD 5 PHADJ_RD [4:0] LL_LID0 7 SCR_RD [6:5] RESERVED [4:0] L_RD-1 [7:0] F_RD-1 [7:5] RESERVED [4:0] K_RD-1 [7:0] M_RD-1 [7:6] CS_RD 5 RESERVED [4:0] N_RD-1 [7:5] SUBCLASSV_RD Settings 0 1 00000 00001 00010 00011 0 1 10 11 00000 11111 Description Received ILAS configuration on Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Received ILAS configuration on Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Reserved. Received ILAS configuration on Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Received ILAS configuration on Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Received ILAS LID configuration on Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Received ILAS configuration on Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Scrambling is disabled. Scrambling is enabled. Reserved. Received ILAS configuration on Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. 1 lane per converter device. 2 lanes per converter device. 3 lanes per converter device. 4 lanes per converter device. Received ILAS configuration on Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. 1 octet per frame. 2 octets per frame. 3 octets per frame. 4 octets per frame. Reserved. Received ILAS configuration on Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Default value. 32 frames per multiframe. Received ILAS configuration on Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Received ILAS configuration on Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Reserved. Received ILAS configuration on Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Received ILAS configuration on Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R R R R R R R R R R R R R R R R R Rev. B | Page 113 of 145 AD9172 Addr. Name 0x409 S_REG Bits Bit Name [4:0] NP_RD-1 [7:5] JESDV_RD-1 0x40A HD_CF_REG [4:0] S_RD-1 7 HD_RD [6:5] RESERVED [4:0] CF_RD 0x40B RES1_REG [7:0] RES1_RD 0x40C RES2_REG [7:0] RES2_RD 0x40D CHECKSUM0_REG [7:0] LL_FCHK0 0x40E COMPSUM0_REG [7:0] LL_FCMP0 0x412 LID1_REG [7:5] RESERVED [4:0] LL_LID1 0x415 CHECKSUM1_REG [7:0] LL_FCHK1 0x416 COMPSUM1_REG [7:0] LL_FCMP1 0x41A LID2_REG [7:5] RESERVED [4:0] LL_LID2 0x41D CHECKSUM2_REG [7:0] LL_FCHK2 0x41E COMPSUM2_REG [7:0] LL_FCMP2 0x422 LID3_REG [7:5] RESERVED [4:0] LL_LID3 Data Sheet Settings 000 001 0 1 Description Received ILAS configuration on Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Received ILAS configuration on Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. JESD204A. JESD204B. Received ILAS configuration on Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Received ILAS configuration on Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Low density mode. High density mode. Reserved. Received ILAS configuration on Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Received ILAS configuration on Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Received ILAS configuration on Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Received checksum during ILAS on Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Computed checksum on Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Reserved. Received ILAS LID configuration on Lane 1. This control is paged by the LINK_PAGE control in Register 0x300. Received checksum during ILAS on Lane 1. This control is paged by the LINK_PAGE control in Register 0x300. Computed checksum on Lane 1. This control is paged by the LINK_PAGE control in Register 0x300. Reserved. Received ILAS LID configuration on Lane 2. This control is paged by the LINK_PAGE control in Register 0x300. Received checksum during ILAS on Lane 2. This control is paged by the LINK_PAGE control in Register 0x300. Computed checksum on Lane 2. This control is paged by the LINK_PAGE control in Register 0x300. Reserved. Received ILAS LID configuration on Lane 3. This control is paged by the LINK_PAGE control in Register 0x300. Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R R R R R R R R R R R R R R R R R R R R Rev. B | Page 114 of 145 Data Sheet Addr. Name 0x425 CHECKSUM3_REG Bits Bit Name [7:0] LL_FCHK3 0x426 COMPSUM3_REG [7:0] LL_FCMP3 0x42A LID4_REG [7:5] RESERVED [4:0] LL_LID4 0x42D CHECKSUM4_REG [7:0] LL_FCHK4 0x42E COMPSUM4_REG [7:0] LL_FCMP4 0x432 LID5_REG [7:5] RESERVED [4:0] LL_LID5 0x435 CHECKSUM5_REG [7:0] LL_FCHK5 0x436 COMPSUM5_REG [7:0] LL_FCMP5 0x43A LID6_REG [7:5] RESERVED [4:0] LL_LID6 0x43D CHECKSUM6_REG [7:0] LL_FCHK6 0x43E COMPSUM6_REG [7:0] LL_FCMP6 0x442 LID7_REG [7:5] RESERVED [4:0] LL_LID7 0x445 CHECKSUM7_REG [7:0] LL_FCHK7 0x446 COMPSUM7_REG [7:0] LL_FCMP7 0x450 ILS_DID [7:0] DID 0x451 ILS_BID [7:0] BID AD9172 Settings Description Received checksum during ILAS on Lane 3. This control is paged by the LINK_PAGE control in Register 0x300. Computed checksum on Lane 3. This control is paged by the LINK_PAGE control in Register 0x300. Reserved. Received ILAS LID configuration on Lane 4. This control is paged by the LINK_PAGE control in Register 0x300. Received checksum during ILAS on Lane 4. This control is paged by the LINK_PAGE control in Register 0x300. Computed checksum on Lane 4. This control is paged by the LINK_PAGE control in Register 0x300. Reserved. Received ILAS LID configuration on Lane 5. This control is paged by the LINK_PAGE control in Register 0x300. Received checksum during ILAS on Lane 5. This control is paged by the LINK_PAGE control in Register 0x300. Computed checksum on Lane 5. This control is paged by the LINK_PAGE control in Register 0x300. Reserved. Received ILAS LID configuration on Lane 6. This control is paged by the LINK_PAGE control in Register 0x300. Received checksum during ILAS on Lane 6. This control is paged by the LINK_PAGE control in Register 0x300. Computed checksum on Lane 6. This control is paged by the LINK_PAGE control in Register 0x300. Reserved. Received ILAS LID configuration on Lane 7. This control is paged by the LINK_PAGE control in Register 0x300. Received checksum during ILAS on Lane 7. This control is paged by the LINK_PAGE control in Register 0x300. Computed checksum on Lane 7. This control is paged by the LINK_PAGE control in Register 0x300. Device (link) identification number. This control is paged by the LINK_PAGE control in Register 0x300. Bank ID, extension to DID. This control is paged by the LINK_PAGE control in Register 0x300. This signal must only be programmed while the QBD is held in soft reset (Register 0x475, Bit 3), and must not be changed during normal operation. Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R R R R R R R R R R R R R R R R R R R/W R/W Rev. B | Page 115 of 145 AD9172 Addr. Name 0x452 ILS_LID0 0x453 ILS_SCR_L 0x454 ILS_F 0x455 ILS_K 0x456 ILS_M 0x457 ILS_CS_N 0x458 ILS_NP 0x459 ILS_S Bits Bit Name 7 RESERVED 6 ADJDIR 5 PHADJ [4:0] LID0 7 SCR [6:5] RESERVED [4:0] L-1 [7:0] F-1 [7:5] RESERVED [4:0] K-1 [7:0] M-1 [7:6] CS 5 RESERVED [4:0] N-1 [7:5] SUBCLASSV [4:0] NP-1 [7:5] JESDV [4:0] S-1 Data Sheet Settings 0 1 11111 000 001 000 001 Description Reserved. Direction to adjust the DAC LMFC. Link information is received on Link Lane 0 as specified in Section 8.3 of JESD204B. Only Link 0 is supported. This control is paged by the LINK_PAGE control in Register 0x300. Phase adjustment request to the DAC. Only Link 0 is supported. This control is paged by the LINK_PAGE control in Register 0x300. Lane identification number (within link). This control is paged by the LINK_PAGE control in Register 0x300. This signal must only be programmed while the QBD is held in soft reset (Register 0x475, Bit 3), and must not be changed during normal operation. Scramble enabled for the link. This control is paged by the LINK_PAGE control in Register 0x300. Descrambling is disabled. Descrambling is enabled. Reserved. Number of lanes per converter (minus 1). This control is paged by the LINK_PAGE control in Register 0x300. Number of octets per frame per lane (minus 1). This control is paged by the LINK_PAGE control in Register 0x300. Reserved. Number of frames per multiframe (minus 1). This control is paged by the LINK_PAGE control in Register 0x300. 32 frames per multiframe. Number of subchannels per link (minus 1). This control is paged by the LINK_PAGE control in Register 0x300. Number of control bits per sample. Only Link 0 is supported. This control is paged by the LINK_PAGE control in Register 0x300. Reserved. Converter resolution (minus 1). This control is paged by the LINK_PAGE control in Register 0x300. Device subclass version. This control is paged by the LINK_PAGE control in Register 0x300. Subclass 0. Subclass 1. Total number of bits per sample (minus 1). This control is paged by the LINK_PAGE control in Register 0x300. JESD204 version. This control is paged by the LINK_PAGE control in Register 0x300. JESD204A. JESD204B. Number of samples per converter per frame cycle (minus 1). This control is paged by the LINK_PAGE control in Register 0x300. Reset 0x0 0x0 0x0 0x0 0x1 0x0 0x7 0x0 0x0 0x1F 0x1 0x0 0x0 0xF 0x0 0xF 0x0 0x1 Access R R/W R/W R/W R/W R R/W R/W R R/W R/W R R R/W R/W R/W R/W R/W Rev. B | Page 116 of 145 Data Sheet Addr. Name 0x45A ILS_HD_CF Bits Bit Name 7 HD [6:5] RESERVED [4:0] CF 0x45B ILS_RES1 0x45C ILS_RES2 0x45D ILS_CHECKSUM [7:0] RES1 [7:0] RES2 [7:0] FCHK0 0x46C LANE_DESKEW 7 ILD7 6 ILD6 5 ILD5 4 ILD4 3 ILD3 2 ILD2 1 ILD1 AD9172 Settings 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Description High density format, always set to 1. This control is paged by the LINK_PAGE control in Register 0x300. Low density mode. High density mode. Reserved. Number of control bits per sample. Only Link 0 is supported. This control is paged by the LINK_PAGE control in Register 0x300. Reserved field 1. This control is paged by the LINK_PAGE control in Register 0x300. Reserved field 2. This control is paged by the LINK_PAGE control in Register 0x300. Calculated link configuration checksum. This control is paged by the LINK_PAGE control in Register 0x300. This signal must only be programmed while the QBD is held in soft reset (Register 0x475, Bit 3), and must not be changed during normal operation. Interlane deskew status for Lane 7. This control is paged by the LINK_PAGE control in Register 0x300. Deskew failed. Deskew achieved. Interlane deskew status for Lane 6. This control is paged by the LINK_PAGE control in Register 0x300. Deskew failed. Deskew achieved. Interlane deskew status for Lane 5. This control is paged by the LINK_PAGE control in Register 0x300. Deskew failed. Deskew achieved. Interlane deskew status for Lane 4. This control is paged by the LINK_PAGE control in Register 0x300. Deskew failed. Deskew achieved. Interlane deskew status for Lane 3. This control is paged by the LINK_PAGE control in Register 0x300. Deskew failed. Deskew achieved. Interlane deskew status for Lane 2. This control is paged by the LINK_PAGE control in Register 0x300. Deskew failed. Deskew achieved. Interlane deskew status for Lane 1. This control is paged by the LINK_PAGE control in Register 0x300. Deskew failed. Deskew achieved. Reset 0x1 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R R R R/W R/W R/W R R R R R R R Rev. B | Page 117 of 145 AD9172 Addr. Name Bits Bit Name 0 ILD0 0x46D BAD_DISPARITY 7 BDE7 6 BDE6 5 BDE5 4 BDE4 3 BDE3 2 BDE2 1 BDE1 0 BDE0 0x46E NOT_IN_TABLE 7 NIT7 6 NIT6 Data Sheet Settings 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Description Interlane deskew status for Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Deskew failed. Deskew achieved. Bad disparity errors status for Lane 7. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ETH[7:0] value. Bad disparity errors status for Lane 6. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ETH[7:0] value. Bad disparity errors status for Lane 5. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ETH[7:0] value. Bad disparity errors status for Lane 4. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ETH[7:0] value. Bad disparity errors status for Lane 3. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ETH[7:0] value. Bad disparity errors status for Lane 2. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ETH[7:0] value. Bad disparity errors status for Lane 1. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ETH[7:0] value. Bad disparity errors status for Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ETH[7:0] value. Not in table errors status for Lane 7. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ETH[7:0] value. Not in table errors status for Lane 6. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ETH[7:0] value. Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R R R R R R R R R R R Rev. B | Page 118 of 145 Data Sheet Addr. Name Bits Bit Name 5 NIT5 4 NIT4 3 NIT3 2 NIT2 1 NIT1 0 NIT0 0x46F UNEXPECTED_ KCHAR 7 UEK7 6 UEK6 5 UEK5 4 UEK4 3 UEK3 AD9172 Settings 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Description Not in table errors status for Lane 5. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ETH[7:0] value. Not in table errors status for Lane 4. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ETH[7:0] value. Not in table errors status for Lane 3. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ETH[7:0] value. Not in table errors status for Lane 2. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ETH[7:0] value. Not in table errors status for Lane 1. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ETH[7:0] value. Not in table errors status for Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ETH[7:0] value. Unexpected K character errors status, Lane 7. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ETH[7:0] value. Unexpected K character errors status, Lane 6. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ETH[7:0] value. Unexpected K character errors status, Lane 5. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ETH[7:0] value. Unexpected K character errors status, Lane 4. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ETH[7:0] value. Unexpected K character errors status, Lane 3. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ETH[7:0] value. Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R R R R R R R R R R R Rev. B | Page 119 of 145 AD9172 Addr. Name Bits Bit Name 2 UEK2 1 UEK1 0 UEK0 0x470 CODE_GRP_SYNC 7 CGS7 6 CGS6 5 CGS5 4 CGS4 3 CGS3 2 CGS2 1 CGS1 0 CGS0 Data Sheet Settings 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Description Unexpected K character errors status, Lane 2. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ETH[7:0] value. Unexpected K character errors status, Lane 1. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ETH[7:0] value. Unexpected K character errors status, Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ETH[7:0] value. Code group synchronization status for Lane 7. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Code group synchronization status for Lane 6. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Code group synchronization status for Lane 5. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Code group synchronization status for Lane 4. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Code group synchronization status for Lane 3. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Code group synchronization status for Lane 2. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Code group synchronization status for Lane 1. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Code group synchronization status for Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R R R R R R R R R R R Rev. B | Page 120 of 145 Data Sheet Addr. Name 0x471 FRAME_SYNC Bits Bit Name 7 FS7 6 FS6 5 FS5 4 FS4 3 FS3 2 FS2 1 FS1 0 FS0 0x472 GOOD_CHECKSUM 7 CKS7 6 CKS6 5 CKS5 AD9172 Settings 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Description Frame synchronization status for Lane 7. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Frame synchronization status for Lane 6. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Frame synchronization status for Lane 5. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Frame synchronization status for Lane 4. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Frame synchronization status for Lane 3. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Frame synchronization status for Lane 2. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Frame synchronization status for Lane 1. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Frame synchronization status for Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Computed checksum status for Lane 7. This control is paged by the LINK_PAGE control in Register 0x300. Checksum is incorrect. Checksum is correct. Computed checksum status for Lane 6. This control is paged by the LINK_PAGE control in Register 0x300. Checksum is incorrect. Checksum is correct. Computed checksum status for Lane 5. This control is paged by the LINK_PAGE control in Register 0x300. Checksum is incorrect. Checksum is correct. Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R R R R R R R R R R R Rev. B | Page 121 of 145 AD9172 Addr. Name Bits Bit Name 4 CKS4 3 CKS3 2 CKS2 1 CKS1 0 CKS0 0x473 INIT_LANE_SYNC 7 ILS7 6 ILS6 5 ILS5 4 ILS4 3 ILS3 2 ILS2 Data Sheet Settings 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Description Computed checksum status for Lane 4. This control is paged by the LINK_PAGE control in Register 0x300. Checksum is incorrect. Checksum is correct. Computed checksum status for Lane 3. This control is paged by the LINK_PAGE control in Register 0x300. Checksum is incorrect. Checksum is correct. Computed checksum status for Lane 2. This control is paged by the LINK_PAGE control in Register 0x300. Checksum is incorrect. Checksum is correct. Computed checksum status for Lane 1. This control is paged by the LINK_PAGE control in Register 0x300. Checksum is incorrect. Checksum is correct. Computed checksum status for Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Checksum is incorrect. Checksum is correct. Initial lane synchronization status for Lane 7. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Initial lane synchronization status for Lane 6. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Initial lane synchronization status for Lane 5. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Initial lane synchronization status for Lane 4. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Initial lane synchronization status for Lane 3. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Initial lane synchronization status for Lane 2. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R R R R R R R R R R R Rev. B | Page 122 of 145 Data Sheet Addr. Name 0x475 CTRLREG0 0x476 CTRLREG1 AD9172 Bits Bit Name 1 ILS1 0 ILS0 [7:4] RESERVED 3 SOFTRST 2 FORCESYNCREQ 1 RESERVED 0 REPL_FRM_ENA [7:5] RESERVED 4 QUAL_RDERR [3:1] RESERVED 0 FCHK_N Settings 0 1 0 1 0 1 0 1 Description Initial lane synchronization status for Lane 1. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Initial lane synchronization status for Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Reserved. QBD soft reset. Active high synchronous reset. Resets all hardware to power-on state. This control is paged by the LINK_PAGE control in Register 0x300. Command from application to assert a synchronization request. Active high. This control is paged by the LINK_PAGE control in Register 0x300. Reserved. When this level input is set, it enables the replacement of frames received in error. This control is paged by the LINK_PAGE control in Register 0x300. This signal must only be programmed while the QBD is held in soft reset (Register 0x475, Bit 3), and must not be changed during normal operation. Reserved. Error reporting behavior for concurrent not in table (NIT) and running disparity (RD) errors. This control is paged by the LINK_PAGE control in Register 0x300. Set this bit to 1. This signal must only be programmed while the QBD is held in soft reset (Register 0x475, Bit 3), and must not be changed during normal operation. NIT has no effect on RD error. NIT error masks concurrent with RD error. Reserved. Checksum calculation method. This control is paged by the LINK_PAGE control in Register 0x300. This signal must only be programmed while the QBD is held in soft reset (Register 0x475, Bit 3), and must not be changed during normal operation. Checksum is calculated by summing the individual fields in the link configuration table as defined in Section 8.3, Table 20 of the JESD204B standard. Checksum is calculated by summing the registers containing the packed link configuration fields (sum of Register 0x450 to Register 0x45A, modulo 256). Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x1 0x0 0x1 0x0 0x0 Access R R R/W R/W R/W R R/W R R/W R/W R/W Rev. B | Page 123 of 145 AD9172 Addr. Name 0x477 CTRLREG2 0x478 KVAL 0x47C ERRORTHRES Bits Bit Name 7 ILS_MODE 6 RESERVED 5 REPDATATEST 4 QUETESTERR 3 AR_ECNTR [2:0] RESERVED [7:0] KSYNC [7:0] ETH Data Sheet Settings 0 1 0 1 Description Data link layer test mode is enabled when this bit is set to 1. CGS pattern is followed by a perpetual ILAS sequence. This control is paged by the LINK_PAGE control in Register 0x300. This signal must only be programmed while the QBD is held in soft reset (Register 0x475, Bit 3), and must not be changed during normal operation. Normal mode. CGS pattern is followed by a perpetual ILAS sequence. Reserved. Repetitive data test enable using the JTSPAT pattern. To enable the test, Bit 7 of this register must = 0. This control is paged by the LINK_PAGE control in Register 0x300. This signal must only be programmed while the QBD is held in soft reset (Register 0x475, Bit 3), and must not be changed during normal operation. Queue test error mode. This control is paged by the LINK_PAGE control in Register 0x300. This signal must only be programmed while the QBD is held in soft reset (Register 0x475, Bit 3), and must not be changed during normal operation. When this bit = 0, simultaneous errors on multiple lanes are reported as one error. Selected when this bit = 1 and when REPDATATEST = 1. Detected errors from all lanes are trapped in a counter and sequentially signaled on SYNCOUTx±. Automatic reset of error counter. The error counter that causes assertion of SYNCOUTx± is automatically reset to 0 when AR_ECNTR = 1. All other counters are unaffected. This control is paged by the LINK_PAGE control in Register 0x300. This signal must only be programmed while the QBD is held in soft reset (Register 0x475, Bit 3), and must not be changed during normal operation. Reserved. Number of 4 × K multiframes during ILAS. This control is paged by the LINK_PAGE control in Register 0x300. This signal must only be programmed while the QBD is held in soft reset (Register 0x475, Bit 3), and must not be changed during normal operation. Error counter threshold value. These bits set when a SYNCOUTx± error or IRQx interrupt is sent due to BD, NIT, or UEK errors. This control is paged by the LINK_PAGE control in Register 0x300. This signal must only be programmed while the QBD is held in soft reset (Register 0x475, Bit 3), and must not be changed during normal operation. Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x1 0xFF Access R/W R/W R/W R/W R/W R R/W R/W Rev. B | Page 124 of 145 Data Sheet Addr. 0x47D Name SYNC_ASSERT_ MASK 0x480 ECNT_CTRL0 0x481 ECNT_CTRL1 0x482 ECNT_CTRL2 AD9172 Bits Bit Name [7:3] RESERVED [2:0] SYNC_ASSERT_ MASK [7:6] RESERVED [5:3] ECNT_ENA0 [2:0] ECNT_RST0 [7:6] RESERVED [5:3] ECNT_ENA1 [2:0] ECNT_RST1 [7:6] RESERVED [5:3] ECNT_ENA2 Settings Description Reserved. SYNCOUTx± assertion enable mask for BD, NIT, and UEK error conditions. This control is paged by the LINK_PAGE control in Register 0x300. Active high, SYNCOUTx± assertion enable mask for BD, NIT, and UEK error conditions, respectively. When an error counter, in any lane, has reached the error threshold count, ETH[7:0], and the corresponding SYNC_ASSERT_MASK bit is set, SYNCOUTx± is asserted. The mask bits are as follows (note that the bit sequence is reversed with respect to the other error count controls and the error counters): Bit 2 = bad disparity error (BDE). Bit 1 = not in table error (NIT). Bit 0 = unexpected K character error (UEK). Reserved. Error counter enables for Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Counters of each lane are addressed as follows: Bit 5 = unexpected K character error (UEK). Bit 4 = not in table error (NIT). Bit 3 = bad disparity error (BDE). Reset error counters for Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Counters of each lane are addressed as follows: Bit 2 = bad disparity error (BDE). Bit 1 = not in table error (NIT). Bit 0 = unexpected K character error (UEK). Reserved. Error counter enables for Lane 1. This control is paged by the LINK_PAGE control in Register 0x300. Counters of each lane are addressed as follows: Bit 5 = unexpected K character error (UEK). Bit 4 = not in table error (NIT). Bit 3 = bad disparity error (BDE). Reset error counters for Lane 1. This control is paged by the LINK_PAGE control in Register 0x300. Counters of each lane are addressed as follows: Bit 2 = unexpected K character error (UEK). Bit 1 = not in table error (NIT). Bit 0 = bad disparity error (BDE). Reserved. Error counter enables for Lane 2. This control is paged by the LINK_PAGE control in Register 0x300. Counters of each lane are addressed as follows: Bit 5 = unexpected K character error (UEK). Bit 4 = not in table error (NIT). Bit 3 = bad disparity error (BDE). Reset 0x0 0x7 0x0 0x7 0x7 0x0 0x7 0x7 0x0 0x7 Access R R/W R R/W R/W R R/W R/W R R/W Rev. B | Page 125 of 145 AD9172 Addr. Name 0x483 ECNT_CTRL3 0x484 ECNT_CTRL4 0x485 ECNT_CTRL5 0x486 ECNT_CTRL6 Bits Bit Name [2:0] ECNT_RST2 [7:6] RESERVED [5:3] ECNT_ENA3 [2:0] ECNT_RST3 [7:6] RESERVED [5:3] ECNT_ENA4 [2:0] ECNT_RST4 [7:6] RESERVED [5:3] ECNT_ENA5 [2:0] ECNT_RST5 [7:6] RESERVED Data Sheet Settings Description Reset error counters for Lane 2. This control is paged by the LINK_PAGE control in Register 0x300. Counters of each lane are addressed as follows: Bit 2 = unexpected K character error (UEK). Bit 1 = not in table error (NIT). Bit 0 = bad disparity error (BDE). Reserved. Error counter enables for Lane 3. This control is paged by the LINK_PAGE control in Register 0x300. Counters of each lane are addressed as follows: Bit 5 = unexpected K character error (UEK). Bit 4 = not in table error (NIT). Bit 3 = bad disparity error (BDE). Reset error counters for Lane 3. This control is paged by the LINK_PAGE control in Register 0x300. Counters of each lane are addressed as follows: Bit 2 = unexpected K character error (UEK). Bit 1 = not in table error (NIT). Bit 0 = bad disparity error (BDE). Reserved. Error counter enables for Lane 4. This control is paged by the LINK_PAGE control in Register 0x300. Counters of each lane are addressed as follows: Bit 5 = unexpected K character error (UEK). Bit 4 = not in table error (NIT). Bit 3 = bad disparity error (BDE). Reset error counters for Lane 4. This control is paged by the LINK_PAGE control in Register 0x300. Counters of each lane are addressed as follows: Bit 2 = unexpected K character error (UEK). Bit 1 = not in table error (NIT). Bit 0 = bad disparity error (BDE). Reserved. Error counter enables for Lane 5. This control is paged by the LINK_PAGE control in Register 0x300. Counters of each lane are addressed as follows: Bit 5 = unexpected K character error (UEK). Bit 4 = not in table error (NIT). Bit 3 = bad disparity error (BDE). Reset error counters for Lane 5. This control is paged by the LINK_PAGE control in Register 0x300. Counters of each lane are addressed as follows: Bit 2 = unexpected K character error (UEK). Bit 1 = not in table error (NIT). Bit 0 = bad disparity error (BDE). Reserved. Reset 0x7 0x0 0x7 0x7 0x0 0x7 0x7 0x0 0x7 0x7 0x0 Access R/W R R/W R/W R R/W R/W R R/W R/W R Rev. B | Page 126 of 145 Data Sheet Addr. Name 0x487 ECNT_CTRL7 0x488 ECNT_TCH0 0x489 ECNT_TCH1 Bits Bit Name [5:3] ECNT_ENA6 [2:0] ECNT_RST6 [7:6] RESERVED [5:3] ECNT_ENA7 [2:0] ECNT_RST7 [7:3] RESERVED [2:0] ECNT_TCH0 [7:3] RESERVED [2:0] ECNT_TCH1 AD9172 Settings Description Error counter enables for Lane 6. This control is paged by the LINK_PAGE control in Register 0x300. Counters of each lane are addressed as follows: Bit 5 = unexpected K character error (UEK). Bit 4 = not in table error (NIT). Bit 3 = bad disparity error (BDE). Reset error counters for Lane 6. This control is paged by the LINK_PAGE control in Register 0x300. Counters of each lane are addressed as follows: Bit 2 = unexpected K character error (UEK). Bit 1 = not in table error (NIT). Bit 0 = bad disparity error (BDE). Reserved. Error counter enables for Lane 7. This control is paged by the LINK_PAGE control in Register 0x300. Counters of each lane are addressed as follows: Bit 5 = unexpected K character error (UEK). Bit 4 = not in table error (NIT). Bit 3 = bad disparity error (BDE). Reset error counters for Lane 7. This control is paged by the LINK_PAGE control in Register 0x300. Counters of each lane are addressed as follows: Bit 2 = unexpected K character error (UEK). Bit 1 = not in table error (NIT). Bit 0 = bad disparity error (BDE). Reserved. Terminal count hold enable of error counters for Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. When set, the designated counter is to hold the terminal count value of 0xFF when it is reached until the counter is reset by the user. Otherwise, the designated counter rolls over. Counters of each lane are addressed as follows: Bit 2 = unexpected K character error (UEK). Bit 1 = not in table error (NIT). Bit 0 = bad disparity error (BDE). This signal must only be programmed while the QBD is held in soft reset (Register 0x475, Bit 3), and must not be changed during normal operation. Reserved. Terminal count hold enable of error counters for Lane 1. This control is paged by the LINK_PAGE control in Register 0x300. When set, the designated counter is to hold the terminal count value of 0xFF when it is reached until the counter is reset by the user. Otherwise, the designated counter rolls over. Counters of each lane are addressed as follows: Bit 2 = unexpected K character error (UEK). Bit 1 = not in table error (NIT). Reset 0x7 0x7 0x0 0x7 0x7 0x0 0x7 0x0 0x7 Rev. B | Page 127 of 145 Access R/W R/W R R/W R/W R R/W R R/W AD9172 Addr. Name 0x48A ECNT_TCH2 0x48B ECNT_TCH3 0x48C ECNT_TCH4 Bits Bit Name [7:3] RESERVED [2:0] ECNT_TCH2 [7:3] RESERVED [2:0] ECNT_TCH3 [7:3] RESERVED [2:0] ECNT_TCH4 Data Sheet Settings Description Bit 0 = bad disparity error (BDE). This signal must only be programmed while the QBD is held in soft reset (Register 0x475, Bit 3), and must not be changed during normal operation. Reserved. Terminal count hold enable of error counters for Lane 2. This control is paged by the LINK_PAGE control in Register 0x300. When set, the designated counter is to hold the terminal count value of 0xFF when it is reached until the counter is reset by the user. Otherwise, the designated counter rolls over. Counters of each lane are addressed as follows: Bit 2 = unexpected K character error (UEK). Bit 1 = not in table error (NIT). Bit 0 = bad disparity error (BDE). This signal must only be programmed while the QBD is held in soft reset (Register 0x475, Bit 3), and must not be changed during normal operation. Reserved. Terminal count hold enable of error counters for Lane 3. This control is paged by the LINK_PAGE control in Register 0x300. When set, the designated counter is to hold the terminal count value of 0xFF when it is reached until the counter is reset by the user. Otherwise, the designated counter rolls over. Counters of each lane are addressed as follows: Bit 2 = unexpected K character error (UEK). Bit 1 = not in table error (NIT). Bit 0 = bad disparity error (BDE). This signal must only be programmed while the QBD is held in soft reset (Register 0x475, Bit 3), and must not be changed during normal operation. Reserved. Terminal count hold enable of error counters for Lane 4. This control is paged by the LINK_PAGE control in Register 0x300. When set, the designated counter is to hold the terminal count value of 0xFF when it is reached until the counter is reset by the user. Otherwise, the designated counter rolls over. Counters of each lane are addressed as follows: Bit 2 = unexpected K character error (UEK). Bit 1 = not in table error (NIT). Bit 0 = bad disparity error (BDE). This signal must only be programmed while the QBD is held in soft reset (Register 0x475, Bit 3), and must not be changed during normal operation. Reset 0x0 0x7 0x0 0x7 0x0 0x7 Access R R/W R R/W R R/W Rev. B | Page 128 of 145 Data Sheet Addr. Name 0x48D ECNT_TCH5 0x48E ECNT_TCH6 0x48F ECNT_TCH7 0x490 ECNT_STAT0 Bits Bit Name [7:3] RESERVED [2:0] ECNT_TCH5 [7:3] RESERVED [2:0] ECNT_TCH6 [7:3] RESERVED [2:0] ECNT_TCH7 [7:4] RESERVED 3 LANE_ENA0 AD9172 Settings Description Reserved. Terminal count hold enable of error counters for Lane 5. This control is paged by the LINK_PAGE control in Register 0x300. When set, the designated counter is to hold the terminal count value of 0xFF when it is reached until the counter is reset by the user. Otherwise, the designated counter rolls over. Counters of each lane are addressed as follows: Bit 2 = unexpected K character error (UEK). Bit 1 = not in table error (NIT). Bit 0 = bad disparity error (BDE). This signal must only be programmed while the QBD is held in soft reset (Register 0x475, Bit 3), and must not be changed during normal operation. Reserved. Terminal count hold enable of error counters for Lane 6. This control is paged by the LINK_PAGE control in Register 0x300. When set, the designated counter is to hold the terminal count value of 0xFF when it is reached until the counter is reset by the user. Otherwise, the designated counter rolls over. Counters of each lane are addressed as follows: Bit 2 = unexpected K character error (UEK). Bit 1 = not in table error (NIT). Bit 0 = bad disparity error (BDE). This signal must only be programmed while the QBD is held in soft reset (Register 0x475, Bit 3), and must not be changed during normal operation. Reserved. Terminal count hold enable of error counters for Lane 7. This control is paged by the LINK_PAGE control in Register 0x300. When set, the designated counter is to hold the terminal count value of 0xFF when it is reached until the counter is reset by the user. Otherwise, the designated counter rolls over. Counters of each lane are addressed as follows: Bit 2 = unexpected K character error (UEK). Bit 1 = not in table error (NIT). Bit 0 = bad disparity error (BDE). This signal must only be programmed while the QBD is held in soft reset (Register 0x475, Bit 3), and must not be changed during normal operation. Reserved. This output indicates if Lane 0 is enabled. This control is paged by the LINK_PAGE control in Register 0x300. Reset 0x0 0x7 0x0 0x7 0x0 0x7 0x0 0x0 Access R R/W R R/W R R/W R R Rev. B | Page 129 of 145 AD9172 Addr. Name 0x491 ECNT_STAT1 0x492 ECNT_STAT2 0x493 ECNT_STAT3 Bits Bit Name [2:0] ECNT_TCR0 [7:4] RESERVED 3 LANE_ENA1 [2:0] ECNT_TCR1 [7:4] RESERVED 3 LANE_ENA2 [2:0] ECNT_TCR2 [7:4] RESERVED 3 LANE_ENA3 Data Sheet Settings Description Terminal count reached indicator of error counters for Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Set these bits to 1 when the corresponding counter terminal count value of 0xFF is reached. If ECNT_TCHx is set, the terminal count value for the corresponding counter is held until the counter is reset by the user; otherwise, the counter rolls over and continues counting. Counters of each lane are addressed as follows: Bit 2 = unexpected K character error (UEK). Bit 1 = not in table error (NIT). Bit 0 = bad disparity error (BDE). Reserved. This output indicates if Lane 1 is enabled. This control is paged by the LINK_PAGE control in Register 0x300. Terminal count reached indicator of error counters for Lane 1. This control is paged by the LINK_PAGE control in Register 0x300. Set these bits to 1 when the corresponding counter terminal count value of 0xFF is reached. If ECNT_TCHx is set, the terminal count value for the corresponding counter is held until the counter is reset by the user; otherwise, the counter rolls over and continues counting. Counters of each lane are addressed as follows: Bit 2 = unexpected K character error (UEK). Bit 1 = not in table error (NIT). Bit 0 = bad disparity error (BDE). Reserved. This output indicates if Lane 2 is enabled. This control is paged by the LINK_PAGE control in Register 0x300. Terminal count reached indicator of error counters for Lane 2. This control is paged by the LINK_PAGE control in Register 0x300. Set these bits to 1 when the corresponding counter terminal count value of 0xFF is reached. If ECNT_TCHx is set, the terminal count value for the corresponding counter is held until the counter is reset by the user; otherwise, the counter rolls over and continues counting. Counters of each lane are addressed as follows: Bit 2 = unexpected K character error (UEK). Bit 1 = not in table error (NIT). Bit 0 = bad disparity error (BDE). Reserved. This output indicates if Lane 3 is enabled. This control is paged by the LINK_PAGE control in Register 0x300. Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R R R R R R R R R Rev. B | Page 130 of 145 Data Sheet Addr. Name 0x494 ECNT_STAT4 0x495 ECNT_STAT5 0x496 ECNT_STAT6 Bits Bit Name [2:0] ECNT_TCR3 [7:4] RESERVED 3 LANE_ENA4 [2:0] ECNT_TCR4 [7:4] RESERVED 3 LANE_ENA5 [2:0] ECNT_TCR5 [7:4] RESERVED 3 LANE_ENA6 AD9172 Settings Description Terminal count reached indicator of error counters for Lane 3. This control is paged by the LINK_PAGE control in Register 0x300. Set these bits to 1 when the corresponding counter terminal count value of 0xFF is reached. If ECNT_TCHx is set, the terminal count value for the corresponding counter is held until the counter is reset by the user; otherwise, the counter rolls over and continues counting. Counters of each lane are addressed as follows: Bit 2 = unexpected K character error (UEK). Bit 1 = not in table error (NIT). Bit 0 = bad disparity error (BDE). Reserved. This output indicates if Lane 4 is enabled. This control is paged by the LINK_PAGE control in Register 0x300. Terminal count reached indicator of error counters for Lane 4. This control is paged by the LINK_PAGE control in Register 0x300. Set these bits to 1 when the corresponding counter terminal count value of 0xFF is reached. If ECNT_TCHx is set, the terminal count value for the corresponding counter is held until the counter is reset by the user; otherwise, the counter rolls over and continues counting. Counters of each lane are addressed as follows: Bit 2 = unexpected K character error (UEK). Bit 1 = not in table error (NIT). Bit 0 = bad disparity error (BDE). Reserved. This output indicates if Lane 5 is enabled. This control is paged by the LINK_PAGE control in Register 0x300. Terminal count reached indicator of error counters for Lane 5. This control is paged by the LINK_PAGE control in Register 0x300. Set these bits to 1 when the corresponding counter terminal count value of 0xFF is reached. If ECNT_TCHx is set, the terminal count value for the corresponding counter is held until the counter is reset by the user; otherwise, the counter rolls over and continues counting. Counters of each lane are addressed as follows: Bit 2 = unexpected K character error (UEK). Bit 1 = not in table error (NIT). Bit 0 = bad disparity error (BDE). Reserved. This output indicates if Lane 6 is enabled. This control is paged by the LINK_PAGE control in Register 0x300. Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R R R R R R R R R Rev. B | Page 131 of 145 AD9172 Addr. Name 0x497 ECNT_STAT7 0x4B0 LINK_STATUS0 Bits Bit Name [2:0] ECNT_TCR6 [7:4] RESERVED 3 LANE_ENA7 [2:0] ECNT_TCR7 7 BDE0 6 NIT0 5 UEK0 4 ILD0 3 ILS0 Data Sheet Settings 0 1 0 1 0 1 0 1 0 1 Description Terminal count reached indicator of error counters for Lane 6. This control is paged by the LINK_PAGE control in Register 0x300. Set these bits to 1 when the corresponding counter terminal count value of 0xFF is reached. If ECNT_TCHx is set, the terminal count value for the corresponding counter is held until the counter is reset by the user; otherwise, the counter rolls over and continues counting. Counters of each lane are addressed as follows: Bit 2 = unexpected K character error (UEK). Bit 1 = not in table error (NIT). Bit 0 = bad disparity error (BDE). Reserved. This output indicates if Lane 7 is enabled. This control is paged by the LINK_PAGE control in Register 0x300. Terminal count reached indicator of error counters for Lane 7. This control is paged by the LINK_PAGE control in Register 0x300. Set these bits to 1 when the corresponding counter terminal count value of 0xFF is reached. If ECNT_TCHx is set, the terminal count value for the corresponding counter is held until the counter is reset by the user; otherwise, the counter rolls over and continues counting. Counters of each lane are addressed as follows: Bit 2 = unexpected K character error (UEK). Bit 1 = not in table error (NIT). Bit 0 = bad disparity error (BDE). Bad disparity errors status for Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ETH[7:0] value. Not in table errors status for Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ETH[7:0] value. Unexpected K character errors status for Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ETH[7:0] value. Interlane deskew status for Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Deskew failed. Deskew achieved. Initial lane synchronization status for Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R R R R R R R R R Rev. B | Page 132 of 145 Data Sheet Addr. Name Bits Bit Name 2 CKS0 1 FS0 0 CGS0 0x4B1 LINK_STATUS1 7 BDE1 6 NIT1 5 UEK1 4 ILD1 3 ILS1 2 CKS1 1 FS1 0 CGS1 AD9172 Settings 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Description Computed checksum status for Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Checksum is incorrect. Checksum is correct. Frame synchronization status for Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Code group synchronization status for Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Bad disparity errors status for Lane 1. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ETH[7:0] value. Not in table errors status for Lane 1. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ETH[7:0] value. Unexpected K character errors status for Lane 1. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ETH[7:0] value. Interlane deskew status for Lane 1. This control is paged by the LINK_PAGE control in Register 0x300. Deskew failed. Deskew achieved. Initial lane synchronization status for Lane 1. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Computed checksum status for Lane 1. This control is paged by the LINK_PAGE control in Register 0x300. Checksum is incorrect. Checksum is correct. Frame synchronization status for Lane 1. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Code group synchronization status for Lane 1. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R R R R R R R R R R R Rev. B | Page 133 of 145 AD9172 Addr. Name 0x4B2 LINK_STATUS2 Bits Bit Name 7 BDE2 6 NIT2 5 UEK2 4 ILD2 3 ILS2 2 CKS2 1 FS2 0 CGS2 0x4B3 LINK_STATUS3 7 BDE3 6 NIT3 5 UEK3 Data Sheet Settings 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Description Bad disparity errors status for Lane 2. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ETH[7:0] value. Not in table errors status for Lane 2. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ETH[7:0] value. Unexpected K character errors status for Lane 2. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ETH[7:0] value. Interlane deskew status for Lane 2. This control is paged by the LINK_PAGE control in Register 0x300. Deskew failed. Deskew achieved. Initial lane synchronization status for Lane 2. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Computed checksum status for Lane 2. This control is paged by the LINK_PAGE control in Register 0x300. Checksum is incorrect. Checksum is correct. Frame synchronization status for Lane 2. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Code group synchronization status for Lane 2. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Bad disparity errors status for Lane 3. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ETH[7:0] value. Not in table errors status for Lane 3. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ETH[7:0] value. Unexpected K character errors status for Lane 3. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ETH[7:0] value. Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R R R R R R R R R R R Rev. B | Page 134 of 145 Data Sheet Addr. Name Bits Bit Name 4 ILD3 3 ILS3 2 CKS3 1 FS3 0 CGS3 0x4B4 LINK_STATUS4 7 BDE4 6 NIT4 5 UEK4 4 ILD4 3 ILS4 2 CKS4 AD9172 Settings 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Description Interlane deskew status for Lane 3. This control is paged by the LINK_PAGE control in Register 0x300. Deskew failed. Deskew achieved. Initial lane synchronization status for Lane 3. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Computed checksum status for Lane 3. This control is paged by the LINK_PAGE control in Register 0x300. Checksum is incorrect. Checksum is correct. Frame synchronization status for Lane 3. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Code group synchronization status for Lane 3. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Bad disparity errors status for Lane 4. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ETH[7:0] value. Not in table errors status for Lane 4. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ETH[7:0] value. Unexpected K character errors status for Lane 4. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ETH[7:0] value. Interlane deskew status for Lane 4. This control is paged by the LINK_PAGE control in Register 0x300. Deskew failed. Deskew achieved. Initial lane synchronization status for Lane 4. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Computed checksum status for Lane 4. This control is paged by the LINK_PAGE control in Register 0x300. Checksum is incorrect. Checksum is correct. Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R R R R R R R R R R R Rev. B | Page 135 of 145 AD9172 Addr. Name Bits Bit Name 1 FS4 0 CGS4 0x4B5 LINK_STATUS5 7 BDE5 6 NIT5 5 UEK5 4 ILD5 3 ILS5 2 CKS5 1 FS5 0 CGS5 0x4B6 LINK_STATUS6 7 BDE6 Data Sheet Settings 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Description Frame synchronization status for Lane 4. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Code group synchronization status for Lane 4. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Bad disparity errors status for Lane 5. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ETH[7:0] value. Not in table errors status for Lane 5. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ETH[7:0] value. Unexpected K character errors status for Lane 5. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ETH[7:0] value. Interlane deskew status for Lane 5. This control is paged by the LINK_PAGE control in Register 0x300. Deskew failed. Deskew achieved. Initial lane synchronization status for Lane 5. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Computed checksum status for Lane 5. This control is paged by the LINK_PAGE control in Register 0x300. Checksum is incorrect. Checksum is correct. Frame synchronization status for Lane 5. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Code group synchronization status for Lane 5. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Bad disparity errors status for Lane 6. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ETH[7:0] value. Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R R R R R R R R R R R Rev. B | Page 136 of 145 Data Sheet Addr. Name Bits Bit Name 6 NIT6 5 UEK6 4 ILD6 3 ILS6 2 CKS6 1 FS6 0 CGS6 0x4B7 LINK_STATUS7 7 BDE7 6 NIT7 5 UEK7 4 ILD7 AD9172 Settings 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Description Not in table errors status for Lane 6. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ETH[7:0] value. Unexpected K character errors status for Lane 6. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ETH[7:0] value. Interlane deskew status for Lane 6. This control is paged by the LINK_PAGE control in Register 0x300. Deskew failed. Deskew achieved. Initial lane synchronization status for Lane 6. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Computed checksum status for Lane 6. This control is paged by the LINK_PAGE control in Register 0x300. Checksum is incorrect. Checksum is correct. Frame synchronization status for Lane 6. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Code group synchronization status for Lane 6. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Bad disparity errors status for Lane 7. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ETH[7:0] value. Not in table errors status for Lane 7. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ETH[7:0] value. Unexpected K character errors status Lane 7. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ETH[7:0] value. Interlane deskew status for Lane 7. This control is paged by the LINK_PAGE control in Register 0x300. Deskew failed. Deskew achieved. Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R R R R R R R R R R R Rev. B | Page 137 of 145 AD9172 Addr. Name Bits Bit Name 3 ILS7 2 CKS7 1 FS7 0 CGS7 0x4B8 JESD_IRQ_ENABLEA 7 EN_BDE 6 EN_NIT 5 EN_UEK 4 EN_ILD 3 EN_ILS 2 EN_CKS 1 EN_FS 0 EN_CGS 0x4B9 JESD_IRQ_ENABLEB [7:1] RESERVED Data Sheet Settings 0 1 0 1 0 1 0 1 Description Initial lane synchronization status for Lane 7. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Computed checksum status for Lane 7. This control is paged by the LINK_PAGE control in Register 0x300. Checksum is incorrect. Checksum is correct. Frame synchronization status for Lane 7. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Code group synchronization status for Lane 7. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Bad disparity error counter. This control is paged by the LINK_PAGE control in Register 0x300. Not in table error counter. This control is paged by the LINK_PAGE control in Register 0x300. Unexpected K error counter. This control is paged by the LINK_PAGE control in Register 0x300. Interlane deskew. This control is paged by the LINK_PAGE control in Register 0x300. Initial lane synchronization. This control is paged by the LINK_PAGE control in Register 0x300. Good checksum. This bit compares two checksums: the checksum that the transmitter sent over the link during the ILAS and the checksum that the receiver calculated from the ILAS data that the transmitter sent over the link. Note that the checksum IRQ only looks at data sent by the transmitter and not the checksum programmed into Register 0x45D. This control is paged by the LINK_PAGE control in Register 0x300. Frame synchronization. This control is paged by the LINK_PAGE control in Register 0x300. Code group synchronization. This control is paged by the LINK_PAGE control in Register 0x300. Reserved. Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R R R R R/W R/W R/W R/W R/W R/W R/W R/W R Rev. B | Page 138 of 145 Data Sheet AD9172 Addr. Name Bits 0 0x4BA JESD_IRQ_STATUSA 7 6 5 4 3 2 1 0 0x4BB JESD_IRQ_STATUSB [7:1] 0 0x4BC IRQ_OUTPUT_MUX_ [7:1] JESD 0 0x580 BE_SOFT_OFF_ 7 GAIN_CTRL [6:3] [2:0] 0x581 BE_SOFT_OFF_ 7 ENABLE Bit Name EN_ILAS IRQ_BDE IRQ_NIT IRQ_UEK IRQ_ILD IRQ_ILS IRQ_CKS IRQ_FS IRQ_CGS RESERVED IRQ_ILAS RESERVED MUX_JESD_IRQ BE_SOFT_OFF_ GAIN_EN RESERVED BE_GAIN_RAMP_ RATE ENA_SHORT_ PAERR_SOFTOFF Settings 0 1 Description Configuration mismatch (checked for Lane 0 only). The ILAS IRQ compares the two sets of ILAS data obtained by the receiver. The first set of data is the ILAS data sent over the JESD204B link by the transmitter. The second set of data is the ILAS data programmed into the receiver via the SPI (Register 0x450 to Register 0x45D). If any of the data differs, the IRQ is triggered. Note that all of the ILAS data, including the checksum, is compared. This control is paged by the LINK_PAGE control in Register 0x300. Bad disparity error counter. This control is paged by the LINK_PAGE control in Register 0x300. Not in table error counter. This control is paged by the LINK_PAGE control in Register 0x300. Unexpected K error counter. This control is paged by the LINK_PAGE control in Register 0x300. Interlane deskew. This control is paged by the LINK_PAGE control in Register 0x300. Initial lane synchronization. This control is paged by the LINK_PAGE control in Register 0x300. Good checksum. This control is paged by the LINK_PAGE control in Register 0x300. Frame synchronization. This control is paged by the LINK_PAGE control in Register 0x300. Code group synchronization. This control is paged by the LINK_PAGE control in Register 0x300. Reserved. Configuration mismatch (checked for Lane 0 only). This control is paged by the LINK_PAGE control in Register 0x300. Reserved. Selects which IRQ pin is connected to the JESD204B IRQx sources. Route the IRQ trigger signal to the IRQ0 pin. Route the IRQ trigger signal to the IRQ1 pin. Must be 1 to use soft off/on. This control is paged by the MAINDAC_PAGE control in Register 0x008. Reserved. Sets ramp rate. The gain ramps from 0 to 1 (or 1 to 0) in 32 steps over 2(CODE + 8) DAC clock periods. This control is paged by the MAINDAC_PAGE control in Register 0x008. Enable short PA error soft off. This control is paged by the MAINDAC_PAGE control in Register 0x008. Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x1 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R R/W R/W R R/W R/W Rev. B | Page 139 of 145 AD9172 Data Sheet Addr. 0x582 0x583 0x584 0x585 0x586 Name Bits 6 [5:4] 3 2 1 0 BE_SOFT_ON_ 7 ENABLE 6 [5:0] LONG_PA_THRES_ [7:0] LSB LONG_PA_THRES_ [7:5] MSB [4:0] LONG_PA_CONTROL 7 [6:4] [3:0] LONG_PA_POWER_ [7:0] LSB Bit Name ENA_LONG_ PAERR_SOFTOFF RESERVED ENA_JESD_ERR_ SOFTOFF ROTATE_SOFT_ OFF_EN TXEN_SOFT_OFF_ EN SPI_SOFT_OFF_EN SPI_SOFT_ON_EN LONG_LEVEL_ SOFTON_EN RESERVED LONG_PA_ THRESHOLD[7:0] RESERVED LONG_PA_ THRESHOLD[12:8] LONG_PA_ENABLE RESERVED LONG_PA_AVG_ TIME LONG_PA_ POWER[7:0] Settings Description Enable long PA error soft off. This control is paged by the MAINDAC_PAGE control in Register 0x008. Reserved. Enable JESD204B side error soft off. This control is paged by the MAINDAC_PAGE control in Register 0x008. When set to 1, the synchronization logic rotation triggers the DAC output soft off. Note that Register 0x03B, Bit 0 must also be high. This control is paged by the MAINDAC_ PAGE control in Register 0x008. When set to 1, a TXENx falling edge triggers the DAC output soft off. This control is paged by the MAINDAC_PAGE control in Register 0x008. Force a soft off when gain is 1. This control is paged by the MAINDAC_PAGE control in Register 0x008. Force a soft on when gain is 0. This control is paged by the MAINDAC_PAGE control in Register 0x008. When set to 1, this bit enables the long level soft on. This control is paged by the MAINDAC_PAGE control in Register 0x008. Reserved. Long average power threshold for comparison. This control is paged by the MAINDAC_PAGE control in Register 0x008. Reserved. Long average power threshold for comparison. This control is paged by the MAINDAC_PAGE control in Register 0x008. Enable long average power calculation and error detection. This control is paged by the MAINDAC_PAGE control in Register 0x008. Reserved. Sets length of long PA averaging time. This control is paged by the MAINDAC_PAGE control in Register 0x008. Averaging time = 29 + LONG_PA_AVG_TIME (PA clock periods). A PA clock period is calculated by the following: If the main interpolation is >1×, PA clock period = 4 × main interpolation × DAC clock period. If channel interpolation is >1×, PA clock period = 8 × main interpolation × DAC clock period. Otherwise, PA clock period = 32 × DAC clock period. Long average power readback. Power detected at data bus = I2 + Q2. The data bus calculation only uses the 6 MSBs of the I and Q data bus samples. This control is paged by the MAINDAC_PAGE control in Register 0x008. Reset 0x1 0x0 0x0 0x1 0x1 0x0 0x0 0x1 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R/W R R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R R/W R Rev. B | Page 140 of 145 Data Sheet AD9172 Addr. Name Bits 0x587 LONG_PA_POWER_ [7:5] MSB [4:0] 0x588 SHORT_PA_THRES_ [7:0] LSB 0x589 SHORT_PA_THRES_ [7:5] MSB [4:0] 0x58A SHORT_PA_ 7 CONTROL [6:2] [1:0] 0x58B SHORT_PA_POWER_ [7:0] LSB 0x58C SHORT_PA_POWER_ [7:5] MSB [4:0] 0x58D TXEN_SM_0 [7:1] 0 0x596 BLANKING_CTRL [7:4] 3 2 [1:0] Bit Name RESERVED LONG_PA_ POWER[12:8] Settings SHORT_PA_ THRESHOLD[7:0] RESERVED SHORT_PA_ THRESHOLD[12:8] SHORT_PA_ENABLE RESERVED SHORT_PA_AVG_ TIME SHORT_PA_ POWER[7:0] RESERVED SHORT_PA_ POWER[12:8] RESERVED ENA_TXENSM RESERVED SPI_TXEN ENA_SPI_TXEN RESERVED Description Reserved. Long average power readback. Power detected at data bus = I2 + Q2. The data bus calculation only uses the 6 MSBs of the I and Q data bus samples. This control is paged by the MAINDAC_PAGE control in Register 0x008. Short average power threshold for comparison. This control is paged by the MAINDAC_PAGE control in Register 0x008. Reserved. Short average power threshold for comparison. This control is paged by the MAINDAC_PAGE control in Register 0x008. Enable short average power calculation and error detection. This control is paged by the MAINDAC_PAGE control in Register 0x008. Reserved. Sets length of short PA averaging. This control is paged by the MAINDAC_PAGE control in Register 0x008. Averaging time = 2SHORT_PA_AVG_TIME (PA clock periods). A PA clock period is calculated by the following: If the main interpolation is >1×, PA clock period = 4 × main interpolation × DAC clock period. If channel interpolation is >1×, PA clock period = 8 × main interpolation × DAC clock period. Otherwise, PA clock period = 32 × DAC clock period. Short average power readback. Power detected at data bus = I2 + Q2. The data bus calculation only uses the 6 MSBs of the I and Q data bus samples. This control is paged by the MAINDAC_PAGE control in Register 0x008. Reserved. Short average power readback. Power detected at data bus = I2 + Q2. The data bus calculation only uses the 6 MSBs of the I and Q data bus samples. This control is paged by the MAINDAC_PAGE control in Register 0x008. Reserved. Enable TXEN state machine. This control is paged by the MAINDAC_PAGE control in Register 0x008. Reserved. If ENA_SPI_TXEN (Bit 2 of this register) = 1, the value of this register is the value of the TXENx status. This control is paged by the MAINDAC_PAGE control in Register 0x008. Enable TXENx control via the SPI by setting this bit to 1. This control is paged by the MAINDAC_PAGE control in Register 0x008. Reserved. Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x1 0x0 0x0 0x0 0x0 0x0 Access R R R/W R R/W R/W R R/W R R R R/W R/W R R/W R/W R Rev. B | Page 141 of 145 AD9172 Data Sheet Addr. Name 0x597 JESD_PA_INT0 Bits Bit Name [7:0] JESD_PA_INT_ CNTRL[7:0] 0x598 JESD_PA_INT1 [7:1] RESERVED 0 JESD_PA_INT_ CNTRL[8] 0x599 TXEN_FLUSH_CTRL0 [7:1] RESERVED 0 SPI_FLUSH_EN 0x705 NVM_LOADER_EN [7:1] RESERVED 0 NVM_BLR_EN 0x790 DACPLL_PDCTRL0 7 PLL_PD5 [6:4] PLL_PD4 3 PLL_PD3 2 PLL_PD2 1 PLL_PD1 0 PLL_PD0 0x791 DACPLL_PDCTRL1 [7:5] RESERVED 4 PLL_PD10 3 PLL_PD9 2 PLL_PD8 Settings Description Each bit enables a JESD204B PA interrupt. Bit 8 = CGS. Bit 7 = frame sync. Bit 6 = good check sum. Bit 5 = initial lane sync. Bit 4 = interlane deskew. Bit 3 = bad disparity error counter. Bit 2 = NIT error counter. Bit 1= UEK error counter. Bit 0 = lane FIFO overflow or underflow. Reserved. Each bit enables a JESD204B PA interrupt. Bit 8 = CGS Bit 7 = frame sync. Bit 6 = good check sum. Bit 5 = initial lane sync. Bit 4 = interlane deskew. Bit 3 = bad disparity error counter. Bit 2 = NIT error counter. Bit 1= UEK error counter. Bit 0 = lane FIFO overflow or underflow. Reserved. Enable datapath flush. This control is paged by the MAINDAC_PAGE control in Register 0x008. Reserved. Enable bootloader. This bit self clears when the boot loader completes or fails. PLL power-down control. Write this bit to 1 if bypassing the PLL. If using the PLL, keep this value at default (0). PLL power-down control. Write this bit to 1 if bypassing the PLL. If using the PLL, keep this value at default (0). PLL power-down control. Write this bit to 1 if bypassing the PLL. If using the PLL, keep this value default (0). PLL power-down control. Write this bit to 1 if bypassing the PLL. If using the PLL, keep this value at default (0). PLL power-down control. Write this bit to 1 if bypassing the PLL. If using the PLL, write this bit to 0. PLL power-down control. Write this bit to 1 if bypassing the PLL. If using the PLL, keep this value at default (0). Reserved. PLL power-down control. Write this bit to 1 if bypassing the PLL. If using the PLL, keep this value at default (0). PLL power-down control. Write this bit to 1 if bypassing the PLL. If using the PLL, keep this value at default (0). PLL power-down control. Write this bit to 1 if bypassing the PLL. If using the PLL, keep this value at default (0). Reset 0x0 0x0 0x0 0x0 0x1 0x0 0x0 0x0 0x0 0x0 0x0 0x1 0x0 0x0 0x0 0x0 0x0 Rev. B | Page 142 of 145 Access R/W R R/W R R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Data Sheet Addr. Name 0x792 DACPLL_CTRL0 0x793 DACPLL_CTRL1 0x794 DACPLL_CTRL2 0x795 DACPLL_CTRL3 0x796 DACPLL_CTRL4 0x797 DACPLL_CTRL5 0x798 DACPLL_CTRL6 0x799 DACPLL_CTRL7 0x7A0 DACPLL_CTRL9 AD9172 Bits Bit Name Settings Description Reset 1 PLL_PD7 PLL power-down control. Write this bit to 1 0x0 if bypassing the PLL. If using the PLL, keep this value at default (0). 0 PLL_PD6 PLL power-down control. Write this bit to 1 0x0 if bypassing the PLL. If using the PLL, keep this value at default (0). [7:2] RESERVED Reserved. 0x0 1 D_CAL_RESET Resets VCO calibration. 0x1 0 D_RESET_VCO_DIV Setting this high holds the VCO output 0x0 divider in reset. This has the effect of turning off the input (and output) of the ADC clock driver. [7:2] RESERVED Reserved. 0x0 [1:0] M_DIVIDER-1 Programmable predivider value for PFD (in 0x0 n - 1 notation). M_DIVIDER = PLL reference clock/PFD frequency. For optimal spectral performance, choose an M divider setting that selects a high PFD frequency within the allowable PFD range. For 9.96 GHz VCO frequency 10.87 GHz, 25 MHz PFD frequency 225 MHz. For 9.96 GHz > VCO frequency > 10.87 GHz, 25 MHz PFD frequency 770 MHz. 0 Divide by 1. 1 Divide by 2. 10 Divide by 3. 11 Divide by 4. [7:6] RESERVED Reserved. 0x0 [5:0] DACPLL_CP Charge pump current control. Charge 0x4 pump current = 100 µA + code × 100 µA. [7:4] RESERVED Reserved. 0x0 [3:0] D_CP_CALBITS DAC PLL optimization control. 0x8 [7:4] PLL_CTRL0 DAC PLL optimization control. 0xD [3:0] RESERVED Reserved. 0x2 [7:6] RESERVED Reserved. 0x0 [5:0] PLL_CTRL1 DAC PLL optimization control. 0x20 7 RESERVED Reserved. 0x0 6 PLL_CTRL3 DAC PLL optimization control. 0x0 [5:0] PLL_CTRL2 DAC PLL optimization control. 0x1C [7:6] ADC_CLK_DIVIDER ADC clock output divider. 0x0 0 Divide by 1. 1 Divide by 2. 10 Divide by 3. 11 Divide by 4. [5:0] N_DIVIDER Programmable divide by N value from 0x8 2 to 50. N_DIVIDER = (DAC frequency × M_DIVIDER)/(8 × reference clock frequency). [7:6] RESERVED Reserved. 0x2 5 D_EN_VAR_FINE_ DAC PLL control. 0x0 PRE [4:3] RESERVED Reserved. 0x2 2 D_EN_VAR_ DAC PLL control. 0x0 COARSE_PRE [1:0] RESERVED Reserved. 0x0 Access R/W R/W R R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev. B | Page 143 of 145 AD9172 Addr. Name 0x7A2 DACPLL_CTRL10 0x7B5 PLL_STATUS Bits Bit Name Settings Description 7 RESERVED Reserved. [6:5] D_REGULATOR_ CAL_WAIT DAC PLL optimization control. [4:3] D_VCO_CAL_WAIT DAC PLL optimization control. [2:1] D_VCO_CAL_ CYCLES DAC PLL optimization control. 0 RESERVED Reserved. [7:1] RESERVED Reserved. 0 PLL_LOCK DAC PLL lock status. Data Sheet Reset 0x0 0x1 0x2 0x2 0x1 0x0 0x0 Access R R/W R/W R/W R/W R R Rev. B | Page 144 of 145 Data Sheet OUTLINE DIMENSIONS A1 BALL CORNER INDICATOR 10.10 10.00 SQ 9.90 R 0.5~1.5 TOP VIEW AD9172 R 1.0 9.80 9.70 SQ 9.60 6.60 REF SQ 0.15 REF 8.80 SQ REF 0.80 BSC 0.60 REF 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M BOTTOM VIEW A1 BALL CORNER PKG-005195 05-10-2016-A 1.71 1.56 1.41 DETAIL A SIDE VIEW 0.40 0.35 0.30 SEATING PLANE DETAIL A 0.87 REF 0.38 0.34 0.30 0.50 0.45 0.40 BALL DIAMETER COPLANARITY 0.12 ORDERING GUIDE Model1 AD9172BBPZ AD9172BBPZRL AD9172-FMC-EBZ COMPLIANT TO JEDEC STANDARDS MO-275-EEAB-1. Figure 88. 144-Ball Ball Grid Array, Thermally Enhanced [BGA_ED] (BP-144-1) Dimensions shown in millimeters Temperature Range -40°C to +85°C -40°C to +85°C Package Description 144-Ball Ball Grid Array, Thermally Enhanced [BGA_ED] 144-Ball Ball Grid Array, Thermally Enhanced [BGA_ED] Evaluation Board 1 Z = RoHS Compliant Part. Package Option BP-144-1 BP-144-1 ©20172019 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D15453-0-8/19(B) Rev. B | Page 145 of 145Adobe PDF Library 11.0