1991 Philips RF Communications Data Handbook

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INTEGRATED CIRCUITS

RF
Communications
...
Signetics
Philips Semiconductors '

,

/ ,. /

PHILIPS

Signetics reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Signetics assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Signetics makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Signetics Products are not designed for use in life support appliances, devices, or systems where malfunction of a Signetics Product can reasonably be expected to result in a personal injury. Signetics customers using or selling Signetics' Products for use in such applications do so at their own risk and agree to fully indemnify Signetics for any damages resulting from such improper use or sale.
Signetics registers eligible circuits under the Semiconductor Chip Protection Act.
Copyright 1991 Signetics Company a division of North American Philips Corporation
All rights reserved.

Product Status

DEFINITIONS

Data Sheet Identification

Product Status

Definition

Ol>Jecllve SpeclllcaBon Formative or In Deolgn

This data sheet contains the design target or goal specftlcatlons for product development. Specifications may change In any manner without notice.

Pnll/mln8fY Spec/llcaBon Preproduction ProcklCt

This data sheet contains preliminary data, and a<q>lemantary dala will be publlehed at a later dall>. Slgnetlc8 reserves the right to make changes at any time without notice in order to l~rove design and supply the best possllle product.

ProdUcf Spedllcallon

Full Production

Thie da!a sheet contains Final SpecWlcatlons. Slgnetlcs reserves the right to make changes at any time without notlce, In order to Jrrprove design and supply the best possible product.

iv

RF Communications Handbook Contents

Preface � . . � � � � . � . . . � . . � . � . . � � . . � � � . . . � � � . . . � . � � � . . . � � . . . � � . . � � � � � � � � � . . � � � . . . . Ill

Product status � . . . . . � . . . . . � � � � . � � � � . � � � . � � � � � � � . . � � . . . � � � � . . . . . � � � � . . � . � . . . . . . � Iv

Alphanumeric product list . � � � � . � � � � � � � . � � . . � � � � . . � � � . . � � � � � . � �. . � � � . � . � � . � . � � . . . vii

Ordering Information � � . � � � . � � . � . . � � � . � � � � � � � � � � � � . . � . � . . . . . . . . � � � . � � � � . . � � � � � � � � x

Section 1 Amplifiers �.���.���..���.�����.�..��..��.���....�����������.�.........

NE/SA5200

RF dual gain-stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

NE/SA5204

Wide-band high-frequency amplifier . . .. . .. .. . . . . .. . . . .. . . . . . . .. . . . . . . . . . .. . 15

NE/SA5205

Wide-band high-frequency amplifier .. . . . . .. . . . . . . .. . . .. . . . . . . .. . . .. . .. .. . . . 25

NE/SA5209

Wideband variable gain amplifier .. . . . .. . . .. . .. . . .. . . . .. . . . . . . . . .. . . .. . . . .. . 35

NE/SA5219

Wideband variable gain amplifier . . .. . .. .. . .. . . .. . .. . . .. . . . . . . . . . . . . .. . . . . . . 50

NE/SA5234

Matched quad high-performance low-voltage operational amplifier . . . . . . . . . . . . . . . . 63

AN1651

Using the NE/SA5234 amplifier............................................ 67

NE/SE5539

High frequency operational amplifier . . .. . . .. . .. . . .. . . . .. . .. .. .. . .. .. . .. . . .. . 81

NE5592

Video amplifier . . .. . .. .. .. . . . .. . .. .. .. . .. .. . . . .. .. .. . . . .. .. . .. .. . .. .. .. . 89

NE/SA/SE592 Video amplifier .. .. . . . .. .. . .. .. .. . .. .. .. . .. . . .. . . . .. . . . . . . . . . . . . .. . .. . . . 94

TDA1010A

6Waudioamplifierwithpreamplifier.................. ... . . . . . . . . . . . . . . . . . . . 102

TDA1015

1 to 4W audio amplifier with preamplnier............... . . . . . . . . . . . . . . . . . . . . . 120

TDA1011A

2 to6Waudio power amplifier with preamplifier . . .. .. . .. . .. . . . . . . . .. . .

130

TDA1013B

4Wamplifierwith DC volume control...............................

138

TDA7052

1 Watt low voltage audio power amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . .

146

TDA7052NAT 1-Watt low voltage audio power amp with DC volume control.. . . . . . . . . . . . . . . . .

151

TDA7056A

3-Watt mono BTL audio output amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

158

Section 2 Compandors � � . . � � � . . � � � . . � � � � . � � . . � � . � � � . � . . . . � � � � � . � � � � � � � � � � � � � � � � � 165

Compandor Selector Guide .. . .. . . .. . .. .. .. . .. .. . .. .. .. .. . . . .. . .. . . . .. . . . . .. . .. . . .. . .. .. . 166

NE570/571/SA571 Compandor .. .. . .. .. .. . . . .. .. .. . .. .. .. . . . .. .. . .. .. .. . . . .. . .. . . .. . .. .. . 167

AN174

Applications for compandors NE570/571/SA571 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

AN176

Compandorcookbook . .. .. . .. . . .. . .. .. .. . .. . . .. . .. . .. .. .. . . . . . .. .. . .. . . . 183

NE/SA572

Programmable analog compandor .. . .. . . .. . .. .. . .. . . . .. .. .. . . . .. .. . .. .. .. . 189

AN175

Automatic level control using the NE572 . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 197

NE/SA575

Lowvoltagecompandor.................................................. 198

NE/SA575SSOP Low voltage compandor in shrink small ouUine paCkage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

NE/SA576

Lowpowercompandor .. .. . . . .. .. . .. . . .. . .. .. . .. .. . .. . . .. .. . .. . . .. . .. . . . 218

NE/SA577

Unity gain level programmable powercompandor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

NE/SA578

Unity gain level programmable low power compandor . . . . . . . . . . . . . . . . . . . . . . . . . . 225

AN 1762

Companding with the NE577 and NE578 . . .. . .. .. . .. .. . . .. . . . .. . .. .. .. . .. . . . 229

Section 3 FM IF Systems � . . � � � � . � � � � � � � � � � � � � � � � � � � � � � . � � . � � � . . . � . � � � . . . � � . . . . . . 241

FM/IF Systems Selector Guide .. . .. . .. .. . .. .. .. .. .. . .. .. .. . .. . . . .. . . .. .. . . . . .. .. . . . . . . . .. . 242

MC3361

Low-power FM IF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

'NE/SA604A

High performance low power FM IF system . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . 246

NE/SA614A

Low power FM IF system .. . .. .. .. . . . .. .. . .. . . . . . . . . . .. . . . . .. . . . . . .. . . .. . 256

AN 1991

Audio decibel level detector with meter driver . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . 266

December 1991

v

Signetics RF Communications
RF Communications Handbook

Contents

Section 3 FM IF Systems (cont.)

AN1993

High sensitivity applications of low-power RF/IF integrated circuits

. . . . . . . . . . . 268

NE/SA605

High performance low power mixer FM IF system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280

NE/SA605SSOP High performance low power mixer FM IF system in shrink small outline package . . . . 290

NE/SA615

High performance low power mixer FM IF system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298

NE/SA615 (SSOP) High performance low power mixer FM IF system in shrink small outline package . . . . 308

AN1994

Reviewing key areas when designing with the NE605 . . . . . . . . . . . . . . . . . . . . . . . . . . 316

AN1995

Evaluating the NE605 SO and SSOP demo-board . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336

NE/SA606

Low-voltage high performance mixer FM IF system . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346

NE/SA616

Low-voltage high performance mixer FM IF system . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362

NE/SA607

Low voltage high performance mixer FM IF system . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378

NE/SA617

Low-voltage high performance mixer FM IF system . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392

TDA 1576T

FM/IF amplifier/demodulator circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406

AN192

A complete FM radio on a chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414

AN 193

TDA7000 for narrowband FM reception . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . 427

TDA 7000

Single-chip FM radio circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

442

TDA 7021T

Single-chip FM radio circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449

Section 4 Mixers ....................... - . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459

MC1496/MC1596 Balanced modulator/demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461

AN189

Balanced modulator/demodulator applications using the MC 1496/1596 ........... . 465

NE/SA602A

Double-balanced mixer and oscillator ...................................... . 470

NE/SA612A

Double-balanced mixer and oscillator ...................................... . 478

AN1981

New low-power single sideband circuits .................................... . 485

AN1982 TDA1574

Applying the oscillator of the NE602 in low-power mixer applications ............. . 493 FM front-end IC ....................................................... . 496

TDA1574T TDA5030A

Integrated FM tuner for radio receivers .................................... . 504

TV VHF mixer/oscillator UHF preamplifier ........ .

513

Section 5 Audio and Data Processors ............................................ . 519

NE/SA5750

Audio processor - companding and amplifier section .......................... . 521

NE/SA5751

Audio processor - filter and control section .................................. . 528

AN1741

Using the NE5750 and NE5751 for audio processing ......................... . 538

PCA5000AT

Paging decoder ....................................................... . 558

PCF5001T

POCSAG paging decoder with EE PROM storage ............................ . 577

TEA6300

Sound fader control circuit .............................................. . 579

UMF1000T

Data processor for cellular radio (DPROC) ................................. . 595

Section 6 Frequency Synthesizers, Pagers, and Data Receivers ...................... . 627

NE/SA701

Divide by: 128/129-64/65 dual modulus low power

ECL pre scaler .......................... .

629

NE/SA702

Divide by: 64/65/72 triple modulus low power ECL prescaler ........................................................ . 633

NE/SA703

Divide by: 128/129/144 triple modulus low power ECL prescaler ........................................................ . 637

TDD1742T

CMOS frequency synthesizer ............................................ . 641

TSA6057/T

Radio tuning PLL frequency synthesizer ................................... . 663

TSA5511

1.3GHz bi-directional 12C bus controlled synthesizer .......................... . 672

UMA1014T

Frequency synthesizer for cellular radio communication ....................... . 683

UMF1005T

Low-power frequency synthesizer ........................................ . 697

SCO/AN91004 Application report for the UMA1014T frequency synthesizer ............ .

718

UMF1009T

Low power frequency synthesizer for radio communication .. , .................. . 746

Section 7 Cellular chip set ..................................................... . 761

Cellular chip set design guide ........................................................... . 762

12C Bus specification .................................................................. . 806

AN168

The inter-integrated circuit (1 2C) serial bus: Theory and practical consideration ..... . 822

December 1991

vi

Signetics RF Communications
RF Communications Handbook

Contents

Section 8 Package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833

NE/SA630

Single pole double throw (SPOT) switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835

Section 9 Package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8-PIN (300 mils wide) Plastic Dualln-Line (N) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8-PIN (157 mils wide) Plastic SO (Small Outline) Dual In-Line (D) Package . . . . . . . . . . . . . . . . . . . . . . . .

8-PIN Plastic Dual in-line (NIP) package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9-PIN Plastic Single in-line (U) package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14-PIN (300 mils wide) Plastic Dual In-Line (NJ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14-PIN (157 mils wide) Plastic SO (Small Outline) Dual In-Line (D) Package . . . . . . . . . . . . . . . . . . . . .

16-PIN (300 mils wide) Plastic Dualln-Line (NJ Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

16-PIN (157 mils wide) Plastic SO (Small Outline) Dualln-Line (DJ Package . . . . . . . . . . . . . . . . . . . .

16-PI N Plastic SO Dual In-Line (DIT) Package . . . . . . . . . . . . . . . . . . . .

.... .. ..... ..........

16-PI N Plastic Dual In-Line (NIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

16-PIN Plastic SOL Dual In-Line (D/T) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

18-PIN Plastic Dual In-Line (NIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

20-PIN (300 mils wide) Plastic Dual In-Line (NJ Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

20-PIN (300 mils wide) Plastic SOL (Small Outline Large) Dual In-Line (D) Package . . . . . . . . . . . . . . . . .

20-PIN Plastic Shrink Small Outline Package (SSOP) (DK Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

20-PI N Plastic SO Dual In-Line (D/T) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

24-PIN (600 mils wide) Plastic Dual IN-Line Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

24-PIN (300 mils wide) Plastic SOL (Small OuWne Large) Dual In-Line (DJ Package . . . . . . . . .

28-PIN (600 mils wide) Plastic Dual In-Line (N) Package . . . . . . . . . . . . . . . . . . . . . . . . . . .

28-PIN (300 mils wide) Plastic SOL (Small Outline Large) Dual In-Line (D) Package . . . . .

28-PIN Plastic Dual In-Line (NIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

28-PIN Plastic SO Dual In-Line (DIT) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

845 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868

Section 1O Sales office listings . __ . _.... _........ _.. _........ _.. _. _____ .. _.... __ . . 869

December 1991

vii

Signetics

RF Cornmunications Handbook Alphanumeric product list

RF Communications

MC1496/MC1596 MC3361 NE/SA5200 NE/SA5204 NE/SA5205 NE/SA5209 NE/SA5219 NE/SA5234
NE/SE5539 NE5592 NE570/571/SA571 NE/SA572 NE/SA575 NE/SA575 SSOP NE/SA5750 NE/SA5751 NE/SA576 NE/SA577 NE/SA578 NE/SA/SE592 NE/SA602A NE/SA604A NE/SA605 NE/SA605 (SSOP) NE/SA606 NE/SA607 NE/SA612A NE/SA614A NE/SA615 NE/SA615 (SSOP) NE/SA616 NE/SA617 NE630 NE/SA701 NE/SA702 NE/SA703 PCA5000AT PCF5001T TDA1010A TDA1011A TDA1013B TDA1015 TDA1574 TDA1574T TDA1576T TDA5030A TDA7000

Balanced modulator/demodulator......................................................... Low-power FM IF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . � . . . . . . . . . . . . . . . . . RF dual gain-stage . . .. . . . . . . . . . . . . .. .. .. . .. . . . .. .. .. . . . . . . . . .. .. . . . .. .. . .. .. .. .. . .. .. . Wide-band high-frequency amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . � . . . . . . . . . . . . . . . . Wide-band high-frequency amplifier . . . .. . . .. . .. .. .. . . � .. .. . .. . . . .. .. . . . .. .. .. . .. .. . .. .. .. . Wideband variable gain amplifier . . . . . .. . . .. . .. .. . .. . . .. . . . . . .. . .. .. . . . .. .. .. . . . . . . .. .. .. . Wideband variable gain amplifier . . . . . .. . . . . . .. . . .. . . . .. . . . .. .. . . . . . .. .. . .. .. . . . . . .. . .. . . . Matched quad hi~h-performance low-voltage operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High frequency operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Video amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Compandor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable analog compandor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low voltage compandor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low voltage compandor in shrink small outline package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Audio processor - companding and amplifier section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Audio processor - filter and control section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low power compandor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . � . . . . . . . . . . . Unity gain level programmable power compandor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unity gain level programmable low power compandor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Video amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Double-balanced mixer and oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .. .. .. . High performance low power FM IF system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High performance low power mixer FM IF system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High performance low power mixer FM IF system in shrink small outline package . . . . . . . . . . . . . . . . . . . Low-voltage high performance mixer FM IF system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low voltage high performance mixer FM IF system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Double-balanced mixer and oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low power FM IF system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High performance low power mixer FM IF system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High performance low power mixer FM IF system in shrink small outline package . . . . . . . . . . . . . . . . . . . Low-voltage high performance mixer FM IF system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-voltage high performance mixer FM IF system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single-pole doulbe-throw switch (SPOT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Divide by: 128/129-64165 dual modulus low power EGL prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Divide by: 64/65/72 triple modulus low power EGL prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . Divide by: 128/129/144 triple modulus low power EGL prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Paging decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . POCSAG paging decoder with EEPROM storage . .. . .. .. . . .. . .. . . . . . .. .. . .. . . .. . . . .. .. . .. .. . SW audio amplifier with preamplifier .. . . . . . .. . .. .. .. . . . . . .. . . . .. . . . . . . . . . . . . .. . . . . . . .. .. .. . 2 to 6W audio power amplifier with preamplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4W amplifier with DC volume control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 to 4W audio amplifier with preamplifier . : . . .. . . .. .. . .. . . . .. .. . . . .. .. .. . .. .. . .. .. . . .. . . . .. . FM front-end IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Integrated FM tuner for radio receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FM/IF amplifier/demodulator circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TV VHF mixer/oscillator UHF preamplifier . . .. . .. . . . .. .. . . . . . . . .. . . . . . . . .. . . . .. . .. .. . .. .. .. . Single-chip FM radio circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

461 243
3 15 25 35 50
63 91 99 167 199 198 208 521 528 219 221 225 94 470 246 280 290 346 378 478 256 299 308 362 392 835 629 633 637 558 577 102 130 138 120 496 504 406 513 442

December 1991

viii

Signetics RF Communications
Alphanumeric product list

TDA7021T TDA7052 TDA7052A TDA7056A TDD1742T TEA6300 TSA5511 TSA6057/T UMF1000T UMF1005T UMF1009T UMA1014T

Single-chip FM radio circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449

1 Watt low voltage audio power amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

1-Watt low voltage audio power amp with DC volume control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

3-Watt mono BTL audio output amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

CMOS frequency synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641

Sound fader control circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . 579

1.3GHz bi-directional 12C bus controlled synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672

Radio tuning PLL frequency synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663

Data processor for cellular radio (DPROC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595

Low-power frequency synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697

Low power frequency synthesizer for radio communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746

Frequency synthesizer for cellular radio communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683

December 1991

ix

Slgnetlcs RF Communications
Ordering Information

LINEAR PRODUCTS PART NUMBERING SYSTEM
-l Example: ~ ~X

~------

Package Description: A Plastic Leaded Chip Carriers (PLCC)
D Plastic SO F Ceramic Dual In-Line G Hermetic Chip Carriers - Leadless H Headers
N Plastic Dual In-Line P Pin Grid Array - Hermetic W = Hermetic Cerpac Y = Ceramic Square Quad Flat Pack

Device Number

Device Family and Temperature Range Prefix
AU -40�C to +125�C NE Oto +70�C
SE -55�C to +12s0 c
SA -40�C to +80�C

PHILIPS PRODUCTS PART NUMBERING SYSTEM PREFIXES HE, PC, PN, SA, TD, TE, TS, UM

~ c p Device Fam:x_a_m_p-le_:_J__.D A

N

Package Description:

N

Plastic Dual In-Line

HEx CMOS Circuit PCx CMOS Circuit PNx NMOS Circuit

D

Plastic SO

F = Ceramic Dual In-Line

U = Plastic Single In-Line

SAx

Digital Circuit

Package Marking on Part:

TDx Linear Circuit

P

Plastic Dual In-Line

TEx

Linear Circuit

T = PlasticSO

TSx

Analog Circuit

D = Hermetic Cerdip

UMx Digital Circuit

Device Number

Operating Temperatures: A Temperature range not specified (see data sheet) B Oto +70�C C -55�C to +125�C D -25�C to +10�c E -25�C to +85�C F -40�C to +85�C

December 1991

x

Signetics RF Communications

Section 1 Amplifiers

INDEX

RF Amplifier Selector Guide

.......... 2

NE/SA5200 RF dual gain-stage . . .

3

NE/SA5204 Wide-band high-frequency amplifier.. . . . . . . . . . . . . . . . . . . . . 15

NE/SA5205 Wide-band high-frequency amplifier . . .

. . . . . . . . . . . . . 25

NE/SA5209 Wideband variable gain amplifier . . . . . . . . . .

35

NE/SA5219 Wideband variable gain amplifier . .

50

NE/SA5234 Matched quad hi~h-performance low-voltage

operational amplifier . . . . . . . . . . . . . . . . . . .

63

AN1651

Using the NE/SA5234 amplifier .

67

NE/SE5539 High frequency operational amplifier

81

NE5592

Video amplifier .

89

NE/SA/SE592 Video amplifier . .

94

TDA1010A

6W audio amplifier with preamplifier

102

TDA1015

1 to4Waudioamplifierwith preamplifier

120

TDA1011A

2 to 6W audio power amplifier with preamplifier. . . . . . .

130

TDA1013B

4Wamplifierwith DC volume control . . . . . .

138

TDA7052

1 Watt low voltage audio power amplifier . . .

146

TDA7052A

1-Watt low voltage audio power amp with

DC volume control

151

TDA7056A

3-Watt mono BTL audio output amplifier

158

~ id!
Vee

RF AMPLIFIER FAMILY OVERVIEW

;..t..i
g
3

(I)
(Q"
::J
c~;�

3

en

c

:c:J;�

NE5200

NE5204

NE5205

NE5209

NE5219

so.�

4-9V

5-SV

5-SV

4.5-7.0V

4.5-7.0V

e::nJ

'cc

8mA/95�A

24mA

24mA

43mA

43mA

Bandwidth (3dB)

1.2GHz

550MHz

550MHz

850MHz

700MHz

Noise Figure

3.6dB

6.0dB 50 Q 4.8dB 750

6.0dB 50 Q 4.8dB 75 Q

9.3dB

9.3dB

.:X,,J

ioduBtpCuot)mpression

"'

rcorudtOpurdt)er Intercept

-6dBm +4dBm

+4dBm +17dBm

+4dBm +17dBm

-3dBm +13dBm

-3dBm +13dBm

,,)>
3
3-i

Input Impedance Output Impedance

SOQ 50Q

son

50Q

1.2kQ

1.2kQ

50Q

50Q

60Q

60Q

CD
-e""n'
CD CD

Gain (per amplifier)

7.5dBH3dB

19dB

19dB

25dB*

25dB*

.(.'.)..
0

""'

Package Features

S08 +Dual Gain Stage

DsoIPsS
+Low-cost amp

DsoIPsS
+Low-cost amp

DIP16 S016

DIP16 S016

+Variable gain and +Variable gain and

G')
cc-�.

+Enable Pin

+Simple

+Simple

attenuation

attentuation

CD

+Good Noise Figure Implementation Implementation +Excellent Linearity +Excellent Linearity

+Low current

consumption

�single in I Differential out

Slgnetlcs RF Communications
RF dual gain-stage

Product speclflcslion
NE/SA5200

DESCRIPTION The NE/SA5200 is a dual amplifier with DC to 1200MHz response. Low noise (NF= 3.6dB) makes this part ideal for RF front-ends, and a simple power-down mode saves current for battery operated equipment. Inputs and outputs are matched to 50.Q.
The enable pin allows the designer the ability to tum the amplifiers on or off, allowing the part to act as an amplifier as well as an attenuator. This is very useful for front-end buffering in receiver applications.

FEATURES � Dual amplifiers � DC - 1200MHz operation � Low DC power consumption (4.2mA per
amplifier@ Vee = 5V) � Power-Down Mode (Ice= 95�A typical) � 3.6dB noise figure at 900MHz � Unconditionally stable � Fully ESD protected �Low cost � Supply voltage 4-9V
� Gain 8:?1 = 7dB at f = 1GHz
� Input and output match S11 , S22 typically <-14dB

ORDERING INFORMATION DESCRIPTION
8-Pin Plastic SO (Surface-mount) 8-Pin Plastic SO (Surface-mount)

TEMPERATURE RANGE 0-10�c
--40-+85�C

ORDER CODE NE5200D SA5200D

BLOCK DIAGRAM

PIN CONFIGURATION

DPackage

Vcco8 OUT1

OUT2 2

7 GNDt

GND2 3

6 IN1

IN2 4

5 ENABLE

APPLICATIONS � Cellular radios �RF IF strips � Portable equipment

Vee
1

ENABLE

GND1

ABSOLUTE MAXIMUM RATINGS

SYMBOL

PARAMETER

Vee Supply voltage 1

Po

Power dissipation, TA= 25�C (still air)2 8-Pin Plastic SO

TJMAX PuAX

Maximum operating junction temperature Maximum power input/output

Tsro Storage temperature range

RATING -0.5 to +9
780 150 +20 -65 to +150

UNITS
v
mW
oc
dBm
oc

NOTE:

1. Transients exceeding 10.5V on Vee pin may damage product.

2. Maximum dissipation is determined by the operating ambient temperature and the thermal resistance, OJA:

8-Pin SO:

OJA= 158�C/W

October 10, 1991

3

853-1578 04270

Signetics RF Communications
RF dual gain-stage

Product specification
NE/SA5200

RECOMMENDED OPERATING CONDITIONS

SYMBOL

PARAMETER

Vee Supply voltage

Operating ambient temperature range

NE Grade

TA

SA Grade

Operating junction temperature

NE Grade

TJ

SA Grade

RATING 4.0 to 9.0
0 to +70 -40 to +8S
0 to +90
-40to +10S

UNITS
v
oc oc oc oc

DC ELECTRICAL CHARACTERISTICS Vee= +SV, TA= 2S'C; unless otherwise stated.

SYMBOL

PARAMETER

TEST CONDITIONS

Yee Supply voltage

Ice

Total supply current

Yee= SV, ENABLE= High
Vee= SV, ENABLE =Low

Yee= 9V, ENABLE= High

Vee= 9V, ENABLE= Low

Yr

TIUCMOS logic threshold voltage 1

V1H

Logic 1 level

Power-up mode

V1L

Logic 0 level

l1L

Enable input current

l1H

Enable input current

Power-down mode
Enable =0.4V Enable =2.4V

Y10C.ODC Input and output DC levels

NOTE: 1. The ENABLE input must be connected to a valid logic level for proper operation of the NE/SAS200.

LIMITS

UNITS

MIN

TYP

MAX

4

s.o

9.0

v

6.4

8.4

10.4

mA

9S

2SS

�A

17.8

22.2

mA

320

960

�A

1.2S

v

2.0

Vee

v

-0.3

0.8

v

-1

0

1

�A

-1

0

1

�A

0.6

0.83

1.0

v

AC ELECTRICAL CHARACTERISTICS1 Vee= +SV, TA= 2s0 c, either amplifier, enable= SV; unless otherwise stated.

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

$21 Insertion gain

f =100MHz

MIN

TYP

MAX

9.2

11

13.2

f =900MHz

S.2

7.S

$22 Output return loss

f =900MHz

-14.3

$12 Reverse isolation

f =900MHz

-17.9

$11

Input return loss

f =900MHz

-16.S

P-1

Output 1dB compression point

f =900MHz

--4.3

NF

Noise figure in 50Q

f =900MHz

3.6

IP2 Input second-order intercept point

f =900MHz

+4.3

IP3 ISOL

Input third-order intercept point Amplifier-to-amplifier isolation2

f =900MHz

-'1.8

f =900MHz

-2S

Pour $21

Saturated output power Insertion gain when disabled

f =900MHz
f =100MHz

-1.7 -13

f =900MHz

-13.S

NOTE: 1. All measurements include the effects of the NE/SAS200 Evaluation Board (see Figure 2). Measurement system impedance is son. 2. Input applied to one amplifier, output taken at the other output. All ports terminated into son.

UNITS
dB dB dB dB dB dBm dB dBm dBm dB dBm dB dB

October 1O, 1991

4

Signetics RF Communications
RF dual gain-stage

Product specification
NE/SA5200

APPLICATIONS
NE/SAS200 is a user-friendly, wide-band, unconditionally stable, low power dual gain amplifier circuit. There are several advantages to using the NE/SAS200 as a high frequency gain block instead of a discrete implementation. First is the simplicity of use. The NE/SAS200 does not need any external biasing components. Due to the higher level of integration and small footprint (SOS) package it occupies less space on the printed circuit board and reduces the manufacturing cost of the system. Also the higher level of integration improves the reliability of the amplifier over a discrete implementation with several components. The power down mode in the NE/SAS200 helps reduce power consumption in applications where the amplifiers can be disabled. And last but not the least is the impedance matching at inputs and outputs. Only those who have toiled through discrete
son transistor implementations for input and
output impedance matching can truly appreciate the elegance and simplicity of the NE/SAS200 input and output impedance
matching to son.
A simplified equivalent schematic is shown in Figure 1. Each amplifier is composed of an NPN transistor with an Ft of 13GHz in a classical series-shunt feedback configuration. The two wideband amplifiers are biased from the same bias generator. In nonmal operation each amplifier consumes about 4mA of quiescent current (at Vee = SV). In the disable mode the device consumes about 90�A of current, most of it is in the TTL enable buffer and the bias generator. The
son. input impedance of the amplifiers is
The amplifiers have typical gain of 11 dB at 1OOMHz and 7dB of gain at 1.2GHz.
It can be seen from Figure 1 that any inductance between Pin 7, 3 and the ground plane will reduce the gain of the amplifiers at higher frequencies. Thus proper grounding of Pins 7 and 3 is essential for maximum gain and increased frequency response. Figure 2

shows the printed circuit board layout and the component placement for the NE/SAS200 evaluation board. The AC coupling capacitors should be selected such that at they are shorts at the desired frequency of operation. Since most low-cost large value surface mount capacitors cease to be simply capacitors in the UHF range and exhibit an inductive behavior, it is recommended that high frequency chip capacitors be utilized in the circuit. A good power supply bypass is also essential for the performance of the amplifier and should be as close to the device as practical.
Figure 3 shows the typical frequency response of the two channels of NE/SAS200. The low frequency gain is about 11 dB at 1OOMHz and slowly drops off to 1OdB at SOOMHz. The gain is about 8dB at 900MHz and 7dB at 1.2 GHz which is typical of NE/SAS200 with a good printed circuit board layout. It can also be seen that both channels have a very well matched frequency response and matched gain to within 0.1dB at 100MHz and 0.2dB at 900MHz.
NE/SAS200 finds applications in many areas of RF communications. It is an ideal gain block for high performance, low cost, low power RF communications transceivers. A typical radio transceiver front-end is shown in Figure 4. This could be the front-end of a cellular phone, a VHF/ UHF hand-held transceiver, UHF cordless telephone or a spread spectrum system. The NE/SAS200 can be used in the receiver path of most systems as an LNA and pre-amplifier. The bandpass filter between the two amplifiers also minimize the noise into the first mixer. In the transmitter path, NE/SAS200 can be used as a buffer to the VCO and isolate the VCO from any load variations due to the power level changes in the power amplifier. This improves the stability of the VCOs. The NE/SAS200 can also be used as a pre-driver to the power amplifier modules.
The two amplifiers in NE/SAS200 can be easily cascaded to have a 13dB gain block at

900MHz. At 100MHz the gain will be 22dB and a noise figure of about S.SdB. The NE/SAS200 can be operated at a higher voltage up to 9V for much improved 1dB output compression point and higher 3rd order intercept point.
Several stages of NE/SAS200 can also be cascaded and be used as an IF amplifier strip for DBSfTV/GPS receivers. Figure S shows a 60dB gain IF strip at 180MHz. The noise figure for the cascaded amplifier chain is given by equation 1.
NF (total)= NF1 + NF2/G1 + NF3/G1.G2 + NF4/G1�G2'G3 + ... (Equation. 1)
NOTE: The noise figure and gain should not be in dB in the above equation.
Since the noise figure for each stage is about 3.6dB and the gain is about 11dB, the noise figure for the 60dB gain IF strip will be about 6.4dB.
In applications where a single amplifier is required with a 7.SdB gain at 900MHz and current consumption is of paramount importance (battery powered receivers), the amplifier A1 can be used and amplifier A2 can be disabled by leaving GND2 (Pin 3) unconnected. This will reduce the total current consumption for the IC to a meager 4mA.
The ENABLE pin is useful for Time-Division-Duplex systems where the receiver can be disabled for a period of time. In this case the overall system supply current will be decreased by 8mA.
The ENABLE pin can also be used to improve the system dynamic range. For input levels that are extremely high, the NE/SAS200 can be disabled. In this case the input signal is attenuated by 13dB. This prevents the system from being overloaded as well as improves the system's overall dynamic range. In the disabled condition the NE/SAS200 IP3 increases to nearly +20dBm.

October 10, 1991

s

Signetics RF Communications
RF dual gain-stage

Product specification
NE/SA5200

PIN 1 Vee

PIN 5o-------;.-.
ENABLE

BIAS GENERATOR

GND1

r----

1

I

PINS
.--'\,,..,,,__._~_,,

I

OUT1

PIN 6 o--~l,__.,__-C

IN1

I

I

I

L~~-- PIN 7

GND1

r----

1

I

I

PIN 4 0--__,l,__.,__-C

IN2

I

I

I

L~~-- PIN3

GND2

Figure 1. Simplified Equivalent Schematic of NE/SA5200

r.l~ (_:_)

0

(:)

(�)~(�)

'�''' �,'�' I...../

\...J

a. Top Side

� � . ~~( )
�x� ~t() ~

o~
<t.-..

0 Q

� � -:~< o.~ . 0

>: Cl "'

0

��

� � . -~~ o Qo 0.�1' �x� ~

'
~~ 00 O>~~
~"

c. Top Silk Screen

b. Bottom Side

IN2
~0.01�F

OUT2 r:1�F

Vee
I 0.1�F
1=

ENABLE
d. NE/SA5200 Evaluation Board Schematic

Figure 2. Printed Circuit Board Layout of the NE/SA5200 Evaluation Board

October 10, 1991

6

Signetics RF Communications
RF dual gain-stage

!- . CHANNEL1

~

Product specification
NE/SA5200
1: 11.t71dB, 10MHz 2: 10.049d81 SOOMHz 3: 8.2439dB, 850MHz 4: 6.9146dB, 1.2GHz

4'--~~~~-'-~~~'---~-'-~-'---'-~'--'---1-.J'--~~~~-'-~~--''--~-'--~'----'-~--'--'~~~--'

10

100

1000

FREQUENCY (MHz)

Figure 3. Typical Frequency Response of NE/SA5200 In a SOQ System

ANTENNA

IFOUT

October 10, 1991

Figure 4. Typical Radio Transceiver Front-End 7

vco
MODULATION

Signetics RF Communications
RF dual gain-stage

Product specification
NE/SA5200

Fl ure 5. 60dB IF Gain Block for 100-300MHz IF for GPS/DBS S stems

I'

450 -;----t----t----t----+-----i
112-+---1-----t---2l~---1t-----+-----I _B

Vcc(V)
Figure 6. Supply Current vs Supply Voltage and Temperature

so-+---t----+----1-----+-----i
Vcc(V)
Figure 7. Disabled Supply Current vs Vee and Temperature

October 10, 1991

8

Signetics RF Communications
RF dual gain-stage

Product specification
NE/SA5200

-8
-10
-12 iD ~ -14
:::
-16

+85"C +25�C -40"C

-18

TA"' +25"C

-20

10

100

1000 2000

10

FREQUENCY (MHz)

100 FREQUENCY (MHz)

1000 2000

Figure 8. Input Match vs Frequency and Vcc

Figure 9. Input Match vs Frequency and Temperature

10

100

1000 2000

FREQUENCY (MHz)

Figure 10. Insertion Gain vs Frequency and Vee

October 10, 1991

9

850 900 950 1000 1050 1100 1150 1200 FREQUENCY (MHz)
Figure 11. Insertion Gain vs Frequency and Vcc
- Expanded Detail -

Signetics RF Communications
RF dual gain-stage

Product specification
NE/SA5200

9.5 -+---t---+----lf---t---+--+---+----1

iii' E
Ns
"'
10

Vee� 5V
100 FREQUENCY (MHz)
Figure 12. Insertion Gain vs Frequency and Temperature

1000 2000

8.5 -+-----t.1~~--<"',__-4_0�G_+---+---+----+--+---<

R..--i--t ~
N
"'

7.5

-:l----f1_-........;::,r:::;'"'+""'25c::..'Ct-~~:+"'""""-:+---f--t---J
.~~

~ 6.5 .....o +---lf--+-~---t---t~ 1:---+"""-l

5.5 -+----lf---t---+--+---+--+---+---i
+ Vee� 5V
eoo eso goo 950 1000 1oso 1rno 11so 1200
FREQUENCY (MHz)

Figure 13. Insertion Gain vs Frequency and Temperature
- Expanded Detail -

12 11 10
""' '
10

~
~
-\ CH1

Vee� 5V TA= +25"C

1\
cl
1 ~

100 FREQUENCY (MHz)

1000 2000

-10
-12
-14 iii' E
N -16
"'
-18
-20
-22
10

Figure 14. Insertion Gain Matching (CH1 vs CH2) vs Frequency

~ +85"C

Vcc-5V

~

+25"

-40�C

100 FREQUENCY (MHz)

1000 2000

Figure 15. Reverse Insertion Gain vs Frequency and Temperature

October 10, 1991

10

Signetics RF Communications
RF dual gain-stage

Product specification
NE/SA5200

�10 -12

-14

-2s-+--------+---------+--'H

g: -16
"'
�18
-20

-22

10

100

1000 2000

10

FREQUENCY (MHz)

+85�C �25'.'.C. -40-C

~
~
1"""'""""'

Vcc-SV
100 FREQUENCY (MHz)

"''
1000 2000

Figure 16. Output Match vs Frequency and Vee

Figure 17. Output Match vs Frequency and Temperature

.0....,.--------,----------,----,

�10

S11

-10 - + - - - - - - - - 1 - - - - - - - - - + - - - l
S12
-20-+--------r----------+---t1

-15
1'i
"'
-20

�25

10

100

1000 2000

10

FREQUENCY (MHz)

CH2

~

CH1

~ _j

Vcc-SV TA�+25�C

100 FREQUENCY (MHz)

1000 2000

Figure 18. S-parameters vs Frequency for Disabled Amplifier

Figure 19. Insertion Gain Matching Disabled (CH1 vs CH2) vs Frequency

October 10, 1991

11

Signetics RF Communications
RF dual gain-stage

Product specification
NE/SA5200

-40 fil' E
""' ' -60

3.7-+---------+---------..~--i
uz .

10

100

1000 2000

FREQUENCY (MHz)

Figure 20. CH1 Input to CH2 Output Isolation vs Frequency

10

100

1000 2000

FREQUENCY (MHz)

Figure 21. Noise Figure vs Frequency and Vee In a 50Q System

TA� +25"0

10

100

1000 2000

FREQUENCY (MHz)

Figure 22. 1dB Output Compression Point vs Frequency and Vee

October 10, 1991

12

TA� +25"C

10

100

1000 2000

FREQUENCY (MHz)

Figure 23. Saturated Output Power vs Frequency and Vee

Signetics RF Communications
RF dual gain-stage

Product specification
NE/SA5200

16
14
12 10
E" ~
r;;,"'

100MHz

Vcc(VJ
Figure 24. Third-Order Output Intercept vs Frequency and Vee

20 - - - - - - - - - - - o;;J;LE,;- -
15

10
E" ~
r;;,"'

v

v---

1�900MHz TA� +25"C

.....

�5

T

Vee (VJ

Figure 25. Third-Order Input Intercept vs Frequency and Vcc

TA .. +25"C
Vcc(VJ Figure 26. Second-Order Output Intercept
vs Frequency and Vcc

TA .. +25"'C I
f �900MHz
4
vcc(VJ
Figure 27. Second-Order Input Intercept vs Frequency and Vee

October 10, 1991

13

Signetics RF Communications
RF dual gain-stage

Product specification
NE/SA5200

= = Figure 28. Switching Speed; 11N 10MHz at -26dBm, V00 SV,
Coupling Capacitors Set to 0.01 �F

= Figure 29. Switching Speed; !1N SOMHz at -26dBm, = Voo SV, Coupling Capacitors Set to 100pF

October 10, 1991

14

Signetics RF Communications
Wide-band high-frequency amplifier

Product specification
NE/SA5204

DESCRIPTION
The NE/SAS204 is a high-frequency amplifier with a fixed insertion gain of 20dB. The gain is flat to �0.SdB from DC to 200MHz. The -3dB bandwidth is greater than 3SOMHz. This performance makes the amplifier ideal for cable TV applications. The NE/SAS204 operates with a single supply of 6V, and only draws 2SmA of supply current, which is much less than comparable hybrid parts. The noise figure is 4.8dB in a 7Sn system and 6dB in a son system.
The NE/SAS204 is a relaxed version of the NES20S. Minimum guaranteed bandwidth is relaxed to 3SOMHz and the "S" parameter Min/Max limits are specified as typicals only.
Until now, most RF or high-frequency designers had to settle for discrete or hybrid solutions to their amplification problems. Most of these solutions required trade-offs that the designer had to accept in order to use high-frequency gain stages. These include high power consumption, large component count, transformers, large packages with heat sinks, and high part cost. The NE/SAS204 solves these problems by incorporating a wideband amplifier on a single monolithic chip.
The part is well matched to SO or 7Sn input and output impedances. The standing wave ratios in SO and 7Sn systems do not exceed 1.S on either the input or output over the entire DC to 3SOMHz operating range.
Since the part is a small, monolithic IC die, problems such as stray capacitance are minimized. The die size is small enough to fit into a very cost-effective 8-pin small-outline (SO) package to further reduce parasitic effects.

NE/SAS204 is internally compensated and matched to SO and 7Sn. The amplifier has very good distortion specifications, with second and third-order intermodulation intercepts of +24dBm and+ 17dBm, respectively, at 100MHz.
The part is well matched for son test equipment such as signal generators, oscilloscopes, frequency counters, and all kinds of signal analyzers. Other applications at son include mobile radio, CB radio, and data/video transmission in fiber optics, as well as broadband LANs and telecom systems. A gain greater than 20dB can be achieved by cascading additional NE/SAS204s in series as required, without any degradation in amplifier stability.
FEATURES
� Bandwidth (min.) 200 MHz, �0.SdB 3SO MHz, -3dB
� 20dB insertion gain
� 4.8dB (6dB) noise figure Z0=7Sn (ZO=SOn)
� No external components required
� Input and output impedances matched to S0/7Sn systems
� Surface-mount package available
� Cascadable

No external components are needed other than AC-coupling capacitors because the
ORDERING INFORMATION

DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

8-Pin Plastic DIP 8-Pin Plastic SO package

Oto +70�C -40 to +8S�C
o to +70�C
-40 to +8S�C

NES204N SAS204N
NES204D SAS204D

PIN CONFIGURATION
N, D Packages
TOP VIEW
APPLICATIONS
� Antenna amplifiers � Amplified splitters � Signal generators � Frequency counters � Oscilloscopes � Signal analyzers � Broadband LANs �Networks �Modems � Mobile radio �Security systems � Telecommunications

November 3, 1987

1S

8S3-1191 91260

Signetics RF Communications
Wide-band high-frequency amplifier

ABSOLUTE MAXIMUM RATINGS

SYMBOL

PARAMETER

Vee

Supply voltage

V1N

AC input voltage

TA

Operating ambient temperature range

NE grade

SA grade

PoMAX

Maximum power dissipation 1, 2 TA=25�C(still-air)

N package

D package

TJ

Junction temperature

Tsm

Storage temperature range

TsoLo

Lead temperature (soldering 60s)

NOTES: 1. Derate above 25�C, at the following rates
N package at 9.3mW/�C D package at 6.2mW/�C 2. See "Power Dissipation Considerations" section.

EQUIVALENT SCHEMATIC

RATING 9 5
0 to +70 -40 to +85
1160 780 150 -55 to +150 300

UNIT
v
Vp_p
oc oc
mW mW
oc oc oc

Vee

Product specification
NE/SA5204

November 3, 1987

16

Signetics RF Communications
Wide-band high-frequency amplifier

Product specification
NE/SA5204

DC ELECTRICAL CHARACTERISTICS
Vcc=6V, Zs=ZL=Zo=50Q and TA=25�C, in all packages, unless otherwise specified.

SYMBOL

PARAMETER

TEST CONDITIONS

Vee

Operating supply voltage range

Ice

Supply current

S21

Insertion gain

S11

Input return loss

S22

Output return loss

S12

Isolation

BW

Bandwidth

BW

Bandwidth

Noise figure (75Q)

Noise figure (SOQ)

Saturated output power

1dB gain compression

Third-order intermodulation intercept (output}

Second-order intermodulation intercept (output}

tR

Rise time

Propagation delay

Over temperature Over temperature 1=100MHz, over temperature
1=100MHz DC--050MHz
1=100MHz DC--050MHz
1=100MHz DC--050MHz
�0.SdB -3dB 1=100MHz 1=100MHz 1=100MHz 1=100MHz
1=100MHz
f=100MHz

LIMITS

Min Typ Max

5

8

19

24

31

16

19

22

25

12

27

12

-25

-18

200 350

350 550

4.8

6.0

+7.0

+4.0

+17

+24
5 5

UNIT
v
mA dB dB dB dB dB dB dB MHz MHz dB dB dBm dBm
dBm
dBm
ps ps

35 34

!"" 32

30

aazw::

1---
28 26

TA= 25�C

::>

...0
::;

24

0. 22

:;;2l

::>

(/) 20 / I

18

17'
:;;ii

16 5.5

6.5

7

SUPPLY VOLTAGE-V

:;;ii 7.5

Figure 1. Supply Current vs Supply Voltage

.E, B
l
a:
::>
"a: 7
w
(/)
Cz 5

Vee= 8v Vee= 7v Yee= 6v Yee= Sv

5 101

4 6 B 1o2
FREQUENCY-MHz
Figure 2. Noise Figure vs Frequency

November 3, 1987

17

Signetics RF Communications
Wide-band high-frequency amplifier

Product specification
NE/SA5204

10'---IL---L--'----"-...___ __,__ _,___.__._,

101

4 6 8 102 2

FREQUENCY-MHz

Figure 3. Insertion Gain vs Frequency (S21)

101

6 8 102

6 8 103

FREQUENCY-MHz

Figure 5. Saturated Output Power vs Frequency

.,E 40

! 35

aw .

aw><.>:- 30

:!ii aw :

25

~aQ: 20
z

8w 15

(/)

10

....< ~
1Zl lZl

IL L

Zo= son
l_Aj_25'.'.;_
I �

4

10

POWER SUPPLY VOLTAGE-V

Figure 7. Second-Order Output Intercept vs Supply Voltage

=:"" Vee= av --t--t-+-lf--+---+--t-t-1
Zo --+--+-.l+-.l..__.1+--t----+-t-i

10 101

6 8 102 2 FREQUENCY-MHz

Figure 4. Insertion Gain vs Frequency (S21)

:S. Vee.av

t- Vcc.&V
b_ Vcc.5V

......

z Vee. 7V

-......:

~ ::s: t!>..
IS ho.

I
t-- Zo= son
f== ~:25'~

""' .......

="" ~ t!i..

~

!'!..

6 8 102 FREQUENCY-MHz
Figure 6. 1dB Gain Compression vs Frequency

POWER SUPPLY VOLTAGE-V
Figure 8. Third-Order Intercept vs Supply Voltage

November 3, 1987

18

Signetics RF Communications
Wide-band high-frequency amplifier

2.0

1.9

I== 1.8 t-- TA=25�C

1.7

;_cc=6V

0:

ll:
g,_?

1.6 1.5

0.
";;!;

1.4

I= 1.3

Zo = 75Il

1.2
I- Zo= 50Q
1.1

�
'LL :...
~

1.0 101

4 s e 102
FREQUENCY-MHz

Figure 9. Input VSWR vs Frequency

40

1l 35

1-........ "g' .i.s.. 30
z ~ ~ ~ 25

~to- ~ " OUTPUT

e: ~ " ~,_

20

r--

Vcc=6V Zo= 50Q

"0. ,0_.
~...... :!: 5 15

TA=25�C

J_NPUT

r-
~ b

6 8 102

6 8103

FREQUENCY-MHz
Figure 11. Input (S11) and Output (S22) Return Loss vs Frequency

25
Jt:zl--H J �cc=Bv,~
�cc= 7v

~ �"

z ~ h..

Yee= 6v

_L _),_~

Vee= Sv .L

.llll

l= Zo= 75"

t-- Tj_= 25'CJ.
10

I l

101

6 8 102

FREQUENCY-MHz

Figure 13. Insertion Gain vs Frequency (S21)

Product specification
NE/SA5204

2.0

1.9

I== 1.8

Tamb = 25'C

a: 1.7 t - - Vee= 6V

ill 1.6

> ... 1.5

"~ 1.4
:= 1.3 Zo:75.Il

I= 1.2
1.1 Zo = SOQ

"J. LL
-2 ~

1.0 101 FREQUENCY-MHz
Figure 10. Output VSWR vs Frequency

10

11 I

-15
~

Zo= 50Il TA= 2s0 c Vee =6V

gi::-20
-25

...- .--~

6 8 10� FREQUENCY-MHz
Figure 12. Isolation vs Frequency (S,.)

25

t--t---

Zo = 75"

I - - Vcc=t

J:
TA :-55�C
I TA=25'C

~

Lr TA=85'C

~
L_ ~~'

TA= 12s�C

~

~

10 101

6 8 102 FREQUENCY-MHz

Figure 14. Insertion Gain vs Frequency (S21)

November 3, 1987

19

Signetics RF Communications
Wide-band high-frequency amplifier

Product specification
NE/SA5204

THEORY OF OPERATION
The design is based on the use of multiple feedback loops to provide wide-band gain together with good noise figure and terminal impedance matches. Referring to the circuit schematic in Figure 15, the gain is set primarily by the equation:
(1)
which is series-shunt feedback. There is also shunt-series feedback due to RF2 and RE2 which aids in producing wide-band terminal impedances without the need for low value input shunting resistors that would degrade the noise figure. For optimum noise performance, RE1 and the base resistance of 0 1are kept as low as possible, while RF2 is maximized. The noise figure is given by the following equation:
where lc1=5.5mA, RE1=12Q, rb=130Q,
son KTiq=26mV at 25�C and Ro=50 for a
system and 75 for a 75Q system.

The DC input voltage level ViN can be determined by the equation:
V1N=VsE1+(lc1+ic3) RE1(3)
where RE1=12n, VsE=O.BV, ic1=5mA and lc3=7mA (currents rated at Vcc=6V).
Under the above conditions, V1N is approximately equal to 1V.
Level shifting is achieved by emitter-follower 03 and diode 0 4, which provide shunt feedback to the emitter of 0 1 via RF1. The use of an emitter-follower buffer in this feedback loop essentially eliminates problems of shunt-feedback loading on the output. The value of RF1=140Q is chosen to give the desired nominal gain. The DC output voltage Your can be determined by:
Vour=Vcc-{b+lcs)R2,(4)
where Vcc=6V, R2=225Q, lc2=7mA and lc6=5mA.
From here, it can be seen that the output voltage is approximately 3.3V to give relatively equal positive and negative output swings. Diode 0 5 is included for bias purposes to allow direct coupling of RF2 to the base of 0 1. The dual feedback loops stabilize the DC operating point of the amplifier.
The output stage is a Darlington pair (06 and 0 2) which increases the DC bias voltage on

the input stage (01) to a more desirable value, and also increases the feedback loop gain. Resistor Ro optimizes the output VSWR (Voltage Standing Wave Ratio). Inductors L1 and L2 are bondwire and lead inductances which are roughly 3nH. These improve the high-frequency impedance matches at input and output by partially resonating with O.SpF of pad and package capacitance.
POWER DISSIPATION CONSIDERATIONS
When using the part at elevated temperature, the engineer should consider the power dissipation capabilities of each package.
At the nominal supply voltage of 6V, the typical supply current is 25mA (30mA max). For operation at supply voltages other than 6V, see Figure 1 for Ice versus Vee curves. The supply current is inversely proportional to temperature and varies no more than 1mA between 25�C and either temperature extreme. The change is 0.1 % per �C over the range.
The recommended operating temperature ranges are air-mount specifications. Better heat-sinking benefits can be realized by mounting the SO and N package bodies against the PC board plane.

Vee

R2

225 RO

L2

Your

November 3, 1987

140 RE1
12
RF2

RE2
12
Q5

Figure 15. Schematic Diagram

20

Signetics RF Communications
Wide-band high-frequency amplifier

Product specification
NE/SA5204

PC BOARD MOUNTING
In order to realize satisfactory mounting of the NE5204 to a PC board, certain techniques need to be utilized. The board must be double-sided with copper and all pins must be soldered to their respective areas (i.e., all GND and Vee pins on the package). The power supply should be decoupled with a capacitor as close to the Vee pins as possible, and an RF choke should be inserted between the supply and the device. Caution should be exercised in the connection of input and output pins. Standard microstrip should be observed wherever possible. There should be no solder bumps or burrs or any obstructions in the signal path to cause launching problems. The path should be as straight as possible and lead lengths as short as possible from the part to the cable connection. Another important consideration is that the input and output should be

AC-coupled. This is because at Vcc=6V, the input is approximately at 1V while the output is at 3.3V. The output must be decoupled into a low-impedance system, or the DC bias on the output of the amplifier will be loaded down, causing los.s of output power. The easiest way to decouple the entire amplifier is by soldering a high-frequency chip capacitor directly to the input and output pins of the device. This circuit is shown in Figure 16. Follow these recommendations to get the best frequency response and noise immunity. The board design is as important as the integrated circuit design itself.
SCATTERING PARAMETERS
The primary specifications for the NE5204 are listed as $-parameters. $-parameters are measurements of incident and reflected currents and voltages between the source,

Vee
1--o VouT
AC COUP UNG CAPACITOR
Figure 16. Circuit Schematic for Coupling and Power Supply Decoupling amplifier, and load as well as transmission losses. The parameters for a two-port network are defined in Figure 17.

S11 - INPUT RETURN LOSS

POWER REFLECTED FROM INPUT PORT
POWER AVAILABLE FROM GENERATOR AT INPUT PORT

a. Two-Port Network Defined

S12- REVERSE TRANSMISSION LOSS OSOLATION

S21 - FORWARD TRANSMISSION LOSS OR INSERTION GAIN
S22- OUTPUT RETURN LOSS

'\J S21 � TRANSDUCER POWER GAIN

822=

POWER REFLECTED FROM OUTPUT PORT
POWER AVAILABLE FROM GENERAIDR AT OUTPUT PORT

b. Figure 17.

November 3, 1987

21

Signetics RF Communications
Wide-band high-frequency amplifier

Product specification
NE/SA5204

son system

I I

l viii rf:iH 1---+----+-_..._,_..,__--+-- Yee= av ~

20 t----+-----ir--+-+-t--1

7v

~

~;:pi'l

j!i

�cc =6v 2::-T--:ll'll~tt't--1

W 1s

�ccisv L-+-.-1-1

-z

1--- Zo = son --+--+-11----+---+-_...._.._,

I== 10

lTA= 2s�c .-+--t-il----+--+--t--t--l
_L

101

4 6 8 102

FREQUENCY-MHz

a. Insertion Gain vs Frequency (S21)

75nSystem

25

E
I

n ~ I Ycc=8Y
Vcc=7v t-t-

:== Zo=750
J-- T.r25'C
10 101

_L !"!..

Yee= &v

_]J

Vee= Sv _L

�� ll

FREQUENCY-MHz

b. Insertion Gain vs Frequency (S2,)

10
F -.25

-IL.J
TA= 25-C Vcc=&V
_..... ~
....-

-30 101

4 6 8 102

4 6 8 103

FREQUENCY-MHz

c. lsolatlon vs Frequency (S12)

10

ILJ

TA=25�C

Vcc=&V

II

~

J7

-30

101

4 6 8 102

FREQUENCY-MHz

d. S12 lsolstlon vs Frequency

6 8 103

40

r-....J

~~OUTPUT

t-- Vcc=&V
Zo=SO<l
TA=25'C

10

101

'

~ ~

"""" ~ J_NPUT

,..... DI

6 8 102

FREQUENCY-MHz

e. Input (S11) and Output (Szz) Return Lo88 vs Frequency Figure 18.

I - -t- 0U_1'UT
:I
INPUT

~ ~
~ ~ Vcc��V

Zo�750 lA=25�C

"

'68102 2

FREQUENCY--
f. Input ($11) and Output ($22) Return Loas vs Frequency

November 3, 1987

22

Signetics RF Communications
Wide-band high-frequency amplifier

Product specification
NE/SA5204

Actual S-parameter measurements using an HP network analyzer (model 8505A) and an HP S-parameter tester (models 8503A/B) are shown in Figure 18.

Values for the figures below are measured

and specified in the data sheet to ease

adaptation and comparison of the

NE/SA/SE5205 to other high-frequency

amplifiers.

The most important parameter is S21 . It is

defined as the square root of the power gain,

and, in decibels, is equal to voltage gain as

shown below:

:CJ: ZD=Z1N=Zour for the NE/SA/SE5205

PJN + -V1-1i Zo

Pour+ -V2o-ouf

Vouf Pour ~ Vouf = Pi
:. P1N = v,if = v,if ZiJ
P1=V1 2 P1=1nsertion Power Gain V1=lnsertion Voltage Gain Measured value for the NE/SA/SE5205 = IS211 2 =100
... P1 = PPo1Nur = I Sz1 I 2 = 100
and V1 = Vour = ./P, = Sz1 = 10
VIN

In decibels: P1(dB) =10 Log I S21 I 2 = 20dB V1(dB) = 20 Log S21 = 20dB :. P1(dB) = Vl(dB) = S21(dB) = 20dB
Also measured on the same system are the respective voltage standing wave ratios. These are shown in Figure 19. The VSWR

can be seen to be below 1.5 across the entire operational frequency range.
Relationships exist between the input and output return losses and the voltage standing wave ratios. These relationships are as follows:
INPUT RETURN LOSS=S11dB
S11dB=20 Log I S11 I
OUTPUT RETURN LOSS=S22dB S22dB=20 Log I S22 I
IN PUT VSWR=51.5 OUTPUT VSWR=51.5
1DB GAIN COMPRESSION AND SATURATED OUTPUT POWER
The 1dB gain compression is a measurement of the output power level where the small-signal insertion gain magnitude decreases 1dB from its low power value. The decrease is due to nonlinearities in the amplifier, an indication of the point of transition between small-signal operation and the large signal mode.
The saturated output power is a measure of the amplifier's ability to deliver power into an external load. It is the value of the amplifier's output power when the input is heavily overdriven. This includes the sum of the power in all harmonics.
INTERMODULATION INTERCEPT TESTS
The intermodulation intercept is an expression of the low level linearity of the amplifier. The intermodulation ratio is the difference in dB between the fundamental output signal level and the generated distortion product level. The relationship between intercept and intermodulation ratio is illustrated in Figure 20, which shows product output levels plotted versus the level of the fundamental output for two equal strength

output signals at different frequencies. The upper line shows the fundamental output plotted against itself with a 1dB to 1dB slope. The second and third order products lie below the fundamentals and exhibit a 2:1 and 3:1 slope, respectively.
The intercept point for either product is the intersection of the extensions of the product curve with the fundamental output.
The intercept point is determined by measuring the intermodulation ratio at a single output level and projecting along the appropriate product slope to the point of intersection with the fundamental. When the intercept point is known, the intermodulation ratio can be determined by the reverse process. The second order IMR is equal to the difference between the second order intercept and the fundamental output level. The third order IMR is equal to twice the difference between the third order intercept and the fundamental output level. These are expressed as:
IP2=Pour+IMR2
IP3=Pour+IM~2
where Pour is the power level in dBm of each of a pair of equal level fundamental output signals, IP2 and IP3 are the second and third order output intercepts in dBm, and IMR2 and IMR3 are the second and third order intermodulation ratios in dB. The intermodulation intercept is an indicator of intermodulation performance only in the small signal operating range of the amplifier. Above some output level which is below the 1dB compression point, the active device moves into large-signal operation. At this point the intermodulation products no longer follow the straight line output slopes, and the intercept description is no longer valid. It is therefore important to measure IP2 and IP3 at output levels well below 1dB compression. One

2.0

1.9

I== 1.8 f-- TA=25�C

~ 1.7

Vcc=&V

g,? 1.6

~ 1.5
:! 1.4
1.3
1.2
1.1

Zo= 75Q Zo= 50<2

1.
IZZ !'I:

1.0 10'

6 8102 FREQUENCY-MHz

2.0

1.9

::: I== 1.8

Tamb = 25'C

~ I== Vcc=&V

~I- 1.5 1A

1.3 Zo = 75"

1.2

rT

1.1 Zo=SO!l

1.0 101

4 � 81a2

4 6 8103

FREQUENCY-MHz

a. Input VSWR vs Frequency

b. Output VSWR vs Frequency

Figure 19. Input/Output VSWR vs Frequency

November 3, 1987

23

Signetics RF Communications
Wide-band high-frequency amplifier

Product specification
NE/SA5204

must be careful, however, not to select too

low levels because the test equipment may

not be able to recover the signal from the

+30

noise. For the NE/SA/SE5205 we have

THIRD ORDER

2ND ORDER

chosen an output level of-10.5dBm with fundamental frequencies of 100.000 and

+20

INTERCEPT POINT

I

I

I

1dB

INTERCEPT POINT

100.01 MHz, respectively. *5COL
ADDITIONAL READING ON

+10

COMPRESSION POINT
I I

I�

SCATTERING PARAMETERS

FUNDAMENTAL RESPONSE

For more information regarding

$-parameters, please refer to

High-Frequency Amplifiers by Ralph S. Carson of the University of Missouri, Rolla, Copyright 1985; published by John Wiley & Sons, Inc.
"$-Parameter Techniques for Faster, More

2ND ORDER RESPONSE
I I
3RDORDER RESPONSE

Accurate Network Design", HP App Note 95-1,

Richard W. Anderson, 1967, HP Journal. "$-Parameter Design", HP App Note 154,

.00 -50 40 -30 -20 -10

0

+10 +20 +30 +40

INPUT LEVEL dBm

1972.

Figure 20.

November 3, 1987

24

Slgnetics RF Communications
Wide-band high-frequency amplifier

Product specification
NE/SA5205

DESCRIPTION
The NE/SA/SES20S is a high-frequency amplifier with a fixed insertion gain of 20dB. The gain is flat to �0.SdB from DC to 4SOMHz, and the -3dB bandwidth is greater than 600MHz in the EC package. This performance makes the amplifier ideal for cable TV applications. For lower frequency applications, the part is also available in industrial standard dual in-line and small outline packages. The NE/SNSES20S operates with a single supply of 6V, and only draws 24mA of supply current, which is much less than comparable hybrid parts. The noise figure is 4.8dB in a ?SQ system and 6dB in a SOQ system.
Until now, most RF or high-frequency designers had to settle for discrete or hybrid solutions to their amplification problems. Most of these solutions required trade-offs that the designer had to accept in order to use high-frequency gain stages. These include high-power consumption, large component count, transformers, large packages with heat sinks, and high part cost. The NE/SNSES20S solves these problems by incorporating a wide-band amplifier on a single monolithic chip.
The part is well matched to SO or ?SQ input and output impedances. The Standing Wave Ratios in SO and ?SQ systems do not exceed 1.S on either the input or output from DC to the -3dB bandwidth limit.
Since the part is a small monolithic IC die, problems such as stray capacitance are minimized. The die size is small enough to fit into a very cost-effective 8-pin small-outline (SO) package to further reduce parasitic effects. A T0-46 metal can is also available that has a case connection for RF grounding which increases the -3dB frequency to 600MHz. The Cerdip package is hermetically sealed, and can operate over the full -SS�C to
+12S�C range.

No external components are needed other than AC coupling capacitors because the NE/SNSES20S is internally compensated and matched to SO and ?SQ. The amplifier has very good distortion specifications, with second and third-order intermodulation intercepts of +24dBm and +1?dBm respectively at 1OOMHz.
The device is ideally suited for ?SQ cable television applications such as decoder boxes, satellite receiver/decoders, and front-end amplifiers for TV receivers. It is also useful for amplified splitters and antenna amplifiers.
The part is matched well for SOQ test equipment such as signal generators, oscilloscopes, frequency counters and all kinds of signal analyzers. Other applications at SOQ include mobile radio, CB radio and data/video transmission in fiber optics, as well as broad-band LANs and telecom systems. A gain greater than 20dB can be achieved by cascading additional NE/SNSES20Ss in series as required, without any degradation in amplifier stability.
FEATURES
� 600MHz bandwidth
� 20dB insertion gain
� 4.8dB (6dB) noise figure Z0=7SQ (ZO=SOQ)
� No external components required
� Input and output impedances matched to SO/?SQ systems
� Surface mount package available
� MIL-STD processing available

PIN CONFIGURATIONS
N, FE, D Packages
APPLICATIONS � 75Q cable TV decoder boxes
�Antenna amplifiers � Amplified splitters � Signal generators � Frequency counters � Oscilloscopes � Signal analyzers � Broad-band LANs � Fiber-optics �Modems � Mobile radio � Security systems � Telecommunications

ORDERING INFORMATION

DESCRIPTION 8-Pin Plastic SO 8-Pin Cerdip 8-Pin Plastic DIP 8-Pin Plastic SO 8-Pin Plastic DIP 8-Pin Cerdip 8-Pin Cerdip 8-Pin Plastic DIP

TEMPERATURE RANGE
o to +70�c
0 to +70�C
oto +70�c
-40 to +8S�C
-40 to +85�C -40 to +85�C -SS to + 12S'C -SS to+ 12S'C

ORDER CODE NES20SD NES20SFE NES20SN SA5205D SA5205N SAS205FE SE5205FE SE5205N

November 3, 1987

2S

853-0058 91249

Signetics RF Communications
Wide-band high-frequency amplifier

EQUIVALENT SCHEMATIC

Vee

R1

R2

YIN o------+----r 01
RE1

Product specification
NE/SA5205
Your

ABSOLUTE MAXIMUM RATINGS

SYMBOL

PARAMETER

Vee

Supply voltage

VAc

AC input voltage

TA

Operating ambient temperature range

NE grade

SA grade

SE grade

PDMAX

Maximum power dissipation, TA=25�C (still-air)1.2

FE package N package D package

NOTES: 1. Derate above 25�C, at the following rates:
FE package at 6.2mW/�C N package at 9.3mW/�C D package at 6.2mW/�C 2. See "Power Dissipation Considerations" section.

RATING 9 5
oto +70
-40to +85 -55 to +125

UNIT
v
Vp.p
oc oc
�C

780

mW

1160

mW

780

mW

November3, 1987

26

Signetics RF Communications
Wide-band high-frequency amplifier

Product specification
NE/SA5205

DC ELECTRICAL CHARACTERISTICS
Vcc=6V, Zs=ZL=Zc=50Q and TA=25�C in all packages, unless otherwise specified.

SYMBOL

PARAMETER

TEST CONDITIONS

Ice S21
S11
S11
S22
S22
S12
tR
BW IMAX IMAX IMAX IMAX IMAX

Operating supply voltage range
Supply current
Insertion gain
Input return loss
Input return loss
Output return loss
Output return loss
Isolation
Rise time Propagation delay Bandwidth Bandwidth Bandwidth Bandwidth Bandwidth Bandwidth Noise figure (75Q) Noise figure (SOQ) Saturated output power 1dB gain compression Third-order intermodulation intercept (output) Second-order intermodulation intercept (output)

Over temperature
Over temperature
f=100MHz Over temperature f=100MHz D, N, FE DC - IMAX D, N, FE f=100MHz EC package
DC-fMAxEC f=100MHz D, N, FE
DC-IMAX f=100MHz EC package
DC-IMAX f=100MHz DC -IMAX
�0.SdB D, N �0.SdB EC �0.SdBFE -3dB D, N
-3dB EC -3dB FE f=100MHz f=100MHz f=100MHz f=100MHz
f=100MHz
f=100MHz

Min 5 5 20 19 17
16.5 12
12
-18
400

SE5205 Typ
24 19 25
27
-25 5 5
300
4.8 6.0 +7.0 +4.0 +17 +24

Max
6.5 6.5
30 31
21 21.5

NE/SA5205

Min Typ Max

5

8

5

8

20

24 30

19

31

17 19 21

16.5

21.5

25

12

24

10

27

12

26

10

-25

-18

5

5

450

500

300

550

600

400

4.8

6.0

+7.0

+4.0

+17

+24

UNIT
v v
mA mA dB
dB dB dB dB dB dB dB dB dB dB ps ps MHz MHz MHz MHz MHz MHz dB dB dBm dBm
dBm
dBm

November3, 1987

27

Signefos RF Communications
Wide-band high-frequency amplifier

Product specification
NE/SA5205

35

l 34 32 30

waa:: 28 I-- TA=25�C

"<.> 26

..:'.....i 24 "'" 22
20 ;21

.....

18

~
:..i!'l Jii"'

16

5.5

6

6.5

7

SUPPLY VOLTAGE-V

....::
..t'l
7.5

Figure 1. Supply Current vs Supply Voltage

I II. t J,." 1--
t----
N~ 4 ~l t----

H
Ycc=BV H
Yee= 7v
Yee= &v b.
Yee= Sv

I
I- ZO= 500
TA:25'C

ll

5 101

4 6 8 102

6 8 103

FREQUENCY-MHz

Figure 2. Noise Figure vs Frequency

25 .---.----,--,---,--.----.----,r-:r--ir-i

I T
t= 1----+----+--<--<-1----<-- Vee= av
_t�tt-- ., 20 t---+----il---+--+-+---t Yee= 7v

l

~

~

L ~

� ~
-

t---+----il---1-+-l 15

Ye�ec=c6~v5v

~
L'-t-'-11-l

!ffli_! 1- Zo= son

I- TA= 25�C -+-1--t-t---+---+-+-..-.

101

4 6 8 102

4 6 8 103

FREQUENCY-MHz

Figure 3. Insertion Gain vs Frequency (S2,)

11

10

9

8

7

~ ~

I= Vee .1v

1- Vcc=6V

~~ j~ I= ,_ 0

Vcc=5V

rt:t---~ Vcc=BV

I== -4 t--- Zo=SOn

-S

TA= 25'C

-...... A

l'l'.

~ ~~

~

1"

x ~ I'SI

~ ~

~

ix

-0

101

6 8 102

6 8 103

FREQUENCY-MHz

Figure 5. Saturated Output Power vs Frequency

25

I :r

TA=55�C r---H

l i i TA=25'C

t--H

ES~

L

TA=85'C le'.'. .L

TA=125'C L

Lll
Vcc=BV

ZO=son
...L
10 101

8 8 102

FREQUENCY-MHz

Figure 4. Insertion Gain vs Frequency (S2,)

10

9

8

7

iii I- Vcc.6V

J

> w ~

t- Vcc.5V
1

-...., ...... Vee.av

z Vee. 7V

~c:ss: ~

~

,_ 0 ~ -1

~ """'

8:; I-- zo.son

I--
-4 t-

~t=25'5_

~ rs:

-S

-6

6 8 102 2

6 8 103

FREQUENCY-MHz

Figure 6. 1dB Gain Compression vs Frequency

.,:E 40

~ 3S
w
a<,w_.>: 30

......
~
IZ

;; wa: 2S
Q
~ 20
z
� 15

lL]

it

Zo:SOn

i

TA= 2s0 c
���

"' 10

.1 .1

4

10

POWER SUPPLY VOLTAGE-V Figure 7. Second-Order Output Intercept
vs upp y o tage

November3, 1987

28

iii
l 25 t---+--+-<l---+--+-<l---+--+-l---+--1---1

il; l;l

.......r-

~ 20 t--+--t---il--+>o""t-lo'"-<t---+--t--t---+--t---i

~ 15 t--+--t---ih''tl"'-+--+-- Zo =son t-t--

V a:

TA:25�C

~ 10 t-+--~~.._,..-+--+--if--1--+-+--+---+-~

~

8

10

POWER SUPPLY VOLTAGE-V

Figure 8. Third-Order Intercept

Signetics RF Communications
Wide-band high-frequency amplifier

Product specification
NE/SA5205

2.0

1.9

1.8 t--- TA= 25�C

t--1.7 t---

Vcc=6V

a: 1.6

:i:

.. t;_ ,g_? 1.5
:::> 1.4 ii!; 1.3

Zo=75n

1.2 I- Zo= son
1.1

_L
LL

IZZ

-;;;z.

~

1.0 101

4 6 8 102

2

6 8 101

FREQUENCY-MHz

Figure 9. Input VSWR vs Frequency

2.0

1.9

1.8 ~ Tamb=25�C

1.7 t---
~ 1.6
.,>_ 1.5
:::>
ii!; 1.4

Vcc=6V

1.3 ~ zo=;_sn

I= 1.2
1.1 zo:;son

[l. 7_
~ ~

1.0 10�

& a 102

s a 101

FREQUENCY-MHz
Figure 10. Output VSWR vs Frequency

40

35

~~ r--J 9 30 ..J

~~
:::> ~

25

20 ~ ,~_ ,~_
it it

Vcc=6V
1-- Zo= son
TA= 2s0 c

8 ii!; 15

~ """'111 ~ OUTPUT
INP~ ......
I"

10 101

6 8 102 FREQUENCY-MHz

Figure 11. Input (511) and Output (522) Return Loss vs Frequency

10

-15

Vcc=sv

i-20
~
-25

---Zo=SO<l
TA= 25�C
i--

~

4 6 8 102 FREQUENCY-MHz
Figure 12. Isolation vs Frequency (512)

25

I �cc =8� ,,L:I=

251--~-+~__,l--+-+-+-~-+~~1--+--+-1

Vcc=7v 7--Jr-+-

.IT

l f~--

Zo=75ll TA=25�C

10

J_

101

4

z ~

Vee= &v

.L ~a..

Vcc=~v ..L

,\11 f\'I

~

l

68102

2

FREQUENCY-MHz

10 101

6 8 1a2 FREQUENCY-MHz

Figure 13. Insertion Gain vs Frequency (521)

Figure 14. Insertion Gain vs Frequency (521)

THEORY OF OPERATION
The design is based on the use of multiple feedback loops to provide wide-band gain together with good noise figure and terminal impedance matches. Referring to the circuit schematic in Figure 15, the gain is set primarily by the equation:

Vour (RF1 + Re1)

(1)

VIN

Re1

which is series-shunt feedback. There is also shunt-series feedback due to RF2 and RE2 which aids in producing wideband terminal impedances without the need for low value input shunting resistors that would degrade the noise figure. For optimum noise performance, RE1 and the base resistance of 0 1 are kept as low as possible while RF2 is maximized.

The noise figure is given by the following equation:

['b +...!IT_]] !NOFlo=g [ I +

+RmRo 2qlc1

dB (2)

November 3, 1987

29

Signetics RF Communications
Wide-band high-frequency amplifier

Product specification
NE/SA5205

where le1=5.5mA, RE 1=12ll, rb=130Q,
KT/q=26mV at 25�C and Ao=50 for a son
system and 75 for a 75Q system.
The DC input voltage level V1N can be determined by the equation:
V1N=VBE1+(lc1+le3) RE1
where RE1=12Q, VBE=0.8V, le1=5mA and ic3=7mA (currents rated at Vee=6V).
Under the above conditions, V1N is approximately equal to 1V.
Level shifting is achieved by emitter-follower
0 3 and diode �'4 which provide shunt
feedback to the emitter of 0 1 via RF 1. The use of an emitter-follower buffer in this

feedback loop essentially eliminates problems of shunt feedback loading on the output. The value of RF1=140Q is chosen to give the desired nominal gain. The DC output voltage Vou1 can be determined by:
Vou1=Vee-(b+lca)R2,(4)
where Vec=6V, R2=225Q, le2=7mA and lea=5mA.
From here it can be seen that the output voltage is approximately 3.3V to give relatively equal positive and negative output swings. Diode 0 5 is included for bias purposes to allow direct coupling of RF2 to

the base of 0 1. The dual feedback loops stabilize the DC operating point of the amplifier.
The output stage is a Darlington pair (06 and 0 2) which increases the DC bias voltage on the input stage (01) to a more desirable value, and also increases the feedback loop gain. Resistor Ro optimizes the output VSWR (Voltage Standing Wave Ratio). Inductors L1 and L2 are bondwire and lead inductances which are roughly 3nH. These improve the high-frequency impedance matches at input and output by partially resonating with 0.5pF of pad and package capacitance.

R2 225
10 3nH

Q2

RF1 140 RE1 12

R3 140
RE2 12

Q5

RF2
200

Figure 15. Schematic Diagram

POWER DISSIPATION CONSIDERATIONS
When using the part at elevated temperature, the engineer should consider the power dissipation capabilities of each package.
At the nominal supply voltage of 6V, the typical supply current is 25mA (30mA Max). For operation at supply voltages other than 6V, see Figure 1 for Ice versus Vee curves. The supply current is inversely proportional to temperature and varies no more than 1mA between 25�C and either temperature extreme. The change is 0.1% per over the range.

The recommended operating temperature ranges are air-mount specifications. Better heat sinking benefits can be realized by mounting the D and EC package body against the PC board plane.
PC BOARD MOUNTING
In order to realize satisfactory mounting of the NE5205 to a PC board, certain techniques need to be utilized. The board must be double-sided with copper and all pins must be soldered to their respective areas (i.e., all GND and Vee pins on the SO

package). In addition, if the EC package is used, the case should be soldered to the ground plane. The power supply should be decoupled with a capacitor as close to the Vee pins as possible and an RF choke should be inserted between the supply and the device. Caution should be exercised in the connection of input and output pins. Standard microstrip should be observed wherever possible. There should be no solder bumps or burrs or any obstructions in the signal path to cause launching problems. The path should be as straight as possible and lead lengths as short as possible from the

November 3, 1987

30

Signetics RF Communications
Wide-band high-frequency amplifier

Product specification
NE/SA5205

part to the cable connection. Another important consideration is that the input and output should be AC coupled. This is because at Vcc=SV, the input is approximately at 1V while the output is at 3.3V. The output must be decoupled into a low impedance system or the DC bias on the output of the amplifier will be loaded down causing loss of output power. The easiest way to decouple the entire amplifier is by soldering a high frequency chip capacitor directly to the input and output pins of the device. This circuit is shown in Figure 16. Follow these recommendations to get the best frequency response and noise immunity. The board design is as important as the integrated circuit design itself.

SCATTERING PARAMETERS
The primary specifications for the NE/SA/SE5205 are listed as $-parameters. $-parameters are measurements of incident and reflected currents and voltages between the source, amplifier and load as well as transmission losses. The parameters for a tw<>-port network are defined in Figure 17.
Actual $-parameter measurements using an HP network analyzer (model 8505A) and an HP $-parameter tester (models 8503A/B) are shown in Figure 18.
Values for the figures below are measured and specified in the data sheet to ease adaptation and comparison of the NE/SA/SE5205 to other high-frequency amplifiers.

Vee
J:: DECOUPUNG CAPACITOR 1-o Your AC COUP UNG CAPACITOR
Figure 30. Circuit Schematic for Coupling and Power Supply Decoupling

Figure 17a. Two-Port Network Defined

S11 - INPUT RETURN LOSS

POWER REFLECTED FROM INPUT PORT
POWER AVAILABLE FROM GENERATOR AT INPUT PORT

S12- REVERSE TRANSMISSION LOSS OSOLATION
S21 - FORWARD TRANSMISSION LOSS OR INSERTION GAIN
S22-0UTPUT RETURN LOSS

-v 821 � TRANSDUCER POWER GAIN

POWER REFLECTED

FROM OUTPUT PORT

I 522 =

POWER AVAILABLE FROM

"'\/ GENERATOR AT OUTPUT PORT

Figure 17b.

November3, 1987

31

Signetics RF Communications
Wide-band high-frequency amplifier

Product specification
NE/SA5205

son system

25 ~~~~~~~~~~~~~f~~

;~ ~~,~~L.~~1t!:tr~ t---+---+--t-t-+---t- �cc=&� t---+---+--t-t-+--t �cc= 7v

~ �cc=~� Jt--=-+---+--t-t-t

::!_ L

~-

�ccj_I=Sv =t=~t::j

z 1-- Zo= son

l ~ TA=25�C .-+-+-t--+----+-t-t--1

10

..l

..l

101

4 8 8 102 2

FREQUENCY-MHz

a. Insertion Gain vs Frequency (S21)

-151--+----+-l--l--+--tc---+--+-+-f

l~m-~ ~-+---+-t-t-+ �" ~
::5

V Ycc=SY t---t-t-1
Zo=SOn

~

TA=25~

-25 f--+---+~c-+-+--:::::;ool"""--+--+-+-1
1---1--+-1-1-i--I

-30 ~-~-~~~~-~--~~~

101

6 8 102

6 8 103

FREQUENCY-MHz

c. lsolatlon vs Frequency (S12)

40.---....----.----.---.rr-----.--..--.--.-.

75nSystem

4 6 8102 FREQUENCY-MHz
b. Insertion Gain vs Frequency (S21)

10
11.7J

TA :25'C

..v Ycc=SY

~ v 111

6 8 1a2 FREQUENCY-MHz
d. S12 Isolation vs Frequency
40

10 ~-~-~~~~-~--~....__._.

101

6 8 102

6 8 103

FREQUENCY-MHz

e. Input (S11) and Output (S22) Return Loss vs Frequency
Figure 18.

t-----1t-- ou1ur
::r
l~UT
10 101

-~ V"
~ ~ Vcc=SV

Zo=75n TA=25�C

"

FREQUENCY-MHz
f. Input (S11) and Output (S22) Return Loss vs Frequency

November 3, 1987

32

Signetics RF Communications
Wide-band high-frequency amplifier

Product specification
NE/SA5205

The most important parameter is S21 . It is defined as the square root of the power gain, and, in decibels, is equal to voltage gain as shown below:

Zo=Z1N=ZouT for the NE/SA/SE5205

NE/SA/ SE5205

Pour+ -Vzo;u;-f

Pour
:. PtN

Pi=V1 2 P1=lnsertion Power Gain
V1=1nsertion Voltage Gain Measured value for the NE/SA/SE5205 = IS21 1 2 =100

:.P1 = Pour =I 5:11 1 2 = 100
PtN

./Pi and V1 = Vour =

= 5:11 = 10

VtN

In decibels: P1cdB) =1 O Log I S21 I 2 = 20dB V1(dB) = 20 Log S21 = 20dB :. P1cdB) = V1cdB) = S21(dB) = 20dB
Also measured on the same system are the respective voltage standing wave ratios. These are shown in Figure 19. The VSWR can be seen to be below 1.5 across the entire operational frequency range.
Relationships exist between the input and output return losses and the voltage standing wave ratios. These relationships are as follows:
INPUT RETURN LOSS=S11 dB S11dB=20 Log I S11 I
OUTPUT RETURN LOSS=S22dB S22dB=20 Log I S22 I

INPUT VSWR=o>1.5 OUTPUT VSWR=o>1.5
1d8 GAIN COMPRESSION AND SATURATED OUTPUT POWER
The 1dB gain compression is a measurement of the output power level where the small-signal insertion gain magnitude decreases 1dB from its low power value. The decrease is due to nonlinearities in the amplifier, an indication of the point of transition between small-signal operation and the large signal mode.
The saturated output power is a measure of the amplifier's ability to deliver power into an external load. It is the value of the amplifier's output power when the input is heavily overdriven. This includes the sum of the power in all harmonics.
INTERMODULATION INTERCEPT TESTS
The intermodulation intercept is an expression of the low level linearity of the amplifier. The intermodulation ratio is the difference in dB between the fundamental output signal level and the generated distortion product level. The relationship between intercept and intermodulation ratio is illustrated in Figure 20, which shows product output levels plotted versus the level of the fundamental output for two equal strength output signals at different frequencies. The upper line shows the fundamental output plotted against itself with a 1dB to 1dB slope. The second and third order products lie below the fundamentals and exhibit a 2:1 and 3:1 slope, respectively.
The intercept point for either product is the intersection of the extensions of the product curve with the fundamental output.

The intercept point is determined by measuring the intermodulation ratio at a single output level and projecting along the appropriate product slope to the point of intersection with the fundamental. When the intercept point is known, the intermodulation ratio can be determined by the reverse process. The second order IMR is equal to the difference between the second order intercept and the fundamental output level. The third order IMR is equal to twice the difference between the third order intercept and the fundamental output level. These are expressed as:
IP2=Pour+IMR2
IP3=PouT+IMR:i/2
where PouT is the power level in dBm of each of a pair of equal level fundamental output signals, IP2 and IP3 are the second and third order output intercepts in dBm, and IMR2 and IMR3 are the second and third order intermodulation ratios in dB. The intermodulation intercept is an indicator of intermodulation performance only in the small signal operating range of the amplifier. Above some output level which is below the 1dB compression point, the active device moves into large-signal operation. At this point the intermodulation products no longer follow the straight line output slopes, and the intercept description is no longer valid. It is therefore important to measure IP2 and IP3 at output levels well below 1dB compression. One must be careful, however, not to select too low levels because the test equipment may not be able to recover the signal from the noise. For the N E/SA/SE5205 we have chosen an output level of -10.5dBm with fundamental frequencies of 100.000 and 100.01 MHz, respectively.

2.0

2.0

1.9

1.8 f--- TA= 25'C 1.7 ~ .'fcc=6V

a:
~

1.6

...,..>... 1.5
::> 1.4
1.3 t_zo.1sn

1.2
1--Zo=SO<l
1.1

.J_
z r
ILL
=

1.9

1.8 ~ Tamb=25'C

a: 1.7 f--- Vee= 6V

;t
"'.>...
::>

1.6 r---+-
1.5

....... 1.4

I= 8 1.3 Zo = 75"

1.2
I= 1.1 Zo =son

tf-
~ ~

1n 10 1

4 6 8102 2

6 8 103

1.0 101

6 8 102 2

6 8 103

FREQUENCY-MHz

FREQUENCY-MHz

a. Input VSWR vs Frequency

b. Output VSWR vs Frequency

Figure 19. lnpuVOutput VSWR vs Frequency

November 3, 1987

33

Signetics RF Communications
Wide-band high-frequency amplifier

Product specification
NE/SA5205

ADDITIONAL READING ON SCATTERING PARAMETERS
For more information regarding S-parameters, please refer to High-Frequency Amplifiers by Ralph S. Carson of the University of Missouri, Rolla, Copyright 1985; published by John Wiley & Sons, Inc.
"S-Parameter Techniques for Faster, More Accurate Network Design", HP App Note 95-1, Richard W. Anderson, 1967, HP Journal.
"S-Parameter Design", HP App Note 154, 1972.

+30

THIRD ORDER

+20

INTERCEPT POINT

I

I

1dB

+10

COMPRESSION POINT
I I

FUNDAMENTAL

RESPONSE

2NDORDER INTERCEPT
POINT

2NDORDER

�20

RESPONSE

I I

3RD ORDER

-30

RESPONSE

-60 -50 -40 .30 -20 -10

0

INPUT LEVEL dBm

+10 +20 +30 +40

Figure20.

November 3, 1987

34

Slgnetlcs RF Communications
Wideband variable gain amplifier

Product specification
NE/SA5209

DESCRIPTION
The NES209 represents a breakthrough in monolithic amplifier design featuring several innovations. This unique design has combined the advantages of a high speed bipolar process with the proven Gilbert architecture.
The NE5209 is a linear broadband RF amplifier whose gain is controlled by a single DC voltage. The amplifier runs off a single S volt supply and consumes only 40mA. The amplifier has high impedance (1 kW) differential inputs. The output is SOW differential. Therefore, the S209 can simultaneously perform AGC, impedance transformation, and the balun functions.
The dynamic range is excellent over a wide range of gain setting. Furthermore, the noise performance degrades at a comparatively slow rate as the gain is reduced. This is an important feature when building linear AGC systems.

FEATURES
� Gain to 1.SGHz � SSOMHz bandwidth � High impedance differential input � SOW differential output � Single SV power supply � O - 1V gain control pin � >60dB gain control range at 200MHz � 26dB maximum gain differential � Exceptional VcoNTRoL I VGAIN linearity � 7dB noise figure minimum � Full ESD protection � Easily cascadable
APPLICATIONS
� Linear AGC systems � Very linear AM modulator � RF balun � Cable TV multi-purpose amplifier � Fiber optic AGC �RADAR � User programmable fixed gain block � Video � Satellite receivers � Cellular communications

PIN CONFIGURATION
N, D PACKAGES

ORDERING INFORMATION

DESCRIPTION

TEMPERATURE RANGE

16-Pin Plastic SO

0 to +70�C

16-Pin Plastic DIP

0 to +70�C

16-Pin Plastic SO

-40 to +85�C

16-Pin Plastic DIP

-40 to +8S�C

ORDER CODE NES209D NES209N SAS209D SAS209N

August20, 1990

3S

8S3-1453 00223

Signetics RF Communications
Wideband variable gain amplifier

Product specification
NE/SA5209

ABSOLUTE MAXIMUM RATINGS

SYMBOL

PARAMETER

Vee Supply voltage

Power dissipation, TA = 25�C (still air)1

Po

16-Pin Plastic DIP

16-Pin Plastic SO

TJMAX Maximum operating junction temperature

Tsrn Storage temperature range

RATING -0.5 to +8.0

UNITS
v

1450�

mW

1100

mW

150

oc

-65 to +150

oc

NOTES: 1. Maximum dissipation is determined by the operating ambient temperature and the thermal resistance, OJA:
16-Pin DIP: 0JA=85�C/W 16-Pin SO: OJA= 110�C/W

RECOMMENDED OPERATING CONDITIONS

SYMBOL

PARAMETER

RATING

Vee Supply voltage

Vcc1=VcC2=4.5to 7.0V

Operating ambient temperature range

TA

NE Grade

SA Grade

0 to +70 -40 to +85

Operating junction temperature range

TJ

NE Grade

SA Grade

0 to +90 -40 to +105

UNITS
v oc oc
oc oc

DC ELECTRICAL CHARACTERISTICS
TA = 25�C, Vcc1= Vcc2 = +5V, VAac = 1.0V, unless otherwise specified.

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

Ice

Supply current

DC tested

38

Over temperature1

30

Av

Voltage gain (single-ended in/single-ended out) DC tested, RL = 1Okil

17

Over temperature1

16

Av

Voltage gain (single-ended in/differential out)

DC tested, RL = 1Okil

23

Over temperature1

22

R1N

Input resistance (single-ended)

DC tested at �SO�A

0.9

Over temperature1

0.8

Rour

Output resistance (single-ended)

DC tested at �1 mA

40

Over temperature1

35

Vos

Output offset voltage (output referred)

Over temperature1

V1N

DC level on inputs

1.6

Over temperature1

1.4

Vour

DC level on outputs

1.9

Over temperature1

1.7

PSRR

Output offset supply rejection ratio

20

(output referred)

Over temperature1

15

Vea

Bandgap reference voltage

4.5V<Vcc<7V Rea= 10kil

1.2

Over temperature1

1.1

August 20, 1990

36

LIMITS TYP 43 19 25 1.2 60 �20 2.0 2.4 45
1.32

MAX 48 55 21 22 27 28 1.5 1.7 75 90 �100 �250 2.4 2.6 2.9 3.1
1.45
1.55

UNIT
mA mA dB dB dB dB
kn
kn
n n
mV
mV
v v v v
dB
dB
v
v

Signetics RF Communications
Wideband variable gain amplifier

Product specification
NE/SA5209

DC ELECTRICAL CHARACTERISTICS
TA= 25�C, Vcc 1 = Vcc2 = +5.0V, VAGC = 1.0V, unless otherwise specified.

LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

RsG VAGC lsAGC

Bandgap loading AGC DC control voltage range AGC pin DC bias current

Overtemperature1

2

10

kn

Over temperature1

0-1.3

v

OV<V AGc<1.3V

-0.7

-6

�A

Over temperature1

-10

�A

NOTES: 1. "Over Temperature Range" testing is as follows:
NE is o to +70�C SA is -40 to +85�C At the time of this data sheet release, the D package over-temperature data sheet limits are guaranteed via guardbanded room temperature testing only.

AC ELECTRICAL CHARACTERISTICS
TA= 25�C, Vcc1 = Vcc2 = +5.0V, VAGC = 1.0V, unless otherwise specified.

LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

BW

-3dB bandwidth

600

850

MHz

Over temperature1

500

MHz

GF

Gain flatness

DC-SOOMHz

�0.4

dB

Over temperature1

�0.6

dB

VrMAX

Maximum input voltage swing (single-ended) for linear operation2

200

mVp.p

VoMAX NF

Maximum output voltage swing (single-ended) for linear operation2 Noise figure (unmatched configuration)

RL =son RL=1kn Rs =son, f =SO MHz

400

mVp.p

1.9

Vp.p

9.3

dB

VrN-EQ S12 !!.Git!. Vee

Equivalent input noise voltage spectral density Reverse isolation Gain supply sensitivity (single-ended)

f = 100MHz f = 100MHz

2.S

nV/"Hz

-60

dB

0.3

dB/V

!!.Gl!!.T

Gain temperature sensitivity

RL= son

0.013

dB/�C

CrN

Input capacitance (single-ended)

2

pF

BWAGC

-3dB bandwidth of gain control function

20

MHz

Po-1dB

1dB gain compression point at output

f = 100MHz

-3

dBm

P1-1dB

1dB gain compression point at input

f = 100MHz, VAGC =0.1V

-10

dBm

IP3ouT

Third-order intercept point at output

f= 100MHz, VAGc>O.SV

+13

dBm

IP3rN

Third-order intercept point at input

f = 100MHz, VAGC <0.SV

+S

dBm

!!.GAB

Gain match output A to output B

f = 100MHz, VAGC = 1V

0.1

dB

NOTE: 1. "Over Temperature Range" testing is as follows:
NE is o to +70�C SA is -40 to +85�C At the time of this data sheet release, the D package over-temperature data sheet limits are guaranteed via guardbanded room temperature testing only. 2. With RL > 1kn, overload occurs at input for single-ended gain < 13dB and at output for single-ended gain > 13dB. With RL =son, overload occurs at input for single-ended gain< 6dB and at output for single-ended gain > 6dB.

August 20, 1990

37

Signetics RF Communications
Wideband variable gain amplifier

Product specification
NE/SA5209

NE5209 APPLICATIONS
The NES2Q9 is a wideband variable gain amplifier (VGA) circuit which finds many applications in the RF, IF and video signal processing areas. This application note describes the operation of the circuit and several applications of the VGA. The simplified equivalent schematic of the VGA is shown in Figure 1. Transistors 01 -06 form the wideband Gilbert multiplier input stage which is biased by current source 11. The top differential pairs are biased from a buffered and level-shifted signal derived from the VAGC input and the RF input appears at the lower differential pair. The circuit topology and layout offer low input noise and wide bandwidth. The second stage is a differential transimpedance stage with current feedback which maintains the wide bandwidth of the input stage. The output stage is a pair of emitter followers with SQQ output impedance. There is also an on-chip bandgap reference with buffered output at 1.3V, which can be used to derive the gain control voltage.
Both the inputs and outputs should be capacitor coupled or DC isolated from the signal sources and loads. Furthermore, the two inputs should be DC isolated from each other and the two outputs should likewise be DC isolated from each other. The NES209 was designed to provide optimum performance from a SV power source. However, there is some range around this value (4.S - 7V) that can be used.
The input impedance is about 1kn. The main advantage to a differential input configuration is to provide the balun function. Otherwise, there is an advantage to common mode rejection, a specification that is not normally important to RF designs. The source impedance can be chosen for two different performance characteristics: Gain, or noise performance. Gain optimization will be

realized if the input impedance is matched to about 1kQ. A 4:1 balun will provide such a broadband match from a SQQ source. Noise performance will be optimized if the input impedance is matched to about 200Q. A 2:1 balun will provide such a broadband match from a SQQ source. The minimum noise figure can then be expected to be about 7dB. Maximum gain will be about 23dB for a single-ended output. If the differential output is used and properly matched, nearly 30dB can be realized. With gain optimization, the noise figure will degrade to about 8dB. With no matching unit at the input, a 9dB noise figure can be expected from a SQQ source. If the source is terminated, the noise figure will increase to about 1SdB. All these noise figures will occur at maximum gain.
The NES209 has an excellent noise figure vs gain relationship. With any VGA circuit, the noise performance will degrade with decreasing gain. The 5209 has about a 1.2dB noise figure degradation for each 2dB gain reduction. With the input matched for optimum gain, the 8dB noise figure at 23dB gain will degrade to about a 20dB noise figure at OdB gain.
The NE52Q9 also displays excellent linearity between voltage gain and control voltage. Indeed, the relationship is of sufficient linearity that high fidelity AM modulation is possible using the NE5209. A maximum control voltage frequency of about 20MHz permits video baseband sources for AM.
A stabilized bandgap reference voltage is made available on the NE5209 (Pin 7). For fixed gain applications this voltage can be resistor divided, and then led to the gain control terminal (Pin 8). Using the bandgap voltage reference for gain control produces very stable gain characteristics over wide temperature ranges. The gain setting resistors are not part of the RF signal path,

and thus stray capacitance here is not important.
The wide bandwidth and excellent gain control linearity make the NE5209 VGA ideally suited for the automatic gain control (AGC) function in RF and IF processing in cellular radio base stations, Direct Broadcast Satellite (DBS) decoders, cable TV systems, fiber optic receivers for wideband data and video, and other radio communication applications. A typical AGC configuration using the NE5209 is shown in Figure 2. Three NE5209s are cascaded with appropriate AC coupling capacitors. The output of the final stage drives the full-wave rectifier composed of two UHF Schottky diodes BAT17 as shown. The diodes are biased by R1 and R2 to Vee such that a quiescent current of about 2mA in each leg is achieved. An NES230 low voltage op amp is used as an integrator which drives the VAGC pin on all three NE5209s. R3 and C3 filter the high frequency ripple from the full-wave rectified signal. A voltage divider is used to generate the reference for the non-inverting input of the op amp at about 1.7V. Keeping D3 the same type as D1 and D2 will provide a first order compensation for the change in Schottky voltage over the operating temperature range and improve the AGC performance. R6 is a variable resistor for adjustments to the op amp reference voltage. In low cost and large volume applications this could be replaced with a fixed resistor, which would result in a slight loss of the AGC dynamic range. Cascading three NE5209s will give a dynamic range in excess of 60dB.
The NE52Q9 is a very user-friendly part and will not oscillate in most applications. However, in an application such as with gains in excess of 60dB and bandwidth beyond 100MHz, good PC board layout with proper supply decoupling is strongly recommended.

August 20, 1990

Figure 1. Equivalent Schematic of the VGA 38

Signetics RF Communications
Wideband variable gain amplifier

Product specification
NE/SA5209

RFnF e>--j INPUT C>---j

........~~------j f-----o AGe ,,,..."�---t------r--i f-----o OUTPUT

.R1

= R2 3.9k

Ra = ason

= R4 62k

Rs = 10on

= Rs 1k pot

2"'L1

10k

= L1

L2

R4
r--'Vl.f\r---,,...--+--'VIJ"v---Kl--o Vee
RS BAT17
Figure 2. AGC Configuration Using Cascaded NE5209s

I I 10�F

0.1�F

Vee
SVDC

f--0 OUTA f--0 OUT9

(16-Pln SO, 150-mll wide)
Figure 3. VGA AC Evaluation Board

August 20, 1990

39

Signetics RF Communications
Wideband variable gain amplifier

Product specification
NE/SA5209

August 20, 1990

+SY

'" �~' 1 ~~~CJ- I~ ���~~ 2:1 BALUN

-=

+1V

=

son
~OUTPUT
=

This circuit will exhibit about a 7dB noise figure with approximately 22dB gain.

Figure 4. Broadband Noise Optimization

'"-�-*- LC TUNED
~ct
SOURCEr

+SY

S209

I

1 son

-:-

YAGC

+1V

"=

~�~��j�~rCa *--. Figures. Narrowband Noise Optimization +SY 4:1 BALUN OR

-= 1:4

1 son YAGC

+1V

-=

~

-q:*- Figure 6. Broadband Gain Optimization

LC TUNED
"'"-AAOO

+SY
I

SOURCEr

S209

son

son
~OUTPUT

Thia circuit wlll exhibit about a 7dB nolee figure with approximately 22dB gain. Narrowband circul1S have the advantage of greater
atablllty, particularly when multiple
devices are cascaded.

son
~OUTPUT

Thia circuit wlll exhibit about an &dB nolee figure with 24dB gain.

~OUsToPn UT
=

This circuit wltl exhibit approximately an BdB noise figure and 25dB gain.

-:-

1 YAGC

+1V

-=:-

son
SOURCE~

Figure7. Narrowband Gain Optimization

l*-1+SY

i son

s209

= p

1son

YAGC

+1V

-=-

son
~OUTPUT

The noise ftgure of thla configuration will be approximately 1SdB.

Figure 8. Simple Amplifier Configuration

40

Signetics RF Communications
Wideband variable gain amplifier

Product specification
NE/SA5209

son
SOURCE~

l*-11 +SY

S209

p

son

-

YAGC

+1V

-=

~OUsToPn UT

With the son eowce left unterminated, the nolae figure le 9dB.

Figure 9 Unterminated Configuration

son
SOURCE~

+SY
~OUsTonPUT
Gain= 19dB +201og10 VAGC
J = where V40c ( Ri R+i R2 Vaa
encl le In unite of olts, for VAaC s 1

Figure 10. User-Programmable Fixed Gain Block

+SY FULL CARRIER
AM(DSB)
~OUsToPn UT

All hannonic distortion products Wfll be at least-SOdBc over the audio spectrum.

CRYSTAL FILTER

Figure 11. AM Modulator

MODULATING SIGNAL

son
OUTPUT
son

The high input Impedance to the NE5209 makes matching to crystal filters relatively easy. The total delta gain of this system will approach SOdB. IF frequencies well into the UHF
region can be configured with this type of architecture.

Figure 12. Receiver AGC IF Chain

August 20, 1990

41

GAIN CONTROL SIGNAL

Signetics RF Communications
Wideband variable gain amplifier

Product specification
NE/SA5209

It
Figure 13. Test Set-up 1 (Used for all Graphs)
Vee=5.5V
Vee= s.ov
Vee :4.5V

T: 25'C
Rs= RL= so.a
Rt ... oo
I� 10MHz

DC Tested see teat~setup 1

0.2

0.4

0.6

0.8

VAGC(V)

Figure 14. Gain vs VAcc and Vee

19.5 +----:f~:~p;;-;;-~;;;;;;;;~ ~:'::'-;;;;::-t--- 5.5V 1 9 + - - - - + - - - + - - - - - + - - - - ' F......_~--j 5.0V
i 18.5 + - - - - + - - - + - - - - - + - - - - + - - - - 4 4.5V

~ 18+----+---+-----+----+----4
g,
~ 17.5 + - - - - + - - - + - - - - - + - - - - + - - - - 4

I 17

RRsL--o~n

-

!

Ap� oo

~ 16.5 -+-----+----+---- VAcc� 1.1V -

1 1 16 + - - - - + - - - + - - - - See Test setup 1 --j
15.5 + - - - - + - - - + - - - - - + - - - - + - - - - 4

15+-,-,..,-,-+.,-,....,..,-t-,-.,-,.-.,-T-t-r-r.,-r+-1-,--,--,.....,~

-100

-50

0

50

100

150

Temperature ("C}

-~re 16. Voltage Gain vs Temperature and Vee

Rs= RL= son
Rte oo See test-setup 1

0

~

M

~

M

U

VAGeM

Figure 15. Insertion Gain vs VAGC and Temperature

55

50

45 -j---"'"*"""'"""=~::---t--"""o;;;;I:::-~""' =7.0V

c
.�. 40
j 35

= 6.0V
:5.0V :4.SV

I 30

25

See te �~tup 1

20

-100

-50

0

50

100

150

Temperature ("C)

Figure 17. Supply Current vs Temperature and Vee

August 20, 1990

42

Signetics RF Communications
Wideband variable gain amplifier

Product specification
NE/SA5209

1.5 1.45
1.4 1.35
c: 1.3
~
..~ 1.25
J! ti 1.2 a:
J1.15 1.1 1.05
-100

h /J ?'
ff
..,,?' ~p -

Vee= 1.ov
Vee :4.5V

s:;:.-::..~ 1 -

+

-50

50

100

150

Temperature ("C)

Vee .1.ov

Vee .G.ov

~

1.5 -t----+----t----+---+-----j

Vee= 5.ov Vee= 4.5V

t

~

i

!

0.5 -t----+----t----+---+-----1
DC Tested See test-aetup 1

-100

-50

0

50

100

150

Temperature (�C}

Figure 19. Input Bias Voltage vs Temperature

~5.-------.---.-------.----.------.

3.5
1J, 3
J!
~ 2.5
0 Q
j 2 c5 1.5
0.5

Vee= 5.ov Vee=4.5V
DC Tested See test-setup 1

-100

-50

50

100

150

Temperature ("C)

Figure 20. Output Blas Voltage vs Temperature and Vee


~ 1.5
..:~.:...:..>...
iS g
0.5

VAGe=1.1V _
RL = 10kll
DC Tested See test-setup 1

-100

-50

50

100

150

Temperature ("C)

Figure 21. DC Output Swing vs Temperature

August 20, 1990

43

Signetics RF Communications
Wideband variable gain amplifier

Product specification
NE/SA5209

� o_av.

~
T: 25�C Rs=RL=50n
Rt� son See Test Setup 1

10

100

1000 1500

Frequency (MHz)

Figure 22. Insertion Gain vs Frequency and VAGC

16
14 12
i 10

........

Vee= 1.ov Vee= s.ov

Vee= 5.ov

Vcc=4.5V

1S
5.SV~

~ 4.5V

~

., 10

t-i

l!.

1

.. 5
:I

T:25"'C VAGC� 1.1V R9111RL=50n

~

S��rrTu Rt� Son

-5

10

100

10001500

Frequency (MHz)

Figure 23. Insertion Gain vs Frequency and Vcc

r.2s0 c
VAGC � 1.1V -
Rt� son f � 10MHz Sea Test Setup 1 -

-100

-so

0

50

100

150

Temperature (..C)

Figure 24. Insertion Gain vs Temperature and Vee

-20 1-

Rs� AL-son

Rt� Son

See Test Setup 1
-25 ...-~--t---t-t--t-H-H----..l_,._-j-.,._..J_,....J...,....J.,...,JJ...,...~,.,.._

10

100

10001500

Frequency (MHz)

Figure 25. Output Return Loss vs Frequency

August 20, 1990

44

Signetics RF Communications
Wideband variable gain amplifier

Product specification
NE/SA5209

0 -10
~

I-'

IL

v_L T=25�C

-70

J-1
~

R,=RL=SO<l
R,= son

t-

See test..eetup 1

~

Tf

~

�

~ ~

Frequency (MHz)

Fl ure 26. Reverse Isolation vs Fr uenc

T =25�C Rs= RL =son
Rt= son I= 100MHz See test-setup 1
..
;!!

0.2

0.4

0.6

0.8

VAGC(V)

Figure 28. Third-Order Intermodulation Intercept vs VAGC

i
:!?. -15
o.'

OUTPUT INPUT

0.2

0.4

0.6

0.8

VAGC(V)

Figure 27. 1dB Gain Compression vs VAGC

ro~~~]'\~~~~~~~~ 19-+-~~-+-~"'~~1--~~+--~~.+-~~~
16+-~~-1-__:~~--i,..:+1-...~...._=+-~~-l-~~-l
~~
14

T= 25"C
Rt= oo l=SOMHz See teat-eetup 1

---I

0.2

0.4

0.6

0.8

VAGC(V)

Figure 29. Noise Figure vs VAGC

August 20, 1990

45

Signetics RF Communications
Wideband variable gain amplifier

Product specification
NE/SA5209

l 8 +---+--+
!!

T= 2s0 c VAac= 1.1V
Ra=RL=son
Rt=ooonlNA See test-setup 1

10

100

1000

Frequency (MHz)

Fl ure 30. Noise Fl ure vs Fre uenc

1.4 1.35
1.3 ~
& 1.25
j ! 1.2
! 1.15
1.1 1,05

Vcc=1.ov Vcc:B.OV Vcc�S.OV Vcc�4.5V
Bandgap Load � 2kn

-100

-50

0

50

100

150

Temperature ("C)

Figure 31. Bandgap Voltage vs Temperature and Vee

10.+:==::::::p:,,,,,,._""_d~f----l----_.j
t---

.g ~ 6+-----f-----+----+------1
I

.;:<4+-----f-----+--- Rs= RL= 5011

R1:50n

R1=R2=10k

1:100MHz -1

-O-t-.-.-.-.,-t-r-,---,--,-t-,--r-r-rSee~l-F,lg_~,e-1TO-r-l

-10

40

90

140

Temperature ("C)

Figure 32. Fixed Gain vs Temperature

August 20, 1990

46

Signetics RF Communications
Wideband variable gain amplifier

Product specification
NE/SA5209

8 8 0 �.�... ~ v 8

0

0 +Vee GND

I";\ I";\

\,,J

\,,J

INA

m ~
~ ~ ~ ~

8 I";\
'-J OUTA

~
8 0 8 ~ 8 0 .>.!:<.

I";\
'-J

I";\ I";\

'-J

'-J

NE5209 OUTe

TOP VIEW� COMPONENT SIDE VGA AC Evaluation Board Layout

TOP VIEW� SOLDER SIDE

August 20, 1990

47

Signetics RF Communications
Wideband variable gain amplifier

Product specification
NE/SA5209

f.\.
\. ./

8

0

8

f.\.
\. _,/

INA

NE5209

INe

f.\.
\._,I

8

0

'0- _,/

8

....��
+VccQ � � GND

iB c-::-J
0

0 0 0

c:J

<". 0 0

�

~

IB
0

0 00

S:::>

0 c:J

0 0

iB

0 0

IB IB
0 0 0 0

00�

C-)0

.(�)

TOP VIEW� COMPONENT SIDE

8 OUTA

f.\
\. ./

0

f'-._\,/

f.\
\. _,/

f.\
\. _,/
0 8 f.\
\. ./ OUT9

TOP VIEW� SOLDER SIDE AGC Configuration Using Cascaded NE5209s � Layout

August 20, 1990

48

Signetics RF Communications
Wideband variable gain amplifier
���������
\..../ \..../

Product specification
NE/SA5209

AMP10101 / NE5219SO/DN8.90 TOP VIEW� COMPONENT SIDE

TOP VIEW� SOLDER SIDE

VGA AC Evaluation Board Layout (DIP Package)

August20. 1990

49

Signetics RF Communications
Wideband variable gain amplifier

Preliminary specification
NE/SA5219

DESCRIPTION
The NES219 represents a breakthrough in monolithic amplifier design featuring several innovations. This unique design has combined the advantages of a high speed bipolar process with the proven Gilbert architecture.
The NE5219 is a linear broadband RF amplifier whose gain is controlled by a single DC voltage. The amplifier runs off a single S volt supply and consumes only 40mA. The amplifier has high impedance {1kn) differential inputs. The output is son differential. Therefore, the S219 can simultaneously perform AGC, impedance transformation, and the balun functions.
The dynamic range is excellent over a wide range of gain setting. Furthermore, the noise performance degrades at a comparatively slow rate as the gain is reduced. This is an important feature when building linear AGC systems.

FEATURES
� 700MHz bandwidth � High impedance differential input � son differential output � Single SV power supply � 0 - 1V gain control pin � >60dB gain control range at 200MHz � 26dB maximum gain differential � Exceptional VcoNTAOL I VaAIN linearity � 7dB noise figure minimum � Full ESD protection � Easily cascadable
APPLICATIONS
� Linear AGC systems � Very linear AM modulator �RF balun � Cable TV multi-purpose amplifier � Fiber optic AGC �RADAR � User programmable fixed gain block �Video �Satellite receivers � Cellular communications

ORDERING INFORMATION

DESCRIPTION

TEMPERATURE RANGE

16-Pin Plastic SO

a to +70�C

16-Pin Plastic DIP

Oto +70�C

16-Pin Plastic SO

-40 to +8S�C

16-Pin Plastic DIP

-40 to +SS�C

ORDER CODE NES219D NE5219N SAS219D SAS219N

PIN CONFIGURATION N, D PACKAGES

June 17, 1991

50

Signetics RF Communications
Wideband variable gain amplifier

Preliminary specification
NE/SA5219

ABSOLUTE MAXIMUM RATINGS

SYMBOL

PARAMETER

Vee Supply voltage

Power dissipation, TA= 25�C (still air) 1

Po

16-Pin Plastic DIP

16-Pin Plastic SO

RATING -0.5 to +8.0

UNITS
v

1450

mW

1100

mW

TJMAX Tsra

Maximum operating junction temperature Storage temperature range

150

oc

-65 to +150

oc

NOTES: 1. Maximum dissipation is determined by the operating ambient temperature and the thermal resistance, 8JA:
16-Pin DIP: 8JA = 85�C/W 16-PinSO: eJA= 11occ/W

RECOMMENDED OPERATING CONDITIONS

SYMBOL

PARAMETER

RATING

Vee Supply voltage

Vcc1=Vcc2=4.5 to 7.0V

Operating ambient temperature range

TA

NE Grade

SA Grade

Oto +70 -40 to +85

Operating junction temperature range

TJ

NEGrade

SA Grade

0 to +90 -40 to +105

UNITS
v
cc cc
cc cc

DC ELECTRICAL CHARACTERISTICS
TA= 25cc, Vcc1= Vcc2 = +5V, VAGC = 1.0V, unless otherwise specified.

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

Ice

Supply current

DC tested

36

Av

Voltage gain (single-ended in/single-ended out) DC tested, RL = 10kQ

16

Av

Voltage gain (single-ended in/differential out)

DC tested, RL = 1OkQ

22

R1N

Input resistance (single-ended)

DC tested at �50�A

0.8

Rour

Output resistance (single-ended)

DC tested at �1 mA

35

Vos

Output offset voltage (output referred)

V1N

DC level on inputs

1.6

Vour

DC level on outputs

1.9

PSRR

Output offset supply rejection ratio

18

Vsa

Bandgap reference voltage

4.5V<Vcc<7V Rsa = 101ill

1.2

Rsa VAGC lsAGC

Bandgap loading AGC DC control voltage range AGC pin DC bias current

2 OV<V AGc<1.3V

LIMITS TYP 43 19 25 1.2 60 �20 2.0 2.4 45
1.32
10 0-1.3 -0.7

MAX 50 22 28 1.6 80
�150 2.4 2.9
1.45
-6

UNIT mA dB dB kQ Q mV
v v
dB
v
kQ
v
�A

June 17, 1991

51

Signetics RF Communications
Wideband variable gain amplifier

Preliminary specification
NE/SA5219

AC ELECTRICAL CHARACTERISTICS
TA= 2S�C, Vcc1 = Vcc2 = +S.OV, VAGC = 1.0V, unless otherwise specified.

LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

BW

-3dB bandwidth

700

MHz

GF

Gain flatness

DC-SOOMHz

�0.4

dB

V1MAX

Maximum input voltage swing (single-ended) for linear operation 1

200

mVp.p

VoMAX NF

Maximum output voltage swing (single-ended) for linear operation1 Noise figure (unmatched configuration)

RL =son RL = 1kn Rs = son, f = SOMHz

400

mVp.p

1.9

Vp.p

9.3

dB

V1N-EQ S12

Equivalent input noise voltage spectral density Reverse isolation

f = 100MHz f = 100MHz

2.S

nVJ.../Hz

-60

dB

tJ.G/tJ.Vcc Gain supply sensitivity (single-ended)

0.3

dB/V

tJ.G!tJ.T

Gain temperature sensitivity

RL =SOn

0.013

dB/�C

C1N

Input capacitance (single-ended)

2

pF

BWAGC

-3dB bandwidth of gain control function

20

MHz

Po.1ds

1dB gain compression point at output

f = 100MHz

-3

dBm

P1.1dB

1dB gain compression point at input

f= 100MHz, VAGC=0.1V

-10

dBm

IP3our

Third-order intercept point at output

f = 100MHz, VAGC >0.SV

+13

dBm

IP31N

Third-order intercept point at input

f = 1OOMHz, VAGC <0.SV

+S

dBm

!J.GAB

Gain match output A to output B

f = 100MHz, VAGC = 1V

0.1

dB

NOTE: 1. With RL > 1kn, overload occurs at input for single-ended gain < 13dB and at output for single-ended gain > 13dB. With RL = son, overload
occurs at input for single-ended gain< 6dB and at output for single-ended gain> 6dB.

NE5219 APPLICATIONS
The NES219 is a wideband variable gain amplifier (VGA) circuit which finds many applications in the RF, IF and video signal processing areas. This application note describes the operation of the circuit and several applications of the VGA. The simplified equivalent schematic of the VGA is shown in Figure 1. Transistors Q1-Q6 form the wideband Gilbert multiplier input stage which is biased by current source 11. The top differential pairs are biased from a buffered and level-shifted signal derived from the VAGC input and the RF input appears at the lower differential pair. The circuit topology and layout offer low input noise and wide bandwidth. The second stage is a differential transimpedance stage with current feedback which maintains the wide bandwidth of the input stage. The output stage is a pair of emitter followers with son output impedance. There is also an on-chip bandgap reference with buffered output at 1.3V, which can be used to derive the gain control voltage.
Both the inputs and outputs should be capacitor coupled or DC isolated from the signal sources and loads. Furthermore, the two inputs should be DC isolated from each other and the two outputs should likewise be

DC isolated from each other. The NES219 was designed to provide optimum performance from a SV power source. However, there is some range around this value (4.S - 7V) that can be used.
The input impedance is about 1kn. The main advantage to a differential input configuration is to provide the balun function. Otherwise, there is an advantage to common mode rejection, a specification that is not normally important to RF designs. The source impedance can be chosen for two different performance characteristics: Gain, or noise performance. Gain optimization will be realized if the input impedance is matched to about 1kQ. A 4:1 balun will provide such a broadband match from a son source. Noise performance will be optimized if the input impedance is matched to about 200n. A 2:1 balun will provide such a broadband match from a son source. The minimum noise figure can then be expected to be about 7dB. Maximum gain will be about 23dB for a single-ended output. If the differential output is used and properly matched, nearly 30dB can be realized. With gain optimization, the noise figure will degrade to about 8dB. With no matching unit at the input, a 9dB noise figure can be expected from a son source. If

the source is terminated, the noise figure will increase to about 15dB. All these noise figures will occur at maximum gain.
The NE5219 has an excellent noise figure vs gain relationship. With any VGA circuit, the noise performance will degrade with decreasing gain. The 5219 has about a 1.2dB noise figure degradation for each 2dB gain reduction. With the input matched for optimum gain, the 8dB noise figure at 23dB gain will degrade to about a 20dB noise figure atOdB gain.
The NES219 also displays excellent linearity between voltage gain and control voltage. Indeed, the relationship is of sufficient linearity that high fidelity AM modulation is possible using the NES219. A maximum control voltage frequency of about 20MHz permits video baseband sources for AM.
A stabilized bandgap reference voltage is made available on the NES219 (Pin 7). For fixed gain applications this voltage can be resistor divided, and then fed to the gain control terminal (Pin 8). Using the bandgap voltage reference for gain control produces very stable gain characteristics over wide temperature ranges. The gain setting resistors are not part of the RF signal path,

June 17, 1991

S2

Signetics RF Communications
Wideband variable gain amplifier

Preliminary specification
NE/SA5219

and thus stray capacitance here is not important.
The wide bandwidth and excellent gain control linearity make the NE5219 VGA ideally suited for the automatic gain control (AGC) function in RF and IF processing in cellular radio base stations, Direct Broadcast Satellite (DBS) decoders, cable TV systems, fiber optic receivers for wideband data and video, and other radio communication applications. A typical AGC configuration using the NE5219 is shown in Figure 2. Three NE5219s are cascaded with appropriate AC coupling capacitors. The output of the final stage drives the full-wave

rectifier composed of two UHF Schottky diodes BAT17 as shown. The diodes are biased by R1 and R2 to Vee such that a quiescent current of about 2mA in each leg is achieved. An NE5230 low voltage op amp is used as an integrator which drives the VAGC pin on all three NE5219s. R3 and C3 filter the high frequency ripple from the full-wave rectified signal. A voltage divider is used to generate the reference for the non-inverting input of the op amp at about 1.7V. Keeping D3 the same type as D1 and D2 will provide a first order compensation for the change in Schottky voltage over the operating temperature range and improve the AGC

performance. RS is a variable resistor for adjustments to the op amp reference voltage. In low cost and large volume applications this could be replaced with a fixed resistor, which would result in a slight Joss of the AGC dynamic range. Cascading three NE5219s will give a dynamic range in excess of SOdB.
The NE5219 is a very user-friendly part and will not oscillate in most applications. However, in an application such as with gains in excess of SOdB and bandwidth beyond 100MHz, good PC board layout with proper supply decoupling is strongly recommended.

RFnF o-j INPUT o-j

BANDGAP REFERENCE

Vea

Figure 1. Equivalent Schematic of the VGA
.......~-.-------lf--o AGC
..-"-~'------~-'f--o OUTPUT

June 17, 1991

Vee Figure 2. AGC Configuration Using Cascaded NE5219s
53

Signetics RF Communications
Wideband variable gain amplifier

Preliminary specification
NE/SA5219

Figure 3. VGA AC Evaluation Board

+SV

.:~~:n2i1L . . 1~ M2:1INBICAILRUCNUITS

~

1

VAGC

"=-

+1V

*- Figure 4. Broadband Noise Optimization +SV

2L:C1 TTUUNRENDS RATIO

son

TRANSq:FORMER

I

SOURCE~

5219

1son

VAGC

+1V

-

s:i son OUTPUT
Thia circuit will exhibit about a 7dB noise figure with approximately 22dB gain.

s:i son OUTPUT

Thia circuit will exhibit about a 7dB noise figure with approximately 22dB gain. Narrowband circuits have the advantage of greater
stability, particularly when muHiple devices are cascaded.

Figure 5. Narrowband Noise Optimization

June 17, 1991

54

Signetics RF Communications
Wideband variable gain amplifier

Preliminary specification
NE/SA5219

c ~ 4M:1INBICAILRUCNUIOTRS
son tJEQUIYALENT
SOURCE

+SY
I

=

11

S219

= 1:4

1son

-= YAGC
+1V

~OUsTonPUT
-=

Thia circuit will exhibit about an SdB noise figure wl1h 24dB gain.

Figure 6. Broadband Gain Optimization

+SY

-�~ct: ~� 1- ~ 4LC:1TTURNENDSRATIO

TRANSFORMER

son

I

son
~OUTPUT

-

YAGC

+1V

-=

Thie circuit will exhibit approxlmatelyan SdB nolae figure and 25dB gain.

Figure 7. Narrowband Gain Optimization

son
SOURCE~

+SY

1 '*-' SOl1
= ~

S219
1SOl1
YAGC

+1V

-=

Figure 8. Simple Amplifier Configuration

~OUST01P1 UT

The noise figure of thla configuration will be approximately 15dB.

son
SOURCE~

+SY

l~I 5219

_r:-l

=

1 son YAGC

+1V

-=-

son
~OUTPUT

With the son source left untennlnated, the noise figure le 9dB.

Figure 9 Unterminated Configuration

son
SOURCE~
Figure 10. User-Programmable Fixed Gain Block

Gain= 19dB + 201og1a VAGc
J whereV.&ec= ( Ri R+2 R2 Yso
and is In units of olta, for VAGc s 1

June 17, 1991

55

Signetics RF Communications
Wideband variable gain amplifier

Preliminary specification
NE/SA5219

CRYSTAL FILTER

+SV

FULL CARRIER

AM(DSB)

500

�?ouTPUT

An hannonlc - o n product8 win be 11 IHll.51JdBc over the audio opectrum.

~MODULATING ~SIGNAL
Figure 11. AM Modulator

500
OUTPUT

VAGC

VAGC

The high Input Impedance to the NE5219 makH matching to cryebl flllere relahely-y. The total delta gain of Illa oyatemwlllapproach80dB. IFfnquonclffwolllntotheUHF region can ba configured with thia type of architecture.

Figure 12. Receiver AGC IF C.haln

Figure 13. Test Set-up 1 (Used for all Graphs)

June 17, 1991

56

Signetics RF Communications
Wideband variable gain amplifier

Preliminary specification
NE/SA5219

Vcc=5.5V Vcc.S.OV
Vcc=4.5V

T: 25"C Rs= RL:50Q
Rt�CIO f � 10MHz

0.2

OA

0.6

0.8

1.2

VAGe(V)

Figure 14. Gain vs VAGe and Vee

20

19.5

19

iii :!!.

18.5

c

~ 18

j
..~ 17.5

i 17 16.5

18

15.5

:::p-"

....,

~ --=!~

5.5V

5.0V

4.5V

Rs-on RL-oo

-

Rt�oo
VAGC� 1.W

-

J - see Test Jetup 1

15

T

T

-100

-50

0

50

100

150

Temperature ("C)

Figure 16. Voltage Gain vs Temperature and Vee

Rs= RL=50n
At=oo
See test-setup 1

0

u

~

~

~

u

VAGeCVl

Figure 15. Insertion Gain vs VAae and Temperature

55

50

45
:c
.5. 40
. j 35
l 30

25

See ~1

20

-100

-50

0

50

100

150

TamperdUl'e (0 C)

Figure 17. Supply Current vs Temperature and Vee

June 17, 1991

57

Signetics RF.Communications
Wideband variable gain amplifier

Preliminary specification
NE/SA5219

1.5 .,,..-~---.----,----,-----,----...,

1.45 -+----+-----+-----+-----+-----t 1.4 -+----+-----+----+----+-----!

}--.'.f=::::;;;;:~;:;:;~:"":::;;~:"'""....---J Vee= 1.ov

1.35 + - - - - + - - - + - - - + - - - - + - - - - ; Vee= 7.0V

Vee=B.OV

A ~ 1.3 +---+---+---+---~-+:rfi"----1 Yee= 4.5V B1.25 -l--+--+--t-�--7'.'iA------l

Vee=S.OV
E 1.5 -+----+----+---+----+----; Vee :4.5V
f

I"

j 1.2 +--+---+--A-'.2--,i.s.~-+----i

!

i 1.15 +---tL..-=====4-----::F-P...-:T-+--+---I

i

1.1 - ' 1 - - - - : : . . . . - - 1 - - - - 1 - - - - + - - - l

0.5 - + - - - - + - - - - + - - - + - - - + - - - - I

1.05 -+----+----+---;

De Tested ---p1

-100
Fl

50

100

150

Temperature ("C)

Vee=1.ov

Vee= &.ov

& 3..l---=i===--+---+---+-----l

I Vee=5.0V

g

2.�

+---+---+--=P-""""'=t---1
Vcc:4.5V

1 2

c5 1.5 +---=i=='---+---+---+----l

-100

0

50

100

150

Temperaiure("C)

Figure 19. Input Blas Voltage vs Temperature

2.5

E

r--r---r-

!i! 1.5

...:~:...:>...
5

- VAGC�1.1V Rt= 1Dlln

8

DCTeelod

---p1

0.5

o-+-r-r.,-,-t--r-r-.-...+-r-.-.-...+-.-,....,.-r-1--.--r-r..,..-1

-100

50

100

150

Temperature ("C)

Figure 20. Output Blas Voltage vs Temperature and Vee

0

-100

0

50

100

150

Temperature ("C)

Figure 21. DC Output Swing vs Temperature

June 17, 1991

58

Signetics RF Communications
Wideband variable gain amplifier

Preliminary specification
NE/SA5219

_ OJIV _ 10+----;-t--1-+.++1H+---+-;-+--HH'i-l'itt--1

i -r++-J.~' ~ !

!). ~

o .!--t--t-t-++1+++------11-+

+-- r-,.. l\ ~--10 +---+--+-+-t+++t+--+--+--t-1-H"t:H"\-4

+-;-;- t--- -t-

~ -3�mX.

-20+---+--+-+-t++H+--+--+--Hl-H~~

T:25'C

Rs=RL=500

Rt� 500 ses Test Setup 1

10

100

1000 1500

Frequency (MHz)

Figure 22. Insertion Gain vs Frequency and VAGC

16

14

12

r=-

Vcc�7.0V
Vcc�B.OV

Vcc:5.0V

Vcc=4.SV

T- 25'C
VAGC� 1.1V -

Rt�500

f � 10MHz

4

See Test Setup 1 -

2

0 -100

0

50

100

150

Temperalu'e ("C)

Figure 24. Insertion Gain vs Temperature and Vee

15

_,,,, 5.5V-.._

4.5V

~

10

ri

0

T= 25'C VAGC�1.1V
Rs= AL= son

~

Rt�SOO

SeT.jl~

10

100

10001500

Frequency (MHZ)

Figure 23. Insertion Gain vs Frequency and Vcc

0-,---,..---,--,..-T"T'TTT,---o--,..-'T"1-r!Tn---i

-5 -+----+---+--+--H-,..,....t---+---+--+-+............---1
~
! -10 -+---+-+-+-H-H+t--+--+-+-+~+tt---i
~

-20 ~-

Rs�RL�500

flt�500 See Tes1 Setup 1

-& -i----+--+-+-+-..........,_,__-J._,__-j.+-..l-t-J.+-J.,....ci.L..,.,Llj.H---t

10

100

10001500

Frequency (MHz)

Figure 25. Output Return Losa vs Frequency

June 17, 1991

59

Signetics RF Communications
Wideband variable gain amplifier

Preliminary specification
NE/SA5219

0
-10 1..,..
'

N
,,,.. -611

-70
~

~

l/t" ""

_L_

]7

Ta25�C

t - - RacAL,=500 Aai:=500 I H 1 H t. . .t u p 1

ll

8
Freq..;cy (MHz)
Fl ure 26. Reverse Isolation vs Fr

uenc

0 OUTPUT
-5

-10
i
:!. -15
.J
-20
-25

I'

T:25�C
At�RL=500
Rt�60n f:100MHz Seeteat-ee1Up1

INPUT'

-30

0

0.2

0.4

0.8

.8

VAQC(Y)

Figure 27. 1dB Gain Compression v� VAGC

T�25�C Rs=RL=50n
RtsSOO. I= 100MHz Seeteat-eetup1
I..
I o + - - - + - + - - - + - - - + - - - + - - - - - I INPUT

20~---rs:::--~--------~

~ r - - - L 1189-l---+-__:~' ~~.::::i:'-~..._.d,----+----l

14

"J

12+---+---+----f"'oo-............;.,--+------I

l10-l----+--~l----+---l-=1--..~._d

!I:

4

T: 25�C Ra=RL=50.0:
At="�
f:50MHz See IHl-eetup 1

---I

0

0.2

0.4

0.6

0.8

VAac(Y)

Figure 28. Third-Order lritermodulatlon Intercept va VAGC

0

0.2

0.4

0.6

0.8

VAQC(V)

Figure 29. Noise Figure va VAoc

June 17, 1991

60

Signetics RF Communications
Wideband variable gain amplifier

Preliminary specification
NE/SA5219

! 8 -+-_ _,____,
!I:

T=25"C V11ac= 1.1V R1 =RL=SO!l R1 =ooonlNA -telll-tup1

10

100

1000

Frequency (MHz)

Fl ure 30. Noise Fl ure vs Fre uenc

12

10

-r----r--

1.4 - - - - - - - - - - - - - - - -
Vcc=1.ov
Vcc=&.OV Vcc:S.OV Vcc=c.sv
t ~ 1.25
~
t 1.2
fm 1.15-, '----+----+----+----4----1
1.1 -1----+-----1----1-----4----1
Bandgap Load � 2kn 1.05 -+----+----1-----1-----'-----'

-100

0

50

100

150

TemperalUnl ("C)

Figure 31. Bandgap Voltage vs Temperature and Vee

- Rs=RL=SO!l
Rt=SO!l
R1=R2=10k
I= 100MHz --l
1Flgure10

0

-80

-10

40

90

140

Temperature ("C)

Figure 32. Fixed Gain vs Temperature

June 17, 1991

61

Signetics RF Communications
Wideband variable gain amplifier

�.: Preliminary specification
NE/SA5219

0 �..�. t;'\ t;'\

"-J

"-J

/~ ":-..

t;'\
"-J

+Vee GND

0 0 t;'\ t;'\

"' "' m INA

I ,-:.;.
0 I 0 ~

t;'\
"-J

~ ~

f~ l
>.~.!:c.

t;'\ t;'\

"-J

"-J

OUTA

t;'\ t;'\

"-J

"-J

"'t;'\ t;'\ (e ��

r." t;'\

"-J I Ne

~8li:
"C>

NE52"19' OUT"e-J

TOP VIEW� COMPONENT SIDE

TOP VIEW� SOLDER SIDE

VGA AC Evaluation Board Layout (DIP Package)

� �� �
~-�..�
v v

0:)0)
AMP10101 / NE5219SO/DN8.90 BOTTOM VIEW� D Package

TOP VIEW� D Package

VGA AC Evaluallon Board Layout (SO Package)

June 17, 1991

62

Slgnetlcs RF Communications
Matched quad high-performance low-voltage operational amplifier

Product specification
NE/SA5234

DESCRIPTION
The NE/SA5234 is a matched, low voltage, high performance quad operational amplifier. Among its unique input and output characteristics is the capability for both input and output rail-to-rail operation, particularly critical in low voltage applications. The output swings to less than 50mV of both rails across the entire power supply range. The NE/SA5234 is capable of delivering 5.5V peak-to-peak across a 6000 load and will typically draw only 700�A per amplifier. The bandwidth is 2.5MHz and the 1% settling time is 1.4�s.
FEATURES � Wide common-mode input voltage range:
250mV beyond both rails
� Output swing within 50mV of both rails
� Functionality to 1.8V typical
� Low current consumption: 700�A per amplifier
� �15mA output current capability
� Unity gain bandwidth: 2.5MHz
� Slew rate: 0.8V/�s
� Low noise: 25nVNHz
� Electrostatic discharge protection
� Short~ircuit protection
� Output inversion prevention

APPLICATIONS
� Automotive electronics
� Signal conditioning and sensing amplification
� Portable instrumentation - Test and measurement - Medical monitors and diagnostics - Remote meters
� Audio equipment
� Security systems
� Communications - Pagers - Cellular telephone - LAN - 5V Datacom bus
� Error amplifier in motor drives
� Transducer buffer amplifier

ORDERING INFORMATION

DESCRIPTION

TEMPERATURE RANGE

14-Pin Plastic SO 14-Pin Plastic DIP

Oto +70�C
oto +70�C

14-Pin Plastic SO

-40 to +85�C

14-Pin Plastic DIP

-40to +85�C

ORDER CODE NE5234D NE5234N SA5234D SA5234N

PIN CONFIGURATION
N, and D PACKAGES
OUTPUT4 ~NPUT4 +INPUT4
GND

June 28, 1990

63

853-1445 99885

Signetics RF Communications
Matched quad high-performance low-voltage operational amplifier

Product specification
NE/SA5234

ABSOLUTE MAXIMUM RATINGS

SYMBOL

PARAMETER

Vee Single supply voltage

RATING 7

UNITS
v

VEsO

ESD protection voltage at any pin5 human body model
robot model

2000

v

200

v

Vs

Dual supply voltage

�3.5

v

I'

Vop Voltage at any device pin1

Vs�0.5

v

lop Current into any device pin1 V1N Differential input voltage2 VcM Common-mode input voltage (positive) VcM Common-mode input voltage (negative)

�50

mA

0.5

v

Vee +0.5

v

VEE� 0.5

v

Po Power dissipation3

TJ

Operating junction temperature3

500

mW

+150

oc

Supply voltage allowing indefinite output short Vsc circuit to either rail3,4

7

v

TsTG TsoLo

Storage temperature range Lead soldering temperature (10sec max)

-65 to +150

oc

+300

oc

9JA Thermal impedance

14 pin Plastic DIP

80

�CIW

14 pin Plastic SO

115

�CIW

NOTES: 1. Each pin is protected by ESD diodes. The voltage at any pin is limited by the ESD diodes. 2. The differential input of each amplifier is limited by two internal diodes, connected in parallel and opposite to each other. For more differential
input range, use differential resistors in series with the input pins.
3. The maximum operating junction temperature is +150�C. At elevated temperatures, devices must be derated according to the package ther-
mal resistance and device mounting conditions. Derates above +25�C: F package at 6.7mWt�C; N package at 9.5mWt�C; D package at
6.25mWt�C. 4. Simultaneous short circuits of two or more amplifiers to the positive or negative rail can exceed the power dissipation ratings and cause
eventual destruction of the device. 5. Guaranteed by design.

RECOMMENDED OPERATING CONDITIONS

SYMBOL

PARAMETER

Vee Single supply voltage

Vs Dual supply voltage

VcM Common-mode input voltage (positive)

VcM Common-mode input voltage (negative)

TA Temperature

NE

SA

RATING +2 to +5.5 �1 to�2.75 Vcc+0.25 VEE� 0.25
Oto +70 -40 to +85

UNITS
v v v v
oc oc

June 28, 1990.

64

Signetics RF Communications
Matched quad high-performance low-voltage operational amplifier

Product specification
NE/SA5234

DC ELECTRICAL CHARACTERISTICS Vee= 2 to 5.5V, Vee = OV, TA= 25�C; Vee< VeM <Vee; unless otherwise stated.
LIMITS

NE5234

SA5234

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

Ice

Supply current

Vee =5.5V
Vee = 5.5V over full temperature range

2.8

3.5

3.0

4.2

Vos Offset voltage

Over full temperature range

�0.2

�4

�0.4

�5

!Nos/AT

Offset voltage drift with temperature

4

A Vos

Offset voltage difference between any amplifiers in

0.4

3

the same package at the common mode level1

Over full temperature range

0.8

4

los

Offset current

Over full temperature range

�3

�20

�4

�30

t>loslAT Offset current drift with temperature

0.02

�.3

Vee< VeM <Vee +0.5V -150

-90

la

Input bias current,

Over full temperature range

-175 -100

Vee +1V < VeM <Vee

25

70

Over full temperature range

35

100

Ala/t.T

Input bias current drift with temperature

0.5

Input bias current difference Vee< VeM <Vee +0.5V

10

30

2.8 3.2 �0.2 �0.6

4

0.4

1.2 �3 �6 0.03

-150 -200

-90 -150
25 35

0.5 10

3.5

mA

4.3

mA

�4

mV

�5

mV

�Vf'C

3

mV

4

mV

�30

nA

�60

nA

�.3

nA/�C

nA

nA

75

nA

120

nA

nAf'C

30

nA

Ala

between any amplifier in the Over full temperature

same package at the same

range

25

50

50

70

nA

common mode level.

Vee +1V < VeM <Vee

5

20

5

20

nA

Over full temperature range

15

30

25

50

nA

VeM Common-mode input range

Voss6mV

Vee-0.25

Vcc+0.25 Vee-0.25

v Vee+0.25

Voss 6mV over full temperature range

Vec-0.1

Vee+0.1 Vee-0.1

Vee+0.1

v

Common-mode rejection ratio, small signal

Vee < VeM < Vee+0.5V, Vee+1V<VeM<Vee

90

100

90

100

dB

CMRR

Over full temperature range

90

100

80

90

dB

Common-mode rejection ratio, large signal

Vee< VeM <Vee

100

100

dB

Over full temperature range

90

90

dB

PSRR Power supply rejection ratio

Vee< VeM <Vee

80

100

Over full temperature range

80

90

80

100

dB

80

90

dB

June 28, 1990

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Matched quad high-performance low-voltage operational amplifier

Product specification
NE/SA5234

DC ELECTRICAL CHARACTERISTICS (continued)

SYMBOL

PARAMETER

TEST CONDITIONS

NE5234

LIMITS

SA5234

MIN TYP MAX

MIN TYP MAX

UNITS

Peak load current, sink and

IL

source

10

15

Over full temperature range

5

10

10

15

mA

I'

5

10

mA

AvoL Open-loop voltage gain
Output voltage swing Vour

90

110

90

110

dB

Over full temperature range

90

90

dB

IPEAK = 0.1mA

VEE+0.05

Vcc-0.05 VEE+0.1

Vcc-0.1

v

IPEAK = 10mA

VEE+0.25

Vcc-0.25 VEE+0.25

Vee-0.25 v

IPEAK = 5mA over full temp range

VEE+0.22

Vcc-0.2 VEE+0.2

Vec-0.2

v

Output voltage swing for Vee= 2.75V, VEE= -2.75V

RL= 2k!l RL =soon,

VEE+0.2 VEE+0.25

Vcc-0.2 VEE+0.2 Vec-0.25 VEE+0.25

Vee-0.2 v Vcc-0.25 v

NOTES: 1. These parameters are measured for VEE< VeM < VEE+.5Vand for VEE+1V < VeM <Vee. By design these parameters are intermediate for
common mode ranges between the measured regions.

AC ELECTRICAL CHARACTERISTICS TA= +25�C; Vee= 2 to 5.5V; RL = 10k; CL= 100pF; unless otherwise stated.

LIMITS

NE5234

SA/SE5234

SYMBOL

PARAMETER

TEST CONDITIONS

MIN TYP MAX

MIN TYP MAX

UNITS

SR Slew rate

Over full temperature range

.5

0.8

BW Unity gain bandwidth: -3dB

Over full temperature range

2

2.5

4.0

9M

Phase Margin

CL= 50pF

55

ts

1% settling time

Av= 1, 1V step

1.4

VN Input referred voltage noise

Av= 1, Rs =On, at
1kHz

25

THO Total harmonic distortion

10kHz, 1Vp.p, Av= 1

0.1

.5

0.8

V/�s

2

2.5

4.0

MHz

55

deg

1.4

�s

25

nV/ Hz112

0.1

%

OUTPUT INVERSION PREVENTION
Vee
sv

CONVENTIONAL OP AMP

= VGND

SIGNETICS NE5234

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Using the NE/SA5234 amplifier

Application note
AN1651

Author: L. Hadley

I. SUMMARY
The NE/SA5234 is a unique low-voltage quad operational amplifier specifically designed to operate in a broadly diverse environment. It is an enhanced pin-for-pin replacement for the LM324 category of devices. Supply conditions can range from 1.8V to 6.0V with a resultant current drain of 2.8mA,-700�A per op amp.
Most notable are the input and output dynamic range characteristics of the individual op amps. The common-mode input voltage can actually exceed the positive and negative supply rails by 250mV with no danger of output latching or polarity reversal. In addition, the output of each op amp will swing to within 50mV of the supply rails over the full supply range.
The frequency related characteristics are also above average for low voltage devices in this class. Internal unity gain compensation makes the NE5234 very resistant to any tendency to oscillate in low closed-loop gain configurations. Even so, a unity-gain bandwidth of 2.5MHz is retained. Slew rate is 0.8V/�s and each op amp will settle to a 1% of nominal level within 1.4�s.
II. DETAILED DESCRIPTION
Input Stage
The input differential amplifier consists of a compound transistor structure of parallel NPN and PNP transistors which account for the unique over-drive characteristics of the NE5234. Referring to Figure 1, it is seen that the NPN pair, 01 and 02, allow the input to operate in the common-mode input voltage range of 1V above VEE� This region is designated the N-mode region in Figure 3a. Operation in the common-mode range below 1V transfers the input stage into the P-mode of operation.
In the N-mode operating condition, collector current from 01 and 02 is summed in the output emitter node of 010 and 012 respectively. 01 's base is the non-inverting input and 02's base the inverting input node for the amplifier.
Linear operation between the two modes is governed by a current steering circuit consisting of 05,6 and 7 in conjunction with voltage reference VB1. Operation in the

(+) IN(-)

IN 07

RIO R11
012 VB1

YBtAS Q9

R8

RB

Figure 1. NE5234 Input Stage

N-region of the common-mode range will automatically cause 05 to transfer the IB1 current source to 07 and the NPN transistor pair 01 and 02. Operation below the 1V level at the inputs allows the current from IB1 to be fed directly to 03 and 04 emitters giving them priority in processing the signal and linearizing their transfer function. (The sum of the NPN and PNP input pair currents remain constant.)

CONVENTIONAL OP AMP

Operation in the common-mode range near the positive supply rail would normally cause the input stage NPN transistor's base collector junction to become forward biased (base current flow directly to the collector circuit) reversing the collector current flow direction. In a conventional op amp, this would have the adverse effect of reversing the output signal polarity as the operating region is traversed by the input signal. (see Figure 2)
To prevent this from occurring, large geometry diode-<:onnected transistors are cross-connected to the opposite NPN collector, (01, 02). This current, in turn, is summed at the emitter of 012 pulling it above the Vee rail voltage and preventing polarity reversal. The inverse condition occurs when 02 is driven above the positive rail, with 01 O emitter being pulled up and signal polarity preserved. (See Figure 1)

Yee

Y1N~

~

Your

= YGND

V \J C> V1N Y our

Yee
~fsY

r

'C.TYGND

SIGNETieS NES234
Fl ure 2. Out ut Inversion Protection

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Using the NE/SA5234 amplifier

Aj)plication note
AN1651

Intermediate Amplifier and Output Stage (Figure 4)
The intermediate stage is isolated from the input amplifier by emitter followers

reaches 15 milliamperes, drive current to the stage is shunted away from current sources IBS or IB9 reducing base current to driver transistors 072 and 082 respectively.

"N-MODE" CMRR

"LARGE SIGNAL"

to prevent any adverse loading effect. This stage adds gain to the over all amplifier and

The prevention of saturation in the output stage is achieved by saturation detectors

VEE+1 < VcM <Vee CMRR
,,,-.~.~~~;;;.~,~.=~

translates levels for the following class-AB current-control driver. Note that 12 is the inverting input and 11 the non-inverting input. The output is taken from multiple collectors on the non-inverting side and provides

078 and 088. When either 071 or 081 approaches saturation, current is shunted away from the driver transistors, 072 or 083 respectively.

',:1

matching for the following stage.

Class-AB control of the output stage is

Ill. CHARACTERISTICS

NE5234 Common-Mode Operating Regions
Figure 3.
For negative going input signals, which drive the inputs toward the VEE rail and below, another set of diode-connected transistors come into operation. These steer the current from the input into 08 or 09 emitter circuits again preventing the reversal effect.
Figure 3 shows graphically how the N and P
mode transitions relate to the common-mode

achieved by 061 and 062 with the associated output current regulators. These act to monitor the smallest current of the non-load supporting output transistor to keep it in conduction. Thus, neither 071 or 081 is allowed to cutoff but is forced to remain in the proper Class-AB region.
Overload protection is provided by monitor circuits consisting of R76-D2 for sinking and R86-D3 for sourcing condition at the output. When the output current, source or sink,

Internal Frequency Compensation
The use of nested Miller capacitors C2 through CS, in the intermediate and output sections, provides the overall frequency compensation for the amplifier. The dominant pole setting capacitor, C2, provides a constant SdB/octave roll-off to below the unity gain frequency of 2.SMHz. Figure 5 shows the measured frequency response plot for various values of closed-loop gains.

input voltage and the offset voltage Vos-

les les

i
193 INTERMEDIATE STAGE

CURRENT CONTROL
Flgure4.

October 7, 1991

68

OUTPUT CLASS AB OUTPUT

Signetics RF Communications
Using the NE/SA5234 amplifier

Application note
AN1651

100
80
dB 80 G1000 40

~
N
l'i. ~
~ ~
N ~

N
20
r-:~

0 10Hz

100Hz

1kHz

10kHz FREQUENCY

100kHz

Figure 5. NE5234 Closed Loop Gain vs Frequency

~
1MHz

+2.SV~
1.r~
\: + 34

-Vu

471<

?1on 100 �10

600'2
~

HP 3585 SPECTRUM
ANA~VZER

Figure 6. Test Circuit

10�1o6

IV. NOISE REFERRED TO THE
INPUT
The typical spectral voltage noise referred to each of the op amps in the NE/SA5234 is specified to be 25nV/./Hz. Current noise is not specified. In the interest of providing a balance of information on the device parameters, a small sample of the standard NE5234s, were tested for input noise current. While this data does not represent a specification, it will give the designer a ball park figure to work with when beginning a particular design with the device. For completeness I have provided the corresponding spectral noise voltage data for the same sample. The data was taken using an HP3585A spectrum analyzer which has the capability of reading noise in nV/./Hz.

The test circuit is shown in Figure 6. As is typical for such measurements the amplifier under test is terminated at its input first with a very low resistance, for the voltage noise reading, followed by the same test with a high value of resistance to register the effect of current noise. The amplifier is set to a non-inverting closed-loop gain of 20dB. Dual supply operation was chosen to allow direct termination of the input resistors to ground.
The measurements were made over the range from 200Hz to 2kHz. Each sample is measured at 200Hz, 500Hz, 1kHz and 2kHz. The data is averaged for each frequency and then the small sample distribution is derived statistically giving the standard deviation relative to the mean.

Referring to the graph in Figure 7a, the equivalent voltage noise is seen to average 18 nV/vHz. The 95% confidence interval is determined to be approximately one nV/vHz. The majority of the errors which contribute to this measurement are due to the thermal noise of the parallel combination of the feedback resistor network, in addition to the 1on termination resistor on the non-inverting input. At 300� Kelvin a 1on resistor generates 0.4 nV/vHz and the feedback network's equivalent resistance of 90n generates 1.2nV/vHz. Their order-of-magnitude difference from the main noise sources allows them to be neglected in the overall calculation of total stage noise.
En for Rs= 1on -nV/Hz
22

nV

oo.i~ liiZ 19

95%j

18 .IS;:N

l'..J

17

.L ~
v!-"'

16 100 200
o.

2000
a.
pA//iiZ

10000

1~ Inp 10

0.1

t-H

100 200

1---1
)11
I p1k 2k

b.

Flgure7.

1 l1Hzl

Noise current is measured across a 47kn resistor and averaged in the same manner. The thermal noise generated by this large resistance is not insignificant. At room temperature it is 28nV/./Hz and must be subtracted lrom the total noise as measured at the output of the op amp in order to arrive at the equivalent current generated noise voltage. Figure 7b shows the derived current noise distribution for the small sample of 10 NE5234 devices. The result shows that noise current in the 200Hz to 2kHz frequency is typically 0.2pA/vHz. The 1/1 region was not determined for either current or voltage noise.

October 7, 1991

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Using the NE/SA5234 amplifier

Application note
AN1651

V. GUIDE LINES FOR MINIMIZING
NOISE When designing a circuit where noise niust be kept to a minimum, the source resistances should be kept low to limit thermally generated degradation in the overall output response. Orders-of-magnitude should be kept in mind when evaluating noise � performance of a particular circuit or in planning a new design. For instance, a transducer with a 1Okn source resistance will generate 2�Vof RMS noise over a 20kHz bandwidth. Using the graphical data above, total noise from a gain stage may be calculated.-

Amplifier Noise Voltage

EQ 1.

25nV/fHZ�fBW = 3.5�VRMS

BW = IOkHz

Noise from source 1Okn Resistance-

Noise Voltage from source resistance EO 2.

14nV/fih � fBW = 2<)1VRMS

Current generated noise

E03.

0.2pA/fih�lo'�fBW = 0.28�VRMs

The total noise is the root-of-the-sum-of-the-squares of the Individual noise voltages-

J En = (35f + (2.0)2 + (0.28)2

E04.

= 4.04�VRMS

To determine the signal-to-noise ratio of the stage we must first choose a stage gain, make it 40dB, and a signal voltage magnitude from the transducer which we will set at 10mVRMS� The resulting signal-to-noise ratio at the output of this stage is determined by first multiplying the gain times the signal which gives 1VRMS with a resultant noise of 400�VRMS� The signal-to-noise ratio is calculated as

EQ5. S/N 201og10 (1.0/4x1o-4) = 68d8

This is quite adequate for good quality audio applications.

Next, assume that the bandwidth is cut to 3.0kHzwith an input of 1mVRMS� The stage gain is kept at 40dB. The total noise is calculated below. nie RMS noise is modified by the ratio of the root of the noise channel bandwidths.

[ ~] EQ6. = ~ �En 1.(i�VRMS v20xlo'

1VRMS SIGNAL +1.lmYRllS NOISE �100
�10

40dB CIRCUIT

ST111JO DISTORTION ANALVZER
=

F ure9.

Amplified Noise= 160�VRMs

[ x1~] S/N

100 EQ7.
20log10 1.6x1u � ,

= S6dB

A 56dB SIN will provide superior voice channel communications �

VI. MULTIPLE STAGE
CONSIDERATIONS Since multiple noise generators are non-�iherent, their total effect is the root-of-the-sum-of-the-squares of the various noise generators at a given amplifier input.

This makes orders-of-magnitude lower noise sources less important than the higher magnitude source. Therefore, when considering the combined signal-to-noise of multiple stages of gain, the first stage in a chain dominates making its design parameters the most critical. For this reason it is good practice to make the preamp stage gain as high as practical to boost signal levels to the second stage allowing at least an order-of-magnitude above the second-stage noise. For instance, a signal input which exceeds the input noise of the following stage by a factor of 10:1 will only be degraded by 0.5% or -46dB, neglecting the
first-stage noise. If we use the preceding example with a first-stage output signal of

October 7, 1991

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Using the NE/SA5234 amplifier

Application note
AN1651

100mVRMS and a 56dB S/N, and an output noise of 0.16mV. Following this with a 10kHz band limited gain-of-10 second-stage, with a 1001<.Q noise source at the non-inverting input, the combined S/N is calculated as follows: (assume a 1oon source resistance from amplifier #1)
The Second stage output noise is:
EQ8.
[J(0.163xlfr3)2+ (J4KT� 100 � 10,000)2]. 10
= l.6mV
K = Boltzman'sConstant = l.38x!0-23 ~
DegKe/vin
T = 300�K ; BW = IOkHz
The amplified output signal = 1VRMS
EQ 10.
S/N = 20log10 (l-.6x-1l-0-, )
= 56dB
Note that there is no effect from the second-stage thermally generated resistor noise due to the dominating effect of the first-stage amplified noise being much greater than the input noise of the second-stage. In addition the equivalent noise resistance of the second-stage is essentially the output resistance of the first-stage plus any series resistance used in coupling the two. This is the parallel combination of source resistance with input terminating or biasing resistance.
VII. LOW HARMONIC DISTORTION
The NE/SA5234 is extremely well adapted to reducing harmonic distortion as it relates to signal level and head room in audio and instrumentation circuits. Its unique internal design limits overdrive induced distortion to a level much below that experienced with other low voltage devices. As will be shown, the device is capable of operating over a wide supply range without causing the typical clipping distortion prevalent in companion operational amplifiers of this class.
A series of tests are shown to allow you to see just how resistant this device is to generating clipping distortion. Two different gain configurations were chosen to demonstrate this particular feature: unity gain non-inverting and 40dB non-inverting. The test set-up was as shown in Figure 9. The Harmonic Distortion analyzer used to make the measurements was a Storage

Vee= 1.BV
UNITY GAIN
L

-j_

j

0

0.1

v

1.0

a.

Vee =2.ov
UNITY GAIN
l

0 0.1
r:.M124

J
r}-
.Ll
v b.
Vee= 3.ov
UNITY GAIN

o~

0.1

v

c.

Figure 10.

1.1
_L
ls2347
v 1 1.1

Technology ST1700. The test frequency is 1kHz. For single supply operation, as previously covered, the amplifier should be biased to half the supply voltage to minimize distortion. Operation with dual supplies is simpler from a parts count standpoint as isolation capacitors are not required. Also the time constants associated with charging and discharging these is eliminated. Figure 1Oa,b and c shows the total harmonic distortion in percent versus input voltage level at 1kHz in VRMS for a non-inverting, unity gain NE5234. The load on the amplifier output is 1Okn. Beginning with a supply voltage of 1.BVand an input level of 0.1VRMS� distortion is well below 0.2% ad remains there up to an input level just over 0.5VRMS (1.4Vp.p) and increases to 0.4% for for 0.6VRMS (1. 7Vp.p).

Vee= 3.ov
- GAIN -40dB

i - - - - - .1 - -
0 0.1

RL = 10k.n
v a.

t
L J
1.1

Vee=2V RL =10k/600n
2.s----~'-.,...---~----~

..... 06.~

~~...i..~(__L_ _L __

0.1

v

b.

__J
1.1

THO tor Vee= 1.av

0.1

v

0.9

c.

Figure 11.
For a 2V supply, the input levels increase to 0.65VRMS and 0. 7VRMS� respectively for similar levels of distortion. With a supply voltage of 3.0V the input may be increased to 1VRMS before THO rises to 0.2% and 1.1VRMS for only 0.8% THD. Operation with a soon load will only raise the THO figures slightly. Byway of comparison, Figure 10c shows the greatly reduced dynamic range experienced when an LM324 is plugged into the test socket in place of the NE5234. Note that The THD is completely off scale for the case of 1.8 and 2.0V supply, then is barely usable for the low level end of the 3.0V supply example. Figure 11a, b, andcdemonstrates the effect on harmonic distortion when closed loop gain is increased to 40dB in the non-inverting mode. It is evident that little increase in THD levels result. The graphs for

October 7, 1991

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Using the NE/SA5234 amplifier

Application note
AN1651

the 2.0 and 3.0V supply case also include

optimizing the Loop-gain. For example, a

additional information on the effect of a soon voice-band audio stage which requires 3kHz

Slew Rate (SR) Is the time-rate-of-change of the signal voltage during any complete cycle,

load on distortion.

bandwidth, should be limited to a closed-loop that is over the range of Oto 2lt. This

gain of 40dB for lowest distortion in the

amounts to taking the time derivative of the

output signal. For higher quality audio

sine wave which results in multiplying the

VIII. GAIN-BANDWIDTH VS

applications requiring a 20kHz bandwidth, the cosine by the factor '2ltf'.

CLOSED LOOP FREQUENCY RESPONSE Figure 5 shows the small signal frequency

closed-loop gain must be limited to 20dB. This results in a Loop-gain of 20dB at the highest signal frequency.

An example of the trade off between signal amplitude and frequency is shown below for the NE5234 slew rate of O.BV/�s. As shown

11

response of the NE5234 versus closed-loop A second consideration in the list of

in Figure 13, the mal<imum allowable

gain in dB. The test circuit is shown in

frequency dependent parameters is the effect amplitude signal which can be reproduced is

Figure 6. The plot is taken from measured

of amplifier slew rate. Not only is it frequency determined by the slew rate response line

data and thus shows how each value of

dependent but it is also a function of signal

which gives peak output volts versus

closed-loop gain coincides with the open-loop amplitude, as we shall see in the next

frequency in Hertz.

response curve. The NE/SA5234's

section.

Mathematically, slew rate is determined, by

open-loop gain response has a uniform

the equation below, as the derivative of the

SdB/octave roll-off which continues beyond

sine wave signal. The resultant slew rate

2.5MHz. This factor guarantees each op

function changes with both frequency and

amp in the IC a high stability in virtually any

amplitude.

gain configuration. In making these

measurements, dual supplies of �2.5V were

GAIN

= Slew Rate Vp (2.ir f) cos (2.ir f I)

used in order to allow a grounded reference

Note that maximum slew rate occurs where

plane and no coupling capacitors which might

the input sine wave signal crosses the values

cause frequency related errors.

of 0, 1t, and 2lt on the radian axis. To get a

A critical parameter which affects the reproduction quality of complex waveforms is the gain-bandwidth-product of the operational amplifier. Essentially, this is a measure of the maximum frequency handling characteristics

I
Is
Ffgure 12.

feel for what this means in regards to the typical low voltage circuit, let us consider a 1VRMS sinusoidal input to a unity gain amplifier. The peak voltage in the above equation is 1.414V. One can then calculate

of any operational amplifier for a given closed-loop gain. As is evident from the graph, the NE/SA5234 has a 2.5MHz unity gain cross-over frequency...much higher than most other low voltage op amps. For comparison, the �A741 has a gain-bandwidth-product of 1MHz, as do the LM324 and the MC3403.
IX. LOOP�GAIN

X. SLEW RATE RESPONSE The slew rate of an operational amplifier determines how fast it can respond to a signal, and is measured in volts-per-microsecond. The NE5234 has a typical slew rate of O.BV/�s. Let us see just what this means in terms of signal handling capability. If a sinusoidal input signal, Vs. is used as reference, it is specified by its frequency and peak amplitude, Vp as follows:

the required slew rate to faithfully reproduce this signal for various signal frequencies. Or with a given slew rate and a required peak signal amplitude, the maximum frequency before slew rate limiting occurs may be determined. For example using the above amplitude of 1VRMS� and the slew rate of the NE5234 which is 800,000V/sec, one determines that the highest frequency
component which may be reproduced before
slew rate distortion occurs is:

The dynamic signal response of any

= Vs Vr sin ('brf t)

EQ.13

closed-loop amplifier stage is a function of

the Loop-gain of that particular stage.

Loop-gain is equal to the open-loop gain in

VpK=1.086V

dB, at a given frequency, minus the

closed-loop gain of the stage. The greater the Loop-gain, the lower the transfer function error of the device. Essentially, any parametric error is reduced by the factor of the Loop-gain. This includes output resistance and output signal voltage accuracy. It is good practice then to

I IIII

VpK�830mV

if

a
>

+4++++

VpK�100mV

" ~ ~ ,....

maximize Loop-gain to the degree that stage

gain may be sacrificed for bandwidth. In

some cases it is actually better to use two

stages of gain in order to preserve signal quality than to use one high gain stage. Of

0.022000

course, there is a trade-off between the aforementioned factors that affect the

(Hz)
Figure 13. Slew Rate Limiting Amplitude vs Frequency

signal-to-noise ratio of the stage and

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Application note
AN1651

,--------------,

+ Yee / /

~~/

=~ A

A.I

v~ - - - - - -

:

-2-

'

', Y1N INPUT ISOLATION
Figure 14. Single Supply Blasing In Cascade

In all cases proper bypassing of the NE5234 supply leads (Pins 4 and 11) is very important particularly in a high noise environment. Bypass capacitors must be of ceramic construction with the shortest possible leads to keep inductance low. Chip capacitors are superior in this respect complimenting the increased use of surface mounted integrated devices. Note that both the NE5234D and the automotive grade SA5234D are available and are the surface mount versions of the device.
R R Yee

800,000 V/sec / 27t � 1.414 volts peak= 90,090Hz. A graphical representation of this relationship is shown in Figure 13. By using this graph along with the information in the preceding Figure 1Oand Figure 11, which relate usable signal levels versus power supply voltage, the dynamic behavior of a particular design may be predicted. For instance, given a single supply configuration operating at 2.0V, Figure 1Ob shows an upper limit to input amplitude of 0.7VRMS� or about 1V peak for 1% THO. Using this level with the data in Figure 13 leads to a figure of 116kHz as an upper frequency limit for a unity gain amplifier stage operating at 2V DC.

dVs = Vr 0> cos 0>t dt
=Slew Rate

EQ 14.

XI. PROCEDURES
Single Supply Operation
When the NE/SA5234 is used in an application where a single supply is necessary, input common-mode biasing to half the supply is recommended for best signal reproduction. Referring to Figure 14, a simplified inverting amplifier input stage is shown with the simplest form of resistive divider biasing. The value of the divider resistance R is not critical and may be increased above the 1Okn value shown as long as the bias current does not interfere with accuracy due to DC loading error. However the divider junction must be kept at a low AC impedance This is the purpose of bypass capacitor Cs. Its use provides transient suppression for signals coming from the supply bus. A low cost 0.1�F ceramic disk or chip capacitor is recommended for suppressing fast transients in the microsecond and sub-microsecond region.

Foil capacitors are simply too inductive for any high frequency bypass application and should be avoided. If low frequency noise such as 60Hz or 120Hz ripple is present on the supply bus, an electrolytic capacitor is added in parallel as shown. The common-mode input source resistance, Rs, should also be matched within a reasonable tolerance for maximizing the rejection of induced AC noise.
The output of the first stage is now fixed at the common mode bias voltage and the amplified AC signal is referenced to this constant value. Capacitive coupling to the inverting input is of course required to prevent the bias voltage from being multiplied by the stage gain. Second stage biasing may now be provided by the output voltage of the first stage if non-inverting operation is used in the former. For lowest noise in a high gain input stage, the magnitude of the input source resistance is critical; low values of resistance are preferred over high values to minimize thermally generated noise.
Non-Inverting Stage Biasing
Non-inverting operation of an amplifier stage with single supply is similar to the previous example but the bias resistor Rs must now be sufficien~y high to allow the signal to pass without significant attenuation. The input source resistance reflects the output resistance of the preceding stage or other sourcing device such as a bridge circuit of relatively high impedance. A simple rule of thumb is to make the bias resistor an order of magnitude larger than the generator resistance. Again the feed back network must be terminated capacitively. In this case R1 and the generator resistance should be matched and then Rs is matched to the feedback resistance ,RF.

Figure 15. Non-Inverting Blasing
APPLICATIONS EXAMPLES
Instrumentation
Strain Gauge Bridge Amplifier The circuit below shows a simple strain gauge circuit with a gain of 100 (40dB) and operated from a single supply. The chart illustrates the transfer function of the circuit for a single order-of-magnitude signal differential range from the bridge beginning with 5mV up to 50mV. The circuit is operated from a single 5V supply, but could equally as well be configured to use a dual balanced supply. It is immediately evident that the wide common-mode output range of the NE5234 is very advantageous in handling this wide range of signals with good linearity due to this feature.
A variation on this particular idea is the remote strain gauge circuit operating from a three wire line, one of which is the shield. This full-<lifferential input circuit has balanced

October 7, 1991

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Using the NE/SA5234 amplifier

Application note
AN1651

Figure 16. A 4-20mA Current Loop

12k 1.2Mn

IV2 -V1I 5.9mV
25.6mV 46.&mV

YD.
0.5V
2.SOV 4.63V

S.G.: Ma1ched Strain Gauge elements

Figure 17. Strain Gauge Ampllfler

+Vee

11

-= \

Two-wire, Twisted-pair Shielded Line

Figure 18. Remote Strain Gauge

4-&V DC

October 7, 1991

Figure 19. Solar Regulator 74

input resistance to afford good common-mode noise rejection characteristics. Resistors are metal film or deposited carbon. Supply leads must be carefully bypassed close to the NE/SA5234 with ceramic or chip monolithic capacitors to give optimum noise performance. As shown, an auxiliary sub-regulator may be added to improve the overall DC stability of the bridge signal voltage. A regulator capable of providing the necessary few milliamperes at somewhat reduced voltage for the transducer is shown in one of the following examples. This makes use of one of the op amps in the same device package to provide the voltage regulation. Note that the use of multiple op amps within a single package minimizes the possibility of thermal drift and mismatched response from various DC parameters.
Multiple sets of transducers may be constructed from The NE/SA5234 or the NE5234D surface mount device to form a compact and stable instrumentation package. This is useful for transducer applications in
the measurement of pressure, strain, position and temperature, which have similar circuit configurations. First order temperature compensation of the transducers such as semiconductor strain gauges, or resistive units may be achieved by using one of the gauges as a reference device only. It is thermally coupled to the same member as the active gauge, as shown in the example. (Figure 18)
A 4 to 20mA Current Loop
Some instrumentation installations require the 4-20mA current loop. This addition to the above bridge transducer circuit examples is demonstrated in Figure 16.
This circuit makes use of the remote transducer bridge previously described and adds current loop signaling capability. The voltage-to-current converter consists of an additional op amp from the same NE/SA5234 package combined with a single transistor to drive the current loop. The sensitivity is actually in mA/V, or transconductance, which is equal to 1/RsH� This sensitivity in this particular example is set to 4mA/V. Thus, with a bridge amplifier having a differential gain of 100, an input of 10mV will produce a 4mA output current and 50mV will produce a 20mA output. Of course the line resistance plus receiver resistance must be within the voltage compliance range of the supply voltage to guarantee linear operation over the total range. A negative supply may be used if it is preferred to have the current loop referenced to ground.

Signetics RF Communications
Using the NE/SA5234 amplifier

Application note
AN1651

pc Regulators and Servos
Closely related to DC and low frequency AC linear transducers are DC regulators and servo circuits. The proliferation of many battery, and solar powered remote instrumentation packages results in a need for adaptable circuits which may readily be made up from existing stock IC's. The examples given here are quite simple, but can be very useful to the designer when economy and size are at a premium.
Solar Regulator for 3-Volt CMOS Working with small instrumentation packages which are to operate from solar photovoltaic cells may bring a need for simple sub-regulators for MOS circuits requiring only a few milliamperes of drain current. Figure 19 shows a simple low voltage regulator making use of the particularly excellent DC characteristics of the

NE/SA5234. The regulator becomes an integral part of any functional analog signal processing package such as an environmental data instrumentation unit. The low current drain of the the typical 3V or 5V MOS digital IC allows one sub regulator to serve up to 10 or more such devices. If the instrument package is to be subjected to wide temperature variations, the SA5234 is recommended. A second op amp in the package may serve as a low battery alarm with tone modulator as in radio links, or simple logic level comparator. Overcurrent protection is easily added within the regulator loop to detect short circuit failures and automatically limit the current.
DC Servo-amps Servo control systems for low voltage motor drives require high gain-accuracy and good

r-------------------,

I

I

I

I

I

I

I

I

IC-1
NE5234

10kn

I

+4.SVDC

14 100

o

I

..VR.1-----------_IJI 0.1�F

I

I

DC stability for many applications. Applications such as the position control of air flow vanes, servo valves, and optical lenses or apertures, are typical examples. Figure 20 demonstrates one simple DC motor servo application with position control feedback. The motor is a 3V permanent magnet rotor type used in micro-position applications and is adaptable to battery supply environments.
Position information is received from a multi-tum potentiometer to give adequate resolution. The input voltage may be generated from another potentiometer which is remote from the motor drive unit proper, or from a DIA converter output for micro processor controlled systems. The input voltage range is 1.0 to 3.0V and the supply voltage is 4.5V.

= VR1-3 1.4V
October 7, 1991

Figure 20. Full Bridge Motor Drive 75

Signetics RF Communications
Using the NE/SA5234 amplifier

Application note
AN1651

Active filters
The NE5234 is easily adapted to use in a variety of active filter applications. Its high open-loop gain and excellent unity gain stability make it ideal for high-pass, band-pass and low-pass configurations operated with low voltage single supplies. Its low output impedance also makes it capable of obtaining low noise operation without resorting to separate high current buffers.
Figure 21a shows the circuit for a VCVS low-pass filter with dual supply biasing and
soon output termination. Figure Figure 21b
is a band-pass filter with AC coupled gain network for single supply operation.
Communications and Audio
Stereo Bridge Amplifier
Figure 22 shows two NE5234 ICs in a bridge amplifier application. The choice of split supplies allows DC coupling, both from the input signal source and to the load. The gain is set to a nominal 20dB. Either inverting or non-inverting operation is available. The
soon inverting input impedance is chosen as
in order to match standard audio impedance lines within a system. The use of two such amplifiers will provide stereo operation to
+1OdBm for a soon load.
Voice Operated Microphone
The processing of voice transmissions for communications channels is generally coupled with the need for keeping the signal-to-noise ratio high and the intelligibility optimized for a given channel bandwidth. In addition, when a circuit is battery operated and portable, the requirement to obtain maximum battery life becomes important. The circuit example shown here is aimed at filling the need for a portable voice operated transmitter, cordless phone, or tape recorder. It utilizes the Signetics NE5234 quad op amp in conjunction with the new low-voltage NE578 compandor to create an audio processor capable of operating in just such an environment. Both devices are operational to a low battery voltage of 2.0V. In addition the design further conserves current by automatically shifting the NE578 compandor to standby during the period when no transmissions are being made. Total current consumption at 3.0V is 2.BmA for the NE5234. In the active mode the NE578 draws 1.4mA and this drops to 170�A in the standby mode. This amounts to reducing the supply current demand by approximately 25% in the 'listen mode'.

R;
R1
a. VCVS Low Pase Riter
b. VCVS Band Pau Filter
Fl ure 21. Figure 23 shows the VOX audio circuit example. A description of its operation for voice activated transmission follows. Audio generated by the electret microphone is fed into the non-inverting input of preamp A 1 and the signal amplified by 12dB. The biasing is accomplished by the resistive divider which provides a level of half the supply voltage which is connected through a 1OOk resistor to the non-inverting temninal of A 1. This automatically provides ratiometric common mode biasing set at Vcc/2 for the device. This level is then transferred directly

to the following amplifier, A2, setting its DC operating point. The DC gain of both stage A 1 and A2 are unity so the cumulative DC error is not multiplied by stage gain. The peak voice level is approximately 100mVRMS at the input to A 1 from the microphone and this is boosted to 400mVRMS� The feedback network gain has a low frequency corner at 1SOHz and is flat up to the intersection of the closed loop gain with the open loop gain curve at nearly 500kHz. This would increase the noise bandwidth to an excessive degree unnecessary for voice channel communication. A band limiting network is, therefore, inserted across the feedback resistor to limit response to a nominal 5kHz.
Amplifier stage A2 is used to provide high level audio to the rectifier-filter stage for the rapid generation of a DC control signal for operating the voice activated switch function. Stage A2 gain is set to 20dB in order to allow activation of the voice channel on the rising edge of the first voice syllable. An attack time of 20ms is implemented by adjusting the input charging impedance (Rs) between the rectifier and the A2 amplifier output. AC coupling must be used to isolate the DC common-mode voltage of the amplifier from the rectifier/storage capacitor and to allow only audio frequencies to drive the switching circuit. Amplifier A3 provides a high impedance unity gain buffer to allow a very slow decay rate to be applied to the time constant capacitor, Cr. The output of the storage capacitor reaches approximately 3.2V for a 250ms duration SOOHz burst signal. Diode D1 (1 N914) provides a negative clamp action

BRIDGE AMP #2 NE5234

RIGHT CHANNEL OUT

Figure 22. Stereo Bridge Amp

October 7, 1991

7S

Signetics RF Communications
Using the NE/SA5234 amplifier

Application note
AN1651

10kn

10kn

+4.SV

4---------,

19

16

12

+4.SV

11 NE578

12kn 4.7�F

I

Ro

I

I

IL _ _ _X1_ _ _ _ _ _!1

o~::-J~~OrN

40.21Ul

which forces the full peak-to-peak voltage from A2 to charge the storage capacitor. D2 then acts to charge the capacitor to the peak input voltage minus one diode drop, 0. 7V. Finally, the buffered DC control signal is led to A4 which acts as a threshold comparator with extremely high gain and controlled hysteresis. This provides a positive going signal for releasing the NE578 from its inhibit mode when voice input is present. The NE578 is switched from standby mode when voice input is present. The NE578 is switched from standby mode to the active state by raising the voltage on Pin 8 of the device above 2Y. Shutting the audio channel off requires this pin to be driven below 100mV. This demands the extremely wide output voltage swing of the NE5234 in order to reach this near to the negative rail voltage. The voltage threshold of the comparator, A4, is adjustable by use of the sensitivity control, Rs. It is used to allow the activation level to be raised or lowered depending upon the ambient audio level in the transmitter vicinity.
Other critical parameters in this type of circuit are the attack and decay times of the RC network which controls the operation of the voice operated switch. Attack time determines how quickly the circuit activates alter a quiet period, and the decay time sets

Figure 23. VOX Audio System
how long the transmitter channel stays active between words. It is important to reach an optimum balance between the two time constants in order to allow unbroken transmissions of good quality and no lost syllables. A 100 to 1 attack/decay ratio is used in this particular application and this is primarily set by the value of RA and R0 . A typical delay of two seconds is easily accomplished. Due to extremely high input impedance of the buffer stage A3, Ro may be in the 1 to 2MQ range allowing a reasonable value of storage capacitor to be used.
The Audio Channel Audio input from the preamplifier, A1, is fed directly to Pin 14 of the NE578 compandor. Referring to Figure 24, which shows the internal diagram of the device, it can be seen that this is the compressor portion of the NE578. There is the option in this system to operate either in a 2:1 compressor mode or an automatic level control mode, (ALC). The compressor mode simply makes a 2:1 reduction in the amplitude dynamic range of the input signal and brings it up to the chosen nominal OdB output level which is programmable from 1OmVRMS to 1YAMS� In this particular example it is programmed for a OdB level of 0.42YRMS which is approximately 1Vp.p. This allows for a standardized output

level with good characteristics for FM modulation where peak deviation must be controlled. Figure 25 shows the input-output characteristics of the compressor and ALC. The compressor also has an attack time determined by capacitor C6 on Pin 11. Attack time is 1Ok� C6, decay time equals four times this value. An auxiliary amplifier stage is used following the NE578 in order to allow bandwidth and special forms of equalization to be implemented. Note that 2: 1 compression in a transmission will enhance the channel dynamic range and may be used with no further processing at the receiver, but feeding the received signal through the complimentary 2:1 expander will achieve even greater enhancement of the recovered audio. The NE578 contains both operations in the same package. Please refer to Signetics applications note AN 1762 by Alvin K. Wong for complete information on these compandor circuits using the NE578.
Fiber Optic Receiver for Low Frequency Data (Figure 26)
This application makes use of the NE/SA5234 to detect photo-optic signals from either fiber or air transmitted IR (Infra-red) pulses. The signal is digitally encoded for the highest signal-to-noise ratio. The received

October 7, 1991

77

Signetics RF Communications
Using the NE/SA5234 amplifier

Application note
AN1651

signal is sensed by an IR photo diode which has its cathode biased to half the supply voltage (2.5V). The first gain stage is configured as a transimpedance amplifier to allow conversion from the microampere diode current signals to a voltage output of approximately 10mV0.p. The second stage provides a gain-of-ten amplifier to raise this signal level to 1V peak amplitude. This stage is directly coupled from the preamplifier stage in order to provide the necessary common-mode voltage of 2.5V. Its gain control network is capacitively coupled to prevent DC gain as is required in single supply configurations. Since this is essentially a pulse gain stage, low frequency gain below the signal repetition rate is not needed. The third stage acts in a limiting amplifier configuration and its output is squared to swing approximately 5V, the standard TTL level. Again common-mode

biasing is passed along from each of the stages up to the last in order minimize parts and simplify circuit layout. The final stage is a simple buffer amplifier to allow the receiver to drive a low impedance long wire line of 6000 to 9000 resistance. Some rise time
response adjustment may be required. This
is easily achieved following stage three by using RrCT to limit the rate of change of the signal voltage prior to the buffer. Note that the last stage acts as a zero-crossing detector. This maximizes noise immunity by allowing a transition only after the third stage output voltage has risen above 2/3Vcc-
Phase inversion may be accomplished, if the
logic level signals are polarity reversed, by making stage 3 inverting and AC coupling the input signal with a sufficiently large capacitor to reduce droop. Stage 3 must then be biased by connecting its non-inverting node to bias point 'A'. This provides a 2.5V

threshold for the proper switching operation of the stage. However, care must be taken not allow the network's time constant to become code dependent as to the average low frequency signal components or errors will result in the output signal.
The advantage of this particular circuit is that it has the simplicity of single supply operation along with the capability of a large output swing making it fully TTL compatible
REFERENCES:
Signetics, a North American Philips Company. Linear Data Manual, Volume 2 : Industrial. Sunnyvale: 1988.
Wong, Alvin K. Companding with the NE577 and NE578..Signetics Applications Note AN1762: September 1990.

�R1, R2 and R3are1% resistors. Figure 24. Block Diagram of NE578 Test and Application Circuit

October 7, 1991

78

Signetics RF Communications
Using the NE/SA5234 amplifier

+16dB OdB

VRMS
2.65V 1.67V 420mV

I
[ )2

COMP~:smON

INPUT TO AG AND!RECT

- J - - <COMPRESSOR OUT)

(EXPANDOR IN)

-1!- __.e......:

[ 1�
REL LEVEL

ABS LEVEL

EXPANDOR DB OUT

dBM

--..!!-
+16.0
+12.0

+10.&8 +6.68

o.o

-5.32

-20dB

42mV

-211

-25.32

-40dB 4.2mV

-40

-45.32

-80dB

-811

-65.32

-80dB

42�V

-811
Figure 25. NE570/571/SA571 System Level

-85.32

__ ___.(..,;):::

Application note
AN1651

T
Figure 26. Fiber Optic Data Receiver

October 7, 1991

79

Signetics RF Communications
Using the NE/SA5234 amplifier

Application note
AN1651

I

-3V

!_ _ L _ - - - - - - --{..___ _,~-\,_\,_1"�........ 111_00__,

/777777777 Figure27.

October 7, 1991

80

Signetics RF Communications
High frequency operational amplifier

Product specification
NE/SE5539

DESCRIPTION
The NE/SE5539 is a very wide bandwidth, high slew rate, monolithic operational amplifier for use in video amplifiers, RF amplifiers, and extremely high slew rate amplifiers.
Emitter-follower inputs provide a true differential input impedance device. Proper external compensation will allow design operation over a wide range of closed-loop gains, both inverting and non-inverting, to meet specific design requirements.

FEATURES
�Bandwidth - Unity gain - 350MHz - Full power - 48MHz - GBW - 1.2GHz at 17dB
� Slew rate: SOON�s
� AvOL: 52dB typical � Low noise - 4nV..JHz typical � MIL-STD processing available

APPLICATIONS
� High speed datacom � Video monitors & TV � Satellite communications � Image processing � RF instrumentation & oscillators � Magnetic storage � Military communications

PIN CONFIGURATION
D, F, N Packages
NC FREQUENCY COM PENS. +V
Top View

ORDERING INFORMATION

DESCRIPTION 14-Pin Plastic DIP 14-Pin Plastic SO 14-Pin Cerdip 14-Pin Plastic DIP 14-Pin Cerdip

TEMPERATURE RANGE Oto +70�C Oto +70�C
o to +70�C
-55 to +125�C -55 to +125�C

ORDER CODE NE5539N NE5539D NE5539F SE5539N SE5539F

ABSOLUTE MAXIMUM RATINGS1

SYMBOL

PARAMETER

Vee Supply voltage

PoMAX

Maximum power dissipation, TA= 25�C (still-air)2
F package N package D package

RATING �12
1.17 1.45 0.99

UNITS
v
w w w

TA
Tsrn TJ
TsoLD

Operating temperature range NE SE
Storage temperature range
Max junction temperature
Lead soldering temperature (1Osec max)

0 to 70

oc

-55 to +125

oc

-65to+150

oc

150

oc

+300

oc

NOTES: 1. Differential input voltage should not exceed 0.25V to prevent excesive input bias current and common-mode voltage 2.5V. These voltage
limits may be exceeded if current is limited to less than 1OmA. 2. Derate above 25�C, at the following rates:
F package at 9.3mW/�C N package at 11.6mW/�C D package at 7.9mW/�C

November 3, 1987

81

853-0814 91253

Signetics RF Communications
High frequency operational amplifier

Product specification
NE/SE5539

EQUIVALENT CIRCUIT

(12) FREQUENCY COMP. ~------------------1----+---o (1o)+Vcc

(-)14 INVERTING INPUT
(+)1 NON-INVERTING r>-----+---<
INPUT

(&)OUTPUT

(3)-Vcc

November 3, 1987

82

Signetics RF Communications
High frequency operational amplifier

Product specification
NE/SE5539

DC ELECTRICAL CHARACTERISTICS
Vee= �8V, TA= 25�C; unless otherwise specified.

SYMBOL

PARAMETER

TEST CONDITIONS

SE5539 MIN TYP MAX

NE5539 MIN TYP MAX UNITS

Vou1 Vour
Ice+ IcePSRR AvoL AvOL
AvoL

Output voltage swing Output voltage swing
Positive supply current Negative supply current Power supply rejection ratio Large signal voltage gain Large signal voltage gain
Large signal voltage gain

RL = 150Q to GND and +Swing

470Q to-Vee

-Swing

RL = 25Q to GND Overtemp

+Swing -Swing

RL = 25Q to GND TA= 25�C

+Swing -Swing

Vo= O, R1 =~.Over temp Vo=O, R1 =~. TA=25�C Vo= 0, R1 =~.Over temp Vo=O, R1 =~. TA=25�C

!!.Vee= �1 V, Over temp

t.Vcc = �1V, TA= 25�C

Vo= +2.3V, -1.7V, RL = 150!1 to GND, 470Q to -Vee

Vo= +2.3V, -1.7V

Over temp

RL = 2Q to GND

TA= 25�C

Vo = +2.5V, -2.0V

Over temp

RL = 2Q to GND

TA= 25�C

+2.3 -1.5 +2.5 -2.0
46 48

+3.0 -2.1 +3.1 -2.7 14 14 11 11 300
53

+2.3 -1.7
18 17 15 14 1000
47
47 60 58

+2.7 -2.2
2.8 14 2.8 11 200 52
52

v

v

3.5 18 3.5 15
1000 57

v
mA mA mA mA �VN �VN
dB

dB 57
dB

DC ELECTRICAL CHARACTERISTICS
Vee= �6V, TA= 25�C; unless otherwise specified.

SYMBOL

PARAMETER

Vos Input offset voltage

los

Input offset current

Is

Input bias current

CMRR Ice+

Common-mode rejection ratio Positive supply current

Ice-

Negative supply current

PSRR Power supply rejection ratio

VouT Output voltage swing

TEST CONDITIONS

Over temp

TA= 25�C

Over temp

TA= 25�C

Over temp

TA= 25�C

VcM = �1.3V, Rs= 100Q

Over temp

TA= 25�C

Over temp

TA=25�CmA

t!.Vcc = �1V

Over temp

TA= 25�C

Over

+Swing

RL = 150Q to GND

temp

--Swing

and 390Q to -Vee

TA=

+Swing

25�C

--Swing

SE5539

MIN TYP MAX UNITS

2

5

mV

2

3

0.1

3

�A

0.1

1

5

20

�A

4

10

70

85

dB

11

14

mA

11

13

8

11

mA

8

10

300 1000 �VN

+1.4 +2.0

-1.1 -1.7

v

+1.5 +2.0

-1.4 -1.8

November3, 1987

83

Signetics RF Communications
High frequency operational amplifier

Product specification
NE/SE5539

AC ELECTRICAL CHARACTERISTICS
Vee= �8V, RL = 150Q to GND and 470Q to -Vee. unless otherwise specified.

SYMBOL

PARAMETER

BW Gain bandwidth product

Small signal bandwidth

Is

Settling time

SR

Slew rate

tpo

Propagation delay

Full power response

Full power response

Input noise voltage

Input noise current

NOTES: 1. External compensation.

TEST CONDITIONS
AcL = 7, Vo= 0.1 Vp.p AcL = 2, RL = 150Q1 AcL = 2, RL = 150Q1 AcL = 2, RL = 150Q1 AcL = 2, RL = 150Q1 AcL = 2, RL = 150Q1 Av= 7, RL = 150Q1
Rs = 50Q, 1MHz 1MHz

SE5539

NE5539

MIN TYP MAX MIN TYP MAX UNITS

1200 110 15 600
7 48 20 4 6

1200 110 15 600
7 48 20 4 6

MHz MHz
ns V/�s
ns MHz MHz nV/\iHz pA/\iHz

AC ELECTRICAL CHARACTERISTICS
Vee= �6V, RL = 150Q to GND and 390Q to -Vee. unless otherwise specified.

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

BW Gain bandwidth product

Small signal bandwidth

Is

Settling time

SR Slew rate

!po

Propagation delay

Full power response

NOTES: 1. Extemalcompensation.

AcL = 7 AcL = 21 AcL = 21 AcL = 21 AcL = 21 AcL = 21

SE5539
TYP
700 120 23 330 4.5 20

MAX

UNITS
MHz MHz
ns V/�s ns MHz

TYPICAL PERFORMANCE CURVES
NE5539 Open-Loop Phase

~

fo "

w

")..:

~ 190

0.

270

360 1 MHz

10MHz

100MHz

FREQUENCY (Hz)

1GHz

NE5539 Open-Loop Gain

60
1-1-i
50
40

~ ~

2ll 10 1 MHz

~
N

10MHz

100MHz

FREQUENCY (Hz)

1GHz

November3, 1987

84

Signetics RF Communications
High frequency operational amplifier
TYPICAL PERFORMANCE CURVES (Continued)
Power Bandwidth (SE)

Product specification
NE/SE5539
Power Bandwidth (NE)

 4 1----------+--~k------l-----1
~B ,___ _ _ 3dBB.W 3>--------+----_.,...___ __._ _ ___,

~

GAIN(-2)

Vee= �BV

RL � 2kn.

1 MHz

1DMHz FREQUENCY (Hz)

100MHz

300Mhz

3dBB.W.

Vcc=�BV RL= 150kn GAIN(-2)
0 1 MHz

10MHz FREQUENCY (Hz)

100MHz

300Mhz

SE5539 Open-Loop Gain vs Frequency

50

40

iii :!!.

30

z

f� 20

10

Vcc=.,&V RL = 126'2

o~
1 MHz

10MHz FREQUENCY (Hz)

100MHz

REF 3.04V P-P
th -2
;-4
9-s :l! 'l!-4

-10

300Mhz

-12 1MHz

Power Bandwidth

~ _'\ ~

GAIN(-7)
= RL 150!2

~

10MHz FREQUENCY (Hz)

100MHz 300MHz

SE5539 Open-Loop Phase vs Frequency

Gain Bandwidth Product vs Frequency

1MHz

10MHz FREQUENCY (Hz)

100MHz

300MHz

Ay=X10 22

iii 20

z:!!.

1=..
18

Av=X7.5

:;:

" 16

14

12 1MHz

I

Vcc=�&V

J

~RL:150<l

3dB BANDWIDTH -

r-

l

.._,,,,

3dB BANDWIDTH

""""'! ~

J

10MHz

100MHz

300MHz

FREQUENCY (Hz)

NOTE:
'llJlll!IJ//j Indicates typical distribution-55"C ~TA:,:; 125�C

November 3, 1987

85

Signetics RF Communications
High frequency operational amplifier

Product specification
NE/SE5539

CIRCUIT LAYOUT CONSIDERATIONS
As may be expected for an ultra-high frequency, wide-gain bandwidth amplifier, the

physical circuit is extremely critical. Bread-boarding is not recommended. A double-sided copper-clad printed circuit board

will result in more favorable system operation. An example utilizing a 28d8 non-inverting amp is shown in Figure 1.

OPTIONAL OFFSET ADJ.

=

Rj � 750 5% CARBON R2 � 750 5% CARBON R3 � 750 5% CARBON R4 � 36K 5% CARBON

Top Plane Copper' (Component Side)

-V
� oao

VI

9b Q:x)

! o 8 OC9
0co cm

0 0

I �~ 0

NE5539

Vo

w/comp.

-V
R5 � 20k TRIMPOT (CERMET) RF � 1.5k (28dB GAIN) R5 � 47C<l 5% CARBON
Component Side (Component Layout)

RFC 3T # 26 BUSS WIRE ON FERROXCUBE VK 200 0913B CORE BYPASS CAPACITORS 1nF CERAMIC (MEPCO OR EQUIV.)
Bottom Plane Copper�

November3, 1987

Figure 1. 28d8 Non�lnverting Amp Sample PC Layout 86

Signetics RF Communications
High frequency operational amplifier

Product specification
NE/SE5539

NE5539 COLOR VIDEO AMPLIFIER
The NE5539 wideband operational amplifier is easily adapted for use as a color video amplifier. A typical circuit is shown in Figure 2 along with vector-scope1 photographs showing the amplifier differential

gain and phase response to a standard five-step modulated staircase linearity signal (Figures 3, 4 and 5). As can be seen in Figure 4, the gain varies less than 0.5% from the bottom to the top of the staircase. The maximum differential phase shown in Figure 5 is approximately +0.1�.

The amplifier circuit was optimized for a 75W input and output termionation impedance with a gain of approximately 10 (20d8).
NOTE:
1. The input signal was 200mV and the output 2V. Vee was �SV.

75

-V

75
Figure 2. NE5539 Video Ampllfler

Figure 3. Input Signal

Figure 4. Differential Gain <0.5%

NOTE:
Instruments used for these measurements were Tektronix 146 NTSC test signal generator, 520A NTSC vectorscope, and 1480 waveform monitor.

November3, 1987

87

Signetics RF Communications
High frequency operational amplifier

Product specification
NE/SE5539

Figure 5. Differential Gain +0.1�
�1.SpF
Figure 6. Non-Inverting Follower
3.3pF
Figure 7. Inverting Follower

November 3, 1987

88

Slgnetics Industrial
Video amplifier

Product specification
NE5592

DESCRIPTION
The NE5592 is a dual monolithic, two-stage, differential output, wideband video amplifier. It offers a fixed gain of 400 without external components and an adjustable gain from 400 to Owith one external resistor. The input stage has been designed so that with the addition of a few external reactive elements between the gain select terminals, the circuit can function as a high-pass, low-pass, or band-pass filter. This feature makes the circuit ideal for use as a video or pulse amplifier in communications, magnetic memories, display, video recorder systems, and floppy disk head amplifiers.

FEATURES
� 11 OMHz unity gain bandwidth � Adjustable gain from 0 to 400 � Adjustable pass band � No frequency compensation required � Wave shaping with 'llinimal external
components
APPLICATIONS
� Floppy disk head amplifier � Video amplifier

� Pulse amplifier in communications

� Magnetic memory

� Video recorder systems

PIN CONFIGURATION
D, N Packages

ORDERING INFORMATION
DESCRIPTION 14-Pin Plastic DIP 14-Pin SO package

TEMPERATURE RANGE
oto 70�C oto 70�C

ORDER CODE NE5592N NE5592D

EQUIVALENT CIRCUIT
+V

INPUT! G

OUTPUT! OUTPUT2

-V

October 20, 1987

89

853-0888 91020

Signetics Industrial
Video amplifier

Product specification
NE5592

ABSOLUTE MAXIMUM RATINGS
TA=25�C, unless othetwise specified.

SYMBOL

PARAMETER

Vee V1N VcM lour
TA

Supply voltage Differential input voltage Common mode Input voltage Output current Operating temperature range NE5592

Tsra Po MAX

Storage temperature range Maximum power dissipation, TA=25�C (still air) 1

D package

N package

NOTES: 1. Derate above 25�C at the following rates:
D package 8.3mW/�C N package 11.9mW/�C

RATING �8 �5 �6 10
Oto +70 -65 to +150
1.03 1.48

UNIT
v v v
mA
oc oc
w w

DC ELECTRICAL CHARACTERISTICS
TA=+25�C, Yss=�6V, VcM=O, unless othetwise specified. Recommended operating supply voltage is Vs= �6.0V, and gain select pins are connected together.

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

UNITS

Min Typ Max

AvoL

Differential voltage gain

RL=2kn, Vour=3Vp.p

400 480 600

VN

R1N

Input resistance

C1N

Input capacitance

3

14

kn

2.5

pF

los

Input offset current

0.3

3

�A

l01AS V1N

Input bias current Input noise voltage Input voltage range

BW 1kHz to 1OMHz

5 4 �1.0

20

�A

nVi'1Hz
v

CMRR Common-mode rejection ratio

VcM � 1V, k100kHz VcM � 1V, f=5MHz

60

93

dB

87

dB

PSRR

Supply voltage rejection ratio

l1Vs=�0.5V

50

85

dB

Vos
VcM Vour

Channel separation
Output offset voltage gain select pins open
Output common-mode voltage Output differential voltage swing

Vour=1Vp.p; f=100kHz (output referenced) RL=1 kn
RL=~ RL=~ RL=~
RL=2kn

65

70

dB

0.5

1.5

v

0.25 0,75

v

2.4

3.1

3.4

v

3.0

4.0

v

Rour

Output resistance

20

Q

Power supply current

Ice

(total for both sides)

RL=~

35

44

mA

October 20, 1987

90

Signetics Industrial
Video amplifier

Product specification
NE5592

DC ELECTRICAL CHARACTERISTICS
Vss=�6V, VcM=O, 0�c s TA s 70�C, unless otherwise specified. Recommended operating supply voltage is Vs= �6.0V, and gain select pins are connected together.

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

UNITS

Min Typ Max

AvoL R1N los lalAS V1N
CMRR

Differential voltage gain Input resistance Input offset current Input bias current Input voltage range
Common-mode rejection ratio

RL=2k0, Vour=3Vp.p
VcM � 1V, 1<100kHz Rs=<I>

350 430 600

VN

1

11

kQ

5

�A

30

�A

�1.0

v

55

dB

PSRR

Supply voltage rejection ratio

aVs=�0.5V

50

dB

Channel separation

Vour-1Vp.p; f=100kHz (output referenced) RL=1kQ

70

dB

Vos
Vour Ice

Output offset voltage gain select pins connected together gain select pins open
Output differential voltage swing Power supply current (total for both sides)

RL=~ RL=~
RL=2k0
RL=~

1.5

v

1.0

v

2.B

v

47

mA

AC ELECTRICAL CHARACTERISTICS
TA=+25�C Vss=�GV, VcM=O, unless otherwise specified. Recommended operating supply voltage Vs=�6.0V. Gain select pins connected together.

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

UNITS

Min Typ Max

BW

Bandwidth

Vour=1Vp.p

25

MHz

tR

Rise time

15

20

ns

tpo

Propagation delay

Vour=1Vp.p

7.5

12

ns

October 20, 1987

91

Signetics Industrial
Video amplifier

Product specification
NE5592

TEST CIRCUITS TA=25�C unless otherwise specified.

0.2�F
"ln~0.2~F 592 �..�OUT �corr

51 51

1k 1k

51

1k 1k

TYPICAL PERFORMANCE CHARACTERISTICS (Continued)

Common-Mode Rejection Ratio

'fm

as a Function of Frequency

100

~0 90 80
l!i 70 ~ 60
~ 50 I - YS�:t.6V

I - TA= 25�C

� : I- R5:0

i 20 I - V1N =2VP1>

1�tt - 10

J_ J_

8 0

1o5

106

107

108

FREQUENCY - Hz

Output Voltage Swing as a Function of Frequency

~"' 5

J. 4

";!
...g...J 3

""'

VS��6V

""" ~

ll[ "~ 2 I-
0 1

RL= 1k<l
1il'J: 215~
~

105

106

107

1oB

FREQUENCY - Hz

Differential Overdrive
Recovery Time
50 ~...-~~-.--.--.--.--.--.-~

Pulse Response as a Function of Supply Voltage
1.6
> 1.4
J. 1.2 HH-+-1--1--b""'""-1-......
"~ 1 t-+-+-+-+--Y'-t::-'"-+-+~
g 0.8 1--1-1-1-hll/C---I-
!~; 00..64 lr-::t::t:::tt~:r:::i:::1
o 0.2 t-+-+-,,+-+++-+-+-1 0 l-+-+""'l-+-++-+-+-+-1

0

40 BO 120 160 200

DIFFERENTIAL INPUT VOLTAGE-mV

Voltage Gain as a

Function of Temperature

l 1.6 1.2 ~ 0.8
~ 0.4 cs g ~

= VS ��6V -
RL=1k<l 1=1MHz _

~-0.4

~--0.8

w CC-1.2

-1.6 0 10 20 30 40 50 60 70

TEMPERATURE: �C

-15-10 -5 0 5 10 15 20 25 30 35 TIME-nS
Gain vs Frequency as a Function of Temperature
60

l 50Ha~~ 40 l-+-l-W--1-1-l+h..l"'IM+-l-+l.l-J

I!

w "

30

H--+-<.+<--+-+-++t-il'7'f'tt.lll'+-t-tt1

;!

g 20 H--+-l#-+-Hi+-

10 ~~~-+-~~~~~~~

105 106

107

1oB

FREQUENCY - Hz

October 20, 1987

92

Vs=�6V TA=25�C

Channel Separation as a Function of Frequency

.,

DI ][

l -10 l-t-1

~ -20 1-H
a: -30

iwf -40

Cll
.zzw..J

-so -eo

:i1! -70

" -BO l.;f"

RL= 1k<l TA= 25'C
i..-1""! 1-'1

106

107 108 109

FREQUENCY - Hz

Pulse Response as a Function of Temperature
1.6
1.4
> 1.2
~J.a.a1 Ft::~~~:i::;~~~=r:~~
5 0.6 f-+-+-+-....<.+-41--+-+-+~
> .... 0.4 1--1-1-r.H-+-* ~ 0.2 I--+-+-_+-....
5 0
--0.2 1--+-+--+--+--+--+--+--+-+-<
--0.4 '-'--'---'--'--'--'--'--'--'--' -15-10 --5 0 5 10 15 20 25 30 35
TIME-nS

Voltage Gain as a Function of Supply Voltage

l 2 H- ~:~i:~

~ 0

y

~ ~

-1 -2

g -~3

1--1--~Lt'.-.rL-+--+--+--+--+--+--t
t-t_..l'lol'-+-t--+--+-+-1--1-t--i

--5 ~1'-1--+-+-+-~f-+-t--+-l

-6 1--1--+-+-+-+-+-+-+-~

3

4

5

6

SUPPLY VOLTAGE-V

Signetics Industrial
Video amplifier

Product specification
NE5592

TYPICAL PERFORMANCE CHARACTERISTICS (Continued)

Gain vs Frequency as a Function of Supply Voltage
60
l:~mt~
~
w ~ 30 ~ l-+-rT"t1""""-t-n-Hf--t-t-IHW't-t+H
~ 00 .........................,H-1<>--+-+<......-+--H+I
IFREQUENCY-Hz

Phase vs Frequency as a Function of Supply Voltage

m 0.
~ 30 60
I
t: 90 il5 1 :JI 150
~ 180
10
240
105

TA� 25'C RLs1kn
...Ll.11..1.J.
1\ -HH--H LL Vs ��BV

JLJ.cVs=�6V I Ill I 11 Vs=�3V

t! llllll

106 107

1a8

109

IFREQUENCY-Hz

35
c
~
aaw:: 34
""~
::: 33
iil

Supply Current as a Function of Temperature
I~ Vs=�SV
T"oo.
1'
~ ~

32 0

10 00 30 40 50 6070
TEMPERATURE- �c

Supply Current as a Function of Supply Voltage
50

II I
t - TA �25�C

k"

"""' I--"' """' .IL
~

10

0

3

4

5 6

7

SUPPLYVOLTAGE-�V

Voltage Gain as a Function of RAoJ

~ ~
~

=: TA�25'C -
RL=�6V

10-1 1

~ ...).
~
10 102 104 103 105 106 RADJ-OHMS

Output Voltage Swing and Sink Current as a Function of Supply Voltage
H6 , - - , - - - . . - - , - - - r - - - - ,
0..
5 i---t----t----t------,:P!ll"'"--1

!E
U)

!a::!

w :::>

"~~"

0 Vi

;:'.: !:; 2 lo!ll''--t----t----t----t-------1

� ~

e:
5

1

r-----....--....--....--....---,

o~-~-~-~-~~

3

4

5

6

7

SUPPLY VOLTAGE - �V

Output Voltage Swing as a Function of Load Resistance
I- Vs=ot!N
TA� 2'C

~

11

.

0

1a5

106

107

1a8

LOAD RESISTANCE - OHMS

Input Resistance as a Function of Temperature
25
G1N1I Vs=�6V
L
v .Y
~
I'
10 0 10 20 30 40 50 60 70 TEMPERATURE-'C

Input Noise Voltage as a Function of Frequency

r - TA. 25"C Vs=�6V r-
I=

I I I
Rs= 1oon

t-

ll
..l.

102 104 106 1a8 1010 FREQUENCY - Hz

October 20, 1987

93

Slgnetlcs RF Communications
Video amplifier

Product specification
NE/SA/SE592

DESCRIPTION
The NE/SA/SE592 is a monolithic, two-stage, differential output, wideband video amplifier. It offers fixed gains of 100 and 400 without external components and adjustable gains from 400 to Owith one external resistor. The input stage has been designed so that with the addition of a few external reactive elements between the gain select terminals, the circuit can function as a high-pass, low-pass, or band-pass filter. This feature makes the circuit ideal for use as a video or pulse amplifier in communications, magnetic memories, display, video recorder systems, and floppy disk head amplifiers. Now
available in an 8-pin version with fixed gain of
400 without external components and adjustable gain from 400 to 0 with one external resistor.

FEATURES
� 120MHz unity gain bandwidth � Adjustable gains from 0 to 400 � Adjustable pass band � No frequency compensation required � Wave shaping with minimal external
components � MIL-STD processing available
APPLICATIONS
� Floppy disk head amplifier � Video amplifier � Pulse amplifier in communications � Magnetic memory � Video recorder systems

BLOCK DIAGRAM

PIN CONFIGURATIONS

INPUT2
NC G29GAIN
SELECT G19GAIN
SELECT y.
NC
OUTPUT2
TOP VIEW
HPACKAGE" ~A GAIN SELECT

INPUT 1
NC ~AGAIN SELECT G1AGAIN SELECT V+
NC
OUTPUT1

INPUT!

INPUT2

V+

~9GAIN SELECT

OUTPUT1

G19GAIN

SELECT

y.

NOTES:

Pin 5 connecxted to case

�Metal cans (H} not rocommrnded for new designs.

0, F, N Packagae

:5 G~I~N~P:Uc:TV2~

~

INPUT 1
:!teC::~N

OUTPUT 2

TOP VIEW

OUTPUT 1

INPUT1 G1A G2A
November 3, 1987

OUTPUT2

R14 -V

94

853-0911 91255

Signetics RF Communications
Video amplifier

ORDERING INFORMATION

DESCRIPTION 14-Pin Plastic DIP 14-Pin Cerdip

TEMPERATURE RANGE
o to +70�C o to +70�C

ORDER CODE NE592N14 NE592F14

14-Pin Cerdip 14-PinSO 8-Pin Plastic DIP

-55�C to +125�C
oto +70�C o to +70�C

SE592F14 NE592D14 NE592N8

8-Pin Cerdip

-55�C to +125�C

SE592F8

8-Pin Plastic DIP 8-PinSO

-40�C to +85�C
o to +70�C

SA592N8 NE592D8

8-PinSO 10-Lead Metal Can

-40�C to +85�C
oto +70�C

SA592D8 NE592H

10-Lead Metal Can

-55�C to +125�C

SE592H

NOTES: NS, N14, DB and D14 package parts also available in "High" gain version by adding "H" before
package designation, i.e., NE592HDB

ABSOLUTE MAXIMUM RATINGS
TA=+25�C, unless otherwise specified.

SYMBOL

PARAMETER

Vee

Supply voltage

V1N

Differential input voltage

VeM

Common-mode input voltage

lour

Output current

TA

Operating ambient temperature range

SE592

NE592

Tsrn

Storage temperature range

Po MAX

Maximum power dissipation,

TA=2s0 c (still air) 1

F-14 package

F-8 package

D-14 package

D-8 package

H package

N-14 package

N-8 package
NOTES: 1. Derate above 25�C at the following rates:
F-14 package at9.3mW/"C F-8 package at 6.3mW/"C D-14 package at 7.8mW/�C D-8 package at 6.3mW/�C H package at 6. 7mW/�C N-14 package at 11.5mW/�C N-8 package at 9.3mW/�C

RATING �8 �5 �6 10
-40 to +85 0 to +70 -65 to +150
1.17 0.79 0.98 0.79 0.83 1.44 1.17

UNIT
v v v
mA
oc oc oc
w w w w w w w

November 3, 1987

95

Product specification
NE/SA/SE592

Signetics RF Communications
Video amplifier

Product specification
NE/SA/SE592

DC ELECTRICAL CHARACTERISTICS
TA=+25�C Vss=+6V, VcM=O, unless otherwise specified. Recommended operating supply voltages Vs=+6.0V. All specifications apply to both standard and high gain parts unless noted differently.

SYMBOL

PARAMETER

TEST CONDITIONS

NE/SA592

SE592

UNIT

Min Typ Max Min Typ Max

AvoL

Differential voltage gain,

standard part

Gain 11

RL=2kn, Vour=3Vp.p

250 400 600 300 400 500

VN

Gain 22�4

80 100 120 90 100 110

VN

High gain part

400 500 600

VN

R1N

Input resistance

Gain 11

4.0

4.0

kn

Gain 22�4

10 30

20 30

kn

C1N

Input capacitance2

Gain 24

2.0

2.0

pF

las

Input offset current

0.4 5.0

0.4 3.0

�A

la1As

Input bias current

9.0 30

9.0 20

�A

VNQISE V1N

Input noise voltage Input voltage range

BW 1kHz to 10MHz

12 �1.0

12 �1.0

�VRMS
v

CMRR

Common-mode rejection ratio

Gain 24

VcM�1V, f<100kHz

60 86

60 86

dB

Gain 24

VcM�1V, f=5MHz

60

60

dB

PSRR

Supply voltage rejection ratio

Gain 24

tNs=�0.5V

50 70

50 70

dB

Vos
VcM Vour

Output offset voltage Gain1 Gain 24 Gain 33
Output common-mode voltage Output voltage swing

RL=oo RL=oo RL=oo
~=oo
RL=2k!l

1.5

1.5

v

1.5

1.0

v

0.35 0.75

0.35 0.75

v

2.4 2.9 3.4 2.4 2.9 3.4

v

3.0 4.0

3.0 4.0

v

differential

Rour

Output resistance

20

20

a

Ice

Power supply current

NOTES:
1. Gain select Pins G1A and G10 connected together. 2. Gain select Pins G2Aand G20 connected together. 3. All gain select pins open.
4. Applies to 10- and 14-pin versions only.

RL:oo

18 24

18 24

mA

November3, 1987

96

Signetics RF Communications
Video amplifier

Product specification
N E/SA/SE592

DC ELECTRICAL CHARACTERISTICS
DC Electrical CharacteristicsVss=i6V, VcM=O, 0�C sTAs70�C for NE592; -40�C STA,; 85�C for SA592, -55�C SfA,; 125�C for SE592, unless otherwise specified. Recommended operating supply voltages Vs=+6.0V. All specifications apply to both standard and high gain parts unless noted differently.

SYMBOL

PARAMETER

TEST CONDITIONS

NE/SA592

SE592

UNIT

Min Typ Max Min Typ Max

AvoL

Differential voltage gain, standard part

Gain 11 Gain 22�4 High gain part

RL=2k0, Vour=3Vp.p

250

600 200

80

120 80

400 500 600

600

VIV

120

VIV

VIV

R1N

Input resistance

Gain 22. 4

8.0

8.0

k!l

los le1AS V1N CMRR

Input offset current Input bias current Input voltage range Common-mode rejection ratio
Gain~

VcM�1V, f<100kHz

�1.0 50

6.0 40
�1.0
50

5.0

�A

40

�A

v

dB

PSRR

Supply voltage rejection ratio

Gain~

/!.Vs=�0.5V

50

50

dB

Output offset voltage

Gain 1

Vos

Gain~

Gain 33

Vour

Output voltage swing differential

Ice

Power supply current

NOTES:
1. Gain select Pins G1A and G19 connected together. 2. Gain select Pins G2A and G29 connected together. 3. All gain select pins open.
4. Applies to 10- and 14-pin versions only.

RL:oo
RL=2k0 RL=oo

1.5

1.5

v

1.5

1.2

1.0

1.0

2.8

2.5

v

27

27

mA

AC ELECTRICAL CHARACTERISTICS
TA=+25�C Vss=+6V, VcM=O, unless otherwise specified. Recommended operating supply voltages Vs=�6.0V. All specifications apply to both standard and high gain parts unless noted differendy.

SYMBOL

PARAMETER

TEST CONDITIONS

NE/SA592

SE592

UNIT

Min Typ Max Min Typ Max

Bandwidth

BW

Gain 11

Gain 22.4

40

40

MHz

90

90

MHz

Rise time

IA

Gain 11

Gain 22�4

Vour=1Vp.p

10.5 12 4.5

10.5 10

ns

4.5

ns

Propagation delay

tpo

Gain 11

Gain 22� 4

NOTES:
1. Gain select Pins G 1A and G10 connected together. 2. Gain select Pins G2A and G29 connected together. 3. All gain select pins open. 4. Applies to 10- and 14-pin versions only.

Vour=1Vp.p

7.5 10 6.0

7.5 10

ns

6.0

ns

November 3, 1987

97

Signetics RF Communications
Video amplifier

Product specification
NE/SA/SE592

TYPICAL PERFORMANCE CHARACTERISTICS

Common-Mode Rejection Ratio

as a Function of Frequency

'I: 100

I
0 90
!a;;:: 80
i!i 70 ~ 60
1:iai:l 50

GAIN2 Vs=�GV H
TA= 25�C H
1-o..
"" '"'bJ
b.:

0 10 () 0
10k 100k 1M

10M 100M

FREQUENCY - Hz

Output Voltage Swing aa a Function of Frequency

7.0
I 6.0 I
~ 5.0
~
""' 4.0
~ 3.0
,_g
:::> 2.0
i=
5 1.0

~:r�GJ' TA=25�C j--, RL=1kn
~
~
\

0

1

5 10

50 100 5001000

FREQUENCY - MHz

Pulse Response

1.8

1.4

Vs��&V TA=25'C -

> 1.2

RL:1k -

I
"",g~_'
:::>
i=
:::> 0

1.0

0.8

[/

II 0.8 t-i GAIN2 JL J_ ] 0.4

GAIN 1 ' __,t -H

0.2

~

-0.2
.0.4 -15 -10 -5 0 5 10 15 20 25 30 35 TIME-no

Differential Overdrive Recovery llme

28

~;;5.~ -I-

.L ~
v l2l
~P'
IA
ILl

SUPPLYVOLTAGE-�V

Pulse Response as a Function of Supply Voltage

1.6 .-...-...-..-..........................--..............

GAIN2
1�4 I- TA=25'C

~ I ..J.

> 1.2 I- RL=1kn -t-+- Vs=�&V -t--1

V I 1.0

~ ;!

0.8 1-t-t-+--ff-b...V..s_=-�6+V-+-t

~ 0.6 l-+-+-+--fll/J-11- Vs= �3V -t-

51~-

0.4 1-+-+-+-fl-#.L-+--+--+--+-+-t

0.2

l,h

l--l--J..-l~--l--1---1----1----1--l

-0.2 1-+-+-+--+--+--+--+--+-+-t
-0.4 ._....__,___,___,__,__.__.__._............
-15 -10 -5 0 5 10 15 20 25 30 35

TIME-no

Pulse Response as a

Function. of Temperature

1.8 1GAl~2 1
1.4 1- Vs=,iev

>
I

1.2 1.0

I--lLi 1~

""' n. ;! r 11 +- >,~_

0.8 0.8

I- Tamb=O'C

'If_-...TA= 25'C

:::> 0.4

i=
:::>

0.2

TA� 70'C

1 0

-0.2
-0.4 -15 -10 -5 0 5 10 15 llO 25 30 35
TIME-no

Voltage Gain as a

Function of Temperature

~s=:!.v 1.10 ,.-....,....--,,...-....,....--,.--...,....--,.---,
1.00 l--+---11---+---ll--

z
1~�
!g:l

1.06 1.04 1.02
1.00

t.~ ~ ...........:..:l:-'-~-t+-"-'-.l.-t-----+'l-----+1--1-1-1----++-------lt
1~ --i--"'l...�.".'ld:~-t--+-GA-l~N._2--1

~"' ~

0.98 0.96
o.94

ll--+--+--+--11--:-:fs"~~_i+-r---,i...:.i.....-.,"r'-"-oll !---+---+- GAIN~-

0.92 l--+--l---+---11--~~f.--'.....l..-. --l

0.90 ~......-~......--'~-'---.'..~........

0 10 20 30 40 50 60 70

TEMPERATURE- �C

Gain vs. Frequency as a Function of Temperature
GAIN2 >-+-+-++--+--+-+< Vs= "8V
RL= 1kn

5 10

50 100 5001000

FREQUENCY - MHz

Voltage Gain aa a Function of Supply Voltage 1.4

1.3 1-1--1-1-+-+-TTa;: ;;25::;

z 1.2

-

1� 1.1

V'"

~
!g:::l

1.0
o.9

1

GAIN2
A ......!-""~L!l

~

S~ 0.8 0.7

y
...ill GAIN1

~:::~

0.4 L......J'--L-L-L-.1-.._.._..__,___, 7
SUPPLY VOLTAGE- 1'N

November 3, 1987

98

Signetics RF Communications
Video amplifier

Product specification
NE/SA/SE592

TYPICAL PERFORMANCE CHARACTERISTICS (Continued)

m... 60

zI 50
~

""~' 40
~ 30 >

"'Q 20

Q

i!i
~

10 H

ii

Ill

-10 1

Gain vs. Frequency as a Function of Supply Voltage
jTGAT.i TIT
TA= 25�C t -
RL= 1k.O:
ll
~ 1v~!_,.av

lVs:,.SV

111
1Vi5CL"3J

j--1

H

5 10

50 100 500 1000

FREQUENCY - MHz

Voltage Gain Adjust Circuit

1000
~
:zcI 100
g"~"" ' 10
:;!
ffi
a: .1
~
Q .01

Voltage Gain as a Function of RADJ (Figure 3)

:s ~

v~:~kHz ~ ~ TA"' 25�C
RGURE3

~

~

~

10 100 1K 10K 100K 1M

Supply Current as a Function of Temperature
21

20

El

II 19

1a
B 11

I~

~

~ 18

15

14

-60 -20

20

60 100 140

TEMPERATURE - 'C

Supply Current as a

Function of Supply Voltage

70
!, 60

~s-:'.",...~

w t- TA=25'C

:I!

GAIN2

..,�,r7

~ 50 >--+-+-+--+--+--+--+!L1-+.P..'......._,

� 40

v

y ~~

30

t--+-+--+--+-t""""'-+-+--+--t
I

~ 20 t--+-+--+--i.L.C.j&...1---1--+-+--+--t

~~ 10 r-+-17~

0 0 20 40 60 80 100 120 140 160 180 200

DIFFERENTIAL INPUT VOLTAGE- mV

Output Voltage and Current

Swing as a Function of

Supply Voltage

l5 El

~ ~

I 1-a:i!i

if~~/iJi<>g~;

2~'C 7.0 ,......,.......,..-.,......,....,.....,.--.-,......,..--,

I TAI=

I

6.0 t--t--+-+--+-+--T-t-i-~ r-l

5.0 t--t--+-V+-O-+L-+T-+A-tG--'EF"~"4

~ 4.0 1--1---1---+--+--+--"""'.l""'-1---l--l

3.0

~

CURRENT-+-

�? !:;
$ !:;

2.o P~-11.--'.:7'1~Hl-Hl-l-l-l-H

� 0 1.0 l--t---l--+--+-+-+-t-1---1--l

3.0 4.0 5.0 6.0 7.0 8.0 SUPPLY VOLTAGE-�V

Output Voltage Swing

as a Function of

Load Resistance

V~=~J 7.0 r-T""T-rr--.-...............,......,...,.,.,......,

~

I 6.0 t--+-l-l+---1-1-+++ TA =25'C f--

1
ii 5.0 t--t-t;+--+-+-+++-+-+-lt++---1 ~
~ 4.0 t-H-tt--t-++tty~-+-+++-1

g ~ 3.0

~ 2.0 t--+-+-1+---1-v-++--+-+-+1+--l

5 1.0 i--t-t-+1H---<...1..7.....-+<>+--+--+->++-t

10

50 100

5001K

SK 10K

LOAD RESISTANCE- O

Input Resistance

as a Function of

Temperature

70 .--..--.,..-..,.....,.....,...--,--,-..--.,..-,

GAIN2

li! 60

Vs:�&V t-

~1 50

y ILf

~ 40 l--+--1--!--l--l--,I~-+--!-~
~~: J-1..RIiY :!i

10 l'L:.."'-t-t-t--+-+--+-+-+---1--1

0 .__.__,__.__,__,__,___,____.__,_....

-60 -20 0 20

60 100 140

TEMPERATURE - �c

100
l :
",], 70
g~ 60 50
~ :
!:; 20
D. ~ 10
0

Input Noise Voltage as a Function of
Source Resistance
~2 TIT
Vs:,.SV r TA= 2s�c rBW: 10MHz r

v

10

100

1K

10K

SOURCE RESISTANCE - Q

November3, 1987

99

Signetics RF Communications
Video amplifier

Product specification
NE/SA/SE592

Phase Shift as a

Function of Frequency

0 N

8l -5
aw :

~
~

" w
0

-10

I

I;:

"':f -15
w
"i"t' -20

hAl~2 I t-
Vs =,o6V
TA=25�C t~
~rs: N '[....

-25 012345678910
FREQUENCY -MHz

-50
"'aww: -100
iii
0 -150
I
I;: :f -200
i"'w -250 -300
-350

Phase Shift as a Function of Frequency

10

100

FREQUENCY - MHz

1000

Voltage Gain as a

Voltage Gain as a

Function of Frequency

Function of Frequency

60

50
.".", 40
:z;;I: 30
"w 20 ";!
5> 10

GAIN1 GAIN2

40

Vs=�6V --1

.".",

30 20

:z;;I:

10

" w ";! -10

5 -20
>

-30

TA=25'C
GAIN3 --1

~

v L
~

\-

-40 -50

~

10

100

1000

.01 .1

10 100 1000

FREQUENCY - MHz

FREQUENCY - MHz

TEST CIRCUITS TA= 2s0 c, unless otherwise specified.

510

0.2~F

�1n~~ 592. 0.2~F
.... ""'

5m _ _ �m

�kk

--

-=-=-=-=

November 3, 1987

100

Signetics RF Communications
Video amplifier
TYPICAL APPLICATIONS

Product specification
NE/SA/SE592

NOTE:

Vo(>)

l.4-1o4

~ �Z(S)+2re

- 1.4 -1o4 Z(S) + 32

+6

Baelc Configuration +5
Q

+6 0.2�F
~
l 2~0

AMPLITUDE: 1-10 mV p-p FREQUENCY: 1-4 MHz
�6

READ HEAD

DIFFERENTIATOR/AMPUAER

ZERO CROSSING DETECTOR

Diec/Tape Phase-Modulated Readback Systems
FILTER NETWORKS

ZNETWORK

R

L

~

ALTER TYPE
LOW PASS

Vo (�) mANSFER V1 (o) FUNCTION
[s+~/L] 1.4 )( 1o4
--L-

NOTE: For frequency F, � 1/211: (32) C
4;. v0 - 1.4x1o4c
Dffferen11atlon wllh High Common-Mode Noise Rejection

R

c

<>--'vVv---j 1-----o

R

L

c

~1--o

HIGH PASS

1.4 )( 1o4 --R-

6 [s+1 /RC]

BAND PASS

1.4 )( 1o4 --L-

[ s2+ R;s+ 1/LC]

L
~

BAND REJECT

1.4 )( 1o4 --R-

[ s2+1/LC ] s2 + 1/LC + s/RC

NOTES:
In the networks above, the A value used Is assumed to include 2r8 , or approximately 32!2.
S�Jm
Ol�2ltf

November3, 1987

101

Slgnetlcs RF Communications
6W audio amplifier with preamplifier

Preliminary specification
TDA1010A

The TOA 1010A isa monolithic integrated class-B audio amplifier circuit in a 9-lead single in-line (SIL)
plastic package. The device is primarily developed as a 6 W car radio amplifier for use with 4 n and 2 n load impedances. The wide supply voltage range and the flexibility of the IC make it an attractive
proposition for record players and tape recorders with output powers up to 10 W. Special features are: �single in-line (SIL) construction for easy mounting �separated preamplifier and power amplifier �high output power � low-cost external components �good ripple rejection �thermal protection

OUICK REFERENCE DATA

Supply voltage range
Repetitive peak output current
Output power at pin 2; dtot = 10% Vp=14,4V;RL=2S?. Vp=14,4V;RL=4S?. Vp=14,4V;RL=8S?.
Vp = 14,4 V; RL = 2 S?.; with additional
bootstrap resistor of 220 n between pins 3 and 4
Total harmonic distortion at P0 = 1 W; RL = 4 S?. Input impedance
preamplifier (pin 8) power amplifier (pin 6)
Total quiescent current at Vp = 14,4 V
Sensitivity for P0 = 5,8 W; RL = 4 S?. Operating ambient temperature
Storage temperature

Vp lo RM
Po Po Po
Po dtot
I Zi I
I 2i I
Itot V�I Tamb Tstg

6 to 24 V

max.

3 A

typ.

6,4 w

typ.

6,2 w

typ.

3,4 w

typ.

9 w

typ.

0,2 %

typ.

30 kS?.

typ.

20 kS?.

typ.

31 mA

typ.

10 mV

-25 to+ 150 oc

-55 to+ 150 oc

November 1982

102

z
~
3
CT
!!l
~
R14 5o--~~~~~~~~~~~~~~~~-{==::::J------i TR9

TR5

TR10

R15

R18

R17

8

R10

TR8

TR11

R21 R22

R28

I

(/)

<O'

O')

:::J

~

CD
5�

aclel:lr.

J"J'
"Tl
0 0
3 3

lll
3
I "O

c:
o:::J� !a!?�.
:::J

::::;:;
4 I (.5.,"

"'

TR20

TR23

:E

R25

;:::+:
~

TR18

TR22

05 R34

R30I

n
R29

I 11

".O.,

CD
lll
3

I

"O ::::;:;

(.5.,"

I

R1

R11

03

R19

gn--.._~.._~+----<>--~~_._~1---+-~.._~__...._~~~_._~~~._~,__~_.~~~-+-~~;-~r-----r

8

6

7Z 75194.1

Fig. 1 Circuit dia!Jram.

"O

-1 ~

0 _)>.

~3' 5�
~

0....... ~"'

0 )>

�:
�'
g-

:::J

Signetics RF Communications
6W audio amplifier with preamplifier

Preliminary specification
TDA1010A

RATINGS

Limiting values in accordance with the Absolute Maximum System (IEC 134)

Supply voltage

Vp

Peak output current

loM

Repetitive peak output current

lo RM

max. max. max.

24 v
5 A 3 A

Total power dissipation Storage temperature Operating ambient temperature

see derating curve Fig. 2

Tstg lamb

-55 to+ 150 oc -25 to+ 150 oc

A.C. short-circuit duration of load
during sine-wave drive;
without heatsink at Vp = 14,4 V

max. 100 hours

10 Ptat
(W)
8
6
4
2
0 -25 0

7Z76419 3

~ !\ ~ ~

~

~

50

100

150

Fig. 2 Power derating curve.

HEATSINK DESIGN

Assume V p = 14,4 V; RL = 2 n; Tamb = 60 oc maximum; thermal shut-down starts at Ti = 150 �c. The maximum sine-wave dissipation in a 2 n load is about 5,2 W. The maximum dissipation for music

drive will be about 75% of the worst-case sine-wave dissipation, so this will be 3,9 W. Consequently, the

total resistance from junction to ambient

Rth

j-a

= Rth

j-tab

+

Rth tab-h

+

Rth

h-a

=

150- 60 3,9

= 23

K/W.

Since Rth j-tab = 10 K/W and Rth tab-h = 1 K/W,

Rth h-a =23- (10+ 1) = 12 K/W.

November 1982

104

Signetics RF Communications
6W audio amplifier with preamplifier

Preliminary specification
TDA101 OA

D.C. CHARACTERISTICS Supply voltage range Repetitive peak output current Total quiescent current at Vp = 14,4 V

Vp lo RM Itot

6 to 24 V

<

3 A

typ. 31 mA

A.C. CHARACTERISTICS Tamb = 25 �C; Vp = 14,4 V; RL = 4 n; f = 1 kHz unless otherwise specified; see also Fig. 3.

A.F. output power (see Fig. 4) at dtot = 10%; measured at pin 2; with bootstrap Vp = 14,4 V; RL = 2 n (note 1)
Vp = 14,4 V; RL = 4 n (note 1 and 2)
Vp= 14,4 V; RL = 8 n (note 1) Vp = 14,4 V; RL = 4 n; without bootstrap
Vp = 14,4 V; RL = 2 n; with additional bootstrap
resistor of 220 n between pins 3 and 4 Voltage gain
preamplifier (note 3)
power amplifier
total amplifier
Total harmonic distortion at P0 = 1 W Efficiency at P0 = 6 W Frequency response (-3 dB) Input impedance
preamplifier (note 4)
power amplifier (note 5)
Output impedance of preamplifier; pin 7 (note 5)

Gvtot
dtot T/ B

typ. 6,4 w

{~p.

5,9 w 6,2 w

typ. 3,4 w

typ. 5,7 w

typ.

9W

typ. 24 dB 21 to 27 dB
typ. 30 dB 27 to 33 dB
typ. 54 dB 5i to 57 dB
typ. 0,2 %
typ. 75 %
80 Hz to 15 kHz

typ. 30 kn 20 to 40 kn
tvP� 20 kn
14 to 26 kn
typ. 20 kn 14 to 26 kn

Output voltage preamplifier (r.m.s. value)
dtot < 1% (pin 7) (note 3)
Noise output voltage (r.m.s. value; note 6) Rs= on
Rs= 8,2 kn
Ripple rejection at f = 1 kHz to 10 kHz (note 7) at f = 100 Hz; C2 = 1 �F
Sensitivity for P0 = 5,8 W Bootstrap current at onset of clipping; pin 4 (r.m.s. value)

Yo(rms)
Yn(rms)
Yn(rms) RR RR
Vj
l4(rms)

>

0,7 v

typ. 0,3 mV

typ. 0,7 mV

<

1,4 mV

>

42 dB

>

37 dB

typ. 10 mV

typ. 30 mA

November 1982

105

Signetics RF Communications
6W audio amplifier with preamplifier

Preliminary specification
TDA1010A

Notes
1. Measured with an ideal coupling capacitor to the speaker load. 2. Up to P0 ,,;;.:; 3 W : dtot ,,;;.:; 1%. 3. Measured with a load impedance of 20 kn. 4. Independent of load impedance of preamplifier.
(j I) 5. Output impedance of preamplifier Z0 is correlated (within 10%) with the input impedance (I ZiJ ) of the power amplifier.
6. Unweighted r.m.s. noise voltage measured at a bandwidth of 60 Hz to 15 kHz (12 dB/octave). 7. Ripple rejection measured with a source impedance between 0 and 2 kn (maximum ripple amplitude:
2 V). 8. The tab must be electrically floating or connected to the substrate (pin 9).

!C2
100 nF

R1 330krl

5

3

C1
rl + 8
1'�F

TDA1010A

vi

9

7 6

j

100 nF

C4

1 nF

IC5
100nF

100�F

4

C7

+

2

C6 100nF

R2
4,7 n

+
+ 1000�F
cs
Vp RL 4n

7Z76418.2

Fig. 3 Test circuit.

November 1982

106

Signetics RF Communications
6W audio amplifier with preamplifier

Preliminary specification
TDA101 OA

Vp(V)

20

Fig. 4 Output power of the circuit of Fig. 3 as a function of the supply voltage with the load impedance as a parameter; typical values. Solid lines indicate the power across the load, dashed lines that available
at pin 2 of the TOA1010. R L = 2 n (1 l has been measured with an additionc�I 220 n bootstrap resistor
between pins 3 and 4. Measurements were made at f = 1 kHz, dtot = 10%, Tamb = 25 �c.
Fig. 5 See next page. Total harmonic distortion in the circuit of Fig. 3 as a function of the output power with the load impedance as a parameter; typical values. Solid lines indicate the power across the load, dashed lines
that available at pin 2 of the TDA 1010. RL = 2 n (1 l has been measured with an additional 220 n bootstrap resistor between pins 3 and 4. Measurements were made at f = 1 kHz, Vp = 14,4 V.

November 1982

107

Signetics RF Communications
6W audio amplifier with preamplifier

Preliminary specification
TDA1010A

lO.--~~~-,-~~..--~.--.....,--r-r.-..,..-,~~~~.....,-~~TTT!---i~......-"TM"l'7'Z"7,Jr-i,o

dtot 1--~~~-t-~~+-~t---+---+---+--t-+-1~~~~-+-~~ttl+--+---+~r1 -Mi+.-1 +-i

(%) I I 1--~~~-t-~~+-~t---+---+---+--+-+-1~~~~-+-~~f+-'-----i~-+-t-tr-H-tt-+I -i

I

JI I'

I
7,5t--~~~;--~-r-~-t--+--t--+--t-+-t-~~~__,~~-il""J"!~t---t-tH--rt-"t-t4

ll_

I

B li. 2�5 1------+---+--+--+--t--t-+-+-t----r---tt--llH'1-Ht'TtiL-t-t--+I -r--t-t
_LIJVI

Fig. 5 For caption see preceding page.

Po
(dB)

0

RL= 2n

,/'
~

4Q rLf_

-2,5

Bn

v

1
LI_

P0 (W)

10
7Z77912

.,........ f'b ,...
_['-..
~

-5

10

f (Hz)

Fig. 6 Frequency characteristics of the circuit of Fig. 3 for three values of load impedance; typical values. P0 relative to 0 dB= 1 W; Vp = 14,4 V.

November 1982

108

Signetics RF Communications
6W audio amplifier with preamplifier

Preliminary specification
TDA1010A

T/
1-+-+-+--+-+-+-+-+--t-i-+-+--+--+-t-+-+-+-+-+-+--+-+-+-+-+-+-t-+-+-1--+--t-11-iRL=2Dt-t-t--t-t(%)
P(Wto)ttj::=ttj::tj=t!=ttj::tj=t!=..l.-=t;:t:~~$:~4=+::4:++:t:+:+:t4:f:~~~+:4:::t~ ;�;:~ 100

2

i--

n o l'--- 4 +-+-+-+-+-+-+-+-+-+-+-t-1 4

l--+-l-+-+-+-+-+-+-+-1-+--+-f-+-+-+-+-+-+--+-+-+-+-+-+-t-+-+-1-+-+-t-++-t-+-+-+-+-+-t-t-t--t-120

o ....._.__.._._.__._...._._.__.._._.__._...._._.__.._........_._..._._.__.._~_._. . . . . . _.__.._~_._~~~~_._ . . . .~o

0

2

4

6

P0 (W)

8

Fig. 7 Total power dissipation (solid lines) and the efficiency (dashed lines) of the circuit of Fig. 3 as
a function of the output power with the load impedance as a parameter (for RL =2 nan external
bootstrap resistor of 220 n has been used); typical values. Vp = 14,4 V; f = 1 kHz.

November 1982

109

Signetics RF Communications
6W audio amplifier with preamplifier

Preliminary specification
TDA1010A

Rthh-a l--+-l--l-l-+-l--l--1-+-l--l--l-+-l--l-1-+-+-+-1-+-+-+-1-+--+-+-1-+-+-+-1-t-+--t-1-t-+--t-1-t-r-t-i--t
(�C/W)1-1---+--1--+----1--<,_+--l-j--+--1-j-t-+-1-t-+-+-+-+-t-+-+-+-+-+-+-+-+-+-+-+-+-t-it-t--t-11-t--t-1-r--i-t-i
201-++-lf-+-+4~,..+--+-+-+-f-+--+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+i-++-t--t-t-t"-t-l-++-t--t--r-r-1
I"

10

H1--+l--+--l+--H1--+l---+l--+H-+--1+---+1-1--H+--+l---+l--+H-+--t+--+1-!l-"+"-:tl-Ht-"+'l--+--o-Fl.l:i:":rH"-t;.--.t-..-+iN.--~t~Ni1--t--.-.+A-+--+1r.rc-=;lF:-,;.,;,:H..-tt--+--t4--H�r--t-~-tt---ttP-tt2owt~r

t +

-

5W t-H

0 L-.J.-L-..L..-J....J-...1-1......4.-L-..L..-l....J-...1-l..-J.-'--'--'--'--'-J........L-L-...................._._........_._....................~........~....................~~~

0

25

50

75

100

heatsink area (cm 2 )

Fig. 8 Thermal resistance from heatsink to ambient of a 1,5 mm thick bri~ht aluminium heatsink as a function of the single-sided area of the heatsink with the total power dissipation as a parameter.

November 1982

110

z
~
~

~

APPLICATION INFORMATION

C10 27 nF
vi

c2I
100nF

R1 330kn

5

3

TDA1010A

+

9
~

7

6

C4 1 nF

~

.. C'>
~

"g<I>�

C5I 100 nF"T'

!cg
~680�F

lcl>
e0r.
ll>
3 "2.. a:::;:;�;

,J,J
0 0
3 3 c
.."ac;�
6"
"

.....

+

;::E:;:

C7 4 100 �F
:;{JI T

2

I

C6 I

I
I I+ Cml:Soo�F

I

Vp

::::T
".O....
CD ll>
3
"O
I a:::;:;�; .....

100nF

) ~RL

4,7n

7Z77941.1

Fig. 9 Complete mono audio amplifier of a car radio.

"ti

-t
0
.)..>..

!3i�
j"

1 0.....
~ g2�

"

Signetics RF Communications
6W audio amplifier with preamplifier

Preliminary specification
TDA1010A

7Z77931
Fig. 10 Track side of printed-circuit board used for the circuit of Fig. 9; p.c. board dimensions 92 mm x 52 mm.

Fig. 11 Component side of printed-circuit board showing component layout used for the circuit of Fig. 9.

November 1982

112

Signetics RF Communications
6W audio amplifier with preamplifier

Preliminary specification
TDA101 OA

C9 27 nF
left channel input
R6 100 kn

c2!

220nF

Rl 150kS1

to a

5

3

TDA1010A

9

7 6

C4 1 nF

~

cs!

...I...

220 nF

+9

+

C7 4 100�F

+

2

+

C6 lOOnF

RL R2 4.7n

balance tone I I I I I
C109 27 nF
right channel input

volume I

I

I

I I

a

I

I

I

I

I

I

I

5 TDA1010A

Cl05I 220 nF

3

C107

4 100�F

+

2

9

7 6

C104 1 nF
,.
Fig. 12 Complete stereo car radio amplifier.

C106 lOOnF
R102 4,7n

+ +
RL
7Z77942.1

November 1982

113

Signetics RF Communications
6W audio amplifier with preamplifier

Preliminary specification
TDA1010A

right channel output

left channel

Ii'

output

7 Z7 7934.1

Fig. 13 Track side of printed-circuit board used for the circuit of Fig. 12; p.c. board dimensions 83 mm x 65 mm.

left channel L input
\\ /j

\\ u

Fig. 14 Component side of printed-circuit board showing component layout used for the circuit of Fig. 12. Balance control is not on the p.c. board.

November 1982

114

Signetics RF Communications
6W audio amplifier with preamplifier
100 channel separation
(dB) 75
typ 50

Preliminary specification
TDA1010A
7Z77922

25

0

10

f (Hz)

Fig. 15 Channel separation of the circuit of Fig. 12 as a function of the frequency.

November 1982

)
"'(220 V)
j

01 BY226 unloaded: + 21 V
....--+-....- + - - - - - - - - - - - - + A loaded: + 17 V
R13
7Z7793 7

Fig. 16 Power supply of circuit of Fiq. 17.
115

z

0 <
CD

3

CT

CD

~

;;:;

""''

B~ T

I

right channel input

C1
II

T I n?\C550B

R4

100

2

----i �--.

kS2

I. R51
2,2 kl1 :

R11
C6 2,2 nF

100 kl1
RS 470 kl1

C9

j-l

100 nF

1100nF

I
I

I Ilff, I I v I *~~7 -

i
I

i�-C-~16:_:Lr

"'

I

I

B

I I 11bass
I I I
I

H~"' �-h ~~~~ Ol

left_ channe

nF

BC550B

C103

R

input

,. . . 1 ".,

rClU8 11

104

100 kll

100 nF

R105 2,2 kS2

I : treble I I I
C106 2,2 nF
rib

1 ' I 1balance
I I I I I I I I
I:~

' I 11volume
I I
I I I I I I I I
I-� --

I 4:81 C108I~F I

j1nFD9

R111
/

ft

O')

::l

~ "gCD'�

p.)

:n

a5c �.
p.)
3

"Tl 0 0
3 3 c
ao�::l

1000�F

"Q_
:::;;

;i5;: '

+C1~ /1

(..i.i.." :E

;::;:

RL ::r

I U~'.;Ll1 ~~

".'.O...
CD

p.)

3

,,,b

"'O
I :::;; (..i.i.."

A
C119 l1�F

r

I1aonFX

d1RL

Fig. 17 Complete mains-fed ceramic stereo pick-up amplifier; for power supply see Fig. 16.

"O

-I 0
)...>... 0......

:~:r
3�
~ .
~

0 )>

!l.
�""
8�

::l

Signetics RF Communications
6W audio amplifier with preamplifier

Preliminary specification
TDA1010A

TDA1010A .f
<
0
r
~
~,,

November 1982

Fig. 18 Track side of printed-circuit board used for the circuit of Fig. 17 (Fig. 16 partly); p.c. board dimensions 169 mm x 118 mm.
117

7277935

Signetics RF Communications
6W audio amplifier with preamplifier

left channel right channel

output

input

left channel input

right channel output

Preliminary specification
TDA1010A

November 1982

Fig. 19 Component side of printed-circuit board showing component layout used for the circuit of Fig. 17 (Fig. 16 partly).
118

Signetics RF Communications
6W audio amplifier with preamplifier

Preliminary specification
TDA1010A

z 100..-~-.----,--,-,-...,.-,...,...,..,--~-.-~..-,.......,....,....,r-T"T"r-~-.-~,--,.......-,.--r-n-r-~-.-~,--,.......-7,.--7T7"9"T2T6t

channel

separation

(dB)

1----~---t----i--i-+-+-1-+-++-~--+-~+--,__,__,_t-t-t_,_~_,_~+---r----t---+--,_,_,...,.--~----,-~r-.,..--.,-,--.,.-.,-,-,

~

tt--..,typ

0 '-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

10

102

103

104

f (Hz)

105

Fig. 20 Channel separation of the circuit of Fig. 17 as a function of frequency.

November 1982

119

Signetics RF Communications
1 to 4W audio amplifier with preamplifier

Product specification
TDA1015

The TOA1015 is a monolithic integrated audio amplifier circuit in a 9-lead single in-line (SIL) plastic package. The device is especially designed for portable radio and recorder applications and delivers up to 4 W in a 4 n load impedance. The very low applicable supply voltage of 3,6 V permits 6 V applications.
Special features are: � single in-line (SIL) construction for easy mounting � separated preamplifier and power amplifier � high output power � thermal protection � high input impedance � low current drain � limited noise behaviour at radio frequencies

QUICK REFERENCE DATA
Supply voltage range Peak output current Output power at dtot = 10%
Vp=12V;RL=4n Vp= 9V;RL=4n Vp= 6V;RL=4n Total harmonic distortion at P0 = 1 W; RL = 4 n Input impedance preamplifier (pin 8) power amplifier (pin 6) Total quiescent current Operating ambient temperature Storage temperature

Vp IQM
Po Po Po dtot
lzd IZil
Itot Tamb Tstg

3,6 to 18 V max. 2,5 A

typ.

4,2 w

typ.

2,3 w

typ.

1,0 w

typ.

0,3 %

>

100 kn

typ.

20 kn

typ.

14 mA

-25 to+ 150 oc

-55 to+ 150 oc

120

Signetics RF Communications
1 to 4W audio amplifier with preamplifier

Product specification
TDA1015

RATINGS

Limiting values in accordance with the Absolute Maximum System (IEC 134)

Supply voltage

Vp

max. 18 v

Peak output current

max. 2,5 A

Total power dissipation

see derating curve Fig. 2

Storage temperature

Tstg

-55 to+ 150 oc

Operating ambient temperature

Tamb -25 to+ 150 oc

A.C. short-circuit duration of load during sine~wave drive; Vp = 12 V

max. 100 hours

Ptot H---+--+--+-+-+--t--1--+-+-+-+---+--+--+-+-+-t--t--+-+-+-t

(W)

~

5H--l--+-+-+-+-~l--f-+-+-+--T~--+--'--'-...._t--1-+-+-+-1
H----+--+--+-+-+-t--t--+-+-+-+----+-<L\H, hinefaitnsiitnek
~ ~ 1-+--+--+-+-+-t--lt--1-+-+-t--+--+--+-~~--r-+-+--+--+-+---t

2 ,5

H--+-+-t-H~ "".t~:-l""'hweiatthsoiunkt

+--t--1-+~~-+-+---+--+--+-+-i
'

~

~

OW-..l-L.J..-L-L-.l-..J_J_-1-..J.._L-..L_L--1.-.~...~...+.J~-'--L-.J'--'-~

-25 O

+50

+100

+150 lamb (�C)

Fig. 2 Power derating curve.

HEATSINK DESIGN
Assume Vp =12 V; RL =4 il; lamb= 45 oc maximum.
The maximum sine-wave dissipation is 1,8 W. 150-45_
Rth j-a = Rth j-tab + Rth tab-h + Rth h-a = l ,8 - 58 K/W�
Where Rth j-a of the package is 45 K/W, so no external heatsink is required.

122

Signetics RF Communications
1 to 4W audio amplifier with preamplifier

Product specification
TDA1015

D.C. CHARACTERISTICS Supply voltage range Repetitive peak output current
Total quiescent current at Vp = 12 V

Vp IQRM Itot

3,6to18 V

<

2 A

typ. 14 mA

<

25 mA

A.C. CHARACTERISTICS

Tamb = 25 �C; Vp = 12 V; RL = 4 S1; f = 1 kHz unless otherwise specified; see also Fig. 3.

A. F. output power at dtot= 10% (note 1) with bootstrap: Vp = 12 V; RL = 4 S1 Vp= 9V;RL=4S1 Vp= 6V;RL=4S1 without bootstrap: Vp=12V;RL=4S1
Voltage gain: preamplifier (note 2) power amplifier
total amplifier

Po

w typ. 4,2

Po

w typ. 2,3

Po

w typ. 1,0

Po

w typ. 3,0

Gv1 Gv2
Gvtot

typ. 23 dB typ. 29 dB typ. 52 dB
49 to 55 dB

Total harmonic distortion at P0 = 1,5 W Frequency response; -3 dB (note 3)

typ. 0,3 %

dtot

<

1,0 %

B

60 Hz to 15 kHz

Input impedance: preamplifier (note 4)

I Zi1 I

>

100 kS1

typ. 200 kS1

power amplifier
Output impedance preamplifier
Output voltage preamplifier (r.m.s. value)
< dtot 1% (note 2)
Noise output voltage (r.m.s. value; note 5) Rs=OS1
Rs= 10 kS1
Noise output voltage at f = 500 kHz (r.m.s. value)
B = 5 kHz; Rs= on
Ripple rejection (note 6) f= 100 Hz

1zi2I

typ.

I Zo1I

typ.

Vo(rms) typ.

20 kS1 1 kS1
0,8 v

Vn(rms) typ. Vn(rms) typ.

0,2 mV 0,5 mV

Vn(rms) typ.

8 �V

RR

typ. 38 dB

123

Signetics RF Communications
1 to 4W audio amplifier with preamplifier

Product specification
TDA1015

Notes 1. Measured with an ideal coupling capacitor to the speaker load.
2. Measured with a load resistor of 20 kU. 3. Measured at P0 = 1 W; the frequency response is mainly determined by Cl and C3 for the low
frequencies and by C4 for the high frequencies. 4. Independent of load impedance of preamplifier. 5. Unweighted r.m.s. noise voltage measured at a bandwidth of 60 Hz to 15 kHz (12 dB/octave). 6. Ripple rejection measured with a source impedance between 0 and 2 kU (maximum ripple
amplitude : 2 V). 7. The tab must be electrically floating or connected to the substrate (pin 9).

! C2

+ 1 �F

Rl

! C6
100nF
+

5

300kU

3

TDA1015

4

I Cl 8
H
'�O"F

2 Vp

V�I

9

7 6

l

C4

RL 4U
7Z89094.1

Fig. 3 Test circuit.

124

Signetics RF Communications
1 to 4W audio amplifier with preamplifier
APPLICATION INFORMATION

Product specification
TDA1015

C1 B
~I l�+F

Rl

330kS1

3

TDA1015

C3

9

100pF

7 6

C5

J

5,6kS1

1,8

nF

4 +C7
2 100�F

Fig. 4 Circuit diagram of a 1 to 4 W amplifier.

7Z89095

Itot
(mA) 1--l--l--+---+---~~+-+-+-+-+-+-+-+--+--+--+--+--t--t---r---r---r--r-r-;--;--r-r--.

I--.__.__.__.__.__+-+-+-+-+ typ

~

v?"

Fig. 5 Total quiescent current as a function of supply voltage. 125

Signetics RF Communications
1 to 4W audio amplifier with preamplifier

Product specification
TDA1015

10 dtot
(%)
7,5
5
2,5

Vp= 6V /.........._
[T

9V
/'-
T

12V
11
T

7Z89093

I

lL

! II

I

If

l

I

!

i ~

I
i I

1 _J_

ii

l 1

�

+
J_

J
T

_:_

l

I

I

I

7 I

J_

lL
] ~

I l

l1 ff

IJ_

1vlj_i 7 .Y L

-"

[?:: ::;:;;;;;, ~

h'

P0 (W)

10

Fig. 6 Total harmonic distortion as a function of output power across R L; - - with bootstrap;
- - - without bootstrap; f = 1 kHz; typical values. The available output power is 5% higher when
measured at pin 2 (due to series resistance of C10).

7Z89096

5

Po

IZ

IL

/I

(W)

IL

~

RL--4S1L17"

I.Ian

2,5

~ ~

ll'.:
~

~

~

~

lo!d 1'

~

~

.i..... i..-1

.i..... i..-

0

I""'

0

5

10

15 Vp (V) 20

Fig. 7 Output power across RL as a function of supply voltage with bootstrap; dtot = 10%; typical
values. The available output power is 5% higher when measured at pin 2 (due to series resistance of C10).

126

::;ignetics RF Communications
1 to 4W audio amplifier with preamplifier
10

Product specification
TDA1015
7Z78637.1

0

.....,...

z

lZl

rz_

-10

7._

typ
1""'
~ ~
~ ~ Ii ..l ~

-20
10

f (Hz)

Fig. 8 Voltage gain as a function of frequency; P0 relative to 0 dB= 1 W; Vp = 12 V; RL = 4 n.

7 278636. 1
10

dtot (%)

7,5

5

2,5
\ I\
N ......_
0 10

rf

typ

11
+"1

f (Hz)

Fig. 9 Total harmonic distortion as a function of frequency; P0 = 1 W; Vp = 12 V; RL = 4 n.

127

Signetics RF Communications
1 to 4W audio amplifier with preamplifier
!--100 Hz

Product specification
TDA1015

........ O'--~~~-'-~~_.._~...._---'~'--"-

_._~~~~.._~---'~__..~~_.__.__._~

1

10

R2 (kn)

10 2

Fig. 10 Ripple rejection as a function of R2 (see Fig. 4); Rs= O; typical values.

600
I-

--- _I --.. Rs= a,2 kn -......, ,........

7Z78633.1

~

IS

400

' "' ~

~

~

IS

~

200

Rs= 0
i--..

"""" ........... ....... r--.

0

1

10

R2 (kQ)

Fig. 11 Noise output voltage as a function of R2 (see Fig. 4); measured according to A-curve; capacitor C5 is adapted for obtaining a constant bandwidth.
128

Signetics RF Communications
1 to 4W audio amplifier with preamplifier

Product specification
TDA1015

10 2 ~~~..---.~,.-..,......,....,.....,....,....,'"T"""~~"'T""~-r--.--.--.-r-r-T"T"~~-,-~"'T""-r-r-r7'ZT"7'8T6"3"T2".'11 t-~~+---1r~~at-~ t-+-+++-~~;-~r--;---;--t-t--t-1H---~~-r-~-;---i--i--;--r-TT1

vn(rms) (�V)

Fig. 12 Noise output voltage as a function of frequency; curve a: total amplifier; curve b: power amplifier; B = 5 kHz; Rs= 0; typical values.

60

7Z78634.1

---- typ ::::::......,,

~

40

~ r-

1~

20

0

1

10

R2 (kS11

Fig. 13 Voltage gain as a function of R2 (see Fig. 4).

129

Slgnetlcs RF Communications
2 to 6W audio power amplifier with preamplifier

Prellmlnary spaclflcatlon
TDA1011A

The TDA 1011 A is a monolithic integrated audio amplifier circuit in a 9-lead single in-line (SIL) plastic

package. The device is especially designed for portable radio and recorder applications and delivers up

to 4 Win a 4 il load impedance. The device can deliver up to 6 W into 4 il at 16 V loaded supply in

mains-fed applications. The maximum permissible supply voltage of 24 V makes this circuit very

i'

suitable for d.c. and a.c. apparatus, while the low applicable supply voltage of 5,4 V permits 9 V

applications. The power amplifier has an inverted input/output which makes the circuit optimal for

applications with active tone control and spatial stereo. Special features are:

� single in-line (SIL) construction for easy mounting

� separated preamplifier and power amplifier

� high output power

� thermal protection

� high input impedance

� low current drain

� limited noise behaviour at radio frequencies

QUICK REFERENCE DATA

Supply voltage range
Peak output current
Output power at dtot = 10% �vp= 16V; RL =4il Vp = 12 V; RL = 4 il Vp= 9V;RL=4il Vp= 6V;RL=4il
Total harmonic distortion at P0 = 1 W; RL = 4 il Input impedance
preamplifier (pin 8)
Total quiescent current
Operating ambient temperature
Storage temperature

Vp

5,4 to 20 V

loM max.

3 A

Po typ. Po typ. Po typ. Po typ,
, dtot typ.

6,5 w 4,2 w 2,3 w 1,0 w
0,2 %

I lzi
Itot Tamb Tstg

>

100 kil

typ.

14 mA

-25 to+ 150 oc

-55 to+ 150 oc

January 1980

130

c... I:c>�
-I<�

~

.. I..\..).

...:>
CD

0

0

~
0

0)

JJ "Tl

-4

:;f

0 0

f 5o--fTRB

nR14

nR19

R21n

nR25

nR27

R33

I Iacll.

I

5�

l 03

I n~l I 1

"O 0

3 3 c :c>;�
..~-
:0>

:E

~ I IRS I I I R131 I I Rlsl I :fo4

r I :fos

I )

I ~R30 I

I

I (..[..). Ill 3

"O

TR17

I

. .....

I

I ....... I I

. ,)

::::;.;
I (..D..."

;::E:;:
~

w
~

R4Ll

I I

TR3

R7

D2

T
R9 I I I

~"I I I

I

I TR15 I---'
R18

I

r�'-fTRlBI I

R22

24

I

I

.:flftj R30

I

".O....
([)
Ill
3 ""2.

::::;.;

. I

I

I

I

I (..D..."
12

TR32

Rl

R2

R6

RIO

R23

ITR1J QTR:!KL/

R17

R32

9

8

7

6

~~

6

Fig. 1 Circuit diagram.

7Z84192

I

"ti

-I 0
I )...>...

~
~j" 5�
~..

t 0............

"O CD

)> ....

:0>

Signetics RF Communications
2 to 6W audio power amplifier with preamplifier

Preliminary specification
TDA1011A

RATINGS

Limiting values in accordance with the Absolute Maximum System (IEC 134)

Supply voltage

Vp

max.

24 v

Peak output current

loM max.

3 A

Total power dissipation

see derating curve Fig. 2

Storage temperature

Tstg -55 to+ 150 oc

Operating ambient temperature

Tamb -25 to+ 150 oc

A.C. short-circuit duration of load
during sine-wave drive; Vp = 12 V

max. 100 hours

Ptot t-1---+--+--+-+-+--1--<--+-+-+--+--+----+--+-+-+--,___.--+-+-+--1

(W)

\

5H--+--+--+-+-+--l---l--+-+-+--+--+-~-+t-t---+--+--+-+-+--1--<--+-+-+--+-___,_....,~

_.__._..__l--hinefaintsiitnek

l--+-+

-+

--!

2�5 l-H-+-r+-......,......,.-1~....,,..l.",t-.t.,hweiathtsoinukt ~l---l-+'~"""'+-+--1--+--+-+-+--1

r-...,.....

~

N

'

OL.L-....__.-'-....J-....__._._....J-.l-...L-'-....J-.l-...L-'-~~~~...1..-.1.-..1.--'---'

-25 0

+50

+100

+150 Tamb(�C)

Fig. 2 Power derating curve.
HEATSINK DESIGN Assume Vp = 12 V; RL = 4 il;Tamb = 60 �c maximum; P0 = 3,8 W. The maximum sine-wave dissipation is 1,8 W. The derating of 10 K/W of the package requires the following external heatsink (for sine-wave drive):
150-60 Rth j-a = Rth j-tab + Rth tab-h + Rth h-a = 1,8 = 50 K/W � Since Rth j-tab = 10 K/W and Rth tab-h = 1 K/W, Rth h-a = 50 - (10 + 1) = 39 K/W.

January 1980

132

Signetics RF Communications
2 to 6W audio power amplifier with preamplifier

Preliminary specification
TDA1011A

D.C. CHARACTERISTICS Supply voltage range Repetitive peak output current
Total quiescent current at Vp = 12 V

Vp IORM

5,4 to 20 V

<

2A

typ.

14 mA

<

22 mA

A.C. CHARACTERISTICS
�c; Tamb = 25 Vp = 12 V; RL = 4 n; f = 1 kHz unless otherwise specified; see also Fig. 3.

A. F. output power at dtot = 10% (note 1) with bootstrap: Vp=16V;RL=4n
Vp=12V;RL=4n
Vp= 9 V; RL = 4 n Vp= 6V;RL=4n

Po

typ. 6,5 w

>

3,6 w

Po

typ. 4,2 w

Po

typ. 2,3 w

Po

typ. 1,0 w

without bootstrap: Vp=12V;RL=4n

Po

typ. 3,5 w

Voltage gain: preamplifier (note 2)

typ.

23 dB

Gv1

21 to 25 dB

power amplifier (note 3) total amplifier (note 3)

Gv2

typ.

29 dB

Gv tot

typ.

52 dB

Total harmonic distortion at P0 = 1,5 W

typ. 0,3 %

dtot

<

1 %

Frequency response; -3 dB (note 4)

B

60 Hz to 15 kHz

Input impedance: preamplifier (note 5)
Output impedance preamplifier Output voltage preamplifier (r.m.s. value)
dtot < 1% (note 2)

I2 i1 I IZo1 I

>

100 kn

typ. 200 kn

typ.

kn

Vo(rms) >

1,2 v

Noise output voltage (r.m.s. value; note 6) Rs= on
Rs= 10 kn

V n(rms) typ. V n(rms) typ.

0,5 mV 0,8 mV

Noise output voltage at f = 500 kHz (r.m.s. value) B = 5 kHz; Rs= on

Vn(rms) typ.

8 1N

Ripple rejection (note 6) f = 1 to 10 kHz f = 100 Hz; C2 = 1 �F

RR

typ.

42 dB

RR

>

35 dB

Bootstrap current at onset of clipping; pin 4 (r.m.s. value) Stand-by current at maximum Vp (note 8)

l4(rms) lsb

typ.

35 mA

<

100 �A

January 1980

133

Signetics RF Communications
2 to 6W audio power amplifier with preamplifier

Preliminary specification
TDA1011A

Notes 1. Measured with an ideal coupling capacitor to the speaker load.
2. Measured with a load resistor of 20 kn.
3. Measured with R2 =20 kn.
4. Measured at P0 = 1 W; the frequency response is mainly determined by C1 and C3 for the low frequencies and by C4 for the high frequencies.
5. Independent of load impedance of preamplifier. 6. Unweighted r.m.s. noise voltage measured at a bandwidth of 60 Hz to 15 kHz (12 dB/octave).
7. Ripple rejection measured with a source impedance between 0 and 2 kn (maximum ripple amplitude: 2 V).
8. The total current when disconnecting pin 5 or short-circuited to ground (pin 9).
9. The tab must be electrically floating or connected to the substrate (pin 9).

c2!

100nF

R1 300kn

! stand-by switch

l C1
c;>-1

8

100oF

5

3

TDA1011A

vi

9

7 6

I

C3 100nF

R2 20 kn

C4

6,SnF

c6! 100 nF
4 +
C7 100 �F 2
cs 100nF

Fig. 3 Test circuit.

+
+
Vp
RL
4n
7284190.1

January 1980

134

Signetics RF Communications
2 to 6W audio power amplifier with preamplifier
APPLICATION INFORMATION

Preliminary specification
TDA1011A

R1 330kD

C1
rl11 �F+
V�I
j

5

3

TDA1011A

4

2 8

._~~~9~~--+~~~-t-6~'""""1~~~~--
C3
100 pF

C6
150nF
+ C7 100�F
CB 100nF

Fig. 4 Circuit diagram of a 4 W amplifier.

7284191.1

1tot l-.1-.1-.l-.l--1--1--1--+--+-+--+--+--+--+--+-+-+-+-+-+-+-+--t--t--t---!r-r-t--t-1
(mA)L-.!..-.!..-.!..-1--1--1--1--f--lf--lf--lf--lf--lf--lf--lf--l--+--+--+--+--+--+--t--t-t---t-t--t--t----1
201--k-l---+-l--+-l--l--+-+-+-+-1---1--+-+-+-+--+--+-+i.--+t---::b....,.."'t-+-+-+-t-t--1
1-+..-+..--1---1--.+---.+----+--+--+--+--+--+--~ +tYP ~

January 1980

Fig. 5 Total quiescent current as a function of supply voltage. 135

Signetics RF Communications
2 to 6W audio power amplifier with preamplifier

Preliminary specification
TDA1011A

10 7Z78631.1

9V
../"-

12V 14V 16V
/\ /I A

I

!

IJ

d tot
(%)

I
I

[rTr

T

11 1

l

11 I

J.

I r1rr

7,5 1---.-1--+--1-+-+-+-++---+---t--+-r,+-+-t-+tt-l---'l'----i>i----t--t-t-:-ilt..-lL...-+-+-+-!

I

l

I II

I �1

l

l

J_

I

l l

I lJ rr 2,5t----+---l--l--+--+-i-+++---+--~~----r-.-t-++,lll----+1-o_-i_--lff-~-+-+-t-H

-j_ I

L~'

Fig. 6 Total harmonic distortion as a function of output power across RL; - - with bootstrap; - - - without bootstrap; f = 1 kHz; typical values. The available output power is 5% higher when measured at pin 2 (due to series resistance of C10).

I I I

7Z82488
~ .~

ll

VI

51-++-+-+-+-++-+-+-+-++-+-+-+-+-+-i-+-+-+-+-1-+-+-+-1-U..++-+-+-+-+~IILZi-+-1-+-+-+-+-1-+-+-1

IZ

~

y ~

(W) i--+-+-+-+--+-+-+-i-+-+-+-+-i-+-+-+-+-ii-+-+-+-+--_.Y.._+-+-+--+.I.L;.o~'+-+-+--+-+-+-i-+-+-+-+-ii-+-+-+~

T

l.2

,., ,., 2,51-+++-H-+-t-+-++-+-+--H~+-+++~~~--H~~12'1~1�++-+-1-+-t-+-++-+-+--H~+-++-+-+--1

I.;'
12'1

.,,,. ~

I' ..,..f'

l.Z....., ..-I

0

0

5

10

15

Vp(V)

20

Fig. 7, Output power across RL as a function of supply voltage with bootstrap; dtot = 10%; typical

values. The available output power is 5% higher when measured at pin 2 (due to series resistance of C1

January 1980

136

Signetics RF Communications
2 to 6W audio power amplifier with preamplifier

Preliminary specification
TDA1011A

10 2 .--~~...---.l"!...--..---T"""l,......,...............-~~""T"""~...-........""T"""T""'1-r-l"'T"""~~........~""T"""....,......,..7..Z,.7..8.T6'"T3".2,..1.,
1--~~+--'-l~:...:~~+-1--+-+++-~~-+-~+---+--+-+-+--Hf-+-~~-1-~-+---+---+--+-+-+-+-t
I-----+---+-~ ~
vn(rms) (�V)
~
101--~~+--'-ll---+--+-t-+-+-+-+-~~-+-~+-.....:..:. s:-+-......,1-+-+-+-~~--+-~-+---+---+--+-+-+-+-t :'S

Fig. 8 Noise output voltage as a function of frequency; curve a: total amplifier; curve b: power amplifier; B = 5 kHz; Rs= O; typical values.

January 1980

137

Slgnetlcs RF Communications
4W amplifier with DC volume control

Development Data
TDA1013B

GENERAL DESCRIPTION

The TOA 1013B is an integrated audio amplifier circuit with DC volume control, encapsulated in a 9-lead single in-line (SIL) plastic package. The wide supply voltage range makes this circuit ideal for applications in mains and battery-fed apparatus such as television receivers and record players.

The DC volume control stage has a logarithmic control characteristic with a range of more than 80 dB;

ii>

control is by means of a DC voltage variable between 2 and 6.5 V.

The audio amplifier has a well defined open loop gain and a fixed integrated closed loop. This device requires only a few external components and offers stability and performance.

Features
� Few external components � Wide supply voltage range � Wide control range � Pin compatible with TOA 1013A

� Fixed gain � High signal-to-noise ratio � Thermal protection

QUICK REFERENCE DATA parameter Supply voltage Repetitive peak output current Total sensitivity
Audio amplifier Output power Total harmonic distortion Sensitivity DC volume control unit Gain control range Signal handling
Sensitivity (pin 6)
Input impedance (pin 8)

conditions

symbol Vp

P0 = 2.5W; DC control at max. gain

IQRM Vi

THO= 10%; RL = 8 n Po=2.5W;RL=8n P0 =2.5W

Po THO V�I

THO< 1%; DC control = 0 dB
V0 = 125 mV; max. voltage gain

IL'lGvl
I Vi
Vi IZil

min. typ. 10 18

max. unit
40 v

-

-

1.5 A

44 55 69 mV

4.0 4.2 -

w

-

0.15 0.1 %

100 125 160 mV

80 -

-

dB

1.2 1.7 -

v

39

45

55

JmV

23 29 35 kn

June 1989

138

Signetics RF Communications
4W amplifier with DC volume control

Development Data
TDA1013B

7

6 5 4

3

TDA1013B

8

(

2

-(

9
PINNING 1 signal ground 2 amplifier output 3 supply voltage 4 electronic filter 5 amplifier input 6 control unit output 7 control. voltage 8 control unit input 9 power ground

input reference voltage B
Fig.1 Block diagram.

7Z21638.1

June 1989

139

Signetics RF Communications
4W amplifier with DC volume control

Development Data
TDA1013B

RATINGS Limiting values in accordance with the Absolute Maximum System (I EC 134)

parameter
Supply voltage Non-repetitive peak output current Repetitive peak output current Storage temperature range Crystal temperature Total power dissipation

symbol
Vp iosM IQRM Tstg Tc Ptot

min.

max.

unit

-

40

v

-

3

A

-

1.5

A

-65

+ 150

oc

-

+ 150

oc

see Fig. 2 .l

Ptot (W)
15i---+--~'\~~----i~-+--+--+~+-~
~
10>----+---+-----i~'\.--+-~~!----+---+-----i
~

50

100

150

lamb (0 C)

- - - - infinite heatsink without heatsink

Fig.2 Power derating curve.

HEATSINK DESIGN EXAMPLE
Assume Vp = 18 V; RL = 8 U; T amb = 60 �C; Tc= 150 �c (max.); for a 4 W application, the maximum dissipation is approximately 2.5 W. The thermal resistance from junction to ambient can be expressed as:
Rth j-a = Rth j-tab + Rth tab-h + Rth h-a =

T_,_im_ax_-_T_a_m_b_m-'-a_x = 150 - 60 = 36 K/W

Pmax

2.5

Since Rth j-tab = 9 K/W and Rth tab-h = 1 K/W, Rth h-a =36 - (9 + 1) = 26 K/W.

June 1989

140

Signetics RF Communications
4W amplifier with DC volume control

Development Data
TDA1013B

CHARACTERISTICS
�c; Vp = 18 V; RL = 8 n; f = 1 kHz; Tamb = 25 see Fiy.10; unless otherwise specified

parameter
Supply voltage range Total quiescent current Noise output voltage
at maximum gain at maximum gain at minimum gain Tot.'.I sensitivity

conditions

symbol min. typ.

Vp

I tot note 1

Rs=on

Vn

Rs= 5 kn

Vn

Rs= on

Vn

P0 =2.5W; DC control at max. gain V�I

10 18

-

25

-

0.5

-

0.6

-

0.25

44 55

max. unit
40 v
60 mA

-

mV

1.4 mV

-

mV

69 mV

Audio amplifier Repetitive peak output
current Output power Total harmonic distortion Sensitivity Input impedance (pin 5) Power bandwidth

THD=10%;RL=8n Po =2.5W; RL =8n P0 = 2.5W

lo RM Po THD V�I IZil Bp

--
4.0 4.2

1.5 A

-

w

-

0.15

1.0 %

100 125

160 mV

100 200

500 kn

-

30 to

40000 -

Hz

DC volume control unit Gain control range Signal handling
Sensitivity (pin 6)
Input impedance (pin 8) Output impedance (pin 6)

THD < 1%;
DC control = 0 dB
V0 = 125 mV; max. voltage gain

IL'iGvl 80 90

V�I
Vi IZil IZ0 1

1.2 1.7
39 44 23 29 45 60

-

dB

-

v

55 mV 35 kn 75 n

Note to the characteristics 1. Measured in a bandwidth in accordance with IEC 179, curve' A'.

June 1989

141

Signetics RF Communications
4W amplifier with DC volume control

Development Data
TDA10138

APPLICATION INFORMATION

7Z21640.1

I [l

7 s

8'1

250/

l---l----l----+-----l--74+----+,v/--+-7-+.i

June 1989

10

20

30

40

Fig.3 Output power as a function of supply voltage; f = 1 kHz; THD = 10% and control voltage (V7) = 6.5 V.

3
2 v1-'1
f
I/

7Z21641
r--.: N

0

0

2

3

4

Fig.4 Power dissipation as a function of output power; Vp = 18 V; f = 1 kHz; RL = 8 n and control voltage (V7) = 6.5 V.

142

Signetics RF Communications
4W amplifier with DC volume control

Development Data
TDA1013B

APPLICATION INFORMATION (continued)

v

v

3

t!

lL

vlL

7Z21642
\
~
~

0 10 I (Hz)
Fig.5 Power bandwidth; Vp = 18 V; RL = 8 SJ.; THO= 10% and control voltage (V7) = 6.5 V.

7Z21643

June 1989

THO
(%)
i
I\
r-t-++++t-t-1-t--""'
10 I (Hz)
Fig.6 Total harmonic distortion as a function of frequency;
Vp = 18 V; RL = 8 n; P0 = 2.5 Wand control voltage= 6.5 V.
143

Signetics RF Communications
4W amplifier with DC volume control

Development Data
TDA10138

10
THO
(%)
8

7Z21644

6

4

2

- _,.... ---1--

0

0.1

10

------ 10 kHz 1 kHz
Fig.7 Total harmonic distortion as a function of output power;
Vp = 18 V; RL = 8 n and control voltage= 6.5 V.

V7 1---+~+---t~--+-~t--+~+----t~--+-~t--t-~+----t~-t-~t---t-~-t----t~-t---j
~ y (Vls f--ll\--l--+--+--r---+--+--t---+--+-+---;---t-+---i---t-;---i----i--:1>L,......_..,

0'---'-~-'-~~~---''---'-~-'-~~~~~~~-'-~~~~~~~~~~~~

10 0

-20

-40

-60

-80

-0.6

-0.4

-0.2

0

0.2

gain control (dB)

17 (mA)

Fig.8 Typical control curve.

June 1989

144

Signetics RF Communications
4W amplifier with DC volume control

APPLICATION INFORMATION (continued)

7Z21646
0.6
~

0.4

I\

rj

0.2

I - -)....--"

Development Data
TDA10138

0

0

2

8

Fig.9 Noise output voltage as a function of the control voltage; Vp = 18 V; RL = 8 n (in accordance with IEC 179, curve 'A').

June 1989

0.22 �F 8

- 1 VI

t--"-----l

9

0.1 �F

6

5

4

$�+

VP

470 �F

"1 (1)

2 0.1 �F 3.3 !1

RL = 8 l1

7Z21639.1

(1) Belongs to power supply circuitry. Fig.10 Application diagram.

145

Slgnetlcs RF Communlcstlo.ns
1 Watt low voltage audio power amplifier

Preliminary specification
TDA7052

GENERAL DESCRIPTION The TDA7052 is a mono output amplifier in a 8-lead dual-in-tine (DI L) plastic package. The device is designed for battery-fed portable audio applications.

Features:
� No external components � No switch-on or switch-off clicks � Good overall stability � Low power consumption � No external heatsink required � Short-circuit proof

QUICK REFERENCE DATA

parameter

conditions

symbol

min. typ. max.

unit

Supply voltage range Tota I quiescent current Voltage gain Output power Total harmonic distortion

RL = oo
THO= 10%;8Q P0 =0,1W

Vp Itot Gv Po THO

3

6

15

v

-

4

8

mA

39

40

41

dB

-

1,2 -

w

-

0,2

1,0

%

July 1990

146

Signetics RF Communications
1 Watt low voltage audio power amplifier

Preliminary specification
TDA7052

Vp

-+----- I + i
input
~;~~~~) -~~-

output 2

PINNING

1 Vp

2 IN

3

GND1

4 n.c.

supply voltage input ground (signal) not connected

1Z25008
Fig. 1 Block diagram.

5 OUT1

output 1

6

GND2

ground (substrate)

7

n.c.

not connected

8

OUT2

output 2

July 1990

147

Signetics RF Communications
1 Watt low voltage audio power amplifier

Preliminary specification
TDA7052

FUNCTIONAL DESCRIPTION
The TDA7052 is a mono output amplifier designed for battery-fed portable audio applications, such as tape recorders and radios. The gain is fixed internally at 40 dB. A large number of tape recorders and radios are still designed for mono sound, plus a space-saving trend by reduction of the number of battery cells. This means a decrease in supply voltage which results in an reduction of output power. To compensate for this reduction, the TDA7052 uses the Bridge-Tied-Load principle (BTL) which can deliver an output power
n of 1,2 W (THO = 10%) into an 8 load with a power supply of 6 V. The load can be short-circuited
at each signal excursion.

RATINGS Limiting values in accordance with the Absolute Maximum System (IEC 134)

parameter
Supply voltage Non-repetitive peak output current Total power dissipation Crystal temperature Storage temperature range

symbol
Vp 'osM Ptot Tc Tstg

min. max. unit

-

18

v

-

1,5

A

see Fig. 2

oc - 1150 -65 + 150 oc

1200 I
Pt at (mW)
800
400
0 -25 0

1Z25007

~ ~ ~ ~ k \ ~

50

100

150

Tamb !�CI

Fig. 2 Power derating curve.

POWER DISSIPATION
Assume Vp =6 V; RL =8 Q; Tamb = 50 oc maximum.
The maximum sinewave dissipation is 0,9 W.
Rthj-a = -1-5-0--o5g0 ""110 K/W.

Where Rth j-a of the package is 110 K/W, so no external heatsink is required.

July 1990

148

Signetics RF Communications
1 Watt low voltage audio power amplifier

Preliminary specification
TDA7052

CHARACTERISTICS
Vp = 6 V; RL = 8 n; f = 1 kHz; T amb = 25 �c; unless otherwise specified.

parameter

conditions

symbol

min. typ,

max. unit

Supply Supply voltage range Total quiescent current Voltage gain Output power Noise output voltage
(RMS value)
Frequency response

Vp

3

RL = oo

Itot

-

Gv THO= 10% Po

.39

note 1 note 2

Vno(rms) -

Vno(rms) -

fr

-

Supply voltage ripple rejection note 3

SVRR

40

DC output offset voltage pin 5 to 8

Rs= 5 kn

~v5-s

-

Total harmonic distortion

P0 =0,1W

THO

-

Input impedance

IZ1I

-

Input bias current

I bias

-

6

15 v

4

8

mA

40

41

dB

1,2

-w

150

300 �V

60

-

�V

20 Hz to -

Hz

20 kHz

50

-

dB

-

100 mV

0,2

1,0 %

100

-

kn

100

300 nA

Notes to the characteristics
1. The unweighted RMS noise output voltage is measured at a bandwidth of 60 Hz to 15 kHz with a source impedance (Rs) of 5 kn.
2. The RMS noise output voltage is measured at a bandwidth of 5 kHz with a source impedance of On and a frequency of 500 kHz. With a practical load (R = 8 n; L = 200 �H) the noise output current is only 100 nA.
3. Ripple rejection is measured at the output with a source impedance of 0 n and a frequency between 100 Hz and 10 kHz. The ripple voltage= 200 mV (RMS value) is applied to the positive supply rail.

July 1990

149

Signetics RF Communications
1 Watt low voltage audio power amplifier

Preliminary specification
TDA7052

APPLICATION INFORMATION
~~~~~~~~~~~~~~~Vp=6V
r T+I 100nF 220�F , *

Rs= 5k!1
6

1Z25009

Fig. 3 Application diagram.

July 1990

150

Slgnetlcs RF Communlcstlons
1�Watt low voltage audio power amp with DC volume control

Objective specification
TDA7052A/AT

FEATURES
� DC volume control � Few external components � Mute mode � Thermal protection � Short-circuit proof � No switch on and off clicks � Good overall stability � Low power consumption � Low HF radiation � ESD protected on all pins

GENERAL DESCRIPTION
The TDA7052A/AT are mono BTL output amplifiers with DC volume control. They are designed for use in TV and monitors, but also suitable for battery-fed portable recorders and radios.

ORDERING INFORMATION

EXTENDED TYPE NUMBER
TDA7052A TDA7052AT

PINS 8 8

PACKAGE

PIN POSITION OIL
mini-pack

MATERIAL plastic plastic

CODE SOT97 SOT96A

QUICK REFERENCE DATA

SYMBOL Vp Po
G.,
qi Ip THO

PARAMETERS
supply voltage range output power
in 8 n (TDA7052A) in 16 n (TDA7052AT)
maximum total voltage gain gain control range total quiescent current total harmonic distortion

CONDITIONS

MIN. 4.5

Vp=6V

1

Vp=6 V

0.5

35

75

- Vp=6V;RL=oo

P0 =0.5W

-

TYP.
-
1.1 0.55 36 80 6 0.2

MAX. 18
-
-
37
-
12 1

UNIT
v
w w
dB dB mA %

August 1991

151

Signetics RF Communications
1-Watt low voltage audio power (lmp with DC volume control

Objecti110 specification
TDA7052A/AT

n.c.

7

TDA7052A TDA7052AT

pos~ive i n p u2t - + - - - - - - - ,

+-- I+ i

>-+---'5+-+ positive output

TDA7052A TDA7052AT
Fig.2 Pinning diagram.

- 1-i

>--+--+-8+-+ negative output

STABILIZER TEMPERATURE 1------~ PROTECTION

signal
ground
Fig.1 Block diagram.

power ground

/olCD385

PINNING
SYMBOL Vp IN+ GND1
vc
OUT+ GND2 n.c OUT-

PIN

DESCRIPTION

1

positive supply voltage

2

positive input

3

signal ground

4

DC volume control

5

positive output

6

power ground

7

not connected

8

negative output

August 1991

152

Signetics RF Communications
1-Watt low voltage audio power amp with DC volume control

Objective specification
TDA7052A/AT

FUNCTIONAL DESCRIPTION
The TDA7052A'AT are mono BTL output amplifiers with DC volume control, designed for use in TV and monitors but also suitable for battery fed portable recorders and radios. In conventional DC volume circuits the control or input stage is AC coupled to the output stage via external capacitors to keep the offset voltage low. In the TDA7052A'AT the DC volume control stage is integrated into the input stage so that no coupling capacitors are required and yet a low offset voltage is maintained. At the same time the minimum supply remains low.

The BTL principle offers the following advantages:
� Lower peak value of the supply current
� The frequency of the ripple on the supply voltage is twice the signal frequency.
Thus a reduced power supply with smaller capacitors can be used which results in cost savings.
For portable applications there is a trend to decrease the supply voltage, resulting in a reduction of output power at conventional output stages. Using the BTL principle increases the output power.

LIMITING VALUES In accordance with the Absolute Maximum System (IEC 134)

SYMBOL Vp IORM losM
P.,,
T.,,,b Tstg Tvi Tse V2
v.

PARAMETER supply voltage range repetitive peak output current non-repetitive peak output current total power dissipation TDA7052A TDA7052AT operating ambient temperature range storage temperature range virtual junction temperature short-circuit time input voltage pin 2 input voltage pin 4

CONDITIONS Tamb '.> 25%

The maximum gain of the amplifier is fixed at 36 dB. The DC volume control stage has a logarithmic control characteristic.
The total gain can be controlled from 36 dB to -44 dB. If the DC volume control voltage is below 0.3 V, the device switches to the mute mode. The amplifier is short-circuit proof to ground and Vp. Also a thermal protection circuit is implemented. If the crystal temperature rises above 150 �C the gain will be reduced, so the output power is reduced. Special attention is given to switch on and off clicks, low HF radiation and a good overall stability.

MIN.
-
-
-
-40
-55
-
-
-
-

MAX. 18 1 1.5
1.25 0.64 85 150 150 1 8 8

UNIT
v
A
A
w w oc oc oc
hr
v v

August 1991

153

Signetics RF Communications
1-Watt low voltage audio power amp with DC volume control

Objective specification
TDA7052A/AT

THERMAL RESISTANCE

SYMBOL Rlh i-�

PARAMETER from junction to ambient in free air TDA7052A TDA7052AT

Note
TDA7052A: Vp =6 V; RL =an.
The maximum sine-wave dissipation is 0.9 W. Therefore T�rrt><mex) = 150 � 100 x 0.9 = 60 �C.
TDA7052AT: Vp =6 v; RL =16 n.
The maximum sine-wave dissipation is 0.46 W.
= = Therefore T�rrt><mexl 150 � 155 x 0.46 78 �C.

TYP.

MAX.

UNIT

-

100

KN/

-

155

KN/

August 1991

154

Signetics RF Communications
1-Watt low voltage audio power amp with DC volume control

Objective specification
TDA7052A/AT

CHARACTERISTICS Vp = 6 V; T�.,.., = 25 �C; f = 1 kHz; unless otherwise specified (see Fig.6). TDA7052A: RL = 8 n; TDA7052AT: RL = 16 Q;

SYMBOL Vp Ip

PARAMETER supply voltage range total quiescent current

= Maximum gain; V4 1.4 V

Po

output power

TDA7052A

TDA7052AT

THO

total harmonic distortion TDA7052A TDA7052AT

Gv

voltage gain

V1

input signal handling

V no(rms)

noise output voltage (RMS value)

B

bandwidth

CONDITIONS
Vp=6V;RL=~
note 1
THO= 10%
= P0 0.5W
P0 = 0.25 W
V4 =1V;THD<1% f = 500 kHz; note 2

MIN. 4.5
-
1 0.5
-
-
35 0.6
-
-

RR

ripple rejection

note 3

40

IV0 HI

DC output offset voltage

-

Z1

input impedance (pin 2)

15

= Minimum gain; V4 0.5 V

Gv

voltage gain

-

v..,(rms)

noise output voltage RMS

note 4

-

value)

Mute position

Vo

output voltage in mute position V, ~ 0.3 V; V1 = 600 mV -

DC volume control

$

gain control range

75

1.

control current

V4 =0.4V

tbf

TYP.
-
6

MAX. 18 12

UNIT
v
mA

u

-

w

0.55

-

w

0.2

1

%

0.2

1

%

36

37

dB

-

-

v

tbf

-

�V

20 Hz to -

20 kHz

-

-

dB

tbf

150

mV

20

25

kn

-44

-

dB

20

30

�V

-

30

�V

80

-

dB

65

tbf

�A

Notes to the characteristics
1. With a load connected to the outputs the quiescent current will increase, the maximum value of this increase being equal to the DC output offset voltage dividend by RL.
2. The noise output voltage (RMS value) at f = 500 kHz is measured with Rs= On and bandwidth= 5 kHz.
= 3. The ripple rejection is measured with Rs= On and f 100 Hz to 10 kHz. The ripple voltage of 200 mV, (RMS
value) is applied to the positive supply rail.
4. The noise output voltage (RMS-value) is measured with Rs= 5 kn unweighted.

August 1991

155

Signetics RF Communications
1-Watt low voltage audio power amp with DC volume control

Objective specification
TDA7052A/AT

40 gain (dB)
20
0
-20
-40
-60
-60 0

MCD388
lZ'
Li
lL
i
7
I/

0.4

0.6

1.2

1.6

2.0

V4 (VJ

Fig.3 Gain control as a function of DC volume control.

1000 vnoise
(�V) 800
600
400
200
0 0

MC0389

L
I
i
I

v

0.4

0.8

1.2

1.6

2.0

v4 (V)

Fig.4 Noise output voltage as a function of DC volume control.

14 (�A)
60f---+--+--l-+---t--+~l---+--I-~
y 20f---+--+--l-+---+--+--J~~"-+-f--
~ -201----+-,l.L""~Y""f-7"t---+--+--+--+~f--
y
-6017"'-+--+----+-+--+--+--11--+--+-~

-100 ~~~~-~~~~-~~~

0

0.4

0.8

1.2

1.6

2.0

V4 (VJ

Fig.5 Control current as a function of DC volume control.

August 1991

156

Signetics RF Communications
1-Watt low voltage audio power amp with DC volume control

Objective specification
TDA7052A/AT

APPLICATION INFORMATION

(1)

= ~----.-----..------ Vp 6 V

I J:; 100 nF

+
220 �F

n.c.

positive input

047 �F

TDA7052A TDA7052AT

+
R L=B n
(TDA7052A) R L= 16 Q
(TDA7052NAT)

+
DC volume control

+
STABILIZER V ref

TEMPERATURE PROTECTION

ground

MCD386

(1) This capacitor can be omitted if the 220 �F electrolytic capacitor is connected close to pin 1.

Fig.6 Test and application diagram.

,--- 4

m
volume control

MCD387

Fig.7 Application with potentiometer as volume control; maximum gain= 30 dB.

August 1991

157

Slgnetlcs RF Communications
3.:watt mono BTL audio output amplifier

Objective specification
TDA7056A

FEATURES

GENERAL DESCRIPTION

� DC volume control

The TDA7056A is a mono BTL

I"

� Few external components

output amplifier with DC volume control. It is designed for use in TV

� Mute mode

and monitors, but also suitable for

� Thermal protection

battery-fed portable recorders and

� Short-circuit proof

radios.

� No switch-on and off clicks � Good overall stability � Low power consumption � Low HF radiation � ESD protected on all pins.

ORDERING INFORMATION

EXTENDED TYPE NUMBER
TDA7056A

PACKAGE

I I I PINS PIN POSITION MATERIAL CODE

9 l

SIL

1 plastic isornoBE

QUICK REFERENCE DATA

SYMBOL Vp Po
G.,
cl>
IP
THO

PARAMETER supply voltage range
output power in 16 n
voltage gain gain control range total quiescent current total harmonic distortion

CONDITIONS Vp= 12 V
Vp=12V;RL=oo Vp=0.5W

MIN.
4.5 3 35 75
-

TYP.
-
3.4 36 80 8 0.2

MAX.
18
-
37
-
16
1

UNIT
v w
dB
dB
mA
%

August 1991

158

Signetics RF Communications
3-Watt mono BTL audio output amplifier

Objective specification
TDA7056A

n.c.
TDA7056A
n.c.
positive input --+-+-------~

+- I+ i

~----6 ..--.. positive output

+-- I -i

> - - - t - -8 + - negative output

+
o - - - - - - - - - - STABILIZER TEMPERATURE

V ref

PROTECTION

4

signal ground
Fig.1 Block diagram.

power ground

MGA072

TDA7056A
MGA071
Fig.2 Pinning diagram.

PINNING
SYMBOL n.c. Vp
v,
GND1
vc
OUT+ GND2 OUTn.c.

PIN

DESCRIPTION

1 not connected

2 positive supply voltage

3 voltage input

4 signal ground

5 DC volume control

6 positive output

7 power ground

8 negative output

9 not connected

August 1991

159

Signetics RF Communications
3-Watt mono BTL audio output amplifier

Objective specification
TDA7056A

FUNCTIONAL DESCRIPTION
The TDA7056A is a mono BTL output amplifier with DC volume control, designed for use in TV and monitor but also suitable for battery-fed portable recorders and radios. In conventional DC volume circuits the control or input stage is AC coupled to the output stage via external capacitor to keep the offset voltage low. In the TDA7056A the DC volume stage is integrated into the input stage so that coupling capacitors are not required and a low offset voltage is maintained. At the same time the minimum

supply voltage remains low. The BTL principle offers the following advantages:
� lower peak value of the supply current
� the frequency of the ripple on the supply voltage is twice the signal frequency
Thus, a reduced power supply and smaller capacitors can be used which results in cost savings. For portable applications there is a trend to decrease the supply voltage, resulting in a reduction of output power at conventional output stages. Using the BTL principle increases the output power.

The maximum gain of the amplifier is fixed at 36 dB. The DC volume control stage has a logarithmic control characteristic. The total gain can be controlled from 36 dB to -44 dB. If the DC volume control voltage is below 0.3 V, the device switches to the mute mode. The amplifier is short-circuit proof to ground and Vp. Also a thermal protection circuit is implemented. If the crystal temperature rises above 150 �C the gain will be reduced, so the output power is reduced. Special attention is given to switch-on and off clicks, low HF radiation and a good overall stability.

LIMITING VALUES In accordance with the Absolute Maximum System (IEC 134)

SYMBOL Vp loRM losM
P1o1
Tamb T.,g Tvi Tse V3 Vs

PARAMETER supply voltage range repetitive peak output current non repetitive peak output current total power dissipation operating ambient temperature range storage temperature range virtual junction temperature short-circuit time input voltage pin 3 input voltage pin 5

CONDITIONS Tease< 60 �C

MIN.
-
-40 55
-

MAX. 18 1 1.5 9 85 150 150 1 8 8

UNIT
v
A
A
w oc oc oc
hr
v v

THERMAL RESISTANCE

SYMBOL
Rlhi-o R.,i..

PARAMETER from junction to case from junction to ambient in free air

TYP.
-

MAX. 10 55

UNIT K/W k/W

Note

VP= 12 V; RL = 16 Q; The maximum sine-wave dissipation is = 1.8 W. The Rih Vi.. of the package is 55 KJW�

Tamb(max)=150-55x1.8=51�C

'

August 1991

160

Signetics RF Communications
3-Watt mono BTL audio output amplifier

Objective specification
TDA7056A

CHARACTERISTICS
vp = 12 V; f = 1 kHz; AL = 16 n; Tamb = 25 �C; unless otherwise specified (see Fig.6)

SYMBOL Vp Ip

PARAMETER supply voltage range total quiescent current

CONDITIONS Vp = 6 V; AL= oo; note 1

MIN.

4.5 -

-

8

TYP.

Maximum gain (Vs= 1.4 V)

Po

output power

THD

total harmonic distortion

G.
v, vro(rrrs)

voltage gain input signal handling noise output voltage (RMS value)

B

bandwidth

RR

ripple rejection

IV0 ffl

DC output offset voltage

z,

input impedance pin 3

THD= 10%
= P0 0.5 W
Vs= 1V;THD<1% f = 500 kHz; note 2
note 3

3

3.4

-

0.2

35

36

0.6 -

-

tbf

-

20 Hz to

20 kHz

40 -

-

tbf

15

20

Minimum gain (V5 = 0.5 V)

Gv
vro(rrrs)

voltage gain
noise output voltage (RMS value)

note 4

-

-44

-

20

Mute position

Vo

- output voltage in mute position Vs~ 0.3 V; V, = 600 mV

-

DC volume control

ti>

gain control range

Is

control current

Vs= OV

75

80

tbf

65

MAX. 18 16

UNIT
v
mA

-w

1

%

37

dB

-v

-

.�V

-

-

dB

150 mV

25

kn

-

dB

30

�V

30

�V

-

dB

tbf

�A

Notes to the characteristics
1. With a load connected to the outputs the quiescent current will increase, the maximum value of this increase being equal to the DC output offset voltage divided by AL.
2. The noise output voltage (RMS value) at f = 500 kHz is measured with R. = On and bandwidth = 5 kHz. 3. The ripple rejection is measured with Rs= 0 n and f = 100 Hz to 10 kHz. The ripple voltage of 200 mV (RMS value)
is applied to the positive supply rail.
4. The noise output voltage (RMS value) is measured with Rs = 5 kn unweighted.

August 1991

161

Signetics RF Commljlllications
3-Watt mono BTL audio output amplifier

Objective specification
TDA7056A

40 gain (dB)
20
-20
-40
-60
-80 0

MGA075
k'.'.:
Lt1
i
f

0.4

0.8

1.2

1.6

2.0

Vs (V)

Fig.3 Gain as a function of DC volume control.

1000 vnoise
(�V) 800
600
400
200
0 0

MGA076

f

1
1
T

v

0.4

0.8

1.2

1.6

2.0

Vs (V)

Fig.4 Noise output voltage as a function of DC volume control.

's
(�A)

501---+--+~1---+--+~1---+--+~.___,

y 201---+--+~l---+--+~l--...Y.....-jo..+~.___,
~
y L -201---+--+~f-->~-+~t---+--+~.___,
-6017"-+--+~t---+--+~t---+--+~.___,

-100~~~~~~~~~~~~~

0

0.4

0.8

1.2

1.6

2.0

v5 (V)

Fig.5 Control current as a function of DC volume control.

August 1991

162

Signetics RF Communications
3-Watt mono BTL audio output amplifier

Objective specification
TDA7056A

APPLICATION INFORMATION

(1)
I 100nF

J;,+ 220 �F

positive input

n.c.

n.c.

9

0.47 �F 3

5

TDA7056A

.,.._ I+ i

6 +

+
DC
volume control

+---1-i

8

+
STABILIZER V ref

TEMPERATURE !------<~--~ PROTECTION

4

MGA073
ground
(1) This capacitor can be omitted if the 220 �F electrolytic capacitor is connected close to pin 2.
Fig.6 Test and application diagram.

r--15

100k!ll
m
volume control

MGA074

Fig.7 Application using a potentiometer for
= volume control; G. 30 dB.

August 1991

163

Signetics RF Communications

Section 2 Compandors

INDEX

Compandor Selector Guide

. . . . . . . . . . . . . . . . . . . . . . . . . . 166

NE570/571/SA571Compandor . . .

. ............................ 167

AN174

Applications for compandors NE570/571/SA571 .............. 174

AN 176

Compandor cookbook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

NE/SA572 Programmable analog compandor ......................... 189

AN175

Automatic level control using the NE572 .................... 197

NE/SA575 Low voltage compandor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

NE/SA575 ~~~:~l~~~;~;'~:,cipr.in�s�h�ri�n�k� sm~I ...................... 208

NE/SA576 Low power compandor .................................. 218

NE/SA577 Unity gain level programmable power compandor ............. 221

NE/SA578 Unity gain level programmable low power compandor .......... 225

AN1762

Companding with the NE577 and NE578 .................... 229

2$1

g

COMPANDOR FAMILY OVERVIEW

3

C Y....

NE570

NE571

NE572

NE575

NE576

NE577

NE578

3 c c::;I�

Q

:::!:

Vee

6-24V

6-18V

6-22V

3-7V

2-7V

2-7V

2-7V

0 ::I

Ice

3.2mA

3.2mA

6mA

3-5.5mA'

1-3mA*

14mA'

1-2mA*

"'

Number of Pins
Packages
NE: Oto+ 70C SA: -40 to +85 C
N: Plastic DIP D: Plastic SO F: CerDIP DJ: SSOP (Shrink Small
Outline Package)

16
NE570F NE570N NE570D

16
NE571F NE571N NE571D
SA571F SA571N SA571D

16
NE572N NE572D
SA572F SA572N SA572D

20
NE575N NE575D NE575DK
SA575N SA575D SA575DK

14 NE576N NE576D
SA576N SA576D

14 NE577N NE577D
SA577N SA577D

16 NE578N NE578D
SA578N SA578D

ALC

Both Channels Both Channels Both Channels Right Channel Right Channel Right Channel

Right Channel

8l

Reference Voltage

,...,
L:::::"'"" ""

~.av

Fixed2.5V

Vcc/2

Vcc/2

Vcc/2

Vcc/2

Unity Gain

775mVrms

775m~ 100mVrms

100mVrms

100mVrms ~OmV to 1V(rms) 10mV to 1V(rms)

Power Down Key Features

[S:No

NOL NO

NO

NO

NO

YES (170�A)

- Excellent Unity ~n!Unity

Gain Tracking Gain Tracking

Error

Error

- Excellent THO - Excellent THO

- Independent Attack& Release Time
-GoodTHD - Needs an Ext
Summing Op Amp

- 2 Uncommitted On-Chip Op Amps Available
- Low Voltage

-Low Power - Low External
Component
Count

-Low Power - Programmable
Unity Gain

-Low Power - Programmable
Unity Gain -Power Down - Mute Function -Summing
Capability (DTMF) -600'1 Drive
Capablllty

Appllcatlons

Cordless Phones

H1h Performance Hit Performance Hit Performance

udio Circuits

udio Circuits

udio Circuits

Cellular Phones

Wireless Mies

Modems

Consumer Audio

"Hi-Fi

"Hi-Fi

"Hi-Fl

Two-way Communications Commercial

Commercial

Studio

Quality"

Quality"

Quality"

Consumer Audio Circuits
"Commercial Quality"

Battery Powered Syatema
'Commercial Quality"

Battery Powered Systems
�commercial Quality'

Battery Powered Systems
'Commercial Quality"

NOTE: NE5750/5751 are also Excellent Audio Processor Components for High Performance Cordless and Cellular Applications that Include the Companding Function 'Ice varies with Vee

'V
~
i
g
3
'tJ 0
::I Cl) ::I
a f
::I Cl)
5"'
0
0
3
"C
D)
:::s
.0Q...
"'CD
-nCD ...0...
G')
cQ-�.
CD

Slgnetics RF Communications
Compandor

Product specification
NE570/571 /SA571

DESCRIPTION
The NE570/571 is a versatile low cost dual gain control circuit in which either channel may be used as a dynamic range compressor or expander. Each channel has a full-wave rectifier to detect the average value of the signal, a linerarized temperature-compensated variable gain cell, and an operational amplifier.
The NE570/571 is well suited for use in cellular radio and radio communications systems, modems, telephone, and satellite broadcast/receive audio systems.

FEATURES
� Complete compressor and expander in one !Chip
�Temperature.compensated � Greater than 11 OdB dynamic range � Operates down to 6VDC � System levels adjustable with external
components � Distortion may be trimmed out � Dynamic noise reduction systems � Voltage-controlled amplifier

PIN CONFIGURATION
D, F, and N Packages1
RECTCAP2 RECTIN2 AGeELLIN2
Vee
INV.IN2 RES. R3 2 OUTPUT2
TOP VIEW NOTE: 1. SOL - Released in Large SO Package Only.

ORDERING INFORMATION
DESCRIPTION 16-Pin Plastic SOL 16-Pin Cerdip 16-Pin Plastic DIP 16-Pin Plastic SOL 16-Pin Cerdip 16-Pin Plastic DIP 16-Pin Plastic SOL 16-Pin Cerdip 16-Pin Plastic DIP

APPLICATIONS
� Cellular radio � Telephone trunk compandor-570 � Telephone subscriber compandor-571 � High level limiter � Low level expander-noise gate � Dynamic filters �CD Player

TEMPERATURE RANGE
Oto +70�C
o to +70�C
Oto +70�C
o to +70�C oto +70�C
Oto +70�C
-40 to +85�C
-40 to +85�C
-40 to +85�C

ORDER CODE NE570D NE570F NE570N NE571D NE571F NE571N SA571D SA571F SA571N

BLOCK DIAGRAM
"GIN RECTIN

R220k R1 10k

INVERTER IN R320k
R4 30k

OUTPUT

June 7, 1990

167

853-0812 99768

Signetics RF Communications
Compandor

Product specification
NE570/571 /SA571

ABSOLUTE MAXIMUM RATINGS

SYMBOL

PARAMETER

Maximum operating voltage

Vee

570

571

Operating ambient temperature range

TA

NE

SA

Po Power dissipation

RATING
24 18
Oto70 -40to +85
400

UNITS
voe
�c
mW

AC ELECTRICAL CHARACTERISTICS Vee= +6V, TA= 25"C; unless otherwise stateel.

LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

NE570

MIN

TYP MAX

Vee Supply voltage

6

24

Ice Supply current lour Output current capability

No signal

3.2

4.8

�20

SR Output slew rate

�.5

Gain cell distortion2

Untrimmed Trimmed

0.3

1.0

0.05

Resistor tolerance

�5

�15

Internal reference voltage

1.7

1.8

1.9

Output DC shitt3

Untrimmed

�20

�100

Expandor output noise

No signal, 15Hz-20kHz1

20

45

Unity gain levels

1kHz

-1

0

+1

Gain change2� 4

�0.1

�0.2

Reference drilt4

�5

�10

Resistor drilt4

+1,-0

Tracking error (measured relative to value at unity
gain) equals [Vo - Vo (unity gain)] dB - V2dBm

Rectifier input, V2 = +6dBm, V, = OdB
V2=-30dBm, V1 =OdB

+0.2 +0.2 -0.5, +1

Channel separation

60

NOTES: 1. lnputto V1and V2 grounded. 2. Measured atOdBm, 1kHz. 3. Expandor AC input change from no signal to OdBm. 4. Relative to value at TA = 25"C. 5. Electrical characteristics for the SA571 only are specified over -40 to +85�C temperature range.
6. OdBm = 775mVRMS�

LIMITS

NEISA571 5

UNITS

MIN

TYP

MAX

6

18

v

3.2

4.8

mA

�20

mA

�.5

Vl�s

0.5 0.1

2.0

%

�5

�15

%

1.65

1.8

1.95

v

�30

�150 mV

20

60

�V

-1.5

0

+1.5 dBm

�0.1

dB

+2,-25 +20, -50 mV

+8,-0

%

+0.2

dB

+0.2 -1,+1.5

60

dB

June 7, 1990

168

Signetics RF Communications
Compandor

Product specification
NE570/571/SA571

CIRCUIT DESCRIPTION
The NE570/571 compandor building blocks, as shown in the block diagram, are a full-wave rectifier, a variable gain cell, an operational amplifier and a bias system. The arrangement of these blocks in the IC result in a circuit which can perform well with few external components, yet can be adapted to many diverse applications.
The full-wave rectifier rectifies the input current which flows from the rectifier input, to an internal summing node which is biased at VREF� The rectified current is averaged on an
external filter capacitor tied to the CRECT
terminal, and the average value of the input current controls the gain of the variable gain cell. The gain will thus be proportional to the average value of the input signal for capacitively-coupled voltage inputs as shown in the following equation. Note that for capacitively-coupled inputs there is no offset voltage capable of producing a gain error. The only error will come from the bias current of the rectifier (supplied internally) which is less than 0. 1�A.
G oc iVIN- VREF I avg
R1 or
Goe VIN I avg
R1
The speed with which gain changes to follow changes in input signal levels is determined by the rectifier filter capacitor. A small capacitor will yield rapid response but will not fully filter low frequency signals. Any ripple on the gain control signal will modulate the signal passing through the variable gain cell. In an expander or compressor application,
TYPICAL TEST CIRCUIT

this would lead to third harmonic distortion,
so there is a trade"off to be made between fast attack and decay times and distortion. For step changes in amplitude, the change in gain with time is shown by this equation.
G(t) = (Ginitial - Gt1naJ)e - t/r: + G11na1 ; -r = 10k X CRECT

The variable gain cell is a current-in, current-out device with the ratio louT/l1N controlled by the rectifier. 11N is the current which flows from the .1.G input to an internal summing node biased at VREF� The following equation applies for capacitively-coupled inputs. The output current, lour. is fed to the summing node of the op amp.

liN = VrN- VREF = V1N

R2

R2

A compensation scheme built into the .1.G cell compensates for temperature and cancels out odd harmonic distortion. The only distortion which remains is even harmonics, and they exist only because of internal offset voltages. The THO trim terminal provides a means for nulling the internal offsets for low distortion operation.

The operational amplifier (which is internally compensated) has the non-inverting input tied to VREF� and the inverting input connected to the .1.G cell output as well as brought out externally. A resistor, R3, is brought out from the summing node and allows compressor or expander gain to be determined only by internal components.

The output stage is capable of �20mA output current. This allows a +13dBm (3.SVRMs) output into a 3000 load which, with a series

Vee= 1sv

0.1�F
I
13

10�F
I

6.11

20k

resistor and proper transformer, can result in +13dBm with a 6000 output impedance.
A bandgap reference provides the reference voltage for all summing nodes, a regulated supply voltage for the rectifier and .1.G cell, and a bias current for the .1.G cell. The low tempco of this type of reference provides very stable biasing over a wide temperature range.

The typical performance characteristics illustration shows the basic input-output transfer curve for basic compressor or expander circuits.

;[ +20 . . . - - - - - - - - - - - .

:!!.
~ +10
~ 0

--------

8-10
S-20 -----
if tl -30
g
-' -40 ~
..~-so
!:;
~ -60 a:
m-70
II!
~ -ao
-40 -30 -20 -10 0 +10
COMPRESSOR OUTPUT LEVEL OR
EXPANDOR INPUT LEVEL (dBm)

Basic Input-Output Transfer Curve

V1 o-j

AG

7.10 Vo

30k

4

8.9

I 200pF

June 7, 1990

169

Signetics RF Communications
Compandor

Product specification
NE570/571 /SA571

INTRODUCTION
Much interest has been expressed in high performance electronic gain control circuits. For non-critical applications, an integrated circuit operational transconductance amplifier can be used, but when high-performance is required, one has to resort to complex discrete circuitry with many expensive, well-matched components. This paper describes an inexpensive integrated circuit, the NE570 Compandor, which offers a pair of high performance gain control circuits featuring low distortion (<0.1 %), high signal-to-noise ratio (90dB), and wide dynamic range (110dB).
CIRCUIT BACKGROUND
The NE570 Compandorwas originally designed to satisfy the requirements of the telephone system. When several telephone channels are multiplexed onto a common line, the resulting signal-to-noise ratio is poor and companding is used to allow a wider dynamic range to be passed through the channel. Figure 1 graphically shows what a compandor can do for the signal-to-noise ratio of a restricted dynamic range channel. The input level range of +20 to -80dB is shown undergoing a 2-to-1 compression where a 2dB input level change is compressed into a 1dB output level change by the compressor. The original 1OOdB of dynamic range is thus compressed to a 50dB range for transmission through a restricted dynamic range channel. A complementary expansion on the receiving end restores the original signal levels and reduces the channel noise by as much as 45dB.

on the IC). The full-wave averaging rectifier provides a gain control current, la, for the variable gain (AG) celt The output of the AG cell is a current which is fed to the summing node of the operational amplifier. Resistors are provided to establish circuit gain and set the output DC bias.

i!i
I I

INPUT I

I

!!< OUTPUT

+20-4------ -20 LEVa l:$

w LEVEL

OdB

I

OdB

A $:::= ~ -40 ____/

"--- -40

_-:Yj"-�- ~-

Figure 1. Restricted Dynamic Range Channel

CRECT

Vee PIN13 GND PIN4

Figure 2. Chip Block Diagram 1 of 2 Channels

The circuit is intended for use in single power supply systems, so the internal summing nodes must be biased at some voltage above ground. An internal band gap voltage reference provides a very stable, low noise 1.SV reference denoted VREF� The nOi'H'nverting input of the op amp is tied to
'JiiEF, and the summing nodes of the rectifier
anCI AG cell (located at the right of R, anc:!_,82) have the same potential. The THO trim pin is
a.rso at ll'le Vs5F potent1ql.
Figure 3 shows how the circuit is hooked up to realize an expandor. The input signal, V1N. is applied to the inputs of both the rectifier and the AG cell. When the input signal drops by 6dB, the gain control current will drop by a factor of 2, and so the gain will drop 6dB. The output level at Vourwill thus drop 12dB, giving us the desired 2-to-1 expansion.
Figure 4 shows the hook-up for a compressor. This is essentially an expandor placed in the feedback loop of the op amp. The AG cell is setup to provide AC feedback only, so a separate DC feedback loop is provided by the two Roe and Coe. The values of Roe will detenmine the DC bias at the output of the op amp. The output will bias to:
v.OUDCT=1+ Roc1 R+4 RDC2
VREF= ( 1 +R3o0crio(r) 1.BV

The significant circuits in a compressor or expander are the rectifier and the gain control element. The phone system requires a simple full-wave averaging rectifier with good accuracy, since the rectifier accuracy determines the (input) output level tracking accuracy. The gain cell determines the distortion and noise characteristics, and the phone system specifications here are very loose. These specs could have been met with a simple operational transconductance multiplier, or OTA, but the gain of an OTA is proportional to temperature and this is very undesirable. Therefore, a linearized transconductance multiplier was designli'd which is insensitive to temperature and offers low noise and low distortion perfonmance. These features make the circuit useful in audio and data systems as well as in telecommunications systems.

NOTE: GAIN � 2 83 VtN (avg) R1 R2 ls le= 140�A
'EXTERNAL COMPONENTS

I 'CRECT

Figure 3. Basic Expander

vouT

BASIC CIRCUIT HOOK-UP AND OPERATION
Figure 2 shows the block diagram of one half of the chip, (there are two identical channels

June 7, 1990

170

Signetics RF Communications
Compandor

Product specification
NE570/571/SA571

The output of the expander will bias up to:
Vour DC = 1 + RR.3i VREF
VREF= ( 1 + ~~~) 1.8V = 3.0V
The output will bias to 3.0V when the internal resistors are used. External resjS)ors may be placed in series witil'R;, (which will affect the
gain), or in parallel with & to raise the DC
bfas to any desired value.

V-

CtN Ra o-{ l-'INv-+----1 V1N

VouT

N:::( )t R1Rzl9 2R3 YJNavg Is= 140JiA
External componenta
Figure 4. Basic Compressor

Figure 5, Rectifier Concept
CIRCUIT DETAILS-RECTIFIER
Figure 5 shows the concept behind the full-wave averaging rectifier. The input current to the summing node of the op amp, V1NR1, is supplied by the output of the op amp. If we can mirror the op amp output current into a unipolar current, we will have an ideal rectifier. The output current is averaged by Rs, CR, which set the averaging time constant, and then mirrored with a gain of 2 to become IG, the gain control current.

NOTE:
IG = 2-V-I"N"aRvg'l
Figure 6. Simplified Rectifier Schematic

Figure 6 shows the rectifier circuit in more detail. The op amp is a one-stage op amp, biased so that only one output device is on at a time. The non-inverting input, (the base of 0 1), which is shown grounded, is actually tied to the internal 1.8V VREF� The inverting input is tied to the op amp output, (the emitters of Os and Os), and the input summing resistor R1� The single diode between the bases of Os and Os assures that only one device is on at a time. To detect the output current of the op amp, we simply use the collector currents of the output devices Os and Os. Os will conduct when the input swings positive and Os conducts when the input swings negative. The collector currents will be in error by the a of Os or Os on negative or positive signal swings, r~spectively. ICs such as this have typical NPN ~s of 200 and PNP ~s of 40. The a's of 0.995 and 0.975 will produce errors of 0.5% on negative swings and 2.5% on positive swings. The 1.5% average of these errors yields a mere 0.13dB gain error. At very low input signal levels the bias current of~' (typically 50nA), will become significant as it must be supplied by Os. Another low level error can be caused by DC coupling into the rectifier. If an offset voltage exists between the V1N input pin and the base of 0 2 , an error current of Vos/R1 will be generated. A mere 1mV of offset will cause an input current of 1OOnA which will produce twice the error of the input bias current. For ~t accuracy, the rectifier should becou � ta 1ve y. thigh input levels the ~of the ~P Os win begin to suffer, and there will be an increasing error until the circuit saturates. Saturation can be avoided by limiting..Jb.e
-~info the rectifier input to 250�A. If
necessary, an external resistor may be

placed in series with R~ to limit the current to this value. Figure 7 shows the rectifier a.ccuracyvs input level at a frequency of 1kHz.
...,
z
~
:!i 0
ffi

-20

0

RECTIFIER INPUT dBm

Figure 7. Rectifier Accuracy

At very high frequencies, the response of the rectifier will fall off. The roll-off will be more pronounced at lower input levels due to the increasing amount of gain required to switch between 0 5 or Os conducting. The rectifier frequency response for input levels of OdBm, -20dBm, and -40dBm is shown in Figure 8. The response at all three levels is flat to well above the audio range.

June 7, 1990

171

Signetics RF Communications
Com pander

Product specification
NES?0/571 /SA571

V+
! r
z3
~

10k

1MEG

FREQUENCY (Hz)

Figure 8. Rectifier Frequency Response vs Input Level

VARIABLE GAIN CELL
Figure 9 is a diagram of the variable gain cell. This is a linearized two-quadrant transconductance multiplier. 0 1, 0 2 and the op amp provide a predistorted drive signal for the gain control pair, 0 3 and 0 4 . The gain is controlled by IG and a current mirror provides the output current.
The op amp maintains the base and collector of 0 1 at ground potential (VREF) by controlling the base of 0 2. The input current l1N (=V1NIR2) is thus forced to flow through 0 1 along with the current 11, so lc1=1 1+1 1N. Since 12 has been set at twice the value of 11, the current through 02 is:

l2-(l1+l1N)=l1-l1N=lc2-
The op amp has thus forced a linear current swing between 0 1 and 0 2 by providing the proper drive to the base of 0 2. This drive signal will be linear for small signals, but very non-linear for large signals, since it is compensating for the non-linearity of the differential pair, 0 1 and 0 2, under large signal conditions.
The key to the circuit is that this same predistorted drive signal is applied to the gain control pair, 0 3 and 0 4. When two differential pairs of transistors have the same signal applied, their collector current ratios will be identical regardless of the magnitude of the currents. This gives us: /C1 /04 /1 + f1N IC2 = /03 = l1-l1N

plus the relationships IG=lc3+104 and lour=l04-lc3 will yield the multiplier transfer function,

lour = Jg_ l1N = ViN Jg_

/1

R2 /1

This equation is linear and temperature-insensitive, but it assumes ideal transistors.

V-

Figure 9. Slmpllfled AG Cell Schematic

Vos=smv
4mV 3mV 2mV 1mV

-6

+8

INPUT LEVEL (dBm)

Figure 10. AG Cell Distortion vs Offset Voltage

second harmonic dis~.shows 'the simple trim netWork required.
~,..
Figure 12 shows the noise performance of the AG cell. The maximum output level before clipping occurs in the gain cell is plotted along with the output noise in a 20kHz bandwidth. Note that the noise drops as the gain is reduced for the first 20dB of gain reduction. At high gains, the signal to noise ratio is 90dB, and the total dynamic range from maximum signal to minimum noise is 110dB.
v c

If the transistors are not perfectly matched, a

parabolic, non-linearity is generated, which

results in second harmonic distortion. Figure

10 gives an indication of the magnitude of the

distortion caused by a given input level and

offset voltage. The distortion is linearly

proportional to the magnitude of the offset

and the input leyel. Saturation of the gain cell

occurs at a +SdBm level. At a nominal

operating level of OdBm, a 1mV offset will

yield 0.34% of second harmonic distortion.

Most circuits are somewhat better than this,

which/"eans our overall offsets are typically

about mV. The distortion is not affected by

the magnitude of the gain control current, and

it does not increase as the gain is changed.

This second harmonic distortion could be

eliminated by making perfect transistors, but

since that would be difficult, we have had to

resort to other methods. A trim in has be

provided to allow trimmin

al

~d

R

Q{I e.211

3.&V

~ 20k
To THO Trim

J_ �200pF
I

Centro �

generated in the

gain cell by imperfect device matching and

mismatches in the current sources, 11 and 12.

When no input signal is present, changing IG

will cause a small output signal. The

distortion trim is effective in nulling out any

control signal feedthrough, but in general, the

null for minimum feedthrough will be different

than the null in distortion. The control signal

feedthrough can be trimmed independently of

distortion by tying a current source to the AG

June 7, 1990

172

Signetics RF Communications
Compandor

Product specification
NE570/571/SA571

input pin. This effectively trims 11. Figure 13 shows such a trim network.
+20 0
90clB
j

OPERATIONAL AMPLIFIER
The main op amp shown in the chip block diagram is equivalent to a 741 with a 1MHz bandwidth. Figure 14 shows the basic circuit. Split collectors are used in the input pair to reduce QM. so that a small compensation
capacitor of just 1OpF may be used. The
output stage, although capable of output currents in excess of 20mA, is biased for a low quiescent current to conserve power. When driving heavy loads, this leads to a small amount of crossover distortion.

0.5% change for the implemented resistors. The implanted resistors have another advantage in that they can be made the size of the diffused resistors due to the higher resistivity. This saves a significant amount of chip area.

-IN

OUT

-80
-20 VCA GAIN (OdB)
Fl ure 12. D amlc Ran e of NE570
Vee
R.SELECT FOR)
1 a.sv..... ------
470k 100k ~ TOPIN30R14
Figure 13. Control ~lgnal Feedthrough Triill

RESISTORS
Inspection of the gain equations in Figures 3 and 4 will show that the basic compressor
and expander circuit gains may be set
entirely by resistor ratios and the internal voltage reference. Thus, any form of resistors that match well would suffice for these simple hook-ups, and absolute accuracy and temperature coefficient would be of no importance. However, as one starts to modify the gain equation with external resistors, the internal resistor accuracy and tempco become very significant. Figure 15 shows the effects of temperature on the diffused resistors which are normally used in integrated circuits, and the ion-implanted resistors which are used in this circuit. Over the critical 0�C to +70�C temperature range, there is a 1O-to-1 improvement in drift from a 5% change for the diffused resistors, to a

Figure 14. Operational Amplifier

1.15

140U/D

~

DIFFUSED RESISTOR

~ 1.10

iii
a:
~ 1.05

1kn1 0
LOW TC IMPLANTE RESISTOR

; 1.00 ~:ss;s~~a~:ss~ 1% ERROR

!i!

BAND

.95 -40

40 80 120 TEMPERATURE

Fl ure 15. Resistance vs Tem erature

~- I -~~I\�-If\,('J.;O-K� th
11*11

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Application note
AN174

APPLICATIONS
The following circuits will illustrate some of the wide variety of applications for the NE570.

BASIC EXPANDOR
Figure 1 shows how the circuit would be hooked up for use as an expander. Both the rectifier and ti.G cell inputs are tied to V 1N so that the gain is proportional to the average value of (V1N). Thus, when V1N falls 6dB, the gain drops 6dB arid the output drops 12dB. The exact expression for the gain is

G. [2 ain exp. =

R, VIN (avg)] 2

R1 Rz lB

la= 140�A
The maximum input that can be handled by the circuit in Figure 1 is a peak of 3V. The rectifier input current can be as large as 1=3VIR1=3V/10k=300�A. The ti.G cell input current should be limited to 1=2.8V/R2=2.8V/20k=140�A. If it is necessary to handle larger input voltages than O�2.BV peak, external resistors should be placed in series with R 1 and R2 to limit the input current to the above values.
Figure 1 shows a pair of input capacitors C1N1 and C 1N2� It is now necessary to use both capacitors if low level tracking accuracy is not important. If R1 and R2 are tied together and share a common capacitor, a small current will flow between the ti.G cell summing node and the rectifier summing node due to offset

The output of the expander is biased up to 3V
by the DC gain provided by R3, A,i. The
output will bias up to
R, Voumc = I+ R4 VREF
For supply voltages higher than 6V, R.i can
be shunted with an external resistor to bias the output up to Vee.
Note that it is possible to externally increase
R1, R2, and R3, and to decrease R3 and A,i.
This allows a great deal of flexibility in setting up system levels. If larger input signals are to be handled, R1 and R2 may be increased; if a larger output is required, R3 may be
increased. To obtain the largest dynamic range out of this circuit, the rectifier input should always be as large as possible (subject to the �300�A peak current restriction).
BASIC COMPRESSOR
Figure 2 shows how to use the NE570/571 as a compressor. It functions as an expander in the feedback loop of an op amp. If the input rises 6dB, the output can rise only 3dB. The 3dB increase in output level produces a 3dB increase in gain in the ti.G cell, yielding a 6dB increase in feedback current to the summing node. Exact expression for gain is
]t Gain comp. = [ R1 R2 [B 2 R, VIN (avg)

output. As in the expander, the rectifier arid ti.G cell inputs could be made common to save a capacitor, but low level tracking accuracy would suffer. Since there is no DC feedback path around the op amp through the ti.G cell, one must be provided externally. The pair of resistors Roe and the capacitor Coe must be provided. The op amp output will
Roe) bias up to(
= Vouwc I +Ii:; VREF
For the largest dynamic range, the compressor output should be as large as possible so that the rectifier input is as large as possible (subject to the �300�A peak current restriction). If the input signal is small, a large output can be produced by reducing R3 with the attendant decrease in input impedance, or by increasing R1 or R2. It would be best to increase R2 rather than R1 so that the rectifier input current is not reduced.

Roe
V1N
o-i t-"VV\,.+----t
C1N

Vour

R3

C1N1

R2

��{C1N2

R1

AG R4

Your

I eRECT
Figure 1. Basic Expander

voltages. This current will produce an error in the gain control signal at low levels, degrading tracking accuracy.

The same restrictions for the rectifier and ti.G cell maximum input current still hold, which place a _limit on the maximum compressor

Rgure 2. Basic Compre..or
DISTORTION TRIM
Distortion can be produced by voltage offsets in the ti.G cell. The distortion is mainly even harmonics, and drops with decreasing input signal (input signal meaning the current into the ti.G cell). The THO trim terminal provides
a means for trimming out the offset voltages and thus trimming out the distortion. The circuit shown in Figure 3 is suitable, as would be any other capable of delivering �30�A into
oon 1 resistor tied to 1.BV.
LOW LEVEL MISTRACKING
The compandor will follow a 2-to-1 tracking ratio down to very low levels. The rectifier is responsible for errors in gain, and it is the rectifier input bias current of <1 OOnA that

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Applications for compandors NE570/571/SA571

Application note
AN174

R3
C1N1 R2
~ { N l - - 2-VV-R1v---l......---J'----o

Your

I CRECT

Figure 4. Expandor With Low Level Mlstracklng

produces errors at low levels. The magnitude signal level drops to a 1�A average, the bias current will produce a 10% or 1dB error in gain. This will occur at 42dB below the maximum input level.
Vee

compression. The bleed current through RA will be a function of temperature because of the two VsE drops, so the low level tracking will drift with temperature. If a negative supply is available, if would be desirable to tie RA to that, rather than ground, and to increase its value accordingly. The bleed current will then be less sensitive to the VsE temperature drift.

ToTHDTrtm :
T � 200pF
Your
Figure 3. THO Trim Network
It is possible to deviate from the 2-to-1 tfanmararacrensiTC:aifowl-;;~~15�as sfiown
i~theCif~uii'ofFigura��4:"E1i'fierR~~f'R;, (ilut
not both). is requirecf.'ihe voltage on CRECT is 2xVsE plus V1N avg. For low level inputs V1N avg is negligible, so we can assume 1.3V as the bias on CRECT� If RA is placed from CRECT to AND we will bleed off a current 1=1.3V/RA. If the rectifier average input current is less than this value, there will be no gain control input to the t..G cell so that its gain will be zero and the expander output will be zero. As the input level is raised, the input current will exceed 1.3V/RA and the expander output will become active. For large input signals, RA will have little effect. The result of this is that we will deviate from the 2-to-1 expansion, present at high levels, to an infinite expansion at low levels where the output shuts off completely. Figure 5 shows some examples of tracking curves which can be obtained. Complementary curves would be obtained for a compressor, where at low level signals the result would be infinite

0

.fW.�...w~... -10

i....l....i.>~... -20

0.
" "! :

0~ .

:5ll!

0 a:

-40

aw: &z

~if

or:i

-70
-80~~~'-lf-'-~~~ -40 -30 -20 -10 0 +10
EXPANDOR INPUT LEVEL dB OR COMPRESSOR OUTPUT LEVEL
Figure 5. Mlstracklng With RA

Rs will supply an extra current to the rectifier equal to (Vcc-1.3V)Rs. In this case, the expander transfer characteristic will deviate towards 1-to-1 at low levels. At low levels the expander gain will stop dropping and the expansion will cease. In a compressor, this would lead to a lack of compression at low levels. Figure 6 shows some typical transfer curves. An Rs value of approximately 2.5M would trim the low level tracking so as to match the Bell system N2 trunk compandor characteristic.

+20 +10

".>.oW~....'...m..~>w.....,..

-10 -20

~8z~""- -30

(/)a:
izg

-40

1:21i:zf -so

8r:i -80

-70

-40 -30 -20 -10 0 +10 EXPANDOR INPUT LEVEL dB OR COMPRESSOR OUTPUT LEVEL
Figure 6. Mlstracklng With Re

15V

~ 330k

10M
~ TO RECTIFIER
INPUT PIN20R15

3.6V 100k

Figure 7. Rectifier Blas Current Compensation

-20 -40 -80
RECTIFER INPUT LEVEL, dBm
Figure 8. Rectifier Performance With Bias Current Com ensatlon

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Application note
AN174

ATTACK AND DECAY TIME

FAST ATTACK, SLOW RELEASE

The attack and decay times of the compandor are determined by the rectifier

HARD LIMITER The NE570/571 can be easily used to make

filter time constant 10kxCRECT� Figure 9 shows how the gain will change when the input signal undergoes a 10, 20, or 30dB

an excellent limiter. Figure 12 shows a typical circuit which requires of an NE570/571, of an LM339 quad comparator, and a PNP

change in level. The attack time is much faster than the

transistor. For small signals, the .1G cell is nearly off. and the circuit runs at unity gain as

iI "

12345878910 TIME CONSTANTS� 10K CRECT
Figure 9. Gain vs Time Input Steps of �10, �20, �30dB

decay, which is desirable in most applications. Figure 10 shows the compressor attack envelope for a+12dB step in input level. The initial output level of 1 unit instantaneously rises to 4 units, and then

set by Re. R7. When the output signal tries to exceed a +or -1V peak, a comparator threshold is exceeded. The PNP is turned on and rapidly charges C4 which activates the L\G cell. Negative feedback through the L\G

starts to fall towards its final value of 2 units. cell reduces the gain and the output signal

I~~

0

I

I

0 .1 .2 .3 A .5

.8' ,7'

I I
.8 .9

The CCITI recommendation on attack and decay times for telephone system compandors defines the attack time as when the envelope has fallen to a level of 3 units, corresponding to t=0.15 in the figure. The CCITI recommends an attack time of 3 �2ms, which suggests an RC product of

level. The attack time is set by the RC product of R1e and C4, and the release time is determined by C4 and the internal rectifier resistor, which is 10k. The circuit shown
attacks in less than 1ms and has a release
time constant of 100ms. Re trickles about
0. 7�A through the rectifier to prevent C4 from

TIME CONSTANTS� 10K CRECT

20ms. Figure 11 shows the compressor output envelope when the input level is

becoming completely discharged. The gain cell is activated when the voltage on Pin 1 or

Figure 10. Compressor Attack Envelope suddenly reduced 12dB. The output, initially 16 exceeds two diode drops. If C4 were

+12dBStep

at a level of 4 units, drops 12dB to 1 unit and allowed to become completely discharged,

then rises to Its final value of 2 units. The

there would be a slight delay before it

1: ~ ~1 t 0

I I I I I I I

0 .2 A .8 .8 1.0 1.2 1.4 1.8 1.8

CCITI defines release time as when the output has risen to 1.5 units, and suggests a value of 13.5 �9ms. This corresponds to t=0.675 in the figure, which again suggests a 20ms RC product. Since R1=10k, the CCITI recommendations will be met if CRecr=2�F.

recharged to >1.2V and activated limiting action.
A stereo limiter can be built out of 1 NE570/571, 1 LM339 and two PNP transistors. The resistor networks R12, R13 and R14, R1s. which set the limiting

TIME CONSTANTS =10K CRECT

There is a trade-off between fast response

thresholds, could be common between

Figure 11. Compressor Release

and low distortion. If a small CRecr is used to channels. To gang the stereo channels

Envelope -12dB. Step

get very fast attack and decay, some ripple

together (limiting in one channel will produce

will appear on the gain control line and

a corresponding gain change in the second

produce distortion. As a rule, a 1�F CRecT

channel to maintain the balance of the stereo

RECTIFIER BIAS CURRENT

will produce 0.2% distortion at 1kHz. The

image), then Pins 1 and 16 should be

CANCELLATION

distortion is inversely proportional to both

jumpered together. The outputs of all 4

The rectifier has an input bias current of

frequency and capacitance. Thus, for

comparators may then be tied together, and

between 50 and 1OOnA. This limits the

telephone applications where CRecr=2�F, the only one PN P transistor and one capacitor C4

dynamic range of the rectifier to about 60dB. ripple would cause 0.1% distortion at 1kHz

need be used. The release time will then be

It also limits the amount of attenuation of the and 0.33% at 800Hz. The low frequency

the product 5kxC4 since two channels are

'1G cell. The rectifier dynamic range may be distortion generated by a compressor would being supplied current from C4.

increased by about 20dB by the bias current be cancelled (or undistorted) by an expandor,

trim network shown in Figure 7. Figure 8

providing that they have the same value of

USE OF EXTERNAL OP AMP

shows the rectifier performance with and

CRECT�

The operational amplifiers in the NE570/571

without bias current cancellation.

are not adequate for some applications.

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Applications for compandors NE570/571/SA571

Application note
AN174

2,15 IOK
RI 2.2MEG R3

214 LM339

l�F
IN~ RS Cl
IOOK
+15VP1n 13 GND Pln4
R1, R2' R.t are Internal to the NE57D/571

IOOK .'�~F R12 OUT C3 R11 IOOK
Figure 12. Fast Attack, Slow Release Hard Limiter

100'2 RIB

Figure 13. Use of External Op Amp
The slew rate, bandwidth, noise, and output drive capability can limit performance in many systems. For best performance, an external op amp can be used. The external op amp may be powered by bipolar supplies for a larger output swing.
Figure 13 shows how an external op amp may be connected. The non-inverting input must be biased at about 1.BV. This is easily accomplished by tying it to either Pin 8 or 9, the THO trim pins, since these pins sit at 1.BV. An optional RC decoupling network is shown which will filter out the noise from the NE570/571 reference (typically about 1O�V in 20kHz BW). The inverting input of the external op amp is tied to the inverting input of the internal op amp. The output of the external op amp is then used, with the internal op amp output left to float. If the external op amp is used single supply (+Vee and ground), it must have an input common-mode range down to less than 1.BV.

RGAIN TRIM l&K
S�F +

IO�F

._-A.II.Ar--+- vcc

2�F +I

R LOW LEVEL TRIM

-:- 43K 3 MEG 43K

>---...... ,.-. . 600'2: 20K ______, ~-'V\rv-

RouT

.245 VRMS 6000'2

_,'"if~~~ '------------<p-----�l-S�_F_4_.0K_

Figure 14. N2 Compressor

N2 COMPANDOR
There are four primary considerations involved in the application of the NE570/571 in an N2 compandor. These are matching of input and output levels, accurate 600Q input and output impedances, conformance to the Bell system low level tracking curve, and proper attack and release times.
Figure 14 shows the implementation of an N2 compressor. The input level of 0.245VRMS is

stepped up to 1.41VRMS by the 600Q: 20kQ matching transformer. The 20k input resistor properly terminates the transformer. An internal 20kn resistor (R3) is provided, but for accurate impedance termination an external resistor should be used. The output impedance is provided by the 4kn output resistor and the 4kn: 600Q output transformer.

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R 20K

600n: 1oon
::J
~

AG S..F
R1
~
1D�F

Application note
AN174

Figure 15. N2 Expander

The 0.275VRMS output level requires a 1.4V op amp output level. This can be provided by increasing the value of R2 with an external resistor, which can be selected to fine trim the gain. A rearrangement of the compressor gain equation (6) allows us to determine the value for R2. R1 = - Ga- in2-x - 2 R~, ~ VIN-a~ vg
R1 ls J2x 2x20kx 1.27
!Ok x 140�A
= 36.3k
The external resistance required will thus be 36.3k-20k=16.3k.
The Bell-compatible low level tracking characteristic is provided by the low level trim
resistor from CREeT to Vee- As shown in Figure 6, this will skew the system to a 1:1
transfer characteristic at low levels. The 2�F rectifier capacitor provides attack and release times of 3ms and 13.Sms, respectively, as shown in Figures 1Oand 11. The R-C-R network around the op amp provides DC feedback to bias the output at DC.
An N2 expander is shown in Figure 15. The input level of 3.27VRMS is stepped down to 1.33V by the GOOQ:1 OOQ transformer, which is terminated with a 1OOQ resistor for accurate impedance matching. The output impedance is accurately set by the 150Q output resistor and the 150Q:600Q output transformer. With this configuration, the 3.46V transformer output requires a 3.46V op amp output. To obtain this output level, it is necessary to increase the value of R3 with an

external trim resistor. The new value of R3 can be found with the expander gain equation
= R, R1 R1 ls Gain
2 VIN avg !Ok x 20k x I40�A x 2.6
2 x 1.20 = 30.3k
An external addition to R3 of 10k is required, and this value can be selected to accurately set the high level gain.
A low level trim resistor from CRECT to Vee of about 3M provides matching of the Bell low-level tracking curve, and the 2�F value of CREeT provides the proper attack and release times. A 16k resistor from the summing node to ground biases the output to 7Vrx;. _
VOLTAGE-CONTROLLED ATTENUATOR The variable gain cell in the NE570/571 may
be used as the heart of a high quality voltage-controlled amplifier (VCA). Figure 16 shows a typical circuit which uses an external op amp for better performance, and an exponential converter to get a control characteristic of-SdB/V. Trim networks are shown to null out distortion and DC shift, and to fine trim gain to OdB with OV of control voltage.
Op amp A2 and transistors 01 and 0 2 form the exponential converter generating an exponential gain control current, which is fed into the rectifier. A reference current of 150�A, (15Vand R20=100k), is attenuated a

factor of two (6dB) for every volt increase in the control voltage. Capacitor C6 slows down gain changes to a 20ms time constant (C6xR1) so that an abrupt change in the control voltage will produce a smooth
sounding gain change. R18 assures that for
large control voltages the circuit will go to full attenuation. The rectifier bias current would normally limit the gain reduction to about 70dB. R18 draws excess current out of the rectifier. After approximately 50dB of attenuation at a-6dB/V slope, the slope steepens and attenuation becomes much more rapid until the circuit totally shuts off at about 9V of control voltage. A1 should be a low noise high slew rate op amp. R1s and R14 establish approximately a OV bias atA1's output.
With a OV control voltage, R19 should be adjusted for OdB gain. At 1V(-6dB gain) R9 should be adjusted for minimum distortion with a large (+1OdBm) input signal. The output DC bias (A1output) should be measured at full attenuation (+1OV control voltage) and then Ra is adjusted to give the same value at OdB gain. Properly adjusted, the circuit will give typically less than 0.1 %
distortion at any gain with a DC output
voltage variation of only a few millivolts. The clipping level (140�A into Pin 3, 14) is �10V peak. A signal-to-noise ratio of 90dB can be obtained.
If several VCAs must track each other, a common exponential converter can be used. Transistors can simply be added in parallel with 0 2 to control the other channels. The transistors should be maintained at the same temperature for best tracking.

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Applications for compandors NE570/571/SA571

Application note
AN174

s1K

IN�T +

RO

100K RS
~

CONTROL VOLTAGE 0~1ov
FOR GANGING MULTIPLE CHANNELS

+15V

DC SHIFT

TRIM

100K

RS

220K R7

150K R10
3.SV

THO TRIM

100K
R9 220K R11

62K R13
l + 10).1.F C2

8,9 ----'\A"---+------1 r - - - -~--J--~ 3,14 I 20K
R2
112 NE5701571

2,15

10K

36K

R15

44MEG R18

100<1 R16

r1�F OUT C OOK

R17

AUTOMATIC LEVEL CONTROL
The NE570 can be used to make a very high performance ALC as shown in Figure 17. This circuit hook-up is very similar to the basic compressor shown in Figure 2 except that the rectifier input is tied to the input rather than the output. This makes gain inversely proportional to input level so that a 20d8 drop in input level will produce a 20d8 increase in gain. The output will remain fixed at a constant level. As shown, the circuit will maintain an output level of �1 dB for an input range of +14 to -43d8 at 1kHz. Additional external components will allow the output level to be adjusted. Some relevant design equations are:
= Output level Ri R2 18 ( -VVININ (avg) ) 2 R3 la= 140�A
Gain = __R~i_R~2'-1-8=- where
2 R3 VIN (avg)
~ = -1ct = I.II (for sine wave)
VIN (avg 2 �2

Figure 16. Voltage-Controlled Attenuator
If ALC action at very low input levels is not desired, the addition of resistor Rx will limit the maximum gain of !he circuit.
Ri +Rx .x Rz x IB Gain max = _,_i."'sv'-----
2 RJ
The time constant of the circuit is determined by the rectifier capacitor, CRECT� and an internal 1Ok resistor.
<=10k CRECT Response time can be made faster at the expense of distortion. Distortion can be approximated by the equation:
THD =( l�F ) (lkllz) x0.2% CRECT freq.
VARIABLE SLOPE COMPRESSOR-EXPANDOR
Compression and expansion ratios other than 2:1 can be achieved by the circuit shown in Figure 18. Rotation of the dual potentiometer causes the circuit hook-up to change from a basic compressor to a basic expandor. In the

center of rotation, the circuit is 1: 1, has neither compression nor expansion. The (input) output transfer characteristic is thus continuously variable from 2:1 compression, through 1:1 up to 1:2 expansion. If a fixed compression or expansion ratio is desired, proper selection of fixed resistors can be used instead of the potentiometer. The optional threshold resistor will make the compression or expansion ratio deviate towards 1:1 at low levels. A wide variety of (input) output characteristics can be created with this circuit, some of which are shown in Figure 18.
HI-Fl COMPANDOR
The NE570 can be used to construct a high performance compandor suitable for use with music. This type of system can be used for noise reduction in tape recorders, transmission systems, bucket brigade delay lines, and digital audio systems. The circuits to be described contain features which improve performance, but are not required for all applications.
A major problem with the simple NE570 compressor (Figure 2) is the limited op amp gain at high frequencies.

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Applications for compandors NE570/571/SA571

Application note
AN174

(1.16)

1 + CRECT

R220K >---'\NV-<.> (3,14)

For weak input signals, the compressor circuit operates at high gain and the 570 op amp simply runs out of loop gain. Another problem with the 570 op amp is its limited slew rate of about 0.6V/�s. This is a limitation of the expander, since the expander is more likely to produce large output signals than a compressor.

2�F

33K

33K

1�F +
(6,11)

R320K

(5,1210--------t>-----30pF
R4 30K
1.&V

Figure 20 is a circuit for a high fidelity compressor which uses an external op amp and has a high gain and wide bandwidth. An input compensation network is required for stability.
Anotherfeature of the circuit in Figure 20 is that the rectifier capacitor (C9) is not grounded, but is tied to the output of an op amp circuit. This circuit, built around an LM324, speeds up the compressor attack time at low signal levels. The response times of the simple expandorand compressor (Figures 1and 2) become longer at low signal levels. The time constant is not simply 10kxCRECT. but is really:

Figure 17. Automatic Level Control
DUAL 10K

V1N COMPRESSION
EXPANSION

( !Ok+ 2( 0IR.0E2cr6V)) x CRECT
When the rectifier input level drops from OdBm to -30dBm, the time constant increases from 10.7kxCRECT to 32.SkxCRECT� In systems where there is unity gain between the compressor and expander, this will cause no overall error. Gain or loss between the
compressor and expandorwill be a mistracking of low signal dynamics. The circuit with the LM324 will greatly reduce this problem for systems which cannot guarantee the unity gain.

R210K (2,15)

THRESHHOLD

1 MEG LOG

r(1.15)
+ CRECT

Rgure 1a. Variable SI- Compreeaor-Expandor

OUTPUT LEVEL 10dB/DI

INPUT LEVEL

10dBIDIV.

Figure 19. Typical Input-Output Tracking Curves of Variable Ratio
Compressor-Expander

Signetics RF Communications
Applications for compandors NE570/571 /SA571

Application note
AN174

When a compressor is operating at high gain, (small input signal), and is suddenly hit with a signal, itwill overload until it can reduce its gain. Overloaded, the output will attemptto swing rail to rail. This compressor is limited to approximately a 7Vp.p output swing by the brute force clamp diodes D3 and D4. The diodes cannot be placed in the feedback loop because their capacitance would limit high frequency gain. The purpose of limiting the output swing is to avoid overloading any succeeding circuit such as a tape recorder input.
The time it takes for the compressor to recover from overload is determined by the rectifier capacitor C9. A smaller capacitor will allow faster response to transients, but will produce more low frequency third harmonic distortion due to gain modulation. A value of 1�F seems to be a good compromise value and yields good subjective results. Of course, the expandor should have exactly the same value rectifier capacitor for proper transient response. Systems which have good low frequency amplitude and phase response can use compandors with smaller rectifier capacitors, since the third harmonic distortion which is generated by the compressor will be undistorted by the expandor.
Simple compandor systems are subject to a problem known as breathing. As the system is changing gain, the change in the background noise level can sometimes be heard.
The compressor in Figure 20 contains a high frequency pre-emphasis circuit (C2, R5 and C8, R14), which helps solve this problem. Matching de-emphasis on theexpandoris required. More complex designs could make the pre-emphasis variable and further reduce breathing.
The expandor to complement the compressor is shown in Figure 21 . Here an external op amp is used for high slew rate. Both the compressor and expandor have unity gain levels of OdB. Trim networks are shown for distortion (THD) and DC shift. The distortion trim should be done first, with an input of OdB at 1OkHz. The DC shift should be adjusted for minimum envelope bounce with tone bursts. When applied to consumer tape recorders, the subjective performance of this system is excellent.

+3.6V

COMPRESSOR

In

C2

.005

3.6V
R16 100K D.C. SHIFT TRIM

.-.,..,.,6l8'vK-...... +7.SV

R11

R9

R10

47K

47K

�

csi 1o�F

03 04
Figure 20. Hi-Fi Compressor With Pre-emphasis

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Applications for compandors NE570/571/SA571

Application note
AN174

R7 220K

D.C. SHIFT TRIM

r -112-NE-570- -

EXPANDOR S�F

1

IN0-+-~~�'--~~.._~14}---'\f\l\r-f

C1

RS

+7.5V
R11 6SK R12 20K

C7 0.005�F

1�F

Figure 21. HI-Fl Expandor With De-emphasis

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Slgnetlcs RF Communications
Compandorcookbook

Appllcatlon note
AN176

Compandors are versatile, low cost, dual-channel gain control devices for audio frequencies. They are used in tape decks, cordless telephones, and wireless microphones per!Orming noise reduction. Electronic organs, modems and mobile telephone equipment use compandors for signal level control.
So what is companding? Why do it at all? What happens when we do it? Compandor is the contraction of the two words compressor and expander. There is one basic reason to compress a signal before sending it through a telephone line or recording it on a cassette tape: to process that signal (music, speech, data) so that all parts of it are above the inherent noise floor of the transmission medium and yet not running into the max. dynamic range limits, causing clipping and distortion. The diagrams below demonstrate the idea; they are not totally correct because in the real world of electronics the 3kHz tone is riding on the 1kHz tone. They are shown separated for better explanation.
Figure 1 is the signal from the source. Figure 2 shows the noise always in the transmission medium. Figure 3 shows the max limits of the transmission medium and what happens when a signal larger than those limits is sent through it. Figure 4 is the result of compressing the signal (note that the larger signal would not be clipped when transmitted). The received/playback signal is processed (expanded) in exactly the same - only inverted - ratio as the input signal was compressed. The end result
BLOCK DIAGRAMS
NE570/571/SA571
CURRENT CONTROLI.ED
GAIN CELL

3V - - - - - - - - - 2V 1Y

Rgure 1. Original Signal Input
Figure 2. Wide-Band Noise Floor of Transmission Line
3V 2V 1Y
-1V -2Y
MAXDYNAMC RANGE &V PK-PK
Figure a.

-1V
-2V
Figure 4. Signal After Compression
is a clean, undistorted signal with a high signal-to-noise ratio.
This document has been designed to give the reader a basic working knowledge of the Signetics Compandor family. The analyses of three primary applications will be accompanied by "recipes" describing how to select external components (for both proper operation and function modification). Schematic and artwork for an application board are also provided. For comprehensive technical information consult the Compandor Product Guide or the Linear Data Manual.
The basic blocks in a compandor are the current-controlled variable gain cell (t.G), voltage-to-current converter (rectifier), and operational amplifier. Each Signetics compandor package has two identical, independent channels with the following block diagrams (notice that the 570/71 is different from the 572).
The operatio~al amplifier is the main signal path and output drive.

OUTPUT

INPUT

ATTACK TIME
CAPACITOR

NE572
CURRENT CONTROLLED
GAIN CELL

0 OUTPUT
RELEASE TIME CAPACITOR

ATTACK/RELEASE TIME CONSTANT
CAPACITOR

INPUT

VOLTAGE TO
CURRENT

SEE NOTES AT END

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Application note
AN176

CURRENT CONTROLLED
GAIN CELL
VOLTAGE TO CURRENT CONVERTER

Your

The full-wave averaging rectifier measures the AC amplitude of a signal and develops a control current for the variable gain cell.
The variable gain cell uses the rectifier control current to provide variable gain control for the operational amplifier gain block.
The compandor can function as a Compressor, Expandor, and Automatic Level Controller or as a complete compressor/expandor system as described in the following:
1) The COMPRESSOR function processes uncontrolled input signals into controlled output signals. The purpose of this is to avoid distortion caused by a narrow dynamic range medium, such as telephone lines, RF and satellite transmissions, and magnetic tape. The Compressor can also limit the level of a signal.
2) The EXPANDOR function allows a user to increase the dynamic range of an incoming compressed signal such as radio broadcasts.
3) The compressor/expandor system allows a user to retain dynamic range and reduce the effects of noise introduced by the transmission medium.
4) The AUTOMATIC LEVEL CONTROL (ALC) function (like the familiar automatic gain control) adjusts its gain proportionally with the input amplitude. This ALC circuit therefore transforms a widely varying input signal into a fixed amplitude output signal without clipping and distortion.

Figure 5. Basic Compressor
HOW TO DESIGN COMPANDOR CIRCUITS
The rest of the cookbook will provide you with basic compressor, expandor, and automatic level control application information. A NE570/571 has been used in all of the circuits. If high-fidelity audio or separately programmable attack and decay time are needed, the NE572 with a low noise op amp should be used.
The compressor (see Figure 5) utilizes all basic building blocks of the compandor. In this configuration, the variable gain cell is placed in the feedback loop of the standard inverting amplifier circuit. The gain equation is Av=-RF/RiN� As shown above, the variable gain cell acts as a variable feedback resistor (RF) (See Figure 5).
As the input signal increases above the crossover level of OdB, the variable resistor decreases in value. This causes the gain to decrease, thus limiting the output amplitude.
Below the crossover level of OdB, an increase in input signal causes the variable resistor to increase in value, thereby causing the output signal's amplitude to increase.
In the compressor configuration, the rectifier is connected to the output.
The complete equation for the compressor gain is:

l
Gain comp. = [ Ri Rz ls ] 2 2 R, VIN (avg)

where:

R1 = 10k
R2 = 20k R3 = 20k Is= 140�A

V1N(avg)=0.9(V1N(RMSJ)

COMPRESSOR RECIPE
1) DC bias the output half way between the supply and ground to get maximum headroom. The circuit in Figure 6 is designed around a system supply of 6V, thus the output DC level should be 3V.

Vour oc=(1+(2Roc/R.i)) VREF
where: Ri=30k VREF=1.8V Roe is external
manipul(ati(n:::)equat)ion~:he result is.

Rvc=

- - -1 -

VREF

2

Note that the C(DC) should be large enough to totally short out any AC in this feedback loop.

2) Analyze the OUTPUT signal's anticipated amplitude.

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AN176

a) if larger than 2.BV peak, R2 needs to be increased. (see INGREDIENTS section)
b) if larger than 3.0V peak, R1will also need to be increased.
By limiting the peak input currents we avoid signal distortion.
3) The input and output coupling caps need to be large enough not to attenuate any desired frequencies (Xc=1/(6.2Bxf)). 4) The CRECT should be 1�F to 2�F for initial setup. This directly affects Attack and Release times. 5) An input buffer may be necessary if the source's output impedance needs matching. 6) Pre-emphasis may be used to reduce noisepumping, breathing, etc., if present. See the NE570/571 data sheet for specific details.

7) Distortion (THO) trim pins are available ifthe already low distortion needs to be further reduced. Refer to data sheet for trimming network. Note thatif not used, the THO trim pins should have 200pF caps to ground.

B) At very low input signal levels, the rectifier's errors become significant and can be reduced with the Low Level Mistracking network. (This technique prevents infinite compression at low input levels.)

The EXPAN DOR utilizes all the basic building blocks of the compandor (see Figure 7). In this configuration the variable gain cell is placed in the inverting input lead of the operational amplifier and acts as a variable input resistance, RiN� The basic gain equation for operational amplifiers in the standard inverting feedback loop is Av=-RF/R1N�

As the input amplitude increases above the crossover level of OdBM, this variable resistor decreases in value, causing the gain to increase, thus forcing the output amplitude to increase (refer to Figure 10).
Below the crossover level, an increase in input amplitude causes the variable resistor to increase in value, thus forcing the output amplitude to decrease.

The complete equation for the expandor gain is:

Gain expandof=(2R3V1N(avg))/R1R2l0

where:

R1 = 10k R2 = 20k
R3 = 20k
10 = 140�A

V1N(avg)=0.9 (V1N(RMS))
In the expander configuration the rectifier is connected to the input.

Roe

Roe

5,12

:;;);;. Coe

CJN
VJN o--J - t---'VIR3A ----..-----! 6,11 R4

7,10

Vour

=
Figure 6. Basic Compressor

EXPANDOR RECIPE
1) DC bias the output halfway between the supply and ground to get maximum headroom. The circuit in Figure B is designed around a system supply of 6V so the output DC level should be 3V.
Vour oc=(1 +R:i/R4)VREF
where: R3 = 20k
R4 =30k
VREF = 1.BV
Note that when using a supply voltage higher than 6V the DC output level should be adjusted. To increase the DC output level, it
is recommended that A. be decreased by
adding parallel resistance to it. (Changing R3 would also affect the expandor"s AC gain and thus cause a mismatch in a companding system.)
2) Analyze the input signal's anticipated amplitude:
a) if larger than 2.BV peak, R2 needs to be increased. (see INGREDIENTS section)
b) if larger than 3.0V peak, R1will also need to be increased. (see INGREDIENTS)
By limiting the peak input currents we avoid signal distortion.
3) The input and output decoupling caps need to be large enough not to attenuate any desired frequencies.
4) The CRECT should be 1�F to 2�F for initial setup.

5) An input buffer may be necessary if the source's output impedance needs matching.
6) De-emphasis would be necessary if the complementary compressor circuit had been pre-emphasized (as in a tape deck application). See the Hi-Fi Expander application in the Linear Data Manual.
7) Distortion (THO) trim pins are available if the already low distortion needs to be further reduced. See Linear Data Manual for trimming network. Note that if not used, the THO trim pins should have 200pF caps to ground.
B) At very low input signal levels, the rectifier's errors become significant and can be reduced with the Low Level Mistracking network (see Linear Data Manual). (This technique prevents infinite expansion at low input levels.)
In the ALC configuration, (Figure 9), the variable gain cell is placed in the feedback loop of the operational amplifier (as in the Compressor) and the rectifier is connected to the input.
As the input amplitude increases above the crossover point, the overall system gain decreases proportionally, holding the output amplitude constant.
As the input amplitude decreases below the crossover point, the overall system gain increases proportionally, holding the output amplitude at the same constant level.

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Application note
AN176

1~AA~..----..-.-.... V1N
>-----e---civouT �

CURRENT

R2

CONTROLLED

GAIN CELL

Your

-=

' ::~ vg~~~i~~o

CONVERTER

~- rCIN1

R2

3,14 20K

V1NL;l~10K

Figure 7. Basic Expander

R3

(6,11)

20K

5,12

R4 ".IJ~F

Figure 8. Basic Expander

l�F

(2,15) R1

,-----11--�----~>--'l/\/l~----l

(1,16)

10K

-=

AG

1 R2 20K (3,14)

2�F

39K

33K

~10+�F Roe

(S,12�n------11------� 30pF

l�F

R320K

V1N o------<f-�---o--VV\r-~------1

(6,11) R4

30K

1.BV

(7,10) Your

Figure 9. Automatic Level Control

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186

The complete gain equation for the ALC is:

Gain = R1 Ri ls 2 R, VIN (avg)

= Output Level

Ri Ri ls 2 R,

( VIN ) VIN (avg)

= = where~ VIN (avg)

_2'.f!i._.

1.11 ifor sine wave)

Note that for very low input levels, ALC may

not be desired and to limit the maximum gain,

resistor Rx has been added. The modified

gain equation is:

= .

(R1+Rx)�R2�ls

Gain max. -'--"--=--"-"'-

2 R,

Rx;::; ((desired max gain)x26k)-10k

INGREDIENTS
[Application guidelines for internal and external components (and input/output constraints) needed to tailor (cook) each of the three entrees (applications) to your taste.[
R1 ( 1OkQ) limits input current to the rectifier. This current should not exceed an AC peak value of �300�A. An external resistor may be placed in series with R1 if the input voltage to the rectifier will exceed �3.0V peak (i.e., 1Okx300�A=3.0V).
R2 (20kQ) limits input current to the variable gain cell. This current should not exceed an AC peak value of �140�A. Again, an external resistor has to be placed in series with R2 if the input voltage to the variable gain cell exceeds �2.SV (i.e., 20kx140�A).
R3 (20kQ) acts in conjunction with ~ as the
feedback resistor (RF) (expander configuration) in the equation. (R3's value can be either reduced or increased externally.) However, it is recommended that R4 be the

Signetics RF Communications
Compandor cookbook

Application note
AN176

one to change when adjusting the output DC level.
R.i (30kn) acts as the input resistor (R1N) in the standard non-inverting op amp circuit. (Its value can only be reduced.)
v Vour oc=( 1+(R:i/R.i)) REF
(for the Expander) VouT Dc=(1 +(2RDcifti))VREF
(for the Compandor, ALC)
[The purpose of these DC biasing equations is to allow the designer to set the output halfway between the supply rails for largest headroom (usually some positive voltage and ground).]
CDc acts as an AC shunt to ground to totally remove the DC biasing resistors from the AC gain equation.
CF caps are AC signal coupling caps.
CRECT acts as the rectifier's filter cap and directly affects the response time of the

circuit. There is a trade-off, though, between fast attack and decay times and distortion.
The time constant is: 10kxCRECT
The total harmonic distortion (THD) is approximated by:
THD;;;; (1�FiCRECT)(1kHz/freq.)x0.2%
NOTES: The NE572 differs from the 570'571 In that: 1. There Is no internal op amp. 2. The attack and release times are programmed sepa�
rately.
SYSTEM LEVELS OF A COMPLETE COMPANDING SYSTEM
Figure 10 demonstrates the compressing and expanding functions:
Point A represents a wide dynamic range signal with a maximum amplitude of+ 1GdB and minimum amplitude of -SOdB.

Point B represents the compressor output showing a 2:1 reduction in dynamic range (--40dB is increased to -20dB, for example). Point B can also be seen as the dynamic range of a transmission medium. Transmission noise is present at the --SOdB level from Point B to Point C.
Point C represents the input signal to the expander.
Point D represents the output of the expander. The signal transformation from Point C to D represents a 1:2 expansion.
APPLICATION BOARD
Shown below is the schematic (Figure 11) for Signetics' NE570/571 evaluation/demo board. This board provides one channel of Expansion and one channel of Compression (which can be switched to Automatic Level Control).

+16dB OdB

NE570/571/SA571 SYSTEM LEVEL

[]"2 VRMS COMPRESSION
IN

iINPUT TO AG AND RECT

rf

REL LEVEL ABS LEVEL

COMPRESSION

DB

out

dBM

(COMPRESSOR (EXPANDOR

--------- --------- --------- ____}___., OUT) B
4.9V 3.1V

C IN)

D +16.0 +12.0

+16 +12

775mV

0.0

-20dB

-20

-20

-40dB

7.75rnV

-40

-40

-80d8

775�V

-60

-60

-OOdB

7.~S�V

-80

-80

Figure 10. System Levels of a Complete Companding System

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+ 2.2�F
SHOWN AS COMPRESSOR (OPTIONAL DE-EMPHASIS) ALC (SPOT SWITCH)

COMPRESSOR/ALC INPUT

10�F EXPANDOR INPUT

8
1_
200pFI

9

1_

13 0--,----

4oL I 200pF

:!L 1D�F

Figure 11-

Application note
AN176

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Slgnetlcs RF Communlcstlons
Programmable analog compandor

Product specification
NE/SA572

DESCRIPTION
The NE572 is a dual-channel, high-performance gain control circuit in which either channel may be used for dynamic range compression or expansion. Each channel has a full-wave rectifier to detect the average value of input signal, a linearized, temperature-compensated variable gain cell (&G) and a dynamic time constant buffer. The buffer permits independent control of dynamic attack and recovery time with minimum external components and improved low frequency gain control ripple distortion over previous compandors.
The NE572 is intended for noise reduction in high-performance audio systems. It can also be used in a wide range of communication systems and video recording applications.

FEATURES
� Independent control of attack and recovery time
� Improved low frequency gain control ripple � Complementary gain compression and
expansion with external op amp � Wide dynamic range-greater than 11 OdB � Temperature-compensated gain control
� Low distortion gain cell
�Low noise-6�V typical
� Wide supply voltage range-6V-22V
� System level adjustable with external components

APPLICATIONS
� Dynamic noise reduction system

� Voltage control amplifier

� Stereo expander

� Automatic level control

� High-level limiter

� Low-level noise gate

� State variable filter

PIN CONFIGURATION
01, N, F Packages
TRACKTRIMA 1 RECOY. CAP A 2
RECT. INA 3 TTACKCAPA 4
&GOUTA 5 THDTRIMA 6
&GINA 7
NOTE: 1. D package released In large SD (SOL) package
only.

ORDERING INFORMATION
DESCRIPTION 16-Pin Plastic SO 16-Pin Plastic DIP 16-Pin Plastic SO 16-Pin Cerdip 16-Pin Plastic DIP

TEMPERATURE RANGE Oto +70�C Oto +70�C
-40 to+85�C -40 to +85�C -40to+85�C

ORDER CODE NE572D NE572N SA572D SA572F SA572N

ABSOLUTE MAXIMUM RATINGS

SYMBOL

PARAMETER

Vee

Supply voltage

TA

Operating temperature range

NE572

SA572

Po

Power dissipation

RATING 22
Oto +70 -40 to +85
500

UNIT Voe
�c
mW

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Signetics RF Communications
Programmable analog compandor

Product specification
NE/SA572

BLOCK DIAGRAM

A1
(7,9)
(6,10)

~--------------1-(5,11)

(16)

(8)

(4,12)

(2,14)

DC ELECTRICAL CHARACTERISTICS
Standard test conditions (unless otherwise noted) Vcc=15V, TA=25�C; Expander mode (see Test Circuit). Input signals at unity gain level (OdB) = 100mVRMSat 1kHz; V1 = V2; R2=3.3kn; R3= 17.3kQ.

SYMBOL

PARAMETER

TEST CONDITIONS

NE572

SA572

UNIT

Min Typ Max Min Typ Max

Vee

Supply voltage

6

22

6

22

Voe

Ice

Supply current

No signal

6

6.3

mA

VA THO

Internal voltage reference
Total harmonic distortion (untrimmed)

1kHz CA=1.0�F

2.3 2.5 2.7 2.3 2.5 2.7

Voe

0.2 1.0

0.2 1.0

%

THO

Total harmonic distortion (trimmed)

1kHz CR=10�F

0.05

0.05

%

THO

Total harmonic distortion (trimmed)

100Hz

0.25

0.25

%

No signal output noise

Input to V1 and V2 grounded (20--20kHz)

6

25

6

25

�V

DC level shift (untrimmed)

Input change from no signal to 100mVRMS

�20 �50

�20 �50

mV

Unity gain level

-1

0

+1 -1.5 0 +1.5

dB

Large-signal distortion

V1=V2=400mV

0.7 3.0

0.7

3

%

Tracking error (measured

relative to value at unity

Rectifier input

gain)=

V2=+6dB V1=0dB

�0.2

�0.2

[Vo-Vo (unity gain)]dB

V2=--30dB V1=0dB

�0.5 -1.5

�0.5 -2.5

dB

-V2dB

+0.8

+1.6

200mVRMS into channel A, measured

Channel crosstalk

output on channel B

60

60

dB

PSRR

Power supply rejection ratio

120Hz

70

70

dB

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Product specification
NE/SA572

TEST CIRCUIT

2.2�F
V1 o--1

(7,9) 6.8k

6G

sn
1 =10�F

(2,14)

(4,12)
1

BUFFER

2.2�F
V2 o---j

3.3k

(3,13)

R2 1%

RECTIAER

(1,15) (16)

+15V

I .1�F

r+ 22�.F

AUDIO SIGNAL PROCESSING IC COMBINES VCA AND FAST ATTACK/SLOW RECOVERY LEVEL SENSOR
In high-performance audio gain control applications, it is desirable to independently control the attack and recovery time of the gain control signal. This is true, for example, in compandor applications for noise reduction. In high end systems the input signal is usually split into two or more frequency bands to optimize the dynamic behavior for each band. This reduces low frequency distortion due to control signal ripple, phase distortion, high frequency channel overload and noise modulation. Because of the expense in hardware, multiple band signal processing up to now was limited to professional audio applications.
With the introduction of the Signetics NE572 this high-performance noise reduction concept becomes feasible for consumer hi Ii applications. The NE572 is a dual channel gain control IC. Each channel has a linearized, temperature-compensated gain cell and an improved level sensor. In conjunction with an external low noise op amp for current-to-voltage conversion, the VCA features low distortion, low noise and wide dynamic range.
The novel level sensor which provides gain control current for the VCA gives lower gain control ripple and independent control of fast

attack, slow recovery dynamic response. An attack capacitor CA with an internal 1Ok resistor RA defines the attack time tA. The recovery time tR of a tone burst is defined by a recovery capacitor CR and an internal 1Ok resistor RR. Typical attack time of 4ms for the high-frequency spectrum and 40ms for the low frequency band can be obtained with 0.1�F and 1.0�F attack capacitors, respectively. Recovery time of 200ms can be obtained with a 4.7�F recovery capacitor for a 100Hz signal, the third harmonic distortion is improved by more than 1OdB over the simple RC ripple filter with a single 1.0�F attack and recovery capacitor, while the attack time remains the same.
The NE572 is assembled in a standard 16-pin dual in-line plastic package and in oversized SOL package. It operates over a wide supply range from 6V to 22V. Supply current is less than 6mA. The NE572 is designed for consumer application over a temperature
range 0-70 The SA572 is intended for applications from -40�C to +85'C.
NE572 BASIC APPLICATIONS
Description
The NE572 consists of two linearized, temperature-compensated gain cells (AG), each with a full-wave rectifier and a buffer amplifier as shown in the block diagram. The two channels share a 2.SV common bias reference derived from the power supply but

otherwise operate independently. Because of inherent low distortion, low noise and the capability to linearize large signals, a wide dynamic range can be obtained. The buffer amplifiers are provided to permit control of attack time and recovery time independent of each other. Partitioned as shown in the block diagram, the IC allows ilexibility in the design of system levels that optimize DC shift, ripple distortion, tracking accuracy and noise floor for a wide range of application requirements.
Gain Cell
Figure 1 shows the circuit configuration of the
gain cell. Bases of the differential pairs 0 1-02 and 0 3-04 are both tied to the output and
inputs of OPA A1. The negative feedback
through 0 1 holds the VaE of 0 1-02 and the VaE of 0 3-04 equal. The following
relationship can be derived from the transistor model equation in the forward active region.
A VBE0304 = AeEa1 Q2
(VaE = Vr lrN IC/IS)

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Product specification
NE/SA572

V+

where hN = RViN;
R1 =6.Bkn 11=140�A 12 = 280�A
/1 /2- Vr/n ( ~:IN)- Vrln ( /~S- fiN) (2)

where l1N = RViN;

lo

R1 =6.Bkn 11=140�A 12 = 280�A

10 is the differential output current of the gain cell and la is the gain control current of the gain cell.
If all transistors 0 1through 0 4 are of the same size, equation (2) can be simplified to:

Io=~� /JN� Io _..!_(h-2/i) �Io

(3)

fz

fz

The first term of Equation 3 shows the multiplier relationship of a linearized two quadrant transconductance amplifier. The second term is the gain control feedthrough due to the mismatch of devices. In the design, this has been minimized by large matched devices and careful layout. Offset voltage is caused by the device mismatch and it leads to even harmonic distortion. The
offset v~31n be !!imm~.Jl.Ul~,,teediOQ
a � J �Qll!2!t'.lYJJ!:ijnJ;.2.5JJA.ill.t!...lbll-TMD !!!m..Rin.
The residual distortion is third harmonic distortion and is caused by gain control ripple. In a compandor system, available control of. fast attack and slow recovery improve ripple' distortion significantly. At the unity gain level of 1OOmV, the gain cell gives THD (total harmonic distortion) of 0.17% typ. Output noise with no input signals is only 6�V in theaudio spectrum (10Hz-20kHz). The output current lo must feed the virtual ground input of an operational amplifier with a resistor from output to inverting input. The- non-inverting input of the operational amplifier has to be biased at VREF if the output current 10 is DC coupled.

THO TRIM

I

YJN Figure 1. Basic Gain Cell Schematic

Rectifier
The rectifier is a full-wave design as shown in Figure 2. The input voltage is converted to
current through the input resistor R2 and turns on eithe-r 0 5 or Os depending on the signal polarity. Deadband of the voltage to current converter is reduced by the loop gain of the- gain block A2. If AC coupling is used, the rectifier error come-s only from input bias current of gain block A2. The input bias current is typically about 70nA. Frequency response of the gain block A2 also causes sooond-order error at high frequency. The collector current of Os is mirrored and summed at the collootor of 0 5 to form the full wave rootified output current IR. The rectifier transfer function is

The internal bias scheme limits the maximum output current IR to be around 300�A. Within a �1 dB error band the input range of the rootifier is about 52dB.

/R = ViN - VREF

(4)

R2

If V1N is AC-coupled, then the equation will be reduced to:

October 7, 1987

Signetics RF Communications
Programmable analog compandor

Product specification
NE/SA572

V+

r------ ---,

I

I

I

R2

I

I I

~N

I I

I

I

I

I

L----------..J

07 06

Figure 2. Slmpllfled Rectifier Schematic

Buffer Amplifier
In audio systems, it is desirable to have fast attack time and slow recovery time for a tone burst input. The fast attack time reduces transient channel overload but also causes low-frequency ripple distortion. The low-frequency ripple distortion can be improved with the slow recovery time. If different attack times are implemented in corresponding frequency spectrums in a split band audio system, high quality performance can be achieved. The buffer amplifier is designed to make this feature available with minimum external components. Referring to Figure 3, the rectifier output current is mirrored into the input and output of the unipolar buffer amplifier A3 through 0 8, 0 9 and 0 10. Diodes D11 and D12 improve tracking accuracy and provide common-mode bias for A3. For a positive-going input signal, the buffer amplifier acts like a voltage-follower. Therefore, the output impedance of A3 makes the contribution of capacitor CR to attack time insignificant. Neglecting diode impedance, the gain Ga(t) for il.G can be expressed as follows:
_,
Ga(t) = (GaINr - GaFNL e<A + GaFNL

GalNT=lnitial Gain
GaFNL=Final Gain
tA=RA � CA=10k �CA
where tA is the attack time constant and RA is a 10k internal resistor. Diode D15 opens the feedback loop of A3 for a nega~ve-going signal if the value of capacitor CR is larger than capacitor CA. The recovery time depends only on CR � RR. If the diode impedance is assumed negligible, the dynamic gain GR (t) for il.G is expressed as follows.
-t
GR{t) = (GRINT - GRFNL e'ifi + GRFNL

013

GR(t)=(GR 1Nr-GR FNLl e +GR FNL

iR=RR � CR=10k �CR

where iR is the recovery time constant and

X2

018

RR is a 1Ok internal resistor. The gain control

current is mirrored to the gain cell through

0 14. The low level gain errors due to input
b(~s. c"Urre51'�tA~..ai\CJA3:'.l<f!9'.ll,~}{t;;)med
J\ lhrao~l"i'!he tracking trim pinin.t() 3 wJtb a.

current source of �3�A.

. .

TRACKING TRIM
Figure 3. Buffer Amplifier Schematic

Basic Expandor
Figure 4 shows an application of the circuit as a simple expander. The gain expression of the system is given by

Vour 2 R3 � V1N(A VG)

(5)

V1N

/1

R2�R1

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Signetics RF Communications
Programmable analog compandor

Product specification
NE/SA572

(l1=140�A)
Both the resistors R1 and R2 are tied to internal summing nodes. R1 is a 6.8k internal resistor. The maximum input current into the gain cell can be as large as 140�A. This corresponds to a voltage level of 140�A � 6.8k=952mV peak. The input peak current into the rectifier is limited to 300�A by the internal bias system. Note that the value of R1can be increased to accommodate higher input level. R2 and R3 are external resistors. It is easy to adjust the ratio of R:i!R2 for desirable system voltage and current levels. A small R2 results in higher gain control

current and smaller static and dynamic tracking error. However, an impedance buffer A1 may be necessary if the input is voltage drive with large source impedance.
The gain cell output current feeds the summing node of the external OPA A2. R3 and A2 convert the gain cell output current to the output voltage. In high-performance applications, A 2 has to be low-noise, high-speed and wide band so that the high-performance output of the gain cell will not be degraded. The non-inverting input of A2 can be biased at the low noise internal
reference Pin 6 or 10. Resistor R.i is used to

bias up the output DC level of A2 for maximum swing. The output DC level of A2 is given by
Vooc = VRE{ +~)-Ve~ (6)
V8 can be tied to a regulated power supply for a dual supply system and be grounded for a single supply system. CA sets the attack time constant and CR sets the recovery time
constant. �scoL

17.3k

C1N1
V1N o---j f----<>--l
2.2�F
RS 100k

Your

(8)

(16

+Vee

Figure 4. Basic Expandor Schematic

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Signetics RF Communications
Programmable analog compandor

Product specification
NE/SA572

Basic Compressor

Figure 5 shows the hook-up of the circuit as a

compressor. The IC is put in the feedback

loop of the OPA A1. The system gain

expression is as follows:

1

Vour ( /1

~�R1 ) 2

(7)

2 . ViN =

R3 � V1N(AVG)

C2 .1�F
V1N o---C-1jNt1----'Vl,..,.___ _ _--1

CDC I10�F

RDC2 9.1k

01 02

Roc1. Ro02. and CDC form a DC feedback for A1. The output DC level of A1is given by

2.2�F 1?3k

Your

Vooc ( = VREF 1 + R001 ~+ RDC2) (8)

C1

-Vs� (Roe;~ RoC2)

The zener diodes D1 and D2 are used for channel overload protection.
Basic Compandor System
The above basic compressor and expandor can be applied to systems such as tape/disc noise reduction, digital audio, bucket brigade delay lines. Additional system design techniques such as bandlimiting, band , splitting, pre-emphasis, de-emphasis and equalization are easy to incorporate. The IC is a versatile functional block to achiev.e a high performance audio system. Figure 6 shows the system level diagram for. reference.
':' I
'� \ .( \ (,

CiN3
2.2�F

CR CA 10�F 1�F

(3,13)

(8)
Vee <18l +p'
Figure 5. Basic Compressor Schematic

j\
I I

/\./ j\,,

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Signetics RF Communications
Programmable analog compandor

Product specification
NE/SA572

VRMS

[ Jt
COMPRESSION IN

3.0V

547.&MV 400MV
100MV

10MV

1MV 100�V 10�V

INPUT TO AG AND RECT
i

[ r

Ra LEVEL

EXPANDOR OUT

ABS LEVEL
dBll

+29.64 +14.77 +12.0

+11.76
--6.76

o.o

-17.76

-20

-47.78

-40

-57.78

-80

-77.78

Figure 6. NE572 System Level

-80

-'17.78

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196

Signetlcs RF Communications
Automatic level control using the NE572

Application note
AN175

NE572 AUTOMATIC LEVEL CONTROL
3.3k
Rx CATATPACK. - - - - - - - 1
1�F CA I

RECOVERY
t - = - - - - - - , CAP

100k
R.i

17.3k V1N
2.2~

TO THO

TRIM PIN OF572

1k

PINS

9.1k

9.1.k

+ I 2.2�F

I1o�F V+
1 VouT DC
V-

+ f--ovouT 2.2�F

RDC2) v.ODC

=

.,
VREF

(1

+

Roc1

R+,i

(Ri OUTPUT LEVEL=

R:l. /s)(~)

2Rs

VtN(a"!I)

Gain= R1 R:l. ls 2R:i VtN (avg)

ATTACK TIME= (10k) CA

RECOVERY TIME= (10k) CR

TO LIMIT THE GAIN AT VERY LOW INPUT LEVELS, ADD Rx:

R1+Rx

= """'2]17""xR2xls

GAIN MAX.

2R3

NOTE: Pin nunt>ers are for side A of the NE572.

WHERE: R.i= 100k
= Roc1 = Roc2 9.1k
VREF = 2.5V
WHERE: R1 = 6.Bk (Internal) R2= 3.3k Rs= 17.3k le= 140�A
~=...!!..._=1.11
212 VtN(a"!I)
(FOR SINE WAVES)

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Signetlcs RF Communications
Low voltage compandor

.Product specification
NE/SA575

DESCRIPTION
The NE/SA575 is a precision dual gain control circuit designed for low voltage applications. The NE575's channel 1 is an expander, while channel 2 can be configured either for expander, compressor, or automatic level controller (ALC) application.

FEATURES
�Operating voltage range from 3V to 7V
�Reference voltage of 100mVRMS = OdB
�One dedicated summing op amp per channel and two extra uncommitted op amps
�soon drive capability
�Single or split supply operation
�Wide input/output swing capability

PIN CONFIGURATION
0 1 and N Packages

APPLICATIONS
�Portable communications �Cellular radio �Cordless telephone �Consumer audio �Portable broadcast mixers �Wireless microphones �Modems �Electric organs �Hearing aids

NOTE: 1. Available In large SOL package only.

ORDERING INFORMATION

DESCRIPTION

TEMPERATURE RANGE

20-Pin Plastic DIP

0 to +70�C

20-Pin Plastic SOL

0 to +70'C

20-Pin Plastic DIP

-40 to +85�C

20-Pin Plastic SOL

-40 to +85'C

ORDER CODE NE575N NE575D SA575N SA575D

ABSOLUTE MAXIMUM RATINGS

SYMBOL

PARAMETER

Vee TA Tsrn 8JA

Single supply voltage

Operating ambient temperature range

Storage temperature range

Thermal impedance

DIP

SOL

RATING

NE575

SA575

8

8

-40 to +85 -40to +85

-65 to +150 -65 to +150

68

68

112

112

UNITS
v
'C 'C 'C/W 'C/W

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Signetics RF Communications
Low voltage compandor

Product specification
NE/SA575

BLOCK DIAGRAM and TEST CIRCUIT

Vou:iT~C3

R5 100k

10""

"=�GND

0.1�F

]_
GND

VouT
R9 100k
-= GND

VREF

RB 30k

R7

Ica

1�F

-=GND

CD13761S

DC ELECTRICAL CHARACTERISTICS

Typical values are at TA= 25�C. Minimum and Maximum values are for the full operating temperature range: 0 to 70�C for NE575, -40 to

+85�C for SA575. Vee = 5V, unless otherwise stated. Both channels are tested in the Expander mode (see Test Circuit)

LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

NE575

SA575

UNITS

MIN

TVP MAX MIN

TVP MAX

For compandor, Including summing amplifier Vee Supply voltage1

3

5

7

3

5

7

v

Ice VREF

Supply current Reference voltage2

No signal Vcc=5V

3

4.2

5.5

3

4.2

5.5

mA

2.4

2.5

2.6

2.4

2.5

2.6

v

RL Summing amp output load

10

10

kn

THO ENo

Total harmonic distortion Output voltage noise

1kHz, OdB BW = 3.5kHz
BW = 20kHz, Rs = on

0.12

1.0

6

20

0.12

1.5

%

6

30

�V

OdB Unity gain level

1kHz

-1.0

1.0

-1.5

1.5

dB

Vos Output voltage offset

No signal

-100

100

-150

150 mV

Output DC shift

No signal to OdB

-50

50

-100

100 mV

Gain cell input= OdB,

1kHz Rectifier input= 6dB,

-0.5

1kHz

0.5

-1.0

1.0

dB

Tracking error relative to OdB Gain cell input = OdB,

1kHz Rectifier input= -30dB,

-0.5

1kHz

0.5

-1.0

1.0

dB

Crosstalk

1kHz, OdB, CReF = 220�F

-80

-65

-80

-65

dB

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Low voltage compandor

Product specification
NE/SA575

DC ELECTRICAL CHARACTERISTICS (cont.)

LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

NE575

SA575

UNITS

MIN

TYP MAX MIN

TYP MAX

For operational amplifier

Vo Output swing

RL = 1011.Q

Vec;-0.4 Vee-0.2

Vcc-0.4 Vcc-0.2

v

I'

RL Output load

1kHz

600

600

n

CMR Input common-mode range

0

Vee

0

Vee

v

CMRR Common-mode rejection ratio

60

BO

60

BO

dB

la

Input bias current

V1N = O.SV to 4.SV

-0.S

o.s

-1

1

�A

Vos Input offset voltage

3

3

mV

AvoL SR

Open-loop gain Slew rate

RL = 10kll

BO

Unity gain

1

80

dB

1

V/�s

GBW Bandwidth

Unity gain

3

3

MHz

ENI Input voltage noise

BW=20kHz

2.S

2.S

�V

PSRR Power supply rejection ratio

1kHz,2SOmV

60

60

dB

NOTES: 1. Operation down to Vee. 2V is possible, but performance is significandy reduced. See curve in Figure 5.
2. Reference voltage, VREF. is typically at 1/2Vee.

FUNCTIONAL DESCRIPTION This section describes the basic subsystems and applications of the NE/SAS7S Compandor. More theory of operation on compandors can be found in AN174 and AN17S. The typical applications of the NES7S low voltage compandor in an Expander (1 :2), Compressor (2:1) and Automatic Level Control (ALC) function are explained. These three circuit configurations are shown in Figures 1, 2, 3 respectively.
The NES75 has two channels for a complete companding system. The left channel, A, can be configured as a 1:2 Expander while the right channel, B, can be configured as either a 2:1 Compressor, a 1:2 Expander or an ALC. Each channel consists of the basic companding building blocks of rectifier cell, variable gain cell, summing amplifier and VREF cell. In addition, the NES75 has two additional high performance uncommitted op amps which can be utilized for application such as filtering, pre-emphasis/de-emphasis or buffering.
Figure 4 shows the complete schematic for the applications demo board. Channel A is configured as an expander while channel B is configured so that it can be used either as a compressor or as an ALC circuit. The switch, S 1, toggles the circuit between compressor and ALC mode. Jumpers J1 and J2 can be used to either include the additional op amps for signal conditioning or exclude them from the signal path. Bread boarding space is provided for R1, R2, C1, C2, R10, R11, C10 and C11 so that the response can be tailored for each individual need. The components as

specified are suitable for the complete audio spectrum from 20Hz to 20kHz.
The most common configuration is as a unity gain non-inverting buffer where R1, C1, C2, R10, C10 and C11 are eliniinatedand R2and R11 are shorted. Capacitors C3, CS, CB, and C12 are for DC blocking, and R4 and RB provide termination (for the capacitors). In systems where the inputs and outputs are AC coupled, these capacitors and resistors can be eliminated. Capacitors C4 and C9 are for setting the attack and release time constant.
CS is for decoupling and stabilizing the voltage reference circuit. The value of CS should be such that it will offer a very low impedance to the lowest frequencies of interest. Too small a capacitor will allow supply ripple to modulate the audio path. The better filtered the power supply, the smaller this capacitor can be. RS and R12 provide DC reference voltage to the amplifiers of channel B. R6 and R7 provide a DC feedback path for the summing amp of channel B, while C7 is a short-circuit to ground for signals. C14 and C1S are for power supply decoupling. C14 can also be eliminated if the power supply is well regulated with very low noise and ripple. Figure B shows the PC board layout of the applications demo board.
DEMONSTRATED PERFORMANCE The applications demo board was built and tested for a frequency range of 20Hz to 20kHz with the component values as shown in Figure 4 and Vee= SV. In the expander

mode, the typical input dynamic range was from -34dB to +12dB where OdB is equal to 100mVRMS� The typical unity gain level measured at OdB@ 1kHz input was �Q.5dB and the typical tracking error was �0.1 dB for input range of -30to+10dB.
In the compressor mode, the typical input dynamic range was from -42dB to�1BdB with a tracking error +0.1 dB and the typical unity gain level was �0.SdB.
In the ALC mode, the typical input dynamic range was from -42dB to +BdB with typical output deviation of .�0.2dB about the nominal output of OdB. For input greater than +9dB in ALC configuration, the summing amplifier sometimes exhibits high frequency oscillations. There are several solutions to this problem. The first is to lower the values of R7 and RB to 20kll each.. the second is to add a curren.t limiting resistor in series with C13 at Pin 13. the third is to add a compensating capacitor of about 22 to 30pF between the input and output of summing amplifier (Pins 12 and 14). With any one of the above recommendations, the typical ALC mode input range increased to +18dB yielding a ciYnamic range of owr 60dB.
EXPANDOR The typical expander configuration is shown in Figure 1. The variable gain cell and the rectifier cell are in the signal input path. The VREF is always 1/2 Vcc to provide the maximum headroom without clipping. The OdB ref is 100mVRMS� The input is AC coupled through CS, and the output is AC coupled through C3. If in a system the inputs

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Signetics RF Communications
Low voltage compandor

Product specification
NE/SA575

and outputs are AC coupled, then C3, C5, R3 and R4 can be eliminated, thus requiring only one extemal component, C4. The variable gain cell and rectifier cell are DC coupled so any offset voltage between Pins 4 and 9 will cause small offset error current in the rectifier cell. This will affect the accuracy of the gain cell. This can be improved by using an extra capacitor from the input to Pin 4 and eliminating the DC connection between Pins 4 and 9.
The expandor gain expression and the attach and release time constant is given by Equation 1 and Equation 2, respectively.
Equation 1.
Expandor gain 4V1N(avg) 3.9kx 100�A
where V1N(avg) = 0.975V1N(RMS)
Equation 2. ~R =~A= 10k X CRECT = 10k X C4
COMPRESSOR
The typical compressor configuration is shown in Figure 2. In this mode, the rectifier cell and variable gain cell are in the feedback

path. R6 and R7 provide the DC feedback to the summing amplifier. The input is AC coupled through C12 and output is AC coupled through CB. In a system with inputs and outputs AC coupled, CB, C12, RB, and R9 could be eliminated and only R5, R6, R7, C7, and C13 would be required. If the extemal components R5, R6, R7 and C7 are eliminated, then the output of the summing amplifier will motor-boat in absence of signals or at extremely low signals. This is because there is no DC feedback path from the output to input. In the presence of an AC signal this phenomenon is not observed and the circuit will appear to function properly.
The compressor gain expression and the attack and release time constant is given by Equation 3 and Equation 4, respectively.
Equation 3.
~ J1/2
Compressor gam. = 3.9k x 100�A 4V1N(avg)
where V1N(avg) = 0.975V1N(RMS)
Equation 4.
~R =~A= 10k X CRECT = 10k X C4

AUTOMATIC LEVEL CONTROL
The typical Automatic Level Control circuit configuration is shown in Figure 3. It can be seen that it is quite similar to the compressor schematic except that the input to the rectifier cell is from the input path and not from the feedback path. The input is AC coupled through C12 and C13 and the output is AC coupled through CB. Once again, as in the previous cases, if the system input and output signals are already AC coupled, then C12, C13, CB, RB and R9could be eliminated. Concerning the compressor, removing RS, R6, R7 and C7 will cause motor-boating in absence of signals. CcoMP is necessary to stabilize the summing amplifier at higher input levels. This circuit provides an input dynamic range greater than 60dB with the output within �0.5dB typical. The necessary design expressions are given by Equation 5 and Equation 6, respectively.
Equation 5.

3.9kx 100�A ALCgain =
4V1N(avg)

Equation 6.

~R =~A= 10k X CRECT = 10k X C9

EXPIN cs o------j r--.-r+-'V'v"V--1

10�F

10k

' 4 Uk

8

IC4

2.2�F

Figure 1. Typical Expandor Confl uratlon

C3tR3 EXPOUT
10~ OOk
tc23250s

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201

Signetics RF Communications
Low voltage compandor

Product specification
NE/SA575

RS 20k

i-----------------------~

8

12

I

o----1 COMP IN

C12

13

>----<>----'\AA.--0--+--1

14 '

10�F

10k

11 10k

16 ' 3.9k
1S ____________ J
C9I 2.2�F

C13 4.7�F

Figure 2. Typical Compressor Configuration

R6

R7

9 C 8 i : R COMPOUT 10�F
k
TC23240S

ALCIN

RS

20k

CCOMP

VREF r---

22pF
----------------------. 12

10�F I

10k

'

14 ''
11 ' 10k

caTR9 ALcouT 10�
k

4.7�F :

10k

._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ J
C9I 2.2�F

Figure 3. Typical ALC Configuration

TC23260S

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Signetics RF Communications
Low voltage compandor

Vee .sv

Product specification
NE/SA575

R12

f-o 10k C12 COMP/

>---------+--+---i

~~c

10�.F

C10
I

OMP

If: cs o----j r - - - - - - - . 10�F

=

= GND

R9

C 8 ? 2 0 0CAOLMCP/

1 �F RS

OUT

100k

30k

I = C7 1�F

VREF
Figure 4. Signetics NE575 Low Voltage Expandor/Compressor/ALC Demo Board

.9

.8

iii .7
:s~ .6 .5 a: .4 a:
w .3 ~ .2

" ~

.1 0

!5-.1

-.2

4

5

6

7

8

SUPPLY VOLTAGE (VJ

Figure 5. Unity Gain Error vs Supply Voltage

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203

Signetic::s RF Communications
Low voltage compandor

Product specification
NE/SA575

TYPICAL PERFORMANCE CHARACTERISTICS

GENERAL DIAGRAM

9-l-~--IC---l--l-+-f-+t+t-~--IC---l--l-+-!-+t+t-~-"10d8'-=:-:l=N--l-++++Hf--~_...+---I
INPUT
4-+-~--1i---+--+-+-t-t-t-t-t-~--1i---+--+-+-t-t-t-t-t-~--1~-+--+-+-+++++-~--t~~'�;�"Hz)

10~F r4.7~
_I ..I
AG REC
SUM *'+
OUTPUT

2-+-~--1r---+--+-+-+-+t+1-~--1r---+--+-+-+-+t+t-~--l~+-+-+-+++++-~--1~;

OdBIN

Ycc=SY

~-1-~--1r---+--+-+-+-+t+1-~--1r---+--+-+-+-+t+t-~--lf--+-+-+-+++++-~--1~;
m~-1-~--1i---+--+-+-+-+t+1-~--1r---+--+-+-+-+t+1-~--1r---r-+-+-+++++-~--1~; ~ ...I w~-+-~--t~+-+-+-+++++-~--t~+-+-+-+++++-~--+~+-+-+-+++++-~--+~~
~
...I ~~-;-~-r----t--r-t-t-t-ttt-~-+--t-t--1--t-++t+-~-;---r-t-+++H+-~-t--t
�~o-+-~--t~+-+-+-+++++-~--t~+-+-+-+++++-~--+~+-+-+-+++++-~--+~~
-12-1-~--t~+-+-+-+-++tt-~--1~+-+-+-+-++++-~--t~+-+-+-+++++-~--t~~
-14-+-~--t~-+--+-+-+-tt++-~--t~-+--+-+-t-tt++-~--t~-+--+-+-+++++-~--t~~
-1e-1-~--t~+-+-+-+-++tt-~--1~+-+-+-+-++++-~--t~+-+-+-+++++-~--t~;

-40dBIN

10

11111

1000

111111111

30000

FREQUENCY (Hz)

Figure 6. Compressor Output Frequency Response

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Signetics RF Communications
Low voltage compandor

Product specification
NE/SA575

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

8
6 ,...__

LI

�

- 2
0

OdBIN

-2

iD -4
~

.w.J
>w -8
..J

I::I

-8

0..

I-

::I

0-10

-12

-14

-16

INPUT (20-20kHz)

GENERAL DIAGRAM

lef-1I REC IH AG 10�F

~UT SUM

Vcc=SV

-18 -20
-22 10

�10dBIN
~

I

I

100

1000

10000

30000

FREQUENCY (Hz)

Figure 7. NE575 Expander Output Frequency Response

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Signetics RF Communications
Low voltage compandor

Product specification
NE/SA575

SIGNETICS
15 NE575

~:G-NDnc

+SV

COMP IN

g 0 C1

C9

O EINXP

~1

R2

N

/'"\/'"\

0 J1

C2

E

C4 +

5

+c:::) C14 + C12
[filJ- c:::)

Ull)-

C10 C11 J2

o+ + c:::)
GND? f 3

7 ca c130

vv

5 o+ C+OMLJALC

EXP

OUT {]D

-c:iii} COMP

-{][J-U!}

c :G: )D- Q i l O U T

+ C7

Sa. Application Board Component Placement

May 30, 1989

� �
SB. Application Board Layout
206

Signetics RF Communications
Low voltage compandor

Product specification
NE/SA575

COMPRESSOR IN +10dB
100mV OdB
-10dB
~B
-30dB

~
/
~

+SdB

/

OdB

-SdB

-10dB

~

-15dB -OOdB -25dB

~

COMPRESSION

,
' EXPANSION

Figure 9. The Companding Function

EXPANDOR OUT +10d9 1oomV OdB -10dB -OOdB
-30dB
~B
-50dB

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Slgnetlcs RF Communications
Low voltage compandor in shrink small outline package

Product specification
NE/SA575SSOP

DESCRIPTION
The NE/SA575 is a precision dual gain control circuit designed for low voltage applications. The NE575's channel 1 is an expander, while channel 2 can be configured either for expander, compressor, or automatic level controller (ALC) application.

FEATURES � Operating voltage range from 3V to 7V
� Reference voltage of
100mVRMS = OdB
� One dedicated summing op amp per channel and two extra uncommitted rail-to-rail op amps
� soon drive capability
� Single or split supply operation
� Wide input/output swing capability � DTMF summing

PIN CONFIGURATION
SSOP Package

APPLICATIONS
� Portable communications � Cellular radio � Cordless telephone � Consumer audio � Portable broadcast mixers � Wireless microphones �Modems � Electric organs � Hearing aids

ORDERING INFORMATION

DESCRIPTION

TEMPERATURE RANGE

20-Pin Plastic SSOP

Oto +70�C

20-Pin Plastic SSOP

-40 to +85�C

ORDER CODE NE575DK SA575DK

ABSOLUTE MAXIMUM RATINGS

SYMBOL

PARAMETER

Vee TA Tsm 9JA

Single supply voltage

Operating ambient temperature range

Storage temperature range

Thermal impedance

SSOP

RATING

NE575

SA575

8

8

0 to +70 -40 to +85

---S5to+150 ---S5to+150

117

117

UNITS
v
oc oc oc/W

January 18, 1991

208

853-1531 01492

Signetics RF Communications
Low voltage compandor in shrink small outline package
BLOCK DIAGRAM and TEST CIRCUIT

VouT~

200

C3

RS 100k

1oi1F

=aND

=GND

Product specification
NE/SA575SSOP

C15

l =

GND

Your

- GND

R8 30k

Ica

1�F

-GND

AC/DC ELECTRICAL CHARACTERISTICS TA = 25�C; Vee = 5V, unless otherwise stated. Both channels are tested in the Expandor mode (see Test Circuit)
LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

NE575

MIN TYP MAX MIN

For compandor, lncludlng summing amplifier

Vee Supply voltage 1

3

5

7

3

Ice Supply current

No signal

3

4.2

5.5

3

VREF Reference voltage2

Vcc=5V

2.4

2.5

2.6

2.4

RL Summing amp output load THO Total harmonic distortion

10

10

1kHz, OdB BW =3.5kHz

0.12

1.0

ENo Output voltage noise

BW = 20kHz, Rs = OQ

6

20

OdB Unity gain level

1kHz

-1.0

1.0

-1.5

Vos Output voltage offset

No signal

-100

100 -150

Output DC shift

No sig11al to OdB

-50

50

-100

SA575 TYP
5 4.2 2.5
0.12 6

UNITS MAX

7

v

5.5

mA

2.6

v

kQ

1.5

%

30

�V

1.5

dB

150 mV

100 mV

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209

Signetics RF Communications
Low voltage compandor in shrink small outline package

Product specification
NE/SA575SSOP

AC/DC ELECTRICAL CHARACTERISTICS

SYMBOL

PARAMETER

TEST CONDITIONS

NE575

MIN

TYP

Gain cell input = OdB, 1kHz Rectifier input= 6dB, 1kHz

-0.5

Tracking error relative to OdB Gain cell input = OdB, 1kHz Rectifier input = -30dB, 1kHz

-0.5

Crosstalk

1kHz, OdB, CREF = 220�F

--80

For operational amplifier

Vo

Output swing

RL = 10kQ

Vcc-0.4 Vcc-0.2

RL

Output load

1kHz

600

CMR Input common-mode range

0

CMRR Common-mode rejection ratio

GO

80

Is Vos AvoL SR

Input bias current Input offset voltage Open-loop gain Slew rate

V1N = 0.5V to 4.5V
RL = 10kQ Unity gain

-0.5 3 80 1

GBW Bandwidth

Unity gain

3

ENI

Input voltage noise

BW = 20kHz

2.5

PSRR Power supply rejection ratio

1kHz, 2SOmV

GO

LIMITS

MAX 0.5

MIN -1.0

SA575 TYP

0.5

-1.0

~5

--80

Vcc-0.4 Vcc-0.2 600

Vee

0

GO

80

0.5

-1

3

80

1

3

2.5

GO

NOTES: 1. Operation down to Vee = 2V is possible, but performance is significantly reduced. See curve in Figure S. 2. Reference voltage, VREF. is typically at 1/2Vcc.

MAX 1.0 1.0
~5
Vee 1

UNITS
dB
dB dB
v
Q
v
dB
�A
mV dB V/�s MHz �V dB

FUNCTIONAL DESCRIPTION
This section describes the basic subsystems and applications of the NE/SA57S Compandor. More theory of operation on compandors can be found in AN174 and AN 17G. The typical applications of the NES7S low voltage compandor in an Expander (1 :2), Compressor (2:1) and Automatic Level Control (ALC) function are explained. These three circuit configurations are shown in Figures 1, 2, 3 respectively.
The NES7S has two channels for a complete companding system. The left channel, A, can be configured as a 1:2 Expander while the right channel, B, can be configured as either a 2:1 Compressor, a 1:2 Expander or an ALC. Each channel consists of the basic companding building blocks of rectifier cell, variable gain cell, summing amplifier and VREF cell. In addition, the NES7S has two additional high performance uncommitted op amps which can be utilized for application such as filtering, pre-emphasis/de-emphasis or buffering.
Figure 4 shows the complete schematic for the applications demo board. Channel A is configured as an expandorwhile channel Bis configured so that it can be used either as a compressor or as an ALC circuit. The switch,

S 1, toggles the circuit between compressor and ALC mode. Jumpers J1 and J2 can be used to either include the additional op amps for signal conditioning or exclude them from the signal path. Bread boarding space is provided for R1, R2, C1, C2, R10, R11, C10 and C11 so that the response can be tailored for each individual need. The components as specified are suitable for the complete audio spectrum from 20Hz to 20kHz.
The most common configuration is as a unity gain non-inverting buffer where R1, C1, C2, R10, C10 and C11 are eliminated and R2 and R 11 are shorted. Capacitors C3, CS, CB, and C12 are for DC blocking, and R4 and RB provide termination (for the capacitors). In systems where the inputs and outputs are AC coupled, these capacitors and resistors can be eliminated. Capacitors C4 and C9 are for setting the attack and release time constant.
CG is for decoupling and stabilizing the voltage reference circuit. The value of CG should be such that it will offer a very low impedance to the lowest frequencies of interest. Too small a capacitor will allow supply ripple to modulate the audio path. The better filtered the power supply, the smaller this capacitor can be. RS and R 12 provide DC reference voltage to the amplifiers of

channel B. RG and R7 provide a DC feedback path for the summing amp of channel B, while C7 is a short-circuit to ground for signals. C14 and C15 are for power supply decoupling. C 14 can also be eliminated if the power supply is well regulated with very low noise and ripple. Figure 8 shows the PC board layout of the applications demo board.
DEMONSTRATED PERFORMANCE
The applications demo board was built and tested for a frequency range of 20Hz to 20kHz with the component values as shown in Figure 4 and Vee= 5V. In the expander mode, the typical input dynamic range was from -34dB to+ 12dB where OdB is equal to 100mVRMS� The typical unity gain level measured at OdB@ 1kHz input was �0.5dB and the typical tracking error was :1:0.1dB for input range of -30 to +1OdB.
In the compressor mode, the typical input dynamic range was from -42dB to�18dB with a tracking error +0.1 dB and the typical unity gain level was �0.SdB.
In the ALC mode, the typical input dynamic range WilS from -42dB to +BdB with typical output deviation of �0.2dB about the nominal

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Product specification
NE/SA575SSOP

output of OdB. For input greater than +9dB in ALC configuration, the summing amplifier sometimes exhibits high frequency oscillations. There are several solutions to this problem. The first is to lower the values of R7 and RS to 20kQ each. The second is to add a current limiting resistor in series with C13 at Pin 13. The third is to add a compensating capacitor of about 22 to 30pF between the input and output of summing amplifier (Pins 12 and 14). With any one of the above recommendations, the typical ALC mode input range increased to +18dB yielding a dynamic range of over 60dB.

EXPANDOR
The typical expander configuration is shown in Figure 1. The variable gain cell and the rectifier cell are in the signal input path. The VREF is always 1/2 Vee to provide the maximum headroom without clipping. The OdB ref is 100mVRMS� The input is AC coupled through CS, and the output is AC coupled through C3. If in a system the inputs and outputs are AC coupled, then C3, CS, R3 and R4 can be eliminated, thus requiring only one external component, C4. The variable gain cell and rectifier cell are DC coupled so any offset voltage between Pins 4 and 9 will cause small offset error current in the rectifier cell. This will affect the accuracy of the gain cell. This can be improved by using an extra capacitor from the input to Pin 4 and eliminating the DC connection between Pins 4 and 9.

The expander gain expression and the attack and release time constant is given by Equation 1 and Equation 2, respectively.

.

4V1N(avg)

Expander gain= 3 _9k x 1OO�A

Equation 1.

COMPRESSOR
The typical compressor configuration is shown in Figure 2. In this mode, the rectifier cell and variable gain cell are in the feedback path. R6 and R7 provide the DC feedback to the summing amplifier. The input is AC coupled through C12 and output is AC coupled through CS. In a system with inputs and outputs AC coupled, CS, C12, RB, and R9 could be eliminated and only RS, R6, R7, C7, and C13 would be required. If the external components RS, R6, R7 and C7 are eliminated, then the output of the summing amplifier will motor-boat in absence of signals or at extremely low signals. This is because there is no DC feedback path from the output to input. In the presence of an AC signal this phenomenon is not observed and the circuit will appear to function properly.

The compressor gain expression and the
attack and release time constant l's given by
Equation 3 and Equation 4, respectively.
Equation 3.

~3.9k Compressor gai.n =

x 1OO�AJ 112

4V1N(avg)

where V1N(avg) = 0.97SV1N(RMS)

Equation 4.
'tR = 'tA = 10k X CREeT = 10k X C4
AUTOMATIC LEVEL CONTROL
The typical Automatic Level Control circuit configuration is shown in Figure 3. It can be seen that it is quite similar to the compressor schematic except that the input to the rectifier

cell is from the input path and not from the feedback path. The input is AC coupled through C12 and C13 and the output is AC coupled through CB. Once again, as in the previous cases, if the system input and output signals are already AC coupled, then C12, C13, CB, RB and R9 could be eliminated. Concerning the compressor, removing RS, R6, R7 and C7 will cause motor-boating in absence of signals. CeoMP is necessary to stabilize the summing amplifier at higher input levels. This circuit provides an input dynamic range greater than 60dB with the output within �0.SdB typical. The necessary design expressions are given by Equation S and Equation 6, respectively.
Equations.

3.9kx 100�A
ALCgain = 4V1N(avg)

Equation 6.

'tR = 'tA = 10k X CREeT = 10k X C9

Figure S shows that the unity gain error remains small over a wide range of supply voltages. The unity gain error is important because it effects the tracking error. So, to achieve the best unity gain error, provide a power supply voltage of 4 to SV to the NES7S.

Figures 6 and 7 show the output level over a range of frequencies and inputs for the compressor and expander, respectively. These graphs reveal that the compandor has a constant and flat output. This is important because the signal will not be altered.

where V1N(avg) = 0.97SV1N(RMS)

Equation 2. 'tR = 'tA = 1Ok X CREeT = 1Ok X C4

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Low voltage compandor in shrink small outline package

Product specification
NE/SA575SSOP

------------------------- .. '

cs
EXP IN o------j l--+-ir-O-�J'v--t

10�F

10k

' 4 3.9k 8
C4I 2.2""
Figure 1. Typical Expandor Configuration

C S t R 3 EXPOUT 10Jlf
OOk
tc23250s

r - - - - - - - - - - - - - - - - - - - .- - - - ..

I

8

12

I

C12

: 13

1 '

COMP IN o---11--;,.-o--�J'v--.--+----j

10�F

10k

1 ,'
10k

6'

C13

3.9k

C9I 2.2""

Figure 2. Typlcal Compressor Configuration

C8tR9 COMPOUT
10Jlf OOk
TC23240S

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Low voltage compandor in shrink small outline package

Product specification
NE/SA575SSOP

RS 20k
r- - -

ALCIN

10�.F :

1Dk

=
CCOMP 22pF
12
1 '
11 ' 1Dk

C 8 t R a ALCOUT 10�
k

4.7�F :

10k
C9l 2.2�F
Figure 3. Typical ALC Configuration Vcc-5V

TC23260S

~~~~~~_....~-+-~fC-12o C~OIMfP/ 1D�F

=

cs

EXPo-----jl--~~~~~

IN

10�F

OMP

R9

C 8 ? 2 0 0CAOLMCP/

R7

�F R9

OUT

30k

100k

C7 _ I1�F -
=

VREF Figure 4. Slgnetlcs NE575 Low Voltage Expandor/Compressor/ALC Demo Board

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Low voltage compandor in shrink small outline package

Product specification
NE/SA575SSOP

.9
.8 ~ .7
~ .6 a: .5
g .4
a: w .3
~ .2
Cl .1
~ 0
!i-.1
-.2

4

5

6

8

SUPPLY VOLTAGE (V)

Rgure 5. Unity Gain Error vs Supply Voltage

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Low voltage compandor in shrink small outline package

Product specification
NE/SA575SSOP

TYPICAL PERFORMANCE CHARACTERISTICS

8
6
4
2
0 -2
ii]-4 ~
>.ww.J ....
....J......
::::>
l..l...
5-10 -12
-14
-16
-18 -20
-22 10

10dBIN OdBIN

GENERAL DIAGRAM

....

INPUT

T 1D�F J'4.7�~ _I_ t>G REC

(20-20kHz)

SUM .....

OUTPUT

Vcc=SV

v ~

-40dBIN

I I

100

1000

10000

30000

FREQUENCY (Hz)

Figure 6. Compressor Output Frequency Response

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Low voltage compandor in shrink small outline package

Product specification
NE/SA575SSOP

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

8 6

LI

4

2 .....

OclB IN

0

-2
m-4
~ ..J
~ -6
..J
!; -6
Cl. I-
::> 0-10
-12

INPUT (20-2llkllz)

GENERAL DIAGRAM

~If- REC IH ..G

~PUT SUM

-

10,..F Vcc=&V

-14 -16

-18
-20
-22 10

-10clBIN

l

.....

I I

100

1000

10000

30000

FREQUENCY (Hz)

Figure 7. NE575 Expandor Output Frequency Response

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Low voltage compandor in shrink small outline package

Product specification
NE/SA575SSOP

COMPRESSOR IN +12dB 100mV
OclB -10clB -20dB
-OOdB
-IOclB
-60clB

"'

+5dB OdB

/

-adB

-10clB -15dB -aldB -25c!B

"~ '

COIFRESSION

' 4J ,
EXPANSION

Figure 9. The Compandlng Function

EXPANDOR OUT +12dB 100mV OclB -10clB -aldB
-OOdB
-IOclB
-80clB

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Phillps Semiconductors-Signetlcs RF Communications
Low power compandor

Product speclflcstion
NE/SA576

DESCRIPTION The NE/SA576 is a unity gain level programmable compandor designed for low power applications. The NE576 is internally configured as an expandor and a compressor to minimize external component count.
The NE576 can operate at 1.8V. During normal operations, the NE576 can operate from at least a 2V battery. If the battery voltage drops to 1.8V, this part will still continue to function, however, turning on the part at a Vee of 1.8V requires two external resistors to bring VREF to half Vee. One resistor connects between Vee and VREF; the other connects from VREF to ground. A typical value for these external resistors is approximately 20k. A lower value can be used, but the power consumption will go up.
The NE576 is available in a 14-pin plastic DIP and SO packages.

FEATURES �Operating voltage range: 1.8V to 7V � Low powerconsumption
(1.4mA@ 3.6V) �Over 80dB ofdynamic range � Wide input/output swing capability
(rail-to-rail) � Low external component count � ESD hardened
APPLICATIONS � Cordless telephone � Consumer audio � Wireless microphones �Modems � Electric organs � Hearing aids � Automatic level contrcl

PIN CONFIGURATION
D and N Packages
Vee
COMPCAP2 COMPiN 11 COMPcAP1 RECT1N 9 GCEl4N
a COMPour

ORDERING INFORMATION

DESCRIPTION 14-Pin Plastic DIP

TEMPERATURE RANGE
o to +70�C

14-Pin Plastic SO

o to +70�C

14-Pin Plastic DIP

-40to +85�C

14-Pin Plastic SO

-40to +85�C

ORDER CODE NE576N NE576D SA576N SA576D

ABSOLUTE MAXIMUM RATINGS

SYMBOL

PARAMETER

Vee TA TsTG
BJA

Supply voltage

Operating ambient temperature range

Storage temperature range

Thermal impedance

DIP

so

RATING

NE576

SA576

8

8

0 to +70 -40to +85

-65to+150 -65to+150

90

90

125

125

UNITS
v oc oc
�C/W �C/W

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853-1536 01613

Philips Semiconductors-Signetics RF Communications
Low power compandor

Product specification
NE/SA576

BLOCK DIAGRAM and TEST AND APPLICATION CIRCUIT

EXPc1N>:-jC1t - ' - � - - , - - ;
10�F

16 i - - - - a Yee
COMPcAP2
15

EXPcAP
c2 + 2.2�F
I C3
I -= EXP~uT 1-�F~-----1 4

I+ lEF

5

O�F

-=

R2�

7
GND

PWRDN/ <>----< MUTE

8

*R1, R2 and R3 are 1% resistors.

EX PAN DOR
YREF BANDGAP IREF

GAINCELL

f-- 1-T---'--�"l

COMPouT

C9 10�F
~~--.... PT~4

+ ~ SUM1N

C10 10J.1F

ELECTRICAL CHARACTERISTICS
TA= 25�C, Vee = 3.6VDC, compandor OdB level = -20dBV = 100mVRMS� output load RL = 1OkQ, Freq= 1kHz, unless otherwise specified. R1, R2 and R3 are 1% resistors.

LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

NE/SA576

UNITS

Vee Supply voltage1

MIN

TYP

MAX

2

3.6

7

v

Ice VREF

Supply current Reference voltage2

No signal R2 = 100kn
Vee= 3.6V

1.4

3

mA

1.8

v

RL THD

Summing amp output load Total harmonic distortion

1kHz, OdB, BW = 3.5kHz

10

kQ

0.25

1.5

%

ENo Expander output noise voltage

BW = 20kHz, Rs = OQ

10

30

�V

OdB Unity gain level

OdB at 1kHz

-1.5

0.18

1.5

dB

Vos Output voltage offset

No signal

-150

1

150

mV

Expander output DC shift

No signal to OdB

-100

7

100

mV

Tracking error relative to OdB output

-20dB expander

-1.0

0.3

1.0

dB

Crosstalk, COMP to EXP

Vo

Output swing low

Output swing high

1kHz, OdB, CREF = 10�F

-80

dB

0.2

v

Vee-0.2

v

NOTE:
1. Operation down to Vee = 1.8V is possible, see description on front page of NE576 data sheet.
2. Reference voltage, VREF. is typically at 1/2 Vee.

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Low power compandor

Product specification
NE/SA576

TYPICAL PERFORMANCE CHARACTERISTICS
Vee= 3.SV, TA= 25�C, R1=R3=18.7k!l, R2=24.3k!l, OdB level= 100mV, Freq.= 1kHz

SUPPLY CURRENT vs SUPPLY VOLTAGE

SUPPLY CURRENT vs TEMPERATURE
1.6-------------~-~

1.B-t---+--1---+---t---+---'I---..,...;
1.6-t---+--+--+----t--..-'fkd'-----lv---;
11.4--+---+-+--7'1"-V_+-V-t---t----1
~ ~
gj 1.2-+---11~-,__--+---+---t--,__--1
()
l ~~ 1-t---H,--1---+---+--+--l-----I
O.B-+--+--!---+---+--+--1-----1

v - t 1 . 5 - + - - - + - - , _ _ - - + - - - + - - - + - - , _ _ - - I
1.4-+--+-~--+~-"1VF--+--+-----1
a V1v 11.3-+--+--t-V--+v--l---+---+---I
g;
~ 1.2-+---t--t----+---+---t--t----1
g,
U)
1.1-+--+--l---+---+--+--1-----1

3

4

5

6

SUPPLY VOLTAGE (V)

UNITY GAIN ERROR vs SUPPLY VOLTAGE
0.6---------------~
NOTE: UNITY GAIN ERROR MAY BE SET TO 0 AT ANY Vee BY
0.4 +-A_D_J_US_TrlN_G_T_H_E_VAL-r-U_E_OF_R1,._R3_ _+--=-"9

0.2+---t--:=----"f"'----t---f----l
~
a::
~ o-r-......;�:::----t---t---f----l ffi
z
<(
~-0.2-t----+----+----t---1-----1
z
:::>
- 0 . 4 - t - - - - + - - - - + - - - - t - - - , _ __ _ ,

1-+---+~-t--~-+-~-+---+--t--.---1

-40 -20

20

40

60

60 100

AMBIENT TEMPERATURE (�C)

UNITY GAIN ERROR vs TEMPERATURE
o.6-----~--------~~

0.4-+----+--t----+---+----+--,__--1

EXPANDOR
~~ oo.~2~+l-----+F"-.v-.f_-~-;r--=---:,b-==--+1--"+"r"-:-:-:.f::-:--.-.-:i:t:---:-:1,-"-1-ti--k-+--�----lj

~

COMPAESSO~

~-0.2-+---+--l---+---+--+----11----1

z
:::>

-0.4-+---+--,__--+---+---+----lf----1

-0.6-t--..---t--...--+--.----t--.--1---r---I

4

5

SUPPLY VOLTAGE (V)

TRACKING ERROR vs INPUT LEVEL

NOTE: RELATIVE TO UNITY GAIN

-0.6

-40 -20

0

20

40

60

TEMPERATURE (�C)

80 100

THO vs TEMPERATURE
0.5

0.4

~

; o+---+----1--c:=~'iE=='--~
w
~

,_lco.3
:i::

~

0

-0.5-+-_,_---t-----1-----+-----I

0.2

-1-t--.--.--.--+-~~~+---....-+----r--1
4 INPUTLEVEL dB

January 31, 1991

220

0.1 -40 -20

0

20

40

60

TEMPERATURE "C

80 100

Phillps Semlconductors-Slgnetlcs RF Communications
Unity gain level programmable power compandor

Product specification
NE/SA577

DESCRIPTION
The NE/SA577 is a unity gain level programmable compandor designed for low power applications. The NE577 is internally configured as an expander and a compressor to minimize external component count.
The NE577 is available in a 14-pin plastic DIP and SO packages.
FEATURES
� Operating voltage range: 1.8V to 7V
� Low power consumption (1.4mA@3.6V)
� OdB level programmable (10mVRMS to 1.0VRMS)
� Over 90dB of dynamic range
� Wide input/output swing capability (rail-to-rail)
� Low external component count
� SA577 meets cellular radio specifications
� ESD hardened

APPLICATIONS
� High performance portable communications
� Cellular radio � Cordless telephone � Consumer audio � Wireless microphones �Modems � Electric organs � Hearing aids � Automatic level control (ALC)

PIN CONFIGURATION
D and N Packages

GCELL1N 1

Vee COMPcAP2

COMP1N

COMPcAP1

RECT1N 9 GCEL'-IN

L__ _...J 8 COMPouT

ORDERING INFORMATION

DESCRIPTION

TEMPERATURE RANGE

14-Pin Plastic DIP

0 to +70�C

14-Pin Plastic SO

o to +70�C

14-Pin Plastic DIP

-40 to +85�C

14-Pin Plastic SO

-40 to +85�C

ORDER CODE NE577N NE577D SA577N SA577D

ABSOLUTE MAXIMUM RATINGS

SYMBOL

PARAMETER

Vee TA TsTG
8JA

Supply voltage

Operating ambient temperature range

Storage temperature range

Thermal impedance

sDoIP

RATING

NE577

SA577

8

8

Oto +70 -40 to +85

-65 to +150 -65to +150

90

90

125

125

UNITS
v
oc oc oc/W oc/W

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Philips Semiconductors-Signetics RF Communications
Unity gain level programmable power compandor

Product specification
NE/SA577

ELECTRICAL CHARACTERISTICS
TA= 25�C, Vee = 3.6VDC, compandor OdB level = -20dBV = 1OOmVRMS� output load RL = 1OkQ, Freq= 1kHz, unless otherwise specified. R1, R2 and R3 are 1% resi stars.
LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

NE/SA577

UNITS

Vee Supply voltage1

MIN

TYP

MAX

2

3.6

7

v

Ice VREF

Supply current Reference voltage2

No signal R2 = 100kQ
Vee= 3.6V

1.4

2

mA

1.7

1.8

1.9

v

RL THO

Summing amp output load Total harmonic distortion

1kHz, OdB, BW = 3.5kHz

10

kn

0.25

1.5

%

ENo Expander output noise voltage

BW = 20kHz, Rs = on

10

25

�V

OdB Unity gain level

OdB at 1kHz

-1.5

0.18

1.5

dB

Programmable range3

R1 = R3 = 18.7kQ, R2 = 24.3kn

0

dBV

R1 = R3 = 22.6kQ, R2 = 100kQ

-10

dBV

R1=R3=7.15kQ, R2 = 100kQ

-20

dBV

R1 = R3 = 1.33kQ, R2 = 200kQ

-40

dBV

Vos Output voltage offset

No signal

-150

1

150

mV

Expander output DC shift

No signal to Od B

-100

7

100

mV

Tracking error relative to OdB output

-20d8 expander

-1.0

0.3

1.0

dB

Crosstalk, COMP to EXP

Vo

Output swing low

Output swing high

1kHz, OdB, CREF = 1O�F

-80

-65

dB

0.2

v

Vcc-0.2

v

NOTE: 1. Operation down to Vee= 1.8V is possible, see application note AN1762. 2. Reference voltage, VREF. is typically at 1/2 Vee.
3. Unity gain level can be adjusted CONTINUOUSLY between -40dBV = 1OmVRMS and OdBV = 1.0VRMS� For details see application note AN1762.

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Unity gain level programmable power compandor
BLOCK DIAGRAM and TEST AND APPLICATION CIRCUIT

=

C3
EXPo~ +

r10�F
lEF +

10�F

=

= GND
�R1, R2 and R3 are 1% resistors.

EXPANDOR
VREF
BANDGAP Vee
GND

Product specification
NE/SA577

14

Vee

eOMPeAP2

TO PIN4

January 31, 1991

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Philips Semiconductors-Signetics RF Communications
Unity gain level programmable power compandor

Product specification
NE/SA577

TYPICAL PERFORMANCE CHARACTERISTICS
Vee= 3.6V, TA= 25�C, R1=R3=18.7kn, R2=24.3kQ, OdB level= 100mV, Freq.= 1kHz

SUPPLY CURRENT vs SUPPLY VOLTAGE

SUPPLY CURRENT vs TEMPERATURE
1.6~-~------~-~---~

1.B-+---+--t---+---t----+----it---<
~1.4-+---+---+--7"1V~_vt---+--;-_, 1.6-+---+-+--t--+--..-f"-k1___,vl---I
!~z 1.2-+--_,v~-t---+---t----+--t---1
()
'.'.; _l ~ 1-+---,--<-+--t----+---1----+--t----<
O.B-+---+---jl---+---+---+---l----1

~ 1 . 5 - + - - - - + - - t - - - + - - - + - - - + - - t - - - - ;
! v 1 u+--t--f----1--"7"4'--t--f-----l
. Y ~r5 1.3-+----+-,,,.LJ"+----+--t---+---+---l j
1~5 1.2V -+-I---+--t---+---+----+--t----;
:::> UJ
1.1-+---+--t---+---t----+--t----<

SUPPLY VOLTAGE (V)
UNITY GAIN ERROR vs SUPPLY VOLTAGE
0.6~-----~--------~
NOTE: UNITY GAIN ERROR MAY BE SET TO 0 AT ANY Vee BY
-+-=-9 0.4 +-AD_J_us_TTIN_G_T~H_E_VA,L_U_E_O_F_R1,._R3_ _

o.2+---+-=---1""----l---f----l
iD '.E. a:
~ 04"~--;;�::----t----j,----t----1
ffi
;z;;: ~-02-+----+----t----jl----t------I
z
:::>
�0.4-+----+----t----jl----t------1

-0.6-+--~--+---+-~-r-~-t-----<

4

5

SUPPLY VOLTAGE (V)

TRACKING ERROR vs INPUT LEVEL

NOTE: RELATIVE TO UNITY GAIN

-40 �20

0

20

40

60

80 100

AMBIENT TEMPERATURE re)

UNITY GAIN ERROR vs TEMPERATURE

0.4--+----+----it--+----+----+--t---l

EXPANDOR

V I ~ o.2-+--+--f-=�--+"""""�'.f-=~~---1 ~ k.... ffi o+--+~-tr---:==----tj------~t---t---t---1

~

COMPRESSO~

~�O 2-+---+---+--+----+---+---lt----1

z
:::>

�0.4-+---+---j--+----+---+---jl-----1

-0.6-+----+~---<t--+---+-~--+~---<t-..----<

~

~

0

20

~

00

TEMPERATURE (0 e)

00 100

THO vs TEMPERATURE

iD '.E. a:
~ o-+----+----+--==-;;:::.-k:::=:==----1
w
g:>::o>-
:::> 0
�0.5-+--r---+-----+----+-----l

January 31, 1991

INPUT LEVEL dB

-40 -20

0204060 TEMPERATURE 0 e

80 100

224

Slgnetlcs RF Communications
Unity gain level programmable low power compandor

Product speclHcatlon
NE/SA578

DESCRIPTION The NE/SA578 is a unity gain level programmable compandor designed for low power applications. The NE578 is internally configured as an expander and a compressor to minimize external component count.
The summing amplifiers of the NE578 have 600W drive capability and the inverting input of the compressor amplifier is accessible through Pin 9 for summing multiple external signals. Power Down/Mute function is active low and requires an open collector output logic configuration at Pin 8. If Power Down/ Mute is not needed, Pin 8 should be left open. When the part is muted, supply current drops to 170mA at 3.6V. The NE578 is available in a 16-pin plastic DIP and SO packages.
FEATURES � Operating voltage range: 1.8V to 7V
� Low power consumption (1.4mA@ 3.6V)
� OdB level programmable (10mVRMS to 1.0VRMS)
� Over 90dB of dynamic range

� Wide input/output swing capability � Low external component count � SA578 meets cellular radio specifications � ESD hardened � Power Down mode
(Ice = 170mA @ 3.6V) � Mute function � Multiple external summing capability � 600W drive capability
APPLICATIONS � High performance portable
communications � Cellular radio � Cordless telephone � Consumer audio

PIN CONFIGURATION D and N Packages
Vee COMPeAP2 COMl'JN eoMPeAP1 REeT1N GeEL4N
COMP our
PWRDNI MUTE - L -_ _ _,---
� Wireless microphones �Modems � Electric organs � Hearing aids �Automatic level control (ALC)

ORDERING INFORMATION

DESCRIPTION

TEMPERATURE RANGE

16-Pin Plastic DIP

Oto +70�C

16-Pin Plastic SO

Oto +70�C

16-Pin Plastic DIP

-40 to +85�C

16-Pin Plastic SO

-40to +B5�C

ORDER CODE NE578N NE578D SA578N SA578D

ABSOLUTE MAXIMUM RATINGS

SYMBOL

PARAMETER

Vee TA TsrG
9JA

Supply voltage

Operating ambient temperature range

Storage temperature range

Thermal impedance

sDoIP

RATING

NE578

SA578

8

8

Oto +70 -40 to +85

-65 to +150 -65to+150

90

90

125

125

UNITS
v
oc oc oc/W oc/W

January 31, 1991

225

853-1537 01614

Signetics RF Communications
Unity gain level programmable low power compandor

BLOCK DIAGRAM and TEST AND APPLICATION CIRCUIT
EX~Cl-1.~--.---t
10�1'

EXPeAP

Ic2 +

2.2�F

C3

-= EXP~ur \ t-��~F---< 4

lEF I�

5

O�F

R2�

7
GND

PWRDNI 0-----4 MUTE

8

�R1, R2 and R3 are 1% resistors.

EXPANDOR
VREF

Product specification
NE/SA578
16 1----0 Vee
eOMPeAP2
15

f-> ,_,_~-�""'

eOMPour

10�F

""'-'-----�� PT~4 + f--<> SUM1N

January 31, 1991

226

Signetics RF Communications
Unity gain level programmable low power compandor

Product specification
NE/SA578

ELECTRICAL CHARACTERISTICS

TA= 25�C, Vee= 3.6VDC, compandor OdB level = -20dBV = 1OOmVRMS� output load RL = 1OkQ, Freq= 1kHz, unless otherwise specified. R1, R2 and R3 are 1% resistors.

LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

NE/SA578

UNITS

Vee Supply voltage'

MIN

TYP

MAX

2

3.6

7

v

Ice VREF

Supply current

operating power down

Reference voltage2

No signal, R2 = 100kQ Vee= 3.6V

1.4

2

mA

170

�A

1.7

1.8

1.9

v

RL

Summing amp minimum output load

600

Q

THD ENo

Total harmonic distortion Expander output noise voltage

1kHz, OdB, BW = 3.5kHz
BW = 20kHz, Rs = on

0.25 10

1.0

%

20

�V

OdB Unity gain level

OdB at 1kHz

-1.0

0.18

1.0

dB

Programmable range3

R1 = R3 = 18.7kn, R2 = 24.3kQ

0

dBV

R1 = R3 = 22.6kn, R2 = 100kn

-10

dBV

R1 = R3 = 7.15kn, R2 = 100kn

-20

dBV

R1 = R3 = 1.33kn, R2 = 200kn

-40

dBV

Vos Output voltage offset Expander output DC shift

No signal No signal to OdB

-150

1

150

mV

-100

7

100

mV

Tracking error relative to OdB output

-20dB expander

-1.0

0.3

1.0

dB

Crosstalk, COMP to EXP

Vo

Output swing low

Output swing high

Power Down/Mute low level

1kHz, OdB, CREF = 10�F

-80

-65

dB

0.2

v

Vee-0.2

v

0

0.4

v

Power Down/Mute input current

Pin 8 grounded

-65

�A

NOTE: 1. Operation down to Vee= 1.SV is possible, see application note AN1762. 2. Reference voltage, VREF� is typically at 1/2 Vee. 3. Unity gain level can be adjusted CONTINUOUSLY between -40dBV = 1OmVRMS and OdBV = 1.0VRMS� For details see application note
AN1762.

January 31, 1991

227

Signetics RF Communications
Unity gain level programmable low power compandor

Product specification
NE/SA578

TYPICAL PERFORMANCE CHARACTERISTICS
Vee= 3.6V, TA= 25�C, R1=R3=18.7kQ, R2=24.3kQ, OdB level= 100mV, Freq.= 1kHz

SUPPLY CURRENT vs SUPPLY VOLTAGE

SUPPLY CURRENT vs TEMPERATURE
1.6--.,---r--.--,--~--r--.---.

1.8
1.6
<S"1.4 S;: aU:J
~ 1.2

lLv ~v ~v

"".;

Cl. :C:>l.

1

-!-

CJ)

0.8

~ 1 . 5 - + - - - + - - - < l - - - + - - - + - - - + - - - < I - - - - !
r3vr v 1.4-!--t---+--+-7"""T-k-1-+---1r--t
1
S;:
~ 1.2-+---+--1----+---+---+--I----!
Cl. ::> CJ)
1.1 -+---+--t-----+---+---+--1-------l

0.6

3

4

5

6

SUPPLY VOLTAGE (V)

UNITY GAIN ERROR vs SUPPLY VOLTAGE
0.6--.,-----,.----,.---,---,-----. NOTE: UNITY GAIN ERROR MAY BE SET TO OAT ANY Vee BY ADJUSTING THE VALUE OF R1, R3
OA--j----,-----,----,---t-::~'"'"9

ro 0.2+---+-:;;;-..-o!'<::::....---l---f------l
:E. a:
~ 0--i'"~---;;;�:::----t-----J---t-----l ffi
< z
~-0.2-t------+----+----1---1----i
z
::>
-0.4-+----+---+----<---l-----!

~

~

o ro ~ oo oo 100
AMBIENT TEMPERATURE ("C)

UNITY GAIN ERROR vs TEMPERATURE o.6-r---.----,c----.---,---.----,c----.

0.4-+---+---1f---+---+---+---1f----i

EXPANDOR

0.2+--+--lf-=l---+"""~l---.=~f,.--I
V - ro

i o-f><::::f---f""._..!;;:=--+--lf----t--+---1

--r--+- f~fi

COMPRESSO~

~-0.2

z
::>

�0.4-t---+--f---+---+---+--f----i

-0.6-t--r----+--.---+--.----1--.--t--.,---i

4

5

SUPPLY VOLTAGE (V)

TRACKING ERROR vs INPUT LEVEL

NOTE: RELATIVE TO UNITY GAIN

�0.6-t--.--+-.-f--r-+--.---t---.-+-r-f--..---1

~

~

o ro ~ oo
TEMPERATURE (�C)

oo 100

THO vs TEMPERATURE
0.5--.,---,.--,----.----.,---r--r-~

~
ia: o--1------1-----+---==.,.;>'!E=='-----1
UJ
f-
:g:>o
::> 0
-0.5-t--+---+-----+----+------1

g0.3--f---+----Jf"'"....,+--+----'l'-"'9f----I
I f-
0.2-t---+---<l---+---+---+---<I----!

January 31, 1991

INPUTLEVEL dB

0.1 -t---.-+-.--1f--r-+--.---t---.-+-r-f--..---l
-40 -ro O r o 4 0 6 0 00 100
TEMPERATURE "C
228

Philips Semlconductors-Signetlcs RF Communications
Companding with the NE577 and NE578

Application Note
AN1762

Author: Alvin K. Wong
INTRODUCTION This application note is written for the designer who understands the basic functions of companding and wants to use the NE577 or NE578. If a designer is not familiar with the functionality of compandors, a good discussion can be found in the earlier Philips Components-Signetics compandor data sheets and applications notes.
Key topics discussed in this paper are: � How to program the unity gain level
(OdB) � How to implement an automatic level
control � How to get the best companding
performance under strict design requirements � How to set the attack and recovery time � How to operate at 1.BV � How to sum external signals using the NE578 � How to power-down the NE578 � How to mute the NE578 � How to use the NE577 and NE578 as a dual expandor
But before reviewing these areas, a summary of Philips ComponentsSignetics compandor family will be presented. A system designer can then determine which compandor is best for the design.
SUMMARY OF COMPANDOR FAMILY In the past, Philips Components-Signetics offered four different types of compandors: the NE570, NE571, NE572, and NE575. Each of the four compandors has its own 'claim to fame'. The NE570 and NE571 are known to work well in high performance audio applications. The only real difference between the two is that the NE570 has a slight edge in performance. However when separate attack and recovery times are needed, the NE572 is the compandor to choose. The NE575 becomes useful when there are low voltage requirements.
With the increasing demand for low current consumption, good flexibility, and ease of use in semiconductors,

Philips Components-Signetics is offering three additional compandors to its family, the NE576, NE577 and NE578. These compandors typically require an Ice of 1.4mA at a Vee of 3.6V, but Philips Components-Signetics has demonstrated that these new chips are functional down to 1.BV.

variations in systems design. The external capacitors are also reduced in value which saves board space and cost. The only trade-off with using smaller capacitors is that there is less filtering. Because of this new approach, the NE576, NE577 and NE578 are easy to implement in any design.

In addition to having low power consumption, the NE578 has a power-down mode. In this mode, the chip consumes only 170�A. This power-down mode is useful when the functionality of the chip is not needed at all times. In the power-down mode , the NE578 maintains all of its pin voltages at all their normal DC operating voltages. Because all of the capacitors remain charged in this mode, the power-up state will occur quickly. Powering down automatically mutes the NE578. Having the mute function internal to the NE578 audio section eliminates the need for an external switch. The NE578 is the only compandor in the family that has power-down and mute functions.
To allow for greater flexibility, the OdB level is now programmable for the NE577 and NE578. However, for the NE576, the OdB level is specified and set at 1OOm VRMS� The earlier compandors also have a set unity gain (OdB) level. The NE570 and NE571 have a set OdB level at 775mVRMS� While the NE572 and the NE575 both have their OdB levels at 1OOmVRMS� If a designer wanted a different OdB level, two op amps would have to be implemented in the design. One of the op amps would connect to the input of the compandor, while the other op amp would connect to the output. But with the NE577 and NE578, these external op amps are no longer needed. The OdB level can be programmed from 1OmVRMS to 1VRMS with three external resistors.
Many of the external parts in the previous family of compandors are now internal to the device. Additionally, the left side of the chip is configured as an expandor, and the right side is configured as a compressor. This allows for minimum part count and fewer

Table 1 shows a brief summary of all the compandors. The seven different compandors offer a wide range of flexibility: different types of packages, power-down capability, programmable or fixed unity gain, different reference voltages, a wide range of operating voltages and currents, different pin outs, etc. From this information, a designer can quickly choose a compandor which best meets the design requirements. After a compandor is chosen from the table, a designer can find additional help from data sheets and application notes.
Since power consumption is important in most designs, it is important to discuss them in this application note. The NE570, NE571, and NE572 have built in voltage regulators, therefore, the current consumption remains roughly the same over the specified supply voltages. This can be especially useful when the power supply is not regulated very well. However with the NE575, NE576, NE577, and NE578, the current consumption will drop as the supply voltage decreases. For this, the power consumption will drop also. This means one can operate the part at a very low power level. This is a good feature for any design having strict power consumption guidelines.
INTRODUCING NE577 AND NE578 Figure 1 and 2 show block diagrams of the NE577 and NE578 respectively. The only substantial difference between the two is that the NE578 has a power-down capability, mute function and summing capabilities (for signals like DTMF tones). In addition the NE578 summing amplifiers are capable
of driving soon loads. Listed below are
the basic functions of each external component for Figure 1 (NE577).

September 1990

229

Philips Semiconductors-Signetics RF Communications
Companding with the NE577 and NE578

Application Note
AN1762

Table 1. Compandor Family Overview

:�:� ��������:�:�:�:�:�:�~: .:�:::::�:;:::;:;:;:::;:;::::::

~~~~~~~~~ili~~~~ti~[~

~~~[~t~trn

NE570

NE571

Vee

6--24V

6-18V

Ice Number of Pins

3.2mA 16

3.2mA 16

Packages
NE: o to +10�c
SA: -40 to +85�C N: Plastic DIP D: Plastic SO
F: Ceramic DIP DJ: SSOP
(Shrink Small
OuUine
Package)

NE570F NE570N NE570D

NE571F NE571N NE571D
SA571F SA571N SA571D

ALC (Automatic Level Control)

Both Channels

Both Channels

Reference Voltage

Fixed 1.BV

Fixed 1.BV

Unity Gain

775mVRMS

775mVRMS

Power-Down

NO

NO

Key Features

-Excellent Unity Gain Tracking Error -Excellent THD

-Excellent Unity Gain Tracking Error -Excellent THD

Appllcatlons Cordless Phones Cellular Phones Wireless Mies Modems Consumer Audio Two-way Communications

High performance audio circuits

High performance audio circuits

"Hi-Fi Commercial
Quality"

"Hi-Fi Commercial
Quality"

NE572 6-22V 6mA
16
NE572N NE572D
SA572F SA572N SA572D
Both Channels Fixed 2.5V 100mVRMS
NO -Independent Attack & RecoveryTime -Good THD -Needs ext. summing op amp
High performance audio circuits
"Hi-Fi Studio Quality"

NE575 3--7V 3-5.5mA'
20
NE575N NE575D NE575DJ SA575N SA575D SA575DJ
Right Channel
Vcc/2 100mVRMS
NO -2 Uncommited on-chip op amps available -Low voltage
Consumer audio circuits
"Commercial Quality"

NE576 2-7V 1-3mA'
14
NE576N NE576D
SA576N SA576D
Right Channel Vcc/2
100mVRMS NO
-Low power -Low external component count
Battery powered systems
"Commercial Quality"

NE577 2-7V 1-2mA'
14
NE577N NE577D
SA577N SA577D

NE578 2-7V 1-2mA'
16
NE578N NE578D
SA578N SA578D

Right Channel Right Channel

Vee/ 2

Vcc/2

10mV to 1VRMS 10mV to 1VRMS

NO

YES(170�A)

-Low power -Programmable unity gain

-Low power -Programmable unity gain -Power down -Mute function -Summing capability (DTMF) -600Q drive capability

Battery powered systems

Battery powered systems

"Commercial Quality"

"Commercial Quality"

NOTES: NE5750/5751 are also excellent audio processor components for high performance cordless and cellular applications that include the companding function..
'Ice varies with Vee.

R1 - Determines the Unity Gain Level for the Expandor
R2 - Determines What Value the Reference Current !IREF) will be for the Part (Also Affects Unity Gain Level)
R3 - Determines the Unity Gain Level for the Compressor

C1 - DC Blocking Capacitor C2 - Determines the Attack and Recovery
Time for the Expandor C3 - DC Blocking Capacitor
C4 - Used to AC Ground the VREF Pin C5 - Provides AC Path from Gain Cell to
Output of Summing Amp

C7 - DC Blocking Capacitor
CB - Provides AC Ground for the DC Feedback Path
C9 - DC Blocking Capacitor
'C10 - Increases the Dynamic Range and limits the Frequency Response to less than 500kHz

September 1990

230

Philips Semiconductors-Signetics RF Communications
Companding with the NE577 and NE578

Application Note
AN1762

=

es
~

EXPouT 10pF

=
R2"
= GND
�R1, R2 and R3are 1% resistors.

EXPANDOR

VREF

BANDGAP

IREF

Vee

GND

Figure 1. NE577 Block Diagram

10�F

EXPeAP

C2 + 2.2�F

I

C3

= I EXP~y f..L.---1 4

10pF

I� jEF

5

10�F
-=

= GND

7

PWRDN/ <>------< MUTE

8

�R1. R2 and R3 are 1% resistors.

EX PAN DOR

VREF

BANDGAP

IREF

Vee

GND PWRDN

Figure 2. NE578 Block Diagram

September 1990

231

Vee
eOMPcAP2
::r::+ C8 2.2�F
= C7
f-oeOMPiN 10�F

10PIN4

Vee

eOMPeAP2

15

::r::+ CB 2.2�F

C7 =

f-oeOMP1N 10�F

I-~'-~+ ~ eOMPouy
10�F
'-------~ Pw4 + ~ SUM1N
C10 10�F

Philips Semiconductors-Signetics RF Communications
Companding with the NE577 and NE578

Application Note
AN1762

Listed below are the basic functions of each external component for Figure 2 (NE578).
R1 - Determines the Unity Gain Level for the Expander
R2 - Determines What Value the Reference Current (IREFl will be for the Part (Also Affects Unity Gain Level)
RS - Determines the Unity Gain Level for the Compressor
R4 - Used to Set the Gain of an External � Signal like DTMF Tones and Sum them with the Companded Signal
C1- DC Blocking Capacitor
C2 - Determines the Attack and Recovery Time for the Expander
C3 - DC Blocking Capacitor
C4 - Used to AC Ground the VREF Pin
C5 - Provides AC Path from Gain Cell to Output of Summing Amp
CS - Determines the Attack and Recovery Time for the Compressor
C7 - DC Blocking Capacitor
CS - Provides AC Ground for the DC Feedback Path
C9 - DC Blocking Capacitor
C10 - DC Blocking Capacitor
�c11 - Increases the Dynamic Range and limits the Frequency Response to less than 500kHz
*Note: Bandwidth limiting is done to increase high frequency noise immunity and to make the performance of the part independent of layout or load capacitance.
HOW TO PROGRAM THE UNITY GAIN LEVEL (OdB)
Three external resistors R1, R2, and R3 define the unity gain level. Both the NE577 and the NE578 OdB levels can vary from 10mVRMS to 1.0VRMS� These limits are used in product characterization, but these parts can function over a wider OdB level range.
In most applications the OdB level is equal for both the compressor and expandor side. Therefore, R1 and R3 are equal in value. R3 sets the OdB level for the compressor side, and R1 sets the OdB level for the expander side. However, there could be a situation where a design requires different OdB levels for compression and expansion. This will not be a problem with the NE577 or NE578, due to the separate OdB level programming.
Using the formulas below, a designer can calculate the resistor values for a desired unity gain level.

Formula 1: R1 = Vso IRBF
where VeG = Bandgap Voltage IREF = Reference Current
(VBG is brought out on Pin 6 and R2 determines the IREF value)

Formula 2: R, = 0�9 �VINRMS IRBF
wll8re VINRMS is IM OdB level (R1 = R3 in most cases)

Programming the Unity Gain Level for the NE577 also applies for the NE578.

Example:

Program the NE577 or NE578 for a OdB Level at 100mVRMS
Step 1: VeG=1.26V....�..Typically IREF=12.6�A.....Good Starting Point
= 1.26V
R, 12.6 �A

Step 2:

R2= 100k

= = R, R3 0.9VINRMS

IRBF

R _ R _ (0.9V) (lOOmVRMS)

1- 3-

12.6�A

:. R1=R3=7.15k

Step 3: R1=Ra=7.15k (1% value) R2 = 100k (1% value)
Step 4: Plug in these resistor values and measure for unity gain. Adjust accordingly for accuracy.
NOTE: Rough Limits for Resistors: 1ks R1s100k (1% values) 20ks R2 s 200k (1% values) 1ksR3s 100k(1%values)

Rough Limits for IREF 6.3�A S IREF S 63�A
The example above gives pretty close results. A designer should use 1% resistors to get the best performance. Below in Table 2 are some recommended values to get started:

Table 2. Recommended Resistor Values for Different OdB Levels

OdB Level dBv R2 R1 &R3

1.0VRMS

0 24.3k 18.7k

316.2mVRMS -10 100k 22.6k

100mVRMS -20 100k 7.15k

10mVRMS -40 200k 1.33k

PARAMETERS THAT LIMIT THE DYNAMIC RANGE
The above example is a good place to start, but to get the optimum performance from the NE577 and NE678, a designer needs to understand certain key parameters. IREF is important because it determines the values for all three resistors (R1, R2, and R3). Since IREF is directly related to Ice (see Figure 3), one should be careful in choosing a value. If one chooses a high IREF current, power consumption goes up. However the output signal will have excellent low level distortion (see Figures 4 and 5). If one chooses a low IREF value, distortion at the output will increase slightly. Conversely, the power consumption is reduced, which might be worth the trade-off in battery operated designs.
The dynamic range of the NE577 and NE578 is determined by supply voltage (Vee) and reference current (IREFl� IREF determines how well the compandor will perform with low level input signals. The supply voltage determines how high (in level) an input signal can be before clipping appears on the output (in some cases increasing IREF also helps). A designer needs to estimate the input range going into the compandor so that an appropriate Vee and IREF can be chosen.
The bandgap voltage (VeG) slightly varies over a wide range of IREF currents (Figure 6). Figure 7 shows how IREF varies with R2. The higher R2 is, the lower IREF is. Figure 8 shows how the dynamic range varies over different values of IREF (the higher the supply voltage the better the dynamic range). The graphs in Figures 3 - 8 were taken at Vcc=3.6V, F=1 kHz and OdB level=100mVRMS� The IREF current was limited between 5�A and 40�A.
It can be seen that IREF plays an important role in current consumption, THO, and dynamic range. With the aid of these figures, one can determine an IREF which meets the design goals.
Example: Making use of the graphs in Figures 3 - 8 and formulas 1 and 2, design a compandor with a OdB level of 100mVRMS� Try to achieve a THO of 0.1 on the compressor side with wide dynamic range. Operate at a supply voltage of 3.6V but with the lowest possible current consumption.
Step 1: According to Figure 5, an IREF of 30�A is required for approximately 0.1% distortion.

September 1990

232

Philips Semiconductors-Signetics RF Communications
Companding with the NE577 and NE578

Application Note
AN1762

.o

v L

_.j

_L

.8

lL

j

17

.2
/

,,n.

0

10

20

30 40

50

IREF(�A)

Figure 3. IREF vs Ice

0

10 I2R0EF(�A3)0 40

50

Figure 4. IREF vs THO, Expandor Side

1.25
....

~1 .23
>

~

.22.

~

.21

o.n.

~
.20.

0

10

20

30 40

50

IREF(�A)

0

10

20 30 40

50

IREF(�A)

Figure 5. IREF vs THO, Compressor Side

Figure 6. IREF vs Vea

100
v-- .........
80

ii

100

:!!. w Ill

g

a~c:

a:

u <z!I 40

10

~

I

50
IREF(�A)
Figure 7. 'REF vs R2, R1

ft_

10

20

30

40

50

IREF(�A)

Figure 8. IREF vs Dynamic Range

= = Tes! Conditions� Vee= 3.6V F 1kHz OdB 100mVRMS

September 1990

233

Step 2: From Figure 8, the dynamic range is approximately 92dB. So far the requirements have been met.
Step 3: Figure 3 shows us that Ice is at 1.9mA with no input signal (thars not bad at all!).
Step 4: Calculating R1, R2, and R3

Graphical Method: From Figure 7: For IReF=30�A and OdB=100mVRMS R1=R3=3k R2=40k
Actual resistors available: R1=R3=3.01k (1%) R2=40.2k(1%)

Formula Method: From Figure 6: VeG=1.21V for IREF=30�A therefore, using formula 1:
Ri = Vso
[REF
Ri = 1.21V 3quA
R2=40.33k R2 = 40.2k (available in 1%)
Recall from formula 2:
R1 =10.9;V;1N;R;M;S-

R _ (0.9V) (IOOmVRMS)

1 -

3quA

R1 =3k R1 = 3.01k (available in 1%)

Connect these external resistors with the determined values and adjust for optimum performance.
Bench results: After completing the exercise above, the resistors were connected and the results are given below.
Ice = 1.89mA (with no input signal) THO = 0.1 (meausured on spectrum
analyzer) OdB = 109mVRMS (off by O.BdB...good!) Dynamic Range = 92dB
These results are very close to what was predicted and by tweaking R1 and R3, the OdB error can be further reduced to zero.

BANDWIDTH OF COMPANDOR Figure 9 shows the typical bandwidth for the NE577 and NE578. The graphs were taken with a Vee of 3.6V and a OdB level of 100mVRMS� The bandwidth of the expandor, the compressor, and the compandor (where a signal goes through the compressor and the expander) is shown in this figure. Although the NE577 and NE578 are conservatively specified with a 20kHz bandwidth, Figure 9 reveals that it is actually around 300kHz.

Philips Semiconductors-Signetics RF Communications
Companding with the NE577 and NE578

Application Note
AN1762

+10dB

OdB~.+--+-...+-++4--4--~~--+-..,..~rr-""i_~,,~, ~ExpoH-'~rM--t~ti11

OdB � _,_ t-++- f�1kH1z00mVRMS
Vcc=3.BV

~~

-70dB
LL.LJ,OOL-....l~..l.....J...1..~1k~-L~...J..-L...J..1~0k~...L.~...L....L...!.::100k::::-....l.~....L.--"....L.,~M;-""""~""""""""-;;;,OM
fNqUoncy(Hz)
F_!llure 9. Bandwidth of NE577 and NE578 Demo Board

HOW TO SET THE ATTACK AND RECOVERY TIMES C2 and CS, from figures 1 and 2, set the attack and recovery times for the NE577 and NE578. Application Note 174 (AN174) defines A and R times and also describes how they are measured on the bench. Formula 3 shows how the A and R time can be calculated.
Formula3: Attack Time [ms]= 10k � C2 or CS
Release Time [ms) =4 � Attack Time
Although a fast attack time is desirable, one must remember that there is a trade-off with low distortion. As a general rule, a 1�F capacitor for C2 will produce 0.2% THO at 1kHz. Since CCITT recommends an RC time constant of 20ms for the attack time, a 2�F capacitor is recommended for telephony applications because it has only 0.1% THO at 1kHz and 0.33% at BOOHz.
Note: AN 174 can be found in the 1989 Linear Data Manual, Volume 1, or the RF Handbook.

IMPLEMENTING A
PROGRAMMABLE AUTOMATIC LEVEL CONTROL The function of an automatic level control (ALC) is to take a given range of input signals and provide a constant AC output level. This type of function is useful in many audio applications. One such application can be found in tape recorders. When a tape recorder with ALC is recording a conversation, a soft spoken person will be heard just as well as a loud spoken person during play back. Another useful application for ALC could be with telephony. A person who has difficulty hearing, will not have to ask the other party to speak up. If the phone already has a volume control, the user has to adjust the volume for different parties. But with the ALC, the volume only has to be set once.
Different constant AC output levels of an ALC can be 'programmed' with the NE577 and NE578. This allows the designer to choose the output level that is needed in the design, and eliminates the need for an external op amp.

The compressor side of the NE577 and
NE578 can be configured to function as an
automatic level control (ALO). Figure 10 and 11 show how this can be done. The circuit shown for the NE577/78 ALO is set up to provide a constant output level of 100mVRMS with an input range from -34dB to +20dB at 1kHz (see Figure 12):

Below are some design equations for the
ALO: Eq 1.

R~~ =[ /REF]� AC outpuJ /evel(VRMs) R3 �

I.II

where R10 = R'Ja = 10k (internal)
IREF = Vso Rz

Eq2.

Eq3.

September 1990

234

Philips Semiconductors-Signetics RF Communications
Companding with the NE577 and NE578

Application Note
AN1762

September 1990

RDC1 30k

RDC2 30k

T E-o

e1nnF

ALC OUTPUT

TOPIN4
Figure 10. NE577 ALC Configuration

RDC1 30k

RDC2 30k

Figure 11. NE578 ALC Configuration 235

Example: Design an ALC with a constant output level of 100mVRMS with a maximum gain of 10.

Step 1: From Eq 1

R �Rii~IREF]. 3 AC oUlpUl level(VRMs) = [

1.11

where R10 = Rz. = !Ok (internal)
/REF= Vso Rz
In terms of R3 R3 =[" AC-o- Ul~ pU~ l le~ vel~ (V~ RM~ sl]~R~ 10 (1.11) (Rz.) [REF
assuming R2 = 1OOk and VsG = 1.26V.
R _ IOOmVRMs� IOk 3 - I.II � !Ok� 12.(\uA
R3 = 7.ISk

Step 2: From Eq 2

.

. 4{R3 + Rx)-Rz. �!REF

Max'"""" Ga111 =

R1.� Vee

In terms of Rx

(Max. Gain) (Vee) (R1;,)

Rx=

4Rz.�IREF

-R3

R - (IO) <3�6V) (!Ok) -7.ISk
x - 4 (!Ok) 12.(\uA

Rx= 707.lk
Rx = 71Sk (available)
Step3: --<X>nnect resistors to circuit -measure AC output level and adjust R3 for best accuracy -check maximum gain by applying a low input level and adjust Rx for best results
Figure 12 shows the characteristics of the NE577/578 ALC circuit without Rx. The output stays ata constant 100mVRMS level for a wide range of different input AC voltages. Any AC input signal above the cross-over point (unity gain level) is attenuated while any signal below the cross-over point is amplified. The cross-over point is where the input signal is equal to the output signal, where Av=1.
Figure 13 reveals the dynamic range of the NE577 ALC circuit using Rx. The input range of the ALC is reduced. Instead of a 2mVRMS input signal to get 100mVRMS on the output, a 10mVRMS input signal is now required (for Rx=681 k). The purpose of limiting the maximum gain of the circuit is to prevent amplification of background noise. To alleviate this problem, Rx is used. Since the ALC was designed with a maximum gain of

Philips Semiconductors-Signetics RF Communications
Companding with the NE577 and NE578

Application Note
AN1762

10, any input signal below 10mV will not be amplified with a gain greater than 10 (100mVRMsl10=10mvRMsJ. Using Rx can be an advantage because the threshold of the ALC can be set.
Figure 14 shows that as Rx increases so does Av. In some applications it might be useful to make Rx a potentiometer. This will allow the user to adjust the threshold for different environmental conditions.
Figures 15-18 show the results of using the ALC for different constant output levels. Vee and IREF limit the dynamic range. The upper part of the range can be increased by either increasing Vee and/or IREF� The lower part of the range can be improved by increasing
IREF�
EXTRA FEATURES FOR NE578 The NE578 has three extra functions over the NE577. These are power-down, mute and summing capabilities. To implement the
power-down/mute mode, Pin a should be
aFcigtiuvreelo1w9)(.opIfetnhecoplolewcetorr-dcoownnfig/muruatetiofne~tsueree
is not used, Pin 8 should be left open. The NE578 only consumes 170�A of current at 3.6V when Pin 8 is activated. The power-down/mute mode is useful in designs when the function of the chip is not utilized at all times. This feature is a necessity where power conservation is critical.
In cellular and cordless applications, It is common to mix DTMF tones with the audio signal. This usually requires another op amp

in which to mix the signals. With the NE578, however, the DTMF tones can be mixed internally on the compressor side. The DTMF signal is also compressed with the audio signal and ready for data transmission Figure 2 shows that the summing of signals � can be done at Pin 9 with R4 and C10. If amplification is not needed, then a 1Ok resistor is a recommended value for R4. In addition the summing amplifiers are capable of driving 600'2 loads.
THE NE577 AND NE578 AS A DUAL EXPANDOR The compressor side can actually be configured as an expandor for both the NE577 and NE578. Figure 20 shows how this can be done. Because Pin 9 of the NE578 is available to the designer, the compressor side can not only be configured as an expandor, but as an expandor with summing capabilities.
OPERATING AT 1.8V The NE577 and NE578 can operate at 1.BV. However, turning on the part at a Vee of 1.BV requires two external resistors to bring VReF to half Vee. One resistor connects between Vee and VReF; the other connects from VReF to ground. A typical value for these external resistors is approximately 20k. A lower value ~an be used, but power consumption will increase.
There are two cases where the external
resistors can be eliminated.

Case 1: NE578 only
With the power supply at 1.SV and Pin 8 active low (power-down/mute activated), turn on the part. Then disable Pin 8 to power up.
Case 2: NE577 or NE578
During normal operations, the NE577 and NE578 can operate from at least a 2V battery. If the battery voltage drops to 1.SV, these parts will still continue to function.
NE577 AND NE578 DEMO BOARDS Figures 21 shows the DIP package layout for the NE577 and NE578 demo boards, respectively. Figures 22 shows the SO layout for the NE577 and NE578 demo boards respectively. The layouts are configured such that R1, R2, R3, and Rx can be removed and replaced easily. A switch is also available to change the operating mode of the compressor to an ALC configuration and vice versa (position the switch to the right for ALC mode).
When the compressor side is being evaluated, disconnect Rx completely from the socket on the demo boards. Rx should only be used when the compandor is being used forALC.
For the NE578 demo board, two extra post are available. One is for power-down; the other is for summing external signals. To power-down, simply ground this post. To sum signals, connect the external signal to the proper post.

+20dB .!.1V?HllL--

NORx

Ayc1

2lllog ( AC lnpMt lewl VRMS ) �mB AC oNlpMI lewl VRMS

Avc1
+20dBl--'1c:.VR!!!MS""--~
I I Rx= 7151<

Av=1

OdB
AC oulpUI level delennlned by Eq. 1, Valuee In the example give 1oomvRMS output.

Av�1

AVMAX

-34dB 2mV MS INPUT OF ALC

OUTPUT OF ALC

Figure 12. Dynamic Range of NE577 ALC Demonstration Board Without Rx

10llmVRMS

I I

I I

1GmVRMS AVMAX =10

I I

lmVRMS _ ~~~ ~ _//

I
4mVRMS -~~~~__/ Av�1

80mVRMS
- - - - - 40mVRMS

INPUT OF ALC

OUTPUT OF ALC

Figure 13. Dynamic Range of NE577 ALC Demo Board with Rx= 7151<'2

September 1990

236

Philips Semiconductors-Signetics RF Communications
Companding with the NE577 and NE578

Application Note
AN1762

-B 1V

AvMAx=10

+20dB 1U!!!ll!UlllSL-,

NO Rx

Rx� 84.3k Rx= 136k
Rx=715k

AvMAx=2 AVMAX=10

100mVRMS

NO Rx

INPUTOFALC

OUTPUT OF ALC

Figure 14. Dynamic Range of NESn ALC Demo Board with Different Rx Values

NO Rx

OdB Av=1

Ay>1

AvMAX

-30dB INPUTOFALC

OUTPUT OF ALC

Figure 15. NESn ALC: AC Output Level= 10mVRMS

NORx

318mVRMS OdB

AVMAX
INPUT OF ALC OUTPUT OF ALC Figure 16. NESn ALC: AC Output Level= 100mVRMS

OUTPUT OF ALC Fl ure 17. NE577 ALC: AC Out ut Level= 316mV

-44dB

Ay>1 &mV
INPUTOFALC

AvMAX OUTPUT OF ALC

Figure 18. NE577 ALC: AC Output Level= 1VRMS

September 1990

237

r----,
I I I I I IL _ _ _ _ .J

NE57B

LEVEL AT PIN B SHOULD BE OPEN COLLECTOR TTL LEVELS
THE REASON FOR OPEN COLLECTOR CONAGURATION IS TO ENSURE:
1) PIN BIS FLOATING WHEN POWER-DOWN/MUTE IS NOT IMPLEMENTED
2) PIN B IS GROUNDED WHEN POWER-DOWN/MUTE IS ACTIVE

Figure 19. Proper Use of NE578 Pin 8

Philips Semiconductors-Signetics RF Communications
Companding with the NE577 and NE578
RDC1 30k
13 NO CONNECTION
RDC3 10lc

Application Note
AN1762
Ct 10pf

R1a 10k
I 2C.B2pF
NO CONNECTION

a. NE577
RDC1 30k

RDC2 llClk

NO CONNECTION
RDC3 10k
4.llk

Ct 10pF
HJ-------1E---o

REXT 2k
b. NE578
Fl ure 20. Ex andor Confl uratlon for the Com ressor Side

September 1990

238

Philips Semiconductors-Signetics RF Communications
Companding with the NE577 and NE578

Application Note
AN1762

~ SIGNETICS ~ NE577

EXP IN

~ R1

-f~ ~

vcc

GND

Cbp

-lf-

COMP IN

.J....C8

T .J....

GND C2 -7f-

.J....TC7

C&T

GND

R3

-A.Mr-

C4+

~ + -)Cf-3

~ R2

C10 +CS-A.Mr-

-lf-

Rx

EXP OUT

C9 ASPG # 1sooo COMP OUT

NESn DIP Top Silk Screen

......

0

�� ��

Top View
.: �� :
��

NE5nN

���������

~ SIGNETICS vcc

GND

~ NE578

EXP IN C1 ~ R1 -7f-
GND

Cbp-lf-

COMP IN

.TJ.... C8 .J....

.J.... TC7

csT

GND

R3

-A.Mr-

EXP PWR
OUT ON

_t_

S1

-r-CS

Rx

+ -A.Mr-
c1ff--A.MCr9- R4

SUM

-7f- COMP

IN

C10 OUT

NE578 DIP Top Silk Screen

0 ...... 0
01 . 0 \t:;.;\I0 C!) �

����
00 000 \I:;.;\I

�"�..�.�.�

0 0

0 0

. . . .

. . .� @ ( ! )

0

0 0

..��....

r.v::v":\ � �

0 ~ ~ ~ \!I

.�~

~
0

80 0 00 ~0803 0 �.0

Top View
.:� �:
� �

:...
��

.:.�.�:

September 1990

Bottom View
Bottom View Figure 21. NE577 and NE578 DIP Application Board Layout
239

Philips Semiconductors-Signetics RF Communications
Companding with the NE577 and NE578

Apj>llcatton Note
AN1762

ie SIGNETICS vcc

GND

NE577

~ SIGNETICS vcc

GND

~ NE578

EXP IN C1+ R1 Cbp C8 r:7 COMP IN

EXP IN

C1 + R1

~p

ca C7

COMP IN

C6

C6

J ~ I

GND C2

+

+ +

++ +

Rx

+CS

R3

C2 +
+ +

:& Rx + R3

C3

R2 C10

C4

c9

GND

EXP OUT ASPG# 15001 COMP OUT

NE577 SO Top Siik Screen

GND C3
EXP

R2

R4

C4 C11

+C1o +

GND
C9
CON!~

OUT

OU1

PW.RON ASPG# 15001 SUM IN

.:��:
� �

: .: NE578 SO Top Siik Screen �� ��

.....
�� ��
0
���������
0

Top View

0

NE577D

0

0
Bottom View

..... 0 ����

Top View

NE578D

0
......

0......

����

����

GXOO>

0

0

0 0

Bottom View

September 1990

Figure 22. NESn and NE578 SO Application Board Layout 240

Slgnetlcs RF Communications

Section 3 FM IF Systems

INDEX

FM/IF Systems Selector Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

MC3361

Low-power FM IF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

NE/SA604A High performance low power FM IF system . . . . . . . . . . . . . . . . . 246

NE/SA614A Low power FM IF system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256

AN1991

Audio decibel level detector with meter driver . . . . . . . . . . . . . . . 266

AN1993

!"ligh sensitiyity !1PPlications of low-power RF/IF integrated c1rcu1ts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

NE/SA605 High performance low power mixer FM IF system . . . . . . . . . . . . 280

NE/SA605 High performance low power mixer FM IF system in shrink small outline package (SSOP) . . . . . . . . . . . . . . . . . . . . 290

NE/SA615 High performance low power mixer FM IF system . . . . . . . . . . . . 298

NE/SA615 High ~rformance low power mixer FM IF system in shnnk small ouUine package (SSOP) . . . . . . . . . . . . . . . . . . . . 308

AN1994

Reviewing key areas when designing with the NE605 . . . . . . . . . 316

AN1995

Evaluating the NE605 SO and SSOP demo-board . . . . . . . . . . . 336

NE/SA606 Low-voltage high performance mixer FM IF system ........... 346

NE/SA616 Low-voltage high performance mixer FM IF system ........... 362

NE/SA607 Low voltage high performance mixer FM IF system . . . . . . . . . . . 378

NE/SA617 Low-voltage high performance mixer FM IF system ........... 392

TDA1576T FM/IF amplifier/demodulator circuit . . . . . . . . . . . . . . . . . . . . . . . 406

AN192

A complete FM radio on a chip . . . . . . . . . . . . . . . . . . . . . . . . . . . 414

AN193

TDA7000 for narrowband FM reception . . . . . . . . . . . . . . . . . . . . 427

TDA7000 Single-chip FM radio circuit

442

TDA7021T Single-chip FM radio circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449

2R

FM IF SYSTEMS FAMILY OVERVIEW

~

3

~ ~

NE604A NE614A NE605

NE615

NE606

NE616

NE607 NE617

3
c:;,

Yee

4.5-BV

4.5-BV

4.5-BV

4.5-BV

2.7-7V

2.7-7V

2.7-7V

2.7-7V

i

Ice

3.3mA@6V 3.3mA@6V 5.7mA@6V 5.7mA@6V

3.5mA@3V

3.5mA@3V

3.5mA@3V 3.5mA@3V

:;,

Cll

Number of Pins

16

16

20

20

20

20

20

20

Package

DIP,SO

DIP,SO DIP, SO, SSOP DIP, SO, SSOP DIP, SO, SSOP DIP, SO, SSOP DIP, SO, SSOP DIP, SO, SSOP

l~ut Frequency ( ax.)

Same as IF

Same as IF

500MHz

500MHz

150MHz

150MHz

150MHz

150MHz

Sensitivity Input Pin
Rin

0.22�V 1.6kn

0.22�V 1.Skn

0.22�V 4.n

0.22�V 4.7kn

0.31�V SkQ

0.31�V SkQ

0.31�V SkQ

0.31�V 8k'2

Mixer Conversion

NIA

NIA

13dB

13dB

Gain

17dB

17dB

17dB

17dB

Input 3rd Order

NIA

Intercept*

NIA

+4dBm

+4dBm

-10dBm

-10dBm

-10dBm

-10dBm

~

Process ft

IF Frequency

(Max.)

SGHz 25MHz

SGHz 25MHz

SGHz 25MHz

SGHz 25MHz

SGHz 2MHz

SGHz 2MHz

SGHz 2MHz

SGHz 2MHz

RSSI Range

90dB

80dB

90dB

SOdB

90dB

RSSI Temp Comp

YES

YES

YES

YES

YES

Conver Stages

NIA

NIA

Single

Single

Single

Features

-High Sensitivity
-High IF Frequency

-High Sensitivity

-High Sensitivity

-High IF

- High Input/IF

Frequency

Frequency

- Relaxed 604A -SSOP20

-High Sensitivity
- High Input/IF Frequency
-SSOP20 - Relaxed 605

-Low Power
-Audio Op-amp on output
- RSSI Op-amp on output
-SSOP20

Applications

-Canconttie with NE602A to produce a single convar mceiVer

-Can corrbina wilhNE612A to produce a single conver receiver

-Cellular
- High Perlormanca
recerv...
- Industry 51andanl

-Celular -Cordless Phone

--�- -Pc<lableCellular
-Conness Phones

SOdB
YES
Single
-Low Power -Audio Op-amp
on output - RSSI Op-amp
on output -SSOP20 - Relaxed 606
---- PortableCellular
-~Phones

90dB

80dB

YES

YES

Single

Single

-Low Power -Low Power

-Audio Op-amp -Audio Op-amp

on output

on output

-~~ency

-Frequency checi<

- Buffered RSSI - Buffered RSSI

- Differential - Differential

limiter output Hmiter output

-SSOP20

-SSOP20

- Relaxed 607

-PortableCellular AMPS/TACS NAMPS/NTACS
Portabloecelver Coidless Phone

- Portable Cellular AMPS/TACS NAMPS/NTACS
Po..- Receiver Coidless Phone

*Note - son Source

1e5n�
:;,
~
Cll
s"T:1
:;:;;;;; "T1
~.e.n.
Cl)
e3n
-en
CD
a.0C.D.
"ca:
CD

Slgnetlcs RF Communications
Low-power FM IF

Product specification
MC3361

DESCRIPTION
The MC3361 is a monolithic low-power FM IF signal processing system consisting of an oscillator, mixer, limiting amplifier, quadrature detector, filter amplifier, squelch, scan control and mute switch. It is intended for use in narrow band FM dual conversion communications equipment. The MC3361 is available in a 16-lead, dual-in-line plastic package and 16-lead SOL (surface-mounted miniature package).

FEATURES
� 2.0V to 8.0V operation � Low current: 4.2mA typ at VCC=4.0VDC � Excellent sensitivity: 2.0�V for --3dB
limiting typ � Low external parts count � Operation to 60MHz

APPLICATIONS
� Cordless telephone � Narrow band receivers � Remote control

PIN CONFIGURATION
0 1 and N Package

CRYoSsTcA.L{ 1
MIXER OUTPUT
Vee 4
LIMITER INPUT
DECOUPLING LIMITER OUTPUT QUAD 8 INPUT

RF INPUT
GND
AUDIO MUTE SCAN CONTROL SQUELCH INPUT ALTER OUTPUT ALTER INPUT
DE MOD OUTPUT

NOTE: 1. Avallable In 16-pin SOL package.

ORDERING INFORMATION
DESCRIPTION 16-Pin Plastic DIP 16-Pin Plastic SOL

TEMPERATURE RANGE -40 to +85�C -40 to +85�C

ORDER CODE MC3361N MC3361D

BLOCK DIAGRAM

MIXER INPUT
16

GND

SCAN SQUELCH ALTER

MUTE CONTROL

IN

OUTPUT

ALTER RECOVERED INPUT AUDIO

CRoYsScT.AL

DECOUPLING

March 28, 1988

243

853-1190 92746

Signetics RF Communications
Low-power FM IF

Product specification
MC3361

ABSOLUTE MAXIMUM RATINGS TA= 25�C unless otherwise noted.

SYMBOL

PARAMETER

Vcc(Max)

Power supply voltage

Vee

Generating supply voltage range

Detector input voltage

Via

Input voltage (Vee;,4.0V)

V14

Mute function

TJ

Junction temperature

TA

Tsra

Storage temperature range

PIN

RATING

4

10

4

2.0to 8.0

8

1.0

16

1.0

14

--0.5 to 5.0

150

-40 to +85

~to+150

AC AND DC ELECTRICAL CHARACTERISTICS Vee= 4.0Voe. 10 = 10.7MHz, di= +3.0kHz, IJVioo= 1.0kHz, TA= 25�C unless otherwise noted.

PARAMETER

PIN

TEST CONDITIONS

Drain current (no signal) squelch off squelch on
Input limiting voltage Detector output voltage Detector output impedance Recovered audio output voltage Filter gain (1 OkHz) Filter output voltage Trigger hysteresis Mute function low Mute function high Scan function low (mute off) Scan function high (mute on) Mixer conversion gain Mixer input resistance Mixer input capacitance

4

16

-,'3.0dB limiting

9

9

100

V1N=1.0mVRMS

11

14

14

13

13

V12=GND

3

16

16

LIMITS

Min

Typ

Max

4.2

7.0

5.4

2.0

6.0

2.0

450

150

270

40

46

1.7

50

10

10

0.5

27 3.6 2.2

UNIT Voe Voe Vp.f' VRMS VpK
�c �c �c
UNIT
mA
�V Voe n mVRMS dB Voe mV n Mn Voe Voe dB kn pF

March 28, 1988

244

Signetics RF Communications
Low-power FM IF
TEST CIRCUIT Yee
t--...--0 SCAN CONTROL
10k
t - - - - o SQ SW INPUT
QUAD COIL TOKOTYPE RMS-2A6597HM

Product specification
MC3361

March 28, 1988

245

Slgnetics RF Communications
High performance low power FM IF system

Product specification
NE/SA604A

DESCRIPTION
The NE/SA604A is an improved monolithic low-power FM IF system incorporating two limiting intermediate frequency amplifiers, quadrature detector, muting, logarithmic received signal strength indicator, and voltage regulator. The NE/SA604A features higher IF bandwidth (25MHz) and temperature compensated RSSI and limiters permitting higher performance application compared with the NE/SA604. The NE/SA604A is available in a 16-lead dual-in-line plastic and 16-lead SO (surface-mounted miniature) package.

APPLICATIONS
�Cellular radio FM IF �High performance communications
receivers �Intermediate frequency amplification and
detection up to 25MHz �RF level meter
�Spectrum analyzer �Instrumentation �FSK and ASK data receivers

FEATURES
�Low power consumption: 3.3mA typical
�Temperature compensated logarithmic Received Signal Strength Indicator (RSSI) with a dynamic range in excess of 90dB
�Two audio outputs - muted and unmuted
�Low external component count; suitable for crystal/ceramic filters
�Excellent sensitivity: 1.5�V across input
pins (D.22�V into son matching network)
for 12dB SI NAD (Signal to Noise and Distortion ratio) at 455kHz
�SA604A meets cellular radio specifications

PIN CONFIGURATION

D and N Packages

IFAMP DECOUPLING
RSSI OUTPUT 5
MUTM�~~~ 6 UNMUTM�~~~ 7
QUADRATURE a INPUT

IFAMP INPUT
IFAMP DECOUPLING IFAMP OUTPUT
GND
LIMITER INPUT LIMITER DECOUPLIN
LIMITER DECOUPLING

ORDERING INFORMATION
DESCRIPTION 16-Pin Plastic DIP 16-Pin Plastic SO (Surface-mount) 16-Pin Plastic DIP 16-Pin Plastic SO (Surface-mount)

TEMPERATURE RANGE 0 to +70'C 0 to +70'C -40 to +85'C -40 to +85'C

ORDER CODE NE604AN NE604AD SA604AN SA604AD

ABSOLUTE MAXIMUM RATINGS

SYMBOL

PARAMETER

Vee Single supply voltage

Tsrn Storage tern perature range

TA

Operating ambient temperature range NE604A SA604A

8JA

Thermal impedance

D package N package

RATING
9
-65to +150
Oto +70 -40 to +85
90 75

UNITS
v
'C
'C 'C
'CfW 'CfW

May 1, 1990

246

853-1431 99620

Signetics RF Communications
High performance low power FM IF system

Product specification
NE/SA604A

BLOCK DIAGRAM

16

15

14

13

12

11

10

9

VOLTAGE REGULATOR

GND

2

3

4

5

6

7

8

DC ELECTRICAL CHARACTERISTICS Vee= +OV, TA= 25�C; unless otherwise stated.

SYMBOL

PARAMETER

TEST CONDITIONS

Vee Power supply voltage range
Ice DC current drain
Mute switch input threshold (ON) (OFF)

LIMITS

NE604A

SA604A

MIN TYP MAX MIN TYP MAX

4.5

8.0 4.5

8.0

2.5

3.3

4.0

2.5

3.3

4.0

1.7

1.7

1.0

1.0

UNITS
v
mA
v v

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High performance low power FM IF system

Product specification
NE/SA604A

AC ELECTRICAL CHARACTERISTICS
Typical reading at TA= 25�C; Vee= �6V, unless otherwise stated. IF frequency = 455kHz; IF level= -47dBm; FM modulation= 1kHz with �8kHz peak deviation. Audio output with C-message weighted filter and de-emphasis capacitor. Test circuit Figure 1. The parameters listed below are tested using automatic test equipment to assure consistent electrical characterristics. The limits do not represent the ultimate performance limits of the device. Use of an optimized RF layout will improve many of the listed parameters.
LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

NE604A

SA604A

UNITS

MIN

TYP MAX MIN

TYP MAX

Input limiting -3dB

Test at Pin 16

-92

-92

dBm/500

AM rejection

80%AM 1kHz

30

34

30

34

dB

THD

Recovered audio level Recovered audio level Total harmonic distortion

15nF de-emphasis 1SOpF de-emphasis

110

175

250

80

175

260

mVRMS

530

530

mVRMS

-35

-42

-34

-42

dB

SIN Signal-to-noise ratio

No modulation for noise

73

73

dB

RSSI output1 RSSI range

RF level= -118dBm RF level = -68dBm RF level = -1 BdBm ~ = 100k (Pin 5)

0

160

550

0

160

650

mV

2.0

2.65

3.0

1.9

2.65

3.1

v

4.1

4.85

5.5

4.0

4.85

5.6

v

90

90

dB

RSSI accuracy

~ = 100k (Pin 5)

�1.5

�1.5

dB

IF input impedance

1.4

1.6

1.4

1.6

kn

IF output impedance

0.85

1.0

0.85

1.0

kn

Limiter input impedance

1.4

1.6

1.4

1.6

kn

Unmuted audio output resistance

58

58

kn

Muted audio output resistance

58

58

kn

NOTE:

1. NE604 data sheets refer to power at 500 input termination; about 21dB less power actually enters the internal 1.5k input.

NE604 (50)

NE604A (1.5k)/NE605 (1.5k

-97dBm

-118dBm

-47dBm

-68dBm

+3dBm

-18dBm

The NE605 and NE604A are both derived from the same basic die. The NE605 performance plots are directly applicable to the NE604A.

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248

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High performance low power FM IF system

Product specification
NE/SA604A

NE604A

~r

MUTE INPUT

Ct 10GnF + 80 -20% 63V K1~V Ceranic C2 100nF+10%50V C3 tOOnF ,.t0% SOY

C4 100nF +10% 50V

cs tOOnF,.t0% SOY

C& tOpF '�2% tOOY NPO Ceramic

C7 100nF .:t.10% SOY

C8 100nF �10% SOY

CB t5nF '�t0% SOY

CtO tSOpF ,.2% tOOY Nt500 Ceramic

Ctt ii,~~5'{.~:J!l.~P Ceramic
Ct2

Ft 455kHz Ceramic Riter Murata SFG455A3

F2 Rt

ml'1'N."t~\JUMetal Rim

R2 1500.G .;t1% 1/4W Metal Film

R3 1500n .:t5% 118W Carbon Compoaitlon

R4 100kn .:1:.1% 1/4W Metal Film

DATA OUTPUT

(~;")'~�'

>SI
~0

0
(~;")'~�' c~0

May 1, 1990

Figure 1. NE/SA604A Test Circuit 249

Signetics RF Communications
High performance low power FM IF system

Product specification
NE/SA604A

VOLTAGE/ CURRENT CONVERTER

Vee
GND
0

Vee
0
Figure 2. Equivalent Circuit

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Signetics RF Communications
High performance low power FM IF system

Product specification
NE/SA604A

NE602

NE604A

455kHz

r -<-l=2-0,

I

I

I

I

I

I

L I~1~1

P 1 47pf

o.20.d2~1H

F
=

I 100nF

MUTE

RSSI

C-MSG
J_ ALTER
I

AUDIO OUT

NE604A IF INPUT (�V) (1500'2)

10

100

1k

10k 100k

_.,:;;;=-- ,,,.------.!~1.2__.__

(_,,.7 /

~7/

4V

3V

CIRCUIT DESCRIPTION
The NEISA604A Is a very high gain, high frequency device. Correct operation Is not possible if good RF layout and gain stage practices are not used. The NEISA604A cannot be evaluated independent of circuit, components, and board layout. A physical layout which correlates to the electrical limits is shown in Figure 1. This configuration can be used as the basis for production layout.
The NE/SA604A is an IF signal processing system suitable for IF frequencies as high as 21.4MHz. The device consists of two limiting amplifiers, quadrature detector, direct audio output, muted audio output, and signal strength indicator (with output characteristic). The sub-systems are shown in Figure 2. A typical application with 45MHz input and 455kHz IF is shown in Figure 3.

2V AM(80%MOD)
1V NOISE

-120 -100 -80

-60

-40

NE602 RF INPUT (dBm) (500)

lication Cellular Radio 45MHz to 455kHz

IF Amplifiers

established for each stage by tapping one of

The IF amplifier section consists of two loglimiting stages. The first consists of two differential amplifiers with 39dB of gain and a

the feedback resistors 1.6kQ from the input. This requires one additional decoupling capacitor from the tap point to ground.

small signal bandwidth of 41 MHz (when

driven from a 50Q source). The output of the first limiter is a low impedance emitter follower with 1kQ of equivalent series resistance. The second limiting stage consists of three differential amplifiers with a gain of 62dB and a small signal AC

bandwidth of 28MHz. The outputs of the final differential stage are buffered to the internal quadrature detector. One of the outputs is

Fi ure 4. First Limiter Blas

available at Pin 9 to drive an external quadrature capacitor and UC quadrature tank.
Both of the limiting amplifier stages are DC biased using feedback. The buffered output of the final differential amplifier is fed back to the input through 42kQ resistors. As shown

Because of the very high gain, bandwidth and input impedance of the limiters, there is a very real potential for instability at IF frequencies above 455kHz. The basic phenomenon is shown in Figure 6. Distributed feedback (capacitance, inductance and radiated fields)

in Figure 2, the input impedance is

May 1, 1990

251

Signetics RF Communications
High performance low power FM IF system

Product specification
NE/SA604A

42k

1----------c::::J---------,

r--c=J---ptCJ~

I

I

I

Figure 5. Second Limiter and Quadrature Detector

Figure 6. Feedback Paths

BPF

HIGH IMPEDANCE 1 - - - - - - ,

I

I

HIGH 1 IMPEDANCE - - - - - ,

I

I

I

I

I

I

LOW IMPEDANCE

I L__

..:J

\

L----~-~-------~

Figure 7. Terminating High Impedance Filters with Transformation to Low Impedance

BPF

Figure 7. Low Impedance Termination and Gain Reduction Figure 7. Practical Termination
430

430
�

NE604A

Figure 8. Crystal Input Filter with Ceramic Interstage Filter

forms a divider from the output of the limiters back to the inputs (including RF input). If this feedback divider does not cause attenuation greater than the gain of the foiward path, then oscillation or low level regeneration is likely. If regeneration occurs, two symptoms may be present: (1)The RSSI output will be high with no signal input (should nominally be 250mV or lower). and (2) the demodulated

output will demonstrate a threshold. Above a certain input level, the limited signal will begin to dominate the regeneration, and the demodulator will begin to operate in a "normal" manner.
There are three primary ways to deal with regeneration: (1) Minimize the feedback by gain stage isolation, (2) lower the stage input

impedances, thus increasing the feedback attenuation factor, and (3) reduce the gain. Gain reduction can effectively be accomplished by adding attenuation between stages. This can also lower the input impedance if well planned. Examples of impedance/gain adjustment are shown in

May 1, 1990

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Signetics RF Communications
High performance low power FM IF system

Product specification
NE/SA604A

Figure 7. Reduced gain will result in reduced limiting sensitivity.
A feature of the NE604A IF amplifiers, which is not specified, is low phase shift. The NE604A is fabricated with a 10GHz process with very small collector capacitance. It is advantageous in some applications that the phase shift changes only a few degrees over a wide range of signal input amplitudes. Additional information will be provided in the upcoming product specification (this is a preliminary specification) when characterization is complete.
Stability Considerations
The high gain and bandwidth of the NE604A in combination with its very low currents permit circuit implementation with superior performance. However, stability must be maintained and, to do that, every possible feedback mechanism must be addressed. These mechanisms are: 1) Supply lines and ground, 2) stray layout inductances and capacitances, 3) radiated fields, and 4) phase shift. As the system IF increases, so must the attention to fields and strays. However, ground and supply loops cannot be overlooked, especially at lower frequencies. Even at 455kHz, using the test layout in Figure 1, instability will occur if the supply line is not decoupled with two high quality RF capacitors, a 0.1 �F monolithic right at the Vee pin, and a 6.8�F tantalum on the supply line. An electrolytic is not an adequate substitute. At 10.7MHz, a 1�F tantalum has proven acceptable with this layout. Every layout must be evaluated on its own merit, but don't underestimate the importance of good supply bypass.
At 455kHz, if the layout of Figure 1 or one substantially similar is used, it is possible to directly connect ceramic filters to the input and between limiter stages with no special consideration. At frequencies above 2MHz, some input impedance reduction is usually necessary. Figure 7 demonstrates a practical means.
As illustrated in Figure 8, 4300 external resistors are applied in parallel to the internal 1.6kCl load resistors, thus presenting approximately 3300 to the filters. The input filter is a crystal type for narrowband selectivity. The filter is terminated with a tank which transforms to 3300. The interstage filter is a ceramic type which doesn't contribute to system selectivity, but does suppress wideband noise and stray signal pickup. In wideband 10.7MHz IFs the input filter can also be ceramic, direcdy connected to Pin 16.
In some products it may be impractical to utilize shielding, but this mechanism may be

appropriate to 10.7MHz and 21.4MHz IF. One of the benefits of low current is lower radiated field strength, but lower does not mean non-existent. A spectrum analyzer with an active probe will clearly show IF energy with the probe held in the proximity of the second limiter output or quadrature coil. No specific recommendations are provided, but mechanical shielding should be considered if layout, bypass, and input impedance reduction do not solve a stubborn instability.
The final stability consideration is phase shift. The phase shift of the limiters is very low, but there is phase shift contribution from the quadrature tank and the filters. Most filters demonstrate a large phase shift across their passband (especially at the edges). If the quadrature detector is tuned to the edge of the filter passband, the combined filter and quadrature phase shift can aggravate stability. This is not usually a problem, but should be kept in mind.
Quadrature Detector
Figure 5 shows an equivalent circuit of the NE604A quadrature detector. It is a multiplier cell similar to a mixer stage. Instead of mixing two different frequencies, it mixes two signals of common frequency but different phase. Internal to the device, a constant amplitude (limited) signal is differentially applied to the lower port of the multiplier. The same signal is applied single-ended to an
external capacitor at Pin 9. There is a 90� phase shift across the plates of this capacitor, with the phase shifted signal applied to the upper port of the multiplier at Pin 8. A quadrature tank (parallel UC network) permits frequency selective phase shifting at the IF frequency. This quadrature tank must be returned to ground through a DC blocking capacitor.
The loaded Q of the quadrature tank impacts three fundamental aspects of the detector: Distortion, maximum modulated peak deviation, and audio output amplitude. Typical quadrature curves are illustrated in Figure 10. The phase angle translates to a shift in the multiplier output voltage.
Thus a small deviation gives a large output
a with a high tank. However, as the
deviation from resonance increases, the nonlinearity of the curve increases (distortion), and, with too much deviation, the signal will be outside the quadrature region (limiting the peak deviation which can be demodulated). If the same peak deviation is applied to a
a lower tank, the deviation will remain in a
region of the curve which is more linear (less distortion), but creates a smaller phase angle (smaller output amplitude). Thus the 0 of the quadrature tank must be tailored to the

design. Basic equations and an example for
a determining are shown below. This
explanation includes first-order effects only.
Frequency Discriminator Design Equations for NE604A

r

Flgure9.

(1a)

Vo=~�

1

� V1N

Cp+Cs

ro1 (ro1}2

1 + 01S+ S

where ro1=

1

(1b)

-.,/ L(Cp + Cs)

01=R(Cp+Cs)"'1

(1c)

From the above equation, the phase shift between nodes 1 and 2, or the phase across Cs will be:
(2)

Figure 1Ois the plot of cp vs. ( ~ }
It is notable that at ro = "'1 � the phase shift is
"% and the response is close to a straight
&cp 201 line with a slope of ~ro = ro1 The signal Vo would have a phase shift of
[-% _~1 ro] with respect to the V1N�

lfV1N =A Sin rot~ Vo =A

(3)

~ Sin [rot+

2

_

201 ro1

roj l

Multiplying the two signals in the mixer, and low pass filtering yields:

V1N �Vo= A2 Sin cot

(4)

J Sin Lf rot +

~
2

-

201 ro1

ro1

after low pass filtering

~ Vour = -1.. A2 Cos[~ 201

(5)

2

2 - ro1

=-1.. A2 Sin( 201) ro

2

ro1

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Signetics .RF Communications
High performance low power FM IF system

Product specification
NE/SA604A

Vour cc 201 :1 = [ 201 { ro1 ;16.ro ~ (6) For 020011ro � 27t

Which is discriminated FM output. (Note that
6.ro is the deviation frequency from the carrier ro1.

Rel. Krauss, Raab, Bastian; Solid State Radio Eng.; Wiley, 1980, p. 311. Example: At 455kHz IF, with �5kHz FM deviation. The maximum normalized frequency will be

45 455 +5kHz 5

= 1.01 o or 0.990

Go to the I vs. normalized frequency curves
(Figure 10) and draw a vertical straight line at
rroo1 = 1.01.

The curves with Q = 100, Q = 40 are not
a linear, but = 20 and less shows better
linearity for this application. Too small Q decreases the amplitude of the discriminated
FM signal. (Eq. 6) => Choose a Q = 20
The internal R of the 604A is 40k. From Eq. 1c, and then 1b, it results that
Cp +Cs= 174pF and L = 0.7mH.
A more exact analysis including the source resistance of the previous stage shows that there is a series and a parallel resonance in the phase detector tank. To make the parallel and series resonances close, and to get maximum attenuation of higher harmonics at 455kHz IF, we have found that a Cs= 10pF and Cp = 164pF (commercial values of 150pF or 1SOpF may be practical), will give the best results. A variable inductor which can be adjusted around 0.7mH should be chosen and optimized for minimum distortion. (For 10.7MHz, a value of Cs= 1pF is recommended.)
Audio Outputs
Two audio outputs are provided. Both are
PNP current-to-voltage converters with 55kQ nominal internal loads. The unmuted output is always active to permit the use of signaling tones in systems such as cellular radio. The other output can be muted with 70dB typical attenuation. The two outputs have an
internal 180� phase difference.

The nominal frequency response of the audio outputs is 300.kHz. this response can be increased with the addition of external resistors from the output pins to ground in parallel with the internal 55k resistors, thus lowering the output time constant. Singe the output structure is a current-to-voltage converter (current is driven into the resistance, creating a voltage drop), adding external parallel resistance also has the effect of lowering the output audio amplitude and DC level.
This technique of audio bandwidth expansion can be effective in many applications such as SCA receivers and data transceivers.
Because the two outputs have a 180� phase relationship, FSK demodulation can be accomplished by applying the two output differentially across the inputs of an op amp or comparator. Once the threshold of the reference frequency (or �no-signal" condition) has been established, the two outputs will shift in opposite directions (higher or lower output voltage) as the input frequency shifts. The output of the comparator will be logic output. The choice of op amp or comparator will depend on the data rate. With high IF frequency (10MHz and above), and wide IF bandwidth (L/C filters) data rates in excess of 4Mbaud are possible.
RSSI
The "received signal strength indicator", or RSSI, of the NE604A demonstrates monotonic logarithmic output over a range of 90dB. The signal strength output is derived from the summed stage currents in the limiting amplifiers. It is essentially independent of the IF frequency. Thus, unfiltered signals at the limiter inputs, spurious products, or regenerated signals will manifest themselves as RSSI outputs. An RSSI output of greater than 250mV with no signal (or a very small signal) applied, is an indication of possible regeneration or oscillation.
In order to achieve optimum RSSI linearity, there must be a 12dB insertion loss between the first and secon.d limiting amplifiers. With a typical 455kHz ceramic filter, there is a nominal 4dB insertion loss in the filter. An

additional 6dB is lost in the interface between the filter and the input of the second limiter. A small amount of additional loss must be introduced with a typical ceramic filter. In the test circuit used for cellular radio applications (Figure 3) the optimum linearity was achieved with a 5.1 kQ resistor from the output of the first limiter (Pin 14) to the input of the interstage filter. With this resistor from Pin 14 to the filter, sensitivity of 0.25�V for 12dB
SINAD was achieved. With the 3.6kQ
resistor, sensitivity was optimized at 0.22�V for 12dB SINAD with minor change in the RSSI linearity.
Any application which requires optimized RSSI linearity, such as spectrum analyzers, cellular radio, and certain types of telemetry, will require careful attention to limiter interstage component selection. This will be especially true with high IF frequencies which require insertion loss or impedance reduction for stability.
At low frequencies the RSSI makes an excellent logarithmic AC voltmeter.
For data applications the RSSI is effective as an amplitude shift keyed (ASK) data slicer. If a comparator is applied to the RSSI and the threshold set slightly above the no signal level, when an in-band signal is received the comparator will be sliced. Unlike FSK demodulation, the maximum data rate is somewhat limited. An internal capacitor limits the RSSI frequency response to about 100kHz. At high data rates the rise and fall times will not be symmetrical.
The RSSI output is a current-to-voltage converter similar to the audio outputs. However, an external resistor is required. With a 91 kQ resistor, the output characteristic is 0.5V for a 1OdB change in the input amplitude.
Additional Circuitry
Internal to the NE604A are voltage and current regulators which have been temperature compensated to maintain the performance of the device over a wide temperature range. These regulators are not accessible to the user.

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Sign~tics RF Communications
High performance low power FM IF system

Product specification
NE/SA604A

2.00
.. 175 150 125 ,.., 75 50 25

0.95

0.975

1.0

1.025

1.05

ro

L\.ro

Figure 10. Phase vs Normalized IF Frequency -;;;;- = 1 + -;;;;-

May 1, 1990

255

Slgnetlcs RF Communications
Low power FM IF system

Product specification
NE/SA614A

DESCRIPTION
The NE/SA614A is an improved monolithic low-power FM IF system incorporating two limiting intermediate frequency amplifiers, quadrature detector, muting, logarithmic received signal strength indicator, and voltage regulator. The NE/SA614A features higher IF bandwidth (25MHz) and temperature compensated RSSI and limiters permitting higher performance application compared with the NE/SA604. The NE/SA614A is available in a 16-lead dual-in-line plastic and 16-lead SO (surface-mounted miniature) package.

FEATURES
�Low power consumption: 3.3mA typical
�Temperature compensated logarithmic Received Signal Strength Indicator (RSSI) with a dynamic range in excess of 90dB
�Two audio outputs - muted and unmuted
�Low external component count; suitable for crystal/ceramic filters
�Excellent sensitivity: 1.5�V across input pins (0.22�V into 50Q matching network) for 12dB SINAD (Signal to Noise and Distortion ratio) at 455kHz
�SA614A meets cellular radio specifications

PIN CONFIGURATION
D and N Packages
IFAMP DECOUPLING
GND 2

RSSI OUTPUT 5
MUTM�~i~ 6 UNMU~~�f/i~ 7 QUADRATURE a
INPUT

12 ~~:l"fR
LIMITER DECOUPLING LIMITER DECOUPLING
9 LIMITER

APPLICATIONS
�Cellular radio FM IF �High performance communications
receivers �Intermediate frequency amplification and
detection up to 25MHz �RF level meter
�Spectrum analyzer �Instrumentation �FSK and ASK data receivers

ORDERING INFORMATION
DESCRIPTION 16-Pin Plastic DIP 16-Pin Plastic SO (Surface-mount) 16-Pin Plastic DIP 16-Pin Plastic SO (Surface-mount)

TEMPERATURE RANGE
oto +70�C
Oto +70�C -40 to +85�C -40 to +85�C

ORDER CODE NE614AN NE614AD SA614AN SA614AD

October 21 , 1988

256

853-0594 94867

Signetics RF Communications
Low power FM IF system

Product specification
NE/SA614A

BLOCK DIAGRAM

16

15

14

13

12

11

10

9

VOLTAGE REGULATOR

GND

2

3

4

5

6

7

8

ABSOLUTE MAXIMUM RATINGS

SYMBOL

PARAMETER

Vee Single supply voltage

Tsrn Storage temperature range

TA

Operating ambienttemperature range NE614A SA614A

Thennal impedance
OJA

D package N package

RATING 9
-85\o +150
Oto+70 -40 to +85
90 75

UNITs
v oc oc oc oc/W oc/W

DC ELECTRICAL CHARACTERISTICS
Vee = +SV, TA = 25�C; unless otherwise stated.

SYMBOL

PARAMETER

TEST CONDITIONS

Vee Power supply voltage range
Ice DC current drain
Mute switch input threshold (ON) (OFF)

LIMITS

NE614A

SA614A

MIN TYP MAX MIN TYP MAX

4.5

8.0 4.5

8.0

2.5

3.3

4.0 2.5

3.3

4.0

1.7

1.7

1.0

1.0

UNITS
v
mA
v v

October 21, 1988

257

Signetics RF Communications
Low power FM IF system

Product specification
NE/SA614A

AC ELECTRICAL CHARACTERISTICS
Typical reading at TA= 25�C; Vee= �6V, unless otherwise stated. IF frequency= 455kHz; IF level= -47dBm; FM modulation= 1kHz with �8kHz peak deviation. Audio output with C-message weighted filter and de-emphasis capacitor. Test circuit Figure 1. The parameters listed below are tested using automatic test equipment to assure consistent electrical characterristics. The limits do not represent the ultimate performance limits of the device. Use of an optimized RF layout will improve many of the listed parameters.
LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

NE/SA614A

UNITS

MIN

TYP

MAX

Input limiting -3dB

Test at Pin 16

-92

dBm/SQQ

AM rejection

80%AM 1kHz

25

33

dB

Recovered audio level

1SnF de-emphasis

60

175

260

mVRMS

Recovered audio level

150pF de-emphasis

530

mVRMS

THD Total harmonic distortion

-30

-42

dB

S/N Signal-to-noise ratio

No modulation for noise

68

dB

RSSI output1

RF level= -118dBm RF level = -68dBm RF level = -18dBm

0

160

800

mV

1.7

2.50

3.3

v

3.6

4.80

5.8

v

RSSI range

~ = 100k (Pin 5)

80

dB

RSSI accuracy

R4 = 1OOk (Pin 5)

�2.0

dB

IF input impedance

1.4

1.6

kn

IF output impedance

0.85

1.0

kn

Limiter input impedance

1.4

1.6

kn

Unmuted audio output resistance

58

kn

Muted audio output resistance

58

kn

NOTE:
son 1. NE614A data sheets refer to power at input termination; about 21dB less power actually enters the internal 1.5k input.

NE614A (50)

NE614A (1.5k)/NE615 (1.Sk

-97dBm

-118dBm

-47dBm

-68dBm

+3dBm

-18dBm

The NE615 and NE614A are both derived from the same basic die. The NE615 perlormance plots are directly applicable to the NE614A.

October 21, 1988

258

Signetics RF Communications
Low power FM IF system

Product specification
NE/SA614A

NE614A

s,

=I
MUTE INPUT

C12!

C1 100nF + 80- 2()0/o 63V K10000-25V Ceramic

C2 100nF +10% 50V

C3 100nF �10% SOV
C4 100nf +10% sov

cs 100nf �10% SOY

C& 10pf �2% 100V NPO Ceramic

C7 100nF �10%50V
ca 100nF � 10% SOY

C9 15nF �10%50V

C10 150pf �2% 1oov N1500 Ceramic

C11 :~F~~~'{,~=l~~P Ceramic
C12

F1 455kHz Ceramic Filter Murata SFG455A3

F2 R1

3~~~.f1~\.11'Me1a1 Film

R2 15000:�1%1/4WMetal Film

R3 1500n �5% 1/SW Carbon Composition

R4 100kn.:t.1% 1!4W Metal Film

(�):;;
z
"II
(�)!:i

DATA OUTPUT
c~0
r-'I(�)

October 21, 1988

Figure 1. NE/SA614A Test Circuit 259

Signetics RF Communications
Low power FM IF system

Product specification
NE/SA614A

VOLTAGE/ CURRENT CONVERTER

Yee
GND
0

Vee
0
Figure 2. Equivalent Circuit

October 21 , 1988

260

Signetics RF Communications
Low power FM IF system

Product specification
NE/SA614A

1 +6V
6.8�F

455kHz

r -0-:.20. ,

I

I

I

I

I

I

L i:l~l

1100nF

MUTE

NE614A IF INPUT (�V) (15000)

RSSI

10

100

1k

10k 100k

C-MSG
..l.. ALTER
I

AUDIO OUT

4V

3V

2V

1V

-80

NOISE

-120 -100 -ao

-60 -40

-20

NE602 RF INPUT (dBm) (500)

Figure 3. Typical Application Cellular Radio (45MHz to 455kHz)

CIRCUIT DESCRIPTION
The NE/SA614A is a very high gain, high frequency device. Correct operation is not possible if good RF layout and gain stage practices are not used. The NEISA614A cannot be evaluated Independent of circuit, components, and board layout. A physical layout which correlates to the electrical limits is shown in Figure 1. This configuration can be used as the basis for production layout.
The NE/SA614A is an IF signal processing system suitable for IF frequencies as high as 21.4MHz. The device consists of two limiting amplifiers, quadrature detector, direct audio output, muted audio output, and signal strength indicator (with log output characteristic). The sub-systems are shown in Figure 2. A typical application with 45MHz input and 455kHz IF is shown in Figure 3.

IF Amplifiers
The IF amplifier section consists of two loglimiting stages. The first consists of two differential amplifiers with 39dB of gain and a small signal bandwidth of 41 MHz (when driven from a son source). The output of the first limiter is a low impedance emitter follower with 1kn of equivalent series resistance. The second limiting stage consists of three differential amplifiers with a gain of 62dB and a small signal AC bandwidth of 28MHz. The outputs of the final differential stage are buffered to the internal quadrature detector. One of the outputs is available at Pin 9 to drive an external quadrature capacitor and UC quadrature tank.
Both of the limiting amplifier stages are DC biased using feedback. The buffered output

of the final differential amplifier is fed back to the input through 42kn resistors. As shown in Figure 2, the input impedance is established for each stage by tapping one of the feedback resistors 1.Skn from the input. This requires one additional decoupling capacitor from the tap point to ground.
I
Fi ure 4. First Limiter Bias

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Low power FM IF system

Product specification
NE/SA614A

Figure 5. Second Limiter and Quadrature Detector

BPF

llGH IMPEDANCE i-::-----,

I I

Figure 8. Feedback Paths

LOW IMPEDANCE Figure 7. Terminating High Impedance Filters with Transformation to Low Impedance

BPF

I

RESISTIVE LOSS INTO BPF

I I

IL-----------------------~

=

J

Figure 7. Low Impedance Termination and Gain Reduction Figure 7. Practical Termination

430

430

NE614A

Figure 8. Crystal Input Filter with Ceramic Interstage Fiiter

Because of the very high gain, bandwidth and input impedance of the limiters, there is a very real potential for instability at IF frequencies above 455kHz. The basic phenomenon is shown in Figure 6. Distributed feedback (capacitance, inductance and radiated fields) forms a divider from the output of the limiters back to the inputs (including RF input). If this

feedback divider does not cause attenuation greater than the gain of the forward path, then oscillation or low level regeneration is likely. If regeneration occurs, two symptoms may be present: (1)The RSSI output will be high with no signal input (should nominally be 250mVor lower), and (2) the demodulated output will demonstrate a threshold. Above a certain input level, the limited signal will begin

to dominate the regeneration, and the demodulator will begin to operate in a �normal" manner.
There are three primm)- ways to deal with regeneration: (1) Minimize the feedback by gain stage isolation, (2) lower the stage input impedances, thus increasing the feedback attenuation factor, and (3) reduce the gain.

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Low power FM IF system

Product specification
NE/SA614A

Gain reduction can effectively be accomplished by adding attenuation between stages. This can also lower the input impedance if well planned. Examples of impedance/gain adjustment are shown in Figure 7. Reduced gain will result in reduced limiting sensitivity.
A feature of the NE614A IF amplifiers, which is not specified, is low phase shift. The NE614A is fabricated with a 10GHz process with very small collector capacitance. It is advantageous in some applications that the phase shift changes only a few degrees over a wide range of signal input amplitudes. Additional information will be provided in the upcoming product specification (this is a preliminary specification) when characterization is complete.
Stability Considerations
The high gain and bandwidth of the NE614A in combination with its very low currents permit circuit implementation with superior performance. However, stability must be maintained and, to do that, every possible feedback mechanism must be addressed. These mechanisms are: 1) Supply lines and ground, 2) stray layout inductances and capacitances, 3) radiated fields, and 4) phase shift. As the system IF increases, so must the attention to fields and strays. However, ground and supply loops cannot be overlooked, especially at lower frequencies. Even at 455kHz, using the test layout in Figure 1, instability will occur if the supply line is not decoupled with two high quality RF capacitors, a 0.1 �F monolithic right at the Vee pin, and a 6.8�F tantalum on the supply line. An electrolytic is not an adequate substitute. At 10.7MHz, a 1�F tantalum has proven acceptable with this layout. Every layout must be evaluated on its own merit, but don't underestimate the importance of good supply bypass.
At 455kHz, if the layout of Figure 1 or one substantially similar is used, it is possible to directly connect ceramic filters to the input and between limiter stages with no special consideration. At frequencies above 2MHz, some input impedance reduction is usually necessary. Figure 7 demonstrates a practical means.
As illustrated in Figure 8, 430W external resistors are applied in parallel to the internal 1.6kW load resistors, thus presenting approximately 330!2 to the filters. The input filter is a crystal type for narrowband selectivity. The filter is terminated with a tank which transforms to 330'2. The interstage filter is a ceramic type which doesn't contribute to system selectivity, but does suppress wideband noise and stray signal

pickup. In wideband 10.7MHz IFs the input filter can also be ceramic, directly connected to Pin 16.
In some products it may be impractical to utilize shielding, but this mechanism may be appropriate to 10.7MHz and 21.4MHz IF. One of the benefits of low current is lower radiated field strength, but lower does not mean non-existent. A spectrum analyzer with an active probe will clearly show IF energy with the probe held in the proximity of the second limiter output or quadrature coil. No specific recommendations are provided, but mechanical shielding should be considered if layout, bypass, and input impedance reduction do not solve a stubborn instability.
The final stability consideration is phase shift. The phase shift of the limiters is very low, but there is phase shift contribution from the quadrature tank and the filters. Most filters demonstrate a large phase shift across their passband (especially at the edges). If the quadrature detector is tuned to the edge of the filter passband, the combined filter and quadrature phase shift can aggravate stability. This is not usually a problem, but should be kept in mind.
Quadrature Detector
Figure 5 shows an equivalent circuit of the NE614A quadrature detector. It is a multiplier cell similar to a mixer stage. Instead of mixing two different frequencies, it mixes two signals of common frequency but different phase. Internal to the device, a constant amplitude (limited) signal is differentially applied to the lower port of the multiplier. The same signal is applied single-ended to an
external capacitor at Pin 9. There is a 90� phase shift across the plates of this capacitor, with the phase shifted signal applied to the upper port of the multiplier at Pin 8. A quadrature tank (parallel UC network) permits frequency selective phase shifting at the IF frequency. This quadrature tank must be returned to ground through a DC blocking capacitor.
The loaded 0 of the quadrature tank impacts three fundamental aspects of the detector: Distortion, maximum modulated peak deviation, and audio output amplitude. Typical.quadrature curves are illustrated in Figure 10. The phase angle translates to a shift in the multiplier output voltage.
Thus a small deviation gives a large output with a high 0 tank. However, as the deviation from resonance increases, the nonlinearity of the curve increases (distortion), and, with too much deviation, the signal will be outside the quadrature region (limiting the peak deviation which can be demodulated).

If the same peak deviation is applied to a lower 0 tank, the deviation will remain in a region of the curve which is more linear (less distortion), but creates a smaller phase angle (smaller output amplitude). Thus the 0 of the quadrature tank must be tailored to the design. Basic equations and an example for determining 0 are shown below. This explanation includes first-order effects only.
Frequency Discriminator Design Equations for NE614A

I

Figure9.

(1a)

Vo=~
Cp +Cs

� -1-+-~- - -(' -~-)2-

�

V1N

01S+ S

where ro1 =

1

(1b)

-./ L(Cp +Cs)

01 = R (Cp +Cs) roi

(1c)

From the above equation, the phase shift between nodes 1 and 2, or the phase across Cs will be:
(2)

Figure 10 is the plot of cp vs. ( ~ }
It is notable that at ro = ro1, the phase shift is
"1i and the response is close to a straight
&cp 201
line with a slope of ~ro = ro1
The signal Vo would have a phase shift of
["1i _~1 ro] with respect to the ViN�

If V1N =A Sin rot=> Vo= A

(3)

1 Sin [rot + .E _ 201 ro J 2 ro1

Multiplying the two signals in the mixer, and low pass filtering yields:

V1N � Vo= A2 Sin rot

(4)

rL 1J Sin rot + .E _ 201 ro 2 ro1

after low pass filtering

October 21, 1988

263

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Low power FM IF system

Product specification
NE/SA614A

1 => VouT =

.1
2

A2

cos[z 2

_

201 ro1

roj

(5)

= .1 A2 Sin( 201) oo

2

001

~ (6)
VouT oe 201 :1 = [ 201 ( 001 ;11!..ro

For �201;r-o � 27t

Which is discriminated FM output. (Note that l!i.ro is the deviation frequency from the carrierro1�
Ref. Krauss, Raab, Bastian; Solid State Radio Eng.; Wiley, 1980, p. 311. Example: At 455kHz IF, with �5kHz FM deviation. The maximum normalized frequency will be
455_:s5:Hz = 1.01 o or 0.990
Go to the f vs. normalized frequency curves (Figure 10) and draw a vertical straight line at
rooo1 =1.01.
a a The curves with = 100, = 40 are not a linear, but = 20 and less shows better a linearity for this application. Too small
decreases the amplitude of the discriminated
FM signal. (Eq. 6) => Choose a Q = 20
The internal R of the 614A is 40k. From Eq. 1c, and then 1b, it results that
Cp +Cs= 174pF and L = 0.7mH.
A more exact analysis including the source resistance of the previous stage shows that there is a series and a parallel resonance in the phase detector tank. To make the parallel and series resonances close, and to get maximum attenuation of higher harmonics at 455kHz IF, we have found that a Cs= 10pF and Cp = 164pF (commercial values of 150pF or 180pF may be practical), will give the best results. A variable inductor which can be adjusted around 0.7mH should be chosen and optimized for minimum distortion. (For 10.7MHz, a value of Cs= 1pF is recommended.)
Audio Outputs
Two audio outputs are provided. Both are PNP current-to-voltage converters with 5511'2 nominal internal loads. The unmuted output is always active to permit the use of signaling

tones in systems such as cellular radio. The other output can be muted with 70dB typical attenuation. The two outputs have an
internal 180� phase difference.
The nominal frequency response of the audio outputs is 300kHz. this response can be increased with the addition of external resistors from the output pins to ground in parallel with the internal 55k resistors, thus lowering the output time constant. Singe the output structure is a current-to-voltage converter (current is driven into the resistance, creating a voltage drop), adding external parallel resistance also has the effect of lowering the output audio amplitude and DC level.
This technique of audio bandwidth expansion can be effective in many applications such as SCA receivers and data transceivers.
Because the two outputs have a 180� phase relationship, FSK demodulation can be accomplished by applying the two output differentially across the inputs of an op amp or comparator. Once the threshold of the reference frequency (or �no-signal' condition) has been established, the two outputs will shift in opposite directions (higher or lower output voltage) as the input frequency shifts. The output of the comparator will be logic output. The choice of op amp or comparator will depend on the data rate. With high IF frequency (10MHz and above), and wide IF bandwidth (LJC filters) data rates in excess of 4Mbaud are possible.
RSSI
The 'received signal strength indicator', or RSSI, of the NE614A demonstrates monotonic logarithmic output over a range of 90dB. The signal strength output is derived from the summed stage currents in the limiting amplifiers. It is essentially independent of the IF frequency. Thus, unfiltered signals at the lim.iter inputs, spurious products, or regenerated signals will manifest themselves as RSSI outputs. An RSSI output of greater than 250mV with no signal (or a very small signal) applied, is an indication of possible regeneration or oscillation.
In order to achieve optimum RSSI linearity, there must be a 12dB insertion loss between the first and second limiting amplifiers. With

a typical 455kHz ceramic fiher, there is a nominal 4dB insertion loss in the filter. An additional 6dB is lost in the interface between the filter and the input of the second limiter. A small amount of additional loss must be introduced with a typical ceramic filter. In the test circuit used for cellular radio applications (Figure 3) the optimum linearity was achieved
with a 5.1 k'2 resistor from the output of the
first limiter (Pin 14) to the input of the interstage filter. With this resistor from Pin 14
to the filter, sensitivity of 0.25�V for 12dB
SINAD was achieved. With the 3.61<'2
resistor, sensitivity was optimized at 0.22�V for 12dB SllilAD with minor change in the RSSI linearity.
Any application which requires optimized RSSI linearity, such as spectrum analyzers, cellular radio, and certain types of telemetry, will require careful attention to limiter interstage component selection. This will be especially true with high IF frequencies which require insertion loss or impedance reduction for stability.
At low frequencies the RSSI makes an excellent logarithmic AC voltmeter.
For data applications the RSSI is effective as an amplitude shift keyed (ASK) data slicer. If a comparator is applied to the RSSI and the threshold set slightly above the no signal level, when an in-band signal is received the comparator will be sliced. Unlike FSK demodulation, the maximum data rate is somewhat limited. An internal capacitor limits the RSSI frequency response to about 100kHz. At high data rates the rise and fall times will not be symmetrical.
The RSSI output is a current-to-voltage converter similar to the audio outputs. However, an external resistor is required.
With a 91 k'2 resistor, the output
characteristic is 0.5V for a 1OdB change in the input amplitude.
Additional Circuitry
Internal to the NE614A are voltage and current regulators which have been temperature compensated to maintain the performance of the device over a wide temperature range. These regulators are not accessible to the user.

October 21, 1988

264

Signetics RF Communications
Low power FM IF system

Product specification
NE/SA614A

200
4)
175

150

125

100

75

50

25

0

0.95

0.975

1.0

1.025

1.05

m;-(J)

d(J)

Figure 10. Phase vs Normalized IF Frequency

= 1 + -;;;;-

October 21, 1988

265

Slgnetlcs RF Communications
Audio decibel level detector with meter driver

Application note
AN1991

Author: Robert J. Zavrel Jr.
DESCRIPTION
Although the NE604 was designed as an RF device intended for the cellular radio market, it has features which permit other design configurations. One of these features is the Received Signal Strength Indicator (RSSI). In a cellular radio, this function is necessary for continuous monitoring of the received signal strength by the radio's microcomputer. This circuit provides a logarithmic response proportional to the input signal level. The NE604 can provide this logarithmic response over an 80dB range up to a 15MHz operating frequency. This paper describes a technique which optimizes this useful function within the audio band.
A sensitive audio level indicator circuit can be constructed using two integrated Circuits: the NE604 and NE532. This circuit draws very litde power (less than 5mA with a single 6V power supply) making it ideal for portable battery operated equipment. The small size and low-power consumption belie the 80dB dynamic range and 10.5�V sensitivity.
The RSSI function requires a DC output voltage which is proportional to the log10 of the input signal level. Thus a standard 0-5

voltmeter can be linearly calibrated in decibels over a single 80dB range. The entire circuit is composed of 9 capacitors and two resistors along with the two ICs. No tuning or calibration is required in a manufacturing setting.
The Audio lnpu1 vs Output Graph shows that the circuit is within 1.5dB tolerance over the 80dB range for audio frequencies from 100Hz to 10kHz. Higher audio levels can be measured by placing an attenuator ahead of the input capacitor. The inpu1 impedance is high (about 50k), so lower impedance terminations (50 or 6000) will not be affected by the input impedance. If very accurate tracking is required (c:0.5dB accuracy), a 40 or 50dB segment can be �selected". A range switch can then be added with appropriate attenuators if more than 40 or SOdB dynamic range is required.
There are two amplifier sections in the 604 with 2 and 3 stages in the first and second sections respectively. Each stage outputs a sample current to a summing circuit. The. summing circuit has a current mirror which appears at Pin 5. This current is proportional to the log10 of the input audio signal. A voltage is dropped across the 100k resistor by the current, and a 0.1 �F capacitor is used to bypass and filter the output signal. The 532

op amp is used as a buffer and meter driver, although a digital voltmeter could replace both the op amp and the meter shown. The rest of the capacitors are used for power supply and amplifier input bypassing. The RC circuit between Pins 14 and 12 forms a low-pass filter which can be adjusted by changing the value of C1. Raising the capacitance will lower the cut-off frequency and also lower the zero signal outpu1 resting voltage (about 0.6V). Lowering the capacitance value will have the opposite effect with some reduction in dynamic range, but will raise the frequency response. The 2kn resistor value provides the near-ideal
t--v''
O�'-"'--'--'-~~~~~~~
-100 -80 -80 -40 ..QI) 0 AUDIO INPUT (dB)

AU,PUT 3r

NC

10�Fl

18 15 14 13 12 11 10
10�F
NE804

4

7 8

NC NC NC

33�FI
+SY

C2

100k

0.1�F

inter-stage loss for maximum RSSI linearity. C2 can also be changed. The trade-off here is between output damping and ripple. Most analog and digital metering methods will tend to cancel the effects of small or moderate

Figure1.
ripple voltages through integration, but high ripple voltages should be avoided.
A second op amp is used with an optional second filter. This filter has the advantage of

I1�F

METER
r~

a low impedance signal source by virtue of the first op amp. Again, a trade-off exists between meter damping and ripple attenuation. If very low ripple and low

December 1991

266

Signetics RF Communications
Audio decibel level detector with meter driver

Application note
AN1991

damping are both required, a more complex active low-pass filter should be constructed.
Some applications of this circuit might include:
1. Portable acoustic analyzer
2. Microphone tester

3. Audio spectrum analyzer 4. VU meters 5. S-meter for direct conversion radio
receiver 6. Audio dynamic range testers

7. Audio analyzers (THD, noise, separation, response, etc.)

December 1991

267

Signetlcs RF Communications
High sensitivity applications of low-power RF/IF integrated circuits

Appllcatlon note
AN1993

ABSTRACT
This paper discusses four high sensitivity receivers and IF (Intermediate Frequency} strips which utilize intermediate frequencies of 10.?MHz or greater. Each circuit utilizes a low-power VHF mixer and high-performance low-power IF strip. The circuit configurations are
1. 45 or 49MHz to 10.?MHz narrowband,
2. 90MHz to 21.4MHz narrowband, 3. 100MHz to 10.?MHz wideband, and 4. 152.2MHz to 10.?MHz narrowband.
Each circuit is presented with an explanation of component selection criteria, (to permit adaptation to other frequencies and bandwidths}. Optional configurations for local oscillators and data demodulators are summarized.
INTRODUCTION
Traditionally, the use of 10.?MHz as an intermediate frequency has been an attractive means to accomplish reasonable image

rejection in VHF/UHF receivers. However, applying significant gain at a high IF has required extensive gain stage isolation to avoid instability and very high current consumption to get adequate amplifier gain bandwidth. By enlightened application of two relatively new low power ICs, Signetics NE602 and NE604A, it is possible to build highly producible IF strips and receivers with input frequencies to several hundred megahertz, IF frequencies of 10.7 or 21.4MHz, and sensitivity less than 2�V (in many cases less than 1�V}. The Signetics new NE605 combines the function of the

NE602 and the NE604A. All of the circuits described in this paper can also be implemented with the NE605. The NE602 andNE604A were utilized for this paper to permit optimum gain stage isolation and filter location.
THE BASICS
First let's look at why it is relevant to use a 10.7 or 21.4MHz intermediate frequency. 455kHz ceramic filters offer good selectivity and small size at a low price. Why use a higher IF? The fundamental premise for the answer to this question is that the receiver architecture is a hetrodyne type as shown in Figure 1.
AUDIO AND/OR DATA

Figure 1. Basic Hetrodyne Receiver

10.7MHzlF
I
~-10

ffi l=-20
l-""
a: ""-40
IMAGE

-

~ ~ ~ t. PRESELEC0TOR FREQ (MHz)

-

Figure 2. Effects of Preselection on Images

IMAGE

455kHzlF

PRESaECTOR FILTER

"\_ DESIRED FREQUENCY

-10

0

+10

~

t. PRESELECTOR FREQ (MHz)

December 1991

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Signetics RF Communications
High sensitivity applications of low-power RF/IF integrated circuits

Application note
AN1993

AUDIO AND/OR DATA

Figure 3. Dual Conversion

1------------o::::J-------------1

I 1--

-

-

~ _rz;---1- -r----- -- -- --1_-__- r--;~:----i_ -----II

l ~ rCLH: I

I

I

I

I

I

I

I

I

I

I

I
Figure 4. Feedback Paths

A pre-selector (bandpass in this case) precedes a mixer and local oscillator. An IF filter follows the mixer. The IF filter is only supposed to pass the difference (or sum) of the local oscillator (LO) frequency and the preselector frequency.
The reality is that there are always two frequencies which can combine with the LO: The pre-selector frequency and the "image" frequency. Figure 2 shows two hypothetical pre-selection curves. Both have 3dB bandwidths of 2MHz. This type of pre-selection is typical of consumer products such as cordless telephone and FM radio. Figure 2A shows the attenuation of a low side image with 10.7MHz. Figure 2B shows the very limited attenuation of the low side 455kHz image.
If the single conversion architecture of Figure 1 were implemented with a 455kHz IF, any interfering image would be received almost as well as the desired frequency. For this reason, dual conversion, as shown in Figure 3, has been popular.
In the application of Figure 3, the first IF must be high enough to permit the pre-selector to reject the images of the first mixer and must have a narrow enough bandwidth that the second mixer images and the intermod products due to the first mixer can be attenuated. There's more to it than that, but those are the basics. The multiple conversion hetrodyne works well, but, as Figure 3 suggests, compared to Figure 2 it is more complicated. Why, then, don't we use the approach of Figure 2?

0
GND
Figure 5. NE602 Equivalent Circuit

THE PROBLEM
Historically there has been a problem: Stability! Commercially available integrated IF amplifiers have been limited to about 60dB of gain. Higher discrete gain was possible if each stage was carefully shielded and bypassed, but this can become a nightmare on a production line. With so little IF gain available, in order to receive signals of less than 1O�V it was necessary to add RF gain and this, in turn, meant that the mixer must have good large signal handling capability. The RF gain added expense, the high level mixer added expense, both added to the potential for instabilities, so the multiple conversion started looking good again.
But why is instability such a problem in a high gain high IF strip? There are three basic mechanisms. First, ground and the supply line are potentially feedback mechanisms from stage-to-stage in any amplifier. Second, output pins and external components create fields which radiate back to inputs. Third,

December 1991

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Signetics RF Communications
High sensitivity applications of low-power RF/IF integrated circuits

Application note
AN1993

VOLTAGE/ CURRENT CONVERTER

Vee
GND
0

Figure 6. NE604A Equivalent Circuit

layout capacitances become feedback mechanisms. Figure 4 shows the fields and capacitances symbolically.
If ZF represents the impedance associated
with the circuit feedback mechanisms (stray capacitances, inductances and radiated
fields), and Z1N is the equivalent input
impedance, a divider is created. This divider must have an attenuation factor greater than the gain of the amplifier if the amplifier is to remain stable.

Figure 7. Symbolic Circuit
� If gain is increased, the input-to-output isolation factor must be increased.
�As the frequency of the signal or amplifier bandwidth increases, the impedance of the layout capacitance decreases thereby reducing the attenuation factor.
The layout capacitance is only part of the issue. In order for traditional 10.?MHz IF amplifiers to operate with reasonable gain bandwidth, the amount of current in the

amplifiers needed to be quite high. The CA3089 operates with 25mA of typical quiescent current. Any currents which are not perfectly differential must be carefully bypassed to ground. The higher the current, the more difficult the challenge. And limiter outputs and quadrature components make excellent field generators which add to the feedback scenario. The higher the current, the larger the field.

December 1991

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High sensitivity applications of low-power RF/IF integrated circuits

Application note
AN1993

e e LO INPUT
e
RF

match from son. In each of the examples which follow, an equivalent 50:1.5k match
was used. This compromise of noise, loss, and match yielded good results. It can be improved upon. Match to aystal filters will require special attention, but will not be given focus in this paper.
This oscillator is a single transistor with an internal emitter follower driving the mixer. For best mixer performance, the LO level needs to be approximately 220mVRMS at the base of the oscillator transistor (Pin 6). A number of oscillator configurations are presented at the end of this paper. In each of the prototypes for this paper, the LO source was a signal generator. Thus, a 51 n resistor was used to terminate the signal generator. The LO is then coupled to the mixer through a DC blocking capacitor. The signal generator is set for OdBm. The impedance at the LO input (Pin 6) is approximately 20kn. Thus, required power is very low, but OdBm across 51n does provide the necessary 220mVRMS�
The outputs of the NE602 are loaded with 1.5kn internal resistors. This makes interface to 455kHz ceramic filters very easy. Other filter types will be addressed in the examples.

Figure 8. Circuit Board Layout

THE SOLUTION The NE602 is a double balanced mixer suitable for input frequencies in excess of 500MHz. It draws 2.5mA of current. The NE604A is an IF strip with over 100dB of gain and a 25MHz small signal bandwidth. It draws 3.5mA of current. The circuits in this paper will demonstrate ways to take advantage of this low current and 75dB or more of the NE604A gain in receivers and IF strips that would not be possible with traditional integrated circuits. No special tricks are used, only good layout, impedance planning and gain distribution.

THE MIXER The NE602 is a low power VHF mixer with built-in oscillator. The equivalent circuit is shown in Figure 5. The basic attributes of this mixer include conversion gain to frequencies greater than 500MHz, a noise figure of 4.6dB @ 45MHz, and a built-in oscillator which can be used up to 200MHz. LO can be injected.
For best performance with any mixer, the interface must be correct. The input impedance of the NE602 is high, typically 3kn in parallel with 3pF. This is not an easy

THE IF STRIP

The basic functions of the NE604A are

ordinary at first glance: Limiting IF,

quadrature detector, signal strength meter,

and mute switch. However, the

performance of each of these blocks

Is superb. The IF has 1OOdB of gain

and 25MHz bandwidth. This feature will

be exploited in the examples. The signal

strength indicator has a 90dB log output

characteristic with very good linearity.

There are two audio outputs wtth greater

than 300kHz bandwidth (one can be

muted greater than 70dB). The total

supply current is typically 3.SmA. This is

the other factor which permtts high gain

and high IF.

�

Figure 6 shows an equivalent circuit of the NE604A. Each of the IF amplifiers has a 1.61<.Q input impedance. The input impedance is achieved by splitting a DC feedback bias resistor. The input impedance will be manipulated in each of the examples to aid stability.

December 1991

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High sensitivity applications of low-power RF/IF integrated circuits

Application note
AN1993

BASIC CONSIDERATIONS In each of the circuits presented, a common layout and system methodology is used. The basic circuit is shown symbolically in Figure 7.
At the input, a frequency selective transformation from SOQ to 1.SkQ permits analysis of the circu.it with an RF signal generator. A second generaior provides LO. This generator second generator provides LO. This generator is terminated with a 51'1

resistor. The output of the mixer and the input of the first limiter are both high impedance (1.5'1 nominal). As indicated previously, the input impedance of the limiter must be low enough to attenuate feedback signals. So, the input impedance of the first limiter is modified with an external resistor. In most of the examples, a 430'1 external resistor was used to create a 330Q input impedance (430//1.SkQ). The first IF filter is thus designed to present 1.51<.ti to the mixer and 330'1 to the first limiter.

The same basic treatment was used between the first and second limiters. However, in each of the 10. 7MHz examples, this interstage filter is not an L/C tank; it is a ceramic filter. This will be explained in the first example.
After the second limiter, a conventional quadrature detector demodulates the FM or FSK information from the carrier and a simple low pass filter completes the demodulation process at the. audio outputs.

L0~1�F
4sm

MUTE ~V

AUDIO

DATA

Figure 9. NE602/604A Demonstration Circuit with RF Input of 45MHz and IF of 21.4MHz �7.SkHz

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Application note
AN1993

CRYSTAL FILTER

10.5

10. 7

10.9

FREOiUENCY (MHz)

Figure 10. Passband Relationship

0.7�.V

7�V

70�V

0.7mV

7mV

70mV

5.0

AUDIO 4.5

-10
Q
@~ -20
~~ �30
!!\!~
t!J� -40
~a:
"~t'"t -50
~~ ll -60

4.0

3.5

3.0

2.5

~
~

!!)

2.0

1.5

-70

1.0

-60

0.5

0 -120 -110 -100 -90 -90 -70 -60 -50 -40 -30 -20 -10 0
RF INPUT (dBm) (50'2)

� 45MHz RF Input �55.7MHz LO
(odBm)

� 10.7MHz IF � 15kHz IF BW � 7kHz deviation

As mentioned, a single layout was used for each of the examples. The board artwork is shown in Figure 8. Special attention was given to: (1) Creating a maximum amount of ground plane with connection of the component side and solder side ground at
L0~1�F
ysm

Figure 11. VHF or UHF 2nd Conversion (Narrow Band)
locations all over the board; (2) careful attention was given to keeping a ground ring around each of the gain stages. The objective was to provide a shunt path to ground for any stray signal which might feed back to an input; (3) leads were kept short and relatively
21.4MHz CRYSTAL
ALTER

820

RSSI MUTE +6V

AUDIO

DATA

Figure 12. NE602/604A Demonstration Circuit with RF Input of 90MHz and IF of 21.4MHz �7.SkHz

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High sensitivity applications of low-power RF/IF integrated circuits

0.7�V
-10 Q
�~ -20
:I:Cl ~~ -30
~g!
~~ -40
"'"'"'"Wu. -50
:!UJ
9~ ;g �60
-70 �BO

7�V

70�V

0.7mV

7mV

70mV

5.0

AUDIO 4.5

4.0

3.5

3.0

2.5

~
Ci

!IJ

2.0

1.5

1.0

0.5

�120 �110 �100 �90 �BO �70 -60 �50 -40 -30 �20 -10 RF INPUT (dBm) (500)

� 90MHz RF input �68.6MHz LO
(odBm)

� 21.4MHz IF �15kHzlFBW � 7kHz deviation

Figure 13. UHF Second Conversion (Narrow Band) or VHF Single Conversion (Narrow Band)

Application note
AN1993
wide to minimize the potential for them to radiate or pick up stray signals; finally (and very important), (4) RF bypass was done as close as possible to supply pins and inputs, with a good (10�F) tantalum capacitor completing the system bypass.
EXAMPLE: 45MHZ TO 10.7MHZ NARROWBAND
As a first example, consider conversion from 45MHz to 10.7MHz. There are commercially available filters for both frequencies so this is a realistic combination for a second IF in a UHF receiver. This circuit can also be applied to cordless telephone or short range communications at 46 or 49MHz. The circuit is shown in Figure 9.
The 10.7MHz filter chosen is a type commonly available for 25kHz channel spacing. It has a 3dB bandwidth of 1SkHz and a termination requirement of 3kQ/2pF. To present 3kQ to the input side of the filter, a 1.SkQ resistor was used between the NE602 output (which has a 1.SkQ impedance) and the filter. Layout capacitance was close enough to 2pF that no adjustment was necessary. This series-resistance approach introduces an insertion loss which degrades the sensitivity, but it has the benefit of simplicity.

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High sensitivity applications of low-power RF/IF integrated circuits

L0~1�F
45"'

10.7MHz CERAMIC
FILTER

Application note
AN1993

RSSI MUTE ""5V

AUDIO

DATA

Figure 14. NE602/604A Demonstration Circuit with RF Input of-100MHz and IF of 10.7MHz�140kHz

The secondary side of the crystal filter is terminated with a 10.7MHz tuned tank. The capacitor of the tank is tapped to create a transformer with the ratio for 3k:330. With the addition of the 4300 resistor in parallel with the NE604A 1.6kil internal input resistor, the correct component of resistive termination is presented to the crystal filter. The inductor of the tuned load is adjusted off resonance enough to provide the 2pF capacitance needed. (Actual means of adjustment was for best audio during alignment).
If appropriate or necessary for sensitivity, the same type of tuned termination used for the secondary side of the crystal filter can also be used between the NE602 and the filter. If this is desired, the capacitors should be ratioed for 1.5k:3k. Alignment is more complex with tuned termination on both sides of the filter. This approach is demonstrated in the fourth example.
A ceramic filter is used between the first and second limiters. It is directly connected between the output of the first limiter and the input of the second limiter. Ceramic filters act much like ceramic capacitors, so direct connection between two circuit nodes with different DC levels is acceptable. At the input to the second limiter, the impedance is again reduced by the addition of a 430Q external

0.7�V

7�V

70�V

0.7mV

7mV

70mV

5.0

AUDIO 4.6

4.0

3.5

3.0
'�
2.5 ~ !!)
2.0

1.5

1.0

0.5

0 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0
RF INPUT (dBm) (50!l)

� 94.7MHz RF Input � 84MHz LO
(odBm)

� 1O.7MHz IF � 280kHz IF BW � 75kHz deviation

Figure 15. FM Broadcast Receiver (Wide Band)

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High sensitivity applications of low-power RF/IF integrated circuits
L0~1�F
ysm

Application note
AN1993

RSSI MUTE +6V

AUDIO

DATA

Figure 16. NE602/604A Demonstration Circuit with RF Input of 152.2MHz and IF of 10.7MHz�7.5kHz

resistor in parallel with the internal 1.6kn input load resistor. This presents the 330!.1
termination to the ceramic filter which the manufacturers recommend.
On the input side of the ceramic filter, no attempt was made to create a match. The output impedance of the first limiter is nominally 1kn. Crystal filters are tremendously sensitive to correct match. Ceramic filters are relatively forgiving. A review of the manufacturers' data shows that the attenuation factor in the passband is affected with improper match, but the degree of change is small and the passband stays centered. Since the principal selectivity for this application is from the crystal filter at the input of the first limiter, the interstage ceramic filter only has to suppress wideband noise. The first filter's passband is right in the center of the ceramic filter passband. (The crystal filter passband is less than 10% of the ceramic filter passband). This passband relationship is illustrated in Figure 10.
After the second limiter, demodulation is accomplished in the quadrature detector. Quadrature criteria is not the topic of this paper, but it is noteworthy that the choice of loaded Q will affect performance. The NE604A is specified at 455kHz using a quadrature capacitor of 10pF and a tuning capacitor of 180pF. (180pF gives a loaded Q of 20 at 455kHz). A careful look at the

3.so..--.--..--,..-..-.,...--,.-.--.--.
Vcc�S.OV

3. so'--'--..._....._.__,__........__._.._....
-10 0 10 20 30 40 50 60 70 80
AMBIENT TEMPERATURE re)

� 152.2MHz RF input � 141.SMHz LO
{odBm)

� 10.7MHz IF � 15kHz IF BW � 7kHz deviation

Figure 17. VHF Single Conversion {Narrow Band)

quadrature equations {Ref 3.) suggests that at 10.?MHz a value of about 1pF should be substituted for the 10pF at 455kHz.
The performance of this circuit is presented in Figure 11. The -12dB SINAD {ratio of Signal to Noise And Distortion) was achieved with a O.G�V input.

EXAMPLE: 90MHZ TO 21.4MHZ NARROWBAND
This second example, like the first, used two frequencies which could represent the intermediate frequencies of a UHF receiver. This circuit can also be applied to VHF single conversion receivers if the sensitivity is

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Application note
AN1993

appropriate. The circuit is shown in Figure 12.

Most of the fundamentals are the same as explained in the first example. The 21.4MHz crystal filter has a 1.5k0/2pF termination requirement so direct connection to the output of the NE602 is possible. With strays there is probably more than 2pF in this circuit, but the performance is good nonetheless. The output of the crystal filter is terminated with a tuned impedance-step-down transformer as in the previous example. Interstage filtering is accomplished with a 1k0:330 step-down ratio. (Remember, the output of the first limiter is 1kn and a 4300 resistor has been added to make the second limiter input 3300). A DC blocking capacitor is needed from the output of the first limiter. The board was not laid out for an interstage transformer, so an "XACTO" knife was used to make some minor mods. Figure 13 shows the performance. The+ 12dB SINAD was with 1.6�V input.
EXAMPLE: 100MHZ TO 10.7MHZ WIDEBAND This example represents three possible applications: (1) low cost, sensitive FM broadcast receivers, (2) SCA (Subsidiary Communications Authorization) receivers and (3) data receivers. The circuit schematic is shown in Figure 14. While this example has the greatest diversity of application, it is also the simplest. Two 10. 7MHz ceramic filters were used. The first was directly connected to the output of the NE602. The second was directly connected to the output of the first IF limiter. The secondary sides of both filters were terminated with 3300 as in the two previous examples. While the filter bandpass skew of this simple single conversion receiver might not be tolerable in some applications, to a first order the results are excellent. (Please note that sensitivity is measured at +20dB in this wideband example.) Performance is illustrated in Figure 15. +20dB SINAD was measured with 1.B�V input.
EXAMPLE: 152.2MHZ TO 10.7MHZ NARROWBAND In this example (see Figure 16) a simple, effective, and relatively sensitive single conversion VHF receiver has been implemented. All of the circuit philosophy has

a. Fundamental Colpltts Crystal

b. Overtone Colpitts Crystal

c.Overtone Butler Crystal

d. Hartley L/CTank

IT
Figure 18. Oscillator Configurations

I
e. Colpitts
L/CTank

been described in previous examples. In this circuit, tuned-transformed termination was used on the input and output sides of the crystal filter. Performance is shown in Figure 17. The +12dB SINAD sensitivity was 0.9�V.
OSCILLATORS The NE602 contains an oscillator transistor which can be used to frequencies greater than 200MHz. Some of the possible configurations are shown in Figures 18 and 19.
L/C When using a synthesizer, the LO must be externally buffered. Perhaps the simplest approach is an emitter follower with the base connected to Pin 7 of the NE602. The use of a dual-gate MOSFET will improve performance because it presents a fairly constant capacitance at its gate and because it has very high reverse isolation.
CRYSTAL With both of the Colpitts crystal configurations, the load capacitance must be specified. In the overtone mode, this can become a sensitive issue since the capacitance from the emitter to ground is actually the equivalent capacitive reactance

of the harmonic selection network. The Butler oscillator uses an overtone crystal specified for series mode operation (no parallel capacitance). It may require an extra inductor (L0) to null out C0 of the crystal, but otherwise is fairly easy to implement (see references).
The oscillator transistor is biased with only 220�A. In order to assure oscillation in some configurations, it may be necessary to increase transconductance with an external resistor from the emitter to ground. 1OkO to 20kn are acceptable values. Too small a resistance can upset DC bias (see references).
DATA DEMODULATION It is possible to change any of the examples from an audio receiver to an amplitude shift keyed (ASK) or frequency shift keyed (FSK) receiver or both with the addition of an external op amp(s) or comparator(s). A simple example is shown in Figure 20. ASK decoding is accomplished by applying a comparator across the received signal strength indicator (RSSI). The RSSI will track IF level down to below the limits of the demodulator (-120dBm RF input in most of the examples). When an in-band signal is

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Application note
AN1993

above the comparator threshold, the output logic level will change.
FSK demodulation takes advantage of the two audio outputs of the .NE604A. Each is a

PNP current source type output with 180� phase relationship. With no signal present, the quad tank tuned for the center of the IF

passband, and both outputs loaded with the same value of capacitance, if a signal is received which is frequency shifted from the

0.118j1H
v c
111nF

10.711Hz

12pP

.::1

FROM SVNTHLOOP
ALTER

'PERllolTS IMPEDANCE MATCH OF NE&o2 OUTPUT OF 1.tlc/8pf TO 3.0k FILTER IMPEDANCE ~cHOOSE FOR IMPEDANCE MATCH TO

Figure 19. Typical Varactor Tuned Application

IF passband, and both outputs loaded with the same value of capacitanee, if a signal is received which is frequency shifted from the IF center, one output voltage will increase and the other will decrease by a corresponding absolute value. Thus, if a

comparator is differentially connected across the two outputs, a frequency shift in one direction will drive the comparator output to one supply rail, and a frequency shift in the opposite direction will cause the comparator

output to swing to the opposite rail. Using this technique, and UC filtering for a wide IF bandwidth, NRZ data at rates greater than 4Mb have been processed with the new NE605.

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L0~1�F
ysm

10.7MHz CERAMIC
ALTER

NE604A

Application note
AN1993

Figure 20. Basic NE602/604A Data Receiver

SUMMARY
The NE602, NE604A and NE605 provide the RF system designer with the opportunity for excellent receiver or IF system sensitivity with very simple circuitry. IFs at 455kHz, 10.7MHz and 21.4MHz with 75 to 90dB gain are possible without special shielding. The flexible configuration of the built-in oscillator of the NE602/605 add to ease of implementation. Either data or audio can be recovered from the NE604A/605 outputs.

REFERENCES
1) Anderson, D.: "Low Power JCs for RF Data Communications", Machine Design , pp 126-128, July 23, 1987.
2) Krauss, Raab, Bastian: Solid State Radio Engineering, p. 311, Wiley, 1980.
3) Matthys, R.: "Survey of VHF Crystal Oscillator Circuits," RF Technology Expo Proceedings, pp 371-382, February, 1987.

4) Signetics: "NE/SA604A High Performance Low Power FM IF System", Linear Data and Applications Manual, Signetics, 1987.
5) Signetics; "NEISA602 Double Balanced Mixer and Oscillator", Linear Data and Applications Manual, Signetics, 1985.
6) Signetics: "AN 1982-Applying the Oscillator of the NE602 in Low Power Mixer Applications", Linear Data and Applications Manual, Signetics, 1985.

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Slgnetlcs RF Communications
High performance low power mixer FM IF system

Product specification
NE/SA605

DESCRIPTION
The NE/SA605 is a high performance monolithic low-power FM IF system incorporating a mixer/oscillator, two limiting intermediate frequency amplifiers, quadrature detector, muting, logarithmic received signal strength indicator (RSSI), and voltage regulator. The NE/SA605 combines the functions of Signetics� NE602 and NE604A, but features a higher mixer input intercept point, higher IF bandwidth (25MHz) and temperature compensated RSSI and limiters permitting higher performance application. The NE/SA605 is available in 20-lead dual-inline plastic and 20-lead SOL (surfacemounted miniature package).
The NE/SA605 and NE/SA615 are functionally the same device types. The difference between the two devices lies in the guaranteed specifications. The NE/SA615 has a higher Ice. lower input third order intercept point, lower conversion mixer gain, lower limiter gain, lower AM rejection, lower SINAD, higher THD, and higher RSSI error than the NE/SA605. Both the NE/SA605 and NE/SA615 devices will meet the EIA specifications for AMPS and TACS cellular radio applications.

FEATURES
�Low power consumption: 5.7mA typical at 6V
�Mixer input to >500MHz
�Mixer conversion power gain of 13dB at 45MHz
�Mixer noise figure of 4.6dB at 45MHz
�XTAL oscillator effective to 150MHz (L.C. oscillator to 1GHz local oscillator can be injected)
�102dB of IF Amp/Limiter gain
�25MHz limiter small signal bandwidth �Temperature compensated logarithmic
Received Signal Strength Indicator (RSSI) with a dynamic range in excess of 90dB �Two audio outputs - muted and unmuted
�Low external component count; suitable for crystal/ceramic/LC filters
son �Excellent sensitivity: 0.22�V into
matching network for 12dB SINAD (Signal to Noise and Distortion ratio) for 1kHz tone with RF at 45MHz and IF at 455kHz �SA605 meets cellular radio specifications
�ESD hardened

PIN CONFIGURATION
0 1 and N Packages

RF1N 1
XTALOSC 3 XTALOSC 4
MUTE1N 5
RSSlouT 7
MUTED AU8:J~ a A~irif~D~ 9

MIXER OUT
IFAMP DECOUPLING IF AMP IN IFAMP DECOUPLING
IF AMP OUT
GND
LIMITER IN
LIMITER DECOUPLING LIMITER DECOUPLING LIMITER OUT

NOTE: 1. Large SO (SOL) package only.

APPLICATIONS
�Cellular radio FM IF �High performance communications
receivers �Single conversion VHF/UHF receivers �SCA receivers �RF level meter �Spectrum analyzer �Instrumentation �FSK and ASK data receivers �Log amps �Wideband low current amplification

ORDERING INFORMATION
DESCRIPTION 20-Pin Plastic DIP 20-Pin Plastic SOL (Surface-mount) 20-Pin Plastic DIP 20-Pin Plastic SOL (Surface-mount)

TEMPERATURE RANGE
o to +70�C o to +70�C
-40 to +85�C
-40 to +85�C

ORDER CODE NE605N NE605D SA605N SA605D

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Signetics RF Communications
High performance low power mixer FM IF system
BLOCK DIAGRAM

Product specification
NE/SA605

ABSOLUTE MAXIMUM RATINGS

SYMBOL

PARAMETER

Vee Single supply voltage

TsTG Storage temperature range

TA Operating ambienttemperature range NE605

SA605

OJA Thermal impedance

Dpackage N package

RATING 9
-65 to +150 0 to +70 -40to +85 90 75

UNITS
v oc oc oc oc/W oc/W

DC ELECTRICAL CHARACTERISTICS
Vee =+6V, = TA 25�C; unless otherwise stated.

SYMBOL

PARAMETER

TEST CONDITIONS

Vee Power supply voltage range Ice DC current drain
Mute switch input threshold (ON)
(OFF)

LIMITS

NE605

SA605

UNITS

MIN

TYP MAX MIN

TYP MAX

4.5

8.0

4.5

8.0

v

5.1

5.7

6.5

4.55

5.7

6.55 mA

1.7

1.7

v

1.0

1.0

v

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Product specification
NE/SA605

AC ELECTRICAL CHARACTERISTICS
Typical reading at TA= 25�C; Vee= +6V, unless otherwise stated. RF frequency= 45MHz + 14.5dBV RF inputstep-up; IF frequency= 455kHz; R17 = 5.1k; RF level= -45dBm; FM modulation= 1kHzwith �8kHz peak deviation. Audio output with C-messageweighted filter and de-emphasis capacitor. Test circuit Figure 1. The parameters listed below are tested using automatic test equipment to assure consistent electrical characterristics. The limits do not represent the ultimate performance limits of the device. Use of an optimized RF layout will improve many of the listed parameters.
LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

NE605

SA605

UNITS

Mlxer/Osc section (ext LO =30DmV)

MIN TYP MAX MIN TYP MAX

f1N

Input signal frequency

lose Crystal oscillator frequency

Noise figure at 45MHz

500

500

MHz

150

150

MHz

5.0

5.0

dB

Third-order input intercept point

f1 = 45.0; f2 = 45.06MHz

-10

-10

dBm

Conversion power gain

Matched 14.5dBV step-up

10.5

13

14.5

10

13

15

dB

50nsource

-1.7

-1.7

dB

RF input resistance

Single-ended input

3.5

4.7

3.0

4.7

kn

RF input capacitance

3.5

4.0

3.5

4.0

pF

Mixer output resistance

(Pin 20)

1.3

1.5

1.25

1.5

kn

IF section

IF amp gain

50nsource

39.7

39.7

dB

Limiter gain

50nsource

62.5

62.5

dB

Input limiting -3dB, R17 = 5.1 k Test at Pin 18

AM rejection

80%AM 1kHz

-113

30

34

42

-113

dBm

29

34

43

dB

Audio level, R10 = 100k
Unmuted audio level, R11 = 100k

15nF de-emphasis 150pF de-emphasis

110

150

250

80

150

260 mVRMS

480

480

mV

SI NAO sensitivity

RF level -118dB

16

16

dB

THO Total harmonic distortion

-35

-42

-34

-42

dB

SIN Signal-to-noise ratio

No modulation for noise

73

73

dB

IF RSSI output, Rg = 100kn1

IF level =-118dBm IF level = -68dBm IF level= -18dBm

0

160

550

0

160

650

mV

2.0

2.5

3.0

1.9

2.5

3.1

v

4.1

4.8

5.5

4.0

4.8

5.6

v

RSSI range

Re= 100kn Pin 16

90

90

dB

RSSI accuracy

Re= 100kn Pin 16

�1.5

�1.5

dB

IF input impedance

1.40

1.6

1.40

1.6

kn

IF output impedance Limiter intput impedance

0.85

1.0

0.85

1.0

kn

1.40

1.6

1.40

1.6

kn

Unmuted audio output resistance

58

58

kn

Muted audio output resistance

58

58

kn

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High performance low power mixer FM IF system

Product specification
NE/SA605

AC ELECTRICAL CHARACTERISTICS

SYMBOL

PARAMETER

TEST CONDITIONS

RF/IF section (Int LO) Unmuted audio level System RSSI output

4.SV = Vee, RF level = -27dBm
4.SV =Vee. RF level= -27dBm

LIMITS

NE605

SA605

UNITS

MIN TVP MAX MIN TVP MAX

4SO

4SO

mVRMS

4.3

4.3

v

NOTE: 1. The generator source impedance is 50'2, but the NE/SA60S input impedance at Pin 18 is 1500'2. As a result, IF level refers to the actual
signal that enters the NE/SAGOS input (Pin 8) which is about 21dB less than the "available power" at the generator.

CIRCUIT DESCRIPTION
The NE/SAGOS is an IF signal processing system suitable for second IF or single conversion systems with input frequency as high as 1GHz. The bandwidth of the IF amplifier is about 40MHz, with 39.7dB(v) of
son gain from a source. The bandwidth of
the limiter is about 28MHz with about G2.SdB(v) of gain from a SOU source. However, the gain/bandwidth distribution is optimized for 4SSkHz, 1.Sk'2 source applications. The overall system is wellsuited to battery operation as well as high performance and high quality products of all types.
The input stage is a Gilbert cell mixer with oscillator. Typical mixer characteristics include a noise figure of SdB, conversion gain of 13dB, and input third-order intercept of -10dBm. The oscillator will operate in excess of 1GHz in UC tank configurations. Hartley or Colpitts circuits can be used up to 1OOMHz for xtal configurations. Butler oscillators are

recommended for xtal configurations up to 150MHz.
The output of the mixer is internally loaded with a 1.Sk'2 resistor permitting direct connection to a 4SSkHz ceramic filter. The input resistance of the limiting IF amplifiers is also 1.Sk'2. With most 4SSkHz ceramic filters and many crystal filters, no impedance matching network is necessary. To achieve optimum linearity of the log signal strength indicator, there must be a 12dB(v) insertion loss between the first and second IF stages. If the IF filter or interstage network does not cause 12dB(v) insertion loss, a fixed or variable resistor can be added between the first IF output (Pin 1G) and the interstage network.
The signal from the second limiting amplifier goes to a Gilbert cell quadrature detector. One port of the Gilbert cell is internally driven by the IF. The other output of the IF is ACcoupled to a tuned quadrature network. This

signal, which now has a 90� phase relationship to the internal signal, drives the other port of the multiplier cell.
Overall, the IF section has a gain of 90dB. For operation at intermediate frequencies greater than 4SSkHz, special care must be given to layout, termination, and interstage loss to avoid instability.
The demodulated output of the quadrature detector is available at two pins, one continuous and one with a mute switch. Signal attenuation with the mute activated is greater than 60dB. The mute input is very high impedance and is compatible with CMOS or TTL levels.
A log signal strength completes the circuitry. The output range is greater than 90dB and is temperature compensated. This log signal strength indicator exceeds the criteria for AMPs or TACs cellular telephone.
NOTE: dB(v) = 20log Vou1N1N

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High performance low power mixer FM IF system

Product specification
NE/SA605

-10dB,

-29dB, 929/SOn PAD

-10.6dB, 50/50<> PAD

a-51.5
= C20 T

a=96.5
32.8 71.5
~Rr17::-- T C19
=

-36dB, 156k/5D<l PAD
rJ=51.7
t.3k
= TC16 ~15

IFT1

MINI-CIRCUIT ZSC2-1B

""C"" WEIGHTED

AUDIO

MEASUREMENT

R8

CIRCUIT

39.2

= MUTE Vee RSSI AUDIO UNMUTED

OUTPUT

AUDIO

November 1, 1990

Automatic Test Circuit Component List

C1 100pF NPO Ceramic C2 390pF NPO Ceramic CS 100nF �10% Monolithic Ceramic C6 22pF NPO Ceramic C7 1nF Ceramic CB 10.0pF NPO Ceramic C9 100nF .�10% Monolithic Ceramic C10 15�F Tantalum (minimum)
C11 100nF .�10% Monolithic Ceramic C12 15nF �10% Ceramic C13 150pF �2% N1500 Ceramic C14 100nF .�10% Monolithic Ceramic C15 10pF NPO Ceramic C17 100nF �10% Monolithic Ceramic C18 100nF �10% Monolithic Ceramic

C21 C23 C25 Flt 1 Flt2 IFT 1
L1 L2
X1 R9 R17 R1D R11

100nF �10% Monolithic Ceramic 100nF �10% Monolithic Ceramic 100nF �10% Monolithic Ceramic Ceramic Fiiter Murata SFG455A3 or equiv Ceramic Filter Murata SFG455A3 or equiv
= 455kHz (Ce 1SOpF) Toko RMC-2A6597H
147-160nH Coilcraft UNl-10/142--04J08S 3.3�H nominal
Toko 292CNS-T1046Z 44.545MHz Crystal ICM4712701 100k �1% 1/4W Metal Film 5.1k�5%1/4W Carbon Composition 1DDk �1% 1/4W Metal Film (optional)
100k .t.1% 1/4W Metal Film (optional)

Figure 1. NE/SA605 45MHz Test Circuit (Relays as shown)

284

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High performance low power mixer FM IF system

Product specification
NE/SA605

C15

C1
J,_______.1
INPUT

IFT1

MUTE Vee RSSI AUDIO UNMUTED

OUTPUT

AUDIO

Appllcatlon Component List

C1 100pF NPO Ceramic C2 390pF NPO Ceramic
cs 100nF �10% Monolithic Ceramic
C6 22pF NPO Ceramic
C7 1nF Ceramic
cs 10.0pF NPO Ceramic
C9 100nF �100k Monolithic Ceramic C10 15�F Tantalum (minimum)
C11 100nF �10% Monolithic Ceramic C12 15nF �10%Ceramic C13 1SOpF �2% N1500 Ceramic C14 100nF �10% Monolithic Ceramic C15 10pF NPO Ceramic C17 100nF �10% Monolithic Ceramic C18 100nF �1D�k Monolithic Ceramic

C21 C23 C25 Flt 1 Flt2 IFT 1
L1 L2
X1 R9 R17 RS R10 R11

100nF �10%MonollthlcCeramlc 100nF �10% Monolithic Ceramic 100nF �10% Monolithic Ceramic Ceramic Filter Murata SFG455A3 or equiv Ceramic Filter Murata SFG455A3 or equiv
455kHz (Ce = 180pF) Toko RMC-2A6597H
147-160nH Collcraft UNl-10/142--04J08S 3.3�H nominal
Toko 292CNS-T1046Z 44.545MHz Crystal ICM4712701 100k�1% 1/4W Metal Fiim 5.1k�5% 1/4W Carbon Composition Not Used In Application Board (see Note 8) 100k�1% 1/4W Metal Fiim (optional)
100k �1% 1/4W Metal Film (optional)

November 1, 1990

Figure 2. NE/SA605 45MHz Application Circuit 285

Signetics RF Communications
High performance low power mixer FM IF system

Product specification
NE/SA605

RF GENERATOR 45MHz

NE605 DEMO BOARD

Vee (+6)

C-MESSAGE

SCOPE

HP339A DISTORTION ANALYZER

Figure 3. NE/SA605 Appllcatlon Circuit Test Set Up
NOTES: 1. C-message: The C-message filter has a peak gain of 100 for accurate measurements. Without the gain, the measurements may be
affected by the noise of the scope and HP339 analyzer. 2. Ceramic filters: The ceramic filters can be 30kHz SFG455A3s made by Murata which have 30kHz IF bandwidth (they come in blue). or
16kHz CFU455Ds, also made by Murata (they come in black). All of our specifications and testing are done with the more wideband filter. 3. RF generator: Set your RF generator at 45.000MHz, use a 1kHz modulation frequency and a 6kHz deviation if you use 16kHz filters, or
8kHz if you use 30kHz filters. 4. Sensitivity: The measured typical sensitivity for 12dB SINAD should be 0.22�Vor-120dBm at the RF input. 5. Layout: The layout is very critical in the performance of the receiver. We highly recommend our demo board layout. 6. RSSI: The smallest RSSI voltage (i.e., when no RF input is present and the input is terminated) is a measure of the quality of the layout and
design. If the lowest RSSI voltage is 250mV or higher, it means the receiver is in regenerative mode. In that case, the receiver sensitivity will be worse than expected. 7. Supply bypass and shielding: All of the inductors, the quad tank, and their shield must be grounded. A 10-15�F or higher value tantalum capacitor on the supply line is essential. A low frequency ESR screening test on this capacitor will ensure consistent good sensitivity in production. A 0.1�F bypass capacitor on the supply pin, and grounded near the 44.545MHz oscillator improves sensitivity by 2-3dB. 8. RS can be used to bias the oscillator transistor at a higher current for operation above 45MHz. Recommended value is 22kn, but should not be below 1OkQ.

November 1, 1990

286

Signetics RF Communications
High performance low power mixer FM IF system

Product specification
NE/SA605

20

Ai110 R~F = 1j4mV~

0

~

L

iii'
~

re;7;;:

r7- !5
~ -20 0
z 0

"~"'~"~~::s.:

iS

::I C-40
I=!
- > w
-sl- ~w-eo

~

x

~

~

::s: a:

z ~ ll
L

~
L 7 .....
k'.'.'.:

+ THDNOISE
AM (80%)

rs;:

L RSSI
(Volts) _,Lj

~

NOISE

J_

-;;;;i_Z-

-100

-130

-110

-00

-70

-60

-30

RF INPUT LEVEL (dBm) Figure 4. NE605 Application Board at 25�C

RF: 45MHz --1 IF = 455kHz --1
Vcc=&V __,
s

RSSI (Volts)

i
-1
...-+... ll

-

0

-10

10

November 1, 1990

287

Signetics RF Communications
High performance low power mixer FM IF system

Product specification
NE/SA605

C21

g; IN':,"UT

FLT10 0~~~2 IFT1

m 0 c~2 rL13Q

a:::::D
lc1s

QC14
0 GND

! uei) OUT if! ~ '�-w~cCQieSXTaAC:::2:L5:Deo~.; ;II=lIl~C�13 DATA 0

SIGNETICS NE605
0 GND

& a:::D C10

MUTE OFF

I _

0

0

O_ I

SW1
0 Vee

0 RSSI

0 AUDIO
OUT
GND

Figure 5. Component Placement for NE605 Appllcatlon Circuit

November 1, 1990

288

Signetics RF Communications
High performance low power mixer FM IF system

Product specification
NE/SA605

� �

��
���

� �

TOP VIEW

0

0

�� ����� ��

� �

���
��

� �

������� ��
November 1, 1990

�� ����� ��
BOTTOM VIEW
Figure 6. Layout for NE/SA605 Appllcation Board 289

Slgnetlcs RF Communications
High performance low power mixer FM IF system in shrink small outline package

Product specification
NE/SA605SSOP

DESCRIPTION
The NE/SA605 is a high performance monolithic low-power FM IF system incorporating a mixer/oscillator, two limiting intermediate frequency amplifiers, quadrature detector, muting, logarithmic received signal strength indicator (RSSI), and voltage regulator. The NE/SA605 combines the functions of Signetics' NE602 and NE604A, but features a higher mixer input intercept point, higher IF bandwidth (25MHz) and temperature compensated RSSI and limiters permitting higher performance application. The NE/SA605 is available in 20-lead dual-inline plastic and 20-lead SOL (surfacemounted miniature package).
The NE/SA605 and NE/SA615 are functionally the same device types. The difference between the two devices lies in the guaranteed specifications. The NE/SA615 has a higher Ice. lower input third order intercept point, lower conversion mixer gain, lower limiter gain, lower AM rejection, lower SINAD, higher THO, and higher RSSI error than the NE/SA605. Both the NE/SA605 and NE/SA615 devices will meet the EIA specifications for AMPS and TACS cellular radio applications.

FEATURES
�Low power consumption: 5.7mA typical at 6V
�Mixer input to >500MHz
�Mixer conversion power gain of 13d8 at 45MHz
�Mixer noise figure of 4.6d8 at 45MHz
�XTAL oscillator effective to 150MHz (L.C. oscillator to 1GHz local oscillator can be injected)
�102d8 of IF Amp/Limiter gain
�25MHz limiter small signal bandwidth �Temperature compensated logarithmic
Received Signal Strength Indicator (RSSI) with a dynamic range in excess of 90d8 �Two audio outputs - muted and unmuted �Low external component count; suitable for crystal/ceramic/LC filters �Excellent sensitivity: 0.22�V into 50Q matching network for 12d8 SINAD (Signal to Noise and Distortion ratio) for 1kHz tone with RF at 45MHz and IF at 455kHz �SA605 meets cellular radio specifications �ESD hardened

PIN CONFIGURATION
SSOP Package

RfiN 1
XTALOSC 3 XTALOSC 4

MIXER OUT
IFAMP DECOUPLING 18 IFAMPIN
17 ~E~PLING

RSSJour MUTED AU&'i~ a
A~':J'~~~ 9
QUADRATU~~ 10

14 LillTERIN
LillTER DECOUPLING LillTER DECOUPLING 11 LillTEROUT

APPLICATIONS
�Cellular radio FM IF �High performance communications
receivers �Single conversion VHF/UHF receivers �SCA receivers �RF level meter �Spectrum analyzer �Instrumentation �FSK and ASK data receivers �Log amps �Wideband low current amplification

ORDERING INFORMATION
DESCRIPTION 20-Pin Plastic SSOP 20-Pin Plastic SSOP

TEMPERATURE RANGE
oto +70�C
-40 to +85�C

ORDER CODE NE605DK SA605DK

January 18, 1991

290

853-153201493

Signetics RF Communications
High performance low power mixer FM IF system in shrink small outline package
BLOCK DIAGRAM
16

Product specification
N E/SA605SSOP

E

B

2

3

4

5

ABSOLUTE MAXIMUM RATINGS

SYMBOL

PARAMETER

Voo Single supply voltage

TsTG TA

Storage temperature range Operating ambient temperature range NE605

SA605

9JA

Thermal impedance

SSOP package

RATING 9
-65to +150 0 to +70
-40 to +85 117

UNITS
v oc oc oc oc/W

DC ELECTRICAL CHARACTERISTICS
Voo = +6V, TA= 25�C; unless otherwise stated.

SYMBOL

PARAMETER

TEST CONDITIONS

Voo Power supply voltage range

loo

DC current drain

Mute switch input threshold (ON)

(OFF)

LIMITS

NE605

SA605

UNITS

MIN

TYP

MAX

MIN

TYP

MAX

4.5

8.0

4.5

8.0

v

5.1

5.7

6.5

4.55

5.7

6.55

mA

1.7

1.7

v

1.0

1.0

v

January 18, 1991

291

Signetics RF Communications
High performance low power mixer FM IF system in shrink small outline package

Product specification
NE/SA605SSOP

AC ELECTRICAL CHARACTERISTICS
TA = 25�C; Vcc = +6V, unless otherwise stated. RF frequency = 45MHz + 14.5dBV RF input step-up; IF frequency = 455kHz; R17 = 5.1k; RF level= -45dBm; FM modulation = 1kHz with �8kHz peak deviation. Audio output with C-message weighted filter and de-emphasis capacitor. Test circuit Figure 1. The parameters listed below are tested using automatic test equipment to assure consistent electrical characterristics. The limits do not represent the ultimate performance limits of the device. Use of an optimized RF layout will improve many of the listed parameters.

LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

NE605

SA605

UNITS

MIN

TYP MAX MIN

TYP MAX

Mlxer/Osc section (ext LO= 300mV)

f1N

Input signal frequency

lose Crystal oscillator frequency

Noise figure at 4SMHz

500

500

MHz

1SO

1SO

MHz

s.o

s.o

dB

Third-order input intercept point

11 = 4S.O; f2 = 4S.06MHz

-10

-10

dBm

Conversion power gain

Matched 14.SdBV step-up

10.S

13

14.S

10

13

1S

dB

RF input resistance

son source Single-ended input

-1.7

3.5

4.7

-1.7

dB

3.0

4.7

kn

RF input capacitance Mixer output resistance

(Pin 20)

3.S

4.0

3.S

4.0

pF

1.3

1.5

1.2S

1.S

kn

IF section

IF amp gain Limiter gain Input limiting -3dB, R17 = 5.1k AM rejection
Audio level, R10 = 1OOk Unmuted audio level, R11 = 100k

son source 50Qsource Test at Pin 18 80%AM 1kHz 1SnF de-emphasis
1SOpF de-emphasis

39.7

39.7

dB

62.5

62.S

dB

-113

-113

dBm

30

34

42

29

34

43

dB

110

1SO

250

80

1SO

260 mVRMS

480

480

mV

THD SIN

SINAD sensitivity Total harmonic distortion Signal-to-noise ratio IF RSSI output, R9 = 100kn1
RSSI range RSSI accuracy IF input impedance IF output impedance Limiter input impedance Unmuted audio output resistance

RF level -118dB
No modulation for noise IF level= -118dBm IF level= -68dBm IF level= -18dBm R9 = 100kn Pin 16 Rg = 100k0 Pin 16

16

16

dB

-3S

-42

-34

-42

dB

73

73

dB

0

160

S50

0

160

650

mV

2.0

2.5

3.0

1.9

2.5

3.1

v

4.1

4.8

5.5

4.0

4.8

5.6

v

90

90

dB

�1.5

�1.5

dB

1.40

1.6

1.40

1.6

kn

0.85

1.0

0.85

1.0

kn

1.40

1.6

1.40

1.6

kn

58

58

kn

Muted audio output resistance

58

58

kn

,January 18, 1991

292

Signetics RF Communications
High performance low power mixer FM IF system in shrink small outline package

Product specification
NE/SA605SSOP

AC ELECTRICAL CHARACTERISTICS (Continued)

SYMBOL

PARAMETER

TEST CONDITIONS

RF/IF section (Int LO) Unmuted audio level System RSSI output

4.SV = Vee. RF level = -27dBm
4.SV =Vee. RF level = -27dBm

LIMITS

NE605

SA605

UNITS

MIN TYP MAX MIN TYP MAX

450

450

mVRMS

4.3

4.3

v

NOTE: 1. The generator source impedance is 500, but the NE/SA605 input impedance at Pin 18 is 15000. As a result, IF level refers to the actual
signal that enters the NE/SA605 input (Pin 8) which is about 21dB less than the "available power� at the generator.

CIRCUIT DESCRIPTION The NE/SA605 is an IF signal processing system suitable for second IF or single conversion systems with input frequency as high as 1GHz. The bandwidth of the IF amplifier is aboU140MHz, with 39.7dB(v) of gain from a 500 source. The bandwidth of the limiter is about 28MHz with about 62.SdB(v) of gain from a 500 source. However, the gain/bandwidth distribution is optimized for 455kHz, 1.5k0 source applications. The overall system is wellsuited to battery operation as well as high performance and high quality products of all types.
The input stage is a Gilbert cell mixer with oscillator. Typical mixer characteristics include a noise figure of 5dB, conversion gain of 13dB, and input third-order intercept of -1 OdBm. The oscillator will operate in excess of 1GHz in LJC tank configurations. Hartley or Colpitts circuits can be used up to 1OOMHz for xtal configurations. Butler oscillators are

recommended for xtal configurations up to 150MHz.
The output of the mixer is internally loaded with a 1.SkO resistor permitting direct connection to a 455kHz ceramic filter. The input resistance of the limiting IF amplifiers is also 1.5k0. With most 455kHz ceramic filters and many crystal filters, no impedance matching network is necessary. To achieve optimum linearity of the log signal strength indicator, there must be a 12dB(v) insertion loss between the first and second IF stages. If the IF filter or interstage network does not cause 12dB(v) insertion loss, a fixed or variable resistor can be added between the first IF output (Pin 16) and the interstage network.
The signal from the second limiting amplifier goes to a Gilbert cell quadrature detector. One port of the Gilbert cell is internally driven by the IF. The other output of the IF is ACcoupled to a tuned quadrature network. This

signal, which now has a 90� phase relationship to the internal signal, drives the other port of the multiplier cell.
Overall, the IF section has a gain of 90dB. For operation at intermediate frequencies greater than 455kHz, special care must be given to layout, termination, and interstage loss to avoid instability.
The demodulated output of the quadrature detector is available at two pins, one continuous and one with a mute switch. Signal attenuation with the mute activated is greater than 60dB. The mute inpU1 is very high impedance and is compatible with CMOS or TTL levels.
A log signal strength completes the circuitry. The output range is greater than 90dB and is temperature compensated. This log signal strength indicator exceeds the criteria for AMPs or TACs cellular telephone.
NOTE: dB(v) = 20log VourN1N

January 18, 1991

293

Signetics RF Communications
High performance low power mixer FM IF system in shrink small outline package

Product specification
NE/SA605SSOP

-25dB,

-10clB,

-29dB,

1500/50'2 PAD 50/Sllo PAD 929/Sllo PAD

-10.&dB, 50/50n PAD

-36dB, 156k/50n PAD

/,

IFT1

January 18, 1991

llNl-CIRCUIT ZSC2-1B

R8 39.2
-=- MUTE vcc

Automatic Test Circuit Component List

C1 47pF NPO Ceramic C2 180pF NPO Ceramic
cs 100nF .:t.10% Monollthlc Ceramic
C6 22pF NPO Ceramic C7 1nFCeramlc
ca 10.0pF NPO Ceramic
C9 100nF .:t.10% Monollthlc Ceramic C10 15�F Tantalum (minimum) C11 100nF .:t10% Monolithic Ceramic C12 15nF .:t10% Ceramic C13 150pF .:t.2% N1500 Ceramic C14 100nF .:t10% Monollthlc Ceramic C15 10pF NPO Ceramic C17 100nF .:t10% Monollthlc Ceramic C18 100nF .:t10% Monollthlc Ceramic

C21 C23 C25 C26 Flt 1 Flt2 IFT1
L1 L2 X1 R9 R17 R10
R11

100nF .:t.10% Monollthlc Ceramic 100nF .:t.10% Monollthlc Ceramic 100nF .:t.10% Monollthlc Ceramic 390pF .:t.10% Monollthlc Ceramic Ceramic Fiiter Murata SFG455A3 or equiv Ceramic Fiiter Murata SFG455A3 or equiv 455kHz 270�H TOKO #303LN-1129
300nH TOKOifjCB-1055Z 1.2�H Collora #1008CS 122
44.545MHz Crystal ICM4712701 100k .:t1% 1/4W Metal Fiim 5.1 k .:t5% 1/4W Carbon Compoaltlon 100k.:t1% 1/4W Metal Fiim (optional) 100k.:t1% 1/4W Metal Fiim (optional)

Figure 1. NE/SA605SSOP 45MHz Test Circuit (Relays as shown)

294

Signetics RF Communications
High performance low power mixer FM IF system in shrink small outline package

Product specification
NE/SA605SSOP

C15

C1
J.~ J CHzC2.___.__.1 INPUT

IFT1

r14

MUTE Vee RSSI AUDIO UNMUTED '="

OUTPUT

AUDIO

Application Component Ust

C1 47pF NPO Ceramic C2 180pF NPO Ceramic CS 100nF �10% Monolilhlc Ceramic C6 22pF NPO Ceramic C7 1nF Ceramic C8 10.0pF NPO Ceramic C9 100nF �10% Monolithic Ceramic c10 15�F Tantalum (minimum)
C11 100nF �10% Monolilhlc Ceramic C12 15nF �10% Ceramic C13 150pF �2% N1500 Ceramic C14 100nF �10% Monolllhlc Ceramic C15 10pF NPO Ceramic C17 100nF �10% Monolilhlc Ceramic C18 100nF �10% Monollthlc Ceramic

C21 C23 C25 C26 Fll1 Fll2 IFT 1
L1
u X1
R9 R17 R10
R11

1OOnF �10% Monollthic Ceramic 1OOnF �10% Monollthlc Ceramic 100nF �10% Monollthlc Ceramic 390pf �10% Monollthlc Ceramic Ceramic Fiiter Murata SFG45SA3 or equiv Ceramic Fiiter Murata SFG4SSA3 or equiv 455kHz 270�H TOKO #303LN�1129
300nH TOKO #5CB�1055Z 1.2�H Collcraft #1008CS 122
44.545MHz Cryatal ICM4712701 100k�1% 1/4W Metal Fiim 5.1 k .:t.5% 1/4W Carbon Composition 100k�1% 1/4W Metal Fiim (optional) 100k�1% 1/4W Metal Fiim (optional)

January 18, 1991

Figure 2. NE/SA605 45MHz Application Circuit 295

Signetics RF Communications
High performance low power mixer FM IFsystem in shrink small outline package

Product specification
NE/SA605SSOP

RF GENERATOR 45MHz
Vcc(+6)

NE605 DEMO BOARD AUDIO

C-MESSAGE

SCOPE

HP339A DISTORTION ANALVZER

Figure 3. NE/SAGOS Appllcatlon Circuit Test Set Up
NOTES:
1. C-message: The C-message filter has a peak gain of 100 for accurate measurements. Without the gain, the measurements may be affected by the noise of the scope and HP339 analyzer.
2. Ceramic filters: The ceramic filters can be 30kHz SFG455A3s made by Murata which have 30kHz IF bandwidth (they come in blue), or 16kHz CFU455Ds, also made by Murata (they come in black). All of our specifications and testing are done with the more wideband filter.
3. RF generator: Set your RF generator at 45.000MHz, use a 1kHz modulation frequency and a 6kHz deviation if you use 16kHz filters, or 8kHz if you use 30kHz filters.
4. Sensitivity: The measured typical sensitivity for 12dB SINAD should be 0.22�Vor-120dBm at the RF input. 5. Layout: The layout is very critical in the performance of the receiver. We highly recommend our demo board layout 6. RSSI: The smallest RSSI voltage (i.e., when no RF input is present and the input is terminated) is a measure of the quality of the layout and
design. If the lowest RSSI voltage is 250mV or higher, it means the receiver is in regenerative mode. In that case, the receiver sensitivity will be worse than expected. 7. Supply bypass and shielding: All of the inductors, the quad tank, and their shield must be grounded. A 10-15�F or higher value tantalum capacitor on the supply line is essential. A low frequency ESR screening test on this capacitor will ensure consistent good sensitivity in production. A 0.1 �F bypass capacitor on the supply pin, and grounded near the 44.545MHz oscillator improves sensitivity by 2-3dB. B. R5 can be used to bias the oscillator transistor at a higher current for operation above 45MHz. Recommended value is 22kn, but should not be below 1Okn.

January 18, 1991

296

Signetics RF Communications
High performance low power mixer FM IF system in shrink small outline package

Product specification
NE/SA605SSOP

20

Aub10 R~F = 1~4mVR~

0

1.-""

L

~

L

I"!..~

IL

~ ~
~ :'S:

v L

' ~

~

~

~

L
L .L ._

THDNOISE
I,........

h..

~

AM(80%)

~ LJ

'X_

_L ~

v L

~ ~

~ RSSI

~

(Volts) _L

NOISE

[Z

-100 ~

-130

-110

-80

-70

-

-30

RF INPUT LEVEL (dBm) Figure 4. NE605 Appllcatlon Board at 25�C

Rf :45MHz IF=455kHz _
Vcc=&V _ RSSI
s (Volts)

......i-..

.J.

.L .L

4

L

ll.

~

0

-10

10

TOP VIEW � COMPONENT SIDE

TOP VIEW� SOLDER SIDE

January 18, 1991

297

Slgnetlcs RF Communications
High performance low power mixer FM IF system

Product specification
NE/SA615

DESCRIPTION
The NE/SA615 is a consumer monolithic lowpower FM IF system incorporating a mixer/oscillator, two limiting intermediate frequency amplifiers, quadrature detector, muting, logarithmic received signal strength indicator (RSSI), and voltage regulator. The NE/SA615 is available in 20-lead dual-in-line plastic and 20-lead SOL (surface-mounted miniature package).
The NE/SA605 and NE/SA615 are functionally the same device types. The difference between the two devices lies in the guaranteed spcifications. the NE/SA615 has a higher Ice. lower input third order intercept point, lower conversion mixer gain, lower limiter gain, lower AM rejection, lower SINAD, higher THD, and higher RSSI error than the NE/SA605. Both the NE/SA605 and NE/SA615 devices will meet the EIA specifications for AMPS and TACS cellular radio applications.

FEATURES
�Low power consumption: 5.7mA typical at 6V
� Mixer input to >500MHz
� Mixer conversion power gain of 13dB at 45MHz
� Mixer noise figure of 4.6dB at 45MHz
� XTAL oscillator effective to 150MHz (L.C. oscillator to 1GHz local oscillator can be injected)
� 102dB of IF Amp/Limiter gain
� 25MHz limiter small signal bandwidth � Temperature compensated logarithmic
Received Signal Strength Indicator (RSSI) with a dynamic range in excess of 90dB � Two audio outputs - muted and unmuted � Low external component count; suitable for crystal/ceramic/LC filters � ESD hardened

PIN CONFIGURATION
01 and N Packages

XTALOSC 3 XTALOSC 4
MUTE1N 5
RSSlouT

MIXER OUT IFAMP DECOUPLING IF AMP IN IFAMP DECOUPLING
LIMITER IN LIMITER DECOUPLING LIMITER DECOUPLING

NOTE:
1. Large SO (SOL) package only.

APPLICATIONS
� Consumer cellular radio FM IF � Single conversion VHF/UHF receivers � SCA receivers � RF level meter � Spectrum analyzer � Instrumentation � FSK and ASK data receivers �Log amps � Wideband low current amplification

ORDERING INFORMATION
DESCRIPTION 20-Pin Plastic DIP 20-Pin Plastic SOL (Surface-mount) 20-Pin Plastic DIP 20-Pin Plastic SOL (Surface-mount)

TEMPERATURE RANGE
oto +70�C oto +70�C
-40 to +85�C
-40 to +85�C

ORDER CODE NE615N NE615D SA615N SA615D

November 1, 1990

298

853-1402 00903

Signetics RF Communications
High performance low power mixer FM IF system
BLOCK DIAGRAM

Product specification
NE/SA615

ABSOLUTE MAXIMUM RATINGS

SYMBOL

PARAMETER

Vee Single supply voltage

Tsro Storage temperature range

TA Operating ambienttemperature range NE615

SA615

BJA Thennal impedance

D package

N package

RATING 9
-65 to +150 0 to +70 -40to+85 90 75

UNITS
v oc oc oc
�CIW
�CIW

DC ELECTRICAL CHARACTERISTICS Vee= +6V, TA= 25�C; unless otherwise stated.

SYMBOL

PARAMETER

Vee Power supply voltage range Ice DC current drain
Mute switch input threshold (ON) (OFF)

TEST CONDITIONS

LIMITS

NE/SA615

MIN

TYP

MAX

4.5

8.0

5.7

7.4

1.7

1.0

UNITS
v
mA
v v

November 1, 1990

299

Signetics RF Communications
High performance low power mixer FM IF system

Product specification
NE/SA615

AC ELECTRICAL CHARACTERISTICS
Typical reading at TA= 25�C; Vee= +6V, unless otherwise stated. RF frequency= 45MHz +14.SdBV RF input step-up; IF frequency= 455kHz; R17 = 5.1k; RF level= -45dBm; FM modulation = 1kHz with �8kHz peak deviation. Audio output with C-message weighted filter and de-emphasis capacitor. Test circuit Figure 1. The parameters listed below are tested using automatic test equipment to assure consistent electrical characterristics. The limits do not represent the ultimate performance limits of the device. Use of an optimized RF layout will improve many of the listed parameters.
LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

NE/SA615

UNITS

MIN

TVP

MAX

Mixer/Osc section (ext LO= 300mV)

f1N lose

Input signal frequency Crystal oscillator frequency Noise figure at 45MHz

500

MHz

150

MHz

5.0

dB

Third-order input intercept point

f1 = 45.00; f2 = 45.0SMHz

-12

dBm

Conversion power gain

Matched 14.SdBV step-up

8.0

13

dB

son source

-1.7

dB

RF input resistance

Single-ended input

3.0

4.7

kn

RF input capacitance

3.5

4.0

pF

Mixer output resistance

(Pin 20)

1.25

1.50

kn

IF section

IF amp gain

son source

39.7

dB

limiter gain

son source

62.5

dB

lnputlimiting -3dB, R17 = 5.1 k AM rejection

Test at Pin 18 80%AM 1kHz

-109

dBm

25

33

43

dB

Audio level, R10 = 1OOk Unmuted audio level, R11 = 100k

15nF de-emphasis 150pF de-emphasis

60

1SO

260 mVRMS

530

mV

SINAD sensitivity

RF level -118dB

12

dB

THD Total harmonic distortion

-30

-42

dB

S/N Signal-to-noise ratio

No modulation for noise

68

dB

IF RSSI output, R9 = 100kQ1

IF level= -118dBm IF level= -68dBm IF level= -18dBm

0

160

BOO

mV

1.7

2.5

3.3

v

3.6

4.8

5.6

v

RSSI range

Rg = 100kn Pin 16

80

dB

RSSI accuracy IF input impedance

R9 = 100kn Pin 16

�2

dB

1.40

1.6

kn

IF output impedance

0.85

1.0

kn

limiter intput impedance

1.40

1.6

kn

MIN

TVP

MAX

Unmuted audio output resistance

58

kn

Muted audio output resistance

58

kn

RF/IF section (int LO)

Unmuted audio level System RSSI output

4.5V =Vee. RF level = -27dBm 4.5V =Vee. RF level = -27dBm

4SO

mVRMS

4.3

v

NOTE: 1. The generator source impedance is son, but the NE/SA605 input impedance at Pin 18 is 1soon. As a result, IF level refers to the actual
signal that enters the NE/SA605 input (Pin 8) which is about 21dB less than the "available power" at the generator.

November 1, 1990

300

Signetics RF Communications
High performance low power mixer FM IF system

Product specification
NE/SA615

CIRCUIT DESCRIPTION The NE/SA615 is an IF signal processing system suitable for second IF or single conversion systems with input frequency as high as 1GHz. The bandwidth of the IF amplifier is about 40MHz, with 39. 7dB(v) of gain from a 50'2 source. The bandwidth of the limiter is about 28MHz with about 62.5dB(v) of gain from a 50'2 source. However, the gain/bandwidth distribution is optimized for 455kHz, 1.5k'2 source applications. The overall system is well-suited to battery operation as well as high performance and high quality products of all types.
The input stage is a Gilbert cell mixer with oscillator. Typical mixer characteristics include a noise figure of 5dB, conversion gain of 13dB, and input third-order intercept of -10dBm. The oscillator will operate in excess of 1GHz in LJC tank configurations. Hardey or Colpitts circuits can be used up to 1OOMHz for x-tal configurations. Buder oscillators are

recommended for x-tal configurations up to 150MHz.
The output of the mixer is internally loaded with a 1.5k'2 resistor permitting direct connection to a 455kHz ceramic filter. The input resistance of the limiting IF amplifiers is also 1.5k'2. With most 455kHz ceramic filters and many crystal filters, no impedance matching network is necessary. To achieve optimum linearity of the log signal strength indicator, there must be a 12dB(v) insertion loss between the first and second IF stages. If the IF filter or interstage network does not cause 12dB(v) insertion loss, a fixed or variable resistor can be added between the first IF output (Pin 16) and the interstage network.
The signal from the second limiting amplifier goes to a Gilbert cell quadrature detector. One port of the Gilbert cell is internally driven by the IF. The other output of the IF is AC-coupled to a tuned quadrature network.

This signal, which now has a 90� phase relationship to the internal signal, drives the other port of the multiplier cell.
Overall, the IF section has a gain of 90dB. For operation at intermediate frequencies greater than 455kHz, special care must be given to layout, termination, and interstage loss to avoid instability.
The demodulated output of the quadrature detector is available at two pins, one continuous and one with a mute switch. Signal attenuation with the mute activated is greater than 60dB. The mute input is very high impedance and is compatible with CMOS or TTL levels.
A log signal strength completes the circuitry. The output range is greater than 90dB and is temperature compensated. This log signal strength indicator exceeds the criteria for AMPs or TACs cellular telephone.
NOTE: dB(v) = 201og VouTNIN

November 1, 1990

301

Signetics RF Communications
High performance low power mixer FM IF system

Product specification
NE/SA615

-25dB,

-10dB,

-29dB,

1500/Sllo PAD 50/SOn PAD 929/SOn PAD

-10.6dB, 50/SOnPAD

-36dB, 156k/50n PAD

IFTI

MINI-CIRCUIT ZSC2-1B

RB 39.2

= MUTE

Vee

RSSI AUDIO UNMUTED

OUTPUT

AUDIO

November 1, 1990

Automatic Test Circuit Component Uat

C1 100pF NPO Ceramic C2 390pF NPO Ceramic CS 100nF :t10% Monollthlc Ceramic C6 22pF NPO Ceramic C7 1nFCeramlc CB 10.0pF NPO Ceramic C9 100nF :t10% Monolithic Ceramic C10 15�F Tantalum (minimum)
C11 100nF :t10% Monolithic Ceramic C12 15nF �10% Ceramic C13 150pF �2% N1500 Ceramic C14 100nF :t10% Monollthlc Ceramic C15 10pF NPO Ceramic C17 100nF �10% Monollthlc Ceramic C18 100nF �10% Monollthlc Ceramic

C21 C23 C25 Flt1 Fll2 IFT 1
L1 L2
X1 R9 R17 R10 R11

100nF �10% Monolithic Ceramic 100nF �10% Monolithic Ceramic 100nF �10% Monollthlc Ceramic Ceramic Fiiter Murata SFG455A3 or equiv Ceramic Fiiter Murata SFG455A3 or equiv
455kHz (Ce =1BOpF) Toko RMC-2A6597H
147-160nH Coilcraft UNl-10/142-04J08S 3.3�H nominal
Toko 292CNS-T1046Z 44.545MHz Crystal ICM4712701 100k �1% 1/4W Metal Fiim 5.1k �5% 1/4W Carbon Composition 100k �1% 1/4W Metal Fiim (optional)
100k:t1% 1/4W Metal Fiim (optional)

Figure 1. NE/SA615 45MHz Test Circuit (Relays as shown)

302

Signetics RF Communications
High performance low power mixer FM IF system

Product specification
NE/SA615

Rt7 5.tk

CtS

Ct
.�....._____'
INPUT

IFT1

IC14

MUlE Vee RSSI AUDIO UNMUTED =

OUTPUT

AUDIO

Appllcatlon Component List

C1 100pF NPO Ceramic C2 390pF NPO Ceramic CS 100nF .t.10% Monolithic Ceramic C& 22pF NPO Ceramic C7 1nF Ceramic C8 10.0pF NPO Ceramic C9 100nF .t.10% Monollthlc Ceramic c10 1S�F Tantalum (minimum)
C11 100nF .t.10% Monolithic Ceramic C12 1SnF .t.10% Ceramic C13 1SOpF .t.2% N1SOO Ceramic C14 100nF .t.10% Monolithic Ceramic C1S 10pF NPO Ceramic C17 100nF .t.10% Monollthlc Ceramic C18 100nF .t.10% Monollthlc Ceramic

C21 C23 C2S Flt 1 Flt2 IFT1
L1 L2
X1 R9 R17 RS R10 R11

100nF .t.10% Monollthlc Ceramic 100nF .t.10% Monollthlc Ceramic 100nF .t.10% Monollthlc Ceramic Ceramic Filter Murals SFG45SA3 or equiv Ceramic Filter Murals SFG45SA3 or equiv
455kHz (Ce =180pF) Toko RMC-2A6597H
147-160nH Collcralt UNl-10/142-04J08S 3.3�H nominal
Toko 292CNS-T1046Z 44.54SMHz Crystal ICM4712701 100k.t.1% 1/4W Metal Fiim S.1 k .t.S% 1/4W Carbon Composition Not Used In Application Board (see Note 8) 100k.t.1% 1/4W Metal Fiim (optional)
100k .t.1% 1/4W Metal Film (optional)

November 1, 1990

Figure 2. NE/SA61S 45MHz Application Circuit 303

Signetics RF Communications
High performance low power mixer FM IF system

Product specification
NE/SA615

RF GENERATOR 45MHz
Vcc(+6)

NE615 DEMO BOARD AUDIO

C-MESSAGE

SCOPE

HP339A DISTORTION ANALYZER

Figure 3. NE/SA615 Application Circuit Test Set Up
NOTES: 1. C-message: The C-message filter has a peak gain of 100 for accurate measurements. Without the gain, the measurements may be af-
fected by the noise of the scope and HP339 analyzer. 2. Ceramic filters: The ceramic filters can be 30kHz SFG455A3s made by Murata which have 30kHz IF bandwidth (they come in blue), or
16kHz CFU455Ds, also made by Murata (they come in black). All of our specifications and testing are done with the more wideband filter. 3. RF generator: Set your RF generator at 45.000MHz, use a 1kHz modulation frequency and a 6kHz deviation if you use 16kHz filters, or
8kHz if you use 30kHz filters. 4. Sensitivity: The measured typical sensitivity for 12dB SINAD should be 0.35�Vor-116dBm at the RF input. 5. Layout: The layout is very critical in the performance of the receiver. We highly recommend our demo board layout. 6. RSSI: The smallest RSSI voltage (i.e., when no RF input is present and the input is terminated) is a measure of the quality of the layout and
design. If the lowest RSSI voltage is 250mV or higher, it means the receiver is in regenerative mode. In that case, the receiver sensitivity will be worse than expected. 7. Supply bypass and shielding: All of the inductors, the quad tank, and their shield must be grounded. A 10-15�F or higher value tantalum capacitor on the supply line is essential. A low frequency ESR screening test on this capacitor will ensure consistent good sensitivity in production. A 0.1 �F bypass capacitor on the supply pin, and grounded near the 44.545MHz oscillator improves sensitivity by 2-3dB. 8. RS can be used to bias the oscillator transistor at a higher current for operation above 45MHz. Recommended value is 221<.Q, but should not
be below 1Ok!l.

November 1, 1990

304

Signetics RF Communications
High performance low power mixer FM IF system

Product specification
NE/SA615

20

I I I I

AUDIO REF= 174mVRMS

0

~

~

""h. ~

~ ~

~ ~

' _.)._

~

~

L

!"!..

~

~ L

'L__

L IL L
~
L
1
._

L
-+
THDNOISE AM(80%)

.L ~

v L

~ ~

i r RSSI
(Vo'.'.L> L

~

z

-11111 ~

-130

-110

.....,

-70

-

NOISE
J_
-30

RF INPUT LEVEL (dBm)
Figure 4. NE615 Appllcallon Board at 2s0 c

RF:45Mllz IF�455kllz
Yee .av
-"-

_
_
5

RSSI (Volta)

_-L'-
_J_ _J_ ~ I/_

-

0

-10

10

November 1, 1990

305

Signetics RF Communications
High performance low power mixer FM IF system

Product specification
NE/SA615

C21

m 0 IN~UT

FLT10 ~ 0~~~2 IFT1

C2 L1 a:::::D"i a:::::D

CC14

if9loQ

lc1s 0 GND

!~s~oce=lo~l ~=XcTaALveo

~=c13
�� tD'"'

DATA
OUT

0

SIGNETICS NE615
0 GND

& CD C10

~~ielOOOI

SW1
0 Vee

0 RSSI

0 AUDIO OUT GND

Figure 5. Component Placement for NE615 Appllcallon Circuit

November 1, 1990

306

Signetics RF Communications
High performance low power mixer FM IF system

Product specification
NE/SA615

.:�� :
��
TOP VIEW

0
0 .:��: ��

� �

���
��

� �

.:� �:
��
November 1, 1990

�� ����� ��
BOTTOM VIEW
Figure 6. Layout for NE/SA615 Application Board 307

Slgnetlcs RF Communications
High performance low power mixer FM IF system in shrink small outline package

Product specification
NE/SA615 (SSOP)

DESCRIPTION The NE/SA615 is a high performance monolithic low-power FM IF system incorporating a mixer/oscillator, two limiting intermediate frequency amplifiers, quadrature detector, muting, logarithmic received signal strength indicator (RSSI), and voltage regulator. The NE/SA615 combines the functions of Signetics' NE602 and NE604A, but features a higher mixer input intercept point, higher IF bandwidth (25MHz) and temperature compensated RSSI and limiters permitting higher performance application. The NE/SA615 is available in 20-lead dual-inline plastic and 20-lead SOL (surfacemounted miniature package).
The NE/SA605 and NE/SA615 are functionally the same device types. The difference between the two devices lies in the guaranteed specifications. The NE/SA615 has a higher Ice. lower input third order intercept point, lower conversion mixer gain, lower limiter gain, lower AM rejection, lower SINAD, higher THO, and higher RSSI error than the NE/SA615. Both the NE/SA605 and NE/SA615 devices will meet the EIA specifications for AMPS and TACS cellular radio applications.

FEATURES �Low power consumption: 5.7mA typical at
6V
�Mixer input to >!iOOMHz
�Mixer conversion power gain of 13dB at 45MHz
�Mixer noise figure of 4.6dB at 45MHz
�XTAL oscillator effective to 150MHz (LC. oscillator to 1GHz local oscillator can be injected)
�102dB of IF Amp/Limiter gain
�25MHz limiter small signal bandwidth
�Temperature compensated logarithmic Received Signal Strength Indicator (RSSI) with a dynamic range in excess of 90dB
�Two audio outputs - muted and unmuted
�Low external component count; suitable lor crystal/ceramic/LC filters
�Excellent sensitivity: 0.22fLV into 50'1 matching network lor 12dB SINAD (Signal to Noise and Distortion ratio) for 1kHz tone with RF at 45MHz and IF at 455kHz
�SA615 meets cellular radio specifications
�ESD hardened

PIN CONFIGURATION
SSOP Package
llXEROUT
18 lfE~'tfuPLING
18 IFAMPIN
17 lfE~'tfuPLING

RSSlouT 7
MUTED AU&'.~ a
Ai=6t~ 9
QUADRATURE 10 IN

LIMITER DECOUPLING LillTER DECOUPLING 11 LillTER OUT

NOTE: See back page for package dimensions

APPLICATIONS �Cellular radio FM IF �High performance communications
receivers �Single conversion VHF/UHF receivers �SCA receivers �RF level meter �Spectrum analyzer �Instrumentation �FSK and ASK data receivers �Log amps �Wideband low current amplification

ORDERING INFORMATION DESCRIPTION
20-Pin Plastic SSOP 20-Pin Plastic SSOP

TEMPERATURE RANGE
o to +70�C
-40to +85�C

ORDER CODE NE615DK SA615DK

January 18, 1991

308

853-1533 01494

Signetics RF Communications
High performance low power mixer FM IF system in shrink small outline package
BLOCK DIAGRAM

Product specification
NE/SA615 (SSOP)

ABSOLUTE MAXIMUM RATINGS

SYMBOL

PARAMETER

Vee Single supply voltage

TsTG Storage temperature range

TA Operating ambient temperature range NE615

SA615

9JA Thermal impedance

SSOP package

RATING 9
~5!0+150
o to +70
-40!0 +85 117

UNITS
v oc oc oc
�C/W

DC ELECTRICAL CHARACTERISTICS
Vee =+6V, = TA 25�C; unless otherwise stated.

SYMBOL

PARAMETER

Vee Power supply voltage range Ice DC current drain
Mute switch input threshold (ON) (OFF)

TEST CONDITIONS

LIMITS

NE/SA615

MIN

TYP

MAX

4.5

8.0

5.7

7.4

1.7

1.0

UNITS
v
mA
v v

January 18, 1991

309

Signetics RF Communications
High performance low power mixer FM IF system in shrink small outline package

Product specification
NE/SA615 (SSOP)

AC ELECTRICAL CHARACTERISTICS
..av, T,. = 25�C; Vee= unless otherwise stated. RF frequency= 45MHz + 14.5dBV RF input step-up; IF frequency= 455kHz; R17 = 5.1k; RF
level = -45dBm; FM modulation = 1kHz with �8kHz peak deviation. Audio output with C-message weighted filter and de-emphasis capacitor. Test circuit Figure 1. The parameters listed below are tested using automatic test equipment to assure consistent electrical characterristics. The limits do not represent the ultimate performance limits of the device. Use of an optimized RF layout will improve many of the listed parameters.
LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

NE/SA615

UNITS

Mlxer/Osc section (ext LO =300mV)

MIN

TYP

MAX

f1N Input signal frequency
lose Crystal oscillator frequency
Noise figure at 45MHz

500

MHz

150

MHz

5.0

dB

Third-order input intercept point

11 = 45.00; 12 = 45.06MHz

-12

dBm

Conversion power gain

Matched 14.5dBV step-up

8.0

13

dB

son source

-1.7

dB

RF input resistance

Single-ended input

3.0

4.7

kn

RF input capacitance

3.5

4.0

pF

Mixer output resistance

(Pin 20)

1.25

1.50

kn

IF section

IF amp gain

son source

39.7

dB

Limiter gain

son source

62.5

dB

Input limiting -3dB, R17 = 5.1 k AM rejection

Test at Pin 18 80%AM1kHz

-109

dBm

25

33

43

dB

Audio level, R10 = 100k

15nF de-emphasis

60

150

260 mVRMS

Unmuted audio level, R11 = 100k SINAD sensitivity

150pF de-emphasis RF level -118dB

530

mV

12

dB

THO Total harmonic distortion

-30

-42

dB

SIN Signal-to-noise ratio

No modulation for noise

68

dB

IF RSSI output, Re= 100kn1

IF level= -118dBm IF level = -OSdBm IF level= -18dBm

0

160

BOO mV

1.7

2.5

3.3

v

3.6

4.8

5.8

v

RSSI range

Re=100knPin16

80

dB

RSSI accuracy

Re=100knPin16

�2

dB

IF input impedance

1.40

1.6

kn

IF output impedance

0.85

1.0

kn

Limiter intput impedance

1.40

1.6

kn

Unmuted audio output resistance

58

kn

Muted audio output resistance

58

kn

RFnF section (Int LO)

Unmuted audio level System RSSI output

4.5V =Va;, RF level = -27dBm 4.5V = Va;, RF level = -27dBm

450

mVRMS

4.3

v

NOTE: 1. The generator source impedance is son, but the NE/SA605 input impedance at Pin 18 is 1500n. As a result, IF level refers to the actual
signal that enters the NE/SA605 input (Pin 8) which is about 21dB less than the "available power" at the generator.

January 18, 1991

310

Signetics RF Communications
High performance low power mixer FM IF system in shrink small outline package

Product specification
NE/SA615 (SSOP)

CIRCUIT DESCRIPTION The NEISA615 is an IF signal processing system suitable for second IF or single conversion systems with input frequency as high as 1GHz. The bandwidth of the IF amplifier is about 40MHz, with 39.7dB(v) of gain from a 50'2 source. The bandwidth of the limiter is about 28MHz with about 62.5dB(v) of gain from a 50'2 source. However, the gain/bandwidth distribution is optimized for 455kHz, 1.5kn source applications. The overall system is wellsuited to battery operation as well as high performance and high quality products of all types.
The input stage is a Gilbert cell mixer with oscillator. Typical mixer characteristics include a noise figure of 5dB, conversion gain of 13dB, and input third-order intercept of -10dBm. The oscillator will operate in excess of 1GHz in UC tank configurations. Hartley or Colpitts circuits can be used up to 1OOMHz for xtal configurations. Butler

oscillators are recommended for xtal configurations up to 150MHz.
The output of the mixer is internally loaded with a 1.5kn resistor permitting direct connection to a 455kHz ceramic filter. The input resistance of the limiting IF amplifiers is also 1.5k'2. With most 455kHz ceramic filters and many crystal filters, no impedance matching network is necessary. To achieve optimum linearity of the log signal strength indicator, there must be a 12dB(v) insertion loss between the first and second IF stages. If the IF filter or interstage network does not cause 12dB(v) insertion loss, a fixed or variable resistor can be added between the first IF output (Pin 16) and the interstage network.
The signal from the second limiting amplifier goes to a Gilbert cell quadrature detector. One port of the Gilbert cell is internally driven by the IF. The other output of the IF is ACcoupled to a tuned quadrature network. This

signal, which now has a 90� phase relationship to the internal signal, drives the other port of the multiplier cell.
Overall, the IF section has a gain of 90dB. For operation at intermediate frequencies greater than 455kHz, special care must be given to layout, termination, and interstage loss to avoid instability.
The demodulated output of the quadrature detector is available at two pins, one continuous and one with a mute switch. Signal attenuation with the mute activated is greater than 60dB. The mute input is very high impedance and is compatible with CMOS or TIL levels.
A log signal strength completes the circuitry. The output range is greater than 90dB and is temperature compensated. This log signal strength indicator exceeds the criteria for AMPs or TACs cellular telephone.
NOTE: dB(v) = 201og VourN1N

January 18, 1991

311

Signetics RF Communications
High performance low power mixer FM IF system in shrink small outline package

PrQduct specification
NE/SA615 (S$0P)

-10dB,

-29dB,

50/SOn PAD 929/SOn PAD

-10.&dB, 50/SOn PAD

-38dB, 158k/50n PAD

IFT1

January 18, 1991

~
11111-CIRCUIT ZSCZ-18

''C" WEIGHTED

118

AUDIO MEACSIURRCEUMITENT

IC14

38.2

Vee -:- MUTE

RSSI AUDIO UNllllTED

OUTPUT

AUDIO

Automatic Teat Circuit Component List

C1 47pF NPO Ceramic C2 180pF NPO Ceramic CS 100nF .:1:10% Monolithic Ceramic C8 22pF NPO Ceramic C7 1nFCeramlc CB 10.0pF NPO Ceramic C9 100nF .:1:10% Monolithic Ceramic C10 15.,.F Tantalum (minimum) C11 100nF .:1:10% Monolithlc Ceramic C12 15nF .:1:10% Ceramic C13 150pF .�2% N1500 Ceramic C14 100nF .:1:10% Monolithic Ceramic C15 10pF NPO Ceramic C17 100nF .:1:10% Monolithic Ceramic C18 100nF .:1:10% Monolithic Ceramic

C21 C23
C25 C28 Flt 1 Flt2
IFT1 L1 L2
X1
R9
R17 R10
R11

100nF .:1:10% Monolithic Ceramic 100nF .:1:10% Monolithic Ceramic 100nF .:1:10% Monolithic Ceramic 390pF :t.10% Monolithic Ceramic Ceramic Fiiter Murata SFG4SSA3 or equiv Ceramic Fiiter Murata SFG45SA3 or equiv 45SkHz 270�H TOKO #303LN-1129
300nH TOKO #SCB�10SSZ
1.2�H Collcraft #1 ooacs 122
44.545MHzCryatal ICM4712701 100k :t.1% 1/4W Metal Fiim S.1k:t.5% 1/4WCarbon Composition 100k :t.1% 1/4W Metal Fiim (optional)
100k :t.1% 1/4W Metal Fiim (optional)

Figure 1. NE/SA61SSSOP 4SMHz Teat Circuit (Relays aa shown)

312

Signetics RF Communications
High performance low power mixer FM IF system in shrink small outline package

Product specification
NE/SA615 (SSOP)

C15

IFT1

IC14

llUTE Yee ASSI AUDIO UNMUTED -=

OUTPUT

AUDIO

Appllcatlon Component Ust

C1 47pF NPO Ceramic C2 180pF NPO Ceramic CS 100nF .:t.10% Monollthlc Ceramic C6 22pF NPO Ceramic C7 1nF Ceramic C8 10.0pF NPO Ceramic C9 100nF .:t.10% Monollthlc Ceramic C10 15id' Tantalum (minimum) C11 100nF .:t.10% Monollthlc Ceramic C12 15nF .:t.10% Ceramic C13 150pF .:t.2% N1500 Ceramic C14 100nF .:t.10% Monollthlc Ceramic C15 10pF NPO Ceramic C17 100nF .:t.10% Monollthlc Ceramic C18 100nF .:t.10% Monollthlc Ceramic

C21 C23 C25 C26 Flt 1 Flt2 IFT1
L1 L2 X1 R9 R17 R10
R11

100nF .:t.10% Monollthlc Ceramic 100nF .:t.10% Monollthlc Ceramic
100nF .:t.10% Monolithic Ceramic 390pF .:t.10% Monolithic Ceramic Ceramic Fiiter Murata SFG455A3 or equiv Ceramic Fiiter Murata SFG455A3 or equiv 455kHz 270�H TOKO #303LN�1129
300nH TOKO #5CB-1055Z
1.2�H Colleran #1 ooacs 122
44.545MHz Crystal ICM4712701 1OOk .:t.1% 1/4W Metal Fiim 5.1k �5% 1/4W Carbon Composition 100k �1% 1/4W Metal Fiim (optional)
100k �1% 1/4W Metal Fiim (optional)

January 18, 1991

Figure 2. NE/SA615 45MHz Application Circuit 313

Signetics RF Communications
High performance low power mixer FM IF system in shrink small outline package

Product specification
NE/SA615 (SSOP)

RF GENERATOR 45MHz
Vcc(+6)

NE605 DEMO BOARD AUDIO

C-MESSAGE

SCOPE

HP339A DISTORTION ANALVZER

Figure 3. NE/SA615 Application Circuit Test Set Up
NOTES: 1. C-message: The C-message filter has a peak gain of 100 for accurate measurements. Without the gain, the measurements may be
affected by the noise of the scope and HP339 analy2er. 2. Ceramic filters: The ceramic filters can be 30kHz SFG455A3s made by Murata which have 30kHz IF bandwidth (they come in blue). or
16kHz CFU455Ds, also made by Murata (they come in black). All of our specifications and testing are done with the more wideband filter. 3. RF generator: Set your RF generator at 45.000MHz, use a 1kHz modulation frequency and a. 6kHz deviation if you use 16kHz filters, or
8kHz if you use 30kHz filters. 4. Sensitivity: The measured typical sensitivity for 12dB SINAD should be 0.22�V or-120dBm at the RF input. 5. Layout: The layout is very critical in the performance of the receiver. We highly recommend our demo board layout 6. RSSI: The smallest RSSI voltage (i.e., when no RF input is present and the input is terminated) is a measure of the quality of the layout and
design. If the lowest RSSI voltage is 250mV or higher, it means the receiver is in regenerative mode. In that case, the receiver sensitivity will be worse than expected. 7. Supply bypass and shielding: All of the inductors, the quad tank, and their shield must be grounded. A 10-15�F or higher value tantalum capacitor on the supply line is essential. A low frequency ESR screening test on this capacitor will ensure consistent good sensitivity in production. A 0.1�F bypass capacitor on the supply pin, and grounded near the 44.545MHz oscillator improves sensitivity by 2-3dB. 8. R5 can be used to bias the oscillator transistor at a higher current for operation above 45MHz. Recommended value is 221<'2, but should not be below 1Okn.

January 18, 1991

314

Signetics RF Communications
High performance low power mixer FM IF system in shrink small outline package

Product specification
NE/SA615 (SSOP)

20

AU1Dlo R~F = 1~4mVR~

J.t"'.".'.:

L

L""1

!""..

L

h::s~ : ~ ~ ~

~

x

~

~

IL

v2l
-L
1
L
~

-THDNOISE AM (80%)

-r~ ~

~

z ~

~ is:

RSSI L

..........

NOISE

(Volts) ~

l

L

-100 ~

-130

-110

-90

-70

-so

-30

RF INPUT LEVEL (dBm)

Figure 4. NE615 Application Board at 25�C

RF:45MHz -

IF=455kHz _

Vcc=6V _

-'-

RSSI s (Volts)

t
- _J_ ll_

......

-10

10

TOP VIEW - COMPONENT SIDE

TOP VIEW - SOLDER SIDE

January 18, 1991

315

Slgnetlcs RF Communications
Reviewing key areas when designing with the NE605

Application note
AN1994

Author: Alvin K. Wong
INTRODUCTION
This application note addresses key information that is needed when designing with the NE605. Since the NE602 and the NE604 are closely related to the NE605, a brief overview of these chips will be helpful. Additionally, this application note will divide the NE605 into four main blocks where a brief theory of operation, important parameters, specifications, tables and graphs of performance will be given. A question & answer section is included at the end. Below is an outline of this application note:
I. BACKGROUND
- History of the NE605 - Related app. notes
II. OVERVIEW OF THE NE605
- Mixer Section RF section Local osc. section Output of mixer Choosing the IF frequency Performance graphs of mixer
- IF Section IF amplifier IF limiter Function of IF section Important parameters of IF section 5. Limiting 6. AM rejection 7. AM to PM conversion B. Interstage loss IF noise figure Performance graphs of IF section
- Demodulator Section
- Output Section Audio and unmuted audio RSSI output Performance graphs of output section
Ill.Question & Answers
I. BACKGROUND
History of the NE605
Before the NE605was made, the NE602 (double-balanced mixer and oscillator) and the NE604 (FM IF system) existed. The combination of these two chips make up a high performance low cost receiver. Soon

after the NE605 was created to be a one chip solution, using a newer manufacturing process and design. Since the newer process and design in the NE605 proved to be better in performance and reliability, it was decided to make the NE602 and the NE604 under this new process. The NE602A and the NE604A were created. To assist the cost-conscious customer, Signetics also offered an inexpensive line of the same RF products: the NE612, NE614, and NE615.
Because the newer process and design proved to be better in performance and reliability, the older chips are going to be discontinued. Therefore, only the NE602A, NE612A, NE604A, NE614A, NE605and NE615 will be available.
Figure 1 shows a brief summary of the RF chips mentioned above. Under the newer process, minor changes were made to improve the perf9rmance. A designer, converting from the NE602 to the NE602A, should have no problem with a direct switch. However, switching from the NE604 to the NE604A, might require more attention. This will depend on how good the original design was in the system. In the "Questions & Answers" section, the NE604 and NE604A are discussed in greater detail. This will help the designer, who used the NE604 in their original design, to switch to the "A" version. In general, a direct switch to the NE604A is simple.
Related Application Notes
There have been many application notes written on the NE602 and NE604A. Since the combination of those parts is very similar to the NE605, many of the ideas and applications still apply. In addition, many of the topics discussed here will also apply to the NE602A and NE604A.
Table 1 (see back of app note) shows the application notes available to the designer. They can be found in either the Signetics Linear Data Manual, Volume 1, or the Signetics RF Communications Handbook. Your local PhilipsComponents-Signetics sales representative can provide you with copies of these publications, or you can contact Signetics Publication Services.

Figure 1. Overview of Selected RF Chips
II. OVERVIEW OF THE NE605
In Figure 2, the NE605 is broken up into lour main areas; the mixer section, the IF section, the demodulator section and the output section. The information contained in each of the four areas focuses on important data to assist you with the use of the NE605 in any receiver application.
Mixer Section
There are three areas of interest that should be addressed when working with the mixer section. The RF signal, LO signal and the output. The function of the mixer is to give the sum/difference of the RF and LO frequencies to get an IF frequency out. This mixing of frequencies is done by a Gilbert Cell four quadrant multiplier. The Gilbert Cell is a differential amplifier (Pins 1 and 2) which drives a balanced switching cell.
The RF input impedance of the mixer plays a vital role in determining the values of the matching network. Figure 3 shows the RF input impedance over a range of frequency. From this information, it can be determined that matching 500 at 45MHz requires matching to a 4.5k0 resistor in parallel with a 2.5pF capacitor. An equivalent model can be seen in Figure 4 with its component values given for selected frequencies. Since there are many questions from the designer on how to match the RF input, an example is given below.

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16

Application note
AN1994

1. llXER SECTION

E

B

2

3

4

5

Vee

2. IFSECTION

3. DEMODULATOR SECTION

4. OUTPUT SECTION
II

�

LO

c:=::J EXTERNAL COMPONENT
r:m:m NESOS.. INTERNAL COMPONENTS

Figure 2. NE605 Broken Down Into Four Areas

MARKER1:
~.1111rfli,.H
MARKER2:
f~Wl..F
MARKERS: Fa!IOOM!lz 588Q 11 2.75pF
MARKER4: Fa250MHz 1'185Q 11 Z.5pF

I

\

....1----i-

' )/,/,.. \ ,,...--iI-'..,. '

I I I 1

' ' , 1/ ' A......'....' ,~ I\\, ,.-.'...''_'~\,

I

....... ......:::::.""

Figure 3. Smith Chart of NE&OS's RF Input Impedance (Pin 1 or 2)

RF Section of Mixer The mixer has two RF input pins (Pin 1 and 2), allowing the user to choose between a

balanced or unbalanced RF matching network. Table 2 (see back of app note) shows the advantages and disadvantages for

either type of matching. Obviously, the better the matching network, the better the sensitivity of the receiver.

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AN1994

�MODEL

L

* I ~ _,.~~ i ,!L, t

z

� INDUCTOR Lt CAN BE NEGLECTED UNTIL THE FREQUENCY APPROACHES tGHz (NEGLECT 'C')
�TWO ELEMENT MODEL
Rflc

FREQ

RJLC

tOMHz

llknll2.15pF

60MHz 4651nll2.5pF

tOOMHz 31DOnll2.5pF

260MHz 1785kn 112.SpF

600Mllz 760Mllz

5880 112.75pF
17510 II 3.12pF

900Mllz 120'2113.2pF

1.IGHz ""2 113.4pF
---t-----1.58Gllz 210 1110.BnH

Figure 4. Equlvalent Model of RF Input Impedance

Example: Using a tapped-C network, match a
son source to the RF input of the NE605 at
45MHz. (refer to Figure 5)

I 0.1�F
RF INPUT MODEL @45Mllz
Fl ure 5. Tapped-C Network Step 1. Choose an inductor value and its "Q"
L = 0.22�H Op= 50 (specified by manufacturer) Step 2. Find the reactance of the inductor
Xp = 21tFL = 21t (45MHz) (0.22�H)
:. Xp=62.2'2 Step 3. Then.
Rp =OpXp =(50)(62.2)
�� Rp =3.11k.Q (the inductance resistance)

Step 4. Q = RrorALIXP
=(Rs' II RLll Rp) I Xp
where Rs'= RL = 4.5k II 4:5k // 3.11k/62.2 = 21.39 :. Q '" 21 (the Q of the matching
network)
where: Rs =source resistance; RL = load resistance; Rs' = what the source resistance should look like to match RL; Rp = inductance resistance
V Step 5. C1 /Rs' C2 = Rs -1=8.6

Step&. Cr=-1-=

1

Xp OJ (62.2) 2n 45MHz

=56.86pF

Step7. . C C1C2 usmg r= C1 + C2

where Cr = 56.86pF.

C1 C2

= 8.6

Cr=_~_+,�1_

1) :. C1 = Cr ( ~ +

andC:!

=~
8.6

thus ...

C1 =539pF

C2=64pF

L. = 0.22pH (value started with)

Step 8. Frequency check

1
OJ= /IC

2nF=-1f[C
F = 45MHz (... so far so good)

Step 9. Taking care of the 2.5pF capacitor

that is present at the RF input at

45MHz

C2A 64pF C1A = 540pF

Eq.1.

Cm c~::~A

Eq. 2.

where CTN = Cr - 2.SpF (recall value of Cr from Step 6.)
Making use of Equations 1 and 2, the new values of C1 and C2 are: C1A = 524pF C2A=60.6pF
[NOTE: At this frequency the 2.5pF capac~or could probably be ignored since its value at 45MHz has little effect on C1 and C2.)

Step 10. Checking the bandwidth
0=...f..._
BW
BW=Fu-FL BW =bandwidth Fu = upper 3dB frequency FL = lower 3dB frequency Using the above formulas results in Fu =46MHz FL=44MHz BW=2MHz The above shows the calculations for a singllH!nded match to the NE605. For a balanced matching network, a transformer
can be used. The same type of calculations
will still apply once the input impedance of the NE605 is converted to the primary side of the transformer (see Figure 6). But before we transform the input impedance to the primary side, we must first find the new input impedance of the NE6Q5 for a balanced
configuration. Because we have a balanced input, the 4.5k.Q transforms to 9k.Q (4.5k +
4.5k = 9k) while the capacitor changes from 2.5pF to 1.3pF (2.5pF in series with 2.5pF is 1.3pF). Notice that the resistor values double while the capacitor values are halved. Now the 9k'2 resistor in parallel with the 1.3pF capacitor must be transformed to the primary side of the transformer (see Figure 6).
RF INPUT MODEL@ 4 5 -
Flgure 8. Using a Tranaformar to Achieve a Balanced Match
Procedure:
Step 1. Zp = (Np)2
Zs Ns
where: Zp = impedance of primary side
Zs = impedance of secondary side
Np = number of turns on primary side Ns = number of turns on secondary side

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Step 2. Recall,
Zs=R II Xe
Zs= 9k 11 j2.7k where R=9k
1 Xe= '2nFC = 2.7k at F= 45MHz
Step 3. Assume 1:N turns ratio for the Iran stormer
Zp= ~ = 2.25k II j 680
(assuming N = 2)
Step 4. :. C = __1_ = S.2pF '2n FXc
R = 2.25k (these are the new values to match using the formulas in tapped-CJ
Step 5. Because the transformer has a magnetization inductance LM, (inductance presented by the transformer), we can eliminate the inductor used in the previous example and tune the tapped-C network with the inductance presented by the transformer. Lets assume LM = 0.22�H (0=50) Therefore C1=381pF C2 = 66.BpF Fu=46.7MHz FL=43.3MHz BW=3.4MHz taking the input capacitor into consideration C1=347pF C2 = 61pF L = 0.22�H (0=50)
Because of leakage inductance, the transformer is far from ideal. All of these leakages affect the secondary voltage under load which will seem like the indicated turns ratio is wrong. The above calculations show one method of impedance matching. The values calculated for C1 and C2 do not take into account board parasitic capacitance, and are, therefore, only theoretical values. There are many ways to configure and calculate matching networks. One alternative is a tapped-L configuration. But the ratio of the tapped-C network is easier to implement than ordering a special inductor. The calculations of these networks can be done on the Smith Chart. Furthermore, there are many computer programs available which will help match the circuit for the designer.
Local Oscillator Section of Mixer The NE605 provides an NPN transistor for the local oscillator where only external

components like capacitors, inductors, or resistors need to be added to achieve the LO frequency. The oscillator's transistor base and emitter (Pins 4 and 3 respectively) are available to be configured in Colpitts, Butler or varactor controlled LC forms. Referring to Figure 7, the collector is internally connected directly to Vee. while the emitter is connected through a 251<.Q resistor to ground. Base bias is also internally supplied through an 1SkQ resistor. A buffer/divider reduces the oscillator level by a factor of three before it is applied across the upper tree of the Gilbert Cell. The divider de-sensitizes the mixer to oscillator level variations with temperature and voltage. A typical value for the LO input impedance is approximately 1Okn.
The highest LO frequency that can be achieved is approximately 300MHz with a 200mVRMS signal on the base (Pin 4). Although it is possible to exceed the 300MHz LO frequency for the on-board oscillator, it is not really practical because the signal level drops too low for the Gilbert Cell. If an application requires a higher LO frequency, an external oscillator can be used with its 200mVRMS signal injected at Pin 4 through a DC blocking capacitor. Table 3 (see back of app note) can be used as a guideline to determine which configuration is best for the required LO frequency.
NE605 Vee
Figure 7. On-board NPN Transistor for Local Oscillator
Because the Colpitts configuration is for parallel resonance mode, it is important to know, when ordering crystals, that the load capacitance of the NE605 is 10pF. However, for the Bu~er configuration, the load capacitance is unimportant since the crystal will be in the series mode. Figure 8 shows the different types of LO configurations used with NE605.
If a person decides to use the Colpitts configuration in their design, they will probably find that most crystal manufacturers have their own set of standards of load

capacitance. And in most cases, they are unwilling to build a special test jig for an individual's needs. If this occurs, the designer should tell them to go ahead with the design. But, the designer should also be ready to accept the crystal's frequency to be off by 200-300Hz from the specified frequency. Then a test jig provided by the designer and a 2nd iteration will sclve the problem.
Output of Mixer Once the RF and LO inputs have been properly connected, the output of the mixer supplies the IF frequency. Knowing that the mixer's output has an impedance of 1.Skn, matching to an IF filter should be trivial.
Choosing the Appropriate IF Frequency Some of the standard IF frequencies used in industry are 455kHz, 10.7MHz and 21.4MHz. Selection of other IF frequencies is possible. However, this approach could be expensive because the filter manufacturer will probably have to build the odd IF filter from scratch.
There are several advantages and disadvantages in choosing a low or high IF frequency. Choosing a low IF frequency like 455kHz can provide good stability, high sensitivity and gain. Unfortunately, it can also present a problem with the image frequency (assuming single conversion). To improve the image rejection problem, a higher IF frequency can be used. However, sensitivity is decreased and the gain of the IF section must be reduced to prevent oscillations.
If the design requires a low IF frequency and good image rejection, it is best to use the double conversion method. This method allows the best of both worlds. Additionally, it is much easier to work with a lower IF frequency because the layout will not be as critical and will be more forgiving in production. The only drawback to this method is that it will require another mixer and LO. But, a transistor can be used for the first mixer stage (which is an inexpensive approach) and the NE605 can be used for the second mixer stage. The NE602A can also be used for the first conversion stage if the transistor approach does not meet the design requirements.
If the design requires a high IF frequency, good layout and RF techniques must be exercised. If the layout is sound and instability still occurs, refer to the "RSSI output" section which suggests solutions to these types of problems.

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Application note
AN1994

NE805

NE805

NE805

IJ XTALI ~

FUNDAMENTAL COLPITTS CRYSTAL
ff-r~F_____lj
HARTLEY L/C TANK � DC BLOCKING CAPACITORS

OVERTONE COLPITTS CRYSTAL

OVERTONE BUTLER CRYSTAL NE805

COLPITTS L/C TANK
Figure 8. Osclllator Configurations

In~-
Wth OVERTONE COLPITTS CRYSTAL

5 2 5 4 5 8 5 85 105 125 TEMPERATURE "C
CBE=5.5pF Figure 9. NE605 Appllcatlon Oscillator Level

88.3 98 92.3 87.7 74.4
"'72.7
63.7 52.8 37 19.3
0 0

28.8 27.3 85.9 114.8 143.2 171.8 229.1 288.4 400.9 LO LEVEL AT BASE VRMS

Figure 10. Mixer Efficiency vs Normalized LO Level

572.8

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15

"-'"'rq...,

T"

b,

'"' ~[""' [""'

a.5V a.OV

H -t- 5001NPUT t- H - 1SODnOUTPUT t- H - EXTERNAL LO 2211mV

6.0V
b..
~ 4.5V

r
I r--r""
~ 10
CJ
I

t -t -t - -

T"-j-....
T"'-b

r--o~

a.SY
a.av

8.0V

t--
I': 4.5V

-5 -55 -35 -15

5 25 45 55 TEMPERATURE �C

a5 105 125

Figure 11. 50'1 Conversion Gain

0 -55 -35 -15

25 45 85 as 105 125

TEMPERATURE "C

Figure 12. Single-Ended Matched Input Conversion Gain (50'1to1.5k'1, 14.SdB Matching Step-up Network)

Performance Graphs of Mixer

Fig.

Description

Oscillator Levels vs. Temperature

9

with Different Supply Voltages for the 44.545MHz Crystal Colpitts

Applications

LO Efficiency vs. Normalized Peak 10 Level at the Base of the Oscillator
Transistor

50'1 Conversion Gain vs. 11 Temperature with Different Supply
Voltages Using an External LO

Mixer Matched Input Conversion 12 Gain vs. Temperature with Different
Supply Voltages

IF Output Power vs. RF Input Level

13

(3rd-order Intercept Point) 1st mixer= diode mxr, 2nd mixer= 605

mxr

14

NE605 and Diode Mixer Test Set Up

15

NE605 LO Power Requirements vs. Diode Mixer

16

NE605 Conversion Gain vs. Diode Mixer

17

Comparing Intercept Points with Different Types of Mixers

Another issue to consider when determining an IF frequency is the modulation. For example, a narrowband FM signal (30kHz IF bandwidth) can be done with an IF of 455kHz. But for a wideband FM signal (200kHz IF bandwidth), a higher IF is required, such as 10.7MHz or 21.4MHz.

IF Section
The IF section consists of an IF amplifier and IF limiter. With the amplifier and limiter working together, 1OOdB of gain with a

25MHz bandwidth.can be achieved (see Figure 18). The linearity of the RSSI output is directly affected by the IF section and will be discussed in more detail later in this application note.
IFAmpllfler The IF amplifier is made up of two differential amplifiers with 40dB of gain and a small signal bandwidth of 41 MHz (when driven by a 50'1 source). The outpu1 is a low impedance emitter follower with an output resistance of about 230'1, and an internal series build out of 700'1 to give a total of 930'1. One can expect a 6dB loss in each amplifier's input since both of the differential amplifiers are single-ended.

0
1
:!!. ..z
~
i ~__._...._-'-#!- 2 -40 ,__,__,......,__+-+t-+-+-+-T--1 -80
!!:

-80 -80 -40 -

0

20

RF INPUT LEVEL (dBm)

Figure 13. Third-Order Intercept and Com ression

The basic function of the IF amp is to boost the IF signal and to help handle impulse noise. The IF amp will not provide good limiting over a wide range of input signals, which is why the IF limiter is needed.
IF Limiter The IF limiter is made up of three differential amplifiers with a gain of 63dB and a small

signal AC bandwidth of 28MHz. The outputs of the final differential stage are buffered to the internal quadrature detector. The IF limiter's output resistance is about 260'1 with no internal build-out. The limiter's output signal (Pin 9 onNE604A, Pin 11 on NE605) will vary from a good approximation of a square wave at lower IF frequencies like 455kHz, to a distorted sinusoid at higher IF frequencies, like 21.4MHz.
The basic function of the IF limiter is to apply a tremendous amount of gain to the IF frequency such that the top and bottom of the waveform are clipped. This helps in reducing AM and noise presented upon reception.
Function of IF Section The main function of the IF section is to clean up the IF frequency from noise and amplitude modulation (AM) that might occur upon reception of the RF signal. If the IF section has too much gain, then one could run into instability problems. This is where crucial layout and insertion loss can help (also addressed later in this paper).
Important Parameters for the IF Section Limiting: The audio output level of an FM receiver normally does not change with the RF level due to the limiting action. But as the RF signal level continues to decrease, the limiter will eventually run out of gain and the audio level will finally start to drop. The point where the IF section runs out of gain and the audio level decreases by 3dB with the RF input is referred to as the --3dB limiting point.
In the application test circuit, with a 5.1 k'1 interstage resistor, audio suppression is dominated by noise capture down to about the -120dBm RF level at which point the phase detector efficiency begins to drop (see Interstage Loss section below).

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AN1994

TI~ 0.1JIF
20 .33�

47pf _ _ __,~.,.. IF AT 45MHz
220pF

NEI05

4 LO HP8753A NETOWRK ANALVZER

RF 50'1 RF GENERATOR

LO HP8753A NETOWRKANALVZER

Figure 14. Test Circuits for NE605 Mixer vs Diode Mixer

+10

~o~Jr.I.~~~ -1t-H

.L
IL

t- -10 NBI05'a ~ER

b::-:1

100 200

500 1000 2000

~cy(MHz)

Figura 15. LO Power Requirements (Matched Input)

I +10 r-~

i "" +8

I J.

t!.

z t-- CONVERSION GAIN

� � ~o

l

I I - Dloi,E ..!ERI

I
r l

-10

l

~ ~
rs:

100MHz 200MHz 500Mllz

1GHz 2GHz

FREQUENCY

Figura 16. NE605 Convaralon Gain vs. Diode Mixer

The audio drop that occurs is a function of two types of limiting. The first type is as follows: As the input signal drops below a level which is sufficient to keep the phase

detector compressed, the efficiency of the detector drops, resulting in premature audio attenuation. We will call this �gain limiting�. The second type of limiting occurs when there is sufficient amount of gain without destabilizing regeneration (i.e. keeping the phase detector fully limited), the audio level will eventually become suppressed as the noise captures the receiver. We will call this "limiting due to noise capture�.
Figure 19 shows the 3dB drop in audio at about 0.26�VRMS. with a-118.7dBm/50n RF level for the NE605. Note that the level has not improwd by the 11dB gain supplied by the mixer/filter since noise capture is expected to slightly dominate here.

INPUT THIRD-ORDER INTERCEPT
DIO~

................T.D.A..S.3.3.0T...-
___________ ....

-20...__N~E&02""""~-~~~~~~~

100 FREQUENCY (MHz)

1300

Figure 17. Comparing Different Types of Mixers

AM rejection: The AM rejection provided by the NE6051604A is extremely good even for 80"k modulation indices as depicted in Figures 20a through 20d. This performance results from the 370mV peak signal levels set at the input of each IF amplifier and limiter stage. For this level of compression at the

inputs, even better performance OOUld be expected except that finite AM to PM conversion coefficients limit ultimate performance for high level inputs as indicated in Figure 20b.
Low level AM rejection performance degrades as each stage comes out of limiting. In particular as the quadrature phase detector input drops below 100mV peak, all limiting will be lost and AM modulation will be present at the input of the quad detector (See Figure 20d).
AM to PM conversion: Although AM rejection should continue to improve above -95dBm IF inputs, higher order effects, lumped under the term AM to PM conversion, limit the application rejection to about 40dB. In fact this value is proportional to the maximum frequency deviation. That is lower deviations producing lower audio outputs result directly in lower AM rejection. This is consistent wi.th the fact that the interfering audio signal produced by the AM/PM conversion process is independent of deviation within the IF bandwidth and depends to a first estimate on the level of AM modulation present As an example reducing the maximum frequency deviation to 4kHz from 8kHz, will result in 34dB AM rejection. If the AM modulation is reduced from 80% to 40%, the AM rejection for higher level IFs will go back to 40dB as expected. AM to PM conversion is also not a
function of the quad tank a, since an
a increase in increases both the audio and
spurious AM to PM convened signal equally.
As seen above, these relationships and the measured results on the application board

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(Figure 36) can be used to estimate high level IF AM rejection. For higher frequency IFs (s~ch as 21.4MHz), the limiter's output will start to deviate from a true square wave due to lack of bandwidth. This causes additional AM rejection degradation.
Interstage Loss: Figure 21 plots the simulated IF RSSI magnitude response for various interstage attenuation. The optimum interstage loss is 12dB. This has been chosen to allow the use of various types of filters, without upsetting the RSSl's linearity. In most cases, the filter insertion loss is less than 12dB from point A to point B. Therefore, some additional loss must be introduced externally. The easiest and simplest way is to use an external resistor in series with the internal build out resistor (Pin 14 in the NE604A, Pin 16 in the NE605). Unfortunately, this method mismatches the filter which might be important depending on the design. To achieve the 12dB insertion loss and good matching to the filter, an L-pad configuration can be used. Figure 22 shows the different set-ups.
Below is an example on how to calculate the resistors values for both Figures 22a and 22b.

Step 1.
j Xds = 20/og (960 + REX1) RFL T _FIL (dB) 960 + REXT+ RFLT
Oust solve for Rexr) where X = the insertions loss wanted in dB Rexr = the external resistor RFLT =the filter's input impedance FIL = insertion loss of filter in dB
2. For our application board X=12dB RFLT = 1.5k FIL=3dB Therefore, using the above eq. gives Rexr=5.1K

Step2.

RsHUNT=

( -XdB )

1-2x10 20

3. In this case, lets assume: FIL= -2dB therefore, Xda = +10, RFLT = 1.5k. The results are: Rexr = 1.41 k, RsHUNT = 4.08k

IF noise figure The IF noise figure of the receiver may be expected to provide at best a 7.7dB noise figure in a 1.5kn environment from about 25kHz to 100MHz. From a 25'2 source the noise figure can be expected to degrade to about 15.4db.

Performance Graphs of IF Section

Fig.

Description

IF Amp Gain vs. Temperature with 24 Various Supply Voltages

IF Limiter Gain vs. Temperature 25 with Various Supply Voltages

IF Amp 20MHz Response vs. 26 Temperature

IF Limiter 20MHz Response vs. 27 Temperature

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VOLTAGE/ CURRENT CONVERTER
+
IF SECTION � Av � 100[dB]
� BW =25[MHz)

IFAMP � Av:40[dB] � BW:41[MHz]
Demodulator Section
Once the signal leaves the IF limiter, it must be demodulated so that the baseband signal can be separated from the IF signal. This is accomplished by the quadrature detector. The detector is made up of a phase comparator (internal to theNE605) and a quadrature tank (external to theNE605).
The phase comparator is a multiplier cell, similar to that of a mixer stage. Instead of mixing two different frequencies, it compares the phases of two signals of the same frequency. Because the phase comparator needs two input signals to extract the information, the IF limiter has a balanced output. One of the outputs is directly connected to the input of the phase comparator. The other signal from the limiter's output (Pin 11) is phase shifted 90 degrees (through external components) and frequency selected by the quadrature tank. This signal is then connected to the other input of the phase comparator (Pin 10 of the NE605). The signal coming out of the quadrature detector (phase detector) is then low-passed filtered to get the baseband signal. A mathematical derivation of this can be seen in the NE604A data sheet.

IF ~..1~ &O[dB] � BW =28[Mllz]

Figure 18. IF Section of NE604A [NE605)

..1.0

�_.8

_.7

i::
II: .4
.3
.2 -65..,'15 -15 5

V1 LO

..

w V1

,

V,.1

4.SV 11.0V

,

25 45 65 85 105 125

c TEMPERATURE 0

Figura 19. NE605 Appllcatlon Board, -3d8 Umltlng (Drop In Audio)

The quadrature tank plays an important role in the quality of the baseband signal. It determines the distortion and the audio output amplitude. If the "O" is high for the quadrature tank, the audio level will be high, but the distortion will also be high. If the "O" is low, the distortion will be low, but the audio level will become low. One can conclude that there is a trade-off.
Output Section
The output section contains an RSSI, audio, and data (unmuted audio) outputs which can

be found on Pins 7, 8, and 9, respectively, on the NE605. However, amplitude shift keying (ASK), frequency shift keying (FSK), and a squelch control can be implemented from these pins. Information on ASK and FSK can be found in Philips Components-Signetics application note AN 1993.
Although the squelch control can be implemented by using the RSSI output, it is not a good practice. A better way of implementing squelch control is by comparing the bandpassed audio signal to high frequency colored FM noise signal from the unmuted audio. When no baseband signal is present, the noise coming out of the unmuted audio output will be stronger, due to the nature of FM noise. Therefore, the output of the external comparator will go high (connected to Pin 5 of the NE605) which will mute the audio output When a baseband signal is present, the bandpassed audio level will dominate and the audio output will now unmute the audio.
Audio and Unmutad Audio (Data) The audio and unmuted audio outputs (Pin 8 and 9, respectively, on the NE605) will be discussed in this section because they are

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Application note
AN1994

basically the same. The only difference between them is that the unmuted audio output is always "on" while the audio output can either be tumed "on� or "off". The unmuted audio output (data out) is for signaling tones in systems such as cellular radio. This allows the tones to be processed by the system but remain silent to the user. Since these tones contain information for cellular operation, the unmuted audio output can also be referred to as the "data" output. Applying 5V to Pin 5 on the NE605 mutes the audio on Pin 8 (connecting ground on Pin 5 unmutes it).
Both of these outputs are PNP current-to-voltage converters with a 551<.Q nominal internal load. The nominal frequency response of the audio and data outputs are 300kHz. However, this response can be increased with the addition of an external resistor (<581<.Q) from the output pins to ground. This will affect the time constant and lower the audio's output amplitude. This technique can be applied to SCA receivers and data transceivers (as mentioned in the NE604A data sheet).
RSSIOutput RSSI (Received Signal Strength Indicator) determines how well the received signal is being captured by providing a voltage level on its output. The higher the voltage, the stronger the signal.
The RSSI output is a current-to-voltage converter, similar to the audio outputs. However, a 91 kn external resistor is needed to get an output characteristic of 0.5V for every 20dB change in the input amplitude.
As mentioned earlier, the linearity of the RSSI curve depends on the 12dB insertion loss between the IF amplifier and IF limiter. The

reason the RSSI output is dependent on the IF section is because of the Vil converters. The amount of current in this section is monitored to produce the RSSI output signal. Thus, the IF amplifier's rectifier is internally calibrated under the assumption that the loss is 12dB.
Because unfiltered signals at the limiter inputs, spurious products, or regenerated signals will affect the RSSI curve, the RSSI is a good indicator in determining the stability of the board's layout. With no signal applied to the front end of the NE605, the RSSI voltage level should read 250mVRMS or less to be a good layout. If the voltage output is higher, then this could indicate oscillations or regeneration in the design.

Performance Graphs of Output Section

Fig.

Description

51 kn Thermistor in Series with

28

1001<.Q Resistor Across Quad Tank (Thermistor Quad Q

Compensation)

29a NE605 Application Board at-55�C

29b NE605 Application Board at -40�C

29c NE605 Application Board al +25�C

29d NE605 Application Board at +85�C

29e

NE605 Application Board al +125�C

NE604A for-OSdBm RSSI Output 30a vs. Temperature at Different Sup-
ply Voltages

NE604A for-18dBm RSSI Output 30b vs. Temperature at Different Sup-
ply Voltages
NE605 for-120dBm RSSI Output 30c vs. Temperature at Different Sup-
ply Voltages

NE605 for-76dBm RSSI Output 30d vs. Temperature at Different
Supply Voltages

NE605 for -28dBm RSSI Output
30e vs. Temperature at different Supply Voltages

31

NE605 Audio level vs. Temperature and Supply Voltage

32

NE605 Data Output at -76dBm vs. Temperature

Referring to the NE/SA604A data sheet, there are three primary ways to deal with regeneration: (1) Minimize the feedback by gain stage isolation, (2) lower the stage input impedances, thus increasing the feedback attenuation factor, and (3) reduce the gain. Gain reduction can be accomplished by adding attenuation between stages. More details on regeneration and stability considerations can be found in the NE/SA604A data sheet.
Ill. QUESTIONS & ANSWERS: Q.-Bypaas. How important is the effect of
the power supply bypass on the receiver performance?
A. While careful layout is extremely critical, one of the single most neglected components is the power supply bypass in applications of NE604A or NE605. Although increasing the value of the tantalum capacitor can solve the problem, more careful testing shows that it is actually the capacitor's ESR (Equivalent Series Resistance) that needs to be checked. The simplest way of screening the bypass capacitor is to test the capacitor's dissipation factor at a low frequency (a very easy test, because most of the low frequency capacitance meters display both C, and Dissipation factor).

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Application note
AN1994

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.01mV .1mv 1mV 10mv 100mv
IF INPUT LEVEL (VRMS), RL =81k
Figure 21. NE804A's RSSI Curve at Different Interstage Losses
Q.-On�chlp osclllstor. We cannot get the NE605 on-chip oscillator to work. What is the problem?
A. The on board oscillator is just one transistor with a collector that is connected to the supply, an emitter that goes to ground through a 25k resistor, and a base that goes to the supply through an 18k resistor. The rest of the circuit is a buffer that follows the

oscillator from the transistor base (this buffer does not affect the performance of the oscillator).
Fundamental mode Colpitts crys1&I oscillators are good up to 30MHz and can be made by a crystal and two external capacitors. At higher frequencies, up to about 90MHz, overtone crystal oscillators (Colpitts) can be made like the one in the cellular application circuit. At higher frequencies, up to about 170MHz, Butler type oscillators (the crystal is in series mode) have been successfully demonstrated. Because ol the BGHz peak fT of the transistors, LC Colpitts oscillators have been shown to work up to 900MHz. The problem encountered above 400MHz is that the onchip oscillator level is not sufficient for optimum conversion gain of the mixer. As a result, an external oscillator should be used at those frequencies.
Generally, about 220mVRMS is the oscillator level needed on Pin 4 for maximum conversion gain of the mixer. An external

oscillator driving Pin 4 can be used
throughout the band. Finally, since the NE605's oscillator is similar to the NE602, all of the available application notes on NE602 apply to this case (assuming the pin out differences are taken into account by the user).
Below are a couple of points to help in the oscillator design. The oscillator transistor is biased around 250�A which makes it very hard to probe the base and emitter without disturbing the oscillator (a high impedance, low capacitance active FET probe is desirable). To solve these problems, an external 22k resistor (as low as 10k) can be used from Pin 3 to ground to double the bias current of the oscillator transistor. This external resistor is put there to ensure the start up of the crystal in the BOMHz range, and to increase the fr of the transistor for above 300--400MHz operation. Additionally, this resistor is required for operations above 80--90MHz. When a 1k resistor from Pin 1 to

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Application note
AN1994

ground is connected on the N E605, half of the mixer will shut off. This causes the mixer to act like an amplifier. As a result, Pin 20 (the mixer, now amplifier output) can be probed to measure the oscillator frequency. Furthermore, the signal at Pin 20 relates to the true oscillator level . This second resistor is just for optimizing the oscillator of course. Without the 1k resistor, the signal at Pin 20 will be a LO feedthrough which is very small and frequency dependent.
Finally in some very early data sheets, the base and emitter pins of the oscillator were inadvertently interchanged. The base pin is Pin 4, and the emitter pin is Pin 3. Make sure that your circuit is connected correctly.
Q.-Sensltlvlty at higher Input frequencies. We cannot get good sensitivity like the 45MHz case at input frequencies above 70MHz. Do you have any information on sensitivity vs. input frequency?
A. The noise figure and the gain of the mixer degrade by less than 0.5dB, going from 50 to 100MHz. Therefore, this does not explain the poor degradation in sensitivity. If other problems such as layout, supply bypass etc. are already accounted for, the source of the problem can be regeneration due to the 70MHz oscillator. What is probably happening is that the oscillator signal is feeding through the IF, getting mixed with the 455kHz signal, causing spurious regeneration. The solution is to reduce the overall gain to stop the regeneration.
This gain reduction can be done in a number of places. Two simple points are the attenuator network before the second filter and the LO level (see Figure 22). The second case will reduce the mixer's noise figure which is not desirable. Therefore, increasing the Interstage loss, despite

minimal effect on the RSSI linearity, is the correct solution. As the Interstage loss is increased, the regeneration problem is decreased, which improves sensitivity, despite lowering of the over-all gain (the lowest RSSI level will keep decreasing as the regeneration problem is decreased). For an 81 MHz circuit it was found that increasing the Interstage loss from 12dB to about 17dB produced the best results (-119dBm sensitivity). Of course, adding any more Interstage loss will start degrading sensitivity.
Conversely, dealing with the oscillator design, low LO levels could greatly reduce the mixer conversion gain and cause degradation of the sensitivity. For the 81 MHz example, a 22k parallel resistor from Pin 3 to ground is required for oscillator operation where a Colpitts oscillator like the one in the cellular application circuit is used. The LO level at Pin 4 should be around 220mVRMS for good
operation. Lowering the LO level to
approximately 1SOmVRMS may be a good way of achieving stability if increasing Interstage attenuation is not acceptable. In that case the 22k resistor can be made a thermistor to adjust the LO level vs. temperature for maintaining sensitivity and ensuring crystal start-up vs. temperature. At higher IF frequencies (above 30MHz), the interstage gain reduction is not needed. The bandwidth of the IF section will lower the overall gain. So, the possibility of regeneration decreases.
Q.-Mlxer noise figure. How do you measure the mixer noise figure in NE605, and NE602?
A. We use the test circuit shown in the NE602 data sheet. The noise figure tester is the HP8970A. The noise source we use is

the HP346B (ENR = 15.46dB). Note that the
output is tuned for 10.?MHz. From th attest circuit the NF-meter measures a gain of approximately 1SdB and 5.5dB noise figure.
More noise figure data is available in the paper titled 'Gilbert-type Mixers vs. Diode Mixers" presented at RF Expo '89 in Santa Clara, California. (Reprints available through Signetics Publication Services.)
Q.- What is the value of the series resistor before the IF filter in the NE605 or NE604A applications?
A. A value of 5. 1kQ has been used by us in our demo board. This results in a maximally straight RSSI curve. A lower value of about 1k will match the filter better. A better solution is to use an L pad as discussed earlier in this application note.
Q.- What is the low frequency input resistance of the NE605?
A. The data sheets indicated a worst case absolute minimum of 1.5k. The typical value is 4.7k.
Q.- What are BE-BC capacitors in the NE605 oscillator transistor?
A. The oscillator is a transistor with the collector connected to the supply and the
emitter connected to the ground through a 25k resistor. The base goes to the supply
through an 18k resistor. The junction capacitors are roughly about 24fF (fempto Farads) for CJE (Base-emitter capacitors), and 44fF for CJC (Collector-base capacitors). There is a 72fF capacitor for CJS (Collectorsubstrate capacitor). This is all on the chip itself. It should be apparent that the parasitic packaging capacitors (1.5-2.5pF) are the dominant values in the oscillator design.

22a. SERIES RESISTOR CONAGURATION

IFAMP

960 BUILDOUT RESISTOR

If LIMITER

22b. L-PAD CONRGURATION

Figure 22. Implementing the 12dB Insertion Loss

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AN1994

Summary of Differences for NE/SA604/604A

NE/SA604

RSSI

No temperature compensation

IF Bandwidth

15MHz

IF Limiter Output

No buffer

Current Drain

2.7mA

NE/SA604A Internally temperature compensated
25MHz Emitter follower buffer output with Bk in the emitter
3.7mA

Q.- What are the differences between the NE604 and NE604A? (see Table below)
A. The NE/SA604A is an improved version of the NE/SA604. Customers, who have been using the NE604 in thii past, should have no trouble doing the conversion.
The main differences are that the small signal IF bandwidth is 25MHz instead of 15MHz, and the RSSI is internally temperature compensated. If external temperature compensation was used for the NE604, the designer can now cut cost with the NE604A, The designer can either get rid of these extra parts completely or replace the thermistor (if used in original temperature compensated design) with a fixed resistor.
Those using the NE604 at 455kHz should not see any change in performance. For 10.7MHz, a couple of dB improvement in performance will be observed. However, there may be a few cases where instability will occur after using NE604A. This will be the case if the PC-board design was marginal for the NE604 in the first place. This problem, however, can be cured by using a larger than 1O�F tantalum bypass capacitor on the supply line, and screening the capacitors for their ESR (equivalent series resistance) as mentioned earlier. The ESR at 455kHz should be less than 0.2n. Since ESR is a frequency dependent value, the designer can correlate good performance with a low frequency dissipation factor, or ESR measurement, and screen the tantalum capacitors in production. There are some minor differences as well. The NE/SA604A uses about 1mA more current than the NE/SA604. An emitter follower has been added at the limiter output to present a lower and more stable output impedance at Pin 9. The DC voltage at the audio and data outputs is approximately 3V instead of 2V in the NE604, but that should not cause any problems. The recovered audio level, on the other hand, is slightly higher in the NE604A which should actually be desirable. Because of these changes, it is now possible to design 21.4MHz IFs using the NE604A, which was not possible with the NE604.
The two chips are identical, otherwise. The customers are encouraged to switch to the NE604A because it is a more advanced

bipolar process than the previous generation used in theNE604. As a result we get much tighter specifications on the NE604A.
Q.- How does the NE605 mixer compare with a typical double balanced diode mixer?
A. Some data on the comparison of the conversion gain and LO power requirements are shown in this application note. These two parameters reveal the advantages in using the NE605 mixer.
The only drawback of the NE605 may seem to be its lower third-order intercept point in comparison to a diode mixer. But, this is inherent in the NE605 as a result of the low power consumption. If one compares the conversion gain of the NE605 with the conversion loss of a low cost diode mixer, it turns out that the third-order intercept point, referred to the output, is the same or better in the NE605. Another point to take into account is that a diode mixer cannot be used in the front end of a receiver without a preamp due to its poor noise figure. A third-order intercept analysis shows that the intercept point of the combination of the diode mixer and preamp will be degraded at least by the gain of the preamp. A preamp may not be needed with NE605 because of its superior noise figure.
For more detailed discussion of this topic please refer to the paper titled "Gilbert-type Mixers vs. Diode Mixers").
Q.- How can we use the NE605 for SCA FM reception?
A. The 10.7MHz application circuit described in AN 1993 can be used in this case. The LO frequency should be changed and the RF front-end should be tuned to the FM broadcast range. The normal FM signal, coming out of Pin 8 of the NE605, could be expected to have about 1.S�V (into 500) sensitivity for 20dB SIN. This signal should be band-pass filtered and amplified to recover the SCA sub-carrier. The output of that should then go to a PLL SCA decoder, shown on the data sheet of Signetics NE565 phase lock loop, to demodulate the base-band audio. The two outputs of the NE605 Pins 8 and 9 can be used to receive SCA data as well as voice, or features such as simultaneous reception of both nonmal FM,

and SCA. The RSSI output, with its 90dB dynamic range, is useful for monitoring signal levels.
Q.- What is the power consumption of the NE605 or NE604A vs. temperature and Vee?
A. The NE605 consumes about 5.6mA of current at SV. This level is slightly temperature and voltage dependent as shown in Figure 33. Similar data for the NE604A is shown in Figure 34.
Q.- How can you minimize RF and LO feedthroughs
A. The RF and LO feedthroughs are due to offset voltages at the input of the mixer's differential amplifiers and the imbalance of the parasitic capacitors. A circuit, such as the one shown in Figure 35, can be used to adjust the balance of the differential amplifiers. The circuit connected to Pins 1 and 2 will minimize RF feedthrough while the circuit shown connected to Pin 6 will adjust the LO feedthrough. The only limitation is that ii the RF and LO frequencies are in the 100MHz range or higher, these circuits will probably be effective for a narrow frequency range.
Q.- Distortion vs. RF Input level. We get a good undistorted demodulated signal at low RF levels, but severe distortion at high RF levels. What is happening?
A. This problem usually occurs at 10. 7MHz or at higher IF's. The IF filters have not been properly matched on both sides causing a sloping IF response. The resulting distortion can be minimized by adjusting the quad tank at the FM threshold where the IF is out of limiting. As the RF input increases, the IF stages will limit and make the IF response flat again. At this point, the effect of the bad setting of the quad tank will show itself as distortion. The solution is to always tune the quad tank for distortion at a medium RF level, to make sure that the IF is fully limited. Then, to avoid excessive distortion for low RF levels, one should make sure that the IF filters are properly matched.
Q.-The most commonly asked questions: ''Why doesn't the receiver sensitivity meet the specifications?"; "Why is the RSSI dynamic range much less than expected?"; "Why

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Application note
AN1994

does the RSSI curve dip at 0.9V and stay flat at 1Vas the RF input decreases?"; "Why does the audio output suddenly burst into oscillation, or output wideband noise as the RF input goes down, instead of dying down slowly?"; "When looking at the IF output with a spectrum analyzer, why do high amplitude spurs become visible near the edge of the IF band as the RF level drops?"
A. These are the most widely observed problems with the NE605. They are all symptoms of the same problem; instability. The instability is due to bad layout and grounding.
Regenerative instability occurs when the limiter's output signals are radiated and picked up by the high impedance inputs of the mixer and IF amp. This signal is amplified by both the IF amp and limiter. Positive feedback causes the signal to grow until the signal at the limiter's output becomes limited. Due to the nature of FM, this instability will dominate any low RF input levels and capture the receiver {see Figure 23).
Since the receiver behaves normally for high RF inputs, it misleads the designer into believing that the design is okay. Additionally the RSSI circuit cannot determine whether the signal being received is coming from the antenna or the result of regenerative instability. Therefore, RSSI will be a good instability indicator in this instance because the RSSI will stay at a high level when the received signal decreases. Looking at the IF spectrum {Pin 11 for 605, Pin 9 for 604A) with the RF carrier present {no modulation). the user will see a shape as shown below. When regenerative instability occurs, the receiver does not seem to have the ultimate sensitivity of which it is capable.

CARRIER

FREQUENNCY A. CARRIER AND IN BAND NOISE FOR
llGH RF LEVELS

A

_ / \ . _ \ CARRIY \ SPURIOUS

,,-

I

I

FREQUENNCY
SPu.\l<ffs~'Q~t1t tK~fu~!Nl:~ER~~~VER
Figure 23.

Make sure that a double sided layout with a good ground plane on both sides is used. This will have RF/IF loops on both sides of the board. Follow our layouts as faithfully as you can. The supply bypass should have a low ESR 10-15�F tantalum capacitor as discussed earlier. The crystal package, the inductors, and the quad tank shields should be grounded. The RSSI output should be used as a progress monitor even if is not needed as an output. The lowest RSSI level should decrease as the circuit is made more stable. The overall gain should be reduced by lowering the input impedance of the IF amplifier and IF limiter, and adding attenuation after the IF amplifier, and before the 2nd filter. A circuit that shows an RSSI of 250mV or less with no RF input should be considered close to the limit of the performance of the device. If the RSSI still remains above 250mV, the recommendations mentioned above should be revisited.
Q.- Without the de-emphasis network at the audio output, the -3dB bandwidth of the

audio output is limited to only 4.SkHz. The maximum frequency deviation is 8kHz, and the IF bandwidth is 25kHz. What is the problem?
A. What is limiting the audio bandwidth in this case is not the output circuit, but the IF filters. Remember that Carson's rule for FM IF bandwidth requires the IF bandwidth to be at least:
2{Max frequency Dev. +Audio frequency)
With a 25kHz IF bandwidth and 8kHz frequency deviation, the maximum frequency that can pass without distortion is approximately 4.5kHz. 2(8kHz + 4.5kHz) is 25kHz as expected.
REFERENCES:
"High-Performance Low-Power FM IF System" {NE604A data sheet). Signetics Linear Data Manual, Signetics, 1988.
"AN199-Designing with the NE/SA604", Signetics Linear Data Manual, 1987.
"AN1981-New Low Power Single Sideband Circuits", Signetics Linear Data Manual, 1988.
"Applying the Oscillator of the NE602 in Low Power Mixer Applications", Signetics Linear Data Manual, 1988.
"AN 1993--High Sensitivity Applications of Low-Power RF/IF Integrated Circuits", Signetics Linear Data Manual, 1988.
"RF Circuit Design", Bowick. C., Indiana: Howard W. Sams & Company, 1982.
"The ARAL Handbook for the Radio Amateur", American Radio Relay League, 1986.
"Communications Receivers: Principles & Design", Rohde, U., Bucher, T.T.N., McGraw Hill, 1988.
"Gilbert-type Mixers vs. Diode Mixers", proceedings of R.F. Expo 1989, Fotowat, A., Murthi, E., pp. 409-413.

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Application note
AN1994

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December 1991

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Figure 29. Performance of the NE605 Application Board at Different Temperatures

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1.7 1-+-+--+--+--+--+--+-t-t-'f-+-+-+--+--+--+--+--t

1.5 .................................................._.____.................................

-55 -35 -15

25 45 65 85 105 125

TEMPERATURE "C

sonsoURCE

30a. NE604A for -68dBm, RSSI OUtput

5i:::;;. ;i;;;!i 2~~~m:EE5a 8.SV
f-t-+-+--+--+--+--+-t-t--ir-t-+-+--+--+--+--+---t 8.ov

~71-t-+--+--+--+--+--+-t-t-f-t-+-+--+--+--+--+-t

3.2 ._.._............................................_._.._.._.._..............................._,

-

-35 -15

25 45 85 85 105 125 TEMPERATURE "C

50.nSOURCE

30b. NE604A for-18dBm, RSSI Output

0.5,

..:&.

--;..._ v """I'--.. 1 !(:jij' o.41---il---!--"'.._.r---...~-+--+--+-+-+-+--19.ov
~

I : :m

o.1

-r- ~:mt,,...~F;;;::--t--t--t--tv"'Zl,,_ir----t

~455kJ: ._

L

:

:

:

:

2.8

9

2:. 2.3

I

I- 91knLOAD
t - IF= 455kHz

B.SV 8.0V
6.0V
4.5V

J_

~ 1.8

-

~ 4

~ 45 e e ~ m
TEMPERATURE �C
son SOURCE

30c. NE805 RSSI at -120dBm

1. 3

-

-35 -15

25 45 85 85 105 125
TEMPERATURE �C

50nSOURCE

5.51DmlmD130d. NE&OSRSSI,-78dBm

s.o

a.5V

a.ov

~ illljllilili ~ 4.5

6.0V

i=t: ~

l=I= !; 4.0
o

91kn LOAD IF= 455kHz

4.5V

~ 3.5

3.0

-55 -35 -15 5

25 45 65 85 105 125

TEMPERATURE "C

50.n SOURCE

30e. NE605 RSSI at -28dBm

Figure 30. RSSI Response for Different Inputs

December 1991

332

Signetics RF Communications
Reviewing key areas when designing with the NE605

Application note
AN1994

I1 1- I �40

8.0V
~ ~ 1 1 8 . 5 V
~

0 160

;s

:::> c 120

~

RF INPUT= -76dBm -+-+-i

100kn LOAD

+-+--1

eot:�::�:::�::l::�::�:::�::l::�::�:i:jt:t:�::l:::l:::�::j

-55 -35 -15 5

25 45 65 85 105 125

TEMPERATURE "C

Figure 31. Audio Level vs Temperature and Supply Voltage

775

675
!
~ 575
:::> 0 475
'=1=l
375

Lio::

~

u..:i

~

L.:; :;a

pr

u.::
L::
F"': /l

8.5V 8.0V k:::
6.0V
"""' 4.5V

�= RF INPUT= -76dBm

100knLOAD

-

275

-55 -35 -15 5

25 45 65 85 105 125

TEMPERATURE"<:

Figure 32. Data Level vs Temperature and Supply Voltage

9.0V

J..--r
A"" .....n~

8.SV 8.0V

...... 1--1 .....+""'""

1 ~

A--1

_8

H

v
I -I -

6.0V 4.5V

IL'1

......+-

Yi

V1

P'"

-55 -35 -25

25 45 65 TEMPERATURE "C

85 105 125

Figure 33. NE605 Ice vs Temperature

100k

3.7 ~-+-++-+-+-!-+-+-+-+-+-+-!-+-+~

v'7 ~

3.6 H-t++~ :J,,,..HH--t-='F::P;..l.'ct-----t-t+-t-l

3�5

N 8.5V

g 33..314-+f-.'4HV-H'IH-:+...++H--H11-H--c-::+:i+---t-HF~H+H_-l-+Hf--ti<-.+.t---+--I+'H~-~-+t--=tI 6.0V

3.2 ~

3.J1

TESTER

3�0-s'=5,,._...,-3"'5..._._.,.,15,.._..,_._25,,...._..,4~5...._+.&5,.....__,as,,,....._1...,0'="5.._.125 TEMPERATURE �C

Figure 34. NE604A Ice vs Temperature

Figure 35. Minimizing RF and LO Feedthrough

December 1991

333

Signetics RF Communications
Reviewing key areas when designing with the NE605

Application note
AN1994

C15

C1
J~
INPUT

IFT1

MUTE

Vee

RSSI AUDIO UNMUTED

OUTPUT

AUDIO

December 1991

Application Component List

C1 100pF NPO Ceramic C2 390pF NPO Ceramic CS 100nF �10% Monolithic Ceramic C6 22pF NPO Ceramic C7 1nF Ceramic CS 10.0pF NPO Ceramic C9 100nF �10% Monolithic Ceramic c10 15�F Tantalum (minimum)
C11 100nF �10% Monolithic Ceramic C12 15nF �10% Ceramic C13 150pF �2% N1500 Ceramic C14 100nF �10% Monolithic Ceramic C15 10pF NPO Ceramic C17 100nF �10% Monolithic Ceramic C18 100nF �10% Monolithic Ceramic

C21 C23 C25 Fii 1 Flt2 IFT 1
L1 L2
X1
R9 R17
RS R10 R11

100nF �10% Monolithic Ceramic 100nF �10% Monolithic Ceramic 100nF �10% Monolithic Ceramic Ceramic Fiiter Murata SFG455A3 or equiv Ceramic Fiiter Murata SFG455A3 or equiv 455kHz (Ce= 180pF) Toko RMC-2A6597H 147-160nH Collcraft UNl-10/142--04J08S 3.3�H nominal
Toko 292CNS-T1046Z 44.545MHz Crystal ICM4712701 100k�1% 1/4W Metal Film 5.1k�5%1/4W Carbon Composition Not Used In Application Board (see Note 8) 100k �1% 1/4W Metal Film (optional) 100k�1% 1/4W Metal Film (optional)

Figure 36. NE/SA605 45MHz Application Circuit 334

Signetics RF Communications
Reviewing key areas when designing with the NE605

Application note
AN1994

Table 1. Related Appllcatlon Notes

App. Note

Date

Tille

Main Topics

AN198 Feb. 1987 Designing with the NE/SA602

-Advantages/Disadvantages to single-ended or balanced matching

AN1981

Dec. 1988 New Low Power Single Sideband Circuits - General discussion on SSB circuits -Audio processing - Phasing-filter technique

AN1982 Dec. 1988 Applying the Oscillator of the NE602 in Low - Oscillator configurations Mixer Applications

AN199 Feb. 1987 Designing with the NE/SA604

Circuits of: -AM synchronous det. - Temp. compensated RSSI circuit - Field strength meter - Product detector

AN1991

Dec. 1988 Audio Decibel Level Detector with Meter - Uses of the 604 in application Driver

AN1993 Dec. 1988 High Sensitivity Application Low-Power -An overview of the NE602 and NE604 in typical applications

RF/IF Integrated Circuits

- Good information before getting started

Table 2. Comparing Balanced vs Unbalanced Matching

NE605 or NE602

Matching

Advantages

Disadvantages

Pins 1 and 2 (RF input)

Single-ended (unbalanced)

- Very simple circuit - No sacrifice in 3rd-order performance

- Increase in 2nd-order products

Balanced

- Reduce 2nd-order products

- Impedance match difficult to achieve

Table 3. LO Configurations
LO(MHz) Suggested Configuration Using On-board Osclllator

0-30

Fundamental mode, use Colpitts

30-70 3rd overtone mode, use Colpitts

70-90

3-Sth overtone mode, use Colpitts with 22kQ resistor connected from the emitter pin to ground

90 -170

Use Butler, crystal in series mode, and a 22kQ resistor connected from the emitter pin to ground

170-300 LC configuration

December 1991

335

Signetlcs RF Communications
Evaluating the NE605 SO and SSOP demo-board

Appllcatlon note
AN1995

Author: Alvin K. Wong
INTRODUCTION: With the increasing demand for smaller and lighter equipment, designers are forced to reduce the physical size of their systems. There are several approaches to solving the size problem. A designer needs to look for sophisticated integrated single chip solutions, chips that are smaller in size, and chips that require minimum external components.
Signetics offers all of these solutions in their NE605. The NE605 single-chip receiver converts the RF signal to audio and is available in three packages: DI P,SO, and SSOP. This offers total flexibility for layout considerations. The SSOP package is the smallest 20 pin package available in the market today, and allows the designer the flexibility to reduce the overall size of a layout.
When working with a smaller and tighter layout in a receiver design, it becomes important to follow good RF techniques. This application note shows the techniques used in the SO and SSOP demo-board. It does not cover the basic functionality of the NE605

but instead focuses more on the layout constraints. This application note also has a trouble-shooting chart to aid the designer in evaluating the SO and SSOP demo-board. For a complete explanation of the NE605, please refer to application note AN 1994 which describes the basic block diagrams, reviews the common problems encountered with the NE605, and suggests solutions to them. Reading AN 1994 is highly recommended before attempting the SO and SSOPlayout.
The recommended layout demonstrates how well the chip can perform. But it should be pointed out that the combination of external parts with their tolerances plays a role in achieving maximum sensitivity.
The minimum and maximum 12dB SINAD measurement for both boards is -11 SdBm and-119.7dBm, respectively. A typical reading taken in the lab for both SO and SSOP demo-boarps is -119dBm.
There were two different design approaches for both layouts. For the SO layout, there are

inductive tuning elements (except for the LO section); for the SSOP layout there are capacitive tuning elements. This approach was taken to show the designer that both ways can be used to achieve the same 12dB SINAD measurement. However, it is worth mentioning that capacitive tuning elements are less expensive than the inductive tuning elements.
Packages Avallable
As mentioned above, there are three packages available for the NE605. See the "Package Outline" section of the Signetics 1992 RF Handbook for the physical dimensions of all three packages. Notice that the DIP package is the largest of the three in physical size; the SSOP is the smallest. The recommended layout and performance graphs for the DIP package are shown in the NE605 data sheet and AN1994. But the SO and SSOP recommended layout and performance graphs are shown in this application note.

SMA RF IN

L1 330nH

I +C10 22�F

U1

c1n1F-=

.1'.:~I r

RFIN BYPASS

i-.---f----_;;:__---~OSCOUT

~--4-------~ OSC IN

.__-------"-!MUTE IN

._------~vcc

NF-605D

~1C9�F

RSSIOUT ~---"-!AUDIO OUT
DATA OUT QUAD IN

IFT1 330� H Va!.

November 13, 1991

Figure 1. NE605 Schematic for the SO Layout 336

Signetics RF Communications
Evaluating the NE605 SO and SSOP demo-board

Application note
AN1995

RF

Slgnetlcs

IN

NE806D

v
;fr

C2[]JC1

n C5

L1

#30001

LJ=i:fjn CJC21

DR9

R17

.R..

11

1

+ A

010

mR10 C=1 FLT2 C18

D
+

c~
IFT1

I

NE6050 DN7/91
(�Xi) 0 (!;

1.71n.

l 0 �:�) (!;

(!;

0(!; ~
~ ~ ~
~

TOP SILK SCREEN

TOP VIEW
Figure 2. NE605 SO Demo-board Layout (Not Actual Size)

1.751n.-----""' BOTTOM VIEW

AUDIO

-125
4.75 4.50 4.25 4.00 3.75 3.50 3.25 3.00
a"'2.75 2.50
> 2.25
2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0.00
-125

-115 -105 -95

-65 -75 -65 RF LEVEL (dBm) RSSl(V)

17 7
~
2
~
::2l
.L.

~
I/

-55 -45 -35 -25
~
P'
~
];'

-115 -105 -95 435 -75 -65 -55 -45 -35 -25 RF LEVEL (dBm)
Figure 3. NE605 SO Performance Curves

SO LAYOUT:
Figure 1 shows the schematic for the SO layout. Listed below are the basic functions of each external component for Figure 1.
C1 - Part of the tapped-C network to match the front-end
C2 - Part of the tapped-C network to match the front-end
CS - Used as an AC short to Pin 2

C6 -
C7 CB C9 C 10 C11 -

Used to tune the LO for the Colpitts oscillator Used as part of the Colpitts oscillator Used as part of the Colpitts oscillator Supply bypassing Supply bypassing Used as filter

C12- Used as filter
C13- Used as filter C14- Used to AC ground the Quad tank C15- Used to provide the 90� phase shift to
the phase detector
C17- IF limiter decoupling cap
C18- IF limiter decoupling cap C21- IF amp decoupling cap
C23- IF amp decoupling cap C26- Quad tank component L1 - Part of tapped-C network to match
the front-end TOKO 5CB-1320Z L2- Part of the Colpitts oscillator Coilcraft
1008CS-122 R9- Used to convert the current into the
RSSI voltage R10- Converts the audio current to a
voltage
R11- Converts the data current to a voltage R17- Used to achieve the -12dB insertion
loss IFT1 - Inductor for the Quad tank TOKO
303LN-1130
Fl LT1 - Murata SFG455A3 455kHz bandpass filter
FILT2 -Murata SFG455A3 455kHz bandpass filter
X1 - Standard 44.545MHz crystal in QC38 package
The recommended SO layout can be found in Figure 2 and should be used as an example to help designers gel started with their projects.
The SO NE605 board performance graphs can be found in Figure 3.

November 13, 1991

337

Signetics RF Communications
Evaluating the NE605 SO and SSOP demo-board

Application note
AN1995

SMA RF IN

U1
RFIN BYPASS 1 - e - - - + - - - - - - - - = - i DSC OUT IN ~-+-----------'-IOSC e - - - - - - - - = - i MUTE IN

NE605DK

-= X1 44.545MHz

*'1 �FC9
R9 100k

C25 BBpF

C26 470pF

�1C1�4F
1s&;~ ":'
Figure 4. NE605 Schematic for the SSOP Layout

SSOP LAYOUT: Figure 4 shows the schematic for the SSOP layout. C1- Part of the tapped-C network to
match the front-end C2- Part of the tapped-C network to
match the front-end
C3- Part of the tapped-C network to match the front-end
CS - Used as an AC short to Pin 2
C6 - Used to tune the LO for the Colpitts oscillator
C7 - Used as part of the Colpitts oscillator CS - Used as part of the Colpitts oscillator C9 - Supply bypassing
C10 - Supply bypassing
C11 - Used as filter C12- Used as filter C13 - Used as filter C14 - Used to AC ground the Quad tank

C15- Used to provide the 90� phase shift to the phase detector
C17- IF limiter decoupling cap
C18- IF limiter decoupling cap
C21- IF amp decoupling cap
C23- IF amp decoupling cap
C24- Part of the Quad tank
C25- Part of the Quad tank C26- Part of the Quad tank L1 - Part of tapped-C network to match
the front-end Coilcraft 1008CS-331
L2- Part of the Colpitts oscillator Coilcraft 1008CS-122
R9- Used to convert the current into the RSSI voltage
R10- Converts the audio current to a voltage
R11 - Converts the data current to a voltage R17- Used to achieve the -12dB insertion
loss

IFT1- Inductor for the Quad tank Mouser ME435-2200
FILT1 -Murata SFGCC455BX 455kHz bandpass filter
FILT2 -Murata SFGCC455BX 455kHz bandpass filter
X1- Standard 44.545MHz crystal
The SSOP layout can be found in Figure 5. The SSOP NE605 board performance graphs can be found in Figure 6.
The main difference between the SO and SSOP demo-boards is that the SSOP demo-board incorporates the low profile 455kHz Murata ceramic filter. It has an input and output impedance of 1.0k.Cl. This presents a mismatch to our chips, but we have found that the overall performance is similar to that when we use the "blue� Murata filters that have the proper 1.5k'1 input and output impedance.

November 13, 1991

338

Signetics RF Communications
Evaluating the NE605 SO and SSOP demo-board

000000

000000

0

0

: 0

10�1~ ~C7

l~'tj!'.l)�1:'11~i0.ICI ~

: 0

. �~i�~~i: ~H o0 � =i1��11:Jcog�1 ,,�.

ovcc
OGND

0

Y1 ~O

5oli ~-

�Ioo
0

tel ORSSI
OGND OAUD

0 0
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il0:.Jj1j1:iJ.I,.~1L1i1'(..!J1iu1a60-rc:g1, 1lit:F1IL.T2a-~

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o

0 OGND

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SIGNETICS O

ODATA 0 l:ll:J

NE605DK 0

0 GND 0 011 ""

#30003

0

00000000000000000

TOP SILK SCREEN

CJ CJ
TOP VIEW

Application note
AN1995

November 13, 1991

BOTTOM VIEW
Figure 5. NE605 SSOP Demo-board Layout (Not Actual Size) 339

Signetics RF Communications
Evaluating the NE605 SO and SSOP demo-board

Application note
AN1995

10

-10

-20
-30 dB
-40
-50
-<10

.. ,. ,:..... 'I-�""' '::::::,,,.!--

THD + N(dB)

t--+--

a..-

tw. REJECTION (dB)

-70

1) NllSE

..;io+--1---+--+--+---l---l---+--l--+--1--+---11---+--+--+---1---1---+--l--I

-125

-115

-105

-95

-85

-75

-<IS

-55

-45

-35

-25

RF LEVEL (dBm)

RSSI (V)

4.75

..... 4.50 -r--t--t--+-+--t--t---t--t--t---+--+--t--t--+---ll---+--+-~-1-:lo"' -i---1

4,25 -l--l---+-+-+----l--+--1--1---+-+-+----l--+--1--11---l--2---l,,,C:.:..+.-+---I

~

v

~

~

3.50 +---'l--+-+-f--+-+-+--11--+-+-t----+-+-......i-+~-::7"4-f--+-+-+~

3.25 +--l---+-+-+----l--+--l---ll---+-+-+--+-__Lj-i.,..q_-1---+----l--+-+---I

3.00

./1

2.75 +--1---+--+--+---+---+--+---'I---+--+----+-~17~+--l---+--+--+---+---l---+----I

~ 2.50 +--l---+-+-+----l--+--l--l---+-+,,"".-i!?:.!-~--1--1---+--+--+----l--+-+---I

:::a g 2.25 +--l---+--+--+---+---1--+--1---i.""/1"--11"---l---l--l--i---l--+---l---1--...l----I 2.00 +--l---+--+--+---+---+--+-~-~-+--+--+--+--l--+---ll---+--+--1---1----1

1.15 +--1---+--+--+---+---+--~-+v...,,,..-+--+---i---1--+--1--+--+--+---1---1---+----1

1.50 +--1---+-+-+--t-.Lj-+v..,,,,e.:+--1---+-+-+----l--+--1--1---+-+-+--1---1

1.25 -t--1---t--+-+--....-1-+V...,,,,..c.r--1--1---+-+-+----l--+--1--1---+-+-+--1---1

1.00

...d7

0.15 +--1---+-.Lj"""v~"+--+--+---+---+--+----11----1---+--1--+--1--+---11----1---+----1

0.50

P'

0.25 -
0.00 -t--+---+--l---t----11---+--+--+---+--+--+---li---+--+--+---+--+--+--1--__,

-125

-115

-105

-95

-85

-75

-<15

-55

-35

-25

RF LEVEL (dBm)

November 13, 1991

Figure 6. NE605 SSOP Performance Graphs
340

Signetics RF Communications
Evaluating the NE605 SO and SSOP demo-board

Application note
AN1995

HOW TO TUNE THE NE605 DEMO-BOARD

Figure 7 shows a trouble-shooting chart for the NE605. It can be used as a general guide to tune the DIP, SO, and SSOP

demo-boards. Below are some of the highlights from the trouble shooting chart that are explained in more detail.

Part may have been damaged, Install another
chip and start over.

�

10

I

I

CONTINUED ON NEXT PAGE

Figure 7. Trouble-shooting Chart for the NE605 Demo-board

November 13, 1991

341

Signetics RF Communications
Evaluating the NE605 SO and SSOP dem0-board
:0

Application note
AN1995

GOOD JOBI

�NOTE: Refer to the appropriate text section of the app. note for further details.

Adjust LO tuning element to achieve the proper LO drive and
check for proper cx>n�ment
values and connection.

November 13, 1991

342

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Evaluating the NE605 SO and SSOP demo-board

Application note
AN1995

How to tell when a pan Is damaged
Since most SO and SSOP sockets hinder the maximum performance of the NE605, it is advisable to solder the packages directly to the board. By this approach, one will be able to evaluate the part correctly. However, it can be a tedious chore to switch to another part using the same layout. Therefore, to be absolutely certain that the chip is damaged, one can measure the DC voltages on the NE605. Table 1 shows the DC voltages that each pin should roughly have to be a good part.

Table 1. Approximate DC Voltage� for theNE605

Pin Number

DC Voltage (V)

1

1.37

2

1.37

3

5.16

4

5.94

5

NIA

6

6.00(Vcc)

7

NIA

8

2.00

9

2.00

10

3.49

11

1.59

12

1.59

13

1.59

14

1.65

15

O.OO(GND)

16

1.60

17

1.60

18

1.60

19

1.60

20

4.87

Note: The DC voltage on Pin 5 1s not specified because it can either be Vee or ground depending if the audio is muted or not (Connecting ground on Pin 5 mutes the audio on Pin 8, while Vee on Pin 5 unmutes the audio).

The DC voltage on Pin 7 is not specified because its DC voltage depends on the strength of the RF signal getting to the input of the NE605. It also can be used as a stability indicator.

If any of the DC voltages are way off in value, and you have followed the trouble-shooting chart, the part needs to be changed.

RSSI Indicator
The next important highlight is using the RSSI pin as a stability indicator. With power connected to the part and no RF signal

applied to the input, the DC voltage should read 250mV or less on Pin 7. Any reading higher than 250mV, indicates a regeneration problem. To correct for the regeneration problem, one should check for poor layout, poor bypassing, and/or poor solder joints. Bypassing the NE605 supply line with a low equivalent series resistance (ESR) capacitor to reduce the RSSI reading can improve the 12dB SINAD measurement by SdB, as found in the lab. If the regeneration problem still exists, read AN1994.
Quad tank and S-Curve
As briefly mentioned in the chart, it is
important to measure the a of the quad tank
if a distortion reading of 1.8% or less cannot be measured. Recall that if the Q of the quad tank is too high for the deviation, then premature distortion will occur. However, if
a the is too low for the deviation' the audio
level will be too low. The audio level coming out of the audio pin should be 140mVRMS to 190mVRMS�
SIGNAL GENERATOR
RF-455kHz Mod Freq.� 1kHz
Mod Level � BkHz

AUDIO PIN
DISTORTION ANALVZER

OSCILLOSCOPE

FREQ. kHz
400 430 455 480 510

DC VOLTAGE
1.86 124 2.13 3.08 2.88

Figure 8. Teet Set-up to Meaeure &Curve of the Quad Tank
If the distortion reading is too high and/or the audio level is too low, then it is important to measure and plot the S-curve of the quad tank. The test set-up used in the lab can be seen in Figure 8.
The following steps were taken to measure the S-curve for the SO and SSOP demo-boards.

Step 1. Remove the second IF ceramic filter from the demo-board.
Step 2. Connect a signal generator to the limiters input through a DC blocking capacitor.
Step 3. Connect a DC voltmeter and an oscilloscope to the audio output pin.
Step 4. Set the signal generator to a 455kHz signal and be sure that the modulation is on (RF=455kHz Mod Freq = 1kHz Mod Level=BkHz). Apply this 455Khz signal to the limiter input such that there is a sinewave on the oscilloscope screen. Adjust the quad tank for maximum sinewave amplitude on the oscilloscope or for lowest distortion. Additionally, adjust the supply input signal to the NE605 such that the 1kHz sinewave reaches its maximum amplitude.
4

3

~
I

2

i
If

r-.. J_
1
~

n. 380 400 420 440 490 490 500 520 FREQUENCY (kHz)
Figure 9. S-Curve for NE605 SO Demo-board

.._

v1...

N

' �N "~rJI
1 380 400 420 440 460 480 500 520 FREQUENCY (kHz)
Figure 10. S-Curve for NE605 SSOP Demo-board

November 13, 1991

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Evaluating the NE605 SO and SSOP demo-board

Application note
AN1995

Step 5. Turn off the modulation and start taking data. Measure the Frequency vs DC voltage. Vary the frequency incrementally and measure the DC voltage coming out of the audio pin. Remember that once the modulation is turned off, the sinewave will disappear from the oscilloscope screen.
Step 6. Plot the S-curve.
Figures 9 and 10 show the S-curve measurements for the SO and SSOP demo-boards. Notice that the center of the S-curve is at 455kHz. The overall linearity determines how much deviation is allowed before premature distortion. Since our application requires �BkHz of deviation, our S-curve is good because it exceeds the linear range of 447kHz to 463kHz.
If the Q of the quad tank needs to be lowered, a designer should put a resistor in parallel with the inductor. The lower the resistor value, the more the Q will be lowered. If the Q needs to be increased, choose a higher Q component. More information on the Quad tank can be found in the NE604A data sheet.
If the linear section of the S-curve is not centered at 455kHz, the quad tank component values need to be recalculated. The way to determine the component values
is by using F = __1_ where F should be
'Or/LC
the IF frequency. In the case of the demo-boards, the IF= 455kHz.
Front End Tuning
The best way to tell if the front end of the NE605 is properly matched is to use a network analyzer in a S11 setting. The lower the dip, the greater the absorption of the wanted frequency. Figures 11 and 12 show the S11 dip for the front end matching of the SO and SSOP demo-boards, respectively.
We have found in the lab that a-BdB to -10dB dip is usually sufficient to get the maximum signal transfer such that a good 12dB SINAD reading is met. The front end circuit uses a tapped-C impedance transformation circuit which matches the 50'1 source with the input impedance of the mixer.
In the process of matching the front end, we have found that the ratio of the two capacitors play an important role in transferring the signal from the source to the mixer input. There should be approximately a 4:1 or 5:1 ratio.

~
- -101--1-4--1--4....:::i:=+..-4--+-4--l
:"g' .
,.~ -2011-+--+--+-+-l-+--+--+-+--l
,f"-30t--+--+--+--+--it---t--t--t--+--i

40

45

50

FREQUENCY (MHz)

Figure 11. S11 Front-End Response for SO Demo-board

-10

~ !--"'I-

i

CJ -20
~

,,,;::-30

40

45

50

FREQUENCY (MHz)

Figure 12. S11 Front-End Response for SSOP Demo-board

Checking the Conversion Gain of the Mixer
Once the front end has been properly matched, a designer should check the conversion gain if there are problems with the SI NAD measurement. Be sure to turn off the modulation when making this measurement.
The method of measuring conversion gain on the bench is fairly simple. For our demo-boards, measure the strength of the 455kHz signal on the matching output network of the mixer with a FET probe. Then measure the 45MHz RF input signal on the matching input network of the mixer. Subtract the two numbers and the measured conversion gain should be around 13dB. Make sure that the input and output matching networks for the mixer have the same impedance since we are measuring voltage gain to get power gain (P = V2/R). Of course this conversion gain value will change ii there is a different RF input. In AN 1994, Figure 16 shows how the conversion gain varies with different RF input frequencies.
Checking the gains in the IF Section
If the IF section does not give 100dB of gain, then the -118dBm SINAD measurement cannot be achieved. In fact some symptoms

of low or no audio level can be due to the IF section.
One way of checking the function of the IF section is to check the gain of the IF amplifier and the IF limiter. The IF amplifier gain should be around 40dB and the IF limiter gain should be around 60dB.
To check this, connect a FET probe to the output of the amplifier. Apply a strong input signal with no modulation and then slowly lower the input signal and wait for the output of the amplifier to decrease. Measure the strength of the output signal in dB and then subtract from it the strength of the input signal in dB. This resulting number indicates the maximum gain of that section. (This method assumes matched input and output impedance.)
If a designer finds one of the sections with lower gain, then one area to check are the IF bypass capacitors. Be sure that the IF bypass capacitors have a good solid connection to the pad. It was also found in the lab that the RSSI stability reading improves when the IF bypass is properly installed.
QUESTION & ANSWER SECTION
Q: When I measure the bandpass response of the IF filters on the SSOP demo-board, it appears to have a little hump compared to the SO demo-board which has a flat filte.r response. Why is there a difference in the bandpass response when the SO and SSOP 605 chips are similar?
A: The answer has to do with the ceramic filters and not the package of the NE605. The reason why the SO demo-board has a flat bandpass response is because it is matched properly with the filter. The SSOP demo board uses the new Murata low profile ceramic 455kHz filter. Unfortunately, the input and output impedance is now 1kn instead of 1.5kn. This presents an impedance mismatch which creates the hump to occur in the bandpass response. But one does not have to worry too much about this response because the situation does not affect the overall performance that much. Additionally, the 12 SINAD measurement is similar whether using the "blue" (1.5k!l) or "white" (1.0kn) Murata filters.
If you are worried about this, then switch to the correct "blue" Murata filters. The SSOP package will work with those filters as well.

November 13, 1991

344

Signetics RF Communications
Evaluating the NE605 SO and SSOP demo-board

Application note
AN1995

But if your design has strict height requirements, the white filters are a good solution.
Q: How much LO signal do you see at the RF port?
A: The worst LO leakage seen at the RF input on the SO and SSOP demo-board is -40dBm/441 mV. This seems to vary with the LO level into the base of the on board transistor. This measurement will also vary with different LO frequencies. The NE605 SO and SSOP demo-boards have a LO frequency of 44.545MHz. Since there are so many variables, a designer needs to measure his/her own board for an accurate LO-RF isolation measurement.
There are several ways to improve the LO leakage from getting to the antenna. One can choose a higher IF frequency and tighten

up the bandwidth of the front-end filter. Another solution is to add a low noise amplifier between the antenna and the mixer, and/or design a double conversion receiver and make sure the 1st mixer has a LO-RF isolation which meets the system specifications.
Q: On the SO and SSOP demo-board, the LO oscillator circuit is tunable with a variable capacitor. Is this a requirement?
A: No. The variable capacitor is used to tune the LO freq., but one can use a fixed value. The advantage of going with a fixed value capacitor is that it is a cheaper component part and there is no need for tuning. The only advantage with a tunable LO is that a designer can optimize the performance of the receiver.

Q: I know that the IF bandwidth of the NE605 allows me to build an IF of 21.4MHZ. Will the NE605 SSOP package perform just as good at 21.4MHz IF as it does at 455kHz?
A: Although we have not worked with NE605 SSOP at 21.4MHZ, we believe that It would be difficult to get a 12dB SINAD measurement at -120dBm. The wavelengths are much smaller at 21.4MHz than 455kHz. Since the wavelengths are smaller, there is a higher probability of regeneration occurring in the IF section. Therefore, a designer will probably have to reduce the gain in the IF section. Additionally, the SSOP package has pins that are physically closer together than with the normal type of packaged parts which can contribute to the unstable state with higher IF frequencies.

November 13, 1991

345

Slgnetlcs RF Communications
Low.;voltage high performance mixer FM IF system

Product specification
NE/SA606

DESCRIPTION

� Temperature compensated logarithmic

PIN CONFIGURATION

The NE/SA606 is a low-voltage high

Received Signal Strength Indicator (RSSI)

performance monolithic FM IF system

with a 90dB dynamic range

D, DK and N Packages

incorporating a mixer/oscillator, two limiting intermediate frequency amplifiers, quadrature detector, logarithmic received signal strength indicator (RSSI), voltage regulator and audio and RSSI op amps. The NE/SA606 is available in 20-lead dual-in-line plastic, 20-lead SOL (surface-mounted small outline

� Low external component count; sui1able for
crystal/ceramic/LC filters
�Excellent sensitivity: 0.31�V into son
matching network for 12dB SINAD (Signal to Noise and Distortion ratio) for 1kHz tone with RF at 45MHz and IF at 455kHz

I, I
17 lfE'c't:iPUNG

large package) and 20-lead SSOP (shrink

� SA606 meets cellular radio specifications

11 IFAIFOUT

small outline package).

� Audio output internal op amp

The NE606 was designed for portable communication applications and will function down to 2. 7V. The RF section is similar to the famous NE605. The audio and RSSI outputs ha\/e amplifiers with access to the feedback path. This enables the designer to level adjust the outputs or add filtering.

� RSSI output internal op amp � Internal op amps with rail-to-rail outputs � ESD protection: Human Body Model 2kV
Robot Model 200V
APPLICATIONS

13 ~~':.UNG
12 ~'mi':.uNG
11 UllTER OUT

FEATURES
� Low power consumption: 3.5mA typical at 3V

� Portable cellular radio FM IF � Cordless phones � Wireless systems

� Mixer input to >150MHz

� RF level meter

� Mixer conversion power gain of 17dB at 45MHz
� XTAL oscillator effective to 150MHz (LC. oscillator or external oscillator can be used at higher frequencies)
� 102dB of IF Amp/Limiter gain
� 2MHz limiter small signal bandwidth

� Spectrum analyzer
� Instrumentation � FSK and ASK data receivers
�Log amps � Portable high performance communication
receiver � Single conversion VHF receivers

ORDERING INFORMATION DESCRIPTION
20-Pin Plastic DIP 20-Pin Plastic SOL (Surface-mount) 20-Pin Plastic SSOP (Surface-mount) 20-Pin Plastic DIP 20-Pin Plastic SOL (Surface-mount) 20-Pin Plastic SSOP (Surface-mount)

TEMPERATURE RANGE Oto +70�C
o to +70�c
0 to +70�C -40 to +85�C -40to +ss�c -40 to +85�C

ORDER CODE NE606N NE606D NE606DK SA606N SA606D SA606DK

ABSOLUTE MAXIMUM RATINGS

SYMBOL

PARAMETER

Vee Single supply voltage

Tsrn Storage temperature range

TA Operating ambient temperature range NE606

SA606

Thermal impedance 9JA

D package DK package N package

RATING
7
-OS to +150
0 to +70
-40to +85
90 117 75

UNITS
v
�c �C �c
�cJW

October 10, 1991

346

853-1576 04268

Signetics RF Communications
Low-voltage high performance mixer FM IF system
BLOCK DIAGRAM

Product specification
NE/SA606

DC ELECTRICAL CHARACTERISTICS
Vee - -t3V, TA = 25�C; unless otherwise stated.

SYMBOL

PARAMETER

Vee Power supply voltage range

Ice

DC current drain

TEST CONDITIONS

LIMITS

NE/SA606

MIN

TYP MAX

2.7

7.0

3.5

4.2

UNITS
v
mA

AC ELECTRICAL CHARACTERISTICS
= TA= 25�C; Vee= +3V, unless otherwise stated. RF frequency= 45MHz + 14.5dBV RF input step-up; IF frequency= 455kHz; R17 2.4kQ
and R18 = 3.3kn; RF level = --45dBm; FM modulation = 1kHz with �8kHz peak deviation. Audio output with de-emphasis filter and C-message
weighted filter. Test circuit Figure 1. The parameters listed below are tested using automatic test equipment to assure consistent electrical characterristics. The limits do not represent the ultimate performance limits of the device. Use of an optimized RF layout will improve many of the listed parameters.

LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

NE/SA606

UNITS

MIN

TYP MAX

Mlxer/Oac section (ext LO" 220mVRMS)

flN

Input signal frequency

150

MHz

fosc Crystal oscillator frequency

150

MHz

Noise figure at 45MHz

6.2

dB

Third-order input intercept point (500 source)

f1 = 45.0; f2 = 45.06MHz Input RF level = -52dBm

-9

dBm

Conversion power gain

Matched 14.5dBV step-up

13.5

17

19.5

dB

500 source

+2.5

dB

RF input resistance

Single--ended input

8

kn

RF input capacitance

3.0

4.0

pF

Mixer output resistance.

(Pin 20)

1.25

1.5

kn

If section

IF amp gain

500 source

44

dB

Limiter gain

500source

58

dB

October 10, 1991

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Signetics RF Communications
Low-voltage high performance mixer FM IF system

Product specification
NE/SA606

AC ELECTRICAL CHARACTERISTICS (Continued)

LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

NE606

UNITS

MIN TYP MAX

Input limiting -3dB, R17a - 2.4k, R17b - 3.3k AM rejection Audio level

Test at Pin 18 80%AM 1kHz Gain of two (2kn AC load)

-109

dBm

45

dB

70

114

160

mv

SINAD sensitivity

IF level-110dBm

17

dB

THO Total hannonic distortion

-35

-50

dB

SIN Signal-to-noise ratio

No modulation for noise

62

dB

IF RSSI output, R9 - 2kn1

IF level= -118dBm IF level = --OBdBm

0.3

.80

v

.70

1.1

1.80

v

RSSI range

IF level = -23dBm

1.20

1.8

2.50

v

90

dB

RSSI accuracy IF input impedance IF output impedance

Pin 18 Pin 16

;t.1.5

dB

1.3

1.5

kn

0.3

kn

Limiter input impedance Limiter output impedance Limiter output voltage RF/IF section (Int LO)

Pin 14 Pin 11 Pin 11

1.3

1.5

0.3

130

kn kn mVRMS

Audio level System RSSI output System SINAD sensitivity

3V = Vrx;, RF level = -27dBm 3V = Vrx;, RF level = -27dBm RF level = -117dBm

240

mVRMS

2.2

v

12

dB

NOTE: 1. T_he generator source impedanel'. is son~ but the ~~A606 input impedance at Pin 18 is 1500'1. As a result, IF level refers to the actual
signal that enters the NE/SA606 input (Pm 18) which 1s about 21 dB less than the �available power" at the generator.

CIRCUIT DESCRIPTION The NE/SA606 is an IF signal processing system suitable for second IF systems with input frequency as high as 150MHz. The bandwidth of the IF amplifier and limiter is at least 2MHz with 90dB of gain. The gain/bandwidth distribution is optimized for 455kHz, 1.5kn source applications. The overall system is well-suited to battery operation as well as high performance and high quality products of all types.
The input stage is a Gilbert cell mixer with oscillator. Typical mixer characteristics include a noise figure of 6.2dB, conversion gain of 17dB, and input third-order intercept of -9dBm. The oscillator will operate in excess of 200MHz in UC tank configurations. Hartley or Colpitts circuits can be used up to 100MHz for xtal configurations. Butler oscillators are recommended for xtal configurations up to 150MHz.
The output impedance of the mixer is a 1.Skn resistor pennitting direct connection to a

455kHz ceramic filter. The input resistance of the limiting IF amplifiers is also 1.5kn. With most 455kHz ceramic filters and many crystal filters, no impedance matching network is necessary. The IF amplifier has 43dB of gain and 5.5MHz bandwidth. The IF limiter has 60dB of gain and 4.5MHz bandwidth. To achieve optimum linearity of the log signal strength indicator, there must be a 12dB(v) insertion loss between the first and second IF stages. If the IF filter or interstage network does not cause 12dB(v) insertion loss, a fixed or variable resistor or an L pad for simultaneous loss and impedance matching can be added between the first IF output (Pin 16) and the interstage network. The overall gain will then be 90dB with 2MHz bandwidth.
The signal from the second limiting amplifier goes to a Gilbert cell quadrature detector. One port of the Gilbert cell is internally driven by the IF. The other output of the IF is AC-<:eupled to a tuned quadrature network.

This signal, which now has a 90� phase relationship to the internal signal, drives the other port of the multiplier cell.
The demodulated output of the quadrature drives an internal op amp. This op amp can be configured as a unity gain buffer, or for simultaneous gain, filtering, and 2nd-order temperature compensation if needed. It can drive an AC load as low as 2kn with a rail-to-rail output
A log signal strength completes the circuitry. The output range is greater than 90dB and is temperature compensated. This log signal strength indicator exceeds the criteria for AMPs or TACs cellular telephone. This signal drives an internal op amp. The op amp is capable of rail-to-rail output. It can be used for gain, filtering, or 2nd-order temperature compensation of the RSSI, if needed.
NOTE: dB(v) = 201og VourN1N

October 10, 1991

348

Signetics RF Communications
Low-voltage high performance mixer FM IF system

Product specification
NE/SA606

!10

R19 IFT1 111k

October 10, 1991

R8 39.2

!IN-CIRCUIT ZSC2-1B

= RSSI Vee

AUDIO

Automatic Test Circuit Component Lisi

C1 100pF NPO Ceramic
C2 390pF NPO Ceramic
CS 100nF .:t.10% Monollthlc Ceramic C6 22pF NPO Ceramic
C7 1nF Ceramic CB 10.0pF NPO Ceramic
C9 100nF .:t.10% Monollthlc Ceramic C10 15~F Tantalum (minimum) C12 2.2�F C14 100nF .:t.10% Monolithic Ceramic
C15 10pF NPO Ceramic
C17 100nF .:t.10% Monollthlc Ceramic C18 100nF .:t.10%MonollthlcCeramlc C21 100nF .:t.10% Monolithic Ceramic C23 100nF .:t.10% Monollthlc Ceramic C25 100nF .:t.10% Monolithic Ceramic C26 100nF .:t.10% Monolithic Ceramic

C27 Flt 1 Flt 2 IFT 1
L1 L2
X1 R9 R10 R11 R12 R13 R14 R17 R18 R19

100nF .:t.10% Monollthlc Ceramic
Ceramic Filler Murata SFG455A3 or equiv
Ceramic Fiiter Murata SFG455A3 or equiv 455kHz (Ce= 180pF) Toko RMC-2A6597H
147-160nH Collcraft UNl-10/142--04.JOSS 0.8..tf nominal
Toko 292CNS-T1038Z 44.545MHz Crystal ICM4712701 2kn .:t.1% 1/4W Metal Fiim 8.2kn.:t.1%
10kn.:t.1%
2kn .:t.1% 20kn.:t.1% 10kn .:t.1% 2.4kn .:t.5% 1/4W Carbon Composition 3.3kn 16kn �

Figure 1. N.E/SA606 45MHz Test Circuit (Relays as shown)

349

Signetics RF Communications
Low-voltage high performance mixer FM IF system

Product specification
NE/SA606

R18 3.3k
C15

Cl
J,__.___ IFTI
INPUT

OU~T Vee

AUDIO

Appllcatlon Component Uat

C1 100pF NPO Ceramic C2 390pF NPO Ceramic CS 100nF .:t.10% Monolithic Ceramic C6 22pF NPO Ceramic C7 1nF Ceramic CS 10.0pF NPO Ceramic C9 100nF .:t.10% McnollthlcCeramlc C10 15iJ' Tantalum (minimum)
C12 2.2�F .:t.10% Ceramic C14 100nF .:t.10% Monolithic Ceramic C15 10pF NPO Ceramic C17 100nF .:t.10% Monollthlc Ceramic C18 100nF .:t.10% Mcmollthlc Ceramic C21 100nF :t.10% Monolithic Ceramic C23 100nF .:t.10% Moncllthlc Ceramic C25 100nF .:t.10% Monolithic Ceramic

C26 C27 Flt1 Flt2 IFT1
L1 L2
X1 RS R10 R11 R17 R18 R19

100nF .:t.10% Monollthlc Ceramic 2.2�F Tantalum or Electrolytic
Ceramic Filter Murata SFG455A3 or equiv Ceramic Filter Murata SFG455A3 or equiv
455kHz (Ce= 180pF) Toko RMC-2A6597H 147-160nH Collcraft UNl-10/142-04J08S o.a~H nomlnal
Toko 292CNS-T1038Z 44.545MHz Crystal ICM4712701 Nol Used In Appllcsllon Board (see Note 8, pg 8)
8.2k .:t.5% 1/4W Carbon Composition
10k.:t.5% 1/4W Carbon Composition 2.4k .:t.5% 1/4W Carbon Composition 3.3k .:t.5% 1/4W Carbon Composition 16k .:t.5% 1/4W Carbon Composition

Figure 2. NE/SA606 45MHz Application Circuit

October 10, 1991

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Signetics RF Communications
Low-voltage high performance mixer FM IF system

Product specification
NE/SA606

RF GENERATOR 45MHz
Vcc(+3)

NE606 DEMO BOARD RSSI AUDIO

DC VOLTMETER

DE-EMPHASIS FILTER
C-MESSAGE

SCOPE

HP339A DISTORTION ANALYZER

Figure 3. NE/SA606 Application Circuit Test Set Up
NOTES: 1. C-message: The C-message and de-emphasis filter combination has a peak gain of 10 for accurate measurements. Without the gain, the
measurements may be affected by the noise of the scope and HP339 analyzer. The de-emphasis filter has a fixed -6dB/Octave slope between 300Hz and 3kHz. 2. Ceramic filters: The ceramic filters can be 30kHz SFG455A3s made by Murata which have 30kHz IF bandwidth (they come in blue), or 16kHz CFU455Ds, also made by Murata (they come in black). All of our specifications and testing are done with the more wideband filter. 3. RF generator: Set your RF generator at 45.000MHz, use a 1kHz modulation frequency and a 6kHz deviation if you use 16kHz filters, or BkHz if you use 30kHz filters. 4. Sensitivity: The measured typical sensitivity for 12dB SINAD should be 0.35�Vor-116dBm at the RF input. 5. Layout: The layout is very critical in the perfonnance of the receiver. We highly recommend our demo board layout. 6. RSSI: The smallest RSSI voltage (i.e., when no RF input is present and the input is terminated) is a measure of the quality of the layout and design. If the lowest RSSI voltage is 500mV or higher, it means the receiver is in regenerative mode. In that case, the receiver sensitivity will be worse than expected. 7. Supply bypass and shielding: All of the inductors, the quad tank, and their shield must be grounded. A 10-15�F or higher value tantalum capacitor on the supply line is essential. A low frequency ESR screening test on this capacitor will ensure consistent good sensitivity in production. A 0.1 �F bypass capacitor on the supply pin, and grounded near the 44.545MHz oscillator improves sensitivity by 2-3dB. 8. R5 can be used to bias the oscillator transistor at a higher current for operation above 45MHz. Recommended value is 22kn, but should not be below 1Okn.

October 10, 1991

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Signetics RF Communications
Low-voltage high performance mixer FM IF system

mA 6

Vcc=7V

Vcc=SV
4
Vcc=3V
Vcc=2.7V

Product specification
NE/SA606

Figure 4. Ice vs Temperature

-a.a

-8.5

-e.o

'E

l -41.5

!i ~

-10.0

Iwi: -10.5
.t.i.&l -11.0 -11.S
i
i!! -12.0
a
&I -12.5

I

I

I

I

I

I

I

I

I

I

I

--~---:---~--~--,--~---~--~--~--~---:---~

--,---�- --.- --,. --. --.. . -.- I

I

I

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I

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I

I

l:-~-~-~,..;;-~-~~---~�~-:::;::::;~-

1

I

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- - LI � � .JI � � �I' � � �'I � � � !I. � 2.

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� 7V �1 --~1---�I -~-I~--�1 --~I-- 1

.L �� J �� J � � � ~ � � ~ � � ! . . J � � ��---~

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-13.5

7- - -:- - -:- - -:- - - t- - ;- - -:-

,

I

I

-14.0

-30 -30 -10 0

10 20

ao 40 50 50 70 80

Temperature (�C)

Figure 5. Third Order Intercept Point vs Supply Voltage

October 10, 1991

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Signetics RF Communications
Low-voltage high performance mixer FM IF system

Product specification
NE/SA606

8.00 ~--------------------------~

'

I

I

I

I

7.75

i - - - ... - - ..... - - . - - - � - - _,_ - - " - - .l - - ... - - - , - - - � - - - � - - -

I

I

I

I

I

I

I

I

7.50 - - - .- - - .&. - - .J - - �1 - - -, - - - , - - - ,- - - i - - ... - - -. - - -, - - - ' -

-�- �- -� -� - - -- - -- -- - 7.25

- - ...

--

I I

-

-

-I
I

-

-

--

--

- ...

I I

- ... - - _,

-

- -I t

I

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I

I

7.00 ...... I .... .&. .... "' .... -, .. - I -, .... - , - .... ,- .... .... .t. .. - i .... -, .. - -�-

aw :
"" 6.50
u:
....Ill 8.25
~

5.75 5.50

I

I

I

I

I

I

I

I

- - - - - -� - - -1- - - - - - - - - - - - - - - - - - -1 - - - - - - - - - .... -

I

I

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5.25

I

I

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I

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. . . . -; . . . . -1 .. � -1- . . . . ,� . . . . ,- . . . . ~ . . . . ~ . . . . -, . . . . �1 . . . . . . I . . . . . . ,. . . . . . I"' ..

5.00 .....__ _ __._ _,__ _ _ _ _ _ _ _ _ _ _ _,__ _ _ _ _....;..._,

-40 -30 -20 -10

10 20 30 40 50 60 70 80 TEMPERATURE (�C)

Figure 6. Mixer Noise Figure vs Supply Voltage

10.00----------------------------

17.75

I

I

I

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I

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~ -

- .1 -

-

- 1� I

-

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-

J. - I

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~z 17.25
~
I17.00 16.75
16.5

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t

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16.25

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16.00~-'--..J_..J_-L-'--'-~-'---'--..J_..J___J_-L-L-'--''--'--.J-..L---L--L-'--'-__JL--J

-40 -30 -20 -10

10 20 30 40 50 60 70 80

TEMPERATURE (�C)

Figure 7. Conversion Gain vs Supply Voltage

October 10, 1991

353

Signetics RF Communications
Low-voltage high performance mixer FM IF system

Product specification
NE/SA606

10

- ... -�- - - - !. - - - J .. - - ..... - - _ 1_ .. - - !. - ..... J ... - .. -� - - - - ... - - ...

I

I

I

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34

RF� INPUT LEVEL (dBm)

Figure 8. Mixer Third Order Intercept and Compreaalon

October 10, 1991

354

Signetics RF Communications
Low-voltage high performance mixer FM IF system

Product specification
NE/SA606

~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ' ..... I AUDIO I ~----..;-~~~--~~~--~~ ~~~--~~~-:-~~~..;-~~~--~~--1 v-----_: _---- ----_;_ ---- ----- ---- ----- ---- _; _----

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RF LEVEL (dBm)

Figure 9. Sensitivity vs RF Level (-40�C)

--� --- -------,.-�--- -.- ---- I -

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-55

-45

-25

RF LEVEL (dBm)

Figure 10. Sensitivity vs RF Level (+25�C)

October 10, 1991

355

Signetics RF Communications
Low-voltage high performance mixer FM IF system

Product specification
NE/SA606

'

I

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I AUDIO I

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RF LEVEL (dBm)

Figure 11. Sensitivity vs RF Level (Temperature 85"C)

0 ........................ .! .... ..

AUDIO
-----.-----�r-----

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-15

25

45

55

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125

TEMPERATURE ("C)

Figure 12. Relative Audio Level, Distortion, AM Rejection and Noise vs Temperature

October 10, 1991

356

Signetics RF Communications
Low-voltage high performance mixer FM IF system

Product specification
NE/SA606

2.ooo+---!--+--+---!--+--+---+--+--l---+--+---!--+--+--+-+--+-~--::o-f'_==_=__'.�---.�1.=--=----1::l-
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---~~
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-95

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-35

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IF LEVEL (dBm)

Figure 13. RSSI (455kHz IF @ 3V)

2.1 2.0

: : : : : t::::

j::::: t:::: :1:::::

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RF LEVEL (dBm)

Figure 14. RSSI vs RF level and Temperature-Vee= 3V

October 10, 1991

357

Signetics RF Communications
Low-voltage high performance mixer FM IF system

Product specification
NE/SA606

y 300
250

Ycc�7V

200

i

Ycc:SV

>e 150 TQ,....-1iiii1-Y-cc==SV~~~==:�============~======:::=ei

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-55

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-15

25

45

65

85

105

125

Figure 15. Audio Output vs Temperature

October 10, 1991

358

Signetics RF Communications
Low-voltage high performance mixer FM IF system

Product specification
NE/SA606

SIGNETICS
NE/SA606SSOP

~0~
:-> C::

RFIN

GND
0

�Appllee to Stand-Alone data sheets only.

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October 10, 1991

Figure 16. NE/SA606DK SSOP Board Layout (2X Actual Size* - For Reference Use Only) 359

Signetics RF Communications
Low-voltage high performance mixer FM IF system
~~
~ SIGNETICS 8�8 RFIN
~ NE606D
GND
���������

Product specification
NE/SA606

'AppllH to Sland�Alone data �heats only.

KTDN9191 NE606

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October 10, 1991

���������
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Figure 17. NE/SA606D SOL Board Layout (2X Actual Size* -For Reference Use Only)

360

Signetics RF Communications
Low-voltage high performance mixer FM IF system

Product specification
NE/SA606

*Applle� to Stllnd-Alone data lheetaonly.

00
e

00

RF
INPUT

-00
65 0

~- 0

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Figure 18. NE/SA606N DIP Board Layout (Actual Size* - For Reference Uae Only)

October 10, 1991

361

Slgnetlcs RF Communications
Low-voltage high performance mixer FM IF system

Preliminary specification
NE/SA616

DESCRIPTION The NE/SA616 is a low-voltage high performance monolithic FM IF system incorporating a mixer/oscillator, two limiting intermediate frequency amplifiers, quadrature detector, logarithmic received signal strength indicator (RSSI), voltage regulator and audio and RSSI op amps. The NE/SA616 is available in 20-lead dual-in-line plastic, 20-lead SOL (surface-mounted small outline large package) and 20-lead SSOP (shrink small outline package).
The NE616 was designed for portable communication applications and will function down to 2. 7V. The RF section is similar to the famous NE615. The audio and RSSI outputs have amplifiers with access to the feedback path. This enables the designer to adjust the output levels or add filtering.
FEATURES
� Low power consumption: 3.5mA typical at 3V
� Mixer input to >150MHz
� Mixer conversion power gain of 17dB at 45MHz
� XTAL oscillator effective to 150MHz (L.C. oscillator or external oscillator can be used at higher frequencies)
� 102dB of IF Amp/Limiter gain
� 2MHz IF amp/limiter small signal bandwidth

� Temperature compensated logarithmic Received Signal Strength Indicator (RSSI) with a 80dB dynamic range
� Low external component count; suitable for crystal/ceramic/LC filters
�Excellent sensitivity: 0.31�V into SOQ matching network for 12dB SINAD (Signal to Noise and Distortion ratio) for 1kHz tone with RF at 45MHz and IF at 455kHz
� SA616 meets cellular radio specifications � Audio output internal op amp � RSSI output internal op amp � Internal op amps with rail-to-rail outputs � ESD protection: Human Body Model 2kV
Robot Model 200V
APPLICATIONS � Portable cellular radio FM IF
� Cordless phones
� Wireless systems
� RF level meter
� Spectrum analyzer
� Instrumentation
� FSK and ASK data receivers
�Log amps � Portable high performance communication
receiver �Single conversion VHF receivers

PIN CONFIGURATION D, DK and N Packages

FEED'JIA'l!~ 7
AUDIOOUT 8
FEEDB~~~ 9
QUADRATURE 10 IN

19 ll'tc'f:iPLING 18 IFAMPIN 17 ll'Et'tfuPLING
LIMITER IN LIMITER DECOUPLING LIMITER DECOUPLING 11 LIMITER OUT

ORDERING INFORMATION
DESCRIPTION 20-Pin Plastic DIP 20-Pin Plastic SOL (Surface-mount) 20-Pin Plastic SSOP (Surface-mount) 20-Pin Plastic DIP 20-Pin Plastic SOL (Surface-mount) 20-Pin Plastic SSOP (Surface-mount)

TEMPERATURE RANGE
Oto +70�C
o to +70�C o to +70�C
-40 to +B5�C
-40 to +B5�C
-40 to +B5�C

ORDER CODE NE616N NE616D NE616DK SA616N SA616D SA616DK

ABSOLUTE MAXIMUM RATINGS

SYMBOL

PARAMETER

Vee Single supply voltage

Tsm Storage temperature range

TA Operating ambienttemperature range NE616

SA616

Thermal impedance 0JA

D package DK package N package

RATING
7 -65 to +150
Oto +70
-40 to +85
90 117 75

UNITS
v oc oc oc
oc/W

October 22, 1991

362

Signetics RF Communications
Low-voltage high performance mixer FM IF system
BLOCK DIAGRAM

Preliminary specification
NE/SA616

DC ELECTRICAL CHARACTERISTICS Vee= +3V, TA= 25�C; unless otherwise stated.

SYMBOL

PARAMETER

Vee Power supply voltage range

Ice

DC current drain

TEST CONDITIONS

LIMITS

NE/SA616

MIN

TYP MAX

2.7

7.0

3.5

5.0

UNITS
v
mA

AC ELECTRICAL CHARACTERISTICS TA= 25�C; Vee= +3V, unless otherwise stated. RF frequency= 45MHz + 14.5dBV RF input step-up; IF frequency= 455kHz; R17 = 2.4kn and R18 = 3.3kn; RF level = -45dBm; FM modulation = 1kHz with �8kHz peak deviation. Audio output with de-emphasis filter and C-message weighted filter. Test circuit Figure 1. The parameters listed below are tested using automatic test equipment to assure consistent elecbicai characterristics. The limits do not represent the ultimate performance limits of the device. Use of an optimized RF layout will improve many of the listed parameters.
LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

NE/SA616

UNITS

MIN

TYP MAX

Mlxer/Oao section (ext LO " 220mVRMS)

!IN

Input signal frequency

150

MHz

lose Crystal oscillator frequency
Noise figure at 45MHz

150

MHz

6.8

dB

ThircH>rder input intercept point (50'2 source)

11 = 45.0; 12 = 45.0SMHz Input RF level. -52dBm

-9

dBm

Conversion power gain

Matched 14.5dBV step-up

11

17

dB

50'2source

+2.5

dB

RF input resistance

Single-ended input

8

k'2

RF input capacitance

3.0

4.0

pF

Mixer output resistance

(Pin20)

1.25

1.5

k'2

IF section

IF amp gain

50'2source

44

dB

Limiter gain

50'2source

58

dB

October 22, 1991

363

Signetics RF Communications
Low-voltage high performance mixer FM IF system

Preliminary specification
NE/SA616

AC ELECTRICAL CHARACTERISTICS (Continued)

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS NE616 MIN TVP MAX

UNITS

Input limiting -3dB, R11a = 2.4k, Rm= 3.3k Test at Pin 18

AM rejection

80%AM 1kHz

Audio level

Gain of two (2kn AC load)

SI NAO sensitivity

IF level-110dBm

THO Total harmonic distortion

SIN

Signal--kH1oise ratio

No modulation for noise

IF RSSI output, R9 = 2k'21

IF level= -118dBm

IF level= -68dBm

IF level = -23dBm

-105

dBm

40

dB

60

114

mV

13

dB

-30

-45

dB

62

dB

0.3

.80

v

.70

1.1

2

v

1.0

1.8

2.50

v

RSSI range

80

dB

RSSI accuracy IF input impedance IF output impedance

Pin 18 Pin 16

.:t.2

dB

1.3

1.5

kn

0.3

kn

Limiter input impedance Limiter output impedance Limiter output voltage RF/IF section (Int LO)

Pin 14 Pin 11 Pin 11

1.3

1.5

0.3

130

kn kn mVRMs

Audio level System RSSI output System SINAO sensitivity

3V = Vex;, RF level = --27dBm 3V = Vex;, RF level = --27dBm RF level = -117dBm

240

mVRMS

2.2

v

12

dB

NOTE:

1.

T_he generator source impedance is 50'2, but the NE/SA616 input impedance signal that enters the NE/SA616 input (Pin 18) which is about 21dB less than

at Pin 18 is 1500'2. As the "available power" at

atheregsuelnt~ItFolre.vel

refers

to

the

actual

CIRCUIT DESCRIPTION The NE/SA616 is an IF signal processing system suitable for second IF systems with input frequency as high as 150MHz. The bandwidth of the IF amplifier and limiter is at least 2MHz with 90dB of gain. The gain/bandwidth distribution is optimized for 455kHz, 1.5k'2 source applications. The overall system is well-suited to battery operation as well as high performance and high quality products of all types.
The input stage is a Gilbert cell mixer with oscillator. Typical mixer characteristics include a noise figure of 6.2dB, conversion gain of 17dB, and input third-order intercept of -9dBm. The oscillator will operate in excess of 200MHz in UC tank configurations. Hartley or Colpitts circuits can be used up to 100MHz for xtal configurations. Butler oscillators are recommended for xtal configurations up to 150MHz.
The output impedance of the mixer is a 1.5k'2 resistor permitting direct connection to a

455kHz ceramic filter. The input resistance of the limiting IF amplifiers is also 1.Skn. With most 455kHz ceramic filters and many crystal filters, no impedance matching network is necessary. The IF amplifier has 43dB of gain and 5.5MHz bandwidth. The IF limiter has 60dB of gain and 4.5MHz bandwidth. To achieve optimum linearity of the log signal strength indicator, there must be a 12dB(v) insertion loss between the first and second IF stages. If the IF filter or interstage network does not cause 12dB(v) insertion loss, a fixed or variable resistor or an L pad for simultaneous loss and impedance matching can be added between the first IF output (Pin 16) and the interstage network. The overall gain will then be 90dB with 2MHz bandwidth.
The signal from the second limiting amplifier goes to a Gilbert cell quadrature detector. One port of the Gilbert cell is internally driven by the IF. The other output of the IF is AC-coupled to a tuned quadrature network.

This signal, which now has a 90� phase relationship to the internal signal, drives the other port of the multiplier cell.
The demodulated output of the quadrature drives an internal op amp. This op amp can be configured as a unity gain buffer, or for simultaneous gain, filtering, and 2nd-order temperature compensation if needed. It can drive an AC load as low as 2k'2 with a rail-to-rail output.
A log signal strength completes the circuitry. The output range is greater than 90dB and is temperature compensated. This log signal strength indicator exceeds the criteria for AMPs or TACs cellular telephone. This signal drives an internal op amp. The op amp is capable of rail-to-rail output. It can be used for gain, filtering, or 2nd-order temperature compensation of the RSSI, if needed.
NOTE: dB(v) = 20log VoorN1N

October 22, 1991

364

Signetics RF Communications
Low-voltage high performance mixer FM IF system

Preliminary specification
NE/SA616

-25dB,

-10dB,

-29dB,

-10.&dB,

1500/Sllo PAD 50/SOa PAD 929/SOa PAD 50/SOaPAD

-36dB, 1561</SOn PAD

~10

R11 IFT1 1811

October 22, 1991

fi=i:il
�II-CIRCUIT ZSC2-18

RB 39.2
= ~~ Vee

AUDIO OUT

Automatic Tast Circuit Component List

C1 100pF NPO Ceramic C2 390pF NPO Ceramic
CS 100nF.:t10% Monolithic Ceramic
C6 22pF NPO Ceramic C7 1nF Ceramic CS 10.0pF NPO Ceramic
C9 100nF.:t10% Monolithic Ceramic C10 15iJ' Tantalum (minimum) C12 2.2�F C14 100nF .:t10% Monolithic Ceramic
C15 10pF NPO Ceramic
C17 100nF.:t10% Monolithic Ceramic C18 100nF.:t10%MonollthicCeramlc C21 100nF.:t10%MonollthlcCeramlc C23 100nF .:t10% Monolithic Ceramic C25 100nF .:t10% Monolithic Ceramic C26 100nF .:t10% Monollthlc Ceramic

C27 Flt 1 Flt 2 IFT 1
L1 L2
X1 R9 R10 R11 R12 R13 R14 R17 R18 R19

100nF .:t10% Monolithic Ceramic
Ceramic Fiiter Murata SFG455A3 or equiv
Ceramic Fiiter Murata SFG455A3 or equiv
455kHz (Ce =180pF) Toko RMC-2A6597H
147-160nH Collcraft UNl-10/142-04J08S
0.8.,.H nominal
Toko 292CNS-T1038Z
44.545MHz Crystal ICM4712701 2kn .:t1% 1/4W Metal Fiim 8.2tcn .:t1%
10kn .:t1%
2tcn .:t1%
20kn.:t1% 10kn.:t1% 2.4kn.:t5% 1/4W Carbon Composition 3.3tcn 16kn

Figure 1. NE/SA616 45MHz Teat Circuit (Relays aa shown)

365

Signetics RF Communications
Low-voltage high performance mixer FM IF system
R18 3.3k

Preliminary specification
NE/SA616

= T Vee

AUDIO OUT

Application Component Ust

C1 100pF NPO Ceramic C2 390pF NPO Ceramic CS 100nF :1:10% Monollthlc Ceramic C6 22pF NPO Ceramic C1 1nF Ceramic C8 10.0pF NPO Ceramic C9 100nF ;1:10% Monollthlc Ceramic C10 15�F Tantalum (minimum)
C12 2.2�F :1:10% Ceramic C14 100nF �10% Monollthlc Ceramic C15 10pF NPO Ceramic
C17 100nF :1:10% Monollthlc Ceramic C18 100nF ;1:10% Monollthlc Ceramic C21 100nF �10% Monollthlc Ceramic C23 100nF :1:10% Monolithic Ceramic C25 100nF �10% Monolithic Ceramic

C26 C27 Flt 1 Flt2 IFT1
L1 L2
X1
RS
R10 R11 R17 R18 R19

100nF �10% Monollthlc Ceramic 2.2�F Tantalum or Electrolytic Ceramic Filter Murata SFG455A3 or equiv Ceramic Fiiter Murata SFG455A3 or equiv
= 455kHz (Ce 180pF) Toko RMC-2A6597H
147-160nH Collcrafl UNl-10/142--04J08S
0.8�H nominal Toko 292CNS-T1038Z
44.545MHz Crystal ICM4712701
Not Uaed In Appllcatlon Board <-Note 8, pg 8)
8.2k ;1:5% 1/4W Carbon Composition
10k ;1:5% 1/4W Carbon Compasltlon 2.4k ;1:5% 1/4W Carbon Composition 3.3k ;1:5% 1/4W Carbon Composition 16k:1:5% 1/4W Carbon Composition

October 22. 1991

Figure 2. NE/SA616 45MHz Application Circuit 366

Signetics RF Communications
Low-voltage high performance mixer FM IF system

Preliminary specification
NE/SA616

RF GENERATOR 45MHz
Vcc(+3)

NE616 DEMO BOARD RSSI AUDIO

DC VOLTMETER

DE-EMPHASIS FILTER

SCOPE

HP339A DISTORTION ANALYZER

Figure 3. NE/SA616 Application Circuit Test Set Up
NOTES: 1. C-message: The C-message and de-emphasis filter combination has a peak gain of 10 for accurate measurements. Without the gain, the
measurements may be affected by the noise of the scope and HP339 analyzer. The de-emphasis filter has a fixed -6dB/Octave slope between 300Hz and 3kHz. 2. Ceramic filters: The ceramic filters can be 30kHz SFG455A3s made by Murata which have 30kHz IF bandwidth (they come in blue), or 16kHz CFU455Ds, also made by Murata (they come in black). All of our specifications and testing are done with the more wideband filter. 3. RF generator: Set your RF generator at 45.000MHz, use a 1kHz modulation frequency and a 6kHz deviation if you use 16kHz filters, or SkHz if you use 30kHz filters. 4. Sensitivity: The measured typical sensitivity for 12dB SINAD should be 0.35�V or-11 SdBm at the RF input. 5. Layout: The layout is very critical in the performance of the receiver. We highly recommend our demo board layout. 6. RSSI: The smallest RSSI voltage (i.e., when no RF input is present and the input is terminated) is a measure of the quality of the layout and design. If the lowest RSSI voltage is 500mVor higher, it means the receiver is in regenerative mode. In that case, the receiver sensitivity will be worse than expected. 7. Supply bypass and shielding: All of the inductors, the quad tank, and their shield must be grounded. A 10-15�F or higher value tantalum capacitor on the supply line is essential. A low frequency ESR screening test on this capacitor will ensure consistent good sensitivity in production. A 0.1�F bypass capacitor on the supply pin, and grounded near the 44.545MHz oscillator improves sensitivity by 2-3dB. 8. RS can be used to bias the oscillator transistor at a higher current for operation above 45MHz. Recommended value is 22kn, but should not be below 10k'1.

October 22, 1991

367

Signetics RF Communications
Low-voltage high performance mixer FM IF system

Preliminary specification
NE/SA616

mA 6

Vcc=7V

5
I.
I

lccCmA> 4

Vcc:5V

Vcc:SV

3

Vcc=2.7V

-55

-35

-15

25

45

S5

85

105

125

TEMPERATURE ("C)

Figure 4. Ice vs Temperature

-s.o

-S.5

-s.o

i"

ID
!!.

-S.5

!i
ii!

-10.0

Iwi:: -10.5

i...&! -11.0 -11.5
~ -12.0
a

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I

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t-

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-14.0

"""� -30 -20 -10 0

10 20

30 40 50 50 70 50

Temperature (�C)

Figure 5. Third Order Intercept Point va Supply Voltage

October 22, 1991

368

Signetics RF Communications
Low-voltage high performance mixer FM IF system

Preliminary specification
NE/SA616

8.00 .....-...,.-~--~-..,.----....,..-...,.-....,,--~-.,...-----...,

I

I

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t

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...............

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s.oo

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-40 -30 -l!O -10 0 10 20 30 40 50 80 70 80

TEMPERATURE ("C)

Figure 6. Mixer Noise Figure vs Supply Voltage

17.75

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1 .... .. 1...... I.,. .... L ..

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-40 ...3Q -l!O -10

10 20 30 40 50 80 70 80

TEMPERATURE ("C)

Figure 7. Conversion Gain vs Supply Voltage

October 22, 1991

369

Signetics RF Communications
Low-voltage high performance mixer FM IF system

Preliminary specification
NE/SA616

. .

.

10 .. - .. �.... - ... !. - - - .! - - ...., .......... �....... - !. - - - J - - ....... - - - ,. - - -

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24

34

RP INPUT LEVEL (dBm)

Figure 8. Mixer Third Order Intercept and Compression

October 22, 1991

370

Signetics RF Communications
Low-voltage high performance mixer FM IF system

Preliminary specification
NE/SA616

. ITT---_:_--------_:_----------------------_;_---- AUDIO
~ ~ ~ ~ ~ 0 - - - - - !.._;-----~------------------------:----~----------1

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RF LEVEL (dim)
Figure 10. Sensitivity vs RF Level (+25"C)

O::tober 22, 1991

371

Signetics RF Communications
Low-voltage high performance mixer FM IF system

Preliminary specification
NE/SA616

'

.. . -�-.--�-�t-��--:--�-�-- I

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-

: i

1
- .. - .. -� -

----

I \\ ...... ,.. ... "' ~ ... ' ; ' , ... - : -

I

I

I

I

I

I

......... T ........... '"'I'"' ............ ., ... "" ......... t"' ......... ,. ~,. "' ......... ~ ... ., ..... "'I .. ,. ........

........ .., .. 10...... :\�\���-,'...... ...... ,- ............ -, ............... I~ ............ - ,I ............... TI .............. ,- - - - - ~I - - - - -

-:- -- - -- -- �- I

\:I I

I

I

I

I

I

I

- - - - - ~ .. ...~, -- - ~ - ..... -- - - ~ - - -... -- - --: - - - ~ -- - - - - ......

-45

.........

-

I
-�-

-

.........

~ I

-

:.' ..,~,.;...I -

-

...

I

f

I

... - - - - -,- - ... - ... : - - ... - ...... - ......... i ... - ... - -

----- .. -... -:- --- .. ~I

I

"�~~~,-:-- =-~~I~~ .._911't.-~

~ .... "'!.-:. -. ---~~=-r����-I~

-55

-

.. -

-

I - �- -

-

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-

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-

-

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... -

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... �- ........ ,

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..

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-:-

..........

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i

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-

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~:;.:.-.:.-.:: .::.-.:.-LI -.;

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I

...... -85+-~~~T-~~--i--i~~-.~~~-+~~~

~~~..-~~~T-~~--i--i~~-.~~~-1

-125

-115

-105

-115

-115

-75

-85

-65

-45

RF LEVEL (dBm)

Figure 11. Sensitivity vs RF Level (Temperature 85"C)

r--------- 0 ............... '

'

AUDIO

I

I

I

I

I

I

I

-5 - - - - - - ~ ...... - - ... ~ - - ... - ... �:- ... - ... - .. :- - - - - ... ; ... - - - - -: ........ - - -:- ... - ......... ~. - - .. - ..

-10 -15

.. ,. ....... "' ~ ... -
I

.. -

I .. ..I -

.... -

I

I

I

...... 1 . . . . . . . . . . . . . . . I. . . . . . . . . . . . . . . .&. -

. I

I

I

I

------~-----1------1------~-----

I

I

I

I

- ....... - .. ~ ............ ~ .............., "' "' - ....... ,.. "' - .... - T

'
.......... J .............1 . . . . . . . . . . - 1............ ..

I

I

I

Vcc11113Y RF:4SMHz

' � ...... L ...........

RF LEVEL= -45dBm DEVIATION= �8kHz

I

I

I

I AUDIOLEVEL�+117.lrnVRMS

- ... - - - - ,. ...... - - ... j - ...... - ... -. - - ... - - - .- ... - - - ... i ..... - ..... 1 .......... - ...... - ... - ...... ,. - - - ... -

I

I

I

I

.......... ,..

r I

.......... -

j I

.

.

.

.

.

.

.

.

.

.

.

.

.

.

I I

..................

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,.

..........

j I

............

-.I

...............I, .............

I j

......... ...

I

I

I

I

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I

I

I

-35 - - ..........� - - - - - _, .. - - - - - ... - ...... - ... .& ...... - - - .... - - - ... - - �- - - ..... - !.. .... - ... - .! ... - ... - ... -

I

I

I

I

I

I

I

I

,P-.. � ...... -40

I

I

I

I

I

I

I

I

L ............... 1 ............... , . . . . . . . . . . . . . ,............... ,. ............. .J ........ - .... 1.............. L ........... ..

.............,_

I

I

I

I

I

I

I

=: ' -45
-5Q

-- -� -� ---- I
I I

~: .!..!.'...~ .__ ... ~I ; ...........

I r

...........

I
1

..........

-.I ............

I
DISTORTION

...

I ~

...........

~ I

...........

I

. . . , ~ � ..........

I I

J�� I � I

....... -......

..

I I

. , . - � ; _-.-. I�.----�-�- :- . : . ,

.... -.... - . ----:------:-- -... -. ~

~-:'..=.:..!::..:..:..: ~:..:..:..:: ~-

~

-65 - - - ... - -: ...... - ... -:- ............. ~ - .......... ; ........... -:- .. AM R~ECTION ..... ~ ............. ~ ..... __ ......

-eo~ -- -� -- -----~i- -��---I :-----I -~--~~I~~~;;~~I ~~~~~-: ~~~~~~~: ~~~~~:: c:::~~

I

I

NOISE'

I

I

....... -85+-~~~-r~~~~i--~~~

~~~-.~~~~..-~~~-+-~~~--i--i~~~-+-~~~--1

-65

-35

-15

25

4S

85

85

105

125

TEMPERATURE ("C)

Figure 12. Relative Audio Level, Distortion, AM Rejection and Noise vs Temperature

October 22, 1991

372

Signetics RF Communications
Low-voltage high performance mixer FM IF system

Preliminary specification
NE/SA616

- 4 -��-:.::-1.: 2.ooo+---+-+-__,f---t--i--+-+---+-+--l--+--f---t--i--+-+---+V--::---:::4'='=::.~-�::: ::l-
�B6:; J..~��:.:;.L_._._ __,

!E 11..2s00o-ol-+~--f--t~--f--~t--f--~+-f--+~--f+-~---f-t~--f--t~--f--+~--f+-~--+b--,-,.t.--j-~t,~-J-..+~-~--.:::i:~~.P~-~�"-d�~'-�:~:~�;4j~ ~~o-.fl._-;_''\E,_'~~'..-:b.j..-j~"-"j.-R"OO1M-~-rf-~-+f-~-+f-~---tl

>

...-~;:~

-4D"C

.,.-;;:~

o.eoo+--l---+--t--+--1-....-.::-bi~~-~-�ifi-~-'F'--t--l'---+--l--t--t--t--t--l--+--+---I

--~ 0.400~

�� ~I

..... ~000-t-~-t-~-+~-t~--ir- r-~1--~+-~+-~-t-~-t-~-+~-t~--i~--ir-~1--~1--~-t-~+-~-+-~-1

-95

-85

-75

-85

-55

-45

--35

IF LEVEL (dBm)

-15

-5

Figure 13. RSSI (455kHz IF @3V)

2.1

2.0 -- -- -~ - - - - ~ - - -- - ~ - - - - -:- - - - - ~ - - -- -:- - - -- ~ - - - - - ~ - - - - -~....�-�!. ---

1

I

I

I

I

I

I

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1.1 .. - .. - � r - "' .. � -.- - - - - i - - - "' ... ,.. � � � ... i ..... � .... ,...... - - - -. - - - - .. ,.. .........._

:::::: :::t:::: 1.8 ---- -~ -----:- ........ r-----:- ----~ ---.. -:- .......... ~ ..... ---~-��� --~-.-..-.:.:

1.7 1.8

~ ~:::: :!:::::~:::: :::::~:.~~:�~�~.;.f�~~~~�:!:::::

1.5

::::~ ~:::: ~::::: ~:::: ::: ::::~ -:::::~�:�~:: ~:::::::: :~:~::: : E 1.4

w
(!I

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~~ 1.2

1.1

-

I
......... :�

.....

-

-

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-

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0.8

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..........

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0.8 :::::~::::]::-~;r:~::~:::::I:::::::::::;:::::~::::J:::::

0.7

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0.8

! ............... ......... ,. L .... - ... ...1 ... .......... 1 .......... .. 1 ... .........

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I

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0.5

.. -' - ............ L .............. 1.. - "' ..... J ............... 1..............1 .... ........ i_ - ... - - ...1 ............ ...

I

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0.4

.............. ...1 .. - - ... - i. .............. 1............. _, ........... ... 1..... - ...... .J .............. L ..............1 ....... "' ....

I

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..... ....... o.3+-~~~.-~~--<,....~~--~~~

. ~~~-t-~~~ ....~~~-1-~~~1--~~

~~~--1

-125

-115

-105

-85

-85

-75

-55

-45

--35

RF LEVEL (dBm)

Figure 14. RSSI vs RF Level and Temperature - Vee"' 3V

October 22, 1991

373

Signetics RF Communications
Low-voltage high performance mixer FM IF system

Preliminary specification
NE/SA616

v
300
250
200
,,,.,
'iali: 150
100
50
0 -55

Vcc�7V
Vcc=SV Ycc=3V Ycc:2.7V

-35

-15

25

45

65

85

Figure 15. Audio Output vs Temperature

105

125

October 22, 1991

374

Signetics RF Communications
Low-voltage high performance mixer FM IF system

Preliminary specification
NE/SA616

SIGNETICS
NE/SA616SSOP

~0~
~ ~

RF IN

GND
0

�Applle� to Stand�Alone data aheeta only.

�����
� ��� GND

NE616 KTDN9191

0

,,....._
..,,--._'--"
'-.../
~

.,,....._
'--",,--._
&

0

. 0 ,,....._
'-.../
0

~ 8~~ ~

�/ ' . .
'-../

8 8C�) �/'.. '-../

0

0

. .
'-.../ '-.../

���������

October 22, 1991

Figure 16. NE/SA616DK SSOP Board Layout (2X Actual Size* - For Reference Use Only) 375

Signetics RF Communications
Low-voltage high performance mixer FM IF system

Preliminary specification
NE/SA616

~ (:;
~ SIGNETICS ~0P, RFIN

~

NE616D

GND
���������

�Applies to Stand-Alone data sheets only.

KTDN9191 NE616

.. . . ��.��
~ ~
..:.., ..:.., GND � �
~:-!~(~-;

October 22, 1991

���������
0

. r:-. ~
~ ~

...._....~

~~�B'-/

(�) 8

8
~ �
'-..../

0C�)
8

2 c:J

0 08

���������

Figure 17. NE/SA616D SOL Board Layout (2X Actual Size� - For Reference Use Only)

376

Signetics RF Communications
Low-voltage high performance mixer FM IF system

Preliminary specification
NE/SA616

*Applies to Stand~lone data sheets only.

00

()

00

RF
INPUT (--:-) (--:-)

a o -0()
?i5 0

~- 0

0 00<�> 00 0 Jf'J

-

- m0 0 0 0C:X!B0<-B0<!.001::1.�B' 0

(:) . .
(i ('.) �

0

0

~

0
�

0

~ $~ IB

GND��:"."��

0 r;P�0~ 0

0 ~

~
0� � 0

SIGNETICS q.p 0 0

NE616

<�> 0

AUDI08

0

(�) r\.;-/.0000 ()0

OUT

0 RSSI

(:) Vee ::�:: GND

Figure 18. NE/SA616N DIP Board Layout (Actual Size� - For Reference Use Only)

October 22, 1991

377

Slgnetlcs RF Communications
Low voltage high performance mixer FM IF system

Preliminary specification
NE/SA607

DESCRIPTION The NE/SA607 is a low voltage high performance monolithic FM IF system incorporating a mixer/oscillator, two limiting intermediate frequency amplifiers, quadrature detector, logarithmic received signal strength indicator (RSSI), voltage regulator and audio and RSSI op amps. The NE/SA607 is available in 20-lead dual-in-line plastic, 20-lead SOL (surface-mounted miniature package) and 20-lead SSOP package.
The NE607 was designed for portable communication applications and will function down to 2. 7V. The RF section is similar to the famous NE605. The audio output has an internal amplifier with the feedback pin accessible. The RSSI output is buffered. The NE607 also has an extra limiter output. This signal is buffered from the output of the limiter and can be used to perform frequency check. This is accomplished by comparing a reference frequency with the frequency check signal using a comparator to a varactor or PLL at the oscillator inputs.
FEATURES
� Low power consumption: 3.5mA typical at 3V
� Mixer input to > 150MHz
� Mixer conversion power gain of 17dB at 45MHz
� XTAL oscillator effective to 150MHz (L.C. oscillator or external oscillator can be used at higher frequencies)
� 102dB of IF Amp/Limiter gain
� 2MHz limiter small signal bandwidth

� Temperature compensated logarithmic Received Signal Strength Indicator (RSSI) with a 90dB dynamic range
� Low external component count; suitable for crystal/ceramic/LC filters
�Excellent sensitivity: 0.31�V into son
matching network for 12dB SINAD (Signal to Noise and Distortion ratio) for 1kHz tone with RF at 45MHz and IF at 455kHz � SA607 meets cellular radio specifications � Audio output internal op amp � RSSI output internal op amp � Buffered frequency check output � Internal op amps with rail-to-rail outputs � ESD protection: Human Body Model 2kV
Robot Model 200V
APPLICATIONS � Portable cellular radio FM IF
� Cordless phones
� Narrow band cellular applications (NAMPS/ NTACS)
� RF level meter
� Spectrum analyzer
� Instrumentation
� FSK and ASK data receivers
�Log amps � Portable high performance communication
receivers � Single conversion VHF receivers � Wireless systems

PIN CONFIGURATION D, DK and N Packages
14 LIMITERIN LIMITER DECOUPLING LIMITER DECOUPLING LillTEROUT

ORDERING INFORMATION DESCRIPTION
20-Pin Plastic DIP 20-Pin Plastic SOL (Surface-mount) 20-Pin Plastic SSOP (Surface-mount) 20-Pin Plastic DIP 20-Pin Plastic SOL (Surface-mount) 20-Pin Plastic SSOP (Surface-mount)

TEMPERATURE RANGE
oto +70�c o to +70�C o to +70�C c -40to +es0
-40 to +85�C
-40 to +85�C

ORDER CODE NE607N NE607D NE607DK SA607N SA607D SA607DK

October 10, 1991

378

Signetics RF Communications
Low voltage high performance mixer FM IF system
BLOCK DIAGRAM

Preliminary specification
NE/SA607

ABSOLUTE MAXIMUM RATINGS

SYMBOL

PARAMETER

Vee Single supply wltage

Tsro TA

Storage temperature range Operating ambient temperature range NE607

Thermal impedance
eJA

SA607
Dpackage DK package N package

RATING 7
-65 to +150 0 to +70
-40 to +85 90 117 75

UNITS
v oc oc oc
oc/W

DC ELECTRICAL CHARACTERISTICS
Vee = +3V, TA = 25�C; unless otherwise stated.

SYMBOL

PARAMETER

Vee

Power supply voltage range

Ice

DC current drain

TEST CONDITIONS

LIMITS

NE/SA607

MIN

TYP MAX

2.7

7.0

3.5

4.2

UNITS
v
mA

October 10, 1991

379

Signetics RF Communications
Low voltage high performance mixer FM IF system

Preliminary specification
NE/SA607

AC ELECTRICAL CHARACTERISTICS
TA= 25�C; Vee= +3V, unless otherwise stated. RF frequency= 45MHz + 14.5dBV RF input step-up; IF frequency= 455kHz; R17 = 2.4k; R18 = 3.3k; RF level = -45dBm; FM modulation = 1kHz with �BkHz peak deviation. Audio output with de-emphasis filter and C-message weighted filter. Test circuit Figure 1. The parameters listed below are tested using automatic test equipment to assure consistent electrical characterristics. The limits do not represent the ultimate performance limits of the device. Use of an optimized RF layout will improve many of the listed parameters.
LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

NE/SA607

UNITS

MIN TYP MAX

Mlxer/Osc section (ext LO= 220mVRMS)

f1N

Input signal frequency

lose Crystal oscillator frequency

150

MHz

150

MHz

Noise figure at 45MHz

6.2

dB

Third-order input intercept point (50n source)

11 = 45.0; f2 = 4S.06MHz Input RF Level= -52dBm

-9

dBm

Conversion power gain

Matched 14.SdBV step-up

13.S

17

19.5

dB

son source

+2.S

dB

RF input resistance

Single-ended input

8

kn

RF input capacitance

3.0

4.0

pF

Mixer output resistance

(Pin 20)

1.2S

1.S

kn

IF section

IF amp gain

son source

44

dB

Limiter gain

son source

S8

dB

Input limiting -3clB, R17 = 2.4k

TestatPin18

-109

dBm

AM rejection

80%AM 1kHz

45

dB

Audio level

Gain of two (2kn AC load)

70

114

160

mV

SINAD sensitivity

RF level -11 OdB

17

dB

THO Total harmonic distortion

-3S

-50

dB

SIN

Signal-to-noise ratio

IF RSSI output, R9 = 2k.Q1

No modulation for noise IF level =-118dBm IF level= -68dBm IF level = -23dBm

62

dB

0.3

0.8

v

.70

1.1

1.80

v

1.2

1.8

2.S

v

RSSI range

90

dB

RSSI accuracy

�1.S

dB

IF input impedance

1.3

1.5

kn

IF output impedance

0.3

kn

Limiter input impedance

1.30

1.S

kn

Limiter output voltage

(Pin 11)

130

mVRMS

RF/IF section (Int LO)

Audio level System RSSI output

3V = Vee, RF level = -27dBm 3V = Vee, RF level = -27dBm

240

mVRMS

2.2

v

System SINAD sensitivity

RF level= -117dBm

12

dB

NOTE: 1. The generator source impedance is son, but the NE/SA607 input impedance at Pin 18 is 15000. As a result, IF level refers to the actual
signal that enters the NE/SA607 input (Pin 18) which is about 21 dB less than the "available power" at the generator.

October 10, 1991

380

Signetics RF Communications
Low voltage high performance mixer FM IF system

Preliminary specification
NE/SA607

CIRCUIT DESCRIPTION The NE/SA607 is an IF signal processing system suitable for second IF systems with input frequency as high as 150MHz. The bandwidth of the IF amplifier and limiter is at least 2MHz with 90dB of gain. The gain/bandwidth distribution is optimized for 455kHz, 1.5kn source applications. The overall system is well-suited to battery operation as well as high performance and high quality products of all types.
The input stage is a Gilbert cell mixer with oscillator. Typical mixer characteristics include a noise figure of 6.2dB, conversion gain of 17dB, and input third-order intercept of -9dBm. The oscillator will operate in excess of 200MHz in UC tank configurations. Hartley or Colpitts circuits can be used up to 1OOMHz for xtal configurations. Butler oscillators are recommended for xtal configurations up to 1SOMHz.
The output impedance of the mixer is a 1.5kn resistor permitting direct connection to a 455kHz ceramic filter. The input resistance of

the limiting IF amplifiers is also 1.Skn. With most 455kHz ceramic filters and many crystal filters, no impedance matching network is necessary. The IF amplifier has 43dB of gain and 5.5MHz bandwidth. The IF limiter has SOdB of gain and 4.5MHz bandwidth. To achieve optimum linearity of the log signal strength indicator, there must be a 12dB(v) insertion loss between the first and second IF stages. If the IF filter or interstage network does not cause 12dB(v) insertion loss, a fixed or variable resistor or an L pad for simultaneous loss and impedance matching can be added between the first IF output (Pin 16) and the interstage network. The overall gain will then be 90dB with 2MHz bandwidth.
The signal from the second limiting amplifier goes to a Gilbert cell quadrature detector. One port of the Gilbert cell is internally driven by the IF. The other output of the IF is AC-coupled to a tuned quadrature network.
This signal, which now has a 90� phase relationship to the internal signal, drives the other port of the multiplier cell.

The demodulated output of the quadrature drives an internal op amp. This op amp can be configured as a unity gain buffer, or for simultaneous gain, filtering, and 2nd-order temperature compensation if needed. It can drive an AC load as low as 2kn with a rail-to-rail output.
A log signal strength completes the circuitry. The output range is greater than 90dB and is temperature compensated. This log signal strength indicator exceeds the criteria for AMPs or TACs cellular telephone. This signal is buffered through an internal unity gain op amp. The frequency check pin provides a buffered limiter output. This is useful for implementing an AFC (Automatic Frequency Check) function. This same output can also be used in conjunction with limiter output (Pin 11) for demodulating FSK (Frequency Shift Keying) data. Both pins are of the same amplitude, but 180� out of phase.
NOTE: dB(v) = 20log VourN1N

October 10, 1991

381

Signetics RF Communications
Low voltage high performance mixer FM IF system

� Preliminary specification
NE/SA607

-25dB, 1500/50o PAD

-29dB,

-10.BdB,

929/SOn PAD 50/SOn PAD

-36dB, 156k/50n PAD

~10

R11 1Fr1 161c

October 10, 1991

MINI-CIRCUIT ZSC2-1B

R8 39.2
Vee

�
AUDIO

IC14

Automatic Test Circuit Component List

C1 100pF NPO Ceramic C2 390pF NPO Ceramic CS 100nF �10% Monolithlc Ceramic C& 22pF NPO Ceramic C7 1nF Ceramic CS 10.0pF NPO Ceramic C9 100nF �10% Monolithlc Ceramic C10 15�F Tantalum (minimum) C12 2.2�F C14 100nF .:1:10% Monolithlc Ceramic C15 10pF NPO Ceramic C17 100nF .:1:10% Monolithlc Ceramic C18 100nF .:1:10% Monolithic Ceramic C21 100nF .:1:10% Monolithic Ceramic C23 100nF .:1:10% Monolithic Ceramic C25 100nF .:1:10% Monolithic Ceramic

C26 C27 Fit 1 Fil2 IFT1
L1 L2
X1
R9 R10 R11 R12 R14 R17 R18 R19

0.1�F �10% Monolithic Ceramic 2.2�F Ceramic Filler Murata SFG455A3 or equiv
Ceramic Filler Murata SFG455A3 or equiv
455kHz (Ce= 180pF) Toke RMC-2A6597H
147-160nH Collcraft UNl-10/142--04J08S
3.3�H nominal
Toke 292CNS-T1046Z
44.545MHz Cryatal ICM4712701 2kn .:1:1% 1/4W Metal Film 8.2kn.:1:1% 10kn.:1:1% 2kn.:1:1% 10kn.:1:1% 2.4k0 .:1:5% 1/4W Carbon Compoaltion 3.3kn .:1:5% 1/4W Carbon Composition 16kn.:1:5% 1/4W Carbon Composition

Figure 1. NE/SA607 45MHz Teat Circuit (Reiaya aa shown)

382

Signetics RF Communications
Low voltage high performance mixer FM IF system

Preliminary specification
NE/SA607

C15

C1
J.~CHzC�,__.________. J
INPUT

R10
JC27 R19 161<
AUDIO FREQ CHECK

Application Component List

C1 100pF NPO Ceramic C2 390pF NPO Ceramic
CS 100nF �10% Monolithic Ceramic CS 22pF NPO Ceramic C7 1nF Ceramic CB 10.0pF NPO Ceramic
C9 100nF �10% Monolithic Ceramic C10 1S�F Tantalum (minimum) C12 2.2�F �10% Ceramic C14 100nF �10% Monolithic Ceramic C1S 10pF NPO Ceramic C17 100nF �10% Monolithic Ceramic C18 100nF �10% Monolithic Ceramic C21 100nF �10% Monolithic Ceramic

C23 C2S C26 C27 Flt 1 Flt 2 IFT 1
L1 L2
X1 RS R17 R18 R19

100nF �10% Monolithic Ceramic
1OOnF�10% Monolithic Ceramic 100nF �10% Monolithic Ceramic 2.2�F �10% Monolithic Ceramic Ceramic Filter Murata SFG4SSA3 or equiv Ceramic Filter Murata SFG4SSA3 or equiv
4S5kHz (Ce = 1BOpF) Toko RMC-2A6S97H
147-160nH Coilcraft UNl-10/142--04J08S O.B�H nominal
Toko 292CNS-T1038Z
44.S4SMHz Crystal ICM4712701 Not Used In Application Board (see Note 8)
2.4kn �S% 1/4W Carbon Composition 3.3kn �S% 1/4W Carbon Composition 1&kn �S% 1/4W Carbon Composition

October 10, 1991

Figure 2. NE/SA607 4SMHz Application Circuit 383

Signetics RF Communications
Low voltage high performance mixer FM IF system

Preliminary specification
NE/SA607

RF GENERATOR 45MHz

Vee (+3)

DC VOLTMETER

DE-EMPHASIS FILTER
C-MESSAGE

SCOPE

HP339A DISTORTION ANALYZER

Figure 3. NE/SA607 Application Circuit Test Set Up
NOTES: 1. C-message: The C-message and de-emphasis filter combination has a peak gain of 10 for accurate measurements. Without the gain, the
measurements may be affected by the noise of the scope and HP339 analyzer. The de-emphasis filter has a fixed -6dB/Octave slope between 300Hz and 3kHz. 2. Ceramic filters: The ceramic filters can be 30kHz SFG455A3s made by Murata which have 30kHz IF bandwidth (they come in blue), or 16kHz CFU455Ds, also made by Murata (they come in black). All of our specifications and testing are done with the more wideband filter. 3. RF generator: Set your RF generator at 45.000MHz, use a 1kHz modulation frequency and a 6kHz deviation if you use 16kHz filters, or 8kHz if you use 30kHz filters. 4. Sensitivity: The measured typical sensitivity for 12dB SINAD should be 0.35�V or-116dBm at the RF input. 5. Layout: The layout is very critical in the performance of the receiver. We highly recommend our demo board layout. 6. RSSI: The smallest RSSI voltage (i.e., when no RF input is present and the input is terminated) is a measure of the quality of the layout and design. If the lowest RSSI voltage is 500mV or higher, it means the receiver is in regenerative mode. In that case, the receiver sensitivity will be worse than expected. 7. Supply bypass and shielding: All of the inductors, the quad tank, and their shield must be grounded. A 10-15�F or higher value tantalum capacitor on the supply line is essential. A low frequency ESR screening test on this capacitor will ensure consistent good sensitivity in production. A 0.1�F bypass capacitor on the supply pin, and grounded near the 44.545MHz oscillator improves sensitivity by 2-3dB. 8. R5 can be used to bias the oscillator transistor at a higher current for operation above 45MHz. Recommended value is 22kn, but should not be below 10kn.

October 10, 1991

384

Signetics RF Communications
Low voltage high performance mixer FM IF system

rnA 6

Vcc=7V

Preliminary specification
NE/SA607

Ycc=SV Vcc=3V Vcc=2.1v

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October 10, 1991

385

Signetics RF Communications
Low voltage high performance mixer FM IF system

Preliminary specification
NE/SA607

'

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Figure 7. Conversion Gain vs Supply Voltage

October 10, 1991

386

Signetics RF Communications
Low voltage high performance mixer FM IF system

Preliminary specification
NE/SA607

10

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October 10, 1991

387

Signetics RF Communications
Low voltage high performance mixer FM IF system

Preliminary specification
NE/SA607

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Oc:lober 10, 1991

388

Signetics RF Communications
Low voltage high performance mixer FM IF system

Preliminary specification
NE/SA607

I

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Figure 12. Relative Audio Level, Distortion, AM Re)ectlon end Noise vs Temperature

October 10, 1991

389

Signetics RF. Communications
Low voltage high performance mixer FM IF system

Preliminary specification
NE/SA607

2.000+----l--+--+---l--l--l---+--+--l---+-+---l--+--+--+-+--l-v-:::--,.""'-:::::--"'"--+-=_.---1=---"1'-

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-125

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RF LEVEL (dBm)

Figure 14. RSSI ve RF Level and Temperature-Vee= 3V

October 10, 1991

390

Signetics RF Communications
Low voltage high performance mixer FM IF system

Preliminary specification
NE/SA607

v
300
250
200
":a,:;'
~ 150
100
50

-55

-35

-15

25

45

65

85

Figure 15. Audio Output vs Temperature

105

125

October 10, 1991

391

Signetics RF Communications
Low-voltage high performance mixer FM IF system

Preliminary specification
NE/SA617

DESCRIPTION
The NE/SA617 is a low voltage high performance monolithic FM IF system incorporating a mixer/oscillator, two limiting intermediate frequency amplifiers, quadrature detector, logarithmic received signal strength indicator (RSSI), voltage regulator and audio and RSSI op amps. The NE/SA617is available in 20-lead dual-in-line plastic, 20-lead SOL (surface-mounted miniature package) and 20-lead SSOP package.
The NE617was designed for portable communication applications and will function down to 2. 7V. The RF section is similar to the famous NE605. The audio output has an internal amplifier with the feedback pin accessible. The RSSI output is buffered. The NE617 also has an extra limiter output. This signal is buffered from the output of the limiter and can be used to perform frequency check. This is accomplished by comparing a reference frequency with the frequency check signal using a comparator to a varactor or PLL at the oscillator inputs.
FEATURES
� Low power consumption: 3.SmA typical at 3V
� Mixerinputto>150MHz
� Mixer conversion power gain of 17d8 at 45MHz
� XTAL oscillator effective to 150MHz (L.C. oscillator or external oscillator can be used at higher frequencies)
� 102dB of IF Amp/Limiter gain
� 2MHz IF amp~imiter small signal bandwidth

� Temperature compensated logarithmic Received Signal Strength Indicator (RSSI) with a BOdB dynamic range
� Low external component count; suitable for crystal/ceramic/LC filters
son �Excellent sensitivity: 0.31�V into
matching network for 12dB SINAD (Signal to Noise and Distortion ratio) for 1kHz tone with RF at 45MHz and IF at 455kHz � SA617 meets cellular radio specifications � Audio output internal op amp � RSSI output internal op amp � Buffered frequency check output � Internal op amps with rail-to-rail outputs � ESD protection: Human Body Model 2kV
Robot Model 200V
APPLICATIONS
� Portable cellular radio FM IF
� Cordless phones
� Narrow band cellular applications (NAMPS/ NTACS)
� RF level meter
� Spectrum analyzer
� Instrumentation
� FSK and ASK data receivers
�Log amps � Portable high performance communication
receivers � Single conversion VHF receivers � Wireless systems

PIN CONFIGURATION
D, DK and N Packages
MIXER OUT IFAMP DECOUPLING IF AMP IN IFAMP DECOUPLING IF AMP OUT GND LIMITER IN LIMITER DECOUPLING LIMITER DECOUPLING LIMITER OUT

ORDERING INFORMATION
DESCRIPTION 20-Pin Plastic DIP 20-Pin Plastic SOL (Surface-mount) 20-Pin Plastic SSOP (Surface-mount) 20-Pin Plastic DIP 20-Pin Plastic SOL (Surface-mount) 20-Pin Plastic SSOP (Surface-mount)

TEMPERATURE RANGE Oto +70'C 0 to +70'C 0 to +70'C -40 to +85'C -40 to +85'C -40 to +85'C

ORDER CODE NE617N NE617D NE617DK SA617N SA617D SA617DK

October 22, 1991

392

Signetics RF Communications
Low-voltage high performance mixer FM IF system
BLOCK DIAGRAM

Preliminary specification
NE/SA617

ABSOLUTE MAXIMUM RATINGS

SYMBOL

PARAMETER

Vee Single supply voltage

Tsrn TA

Storage temperature range Operating ambient temperature range NE617

Thermal impedance 9JA

SA617
D package DK package N package

RATING 7
~5to+150
Oto +70
-40to +85 90 117 75

UNITS
v oc oc oc
oc/W

DC ELECTRICAL CHARACTERISTICS
Vee= +3V, TA= 25�C; unless otherwise stated.

SYMBOL

PARAMETER

Vee

Power supply voltage range

Ice

DC current drain

TEST CONDITIONS

LIMITS

NE/SA617

MIN

TYP MAX

2.7

7.0

3.5

5.0

UNITS
v
mA

October 22, 1991

393

Signetics RF Communications
Low-voltage high performance mixer FM IF system

Preliminary specification
NE/SA617

AC ELECTRICAL CHARACTERISTICS
TA = 25�C; Vee = +3V, unless otherwise stated. RF frequency = 45MHz + 14.5dBV RF input step-up; IF frequency = 455kHz; R17 = 2.4k; R1 B = 3.3k; RF level = -45dBm; FM modulation = 1kHz with �BkHz peak deviation. Audio output with de-emphasis filter and C-message weighted filter. Test circuit Figure 1. The parameters listed below are tested using automatic test equipment to assure consistent electrical characterristics. The limits do not represent the ultimate performance limits of the device. Use of an optimized RF layout will improve many of the listed parameters.
LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

NE/SA617

UNITS

MIN

TYP MAX

Mlxer/Osc section (ext LO= 220mVRMS)

f1N lose

Input signal frequency Crystal oscillator frequency Noise figure at 45MHz

150

MHz

150

MHz

6.B

dB

Third---Order input intercept point (50Q source)

11 = 45.0; 12 = 45.06MHz Input RF Level= -52dBm

-9

dBm

Conversion power gain

IF section
THD S/N

RF input resistance RF input capacitance Mixer output resistance
IF amp gain Limiter gain Input limiting -3dB, R17 = 2.4k AM rejection Audio level SINAD sensitivity Total harmonic distortion Signal-to-noise ratio IF RSSI output, R9 = 2kQ1

RSSI range RSSI accuracy IF input impedance IF output impedance Limiter input impedance Limiter output impedance Limiter output voltage RF/IF section (Int LO) Audio level System RSSI output System SINAD sensitivity

Matched 14.5dBV step-up 50Q source Single-ended input
(Pin 20)
50Qsource 50Qsource Test at Pin 1B BO%AM 1kHz Gain of two (2kQ AC load) RF level -11 OdB
No modulation for noise IF level= -11BdBm IF level = --OBdBm IF level= -23dBm
(Pin 11) (Pin 11)
3V = Vee. RF level = -27dBm 3V =Vee, RF level= -27dBm RF level =-117dBm

11.0

17

dB

+2.5

dB

B

kQ

3.0

4.0

pF

1.25

1.5

kQ

44

dB

58

dB

-105

dBm

40

dB

60

114

mV

13

dB

-30

-45

dB

62

dB

0.3

0.B

v

.70

1.1

2.0

v

1.0

1.B

2.5

v

BO

dB

�2.0

dB

1.3

1.5

kQ

0.3

kQ

1.30

1.5

kQ

0.3

kQ

130

mVRMS

240

mVRMS

2.2

v

12

dB

NOTE: 1. The generator source impedance is 50Q, but the NE/SA617 input impedance at Pin 1Bis 1500'2. As a result, IF level refers to the actual
signal that enters the NE/SA617 input (Pin 18) which is about 21dB less than the "available power" at the generator.

October 22, 1991

394

Signetics RF Communications
Low-voltage high performance mixer FM IF system

Preliminary specification
NE/SA617

CIRCUIT DESCRIPTION
The NE/SA617 is an IF signal processing system suitable for second IF systems with input frequency as high as 150MHz. The bandwidth of the IF amplifier and limiter is at least 2MHz with 90dB of gain. The gain/bandwidth distribution is optimized for 455kHz, 1.5kQ source applications. The overall system is well-suited to battery operation as well as high performance and high quality products of all types.
The input stage is a Gilbert cell mixer with oscillator. Typical mixer characteristics include a noise figure of 6.2dB, conversion gain of 17dB, and input third-order intercept of -9dBm. The oscillator will operate in excess of 200MHz in UC tank configurations. Hartley or Colpitts circuits can be used up to 100MHz for xtal configurations. Butler oscillators are recommended for xtal configurations up to 150MHz.
The output impedance of the mixer is a 1.5kQ resistor permitting direct connection to a 455kHz ceramic filter. The input resistance of

the limiting IF amplifiers is also 1.5kQ. With most 455kHz ceramic filters and many crystal filters, no impedance matching network is necessary. The IF amplifier has 43dB of gain and 5.5MHz bandwidth. The IF limiter has 60dB of gain and 4.5MHz bandwidth. To achieve optimum linearity of the log signal strength indicator, there must be a 12dB(v) insertion loss between the first and second IF stages. If the IF filter or interstage network does not cause 12dB(v) insertion loss, a fixed or variable resistor or an L pad for simultaneous loss and impedance matching can be added between the first IF output (Pin 16) and the interstage network. The overall gain will then be 90dB with 2MHz bandwidth.
The signal from the second limiting amplifier goes to a Gilbert cell quadrature detector. One port of the Gilbert cell is internally driven by the IF. The other output of the IF is AC-coupled to a tuned quadrature network.
This signal, which now has a 90� phase relationship to the internal signal, drives the other port of the multiplier cell.

The demodulated output of the quadrature drives an internal op amp. This op amp can be configured as a unity gain buffer, or for simultaneous gain, filtering, and 2nd-order temperature compensation if needed. It can drive an AC load as low as 2kQ with a rail-to-rail output.
A log signal strength completes the circuitry. The output range is greater than 90dB and is temperature compensated. This log signal strength indicator exceeds the criteria for AMPs or TACs cellular telephone. This signal is buffered through an internal unity gain op amp. The frequency check pin provides a buffered limiter output. This is useful for implementing an AFC {Automatic Frequency Check) function. This same output can also be used in conjunction with limiter output {Pin 11) for demodulating FSK (Frequency Shift Keying) data. Both pins are of the same amplitude, but 180� out of phase.
NOTE: dB{v) = 201og VourN1N

October 22, 1991

395

Signetics RF Communications
Low-voltage high performance mixer FM IF system

Preliminary specification
NE/SA617

-25dB,

-29dB, 929/SOnPAD

-10.6dB, 50/SOnPAD

a ~ a9-6.5=

3.3k 32.8 71.5

-=

T

R17 4k

~

T

C19

=

-36dB, 156k/50n PAD
r i5-1.7=
1.3k
-= TC16 ~15

C1
C2 R19 161<

October 22, 1991

MINI-CIRCUIT ZSC2-1B

R8 39.2
-= ~~ Vee

AUDIO OUT

Automatic Test Circuit Component List

C1 100pF NPO Ceramic
C2 390pF NPO Ceramic
cs 100nF �10% Monolithic Ceramic cs 22pF NPO Ceramic
C7 1nFCeramlc
ca 10.0pF NPO Ceramic
C9 100nF �10% Monolithic Ceramic
C10 15�F Tantalum (minimum) C12 2.2�F C14 100nF .�10% Monollthlc Ceramic
C15 10pF NPO Ceramic
C17 100nF �111"k Monolithic Ceramic
C18 100nF �10% Monolithic Ceramic C21 100nF �10% Monolithic Ceramic C23 100nF �111"k Monolithic Ceramic C25 100nF �10% Monolithic Ceramic

C26 C27 Fii 1 Flt 2 IFT 1
L1 L2
X1 R9 R10 R11 R12 R14 R17 R18 R19

0.1�F �10% Monolllhlc Ceramic 2.2�F Ceramic Filter Murata SFG455A3 or equiv
Ceramic Filter Murata SFG455A3 or equiv
455kHz (Ce= 180pF) Toko RMC-2A6597H 147-160nH Coilcraft UNl-10/142--04J08S
3.3�H nominal
Toko 292CNS-T1046Z
44.545MHz Crystal ICM4712701 2kn.�1% 1/4W Metal Film 8.2kn�1% 10kn�1% 2kn�1% 10kn�1% 2.41<.Q �5% 1/4W Carbon Composition 3.31<.Q �5% 1/4W Carbon Composition 161<.Q �5% 1/4W Carbon Composition

Figure 1. NE/SA617 45MHz Test Circuit (Relays as shown)

396

Signetics RF Communications
Low-voltage high performance mixer FM IF system
C26~

Preliminary specification
NE/SA617
C15

c1
d~�~ I INPUT

::i;:. C27
R19 16k

~~~UT Vee

AUDIO FREQ OUT CHECK

Application Component List

C1 100pF NPO Ceramic
C2 390pF NPO Ceramic
cs 100nF .t.10% Monolithic Ceramic cs 22pF NPO Ceramic
C7 1nF Ceramic
cs 10.0pF NPO Ceramic
C9 100nF .t.10% Monolithic Ceramic C10 1S�F Tantalum (minimum)
C12 2.2�F .t.10% Ceramic C14 100nF .t.10% Monolithic Ceramic
C1S 10pF NPO Ceramic
C17 1OOnF�10% Monolithic Ceramic
C18 100nF .t.10% Monolithic Ceramic C21 100nF .t.10% Monolithic Ceramic

C23 C2S C26 C27 Flt 1 Flt 2 IFT 1
L1
L2
X1 RS R17 R18 R19

100nF .t.10% Monolithic Ceramic 100nF .t.10% Monolithic Ceramic 100nF .t.10% Monolithic Ceramic
2.2�F .t.10% Monolithic Ceramic Ceramic Filter Murata SFG4SSA3 or equiv
Ceramic Filter Murata SFG4S5A3 or equiv 4SSkHz (Ce= 1SOpF) Toko RMC-2A6S97H 147-160nH Coilcrafl UNl-10/142--04J085 0.8�H nominal
Toko 292CNS-T1038Z
44.54SMHz Crystal ICM4712701 Not Used in Application Board (see Note 8)
2.4kn .t.S% 1/4W Carbon Composition 3.3kn .t.S% 1/4W Carbon Composition 16kQ .t.S% 1/4W Carbon Composition

October 22, 1991

Figure 2. NE/SA617 4SMHz Application Circuit 397

Signetics RF Communications
Low-voltage high performance mixer FM IF system

Preliminary specification
NE/SA617

RF GENERATOR 45MHz

NE617 DEMO BOARD .--------~ RSSI AUDIO

Vee (+3)

DC VOLTMETER

DE-EMPHASIS FILTER
C-MESSAGE

SCOPE

HP339A DISTORTION ANALYZER

Figure 3. NE/SA617 Application Circuit Test Set Up
NOTES: 1. C-message: The C-message and de-emphasis filter combination has a peak gain of 1O for accurate measurements. Without the gain, the
measurements may be affected by the noise of the scope and HP339 analyzer. The de-emphasis filter has a fixed -6dB/Octave slope between 300Hz and 3kHz. 2. Ceramic filters: The ceramic filters can be 30kHz SFG455A3s made by Murata which have 30kHz IF bandwidth (they come in blue). or 16kHz CFU455Ds, also made by Murata (they come in black). All of our specifications and testing are done with the more wideband filter. 3. RF generator: Set your RF generator at 45.000MHz, use a 1kHz modulation frequency and a 6kHz deviation if you use 16kHz filters, or BkHz if you use 30kHz filters. 4. Sensitivity: The measured typical sensitivity for 12dB SINAD should be 0.35�V or-116dBm at the RF input. 5. Layout: The layout is very critical in the performance of the receiver. We highly recommend our demo board layout. 6. RSSI: The smallest RSSI voltage (i.e., when no RF input is present and the input is tenminated) is a measure of the quality of the layout and design. If the lowest RSSI voltage is 500mV or higher, it means the receiver is in regenerative mode. In that case, the receiver sensitivity will be worse than expected. 7. Supply bypass and shielding: All of the inductors, the quad tank, and their shield must be grounded. A 10-15�F or higher value tantalum capacitor on the supply line is essential. A low frequency ESR screening test on this capacitor will ensure consistent good sensitivity in production. A 0.1�F bypass capacitor on the supply pin, and grounded near the 44.545MHz oscillator improves sensitivity by 2-3dB. B. R5 can be used to bias the oscillator transistor at a higher current for operation above 45MHz. Recommended value is 22kn, but should not be below 10kQ.

October 22, 1991

398

Signetics RF Communications
Low-voltage high performance mixer FM IF system
mA
Vcc=7V

Preliminary specification
NE/SA617

lcc(mA)

Yee= sv
Vcc=�V Vcc=2.1v

-55

-35

-15

25

45

65

85

105

125

TEMPERATURE (0 C)

Figure 4. Ice vs Temperature

~----------------------------------------------------�------

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e
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-40 -30 -20 -10

10 20

30 40 50 BO

70 BO

Temperature (�C)

Figure 5. Third Order Intercept Point vs Supply Voltage

October 22, 1991

399

Signetics RF Communications
Low-voltage high performance mixer FM IF system

Preliminary specification
NE/SA617

8.00 ~--------------------------~

7.75

I

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7.25

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aw :
":::> 6.50
ii:
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2 6.00
5.75
5.50
5.25

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-40 -30 -20 -10

10 20 30 40 TEMPERATURE (�C)

50 60

70 BO

Figure 6. Mixer Noise Figure vs Supply Voltage

1s.oor--...,.-------,--,.------,---,-------,----~~

17.75

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� - .1 - - - I - I

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10 20

30 40

50 60

70 BO

TEMPERATURE (�C)

Figure 7. Conversion Gain vs Supply Voltage

October 22, 1991

400

Signetics RF Communications
Low-voltage high performance mixer FM IF system

Preliminary specification
NE/SA617

10

- - -:- - - - ~ - - - ~ - - - -1 - - - -:- - - - ; - - - ~ - - - -� - - - - r- - - -

---:- - - -~ - - - ~ ----:- - - -:- - - --- ,' -- - -: -- --~ ---

-10

' - - -�- - - - I- - - - .. - - - -, - - - -

RF-45MHz 1

,

, IF � 1455kHz :

- I- - - - ... - - - -, - - - - ,- - - -

'' '' - - - - - - - - - -� - - - - to - - -

0 500INPUT

_ 3;dORDER 1PRODUCf. __ -:- ___ :- __ _

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-6

4

14

24

34

RF0 INPUT LEVEL (dBm)

Figure 8. Mixer Third Order Intercept and Compression

October 22, 1991

401

Signetics RF Communications
Low-voltage high performance mixer FM IF system

Preliminary specification
NE/SA617

I AUDIO I
~ v~ ~:-~~t~ ---_:_----~ ----_;_ ----~ -----~ ----_: _----~ ----_; _----

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Figure 9. Sensitivity vs RF Level (-40�C)

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I

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. - - - -�- - - - - T - - - - -:- - - - -

- - - - -�- - - - -

-40

--45

-50

-55

-125

-115

-105

-95

-95

-75

-65

-55

--45

-35

-25

RF LEVEL (dBm)

Figure 10. Sensitivity vs RF Level (+25�C)

October 22, 1991

402

Signetics RF Communications
Low-voltage high performance mixer FM IF system

Preliminary specification
NE/SA617

-�-.-��--j-4'�----:-�-�-�� .. . '

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RF LEVEL (dBm)

Figure 11. Sensitivity vs RF Level (Temperature BS"C)

0 ------~------'---

AUDIO

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m

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--

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25

45

65

85

105

125

TEMPERATURE (�C)

Figure 12. Relative Audio Level, Distortion, AM Rejection and Noise va Temperature

October 22, 1991

403

Signetics RF Communications
Low-voltage high performance mixer FM IF system

Preliminary specification
NE/SA617

0.400~

o.ooo+-~-t-~--t~~t-~-t-~-t-~--t~~t-~-t-~-t-~--t~~t-~+-~-+~--t~~t-~+-~-+~-+~~1-----1

-95

-85

-75

-65

-55

-45

-35

-25

-15

-5

IF LEVEL (dBm)

Figure 13. RSSI (455kHz IF @3V)

2.1 2.0

:::::::::::::::::~ ::::::: ::::;::::::: :::::::::::::.~.:.~.~~�--~---

1.9

::::: : ::::: : ::::!::::: : ::::~:::: : : ::::.~~:�~~.�~�f �~~~~�r~~�~~ 1.8

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1.7

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-85

-75

-65

-55

-45

-35

-25

RF LEV.EL (dBm)

Figure 14. RSSI vs RF Level and Temperature� Vee= 3V

October 22, 1991

404

Signetics RF Communications
Low-voltage high performance mixer FM IF system

v
300
250
200
:":;'
a: ~ 150
100
50

Vcc=5V Vcc=3V Vcc=2.7V
Figure 15. Audio Output vs Temperature

Preliminary specification
NE/SA617

October 22, 1991

405

Slgnetlcs RF Communications
FM/IF amplifier/demodulator circuit

Preliminary specification
TDA1576T

FEATURES � Fully balanced 4-stage limiting IF
amplifier � Symmetrical quadrature
demodulator � Field-strengh indication output for
1 mA ammeter � Detune detector for side response
and noise attenuation
� Detune voltage output � Internal muting circuit
� oo and 1800 AF output signals
� Reference voltage output
� Electronic smoothing of the supply voltage

QUICK REFERENCE DATA

SYMBOL

PARAMETER

Vp

supply voltage range (pin 1)

MIN. TYP. MAX. UNIT

7.5 8.5 15

v

Ip

supply current

10

16

23

mA

V;!F

input sensivity (RMS value)

-3 dB before limiting SIN= 26 dB

14

22

35

�V

-

10 -

�V

S/N = 46 dB

-

55

�V

VoAF

AF output signal (RMS value) -

67

mV

THO

total harmonic distortion

with double resonant circuits

-

0.02 -

%

S/N

signal-to-noise ratio (V; > 1 mV)

72

dB

a AM

AM suppression

50

dB

RR

ripple rejection (f = 100 Hz)

- 43

48

dB

115 Tamb

maximum indicator output current -
- operating ambient temperature -30

2

mA

+80 oc

GENERAL DESCRIPTION
The TOA1576T is a monolithic integrated FM-IF amplifier circuit for use in mono and stereo FM-receivers of car radios or home sets.

ORDERING AND PACKAGE INFORMATION

EXTENDED TYPE NUMBER PINS

TDA1576T

20

PACKAGE

PIN POSITION

MATERIAL

mini-pack

plastic

CODE SOT163A

February 1991

406

Signetics RF Communications
FM/IF amplifier/demodulator circuit

Preliminary specification
TDA1576T

2 v (RMS) Rs
Rs

i 0.1 �F

zero adjust

18

17

25 kn

4-STAGE LIMITER/
AMPLIFIER

25 kn

TDA1576T
V2

LEVEL DETECTOR
MUTE AITENUATOR
QUADRATURE DEMODULATOR

detune voltage

videt

Vref
+4.9V 14

0.47 �F
~

13

12

n.c. 11

REFERENCE VOLTAGE

V2 3.7 kn 3.7 kn

2
V-"p--C=f-1 +8.5 V
1on

5

6

33 pF

l FM on

33 pF

560pF

0L=20 f0 =10.7 MHz

8

9

6.8nF
audio outputs

10 n.c.
MEH139

Fig.1 Block diagram and application circuit.

February 1991

407

Signetics RF Communications
FM/IF amplifier/demodulator circuit

Preliminary specification
TDA1576T

PINNING

SYMBOL PIN

Vp

1

Cps

2

IF1

3

RES1

4

FMON

5

RES2

6

IF2

7

VoAFt

8

Vo AF2

9

n.c.

10

n.c.

11

V; det

12

Vo det

13

vref

14

VF

15

VFo

16

V; IF

17

IN2

18

IFLV

19

GND

20

DESCRIPTION
positive supply voltage smoothing capacitor of power supply IF signal to resonant circuit resonant circuit FM-ON, standby switch resonant circuit IF signal to resonant circuit AF output voltage (0� phase) AF output voltage (180� phase) not connected not connected detune detector input for external audio reference detune detector output voltage reference voltage output level output for field-strengh zero adjust for field-strengh FM-IF input signal input 2 of differential IF amplifier IF input level ground (0 V)

PIN CONFIGURATION

IF1 RES1
VoAF1
n.c.

MEH140
TDA1576T

GND IFLV IN2 Vi IF VFo VF Vref Vo det videt n.c.

Fig.2 Pin configuration.

LIMITING VALUES In accordance with the Absolute Maximum System (IEC 134)

SYMBOL

PARAMETER

Vp

supply voltage (pin 1)

V2, 5, 16 voltage on pins 2, 5 and 16

Ptot

total power dissipation

Ts_tg_ Tamb

storage temperature range operating ambient temperature range

MIN. 0 0 0 -55 -30

MAX. UNIT

15

v

Vp

v

450 mW

150 oc

+85

oc

THERMAL RESISTANCE

SYMBOL

PARAMETER

Rthj-a from junction to ambient in free air

MIN.

MAX. 85

UNIT KNJ

February 1991

408

Signetics RF Communications
FM/IF amplifier/demodulator circuit

Preliminary specification
TDA1576T

CHARACTERISTICS
Vp = 8.5 V; fi ZF = 10.7 MHz; Rs= 60 Q; Im= 400 Hz with 61 = �22.5 kHz; 50 �s de-emphasis (CS-9 = 6.8 nF);
Tamb = 25 �C and measurements taken in Fig.1, unless otherwise specified. The demodulator circuit is adjusted at
minimum second harmonic distortion for Vi ZF = 1 mV and a deviation t.f = �75 kHz.

SYMBOL

PARAMETER

Vp

supply voltage range (pin 1)

Ip

supply current

Reference voltage

Vref t>Vref

reference voltage (pin 14)
reference voltage dependence on temperature

114

maximum output current

R14

output resistor (1'.V14 /i'>l14)

IF amplifier

Vi IF R17-18 C17.1s

input sensivity (RMS value, pin 17) input resistance input capacitance

VolF

output signal at pins 3 and 7 {peak-to-peak value)

R3-7

output impedance

Demodulator

R4-6 C4.s Rs. 9 Va,9

input resistance input capacitance output impedance DC offset voltage on output pins
at v 4_6 = o

t.V/t.<p

demodulator efficiency

demodulator efficiency dependent on supply voltage (note 1)

VIV

DC voltage ratio

t.V/l'.T

dependence on temperature

Field-strengh output

V15

output voltage (Fig.4)

s
R1s l'.V/1'.T 115

control steepness output resistance dependence on temperature stand-by operational cut-off current

CONDITIONS V5 =V9 =V13 =0

MIN. 7.5 10

TYP. 8.5 16

MAX. 15 23

UNIT v mA

114 = -1 mA

t>V14 IV14 �t.T

-

short-circuit current 4

114 < 1.2 mA

4.9

-

v

0.3

%/K

6

7.5

mA

60

150

Q

-3 dB before limiting 14

22

35

�V

V; IF= 200 mV (RMS) 10

kn

V; IF= 200 mV (RMS)

5

pF

Z3, 7 = 10 pF // 1Mn 610

680

750

mV

200

250

300

n

20

30

40

kn

-

1

2.5

pF

2.9

3.7

4.5

kn

V5 >3 VorV3_7 = 0

or V13 < 0.3 V

-

t.Vg.911'.<p

-

0

�100 mV

40

mV/ 0

K Vs+V912.V2 t.(V8+V9 / 2�V2)/t.T

0.653
-

6.2 0.667 10-5

0.680
-

mV/ 0 VIV 1/K

Vi IF= 0

0

V; IF= 1 mV (RMS)

1.1

V; IF = 250 mV (RMS) 3.2

Fig.4

-

-

vi IF= l'.V15/(6T�V1s) V5 ~ 3 V; V15 =Oto 5 V -

0.1 1.5 3.6 0.85 150 0.3
-

0.25 1.9 4.1
-
200
10

v v v V/dec n %/K �A

February 1991

409

Signetics RF Communications
FM/IF amplifier/demodulator circuit

Preliminary specification
TDA1576T

SYMBOL

PARAMETER

Zero level adjustment

V1s

internal bias voltage

R15

input resistance

s

control steepness

Detuning detector

112 R12 V13N14

input bias current
input resistance (Fig.5)
output voltage ratio for llcp = cp (pins 3-7) - cp (pins 4-6) -90�; (Fig.6)

llcp = 9.20 (43 kHz), Q = 20

llcp = 3_50 (16 kHz), Q = 20

llcp = 140 (65 kHz), Q = 20

113

maximum output current (Fig.7)

cut-off current

Internal audio attenuation

V13N14 output voltage ratio (Fig.8)

for a= 1 dB

for a= 7.2 dB

fora~ 40 dB

113

input current

Stand-by switch

V5

input voltage for FM-on

input voltage for FM-off

linear range (Fig 9)

15

input current

V5t!lT

temperature dependence

Supply voltage smoothing

V1-2

internal voltage drop

R1.2

internal resistor

CONDITIONS

MIN.

Vi IF= 100 mV; A=llV15/l'N1s

. .
0.87

.

5 V/61 12

6

V1 =V2 =7.5V R13.14 = 1o kn; pins 9 and 12 short-circuit

V9, 12 = 334 mV V9, 12 = 138 mV V9, 12 = 501 mV V13 = 6 V V13 = 2.5 V; V9, 12 = 0

0.45 0.75 0.335 0.4
.

a= attenuation factor V13IV13~0.1

0.11 0.095
.
.

V3, 7 / V3, 7(max) = 0.9 2.4

V19 = 0.3 V

.

V5 =Oto 2 V

.

V5=3.5to15V

FM-on (3.5VsE)

FM-off (5VsE)

.

proportional to

V1 ~VBE

80

5.8

TYP.
260 19
1.0
20 30
0.5 0.8 0.345 0.5 .
0.12 0.1 0.06
.
2.5 2.9 350
. .
7 10
210 8.3

MAX. UNIT

.

mV

.

kn

1.2

VN

100

nA

.

Mn

0.55

VN

0.85

VN

0.355 VN

0.6

mA

-100 nA

0.13 0.105 . -225 nA

.
3
.
-100 1
. .

v v
mV
�A �A
mV/K mV/K

400

mV

10.8 kn

February 1991

410

Signetics RF Communications
FM/IF amplifier/demodulator circuit

Preliminary specification
TDA1576T

OPERATING CHARACTERISTICS
Vp = 8.5 V; fi ZF = 10.7 MHz; Rs= 60 n; fm = 400 Hz with t.f = �22.5 kHz; 50 �s de-emphasis (C8_9 = 6.8 nF);
Tamb = 25 �C and measurements taken in Fig.1, unless otherwise specified. The demodulator circuit is adjusted at
minimum second harmonic distortion with Vi ZF = 1 mV.

SYMBOL

PARAMETER

CONDITIONS

MIN. TVP. MAX. UNIT

IF amplifier and demodulator

Vi IF

input sensivity (RMS value, pin 17) input signal for S/N = 26 dB

-3 dB before AF limiting 14
- f = 250 to 15000 Hz

input signal for S/N = 46 dB

f = 250 to 15000 Hz

Vo AF Vo N
SIN

output signal at (RMS value, pins 8 and 9)

60

noise voltage for Vi IF= o
(RMS value, pins 8 and 9)

Rs= 3000 f = 250 to 15000 Hz

weighted noise voltage according to

DIN 45405

-

signal-to-noise ratio Fig.3 (pin 8 and 9) vi IF = 1 mV (RMS)

-

<XAM

AM suppression

Vi IF= 0.5 to 200 mV FM: 70 Hz, �15 kHz
AM: 1 kHz, m = 30% -

<XFM t.Va, 9

FM rejection for FM-off
AFC shift in relation to minimum second harmonic distortion o.2H DC offset at second harmonic distortion

vi IF= 500 mV; V5 = 3V 80

Vi IF = 0.03 to 500 mV

operating

-

mute or FM-off

-

o.3H

distortion for third harmonic

RR

ripple rejection

Vripple = 200 mV on Vp

f = 100 Hz

43

22

35

�V

10

-

�V

55

�V

67

75

mV

900

�V

2

mV

72

-

dB

50

-

dB

-

-

dB

25

-

mV

0

�100 mV

0

�50

mV

0.65

%

48

dB

Note to the characteristics 1. V5_9 / t.q> = K(Vp - 3 VsE)

February 1991

411

Signetics RF Communications
FM/IF amplifier/demodulator circuit

Preliminary specification
TDA1576T

MEH166
,,.Y
v,. v, f---t--t-+-++H+t.-L_"--+--f-+++i++t--+--t-l--+H-Hft----1--t-+-t+++++---t--+-i-+-t-++t+----+-+--+-t++i-ti
-20 J---+-...,vl-+-vi""~H+<+--+-+--+-++++++-----!-+-+-l-l+<f-++--+--+-+-++t+++---+-+-+-++t++t--+---+-H-1-+++i
(dB) ~
~oi=:+:tl:t:J:H~-l...b-U--l-llil~.l-J--U-Lil!_j___j_-+-+.+U-W--+-+--i-W-+W~~W_j+++W
~ ~Of---t--t-+-++H+l--+--f-+++l++th,,~-+~ --t-l--+H+ft----1--t-+-t+++++---t-N-+-i-+-t-++t+----+-+--+-t++i-ti

10�"

10-.1

10-� V; 17 (rms) (V)

Fig.3 AF output voltage level on pins 8 and 9 as a function of Vi IF at Vp = 8.5 V; f m = 1 kHz; QL = 20 and with de-emphasis. S =signal; N =noise.

MEH143
~.f---t--t-+-++H-++--+-+-+++++H--+--+-++H+l+----1--+-t-++++++--t--t-1-HH-H+--+-+-+-f-t+t-H
(~4t---t--t--t-t-tiiit---t-t-+-++ttti--t--t--t--t-tti-H---1r-i-t-t-H+t+--+--t-t--HH-ttt---t--t-:Fl-tttt1 ~
,...r- 31---t--t-+++t+t+--l--f-+++1-ttt--+--+-t-+f+H-t---t-+-t-Ht+t+--+--J:...l~+t+t--+--+-H-++1-H
2f---t--t-+++Ht+--r-f-++t1+tt--+--t-t-+ftt1-t--~ -\-::;;;olo""f'-Ht++t-+-+-l-+t+ttt--t-t-t-t-ttf-H
i...--1 11---t--t-+++t+t+--t--f-+++1-ttt--h-~.."...'.-t-t++++t--+--+-t-Hf++l-t--+-+-HH+f+t---t-+-t-t-t++H

February 1991

Fig.4 Field-strengh output (115 = 0). 412

Signetics RF Communications
FM/IF amplifier/demodulator circuit

Preliminary specification
TDA1576T

' ' '
R. ,/
/ .........:--
_____\,!'___ _
v�. 12
MEH144
Fig.5 Detuning input impedance.

MEH145

v131 v14

-t \I ~ ~ ~

� I 0.5

~ 'I

-1.2 --0.8 --0.4

0

0.4 0.8 1.2

Vs,12 (V)

Fig.6 Detuning curve;

113 (mA)

MEH146

0.5 1---t----J;~---,.r----v---ihI..--~
11.2 Ji j05

1
1

2

4 V13 5 (V) 6

Fig.7 Detuning output.

MEH147 o.---r-~~IL::---,.......---.~--.----,
a
r-----+--+t~r----+-----+-----1 -101----+----lt--+-----+--+---~
-20
�

-60~

-80L----__,__ __._ _...__ _,__ _,___~

0

0.1

Fig.8 Internal audio attenuation.

February 1991

413

Slgnetlca RF Communications
A complete FM radio on a chip

Appllcatlon note
AN192

Authors: W.H.A.Van Dooremolen M. Hulschmidt
Until now, the almost total integration of an FM radio has been prevented by the need for LC tuned circuits in the RF, IF, local oscillator and demodulator stages. An obvious way to eliminate the coils in the IF and demodulator stages is to reduce the normally used intermediate frequency of 10.7MHz to a frequency that can be tuned by active RC filters, the op amps and resistors of which can be integrated. An IF of zero deems to be ideal because it eliminates spurious signals such as repeat spots and image response, but it would not allow the IF signal to be limited prior to demodulation, resulting in poor signal-to-noise ratio and no AM suppression. With an IF of 70kHz, these problems are overcome and the image frequency occurs about halfway between the desired signal and the center of the adjacent channel. However, the IF image signal must be suppressed and,

in common with conventional FM radios, there is also a need to suppress interstation noise and noise when tuned to a weak signal. Spurious responses above and below the center frequency of the desired station (side tunings), and harmonic distortion in the event of very inaccurate tuning must also be eliminated.
We have now developed a mono FM reception system which is suitable for almost total integration. It uses an active 70kHz IF filter and a unique correlation muting circuit for suppressing spurious signals such as side responses caused by the flanks of the demodulator S-curve. With such a low IF, distortion would occur with the �75kHz IF swing due to received signals with maximum modulation. The maximum IF swing is therefore compressed to �15kHz by controlling the local oscillator in a frequency-locked loop (FLL). The combined

action of the muting circuit and the FLL also suppresses image response.
The new circuit is the TDA7000 which integrates a mono FM radio all the way from the aerial input to the audio output. External to the IC are only one tunable LC circuit for the local oscillator, a few inexpensive ceramic plate capacitors and one resistor. The � TDA7000 dramatically reduces assembly and post-production alignment costs because only the oscillator circuit needs adjustment during manufacture to set the limits of the tuned frequency band. The complete FM radio can be made small enough to fit inside a calculator, cigarette lighter, key-ring lob or even a slim watch. The TDA7000 can also be used as receiver in equipment such as cordless telephones, CB radios, radio-controlled models, paging systems, the sound channel of a TV set or other FM demodulating systems.

A laboratory Model of the TDA7000 In a Complete FM Radio. Alao Shown la the TDA7010T In the SO Package Agelnat a CM Scale.

BRIEF DATA

SYMBOL

DESCRIPTION

Vee

Typical supply voltage

Ice

Typical supply current

IRF

RF input frequency range

VRF-3dB VRF Vo

Sensitivity for -3dB limiting EMF with Zs= 75n, mute disabled Maximum signal input for THO< 10%, .11 = � 75kHz EMF with Zs= 750 Audio output (RMS) with RL = 22kn, '11 = � 22.SkHz

MIN TYP MAX UNITS

4.5

v

8

mA

1.5

110 MHz

1.5

�V

200

mV

75

mV

Using the TDA7000 results in significant improvements for all classes of FM radio. For simpler portables, the small size, lack-0f IF coils, easy assembly and low power consumption are not the only attractive features. The unique correlation muting system and the FLL make it very easy to tune, even when using a tiny tuning knob. For

higher-performance portables and clock radios, variable-capacitance diode tuning and station presetting facilities are often required. These are easily provided with the TOA7000 because there are no variable tuned circuits in the RF signal path. Only the local oscillator needs to be tuned, so tracking and distortion problems are eliminated.

The TDA7000 is available in either an 18-lead plastic DIP package (TDA7000), or in a 16-pin SO package (TDA7010T). Future developments will Include reducing the present supply voltage (4.5V typ.), and the introduction of FM stereo and AM/FM versions.

December 1991

414

Signetics RF Communications
A complete FM radio on a chip

Application note
AN192

VP-~~-.~~~~~~~~~.-~~~~~~~~~~+-~.-~~~~~-+-~-.-~~~~~-.~~~~~ (+4.SV)

r---

C15 100nF

130nH

18

15 14

1.4V

C12 13 12

C11

C10

11

10

(1)

I I

J �>!!!!E~!QR_

_

M3 _

I

mute control

MUTE

If FILTER

NOISE SOURCE
3 (1)
C3

c;r 3.3nF

C8 180pF

a.I. output
NOTES: 1. These pins are not used In the SO package version (TDA7010T) AP - All-Pass filter. 2. L2 ls printed on the experimental PCB (Figure 12).
L1 � Toko MC108 No. 514 HNE 150013813. C20 � Toko No.2A-158T-R01.
Figure 1. The TDA7000 as a Variable Capacitor-Tuned FM Broadcast Receiver

December 1991

415

Signetics RF Communications
A complete FM radio on a chip

Application note
AN192

CIRCUIT DESCRIPTION As shown in Figure 1, the TOA7000 consists of a local oscillator and a mixer, a two-stage active IF filter followed by an IF limiter/amplifier, a quadrature FM demodulator, and an audio muting circuit controlled by an IF waveform correlator. The conversion gain of the mixer, together with the high gain of the IF limiter/amplifier, provides AVC action and effective suppression of AM signals. The RF input to the TDA7000 for-3dB limiting is 1.5�V. In a conventional portable radio, limiting at such a low RF input level would cause instability because higher harmonics of the clipped IF signal would be radiated to the aerial. With the low IF used with the TDA7000, the radiation is negligible.
To prevent distortion with the low IF used with the TDA7000, it is necessary to restrict the IF deviation due to heavily modulated RF signals to �15kHz. This is achieved with a frequency-locked loop (FLL) in which the output from the FM demodulator shifts the local oscillator frequency in inverse proportion to the IF deviation due to modulation.
Active IF Filter
The first section of the IF filter (AF1A) is a second-order low-pass Sallen-Key circuit with its cut-off frequency determined by internal 2.21<.n resistors and external capacitors C7 and C8� The second section (AF1 BJ consists of a first-order bandpass filter with the lower limit of the passband determined by an internal 4.7k.n resistor and external capacitor C11 . The upper limit of the passband is determined by an internal 4.71<.n resistor and external capacitor C10. The final section of the IF filter consists of a first-order low-pass network comprising an internal 12kn resistor and external capacitor C12. The overall IF filter therefore consists of a fourth-order low-pass section and a first-order high-pass section. Design equations for the filter are given in Figure 2. Figure 3 shows the measured response for the filter.
FM Demodulator
The quadrature FM demodulator M2 converts the IF variations due to modulation into an audio frequency voltage. It has a conversion gain of --,'3.6V/MHz and requires phase quadrature inputs from the IF limiter/amplifier. As shown in Figure 4, the 90� phase shift is provided by an active all-pass filter which has about unity gain at all frequencies but can provide a variable phase shift, dependent on the value of external capacitor C17.

For C7 � 3.3nF, Ce� 180pF;O� 2.1and1o�94kHz

Band- circuit

Aap =

1

l+J�C10R2

P"'/I.P =--1- - ml/HP =--1- -

2arR2C10

2:1R2C11

(1 Asp =::::. . ( I )

II.P)

1+jfHP 1-jf +1

For C10 � 330pF, C11 � 3.3nF, ILP � 103kHz, IHP � 10.3kHz

Low.P- circuit

Af.P =

1

1 +J� C12R3

fut

II.P

�

-2 o- r C1- 12

R3

Au=--kj �I.P

For C12� 150pF, fLP � BB.4kHz

Figure 2. IF Filter of the TDA7000

December 1991

416

Signetics RF Communications
A complete FM radio on a chip

Application note
AN192

IF Swing Compression With the FLL
With a nominal IF as low as 70kHz, severe harmonic distortion of the audio output would occur with an IF deviation of �75kHz due to full modulation of a received FM broadcast signal. The FLL of the TDA7000 is therefore used to compress the IF swing by using the audio output from the FM demodulator to shift the local oscillator frequency in opposition to the IF deviation. The principle is illustrated in Figure 5, which shows how an IF deviation of 75kHz is compressed to about 15kHz. The THD is thus limited to 0. 7% with �22.SkHz modulation, and to 2.3% with �75kHz modulation.
Correlation Muting System With Open FLL
A well-known difference between FM and AM is that, for FM, each station is received in at least three tuning positions. Figure 6 shows the frequency spectrum of the output from the demodulator of a typical portable FM radio receiving an RF carrier frequency-modulated with a tone of constant frequency and amplitude. In addition to the audio response at the correct tuning point in the center of Figure 6, there are two side responses due to the flanks of the demodulator S-curve. Because the flanks of the S-curve are non-linear, the side responses have increased harmonic distortion. In Figure 6, the frequency and intensity of the side responses are functions of the signal strength, and they are separated from the correct tuning point by amplitude minima. However, in practice, the amplitude minima are not well defined because the modulation frequency and index are not constant and, moreover, the side response of adjacent channels often overlap.
High performance FM radios incorporate squelch systems such as signal strength-dependent muting and tuning deviation-dependent muting to suppress side responses. They also have a tuning meter to facilitate correct tuning. Although the TDA7000 is mainly intended for use in portables and clock radios, it incorporates a very effective new correlation muting system which suppresses interstation noise and spurious responses due to detuning to the flanks of the demodulator S-curve. The muting system is controlled by a circuit which determines the correlation between the waveform of the IF signal and an inverted version of it which is delayed (phase-shifted) by half the period of the nominal IF (180�). A noise generator works in conjunction with the muting system to give an audible indication

+10 VofV;
rT (dB) -10 _,,.,
-30
-40
-60
-60
-70 0

~
~ h. ~ " ' .........__

100

200

300

400

500

f(kHz)

Figure 3. Measured Response of the IF Filter

Vjf

With R2�0 �1- -2tan-1 roR1C17

=- for ft = -900, C17 1- = ll7pF

for fL ... 70kHz

�'RI

To improve the performance of the all�pass filter with the amplitude�limited IF waveform, R2 has been added. Since this influences the phase angle by 45%, i.e., to 330pF for ftF ... 70kHz.

Figure 4. FM Demodulator Phase Shift Circuit (All-Pass Filter)

December 1991

417

Signetics RF Communications
A complete FM radio on a chip

Application note
AN192

High performance FM radios incorporate squelch systems such as signal strength-dependent muting and tuning deviation-dependent muting to suppress side responses. They also have a tuning meter to facilitate correct tuning. Although the TDA7000 is mainly intended for use in portables and clock radios, it incorporates a very effective new correlation muting system which suppresses interstation noise and spurious responses due to detuning to the flanks of the demodulator S-Curve. The muting system is controlled by a circuit which determines the correlation between the waveform of the IF signal and an inverted version of it which is delayed (phase-shifted) by half the period of the nominal IF (180�). A noise generator works in conjunction with the muting system to give an audible indication of incorrect tuning.
Figure 7 illustrates the function of the muting system. Signal IF' is derived by delaying the IF signal by half the period of the nominal IF and inverting it With correct tuning as shown in Figure 7a, the waveforms of the two signals are identical, resulting in large correlation. In this situation, the audio signal is not muted. With detuning as shown in Figure 7b, signal IF' is phase-shifted with respect to the IF signal. The correlation between the two waveforms is therefore small and the audio output is muted. Figure
a 7c shows that, because of the low of the IF
filter, noise causes considerable fluctuations of the period of the IF signal waveform. There is then small correlation between the two waveforms and the audio is muted. The correlation muting system thus suppresses noise and side responses due to detuning to the flanks of the demodulator S-curve. Since the mute threshold is much lower than that obtained with most other currently-used muting systems, this muting system is ideal for portable radios which must often receive signals with a level only slightly above the input noise.
As shown in Figure 8, the correlation muling circuit consists of all-pass filter AP2 connected in series with FM demodulator all-pass filter AP1 and adjusted by an external capacitor to provide a total phase shift of 180�. The output from AP2 is applied to mixer M3 which determines the correlation between the undelayed limited IF signal at one of its inputs and the delayed and inverted version of it at its other input. The output from mixer M3 controls a muting circuit which feeds the demodulated audio signal to the

fn 56nH

MIXER AND

iw

l.F. AMPLIFIER

lose
VOLTAGECONTROLLED
LOCALOSC. Cdlodo (SLOPE S �
-1.14pFIV)

F.M.

DEMDDULAlOR

v

(CONVERSION

GAIND�

-3.BV/MHz)

C17 J330pF

LOOP AMPLIFIER

AL�-1.06

Co - CEXT + CsTRAY + Co100E with open loop - 49pF at fo - 96MHz

F - factor /I � At Bio 2 Co
Open-loop oonverslon gain. D. -3.SVIMHz

C/osed-/oap

convetSlon gain

�

_D_
1 + c:tJ

�

0.66V/MHz for

10

�

96MHz

Modulation corrplfl68/on ladOr k � open-/oap gain � 3.6V/MHz � 5 ciossd-/oap gain 0.684V/MHz
A lose - A IR~1-~)
A':F AltF�

for ""RF� 75kHz. Mose� OOlrHz, AlfF � 151rHz

Af1�B5-70� 15kHz

fosc�fo

rose fn

f'n

I -~ Afo~ sc- � o- okH- z 1

tit� 70kHz

II,,

Afn�75kHz

95.9

95.93

95.99

96

In (kHz)

96.075 96.1

Figure 5. IF Swing Compression with the FLL

output when the correlation is high, or feeds the output from a noise source to the output to give an audible indication of incorrect tuning when the correlation is low. The switching of the muling circuit is progressive (soft muling) to prevent the generation of annoying audio transients. The output from mixer M3 is available externally at Pin 1 and can also used to drive a detuning indicator.
Figure 9 shows that there are two regions where the demodulated audio signal is fed to the output because the muting is inactive. One region is centered on the correct tuning

point fL. The other is centered on the image frequency-fl. The image response is therefore not suppressed by the muting system when the frequency-locked loop is open. When the loop is closed, the time constant of the muting system, which is determined by external capacitor C1, prevents the image response being passed to the audio output. This is described under the next heading.

December 1991

418

Signetics RF Communications
A complete FM radio on a chip

200kHz
VaI 11------~-v_"_-_'�_m_v_
Vaft--1-~-1m_v

Vaf t-l-----~---1oo_�_v_

Vaf

1

-

----~---1-0�_v_
:

Vaf t-1------~----3-�V

i-1------~~��:ll�� Vaf

-.;����;:/��;;;li:C::��Z�����>----1._s�_v

. It-----~

I

I

I enlarged i~

I

'�.I

~~

Figure 6. Audio Signal of a Typical Portable Radio as a Function of Tuned Frequency With RF Input as a Parameter.
The Modulation and Amplitude are Both Constant.

Application note
AN192

December 1991

419

Signetics RF Communications
A complete FM radio on a chip

Application note
AN192

Correlation Muting System With Closed FLL
The closed-loop response of the FLL is shown in Figure 10, in which the point of origin is the nominal IF (fRrfosc=fL ). With correct tuning, the muting is inactive and the audio signal is fed to the output. Spurious responses due to the flanks of the demodulator S-curve which occur outside the IF band -f2 to f2 are suppressed because the muting is active. Fast transients of the audio signal due to locking of the loop (A and B), and to loss of lock (C and D) are suppressed in two ways.
Lock and loss of lock transients B and D occur when the IF is greater than f2 and are therefore suppressed because the muting is active. The situation is different during loss of lock transient C because the muting is only active for the last part of the transient. To completely suppress this transient, capacitor C1 in Figure 1 holds the muting control line positive (muting active) during the short interval while the IF traverses from -f1 to -f2. The same applies for lock transient A during the short interval while the IF traverses from -f2 to -f1. Since the image response occurs halfway between -f1 and -f2, it is also suppressed.
Figure 11 shows the audio output from the TDA7000 radio as a function of tuned frequency with aerial signal level as a parameter. Compared with the similar diagram for a typical conventional portable radio (Figure 6), there are three important improvements:
1. There are no side responses due to the flanks of the demodulator S-curve. This is due to the action of the correlation muting system (soft mute) which combines the function of a detuning-dependent muting system with that of a signal strength-dependent muting system.
2. The correct tuning frequency band is wide, even with weak aerial signals. This is due to the AFC action of the FLL which reduces a large variation of aerial input frequency (equivalent to detuning) to a small variation of the IF. There is no audio distortion when the radio is slightly detuned.
3. Although the soft muting system remains operative with low level aerial signals, there is no degradation of the audio signal under these conditions. This is due to the high gain of the IF limiter/amplifier which provides -3dB limiting of the IF signal with an aerial input level of 1.5�V. However, the soft muting action does reduce the audio output level with low level aerial signals.
December 1991

co~~ion l.F. .JLJL.r

with

(a)

. J L J L . r correct
tuning

\.F.'

n . I U l _ small

1.F.

correlation

(b)

_ _ f U L J l _ due to
detuning l.F.'

J L J l _ J l.F.
very small

correlation

(c)

due to noise

~ l.F.'

Figure 7. Function of the Correlation Muting System

~-------
I C18

for #2

-

-1eo0

c18

�

- 1., R1

for fit � 70kHz, C1e � 227pF

Figure 8, Correlator of the TDA7000

420

Signetics RF Communications
A complete FM radio on a chip
v F~u~~~W1;r-~--~"--+---'...,_--,.---- (a)
frt- lose
(b)

(d)
fn- lose
(�)
Figure 9. Operation of the Correlation Muting System with Open�Loop FLL
Mose
�AVQ incorrect side tuning suppresseO\
D
capture range holdln ran e
CJ - area of correct tuning
Figure 10. Closed-Loop Response of the FLL

December 1991

421

Application note
AN192

Signetics RF Communications
A complete FM radio on a chip

200kHz
r--"*I

Vat !-------

1mV

Application note
AN192
C1e and C21 - Local oscillator tuning capacitors. Their values depend on the required tuning range and on the value of tuning capacitor C20. C22, C23, L1, L2- The values given are for an RF bandpass filter with Q = 4 for the European and USA domestic FM broadcast band (87.5MHz to 108MHz). For reception of the Japanese FM broadcast band (76MHz to 91 MHz), L1 must be increased to 78nH and ~must be increased to 150nH. If stopband attenuation for high level AM or TV signals is not required, L2 and C22 can be omitted and C23 changed to 220pF. R2 - The load for the audio output current source. It determines the audio output level, but its value must not exceed 22kn for Vee = 4.5V, or 47k'1 for Vee= 9V.

Vatl._____--3j1V

tuned frequency
Figure 11. Audio Slgnal of the TDA7000 aa a Function of the Tuned Frequency with RF Input u a Parameter

RECEIVER CIRCUITS
Circuits With varlable Capacitor Tuning
The circuit diagram of the complete mono FM radio is given in Figure 1. An experimental printed-wiring board layout is given in Figure 12. Special attention has been paid to supply lines and the positioning of large-signal decoupling capacitors.
The functions of the peripheral components of Figure 1 not already described are as follows:
C1- Determines the time constant required to ensure muting of audio transients due to the operation of the FLL.
C2- Together with R2determines the time constant for audio de-emphasis (e.g., R2C2 = 40�s.
03 - The output level from the noise generator during muting increases with increasing value of C3. If silent mute is required, C3 can be omitted.

C4- Capacitor for the FLL filter. It eliminates IF harmonics at the output of the FM demodulator. It also determines the time constant for locking the FLL and influences the frequency response.
C5 - Supply decoupling capacitor which must be connected as close as possible to Pin 5 of the TDA7000.
C7 to C12. C11 and C18 - Filter and demodulator capacitors. The values shown are for an IF of 70kHz. For other �intermediate frequencies, the values of these capacitors must be changed in inverse proportion to the IF change.
C14 - Decouples the reverse RF input. It must be connected to the common return via a good quality short connection to ensure a low-impedance path. Inductive or capacitive coupling between C14 and the local oscillator circuit or IF output components must be avoided.
C15 - Decouples the DC feedback for IF limiter/amplifier LA1.

December 1991

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Signetics RF Communications
A complete FM radio on a chip

Application note
AN192

Vo
(dB)
(75mV) o
~.-;1
t;ll.-1 1
-20
1----\-(t-.
f-----1 1
~ N

-ea
10-6

10-5

10-4

s+ 1N
NOISE 10-3

THD (%)
10 THD
El
10-1 Vr1(e.m.f.)

NOTES: The curvee numbered 1 were meaeured with the muting eyetem active. The curves numbered 2 were measured with the muting ayetem disabled by Injecting about 20�A Into Pin 1 of the TDA7CK>O. The Input frequency was 96MHz modulated with 1kHz with a deviation of �75kHz for the distortion curve.

Figure 12. Audio Output as a Function of Input EMF

PERFORMANCE OF THE CIRCUIT
Vcc=4.5V, TA=25�C fRF=96MHz, VRF=0.2mV EMF from a 75'1 source, modulated with t.1=�22.SkHz, fM=1kHz. Noise voltage measured unweighted over the bandwidth 300Hz to 20kHz, unless otherwise specified.

SYMBOL

PARAMETER

TYP

MAX

EMF EMF EMF

<80>Sensitivity {EMF voltage)for -3dB limiting: muting disabled for -3dB muting for {S+N)iN=26dB

1.5 6
5.5

EMF

<80>Signal handling {EMF voltage) for THD<10%; ll.f=�75kHz

200

(S+N)/N

Signal-to-noise ratio {see Figure 13)

60

THD THD

<80>Total harmonic distortion {see Figure 13) at ll.f=�22.5kHz at II.I=�75kHz

AMS

<SO>AM suppression {ratio of the AM output signalreferred to the FM output signal) FM signal: fm=1 kHz;Af=�75kHz AM signal: 1m=1kHz; m=80%

RR

10

Vs-sRMS

250

II.lose

80Variation of oscillator frequencywith supply voltage {ll.Vcc=1V)

60

S+300

45

S-300

35

11.fRF B

AFC range SOAudio bandwidth at 11.Vo=3dBmeasured with pre-emphasis {t=50�s)

�300 10

VocRMS)

BOAF output voltage {RMS value)at RL=22kQ

75

RL

22

RL

47

December 1991

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Signetics RF Communications
A complete FM radio on a chip

Application note
AN192

TDA7000 (Figure 1)
BBB09 ' - - - - - - - PIN 6
o v - - < 1 0 - - - - - - - - - - - - - - - - - - - - - - PIN 16 Figure 13. Variable-Capacitance Diode Tuning for the Local Oscillator. Additional
Meaaurea Must be Taken to Ensure Temperature Stablllty.

Circuit With Variable-Capacitance Diode Tuning
Since it is only necessary to tune the local oscillator coil, it is very simple to modify the circuit of Figure 1 for variable-capacitance diode tuning. The modifications are shown in Figure 13. A circuit board layout for the modified receiver and a photograph of a complete laboratory model are shown in Figure 14.
Narrow-Band FM Receiver
The TOA7000 can also be used for reception of narrowband FM signals. In this case, the local oscillator is crystal-controlled (as shown in Figure 15) and there is therefore hardly any compression of the IF swing by the FLL. The deviation of the transmitted carrier frequency due to modulation must therefore be limited to prevent severe distortion ol the demodulated audio signal.

a.I.output ov
Figure 14. Circuit Board Layout and Complete Model of a TDA7000 Radio With Variable-Capacitance Diode Tuning

December 1991

424

Sig:ietics RF Communications
A complete FM radio on a chip

Application note
AN192

+4.5V

C18

C17

4.7nF

r.f.lnput

C23 220pF

C12 3.3nF

18

17

C1 150nF

16

15

14

13

TOA7000 (seaFlg.1)

8

4

C2 2.7nF

C4 4.7nF

C5 1oon
I

12

11

10

2 C7
100nF
CB 2.2nF

a.f.output

Figure 15. A Narrowband FM Receiver With a Crystal-Controlled Local Oaclllator

+2or-------------------.
20 log !!. Vo +10
(dB)

The component values in Figure 16 result in an IF of 4.SkHz and an IF bandwidth of 5kHz (Figure 16). If the IF is multiplied by N, the
values of capacitors C17 and C18 in the all-pass filters and the values of filter
capacitors C7, Ca, C10. C11, and C12 must be multiplied by 1/N. For improved IF selectivity to achieve greater adjacent channel attenuation, second-order networks can be used in place of C10 and C11 �

In this circuit the detuning noise generator is not used. Since the circuit is mainly for reception of audio signals, the audio output must be passed through a low-pass Chebyshev filter to suppress IF harmonics.

Figure 16. IF Selectlvlty for the Narrowband FM Receiver

AUDIO AMPLIFIER AND DETUNING INDICATOR CIRCUITS
Audio output stages suitable for use with the TDA7000 are shown in Figures 17 and 18. Figure 19 shows how the muting signal can be used to operate an LED to give an indication of detuning.

December 1991

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Signetics RF Communications
A complete FM radio on a chip

+3V
220kn

65'1 earpiece

fromP1n2 TOA7000
ov

1) 22kn

BC550B
Po. OAmW, d -10% quiescent current - 4mA

Figure 17. A 0.4mW Transistor Audio Output Stage Without Volume Control for Driving an Earpiece

+4.5V ----...---+------------~

to Pin 5 --'VVlr--' TDA7000

220�F

'%"}.j~ _ ___,,_____ 1)
22kn

Application note
AN192
4.7n

NOTE: 1. These components replace C2 and R2 In Figure 1. Po� 250mW, d. 10% quiescent current- BmA.

Figure 18. An Integrated 250mW Audio Output Stage

+3V=1 from Pin 1

470kn

of the

BC558

TOA7000 (Flg.1)

/,i-

ACKNOWLEDGEMENTS The authors wish to acknowledge the information provided by D. Kasperkovitz and H.v. Rump! for incorporation in this article.

REFERENCE NOW, W. and SIEWERT, I., "Integrated circuitsfor hi-fi radios and tuners', Electronic Componentsand Applications, Vol. 4, No. 1, November 1981,pp. 11to27.

OV
Figure 19. A Detuning Indicator Driven by the Mute Signal From the TDA7000

December 1991

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Slgnetlca RF Communications
TOA7000 for narrowband FM reception

Application note
AN193

Author: W.V. Dooremolen
INTRODUCTION
Today's cordless telephone sets make use of duplex communication with carrier frequencies of about 1.7MHz and 49MHz.
� In the base unit incoming telephone information is frequency-modulated on a 1. 7MHz carrier.
� This 1.7MHz signal is radiated via the AC mains line of the base unit.
� The remote unit receives this signal via a ferrite bar antenna.
� The remote unit transmits the call signals and speech information from the user at 49MHz via a telescopic antenna.
� The base unit receives this 49MHz FM-modulated signal via a telescopic aerial.
Today's Remote Unit Receivers
In cordless telephone sets, a normal superheterodyne receiver is used for the 1.7MHz handset. The suppression of the adjacent channel at, e.g., 30kHz, must be 50dB, and the bandwidth of the channel must be 6-1 OkHz for good reception. Therefore, an IF frequency of 455kHz is chosen. Since at this frequency there are ceramic filters with a bandwidth of9kHz (AM filters), the 1.7MHz is mixed down to 455kHz with an oscillator frequency of 2.155MHz. Now there is an image reception at 2.61 MHz. To suppress this image sufficienUy, there must be at least two RF filter sections at the input of the receiver.
Thi! ceramic IF filter with its subharmonics is bad for far-off selectivity, so there must be an extra LC filter added between the mixer output and the ceramic filter.
After the selectivity there is a hard limiter for AGC function and suppression of AM.
Next, there is an FM detector which must be accurate because it must detect a swing of �2.5kHz at 455kHz; therefore, it must be tuned.
Figure 1 shows the block diagram which fulfills this principal. The total number of alignment points of this receiver is then 5:

Z.155Mllz
Figure 1. Remot�unlt Receiver: 1��7MHz

2 RF filters 1 Oscillator 1 IFfilter 1 FM detector
5Alignments
A Remote Unit Receiver With TDA7000
The remote unit receiver (see Figure 2) has as its main component the IC TDA7000, which contains mixer, oscillator, IF amplifiers, a demodulator, and squelch functions.
To avoid expensive filtering (and expensive filter-adjustments) in RF, IF, and demodulator stages, the TDA7000 mixes the incoming signal to such a low IF frequency that filtering can be realized by active RC filters, in which the active part and the Rs are integrated.
To select the inooming frequency, only one tuned circuit is necessary: the oscillator tank circuit. The frequency of this circuit can be set by a crystal.

10kHz from the required frequency (see Figure 3).
An IF frequency of 5kHz has been chosen because:
� this frequency is so low, there will be no neighboring channel reception at the image frequency.
� this frequency is not so low that at maximum deviation (maximum modulation) distortion could occur (folding distortion, caused by the higher-order bessel functions)
� this frequency gives the opportunity to obtain the required neighboring channel suppression with minimum oomponents in the IF selectivity.

IMAGE RECEPTION
For today's concept, a number of expensive components are necessary to suppress the image sufficienUy. The suppression of the image is very important because the signal at the image can be much larger than the wanted signal and there is no correlation between the image and the wanted signal.
In a concept with 455kHz IF frequency, the 1.7MHz receiver has image reception at 2.155MHz. In the TDA7000 receiver, the IF frequency is set at 5kHz. Then the 1.7MHz receiver (with 1.695MHz oscillator frequency) has image reception at 1.69MHz, which is at

December 1991

427

Signetics RF Communications
TDA7000 for narrowband FM reception

Application specification
AN193

+Vs
p!

1
1DA7000

NE6535
[>

NE5535
[>
A.F. FILTER

'=' TALK
0 STAND BY

17

Flgure2.

CIRCUIT DESCRIPTION (SEE FIGURE 2) When a remote unit is at "power-on" in the "standby" position, it is ready to receive a "bell signal". A bell signal coming through the telephone line will set the base unit in the mode of transmitting a 1. 7MHz signal, modulated with, e.g., 0.75kHz with �3kHz deviation.
The ferrite antenna of the remote unit receives this signal and feeds it to the mixer, where it is converted into a 5kHz IF signal.
Before the RF signal enters the mixer (at Pins 13 and 14) it passes RF selectivity, taking care of good suppression of unwanted signals from, e.g., TV or radio broadcast frequencies. The IF signal from the mixer output passes IF selectivity (Pins 7 to 12) and the IF amplifiernimiter (Pin 15), from which the output is supplied to a quadrature demodulator (Pin 17). Due to the low IF frequency, cheap capacitors can be used for both IF selectivity and the phase shift for the quadrature demodulator.
The AF output of the demodulator (Pin 4) is fed to the AF filter and AF amplifier NE5535.
The RF Input Circuit
As the image reception is an in-channel problem, solved by the choice of IF frequency and IF selectivity, the RF input filter is only required for stopband selectivity (a far-off

selectivity to suppress unwanted large signals from, e.g., radio broadcast transmitters).
In a remote unit receiver at 1.7MHz, this filter is at the ferrite rod. Figure 4 shows the bandpass behavior of such a filter at 1.7MHz.
The Mixer
The mixer conversion gain depends on the level of the oscillator voltage as shown in Figure 5, so the required oscillator voltage at Pin 6 is 200mVRMS�
The Oscillator
To obtain the required frequency stability in a

cordless telephone set, where adjacent channels are at 20 or 30kHz, crystal oscillators are commonly used.
The crystal oscillator circuits usable for this kind of application always need an LC-bJned resonant circuit to suppress the other modes of the crystal. In this type of oscillator (see Figure 6 as an example) the crystal is in the feedback line of the oscillator amplifier. Integration of such an amplifier should give a 2-pin oscillator.
The TDA7000 contains a 1-pin oscillator. An amplifier with current output develops a voltage across the load impedance. Voltage feedback is internal to the IC.

,--

/

/ /

+
I

I

I

-5kHzlDIV

1osc Figures.

December 1991

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Signetics RF Communications
TDA7000 for narrowband FM reception

Application specification
AN193

UL11 1~--40 I1~ ' 950

-10 -15

I I
20:1

' 14L __

L1 :2.3mH

-25

-35

1.0

1.2

1.4

1.6 1.7 1.8

2.0

2.2

lo(MHz)

Figure 4.

~
t
1

TDA,l ATfiC = 1]MHz -
~
~ rs::
'

0 ~~-

-

~Vosc(m- V) -

-

-

Figure 5. Relative Mixer Conversion Gain

~ ~

~~~---loo--~~~
a
Figure 6.

To obtain a crystal oscillator with the TDA7000 1-pin concept, a parallel circuit configuration as shown in Figure 7 has to be used.
Explanation of this circuit: 1. Without the parallel resistor RP-
Figure 8 shows the relevant part of the equivalent circuit. There are three frequencies where the circuit is in resonance (see Figure 9, and the frequency response for "impedance" and "phase", shown in Figure 10). The real part of the highest possible oscillation frequency dominates, and, as there is also a zero-crossing of the imaginary part,

this highest frequency will be the oscillator frequency. However, this frequency (!PAR) is not crystal-controlled; it is the LC oscillation, in which the parasitic capacitance of the crystal contributes.

2. With parallel resistor RPThe frequency response (in "amplitude" and "phase"') of the oscillator circuit of Figure 7 with RP is given in Figure 11. As the resistor value of RP is large related to the value of the crystal series resistance R1 or R3, the influence of RP at crystal resonances is negligible. So, at crystal resonance (see Figure 9b), R3 causes a circuit damping

(1 C:!) R = _W2.2._. R3 � C12 + R3

+

2

C1

However, at the higher LC-oscillation
frequency !PAR (see Figure 9c), Rp reduces
the circuit impedance Ro to

Ro� RoAMPING = Re
Ro + RoAMPING
where
~ c, RoAMPING = � Rp� 2 + Rp ( 1

Thus a damping resistor parallel to the crystal (Figure 7) damps the parasitic LC oscillation at the highest frequency. (Moreover. the imaginary part of the impedance at this frequency shows incorrect zero-crossing.)
Taking care that Rp > RsERIES. the resistor is too large to have influence on the crystal resonances. Then with the impedance Re at the parasitic resonance lower than R at crystal resonance, oscillation will only take place at the required crystal frequency, where impedance is maximum and phase is correct (in this example, at third-overtone resonance).
Remarks: 1. It is advised to avoid inductive or
capacitive coupling of the oscillator tank circuit with the RF input circuit by careful positioning of the components for these circuits and by avoiding common supply or ground connections.
The IF Amplifier
Selectivity Normal selectivity in the TDA7000 is a fourth-order low-pass and a first-order high-pass filter. This selectivity can be split up in a Sallen and Key section (Pins 7, 8, 9), a

December 1991

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Signetics RF Communications
TDA7000 for narrowband FM reception

Application specification
AN193

bandpass filter (Pins 10, 11 ), and a first-order low-pass filter (Pin 12).
Some possibilities for obtaining required selectivity are given:
1. In the basic application circuit, Figure 12a, the total filter has a bandwidth of 7kHz and gives a selectivity at 25kHz IF frequency of 42dB. In this filter the lower limit of the passband is determined by the value of C4 at Pin 11, where C3 at Pin 10 determines the upper limit of the bandpass filter section.
2. To obtain a higher selectivity, there is the possibility of adding a coil in series with the capacitor between Pin 11 and ground. The so-obtained fifth-order filter has a selectivity at 25kHz of 57dB (see Figure 12b).
3. If this selectivity is still too small, there is a possibility of increasing the 25kHz selectivity to S5dB by adding a coil in series with the capacitor at Pin 11 to ground. In this application, where at 5kHz IF frequency an adjacent channel at -30kHz will cause a (30-5)=25kHz interfering IF frequency, the pole of the last-mentioned LC filter (trap function) is at 25kHz (see Figure 12c).

modulation. DC feedback of the limiter is decoupled at Pin 15.
The Signal Demodulator
The signal demodulator is a quadrature demodulator driven by the IF signal from the limiter and by a phase-shifted IF signal derived from an all-pass filter (see Figure 14).
This filter has a capacitor connected at Pin 17 which fixes the IF frequency. The IF frequency is where a 90 degree phase shift takes care of the center position in the demodulator output characteristics (see Figure 15, showing the demodulator output (at Pin 4) as a function of the frequency, at 1mV input signal).
The AF Output Stage
The signal demodulator output is available at Pin 4, where a capacitor, C, serves for elimination of IF harmonics. This capacitor also influences the audio frequency response. The output from this stage, available at Pin 2, has an audio frequency response as shown in Figure 16, curve a. The output at Pin 2 can be muted.

such a filter is given in Figure 16, Curve b, for an active second-order filter with an additional passive RC filter.
Output Amplification
The dimensioning of the operational amplifier of Figure 17a results in no amplification of the AF signal. In case amplification of this op amp is required, a feedback resistor and an RC filter at the reverse input can be added (see Figure 17b, for about 30dB amplification).
I
c:::J
Figure Ba.

For cordless telephone sets with channels at 15kHz distance, the filter characteristics are optimum as shown in the curves in Figure 13, in which case the filters are dimensioned for 5kHz IF bandwidth (instead of 7kHz). So for this narrow channel spacing application, the required selectivity is obtained by reducing the IF bandwidth; this at the cost of up to 2dB loss in sensitivity. NOTE:
At 5kHz IF frequency adjacent channels at +15kHz give
undesired IF frequencies of 20kHz and 10kHz, respectlvely.
Limiter/Amplifier The high gain of the limiter/amplifier provides AVC action and effective suppression of AM

Rp
Figure?.
Output Signal Filtering
Output signal filtering is required to suppress the IF harmonics and interference products of these harmonics with the higher-order bessel components of the modulation. Active filtering with operational amplifiers has been used (see Figure 17). The frequency response of

Figure Sb.

f:� Ro C2
Rp

[~ Rp

Ro
02

le,

{~

Ro

a.At f1

b.Atf3 Fl ure9.

c. At fPAR

December 1991

430

Signetics RF Communications
TOA7000 for narrowband FM reception

Application specification
AN193

MEASUREMENTS
For sensitivity, signal handling, and noise behavior information in a standard application as shown in Figure 18, the signal and noise output as a function of input signal has been measured at 1.7MHz, at 400Hz modulation where the deviation is �2.5kHz (see Figure 19). As a result the S+N/N ratio is as given in Figure 19, Curve 3.
APPENDIX
RF-Tuned Input Circuit at 46MHz
In Figure 20 a filter is given which matches at 46MHz a 750 aerial to the input of the TDA7000. Extra suppression of RF frequencies outside the passband has been obtained by a trap function.
RF Pre-Stage at 46MHz
For better quality receivers at 46MHz, an RF pre-stage can be added (see Figure 21) to improve the noise figure. Without this transistor, a noise figure F=11dB was found. With a transistor (BFY 90) with RC coupling at 3mA, F=7dB or at 6mA F=6dB.
With a transistor stage having an LC-tuned circuit, one can obtain F=7dB at 1=0.3mA. NOTE: The noise figure includes lmage�noise.
An LC Osclllator at 1.7MHz
An LC oscillator can be designed with or without AFC. If for better stability external AFC is required, one can make use of the DC output of the signal demodulator, which delivers 80mV/kHz at a DC level of 0.65V to +supply. An LC oscillator as shown in Figure 22a, using a capacitor with a temperature coefficient of -150ppm, gives an oscillator signal of 190mV, with a temperature stability of 1kHz/50�.
With the use of AFC, as shown in Figure 22b, one can further improve the stability, as AFC reduces the influence of frequency changes in the transmitter (due to temperature influence or aging). The given circuit gives a factor 2 reduction. Note that the temperature behavior of the AFC diode has to be compensated. In Figure 22b, with BB405B having a capacitance of 18pF at the reverse voltage V4=0.7V, the temperature coefficient of the capacitor Chas to be -200ppm.
AF Output Posslblllties
The AF output from the signal demodulator, available at Pin 4, depends on the slope of the demodulator as shown in Figure 15. The TDA7000 AF output is also available at Pin 2 (see Figure 23). The important difference between the output at Pin 2 and the output at Pin 4 is that the Pin 4 output is amplified and

limited before it is led to Pin 2 (see Figure 24). Moreover, the Pin 2 output is controlled by the mute function, a mute which operates in case the received signal is bad as far as noise and distortion are concerned.
The Pin 2 output delivers a higher AF signal; however, the AF output spectrum shows more mixing products between IF harmonics and modulation frequency harmonics. This is due to the "limited output situation" at Pin 2. In narrow-band application with relatively large deviation these products are so high that extra AF output filtering is required and, moreover, the IF center frequency has to be higher compared to the concept, using AF output at Pin 4.
So for those sets where the mute/squelch function of the TDA7000 is not used, and the higher AF output is not required, the use of the AF output at Pin 4 is advised, giving less interfering products and simplified AF output filtering.
Squelch and Squelch Indication
The TDA7000 contains a mute function, controlled by a "waveform correlator", based on the exactness of the IF frequency.
The correlation circuit uses the IF frequency and an inverted version of it, which is delayed (phase-shifted) by half the period of nominal IF. The phase shift depends on the value of the capacitor at Pin 18 (see Figure 23).
This mute also operates at low field strength levels, where the noise in the IF signal indicates bad signal definition. (The correlation between IF signal and the inverted phase-shifted version is small due to fluctuations caused by noise; see Figure 25.) This field strength-dependent mute behavior is shown in Figure 26, Curve 2, measured at full mute operation. The AF output is not ''fast-switched" by the mute function, but there is a "progressive (soft muting) switch". This soft muting reduces the audio output signal at low field strength levels, without degradation of the audio output signal under these conditions.
The capacitor, C1, at Pin 1 (see Figure 23) determines the time constant for the mute action.
Part operation of the mute is also a possibility (as shown by Figure 26, Curve 3) by circuiting a resistor in parallel with the mute capacitor at Pin 1.
In Figure 26 the small signal behavior with the mute disabled has been given also (see Curve 1).
One can make use of the mute output signal, available at Pin 1, to indicate squelch

situation by an LED (see Figure 27). Operation of the mute by means of an external DC voltage (see Figure 28) is also possible.
Bell Signal Operation
To avoid tone decoder filters and tone decoder rectifiers for bell signal transmission, use can be made of the mute information in the TDA7000 to obtain a bell signal without the transmission of a bell pilot signal.
With a handset receiver as shown in Figure 23 in the "standby" position, the high mute output level turns amplifier 1 off via transistor T1 until a correct IF frequency is obtained. This situation appears at the moment that a bell signal switches the base unit in transmission mode. If the transmitted field strength is high enough to be received above a certain noise level, the mute level output goes down; T1 will be closed and amplifier 1 starts operating. However, due to feedback, 1his amplifier starts oscillating at a low frequency (a frequency dependent on the filter concept). This low-frequency signal serves for bell signal information at the loudspeaker.
Switching the handset to "talk" position will stop oscillation. Then amplifier 1 serves to amplify normal speech information.
Mute at Dlallng
During dial operation, the key-pulser IC delivers a mute voltage. This voltage can be used to mute the AF amplifier, e.g., via T1 of the bell signal circuit/amplifier (see Figure 23).
CONCLUSIONS
The application of the TDA7000 in the remote unit (handset) as narrow-band FM receiver is very attractive, as the TDA7000 reduces assembly and post-production alignment costs. The only tunable circuit is the oscillator circuit, which can be a simple crystal-controlled tank circuit.
A TDA7000 with:
� filth-order IF filter
�third-order AF output filter
� matched input circuit
� crystal oscillator tank circuit
� disabled mute circuit gives a sensitivity of 2.5�V for 20dB signal-to-noise ratio, at adjacent channel selectivity of 40dB (at 15kHz) in cordless telephone application at 1.?MHz.
The TDA7000 circuit is:
� without an RF pre-stage

December 1991

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Signetics RF Communications
TDA?OOO for narrowband FM reception

Application specification
AN193

� without RF-tuned circuits �without oscillator transistor (and its compo-
nents) � without LC or ceramic filters in IF and de-
modulator.
For improved performance, the TDA7000 circuit can be expanded: � with an RF pre-stage and RF selectivity � with higher-order IF filtering �with mute/squelch function.
For reduced performance the TDA7000 circuit can be simplified: � to LC-tuned oscillator � to lower-order IF filter � to bell signal operation without pilot trans-
mission.
Previously published as "BAE83135," Eindhoven, The Netherlands, December 20, 1983.

6/0IV 80

_ _ o~

._..__,_~__.__.~_._'--'----'---'---'--''--'"-'-~

10MG 11

13

lper

1G

FREQUENCY

100/DIV.

a. 1-Pln Crystal Osclllator

soo

~<> 0 1---------------t------------
~

-600~---"'--"'-~--'~-'-~'--'-"'--"'---'-~---'-'---'~

10MG

11

13

lpor

1G

FREQUENCY

b. 1-Pln Crystal Osclllator

Figure 10.

December 1991

432

Signetics RF Communications
TDA7000 for narrowband FM reception
8/DIV 80

Application specification
AN193

Rp:250CI

O'--~~~-'-~'--"-''-'-....._.~~~-'-~-'-~---''---'-'--'-'-'

10MG

1G

FREQUENCY

a.1-Pln Crystal Oscillator
(R =oo, 250, 60)

100/DIV.

600

................... -800 '--~~~~-'--'-~-'--'--'-~~~~~-'--'-~-'-

10MG

1G

FREQUENCY

b. 1-Pln Crystal Oaclllator
(R =oo, 250, 60)

Figure 11.

December 1991

433

Signetics RF Communications
TDA7000 for narrowband FM reception

Application specification
AN193

10dBIDIV 40
.; 0

42d8

R5 �121< A11:1 A2. 2.2K
R3sA4=4.7K
C1�1.3nF
C2.18nF C3:3nf C4:47nf
cs. 3.3nf

....,~~--'~~~~~~~~-'-~~~~~~~~~~~

0

40K

FREQUENCY 5lllDIV

10dBIDIV 40
.. 0
>

LS1.cn:-,
12

1
57. .

R5:12K
R1 � R2� 2.2K R3aR4�4.7K C1 �1.3nF C2.18nF
C3�3nF C4o47nf CS:3.3nF L1=10DmH

..... ~~~~~~~~~~--'~~-'-~~...-~~~~--'

0

1DK

4DK

FREQUENCY 5lllDIV

Flgure12.

December 1991

434

Signetics RF Communications
TDA7000 for narrowband FM reception
IF SELECTIVITY 0 -10 -20

Application specification
AN193

-70

10

15

FREQUENCY (kHz)

Figure 12 (Continued)

10 4.7nF
a.

12

15

I I 3.3nf 4.7�F
�

8

10

11 12

15

I I 3.3nF 4.7�F 1:1

b.

�

Figura 13.

20
c. d.

December 1991

435

Signetics RF Communications
TDA7000 for narrowband FM reception

Application specification
AN193

v.,

~------ TO CORRELATOR 17

NOTES:

With R2 � 0. 4' - �2tan1 sR1C17

= for cp .. -90�C, C17

j -1

=4.ln.F for f1F = 5kHz.

wRi RR43

To improve the performance of the all-pass filter with the amplitude limited IF waveform, R2 has been added. Since this Influences the phase angle, the value o1 C17 must be increased by 13%, I.e., to 4.7nF.
Figure 14. FM Demodulator Phase-Shift Circuit (All-Pass Filter)

~

I I I I i ~Ii

1.2 ~-+-+-+--11-+-+-+--1 TJAi~ A~ 1~1.J.ii v;1= ~m~ !-+-

~ ::~

!~C

o.e
0.8

l"J~ hi,.

11
II
,\ I

5
il
>

0o~..!611t--1r--tr--t+--i--tt--+--t!tlS"-I"1--ft"-~Tl'"".:,:.+.-~+,-_i-,+:+:-�1:7"'F"J','.1"-"+'iL-l-tJ+--1+Y--+i-"l+-i+-i-+t+-+-++---1l

o.3 H-+++-+-H-l--+++-+-H-+++-+-H-1--1

0.2 H-+-t-+-+-t-1-+-+-+-+-+-f-l-+-++-+-t-11-+-I

0.1 H-+-+-+-+-t-1-+-+-+-+-+-f-l-+-++-+-f-11-+-I
o~.....L-'--'--L-.L...J....J......L-'-..L.'--L...l-'--L..1-..L..L...JL.J._J

0 1 2 3 4 5 6 7 8 9 101112131415161718 19202122
~f(kHz)

Figure 15.

10

0
~
Nb

�N

~

i-.,... ,...,...

-60

~

0 1 2 3 4 5 6 7 8 9 1011121314 1516171819 202122

l(kHz) Figure 16.

December 1991

436

Signetics RF Communications
TDA7000 for narrowband FM reception
+ TDA 7000
4 i-.-"IM.+-'IN\.-.-"I

a.

10K

b.

Figure 17

-r- I+Vs 10

1Vose

AOnf

=200mV

*

4.7nf

4.7 4.7 3.9 �F nf nf

December 1991

Figure 18. 437

Application specification
AN193
900K

Signetics RF Communications
TDA7000 for narrowband FM reception

Application specification
AN193

0

60

iJ -10 50

-Ill)

I40

r I,_
�"' -

l
~30

v 20 uc: -40

_j_

~/

-50 10

0 1�V

I
1/ls
~
t\
10�V

y~ 1 l"J ~J=~ ~ 1000 Fs= 1.7MHZ V =4.IV

r'P.�

10"�"V"

1mV

V1 AT PINS 13/14 (WITH Rs =500)

Figure 19.

~~~[IlTICOI:LIQNsT:2N0AL

10

~:I

I

llOpF

I

12pF 150

I

FREQUENCY
Figure 20.

400MG 10MG/DIV.

December 1991

438

Signetics RF Communications
TDA7000 for narrowband FM reception

OSC. TANK CIRCUIT

OSCILLATOR

l

llXER

Application specification
AN193

Figure 21.

TDA 7000

r---,

�-1

I 210!>!:
" 1 1N150

5

L _ _ _ _J

+4.BV

TOKYO COL. TYPE/7BR
n1 = 30TURNS n2 = 7TURNS
Clo= 100
L= 32�H

a.

r---,

n1 II C 270pF

884058

4.7nF
180K
b. Figure 22.

December 1991

439

Signetics RF Communications
TDA7000 for narrowband FM reception
0
+Vs

Application specification
AN193
I'

Figure 23. Remote Unit Receiver: 1.7MHz
l.F.ILJ-u LARGE CORRELATION WCTUOITRllHNRGECT I� �F . ' I U - u
a.

SMALL

CORRELATION

n n n DUETO
LJ LJ DETUNING

� l.F.

_J

L

b.

l.F.~

0

6 ~.f.(kHz)

8

9

10 11

L _ _ f L J VERY SMALL
CORRELATION DUE TO

Figure 24. Demodulator Characteristics

NOISE

l.F.'
c.

Figure 25. Function of the Correlation Muting System

December 1991

440

Signetics RF Communications
TDA7000 for narrowband FM reception

Application specification
AN193

0

~ -10
I

~
T

--20

V1

- - - MUTE DISABLE

--50 H

1----

FULL MUTE PARTIAL

--60 llllllL llllilll ll

1�V

10�V

100�V

1mV

Flgure26.

~
_L ~

J
~

v

0

I/

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4

Y1-5(YOLT)

Figure 28.

TDA7000

Figure 27. Function of the Correlation Muting System

December 1991

441

Slgnetlcs RF Communications
Single-chip FM radio circuit

Preliminary specification
TDA7000

GENERAL DESCRIPTION

The TDA7000 is a monolithic integrated circuit for mono FM portable radios, where a minimum on

peripheral components is important (small dimensions and low costs).

i' I'

The IC has an FLL (Frequency-Locked-Loop) system with an intermediate frequency of 70 kHz. The i.f. selectivity is obtained by active RC filters. The only function which needs alignment is the resonant circuit for the oscillator, thus selecting the reception frequency. Spurious reception is avoided by means of a mute circuit, which also eliminates too noisy input signals. Special precautions are taken to meet

the radiation requirements.

The TDA7000 includes the following functions:

� R.F. input Stage � Mixer � Local oscillator � l.F. amplifier/limiter � Phase demodulator � Mute detector � Mute switch

QUICK REFERENCE DATA
Supply voltage range (pin 5)
Supply current at Vp = 4,5 V
R.F. input frequency range
Sensitivity for -3 dB limiting
(e.m.f. voltage) (source impedance: 75 il; mute disabled) Signal handling (e.m.f. voltage) (source impedance: 75 il)
A.F. output voltage at RL = 22 kil

Vp

2,7 to 10 V

Ip

typ.

8 mA

frt

1,5to 110 MHz

EMF typ. 1,5 �V
EMF typ. 200 mV Vo typ. 75 mV

March 1983

442

Signetics RF Communications
Single-chip FM radio circuit

Preliminary specification
TDA7000

r.f. input

18

17

DEMODULATOR mute control

15 14 1,4V

13 12

11

10

13,6 kQ

x
MIXER

12krl 1.F.
TOA 7000

Vp 1+4,5V)

I
a.f. output

Fig, 1 Block diagram.

7286939.1

March 1983

443

Signetics RF Communications
Single..;chip FM radio circuit

Preliminary specification
TDA7000

RATINGS

Limiting values in accordance with the Absolute Maximum System (IEC 134)

Supply voltage (pin 5)

Vp max.

12 v

Oscillator voltage (pin 6)

V5.5 Vp-0,5 to Vp +0,5 V

Total power dissipation

see derating curve Fig. 2

Storage temperature range

Tstg

-55 to+ 150 oc

Operating ambient temperature range

Tamb

Oto +60 oc

2 Ptat
(W)
1,5
0,5
0 -50

7287251

~
~ I'<.. ~ l ~ \

0

50

100

150

T amb (OC)

Fig. 2 Power derating curve.

D.C. CHARACTERISTICS Vp = 4,5 V; Tanib = 25 �c; measured in Fig. 4; unless otherwise specified

parameter
Supply voltage (pin 5) Supply current
atVp=4,5V Oscillator current (pin 6) Voltage at pin 14 Output current at pin 2
Voltage at pin 2; RL = 22 kn

symbol

min.

typ.

Vp

2,7

4,5

max.

unit

10

v

Ip

-

8

-

mA

15

-

280

-

�A

. V14-16

-

1,35

-

v

12

-

60

-

�A

V2-16

-

1,3

-

v

March 1983

444

Signetics RF Communications
Single-chip FM radio circuit

Preliminary specification
TDA7000

A.C. CHARACTERISTICS
Vp = 4,5 V; Tamb = 25 oc; measured in Fig. 4 (mute switch open, enabled); frf = 96 MHz (tuned to max. signal at 5 �V e.m.f.) modulated with Lif = � 22,5 kHz; fm = 1 kHz; EMF= 0,2 mV (e.m.f. voltage at a source impedance of 75 n); r.m.s. noise voltage measured unweighted (f = 300 Hz to 20 kHz); unless otherwise specified.

parameter

symbol

min.

typ.

max.

unit

Sensitivity (see Fig. 3) (e.m.f. voltage)

for -3 dB limiting; muting disabled

EMF

-

for -3 dB muting
for S/N = 26 dB

EMF

-

EMF

-

Signal handling (e.m.f. voltage)

for THO< 10%; Lif = � 75 kHz

EMF

-

Signal-to-noise ratio

S/N

-

Total harmonic distortion
at Lit=� 22,5 kHz
at Lit=� 75 kHz

THO

-

THO

-

AM suppression of output voltage

(ratio of the AM output signal

referred to the FM output signal)

FM signal: fm = 1 kHz; Lif = � 75 kHz

AM signal: fm = 1 kHz; m = 80%

AMS

-

Ripple rejection (LiVp = 100 mV;

f=1 kHz)

RR

-

Oscillator voltage (r.m.s. value) at pin 6
Variation of oscillator frequency with supply voltage (LiVp = 1 V)

v6-5(rms)

-

Lifosc

-

Selectivity A.F.C. range

S+300

-

S-300

-

Lif rt

-

Audio bandwidth at LiV0 = 3 dB

measured with pre-emphasis (t = 50 �s) B

-

A. F. output voltage (r.m.s. value) at RL = 22 kn
Load resistance
at Vp = 4,5 V
at Vp = 9,0 V

Vo(rms)

-

RL

-

RL

-

1,5

-

�V

6

-

�V

5,5

-

�V

200

-

mV

60

-

dB

0,7

-

%

2,3

-

%

50

-

10

-

250

-

60

-

45

-

35

-

� 300 -

10

-

75

-

-

22

-

47

dB
dB
mV
kHz/V dB dB kHz
kHz
mV
kn kn

March 1983

445

Signetics RF Communications
Single-chip FM radio circuit

Preliminary specification
TDA7000

7Z87252

Vo (dB)

0 1~

VI

V2 I Y1

-20 h--l.1L 1

~~

THO

r--+---111"i:~~H+t~--t-+-f-+f+H+--+-t-+t+tl-tt-~t-1-++tiftlt~+--t-H-t-tttt--t--++t+tl~ (%)

-40t---+---+-+-+-+++~~~~........+--+--+->-+++++-~+-+-+-++-H++~--+---+--+-+-~f<---+---+-+--+-++-H+-~+-+--+-++-H-H10

t----t--t--t-t-ttttt----t~-t!--..""k:H-tttt-~t---t-t-tt-tttt�NMOwlS~E---t--t-t-tttlrt--t------t---H--trlit-~r~�H~D-t-t--ttt+l5
-60 ~~~~~'H~+-_-_-~+_-~+~-i:_~+~+l~=l:l~=-=_=~F=-~F=~:l=~:l=~!=l~*~Fl=_:::::_:_=FI~_:=~~,:i_=!=!f!~~_:=~_:=_:=_:=_:=:i.:t~:;~~Ll~~~ o

10-6

10-5

10-4

10-3

10-2

10-1

1

EMF (V) at Rs= 75U

Fig. 3 A. F. output voltage (V0) and total harmonic distortion (THD) as a function of the e.m.f. input voltage (EMF) with a source impedance (Rs) of 75 n: (1) muting system enabled; (2) muting system disabled. Conditions: 0 dB= 75 mV; frf = 96 MHz.
for S + N curve: ~f = � 22,5 kHz; fm = 1 kHz.
for THD curve: ~f = � 75 kHz; fm = 1 kHz.

Notes 1. The muting system can be disabled by feeding a current of about 20 �A into pin 1. 2. The interstation noise level can be decreased by choosing a low-value capacitor at pin 3. Silent
tuning can be achieved by omitting this capacitor.

March 1983

446

Signetics RF Communications
Single-chip FM radio circuit

Preliminary specification
TDA7000

C18 220pF
18 CORRELA TOR

C17 330pF
17

DEMODULATOR

mute control

MUTE

C15 100 nF
15

C12 150pF

C11 3,3 nF

11

10

13,6k!1

x
MIXER

12k!1 l_F_
TOA 7000

2,2 k!! 2,2 k!!

NOISE SOURCE

R1

enabled

nF

Vp (+4,5 V) mute switch
a.f. output

C2 I1,8nF

C3 22nF

C4 10nF

L 1 56 nH
c,

C7

3,3 nF
ca

180pF

7-286940.1

Fig. 4 Test circuit; for printed-circuit boards see Figs 5 and 6.

March 1983

447

Signetics RF Communications
Single-chip FM radio circuit

Preliminary specification
TDA7000
I
i'

l!\I
7Z86938.1
Fig. 5 Track side of printed-circuit board used for the circuit of Fig. 4.

Fig. 6 Component side of printed-circuit board showing component layout used for the circuit of Fig. 4.

March 1983

448

Slgnetlcs RF Components
Single-chip FM radio circuit

Development Data
TDA7021T

GENERAL DESCRIPTION
The TDA7021T integrated radio receiver circuit is for portable radios, stereo as well as mono, where a minimum of periphery is important in terms of small dimensions and low cost. It is fully compatible for applications using the low-voltage micro tuning system (MTS). The IC has a frequency locked loop (FLL) system with an intermediate frequency of 76 kHz. The selectivity is obtained by active RC filters. The only function to be tuned is the resonant frequency of the oscillator. lnterstation noise as well as noise from receiving weak signals is reduced by a correlation mute system.
Special precautions have been taken to meet local oscillator radiation requirements. Because of the low intermediate frequency, low pass filtering of the MUX signal is required to avoid noise when receiving stereo. 50 kHz roll-off compensation, needed because of the low pass characteristic of the FLL, is performed by the integrated LF amplifier. For mono application this amplifier can be used to directly drive an earphone. The field-strength detector enables field-strength dependent channel separation control.

Features
� RF input stage � Mixer � Local oscillator � IF amplifier/limiter � Frequency detector � Mute circuit � MTS compatible

� Loop amplifier � Internal reference circuit � LF amplifier for
- mono earphone amplifier or - MUX filter � Field-strength dependent channel separation control facility

QUICK REFERENCE DATA

parameter
Supply voltage (pin 4) Supply current RF input frequency Sensitivity (e.m.f.) for
-3 dB limiting
Signal handling (e.m.f.) AF output voltage

conditions Vp= 3 V

symbol

min. typ.

Vp = V4_3 1,8 -

14

-

6,3

f rf

1,5 -

max. unit

6,0 v

-

mA

110 MHz

source impedance= 75 n;
mute disabled
source impedance= 75 n

EMF EMF

Vo

-

4

-

�V

-

200 -

mV

-

90 -

mV

PACKAGE OUTLINE 16-lead mini-pack; plastic (5016; SOT109A).

February 1991

449

~
.,CT
2
-< ~

MUX out
t I

16

15

l
114

RF input
1
t G

field strength
10

w.
c::cJ C., i)

Q1 ro
::>
...CD
~
0
.J,J,
0

(')
-,:o:,r�
s::

0
3
-0 0 ::> CD
:o:>r

.....

17,5 kl!

52 kl!

~

170 �A

5�

13 kl!

J; 60 pF

16 kl!

0,9V 700 I! 700 I!

+

.Q.....
c0 :

;::::;:

RF STAGE

IF FILTER

+

TDA7021T

...
0"'

I ~ II I-

I

x

I 2,2 kl!

150pf1 2,2 kl!

MUTE CONTROL.

MIXER

4,7 kl!

6

17 18

-I

0 c

+ Vp

,-,-:.;.-1.-.1. 893

)> ~

.......i 0
I...\..).
I -I

0
-0
3
acC.D,

Fig. 1 Block diagram.

I�

Signetics RF Components
Single-chip FM radio circuit

Development Data
TDA7021T

RATINGS Limiting values in accordance with the Absolute Maximum System {IEC 134)

parameter

conditions symbol

Supply voltage {pin 4) Oscillator voltage Storage temperature range Operating ambient temperature range

Vp = V4_3 V5_4 Tstg Tamb

min.
-
Vp-0,5 -55 -10

max.

unit

7,0

v

Vp + 0,5 v

+150

oc

+70

oc

THERMAL RESISTANCE From junction to ambient

Rth j-a 300 K/W

DC CHARACTERISTICS
Vp = 3 V, Tamb = 25 oc, measured in circuit of Fig. 4, unless otherwise specified

parameter Supply. voltage {pin 4) Supply current Oscillator current Voltage at pin 13 Output voltage {pin 14)

conditions symbol

Vp = 3 V

Vp = V4_3
14

15

V13-3 V14_3

min. typ.

1,8 3,0

-

6,3

-

250

-

0,9

-

1,3

max. unit

6,0 v

-

mA

-

�A

-

v

-

v

Ip (mAI
/i

7Z87965

4

l

3

0

4 Vp IV)

Fig. 2 Supply current as a function of the supply voltage.

February 1991

451

Signetics RF Components
Single-chip FM radio circuit

Development Data
TDA7021T

AC CHARACTERISTICS (MONO OPERATION)
Vp = 3 V; Tamb = 25 �C; measured in Fig. 5; frt = 96 MHz modulated with At=� 22,5 kHz; fm = 1 kHz; EMF= 0,3 mV (e.m.f. at a source impedance of 75 Q); r.m.s. noise voltage measured unweighted (f = 300 Hz to 20 kHz); unless otherwise specified

parameter

conditions

symbol

min. typ.

Sensitivity (e.m.f.)

see Fig. 3

for -3 dB limiting

muting disabled

EMF

4,0

for -3 dB muting

EMF

5,0

for(S+N)/N = 26 dB

EMF

7,0

Signal handling (e.m.f.)

THO< 10%;

Af = � 75 kHz

EMF

200

Signal-to-noise ratio

(S+N)/N

60

Total harmonic distortion

Af = � 22,5 kHz

THO

0,7

Af=�75kHz

THO

2,3

AM suppression of output voltage

ratio of AM signal

(fm = 1 kHz; m = 80%)

to FM signal (fm =

1 kHz; Af = 75 kHz) AMS

50

Ripple rejection

AVp = 100 mV;

f = 1 kHz

RR

30

Oscillator voltage (r.m.s. value)

V5.4(rms)

250

Variation of oscillator frequency

with supply voltage

AVp = 1 V

Afosc

5

AVp

Selectivity
AFC range Mute range Audio bandwidth
AF output voltage (r.m.s. value)
AF output current max. d.c. load max. a.c. load (peak value)

see Fig. 9; no modulation
1
AV0 =3dB; measured with 50 �s pre-emphasis

S+300 5-300 �Afrf �Afrt
B

RL (pin 14)= 10on Vo(rms)

THO= 10%

lo(dc) lo(ac)

46 30 160 120
10
90
-100 3

max. unit
�V �V �V
mV dB % %

dB
dB mV
kHz/V

dB dB kHz kHz

kHz

mV

+100 �A

-

mA

February 1991

452

Signetics RF Components
Single-chip FM radio circuit

Development Data
TDA7021T

0,20 DC level O, 18
IVI 0,16 0,14 0,12 0,10 0,08 0,06 0,04 0,02 0 10-6

!
b-.
~
1h
~
bI~ t-
10-5

7Z87966. I
-L !
11
I 1

10- 2

10-1 EMF !VI

Fig. 3 Field strength voltage (V9_3) at Rsource = 1 kQ; f = 96,75 MHz; Vp = 3 V.

7ZB777B.2

~;

-201f---./,f=t-~~:+t++tt--t-t-t-l-+++t+-~+-+-t-+-f-ttH-----1---1-t-t+fttt~-t--t--t-+ttttt-~t-t-t-f-ttt+ITHD

~"t--

(%)

-401-"'l---+-+-H-++H~t----1'...+-+-H++++-~-+--+-t-+-f+l-ft----j--j-+-++-fttt~-+--+-++++tft-~t--t-+-+++t+ilO

~

_ 60

I'-

NOISE

5

t----+--+-+-t-+++++-~-+---+--+-+-t++t+---J--J-t-rt-rttt-TH~-+-+-+-+-++++~-;--;-r-r-t-tttt-~r-t-t--i-t-ttti

-80~~~~~~~~~~~~~~~~~~-~~~~~~~~~~~~~~~~o

10-6

10-5

10-4

10- 3

10- 2

10-l

EMF I VI at Rs= 75!1

Fig. 4 Mono operation: AF output voltage (V0 ) and total harmonic distortion (THO) as functions of input e.m.f. (EMF); Rsource = 75 D; frf = 96 MHz; 0 dB= 90 mV. For S+N and noise curves (1) is with muting enabled and (2) is with muting disabled; signal Llf = � 22,5 kHz and fm = 1 kHz. For THD curve, Llf = � 75 kHz and fm = 1 kHz.

February 1991

453

Signetics RF Components
Single-chip FM radio circuit

Development Data
TDA7021T

AF
output

~ I
110011 3,3

TnF

nF

I I

16

15

14

~ EMF t,1 !220 Rs=75n

pF

220

4,7 nF

pF

field strength
8,2 kH

13

12

11

10

9

TDA7021T

7Z97113.1

1) The AF output can be decreased by disconnecting the 100 nF capacitor from pin 16.

Fig. 5 Test circuit for mono operatio01.

AC CHARACTERISTICS (STEREO OPERATION)
Vp = 3 V; Tamb = 25 �C; measured in Fig. 8; frf = 96 MHz modulated with pilot Af = � 6,75 kHz and AF signal Af = � 22,5 kHz; fm = 1 kHz; EMF= 1 mV (e.m.f. at a source impedance of 75 !1); r.m.s.
noise voltage measured unweighted (f = 300 Hz to 20 kHz); unless otherwise specified

parameter Sensitivity (e.m.f.)
for (S+N)/N = 26 dB Selectivity
Signal-to-noise ratio Channel separation

conditions

symbol min. typ.

see Fig. 8; pilot off

EMF -

11

see Fig. 9; no modulation S+300 -

40

5-300 -

22

(S+N)/N -

50

Vi= L-signal; fm = 1 kHz;

pilot on:

at frf = 97 MHz

a

at frf = 87,5 MHz

and 108 MHz

a

-

26

-

14

max. unit

-

�V

-

dB

-

dB

-

dB

-

dB

-

dB

February 1991

454

Signetics RF Components
Single-chip FM radio circuit

Development Data
TDA7021T

-50f--~+---+--+-++++TI~~+---t--t-+t-f�~~~-)'t...-_-~ -t--+-+t+'-ff't-r--,-=..:...;..;"1===fst=erfe:o=nlo=is=el=l==l=l=l50

-eol_~_l_~L_LJ_l_LLLi_~_J~_l___l___Ll_J_Jjj_~~_l_:::t::�:�- :, .�_:�_:���::::=:::::::r::m:o:n:o::nEo:is:e:!:::f:�:��~eo

1

10

102

103

EMF (�VI

104

Fig. 6 Stereo operation: signal/noise and channel separation of TDA7021T when used in the circuit of Fig. 8.

30

7Z97894

channel separation a
(dB)
20
10 10

~ v
1'
y
JL

97 MHz

"b-
~
I)_ )'\

87,5 and 108 MHz _j_ _J _J

~

f (Hz)

Fig. 7 Stereo operation: channel separation as a function of audio frequency in the circuit of Fig. 8.

February 1991

455

Signetics RF Components
Single-chip FM radio circuit

Development Data
TDA7021T

100

1,5 nF

nF

330 pF

22 pF

100 nF

I100
nF

TDA7021T

10

11

12

13

14

~~

56 pF

I 2. :, 220

rF

100

BC549C

pF

270 kll

15 ll

Vp

k2n2~

100 nF

~~a !
10 nF

TDA7040T

TDA7050T

Fig. 8 Stereo application in combination with a low voltage PLL stereo decoder (TDA7040T) and a low voltage mono/stereo power amplifier (TDA7050T).

February 1991

456

Signetics RF Components
Single-chip FM radio circuit

Development Data
TDA7021T

TDA7021T

100k!1 11 IN

LIM

V;

VP

generator

f;

4

R6 100 k!1

Fig. 9 Test set-up; Vi= 30 mV; fi = 76 kHz; selective voltmeter at output has Ri;;;, 1 Mn and Ci.;; 8 pF, f0 = fi.

Note to Fig. 9
This test set-up is to incorporate the circuit of Fig. 5 for mono operation or the circuit of Fig. 8 for stereo operation. For either circuit, replace the 100 nF capacitor at pin 6 with R6 (100 kn) as shown above.

Selectivity
Vo I (300 kHz -fi) 5+300 = 20 log - - - - - -
Vo I fi

Vo I (300 kHz+ fj) S-300 = 20 log - - - - - -
Vo I fj

February 1991

457

Signetics RF Communications

Section 4 Mixers

INDEX

MC1496/MC1596 Balanced modulator/demodulator .....................�. 461

AN189

Balanced modulator/demodulator applications using the MC1496/1596 ...............�............... 465

NE/SA602A Double-balanced mixer and oscillator ....�................ 470

NE/SA612A Double-balanced mixer and oscillator ..................... 478

AN1981

New low-power single sideband circuits ................... 485

AN1982

Applying the oscillator of the NE602 in low-power mixer applications ........................... 493

TDA1574

FM front-end IC ...�.................................. 496

TDA1574T Integrated FM tuner for radio receivers .............��.... 504

TDA5030A TV VHF mixer/oscillator UHF preamplifier ................. 513

Slgnetlcs RF Communications
Balanced modulator/demodulator

Product specification
MC1496/MC1596

DESCRIPTION
The MC 1496 is a monolithic double-balanced modulator/demodulator designed for use where the output voltage is a product of an input voltage (signal) and a switched function (carrier). The MC1596 will operate over the full military temperature range of -55 to
+125�C. The MC1496 is intended for
applications within the range of 0 to +70�C.

FEATURES
� Excellent carrier suppression 65dB typ@ 0.5MHz 50dB typ@ 10MHz
� Adjustable gain and signal handling
� Balanced inputs and outputs
� High common-mode rejection-85dB typ

APPLICATIONS
� Suppressed carrier and amplitude modulation
� Synchronous detection � FM detection � Phase detection �Sampling � Single sideband � Frequency doubling

PIN CONFIGURATION
F, N Packages

POSITIVE 1 SIGNAL INPUT GAIN ADJUST 2
GAIN ADJUST 3
SIG~ff~'\JY}t 4
BIAS 5
p83+'ll~!f 6

Vee
NC NEGATIVE OUTPUT 11 NC
NEGATIVE CARRIER INPU 9 NC 8 POSITIVE CARRIER INPU

ORDERING INFORMATION
DESCRIPTION 14-Pin Cerdip 14-Pin Plastic 14-Pin Cerdip 14-Pin Plastic

TEMPERATURE RANGE 0 to +70�C 0 to +70�C
-55 to +125�C -55 to +125�C

ORDER CODE MC1496F MC1496N MC1596F MC1596N

ABSOLUTE MAXIMUM RATINGS

SYMBOL

PARAMETER

Applied voltage

Va-V10 Differential input signal

V4-V1 Differential input signal

V2-V1, v'5"v4

Input signal

Is

Bias current

rvfax1mum powerrnss1pat1on, T A~iiif:air)

PD

F package

N package

TA

Operating temperature range

MC1496

MC1596

Tsrn

Storage temperature range

NOTES: 1. Derate above 25�C, at the following rates:
F package at 9.5mW/�C N package at 11.4mWi�C

RATING 30 �5.0
(5�15 R0 )
5.0
10
1190 1420
Oto +70 -55to +125 -65 to +150

UNIT v v v
v
mA
mW mW
oc
"C
oc

March 18, 1987

461

853-1201 88138

Signetics RF Communications
Balanced modulator/demodulator
EQUIVALENT SCHEMATIC

Product specification
MC1496/MC1596

I�
I
10
CARRIER(-)
INPUT(+)

4 SIGNAL(-)
INPUT(+) BIAS

2 GAIN ADJUST
3

14
V-

DC ELECTRICAL CHARACTERISTICS Vee=+12Voc: Vcc=-8.0Voc: 15=1.0mADC; RL=3.9kn; Re=1.0kn; TA=25�C, unless otherwise specified.

SYMBOL

PARAMETER

TEST CONDITIONS

MC1596

Min Typ Max

Single-ended input impedance

Signal port, f=5.0MHz

R1p

Parallel input resistance

200

C1p

Parallel input capacitance

2.0

Single-ended output impedance

f=10MHz

RoP

Parallel output resistance

40

Cop

Parallel output capacitance

5.0

Input bias current

las

las=

lac

lee=

12 25 12 25

Input offset current

l1os

l1os=l1-l4

l1oc

l1oc=le-l10

0.7 5.0 0.7 5.0

TcllO loo

Average temperature coefficient of input offset current Output offset current
le-112

2.0 14 50

Tcloo

Average temperature coefficient

90

of output offset current

Common-mode quiescent

Vo

output voltage (Pin 6 or Pin 12)

8.0

Power supply current

lo+

le+l12

lo.

114

2.0 3.0 3.0 4.0

Po

DC power dissipation

33

MC1496 Min Typ Max
200 2.0
40 5.0
12 30 12 30
0.7 7.0 0.7 7.0
2.0
15 80 90
8.0
2.0 4.0 3.0 5.0 33

UNIT
kn pF kn pF �A �A �A �A nAl"C �A nAl"C
Voe mAoc
mW

March 18, 1987

462

Signetics RF Communications
Balanced modulator/demodulator

Product specification
MC1496/MC1596

AC ELECTRICAL CHARACTERISTICS Vee=+12oc; Vee=-9.0Voc; 15=1.0mA00; RL=3.9kn; RE=1.0kn; TA=+25�C unless otherwise specified.

SYMBOL

PARAMETER

TEST CONDITIONS

MC1596

Min Typ Max

VcFT

Carrier feedthrough

Ve=60mVRMS sinewave and offset adjusted to zero

fe=1.0kHz

40

fe=10MHz

140

Ve=300mVp.p squarewave:

Offset adjusted to zero fe=1.0kHz

0.04 0.2

Offset not adjusted le=1.0kHz

20 100

Ves

Carrier suppressions

fs=10kHz, 300mVRMS sinewave fe=500kHz, 60mVRMS sinewave 50 65

fe=10MHz, 60mVRMS sinewave

50

BW3c1e

Transadmittance bandwidth

Carrier input port, Ve=60mVRMS

300

(Magnitude) (RL=50n)

sinewave fs=1.0kHz,

300mVRMS sinewave

Signal input port, Vs=300mVRMS

BO

sinewave IVe I = 0.5Voe

Avs

Signal gain

Vs=100mVRMS; 1=1.0kHz

2.5 3.5

IVe I = 0.5Voc

CMV

Common-mode input swing

Signal port, fs=1.0kHz

5.0

AeM

Common-mode gain

Signal port, fs=1.0kHz

-85

IVe I = 0.5Voc

DVouT

Differential output voltage swing capability

8.0

MC1496 Min Typ Max
40 140
0.04 0.4 20 200
40 65 50 300
BO
2.5 3.5
5.0 -85
8.0

UNIT
�VRMS
mVRMS
dB MHz
MHz VN Vp.p dB Vp.p

March 18, 1987

463

Signetics RF Communications
Balanced modulator/demodulator
TEST CIRCUITS

Product specification
MC1496/MC1596
+12YDC

OUTPUT

_ _ _ 'c INPUT ..._.\Nl,,.._,\N\~---+----ll----0
.01�F

Carrier Re)ectlon and Suppression

= -8VDC
Signal Gain and Output Swing

3.llk i-,o+---+-<0 +Yo l-0--""-Yo
rt---t-<>-'-!.....--,.J
-=- CARRIER NULL -8VDC
Carrier Re)ectlon and Suppression

March 18, 1987

464

Signetics RF Communications
Balanced modulator/demodulator applications using the MC1496/1596

Application note
AN189

BALANCED MODULATOR/DEMODULATOR APPLICATIONS USING MC1496/MC1596 The MC 1496 is a monolithic transistor array arranged as a balanced modulator-demodulator. The device takes advantage of the excellent matching qualities of monolithic devices to provide superior carrier and signal rejection. Carrier suppressions of 50dB at 1OMHz are typical with no external balancing networks required.
Applications include AM and suppressed carrier modulators, AM and FM demodulators, and phase detectors.
THEORY OF OPERATION As Figure 1 suggests, the topography includes three differential amplifiers. Internal connections are made such that the output becomes a product of the two input signals Ve and Vs.
To accomplish this the differential pairs 01-02 and 03-04, with their cross-coupled collectors, are driven into saturation by the zero crossings of the carrier signal Ve. With a low level signal, Vs driving the third differential amplifier 05-06, the output voltage will be lull wave multiplication of Ve and Vs. Thus for sine wave signals, VouT becomes:
Vour = ExEy [cos(111x+111y)t+ cos(111x-111.Y)t] (1)
As seen by equation (1) the output voltage will contain the sum and difference

frequencies of the two original signals. In addition, with the carrier input ports being driven into saturation, the output will contain the odd harmonics of the carrier signals. (See Figure 4.)
Internally provided with the device are two current sources driven by a temperature-compensated bias network. Since the transistor geometries are the same and since VeE matching in monolithic devices is excellent, the currents through 0-, and 0 8 will be identical to the current set at Pin 5. Figures 2 and 3 illustrate typical biasing arrangements from split and single-ended supplies, respectively.
Of primary interest in beginning the bias circuitry design is relating available power supplies and desired output voltages to device requirements with a minimum of external components.
The transistors are connected in a casoode fashion. Therefore, sufficient collector voltage must be supplied to avoid saturation if linear operation is to be achieved. Voltages greater than 2V are sufficient in most applications.
Biasing is achieved with simple resistor divider networks as shown in Figure 3. This configuration assumes the presence of symmetrical supplies. Explaining the DC biasing technique is probably best accomplished by an example. Thus, the initial assumptions and criteria are set forth:
1. Output swing greater than 4Vp.p.
2. Positive and negative supplies of 6V are available.

3. Collector current is 2mA. It should be noted here that the collector output current is equal to the current set in the current sources.
As a matter of convenience, the carrier signal ports are referenced to ground. If desired, the modulation signal ports could be ground referenced with slight changes in the bias arrangement. With the carrier inputs at DC ground, the quiescent operating point of the outputs should be at one-half the total positive voltage or 3V for this case. Thus, a collector load resistor is selected which drops 3V at 2mA or 1.5kn. A quick check at this point reveals that with these loads and current levels the peak-to-peak output swing will be greater than 4V. It remains to set the current source level and proper biasing of the signal ports.
The voltage at Pin 5 is expressed by
= = VstAs Vse 500 � Is
where Is is the current set in the current sources.
BIASING Since the MC1496 was intended for a multitude of different functions as well as a myriad of supply voltages, the biasing techniques are specified by the individual application. This allows the user complete freedom to choose gain, current levels, and power supplies. The device can be operated with single-ended or dual supplies.
Vee

CARRIER") INPUT ( + ) 0 - - - - < . _ - - f - - - - - - + - - - - '

4 (-),0------c

SIGNAL INPUT

(+)b------+--~

GAIN

e-------+---<> ADJUST

10

NOTE:

�..0----+--+-------'

All resistor values are In ohms

Figure 1. Balanced Modulator Schematic

May 1988

465

NOTE:
All resistor values are In ohms
Figure 2. Single-Supply Blasing

Signetics RF Communications
Balanced modulator/demodulator applications using the MC1496/1596

Application note
AN189

NOTE: All resistor values are In ohms
Figure 3. Dual Supply Blaalng
l
i

mentioned, contains the sum and difference frequencies while attenuating the fundamentals. Upper and lower sidel:>and signals are the strongest signals present with harmonic sidebands being of diminishing amplitudes as characterized by Figure 4.

Gain of the 1496 is set by including emitter degeneration resistance located as RE in Figure 5. Degeneration also allows the maximum signal level of the modulation to be increased. In general, linear response defines the maximum input signal as

Vs s 15 �RE (Peak)

and the gain is given by

Avs =_ii_
RE+ 2re

(2)

This approximation is good for high levels of carrier signals. Table 1 summarizes the gain for different carrier signals.

As seen from Table 1, the output spectrum suffers an amplitude increase of undesired sideband signals when either the modulation or carrier signals are high. Indeed, the modulation level can be increased if RE is

NOTES:
fc Carrier Fundamental

FREQUENCY

Is Modulating Signal le� Is Fundamental Ca"ler Sidebands
le� nls Fundamental CMler Sideband Harmon.lcs

nfc earner Harmonics nfc � nfg carrier Harmonic Sidebands

-

Figure 4. Modulator Frequency Spectrum

Ve1AS = VeE = 500 x Is
where Is is the current set in the current sources.
For the example VeE is 700mV at room temperature and the bias voltage at Pin 5 becomes 1. 7V. Because of the cascade configuration, both the collectors of the current sources and the collectors of the signal transistors must have some voltage to operate properly. Hence, the remaining voltage of the negative supply (--OV+1.7V=-4.3V) is split between these transistors by biasing the signal transistor

bases at -2.15V. Coundess other bias arrangements can be used with other power supply voltages. The important thing to remember is that sufficient DC voltage is applied to each bias point to avoid collector saturation over the expected signal wings.
BALANCED MODULATOR
In the primary application of balanced modulation, generation of double sideband suppressed carrier modulation is accomplished. Due to the balance of both modulation and carrier inputs, the output, as

increased without significant consequence. However, large carrier signals cause odd hanmonic sidebands (Figure 4) to increase. At the same time, due to imperfections of the carrier waveforms and small imbalances of the devic:ie, the second harmonic rejection will be seriously degraded. Output filtering is often used with high carrier levels to remove all but the desired sideband. The filter removes unwanted signals while the high carrier level guards against amplitude variations and maximizes gain. Broadband modulators, without benefit of filters, are implemented using low carrier and

May 1988

466

Signetics RF Communications
Balanced modulator/demodulator applications using the MC1496/1596

Application note
AN189

modulation signals to maximize linearity and minimize spurious sidebands.

AM MODULATOR The basic current of Figure 5 allows no carrier to be present in the output. By adding offset to the carrier differential pairs, controlled amounts of carrier appear at the output whose amplitude becomes a function of the modulation signal or AM modulation. As shown, the carrier null circuit is changed from Figure 5 to have a wider range so that wider control is achieved. All connections are shown in Figure 6.
AM DEMODULATION As pointed out in Equation 1, the output of the balanced mixer is a cosine function of the angle between signal and carrier inputs. Further, if the carrier input is driven hard enough to provide a switching action, the output becomes a function of the input amplitude. Thus the output amplitude is maximum when there is 0� phase difference as shown in Figure 7.
Amplifying and limiting of the AM carrier is accomplished by IF gain block providing 55dB of gain or higher with limiting of 400�V. The limited carrier is then applied to the detector at the carrier ports to provide the desired switching function. The signal is then demodulated by the synchronous AM demodulator ( 1496) where the carrier frequency is attenuated due to the balanced nature of the device. Care must be taken not to overdrive the signal input so that distortion does not appear in the recovered audio. Maximum conversion gain is reached when the carrier signals are in phase as indicated by the phase-gain relationship drawn in Figure 7.
Output filtering will also be necessary to remove high frequency sum components of the carrier from the audio signal.
PHASE DETECTOR The versatility of the balanced modulator or multiplier also allows the device to be used as a phase detector. As mentioned, the output of the detector contains a term related to the cosine of the phase angle. Two signals of equal frequency are applied to the inputs as per Figure 8. The frequencies are multiplied together producing the sum and difference frequencies. Equal frequencies cause the difference component to become DC while the undesired sum component is filtered out. The DC component is related to the phase angle by the graph of Figure 9.

CARRIER Ve 0.1�F
INPUT 0----1t---+-----------I
~lg~~tATINuo---...--------<>-----1

3 8
MC1496

INPUT

Vs

4 10

5 9

10k 51

51

+Vo -Vo

CARRIER NULL NOTE: All resistor values are In ohms

V-8VDC

Figure 5. Double Suppressed Carrier Modulator

Table 1. Voltage Gain and Output vs Input Slgnal

CARRIER INPUT SIGNAL(Vc)

APPROXIMATE VOLTAGE GAIN

Low-level DC High-level DC Low-level AC

RL Ve
2(RE + 2rE) (.OV:)
-2!:_
R + 2r,
RL Ve (rms)
2 fi. (.OV:) (RE + 2r,)

High-level AC

0.631RL
RE+ 2r,

OUTPUT SIGNAL FREQUENCY(S)
fM
fM
fc�fM
fc�fM,3fc�fM. 5fc�fM...

+12VDC 1k

I 0.1�F

51

2

3

CARRIER Ve

0.1�F

7

6

INPUT

o-------)1------------1 MC1596K

MODULATING SIGNAL INPUT

MC1496K

Vs

4

9

-750

750 51

10 51

5
IJ 6.8k

RL RL 3.9k 3.9k
+Vo
-Vo

CARRIER ADJUST
NOTE: All resistor values are In ohms

V-8VDC

Fi ure 6. AM Modulator

May 1988

467

Signetics RF Communications
Balanced modulator/demodulator applications using the MC1496/1596
+12V
.1

Application note
AN189

NOTE: All resistor values are Inn..

I /":\ 6.Bk

~I DE-EMPHASIS

-=

-90" 0 90�

PHASE ANGLE

Fl ure 7. AM Demodulator
+1 DC

NOTE: All resistor values are In n.

At 90� the cosine becomes zero, while being at maximum positive or maximum negative at 0� and 180�, respectively.
The advantage of using the balanced modulator over other types of phase comparators is the excellent linearity of conversion. This configuration also provides a conversion gain rather than a loss for greater resolution. Used in conjunction with a phase-locked loop, for instance, the balanced modulator provides a very low distortion FM demodulator.
FREQUENCY DOUBLER
Very similar to the phase detector of Figure 8, a frequency doubler schematic is shown in
Figure 10. Departure from Figure a is
primarily the removal of the low-pass filter. The output then contains the sum component which is twice the frequency of the input,

Figure 8. Phase Comparator since both input signals are the same frequency.
....., ....., ....., .....,
vco -Jl......J L..I LJ L-
INPUT 'v'\/'v�d
+=80� / / / / / / / / 8VDCAVERAG
� =O" fYYYYYYY'\ + VDC AVERA � � 180" \.A.J.J\.AAAN -VDC AVERAG
Figure 9. Phaae Detector� Voltages

May 1988

468

Signetics RF Communications
Balanced modulator/demodulator applications using the MC1496/1596

+12VDC

1k

I 100�F

f---'11--'-'VW",,,._----l e MC1596
1 MC1496
4 10

INPUT 15mVRMS

t 6.8k
Is

3.9k
OUTPUT --0

NOTE: All resistor values are In n.

BALANCE

.v..aoe

Figure 10. Low Frequency Doubler

Application note
AN189

May 1988

469

Slgnetlcs RF Communications
Double-balanced mixer and oscillator

Product specification
NE/SA602A

DESCRIPTION The NE/SA602A is a low-power VHF monolithic double-balanced mixer with input amplifier, on-board oscillator, and voltage regulator. It is intended for high performance, low power communication systems. The guaranteed parameters of the SA602A make this device particularly well suited for cellular radio applications. The mixer is a "Gilbert cell" multiplier configuration which typically provides 1SdB of gain at 45MHz. The oscillator will operate to 200MHz. It can be configured as a crystal oscillator, a tuned tank oscillator, or a buffer for an external LO. For higher frequencies the LO input may be externally driven. The noise figure at 45MHz is typically less than SdB. The gain, intercept performance, low-power and noise characteristics make the NE/SA602A a superior choice for high-performance battery operated equipment. It is available in an 8-lead dual in-line plastic package and an 8-lead SO (surface-mount miniature package).

FEATURES �Low current consumption: 2.4mA typical �Excellent noise figure: <4.7dB typical at
45MHz �High operating frequency �Excellent gain, intercept and sensitivity �Low external parts count; suitable for crys-
tal/ceramic filters �SA602A meets cellular radio specifications
APPLICATIONS �Cellular radio mixer/oscillator �Portable radio �VHF transceivers �RF data links �HFNHF frequency conversion �Instrumentation frequency conversion �Broadband LANs

PIN CONFIGURATION

F, D and N Packages

INAo�8 INg 2

7 VOeSeCE

GND 3

6 OSCa

OUTA 4

5 OUTa

ORDERING INFORMATION
DESCRIPTION 8-Pin Plastic DIP 8-Pin Plastic SO (Surface-mount) 8-Pin Cerdip 8-Pin Plastic DIP 8-Pin Plastic SO (Surface-mount) 8-Pin Cerdip

TEMPERATURE RANGE 0 to +70�C o to +10�c Oto +70�C -40to +85�C -40to +8s0 c -40to+es�c

ORDER CODE NE602AN NE602AD NE602AFE SA602AN SA602AD SA602AFE

ABSOLUTE MAXIMUM RATINGS

SYMBOL

PARAMETER

Vee Maximum operating wltage

Tsm Storage temperature range

TA Operating ambient temperature range NE602A

SA602A

9JA Thermal impedance

D package

N package

RATING 9
-65 to +150 0 to +70 -40to +85 90 75

UNITS
v
�c
�c
�C
�ctw �ctw

April 17, 1990

470

853-1424 99374

Signetics RF Communications
Double-balanced mixer and oscillator
BLOCK DIAGRAM

Product specification
NE/SA602A

AC/DC ELECTRICAL CHARACTERISTICS
Vee= +6V, TA= 25�C; unless otherwise stated.

SYMBOL

PARAMETER

Vee f1N lose
R1N C1N

Power supply voltage range DC current drain Input signal frequency Oscillator frequency Noise figure at 45MHz
Third-order intercept point
Conversion gain at 45MHz RF input resistance RF input capacitance Mixer output resistance

TEST CONDITIONS
RF1N = -45dBm: f1 = 45.0MHz f2 = 45.0SMHz
(Pin 4 or 5)

LIMITS

NE/SA602A

MIN

TYP

MAX

4.5

8.0

2.4

2.8

500

200

5.0

5.5

UNITS
v
mA MHz MHz dB

-13

-15

dBm

14

17

dB

1.5

kn

3

3.5

pF

1.5

kn

DESCRIPTION OF OPERATION
The NE/SA602A is a Gilbert cell, an oscillator/buffer, and a temperature compensated bias network as shown in the equivalent circuit. The Gilbert cell is a differential amplifier (Pins 1 and 2) which drives a balanced switching cell. The differential input stage provides gain and determines the noise figure and signal handling performance of the system.
The NE/SA602A is designed for optimum low power performance. When used with the SA604 as a 45MHz cellular radio second IF and demodulator, the SA602A is capable of receiving -119dBm signals with a 12dB SIN ratio. Third-order intercept is typically -13dBm (that is approximately +5dBm output

intercept because of the RF gain). The system designer must be cognizant of this large signal limitation. When designing LANs or other closed systems where transmission levels are high, and small-signal or signal-to-noise issues are not critical, the inputto the NE602A should be appropriately scaled.
Besides excellent low power performance well into VHF, the NE/SA602A is designed to be flexible. The input, RF mixer output and oscillator ports can support a variety of configurations provided the designer understands certain constraints, which will be explained here.

The RF inputs (Pins 1 and 2) are biased internally. They are symmetrical. The equivalent AC input impedance is
approximately 1.5k II 3pF through 50MHz.
Pins 1 and 2 can be used interchangeably, but they should not be DC biased externally. Figure 3 shows three typical input configurations.
The mixer outputs (Pins 4 and 5) are also internally biased. Each output is connected to the internal positive supply by a 1.5kQ resistor. This permits direct output termination yet allows for balanced output as well. Figure 4 shows three single ended output configurations and a balanced output.

April 17, 1990

471

Signetics RF Communications
Double-balanced mixer and oscillator

Product specification
NE/SA602A

The oscillator is capable of sustaining

operation is utilized. Capacitor C3 and

The resistive divider in the emitter-follower

oscillation beyond 200MHz in crystal or tuned inductor L1 suppress oscillation at the crystal circuit shi>uld be chosen to provide the

tank configurations. The upper limit of

fundamental frequency. In the fundamental minimum input signal which will assure

operation is determined by tank �a� and

mode, the suppression network is omitted.

correct system operation.

�a� required drive levels. The higher the of
the tank or the smaller the required drive, the higher the permissible oscillation frequency.
If the required LO is beyond oscillation limits, or the system calls for an external LO, the external signal can be injected at Pin 6 through a DC blocking capacitor. External LO should be at least 200mVp.p.

Figure 6 shows a Colpitts varactor tuned tank oscillator suitable for synthesizer-controlled applications. It is important to buffer the output of this circuit to assure that switching spikes from the first counter or presceler do not end up in the oscillator spectrum. The dual-gate MOSFET provides optimum isolation with low current. The FET offers

When operated above 100MHz, the oscillator may not start if the Q of the tank is too low. A 22kil resistor from Pin 7 to ground will increase the DC bias current of the oscillator transistor. This improves the AC operating characteristic of the transistor and should help the oscillator to start. A 22kil resistor will not upset the other DC biasing internal to

!,,,.
I'

Figure 5 shows several proven oscillator

good isolation, simplicity, and low current,

the device, but smaller resistance values

circuits. Figure Sa is appropriate for cellular while the bipolar transistors provide the

should be avoided.

radio. As shown, an overtone mode of

simple solution for non-critical applications.

Vee 602A

47pF
INPUT~0.209to0.283�H

220pF

100nF

Figure 1. Teat Configuration

150pF

1.Sto 44.2�H

~UT

Ci 120pF-=

April 17, 1990

472

Signetics RF Communications
Double-balanced mixer and oscillator

Product specification
NE/SA602A

GND
Figure 2. Equivalent Circuit

602A

602A

I
a. Slngle�Ended Tuned Input

b. Balanced Input (For Attenuation of Second-Order Producte)
Figure 3. Input Configuration

602A c. Slngle~Ended Untuned Input

April 17, 1990

473

Signetics RF Communications
Double-balanced mixer and oscillator

Product specification
NE/SA602A

L Single-Ended Ceramic Filter

602A b. Single-Ended Cryallll Filter

TC021171S

602A

602A

c. Single-Ended IFT

Figure 4. Output Configuration

cl.. Balanced Output

602A

TCll21018
L Colpltla Cryotal Oacillator (Overtona Mode)

TCOll1118
b. Colpltla UC T�'* Oaclllotor
Figure 5. Oscillator Circuits

602A c. - Y UC Tank Oaclllator

April 17, 1990

474

Signetics RF Communications
Double-balanced mixer and oscillator
5.5jlH

Product specification
NE/SA602A

100k
2pF
>-l
100k 100k

0.01J'I'
1 3SK12&
~
TO SYNTHESIZER

330 11.Dnf

0.01J'I'

>-l

211818

Figure 6. Colpitts Oscillator Suitable for Synthesizer Appllcatlons and Typical Buffers

April 17, 1990

475

Signetics RF Communications
Double-balanced mixer and oscillator

Product specification
NE/SA602A

'I'Yee
6.8�F

602A

47pl;
INPUT~�0.209to0.283�H

220pF

100nF

Figure 7. Typical Appllcatlon for Cellular Radio

SFG4SSA3
~1-I

April 17, 1990

476

Signetics RF Communications
Double-balanced mixer and oscillator

Product specification
NE/SA602A

o 8.5V 6 8.0V c 4.SV

1.50+-<-+-...+....-t~+-.--+-.,...+-.....+~.............,-+-...+....-1--.-1
-40 -30 -20 -10 0 10 2D 30 40 50 60 70 80 90 TEMPERATURE oc
Figure 8. Ice vs Supply Voltage

-1 0

-1 o.s:
i-1 1.0

.- ....,...,

,, -1 1.5

ii -1~

!2 -12.5
... -13~

e ::z -13.5

m!:
...~

-1 4.ir
-1 4.o,
-1 s.u,

L .L.

.L

...n.. ~
...d"'
/'I

i! -1 5.5

-1 -1

-40 -1 7 -30 -

-10 0 10 20 311 40 50 80 70 80 80 TEMPERATURE oC

Figure 1O. Third-Order Intercept Point

RF1 = 45MHz, IF= 455kHz, RF2 = 45.06MHz
'l+-1 1-J-t-++ 3td ORDER PRODUCT
20r++-t-++-t-++-t-++-t-++...f-+-bo'lr+-i

i

1
"'~- FUND. PRODUCT ...~ �:::>-40

~
IZ

!!:

~ -80

IZ

-

-80

-40

-

0

RF INPUT LEVEL (dBm)

20

Figure 12. Third-Order Intercept and Compression

���.��~
8�.�5~

�7.�~

.......

87..u".'i . -1-1
. - v 18.i

5."-

r-

6 &JN
o 8.SV D 4.SV

5.~

4.�.

-40 14.U -30 -

-10 0

10 20 30 40 50 60 70 80 80 TEMPERATURE oC

Figure 9. Conversion Gain vs Supply Voltage

D 4.SV 4 8.0V o 8.5V

4.~ ,...,
4.~
4..._. -30 - -10 0 10 !iO 30 40 50 l!o 70 ilo 80
TEMPERATURE oC Figure 11. Noise Figure

-10

-11
1Z

-

-17 -18

4

8

7

8

10

Vcc<VOLTS)

Figure 13. Input Third-Order lntermod Point vs Vee

April 17, 1990

477

Signetics RF Communications
Double-balanced mixer and oscillator

Product specification
NE/SA612A

DESCRIPTION
The NE/SA612A is a low-power VHF monolithic double-balanced mixer with on-board oscillator and voltage regulator. It is intended for low cost, low power communication systems with signal frequencies to 500MHz and local oscillator frequencies as high as 200MHz. The mixer is a "Gilbert cell" multiplier configuration which provides gain of 14dB or more at 45MHz.
The oscillator can be configured for a crystal, a tuned tank operation, or as a buffer for an external L.O. Noise figure at 45MHz is typically below 6dB and makes the device well suited for high performance cordless phone/cellular radio. The low power consumption makes the NE/SA612A excellent for battery operated equipment. Networking and other communications products can benefit from very low radiated energy levels within systems. The NE/SA612A is available in an 8-lead dual in-line plastic package and an 8-lead SO (surface mounted miniature package).

FEATURES
� Low current consumption �Low cost � Operation to SOOMHz � Low radiated energy � Low external parts count; suitable for
crystal/ceramic filter � Excellent sensitivity, gain, and noise figure
APPLICATIONS
� Cordless telephone � Portable radio � VHF transceivers � RF data links � Sonabuoys � Communications receivers � Broadband LANs � HF and VHF frequency conversion � Cellular radio mixer/oscillator

PIN CONFIGURATION
D, N Packages

I N P U T A o � Vee

INPUT B 2

7 OSCILLATOR

GND 3

6 OSCILLATOR

OUTPUT A 4

5 OUTPUT B

ORDERING INFORMATION
DESCRIPTION 8-Pin Plastic DIP 8-Pin Plastic SO (Surface-Mount) 8-Pin Plastic DIP 8-Pin Plastic SO (Surface-Mount)

TEMPERATURE RANGE
o to +70�C o to +70�C
-40to +85�C
-40to +85�C

ORDER CODE NE612AN NE612AD SA612AN SA612AD

BLOCK DIAGRAM

September 17, 1990

478

853-0391 00446

Signetics RF Communications
Double-balanced mixer and oscillator

Product specification
NE/SA612A

ABSOLUTE MAXIMUM RATINGS

SYMBOL

PARAMETER

Vee

Maximum operating voltage

Tsm

Storage temperature

Operating ambient temperature range

TA

NE

SA

RATING 9
-65to+150
0 to +70 -40 to +85

UNIT
v oc
oc

AC/DC ELECTRICAL CHARACTERISTICS TA=25�C, Vee= SV, Figure 1

SYMBOL

PARAMETER

Vee

Power supply voltage range

DC current drain

f1N

Input signal frequency

lose

Oscillator frequency

Noise figured at 45MHz

Third-order intercept point at 45MHz

Conversion gain at 45MHz

R1N

RF input resistance

C1N

RF input capacitance

Mixer output resistance

TEST CONDITION
RF1N~45dBm
(Pin4 or5)

LIMITS

Min

Typ

Max

4.5

8.0

2.4

3.0

500

200

5.0

-13

14

17

1.5

3

1.5

UNIT
v
mA MHz MHz dB dBm dB kn pF kn

DESCRIPTION OF OPERATION The NE/SA612A is a Gilbert cell, an oscillator/buffer, and a temperature compensated bias network as shown in the equivalent circuit. The Gilbert cell is a differential amplifier (Pins 1 and 2) which drives a balanced switching cell. The differential input stage provides gain and determines the noise figure and signal handling performance of the system.

The NE/SA612A is designed for optimum low power performance. When used with the NE614A as a 45MHz cordless phone/cellular radio 2nd IF and demodulator, the NE/SA612A is capable of receiving -119dBm signals with a 12dB SIN ratio. Third-order intercept is typically -15dBm (that's approximately +5dBm output intercept

because of the RF gain). The system designer must be cognizant of this large signal limitation. When designing LANs or other closed systems where transmission levels are high, and small-signal or signal-to-noise issues not critical, the input to the NE/SA612A should be appropriately scaled.

September 17, 1990

479

Signetics RF Communications
Double-balanced mixer and oscillator

Product specification
NE/SA612A

TEST CONFIGURATION

Besides excellent low power performance well into VHF, the NE/SA612A is designed to

O.Sto 1.3�H

1 ..L

"'1::-

be flexible. The input, output, and oscillator ports can support a variety of configurations

22pF - 34.545Mltz TllRD OVERTONE CRYSTAL

provided the designer understands certain

10 Vee

constraints, which will be explained here.

8.8�F

The RF inputs (Pins 1 and 2) are biased

I�

internally. They are symmeb'ical. The

612A

150pF
~UT i 1.Sto
a 44.2�H

equivalent AC input impedance is
approximately 1.Sk II 3pF through SOMHz.
Pins 1 and 2 can be used interchangeably,
but they should not be DC biased externally.
Figure 3 shows three typical input configurations.

120pF =

The mixer outputs (Pins 4 and 5) are also

internally biased. Each output is connected to

47pF

the internal positive supply by a 1.5k'1

INPUT

2119 to 283�H

resistor, This permits direct output termination yet allows for balanced output as well. Figure

4 shows three single-ended output

100nF

configurations and a balanced output.

Figure 1. Test Configuration

The oscillator is capable of sustaining oscillation beyond 200MHz in crystal or tuned tank configurations. The upper limit of operation is determined by tank "O" and required drive levels. The higher the Q of the tank or the smaller the required drive, the higher the

permissible oscillation frequency. If the required LO. is beyond oscillation limits, or the system calls for an external L.O., the external signal can be injected at Pin 6 through a DC blocking capacitor. External L.O. should be 200mVp.p minimum to 300mVp.p maximum.

Figure 5 shows several proven oscillator circuits. Figure Sa is appropriate for cordless phones/cellular radio. In this circuit a third overtone parallel-mode crystal with approximately SpF load capacitance should be specified. Capacitor C3 and inductor L1 act as a fundamental trap. In fundamental mode oscillation the b'ap is omitted.

GND
.Figure 2. Equivalent Circuit

Figure 6 shows a Colpitts varacter tuned tank oscillator suitable for synthesizer-<:entrolled applications. It is important to buffer the output of this circuit to assure that switching spikes from the first counter or prescaler do not end up in the oscillator specb'um. The dual-gate MOSFET provides optimum isolation with low current. The FET offers good isolation, simplicity, and low current, while the bipolar circuits provide the simple solution for non-critical applications. The resistive divider in the emitter-follower circuit should be chosen to provide the minimum input signal which will assume correct system operation.

September 17, 1990

480

Signetics RF Communications
Double-balanced mixer and oscillator

612A

812A

Product specification
NE/SA612A
612A

.. Single-Ended Tuned Input

TCD21151S
b. lloloncad Input (For Attoniatlon of Second-Order Producto)
Figure 3. Input Configuration

c. Single-Ended Untuned Input

812A

CFU455
or Equivalent

L Single-Ended Coromlc Fll1lr

TCll2011S

�r+ 1ITI lf'

812A

Aller K&L 1111780 or Equlvalent
�cy matchal 3.Skn to next etage

b. Single-Ended Cryatol Aller

812A

812A

c. Slngle<nded IFT

Figure 4. Output Configuration

d.� Bolancad Output

TCD2011S

September 17, 1990

481

Signetics RF Communications
Double-balanced mixer and oscillator

Product specification
NE/SA612A

~

...c Ci!
Ci

~

F l ...c

~

I'

612A

&12A

612A

L Colpitta Crystal Oscillator (Overtone-)

b. Colpltta L/C Tank Oadllator
Figure 5. Oscillator Circuits
5.5�H

TC0211!18
c. llll'tley L/C Tank Ooclllator

100k
2pf
>-j
100k 100k

612A

5 ...__ _ _ _ _....

lOOOpFrE-----T-o DC CONTROL VOLTAGE

l . lOOOpF

FROM SYNTHESIZER

t A G.06�H

MV2105

-::

.:!,. OR EQUlVALENT

I 0.01~F
3SK126

TO SYNTHESIZER

330

0.01~

>--1

J
E------o
TO SYNTHESIZER

2Nl18

Figure 6. Colpltts Oscillator Suitable for Synthesizer Applications and Typical Buffers

September 17, 1990

482

Signetics RF Communications
Double-balanced mixer and oscillator

TEST CONFIGURATION
Vee
6.S�F ".['

O.Sto 1.3�H

l I 22pF

612A

Product specification
NE/SA612A

47pF
INPUT~0.209to0.283�H

45MHzlN

220pF

100nF

Figure 7. Typical Application for Cordless/Cellular Radio

September 17, 1990

483

Signetics RF Communications
Double-balanced mixer and oscillator

Product specification
NE/SA612A

..Ii
!Z

1 3�25 1111-r-~ r-:r:t::::i::::::i--.r-n
3.oo~ -f--+--c:!.-t-""'F--1--f--f-l--f--+--f---l-l

o
�

8.5V 6.0V

i 2.75

a 4.SV

U 2.60+-+-+--l-+--::�;.-l-""'fi...-::::...t-l---+l---t-""l-+--b-.::J

~

~

~

0.. 2.25 ,.....
iJ: r

~

~ 2.00-l--l---!:""'""""'f--l--+-+-l-+-+-+--1-l
1.75+--t--+--l-+--+--+-t-t--+--t--+--lr--l

1.60-+--t-..-+-rll--+-r-+-rl--rl-t--r-+--t-..-+~,__,._,
-40 -30 -20 -10 0 10 20 30 40 60 60 70 80 90
TEMPERATURE 0c
Figure 8. Ice vs Supply Voltage

- 1 0 .~

-10.5
e -11 .0
cg -11 .5

~ -12.~

~ -12.5

e.... -13 -13.5 ~ -14M

.;;.!..;
~

-14.s -15.o

!: -15.5

L .Li

L
.L'l Jd

_n. L.--1
L"

-16'.0-: -16 .5

-17.~ -40 -30 -20 -10 0 10 20 30 40

H
50 6070

-1-,:80 90

TEMPERATURE �C

Figure 10. Third-Order Intercept Point

RF1 = 45MHz, IF = 455kHz, RF2 = 45.06MHz

t-+++ 3rd ORDER PRODUCT

t--t--

20 H--+-H--+-H--+-H--+-t-t--Hf-+-1"'1~

. e
~
"'~-20
.~...
::I
i:-40
::I
0 !:

FUND. PRODUCT

(/_ f"'I
IL

-60 E::

IL

-60

-40

-20

0

20

RF INPUT LEVEL (dBm)

Figure 12. Third-Order Intercept and Compression

20n-r~-~~~~~~~~-r--~......-~--,

19.~'<-+---i-+--+---+--11---+--+--+-+-+--+---i---i

! 19.IH---l-+--+--+-l--+--t--+-t--+--+--lr--l 18.5'+--+--+-+--+--+---11--+--+---+-l--+--+--l

~ 18

i!i 11.s-<

i!5 �

,_-

~:~...-~

~ 1; ,,..... J..-1

A 6.0V
o 8.5V
D4.5V

81ss+--+-+--+--+---l-+--+---+-1--+--t--t--l

15Mn+:--1'--+--f---+-l--+--!--t-+--t--f---if---/

14.oj
14.un+--...--t-+-r-+-.-+-.-t-+-,.-+-.-t-~,_,_......,_,._.,.....-.-.
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 TEMPERATURE �C

Figure 9. Conversion Gain vs Supply Voltage

a.no

i

��a ~ 5.711t---t---+--l-+-+--+--+~l---+--+--+---t--

g~..5..2.

~111%

~

~

4.7

~

4� ... -~ ~

4,2.0--+--+-+-+--+---+--l-+-+--+--+-1---1

o 4.5V
A 6.0V
o 8.5V

4��1M-401---t-30--20t--r--t1~0-t-0..-+10-rl201--+3o-rl�40-t--rSo.-teo-�701---tBo.....-l.90 TEMPERATURE �C
Figure 11. Noise Figure

-111---+---+---t---+---l--t----l
I -12
~ -13 t--1Z-,L....,__t--+---+---+--+
lb -14 l---+=---+---+----+---1--+----l
i&l -15 ~61---+---+---+--+---11---+----l
-17 l----+---+---+---+---11---+----l
-18 l---+---+---+--+--1---+----1

5

6

7

8

10

Vcc(VOLTS)

Figure 13. Input Third-Order lntermod Point vs Vee

September 17, 1990

484

Signetlcs RF Communlcetions
New low-power single sideband circuits

Appllcetlon note
AN1981

Author: Robert J. Zavrell Jr.
INTRODUCTION
Several new integrated circuits now permit RF designers to resurrect old techniques of single-sideband generation and detection. The high cost of multi-pole crystal filters limits the use of the SSB mode to the most demanding applications, yet the advantages of SSB over full-carrier AM and FM are well documented (Ref 1 &2). The use of multi-pole filters can now be circumvented by reviving some older techniques without sacrificing performance. This has been made possible by the availability of some new RF and digital integrated circuits.
DESCRIPTION
Figure 1 shows the frequency spectrum of a 1OMHz full-carrier double-sideband AM signal using a 1kHz modulating tone. This well-known type of signal is used by standard AM broadcast radio stations. Full-carrier AM's advantage is that envelope detection can be used in the receiver. Envelope detection is a simple and economical technique because it simplifies receiver circuitry. Figure 2 shows the time domain "envelope" of the same AM signal.
The 1kHz tone example of Figures 1 and 2 serves as a simple illustration of an AM signal. Typically, the sidebands contain complex waveforms for voice or data communications. In the full-carrier double sideband mode (AM), all the modulation information is contained in both sidebands, while the carrier "rides along" without contributing to the transfer of intelligence. Only one sideband without the carrier is needed to effectively transmit the modulation information. This mode is called "single-sideband suppressed carrier". Because of its

reduced bandwidth, it has the advantages of improved spectrum utilization, better signal-to-noise ratios at low signal levels, and improved transmitter efficiency when compared with either FM or full-carrier AM. A finite frequency allocation using SSB can support three times the number of channels when compared with comparable FM or AM full-carrier systems.
CARRIER

LOWER>I
SID EBAN J

I UPPER SIDEBAND

9.999MHz 10.000MHz 10.001 MHz
Figure 1. Frequency Domain Display of a 1OMHz Carrier AM Modulated by a
1kHz Tone (Spectrum Analyzer Display)
I-- 1mS---!
�<>
10MHz CARRIER
Figure 2. Time Domain Display of the Same Signal Shown In Figure 1. (Oscilloscope Display)
There are three basic methods of single-sideband generation. All three use a balanced modulator to produce a double-sideband suppressed carrier signal. The undesired sideband is then re"!oved by phase and amplitude nulling (the phasing method). high Q multi-pole filters (the filter method). or a "third" method which is a derivation of the phasing technique called here the "Weaver" method for the apparent inventor. The reciprocal of the generator functions is

employed to produce sideband detectors. Generators start with audio and produce the SSB signal; detectors receive the SSB signal and reproduce the audio. Since the sideband signal is typically produced at radio frequencies, it can be amplified and applied to an antenna or used as a subcarrier.
Reproduction of the audio signal in a full-carrier AM receiver is simplified because the carrier is present. The signal envelope, which contains the carrier and the sidebands, is applied to a non-linear device (typically a diode). The effect of envelope detection is to multiply the sideband signal by the carrier; this results in the recovery of the audio waveform. The mathematical basis for this process can be understood by studying trigonometric identities.
Since the carrier is not present in the received SSB signal, the receiver must provide it for proper audio detection. This signal from the local oscillator (LO) is applied to a mixer (multiplier) together with the SSB signal and detection occurs. This technique is called product detection and is necessary in all SSB methods. A major problem in SSB receivers is the ability to maintain accurate LO frequencies to prevent spectral shifting of the audio signal. Errors in this frequency will result in a "Donald Duck" sound which can render the signal unintelligible for large frequency errors.
Theory of Single-Sideband Detection
Figures 3 through 8 illustrate the three methods of SSB generation and detection. Since they are reciprocal operations. the circuitry for generation and detection is similar with all three methods. Duplication of critical circuitry is easy to accomplish in transceiver applications by using appropriate switching circuits.

December 1991

485

Signetics RF Communications
New low-power single sideband circuits

Application note
AN1981

Figures 3 and 4 show the generation and

detection techniques employed in the filter

SINGLE SIDEBAND
....----. + SUPPRESSED CARRIER ALTER

method. In the generator a double sideband signal is produced while the carrier is eliminated with the balanced modulator. Then the undesired sideband is removed with a

BALANCED MODULAR

high Q crystal bandpass filter. A transmit mixer is usually employed to convert the SSB

Ir

signal to the desired output frequency. The

detection scheme is the reciprocal. A receive

MODULAR LO

TRANSMIT LO

mixer is used to convert the selected input frequency to the IF frequency, where the filter

Figure 3. Filter Method SSB Generator

removes the undesired sSB response. Then the signal is demodulated in the product

RFSSB INPUT

ALTER

PRODUCT DETECTOR
, _ __JI .....~~~ AUmo OUTPUT

detector. A major drawback to the filter method is the fact that the filter is fixed-tuned to one frequency. This necessitates the receive and transmit mixers for� multi-frequency operation.

Figures 5 and 6 show block diagrams of a

generator and demodulator which use the

phase method. Figure 6 also includes a

mathematical model. The input signal

RECEIVE LO

PRODUCT
DETECTOR LO

(Cos(Xt)) is led in-phase to two RF mixers where "X" is the frequency of the input signal. The other inputs to the mixers are led from a

Figure 4. Fiiter Method SSB Detector

local oscillator (LO) in quadrature (Cos(Yt) and Sin(Yt)), where "Y" is the frequency of

the LO signal. By differentiating the output of

CLOCK SIN(4yt)

one of the mixers and then summing with the other, a single sideband response is

obtained. Switching the mixer output that is

differentiated will change the selected

AUDIO INPU'TO---

90" PHASE
SHIFT

DUAL FLIP-FLOP

sideband, upper (USB) or lower (LSB). In most cases the mixer outputs will be the audio passband (300 to 3000Hz). Differentiating the passband involves a 90 degree phase shift over more than three

octaves. This is the most difficult aspect of

using the phasing method for voice band

Figure 5. Phasing Method Generator

SSB. For voice systems, difficulty of maintaining

accurate broadband phase shift is eliminated

UPPER SIDEBAND AUmOOUTPUT
-1.!COS(X+J)t

by the technique used in Figures 7 and 8. The "Weaver" method is similar to the phasing method because both require two quadrature steps in the signal chain. The

difference between the two methods is that

RF
SSB INPUT

2SIN(xt)

SIN (x+y)t + SIN(x-y)t

-COS (x+y)t - COS(x-y)

the Weaver method uses a low frequency (1.8kHz) subcarrier in quadrature rather than the broad-band 90 degree audio phase shift.

The desired sideband is thus 'folded over"

90� PHASE SllFTER (mFFERENTIATOR)

the 1.8kHz subcarrier and its energy appears between Oand 1.5kHz. The undesired

COS(YI)

sideband appears 600Hz farther away

Figure 6. Phasing Method Detector with Simplified Mathematical Model

between 2.1 and 4.8kHz. Consequently, sideband rejection is determined by a

low-pass filter rather than by phase and

amplitude balance. A very steep low-pass

response in the Weaver method is easier to

achieve than the very accurate phase and

amplitude balance needed in the phasing

December 1991

486

Signetics RF Communications
New low-power single sideband circuits

Application note
AN1981

7.2kllz LO

RFLO OFFSET BY 7.2kllzFROM RECEIVED SIGNAL

RF SSB OUTPUT

1.8 kHz LP.FILTER
Fl ure 7. Weaver Method Generator

7.2kllz LO

SUMMING AMPLIFIER

AUDIO INPUT

1.8 kHz LP.FILTER
Figure 8. Weaver Method Detector

D CK2

4xOUTPUT FREQUENCY

Figure 9. Dual Flip-Flop Quadrature Synthesis

,- - - - - - - - - - - - - - - - - - - - - -NESo2]

I

r-----------1

I

I

I

I

I

I I

I PHASE
DETECTOR _J

I

I

I

I

I

I

I

0 SINc.ot
Figure 10. PLL Quadrature Synthesis

COSrot

December 1991

487

method. Therefore, better sideband rejection is possible with the Weaver method than with the phasing method.
Quadrature Dual Mixer Circuits
One of the two critical stages in the phasing method and both critical stages in the Weaver method require quadrature dual mixer circuits. Figures 9 and 10 show two methods of obtaining quadrature LO signals for dual mixer applications. Other methods exist for producing quadrature LO signals, particularly use of passive LC circuits. LC circuits will not maintain a quadrature phase relationship when the operating frequency is changed. The two illustrated circuits are inherently broad-banded; therefore, they are far more flexible and do not require adjustment. These circuits are very useful for SSB circuits, but also can be applied to FSK, PSK, and QPSK digital communications systems.
The NE602 is a low power, sensitive, active, double-balanced mixer which shows excellent phase characteristics up to 200MHz. This makes ii an ideal candidate for this and many other applications.
The circuit in Figure 9 uses a divide-by-four dual flip-flop that generates all four quadratures. Most of the popular dual flip-flops can be used in different situations. The HEF4013 CMOS device uses very little power and can maintain excellent phase integrity at clock rates up to several megahertz. Consequently, the HEF4013 can be used with the ubiquitous 455kHz intermediate frequency with excellent power economy. For higher clock rates (up to 120MHz for up to 30MHz operation), the fast TTL 74F74 is a good choice. It has been tested to 30MHz operating frequencies with good results (>30 dB SSB rejection). At lower frequencies (SMHz) sideband rejection increases to nearly 40d8 with the circuits shown. The ultimate low frequency rejection is mainly a function of the audio phase shifter. Better performance is possible by employing higher tolerance resistors and capacitors.
The circuit in Figure 10 shows another technique for producing a broadband quadrature phase shift for the LO. The advantage of this circuit over the flip-flops is that the clock frequency is identical to the operating frequency; however, phase accuracy is more difficult to achieve. A PLL will maintain a quadrature phase relationship when the loop is closed and the VCO voltage is zero. The DC amplifier will help the accuracy of the quadrature condition by presenting gain to the VCO control circuit. The other problem that can arise is that PLL circuits tend to be noisy. Sideband noise is troublesome in both SSB and FM systems,

Signetics RF Communications
New low-power single sideband circuits

Application note
AN1981

1 Sl~9i:il
SOURCE OdBm
0-120 MHz '=

o.1~0.1�F

CK1

1------.--e--< CK2

NE5205

74F74 1K

Figure 11. FAST TTL Driver from Analog Slgnal Source Using NE5205

74F74

1so0 Q2

270" "01

s1on

..~

510.0

300

300

��~NES02

+SY

Figure 12. Interface Circuitry Between 74F74 and the NE602s

but SSB is less sensitive to phase noise problems in the LO.
Figure 11 shows a circuit that is effective for driving the 74F74, or other TTL gates, with a signal generator or analog LO. The NE5205 provides about 20dB gain with 50Q input and output impedances from DC to 450MHz. Minimum external components are required. The 1kQ resistor is about optimum for 'pulling" the input voltage down near the logic threshold. A 50Q output level of OdBm can be used to drive the NE5205 and 74F74 to 100MHz. Two NE5205s can be cascaded for even more sensitivity while maintaining extremely wide bandwidth. An advantage of using digital sources for the LO is that low-frequency power supply ripple will not cause hum in the receiver front end. This is a common problem in direct conversion designs.
Figure 12 shows the interface circuitry between the 74F74 and the NE602 LO ports. The total resistance reflects conservative current drain from the 74F74 outputs, while the tap on the voltage divider is optimized for proper NE602 operation. The low signal source impedance further helps maintain phase accuracy, and the isolation capacitor is miniature ceramic for DC isolation.
Audio Amplifiers and Switching
Using active mixers (NE602) in these types of circuits gives conversion gain, typically 1SdB. More traditional applications use passive

diode ring mixers which yield conversion loss, typically ?dB. Consequently, the detected audio level will be about 25dB higher when using the NE602. This fact can greatly reduce the first audio stage noise and gain requirements and virtually eliminate the "microphonic" effect common to direct conversion receivers. Traditional direct conversion receivers use passive audio LC filters at the mixer output and low noise, discrete JFETs or bipoiars in the first stages. The very high audio sensitivity required by these amplifiers makes them respond to mechanical vibration - thus the "microphonics" result. The conversion gain allows use of a simple op amp stage (Figure 13) set up as an integrator to eliminate ultra-sonic and RF instability. The NE5534 is well known for its low noise, high dynamic range, and excellent audio characteristics (Reference 12) and makes an ideal audio amp for the 602 detector.
The sideband select function is easily accomplished with an HEF4053 CMOS analog switch. This triple double-pole switch drives the phase network discussed in the next section and also chooses one of two amplitude balance potentiometers, one for each sideband. Figure 14 illustrates this circuit. A buffer op amp is used with the two sideband select sections to reduce THD, maintain amplitude integrity, and not change the filter network input resistance values. The gain distribution within both legs of the

receiver was found to be very consistent (within 1dB), thus the amplitude balance pots may be eliminated in less demanding applications. The NE602s have excellent gain as well as phase integrity.
Audio Phase Shift Circuits
The two critical stages for the phasing method are a dual quadrature mixer and a broadband audio phase shifter (differentiator). There are several broadband, phase shift techniques available. Figure 15 shows an analog all-pass differential phase shift circuit. When the inputs are shorted and driven with a microphone circuit, the outputs will be 90 degrees out-of-phase over the 300 to 3000Hz band. This "splitting" and phase shift is necessary for the phasing generator. For phasing demodulation the two audio detectors are fed to the two inputs. The outputs are then summed to affect the sideband rejection and audio output.
Standard 1% values are shown for the resistors and capacitors, although better gain tolerances can be obtained with 0.1% laser-trimmed integrated resistors. Polystyrene capacitors are preferred for better value tolerance and audio performance. Two quad op amps fit nicely into this application. One op amp serves as a switch buffer and the other three form a phasing section. The NE5514 quad op amps perform well for this application. Careful attention to active filter configurations can yield highly linear and very high dynamic range circuits. Yet these characteristics are much easier to achieve at audio than the common IF RF frequencies. This fact, coupled with the lack of IF tuned circuits, shielding, and higher power requirements make audio IF systems attractive indeed.
Figure 16 shows a "tapped" analog delay circuit which uses weighted values of resistors to affect the phase shift. Excellent phase and amplitude balance are possible with this technique, but the price for components is high. It should be stressed that the audio phase shift accuracy and amplitude balance are the limiting factors for SSB rejection when using the phase method; thus the higher cost may be justified in some applications.
Audio Processing
The summing amplifier is a conventional, inverting op amp circuit. It may be useful to configure a low-pass filter around this amplifier, and thus help the sharp audio filters which follow. Audio filters are necessary to shape the desired bandpass. Steep slope audio bandpass filters can be built from switched capacitor filters or from active filters

December 1991

488

Signetics RF Communications
New low-power single sideband circuits

Application note
AN1981

0.1 F

450pF 110K

TOAGURE14 CIRCUIT

RESONA NY TUNED CIRCUIT

0.1�F

+SV NE602
+SV
0.2�F

CIRCUIT FROM
AGURES 9& 12

450pF 110K

TOAGURE 14 CIRCUIT

Figure 13. Phasing Method Detector for Direct Conversion Receiver

requiring more op amps. Switched capacitor filters have the disadvantage of requiring a clock frequency in the RF range. Harmonics can cause interference problems if careful design techniques are not used. Also, better dynamic range is obtained with active filter techniques using "real" resistors although much work is being done with SCF's and performance is improving.
Direct conversion receivers rely heavily on audio filters for selectivity. Active analog or switched capacitor filters can produce the high Q and dynamic ranges necessary. Signal strength or "S-meters" can be constructed from the NE602's companion part, the NE604. The "RSSI" or "received signal strength indicator" function on the 604 provides a logarithmic response over a 90d8 dynamic range and is easy to use at audio frequencies. Finally, the AGC (automatic gain control) function can also be performed in the audio section. Attack and delay times can be independently set with excellent distortion specifications with the NE572 compandor IC. The audio-derived AGC eliminates the need

for gain controlling and RF stage, but relies on an excellent receiver front-end dynamic range. In ACSSB (Amplitude Compandored Single-Side Band) systems transmitter compression and receiver expansion are defined by individual system specifications.
Phasing-Filter Technique
High quality SSB radio specifications call for greater than 70dB sideband rejection. Using the circuits described in this paper for the phasing method, rejection levels of 35d8 are obtainable with good reliability. Coupled with an inexpensive two-pole crystal or ceramic filter, the 70d8 requirement is obtained. Also, the filtering ahead of the NE602 greatly improves the intermodulation performance of the receiver. Figure 17 shows a complete SSB receiver using the Phasing-Filter technique. The sensitivity of the NE602 allows low gain stages and low power consumption for the RF amplifier and first mixer. A new generation of low power CMOS frequency synthesizers is now available from several manufacturers including the

TDD1742 and dual chip HEF4750/51 solutions.
Direct Conversion Receiver
The antenna can be connected directly to the input of the NE602 (via a bandpass filter) to form a direct conversion SSB receiver using the phasing method. 35d8 sideband rejection is adequate for many applications, particularly where low power and portable battery operation are required. Figure 13 shows a typical circuit for direct conversion applications.
There are many other applications which can make use of SSB technology. Cordless telephones use FM almost exclusively. Eavesdropping could be greatly reduced for systems which employ SSB rather than FM. Furthermore, the better signal-to-noise ratio will extend the range, and battery life will be extended because no carrier is needed.
SSB is also used for subcarriers on microwave links and coaxial lines. Telephone communications networks that use SSB are

December 1991

489

Signetics RF Communications
New low-power single sideband circuits

Application note
AN1981

called FDM or F'requency Domain Multiplex systems. The low power and high sensitivity of the NE602 can offer FDM designers new techniques for system configuration.
weaver Method Receiver Techniques
The same quadrature dual mixer can be used for the first stage in both the phasing and Weaver method receiver. The subcarrier stage in the Weaver method receiver can use CMOS analog switches (HEF4066) for great power economy. Figure 18 shows a circuit for the subcarrier stage. A 1.SkHz subcarrier requires a 7.2kHz clock frequency. If switched capacitor filters are used for the low-pass and audio filters, a single clock generator can be used for all circuits with appropriate dividers. Furthermore, if the receiver is used as an IF circuit, the fixed LO

signal could also be derived from the same clock. This has the added advantage that harmonics from the various circuits will not interfere with the received signal.
Results
The circuit shown in Figures 13, 14, and 15 has a 10dB SIN sensitivity of 0.5�V with a dynamic range of about 80dB. Single-tone audio harmonic distortion is below 0.05% with two-tone intermodulation products below 55dB at RF input levels only 5dB below the 1dB compression point. The sideband rejection is about 38dB at a 9MHz operating frequency. The good audio specifications are a side benefit to direct conversion reoeivers. When used with inexpensive ceramic or crystal filters, this circuit can provide these specifications with >70dB sideband rejection.

Conclusions
Single sideband offers many advantages over FM and full-carrier double-sideband modulation. These advantages include: more efficient spectrum use, better signal-to-noise ratios at low signal levels, and better transmitter efficiency. Many of the disadvantages can now be overcome by using old techniques and new state-of-the-art integrated circuits. Effective and inexpensive circuits can use direct conversion techniques with good results. 35dB sideband rejection with less than 1�V sensitivity is obtained with the NE602 circuits. 70dB sideband rejection and superior sensitivity are obtained by using phasing-filter techniques. Either the phasing or Weaver methods can be used in either the direct conversion or IF section applications. The filter and phase-filter methods can be used in only the IF application.

HEF4053

2 X NE5514

BROADBAND PHASE SHIFT NETWORK RGURE 15 CIRCUIT

NE5534 DETECTOR

NE5534 DETECTOR
THETHREE SWITCH CONTROL PINS ARE TIED TOGETHER FOR ONE BIT SIDEBAND SELECT FUNTION

Figure 14. Sideband Select Switching Function

December 1991

490

Signetics RF Communications
New low-power single sideband circuits

Application note
AN1981

ANALOG SWITCH BUFFERS
INPUT A

101<.n

101<.n

10Kn

INPUT B

10Kn

10Kn

101<.Q

CLOCK
VOICE INPUT

f
~

Fl ure 15
TAPPED
...... DELAY LINE
NSAMPLES

JRETICONTA0-32

R1

R2

R3

RN-2 =R3

RN-1 =R2

RN=R1

1

WEIGHTED SUM

VOICE 900

-II
REFERENCE
CHANNEL

AXED DELAY N/2 SAMPLES
RETICON TAD-32

VOIC ED�

Figure 16. Broadband 90� Audio Phase Shilt Technique Using Tapped Delay Line (Reference 4)

1ST MIXER
FRONT END
FILTERS

DIRECT CONVERSION
PHASINGSSB RECEIVER

AUDIO ALTERS, ~ETERAND
AGC

SYNTHESIZED LO
Receivers built using this technique can exhibit excellent characteristics without resorting to expensive multi-pole filters or an IF amplttier chain.
Figure 17. Complete Phasing-Filter Receiver

December 1991

491

Signetics RF Communications
New low-power single sideband circuits
.<.120 MHz LO
CLOCK

Application note
AN1981

SSB Rf INPUT

I~

OSCILLATOR AND+512 CIRCUIT

7.2 kHz CLOCK

Figure 18. Weaver Method Receiver Concept Example for,;; 30MHz Operation

REFERENCES
1. Spectrum Scarcity Drives Land-mobile Technology, G. Stone, Microwaves and RF, May, 1983.
2. SSB Technology Fights its Way into the Land-mobile Market, B. Manz, Microwaves and RF, Aug., 1983.
3. A Third Method of Generation and Detection of Single-Sideband Signals, D. Weaver, Proceedings of the IRE, 1956.
4. Delay Unes Help Generate Quadrature Voice for SSB, Joseph A. Webb and M. W. Kelly, Electronics, April 13, 1978.

5. A Low Power Direct Conversion Sideband Receiver, Robert J. Zavrel Jr., ICCE Digest of Technical Papers, June, 1985.
6. Electronic Filter Design Handbook, Arthur B. Williams, McGraw-Hill, 1981.
7. Solid State Radio Engineering, Herbert L. Krauss, et al, Wiley, 1980.
8. ACSB-An Overview of Amplitude Compandored Sideband Technology, James Eagleson, Proceedings of RF Technology Expo 1985.
9. The ARRL Handbook for the Radio Amateur, American Radio Relay League, 1985.

10. Designing With the SA!NE602 (AN198), Signetics Corp., Robert J. Zavrel Jr., 1985.
11. RF /C's Thrive on Meager Battery-Supply Diet, Donald Anderson, Robert J. Zavrel Jr., EON, May 16, 1985.
12. Audio IC Op Amp Applications, Walter Jung, Sams Publications, 1981.
13. 2 Meter Transmitter Uses Weaver Modulation, Norm Bernstein, Ham Radio, July, 1985.

December 1991

492

Slgnetlcs RF Communications
Applying the oscillator of the NE602 in low-power mixer applications

Application note
AN1982

Author: Donald Anderson
INTRODUCTION
For the designer of low power RF systems, the Signetics NE602 mixer/oscillator provides mixer operation beyond 500MHz, a versatile oscillator capable of operation to 200MHz, and conversion gain, with only 2.5mA total current consumption. With a proper understanding of the oscillator design considerations, the NE602 can be put to work quickly in many applications.
DESCRIPTION
Figure 1 shows the equivalent circuit of the device. The chip is actually three subsystems: A Gilbert cell mixer (which provides differential input gain), a buffered emitter follower oscillator, and RF current and voltage regulation. Complete integration of the DC bias permits simple and compact application. The simplicity of the oscillator permits many configurations.
While the oscillator is simple, oscillator design isn't. This article will not address the rigors of oscillator design, but some practical guidelines will permit the designer to accomplish good performance with minimum difficulty.
Either crystal or LC tank circuitry can be employed effectively. Figure 2 shows the four most commonly used configurations in their most basic form.
a In each case the of the tank will affect the
upper frequency limits of oscillation: the higher the Q the higher the frequency. The NE602 is fabricated with a 6GHz process, but the emitter resistor from Pin 7 to ground is nominally 20k. With 0.25mA typical bias current, 200MHz oscillation can be achieved with high Q and appropriate feedback.
The feedback, of course, depends on the Q of the tank. It is generally accepted that a minimum amount of feedback should be used, so even if the choice is entirely empirical, a good trade-off between starting characteristics, distortion, and frequency stability can be quickly determined.

[II
GND
Figure 1

a. Fundamental Crystal

b. Overtone Crystal

December 1991

c. Colpitts UC Tank
493

Figure2

d. Hartley UC Tank

Signetics RF Communications
Applying the oscillator of the NE602 in low-power mixer applications

Application note
AN1982

Crystal Circuit Considerations

Crystal oscillators are relatively easy to

implement since crystals exhibit higher Q's

than LC tanks. Figure 3 shows a complete

Vee

implementation of the SA602 (extended

temperature version) for cellular radio with a

45MHz first IF and 455kHz second IF.

The crystal is a third overtone parallel mode with 5pF of shunt capacitance and a trap to suppress the fundamental.

THRD OVERTONE CRYSTAL
~~OUTPUT
T-=-

LC Tank Circuits
LC tanks present a little greater challenge for the designer. If the Q is too low, the oscillator won't start. A trick which will help if all else fails is to shunt Pin 7 to ground with a 22k resistor. In actual applications this has been effective to 200MHz with high Q ceramic capacitors and a tank inductor of 0.08mH and a Q of 90. Smaller resistor value will upset DC bias because of inadequate base bias at the input of the oscillator. An external bias resistor could be added from VCC to Pin 6, but this will introduce power supply noise to the frequency spectrum.
The Hartley configuration (Figure 2D) offers simplicity. With a variable capacitor tuning the tank, the Hartley will tune a very large range since all of the capacitance is variable. Please note that the inductor must be coupled to Pin 7 with a low impedance capacitor. The Colpitts oscillator will exhibit a smaller tuning range since the fixed feedback capacitors limit variable capacitance range; however, the Colpitts has good frequency stability with proper components.
Synthesized Frequency Control
The NE602 can be very effective with a synthesizer if proper precautions are taken to minimize loading of the tank and the introduction of digital switching transients into the spectrum. Figure 4 shows a circuit suitable for aircraft navigation frequencies (108-118MHz)with 10.7MHz IF.
The dual gate MOSFET provides a high degree of isolation from prescaler switching spikes. As shown in Figure 4, the total current consumption of the NE602 and 3SK126 is typically 3mA. The MOSFET input is from the emitter of the oscillator transistor to avoid loading the tank. The Gate 1 capacitance of the MOSFET in series with the 2pF coupling capacitor adds slightly to the feedback capacitance ratio. Use of the 22k resistor at Pin 7 helps assure oscillation without upsetting DC bias.
For applications where optimum buffering of the tank, or minimum current are not mandatory, or where circuit complexity must be minimized, the buffers shown in Figure 5 can be considered.

47pF~-e---=i
INPUT~0.209to0.283�H

44.9MHz 220pF

100nF

Figure 3. Cellular Radio Application
The effectiveness of the MRF931 (or other VHF bipolar transistors) will depend on frequency and required input level to the prescaler. A bipolar transistor will generally provide the least isolation. At low frequencies the transistor can be used as an emitter follower, but by VHF the base emitter junction will start to become a bidirectional capacitor and the buffer is lost.
The 2N5484 has an IDSS of 5mA max. and the 2SK126 has IDSS of 6mA max. making them suitable for low parts count, modest current buffers. The isolation is good.
Injected LO
If the application calls for a separate local oscillator, it is acceptable to capacitively-couple 200 to 300mV at Pin 6.
Summary
The NE602 can be an effective low power mixer at frequencies to 500MHz with oscillator operation to 200MHz. All DC bias is provided internal to the device so very compact designs are possible. The internal bias sets the oscillator DC current at a relatively low level so the designer must choose frequency selective components which will not load the transistor. If the guidelines mentioned are followed, excellent results will be achieved.

December 1991

494

Signetics RF Communications
Applying the oscillator of the NE602 in low-power mixer applications

Application note
AN1982

Vee
6.8�Fi

0.08�H

llV2105 OR EQUIV

Vee
TO PRESCALER

12pF" 2-10pF

FROll SYNTH LOOP
FILTER

NOTES:

llV2105 OREQIV

�Permits Impedance match of NE602 output. I.e.: 1.Sk filter Impedance. *" Chooae for Impedance match to next stage.

Flgure4

2K"

2pF

0.01

@--J(-.....---t-e--Jt--;O

0.01

e--e---t lr--i>---t1f"-

0---11-----t-7---I

~~E

PRESCALER

47K

llRF931
NOTES: � 2k or �� neceuary for current llmlta or preecaler Impedance match.

2N5484
Figures

3SK126

December 1991

495

Slgnetics RF Communications
FM front-end IC

Preliminary specification
TDA1574

GENERAL DESCRIPTION
The TOA 1574 is a monolithic integrated FM tuner circuit designed for use in the r.f./i.f. section of car radios and home-receivers. The circuit comprises a mixer, oscillator and a linear i.f. amplifier for signal processing, plus the following additional features.

Features
� Keyed automatic gain control (a.g.c.) � Regulated reference voltage � Buffered oscillator output � Electronic standby switch � Internal buffered mixer driving

QUICK REFERENCE DATA

Supply voltage range (pin 15) Mixer input bias voltage (pins 1 and 2)
noise figure Oscillator output voltage (pin 6)
output admittance at pin 6 for f = 108,7 MHz Oscillator output buffer
O.C. output voltage (pin 9) Total harmonic distortion Linear i.f. amplifier output voltage (pin 10)
noise figure at Rs = 300 U Keyed a.g.c. output voltage range (pin 18)

Vp V1,2-4 NF V5-4 Y22
V94 THO V1Q-4 NF V1g.4

7 to 16 V

typ.

1 v

typ.

9 dB

typ.

2 v

typ. 1,5 + j2 ms

typ.

6 v

typ.

-15 dBC

typ.

4,5 v

typ.

6,5 dB

+ 0,5 to Vp-0,3 V

February 1985

496

~

2
~
~
"'

100 rr

a.g.c. output

10 rr
.---~~~~~;-~~~c:=:::J-~~~~~~~~~~~~~o--~~~+Vp

r

-RM~ L 32 00UN1 VM out 68 rr

150pF

I10nF

.l 22 nF

! 22 nF

a.g.c. narrowband information
VF

standby switch

.....
-0
::J
-I
CD
a::J.

18

17

16

15

14

13

300 rr

t 12

11

~ ,~ ,r I n I 3oF on 1100 I '

IliIn.eaarmpi;fi"

(")

R

output

l.F. AMPLIFIER

I STANDBY
SWITCH

I ~L 300U

TDA1574

J:

1 nF

buffered

>---c::i-------J-------+ oscillator

output

.t.E.,

EMF1 f = 98 MHz

6,8 pF

Coil data
L 1: TOKO MC.108, 514HNE 150014514; L , 0,078 �H L2: TOKO MC� 111, E516HNS�200057; L , 0,08 �H L3: TOKO coil set 7P, Nl , 5,5 + 5,5 turns, N2, 4 turns

REFERENCE VOLTAGE

�2 6,8 pF

~ 1nF R52 sou

m;

EMF2 f=98MHz

Fig. 1 Block diagram and test circuit.

' - - - - - - - - - ' 7Z90311.2

-a

~

-i 0
.)..>...
01

:~;r�
~
i

" ~ .j:>.

0

:0

Signetics RF Communications
FM front-end IC

Preliminary specification
TDA1574

FUNCTIONAL DESCRIPTION
Mixer The mixer circuit is a double balanced multiplier with a preamplifier (common base input) to obtain a large signal handling range and a low oscillator radiation.

Oscillator The oscillator circuit is an amplifier with a differential input. Voltage regulation is achieved by utilizing the symmetrical tanh-transfer-function to obtain low order 2nd harmonics.

Linear IF amplifier The IF amplifier is a one stage, differential input, wideband amplifier with an output buffer.

Keyed AGC
The AGC processor combines narrow- and wideband information via an RF level detector, a comparator and an AN Ding stage. The level dependent, current sinking output has an active load, which sets the AGC threshold. The AGC function can either be controlled by a combination of wideband and narrowband information (keyed AGC), or by a wideband information only, or by narrowband information only. If only narrowband AGC is wanted pin 3 should be connected to pin 5. If only wideband AGC is wanted pin 12 should be connected to pin 13.

RATINGS

Limiting values in accordance with the Absolute Maximum System (I EC 134)

Supply voltage (pin 15)

Vp = V 15-4

Mixer output voltage (pins 16 and 17)

v16, 17-4

Standby switch input voltage (pin 11)

V11-4

Reference voltage (pin 5)

V5_4

Field strength input voltage (pin 12)

V12-4

Total power dissipation

Ptot

Storage temperature range

Tstg

Operating ambient temperature range

Tamb

max. max. max. max. max.

18 v 35 v 23 v 7 v 7 v

max. 800 mW

-55 to+ 150 oc

-40 to + 85 �c

THERMAL RESISTANCE From junction to ambient (in free air)

Rth j-amb

80 K/W

Note All pins are short-circuit protected to ground.

February 1985

498

Signetics RF Communications
FM front-end IC

Preliminary specification
TDA1574

CHARACTERISTICS Vp = V 15-4 = 8,5 V; Tamb = 25 oc; measured in test circuit Fig. 1; unless otherwise specified

parameter

symbol

min. typ. max. unit

Supply (pin 15) Supply voltage Supply current (except mixer) Reference voltage (pin 5)

Vp = V15_4 7

-

16

v

Ip= 115

16 23 30

mA

V5_4

3,9 4, 1 4,4

v

Mixer D.C. characteristics Input bias voltage (pins 1 and 2) Output voltage (pins 16 and 17) Output current (pin 16 +pin 17)

V1,2-4

-

1

-

v

V15, 17-4

4

-

35

v

115+ 117

-

4,0 -

mA

A.C. characteristics (ti = 98 MHz)

Noise figure

Noise figure including transforming network

3rd order intercept point

Conversion power gain

4 (VM(out) 10,7 MHz) 2 Rs1

101og

x-

(EMF1 98 MHz) 2

RML

Input resistance (pins 1 and 2)

Output capacitance (pins 16 and 17)

NF

-

NF

-

EMF1 IP3

-

9

-

11 -

115 -

Gp
R1,2-4 C16, 17

-

14 -

-

14 -

-

13 -

dB dB dB�V
dB
n
pF

Oscillator D. C. characteristics Input voltage (pins 7 and 8) Output voltage (pin 6)

v7,8-4

-

1,3 -

v

V5_4

-

2

-

v

A.C. characteristics (fosc = 108,7 MHz)

Residual FM (Bandwidth 300 Hz to 15 kHz);

de-emphasis = 50 �s

bot

-

2,2 -

Hz

February 1985

499

Signetics RF Communications
FM front-end IC

Preliminary specification
TDA1574

parameter

symbol

min.

typ.

max.

unit

Linear i.f. amplifier

D.C. characteristics

I,

Input bias voltage (pin 13)

V13-4

-

1,2

-

v

Output voltage (pin 10)

V10_4

-

4,5

-

v

A.G. characteristics (fi = 10,7 MHz) Input impedance
Output impedance
Voltage gain

R14-13

240

300

360

n

C14-13

-

13

-

pF

R10_4 C10_4

240

300

360

n

-

3

-

pF

20 lo V10-4 gV14-13

Gv1F

27

30

-

dB

T amb = -40 to + 85 oc

AGVIF

-

0

-

dB

1 dB compression point (r.m.s. value)

at Vp = 8,5 V atVp = 7,5 V

V10-4rms

-

750

-

mV

V10-4rms

-

550

-

mV

Noise figure

at Rs= 300 n

NF

-

6,5

-

dB

Keyed a.g.c.
D. c_ characteristics
Output voltage range (pin 18) A.G .C. output current
at 13 =�or V 12-4 = 450mV;V18-4 = Vp/2
at V3-4 = 2 V and V12-4 = 1 V; V18-4 = V15_4

V18-4 -113 113

0,5

-

Vp-0,3 v

25

50

100

�A

2

-

5

mA

February 1985

500

Signetics RF Communications
FM front-end IC

Preliminary specification
TDA1574

CHARACTERISTICS (continued)

parameter

symbol

min.

typ. max. unit

Narrowband threshold at V3.4 = 2 V; V12.4 = 550 mV at V3.4 = 2 V; V12.4 = 450 mV

V18-4

-

-

1

v

V18-4

Vp-0,3 -

-

v

A.G. characteristics (fi = 98 MHz)

Input impedance

R3.4

-

C3_4

-

Wideband threshold (r.m.s. value) (see figures 2, 3, 4 and 5)

at V12-4 = 0,7 V; V18-4 = Vp/2; 118 = 0 EMF2rms

-

4

-

kn

3

-

pF

17

-

mV

Oscillator output buffer (pin 9) D.C. output voltage Oscillator output voltage (r.m.s. value)
at RL = oo; CL= 2 pF
n at RL = 75
D.C. output impedance Signal purity Total harmonic distortion Spurious frequencies
n at EMF1 = 0,2 V; Rs1 = 50

V9-4

-

V9.4(rms)

-

V9-4(rms)

30

R9.15

-

THD

-

fs

-

6,0 -

v

110 -

mV

50

-

mV

2,5

-

kn

-15 -

dBC

-35 -

dBC

Electronic standby switch (pin 11)

Oscillator; linear i.f. amplifier; a.g.c.

at Tamb = -40 to + 85 oc

Input switching voltage

for threshold ON; V 18-4 =;;:;, Vp-3 V

V11-4

0

for threshold OFF; V 18-4 = .;; 0,5 V

v,,_4

3,3

Input current

at ON condition; V 11-4 = 0 V at OFF condition; V 11-4 = 23 V

-111

-

I 11

-

Input voltage

at11 1 =<1>

v,,_4

-

-

2,3

v

-

23

v

-

150

�A

-

10

�A

-

4,4

v

February 1985

501

Signetics RF Communications
FM front-end IC
7290310
10.---~.-~~~---,-~~~~~~,
V18-4 IV)

Preliminary specification
TDA1574
10.---~.-~~~---,-~~.-~,7-Z9_0_3007 v18-4
(V)

oL-~..J_~_[_~_J_~=='~~"====="

0

10

20

30 �

V3_4 (mV)

Fig. 2 Keyed a.g.c. output voltage V 18-4
as a function of r.m.s. input voltage V3_4. Measured in test circuit Fig. 1
at v 12_4 = 0,7 V; 118 = �.

118
(mA) 4 3
0 0

7290308

i 1
u ]
I/

10

?0

30

v3 _ 4 (mV)

Fig. 4 Keyed a.g.c. output current I 18 as a function of r.m.s. input voltage V3_4. Measured in test circuit Fig. 1 at V12-4 = 0,7 V; V18-4 = 8,5 V.

OL-~..J_~_[_~=:;,~~>==~�=~~

400

500

600

700

V12-4 (mV)

Fig. 3 Keyed a.g.c. output voltage V 18-4 as a function of input voltage V 12-4� Measured in test circuit Fig. 1 at V3_4=2V;118 = �.

7 290309
5,-~-,-~-.--~--.~~.-~.-~-
118
(mA)

500

600

700

V12-4 (mV)

Fig. 5 Keyed a.g.c. output current I 18
as a function of input voltage V 12-4� Measured in test circuit Fig. 1
at V3_4 = 2 V; V18-4 = 8,5 V.

February 1985

502

"J1

CT

2

� ~

10!l
r - - - - - , - - - - - - , r - - - - - - - - - - t - - - C : = J - - - - - - - - - - - - - - + - - - + V 8,5V

"' APPLICATION INFORMATION

OJ

IO,l�F

01

10 nF a.g.c.

I

narrowband information

standby switch LOW for FM ON

-IsI:
...,
0
:..:.J.. I

VF(1l

CD

:a:J.

17

16

15

14

13

~--------'

JOOn

l.F.

18

AMPLIFIER

12

11

(")

Joan
10

!OHO!-+ SFE

linear

i,f, omp1;1;.,

~

ootpot

STANDBY SWITCH

Coil data
Ll: TOKO MC�108, 514HNE�15023S15, Nl = 5,5 turns, N2 = 1 turn
� LL2J:: see F'19. 1

TDA1574

1 nF

buffered

>-------CJ---t-r-r-+ oscillator
output

0AL

(foscl

.;,,75!l

(1) Field strength indication of main i.f. amplifier.

REFERENCE VOLTAGE

1,SpF

r10nF

L2

antenna

+VP

a.g.c.

GAIN CONTROLLED RF PRESTAGE

5,Gkn

7Z90312.2

~--------+----------------------.._---+-- tuning voltage

" i

-I 0
)...>..
01

~j' 5'
~
~"'

'-I
.j:>.

~

0 ::>

Signetics RF Communications
Integrated FM tuner for radio receivers

Preliminary specification
TDA1574T

GENERAL DESCRIPTION
The TOA 1574T is an integrated FM tuner circuit designed for use in the RF /IF section of car radios and home-receivers. The circuit contains a mixer and an oscillator and a linear IF amplifier for signal processing. The circuit also incorporates the following features.

Features
� Keyed Automatic Gain Control (AGC) � Regulated reference voltage � Buffered oscillator output � Electronic standby switch � Internal buffered mixer driving

QUICK REFERENCE DATA

parameter

conditions

symbol min. typ.

max.

unit

Supply voltage range (pin 17)

Vp

7

-

14

v

Mixer input bias voltage (pins 1 and 2)
Noise factor

V1,2-4 -

1

-

v

NF

-9

-

dB

Oscillator output voltage (pin 6)

V5_4

-

2

-

v

Output admittance at pin 6 f = 108.7 MHz Y22

-

1.5 + j2

ms

Osei llator output buffer DC output voltage (pin 9)

V9_4

-

6

-

v

Total harmonic distortion

THO

-

-15

-

dB

Linear IF amplifier output

voltage (pin 12)

V12-4

-

4.5

-

v

Noise factor

Rs= 300 n

NF

-

6.5

-

dB

Keyed AGC output voltage range (pin 20)

V20.4

0.5 -

Vp-0.3 v

February 1965

504

Signetics RF Communications
Integrated FM tuner for radio receivers

Preliminary specification
TDA1574T

100 u

I

20

EMF 1 I= 98 MHz

82 pf 19

10 u

J;onF

from tFfilter
l22nF

!22nF

AGC narrowband 1nlormat1on
v,

standby switch threshold
supply voltage

"

17

16

15

14

13

300 u

300 U 12 22 nF

linear

C>---J----t--c=:::l-:+--it IF omp"f'e'

output

IF AMPLIFIER
1---~o-------,--_,

STANDBY SWITCH

R

0 ll

11
TDA1574T

1 nF

butlered

T~~~~~~tor

"'~""

REFERENCE VOLTAGE

6 8 pf

~!of "s2 50 u

,

EMF 2 I= 98 MHz

10 7Z24461.2

Coil data L 1: TOKO MC-108, 514HNE-150023S14; L = 0.078 �H L2: TOKO MC-111, E516HNS-200057; L = 0.08 �H
L3: TOKO Coil set 7P, N 1 = 5.5 + 5.5 turns, N2 = 4 turns
Fig.1 Block diagram and test circuit.

February 1985

505

Signetics RF Communications
Integrated FM tuner for radio receivers

Preliminary specification
TDA1574T

PINNING

1. Mixer input 1

2. Mixer input 2

AGC

3. Wideband information input

MX02

4. Ground

,,,

5. Voltage reference

MX01

6. Osei Ilater output

7. Oscillator input 1

VP

8. Oscillator input 2

IFl2 TOA 1574T
IFl1

9. Buffered oscil later output 10. Not connected 11. Not connected

NBI

12. IF output

13. Standby switch

STB

14. Narrowband information input

IFO

15. IF input 1

16. IF input 2

n.c

17. Supply voltage

7Z24460

18. Mixer output 1

19. Mixer output 2

Fig.2 Pinning diagram.

20. AGC output

FUNCTIONAL DESCRIPTION Mixer The mixer circuit uses a double balanced multiplier with a preamplifier (common base input) in order to obtain a large signal handling range and low oscillator radiation.

Oscillator
The oscillator circuit uses an amplifier with a differential input. Voltage regulation is achieved by utilizing the symmetrical tan h-transfer-function to obtain low order 2nd harmonics.

Linear IF amplifier The IF amplifier is a one stage, differential input, wideband amplifier with an output buffer.

Keyed AGC
The AGC processor combines narrow and wideband information via an RF level detector, a comparator and an AN Ding stage. The level dependent current sinking output has an active load which sets the AGC threshold. The AGC function can either be controlled by a combination of wideband and narrowband information (keyed AGC) or by a wideband/narrowband information only. If narrowband AGC is required pin 3 should be connected to pin 5. If wideband AGC is required pin 14 should be connected to pin 15.

February 1985

506

Signetics RF Communications
Integrated FM tuner for radio receivers

Preliminary specification
TDA1574T

RATINGS Limiting values in accordance with the Absolute Maximum System (IEC 134)

parameter

conditions

symbol

min.

max.

Supply voltage (pin 17) Mixer output voltage
(pins 18and 19) Standby switch input voltage
(pin 13) Reference voltage (pin 5) Total power dissipation Storage temperature range Operating ambient temperature range
THERMAL RESISTANCE From junction to ambient (in free air)

V17_4

-

vlB,19-4 -

V13.4 V5_4 Ptot Tstg Tamb

-
-
-55 -40

14
35
23 7 500
+ 150 + 85

Rth j-a

unit v
v
v v mW oc oc
95 K/W

February 1985

507

Signetics RF Communications
Integrated FM tuner for radio receivers

Preliminary specification
TDA1574T

CHARACTERISTICS
Vp = V17_4 = 8.5 V; Tamb = 25 �c; measured in test circuit Fig.1; Al I measurements are with respect to ground (pin 4); unless otherwise specified

parameter

conditions

symbol

min. typ. max. unit

Supply (pin 17) Supply voltage Supply current
(except mixer) Reference voltage (pin 5)
Mixer DC characteristics Input bias voltage
(pins 1 and 2) Output voltage
(pins 18 and 19) Output current
(pins 18 and 19)
AC characteristics Noise figure Noise figure including
transforming network 3rd order intercept point Conversion power gain Input resistance
(pins 1 and 2) Output capacitance
(pins 18 and 19)
Oscillator DC characteristics Input voltage
(pins 7 and 8)
Output voltage (pin 6)
AC characteristics Residual FM (bandwidth=
300 Hz to 15 kHz)

Vp = V17 Ip= 117

V17

7

-

14 v

117

16 23 30 mA

V5

4.0 4.2 4.4 v

fi=98MHz note 1

V1,2

-

vrn,19

4

113 + 19 -

1

-

v

-

35 v

4.5 -

mA

NF

-

NF

-

EMF11p3 -

Gcp

-

R1,2

-

c18,19

-

9

-

11

-

115 -

14 -

14 -

13 -

dB
dB dB/�V dB
n
pf

V7,8 V5

-

1.3 -

v

-

2

-

v

de-emphasis= 50 �s .:lf

-

2.2 -

Hz

Linear IF amplifier DC characteristics Input bias voltage (pin 15)

V15

-

1.2 -

v

February 1985

508

Signetics RF Communications
Integrated FM tuner for radio receivers

Preliminary specification
TDA1574T

CHARACTERISTICS (continued)
parameter
Output voltage (pin 12)
AC characteristics
Input impedance
Output impedance
Voltage gain Voltage gain with
variation of temperature
1 dB compression point (RMS value) at Vp = 8.5 V at Vp = 7.5 V
Signal-to-noise ratio
Keyed AGC DC characteristics Output voltage range
(pin 20) AGC output current
at 13 = 0 or V14 = 450 mV; V20 = Vp/2 at V3 = 2 V and V14=1V;V20=V15 Narrowband threshold atV3=2V;V14=550mV atV3=2V;V14=450mV
AC characteristics
Input impedance

conditions

symbol

min.

V12

-

fi = 10.7 MHz

R 16-15

240

C15.15

-

R12

240

C12

-

note 2

Gv

27

Tamb = -40

to+ 85 oc

LlGr

-

typ. max.

unit

4.5 -

v

300 360

.n

13 -

pF

300 360

.n

3

-

pF

30

-

dB

0

-

dB

Rs= 300 .n

V12(rms) -
V 12(rms) -

S/N

-

750 -

mV

550 -

mV

6.5 -

dB

LlV20

0.5

-

Vp-0.3 v

-120
120
V20 V20
fi = 98 MHz R3 C3

25

50 100

�A

2

-

5

mA

-

-

1

v

Vp-0.3 -

-

v

-

4

-

kil

-

3

-

pF

February 1985

509

Signetics RF Communications
Integrated FM tuner for radio receivers

Preliminary specification
TDA1574T

parameter

conditions

symbol

min. typ. max. unit

Wideband threshold (RMS value) (see Figs 3, 4, 5 and 6) at V14 = 0.7 V; V20 = Vp/2; 120 = 0

EMF2(rms) -

17 -

mV

Oscillator output buffer (pin 9)
DC output voltage
Oscillator output voltage (RMS value) atRL=oo;CL=2pF
at RL = 75 n
DC output resistance
Signal purity
Total harmonic distortion
Spurious frequencies at EMFl = 1 V; Rs1=50il

V9

-

6

-

v

V9(rms)

-

110 -

mV

V9(rms)

30

50

-

mV

R9-17

-

2.5 -

kil

THO ts

-

-15 -

dB

-

-35 -

dB

Electronic standby switch (pin 11)
Oscillator; linear IF amplifier; AGC
Input switching voltage for threshold ON for threshold OFF
Input current at ON condition at OFF condition
Input voltage

Tamb = -40 to+ 85 oc

V20 = > Vp-3 V V13

V20= <0.5 V

V13

V13 = 0 V V13 = 23 V
113 = 0

-113 -113
V13

0

-

3.3 -

-

-

-

-

-

-

2.3 v

23

v

150 �A

10

�A

4.4

v

Notes to the characteristics 1. Power gain conversion is equated by the following equation:

4 (VM(out) 10.7 MHz) 2 Rs 1

10 log

x -

(EMF1 98 MHz) 2

RML

2. Voltage gain is equated by the following equation:

V12 201og--
V15.15

February 1985

510

Signetics RF Communications
Integrated FM tuner for radio receivers

10 V20-4
(V)
a
6
4

7Z24459

10 V20-4
(VI
a
6
4

Preliminary specification
TDA1574T
7Z24456

OL_~_J_~_J_~__J---"~"'=~""=~-

0

10

20

30

v3 _ 4 (mV)

Fig.3 Keyed AGC output voltage V20 as a function of RMS input voltage V3.
Measured in test circuit Fig.1 at V14 = 0.7 V; 120 = 0.

..... ..... QL_~_J_~_J_--"=,,,..,,,,,,,,,~,.,,,,~

~

400

500

600

700

v14_ 4 (mV)

Fig.4 Keyed AGC output voltage V20 as a function of input voltage V 14� Measured in test circuit Fig.1 at V3 = 2 V; 120 = 0.

5 120
(mA) 4
3
0 0

7Z24457

i
j

d
I/

10

20

30

v3 _ 4 (mV)

Fig.5 Keyed AGC output current I20 as a
function of RMS input voltage V3.
Measured in test circuit Fig.1 at V 14 = 0.7 V; V20 = 8.5 V.

7Z24458
5~~~~~~~~~~~.,--~-,
120
(mA)

O'=="""'"""~""'-~--'~~-'-~-'-~--'

400

500

600

700

v14 _4 (mV)

Fig.6 Keyed AGC output voltage 120 as a function of input voltage V 14� Measured in test circuit Fig.1 at V3 = 2 V; V20 = 8.5 V.

February 1985

511

Signetics RF Communications
Integrated FM tuner for radio receivers

Preliminary specification
TDA1574T

i.
TDA1574T
Jr----;=:r--r----t-'"-F-l~ oscillator
AL ,(.J,, 75 U

IQOkll
GAIN CONTROLLED RF PRESTAGE L__ _ _ _ _ __.__ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___._ _ _ _ _ _ 1unong voltage

Coil data

L 1: TOKO MC-108, N 1 = 5.5 turns, N2 = 1 turn

LL32

::

\
1

see

F'1g. 1

(1) Field strength indication of main IF amplifier.

Fig.7 TDA1574T application diagram.

February 1985

512

Slgnetlcs RF Communications
TV VHF mixer/oscillator UHF preamplifier

Preliminary specification
TDA5030A

GENERAL DESCRIPTION
The TDA5030A provides VHF local oscillator, VHF mixer and UHF IF preamplifier functions for VHF/UHF television receivers. It includes a buffered output from the VHF local oscillator, a VHF/UHF switching circuit and an IF amplifier stage for an external SAW filter.

Features � Balanced VHF mixer � Voltage-controlled VHF local oscillator � IF amplifier for SAW filter � UHF IF preamplifier � Local oscillator buffer output for external prescaler � Voltage stabilizer � UHF/VHF switching circuit � Electrostatic discharge protection diodes at pins 10, 11, 12 and 13

QUICK REFERENCE DATA

parameter
Supply voltage Supply current VHF mixer frequency range Conversion gain Conversion noise Input signa I for
1% cross modulation Storage temperature range Operating ambient
temperature range

conditions pin 15

symbol
Vp Ip f

300 MHz

Tstg Tamb

min.
10
50
-
-

typ.
42
-
24,5 10

max.
13,2
-
470 -
-

unit
v
mA MHz dB dB

-

99

-55 -

+ 125

dB�V oc

-25 -

+ 85

oc

June 1986

513

Signetics RF Communications
TV VHF mixer/oscillator UHF preamplifier

Preliminary specification
TDA5030A

18

16

VHF LOCAL OSCILLATOR

VHF MIXER

15
TDA5030A

BUFFERED

13

OSCILLATOR

OUTPUT

11

SAW FILTER

IF AMPLIFIER

10

5 UHF IF

4

PREAMPLIFIER

3, 14 17

7 6

8 9

STABILIZER
AND
SWITCH
12 7Z92276.2

Fig. 1 Block diagram.

RATINGS Limiting values in accordance with the Absolute Maximum System (I EC 134)

parameter

conditions

symbol

min. max.

Supply voltage Input voltage V HF switching vo Itage Output current
Short-circuit time on outputs
Storage temperature range
Operating ambient temperature range
Junction temperature range

pin 15

Vp = V15_3 -

pins 1, 2, 4 and 5 Vi

0

pin 12 pins 10, 11 or 13

V12

0

-110, 11, 13 -

14 5 V15+0,3 10

pins 10 and 11

tss

-

10

Tstg

-55 + 125

Tamb

-25 + 85

Tj

-

+ 125

THERMAL RESISTANCE From junction to ambient

Rthj-a

unit
v v v
mA
s oc
oc
oc
55 K/W

June 1986

514

Signetics RF Communications
TV VHF mixer/oscillator UHF preamplifier

Preliminary specification
TDA5030A

CHARACTERISTICS
Measured in circuit of Fig. 2, Vp = V 15-3 = 12 V, Tamb = 25 �c, unless otherwise specified

parameter

conditions

symbol

min. typ. max.

unit

Supply Supply voltage Supply current Switch voltage level
for VHF Switch voltage level
for UHF Switch current

pin 15
pin 12 pin 12 UHF selected

V15-3 I 15
V12
V12 112

10

-

-

42

0

-

9,5 -

-

-

13,2

v

55

mA

2,5

v

V15+0,3 v

0,7

mA

VHF mixer (including IF amplifier)

Frequency range

Noise factor

pin 2 f= 50 MHz f = 225 MHz f= 300 MHz f = 470 MHz

Optimum source conductance

pin 2 f= 50 MHz f = 225 MHz f=300MHz

Input conductance

pin 2 f= 50 MHz f= 225 MHz f= 300 MHz

Input capacitance

pin 2 f= 50 MHz

Input voltage for 1% cross-modulation (in channel)

Input voltage for 10 kHz pulling (in channel)

f < 300 MHz

Voltage gain

f
F F F F
G G G
G�I Gi Gi
Ci
V2-3
V2-14 Av

50

-

470

-

7,5

9

-

9

10

-

10

12

-

11

13

-

0,5

-

-

1,1

-

-

1,2

-

-

0,23 -

-

0,5

-

-

0,67 -

-

2,5

-

97

99

-

100 -

-

22,5 24,5 26,5

MHz
dB dB dB dB
ms niS mS
mS ms ms
pF
dB�V
dB�V dB

June 1986

515

Signetics RF. Communications
TV VHF mixer/oscillator UHF preamplifier

Preliminary specification
TDA5030A

CHARACTERISTICS (continued)

parameter

conditions

I
UHF preamplifier (including IF amplifier)

Input conductance

pin 5

Input capacitance

pin 5

Noise factor

pin 5

Optimum source conductance

pin 5

Input voltage for 1% cross-modulation (in channel)

Voltage gain

symbol
Gi C�I F G
V5_14 Av

min.
-
-
-
88 31,5

VHF mixer Conversion
transadm ittance
Output impedance

pins 2 to 6,7

Yc2-6,7

-

pins 6 and 7

Zo

-

VHF oscillator

Frequency range

f

70

Frequency shift

AVp = 10%;

f = 70-330 MHz Af

-

Frequency drift

AT=15K;

f = 70-330 MHz Af

-

Frequency drift

between 5 s and

15 min after

switch-on

Af

-

SAW filter IF amplifier Input impedance
Transimpedance Output reflection
coefficient: modulus phase

Z10, 11 = 2 kil; f=36MHz

Zs,9

-

Zs, 9-10, 11 -

f = 36 MHz

0,45 -63

typ. max.

0,3

-

3,0

-

5

6

3,3

-

90

-

33,5 35,5

5,7

-

1,6

-

-

520

-

200

-

250

-

200

30o+ j100

-

2,2

-

0,37 0,41 -112 -134

unit
ms pf dB mS
dB�V dB
ms kil
MHz kHz kHz
kHz
n
kil
deg

June 1986

516

Signetics RF Communications
TV VHF mixer/oscillator UHF preamplifier

Preliminary specification
TDA5030A

parameter

conditions

I
VHF local oscillator output buffer

Output voltage

pin 13
RL = 75 n
f< 100 MHz

f> 100 MHz

Output impedance

f = 100 MHz

RF signal on local oscillator output

RL = 75 n

Vi= 1 V; f,;;;225MHz

Vi=0,3V; f = 225-300 MHz

IF signal on local oscillator output

UHF selected;
RL = 75 n;
Vi=350mV

Local oscillator harmonics w.r.t. local oscillator output signal

RL = 75 n

symbol

min. typ.

V13

14

20

V13

10

20

Z13

-

90

RF/(RF+LO) -

-

RF/(RF+LO) -

-

IF/(IF+LO)

-

-

-

-

max. unit

-

mV

-

mV

-

n

10

dB

10

dB

3

mV

-14 dB

June 1986

517

cc.:..
::>
(I)
'�OJ
(J)

UHF/VHF

Vt

Vp

switch

:c

-< I

::>
(I)
B�

< :"0'

I

Tl ()

"Tl

0
3

3x�

3c: :c:>;�

~
OJ

"~kU
:~~6An482 F

.J. T

869096 47kU

82pF

IN750 I

r,.11,8 1,81

11nF
I

11nF
I

18U

I i nF
18 17 16 15 14 13 12 11 10 TDA5030A

1Jr .. 11nF

local oscillator output
'
~.

aCD-
(/)

aer
::>
"'

Q.

~
0.....
c
I
"Tl

"..O...
CD
~
3 "2.
:::;:;
C...i.)."

VHF input

1 nF
' I

IF input

1 nF
' I

34 56 78 9 .J..
J:

(1)

(2)

7Z96391

(1) c = 18 pF, L = 2,2 �H, fcL = 36,5 MHz.
(2) Turns ratio = 7 : 1, load = 50 n.

Fig. 2 Test circuit.

"tJ

-I ~

0
)> 01

~r 5�
~

1. 0c.>

0 )>

[

0 ::>

Signetics RF Communications

Section 5 Audio and Data Processors

INDEX

NEISA5750 NE/SA5751 AN1741 PCASOOOAT PCF5001T TEA6300 UMA1000T

Audio processor - companding and amplifier section . . . . . . . . . 521 Audio processor - filter and control section . . . . . . . . . . . . . . . . 528 Using the NE5750 and NE5751 for audio processing ........ 538 Paging decoder . . . . .. .. . . . . . . .. . . .. . .. . . . . . . . . . . . . . . 558 POCSAG paging decoder with EEPROM storage . . . . . . . . . . . 577 Sound fader control circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579 Data processor for cellular radio (DPROC) ................ 595

Signetics RF Communications
Audio processor - companding and amplifier section

Product specification
NE/SA5750

DESCRIPTION
The NE/SA5750 is a high performance low power audio signal processing system. The NE/SA5750 subsystems include a low noise microphone preamplifier with adustable gain, a noise cancellation switching amplifier with adjustable threshold, a voice operated transmitter (VOX) switch, VOX control, an audio compressor with buffered input, audio expandor, a unity gain power amplifier to drive a speaker, a summing power amplifier for sidetone attenuation and headphone (earpiece) drive, and an internal bandgap voltage regulator with power down capability. When used with Signetics' NE/SA5751, the complete audio processing function of an AMPS or TACS cellular telephone is easily implemented. The NE/SA5750 can also be used without the NE/SA5751 in a wide variety of radio communications applications.

FEATURES
� High performance � 5V supply � Adjustable VOX and noise cancellation
threshold �Adjustable gain preamplifier � Audio companding � ESD protected � Open collector VOX output � Logic inputs CMOS compatible � Power down mode � Built-in drivers for speaker and earpiece � Few external components � SOL and DIP packages

BENEFITS
� Very compact applications
� Long battery life in portable equipment
� Complete cellular audio function with the SA5751

APPLICATIONS
� Cellular radio � Mobile communications � High performance cordless telephones � 2-way radio

PIN CONFIGURATION
01 and N PACKAGE

MIC1N 1 PREAMPGRES 2
RECTGRES 3 NCANcAP 4 VOXouT 5 VOJCcTL
HpoN SPKRouT
EARouT

NCANouT COMP1N COMPcAP1 COMPcAP3 COMPouT COMPcAP2
Vee
EXP1N EXPouT EXPcAP SPKR1N EAR1N

NOTE: 1. Available only in SOL (large SO) package.

ORDERING INFORMATION

DESCRIPTION 24-Pin Plastic DIP

TEMPERATURE RANGE
o to +70'C

24-Pin Plastic SOL

Oto +70'C

24-Pin Plastic DIP

-40 to +85'C

24-Pin Plastic SOL

-40 to +85'C

ORDER CODE NE5750N NE5750D SA5750N SA5750D

ABSOLUTE MAXIMUM RATINGS

SYMBOL

PARAMETER

Power supply voltage

Vee

Voltage applied to any pin

TsTG TA

Storage temperature
Ambient operating temperature NE5750 SA5750

RATING 6
-0.3 to (Vee+ 0.3) -65to+150
Oto 70 -40 to +85

UNIT
v v
'C
'C

August 17, 1990

521

853-1451 00210

Signetics RF Communications
Audio processor - companding and amplifier section

Product specification
NE/SA5750

PIN DESCRIPTIONS
PINNO. SYMBOL

DESCRIPTION

1

MIC1N

Microphone input

2

PREAMPGRES Preamplifier gain resistor

3

RECTGRES Reactifier gain resistor

4

NCANeAP Noise cancellation timing capacitor

5

VOXouT Voice operated transmission output

6

VOXerL Voice operated transmission control

7

VOXTR

Voice operated transmission threshold resistor

8

GND

Ground

9

VREF

Reference voltage

10

HPDN

Hardware power down

11

SPKRour Speaker output

12

EARour Earpiece output

13

EAR1N

Earpiece input, side tone input

14

SPKR1N Speaker input

15

EXPeAp Expander timing capacitor

16

EXPour Expander output

17

EXP1N

Expander input

18

Vee

Positive supply

19

COMPeAP2 Compressor timing capacitor 2

20

COMPour Compressor output

21

COMPeAP3 Compressor timing capacitor 3

22

COMPeAP1 Compressor timing capacitor 1

23

COMP1N Compressor input

24

NCANouT Noise cancellation output

BLOCK DIAGRAM

24

23 22

21

20

19

18

17

16

15

14

13

BUFFER

EXPANDOR

COMPANDOR

Vee NE/SA5750

NOISE CANCEL

BANDGAP VOLTAGE REF

11

12

August 17, 1990

522

Signetics RF Communications
Audio processor - companding and amplifier section

Product specification
NE/SA5750

DC ELECTRICAL CHARACTERISTICS
TA= 25�C, Vee= +5.0V, OdB = 77.5mVRMS� See test circuit, Figure 4.

SYMBOL Vee Ice

PARAMETER Supply voltage Supply current

TEST CONDITIONS
No signal Power down mode

Load impedance

ZL

pins NCANour. EXPour

COMPour1

Input impedance

Z1N

COMP1N. MIC1N. SPKR1N

EXP1N2

Noise cancellation current

Pin 7, grounded

Vos

DC offset NCANour3

NOTES: 1. Compressor is tested in production with 50kQ load. 2. Not tested in production. 3. Offset values are identical for both gain states of noise reduction circuit.

MIN 4.75
50 10 40 2.0 40 -50

LIMITS TYP 5.0 8.4 1.8
50 2.5 50

MAX 5.25 12.0 3.0
60
60 50

UNIT
v
mA mA
kQ kQ
kQ kQ �A mV

AC ELECTRICAL CHARACTERISTICS
TA= 25�C, Vee = +5.0V, OdB level= 77.5mVRMS� See test circuit, Figure 4.

SYMBOL

PARAMETER
Preamplifier gain range Preamplifier voltage gain OdB Preamplifier voltage gain 40dB

Preamplifier noise density

Switch amplifier gain

Sidetone attenuation range

Compandor 1kHz, all tests1

COMPour Compressor error at-21dB output level

COMPour Compressor error at -1 OdB output level

COMPour Compressor error at OdB output level

COMPour Compressor error at +5dB output level

COMPour Compressor error at+ 12.3dB output level

EXPour

Expander error at -42dB output level

EXPour

Expander error at-21dB output level

EXPour

Expander error at -1 OdB output level

EX P o u r

Expander error at OdB output level

EXPour

Expander error at+ 10dB output level

EX P o u r

Expander error at +24.6dB output level2

EXPour Expander Vos

EX P o u r

Expander output DC shift

TEST CONDITIONS
Pin 2 open Pin 2 AC ground
Pin 2 AC grounded RS =0-50kQ unweighted 20Hz-20kHz
weighted CCIR DI N45405 20-20kHz

MIN 0
-1.0 39.0
9

Input level = -42dB Input level = -20dB Input level = OdB Input level = +1OdB Input level= +24.6dB Input level = -21 dB Input level= -10.5dB Input level = -5dB Input level = OdB Input level = +5dB Input level = +12.3dB No signal No signal to OdB

-1.0 -1.5 -1.0 -1.0
-1.0 -1.0 -1.5 -1.0 -1.5 -50.0 -100

LIMITS TYP 0 40
7 8 10
0.38 0.12
-0.41
-0.18

MAX
40 1.0 41.0

UNIT
dB dB dB

nV/fih

nV/fih

11

dB

30

dB

dB

1.0

dB

1.5

dB

1.0

dB

1.0

dB

dB

1.0

dB

1.0

dB

1.5

dB

1.0

dB

1.5

dB

50.0

mV

100

mV

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Product specification
NE/SA5750

AC ELECTRICAL CHARACTERISTICS
TA= 25�C, Vee= +5.0V, OdB level= 77.5mVRMS� See test circuit, Figure 4.

SYMBOL THD

PARAMETER Timing capacitors compandor Total harmonic distortion
Compressor Expandor
NCANouT

TEST CONDITIONS

MIN

1kHz, OdB
1kHz, OdB
1kHz. Pin 2 open output level = OdB

1kHz, Pin 2 open output level = +25dB

Speaker amplifier Drive capability

Output swing (<1% THD)

50Qload

2

Ear amplifier Drive capability
Output swing (<1%THD)

1000 load

3

No load

4

300Qload

3

VOXouT VOXcTL
HPDN

Sink current

Low level High level

Input current

Low

High

Input level

Low High

Input current

Low

High

Input level

Low High

Reference filter capacitor

2000Qload

4

No load

4

Open collector IL= 0 .5mA

4

-50

-10

0 3.5

-10

-10

0 3.5

NOTE: 1. Measurements are relative to OdB output 2. Measurement is absolute and indicative of the output dynamic range capability.

LIMITS TYP 2.2 0.09 0.09 0.18 0.13
3.2 4.1 4.9
4.3 4.9 4.9 0.07 5 -21
10

MAX

UNIT �F

1

%

1

%

1

%

1

%

40

mAp.p

Vp.p

Vp.p Vp.p

10

mAp.p

Vp.p

Vp.p

Vp.p

0.5

mA

0.4

v

v

0

�A

+10

�A

1.5

v

5

v

+10

�A

+10

�A

1.5

v

5

v

�F

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Audio processor - companding and amplifier section

Product specification
NE/SA5750

Compandlng and Amplifier Section NE/SA5750
PREAMP
GAIN ---+--~ CONTROL
vex
SENSITIVITY

Fiiter and Control Section NE/SA5751

TX BANDPASS
ALTER

SUMMING AMP

AUDIO TO TRANSMITTER

EXPANDOR SPEAKER

DTMF GENERATOR

AUDIO FROM RECEIVER
DEMODULATOR

ATTENUATOR

12c
BUS INTERFACE ~jlllllllll!l!lllllllli!
FROM SYSTEM CONTROLLER 12c BUS
VOXCONTROL

Figure 1. Typical Configuration of Audio Processor (APROC) System Chip Set

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Product specification
NE/SA5750

DEMODDATA_. TXEN

DATA BLOCK

RXCLOCK
RXDAIA
Tl<CLOCK TYnATA
t----i
t----i

DATA PROCESSOR
~

DATA

s .. "' ~z
g Q

~
:JI

<i>t

!il iii
~ ::> ID

DEMOD j

1---1

RF BLOCK

1--1 AUDIO BLOCK

l1 MOD I

r

vox

T

~
IC

MIC SPEAKER EARS

j

t

j

LOGIC UNIT

J 1

L
a-

"

CONTROL UllT

5v.c-1

7.5v.c-1

POWER SUPPLY

5.0/0V.c-1

7.5/0V~

+ '

POWER SUPPLY ENABLE

Figure 2. Cellular Radio System

DEMODDATA TXEN

DATA PROCESSOR

DATA

DEMOD

l

f-

H

RF BLOCK
1-

NE5750 H
H

NE5751

ll tMOD 1
vox

H

.l.

:r

l12c ---
::i.

RSSI

MIC

SPEAKER

LOGIC UNIT
�TI

EARS

CONTROL UNIT

5V-

7.SV5.0/0V-

POWER SUPPLY

7.5/0V-
+

POWER SUPPLY ENABLE

Figure 3. APROC Application Diagram

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Audio processor - companding and amplifier section

Product specification
NE/SA5750

C2 PREAMP~+

A~.7..1

4.7�F

-::- R2 RECTGRES -~VV\~-a----1
c1sI 22nF
C3 NCANcA.I:-------1 +
-= 15�F

VOXOUTo-------1

VOJCcTL o-------1
R3 VOXTR
S.6k
GND n - - - - - - - - - 1

NOISE CANCEL

BUFFER

SIDE TONE C13~CANouT

COMPRESSOR,__ _ _ __,
vex

COMPouT

.___ _ _ _ _ _ _ ___, 1a < - - - - - - . . . . n Vee

VREF

BANDGAP VOLTAGE REF

Vee

HPDN

10

rO

cs

SPKRouT~ ~10�F I _L

11

C1S

J220nF

cs
EARouT~ +

12 >-------~

10�F

EXPANDOR

1S ~-----<" EXPouT

SPKRtN 14

RS

EARIN

13

S1k

RS

SIDE TONE

S1k

TOPIN

24 R4 S1k

Figure 4. NE/SA5750 Test and Application Circuit

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Product specification
NE/SA5751

DESCRIPTION

BENEFITS

PIN CONFIGURATION

The NE/SA5751 is a high performance low power CMOS audio signal processing

� Very compact application

NPACKAGE

system. The NE/SA5751 subsystems include complementary transmit/receive voice band (300-3000Hz), switched capacitor bandpass filters with pre-emphasis and de-emphasis respectively, a transmit low pass filter, peak deviation limiter for transmit, a digitally

� Long battery life in portable equipment � Complete cellular audio function with the
SA5750
APPLICATIONS

TXBFouT 4

NC

TXLFouT

11

TXDTMFouT

I

TXSiN

controlled volume control with 30dB range (in 2dB steps), audio path mute switches, a programmable DTMF generator, power- down circuitry for low current standby, power-on reset capability, and an 12c interface. When

� Cellular radio � Mobilecommunications � High performance cordless telephones

PREMP1N 5
Yoo OEMPouT 7
VCiN 8

TXSoUT GNO CLKiN SOA

the SA5751 is used with an SA5750

� 2-way radio

SCL

(companding function), the complete audio processing system of an AMPs or TACs cellular telephone is easily implemented.

VCouT2 MUTET

SA1 RXBF1N

MUTER

VOXctL

FEATURES

�Low power � High performance � 5Vsupply � Built-in programmable DTMF generator � Built-in digitally controlled volume control

0 1 Package

NC
NC
TXLFOUT TXOTMFouT

� Built-in peak-deviation limit � 12c Bus controlled � Power-on reset � Power-down capability

TXS1N TXSouT GNO CLK1N SDA

SCL

SA1

MUTET

RXBliN

MUTER NC

VOXCTL
NC

ORDERING INFORMATION

eu- NOTE:
1. Av�H- In SOL (Jorge

mount) package onl

DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

24-Pin Plastic DIP

o to +10�c

NE5751N

28-Pin Plastic SOL

oto +10�c

NE5751D

24-Pin Plastic DIP

-40to +B5�C

SA5751N

28-Pin Plastic SOL

-40to +85�C

SA5751D

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Audio processor - filter and control section

PIN DESCRIPTIONS

PINNO. (1)

SYMBOL NC

Not connected

DESCRIPTION

1 (2)

NC

Not connected

2 (3)

VREF

Reference voltage

3 (4)

TXBF1N

Transmit bandpass filter input

4 (5)

TXBFour Transmit bandpass filter output

5 (6)

PREMP1N Pre-emphasis input

6 (7)

Voo

Positive supply

7

(8)

DEMPour De-emphasis output

8 (9)

VC1N

Volume control input

9 (10)

VCoun

Volume control output 1

10 (11)

VCour2

Volume control output 2

11 (12)

MUTET

TX analog voice path mute input

12 (13)

MUTER

RX analog voice path mute input

(14)

NC

Not connected

(15)

NC

Not connected

13 (16)

VOXcrL

Vox control output

14 (17)

RXBF1N

Receive bandpass filter input

15 (18)

SA1

Serial bus address

16 (19)

SCL

Serial clock line

17 (20)

SDA

Serial data line

18 (21)

CLK1N

Clock input

19 (22)

GND

Ground

20 (23)

TXSour

Transmit summer output

21 (24)

TXS1N

Transmit summer input

22 (25) TXDTMFouT Transmit DTMF output

23 (26)

TXLFouT Transmit low-pass filter output

24 (27)

NC

Not connected

(28)

NC

Not connected

NOTE: 1. Callouts are for N package; those in parentheses are for the D (SOL) package.

Product specification
NE/SA5751

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BLOCK DIAGRAM

POWER ON
RESET

DTMF GENERATOR

Product specification
NE/SA5751

12<: BUS RECEIVER

NOTES: 1. T1 to T10 represent the signal path switches. 2. M1 and M2 represent the mute switches. 3. PRE and DEE represent the bypass switches for pre-emphasis and de-emphasis, respectively. 4. B1 to B6 represent the output buffers.

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Product specification
NE/SA5751

ABSOLUTE MAXIMUM RATINGS

SYMBOL

PARAMETER

Power supply voltage1

Tsm

Storage temperature

TA

Ambient operating temperature NE5751

SA5751
NOTE: 1. Voltage applied to any pin -0.3 to Voo +0.3V

RATING 6
-65to+150 Oto70
-40to +85

UNIT
v oc oc
oc

DC ELECTRICAL CHARACTERISTICS

SYMBOL Voo loo

PARAMETER Power supply voltage range
Supply current

TA= 25�C, Voo = +5.0V, unless otherwise specified. See test circuit, Figure 4.

LIMITS

TEST CONDITIONS

MIN

TYP

MAX

UNIT

4.75

5.0

5.25

v

Operating Standby

2.7

5.0

mA

0.9

2.0

mA

AC ELECTRICAL CHARACTERISTICS

SYMBOL

PARAMETER RX BPF anti alias rejection RX BPF input impedance RX BPF gain with de-emphasis RX BPF gain with de-emphasis RX BPF gain with de-emphasis RX BPF gain with de-emphasis RX BPF gain with de-emphasis RX BPF noise with de-emphasis RX dynamic range DEMPouT output impedance DEMPouT output swing (1%) VCoun ouput swing (1%) VCouT2 output swing (1%)
VCoun noise

VCouT2 noise
Mute threshold off Mute threshold on CLK1, 2 high CLK1, 21ow TX BPF anti alias rejection TX BPF input impedance

TA= 25�C, Voo = +5.0V. See test circuit, Figure 4. Clock frequency= 1.2MHz;

test level = OdBV = 77.5mVRMS = -20dBm, unless otherwise specified.

LIMITS

TEST CONDITIONS

MIN

TYP

MAX

UNIT

40

dB

f= 1kHz

500

kn

f = 1kHz

-0.5

0

0.5

dB

f = 100Hz

-31

-29

dBmO

f = 300Hz

9.0

9.6

11.0

dBmO

f = 3kHz

-11.0

-10.0

-9.0

dBmO

f = 5.9kHz

-68

-50

dBmO

300Hz-3kHz with deemphasis

170

�VRMS

80

dB

f = 1kHz

40

n

2.3kn to VREF; f = 1kHz Voo-3

3.5

Vp.p

50kn toVREF; f = 1kHz

Voo -1

4.5

Vp.p

50kn to VREF; f = 1kHz Voo -1

4.5

Vp.p

VC 1N grounded C- message

25

�VRMS

VC 1N grounded C - message

25

�VRMS

0

0.8

v

2.0

5.0

v

4.0

5.0

v

0

1.0

v

t = 3kHz

40

dB

500

KQ

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Audio processor - filter and control section

Product specification
NE/SA5751

AC ELECTRICAL CHARACTERISTICS (continued)

SYMBOL

PARAMETER TX BPF noise TX LPF gain TX LPF gain with pre-emphasis TX LPF gain with pre-emphasis TX LPF gain with pre-emphasis TX LPF gain with pre-emphasis TX LPF gain with pre-emphasis TX LPF gain with pre-emphasis TX overall gain TX overall gain TX overall gain TX overall gain TX overall gain TX BPF output impedance
TX BPF output swing (1%THD)
TX BPF dynamic range PREMP 1N input impedance Summing op amp
Slew rate Output impedance Output swing (1% THO) Volume control accuracy Analog switches Insertion loss

On time transition

Off time transition

TEST CONDITIONS 300 - 3000kHz f = 5.9kHz f = 1kHz, 20dBV f = 100Hz 1=300Hz f = 3kHz f=5900Hz f = 9kHz 1kHz 100Hz 300Hz 3kHz 5.9kHz f = 1kHz 50kn to VREF f = 1kHz
f = 3kHz
CL= 15pF Unity gain; f = 3kHz 1kHz, 5kQ load (25�C)
-30dBtoOdB
MUTET, MUTER O.BV->2.0V
MUTET, MUTER 2.0V->0.BV

MIN
11.3 -11 8
-1

LIMITS TVP 90 -39 12.06 -19 -10.45 9.14 -39 -51 11.8 -47 -10.4 9 -52 360
4.5
90 500
0.75 40 4.3 0
60
3
0.25

MAX -36
12.5 -45 -9 9.6 -45

UNIT �VRMS
dB dB dBmO dBmO dBmO dBmO dBmO dB dBmO dBmO dBmO dBmO Q
Vp.p
dB kn

V/�s Q

Vp.p

+1

dB

dB �s �s

12c CHARACTERISTICS
The 12C bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both SDA and SCL are bidirectional lines connected to a positive supply voltage via a pull-up resistor. When the bus is free, both lines are high. Data transfer may be initiated only when the bus is not busy.
The output devices, or stages, connected to the bus must have an open drain or open collector output in order to perform the wired-AND function.
Data at the 12 C bus can be transferred at a rate up to 100kbitsls. The number of devices con-

nected to the bus is solely dependent on the maximum allowed bus capacitance of 400pF.
Due to the variety of different devices which can be connected to the i2C bus, the levels of the logical "O" and "1" are not fixed and depend on the appropriate level of V00. For the typical supply voltage of 5V which is chosen here, logical "1" and logical "O" are, however, fixed respectively on maximum input LOW voltage, 1.5V and minimum input HIGH voltage, 3.0V.
BIT TRANSFER
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock's

cycle. If it does not remain HIGH, it may be interrupted as a control signal.
START AND STOP CONDITIONS
Both data and clock lines remain HIGH when the bus is not busy. A HIGH to LOW transition of the data line while the clock line is HIGH is defined as a start condition S. A LOW to HIGH transition of the data line while the clock is HIGH is defined as a stop condition.
SYSTEM CONFIGURATIONS
A device generating a message is a "transmitter"; a device receiving a message is the "receiver". The device that controls the

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Product specification
NE/SA5751

message is the "master"; and devices which are controlled by the master are the "slaves".
ACKNOWLEDGE
The number of data bytes transferred between the start and the stop condition from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so thatthe SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse; set up and hold times must be taken into account.
12c BUS DATA CONFIGURATIONS
The NE5751 is always a slave receiver in the 12C bus configuration (R/W bit-0). The slave address consists of seven bits in the serial mode where the least significant bit is selectable by hardware on input AO and the other more significant bits are internally fixed.
POWER ON RESET
In order to avoid undefined states of the NE5751 when the power is switched on, a power on reset is supplied. The reset is active when Pin VREF is held below 0.SV. The reset is off when Pin VREF is above 2.0V. Pin VREF is normally at 2.SV generated by a resistive divider from V00. Nominal impedance is 20k!l In a typical application a capacitor is connected to Pin VREF to improve power supply rejection. The time delay of the network resets the internal registers when power is first applied. The signal paths are off in the reset condition. The NE5751 must be programmed via the 12C bus for normal operation. The Power Down mode is defined only when all register values are zero.

CONTROL REGISTERS

Register Map

The address register is as follows:

MSB

LSB

A6 A5 A4 A3 A2 A1 AO R!W

0 0 0 0 0 SA1 0

SA 1 is controlled by serial bus address pin.

Signal Path Register

MSB

LSB

T10 T9 TS T6 VOXEN T4 T3T5 T2

T2 T3T5

is the transmission gate between Pin PREEMP1N and the emphasis input.
connects the output of the DTMF generator to the emphasis input and connects the output of the XMT LPF to Pin TXDTMFouT�

T 4

connects the output of the XMT LPF

to Pin TXLFouT�

VOXEN enables the VOX function of NE5750.

T6

connects Pin VC1N to the volume

control.

TS

connects the output of the DTMF

generator to the volume control.

T9

enables VCoun.

T10 enables VCouT2�

Volume Control and Test Register

MSB

LSB

POW T1 T7 DEE PRE V1 V2 V3 V4

V4

is volume control bit 4. This is the

MSB. A zero is 16dB attenuation.

V3

is volume control bit 3. A zero is SdB

attenuation.

V2

is volume control bit 2. A zero is 4dB

attenuation.

V1

is volume control bit 1. A zero is 2d8

attenuation.

PRE is the bypass for the pre-emphasis.
DEE is the bypass for the de-emphasis.
T1T7 is the bypass for the compressor and expander.
POW is the control for power down mode.
This mode is defined only when all register values are reset to zero.

High Tone DTMF Register

MSB

LSB

HD7 HD6 HD5 HD4 HD3 HD2 HD1 HDO

The eight bits determine the output frequency by the following formula.:

High Frequency= 1200kHz/6/HD where HD is the value of the register.

Low Tone DTMF Register

MSB

LSB

LD7 LD6 LDS LD4 LD3 LD2 LD1 LOO

The eight bits determine the output frequency by the following formula.:

Low Frequency = 1200kHz/12/LD where LD is the value of the register.

The operation of the 96ms DTMF timer is initiated by the loading of the low tone DTMF register. This timer terminates transmission of the tones as the generated tones cross the reference level after 96ms. The on time of the tones can thus vary by up to one cycle of the tones.

Continuous tones can be obtained by again loading the two DTMF registers before 96ms have elapsed.

Single tones can be obtained by loading 0, 1 or 2 into one of the registers to silence it.

Phase continuous frequency modulation can be produced by loading a new value into a DTMF register during operation.

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Audio processor - filter and control section

Product specification
NE/SA5751

Compandlng and Amplifier Section NE/SA5750
PREAMP
GAIN ----t---~ CONTROL
vox
SENSITIVITY

Filter and Control Section NE/SA5751

TX BANDPASS
ALTER

SUMMING AMP

AUDIO TO TRANSMITTER

EXPANDOR

AUDIO FROM RECEIVER
DEMODULATOR

SPEAKER

ATTENUATOR

12c

i<::"-1-----< CLOCK
1.2Mllz

BUS

INTERFACE ..l!m!l!!llll!lllii!lll

FROM SYSTEM CONTROLLER 12c BUS

VOXCONTROL

Figure 1. Typical Configuration of Audio Processor (APROC) System Chip Set

August 17, 1990

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Signetics RF Communications
Audio processor - filter and control section

Product specification
NE/SA5751

DEMODDATA_.. TXEN

DATA BLOCK

RXCLOCK RYllATA TXCLOCK TXnATA
1--t---

DATA PROCESSOR
f

DATA

,__ ...l

DEMOD

i---
RF BLOCK

AUDIO BLOCK

MOD
lT
vox

:n l
~c

, MIC SPEAKER

EARS

g"' "' "' g

z
~
c

>
0:
~

0
1t

ii!
> ~

> :m:>

j

t

LOGIC UNIT

~ 8

CONTROL UNIT

5V-

7.5V5.0/IJV-

POWER SUPPLY

7.5/IJV-
+ -

POWER SUPPLY ENABLE

Figure 2. Cellular Radio System

DEMODDATA......
TXEN

DATA PROCESSOR

DEMOD
r-
11RF BLOCK 1-
MOD
vox

DATA

j

1

NE5750

H

H

NE5751

H

H

-l

RSSI

1 MIC EARS

SPEAKER

LOGIC UNIT

� 1 I j 1

.t.

ii'c

a-

"

CONTROL UNIT

Figure 3. APROC Application Diagram

5V7,5y,._J 5.0/IJV._;

POWER SUPPLY

7.5/0v4-
+

POWER SUPPLY ENABLE

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Signetics RF Communications
Audio processor - filter and control section

Product specification
NE/SA5751

10�F
100kll 2.2�F

t

MUTER

SWITl_ NC

NC

TXLFouT

12c BUS RECBVER

51kll TXSiN
51kll
f--~1-------l ~OUT 2.2�F GND
f-------OCL~N
f-----{JDA
f-----dSCL

1._ SWITCH

2.2�F -::-
1--------+'--l~

100kll

RXBF1N

VOXcTL NC

Figure 4. NE/SA5751 Test and Application Circuit

August 17, 1990

536

ci. Signetics RF rnunication~'
Audio processor - filter and control section

Product specification
NE/SA5751

PERFORMANCE CHARACTERISTIC
THO(%) vs INPUT SIGNAL VOLTAGE (1kHz) FOR THE RX BANDPASS, TX BANDPASS, AND TX LOW-PASS FILTERS

RX ' BANDPASS

t =::::::::::::�::=:==:=:b.::::::::::::::::::b::::::::::::::::b::::::::::::::=!::::::::::::::::d::::::::::::::::::=:ITLXOW-PASS
INPUT (Vp.p)

August 17, 1990

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Slgnetlcs RF Communications
Using the NE5750 and NE5751 for audio processing

41\,pllcatlon note
AN1741

Author: Alvin K. Wong
INTRODUCTION
The NE5750 and the NE5751 are two audio processor chips that can be used in RF communications. The chip-set processes a voice so that by the time it is transmitted and received, the quality is preserved. This is accomplished through the use of compression/expansion and pre-emphasis/ de-emphasis.
The audio processor chip-set (APROC) has a wide variety of high performance applications such as cellular phones, cordless voice microphones, cordless intercom systems, standard phones, and hand-held, base, or mobile two-way communications equipment.
Below is an outline of this application note:
I. WHAT IS AUDIO PROCESSING
- How the Voice is Processed by the NE5750 and NE5751
- More Detail on the Key Features - Performance Graphs

UMITERAND ALL-PASS CKT
TOTX
_,t?:"'\',fl----.. rz ft':'f:'%l'+--->1 -----.....__
EXPANDOR
NOTE:D NE5750
El] NE5751
Figure 1. Key Functions of the NE5750 and NE5751 That Contribute to Improving the SIN Ratio and Sensitivity In the System.

II. NE5750
- A Breakdown of the NE5750 �preamp �noise canceller �VOX � VOXouT and VOXcTRL �setting the threshold �Compandor +compressor +expander �how to measure the attack and recovery time �Amplifier Section +speaker amplifier +earphone amplifier
- How to Power Down
Ill. NE5751
- A closer look at the NE5751 �transmit path +limiter and all-pass circuit �receive path
- 12c Bus Receiver
IV. APROC DEMO-BOARD
- How to Power Down the Chip set - Component list and layout
V. NE5750 DEMO-BOARD
- Component list and layout

INPUT FROM MOUTHPIECE (TRANSMITTER)

S/NWITH
......~. 'lt'-'t�"' COMPANDING
OUTPUT TO EARPIECE (RECEIVER)

NOISE INTRODUCED FROM THE TRANSMISSION

Figure 2. S/N Ratio With Compandlng vs Without Compandlng

VI. QUESTION AND ANSWER SECTION
I. WHAT IS AUDIO PROCESSING
HOW THE VOICE IS PROCESSED BY THE NE5750 and NE5751:
Audio processing begins when a person speaks into a microphone (see Figure 1). The signal is first amplified by the preamp, then screened by a bandpass filter. Alter the noise is filtered out, the voice signal is processed by the compressor. The function of the compressor is to attenuate loud voices and amplify soft ones. The upper voice frequencies are then amplified by pre-emphasis before their voltage amplitudes are restricted by the limiter and all-pass circuit. When this is completed, the processed voice is ready for transmission.
Since the voice signal was processed by the APROC before transmission, it must be unprocessed upon reception. The received signal is screened again so that the unwanted received noise is blocked before it goes

through de-emphasis. In de-emphasis, the upper voice frequencies are attenuated. Then the signal is expanded back to its primary dynamic range by the expander. Because the voice is restored to its original state, it is ready for amplification by the power amp whose output can be connected to an external speaker. The receiving party will now be able to hear the transmitting party.
MORE DETAIL ON THE KEY FEATURES:
During compression, low level signals are amplified to "jump" over the transmitter channel noise, while the high level signals are compressed to prevent distortion. In general, because we are dealing with a limited dynamic range transmission medium, it is desirable to compress the signal prior to transmission. However, in order to preserve the dynamic range of the original voice signal, the compressed signal is expanded at reception. Figure 2 shows a diagram of a cordless phone application using companding. Note the signal-to-noise ratio with and without companding.

May 29, 1991

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Signetics RF Communications
Using the NE5750 and NE5751 for audio processing

Application note
AN1741

Another key function of the APROC is the pre-emphasis/de-emphasis capability which is used to overcome the "colored" noise,

Compendlng and Amplifier Section NE/SA5750

present in all FM receivers, generated by the

FM demodulator. This noise worsens at the

llC

PREAMP

upper voice band as shown in Figure 3.

Therefore, to keep the same signal-to-noise

ratio in the lower and upper voice bands,

pre-emphasis/de-emphasis is required. A

person with a high-pitched voice will now be

heard just as well as a person with a low,

deep voice.

AMPLITUDE

Alter and Control Section NE/SA5751

300Hz

3kHz

FREQUENCY

WHY PRE-EMPHASIS? (S/N)1 =SIGNAL-TO-NOISE RATIO WITHOUT
(S/NJ:! =SIGNAL-TO-NOISE RATIO WITH

Figure 3. Pre-emphasis Response

Another key stage of the APROC is the limiter with the all-pass circuit. Its main function is to limit the amplitude of the voice signal so that the maximum frequency deviation is limited to 12kHz. Cellular radio specifications allow for a 30kHz channel spacing with an audio bandwidth of 3kHz. Therefore, by Carson's rule the maximum frequency deviation of the limiter must be 12kHz as shown below.

1. Bandwidth
or 2. Max Freq Dev

2 (Modulating Freq + Max Freq Dev)
Bandwidth/2 (Mod Freq) 30kHz/2 - 3kHz 15kHz-3kHz 12kHz

PERFORMANCE GRAPHS OF APROC DEMO-BOARD:
Figure 4 shows the general diagram of the audio processor chip set without the external components. External components for the chip set can be found in Figure 31, and the values were chosen for AMPSITACS specs. To demonstrate the performance of the chip set, data was taken in the lab and resulted in the following figures.

Figure 4. Typical Configuration of Audio Processor (APROC) System Chip Set

Figure 5 Description
Figure 5 reveals what the signal would look like on the bench with different input levels. Figures Sa, b, and call use the same audio input signal. The audio signal (0-6kHz) varies from 20d8 to -30d8 in 10d8 steps.
Figure Sa This graph shows the Tx channel. Notice the signal's increase in amplitude as the frequency is increased due to pre-emphasis. Additionally, the slope of the signal decreases as the input increases.
The compressor function is readily shown where a 5dB change in the output level occurs for every 1OdB change in the input.
Figure Sb The 2:1 expansion of audio (20dB change for every 1OdB), bandpass filtering and the de-emphasis filter response (300-3kHz) are shown. The graph shows the Rx channel. Notice the signal's decrease in amplitude as the frequency increases due to de-emphasis.
Figure Sc This shows that a flat frequency response is achieved upon normal reception. Notice the 20dB gap, although the input steps are for 10dB. This is due to the noise canceller turning on. The decrease in amplitude for higher level, higher frequency tones is the result of the deviation limiter action.

FREQUENCY
a) TRANSllT CHANNEL (AUDIO LEVEL DECREASING)

FREQUENCY b) RECEIVE CHANNEL

FREQUENCY c) LOOPBACK
All Graphs: 10dB/Oiv CENTER: 3000Hz

SPAN: 6000Hz

Figure 5.

May 29, 1991

539

Signetics RF Communications
Using the NE5750 and NE5751 for audio processing

Application note
AN1741

D

SPEAKER

12C BUS

NE5750/NE5751

Figure 6. NE5750/NE5751 Test Set-Up

AUDIO NOISE

c
WITH COMPANDING AND PRE-EMPHASIS/DE-EMPHASIS
D

B

THERE IS GAIN IN THE PREAMP WITH A TONE PRESENT.

10mV

'
r

-

'
r

-

t I

-

'
r

-

SOO�s

I

I

I

I

L I

I

I

I

- - ,- - r - r - r - j - r - r - , - , -

: : : -r-1 - ~ - : ~ - : - B

l--11-11-l-11-.-. -

LI - ~ - - '- - �- - 1_ - !... -

I

I

'

I

!.. - - .!. - .!. -

I

I

'

I

j -

- 11-0m- 'V- -

'- I

!.. -
I

~ -

!. -
I

.!. -
I

1 -
1

1 -
1

A

NO GAIN IS OBSERVED IN THE NOISE LEVEi. Figure 7.

Figure 7 8 9 10

Description
No noise gain is observed at the output of the Tx channel because of the noise canceller circuit.
Shows why companding and emphasis are needed to improve the quality of the audio signal when BASEBAND NOISE is present in the system
Shows why companding and emphasis are needed to improve the quality of the audio signal when RF NOISE is present in the system.
Shows that the sensitivity and the signal-to-noise ratio of a receiver improved due to audio processing.

May 29, 1991

D
c
WITH COMPANDING AND PRE-EMPHASIS/DE-EMPHASIS

'

I

'--L-t-.l.-.1-J._.J_

c

10mV I

1

I

I

I

NO COMPANDING, NO PRE-EMPHASIS/DE-EMPHASIS

D

c
NO COMPANDING, NO PRE-EMPHASIS/DE-EMPHASIS
D
c
NO COMPANDING, PRE-EMPHASIS/DE-EMPHASIS ONLY C = BOTTOM TRACE AUDIO SIGNAL BEFORE GOING TO THE RF TRANSMITTER D = TOP TRACE RNAL SPEAKER OUTPUT
Figure 8. Audio Output with Baseband Channel Noise

NO COMPANDING, PRE-EMPHASIS/DE-EMPHASIS ONLY
C = BOTTOM TRACE AUDIO SIGNAL BEFORE GOING TO THE RF TRANSMITTER
D =TOP TRACE RNAL SPEAKER OUTPUT
Figure 9. Audio Output with a Noisy RF Channel
After studying these figures, a designer will have a graphical understanding of how the APROC processes a signal.
Figure 6 shows the test set-up using the APROC demo-board to simulate a real cellular phone call. Audio noise is added to the input of the microphone and RF noise is added to the receiver. The table for Figures 7-10 describes what the associated waveforms reveal when certain key stages of the APROC are activated or bypassed.
As seen from the following figures, there is a definite advantage in using the chip set in high performance communication systems.

540

Signetics RF Communications
Using the NE5750 and NE5751 for audio processing

Application note
AN1741

ANAL AUDIO SENSITIVITY FOR 12dB SINAD

� � � No Comp. No P/D

-85

- - P/D only

- Comp. and P/D

i-90 \

:!!. \ \ ~-95 \ \

>~100

\ \
\ \

Cl
Ul105
�110

-- .... ' \
'' .. '

-20 �10

10 20

Audio Level (dB)

SIGNAL TO BACKGROUND NOISE (�100dBm RF)
l70

~60
~50
Cz l
~40
"~30
~
g20

..3Q �20 �10 0

10 20

Audio Level (dB)

Fl ure 10.

II. NE5750
A CLOSER LOOK AT THE NE5750:
Referring to Figure 11, the NE5750 has seven main features which make this chip unique: preamp, noise canceller, VOX, compressor, expander, buffer, and power amplifiers. (NOTE: All component labels in this section are referenced to Figure 11, unless otherwise indicated.)
Preamp: The NE5750 provides a preamp with adjustable gain. This allows the designer to boost the low level audio signal coming out of the microphone. The microphone can be connected to Pin 1 through a DC blocking capacitor, C1 (see Figure 12). The input impedance at this Pin is 50kQ.
The preamp gain of the NE5750 can be adjusted from OdB to 40dB by an external resistor, R7, connected to Pin 2 through a capacitor C2. Below is a formula which allows the designer to determine the value of R? for a certain value of gain.
If a designer wanted a preamp gain of 20dB, a 5kQ resistor would be required (see Table 2).

(1)

X~B)) - Fr7 = [ 50,000 ] - 500

10(

1

"X" in dB

Table 2. Calculated R7 Values for Different Preamp Gains

X (dB)

R7

0

Leave Pin 2 open

5

64k

10

22k

15

10k

20

5.1k

25

2.5k

30

1.1k

35

405

40

Pin 2 AC grounded

Noise Canceller: The output of the preamp is connected to the input of the noise canceller circuit which is internal to the device. The function of the noise canceller is to automatically provide a set gain of either OdB when no signal is present, or 10dB when a signal is present. With this feature, background noise is minimized from transmission.

This automatic gain selling can only be implemented when the noise canceller circuitry is used in conjunction with the VOX circuitry. The threshold and attack and release time can be set externally. This will be described in more detail in the "VOX" section.

Although the noise canceller circuit is really designed to be used with the VOX circuitry, it can be implemented without it. The noise canceller circuit can be set up to provide either OdB or 1OdB of gain at all times (regardless of the presence of a signal). Table 3 shows how to achieve either gain settings when the VOX function is bypassed.

Table 3. Setting Up the Gain of the Noise Canceller

Pin

Gain of Noise Canceller

No.

OdB

10dB

3

Ground

Ground

4

Ground

Vee

7

10k to GND

Ground

The output of the noise canceller is accessible to the designer at Pin 24. C13 is used as a DC blocking capacitor.

VOX:
As mentioned earlier, the VOX circuitry works together with the noise canceller circuit. Pins 3, 4, 5, 6, and 7 all deal with the VOX's performance.
All of the resistor and capacitor values given in the NE5750 data sheet are chosen to meet AMPS/TACS specification for cellular radio. So any deviation from these values should be considered carefully if the application is in cellular radio.
Connected to Pin 3 is a resistor R2 and capacitor C15, as shown in Figure 13. These components set the gain of the VOX. The values here are for internal use only and have no direct relationship with the performance. So the values should be kept as shown. In some special applications, R2 may be adjusted such that the voltage on Pin 4 can be increased. By increasing this voltage, the voltage on Pin 7 can be set to a higher range (more details later).
Pin 4 has C3 and R1 connected to it which affects the attack and release time of the VOX circuit. In general the attack time should be faster than the release time.
The values given for C3 and R1 provide an approximate attack time of 12ms and release time of 120ms. These values should be kept as shown.
The timing of the VOX circuit is important because it controls the gain of the noise canceller, and can also turn the transmitter on and off.
� VOXouT and VOXcTRL By using VOXouT and VOXerRL� Pins 5 and 6 respectively, the NE5750 can control the status of the transmitter. The VOXouT Pin should have a 1Okil pull-up resistor to Vee. When probing Pin 5, a logic '1' or 'O' will be read. The VOXeTRL pin should have a logic '1' or 'O' connected to it. Table 4 shows how Pins 5 and 6 can be used:
Having a logic 'O' on Pin 6 is sufficient in most applications. When voice is present, the noise canceller kicks on while the VOXout Pin supplies a logic '1 ';when voice is not present, VOXout Pin supplies a logic '0'. In a cordless phone application this logic level could be used to turn the transmitter on and off, thereby conserving power for any battery operated applications.
Supplying a logic '1' on Pin 6 would cause the transmitter to stay on regardless of any signal input to Pin 1. However, the functionality of the noise canceller will still be signal dependent.

May 29, 1991

541

Signetics RF Communications
Using the NE5750 and NE5751 for audio processing

Application note
AN1741

NOISE CANCEL

BUFFER

COMPRESSOR1------l
vox

VOXcTL o--v_c_c_ _ _-1
R3 VOXfR ,..---'VV'v---1
5.&k
GNDa---~---<

BANDGAP VOLTAGE REF

EXPANDOR

cs
SPKRouT o--j +

11 1 - - - - - - - - - - - - - - - <

10�F C14 'I220nF

EARouy

o

-

-

jC6 +

=

C1 DC blocking cap for Mic amp

set- NE5750 COMPONENT UST R1 uaed to

time of VOX

C2 DC blocking cap for Mic gain

R2 aet gain of vox, but for Internal UH only

C3 ueed to eet attack ~ release dme of VOX

effects voltage on Pin 4

C4 VREF fllter capacitor

R3 - .........kl level of vox

CS DC blocking cap for speaker at Pin 11

R4 feecl>eck realator for ear amp

C& DC blocking cap for EARour pin C7 eeta attack and releaae time for expandor C8 DC blocking cap for expandor"a Input

RS eeta gain of ear amp for lkle tone signal� RS - gain of ear amp for bueband olgnala R7 - microphone preamp gain

C9 AC bypaaaing for compresaor

C10 p..... AC to GND

C11 eeta attack and release time of compreaaor

C12 DC blocking cap for comprenor'a input

C13 DC blocking cap

C14 low pau filtering for speaker output

C15 ueed for filtering, internal use only

1-~-.J\/\R6flr-+--Cl 2I_2 ___EAR1N 51k ,...., RS 2.2�F SIDE TONE

R4 270k 51k

TOPIN 24

ADQEQ FOB NE57�Q DEMO-BQARD
RS pull-up reolator to get loglc level� out
C18 byp- capacitor C17 bypau c1pacltor C18 - � A C to GND ~ow pooo) C19 DC blocking cap for compondor out C20 DC blocking cap for expandor out c21 DC blocking cop for opeaker In C22 DC blocking cap for ear In

May 29, 1991

Figure 11. NE/SA5750 Application Demo-Board
542

Signetics RF Communications
Using the NE5750 and NE5751 for audio processing

Application note
AN1741

r - - - - - - - - -NE5750

Mic��phone

Pin 1 I

~l--~>---<1>--~~--1

I I
I
I Ptn2 I

50k
=

Noloe C1ncell1don
Gain Control

O.Sk

: . [ ~: -500]

=

10 20 -1

""X"" In dB

Figure 12. Setting Microphone Preampllfler Gain

I

Control

I

I

I

I

I

I

Vee I

I

'L1O'oGrI'CO'O U T : q f Pin 5

I I I

~~~!l,!N -->9 Pin 6

I

Pl_n7 _ _ _ _ _ _Jf

Figure 13. VOX Circuit

COMPRESSOR IN

EXPANDOR OUT

+24.&dB

+24.&dB

i �+~� ~~2 .~.0dB .~.

77.SmV OdB

+SdB OdB
-B

77.SmV OdB

-1

DdB

~�f�~-

;:;;-J -e2dB -30dB / / \\

-30dB

COMPRESSION EXPANSION

Figure 15. Compandor Dynamic Range

High Goin
10d~
low gain
'----+---+----+dllspL ~ 10dB Input Figure 14.
This condition is mainly used if the battery consumption is not a problem. Such a condition would be for any car cellular radios.

� setting the threshold R3 at Pin 7 is used to set the threshold of the VOX. Setting the threshold determines the voltage level input at which the noise canceller and VOX will activate. Formula 4 shows how to calculate the VOX's threshold.
VOXmRESH (mV) = 50�A. FrJ (l<D) (4) Where FrJ > 3kn)
If R3 = 5.6k, the measured voltage at Pin 7 should be approximately 280mV.
The way to adjust the VOX is to first determine what signal level is desired at Pin 1 to activate the VOX noise canceller circuits. Once that level is applied to Pin 1, connect a voltmeter to Pin 4. The voltage level measured here should be plugged into formula 4 to determine R3.

As mentioned earlier, the voltage at Pin 4 can be increased by R2. But one should only deviate from the R2 value if the voltage at Pin 7 cannot come down. In most cases, setting R2 to 43kQ and setting Pin 7 to the voltage at Pin 4 is sufficient.
Figure 14 shows graphically how R3 and R2 affect the location of the "box". The "box" is always 1OdB, which is due to the noise canceller circuit.
EXAMPLE I : Set the VOX threshold such that it "kicks on" when 30mVp.p is applied to Pin 1 of the NE5750 with a preamp gain of OdB.
Step 1: Make sure:
a. Pin 7 is left open.
b. The VOX attack and recovery components are in place at Pin 4.
c. R2 and C15 are connected to Pin 3.
d. If using the NE5750 alone, be sure to connect the preamp output (Pin 24) to the compressor input (Pin 23) with a DC blocking cap.
e. The preamp gain is already set (in this instance the preamp gain is OdB).
f. Make sure that the compressor's components are also connected; compressor's attack time has to be functional
Step 2: Apply a constant 1kHz sinewave signal to Pin 1 with the desired threshold. In this case, 30mVp.p.
Step 3: Measure the DC voltage on Pin 4; V4=260mV
Step 4: Calculate R3:
R3 = V4(V) /(50�A) = 0.260/SO�A = 5.2k
let's use a 5.3kn
Step 5: Connect R3 to Pin 7 and verify that VOX "kicks on" at the desired threshold.
- This set-up has the VOX kicking on at 30mVp.p and kicking off al 11mVp.p.
Referring to the above example, if a preamp gain of 1OdB was chosen before setting the threshold, the threshold will also change. So it is vital that the preamp gain be set before setting the VOX threshold.

May 29, 1991

543

Signetics RF Communications
Using the NE5750 and NE5751 for audio processing

Application note
AN1741

Table 4. VOX Truth Table

Inputs

Voice (Pin 1)

VOXcTRL (Pin 6 of NE5750)

Not Present

logic'O'

Present

logic'O'

Not Present

logic'1'

Present

logic'1'

Outputs Noise Canceller Gain
OdB 10dB OdB 10dB

VOXour logic'O' logic '1' logic'1' logic'1'

NOTE: To apply a logic 'O' on Pin 6 by the 12C evaluation program, be sure that the VOXEN is high, and low for a logic '1' on Pin 6. If the
NE5750 is used alone, be sure that the output of the noise canceller is AC coupled to the input of the compressor. Also, make sure that all of
the components for the compressor are connected.

Compandor:
�compressor The compressor input at Pin 23 requires an external DC blocking capacitor (C 12). The input impedance is roughly 50kn. Unlike the older compandors, this input can be directly driven from CMOS circuits (e.g. NE5751).

The gain from the preamp should be adjusted such that there is enough signal gelling to the compandor. However, one must be careful not to overdrive the inputs. Additionally, do not forget the extra 10dB gain from the noise canceller (assuming it is being used).

Figure 15 shows the typical dynamic range of the compandor. The maximum input signal that the compressor can handle is 3.72Vp.p or 24.6dB. The minimum input is approximately 1.74mVp.p or -42dB. Knowing that the OdB point of the compandor is at 77.5mVRMS� one can easily convert from volts to dB. Formula 5 shows the conversion from VRMS to dB.
(5) X(dB) = 20log ( VRMS )
77.5(mVRMS)
where X = value in dB V = voltage in RMS.

Usually it is easier to work in voltages, but in this case it is better to work in dB. If one knows the input signal in dB, the designer can predict the output of the compressor (also in dB) to be half or two times the input. For instance, if the input were 10dB, we could expect the output to be 5dB. On the other hand, if the input was -20dB, we could expect the output to be -1 OdB.
Capacitor C11 on Pin 22 controls both the attack and release time of the compressor. The attack time may be calculated by Formula6.

Attack time = R� C

(6)

where R=10kn

1-+-t- SOms/dlv t-+-H
lll
a. Input
1--1-1--+-+-l--+--+--l.-+-12~
soma/di~~ 1 unit
--+-llll
b. Output
j_

T 1-1---1--t- 2ms/div,-+-I B11
--1-1--
c. Attack time

�-;- J_

r--.1

I

0.75

unit� SOms/div

lll --i 13.smo 1--

d. Release time

Figure 16. Compressor Dynamic Response

NOTE: The release time is roughly 4 times slower than the attack time by design.
Release time = 4 �Attack time
Capacitor C10 on Pin 21 is used for AC bypassing. Capacitor C9 on Pins 19 and 20 is also for AC bypassing.
� expandor The expander input at Pin 17 requires an external DC blocking capacitor (CB). The input impedance is around 2.5kn. Referring to Figure 15, the input range of the expander is from 19.53mVp.p (-21dB) to 903mVp.p (12.3dB). The output range is from 1.74mVp.p (-42dB) to 3.72Vp.p (24.6dB).
Capacitor C7 is used to set the attack and release time of the expander. Formula 6 can also be used to determine those values.
� how to measure attack and recovery time In this section we will briefly describe the bench procedure for measuring attack and recovery times. Additional information can be found in AN174 in the "Attack and Decay Time" section.
Let's assume that CRECT =2�F and R1NTERNAL=10k. Since T=R. C, then T=20ms. If we wanted a different "RC" time constant we would change the CRECT value (R1NTERNAL is a fixed value).
Using these component values let's measure the attack and recovery times to see if the CCITT and EIA specifications are met.
measurement at compressor: EIA Specifications
Attack time is the time required for the transmitter deviation to settle to a value equal to "1.5" times the final steady state value, for a 12dB step up.
Release time is the time required for the transmitter deviation to settle to a value equal to "O.75" times the final steady state value, for a 12dB step down.

May 29, 1991

544

Signetics RF Communications
Using the NE5750 and NE5751 for audio processing

Application note
AN1741

The compressor must have a nominal attack time of 3ms and a nominal recovery time of 13.5ms as defined by CCITT.
Bench Procedure for Compressor Test
1. Apply a 1kHz sinewave signal at OdB to the input of the compressor (OdB is defined where the compandor passes the input signal through to the output - unity gain level for the APROC is 77.5mVRMS�
2. Modulate the 1kHz input signal with a 1Hz-2Hz square wave.
3. Connect an oscilloscope probe to the input of the compressor and adjust both the modulation and oscilloscope (uncalibrate it) so that a 1:4 ratio is achieved on the screen of the oscilloscope (see Figure 16a).
Adjusting for a 1:4 ratio produces a OdB to 12dB step at the input. The unit "1" represents the OdB input level and the unit "4" represents the 12dB input level (201og (4/1) =12dB).
4. Connect another oscilloscope probe to the output of the compressor and observe the waveform (see Figure 16b). The "final steady-state" value for the attack time is "2" units while the release time is "1" unit. These output values are expected because, for a compressor, the ratio is 2: 1 unless the input is at OdB, in which case, the ratio is 1:1.
5. Now to measure the attack and release time, capture the beginning and end of the output waveform where the changes occur (see Figure 16c and Figure 16d).
To measure the attack time (TAl:
-According to the EIA specifications:
TA = 1.5 � Final Steady- State Value
-therefore
TA = 1.5 � 2 units = 3 units
-Measure the time it takes for the output to drop to the 3rd unit. According to Figure 16c, our attack time is 3ms. This indeed meets CCITT specs..
To measure the release time (TR):
-According to the EIA specifications:
TR = 0.75 �Final Steady-State Value
-therefore

a. Input
�-;r ~r/-~o-+----1
!-+--+- 50ms/dlv l-+-+-
+-+-,._+--1--1--1---1----i....._-1 1 unit
b. Output

__, _ 1---
c. Attack time

!-+-�

J_

1.5

unite

1

jmtlv

---i 13.Smo f---
d. Release time
Figure 17. Expander Dynamic Response

TA = 0.75 � 1 unit = 0.75 units
-Measure the amount of time it takes for the output to rise up to 0.75 units. According to Figure 16d, our release time is 13ms. Again the CCITT spec. is met.
measurement at expander: EIA Specifications
Attack time is the time required for the transmitter deviation to settle to a value equal

to "0.57" times the final steady state value, for a 6dB step up.
Release time is the time required for the transmitter deviation to settle to a value equal to "1.5" times the final steady state value, for a 6dB step down.
The expander must have a nominal attack time of 3ms and a nominal recovery time of 13.5ms as defined by CCITT.
Bench Procedure for Expander Test
1. Apply a 1kHz sinewave signal at OdB to the input of the expander (OdB is defined where the compandor passes the input signal through to the output - unity gain level).
2. Modulate the 1kHz input signal with a 1Hz-2Hz square wave.
3. Connect an oscilloscope probe to the input of the expander and adjust both the modulation and oscilloscope (uncalibrate it) so that a 1:2 ratio is achieved on the screen of the oscilloscope (see Figure 17a).
Adjusting for a 1:2 ratio produces a OdB to 6dB step at the input. The unit "1 � represents the OdB input level and the unit "2" represents the 6dB input level (201og(2/1 )=6dB).
4. Connect another oscilloscope probe to the output of the expander and observe the waveform (see Figure 17b). The "final steady-state" value for the attack time is "4" units while the release time is "1" unit.
5. These output values are expected because for an expander the ratio is 1:2 unless the input is at OdB, in which case, the ratio is 1:1.
6. Now to measure the attack and release time, capture the beginning and end of the output waveform where the changes occur (see Figure 17c and Figure 17d).
To measure the attack time (TA):
-According to the EIA specifications:
TA = 0.57 �Final Steady-State Value
-therefore
TA = 0.57 � 4 units = 2.28 units
-Measure the time it takes for the output to reach 2.28 units. According to Figure 17c,

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Application note
AN1741

our attack time is 3ms. This indeed meets CCITT specs.. To measure the release time (TR): -According to the EIA specs.: TR = 1.5 �Final Steady-State Value -therefore TA= 1.5�1unit=1.5 units -Measure the amount of time it takes for the output to drop to 1.5 units. According to Figure 17d, our release time is 13ms. Again the CCITT specification is met. These results show that the release time is about 4 times slower than the attack time. All Signetics compandors are internally set up this way so that once the attack time is set by CREer, the release time is automatically set.
NE5750
Figure 18. Speaker Ampllfler for theNE5750
I NE5750 I
Pin 121
TO o-J
EARP HON
=- - Earphone Gain Ay R4 R6
= Sideton1: Gain Av -~ R5 Figure 19. Setting Gain for Earphone Amplifier
Special Note: In AN174, Figures 10 and 11 show the X-axis as being in fractions of the time constant. The way to clarify this is by multiplying 20ms to these numbers to convert them to the measured attack and recovery time. The 20ms comes from the "RC" time constant which can be varied by varying the CREeT value. But again, once these numbers

BPF 20
10

.m..
z
~ -10 I!:
m -20 &!
-50 10

1-

IS
~

1

1'

1-

fl

!_\:s:

100

1k

1Dk

Frequency In Hz

100k

Figure 20. NE5751 Tx Bandpass Fiiter

are converted, one can see that these figures show similar results as ours in the lab.

Amplifier Section:

-speaker amplifier The speaker amplifier is a unity gain amplifier with a high input impedance. Located on Pin 11, the output of the amplifier, are two capacitors C5 and C16. Capacitor C5 is for DC blocking, while C16 is for high pass filtering.
Since the amplifier's input is not directly accessible to the designer (see Figure 18), it is impossible to exceed a gain of one. However, if external attenuation is desired, use formula 7 to determine the series resistor that would connect to Pin 14.

Av= -RF

(7)

R1N

-50k

(50k + Rs)

In most cases, the attenuation takes place in the NE5751 before the signal gets to the amplifier. Therefore, adding external attenuation is rare.

-earphone amplifier: Unlike the speaker amplifier, the gain of the earphone amplifier can be set by external resistors. In this case, the required output and input are directly accessible. Figure 19 is a diagram of the earphone amplifier with the required equations. Sidetone gain can also be implemented with an external resistor.

How To Power Down
"Power down" or "power up" can be implemented by Pin 10 of the NE5750. When Pin 10 is connected to Vee. the chip is in the "power up" state. In this mode, the chip is fully functional. However, when Pin 10 is connected to ground, the chip is in the "power down� state where the current consumption drops dramatically (CMOS or TTL levels will suffice). In this mode, the chip is not expected to be functional, but all of the capacitors remain charged so that "power up' can occur quickly. Having this capability allows the system to conserve battery power.
Ill. NE5751
A CLOSER LOOK AT THE NE5751:
Figure 24 shows a block diagram of the NE5751. Key functions for this chip include a TX bandpass filter, TX pre-emphasis filter, TX low pass filter, summing amplifier, RX bandpass filter, RX de-emphasis, programmable DTMF generator, programmable attenuator, and an 12C bus interface.
-TX path The input and output of the TX bandpass filter are located on Pins 3 and 4, respectively. The 4th-order Chebyshev bandpass filter is designed to pass 300 to 3000Hz (voice band). (see Figure 20).
The input to the pre-emphasis circuit is accessible through Pin 5. This filter shapes

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Application note
AN1741

the spectrum with a +6dB per octave slope in

LPF

the pass band (see Figure 21). The output is

then connected internally to a low pass filter

and limiter circuit (see Figure 22). The

functions of the last two filters guarantee that

the 12kHz maximum frequency deviation for

cellular radio is not violated.

The output of the limiter filter (Pin 23) and the

output of the programmable DTMF generator

(Pin 22) can be connected to the input of the

summing amplifier. The gain of this amplifier

can be controlled with external resistors. In

Figure 24, the resistors are all 51 kn which

creates a unity gain configuration. The

output of the amp is then connected to the

transmitter.

10

J:t!!i:20
Min

10
1111
~ !!I
.5
~-10

~

~

'ii-20
~I

f

1

~

100

1k

10k

100k

Frequency In Hz

Figure 22. NE5751 Tx Low Pass Fiiter

PM3320 O"SCOPE
HP3a9A DISTORTION ANALYZER

-50 10

100

1k

1Dk

Frequency In Hz

100k

Fl ure 21. Pre-em hasis Curve

The Limiter and All-pass Circuit: An important aspect of the AMPS specification is concerned with the 12kHz maximum frequency deviation. The output of the APPROC should be less than 12kHz regardless of the input signal. Figure 23 shows the equipment used for the test measurements and how the signal was processed. A 1kHz signal was applied to the input of the demo-board until a 5% distorted signal was measured at the limiter output. This waveform's peak-to-peak voltage was recorded as a reference, then, at various chosen frequencies, the input of the demo-board was overdriven so we could record the distorted peak-to-peak waveform. (See Figure 26)

Formula 8 was used to calculate maximum frequency deviation from the waveforms shown in Figure 26.

Max Freq Dev with All-Pass Ckt =

(8)

where

BWF �8kHz BWR

TRANSMIT PATH
Figure 23. Test Set-up and Tx Path of Signal

BWF =the bottom waveform's peak-to-peak voltage from one of the observed Figures.
BWR =the bottom waveform's peak-to-peak voltage from the reference Figure.

Table 5. Maximum Frequency Deviation Results for the 12kHz Test

Frequency (Hz)

With AH-Pass (kHz)

300

5.91

500

9.04

800

10.09

1000

10.09

1200

10.09

2000

11.13

3000

10.78

Table 5 reveals the calculated results for maximum frequency deviation over the voice band. The test results show that the NE5750 and NE5751 will meet the 12kHz AMPS specification. If a customer needs further

assurance that the 12kHz specification will be satisfied, an Automatic Level Control (ALC) circuit can be placed after the summing amplifier output of the NE5751. Keep in mind, though, that this ALC will only provide attenuation.
�RX path For the receive side of the NE5751, the signal goes to the input of the RX bandpass filter (Pin 13) which has the same characteristics as the TX bandpass filter. The only difference is that this filter also has a stop-band notch filter at 6kHz to reject the Supervisory Audio Tone (SAT) signals as seen in Figure 27.
The output is then internally connected to the de-emphasis filter. This filter provides a -6dB/octave slope over the passband to compensate for the pre-emphasis function (see Figure 28).
The attenuator can be digitally programmed by 12c. The input signal level can be attenuated 16 steps in 2dB increments. This

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Application note
AN1741

NC
l~� Cl8

o2-.12�1F--C+l-.-----;
TXBF1N
~REF

TXBFouT

C2 2.2�F R3

RESET
DTMF GENERATOR

TXLFouT

51kn

TXS1N

Rl3 Slkn

~OUT

2.2�F C23

GND
-=
CLK1N

t

MUTER

sm11_ NC

12C BUS RECEIVER

DA
SCL
~Voo
1 SWITCH
+ 2f.2-�=F ---o
C20 RXBF1N R9 IOOkn
VREF VOXcTL
NC

R10 Input resistor for summing amp out can be used to set gain of signal Input R11 Resistor for summing amp out can be used to set gain of DTMF feedback R13 Resistor for sum amp can be used to set gain of all the Inputs Used to biae up

R2 RR3I } R4
~:
R7 R9

Used to bias respective pins to 2.SV by connecting the other end of the resistor to the
VREF pin without loading down the VREF source

C18 Uaed to AC GNO VREF pin C19 Power supply bypan cap C20 DC blocking cap for Rec input C23 DC blocking cap for sum amp out C24 Power supply bypaas cap

g:CC2l }
CS
C6 C7

Provide_� DC blocking for the respective pine

Figure 24. NE/SA5751 Test and Application Circuit

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AN1741

Table 6. Maximum Frequency Deviation Results for the 12kHz Test

Number Dialed

High Freq.

Low Freq.

1

1209

697

2

1336

697

3

1477

697

4

1209

770

5

1336

770

6

1477

770

7

1209

S52

s

1336

S52

9

1447

S52

. 0

1336

941

1209

941

#

1477

941

DTMFHI A5 96 S7 A5 96 S7 A5 96 S7 96 A5 S7

DTMFLO SF SF SF S2 82 S2 75 75 75 SA 6A 6A

gives a range from OdB to -30dB. The attenuator error is shown in Figure 29.
12c Bus Interface:
The NE5751 is controlled by a serial control bus comprised of a clock input, serial bus address, serial clock line, and serial data line.

A designer who is unfamiliar with 12c can refer to the following documents for assistance: 1) 12C Bus Specification and 2) Signetics AN16S. Both of these documents can be found in the 19S9 Signetics Linear Data Manual or the 1991 RF Communications Handbook.
The clock input requires an input frequency of 1.2MHz. This frequency is vital for the operation of the part because it effects the DTMF generator and the 3dB point of all the switch capacitor filters.
The output of the DTMF generator can be determined by Formula S.

Clock Input Freq

(Sa)

Low Freq = --L=1 ~~-

where LD is the value of the register This translates to: DTMF LO REG= 100000/ LO REG(Hz)

Clock Input Freq

(Sb)

High Freq = -~~~0--

where HD is the value of the register
This translates to: DTMF HI REG= 200000/
HI REG (Hz)
Table 6 can be used to help the designer program the DTMF generator.
There are a few key points that should not be overlooked when programming the NE5751. The control registers consist of the
1. Register map

2. Signal path register
3. Volume control and test register
4. High tone DTMF register
5. Low tone DTMF register
To generate a single tone from the DTMF generator, use the appropriate registers (high or low DTMF) and load the other one with a 'O', '1 ', or '2' to silence it.
The order of these registers is important. If the programmer wanted to turn down the volume, he/she would have to re-program the register map, signal path, and then give the new data to the volume control and test register.
IV. APROC DEMO-BOARD About the APROC demo-board: The NE5750/51 demo-board layout can be
seen in Figure 30, Figure 31, and Figure 32. It incorporates the use of DIP packages. However, an SO adapter could be made to test the SO APROC chips.
A separate board is used to interface the APROC demo-board with the computer's parallel port. This converter utilizes the 74LS05 as a buffer scheme.
An 12C program for the APROC is provided so that a designer can easily program and evaluate the chip set. This eliminates the need to write an evaluation program. However, it does not eliminate the need for a final system program.
The evaluation program has a graphic display that shows the transmit and receive path of the APROC on the terminal, as seen in Figure 33. By selecting a function, one can toggle the space bar on the key board to turn on or off any key features. The designer could also type in the codes for any registers to control the functions.

Figure 25 shows how the interface board and the demo-board can be used in conjunction with a computer. Once everything is connected properly, one can make his own evaluations on the chip set.
e II e
������ �~ 00�� ����� �~� GiiJ l:!:ill illiJ [iii:]
12c
INTERFACE BOARD
00000000 00000000 00000000 00000000 00000000 00000000
Figure 25. Interfacing the APROC Demo-board with the 12C Evaluation Pro ram

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Using the NE5750 and NE5751 for audio processing

Application note
AN1741

REFERENCE

F--300Hz

Lt>. Lt>. Lt>. --"' Lt>.

If r\ I

r\ I

ro IV l\J lY y

A

iu \ I u\

p

\I/ 11

u

A

rJ ~L\

~~ I7L l J

m lfT
J \ IL

B

..lrllll
(V

Jl

h;II

V

B

.F 500Hz

-F- 800Hz

If

rr If

"1
A ~r7

rt 7\ A

rq fO :u rq fO

\jT
,.:n-

Jl:J:
i;:::;;

\
:n

]q Q

ii ii ii ]II ]II

[1 B

fT 1

B

ll [ rv [

T: SOO�o A: 500mV B: 1V

T: 2m�

A: 2V B: 1V

T: 1mo

A: 2V

B: 1V

T:500�o A:2V

8:1V

F: 1kHz

= F 1.2kHz

-F-2kHz

-F-3kHz

I/

rr

A

\.JI \J ~ [!=1 u

-\ t ~ ~ Ill M k

_\

B

;J ~ J. rv- ~

rirI a: ]
r.:fJ[l -\i

pla]:

A
"1:l

h

f'l h

f'l

d�I

I /II B

fTrl

I"'

vc

J [l\:i \ IT

1 A

LSJ- 1u1 LSJ- I'-'

r\7
�-1

'l r\7 A
}[-q

~-f T II 7 '

rr II

[\
7

T.T rTrT

7'i i\ I I/'\

B
T

7 I 7TT

B
I T

l'7

T: SOOllS

A: 2V

B: 1V

T: SOO�o A: 2V B: 1V

T: 200�o A: 2V

B: 1V

T: 200�o

Figure 26. Results From the 12kHz Maximum Frequency Deviation Test

A: 2V

B: 1V

BPF 20

10

0
'II
.E ~ -10
~
li-20
-50 1.0E.01

f

\

I

\

t
l-

~

;...
1.0E.02

1.0E.03

In\

~
\

1.0E.o4

Frequency In Hz Figure 27. NE5751 Rx Bandpass Fiiter

1.0E.OS

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Using the NE5750 and NE5751 for audio processing

Application note
AN1741

M!!

Error Plot 1.0

Min

20

10

!Ii

o. 5

'll

.E

~

,i~jO.ol_...

v

-0.5 -30

-50 Jllj Lil I llJ l 1.oe..01 1.oe..02 1.oe..03 1.0E+04 1.oe..os Frequency In Hz
Figure 28. NE5751 Rx De-emphasis
How to Power Down on the NE5750/51 Demo-Board:
In general, power down mode is a condition where a system has just enough power to "stay alive" and, therefore, is not expected to be fully operational. When called upon, the system can quickly get out of this mode and into the power up mode and be ready to perform its functions. This fast reaction time is possible because all of the capacitors have maintained their charges. This is because power was not cut-off completely. The power down function reduces overall current consumption when the system is not fully operational, and is especially helpful when the system is operating from a battery powered source.
There are three power down conditions when we refer to to the NE5750/51 demo-board. They are listed and described as follows:
1. NE5750 Power Down
Purpose:
- to reduce current consumption
- to maintain all DC voltages on the device pin to keep the capacitors charged
How To:
- use hardware switch on demo-board which forces Pin 1Oto ground
- or use a CMOS logic output into Pin 10
Benefits:
- reduces current consumption while maintaining readiness

-1 .0 0

12

16

20

Attenuation in dB

24

28

Figure 29. NE5751 Attenuation Error

- current drops from 8.4mA to 1.SmA (typically)

1. The transmitter and receiver are muted on the NE5751

Mode of Operation:
- Everything is semi-functional, although performance is not, and will not be, guaranteed
2. NE5751 Power Down
Purpose:

2. The NE5751 is powered down (all registers are set to zero), and
3. The NE5750 is powered down
How to Power Down the Chlp�Set Properly (1st Choice): Please follow this recommended sequence;

- to reduce current consumption
- to maintain all DC voltages on the device Pin to keep the capacitors charged up
- to open all voice paths so that no signals will flow

1. Mute both the transmitter and receiver on the NE5751.
2. Program the following registers as follows:
Signal Path Register: 00000000

How To:

Volume Control Register: 00000000

- program the 12c bus under the condition that all registers are set to zero

High DTMF Register: 00 Low DTMF Register: 00

Benefits:

3. Power Down the NE5750.

- all the registers are always at zero when powering up from the power down mode
- reduces current consumption while maintaining readiness
- current drops from 2.7mA to 1.1 mA (typically)
Mode of Operation:
- Everything is semi-functional, although performance is not, and will not be, guaranteed

How to Simulate the Power Down on the Chip-Set (2nd choice)* Please follow this recommended sequence; 1. Program the following registers as follows:
Signal Path Register: 00010000 Volume Control Register: 01100000 High DTMF Register: 00 Low DTMF Register: 00

3. Chip-Set Power Down

2. Power Down the NE5750

Definition:
-the NE5750 and NE5751 demo-board is in the power down mode when:

�NOTE: this method is only used when the NE5751 mute switches are not accessible, by design.

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Application note
AN1741

Comments
1. Muting both the transmitter and receiver on the NE5751 can be done by the two "hardware" switches on the demo-board (forces Pins 11and12 to Vee).
2. Powering down the NE5751 can be done by programming the correct assigned register to zero (For more details, consult the NE5751 data sheet).
3. Powering down the NE5750 can be done by the "hardware" switch on the demoboard (forces Pin 10 to ground).
4. When coming out of the power down mode to the power up mode, reverse the procedure given above.
5. If functions are activated while in the power down mode before power up occurs, the "chip-set power down" is no longer valid.
6. We recommend that a 2.2�F capacitor be placed between the NE5751 de-emphasis output to the NE5750 expander input. The purpose of this capacitor is to block any DC offset that might occur between the two chips while in the power down mode. If this capacitor is not used, an abnormal reaction might occur where white noise is generated.
V. NE5750 DEMO-BOARD Figure 34 shows the layout for the NE5750 demo-board. This board can be used to evaluate the NE5750, alone, and allows the designer to do extensive testing without having to worry about other external factors. Again, this board makes use of dip packages only. However, a SO adapter can be made to implement the SO version of the NE5750.
VI. QUESTION AND ANSWER SECTION
NE5750 and NE5751 (APROC): Q: Is it OK to connect the VREF pins
together for the NE5750 and NE5751? My circuit seems to be working properly.
A: No, this is not a good idea. Although both VREFS are at 2.5V (VREF =Vcc/2), there is no guarantee that they will be exactly equal over temperature. One of the VREFS might influence the function of the other chip which, in turn, might have a detrimental effect on the performance of the chips.

Q: Will the APROC chip set work for TACS, NMT or NAMPS specifications as it does for AMPS specification?
A: The APROC was designed to meet AMPS and TACS specifications, however, as it stands now, the chip set will also meet the NAMPs requirements. The chip set will not work for NMT specifications.
Q: In the power down mode, is it OK to program the DTMF registers before powering up?
A: No. This will break the rules of powering down. All the registers are set to zero in this mode. Please review the section on powering down the chip set properly.
NE5750: Q: Even though I have all the required
external components in place on Pins 1,2,3,4,5,6 and 7, my VOX circuit does not work. What is wrong?
A: The VOX circuit is not a trivial connection. Even though all the components are connected, be sure that the output of the NE5750 noise canceller is AC coupled to the input of the compressor to complete the VOX loop. This holds true if the NE5750 is used alone. However, if the NE5751 is used make sure that the signal is fed from the band-pass filter to the input of the NE5750 compressor input. For further advice, please read example 1 in the "setting the threshold" section of this application note.
Q: Do I have to use 12c if I use the NE5750 alone?
A: No, the NE5750 can be used by itself and does not require the use of 12c.
Q: ~e
~
A: Not directly. The release time is dependent on the attack time setting. Once the attack time is set by C11 on Pin 22 of the NE5750, the release time is set internally to be four times slower. So to increase the release time requires that the attack time be increased. One should be careful because setting the

attack time too fast could cause more distortion on the output.
Q: The NE5750 compressor input impedance is around SOkn. Why is this impedance higher than that of others in your family of compandors?
A: The NE5750 was designed to be compatible with the NE5751. The NE5750 compressor input was modified to accept CMOS driven outputs like the NE5751. This internal modification eliminates the need for an external buffer.
NE5751: Q: Can I change the filter characteristics?
~
A: Yes, by changing the master clock input frequency the 3dB points will be effected. For example, if F=1.2MHz, then BPF1=3kHz. Now, if F=600kHz, BPF1 =1.5kHz; and if F=2.4MHz, BPF1 =6kHz. This type of application is not recommended because the part was not designed to be used this way and, therefore, performance will not be guaranteed. Additionally, the DTMF generator will be off in frequency from calculated values because of the assumption of a 1.2MHz clock, and the 12C interface will not be functional.
Q: Besides 12C, can I communicate to the NE5751 with another type of operating scheme?
A: Yes, by bit banging. Instead of using the 12C hardware one can supply the clock and data defined in the 12C protocol software. But this takes up a lot of memory, therefore, it is preferable to implement the 12c hardware.
Q: The limiter seems to work when I overdrive the input with a strong signal. However, when I try to pass DTMF tones, the limiter's level varies when switches T3ff5 and T4 are set to different settings Why is this? Isn't the output supposed to stay constant regardless of the input being overdriven or passing DTMF tones?
A: Yes, the limiter should hold the output constant when an overdriven signal is applied, but only when the switches are

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Signetics RF Communications
Using the NE5750 and NE5751 for audio processing

used properly. When passing DTMF tones, T1, T2, and T4 should be left open, while T3/T5 are closed. The voice path should be disconnected when DTMF tones are being passed. Hence, T3/T5 should be left open when DTMF is not used.
Q: When I program a DTMF tone, it only stays on for 96ms. How can I make it stay on longer?
A: The way to make it stay on longer than 96ms is to re-load the DTMF registers (re-program the DTMF registers before 96ms expires).
REFERENCES:
"Audio Processing for Cellular Radio or High Performance Transceivers", proceedings of R.F. Expo 1989, A. Fotowat, S. Navid, L. Engh, pp. 195-203.
"Designing Cellular Radios with the Philips Components-Signetics Cellular Chip Set", Cellular Radio Chip Set Design Manual, Feb. 25, 1990.

<OOX-> ex:x�>
TOP VIEW

Application note
AN1741

May 29, 1991

BOTTOM VIEW Figure 30. Layout of the APROC Demo-board
553

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''<"
J"D'
'~�

MICROPHONE
~~220nf 1
,,
.a�
c:
al
~

z

m
"'....

R1
vox

10k

p OUT
"'z

T+Vcc

6

..m

"'UI

vox ;
CONTROL

5.6k 7

""...''. I~
. !
:D
sa�.
,,),,>

R4

8 GND

~�F 9

VREF

10

lr
!s!�t

11

:J

12

9.

il
S�

J 10� F
SPEAKER

220n

OUT

C2 I�F EAR OUT

SIDE TONE

VREF

NE5750 APROC

C1~ 15 2.2 � F
14 13 R8

RS 51k

s1:S

I l_;cc

"
sto:7:Ne

I~l

MUTE

FROM SAT
)I.
R12 51k

vox
ENABLE

>:
VREF

FROM RECEIVER
TO
vox
CONTROL

w.

c
rJ)
-5�
co
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CD
z
m

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0 :J :J

0

It

Signetics RF Communications
Using the NE5750 and NE5751 for audio processing

Application note
AN1741

O O fi30 O O

� ~�1e.�.:!�:~1~M=�~:� �

cs

~ irio

0

mo

��

oo--vvv-o

R2 0-VVV-00

0 +0 C12 0

00--VVV-0R11

R3 0-VVV-00

0

C13 0

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~ R4l~ l5~"a0~C~7 o00 '5! �o0 igJi C214

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g 0
o

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0 ; c 2 0 F o o o ! P1

c21 swl 000 I I 000 lsw i::::I

0

swl 000

000 !sw ~P2.

Component Values

C1 0.1�F C2 10�F C4 0.22�F CS 4.7�F C7 1S�F
C8 10�F C9 10�F C10 0.22�F C12 2.2�F C13 2.2�F C14 2.2�F C16 100pF C17 2.2�F C1s 10�F C19 .1�F
C20 0.22�F C21 10�F C22 .022�F C23 2.2�F
C24 10�F

R1 10kn
R2 43lcn
R3 4.3kn R4 S.Skn RS S1kn
R6 270kn R7 1kn
RS 51kn
R9 100kn R10 S1kn R11 51kn
R12 S1kn R13 S1kn R14 OPTIONAL
J1 JUMPER J2 JUMPER IC NE5750 NARROW
24-PIN SOCKET IC NE57S1 WIDE
24-PIN SOCKET P1 4 PRONG HEADER P2 4 PRONG HEADER SW MINI SLIDE SWITCH

Component Functions
R1 PUii-up resistor for VOXour logic levels R2 Seta gain of VO~ but for lntemal use only effects voltage on Pin 4 R3 Used to aet releaee time of VOX R4 Seta threehold level of VOX RS Feedback realator for e.r amplifier RS Seta gain of ear amplifier for the aide tone Input R7 Used In conjunction with C10 to filter out unwanted noise. Opdonal R8 Seta gain of ear amplifier R9 Used to bias up Pin 14 to 2.SV by connecting VTHRESH to VREFWithout
loading down VREF source R10 Input resistor for summing amp out. Can be used to eet gain of signal R11 Input reelator for summing amp out. Can be used to eet 1he gain of the OT.MF R12 Input resistor for summing amp. Can be used to aet gain of the aide tone Input R13 Feedback resistor for summing amp. Can be used to set gain of all the inputs R14 Used to set gain of 1he preamp of NE5750 (OPTIONAL)
J1 JUMPER J2 JUMPER

C1 Bypaaa cap for VCC of NE5750
C2 BypeH cap for Vee of NES750
C4 DC blocking cap for mlc Input CS DC blocking cap for mlc gain setting realator C7 Used to set attack a releaee time of VOX
C8 Uoed to AC ground the VREF pin (S750)
ea DC blocking cap for speaker out
c10 filter for speaker out C12 Seta attack and reteaae time of compreaaor C13 Used to AC short the DC path for the compre. .or C14 Provides AC path to the VOX circuitry C16 OPTIONAL Baeically to filter out noise C17 Seta attack and release time for the expandor
C1S Uoed to AC ground VREF pin (S7S1)
C19 Bypeaa cap for Vee of NE5751
C20 DC blocking cap for receiver input
C21 DC blocking cap for ear amplifier output C22 Sets gain of VOX. lntemal use only C23 DC blocking cap for summing amp out
C24 BypaH cap for Vee of NE5751

NOTE: The board la constructed In such a way ae to allow a single power supply to power the chip set. or for each chip to be powered by a separate power supply. Using separate power supplies will pennlt monitoring of current consumption of each part when Jumpera 3 and 4 are removed.

May 29, 1991

Figure 32. Parts and Function List of APROC Demo-board 555

Signetics RF Communications
Using the NE5750 and NE5751 for audio processing

Application note
AN1741

I I APROC NE5750/NE5751

SLAVE ADDRESS = 80

l"PciWEiil
~

T3

DTMFFREQ HIGH:OFF LOW:OFF

T4~ '/ SUM

MOD

' / AMP TS

I I SIGNAL PATH REGISTER 00000000
VOLUME REGISTER
I I �0000000
DTMF REGISTERS
BB

...
MICIN
0

Figure 33. Graphical Display of the 12C Evaluation Program

NCAN

COMP

SIDE

OUT

IN

TONE

000

May 29, 1991

NE5750
Figure 34. NE5750 Demo-board Layout
556

Signetics RF Communications
Using the NE5750 and NE5751 for audio processing

Application note
AN1741

0
SIGNETICSIPllUPS llC INTERFACE

00~~ :~000000 00 0 00000000

0 0
0 0 0 0
0
a0 0

00000
RK~~ 12CSLAV
00

Flgure35.

May 29, 1991

557

Signetics RF Communications
Paging decoder

Development Data
PCASOOOAT

GENERAL DESCRIPTION
The PCA5000AT is a fully integrated decoder for the CCI R Radio Paging Code number 1 (POCSAG-code). It supports two basic modes of operation:
Alert-Only-Pager. This is a stand-alone mode in which the PCA5000AT scans inputs from three external switches that relate to the states ON, OFF and SI LENT. Only a few external components are required to build an Al-ert-Only pager.
Display-Pager. In this mode, received calls and messages are transferred via the IC's serial communication interface to an external microcontroller. A built-in voltage converter can double the supply voltage output and perform level shifting on the interface signals.
Call-alert cadences are generated when valid calls and messages are received, and status cadences to indicate the present state of the decoder are generated following a status interrogation. An on-chip 5 x 9-bit static RAM with battery back-up is provided for programming two user-addresses and for special functions. Synchronization of the input data stream is achieved by the built-in ACCESS algorithm which allows data to be synchronized without preamble detection and minimizes battery power consumption by receiver-enable control. One of three error correction algorithms is applied to received code words to optimize the call success rate.
The PCA5000AT is fabricated in SACMOS-technology to ensure low power consumption at low supply voltages. Typical applications are alert-only pagers, numeric/alphanumeric display pagers, cellular radio and data/telemetry decoders.
Features
� Wide operating supply voltage range (1.7 to 6.0 V) � Very low supply current (15 �A typ.) � Decodes CCI R Radio Paging Code number 1 � Data rate: 512 bits/s � Powerful 'ACCESS' synchronisation algorithm � Supports two user addresses � Four cadences per user address � Silent call storage, up to four different calls � Interfaces directly to the UAA2033 digital paging receiver � Directly drives a 2 kHz bleeper � High-level alert facility requires only a single external transistor � Receiver-enable control for battery economy � On-chip static RAM, non-volatile with battery back-up � On-chip voltage converter � Level-shifted microcontroller interface � Battery-low alert � Out-of-range indication (optional)

PACKAGE OUTLINE 28-lead mini-pack; plastic (S028; SOT136A.)

May 1991

558

Signetics RF Communications
Paging decoder

CP

CN

l

l

27

26

VOLTAGE CONVERTER

PCASOOOAT

Development Data
PCA5000AT

DIGITAL INPUT FILTER
F~

SERIAL DATA PROCESSOt:l

SERIAL

20 DO

COMMUNICATIONS r--~~"t

INTERFACE

MASTER DIVIDER

CLOCK RECOVERY

PREAMBLE/SYNCHRONIZATION/ADDRESS DETECTION CONTROL

DATA OUTPUT CONTROL
J

22 OS

J

___ ~
x~.___

osc

....

RAM ADDRESS COUNTER

.
.___+-+---I BIT/CODE WORD/BATCH
TIMING CONTROL

.

I ~ ~

SYNCHRONIZATIONti...! OR

CONTROL

I " t-"

L

l

RAM INPUT/OUTPUT
REGISTER

FRAME DETECTOR
l

TEST

7 TS

CONTROLt--t-

ALERTER CONTROL

RECEIVER

~E

POWER CONTROL

5 x 9-bit
RANDOM ACCESS MEMORY

SWITCH CONTROL
BATTERY
~ LEVEL ~
DETECTOR

ALERTER INTERFACE

v~
VVos~ s.!13:!f+AN-LDEjV,SEU_LP_DP~EL~TYE~SC~WT~OIT-RC-H'
J21
l
n.c.

.
'--
18 17 16 12 15 ON OFF SK BS BL

14

19

8

Al

as OR

11 AL 7Z81681.1

May 1991

Fig. 1 Block diagram.
559

Signetics RF Communications
Paging decoder
PINNING

pin
1 2 3 4 5
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
May 1991

mnemonic
Vs PR DI WR
X1 X2
TS QR OR RE AL BS
Vss Al BL SK OFF ON as DO n.c. DS FL PC
VREF CN CP
VDD

Development Data
PCASOOOAT

VDD CP CN

VREF PC

FL
DS PCASOOOAT
n.c.
DO
as
ON
OFF
SK

BL

description

Fig. 2 Pinning diagram.

RAM back-up negative supply voltage programming enable input serial data input programming WRITE input oscillator input oscillator output test mode enable input alert high-level.output/vibrator output out-of-range output receiver enable output alert low-level output battery sense input negative supply voltage alarm input battery-low output silent key/mute input off key/reset input on key/on-off input vibrator enable input received data output not connected received data strobe output frequency reference output power control input to voltage converter microcontroller interface negative reference voltage voltage converter external capacitor (negative) voltage converter external capacitor (positive) positive supply voltage (common)
560

Signetics RF Communications
Paging decoder

Development Data
PCASOOOAT

FUNCTIONAL DESCRIPTION
Operating modes The decoder has two basic operating modes; alert-only-pager and display-pager. There is also a programming mode in which the contents of the internal RAM are programmed or verified. The RAM holds two user-addresses and special function bits.
Alert-Only-Pager No external microcontroller is required in this mode. Tone-alert cadences are generated when valid calls are received. Four different alert cadences are available and are called by combinations of the function bits. The voltage doubler is disabled in this mode. The decoder continually scans the inputs ON, OFF and SK from the external switches ON, OFF and SI LENT that determine the internal operating status. Operating one of the switches first causes the cadence of the existing internal status to be generated and then, after 1.5 s switch operation, generation of a cadence to indicate the new internal status of the decoder.
Display-Pager
In this mode the decoder receives calls/messages and directs those addressed to one of the two stored user addresses to an external microcontroller for post-processing and display. Tone-alert cadences are generated when valid calls are received. The decoder provides a doubled supply voltage output to the microcontroller and associated hardware, and the interface signals are level-shifted to allow direct coupling to the microcontroller. The internal state of the decoder is determined by the logic levels on the static inputs ON and SK.
Internal states If the decoder is in one of the two operating modes, its internal status is always one of the following:
OFF state. This is the power-saving inactive state in which no decoding takes place and the paging receiver is disabled. Scanning of the ON, OFF and SK inputs is maintained to allow state-changes to be effected. ON state. This is the normal active state of the decoder. Received calls and messages are compared with the two user addresses stored in the RAM. When the validity of incoming calls is confirmed, appropriate cadences are generated and data is shifted out via the serial microcontroller interface. SI LENT state. This is the same as the ON state except that alert cadences are not generated following valid calls. Instead, if programmed as an alert-only pager, the decoder stores up to four different calls. The appropriate alert cadences are generated after the decoder has been returned to the ON-state. However, special silent override calls will cause generation of alert cadences.

May 1991

561

Signetics RF Communications
Paging decoder

Development Data
PCA5000AT

POCSAG code structure
A transmission using the CCI R Radio Paging Code No. 1 (POCSAG code) is structured according to the following rules (see Fig. 3)
The transmission is started by sending a preamble which is a sequence of at least 576 continually alternating bits (01010101 ...). The preamble precedes a number of batch blocks. The transmission is terminated after the last batch.
Every batch comprises a synchronisation code word with a fixed 32-bit pattern followed by eight frames (numbered 0 to 7). Only complete batches are transmitted.
A frame comprises two code words, each 32 bits long. A code word is either an address, message or an idle code word. Idle code words are transmitted to fill empty batches or to separate messages.
An address code word is coded as shown in Fig. 3; 18 bits of the 21-bit user address are coded in the code word and are protected against transmission errors by a CRC check word (bits 22 to 31 ). The other three bits of the user address are coded in the number of the frame in which the address code word is transmitted. Two function bits (bits 20 and 21) allow distinction between four different calls to one user address.
A message code word contains 20 bits of any information, these are also protected by a check word.

preamble

1st batch

2nd batch

a) Call structure 1 batch = 17 code words

subsequent batches

-

'-synchronization code word

.. ... ' - - - 1 frame= 2 code words b) Batch structure

bit

1

0

2 to 19 user address

20 21 FC FC

22 to 31

32

parity check

c) Address code word structure (FC are function code bits)

bit

1

1

May 1991

2 to 21 message

22 to 31

32

parity check

d) Message code word structure
Fig. 3 POCSAG coding structure.
562

Signetics RF Communications
Paging decoder

Development Data
PCA5000AT

FUNCTIONAL DESCRIPTION (continued)
Decoding
The POCSAG-coded input data is first noise-filtered by a digital filter. A sampling clock, synchronous to the 512 bits/s data rate, is derived from the filtered data.
Synchronization is performed on the POCSAG code structure using the ACCESS algorithm, which is a five-stage state mechanism.
The decoder first searches the data stream for preamble or synchronization code word patterns. Before synchronism can be achieved, the decoder must ascertain that synchronization code words are correctly positioned at the beginning of each batch. When the correct structure is detected, the decoder switches to the 'receive mode'. (The receiver enable output (RE) is active before input data is required.) Error correction algorithms are applied to the data. If synchronization is lost (i.e. no synchronization code word found at the beginning of the next batch) the decoder enters a two-step recovery mechanism. In the first step, over the next 15 batches, the decoder attempts to resynchronize by bit-wise shifting its frame window. A 'carrier off' state is entered in the second step, in this the data stream is tested convolutionally for a preamble or synchronization code word at every effective bit position within a continuous stream of at least 17 batches. When synchronization is regained, the decoder returns to the 'receive mode'.
In the 'receive mode', the input data stream is sampled at the frame position pointed to by the RAM program and the sampled code words are error-corrected. If they are address code words, they are compared with the two user addresses from the RAM. If the result of this comparison is 'true', the following actions take place:
� a store is set for a call-alert cadence. The cadence will relate to the combination of the function bits in the accepted code word but will not be generated until the call has been terminated;
� the receiver enable output (RE) is held active so that reception of the call can continue. This condition remains until - another address code word or an ID LE instruction is received - the error-correction algorithm fails to generate a code word - synchronisation is lost;
� message code words attached to the validated address code word are transferred via the serial communication interface to the external microcontroller.
Programming
The on-chip RAM is organized in five 9-bit words (Fig. 4). It is used to store two user addresses (receiver identification codes) and six programmed special function bits. A lithium back-up battery maintains data retention when the main power supply is removed.

May 1991

563

Signetics RF Communications
Paging decoder

Development Data
PCASOOOAT

bit 8 word 0 A08 word 1 A17 word 2 808 word 3 817 word 4 FR2

bit 7 A07 A16 807 816 FR1

bit6 A06 A15. 806 815 FRO

bit 5 A05 A14 805 814 SP6

bit 4 A04 A13 804 813 SP5

bit 3 A03 A12 803 812 SP4

bit 2 A02 A11 802 B 11 SP3

bit 1 A01 A10 801 810 SP2

bit 0 AOO A09 BOO 809 SP1

where:

AXX are 18 bits of user address 'A' BXX are 18 bits of user address 'B' FR2 to FRO are frame number bits common to both addresses'A' and 'B' SP6 to SP1 are special function bits.

Fig. 4 RAM organization.

A user address in POCSAG code comprises 21 bits, three of which are coded in the frame number. In the PCA5000AT the frame number is common to both user addresses.

The special function bits are programmable to select from the following:

bit SP1: 0 alert-only-pager mode; silent override enabled on address 'B' 1 display-pager mode

SP2: 0 enable voltage converter (SP1 = 1)
1 disable voltage converter (SP1 = 1); cadence 1 also for FC = 11

SP3: 0 1-bit error-correction on message code words 1 4-bit burst error-correction on message code words on address 'B' (FC = 00 or 11)

SP4:

free for user-application

SP5: 0 silent override enabled on address 'B' (FC = 01 or 10) 1 silent override enabled on address 'B' (FC = 00 or 11)

SP6: 0 silent override disabled on address 'A' (FC = 10) silent override enabled on address 'A' (FC = 10)

The programming mode is entered by holding input PR at VDD during power-on; exit from the programming mode is made by removing the main power supply. The back-up battery must remain connected to the PCA5000AT to keep the RAM contents when the main power supply is removed. During programming, inputs ON, OFF and SK must not all be '1' at the same time.

Programming of the RAM and verifying its contents is performed in a sequence starting with word 0, bit 0 and progressing through each of the five words in turn. Input and output is a serial operation; X1 is the shift clock input and DI, DO are respectively the data input and output.

During the RAM programming operation, a negative-going pulse first on WR and then on PR copies the 9 bits just shifted in into the RAM and switches to the next word (see Fig. 10).

During the RAM verify operation, reading the first word is triggered by a negative-going pulse on PR, which also switches to the next word in the sequence after 9 bits have been read (see Fig. 11 ).

Exit from the programming mode should be made after programming or verification of the RAM contents has been performed on all five words.

May 1991

564

Signetics RF Communications
Paging decoder

Development Data
PCA5000AT

FUNCTIONAL DESCRIPTION (continued)

address decimal value (example: address 'A'= 105 decimal)

l I binary equivalent (18 + 3 bits available) (example: 000000000000001101001)

l
J

-

t 0 RAM Iocat"ion

..

AOO A01 A02 A03 A04 A05 A06 A07 AOB A09 A10 A11 A12 A13 A14 A16 A17 FRO FR1 FR2

0 0 0 0 0 0 0 0 0 0 0 0 0 1 10 10 0 1

Fig. 5 Example of bit conversion in user address programming.
Generation of output signals
Alerter interface
The alerter interface provides for the acoustic signalling of calls received (Fig. 8) and of changes of pager status (Fig. 9).
When valid calls are received and the pager is in the ON state, the decoder generates 2 kHz squarewave output signals to produce tone alert cadences via a magnetic or piezoceramic 2 kHz bleeper. The cadence signals differ in modulation according to the two function bits FC in the address code word (Fig. 6b). The PCA5000AT supports two levels of alerter loudness: during the first four seconds, cadences are generated at low intensity (output AL active, output QR inactive); during the following twelve seconds, the intensity is increased (outputs AL and QR both active).
The alert tone generation is automatically terminated after sixteen seconds. Alert cadences are also terminated by an ON, OFF or SI LENT input when in alert-only-pager mode, or by pulsing the status/reset input in display-pager mode.
If the call is a message with subsequent message code words, alert cadence generation begins after the message has been terminated.
The alerter generates cadences to indicate the present internal status when interrogated and, when the main supply is low, gives a battery-low indicator output and generates an alarm tone.

May 1991

565

Signetics RF Communications
Paging decoder

Development Data
PCA5000AT

Serial communication Interface
This interface facilitates communication with an external microcontroller. Data is transmitted serially in the format shown in Fig. 6.
After receiving a valid address code word, transmission commences by sending a start command. The start command contains function data from the RAM, user address called (A or B) and function control bits FC from the address code word. The transmission continues with message words that contain the data from the received message code words. The end of a message transfer is marked by the sending of a stop command or another start command. In a stop command, bit 2 indicates that the call was successfully terminated.
I-frame 6 -I-frame 7 -I

data input data output

A IA

M

M

M

SC

M

M

A

A

0 LJ u
start command

[]
message words

[] [] D stop command

a) Message format

bit

0

1

2

3

4

5

6

7

user

address address

0

1

SP3

SP6

SP5

address bit 20 bit 21

A or B (FC)

(FC)

b) Start command format

bit

4 to 23

message code word bits 2 to 21 as received

c) Message word format

bit

0

1

2

3

4

5

6

7

0

0

successful term in-

O- S input

SP4

SP2

not used

not used

at ion

d) Stop command format

Fig. 6 Serial communication interface.

May 1991

566

Signetics RF Communications
Paging decoder

Development Data
PCASOOOAT

RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134) Voo is referred to as 0 V (ground)

parameter

symbol

min.

max.

unit

Supply voltage

Vss = V13-28 +0.5

-7.0

v

RAM back-up supply voltage

Vs

Vss + o.8 -6.0

v

Input voltage on pins

ON, OFF, SK, Al, PC, FL, BL,

OS, DO

V1

0.8

VREF-0.8 v

Input voltage on any other pin

V1

0.8

Vss-0.8

v

Power dissipation per output

Po

-

100

mW

Total power dissipation

Ptot

-

250

mW

Operating ambient temperature range Tamb

-10

+60

oc

Storage temperature range

Tstg

-55

+ 125

oc

CHARACTERISTICS: Alert-Only-Pager (SP1=0)
Voo = 0 V; Vss = -2.7 V;VREF =-2.7V; Vs= -3.0 V;Tamb = 25 oc;quartz crystal f = 32.768 kHz, Rsmax = 40 kn, Cl (Fig. 12) = 8 to 40 pF

parameter

conditions

symbol min.

typ. max.

unit

Operating supply voltage range

Vss

-1.7

-2.7 -6.0

v

Operating supply current

all outputs open;

all inputs at Vss;

voltage converter off lss

-

-

-22.0

�.A

Level at which RAM switches to Vs

Vss(swl -1.0

-

-1.7

v

Supply current; peak value

AL= LOW

issM

-

-

-45.0

mA

Input voltage LOW

PR, DI, BS, OS, WR, TS Al, ON, OFF, SK, PC

VIL

0.1 Vss -

-

v

V1L

0.7 VREF -

-

v

Input voltage HIGH PR, DI, BS, OS, WR, TS Al, ON, OFF, SK, PC

V1H

-

V1H

-

-

o.3 Vss v

-

0.3 VREF v

May 1991

567

Signetics RF Communications
Paging decoder

Development Data
PCASOOOAT

CHARACTERISTICS: Alert-Only-Pager (continued)

parameter

conditions

symbol min.

typ. max.

unit

Input current PR, TS, BS WR DI
PR, TS, BS, DI, OS, PC WR, OS, PC Al, ON, OFF, SK, Al, ON, OFF, SK
Input capacitance BS, DI, PR, WR, OS, TS Al, ON, OFF, SK, PC X1
Output current LOW RE, OR, OR DO, DS, BL, FL AL
Output current HIGH RE OR,OR DO, DS, BL, FL AL
Output capacitance X2
l--------~------~--~-

Vi= vDD Vi= Vss Vi= vDD; VRE = Vss Vi= Vss Vi= vDD Vi= vDD Vi= Vss

11

7.0

-

18.0

�A

11

-9.0 -

-28.0 �A

11

6

-

16

�A

11

-

-

-0.1

�A

11

-

-

0.1

�A

11

6.0

-

16.0

�A

11

-

-

-0.1

�A

C1

-

C1

-

C1

-

-

5

pF

-

5

pF

-

5

pF

Vol= -1.35 V Vol= -1.35 V Vol= -1.5 V

loL

10.0

--

-

�A

loL

10.0

-

-

�A

loL

17 .5

-

41.5

mA

VoH = -1.35 V

-loH 10.0

-

-

�A

VoH = -1.35 V

-loH 10.0

540 7.50

�A

VoH = -1.35 V

-loH 10.0

-

-

�A

AL= high impedance -loH -

-

0.2

�A

------ -

Co

19

-

23

pF

------�- --- �------- -�- - --- --- -- �---� -- ..--.�--��-�-�� - --------

CHARACTERISTICS: Display-pager; alphanumeric mode (SP1=1, SP2 = 1)
CN and CP open circuit; VDD = 0 V; Vss = -3.0 V; VREF = -6.0 V; Tamb = 25 oc; quartz crystal f = 32.768 kHz, Rsmax = 40 kn, C1 (Fig. 13) = 8 to 40 pF

parameter

conditions

symbol

min.

typ. max.

unit

Operating supply voltage range

Vss

-1.7

-

-3.0

v

Microcontro Iler interface negative reference

VREF

Vss

-

-6.0

v

Input current

Al, ON, OFF, SK V1 = VREF or VDD 11

-

-

0.1

�A

May 1991

568

Signetics RF Communications

Development Data

Paging decoder

PCA5000AT

CHARACTERISTICS: Display-pager; numeric mode (SP1 = 1, SP2 =0)
220 nF capacitor connected to CN, CP;
VDD =0 V; Vss =-3.0 V; Tamb =25 OC; quartz crystal f =32.768 kHz, Rsmax =40 k.Q, C1 (Fig. 13) =8 to 40 pF

parameter

conditions

symbol min.

typ.

Operating supply voltage range
Voltage converter VREF output: output voltage
output current
Input current Al, ON, OFF, SK

Vss

-1.7 -

Vss =-3.0 V; no load
Vss =-2.0 v;

VREF -5.95 -

I V REF = 150 �A; PC =0 VREF -2.7 -
Vss =-2.0 v;

IVREF =45 �A; PC= 1 VREF -2.7

-

Vss =-2.0 V; PC= 0 Vss =-2.0 V; PC= 1

IVREF -150 -

IVREF -45

-

V1 =VREF or VDD

11

-

-

TIMING: Display-pager (SP1=1)
VDD =0 V; Vss =-2.7 V; Tamb =25 �C; quartz crystal f =32.768 kHz, Rsmax =40 k.Q, C1 (Fig. 13) =8 to 40 pF

max. unit
-3.0 v

-6.0 v

-v

-v

-

�A

-

�A

0.1 �A
.~

parameter

conditions

Oscillator frequency Alerter frequency Data input rate Frequency reference
FL output Data input transition time Preamble duration Batch duration Bit period Data output rate Data output transition time Data strobe clock period Data output set-up time Data strobe pulse width Data hold time Call alert period Call alert (low level)
AL output only Call alert (high level)
QR and AL outputs

CL= 5 pF

May 1991

569

symbol min.

fosc

-

falert -

fD1

-

fFL tTDI
tBAT tBIT fDo tDTO tDs tDos tDsw tDH tALT

1125 -
-
61 30.5 -

tALL -

tALH -

typ. max.
32.768 -
2048 -
512 -

unit
kHz Hz
bits/~

16.384 -

-

100

-

-

1062.5 -

1.9531 -

512 -

-

100

1.9531 -

1.77 -
122 -

61

-

16

-

kHz �s ms ms ms bit/s ns ms ms �s �s s

4.0 -

s

12.0 -

s

Signetics RF Communications
Paging decoder

Development Data
PCA5000AT

parameter
Call alert cycle period Call alert pulse period Status pulse set-up time Status pulse duration Status alert period Status alert delay Receiver control RE
transition time RE establishment time Programming:
data clock period data settling time write set-up time write pulse width program input pulse width program input settling time Power-on reset pulse width Program start delay time Program data hold time Data clock period LOW

conditions CL= 5 pF

symbol
tALC tALP tsTP tSTD tSTON tSTOF

min.
-
-
10.0 10.0
-

tRXT

-

tRXON -

tpoc tpos twsu twp tpR tPRS tPQR tcsu tpoE tx1

-
20.0 20.0 I 10.0 10.0 20 7.5 20.0 10.0 10.0

typ.
1.0 125 330 330 62.5 62.5
31.2
100 -
-
-
-
-
50.0

max. unit

-

s

-

ms

-

�s

-

�s

-

ms

-

ms

100 ns

-

ms

-

�s

-

�s

-

�s

-

�s

-

�s

-

�s

-

�s

-

�s

-

�s

-

�s

May 1991

570

Signetics RF Communications
Paging decoder

Development Data
PCA5000AT

data output
DO
data strobe
DS

-

--1 1-trno

--1 1- ~I
u r - - - - u 1oos--1� ~ 1os ----->-

tosw

Fig. 7 Serial communications interface timing.

7Z81683.1

May 1991

____ tALC
cadence 2
(FC = 01)
cadence 3
(FC = 10)

cadence 4
(FC = 11)
Fig. 8 Call alert cadences; FC refers to function control bits 20 and 21 in the address code word.

7Z81685.1

~,_ ON

_ _ __ : - - - -

~ 1.._tSTON

OFF~,____;!----:___~,_____
1.._tsTOF~

_:-----1.____ ~,_ SILENT ___: - - - :___

__.f-----

7Z81686

Fig. 9 Status indication cadences.
571

Signetics RF Communications
Paging decoder
supply
voltage Vss

Development Data
PCASOOOAT

data

input DI

AOB

oscillator input X1
write input WR
programming enable PR
supply
voltage v55
programming enable PR

---1 tpDc 1- -.I 1- tx1

1- twsu-1

).- tcsu

twp ____...

\............... ~---..-------

tpRSj

Fig. 10 Timing of RAM programming operation.

7Z81684

data

AOO

output DO - - - - - - - - ' I ' - - - '

oscillator input X1

write input WR
May 1991

Fig. 11 Timing of RAM verify operation.
572

AOB

A09 A10

7Z81687

J
~

Vp~-----rf\=--TTTI BAS16 Voo

OFF f SILENT

C1

3V

(lithium)

~~~~~
~ ON I OFF( SK

BAS16

~I I

VB I

28 18 17 16

+

"(j'

AERIAL

PAGING

10 �F

RECEIVER

data

enable

32.768 kHz
01 ,
4.7 M!l

-X1
X2 I 6
I
-DI
RE

11 ,.-~--,---6,_-8_.0_._n,_,-l-

PCA5000AT

9 .0R

BCW33

+ 10 �F

I1.5V
1.5 v

battery sense

;;-110 s 12 7 19 14 24 25

I BCW33
13

22 n

2.2 Mil

TS(QS(AI IPC(VREFIVss

Vss

7Z81688.2

Fig. 12 Example of alert-only pager.

~

.. ""Cl
c~o

"."0.'.

c:o:I

JJ
"Tl 0

)>

0

r--cc c=;
)> -t
0 z

0. 3

CD
(')
0 0.
.C..D..

3 c
i.""..

,z ,

0
:::s0:
)>
-t
0 z

""Cl

()

)> 0

01 0 0

~
0
'O

0
~

3
~
0

~

i
~

Vp
-
AE "AL
~ -
Yss

PAGING RECEIVER

G~ BAS16

Yoo

C1~

1
3V (lithium)

Yoo

~~ BAS16
680 n
rAL

t'--- r-

G~~
22 �F +~

switch
~"

....----

V9

28

11

DO

1

20

32.768 kHz

X1 5

DS 22

$ +
10�F

f---0

X2 6

FL 23
BL

~

data

4..-7--M---f.! ~

DI 3

15

Al 14

PCASOOOAT

ON

18

MICROCONTROLLER

LCD

enable

RE

OFF

10

17

battery sense

BS 12

SK 16

CP

27

PC

24

'~}"i"i�'~~-j ~~ [J22Mf!

22onFG 26

VREF 25
00

~

VREF

1------o

l1_5v-
$10�F 1.5 v-;;
22f! [)

7Z81689.3

w.

-u
Sl)

'gf�fi�

CQ. c::oJ

"-Jn'J
o�

a. ~

nCD

3 c =>

i- a0 .
C...D.. "'

Fig. 13 Example of display-pager in alphanumeric mode with voltage converter enabled.

-u

()

)> 01 0 0 0
~

~
_g :~a
a

~

Signetics RF Communications
Paging decoder

Development Data
PCA5000AT

Application notes

Input pins
The programming control inputs have internal biasing resistors of sufficiently low impedance to provide safe operation even if the pins are left open circuit.
Pin 1 (V9): RAM back-up battery negative supply. Connect this pin to the negative terminal of a lithium battery and connect the positive battery terminal to VDD� This battery supply ensures data retention when the main supply voltage is removed.
Pin 2 (PR): programming enable, normally LOW. To enter the programming mode, pull this input HIGH when connecting the main supply voltage.
Pin 3 (DI): serial data input. During normal operation, POCSAG-coded data is received via this pin. When in programming mode, data to be stored in the internal RAM is read from this input whenever a pulse on X1 occurs.
Pin 4 (WR): programming write input, normally HIGH. A positive edge on this pin copies the preceding
word shifted into the internal RAM. Keep this pin HIGH during RAM-read operations.
Pin 5 (X1): oscillator input. Connect a 32 kHz crystal to this pin during normal operation. When in programming write mode, a positive edge on X1 shifts the data present on DI to the internal register. When in programming read mode, a positive edge on X1 moves the next bit from the internal register to DO.
Pin 6 (X2): oscillator output. Return connection to the 32 kHz crystal.
Pin 7 (TS): test mode enable input, always LOW.
Pin 12 (BS): battery sense input. The decoder samples this input when it is in the ON state and the receiver is enabled. Every single sample is copied to the BL output. A continuous high-level alert tone is generated if four sequential samples are HIGH.
Pin 13 (Vssl: main negative supply voltage. Remove the voltage from this pin to leave the programming
mode. The RC combination of 22 n and 10 �F (Figs 12 and 13) should remain connected; disconnect
the battery only.
Pin 14 (Al): alarm input, normally LOW. A HIGH on this input causes a continuous high-level alert tone to be generated. The input may be pulsed to modulate the output tone.
Pin 16 (SK): silent key/mute input. Alert-Only-Pager: push-button switch input, pushing the switch selects SI LENT state. Display-Pager: static input, when HIGH no calls are stored and no alert tones are generated for calls received.
Pin 17 (OFF): off key/reset input. Alert-Only-Pager: push-button switch input, pushing the switch selects OFF state. Display-Pager: static input, normally LOW. A positive-going pulse on this input causes (a) status indication cadences to be generated if the decoder is not alerting or (b) resetting an alert call or a battery-low alert if active.
Pin 18 (ON): on key/on-off input. Alert-Only-Pager: push-button switch input. Pushing the switch selects ON state. Display-pager: static input. LOW level selects OFF state, HIGH level selects ON state.
Pin 19 (OS): vibrator enable input, normally LOW. A HIGH level enables the vibrator output logic and switches OR to vibrator output.
Pin 24 (PC): voltage converter power control. The level on this pin determines the output impedance of the voltage converter. LOW selects low impedance, HIGH selects high impedance.
Pin 26 (CN): voltage converter external capacitor, negative connection.

May 1991

575

Signetics RF Communications
Paging decoder

Development Data
PCA5000AT

Input pins (continued)
Pin 27 (CP): voltage converter external capacitor, positive connection.
Pin 28 (Voo): main positive supply input. This pin is common to all supply voltages and is referred to as GROUND.
Output pins
Pin 8 (QR): alert high-level output/vibrator output. This output can directly drive an external bipolar transistor to control a vibrator-type alerter if OS is set HIGH, or supports high-level alerting in conjunction with AL.
Pin 9 (OR): out-of-range output, active HIGH. If the decoder detects 'carrier-off', an output is generated for the duration of the synchronization scan period. Connecting OR to QR provides alert tone generation during 'carrier-off'.
Pin 10 (R El: receiver enable output, active HIGH. Connect the radio paging receiver power control input to this pin to minimize power consumption. Whenever no input data is required, the PCA5000AT will disable the paging receiver to conserve power.
Pin 11 (AL): alert low-level output, active LOW. The low-level alert tone is generated via this output; the alert becomes high-level in conjunction with OR.
Pin 15 (BL): battery-low output, active HIGH. Every time the PCA5000AT samples the BS input, data sensed is output on this pin.
Pin 20 (DO): received data output. During normal operation, accepted calls and possibly subsequent message code words are output via this pin at a rate of 512 bits/s. When in programming read mode, data read from the internal RAM is presented bit-by-bit on this pin.
Pin 22 (OS): received data strobe output, active LOW. In normal operation, every time this output goes LOW, the next bit on the DO output is valid.
Pin 23 (FL): frequency reference output. If the decoder is programmed as a Display-Pager, a 16 kHz squarewave reference is output from this pin.
Pin 25 (VR EF): microcontroller interface negative reference voltage. The LOW level of pins FL, BL, DO, OS, Al, ON, OFF, SK and PC is related to the voltage on VREF�
Alert-Only-Pager: Connect VREF output to Vss. Display-Pager: The doubled negative supply voltage generated by the internal voltage converter is output from VREF� The VREF pin may also be driven from an external supply if the capacitor across CN/CP is removed and CN/CP are left open circuit.

May 1991

576

Slgnellcs RF Communications
POCSAG paging decoder with EEPROM storage

Product specification
PCF5001T

DESCRIPTION
The PCF5001 Tis a very low power Decoder and Pager Controller specially designed for use in Radiopagers. The architecture of the PCF5001T allows for flexible application in a wide variety of Radiopager designs.
The PCF5001T is fully compatible with CCIR Radiopaging Code Number 1 (also known as the POCSAG code) operating at the 512 bps data rate, and 1200 bps data rate. 2400 bps operation is also possible. The PCF5001 T also offers features which extend the basic flexibility and efficiency of this code standard.
On-chip non-volatile 114 bit EEPROM storage is provided to hold up to four user addresses, two frame numbers and the programmed decoder condifuration.

FEATURES
� Wide operating supply voltage range (1.5 to6.0V)
� Extended temperature range: --40 to +85�C
� Very low supply current (60�A typ. with 76.BkHz crystal)
� Programmable call termination conditions
� Eight different alert cadences
� Directly drives magnetic or piezoelectric beeper
�Silent call storage, up to eight different calls
� Repeat alarm facility
� Programmable duplicate call suppression
� Interfaces directly to UAA2050T and UAA2080T digital paging receivers
� Programmable receiver power control for
battery economy
� On-chip voltage converter with improved drive capability
� Serial microcontroller interface for display pager applications
� Optional visual indication of received call data using a modified RS-232 format
� Level shifted microcontroller interface signals
� Alert on low battery
� Optional out-of-range indication

PIN CONFIGURATION
DPACKAGE

FL

OS

DO

OR

BL Al

ON

PS

SR

X1

SK

X2

TS

TT

-.____ AH

Vss

OL

OM

RE

,.- AL

APPLICATIONS
� Alert-only pagers, display pagers � Telepoint � Telemetry/data receivers

ORDERING INFORMATION

DESCRIPTION

TEMPERATURE RANGE

28-Pin Plastic SO

o to +70�C

ORDER CODE SOT-136A

September 1991

577

Signetics RF Communications
POCSAG paging decoder with EEPROM storage

BLOCK DIAGRAM,

Vss

Yoo

Product specification
PCF5001T

DO

DS

DI

DIGITAL INPUT

ALTER

SERIAL DATA PROCESSOR

DATA OUTPUT CONTROL
,--!

t--J
CLOCK RECOVERY

DECODER AND ERROR CORRECTION
CONTROL

1
EEPROM MEMORY
!

PD EEPROM CONTROL
PS

RECEIVER ENABLE CONTROL

!---+ SYNC CONTROL

TIWNG CONTROL

OSCILLATOR VOLTAGE
CONVERTER

~

CLOCK GENERATION
POWER-ON RESET

'-I
PCF5001T

I--

rl

h
1

J TEST
CONTROL

STATUS CONTROL
~

ALERT GENERATION
CONTROL
I l BACTOTENRTYROLOLW

AH AL OR ~ OM ~ OL Al

CP CN VREF

FL TS

TT

SR SK ON IE BL

BS

September 1991

578

Slgnetlcs RF Communications
Sound fader control circuit

Product specification
TEA6300

GENERAL DESCRIPTION The Sound Fader Control circuit (SOFAC) is an 12 C-bus controlled preamplifier for car radios.

Features
� Source selector for three stereo inputs � Inputs and outputs for noise reduction circuits � Volume and balance control; control range of 86 dB in steps of 2 dB � Bass and treble control from+ 15 dB (treble 12 dB) to -12 dB in steps of 3 dB � Fader control from 0 dB to -30 dB in steps pf 2 dB � Fast muting � Low noise suitable for DOLBY* Band C N R (noise reduction) � Signal handling suitable for compact disc � 12 C-bus control for all functions � ESD protected

QUICK REFERENCE DATA

parameter
Supply voltage Input sensitivity for full power
at the output stage Input signal handling Frequency response Channel separation
f =250 Hz to 10 kHz
Total harmonic distortion Signal plus noise-to-noise ratio Operating ambient tell)perature range

symbol
Vee
Vi(rms) Vi(rms) fr
acs
THD (S+N)/N Tamb

min.

typ.

max.

unit

7,0

8,5

13,2

v

-

50

-

mV

-

1,65 -

v

35

-

20000 Hz

70

92

-

dB

-

0,05 -

%

-

80

-

dB

-40 -

+ 85

oc

* Dolby is a registered trademark of Dolby Laboratories Licencing Corporation, San Fransisco,
California (U.S.A.).

May 1990

579

s:
'"<'
<O
<D 0

en

I (/) c0 :

<i"i"
:>
."cClr).

TEA6300 TEA6300T

330nF

QSLI 13
I

INL }c.
14 19

33nF

BLO

BL1

7

6

I
-, 5,6 nF TL 5
I

I .......

-a::i.
a~ .

JJ
"Tl 0 0
3 3c:

.C..D..
(")
-0
::i
.....

:>
i.:>

-0

"~~~

INLB ---f + 10 I

~

INLe ---f"

12 ? 1

4 QL';:--llf--

4,7 �F

~ I~ I ~ I I

I

I

~ I

I I

I

+':01--4,7 �F

Q......
(")
c:
~

INRA---f + INRB ---f +
8l
0
INRe---f

FADER MUTE

25 ORF f---
+
4,7�F

Vee

I I I 127

POWER

20

SUPPLY

I 12C-BUS LOGIC

I I

Vref

, +
12�F

11

18 16

15 28 1 2

23

ELFIJ; GND QSR

INR

BRO

BR1

. lOO�F

330nF

SeL GNDB
SDA '---r----'
12 C-bus

33nF

I II
24
ITR 5,6nF

Fig. 1 Block diagram.

~ ? I-- �F
7Z81157.2

I

m-i
)>

a-0
..s0c.

I O> U) 0 0

al
~
�er.

0 :>

Signetics RF Communications
Sound fader control circuit

SCL
Vee

ORR

ORF TR

BL1

BR1

TEA6300 TEA6300T

BRO INRA

v,.1

INLB

INRB

GND

INLC

INRC

OSL

OSR

INL

INR

1Z96996

Fig. 2 Pinning diagram.

Product specification
TEA6300

PINNING

SDA

2 GNDB

3 QLR

4 QLF

5 TL

6 BL1

7 BLO

8 INLA

9 i.e.

10 INLB

11 ELF!

12 INLC

13 QSL

14 INL

15 INR

16 QSR

17 INRC

18 GND

19 INRB

20 Vref

21

!NRA

22 BRO

23 BR1

24 TR

25 ORF

26 ORR

27 Vee 28 SCL

serial data input/output (12C-bus) ground for 12 C-bus terminals output left rear output left front treble control capacitor; left channel bass control capacitor; left channel bass control capacitor; left channel input left source A internally connected input left source B electronic filtering for supply input left source C output source selector left input left control part input right control part output source selector right input right source C ground input right source B
reference voltage (1/2 vcc)
input right source A bass control capacitor; right channel bass control capacitor; right channel treble control capacitor; right channel output right front output right rear supply voltage serial clock input (12 C-bus)

May 1990

581

Signetics RF Communications
Sound fader control circuit

Product specification
TEA6300

FUNCTIONAL DESCRIPTION
The source selector selects three stereo channels -RF part (AM/FM). recorder and compact disc. As the outputs of the source selector and the inputs of the main control part are available, additional circuits such as compander and equalizer systems may be inserted into the signal path. The AC signal setting is performed by resistor chains in combination with multi-input operational amplifiers. The advantage of this principle is the combination of low noise, low distortion and a high dynamic range for the circuit.
The separate volume controls of the left and the right channel facilitate correct balance control. The range and balance control is software programmable.
Because the TEA6300 has four outputs a low-level fader is included. The fader control is independent of the volume control and an extra mute position is built in for the front, the rear or for all channels. The last function may be used for muting during preset selection. An extra pop suppression circuit is built in for pop-free switching on and off. As all switching and control functions are controllable via the two-wire 12 e-bus,no external interface between the microcomputer and the TEA6300 is required.
The on-chip power-on-reset sets the TEA6300 to the general mute mode.

RATINGS Limiting values in accordance with the Absolute Maximum System (I Ee 134)

parameter

symbol

min.

max.

unit

Supply voltage (pin 27-18) Maximum power dissipation Storage temperature range Operating ambient temperature range

Vee Ptot Tstg Tamb

-

16

v

-

1

w

-55

+ 150

oe

-40

+85

oe

May 1990

582

Signetics RF Communications
Sound fader control circuit

Product specification
TEA6300

CHARACTERISTICS
Vee= 8,5 V; Rs= 600 il; RL = 10 kil; f = 1 kHz; Tamb = 25 oe; test circuit Fig. 10; unless otherwise specified

parameter
Supply voltage
Supply current
Supply current at 8,5 V
Supply current at 13,2 V
DC voltage inputs, outputs and reference
Internal reference voltage (pin 20) Vref = 0,5 Vee
Maximum voltage gain bass and treble linear, fader off
Output voltage level for Pmax at the output stage for start of clipping
Input sensitivity at V0 = 500 mV .
Frequency response bass and treble linear; roll-off frequency -1 dB
Channel separation Gv = 0 dB; bass and treble linear; frequency range 250 Hz to 10 kHz
Total harmonic distortion frequency range 20 Hz to 12,5 kHz Vi= 50mV;Gv= 20dB Vi= 500 mV; Gv = OdB Vi= 1,6 V; Gv=-10dB
Ripple rejection
Vr(rms) < 200 mV; Gv = OdB;
bass and treble linear; at f = 100 Hz at f = 40 Hz to 12,5 kHz

symbol Vee ice Ice Ice Voe
VREF Gv
Vo(rms) Vo(rms) Vi(rms)
fr
acs
THO THO THO

min. typ.

7,0 8,5

--

26

--

-

-

0,45 0,5

max. unit

13,2 v

-

mA

33

mA

44

mA

0,55 v

-

4,25 -

v

19

20

21

dB

-

500 -

mV

-

1000 -

mV

-

50

-

mV

35

-

20000 Hz

70

92

-

dB

-

0,1

0,3

%

-

0,05 0,2

%

-

0,2

0,5

%

RR100 RRrange

-

70

-

dB

-

60 -

dB

May 1990

583

Signetics RF Communications

Product specification

Sound fader control circuit

TEA6300

CHARACTERISTICS (continued)

parameter

symbol

min. typ. max. unit

Signal plus noise-to-noise ratio

bass and treble linear; notes 1 and 2

CCI R 468-2 weighted; quasi peak

VI�= 50mV; V0 = 46 mV; P0 = 50 mW (S + N)/N

-

65

-

dB

Vi=500mV; V0 = 45mV;P0 =50mW (S + N)/N

-

67

-

dB

VI�= 50 mV; V0 = 200 mV; P0 = 1W

(S + N)/N

65

70

-

dB

I�
I

Vi= 500 mV; V0 = 200 mV; P0 = 1W (S + N)/N

65

78

-

dB

Vi= 50 mV; V0 = 500 mV; P0 = 6W

(S + N)/N

-

70 -

dB

Vi= 500 mV; V0 = 500 mV; P0 = 6W

(S + N)/N

-

85

-

dB

Noise output power

mute position, only contribution of

TEA6300; power amplifier for 25 W

Pno

-

-

10

nW

Crosstalk (20 log Vbus(p-p)IYo(rms)l

. between bus inputs and signal outputs

Gv = 0 dB; bass and treble linear

as

-

110 -

dB

Source selector
Input impedance Output impedance
Output load resistance
Output load capacity Input isolation
not selected source; frequency range 40 Hz to 12,5 kHz Voltage gain RL ~ 10 kn Internal bias voltage ratio
Maximum input voltage level (RMS value) TH0<0,5% THO< 0,5%; Vee= 7,5 v
Total harmonic distortion vi= 500 mV; RL = 10 kn
Noise output voltage weighted CCI R 468-2, quasi peak
DC offset voltage between any inputs

zi Zo RL CL
as
Gv vb int!Vref
Vi(rms) Vi(rms) THO
Vno
Vo

20

30

40

kn

-

-

100 n

10 -

-

kn

0

-

200 pF

-

80 -

dB

-

0

-

dB

-

1

-

-

1,65 -

v

-

1,5

-

v

-

-

0, 1 %

-

9

20

�V

-

-

10

mV

Control part

Source selector disconnected, source resistance 600 n Input impedance Output impedance Output load resistance Output load capacity

zi

35

50

65

kn

Zo

-

100 150 n

RL

5

-

-

kn

CL

0

-

2500 pF

May 1990

584

Signetics RF Communications
Sound fader control circuit

parameter
Maximum input voltage THO< 0,5%; Gv = -10 dB; bass and treble linear
Noise output voltage weighted ace CC IR 468-2, quasi peak, bass and treble linear, fader off Gv = 20 dB Gv= 0 dB Gv = -66 dB mute position
Volume control Continuous control range Step resolution Attenuator set error
(Gv = + 20 to -50 dB) Attenuator set error
(Gv = + 20 to -66 dB) Gain tracking error
balance in mid position, bass and treble linear Mute attenuation DC step offset
Between any adjoining step and any step to mute Gv = 0 to -66 dB Gv = 20 to 0 dB
In any treble and fader position Gv = 0 to -66 dB
In any bass position Gv = 0 to -66 dB
Bass control
Bass control range f = 40 Hz; maximum boost f = 40 Hz; maximum attenuation
Step resolution Step error
Treble control Tre~;la control range
f = 15 kHz; maximum boost f = 15 kHz; maximum attenuation f> 15 kHz; maximum boost Ste;J resolution Step error
May 1990

symbol
Vi(rms)
Vno Vno Vno Vno Ge AG a AG a A Gt
am
Gb Gb
Gt Gt Gt
585

Product specification
TEA6300
min. typ. max. unit

-

2,0

-

v

-

110 220 �V

-

25

50

�V

-

19

38

�V

-

11

22

�V

-

86

-

dB

-

2

-

dB

-

-

2

dB

-

-

3

dB

-

-

2

dB

72

90

-

dB

-

0,2

10

mV

-

2

15

mV

-

-

10

mV

-

-

20

mV

14

15

16

dB

11

12

13

dB

-

3

-

dB

-

-

0,5

dB

11

12

13

dB

11

12

13

dB

-

-

15

dB

-

3

-

dB

-

-

0,5

dB

Signetics RF Communications
Sound fader control circuit

Product specification
TEA6300

CHARACTERISTICS (continued)

parameter

symbol

min. typ. max. unit

Fader control Continuous attenuation
fader control range Step resolution Attenuator set error Mute attenuation
Digital part Bus terminals Input voltage
HIGH 'LOW Input current HIGH LOW Output voltage LOW IL= 3 mA
AC characteristics in accordance with the 12 C-bus specification

Gf
am
V1H V1L l1H l1L Vol

-

30

-

dB

-

2

-

dB

-

-

1,5

dB

74

84

-

dB

3

-

-0,3 -

-10 -
-10 -

-

-

12

v

+ 1,5 v

+10 �A + 10 �A

0,4

v

Power-on-Reset
When RESET is active the GMU (general mute) bit is set and the 12 C-bus receiver is in RESET position
Increasing supply voltage start of reset end of reset
Decreasing supply voltage start of reset

Vee Vee
Vee

-

-

2,5

v

5,2

6,0

6,8

v

4,2

5,0

5,8

v

Notes to the characteristics
1. The indicated values for output power assume a 6 W power amplifier with 20dB gain, connected to the output of the circuit. Signal-to-noise ratios exclude noise contribution of the power amplifier.
2. Signal-to-noise ratios on a CCI R 468-2 average meter reading are 4,5 dB better than on CCI R 468-2 quasi peak.

May 1990

586

Signetics RF Communications
Sound fader control circuit

Product specification
TEA6300

12 C-BUS FORMAT

I I s

SLAVE ADDRESS

A

SUBADDRESS

A

DATA

A

p

S

= start condition

SLAVE ADDRESS = 1000 0000

A

= acknowledge, generated by the slave

SUBADDRESS =see Table 1

DATA

=see Table 1

P

= STOP condition

If more than 1 byte of DATA is transmitted, then auto-increment of the subaddress is performed.

Table 1 12 C�bus; subaddress/data

function

subaddress

volume left volume right bass treble fader switch

0 0 0 0 0 0 0 0 0000000 1 000000 10 00000011 00000 100 00000 10 1

D7 D6
x x x x x x x x x x GMU x

D5
VL5 VR5
x x
MFN
x

DATA D4 D3
VL4 VL3 VR4 VR3
x BA3 x TR3
FCH FA3
x x

D2 D1 DO

VL2 VR2 BA2 TR2 FA2
sec

VL 1 VR1 BA1 TR1 FA1 SCB

VLO VRO BAO TRO FAQ SCA

Function of the bits:

VLO to VL5 VRO to VR5 BAO to BA3 TRO to TR3 FAQ to FA3 FCH MFN
SCA to sec
GMU
x

volume control left volume control right bass control treble control fader control select fader channel (front or rear) mute control of the selected fader channel (front or rear) source selector control mute control (general mute) for the outputs OLF, OLR, ORF and ORR don't care bits (logic 1 during testing)

May 1990

587

Signetics RF Communications
Sound fader control circuit

Product specification
TEA6300

Table 2 Bass setting

Gv

DATA

dB

BA3 BA2 BA1

BAO

+15

1

1

1

1

+15

1

1

1

0

+15

1

1

0

1

+15

1

1

0

0

+12

1

0

1

1

+ 9

1

0

1

0

+ 6

1

0

0

1

+ 3

1

0

0

0

0 0

1

1

1

-3 0

1

1

0

-. 6 0

1

0

1

-9 0

1

0

0

-12 0

0

1

1

-12 0

0

1

0

-12 0

0

0

1

-12 0

0

0

0

Table 3 Treble setting

Gv

dB

TR3

+12

1

+12

1

+12

1

+12

1

+12

1

+ 9

1

+ 6

1

+ 3

1

0

0

-3

0

-6

0

-9

0

-12

0

-12

0

-12

0

-12

0

DATA TR2 TR1 TRO

1

1

1

1

1

0

1

0

1

1

0

0

0

1

1

0

1

0

0

0

1

0

0

0

1

1

1

1

1

0

1

0

1

1

0

0

0

1

1

0

1

0

0

0

1

0

0

0

May 1990

588

Signetics RF Communications

Product specification

Sound fader control circuit

TEA6300

Table 4 Volume setting LEFT

Table 5 Volume setting RIGHT

Gv

DATA

dB VL5 VL4 VL3 VL2 VL 1 VLO

20

11 1 1 1 1

18

11 1 1 1 0

16

11 1 1 0 1

14

11 1 1 0 0

12

11 1 0 1 1

10

11 1 0 1 0

8

11 1 0 0 1

6

11 1 0 0 0

4

11 0 1 1 1

2

11 0 1 1 0

0

11 0 1 0 1

-2

11 0 1 0 0

-4

11 0 0 1 1

-6

11 0 0 1 0

-8

11 0 0 0 1

-10

11 0 0 0 0

-12

10 1 1 1 1

-14

10 1 1 1 0

-16

10 1 1 0 1

-18

1 0. 1 1 0 0

-20

10 1 0 1 1

-;-22

10 1 0 1 0

-24

10 1 0 0 1

-26

10 1 0 0 0

-28

10 0 1 1 1

-30

10 0 1 1 0

-32

10 0 1 0 1

-34

10 0 1 0 0

-36

10 0 0 1 1

-38

10 0 0 1 0

-40

10 0 0 0 1

-42

10 0 0 0 0

-44

01 1 1 1 1

-46

01 1 1 1 0

-48

01 1 1 0 1

-50

01 1 1 0 0

-52

01 1 0 1 1

-54

01 1 0 1 0

-56

01 1 0 0 1

-58

01 1 0 0 0

-60

01 0 1 1 1

-62

01 0 1 1 0

-64

01 0 1 0 1

-66

01 0 1 0 0

mute left 0 1 0 0 1 1

mute left 0 1 0 0 1 0

Gv

DATA

dB

VR5 VR4 VR3 VR2 VR1 VRO

20

11 1111

18

11 11 10

16

11 110 1

14

11 1100

12

11 10 11

10

11 10 10

8

11 100 1

6

11 1000

4

11 0111

2

11 0 110

0

11 0 10 1

-2

11 0 100

-4

11 0011

-6

11 00 10

-8

11 0001

-10

11 0000

-12

10 1111

-14 . 1 0 1 1 1 0

-16

1 0

110 1

-18

10 1100

-20

10 10 11

-22

10 10 10

-24

10 1001

-26

10 1000

-28

10 0 111

-30

10 0 110

-32

10 0 10 1

-34

10 0 100

-36

10 00 11

-38

10 00 10

-40

10 000 1

-42

10 0000

-44

01 1111

-46

0 1 1 110

-48

0 1 110 1

-50

0 1 1100

-52

0 1 10 11

-54

0 1 10 10

-56

0 1 100 1

-58

0 1 1000

-60

01 0111

-62

0 1 0 110

-64

0 1 0 10 1

-66

0 1 0 100

mute right 0 1 0 0 1 1

mute right 0 1 0 0 1 0

mute left 0 0 0 0 0 0

mute right 0 0 0 0 0 0

May 1990

589

Signetics RF Communications
Sound fader control circuit

Product specification
TEA6300

Table 6 Fader function

setting
front rear dB dB

DATA MFN FCH FA3 FA2 FA1 FAQ

setting

DATA

front rear dB dB MFN FCH FA3 FA2 FA1 FAQ

fader off

fader off

I I

0 0

11 111 1

Q

Q 1

Q

1 1

1

1

I,,

0 0

Q1 1 1 1 1

Q

Q Q

Q

1 1

1

1

-2 Q
-4 Q
-6 Q
-8 Q -10 Q
-12 Q -14 Q -16 Q -18 Q -20 Q -22 Q -24 Q -26 Q -28 Q -30 Q

fader front

11 111 Q

1 1 11Q 1

1 1 11Q Q

1 1

1 Q 1

1

1 1 1Q1 Q

1 1

1 QQ 1

1 1 1 QQ Q

1 1 Q1 1 1

1 1 Q11 Q

1 1 Q1Q 1

1 1 Q1Q Q

1 1 QQ1 1

1 1 QQ1 Q

1 1 QQQ 1

1 1 QQQ Q

Q -2 1
Q -4 1
Q -6 1 Q -8 1
Q -10 1
Q -12 1 Q -14 1 Q -16 1 Q -18 1 Q -2Q 1 Q -22 1 Q -24 1 Q -26 1 Q -28 1 Q -3Q 1

fader rear

Q 11

1

Q

Q 11 Q 1

Q 11 QQ

Q 1Q 1 1

Q 1Q 1 Q

Q 1Q Q 1

Q 1Q Q Q

Q Q1

1

1

Q Q1

1

Q

Q Q1 Q 1

Q Q1 Q Q

Q QQ

1

1

Q QQ 1 Q

Q QQ Q 1

Q QQ Q Q

mute front

-80 Q

Q 1

1 1 1

Q

Q -8Q Q

mute rear

Q

1 1

1

Q

-8Q 0

Q 1 QQQ Q

Table 7 Selected inputs

selected inputs

DATA
sec SCB

data not allowed data not allowed data not allowed INLC, INRC data not allowed INLB, INRB INLA, INRA data not allowed

1

1

1

1

1

Q

1

Q

Q

1

Q

1

Q

Q

Q

Q

SCA
1 Q 1 Q 1 Q 1 Q

Q -8Q Q

Q QQ Q Q

Table 8 Mute control

MUTE control

DATA GMU

remarks

active passive

1

outputs OLF, OLR

ORF and ORR are

muted

Q

no general mute

May 1990

590

Signetics RF Communications
Sound fader control circuit

Product specification
TEA6300

-15'--~-'-~'--~-'-J.J..LJ__~~'---__L___J__L_L.LL.LI~~-'-__J~L...J.__L_LJ.jLJ__~__J~_J__l_.L..JJ_LLJ
10 I (Hz)
Fig. 3 Bass control without T-pass filter.
Gv (dBi

f---T-1---t-t-++++----+--~
y -1ot--~-i=--t-t-t-~l:li=====-+-""'~+-t+-t+tt-~--+~t-l-\--+-t-t+t-~-+---+--+--+-H-f+1

May 1990

Fig. 4 Bass control with T-pass filter.

TEA6300 TEA6300T
7 (22)

68nF

68nF

10kf!

7Z94998

Pin numbers in parenthases refer to the bass control, right channel. Fig. 5 T-pass filter.
591

Signetics RF Communications
Sound fader control circuit

Product specification
TEA6300

Gv 15
(dB}
10

7Z81161 1

5

0
-5 rL_ 1-1
-10

t--
N --

-15 10
Vno 160
(�V}
140

Fig. 6 Treble control.

f (Hz) 1Z81162 1

120

j

100

80
60
Q.
40 i--$.,
.,1i)
20 I
0

LY
-""' _Montrol part only

-60

-50

-40

-30

-20

-10

0

10

20

Gy (dB}

Fig. 7 Output noise voltage (CCI R 468-2 weighted: quasi peak).

6ot---+-+-hf-ttttt-~-t--t-H-H::J.~......-::j......,,t:::-'1F-l--11-+-t+t+hf---+-+--H-+tttt-~-t--t-t-+t+tH
i.J:::
50t----t--1r-+-t-t-i:::!>i~.........-=--~t--t-t-+-l-++tt-~+-+-+-++-H+t-~-t--t--+t-++ttt-~-t--t--t--H--j-t-H t--H
40 ~

30'--~'---'-.L...l...J...L.LI..J.~-J.~'-'-'-1...LI-'-'-~-'--J.~--'-l..J...L'-1-~-'--'---'-,L_J_LLJ..L._~.l___-'-_,l_JW-.JcJ...1..J

0,1mW

1mW

10mW

0,1W

1W

10W

Fig. 8 Signal-to-noise ratio (CCIT 468-2 weighted; quasi peak) with a 6 W power amplifier (gain 20 dB) without noise contribution of the power amplifier (see Fig. 9).

May 1990

592

Signetics RF Communications
Sound fader control circuit

Product specification
TEA6300

TEA6300
Gv max= 20dB V;

POWER OUTPUT STAGE

JZBl 159.1
Fig. 9 Recommended level diagram; Vi min= 50 mV, V0 = 500 mV for Pmax�

May 1990

593

Signetics RF Communications
Sound fader control circuit

Product specification
TEA6300

APPLICATION INFORMATION

15

14

16

- - - f input right source C

+

17

2,2�F

~-------118

- - - f input right source B

+

19

2,2 �F

- - - f input right source A

+

21

2,2�F

22

TEA6300 TEA6300T

13

12

I - - - +

input left source C

2,2�F

11

+ ~

100�F

10

I - - - +

input left source B

2,2 �F

9

Le.

8

I - - - + input left source A

2,2�F

23

6

~

24

5,6nF

- - - f output right front

+

25

4,7 �F

- I output right rear

+

26

4,7 �F

Vee - - - - - - - < 21
(8,5V)

5

~

5,6nF

4

1 - - +

output left front

4,7 �F

3

1 - - +

output left rear

4,7 �F

2

GNDB

28

SDA

} ''c-oo,

7Z81158.2

SeL

Fig. 10 Test and application circuit.

May 1990

594

Slgnellcs RF Communications
Data processor for cellular radio (DPROC)

Development Data
UMA1000T

GENERAL DESCRIPTION
The LIMA lOOOT is a low power CMOS LSI device incorporating the data transceiving, data processing, and SAT functions (including on-chip filtering) for an AMPS or TACS hand-held portable cellular radio telephone.

Features � Single chip solution to all the data handling and supervisory functions � Configurable to both AMPS and TACS � 12 C serial bus control � All analog interface and filtering functions fully implemented on chip � Error handling in hardware reduces software requirements
� Robust SAT decoding and transponding circuitry � Low current consumption � Small physical size � Minimum external peripheral components required

QUICK REFERENCE DATA

parameter

symbol

min.

typ.

max.

unit

Supply voltage (pin 28)

Voo

4.5

5.0

5.5

v

Supply current (pin 28) normal operation

loo

-

2

-

mA

Operating ambient temperature range

Tamb

-40

-

+85

oc

PACKAGE OUTLINE 28-lead mini-pack; plastic (S028; SOT136A).

February 1991

595

;/,'
CJ"
2
~ a;
<D
~

TEST

i.e.

SYNCCLK

RESET

VDD

Le.

INVRX

6

110

I 16

126

I 28

I g

I 1

I RESET
GENERATOR

I

r-1 I WORD SYNC T

~1 I DEMOOD

ANTI �ALIAS

FILTER

S + ~

PASSIVE

INPUT FILTER

INTERPOLATORS

�[t>-- DATA RECOVERY

f

I SAT RECOVERY

MAJORITY VOTING
DOTTING DETECTOR

..J.:___j "'<D
"' AGNO

REFERENCE VOLTAGE

GENERATOR

UMA1000T

VssA DATA

~ CLOCKNOISE

FILTER

FILTER

GATED D/A GATED 0/A

SAT

L

REGENERATION

SAT DETERMINATION

MANCHESTER AND BCH ENCODING

CLKIN -f--.-.1 CLO~ GENERATOR 13

I ~ GATEDD/A

SIGNAL TONE GENERATOR

c:r,4

21

:g.

a 0
O>

::>
"5' �
,"J,J'

-.0....
0

0 0
3

1
191 � BUSY

(')

CD

CJ)

I -I

CJ)
.0....

0....

3c:
g.:c::;i�
:::i
"'

(')

CD

c

ERROR CORRECTION
ARBITRATION LOGIC

AXLINE RXCLK

O......>..

5 I> RACTRL

-aOe>r.
0

"'U

TXCTRL

:D

-0
()

11 TACTRL

TRANSMIT BUFFER

TXCLK TX HO LO TXLINE

12 c
INTERFACE

1...----.- SCL
ISDA

BU FOUT

VssD

Fig. 1 Block diagram.

INVTX Al AO

7Z22084.2

cs: 0

)__>.. ""<0''

I

0 0

0

"O
3
;"!'.

-I 0

~

Signetics RF Communications
Data processor for cellular radio (DPROC)

Development Data
UMA1000T

AGND DEMODD
RACTRL
AXLINE
i.e. i.e.
TACTRL CLKIN
BU FOUT Vsso

UMA1000T
MLA033-1

Voo RXCLK RESET SCL SDA AO A1 INVTX TXCTRL BUSY TXCLK TXHOLD SYNCCLK TXLINE

Fig.2 Pinning diagram.

PINNING

1 VssA 2 AGND 3 DEMODD

analog negative supply (0 V) (Voo - VssAl/2 analog reference ground received data signal input

4 DATA

transmitted data signal output

5 RACTRL received audio control output

6 TEST

SCAN Control input - used for power on reset

7 INVRX

inverts sense of received data stream

8 AXLINE received data signal output

9 i.e. 10 i.e.

[ internally connected; must be left open
J -circuit

11 TACTRL transmitter audio control output

12 CLKIN

1.2 MHz external master clock input

13 BU FOUT buffered output of internal clock oscillator

14 Vsso 15 TXLINE

digital ground transmitted data signal

16 SYNCCLK SCAN CLOCK Control input - used for power-on reset

17 TXHOLD holds off transmission of data

18 TXCLK

transmitted data clock input

19 BUSY

reverse control channel status output

20 TXCTRL transmitter control output

21 INVTX 22 A1

inverts sense of transmitted data stream
address input 1 - used for power-on reset

23 AO 24 SDA

address input 0 serial data input/output

12 C-bus

25 SCL

serial clock input

26 RESET

master rest input

27 RXCLK

received data clock input

28 Voo

positive supply voltage (+ 5 V)

February 1991

597

Signetics RF Communications
Data processor for cellular radio (DPROC)

Development Data
UMA1000T

CHARACTERISTICS Voo = 5 V � 10%; Tamb = -40 to +85 oc; unless otherwise specified

parameter

conditions

symbol min.

typ. max.

unit

Supply

I<

Supply voltage

Voo

4.5

5.0 5.5

v

Supply current

normal operation 100

-

2.0 -

mA

Digital inputs Input voltage LOW Input voltage HIGH Input capacitance

note 1

V1L

0

-

0.3 Voo v

V1H

0.1 Voo -

Voo + 0.3 v

C1

-

-6

pF

Digital outputs

note 1

Output voltage LOW

Isink= 1 mA

VOL

-

-

0.4

v

Output voltage HIGH

Isource= 1 mA

VOH

voo�-0.4 -

-

v

Open-drain outputs Output voltage LOW

note 2 Isink= 2 mA

Vol

-

-

0.4

v

Open-drain SDA Output voltage LOW

Isink= 3 mA

Vol

-

-

0.4

v

Notes to the characteristics
1. All digital inputs and outputs of DPROC are compatible with standard CMOS devices and the following general characteristics apply.
2. Open-drain outputs have no internal pull-up resistors.

February 1991

598

Signetics RF Communications
Data processor for cellular radio (DPROC)

Development Data
UMA1000T

FUNCTIONAL DESCRIPTION
General
The UMA 1000T (DPROC) is a single chip CMOS device which handles the data and supervisory functions of an AMPS or TACS subscriber set. These functions are:
� Data reception and transmission � Control and voice channel exchanges � Error detection, correction, decoding and encoding � Supervisory Audio Tone decoding and transponding � Signalling Tone generation
In an AMPS or TACS cellular telephone system, mobile stations communicate with a base over full duplex RF channels. A call is initially set up using one out of a number of dedicated control channels. This establishes a duplex voice connection using a pair of voice channels. Any further transmission of control data occurs on these voice channels by briefly blanking the audio and simultaneously transmitting the data. The data burst is brief and barely noticable by the user. A data rate of 10 kbit/s is used in the AMPS system and 8 kbits/s in TACS. The signalling formats for both Forward Channels (base to mobile) and Reverse Channels (mobile to base) are shown in Fig. 3.
A function known as Supervisory Audio Tone (SAT), a set of 3 audio tones (5970, 6000 and 6030 Hz), is used to indicate the presence of the mobile on the designated voice channel. This signal, which is anatagous to the On-Hook signal on land lines, is sent out to the mobile by the base station on the Forward Voice Channel. The signal must be accurately recovered and transponded back to the base station to complete the 'loop'. At the base station this signal is used to ascertain the overall quality of the communication link.
Another voice channel associated signal is Signalling Tone (ST). This tone (8 kHz TACS, 10 kHz AMPS) is generated by the mobile and is sent in conjunction with SAT on the Reverse Voice Channel to serve as an acknowledgement signal to a number of system orders.
The key requirements of a hand held portable cellular set are:
� small physical size � minimum number of interconnections (serial bus) � low power consumption � low cost
The DPROC is a member of our Cellular Radio chipset, based on the 12 C-bus, which meets these requirements. A cellular radio system schematic using the chip set is shown in Fig. 4.

February 1991

599

~
2
~
~

10

11

40

40

40

40

40

40

40

BIT WORD REPEAT 1 SYNC SYNC OF WORD A

REPEAT 1 OF WORD B

REPEAT2 OF WORD A

---

REPEAT4 OF WORD A

REPEAT4 REPEATS OF WORD B OF WORD A

REPEATS OFWORDB

10
BIT SYNC

t t
Busy/Idle Bit

t t t ttt t ttt t ttt t
(a) forward control channel

ttt t t

101 11

40

37

11

40

37

11

40

37

11

40

37

11

40

I BIT I WORD I REPEAT 1 I BIT I WORD I REPEAT 2 I BIT I WORD I - - - I REPEAT 9 IBIT IWORDIREPEAT10 IBIT IWORDIREPEAT11

SYNC SYNC OF WORD SYNC SYNC OF WORD SYNC SYNC

OF WORD SYNC SYNC OF WORD SYNC SYNC OF WORD

I

~

(b) forward voice channel

0

30

11

7

240

240

BIT

WORD CODED FIRST WORD REPEATED I SECOND WORD REPEATED

SYNC SYNC DCC

S TIMES

S TIMES

(cl reverse control channel

101 11
BIT WORD SYNC SYNC

4B

37

11

48

37

11

REPEAT 1 BIT WORD REPEAT 2 BIT WORD OF WORD 1 SYNC SYNC OF WORD 1 SYNC SYNC

48

---

REPEATS OF WORD 1

37

11

48

BIT WORD REPEAT 1
SYNC I SYNC OFWORD2

37
BIT SYNC

11

48

WORD ~EATS
SYNC - - - OF WORD 2

(d) reverse voice channel Fig. 3 Signalling formats.

fg.

a 0
ll>
a"'O

::J
!"".l''�
:-Dn
() 0
3

0
CD
Ch
-Ch
0..... 0.....

c 3
::J
..1:
::J

0 ~

c

l....l..>....

-I
I

e~ r
0

"'"U

JJ

-0
()

cs:: 0

.)...>...
0 0 0

."0G.,'i
3
"a '

-I ;0

~
O"
2
.!!
~
RECEIVER SUBSYSTEM

12 C-bus

11

~

0 ~

":>' "."0,''�

~
-,0

-Jnl
0

0

0
3

(')
CD
(J)

,,.3c
:>

(J)
-0 ,
0 ,

~-
.:0>,

12 c

(')

r-----1

DATA

~

ILSYNTHESIZER..JI demodulation

~ PROCESSOR I+ syndchtrolnous

--+ PORT

address/data bus

c

1

-----
II j

line 9,6 MHz

f'data J_

J-a a me
j 9,6 MHz

--+ XTAL

{DUPLEX

+-------- -1---i

l TCXO

~

l ~:.~: ;,. mm

TRANSMITTER

t~ line

,:~:;;~" 4

''' ""'

.":;:~:;::~"'

SUBSYSTEM

I 2C-bus

taudio

}

, , ~
a~ .

[ EPROMJ

-5�
0

"U

1lJ. l ,::;, ,_]

JJ
g 0

RAM

[�~~~~'~"]

rr;Q ,,, ""'

J

~

in~::;.ce ~gg ---------'

0~9--o

keyboard scan bus

.

analogue lines

INTO "i~--~

ADC

PWM

power

1

su1:~1L

POWER

Yl

transmitter power control

I NiCds)

7Z21321.1

Fig. 4 Cellular radio system schematic.

cs:: 0

)_>. "('�'

0 0
0- ;

0
"O
3
"~ '
0

~

Signetics RF Communications
Data processor for cellular radio (DPROC)

Development Data
UMA1000T

EXTERNAL PIN DESCRIPTION
Supply (Voo; VssA; VssD; AGND) VDD : Positive supply voltage for digital and analog circuitry (� 5 V +10%) VssA : Negative supply voltage for analog circuitry (0 V) VssD : Digital ground (O V) AGND: Internally generated reference ground used by internal analog circuitry. Voltage level
(VDD - VssAl/2 � 2%. Both VssA and VssD must be connected to common ground.
System clock (CLKIN; BUFOUT) CLKIN is a digital input for the externally generated 1.2 MHz master clock. This signal should be accurate to 100 x 10-5 and have a worst case of 60: 40 mark-space ratio. BU FOUT is the buffered output of the clock oscillator and provides the option of generating the clock signal on chip by connecting a 1.2 MHz crystal between BUFOUT and CLKIN.

_1,_
-tr-

-

1HIGH - - 1LOW -

1--~~~~- Tp~~~~--<~I

MEA160

I parameter
I
Clock period time
HIGH time
LOW time Rise time
Fall time

I symbol
!
i Tp
I tHJGH
tLQW
tr
tf

min.

I 833.25

I 40%

I I

-

I

l -

typ.
833.33 50% T p-tHIGH 50 50

max.

unit

833.42

ns

60%

Tp

-

-

ns

-

ns

12 C serial data link (SDA; SCL)
SDA is the bi-directional data line; SCL the clock input from an 12 C master. These constitute a typical 12 C link and conform to standard characteristics as defined in the 12 C-bus specification. � data rate: up to 100 kbit/s

Slave Address Select (AO; A 1)
Selection of the device slave address is achieved by connecting AO to either VssD or VDD and connecting A 1 to either pin 16 and pin 6 or to VDD� The slave address is defined in accordance with the 12 C specifications as shown in Fig. 5.

0

A1 AO R/W

February 1991

Fig. 5 Device slave address. 602

Signetics RF Communications
Data processor for cellular radio (DPROC)

Development Data
UMA1000T

Power-up state
DPROC will not respond reliably to any inputs (including RESET) until 100 �s after the power supply has settled within the specified tolerance. The analog sections of the device will have stabilized within 5 ms. No power-on-reset is provided, therefore before the device can enter normal operation TEST and SYNCCLK must be pulsed HIGH. The reset pulse on these pins must have a minimum period of 250 �s and the fall time of the negative going edge must be faster than 1 �s. Pin A1 must remain HIGH during this reset period therefore if the A 1 bit of the 12 C address is required to be logic 0. A1 may be connected to TEST and SYNCCLK. If it is required to be at logic 1 then A1 may be permanently connected to VoD� If it is required that AO= logic 1, then a normal master reset (pin 26) sequence must follow the power-on-reset sequence to get the internal registers in the defined state.
After the power-on-reset a dummy transmission should be made to initiate internal DPROC counters. This transmission should be made with arbitration (ABREN) disabled and the RF transmitter stage switched OFF. Figure 6 shows the power-on reset sequence.

power-on and
master clock act ive
TEST/SYNCCLK
A1
TXLINE

-- - - -t1

r ti-

v I'\
tHDJ-
v - "\

program DPROC

12 C-bus

control registers

11
: :' '

!

transmit one
dummy word
i

.' .'
:,'
.' .I
.' .'
.' !
; ,r

m

1111111111

I

TXCLK
Where: tl = time not critical. tr = reset time = 250 �s max. tf = pulse fall time= 1 �s max. tHo =Al hold time= 0 �s min.

: .I

mm

I I

MEA171

Note The RF transmitter is OFF during reset sequence.
Fig.6 Power-on reset programming sequence.

Master reset (RESET)
RESET is an asynchronous active LOW master reset input, with a minimum active pulse width of 2 �s which may be used to reset certain logic within DPROC to a predefined state as illustrated in Tables 1 and 2. Alternatively, DPROC may be set into a known initial state be setting the 12 C control register as required. The internal reset sequence after a negative pulse on RESET takes 250 �s.

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UMA1000T

EXTERNAL PIN DESCRIPTION (continued) Table 1 Predefined state of the digital output pins

output
RXLINE TXCTRL TACTRL RACTRL BUSY

state
HIGH HIGH HIGH HIGH HIGH

Table 2 Predefined state of the 12 C re.gisters
,----

register 7

6

5

4

control SATO TST

LOW LOW LOW

LOW LOW LOW

LOW LOW LOW

LOW LOW LOW

bit
3
LOW LOW LOW

2
LOW LOW LOW

1
LOW LOW LOW

0
LOW LOW LOW

Data Transfer Link (RXLINE; TXLINE; TX HOLD; TXCLK and RXCLK)

RXLI NE, TXU NE, TXCLK and RXCLK provide a dedicated serial data link for the transfer of system data messages between DPROC and the system controller at variable rates of up to 200 kbits/s. TXHOLD allows the system controller to preload the DPROC transmit register with one word without the data being transmitted. DPROC then starts transmitting the instant TXHOLD is driven LOW.

� RXCLK � RX LINE � TXCLK � TXLINE � TXHOLD

: clock input from system controller : data output from DPROC to system controller : clock input from system controller : open drain data bi-directional line to the system controller : (HIGH) holds off transmission of data

� data rate Note

: up to 200 kbit/s

A minimum mean data transfer rate for the received data of 2.1 kbits/s (AMPS) and 1.7 kbits/s (TACS) is required to ensure contiguity of message words.

The format for received and transmitted data words is shown in Fig. 14 (a) and Fig. 14 (b) respectively. The receive and transmit data timing is illustrated in Fig. 15 (a) and Fig. 15 (b) respectively.

Transmitter Control (TXCTR L) TXCTR L is an open-drain output used to disable the transmitter during a Reverse Control Channel access failure.
� output level HIGH : RF enable � output level LOW : RF disable

Transmitter Audio Enable (TACTR L) TACTR Lis an open-drain digital output signal used to blank the audio path and enable the data path to the modulator during data bursts on the Reverse Voice Channel.
� output level HIGH : audio enabled � output level LOW : audio muted

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Data processor for cellular radio (DPROC)

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UMA1000T

Receiver Audio Enable (RACTR L) RACTR L is an open-drain digital output used to blank the audio path to the earpiece when a sequence of dotting and word sync is detected.
RACTR Land TACTR L functions can be combined using one line. � output level HIGH : audio enabled � output level LOW : audio muted
Reverse Control Channel Status (BUSY) BUSY is a digital output giving the status of the Reverse Control Channel. This is determined by a majority decision on the result of the last 3 consecutive Busy-Idle bits and has the following logic levels: � output level HIGH : channel busy � output level LOW : channel idle On a voice channel BUSY indicates channel idle.
Invert Receive Data (INVRX) Enables an additional inverter in the receive data path. This allows RF demodulators with high or low local oscillators to be used. The TACS and AMPS specifications define a NRZ encoded logic 1 as a LOW-to-HIGH transition in the centre of a data bit period. The polarity of the demodulated data stream into DPROC depends on the receiver local oscillator. � input HIGH : data inverted � input LOW : data normal
Invert Transmit Data (I NVTX) Enables an additional inverter in the transmit data path. This allows RF modulators with high or low local oscillators to be used. The TACS and AMPS specifications define a NRZ encoded logic 1 as a LOW-to-HIGH transition in the centre of a data bit period. The polarity of the modulated data stream depends on the transmitter local oscillator. � input HIGH : data inverted � input LOW : data normal

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UMA1000T

EXTERNAL PIN DESCRIPTION (continued)

Transmitted Data Output (DATA)

Data is an analog output which provides Manchester encoded and filtered data signal SAT and signalling tone. This signal should normally be AC coupled into the Audio/Data summer.

� DC level

: analog ground (AGND)

� signal level

: 2 V (p-p) *for signalling tone

� signal tolerance

: 2% +supply voltage variation (AVDD)

� minimum load impedance : 10 kU

� maximum load capacitance : 2 nF
� maximum output impedance : 50 n

Received Data Input (DEMODD)
Demodd inputs analog data and SAT signals from the RF demodulator. This pin should normally be AC coupled (characteristics for UMA 1000T/F4 upwards).

� DC level � maximum data level � nominal data level � minimum data level � minimum SAT level � input impedance

: analog ground (AGND)
: 1 v (p-p)
: 250 mV (p-p)
: 200 mV (p-p)
: 50 mV (p-p)
:> 1 MU

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UMA1000T

CHARACTERISTICS OF THE 12C BUS The 12 C bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.
Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals.

SDA

~--+-------+---'x'--.+---===~
---\__

SCL

data line stable:
data valid

change
of data allowed

7287019

Start and stop conditions

Fig. 7 Bit transfer.

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (P).

- - 1 \ SDA

r----,

I

I

I

I

I

I

I

SCL

I

I

I

I

Is I

\

I L

___

I
_j

start condition

r=== ;--\

r---,

I

I I

SOA

I

I

I I
I

SCL

I
L _ _ _ .J

stop condition

7287005

Fig. 8 Definition of start and stop conditions.

System configuration
A device generating a message is a "transmitter", a device receiving a message is the "receiver". The device that controls the message is the "master" and the devices which are controlled by the master are the "slaves".

SDA-----...--------...-------~------...---------.SCL-..,_...---;---_,..----+----<~---t---...-----+----....----1--

MASTER TRANSMITTER/
RECEIVER

SLAVE RECEIVER

SLAVE TRANSMITTER/
RECEIVER

MASTER TRANSMITTER

MASTER TRANSMITTER/
RECEIVER
7287004

February 1991

Fig. 9 System configuration.
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UMA1000T

CHARACTERISTICS OF THE 12 C BUS (continued)
Acknowledge
The number of data bytes transferred between the start and stop conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse, set up and hold times must be taken into account. A master receiver
must signal an end of data to the transmitter by not generating an acknowledge on the last byte that
has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a stop condition.

start condition
I I

clock pulse for acknowledgement
i

SCL FROM

I

MASTER

I

I

--~

I

I

DATA OUTPUT BY TRANSMITTER

1'~..__/_x'---_K~~)(._____.7

s I
DATA OUTPUT BY RECEIVER

--~

7Z87007

Fig. 10 Acknowledgement on the 12 C bus.

Timing specifications
Masters generate a bus clock with a maximum frequency of 100 kHz. Detailed timing is shown in Fig. 11.

SDA

tBuF-

SCL

- 1HD;STA -

tr

_...

.-

~~~~~~~~~~~~~~~-t-~~_,,tHD;DAT

SDA 7Z87013.2

- tsu;STA

February 1991

Fig. 11 Timing.
608

- - -tsu;DAT

Signetics RF Communications
Data processor for cellular radio (DPROC)

Development Data
UMA1000T

Where: tsuF
tHD; STA tLOWmin tHIGHmin tsu; STA tHD; DAT tsu; DAT tr tf tsu; STO

t >tLOWmin
t>tHIGHmin 4.7 �s 4 �s t>tLOWmin � t>O�s t > 250 ns t.;;; 1 �s t.;;; 300 ns t >tLOWmin

The minimum time the bus must be free. before a new transmission can start Start condition hold time Clock LOW period Clock HIGH period Start condition set-up time, only valid for repeated start code Data hold time Data set-up time Rise time of both the SDA and SCL line Fall time of both the SDA and SCL line Stop condition set-up time

Note All the values refer to VI H and VIL levels with a voltage swing of VDD to Vss.

'---'

'----' '----'

START ADDRESS R/W ACK

CONDITION

DATA

,___.

'----' .....___,

ACK START ADDRESS R/W ACK

CONDITION

Fig. 12 Complete data transfer.

STOP 7287014

Where:

Clock tLOWmin

4.7 �s

tHIGHmin

4 �s

The dashed line is the acknowledgement of the receiver

Max. number of bytes

Unrestricted

Premature termination of transfer

Allowed by generation of STOP condition

Acknowledge clock bit

Must be provided by the master

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Data processor for cellular radio (DPROC)

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UMA1000T

12 C REGISTERS

General

The 12 C register block resides internally within the 12 C interface block and contains various items of status and control information which are transferred to and from DPROC via the 12 C-bus. The block is organized into four 8-bit registers:

� Status Register � Control Register � SAT Programmable Phase Shift Register � TEST Register

contains read only items
l contain write only items
J

Note
In normal operation the SAT delay register and the TEST register require programming only after a device reset.

Table 3 Register map

bit

register

7

6

5

4

3

2

1

0

status control SATO

-

-

WSYNC BUSY

TXABRT TXIP

MSCC1 MSCCO

-

SERV

STS

TXRST AB REN FVC

STEN SATEN

<---------------------------------------------------- SAT delay data ------------------------------------------------>

_L

_L

J.

_i

I

J.

J.

I I I I s

DPROC ADR

R

A

STATUS

A

p

(a) read from DPROC status register

I I I I I I I I s DPROC ADR

w A

CONTROL A

p

(b) write to DPROC control register

s DPROC ADR w A CONTROL A SAT DELAY A TEST A p
(c) write to all DPROC registers

Where:

S W R A P DPROC ADR TEST

: START condition : read/write bit (logic 0 =write) : read/write bit (logic 1 =read) : acknowledge bit : STOP condition : slave address of DPROC : must be programmed to logic 0 for normal operation

Fig. 13 12 C data format.

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UMA1000T

Status Register This is a read only register containing DPROC status information.

Measured SAT Colour Code (MSCC1; MSCCO) MSCC1 and MSCCO provide information about the current measured SAT colour code in accordance with Table 4.

Table 4 Measured SAT Colour Code

MSCC1

MSC CO

SAT frequency (Hz)

0

0

5970

0

1

6000

1

0

6030

1

1

no valid SAT

Transmission In Progress (TXI Pl TXIP indicates whether DPROC is currently accessing the Reverse Control or Voice Channels.
� logic 1 : data transmission in progress � logic 0 : transmission not in progress

Transmission Abort Status (TXAB RT) TXABRT indicates that a Reverse Control Channel Access Attempt has been aborted by DPROC without successful message transmission. � logic 1 : transmission attempt aborted � logic 0 : no access collision detected
Reverse Control Channel Status (BUSY) BUSY gives the status of the Reverse Control Channel. This is determined by a majority decision on the result of the last 3 consecutive Busy-Idle bits on the Forward Control Channel.
� logic 1 : channel busy � logic 0 : channel idle On a voice channel the BUSY bit defaults to the set state.

Note This signal is also routed to the BUSY output pin.

Word Synchronization Indicator (WSYNC) WSYNC indicates whether DPROC has acquired frame synchronization according to the Forward Control Channel format.
� logic 1 : frame synchronization acquired � logic 0 : no frame synchronization

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UMA1000T

12 C REGISTERS (continued)
Control Register This is a write only register containing DPROC control information.

SAT Path Enable (SATEN) SATEN enables the SAT transponded signal to be output on external pin DATA.
� logic 1 : SAT tone enabled
� logic 0 : SAT tone inhibited

Signalling Tone (ST) Path Enable (STEN)
STEN enables the Signalling Tone to be output on external pin Data.
� logic 1 : ST enabled
� logic 0 : ST inhibited

Channel Format Select (FVC)
FVC selects the required channel format.
� logic 1 : Voice channel format
� logic 0 : Control channel format

Transmission Abort Permission (AB REN)
AB REN indicates whether DPROC has permission to abort data transmission and disable RF on the Reverse Control Channel following the detection of a channel access attempt collision.
� logic 1 : RF disable allowed � logic 0 : RF disable inhibited

Message Transmission Abort (TXRST)
TXRST terminates a message being transmitted on the reverse channel. It is a monostable signal which when activated causes a reset of the message transmission circuitry and causes TXABRT and TXIP 12 C signa Is to be reset. This signal does not clear the DPROC transmit register; therefore if a word has been loaded into DPROC after a TXABRT has occured the control line TXHOLD should be held LOW to allow the word to be cleared from the DPROC input register.
� logic 1 : reset active � logic 0 : reset inactive

System Type Select (STS)
STS selects required system format.
� logic 1 : AMPS
� logic 0 : TACS
Note Toggling this signal also resets the receive logic in DPROC.
Serving System Select (SE RV)
SE RV selects which of the serving system data streams (A or B) is accepted. � logic 1 : system A selected � logic 0 : system B selected

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UMA1000T

SAT Programmable Delay Register (SATO)
SATO programs the value of phase shift which is applied to the SAT tones in the SAT Regeneration Block. This value will be determined and programmed into the System Controller during manufacture. The recovered SAT is delayed in time by approximately 0.8 �s x value in the register which corresponds to approximately 1,8 degrees x value in the register. The total phase shift is limited to 360 degrees.
The ability to adjust SAT phase angle is not necessary in current AMPS and TACS systems. Therefore this register should normally be in AMPS and TACS, this function is not necessary and should programmed to zero.
DIGITAL CIRCUIT BLOCKS General
The majority of the digital circuitry within the DPROC device is identical for both AMPS and TACS. The device has little additional redundancy to implement both systems. The functions of these blocks are described in the following sections and relate to those shown in Fig. 1. Data Recovery
The Data Recovery Block receives wideband Manchester encoded data in sampled and sliced form from the Strobed Comparator Block, on which it performs the following functions:
� clock recovery � Manchester decoding � data regeneration
The Clock Recovery Block extracts an 8 or 10 kHz (TACS or AMPS) phase locked clock signal from the Manchester encoded data stream. This is implemented using a digital-phase-locked-loop (PLL) which has an adjustable "bandwidth" to provide both fast acquisition and low jitter.
Manchester decoding is performed by exclusive ORing the recovered Manchester encoded data with the recovered clock.
The N RZ data regeneration is performed by a digital integrate and dump circuit. This consists of an up/down counter that counts 1.2 MHz cycles during the data period. The sense of the count is determined by the result of the Manchester Decoder output. The number of counts is sampled at the end of a data period. If this number exceeds a threshold the data is latched as a 1 otherwise it is latched as a 0. SAT Processing
The Supervisory Audio Tone processing consists of the following functions:
� SAT recovery � SAT determination � SAT regeneration

SAT recovery
The SAT Recovery Block receives a filtered and sliced SAT signal which must be recovered before being routed to the Determination and Regeneration Blocks. The recovery is performed using a digital phase-locked-loop.

SAT determination
The SAT Determination Block indicates which, if any, of the valid SAT tones is detected from the recovered SAT. The AMPS and TACS specifications require that a determination is made at least every 250 ms. Determination involves counting the number of cycles of the regenerated SAT in this time period. This count is then compared to a set of four known counts which define the boundaries between the SAT frequencies and the SAT not valid events. The resu It is then coded into the 12 C status registers MSCCO and MSCC1 as shown in Table 5.

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UMA1000T

Table 5 Status registers MSCCO, MSCC1; decoded SAT frequencies

register MSC CO MSCC1

1

1

0

0

0

1

1

0

1

1

SAT frequency band (Hz �4 Hz)
<5956 5956 to 5986 5986 to 6014 6014 to 6046
>6046

decoded SAT (Hz)
not valid 5970 6000 6030 not valid

SAT regeneration

The SAT Regeneration Block generates a digital SAT stream from the recovered SAT stream for transponding back to the base station. The AMPS and TACS specifications require the SAT to be transponded with a maximum phase shift of 20 degrees between the point the modulated RF signal enters the mobile from the base station, and the point the modulated RF leaves the mobile. A variable phase compensation circuit is provided in DPROC to shift the recovered SAT through 0 to 360 degrees before being passed to the output summing network. The degree of phase shift is determined during manufacture of the set and the required additional phase shift is stored in non-volatile RAM and programmed via 12 Cat each power-on cycle. The phase correction is performed by a counter delay method using signals which are phase locked to the recovered SAT.

Dotting Detector

The Dotting Detector Block determines whether a data inversion (dotting) pattern has been received on the Forward Voice Channel. The detection of 32 bits of data inversion indicates that the Clock Recovery Block has acquired bit synchronization and that the narrow bandwidth mode on the clock recovery phase-locked-loop is selected. This signal is also used to indicate that a data burst is expected and activates the audio mute RACTR L, after a Word Synchronization Block has been received, for the duration of the burst.

Word Synchronization Detector

The Word Synchronization Block performs the following functions:

� Frame synchronization � Reverse Control Channel status (B/I determination) � Valid Serving System determination
These functions are associated solely with the Forward Control Channel and have no meaning on the Forward Voice Channel.

Information in a data stream is identified by its position with respect to a unique synchronization word. This synchronization word is an 11 bit-Barker code which has a low probability of simulation in an error environment, and can be easily detected. Data received is only considered valid at times when DPROC has achieved frame synchronization. In this condition the block leaves its search mode and enters its lock mode. This is indicated by bit WSYNC being set HIGH. In order to achieve this two consecutive synchronization words separated by 463 bits must be detected. Once in lock mode, the synchronization word detector is examined every 463 bits and only loses frame synchronization after 5 consecutive unsuccessful attempts at detecting the synchronization word have been made. At this point bit WSYNC is cleared and the device is returned to its search mode. On the Forward Voice Channel detection of the synchronization word indicates that the following 40 bits are valid data. Information detailing the status of the Reverse Control Channel is given by the Busy/Idle bits. These occur at intervals of 11 bits within the frame, the first occurring immediately following the synchronization word. The status of the channel is determined by a majority decision on the last three consecutive Busy/Idle bits.

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UMA1000T

Majority Voting Block The Majority Voting Block performs the following functions:
� identifying position and validity of frames in the received data stream � extracting 5 repeats of each word from a valid frame � performing a bit-wise majority decision on the five repeats of the data word
The validity of the frames is determined by setting a counter in operation which times out and resets the circuitry after 920 or 463 bit periods from detecting valid word synchronization. The time out period selected depends on whether DPROC is monitoring the Forward Voice or Control Channel respectively. Up to five repeats of the message word are searched for and extracted by DPROC. On the forward Voice Channel DPROC will extract the first five words that occur for which a correct synchronization word is found. These words can occur in any position in the frame. A serial majority vote is performed as the fifth word is being extracted.
Error Correction Block
The Error Correction Block performs the following functions:
� extraction of a valid message from the Majority-Voted Word � computation of the S1 and S3 syndromes � correction of up to one error in the word � communication of received data to the System Controller via the Received Data Serial Link.
Interpretation of parity of a received word is obtained from knowledge of the syndromes of the word. The syndromes are calculated using feedback shift registers with two characteristic equations:
1 + X + X6 and 1 + X + X 2 + X4 + X6
Once the syndromes of a received word are known, it is possible to determine if a correctable error is present. DPROC only corrects up to one error although the code used has a Hamming distance of five. The occurence of two or more errors is signalled by setting the BCH error flag, which is communicated to the System Controller via the Received Data Serial Link.

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UMA1000T

Received Data Serial Link
The Received Data Serial Link transfers data and control information from DPROC to the System Controller. The data is transferred on AXLINE under control of a clock signal RXCLK, generated by the System Controller. The system controller is informed of the arrival of a decoded data word in the DPROC output register by AXLINE being driven LOW. If the system controll.er chooses to ignore the received data or only partially clock the data out, the DPROC will reset the receive buffer for the next word after the period RWIN (see Fig. 15).
Data Format
Each Received Data word consists of 4 bytes. The word format is shown in Fig. 14 (a). The sense
and function of the fields is shown in Table 6.

Table 6 Received Data word

bit 31 30
29 to 2 1

title start BCH error
received data AXLINE error

0

stop

sense LOW active HIGH
binary data LOW
HIGH

function
identifies start of word indicates that an uncorrected BCH error is associated with the word received data .word if detected as HIGH indicates that a transmission error has occured on the microprocessor to DPROC serial link identifies end of the word

Link Protocol
The Received Data protocol is described by the timing diagram Fig. 15 (a) and has the following parameters:
� maximum receive window (RWIN)
Control Channel (TACS) =47 ms
= Control Channel (AMPS) 37 ms
� minimum clock period (tcLK(min) = 2 �s � minimum clock hold-off (twA1Tl = 100 �s
Transmit Data Serial Interface
The Transmit Data Serial Link performs reception of data from the System Controller to DPROC over a dedicated line TXLINE. The transfer of data is synchronous with a clock signal TXCLK, generated by the System Controller.

Data Format
Each Transmit Data word consists of 5 bytes. The word format is shown in Fig. 14 (b). The sense and
function of the fields is shown in Table 7.

Table 7 Transmit Data word

bit
39 38,37 36 to 1 0

title
start DCC transmit data stop

sense
LOW binary data binary data HIGH

function
identifies start of word digital colour code transmit data word identifies end of the word

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UMA1000T

Link Protocol
Messages are normally up to 5 words in length on the Reverse Control Channel and up to 2 words in length on the Reverse Voice Channel. However, DPROC will transmit messages of any word length. These must be transmitted on the data stream without interruption. To avoid the need for large buffer areas, a flexible protocol is used to allow DPROC to control the transfer of data words. DPROC has an on-chip buffer which can hold one complete word of a message. Whilst new words are being loaded into DPROC, within the time period Buffer clear to end of TWIN, DPROC will maintain uninterrupted data transmission. The System Controller can abort the transmission of a message at any point activating the l 2 C signal TXRST. This signal causes the interface to return to its power-up state and resets TXIP and TXABRT (see Table 3). On completion of these tasks TXRST will return to its inactive state. The Transmit Data Protocol is described by the timing diagram shown in Fig. 15(b) and has the following parameters:
� maximum transmit window (TWIN) voice channel (TACS) = 60 ms voice channel (AMPS) = 48 ms control channel (TACS)= 29 ms control channel (AMPS)= 23 ms
� minimum clock period (tcLK(min)l = 2 �s

MSB START Bit 31

BCH ERROR JRECEIVED WORD (28 bits) ~

! JcHECK BIT(= 0)

LSB STOP

Bit 30

Bit 29

Bit 2 Bit 1

Bit 0

(a) received data word

MSB START Bit 39

DCC 1 DCC 0 TRANSMIT WORD (36 bits) Bit 38 Bit 37 Bit 36
(b) transmit data word Fig. 14 Data word formats.

Bit 1

LSB STOP Bit 0

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UMA1000T

DIGITAL CIRCUIT BLOCKS (continued)

RWIN - - - - - - - - - - - - - � 1

....,_ bit31-+--+- bit30~ .... bit29 ....

~ bit 2 -+-~ bit 1 .__...._bit 0 .......

AXLINE
I

RXCLK

- twAIT
(a) DPROC to microcontroller link; receive data timing.

TX LINE

-bit39 -

bit38-+

DPROC holds TX LINE LOW

buffer cleer

TXCLK

�---TWIN7222083.1

Where:

tHo =100 ns minimum

tsu

0 ns minimum

twAIT = 0 ns minimum

(b) Microcontroller to DPROC link; transmit data timing.

(1) The buffer busy time depends on whether the first or subsequent words are being loaded.
(2) The system controller should monitor the TXLINE during bit 0, if the status of TXLINE does not change from a HIGH to a LOW on the rising edge of TXCLK, then a framing error has occured. This can be caused by glitches on the clock line or if an arbitration error occured while the DPROC transmit register was being loaded. The system controller should recover the situation by holding TX LINE HIGH and supplying clocks on TXCLK until TXLINE goes LOW. Then the situation should be treated as a normal channel arbitration failure as described in Reverse Control Channel Access Arbitration - Abort Procedure.

Fig. 15 Data timing diagrams.

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UMA1000T

BCH and Manchester Encoding Block
The functions performed by this circuit block include:
� reception of data from the System Controller � parity generation � message construction � Manchester encoding Each 36-bit Information Word sent on the Reverse Voice and Control Channels is coded into a 48 bit code word. The code word consists of the 36-bit word followed by 12 parity bits. These parity bits are formed by clocking the information word into a 12-bit feedback shift register with characteristic equation:
1 +X3 +X4 +xs +xs +xio +x12
The BCH Encoder Block constructs the Reverse Voice and Control Channel data streams from the information it receives from the System Controller. The streams are formed out of the four possible field types:
� Dotting (data inversions) � 11-bit Synchronization Word � Digital Colour Code � 48-bit code word
The 2 bits of DCC received from the System Controller are coded into a 7-bit word as shown in Table 8.

Table 8 Digital Colour Code; 7-bit word

DCC1
0 0 1 1

DCCO
0 1 0 1

0 0 0 0 1 1 1 1
L___J
DCC1

Coded DCC

0 0 0 0 0

1 1 1 1 1

000 11

1 1 1 00

l

I

L___J

DCCO DCC1 .EXOR .Deco

The data sense for Manchester Encoding has a NRZ logic 1 encoded as a O-to-1 transition and a NRZ logic 0 encoded as a 1-to-O transition.

February 1991

619

Signetics RF Communications
Data processor for cellular radio (DPROC)

Development Data
UMA1000T

DIGITAL CIRCUIT BLOCKS (continued) Reverse Control Channel Access Arbitration
The AMPS and TACS specifications require a method of arbitration on the Reverse Control Channel to prevent two mobiles from transmitting on the same channel at the same time. This function is performed by DPROC monitoring the Busy/Idle stream sent on the Forward Control Channel.
The AMPS and TACS specifications state that once the mobile has commenced transmitting on the Reverse Control Channel it must monitor the Busy/Idle stream. If this stream becomes active outside a predetermined 'window', measured from the start of the transmission of the message, the mobile must terminate its transmission and disable the transmitter immediately.
In the Cellular Radio chip-set there are two levels of control of the RF transmitter; the first is absolute control by the System Controller, the second is conditional by other devices in the set. In DPROC the conditional control of the transmitter is performed via the output TXCTR L. This line is effectively wired ANDed together, using open-drain outputs, with other devices which may wish to control the transmitter. When these devices do not wish to disable the transmitter their output is in a HIGH impedance state.
An exception to this procedure occurs when the Serving System instructs the mobile not to monitor the Busy/Idle bits. In this event the arbitration logic can be disabled by clearing 12 C register bit AB REN.
The flow of events during a Control Channel Access attempt is as follows:

Initial State

� transmitter power off via 12 C � DPROC transmit circuitry in power-up state � TXCTRL line HIGH Access Attempt Procedure

1. System Controller decides to send message (note 1). 2. System Controller drives TXCTR L low directly. 3. System Controller switches transmitter power on and waits for power-up for the transmitter
module (RF transmitter is still disabled by TXCTRL).
4. System Controller sets TXRST via 12 C to DPROC.
5. System Controller sets AB REN via 12 C (if required) allowing DPROC to control the transmitter. 6 System Controller determines status of Reverse Control Channel by monitoring the Busy/Idle
bit. If busy, waits a random time then tries again. 7. System Controller releases TXCTR L allowing it to be pulled HIGH enabling the transmitter output. 8. System Controller transfers the first word of the message to DPROC via serial link (note 1). 9. DPROC sets 12 C signal TXI P and starts sending message while monitoring Busy/Idle status. 10. If channel becomes busy before 56 bits and AB REN is set then perform Abort Procedure. 11. If channel remains idle after 104 bits and AB REN is set then perform Abort Procedure. 12. System controller loads the subsequent words of the message into DPROC when the buffer
becomes clear (Fig.15b). 13. On completion of entire message DPROC clears TXIP and 25 ms later the System Controller
disables transmitter via 12C. 14. System Controller finally sends TXRST to prepare DPROC for next transmission.

Note to the Access Attempt Procedure

1. At stage 1 the system controller may choose to preload DPROC with the first word of the message

and hold it from transmission until stage 7 using the TXHOLD line. This gives a lower time overhead

between detecting an IDLE channel and commencing the transmission. To use this feature TXHOLD

must be driven HIGH before the last bit of data has been transferred into DPROC.

Figure 16 illustrates the DPROC data transmission timing.

February 1991

620

Signetics RF Communications
Data processor for cellular radio (DPROC)

Development Data
UMA1000T

DPROC

DPROC

DPROC

1~w~l ~n\ ~oo~~~l1---~ TXLINE

holds LOW TXLINE
word 1

releases TXLINE
word 2

holds LOW TXLINE
I I

11
TXHOLD

DPROC data ----11111111111111111111111111111111111
dotting W.S. DCC word 1 Parity word 1

I 1.' ! 11

. II

Panty, ,

word 1

q
Parity

repeat1

repeat 2

II

repeat 5

30

11 7

36

12

36

12

36

12

DPROC

releases

DPROC

c:::>_n..o..o._________ __;;_ TXLINE
continued

TXLINE

\

word 3

I I holds LOW TXLINE

word 4

--i1 _1_ ___.n~oo

/ I
q

II

II

q TXHOLD

" q

continued

~~~~~~~~~~~~~--1 1--~~~~~~~~~~~~---; /,..........:

DPROCdataq continued Parity
12

word 2 repeat 1
36

Parity 12

word 2 repeat 2
36

Parity

I 1 I ---~~~~~~~~~~~--11 )___

" q

I I

-I _._~~__.~.._~~~--'"--Ii
I

~

word2 Parity word 3 Parity

II
12

repeat 5

repeat 1

II

36

12

36

12

TXLINE

continued

II

II
TXHOLD continued

--.------.---.----....---.--<I ~I--..------.-~

DPROCdataq

continued

_ __.._ _ _ _.___.__ _ ___,.___.__,/ ,~I_..___ _ _....___,

Parity word n Parity word n Parity

repeat 1

repeat 2

I I

12

36

12

36

12

word n Parity

repeat 5

36

12

Fig. 16 DPROC data transmission timing/microcontroller interface.

MEA173

February 1991

621

Signetics RF Communications
Data processor for cellular radio (DPROC)

Development Data
UMA1000T

DIGITAL CIRCUIT BLOCKS (continued)
Abort Procedure (see Fig. 17) 1. DPROC immediately disables transmitter output by driving TXCTR L low. 2. DPROC sets TXABRT. 3. System Controller detects failure by monitoring TXCTR Land TXABRT. 4. System Controller disables transmitter via RF power amplifier. 5. System Controller sends TXRST to prepare DPROC for next transmission.
Note If a message is loaded into DPROC after a TXABRT has occured this word will remain in the DPROC transmit register and will not be cleared to TXRST. If this situation arises the method of clearing the buffer ready for a second access attempt is to leave TXHOLD LOW and then send a TXRST prior to setting up a new transmission after TXLINE goes HIGH; this will clear any residual data in the buffer.
Signal Tone Generation (ST) The 8 or 10 kHz (TACS or AMPS) tone generated from the Manchest~r Encoding Block is used as the Signalling Tone stream.

February 1991

622

Signetics RF Communications
Data processor for cellular radio (DPROC)

Development Data
UMA1000T

TXLINE TXHOLD

DPROC holds LOW
TXLINE
word 1
JOO l

DPROC

arbitration failure

releases TXLINE

DPROC holds LOW

Busy/Idle stream remains Idle

TXLINE word2
\noo l

after 104 bits

I I

11
''
11

.11;_

12C-bus send

TXRST to DPROC

DPROC ready for

new transmisson

DPROCdata ------1llllllllllllllllllllllllllllllarr=ID---/1.1--,I- - -

BUSY

dotting W.S. DCC word 1 Parity word 1 , ,

repeat1

repeat 2 / /

30

11 7

36

12 truncated, ,

~~~~~~~~~~10~ 4 bi~ ts ~~~~~;11L~�~~~~~~~~~ ! !

TXCTRL

----+--'1
/ L,__.I
'.'

Fig. 17 DPROC data transmission timing/microcontroller interface during arbitration failure.

February 1991

623

Signetics RF Communications
Data processor for cellular radio (DPROC)

Development Data
UMA1000T

ANALOG CIRCUIT BLOCKS

General

The analog signal processing functions on DPROC are implemented using switched-capacitor

techniques. The main filtering functions are operated at 300 kHz, and these circuits are 'interfaced'

to the continuous time and sampled digital domains by distributed RC active filters, passive

I

interpolators and comparators.

I�

The distributed RC sections, the Anti-Alias Filter and the Clock Noise Filter, are non-critical and are designed to tolerate process spreads. The critical filtering in the SAT Filter and the Output Filter, is performed by 300 kHz switched-capacitor circuitry. The Passive lnterpolators increase the sampling rate from 300 kHz to 1.2 MHz. The sampled analog signals from the Passive Interpolators are converted to sampled 2-state digital signals by the Strobed Comparators. The Gated Digital-to-Analog converters and Analog Summer blocks perform resynchronization and sub-sampling of the digitally

generated DPROC output signals, and conversion to the sampled analog domain.

These analog section of the device are shown in Fig. 1.

Reference Voltage Generator
The Reference Voltage Generator generates the analog ground referenr:e voltage (AGND) used internally within the DPROC device. To minimize noise AGND must be externally decoupled to VssA as shown in Fig. 18.

Anti-Alias Filter
The Anti-Alias Filter is placed before the SAT sampling block to prevent any unwanted signals or high-frequency noise present on the DE MOOD pin being aliased into the pass-band by the sampling action of the switched-capacitor filter. To achieve this the Anti-Alias Filter is a continuous timedistributed RC-active low-pass filter.

SAT Input Filter
The SAT Input Filter is a switched-capacitor filter which provides band-pass filtering of the SAT signals from the DE MOOD pin to improve the SAT signal-to-noise ratio prior to recovery and transpond ing.

Passive lnterpolator
The function of the Passive lnterpolator is to increase the sampling rate at the output of the switched-capacitor filters. This reduces the coarseness of the zero crossing information which would otherwise cause unacceptable isochronous distortion in the recovered signal.

Strobed Comparators
The Strobed Comparators form the analog-to-digital interface for the received data and SAT signals from the DEMODD pin. These comparators act as limiting amplifiers wich convert the filtered sampled analog signals into 2-state sampled digital signals containing only the zero-crossing information from the analog signal.

February 1991

624

Signetics RF Communications
Data processor for cellular radio (DPROC)

Development Data
UMA1000T

Gated Digital-to-Analog and Analog Summer
The Gated Digital-to-Analog converters and Analog Summer form the interface between the digital and analog circuitry on the transmit path of DPROC. It is at this point that the three sampled digital signals, containing SAT, ST and encoded digital data, are combined to form a composite signal. The data streams are enabled by the 12 C signals STEN, SATEN and the internal signal DATAEN respectively (DATAEN disables SAT and ST when data is being transmitted). The digital-to-analog conversion and sub-sampling operation is performed by the Gated Digital-to-Analog converters and Analog Summer. The relative signal weights applied in the summer (with respect to the data path) are shown in Table 9.

Table 9 Relative signal weights

signal
ST SAT DATA

relative output level AMPS and T ACS
1.0 0.25 1.0

Output Filter The Output Filter is a switched-capacitor filter which performs band-limiting of the DPROC output signals in accordance with the AMPS and TACS specifications. The required below band roll-off is achieved via external AC coupling from the DATA pin.
Clock Noise Filter The filter is a non-critical continuous time-distributed RC-active low-pass filter used to remove any switching transient residues from the output signal.

February 1991

625

I alternative clock using DPROC

~

on-chip oscillator circuit

vDD (+5V)

1.2MHz

~ 1Mnl

13

""~"" 12

10�F~ 100 ~
9
28 i.e. ----I 10
i.e. - - 1 9

lSDA 24

j_SCL 25 19 BUSY
AXLINE 8
RXCLK 27

c } 12 interface
... MICROCONTROLLER (PCB80C552)

TXLINE 15

RECEIVER SUBSYSTEM
1.2MHz OUTPUT
~

demodulated data/audio 270pfl

Q 10 nf
_JL
II100 k!l

DEMODD 3

1-r,ool 22�F 1nf

AGND 2
VssA 1

VssD

-;Ji

14

l INVTX 21 INVRX
~BUFOUT 7

n.c.

13

TXCLK 18

GENERAL PURPOSE l/Oports

DATA PROCESSOR UMA1000T

TXHOLD 17
RESET 26

r+

SYNCCLK 16
TEST 6
Al 22

J

power-on-reset

' l

vDD

-(+5Vj

1.2MHZ

CLKIN

12

23 r -AO- T - - - - - - vDD

* 4

20

11

5

DATA 1XCTRL TACTRL RACTRL

(+5V)

TXDIS

TRANSMITTER SUBSYSTEM

~
modulation MODOUT line

=r
'vox DEMOD

jAGND

*
DATA

AUDIO PROCESSOR

Fig. 18 DPROC application circuit.

TX MUTE
RX
f+- MUTE

Ml.All34-1

~

.. a0 ~ 8'

I� ~

a"O

0 0
3

(')
CD
"".0...''.

3 c
::J
[
.6"
::J

0.....

(')
CD
c:

~

-ea~ r .
0
""CJ
JJ
-0
0

cs:: .)..>..

[

1 0
0 0

-I ~

SlgneHcs RF Communications

Section 6 Frequency Synthesizers, Pagers, and Data Receivers

INDEX

NE/SA701

Divide by: 128/129-64165 dual modulus low power ECL prescaler . � � � . . � . . . . . . � . . . . . . � . . . . . . . . � � . � . . . . . 629

NE/SA702

Divide by: 64165172 triple modulus low power ECL prescaler .. .. .. .. . .. .. .. . .. .. .. . . .. . . .. .. .. .. .. 633

NE/SA703

Divide by: 12811291144 triple modulus low power ECL prescaler . . . . � . . . . � � . . . . . . . � . . � � � . . � . . � � . . � . . � � 637

TDD1742T CMOS frequency synthesizer .......................... 641

TSA6057fT Radio tuning PLL frequency synthesizer . . . � . . . . . . . . . � . . . � 663

TSA5511

1.3GHz bi-directional 12C bus controlled synthesizer . . � . . . � � 672

UMA1014T Frequency synthesizer for cellular radio communication � � . . . . 683

UMF1005T Low-power frequency synthesizer � . . . � . � . � . � � . � . . � � � � � . . 697

SCO/AN91004 Application report for the LIMA1014T frequency synthesizer . . 718

UMF1009T Low power frequency synthesizer for radio communication . � � 746

Signetics RF Communications
Divide by: 128/129-64/65 dual modulus low power ECL prescaler

Objective specification
NE/SA701

DESCRIPTION The NE701 is an advanced dual modulus (Divide By 128/129 or 64/65) low power ECL prescaler. The minimum supply voltage is 2.5V for compatibility with the new CMOS UMF1005 and UMF1009 synthesizers from Philips and other logic circuits. The maximum supply current is 2.SmA allowing application in battery operated low-power equipment Maximum input signal frequency is 1.2GHz for cellular and other land mobile applications. There is no lower frequency limit due to a fully static design. The circuit is implemented in ECL technology on the HS4+ process (lhe bipolar portion of the OU BiC process). The circuit will be available in an 8 pin SO package wilh 150 mil package width.

FEATURES �Low voltage operation �Low current consumption �Operation up to 1.2GHz
APPLICATIONS �Cellular phones �Cordless phones �RF LANs �Test and measurement �Military radio �VHF/UHF mobile radio �VHF/UHF hand-held radio

PIN CONFIGURATION

DPackage

INOBIR

vcc2

7nc

sw3

8MC

OUT 4

5 GND

ORDERING INFORMATION DESCRIPTION
8-Pin Plastic SO (Surface-mount) 8-Pin Plastic SO (Surface-mount)

TEMPERATURE RANGE o to +70�C -40 to +B5�C

ORDER CODE NE7010 SA701D

ABSOLUTE MAXIMUM RATINGS

SYMBOL

PARAMETER

Vee Maximum operating voltage

V1N Input voltage

lo Output current

TsTG Storage temperature range

TA Operating ambient temperature range

9JA Thermal impedance

RATING -0.5 to +7.0 -0.5 to Vee
10 -65 to +125 -55to +125
90

UNITS
v v
mA
oc oc
�C/W

April 16, 1991

629

Signetics RF Communications
Divide by: 128/129-64/65 dual modulus low power ECL prescaler
BLOCK DIAGRAM

Objective specification
NE/SA701

April 16, 1991

630

Signetics RF Communications
Divide by: 128/129-64/65 dual modulus low power ECL prescaler

DC ELECTRICAL CHARACTERISTICS

The following DC specifications are valid for-40�C <TA< +85�C; unless otherwise stated.

SYMBOL

PARAMETER

TEST CONDITIONS

Vee Power supply voltage range Ice Supply current VoH Output high level VoL Output low level

V1H MC input high threshold

V1L MC input low threshold

11

MC input current

V1H SW input high threshold

V1L SW input low threshold

11

SW input current

lour= 1.2mA
Vcc~3.2V
Vrx; < 3.2V 1Mc=60�A 1Mc=20�A VMe = Vrx; = 5.0V
Vsw =Vee= 5.0V

Objective specification
NE/SA701

LIMITS

MIN

TYP

2.5

Vcc-1.4

2.0

2.0

UNITS

MAX

6.0

v

2.8

mA

v

Vcc;-3.0 v

0.2

v

v

0.8

v

150 �A

v

0.8

v

100 �A

AC ELECTRICAL CHARACTERISTICS

The following AC specifications are valid for Vrx; = 3.0V, -40�C <TA< +85�C; unless otherwise stated.

SYMBOL

PARAMETER

TEST CONDITIONS

VtN Input signal amplitude

f1N

Input signal frequency

Rio Differential input resistance C1 Input capacitance Vo Output voltage

ts

Modulus set-up time

Iii

Modulus hold time

lpo Propagation time

1000pF input coupling Direct coupled input 1000pF input coupling
DC measurement
Vrx;= 5.0V Vrx;=3.0V ftN= 1.2GHz ftN= 1.2GHz

LIMITS

UNITS

MIN TYP MAX

0.1

2.0 Vp.p

0

1.2 GHz

1.2 GHz

5

kn

TBD pF

1.6

Vp.p

1.2

Vp.p

TBD

ns

TBD

ns

TBD

ns

DESCRIPTION OF OPERATION The NE701 comprises a frequency divider circuit implemented using a divide by 4 or 5 synchronous prescaler followed by a fixed 5 stage synchronous counter, see BLOCK DIAGRAM. The normal operating mode Is for SW (Modulus Set Switch) input to be set low and MC (Modulus Control) input to be set high in which case the circuit comprises a divide by 128. For divide by 129 the MC singal is forced low, causing the prescaler circuit to switch into divide by 5 operation for the last cycle of the synchronous counter. Similarly, for divide by 64 and 65 the NE701 will generate those respective moduli with the SW signal forced high, in which the fourth stage of the synchronous divider is bypassed.

A truth table for the modulus values is given below:

Table. Modulua 128 129 64 65

MC

SW

1

0

0

0

1

1

0

1

For minimization of propagation delay effects, the second divider circuit is synchronous to the divide by 4/5 stage output.
The prescaler input is positive edge sensitive, and the output at the final count is a failing

edge with propagation delay tpo relative to the input. The rising edge of the output occurs at the count 64 for modulus 128/129 or count 32 for modulus 64/65 with delay 1p0� The SW input is not designed for synchronous switching.
The MC and SW inputs are TTL compatible threshold inputs operating at a reduced input current. CMOS and low voltage interface capability are allowed. The SW input has an internal pull-down simplifying modulus group selection. With SW open the divide by 128/129 mode is selected and with SW connected to Vee divide by 64/65 is selected.
The prescaler input is differential and ECL compatible. The output is single-ended ECL compatible.

April 16, 1991

631

Signetics RF Communications
Divide by: 128/129-64/65 dual modulus low power ECL prescaler

Objectiw specification
NE/SA701

AC TIMING CHARACTERISTICS

cou::~nJL_t~f1_flh_

MC-!___._L1-1 � I
J OUT I ,__L ____..
1 I tpo

I
SW= 0. DIVIDE BY 1211129 OPERATION.

? ~

I

I

L I

I

_L_-__-_:- -

,- ts -,- Ill - 1

cou: ~nJL_tLrl_fUL,f1-fLr1--h-

llC

! ~I

I

~ ~ --~1....
OUT

tpo

I

1'

I

I~IS~

SW � 0. DIVIDE BY 1211129 OPERATION.

C

I

I

I

I

I

~~

cou: l___fLh,nJL_t~NLh_

L11 MC

i

I

r ~

I I
--~1....

OUT

I

I
-i

r-

I

I

I

I

I

I

I

I '---+I- -

~ts --i--~

tpo

SW= 1. DIVIDE BY 114115 OPERATION.

cou: '---fLh,nJLfLrl_fUL,f1-fl-tlJL

llC

! ~I

I I

--+I~

OUT

I

I
-i

r-

tpo

I
SW � 1. DIVIDE BY 114115 OPERATION.

1' � ! .

I

I

I

I

I

I

~ts --1

! C

I

I

I

I

I

I

I '----i-1--

~~

April 16, 1991

632

Signetlcs RF Communications
Divide by: 64/65/72 triple modulus low power ECL prescaler

Objective specification
NE/SA702

DESCRIPTION
The NE702 triple modulus (Divide By 64/65/72) low power ECL prescaler is used in synthesizer systems to achieve low phase lock time, broad operating range, high reference frequency and small frequency step sizes. The minimum supply voltage is 2.5V for compatibility with the new CMOS UMF1005 and UMF1009 synthesizers from Philips and other logic circuits. The maximum supply current is 2.8mA allowing application in battery operated low-power equipment. Maximum input signal frequency is 1.2GHz for cellular and other land mobile applications. There is no lower frequency limit due to a fully static design. The circuit is
implemented in ECL technology on the HS4+ process (the bipolar portion of the OU BiC process). The circuit will be available in an 8 pin SO package with 150 mil package width.

FEATURES
�Low voltage operation �Low current consumption �Operation up to 1.2GHz
APPLICATIONS
�Cellular phones �Cordless phones �RF LANs �Test and measurement �Military radio �VHF/UHF mobile radio �VHF/UHF hand-held radio

ORDERING INFORMATION
DESCRIPTION 8-Pin Plastic SO (Surface-mount) 8-Pin Plastic SO (Surface-mount)

TEMPERATURE RANGE 0 to +70'C -40 to +85'C

ORDER CODE NE702D SA702D

PIN CONFIGURATION
D Package

VeIeN2 OSIN7 GND

MC2 3

6 MC1

OUT 4

5 OUT

ABSOLUTE MAXIMUM RATINGS

SYMBOL

PARAMETER

Vee Maximum operating voltage

V1N

Input voltage

lo

Output current

Tsrn Storage tern perature range

TA

Operating ambient temperature range

0JA

Thermal impedance

RATING -0.5 to +7.0 -0.5 to Vee
10 -65 to +125 -55to +125
90

UNITS
v v
mA 'C 'C 'C/W

April 16, 1991

633

Signetics RF Communications
Divide by: 64/65/72 triple modulus low power ECL prescaler
BLOCK DIAGRAM

Objective specification
NE/SA702

April 16, 1991

634

Signetics RF Communications
Divide by: 64/65/72 triple modulus low power ECL prescaler

DC ELECTRICAL CHARACTERISTICS

The following DC specifications are valid for-40�C <TA< +85�C; unless otherwise stated.

SYMBOL

PARAMETER

TEST CONDITIONS

Vee Power supply voltage range Ice Supply current VoH Output high level Vol Output low level

V1H MC1 ,2 input high threshold

V1L MC 1,2 input low threshold

11

MC 1,2 input current

lour= 1.2mA
Vcc~3.2V
Vcc<3.2V 1Mc=60�A IMc = 20�A VMc =Vee = 5.0V

Objective specification
NE/SA702

MIN 2.5 Vcc-1.4
2.0

LIMITS TYP

UNITS

MAX

6.0

v

2.8

mA

v

Vcc-3.0 v

0.2

v

v

0.8

v

150

�A

AC ELECTRICAL CHARACTERISTICS

The following AC specifications are valid for Vee = 3.0V, -40�C <TA< +85�C; unless otherwise stated.

SYMBOL

PARAMETER

TEST CONDITIONS

V1N Input signal amplitude

f1N

Input signal frequency

Rio Differential input resistance

C1

Input capacitance

Vo Output voltage

ts

Modulus set-up time

Ii-I

Modulus hold time

lpo Propagation time

1OOOpF input coupling Direct coupled input 1OOOpF input coupling DC measurement
Vcc=5.0V Vcc=3.0V f1N = 1.2GHz f1N = 1.2GHz

LIMITS

UNITS

MIN

TYP MAX

0.1

2.0 Vp.p

0

1.2 GHz

1.2 GHz

5

kn

TBD pF

1.6

Vp.p

1.2

Vp.p

TBD

ns

TBD

ns

TBD

ns

DESCRIPTION OF OPERATION The NE702 comprises a frequency divider circuit implemented using a divide by 4 or 5 synchronous prescaler followed by a 5 stage synchronous counter, see BLOCK DIAGRAM. The normal operating mode is for MC1 (Modulus Control) to be set high and MC2 input to be set low in which case the circuit comprises a divide by 64. For divide by 65 the MC1 singal is forced low, causing the prescaler circuit to switch into divide by 5 operation for the last cycle of the sunchronous counter. For divide by 72, MC2 is set high configuring the prescaler to divide

by 4 and the counter to divide by 18. A truth table for the modulus values is given below:

Table. Modulus 64 65 72 72

MC1

MC2

1

0

0

0

0

1

1

1

For minimization of propagation delay effects, the second divider circuit is synchronous to the divide by 4/5 stage output.

The prescaler input is positive edge sensitive, and the output at the final count is a falling edge with propagation delay tpo relative to the input. The rising edge of the output occurs at the count 32 with delay lpo.
The MC1 and MC2 inputs are TTL compatible threshold inputs operating at a reduced input current. CMOS and low voltage interface capability are allowed.
The prescaler input is differential and ECL compatible. The output is differential ECL compatible.

April 16, 1991

635

Signetics RF Communications
Divide by: 64/65172 triple modulus low power ECL prescaler

Objective� specification
NE/SA702

AC TIMING CHARACTERISTICS

. I * *= cou: ~rfl_h__I'~fl-tlh-

MC~:�) (DO) J ~I

~~

i cm>

I
I�
I

OUT ----1..1..,

I I

I I

I I

I
1
-Iir-I
I OiiT ----i--+I

I

I L.....-+.I- -

I I

II _ __._I1_ _

I

I

I 14---

ts

-II +-~I

tpo

SWITCH FROll/85 TOI&!

cou: L__flnrfl_h__I'Vl.,fl_fl,~

MC

(DO)!

~I

I
--l r- OUT --+-II-, tpo

~X) I

I I

I

I I

I

I ~

ts

I -I

SWITCH FROM 185 TO n2

I

(10) I

I

I

I I

I

I

I

I~t'i-t---I+-1--

April 16, 1991

636

Slgnetlcs RF Communications
Divide by: 1281129/144 triple modulus low power ECL prescaler

Objective specification
NE/SA703

DESCRIPTION
The NE703 triple modulus (Divide By 128/129/144} low power ECL prescaler is used in synthesizer systems to achieve low phase lock time, broad operating range, high reference frequency and small frequency step sizes. The minimum supply voltage is 2.5V for compatibility with the UMF1005 and UMF1009 synthesizers from Philips and other logic circuits. The maximum supply current is 2.BmA allowing application in battery operated low-power equipment. Maximum input signal frequency is 1.2GHz for cellular and other land mobile applications. There is no lower frequency limit due to a fully static design. The circuit is implemented in ECL technology on the HS4+ process (the bipolar portion of the QUBiC process}. The circuit will be available in an B pin SO package with 150 mil package width.

FEATURES
�Low voltage operation �Low current consumption �Operation up to 1.2GHz
APPLICATIONS
�Cellular phones �Cordless phones �RF LANs �Test and measurement �Military radio �VHF/UHF mobile radio �VHF/UHF hand-held radio

PIN CONFIGURATION
D Package

VeIeN2 OOIN7 GND

MC2 3

6 MCI

OUT 4

5 OUT

ORDERING INFORMATION
DESCRIPTION B-Pin Plastic SO (Surface-mount} B-Pin Plastic SO (Surface-mount}

TEMPERATURE RANGE 0 to +70�C -40 to +B5�C

ORDER CODE NE703D SA703D

ABSOLUTE MAXIMUM RATINGS

SYMBOL

PARAMETER

Vee Maximum operating voltage

V1N

Input voltage

lo

Output current

Tsrn TA

Storage temperature range Operating ambient temperature range

9JA

Thermal impedance

RATING -0.5 to +7.0 -0.5to Vee
10 -65 to +125 -55 to +125
90

UNITS
v v
mA
oc oc oc/W

April 16, 1991

637

Signetics RF Communications
Divide by: 128/129/144 triple modulus low power ECL prescaler
BLOCK DIAGRAM

Objective specification
NE/SA703

April 16, 1991

638

Signetics RF Communications
Divide by: 128/129/144 triple modulus low power ECL prescaler

Objective specification
NE/SA703

DC ELECTRICAL CHARACTERISTICS

The following DC specifications are valid for -40�C <TA< +85�C; unless otherwise stated.

SYMBOL

PARAMETER

TEST CONDITIONS

Vee Power supply voltage range

Ice

Supply current

VoH Output high level

Vol Output low level

V1H

MC 1,2 input high threshold

V1L

MC1 ,2 input low threshold

11

MC1 ,2 input current

lour= 1.2mA Vee ;,3.2V Vee< 3.2V IMc =60�A IMc =20�A VMc =Vee = 5.0V

MIN 2.5 Vec-1.4
2.0

LIMITS TYP

UNITS

MAX

6.0

v

2.8

mA

v

Vec-3.0 v

0.2

v

v

0.8

v

150

�A

AC ELECTRICAL CHARACTERISTICS

The following AC specifications are valid for Vee = 3.0V, -40�C <TA< +85�C; unless otherwise stated.

SYMBOL

PARAMETER

TEST CONDITIONS

V1N

Input signal amplitude

f1N

Input signal frequency

Rio

Differential input resistance

C1

Input capacitance

Vo

Output voltage

Is

Modulus set-up time

tH

Modulus hold time

tpo

Propagation time

1OOOpF input coupling Direct coupled input 1OOOpF input coupling
DC measurement
Vee= 5.0V Vee= 3.0V f1N = 1.2GHz f1N = 1.2GHz

LIMITS

UNITS

MIN

TYP

MAX

0.1

2.0

Vp.p

0

1.2

GHz

1.2

GHz

5

kn

TBD

pF

1.6

Vp.p

1.2

Vp.p

TBD

ns

TBD

ns

TBD

ns

DESCRIPTION OF OPERATION
The NE703 comprises a frequency divider circuit implemented using a divide by 4 or 5 synchronous prescaler followed by a 6 stage synchronous counter, see BLOCK DIAGRAM. The normal operating mode is for MC 1 (Modulus Control) to be set high and MC2 input to be set low in which case the circuit comprises a divide by 128. For divide by 129 the MC1 singal is forced low, causing the prescaler circuit to switch into divide by 5 operation for the last cycle of the sunchronous counter. For divide by 144, MC2 is set high configuring the prescaler to divide by 4 and the counter to divide by 36. A

truth table for the modulus values is given below:

Table.
Modulus 128 129 144 144

MC1 1 0 0 1

MC2 0 0 1 1

For minimization of propagation delay effects, the second divider circuit is synchronous to the divide by 4/5 stage output.

The prescaler input is positive edge sensitive, and the output at the final count is a falling edge with propagation delay tpo relative to the input. The rising edge of the output occurs at the count 64 with delay !po.
The MC1 and MC2 inputs are TTL compatible threshold inputs operating at a reduced input current. CMOS and low voltage interface capability are allowed.
The prescaler input is differential and ECL compatible. The output is differential ECL compatible.

April 16, 1991

639

Signetics RF Communications
Divide by: 128/129/144 triple modulus low power ECL prescaler

Objective specification
NE/SA703

AC TIMING CHARACTERISTICS

_.;11 * *= cou: Lfl--h,nJV~f1_flh_

~1-l MC(2:11

- - ( X - X l_

_ _.._!....,

OUT

:

II ~11 IIi I :I

1.

I

I

I .___....I- -

1
_,1I

Ir-

I I

I .---1--

i I
I+-

ts

-

I I i.

� -

~II

lpD

SWITCH FROM1128T0/128

cou: Lfl--h,nJVV\rt-(l,nJL__fl_J-L

MC~I

I : (XXI

I

(101 I

:

I
~ ~ --+-I....
OUT

I
I~ts ~

I
~-lff-::-1--TI-l- -

lpD SWITCH FROM /128 TO /144

April 16, 1991

640

Slgnetlcs RF Communications
CMOS frequency synthesizer

Preliminary specification
TDD1742T

GENERAL DESCRIPTION
The T001742T is a low power, high-performance frequency synthesizer in local oxidation CMOS (LOCMOS) technology. The device is designed for use in channelized VHF/UHF applications especially portable and mobile radios.
The circuit incorporates many of the features of the HEF4750V (frequency synthesizer) and HEF4751 (universal divider), including a high-gain phase comparator together with an on-chip sample-and-hold capacitor and phase modulator.
A multiplexed or bus-structured programming sequence allows interface to a microcontroller or external memory (ROM/PROM); power is applied to the memory only when it is required for programming via additional on-chip circuitry.
Operation is possible with a minimum supply voltage of 7 V and a maximum input frequency of 8,5 MHz.
Encapsulation in a 28-lead mini-pac~ enables the construction of small, low power consumption synthesizers with low noise performance and high side-band attenuation.

Features
� On-chip sample-and-hold capacitor � Low power consumption � High-gain phase comparator with low levels of noise and spurious outputs � Auxiliary digital phase comparator for fast locking � On-chip phase modulator � Simple interfacing to external memory � Microcontroller compatible � Power-on reset circuitry

QUICK REFERENCE DATA

Supply voltage ranges pin 14 pin 8 pin 1
Supply current (at Tamb = 25 �C; Voo1=Voo3=7,4 V; Voo2 = 5 V)
pin 14 (phase modulator OFF) pin 8

Voo1 = V14-6 Voo2 = va-6 Voo3 = V1-6

7 to 10 V 4,5 to 5 V 7 to 10 V

1001 =114 1002 =la

max. 1,5 mA max. 100 �A

February 1987

641

;b'
CT
2
~ .~....
main programmable d1v1dermput

phase modulator input

Voo1 Voo2 Voo3

outof�lock1nd1cat1on flag output

ANALOGUE BIASSING

�z..{---aRC

uesn�

() ~

:0
.<"CD'l�

-0
(./")
....

JJ
""Tl 0 0
3

CD
.c0
CD ::J
.Q

3 c
.e"aor�
:0

-I

~
::J

:::;

CenD
j:::i"

.C..D.

feedback output +-f-�-------<�

COMPARATOR 2

DBO

~
"'

~~:.:"' { ::: 1::

:1

"""""{:;+-;fO-""~-----~ PROGRAM DATA DECODER AND PROM CONTROL CIRCUIT

program enable { " '

1npu!s

PE 2 ~----->l

memory enable + - ; C - - - - - - - o j

reset input -jf'-'-----------~

clock output

FIXED DIVIDER (-'-4)

reterenceosc1llator XTAL input

Fig. 1 Block diagram.

"U

Vs's

I -I 0

Cil
:3;�

. .0...... -"<'

-...J -0

.j::>. I\)
-I

<D
~

:0

Signetics RF Communications
CMOS frequency synthesizer

Preliminary specification
TDD1742T

PINNING

Pin functions

pin no.

mnemonic

Voo3

2

PC1

3

PC2

4

i.e.

5

CLK

6

Vss

7

DIV(M)

8

Voo2

9

FB

10

OL

11

RESET

OL
XTAL
osc
Voo1

BRA

BRC BRB MEMEN

MOD PE1

TDD1742T

PE2 AB2

AB1

ABO

DBO DB1

DB2

DB3

1Z81435

Fig. 2 Pinning diagram.

description Power Supply 3: analogue supply voltage (7 to 10 V).
Phase Comparator 1: high-gain analogue phase comparator output which is used when the system is in-lock to give low levels of noise and spurious outputs. Phase Comparator 2: low-gain digital phase comparator 3-state output which enables the achievement of fast lock times when the system is initially out-of-lock. Phase comparator 2 is inhibited when the phase is within the locking range of phase comparator 1.
internally connected (must be left floating).
Clock: clock output.
Ground: circuit earth potential. Divider: input tci the main programmable divider (8,5 MHz max.), usually from prescaler. Power Supply 2: supply voltage for TTL-compatible stages(+ 5 V � 10%).
Feedback: feedback output to control the modulus of the external prescaler. Out-of-lock: out-of-lock indication flag output. This output is HIGH when phase comparator 2 is in operation (when the system is out-of-lock).
Power-on-Reset: Following power up an initial pulse is applied to this input pin to set the internal counters.

February 1987

643

Signetics RF Communications
CMOS frequency synthesizer

Preliminary specification
TDD1742T

Pin functions (continued)

pin no.

mnemonic

description

12

XTAL

Crystal: output to external crystal to form the oscillator circuit in

combination with the OSC input.

Alternatively this pin may be used as a buffer output.

I
I�

13

osc

Oscillator: input to reference oscillator which together with the XTAL

output and an external crystal is used to generate the reference frequency.

Alternatively to OSC input may be used as a buffer amplifier for an

external reference oscillator.

14 15-18

Voo1 DB3-DBO

Power Supply 1: digital supply voltage (7 to 10 V). Data Bus: Data Bus inputs (TTL compatible).

19-21

ABO-AB2

Address Bus: TTL compatible bidirectional address bus. Provides address output to an external memory or input from microcontroller. The outputs are 3-state with internal pull-downs.

22

PE2

23

PE1

24

MOD

Program Enable 2: { TTL compatible inputs to initiate the programming cycle or strobe the internal
Program Enable 1 : data latches.
Modulator: high impedance linear phase modulator input, which applies a voltage controlled delay to the programmable divider output to the phase comparator.

25

MEMEN

Memory Enable: mode control and memory enable bidirectional pin.

If pin 25 is LOW at general reset the TDD1742T is set to the micro-

controller mode; if pin 25 is HIGH at general reset the TDD1742T is

set to the memory mode and the ROM/PROM is enabled.

26

BRB

Bias Resistor B: current mirror which acts as gain control for the phase modulator.

27

BRC

Bias Resistor C: current mirror pin which provides analogue biassing.

28

BRA

Bias Resistor A: current mirror pin which acts as gain control for phase comparator 1.

February 1987

644

Signetics RF Communications
CMOS frequency synthesizer

Preliminaiy specification
TDD1742T

FUNCTIONAL DESCRIPTION
Reference oscillator chain
The reference oscillator chain comprises a crystal oscillator and dividers to give the required frequency to drive the phase comparators. The oscillator stage is a single inverter connected between pin 12 (XTAL) and pin 13 (OSC). Satisfactory operation is achieved with crystals up to 9 MHz. Alternatively, the OSC input may be used as a buffer amplifier for an external reference oscillator. The reference divider chain comprises a fixed divide by 4-stage followed by three cascaded programmable dividers of ratios+ 12/13/14/15, + 5/6/7/9 and+ 1/2/4/8. The output of the last stage is applied as one input ( R) to the two phase comparators. Thus a number of division ratios between 240 and 4320 are possible which provides all the required VHF and UHF channel spacings with reference crystals in a 1 to 9 MHz range.

Main programmable divider
The main programmable divider is a rate feedback binary divider. As shown in figure 1 it comprises a fixed 7-bit binary divider(+ 128) and two rate selectors (n1 and no). One rate selector controls a 7-bit fully programmable dual modulus divider (+ n2/n2 + 1) and the other controls the external dual modulus prescaler (+A/A+ 1).
The overall division rate (N) is given by:
N = ( 128 n2 + n1) A+ no

Where:

o.;;; no.;;; 127 O<n1<127 1.;;;; n2 < 127.

The output from the programmable divider is fed to the phase comparators via the phase modulator and the multiplexer. The phase modulator is bypassed if not selected.

Phase comparison

The TDD1742T contains 2 phase comparators which act in close co-operation. Phase comparator 1 is

the main comparator. It is designed to have a high-gain analogue output, 4500 volts/cycle at 10 kHz (typ.).

This enables a low noise performance to be achieved. However, the output of phase comparator 1 will

saturate at high or low levels for very small phase excursions.

Phase comparator 2 is an auxiliary comparator with a wide range, which enables faster lock times to be

achieved than otherwise would be possible. This digital phase comparator has a linear� 2 7r radians phase

V~o range, which corresponds to a gain of

volts/cycle.

To avoid degrading the noise performance of the system by the relatively low gain of phase comparator 2, once a small phase error has been achieved an internal switch disconnects phase comparator 2, leaving only phase comparator 1 connected. Thus the low noise properties of phase comparator 1 are obtained once phase-lock has been achieved.

February 1987

645

Signetics RF Communications
CMOS frequency synthesizer

Preliminary specification
TDD1742T

FUNCTIONAL DESCRIPTION (continued) Phase comparator 1 (see Fig. 3) Phase comparator 1 is comprised of a linear ramp generator and a sample and hold circuit.

BRA
I I

i Voo3

'+-i
__ .., S2 :

I

RAMP/
HOLD/ -- .;. 1 i

RESET/

1 --

LOGIC

,

R

BRC
I I

~-~----------.......-~ EOR I

~--------------,

r---1I

I I

I

S3

PC1

VF1

t

ONE-SHOT OSCILLATOR

Fig. 3 Simplified block diagram of phase comparator 1.

7Z81436.1

A negative-going transition at the VMUX input causes the hold capacitor CA to be discharged via switch 51 and constant current source I1. A positive-going transition at the VMUX input causes the hold capacitor CA to be charged via switch 52 and constant current source 12, which produces a linear ramp. A negative-going transition at the R input terminates the linear ramp. Capacitor CA holds the voltage that the ramp has attained, and is buffered by the voltage follower VF1. After the output of VF1 is stable (2 �s), the sample switch S3 is closed for approximately 1 �s by the one-shot oscillator. This enables the capacitor Cc to charge to the voltage level of VF1 and in turn buffered by voltage follower VF2 made available at output PC1. The construction and small duty cycle of the sample switch S3 provides a low hold step, resulting in a minimum side-band level. If the linear ramp terminates before a negative-going transition at the R input is present, an end of ramp (EOR) signal is produced, generating in turn an out-of-lock (OL) signal. OL enables phase comparator 2 via the out-of-lock detector.
These actions are illustrated in the waveforms of Fig. 4 and Fig. 5.
The gain of phase comparator 1 as measured at PC1 is given by:
. 446 IBRA
PCgam~---
FR
Where:
IBRA is in �A FR is the phase comparator reference frequency in kHz

February 1987

646

Signetics RF Communications
CMOS frequency synthesizer
R

Preliminary specification
TDD1742T

S3 ~------- OFF

EOR

7Z81437

Fig. 4 Waveforms of phase comparator 1; in-lock condition.

R - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~00

S3 EOR

.~-------'-- --- --- - - - - - - - - -- -- ---- -- Vss
ON ~--,~-----
~-----OFF

OL 1Z81438
Fig. 5 Waveforms of phase comparator 1; out-of-lock condition.
When VMUX leads R the output signal at pin 2 (PC1) is proportional to the phase difference (in-lock condition) or HIGH (out-of-lock condition). When R leads VMUX the output signal at pin 2 (PC1) remains LOW.

February 1987

Fig. 6 Phase characteristic of output PC1. 647

Signetics RF Communications
CMOS frequency synthesizer

Preliminary specification
TDD1742T

FUNCTIONAL DESCRIPTION (continued) Phase comparator 2 (see Fig. 7)

PHASE COMPARATOR 2

D

a

T
R Ci

LOW if phase comparator 1 operates

Voos
l

a

R a

LOW in locked

PC2

state

R

EOR

to out-of-lock circuitry

Fig. 7 Simplified block diagram of phase comparator 2.

7ZIH440

The digital phase comparator (PC2) has three stable states: � Reset � VMux leads R � R leads VMux
Table 1 Phase comparator 2: stable states and corresponding output levels

state
reset VMux leads R RleadsVMux

VMUX leads R
0 1 0

R leads VMux
0 0 1

Transition from one state to another takes place on command of either an active VMux-edge or an active R-edge as shown in Fig. 8.

February 1987

-_-_-_-o- o_-_-_- active A-edge (negative going)

active A-edge (negative going)

active VMux-edge (negative going)

active VMux-edge (negative going)

Fig. 8 Transition of state; phase comparator 2.

7Z81441

648

Signetics RF Communications
CMOS frequency synthesizer

Preliminary specification
TDD1742T

The output of phase comparator 2 produces positive or negative going pulses with variable width,

dependent on the phase relationship of Rand VMUX�

The average output voltage is a linear function of the phase difference. Output at pin 3 (PC2) remains

in the high impedance OFF-state in the region in which phase comparator 1 operates

I
aPvCe2rage

_/

output

voltage

7Z81442

Fig. 9 Phase characteristic of output PC2.
To reach the reset state of phase comparator 2 it is necessary to apply: � 2VMux + R*
or � 2R + VMux Thus to achieve the R leads VMUX state 2R must be applied; to achieve the VMUX 1 leads R state 2VMUX must be applied.
Out-of-lock function
There are several situations when the system goes from the locked to the out-of-lock state (OL output goes HIGH):
� VMUX leads R, however out of the range of phase comparator 1 � R leads VMuX � A-pulse is missing � VMux-pulse is missing In the first three situations the locked state can be reset by applying two successive cycles within the range of phase comparator 1. In the fourth situation the locked state can be reset by applying a VMUX pulse followed by two successive cycles within the range of phase comparator 1.
Phase modulator (see Fig. 10)
The linear phase modulator applies a voltage controlled delay to the signal from the programmable divider to the phase comparator input. The gain of the phase modulator is adjustable via an external bias resistor (BRB) which is connected between pin 26 and ground. The time delay introduced into the V path to the phase modulator is:
o9 9 ns/volt of input applied to pin 24 (MOD)
IBRB When a positive-going transition appears at the V-input, the D type flip-flop produces a HIGH V' level and causes capacitor Cs to produce a positive-going ramp via switch 51 and constant current source I1 starting at the V55 potential. When the ramp has reached a value equal to the modulation input voltage (at MOD), the comparator resets the D type flip-flop, which terminates the V pulse. Cs now discharges to V55 via switch 51 and constant current source 12 and the circuit returns to the start position. Because the trailing edge of the V' pulse is the active edge for the phase comparators, a linear phase modulation is achieved. The associated waveforms are shown in Fig. 11. The phase modulator can be switched OFF, via the programming logic, to avoid superfluous dissipation. To achieve, this the M signal must be programmed to logic 0. The V pulse will then be connected via switch 52 to VMUX�
* This means apply two successive active VMUX edges followed by one active R edge.

February 1987

649

Signetics RF Communications
CMOS frequency synthesizer

Preliminary specification
TDD1742T

FUNCTIONAL DESCRIPTION (continued)

M (from program control)
I I

I

I

~-----,

I

I

I

I

v -

-

1

-

-

+

-

logic - ' -1- -

-I

D T

Q
R a

V'

7Z81443

----"'\ \ I
ICB

VDD3
1;-1
I I
t--jS1 I 2 I I I I I I

I

I

I

I

BRC MOD

BRB

Fig. 10 Simplified block diagram of the phase modulator.

v
- - - - - - - - - - - - - VDD3

V' =VMUX
A= reset _n.______n.____
1Z81444
Fig. 11 Phase modulator waveforms; M = 1.

February 1987

650

Signetics RF Communications
CMOS frequency synthesizer

Preliminary specification
TDD1742T

Program control
A multiplexed or bus structured sequence allows the TDD1742T to be interfaced to a microcontroller or a PROM. The device is fully programmable in ter\ns of:
� 6 bits to define the reference divider ratio � 21 bits to define the main divider ratio � 1 bit to switch the modulator � 4 bits to determine the test status
Thus the TDD1742T is programmed with a total of 32 bits which are organized as eight 4-bit words. The address bus is 3 bits wide and the data bus is 4 bits wide. Both buses are TTL compatible. The data words are described in detail in Tables 3 to 7.
Microcontroller mode
If pin 25 (MEMEN) is LOW at general reset, the device is set to the micro-controller mode. In this mode a 7-bit word, comprised of 3 address bits (ABO to AB2) and 4 data bits (DBO to DB3), may be strobed into the TDD1742T when the program enable pins PE1 and PE2 are set to opposite state (EXCLUSIVE -OR condition; see Fig. 12 and Table 2). One frame of 8 words is necessary to completely program the TDD1742T. Incoming data is not clocked into the internal counter latches until after the receipt of data corresponding to address 111. Upon subsequent reprogramming it is not necessary to change all eight words but a reprogramming sequence must always finish with the data corresponding to address 111.

A80-A83 (1)
080-083

_____ PE1, PE2

(EXCLUSIVE-OR)

,,

1Z81445

(1) Address and data valid. (2) Address and data not valid.

Fig. 12 Waveforms for program enable function; microcontroller mode.

Table 2 Truth table for program enable function; microcontroller mode

PE1 PE2 load

0

0

NO

1

0

YES

0

1

YES

1

1

NO

February 1987

651

Signetics RF Communications
CMOS frequency synthesizer

Preliminary specification
TDD1742T

Program control (continued)
Memory mode (PROM) If pin 25 (MEMEN) is HIGH at general reset, TDD1742T is set to the memory mode and a programming cycle is initiated. Subsequent reprogramming is performed by applying a pulse to program enable PE1 (pin 23) or PE2 (pin 22). If PE1 is LOW, programming will occur on the LOW-to-HIGH transition of PE2. If PE1 is HIGH, programming will occur on the HIGH-to-LOW transition of PE2. PE1 and PE2 are interchangeable. Reprogramming will also occur by applying a pulse to RESET (pin 11).
At the start of a programming sequence pin 25 goes LOW and may be used to apply power to the memory via an external driver. After a settling time the address bus outputs 000 followed by the remaining seven addresses. During the second half of each address period data, from the memory is latched into the TDD1742T so that the access time of the PROM is not critical.
Note The program clock is derived from the reference divider chain and its frequency equals fosc/4Ro.
After the full 32 bits have been read the address returns to address 000 before going 3-state. This step transfers data from the internal data latches to the appropriate divider latches. Pin 25 now returns to a high impedance state and power is removed from the memory. Fig. 13 shows the timing for a reset initiated programming sequence; the timing is similar for program enable initiated sequence.

PROGRAM CLOCK (2)
RESET

l: : : : : : : : : addressbus outputs ---------------1~---~

Lr---

DATA VALID (3)

~ ~ ~ ~ ~ ~ �~ ~ ~ 1Z81446

(1) Delay time for PROM settling. (2) The program clock is derived from the reference divider chain. (3) Data is valid during the shaded period.
Fig. 13 Timing diagram for TDD1742T PROM control.

February 1987

652

Signetics RF Communications
CMOS frequency synthesizer

Preliminary specification
TDD1742T

Data memory maps Table 3 Bit programming of the eight 4-bit words

AB2 0 0 0 0 1 1 1 1

address AB1 0 0 1 1 0 0 1 1

ABO 0 1 0 1 0 1 0 1

DB3
no3 RoO n13 Ro1 n23 M R21

data

DB2

DB1

I see Table 4

no2

no1

no6

no5

n12

n 11

n16

n15

n22

n21

n26

n25

R20

R11

DBO I
noO no4 n10 n14 n20 n24 R10

In Table 3 no. n1 and n2 comprises the main programmable divider. noO is the LSB of no, no6 the MSB and so forth. If M is 1 the modular is ON.

Table 4 Memory map for address 000

DB3

DB2

DB1

DBO

0

0

x x

0

1

0

0

all other combinations

program clock to output CLK
yes no not defined

mode
idle idle not defined

Where X =don't care. For optimum performance (minimum crosstalk) 0100 should be programmed into address 000.

February 1987

653

Signetics RF Communications
CMOS frequency synthesizer

Preliminary specification
TDD1742T

Memory maps (continued) Table 5 Reference divider control; part 1

Ro1

RoO

division ratio

0

0

12

0

1

13

1

0

14

1

1

15

In Table 5: RoO and Ro1 control the+ 12/13/14/15 portion of the reference divider.

Table 6 Reference divider control; part 2

R11

R10

division ratio

0

0

9

0

1

5

1

0

6

1

1

7

In Table 6: R10 and R11 control the+ 5/6/7/9 portion of the reference divider.

Table 7 Reference divider control; part 3

R21

R20

division ratio

0

0

1

0

1

2

1

0

4

1

1

B

In Table 7: R20 and R21 control the+ 1/2/4/B portion of the reference divider.

Current biassing Current biassing is provided by 3 external bias resistors A, Band C.
Bias Resistor A: is connected between pin 28 (BRA) and ground. The value of the resistor must be such that I BRA= 20 �A, which acts as gain control for analogue phase comparator 1. Bias Resistor B: is connected between pin 26 (BRB) and ground. The value of the resistor must be such that IBRB = 3 to 25 �A, which acts as gain control for the phase modulator. Bias Resistor C: is connected between pin 27 (BRC) and ground. The value of the resistor must be such that IBRC = 5 to 30 �A, which provides biassing for the remainder of the analogue circuitry.

February 1987

654

Signetics RF Communications
CMOS frequency synthesizer

Preliminary specification
TDD1742T

RATINGS

Limiting values in accordance with the Absolute Maximum System (IEC 134)

Supply voltage ranges pin 14 pin 8 pin 1
Voltage on any input
Relative supply voltage
Relative supply voltage
D.C. current into any input or output

Voo1 Voo2 Voo3 V1
Voo2-Voo1
Voo3-Voo1 �1

-0,5 to+ 15 v -0,5 to+ 15 v -0,5 to+ 15 v

-0,5 to v 001 + 0,5 v

max.

0,5 v

max.

0,5 v

max.

10 mA

Power dissipation per package
for Tamb =0 to + 85 oc
Power dissipation per output
for Tamb = 0 to + 85 �c
Storage temperature range
Operating ambient temperature range

Ptot
Po Tstg Tamb

max.

400 mW

max.

100 mW -65 to 150 oc
-40 to 85 oc

February 1987

655

Signetics RF Communications
CMOS frequency synthesizer

Preliminary specification
TDD1742T

D.C. CHARACTERISTICS
Voo1 = Voo3 =7,4 V; Voo2 = 5 V; Vss =0 V; Tamb = 25 �c unless otherwise specified; for
definitions see note 1.

parameter

symbol min.

typ. max.

unit

Supply
Supply voltage pin 14 pin 8 pin 1
Supply current pin 14 (phase modulator OFF) pin 8 pin 1 (phase modulator OFF}
Input leakage current (notes 2 and 3) logic inputs, MOD
Output leakage current (notes 2 and 3) at% Voo PC2 high impedance OFF state MEMEN high impedance state
1/0 current ABO to AB2 high impedance state
Logic input voltage LOW CMOS inputs; CMOS I/Os TTL inputs; TTL I/Os
Logic input voltage HIGH CMOS inputs; CMOS I/Os TTL inputs; TTL I/Os
Logic output voltage LOW (note 2) at llo\ <1 �A
Logic output voltage HIGH (note 2) at \lo\< 1 �A

Voo1 Voo2 Voo3
1001 1002 1003
� iu
�ILO � ILQ
11;0
V1L V1L
V1H V1H
Vol
VoH

7

-

4,5

-

7

-

-

-

-

-

-

-

-

-

-

-

-

-

5

-

-

-

-

-

0.7Voo1 -

2

-

-

-

Voo1-5o -

10

v

5

v

10

v

1,5

mA

100

�A

1,5

mA

300

nA

50

nA

1,6

�A

30

�A

o,3Voo1

v

0,8

v

-

v

-

v

50

mV

-

mV

February 1987

656

Signetics RF Communications
CMOS frequency synthesizer

Preliminary specification
TDD1742T

parameter

symbol

Logic output voltage LOW (note 2) ~atloL=4mA PC2 at IOL = 1,5 mA CLK; OL at loL = 1 mA XTAL at loL = 3 mA FB at loL = 1 mA ABO; AB1; AB2 at loL = 0,2 mA
Logic output voltage HIGH (notes 2 and 3) PC2 at -loH = 1,5 mA CLK; OL at -loH = 1 mA XTAL at -foH = 3 mA FB at -foH = 1 mA ABO; AB 1 at 'aH = 0,2 mA AB2 at IOH = 0,8 mA
Output PC1 sink current (notes 2, 3 and Fig. 15) source current (notes 2, 3 and Fig. 16)
Internaf resistance of phase comparator 1 (notes 2 and 3)
locked state !output swingl < 200 mV
specified output range:
0,5 Voo -0,5 v to 0,5 v 00 +0,5 v

Vol Vol Vol Vol VoL Vol
VoH VoH VoH VoH VoH VoH
lo -10
Ri

min.
-
-
-
Voo1-0,5 Voo1-0,5 Voo1-1 Voo2-1 2,4 2,4
1 1
-

typ, max. unit

-

1

v

-

0,5 v

-

0,5 v

-

0,5 v

-

0,5 v

-

0,4 v

--v

-

-

v

-- v

--v

-- v

--v

-

-

mA

-

-

mA

2,0 -

.n

February 1987

657

Signetics RF Communications
CMOS frequency synthesizer

Preliminary specification
TDD1742T

A.C. CHARACTERISTICS
Adynamic specification is given for the circuit, built-up with external components as shown in Fig. 14, under the following conditions; for definitions see note 1; Voo = 7,4 � 0,4 V; Tamb = 25 �c; input transition times.;;; 40 ns; CA= Cs= Cc= 10 nF; RA chosen so that I RA= 20 �A� 1 �A; Rs chosen so that I RB = 3 to 25 �A; Re chosen so that IRC= 5 to 30 �A; unless otherwise specified.

parameter

symbol

min. typ. max. unit

Main programmable divider (DIV(M); pin 7)

input frequency all divider ratios

(square wave input)

folV(M)

8,5

-

-

Reference divider input frequency all divider ratios (square wave input)
Oscillator frequency (OSC; pin 13)

folV(R)

9

tosc

9

-

-

12

-

Input capacitance

DIV(M);OSC

C1

-

-

3

DBO to DB3; PE1; PE2; ABO to AB2

C1

-

-

5

Propagation delay (see Fig. 17)

Feedback output to external prescaler DIV (M) --> FB at CL= 10 pF HIGH to LOW* LOWtoHIGH*

tPHL tPLH

-

35

70

-

35

70

Average power supply current.(notes 3 and 4)

in-lock state

1001

-

2

-

1002

-

0,15 -

1003

-

0,45 -

MHz
MHz MHz
pF pF
ns ns in A mA mA

February 1987

658

Signetics RF Communications
CMOS frequency synthesizer

Preliminary specification
TDD1742T

TDD1742T

28
BRA

26 BRB

27
BRC

Cc Re

7Z8)'447
Fig. 14 Test circuit for measuring a.c. characteristics.
Notes to the characteristics
1. Definitions: RA =external biassing resistor between pins BRA and Vss� Rs =external biassing resistor between pins BRB and Vss� Re =external biassing resistor between pins BRC and Vss� CA =decoupling capacitor between pins BRA and Voo� Cs =decoupling capacitor between pins BRB and VoD� Cc =decoupling capacitor between pins BRC and Voo� CMOS logic inputs: RESET, OSC. CMOS logic outputs: PC2, CLK, OL, XTAL. CMOS logic 1/0: MEMEN. TTL logic inputs: DBO to DB3, PE2, PE1. TTL logic output: FB. TTL logic 1/0: ABO to AB2. Analogue inputs: DIV(M), MOD. Analogue output: PC1. Analogue biassing pins: BRA, BRB, BRC.
2. All logic inputs at Vss or Voo� 3. RA connected; its value chosen such that IBRA= 20 �A.
Rs connected; its value chosen such that ls RB= 20 �A Re connected; its value chosen such that IBRC = 20 �A.
4. Average power supply current measured at: fosc = 5 MHz, external clock, divider ratio 420; fo1V(M) = 2 MHz, divider ratio 168.

February 1987

659

Signetics RF Communications
CMOS frequency synthesizer

Preliminary specification
TDD1742T

input forced LOW
by 2 preceding A-pulses ----.------!
BRC

-lo PC1
internal voltage follower (VF2; see also Fig. 3)

Voo
7Z81448

Fig. 15 Equivalent circuit for output PC1 sink current.

input forced HIGH by 2 preceding VMUX -pulses
BRC

Voo

7Z81449

internal voltage follower (VF2; see also Fig. 3)

-lo PC1

Fig. 16 Equivalent circuit for output PC1 source current.

February 1987

DIV(M) input 30%

30%

FB output

50%

50%

1Z81450
Fig. 17 Waveforms showing propagation delay; DIV (M)-+ FB.

660

Signetics RF Communications
CMOS frequency synthesizer

Preliminary specification
TDD1742T

APPLICATION INFORMATION

Fig. 18 shows a typical application circuit using the TDD1742T in the memory mode with the following design parameters:

Frequency range

150 to 155 MHz

VCO sensitivity

1 MHz/V

Reference frequency

12,5 kHz

Prescaler

+ 80/81

Reference crystal frequency

5,25 MHz

Reference divider chain

+15;+7;+1

Total division ratio

12000 to 12400

Loop bandwidth

300 Hz

February 1987

661

~

2
~

jg

APPLICATION INFORMATION (continued)

....

program enable

Vee1 (+5V)

inputs

+ 7,4 v

+5V

,---A--.

ti::

!100
�F I TnF
5-65
pf

+7,4 v +5V
I 10
kfl Be559

fg.

.. s:: "' ()

:::>

"0 '�

-0en
I .....

:,0,
0 0
3

CD
I .c0 CD :J (')

3c:
:e::>r
..~-
0 :::>

I '<

(/)

1 nF
from veo -+-J

vee2 Q

PE2

Voo2 '!'OSe XTAL MEMEN

Vee

0

13

12

25

16

'<
:J
.:.:-:+r
CD

19 ABO AO 5

13

eE1

(N/).

rnf + 7,4 v

VEE RESEL.J 11
+ 7,4 v

TDD1742T

20 AB1 21 AB2 18 DBO 17 DB1

A1 6 A2 7 01 12 02 11

1024-BIT PROM 82S129
1256 x 4)

4 A3 3 A4 2 AS 1 A6

}""'""" selection outputs

.C..D..

16 DB2

03 10

A7 15

8l
N

100

100

kfl

phase

nF

~odulator ---11-----+----+-+--I 242 input

3

10

28

26

27

15 DB3 04 9

14

eE2

Pe1

Pe2

+7,4 v

OL

BRA

BRB

BRe

Vss

270

270

270

VEE

7Z81451

.. kO

kfl

kfl

10

k(l

10

100

kfl,

nF

470 nf

transmitter mute

I~SF
toVeO
Fig. 18 Typical application circuit using the TDD1742T in memory mode.

"U

-I ~

. 0
.0.....

~r 5�
-"<'

-...J
~

al
0

I'\)

3i

-I

fil "0 '�

:::>

Slgnetlcs RF Communications
Radio tuning PLL frequency synthesizer

Preliminary specification
TSA6057/T

GENERAL DESCRIPTION The TSA6057/6057T is a bipolar single chip frequency synthesizer manufactured in SUBI LO-N technology (components laterally separated by oxide). It performs all the tuning functions of a PLL radio tuning system. The IC is designed for application in all types of radio receivers.
Features
� On-chip AM and FM prescalers with high input sensitivity � On-chip high performance one input (two output) tuning voltage amplifier for the AM and
FM loop filters � On-chip 2-level current amplifier (charge pump) to adjust the loop gain � Only one reference oscillator (4 MHz) for both AM and FM � High speed tuning due to a powerful digital memory phase detector � 40 kHz output reference frequency for co-operation with the FM/IF system and microcomputer-
based tuning interface IC (TEA6100) � Oscillator frequency ranges of: 512 kHz to 30 MHz and 30 MHz to 150 MHz � Three selectable reference frequencies of 1 kHz, 10 kHz or 25 kHz for both tuning ranges � Serial 2-wire 12 C-bus interface to a microcomputer and one programmable address input � Software controlled bandswitch output
QUICK REFERENCE DATA

parameter

conditions

symbol

min. typ. max. unit

Supply voltage pin 3 pin 16
Supply current pin 3 pin 16
Max. input frequency on AM1
Min. input frequency on AM1 Max. input frequency on FM1 Min. input frequency on FM 1 Input voltage on AM1
(RMS value)
Input voltage on FM 1 (RMS value)
Total power dissipation
Operating ambient temperature range

no outputs loaded
ViFM = 0 V ViAM = OV

Vcc1 = V3-4 4.5 Vcc2 = V15_4 Vcc1

13

12

I 15

0.7

fiAM

30

fiAM

-

fiFM

150

fiFM

-

ViAM(rms)

30

ViFM(rms)

20

Ptot

-

Tamb

-30

5.0 5.5 v 8.5 12 v

20 28 mA 1.0 1.3 mA

-

-

MHz

-

0.512 MHz

-

-

MHz

-

30 MHz

- 500 mV

-

300 mV

0.14 -

w

-

+ 85 oc

PACKAGE OUTLINES
TSA6057: 16-lead DI L; plastic (SOT38). TSA6057T: 16-lead minipack; plastic (S016L; SOT162A).

August 1988

663

)>
c:
"� '
m
AMVCO input
prescaler decoupling
FMVCO input

"",.''
Vcc1
L
VEE

,.,;, f,
data input

serial

11

clock input

address select 112 input

I POWER SUPPLY

40 kHz reference output

MULTIPLEXER

l____......I PRESCALEA

13-BIT PROGRAMMABLE

I I -;- 3 : 4

~

DIVIDER

DIGITAL PHASE DETECTOR

3- 1 MULTIPLEXER

REFERENCE COUNTER

AEFERENCE OSCILLATOR

reference oscillator input
reference oscillator output

PROGRAMMABLE CURRENT AMPLIFIER

16 Vcc2

~ I

....._O l

I I 1 "'

AM output for external loop filter

I14 tuning voltage amplifier input

> I

�-J;;1

I '~ I

FM output
for external loop filter

~

maJJ. 5�

::>
"0CD'�
:"-nn'

.c.....
::I

() 0
3 3

c:o:I
-u
r r

c:
:e:>r 5el.�
::>
"'

............

CD

..0
c

CD

::I

(")

'<

CJ)
-'<
::I
::r
CD
CJ)
;:::i"

C...D..

TSA6057 TSA6057T
Fig.1 Block diagram.

BAND SWITCH

bandswitch output

7Z97827.3

e-nI

"U
!B..
~r

)> 5'
m ~

j 0
01

i -...J
~

::>

Signetics RF Communications
Radio tuning PLL frequency synthesizer

Preliminary specification
TSA6057/T

XTAL1 XTAL2
Vcc1 VEE FM1 DEC AM1
BS

TSA6057 TSA6057T

Vcc2 AMo LOOP 1 FMo AS

1Z91825.2

SDA
f ref

Fig.2 Pinning diagram.

PINNING 1 XTAL1 2 XTAL2 3 Vcc1 4 VEE 5 FM1 6 DEC 7 AM1 8 BS 9 f ref
10 SDA 11 SCL 12 AS 13 FMo 14 LOOP1 15 AMo 16 Vcc2

reference osci 1lator output reference oscillator input positive supply voltage ground FM VCO input prescaler decoupling AM VCO input bandswitch output 40 kHz reference output serial data input \ serial clock input (C-bus address select input FM output for external loop filter tuning voltage amplifier input AM output for external loop filter positive supply voltage

FUNCTIONAL DESCRIPTION
The TSA6057/6057T contains the following parts and facilities:
� Separate input amplifiers for the AM and FM VCO-signals. � A prescaler with the divisors 3:4 on AM and 15:16 on FM, a multiplexer to select AM or FM and
a 4-bit programmable swallow counter. � A 13-bit programmable counter. � A digital memory phase detector. � A reference frequency channel comprised of a 4 MHz crystal oscillator followed by a reference
counter. The reference frequency can be 1 kHz, 10 kHz or 25 kHz and is applied to the digital memory phase detector. The reference counter also outputs a 40 kHz reference frequency to pin 9 for co-operation with the FM/IF system and microcomputer-based tuning interfaci. IC (TEA6100). � A programmable current amplifier (charge pump) which consists of a 5 �A and a 450 �A current source. This allows adjustment of loop gain, thus providing high current-high speed tuning and low current-stable tuning. � A one input - two output tuning voltage amplifier. One output is connected to the external AM loop filter and the other output to the external FM loop filter. Under software control, the AM output is switched to a high impedance state by the FM/AM switch in the FM position and the FM output is switched to a high impedance state by the AM/FM switch in the AM position. The outputs can deliver a tuning voltage of up to 10.5 V. � An 12 C-bus interface with data latches and control logic. The 12 C-bus is intended for communication between microcontrollers and different ICs or modules. Detailed information on the 12 C-bus specification is available on request. � A software-controlled bandswitch output.

August 1988

665

Signetics RF Communications
Radio tuning PLL frequency synthesizer

Preliminary specification
TSA6057/T

FUNCTIONAL DESCRIPTION (continued)
Controls
The TSA6057 /6057T is controlled via the 2-wire 12C-bus. For programming there is one module address, a logic 0 R/W bit, a subaddress byte and four data bytes. The subaddress determines which one of the four data bytes is transmitted first. The module address contains a programmable address bit (D 1) which with address select input AS (pin 12) makes it possible to operate two TSA6057s in one system.
The auto increment facility of the I 2C-bus allows programming of the TSA6057 /6057T within one transmission (address+ subaddress + 4 data bytes).
� The TSA6057/6057T can also be partially programmed. Transmission must then be ended by a stop condition.
The bit organization of the 4 data bytes is shown in Fig.3 and are described in sections (a) to (f).
(a) The bits SO to S16 (DBO: 07-01; DB 1: 07-00; DB2: 01-DO) together with bit FM/AM (DB2: 05) are used to set the divisor of the input frequency at inputs AM1 (pin 7) or FM1 (pin 5). If the system is in lock the following is valid:

FM/AM

input frequency (fil

input

0

(SOx 2�+S1x2 1 ����� + S13 x 213 + S14x 2 14 ) x fref

AM1

1

(SO x 2� + S1 x 21 ����� + S15 x 215 + S16 x 216) x fref

FM1

Where

The minimum dividing ratio for AM mode is 26 = 64
The minimum dividing ratio for FM mode is 28 =256

(b) The bit CP is used to control the charge pump current (DBO: DO).

CP

current

0

low

1

high

(c) The bits REF 1 and REF2 are used to set the reference frequency applied to the phase detector (DB2: D7-D6).

REF1

REF2

frequency (kHz)

0

0

1

0

1

10

1

0

25

1

1

none

(d) The bit FM/AM OPAMP controls the switch AM/FM; FM/AM in the tuning voltage amplifier output circuitry (DB2: 04).

FM/AM OPAMP switch FM/AM

switch AM/FM

1

closed

open

0

open

closed

August 1988

666

Signetics RF Communications
Radio tuning PLL frequency synthesizer

Preliminary specification
TSA6057/T

(e) The bit BS controls the open collector bandswitch output (OB2: 02).

BS

bandswitch output

1

sink current

0

floating

(f) The data byte OB3 must be set to 0 ...... 0. It is also used for test purposes.

MODULE

s ADDRESS O A SUBADDRESS A DATA BYTE 0 A DATA BYTE 1 A DATA BYTE 2 A DATA BYTE 3 A P

BYTE

BYTE

A7

AO

D7

DO D7

DO D7

DO D7

DO

MSB MODULE ADDRESS
A7

0

0

0

LSB

0/1

0

AO

SUBADDRESS

0

0

0

0

0

0

0/1

0/1

DATA BYTE 0 ( DBO)

S6

S5

S4

S3

S2

Sl

D7

so

CP

DO

DATA BYTE 1 (DB1)

S14

S13

S12

S11

S10

S9

D7

SB

57

DO

DATA BYTE 2 ( DB2)

REF1

REF2

FM/AM FM/AM OPAMP

NOT USED

BS

D7

S16

515

DO

DATA BYTE 3 ( DB3)

Tl

T2

NOT

NOT

NOT

NOT

NOT

T3

USED USED USED USED USED

D7

DO

Examples using auto-increment facility

Isl ADDRESS IAisuBADDREsso2 iAI

082

IAI

DB3

Hpl

Isl ADDRESS IAI SUBADDRESS 00 IAI

DBO

IAI

DB1

IAH

isl ADDRESS IAISUBADDRESS031AI

DB3

H

DBO

H

DB1

IAI

DB2

IAI p I

7Z97826.2

August 1988

Fig.3 Bit organization. 667

Signetics RF Communications
Radio tuning PLL frequency synthesizer

Preliminary specification
TSA6057/T

RATINGS Limiting values in accordance with the Absolute Maximum System (I EC 134)

parameter /----
Supply voltage (pin 3)
Supply voltage (pin 16)
Total power dissipation Operating ambient temperature Storage temperature range

symbol

min.

max.

unit

Vcc1 = V3.4

-0.3

5.5

v

Vcc2 = v16-4

Vcc1

12.5

v

Ptot

-

0.85

w

Tamb

-30

+85

oc

Tstg

-65

+ 150

oc

CHARACTERISTICS
Vcc1 = 5 V; Vcc2 = 8.5 V; Tamb = 25 �c; unless otherwise specified

parameter
Supply voltage (pin 3) Supply voltage (pin 16) Supply current
pin 3 pin 16 12 C-bus inputs (SDA;SCL) Input voltage HIGH Input voltage LOW Input current HIGH Input current LOW SDA output Output voltage LOW AS input Input voltage HIGH Input voltage LOW Input current HIGH Input current LOW RF input (AM; FM) Max. input frequency on AM I Min. input frequency on AM1 Max. input frequency on FM1 Min. input frequency on FM1 Input voltage on AM1 (RMS value) Input impedance AM1 resistance capacitance

conditions

symbol

no outputs loaded

Vcc1 Vcc2
1cc1 1cc2

min. typ. max. unit

4.5

5.0 5.5 v

v Vcc1 8.5 12

12

20 28 mA

0.7

1.0 1.3 mA

open collector loL = 3.0 mA

V1H V1L l1H l1L
Vol

3.0 -

-0.3 -

--

-

-

-

-

5.0 v 1.5 v
10 �A 10 �A
0.4 v

V1H

3.0

-

5.0 v

V1L

-0.3 - 1.0 v

l1H

-

- 10 �A

l1L

-

- 10 �A

ViFM = OV measured in Fig.4

fiAM

30

fiAM

-

fiFM

150

fiFM

-

ViAM(rms) 30

RAM

-

CAM

-

--

MHz

- 0.512 MHz

- - MHz

- 30 MHz

- 500 mV

5.9 �- kn

2 -

pF

August 1988

668

Signetics RF Communications
Radio tuning PLL frequency synthesizer

Preliminary specification
TSA6057/T

parameter

conditions

RF input (continued)
Input voltage on FM1 (RMS value)
Input impedance FM1 resistance capacitance
Oscillator (XTAL 1; XTAL2)
Crystal resonance resistance (4 MHz)
Programmable charge pump Output current to loop filter
bit CP = logic 0 bit CP = logic 1
Ripple rejection
20 log t:Ncc1!tNo
20 log t:N cc2!t:N 0
Bandswitch output (pin 8)
Output voltage HIGH
Output voltage LOW
Output leakage current
Reference frequency output (pin 9)
Output frequency
Output voltage HIGH
Output voltage LOW
Tuning voltage amplifier outputs AM output (pin 15)
max. output voltage
min. output voltage max. output source current max. output sink current
FM output (pin 13) max. output voltage
min. output voltage max. output source current max. output sink current
Impedance of switched off output
Input bias current (absolute value)

ViAM = OV measured in Fig.4
see Fig.5
fripple = 100 Hz
loL = 3 mA VoH = 12 V 4 MHz crystal Isource= 5 �A
Isource= 0.5 mA lsink = 1 mA
.
Isource= 0.5 mA lsink = 1 mA

symbol

min. typ. max. unit

ViFM(rms) 20

RfM

-

Cf M

-

- 300 mV

3.6 -

kn

2 -

pF

RxTAL

-

- 150 n

lchp lchp
RR RR
VoH Vol ILQ

3

5 7

�A

400 500 600 �A

40

50 -

dB

40

50 -

dB

�-

- 12 v

-

- 0.8 v

-

- 10 �A

fref VoH Vol

-

40 -

kHz

1.2

1.4 1.7 v

-

0.1 0.2 v

Vo( max)
Vo( min) I source I sink
Vo( max) Vo(min) I source I sink

Vcc2 -

-1.5

-

-

0.5

-

1.0 -

Vcc2 -

-1.5

-

-

0.5 -

1.0 -

-v

0.8 v

-

mA

-

mA

-v

0.8 v

-

mA

-

mA

Zo(off)

5

--

Mn

I bias

-

1 5

nA

August 1988

669

Signetics RF Communications
Radio tuning PLL frequency synthesizer
SENSITIVITY MEASUREMENT

Preliminary specification
TSA6057fr

FM sinewave
generator

HYBRID JUNCTION
s-3dB

50!:!

AM sinewave
generator

HYBRID JUNCTION
-~-3dB

50!:!

Vcc1

3

4

50!:!

10 nF
10 nF
~

5
TSA6057 TSA6057T 6

10 nF

7Z97824.1

= 50 n coaxial Fig.4 Prescaler input sensitivity.
APPLICATION INFORMATION

August 1988

2

TSA6057

TSA6057T

7Z97823.1
Fig.5 Crystal connection (4 MHz).
670

Signetics RF Communications
Radio tuning PLL frequency synthesizer

Preliminary specification
TSA6057ff

CT 4MHz
~ ~HD 27 pF

XTAL 1 1

Vcc2 16

+ 12V

+

C2I47�F

XTAL2 2

AMo 15

R 1

+5V

Vcc1 3

47�F C1

LOOP 1 14

220nF C4

38 nF C6

AM tuning voltage output
FM tuning voltage output

FM VCO input
160!1

VEE 4

CFM 1nF

FM 1 5

RFM
Co EC DEC 6
10nF

FMo 13
TSA6057 TSA6057T
AS 12
SCL 11

10k!1
tt+5V J1 "'~mmm�"''"""'"' J1: A1=1 J2:A1=0 J2 l
t,,,,,,

� AM VCO input

CAM
I
22 nF

AM 1

SDA 10

bandswitch +-----..----BS-t 8

output

,..I .,

1okn::Rss
�'r'
I +5V

9 fret

40kHz reference output
7Z95911.2

August 1988

Fig.6 Application diagram
671

Slgnetlca RF Communications
1.3GHz bi-directional 12C bus controlled synthesizer

Preliminary specification
TSA5511

FEATURES
� Complete 1.3 GHz single chip system
� Low power 5 V, 35 mA � 12C-bus programming � In-lock flag � Varicap drive disable � Low radiation � Address selection for
Picture-In-Picture (PIP), DBS tuner � Analog-to-digital converter � 8 bus controlled ports (5 for TSA5511T), 4 open collector outputs (bi-directional) � Power-down flag
APPLICATIONS
� TV tuners � VCR Tuners
DESCRIPTION
The TSA5511 is a single chip PLL frequency synthesizer designed for TV tuning systems. Control data is entered via the 12C-bus; five serial bytes are required to address the device, select the oscillator frequency, programme the eight output ports and set the charge-pump current. Four of these ports can also be used as input ports (three general purpose 1/0 ports, one ADC). Digital information concerning those ports can be read out of the TSA5511 on the SDA line (one status byte) during a READ operation. A flag is set when the loop is 'in-lock' and is read during a READ operation. The device has one fixed 12C-bus address and 3 programmable addresses, programmed by applying a specific voltage on Port 3. The phase comparator operates at 7.8125 kHz when a 4 MHz crystal is used.
August 1991

~
lliiJ

QUICK REFERENCE DATA

SY,MBOL

PARAMETER

Vee

supply voltage

Ice

supply current

M

frequency range

v,

input voltage level

80 MHz to 150 MHz

150 MHz to 1 GHz

1 GHz to 1.3 GHz

fxTAL

crystal oscillator

lo

open-collector output current

lo

current-limited output current

Tamb

operating ambient temperature

range

Ts1g

storage temperature range (IC)

MIN.
-
64
12 9 40 3.2 10
-
-10
-40

TYP. 5 35
-
-
-
4
-
1
-
-

MAX. UNIT
-v

-

mA

1300 MHz

300 mV

300 mV

300 mV

4.48 MHz

-

mA

-

mA

80 oc

150 oc

ORDERING INFORMATION

EXTENDED TYPE
NUMBER
TSA5511 TSA5511T TSA5511AT

PACKAGE

PINS PIN POSITION
18 OIL
16 so 20 so

MATERIAL
plastic plastic plastic

CODE
SOT102 SOT109 SOT163

672

l
!
~

RFIN1 RFIN2
y~o Ol 02

I ~ ] +

PRESCALER

_

+B

OSCILLATOR 4MHz

I DIVIDER N = 512

I 7.8125 kHz

1 PROG1R5A-BMIMT ABILE tD1v DIVIDER
..;;

PD
~ '~'"'PUMP ~ l '"'

11

f REF I I ~~~~AEL

TOI ICP

�

1 COMPARATOR

"(.;'j
SCL
SDA

POWER DOWN DETECTOR
12 C-BUS TRANSCEIVER

r
IN-LOCK [ DETECTOR
j+-J

15-BIT LATCH DIVIDER RATIO
A

h

ADDRESS SELECTION

3-BIT ADC

TTL LEVEL COMPARATORS

8-BIT LATCH

j

PORT INFORMATION

TSA5511

I LO~IC
OS

LATCH 3 CONTROL DATA

VEE
--+t
~

GATE T1

PO P1 P2 P3 P4 PS P6 _P?
Fig.1 Block diagram.

MC0239

..:c ......
(.>

igi!-

G) :n

J:
,.N
C"

"l1 0
3
c 3

,,. .. 9..,:
uCD

"gj;i"�

:J
~
I\) (')
Cec n "
-0
0 :J
a

aCD. en
-'<
:J
';3"
CeNnD.
C..D,

-0

~

-enI
)>

3�
5�
~.,

01 al

.0.......1....

~
�g-

::i

Signetics RF Communications
1.3GHz bi-directional 12C bus controlled synthesizer

Preliminary specification
TSA5511

TSA5511

UD VEE RFIN2 RFIN1 Vee PO P1 P2 P3

Fig.2 Pin configuration (SOT102).

TSA5511T

UD VEE RFIN2 RFIN1 Vee n.c. P3

Fig.3 Pin configuration (SOT109).

UD

VEE

RFIN2

RFIN1

TSA5511AT

Vee PO

P1

P2

P3

PS

P4

MCD237
Fig.4 Pin configuration (SOT163).

PINNING
SYMBOL
PD 01 02 n.c. SDA SCL P7 n.c. P6 P5 P4 P3 P2 n.c. P1 PO Vee RF1N1 RF1N2 Vee UD

PIN OIL 18
1 2 3
4 5 6
7 8 9 10 11
12 13 14 15 16 17 18

PIN S016
1 2 3
4 5 6
7 8 9 10
11
12 13 14 15 16

PIN S020
1 2 3 4 5 6 7 8 9 10 11 12 13
14 15 16 17 18 19 20

DESCRIPTION
charge-pump output crystal oscillator input 1 crystal oscillator input 2 not connected serial data inpuVoutput serial clock input port outpuVinput (general purpose) not connected port outpuVinput for general purpose ADC port outpuVinput (general purpose) port outpuVinput (general purpose) port outpuVinput for address selection port output not connected port output port output voltage supply UHFNHF signal input 1 UHFNHF signal input 2 (decoupled) GND drive output

August 1991

674

Signetics RF Communications
1.3GHz bi-directional 12c bus controlled synthesizer

Preliminary specification
TSA5511

FUNCTIONAL DESCRIPTION
The TSA5511 is controlled via the two-wire 12C-bus. For programming, there is one module address (7 bits) and the R!W bit for selecting READ or WRITE mode.
WRITE mode : RiW = 0 (see Table 1)
After the address transmission (first byte), data bytes can be sent to the device. Four data bytes are needed to fully program the TSA5511. The bus transceiver has an

auto-increment facility which permits the programming of the TSA5511 within one single transmission (address+ 4 data bytes).
The TSA5511 can also be partially programmed on the condition that the first data byte following the address is byte 2 or byte 4. The meaning of the bits in the data bytes is given in Table 1. The first bit of the first data byte transmitted indicates whether frequency data (first bit = 0) or charge pump and port information (first bit= 1) will follow. Until an 12C-bus STOP condition is sent by

the controller, additional data bytes can be entered without the need to re-address the device. This allows a smooth frequency sweep for fine tuning or AFC purpose. At power-on the ports are set to the high impedance state.
The 7.8125 kHz reference frequency is obtained by dividing the output of the 4 MHz crystal oscillator by 512. Because the input of UHFNHF signal is first divided by 8 the step size is 62.5 kHz. A 3.2 MHz crystal can offer step sizes of 50 kHz.

Table 1 Write data format

MSB

Address

1

Programmable

0

divider

Programmable

N7

divider

Charge-pump

1

and test bits

Output ports

P7

control bits

LSB

1

0

0

0

MA1 MAO

0

N14 N13 N12 N11 N10 N9

NB

N6

N5

N4

N3

N2

N1

NO

CP

T1

TO

1

1

1

OS

P6

P5

P4

P3

P2* P1*

PO*

A byte 1 A byte 2 A byte 3 A byte 4 A byte 5

note * not valid for TSA5511T.

MA1, MAO
A

programmable address bits (see Table 4) acknowledge bit

N = N14 x 214 + N13 x 213 + ... + N1 x 21 +NO

CP

charge-pump current

CP= 0

50�A

CP = 1

220 �A

P3 to PO = 1 limited-current output is active

P7 to P4 = 1 open-collector output is active

P7 to PO = 0 output are in high impedance state
T1 = 1 P6 =f,.,, P7 =f01v

TO = 1

3-state charge-pump

OS= 1

operational amplifier output is switched off (varicap drive disable)

August 1991

675

Signetics RF Communications
1.3GHz bi-directional 12C bus controlled synthesizer

Preliminary specification
TSA5511

FUNCTIONAL DESCRIPTION (continued)
READ mode : RiW = 1 (see Table
2)
Data can be read out of the TSA5511 by setting the R/W bit to 1. After the slave address has been recognized, the TSA5511 generates an acknowledge pulse and the first data byte (status word) is transferred on the SDA line (MSB first). Data is valid on the SDA line during a high position of the SCL clock signal. A second data byte can be read out of the TSA5511 if the processor generates an acknowledge on the

SDA line. End of transmission will occur if no acknowledge from the processor occurs. The TSA5511 will then release the data line to allow the processor to generate a STOP condition. When ports P3 to P7 are used as inputs, they must be programmed in their high-impedance state. The POR flag (power-on-reset) is set to 1 when Vcc goes below 3 V and at power-on. It is reset when an end of data is detected by the TSA5511 (end of a READ sequence). Control of the loop is made possible with the in-lock flag FL which indicates (FL = 1) when the loop is

phase-locked. The bits 12, 11 and 10 represent the status of the 1/0 ports P7, P5 and P4 respectively. A logic O indicates a LOW level and a logic 1 a HIGH level (TTL levels). A built-in 5-level ADC is available on 1/0 port P6. This converter can be used to feed AFC information to the controller from the IF section of the television as illustrated in the typical application circuit in Fig. 5. The relationship between bits A2, A1 and AO and the input voltage on port P6 is given in Table 3.

Table 2 Read data format

Address Status byte

MSB
1 I
POR j

1 l l FL

0 l l 12

0 l l 11

0 j MA1 j MAO 10 j A2 j A1

LSB
1 l l AO

J A byte 1 - Jbyte 2

POR FL 12, 11, 10 A2,A1,AO

power-on-reset flag. (POR = 1 on power-on)
in-lock flag (FL= 1 when the loop is phase-locked)
digital information for 1/0 ports P7, P5 and P4 respectively
digital outputs of the 5-level ADC. Accuracy is 1/2 LSB (see Table 3)

MSB is transmitted first.

Address selection
The module address contains programmable address bits (MA1 and MAO) which together with the 1/0 port P3 offers the possibility of having several synthesizers (up to 3) in one system. The relationship between MA1 and MAO and the input voltage 1/0 port P3 is given in Table 4.

August 1991

676

Signetics RF Communications
1.3GHz bi-directional 12C bus controlled synthesizer

Preliminary specification
TSA5511

Table 3 A/D converter levels
Voltage applied on the port P6 0.6 Vee to 13.5 V 0.45 Vee to 0.6 Vee 0.3 Vee to 0.45 Vee 0.15 Vee to 0.3 Vee Oto0.15V

A2

A1

AO

1

0

0

0

1

1

0

1

0

0

0

1

0

0

0

Table 4 Address selection
MA1 0 0 1 1

MAO 0 1 0 1

0 to 0.1 Vee always valid 0.4 to 0.6 Vee 0.9 Vee to 13.5 V

Voltage applied on port P3

LIMITING VALUES In accordance with Absolute Maximum System (IEC 134)

Vee V1 V2 V4 Vs Vs-13 V1s V1a 16 14 Tstg Ti

SYMBOL

PARAMETER supply voltage charge-pump output voltage crystal (01) input voltage serial data inpuVoutput serial clock input P7 to P1 1/0 voltage prescaler input drive output voltage P7 to PO output current (open collector) SDA output current (open collector) storage temperature range (IC) maximum junction temperature

MIN. -0.3 -0.3 -0.3 -0.3 --0.3 -0.3 --0.3 -0.3 -1 -1 --40

MAX. 6 Vee Vee 6 6 +16 Vee Vee 15 5 +150 150

UNIT
v v v v v v v v
mA
mA
oc oc

THERMAL RESISTANCE

SYMBOL Rth i��

PARAMETER from junction to ambient in free air (DIL 18) from junction to ambient in free air (S016) from junction to ambient in free air (S020)

TYP.
-

MAX. 80 110 80

UNIT K/W K/W K/W

August 1991

677

Signetics RF Communications
1.3GHz bi-directional 12C bus controlled synthesizer

Preliminary specification
TSA5511

CHARACTERISTICS Vee= 5 V; Tamb = 25 �C; unless otherwise specified All pin numbers refer to DI L 18 version

SYMBOL

PARAMETER

CONDITIONS

Functional range

Vee

supply voltage range

Tamb

operating ambient temperature range

fcLK

clock input frequency

N

divider

Ice

supply current

fxrAL

crystal oscillator

z,

input impedance (pin 2)

input level

Vee= 4.5 V to 5.5 V; Tamb = -10 to 80 �C; see typical sensitivity curve in Fig. 6

f = 80 to 150 MHz

f = 150 to 1000 MHz

f = 1000 to 1300 MHz

R,

prescaler input resistance

see SMITH chart in Fig. 7

c,

input capacitance

Output ports (current-limited) PO-P3

ILO

leakage current

I sink

output sink current

V13 = 13.5 V V13=12V

Output ports (open collector) P4-P7 (see note 1)

ILO

leakage current

VoL

output voltage LOW

V9 =13.5V lg= 10 mA; note 2

Input P3

loH

input current HIGH

loL

input current LOW

Input ports P4-5, P7

VoH = 13.5 V VoL = 0 V

V1L

input voltage LOW

V1H

input voltage HIGH

l1H

input current HIGH

l1L

input current LOW

Input port P6

Ve= 13.5 V Ve= 0 V

l1H

input current HIGH

l1L

input current LOW

V1=13.5V V1= 0 V

MIN. TYP.

4.5 -10 64 256 25 3.2 -480

-
35 4 -400

12/-25 -

9/-28 -

40/-15 -

-

50

-

2

-

-

0.7

1.0

-

-

-

-

-

-

-10

-

-

-

2.7

-

-

-

-10

-

-

-

-10

-

MAX.

UNIT

5.5 80 1300 32767 50 4.48 -320

v
oc
MHz
mA MHz
Q

300/2.6 mV/dBm

300/2.6 mV/dBm

300/2.6 mV/dBm

-

Q

-

pF

10

�A

1.5

mA

10

�A

0.7

v

10

�A

-

�A

0.8

v

-

v

10

�A

-

�A

10

�A

-

�A

August 1991

678

Signetics RF Communications
1.3GHz bi-directional 12c bus controlled synthesizer

Preliminary specification
TSA5511

SYMBOL

PARAMETER

CONDITIONS

SCL and SDA inputs

V1H

input voltage HIGH

V1L

input voltage LOW

llH

input current HIGH

l1L

input current LOW

Vs= 5 V, Vee= 0 V; Vs= 5 V, Vee= 5 V
Vs= 0 V, Vee= 0 V; Vs= 0 V, Vee= 5 V

Output SDA (open collector)

ILO

leakage current

V4

output voltage

V4= 5.5 V l4 =3 mA

Charge-pump output PD

llH l1L Vo l1Leak

input current HIGH (absolute value) input current LOW (absolute value) output voltage off-state leakage current

CP=1 CP=O in-lock TO= 1

Operational amplifier output UD (test mode: TO= 1)

Vrn

output voltage

V1L = 0 v

Vrn

output voltage when switched-off

OS = 1; VIL = 2 v

G

operational amplifier current gain;

OS= O; V1L= 2 V;

119/(11 - l11eak)

118 = 10 �A

MIN. TYP. MAX.

UNIT

3.0

-

-

-

-

-

-

-

-10

-

-10 -

5.5

v

1.5

v

10

�A

10

�A

-

�A

-

�A

-

-

10

�A

-

-

0.4

v

90

220

300

�A

22

50

1.5

-

75

�A

2.5

v

-5

-

5

nA

-

-

-

-

2000 -

100

mV

200

mV

-

Notes to the characteristics 1. When a port is active, the collector voltage must not exceed 6 V. 2. Measured with a single open-collector port active.

August 1991

679

l
c:
~
~
2c kil
~
39 nF

22kn
r-C=:J- +33 v
I varicap
input

......
(,)

!ll
IQ
.""c0o'

{j) :D

I
N 0;--�

"Tl
0
~
c3 :

. ~
gc""o'

&.
0
"

6'

:J

Ill

rn--~J ~F '2

18

'N
(')
c0rn-

4 MHz 27 p

3

17HnF

16

I-

. - - - - - - - - - - - - - - - - - - - - - - ! oscillator
output

SDA MICROCONTROLLER

nF

14

15

TSA5511

.------------~1} ~~~~s

~

SCL

15

H 1 4 r r . ;

P7

13 , PO

0.1 �F

8
:J
a....+
cao . rn
'<

----:16

IF

AFC

SECTION

7

12

:J

....+

TUNER

c::oT

~.

P5

cN o

P4

""'

I

J_ 22

22

22

kn

kn

kn

IF signals

+5V

Fig.5 Typical application (DIL18).

MCD238
+12V

.,,
~
en-I 53�
)> $
1. 01
0........1.... 2g�

Signetics RF Communications
1.3GHz bi-directional 12C bus controlled synthesizer

Preliminary specification
TSA5511

7Z21590.1
1000 s3~~'E�s3~~'E�s
z CL. guaranteed operating area

1~~~~~~~~~~~~~

0

500

1000

1500

fi (MHz)

Fig.6 Prescaler typical input sensitivity curve; Vcc= 4.5 to 5.5 V; Tarrb = -10 to +80 �C.

Fig.7 Prescaler Smith chart of typical input impedance; Vee= 5 V; reference value= 50 0.

August 1991

681

Signetics RF Communications
1.3GHz bi-directional 12c bus controlled synthesizer

Preliminary specification
TSA5511

FLOCK FLAG DEFINITION (FL)
When the FL flag is 1, the maximum frequency deviation (~f) from stable frequency can be expressed as follows:
M=� (Kvc0 1K0 ) x lcpX(C1 + C2)/(C1 xC2)

where:

Kvco lcp Ko C1 and C2

oscillator slope (HzN) charge-pump current (A) 4 x 10E6 loop filter capacitors

FLOCK FLAG APPLICATION
� Kvco = 16 MHzN (UHF band) � lcp =220 �A � C1 =180 nF � C2 =39 nF � ~f =� 27.5 kHz.

Table 5 Flock flag settings
Time span between actual phase lock and FL-flag setting Time span between the loop losing lock and FL-flag resetting

MIN. 1024 0

C2
-1~ R MGA032
Fig.8 Loop filter.

MAX. 1152 128

UNIT �s �s

c Purchase of Philips 12 components conveys a license under the Philips' 12C patent to use
the components in the 12C system provided the system conforms to the 12C specification defined by Philips. This specification can be ordered using the code 9398 358 10011.

August 1991

682

Signetics RF Communications
Frequency synthesizer for cellular radio communication

Objective specification
UMA1014T

FEATURES

QUICK REFERENCE DATA

- Single chip synthesizer solution; - Compatible with Philips Cellular

Symbol

Parameter

Min. Typ. Max. Unit

Radio chipset; - Fully programmable RF divider;

VCC& VCP Supply voltage range

4.5 s.o s.s v

- IIC two-line serial bus interface; - On chip crystal oscillator\TCXO

ICC+ ICP Supply current

-

13

.

mA

buffer from 3 to 16 MHz; - 16 reference division ratios allowing ICCpd

ICC in power down

-

2.5

- mA

5 to 100 kHz channel spacing; - Crystal frequency divide-by-8 output; FREF - On chip out-of-lock indication ;

Phase comparator reference

s

frequency

-

100 KHz

- Two VCO control outputs;

- Latched synthesizer alarm output;

RFin

- Status register including out-of-lock

RF frequency input

so

-

1100 MHz

indication and power failure; � Power down mode.

Tamb

Operating temperature range -40

-

85

oc

APPLICATIONS
- Cellular mobile radio (NMT, AMPS, TACS) - Private Mobile Radio (PMR) � Cordless telephones

GENERAL DESCRIPTION

ORDERING AND PACKAGE INFORMATION

The UMA1014T is a low power universal synthesizer which has been designed for use in channelized radio communications. The IC is manufactured in bipolar technology and is designed to operate from 5 to 100 kHz channel spacing with an RF input of 50 to 1100 MHz. The channel is programmed via the standard IIC bus. A low power sensitive RF divider is integrated as well as a dead
zone eliminated tri-state phase comparator. A low noise charge pump delivers 1 mA or 1/2 mA output current enabling better compromise between fast switching and loop bandwidth. A power down circuit allows the synthesizer to be idled.

Extended Type number
UMA1014T UMA1014M

Package

Pins

Pin Position

Material

16 S016

plastic

20 SSOP20 plastic

Code
SOT109A SOT266A

683

Signetics RF Communications
Frequency synthesizer for cellular radio communication

Objective specification
UMA1014T

tZl IC ~"

=...

.~.........~.>....
IC C

II

...

.......I..C..........a~...:...
:i u

~
.a.:.
"'

I l l "Q '

I 1

FIG. 1 Block diagram

684

Signetics RF Communications
Frequency synthesizer for cellular radio communication

Objective specification
UMA1014T

FIG 2 PIN CONFIGURATION

PINNING

llCln

,....111n

........

&IOllJ

..

mc. . 1.
.....
��

Symbol

Pin S016 SSOP20

"'' OSCin

1

1

OSCout

2

3

WCDI VCP
.... vcc PCD

3

4

4

s

s

6

GD

6

7

VCOA

7

8

RF

8

10

SCL

9

11

SDA
�. c.
HPDN

10

13

11

14

SAA

12

15

VCOB
- l.C. SYA
ll,C.
SCL FX8

13

16

14

17

15

18

16

20

N.C. =not connected

Description
Oscillator input or TCXO input Oscillator output Charge pump S Volts supply S Volts supply Charge pump output Ground VCO buffer switch output A (including out-of-loct) RF input Serial clock line input Serial data line input/output Hardware power down (low active) Slave address select input A VCO buffer switch output B Internally connected (for test purpose only) Synthesizer alann output 1/8 crystal frequency output

LIMITING VALUES

ln accordance with the Absolute Maximum System (IEC 134).

Symbol
vcc
Vi Tstg Tamb

Parameter Supply voltage range Voltage range at pin i to ground Storage temperature range Operating ambient temperature range

Min

Max

Unit

-0.3

7

v

0

Vee

v

-SS

+125

oc

-40

8S

oc

HANDLING
Every pin withstands the ESD test in accordance with MIL-SID-883C class A (method 301S-2). Inputsad outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling Integrated Circuits.

685

Signetics RF Communications
Frequency synthesizer for cellular radio communication

Objective specification
UMA1014T

FUNCTIONAL DESCRIPTION
The UMA1014T is a low power frequency synthesizer for radio communications which operates in the 50 to 1100 MHz range. The device includes an oscillatot-.buffer circuit, a reference divider, an RF main divider, a tri-state phase comparator, a charge �pump and a control circuit which transfers the serial data into the four internal 8 bit-registers. The VCC supply feeds the logic part while VCP feeds the charge-pump only. Both supplies are +5 Volts (+/10%). The power down facility puts the synthesizer in the idle mode (all current supplies are switched off except in the control part). Any IIC transfer is permitted during this mode and all information in the registers is retained allowing fast power-up.
MAIN DIVIDER.
The main divider is a fully programmable pulse swallow type counter. After a sensitive input amplifier (50 mV, -13 dBm), the RF signal is applied to a 31/32 dual-modulus counter. The output is then used as the clock for the 5-bit swallow counter R= (MD4,..., MDO) and the 13 bit main counter N= (MD17, ..., MD5). The ratio is sent via the IIC bus into the registers B, C and D. It is then buffered in a 18-bit latch. The ratio in the divider chain is updated with this new information only after the least significant bit (DO) is received. This update is synchronized to the output of the divider in order to limit the phase error during small jumps of the synthesized frequency.

MD17 MD16 MD15

Bl

BO

Cl

MSB

:N
MD8 MD7
CO D7

:R

MD5 MD4

MDO

D5 D4

DO

LSB

Division ratio in the main divider
The main divider can be programmed to any value between 2048 and 262143 (i.e. 218.J). If a ratio X, which is less than 2048, is sent to the divider, the ratio (X+2048) will be programmed. For switching between adjacent channels it is possible to program only register D allowing shorter IIC programming time.
OSCILLATOR.
The oscillator is a common collector Colpitts type with external capacitive feedback. It has been designed to function also as a buffer when a TCXO or any clock is used. The oscillator has very small temperature drift and high voltage supply rejection. When acting as a buffer, no additional external components will be necessary.

686

Signetics RF Communications
Frequency synthesizer for cellular radio communication

Objective specification
UMA1014T

REFERENCE DIVIDER.

The reference divider is semi-programmable with 16 division ratios which are selected via the IIC bus. The programming uses bits A3 to AO of register A as shown below. These ratios can be used with crystal frequencies from 3 to 16 MHz. All popular channel spacings can be obtained from a single crystal I TCXO frequency of 9.6 MHz.

0

0

0

0

0

1

0

0

0

0

0

1

1

0

0

0

0

0

1

0

l

0

0

1

1

0

0

0

0

0

0

0

0

1

1

0

0

1

0

1

1

1

0

1

i!,~Jilil~~~~~~~it"

.. . .. :.: .:�:~.�; ...�.

.�.. .� .. . . �.' ...... : ,.;.:.� �.�.� ..

reference divider programming

687

Signetics RF Communications
Frequency synthesizer for cellular radio communication

Objective specification
UMA1014T

PHASE COMPARATOR AND CHARGE PUMP.
The block diagram of the phase comparator and charge pump is shown below. The phase comparator is both a phase and frequency detector. It comprises dual flip-flops together with logic circuitry which eliminates the dead zone. When a phase error is detected, the UP or DOWN signal becomes high . It switches on the corresponqing current generator which sources or sinks current as appropriate into the loop filter. When no phase error is detected, PCD goes tristate. The final tuning voltage of the VCO is provided by the loop filter. The charge pump current is programmable via the IIC bus. When bit IPCD (bit AS) is set to logic 1, the charge pump will deliver 1 mA. When IPCD is logic 0, the charge pump will deliver 0.5 mA.
The phase comparator has a phase inverter logic input (PHI). This allows the use of inverted or non-inverted loop filter configurations. It is thus possible to use a passive loop filter which can offer high performance without an operational amplifier. The function of the phase comparator and charge pump is given in the table below and a typical transfer curve is shown overleaf.

UP DOWN
Ipcd

PHI=O Fref<Fvar
0 1 -1 mA

(Passive loop filter)

Fref>Fvar Fref=Fvar

1

0

0

0

1 mA

< +/- 5 nA

PHI= 1 Fref<Fvar
1 0 lmA

(Active loop filter)

Fref>Fvar Fref=Fvar

0

0

1

0

-1 mA <+/- 5 nA

Operation of the phase comparator

688

Signetics RF Communications
Frequency synthesizer for cellular radio communication

Objective specification
UMA1014T

tPCD averaged owr Reference Period ol 2� u1 (Amps)
25u ...---..-----,....-----.---.---"""T""----.

2�u -+---+--.......,~-----+----+--~---.,~

15U -t---+----;l----+---+---'7"----1

1.ou
500.0n

-+---+----.,1----+---+-...,,,...L__,~-=..., +---+--__...1----1---.,+--.:r ::o.z ...,:~ :+---1

: z . r o.o
-500.on

++-----;~+..-..-.--=.i,.i,.-..-'-=i.~-:":";:"..',.=..-..-z'+----+---++-----;----;1

.....-r � -1.lkJ
Z J z -15u

IPCD.o.SmA

�-22..S0Uu +_�1.P_ .'C.o,._ ,1m,A,_ j.-i_ <_ --+_-_ --1_-_ ---_+_ ---_+_ --_ -+_ --_ --.I....

-30.0n

-20.0n

10.0n

10 On 0.0 Phue Difference 20.0n

30 On

FIG. 4 Gain of phase detector and charge pump OUT-OF-LOCK DETECTOR.
An out-of-lock detector using the UP and DOWN signals from the phase comparator is included on chip. Pin VCOA is an open collector output which is forced low during out-of-lock. This information is also available via the IIC bus in the status register. When the phase error (measured at the phase comparator) is greater than approximately 200 ns, an out-of-lock condition is immediately flagged. The flag is only released after 6 reference cycles of phase error less than 200 ns.

UP

or
DOWN

- N i - I- - - - -

REF

OOL

VCOR

FIG. 5 Out-of-lock function
689

Signetics RF Communications
Frequency synthesizer for cellular radio communication

Objective specification
UMA1014T

MAL!\J CONTROL

The control part consists mainly of the IIC control interface and a set of four registers, A, B, C and D. The serial input data (SDA) is converted to 8 bit parallel words and stored in the appropriate registers. The data transmission to the synthesizer is executed in the burst mode with the following format:

//slave addr./subaddr./datal/data2/.../datan// ; n up to 4.

Data byte 1 is written in the register indicated by the subaddress. An auto-increment circuit if enabled (AVl=l) then provides the correct addressing for the following data bytes. Since the length of the data burst is not fixed, it is possible to program the whole set of registers or just one. The registers are structured in such a way so that the burst, for normal operation, is kept as short as possible. The bits that are only programmed during the set-up (reference division ratio, power down, phase inversion and current on PCD) are stored in registers A and B.

In the slave address, six bits are fixed. The remaining two bits depend on the application.

0

0

0

1

I I SAAN R/WN

Slave address
SAAN is the slave address select not. When SAA (pin 12) is high, then SAAN = 0, and when pin 12 goes low SAAN = 1. This allows the use of two UMA1014Ts on the same IIC bus with a different address. R/WN ( read/write not) should be set to 0 when writing to the synthesizer or set to 1 when reading the status register.
The subaddress includes the register pointer, and sets the flags related to the auto-increment (AVI) and the alarm disable (DI) :

x

x

x

DI AVI x SBl SBO

Subaddress

SBl SBO

DI (Disable Interrupt); Dl=l disables SYA alarm DI=O allows SYA alarm

0

0

AYI (Auto Value Increment);

AVI=l enables auto-increment AVI=O disables auto-increment

0

1

SBl/SBO point to the register where DATAl will be written. (see table attached)

1

0

x means not used.

1

1

register pointed
A
B
c
D

Pointer of the registers

690

Signetics RF Communications
Frequency synthesizer for cellular radio communication

Objective specification
UMA1014T

MAIN CONTROL (continued)
When the auto-increment is disabled (AVI=O) , the subaddress pointer will maintain the same value during the IIC bus transfer. All the databytes will then be written consecutively in the same register pointed to by the subaddress.

STATUS REGISTER and synthesizer alarm.
When an out-of-lock condition or a power dip occurs, open collector output SYA (pin 15) is forced low and latched. The pin SYA will be only released after the status register is read via the IIC bus.
The status register contains information as shown below:

0

0

0 OOL 0 ILOOLI LPD DI

where:

OOL momentary out-of-lock

LOOL latched out-of-lock

LPD latched power dip

DI

disable interrupt (of the last write cycle )

The IIC bus protocol to read this internal register is a single byte without subaddressing: //slave address (RJWN=l)/status register (read)//

691

Signetics RF Communications
Frequency synthesizer for cellular radio communication
MAIN CONTROL (continued) BIT ALLOCATION :

Objective specification
UMA1014T

01

0

1

PHI VCOB VCOA MD17 MD16 10100101

10 MD15 MD14 MD13 MD12 MDll MDlO MD9 MD8 00111000

11 MD7 MD6 MDS MD4 MD3 MD2 MDl MDO 10000000

X means not used

register name
A
B
c

bit name

function

preset value

PD IPCD RD3 ... RDO PHI VCOA VCOB MD17MD16 MD15 ... MD8 MD7 ... MDO

power down
programmable current in PCD reference ratio phase inverter
VCO switch A VCO switch B bits 17 and 16
bits 15 ... 8
bits 7 ... 0

PD=O normal operation
IPCD=l: lmA IPCD=O : 1/2mA
see table
PHI=O passive loop filter
set the pin 7
set the pin 13
MSB of main divider ratio
main divider ratio
main divider ratio

0
0
1110; r=1536 0
1 0 01
00111000
10000000 r=80000

Registers in UMA1014T

692

Signetics RF Communications
Frequency synthesizer for cellular radio communication

Objective specification
UMA1014T

CHARACTERISTICS Vee = 4.5 to 5.5V ; 25 deg; unless otherwise specified.

Symbol

Parameter

Supply (pins VCC & VCP).

vcc

Supply voltage

range

ICC

Supply current

ICCpd

Supply current

VCP

Supply voltage of

the charge pump

ICP

Supply current C-P

ICPpd

Supply current C-P

Conditions
power down IPCD=O.SmA power down

Min" Typ. Max. Unit.

4.S

.

s.s v

.

11.5

.

mA

-

2.S

- mA

4.5

.

s.s v

.

1.4

.

mA

.

O.OI

.

mA

RF dividers (pin RF)

FRF

Frequency range

so

VRFrms

input voltage level

SO to IOOMHz

ISO

IOO to 1100 MHz

so

at I GHz

.

Rin

Input resistance

at IOOMHz

.

Cin

Input Capacitance*

.

RRF

Division ratios

2048

.

1100 MHz

.

200

mV

-

ISO

mV

200

.

n

600

.

n

2

.

pF

. 262143 .

� Note: Cin in parallel with Rin

Oscillator and reference divider (pins OSCin, OSCout)

FOSC

Oscillator

3

frequency.range

VOSC (ru)

Input level sine

0.1

wave

vosc (p-p) Input level square

0.3

wave

Zoscout

output impedance at OSCout pin

.

RrlEF

Reference division ratio

see table

128

Fo

Output frequency

s

range

.

16

MHz

- VCC+ Vrms 2.8

.

vcc Vpp

.

2

Kn

.

1920

.

.

IOO KHz

693

Signetics RF Communications
Frequency synthesizer for cellular radio communication

Objective specification
UMA1014T

CHARACTERISTICS (continued)

Symbol

Parameter

Conditions

Min. Typ.

118 crystal frequency open collec�r output (pin FX8)

loL

Current output low

Vol C!:0.6V

1

.

Phase comparator (pin PCD)

FPCO

Frequency range

5

\>co
1Pco1k

Output current
Vpco =2.5 v
Output leak.age current

BitlPCD= l BitIPCD=O

0.8

1

0.4

0.5

.5

+/-1

VPCD

Output voltage

0.4

Serial clock input, serial data input (pins SDA, SCL)

Fclk

clock frequency

VIH

input voltage high

VIL

input voltage low

IlH

input current high

0

.

3

.

.

.

.

3

IlL

input current low

Cl

input capacitance

IOL

SDA sink current VOL=0.4 V

-10

-5

.

.

.

.

Slave address select input (pin SAA) hardware power down input (pin HPDN)

VIH

input voltage high

3

.

VIL

input voltage low

.

.

IlH

input current high

.

.

IlL

input current low

-10

.

VCO output switches (pins VCOA, VCOB), synthesizer alarm (pin SY A)

VOL output voltage low

note 1

.

.

IOL

sink current low

400

.

Note: 1. The pin VCOA is forced to zero state during out-of-lock

Max. Unit.

.

mA

100

KHz

13

mA

0.7

mA

5

nA

VCP-0.5 v

100

KHz

.

v

1.5

v

10

�A

.

�A

10

pF

3

mA

. v

0.4

v

0.1

�A

.

�A

0.4

v

.

�A

694

Signetics RF Communications
Frequency synthesizer for cellular radio communication

Objective specification
UMA1014T

AF lnpu CriV rrisl
200
150
100
58

r1

I I

\ I- - - - - - - - - - - - - -- .,

I

\

\

Guoronteed Region

OF Opero ti on

I I
I

\

I

L - - - - - - - - - - - - - _j

T1:1picol RF Sene1t11,1it1i1 C25� Cl

u m im-
m

I\)
m
C!l

U1 Input

.....

Q
m

Frequencbl

m m

lMHzl Q

-I\)
C!l
(!)

AF I npu CriV rrisl
200
150
100
50

Low Frequency Sensitivity

r----

1

I

I

I

' ' L--------- Guoronteed Region

' ' ' ' '

OF Operotion

T1:1picol RF Seneit11,1~i~t~1:1:--""i1;2~5ccrci,-~------~

-c::iFIrenqpuuentc1:1U...1..

m

c::i

CHHzl

I\.)
m m

FIG. 6 RF Input Sensitivity

695

V::c V:c

�7.5Y

Ul 78L05
I VI

VO I

Vee

vo-::c

- Vee vce

I

LOV W l *

CURR< NT

'\,

LED 'Iii

~r I 2A nR172R

GI

Cll 120p

.. _,_

~ UI

vee

Cl5 ;r..,tOOn

~

..Le��
;r..,�00n

- -5DA

m m<D

rh ~

VI iJATl7

Yee
n
c�

lc6
"'"T"" In

l
R6

All 56R
_I_

Y2

8ATl7

Al

IOK

~p X]r@

GNO

SMA

C2

..J...Cl

_LCI

Jt5n

~~50n J;en

J,SK

.,, .(o/)�

.,

:l (I)

CD
.c.0

5� J"'J
Tl

CD :::::i

0
~

~

3 c

,,. Cl>

g:l

'<

.::.:::.:.::.ir.

:l
"'

CD

CNl>.

.CD,

.0 ,

0 CD
c
I.l,l

~
()"

0 0
3 3 c
:::::i
6"
!!
()"
:::::i

cs:

.0g:
Cl)

.)..>... 0......

.a""0,,''i�
(I)

0

� ~
-i "0"�

:l

Slgnetlcs RF Communlcstlons
Low-power frequency synthesizer

Objective specification
UMF1005T

DESCRIPTION
The UMF1005 is a low power, high performance frequency synthesizer in CMOS technology. This integrated circuit is designed to achieve 10-2000 KHz channel spacing. The channel is selected via a high speed serial interface.
FEATURES
- Fast locking by "Fractional-N" divider - Auxiliary synthesizer. - Digital phase comparator with proportional and integral charge pump output. - High speed serial input. - Low power consumption.

Applications
- Mobile telephony - Portable battery-powered radio equipment Package outlines
UMF1 OOST: 20-lead plastic mini-pack; (SSOP20,SOT266)

October 1991

697

Signetics RF Communications
Low-power frequency synthesizer

Objective specification
UMF1005T

DATA CLOCK STROBE
INM1 INM2
INR
INA

Serial input + program latches

NM2 NM3
8

u
NM4 4

FMOD

NF 3

Fractional accumulator

EM

UMF1005

Main phase detector

FRO 8
2

Prescaier feedback
Normal output charge pump

EM+EA

NR 12

SM 2

Main reference
select

CL
2 Speedup output charge pump

Reference divider 2

CK 4

Integral
output charge pump

EA

NA

EA

12

-+-8

Auxiliary divider

2

Auxiliary

output

charge

pump

FB1 FB2 RF RN
PHP
PHI RA
HA LOCK

Vss

VssA

Fig. 1: Block diagram UMF 1OOST

October 1991

698

Signetics RF Communications
Low-power frequency synthesizer

Objective specification
UMF1005T

PINNING

Symbol

Pin

Voo

INM1

2

INM2

3

DATA

4

CLOCK

5

STROBE

6

INR

7

INA

8

RA

9

PHA

10

PHI

11

VssA

12

PHP

13

VooA

14

RN

15

RF

16

LOCK

17

FB1

18

FB2

19

Vss

20

Voe IN M l INM2 DATA CLOCK STROBE
INR INA
RA PHA

UMF1005T

vss FB2 FBI LOCK RF RN
VDDA PHP
VssA PHI

Fig. 2: Pinning UMF1005T

Description
digital supply voltage main divider positive input main divider negative input serial data input line serial clock input line serial strobe input line reference divider input line auxiliary divider input line auxiliary current setting; resistor to Vss auxilia:ry phase detector output integral phase detector output analog ground; internally connected to Vss proportional phase detector output analog supply voltage main current setting; resistor to Vss frac. comp. current setting; resistor to Vss lock detector output feedback output for prescaler modulus control feedback output for prescaler modulus control common ground connection

October 1991

699

Signetics RF Communications
Low-power frequency synthesizer

Objective specification
UMF1005T

Serial programming input
The serial input is a 3 wire input (CLOCK, STROBE, DATA) to program all counter ratios, DAC's, selection and enable bits. The programming data is structured into 24 or 32 bit words; each word includes 1 or 4 address bits. Figure 3 shows the timing diagram of the serial input. When the STROBE = L, the clock driver is enabled and on the positive edges of the CLOCK the signal on DATA input is clocked into a shift register. When the STROBE= H, the clock is disabled and the data in the shift register remains stable. Depending on the 1 or 4 address bits the data is latched into different working registers or temporary registers. In order to fully program the synthesizer, 4 words must be sent: D, C, B and A. Figure 4 shows the format and the contents of each word. The E word is for testing purposes only. The E (test) word is reset when programming the D word. The data for NM4, CN, and PR is stored by the B word in temporary registers. When the A word is loaded, the data of these temporary registers is loaded together with the A word into the work registers which avoids false temporary main divider input. CN is only loaded from the temporary registers when a short 24 bit AO word is used. CN will be directly loaded by programming a long 32 bit A1 word. The flag LONG in the D word determines whether AO (LONG = "O") or A1 (LONG = "1 ") format is applicable. The A word contains new data for the main divider. The A word is loaded only when a main divider synchronization signal is also active, to avoid phase jumps when reprogramming the main divider. The synchronisation signal is generated by the main dividers. It disables the loading of the A word each main divider cycle during maximum 300 main divider input cycles. To be sure that the A word will be correctly loaded the STROBE signal must be H for at least 300 main divider input cycles. Programming the A word means also that the main charge pumps on output PHP and PHI are set into the speed-up mode as long as the STROBE is H.
DATA DATA VALID CHANGE

STROBE October 1991

II

'susT

tHOST

i

i'

�VH �VL

I

Clock Enabled

Clock Disabled

i

Shift In Data

Store Data

Fig. 3 Serial Input timing sequence

700

Signetics RF Communications
Low-power frequency synthesizer

Objective specification
UMF1005T

MSB

LSB

J ~ ,:..::..;.._031...-.-.---.-.-~--,--,-,--,-,....,...,..,.....-r-r-r-i--,--,-,-0rm0

NM2

Mrt:1 :--, : 1:)t~~:i==
� l,:.:�:�I �~ I ,; I ~ l+,I

,l,:�:�:,1 : .. : I I

I IT
0 1 0 10 _l_l_l
� I,:,:,: ,I
~

T

I

NR

..1

..1

I

I

F L

SM

~

SA

E MO A 0 N

DG

l ..1

~~,,,, I

00

Fig. 4 Serial input word format

October 1991

701

Signetics RF Communications
Low-power frequency synthesizer

Objective specification
UMF1005T

Symbol NM1 NM2 NM3 NM4 PR

Bits 12
8 if PR= "Ox" 4if PR="1x" 4if PR="1x"
4 if PR= "11"
2

NF

3

FMOD

1

LONG

CN

8

CL

2

CK

4

EM

1

EA

1

SM

2

AM

2

NR

12

NA

12

Function
number of main divider cycles when prescaler is programmed in ratio R1 (FB1 = "1", FB2 = "O")*

number of main divider cycles when prescaler is

I

programmed in ratio R2 (FB1 = "O", FB2 = "O")*

I�
I

number of main divider cycles when prescaler is programmed in ratio R3 (FB1 = "O", FB2 = "1 ")*

number of main divider cycles when prescaler is programmed in ratio R4 (FB1 = "O", FB2 = "1 ")*

prescaler type in use PR= "00": modulus 2 prescaler PR= "10": modulus 3 prescaler PR = "11 ": modulus 4 prescaler fractional - N increment fractional - N modulus selection flag "1" : modulo 8 A word format selection flag "O": 24 bit AO format "1": 32 bit A1 format current setting factor for main charge pumps acceleration factor for proportional charge pump current acceleration factor for integral charge
pump current main divider enable flag auxiliary divider enable flag reference select for main phase detector reference select for aux. phase detector reference divider ratio auxiliary divider ratio

* not including reset cycles and fractional - N effects.

October 1991

702

Signetics RF Communications
Low-power frequency synthesizer

Objective specification
UMF1005T

Auxiliary variable divider The input signal on INA is amplified to logic level by a single ended input buffer, which accepts low level AC coupled input signals. This input stage is enabled if the serial control bit EA= "1 ". Disabling means that all currents in the buffer are switched off. A fixed divide by 8 divider is the first stage of the counter, which has been optimized to accept a 100 MHz input signal. The second stage is a 12-bit programmable counter. The total division ratio can be expressed as:
N Aux = 8 x NA; with NA= 4 to 4095
Reference variable divider (fig. 5)
The input signal on INR is amplified to logic level by a single ended input buffer, which accepts low level AC coupled input signals. This input stage is enabled by the OR function of the serial intput bits EA and EM. Disabling means that all currents are switched off. The reference divider consists of a programmable divider by NR (NR = 4 to 4095) followed by a three bit binary counter. The 2 bit SM determines which of the 4 output pulses is selected as main phase detector input. The 2 bit SA determines the selection of the auxiliary phase detector signal. To obtain the best time spacing for the main and auxiliary reference signals, the opposite output will be used for the auxiliary phase detector, reducing the possibility of unwanted interactions. For this reason the programmable divider produces a symmetric output pulse for even ratios and a 1 input cycle asymmetric pulse for odd ratios.

October 1991

703

Signetics RF Communications
Low-power frequency synthesizer

Objectiw specification
UMF1005T

MAIN SELECT SM:"OO"

DETECTOR

I��

SM= "10"

IRnepfuetrenc�~ Divide by NR

l
+2 +2 +2
l

SM: "11"

AUXILIARY SELECT EM= "11"

.... EM= "10"
- EM: "01"

AUXILIARY
PHASE . DETECTOR

EM= "00"

Fig. 5 Reference variable divider

Main variable divider
The input signals on INM1, INM2 are amplified to a logic level by a balanced input comparator
= giving a common mode rejection. This input stage is enabled by serial control bit EM 1.
Disabling means that all currents in the comparator are switched off. The main divider is built up by a 12 bit counter plus a sign bit. Depending on the serial input values NM1, NM2, NM3, NM4 and the prescaler select PR, the counter will select a prescaler ratio during a number of input cycles according to the following table:

I I�

October 1991

704

Signetics RF Communications
Low-power frequency synthesizer

Objective specification
UMF1005T

Counter Status (-NM1 - 1) to 0 (-NM1 -1) to -1 1 to NM2 0 to NM2 0 to NM3 0 to NM4

FB1 1 1 0 0 0 1

FB2 0 0 0 0 1 1

Prescaler ratio R1 R1* R2 R2* R3 if PR= "1X"
= R4 if PR "11"

� when the fractional accumulator overflows

The total division ratio from prescaler to the phase detector may be expressed as:

N = (NM1 + 2) x R1 + NM2 x R2 + [(NM3 + 1) x R3 + [(NM4 + 1) x R4]]

or when the fractional accumulator overflows:

N' = (NM1 + 1) x R1 + (NM2 + 1) x R2 + [(NM3 + 1) x R3 + [(NM4 + 1) x R4]]
= = with prescaler ratio R2 R1 + 1 --> N' N + 1

PR defines the prescaler type in use and the bit capacity for NM2, NM3 according to the following table:

PR

Modulus prescaler

00

2

01

2

10

3

11

4

Bit capacity NM1 NM2 NM3 12 8 12 8 12 4 4 12 4 4

NM4 4

When a number of prescaler ratios is set on 2, respectively 3, the reset cycles for R3, respectively R4 will also not occur. Programming to e.g. 2 prescaler ratios will result in an overall divider ratio:
N =(NM1 + 2) x R1 + NM2 x R2

The loading of the work registers NM1, NM2, NM3, NM4, PR is synchronized with the state of the main counter, to avoid extra phase disturbance when switching over to another main divider ratio as is explained in the Serial Programming Input chapter.

October 1991

705

Signetics RF Communications
Low-power frequency synthesizer

Objective specification
UMF1005T

At the completion of a main divider cycle, a main divider output pulse is generated which will drive the main phase comparator. Also the fractional accumulator is incremented with NF. The accumulator works modulo Q. Q is preset by the serial control bit FMOD to 8 when FMOD = "1 ". Each time the accumulator overflows, the feedback to the prescaler will select one cycle using prescaler ratio R2 instead of R1. As shown above, this will increase the overall division ratio by 1 if R2 = R1 + 1. The mean division ratio over Q main divider cycles will then be:
NO= (NM1 + NM2 +2) x R1 + [(NM3 + 1) x R3 + [(NM4 + 1) x R4) +NF IQ
Programming a fraction means the prescaler with main divider will divide by Nor N + 1. The output of the main divider will be modulated with a fractional phase ripple. This phase ripple is proportional to the contents of the fractional accumulator FRO, which is used for fractional current compensation.
Phase detectors (fig. 6)
The auxiliary and main phase detectors are a 2 0-type flipflop phase and frequency detector. The flipflops are set by the negative edges of output signals of the dividers. The reset inputs are activated when both flipflops have been set and when the reset enable signal is active (L). Around zero phase error this has the effect of delaying the reset for 1 reference input cycle. This avoids non-linearity or deadband around zero phase error. The flipflops drive on-chip charge pumps. A pull-up current from the charge pump indicates the VCO frequency shall be increased while a pull-down pulse indicates the VCO frequency shall be decreased.

October 1991

706

Signetics RF Communications
Low-power frequency synthesizer

Objective specification
UMF1005T

INR

Reference Divider

R

Aux/Main Divider

P-type
PH
N-type charge pump

INR

L

LJ

LJ

R
x

p ~~~--'r--l~~~~~~~~~r--1~~~~-

N ~~~----'ll

r--1~~~~

Fig. 6 Phase detector structure with timing
Current settings
The UMF1005 has 3 current setting pins RA, RN, and RF. The active charge pump currents and the fractional compensation currents are linearly dependent on the current in the current setting pins. This current IR can be set by an external resistor to be connected between the current setting pin and Vss. The typical value R (current setting resistor) can be calculated with the formula:
R = ( VooA - 1.1 - 80 x SQRT(IR)) I IR
The current can be set to zero by connecting the corresponding pin to VoDA�

October 1991

707

Signetics RF Communications
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Objective specification
UMF1005T

Auxiliary output charge pumps
The auxiliary charge pumps on pin PHA are driven by the auxiliary phase detector and the current value is determined by the external resistor RA at pin RA. The active charge pump current is typically:

Main output charge pumps and fractional compensation currents

The main charge pumps on pin PHP and PHI are driven by the main phase detector and the current value is determined by the current at pin RN and via a number of OACs which are driven by registers of the serial input. The fractional compensation current is determined by the current at pin RF, the contents of the fractional accumulator FRO and a number of OACs driven by registers from the serial input. The timing for the fractional compensation is derived from the reference divider. The current is on during 1 input reference cycle before and 1 cycle after the output signal to the phase comparator. Figure 7 shows the waveforms for a typical case.
When the serial input A word is loaded, the output circuits are in the "speed-up mode" as long as the STROBE is H, else the "normal mode" is active. In the "normal mode" the current output PHP is:

IPHP_N = lpump10 + lcomp10

where:

lpumpto = �CN x IRN I 32 lcomp1 o=�FRO x IRF I 128

:charge pump current :fractional compensation current

The current in PHI is in "normal mode" zero. In "speed-up mode" the current in output PHP is:

IPHP_s = IPHP_N + lpump11 + lcomp11

where:
lpump11 = lpump10 X 2(CL+1) lcomp11 = lcomp10 X 2(CL+1)

:charge pump current :fractional compensation current

In "speed-up mode" the current in output PHI is:

IPHl_S = lpump21 + 1comp21

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UMF1005T

where:

lpump21 = lpump11 X CK 1comp21 = lcomp11 X CK

:charge pump current :fractional compensation current

Figure 7 shows that for a proper fractional compensation the area of the fractional compensation current pulse must be equal to the area of the charge pump ripple output. This means that the current setting on the input RN, RF must have the following ratio:

IRN I IRF = (Q x fvco) I (2 x CN x f1RA)

where:

Q

: fractional-N modulus

fvco = f1NM x N : input frequency of the prescaler

Lock detect
The output LOCK is H when the auxiliary phase detector AND the main phase detector indicates a lock condition. The lock condition is defined as a phase difference of less than �1 cycle on the reference input JNR. The look condition is also fullfilled when the relative counter is disabled (EM= "O" or respectively EA= "O") for the main, respectively auxiliary counter.

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Low-power frequency synthesizer

Objective specification
UMF1005T

[ [ [ [ [[
Reference R

MalnN

[ [, [

~ I

[

I

+N

+N

+N+1

+N

+N+1

Detector output

0D nD

Contents accum.

2

4

3

0

Fractional compensation current

'I.____.

Pulse-width modulation

t1

Output on

PHP, PHI

t2

i
Puls�level modulation

Fig. 7 Waveforms for NF=2, Fraction=0.4

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UMF1005T

LIMITING VALUES

In accordance with the Absolute Maximum System (IEC 134)

Symbol Voo VI I
Ptot
Tstg
Tamb

Parameter

Min

supply voltage

-0.5

voltage on any input

-0.5

DC current into any

-10

input or output

total power dissipation

storage temperature

-65

range

operating ambient

temperature range

-40

Max 6.5 Voo + 0.5 10
tbf 150
85

Unit
v v
mA
mocW
oc

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Objective specification
UMF1005T

DC CHARACTERISTICS
= Voo VooA = 4.5 to 5.5 V; Tamb = -40 to+ 85 �C; unless otherwise specified

Symbol

Parameter

Conditions

Min Typ Max Unit

loo

standby digital supply ENM=ENA=O;

current

inputs on Voo or O

loo

Operational supply

ENM=ENA=1;

current

f1NM=fREF=10 MHz

! '
�A
tbf �A

f1NA=50 MHz

looA

Standby analog supply VRA= VooA; VRF =

currents

VooA; VRN=VooA

looA

Operational analog

supply current

�A tbf �A

Digital outputs FB1, FB2, LOCK

Vol

Output voltage LOW

Vol

Output voltage LOW

VoH

Output voltage HIGH

VoH

Output voltage HIGH

10=1 �A 10=2 mA 10 = -1 �A 10 =-2 mA

- Voo-50 - Voo-0.5

50 mV
0.4 v
mV
v

Charge pump PHA

IPHA IPHA lllPHAljlpHAI

output current PHA
output current PHA
relative output current variation PHA

IRA= -62.5 �A;
VPHA = Voo I 2 IRA= -6.25 �A;
VPHA = Voo I 2
IRA = -62.5 �A; note 2

�450 �500 �550 �A �45 �50 �55 �A
10 %

Charge pump PHP, normal mode (note 1), IRN = -5 to -100 �A, VRF =Yoo

output current PHP

CN x IRN = -16 mA; �450 �500 �550 �A

VPHP = Voo I 2

IPHP

output current PHP

CN x IRN = -1.6 mA;�45 �50 �55 �A

VPHP = Voo I 2

relative output current CN x IRN = -1.6 mA; -

10 %

variation PHP

note 2

CN monotonic output CN = 0 to255;

current range PHP

VPHP =

0

�500 �A

0.4 to Voo - 0.4 V

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UMF1005T

= = Charge pump PHP, speed up mode (note 1), IRN -5 to -100 �A, VRF Voo

IPHP IPHP ~IPHPlllPHPI

output current PHP
output current PHP
relative output current variation PHP CN monotonic output current range PHP

CN x (2(CL+1)+1) X IRN = -96 mA; VPHP = Voo/2 CN x (2(CL+1)+1) x IRN = -9.6 mA; VPHP = Voo/2 CN x (2(CL+1) +1) X IRN = -96 mA; note 2 CN = 0 to 255; VPHP= 0.4 to Voo - 0.4 V

�2.5 �0.25
0

�3.0 �0.30

�3.5 mA �0.35 mA 10 % �3.0 mA

= = Charge pump PHI, speed up mode (note 1), IRN -5 to -100 �A, VRF Voo

lpHJ lpHJ ~IPHif!IPHll

output current PHI
output current PHI
relative output current variation PHI CN monotonic output current range PHI

CN x 2(CL+1)
x CKx IRN = -320 mA; VPHI = Voo/2 CN x 2(CL+1)
x CKx IRN =-32 mA; VpHJ = Voo/2 CN x 2(CL+1) xCK X IRN = -320 mA ; note2 CN = 0 to 255; VPHI= 0.4 to Voo-0.4 V

�8 �0.8
0

�10 �1.0

�12 mA �1.2 mA 15 % �10 mA

= = Fractional compensation PHP, normal mode (note 1),
IRF -5 to -100 �A, VRN Voo

IPHP_FIFAD IPHP_F/FAD

fractional comp. output IRF = -76.8 �A;
current PHP versus FAD FAD = 1 to 7 note 3
fractional comp. output IRF = -7.68 �A;
current PHP versus FAD FAD= 1 to 7 note 3

-700 -600 -500 nA -70 -60 -50 nA

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Objective specification
UMF1005T

Fractional compensation PHP, speed up mode {note 1),
= = IRN -5 to �100 �A, YRN Yoo

IPHP_F/ FRD IPHP_F/ FRO

fractional compensation (2(CL+1)+1 ) x IRF

output current PHP

= -460.8 �A;

versus FRO note 3

FRO= 1to7

fractional compensation (2(CL+1)+1) x IRF

output current PHP

= -46.08 �A;

versus FRO note 3

FRO= 1to7

-4.5 �3.6 -2.7 mA -0.45 �0.36 -0.27 mA

Fractional compensation PHI, speed up mode (note 1),
= = IRN -5 to -100 �A, YRN Yoo

IPHl_F I FRO lpHl_F I FRO

fractional compensation 2(CL+1) x CK x IRF -16 -12

output current PHI

= �1536 �A;

versus FRO note 3

FRO= 1to7

fractional compensation 2(CL+1) x CK x IRF -1.6 -1.2

output current PHI

= -153.6 �A;

versus FRO note 3

FRO= 1to7

-8

�A

-0.8 �A

Charge Pump Leakage Currents

IPHP_L IPHl_L IPHA_L

output leakage current PHP
output leakage current PHI
output leakage current PHA

VRF= VooA VRN = VooA VPHP = 0 to YooA VRF= VooA VRN = VooA VpHI = 0 to VooA VRF= VooA VRN = VooA VPHA = 0 to YooA

�10 nA �10 nA �10 nA

note 1:When a serial input "A" word is programmed, the main charge pumps on PHP and PHI are in the "speed up mode" as long as STROBE = H. When this is not the case, the main charge pumps are in the "normal mode". note 2:The relative output current variation is defined thus:
blour I lour= 2 x (12+11)I1(12 � 11)1; with V1 = 0.4 V, V2 =Yoo� 0.4 V (see fig. 8) note 3:FRO is the value of the 3 bit fractional accumulator

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Objective specification
UMF1005T

Fig. 8 Output current definition

AC CHARACTERISTICS

symbol

parameter

Main divider f1NM V1NM1,2
tPHL
tPLH
tMSM Z1NM

Max. input frequency Differential input signal amplitude
Prop. delay V1NM1-V1NM2 to falling edge FB1, FB2 Prop. delay V1NM1-V1NM2 to rising edge FB1, FB2 Mark-space ratio Minimum impedance Resistive, Capacitive

Reference divider f1NR V1NR tMSR Z1MR

Max. input frequency Input signal amplitude Mark-space ratio Min. impedance Resistive Capacitive

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min typ max unit

20 600
35/65 5

MHz

mVpp

25

ns

25

ns

65/35 %

k.Q

5

pF

30 300 35/65
5

65/35

MHz mVpp %

k.Q

5

pF

Signetics RF Communications
Low-power frequency synthesizer

Objective specification
UMF1005T

AC CHARACTERISTICS (Can't)

Auxiliary f1NA V1NA tMSA Z1NA
Serial Interface fclock

Max. input frequency input signal amplitude Mark-space ratio Min. impedance Resistive Capacitive
Clock frequency

100 300 35/65
5

MHz mVpp %

k.Q

5

pF

10

MHz

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Objective specification
UMF1005T

DEFINITIONS Data sheet status

Objective specification:

This data sheet contains target or goal specifications for product development.

Preliminary specification: This data sheet contains preliminary data; supplementary data may be published later.

Product specification:

This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

�Philips Export B.V. 1991

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not imply any license under patent- or other industrial or intellectual property rights.

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Appllcatlon report for the UMA1014T frequency synthesizer

Appllcatlon note
SCO/AN91004

1.

INTRODUCTION

This application note is intended as a guide to designing a phase locked loop based on the Philips UMA1014T frequency synthesizer integrated circuit.
The UMA1014T is a low power single chip solution to frequency synthesis
in the range 100 MHz to 1100 MHz and is primarily intended for use in analogue cellular radio applications.

The device comprises of the following functional blocks:

�

RF dual-modulus prescaler.

�

RF programmable divider.

�

Reference oscillator.

�

Reference programmable divider.

�

Digital phase comparator.

�

In-lock detection circuitry.

�

J2C serial programming interface.

In addition, the device features a power down mode for battery conservation and a XTAL/8 output for use with the Philips cellular radio chipset. The only major external component required is a voltage controlled oscillator (VCO).

This application report presents a design for a frequency synthesizer based on the UMA1014T suitable for the local oscillator for analogue cellular radio applications in the 900 MHz band. A PCB layout is suggested. For detailed device specifications of the UMA1014T refer to the data sheet (Reference 1).

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Application note
SCO/AN91004

2.

FUNCTIONAL DESCRIPTION OF THE UMA1014T

The main functions are illustrated in a Phase Lock Loop (PLL) block diagram (Fig 1). A temperature controlled crystal oscillator (TCXO) provides a reference frequency to the PLL. A phase comparator uses a charge pump to send correction current pulses to a low pass filter. The filter integrates the pulses giving a voltage which controls a VCO. VCO and TCXO o/ps are divided down to a common comparison frequency to control the phase comparator. When the VCO o/p is on frequency the current pulses need only be large enough to cancel leakage currents thus maintaining the required voltage on the VCO.

2.1 Main Divider Chain

The UMA1014T contains a fully programmable main divider chain with an on-chip RF prescaler. The range of the main divider is from 2048 to 262143, thus permitting all useful phase detector comparison frequencies over the full range ofinput frequencies.

2.2 Reference Divider Chain

Since current analogue systems have only a few different channel spacings, and in any system there is a restricted choice of reference crystal frequencies, the UMA1014T implements a reference divider with limited programmability. A total of 16 different division ratios can be selected which enables all the required phase detector comparison frequencies to be generated. These ratios are 128, 160, 192, 240, 256, 320, 384, 480, 512, 640, 768, 960, 1024, 1280, 1536 and 1920.

In addition, there is one eighth of the crystal frequency available on an output for use with the Philips cellular radio chipset. This chipset uses a 1.2 MHz clock for the analogue and digital baseband circuits which is provided by the frequency synthesizer; the synthesizer thus requires the use of a 9.6 MHz crystal in this application.

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Application note
SCO/AN91004

2.3 Phase Detector

There are three requirements for the phase detector; firstly it should cover the full 360 degree phase range, secondly it should have good noise performance, and thirdly it should have good comparison frequency suppression. In order to meet these requirements, the use of a high gain digital phase comparator is beneficial. The comparator covers the complete phase range while introducing little noise owing to the high proportion of time that is spent in a high impedance state. Good reference rejection is achieved due to low leakage currents.

2.3.1 Digital Phase Comparator

The Digital Phase Comparator (PCD) has three states, sinking current, sourcing current and a high impedance tristate. The design is based on D type flip-flops and responds to the full 360 degree range of phase inputs. The D type flip-flops control two current sources arranged in a push pull configuration. PCD delivers a constant current while the main and reference dividers are out of phase, either sinking or sourcing (Fig 2). The current IPCD is programmed via the I2C interface to be either 1 mA or 0.5 mA. The phase comparator gain is hence:

PCD gain = -IPC-D A I rad

(1)

2xn

The phase comparator circuit incorporates a delay which eliminates a dead band that would otherwise be present in digital phase comparators. Dead bands are due to the finite time the current sources take to switch on. The design of the UMA1014T takes this into account by introducing the delay into the D type reset line. This gives the current sources enough time to respond. Both current sources are switched on for the duration of the delay thus cancelling each other at PCD.

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3.

INTERFACING TO THE UMA1014T

Application note
SCO/AN91004

The UMA1014T provides two way communication to a controller, power down facility, programmable o/p ports, oscillator circuitry and PLL control. The UMA1014T is designed to have the minimum of external components to enable low cost, compact and reliable circuits.

3.1 Programming the UMA1014T

The UMA1014T is programmed via the Philips Standard I2C bus. To program information into the device registers, it is necessary to transmit first the device address, then the sub-address, and finally the data bytes for the register(s) (Reference 2). To read the status register, it is only necessary to transmit the address before reading back the value of the status register. When writing to the UMA1014T the sub-address allows writing to any single register, or a burst mode where all registers can be written in one I2C transfer. The formats are thus:

Write to one register:
START- address- sub-address- data - STOP
!__contains register number to be accessed
__R/WN (read/write not) bit set to 0 (write)

Write to several registers:
START- address- sub-address- data 1- ... - data n - STOP
I__ contains first register number to be
accessed in the sequence and autoincrement enabled __R/WN bit set to 0 (write)

Read from status register:

April 12, 1991

START- address- status- STOP
l__R/WN bit set to 1 (read)
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Application note
SCO/AN91004

The address byte, in addition to containing the RJWN bit as shown above, has one bit that reflects the inverse of the SAA pin logic level. This allows the addressing of up to two synthesizer circuits on the same I2C bus.

The format for the address bus is as follows:
1 1 0 0 0 1 SAANRJWN
l__o (write), 1 (read)
_opposite logic level to that of SAA pin
__MSB of device address, transmitted first after START condition

The sub-address has the following format: (X means not used)
X X X DI AVI X SBl SBO
l__l__register pointer
__auto-increment- 0 (disable), 1 (enable)
__SYA interrupt- 1 (disable), 0 (enable)

The status register relates to the alarm of the ciruit as follows:
I I I I I I I I I o o o ooL o LooL LPD DI ~~ieeb~~~ii.

OOL Momentarily out oflock, LOOL Latched out oflock <tl,

LPD Latched power dip (t),

DI Interupt disabled on SYA,

(t) Reading status register clears these if the error condition has been

removed.

Data is formatted as a series of registers as follows:

Reg/

If>
m

V>
o>

ister - 0

Bit Allocation

Preset

7

6

5

4

3

2

1

0

A 00 PD

x 0 IPCD

RD3 RD2 RDl RDO 00001110

B 01 1

0

1 PHI VCOB VCOA MD17 MD16 10101001

c 10 MD15 MD14 MD13 M012 MDll MOlO M09 MOS 00111000

April 12, 1991

D 11 M07 M06 M05 M04 M03 M02 MDI MOO 10000000
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Signetics RF Communications
Application report for the UMA1014T frequency synthesizer

Application note
SCO/AN91004

Register map bit polarities:

PD IPCD RD3 ..0 PHI VCOA VCOB MD17 ..0

0

1

Normal operation Current in PCD = 0.5 mA

Power down
PCD = lmA

Reference divider ratio MSB = RD3

Passive loop (no inversion)

Active loop (Phase inversion)

Set pin 7 low

Set pin 7 high

Set pin 13 low

Set pin 13 high

MaindividerratioMSB = MD17

RD3 ..RDO reference divider programming:

RD3

RD2

RDl

RDO Reference Division Ratio

0

0

0

0

0

0

0

1

0

0

1

0

0

0

1

1

0

1

0

0

0

1

0

1

0

1

1

0

0

1

1

1

1

0

0

0

1

0

0

1

1

0

1

0

1

0

1

1

1

1

0

0

1

1

0

1

1

1

1

0

1

1

1

1

128 160 192 240 256 320 384 480 512 640 768 960 1024 1280 1536 1920

April 12, 1991

MDl 7..MDO main divider value 2048 to 262143 (hex $800 to $3fffl).
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3.2 Hardware Control Inputs and Outputs

Application note
SCO/AN91004

There are a number of status and control signals generated by the UMA1014T and also a hardware control input.

3.2.1 HPD Input

This input is used to disable the divider chains in order to save power when the synthesizer is not required to be operational. The power down state can be activated either by taking this pin low or by setting the power down bit in the I2C register to a '1'. The input has an internal pull-up resistor so that normal operation will be obtained ifthe pin is left open circuit.

The power down state does not have any effect on the I2C circuitry, so that the device may still be addressed, and new information programmed into the registers even in the power down mode.
3.2.2 FX8 Output

This is an open collector output of one eighth of the crystal or TCXO input frequency. It is required for use with the Philips cellular radio chipset for AMPS and TACS systems; in this application the synthesizer should be used with a 9.6 MHz TCXO. The recommended pull-up load is 27 k Ohm.

3.2.3 SYA (Synthesizer Alarm) Output

This is an open collector output which is normally held high by an external 27 k Ohm load. Under error conditions, the synthesizer latches SYA low. The error conditions that set SYA low are a power dip or an out-of-lock condition. A power dip occurs when VCC supply falls below about 3.5 V. SYA is reset again by reading the status register, which contains the relevant alarm information. The SYA output can also be enabled and disabled via I2C as required.

The typical use of SYA would be to interrupt a microcontroller to warn of

the error condition. As the output is open collector, it is possible to connect

more than one device together directly; in this case the microcontroller

would poll the relevant devices to locate the source of the error condition.

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3.2.4 VCOO and VCOl Outputs

Application note
SCO/AN91004

These are open collector outputs and are intended for enabling the power supply to VCOs or buffer stages so that these parts of the set can be powered down when not required to be operational. The outputs are controlled via I2C. In addition, the VCOO output is forced low during an out-of-lock condition; this output could therefore be used to disable the transmitter when this condition occurs to prevent causing interference. In this case, there may well he other parts of the circuitry also controlling the transmitter in the same way; as the VCOO and VCOl lines are open collector, they may be directly connected to other such controlling signals.

The VCOl output is not affected by the hardware power down input or power down via I2C. The VCOO output will of course be forced low due to the out-of-lock condition resulting from a power down.

3.3 Crystal Oscillator

For analogue cellular radio applications, the UMA1014T will almost certainly be used with an external oscillator in order to provide the stability necessary to ensure operation within the specification. However, in case some other applications do not require such accuracy, provision has been made to form a crystal oscillator using the OSCIN and OSCOUT inputs (pins 1 and 2 respectively). The oscillator circuit should he of the Colpitts type and requires the addition of four capacitors to function. This is shown in Fig 3, with capacitor values suitable for operation at 9.6 MHz.

The internal biasing provides possible operation over the range 3 MHz to 16 MHz with tlie addition of a suitable crystal. It may be necessary to adjust the values of the capacitors slightly to guarantee oscillation under all conditions for frequencies significantly different to 9.6 MHz.

The crystal used in this circuit is parallel resonant, fundamental mode, with a load capacitance of 30 pF which is approximately the series combination of the three fixed capacitors in parallel with the trimmer capacitor.

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3.4 External Oscillator

Application note
SCO/AN91004

When using an external oscillator such as a TCXO module, the output from the oscillator should be connected directly to the OSCin pin (pin 1). The OSCout pin (pin 2) should either be left open circuit, or could be used as a buffered version of the signal applied to OSCin.

3.5 RF Connection to Main Divider

The output from the VCO needs to be split between the synthesizer RF o/p and the UMA1014T main divider input. A matched splitter is used as shown in Fig 4. Ideally, the splitter should provide maximum isolation to the VCO to prevent pulling or modulation due to changes in the load impedance at the RF o/p and main divider input. The amount of isolation is limited by the required RF output power and the main divider input sensitivity. Emphasis is placed on the importance of providing sufficient isolation between the VCO and the main divider to keep spurious modulations at a minimum level.

3.6 Loop Filter Design

The correct design of the loop filter is of considerable importance to the optimum performance of the synthesizer. The filter should be designed so as to achieve the required compromise between noise performance and switching time. The actual circuit will therefore depend on the particular application. A procedure has been established to ensure quick and simple loop filter design. The method, based on first order approximations, provides a working solution without a need for computer simulation and modelling.

Design Procedure

For typical applications a passive loop is used thus removing the need for an operational amplifier. The following design is based on a second order low pass filter (Reference 3). Then, for applications requiring further reference breakthrough rejection, a third order is incorporated. The third order loop filter is used for circuits and measurements in this report.

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Application report for the UMA 1014T frequency synthesizer

Application note
SCO/AN91004

Loop parameters are first chosen, these are:

�

Radio frequency

RF

�

Comparison frequency

CF

�

Switching time

St

�

Minimum modulating frequency MF

�

VCO gain rad/Volt

Ko

�

Phase comparator gain Amps/rad Kd

�

Phase margin

<P

Determine the loop bandwidth Fn from

3

-----=Fn

(2)

switching time

Determine main divider ratio N from

N = RF I CF

(3)

Determine angular velocity wn rads Is from wn = 2 x n x Fn

The loop filter circuit (Fig 5) has three time constants, these are:

�

Tl= C3xR2

(4)

�

T2 = R2 x Cl x C3/(C3 + C4)

(5)

�

T3 = C2xRl

(6)

The second order loop is designed by omitting Rl and C2 (T3) and uses the equations below:

I

T2 = - - -Tan <P

(7)

COS<t>

wn

TI=1/(wn 2 xT2)

(8)

j l + (wn xT1) 2

C3 +CI = K

2

(9)

I+ (wn xT2)

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KdxKo whereK= - - -
Nxwn2

Application note
SCO/AN91004
(10)

T2x(C3 +CI) CI=-----
TI C3 = CC3 + Cl) - CI

(11)
I
I"
(12)

R2 =TI /C3

(13)

Measuring the reference spurs and comparing with a particular specification establishes ifa third order is necessary.

If a further 'A' dB of breakthrough suppression is needed to meet specification, then T3 is included to make a third order filter. Note 'A'
should not be so large that T3 x 10 > Tl. A good starting value for 'A' is
20dB.

=Ji( T3

10<A/20> - I )'

(14)

(2 xnxFc) 2

T2 determines the loop stability and remains the same as for 2nd order loop.

A calculated value of closed loop bandwidth wnc is used. This is usually slightly less than wn so the switching time will be slightly longer than originally specified.

(Jil+ wnc= (T2+T3) xtan<t>x

4xT2 2

-I )

(15)

T2 2

(2xtan<t>x(T2 + T3)) 2

I

TI=------

(16)

wnc2x (T2 + T3)

j

I+ (wncxT1) 2

C3 +CI= K -

(17)

(1 - wnc 2 xT2xT3) 2 + -T3-+T-2

7'I

April 12, 1991

728

Signetics RF Communications
Application report for the UMA 1014T frequency synthesizer
KoxKd whereK= - - -
Nxwnc2

Application note
SCO/AN91004
(18)

(C3 + Cl)xT2

Cl=

(19)

Tl

C3 = (C3 +Cl) - Cl

(20)

C2 =Cl 116

(21)

R2 = Tl/C3

(22)

Rl=T3/C2

(23)

For a successful filter it is important that C3 > > Cl and Cl > > C2.

3.6.1 Worked Example

As an example the design of the third order loop filter for the UMA1014T under the following conditions is shown below. This design on the PCAL1143-l board suitable for ETACS transmit application. Switching time is set sightly shorter than expected to compensate for the reduction in the final loop bandwidth Fnc.

April 12, 1991

VCO frequency

VCO gain

Ko

Channel spacing

Reference oscillator

Switching time

Min mod frequency

Phase margin(degrees)

Additional reference

Rejection

A

888 MHz 13 MHz/V 25 kHz (with half channel offset) 9.6MHz
12 ms (for a requirement < 14 ms)
300Hz 45
20dB

729

Signetics RF Communications
Application report for the UMA1014T frequency synthesizer

Application note
SCO/AN91004

In this example the phase comparator gain Kd chosen is 1 mA I cycle as opposed to 0.5 mA I cycle. In open environments a loop based on this is less susceptible to interference as capacitor values are higher. A comparison frequency of 12.5 kHz is chosen to allow for the half channel offset specified inETACS.

The first order loop bandwidth Fn:
3 - - - = 250 Hz wn = 2 x nxFn = 1570 rads/ s 12xI0 3

Use (2)

The main divider ratio N:

888 x IO 6 12.5x103 = 71040

Use (3)

T2 = -1- - tan 45 = 2.64x10 - 4 cos 45 1570

A 1020'20-1 )

5

T3= \

=3.82x10-

(2xnx 12500) 2

Use (7) Use (14)

(2.64xlo- 4 + 3.82xl0-5 )xtan 45

wnc=

x

(2.64x10- 4 ) 2

(Ji1 +

4x(2.64x10 - 4 ) 2

-

)
1

=

1421

(2xtan 45x (2.64xl0- 4 + 3.82x10 - 5 )) 2

Use (15)

April 12, 1991

Tl

1

=1.64xl0- 3

1421 2 x(2.64xl0- 4 + 3.82xl0-5 )

730

(Use (16)

Signetics RF Communications
Application report for the UMA 1014T frequency synthesizer

Application note
SCO/AN91004

13x10 6 xl0 - 3

K=

=9.04xI0- 8

71040x1421 2

Use (18)

j Cl + C3 = K

1+(142lxl.64xl0-3 ) 2 ----------------------

(1 -

1421

2

4
x2.64xl0-

x

3.82

5 2
-)

+

-3.8-2 x-10-- 5-+ -2.-64 -- 4

1.64 x 10- 3

=2.14xl0- 7

Use (17)

Cl= 2.14xl0-7 x2.64xl0- 4 = 3.45xl0 - 8 1.64xl0- 3

Use (19)

C3 = 2.14xl0- 7 - 3.45xl0- 8 = 1.8xl0 - 7

Use (20)

C2 = 3.45xl0- 8 /16 = 2.15xl0- 9

Use (21)

R2=1.64x10- 3 /l.8x10 - 7 = 9111

Use (22)

RI= 3.82xl0-5 I 2.15xI0- 9 = 17767

Check C2 < < Cl < < C3.

Values chosen for filter components are:

Cl= 33 nF
C2 = 2.2 nF
C3 = 180 nF

Rl = 18 kOhms
R2 = 10 kOhms

Use(23)

April 12, 1991

731

Signetics RF Communications
Application report for the UMA 1014T frequency synthesizer

Application note
SCO/AN91004

3.7 PCB Layout Considerations
The circuit of the UMA1014T demonstration board (PCAL1143-l) is shown in Fig 6, with the layout shown in Fig 7. This PCB has a solid ground plane on one side (apart from isolated pads for non-grounded connections to leaded components). In addition, there are areas of ground plane on the surface mount side of the board to ensure satisfactory grounding of important components. There are a good number of plated-through holes connecting the two layers of ground plane. Normal RF design practices should of course be taken into account when laying out the circuit.
There are a number of particular points that should be borne in mind when considering the circuit and layout.

�

The non-surface mount side of the board (if a 2 sided board

is used) should be virtually solid ground plane to give good

RF performance.

�

The 5 V digital supply (VCC) should be well decoupled as

close to the pin as possible, preferably with a large value

capacitor (eg: 47 uF) and in series with a small value

resistor (eg: 12 Ohms) from the 5 V line.

�

The 5 V charge pump supply (VCP) should be decoupled

separately from VCC but in a similar manner. Routing the

5 V supply under the IC is to be avoided.

�

Incorporating a ground plane on the surface mount side of

the PCB underneath the synthesizer helps isolate digital

noise from the charge pump parts. This ground plane

should be well connected with vias to the full ground plane.

April 12, 1991

732

Signetics RF Communications
Application report for the UMA1014T frequency synthesizer

Application note
SCO/AN91004

4.

TYPICAL PERFORMANCE_

This section describes the typical performance obtainable with the UMA1014T with the circuit shown in Fig 6 and parameters listed in 3.6.1. The relevant performance criteria for a synthesizer are usually:

Close-in phase noise (ie: noise within the loop bandwidth).

Noise floor at an offset from the carrier.

Comparis@n breakthrough components.

Switching time.

It should be noted of course that these criteria can be traded off against each other to some extent to tailor the overall performance, and that the performance described here is only one compromise between the various criteria. In general, the choice of a low loop bandwidth will improve the comparison frequency breakthrough and will filter out more of the close-in phase noise, but will result in a longer switching time. The use of a higher order filter can improve comparison frequency breakthrough with little effect on the noise or switching time. The noise floor at offsets significantly higher than the loop bandwidth are determined completely by the VCO itself.

Plots of the close-in spectrum (span of 2 kHz) and also a span of 50 kHz are shown in Figs 8 and 9 respectively for a carrier frequency of 888 MHz and a comparison frequency of 12.5 kHz. From Fig 8 we can see from the noise plateau that the loop bandwidth is around 270 Hz, and Fig 9 shows the spectrum analyser noise floor at offsets greater than about 15 kHz from the carrier with the first and second comparison frequency breakthrough component being visible at 12.5 kHz and 25 kHz from the carrier respectively.

April 12, 1991

733

Signetics RF Communications
Application report for the UMA 1014T frequency synthesizer

Application note
SCO/AN91004

Figure 10 shows switching waveforms for a frequency jump of 10 MHz. The top trace (labelled CHI) is the I2C transfer to the UMA1014T; the second CCH2) is the VCO control line. The third trace (CH3) is the VCOA output showing the out-of-lock condition. The fourth trace (CH4) is the RF output of the VCO mixed down to 0 Hz with a signal generator at the destination frequency. The VCO output is coupled to the mixer via an amplifier with 17 dB gain followed by a 10 dB attenuator. This is to provide isolation to the VCO from the mixer.

The mixer output trace shows that the switching time is 13 m seconds, which is a little longer than the VCO control line trace appears to show. This is because observation of the VCO control line is not accurate due to the very high VCO gain (13 MHz IV).

From Fig 10, we can see that the VCO control line has a single overshoot during switching; this shows that the loop is properly damped, so the phase margin is correct.

To summarise the performance of the circuit in Fig 6:

loop bandwidth

270Hz

close-in noise

- 55 dBc I Hz at 200 Hz from carrier

VCO noise floor

- 113 dBc I Hz at 25 kHz from carrier

residual fm

< 18 Hz rms, CCITT weighted

comparison frequency breakthrough - 65 dBc at 12.5 kHz - 82 dBc at 25 kHz

typical switching time

< 13 m seconds for 10 MHz jump to
within 1 kHz of the destination frequency

April 12, 1991

734

Signetics RF Communications
Application report for the UMA 1014T frequency synthesizer

Application note
SCO/AN91004

5.

CONCLUSIONS

Information regarding the use of the UMA1014T in a frequency synthesizer application has been presented. A methodology for determining the loop filter components has been described since the switching and noise performance of the complete circuit depends on a good filter design. The layout of the PCAL1143-1 demonstration board has been shown as an example PCB layout.

6.

REFERENCES

1.

UMA1014T, Initial Specification Data Sheet, September 1990.

2.

N MW Oatley;

Application Information for the UMA1010T/UMA1012T,

Philips Components Application Report MC090001.

3.

Ulriche, L Rhode;

Digital PLL Frequency Synthesizers Theory and Design.

28/3/91.

April 12, 1991

735

Signetics RF Communications
Application report for the UMA1014T frequency synthesizer

Application note
SCO/AN91004

Low pass filter

Voltage contro 11 ed oscillator

R.F. Output

TCXO
Fig 1 PLL Circuit Block Diagram

April 12, 1991

736

Signetics RF Communications
Application report for the UMA 1014T frequency synthesizer

Application note
SCO/AN91004

_J ~ ~

~

I
~ ~

mA

n

-011J

D
R

Pese

Main R

ol

D

DTYPE

Delay

Reference (jiviijer output

fl I
n ~

Marn (jivi1jer output
Sourcing charge pump
Sinking charge pump
PCD output current

+S \/

Sourcing charge pump

PCD output

Sinking charge pump

April 12, 1991

Fig 2 Digital Phase Comparator Operation
737

Signetics RF Communications
Application report for the UMA 1014T frequency synthesizer

Application note
SCO/AN91004

C13
120p

__.._(12
68p

C8 2-20p

~.6f'G�11Hz

TC
_

11
39p

Fig3 Crystal Oscillator Circuit Diagram

April 12, 1991

738

Signelics RF Communications
Application report for the UMA1014T frequency synthesizer

Application note
SCO/AN91004

R.F. Synthesiser
output
�

18R

~L__r----L.:.:J~...-~~1-----

18 R

18R

1nF

vco

56R
1

Fig 4 RF Power Splitter Circuit Diagram

April 12, 1991

739

Signetics RF Communications
Application report for the UMA1014T frequency synthesizer

Application note
SCO/AN91004

C2

R1

2n2

18K

C3

C1

33n

R2 10K

-

--==-

vco
888MHz 13MHz/V
Fig 5 Loop Filter Circuit Diagram

April 12, 1991

740

~
2:
~
~
vcc vcc

vcc
+6v
lVO l----9---' C14 100n

vcc

vcc vcc
C13

A7 12r
AB 12r

CB 2-20p

9.6MHZ
en
D Cll 39

A9 3K9

~~~11~~u

A
DMA1014

~

C6 to

vcc
R3 12r

l �1~r~ Al 1B1< C2 2n2

l47U!.. c~

XIO

~-----<B

~----1

RS !Sr

R11 !16r

~C7 ~~A

H p

18r

18r

rh c~

Fig6 Frequency Synthesizer Circuit using the UMA1014T

rn )> ~5

'< "'C g�

:::J "'C
st=

.~.

CrnD I0�

o
o

-N� O!:t. 33

....CD :::J � ~-

..g CD
"'C 0

::::i.

.0...

....+
::::1' CD

c

3:
.)..>....

.0......

-~
--f CD
.c.0:
CD :::J
~

en

~

z
<...O....
0 0

~
'2.
gEi'

~ i

Signetics RF Communications
Application report for the UMA1014T frequency synthesizer

Application note
SCO/AN91004

D

S::LJ

EX

~~R~ V2 n

Vl iU

w

Ol

~ I\)

7
J-EW JAJ9 l012 ~nOJ

April 12, 1991

Fig 7 Board Layout for UMA1014T Frequency Synthesizer
742

Signetics RF Communications
Application report for the UMA1014T frequency synthesizer

Application note
SCO/AN91004

UMA1014T ETACS TX IPCD-1mA

hp REF -4.5 dBm

ATTEN 10 dB

10 dB/

SAMPLE

MKR 888.000250 MHz -57.30 dBm (1 Hz)

l_

VID AVG 10

~ ~

J~.I.. ~.:~JI
T' "''If'" '"1 .,..,

~1rr

__._

~..lul.1-.. ft"'" ' .,,

_....J .d1
21',.'_!

~L

_::l

I

~ ~~~ -I

I'I'" .....,.""

CENTER 888.000000 MHz RES BW 10 Hz

VBW 10 Hz

SPAN 2.121121121 kHz SWP 50 sec

Fig 8 Typical Carrier Spectrum - 2 kHz Span

April 12, 1991

743

Signetics RF Communications
Application report for the UMA1014T frequency synthesizer

UMA112114T ETACS TX IPCD-1mA

fp REF -5.6 dBm

ATTEN 1121 dB

1121 dB/

SAMPLE

Application note
SCO/AN91004
MKR A 12.1121 kHz -64.6121 dB '
I'

1 VID 1121

AVG ""

I

l \

~

~-�" ...., l ...,., il..i...J...........i..4.Lu.... ....J......

, � .L

::.r u:

. ..... ��..Jl..l ul..Lll.ad �-.Jt.L.-. ~...........A....

'

T

CENTER 888.121225121 MHz RES BW 1121121 Hz

VBW 1121121 Hz

SPAN 5121 .121121 kHz SWP 1121 sec

Fig 9 Typical Carrier Spectrum - 50 kHz Span

April12,1991

744

Signetics RF Communications
Application report for the UMA1014T frequency synthesizer

Application note
SCO/AN91004

Chi SCL
Ch2 VCO Control

, ..

Switching time 13ms
--1

/_.........___
.....__ ���-.�-~.--=:---~.;.:.-.---=-�- ��__:,.__:__-_�--�--~---��--�------�-

Ch3 OOL Mixed to D.C.

\ ';..~~.':!:..~::.;:.

Fig 10 Typical Switching Waveforms

April12, 1991

745

Slgnetlca RF Communication�

Prellmlnary specification

Low power frequency synthesizer for radio communication UMF1009T

GENERAL DESCRIPTION
The UMF1009T is a low-power, high performance dual modulus frequency synthesizer designed in CMOS technology. :rhe device is designed for use in channelled VHF/UHF applications, especially portable and mobile radios. The synthesizer is programmed via the standard two-line serial 12C-bus.
FEATURES
� On-chip sample-and-hold capacitor
� Low power consumption � High gain phase comparator with
low levels of noise and low level spurious outputs

� Digital phase comparator for fast locking
� On-chip crystal oscillator from 2.4 to 16.8 MHz; circuit can be used with a crystal or a tuned-circuit TCXO
� A large reference frequency range at the phase detector (binary 15-bit programmable reference counter)
� In-lock detector open-drain output

� 1.2 MHz output for easy interface to the other cellular radio chip set devices
� Single supply voltage (2.7 to 5.5 V).

ORDERING INFORMATION

I T T EXTENDED

PACKAGE

TYPE NUMBER PINS PIN POSITION MATERIAL

CODE

UMF1009T

T 16

S016

Tplastic

TSOT109A

QUICK REFERENCE DATA

SYMBOL

PARAMETER

Supply voltage range

Vooo VooA

supply voltage digital supply voltage analog

Operating current

looo

digital

looA

analog

Frequency range

ft

input frequency

fosc

crystal frequency range

Temperature

Tamb

operating ambient temperature range

CONDITIONS
Voo=5V Voo=3V Voo=5V Voo=3V
Voo=5V Voo=3V Voo=5V Voo=3V

MIN.
2.7 2.7
----
0 0 2.4 '2.4
-40

TYP.
-
-
-
---
-

MAX.

UNIT

5.5

v

5.5

v

1.5

mA

0.8

mA

1.0

mA

0.6

mA

18.0 8.0 16.8 8.0

MHz MHz MHz MHz

+85

oc

Februmy 1991

746

Signelics RF Communications
Low power frequency synthesizer for radio communication

Preliminary specification
UMF1009T

5-BIT LATCH
n2/n2+1+ DIVIDER n2= 1to127

FB 9
AO 11 A1 12 SDA 13 SCL 14

12c-0us
INTERFACE

Vss

Vooo

10

15

UMF1009T

PHASE DETECTOR

1 PCA 16 RA

IN-LOCK DETECTOR

3 IL

PHASE COMPARATOR

2 PCD

n4 DIVIDER n4 = 1 to 7
XTAL

n3 DIVIDER n3 = 1210 4095

7 F12
MLA214-f

February 1991

Fig.1 Block diagram. 747

Signetics RF Communications
Low power frequency synthesizer for radio communication

Preliminary specification
UMF1009T

PCA~RA

~ PCD

~ VooA

14 SCL

UMF1009T

SDA A1

AO

Vooo

MLA213-1
Fig.2 Pin configuration.

PINNING

PCA PCD IL

SYMBOL

Vss DIVref XTAL F12 DIV1 FB

Vooo AO A1 SDA SCL

VooA RA

PIN

DESCRIPTION

1

analog phase detector output

2

digital phase detector output

3

in-lock detector output (HIGH when in lock)

4

ground

5

refer~nce divider input

6

output to external crystal

7

1.2 MHz output

8

main divider input from prescaler

9

feedback output for prescaler modulus control

10

digital supply; 2.7 to 5.5 V

11

address input O

12

address input 1

13

serial data input/output

14

serial clock input

15

analog supply; 2.7 to 5.5 V

16

PCA gain setting resistor

February 1991

748

Signetics RF Communications
Low power frequency synthesizer for radio communication

Preliminary specification
UMF1009T

FUNCTIONAL DESCRIPTION
Figure 1 shows the functional block diagram of the UMF1009T. The main divider, reference divider, phase detectors and the 12c-bus interface are described in the subsequent sections.
Main divider
The main divider is a rate-feedback binary type comprising a fixed 7-bit binary divider and two rate selectors n1 and no. One rate selector controls a 7-bit fully programmable dual
modulus divider (n2/n2 + 1), and the
other controls an external dual modulus prescaler (A/A+ 1). The total division ratio is given by:

= N (128.n2 + n1)� A+ no
Where:
o :5 nO :5127, O:5 n1 :5127 and 1 :5 n2 :5127
Thus if the division ratio is expressed as a binary number and A is chosen to be 128, then the no rate selector will contain the least significant bits, the n1 selector the next 7 bits and the n2 divider the most significant 7 bits. If A is chosen to be a lower power of 2, then the number of bits of the no divider that require programming can be reduced. For example, if A= 32, then only 5 bits of no need to be programmed and the most

significant 2 bits can remain at zero while still retaining full programmability. If the most significant bits of no are used in this situation, then several combinations of values for the no, n1 and n2 counters will give the same division ratio.
The output from the programmable divider is fed to the phase detectors.

February 1991

A/A+1

CLK

TC

MOD

DIV1:

'----..----' I

n2 I n2 + 1

CLK

TC

MOD

+ 128

CLK

TC

~--_...___, n1 SELECTOR

UMF1009T FB

nOSELECTOR

MLA215

Fig.3 Main divider structure.
749

Signetics RF Communications
Low power frequency synthesizer for radio communication

Preliminary specification
UMF1009T

Reference divider

If the 1.2 MHz output is not required, both a good noise performance and

The reference oscillator chain

then the n4 divider can be

fast frequency locking over a large

comprises a crystal oscillator and

programmed to any suitable value.

range. Phase detector 1 (PCA) is the

dividers to produce the required

Setting n4 = 1 will give access to the main analog detector. It is designed

frequency to drive the phase

fully programmable n3 reference

to have a high gain, typically

detectors. The oscillator stage is a simple inverter connected between

divider without any fixed division. The n3 divider is fully programmable over

5x 1012 x(Vooo-0.7)

R fDIV

V/Cycle

AX

(ref)

I
1�

pin 6 ()ITAL) and pin 5 (DIVret).

the range 12 to 4095 to allow

thus enabling low noise operation to

Satisfactory operation is achieved

complete flexibility in the choice of

be achieved. Phase comparator 2

using a crystal up to 16.8 MHz

input frequency to the DIVref pin for

(PCD) is a digital phase comparator

(Voo = 4.5 V), (up to 8 MHz Voo = 2.7 V). the required reference frequency.

with a linear 2n: radians phase

Alternatively, the DIVref input may be used as a buffer amplifier for an external reference oscillator.

The total reference division is given
by: N =n3 x n4

range corresponding to a gain of Voorf2 V/cycle.

In order to avoid degrading the noise

The reference divider contains two sections; the first divider section is programmed to divide by a suitable ratio to give the correct 1.2 MHz

Where:
12 ::;; n3 ::;; 4095 (FFF hex) 1::;; n4::;; 7

performance of PCA, once a small phase error has been achieved, an internal switch is used to disconnect PCD.

output frequency. The second divider

section will now operate at 2.4 MHz and is fully programmable. Thus the input frequency at DIVref can be any of the frequencies given in Table 1.

Phase detectors
There are two phase detectors which work in close co-operation to provide

PCA phase detector
The analog phase detector consists of a linear ramp generator and a sample-and-hold circuit. At the

Table 1 DIVref input frequencies

n4

DIVref input for

1.2 MHz output

1

2.4 MHz

2

4.8 MHz

3

7.2 MHz

n3 for reference frequency

12.5 kHz 192 192 192

15 kHz 160 160 160

beginning of the reference cycle an internal capacitor is charged from a constant current source to give the linear ramp. The output voltage from the capacitor is buffered by a voltage follower. When both the main and reference divider outputs are in phase, the ramp is terminated. After

4

9.6 MHz

192

160

a short delay, to allow the voltage

5

12.0 MHz

192

160

follower to settle, the follower output

6

14.4 MHz

192

160

is sampled and held by a second

7

16.8 MHz

192

160

internal capacitor. This is buffered and routed to the PCA output pin.

After the sample has been acquired,

the first capacitor is discharged by a

n4 TC

2 TC

F1.2

constant current sink to provide a controlled discharge, thus minimizing

the disturbance to the sample-and-

hold circuit.

n3 TC

reference
MLA216

If the linear ramp approaches the value of the analog supply rail and

Fig.4 Reference divider str~cture.

February 1991

750

Signellcs RF Communications
Low power frequency synthesizer for radio communication

Preliminary spec:ffication
UMF1009T

the two divider outputs are not in phase, then the digital phase comparator PCD will be enabled and an out-.of-lock error will be indicated as a LOW state on the open drain output IL (pin 3).
To allow for more flexibility in the design of the loop dynamics, the gain of PCA is controlled by a variable resistor connected between RA and Vss. This resistor controls a current

source via a current mirror; a typical value for the resistor is 470 kn.
PCD phase comparator
The output of the PCD is a series of positive (Voo) or negative (Vss) voltage pulses with variable width which is dependent on the phase relationship of the main and reference divider outputs. During the time the two outputs are in pliase,

the output from PCD is in a high impedance state. If PCA is in its operating range then PCD is disabled. The enable signal for PCD is inverted and routed to the IL pin so that when PCD is enabled, pin IL is pulled LOW.

LIMITING VALUES

In accordance with the Absolute Maximum System (IEC 134)

SYMBOL VooA Vooo V1 Vooo-VooA 11 Ptot Po Ts!li Tamb

PARAMETER supply voltage (analog) supply voltage (digital) voltage on any input relative supply voltage DC current into any input or output total power dissipation per package power dissipation per output storage temperature range operating ambient temperature range

CONDITIONS Tamb = 0 to +85 �C

MIN.
-0.5
-0.5
-0.5
-
-10
-
-65
-40

MAX. 6.5 6.5 Vooo+0.5 0.5 +10 400 100 +150 +85

UNIT
v v v v
mA
mW
mW
oc oc

February 1991

751

Signellcs RF Communications
Low power frequency synthesizer for radio communication

Preliminary speclficalion
UMF1009T

DC CHARACTERISTICS

Tamb = -40 to +85 �C; unless otherwise specified

SYMBOL

PARAMETER

Supply voltage

VooA Vooo

analog supply digital supply

Supply current (note 1)

looA

analog supply

looo

digital supply

Logic
V1L V1H VoL VoH VoL

input voltage LOW input voltage HIGH CMOS output voltage LOW CMOS output voltage HIGH output voltage LOW (IL, PCD and F12)

VoL

SDA output voltage LOW

VoH

output voltage HIGH

(PCD, FB and F12)

IL

leakage current

PCD 3-state mode

CMOS inputs/outputs

Analog output current (pin 1)

Isink

sink current

Isource

source current

Operating voltage range (pin 1) VpcAL operating voltage LOW
VpcAH operating voltage HIGH

Input capacitance

C1

DIV1 and DIVret (pins 5 and 8)

all other inputs

CONDITIONS
Voo=5V Voo=3V Voo=5V Voo=3V
lo< 1 �A lo< 1 �A Voo = 4.5 V; loL=2mA Voo= 2.7 V; loL=1 mA Voo= 4.5 V; loL=3mA Voo= 2.7 V; loL= 1.5 mA Voo =4.5 V; -loL= 2 mA Voo = 2.7 V; -loL= 1 mA
Voo = 4.5 V; VpcA= Vooo Voo = 2.7 V; VpcA= Vooo VpcA=Vss; Voo =4.5 V VpcA=Vss; Voo= 2.7 V
Voo = 4.5 V; lpcA= 0 Voo = 2.7 V; IPCA= 0 Voo = 4.5 V; IPcA= 0 Voo = 2.7 V; IPCA= 0

MIN.

TYP.

2.7 2.7

--

--

--

-

-

-

-

-0.5

-

0.7Vooo -

-

-

- Vooo-0.05

-

-

-

-

-

-

-

-

- Vooo-0.5

- Vooo-0.5

MAX.
5.5 5.5
1 0.6 1.5 0.8
0.3 Vooo Vooo+0.5 50
-
0.4
0.4
0.4
0.4
-
-

UNIT
v v
mA mA mA mA
v v
mV
v v v v v v v

-

-

50

nA

-

-

100

nA

1

-

-

mA

0.5

-

-

mA

-1

-

-

mA

-0.5

-

-

mA

2

-

-

v

0.5

-

-

v

-

-

3

v

-

-

1

v

--

-

3

-

�5

pF pF

Note to the DC characteristics

1 Supply current at maximum frequency (DIV1 and DIVret), maximum reference division ratio without any load at the outputs.

February 1991

752

Signetics RF Communications
Low power frequency synthesizer for radio communication

Preliminary specification
UMF1009T

AC CHARACTERISTICS

SYMBOL

PARAMETER

Main programmable divider

foJV(M) input frequency

V1(p-p) tPHL

input signal amplitude (peak-to-peak value) propagation delay (HIGH-to-LOW)

tPLH

propagation delay

(LOW-to-HIGH)

Reference divider foJV(R) input frequency

fret

reference frequency

tH-L

1.2 MHz output (F12)

(HIGH-to-LOW)

12c-bus
fcLK tspike

SDA clock frequency tolerable spike width at SDA andSCL

CONDITIONS
Voo= 5 V Voo = 3 V
DIV1 > FB; CL= 10 pF
Voo = 5 V Voo = 3 V DIV1 > FB; CL= 10 pF
Voo = 5 v Voo = 3 v
Voo = 5 V Voo = 3 V Voo = 5 V Voo = 3 V Voo = 5 V; CL = 10 pF
Voo = 3 V; CL = 10 pF

MIN.

TYP.

MAX. UNIT

0 0

--

0.5

-

18

MHz

8

MHz

-

v

-

17

35

ns

-

40

80

ns

-

17

35

ns

-

40

80

ns

0

-

16

MHz

0

-

8

MHz

-

-

100

kHz

-

-

50

kHz

-

-

40

ns

-

-

90

ns

-

-

100

kHz

-

-

100

ns

CHARACTERISTICS OF THE 12c-bus
The 12c-bus is for 2-way, 2-line communication between different IC modules. The two lines are serial data line (SDA) and serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data

transfer may be initiated only when the bus is not busy.
Bit transfer
One data bit is transferred during each clock pulse. The data SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as�control signals.

February 1991

SDA~===~

ir--\! :,---,

SCL ___}/

"t-----Y

\___

I

\

data line

I

I

I change I

l

stable:

I of data I

I

datavalid

I allowed I

7287019

Fig.5 Bit transfer.
753

Signetics RF Communications
Low power frequency synthesizer for radio communication

Start and stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH, is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (P).

System configuration
A device generating a message is a "transmitter", a device receiving a message is a "receiver". The device that controls the message is the "master" and the devices which are controlled by the master are the "slaves".

Preliminary specification
UMF1009T

SDA --i\'---+i____c.____==~-- SDA

._JI I

I

i s i \__/ SCL --~

; - - - \ ,___

I

I

I :

iPi

SCL

L---~
start condition

L---J stop condition

7287005

Fig.6 Definition of start and stop conditions.

SDA----_..,.-------0-------~------~-----~~
SCL-------1----+----4---+----+---+-----1---+-------1-

MASTER TRANSMITTER/
RECEIVER

SLAVE RECEIVER

SLAVE TRANSMITTER/
RECEIVER

MASTER TRANSMITTER

MASTER TRANSMITTER/
RECEIVER
7287004

Fig.7 System configuration.

February 1991

754

Signetics RF Communications
Low power frequency synthesizer for radio communication

Preliminary specification
UMF1009T

Acknowledge
The number of data bytes transferred between the start and stop conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must

generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse; set up and hold times must also be taken into account.

generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a stop condition.
Timing specifications
Masters generate a bus clock with a maximum frequency of 100 kHz. Detailed timing is shown in Fig.9.

A master receiver must signal an end of data to the transmitter by not

start condition

clock pulse for acknowledgement

SCL FROM MASTER

!

\: _

_

_

F

\

_

_

F

\

_

__

_

_

F

\

_

_

+
F\

_

I

I

~~~/~X~~)(~~)( DATA OUTPUT
BY TRANSMITTER

I

DATA OUTPUT BY RECEIVER

--~
7287007

Fig.8 Acknowledgement on the 12C-bus.

SDA SCL SDA
7287013.2
February 1991

---+- t LOW ..__
1SU;STA
Fig.9 Timing. 755

'su;STO

Signetics RF Communications
Low power frequency synthesizer for radio communication

Preliminary specification
UMF1009T

Where:

tsuF

t ~ tLOw (min) the minimum time the bus must be free

before a new transmission can start

tHD; STA

t ~ tHIGH (min) start condition hold time

I

I"

tLOW(min)

4.7 �s

clock LOW period

tHIGH(min)

4�s

clock HIGH period

Tsu;STA

t ~ tLOw (min)

start condition set-up time, only _valid for repeated start code

THD;DAT

t ~o �s

data hold time

Tsu;DAT

t ~250 ns

data set-up time

tr

ts;1�s

rise time of both SDA and SCL line

t1

ts; 300 ns

fall time of both SDA and SCL line

Tsu;STO

t ~ tLOw (min) stop condition set-up time

Note
All the values refer to V1H and V1L levels with a voltage swing of Voo to Vss.

SDA \_j --\_...__ __ )_ 1 L-] - 'C_ ~--- -1;-rJ:--T\_I"L ----- " -~

L-....1 L------J L--....J 1.-..-..J
START ADDRESS R/W ACK CDNDITION

~---~ ,______.

1...--J L-----1 ~ '-----'

DATA

ACK START. ADDRESS R/W ACK

CONDITION

STOP 7287014

February 1991

Fig.10 Complete data transfer. 756

Signetics RF Communications
Low power frequency synthesizer for radio communication

Where:
Clock; t LOW (min) = 4.7 �s Clock; !HIGH (rrin) = 4 �s
The dashed line is the acknowledgement of the receiver
Maximum number of bytes unrestricted
Premature termination of transfer allowed by generation of STOP condition
Acknowledge clock bit must be provided by the master

12c protocol
In order to fully program the synthesizer, a sequence of five data bytes is necessary. The data bytes are organized so that on subsequent transfers, not all five bytes need to be sent. This is achieved by the arrangement in Figure 11 .

Preliminary specification
UMF1009T

. ( all acknowledges
from UMF1009 n1 BIT 0

programming of all five registers

L_s_L--L_L__J_J.......;L.J.-L.,-J.---L--L--'-nO~B~IT~S~0--~6--'---'-A-'--'-"--n~1~B-IT~S-1~-~6'-'--A-'-~'-'--n2~B-l~TS~2-~6~A~-::i

R/W

'-v-'
n2 BITS o -1

'------..r-'
not used

n4 BITS

0-2
,---->----.,

L_ I : ~3 ~ITH- f : IAI I : : I : : : Hp I

t

'-----v--'

not

n3 BITS

used

8-11

MLA217~1

SDA.

data byte repeated for up to 5 words total

SCL START
February 1991

ADDRESS

R/W ACK (write shown)
Fig. 11 12c protocol timing.

DATA

757

ACK STOP
MLA218

Signetics RF Communications
Low power frequency synthesizer for radio communication

The information from the 12C-bus interface is only transferred to the relevant divider(s) on successful completion of the data after the STOP condition. For subsequent programming, e.g. on changing channels, it is only necessary to program the dividers which need altering.

The new information will only be locked into the lower 14 bits of the main divider registers. This reduces the loading on the 12C-bus.

Preliminary specification
UMF1009T

n1 BITO

n2 BITS
,,0...-..1..,

s

no BITS 0 - 6. A

n1 BITS 1 - 6 A P

MLA219

Fig.12 no and n1 programming.

Table 1 Data bit map

Register
1 2 3 4 5

7MSB 6

n1 .0 n0.6

n2.1 n2.0
x x

n3.7 n3.6

x

n4.2

5
n0.5 n1 .6
x
n3.5 n4.1

bit

4

3

n0.4 n1 .5 n2.6 n3.4 n4.0

n0.3 n1 .4 n2.5 n3.3 n3.11

2
n0.2 n1 .3 n2.4 n3.2 n3.10

1
n0.1 n1 .2 n2.3 n3.1 n3.9

0 LSB
nO.O n1 .1 n2.2 n3.0 n3.8

Where:

Slave address select (AO, A1)

nO, n1, n2 comprise the main divider n3, n4 comprise the reference divider nO.O is the least significant bit of no and so forth
= X don't care - bit position is not
used. Bit 7 (the MSB) is transmitted first on the bus.

Selection of the device slave address is achieved by connecting AO and A 1 to either Vss or Voo.
The slave address is defined in accordance with the 12c-bus specification as shown in Figure 13.

February 1991

0

0

0

A1

Fig.13 Slave address.

758

AO

R/W

Signetics RF Communications
Low power frequency synthesizer for radio communication
APPLICATION DIAGRAM

Preliminary specification
UMF1009T

HIGH FREQUENCY PRE SCALER

SCL

12c-sus
INTERFACE

VDDD SDA

DIGITAL AND ANALOG

Vss

PHASE COMPARATORS

PCD PCA

RA 470 kQ

MLA220

Fig.14 Application diagram.

Purchase of Philips' 12C components conveys a license under the Philips' 12 C patent to use the components in the 12C-system provided the system conforms to the 12 C specifications defined by Philips.

February 1991

759

Signetics RF Communications

Section 7 Cellular chip set

INDEX

Cellular chip set design guide .................................... . 762

12C Bus specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 806

AN168

The inter-integrated circuit (12C) serial bus: Theory and practical consideration . . . . . . . . . . . . . . . . . . . . . . . . . 822

Signetics

Cellular chip set design guide

RF Communications

The Philips Components-Signetics Cellular chip set is the world's first complete chip set commercially available from one manufacturer. It combines both Bipolar and CMOS technologies to bring a highly integrated

solution to the market. The complete chip set consists of 12 ICs that handle the processing of data, the processing of audio, the receiver, the switching of channels and ihe transmitter.

This section describes how the chip set
functions and how the software interacts
with the chip set. Acomplete demo board can be ordered through any local Philips Componsnts~Signetics sales office.

INTRODUCTION ............................................................................... . 802
1. CELLULAR SYSTEM DEFINITION ......................................................................... . 802 1.1. AMPS and TACS Spectrum Allocation .................................................................... . 803 1.2. An integrated chip-set addressing cellular market needs ...................................................... . 805 References ................................................................................ , ... , . , , , , , , , , 805

SYSTEM ARCHITECTURE ....................................................................... . 807

2. OVERALL ARCHITECTURE ...................... , ........ , ........ , ..... , , . , . , ..................... , .... . 807

2. 1. Clocking . . . . .

. ......................................... , ..... , ... , . , . , . , .. , .. 807

2.2. RF Architecture .................................................... , , ........ , ....................... . 807

2.3. Baseband Architecture .. , .................. , ........ , ........ , ....................... , .... , , .. , , ... , , . , 807

2.4. Other 12C Peripherals ..................................................................... , ........... . 808

HARDWARE DESCRIPTION ...................................................................... . 812

3. OVERVIEW .................................... , , ..... , ...... , , . , ......... , , .. , , , .... , ................. . 812

3.1. RF ........................................................ , .......... , ..... .

812

3.2. Baseband ............................................................ , . , . , ...... , .. , .. , ............ . 813

3.3. Data Path Description ................................................................................. . 815

3.4. Layout ............................................................................. , ............... . 815

SOFTWARE DESCRIPTION ...................................................................... . 833 4. OVERVIEW ............................................................................................ . 833 4. 1. Cellular Phone Operation .............................................................................. . 833 4.2. Setup & Implementation .......... , ........................ , ..................... , .... , ................ , 839

DATA SHEETS FOR THE CELLULAR CHIP SET ...................................................... .

TDA7052

1-Watt low voltage audio power amp..... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

NE/SA605

High performance low power mixer FM IF system .................................. , . . . . . . . . . . . . . . . . 280

NE/SA5750 Audio processor - companding and amplifier section (special components for cellular radio) . . . . . . . . . . . . . . . . . . 521

NE/SA5751

Audio processor -filter and control section (special components for cellular radio) .............. , . . . . . . . . . . . 528

UMA1000T

Data processor for cellular radio (DPROC) .................... , ........ , ..... , , ..... , ... , .. , , .. , , , , 595

TDD1742T

Low power frequency synthesizer (LOPSY) .. , ....................................... , . . . . . . . . . . . . . 641

UMA1014T

Frequency synthesizer for cellular radio communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683

762

Signetics RF Communications
Cellular chip set design guide

INTRODUCTION

INTRODUCTION
1. CELLULAR SYSTEM DEFINITION
A cellular system consists of an FM radio network covering a set of geographical areas (known as Cells) inside of which mobile two-way radio units, like Cellular Telephones, can communicate. The radio network is defined by a set of Base Stations distributed over the area of system coverage, managed

and controlled by a centralized or de-centralized digital switch equipment known as MTSO, or Mobile Telephone Switching Office. A base station in its geographical placement is known as a cell site. It is composed of low powered FM transceivers, power amplifiers, control unit, and other hardware depending on the system configuration. Its function is to interface between cellular mobiles and the MTSO. It communicates with the MTSO over dedicated data links, wire or non-wire, and

communicates with mobiles over the air waves. The MTSO's function is controlling call processing, call setup, and release which includes signalling, supervision, switching and allocating RF channels. MTSO also provides a centralized administration and maintenance point for the entire network. It interfaces with Public Switched Telephone Network (PSTN), over wire line voice facility, to honor services to and from conventional wire line telephones. Figure 1.1 depicts the components and layout of a cellular system.

Figure 1.1. The Components and Layout of a Cellular System.

An MTSO is known under different names depending on the manufacturer and on the system configuration. MTSO (Mobile Telephone Switching Office) was given to it by Bell Labs; EMX 1 (Electronic Mobile Xchange) by Motorola; AEX2 by Ericcson; NEAX3 by NEC; SMC (Switching Mobile

Center) and MMC4 (Master Mobile Center) are Novatel's. There are several types of Cellular telephones: mobiles, or car mount; portable, or pocket phone; and hand-held, or transportable phone. They fall into three classes (TACS has 4 classes) defined by the

amount of their power output: Mobiles (Class 1) radiate the most power; Transportables (Class 2); Pocket phones (Class 3; Classes 3 and 4 for TAGS) have minimum power output. Tables 1.1 a and 1.1 b show the classes of cellular phones and their power levels for AMPS and TACS, respectively.

February 25, 1990

763

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Cellular chip set design guide

INTRODUCTION

Table 1.1 a. Power of Mobile Phone for AMPS

Power of Mobile Phone for AMPS

Power Level
0 1 2 3 4 5 6 7

I

dBW

mW

6

4000

2

1600

-2

630

-6

250

-10

100

-14

40

-19

15

-22

6

Mobile Station Power Class

II

dBW

mW

2

1600

2

1600

-2

630

-6

250

-10

100

-14

40

-18

15

-22

6

lll

dBW

mW

-2

630

-2

630

-2

630

-6

250

-10

100

-14

40

-18

15

-22

6

Table 1.1 b. Power of Mobile Phone for TACS

Power Level
0 1 2 3 4 5 6 7

I

dBW

mW

10

10000

2

1600

-2

630

-6

250

-10

100

-14

40

-19

15

-22

6

Power of Mobile Phone for TACS

Mobile Station Power Class

II

Ill

dBW

mW

dBW

mW

6

4000

2

1600

2

1600

2

1600

-2

630

-2

630

-6

250

-6

250

-10

100

-10

100

-14

40

-14

40

-18

15

-18

15

-22

6

-22

6

IV

dBW

mW

-2

630

-2

630

-2

630

-6

250

-10

100

-14

40

-18

15

-22

6

A cell is defined by its physical size, and more importantly by the size of its population and its traffic patterns. An entire city like Chicago can be one cell. There are disadvantages, however, to such definition in that the number of channels would be limited to a small fraction of inhabitants, i.e., the system's capacity would be very limited, and the transmitter of the cell would have to be very powerful to cover such a large area. The major advantage behind a cell-based system configuration is the frequency re-use scheme, whereby, the same set of frequencies/channels can be allocated to more than one nearby cell provided the cells are a certain distance apart. Most cellular systems adopt a frequency re-use pattern of 7. The last constituent of a Cellular system is the communication protocol that governs the way a phone call is established. Cellular protocols differ between countries, e.g., in the USA the Advanced Mobile Phone Service standard (AMPS) is used, while in Canada

the AURORA 800 is used. In Europe each country has its own standard. Total Access Communication System (TACS) is used in the United Kingdom; NMT or Nordic system is used in the Scandinavian countries (Denmark, Norway, Sweden, and Finland); RC2000 is used in France; and NETZ C-450 is used in Germany. NTT is the Japanese standard for cellular.
1.1. AMPS and TACS Spectrum Allocation
In 1980 the FCC changed its policy towards a one-system-per-market, and established two licensed carriers per service area. It was the FCC 's view that such an approach would eliminate monopoly and provide some competitive advantages. Two systems (A and B) emerged, each with its own group of channels, to share the allocated spectrum (Figure 1.2). System A is defined for the non-wire-line companies, and system B is defined for the wire-line companies.

AMPS Cellular systems employ a frequency spectrum of 20MHz made up of 666 channels with 30kHz channel spacing. The transmit frequency at 825.030MHz is specified as channel 1, and transmit frequency at 844.980MHz is specified as channel 666. The receiver operates at 45MHz above the transmit frequency, therefore, channel 1 receives at 870.030MHz and channel 666 receives at 889.980MHz. An additional 5MHz spectrum was subsequently added to the existing 20MHz which increased the number of channels from 666 to 832. As for the TACS Cellular standards, its frequency spectrum is 15MHz comprised of 600 channels with 25kHz channel spacing. The transmit frequency at 890.0125MHz is specified as channel 1, and the transmit frequency at 904.9875MHz is specified as channel 600. The receiver operates at 45MHz above the transmit frequency, therefore, channel 1 receives at

February 25, 1990

764

Signetics RF Communications
Cellular chip set design guide

INTRODUCTION

935.0125MHz and channel 600 receives at 959.9875MHz. The AMPS and TACS channel spectrum is divided into 2 basic groups. A set of

channels are dedicated for control information exchange (mobile H cell site) and are termed control channels (shaded areas). The

second group, made up of the remaining channels, are termed voice channels and are used for conversations.

MoblleTx

Freq

824

825

A

Channel# 991

1

1023

Cell Site Tx

Freq

869

870

A" 33

Channel# 991

1

1023

835

845

846.5

849

851 MHz

A

B

A

B

R

333

666

716

799

r....r. �..] 880

A

'...."",/",./ ...........�...... 1

B

333

I""::::: .. :::::.�::::�:::::.�::::>:::

333

313 333 354

890

891.5

A'

B'

50

83

666

716

894

896 MHz

R

799

Figure 1.2. AMPS Frequency Management.

MobileTx

Freq

890

I

A

Channel#

Freq Channel#

Cell Site Tx

935

I

1........... / .1 :. . ',,./,/',..."':A
�' �'' ,,11 r'

23 43

897.5

I

B

300

942.5
I
300

l'"'"';..��:... �:...:1 :..."':. �"':....���:.....

B

343

905

910

915 MHz

II I

600

800

1000

- Not implemented

950

955

960 MHz

II I

600

800

1000

Figures 1.2 and 1.3 show the frequency spectrum and channel assignment for AMPS and TACS, respectively. Both figures include the additional spectrum of 166 extra channels for AMPS and 400 channels for TACS. Note, however, that TACS' additional spectrum has not been implemented and the dedicated

Figure 1.3. TACS Frequency Management
control channels are for the 600 channel system. The shaded area outlines the set of DEdicated Control Channels. Table 1.2 below summarizes the frequency parameters of AMPS and TACS. The set of control channels may be split by the system operator (MTSO) into subsets of DEdicated Control

Channels, Paging Channels and Access Channels. Figure 1.4 depicts an optional configuration of control channels by the MTSO, based on the Combined Page/Access channels variable (CPA) which is set by an overhead message.

February 25, 1990

765

Signetics RF Communications
Cellular chip set design guide

INTRODUCTION

CPA=1

206
t
LASTCHA

LASTCHP
i
302 313

FIRSTCHP
i
333
t
FIRSTCHA

CPA:O

LASTCHA
i
174

LASTCHP
i
301 302 313
I I
t
FIRSTCHA

FIRSTCHP
i
333

Figure 1.4. Optional Division of Control Channels for 'System A' Based on CPA.

1.2. An Integrated chip-set addressing cellular market needs
Cellular mobile telephones have been with us for several years. The first equipment was complex and highly priced (affordable only by the business sector). A rapid build-up in the number of users, fuelled by competition, has resulted in a steadily decreasing selling price to the consumer. In order to remain competitive, setmakers must continually strive to reduce costs. Key to achieving this aim is the adoption of an optimum architecture. Such an architecture must minimize complexity through the use of VLSI.

Existing sets tend to comprise a mix of analog functions provided by standard integrated circuits coupled with digital functions using custom/semi-custom circuits. By adopting a total chip-set approach using bipolar and CMOS technologies where most appropriate, a more optimal solution can be achieved. A series of developments with careful attention to low current consumption has resulted in a chip set of six ICs that is applicable to portables, trarisportables and mobile telephony. The chip set is suitable for both the American AMPS and the English (United Kingdom) TACS standards.

A software package implementing the AMPS and TACS standards, written entirely in PUM51, has been developed to introduce a fully functional cellular radio.
References
1. EMX is a trade mark or symbol of� Motorola
2. AEX is a trade mark or symbol of Erice son
3. NEAX is a trade mark or symbol of NEC
4. SMC and MMC are trade mark or symbols of Novatel

February 25, 1990

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Signetics RF Communications
Cellular chip set design guide

INTRODUCTION

Table 1.2 AMPS and TACS Frequency Allocation

AMPS

Channel Spacing

30kHz

Spectrum Allocation

20MHz

Additional Spectrum

5MHz

Total #of Channels

832

System A Frequency Allocation

AMPS

CH#

Mobile TX MHz

Mobile RX MHz

CH#

1

825.030

870.030

1

3131

834.390

879.390

232

3332

834.990

879.990

43 1

667

845.010

890.010

300

716

846.480

891.480

991

824.040

869.040

1023

825.000

870.000

System B Frequency Allocation

AMPS

3343

835.020

880.020

3233

3544

835.620

880.620

3434

666

844.980

890.000

600

717

846.510

891.000

799

848.970

894.000

NOTES: 1. Last DEdicated Control Channel for System A 2. First DEdicated Control Channel for System A 3. Last DEdicated Control Channel for System B 4. First DEdicated Control Channel for System B

TACS 25kHz 15MHz 10MHz 1000

TACS Mobile TX MHz
890.0125 890.5625 891.5625 897.5625

Mobile RX MHz 935.0125 935.5625 936.5625 942.5625

TACS 897.0625 897.5625 904.9875

942.0625 942.5625 949.9875

February 25, 1990

767

Signetics RF Communications
Cellular chip set design guide

SYSTEM ARCHITECTURE

SYSTEM ARCHITECTURE
2. OVERALL ARCHITECTURE
The RF section includes low power frequency synthesizers (UMA1014} and a single chip second mixer/oscillator/IF amplifier/demodulator (NE605}. A single chip CMOS data processor (UMA1000) performs all functions associated with control data, supervisory and signaling tones. All voice, alert and DTMF functions are contained on two audio processor devices; one CMOS and the other bipolar (NE/SA5751 and NE/SA5750, respectively}. Switched capacitor integrated filter technology is used in all baseband processing functions to achieve a minimum number of external passive components. The system's master controller is the 80C552 which is a derivative
of the Intel 80C52 �controller with integrated ADC (Analog-to-Digital Converter), PWM (Pulse Width Modulator), 12C and UART interfaces. The DPROC, the APROCs, and the LOPSYs are interconnected via an 12C bus which is a 2-wire serial bus that can transfer dataat 100kb/s. Refer to Figure 2.1 to view the system's architecture.
2.1. Clocking
A 9.6Hz VTCXO (Voltage controlled Temperature Compensated Xtal Oscillator) is divided by 8 to provide a 1.2MHz frequency for the data processor (DPROC, UMA1000}, and the audio processors (AP ROCs, NE/SA5750/5751). The �controller is clocked by aseparate11.059MHz crystal.
2.2. RF Architecture
2.2.1. Receiver Front-End
The receiver adopts a double conversion superhet architecture with a first IF of 45MHz and a second IF of 455kHz. A single transistor circuit is used for the RF amplifier and first mixer stages. The second mixer, second local oscillator, all IF amplification, limiter, demodulator and RSSI functions are provided by the NE605. The receiver's local oscillator comprises a single loop frequency synthesizer, UMA1014 a 7.2MHz oscillator for the frequency synthesizers, and another division by 6 to provide, normally operating at 45MHz above the receive frequency. An on-chip divide by 8, generating a 1.2MHz clock, for the Data and Audio processors, from a 9.6MHz VTCXO.

2.2.2. Transmitter
The modulation is applied to the transmit VCO. A loop bandwidth of approximately 200Hz is used in the transmit synthesizer path, achieving a flat modulation characteristic above 300Hz and permitting sufficiently fast switching time. Hybrid power modules are used to amplify the transmit signal to the level required according to the power class of the equipment
The cellular system requires the transmit power to be reduced in 4dB steps down to 6mW. To achieve a flat characteristic, independent of gain spreads in the amplifier stages, a power leveling loop external to the PA module is used (Figure 2.2). The output of the power module is adjustable by varying the supply voltage to one or more of the amplifier stages. A power sensor in the output of the transmitter generates a DC voltage related to the transmitter output power. This can comprise a simple diode detector, or a more complex system using a coupler with multiple sensing to reduce sensitivity to load VSWR. The sensor output is compared with a reference DC level using a voltage comparator and the difference used to control the power output. The loop will settle, such that the sensor output will be equal to the reference level. The reference level is derived by integrating the PWMO out-
put from the �controller and is set according to the required output power. Non-linearities in the sensor may be accommodated by suitable software calibration of the reference level.
There are a number of circuit functions which need to disable the transmitter (signal TX01s}:
the �controller for system control (in the case of a malfunction}; audio processor for VOX control in discontinuous voice mode; and data processor if a collision is detected during reverse control channel access. Control of the transmitter is provided by a single line with controlling devices 'pulling low' to disable in a wired-OR configuration.
2.3. Baseband Architecture
2.3.1. Audio Processors
All audio functions associated with the voice channel are processed in the NE5750/51 (Figure 2.4). Microphone amplification, VOX provision, compression, expansion and audio power output are provided in a bipolar IC, the NE5750. All filters, pre-emphasis, deviation limiting, de-emphasis, signal path switching, volume control and tone generation are provided in a CMOS IC, the NE5751.

Switched capacitor techniques have been used to fully integrate all filter functions. The tone generator is used for DTMF signaling, ringing tones and key confirmation. The pinouts of the two ICs have been arranged so that a straightforward interconnection is achieved on the PCB layout. Access to different parts of the audio signal path is inherent in this approach and eases the connection of ancillary units such as modem, hands-free adaptor, etc.
2.3.2. Data Processor
All functions associated with control data, supervision (SAT) and signaling (ST) are incorporated into a single CMOS data processor IC, the UMA1000 (Figure 2.5).
In the receive path, a dedicated two-wire serial link (RXcLocK. RXuNE} passes the fully decoded data word to the �controller. Clock-
ing is under control of the �controller and is not time-critical. When operating on a voice channel, the dotting detector, which precedes a data burst, is used to blank the audio path directly to prevent data bursts from being heard by the user (RAcTRLl�
In the transmit path, a 40-bit (36 data bits and 4bits of framing and DCC} word to be transmitted is passed from the �controller to the data processor via another dedicated two-wire serial link (TXcLOCK. TXuNEJ-where it is held in a buffer. The �controller can trigger immediate transmission of the data at the appropriate time. The base station returns the status of the channel access within the busy/idle stream. If the busy/idle stream does not revert to 'busy' during the specified window, transmission is aborted (TXcrRLl� This time-critical channel arbitration sequence is performed by the data
processor IC independent of the �controller.
2.3.3. Mlcrocontroller
The PCB80C552 �controller handles the functions of the cellular portable with low power and high operating speed. This CMOS processor is a derivative of the 6051
�controller. It can operate with an instruction cycle time of less than 1�s, and about 50% of its operations execute in a single machine cycle. This device also supports extensive power saving modes, giving approximately 75% power saving in a standby mode, and a micropower power--OOwn mode for backup battery operation. The low power modes ideally complement the UMA 1000T data processor which processes the continuous
cellular data stream, enabling the �controller

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Cellular chip set design guide

SYSTEM ARCHITECTURE

to operate in a burst processing mode. Thus the processor may spend in excess of 90% of the time in a standby mode.
The processor operates over a wide temperature range and has a high degree of EMC protection. It has an 8-cliannel-multiplexed 10-bit ADC, used for RSSI processing, battery voltage monitoring etc, and a pseudo 8-bit analog output (based on PWM} used to control the transmit amplifier's power level. A full hardware implementation of an 12C UART (in addition to the standard RS-232 UART), six 8-bit 110 ports and an 'on-<:hip' watchdog timer are all included. It has an industry standard 8052 core, which gives access to an extensive range of development support facilities, including 'High Level Language' support (PUM51, a Pascal....Jike language}, 'In Circuit Emulation' and symbolic debug facilities. This promotes fast development and debugging of equipment software.
A software package implementing the AMPS and TACS standards, written entirely in PUM51, has been developed to introduce a fully functional cellular radio.

c 2.3.4. 12 Bus
The 12C bus (Figure 2.3) is essentially a Local Area Network (LAN} for integrated circuits. Each device has its own 7-bit address and is connected to a tw~ire serial bus. The interface protocol is self-checking and selfarbitrating, allowing a multi-master control of the bus. Data is transferred at a rate of 1OOkb/s as a message block consisting of device address, a read/write indication, and the data block. A general description of the 12c bus is specified in the publication "The 12c Bus Specification" (order code 9398-358-10011).
The multi-master mode of the 12C bus can allow a simple test harness to take full control of the equipment for functional system tests and alignment in production. Test functions of the devices not used in normal operation can be exercised in this way.
2.4. Other 12c Peripherals
In addition to the major components of the Cellular Radio Chip Set, there are a large

number of general purpose peripheral ICs with 12C interfaces.
The PCF8576 is one of a range of LCD matrix and segment drivers. This device can address up to 160 segments, and is cascadable for larger displays. It is available in TAB packaging, allowing the device to be directly mounted onto a flexible connector driving the LCD. A six-wire connection to the main PCB (power, 12C and contrast control}, shows further cost advantages by reducing PCB area over that needed for normal direct LCD drivers.
This device exhibits most of the advantages that can be attained when using 12C peripherals for adding features to any particular equipment. The range of such devices cover most requirements, with the availability of EEPROMs, RAMs, clock/calendars, tone generators and 1/0 expanders, all usable on the same bus with no compatibility problems.

Antenna
Duplex Filter

Receiver ,,. "' , "'

,.. �' �'

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UMA1014

PCB80C552 Microcontrolle

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UMA1014

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Figure 2.1 System Architecture

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Signetics RF Communications
Cellular chip set design guide

SYSTEM ARCHITECTURE

BGY110D TX D R I V E . . - - - - -.....

DIRECTIONAL COUPLER
r--------,

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December 1991

RAM/EE PROM
Figure 2.3 12c Bus Structure

PRODUCTION TEST
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no

Rev. MK2A

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:mII

Signetics RF Communications
Cellular chip set design guide

HARDWARE DESCRIPTION

HARDWARE DESCRIPTION
3.0VERVIEW
The chip-set evaluator hardware design is divided into two major sections: RF section, and Data/Audio and Program Control section. al so known as the Baseband section.
The RF section consists of a receive and a transmit Local Oscillators. a receiver front-end circuit, a duplexer, and a transmit module. The Local Oscillators are clocked from a single source, a Temperature Compensated Xtal Oscillator (9.6MHz VTCXO). The receiver front-end circuit is composed of a preamp mixer for 1st IF, and 2nd IF and a demodulator circuit (NE605, Figure 3.1 ). The Local Oscillators' circuits utilize the UMA1014, a single chip frequency synthesizer with on-board llC interface allowing easy programmability and control from the micro. (Figures 3.3, 3.4).
The Base Band section consists of the Logic and Program Control circuit (Figure 3.6), a Data PROCessing circuit (UMA 1000, Figure 3.9), and an Audio PROCessing circuit which includes an Audio Power Amplifier, (NE/ SA5750/51, TDA7052, Figure 3.10). A separate MAX-232 driver board is provided to interface the Program Control circuit to a dumb terminal. This will aid the user in software development and debugging (Figure 3.8). Tables 3.4 and 3.5 show the codes and specifications a cellular phone should meet and how they can be met [Ref. 3]. Next we will identify the specifications that require further careful design.
3.1. RF
3.1.1. Receiver Design Consideration
3.1.1.1. Preamp Mixer Design
The AMPS specification calls for a -116dBm sensitivity at 12dB (SINAD) demodulated signal-to-noise ratio (EIA/IS-19-B 2.3.1.3.). There is 6d8 improvement in performance due to the pre-emphasis/de-emphasis function on board the NE/SA5751. This means that the detected S/N ratio has to be 6d8 prior to pre-emphasis/de-emphasis. For a 1kHz tone and a typical frequency deviation of 8kHz, normal FM demodulation characteristic curves show that a S/N ratio of 1-2dB is required. For a channel bandwidth of 30kHz, the input noise will be -129dBm. If we choose -119dBm as our sensitivity design

goal, it appears that this noise can only be degraded 8dB by the front-end in order to achieve the minimum detectable input carrier level of-119dBm. Assuming a worst case loss of SdB by the duplexer, a post duplexer amplifier with 3dB noise figure is required. In addition, because the front-end amplifier is followed by an 881 MHz ceramic filter and a mixer, the distribution of gains has to be optimized so that the overall noise figure of the front-end (including the duplexer) is not going to exceed BdB. In Figure 3.2 the gains and NFs are shown on the block diagram.
While all of the gain of the front-end can be achieved in the preamp, this has to be traded off against the required intercept characteristics. The AMPS specification calls for good detection in the presence of signals that are 60kHz and 120kHz away from the carrier. The carrier should be close to the minimum acceptable level for good detection. In this condition, the interfering signals should be 65dB larger than the desired carrier until they begin to cause reduction in detected signal level. A little bit of analysis shows that this specification (EIA 2.3.3.3) translates into a -17dBm system third-order intercept as measured from the antenna. Looking at Figure 3.2, since the first IF filteF (30kHz wide, 4-pole crystal filter at 45MHz) is narrow enough to eliminate the interfering signals, the intercept point of the overall system is set mostly by the front-end and the first mixer. Assuming a SdB worst case loss in the duplexer, a 1OdB gain in the front-end amplifier and 2dB loss in the 881 MHz ceramic filter, the first mixer must have an input intercept of about-14dBm (See Figure 3.1 ). For every dB of improvement in the intercept point of this mixer, the gain of the front-end can be improved by 1dB to help it better overcome the noise figure of the following stages. Having said this, however, it is recommended that the intercept point of the 2nd mixer not be ignored because future cellular requirements call for dynamic frequency allocations, or other modulation methods that may cause adjacent channels to be used within the same cell.
While we have used a bipolar device as our first mixer, a dual gate MOSFET has the potential of exhibiting better third-order intermod characteristics. Another technique for the front-end is to combine the preamp and mixer in one device. This has the advantage of relaxing the mixer intercept point by about 8dB. The problem, however, is that one has to depend on the duplexer filter for all of the image rejection to reduce the effective noise figure of the mixer.
3.1.1.2. FM IF

The Signetics NE605 chip is used to produce the FM IF. This chip first mixes the 45MHz first IF signal down to 455kHz (2nd IF). The signal then goes through approximately 100d8 of gain in a multi-stage limiter. The fully limited signal is then demodulated in the final quad-tank FM demodulator. The demodulator provides two outputs: Data and Audio. The data output contains data bursts and goes to the DPROC DEMODD input (Pin 3). The audio output is mutable; it goes to the APROC-NE5751 's RXBF1N input (Pin 17). The Audio channel is muted for the 1OOms data bursts period during a conversation. Another output of the chip is an internally temperature-compensated RSSI, Received Signal Strength Indicator, with more than 90dB dynamic range. With about 115dB overall gain and high impedances, the 2nd IF can pick up a multitude of signals and frequencies that are readily available in a cellular phone. (We will cover these when we discuss the layout and shielding issues). In recent years a number of cellular phone manufacturers have increased the first IF frequency to around 80-90MHz to be able to use SAW device first IF filters, and obtain better image rejection characteristics. While this can easily be accomplished with the NE605 chip, the increase of the IF frequency will increase the probability of closing spurious feedback loops that can cause regenerative oscillations in case layout is not done carefully. The AMPS spec for RSSI linearity (2.6.3) is directly satisfied by this FM IF, while other specs, such as sensitivity and hum and noise S/N (2.2.2.4.3), are partially satisfied by the FM/IF. In the case of the hum and noise SIN, the phase noise of the receive synthesizer is also important, but it can be neglected as long as its residual FM noise is much less than 1OOHz.
3.1.2. VTCXO
The 9.6MHz Voltage controlledTemperature Compensated Xtal Oscillator provides a reference clock to the transmit and receive Local Oscillators where it is divided by 8 to generate a 1.2MHz clock source to the APROCs and the DPROC.
3.1.3. Local Osclllators
The receive Local Oscillator circuit consists of the single chip frequency synthesizer, UMA1014, with on-board prescaler and loop filter, and a 926MHz VCO (45MHz above receive frequency. (Figure 3.3)
The transmit Local Oscillator circuit is similar to that of the receive LO circuit except that the VCO frequency is 836MHz and is used to modulate the signal (data or SAT+Audio) to be transmitted. (Figure 3.4)

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HARDWARE DESCRIPTION

The receive local oscillator frequency is set with small variations in gains or load

The following sequence should be followed

by the master �controller as follows: The

impedance, the power out could fluctuate as to insure proper operation of the DPROC:

�controller accesses the frequency synthesizer, via llC interface, and loads it with a reference and main divider values. The reference divider divides the 9.6MHz ieference frequen~/ down to 15kHz. The main divider value divides the VCO output frequency, after a fixed divide by 2 prescaler,

well. Also, if the antenna is accidentally removed with the unit in operation, the reverse power may damage the unit. To solve these problems, a feedback loop is generated by making a -1 SdB directional coupler which senses the reverse power (see Figure 3.5) and rectifies it. This can be a

1. Pin 22 - llC address Pin A1, must be tied HIGH; at least during the reset pulse. (Note that this will alter the DPROC llC address from OD8h to ODCh)
2. Pin 26 - NRESET must be tied HIGH.

I'
!

to produce 1SkHz. A mismatch, detected by simple diode detector, or a more complex

3. Pins 6 and 16 - must be tied to the RE-

the small phase comparator, causes the VCO to adjust its frequency such that, when divided by the main divider, it will yield 1SkHz. Note that the VCO output is 45MHz above the carrier frequency, and the main divider value must be set accordingly.
The transmit Local Oscillator frequency is set
similarly by the master �controller. Note

system using a coupler with multiple sensing and a dynamic matching network to further reduce sensitivity to load VSWR. This error signal is, in effect, added to the DC control
signal coming from the �controller PWM so
as to control the power module with a 2o�s time constant. The loop will settle, such that the directional-coupler diode detector output will be equal to the reference level. The

SET signal from the �controller, which was connected to Pin 26 (NRESET). Note that the reset from the
�controller must be active HIGH, because Pins 6 and 16 are active HIGH. The software must, therefore, change the polarity of the reset pulse accordingly.

however that the VCO output equals the car- reference level is derived directly from the

4. The RESET signal timing is as follows:

rier frequency, and that the reference frequency is 1.2MHz.

�controller (PWMO port) and is set according to the required output power. Non-linearities

~ 2so�sec in the HIGH state; < 1�sec fall time.

3.1.3.1. Receiver Frequency Syn-
thesizer
The design of the loop filter of the synthesizer and its resulting phase noise will help satisfy the (2.2.2.4.3) spec. In this case we have used a 200Hz filter which will give acceptable phase noise characteristics, and be fast enough for switching between channels.

in the sensor may be accommodated by suitable software calibration of the reference level. (This part of the circuit satisfies the 3.2.1.3 RF power output levels.)
3.2. BASEBAND
3.2.1. Logic and Program Control
This section of the baseband consists of a

3.2.2.1. Receiving Data
The data processor extracts digital data from the NE605 demodulated signal output (DATA). The data stream transmitted on the FOrward Control Channel is composed of a 463-bit message made up of word blocks, where each word block is a 28-bit data word and 12 parity bits repeated 5 times, and pre-

3.1.3.2. Transmitter Frequency Synthesizer
While a variety of synthesizer configurations are available, a more reliable operation with fewer spurious signals can be achieved if both transmit and receive frequencies are directly synthesized independent of each other. The transmit synthesizer has the same loop time constant as the receive synthesizer. The only difference is that a 300Hz-6kHz bandpass filtered signal (Voice+ SAT) is added to the VCO modulating input.
3.1.4. Transmitter Design Considerations
3.1.4.1. Power Leveling Loop

central processing and management unit, the
PCB80C552 �Controller, and its associated
circuitry. The �controller fetches program instructions stored on board a 64kBytes Programmable Read Only Memory (PROM, SN27C512-15 FA). An 8kBytes of Static RAM (FCB61 C65-70) is used to store data structures and program variables. Because
the �controller is based on Intel's 8051 family
of �controllers, and the data bus and the lower-order address bus share the same port (por!O). a 3-state Octal D-type transparent latch (74HC573D) is used to separate data from address (Figures 3.6, and 3.8). Table
3.1 lists the 1/0 signals on the �controller and their functions in the Cellular application.

ceded by a preamble (dotting) and word synchronization bits (as per EIAllS-3-D).
Detection of the Dotting sequence (10101010 ... ) is an indication to the DPROC that a message has arrived. The word synch, WSYNC, sequence trains the clock recovery circuitry and synchronizes it.
DPROC then extracts from each word block the 5-time repeated word and selects, by majority voting, one word. The selected word goes through error detection and correction where up to one error can be corrected. The DPROC then pulls RXuNE low, indicating to
the �controller that a data word is available. The DPROC repeats this process for each word block in the FOCC message.

A cellular system requires the transmit power to be reduced in 4dB steps down to 6mW. To achieve a flat characteristic, independent of gain spreads in the amplifier stages, a power leveling loop external to the PA module is used. The output of the power module is adjusted by varying the supply voltage to one or more of the amplifier stages. A PWM
signal coming out of the �controller is
low-pass filtered to get a DC control signal. A phone could, in principle, be calibrated in this mode using an external power meter to find the corresponding PWM number for each power level. The problem, however, is that

3.2.2. Data Processing
The data processing circuit consists of a DPROC, UMA1000T IC, with a small number of external passive components. The DPROC function is to decode received, demodulated data (DEMODD). from the NE605 and to encode and transmit digital
data from the �controller (Figure 3.9). The following sections will describe the receive and transmit paths of the DPROC, and Table 3.2 will describe its inputs and outputs and their functions.
Note on DPROC RESET sequence:

3.2.2.2. Transmitting Data
Data to be transmitted is fed to the DPROC,
from the �controller, for Manchester and BCH encoding, and conversion to an analog signal. The resultant analog signal output (DATA) goes to the APROC (NE5751) transmit summer input where it is added to an Audio signal (DTMF or speech) path. The transmit summer output is then modulated, in the transmit Local Oscillator block, and sent to the transmit module.
Two other analog components are outputted at Pin 4 (DATA), during Voice CHANnel state:

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Cellular chip set design guide

HARDWARE DESCRIPTION

Signaling Tone (ST) and Supervisory Audio Tone (SAT). ST, a 1OkHz carrier, is generated on board the DPROC and is used to acknowledge reception of control messages from the cell site. When ST is transmitted the audio signal in the transmit path is muted (TACTRL, disabling NES7S1 T4 & TS switches). SAT (SkHz � 30Hz signal) is used by the cell site to measure the mobile's signal quality. It is received by DPROC's Digital PLL, and transponded to the cell site by summing it with the speech signal coming from the APROC (NES7S1, T4 & TS enabled). Both ST and SAT are disabled when data is transmitted on the reverse voice channel (done inside DPROC).
3.2.3. Audio Processing
The audio processing functions for cellular applications are implemented on two IC's, the NES7SO and the NES7S1 (Figure 3.10).
3.2.3.1. NE5750
The NES7SO is a Bipolar IC. It integrates a noise cancellation circuit, a VOX circuit and a Companding circuit.
Noise Cancellation
When the input signal, produced by the microphone, drops below a certain threshold (e.g., when there is no speech), the noise cancellation circuitry reduces the overall gain by 1OdB. This threshold is set by an external resistor R3 (R3 Ohm x 0.0S VRMS)� The background noise canceller circuit has a builtin hysteresis to prevent VOX activation when the input signal is approximately at the threshold level.
Voice Operated Transmission, with an attack (C3), and decay (T = C3R1) set with external components.
Com pan ding

The audio signal's dynamic range is compressed before transmission, and expanded after reception.
3.2.3.2. NE5751
The NES7S1 is a CMOS IC. It integrates a de-emphasis, a pre-emphasis, a deviation limiter, and a DTMF generator. It also provides programmable digital switches to control the signal path (audio mute), and a digital volume control.
Pre-emphasis/de-emphasis: In order to improve FM receiver sensitivity and maintain good SIN for higher audio tones, the baseband audio signal's higher frequency components are amplified before transmission (pre-emphasis), and attenuated after reception (de-emphasis).
Deviation limiter: It guarantees a maximum audio signal (voice) deviation of �12kHz.
DTMF generator: Two DTMF registers are accessible form the 12c bus: High tone and Low tone DTMF registers. The High and Low frequency tones are computed as follows: High frequency= 1200kHz/S/HD
where HD is the High register value. Low frequency = 1200kHz/12/LD
where LD is the Low register value. This translates to: DTMF HI REG= 200000 I HI REG Hz and DTMF LO REG = 100000 I LO REG Hz
3.2.3.3. NE5750
The NES750 is a Bipolar IC. It integrates a noise cancellation circuit, a VOX circuit and a Companding circuit.
Noise Cancellation
When the input signal, produced by the\ microphone, drops below a certain threshold (e.g., when there is no speech), the noise cancellation circuitry reduces the overall gain by 1OdB. This threshold is set by an external resistor R3 (R3 Ohm x O.OS VRMs). The

background noise canceller circuit has a builtin hysteresis to prevent VOX activation when the input signal is approximately at the threshold level.
Voice Operated Transmission, with an attack (C3), and decay (T = C3R1) set with external components.
Compading
The audio signal's dynamic range is compressed before transmission, and expanded after reception.
3.2.3.4. NE5751
The NES7S1 is a CMOS IC. It integrates a de-emphasis, a pre-emphasis, a deviation limiter, and a DTMF generator. It also provides programmable digital switches to control the signal path (audio mute), and a digital volume control.
Pre-emphasis/de-emphasis: In order to improve FM receiver sensitivity and maintain good SIN for higher audio tones, the baseband audio signal's higher frequency components are amplified before transmission (pre-emphasis), and attenuated after reception (de-emphasis).
Deviation limiter: It guarantees a maximum audio signal (voice) deviation of �12kHz.
PTMF generator: Two DTMF registers are accessible form the 12C bus: High tone and Low tone DTMF registers. The High and Low frequency tones are computed as follows:
High frequency= 1200kHz/S/HD where HD is the High register value.
Low frequency = 1200kHz/12/LD where LD is the Low register value.
This translates to: DTMF HI REG = 200000 I HI REG Hz and
DTMF LO REG = 100000 I LO REG Hz

Table 3.0 Std DTMF Freq./Corresponding Values of DTMF HI/LO Registers

Number Dialed

High Freq.

Low Freq.

DTMFHI

1

1209

S97

AS

2

133S

S97

9S

3

1477

S97

B7

4

1209

770

A5

s

133S

770

9S

s

1477

770

87

7

1209

8S2

A5

8

133S

8S2

9S

9

1447

8S2

87

. 0

133S

941

AS

1209

941

9S

#

1477

941

87

DTMFLO BF BF BF B2 B2 82 75 7S 7S SA SA SA

December 1991

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Signetics RF Communications
Cellular chip set design guide

HARDWARE DESCRIPTION

The register values quoted will not give exactly these frequencies. Note that single tones can also be generated by loading 0, 1, or 2 in the high frequency register.
3.2.3.5. Receiving Audio
The demodulated signal (AUDIO) produced by the NE605 circuit-carries FM audio. It is fed to the NE5751 receiver input (Pin 17) where it is filtered by a 4th-order band-pass filter with a stop-band notch at 6kHz to reject the SAT signal. The resultant audio signal (300 - 3000Hz) is then de-emphasized with -6dB/Octave slope filter, over the higher frequency range, to compensate for the pre-emphasis function in the transmitter. The de-emphasized signal then goes to the NE5750 for expansion, to compensate for the compression in the transmitter. The recovered audio signal (expander output) comes back to the NE5751 into a digitally programmable attenuator circuit where the volume can be adjusted to 1 out of 16 levels, each with 2dB increments (level 0 = OdB, level 15 = 32dB). Finally, the attenuated signal feeds an audio power amp on board the NE5750 which drives the speaker. The same signal is summed to the side tone coming from the microphone using an audio power amplifier which drives the earpiece (Figure 3.1 Oa).
3.2.3.6. Transmitting Audio
The voice signal produced by the microphone is preamplified with a low noise, programmable gain preamplifier controlled by R7, on board the NE5750. The signal then feeds the noise cancellation circuit where gain is reduced by 1OdB in the presence of background noise (or absence of speech). The resultant signal then enters the NE5751 at Pin 4 where it is filtered with a 4th-order 300 3000Hz band-pass filter. The filtered signal leaves the NE5751 to be compressed on the NE5750. The compressed signal leaves the NE5750 and enters the NE5751 at Pin 6 where it is pre-emphasized 6dB/Octave slope in the pass band; a limiter circuit guarantees a maximum frequency deviation of �12kHz, and a 5th-order 3000Hz low-pass splatter filter controls the spectrum occupancy of the baseband signal to 3kHz (�1SkHz from center frequency). Before leaving the NE5751, the signal is summed to DTMF signals, generated internally, and to the SAT signal coming from the DPROC. The summer output is then modulated inside the transmit Local Oscillator block before going to the transmit module (Figure 3.10a).

3.3. Data Path Description
3.3.1. Receiving Data/Audio
The incoming SOOMHz RF modulated carrier through the Duplexer is mixed, using a single transistor circuit, with the receiver Local Osci!!ator to produce a 45MHz !F signal. This 45MHz modulated IF is then mixed down to 455kHz, filtered, and demodulated on board the NE605 (see 3.1.1.2). Only one of the two resultant demodulated signals from the NE605 goes to the APROC and DPROC for further filtering and separation into voice and data signals, respectively. The NE605 also provides a Received Signal Strength Indicator (RSSI). RSSI is routed to the ADC (Analog-to-Digital Converter) input of the
main �controller which can determine, based on the quantized value of the RSSI, the best channel from which to receive.
The NE605 demodulated output provides a data signal (DEMODD) to the data processor (DPROC) for digital data recovery and error correction. The recovered data is presented
to the �controller over a dedicated 2-wire bus (RXuNE & RXcLK). The controller then reads the data by clocking it out of the DPROC via RXcLK and processes it as dictated by the AMPS!TACS specifications. The DEMODD data signal also goes to the APROC (NE/SA5751, Pin 17)whereitis DEMPhesized, band-pass filtered to receive audio frequencies ranging from 300Hz to 3kHz, EXPANDed by the NE/SA5750, then sent to the earpiece.
3.3.2. Transmitting Data/Audio
Outgoing data frames are set up by the mas-
ter �controller and sent to the DP ROC over a dedicated 2-wire bus (TXuNE & TXcLK); the
�controller clocks the data into the DPROC via TXcLK� Refer to DPROC application note for transmitter link protocol [5]. The DPROC encodes the data into BCH and Manchester, converts it into an analog signal (DATA), and sends it to the APROC (NE/SA5751, Pin 24) transmit summer input. Speech signals coming from the microphone are fed into a noise cancellation circuit (NE/SA5750), band-pass filtered on the NE5751, then fed to the NE5750 for COMPression. The COMPressor output goes through the NE/ SA5751 where it is PREMphasized and low-pass filtered, and goes out at Pin 26 to the transmit summer input.
The APROC NE/SA5751 summer output, Pin 23 (signal TXMOD), goes to the transmit local

oscillator circuit where the signal is modulated, and then sent to the transmit module. For more information on Audio Processing refer to a paper by Ali Fotowat, et al [2].
3.4. LAYOUT
3.4.1. Layout and Shielding Techniques for Reducing Spurious Signals
The full-duplex feature of the cellular phone and the requirement for light and small phones, makes the layout very critical. Several paths for receiver blockage and instability do exist that have to be identified and eliminated. It should be made certain, however, that the gain blocks are designed with enough gain (e.g., for an FM IF chip with -106dBm sensitivity, at least 1OdB of noise free gain is required in the front-end and the first IF). In the case of the NE605, however, with better than -116dBm sensitivity already at the IF, the problem is reduced to calculating the noise figures and having just enough gain to overcome the front-end noise as it was calculated before. In either case, the final IF spectrum of a "noise" or "gain" limited receiver looks deceptively symmetric and clean; the only problem being not enough sensitivity. After these problems have been solved, the spurious signals start to show up in the final IF. There are several sources of these spurious signals that we have determined through experimentation and during the course of our design:
� The first and most important is the
leakage of the transmitter power or its sub-harmonics into the receiver section. This can be in the form of radiated or conducted spurious emission. The former can be eliminated by making certain that the whole phone package is made of metal or that at least the receiver section is totally shielded from the antenna. The latter can only be eliminated by the duplexer and the transmit-receive filters. Paths through the power supply should be eliminated by filtering the supply and using separate regulators for the RF power amp and the receiver.
� The second important source of
spurious signals is due to the receiver synthesizer and mixing products. Any phase noise or low frequency signal riding on the VCO input will end up in the IF pass-band. Too much LO level (overdrive of the first

December 1991

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Cellular chip set design guide

HARDWARE DESCRIPTION

mixer) will also mix with other available spurs, causing many unwanted in-band spurs.
� The third type of spur is due to the 2nd IF chip. Although the IF frequency is 455kHz, most of the gains are here and a poorly designed 2nd IF PC board layout can cause multiple loops. The 455kHz IF, although not a mixer, can reproduce the 45MHz IF component by mixing the LO and noise due to the nonlinearity of the amplification in limiters.
� Finally, spurs can be generated by the
�controller communication with the EPROM software, or other logic circuits (like the extra RS-232 interface used in our phone for demonstration purposes) or the dividers that divide the VTCXO frequency. All three circuits generated 455kHz IF band spurs. Although the clock frequencies in these sections are around 10MHz, the random pattern of data transmission can also generate strong enough non-harmonic spurs as high as 80 or 90MHz that can block the first IF for low levels, as well.
There are several techniques for detecting the presence of spurs. The easiest one is to check the DC voltage in the received signal strength indicator. RSSI in the NE605 has a wide dynamic range and does not distinguish between signals actually coming from the antenna or spurs looping in the receiver. Consequently, as the signal from the antenna weakens, the RSSI curve drops logarithmically, making a small (but distinguishable) dip, but remains flat at the RSSI level of the spurs, instead of going down to 0.5V or lower (depending on the front-end gain), which is

the case in the absence of such spurs. The second method is to use a low capacitance high impedance probe to look at the final 455kHz IF output on a spectrum analyzer. With no modulation and large RF signals (e.g., -80d8m), the rough shape of IF filters will be observable. As the RF input decreases, the noise level increases correspondingly and, eventually, the spurs will show up in the final IF. As long as the carrier level is a couple of dB above the spurs, the receiver seems to behave normally due to the FM capture effect. As the RF input becomes comparable or less than the spurs (as seen in the final IF), the receiver will be captured by the spur and the audio output will exhibit a lot of noise. To find out the source of each spur, one has to eliminate the sources by going back through the receiver stages. For example, if shorting the final 455kHz input to ground eliminates a spur, it is a sign that a simple 2nd IF loop is present. In this case, improvement in the grounding around the IF amps and use of low ESR tantalum supply bypass capacitors can help solve the problem. The same procedure is used in stopping or reducing the 2nd LO level, and/or shorting the 45MHz input of the FM/IF chip to ground. If a spur is eliminated this way, it is a sign of a 45MHz loop. The solution in this case, ironically, may be to reduce the gain. This can be done easily after the first 455kHz IF limiter without degrading the system noise figure. Of course, too much reduction in gain can also reduce sensitivity. As a result, the optimum reduction in gain which will eliminate the spur may be of the order of only 1 or 2d8, as we observed in our design. Disabling or reducing the 1st LO level is the next thing to

try in the same manner as above. This procedure will identify the place and the frequency at which the spurs enter the receiver. Finally, by eliminating other sources of
noise, like turning off the �processor or disconnecting various voltage regulators, the source of the fourth type of spurious signals can be systematically identified and eliminated.
The layout, shown in Figure 3.11, is divided into two sections: the top portion is the RF section, and the bottom portion consists of
the �controller, Audio, and baseband signal processing. The transmitter and receiver stages use different voltage regulators, and have also been separated as much as possible. The VTCXO is placed between the transmit and receive synthesizers. In the baseband portion, the APROC chips are placed close to the modulator synthesizer to minimize pick-up on the modulation input.
The positioning of the �controller and EPROM could be improved by placing them further away from the FM IF section. The current positioning required shielding of the FM IF chip.
Finally, each block was separated from the others by a grounded strip with many feedthrough holes. This allowed us to shield different parts of the board after we had eliminated many of the more obvious spurious signals, and helped in finding more potentially hazardous ones. Table 3. 1 shows the measurements on sensitivity with various sections shielded. It is obvious that the shielding of the IF section seems to have had the most effect.

Table 6. 1. Receiver Sensitivity Measurement Based on Shielding

Shielding on:

Receiver sensitivity

Front-end

-115d8m

2nd IF

-116d8m

Receive synthesizer

-115dBm

TC XO/Divider

-116d8m

Transmit synthesizer

-115d8m

Microcontroller/EPROM

-115d8m

Finally, comparison of our board with other existing phones of similar size shows a reduction from a 4 layer board to a two layer board, a 50% reduction in the number of ICs, and a 75% reduction in the number of external components in addition to minimum shielding.

REFERENCES:
1. "The 12C Bus Specification", order code 9398-358-10011, Signetics, September 1988
2. "Audio Processing For Cellular Radio or High Performance Transceivers", proceedings of RF Technology Expo, February 1989, A. Fotowat, S. Navid, L. Engh.
3. "EIA Interim Standard, Recommended Minimum Standards for 800-MHz Cellular

Subscriber Units", EIAllS-19-8, May 1988.
4. "An Integrated Chip Set for Cellular Mobile Telephones", Proceedings RF Expo West, 1989, T.G.R. Hall, P.J. Hart.
5. "The UMA1000T 'DPROC' Data Processor For Cellular Radio", TG.R. Hall, August 31, 1989. Report No: MCOB9005.

December 1991

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Rev. MK2A

Signetics RF Communications
Cellular chip set design guide

HARDWARE DESCRIPTION

Table 6. 2. �Controller 1/0 Signals and Their Functions In the Cellular Application

Port# Pin# Signal Name

Description

0

50-57 ADO-AD7 Data bus and low order address bus.

1

16

PWRDWN

Output. Power down control. It shuts off the power to the transmit LO circuit. It is active
high: 1 =power down.

17

HPDN

Output. Power down control. It powers down the APROC NE5750. 101 is active low:
O=power down.

Open-drain. It enables/disables the transmit module. The �controller must disable

transmission at the end of Conversation, or in the case of malfunction. It is also

18

TXCTRL. connected to DPROC which will disable transmission if a collision is detected during

SYStem access state, and to APROC (NE5750) to implement VOX during Voice

CHANnel state.

19

BUSY

Input from DPROC. Indicates the status of the REverse Control Channel. It is used in the SYStem access state to control the number of access attempts.

20,21 22,23

RXcLK� RXuNE SCL, SDA

A two-wire dedicated serial bus used to ship data from DPROC to the �controller. RXuNE is input, RXcLK is output. Four bytes of data are made available by the DPROC. RXuNE is first pulled low, signaling to the �controller that data is available. the �controller responds by targeting RXcLK and clocks data out of the DPROC.
12C bus clock and data signals, respectively. Please refer to appendix ii for description of the 12C bus specification.

2

39-46

A8-A15

High order address bus.

Receive and transmit signals for the on-board UART (Universal Asynchronous

3

24,25 RXD, TXD Receiver/Transmitter). They are connected via a MAX232 IC to the RS-232 connector

of a dumb terminal.

26,27 28

TXuNE. TXcLK TX HOLD

Dedicated two-wire serial bus used to ship data from the �controller to DPROC. TXcLK is output; TXuNE is 1/0. When the mcontroller needs to send data to DPROC it polls TXuNE� TXuNE in the high state indicates that DPROC is ready to receive it. Five bytes of data are sent to DPROC and will eventually be transmitted on the reverse access channel.
Output. Active high. It disables DPROC transmit buffer. It can be used to control message transmission.

29

NRESET Output. Active low. A pulse is generated to reset the DPROC.

4

7-14

KBO-KB7 110. They form a matrix for scanning the keypad.

5

1

RSSI

Input to ADCO. Received Signal Strength Indicator coming from NE605 is converted to digital. Selection of Best and 2nd Best of Dedicated, Page, or Access channels is done based on RSSl's digital value.

62-68 ADC1-ADC7 Unused.

Output of PWMO. Used to provide a voltage level to regulate power output of the

4

PWM

transmit module. The output has a dty cycle for responding to one of the seven power

levels.

December 1991

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Rev. MK2A

Signetics RF Communications
Cellular chip set design guide

HARDWARE DESCRIPTION

Table 6. 3. DPROC 1/0 Signals and Their Functions In the Cellular Application

Pin# Signal Name

Description

1

Analog ground.

2

Analog reference ground.

3

DEMODD Input. Demodulated signal carrier data or audio from the NE605 circuit.

4

DATA

Output, to NE5751. Analog output providing Manchester encoding and filtered data signal, SAT, and Signaling Tone.

Open drain, connected to APROC (NE5751 ). Receiver audio control. While in VCHAN state,

5

RACTRL and a dotting sequence is detected indicating the arrival of a control message, the audio path

to the earpiece (switch M2) is muted to prevent the user from hearing the the data burst.

6,

7, 16,

See DPROC specification.

21

8, 27

RXuNE� RXcLK

Two-wire serial bus used to ship received data words from DPROC to the �controller.

11

TACTRL Open drain connected to APROC (NE5751 ). Transmit audio control. While in VCHAN state and

data needs to be transmitted, the audio path (switch M1) is muted allowing only data path to the

APROC summer input.

15, 18

TXuNE� TXcLK

Two-wire serial bus used to ship data words to be transmitted from the �controller to DPROC.

Input, from �controller. It disables data words from going through the transmit path of the

17

TXHOLD DPROC. The �controller may load the DPROC transmit buffer, but inhibit transmission until the

BUSY signal changes to IDLE.

Output, to �controller. Multiplexed with a data stream transmitted on FOCC is the BUSY/IDLE

bit indicating the status of the reverse control channel. DPROC sets BUSY signal accordingly.

19

BUSY

It is used to determine whether a collision has occurred during transmission: if the channel

becomes busy before 56 bits have been transmitted, or if channel does not become busy after

104 bits have been transmitted.

Open drain disables transmit module. DPROC control over transmission is activated when a

20

TXCTRL collision, as defined in EIA/IS-3-D (also, on page 13 of DPROC spec, items 9, 10 of Access

Attempt Procedure), is detected (see BUSY).

24,

SDA, SCL 12C bus data and clock signals, respectively. For a description of 12C bus refere to Appendix ii.

25

DPROC 12C address = OD8h

December 1991

779

Rev. MK2A

Signetics RF Communications
Cellular chip set design guide

HARDWARE DESCRIPTION

Table 6. 4. Meeting Receiver Specifications AMPS Standards

EIA/IS-19-B

Specification

Met By

2.2.2.1.3

Audio Frequency Response

APROC

2.2.2.2.3 2.2.2.3.3

Audio rv1uting

APROC OR NE605

I

expander Tracking

NE5750

i

2.2.2.4.3

Hum and Noise S/N

NE605

2.2.2.5.3

Audio Distortion

APROC AND NE605

2.2.2.6.3

Audio Sound Level

SPEAKER, NE5750

2.2.3.2.3

Bad SAT Report

DPROC

2.3.1.3

Sensitivity

FRONT-END AND NE605

2.3.2.3

Adjacent Channel Selectivity

MURATA FILTERS

2.3.3.3

lntermods

FRONT-END

2.3.4.3

Spurious Response Interference

SYSTEM DESIGN

2.3.5.3

Bit-Error-Rate

DPROC, NE605

2.4.3

Conducted Spurious Emission

LAYOUT, FILTERING

2.5.3

Radiated Spurious Power

PACKAGING AND FCC

2.6.3

RSSI Linearity

NE605

December 1991

780

Rev. MK2A

Signetics RF Communications
Cellular chip set design guide

HARDWARE DESCRIPTION

Table 6. 5. Meeting Transmitter Specifications AMPS Standards

EIA/IS-19-8

Specification

3.1.2.3

Frequency Stability

3.1.3.3

Carrier Switching Time

3.1.4.3

Channel Switching Time

3.2.1.3

RF Power Output Levels

3.2.2.3

Switching Time Between Power Levels

3.2.3.3

Carrier-On State

3.3.1.3

Modulation Stability

3.3.2.1.3

Compressor Tracking

3.3.2.2.3

Transmit Frequency Response

3.3.2.3.3

Inst. Peak Deviation

3.3.2.4.3

Audio Muting

3.3.2.5.3

Transmit Audio Sensitivity

3.3.3.3

Wideband Data

3.3.4.3

SAT Deviation and Phase Error

3.3.5.3

ST Frequency and Deviation

3.3.6.3

FM Hum and Noise

3.3.7.3

Residual AM

3.3.8.3

Modulation Distortion and Noise

3.4.1.3

Spectrum Noise Suppression

3.4.2.3

Conducted Spurious Emissions

3.4.3.3

Radiated Spurious Emissions

3.5.3

Crosstalk (Audio)

4.

Environ mental

EIA/IS�3�D

CELLULAR SYSTEM MOBILE STATION - LAND STATION COMPATIBILITY SPECIFICATION

Met By TCXO, UMA1014 RF Power Module UMA1014 Power Mod, PWM Cal. Power Leveling Loop RF Power Module and Driver APROC NE5750 NE5751 NE5751 APROC Microphone, NE5750 DPROC DPROC DPROC and 5751 NE5750, UMA1014, VCO Synthesizer and RF Amp APROC APROC, Filtering, Shielding Duplexer, RF Power Mod Shielding APROC, Packaging Ruggedness
Signetics AMPS Software

December 1991

781

Rev. MK2A

I

CT

+

!!l

<D

~

FILT4

45MHz

.O,J
I C107N0

R52 150
R50� 24k

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s:
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FILT3 45MHz
C113 5pF

C72 30pF
I C37 .1u

L3 620nH

L1

C58

~ 1.2uH

1N

~F
= 44~

L4 620nH

C67 30pF

r~C47
RSSI
R45 100k

U17 NE605DK

MXROUT
oEcoupl-'-"---r---,

DEC~J~ �_,'-------

NE605DK !FOUT

R47

5.1k

Ll~~~~~-----

DECOUP !-"'--------,
DE COUP
LIMOUT

C35 10oF

�ADDS TUNABILllY TO QUAD TANK

L7 220nH
I~

- ~ -~
~
'-j

.___-~~+-+~~~~~~~~~~~~~~~~~~~-~
'-----+--~-----------------~�~

" . 1R.525k

. R46 . 100k
.___-.---+------------------~

R67 100k

Figure 3.1 First IF, Second IF and Demodulatlon Circuit

Rev. MK2A: 516191

Ql

0

re ~

!c!.

~:0
"Tl

ii) 0

0

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0 z

Signetics RF Communications
Cellular chip set design guide

HARDWARE DESCRIPTION

Figure 3.2 Front-End Galna and Nolae Figures

D~ber1991

783

Rev. MK2A

~

J
~

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i...i

..g~�
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VCOOUT

9.6MHz
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0 z

Signetics RF Communications
Cellular chip set design guide

HARDWARE DESCRIPTION

~
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December 1991

789

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Signetics RF Communications
Cellular chip set design guide

HARDWARE DESCRIPTION

1 l RF POWER MOD

TX SYNlll

TCXO

APROC I DPROC

l l DUPLEXER

RX SYNTH

RF AMP/ 1stlF
2nd IF LIMITER
DMOD

�Controller

POWER I REGULATION

RS-232 INTERFACE

Figure 3.11 PCB Layout

RF
BASEBAND/ CONTROLLER

December 1991

793

Rev. MK2A

Signelics RF Communications
Cellular chip set design guide

SOFTWARE DESCRIPTION

SOFTWARE DESCRIPTION
4.0VERV!EW
The source code is developed using Intel's Programming Language for �controller 8051 family (PLM51) and PLM51 compiler. The soflware was initially developed to implement TACS (Total Access Systems, United Kingdom) protocol. The AMPS parameters W8R1 extracted from the EIA IS-3-D

specifications and added to the existing source code to result in a single piece of software that can run either AMPS or TACS standards. To select between the two standards, a compilation switch would have to be set accordingly, and ALL the high level software modules would have to be recompiled. An example of a compilation batch file is shown in the Appendix.
4.1. Cellular Phone Operation
From a protocol stand point, a cellular telephone operates as a state machine

switching between four major states: INIT (INITialization), IDLE, SYS (SYStem acoess), and VCHAN (Voice CHANnel). Four software modules, with similar names but with .PLM extension, implement these states respectively, and are described in section 4.2.2, High Level Modules. Following is a description oi ihe software's !op level state diagram (Figure 4.1) linking these states together.

MAIN
t
POWER-UP
t
NORMOD

lnlt of Flags, Software Global -c-- varlables, buffers, Interrupts, DPROC,
APROC, 12c... especially timers

Mobile Roamed to a Different System

c

LOW POWER MODE

c

Walt for

USER or SYSTEM REQUESTS

INIT.
t
IDLE
t

RESCAN

Xmltted MIN & ESN

HAND-OFF

SYS ace

t "ORIGINATION"" "'PAGE RESP""

c VCHAN

RELEASE

CHANGE POWER

Other

/Id hardware power up or system reset, the mobile executes POWRUP routine followed by NORMOD, the state machine handler, which then switches the phone state to the INITstate.
Figures 4.2 through 4.5 show a high level ftowchart of the AMPS protocoVsoftware. It is

designed to give the reader a general idea of the activities of a cellular telephone. The major states are enclosed in rectangular boxes, and are interconnected with arrows leading to decisions (lozenges) and reasons for exiting any particular state. Each of the states is tagged with a reference number

corresponding to a paragraph in the EIA/IS-3-D specification.
4.1.1. INIT
In the INIT state the mobile scans the Dedicated Control Channels spectrum and selects the two best channels based on the

February 25. 1990

794

Signetics RF Communications
Cellular chip set design guide

SOFTWARE DESCRIPTION

quantized value of the RSSI signal coming from the RF FRONT-END circuit (NE605).
The mobile then locks onto the best channel and reads and decodes overhead control messages (OHO) which are periodically transmitted by the cell site on the FOrward Control Channels(FOCC). Part of the OHD messages read are information to configure the Paging channels.
If unable to read any messages from best channel (mobile roamed away from nearest cell site), the mobile tries again by listening to the 2nd best channel. If the mobile fails again to read messages from the 2nd best channel, it repeats the !NIT state and re-scans the Dedicated Control Channels spectrum. Otherwise, the mobile does the following:
Once configured, Paging Channels are scanned and OHO messages are decoded from best or 2nd best Page Channel, then compared to information already read from best or 2nd best Dedicated Control Channel (EIA 2.6.1.2.2). The need for such comparison arises due to the roaming feature of cellular. The user may have roamed out of his Home System between reading data from the Dedicated Control Channel and reading data from the Paging Channel. Upon verification, i.e. the mobile is still in Home System, the mobile switches to the IDLE state. Otherwise, the mobile has roamed to another system and the !NIT state is re-executed.
4.1.2. IDLE
In the IDLE state the mobile listens to the Best or 2nd Best Page channel, as determined in the INIT state, and waits for requests from the User or from the system, i.e. the cell site. Requests from the system are sent in OverHeaD messages, such as REGISTRATION and RESCAN, and as mobile Station Control Messages, such as AUDIT order and PAGE order. User request can only be a call ORIGINATION, and is issued by pressing the SEND key. All requests, such as Registration, Audit, or Page (from the system) and Origination (from the user) require the mobile to transmit control information back to the system on the REverse access Control Channel (RECC) (see SYStem access below). Hence, following the receipt of a request, the mobile goes into SYStem access state. In the case of a RESCAN order, the mobile does not need to go to the SYStem access state; it simply loops back into the INITialization state. Note that OH D messages received over Page channel carry information to configure

Access channels which are used in the system access state. During the IDLE state the mobile's transmitter and its Audio processing circuitry are not operational, so they can be powered down and reduce the phone's power consumption level.
4.1.3. SYS Access
The main task in the system access state is to seize a Reverse access Control Channel and transmit to the cell site the mobile Identification Number (MIN or Tel. #) followed by the mobile Electronic Serial Number (ESN), as per EIA 2.6.3. 7 (Service Request). Criteria for reverse control channel seizure, like maximum number of seizure attempts and maximum number of channel busy indications, are communicated to the mobile over the best forward access control channel. The mobile starts the SYStem access state by scanning the set of access channels and selecting the 2 best channels, as done for dedicated and paging channel selection. The mobile then attempts to acquire a reverse access channel by first monitoring the Busy/Idle bit. If the channel is busy, the number of busy attempts is incremented. However, if the channel is not busy, and the mobile has started transmission of its MIN and ESN, but a collision is detected (by DPROC, which will abort the transmission), the number of seizure attempts is incremented. In either case of channel acquisition failure (due to Busy or collision), the mobile waits 200msec before attempting another channel seizure. If the number seizure attempts, or the number of busy occurrences, have been incremented to exceed a certain maximum, the mobile aborts SYStem access and goes to INIT state. Otherwise, if the system access timer times out before it was able to seize a REverse Control Channel, the mobile exits system access state and goes to INIT state. If the system access timer did not time out, channel seizure was successful, and MIN and ESN were transmitted, the mobile changes its internal state to Service Request (Figures 4.4 and 4.5) where a next step decision is made based on the reason for entering SYS access state (i.e., Registration, Audit, Page Response, or Origination). If the mobile has entered the SYStem access state in response to an Audit order, the mobile goes to INIT state. (Audit is a way for the system to poll roaming mobiles to determine their geographic location on a cell boundary.) If the mobile has entered the SYStem access state in response to a Registration indication,

it waits for the cell site to acknowledge the receipt of MIN and ESN by sending a Registration Confirmation control message. The mobile, having received the confirmation message, will then update its Registration timestamp and return to !NIT stale. (FigU19 4.5, Auto Reg Update, 'Success1 If system access Is entered in response to Origination or Paging Request, the mobile waits for the cell site to assign it an initial voice channel, and then goes to the llOica channel state. If system -�timer times out before a voice channel is assigned, the mobile exits system access and goes to INIT state. Note that in response to a user originated call, the mobile transmits the dialed number in addition to transmitting MIN and ESN.
4.1.4. VCHAN
The mobile verifies that the initial voice channel assigned to it in SYStem - � state is a valid channel, i.e., within the spectrum of voice channels, then tunes to It. Voice channel state consists of three sub-states: Conversation, Waiting for Order and Waiting for Answer. If the mobile enl8nl VCHAN in response to a user originatllld cal, it goes directly to Conwrsation sub-state and remains there until ordered by the cell site to change sub-states (or state, e.g. Release state). If the mobile enters VCHAN in response to system originated call (or paging), it goes to Wait for Order sub-state. In this sub-state the cell site sends an Alert message to the mobile ordering it to ring. The mobile rings and changes sub-state to Wait for Answer.
The user would answer the phone by pressing the SEND key, changing the mobile sub-state to Conversation. During sub-statn the mobile can be handed off to another channel, or the power level changed, by order messages from the cell site. Receipt of cell site orders are acknowledged by the mobile by generating a 10kHz signaling tone with variable duration, based on the received message.
When the conversation is terminated, by the user pressing the END key or by a Release order from the cell site, the mobile turns on Its signaling tone for 1.Ssec to indicate to the cell site that it will release the voice channel and shut off its transmitter. The mobile then goes to !NIT state.
This was an overall description on the cellul� behavior. Following is a brief description of each of the software modules.

February 25, 1990

795

Signetics RF Communications
Cellular chip set design guide

SOFTWARE. DESCRIPTION

RETRIEVE SYS. PARAMS
2.&.1.1

lllTIAUZATION

PAGING CHAN
saECT
2.&.1.2

I

"SSECTO

i

ON ZND BEST CHAN"

TOGGLE SEIMNG-SYSTEM

February 25, 1990

INITSTATE IDLE STATE

"ORDER INDICATION" "REGISTRATION"

SYSTEM ACCESS 2.8.3

PAGE MATCH 2.8.2.2 ORDER 2.8.2.3
NO

YES "ORIGINATION"

"REGISTRATION"

YES

796

Slgnetics RF Communications
Cellular chip set design guide

SOFTWARE DESCRIPTION

TUNE TO Ind STRONGEST CHANIE.

SYSTEM ACCESS
I.I.I
8ET ACC TllER
SCANACC c:tfANNELS
2.1.3.2
RETRIEVE ACC ATTEMPT PARAMS
2.1.3.3

ALTERNATE ACC CHANNEL 2.1.3.11

ALREADY TUNED TO Ind STRONGEST CHA

YES
8EllVING SYSTEM DE1ERllNATION
2.11.3.12

NO

UPDATE

"OllEllLOAD CONTROL lllSG"

OVERHD

INFO

2.11.3.4

SEIZERECC 2.11.3.5

xWAIT
(0 c c 0.75mo)

NO

"ACC TYPE PARAM MSG" "ACCATTEMPT PlllRAM MSG"

READ"BUSY" UNE

WAIT (OcXc

February 25, 1990

SERVICE REQUEST
2.11.3.7
Figure 4.3. AMPS Flow Chart: System Access State
797

Signetics RF Communications
Cellular chip set design guide

SOFTWARE DESCRIPTION

I SERVICE REQUEST

.

2.6.3.7

. "ORDER CONARMATION" "REGISTRATION''

Ssec:TO

(2.6.3.3))

"INITIAL VCHAN DESIGNATION"

"DIRECTED RETRY"

"INTERCEPT" "REORDER"

"DIRECTED RETRY'' 2.6.3.14

USER INVOKED RELEASE TERM. ST. ENA.
NO

SERV. SYS. DETERMINATION 2.6.3.12

AUTONOMOUS REG
UPDATE 2.6.3.11

.----------
CONARM INITIAL VOICE CHANNEL
2.6.4.2

ALERT: TO

ORDER: Ssec TO

SYS Ace STATE

"ORIGINATION"

"PAGE RESP."

VCHANSTATE

CONVERSATION 2.6.4.4
"USERAN "

WAIT FOR ORDER 2.&A.3.1

14-----~ "HANDOFF"

"AUDIT' (RST ORDER TIMR

"CHANGE POWER" ,.__ _ _ _ _ _ _ _,._, "OTHER ORDER"

O.Saec:TO

"STOP ALERT"

"ALERT"

CONVERSATION ,__ _ _ _ _ �usER INVOKED RELEASE

"MAINTENANCE"

ORDERS

"RELEASE" ~------------1--f---------~

'--r---.--......1 (WAIT 0.Ssec.) TERMINATION STATUS ENA.

"RELEASE"

"HANDOFF" "SEND CALLED ADD"
"AUDIT" "CHANGE POWER"
"OTHER"

"HANDOFF" "AUDIT" "MAINTENANCE" "CHANGE POWER" "OTHER"

WAIT FOR ANSWER

RELEASE

'-------......! 2.6.4.3.2

"RELEASE"

._.....,--.---~ (WAIT 0.5oec.)

2.6.4.5

"ALERT", "MAINTENANCE"

February 25, 1990

Figure 4.4. AMPS Flow Chart: System Access State (cont) and Voice Channel State 798

Signetics RF Communications
Cellular chip set design guide

SOFTWARE DESCRIPTION

"ORDER CONRRMATION" (RESP TO AUDIT)

SERVICE REQUEST 2.1.3.2

SERVING SYS DETER�NATION
2.8.3.12

NO YES

SSEC:TO
ACTION ON REG FAILURE 2.8.3.10
"RELEASE"

"OTHER"

YES "ORDER CONFIRMATION" (RESP TO REGISTRATION)

{REGISTRATION DONE}

("SUCCESS")
AUTO REG UPDATE 2.1.3.11

Figure 4.5. AMPS Flow Chart: System Access Stale (cont)

February 25, 1990

799

Signetics RF Communications
Cellular chip set design guide

SOFTWARE DESCRIPTION

4.2. Setup & Implementation
The software modules can be divided into two categories:
1. Device driver modules.
2. High level, protocol dependent modules.
Device drivers are hardware dependent routines allowing the user control over the ICs using a high level language. High level modules are hardware independent routines and typically address the device drivers during normal operation. Following is the list of device drivers for the cellular chip set
4.2.1. Device Drivers
APCINTPLM� This file programs the Analog-to-Digital Converter on board the �controller PCB80C552. The software waits until the ADC has converged before reading the digital value of the analog signal (typically RSSI).

DPROC.PLM� This file is temporary. It is a patch for the DPROC, version TN2682. It contains routines that perform message set-up and transmission, bypassing the DPROC transmit path. This is due to the fact that the TN2682 has a faulty Manchester encoder (see note in INTDAT.PLM below). Two other programs, described beiow, are developed to work in conjunction with this module: SENDl.ASM and INTERRUP.ASM.
llQ.PLM; This file programs the 12C bus interface on board the �controller PCB80C552. The software performs retries in the case of no acknowledgment.
INIDAT PLM: DPROC communication software with the system controller over the dedicated xmit/receive lines:
RXcLK. RXuNE DPROC ->�controller
TXcLK� TXuNE �controller -> DPROC

Hold

�controller -> DPROC

Transmitter Routine When the system controller needs to send data (typically MIN and ESN during a system access), it polls TXuNE� indicating DPROC readiness to receive data. The transmit
routine wm not be called unless the TXuNE
has been released HIGH by the DPROC, signifying buffer Not busy, or readiness for receiving more data. The transmit routine picks up the data (5 bytes) from the data structure TX_MESSAGE(TX_WORD_NUMBER).TX_ WRD_DATPRO, and transmits it serially on TXuNE while toggling TXcLK (data stable on positive edge). On the last rising edge of
TXcLK� DPROC will pull the TXuNE LOW as an ACK/(buffer)BUSY signal. The transmitted word has the following format (e.g., word1).

BYTEO

BYTE 1

BYTE2

BYTE3

BYTE4

7 65 4321 0 7 6 54 32 0 76 54 32 10 76 54 32 10 7 654 3210

E s D D F NAWC T s E R SCM

<----------------- MIN23.0 ----------------->

s

M T c c

s

T

p Acc

v

0

TR 0

D

p

y T

NOTES: 1. The STOP bit is not part of the structure.

2. The EMPTY bit is not used and is always set to zero.

Message to be transmitted is stored in

structure: TX_MESSAGE

(m).TX_WRD_DATPRO (b)

where:

mis word number ( 0-5 )

bis byte number within

word (0-4 ) counting from left

~:Due to the DPROC hardware problem
in transmission, the �Controller performs message formatting and transmission instead of the DPROC. To that effect, the transmit software routine which normally passes to the DPROC a data word (40bits), namely DPROC_SEND_DATA_WORD, has been replaced with another routine, SEND_DPROC_MESSAGE in DPROC.PLM module.

SEND_DPROC_MESSAGE now forms the message to be transmitted by calculating the parity for each of the repeats of the word (5 repeats) and forms a frame. This frame of 5 data words is then preceded with Dotting, Word synchronization, and encoded DCC to form the final message to be transmitted.

SND_DATA_ASM routine is then called to perform the transmission on the TXuNE. The transmit driverroutine, SND_DATA_ASM, is written in assembly language for better efficiency, and is located in a file called SENDl.ASM. Note that TXi.tNE wire is used to transmit the data. It must be routed to the APROC's summing input. TXcLK is unused (not toggled by software).
We have included in the software a compilation variable, BYPASS, in order to invoke the appropriate transmit routine. With the new DPROC (TN2683) which fixes the transmit hardware problem, the transmit software routine can be removed. The user should, however, re-compile all modules with BYPASS =0 (see compilation example) in order to select DPROC_SEND_DATA_ WORD routine (DPROC.PLM and SENDl.ASM may be deleted).
Summary: If BYPASS = 1, the parity is computed and appended at the end of each

word of the 5-word frame, and Dotting + WSYNC + encoded DCC are inserted at the beginning of that frame before the whole message is transmitted on TXuNE to APROC summing input, by SENDl.ASM. Receiver Routine When the DPROC has received and decoded the incoming DEMODD data of the Forward control channel (FOCC), it pulls the RXuNE LOW. The system controller, which is now in receive message mode polling RXuNE continuously looking for messages on FOCC, supplies RXcLK to clock the data out of the DPROC according to the received data timing (page 12 of DPROC spec.). The receive routine, DATA_PRO_RX, first pulls the clock line LOW, waits some time for the hardware to settle, then clocks out DPROC data on the rising edge. A total of 32 bits (4 bytes) are clocked in and the clock is left in a HIGH state as the spec. shows.
The received word has the following format (word1).

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SOFTWARE DESCRIPTION

BVTEO

7 6 5 4 3 2
s B TT DD

Tc 2cc

A H

c c

R E

0

T R

R

BVTE1

BVTE2

BYTE3

0 76543 2

0 76543 2 10 765 43 2

0

<----------------- SID1 ----------------->

RSVD

NAWC

OHD s s

p T

A 0

R p

E

Received message is stored in structure:

RX_MESSAGE (m).RX_WRD_DATPRO (b)

where:

m is word number (0-15)

b is byte number within

word (0-3) counting from left

IOMOD PLM� This file contains a list of high level routines used to program devices on !he 12C bus. Such routines rely on lower level 12C routines, in 12C.PLM, to perform the actual data transfer. Note that a specific data structure must be adopted in order to make use of IOMOD.PLM independenUy.

MSGXHAND PLM� This file contains high level routines !hat perform siring processing for the UART interface. They rely on lower level routines, in V241NT.PLM, to maintain the data structure for data received from !he Dumb terminal keyboard, and data sent to the Dumb terminal screen.

SENDI PLM� This Is a program written in assembly language and designed to transmit the message for the DPROC. The data bits are shifted out on TXuNE at a frequency equals twice the data rate. due to Manchester encoding.

SYNTH PLM ILOPSYPLM)� This file contains procedures to program the synthesizers (Receive and Transmit). They use the 12C routines which do the actual data transfer. SYNTH.PLM MUST be used with the UMA1010/12 synthesizers only, and LOPSY.PLM MUST be used with TDD1742 synthesizers. Both files contain the same set of routine names. So if they are both compiled, the one that is linked last will be the effective one. Note that TDD 1742 has no 12C interface, and must be used with an 1/0 expander PCF8574.

V241NT PLM� This file holds the �controller PCBBOC552 UART interface routines for data transfer from and to the Dumb terminal. This file sits below MSGXHAND.PLM hierarchically.

NOTE: V241NT.PLM and MSGXHAND.PLM are NOTpart of cellular operation. They were developed to support test programs and utilities in TESTH.PLM.

4.2.2. High Level Modules
This is the list of modules that implement the AMPS/TACS standards. It is presented alphabetically.
CODMSG PLM: This module is a support module. II deals with encoding of words A..E, as labeled in EIA spec, for transmission on the reverse control channel. It also encodes words F..H for transmission on the reverse voice channel. Note that words F, G and H are Order Confirmation, Called-Address Word, and Called-Address Word 2, respectively.
IDLE PLM� The Idle mode has several main functions to perform. These include:
1. Check data fading, (5sec. timer to read OverHeaD message)
2. Check non-preferred system timeout, (TACSonly)
3. Respond to Overhead MSG,
4. Respond to mobile control MSG (Page and Order),
5. Check re-registration timeup, (TACSonly)
6. Support call initiation request (SEND key pressed)
When certain conditions specific to the function involved are satisfied, the above functions can cause the mobile to exit from Idle state into either IN!lialization or SYStem access states. When this happens, the program returns IDLE_EXIT_REASON flag which will be used by a higher level module (NORMOD) to decide on the next action to take. IDLE_EXIT_REASON is initially set to NU LL and is used to keep the mobile in Idle state.
While the mobile is in IDLE state, and IDLE_EXIT_REASON =NULL, the �controller is put in idle or "sleep� mode by setting register PCON[O] = 1. In addition, we set variable LO_POWER_MODE =TRUE to indicate to the master timer routine, in TIMINT.PLM, to change the periodic

interrupts from 1msec to 25msec. At the next
timer interrupt, the �controller wakes up (every 25msec.) and resumes execution of the IDLE state starting from the line of code following the assignment statement: 'PCON = 0000001'.
lli.IIf.LM; The top level routine, INITIALIZATION_STATE, consists of three nested loops. The inner most one dictates that an overhead message must be read on the DEDICATED CONTROL CHANNEL and parameters updated. II is possible that the mobile alternates between two serving systems if no overhead message can be received from either system.
Coming out of the inner loop, the mobile needs to read an overhead message on the PAGING CHANNEL. If it failed on the current serving system (system A or system 8), it has to restart on the other serving system. If ii has successfully gone through the above two stages, the overhead information collected on the Dedicated Control Channel is compared with that collected on the Paging Channel. Unless they match, the above activities are repeated indefinitely.
There is another requirement of the spec (SSDn which allows the mobile lo enter this procedure al the middle, skipping stages of initialization and the inner loop described above. Thal is dealt with using a flag INIT_1ST_STAGE.
MAIN PLM: Contains a call to POWERUP to inltialize the software and the hardware and a call to the state machine handler (NORMOD) which decides which of the four states to go to next (Figure 4.1 ).
NORMOD PLM� State machine handler. Based on the ...EXIT_REASON of one state, this routine selects next state and calls the corresponding routine. Debug messages can be placed here, displaying reasons for exiting one state and entering another.
PWRUP.PLM: Initializes global variables such as control registers for DPROC and APROC, serving system, etc.

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RPMSSG PLM: This is a support module. It reads state dependent messages from DPROC.
~: This is a support module. It deals with updating the registration variables, and keeps track of the last four visited areas (NEXTREGs-p SIDs-p pair).
REPLY PLM: This is a support module. It contains functional blocks related to handling replies from land station during system access.
BFXHIXLE PLM: High level to SYNTH.PLM (or LOPSY.PLM). It scans the dedicated control channel spectrum of system A or system B and chooses the best channel.
~When a mobile enters System Access state from Idle, its IDLE EXIT BEASON becomes the ACCESS AIM in the context of this state. A SYSACC EXIT BEASON is initially set to NULL on entry. When changed to one of the following

reasons, the SYSACC EXIT BEASON .causes an exit from this state.
ORDER_CONFIRMED MSG_TIMOUT
OVERLOAD_DISTB_DELAY, (TACS) EXCEED_MAX_BUSY
EXCEED MAX SEIZE RELEASE
INTERCEPT RE-ORDER
USR_HALT ACCESS_TIMOUT
VCHAN_ASSIGNED
Apart from VCHAN ASSIGNED in which case the mobile enters 'Control of voice channel' state, the other reasons cause it to go to SSDT (Serving System Determination Task). The mobile can retry to gain access if it

received a directed retry message from the land station by selecting from a new set of access channels' two best ones.
Tl MINI PLM: Interrupts occur every 1msec during the active states of the mobile, i.e., POWER UP, INITIALIZATION, SYSTEM ACCESS and VCHAN; but during IDLE state the interrupts occur every 25msec with the timer increments being adjusted accordingly. This allows the processor to spend more time in the low power mode which is flagged by a bit (LO_POWEB_MODE), and the timer interrupt sets another bit (LONG_TIMER_INT) to flag the change from 1ms to 25msec increments.
nmers are configured into two arrays of 5 entries each. One array measures in MSEC (millisecond), and the other measures in MINutes. They are considered as high level timers and are declared as follows:

GP_TIMER_MSEC (NUM_OF_GP_TIMERS)

word

external auxiliary

GP_TIMER_MIN (NUM_OF_GP_TIMERS)

byte

external auxiliary

where NUM_OF_GP_TIMERS= 5 Note that handling these is the responsibility of the user, i.e., they can be used as any system timer as defined by AMPS or TACS.
The main part of this module is the TO interrupt vector routine which is called every 1msec (or 25msec). The msec portions of the timers is decremented by one. When msec reaches zero, the MIN portion is examined and decremented if> 0 while the MSEC portion is loaded with 60000. If the

MIN portion is zero and the MSEC portion is also zero, the timer is no longer decremented. Note that the timers can be Enabled and Disabled by loading OOh and OFFh, respectively, in the MIN part. If the timer value is more than 1 minute, it is automatically enabled.
The timer interrupt allocates timeslots within a 128msec frame to perform the various time related functions. The low level timers are

updated every 1msec, and high level timers are updated every 4msec to prevent timer interrupt overrun. The keypad is scanned every 32msec.
The interrupt by timer TO is caused by a 16-bit counter overflow. Therefore, TO must be loaded with an initial value of OFC65hex to cause 1msec interrupt, and must be loaded with OA5FFhex for a 25msec interrupt according to the following:

Xtal = 11.059MHz.

nmer Period of 1msec is TP = (XTAL Hz/12)10�3 sec. = 1ms;

where 12 = 1 machine cycle.

@ 11.059MHz, 1msec period 1 ms TIMER

= 039Ah
=OFFFFh - 039A

= OFC65h; counting up

@ 11.059MHz, 25msec period

= 5AOOh

25 msec TIMER

= OFFFFh - 5AOOh

= OA5FFh; counting up

Hence

TIMEB_BELOAD_HI

=OFCh

TIMEB_RELOAD_LO

=065h

TIMER_RELOAD_Hl_25

=0A5h

TIMER_RELOAD_L0_25 = OFFh:

This module also handles the telephone keypad by scanning it. Routine KBOARD_SC scans the keypad and returns the declared value of the key pressed; NULL if no key pressed, or OFFh if two keys pressed. The key pressed is checked again in 32msec for debounced. If the key is

accepted the key value is stored into the keypad buffer and later used by READ_USER_INPUT routine, called from various points in the software to update the LCD. Note that if a key remains pressed, it is only accepted once.

TXMSSG.PLM: High level to INTDAT.PLM (or DPROC.PLM) in that it deals with transmission of data words to DPROC. It monitors channel arbitration (BUSY/IDLE signal from DPROC) and turns OFF
transmitter (TXDIS =0) in the case of

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SOFTWARE DESCRIPTION

collision, as specified by UMA 1000 specification, Reverse Control Channel Access Arbitration, page 11. The arbitration is specified as follows:
1. Initial condition: Busy/Idle= Idle; transmission in progress.
2. If Bii reverts to Busy before the first 54 bits have been transmitted, a collision has occurred.
3. If Bii does not revertto Busy after 104 bits have been transmitted, a collision has occurred.
VCHAN PLM (mobile station control of voice channel): The Control of Voice channel state consists of the following sub-states:
1. WAIT FOR ORDER
2. WAIT FOR ANSWER
3. CONVERSATION
4. RELEASE VOICE CHANNEL
Within these sub-states, the mobile waits to receive either a user command or an order from the land station. Apart from having received a command/order which requires the mobile to come out of the wait loop, it also emerges when other conditions are satisfied. These conditions are
1. Fade timeout
2. Time to check channel quality (SAD, at least every 250msec
After having processed the order/command/emerge condition, the sub-states report the result to its immediate calling routine ( 1 level up, control of voice channel) which directs the mobile to enter a new sub-state as listed above, or re-enter the same sub-state. The mobile stays on the voice channel until there is a reason to leave

such as Answer timeout, Fade timeout or Release command. When VCHAN is first entered, the task of 'Confirming initial voice channel ' is carried out. For as long as the mobile remains on the voice channel, the quality of the voice channel is monitored by reading SAT color code (SCC).
XTRCT Pl M: This is a support module. It unpacks received messages into individual fields and sets appropriate variables.
4.2.3. Include Flies
DATETIME DCL' This file contains a declaration of a CONSTant string which, when called by the software, will display a date and time stamp. It is included in MAIN.PLM. This file must be updated to reflect the current date and time before compilting MAIN.PLM. Such utility is not provided with the source code.
DECLAR.QCL: This is a list of declaration of variables. It is inluded in all � .PLM files.
EXTRNS.PCL' This is a list of declaration of external variables and external procedures. It is inluded in PWRUP.PLM file.
REG552.QCL� This file contains the 80C552 Special Function Register map and declarations of those registers. It is developed by INTEL.
REPEAIPCL� This file contains a macro definition of REPEAT...UNTIL statement. It is included in DPROC.PLM.
PUBLIC DCL' This is a list of global variable declarations. It is included in MAIN.PLM. A change in this list must be followed by a compilation of MAIN.PLM.
UTIL51 DCL' This is a list of library routines to aid in the programming. It is developed by INTEL, the supplier of PLM51 compiler.

4.2.4. Installation
The hardware platform is assumed to be an IBM PC or compatible. There are three floppies containing all the files needed to generate the PROM code for the chip-set evaluator unit. The PLM51 compiler and linker programs must be resident, or reachable, from the working directory. Insert the floppies and use the COPY command to copy the content into a working directory. Proceed to next section to learn about compilation and linking, but here is a summary of commands to get PROM code:
1. COPY B:�.� <CR> ( Repeat for all three floppies }
2. BUILD <CR>
3. LINK<CR>
The final PROM code resides in file CELL1.HEX
4.2.5. Compiling and Linking
There are several command files set up to aid the programmer in the compilation of the source modules, and link their corresponding object modules. After every source module is compiled, it is added to a library called USERL!B.L!B (this file can be created by running LIB51 program). When all modules have been compiled and added to USERLIB.LIB, the linker must be invoked by running RL51 program to resolve all external definitions and produce the final HEX code. Below is a list of the command files and their functions.
PLMA BAT This command file calls up the PLM51 compiler and, if there are no errors, invokes the library program LIB51 to add the compiled module to the list of object modules. When done, it deletes the .OBJ file to free up disk space. An example of PLMA content is shown below.

USAGE: PLMA < module name, without .PLM extension>

Example: PLMA ADCINT

N~TE: ~e us~r must provide a program to automatically update file DATETIME.DCL evety time PLMA is called on MAIN(.PLM). Date and Time stamping 1s important to keep track of software revisions.

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SOFTWARE DESCRIPTION

Example: PLMA.BAT
echo off if exist%1.plm goto COMPILE echo ERROR ! File does not exist goto END :COMPILE echo Compiling ... AMPS = SET, BYPASS =SET if % 1==main echo Running date stamp if %1==MAIN echo Running date stamp if %1==main <Include a call to a program to update the date/time stamp in DATETIME.DCL file> if %1==MAIN <Include a call to a program to update the date/time stamp in DATETIME.DCL file> plm51 % 1.PLM SET(BYPASS) SET(AMPS) DEBUG LIST OPTIMIZE(3) CODE if not errorlevel 2 goto LIBRARY echo ERROR in compilation ! echo MODULE has not been updated in library goto END :LIBRARY if %1==main goto END if%1==MAIN goto END echo Adding to Library lib51 replace % 1.obj in userlib.lib del %1.obj del %1.lst :END echo on

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SOFTWARE DESCRIPTION

UNJ:UlAI This routine must be called to link
the object modules and produce the final hex code. Below is an example of LINK.BAT.

USAGE:

LINK

Example: LINK.BAT

echo off RL51 MAIN.OBJ, SENDl.OBJ, INTERRUP.OBJ, USERLIB.LIB, PLM51.LIB, UTIL51.LIB TO CELL1.ABS IXREF overlay
oh cell1.abs to cell1.hex echo on

BUILD BAT This utility file will compile all the modules and add them to USERLIB.LIB. It must be followed by LINK.BAT to generate

the PROM code. Below is an example of BUILD.BAT.
Example: BUILD.BAT

USAGE:

BUILD

call PLMA codmsg call PLMA dproc call PLMA except call PLMA hsekpr call PLMA idle call PLMA iic call PLMA init call PLMA intdat

call PLMA lopsy call PLMA main call PLMA msgxhand call PLMA normod call PLMA pwrup call PLMA rdmssg call PLMA reg call PLMA reply

call PLMAsys call PLMA testh call PLMA timint call PLMA txmssg call PLMA v24int call PLMA vchan call PLMA xtrct

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Signetics

12C Bus specification

RF Communications

INTRODUCTION For 8-bit applications, such as those requiring singie-chip microcomputers, certain design criteria can be established:
� A complete system usually consists of at least one microcomputer and other peripheral devices, such as memories and 1/0 expanders.
� The cost of connecting the various devices within the system must be kept to a minimum.
� Such a system usually performs a control function and does not require high-speed data transfer.
� Overall efficiency depends on the devices chosen and the interconnecting bus structure.
In order to produce a system to satisfy these criteria, a serial bus structure is needed. Although serial buses don't have the through-put capability of parallel buses, they do require less wiring and fewer connecting pins. However, a bus is not merely an interconnecting wire, it embodies all the formats and procedures for communication within the system.

Devices communicating with each other on a serial bus must have some form of protocol which avoids all possibilities of confusion, data loss, and blockage of information. Fast devices must be able to communicate with slow devices. The system must not be dependent on the devices connected to it; otherwise, modifications or improvements would be impossible. A procedure has also to be resolved to decide which device will be in control of the bus and when. And if different devices with different clock speeds are connected to the bus, the bus clock source must be defined.
All these criteria are involved in the specification of the 12c bus.
THE 12c BUS CONCEPT Any manufacturing process (NMOS, CMOS, 12L) can be supported by the 12c bus. Two wires (SCA-serial data, SCL-serial clock) carry information between the devices connected to the bus. Each device is recognized by a unique address-hether it is a micro-

computer, LCD driver, memory or keyboard interlace-and can operate as either a transmitter or receiver, depending on ihe iunction of the device. Obviously an LCD driver is only a receiver, while a memory can both receive and transmit data. In addition to transmitters and receivers, devices can also be considered as masters or slaves when performing data transfers (see Table 1). A master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. At that time, any device addressed is considered a slave.
The 12C bus is a multimaster bus. This means that more than one device capable of controlling the bus can be connected to it. As masters are usually microcomputers, let's consider the case of a data transfer between two microcomputers connected to the 12C bus (Figure 1). This highlights the master-slave and receiver-transmitter relationships to be found on the 12C bus. It should be noted that these relationships are not permanent, but only depend on the direction of data transfer at that time. The transfer of data would follow in this way:

Microcoll1jlUler
A

Gate Array
ADC

LCD Driver
Static RAM orEEPROM

Mcrocomputer B
Figure 1- Typical 12C Bus Configuration

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Signetics RF Communications
12c Bus specification

Table 1. Definition of 12c Bus Terminology

TERM

DESCRIPTION

Transmitter

The device which sends data to the bus

Receiver

The device which receives data from the bus

Master

The device which initiates a transfer, generates clock signals, and terminates a transfer

Slave Multi-master

The device addressed by a master
More than one master can attempt to control the bus at the same time without corrupting the message

Arbitration

Procedure to ensure that if more than one master simultaneously tries to control the bus, only one is allowed to do so and the message is not corrupted

Synchronization

Procedure to synchronize the clock signals of two or more devices

1. Suppose microcomputer A wants to send information to microcomputer B.
-Microcomputer A (master) addresses microcomputer B (slave)
-Microcomputer A (master transmitter) sends data to microcomputer B (slave receiver)
-Microcomputer A terminates the transfer.
2. If microcomputer A wants to receive information from microcomputer B
-Microcomputer A (master) addresses microcomputer B (slave)
-Microcomputer A (master receiver) receives data from microcomputer B (slave transmitter)
-Microcomputer A terminates the transfer.
Even in this case, the master (microcomputer A) generates the timing and terminates the transfer.
The possibility of more than one microcomputer being connected to the 12c bus means that more than one master could try to initiate a data transfer at the same time. To avoid the chaos that might ensue from such an event, an arbitration procedure has been developed. This procedure relies on the wired-AND connection of all devices to the 12c bus.
If two or more masters try to put information on to the bus, the first to produce a one when the other produces a zero will lose the arbitra-

tion. The clock signals during arbitration are a synchronized combination of the clocks generated by the masters using the wired-AND connection to the SCL line (for more detailed information concerning arbitration see Arbitration and Clock Generation).
Generation of clock signals on the 12C bus is always the responsibility of master devices; each master generates its own clock signals when transferring data on the bus. Bus clock signals from a master can only be altered when they are stretched by a slow slave device holding down the clock line or by another master when arbitration takes place.
GENERAL CHARACTERISTICS Both SDA and SCL are bidirectional lines, connected to a positive supply voltage via a pull-up resistor (see Figure 2). When the bus is free, both lines are High. The output stages of devices connected to the bus must have an open-drain or open-collector in order to perform the wired-AND function. Data on the 12c bus can be transferred at a rate up to 1OOkbit/s. The number of devices connected to the bus is solely dependent on the limiting bus capacitance of 400pF.
BIT TRANSFER Due to the variety of different technology devices (CMOS, NMOS, 12L) which can be connected to the 12C bus, the levels of the logical

0 (low) and 1(High) are not fixed and depend on the appropriate level of Voo (see Electrical Specifications). One clock pulse is generated for each data bit transferred.
DataValldlty The data on the SDA line must be stable during the High period of the clock. The High or Low state of the data line can only change when the clock signal on the SCL line is Low (Figure3).
Stan and Stop Conditions Within the procedure of the 12C bus, unique situations arise which are defined as start and stop conditions (see Figure 4).
A High-to-Low transition of the SDA line while SCL is High is one such unique case. This situation indicates a start condition.
A Low-to-High transition of the SDA line while SCL is High defines a stop condition.
Start and stop conditions are always generated by the master. The bus is considered to be busy after the start condition. The bus is considered to be free again a certain time after the stop condition. This bus free situation will be described later in detail.
Detection of start and stop conditions by devices connected to the bus is easy if they have the necessary interfacing hardware. However, microcomputers with no such interface have to sample the SDA line at least twice per clock period in order to sense the transition.

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12c Bus specification

-�........ Rp

+YDD Rp

i-.-1.1ne1
SDA

(Serio! Clock Uno)

i

SCL

I'

SCLK

SCLK

SCIX1 OUt

1lll'llt1 OUI

SClK In

DATA In

SCLK In

..DATA

Figure 2. Connecllon of Devi_ to lhe l2C Bus

SDA
--� -= SCL ------�!/ -Une Figure 3. Bh Transfer on the l'C Bus

It SDA .t\_�___I____,:,_:__\___. ' SDA

~� �I n 'I L r '

I

�I .

SCL

I

I

I

I

ICL

I

I

I

I

I

8

I

I

p

I

'

'

StaltCondHlon

Stop-
Figure 4. Start and Stop Condition�

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Signetics RF Communications
12c Bus specification

TRANSFERRING DATA
Byte Format
Every byte put on the SDA line must be 8 bits long. The number of bytes that can be transmitted per transfer is unrestricted. Each byte must be followed by an acknowledge bit.
Data is transferred with the most significant bit (MSB) first (Figure 5). If a receiving device cannot receive another complete byte of data until it has performed some other function, for example, to service an internal interrupt, it can hold the clock line SCL Low to force the transmitter into a wait state. Data transfer then continues when the receiver is ready for another byte of data and releases the clock line SCL.
In some cases, it is permitted to use a different format from the 12c bus format, such as CBUS compatible devices. A message which starts with such an address can be termi-

nated by the generation of a stop condition, even during the transmission of a byte. In this case, no acknowledge is generated.
Acknowledge
Data transfer with acknowledge is obligatory. The acknowledge-related clock pulse is generated by the master. The transmitting device releases the SDA line (High) during the acknowledge clock pulse.
The receiving device has to pull down the SDA line during the acknowledge clock pulse so that the SDA line is stable Low during the high period of this clock pulse (Figure 6). Of course, setup and hold times must also be taken into account and these will be described in the Timing section.
Usually, a receiver which has been addressed is obliged to generate an acknowledge after each byte has been received (except when the message starts with a CBUS address).

When a slave receiver does not acknowledge on the slave address, for example, because it is unable to receive while it is performing some real-time function, the data line must be left High by the slave. The master can then generate a STOP condition to abort the transfer.
If a slave receiver does acknowledge the slave address, but some time later in the transfer cannot receive any more data bytes, the master must again abort the transfer. This is indicated by the slave not generating the acknowledge on the first byte following. The slave leaves the data line High and the master generates the STOP condition.
In the case of a master receiver involved in a transfer, it must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that was clocked out of the slave. The slave transmitter must release the data line to allow the master to generate the STOP condition.

S D A: N - Q D G '
' ' ' '

:

I

MSB

Acknowledgment Sign�I from Receiver

r - - ..
' '

' ' '

,

:

1

S''' C s '' L1 ~' 2 ~- - J Start Condition

Byte Complete, Interrupt within Receiver

Clock Une Held Low While Interrupts Are Serviced

Figure 5. Data Transfer on the 12c Bus

Stop Condition

Data Output by Transmitter

~

g;~~~:~~~~~~~~~~~~~~~--1~

December 1988

SCLfrom Master
s
Start Condition

~ Clock Pulae for Acknowledgment

Figure 6. Acknowledge on the 12c Bus

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Signetics RF Communications
12c Bus specification

ARBITRATION AND CLOCK GENERATION

High level, while another master transmits a Low level, will switch off its DATA output stage since the level on the bus does not cor-

On the byte level, a device may be able to receive bytes of data at a fast rate, but needs more time to store a received byte or prepare

respond to its own level.

another byte to be transmitted. Slave devices

Synchronization
All masters generate their own clock on the SCL line to transfer messages on the 12c bus. Data is only valid during the dock High period on the SCL line; therefore, a defined clock is

Arbitration can carry on through many bits. The first stage of arbitration is the comparison of the address bits. If the masters are each trying to address the same device, arbitration continues into a comparison of the data. Be-

can then hold the SCL line Low, after reception and acknowledge of a byte, to force the master into a wait state until the slave is ready for the next byte transfer in a type of handshake procedure.

I
i'

needed if the bit-by-bit arbitration procedure cause address and data information is used On the bit level, a device such as a micro-

is to take place.

on the 12C bus for the arbitration, no informa- computer without a hardware 12c interlace

Clock synchronization is performed using the tion is lost during this process.

on~hip can slow down the bus clock by ex-

wired-AND connection of devices to the SCL LINE. This means that a High-to-Low transition on the SCL line will affect the devices concerned, causing them to start counting off

A master which loses the arbitration can generate clock pulses until the end of the byte in which it loses the arbitration.

tending each clock Low period. In this way, the speed of any master is adapted to the internal operating rate of this device.

their Low period. Once a device clock has gone Low it will hold the SCL line in that state until the clock High state is reached (Figure 7). However, the Low-to-High change in this device clock may not change the state of the SCL line if another device dock is still within its Low period. Therefore, SCL will be held Low by the device with the longest Low period. Devices with shorter Low periods enter a High wait state during this time.
When all devices concerned have counted off their Low period, the clock line will be released and go High. There will then be no difference between the device clocks and the state of the SCL line and all of them will start counting their High periods. The first device to complete its High period will again pull the SCLlineLow.
In this way, a synchronized SCL clock is generated for which the Low period is determined by the device with the longest clock Low period while the High period on SCL is determined by the device with the shortest clock High period.
ArbHratlon
Arbitration takes place on the SDA line in

If a master does lose arbitration during the addressing stage, it is possible that the winning master is trying to address it Therefore, the losing master must switch over immediately to its slave receiver mode.
Figure 8 shows the arbitration procedure for two masters. Of course more may be involved, depending on how many masters are connected to the bus. The moment there is a difference between the internal data level of the master generating DATA 1 and the actual level on the SDA line, its data output is switched off, which means that a High output level is then connected to the bus. This will not affect the data transfer initiated by the winning master. As control of the 12c bus is decided solely on the address and data sent by competing masters, there is no central master, nor any order of priority on the bus.
Use of the Clock Synchronizing Mechanism as a Handshake
In addition to being used during the arbitration procedure, the clock synchronization mechanism can be used to enable receiving devices to cope with fast data transfers, either on a byte or bit level.

Fonnats
Data transfers follow the format shown in Figure 9. After the start condition, a slave address Is sent. This address is 7 bits long; the eighth bit is a data direction bit (R/W). A zero indicates a transmission (WRITE); a one indicates a request for data (READ). A data transfer is always terminated by a stop condition generated by the master. However, if a master still wishes to communicate on the bus, it can generate another start condition, and address another slave without first generating a stop condition. Various combinations of read/write formats are then possible within such a transfer.
At the moment of the first acknowledge, the master transmitter becomes a master receiver and the slave receiver becomes a slave transmitter. This acknowledge is still generated by the slave.
The stop condition is generated by the master.
During a change of direction within a transfer, the start condition and the slave address are both repeated, but with the R/W bit reversed.

such a way that the master which transmits a

II

December 1988

810

Signetics RF Communications
12c Bus specification

CLK 1
CLK 2
SCL
Data 1
Data 2
SDA
SCL

;-
Counter Reset

Start Counting

Walt State

- - - - - 1 - -Hig-h -Period

_,1,_ _ _""'\....______

-'

Figure 7. Clock Synchronization During the Arbitration Procedure
T!:lll'\"~~J. Looea Arbitration

Figure 8. Arbitration Procedure of Two Masters

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Signetics RF Communications
12c Bus specification

r - - ..

' - - ..

-'~~~tx=x=Alj'

S' Clnt.~~tv:vif:

'. -~ ; "---y--J L-y-l "----v--J

Start

Add..,..

R/W

Condition

ACK

L-.,-1 '----v------..J "----v--J '. _P_ ;

Data

ACK

Data

ACK

Stop

Condition

Figure 9. Complete Data Transfer
Posslble Data Transfer Formats Are:

a) Master transmitter transmits to slave receiver. Direction Is not changed.

sA --

Acknowledge Start

p. Slop

b) Master reads slave lmmedlately after first byte.

s

Slave AddreM

A

Data

A Data

A

p

�o� (Write)

~~~~~lrl~~~~
Da� Tranaterred (n Byte� + Aclcnowtedge)

s

Slave Addreae

A

Date

A

A

p

'1'(Read)

~~~~~-...ltl~~~~~-
Data Tranelerred (n Bytes + Aclcnowledge)

c) Conilined formats.

J ~t3 +Acknowledge)
Read or Write

J
Read or Write

I~~,

[

Direction of

Treneler May

Change at

Thie Point

NOTES: 1. Col'Tblned formats can be used, for example, to control a serial memory. During the first data byte, the Internal memory location has to be written. After the start condition
is repeated, data can then be transferred. 2. All decisions on au~lncrement or decrement of previously accessed memory locations, etc., are taken by the designer of the device. 3. Each byte Is followed by an acknowledge as Indicated by the A blocks in the sequence.
4. i2c devices have to reset their bus loglc on receipt of a start condition so that they all anticipate the sending of a slave address.

December 1988

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Signetics RF Communications
12c Bus specification

ADDRESSING
The first byte after the start condition determines which slave will be selected by the master. Usually, this first byte follows that start procedure. The exception is the general call address which can address all devices. When this address is used, all devices should, in theory, respond with an acknowl-

edge, although devices can be made to ignore this address. The second byte of the general call address then defines the action to be taken.
Definition of Bits In the First Byte
The first seven bits of this byte make up the slave address (Figure 1OJ. The eighth bit

(LSB-least significant bit) determines the direction of the message. A zero on the least significant position of the first byte means that the master will write information to a selected slave; a one in this position means that the master will read information from the slave.

MSB

LSB

Slave AddreM
Figure 10. The First Byte After the Start Procedure

When an address is sent, each device in a system compares the first 7 bits after the start condition with its own address. If there is a match, the device will consider itself addressed by the master as a slave receiver or slave transmitter, depending on the R/W bit.
The slave address can be made up of a fixed and a programmable part. Since it is expected that identical !Cs will be used more than once in a system, the programmable pan of the slave address enables the maximum possible number of such devices to be connected to the 12C bus. The number of programmable address bits of a device depends on the number of pins available. For example, if a device has 4 fixed and 3 programmable address bits, a total of eight identical devices can be connected to the same bus.
The 12C bus committee is available to coordinate allocation of 12C addresses.
The bit combination 1111XXX of the slave address is reserved for future extension purposes.
The address 1111111 is reserved as the extension address. This means that the addressing procedure will be continued in the next byte(s). Devices that do not use the ex-

tended addressing do not react at the reception of this byte. The seven other possibilities in group 1111 will also only be used for extension purposes but are not yet allocated.
The combination OOOOXXX has been defined as a special group. The following addresses have been allocated:

FIRST BYTE

SLAVE ADDRESS

RIW

0000 000 0 General call address 0000 000 1 Start byte

0000 001 0000 010

x CBUS address x Address reserved for
different bus format

x 0000 011

0000 100 0000 101 0000 110 0000 111

x x x x

To be defined To bedefined To be defined To be defined

No device is allowed to acknowledge at the reception of the start byte.
The CBUS address has been reserved to enable the intermixing of CBUS and 12C devices

in one system. J2C bus devices are not allowed to respond at the reception of this address.
The address reserved for a different bus format is included to enable the mixing of 12C and other protocols. Only 12C devices that are able to work with such formats and protocols are allowed to respond to this address.
General Call Address The general call address should be used to address every device connected to the 12c bus. However, if a device does not need any of the data supplied within the general call structure, it can ignore this address by not acknowledging. If a device does require data from a general call address, it will acknowledge this address and behave as a slave receiver. The second and following bytes will be acknowledged by every slave receiver capable of handling this data. A slave which cannot process one of these bytes must ignore it by not acknowledging. The meaning of the general call address is always specified in the second byte (Figure 11).

FlratByte (General Call Addreea)

x
Second Byte

Figure 11. General Call Address Format

December 1988

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Signetics RF Communications
12c Bus specification

There are two cases to consider: 1. When the least significant bit is a zero.
2. When the least significant bit is a one.
When B is a zero, the second byte has the following definition:
0000011 O(H'06') Reset and write the programmable part of slave address by software and hardware. On receiving this two-byte sequence, all devices (designed to respond to the general call address) will reset and take in the programmable part of their address. Precautions must be taken to ensure that a device is not pulling down the SDA or SCL line after applying the supply voltage, since these low levels would block the bus.
00000010 (H'02') Write slave address by software only. All devices which obtain the programmable part of their address by software (and which have been designed to respond to the general call

address) will enter a mode in which they can be programmed. The device will not reset.
An example of a data transfer of a programming master is shown in Figure 12 (ABCD represents the iixed pan oi me addressj.
00000100 (H'04') Write slave address by hardware only. All devices which define the programmable part of their address by hardware (and which respond to the general call address) will latch this programmable part at the reception of this two-byte sequence. The device will not reset.
00000000 ('HOO') This code is not allowed to be used as the second byte.
Sequences of programming procedure are published in the appropriate device data sheets.
The remaining codes have not been fixed and devices must ignore these codes.
When B is a one, the two-byte sequence is a hardware general call. This means that the

sequence is transmitted by a hardware master device, such as a keybcard scanner, which cannot be programmed to transmit a desired slave address. Since a hardware master does not know in advance to which device the message must be transferred, it can only generate this hardware general call and its own address, thereby identifying itself to the system (Figure 13).
The seven bits remaining in the second byte contain the device address of the hardware master. This address is recognized by an intelligent device, such as a microcomputer, connected to the bus which will then direct the information coming from the hardware master. If the hardware master can also act as a slave, the slave address is identical to the master address.
In some systems an alternative could be that the hardware master transmitter is brought in the slave receiver mode after the system reset. In this way, a system configuring master can tell the hardware master transmitter (which is now in slave receiver mode) to which address data must be sent(Figure 14). After this programming procedure, the hardware master remains in the master transmitter mode.

H'O&'

I s

I H'02'

A

ABCD001

Figure 12. Sequence of a Programming Master

I s

00000000

A I

'----v-----'
General Call Addntea

Maeler Addreae Second Byte

(B)

I I

1

A

Dita

I A

Data

AIp I

l
~n Bytea + Aclcnowledge)

Figure 13. Data Transfer From Hardware Master Transmitter

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Signetics RF Communications
12c Bus specification

Sl�w Addr Hl\Y Maater

Dump Addr for HIW Muter

Wrl., A. Configuring Miister Send� Dump Addreea to Hardware Maeter

s I

Slave Addr H/W Maeter

Data

Data

A

Write

(n Bytao + Acknowledge)

B. Hardware Mae1er Dumpe Data to Selected Slave Device

Figure 14. Data Transfer From Hardware Master Transmitter Capable of Dumping Data Dlrectly to Slave Devices

Start Byte Microcomputers can be connected to the 12c bus in two ways. If an on-chip hardware 12c bus interface is present, the microcomputer can be programmed to be interrupted only by requests from the bus. When the device possesses no such interface, it must constantly monitor the bus via software. Obviously, the more times the microcomputer monitors, or polls, the bus, the less time it can spend carrying out its intended function.
Therefore, there is a difference in speed between fast hardware devices and the relatively slow microcomputer which relies on software polling.

In this case, data transfer can be preceded by a start procedure which is much longer than normal (Figure 15). The start procedure consists of: 1. A start condition, (S)
2. A start byte 00000001
3. An acknowledge clock pulse
4. A repeated start condition, (Sr)
After the start condition (SJ has been transmitted by a master requiring bus access, the start byte (00000001) is transmitted. Another microcomputer can therefore sample the SDA line on a low sampling rate until one of the

seven zeros in the start byte is detected. After detection of the Low level on the SDA line, the microcomputer is then able to switch to a higher sampling rate in order to find the second start condition (Sr), which is then used for synchronization.
A hardware receiver will reset at the reception of the second start condition (Sr) and will therefore ignore the start byte.
After the start byte, an acknowledge-related clock pulse is generated. This is present only to conform with the byte-handling format used on the bus. No device is allowed to acknowledge the start byte.

Dummy Acknowledge
(High)

SCL~ 1 ,2 :

's '

.. - - - J

I

Stan By1e 00000001

Figure 15. Start Byte Procedure

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Signetics RF Communications
12c Bus specification

CBUS Compatlblllty Existing CBUS receivers can be connected to the 12c bus. In this case, a third line, called OLEN, has to be connected and the acknowledge bit omitted. Normally, 12C transmissions are multiples of 8-bit bytes; however, CBUS devices have different format.
In a mixed bus structure, 12c devices are not allowed to respond on the CBUS message. For this reason, a special CBUS address

(0000001 X) has been reserved. No 12C device will respond to this address. After the transmission of the CBUS address, the OLEN line can be made active and transmission, according to the CBUS format, can be performed (Figure 16).
After the stop condition, all devices are again ready to accept data.
Master transmitters are allowed to generate CBUS formats after having sent the CBUS

address. Such a transmission is terminated by a stop condition, recognized by all devices. In the low speed mode, full 8-bit bytes must always be transmitted and the timing of the OLEN signal adapted.
If the CBUS configuration is know and no expansion with CBUS devices is foreseen, the user is allowed to adapt the hold time to the specific requirements of device(s) used.

SCL

OLEN:

-.... '= I ' s ' ...__~~~-......~~~--'l....y-Jl..y-J --~~~~~---~~~~~~~l....y-J

Start Condition

CBUS

nDotaBlta

CBUS Lood

ACKRol-

Puloe

Clock Puloe

Figure 16. Data Format of Transmissions with CBUS Receiver/Transmitter

'
' p'

ELECTRICAL SPECIFICATIONS OF INPUTS AND OUTPUTS OF 12c DEVICES
The 12C bus allows communications between devices made in different technologies which might also use different supply voltages.
For devices with fixed input levels, operating on a supply voltage of +5V �10%, the following levels have been defined:
V1Lmax =1.5V (maximum input Low voltage) V1Hmln =3V (minimum input High voltage)
Devices operating on a fixed supply voltage different from +5 (e.g., 12L) must also have these input levels of 1.5V and 3V for Vil and V1H. respectively.
For devices operating over a wide range of supply voltages (e.g., CMOS), the following levels have been defined:
V1Lmax =0.3Voo (maximum input Low voltage) V1Hmln =0.7Voo (minimum input High voltage)

For both groups of devices, the maximum output Low value has been defined:
VoLmax =0.4V (max. output voltage Low) at 3mA sink current)
The maximum low-level input current at VoLmax of both the SDA pin and the SCL pin of an 12C device is -1 O�.A, including the leakage current of a possible output stage.
The maximum high-level input current at 0.9Voo of both the SDA pin and SCL pin of an 12C device is 1O�.A, including the leakage current of a possible output stage.
The maximum capacitance of both the SDA pin and the SCL pin of an 12c device is 1OpF.
Devices with fixed input levels can each have their own power supply of +5V �10%. Pull-up resistors can be connected to any supply (see Figure 17).
Howeve~ the devices with input levels related to V00 must have one common supply line to

which the pull-up resistor is also connected (see Figure 18).
When devices with fixed input levels are mixed with devices with Voo-related levels, the latter devices have to be connected to one common supply line of +5V �10% along with the pull-up resistors (Figure 19).
Input levels are defined in such a way that: 1. The noise margin on the Low level is 0.1
Voo.
2. The noise margin on the High level is 0.2 Voo-
3. Series resistors (Rs) up to 3000 can be used for flash-over protection against high voltage spikes on the SDA and SCL line (due to flash-over of a TV picture tube, for example) (Figure 20).
The maximum bus capacitance per wire is 400pF. This includes the capacitance of the wire itself and the capacitance of the pins connected to it.

December 1988

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Signetics RF Communications
12c Bus specification

Voo1... =SY� 10%

SDA SCL
Figure 17. Fixed Input Level Devices Connected to the 12c Bus
Voo=��Sll��3V
SOA SCL
Figure 18. Devices with a Wide Range of Supply Voltages Connected to the 12c Bus

Voo1 � SY� 10%

Voo2 = SY � 10%

Vo03 =SY� 10%

SOA SCL
Figure 19. Devices with Yoo Related Levels Mixed with Fixed Input Level Devices on the 12C Bua

Yoo

Yoo

SOA SCL

Rp

Rp

Figure 20. Serlal Resistors (Rs) for Protection Against High Voltage

December 1988

817

Signetics RF Communications
12c Bus specification

TIMING The clock on the 12C bus has a minimum Low period of 4. 7�s and a minimum High period of 4�s. Masters in this mode can generate a bus clock with a frequency from 0 to 100kHz.
AU de-..icas c:cnnacted to the bus must be ab!e to follow transfers with frequencies up to 1OOkHz, either by being able to transmit or receive at that speed or by applying the clock synchronization procedure which will force the master into a wait state and stretch the Low periods. In the latter case the frequency is reduced.
Figure 21 shows the timing requirements in detail. A description of the abbreviations used is shown in Table 2. All timing references are at V1Lmax and V1Lmln�

LOW-SPEED MODE As explained previously, there is a difference in speed on the 12C bus between fast hardware devices and the relatively slow microcomputer which relies on software polling. For this reason a low speed mode is available on the 12C bus to allow these microcomputers to poll the bus less often.
Start and Stop conditions
In the low-speed mode, data transfer is preceded by the start procedure.
Data Format and Timing
The bus clock in this mode has a Low period of 130�s +25�s and a High period of 390�s

+25�s, resulting in a dock frequency of approximately 2kHz. The duty cycle of the dock has this Low-to-High ratio to allow for more efficient use of microcomputers without an on-chip hardware 12C bus interface. In this mode also, data transfer with acknowledge is obligatory. The maximum number of bytes transferred Is not limited (Figure 22).
In this mode, a transfer cannot be terminated during the transmission of a byte.
The bus is considered busy after the first start condition. It is considered free again one minimum dock Low period, 105�s, after the detection of the stop condition. Figure 23 shows the timing requirements in detail Table 3 explains the abbreviations.

r- - ,
'
SDA

r- - ,
'

r - - ..
'

SCL ,

�~DjSTA:'

I

1 pI
�--J

I 8I
~--J

, , ISU;STA ' Sr '

ISU;STO

' p'

Figure 21. Timing Requirements for the 12C Bus

December 1988

818

Signetics RF Communications
12c Bus specification

Table 2. Timing Requirement for the 12C Bus

SYMBOL

PARAMETER

LIMITS

MIN

MAX

fscL teuF IHO;STA It.ow !HIGH lsu;STA IHD;DAT

SOL clock frequency

0

100

lime the bus must be free before a new transmission can start

4.7

Hold time start condition. After this period the first clock pulse is generated

4

The Low period of the clock

4.7

The High period of the clock

4

Setup time for start condition (only relevant for a repeated start condition)

4.7

Hold time DATA

for CBUS compatible masters for 120 devices

o5 �

tsu;DAT tR IF

Setup time DATA Rise time of both SDA and SOL lines Fall time of both SDA and SOL lines

250 1
300

tsu�sro

Setup time for stop condition

4.7

NOTES:

All values referenced to V1H and V1L levels.

� Note that a transmitter must Internally provide a hold time to bridge the undefined region (300ns max.) of the falling edge of SOL.

UNIT
kHz �s �s �s �s �s
�s �s ns �s ns �s

s....
Condition SDA

s.... ayio

-y
Acknowledge
(Hgh}

Rope-
s-

-

ACK

~Ilion

Figura 22. Data Transfer Low-Spead Mode

Dota

ACK

Stop

nBytee

Concltion

r- -�
'

,--�
'

1 �au~

SCL

':ffD;srA

p,

s,

Figure 23. Timing Low-Spead Mode

'
:

Sr

'

�su;STA

�su;STO

' p'

December 1988

819

Signetics RF Communications
12c Bus specification

LOW SPEED MODE
CLOCK DUTY CYCLE
START BYTE MAX. NO. OF BYTES PREMATURE TERMINATION OF TRANSFER ACKNOWLEDGE CLOCK BIT ACKNOWLEDGMENT OF SLAVES

It.ow= 130�s � 25�s IHIGH = 390�s � 25�s 1:3 Low-to-High (Duty cycle of clock generator)
00000001
UNRESTRICTED NOT ALLOWED ALWAYS PROVIDED
OBLIGATORY

Table 3. Timing Low-Speed Mode

SYMBOL

PARAMETER

LIMITS

MIN

MAX

teuF IHD;STA IHD;STA ILQW

Time the bus must be free before a new transmission can start

105

Hold time start condition. After this period the first clock pulse is generated

365

Hold time (repeated start condition only)

210

The Low period of the clock

105

155

IHIGH lsu;STA tHo; loAT

The High period of the clock

365

415

Setup time for start condition (only relevant for a repeated start condition)

105

155

Hold time DATA

for CBUS compatible masters

5

for 12c devices

o�

lsu;DAT IA

Setup time DATA Rise time of both SDA and SCL lines

250 1

IF

Fall time of both SDA and SCL lines

300

lsu�STO

Setup time for stop condition

105

155

NOTES:

All values referenced to V1H and V1L levels.

� Note that a transmitter must internally provide a hold time to bridge the undefined region (300ns max.) of the falling edge of SCL.

UNIT
�s �s �s �s �s �s
�s �s ns �s ns �s

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Signetics RF Communications
12c Bus specification

APPENDIX 1 Maximum and minimum values of the pull-up resistors Rp and series resistors Rs (see Figure 20).
In an 12c bus system these values depend on the following parameters: - Supply voltage
- Bus capacitance
- Number of devices (input current + leakage current)
1.The supply voltage limits the minimum value of the Rp resistor due to the speci� fied 3mA as minimum sink current of the output stages, at 0.4V as maximum low wltage. In graph 1, Voo against Rpm1n is shown .

The desired noise margin of 0.1 Voo for the low level limits the maximum value of Rs.
In Graph 2, Rsmax against Rp is shown.
2. The bus capacitance is the total capacitance of wire, connections, and pins. This capacitance limits the maximum value of Rp because of the specified rise timeof 1�s.
In Graph 3, the bus capacitance-Rpmax relationship is shown.
3. The maximum high-level input current of each input/output connection has a specified value of 1O�A max. Due to the desired noise margin of 0.2 Voo for the

high level, this input current limits the maximum value of Rp. This limit is dependent on Voo.
In Graph 4 the total high-level input current-Rpmax relationship is shown.
12CLICENSE Purchase of Signetics or Philips 12c components conveys a license under the Philips 12c patent rights to use these components in an 12c system, provided that the system conforms to the 12C standard specification as de� fined by Philips.

�
s
..i 4
~
i
i 2

0 0
llO
11
i..fir...
i 12
ill
;i 8
4 0
0

4

8

12

Voo(Y)

Graph 1

100

200

300

BUS CAPACrrANCE (pf)

Graph3

December 1988

0

0

400

800

1200

1800

MAXIMUM VALUE Rs (ll)
18

Graph 2

llO

i 11
.fir.
... 12
;II
ill
; i
4

0

400

0

40

80

11111

180

200

TOTAL llGH LEVEL INPUT CURRENT (II�')

Graph4

821

Slgnetlcs RF Communications
The inter-integrated circuit (12C) serial bus: theory and practical consideration

Application note
AN168

Author: Carl Fenger
INTRODUCTION The 12c (Inter-IC) bus is becoming a popular concept which implements an innovative serial bus protocol that needs to be understood. On the hardware level 12C is a collection of microcomputers (MAB8400, PCD3343, 83C351, 84CXX) and peripherals (LCD/LED drivers, RAM, ROM, clock/timer, AID, DIA, IR transcoder, 110, DTMF generator, and various tuning circuits) that communicate serially over a two-wire bus, serial data (SDA) and serial clock (SCL). The 12C structure is optimized for hardware simplicity. Parallel addressand data buses inherent in conventional systems are replaced by a serial protocol that transmits both address and bidirectional data over a 2-line bus. This means that interconnecting wires are reduced to a minimum; only Vee. ground and the two-wire bus are required to link the controller(s) with the peripherals or other controllers. This results in reduced chip size, pin count, and interconnections. An 12c system is therefore smaller, simpler and cheaper to implement that its parallel counterpart.
The data rate of the 12C bus makes it suited for systems that do not require high speed. An 12C controller is well suited for use in systems such as television controllers, telephone sets, appliances, displays or applications involving human interface. Typically an 12c system might be used in a control function where digitally-controllable elements are adjusted and monitored via a central processor.
The 12C bus is an innovative hardware interface which provides the software designer the flexibility to create a truly multi-master environment. Built into the serial interface of the controllers are status registers which monitor all possible bus conditions: bus free/busy, bus contention, slave acknowledgement, and bus interference. Thus an 12C system might include several controllers on the same bus each with the ability to asynchronously communicate with peripherals or each other. This provision also provides expandability for future add-on controllers. (The 12c system is also ideal for use in environments where the bus is subject to noise. Distorted transmissions are immediately detected by the hardware and the information presented to the software.) A slave acknowledgement on every byte also facilitates data integrity.

An 12C system can be as simple or sophisticated as the operating environment demands. Whether in a single master or multi-master system, noisy or 'safe', correct system operation can be insured under software control. "
CONTROLLERS Cunrently the family of 12c controllers include the MAB8400, and the PCD3343 (the PCD3343 is basically a CMOS version of the MAB8400). The MAB8400 is based on the 8048, with a few instructions added and a few deleted. Tables 1 and 2 summarize the differences.
Programs for the MAB8400 and PCD3343 may be assemmbled on an 8048-assembler using the macros listed in Appendix A. The serial 1/0 instructions involve moving data to and from the SO, S 1, and S2 serial 1/0 control registers. The block diagram of the 12c interface is shown in Figure 1.
SERIAL 1/0 INTERFACE A block diagram of the Serial Input/Output (SIO) is shown in Figure 1. The clock line of the serial bus (SCL) has exclusive use of Pin 3, while the Serial Data (SDA) line shares Pin 2 with parallel 1/0 signal P23 of port 2. Consequently, only three 1/0 lines are available for port 2 when the 12C interface is enabled.

Communication between the microcomputer and interface takes place via the internal bus of the microcomputer and the Serial Interrupt Request line. Four registers are used to store data and information controlling the operation of the interface:
� data shift register so
� address register so�
� status register S 1
� clock control register S2
THE 12c BUS INTERFACE SERIAL CONTROL REGISTERS SO, S1
All serial 12C transfers occur between the accumulator and register SO. The 12c hardware takes care of clocking out/in the data, and receiving/generating an acknowledge. In addition, the state of the 12C bus is controlled and monitored via the bus control register S1. A definition of the registers is as follows:

Table 1. MAB8400 Family Instructions not In the MAB8048 Instruction Set

SERIALl/O
MOVA.Sn MOVSn,A MOV Sn,#data ENSI DISS!

REGISTER
DEC@Rr DJNZ @Rr,addr

CONTROL
SELMB2 SELMB3

CONDITIONAL BRANCH
JNTF addr

Table 2. MAB8048 Instructions not In the MAB8400 Family Instruction Set

DATA MOVES
MOVXA,@R MOVX@R,A MOVP3A,@A MOVDA,P MPVD P,A ANLD P,A ORLD P,A

FLAGS
CLRFO CPLFO CLRF1 CPLF1

BRANCH *JNI addr JFOaddr JF1 addr
'replaced by JTO, JNTO

CONTROL ENTOCLK

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Signetics RF Communications
The inter-integrated circuit (12C) serial bus: theory and practical consideration

Application note
AN168

E DIG. FILTER
DATA

810 INTERRUPT 1 - - - - - - - + 1 LOGIC

8400 INTERRUPT
LOGIC

WRSO ,___.__,__.._-*-__._...__.___,c...,..._,...-,RDSO

INTREQ ENSI DISSI

INITIALIZE (Pin 17)
o - - - - - + RESET

PIN INTERNAL MICROCOMPUTER BUS

DIG FILTER CLOCK

CLOCK SYNC LOGIC
CON~ROL

CLOCK

BIT7
S1

WRS1 RDS1

SERIAL CLOCK PULSE GENERATOR

-----INTERNAL CLOCK

Figure 1. Block Diagram of the MAB8400 SIO Interface

Data Shift Reglater SO - SO is the data shift register used to perform the conversion between serial and parallel data format. All transmissions or receptions take place through register SO MSB first. All 12C bus receptions or transmissions involve moving data to/from the accumulator from/to SO.
Addresa Reglater SO' - In multi-master systems, this register is loaded with a controlle~s slave address. When activated, (ALS = 0). the hardware will recognize when it is being addressed by setting the AAS (Addressed As Slave) flag. This provision allows a master to be treated as a slave by other masters on the bus. Status Register St - St is the bus status register. To control the SIO interface, information is written to the register. The lower 4 bits in St serve dual purposes; when

written to, the control bits ESO, BC2, Bc1, BcO are programmed (Enable Serial Output and a 3-bit counter which indicates the current number of bits left in a serial transfer). When reading the lower four bits, we obtain the status information AL, AAS, ADO, LRB (Arbitration Lost, Addressed As Slave, Address Zero (the general call has been received). the Last Received Bit (usually the acknowledge bit)). The upper 4 bits are the MST, TRX, BB and PIN control bits (Master, Transmitter, Bus Busy, and Pending Interrupt Not). These bits define what role the controller has at any particular time. The values of the master and transmitter bits define the controller as either a master or slave (a master initiates a transfer and generates the serial clock; a slave does not). and as a transmitter or receiver. Bus Busy

keeps track of whether the bus is free or not, and is set and reset by the 'Start' and 'Stop' conditions which will be defined. Pending Interrupt Not is reset after the completion of a byte transfer+ acknowledge, and can be polled to indicate when a serial transfer has been completed. An alternative to polling the PIN bit is to enable the serial interrupt; upon completion of a byte transfer, an interrupt will vector program control to location 07H.
SERIAL CLOCK/ACKNOWLEDGE CONTROL REGISTER S2 Register S2 contains the clock-control register and acknowledge mode bit. Bits S20-S24 program the bus clock speed. Bit S26 programs the acknowledge or not-acknowledge mode (1/0). The various

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The inter-integrated circuit (12C) serial bus: theory and practical consideration

Application note
AN168

12c bus clock speed possibilities are shown in Table3.

Table 3. Clock Pulse Frequency Control When Using a 4.43MMHz Crystal

HEX S20-S24 CODE

DIVISOR

APPROX. fctocK (kHz)

0

0

0

1

39

114

2

45

98

3

51

87

4

63

70

5

75

59

6

87

51

7

99

45

8

123

36

9

147

30

A

171

26

B

195

23

c

243

18

D

291

15

E

339

13

F

387

11

10

483

9.2

11

579

7.7

12

675

6.6

13

771

5.8

14

963

4.6

15

1155

3.8

16

1347

3.3

17

1539

2.9

15�

1923

2.3

19�

2307

1.9

1A�

2691

1.7

1B�

3075

1.4

1C

3843

1.2

1D

4611

1.0

1E

5379

0.8

1F

6147

0.7

�only values that may be used In the tow speed mode (ASC� 1)

These speeds represent the frequency of the serial clock bursts and do not reflect the speed of the processor's main clock (i.e., it controls the bus speed and has no effect on the CPU's execution speed).

The losing Master is now configured as a slave which could be addressed during this very same cycle. These provisions allow for a number of microcomputers to exist on the same bus. With properly written subroutines, software for any one of the controllers may regard other masters as transparent
12c PROTOCOL AND ASSEMBLY LANGUAGE EXAMPLES
12C data transfers follow a well-defined protocol. A transfer always takes place between a master and a slave. Currendy a microcomputer can be master or slave, while the 'CLIPS' peripherals are always salves. In a 'bus-free' condition, both SCL and SDA lines are kept logical high be external pull-up resistors. All bus transfers are bounded by a 'Start' and a 'Stop' condition. A 'Start' condition is defined as the SDA line making a high-to-low transition whlle the SCL llne Is high. At this point, the internal hardware on all slaves are activated and are prepared to clock-in the next 8 bits and interpret it as a
7-bit address and a R/W control bit (MSB first). All slaves have an internal address 12c
data transfers follow a well-defined protocol. A transfer always takes place between a master and a slave. Currently a microcomputer can be master or slave, while the 'CLIPS' peripherals are always salves. In a 'bus-free' condition, both SCL and SDA lines are kept logical high be external pull-up resistors. All bus transfers are bounded by a 'Start' and a 'Stop' condition. A 'Start' condition is defined as the SDA line making a high-to-low transition whlle the SCL llne Is high. At this point, the internal hardware on

all slaves are activated and are prepared to clock-in the next 8 bits and interpret it as a
7-bit address and a R/W control bit (MSB
first). All slaves have an internal address (most have 2 - 3 programmable address bits) which is then compared with the received address. The slave that recognized its address will respond by pulling the data line low during a ninth clock generated by the master (all 12C byte transfers require the master to generate 8 clock pulses plus a ninth acknowledge-related clock pulse). The slave-acknowledge will be registered by the
master as a �o� appearing in the LRB (Last
Received Bit) position of the S1 serial 1/0 status register. If this bit is high after a transfer attempt, this indicates that a slave did not acknowledge and that the transfer should be repeated. After the desired slave has acknowledged its address, it is ready to either send or receive data in response to the master's driving clock. All other slaves have withdrawn from the bus. In addition, for multi-master systems, the start condition has set the 'Bus Busy' bit of the serial 1/0 register S1 on all masters on the bus. This gives a software indication to other master that the bus is in use and to wait until the bus is free before attempting an access.
Vee

BUS ARBITRATION
Due to the wire-AND configuration of the 12c bus, and the self-synchronizing clock circuitry of 12C masters, controllers with varying clock speeds can access the bus without clock contention. During arbitration, the resultant clock on the bus will have a low period equal to the longest of the low periods; the high period will equal the shortest of the high periods. Similarly, when two masters attempt to drive the data line simultaneously, the data is 'ANDed', the master generating a low while the other is driving a high will win arbitration. The resultant bus level will be low, and the loser will withdraw from the bus and set its 'Arbitration Lost' flag (S1 bit 3).

SCL SDA

MAB 8400

Ao

PCF 8574

A,

Ao

PCB
8570

A1

Az

Az

-=-
11111111 '40'H llOEXPANDOR ADDR:

-=-
":mi\\~:frl�HEI

Figure 2. Schematic for Assembly Examples

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The inter-integrated circuit (12C) serial bus: theory and practical consideration

Application note
AN168

RD.wll

SDA

I

I

I

I

I

I

I

I

SCLI --nmuuuuuuI trIlll--nJUlJUlJUUUl.....,.....___I .I

i I

ADDRESS '40H'

i I

I I

START CONDITION

I I

DATA '2AH'

I i

I I

STOP CONDITION

MOVS1,#18H
MOY SI, #OF8H CALLACKWT:
MOVA,#2AH MOVSO,A CALLACKWT: MOVS1,#0D8H

:Initialize S1�Slave, Receiver, Bue not :-y. Enable Serial UO :Preloac:I SO with Slave'� acl*eM & :R/Wblt :Invoke �tart condition & slave adlhu :(Mllater, Tnnemitter, Bua Buey, Enable
:Seriol UO, Bit Counter= 000) :Check for 1raMmiulon complele, �ck :received, no arbitration, ate. :Gel a-byte :T>onomit data byle :Walt for tnrnarniaaion complete again :Generate Stop condition
:(Muter, Tranemltter, Bua not Buey)

Flgure3

There are two types of 12c peripherals that now must be defined: there are those with only a chip address such as the 1/0 expander, PCF8574, and those with a chip address plus an internal address such as the static RAM, PCF8570. Thus after sending a start condition, address, and RIW bit, we must take into account what type of slave is being addressed. In the case of a slave with only a chip address, we have already indicated its address and data direction (RIW) and are therefore ready to send or receive data. This is perfonned by the master generating bursts of 9 clock pulses for each byte that is sent or received. The transaction for writing one byte to a slave with a chip address only is shown in Figure 3.
In this transfer, all bus activity is invoked by writing the appropriate control byte to the serial 1/0 control register S1, and by moving data to/from the serial bus buffer register SO. Coming from a known state (MOV S 1, #1 SH-Slave, Receiver, Bus not Busy) we first load the serial 1/0 buffer SO with the desired slave's address (MOV SO, #40H). To transmit this preceded by a start condition,

we must first examine the control register S1, the transfer by setting the 'Bus Busy' bit,

which, after initialization, looks like this:

clears the Pending Interrupt Not (an inverted

MAS-

BUS

TEA TRANS BUSY PIN ESO BC2 BCI BCO

1�1�1�1 1 11 1�1�1�1

To transmit to a slave, the Master,

flag indicating the completion of a compete byte transfer), and activates the serial output logic by setting the Enable Serial Output (ESO)bit.

Transmitter, Bus Busy, PIN (Pending Interrupt Not), and ESO (Enable Serial Output) must be set to a 1. This results in an 'FSH' being written to S1. This word defines the controller as a Master Transmitter, invokes

BIT COUNTER S12, S11, S10
BC2, BC 1 and BCD comprise a bit-counter which indicates to the logic how long the word is to be clocked out over the serial data line. By setting this to a OOOH, we are telling

Table 4. Binary Numbers In Bit-Count Locations BC2, BC1 and BCO

BC2

BC1

BCO

BITS/BYTE WITHOUT ACK

BITS/BYTE WITH ACK

0

0

1

1

2

0

1

0

2

3

0

1

1

3

4

1

0

0

4

5

1

0

1

5

6

1

1

0

6

7

1

1

1

7

8

0

0

0

8

9

December 1991

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Signetics RF Communications
The inter-integrated circuit (12C) serial bus: theory and practical consideration

Application note
AN168

it to produce 9 clocks (8 bits plus an acknowledge clock) for this transfer. The bit counter will then count off each bit as it is transmitted. The bit counter possibilities are shown in Table 4.
Thus the bit counter keeps track of the number of clock pulses remainina in a serial transfer. Additionally, there is a not-acknowledge mode (controlled through bit 6 of clock control register S2) which inhibits the acknowledge clock pulse, allowing the possibility of straight serial transfer. We may thus define the word size for a serial transfer (by pre-loading BC2, BC 1, BCO with the appropriate control number), with or without an acknowledge-related clock pulse being generated. This makes the controller able to transmit serial data to most any serial device regardless of its protocol (e.g., C-bus devices).
CHECKING FOR SLAVE ACKNOWLEDGE After a 'Start' condition and address have been issued, the selected slave will have recognized and acknowledged its address by pulling the data line low during the ninth clock pulse. During this period, the software (which runs on the processor's 4MHz clock) will have been either waiting for the transfer to be completed by polling the PIN bit in S1 which goes low on completion of a transfer/reception (whose length is defined by the pre-loaded Bit-counter value), or by the hardware in Serial Interrupt mode.. The serial interrupt (vectored to 07H) is enabled via the EN SI (enable serial interrupt) instruction.
At the point when Pl N goes low (or the serial interrupt is received) the 9-bit transfer has been completed. The acknowledgement bit will now be in the LRB position of register S1, and may be checked in the routine 'ACKWT' (Wait for Acknowledge) as shown in Figure 4.
This routing must go one step further in multi-master systems; the possibility of an Arb_itration Lost situation may oocur if other masters are pre.sent on the bus. This condition may be detected by checking the 'AL' bit (bit 3). If arbitration has been lost, provisions for re-attempting the transmission should be taken..If arbitration is lost, there is the possibility that the controller is being addressed as a Slave. If th is condition is to be recognized, we must test on the 'AAS' bit
(bit 2). A 'General Call' address (OOH) has also been defined as an 'all-call' address for all slaves; bit1, ADO, must be tested if this feature is to be recognized by a Master.

ACKWT:

MOVA,S1 JB4ACKWT
JBOBUSERR RET

Figure4

;Get bus status word ;fromS1. ;Poll the PIN bit ;until it goes low ;indicating transfer ;completed ;Jump to BUSERR ;routine ii acknowledge ;not received. ;transfer complete, ;acknowledge received - return.

After a successful address transfer/acknowledge, the slave is ready to be sent its data. The instruction MOV SO,A will now automatically send the contents of the accumulator out on the bus. After calling the ACKWT routine once more, we are ready to terminate the transfer. The Stop condition is created by the instruction 'MOV S1, #OD8H'. This re-sets the bus-busy bit, which tells the hardware to generate a Stop - the data line makes a low-te>-high transition while the clock remains high. All bus-busy flags on other masters on the bus are reset by this signal.
The transfer is now complete - PCF8574 1/0 Expander will transfer the serial data stream to its 8 output pins and latch them until further update.
MASTER READS ONE BYTE FROM SLAVE A read operation is a similar process; the address, however, will be 41H, the LSB indicating to the 1/0 device that a read is to be performed. During the data portion of a read, the 1/0 port 8574 will transmit the contents of its latches in response to the clock generated by the master. The Master/Receiver in this case generates a low-level acknowledge on reception of each byte (a 'positive� acknowledge). Upon completion of a read, the master must generate a 'negative' acknowledge during the ninth clock to indicate to the slaves that the read operation is finished. This is necessary because an arbitrary number of bytes may be read within the same transfer. A negative acknowledge consists of a high signal on the data line during the ninth clock of the last byte to be read. To accomplish this, the master 8400 must leave the acknowledge mode just before the final byte, read the final byte (producing only 8 clock pulses), program the bit-counter with 001 (preparing for a one-bit negative acknowledge pulse), and simply mqve the contents of SO to the

aocumulator. This final instruction accomplishes two things simultaneously: it transfers the final byte to the aocumulator and produces one clock pulse on the SCL line. The structure of the serial 1/0 register SO is such that a read from it causes a double-buffered transfer from the 12C bus to SO, while the original contents of SO are transferred to the accumulator. Because the number of clocks produced on the bus is determined by the control number in the Bit Counter, by presetting it to 001, only one clock is generated. At this point in time the slave is-still waiting for an acknowledge; the bus is high due to the pull-up, as single clock pulse in this condition is interpreted as a 'negative' acknowledge. The slave has now been informed that reading is completed, a Stop condition is now generated as before. The read process (one byte from a slave with only a chip address) is shown in Figure 5.
These examples apply to a slave with a chip address - more than one byte can be written/read within the same transfer; however, this option is more applicable to 12c devices with sub-addresses such as �the static RAMs or Clock/Calendar. In the case of these types of devices, a slightly diffBrent protocol is used. The RAM, for example, requires a chip address and an internal memory location before it can deliver or accept a byte of information. During a write operation, this is done by simply writing the secondary address right after the chip address - the peripheral is designed to interpret the second byte as an internal address. In the case of a Read operation, the slave peripheral must send data back tot he Master after it has been addressed and sub-addressee;!. To accomplish this, first the Start, Address, and Sub-address is transmitted. Then we have repeated start condition to reverse .the direction of the data transfer, followed by the chip address and RD, than a data string (w/acknowledges). This repeated Start does not affect other peripherals - they have been deactivated and

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The inter-integrated circuit (12C) serial bus: theory and practical consideration

RD

SDA

I I

ACKNOWLEDGE

SCL
I I I I I I START I CONDITION

WAIT:

MOVS1,#18H MOY SO, MOH
MOVS1,#llF8H CALLACKWT: MOVS2,#01H MOVSO,A ---~ MOVA,S1 JB4 Woll MOY S1, #OA9H
MOVSO,A - - - - - - MOVS1,#llD8H---------'

:Initialize oeriol 110 control :register
:Preload Mrlol regi�"" so
:with alave addreu and RD :control bit :Send addreea to bus along with
:...rt concition :Walt for acknowledge (u :before) :Leave acknowledge mode :Read datti from elave to SO :Toot for byte received by :leating S1 PIN bit :Woll until PIN received :Set Bit Counter to 1 and :become a receiver (A9 = :Me~ Rec, Bus Buoy, Bit Counler = :0001) :Move data to acclH'nulator and :dock out a negative :oclmOWfedge :Generole Stop Condition

Figures

Application note
AN168
I I I I STOP I CONDITION

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The inter-integrated circuit (1 2C) serial bus: theory and practical consideration

Application note
AN168

COMMUNICATION WITH PERIPHERAL REQUIRED INITIALIZE BUS STATUS
LOAD SO WITH SLAVE ADDRESS AND RD/WR BIT
START CONDITION AND TRANSMIT ADDRESS

NO

GENERATE STOP

CONDITION

SEND/RECEIVE DATA BYTE
NO

GENERATE STOP CONDITION
RETURN

MOVS1 0 #18H

WAIT1'

MDV SO, #OAOH
MOVS1,#0F8H
CALLACKWT MOVA,#DOH
MOVSO,A CALLACKWT MOVS1,#18H
MOVA,#OA1H MOVSO,A MOV S1, #OF8H
CALL ACKWT MOVA,SO CALLACKWT MOVA,SO
CALL ACKWT MDV RO,A MOVA,SO
CALLACKWT MOVRl,A
MOVS2,#01H
MOVA,SO
MOVR2,A MOVA.St JB4 WAIT! MDV SI, #ODSH MOVS2,#41H

:Initialize bua-at.atua register :Maater, Transmitter, :Bua~ot-Buey, Enable SIO, :Load SO with RAM'a chip :iliddn;n :Start cond. end tranamit :address :Wait until addre&a received :Set up for transmitting RAM :location address :Transmit firet RAM addreaa :Walt :Set up for a repeated Start :condition :Get RAM chip address & RD bit :Send out to bus 'preceded by repeeted Siert
:Wait :First data byte to SO :Wait :Second data byte to SO :And Rret data byte to Acc. :Walt :Save flrat byte In RO ffhird date by1e to SO :and aecond data byte to Acc. :Wait :Save eecond data byte :lnR1 :Leave ack. mode :Bit Counter=001 for neg ack. :Third data byle to �cc :negative ack. generated '5ove lhlrd date byle In R2 :Get bue eta.tu� :Walt until transfer complete :Stop condition :Restore acknowledge mode

Figure 6. Flowchart for Reading/Writing One Byte to an 12C Peripheral; Single-Master, Single-Address Slave

Figure7

will not reactivate until a Stop condition is detected. 12C peripherals are equipped with auto-incrementing logic which will automatically transmit or receive data in consecutive (increasing) locations. For example, to read 3 consecutive bytes to PCB8571 RAM locations 00, 01 and 02, we use the following format as shown in Figure 7.
This routine reads the contents of location 00, 01 and 02 of the PCB8571 128-byte RAM and puts them in registers RO, Rt, and R2. The auto-incrementing feature allows the programmer to indicate only a starting location, then read an arbitrary block of

consecutive memory addresses. The WAIT 1 loop is required to pell for the completion of the final byte because the ACKWT routine will not recognize the negative acknowledge as a valid condition.
BUS ERROR CONDITIONS: ACKNOWLEDGE NOT RECEIVED
In the above routines, should a slave fail to acknowledge, the condition is detected during the 'ACKWT' routine. The occurrence may indicate one of two conditions: the slave has failed to operate, or a bus disturbance has occurred. The software response to either

event is dependent on the system application. In either case, the 'BusErr' routine should reinitialize the bus by issuing a 'Stop' condition. Provision may then be taken to repeat the transfer an arbitrary number of times. Should the symptom persist, either an error condition will be entered, or a backup device can be activated.
These sample routines represent single-master systems. A more detailed analysis of multi-master/noisy environment systems will be treated in further application notes. Examples of more complex systems can be found in the 'Software Examples' manual; publication 9398 615 70011.

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The inter-integrated circuit (12C) serial bus: theory and practical consideration

Application note
AN168

APPENDIX A Only the 8048 assembler is capable of assembling MAB8400 souroa code when it has at least a "DATA" or "Define Byte" assembler directive, possibly in combination with a MACRO facility.

The new instructions can be simply defined by MACROS. The instructions which are not in the MAB8400 should not be in the MAB8400 souroa program.
An example of a macro definitions list is given here for the Intel Macro Assembler.

This list can be copied in front of a MAB8400 souroa program; the new instructions are added to the MAB8400 via its name in the op-code field and (if required) followed by an operand in the operand field.

MACRO DEFINITIONS LINE

SOURCE STATEMENT

1 $MACROFILE

2 ;MACROS FOR 8048 ASSEMBLER RECOGNITION

3 ;OF 8400 COMMANDS

4

MOVSOA

5

DB3CH

6

ENDM

7

MOVASO

8

DB OCH

9

ENDM

10

MOVS1A

11

DB3DH

12

ENDM

13

MOVASt

14

DBODH

15

ENDM

16

MOVS2A

17

DB3EH

18

ENDM

19

MOVSO

20

DB9CH,L

21

ENDM

22

MOVS1

23

DB9DH,L

24

ENDM

25

MOVS2

26

DB9EH,L

27

ENDM

28

ENSI

29

DBB5H

30

ENDM

31

DISS!

32

DB

33

ENDM

34�

35; PORT 0 INSTRUCTIONS:

36�

INAPO

37

DB

38

ENDM

39;

40

OUTPOA

41

DB

42

ENDM

43�

44

ORLPO

45

DB

46

ENDM

47;

48

ANLPO

49

DB

50

ENDM

51;

MACRO
MACRO
MACRO
MACRO
MACRO
MACROL
MACROL
MACROL
MACRO
MACRO 95H
MACRO OBH
MACRO 38H
MACROL 88H,L
MACROL 98H,L

;MOVSO,A ;MOVA.SO ;MOVS1,A ;MOVA,St ;MOVS2,A ;MOV SO,#DATA ;MOV St ,#DATA ;MOV S2,#DATA ;ENSI ;DIS SI (Disable serial interrupt)
;INA,PO ;OUTLPO,A ;ORL PO,#DATA ;ANL PO.#DATA

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The inter-integrated circuit (12C) serial bus: theory and practical consideration

Application note
AN168

MACRO DEFINITIONS (Continued) LINE

SOURCE STATEMENT

52 DATA MEMORY INSTRUCTIONS; 53 54 55 56� 57 58 59 60; 61 SELECT MEMORY BANK INSTRUCTIONS: 62 63 64 65; 66
67 68 69; 70;CONDITIONAL JUMP INSTRUCTIONS: 71 72 73 74; 75 76
n
78; 79

DECARO DB ENDM
DECAR1 DB ENDM
SELMB2 DB ENDM
SELMB3 DB ENDM
DJNZAO DB ENDM
DJNZA1 DB ENDM
JNTF

80 81 82 83;END OF MACRO DEFINITIONS

DB ENDM

MACRO OCOH
MACRO OA5H

;DEC@RO ;SELMB2

MACRO OC1H
MACRO OB5H

;SELMB2 ;SELMB3

MACROL

;DJNZ @RO,ADDR

OEOH,L AND OFFH

MACROL

;DJNZ @R1 ,ADDR

OE1 H,L AND OFFH

MACROL

;JUMP IF TIMERFLAG JS

NON ZERO

06H,L AND OFFH

December 1991

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The inter-integrated circuit (12C) serial bus: theory and practical consideration

Application note
AN168

THE 8400 INSTRUCTIONS BUILT FROM THE MACRO LIST

LOC/OBJ LINE

SOURCE STATEMENT

0000

1

2

oooooc

3+

0001 OD

5+

6

00023C

7+

8

000330

9+

10

00043E

11+

12

00059C

13+

000656

14

000790

15+

0008 9F

16

00099E

17+

OOOA ES

18

OOOBSS

19+

20

oooc 9S

21+

22

000008

23+

24

OOOE 38

25+

26

OOOF88

27+

0010 SA

28

0011 98

29+

0012 2F

30

0013 co

31+

32

0014 C1

33+

34

0015A5

3S+

36

0016 BS

37+

38

0017 EO

39+

0019 67

40

0019 E1

41+

001A FE

42

001B 06

43+

001C 89 44

ORGO MOVASO DB MOVAS1 DB MOVSOA DB MOVS1A DB MOVS2A DB MOVSO DB
MOVS1 DB
MOVS2 DB
ENS1 DB DISSI DB INAPO DB OUTPOA DB ORLPO DB
ANLPO DB
DECARO DB DECAR1 DB SELMB2 DB SELMB3 DB DJNZAO DB
DJNZA1 DB
JNTF DB
END

OCH
OOH
3CH
3DH
3EH 56H 9CH,56H

;MACRO for MOV A,S1 ;MACRO for MOV SO.A ;MACRO for MOV S1 ,A ;MACRO for MOV S2,A ;MACRO for MOV S0,#56H

9FH 9DH,9FH

;MACRO for MOV S1 ,#9FH

OEBH 9EH,OEBH

;MACRO for MOV S2,#0EBH

;MACRO for EN S1

85H

;MACRO for DIS SI

95H

;MACRO for IN A.PO

08H

;MACRO for OUTL PO,A

38H

SAH

;MACRO for ORL PO,A

88H,5AH

2FH 98H,2FH

;MACRO for ANL PO,A

;MACRO for DEC @RO

OCOH

;MACRO for DEC @R1

OC1H

;MACRO for SEL MB2

OASH

;MACRO for SEL MB3

OBSH

567H

;MACRO for DJNZ @R0,567H

OEOH,567H AND

OFFH

OEFEH

;MACRO for DJNZ @R 1,0EFEH

OE1H,OEFEH AND

OFFH

789H

;MACRO for JNTF 789H

06H, 789H AND

OFFH

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I
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Signetics RF Communications

Section 8 Complementary RF Products

NE630

INDEX
Single-pole doulbe-throw switch (SPDT) . . . . . . . . . . . . . . . . . . 835

Slgnetics RF Communications
Single pole double throw (SPOT) switch

Product specification
NE/SA630

DESCRIPTION
The NE630 is a wideband RF switch fabricated in Bi CMOS technology and incorporating on-chip CMOS/TTL compatible drivers. Its primary function is to switch signals in the frequency range DC - 1GHz from one 50Q channel to another. The switch is activated by a CMOS/TTL compatible signal applied to the enable channel 1 pin (ENCH1).
The extremely low current consumption makes the NE/SA630 ideal for portable applications. The excellent isolation and low loss makes this a suitable replacement for PIN diodes.
The NE/SA630 is available in an 8-pin dual in-line plastic package and an 8-pin SO (surface mounted miniature) package.

FEATURES
�Wideband (DC - 1GHz) �Low through loss (1dB typical at 200MHz) �Unused input is terminated internally in 50Q �Excellent overload capability (1dB gain
compression point +18dBm at 300MHz) �Low DC power (170�A from 5V supply) �Fast switching (20ns typical) �Good isolation (off channel isolation 60dB at
100MHz) �Low distortion (IP3 intercept +33dBm) �Good 50Q match (return loss 18dB at
400MHz) �Full ESD protection �Bidirectional operation

PIN CONFIGURATION

VoooB Dand N Packages OUT1

GND 2

7 AC GND

INPUT 3

6 GND

ENCH1 4

5 OUT2

APPLICATIONS
�Digital transceiver front-end switch �Antenna switch �Filter selection �Video switch �FSK transmitter

ORDERING INFORMATION
DESCRIPTION 8-Pin Plastic DIP 8-Pin Plastic SO (Surface-mount) 8-Pin Plastic DIP 8-Pin Plastic SO (Surface-mount)

TEMPERATURE RANGE 0 to 70�C 0 to 70�C
-40 to +85�C -40 to +85�C

ORDER CODE NE630N NE630D SA630N SA630D

BLOCK DIAGRAM

-- ,
'

...........-. -,---- OUTPUTnNPUT

_

______,/

I

.... - INPUT/OU~.. PUT ',

�, �~' -~�----

OUTPUTnNPUT

ENCH1

ABSOLUTE MAXIMUM RATINGS

SYMBOL

PARAMETER

Voo Supply voltage

Power dissipation, TA= 25�C (still air)1

Po

8-Pin Plastic DIP

8-Pin Plastic SO

RATING -0.5 to +5.5

UNITS
v

1160

mW

780

mW

TJMAX PMAX Tsm

Maximum operating junction temperature Maximum power inpuVoutput Storage temperature range

150 +20 -65to+150

'C dBm 'C

NOTES: 1. Maximum dissipation is determined by the operating ambient temperature and the thermal resistance, eJA:
8-Pin DIP: eJA = 108�C/W 8-Pin SO: eJA = 158�C/W

October 10, 1991

835

853-157704269

Signetics RF Communications
Single pole double throw (SPOT) switch

Product specification
NE/SA630

EQUIVALENT CIRCUIT

+svo----'--+---~

------

CONTROL LOGIC

0
----,

I

h
I

I

1 I

INPUT

o------1

>

-

-

"

-

l

>

-

+

-

-

-

-

'
-

'
--

'
-

0'

_'

-

i
I
L_

ENCH1 0-----~4+-~

20kn
sen
50'2 20kn

~ OUT1
AC BYPASS
I
~ OUT2

RECOMMENDED OPERATING CONDITIONS

SYMBOL

PARAMETER

Voo Supply voltage

Operating ambient temperature range

TA

NE Grade

SA Grade

Operating junction temperature range

TJ

NE Grade

SA Grade

RATING 3.0to5.5V
Oto +70 -40 to +85
0 to +90 -40to +105

UNITS
v oc oc
oc oc

DC ELECTRICAL CHARACTERISTICS
V00 = +5V, TA= 25�C; unless otherwise stated.

SYMBOL

PARAMETER

TEST CONDITIONS

loo Supply current

Vr

TTUCMOS logic threshold voltage1

V1H

Logic 1 level

Enable channel 1

V1L

Logic Olevel

Enable channel 2

l1L

ENCH 1 input current

ENCH1 =0.4V

l1H

ENCH 1 input current

ENCH1 = 2.4V

NOTE: 1. The ENCH1 input must be connected to a valid Logic Level for proper operation of the NE/SA630.

LIMITS

NE/SA630

MIN

TYP

MAX

40

170

300

1.1

1.25

1.4

2.0

Voo

-0.3

0.8

-1

0

1

-1

0

1

UNITS
�A
v v v
�A �A

October 10, 1991

836

Signetics RF Communications
Single pole double throw (SPOT) switch

Product specification
NE/SA630

AC ELECTRICAL CHARACTERISTICS1 � D PACKAGE
V00 = +SV, TA= 2S�C; unless otherwise stated.

LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

NE/SA630

UNITS

MIN

TYP

MAX

S21. S12 Insertion loss (ON channel)

DC-100MHz SOOMHz 900MHz

1

1.4

dB

2

2.8

S21. S12 Isolation (OFF channel)2

10MHz 100MHz SOOMHz 900MHz

70

80

60
so

dB

24

30

S11" S22 Return loss (ON channel)

DC-400MHz 900MHz

20 12

dB

S11. S22 Return loss (OFF channel)

DC-400MHz 900MHz

17 13

dB

to t,,tf
P.1dB IP3 IP2

Switching speed (on-off delay) Switching speeds (on-off rise/fall time) Switching transients 1dB gain compression Third-order intermodulation intercept Second-order intermodulation intercept

SO% TTL to 90/10% RF 90%/10% to 10%/90% RF
DC -1GHz 100MHz 100MHz

20

ns

s

ns

165

mVp.p

+18

dBm

+33

dBm

+S2

dBm

NF Noise figure (Zo = son )

100MHz 900MHz

1.0 2.0

dB

NOTE:
1. All measurements include the effects of the D package NE/SA630 Evaluation Board (see Figure 1B). Measurement system impedance is
son.
2. The placement of the AC bypass capacitor is critical to achieve these specifications. See the applications section for more details.

AC ELECTRICAL CHARACTERISTICS1 � N PACKAGE
Voo = +SV, TA= 25�C; all other characteristics similar to the D-Package, unless otherwise stated.

LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

NE/SA630

UNITS

MIN

TYP

MAX

S21. S12 Insertion loss (ON channel)

DC - 100MHz SOOMHz 900MHz

1

1.4

dB

2.S

S21, S12 Isolation (OFF channel)

10MHz 100MHz SOOMHz 900MHz

58

68

so

37

dB

1S

NF

Noise figure (Zo = son )

100MHz 900MHz

1.0 2.S

dB

NOTE: 1. All measurements include the effects of the N package NE/SA630 Evaluation Board (see Figure 1C). Measurement system impedance is
son.

APPLICATIONS

The typical applications schematic and

printed circuit board layout of the NE/SA630

evaluation board is shown in Figure 1. The

layout of the board is simple, but a few

cautions need to be observed. The input and

son. output traces should be

The placement

of the AC bypass capacitor is extremely

criticalif a symmetric isolation between the two channels is desired. The trace from Pin 7 should be drawn back towards the package and then be routed downwards. The capacitor should be placed straight down as close to the device as practical. For better isolation between the two channels at higher frequencies, it is also advisable to run the two

output/input traces at an angle. This also minimizes any inductive coupling between the two traces. The power supply bypass capacitor should be placed close to the device. Figure 7 shows the frequency response of the NE/SA630. The loss matching between the two channels is excellent to 1.2GHz as shown in

October 10, 1991

837

Signetics RF Communications
Single pole double throw (SPOT) switch

Product specification
NE/SA630

VDD +SY
0.01�F
t-----1 f----0 OUT1
>------< f----0 OUTz
0.01�F
a. NE/SA Evaluatlon Board Schematic
a.� ~ 0 ��
'�'
� �
630C1 7/91
b. NE/SA630 D-Package Board Layout

October 10, 1991

:.J!':.
';i':
I I :J!ll.it
';'ir.
� �
1�1il0i'kil
c. NE/SA630 N-Package Board Layout Figure 1 838

Signetics RF Communications
Single pole double throw (SPDT) switch

Product specification
NE/SA630

Figure 1O. The isolation and matching of the two channels over frequency is shown in Figure 12 and Figure 14, respectively.
The NE630 is a very versatile part and can be used in many applications. Figure 2 shows a block diagram of a typical Digital RF transceiver front-end. In this application the NE630 replaces the duplexer which is typically very bulky and lossy. Due to the low power consumption of the device, it is ideally suited for handheld applications such as in CT2 cordless telephones. The NE630 can also be used to generate Amplitude Shift Keying (ASK) or On-Off Keying (OOK) and Frequency Shift Keying (FSK) signals for digital RF communications systems. Block diagrams for these applications are shown in Figure 3 and Figure 4, respectively.
For applications that require a higher isolation at 1GHz than obtained from a single NE630, several NE630s can be cascaded as shown in Figure 5. The cascaded configuration will have a higher loss but greater than 35dB of isolation at 1GHz and greater than 65dB @ SOOMHz can be obtained from this configuration. By modifying the enable control, an RF multiplexer/ de-multiplexer or antenna selector can be constructed. The simplicity of NE630 coupled with its ease of use and high performance lends itself to many innovative applications.
The NE/SA630 switch terminates the OFF
channel in son. The son resistor is internal
and is in series with the external AC bypass capacitor. Matching to impedances other
than son can be achieved by adding a
resistor in series with the AC bypass capacitor (e.g., 25Q additional to match to a 75Q environment).

TXIAX

MICRO CONTROLLER
~~~~~~~~--1

A TYPICAL TOMA/DIGITAL RF TRANSCEIVER SYSTEM FRONT-END
Figure 2
ASK OUTPUT

TTL DATA AMPLITUDE SllFT KEYING (ASK) GENERATOR
Fl ure 3

ENABLE
Figures

FREQUENCY SHIFT KEYING (FSK) GENERATOR
Figure4

October 10, 1991

839

Signetics RF Communications
Single pole double throw (SPOT} switch

Product specification
NE/SA630

200

. . . +85�C

-t.-:.=--- 180

. . -

160

�:L:_i.--...:::::::

..< 140 �/:v/,,,,

i---~ +25�C
-40"C

V,.....-:7 tz- 120

UrrrrJ:: :J

100

~

" ~

:""J-- 80

<I)

60

40

20

3V iiJ ~--4-+--------+---------1-llt---i

3.5

4

4.5

5.5

SUPPLY VOLTAGE (V)

Figure 6 Supply Current vs. V00 and Temperature

'

I

I

I I I III

I

I

I

''
11 I

-

-

-

-

"

-

_ ,_

-�-

I...!"!..'I I II

5-V-

-

- �- -

_. -

... -'- '- �-�-�
I I I III

-1

-t:::::i:=:::;::::;::::;=:~~�~�~;,,.....,....'.._~~2'_;.'_;_'~�~�~�~

I

I I

I

-�- �-�-� I I I I I I
- �- ...I I I I I I

I

I

I I I III

� � - - j - � I� - I - j" 't j ,- i� � � - - I-

t I I I I I I - , - ~ I �i

t

I

I I I III

I

I

I I I III

- - - - 1 - - r - r - " ' 1 � 1 -1.JJ. _ _ _ _ T--1--1- JTr- 1-

J_-_-_-_;-,_-_-;,-_+~-.+:--';. _.;.'_.;.'..;.~.j._:.3V:._~

1 : : ::

1

I I I III

; ~ 1�

I

I

I I I III

I

� � � � T � - 1� - I� r " T I.. I. - - - � 1� -

--- - ~ - _:__ :_ ~ ~ ~ ~:_ - -- _:_ - ~ - ~ _:_

I

I I I I 1I

I

1

I

I I I III

I

I

I II

- - - - T - - ,- - , - i ,. T "' �- - - - - ,- - -, - I 1 �

I

I

I I I III

I

I

I

-

-

-

-

"

-

- �-

- �'

...
I

.!
I

"
I

!.. �-
l I

-

-

-

- �-

-

_. -

.I 1

-

I

'I -

J

I

I I I I II

I

I

I II

- - - - i - - ,- -,- i ,. i,. ,. - - - - .- - -. - i -�-

-2-+~~-r�~~�~T�_,_�_:....,..�+:4:+-T-A_-_._2~~0-c~r'--.'-+'-+''t-t"H

10

100

1000

FREQUENCY (MHz)

Figure 8 Loss vs. Frequency and Voe for D-Package -Expanded Detail-

1IJ
Figure 7

100 FREQUENCY (MHz)

1000

Loss vs. Frequency and V00 for D-Paokage

10

100

1000 2000

FREQUENCY (MHz)

Figure 9 Loss Matching vs. Frequency for N-Package (DIP)

October 10, 1991

840

Signetics RF Communications
Single pole double throw (SPOT) switch

Product specification
NE/SA630

0 -1 -2 -3 iii
Jr'li!. -4
-5 -8 -7 -8

~

ll
~--

t:\� CH1

Voo-sv
TA�+25"C

'

100

1000 2000

FREQUENCY (MHz)
Figure 10 Loss Matching vs. Frequency; CH1 vs. CH2 for D-Pakage

-40"C

-1

~~ +25"C

'

+S5"Ct

-5

i

-8

j

-7
Voo-SV

-8

100

1000 2000

FREQUENCY (MHz)

Figure 11 Loss vs. Frequency and Temperature for D�Package

-10

-20

-30 iii
~ -40
~ -50

-80

-70

-80 10

100

1000 2000

FREQUENCY (MHZ)

Figure 12 Isolation vs. Frequency and VDD for D-Package

-10

-20

-30
~-40
~ -50

-80

-70
-80
w

TA�+25"C
Voo-sv
100 FREQUENCY (MHz)

1000 2000

Figure 13 Isolation Matching vs. Frequency for N-Package (DIP)

October 10, 1991

841

Signetics RF Communications
Single pole double throw (SPOT) switch

Product specification
NE/SA630

0

-10

-l!O

-30
~-40
c8'
-so
-�>

-70

-�>
1D

100 FREQUENCY (MHz)

1000 2000

Figure 14 Isolation Matching vs. Frequency; CH1 vs. CH2 for D�Package

0
-s

.. -10
~-15 t1i
4V -l!O
5V
-25

-30 10

100

1000 2000

FREQUENCY (MHz)

Figure 15 Input Match On-Channel vs. Frequency and Vuo

z

j'j

-10

-10

lIi -15

L _/

~Ii -15

CH1:3V CH1:5V
-

1
_,/

CH2:5V

-l!O

-25 Yoo� 5V
TA�+25"C

10

100

1000 2000

FREQUENCY (MHZ)

Figure 16 Output Match On�Channel va. Frequency

-25 TA�+25"C

-00 10

100 FREQUENCY (MHz)

1000 2000

Figure 17 OFF-Channel Match vs. Frequency and Voe

October 10, 1991

642

Signetics RF Communications
Single pole double throw (SPOT) switch

Product specification
NE/SA630

20

18

-5

-10

~

18 14

fil
- - - - - ,j_ ~-15

+85�C
--
+25�C

----~/

12
"E
"':2. 10

//

a.'

-- -- -- - -20 -40�C

i--

5V
._,,,
4V
3V

~ ~
~ ~
7-v] L

-25 voo-5V

-30 10

100 FREQUENCY (MHz)

1000 2000

Figure 18 OFF Channel Match vs. Frequency and Temperature

TA� +25�C

10

"'" 100

1000 2000

FREQUENCY (MHz)

Figure 19 P.1 dB vs. Frequency and Yoo

~ 40-t-~~-t-~~-t-~~-t-~~-t-~~-t-~~-I
:2.
~~ 30 -l-~~-i-==IP~3==t:::-:-:+:-=-::1--~~l--~~l--~--l
~
~ 20-;-~~.,...~~.,...~~-T-~~-T-~~-T-~~-1

TA �+25�C

0-h-i,-,--r-h-,-,.....--+-~Ml-.--.-.-~l+-r....-,...,.+~~

I

I

3.5

4

4.5

5.5

SUPPLY VOLTAGE (V)

Figure 20 Intercept Points vs. Yoo

4.5
3.5
~ 3
aaw: 2.5
u:
w ~ 2
~
1.5

TA� +25�C ZcJ�5Dn
3V
-- - - -4V-

5V 0.5

I

_t_

--

,L,,,1
d_

10

100

1000 2000

FREQUENCY (MHz)
Figure 21 Noise Figure vs. Frequency and Yoo for 0- Package

October 10, 1991

843

Signetics RF Communications
Single pole double throw (SPOT) switch

Product specification
NE/SA630

ENCH1 (Pin4) OUT1(Pin8)
Figure 22 Switching Speed; f1N =100MHz at �6dBm, V00 =SV

October 10, 1991

844

Signetics
RF Communications

Section 9 Package outlines

INDEX

8-Pin (300 mils wide) Plastic Dual In-Line (N) Package ..................... 847

8-PIN (157 mils wide) Plastic SO (Small Outline) Dual In-Line (D) Package ...... 848

8-PIN Plastic Dual in-line (NIP) Package ................................. 849

9-PIN Plastic Single In-Line (U) Package . .

. . . . . . . . . . . . . . . . . . . . . . . . . 850

14-Pln (300 mils wide) Plastic Dual In-Line (N) Package .................... 851

14-PIN (157 mils wide) Plastic SO (Small Outline) Dual In-Line (D) Package ..... 852

16-Pin (300 mils wide) Plastic Dual In-Line (N) Package .................... 853

16-Pin (157 mils wide) Plastic SO (Small Outline) Dual In-Line (D) Package ..... 854

16-PIN Plastic SO Dual In-Line (DIT) Package ............................ 855

16-PIN Plastic Dual In-Line (NIP) Package ............................... 856

16-PIN Plastic SOL Dual In-Line (DIT) Package ........................... 857

18-PIN Plastic Dual In-Line (NIP) Package ............................... 858

20-Pin (300 mils wide) Plastic Dual In-Line (N) Package .................... 859

20-PIN (300 mils wide) Plastic SOL (Small Outline Large) Dual In-Line (D) Package ....................................... 860

20-PIN Plastic Shrink Small Outline Package (SSOP) (DK) Package ........... 861

20-PIN Plastic SO Dual In-Line (DIT) Package ............................ 862

24-Pin (600 mils wide) Plastic Dual In-Line Package ....................... 863

24-Pin ~~ ~'.l~i~~~~t~~~~~i~~.<~~~11 ~u.!Une .La~~~) .................... 864

28-pin (600 mils wide) Plastic Dual In-Line (N) Package ..................... 865

28-PINd~~?1~iL~:Si?gl ~~;~~g~o.~ (Sm~~l .O~tline. Lar.g~! .................... 866

28-PIN Plastic Dual In-Line (NIP) Package ............................... 867

28-PIN Plastic SO Dual In-Line (DIT) Package ............................ 868

December 1991

f ~
I;;;
~ ~
~

, �

@I � , 1'9-1 D 0.004 (0.10)1

I

I

r

0.255(6.48)

0.245 (6.22)

�;

v

v

. __i
ljjll

1---1- 1 I

I

0.100 (2.54) BSC

0.376 (0.955)---...l 0.365 (0.927)

0.042(1.07) 0.035(0.89)

----.

JL

0.138(3.51) 0.120 (3.05)

I O.ll22(0.56)-j$11 e lo@lo.010(0.25>�1
0.017(0.43)

qi

z"ti w
8

3

NOTES

ii

:e 1. Controlling dimension: Inches. Metric are shown in parentheses.

! 2. Package dimensions confonn to JEDEC Specification MS-001-AB

for standard Dual In-Line (DIP) package 0.300 inch row spacing (plastic) B leads (Issue B, 7185).

"ti
!i:

3. Dimension and tolerancing perANSI Y14, 5M - 1982.

th

::!

4. "T", "D", and "E" are reference datums on the molded body and

0

do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm) on any side.

c c

5. These dimensions measured with the leads constrained to be perpendicular to plane T.
6. Pin numbers start with Pin #1 and continue counterclockwise to Pin #8 when viewed from the top.

r:I>
rmzz-

~

~

~

:I>

0.125(3.18)

mC)

0.115(2.92) 1

IY

=t J '!i o.035(0.89)

020

'~

\
1~1
~~ 0.300~.62) --f I
(NOTE5)

0.015 (0.38) 0.010 (0.25)

0.395 (10.03) 0.300 ( 7.62)

a(sJ)�

.. "O
nD>

"CD
5�

~
ca

Jl "Tl 0 0

CD
c 0
~ s�

3 3 c
."gc;.�
"

eCnD

~

IIf

!
~

~ "~'

i6

J �

�I l-tlo@lo.10(0.004)1

6.20 (0.244)
5.95 (0.234)�
l"$"1e �lo.25(0.010)@1

~

_J_

I L - - i ~�~~~~=:3 1.66(0.066)�

[iJ

~ 1.45(0.057)

lqo.1o(O.DD4ll

--J ~:: ~:~:::-lr:-$-""r:lr,...1.-e...,1-o""""'@'""'I0-.2-5-10-.01_0)_@~1

CjD
-z"II
...... U.....I.

3 ~

NOTES

!a.
.!.

1. Package dimensions conform to JEDEC Specification MS-012-AA for standard Small Outline (SO) package, 8 leads, 3. 75mm (0.150")

r"II

body width (Issue A, June 1985).

]>

2. Controlling dimensions are mm. Inch dimensions in parentheses.

~
0

3. Dimensioning and tolerancing per ANSI Y14.5M-1982.

~

4. "T", �o�, and 'E" are reference datums on the molded body and
do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25mm (0.010") on any side.

esn::
]>

5. Pin numbers start with Pin #1 and continue counterclockwise to Pin #8 when viewed from top.

r r
c 0

6. Signetics ordering code for a product packages in a plastic Small OuUine (SO) package is the suffix D after the product number.

-czI

.!!!

L
T
0.25 (0.010) 0.19 (0.007)

0.25 (0.010) 0.10 (0.004)

c 0
]>
r
rzmz-
:�

0.82 (0.032) �

~
0

0.56 (0.022) .

~

C)
m

ceen�

"CJ
I�

"iCiD�

()
c&c

,"J,'J
() 0

CD
c 0 ::::;:!�:.
CD

3 3 c
"aec;r� ""'

"'

!!l

Signetics RF Communications
Package outlines
8�PIN PLASTIC DUAL IN�LINE (NIP) PACKAGE

-a.2smax-

I 0,53 I
~x O,Jj,_ --H~lo.254@1 111
- i--i~i--i 1,15 max

I

I

I

I

..... J.L 0,32

11

11 max

II

' ~

~

' i-17,s21-i '

9,5 --~...

8,3

7273585.S

Dimensions in mm
SOT97

top view

$ Positional accuracy.
@ Maximum Material Condition.
(1) Centre-lines of all leads are within �0,127 mm of the nominal position shown; in the worst case, the spacing between any two leads may deviate from nominal by �0,254 mm.
(2) Lead spacing tolerances apply from seating plane to the line indicated.
(3) Only for devices with asymmetrical end-leads.
7Z73585.5

December 1991

849

Signetics RF Communications
Package outlines

9-PIN PLASTIC SINGLE IN-LINE (U) PACKAGE
21 ----------<..,

- - - - - - - - 15 - - - - - - - - - - 1..1

,I,.

I

I

r

1�

8,7
t max

4,3
i 18,5 max

.
~
-t-
3,9 3,4
~

-. I

2

3

4

5

6

7

8 9

-1,20 '

3
�min
+, -+-t----,0 76 121
0,67 I
0' 50-I .~~(1)

Bx

1

.
-

.

..
I

-- ,
' _ 1 1 2~ 0 1, _1

,I_.1_[_b_I.�__]_,I_,I_I,_

-Ll--o,35
I

max

_____6,l35
0,4-11.-
7Z76161.1

Dimensions in mm
SOT110B

top view

)I
22max -----------+

$ Positional accuracy.
@ Maximum Material Condition.
(1) Centre-lines of all leads are within �0,127 mm of the nominal position shown; in the worst case, the spacing between any two leads may deviate from nominal by �0,254 mm.
(2) Lead spacing tolerances apply from seating plane to the line indicated.
7Z76161.1

December 1991

850

0
i �
3
CT
~

~

[ll
I

~

~
I 0.255 (6.48) 0.245 (6.22)
_J_ "'=;==;=;==;==;==;=;==;=;===;=;==r=;==;==i
-0- f--+o>------

SEATING PLANE

0.180 (4.06)

JL- 0.022(0.58)

L '�T"

-

0.138(3.51)

I ID �I 0.017 (0.43) --1$1 T E

O.Q10 (0.25)@10.120 (3.05)

......

i"z:""i
w
0 0

NOTES

2.
"iii

1. Controlling dimension: Inches. Metric are shown in parentheses.

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(plastic) 14 leads (Issue 8, 7185).

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3. Dimension and tolerancing per ANSI Y14, 5M- 1982.

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4. "T'', "D", and "E" are reference datums on the molded body and do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm) on any side.

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5. These dimensions measured with the leads constrained to be perpendicular to plane T.
6. Pin numbers start with Pin #1 and continue counterclockwise to Pin #14 when viewed from the top.

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1. Package dimensions conform to JEDEC Specification MS-012-AB for standard Small Outline (SO) package, 14 leads, 3.75mm (0.1501

>r"Of..l..).

body width (Issue A, June 1985).

0

2. Controlling dimensions are mm. Inch dimensions in parentheses.

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0

3. Dimensioning and tolerancing per ANSI Y14.5M-1982.

Ci>

4. "T", �o�, and "E" are reference datums on the molded body and
do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25mm (0.010") on any side.

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5. Pin numbers start with Pin #1 and continue counterclockwise to Pin #14 when viewed from the top.

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6. Signetics ordering code for a product packages in a plastic Small

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'iii

NOTES 1. Controlling dimension: Inches. Metric are shown in parentheses.

a::e:

2. Package dimensions conform to JEDEC Specification MS-001-AA .!!!.

for standard Dual In-Line (DIP) package 0.300 inch row spacing (plastic) 16 leads (Issue B, 7185).

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3. Dimension and tolerancing per ANSI Y14, SM - 1982.

-I

0

4. "T", "D", and "E" are reference datums on the molded body and do not include mold flash or protrusions. Mold flash or protrusions

cc :

shall not exceed 0.010 inch (0.25mm) on any side.

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5. These dimensions measured with the leads constrained to be perpendicular to plane T.
6. Pin numbers start with Pin #1 and continue counterclockwise to Pin #16 when viewed from the top.

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" >
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Ill

= t0.035(0.89) 'll

1~1

~~

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(NOTES)

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0.395 (10.03)] 0.300 ( 7.62)

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1. Package dimensions conform to JEDEC Specification MS-012-AC for standard Small Outline (SO) package, 14 leads, 3. 75mm (0.150") body width (Issue A, June 1985).

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4. "T", �o�, and "E" are reference datums on the molded body and
do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25mm (0.010') on any side.

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5. Pin numbers start with Pin #1 and continue counterclockwise to Pin #16 when viewed from top.

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6. Signetics ordering code for a product packages in a plaslic Small

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Signetics RF Communications
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16-PIN PLASTIC SO DUAL IN�LINE (DfT) PACKAGE ,_ _ _ _ _ _ _ _ 10,0 _ _ _ _ _ _ _ _, 9,8

I

~:~----+I

_1.2s_4.o_

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0,7mox
sot 109A

top view
Dimensions in mm
$ Positional accuracy.
@ Maximum Material Condition.
7Z73978.5

December 1991

855

Signetics RF Communications
Package outlines

16-PIN PLASTIC DUAL IN-LINE (N/P) PACKAGE
+---~-_J------22mox---------~

-B,25max-

SOT38

4,7
. max 0,51 min 0 75121 '
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(1) Centre-lines of all leads are within �0.127 mm of the nominal position shown; In the worst case, the spacing between any two leads may deviate from nominal by �0.254 mm.
(2) Lead spacing tolerances apply from seating plane to the line indicated.
(3) Dimensions in mm.
7Z55041.8

December 1991

856

Signetics RF Communications
Package outlines
16-PIN PLASTIC SOL DUAL IN-LINE (DIT) PACKAGE

- - - - - 89..2755 -------<~I 1 - 4 - - - - 77..64 - - - - . -

_ _ _ _ _ _ 10.65_ _ _ _O_ .Jm_ inl�

10.0

7Z83896.3

top view
2.0 max
10 11 12 13 14 15 16
(1) Dimensions in mm.
SOT 162A

7Z83896.3

December 1991

857

Signetics RF Communications
Package outlines

18�PIN PLASTIC DUAL IN-LINE (N/P) PACKAGE

.

22 max

f j

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(1) Centre-lines of all leads are within �0.127 mm of the nominal position shown; in the worst case, the spacing between any two leads may deviate from nominal by �0.254 mm.
(2) Lead spacing tolerances apply from seating plane to the line indicated.
(3) Dimensions in mm.
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December 1991

858

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NOTES

iii

1. Controlling dimension: Inches. Metric are shown in parentheses.
2. Package dimensions conform to JEDEC Specification MS-001-AE for standard Dual In-Line {DIP) package 0.300 inch row spacing {plastic) 20 leads {Issue B, 7/85).

,,a:e:
.!!!.

r

3. Dimension and tolerancing per ANSI Y14, 5M - 1982.

e>n

4. �r, "D", and "E" are reference datums on the molded body and
do not include mold flash or protrusions. Mold flash or protrusions
shall not exceed 0.010 inch {0.25mm) on any side.

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5. These dimensions measured with the leads constrained to be perpendicular to plane T.
6. Pin numbers start with Pin #1 and continue counterclockwise to Pin #20 when viewed from the top.

r >
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0.135 (3.43)

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body width (Issue A, June 1985).

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GIBI�J0.25To01o)�] 2. Controlling dimensions are mm. Inch dimensions in parentheses.

-I
0

3. Dimensioning and tolerancing per ANSI Y14.5M-1982.
4. "T", "D", and "E" are reference datums on the molded body and do not indude mold flash or protrusions. Mold flash or protrusions
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+

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0.25 (0.010)�1

0.35 (0.014)

Pin #20 when viewed from top.

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6. Signetics ordering code for a product packaged in a plastic Small Outline (SO) package is the suffix D after the product number.

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Signetics RF Communications
Package outlines

20-PIN PLASTIC SHRINK SMALL OUTLINE PACKAGE (SSOP) (DK PACKAGE)
55.7 .2-f1
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6.2

20

11

4.5

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1CY

10

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C1' T0100

DETAIL

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SSOP Package Outline: All dimensions in "mm"

December 1991

861

Signetics RF Communications
Package outlines

20-PIN PLASTIC SO DUAL IN-LINE (DfT) PACKAGE

~

~- - - - - - 13.0 _ _ _ _ _ _,

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(1) Dimensions in mm.
SOT 163A

7Z83897.3

December 1991

862

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1.260 (32.00) ,_._ _ _ _ 1.240(31.50)

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0.022 (0.56)

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0.010 (0.25)

0.138(3.51)
0.120 (3.05)
I

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3

NOTES: 1. Controlling dimension: Inches. Metric are shown in parentheses.

I ~ ~

2. Package dimensions conform to JEDEC Specification MS-011-M .!.

for standard Dual In-Line (DIP) package 0.600 inch row spacing 'ti

(plastic) 24 leads (Issue B, 7/85). 3. Dimension and tolerancing per ANSI Y14, 5M- 1982.

~
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4. "l", "D", and "E" are reference datums on the molded body and do not include mold flash or protrusions. Mold flash or protr:usions shall not exceed O.Q1 Oinch (0.25mm) on any side.
5. These dimensions measured with the leads constrained to be perpendicular to plane T.
6. Pin numbers start with Pin #1 and continue counterclockwise to Pin #24 when viewed from the top.

0 cc : > r
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0

0.620 (15.75)~ 0.600 (15.24)
(NOTES)

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0.015 (0.38) 0.010(0.25)

0 695 (17.65) 0:600(15.24)

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1. Package dimensions conform to JEDEC Specification

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MS-013-AD for standard Small Outline (SO) package, 24 leads, 7.50mm (0.300") body width (Issue A. June 1985).

>-a

2. Controlling dimensions are mm. Inch dimensions in parentheses.

(/)
-t
0

3. Dimensioning and tolerancing per ANSI Y14.5M-1982.
4. "T", "D", and "E" are reference datums on the molded body and do not incluce mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25mm (0.010") on any side.

(/)
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~

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15.20 ~.598)

5. Pin numbers start with Pin #1 and continue counterclockwise rr--

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c 0

6. Signetics ordering code for a product packaged in a plastic Small Oudine (SO) package is the suffix D after the product number.

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1- ~.020) 0.75 ~.030) x45� 0.50

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NOTES: 1. Controlling dimension: Inches. Metric are shown in parentheses.

'iii
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2. Package dimensions conform to JEDEC Specification MS-011-AB .!.

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(plastic) 28 leads (Issue B, 7/84).

~

3. Dimension andtolerancing per ANSI Y14, 5M-1982.

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0 cc :
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5. These dimensions measured with the leads constrained to be perpendicular to plane T.
6. Pin numbers start with Pin #1 and continue counterclockwise to Pin #28 when viewed from the top.

r
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J 0.01S(0.38)

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0.600 (1 S.24)

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NOTES 1. Package dimensions conform to JEDEC Spe<:ification

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MS-013-AE for standard Small Outline (SO) package,

.!.

28 leads, 7.50mm (0.300") body width (Issue A, June 1985). r'ti

~l

2. Controlling dimensions are mm. Inch dimensions in

el>n

1'171 E @lo.25 (0.010)@1 parentheses.

~

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3. Dimensioning and tolerancing per ANSI Y14.SM-1982.

0 en

4. "T", "D", and "E" are reference datums on the molded body and do not incluce mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.25mm (O.Q10") on any side.

e0srn::

5. Pin numbers start with Pin #1 and continue counterclockwise rl>

to Pin #28 when viewed from top.

r

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r-;;-i
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� 1 . 2 7 (0.050) BSC

18.10(0.713) ~~~~~~~~~~"'I 17.70 (0.697)

6. Signetics ordering code for a product packaged in a plastic
Small Outline (SO) package is the suffix D after the product number.

c 0
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0.75 (0.030)
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2.35 (0.093)

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Signetics RF Communications
Package outlines
28-PIN PLASTIC DUAL IN-LINE (N/P) PACKAGE

top view
'"

, - - - - - 15,8 max - - - - - 1
- - - - 1 4 , 1 max---~~'

side view

I
11
r�i: 0 32 111
!______ [1illJ - - - - -
17,15 _ _ _ _ _ _, 15,90

Dimensions in mm
SOT 117

$ Positional accuracy.
@ Maximum Material Condition.
(1) Centre-lines of all leads are within �0,127 mm of the nominal position shown; in the worst case, the spacing between any two leads may deviate from nominal by �0,254 mm.
(2) Lead spacing tolerances apply from seating plane to the line indicated.
(3) Index may be horizontal as shown, or vertical.
7273669.2

December 1991

667

Signetics RF Communications
Package outlines

28�PIN PLASTIC SO DUAL IN-LINE (Off) PACKAGE

~

~-17 181 7-

a�

_ 2 o_

/..... 50

1 max

00.�+455

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f~~l1g-;~l1'l~'

2.65 2.35
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,------ g~------~I

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December 1991

868

Signetics
RF Communications

Section 10 Sales offices

December 1991

Signetics

Sales Offices, Representatives & Distributors

RF Communications
SIGNETICS HEADQUARTERS 811 East Arques Avenue P.O. Box 3409 Sunnyvale, CA 94088-3409
ALABAMA Huntsvllle
Phone: (205) 464-0111
CALIFORNIA Calabasas
Phone: (818) 880-6304
Irvine Phone: !J14) 833-8980 ( 14) 752-2780
San Diego Phone: (619) 560-0242
Sunnyvale Phone: (408) 991-3737
COLORADO En~ewood
hone: (303) 792-9011
GEORGIA Atlanta
Phone: (404) 594-1392
ILLINOIS Itasca
Phone: (708) 250-0050
IN DIANA Kokomo
Phone: (317) 459-5355
MASSACHUSETTS Westford
Phone: (508) 692-6211
MICHIGAN Farmington Hills
Phone: (313) 553-6070
NEW JERSEY Toms River
Phone: (908) 505-1200
NEW YORK Wa~~ingers Falls
one: (914) 297-4074
OHIO Columbus
Phone: (614) 888-7143
OREGON Beaverton
Phone: (503) 627-0110
PENNSYLVANIA Plymouth Meeting
Phone: (215) 825-4404
TENNESSEE Greeneville
Phone: (615) 639-0251

TEXAS Austin
Phone: (512) 339-9945
Richardson Phone: (214) 644-1610
CANADA SIGNETICS CANADA, LTD. Etoblcoke, Ontario
Phone: (416) 626-6676
Nepean, Ontario Phone: (613) 225-5467
REPRESENTATIVES
ALABAMA Huntsvllle
Elcom, Inc. Phone: (205) 830-4001
ARIZONA Scottsdale
Thom Luke Sales, Inc. Phone: (602) 941-1901
CALIFORNIA Orangevale
Webster Associates Phone: (916) 989-0843
COLORADO En~lewood
horn Luke Sales, Inc. Phone: (303) 649-9717
CONNECTICUT Walli'lflford
JE CO Phone: (203) 265-1318
FLORIDA Oviedo
Conley and Assoc., Inc. Phone: (407) 365-3283
GEORGIA Norcross
Elcom, Inc. Phone: (404) 447-8200
ILLINOIS Hoffman Estates
Micro-Tex, Inc. Phone: (708) 765-3000
IN DIANA lndianar\:lis
Moh ield Marketing, Inc. Phone: (317) 546-6969
IOWA Cedar Rapids
J.R. Sales Phone: (319) 393-2232
MARYLAND Columbia
Third Wave Solutions, Inc. Phone: (301) 290-5990

MASSACHUSETTS
Chelmsford JEBCO Phone: (508) 256-5800

TEXAS
Austin Synergistic Sales, Inc. Phone: (512) 346-2122

MICHIGAN Brighton
AP Associates Phone: (313) 229-6550
MINNESOTA Eden Prairie
High Technol~ Sales Phone: (612) 4-7274
MISSOURI

Houston S~nergistic Sales, Inc. P one: (713) 937-1990
Richardson S~nergistic Sales, Inc. P one: (214) 644-3500
UTAH Salt Lake City
Electrodyne Phone: (801) 264-8050

Bridgeton
Centech, Inc. Phone: (314) 291-4230

WASHINGTON Bellevue
Western Technical Sales

Raytown

Phone: (206) 641-3900

Centech, Inc. Phone: (816) 358-8100
NEW YORK Ithaca
Bob Dean, Inc. Phone: (607) 257-1111
Rockville Centre S-J Associates Phone: (516) 536-4242
Wa~ln8ers Falls b ean, Inc.
Phone: (914) 297-6406
NORTH CAROLINA Matthews
ADI, Inc. Phone: (704) 847-4323

Spokane Western Technical Sales Phone: (509) 922-7600
WISCONSIN Waukesha
Micro-Tex, Inc. Phone: (414) 542-5352
CANADA Ca~ary, Alberta
ech-Trek, Ltd. Phone: (403) 241-1719
Mississauga, Ontario Tech-Trek, Ltd. Phone: (416) 238-0366
Ne~ean, Ontario ech-Trek, Ltd. Phone: (613) 225-5161

Smith field ADI, Inc. Phone: (919) 934-8136
OHIO

Richmond, B.C. Tech-Trek, Ltd. Phone: (604) 276-8735
Ville St. Laurent, Quebec Tech-Trek, Ltd.

Aurora lnterActive Technical Sales, Inc. Phone: (216) 562-2050
Damon nterActive Technical Sales, Inc. Phone: (513) 436-2230

Phone: (514) 337-7540
PUERTO RICO Santurce
Mectron Group Phone: (809) 723-6165
DISTRIBUTORS

Dublin lnterActive Technical Sales, Inc. Phone: (614) 792-5900
OREGON Beaverton
Western Technical Sales Phone: (503) 644-8860
PENNSYLVANIA Hatboro
Delta Technical Sales, Inc. Phone: (215) 957-0600

Contact one of our local distributors: Almac/Arrow Electronics Anthem Electronics Arrow/Schweber Electronics Falcon Electronics, Inc. Gerber Electronics Hamilton/Avnet Electronics Marshall Industries Wyle/EMG Zentronics, Ltd.

10/30/91

Philips - a worldwide company

Argentina: PHILIPS ARGENTINA S.A. Div. Philips Components, Vedia 3892, 1430 BUENOS AIRES, Tel. (01) 5414261 ,
Australia: PHILIPS COMPONENTS PTY J,I<'. 34 Waterloo Road,
NORTH RYDE, NSW 2113, TEL (02) <!05-4455. Fax (02) 805 4466
Austria: OSTERREICHISCHE PHJi,'fS INDUSTRIE G.m.b.H., UB Bauelemente, Triesler ~~. 1101 WEN. Tel. (0222) 60101-820
Belgium: N.V. PHILIPS Pf!W: SYSTEMS- Components Div.. 80 Rue Des Deux Gare�, B�1070 BRUXEUES, Tel. (02) 5256111
Brazil: PHILIPS CQMpONENTS (Active Devices & LCD)
Rua Do ~ Zlo, SAO PAULO-SP, CEP 4552, P.O. Box 7383,
CEP 0105�, Tel. (011) 829-1166. Fax (011) 829-1849. PHILIPSCOMPONENTS (Passive Devices &Materials) Av. Francisco Monteiro 702, RIBEIRAO PIRES-SP, CEP 09400, Tel. (011 )459-8211. Fax (011)459-8282
d.'..ac1a: PHILIPS ELECTRONICS LTD.. Philips Components, 601 Milner Ave., SCARBOROUGH, Ontario, Ml B1M8 Tel. (416) 292-5161. (IC Products) SIGNETICS CANADA LTD., 1 Eva Road, Suite 411, ETOBICOKE, Ontario, M9C4Z5, Tel. (416) 626�6676
Chile: PHILIPS CHILENA SA. Ay. Santa Maria, Casilla 0760. SANTIAGO, Tel.(02)0773816
Colombia: IPRELENSO LTDA., Carrera21No.56-17, BOGOTA, D.E .� P.O. Box 77621, Tel. (01) 2497624
Denmark: PHILIPS COMPONENTS A/S, Prags Boulevard 80, PB1919, DK-2300 COPENHAGEN S, Tel. 32�883333
Finland: PHILIPS COMPONENTS, Sinikalliontie 3, SF-02630 ESPOO Tel. 358-0-50261
France: PHILIPS COMPOSANTS, 117 Ouai du President Roosevelt, 92134 ISSHES-MOULINEAUX Cedex, Tel. (01) 40938000. Fax. 0140938692
Germany: PHILIPS COMPONENTS US der Philips G.m.b.H., Burc!lardstrasse 19, D-2 HAMBURG 1, Tel. (040) 3296-0, Fax. 040 3296912.
Greece: PHILIPS HELLENIQUE SA, Components Division, No. 15, 25th March Street, GR 17778TAVROS, Tel. (01)4894339/4894911
Hong Kong: PHILIPS HONG KONG LTD., Components Div., 15/F Philips Ind. Bldg., 24 Kung Yip St, KWAICHUNG, Tel. (0)4245121
India: PEICO ELECTRONICS & Et�CTRICALS LTD., Components Dept., Shivsagar Estate 'A' Block, P.O. Box 6598, 254-0 Dr. Annie Besant Rd .. BCMBAY40018 Tel. (022) 4921500-4921515. Fax. 02249419063
Indonesia: P.T. PHILIPSRALIN ELECTRONICS, Components Div., Setiabudi II Building, 6th Fl., Jalan H.R. Rasuna Said (P.O. Box 223'1\BY) Kuningan, JAKARTA, 12910, Tel. (021) 517995
Ireland: PHILIPS ELECTRONICS (IRELAND) LTD., Components Division, Newstead, Clonskeagh, DUBLIN 14, Tel. (01) 693355
Italy: PHILIPS S.p.A., Philips Components, Piazza.IV Novembre 3, 1-20124 MILANO, Tel. (02) 6752.1, Fax. 0267522642
Japan: PHILIPS JAPAN LTD., Components Di~sioo, Philips Bldg. 13�37, Kohnan 2-c!lome, Minato-ku, TOKYO 108, Tel. (03) 813-3740-5030. Fax. 03 81337400570
Korea (Republic of): PHILIPS INDUSTRIES (KOREA) LTD., Components Divi� sion, Philips House, 260.199 haewon-dong, Yongsan-ku, SEOUL, Tel. (02) 794-5011
Malaysia: PHILIPS MALAYSIA SON BHD, Components Div., . 3 Jalan SS15f2A SUBANG, 47500 PETALING JAYA, Tel. (03) 7345511
Mexico: PHILIPS COMPONENTS, Paseo Triunlo de la Republica, No 215 I
local 5, Cd Juarez CHIHUAHUA 32340 MEXICO, Tel. (16) 18-67-01'�2 Netheriands: PHILIPS NEDERLAND B.V., Markt9roep Philips Components,
Postbus 90050, 5600 PB EINDHOVEN, Tel. (040) 783749
New Zealand: PHILIPS NEW ZEALAND LTD., Components Division, 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. (09) 894-160, Fax. (09) 897-811
9398181 40011

Holway: NORSK MJ PHILIPS, Philips Components, Box 1, Manglerud 0612, OSLO, Tel. (02) 741010
Pakistan: PHILIPS ELECTRICAL CO. OF PAKISTAN LTD., Philips Markaz, M.A. Jinnah Rd., KARACHl-3, Tel. (021) 725772
Peru: CADESA, Carretera Central 6.500, LIMA 3, Apertado 5612, Tel.51 -14-360059
Phlllpplnes: .PHILIPS SEMICONDUCTORS PHILIPPINES Inc., 106 Valero SI. Salcedo lfll"9e, P.O. Box 911, MAKATI, Metro MANILA, Tel. (63-2)810-0161 Fax. 632 817 3474
Portugal: PHILIPS PORTUGLESA S.A.R.L, Av. Eng. Duarte Pacheco 6, 1009 LISBQA Codex, Tel. (019) 68 31 21
Singapore: PHILIPS SINGAPORE, PTE LTD., Components Div., Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. 3502000
South Africa: SA PHl.IPS PTY LTD., Components Division, 195-215 Main Road, JOHANNESBURG 2000, P.O. Box 7430, Tel. (011)470-5434. Fax. (011) 470 5494
Spain: PHILIPS COMPONENTS, Balmes 22, 08007 BARCELONA, Tel. (03) 301 6312. Fax. 03 3014243
Sweden: PHILIPS COMPONENTS, A.B., Tegeluddsvagen 1, S-11584 STOCKHOLM, Tel. (0)8�7821000
Swltzeriand: PHILIPS A.G., Components Dept, Allmendstrasse 140-142, CH-8027 ZORICH, Tel. (01) 4882211
Taiwan: PHILIPS TAIWAN LTD.. 581 Min Sheng East Road, P.O. Box 22978, TAIPEI 10446, Taiwan, Tel. 886-2�509�7666. Fax. 886 2500 5899
Thailand: PHILIPS ELECTRICAL CO. OF THAILAND LTD., 283 Silon Road, P.O. Box 961, BANGKOK, Tel. (02) 233-6330-g
Turi<ey: TORK PHILIPS TICARET A.S.. Philips Components, Talatpasa Cad. No. 5, 80640 LEVENT/ISTANBUL, Tel. (01) 179 2770
United Kingdom: PHILIPS COMPONENTS LTD., Mullard House, Torrington Place, LONDON WCI E 7HD, Tel. (071) 580 6633, Fax. (071) 436 2196
United st.a.s: (Color Picture Tubes� Monochrome & Colour Dis~ay Tubes) PHILIPS't>ISPLAY COMPONENTS COMPANY, 1600 Huron Parkway, P.O. Box 963, ANN ARBOR, Michigan 48106, Tel. (313) 996-9400 (IC Products) SIGNETICS COMPANY, 811 East Arques Avenue, SUNNYVALE. CA 94088-3409, Tel. (800) 227� 1817, Ext. 900 (Passive Components, Discrete Semiconductors, Materials and Professional Components & LCD) PHILIPS SEMICONDUCTORS, Disaete Products Division, 2001 West Blue Heron Blvd., P.O. Bmi: 10330, RIVIERA BEACH, Florida 33404, Tel. (407) 881-3200
Uruguay: PHILIPS COMPONENTS, Coronel Mora 433, MONTEVIDEO, Tel. (02) 704044
VeneZ1Jela: MAGNETICA s.A.� Calle 6, Ed. L.S Tres Jotas, CARACAS 1074A,
Apf>. Post. 78117, Tel. (02) 241 7509 Zimbabwe: PHILIPS ELECTRICAL (PVT) LTD., 62 Mutare Road, HARARE,
P.O. Box 994, Tel. 47211
For ah other countries ~Y to: Philips Comp)nents, Marketing Communications, PO. Box 218, 5600 MD EINDHOVEN, The Netherlands, Telex 35000 phtcnl, Fax +-'3140-724825 ADS92 �Philips Export B.V. 1991
Al! rights are reseived. Reproduction ln whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quota lion or contrac~ is believed to be accurate and reliable and may be changed without notice. No liability will be accepted 11,' the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or industrial or intellectual property rights.
1112~1
1320L/29M/CR311291 882pp 98�21J00.290�03

Philips Semiconductors