S32SDK for S32V23x BETA 0.9.0 ReleaseNotes

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Cezar Dobromir

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S32SDK-S32V23x-RN

S32 SDK for S32V23x Release Notes
Version 0.9.0 BETA
© 2019 NXP Semiconductors N.V.

Contents
1. DESCRIPTION............................................................................................................................3 2. NEW IN THIS RELEASE ................................................................................................................4
2.1 Drivers............................................................................................................................4 2.2 Examples........................................................................................................................4 2.3 PAL................................................................................................................................4 2.4 Middleware .....................................................................................................................4 2.5 RTOS .............................................................................................................................4 2.6 Fixed from EAR 0.8.1 ......................................................................................................4 3. SOFTWARE CONTENTS ...............................................................................................................7 3.1 Drivers............................................................................................................................7 3.2 PAL................................................................................................................................7 3.3 RTOS .............................................................................................................................8 3.4 Middleware .....................................................................................................................8 4. DOCUMENTATION ......................................................................................................................9 5. EXAMPLES ............................................................................................................................. 10 6. SUPPORTED HARDWARE AND COMPATIBLE SOFTWARE ................................................................... 11 6.1 CPUs.................................................................................................................................. 11 6.2 Boards ................................................................................................................................ 11 6.3 Compiler and IDE versions: .................................................................................................. 11 6.4 Debug Probes ..................................................................................................................... 11 7. KNOWN ISSUES AND LIMITATIONS ............................................................................................... 12 7.1 S32 Design Studio integration............................................................................................... 12 7.2 S32 Configuration Tool integration ........................................................................................ 12 7.3 Drivers ................................................................................................................................ 12 7.4 Stacks................................................................................................................................. 13 7.5 Examples ............................................................................................................................ 13 8. COMPILER OPTIONS ................................................................................................................. 14 8.1 GCC Compiler/Linker/Assembler options............................................................................... 14 8.2 GHS Compiler/Linker/Assembler options............................................................................... 16 8.3 DIAB Compiler/Linker/Assembler options .............................................................................. 18 9. ACRONYMS ............................................................................................................................ 19 10. VERSION TRACKING ................................................................................................................. 20

1. Description
The S32 Software Development Kit (S32 SDK) is an extensive suite of peripheral drivers, RTOS, stacks and middleware designed to simplify and accelerate application development on NXP S32V23x ARM based microcontrollers.
This release has BETA quality status in terms of testing and quality documentation. BETA releases are not fully qualified and tested. BETA releases are release candidates that can be used by customer for development and qualification. It is not recommended to be used in production.
This SDK can be used as is (see Documentation) or it can be used with S32 Design Studio IDE.
Refer to License(License.txt) for licensing information and Software content register(SWContent-Register-S32-SDK.txt) for the Software contents of this product. The files can be found in the root of the installation directory.
For support and issue reporting use the following ways of contact: - NXP Support to https://www.nxp.com/support/support:SUPPORTHOME - NXP Community https://community.nxp.com/

2. New in this release

2.1 Drivers
PINS
· Added support for managing the identifier field for each pin and generate it as a define in the code.
FLEXRAY · Added driver.
CPU · Added Cache Management API. · Modified data and bss initialization mechanism. Regions that must be copied at startup or bss(zero initialized) regions are now grouped into two tables: zero_table and copy_table.
FLEXCAN, CAN_PAL · Added bitrate configuration in S32CT components.

2.2 Examples FreeRT OS
· Replaced makefile example with DS example project.

2.3 PAL PWM_PAL
· Added default configuration for configurator. ADC_PAL
· Configurator improvements.

2.4 Middleware · Added configuration components for TCP/IP and SDHC.

2.5 RTOS FreeRT OS
· Updated to v10.1.1

2.6 Fixed from EAR 0.8.1

Component adc_sar

Description
ADC returned incorrect values when left aligned representation was used for conversion results.

can_pal

Configuration component allowed invalid message buffer allocation (RX FIFO plus MBs space to exceed available MBs no).

clock_manager

VIDEO_PLL_PHI0_CLK could not be routed to clock output pin.

clock_manager

Description for several clock names in "Module clocks" table was incorrect.

clock_manager

Divider enablement was not implemented.

clock_manager crc eim examples

Values of selector entries generated by S32CT were incorrect for several peripheral clocks.
When multiple instances of CRC were selected in peripheral tool, there were compilation errors.
Added note in documentation for error recovery on channels 8 and 9, targeting Cortex-M4 System Cache Tag.
Warnings were shown when examples were imported.

examples

Delay period was not large enough in hello_world_mkf.

examples

STM example was issuing warning because interrupt manager header file was not included in main.c

examples

STM example was not working according to description.

flexcan header_file i2c i2c i2c i2c_pal ic_pal interrupt_manager mpu_pal

Driver did not clear MB RAM, which could trigger the module to enter Freeze mode on parts with ecc memory detection.
CDATA bitfield width was changed from 12 to 16 to match ADC_SAR working behavior.
Default name for I2C configuration structure was updated to avoid duplicated variables.
Bus busy was checked in case the previous transfer ended with repeated start to avoid the case when the master is keeping the bus busy until stop is generated and next transfer are blocked.
If DMA configuration erros are detected I2C_DRV_MasterSendDataBlocking and I2C_DRV_MasterSendData returns STATUS_ERROR.
Default name for I2C_PAL configuration structure was updated to avoid duplicated variables.
Some internal variables were updated to avoid unexpected behavior if IC_PAL over FTM channels are initialized as IC_DISABLE_OPERATION.
INT_SYS_GenerateDirectedCpuInterrupt method was removed from interrupt_manager public API because it did not feature any requirements, design and test cases.
An error was raised when MPU access error attributes were checked.

phy

PHY_GetState returned active state even when the PHY was powered down.

phy
pins pins pins

The value of the OUI field returned by PHY_GetID was incorrect.
NUM_OF_CONFIGURED_PINS was not generated correctly by the pins component. PINS configurator was generating incorrect base addresses for some pins. PINS configurator was not allowing multiple configurations to be generated.

pit pit power_manager
pwm_pal
qspi qspi qspi stm stm swt wdog_pal xrdc

LPIT_DRV_InitChannel() was disabling interrupts for all channels, if interrupt was not enabled in the configuration structure. Duplicate configuration names were not checked in driver configurators.
Duplicate configuration names were not checked in driver configurators.
Updated PWM_PAL component to verify that the duty is lower or equal to the period, to check that there are no duplicate configurations for one channel and removed Fixed clock that is not available over FTM. All drivers needed by QSPI were added automatically to project by CT component. If errors are detected by QSPI the DMA channels used in transfer were disabled.
QSPI read modes were updated in CT to match the driver code.
STM configurator did not allow configuration of multiple channels.
Duplicate configuration names were not checked in driver configurators.
When multiple instances of SWT were selected in peripheral tool, there were compilation errors.
Hint for Timeout Value was not correct in WDG_PAL configurator.
Duplicate configuration names were not checked in driver configurators.

3. Software Contents
3.1 Drivers
· ADC_SAR · CLOCK MANAGER · CPU · CRC · CSE3 · DSPI · EDMA · EIM · ENET · ERM · FCCU · FLEXCAN · FLEXRAY · FTM · HEADER · HYPERFLASH · I2C · INTERRUPT MANAGER · LINFLEXD_UART · OSIF · PHY · PINS · PIT · POWER MANAGER · QSPI · SEMA42 · STM · SWT · USDHC · WKPU · XRDC
3.2 PAL
· ADC_PAL · CAN_PAL · I2C_PAL · IC_PAL · MPU_PAL · OC_PAL · PWM_PAL · SECURITY_PAL · SPI_PAL · TIMING_PAL · UART_PAL · WDOG_PAL

3.3 RTOS · FreeRTOS version 10.1.1
3.4 Middleware
· SDHC · TCP/IP

4. Documentation
· Quick start guide available in "doc" folder. · User and integration manual available at "doc\Start_here.html". · Driver user manuals available in "doc" folder. · Release notes for Middleware available in "doc" folder. · Documentation for the Middleware can be found in the respective folder.

Driver examples

5. Examples
Name adc_swtrigger adc_pal can_pal
crc_checksum edma_transfer eim_injection enet_ping erm_report fccu_fault_injection
flexcan
flexray ftm linflexd_uart mpu_pal_memory_protection oc_pal phy_autoneg pit_periodic_interrupt power_mode_switch stm_periodic_interrupt swt_interrupt timing_pal uart_pal wdg_pal_interrupt xrdc_memory_protection FreeRTOS
hello_world
hello_world_mkf
lwip
sdhc_fatfs

Description Shows the functionality of ADC_SAR Shows the functionality of ADC_PAL Shows the usage of CAN PAL over FlexCAN interface Calculates CRC using the peripheral driver for multiple standards Shows the usage of eDMA Shows the functionality of the EIM Shows the functionality of ENET Shows the functionality of the ERM Show the usage of FCCU driver Shows the usage of FlexCAN driver configured as both bus master and slave Shows the functionality of FLEXRAY Shows the usage of the FTM Shows the functionality of LINFLEXD Shows the usage of the MPU_PAL Shows the usage of the OC_PAL over FTM Shows the functionality of PHY Shows the usage of the PIT Transitions the MCU into all available power modes Shows the usage of the STM Shows the usage of the SWT Shows the usage of the TIMING_PAL over PIT and FTM Shows the usage of UART PAL over LinFlexD Shows the usage of the WDOG_PAL Shows how to use Extended Resource Domain Controller
Shows the usage of FreeRTOS This is a simple application created to show the basic configuration with S32DS This is a simple application created to show the basic configuration with makefile for the supported compilers
Shows the usage of TCP IP stack
Shows the usage of SDHC stack

Demos

6. Supported hardware and compatible software
6.1 CPUs · S32V234 - 1N81U · S32V232
The following processor reference manual has been used to add support: · S32V234RM Rev. 3 10/2017
6.2 Boards · EVB SBC-S32V234 Microsys · X-TR-DVAL-625 PCB RevX2
6.3 Compiler and IDE versions: · GCC Compiler for ARM NXP GCC 6.3.1 o 20170509 (BLD = 1574 rev=g924fb68) o included in S32 Design Studio v2018.EAR3 · Green Hills Multi 7.1.4 / v.2017.1.4 · Windriver DIAB Compiler v5.9.6.2
6.4 Debug Probes · Lauterbach TRACE32 JTAG Debugger · P&E Multilink (with P&E GDB Server)

7. Known issues and limitations
7.1 S32 Design Studio integration · An error is returned when a new component is added to the project. · Attach / Detach SDK functionality does not work at the moment, therefore the user cannot create a project without the SDK and add it afterwards. Workaround: Create a project with SDK enabled from the beginning with New Project Wizard or start from an example from the SDK release.
7.2 S32 Configuration Tool integration · If the same configuration component is enabled over multiple module instances, the according generated structures will have the same name. It is user's responsibility to make sure different names are used for different structures.
7.3 Drivers CLOCK_MANAGER
· Clock sources can't be enabled/disabled per power mode. A clock source is enabled or is disabled in all power modes. Module clock gate can't be configured from "Peripheral clocks". As a workaround module clock gate must be configured from clock diagram
· SMDEN, SSCGBYP, STEPSIZE, STEPNO PLL parameters are not configurable. PINS
· Generating the settings for the DDR pins is not supported. · For PINS PA1 and PA2 the default values for drive strength, slew rate, Pull select
field and Pull Up / Down Config are different from the reset values. LINFLEXD_UART
· In DMA mode, a new reception may contain junk data received previously; the FIFO cannot be flushed before receiving a new buffer.
SWT · Module does not return a bus error when accesses are invalid and the module is configured to not reset the CPU on invalid accesses.
FTM_MC · Frequency Value from user interface is always 1200000000Hz, no matter how clock tree is configured. · The hardware trigger is not work as expected when the source is ENET module from MAC0_TIMER3 to trigger0 of FTM.
PIT /ST M · Module cannot run in Debug Mode (counter not count).
QSPI · Despite QSPI_READ_MODE_LOOPBACK_DQS and QSPI_READ_MODE_INTERNAL_SAMPLING modes being available in CT component, they are not available in source code. Please don't use these modes in your application.

CTU · Component appears in the drivers list in "Manage SDK Components" view in S32 Configuration Tool, but it is not supported in this release (should be disregarded).
ET IM ER · Component appears in the drivers list in "Manage SDK Components" view in S32 Configuration Tool, but it is not supported in this release (should be disregarded).
POWER_MANAGER · User must enable clock source in other mode of the clock configuration which correspond with peripheral clock source. This one is changed before user calls the API CLOCK_DRV_Init.
FLEXRAY · FLEXRAY_DRV_ClearGlobalInterruptFlag does not clear FLEXRAY_FIFOA_INTERRUPT. · FLEXRAY_DRV_SendBlocking, FLEXRAY_DRV_GetTransferStatus return STATUS_SUCCESS in case of conflict on TX.
7.4 Stacks T CP/IP
· No FreeRTOS support (i.e. only bareboard version is available). SDHC
· File system timestamp is not available.
7.5 Examples · Some examples may display warning messages with unresolved includes.

8. Compiler options

8.1 GCC Compiler/Linker/Assembler options

Table 8-1 GCC Compiler options

-mcpu=cortex-m4 -mthumb

Option

-std=gnu99 -DCPU_S32V234 -L$(<library_path>)

-g -mfpu=fpv4-sp-d16 -mfloat-abi=hard -O1 -Werror -Wall -Wextra -Wstrict-prototypes
-pedantic -Wunused -Wsign-compare -funsigned-char -funsigned-bitfields -fshort-enums
-ffunction-sections
-fdata-sections
-fno-common

-fno-jump-tables

Description Selects target processor: Arm Cortex M4 Selects generating code that executes in Thumb state. Use C99 standard Define a preprocessor symbol for MCU Add specific library used in the compiler options. V23X : ../arm-none-eabi/newlib/lib/thumb/v7em/fpv4-sp/(softfp or hard) Generate debug information Use single precision FPU instructions
Optimize option Treat warnings as errors Produce warnings about questionable constructs Produce extra warnings that -Wall Warn if a function is declared or defined without specifying the argument types. Issue all the warnings demanded by strict ISO C Produce warnings for unused variables Produce warnings when comparing signed type Let the type char be unsigned, like unsigned char Bit-fields are signed by default Allocate to an enum type only as many bytes as it needs for the declared range of possible values. Place each function into its own section in the output file Place data item into its own section in the output file The -fno-common option specifies that the compiler should place uninitialized global variables in the data section of the object file. Do not use jump tables for switch statements

-mcpu=cortex-m4 -mthumb

Option

--entry=<entry_symbol> -T <linker_script_file.ld> -Xlinker --gc-sections -lc -lm, -lgcc
-Wl, -Map=<map_file_name> -mfpu=fpv4-sp-d16 -mfloat-abi=hard

Table 8-2 GCC Linker options
Description Selects target processor Selects generating code that executes in Thumb state Make the symbol Reset_Handler be treated as a root symbol and the start label of the application Use the specified linker file Remove unused sections Link C library Link Math library, Link libgcc Produce a map file
Use single precision FPU instructions

-mcpu=cortex-m4 -mthumb

Option

-mfpu=fpv4-sp-d16 -mfloat-abi=hard
-x assembler-with-cpp

Table 8-3 GCC Assembler options
Description Selects target processor Selects generating code that executes in Thumb state
Use single precision FPU instructions Preprocess assembly files

8.2 GHS Compiler/Linker/Assembler options

-cpu=cortexm4
-thumb -c99 --gnu_asm -DCPU_S32V234

Option

-L$(<library_path>) -gdwarf-2 -G -fsingle, -fhard, -fpu=vfpv4_d16 -Wunknown-pragmas -Wimplicit-int

-Wshadow -Wtrigraphs -Wundef

--quit_after_warnings --unsigned_chars -unsigned_fields --short-enum -fno-common

Table 8-4 GHS Compiler options
Description Selects target processor Selects generating code that executes in Thumb state. Use C99 standard Enables GNU extended asm syntax support Define CPU name Add specific library used in the compiler options. /lib/thumb2 Generate DWARF 2.0 debug information Generate debug information Use single precision FPU instructions
Produce warnings if functions are assumed to return int Produce warnings if variables are shadowed Produce warnings if trigraphs are detected Produce a warning if undefined identifiers are used in #if preprocessor statements Treat warnings as errors Let the type char be unsigned, like unsigned char Bitfields declared with an integer type are unsigned Store enumerations in the smallest possible type Allocates uninitialized global variables to a section and initializes them to zero at program startup

-cpu=cortexm4

Option

-entry=<entry_symbol> -T <linker_script_file.ld> -map=<map_file_name> -larch

-entry=<entry_symbol>

Table 8-5 GHS Linker options
Description
Selects target processor Make the symbol Reset_Handler be treated as a root symbol and the start label of the application
Use the specified linker file Produce a map file
Link architecture specific library Make the symbol Reset_Handler be treated as a root symbol and the start label of the application

Option -cpu=cortexm4 -preprocess_assembly_files

Table 8-6 GHS Assembler options
Description Selects target processor Preprocess assembly files

8.3 DIAB Compiler/Linker/Assembler options

Option -tARMCORTEXM4LV
-mthumb -Xdialect-c99 -DCPU_S32V234 -Xfp-float-only -g -ei5388,5387,1824 -Xstop-on-warning
-Xsection-split
-Xno-common

Table 8-7 DIAB Compiler options
Description Selects target processor Selects generating code that executes in Thumb state Use C99 standard Define CPU name Use single precision FPU Add debug information to the executable ignore some specific warnings Treat warnings as error Generate a separate section for each function/variable to remove some unused function Allocates uninitialized global variables to a section and initializes them to zero at program startup

Option -tARMCORTEXM4LV -Xremove-unused-sections
-lc
-lm <linker_script_file.dld> -e <entry_symbol> -m6 > <map_file_name>

Table 8-8 DIAB Linker options
Description
Selects target processor Removes unused code sections
Link the standard C library to the project in order to support elementary operations that are used by the drivers Link the standard math library to the project in order to support elementary math operations that are used by the drivers
Use the specified linker file Make the symbol Reset_Handler be treated as a root symbol and the start label of the application
Produce a linker map

Option -tARMCORTEXM4LV -Xpreprocess-assembly

Table 8-9 DIAB Assembler options
Description Selects target processor Preprocess assembly files

9. Acronyms

Acronym EAR JRE EVB PAL RTOS S32CT PD S32DS SDK SOC RTM

Description Early Access Release Java Runtime Environment Evaluation board Peripheral Abstraction Layer Real Time Operating System S32 Configuration Tool Peripheral Driver S32 Design Studio IDE Software Development Kit System-on-Chip Release To Manufacture

10. Version Tracking

Date

Version

(dd-Mmm-YYYY)

Comments

14-Oct-2016

1.0

First version for EAR 0.8.0

30-Ian-2017

1.1 First version for S32V EAR 0.8.0

10-Dec-2018

1.2 First version for S32V EAR 0.8.1

26-Mar-2019

1.3 First version for S32V BETA 0.9.0

Author
Cezar Dobromir
Iulian T.
Banciu Alexandru
Banciu Alexandru

Microsoft Word 2016