Index of /components/exar/ dataBooks
Introduction
This Data Book contains a comprehensive collection of application notes and technical articles, prepared by Exar's engineering staff. These articles cover the use and applications of Exar's broad line of monolithic IC products. The applications and design examples discussed cover a wide range of subjects, from FSK Modem design to electronic music synthesis. In each case, specific design examples are given to illustrate the use of the integrated circuit in that particular application or end product.
EXPERIENCE AND PRODUCTS
Exar's innovativeness, product quality and responsiveness to customer needs have been the key to its success. Exar today offers a broad line of linear and interface circuits. In the field of standard linear IC products, Exar has extended its circuit technological leadership into the areas of communications and control circuits. Today Exar has one of the most complete lines of IC oscillators, timing circuits and phase-locked loops in the industry. Exar also manufactures a large family of telecommunication circuits such as tone decoders, compandors, modulators, PCM repeaters and FSK Modem Circuits. In the field of industrial control circuits, Exar manufactures a broad line of quad and dual operational amplifiers,voltage regulators, radio-control and servo driver IC's, and power control circuits.
Exar's experience and expertise in the area of bipolar IC technology extends both into custom and standard IC products. In the area of custom IC's, Exar has designed, developed, and manufactured a wide range of full-custom monolithic circuits, particularly for applications in the areas of telecommunications, consumer electronics, and industrial controls.
In addition to the full-custom capability, Exar also offers a unique semi-custom IC development capability for low to medium-volume custom circuits. This semi-custom program, is intended for those customers seeking cost-effective solutions to reduce component count and board size in order to compete more effectively in a changing marketplace. The program allows a customized monolithic IC to be developed with a turnaround time of several weeks at a small fraction of the cost of a full-custom development program.
EXCELLENCE IN ENGINEERING
Exar quality starts in Engineering where highly qualified people are backed up with the advanced instruments and facilities needed for design and manufacture of custom, semicustom and standard integrated circuits. Exar's engineering and facilities are geared to handle all three classes of IC design: (1) semi-custom design programs using Exar's bipolar and I2L master chips; (2) full-custom IC design; (3) development and high-volume production of standard products.
Some of the challenging and complex development programs successfully completed by Exar include analog compandors and PCM repeaters for telecommunication, electronic fuelinjection, anti-skid braking systems and voltage regulators for automotive electronics, digital voltmeter circuits, 40-MHz frequency synthesizers, high-current and high-voltage display and relay driver ICs, and many others.
NEW TECHNOLOGIES
Through company sponsored research and development activities, Exar constantly stays abreast of all technology areas related to changing customer needs and requirements. Exar has recently completed development efforts in Integrated Injection Logic (12L) technology, which offers unique advantages in the area of low-power, high-density logic arrays. Exar has a complete design engineering group dedicated to this new technology, and is currently supplying over twenty different custom and semi-custom I2L products.
FIRST IN QUALITY
From incoming inspection of all materials to the final test of the finished goods, Exar performs sample testing of each lot to ensure that every product meets Exar's high quality standards. Exar's manufacturing process is inspected or tested in accordance with its own stringent Quality Assurance Program, which is in compliance with MIL-Q-9858A. Additional special screening and testing can be negotiated to meet individual customer requirements.
Throughout the wafer fab and assembly process, the latest scientific instruments, such as scanning electron microscopes, are used for inspection, and modern automated equipment is used for wafer probe, AC, DC, and functional testing. Environmental and burn-in testing of finished products is also done in-house. For special environmental or high reliability burn-in tests outside testing laboratories are used to complement Exar's own extensive in-house facilities.
FIRST IN SERVICE
Exar has the ability and flexibility to serve the customer in a variety of ways from wafer fabrication to full parametric selection of assembled units for individual customer requirements. Special marking, special packaging and military screening are only a few of the service options available from Exar. We are certain that Exar's service is flexible enough to satisfy 99% of your needs. The company has a large staff of Applications Engineers to assist the customer in the use of the product and to handle any request, large or small.
Exar reserves the right to make changes at any time in order to improve design and to supply the best product possible.
Exar cannot assume responsibility for any circuits shown or represented, as being free from patent infringement.
Table of Contents
Page OVERVIEW OF EXAR'S APPLICATION NOTES .............................................. 2
ADDITIONAL TECHNICAL LITERATURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
APPLICATION NOTES
AN-01 Stable FSK Modems Featuring XR-2206, XR-2207 and XR-2211 ......................... 4 AN-02 XR-C240 Monolithic PCM Repeater ................................................ 9 AN-03 Active Filter Design with IC Op Amps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 AN-04 XR-C277 Low Voltage PCM Repeater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 AN-05 Tri-State FSK Modem Design Using XR-2207 and XR-2211 ............................ 28 AN-06 Precision PLL System Using the XR-2207 and the XR-2208 ............................ 34 AN-07 Single-Chip Frequency Synthesizer Employing the XR-2240 ............................ 37 AN-08 Dual Tone Decoding with XR-567 and the XR-2567 .................................. 39 AN-09 Sinusoidal Output from XR-215 Monolithic PLL Circuit ............................... 41 AN-10 XR-C262 High Performance PCM Repeater ......................................... 43 AN-11 A Universal Sinewave Converter Using the XR-2208 and XR-2211 ....................... 51 AN-12 Designing High Frequency Phase-Locked Loop Carrier-Detector Circuits ................... 55 AN-13 Frequency Selective AM Detection Using Monolithic Phase-Locked Loops ................. 58 AN-14 A Complete Function Generator System Using the XR-2206 ............................ 62 AN-15 An Electronic Music Synthesizer Using the XR-2207 and the XR-2240 .................... 66 AN-16 Semi-Custom LSI Design with I2L Gate Arrays ...................................... 68 AN-17 XR-C409 Monolithic I2L Test Circuit ............................................. 74
QUALITY ASSURANCE STANDARDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
PRODUCT ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
FOREIGN SALES OFFICES AND REPRESENTATIVES ........................................ 80
AUTHORIZED STOCKING DISTRIBUTORS ................................................. 81
AUTHORIZED REPRESENTATIVES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Overview of Exar's Application Notes
The following list gives a brief summary, and the description, of the subject material covered in each one of Exar's Application Notes included in this Data Book.
AN-01: Stable FSK Modems Featuring the XR-2206, XR-2207 andXR-2211 Design of stable full-duplex FSK modems is described using the XR-2206 or the XR-2207 as the modulator, and the XR-2211 as the demodulator with carrier-detection capability. Complete design examples are given for FSK modems covering mark/space frequencies from a few Hertz to 100 kHz.
AN-02: XR-C240 Monolithic PCM Repeater The principle of operation of the XR-C240 monolithic regenerative repeater IC is described. Design examples and external connections of the circuit are discussed for applications in T-1 type 1.544 Megabit PCM telephone lines.
AN-03: Active Filter Design with IC Op Amps This application note is intended to familiarize the filter designer with the fundamentals of active filter design, using monolithic IC op amps. It presents a table of transfer functions and network equations for high-pass, low-pass, band-pass and band-reject filters. Several design examples are given to illustrate the respective merits and limitations of various filter configurations. Particular emphasis is given to applications of programmable quad operational amplifiers, such as the XR-4202, as an active filter element in FSK Modems.
AN-04: XR-C277 Low-Voltage PCM Repeater IC The design principles and the applications of the XR-C277 low-voltage (6.3 volt) regenerative PCM repeater are described. The monolithic IC contains all the basic functional blocks of a conventional PCM repeater, including the automatic line builtout section. Circuit connection diagrams and application examples are given for operation in 1.544 Megabit T-1 type PCM telephone systems.
AN-07: Single-Chip Frequency Synthesizer Employing the XR-2240 (Reprinted in This Data Book) The operation of the XR-2240 programmable/counter IC as a frequency synthesizer is described. The circuit can simultaneously multiply an input frequency by an integer modulus M, and divide it by a different modulus N+l. Thus, a wide range of non-integer output frequencies can be produced from a single input reference frequency.
AN-08: Dual-Tone Decoding with XR-567 and XR-2567 Application examples are given for simultaneous or sequential decoding of dual-tone control signals using either two XR-567 PLL tone decoders, or a single XR-2567 dual tone decoder. The examples include high-speed, narrow-band tone detection and Touch-Tone® decoding.
AN-09: Sinusoidal Output from XR-215 Monolithic PLL Circuit A simple circuit technique is described to convert the VCO output of the XR-215 into a low-distortion sinewave. The external sinewave-shaping circuit is obtained using the XR-ClOl monolithic NPN transistor array.
AN-10: XR-C262 High-Performance PCM Repeater The design principle and the electrical characteristics of the XR-C262 high-performance PCM repeater IC are described. The circuit contains all the active components necessary for a regenerative PCM repeater system and operates with a single 6.8 volt power supply. Circuit connection and application examples are given for its use in 1.5 Megabit or 2 Megabit PCM systems.
AN-11: A Universal Sinewave Converter Using the XR-2208 andXR-2211 A circuit technique is described which can convert any periodic waveform into a low-distortion sinewave. The circuit operation is completely independent of input waveform amplitude and frequency as long as the input signal is periodic, and can operate over a frequency range of 1 Hz to over 100 kHz.
AN-OS: Tri-State FSK Modem Design Using XR-2207/XR-2211 Design of FSK modems with carrier detection and control capability are discussed. Such a "tri-state" modem uses a third carrier frequency for control functions, in addition to the normal "mark" and "space" frequencies used in conventional "bi:state" FSK systems. This carrier control feature allows each transmitter in a modem system to be automatically interrogated, one at a time, by a control processor, without interference from other modem transmitters within the system.
AN-06: Precision PLL System Using XR-2207 /XR-2208 A two-chip versatile phase-locked loop system is described, using the XR-2207 oscillator as the VCO, and the XR-2208 multiplier as the phase detector. The resulting PLL system features 20 ppm/°C temperature stability. Design equations are given to tailor the circuit parameters to specific applications.
AN 12: Designing High Frequency Phase-Locked Loop CarrierDetector Circuits A design technique is described for high frequency tone or carrier detection. The two-chip circuit uses either the XR-210 or the XR-215 PLL circuit, in conjunction with the XR-2228 multiplier/detector, and can operate with carrier frequencies up to 20MHz.
AN-13: Frequency Selective AM Detection Using Monolithic Phase-Locked Loops The fundamentals of synchronous AM detection techniques are reviewed. The application of monolithic PLL circuits for frequency-selective AM detection is discussed. Several design examples are given, both for low- and high-frequency demodulation applications, using the XR-2212 or the XR-215 PLL circuits, in conjunction with the XR-2228 modulator/detector integrated circuit.
2
AN-14: A Complete Function Generator System Using the XR-2206 A laboratory quality self-contained function generator system is described, using the XR-2206 waveform generator IC. Complete circuit connection diagram, parts list and assembly instructions are given for a DC to 100 kHz self-contained function generator system with AM/FM capability and triangle, sine and square wave output.
AN-IS: An Electronic Music Synthesizer Using the XR-2207 and the XR-2240 (Reprinted in This Data Book) Design of a simple, low-cost "music synthesizer" system is described. The electronic music synthesizer is comprised of the XR-2207 voltage-controlled oscillator IC which is driven by the pseudo-random binary pulse pattern generated by the XR-2240 counter/timer circuit.
AN-16: Semi-Custom LSI Design with I2L Gate Arrays A unique design approach to developing complex LSI systems is described using XR-300 and XR-500 12 L gate arrays. This technique greatly reduces the design and tooling cost and the prototype fabrication cycle associated with the conventional full-custom IC development cycle; and thus makes custom ICs economically feasible even at low production volumes.
AN-17: XR-C409 Monolithic I2L Test Circuit A monolithic test circuit has been developed for evaluation of speed and performance capabilities of Exar's Integrated Injection Logic (12L) technology. This test circuit, designated the XR-C409, is intended to familiarize the I2L user and the system designer with some of the performance features of I2L such as its frequency capability and power-speed tradeoffs.
Additional Technical Literature
As a companion set to this Applications Data Book, Exar's technical staff and applications engineers have prepared a s~ries of additional Data Books which cover some of the key features and applications of Exar's other IC products. These Data Books also present a number of tutorial articles on the fundamentals of such important IC products as timers, phaselocked loops, and voltage-controlled oscillators. These books are available directly from your Exar sales or technical representative ..
A brief description of each of these data books is given below:
LINEAR AND DIGITAL SEMI-CUSTOM DESIGN BROCHURE:
This brochure contains a detailed description of Exar's unique bipolar and integrated injection logic (12L) semi-custom design technology. Economic advantages of the semi-custom designs are discussed and economic guidelines are given for choosing the most cost-effective solution to a custom IC requirement. In addition, this brochure provides technical information on Exar's Master Chips and IC Design Kits. (36 pages)
TIMER DATA BOOK:
This data book provides a collection of technical articles and application information on monolithic timer IC products. Also included are the data sheets and the detailed electrical specifications of all of Exar's timer circuits, including the programmable timer/counters, micropower and long-delay timers. (48 pages)
FUNCTION GENERATOR DATA BOOK:
This comprehensive data book contains a number of technical articles and application notes on monolithic voltage-controlled oscillator (VCO) and function generator IC products. In addition, the data sheets and technical specifications of Exar's monolithic VCO's and function generators are given. (50 pages)
OPERATIONAL AMPLIFIER DATA BOOK:
This book contains a collection of technical articles on the fundamentals of monolithic IC op-amps. Some of the basic op-amp circuits are given, and the applications of IC op-amps in active filter design are discussed. The book also contains a complete set of electric! specifications in Exar's bipolar and BIFET op-amp products. (60 pages)
PHASE-LOCKED LOOP DATA BOOK:
This data book covers the fundamentals of design and applications of monolithic phase-locked loop (PLL) circuits. A long list of PLL applications are illustrated covering FM demodulation, frequency synthesis, FSK and tone detection. Particular emphasis is given to application of PLL circuits in data interface and communication systems such as FSK modems. This book also contains the data sheets and electrical specifications of all of Exar's PLL products. (74 pages)
3
Application Note
AN-01
Stable FSK Modems Featuring the XR-2207, XR-2206 and XR-2211
INTRODUCTION
Frequency shift keying (FSK) is the most commonly used method for transmitting digital data over telecommunications links. In order to use FSK, a modulator-demodulator (modem) is needed to translate digital 1's and O's into their respective frequencies and back again.
This Applications Note describes the design of a modem using state-of-the-art Exar devices specifically intended for modem application. The devices featured are the XR-2206 and XR-2207 FSK modulators, and the XR-2211 FSK demodulator with carrier-detect capability. Because of the superior frequency stability (typically 20 ppm/°C) of these devices, a properly designed modem using them will be virtually free of the temperature and voltage-dependent drift problems associated with many other designs. In addition, the demodulator performance is independent of incoming signal strength variation over a 60 dB dynamic range. Because bias voltages are generated internally, the external parts count is much lower than in most other designs. The modem designs shown in this Applications Note can be used with mark and space frequencies anywhe're from several Hertz to 100 kiloHertz.
THE XR-2206 FSK MODULATOR
FEATURES · Typically 20 ppm/°C temperature stability · Choice of 0.5% THD sinewave, triangle, or squarewave
output · Phase-continuous FSK output · Inputs are TTL and C/MOS compatible · Low power supply sensitivity (0.01%/V)
Potentiometers Rs and R9 should be adjusted for minimum total harmonic distortion. In applications where minimal distortion is unnecessary, pins 15 and 16 may be left opencircuited and Rs may be replaced by a fixed 200n resistor. In applications where a triangular output waveform is satisfactory, pins 13 thru 16 may be left open-circuited.
The output impedance at pin 2 is about 600n. In most applications, AC coupling of the output is recommended.
· Split or single supply operation
· Low external parts count
OPERATION
The XR-2206 is ideal for FSK applications requiring the spectral purity of a sinusoidal output waveform. It offers TTL and C/MOS compatibility, excellent frequency stability, and ease of application. The XR-2206 can typically provide a 3 volt p-p sinewave output. Total harmonic distortion can be trimmed to 0.5%. If left untrimmed, it is approximately 2.5%.
The circuit connection for the XR-2206 FSK Generator is shown in Figure 1. The data input is applied to pin 9. A high level signal selects the frequency (1/R6C3 ) Hz; a low level signal selects the frequency (1/R7C3) Hz, (resistors in ohms and capacitors in farads). For optimum stability, R6 and R1 should be within the range of 10 kn to 100 kn. The voltage applied to pin 9 should be selected to fall between ground and V+.
Note: Over and under voltage may damage the device.
SINE OR TRIANGLE FSK OUTPUT <>---,,,.._=---<
'Vl.i
'-------0 ~~~~~~~~~E
4.7K
V+
Figure 1. The XR-2206 Sinusoidal FSK Generator
4
THE XR-2207 FSK MODULATOR
FEATURES
+12V
· Typically 20 ppm/°C temperature stability · Phase-continuous FSK output · Provides both triangle and squarewave outputs · Operates single-channel or two-channel multiplex · Inputs are TTL and C/MOS compatible · Split or single power supply operation · Low power supply sensitivity (0.15%/V) · Low external parts count OPERATION
FSK OUTPUT
The XR-2207 is a stable FSK generator which is designed for those applications where only a triangle or squarewave output is required. It is capable of either single-channel or two-channel multiplex operation, and can be used easily with either split or single power supplies.
Figure 2. The XR-2207 FSK Modulator Single-Supply Operation
+6V
Figure 2 shows the XR-2207 using a single-supply and Figure 3 shows split-supply operation. When used as an FSK modulator pins 8 and 9 provide the digital inputs. When the 2207 is used with a split-supply, the threshold at these pins is approximately +2 volts, which is a level that is compatible with both TTL and C/MOS logic forms. When used with a single supply, the threshold is near mid-supply and is C/MOS compatible. Table 1 shows how to select the timing resistors R1 thru R4 to determine the output frequency based upon the logic levels applied to pins 8 and 9. For optimum stability, the values of R 1 and R 3 should be selected to fall between 10 kn and 100 kn.
With pin 8 grounded, pin 9 serves as the data input. A high level signal applied to pin 8 will disable the oscillator. When used in this manner, pin 8 of the XR-2207 serves as the channel select input. For two-channel multiplex operation, pins 4 and 5 should be connected as shown by the dotted lines. (For single channel operation, pins 4 and 5 should be left open-circuited.)
The XR-2207 provides two outputs; a squarewave at pin 13 and a trianglewave at pin 14. When used with a split-supply, the trianglewave peak-to-peak amplitude is equal to V- and the de level is near ground. Direct coupling is usually used. With a single-supply, the peak-to-peak amplitude is approximately equal to YzV+, the DC level is at approximately midsupply and AC coupling is usually necessary. In either case, the output impedance is typically !On and is internally protected against short circuits.
The squarewave output has an NPN open-collector configuration. When connected as shown in Figure 2 or 3 this output voltage will swing between V+ and the voltage at pin 12.
1-r---.:---v fJl/N\ FS K
nJJl OUTPUT
-6V
DATA INPUT 1·t-----<> ENABLE/DISABLE OR
CHANNEL SELECT
-6V
Figure 3. The XR-2207 FSK Modulator Split-Supply Operation
TABLE I XR-2207 FSK Input Control Logic
Logic Level Pin 8 Pin 9
L
L
L
H
H
L
H
H
Active Timing Resistor Pin 6
Pins 6 and 7 Pin 5
Pins 4 and 5
Output Frequency
-I-
CoR1 -1- + -1CoR1 CoR2
-1-
CoR3 -1- + -I CoR3 CoR4
Units: Resistors - Ohms; Capacitors - Farads; Frequency - Hz
5
THE XR-221 FSK DEMODULATOR WITH CARRIER DETECT
FEATURES
· Typically 20 ppm/°C temperature stability
· Simultaneous FSK and carrier-detect output
· Outputs are TTL and C/MOS compatible
· Wide dynamic range (2 mV to 3 Vrms)
· Split or single supply operation
· Low power supply sensitivity (0.05%/V)
· Low external parts count
OPERATION
The XR-2211 is a FSK demodulator which operates on the phase-locked-loop principle. Its performance is virtually independent of input signal strength variations over the range of 2 mV to 3 Vrms.
Figure 4 shows the circuit connection for the XR-2211. The
center frequency is determined by f0 = (1/C 1R4 ) Hz, where
capacitance is in farads and resistance is in ohms. F0 should be calculated to fall midway between the mark and space frequencies.
The tracking range (±l::.f) is the range of frequencies over which the phase-locked loop can retain lock with a swept input signal.
This range is determined by the formula: l::.f =(R4 f0 /R5 ) Hz.
L::,f should be made equal to, or slightly less than, the difference between the mark and space frequencies. For optimum stability, choose an R4 between 10 kQ and 100 kD.
The capture range (±L::,fc) is the range of frequencies over which the phase-locked loop can acquire lock. It is always less than the tracking range. The capture range is limited by C2 , which, in conjunction with R5 , forms the loop filter time constant. In most modem applications, Mc= (80% - 99%) l::.f.
The loop damping factor Cn determines the amount of over-
shoot, undershoot, or ringing present in the phase-locked loop's response to a step change in frequency. It is determined by
r = 14v'C 1/C 2 . For most modem applications, choose~~ Yz.
The FSK output filter time constant (rF) removes chatter from
the FSK output. The formula is: TF = RFCF. Normally
calculate Tr to be approximately equal to [0.3/(baud rate)]
seconds.
The lock-dek!ct filter capacitor (C 0 ) removes chatter from the lock-detect output. With R0 = 510 kQ, the minimum value of C0 can be determined by: C0 (µf) ~ 16/capture range in Hz. Note: Excessive values of Cn will unnecessarily slow the lockdetect response time.
The XR-2211 has three NPN open collector outputs, each of which is capable of sinking up to 5 mA. Pin 7 is the FSK data output, Pin 5 is the Qlock-detect output, which goes low when
a carrier is detected, and Pin 6 is the Q lock detect output, which goes high when lock is detected. If pins 6 and 7 are
wired together, the output signal from these terminals will provide data when FSK is applied and will be "low" when no carrier is present.
If the lock-detect feature is not required, pins 3, 5 and 6 may be left open-circuited.
+12V
0.1;; F ::C.
XR-2211
510Kll
Q LOCK DETECT OUTPUT 0 LOCK-DETECT OUTPUT
:r: c,
Figure 4. The XR-2211 FSK Demodulator with Carrier Detect
DESIGNING THE MODEM
Table 2 shows recommended component values for the three most commonly used FSK bands. In many instances, system constraints dictate the use of some non-standard FSK band. The XR-2206/XR-2207, XR-2211 combination is suitable for any range of frequencies from several Hertz to 100 kiloHertz.
· For maximum baud rate, choose the highest upper frequency that is consistent with the system bandwidth.
· The lower frequency must be at least 55% of the upper frequency. (Less than a 2: I ratio)
Here are several guidelines to use when calculating non-standard frequencies:
· For minimum demodulated output pulsewidth jitter, select an FSK band whose mark and space frequencies are
6
both high compared to the baud rate. (i.e., for a 300 baud channel, mark and space frequencies of 2025 Hz and 2225 Hz would result in significantly less pulsewidth jitter than 300 Hz and 550 Hz).
· For any given pair of mark and space frequencies, there is a limit to the baud rate that can be achieved. When maximum spacing between the mark and space frequencies is used (where the ratio is close to 2: 1) the relationship
For narrower spacing, the minimum ratio should be about 67%.
· The values shown in Table 2 may be scaled proportionately for mark and space frequencies, maximum baud rate, and (inversely) capacitor value. It is best to retain (approximately) the resistor values shown.
mark-space frequency difference (Hz) ~83% maximum data rate (baud)
should be observed.
TABLE 2 Recommended Component Values for Typical FSK Bands
FSK Band
XR-2207
XR-2206
XR-2211
Baud Rate
fL
fu R1A R1e R2A R2B Co ~A ~B R1A R1e C3 R4A ~B Rs C1 R3A R3B R4A R4B
C2
Cp Co
300 1070 I270 IO 20 100 IOO .039 IO I8 IO 20 .039 IO I8 IOO .039 .01 .005 .OS
300 202S 222S IO I8 ISO 160 .022 10 16 10 18 .022 10 18 200 .022 .0047 .OOS .OS
I200 I200 2200 20 30 20 36 .022 IO I6 20 30 .022 10 I8 30 .027 .01 .0022 .01
Units: Frequency - Hz; Resistors - kn; Capacitors - µF
DESIGN EXAMPLES
A. Design a modem to handle a 10 kilobaud data rate, using the minimum necessary bandwidth.
b. For the XR-2206, we can make R7 equal to R1
and C3 equal to c0 above. To detennine R6 :
1. Frequency Calculation Because we want to use the minimum possible bandwidth (lowest possible upper frequency) we will use a 55: 100 frequency ratio. The frequency difference, or 4S% of the upper frequency, will be 83% of I0,000. We therefore choose an upper frequency:
83 x 10,000 = 18.444 kHz '"'=' 18.S kHz.
45
and the lower frequency:
0.55 x 18.S kHz = 10.175 kHz.
2. Component Selection a. For the XR-2207 FSK modulator, set R 1 '"'=' 30 kn. Now, select a value ofC 0 to generate 10.l 7S kHz with R1 :
10.175 kHz = l/(C0 x 30,000) ;C 0 = 3300 pF. To choose R2:
18.SOO kHz - 10.175 kHz = 8.32S kHz l/CoR2 ; R2 = 36 kn.
A good choice would be to use l 0 kn potentiometers for R1A and R2A, and to set R18 = 24 kn
and R28 =30 kn.
Use a IO kn potentiometer for R6A and set
R 6B = 13 kn.
c. For the XR-2211 demodulator, we need to first
detennine R4 and C1. First, f0 = (fL + f8 )/2 = (I0.17S + 18.S00)/2 = 14.338 kHz. If we make
R4 = 25 kn, then 1/(C 1 x 25,000) = 14,338; C1 = 2790 pF '"'=' 2700 pf. With that value of C1, the precise value of R4 is now 2S .8 kn. Select
R4s = 18 kn and use a IO kn for R4A.
3. Frequency Component Selection
a. To calculate R5 , we first need our .:lf, which is 18.500 - 10.175, or 8.32S kHz.
832S = (2S,800 x 14,338)/Rs ; R5 = 44.4 kn'""" 47 kn.
b. To detennine C2 use~= Yz = Y<i ../C 1/C 2. Then,
C2 = Y<i C1 ;C 2 = 670 pF.
c. To select CF, we use Tp = (0.3/(baud rate)] seconds.
rF = 0.3/ I 0,000 = 30 µsec. ; with
RF= 100 kn, CF= 300 pF.
7
4. Lock Range Selection To select C0 , let us start with the actual lock range:
If we assume a capture range of 80%,
Mc =6296Hz; therefore, our total capture range or ~fc is I 2,592 Hz. Our minimum value for C0 is {16/ I 2,592) µf or 0.00I3 µf.
5. Completed Circuit Example See Figure 5.
B. Design a 3 kilobaud modem to operate with low output jitter. The bandwidth available is 13 kHz.
For this modem, we can take the values from 2 for the 300 baud modem operating at I070 Hz and I270 Hz, multiply our baud rate and mark and space frequencies by IO, and divide all capacitor values on the table by IO. Resistor values should be left as they are.
c have: I 700 = I/(C0 x 20,000); 0 = 0.029 µf which is
approximately equal to 0.033 µf.
Calculating R1 using 600 Hz and 0.033 µf, we get R1 = 50.5 kn. We can use Rm = 47 kn and R1A = IO kn. For R2, we get IOI kn. Use R28 = 9I kn and R2A = 20kn. To determine R3 , use: I400Hz = I/R3C0 , which gives us R3 = 2 I .6 kn. Use R3B = 18 kn and R3A = 5 kn. R4 must generate a 300 Hz shift in frequency, the same as R2. Therefore set R4 equal to R2.
V+
SINEWAVE
l f ' u OUTPUT <>---'l'------=--j · 1
V+
R, 4.7K
1111--=---...+.-o ~~~~~~WAVE
fiJ:--=---DA_T-oAINPUT I t ,
~---r-
12 _ J
10K
-=- V+
R5 Optional Vpp Output Adjust
l RA Sine Shaping .
for,,,,. .S% THO
R8 Symmetry Ad1ust \
R, ~ I
RA 200f/. \ for,., 2.5% THO
C. Design a 2 channel multiplex FSK modulator to operate at the following pairs of mark and. space frequencies: 600 Hz and 900 Hz, and 1400and 1700 Hz. (Each of these channels could handle about 400 baud.)
For this task, we will use the XR-2207. The only real consideration here is that, if possible, we want to keep the following resistances all between IO kn and IOO kn: R 1 , R 1/R2, R3 and R3 /R4 . The ratio between the maximum and minimum frequencies is less than 3: 1, so we should have no trouble meeting this criterion. If we set our maximum frequency with an R of about 20 kn, we
DATA OUT 10K V+
Figure 5. Full Duplex FSK Modem Using XR-2206 and XR-2211. (See Table 2 for Component Values.)
ADJUSTMENT PROCEDURE
The only adjustments that are required with any of the circuits in this application note are those for frequency fine tuning. Although these adjustments are fairly simple and straightforward, there are a couple of recommendations that should be followed.
and VCO frequency may be anywhere within the lock range. There are several ways that f0 can be monitored:
I. Short pin 2 to pin I 0 and measure f0 at pin 3 with C0 disconnected;
The XR-2207:
Always adjust the lower frequency first with Rm or R3B and a low level on pin 9. Then with a high level on pin 9, adjust the high fre-
quency using R2B or R4B. The second adjustment affects only the high frequency, whereas the first adjustment affects both the low and the high frequencies.
The XR-2206: The upper and lower frequency adjustments are independent so the sequence is not important.
The XR-2211: With the input open-circuited, the loop phase detector output voltage is essentially undefined
2. Open R5 and monitor pin I3 or I4 with a high-impedance probe; or
3. Remove the resistor between pins 7 and 8 and find the input frequency at which the FSK output changes state.
Note: Do NOT adjust the center frequency of the XR-2211 by monitoring the timing capacitor frequency with everything connected and no input signal applied.
For further information regarding the use of the XR-2207, XR-2206 and XR-2211 refer to the individual product data sheets.
8
Application Note
AN-02
XR-C240 Monolithic PCM Repeater
INTRODUCTION
The XR-C240 is a monolithic repeater circuit for Pulse-Code Modulated (PCM) telephone systems. lt is designed to operate as a regenerative repeater at 1.544 Mega bits per second {Mbps) data rates on T-1 type PCM lines.
The XR-C240 monolithic IC is packaged in hermetic 16-pin DIP package and is designed to operate over a temperature range of -40°C to +85°C. It contains all the basic functional blocks of a regenerative repeater system including Automatic Line Build-out (ALBO) and equilization, and is insensitive to reflections caused by cable discontinuities.
Compared to conventional repeater designs using discrete components, the XR-C240 monolithic repeater lC offers greatly improved reliability and performance and provides significant savings in power consumption and system cost.
THE T-1 REPEATER SYSTEM:
The T-1 Repeater Line is designed to provide a transmission capability for 24 two-way voice frequency signals which are transmitted digitally using a Pulse-Code Modulation (PCM) technique. The system operates at a data rate of 1.544 Mbps, with bipolar data pulses. It can operate on either pulp- or polyethylene-insulated paired cable that is either pole mounted or buried. Operation is possible with a variety of wire gauges, provided that the total cable loss at 772kHz is less than 36db. Thus, the system can operate satisfactorily on nearly all paired cables which are used for voice frequency trunk circuits.
The transmission system is designed to operate with both directions of transmission within the same cable sheath. The system performance is limited primarily by near-end crosstalk produced by other systems operating within the same cable sheath. In order to insure that the probability of a bit error is less than l o-6, the maximum allowable repeater spacing, when used with 22-gauge pulp cable, is approximately 6000 feet.
The details of the T-1 type PCM systems are well covered in the literature listed in References 1 thru 5.
Figure 1 shows the block diagram of a bi-directional PCM repeater system consisting of two identical digital regenerator or repeater sections, one for each direction of transmission. These repeaters share a common power supply. The DC power is simplexed over the paired cable and is extracted at each repeater by means of a series zener diode regulator. The XR-C240 monolithic IC replaces about 90% of the electronic components and circuitry within the "digital repeater" sections of Figure 1. Thus, a bi-directional repeater system would require two XR-C240 IC's, one for each direction of inforination flow.
Figure 2 shows the functional block diagram of one of the digital repeater sections, along with the external zener regulator. The basic system architechture shown in the figure is the same as that utilized in the design of the XR-C240 monolithic IC.
SIGNAL FLOW -
11
11
~II
llC
~SIGNAL FLOW
Figure 1. Block Diagram of a Bi-directional Digital Repeater System
BALANCED REGEN EAATOR
BIPOLAR T2 OUTPUT
II
Figure 2. Block Diagram of a Digital PCM Repeater Section
9
In terms of the functional blocks shown in Figure 2, the basic operation of the repeater can be briefly explained as follows:
The bipolar signal, after traversing through a dispersive, noisy medium, is applied to a linear amplifier and automatic equalizer. It is the function of this circuit to provide the necessary amount of gain and phase equalization and, in addition, to band limit the signal in order to optimize the performance of the repeater for near-end crosstalk produced by other systems operating within the same cable sheath.
The output signals of the preamplifier which are balanced and of opposite phases are applied to the clock extraction circuit and also to the pulse regenerator. The signals applied to the clock extraction circuit are rectified and then applied to a high-Q resonant circuit. This resonant circuit extracts a 1.544 MHz frequency component from the applied signal. The extracted signal is first amplified and then used to control the time at which the output signals of the preamplifier are sampled and also to control the width of the regenerated pulse.
It is the function of the pulse regenerator to perform the sampling and threshold operations and to regenerate the
I
appropriate pulse. The regenerated pulse is in turn applied to a discrete switch which is used to drive the next section of the paired cable.
REFERENCES ON PCM REPEATERS:
1. Mayo, J. S., "A Bipolar Repeater for Pulse Code Signals," B.S.T.J., Vol. 41, January, 1962, pp. 25-97.
2. Aaron, M. R., "PCM Transmission in the Exchange Plant," B.S.T.J., Vol. 41, January, 1962, pp. 99-143.
3. Davis, C. G., "An Experimental Pulse Code Modulation System for Short-Haul Trunks," B.S.T.J., Vol.41,January, 1962, pp. 1-25.
4. Fultz, K. E. and Penick, D. B., "The T-1 Carrier System," B.S.T.J., Vol. 44, September, 1965, pp. 1405-1452.
5. Tarbox, R. A., "A Regenerative Repeater Utilizing Hybrid IC Technology," Proceedings of International Communications Conference, 1969, pp. 46-5 - 46-10.
OPERATION OF THE XR-C240
The XR-C240 combines all the functional blocks of a PCM repeater system in a single monolithic IC chip. The pin connections for each of the functional circuits within the repeater chip are shown in Figure 3, for a 16-pin dual-in-line (DIP) package.
The circuit is designed to operate with two positive supply
voltages, v++ and v+ which are nominally set to be 8.2V and
4.3V, respectively. Figure 4 gives a typical recommended power supply connection for the circuit.
The supply currents IA and Ia drawn from the two supply voltages applied to the chip are specified to be within the following limits:
ALBO OUTPUT
ALBO TERMINATION
V+·4.3V
LC TANK
GND
Figure 3. Package Diagram of XR-C240 Monolithic PCM Repeater
v++
+ 8.2V
+ 3.9V
V21 +
+
V22
i 10 1A
XR-C240
15
6
13
Figure 4. Recommended Supply Voltage Connection for XR-C240 (Note: See Figure 6 for Recommended Bypass Capacitors)
a. Current from 8.2V supply voltage, IA:
l.lmA ~IA~ 2.5mA
b. Current from 4.3V supply voltage, Ia:
6mA~IB~ llmA
The external components necessary for proper operation of the circuit are shown in Figure 5, in terms of the system block diagram. Note that all the blocks shown in Figure 6 are a part of the monolithic IC; and the numbered circuit terminals correspond to the IC package pins (see Figure 4).
Figure 6 shows a practical circuit connection for the XR-C240 in an actual PCM repeater application for 1.544 Mbps T-1 Repeater application. For simplification purposes, the lightening protection circuitry and the second repeater section are not shown in the figure.
10
15
3.51K
311
0.0226µF 3K
430
5.11K
I 0.1µF
-::- -::- 3.3µH
ALSO 556
o.1µFI
·set C1 to obtain resonant tank frequency of 1.544MHz
·c,
PEAK DETECTOR
FULL WAVE RECTIFIER
OATA THRESHOLD
GATE
1.544MHz
Figure-5. External Components Necessary for Circuit Operation
A1
A1
C7
R1
R4 0.0226
556
5.1
L2 3.3µH
Al
C5
R7
0.1
130
Ca 102pl
Al R3 1.1K
1.97K C11 102PI
A1
Rg
3K
Tl
Al
Ra 430
Ill
C12
R39
0.1
5.11K
Ra -=
3.9
T2
XR-C240
15 12
11
-=
C10
C3 160pl
33pl
L1
C4 47pl
R34 27.4K
+a.2V
3.57K
~-1~
C19
0.1
CR2
3.9V
4.3V
C14 6.a
a.2V
POWER TO REPEATER SECTION NO. 2
Figure 6. A Typical Circuit Connection for XR-C240 in 1.544 MHz T-1 Repeater System
11
INPUT
OUTPUT
C15 6.8
R2s
C17
300
0.1
DESCRIPTION OF CIRCUIT OPERATION:
This section gives a brief description of the internal circuitry contained within the XR-C240 monolithic IC.
The circuit diagram of the preamplifier section is shown in Figure 7. This section is designed as a two-stage differential amplifier with a broadband voltage gain of 52db. The differential outputs of the preamplifier (pins 4 and 5) are internally connected to the peak-detector, full-wave rectifier and the threshold detector sections of the XR-C240 as shown in Figure 8.
The peak-detector output (terminal B of Figure 8) is internally connected to the Automatic Line Build-out (ALBO) section of the circuit and controls the OC bias current through the ALBO diodes Q19 through Q20, as shown in Figure 9.
The full-wave rectifier output (output D of Figure 8) is internally connected to the clock-extractor section of the repeater and provides the excitation signal for the L-C tuned tank circuit (pin 14) of the injection locked oscillator. The thresholddetector outputs (G+ and G- of Figure 8) provide the differential logic drive to the data latches of the logic section of XR-C240.
INPUT { A> FROM PRE AMF A-
v· ~ 4.3"
.---.,.-----+---<11
G-
t---+-< 07
"··
"12
...---+--A-
GNO 13r-___.__ ___.__ ___.,___ _...J
"··
GND
Figure 8. Circuit Diagram of Threshold-Detector, Full-Wave Rectifier and Peak-Detector Sections
v+ =4.3V 7>---.--------.
PEAK DETECTOR INPUT
>---OB
Figure 7. Circuit Diagram of Preamplifier Section
Figure 9. Automatic Line Build-Out (ALBO) Section 12
:rhe clock-extractor section of XR-C240 is designed as an injection locked oscillator as shown in the circuit schematic of Figure 10. The excitation is applied to the emitter of Q23, through terminal D which is internally connected to the output of the threshold comparator. This signal in turn controls the current in the resonant L-C tank circuit connected to pin 14. The .sinusoidal waveform across the tank is then amplified and squared through the cascaded differential gain stages made up of Q31, Q32 and Q35, 036· The output swing of the second gain stage is "integrated" by the phase-shift capacitor, C1, externally connected to pins 11 and 12. (See timing diagrams of Figure 13.) The nominal value of this capacitor is in the 30 to 40pf range. The triangular waveform across pins 11 and 12 is at quadrature phase with the sinusoidal voltage swing across the L-C tank circuit. This waveform is then used to generate the "strobe" signal, Cp, and the clock pulse C<fJ, which is applied to the data latches of the logic section.
M ~~NK
The strobe and clock pulses out of the clock-regenerator section are applied to the output data latches shown in Figure 11. The two parallel output R-S flip-flops are driven by the differential inputs (G+ and G-) from the data comparator of Figure 8. The two sets of differential data signals, F1, F1 and F1, F2 are then applied to the output driver amplifier shown in Figure 12. The high-current outputs of the driver stage (pins 8 and 9) are connected to the center-tapped output transformer as shown in Figure 5. The voltage swing across the output is one diode drop (VBE) less than the supply voltage spread, i.e.:
Peak Output Swing= (V++) - (V+) - (VBE)"" 3.2V
The output stage is designed· to work into a nominal load impedance of 100 ohms, and can handle peak load currents of 30mA.
I ,, I r·------11-------1
.---------...---(i· v++~s.2v
INPUT FROM THRESHOLD DETECTOR
Figure 10. Circuit Diagram of Clock Extractor Section
c, v,
r-r----+---+-----.--.---{ lll v·
C·
G-
,...---.---~-----.--~---{II) v+> ~ 82V
lOUTPUTS TO
I
TRANSFORMER
PRIMARY
...
VB~ INTERNAL
BIAS >-t--+-t,,..---t------1'-C
Figure 11. Data Output Latches (Logic Section)
v,
(INTERNAL BIASI -I--+---+-~-------<
Figure 12. Output Driver Section
13
Figure 13 shows the typical timing sequence of the circuit waveforms. For illustration purposes, a "one-zero-one" input data pattern is assumed.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Power Dissipation
Derate above +25°C' Storage Temperature Range
+IOV 750mW 6mW/°C -65°C to +150°C
AVAILABLE TYPES
Part Number XR-C240
Package Ceramic
Operating Temperature -40°C to +85°C
INPUT SIGNAL
OSCILLATOR WAVEFORM (PIN 14)
INTEGRATED OSCILLATOR WAVEFORM (PIN 11 OR 12)
STROBE PULSE
c.
REGENERATED CLOCK PULSE
c,
REGENERATED BIPOLAR OUTPUT (PINS 8 ANO 9)
Figure 13. Typical Timing Waveforms for a 1 - 0 - 1
ELECTRICAL CHARACTERISTICS
Input Data Pattern
(Measured at 25°C with v++=8.2V, v+=4.3V, unless specified otherwise.)
CHARACTERISTICS
Supply Voltage: v++ v+
Supply Current: IA IB Total Current
Preamplifier Input Offset Voltage, Vos Open Loop Differential Gain, Ao Input Bias Current, IB Input Offset Current, Ios Input Impedance, Rin
Comparator Thresholds
Peak Detector (ALBO) Threshold Full-Wave Rectifier Threshold Data Threshold
Clock Extractor Section Tank Drive Impedance Tank Drive Current "Zero" Signal Current "One" Signal Current Recommended Tank Q Phase Shifter Offaet Voltage
Output Drive Section
Output Voltage Swing Low Output Voltage Output Leakage Current Output Pulse
Maximum Pulse Width Error Rise and ·Fall Times
LIMITS
MIN.
MAX.
7.79 4.085
8.61 4.515
1.1
2.5
6
11
7.1
13.5
15
50
54
4
2
50
±1.3 ±0.9 ±0.28
50
12 80 100 -18
±1.6 ±1.15 ±0.48
24 220 +18
3.0
0.65
0.95
50
±30 80
UNITS
v v
mA mA mA
mV db µA µA kS1
v v v
kS1
µA µA
mV
v v µA
nsec nsec
CONDITIONS
Measured at Pin 10 Measured at Pins 7 and 15 See Figure 4 Supply = 8.2V Supply= 4.3V
See Figure 8 Measured Differentially Across Pins 4 and 5
See Figure 10 At Pin 14
Voltage applied to Pins 7 and 14 to reduce differential voltage across Pins 11 and 12 to zero. See Figure 12 Voltage levels referenced to Pin 7
RL = 10on
Referenced to Pin 7, IL= 30mA See Figure 13
14
Application Note
AN-03
Active Filter Design with IC Op-Amps
INTRODUCTION
This application note is intended to familiarize the filter designer with the fundamentals of active filter design, using monolithic IC op amps. It presents a table of transfer functions and network equations for high-pass, low-pass, band-pass and band-reject filters. Several design examples are given to illustrate the respective merits and limitations of various filter configurations. Particular emphasis is given to applications of programmable quad operational amplifiers, such as the XR-4202, as an active filter element in FSK Modems.
FUNDAMENTALS OF ACTIVE FILTERS
The availability of low cost dual or quad operational amplifier IC's have made the operational amplifier based active filter techniques cost effective over conventional passive filters. The recent availibility of programmable quad operational amplifiers such as the XR-4202 or the XR-346 have provided the active filter designer with the flexibility to externally program gain-bandwidth product, supply current, input bias current, input offset current, input noise and the slew rate. The user, therefore, can trade off bandwidth for supply current or optimize the noise figure. Likewise, other amplifier characteristics can be programmed for a specific need.
Since the operational amplifier plays such a key role in the active filter, its characteristics are of prime importance. By using operational amplifiers as the basic gain stage of the active filter, problems previously encountered due to low input impedance, high output impedance and low gain are virtually eliminated. Operational amplifiers provide the required response for various filter types. Some of the more popular filters are multiple feedback, state variable, bi-quad and Sallen Key which can be used to obtain high pass, band pass and low pass filter functions (and which are capable of giving the designer all of the standard filter responses, i.e., Butterworth, Chebychev, Bessel, etc.)
Table 1 is intended to give the· designer a brief review of the basic transfer functions, and· network defining equations. It is noted that a family of curves exists for all cases except first order low pass and high pass. This is due to the presence of a, the damping coefficient.
Once the transfer function has been determined, the next step in filter design is to decide upon the desired response. As previously mentioned the damping of the filter determines it's characteristics near cut off. There are three basic types of responses which are depicted in Table 2 along with their
characteristics. In the case of the Butterworth and Bessel, the response has been fixed. However, for the Chebychev the a is chosen for the particular response desired. This is done by using a nomograph such as the one shown in Figure 1. To use a nomograph the information required is: Amax (maximum ripple in the passband), Amin (minimum attenuation in the stop band), and D 5 (ratio of the Amin bandwidth to the Amax bandwidth). These terms are illustrated in Figure 2. Once these terms are known the nomograph is used by locating Amax and drawing a straight line through Amin to the left hand side of the graph. From this point a horizontal line is drawn to the intersection of ns. The minimum order of the transfer function will be the number of the curve passing above this point. Once this is done the a and wo for each stage. is found by consulting the Chebychev network parameter tables for the desired passband ripple, and the number of poles. Such tables can be found in standard filter handbooks.
FILTER REALIZATIONS
There are numerous ways of realizing the transfer functions discussed. Each of these methods have their own relative merits. The configuration selected depends primarily on the specific application and the desired sensitivity parameters. Sensitivity parameters are a means of relating the resultant change in the transfer function due to an element change. Although these parameters are only directly applicable to an infinitesimal change they are easily used to evaluate performance for 1% changes, and many times are used for element changes up to 10%. Examples will be given later in this section that will help clarify this parameter.
The filter realizations presented here are to be used as a basic guide to help the designer to become more adept at designing filters. State-variable and multiple-feedback filters will be discussed and the relative merits of each will be given. It will also be shown that many of the commonly used filters are actually specific cases for the filters mentioned.
15
TABLE 1
~
H(s) = How~
S +WO
=[ J [H(jw)]
l6 Ho2wo
w2 + wo2
q, = Tan- 1 ~ WO
High Pass
H(s)=~ S +WO
=f l [H(jw)] Ho2 wo2 l6
lf.i2 + wo2J
Band Pass
H(s) = Ho a wos
s2 + awos + wo2
[H(jw)) = [
Ho2 a 2 wo2 w 2
Jl6
w4 + w 2wo2 (a2-2) + wo4
q, = !'. - Tan-1 ( 2Qw + ~)
2
WO
- Tan- 1 (2-Q-:;w;- - v~ 4Q ) - I
(H(jw)] 0
-20 00
¢
-45°
[H(jw)] O
-20 90°
¢
45°
[H(jw)] 0
-20
00
-900 .1
w
1 10
Wo
00 .1
1
w
10
Wo
.1
1
w
10 wo
Low Pass Second Order
H(s) = H_o_w_o_2_ __
s2 + awos + wo2
=f [H(jw)]
Ha2wo4
Jl6
Lw4 + w 2wo2(a 2 - 2) + woA
¢i=-Tan- 1 [_!_ 2~+~]
Q
WO
J - Tan- 1 [ l6 ~~ -V4-a2
High Pass Second Order
H(s) =
Hos2
s2 + awos + wo2
[H(jw)) = [
H2 4 o w
Jl6-
w 4 + w 2 wo2(a2 - 2) + wo4
[H2 ¢ =rr-Tan- 1
~ + V4-a2)]
[H2 -Tan- 1 ~ -v4=a')]
Band Reject
H(s) = ( s2 + wo2 )Ho
s2 + awos + wo2
]Yo [H(jw)] =
[
w4
Ho2 w4 + wo4 +w 2 wo(a2 -2)+wo4
J ¢i = '.'.__ Tan-I ( 2Qw + 4Q2 - I)
2
WO
- Tan-1 (2~: J4Q11)
[H(jw)]
-40 00
¢
-900
-180° .1
[H(jw)]
0 -40 180°
¢
900
[H(jw)] 0 -6
+900
¢
00
1
10
w
wo
oo
.1
w
1
10
wo
-90° .1
Definition of Terms
wo =Cut off frequency 2 nf0
a = Loop damping
s = a+ jw complex frequency we =Center frequency Wt =Lower cut off frequency
w2 =Upper cut off frequency Q = l / a =w-e- -
W2 -wt
</J =Phase [HUw)] = Magniture response
H(s) =Transfer function
w
10 WQ
16
Filter Type Bessel Butterworth Chebychev
TABLE 2
Q
Basic Features
Amp. Response
VJ
Best time dl'la) Smoothest phase rcspon~e
~
Ve.
Maximally tlat ;impl11udc response
l\
Cm Vary
Passband ripple Fast cutoff slope
l~
40
140
130
120
20
110
100
90 10
345678910
+
+
-1El
-
-
1-Eo
-
FIGURE 3
E-1
E0
-Yi Y3
£i(s)=Y5 (Y 1 +Y2 +Y3 +Y4)+Y3Y4
form of the characteristic equation is given in Table I. To transform E--1 in to the high-pass characteristic, then Y 1 , Y 3 , and Y4 become capacitors and Y2 and Y 5 resistors. (It should be obvious that a low-pass function could have been fabricated by letting Y 2 and Y 5 be capacitors, and similarly
a bandpass function could have been realized by making Y3
and Y4 capacitors.) The terms of the network function of the high-pass filter shown in Figure 4 are given in Table 3 along with their sensitivity parameters. The transfer function for Figure 4 is given by E--2.
0.01 0.005
0.001 0.0005
± 0.0001
0.00005
~
o...::::::__~L_---1~L_.Ll_j_LLJ
3 4 5678910 ll,
FIGURE I
fE -
FIGURE 2
Figure 3 illustrates a typical multiple-feedback connection with the non-inverting input grounded. To minimize offset this point should be returned to ground via a resistor whose value is equal to the impedance at the inverting input. The transfer function for this circuit is given by E-1. Each element represents a single resistor or capacitor. To realize the transfer function each admittance parameter is replaced by I /R for a resistor and sC' for a capacitor. An example will help to clarify this point. If the desired response is a high pass. the
FIGURE 4
E-2
2
E0
·(C, /C4 )s
Et (s) = s2 + s(l/Rs)(C, /C3C4 + l/C4 + l/C3) + l/R2RsC3(4
As can be seen from the sensitivity parameters. there is a high degree of circuit sensitivity due to the component tolerances. Due to the interaction of components the tuning of this circuit may be rather involved. However. with tight component tolerances. these circuits give the designer very predictable results. Due to the high input impedance and low output impedance. several of these stages may easily be cascaded to achieve a higher order function. What is desired is to have a lower sensitivity to component tolerances. The most commonly used filter for this purpose is the state-variable.
The state-variable synthesis approach is used in most present day Universal Active Filters (U.A.f.). With this method the actual nth order polynomial of the transfer function is simulated as it would be with an analog computer. When using the state-variable approach all three outputs (high-pass. low-pass and hand-pass) are all available simultaneously. The sensitivities with respect to component tolerances are
typically less than or equal to one. and the sensitivity of Q
17
Parameter
Defining Equation
TABLE 3
Sensitivity
Note: The sensitivity of Ho with This implies that if C 1 changes by I% Ho will also change by 1%. The defining equation for a sensitivity parameter is
Sx Y
xdY =--
Yctx
Wo
with respect to amplifier gain is nearly zero, if the amplifier · gain is high. Because of the high amplifier gain requirement
these filters tend to be limited to audio range. The cost of re-
ducing the circuit element sensitivities is the need to use (n + 2)
operational amplifiers to synthesize an nth order transfer function. For this reason, this type of configuration may not be cost effective in the synthesis of low Q high-pass and low-pass filters. Figure 5 shows a typical state-variable configuration whose characteristic equations are given by E-3, E-4, and E-5. It is noted that these equations all have the same denominators; and the numerator is determined by the point at which the output is taken. This form may also be used to simulate a band-reject function by summing the high-pass and lowpass outputs. The defining equations and sensitivity parameters are given in Table 4. It is noted here that the bi-quad is actually a slight variation of a second order state-variable.
FIGURE 5
E-4 EHP _
El- s2 +s(-1-) RsC1
E-5
MODEM FILTER
A typical application for an active filter is the input stage of a frequency demodulator. Any noise or spurious signals at this point would affect the overall quality of the output. A more specific example can be cited by considering the F. S. K. system shown in Figure 6. (Frequency shift keying is a means of transmitting digital information, primarily through telecommunications links.) This type of system is thoroughly covered in Exar Application Note, AN-01 and will only be briefly discussed here.
In this system, the digital data to be transmitted is used to key the XR-2206. The frequency shift keyed output of the XR-2206 is then sent through the hybrid and out on to the line. (The hybrid is used to obtain isolation between data transmitted and data received, and also may be used to amplify the received signal.) In full duplex operation this system must be able to receive and transmit simultaneously. Due to line losses, the received signal may range from -12 dBm to -48 dBm. The output level of the transmitter is typically -6 dBm (allowing for a 6 dB loss in the hybrid), due to line mismatch, the hybrid may only provide I0 dB of isolation to the filter. (Therefore. the levels at the input of the filter, assuming a gain of 6 dB from the line through the hybrid is -6 and
18
Output
Low Pass E-3
High Pass E-4
Band Pass E-5
Parameters Ho
Wo ex
Ho
Wo
"
Ho Wo Q= I/a
TABLE4
Defining Equation
I+ R,/R· I +R 1/R2
r [ R,R,RR:c,c,
I + R4/R 3 (R 3 R6 C2)
\6
-
I+ R2 /R 1 R4R5C1
I+ R4/R, I+ R1/R2
SAME AS LOW PASS
(1 + R4/R3) (R 3 R6 C2) \6 I + R2 /R 1 R4 R5 C1
R,
R;
SAME AS LOW PASS
(1 + R2 /R 1) (R4R5 C1) h I + R4/R 3 R 3 R6 C2
Sensitivity
SR, Ho= -SR, Ho= -1/(I + R2 /R 1 ) s Ho--s Ho - J..(_R,/R. )
R1 - R· - Ho I + R1 /R,
SR Wo 3
=
SR s Wo
=
SR Wo 6
=
Sc Wo I
=
Sc Wo 2
=
-SR 4 Wo -- 2 - !
SR4Q
=
-S
R1
"=
-
!+ 2
R,C,
R4/R 3 aw0 (1 +
R,/R 1 )
SR, " =-SR, " =I +R,I/R,
SR6 " = St-," 7 -SR 5 " =·-Sc,"= ~
SR, Ho= -SR 2 Ho= -1/(1 + R2 /R 1 )
SR, Ho-_-SR4 Ho-_HJ.o.(_l&+RL&,/R__, )
SR4 a
=-SR<>=-!+
R./R,
3
2 R5 C 1aw0 (1 +R,/R,)
SR,"=
-SR,
"
= I
--1+R,/R2
sR." =Sc,"= -sR," =-Sc,"= 1/2.
SR, Ho= -~Ho =-I
SR s O
"'
Sc O 1
=
-SR O 6
=
-Sc 2
O
=
!2_
SR 4 O
=
SR O 3
=
!2_
-
R4 /R 3 R,C, <>woO + R2 /R,)
sRO , --
-
sO
R1
-
-
I
+
RI ,
/R,
FSK MODULATOR XR-2206
LINE HYBRID
FSK DEMODULATOR
XR-2211
>----+--
BANDPASS FILTER
600 LINE TERM.
0 -1dB
FIGURE 6
-42 dBm for the desired signal and -16 dBm from the local oscillator.) This means that in a worst case situation, the input level of the received signal is -42 dBm with the level of the local oscillator 26 dB above this. For the XR-2211 to operate with a low bit error rate, the input should be 6 dB higher than the interfering signal. This implies that the stopband Amin from Figure 2 is 32 dB. The XR-2211 has an internal preamplifier with a dynamic range of greater than 60 dB, and requires a minimum input level of -38 dBm to cause limiting. If we choose a filter to have a passband ripple of 1 dB and an overall gain of 5 dB, the input conditions of the XR-2211 will be satisfied. The filters introduce a phase shift that is only linear for approximately 1/2 to 1/3 of the passband, therefore, a bandwidth of 400 Hz is used for the filter. The general shape of the filter is shown in Figure 7.
-32
1270 1925 Frequency, Hz
2325
2980
FIGURE 7
Note: The values used in this filter are based on a modem using an XR-2206 as the modulator and XR-2211 as the demodulator. If digital techniques are used, the filter parameters may be different due to the harmonics generated by digital synthesis of a sine wave and higher signal to noise requirements of the demodulator.
To find the minimum number of poles required for this response the nomograph in Figure 1 is used. The point falls between a 2 and 3 pole filter. The values of w0 + a are determined from the tables for a 3rd order chebychev response with 1 dB ripple.
19
l From tables Wo = .997098 a= .495609 Wo = .494171
complex pole - real pole.
The geometric center is w 0 = ../w3w2 or .JG[;
The
. filter
Oo
= Oo
= f3
f0
_
f2
=
../(1925)(2325) 2325 _ 1925
=
5.28892
Where
M = W1 = Wo = .G = fg
Wo W2 fo f1
M = 1.0955 f,=2317.6 f1 = 1931.l
for Section 3 the real pole is transformed into a complex pole pair.
0 3
_
-
200 ac.va=
10.7
The Oof each section of the filter is determined by Equation 6.
The 3 filter stages are now defined:
f, = 2317.6
f1 = 1931.1
f3=2115.56
01 = 21.49
02 = 21.49 03 = 10.7
O1 = 21.49 = 0 2 Section 2 is a reflection of section one about
f0 . The center frequencies are found by E- 7.
In this example the multiple-feedback approach is used since 3 pole pairs can be generated with 3 op-amps, 6 capacitors and 9 resistors; an equivalent filter could have been designed with the state-variable techniques, but this would have required 5 op-amps to realize. The actual filter is shown in Figure 8. All capacitor values are chosen to be .01 µf, 5% and all resistors are 1%. The values for this filter and a low band filter are
shown in Table 5.
TABLE 5
fo
Wo
Qo
R1
R1
R3
C1
C2
Ho
A
Originate B
c
1931.1 2317.6 2115.6
12.I 335K 14.562K 13.293K
21.49 21.49
10.7
88.6K 74K 40K
192
354K
.01
.01
2
160
295K
.01
.01
2
355
161K
.01
.01
2
1
2
Answer
A
1362.26
I0.115K
11.827
58.5K
421
234K
.01
.01
2
B
975.51
6129.3
11.827
96.5K
695
386K
.01
.01
2
c
1152.78
7.243K
5.832
40.3K
1219.S
161K
.01
.01
2
\
FIGURE 8 20
Figure 9 shows a circuit schematic for a complete "Originate or Answer" modem. The values for the XR-2206 are given in Table 6. For an originate modem the transmitting frequencies are 1070 Hz and 1270 Hz, the receiving frequencies are 2025 Hz and 2225 Hz, for a space and mark respectively.
The first op amp in Figure 9 is connected as an active hybrid which should supply a minimum of 10 dB isolation from transmit to receive, while adding 3 dB gain from the line to the receiver.
Goon
b... . _ _ - - - ' \ / \ A r - - - + - 1
510KS!
CF"'=-
1µ~
V+
L--------..J"'l DATA RECEIVED
'----------.....n CARRIER DETECT
DATA TO BE SENT
FIGURE 9
TABLE 6 Recommended Component Values for Typical FSK Bands Units: Frequency - Hz; Resistors - kD.; Capacitors - µF.
FSK Band
Baud
Rate
fL
fH R6A
Originate 1070 1270 10 Answer 2025 2225 10
XR-2206
R6B R7A ~B
18
10
20
16
10
18
Comoonent Values
cJ Rx Re RA
XR-2211
co
CA
c;, ~
.039 10 18 100 .039
.01 .005 .OS
.022 10 18 200 .022 .0047 .005 .05
21
Application Note
AN-04
XR-C277 Low-Voltage PCM Repeater IC
INTRODUCTION
The XR-C277 is a monolithic repeater circuit for Pulse-Code Modulated (PCM) telephone systems. It is designed to operate as a regenerative repeater at 1.544 Mega bits per second (Mbps) data rates on T-1 type PCM lines. It is packaged in a hermetic 16-pin CERDIP package and is designed to operate over a temperature range of -40° C to +85° C. It contains all the basic functional blocks of a regenerative repeater system including Automatic Line Build-Out (ALBO) and equalization, and is insensitive to reflections caused by cable discontinuities.
The key feature of the XR-C277 is its ability to operate with low supply voltages (6.3 volts and 4.4 volts) with a supply current of less than 13 mA. Compared to conventional repeater designs using discrete components, the XR-C277 monolithic repeater IC offers greatly improved reliability and performance and provides significant savings in power consumption and system cost.
FUNDAMENTALS OF PCM REPEATERS
Figure 1 shows the block diagram of a bi-directional PCM repeater system consisting of two identical digital regenerator or repeater sections, one for each direction of transmission. These repeaters share a common power supply.1The DC power is simplexed over the paired cable and is extracted at each repeater by means of a series zener diode regulator. The XR-C277 monolithic IC replaces about 90% of the. electronic .::omponents and circuitry within the "digital repeater" sections
of Figure 1. Thus, a bi-directional repeater system would require two XR-C277 IC's, one for each direction of information flow.
Figure 2 shows the functional block diagram of one of the digital repeater sections, along with the external zener regulator. The basic system architecture shown in the figure is the same as that utilized in the design of the XR-C277 monolithic IC.
SIGNAL FLOW _____,...
DIGITAL
REPEATER
11
+6.3V +4.4V
II
311
+6.3V +4.4V
DIGITAL REPEATER
. . , _ S I G N A L FLOW
llL
Figure 1. Block Diagram of a Bi-Directional Digital Repeater System
BIPOLAR INPUT T1
II
.,
BIPOLAR T2 OUTPUT
~·2>---L_J--L---'T" 11
PEAK DETECTOR
6.3V
Figure 2. Functional Block Diagram of a Digital PCM Repeater System
22
In tenns of the functional blocks shown in Figure 2, the basic operation of the repeater can be briefly explained as follows:
The bipolar signal, after traversing through a dispersive, noisy medium, is applied to a linear amplifier and automatic equalizer. It is the function of this circuit to provide the necessary amount of gain and phase equalization and, in addition, to band limit the signal in order to optimize the perfonnance of the repeater for near-end crosstalk produced by other systems operating within the same cable sheath.
The output signals of the preamplifier which are balanced and of opposite phases are applied to the clock extraction circuit and also to the pulse regenerator. The signals applied to the clock extraction circuit are rectified and then applied to a high-Q resonant circuit. This resonant circuit extracts a 1.544 MHz frequency component from the applied signal. The extracted signal is first amplified and then used to control the time at which the output signals of the preamplifier are sampled and also to control the width of the regenerated pulse.
It is the function of the pulse regenerator to perfonn the sampling and threshold operations and to regenerate the appropriate pulse. The regenerated pulse is in turn applied to a discrete output transformer which is used to drive the next section of the paired cable.
Additional References on PCM Repeaters:
1.. Mayo, J. S., "A Bipolar Repeater for Pulse Code Signals," B.S.T.J., Vol. 41, January, 1962, pp. 25-97.
2. Aaron, M. R., "PCM Transmission in the Exchange Plant," B.S.T.J., Vol. 41, January, 1962, pp. 99-143.
3. Davis, C. G., "An Experimental Pulse Code Modulation System for Short-Haul Trunks," B.S.T.J., Vol. 41, January, 1962, pp. 1-25.
4. Fultz, K. E. and Penick, D. B., "The T-1 Carrier System," B.S.T.J., Vol. 44, September, 1965, pp. 1405-1452.
5. Tarbox, R.A., "A Regenerative Repeater Utilizing Hybrid IC Technology," Proceedings of International Communications Conference, 1969, pp. 46-5 - 46-10.
OPERATION OF THE XR-C277
The XR-C277 combines all the functional blocks of a PCM repeater system in a single monolithic IC chip. The pin connections for each of the functional circuits within the repeater chip are shown in Figure 3, for a 16-pin dual-in-line package.
The circuit is designed to operate with two positive supply
voltages, v++ and v+ which are nominally set to be 6.3V and
4.4V, respectively. Figure 4 gives the recommended power supply connection for the circuit.
The supply currents IA and 18 drawn from the two supply voltages applied to the chip are specified to be within the following limits:
a. Current from 6.3V supply voltage, IA:
2.5 mA,.;;;; IA,.;;;; 4.0 mA
ALBO OUTPUT
il PREAMP INPUTS
il PREAMP
OUTPUTS
ANALOG GROUND
DIGIT AL GROUND (+I DRIVER OUTPUT
Figure 3. Package Diagram of XR-C277 Monolithic PCM Repeater
V++
+ 6.3V
10 XR-C277
Figure 4. Recommended Supply Voltage Connection for XR-C277 (Note: See Figure 6 for Recommended Bypass Capacitors)
b. Current from 4.4V supply voltage, le:
7 mA ..;;re ,.;;;;9 mA
The external components necessary for proper operation of the circuit are shown in Figure 5, in terms of the system block diagram. Note that all the blocks shown in Figure 5 are a part of the monolithic IC; and the numbered circuit terminals correspond to the IC package pins (see Figure 3).
Figure 6 shows a practical circuit connection for the XR-C277 in an actual PCM repeater application for 1.544 Mbps T-1 Repeater application. For simplification purposes, the lightning protection circuitry and the second repeater section are not shown in the figure.
23
--------------------------------------------t15 V+·4.4V
3.5K
INPUT
811
5.1K
PEAK DETECTOR
FULL WAVE RECTIFIER
DATA THRSSHOLD
GATE
556
1.544MHz
Figure 5. External Components Necessary for Circuit Operation in 1.544 MHz T-1 Repeater
*Set C1 to obt1in reson1nt tlnk frequency of 1.544 MHz
+ XR-C277
+ 4.4V
1 6.BµF
Figure 6. Typical Circuit Connection of XR-C227 in 1.544 MHz T-1 Repeater System. (Note: Set Land C to form a high Q tank
resonant at 1.544 MHz. It is recommended that Q < 100, and C:::::: pf for most applications).
24
DESCRIPTION OF CIRCUIT OPERATION
Preamplifier Section (Fig. 7):
The circuit diagram of the preamplifier section is shown in Figure 7. This section is designed as a two-stage differential amplifier with a broadband differential voltage gain of 52 db. The differential outputs of the preamplifier (pins 4 and 5) are internally connected to the peak-detector, full-wave rectifier and the data threshold detector sections of the XR-C277.
Automatic Line Build-Out (ALBO) Section (Fig. 8):
The ALBO function is achieved by controlling the dynamic impedance of ALBO diodes (Q21 and Q22). The current whic sets this dynamic impedance is supplied through Q21 and is controlled by the peak-detector output level applied to base of Q23.
Data-Threshold Detector; Full-Wave Rectifier and Peak Detector Sections (Figure 9):
The level detector and peak rectifier sections of the XR-C277 are made up of two sets of gain stages which are driven differentially with the (A+) and (A-) outputs of the preamplifier section. The outputs of the data threshold comparators, o+ and D- activate the data latches shown in Figure 11.
The peak-detector output (terminal B of Figure 9) is internally connected to the Automatic Line Build-Out (ALBO) section of the circuit and controls the DC bias current through the ALBO diodes Q21 through Q22, as shown in Figure 8.
The full-wave rectifier output is internally connected to the clock-extractor section of the repeater and provides the excitation signal for the L-C tuned tank circuit (pin 14) of the injection locked oscillator. The detection thresholds of the comparators are set by the resistor chains (R45, R47, R51, Rss) and (R46, R4g, R52, R56)· The resistor ratios are chosen such that the data threshold is 50% of the ALBO threshold; and the clock extractor threshold is 73% of the ALBO threshold.
R33 R36 R37
V+ = 4.4V 15
031
032
A+
A-
Ve= INTERNAL BIAS
Vt - 4.4V
PEAK DETECTOR INPUT
"1----<l B
Figure 8. Automatic Line Build-Out (ALBO) Section
FROM
PREAMP
OUTPUT
V+
~V+
A-
A+
A44
O+}TODATA - - - - - D - LATCHES
..--t---t--+----,
R46
R48
-=-
~~
ii: ...
~_.~u .:.:.ia":'
-=-
,----,,---t--t-----:-~~--11------a TO ALBO
....a0u.......:.
0
..<"..(
R56
6 '---~~--------4>------4>----0GNO
GNO
Figure 7. Circuit Diagram of Preamplifier Section
Figure 9. Data-Threshold Detector, Full-Wave Rectifier and the Peak Detector Sections of XR-C277
25
Clock Extractor Section (Figure JO):
The clock-extractor section of XR-C277 is designed as an injection locked oscillator as shown in the circuit schematic of Figure 10. The excitation is applied to the emitterofQrn,from the output of the full-wave rectifier. This signal in turn controls the current in the resonant L-C tank circuit connected to pin 14. The sinusoidal waveform across the tank is then amplified and squared through two cascaded differential gain stages made up transistors Q3 through Q9. The output swing of the second gain stage is "integrated" by the phase-shift capacitor, CI· .externally connected to pins 11 and 12. (See timing diagrams of Figure 13 .) The nominal value of this capacitor is in the 30 to 40 pf range. The triangular waveform across pins 11 and 12 is at quadrature phase with the sinusoidal voltage swing across the L-C tank circuit. This waveform is then used to generate the "strobe" signal, CP, and the clock pulse Cl/>, which are applied to the data latches of the logic section.
Data-Latch and Output Driver Sections (Figures 11and12):
The data-latch section consists of two parallel flip-flops,
driven by the (D-t) and (D-) inputs from the data-threshold detector. When the D+ input is at a "low" state, the sampling or strobe pulse, Cp. is steered through Q 4 7A and sets flip-
o- flop I, on the leading edge of Cp. Conversely, when input
is at a "low" state, the sampling pulse is steered through 0478 to set flip-flop 2. Each flip-flop section is then reset at the trailing ed_ge of the clo£_k pulse input, C <P· The flip-flop outputs, (Fl· FI) and (F 2· F 2) are then used to drive the output drivers. This logic arrangement results in .an output pulse width which is the same as the extracted clock pulse width (see timing diagram of Figure 13).
The outputs of the two data latches drive the two output driver stages shown in Figure 12. The high-current outputs of the driver stage (pins 8 and 9) are connected to the center-tapped output transformer as shown in Figure 5. The voltage swing across the output is one diode drop (YBE) less than the supply voltage at pin I 0. The output stages are designed to work into a nominal load impedance of 100 ohms, and can handle peak load currents of 30 mA .
........
12 --! 1-- "
c,
FULL "W"'"A"V"'"E'
RECTIFIER
Figure 10. Circuit Diagram of Clock Extractor Section
.,. ... ""
·,
,,
Figure 11. Data-Latch Section of XR-C277
Figure 12. Output-Driver Section 26
Figure 13 shows the typical timing sequence of the circuit waveforms. For illustration purposes, a "one-zero-one" input data pattern is assumed.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Power Dissipation
Derate above +25°C Storage Temperature Range
+lOV 750mW 6 mW/°C -65°C to + l 50°C
AVAI LAB LE TYPES
Part Number XR-C277
Package CERDIP
Operating Temperature -40°C to +85°C
INPUT SIGNAL
_ _,_,l/-i-4--'"-l-.._...._.........,_........_--t OWSACVIELFLOARTMOR
(PIN 14)
INTEGRATED
:./'-~~Q!mF~i/C-~~_,.-f ~~~~~~~A
IPIN 11 OR 12)
_ ___,_.__.._'-""_--'_~---I
REGENERATED CLOCK PULSE
c,
. . REGENERATED
-~~b-- ~:!::11-----1 ~~t-G'," {PINS 8 AND 9)
Figure 13. Typical Timing Waveforms for a 1 - 0 - 1
ELECTRICAL CHARACTERISTICS
Input Data Pattern
(+25°C, V++ = 6.3V ±5%, V+ = 4.4V ±5%, unless specified otherwise.)
PARAMETER
Supply Current IA Is
Total Current
Preamplifier Input Offset Voltage Input Bias Current Voltage Gain
Preamp Output Swing High Swing Low Swing
Output DC Level
ALBO Section ALBO "Off" Voltage ALBO "On" Voltage ALBO "On" Voltage Aj.,BO Threshold
Differential Threshold
ALBO "On" Impedance ALBO "Off" Impedance
Comparator Thresholds Clock Threshold Data Threshold
Clock Extractor Oscillator Current Tank Drive Impedance Recommended OSC. Q !injection/Io SC.
MIN.
8
44 3.4S 1.2S 2.47
0.6 1.2 l.3S -7S
20 68 47 10 100 6.0
Output Driver Low Output Voltage
Output "Off" Current Output Pulse
Maximum Pulse Width Error Rise Time Full Time
0.6S
LIMITS
TYP.
MAX.
3.S 7.S 11
1. s
0.3 48
3.6 1.4 2.SS
10 0.87
l.S I.SO
s
50
73
so
14
so
7
13
IS 4
SI 3.7S I.SS 2.72
7S I. I 2.1 l.6S +7S
10
78 S3
20
7.S
0.7S
s
0.9S 100
±30 80 80
UNITS
mA mA mA
mV µA dB
v v v
mV
v v v
mV
n
k.11
% %
µA k.11
v
µA
n sec n sec n sec
CONDITIONS
See Figure 4 Measured at Pin I 0 Measured at Pin I S
Oc + Is)
See Figure 7 Measured at Pins 2 and 3 Measured at Pins 2 and 3 Single-ended gain Measured at Pins 4 and S Maximum voltage swing Minimum voltage swing
See Figure 8 Measured from Pin I and Pin 16 to ground Measured at Pin I Measured at Pin 16 Measured differentially across Pins 4 and S Threshold difference for polarity reversal at Pins 4 and S Measured at Pin I Measured at Pin I
See Figure 9
%of ALBO threshold %of ALBO threshold
See Figure I 0
Ratio of current in Q 1B to current in 01A See Figure 12 Measured at Pins 8 and 9, IL= lS mA V0 ut=20V See Figure 1 3
27
Application Note
Tri-State FSK Modem Design Using XR-2207 And XR-2211
AN-05
INTRODUCTION
This application note ,describes the design principle and the operation of "tri-state" frequency-shift keyed (FSK) Modems for industrial process control systems. Compared to conventional "bi-state" Modems which utilize only the mark ancl space frequencies, the tri-state Modems utilize a third frequency, called the "carrier signal", for additional command and control functions. This carriercontrol feature allows each Modem system connected to a central processor (CPU) to be interrogated or activated, one at a time, without interference from the other Modem transmitters or receivers within the same system.
The design and operation of conventional bi-state FSK Modems using the XR-2206 modulator and the XR-2211 demodulator are covered in Exar's Application Note AN-01. This application note extends these basic concepts to the design of FSK modulators or demodulators with tri-state operation capability.
FUNDAMENTALS OF TRI-STATE OPERATION
In a wide variety of industrial process control applications, it is necessary to have a number of separate sensors and controllers activated by a centraliz~d computer or processing unit (CPU). This can be achieved by operating a number of separate FSK modulator/demodulator (Modem) stations over a common set of telephone lines and address to them, one at a time, from the CPU. The simplified block diagram of such a process control system is shown in Figure 1. In many cases, such a process controlled system also makes use of the "distributedintelligence" concept by employing a separate data acquisition system at each control station. Such an intelligent data
acquisition system is normally made up of a microprocessor along with its A/D and D/A converter circuitry which interface with the sensors and the control machinery; and an FSK Modem which interfaces with the telephone wires going back to the central command unit, the CPU.
In such a complex process control system, the FSK Modem stations play a crucial role in interfacing the distributed control stations with the CPU. The Modem arrays are selectively "interrogated" by the CPU, one at a time, by operating them under so-called "carrier-control" mode, i.e., they are addressed or enabled only when a specific carrier-tone is sent out from the CPU.
VALVE
VALVE MOTOR
VALVE
MICRO PROCESSOR
MICRO PROCESSOR
MICRO PROCESSOR
XR 2211 RECEIVER
f1
XR 2207
XR 2211 RECEIVER
!2
CENTRAL PROCESSING UNIT (CPU)
DATA IN
CHANNEL SELECT DATA OUT
XR 2207
XR 2211
.J ... CARRIER
rn_A_Ns_M_IT.T.E...R......,..,."'-C-Elv_'_"...
CONTROL
fN
PHONE LINE OR DEDICATED LINE
XR 2211 FSK RECEIVER
XR 2207 FSK TRANSMITTER
Figure 1. Simplified Block Diagram of a Complex Process Control System with multiple FSK Modems.
28
In conventional operation of FSK Modems, one operates them in their "bi-state" mode, i.e., the information to be transmitted or received is available in two states, corresponding to either a mark or a space frequency. In a complex process control system, such as the one shown in Figure I, the versatility of the system can be greatly enhanced by operating the FSK modulator and the demodulator in a "tri-state" mode where the information to be transmitted or received is available in three states, i.e., a "mark" or a "space" frequency, or a "carrier" signal, which is normally a tone having a frequency half-way between the mark and space frequencies.
Figure 2 shows a detailed block diagram of a complete tristate FSK Modem system. The system is made up of five blocks:
(A) FSK transmitter or encoder which converts the input data or logic signals into transmitted "mark", "space" and "carrier" tones.
(B) FSK receiver or decoder which converts the frequency signals sent over the telephone lines into binary logic signals.
(C) Transmitter band-pass filter which band-limits the frequency output of the transmitter to the allocated transmitter bandwidth.
(D) Receiver band-pass filter which limits the incoming signals to those frequencies which fall within the allocated receiver bandwidth.
(E) A "line hybrid", or a 4-wire to 2-wire transformer, which isolates or de-couples the transmitter output from the receiver input.
The first 2 blocks, i.e., the FSK transmitter and the receiver, are the essential part of the Modem system. The remaining three blocks, namely the active filters and the line-hybrid are support circuits, depending on the frequency-band requirements or the necessary telephone line interconnections. Detailed descriptions and design examples for these active filters are given in Exar's Application Note AN-03.
The tri-state Modem is designed to operate in two separate frequency bands: A "transmit-band" for the transmitted data, and a "receive-band" for the incoming frequencies. In certain operating modes, such as the half-duplex operation, these frequency bands may be one and the same. In its most general case, the frequency information associated with the tri-state Modem system of Figure 2, is concentrated in three discrete frequencies in each of the transmit- and receive-bands. These are:
Transmit-Band (transmitter output):
fn = Transmitter "mark" frequency
fT2 =Transmitter "space" frequency
fTO = Transmitter "carrier" or "center" frequency
CARRIER CONTROL
l
DATA
IAI
INPUT
H TRI-STATE
TRANSMITTER (XR-2206)
. - EN ABLE/DISABLE
co NTROL
*
ACTIVE FILTER
IBI
t--i
'-I
rl
*
LINE
- HYBRID t - - -
- IEI
'----I
S L DATA OUTPUT
TRI-STATE RECEIVER IXR-21111
ICI
I--
*
ACTIVE
Fll TEA I - -
IOI
~-----J
OPTION AL
DUAL/MODE MONITOR
OUTPUT s
00- --------2
*SEE EXAR APP NOTE AN 03 FOR ACTIVE Fil TEA DESIGN
Figure 2. Block Diagram of a Tri-State FSK Modem System.
Receive-Band (receiver input):
fRl =Receiver "mark" frequency
fR2 =Receiver "space" frequency
fRQ = Receiver "carrier" or "center" frequency
Normally the "mark" and "space" frequencies are chosen to be near the opposite edges of the receive- or transmit-band, and the "carrier" frequency is chosen to be at the center of the corresponding band.
When activated by the enable/disable control, the tri-state transmitter generates either the FSK mark/space frequencies (i.e., frequencies fn and fT2) or the carrier frequency, fTO· The carrier frequency is activated by the "carrier control" input, and can over-ride the input data.
The tri-state receiver provides two outputs: A binary data output, when activated by the input mark/space frequencies (i.e., fRI and fR2), and a logic signal to control or enable the transmitter, when the receive-carrier frequency, fRQ, is present. As an option, it may have a dual-mode operation capability which can provide serial data outputs for half-bandwidth deviations of the input signal, i.e., for FSK signals comprised of centerto-mark or center-to-space frequency shifts. The data outputs corresponding to this mode of operation are shown as outputs D1 and D2 of Figure 2.
29
MODES OF OPERATION
The generalized tri-state Modem system of Figure 2 can operate in a multiplicity of modes. Some of these are outlined below:
Answerback Under CPU Control: The Modem will be in a stand-by mode, with the transmitter disabled, and with the receiver in a stand-by condition with its data output disabled. It will be activated only when an "interrogate" tone at the receiver center frequency, fRQ, is transmitted by the control Modem unit associated with the CPU (see Figure 1). This tone is detected by the receiver; it activates the transmitter via its enable/disable control and instructs the local microprocessor to transmit its status information, via the local transmitter. This data is transmitted as an FSK signal made up of the transmit mark and space frequencies, fn and fT2· When the information transmission is complete, or when the "interrogate" tone is discontinued, the entire Modem system again reverts back to its stand-by mode.
Receive Under CPU Control: In this mode of operation, the transmitter remains disabled, the receiver is at its stand-by mode with its data output disabled. When the FSK data is sent by the CPU Modem transmitter, at mark/space frequencies of fR1 and fR2, the data output is enabled and the decoded binary data is fed into the local microprocessor. Since the "center" receive-frequency, fRO is not transmitted, the transmitter remains disabled.
Priority-Transmit Request: In an "emergency" situation, the local transmitter can be activated, by its carrier-control input, which causes it to transmit a tone, fTo, at its center frequency. When this tone is received by the CPU, it will be treated as a priority-request to transmit information; and the CPU will immediately "interrogate" the corresponding local Modem by sending out its address tone, at frequency fRO·
Dual-Channel Receive: As an option, the receiver can provide serial data outputs, through separate terminals D1 and D2 of
Figure 2, for half-bandwidth deviations of the input FSK signal. In this mode, the input data will be in the form of center-to-mark frequency shifts for one channel, and centerto-space shifts for the other. This mode of operation allows two separate sets of data or control instructions to be transmitted within the same channel bandwidth, provided that only one of these channels is used at any one time.
Dual-Channel Transmit: As an option, the transmitter can also transmit two separate channels, using half-bandwidth deviations of the transmit signal. In this case, the outgoing data will be encoded with center-to-mark transitions of the transmitter frequency in one of the channels; and with the center-to-space transitions in the other. However, similar to the case of the receiver, only one or the other, and not both, of these halfbandwidth channels can be "on" at a given time.
XR-2207 AS A TRI-STATE FSK TRANSMITTER
The XR-2207 is a monolithic voltage-controlled oscillator (VCO) circuit with excellent temperature stability. It provides simultaneous triangle and square wave outputs and can be keyed to any one of four pre-programmed frequencies, by means of external logic signals. These four discrete frequencies are pre-programmed by the choice of four external timing resistors.
Figure 3 shows a functional block diagram of the XR-2207 monolithic FSK generator chip. The circuit is comprised of four functional blocks: a variable-frequency oscillator which generates the basic periodic waveforms; four current switches actuated by binary keying inputs; and buffer amplifiers for both the triangle and square wave outputs. The internal current switches transfer the oscillator current to any of four external timing resistors to produce four discrete frequencies which are selected according to the binary logic levels at the keying terminals.
The frequency of oscillation is set by an external timing capacitor, and by the combination, of one or more, of the external
10
TIMING
f-- D---fo---1
CAPACITORT__ , >---+---I
BINARY U---+--I
KEYING
INPUTS <>---+--1
BIAS 11
TRIANGLE ~---t-<J WAVE
OUTPUT SQUARE
TIMING RESISTORS
4 56 7
GROUND
-VEE
Figure 3. Functional Diagram of XR-2207 Monolithic FSK Generator.
Logic Level Active Timing Resistor Output Frequency
Pin 8 Pin 9
L
L
L
H
H
L
H
H
Pin 6 Pins 6 and 7
Pin 5 Pins 4 and 5
-ICoR1
-I- + -I CoR1 CoR2
-I-
CoR3
-I- + -I CoR3 CoR4
TABLE 1. Output Frequency of the XR-2207 as a function of the Keying Logic.
(*Frequency in Hz, R in Ohms and C in Farads.)
30
~12V
Q_lµF
I
=
5 lK
"'4.7K
MJN... l - - - - - - - + - - - 1 1 - - - + - - - - - - - - - - - - 0
FSK
OUTPUT ~---<>-~~~~~~~~~---oJU1JL
~------1--~
ENABLE/DISABLE
1----+----~'1 CARRIER CONTROL
Figure 4. Tri-State FSK Transmitter using the XR-2207.
timing resistors, R 1 through R4.. The keying terminals switch
these external resistors in and out of the circuit and thus, control the operating frequency. Table 1 shows the four discrete frequencies which can be obtained as a function of four logic states at pins 8 and 9. It should be noted that the frequency is inversely proportional to the timing resistor connected to the activated timing pin. Thus, for example, if only one of the timing pins, say pin 5, is activated, yet its associated resistor, R3 is left open-circuited (i.e., R3 = 00) the oscillator will be keyed "off" since this corresponds to a "zero-frequency" state.
Figure 4 shows the recommended circuit connection of the XR-2207 for its operation as a tri-state FSK transmitter. The
three resistors, Ri, R1 and R4 are used to set the three dis-
crete frequencies to be transmitted in accordance with the frequency expressions given in Table 1, where:
It should be noted that pin 5 is left open circuited (i.e., R3 = 00). This allows the circuit to be keyed "off", or disabled, by applying a "high" logic state to pin 8 and a "low" logic state to pin 9 (see Table 1).
The functions of the three control terminals can be described as follows:
A. FSK Data Input: The serial binary data is applied to this terminal. With the carrier control at "low" and Enable/Disable control at "high" state, the binary data causes the transmitter to generate the mark and space frequencies, fn and fT2·
B. Enable/Disable Control: When this input is at "low" state, the transmitter is disabled.
C. Carrier-Control: When this terminal is at "high" state, the transmitter generates a continuous tone at frequency fTO·
With the external logic circuitry as shown in Figure 4, CarrierControl can over-ride both the Enable/Disable or the FSK data inputs. A detailed truth-table of the circuit outputs is given in Table 2, for various states of the three control inputs.
XR-2211 AS A TRI-STATE RECEIVER
The XR-2211 is a monolithic FSK demodulator which operates on the phase-locked loop principle. In addition to the basic PLL system, the monolithic chip also contains a quadrature-detector circuit which produces a logic signal when a carrier signal, or tone, is present within the capture range of the PLL. A simplified functional block diagram of the circuit is shown in Figure 5.
Basic Bi-State Operation: The basic operation of the XR-2211, in conventional bi-state Modems, is described in detail in
CONTROL INPUT STATES
AB c
L L L H L L L H L H H L L L H L H H H H H
TRANS-
LEVEL LEVEL MITTER
AT AT OUTPUT PIN 9 PIN 9 FREQUENCY
L
H
OFF
L
H
OFF
L
L
fn
H
L
fT.2.
H
H
fro
H
H
fro
H
H
fTQ
TRANSMITTER OPERATING MODE TRANSMITTER OFF TRANSMIT DATA TRANSMIT CARRIER ONLY
TABLE 2. Tri-State Transmitter Operating Modes as a function of Control Inputs.
31
FSK DATA OUTPUT
REF. VOLTAGE OUTPUT 10
LOCK DETECT OUTPUTS Q
Figure S. Functional Block Diagram of XR-2211 FSK and Tone Detector. Exar's Application Note AN-01. It will be briefly reviewed below:
The basic circuit connection for the XR-2211 for bi-state FSK detection is shown in Figure 6. The center frequency is determined by fo = (1/C1 R.4-) Hz, where capacitance is in farads and resistance is in ohms. fo should be calculated to fall midway between the mark and space frequencies.
The tracking range (±At) is the range of frequencies over which the phase-locked loop can retain lock with a swept input signal:This range is determined by the formula:
Af= (R.4-fo/Rs) Hz.
Af should be made equal to, or slightly less than, the difference between the mark and space frequencies. For optimum
stability the recommended range of values for R4 is between
IO kn and 100 kn.
+12V
1µF .I.
FSK SIGNAL n---+--------~ INPUT
10k 10k
+12V
XR-2211
510KH
'---"./\A~~---<l DATA OUTPUT Q LOCK DETECT OUTPUT Q LOCK-DETECT OUTPUT
I c,
Figure 6. XR-2211 as a Bi-State Receiver with Tone-Detection Capability.
The capture range (±Afc) is the range of frequencies over which the phase-locked loop can acquire lock. It is always less than the tracking range. The capture range is limited by C2, which, in conjunction with Rs, forms the loop filter time constant. In most Modem applications, Afc is chosen to be ~ 80% to 95% of the tracking range, Af.
The bi-state FSK data filter, made up of RF and CF removes the jitter from the demodulated FSK signal. Similarly, the lock-detect filter capacitor (Cn) removes chatter from the lock-detect output. With Rn= 5IO kn, the minimum value of Cn can be determined by: Cn (µf) ~ 16/capture range in Hz. The XR-2211 has three NPN open collector outputs, each of which is capable of sinking up to 5 mA. Pin 7 is the FSK data output, pin 5 is the Q lock-detect output, which goes low
when a carrier is detected, and pin 6 is the Qlock-detect out-
put, which goes high when lock is detected. If pins 6 and 7 are
wired together, the output signal from these terminals will provide data when FSK is applied and will be "low" when no carrier is present.
o, o,
1/2 of XR-4558
DATA OUTPUT
fro DETECTOR OUTPUT (JRANSMtTTER ENABLE/DISABLE)
I
Ry
Figure 7. Circuit Connection for Operating XR-2211 as a Tri-State FSK Receiver
200pF 1/2of XR-4558
32
Tri-State Operation: The XR-2211 FSK demodulator circuit can be made to operate as a tri-state receiver (see Block B of Figure 2) using the circuit configuration shown in Figure 7. With reference to the Figure, the basic operation of the circuit can be described as follows: The basic FSK decoding function, i.e., converting the incoming "mark" and "space" signals at frequencies fRI and fR2, is performed in the same manner as in the bi-state case and the resulting output is available at pin 7 of XR-2211. Pin 7 is connected to the tone-detect output, and then gated by the complement of the carrier-detect output. Thus, the "Data Output" terminal will be enabled only when the mark and space frequencies are present, but not when the receive-carrier, fRQ, is present.
The external voltage comparators shown in Figure 7 are added to the circuit to distinguish PLL output voltage levels corresponding to various input frequencies. Their function can be understood by referring to Figure 8, which shows the XR-2211 frequency-to-voltage transfer characteristics, at pin 11. The voltage levels and polarities shown are relative to the XR-2211 internal reference voltage, V10, at pin 10. The mark and space frequencies, fRI and fR2, generate the maximum d-c level shifts VR1 and VR2, that are sensed by the internal FSK comparator (see Figure 5) which is internally biased from the reference voltage, V10.
The external comparators, Comp. A and Comp. B of Figure 7, are biased at voltage levels VA and VB, at approximately halfway between VR1 and VR2, to trip at frequencies fA and fB, which are half-way between mark-to-center and space-tocenter frequency shifts. This biasing is achieved with the external resistive dividers, RA, RB, Rx and Ry of Figure 7, which generate the reference voltage levels, VA and VB, with respect to the XR-2211 internal reference at pin 10. It should be noted that the values of the resistors, (RA + RB) and (Rx + Ry) must be as large as possible (typically in ex-
::
z ii:
w"'""
"~ '
> 0
0
>
~'""
::>
'
?
0
~
~
~
--I ~TOTAL TRACKING BANDWIDTH
--VA _________ ,'_
'"'
- - VR2 --
INPUT SIGNAL FREQUENCY
Figure 8. XR-2211 Frequency-to-Voltage Transfer Characteristics. (Note: V11 and V10 are the DC voltage levels at pins 11 and 10, respectively.)
cess of 100 k.Q) to avoid disturbing the voltage level at pin 10.
The output of pin 11 is filtered by RK and CK and is used to drive the external voltage comparators. The outputs of these comparators are then connected through the external logic gates, to produce the carrier-detect or the enable/disable signal. The resulting logic output will be normally at a ''low" state, and will go "high" only when the carrier signal, fRQ, is present. This logic signal is normally used for transmitter enable/disable control, as shown in Figure 2.
The logic level changes at external comparator outputs correspond to mark-to-carrier or space-to-carrier frequency shifts (see Figure 8); thus, these outputs can be utilized as optional "Dual-Mode Monitor" outputs, D1 and D2, of Figure 2.
33
Application Note
AN-06
Precision PLL System Using the XR-2207 and the XR-2208
INTRODUCTION
The phase-locked loop (PLL) is a versatile system block, suitable for a wide range of applications in data communications and signal conditioning. In most of these applications, the PLL is required to have a highly stable and predictable center frequency and a wellcontrolled bandwidth. Presently available monolithic PLL circuits often lack the frequency stability and the versatility required in these applications.
This application note describes the design and the application of two-chip PLL system using the XR-2207 and the XR-2208 monolithic circuits. The XR-2207 is a precision voltage controlled oscillator (VCO) circuit with excellent temperature stability (±20 ppm/°C, typical) and linear sweep capability. The XR-2208 is an operational multiplier which combines a four quadrant multiplier and a high gain operational amplifier in the same package. Both circuits are designed to interface directly with each other with a minimum number of external components. Their combination functions as a high performance PLL, with the XR-2207 forming the VCO section of the loop, and the XR-2208 serving as the phase-detector and loop amplifier.
As compared with the presently available single-chip PLL circuits such as the XR-210 or the Harris Hl-2820, the two-chip PLL system described in this paper offers approximately a factor of 10 improvement in temperature stability and center frequency accuracy. The system can operate from 0.01 Hz to 100 kHz, and its performance characteristics can be tailored to given design requirements with the choice of only four external components.
DEFINITIONS OF PLL PARAMETERS
The phase-locked loop (PLL) is a unique and versatile feedback system that provides frequency selective tuning and filtering without the need for coils or inductors. It consists of three basic functional blocks: phase comparator, low-pass filter, and voltage-controlled oscillator, interconnected as shown in Figure 1. With no input signal applied to the system, the error voltage, Vct, is equal to zero. The VCO operates at a set "free-running" frequency, f0 · If an input signal is applied to the system, the phase comparator compares the phase and frequency of the input signal with the VCO frequency and generates an error voltage, Ve(t), that is related to the phase and frequency difference between the two signals. This error voltage is then filtered and applied to the control terminal of the VCO. If the input signal frequency, fs, is sufficiently close to f0 , feedback causes the VCO to synchronize or "lock" with the incoming signal. Once in lock, the VCO frequency is identical to the input signal, except for a finite phase difference.
Two key parameters of a phase-locked loop system are its "lock" and "capture" ranges. These can be defined as follows:
Lock Range = The band of frequencies in the vicinity of f0 over which the PLL can maintain lock with an input signal. It is also known as the "tracking" or "holding" range. Lock range increases as the overall loop gain of the PLL is increased.
Capture Range = The band of frequencies in the vicinity of f0 where the PLL can establish or acquire lock with an input signal. It is also known as the "acquisition" range. The capture is always smaller than the lock range. It is related to the low pass filter bandwidth and decreases as the low pass filter time constant increased.
INPUT SIGNAL
PHASE
Veit)
LOW PASS
COMPARATOR
FILTER
""
v0 ttl
'o
vco
v.
Figure 1. Block Diagram of a Phase-Locked Loop.
---·'L ·I
l·I
____,.. INCREASING FREQUENCY fs
II
l·I
l·I
1-1
Figure 2. Frequency to Voltage Transfer Characteristics of a PLL System; (a) Increasing Input Frequency; (b) Decreasing Input Frequency.
34
V< V·
13
I L f L SQUARE WAVE
14 /V\
OUTPUT
TRIANGLE OUTPUT
v
c,
I
ANALOG OUTPUT IOPTIONAU
Figure 3. Circuit Interconnections for the Precision PLL System Using the XR-2207 and the XR-2208 Monolithic Circuits. (SplitSupply Operation, ±6V to ±13V.)
V· 5.1K
Vt
16
2 13
14
V·
5.1K
10K
5.1K
SQUARE WAVE OUTPUT
I
TRIANGLE OUTPUT
-=-
SIGNAL INPUT
1
Cc ~ COUPLING CAPACITOR CB~ BYPASS CABAC1TOR
"2
c,I
=
Figure 4. Circuit Interconnections for Single Supply Operation.
-
ANALOG
OUTPUT (OPTIONAL)
c"I --
(V+ - 12V to 24V)
5.lK
5.1K
-=-
TABLE I
Phase-Locked Loop Design Equations*
(1)
1 Center Frequency: f0 = RoCo Hz
T i (7)
Loop
. Damping:=
2~ 1
=
.Jhe;;
(2) Lock Range: (ML/f0 ) = (0.9)(R0 /R 1 )
(3) Phase Detector Gain: K<t> = 0.5 Vee volts/radian
Where Vee = y+ for split supply; Vee = v+;2 for single
supply.
(4)
VCO
Conversion
Gain:
Kv
=
2
V ~ R
cc 0 I
rad/sec/volt
(5)
Loop
Gam. :
K
L
=
K,K qrv
=
0.25 CoR1
_t
sec
(8) Capture Range: a) Underdamped Loop(~< 1/2):
A (Mc/fo) = 0·:~ 0
b) Overdamped Loop(~> 1):
(6) LowPassFilterTimeConstant:r=c 1: 1 sec.
*See Figures 3 and 4 for component designation.
35
The PLL responds only to those input signals sufficiently close to the VCO frequency, f0 , to fall within the "lock" or "capture" ranges of the system. Its performance characteristics, there· fore, offer a high degree of frequency selectivity, with the selectivity characteristics centered about f0 · Figure 2 shows the typical frequency-to-voltage transfer characteristics of the PLL. The input is assumed to be a sine wave whose frequency is swept slowly, over a broad frequency range covering both the "lock" and the "capture" ranges of the PLL. The vertical scale corresponds to the filtered loop error voltage, Vd, appearing at the VCO control terminal.
As the input frequency, ~. is swept up (Figure 2(a)) the system does not respond to the input signal until the input frequency reaches the lower end of capture range, fcL. Then, the loop suddenly locks on the input signal, causing a positive jump in the error voltage Vd. Next, Vd varies at a slope equal to the reciprocal of VCO voltage-to-frequency conversion gain, (Ky), and goes through zero at ~ = f0 · The loop tracks the input frequency until ~ reaches the upper edge of the lock range, fLH· Then the PLL loses lock, and the error voltage drops to zero. If the input frequency is swept back slowly, from high towards low frequencies the cycle repeats itself, with the characteristics shown in Figure 2(b). The loop captures the signal at the upper edge of the capture range, fcH· and tracks it down the lower edge of the lock range, fLL. With reference to the figure, the "lock" and the "capture" ranges can be defined as:
Lock Range = .1fL = fLH - fLL
Capture Range = .1fc = fcH - fcL
The gain parameters associated with the PLL are defined as follows:
Phase Detector Gain, Kit>: Phase detector output per unit of phase difference between the two signals appearing at the phase detector inputs. It is normally measured in volts per radian.
VCO Conversion Gain, Ky: VCO frequency change per unit of input voltage. It is normally measured in radians/sec./volt.
Loop Gain, KL: Total ~ gain around the feedback loop. It is equal to the product of K4> and Ky.
Loop Damping Factor, ~: Defines the response of the loop error voltage Vd, to a step change in frequency. If ~ < 1, the loop is underdamped; and the error voltage Vd will exhibit an underdamped response for a step change of signal frequency.
The lock range of the phase-locked loop is controlled by the loop gain, KL. The capture range and the damping factor are controlled by both the loop gain and the low pass filter.
PRECISION PLL USING XR-2207 AND XR-2208
The XR-2207 VCO and the XR-2208 operational multiplier can be inter-connected as shown in Figure 3, to form a highly stable PLL system. The circuit of Figure 3 operates with supply voltages in the range of ±6 volts to ±13 volts; and over a frequency range of 0.01 Hz to 100 kHz. In the PLL system of Figure 3, all the basic performance characteristics of the PLL can be controlled and adjusted by the choice external 4 components identified as resistors R0 and R1 , and the capacitors C0 and C1 , C0 and R0 control the VCO center frequency; R1 and C1 determine the tracking range and the low pass filter characteristics. The two-chip PLL system can be readily converted to single supply operation by inter-connecting the circuit as shown in Figure 4. The PLL circuit of Figure 4 operates over a supply voltage range of+ l 2V to +26V.
For best results, the timing resistor Ro should be in the range
of 5k to lOOk, and R1 > R0 · Under these conditions, the basic
parameters of the PLL can be easily calculated from the design equations listed in Table 1.
Design Example
As an example, consider the design of a PLL system using the circuit of Figure 3, to meet the following nominal performance specifications:
a) Center Frequency = 10 kHz
b) Tracking Range= 20% (9 kHz to 11 kHz) c) Capture Range= 10% (9.5 kHz to 10.5 kHz)
Solution:
a) Set Center Frequency:
Choose R0 = lOk (Arbitrary choice for 5k <Ro < lOOk)
Then, from equation 1 of Table 1:
Co = (l/f0 R0 ) = 0.01 µF
b) Set Lock Range : From equation 2 of Table 1:
R1 = (4.5) Ro = 45k
c) Set Capture Range: Since capture range is significantly smaller than Lock range, equation 8(a) applies. Solving equation 8(a) for C1 , one obtains:
C1 = 0.032 µF
36
Application Note
AN-07
Single-Chip Frequency Synthesizer Employing the XR-2240
INTRODUCTION
The XR-2240 monolithic timer/counter contains an 8-bit programmable binary counter and a stable time-base oscillator in a single 16-pin IC package. Although the circuit was originally designed as a long-delay timer capable of generating time delays from microseconds to weeks, it also offers a wide range of other applications beyond simple time-delay generation. One such unique application is its use as a single-chip, frequency synthesizer, where it can generate over 2,500 discrete frequencies from a single reference frequency input.
PRINCIPLE OF OPERATION
The operation of the XR-2240 as a frequency synthesizer is possible because of the ability of the circuit to both multiply and divide the input frequency reference. It can, simultaneously, multiply the input frequency by a factor, "M," and divide it by a factor "N+ l ," where both M and N are adjustable integer values. Therefore, the circuit can produce an output frequency, fQ, related to the input reference frequency fR as:
Figure 1 shows the circuit connection for operating the XR-2240 timer/counter as a self-contained frequency synthesizer. The integer values M and N can be externally adjusted over a broad range:
1~M~10 1~N~255
The multiplication factor M is obtained by locking on the harmonics of the input frequency. The division factor N is determined by the pre-programmed count in the binary counter section. The principle of operation of the circuit can be best understood by briefly examining its capabilities for frequency division and multiplication separately.
Frequency Division by (l+N):
When there is no external reference input, f R, the time-base oscillator section of the XR-2240 free-runs at its set frequency,
f5 (f5 = l/RC), where Rand Care the external components at
pin 13. The 8-bit binary counter can be programmed to divide the time-base frequency by an integer count, N, and generate an output pulse train whose frequency is:
Frequency Multiplication by "M":
Frequency multiplication is achieved by synchronizing the time-base oscillator with the harmonics of the input sync or reference signal. Thus, if the time-base oscillator is made to free-run at "M" times the input frequency, it can be made to synchronize with the "M"th harmonic of the input reference signal. Typical capture range of the circuit is better than ±3%, for values of 1 ~ M ~ 1O; and since the time-base is accurate to within ±0.5% of the external R-C setting, lock-up does not present a problem for a given harmonic lock setting.
1K "'
0.1 ~F ~REFERENCE INPUT
..:r· 5.1K
3K
OUTPUT
. . . . . . FoO-.....--Cl--',____.______,.__~__,___.___._~.__~'VV~~""°'
-'V'V°lr"~
FIGURE 1
37
Circuit Operation:
With reference to Figure l, the operation of the synthesizer circuit can be briefly explained as follows: The reference input frequency, fR, is applied to the time-base sync terminal (pin 12) through a 5.1 Kn series resistance and a coupling capacitor. The recommended waveform for the input frequency, fR, is a 3 Vpp pulse train with a pulse width in the range of 30% to 80% of the time-base period, T. The multiplication factor M is chosen by the potentiometer R1 which sets the time-base period T (T = RC). If no external reference is used, then M is automatically equal to I.
The divider modulus, N, is chosen by shorting various counter outputs to a 3K common pull-up resistor. The output wave-
form is a pulse train with a fixed pulse width, T = RC, and a
period T0 =(N + I)RC.
The external R-C network between the output and the trigger and reset terminals of the XR-2240 is a non-critical delay net-
work which resets and re-triggers the circuit to maintain a periodic output waveform. For the component values shown in Figure I, the circuit can operate with the timing components Rand C in the range of:
c 0.005 µF :i;;; :i;;; .I µF; 1 Kn :i;;; R :i;;; I Mn
The XR-2240 is a low-frequency circuit. Therefore, the maximum output frequency is limited to ~200 kHz, by the frequency capability of the internal time base oscillator.
A particularly useful application of the simple synthesizer circuit of Figure 1 is to generate stable clock frequencies which are synchronized to an external reference, such as the 60 Hz line frequency. For example, one can generate a 100 Hz reference synchronized to 60 Hz line frequency simply by set-
ting M =5 and N =2 such that:
f0 =fR T+MN =(60) Ti5-2 = 100 Hz
38
Application Note
AN-08
Dual Tone Decoding with XR-567 and XR-2567
INTRODUCTION
Two integrated tone decoders, XR-567 units, can be connected (as shown in Figure IA) to permit decoding of simultaneous or sequential tones. Both units must be on before an output is given. R1 C1 and R' 1 C' 1 are chosen, respectively, for tones I and 2. If sequential tones (I followed by 2) are to be decoded, then C3 is made very large to delay turn-off of unit I until unit 2 has turned on and the NOR gate is activated. Note that the wrong sequence (2 followed by I) will not provide an output since unit 2 will turn off before unit I comes on. Figure I B shows a circuit variation which eliminates the NOR gate. The output is taken from unit 2, but the unit 2 output stage is biased off by R2 and CR 1 until activated by tone I. A further variation is given in Figure IC. Here, unit 2 is turned on by the unit I output when tone I appears, reducing the standby power to half. Thus, when unit 2 is on, tone I is or was present. If tone 2 is now present, unit 2 comes on also and an output is given. Since a transient output pulse may appear during unit I turn-on, even if tone 2 is not present, the load must be slow in response to avoid a false output due to tone I alone.
The XR-2567 Dual Tone Decoder can replace two integrated tone decoders in this application.
HIGH SPEED, NARROW BAND TONE DECODER
The circuit of Figure I may be used to obtain a fast, narrow band tone decoder. The detection bandwidth is achieved by overlapping the detection bands of the two tone decoders. Thus, only a tone within the overlap portion will result in an output. The input amplitude should be greater than 70 mV rms at all times to prevent detection band shrinkage and C2 should be between 130/f0 and 1300/f0 mfd where f0 is the nominal detection frequency. The small value of C2 allows operation at the maximum speed so that worst-case output delay is only about 14 cycles.
TOUCH-TONE DECODER
Touch-Tone decoding is of great interest since all sorts of remote control applications are possible if you make use of the encoder (the push-button dial) that will ultimately be part of every tone. A low-cost decoder can be made as shown in Figure 2. Seven 567 tone decoders, their inputs connected in common to a phone line or acoustical coupler, drive three integrated NOR gate packages. Each tone decoder is tuned, by means of R 1 and C1 , to one of the seven tones. The R2 resistor reduces the bandwidth to about 8% of I 00 mV and 5% at 50 mV rms. Capacitor C4 decouples the seven units. If you are willing to settle for a somewhat slower response at low input voltages (50 to 100 mV rms), the bandwidth can be controlled in the normal manner by selecting C2 , thereby
eliminating the seven R2 resistors and C4 · In this case, C2 would be 4.7 mfd for the three lower frequencies or 2.2 mfd for the four higher frequencies.
The only unusual feature of this circuit is the means of bandwidth reduction using the R2 resistors. As shown in the 567 data sheet under Alternate Method of Bandwidth Reduction, the external resistor RA can be used to reduce the loop gain and, therefore, the bandwidth. Resistor R2 serves the same function as RA except that instead of going to a voltage divider for de bias it goes to a common point with the six other R2 resistors. In effect, the five 567's which are not being activated during the decoding process serve as bias voltage sources for the R2 resistors of the two 567's which are being activated. Capacitor C4 (optional) decouples the ac currents at the common point.
LOW COST FREQUENCY INDICATOR
Figure 3 shows how two tone decoders set up with overlapping detection bands can be used for a go/no/go frequency meter. Unit l is set 6% above the desired sensing frequency and unit 2 is set 6% below the desired frequency. Now, if the incoming frequency is within 13% of the desired frequency, either unit l or unit 2 will give an output. If both units are on, it means that the incoming frequency is within l % of the desired frequency. Three light bulbs and a transistor allow low cost read-out.
39
DETECTION OF TWO SIMULTANEOUS OR SEQUENTIAL TONES
~
INPI"
+V
+V
RL 20K TONE 1 DECODER 1 7
(
+V
o-}
ll\IPUT
+V
+V
TONE2 DECODER
OUTPUT
FIGURE IA
FIGURE IB
LOW-COST TOUCH TONE®DECODER
C2 C3
J~
FIGURE IC FREQUENCY METER WITH LOW-COST LAMP READOUT
+V
4 3 UNIT 1
5 6 2 17
ON FREQUENCY
INPUT o---}
100-1000 mV nn1
+V HIGH
4
St-------'
UNIT2
6
17
COMPONENT VALUES (TYPICAL)
6.8 to 15K ohm
4.7K ohm
2.0K ohm
0.1 mfd
1.0 mfd 6V
2.2 mfd 6V
250
6V
FIGURE 2
40
ts--j t--0.1311 --f--0.13
UNIT 1 DETECTION
I I
UNIT 2
DETECTION
~-B_A_N_D_~-t--"-~B~A~N~D~__.FREQUENCY
I BOTH UNITS "ON"' AT OVERLAP
SENSING CENTER FREQUENCY
FIGURE 3
Application Note
AN-09
Sinusoidal Output From XR-215 Monolithic PLL Circuit
INTRODUCTION
In a wide range of communication or signal conditioning applications, it is necessary to obtain a sinusoidal output signal which is synchronized to a desired reference or clock input. This can be achieved by using the XR-215 type monolithic PLL circuit and an additional sine-shaping network.
When a periodic input signal is present within the capture range of the XR-215 PLL, the system will "lock" on the input; and the VCO section of the PLL will synchronize with the input frequency. The output of the oscillator section of the PLL can then be converted to a low distortion sine wave by a relatively simple sine-shaping circuit.
PRINCIPLE OF OPERATION
Figure 1 contains a functional block diagram of the XR-215 monolithic PLL system. The circuit consists of a balanced phase comparator, a highly stable voltage-controlled oscillator (VCO) and a high speed operational amplifier. The phase comparator outputs are internally connected to the VCO inputs and to the non-inverting input of the operational amplifier. A self-contained PLL system is formed by simply ac coupling the VCO output to either of the phase comparator inputs and adding a low-pass filter to the phase comparator output terminals. The XR-215 can operate over a large choice of power supply voltages ranging from 5 volts to 26 volts and a wide frequency band of 0.5 Hz to 35 MHz. It can accommodate analog signals between 300 microvolts and 3 volts and can interface with conventional DTL, TTL and ECL logic families.
+Vee
PHASE COMPARATOR OUTPUTS
RANGE SELECT
vco
TIMING
CAPACITOR
PHASE COMPARATOR INPUTS
PHASE COMPARATOR BIAS
15 VCO OUTPUT
"
VCO SWEEP INPUT
11 VCO GAIN CONTROL
-VEE
OP AMP INPUT
OP AMP COMPENSATION
OP AMP OUTPUT
Figure 2 shows the simplified circuit schematic of the XR-215 phase-locked loop JC. The VCO part ofXR-215, shown in the
Figure 1. Functional Block Diagram of XR-215 Phase-Locked Loop
~:~~e -------~------ VCO - - - - - - - 1 - - - - - - - OP.AMP. - - - - - - -
Figure 2. Simplified Circuit Schematic of XR-215
41
center section of Figure 2, is an emitter-coupled multivibrator circuit, whose frequency is set by an external capacitor, Co, connected across the timing terminals (pins 13 and 14). In this type of an oscillator, the differential voltage waveform across the timing capacitor, Co, is a linear triangle, with a peak-to-peak amplitude of 1.4 volts. This output amplitude across the timing capacitor is independent of supply voltage.
This triangular waveform can be shaped into a low distortion sinewave by passing it through a simple differential gain stage, as shown in Figure 3. By adjusting the potentiometer Rq of Figure 3, the input transistors TI and T2 of the differential stage can be brought to the verge of cutoff at the positive and the negative extremities of the input triangle wave. This causes the peaks of the triangle waveform to be rounded, resulting in a nearly sinusoidal output waveform from the differential stage. If the transistor characteristics and the current levels in the differential gain stage are well matched, one can reduce the total harmonic distortion (THD) of the sinusoidal output waveform to less than 3%.
Pin 8 =Substrate
Figure 4. Package Diagram for XR-ClOl Matched NPN Transistor Array
I
r,
INPUT
FROM PINS
13AND 14
OF
XR·215
V+ (12V)
5.1K SINUSOIDAL OUTPUT
JW
12K v+ (12V)
v+ = 12V WAVE FORM ADJ. #
I 15
FROM PINS 13AND 14 OF XR·215
12K v+ l12VI
XR·C101 NPN TRANSISTOR ARRAY
s1on
v+"' 12V
5.1K
16 SINUSOIDAL OUTPUT
1K
510H
*Adjust Rq for minimum harmonic distortion
Figure 3. A Simple Triangle-to-Sinewave Converter Using a Differential Gain Stage
The sine-shaper circuit of Figure 3 can be designed by using the XR-C I 01 NPN transistor array, which provides five identical NPN transistors in a single IC package. Figure 4 shows the
*Adjust Rq for minimum harmonic distortion
Figure 5. Use of XR-ClOl Transistor Array to Obtain Sinusoidal Output from XR-215 PLL
package diagram of XR-ClOl chip, in terms of its 16-pin DIP package.
The five independent transistors contained in the XR-C 101 transistor array can be interconnected, as shown in Figure 5, to form the differential sinewave-shaping circuit of Figure 3. The inputs of the sine-shaper can be directly connected to the timing capacitor terminals (pins 13 and 14) of the XR-215 PLL.
42
Application Note
AN·10
XR-C262 High-Performance PCM Repeater IC
INTRODUCTION
The XR-C262 is a monolithic repeater circuit for Pulse-Code Modulated (PCM) telephone systems. It is designed to operate as a regenerative repeater at 1.544 Megabits per second (Mbps) data rates on T-1 type PCM lines. It is packaged in a hermetic 16-pin CERDIP package and is designed to operate over a temperature range of -40°C to +85°C. It contains all the basic functional blocks of a regenerative repeater system including Automatic Line Built-Out (ALBO) and equalization, and is insensitive to reflections caused by cable discontinuities.
The XR-C-262 operates with a single 6.8-volt power supply, and with a typical supply current of 13 mA. It provides bipolar output drive with high-current handling capability. The clock-extractor section of XR-C-262 uses the resonant-tank circuit principle, rather than the injection-locked oscillator technique used in earlier monolithic repeater designs. The bipolar output drivers are designed to go to "off' state automatically when there is no input signal present. Compared to conventional repeater designs using discrete components, the XR-C262 monolithic repeater IC offers greatly improved reliability and performance and provides significant savings in power consumption and system cost.
This application note outlines the basic design principles and the electrical characteristics of the XR-C262 monolithic repeater IC. In addition, circuit connections and applications information are provided for its utilization in T-1 type 1.544 Megabit PCM repeater systems.
FUNDAMENTALS OF PCM REPEATERS
The Pulse-Code Modulation (PCM) telephone systems are designed to provide a transmission capability for multiplechannel two-way voice frequency signals which are transmitted in a digital PCM format. In order to minimize error rates, and provide transmission over long distances, this digital signal must be regenerated at periodic intervals, using a regenerative repeater system. Figure 1 shows the block diagram of a bidirectional PCM repeater system consisting of two identical digital regenerator or repeater sections, one for each direction
SIGNAL FLOW -
11
11
=311
6.BV
DIGITAL REGENERATOR
llL
- - - SIGNAL FLOW
Figure 1. Block Diagram of a Bi-Directional Repeater System.
of transmission. These repeaters share a common power supply. The DC power is simplexed over the paired cable and is extracted at each repeater by means of a series zener diode regulator.
In the United States, the most widely used PCM telephone system is the T-1 type system which operates at a data rate of 1.544 Mbps, with bipolar data pulses. It can operate on either pulp- or polyethylene-insulated paired cable that is either pole-mounted or buried. Operation is possible with a variety of wire gauges, provided that the total cable loss at 772 kHz is less than 36 dB. Thus, the system can operate satisfactorily on nearly all paired cables which are used for voice frequency trunk circuits.
The T-1 type transmission system is designed to operate with both directions of transmission within the same cable sheath. The system performance is limited primarily by near-end crosstalk produced by other systems operating within the same cable sheath. In order to insure that the probability of a bit error is less than 10-6, the maximum allowable repeater spacing, when used with 22-gauge pulp cable, is approximately 6000 feet.
The XR-C262 monolithic IC replaces about 90% of the electronic components and circuitry within the "digital repeater" sections of Figure 1. Thus, a bi-directional repeater system would require two XR-C262 ICs, one for each direction of information flow.
43
OPERATION OF THE XR-C262
The XR-C262 monolithic repeater is packaged in a 16-pin dualin-line hennetic package, and is fabricated using bipolar process technology. The functions of the circuit terminals are defined in Figure 2, in tenns of the monolithic IC package.
for line losses and band-limiting to reject unwanted noise as well as gain and phase equalization to shape received pulses.
A more detailed system block diagram for the monolithic repeater system is given in Figure 3. The system blocks shown within the dotted area are included on the monolithic chip. The numbers on the circuit tenninals correspond to the pin numbers of the 16-pin IC package containing the repeater chip. In tenns of the system block diagram of Figure 3, the overall repeater operation can be briefly explained as follows.
The bipolar PCM signals which are attenuated and distorted due to the preceding transmission medium are applied to the input of a preamplifier (Block 1) through an Automatic Line
Build-Out (ALBO) circuit. The impedance, Zi. corresponds to the passive section of the ALBO network. The preamplifier
section, along with the passive equalizer networks Zi and Z3
connected in feedback around it, provides gain to compensate
Figure 2. Package Diagram of XR-C262 Monolithic PCM Repeater.
INP~TJ PCSMIGNAL
11
CLOCK DRIVE OUTPUT
'>-----------~-113
VOLTAGE
DIVIDER 1 - - - 1 - - - - - - - - - - - - - - - - - ' - - I
NETWORK
'------....~·-1=4-~+---c=V~R~E~F:-::----t 151
CTR. TAP
ECL
DATA
C9 BYPASS CAP
LATCHES
Cc COUPLING CAP.
(9)
ZERO·
I ©-+-I ANALOG
·Vee <i3)--t--
INPUT SHUTDOWN
1111
l+I
I D1G1TAL
l 0 + - ANALOG I
GROUND
~
I DIGITAL
XR-C262 MONOLITHIC REPEATER
OUTPUT DRIVER
1121
1-1 OUTPUT DRIVER
1131
L--------------------~
Figure 3. Detailed Block Diagram of the XR-C262 Monolithic Repeater System.
REGENERATED
[
PCM OUTPUT
44
The ALBO circuitry provides attenuation and shaping to automatically adjust for vaiying cable characteristics. The output of the preamplifier is controlled to swing between two established peak levels. This is accomplished by feedback circuitry, and is similar in concept to automatic gain control. When the preamplifier output passes through the peak thresholds it is detected by the peak detector (Block 2) and produces a signal which is used to control a feedback loop establishing the attenuation and shaping of the ALBO network. The actual circuit design associated with this function is described in more detail in the discussion of peak detection and ALBO circuitry.
The output of the preamplifier drives a set of data comparators which are internally biased from a voltage reference (Block 4) and the precision voltage divider network (Block 5). Thus, the preamplifier output is "sliced" at various voltage levels to eliminate the effects of the baseline noise. This output is full-wave rectified and amplified through Block 6 of Figure 3. The resulting signal has a strong Fourier component at the clock frequency and is used to drive a high Q ("'='! 00) resonant circuit tuned to that frequency. The output of the resonant circuit is transformer-coupled to a zero-crossing detector and clock limiter (Block 10). The resultant output is the desired recovered timing. This resonant circuit is driven by a low impedance amplifier, and the resulting clock edges are in phase with the peak of the received pulses.
guarantees that in the event incoming data disappears, the output switches will not latch in the "on" state. When no input signal is present, the absence of clock is sensed and the output drivers are held in the "off' state.
DATA & CLOCK THRESHOLDS
PREAMP OUTPUT, "EYE" PATTERN
RESONATOR DRIVING WAVEFORM
The regeneration of the data is achieved through the two data comparators (Blocks 7 and 8) and the ECL latches (Block 9) which function as tracking flip-flops. The positive and negative data paths are separate; and, with the exception of the data· limiter and slicer levels, identical in design. The preamplifier output is sliced at about 45 percent of the peak voltage and its amplitude is limited to provide digital data pulses. The data is applied to one of the inputs to the tracking flip-flop, whose state is latched and unlatched by the clock. During acquisition, the flip-flop acquires data; during hold, further data transitions are ignored and the state of the flip-flop output determines whether an output pulse is transmitted. The implication of using the clock to perform data sampling is that path delays of the data and clock must be controlled to be equal. The monolithic integrated circuit technology affords this control. The advantage of this technique is that the need for clock shifting or strobe pulse generating circuitry for accurate sampling alignment is eliminated. Actual circuit implementation resulted in a 40 nsec misalignment of clock and data. This 40-nsec error in sampling time amounts to less than .4 dB degradation in SNR performance. Figure 4 shows the idealized timing and signal waveforms within the circuit.
RESONATOR OUTPUT WAVEFORM
CLOCK LIMITER WAVEFORM
Figure 4. Timing Diagrams of Voltage Waveforms within the Clock Regeneration Section.
The output drivers use latched data and clock to produce an output pulse-width which is accurately controlled by the duration of the clock. Non-saturating output drivers (Blocks 12 and 13) insure that output pulse rise and fall times are less than 100 nsec. The zero input shut-down circuitry (Block 11)
Figure 5 shows a practical circuit connection for the XR-C262 in an actual PCM repeater application for 1.544 Mbps T-1 repeater system. For simplification purposes, the lightening protection circuitry and the second repeater section for the reverse channel are not shown in the figure.
45
430µH
11
2 Krl
XR-C262
6.8V
4.7 µF
J;47 µF
NOTE
-t =ANALOG GROUND
m =DIGITAL GROUND
Figure 5. A Recommended Circuit Connection Diagram for T-1 Type Repeater Application.
DESCRIPTION OF CIRCUIT OPERATION
Preamplifier Section (Figure 6):
The circuit diagram of the preamplifier section is shown in Figure 6. This section is designed as a single-stage high-gain amplifier with differential inputs and a single-ended output. The amplifier output is internally connected to the peakdetector, full-wave rectifier and the data-comparator sections. The circuit exhibits a high differential input resistance (~ 106 ohms) and a low output impedance(~ 80 ohms). It has a nominal voltage gain of 69 dB at DC and ;;;. 50 dB at I MHz. The frequency response of the circuit exhibits a singlepole roll-off characteristics.
Peak-Detector and ALBO Section (Figure 7):
the ALBO filter. In the steady state, DC level across the ALBO filter controls the current through the diode string; and the
dynamic resistance of the diodes acts as the variolosser element. The usable linear resistance range in this application is almost
three orders of magnitude ranging from I IQ to ~ 6 Kn.
ANALOG------------------------~
+Vee
R3
01 · INPUTO
5
05
04 08
07
I I
f--------l---t--<J INPUT
3
09
The peak-detector circuit is designed to detect the peaks of the preamplifier output, provided that these peaks exceed the internal detection threshold levels. This peak information is then low-pass filtered and is used to control the current in a diode string which acts as a variable-loss or "variolosser" element in a feedback path. In the circuit, the comparators conduct whenever the preamp output exceeds the (+) threshold in a positive direction or the (-) threshold in a negative direction. Transistor Q5 then injects a pulse of current into
OUTPUT
ANB~~fG - - f - - - - - - - f - - - - - - - J - - - - J - - - J
ANALOG--4-----~'-------+---~-~ GROUND
Figure 6. Circuit Diagram of Preamplifier Section.
46
ANAlCJ(,
Vee
------------.~-----.--------~
01
RJ
05
01
·Pl Al<. THfHSllOI I)
VOl TA!.I
PEAK THRESHOLD
VOLTAGE
()lllf'lll
I - - - - - - - I A'\IAI ()(, - - - -fl IA~ IJJ
[)4 ANAL Oli liROIJNll --~-------------------~
Figure 7. Circuit Diagram of the Peak-Detector and the ALBO Sections.
Data Latches (Figure 8):
The data latches are required to be impervious to data transitions in the latch mode, and to be "transparent," (i.e., tracking the input data) during the tracking mode. Figure 8 shows the basic circuit configuration used in the XR-C262, which meets the above-mentioned perfonnance requirements. During the time when the clock pulse is high, the acquisition transistors Q1 and Q2 are differentially switched with data transitions, and the data is coupled to the respective bases of
0 3 and 0 4 . When the clock pulse goes low at the sample time
(see Figure 4), the information is regeneratively latched into
0 3 and 0 4 . While the clock is low, further data transitions
have no effect upon the state of the flip-flop. A more detailed description of the timing waveforms is given in Figure 13_
DIGITAL Vee ----------------->---~
08
R1
R2
07
D1 D2
Threshold Circuitry (Figure 9):
Threshold circuitry is a low impedance voltage-divirler circuit· corresponding to Block 5 of Figure 3, and it establishes the fixed levels required for data, clock and peak detection. It is important that the thresholds are insensitive to temperature variations, and that they are of sufficiently low impedance to guarantee that there is no threshold variation due to changing signal conditions. The reference voltages of the peak-detector, data, and clock thresholds are set by a resistor chain which. divides down the voltage of the on-chip zener diode. The ratios of data threshold to peak-detector threshold and that of clock threshold to peak-detector threshold are both set at 45 percent. In the actual circuit implementation, as shown in Figure 10, a compound connection of PNP's and NPN's are used to reduce the output impedance of the reference levels. The currents through the NPN and PNP transistor strings are set so as to insure that the base emitter voltage drops of the NPN's and PNP's are nominally the same. The output impedance of the resulting reference voltage taps are about 300 ohms. The center tap of the buffered divider is brought to a separate package tenninal (Pin 14 of Figure 3) for biasing the preamplifier input.
+Vee
ON CHIP ZENER V+ R1 R2 R3 R4
R5 R6
06 +PEAK THRESHOLD +DATA/CLOCK THRESHOLD CENTER TAP -DATA/CLOCK THRESHOLD - PEAK THRFSHOLD
R9
01 DATA ._!-----1
CLOCK -+--------1
02
t---+--DA TA
t--------1-CLOCK
DIGITAL GROUND ":"
Figure 8. Circuit Configuration for Tracking Data Latches.
Figure 9. Internal Voltage-Divider Network for Comparator Threshold Setting.
Clock Recovery Section (Figure 10):
Clock recovery circuitry consists of a full-wave rectifier, an external L-C resonant circuit, a zero crossing detector, and limiting amplifier, as shown in Figure 10. The full-wave rectifier circuit, comprising of cross-coupled transistor pairs Q1 through Q4 has a net voltage gain of 2, which is obtained
by Setting R 1 = R2 = (l/2)R 3 . The rectified output is then
buffered by the Darlington emitter-follower stage made up of
Os and Q6 , and applied to the external L-C resonant circuit.
47
CLOCK DRIVE 13 OUTPUT ~------+---.-----+----+---+--+---------+---+--+----+---+---+---+-----+---<>----Vee
R3
R6
R7
FULL·WAVE RECTIFIER
Figure 10. Circuit Diagram of the Clock Recovery Section.
0 6 is operated at a high bias current level to provide an output
impedance of less than I 5.Sl. This low impedance is required to insure that the L-C tank-drive circuitry looks like a voltage source.
The inductor of the resonant tank circuit is also a transformer which couples the sine wave signal to the zero crossing detector and limiting amplifier. The zero crossing detector is a differential amplifier with a nominal voltage gain of 20 and input impedance of 4 Mn. The sine wave from the resonant circuit is sliced to produce a square wave with sharp transitions at the zero crossings. This eliminates timing variations that may be caused by amplitude changes of the sine wave signal. The output of the zero crossing detector is further enhanced by the limiter which is another differential pair with a nominal voltage gain of 30. The output of this amplifier is a I .SY peak-to-peak square wave clock which drives the data latches and the output drivers.
Zero-Input Protection Circuit (Figure 11):
The zero input protection circuitry accomplishes the dual task of preventing the output switches from latching in an "on" state, as well as reducing the likelihood of output pulses with no input signal. The data, clock, and regenerator circuitry are all balanced DC coupled circuits. Controlling the steady state, no-signal condition of these circuits without building an unacceptable offset into the path is not practical. Instead, a retriggerable one-shot that uses the saturation characteristics of PNP transistors is used to control the level of the clock into the output switches. This technique uses the bandpass characteristics of the timing recovery resonant circuit to reject out of band signals thus minimizing the chance of producing output pulses with no input signal and the presence of noise. Figure I I shows the basic implementation of the zero-input protection
circuit. 0 1 and 0 2 function as a simple retriggerable one-shot. The transistor 0 2 is a lateral PNP device with a limited fre-
quency capability and long storage-time delay. The existence
of the I .544 MHz clock causes 0 2 to saturate and remain in
saturation while clock pulses are present. The comparatively
long time constant associated with 0 2 coming out of satura-
tion (""=' 5 µsec) insures that, when data is present, the zero input protection has no effect upon operation. When data dis-
CLOCK AMPLIFIER
01 CLOCK---+------!
05 CLOCK
CLOCK 2 CLOCK 1
Figure 11. Zero-Input Shutdown Circuit for Output Protection.
appears there is no clock to retrigger the one-shot, thus 02 comes out of saturation, causing 0 3 to saturate which pulls
the respective clock lines high, and disables both output drivers in their "off' state.
Output Drive Circuitry (Figure 12): The output drive circuitry is made up of two identical channels as indicated in the block diagram of Figure 2. The circuit configuration for each of these driver sections is shown in Figure I2. The output would follow the data input from the latches only when the clock input is at a "high" state, i.e.,
with 0 2 off and 0 3 on. In this manner, the output pulse-
width is controlled by the clock. To provide the fast turn-on and turn-off of the output drivers, all the transistors operate
in a nonsaturating state. 0 4 forms an active clamp to reduce
voltage swing at the base of Q6 , and the clamp diode D5
prevents the saturation of the output driver 0 7 . Because of
the biasing scheme mentioned above, the amplitude of the clock and the latched data are insensitive to supply voltage and temperature changes. Thus, the variations of the regenerated pulse-width over temperature and supply are minimized.
48
02
INf'llT ~HOM DATA!,\ !CHES
transformer (see Figure 3) to provide the regenerated bipolar output pulses shown in waveform (12) of Figure 13.
PREAMP
( 1)
OUTPUT
Figure 12. Circuit Configuration for the Output Drivers.
Timing Waveforms (Figure 13):
Figure 13 illustrates the relative time and phase relationships between the signal levels at various points within the circuit. For the purpose of illustration an input data pattern comprised of a string of "ONE"s is assumed, which looks like a nearly sinusoidal input, after having traveled through a dispersive transmission medium such as a long cable. Wave form ( 1) is the output of the preamplifier; waveforms (2) through (5) are the outputs of the two data comparators driven by the preamplifier output (see Figure 3). Waveform (6) is the lowlevel clock signal obtained from the resonant tank circuit, at pin 16 which is then amplified and "sliced" by the clockrecovery circuitry (see Figure 11) and appear as the internal clock signals shown as waveforms (7) and (8). The waveform (9) shows the output of one of the data latches (Figure 8) as a function of the clock and data inputs. The output of the latch tracks +DATA when the clock is low, and stays latched in that condition when the clock goes high. The output drive at pin 9, which is shown as waveform (10) will then go low only when the waveforms (8) and (9) are low. The waveform (11) shows the second output available at pin 11. These two outputs are then differentailly combined by the output
(2)
(+)JlATA
(3)
(+)DATA
(4) (5)
(6)
(7)
(8) (9) (10) ( 111 (12)
(-)DATA
(-)DATA
LC-TANK OUTPUT (PIN 16)
CLOCK
CLOCK
DATA LATCH OUTPUT (+)DRIVER OUTPUT (PIN 9) (-)DRIVER OUTPUT (PIN 11) BIPOLAR OUTPUT FROM XMFR
Figure 13. Timing Diagram of Circuit Waveforms for a 1-1-1 Input Data Pattern.
49
ELECTRICAL CHARACTERISTICS
+Vcc = 6.8 Volts, TA = -40°C to +85°C.
CHARACTERISTICS
Supply Current Digital Current Analog Current Totaf Current
Preamplifier Input Offset Voltage DC Gain Output High Level Output Low Level
Clock Recovery Section Clock Drive Swing (High) Clock Dri".e Swing (Low) Clock Bias Clock Source Input Current
Comparator Thresholds ALBO Threshold Clock Threshold
Internal Reference Voltages Reference Voltage Divider Center Tap
ALBO Section Off Voltage On Voltage On Impedance Filter Drive Current
Output Driver Section Output High Swing Output Low Swing Leakage Current Output Pulse Width Output Rise Time Output Fall Time Pulse Width Unbalance
MIN.
LIMITS TYP.
MAX.
UNITS
7
IO
2
3.5
13
13
mA
5
mA
17
mA
-15
+15
mV
60
69
4.3
74
dB
v
0.5
v
5.1
3.8
4
0.5
v
3.8
v
4.2
v
4
µA
0.75
0.9
1.1
v
0.323
0.4
0.517
v
5.2
5.45
5.55
v
2.6
2.78
2.85
v
IO 1.2
0.7
1
5.9
6.8
0.6
0.7
294
324
75
mV
1.7
v
15
n
1.5
mA
v
0.9
v
IOO
µA
354 nsec
IOO nsec
IOO nsec
15
nsec
CONDITIONS
Measured at Pin 12 Measured at Pin 8
Measured between Pins 3 and 5
Measured at Pin 1 Measured at Pin 1
Measured at Pin 13 Measured at Pin 13 Measured at Pin 15 Measured at Pin 16 Measured at Pin 1 relative to Pin 14
Measured at Pin 2 Measured at Pin 14
Measured at Pin 7 Measured at Pin 7 Measured at Pin 7 Drive current available at Pin 6 Measured at Pins 9 and 11 ~ =400rl IL= 15 mA Measured with output in off state
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Power Dissipation
Derate above +25°C Storage Temperature Range
+lOV 750mW 6 mW/°C -65°C to +150°C
PACKAGE INFORMATION
··
---I ..... OOS7
I J
O.OIJ
AVAILABLE TYPES
Part Number XR-C262
Package CE RD IP
Operating Temperature -40°C to +85°C
50
Application Note
AN-11
A Universal Sine Wave Converter Using the XR-2208 and the XR-2211
INTRODUCTION
A universal sine wave converter is a system block which can convert any periodic input signal waveform to a low-distortion sine wave, whose frequency is identical to the repetition rate of the periodic input signal. Such universal sine wave converters find applications in communications and telemetry systems. They are particularly useful for converting transducer output waveforms, or pulses, into clean sine wave signals over a band of frequencies. This conversion to sine wave is often necessary to reduce the required system bandwidth for signal transmission by eliminating the harmonic frequencies of the signal.
In the cases where the input frequency is known, and does not change, the universal sine wave converter can be replaced by a simple high-Q filter, tuned to the input frequency. However, in many cases the input frequency, or the repetition rate, is not constant, but varies as a function of time or input data. In such cases a fixed-frequency filter is not feasible, and one is forced to use a universal sine wave converter which is esentially a "tracking regenerative filter".
In this application note, the design principle and the performance characteristics of a regenerative sine wave converter circuit is described. The circuit operates on the phase-locked loop (PLL) principle and can be implemented using the XR-2211 monolithic PLL tone decoder and the XR-2208 multiplier IC.
PRINCIPLE OF OPERATION
Figure 1 shows the functional block diagram of a regenerative sine wave converter system, comprised of four functional blocks: (1) a phase-locked loop (PLL), (2) a sine-shaper, (3) a keyed amplifier, and (4) a lock-detect circuit. With reference to the figure, the principle of operation of the entire system can be briefly explained as follows:
When a periodic input signal is present at the input, within the tracking range of the PLL, the circuit would "lock" to the input signal; and the output of the voltage-controlled oscillator (VCO) section of the PLL will duplicate the frequency of the input signal. However, the VCO output waveform will have a fixed wave shape (normally a triangle wave) independent of 'the input waveform or amplitude. The output of the oscillator section then can be connected to a triangle-to-sine wave converter which converts it to a low-distortion sine wave. The ·output of the triangle-to-sine converter is then applied to a variable-gain amplifier which sets the desired output amplitude. Since the oscillator section of the PLL is always running, the circuit also contains a "lock-detect" section which enables the output amplifier only when there is an input signal. Thus, with no input signal present within the bandwidth of the PLL, the lock-detect section will keep the output amplifier in the "off" state, and the circuit will not produce an output signal.
PERIODIC
LOOP
~Pll)
f\J\..
SINUSOIDAL OUTPUT
LOCK-DETECT1---------~
CIRCUIT
ENABLE/DISABLE
141
Figure 1. Basic Concept of a Regenerative Sinewave Converter.
CIRCUIT DESIGN
The basic regenerative sine wave converter system of Figure 1 can be easily implemented using the XR-2211 monolithic tone decoder and the XR-2208 monolithic multiplier IC's, with only a minimum number of external components.
The XR-2211 is a monolithic PLL circuit especially designed for FSK and tone detection. Thus, it contains the complete PLL and lock-detect sections (Blocks 1 and 4 of Figure 1) on the same chip. Its overall block diagram is shown in Figure 2. The circuit is packaged in a 14-pin dual-in-line package; and the functions of the circuit terminals are given in Figure 3 in terms of the monolithic IC package. In the sine wave converter
51
LOOP FILTER
DATA FIL TEA
b
LOCK DETECT FILTER
LOCK DETECT
COMP
+Vee
INPUT
LOCK·DETECT FIL TEA
GROUND
Io
LOCK DETECT OUTPUTS
L a
DATA OUTPUT
TIMING CAPACITOR
J
TIMING RESISTOR
LOOP o-OET OUT REF VOLTAGE OUT
FSK COMP. INPUT
Figure 2. Block Diagram of XR-2211 Phase-Locked Loop FSK and Tone Decoder IC.
application, the FSK detector portion of the circuit is not used; only the basic phase-locked loop and the lock-detector sections are utilized. Figure 4 illustrates the necessary external components for its application in the sine wave converter system. The oscillator section of the XR-2211 is an emitter coupled multivibrator which oscillates by charging and discharging the external timing capacitor, C0 , (connected across pins 13 and 14) through internal constant-current stages. Thus, the output waveform, taken differentially across the timing capacitor, is a linear triangle wave. This waveform can then be converted to a low-distortion sine wave by the XR-2208 multiplier.
The XR-2208 is a monolithic multiplier circuit which contains a four-quadrant analog multiplier, an op amp, and a unity-gain buffer amplifier in a 16-pin dual-in-line package. Its functional block diagram and equivalent circuit schematic are given in Figures 5 and 6, respectively.
Figure 3. Package Diagram of XR-2211 PLL Circuit.
INPUT SIGNAL
1'
R1
LOCK DETECT COMP
Figure 4. External Circuit Connections for XR-2211 for Sinewave Converter Application.
I
MULTIPLIER OUTPUTS
L x
INPUT
COMMON
y INPUT
I
Y-GAIN
l
X-GAIN
+Vee
HIGH FREQ. OUTPUT
l
OP AMP INPUTS
J
COMP.
OP AMP OUTPUT
-VEE
X-GAIN
r- ---OPAMP--
Figure 5. Block Diagram of XR-2208 Operational Multiplier.
Figure 6. Simplified Circuit Schematic of the XR-2208 Operational Multiplier.
52
Figure 7 shows the recommended circuit connection of the XR-2211 and the XR-2208 to form a universal sine wave converter circuit. In the figure, a non-crital zener diode (Vz:::::: 6V to 7V) is used to reduce the supply voltage applied to XR-2211, to facilitate DC coupling between the two chips. The frequency of the VCO section of the XR-2211 is set by the timing components R0 and C0 . In this application, a fixed
value of Ro = 1OKn is recommended, giving a center fre-
quency, f0 value of:
The triangle wave oscillator output of the XR-2211 PLL is attenuated through a resistive divider made up of two 1OKn resistors, and a variable lOKQ potentiameter, Rx. The attenuated triangle wave across Rx is then applied differentially to the X-input (pins 4 and 5) of the XR-2208. The 1oon external resistor across Y-gain setting terminals (pins 6 and 7) causes the Y-input of the multiplier to be slightly overdriven, and thus causes the peaks of the triangle input rounded into a low-distortion sine wave.
The distortion of the sine wave is minimized by adjusting Rx, which sets the triangle wave amplitude. The sinusoidal output is available at the unity-gain buffer terminal (pin 15) of the XR-2208. This output is then level-shifted toward ground, through two 1OKn resistors, and is AC coupled to the inverting input of the op amp section of XR-2208. The gain of the op amp is externally adjusted by means of the 500Kn potentiometer, RF. The DC voltage level of the op amp output is set at the reduced supply voltage (i.e., Vee -Vz).
The lock-detect output of the XR-2211 (pin 6) is shorted to the mid-point of the resistive divider at pin 15 of the XR2208. With no input signal present at the input within the lock range of the XR-2211, pin 6 is at a "low" state. Thus it acts as a shorting switch to ground and disables the op amp section of the XR-2208. When a periodic input signal appears at the circuit input and the XR-2211 establishes lock with the signal; the lock-detect output at pin 6 goes to a "high" or nonconducting state and enables the output op amp of the XR2208; and a low-distortion sine wave output is obtained at the output (pin 11 of XR-2208).
JLJl c
PERIODIC"
IC
INPUT V------,
Co 1 µF
XR-2211
7
10K
2 XR-2208
Vz 6.7V +
OUTPUT
Vee
Rx= Distortion Adj. Potentiometer RF =Output Amplitude Adj. Pot.
Cc = Coupling Capacitor (~0.1 µF)
Fhure 7. Recommended Circuit Connection for the Regenerative Sinewave Converter. 53
The circuit of Figure 7 can operate as a sine wave converter, over a frequency band between two frequencies fH and fL corresponding to the upper and lower lock ranges of the PLL. With the components shown in the figure, this corresponds to approximately ± 30% bandwidth around the center frequency, f 0 , for inputs with close to 50% duty cycle. For periodic inputs with less than 50% duty cycle, this lock range is reduced further. For example, for inputs with 20% duty cycle, this bandwidth drops to about ± 10% of center frequency. The operation of the circuit with input signals having less than 10%
(or more than 90%) duty cycle is not practical. The minimum input level required for circuit operation is lOmV rms. The circuit can generate a nearly sinusoidal output with input signals from very low frequencies up to 100 kHz. Typical distortion characteristics of the output are shown in Figure 8, as a function of frequency of operation. Figure 9 shows a typical example of input and output waveforms for the sine converter circuit of Figure 7, operating at 1 kHz input repetition rate, with a noisy input signal.
VouT = 3V, pp.
1 kHz
10 kHz FREQUENCY____...
Figure 8. Output Distortion vs Frequency.
100 kH2
Figure 9. Typical Input-Output Waveforms.
(Top: Noisy Input Signal; Bottom: Sinusoidal Output.)
Scale: Vertical:
1 Volt/Div.
Horizontal: 1 m Sec./Div.
54
Application Note
AN-12
Designing High Frequency Phase· Locked Loop Carrier-Detector Circuits
INTRODUCTION
The phase-locked loop (PLL) system can be converted to a frequency-selective tone- or carrier-detection system by the addition of a "quadrature detector" section to the basic PLL. Such a carrier-detect system serves as a "lock indicator" for the PLL and produces a logic signal at its output when there is a tone or a carrier signal present within the lock range of the phase-locked loop.
A number of monolithic tone-decoder IC's have been developed which implement the quadrature-detection technique for detection of low frequency tones, such as those used for telephone dialing or ultrasonic remote control. However, because of the particular PLL designs used in these monolithic detectors, their applications are limited to frequencies below 100 kHz. This application note describes a circuit approach, using the XR-210 or the XR-215 high frequency PLL's, along with the XR-2228 monolithic multiplier/detector, which extends phase-locked loop tone detection capabilities to frequencies up to 20 MHz.
PRINCIPLE OF OPERATION
The basic block diagram of a phase-locked loop tone detector system is shown in Figure 1. Such a detector system produces a logic-level signal at its output, when the PLL is locked on an input signal. It is made up of two main sections:
1. A PLL section which synchronizes or "locks" on the input signal.
2. A "quadrature detector" section made up of a phasedetector, a low-pass filter and a voltage-comparator.
Its principle of operation can be briefly described as follows: When the PLL is locked on an input signal, its voltagecontrolled oscillator (VCO) section produces a set of input
signals, <1>1 and ili 1. which are 90° apart in phase, but have the
same frequency as the input signal to be detected. One of these signals, <1>1, is used to drive the PLL phase detector; the other output, which is called the "quadrature output" is used to drive a "quadrature phase-detector'', as shown in Figure I. If the PLL is locked on the input signal, then the input signal and the VCO signal applied to the quadrature phase-detector are coherent in phase and frequency. This causes a DC level shift at the low-pass filtered output of the quadrature phasedetector and makes the voltage comparator output change its output logic state. Thus, an output logi9 signal is produced indicating the "lock" condition of the PLL.
This type of tone detection technique is a special case of the "synchronous AM detection" principle, discussed in detail in Exar's Application Note AN-13. The key difference between the tone detection and the synchronous AM detection application is that, in the case of the tone detection, a binary logic output is produced, corresponding to the "presence" or the "absence" of the desired input tone, rather than an analog demodulated signal.
XR-210 AND XR-215 HIGH FREQUENCY PLL CIRCUITS
The XR210 and the XR-215 are high frequency phase-locked loop detector and demodulator circuits. Their functional block diagrams are shown in Figures 2 and 3. Both circuits are packaged in 16-pin dual-in-line packages and contain high frequency VCO and phase-detector sections. The XR-215 chip also contains an operational amplifier. In the case of the XR-210, this op amp section is replaced by a high-gain voltage comparator which drives an open-collector type logic output. The XR-210 is particularly intended for FSK demodulation and can operate up to 20 MHz. The XR-215 is designed for linear FM detection and is suitable for frequencies up to 35 MHz. Except for the frequency capability of the VCO, the oscillator and the phase-comparator sections of both circuits are quite similar.
TONE OR CARRIER INPUT
PHASE-LOCKED LOOP
r-------b--'---, II
PHASE DETECTOR
I I
I I
I
IL_
LOW PASS FILTER
I I
Vco
I
"-!...________ _JI
DEMODULATED FM OR FSK OUTPUT
r--
I QUAD
-
4
-
-
-
b--
"--
-
-
-
-
,
I
PHASE DETECTOR
I
IL_______~_~;:_ss_____ _JI
QUADRATURE DETECTOR
TONE DETECT OUTPUT
Figure 1. Functional Block Diagram of a PLL Tone- or Carrier-Detector System
55
+Vee
PHASE COMPARATOR OUTPUTS
VCO CONTROLS
vco
TIMING CAPACITOR
9 10 13
14
PHASE COMPARATOR INPUTS
PHASE COMPARATOR BIAS
PHASE
VCO OUTPUT
VCO SWEEP AND GAIN CONTROLS
LOGIC OUTPUT
COMPARATOR INPur
-VEE
Figure 2. Functional Block Diagram of XR-210 HighFrequency FSK Modulator/Demodulator
+Vee
PHASE COMPARATOR OUTPUTS
RANGE SELECT
vco
TIMING
CAPACITOR
10
13
Figure 1. The op amp is used as a high-gain voltage comparator which converts the differential voltage level changes at the multiplier outputs into logic level output signals.
(a) VCO OUTPUT
WAVEFORM (PIN 151
/ \ / \ / \ / \ (b) WAVEFORMACROSS V V V V \ VCO TIMING
_JnLJoLoJ LnJ L CAPACITOR (PINS 11AND121
(C) "SLICED" VERSION
OF TIMING CAPACITOR WAVEFORM
Figure 4. Timing Diagram of VCO Output Waveforms Available from XR-210 or XR-215 High-Frequency PLL Circuits
·Vee
MULTIPLE OUTPUTS
15
1 16
OP AMP INPUTS
OP AMP COMPARATOR
14 13
12
PHASE COMPARATOR INPUTS
PHASE COMPARATOR BIAS
PHASE
"
VCO OUTPUT
12
VCO SWEEP
INPUT
11 VCO GAIN CONTROL
X-INPUTS
x
FOUR QUADRANT MUL Tl PLIER
11 OP AMP >-----+~< I OUTPUT
OP AMP INPUT
OP AMP COMPENSATION
OP AMP OUTPUT
Figure 3. Functional Block Diagram of XR-215 HighFrequency Phase-Locked Loop
The VCO section of the XR-210 or the XR-215 does not provide a separate "quadrature output", which is 90° phaseshifted with respect to the basic VCO output (pin 15 ). However. the triangular output available across the VCO timing capacitor terminals (pins 13 and 14) can serve as such a quadrature output if it is amplified and "sliced" externally, as shown in the timing diagram of Figure 4.
XR-2228 MULTIPLIER/DETECTOR CIRCUIT
The XR-2228 is comprised of a four-quadrant multiplier and a high-gain op amp on a single monolithic chip. It is packaged in a 16-pin dual-in-line package and has the functional block diagram shown in Figure 5. It contains independent and fully differential X- and Y-inputs which makes it easy to interface with the XR-210 or the XR-2 I 5 type PLL circuit for carrierdetection applications. In the tone- or carrier-detect application. the multiplier section of the XR-2228 is used as the "quadrature phase-detector" section of the block diagram of
6 78 9
Y-GAIN X-GAIN
SET
SET
10 -VEE
Figure 5. Functional Block Diagram of XR-2228 Multipler/ Detector
CIRCUIT OPERATION
Figure 6 shows the generalized circuit connection of the XR-2228, along with either the XR-210 or the XR-215 high frequency PLL IC for tone- or carrier-detection application. Since the external connections for the XR-210 or the XR-215 are the same as those given in their respective data sheets. only the external circuitry associated with the XR-2228 is shown in the figure. The circuit, as shown. can operate with a single power supply, from IOV to 20V. or with split supplies in the range of ±5V to ±IOV. In the case of split power supplies. the resistor string biasing the input terminals of the XR-2228 is not necessary and can be eliminated by connecting node A of Figure 6 to ground.
The input signal is AC coupled, with separate coupling capacitors, both to the input of the particular PLL circuit to be used. and to the X-input terminal (pin 2) of the XR-2228.
56
The Y-inputs (pins 4 and 5) are driven differentially from the VCO timing capacitor signal (available at pins 13 and 14 of the PLL IC) which is AC coupled to pins 4 and 5 of the XR-2228 multiplier input. The multiplier input stage "slices" this signal to produce the quadrature frequency waveform shown in Figure 4(c).
The differential DC voltage level at the multiplier output terminals (pins 1 and 6) is offset by means of an external resistor. RA, as shown in Figure 6. This initial offset causes the op amp output of the XR-2228 to settle to a known state when there is no carrier or tone signal to be detected. With the op amp input connections as shown in Figure 6, the op amp output (pin 11) would be at a "low" state when the PLL is not locked on a tone, and goes to a "high" state (i.e., near +Vee) when the PLL circuit is "locked" on to an input tone. The output logic polarity can be reversed simply by reversing the op amp inputs.
The filtercapacitor,CA.connectedacrosspins 1and16ofthe multiplier outputs, serves as the post-detection low-pass filter (Block 5 of Figure I). The time constant of this filter is equal to (CA Rs) where Rs ( ~ 8k£1) is the internal resistance of the IC at pins 1 and 16. The value of CA is chosen to provide a compromise between the response time and the spurious noise rejection characteristics of the circuit: increasing CA improves the noise rejection characteristics of the circuit. but slows down the response time.
The detection threshold (i.e., minimum detectable input sig-
nal amplitude) varies inversely with the multiplier gain-setting resistor Rx. Figure 7 shows the typical detectable signal level, as a function of Rx, with the output offset resistor, RA, equal to 10 ks-2. Note that the minimum detectable input signal, with Rx= 0, is approximately 100 mV, rms.
1000
~
>"
.§
800
~
i'
::;
~
< "
600
z
".'"..
~
"'.~,
400
".~..
c
""" 200
z
i
1K
2K
JK
4K
5K
Rx ui Kil
Figure 7. Minimum Detectable Input Carrier Level, as a Function of Multiplier Gain Setting Resistor. Rx.
1µF+
INPUT ______iUWlW_
SIGN Al
"""""
0 ·
I 0.1 µF :;----1
XR 210
XR 215 HIGH FREQUENCY PHASE LOCKED LOOP
I
I I I
I
" I
Co
I
14
_______ _J
14
0. 1 µF 10K 0. 1 µF 0.1 µF
+Vee 15
XA-2228
x
MULTIPLIER
10K
10K
:::i;::: 2 µF
f-1-j
_fl_
11
CARRIER
DETECT
OUTPUT 12
Rx
Figure 6. Recommended Circuit Connection of the XR-2228 with the XR-210 or the XR-215 High-Frequency Phase-Locked Loops for Tone- or Carrier-Detector Application
57
Application Note
AN-13
Frequency- Selective AM Detection Using Monolithic Phase· Locked Loops
INTRODUCTION
This application note describes the use of monolithic phase-locked loop (PLL) circuits in detection of amplitude-modulated (AM) signals. The detection capabilities of a PLL system, which is a frequency-selective FM demodulator. can be extended to cover AM
signals simply by the addition of an analog multiplier (or mixer) and a low-pass filter to the basic phase-locked loop. This tech· nique of AM demodulation, which is called "synchronous AM detection", offers significant performance advantages over conventional "peak-detector" type AM demodulators, in terms of its dynamic range and noise characteristics.
This application note outlines some of the fundamental principles of synchronous AM detectors, and gives design examples using the XR-2228 multiplier/detector IC in conjunction with the XR-215 and the XR-2212 monolithic PLL circuits.
PRINCIPLE OF OPERATION
The phase-locked loop AM detector circuits operate on the socalled "coherent AM detection" principle, where the amplitude modulated input signal is mixed with an unmodulated "coherent" carrier signal, and then low-pass filtered to produce the desired demodulated output signal. Figure I gives a simplified block diagram of such a detector system.
The amplitude-modulated input signal can be described by an expression of the form:
Input Signal= Ym(t) cos w 0 t
where Ym(t) is the modulated amplitude of the input signal and w 0 is the input signal frequency expressed in radians. If this signal is linearly multiplied with an unmodulated signal which has the same frequency and phase as the input signal, then the output of the multiplier, Vo(t), is a col)1posite signal of the form:
Vo(t) = KoVm(t) [I +cos (2 w 0 t) J
where Ko is the gain of the multiplier circuit. If the above signal is then passed through a low-pass filter, to eliminate the double-frequency term, the resulting output signal is:
Yout =Output Signal= Ko Ym(t)
which corresponds to the detected AM information.
The phase-locked loop AM detectors also operate on a s1m1-
lar principle: the PLL is made to "lock" on the carrier fre-
quency of the input AM signal; then the VCO output of the
PLL will regenerate the unmodulated coherent carrier signal
necessary for detection. When this signal is mixed with the input AM signal and the resulting composite signal is passed through a low-pass filter, one obtains the demodulated output. Figure 2, gives a block diagram of such an AM detector system. Compared to the basic synchronous AM detector system
of Figure I, the phase-locked loop AM detector of Figure 2,
also has one added feature: the output of the PLL control voltage (i.e., output of the PLL low-pass filter) can be used
as an FM detector or a frequency discriminator. Thus, such a system is capable of simultaneous AM and FM detection. In other words, the frequency and the amplitude modulation information present on the input signal can be separately and simultaneously demodulated. The particular design and application examples given in this application note (all into this category.
AM SIGNAL INPUT
Vm(t) cos w 0 t
x
MULTIPLIER
UNMODULATED CARRIER SIGNAL Ee cm v.:ot
Vo(t)
b
LOW PASS FILTER
Vout
DEMODULATED OUTPUT KoVm(tl
Figure 1. Block Diagram 01 a Synchronous AM Detector
AM OR FM INPUT
r - - - - - - - - - - - - 1 PHASE LOCKE0 LOOP
I PHASE
DETECTOR
I--... 2 LJ
I
DEMODULATED
I
FM OUTPUT
LOW PASS FIL TEA
I I
....-----.
I
vco
I
L_ _ _________JI
r- ---------1
:[Kl-I b'l l .~ DEMODULATED
L____________ I MuLr1PL1ER
~~L~;:ss
_JI
AMouTPUT
SYNCHRONOUS DETECTOR
Figure 2. The Basic Phase-Locked Loop AM Detector
58
XR-2212 AND XR-2228 MONOLITHIC CIRCUITS
The XR-2212 monolithic PLL is made up of an input preamplifier, a phase-detector, a high-gain differential amplifier and a stable voltage-controlled oscillator (VCO) as shown in Figure 3. The key feature of the XR-2212 PLL is the temperature stability and the frequency accuracy of its VCO section: it offers 20 ppm/° C typical temperature stability and a frequency accuracy of ± 1% for an external RC setting. The oscillator section of the XR-2212 contains a separate "quadrature output'' terminal (pin 15) which is particularly intended for interfacing with a synchronous AM detector such as the XR-2228.
The XR-2228 multiplier/detector IC is specifically intended as a basic building block for synchronous AM detection. It contains a four-quadrant analog multiplier and a high-gain op amp on the same chip, as shown in the functional block diagram of Figure 4.
·VCC
PHASl OE T INPUT
PHASED~ T
OP AMP INPUTS
OP AMP COMP
SI GNA l (')-C----1----1
INPLJ T
vco VOL TAI,! 0-'--4-C
OUTPlJ!
PHASE DET
VCO OUTPUT
OUAOHAlURl OUTPUT
TIMING CAP
GROUND
vco INPUT
ITIMING fHSISTOHI
Figure 3. Functional Block Diagram of XR-2212 Precision Phase-Locked Loop
XR-215 HIGH FREQUENCY PHASE-LOCKED LOOP
The XR-215 is a high frequency phase-locked loop circuit capable of operating with input signal frequencies up to 35 MHz. It is comprised of a high frequency VCO, a phasedetector and an op amp section, as shown in the block diagram of Figure 5.
Unlike the XR-2212 PLL, the VCO section of the XR-215 does not have a separate "quadrature output" terminal. However, such a quadrature oscillator signal can be obtained by amplifying and "slicing" the triangle waveform available across the timing capacitor (pins 13 and 14) of the XR-215 oscillator section. Figure 6, shows the relative phase relationship of these oscillator waveforms available from the circuit. The desired quadrature output signal (Curve C of Figure 6) can be obtained by directly connecting one pair of the differential inputs of the XR-2228 directly across the timing capacitor terminals of the XR-215.
AM/FM DETECTION USING THE XR-2212 PLL
Figure 7, shows a generalized circuit connection diagram for a
·Vee
MUL T OUTPUTS
15
1 16
OP AMP INPUTS
OP AMP COMP
14 13
12
X-INPUTS Y INPUTS
x
FOUR QUADRANT MULTIPLIER
>--+--<1 OP AMP
OUTPUT
67 8 9
Y GAIN )(GAIN
SET
Sf T
Figure 4. Functional Block Diagram of XR-2228 Multiplier/ Detector IC
two-chip AM and FM detection system, utilizing the XR-2212 PLL and the XR-2228 multiplier/detector. The XR-2212 section serves as the basic FM detector. The quadrature output of its VCO (pin 15) is AC coupled to the Y-input of the XR-2228.
The Y-input of the XR-2228 is operated in its switching mode, with the Y-gain terminals (pins 6 and 7) shorted together. The AM and/or FM signal is simultaneously applied to both circuits through coupling capacitors; and all the multiplier inputs are DC biased from the internal reference output of the XR-2212 (pin 11). The output of the multiplier, at pin 16, is AC coupled to the op amp section of the XR-2228, which serves as the post-detection amplifier for the demodulated AM signal.
· Vee
PHASE COMPARATOR OUTPUTS
16
RANGE SELECT
vco
TIMING CAPAC! TOR
10
13 14
PHASE COMPARATOR INPUTS
PHASE
PHASE COMPARATOR l r--------~ BIAS
15
'------+--'.:.'.() VCO SWEEP
INPUT
[) '-------+--'~' VCO GAIN CONTROL
OP AMP INPUT
OP AMP COMPENSATION
OP AMP OUTPUT
Figure 5. Functional Diagram of XR-215 High-Frequency Phase-Locked Loop
The circuit configuration shown in Figure 7, can operate with a single power supply, over the supply voltage range, of IOV to 20V. Its operation or performance can be t;ii!ored for any particular AM and FM detection application by the choice of external components shown in the figure, over a carrier frequency band of 1 kHz to 300 kHz. The functions of these external components are as follows:
59
(a) ~~~~~~=~T
(PIN 151
/ \ / \ / \ / \ (b) ~~~~~~1:~~~~oss
\ / V V \ / \ (PINS 11ANO12)
n n n n "SLICED"VERSION
----t----t------+---+--+------1t-----t----+-- (c) OF TIMING CAP
_J LJ D LJ L WAVEFORM
Figure 6. Timing Diagrams of VCO Output Waveforms from XR-21 S Monolithic Phase-Locked Loop
a) Ro and Co set the VCO center frequency for the XR-2212
PLL circuit. The center frequency, fo is given as:
I fo- - -
Roco The VCO frequency fo is chosen to be equal to the carrier frequency of the input signal. Ro is normally chosen to be in the range of 10 kD to 100 kD. This choice is arbitrary. For most applications Ro "'=' 20 kD is recommended. Once
fo is given and Ro is chosen, then Co can be calculated
from the above equation.
b) R1 determines the tracking bandwidth of the PLL. For
a required tracking bandwidth, .6f (see Figure 9 of XR-2212 data sheet) and fo, R1 can be calculated as:
(ro) R1 =Ro ~f
This tracking bandwidth, .6f, is the band of frequencies in
the vicinity of fo, over which the PLL can maintain lock.
c) C1 sets the loop-damping factor for the PLL. For most
applications, Ct is chosen to be equal to one-ha! f of Co.
d) R2 and C2 fom1 a low-pass filter for the detected FM signal. The 3-dB frequencing, f2. of this low-pass filter is:
f 2 = -27r-RI-2C-.2-
Nom1 ally, f2 is chosen to be equal to the demodulated FM information bandwidth.
e) Re and RFt set the gain of the op amp section of the XR-2212 as:
=I+ Ay
Ri:1)
\ Re
This op amp section serves as the post-detection amplifier
for the demodulated FM signals.
f) Rx sets the multiplier gain for the X-input and RF2 sets the gain of the op amp section of the XR-2228. Thus. the demodulated AM signal output swing. Yout- for a given input signal of peak amplitude of VM and modu-
lation index of m (0 < m < I) can be approximated as:
v = (vM)m ( RF2)
out
4
Rx
Thus. for example. a 100 mV peak input signal with 30'/r, AM modulation (m = 0.3) will give a demodulated output of 150 mY peak. with RF2 = I00 U2 and Rx= 5 kS2. at pin 11 of the XR-2228.
g) C3. in conjunction with the 5 kn internal impedance of the multiplier output (pin 16) serves as the low-pass postdetection filter for the demodulated AM signal.
For further explanation and description of the system design equations, the reader is referred to the XR-2212 and the XR-2228 data sheets.
r ice
AMO
SIGN
INPUT Ro
10K 14
13 lOOK
Cc 0 1 16
C3 _I_
-
5 1K
2K
x MUL Tl PLIER
1--1-5 r >-----<>-< 1 +vcc
Figure 7. A Two-Chip AM/FM Detector System Using the XR-2212 Phase-Locked Loop and the XR-2228 Multiplier/Detector 60
Design Example: Design an AM demodulator for 100 kHz
carrier frequency with a detection (tracking) bandwidth of ±4%. The demodulated information bandwidth is 3 kHz and an output level of 1 volt peak is required for a 1 volt peak input with 30% modulation.
Using the circuit of Figure 7, one proceeds as follows: Since FM detection is not required in this example, components
R2, C2, Re and RF1 are not essential to circuit operation.
R2 and Re can be short-circuited, C2 and RF1 can be left
open-circuited. The rest of the component values are calcu-
lated as follows:
Step I)
Set fo = 100 kHz by choosing Ro = 20 kn and calculating Co from paragraph (a) above:
1 co= Rofo = 500 pF
Step 2) Determine R1 to set tracking bandwidth to ±4%, from paragraph (b ): R1 = 500 kn
Step 3) Calculate C1: C1 ""'Co/2 ""' 250 pF
Step 4)
From paragraph (f), calculate the value of Rx and RF2· For a typical choice of Rx = 5 kn, and m = 0.3 (30% modulation) with I volt input carrier level, the value of RF2 to get I volt demodulated output is: RF2 = 67 kn
Step S) Calculate C'3 to get 3 kHz bandwidth for postdetection filter: C3 ""'0.01 µF
AM DETECTION USING THE XR-21 S PLL
Figure 8, shows the circuit connection diagram for a two-chip AM and FM detection system, using the XR-215 highfrequency PLL in conjunction with the XR-2228 multiplier/ detector. Because of the high-frequency capability of the XR-215, the circuit of Figure 8, is useful as a phase-locked
AM detector for carrier frequencies up to 20 MHz, and oper-
ates over a supply voltage range of IOV to 20V.
The VCO section of XR-215 does not have a separate "quadrature" output. However, this problem can be overcome by driving the XR-2228 multiplier directly from the timing capacitor terminals (pins 13 and 14) of XR-215. The Y-input of the XR-2228 is operated with maximum gain, since the Y-gain control terminals (pins 6 and 7) are shorted together. This causes the triangular waveform across Co to be converted to an effective "quadrature" drive as indicated by the timing diagram of Figure 6. The modulated input signal is simultaneously applied to both circuits through coupling capacitors. The phase-detector inputs of the XR-215, as well as the multiplier X-inputs of the XR-2228, are biased at approximately one-half of Vee, by means of an external resistive divider.
In Figµre 8, Co sets the VCO frequency of the XR-215. In the case of FM demodulation, R1 and C1 serve as the postdetection filter for the detected FM signal and RF1 sets the gain of the FM post-detection amplifier.
The mode of operation of the XR-2228 is virtually the same as that described in connection with Figure 7: Rx sets the multiplier demodulation gain; C3 serves as the low-pass postdetection filter. The values of Rx, RF2 and C3 are calculated as given in paragraphs (f) and (g).
AM/FM Q>---1------------:-:o;;;-------------,
SINIGPUNTAi
Rfl
100K
R1
Cc
..I:1
Vee 0.1 µF
2K
2K
lK
J
2K
48µ1
0.1 µF
.I
14
Co 13
,,
12
3K
CC= COUPLING CAPACITOR
Figure 8. Circuit Connection for a High-Frequency AM and FM Detector Using the XR-215 and the XR-2228
61
Application Note
AN-14
A High Quality Function Generator System Using the XR-2206
INTRODUCTION
Waveform or function generators capable of producing AM/FM modulated sine wave outputs find a wide range of applications in electrical measurement and laboratory instrumentation. This application note describes the design, construction and the performance of such a complete function generator system suitable for laboratory usage or hobbyist applications. The entire function generator is comprised of a single XR-2206 monolithic IC and a limited number of passive circuit components. It provides the engineer, student, or hobbyist with highly versatile laboratory instrument for waveform generation at a very small fraction of the cost of conventional function generators available today.
GENERAL DESCRIPTION
The basic circuit configuration and the external components necessary for the high-quality function generator system is shown in Figure I. The circuit Shown in the figure is designed to operate with either a l 2V single power supply, or with a ±6V split supplies. For most applications, split-supply operation is preferred since it results in an output DC level which is nearly at ground potential.
The circuit configuration of Figure 1 provides three basic waveforms: sine, triangle and square wave. There are four overlapping frequency ranges which give an overall frequency range of 1 Hz to 100 kHz. In each range, the frequency may be varied over a 100: 1 tuning range.
The sine or triangle output can be varied from 0 to over 6V (peak to peak) from a 600 ohm source at the output terminal.
A squarewave output is available at the sync output terminal for oscilloscope synchronizing or driving logic circuits.
TYPICAL PERFORMANCE CHARACTERISTICS
The performance characteristics listed below are not guaranteed or warranted by Exar. However, they represent the typical performance characteristics measured by Exar's application engineers during the laboratory evaluation of the function generator system shown in Figure 1. The typical performance specifications listed below apply only when all of the recommended assembly instructions and adjustment procedures are followed:
(a) Frequency Ranges: The function generator system is designed to operate over four overlapping frequency ranges:
1 Hz to 100 Hz 10 Hz to 1 kHz 100 Hz to 10 kHz 1 kHz to 100 kHz
The range selection is made by switching in different tiining capacitors.
(b) Frequency Setting: At any range setting, frequency can be varied over a 100: I tuning range with a potentiometer (see R13 of Figure 1).
(c) Frequency Accuracy: Frequency accuracy of the XR2206 is set by the timing resistor R and the timing capacitor C, and is given as:
f =I/RC
The above expression is accurate to within ±5% at any range setting. The timing resistor R is the series combination of resistors ~ and R13 of Figure 1. The timing
capacitor C is any one of the capacitors c3 through c6,
shown in the figure.
(d) Sine and Triangle Output: The sine and triangle output amplitudes are variable from OV to 6 Vpp· The amplitude is set by an external potentiometer, R12 of Figure 1. At any given amplitude setting, the triangle otttput amplitude is approximately twice as high as the sinewave output. The internal impedance of the output is 600S1.
(e) Sinewave Distortion: The total harmonic distortion of sinewave is less than 1% from 10 Hz to 10 kHz and less than 3% over the entire frequency range. The selection of a waveform is made by the triangle/sine selector switch, S2.
(t) Sync Output: The sync output provides a 50% duty cycle pulse output with either full swing or upper half swing of the supply voltage depending on the choice of sync output terminals on the printed circuit board (see Figure 1).
(g) Frequency Modulation (External Sweep): Frequency can be modulated or swept by applying an external control voltage to sweep terminal (Terminal I of Figure 1). When not used, this terminal should be left open-circuited. The open circuit voltage at this terminal is approximately 3V above the negative supply voltage and its impedance is approximately 1000 ohms.
62
AMPLITUDE
R12
AM INPUT OUTPUT
r------
A
R
a
p
------------------,
I
I I I I
I TRI/SINE SW
0 52
V+ +6V IC
D C3 1µ
~ 0.1µ
Sl
~ 0.01µ
R3 1K
~ 0.001µ
R4 9K
H
R6 SK
R5 SK
+
C7 10µ/&V
L__ _ _ _ _ _ _ _ I
J
SWEEP INPUT
R13 1M
FREQUENCY
NOTE: 1. For single supply operation lift GND connection keeping R12 across terminals Rand B intact, and connect terminal A to GND. 2. For maximum output, Rx may be open. Rx= 68 Kn is recommended for external amplitude modulation.
Figure 1. Circuit Connection Diagram for Function Generator. (See Note 1 for single supply operation.)
(h) Amplitude Modulation (AM): The output amplitude varies linearly with modulation voltage applied to AM
input (terminal Q of Figure 1). The output amplitude reaches its minimum as the AM control voltage approaches
the half of the total power supply voltage. The phase of the output signal reverses as the amplitude goes through its minimum value. The total dynamic range is approximately 55 dB, with AM control voltage range of 4V referenced to the half of the total supply voltage. When not used, AM terminal should be left open circuited.
(i) Power Source: Split supplies: ±6V, or single supply: +l 2V. Supply Current: 15 mA (see Figure 3).
EXPLANATION OF CIRCUIT CONTROLS:
Switches
Range Select Switch, S 1: Selects the frequency range of operation for the function generator. The frequency is inversely proportional to the timing capacitor connected across Pins 5 and 6 of the XR-2206 circuit. Nominal capacitance values and frequency ranges corresponding to switch positions of S1 are as follows:
Position
1 2 3 4
Nominal Range
1 Hz to 100 Hz 10 Hz to 1 kHz 100 Hz to 10 kHz 1 kHz to 100 kHz
Timing Capacitance
1 µF 0.1 µF 0.01 µF 0.001 µF
If additional frequency ranges are needed, they can be added by introducing additional switch positions.
Triangle/Sine Waveform Switch, S2: Selects the triangle or sine output waveform.
Trimmers and Potentiometers
DC Offset Adjustment, R9: The potentiometer used for adjusting the DC offset level of the triangle or sine output waveform.
Sinewave Distortion Adjustment, RIO: Adjusted to minimize the harmonic content of sinewave output.
Sinewave Symmetry Adjustment, RI 1: Adjusted to optimize the symmetry of the sinewave output.
Amplitude Control, RI 2: Sets the amplitude of the triangle or sinewave output.
63
Frequency Adjust, R13: Sets the oscillator frequency for any range setting of Sl. Thus, R13 serves as a frequency dial on a conventional wavefonn generator and varies the frequency of the oscillator over an approximate 100 to 1 range.
Tenninals
A. Negative Supply -6V B. Ground C. Positive Supply +6V D. Range 1, timing capacitor terminal E. Range 2, timing capacitor terminal F. Range 3, timing capacitor terminal G. Range 4, timing capacitor terminal H. Timing capacitor common terminal I. Sweep Input J. Frequency adjust potentiometer terminal K. Frequency adjust potentiometer negative
terminal L. Sync output (1/2 swing) M. Sync output (full swing) N. Triangle/ sine waveform switch terminals 0. Triangle/sine waveform switch terminals P. Triangle or sinewave output Q. AM input R. Amplitude control terminal
supply
PARTS LIST
The following is a list of external circuit components necessary to provide the circuit interconnections shown in Figure 1.
Capacitors:
CI,C2,C7 C3 C4
cs
C6
Electrolytic, 10 µF, lOV Mylar, I µF, nonpolar, 10% Mylar, 0.1 µF, 10% Mylar, 0.01µF,10% Mylar, 1000 pF, 10%
Resistors:
RI R2 R3,R7 R4 R5,R6 R8 RX
30 Kn, l/4W, 10% 100 Kn, l/4W, 10% I Kn, l/4W, 10% 9 Kn, l/4W, 10% 5 Kn, l/4W, 10% 300n, l/4W, 10% 62 Kn, 1/4 W, 10% (RX can be eliminated for maximum output)
Potentiometers:
R9
Trim, I Mn, l/4W
RIO
Trim, I Kn, l/4W
RI 1
Trim, 25 Kn, 1/4W
The following additional items are recommended to convert the circuit of Figure 1 to a complete laboratory instrument:
Potentiometers:
Rl2
Amplitude control, linear, 50 Kn
Rl3
Frequency control, audio taper, 1 Mn
Switches:
Sl S2
Rotary switch, 1-pole, 4 pas. Toggle or slide, SPST
Case: 7" x 4" x 4" (approx.) Metal or Plastic
(See Figures 4(a) and 4(b).)
Power Supply: Dual supplies ±6V or single + l 2V Batteries or power supply unit
(See Figures 3(a) and 3(b).)
Miscellaneous: Knobs, solder, wires, terminals, etc.
BOARD LAYOUT
Figures 2(a) and 2(b) show the recommended printed-circuit board layout for the function generator circuit of Figure 1.
(a) Split Supply PC Board Layout
'd KJ \JI
S1
Hf:(JF,
~
M
(b) Single Supply PC Board Layout
Figure 2. Recommended PC Board Layout for Function Generator Circuit of Figure 1. RECOMMENDED ASSEMBLY PROCEDURE
The following instructions and recommendations for the assembly of the function generator assume that the basic PC board layout of Figures 2(a) or 2(b) is used in the circuit assembly.
64
All the parts of the generator, with the exception of frequency adjust potentiometer, amplitude control potentiometer, triangle/sine switch and frequency range select switch, are mounted on the circuit board.
Install and solder all resistors, capacitors and trimmer resistors on the PC board first. Be sure to observe the polarity of capacitors C1, C2 and C7. The timing capacitors C3, C4, C5 and C6 must be non-polar type. Now install IC 1 on the board. We recommend the use of an IC socket to prevent possible damage to the IC during soldering and to provide for easy replacement in case of a malfunction.
The entire generator board along with power supply or batteries and several switches and potentiometers will fit into a case of the type readily available at electronic hobby shops. It will be necessary to obtain either output jacks or terminals for the outputs and AM and frequency sweep inputs.
Install the frequency adjust pot, the frequency range select switch, the output amplitude control pot, the power switch, and the triangle/swine switch on the case. Next, install the PC board in the case, along with a power supply.
Any simple power supply having reasonable regulation may be used. Figure 3 gives some recommended power supply configuration.
Precaution: Keep the lead lengths small for the range selector switch.
Figure 4 gives an example of the fully assembled version of the function generator system described above.
n·:Jii
Rl 51
Cl
500 µF
·6V
D5 6V GND
C2
500 µF
51 A2
D6 6V -6V
(a) Zener Regulated Supply
- ~_6'.'._--i~·6V __r::-<> GND
f-6V-1-J- ~-6V
(b) Battery Power Supply
T1: Filament transformer Primary 115V/Secondary 12.6 VCT, 0.5A
01 - 04: I N4001 or'similar 05, 06: I N4735 or similar C1, C2: Electrolytic, 500 µF/12 VDC A1, A2: 51!1, 1/2W, 10%
Figure 3. Recommended Power Supply Configurations.
Figure 4. Typical Example of a Fully Assembled Function Generator.
ADJUSTMENT PROCEDURE
When assembly is completed and you are ready to put the function generator into operation, make sure that the polarity of power supply and the orientation of the IC unit are correct. Then apply the DC power to the unit.
To adjust for minimum distortion, connect the scope probe to the triangle/sine output. Close S2 and adjust the amplitude control to give non-clipping maximum swing. Then adjust RIO and RI 1 alternately for minimum distortion by observing the sinusoidal waveform. If a distortion meter is available, you may use it as a final check on the setting of sine-shaping t:immers. The minimum distortion obtained in this manner is
typically less than I7r from I Hz to 10 kHz and less than 3%
over the entire frequency range.
65
Application Note
AN-15
An Electronic Music Synthesizer Using the XR-2207 and the XR-2240
INTRODUCTION
This application note describes a simple, low-cost ''music synthesizer" system made up of two monolithic IC's and a minimum number of external components. The electronic music. synthesizer is comprised of the XR-2207 programmable tone generator IC which is driven by the pseudo-random binary pulse pattern generated by the XR-2240 monolithic counter/timer circuit.
PRINCIPLE OF OPERATION
All the active components necessary for the electronic music synthesizer system is contained in the two low-cost monolithic IC's, the XR-2207 variable frequency oscillator and the XR-2240 programmable counter/timer. Figure I shows the functional block diagram of the XR-2207 oscillator. This monolithic IC is comprised of four functional blocks: a variable-frequency oscillator which generates the basic periodic waveforms; four current switches actuated by binary keying inputs; and buffer amplifiers for both the triangle and squarewave outputs. The internal current switches transfer the oscillator current· to any of four external timing resistors to produce four discrete frequencies which are selected according to the binary logic levels at the keying terminals (pins 8 and 9).
The XR-2240 programmable counter/timer is comprised of an internal time-base oscillator, a control flip-flop and a programmable 8-bit binary counter. Its functional block diagram is shown in Figure 2, in terms of the 16-pin IC package. The eight separate output terminals of the XR-2240 are "opencollector" type outputs which can either be used individually, or can be connected in a "wired-or" configuration.
Figure 3 shows the circuit connection for the electronic music or time synthesizer system using the XR-2207 and the XR-2240. The XR-2207 produces a sequence of tones by oscillating at a
frequency set by the external capacitor C 1 and the resistors R 1 through R6 connected to Pins 4 through 17. These resistors set the frequency or the "pitch" of the output tone sequence. The counter/timer IC generates the pseudo-random pulse patterns by selectively counting down the time-base frequency. The counter outputs of XR-2240 (Pins 1 through 8) then activate the timing resistors R1 through R6 of the oscillator IC, which converts the binary pulse ·patterns to tones. The time-base oscillator frequency of the counter/timer sets the "beat" or the tempo of the music. This setting is done through C3 and R0 of Figure 3.
The pulse sequence coming out of the counter/timer IC can be programmed by the choice of counter outputs (Pins 1 through 8 of XR-2240 connected to the programming pins (Pins 4 through 7) of the XR-2207 VCO. The connection of Figure 3 is recommended since it gives a particularly melodic tone sequence at the output.
The pseudo-random pulse pattern out of the counter-timer repeats itself at 8-bit (or 256 count) intervals of the timebase period. Thus, the output tone sequence continues for about I to 2 minutes (depending on the "beat") and then repeats itself. The counter/timer resets to zero when the device is turned on; thus, the music, or the tone sequence, always starts from the same point when the synthesizer is turned on.
r
TIMING CAPACITOR
L
,., 4
I ., TIMING
l"'RESISTORS "·
Figure 1. Functional Block Diagram of XR-2207 Oscillator Circuit.
Figure 2. Functional Block Diagram of XR-2240 Counter/ Timer.
66
+12V
RS 5.1K
VOLUME
CONTROL
R7
R21
R9 3.9K
C5
.1 µF
SPEAKER
C4
I1µF
XR-2207
C1 0.01 µF R1 R2 R3 R4 R5 R6
RO THRU R6 = 100K R7 = 10 Kil
R16 10K
R17 10K
OFF ---0
ON +12V
XR-2240
+12V
R20
+
R10
C2
C3
Io.1 µFL-1oµF
Figure 3. Circuit Connection Diagram for the Music Synthesizer.
67
100K
Application Note
AN-16
Semi-Custom LSI Design with 12L Gate Arrays
INTRODUCTION
In designing semi-custom monolithic LSI, one uses a partially fabricated silicon wafer which is "customized" by the application of one or more special mask patterns. This technique greatly reduces the design and tooling cost and the prototype fabrication cycle associated with the conventional full-custom IC development cycle; and thus makes custom IC's economically feasible even at low production volumes.
Until recently, the application of semi-custom design technology to complex digital systems has been somewhat limited due to one key factor: to be economically feasible, a complex digital LSI chip must achieve a high functional density on the chip {i.e., high gate count per unit chip area). Traditionally, this requirement is not compatible with the random interconnection concept which is key to the semi-custom or master-slice design approach. This paper describes a new approach to the master-slice concept which overcomes this age-old problem. It achieves packing densities approaching those of full-custom digital LSI layout while still maintaining the low-cost and the quick tum-around attributes of semi-custom IC design. This is achieved by making use of unique layout and interconnection properties of I2L gates, and by extending the mask-programming to additional mask layers besides the metal interconnection.
FEATURES OF I2LTECHNOLOGY
Integrated Injection Logic (12L) is one of the most significant recent advances in the area of monolithic LSI technology. Compared to other monolithic LSI technologies, I2L offers the following unique advantages:
High Packing Density Bipolar Compatible Processing Low Power and Low Voltage Operation Low (Power x Delay) Product
Figure 1 gives a comparison of the speed and power capabilities of various logic families, including J2L Since I2L technology is a direct extension of the conventional bipolar IC technology, it readily lends itself to combining highdensity digital functions on the same chip along with conventional Schottky-bipolar circuitry. The availability of bipolar input-output interface on the same chip along with the highdensity J2L logic makes it very convenient to retrofit custom J2L designs into many existing logic systems.
The J2L logic technology is developed around the basic singleinput, multiple-output inverter circuit shown in Figure 2. A recommended circuit symbol for this gate circuit is also defined in the figure. Most terminals of the I2L gate share the same semi-conductor region {for example, the collector of the PNP is the same as the base of the NPN; and the emitter of the NPN is the same as the base of the PNP). This leads to a very compact device structure, and results in very high packing density in monolithic device fabrication. Figure 3 illustrates the basic device structure and the cross-section for a bipolarcompatible I2L gate. Since the individual I2L gates do not require separate P-type isolation diffusions, they can be placed in a common N-type tub. This feature greatly enhances the packing density on the chip since it eliminates the need for
separate isolation pockets for individual gates. With conventional photo-masking and diffusion tolerances, gate densities of greater than 200 gates/mm2 can be readily achieved in fullcustom layout. Using the semi-custom approach which is outlined in this paper, one can maintain a packing density of
CMOS
54L TTL
54LS TTL
"" 54H TTL
' " · 1 Pi
1' 0pi,
' EtL· ECL
10K
111
" " 1n1.__~~---'~~~-"~~~-"~~~-"~~~.....
" " 1.w
100.w
1 mW
10mW
100mW
POWER/GATE
Figure 1. Comparison of Speed and Power Capabilities of Various Logic Families.
greater than 120 gates/mm2 even with random metallization or interconnection requirements. This offers at least a fact9r of four improvement over conventional bipolar master-slice technology and approximately a factor of two improvement over MOS master-slice approach in terms of gate-density and chip area utilization.
68
Figure 2. Equivalent Circuit (a), and a recommended symbol {b) for an I2L Gate.
·~:
TABLE I List of Components on XR-300 and XR-500 Semi.Custom Chips
COMPONENT TYPE
Multiple Output J2L Gates Input/Output Buffer.; Schottky - NPN Transistor.; Resistor.; Bonding Pads Chip Size (mils)
Chip Type XR-300
288 28 56 168 34
104xl40
XR-500 520 40 80 240 42
122xl85
L-11--------'
n-TYPE Tue
S,07
,....wL..~i> ..............
,,_
,........,...:..,
. ,, ··,_,
... .u..u.......
--·o-;;o-~r-
...,u........._~
'_"",''',· 'h' ,.1lJLu.
MOO t1jJm'
I
'
Figure 3. Basic Device Structure for Bipolar Compatible 12L.
DESIGNING WITH I2L GATE ARRAYS
A number of I2L gate arrays have been developed at Exar utilizing bipolar-compatible integrated injection logic technology. The most recent additions to this family of products are the XR-300 and the XR-500 gate array chips which are specifically intended for semi-custom IC designs involving complex digital systems. These chips contain a large number of multiple-output I2L gates along with Schottky-bipolar mput/ output buffers. Table I gives a summary of the components available on each of these chips.
Figure 4 shows the basic layout architecture of the XR-300 and the XR-500 gate array chips. As indicated in the figure, each chip is made up of two sections: (a) the r2L gate matrix; and (b) the Schottky-bipolar input/output interface. In addition, the bipolar I/O section contains two identical sets of resistor arrays, located at opposite ends of the chip, which are used for biasing the injectors of the I2L gates. The basic features of each of the sections of the gate array chips are outlined below:
Figure 4. Basic Architecture of XR-300 and XR-500 I2L Gate Arrays.
a) The I2L Gate Matrix:
This section of the I2L gate array is made up of 8-gatc "cells." These cells contain eight multiple-output I2L inverters which share a common set of four injectors. Figure 5 shows a basic 8-gate cell section within the I2L gate section, prior to customization. The basic 8-gate cells forming the r2L gate matrix are made up of P-type injectors and gate fingers which serve as the base regions of the I2L gates. The six dots on each gate area indicate the possible locations or sites for gate input or outputs. The particular use of these sites as an input or an output is determined by two custom masks: an N-type collector diffusion mask which defines the locations of outputs, and a custom contact mask which opens the appropriate input and output con tact. Finally, a third custom mask is applied to form the metal interconnections between the gates, and the gate cells. The custom N-type diffusion step, which detem1ines the locations of gate outputs, is also used for forming lowresistivity underpasses between the gate-cells. The area between each of the gate cells can accomodate two or three parallel underpasses in the horizontal and the vertical directions, respectively. Since the N-type diffusion which forms these underpasses is a part of the customizing step, the location and the length of each underpass can be chosen to fit a given interconnection requirement. This method
69
provides the designer with virtually all the advantages and capabilities of multi-layer interconnection paths on the surface of the chip; and allows approximately 80% of the gates on the chip to be utilized in a typical random-logic layout.
function of the injector current per gate. As indicated in Figure 8, the average power-delay product for a four-output gate is approximately 0.5 pJ at low currents; and the typical propagation delay, tpd· at injector currents in excess of 100 µA/gate is approximately 50 nsec for the output furthest from the injector. Figure 9 shows the two components of the total propagation delay, namely the turn-on and turn-off delay, as a function of the injector bias. At low injector currents (i.e., Ij :s;;; I 0 µA), turn-on delay is the dominant factor. For high-speed operation with Ij ~ 50 µA, turn-off delay becomes the dominant limitation in speed. Typical toggle rate of a D-type flip-flop as a function of injector current is shown in Figure 10. As indicated in the figure, toggle rates of 3 MHz are obtained at injector current levels of approximately 100 µA per gate.
_J
SYMBOLS · Me11l ln1frconnect1on
<) · ln1ectorCon11c1 Q · G11e0u!ptJI
t:l · Gate Input
L_
DOTS INDICATE LOCATION OF INPUT/OUTPUT SITES
Figure 5. Basic 8-Gate Cell Before Customization.
The custom logic interconnections can be easily laid out in pencil on a layout sheet by simply interconnecting the desired gate "sites" with a pencil line and appropriately defining the function of the site as an input, output, injector contact or an underpass. Figure 6 shows a typical example of such a logic layout. The corresponding symbols defining the function of the sites on the layout are also identified in the figure. For convenience, an underpass is indicated with a resistor symbol, connecting two triangles corresponding to the terminal points of the underpass.
Figure 7 shows the sample layout of the same 8-gate cell, after its customization with a selective N-type collector diffusion, contact-window cut and the metal interconnection patterns.
Typical electrical characteristics of the I2L gates within the gate matrix are listed in Table 2. Typical operating characteristics of the gates are given in Figures 8, 9 and 10, as a
TABLE 2 Typical Characteristics of I2L Gates
Parameter
Typical Characteristics at Various Injector Currents lj = 100 nA Ij =I µA Ij = IOµA Ij = IOOµA
Output Sink Current. Io Output Sat. Voltage, VoL Input Threshold Pwr. - Delay Product (V+ = 1V) Average Prop. Delay Max. Toggle Freq. (D F/F) Input OFF Current (V1N = 0) Output Breakdown Voltage
300 nA 3 mV 0.48 mV 0.6 pJ 6 µsec 6 kHz 150 nA
3V
8 µA 3 mV 0.54 mV 0.6 pJ 0.6 µsec 60 kHz 1.5 µA
3V
80 uA 4mV 0.60 mV 1.0 pJ 200 nsec 400 kHz 15 µA
3V
600 µA IOmV 0.66 mV
3 pJ 50 nsec 3 MHz 130 µA
3V
INJECTOR BUS
Figure 6. Sample Pencil Layout on a Logic Cell.
_J
GA TE INPUT
INPUT
METAL INTERCONNECTION
DIFFUSED UNDERPASS
INJECTOR BUS
a,
Figure 7. Sample Layout of 8-Gate Cell After Customizing it with N+ Collector Diffusion, Contact Mask and Metal Interconnection Pattern.
70
.....
......
·~·~-------------------~
·~·
100nA
h·A
10.,A
INJECTOR <;UR RENT PER GATE
lOOµA
1mA
Figure 8. Propagation Delay Characteristics of I2L Gates as a Function of Injector Current.
'"""'
>
~
0
,....
~ ~
Q ~
;:
0z< z
'"'
Q
~
;:
~ JOOni
~ > <
AVERAGE TUAN ON DELAY AVERAGE TURN OFF DELAY __/
·~·~-------------------~
·~·
100nA
10µA
lOOµA
INJ~CTOl-l C:lJRH~NT P~H (,/\If
Figure 9. Average Tum-On and Tum-Off Delay vs. Injector Current.
zu>-
w
10 MHz 5
:l
0
2
wa:
u..
1 MHz
w
.J
500
"'"0'
200
t- 100 kHz
::i
:l
~
50
x
20
<(
::i 10 kHz
0,01 µA
0.1 µA
1 µA
10 µA
100µA
INJECTOR CURRENT PER GATE
1 rnA
Figure 10. Maximum Toggle Rate of D-Type Flip-Flop as a Function of Injector Current.
b) Schottky-Bipolar 1/0 Section:
The Schottky-bipolar input/output interface sections are located along the periphery of the XR-300 and the XR-500 gate array chips. In addition, this bipolar section of the chip contains two sets of resistor arrays, located at opposite ends of the chip (see Figure 4) for programming or setting the injector current levels for the 12L gates. By proper tapping of these resistor arrays, the injector currents of the gates
can be set to any value between 1 µA to 100 µA per gate. For operating with current levels below 1 µA/gate, an external current setting resistor can also be used.
The component layout of a typical bipolar input/output interface cell is shown in Figure 11. Such an 1/0 interface cell contains one bonding-pad, several diffused resistors of varying values, two Schottky-clamped NPN transistors and a clamp diode to the substrate. Each of the NPN bipolar transistors are capable of sinking lOmA of output current, with typically a saturation voltage of O.SV. The breakdown voltage of the bipolar output transistors is 6V; however, modified versions of the XR-300 and XR-500 I2L gate arrays are also available with output breakdown voltage in excess of 15V. Figure 12 shows some of the most commonly used input and output interface circuit configurations available from the basic bipolar 1/0 cell.
BONDING PAD
R1 = 1OK
Figure 11. Typical Schottky-Bipolar Input/Output Interface Cell.
10K INPUT
10K
(A) INPUT INTERFACE CIRCUIT
~-----+--- v·
20K
5K
OUTPUT
(Bl OUTPUT INTERFACE CIRCUIT
Figure 12. Typical Bipolar I/O Interface Circuits.
71
SEMI-CUSTOM DESIGN CYCLE
The semi-custom LSI design program utilizing the XR-300 and XR-500, is devised for maximum versatility, to suit varying customer needs or capabilities. Figure 13 gives an outline of the six basic steps associated with a typical I2L semi-custom program. The sequence of these steps are also outlined below:
(1)
Feasibility Review
and
Logic Conversion to 12 L Gates
1
(2)
Pencil Layout on Gate Array Worksheets
l
(3) Computerized Mask Artwork
Generation
t
(4)
Mask Fabrication
N+/Contact/Metal Masks
l
(5) Customizing Pre-Fab Wafers:
Collector Diff./Contact and Metal
I
(6)
Assembly{fest and
Prototype Delivery
defined in the layout example of Figure 6. In this layout, the bipolar I/O cells do not need to be internally interconnected. Since these cells are standardized, it is only necessary for the designer to specify if a particular I/O cell is to be used as an input or an output.
Step 3. Computerized Mask Artwork Generation:
Using a specially developed computerized mask generation technique, the three layers of necessary custom IC tooling {i.e., for custom N-type diffusion, contact window cut; and the metal interconnections) can be automatically generated by a single "digitizing" step from the pencil layout. This simultaneous and automated generation of the three custom mask layers greatly reduces the tooling cost and turnaround time, and avoids mask errors.
Step 4. Mask Fabrication:
The photographic tooling plates, or "masks," are fabricated by a pattern-generation technique from the digitized coordinate information stored in the computer.
Step 5. Customizing Prefabricated Wafers:
The prefabricated I2L wafers containing the P-type base diffusion and the gate "fingers" (see Figure 5) are customized into completed monolithic LSI chips using the custom IC tooling generated in Steps 3 and 4.
Figure 13. Sequence of Steps Associated with a Semi-Custom LSI Development Cycle.
Step 1. Feasibility Review and Logic Conversion:
Starting with the customer's logic diagram (preferably reduced to flip-flops and gates) the first step is a detailed review of the system requirements with regards to the overall gate count, I/O requirements, operating speeds, etc., to assure feasibility of integration, and to choose the most economical gate array chip to be used. If the results of this review indicate feasibility, the next step is to convert the logic diagram into I2L gates. At this state, a computer simulation of the logic diagram may also be performed, if deemed necessary.
Step 2. Pencil Layout on Gate Array Worksheets:
Once the logic diagram is converted to I2L gates, the next step will be to make a pencil layout of the circuit on the appropriate array worksheet. This pencil layout is done on a blank worksheet where the gate input and output locations are shown as target dots (see Figure 5). During the layout, an appropriate symbol is placed over the corresponding dot on the gate outline, and the interconnections and the underpasses between the gates are indicated by pencil lines and with the symbols
Step 6. Assembly/Test and Prototype Delivery:
The completed monolithic chips are first evaluated on the' finished IC wafer, and later assembled, electrically tested and delivered as the completed prototypes.
In many cases, the first two ste.ps indicated in the flow chart of Figure 13, can be done by the customer, in consultation with Exar, using Exar's I2L Design Kit and the design instruction manual. Whenever possible, such an approach is recommended, since it greatly reduces the development costs and the turnaround time.
Typical development cycle containing all the steps outlined in the flow chart of Figure 13, takes about 8 to 12 weeks, depending on the circuit complexity, and whether the customer or Exar does the logic conversion and pencil layout.
Figure 14 shows the photo-micrograph o( a typical semicustom LSI chip, fabricated using the technology outlined in this paper. As indicated in the figure, the use of 3-mask customization step results in an efficient layout and utilization of the available active devices within the I2L gate array.
72
approach more economical for high production volumes. Typical cross-over point between the economics of'the full or semi-custom technology comes about in the quantity range of 50,000 pieces to 150,000 pieces, as implied by the illustration of Figure 15. However, it should be noted that Figure 15 is only a typical "case study," and that the actual cross-over point for a given program will depend on the circuit complexity, performance and test requirements, and the type of IC package used.
Figure 14. Photo-Micrograph of a Typical Semi-Custom I2L LSI Chip.
ECONOMICS OF SEMI-CUSTOM DESIGN
In developing custom LSI circuits, one is confronted by the following key question: for a given production requirement, is it cheaper to develop a full or semi-custom IC? Since the performance and functional requirements of custom IC's vary greatly, there is no general answer to the above question. However, based on the overall production requirements it is possible to establish some economic guidelines for deciding which custom IC technology to use, and when.
One of the main advantages of semi-custom LSI design over conventional full custom IC development is the greatly reduced development cost. This development cost generally amounts to 10% to 30% of that required for a complete custom IC design. However, since the semi-custom design technique tends to waste some of the IC chip area due to random interconnections, the unit price of a semi-custom LSI chip in volume production is slightly higher (approximately 10% to 30%) then a full or complete custom design. Therefore, to decide which is the most economical approach, it is best to compare the estimated amortized unit cost per device for various production quantities. Figure 15 gives such a comparison for a "typical" custom LSI chip, as a function of total production requirement. The total amortized cost per unit is defined as the total cost of the development plus the production purchase, divided by the total number or quantity of units purchased. The extremely high development costs (typically in the range of $50,000 to $100,000) associated with full custom designs make the amortized unit cost of full custom IC's far more expensive than semi-custom designs, at low production quantities. Similarly, for the lower chip cost of full custom !C's make this
1K
10K
100K
1000K
TOTAL QUANTITY OF UNITS PURCHASED
Figure 15. A Comparison of Relative Cost Advantages of SemiCustom and Full Custom LSI Products. (NOTE: Amortized cost per unit includes the development cost.)
CONVERTING SEMI-CUSTOM TO FULL CUSTOM
It is often possible to start a development program using the semi-custom technology, such as the I2L gate arrays described in this paper, and later change to a full custom design when the production quantities increase beyond the cost crossover point illustrated in Figure 15. Such two-phase approach often combines the best advantages of each of the semi- and full custom technologies. For example, the initial development can be done in a semi-custom manner, using Exar's J2L gate arrays, and thus take full advantage of the low tooling cost and the short development cycle. As a customer's product matures and its market expands, resulting in higher volume production run rates, Exar can convert the multiple semi-custom chip approach into a single custom IC, achieving a cost reduction and in many cases a performance improvement. The significant advantage of this type of program is that the risk associated with a custom development is greatly reduced: the IC design approach has been proven, and the design "bugs" are removed at the semi-custom stage thus eliminating the need for lengthy re-design cycles at the full custom level. Once the semi-custom chip is completely characterized in the user's system, and is used for the initial production runs, it can be gradually "phased-out" by a full custom design without interrupting the user's production line.
73
Application Note
AN-17
XR·C409 Monolithic 12L Test Circuit
INTRODUCTION
The XR-C409 monolithic IC is a test circuit for evaluation of speed and performance capabilities of Exar's Integrated Injection Logic (I2L) technology. It is intended to familiarize the I2L user and the digital system designer with some of the performance features of 12L, such as its high-frequency capability and power-speed tradeoffs.
Figure 1 shows the package diagram of the XR-C409 I2L test circuit. It is comprised of five separate evaluation blocks as shown in the figure. Blocks 1 and 2 are D-type flip-flops which are internally connected as frequency dividers. Each of these dividers provide buffered open-collector outputs. Blocks 3, 4, and 5 are 8-stage ring-oscillators with buffered outputs to be used for measuring gate propagation delays at different injector current levels.
FREQUENCY DIVIDER SECTION
The frequency divider sections of XR-C409 test circuits are made up of two D-type flip-flops internally connected in the (+2) mode. These frequency dividers are operated with serial clocking and parallel reset controls.
The internal interconnections of these D-type flip-flop sections are shown in Figure 2. The corresponding package terminals are also identified in the figure. The flip-flops operate on the negative-transitions of the clock input, and reset with the reset at a "high" fogic state. When the circuit is reset, all the outputs go to a "low" state. The logic polarities and the timing sequence of the circuit waveforms are given in Figure 3.
Evaluating the Frequency Divider Section
Figure 4 shows the circuit connection for the frequency divider section of the XR-C409. The recommended clock input level is OV and +IV for the "low" and "high" levels. For optimizing high frequency performance, a square wave clock input is recommended with a source impedance E;;;IOOil.
Biasing of Injectors
All of the 16 J2L gates forming the frequency divider sections are biased by the total injector current, IT, applied to the injector terminal (Pin 1) as shown in Figure 4. The total injector current, IT, applied to the flip-flop sections of XR-C409 is set by the external bias resistor, Ra, as:
y+ _ Vbe
IT= Rs
(1)
where Ybe (~0.7V) is the transistor base-emitter voltage drop.
The total injector current ,IT, is shated amoung 16 individual I2L gates forming the frequency-divider sections. Thus, the operating current of each gate, Ij, is equal to 1/16 of the total injector bias, or:
Ij = IT/16
(2)
INJECTOR A
r2 40UTPUTS
03
INJECTOR B
OSCILLATOR OUTPUT
INJECTOR C
OSCILLATOR OUTPUT GROUND !SUBSTRATE)
CLOCK INPUT
RESET
( 2) OUTPUT
01 N.C.
N.C.
N.C. OSCILLATOR OUTPUT INJECTOR D
Figure 1. Package Terminals for XR-C409 Test IC.
INJECTOR
. - - - - - - - - 0 2 + OUTPUT 14
D
0
0
0
CLOCK INPUT
(1)
(2)
Ck R
a 1------ Ck R
a
RESET 15
Figure 2. Block Diagram of Frequency Divider Section.
74
CLOCK INPUT (PIN 161
r - RE
(PIN
SE 151
T
-
--
,!.__
_
_
_
_
_
_
_
_
_
_
_
_ ____,!
+ 20UTPUT
(PIN 141
___ + 4 OUTPUTS
(PINS 2 AND 31
__.
Figure 3. Timing Diagram for Frequency Divider Section.
v+ 5V~--.......- - - - - ,
+IT Rs
·~:JlJL JOOco 16
CL K INPUT 0--'VV\r-<>-t DISABLE
:1~
ENABLE
Dl =LOW CAPACITANCE CLAMP DIODE
Figure 4. Test Circuit for Frequency Divider Section.
M~asuring Output Waveforms
Each of the output terminals of XR-C409 frequency-divider are open-collector type terminals which require a pull-up resistor to positive supply voltage. Thus, the output risetime is limited by the external RC time constant due to the load resistance, RL, and the parasitic and/or load capacitance, CL.
Figure 5 shows a recommended circuit connection to test the output swing at high frequencies, using a low-capacitance clamp-diode, 0 1 , to clamp the output swing to ::::::+o. 7V above ground.
v·
OUTPUT
Dl =CLAMP DIODE
Figure 5. Recommended External Connections to Measure Output Waveforms.
The value of the load resistor, RL, is determined by the current sinking capability of the output transistor, T 1 , internal to the chip. Since T 1 is the output of an 12 L gate, its worst case sinking current is limited to the individual gate current, i.e.:
(3)
This current-sinking capability in tum limits the minimum value of load resistance RL to:
(4)
The peak output swing is limited to approximately 3 volts due to the collector-base breakdown of the I2L gate output, i.e., transistor T 1 of Figure 5.
High Frequency Capability
The maximum operating frequency of I2L frequency-divider circuits is a function of the total injector current. For lowcurrent operation, the maximum toggle-frequency of the flip-flops forming the frequency-divider section increases
lOMHzr----...,.-----,------,----..,-------,
u >
§ ~ IMHzl---~~~-1-~~~-+~~--J~f--~~~-+--~~~---J
~ 500
~
"g 200
....
~ 100kHzl---~~~-l-~,,,_~-+~~~~f--~~~-+--~~~---j
x:!:
50
<
:!:
20
lOkHz L-...J.--'---...L-'--...J.-....J..-L--'--'---'--'---'--'---'---'
O.lµA
lµA
10µA
100µA
lmA
lOmA
TOTAL INJECTOR CURRENT, IT. APPLIED TO PIN 1116 GATES!
Figure 6. Typical Maximum Toggle Frequency vs. Injector Current Characteristics for XR-C409 Frequency Divider Section.
(NOTE: Clock Input: 1 Vp-p Square Wave)
linearly with increasing injector current. Typical maximum toggle frequency vs. injector current characteristics are shown in Figure 6. Note that the maximum toggle-rate obtainable is in the range of 3 to 5 MHz, at a total injector current level of 1 to 2 mA, which corresponds to individual injector currents of approximately 60µA to l 20µA per gate.
RING-OSCILLATOR SECTIONS
The ring-oscillator sections of XR-C409 test circuit are intended for measurement of propagation delays associated with I2L gates. Each of these oscillators are made up of a cascade of 8 four-output I2L gates. Figure 7(a) shows the basic electrical equivalent circuit of a four-output I2L gate. Its corresponding logic symbol is shown in Figure 7(b). The basic gate operates as an inverter with single input and four outputs.
75
INJECTOR
INPUTS (COMMON)
1}~ OUTPUTS INPUTS~:} 4
1 OUTPUTS
EQUIVALENT CIRCUIT
LOGIC SYMBOL
Figure 7. Four-Output I2L Gate.
The propagation delay through an 12L gate depends on the following sets of parameters:
1. Device design: (i.e., manufacturing methods and device layout used in fabrication process).
2. Injector current level: (gate switching speed increases with increasing current, until a maximum is reached).
3. Choice of outputs used: (the output closest to the injector has minimum propagation delay at high currents).
4. Number of outputs used: (if fewer outputs are used and the unused outputs left open, the gate delay is Lower at low currents. However, at high currents, i.e., lj ~ 1OOµA/gate, gates with fewer outputs left unused show lower delays. This is due to excess storage-time effects due to open-circuited gate outputs. See Figure 10.)
Figure 8 shows the basic seven-stage ring-oscillator circuits included on the XR-C409 chip to evaluate the propagation delay characteristics of 12L gates. Since the delay characteristics depend on the choice and the number of gate outputs used, the test IC includes three separate ring oscillator sections. The ring oscillator of Figure 8(a) corresponds to section (3) in the package diagram of XR-C409 shown in Figure 1. This oscillator uses only one gate-output per gate. The output used is the one closest to the injector, with the remaining outputs left open-circuited.
The ring-oscillator of Figure 8(b) uses two gate outputs per stage. The outputs used are the two closest to the injector. The ring oscillator of Figure 8(c) has all four outputs shorted together.
All three oscillator sections of XR-C409 have separate injectors, but share a common ground (pin 8). Each oscillator also has a separate output buffer stage.
Figure 9 shows a recommended test circuit for evaluating gate delay vs. gate current characteristics using the ring oscillator sections of XR-C409. Since each ring-oscillator section is comprised of 8 gates, the actual injector current per gate, Ij, is 1/8 of the total injector current, IT,:
IT
Ij =injector current/gate= g
(5)
The total injector current, IT, is determined by the external bias resistor, Rs, as given by equation(!).
IPIN 41 INJECTOR (PIN SJ OSCILLATOR r---,__,,,n-~--0 OUTPUT
PIN B !al
Ring Oscillator Using Single Gate Output per Stage (Section 3)
!PIN 9) INJECTOR
(PIN 101 OSCILLATOR
n--r-+--0 OUTPUT
PIN 8 (bl
Ring Oscillator Using Two Gate-Outputs per Stage (Section 5)
PIN 8
IPIN 61 INJECTOR
i
Id
(PIN 71
n--,--+--O
OSCILLATOR OUTPUT
Ring Oscillator Using Four Gate-Outputs per Stage (Section 4)
Figure 8. Equivalent Circuits of the 7-Stage Ring Oscillator Section.
r v+
INJECTOR (PINS 4, 6,_OR .9.1..._ . . , (PINS5, 7.
OR 101
GROUND (PIN 81
I CL ...._
I
D1 =LOW CAPACITANCE CLAMP DIODE
Figure 9. Recommended Test Circuit for Evaluating PowerDelay Characteristics of 12L Gates Using Ring Oscillator Sec-
tions of XR-C409.
76
Measuring Output Waveforms
The output terminals of XR-C409 ring counter sections are open-collector type terminals, similar to the outputs of the frequency divider sections. Thus, the outputs require pull-up resistors to the positive supply voltage. The output rise-time is strongly affected by the external RC time constant due to. the load resistance, RL, and the parasitic load Cl!pacitance, CL. In the test circuit of Figure 9, a low-capacitance clamp diode, 0 1 is used to limit the output swing and thus minimize the slow rise-time effects.
For the case of the 7-stage oscillator circuits in the XR-C409 test chip, Td can be calculated from equation (8) by setting N=7.
Figure 10 shows the typical gate-delay vs. injector current characteristics measured from the three ring-oscillator sections of XR-C409. In the figure, the gate delay is plotted as a function of the injector current per gate. The gate geometry layout of XR-C409 ring-oscillator sections is not optimized for high frequency operation.
The minimum value of load resistance, RL, is determined by the current sinking capability of the output 12L gate. For proper operation of the ring-oscillator circuits, the load current, IL, should be limited to:
(6)
which limits the output load resistance, RL. for ring-oscillator sections to:
(7)
Calculating Propagation Delays
The average propagation delay Td per gate can be calculated from the ring oscillator frequency, f0 as:
1
Td = 2Nf0 sec
(8)
where N is the number of stages in the ring oscillator.
1011s---------~----~-----
...
,.:
~ 1µsf----~~.------f-----+-------j
Q
~ ~
500
..0: 200
a:
SECTION 3 IONEOUTPUT/GATEI
~100nst-------1-----f""'il:~----+-----f
ffi
:; 50
20
10ns ....__..__ .1µA
SECTION 4 (4 OUTPUTS/GATE)
_._~..___.__...___._...__~__..-~_...__,
1µA
lOµA
100µA
lmA
INJECTOR CURRENT PER GATE. 11
Figure 10. Typical Propagation Delay vs. Injector Current Characteristics as Measured from 7-Stage Ring Oscillator Section of XR-C409.
77
QUALITY ASSURANCE STANDARDS
The quality assurance program at Exar Integrated Systems defines and establishes standards and controls on manufacturing, and audits product quality at critical points during manufacturing.The accompanying Manufacturing/QA process flows illustrate where quality assurance audits, by inspection or test, the manufacturing process. The insertion of these quality assurance points is designed to insure the highest quality standards are maintained on Exar product during its manufacture.
Realizing that these standard Manufacturing/QA process flows do not meet the needs of every customer's specific requirements, Exar quality assurance can negotiate and will screen product to meet any individual customer's specific requirement.
All products ending with the suffix M are fully screened to the requirements of MIL-STD-883, Method 5004, Condition C.
Wafer Fabrication/QA Flow
Polished Silicon Slices
Masks
Materials
Per Applicable
Per Applicable
Procurement
QC
MQCl's
...._.....,~_.Specification, MOCl's .....__,,_ _,
-eMQCl's
Visual Inspection for Dirt, Contamination, etc.
Verify Layer Thickness and Resistivity, Inspect !or Stacking Faults, etc.
Visual Inspection to Verify Proper Mask, Check Alignment, Undercutting, Proper Oxide Removal, etc.
S.E.M. Analysis
Individual Wafer S.E.M. Analysis (optional for high reliability military programs only)
Waler probe 100% probe AC, DC, and Functional Testing
Move to Assa";::;;;;-1 QC
i
High Reliability Aasambly 1
Die Sort Yield Analysis (optional, !or high rallabillly military programs only)
Cerdlp Assambly
2
Plastic Aasambly 3
High Reliability Assembly/QA Flow
Initiate Serialized Loi Traveler to Maintain Traceablllty Back to Silicon Manufacturing
Wafer Saw
Break/Plate Dice
e - Monitor Temperature
Settings, Pick-up
QA
Tools, Operator Audit,
Exar OCI 2007
Monitor Bond Pulls, & - A Power Settings, Operator Audit Exar QCI 2006/2008
Per Mll-Std-883, Method 201 OB. ...__ __. Latest Revision
Die/Frame Attach
Per Mil-Std-883, Method 2010B. Latest Revision
Wire Bond
Per Mil-Std-833, Method 201 O B. ....__ __. (Precap Visual Inspection)
Furnace Certification
QCI 2002
&-
e-----i Seal Strength, Monitor
per Exar
@--
Seal
Tin Plate Leads 150 Micro Inch Minimum
Lead Trim
Stabilization Bake, Mil-Std-883, Method 1008C.
Temperature Cycle Mil-Std-883, Method 1010C.
Constant Acceleration, Mil-Sld-883, Method 2001 E, Y1 axis.
Fine Leak, Mil-Std-883, Method 1014A or B.
Gross Leak, Mll-Std-883, Method 1014C, Step 1.
AC, DC and Functional Tests to Data Sheet Parameters .65% AOL
Production Electrical Test, AC, DC, Functional Tests.
To further environmental - - - - - - 1
preconditioning,
screening, burn-in per
individual customer requirements.
Mark - Applicable Marking and Date Code
Lot Acceptance, verify
product type, count
package, completion of all ...__ __. process requirements.
SHIP
Verify required documentation. QCI 3001
78
Cerdip Assembly/QA Flow
Plastic Assembly/QA Flow
e-- 100% Exar OCI 2004
QCI 200112006 Monitor Temperature ~
Setting, Bond Pull. ~
Machine Certification
{
Scribe/Break/Plate
Optical Inspection per Exar QCI 2004 (Mil-Std-883, Method 2010 Condition B modified)
Die/frame Attach
Wire Bond
100%Exar OCI 2007. 2008
~ ~
@ - Furnace Certification
'----r--'
Optical Inspection per Exar QCI 200112008 (Mil-Std-883 Method 2010 Condition B Modified)
Seal CCI 2002
I::'\___ Monitor Seal Strength~
Per Exar QCI 2002
Tin Pl11te
Trim Fine Leak. 5 x 1O 7 cc/sec
CTI 3000 AC, DC Functional Test Data Sheet Parameter .65% AOL
Gross Leak. Bubble Test
Stabilization Bake. 150 C, 24 hrs. min., 100%
Production Testing, AC. DC. and Functional Test at 25 C. Marking - Applicable Marking and Date Code
Lot Acceptance QTI 3001
Ship
PRODUCT ORDERING INFORMATION
Part Identification
XR
Manufacturer's Prefix Grade M Military N Prime
Electrical P Prime
Electrical C Commercial K Kit
xxxxx
Basic Type (5 spaces)
Package Type N Ceramic Dual-in-line P = Plastic Dual-in-line
Manufacturer's Prefix
Example:
XR-2216 CN
~~
Basic Type
Grade
Package Type
e-- 100% Exar QCI 2004
e Visual Monitor
Temperature Setting QCI 200112006 Bond Pull Machine
{
Certification
@ - 100% Exar QCI
200712008
Scribe1BreakJPlate
Optical Inspection per Exar CCI 2004 (Mil-Std-883, Method 2010 Condition 8 Modified)
Die Bond
Wire Bond
Optical Inspection per Exar OCI 200712008 (Mil-Std-883, Method 2010 Condition B modified)
Seal
Monitor Marking Permanency
Hot Open Testing al +85 C
QTI 3000 AC, DC Functional Test Data Sheet Parameters .65% AOL
Mil-Std-883 Latest Rev.
Tin Plate
Oeflash. Trim. Form leads
Solder Dip
Stabilization Bake 150 C. 24 hrs. min. Mark - Applicable Marking and Date Code
100°10 Production Test AC. DC and Functional Test at 25 C
Lot Acceptance QTI 3001 Ship
Definition of Symbols:
M
Military Grade Part, Ceramic Package Only.
All Military Grades have been processed to MIL-STD-883
Level C, and are guaranteed to operate over military
temperture range.
N
Prime Grade Part, Ceramic Package.
P
Prime Grade Part, Plastic Package.
CN Commercial Grade Part, Ceramic Package.
CP Commercial Grade Part, Plastic Package.
N, P, CN and CP parts are electrically identical and guaranteed to
operate over 0°C to + 75°C range unless otherwise stated. In
addition, N and P parts generally have operating parameters more tightly controlled than the CN or CP parts.
For details, consult Exar Sales Headquarters or Sales /Technical Representatives.
Legend:
CJ Surveillance Q Operation
L J 100% inspection
QC = Quality Control M = Manufacturing
79
INTERNATIONAL SALES OFFICES AND REPRESENTATIVES
ARGENTINA Rayo Electronics SRL Belgrando 990 Pisos 6Y2 Phone: 37 98 90 Telex: (390) 122153 (RAYOX AR)
AUSTRALIA Total Electronics 31 O Queen St. Melbourne G.P.O. Box 1286K Melbourne, 3001 Phone: 67 9306 Telex (790) 31261 (TOTE LEC AA)
BELGIUM (See Germany)
BRASIL R.Ohm Do Brasil lndustria Electronica Ltda. Av. Dom Pedro I, 420 01552 Sao Paulo Telex: (391) 1121178 (UIEL BR)
DENMARK Mer-el A/S Ved Klmdebo 18 DK-2970 H!Zlrsholm Phone: 571000 Telex: (855) 37360 (MEREL DK)
FINLAND Y leiselektroniikka/oy Atomitie 5B 00370 Helsinki 37 Phone: 90-562 1122 Telex: 123212 (YLEOY SF)
FRANCE Tekelec/ Airtronic Rue Carle Vernet F-9231 O Sevres Phone: (1) 534 75 35 Telex: (842) 204552 (TKLEC A)
GERMANY (WEST) R.Ohm Electronics GmbH D-4051 Korschenbroich Muehlenstrasse 70 Phone: (02161) 29 805 Telex: (841) 852330 (ROHM D)
GREECE General Electronics Ltd. 209 Thevon Street Nikaia 77, Piraeus Phone: 49 13 595 Telex: (863) 212949 (GELT GR)
HONG KONG R.Ohm Electronics (H.K.) Co., Ltd. Rm 1027A, Ocean Centre 5, Canton Road, Tsimshatsui, Kowloon Phone: 3-688841 /3-672307 Telex: (780) 37503 (REHCL HX)
INDIA Zenith Electronics 541 Panchratna Mama Parmanand Marg Bombay 400004 Phone: 38 42 14 Telex: (953) 11 3152 (ZNTH IN)
ISRAEL CVS Technologies 1974 Ltd. 54 Jabotinsk y Str. Ramat-Gan 52462 Phone: 330190 Telex: (922) 341363 (MEIS IL)
ITALY E led ra 3S S.p.A. Viale Elvezia, 18 20154 Milano Phone: 34.93.041 Telex: (843) 332332 (ELEDRA I)
JAPAN Tokyo Electron Ltd. Panetron Division 38 FL Shinjuku Nomura Bldg. 1-26-2, N ishi-Shinjuku Shinjuku-ku, Tokyo 160 Phone: 03-343-4411 Telex: (781) 2322240 (LABTEL J)
LIECHTENSTEIN (See Switzerland)
LUXEMBOURG (See Germany)
NETHERLANDS Tekelec/Airtran ic B. V. Stork Staat 7 2722 NN Zoetermeer Phone: 079-310100 Telex: (844) 33332 (TKLEC NL)
NEW ZEALAND Professional Electronics Ltd. 126 Kitchener Road Milford, Auckland 9 Phone: 46 94 50 Telex: (791) 21084 (PROTON)
NORWAY Hefro Teknisk A/S Trondheimsveier 80 Oslo 5 Phone: 38 02 86 Telex: (856) 16205 (HEFRO N)
SINGAPORE Rohm Electronics Co. Pte. Ltd. Unit G, Third Floor Cheng Chwee Huat Ind. Bldg. 118-D, Paya Lebar Road Singapore 1440 Phone: 2834327 Telex: (786) 26648 (ROHM S)
SOUTH AFRICA South Continental Devices (Pty.) Ltd. Suite 516, 5th Floor, Randover House Car. Hendrik Verwoerd, Dover Road Randburg, Transvaal Phone: 48 05 15 Telex: (960) 4-24849 (SA)
SPAIN Unitronics, S. A. Princesa, 1 Madrid 8, Phone: 242 52-04 Telex: (831) 46786 (UTRON E)
SWEDEN Lagercrantz Electronix AB Kanalvagen 5 S-194 01 Upplands Vasby Phone: (0760) 86 120 Telex: (854) 11275 (LAGERS)
SWITZERLAND Amera Electronics AG Lerchenhaldenstrasse 73 CH-8046 Zurich Phone: (01) 57 11 12 Telex: (845) 59837 (AME RA CH)
TAIWAN (See Hong Kong)
UNITED KINGDOM Thame Components Thame Park Road Thame, Oxon OX9 3RS Phone: (084 421) 3146 Telex: (851) 837917 (MEMEC G)
LATIN AMERICA I ntectra 2349 Charleston Road Mt. View, CA 94043 U.S.A. Phone: (415) 967-8818 Telex: 345545 (INTECTRA MNTV)
ALL OTHER COUNTRIES (Call Exar Direct)
June 1981
80
AUTHORIZED STOCKING DISTRIBUTORS
ALABAMA Resisticap, Inc. Huntsville (205) 881-9270
ARIZONA Sterling Electronics Phoenix (602) 258-4531
ARKANSAS (See Oklahoma)
CALIFORNIA Anthem Electronics San Diego (714) 279-5200
Anthem Electronics San Jose (408) 946-8000
Anthem Electronics Tustin (714) 730-8000
Bell Industries Sunnyvale (408) 734-8570
JACO Chatsworth (213) 998-2200
VSI Electronics (USA) Inc.
Santa Ana (213) 299-7760
Zeus VIiest, Inc. Anaheim (714) 632-6880
COLORADO Bell Industries Wheat ridge (303) 424-1985
Diplomat Electronics Denver (303) 427-5544
CONNECTICUT Diplomat Electronics Danbury (203) 797-9674
JV Electronics, Inc. East Haven (203) 469-2321
DELAWARE (See Pennsylvania)
FLORIDA Diplomat Southland Clearwater (813) 443-4514
Diplomat Southland Ft. Lauderdale (305) 971-7160
FLORIDA (Continued) Diplomat Southland Palm Bay (305) 725-4520
GEORGIA (See Florida)
IDAHO (See Washington)
ILLINOIS Diplomat Electronics Bensenville (312) 595-1000
R.M. Electronics Lombard (312) 932-5150
IN DIANA Graham Electronics Indianapolis (317) 634-8202
R.M. Electronics Indianapolis (317) 247-9701
IOWA DEECO, Incorporated Cedar Rapids (319) 365-7551
KANSAS Component Specialties Lenexa (913) 492-3555
KENTUCKY (See Indiana)
LOUSIANA (See Texas)
MAINE (See New Hampshire)
MARYLAND Diplomat Electronics Columbia (301) 995-1226
Pioneer Electronics Gaithersburg (301) 948-0710
MASSACHUSETTS Diplomat Electronics Holliston (617) 429-4121
Gerber Electronics Norwood (617) 329-2400
RC Components Wilmington (617) 657-4310
MICHIGAN Camelot Electronics Livonia (313) 591-0055
Diplomat Electronics Fannington (313) 477-3200
R.M. Electronics Grand Rapids (616) 531-9300
MINNESOTA Diplomat Electronics Minneapolis (512) 788-8601
MISSISSIPPI (See Alabama)
MISSOURI Olive Industrial Elect. St. Louis (314) 426-4500
MONTANA (Call Exar Direct)
NEVADA (See California)
NEW HAMPSHIRE Yankee Electric Supply Manchester (603) 625-9746
NEW JERSEY Diplomat Elecronics Mount Laurel (609) 234-8080
Diplomat Electronics Totowa (201) 785-1830
NEW MEXICO Bell Industries Albuquerque (505) 292-2700
NEW YORK Diplomat Electronics 4610 Wetzel Road Liverpool, NY 13088 (315) 652-5000
Diplomat Electronics Melville (516) 454-6400
JACO Hauppauge (516) 273-5500
Zeus Components, Inc. Elmsford (914) 592-4120
NORTH CAROLINA (See Maryland)
NORTH DAKOTA (Call Exar Direct)
OHIO Graham Electronics Cincinnati (513) 772-1661
OKLAHOMA Component Specialties Tulsa (918) 664-2820
Radio, Inc. Tulsa (918) 587-9123
Quality Components Tulsa (918) 664-8812
OREGON Radar Electric Co., Inc. Portland (503) 233-3691
PENNSYLVANIA Advacom Erie (814) 476-7774
Pioneer Electronics Horsham (215) 674-4000
RHODE ISLAND (See Massachusetts)
SOUTH CAROLINA (See Maryland)
SOUTH DAKOTA (Call Exar Direct)
TENNESSEE (See Alabama)
TEXAS Component Specialties Austin (512) 837-8922
Component Specialties Dallas (214) 357-6511
Component Specialties Houston (713) 771-7237
Quality Components Addison (214) 387-4949
Quality Components Austin (512) 835-0220
Quality Components Houston (713) 772-7100
UTAH Bell Industries Salt Lake City (801) 972-6969
Diplomat Electronics Salt Lake City (801) 486-4134
VERMONT (See New Hampshire)
VIRGINIA (see Maryland)
WASHINGTON Radar Electric Co., Inc. Seattle (206) 282-2511
Vllestern Electromotive Seattle (206) 575-1910
WISCONSIN Taylor Electric Co. Mequon (414) 241-4321
WYOMING (See Colorado)
CANADA Future Electronics Montreal, Quebec (514) 731-7441
lntek Electronics Ltd. Vancouver, B.C. (604) 324-6831
R-A-E Industrial Elect. Burnaby, B.C. (604) 291-8866
Cam Gard Supply Ltd. Calgary, Alberta (403) 287-0520
Cam Gard Supply Ltd. Saskatoon,
Saskatchewan (306) 652-6424
Cam Gard Supply Ltd. Toronto, Ontario (416) 252-5031
Cam Gard Supply Ltd. Vancouver, B.C. (604) 291-1441
Cam Gard Supply Ltd. Winnipeg, Manitoba (204) 786-8401
AUTHORIZED REP RESENTATIVES
ALABAMA Re p, Incorporated 11527 S. Memorial
Parkway Hu ntsville , AL 35803 (205) 881-9270 TVVX 8 10-726-2102
ALASKA (Call Exar Direct)
ARIZONA Summit Sales 7336 E. Shoeman Lane Suite 116E Scottsdale, AZ 85251 (502) 994-4587 TVVX 910-950-1283
ARKANSAS (See Oklahoma)
CALIFORNIA (NO.) Criterion 3350 Scott Blvd .
Bldg. 44 Santa Clara. CA 95051 (408) 988 -6300 TVV X 910-338-7352
CALIFORNIA (SO.) Varigon Associates 137 Eucalyptus Drive El Segundo. CA 90245 (213) 322-1120 TVVX 910-348-7141
Varigon/ ARC 2356 Moore St. .
Suite 102 San D iego, CA 921 10 (714) 299-5413
COLORADO Waugaman Assoc., Inc. 4800 Van Gordon St. W heatridge . CO 80033 (303) 423-1020 TVVX 910-938-0750
CONNECTICUT Phoenix Sales 389 M ain Street Ridgefield. CT 06877 (203) 438-9644 TVVX 7 10-467-0662
DELAWARE (See M ary land)
FLORIDA Donato & Assoc., Inc. 2660 West Oakland
Park Blvd. Suite210 Ft. Lauderdale, FL
33311 (305) 733-3450 TVVX 510-955-9789
GEORGIA Rep, Incorporated 1944 Cooledge Road Tucker, GA 30084 (404) 938-4358
HAWAII (Call Exar Direct)
IDAHO (See Washington)
ILLINOIS (NORTH) Janus. Incorporated 3 166 Des Plaines Ave. Suite 14 Des Plaines , IL 60018 (312) 298-9330
ILLINOIS (SOUTH) (See Missouri)
INDIANA (See Ohio)
IOWA Dytronix. Inc. 23 Twixt Town Road
N o rt h e a st Suite 20 1 Cedar Rapids, IA 52402 (319) 377-8275
KANSAS (See Missouri)
KENTUCKY (See Ohio)
LOUSIANA (See Texas)
MAINE (See Massachusetts)
MARYLAND Component Sales, Inc. 3701 Old Court Rd . Suite 14 Baltimore, MD 21208 (301) 484-3647 TWX 710-862-0852
MASSACHUSETTS Contact Sales. Inc. 101 Cambridge Street Burlington. MA 01803 (617) 273-1520 TWX 710-332-6569
MICHIGAN (See Ohio)
MINNESOTA Dan '! Engineering 12350 W. 175th St. Lakeville, MN 55044 (6 12) 435-6000
MISSISSIPPI (See Alabama)
MISSOURI Dy-Tronix. Inc. 11190 Natural Bridge Bridgeton, MO 63044 (314) 731-5799 TWX 910-762-0651
Dy-Tronix, Inc. 13700 E. 42nd Terrace Suite 202 lndepedence, MO 64055 (816) 373-6600
MONTANA (See Colorado)
NEBRASKA (See Missouri)
NEVADA (See California No.)
NEW HAMPSHIRE (See Massachusetts)
NEW MEXICO Syntech 302C San Pablo S.E. Albuquerque , NM 87108 (505) 266-7951
NEW JERSEY (NO.) (See New York City)
NEW JERSEY (SO.) (See Pennsylvania)
NEW YORK (UPSTATE)
Q uality Components 2095 Kensington Ave . Buffalo. NY 14226 (716) 839-4 170
Quality Components 116 E. Fayette St. Manlius, NY 13104 (3 15) 682-8885 TWX 710-545-0663
NEW YORK (CITY) ERA, Incorporated 254 Veterans
Memori al Hwy. Commack, NY 11725 (516) 543-0510 In NJ : 800-645-5500 / 1 TVVX 510-226- 1485
NORTH CAROLINA Component Sales, Inc. P.O . Box 18821 Raleigh, NC 27619 (919) 782-8433 TWX 510-928-05 13
NORTH DAKOTA (See Minnesota)
OHIO McFadden Sales 4645 Executive Drive Columbus, OH 43220 (614) 459- 1280 TVVX 810-482- 1623
OKL AHOMA Technical Marketing 9717 East 42nd St. Suite 210 Tulsa, OK 74145 (918) 622-5984
OREGON (See Washington)
PENNSYLVANIA (WEST)
(See Ohio)
PENNSYLVANIA (EAST)
Vantage Sales Company 21 Bala Avenue B ala Cynwyd , PA 19004 (2 15) 667-0990 TVVX 510-662-5846
RHODE ISLAND (See Massach usetts)
SOUTH CAROLINA (See North Carolina)
SOUTH DAKOTA (See Minnesota)
T ENNESSEE Rep. Incorporated 113 S. Branner Ave. Jefferson C ity. TN
37760 (615) 475-4105 TVV X 810-570-4203
TEXAS Technical Marketing 9027 North gate Blvd. Suite 140 Austin. TX 78758 (512) 835-0064
Technical Marketing 3320 Wiley Post Road Carrollton . TX 75006 (2 14) 387-3601 TVVX 910-860-5158
Technical Marketing 6430 Hillcroft
Suite 104 Houston, TX 77081 (713) 777-9228
Ye
EXAR
EXAR INTEGRATED SYSTEMS, INC.
7 50 P a lomar Avenue. Sunnyvale. CA 94088
(4 081 7 32 -7970 TWX 910-339 -9233
UTAH SK Component Sales 2520 S. State Salt Lake City, UT 84 11 5 (801) 484-4222
VERMONT (See Massachusetts)
VIRGINIA (See Maryland)
WASHINGTON SD-R2 Products & Sales 14042 NE 8th Street Suite 201 Bellevue, WA 98007 (206) 747-9424 TWX 910-443-2483
WASHINGTON, D.C. (See Maryland)
WEST VIRGINIA (See Ohio)
WISCONSIN (S. EAST) Janus Inc. 1200 W. Sierra Lane
#3 Mequon, WI 53092 (41 4) 24 1-8052
WISCONSIN (WEST) (See Minnesota)
WYOMING (See Colorado)
CANADA (EAST) R.F.Q. Limited 385 The West Mall Suite 209 Etobicoke , Ontario M9C 1E7 (416) 626- 1445 TVVX 610-492-2540 R.F.Q. Limited 2249 Carling Avenue Suite204 Ottawa, Ontario
K2B 7E9 (613) 820-8445/ 8446 TWX 61 0-562-1973
June 1981
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