Zynq UltraScale MPSoC Product Tables and Product Selection Guide
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Zynq UltraScale MPSoC Product Tables and Product Selection Guide
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� Copyright 2016�2021 Xilinx Zynq� UltraScale+TM MPSoCs Page 2 Application Processor Real-Time Processor Graphics Processor Video Codec Programmable Logic Applications CG Devices Dual-core Arm� Cortex�-A53 MPCoreTM up to 1.3GHz Dual-core Arm Cortex-R5F MPCore up to 533MHz EG Devices Quad-core Arm Cortex-A53 MPCore up to 1.5GHz Dual-core ARM Cortex-R5 MPCore up to 600MHz MaliTM-400 MP2 EV Devices Quad-core Arm Cortex-A53 MPCore up to 1.5GHz Dual-core ARM Cortex-R5 MPCore up to 600MHz MaliTM-400 MP2 H.264 / H.265 81K�600K System Logic Cells 81K�1143K System Logic Cells � Sensor Processing & Fusion � Motor Control � Low-cost Ultrasound � Traffic Engineering � Flight Navigation � Missile & Munitions � Military Construction � Secure Solutions � Networking � Cloud Computing Security � Data Center � Machine Vision � Medical Endoscopy � Copyright 2016�2021 Xilinx 192K�504K System Logic Cells � Situational Awareness � Surveillance/Reconnaissance � Smart Vision � Image Manipulation � Graphic Overlay � Human Machine Interface � Automotive ADAS � Video Processing � Interactive Display XMP104 (v2.5.1) Zynq� UltraScale+TM MPSoCs: CG Devices Programmable Logic (PL) Processing System (PS) Application Processor Unit Real-Time Processor Unit External Memory Connectivity Integrated Block Functionality PS to PL Interface Programmable Functionality Memory Clocking Integrated IP Transceivers Speed Grades Device Name(1) Processor Core Memory w/ECC Processor Core Memory w/ECC Dynamic Memory Interface Static Memory Interfaces High-Speed Connectivity General Connectivity Power Management Security AMS - System Monitor System Logic Cells (K) CLB Flip-Flops (K) CLB LUTs (K) Max. Distributed RAM (Mb) Total Block RAM (Mb) UltraRAM (Mb) Clock Management Tiles (CMTs) DSP Slices PCI Express� Gen 3x16 150G Interlaken 100G Ethernet MAC/PCS w/RS-FEC AMS - System Monitor GTH 16.3Gb/s Transceivers GTY 32.75Gb/s Transceivers Extended(2) Industrial ZU1CG 81 74 37 1.0 3.8 3 216 1 - Notes: 1. For full part number details, see the Ordering Information section in DS891, Zynq UltraScale+ MPSoC Overview. 2.-2LE (Tj = 0�C to 110�C). For more details, see the Ordering Information section in DS891, Zynq UltraScale+ MPSoC Overview. Page 3 ZU2CG 103 94 47 1.2 5.3 3 240 1 - ZU3CG ZU4CG ZU5CG ZU6CG Dual-core Arm� Cortex�-A53 MPCoreTM up to 1.3GHz L1 Cache 32KB I / D per core, L2 Cache 1MB, on-chip Memory 256KB Dual-core Arm Cortex-R5F MPCore up to 533MHz L1 Cache 32KB I / D per core, Tightly Coupled Memory 128KB per core x16: DDR4 w/o ECC; x32/x64: DDR4, LPDDR4, DDR3, DDR3L, LPDDR3 w/ ECC NAND, 2x Quad-SPI PCIe� Gen2 x4, 2x USB3.0, SATA 3.1, DisplayPort, 4x Tri-mode Gigabit Ethernet 2xUSB 2.0, 2x SD/SDIO, 2x UART, 2x CAN 2.0B, 2x I2C, 2x SPI, 4x 32b GPIO Full / Low / PL / Battery Power Domains RSA, AES, and SHA 10-bit, 1MSPS � Temperature and Voltage Monitor 12 x 32/64/128b AXI Ports 154 192 256 469 141 176 234 429 71 88 117 215 1.8 2.6 3.5 6.9 7.6 4.5 5.1 25.1 - 13.5 18.0 - 3 4 4 4 360 728 1,248 1,973 - 2 2 - - - - - - - - - 1 1 1 1 - 16 16 24 - - - - -1 -2 -2L -1 -1L -2 ZU7CG 504 461 230 6.2 11.0 27.0 8 1,728 2 1 24 - ZU9CG 600 548 274 8.8 32.1 4 2,520 1 24 - � Copyright 2016�2021 Xilinx XMP104 (v2.5.1) Zynq� UltraScale+TM MPSoCs: EG Devices Programmable Logic (PL) Processing System (PS) Application Processor Unit Real-Time Processor Unit Graphic & Video Acceleration External Memory Connectivity Integrated Block Functionality PS to PL Interface Programmable Functionality Memory Clocking Integrated IP Transceivers Speed Grades Device Name(1) Processor Core Memory w/ECC Processor Core Memory w/ECC Graphics Processing Unit Memory Dynamic Memory Interface Static Memory Interfaces High-Speed Connectivity General Connectivity Power Management Security AMS - System Monitor ZU1EG System Logic Cells (K) 81 CLB Flip-Flops (K) 74 CLB LUTs (K) 37 Max. Distributed RAM (Mb) 1.0 Total Block RAM (Mb) 3.8 UltraRAM (Mb) - Clock Management Tiles (CMTs) 3 DSP Slices 216 PCI Express� Gen 3x16 150G Interlaken - 100G Ethernet MAC/PCS w/RS-FEC AMS - System Monitor 1 GTH 16.3Gb/s Transceivers GTY 32.75Gb/s Transceivers - Extended(2) Industrial Notes: 1. For full part number details, see the Ordering Information section in DS891, Zynq UltraScale+ MPSoC Overview. 2.-2LE (Tj = 0�C to 110�C). For more details, see the Ordering Information section in DS891, Zynq UltraScale+ MPSoC Overview. Page 4 ZU2EG 103 94 47 1.2 5.3 3 240 1 -1 -2 -2L ZU3EG ZU4EG ZU5EG ZU6EG ZU7EG ZU9EG ZU11EG ZU15EG Quad-core Arm� Cortex�-A53 MPCoreTM up to 1.5GHz L1 Cache 32KB I / D per core, L2 Cache 1MB, on-chip Memory 256KB Dual-core Arm Cortex-R5F MPCoreTM up to 600MHz L1 Cache 32KB I / D per core, Tightly Coupled Memory 128KB per core MaliTM-400 MP2 up to 667MHz L2 Cache 64KB x16: DDR4 w/o ECC; x32/x64: DDR4, LPDDR4, DDR3, DDR3L, LPDDR3 w/ ECC NAND, 2x Quad-SPI PCIe� Gen2 x4, 2x USB3.0, SATA 3.1, DisplayPort, 4x Tri-mode Gigabit Ethernet 2xUSB 2.0, 2x SD/SDIO, 2x UART, 2x CAN 2.0B, 2x I2C, 2x SPI, 4x 32b GPIO Full / Low / PL / Battery Power Domains RSA, AES, and SHA 10-bit, 1MSPS � Temperature and Voltage Monitor 12 x 32/64/128b AXI Ports 154 192 256 469 504 600 653 747 141 176 234 429 461 548 597 682 71 88 117 215 230 274 299 341 1.8 2.6 3.5 6.9 6.2 8.8 9.1 11.3 7.6 4.5 5.1 25.1 11.0 32.1 21.1 26.2 - 13.5 18.0 - 27.0 - 22.5 31.5 3 4 4 4 8 4 8 4 360 728 1,248 1,973 1,728 2,520 2,928 3,528 - 2 2 - 2 - 4 - - - - - - - 1 - - - - - - - 2 - 1 1 1 1 1 1 1 1 - 16 16 24 24 24 32 24 - - - - - - 16 - -1 -2 -2L -3 -1 -2 -2L -3 -1 -1L -2 ZU17EG 926 847 423 8.0 28.0 28.7 11 1,590 4 2 2 1 44 28 ZU19EG 1,143 1,045 523 9.8 34.6 36.0 11 1,968 5 4 4 1 44 28 � Copyright 2016�2021 Xilinx XMP104 (v2.5.1) Zynq� UltraScale+TM MPSoCs: EV Devices Device Name(1) Application Processor Unit Processor Core Memory w/ECC Processing System (PS) Real-Time Processor Unit Processor Core Memory w/ECC Graphic & Video Graphics Processing Unit Acceleration Memory External Memory Dynamic Memory Interface Static Memory Interfaces Connectivity High-Speed Connectivity General Connectivity Integrated Block Functionality Power Management Security AMS - System Monitor PS to PL Interface Programmable Functionality System Logic Cells (K) CLB Flip-Flops (K) CLB LUTs (K) Max. Distributed RAM (Mb) Programmable Logic (PL) Memory Total Block RAM (Mb) UltraRAM (Mb) Clocking Clock Management Tiles (CMTs) DSP Slices Video Codec Unit (VCU) Integrated IP PCI Express� Gen 3x16 150G Interlaken 100G Ethernet MAC/PCS w/RS-FEC AMS - System Monitor Transceivers GTH 16.3Gb/s Transceivers GTY 32.75Gb/s Transceivers Speed Grades Extended(2) Industrial Notes: 1. For full part number details, see the Ordering Information section in DS891, Zynq UltraScale+ MPSoC Overview. 2.-2LE (Tj = 0�C to 110�C). For more details, see the Ordering Information section in DS891, Zynq UltraScale+ MPSoC Overview. Page 5 ZU4EV 192 176 88 2.6 4.5 13.5 4 728 1 2 1 16 - ZU5EV Quad-core Arm� Cortex�-A53 MPCoreTM up to 1.5GHz L1 Cache 32KB I / D per core, L2 Cache 1MB, on-chip Memory 256KB Dual-core Arm Cortex-R5F MPCoreTM up to 600MHz L1 Cache 32KB I / D per core, Tightly Coupled Memory 128KB per core MaliTM-400 MP2 up to 667MHz L2 Cache 64KB x16: DDR4 w/o ECC; x32/x64: DDR4, LPDDR4, DDR3, DDR3L, LPDDR3 w/ ECC NAND, 2x Quad-SPI PCIe� Gen2 x4, 2x USB3.0, SATA 3.1, DisplayPort, 4x Tri-mode Gigabit Ethernet 2xUSB 2.0, 2x SD/SDIO, 2x UART, 2x CAN 2.0B, 2x I2C, 2x SPI, 4x 32b GPIO Full / Low / PL / Battery Power Domains RSA, AES, and SHA 10-bit, 1MSPS � Temperature and Voltage Monitor 12 x 32/64/128b AXI Ports 256 234 117 3.5 5.1 18.0 4 1,248 1 2 1 16 -1 -2 -2L -3 -1 -1L -2 ZU7EV 504 461 230 6.2 11.0 27.0 8 1,728 1 2 1 24 - XMP104 (v2.5.1) � Copyright 2016�2021 Xilinx Zynq� UltraScale+TM MPSoCs PS I/Os(1), 3.3V High-Density (HD) I/O, 1.8V High-Performance (HP) I/Os PS-GTR 6Gb/s, GTH 16.3Gb/s, GTY 32.75Gb/s Pkg Footprint(2,3) A484(4) A494 A530 A625(4) C784(4,5) Dimensions Ball Pitch (mm) (mm) 19x19 0.8 9.5x15 0.5 ZU1 170, 24, 58 4, 0, 0 170, 24, 58 4, 0, 0 9.5x16 0.5 21x21 23x23 0.8 170, 24, 156 4, 0, 0 0.8 214, 24, 156, 4, 0, 0 ZU2 170, 24, 58 4, 0, 0 170, 24, 58 4, 0, 0 170, 24, 156 4, 0, 0 214, 96, 156 4, 0, 0 B900 31x31 1.0 C900 31x31 1.0 B1156 35x35 1.0 C1156 35x35 1.0 B1517 40x40 1.0 F1517 40x40 1.0 C1760 42.5x42.5 1.0 D1760 42.5x42.5 1.0 E1924 45x45 1.0 ZU3 170, 24, 58 4, 0, 0 170, 24, 58 4, 0, 0 170, 24, 156 4, 0, 0 214, 96, 156 4, 0, 0 ZU4 ZU5 ZU6 ZU7 ZU9 ZU11 ZU15 ZU17 ZU19 214, 96, 156 4, 4, 0 214, 48, 156 4, 16, 0 214, 96, 156 4, 4, 0 214, 48, 156 4, 16, 0 214, 48, 156 4, 16, 0 214, 120, 208 4, 24, 0 214, 48, 156 4, 16, 0 214, 48, 312 4, 20, 0 214, 48, 416 4, 24, 0 214, 48, 156 4, 16, 0 214, 120, 208 4, 24, 0 214, 48, 312 4, 20, 0 214, 72, 416 4, 16, 0 214, 48, 416 4, 32, 0 214, 96, 416 4, 32, 16 214, 48, 156 4, 16, 0 214, 120, 208 4, 24, 0 214, 72, 572 4, 16, 0 214, 96, 416 4, 32, 16 214, 48, 260 4, 44, 28 214, 96, 572 4, 44, 0 214, 72, 572 4, 16, 0 214, 96, 416 4, 32, 16 214, 48, 260 4, 44, 28 214, 96, 572 4, 44, 0 Notes: 1. PS I/O is a combination of PS MIO and PS DDRIO. 2. Packages with the same last letter and number sequence, e.g., A484, are footprint compatible with all other UltraScale devices with the same sequence. 3. For full part number details, see the Ordering Information section in DS891, Zynq UltraScale+ MPSoC Overview. 4. These packages are only offered in 0.8mm ballpitch. All other packages are offered in 1.0mm ball pitch. 5. GTH transceivers in the C784 package support data rates up to 12.5Gb/s. Page 6 � Copyright 2016�2021 Xilinx XMP104 (v2.5.1) Zynq� UltraScale+TM MPSoC Device Migration Table The Zynq UltraScale+ family provides footprint compatibility to enable users to migrate designs from one device to another. Any two packages with the same footprint identifier code (last letter and number sequence) are footprint compatible. Pkg A484 A494 A530 A625 C784 B900 C900 B1156 C1156 B1517 F1517 C1760 D1760 E1924 Zynq� UltraScale+TM mm CG Devices EG Devices EV Devices ZU1CG ZU2CG ZU3CG ZU4CG ZU5CG ZU6CG ZU7CG ZU9CG ZU1EG ZU2EG ZU3EG ZU4EG ZU5EG ZU6EG ZU7EG ZU9EG ZU11EG ZU15EG ZU17EG ZU19EG ZU4EV ZU5EV ZU7EV 19 9.5x15 9.5x16 21 23 31 31 35 35 40 40 42.5 42.5 45 Page 7 � Copyright 2016�2021 Xilinx XMP104 (v2.5.1) Zynq� UltraScale+TM MPSoC Speed Grades Extended(2) Speed Grade -1 ZU1 CG EG �� ZU2 CG EG �� ZU3 CG EG �� ZU4 CG EG EV ��� ZU5 CG EG EV ��� Device Name(1) ZU6 ZU7 CG EG CG EG EV ����� ZU9 CG EG �� -2 ������������������� -2L ������������������� -3 ������������������� -1 ������������������� -1L ������������������� -2 ������������������� ZU11 EG � � � � � � � ZU15 EG � � � � � � � ZU17 EG � � � � � � � ZU19 EG � � � � � � � Industrial Notes: 1. For full part number details, see the Ordering Information section in DS891, Zynq UltraScale+ MPSoC Overview. 2.-2LE (Tj = 0�C to 110�C). For more details, see the Ordering Information section in DS891, Zynq UltraScale+ MPSoC Overview. � :: available � :: not offered Page 8 � Copyright 2016�2021 Xilinx XMP104 (v2.5.1) Zynq� UltraScale+TM MPSoC Ordering Information Device Name Device Attributes Footprint XC ZU # E G -1 F F V A # E Xilinx Commercial Zynq UltraScale + Value Index Processor Engine Type System G: General Purpose Identifier V: Video C: Dual APU Dual RPU E: Quad APU Dual RPU Single GPU Speed Grade -1: Slowest -L1: Low Power -2: Mid -L2: Low Power -3: Fastest F: Flip-chip w/ 1.0mm Ball Pitch S: Flip-chip w/ 0.8mm Ball Pitch U: InFO w/ 0.5mm Ball Pitch F: Lid V: RoHS 6/6 Package B: Lidless Designator Package Pin Count Temperature Grade (E, I) E = Extended (Tj = 0�C to +100�C) I = Industrial (Tj = �40�C to +100�C) Note: -L2E (Tj = 0�C to +110�C). Refer to DS891, Zynq UltraScale+ MPSoC Overview for additional information. Page 9 Important: Verify all data in this document with the device data sheets found at www.xilinx.com � Copyright 2016�2021 Xilinx XMP104 (v2.5.1) References DS890, UltraScaleTM Architecture and Product Overview DS891, Zynq� UltraScale+TM MPSoC Overview DS925, Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics UG1075, Zynq UltraScale+ MPSoC Packaging and Pinouts UG1085, Zynq UltraScale+ MPSoC Technical Reference Manual UG1087, Zynq UltraScale+ MPSoC Register Reference UG1137, Zynq UltraScale+ MPSoC: Software Developers Guide UG1169, Zynq UltraScale+ MPSoC QEMU: User Guide UG1186, Zynq UltraScale+ MPSoC OpenAMP: Getting Started Guide UG571, UltraScale Architecture SelectIOTM Resources User Guide UG572, UltraScale Architecture Clocking Resources User Guide UG573, UltraScale Architecture Memory Resources User Guide UG574, UltraScale Architecture Configurable Logic Block User Guide UG576, UltraScale Architecture GTH Transceivers User Guide UG578, UltraScale Architecture GTY Transceivers User Guide UG579, UltraScale Architecture DSP Slice User Guide UG580, UltraScale Architecture System Monitor User Guide UG583, UltraScale Architecture PCB and Pin Planning User Guide PG150, LogiCORETM IP UltraScale Architecture-Based FPGAs Memory Interface Solutions PG182, UltraScale FPGAs Transceivers Wizard Product Guide Important: Verify all data in this document with the device data sheets found at www.xilinx.com Page 10 � Copyright 2016�2021 Xilinx XMP104 (v2.5.1)