Intel Programmable Acceleration Card (PAC) with Intel Arria 10 GX FPGA Data Sheet
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Intel Programmable Acceleration Card (PAC) with Intel Arria 10 GX FPGA Data Sheet
This document provides electrical, mechanical, compliance, and other key specifications of the Intel Programmable Acceleration Card with Intel Arria 10 GX FPGA.
Intel Programmable Acceleration Card with Intel Arria 10 GX FPGA, Intel PAC with Intel Arria 10 GX FPGA, Arria 10 PAC, FPGA PAC, PAC Data Sheet
Intel FPGA Data Sheet
Intel Acceleration Stack Quick Start Guide for Intel Programmable Acceleration Card with Arria 10 GX FPGA. 1. Introduction DS-1054 | 2019.05.30
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Intel� Programmable Acceleration Card (PAC) with Intel� Arria� 10 GX FPGA Data Sheet Subscribe Send Feedback DS-1054 | 2019.05.30 Latest document on the web: PDF | HTML Contents Contents 1. Introduction .................................................................................................................. 3 2. Overview........................................................................................................................ 5 2.1. Views of the Intel PAC with Intel Arria 10 GX FPGA.....................................................5 2.2. Overview of Product Features.................................................................................. 6 2.2.1. Intel Arria 10 GX FPGA............................................................................... 6 2.2.2. On-Board Memory..................................................................................... 6 2.2.3. Interfaces and Dimensions ......................................................................... 6 2.2.4. Software.................................................................................................. 7 2.2.5. Power...................................................................................................... 7 2.2.6. CPLD....................................................................................................... 7 2.2.7. QSFP+ .................................................................................................... 7 2.2.8. Control and Support...................................................................................8 3. System Compatibility ................................................................................................... 10 4. Mechanical Information ............................................................................................... 12 5. Thermal Specifications ................................................................................................. 15 5.1. Thermal Test Performance Results.......................................................................... 15 6. FPGA Interface Manager .............................................................................................. 17 6.1. Updating the FIM ................................................................................................ 17 7. Board Management Controller...................................................................................... 18 7.1. Features............................................................................................................. 18 7.1.1. BMC Voltage and Thermal Handling............................................................ 19 7.2. BMC Tools .......................................................................................................... 19 7.2.1. BWConfig................................................................................................20 7.2.2. BwMonitor ............................................................................................. 20 7.3. Updating the BMC Configuration and Firmware.........................................................26 8. PLDM Commands for the Board Management Controller............................................... 27 8.1. I2C/SMBus Address ............................................................................................. 27 8.2. Supported SMBus Commands................................................................................ 27 8.3. Supported MCTP Commands..................................................................................27 8.3.1. MCTP Control Messages............................................................................ 27 8.4. Supported PLDM Commands..................................................................................28 8.4.1. PLDM Base Specification Commands........................................................... 28 8.4.2. PLDM for Platform Monitoring and Control Specification Commands................ 28 8.5. Defined Platform Descriptor Records.......................................................................28 8.6. Sensor and Threshold Information..........................................................................30 A. Regulatory Information................................................................................................ 31 B. References....................................................................................................................37 C. Document Revision History for Intel Programmable Acceleration Card (PAC) with Intel Arria 10 GX FPGA Data Sheet.......................................................................... 38 Intel� Programmable Acceleration Card (PAC) with Intel� Arria� 10 GX FPGA Data Sheet 2 Send Feedback DS-1054 | 2019.05.30 Send Feedback 1. Introduction Figure 1. Intel� Programmable Acceleration Card with Intel� Arria� 10 GX FPGA This datasheet for the Intel� PAC with Intel Arria� 10 GX FPGA shows electrical, mechanical, compliance, and other key specifications. This datasheet assists data center operators and system integrators to properly deploy this PAC into their servers. It also documents the FPGA power envelope, connectivity speeds to memory, and network connectivity, so that accelerator function unit (AFU) developers can properly design and test their IP. The PAC is supported by the Intel Acceleration Stack for Intel Xeon� CPU with FPGAs. The Intel Acceleration Stack provides a common developer interface to both application and acceleration function developers and includes drivers, Application Programming Interfaces (APIs) and an FPGA Interface Manager (FIM). Along with acceleration libraries and development tools, the Acceleration Stack saves development time and enables code re-use across multiple Intel FPGA form-factor products, allowing the developer to focus on the unique value-additon of their solution. Developers can use the Accelerator Functional Unit (AFU) User Guide to get started. Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2015 Registered 1. Introduction DS-1054 | 2019.05.30 Intel validates each Intel Programmable Acceleration Card with Intel Arria 10 GX FPGA to support large scale deployments requiring FPGA acceleration. This platform is targeted for market-specific acceleration in applications such as: � Big Data Analytics � Artificial Intelligence � Video Transcoding � Cyber Security � Genomics � High-Performance Computing � Finance This document supports Acceleration Stack versions 1.1 and 1.2. Related Information Intel Acceleration Stack Quick Start Guide for Intel Programmable Acceleration Card with Arria 10 GX FPGA Intel� Programmable Acceleration Card (PAC) with Intel� Arria� 10 GX FPGA Data Sheet 4 Send Feedback DS-1054 | 2019.05.30 Send Feedback 2. Overview This chapter provides an overview of the programmable acceleration card and describes the board architecture and its components. 2.1. Views of the Intel PAC with Intel Arria 10 GX FPGA Figure 2. Intel PAC with Intel Arria 10 GX FPGA Internals Figure 3. Intel PAC with Intel Arria 10 GX FPGA Conceptual View Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2015 Registered 2. Overview DS-1054 | 2019.05.30 2.2. Overview of Product Features 2.2.1. Intel Arria 10 GX FPGA The Intel Arria 10 FPGAs feature industry-leading programmable logic built on 20 nm process technology that integrate a rich feature set of embedded peripherals, embedded high-speed transceivers, hard memory controllers and IP protocol controllers. Variable-precision digital signal processing (DSP) blocks integrated with hardened floating point (IEEE 754-compliant) enable the Intel Arria 10 FPGAs to deliver floating point performance of up to 1.5 TFLOPS. Arria 10 FPGAs have a comprehensive set of power-saving features. Combined, these features allow developers to build versatile set of acceleration solutions. When developing the accelerator function for the Intel PAC, select the 10AX115N2F40E2LG device. Related Information � Intel FPGA Devices Detailed information about features of the Intel Arria 10 GX FPGA family � Intel Arria 10 Device Datasheet This datasheet describes the electrical characteristics, switching characteristics, configuration specifications, and I/O timing for Intel Arria 10 devices. � Intel Arria 10 Device Overview This device overview provides information about known device issues affecting Intel Arria 10 GX/GT devices. It also offers design recommendations you should follow when using Intel Arria 10 GX/GT devices. 2.2.2. On-Board Memory � 8 GB Double Data Rate 4 (DDR-4) memory -- 2133 Mbps -- Two 4 GB DDR-4 memory banks, part number MT40A512M16JY-083E:B -- Width: 64 data bits Note: Refer to the Accelerator Functional Unit (AFU) Developer's Guide for access within the FIM to this memory link. � One 1 GB (128 MB) Flash � for use with the FIM Related Information Accelerator Functional Unit (AFU) Developer's Guide 2.2.3. Interfaces and Dimensions � PCI Express (PCIe) x8 Gen3 electrical, x16 mechanical for stability Note: The Intel PAC with Intel Arria 10 GX FPGA does not support PCIe Gen4. � USB 2.0 interface for debugging. Also available as an alternative to PCIe for programming FPGA and flash. � 1x Quad Small Form Factor Pluggable+ (QSFP+) with 4x 10GbE or 40GbE support. � Conforms to 1 Rack Unit. Intel� Programmable Acceleration Card (PAC) with Intel� Arria� 10 GX FPGA Data Sheet 6 Send Feedback 2. Overview DS-1054 | 2019.05.30 Note: � � Length, full height card with air duct installed (default) � � Length, � height card with air duct removed and low profile bracket installed � Standard bracket available with air duct addition available. One rack unit is 44.5 mm (1.75 inches) high. One rack unit is commonly designated as "1U". 2.2.4. Software � Acceleration Stack for Intel Xeon CPU with FPGAs � FIM Installed Note: Certain development sample boards may be supplied without the FIM installed. � Board Management Controller firmware Related Information Intel FPGA Acceleration Hub Information about the Intel Acceleration Stack. 2.2.5. Power � 66W TDP -- The TDP is based on the max current, per the PCIe specification, of 5.5A on the 12V rail. -- As the developers or solution provider, you must ensure that the AFU does not exceed this limit or the limit provided by the qualified server vendor. Functionality and reliability of the server is not supported for AFUs that exceed the specification. � Up to 45 W FPGA power consumption � The PAC source power is from the 12V rail of the PCIe* edge connector. The PAC does not draw power from the 3.3V rail. 2.2.6. CPLD The CPLD is an Intel FPGA Download Cable. JTAG is used for debug and instances where the FIM image is corrupted or needs to be updated. 2.2.7. QSFP+ The Intel PAC with Intel Arria 10 GX FPGA has a QSFP+ cage on the front panel which supports 40GbE or four 10GbE. The table below details the Intel-supported connectors. For volume deployment, you must use Intel-validated QSFP+ cables. Successful functioning of 40GbE and 10GbE requires appropriate physical medium attachment (PMA) settings. Run the provided PMA settings script as detailed in the 10Gbps Ethernet Accelerator Functional Unit (AFU) Design Example User Guide or 40Gbps Ethernet Accelerator Functional Unit (AFU) Design Example User Guide. Send Feedback Intel� Programmable Acceleration Card (PAC) with Intel� Arria� 10 GX FPGA Data Sheet 7 2. Overview DS-1054 | 2019.05.30 Table 1. QSFP+ Support for the Intel Programmable Acceleration Card with Intel Arria 10 GX FPGA Intel Ethernet QSFP+ 1-meter direct attach cable (DAC) twinaxial cables Intel Ethernet QSFP+ 3-meter direct attach cable (DAC) twinaxial cables Intel Ethernet QSFP+ short reach (SR) optic module Intel Ethernet QSFP+ 1-meter Passive Breakout Cable Intel Ethernet QSFP+ 3-meter Passive Breakout Cable Model Number XLDACBL1 XLDACBL3 E40GQSFPSR X4DACBL1 X4DACBL3 Switches Intel has validated the following switches: Table 2. Intel-Validated Switches Ethernet AFU Switch Brand 40 Gbps Ethernet Dell* Extreme Networks* Mellanox* 10 Gbps Ethernet Cisco* Lenovo* Dell Switch Model Number Z9100-ON x870-32C SN2700 Nexus N9K-C93180YC-EX 8272 8024F QSFP+ SerDes The QSFP+ interface has four Serializer/Deserializer (SerDes) lanes connected directly to the FPGA. Related Information � Running 10GbE PAC-to-PAC Test between two connected PACs in the 10Gbps Ethernet Accelerator Functional Unit (AFU) Design Example User Guide � Running 40GbE PAC-to-PAC Test between two connected PACs in the 40Gbps Ethernet Accelerator Functional Unit (AFU) Design Example User Guide 2.2.8. Control and Support The following features are available on this acceleration card for configuration, control and support: � USB � PCIe � Board Management Controller (BMC) 2.2.8.1. USB Overview This acceleration card has a USB 2.0 port (J1) for debug and configuration in select cases. The USB interface is used for the following: Intel� Programmable Acceleration Card (PAC) with Intel� Arria� 10 GX FPGA Data Sheet 8 Send Feedback 2. Overview DS-1054 | 2019.05.30 � Read/write Intel Arria 10 FPGA configuration in Flash � Read manufacturing data via USB � Monitor on-board temperature and power � Update the board's BMC firmware � JTAG access to the Intel Arria 10 FPGA through the board's embedded Intel FPGA Download Cable Note: The specification of the inbound hub is USB 2.0 but it auto-negotiates from a USB 3.0 host PC. 2.2.8.2. PCIe Overview This acceleration card has a PCIe interface for configuration in select cases. When Intel Acceleration Stack for Intel Xeon CPU with FPGAs version 1.2 and the latest BMC firmware are installed, the PCIe interface can be used for the following: � Read/write Intel Arria 10 FPGA configuration in Flash � Read manufacturing data via USB � Monitor on-board temperature and power � Update the board's BMC firmware 2.2.8.3. Board Management Controller Overview The Board Management Controller (BMC) is responsible for controlling, monitoring and giving low-level access to board features. The BMC microcontroller interfaces with onboard sensors, the FPGA and the flash, and it controls power and resets. The microcontroller communicates over PCIe I2C using: � Platform Level Data Model (PLDM) for Platform Monitoring and Control version 1.1.1 � The Open Programmable Acceleration Engine (OPAE) FPGA tool The firmware that runs on the BMC microcontroller is field upgradeable over PCIe or USB. You can use a BittWorks ToolKit to access utilities and libraries for communicating to devices on the platform at a higher, more abstract level. You can flash the BMC firmware and read sensor data with the OPAE commands fpgaflash and fpgainfo. For more details, refer to the Board Management Controller section. Related Information Board Management Controller on page 18 Send Feedback Intel� Programmable Acceleration Card (PAC) with Intel� Arria� 10 GX FPGA Data Sheet 9 DS-1054 | 2019.05.30 Send Feedback 3. System Compatibility This section describes the platforms and LinuxTM distribution targeted for the acceleration card validation. Platforms Refer to the Qualified Servers and Ordering Information page for a list of the latest qualified servers. Operating System Validation Table 3. Operating System Validation Operating Systems (OS) RHELTM 7.4 CentOS 7.4 Ubuntu 16.04 RHEL CentOS Ubuntu OS Family Note: The above mentioned Operating Systems are Linux Kernel 3.10. Adapters must have the following PCIe ID and power/thermal budget. Note: � VID - Vendor ID � SVID - Sub Vendor ID � DID - Device ID � SDID - Sub Device ID Table 4. PCIe ID and Power/Thermal Budget PAC Intel PAC with Intel Arria 10 GX FPGA PCIe VID 0x8086 PCIe DID 0x09C4 PCIe SVID 0x8086 PCIe SDID 0x0000 Table 5. Ordering Code vs. Intel Acceleration Stack Version Compatibility Ordering Code DK-ACB-10AX1151AES DK-ACB-10AX1152AES Intel Acceleration Stack Version 1.0 1.1 1.2 Yes Yes Yes Not validated Yes Yes Note: If you purchased a board from a qualified OEM, please contact the OEM to confirm which version(s) of the Acceleration Stack it supports. Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2015 Registered 3. System Compatibility DS-1054 | 2019.05.30 Table 6. Validated BMC and Intel Acceleration Stack Versions Intel Acceleration Stack Version 1.0 1.1 Alpha 1.1 Beta and Production 1.2 Early Access 1.2 26815 26819 26822 26889 26889 BMC Firmware Version PACs ordered under the following codes are development samples and should not be used for volume deployment. Table 7. Development Samples DK-ACB-10AX1151AES DK-ACB-10AX1152AES OPN 980016 980017 MM# Send Feedback Intel� Programmable Acceleration Card (PAC) with Intel� Arria� 10 GX FPGA Data Sheet 11 DS-1054 | 2019.05.30 Send Feedback 4. Mechanical Information Figure 4. Dimensions of the Intel PAC with Intel Arria 10 GX FPGA � Standard height, half length PCIe card � Low profile option available � Card Weight with air duct: 255 g � Maximum component height: 14.47 mm � PCIe x16 mechanical Acceleration Card - Standard Profile Bracket with Airduct Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2015 Registered 4. Mechanical Information DS-1054 | 2019.05.30 Figure 5. Air Duct Assembly Figure 6. Acceleration Card - Low Profile Bracket Send Feedback Intel� Programmable Acceleration Card (PAC) with Intel� Arria� 10 GX FPGA Data Sheet 13 4. Mechanical Information DS-1054 | 2019.05.30 Figure 7. Acceleration Card - Standard Profile Bracket with No Air Duct Note: You can assemble or disassemble the air duct. Three screws hold the air duct in place. Two screws hold the bracket to the card and heat sink. Removal of air duct requires a different bracket to be used. Additional bracket options are available in Development Sample only to support the Intel PAC with Intel Arria 10 GX FPGA without air duct. Intel� Programmable Acceleration Card (PAC) with Intel� Arria� 10 GX FPGA Data Sheet 14 Send Feedback DS-1054 | 2019.05.30 Send Feedback 5. Thermal Specifications Figure 8. This acceleration card is thermally limited to dissipate no more than 45 W on the FPGA. FPGA junction temperature must not exceed 95�C. Make sure the temperature of the QSFP+ module is within the vendor specification, usually 70�C or 85�C. � Operating Temperature: 95 �C � Shutdown Temperature: 100 �C Refer to the Power Estimator Guide to avoid exceeding 95 �C. Contact your Intel sales representative to get the Power Estimation and Verification for Intel PAC with Arria 10 GX FPGA document. This document describes how to verify and ensure that the AFU operates within the power supported by the Intel PAC with Intel Arria 10 GX FPGA. AFU Developers should use the Arria 10 PowerPlay Early Power Estimator and the Intel Quartus� Prime Power Analyzer to estimate power consumption. Airflow Pattern Related Information Power Analysis and Optimization User Guide: Intel Quartus Prime Pro Edition The Intel Quartus Prime Pro Edition software provides a complete design environment for FPGA and SoC designs. The Power Analyzer is described in the Power Analysis and Optimization User Guide: Intel Quartus Prime Pro Edition. 5.1. Thermal Test Performance Results Table 8. Terms and Descriptions Term Linear Feet per Minute (LFM) TLA Description Air velocity is calculated by dividing the volumetric flow rate by the cross-sectional area of the flow passage. The measured ambient temperature locally surrounding the FPGA. The ambient temperature should be measured just upstream of a passive heatsink or at fan inlet for an active heatsink. Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2015 Registered 5. Thermal Specifications DS-1054 | 2019.05.30 Table 9. 30 35 40 45 50 55 Table 10. 30 35 40 45 50 55 TLA vs. Velocity Profile with Air Duct TLA (�C) Velocity (LFM) (85 �C QSFP spec) 270 300 360 420 510 660 Velocity (LFM) (70 �C QSFP spec) 270 300 360 420 510 690 TLA vs. Velocity Profile without Air Duct TLA (�C) Velocity (LFM) (85 �C QSFP spec) 330 390 420 510 600 810 Velocity (LFM) (70 �C QSFP spec) 330 390 420 510 630 870 Intel� Programmable Acceleration Card (PAC) with Intel� Arria� 10 GX FPGA Data Sheet 16 Send Feedback DS-1054 | 2019.05.30 Send Feedback 6. FPGA Interface Manager The FPGA Interface Manager (FIM) contains the FPGA logic to support the accelerators, including the PCIe IP core, the Core Cache Interface protocol (CCI-P) fabric, the onboard DDR memory interface, and management engine. Specific features of the FIM are listed in the following documents: � Intel Acceleration Stack Quick Start Guide for Intel Programmable Acceleration Card with Intel Arria 10 GX FPGA � OPAE Intel FPGA Linux Device Driver Architecture Guide The 1024 Mb flash memory stores the FPGA Interface Manager (FIM) which provides a common user interface for placement of accelerator functions. In addition, the FIM allows dynamic downloading of new accelerator functions and updates to the FIM. The FIM can read all sensor data from the BMC, using the Intel Acceleration Stack. For example, to read the FPGA temperature, use the following command: sudo fpgainfo temp To read voltage and current data, use the following command: sudo fpgainfo power Refer to the Intel Acceleration Stack Quick Start Guide for the Intel Programmable Acceleration Card with Intel Arria 10 GX FPGA to learn how to use these features. 6.1. Updating the FIM The FIM image in flash memory can be updated using the following methods: � The primary method is for the FIM to be updated over PCIe via the Acceleration Stack program fpgaflash. This loads the FIM image into the onboard flash memory. Upon power up, the board loads the image from flash onto the FPGA. � Directly configure the FPGA via JTAG through the USB port. This use case should only be used if the FIM image gets corrupted or erased. Note: Please refer to the Intel Acceleration Stack Quick Start Guide for the Intel Programmable Acceleration Card with Intel Arria 10 GX FPGA for instructions on updating the FIM. Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2015 Registered DS-1054 | 2019.05.30 Send Feedback 7. Board Management Controller A board management controller (BMC) resides on the Intel PAC with Intel Arria 10 GX FPGA. 7.1. Features The on-board microcontroller: � Provides low-level access to board features. � Interfaces with sensors, FPGA, flash and QSFP. � Controls power and resets on the board. � Monitors temperatures, voltages and currents and provides protective action when readings are outside of critical thresholds. � Provides Platform Level Data Model (PLDM) for PCIe I2C communication. The I2C slave address is 0xCE. � Supports field upgrades of BMC firmware. Figure 9. Board Management Controller for the Intel PAC with Intel Arria 10 GX FPGA USB 2.0 Intel� Arria 10� FPGA Flash BMC SPI Microcontroller SPI SPI I2C Programmable Clocks, DACs etc. Voltage Sensors Current Sensors Temperature Sensors Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2015 Registered 7. Board Management Controller DS-1054 | 2019.05.30 7.1.1. BMC Voltage and Thermal Handling The BMC powers down the Intel PAC with Intel Arria 10 GX FPGA and reboots the server if the power, temperature or voltage reaches a certain threshold. This response prevents damage to the server or Intel PAC with Intel Arria 10 GX FPGA. For threshold limits refer to the Device Peripheral Table section. This table shows the upper non-recoverable (UNR) value, which specifies the shutdown condition. The BMC will shut down power to the board under conditions that include the following: � Backplane voltage reaches 14 V, or current reaches 6A (i.e., a maximum of 84W total power) � FPGA junction temperature reaches 100�C Note: The backplane power limits shown above are sufficient to protect the Intel PAC with Intel Arria 10 GX FPGA hardware. If your server components require more conservative limits, you can change any threshold using PLDM commands as described in PLDM Commands for the Board Management Controller. To avoid unintended shutdown and loss of data: � Use an Intel-validated server. � Perform extensive power validation and consumption analysis on worst-case workloads. � Use a qualified solution that is stress-tested across multiple servers and long durations. � Enable the pacd daemon. This system service monitors sensor readings versus defined thresholds, and disables access to the Intel PAC when it exceeds a threshold. For information about pacd, refer to OPAE FPGA Tools in the Open Programmable Acceleration Engine page. You can identify whether the BMC has detected a board failure from the two on-board LEDs. Looking into the bracket of the Intel PAC through the venting holes on the back side of the server, you can see four steadily ON green LEDs. Behind them (further into the board), there is either a green LED or red LED that is on. The green LED blinks whenever the BMC is operating and is steadily on if the BMC is being initialized. When the BMC detects a failure condition and holds off board power, a red LED (next to the green LED) will be steadily on. Board failure conditions may occur because of an overheated FPGA or too much power draw from the board. Related Information � PLDM Commands for the Board Management Controller on page 27 � Device Peripheral Table on page 24 7.2. BMC Tools The BittWare Toolkit features several utilities that allow you to configure your device in the system, interact with FPGA and debug the FPGA, control the BMC on your board, and access the board from a remote system. To use the BWConfig and BwMonitor tools, you need a Micro-USB cable to connect the acceleration card to any USB port on host server. Send Feedback Intel� Programmable Acceleration Card (PAC) with Intel� Arria� 10 GX FPGA Data Sheet 19 7. Board Management Controller DS-1054 | 2019.05.30 Note: Before using BwMonitor to get telemetry data from the acceleration card, you need to run BWConfig, scan the USB bus, find the card being tested, and map it as device 0. The OPAE tools fpgainfo and fpgaflash can retrieve BMC telemetry data and update BMC over PCIe, eliminating the need for a USB cable. Refer to the Intel Acceleration Stack Quick Start Guide for the Intel Programmable Acceleration Card with Intel Arria 10 GX FPGA to learn how to use these features. 7.2.1. BWConfig BwConfig is a utility for configuring the BMC in a system. BwConfig: � Controls BMC hardware on the platform � Scans and maps new devices through PCIe or USB � Views device properties � Controls FPGA boot and flash loading � Can backup flash to restore a factory default image over PCIe � Supports resetting and loading FPGA images without the need to attach additional cables or hardware 7.2.2. BwMonitor BwMonitor provides a view into the board management capabilities of your Intel Programmable Acceleration Card with Intel Arria 10 GX FPGA. You can use BwMonitor through a GUI or console. BwMonitor allows you to: � View board health � Read and log sensors � Control sensor thresholds that determine when the board will shut down � Load programmable clocks � Override voltages � Access devices via I2C � Upgrade the BMC firmware � Monitor the board over PCIe or USB 7.2.2.1. bwmonitor --read Command Use the --read command in the console to read any combination or number of the available peripheral devices. The following table describes the additional arguments that can be used with the --read command. Intel� Programmable Acceleration Card (PAC) with Intel� Arria� 10 GX FPGA Data Sheet 20 Send Feedback 7. Board Management Controller DS-1054 | 2019.05.30 Table 11. bwmonitor --read Command Argument Options --type Available Arguements --id --loop --read_every Description Narrows results to a certain type of peripheral device, for example sensors. Use in conjunction with the --type argument to read only one device. Continues reading sensors in a loop. Controls how often the sensors are read. Note: In bwmonitor output, "SDR" is equivalent to PDR (platform descriptor record). 7.2.2.1.1. Example: Read all peripheral devices $ bwmonitor --dev=0 --read Fri Nov 2 10:35:45 2018 Board Management Controller A10SA4 dev 0 (1) Microcontroller Version 26879 SDR Sensors A10SA4 dev 0 (0) Board Power OK 19 Watts (1) 12v Backplane Current OK 1.58 Amps (2) 12v Backplane Voltage OK 12.01 Volts (4) 1.2v Current OK 2.66 Amps (3) 1.2v Voltage OK 1.22 Volts (6) 1.8v Current OK 2.54 Amps (5) 1.8v Voltage OK 1.84 Volts (8) 3.3v Current OK 0.54 Amps (7) 3.3v Voltage OK 3.33 Volts (9) FPGA Core Voltage OK 0.90 Volts (10) FPGA Core Current OK 4.74 Amps (11) FPGA Core Temperature OK 39 degrees C (15) Core Supply Temperature OK 46 degrees C (12) Board Temperature OK 26 degrees C (14) QSFP Temperature Unavailable (13) QSFP Voltage Unavailable (17) VCCR Voltage OK 1.04 Volts (18) VCCT Voltage OK 1.04 Volts (19) VCCR Current OK 0.90 Amps (20) VCCT Current OK 0.43 Amps (21) VPP Voltage OK 2.56 Volts (22) VTT Voltage OK 0.60 Volts Pluggable Transceivers (SFP) A10SA4 dev 0 (0) QSFP Programmable Clocks (PLL) A10SA4 dev 0 (0) Si5338 322.2656, 100, 266.6666, 266.6666 FRU EEPROMs A10SA4 dev 0 (0) FRU FPGAs A10SA4 dev 0 (0) FPGA Networking Modules A10SA4 dev 0 MAC Prom 1670:0204:5410:0060:c4ae:a000:a000:0065 7.2.2.1.2. Example: Read all sensors $ bwmonitor --dev=0 --read --type=sensor Fri Nov 2 10:37:50 2018 SDR Sensors A10SA4 dev 0 (0) Board Power OK (1) 12v Backplane Current OK (2) 12v Backplane Voltage OK (4) 1.2v Current OK (3) 1.2v Voltage OK (6) 1.8v Current OK 19 Watts 1.58 Amps 12.01 Volts 2.66 Amps 1.22 Volts 2.54 Amps Send Feedback Intel� Programmable Acceleration Card (PAC) with Intel� Arria� 10 GX FPGA Data Sheet 21 7. Board Management Controller DS-1054 | 2019.05.30 (5) 1.8v Voltage (8) 3.3v Current (7) 3.3v Voltage (9) FPGA Core Voltage (10) FPGA Core Current (11) FPGA Core Temperature (15) Core Supply Temperature (12) Board Temperature (14) QSFP Temperature (13) QSFP Voltage (17) VCCR Voltage (18) VCCT Voltage (19) VCCR Current (20) VCCT Current (21) VPP Voltage (22) VTT Voltage OK OK OK OK OK OK OK OK Unavailable Unavailable OK OK OK OK OK OK 1.84 Volts 0.54 Amps 3.33 Volts 0.90 Volts 4.74 Amps 39 degrees C 46 degrees C 26 degrees C 1.04 Volts 1.04 Volts 0.90 Amps 0.43 Amps 2.56 Volts 0.60 Volts 7.2.2.1.3. Example: Read the FPGA Core Temperature Sensor $ bwmonitor --dev=0 --read=11 --type=sensor Fri Nov 2 10:38:59 2018 SDR Sensors A10SA4 dev 0 (11) FPGA Core Temperature OK 39 degrees C Intel� Programmable Acceleration Card (PAC) with Intel� Arria� 10 GX FPGA Data Sheet 22 Send Feedback 7. Board Management Controller DS-1054 | 2019.05.30 7.2.2.2. How to Invoke the BMC GUI 1. Type the following command: bwmonitor -gui & 2. Click connect Send Feedback Intel� Programmable Acceleration Card (PAC) with Intel� Arria� 10 GX FPGA Data Sheet 23 7. Board Management Controller DS-1054 | 2019.05.30 7.2.2.3. BMC Settings Right-click any sensor with a green icon to open the Sensor Thresholds dialog box. Figure 10. Board Power Sensor Threshold Window 7.2.2.4. Device Peripheral Table The following table describes the peripherals, currents or voltages that you can monitor on the Intel PAC with Intel Arria 10 GX FPGA: � Type: Indicates the origin of measurement � Channel and Address columns: Indicate the virtual I2C channel and address that are used to access the peripheral through the microcontroller. � ID (DEV/PDR): Indicates the platform descriptor record (PDR) index; otherwise, indicates the device number (DEV), if any, to be passed to the relevant PLDM command. � UNC: Upper non-critical value � UC: Upper critical value � UNR: Upper non-recoverable value: the threshold for power shutdown(1) (1) For a detailed discussion of UNR, refer to BMC Voltage and Thermal Handling Intel� Programmable Acceleration Card (PAC) with Intel� Arria� 10 GX FPGA Data Sheet 24 Send Feedback 7. Board Management Controller DS-1054 | 2019.05.30 Table 12. Device Peripheral Table Name Board Power 12v Backplane Current 12v Backplane Voltage 1.2v Current Type Sensor Sensor Channel Address ID (DEV/ PDR) - - 0 5 0xD4 1 UNC 75 5.5 UC UNR Description 100 113 - 6 6 LTC4151 Input Current Sensor 5 0xD4 2 13.5 14 14 LTC4151 Input Voltage Sensor 6 0xD0 4 12 13 15 LTC4151 Output Current 1.2v Voltage Sensor 6 0xD0 3 1.26 1.3 1.4 LTC4151 Output Voltage 1.8v Current 1.8v Voltage Sensor Sensor 6 0xD2 6 6 7 8 LTC4151 Output Current 6 0xD2 5 1.9 2 2.04 LTC4151 Output Voltage 3.3v Current Sensor 6 0xD4 8 6 7 8 LTC4151 Output Current 3.3v Voltage FPGA Core Voltage FPGA Core Current FPGA Core Temperature Core Supply Temperature Board Temperature QSFP Temperature QSFP Voltage Sensor Sensor Sensor Sensor Sensor Sensor Sensor Sensor 6 0xD4 7 3.47 3.6 3.96 LTC4151 Output Voltage 6 0xDA 9 0.95 1 1.08 LTC4151 Output Voltage 6 0xDA 10 50 55 60 LTC4151 Output Current 0 0x98 11 90 95 100 NCT72CMTR2G External - - 15 100 110 120 - 0 0x98 12 70 75 80 NCT72CMTR2G Local 3 0xA0 14 70 80 90 - 3 0xA0 13 3.4 3.5 3.7 - VCCR Voltage VCCT Voltage VCCR Current VCCT Current VPP Voltage VTT Voltage QSFP Sensor Sensor Sensor Sensor Sensor Sensor SFP/QSFP - - 17 - - - 18 - - -- - - 19 - - -- - - 20 - - 21 - - -- - - 22 - - -- - 0xA0 1 - - -- Si5338 Programmable 0 Clock MAC Prom Network 4 0xE0 0 0xA0 - - - - Defaults to 125, 125, 266.666667, 266.666667 - - - AT24CS04 Send Feedback Intel� Programmable Acceleration Card (PAC) with Intel� Arria� 10 GX FPGA Data Sheet 25 7. Board Management Controller DS-1054 | 2019.05.30 Note: The table above lists ID (DEV/PDR) (device IDs) based at 0, as shown by the Bittware tools and the fpgainfo command. However, the PLDM commands use device IDs based at 1. Therefore, when using PLDM commands, you must add 1 to the table device ID to obtain the PLDM device ID. For example, the board power ID is listed as 0 in the Device Peripheral Table, but in PLDM commands the board power ID is 1. Refer to the Intel Acceleration Stack Quick Start Guide for the Intel Programmable Acceleration Card with Intel Arria 10 GX FPGA for information about the fpgainfo command. Related Information � PLDM Commands for the Board Management Controller on page 27 � BMC Voltage and Thermal Handling on page 19 7.3. Updating the BMC Configuration and Firmware The BMC contains an in-system programmable boot loader for upgrading the firmware over PCIe or USB. Intel provides the firmware for image upgrades. The upgrade process takes seconds and the board is reset when the upgrade is complete. For directions on how to update the BMC configuration and firmware, you must refer to the Updating FPGA Flash and BMC Firmware section in the Intel Acceleration Stack Quick Start Guide for Intel Programmable Acceleration Card with Intel Arria 10 GX FPGA. With the Intel Acceleration Stack version 1.2, you can avoid connecting a USB cable by updating BMC firmware over PCIe, using the fpgaflash command. Note: Firmware update over PCIe is supported only by the BMC firmware included with the Intel Acceleration Stack version 1.2 or later. If your board is running an earlier firmware version, you must use a USB cable to upgrade to version 1.2 or later before you can take advantage of the PCIe update feature. Note: Before updating firmware, verify that your OEM has fully validated the new firmware against your OEM server software version. Intel does not validate BMC firmware against all OEM software versions. Related Information Intel Acceleration Quick Start Guide for Intel Programmable Acceleration Card with Intel Arria 10 GX FPGA Intel� Programmable Acceleration Card (PAC) with Intel� Arria� 10 GX FPGA Data Sheet 26 Send Feedback DS-1054 | 2019.05.30 Send Feedback 8. PLDM Commands for the Board Management Controller Note: The BMC on the Intel PAC with Intel Arria 10 GX FPGA can communicate with a server BMC over the PCIe I2C bus. The supported protocol is the PLDM over Management Component Transport Protocol (MCTP) stack. The PAC BMC supports a subset of PLDM and MCTP commands, to enable a server BMC to obtain sensor data for fan control. The BMC supports version 1.1.1 of the PLDM for Platform Monitoring and Control standard (DTMF specification DSP0248). It does not support version 1.1.0. For more information about the PLDM and MCTP protocol specifications, refer to DMTF Specifications on the Platform Management Components Intercommunication website. The PAC BMC does not break large MCTP packets down to 64-byte packets, as described in the MCTP specification for baseline transmission unit size. Otherwise the BMC is fully compliant to the DMTF specifications. Related Information Platform Management Components Intercommunication 8.1. I2C/SMBus Address The PCIe I2C slave address of the Intel PAC with Intel Arria 10 GX FPGA is fixed at 0xCE. There is no Address Resolution Protocol (ARP) support. 8.2. Supported SMBus Commands � smbus_get_udid 8.3. Supported MCTP Commands 8.3.1. MCTP Control Messages � mctp_set_endpoint_id � mctp_get_endpoint_id � mctp_get_endpoint_uuid � mctp_get_mctp_version_support � mctp_get_message_type_support � mctp_get_vendor_defined_message_support Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2015 Registered 8. PLDM Commands for the Board Management Controller DS-1054 | 2019.05.30 8.4. Supported PLDM Commands 8.4.1. PLDM Base Specification Commands � pldm_settid � pldm_gettid � pldm_getterminusuid � pldm_getpldmversion � pldm_getpldmtypes � pldm_etpldmcommands 8.4.2. PLDM for Platform Monitoring and Control Specification Commands � pldm_settid � pldm_gettid � pldm_setnumericsensorenable � pldm_getsensorreading � pldm_getsensorthresholds � pldm_setsensorthresholds � pldm_restoresensorthresholds � pldm_getsensorhysteresis � pldm_setsensorhysteresis � pldm_getpdrrepositoryinfo � pldm_getpdr 8.5. Defined Platform Descriptor Records 71 Platform Descriptor Records (PDRs) for A10SA4 rev 26815 � NumericSensorPDR_1 � NumericSensorPDR_2 � NumericSensorPDR_3 � NumericSensorPDR_4 � NumericSensorPDR_5 � NumericSensorPDR_6 � NumericSensorPDR_7 � NumericSensorPDR_8 � NumericSensorPDR_9 � NumericSensorPDR_10 � NumericSensorPDR_11 � NumericSensorPDR_12 � NumericSensorPDR_13 Intel� Programmable Acceleration Card (PAC) with Intel� Arria� 10 GX FPGA Data Sheet 28 Send Feedback 8. PLDM Commands for the Board Management Controller DS-1054 | 2019.05.30 � NumericSensorPDR_14 � NumericSensorPDR_15 � NumericSensorPDR_16 � NumericSensorPDR_17 � NumericSensorPDR_18 � NumericSensorPDR_19 � NumericSensorPDR_20 � NumericSensorPDR_21 � NumericSensorPDR_22 � NumericSensorPDR_23 � NumericSensorInitializationPDR_1 � NumericSensorInitializationPDR_2 � NumericSensorInitializationPDR_3 � NumericSensorInitializationPDR_4 � NumericSensorInitializationPDR_5 � NumericSensorInitializationPDR_6 � NumericSensorInitializationPDR_7 � NumericSensorInitializationPDR_8 � NumericSensorInitializationPDR_9 � NumericSensorInitializationPDR_10 � NumericSensorInitializationPDR_11 � NumericSensorInitializationPDR_12 � NumericSensorInitializationPDR_13 � NumericSensorInitializationPDR_14 � NumericSensorInitializationPDR_15 � NumericSensorInitializationPDR_16 � NumericSensorInitializationPDR_17 � NumericSensorInitializationPDR_18 � NumericSensorInitializationPDR_19 � NumericSensorInitializationPDR_20 � NumericSensorInitializationPDR_21 � NumericSensorInitializationPDR_22 � NumericSensorInitializationPDR_23 � SensorAuxiliaryNamesPDR_1 � SensorAuxiliaryNamesPDR_2 � SensorAuxiliaryNamesPDR_3 � SensorAuxiliaryNamesPDR_4 � SensorAuxiliaryNamesPDR_5 Send Feedback Intel� Programmable Acceleration Card (PAC) with Intel� Arria� 10 GX FPGA Data Sheet 29 8. PLDM Commands for the Board Management Controller DS-1054 | 2019.05.30 � SensorAuxiliaryNamesPDR_6 � SensorAuxiliaryNamesPDR_7 � SensorAuxiliaryNamesPDR_8 � SensorAuxiliaryNamesPDR_9 � SensorAuxiliaryNamesPDR_10 � SensorAuxiliaryNamesPDR_11 � SensorAuxiliaryNamesPDR_12 � SensorAuxiliaryNamesPDR_13 � SensorAuxiliaryNamesPDR_14 � SensorAuxiliaryNamesPDR_15 � SensorAuxiliaryNamesPDR_16 � SensorAuxiliaryNamesPDR_17 � SensorAuxiliaryNamesPDR_18 � SensorAuxiliaryNamesPDR_19 � SensorAuxiliaryNamesPDR_20 � SensorAuxiliaryNamesPDR_21 � SensorAuxiliaryNamesPDR_22 � SensorAuxiliaryNamesPDR_23 � TerminusLocatorPDR � FRURecordSetPDR_0 8.6. Sensor and Threshold Information Refer to Device Peripheral Table for a list of the peripherals, currents and voltages that can be monitored through the BMC. Note: Although the PLDM commands use device IDs based at 1, the Device Peripheral Table lists device IDs based at 0(2) in the ID (DEV/PDR) column. Therefore, when referring to a device ID in the table, you must add 1 to obtain the device ID used by the PLDM commands. For example, the board power ID is listed as 0 in the Device Peripheral Table, while PLDM commands use 1. Related Information Device Peripheral Table on page 24 (2) as shown by the Bittware tools and the fpgainfo command Intel� Programmable Acceleration Card (PAC) with Intel� Arria� 10 GX FPGA Data Sheet 30 Send Feedback DS-1054 | 2019.05.30 Send Feedback A. Regulatory Information Regulatory Model Number: 10AX115 United States Federal Communications Commission (FCC) Class A User Information The Class A Product: Intel Programmable Acceleration Card with Intel Arria 10 GX FPGA complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: 1. This device may not cause harmful interference. 2. This device must accept the interference received, including interference that may cause undesired operation. Attention: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to Part 15 of the FCC rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with other instrcutions, may cause harmful interference to radio communications. Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to correct the interference is at his/her own expense. Caution: If this device is changed or modified without permission from Intel, the user may void his or her authority to operate the equipment. VCCI Class A Statement BSMI Class A Statement Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2015 Registered Republic of Korea KCC Notice Class A A. Regulatory Information DS-1054 | 2019.05.30 Canada EMC Compliance Statement This Class A digital apparatus complies with Canadian ICES-003. Cet appareil num�rique de la classe A est conforme � la norme NMB-003 du Canada. European Community Manufacturer Declaration Belgium Par la pr�sente, Intel Corporation d�clare que la carte Intel PAC with Intel Arria 10 GX FPGA est conforme aux directives 2014/30/UE, 2014/35/UE et 2011/65/UE. Att. Corp Quality, Intel Deutschland GmbH, Am Campeon 10-12, Neubiberg, 85579 Germany Le texte int�gral en anglais de la d�claration europ�enne de conformit� est disponible � l'adresse suivante: Declaration of Conformity Denmark Intel Corporation erkl�rer hermed, at Intel PAC with Intel Arria 10 GX FPGA overholder direktiverne 2014/30/EU, 2014/35/EU og 2011/65/EU. Att. Corp Quality, Intel Deutschland GmbH, Am Campeon 10-12, Neubiberg, 85579 Germany Den fulde tekst for EUs overensstemmelseserkl�ring findes p� engelsk p� f�lgende adresse: Declaration of Conformity Intel� Programmable Acceleration Card (PAC) with Intel� Arria� 10 GX FPGA Data Sheet 32 Send Feedback A. Regulatory Information DS-1054 | 2019.05.30 Netherlands Intel Corporation verklaart hierbij dat Intel PAC with Intel Arria 10 GX FPGA in overeenstemming is met de richtlijnen 2014/30/EU, 2014/35/EU en 2011/65/EU. Att. Corp Quality, Intel Deutschland GmbH, Am Campeon 10-12, Neubiberg, 85579 Germany De volledige Engelse tekst van de EU-conformiteitsverklaring is hier beschikbaar: Declaration of Conformity Germany Hiermit erkl�rt die Intel Corporation, dass die Intel PAC with Intel Arria 10 GX FPGA den Richtlinien 2014/30/EU, 2014/35/EU und 2011/65/EU entspricht. Att. Corp Quality, Intel Deutschland GmbH, Am Campeon 10-12, Neubiberg, 85579 Germany Die vollst�ndige EU-Konformit�tserkl�rung ist in englischer Sprache unter der folgenden URL einsehbar: Declaration of Conformity Sweden H�rmed intygar Intel Corporation att Intel PAC with Intel Arria 10 GX FPGA �verensst�mmer med direktiven 2014/30/EU, 2014/35/EU och 2011/65/EU. Att. Corp Quality, Intel Deutschland GmbH, Am Campeon 10-12, Neubiberg, 85579 Germany Den fullst�ndiga engelska texten f�r EU-�verensst�mmelsen finns p� f�ljande internetadress: Declaration of Conformity Finland Intel Corporation vakuuttaa t�ten, ett� Intel PAC with Intel Arria 10 GX FPGA on direktiivien 2014/30/EU, 2014/35/EU ja 2011/65/EU m��r�ysten mukainen. Att. Corp Quality, Intel Deutschland GmbH, Am Campeon 10-12, Neubiberg, 85579 Germany EU-vaatimustenmukaisuusvakuutuksen koko englanninkielinen teksti on saatavilla osoitteessa: Declaration of Conformity Ireland Hereby, Intel Corporation declares that the Intel PAC with Intel Arria 10 GX FPGA is in compliance with Directives 2014/30/EU, 2014/35/EU and 2011/65/EU. Att. Corp Quality, Intel Deutschland GmbH, Am Campeon 10-12, Neubiberg, 85579 Germany The full text of the EU declaration of conformity is available at the following URL: Declaration of Conformity Send Feedback Intel� Programmable Acceleration Card (PAC) with Intel� Arria� 10 GX FPGA Data Sheet 33 A. Regulatory Information DS-1054 | 2019.05.30 Portugal A Intel Corporation declara, por este meio, que a Intel PAC with Intel Arria 10 GX FPGA cumpre as Diretivas 2014/30/UE, 2014/35/UE e 2011/65/UE. Att. Corp Quality, Intel Deutschland GmbH, Am Campeon 10-12, Neubiberg, 85579 Germany Pode consultar o texto da declara��o de conformidade da UE na �ntegra, dispon�vel em ingl�s atrav�s do seguinte URL: Declaration of Conformity Spain Por la presente, Intel Corporation declara que Intel PAC with Intel Arria 10 GX FPGA cumple las directivas 2014/30/UE, 2014/35/UE y 2011/65/UE. Att. Corp Quality, Intel Deutschland GmbH, Am Campeon 10-12, Neubiberg, 85579 Germany El texto completo (en ingl�s) de la declaraci�n de conformidad de la UE est� disponible en la siguiente URL: Declaration of Conformity France Par la pr�sente, Intel Corporation d�clare que la carte Intel PAC with Intel Arria 10 GX FPGA est conforme aux directives 2014/30/UE, 2014/35/UE et 2011/65/UE. Att. Corp Quality, Intel Deutschland GmbH, Am Campeon 10-12, Neubiberg, 85579 Germany Le texte int�gral en anglais de la d�claration europ�enne de conformit� est disponible � l'adresse suivante: Declaration of Conformity Italy Con il presente documento, Intel Corporation dichiara che la scheda di accelerazione programmabile Intel PAC with Intel Arria 10 GX FPGA � conforme alle direttive 2014/30/EU, 2014/35/EU e 2011/65/EU. Att. Corp Quality, Intel Deutschland GmbH, Am Campeon 10-12, Neubiberg, 85579 Germany Il testo completo della dichiarazione di conformit� UE in lingua inglese � disponibile al seguente indirizzo: Declaration of Conformity United Kingdom Hereby, Intel Corporation declares that the Intel PAC with Intel Arria 10 GX FPGA is in compliance with Directives 2014/30/EU, 2014/35/EU and 2011/65/EU. Att. Corp Quality, Intel Deutschland GmbH, Am Campeon 10-12, Neubiberg, 85579 Germany The full text of the EU declaration of conformity is available at the following URL: Declaration of Conformity Intel� Programmable Acceleration Card (PAC) with Intel� Arria� 10 GX FPGA Data Sheet 34 Send Feedback A. Regulatory Information DS-1054 | 2019.05.30 Poland Firma Intel Corporation niniejszym owiadcza, e karta Intel PAC with Intel Arria 10 GX FPGA jest zgodna z dyrektywami 2014/30/UE, 2014/35/UE i 2011/65/UE. Att. Corp Quality, Intel Deutschland GmbH, Am Campeon 10-12, Neubiberg, 85579 Germany Pelny tekst deklaracji zgodnoci z wymogami UE w jzyku angielskim jest dostpny na stronie: Declaration of Conformity End-of-Life/ Product Recycling Product recycling and end-of-life take-back systems and requirements vary by country. Contact the retailer or distributor of this product for information about product recycling and/or take-back. Regulatory Markings Send Feedback Intel� Programmable Acceleration Card (PAC) with Intel� Arria� 10 GX FPGA Data Sheet 35 Hazardous Substances Table A. Regulatory Information DS-1054 | 2019.05.30 Intel� Programmable Acceleration Card (PAC) with Intel� Arria� 10 GX FPGA Data Sheet 36 Send Feedback DS-1054 | 2019.05.30 Send Feedback B. References Related Information Intel Arria 10 GX/GT Device Errata and Design Recommendations This errata sheet provides information about known device issues affecting Intel Arria 10 GX/GT devices. It also offers design recommendations you should follow when using Intel Arria 10 GX/GT devices. Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2015 Registered DS-1054 | 2019.05.30 Send Feedback C. Document Revision History for Intel Programmable Acceleration Card (PAC) with Intel Arria 10 GX FPGA Data Sheet Document Version 2019.05.30 2019.03.26 2018.12.04 2018.08.16 2018.08.06 2018.04.11 2018.01.22 Changes � Updated Figure: Intel Programmable Acceleration Card with Intel Arria 10 GX FPGA. � Updated Appendix: Regulatory Information. Updated Views of the Intel PAC with Intel Arria 10 GX FPGA on page 5. Removed reference to ECC from PAC block diagram. � Updated for Acceleration Stack version 1.2. Maintains support for Acceleration Stack version 1.1. � Updated BMC version with support for PCIe update � Added PLDM Commands for the Board Management Controller chapter � Updated the following sections: -- FPGA Interface Manager in the FPGA Interface Manager chapter -- BMC Voltage and Thermal Handling in the Board Management Controller chapter -- BwMonitor in the Board Management Controller chapter -- Updating the BMC Configuration and Firmware in the Board Management Controller chapter � ECC not supported in on-board memory � Clarified: BMC communication based on PLDM for Platform Monitoring and Control � Terminology correction: previously SDR, now PDR Corrected broken link in FPGA Interface Manager. Updated the following sections: � Introduction � Block Diagram � QSFP+ � System Compatibility � Interfaces and Dimensions Added substantial content to the Board Management Controller chapter Updated the following sections: � On-Board Memory on page 6 � QSFP+ on page 7 � Power on page 7 � Board Management Controller on page 18 � System Compatibility on page 10 � Mechanical Information � Thermal Specifications on page 15 Updated the following sections: � Introduction on page 3 � On-Board Memory on page 6 � Interfaces and Dimensions on page 6 � Power on page 7 � CPLD on page 7 � Board Management Controller on page 18 continued... Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2015 Registered C. Document Revision History for Intel Programmable Acceleration Card (PAC) with Intel Arria 10 GX FPGA Data Sheet DS-1054 | 2019.05.30 Document Version 2017.11.03 Changes � Mechanical Information � Thermal Test Performance Results on page 15 � Regulatory Information on page 31 Initial Release Send Feedback Intel� Programmable Acceleration Card (PAC) with Intel� Arria� 10 GX FPGA Data Sheet 39