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Technical Reference Manual
Part No. 2223216-0001, Rev. A
INSTRUMENTS
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Copyright © 1984 Texas Instruments Incorporated All Rights Reserved -- Printed in USA
The information herein and patents which might be granted thereon disclosing or employing the materials, methods, techniques or apparatus described herein are the exclusive property of Texas Instruments Incorporated.
No copies of the mformanon or drawmgs shail be made without the pnor copsent qfl'lfe_xq's Instrumeg\;ts
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Address all correspondence regarding orders to: Texas Instruments Incorporated Data Systems Group P.O. Box 1444, M/S 7793 Houston, TX 77251
TECHNICAL REFERENCE -
PREFACE
PREFACE
The Technical
-ence
design
and function of
is intended for use by
technlcal persons,
anuatl contp?ns
detailed
1hform§txoh .on
the
the Texas Instruments Professional Computer and
software
and
hardware
des:gnars
and other
This manual is divided into six major sections:
Section
1.
Instruments
Introduction Professional
- Provides Computer
a
general
< Qe?crxpgxon,,
9 the Texas
and
1dent1f1e=n L A& Boan vprxous
configurations,
options,
and accessories.
This
tables listxng environmental requxrements for the
section also system, t;m
1nb1udes !
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Section
4.
Device
Service
Routines
5
interrupt vecfor lists, and a keyboard scan
Cigie
Descrxbes
the
dod;ng table.
R
ROM, e,
.gives | [
Section S. Assembly
Drawings
detailed
drawings for all field
List
of
accompanies
Materials,
identifying
each assembly draving
"C'
7
i
and. Lists
-of-wHatefials«~--- Inmcludes
replaceable assemblies and options.
A
all
components- »and""pr!cE""'parts,
e R (a
"J'fl
R
8.étlon 6. schematigs
Schemnt:cs
for
each
pnd Loglc Dravans = component - and fiel
Texas Instruments Professional Computer.TM
Jlogrc S
QPiaEqTrY`dasfi
atnhde
§
t
The
appendixes
provide
reference intormation, such
all /0 addresses, and a complete memory map (covernng
all memory connected to the
bus).
Also
included
are
furnished with the computer
between the various options
expansion bus,
and
the
complete information on
and a breakdown
of
the
and printed wiring boards.
as defxnitldns of
the motherboard
memory
expansion
the cha}acter sets
power 'allocation
:
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TECHNICAL REFERENCE
CONTENTS
Section
Preface
1
1.1 TP
1.1.2
1.1.3 1.2
1.2.1 1.2.2 1.2.3 1.2.4
1*2S, 1.2.6
oot/ 1.3
Table of Contents
Title
Page
iii
INTRODUCTION .
.
o
o
.
.
.
.
.
.
`Hi=]
SYSTEM COMPONENTS
.
.
.
.
o
.
.
'
. 1-1
Keyboard.
o
&
S
n
o
o
o
o
.
.
. 1-1
System Unit.
0
.
s
.
o
.
6
.
&
. 1-2
Display Unit
.
5
o
.
.
5
.
.
.
. 1-2
OPTIONAL COMPONENTS.
S
.
o
.
o
.
.
o 1-2
Diskette Drive
s.
o)so o..
1=-3
Hinchester Disk Drive
e ea H. .
1-3
Expansion Memory Boards.
. . g = a
1=3
Synchronous-Asynchronous
Communications Board .
.
3
3
.
.
=3
Internal Modem Boards
) 5 S o . . mls3
Graphics Video Controller Board .
.
.
. 1-4
Color Display Unit
o
&
o
2
3
.
T
. 1-4
ENVIRONMENTAL CONDITIONS .
s
.
5
.
.
. 1-4
2
2.1 2.2
2.2.1 2.2.2 2.2.3
2.2.4
2.2.5 2.2.6 2.2.7
2.3 2.4
2.4.1
2.4.2
2.4.2.1 2.4.2.,2 2.4.2.3 2.4.2.4 2.4.2.5 2.4.3 2.4.3.13 2.4.3.2
2.4.3.3
2.4.3.4 2.4.4 2.4.5 2004 IS VY
SYSTEM HARDWARE
INTRODUCTION .
.
e
B
.
.
.
.
.
5
2=l
KEYBOARD
.
a
.
o
o
.
.
S
.
=, 2-3
Encoding Keystrokes . 5 . . .
2-3¢
Transmission
5
E
a o .
2~-3
Receiving and Respond:nq to system o7l
Unit Commands
. ?
3
g e .
2-4
Implementing a Software- watchable
Repeat-Action Function
o . s 3 o
2-6
Performing n-Key Rollover . s o . 6
2-6
Locking/Unlocking the Keyboard
. 0 o
2-7
Performing a Self-Test . o 4 d s . . 2=7
SYSTEM UNIT BOARD
o
.
o
2
6
.
S
g
. 2~8
SYSTEM SUPPORT
.
e
o
.
o
.
s
.
.
. 2-10
Keyboard Port .
:
g
a
e
.
a
d
o
. 2-10
System CPU .
.
)
AR
.
.
.
.
. 2-113
Optional Numerlc Coprocessor
S e . 21
CPU Clock Generator
o . . g z & m2-11
CPU Bus Buffering . . . . . . g . 2-13
CPU Bus Controller.
a . o o . e . 2-12
Reset Detection Circuit .
o : b
2=12
Motherboard Input/Output System : it o L2212
I/0 Decoding.
o o
. a o » . 2-15
Parallel Printer Port'
S s 0 6 0 . 2-16
Timers.
.
o
a
S
e
a
.
.
. 2-18
Speaker Amplif:er ) a
e o o R `H2=18
Motherboard Interrupt 5ystem o n e S . 2-18
Motherboard Memory System . 5 0 . a . 2-20
Motherboard Memory Addressing .
o
5
. 2-20
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TECHNICAL REFERENCE
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Memory Control Logic
CAS and Address Multiplexer Sv;tch
Parity Generation and Checking.
Memory Control State Machine Floppy Disk Controller
Floppy Disk Controller IC
Sector Buffer
Write Precompensation C1rcu1t
`Data Separator
Diskette Drive Interface.
Diskette Drive
CRT Controller B oard.
Display Characteristics
Character Attributes
Character Sets
Cursor.
.
.
Scrolling.
"Video Connecto r.
.
CRT Controller IC.
CRT Screen/CPU Arh;tratlon Logic
Subsystem . °
CRT Address Decode Log1c
5
Character Set and Attribute Logzc.
Generating a Character ROM
B
.~ Attribute Interaction.
Attribute Hardware.
CRT Interrupt Logic Subsystem
Diagnostic Loopback
g
EXPANSION BUS.
Expansion Bus'Sagnal Descriptxons
Loading and Driving Requzrements.
Memory Timing . I/0 Timing . .
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. +o222E5-:222263 2-26
. 2-26 . 2-30
2-30 "2-31 "2.35 .'ziav . 2341
. .2-42
. 2-43
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HARDWARE OPTIONS
INTRODUCTION
:
EXPANSION MEMORY,
v
siz2/76é8 K BYTES
Addressing the Expansion Memory
Expansion Memor$ Control Logic. Expansion Memory Refresh Logic
CAS and Address MUX Switch Generation.
Expansion Memory Parity Generation
and Checking -Expansion Memory Control state Machine
SYNCHRONOUS -ASYNCHRONOUS COMHUNICATIONS
:
BOGARD.
o
TiSystem Interface
Badd Rate Genera tion.
Addressing
Programming.
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" TECHNICAL REFERENCE
CONTENTS
-suction
3.4 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.4.6 3.4.6.1 3.4.6.2 3.4.7
3.5 3.5.1 3.5.2 3.5.3 3,.5.4 L3 3.6.1 3.6.1.1 IT6MIN2 3.6.1.3
]
3.6.1.4
3.6.1.5 3.6.1.86 3.6.1.7
3.6.2 3.6.2.1 3 %622 3.6.2.3 3.6.2.4 3.6.2.5 3.6.2.6 3¥ETM3 3.6.4 3.6.5 3.6.6 3.6.6.1
3.6.6.2
3.8.6.3 3.6.6.4 3%i6-i6h S 3.6.6.6 366l 7 3.6.6.8
33.66.66..910
3.6.6.11 3.6.6.12 3.6.6.13 3.6.7 3.6.8 3.6.9
3.6.1
3.6.1
- 0
Title
Page
M
INTERNAL MODEMS .
o
o
.
.
¥
s
.
S
. 3-14
Architecture
SR
.
oO e G
.
.
2 »3-18
Zilog 8530--Modem ngnals .
il
o AT 3~15
Modem Initialization.
a e
o
5
o .3-18
Command Mode Operation .
.
q
.
e
&
= 3-18
Dialing Procedure.
P
e s 8
3-18
Time-Outs
S o
.
S
o
SRR i3-20
Terminal or Softvare Tlme Outs
s s . 3-21
Modem Time-Outs
. "s . . o . . & 3-21
Modem Software.
o
-og .
3-22
GRAPHICS VIDEO CONTROLLER BOARD
g
o
S
Pixel Addressing . ST
o .
Color Selectiong . . 5 s .
Timing and Synchronization.
LR
Graphics Logic Array Program
WINCHESTER DISK DRIVE Winchester Hardware
AND CONTROLLER OPTION Theory of Operation;
On-Board EPROM/ROM.
.
o
s
5
.o
Commands and Command Testxng S
4
Explanation of Bytes in the Devxce
Control Block.
. .
-
k
3-24 -3-26 3-27 3-31 3-33 13-34 ..3-34 3-34 3-35
3-3S5
Control Field Detailed Descr:ptxon
<
3-36
Command Completion Status Byte.
g 3-37
Logical Address (HIGH, MIDDLE and Low) ' 3-37
Sector Interleav:ng
AT e e
g
L3, 2-37
Register Assignments.
=
S
.
.
B
3-38
Data Input Port.
- 5 .
i3
. s 3 3-39
Data Output Port
. 7
. o
& 3-389
Controller Status- Reglster
.
T . ' 3-39
Reset Port
4
o
.
a
T
S & 3-39
Interrupt Mask .
TN
ot oy S . s 3-40
Error Status Byte . o
-
L 3-40
Bit Definitions for Reg:sters and Ports
3-40
Controller Status Bit Combinations . 4 = 3-42
Normal Command Sequence; Operatipn: . o
Detailed Description of Commands.
o 5
3-43 3-44
TEST DRIVE READY Commangd.
S gi o
S
3 3-44
RECALIBRATE DRIVE Gopmand, .
o
2
.
3-44
REQUEST SENSE STATUS . Command
a
s
S
3-44
FORMAT DRIVE Command.. ... . ..,
a L 5 3-51
CHECK TRACK FORMAT .Command . ..
g
. 3-S2
FORMAT TRACK Command
s
o
.
)
=T, 3-53
FORMAT BAD TRACK Command. . .
s
o
.
` 3-54
READ Command.
3-5§
SWEREIKTE CoCmommamnadn.d
i
3-55 3-56
INITIALIZE DRIVE CHARACTERISTICS Commsnd 3-57
READ ECC BURST ERROR LENGTH Ggommand
3-58
FORMAT ALTERNATE TRACK Command.,.
3-60
Alternate Track Assignment.
. eI
. . 3-61
Alternate Address Protocol.
s . g & S 3-62
WRITE SECTOR BUFFER Command
3-64
READ SECTOR BUFFER Commangd.
RAM DIAGNOSTICS Command.
o
3-64 3-65
=viie
TECHNICAL REFERENCE
CONTENTS
»
> >
PR ERDDRREREEDBRARDEBLEPE TR PEEEALLAELLE SRS EdbEEDbA
Se;tio n
3.6.12 33..66..1134 3.6.15 33..66..1176 3.6.18 3.6.19 3.6.20
Title
DRIVE DIAGNOSTICS Command . . .
CONTROLLER INTERNAL DIAGNOSTICS Command
READ LONG Command.
&oS .o
WRITE LONG Command
. .
a a
Execution Order of Rema;ning Diagnostxc
Error Correction Philosophy
. o
Sector Field Description
s &
Specifications -~ Controller Board
Electrical Interface.
5 g S s
Page
#-65
3-663-66 3-67° 3-68" 3-68 3-69 3-71 3-72"
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DEVICE SERVICE ROUTINES
ROM INTERFACE INFORMATION,.
. ..
WRITING SOFTWARE FOR COMPATIBILITY NITH
FUTURE PRODUCTS
.
a
.
.
o
o
Compatibility Levels.
8
o
o
o
Operating System
.o o
S
System ROM Interface . o
Hardware Interface.
o
s
Areas of Hardware Compatxhility s
Alphanumeric CRT
.
o
o
a
3
Graphics CRT.
.53= !8
Disk Subsystem . . . 3 o 3
Keyboard System.
e
o
S
3
S
Interrupt Controller . e 0 3
System Timers and Speaker
Parallel Printer Port.
4 b
Serial Communications.
S
.
SYSTEM ROM INTERRUPT VECTOR USAGE
Hardware Interrupt Service Routines.
_Common Interrupt Exit Vector .
Timer Interrupts'
e o
s
ROM STRUCTURE.
.
.
S
.
.
o
ROM Usage
2 oeSo
ROM Format . o . .
Option ROM Interrupt Vector Usage
RAM Usage by Option ROM.
o a
Initializing the Option ROM
BOOTING UP THE SYSTEM .
.
.
Boot Sequence . 9
.
Loading and Calling the Boot Code
Booting From an Option Device.
SYSTEM CONFIGURATION FUNCTION CALLS System Configuration Function.
Extra System Configuration Function.
Get Pointer to System Configuration.
Get Pointer to Extra System Configuration.
GENERAL PURPOSE ROM FUNCTIONS
Delay.
.
8 .
CRC calculation
Ss 5
Print ROM Message.
s
o
.
Digsplay System Error Code " b
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-viii
.TECHNICAL REFERENCE
AL PLLALEDIDRILLRMD
= 0WVLVOYWOD®®ODO®D®D
Secti on
4.10. 4.10. 4.10.
.10 .11 .12 .13 .14 .15 .16
4.10. 17 4.10. 18 4.10. i9 4.11 4.11. 4.11. 4.11. 4.11. 4.11. 4.11. 4.11. 4 N11 4.11. 4.11. 4.11. 4.11. 12 4.11. 13 4.11. 14
=
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Title
SPEAKER DSR
.
o
.
o
.
a
a
.
P
d
Sound the Speaker - AH = 0.
g s o a
Get Speaker Status
<~ AH = 1.
b ?
Set Speaker Frequency
- AH = 2.
. .
Speaker ON =~ AH =3 . ., ., ",
Speaker OFF - AH = 4
5 o R
e
TIMENOEMDA YHCLOCKRDS RIS UE N R
Set the Date
Set the Time
- AH = O.
- AH = 1.
o 5 9 o
. . ..
Get the Date and Time
- AH = 2,
s
CRT DSR.
o
o
8
s
5
4
3
&
o
o
Set Cursor Type -~ AH = O1lH.
. . .
Set Cursor Position - AH = O2H
.
o
S
Read Cursor Position - AH = O03H . a £
Scroll Text Block - AH = 06H and 07H
.
Read Character/Attribute at Curaor
Pogition - AH = 08H
. .
&
Write Character/Attribute at Cursor
Position - AH = OS9H . S & . o o
Write Character at Cursor
¢
WriPtoesitAiSoCnII - TeAHlet=ypeOAH - A. H =a OEGH e.
Hrite Block of Characters at Cursor
With Attribute - AH=10H . . . o s
WriPtoesitBiloonck - ofAH Ch= ar1a1cH ters. O. nl.y a`t0T Cu| rsor
Change Screen Attribute(s) - AH = 12H
Clear Text Screen and Home the
Cursor - AH = 13H , . SR
a
Clear Graphics Screen(s) - AH = 14H.
Set TTY Status Region Beginning -
AHE =R H
e
e A L sl
Set Attribute(s) - AH = 16H . . .
GetAHE Ph=y1s1i7cHaRl Display- Begln Poxnteer y =
Print TTY String - AH = 18H S
A il
CRT TTY Mode Behavior
. i- 3 5 o
DISCKustDoSmR Enc. odi. ng of thRe CeRT. _. 0
.
.
Reset Disk System ~ OOH.
O 1O
Return Status Code - O1H
, .
A
Read Sectors - 02H
. .
UL
.
Hrite Sectors -03H
. o o a o S o
Verify Sector CRCs - 04H . E e S
Null Operation - OSH. Verify Data,-"O06H.-1"
a a o B g8
Return Retry Status - 07H g A
' s
Set Standard Disk Interface Table ~ 08H
Set DIT Address for Drive - O09H
b .
Return DIT Address for Drive - OAH
Turn Off All Diskette Drives - OBH
Status Codes
.
.
.
.
.
Disk Interface Tables (DITs) . o G
--ix=-
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CONTENTS Page
4-18 4-18 4-19 4-19 4-194-19 4-20 4-20 f44--22105"¢
4-21 4-23 4-24 4-24 4-2S 4-27
4-39°
4-40 44--4400" 4-41"
TECHNICAL REFERENCE o5
1y
5
CONTENTS
Section
4.12
4.12.1
Title
Page- -
KEYBOARD DSR . .
Initialization Log;c
N
T S A)
9
s
8
5
5
o
. 4-44:;&
4.12.2 4,12.3 4.12.4 4.12.5 4.12.6 4.12.7
4.12.8 4.12.9 4.12.10 4.12.13 4.12.12 4.12.13 4.12.14 4.12.15 4.12.15.1 4.12.15.2 4.12.15.3 4.12.15.4 4.12.15,5 4.12.16 4.12.17 4.13 4.13.1
4.13.2
4.13.3
4.13.4 4.14 4.14.1 4.14.2 4.14.3 4.14.4 4.14.5 4.14.6 4.14.7 4.14.8 4.14.8.1 4.14.8,2 4.14.8.3 4.14.8.4 4.14.8.5 4.14.8.6 4.14.8.7 4.14.8.8
4.14.8.9
Read Keyboard Input - AH = 0 . e o . . 4-44. . 3
Read Keyboard Status
- AH = 1 . o o . 4-45;+;
Read Keyboard Mode
- AH = 2.
. . . . 4-45;:
Flush Keyboard Buffer
- AH = 3.
. 5 . 4-46:: -
Keyboard Output
- AH = 4.
5
S o . 4-46 .
Put Character Into Keyboard Buffer -
).
AH = §.
.
General Keyboard Layout.
B
.
.
.
o
. 4-47
o S S o e . 4-48
Character Codes
.o .
e o e a S . 4-49
Extended Codes.
5 S s 5 S S . . . 4-52
Keyboard Modes.
) o o o S s s 3 . 4-53
Type-Ahead Buffer.
S
3 fi
s
3
a
.
. 4-53
Repeat-Action Feature
o . . . o o . 4-54
Special Handling . b
a S o o o . 4-54
User~-Available Interrupts s 0 5 o g . 4-55
Keyboard Mapping
. o o S a . s . 4-55.
Program Pause
. S
2
=
s
B
s
o
. 4-SS
Program Break
. o 0 A 9 s e g . 4-S6
Print Screen.
S
o
.
S
S
.
.
8
. 4-56
Keyboard Queueing .
S
s
5
5
o
o
. 4-56
Custom Encoding
.
5 o g s B 5 . 4-S6
Keyboard Interface Protocol
s B . = . 4-57
PARALLEL PRINTER PORT DSR.
.
.
o
.
S
. 4-60
Qutput Character to Printer
-
4
AH = 0, DL = 0 .
o
.
S
o
.
.
S
. 4-60
Initialize Printer
=~
AH = 1, DL = 0 .
.
.
5
4
.
D
Return Printer Status
-
. 4-60
AH = 2, DL = 0 .
o
o
.
3
S
.
Use Under an Operatxng System.
. 3 0 .
HINCHESTER ROM
o
.
.
S
.
e
s
.
S
.
Limitations.
.
.
5
5
5
o
3
b
5
.
System Interface .
.
5
3
o
e
5
s
.
System RAM Usage .
a
.
.
o
.
o
o
.
Power-up Testing
o 5 3 s .
Booting from the Hinchester
o 2 . é .
Error Recovery.
.
o
o
s
B
.
S
4
.
Error Reporting
s
.
o
.
S
3
.
.
Hardware Interface Rout1nea
S
a .
Initialize Winchester Disk System
D .
Check KWinchester ROM Version
. . 3 .
Request Controller Error Sense.
. a .
Send HWinchester Controllier Command
. .
Gel Data From the Winchester Controller.
Write Data to the Hinchester Controller.
Get Status From Winchester Controller
.
Get and Compare Data From the
Winchester Controller . s
s 5 .
Enable Data and Status Interrupt
4-60 4-62 4-63 4-63 4~64 4-64 4-65 4-66 4-66 4-67 4-69 4-70 4-70 4-71 4-71 4-71 4-72 4-72
4-73
from Controller . 5 S s . o s . 4-73
- -
*TECHNIGAL REFERENCE
CONTENTS
Section
4.14.8.10 4.14.8.11
4.14.8.12
47.11485013
4.14.8.14 4.14.8.15
4.14.8.16
4.14.8.17
Title
Page
Enable Status Interrupt From Controller.
Disable Data and Status Interrupt From
Controller.
:
o s 2e .
Poll for Controller Request
o &e .
Format a Track . P 0
5 SRR
Format an Alternate Track
o e s0 .
Format a Track as Bad.
e& e yb.
Check the Track Format
. . . ., 1%, |,
Format a Winchester Drive
. 5 o. .
4-73
4-74 4-74
427
4-7S 4-75
4-76
4-76
5
"ASSEMBLY DRAWINGS AND LISTS OF MATERIALS
.
.
< 54{
6
SCHEMATICS AND LOGIC DRAWINGS .
.
S
.
. 6=1
APPENDIXES
A
B
C;
D
E
System 1/0 Map.
g 3 3 "Wal-
3 .
System Memory Map.
g
3
3
s
o
.
Character Set . a o . 5 5 i
F
Current Requirements.
Asynchronous COmmunxcatxons gample
Program
R
. ShEnrt
o 3
Modem Sample Routlnes
s s
A
Boot Routine and Sample Assembly Code
Sample Interrupt Service Routine.
. A-1
WB-1
c~-1
D-1
E U F, . G-
H
T aom -
-%i-
TECHNICAL REFERENCE
R
1LLUSTRAR 1OKS
Figure
No.,
List of Illustrations
Title
2-¥
2-2
2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10
System Block Diagram.
oo9o ao0 0 s
Motherboard Block Diagram . . . . . . . .
Memory System Timing Diagram . 5 o o 5 & o
Floppy Disk Timing Diagrams
s
o
Alphanumeric CRT Controller Boerd Block D1agram.
Alphanumerics State Machine Timing Diagram
.
Sample Character Font Definition.
. 9 o g .
Encoding Examples.
.
"
o
"
Expansion Bus Memory Interface Timing Dxegram
£
Expansion Bus I/0 Interface Timing Diagram
E o
3-1
Expansion Memory Timing Diagram . o S 6 o s
3-2
Sync-Async Comm Board Block Diagram. a8 oGt
3-3
Modem Hardware Interface
. q
» 5 s o
3-4
Zilog 8530--Modem Interface ngnals
5 o b S
3-S
Graphics Video Controller Board Block Diagram
.
3-6
Color Latch Byte . .
s . .
3-%
Graphics Video Controller Timlng Dxagram 5 s S
3= - Controller Operational Flowchart.
S . .
3-9
Control and Data Cabling for the Winchester stk'
Drive.
aa= e4og5soSs 5o
4-1
Register AL Drive Byte . 9
" g < s S
4~2
Byte Definition - Set Cursor Type
o
5
v
3
.
4-3
Byte Definition - Set Attr:bute(s)
L A a W
4-4° DIT Structure . .
SR S
4-5
Byte Definition - Keyboard Kodes
s
o s
4-6
General Keyboard Layout Showing Scan Codes
. B
4-7
`Byte Definition - Keycode . g
s a .
4-gwiotf Byte Definition - Return Prxnter Status
. . .
e
S O
et
LTy
SR
page'
2
H2=2
2-9
2-25 2-29 2-38 2-40 . 2-83° 2-54 . 2-60 2-61
3= 7,
BUEED)
. 3-18s . 3-16° . 3-25 . 3-29
3=32 . 3-42
o 3~72?
a 4-16? . 4-23°
4-32 RS~4 2
. 4-4S . 4-4g' . 4-59 . 4-62 -
=
vk
s
i
-E
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oc Daaiy
.
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£
T
Ik
L
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-xii=-
. TECHNICAL REFERENCE
TABLES
NMOROMRNNNMNDOMDODODNND b
H = OONOUAEWONP
I
14 -
3-15 3-16 3-17
H (=HOONOUNEWN
List of Tables
Title
Storage Conditions, Standard System.
e s Tin g D
Operating Conditions, Standard System . o
.
Storage Conditions,
System with Winchester stk
Operating Conditions,
System with Winchester
e
Disk . . B S > e s o o o a o 5 : s .
Keyboard Commands and Responses . . . . . {;
Map of the Motherboard I/0 Addresses
e
Input/Output Signals - HAL12L& Integrated C;rcuxt;.
Printer Port Pin-Out.
g o S o o . o
Interrupt Level Assignments
s5a oo .
Motherhoard Memory Map . o
ROM Access Times .
. ..
Memory Control state Hach1ne Logic - HALl16R4.
Programming for the HALIOLS8 Device . . . o
Internal Diskette Drive Connector Pin-out.
.
e
External Diskette Drive Connector Pin-Out.
o o
Diskette Drive Specifications.
9 . . . o qegte
VIDEO AC PARAMETERS .
.
.
.
.
.
.
S
agAeos
Color Video Connector Pin-Out. CRTC Programming Values.
o a RS . . . . .
Alphanumerics State Machine PAL . 5 s o 5 o e
CRT System Memory Map
. a 6 o a o 5 fy. o
:
Alphanumeric Decoding PAL . . . . s 5 ok
Color Map . . CRIER
IO
I
A ey
Expansion Bus Pin-Outs .
S
e
o
a
S
Lt s T
At syl
Expansion Memory Control State Machine Logic - | .
HAL16R4 . .
I
- TI R
=I es
Sync-Async Comm Board Baud Rate . . 3 c el atd
Sync-Async Comm Board Port Addresses
o 0
Channel B Pin-out for Z853¢
S o
o
Channel B Pin-out for Z8530 Interrupt Enable.
RS-232-C Connector Signals.
o a a 0
Modem Default Parameters
o E
o6. .S S
Types and Durations of Dlsconnects a
a
3
Commands from the Software to the Modem
. o
Response from the Modem to the Software
.
Diagnostic Status Indicators . 3 E s S s o 5
Color Combinations
.g 5 4s5s6 S = .
Bit Correlations . . 1
Aapo 4..
Default Vvalues of Color Latches a E 5 3 S o .
Programming for the Graphics State Machine HAL
Device Control Block Bit Diagram.
s s b 0 o
Command Descriptor Byte.
S e S S 3 & E 2
33333-----111112334 0, 33333-----2122218344 333333------233233805936
-xiii-
WWwwwwwwwww
www (bgSPRWSN
TECHNICAL REFERENCE
Table No.
Title
3-24 3-25 3-26 3-27
Winchester Controller 1I/0 Port Assignment.
o
Bit Definitions for Controller Registers and
Ports.
S
5
valid Bit COmbxnatlons for cOntroller status
Type O Error Codes, Winchester Disk.
& e d
Type 1 Error Codes, Controller Board
Types 2 and 3 Error Codes, Command and
Miscellaneous . . . S
Error Code Summary
2
.
o
5
.
.
2 iz
3
Sector Field Format . . o . . o o s
S12-Bytes-Per-Sector Format
s 5&
&
Winchester Controller Board Spec1f1catxons
4-13
4-x4
System Interrupt Vector Usage.
. . E o e
ROM Addresses and Suggested Uses.
S . . .
Pointer addresses and Descriptions . . . .
System Configuration Word-Bit Definition . .
Extra System Configuration Word 1 (BX).
0 o
CRT DSR Opcodes and Functions.
o 3 o . .
Disk DSR Opcodes and Functions
0 o 0 ; v
Error Codes.
. . . S g 0 =
Keyboard Commands.
s
o
.
2
5
Standard Keyboard Character Codes
.
.
.
Extended Function Codes.
e g o . .
RAM Segment Pointers.
s
:
s
z
-
z
-
Hinchester DSR Error Codes.
. 3 2 ; ' v
Displayed Error Codes
3~-41 3-42 3-46 3-47
o=DLPL OAOED I NLD®ED MR1E ADPLERDL WLD NN-t
P R
-N 1
-xiv-
TS ECHNICe AL REFERENCE
_
iINTROIDRLUECTTION
<
-~
P
Section 1
s
INTRODUCTION
1.1 SYSTEM COMPONENTS
c-L
That basic Texas Instruments Professional Computer system consists of
three major parts:
the keyboard,
the
system
wunit
(including rthe
diskette
drive),
and
a monochrome
display
unit.
A general
description of each is given in this section.
The available
options
are
also
briefly
information, refer
described to Section
in
this
section.
2, "System Hardware",
For more detajled and to Section B¢
"Hardwvare Options."
-
1.1.1
Kéyhoard
e
«
The low-profile keyboard is easy
to use.
The large,
sculptured,
paetttahrlhyeceopphsgheerawkvanearmuycimmbrttaeoowebrsaorlisr-ecdligtkhrfdceeoaaunutnapc.sttoXbipekoey~nscToufhoseenkdtegtryhrssoeomalsuasplakelreadeeyrbctohaaoaenlrnrcruduam.tlnehdagreietisdocprmla.aikiynneypAktaehcdryufebrieosvo=oanerr-gdkrteohymueaoprsverecilmgueouhsfsntteted.froustraibdeTetwe:wenXelteeveyoenrsf
Other keyboard features include:
* A full-length degrees.
tilt-bar,
adjustable
from S degrees to 1S
*
The sculptured, low-profile European 30-millimeter (mm)
Xeys,
which
comply
with
the
home row height requirements.
*
Tactile-designed
F and
J Xkeys,
"home" position on the alphanumeric
which help keys.
to locate
the
* A raised dot on the numeric keypad S, indicating the key.
center
*
A keyboard
microprocessor, 'vhich converts
character information and conducts keyboard
every power-up.
keystrokes into
diagnostics
on
() £ @ A 3 b - P
IEQ'!ICAL REFERENCE
INTRQDUCTION
1.1.2 System Unit
L ©
The
system
unit
is
the heart
of
the
computer.
Thd basfc
configuration includes the central processing unit (CPU), the floppy
disk
controller
(FDC),
a parallel printer port, a power supply, &
read-only memory (ROM), and 64K bytes (XK = 1024) dynamic random-
access
memory
(RAM).
standard equipment.
A cathode-ray
tube
(CRT)
controller
boar. ids,
Rih y
The system unit board is a 361.95 x 21S5.9-millimeter
(mm)
(14. 25 x
8.5S~inch (in)) printed wiring board (PWB) mounted horizontally on the
bottom
of
the
system
unit
chassis,
This
board
houses
thg
microprocessor and control logic.
It also supports an expansion.
bys
with
five
card-edge
connectors
for option
Dboards
and
another
connector for a memory expansion option.
The system unit power supply
with
three
output
levels.
every combination of options.
is a
It
switching-type,
will sustain a
110-watt
(W)
system equipped
unit
with L
The 5 1/4-in diskette drive is a mass storage device for
reading
or
writing
data
to a removable
diskette.
The Texas
Instruments
Professional
Computer
uses
a double-density,
modified
frequency
moduylation
(MFM)
recording
format.
This format requires certified
double-sided, dual-density, soft-sectored S 1/4-in
diskettes.
3
data
separation
logic
uses a phase-lock
fieliability.
The computer is equipped with one
can store approximately 320K bytes of data.
loop
technique
diskette drive, Vhlfib
2
1.1.3 Display Unit
ke
The display unit
Computer
is a
green
phosphor
furnished with the Texas
Instruments
Professional
high-resolution (720 x 300 pixels), composite video,
monochrome
unit.
The
standard
CRT
controller
contained
in the system unit supports eight intensity levels for the
djfiplay.
The display presents information in a 2S-line x 80-column
alphanumeric
format,
which
works well with the bit-mapped graphics
aption.
The display unit is
specially
adapted
to accomodate
the
horizontal scan rate of 19 200 lines per second
1.2 OPTIONAL COMPONENTS
There are
several
options
Professional Computer.
These
available
for
the Texas
Instfumedgg
options
`include
additional
320K-§x:e
diskette drives,
a Winchester
disk drive, expansion memory boards
(which can expand the system memory to 768K
bytes),
a synchronous-
asynchronous
communications board, internal modem boards, a graphics
video controller board, and a high-resolution color display unit.
A
general
description
of
each
of
these
options
is given
in the
1-2
FECHNICAL REFERENCE
`INTRODUCTION
P
following paragraphs. t% ERSCection 3, Hardware
SQE e
£.2.1 metr
Diskette Drive
If more detailed Options.
information
{s'needed,
feféf
L
YOy
£
L=At T
one' internal
diskette
drive
is standard
equipment for The Tegid
Instruments
Professional
Computer.
Enough
internal
space
is
available
to
install either a second diskette drive or a Hinchesten
&{sk drive.
You can also install two external drives.
:
Piskettes used Be certified
diskettes.
with the Texas double-sided,
Instruments Professional Computer
mdn{
dual- ~density,
soft-sectored,
S 1/4-in
:
1.2.2
MHWinchester Disk Drive
The Winchester disk drive and controller option is available
10-megabyte capacities.
You can install the Winchester disk
the space set aside for the second diskette drive.
.
L
in S-ror drive in
ii2.3 Expansion Memory Boards
The system unit board contains 64K bytes of dynamic RAM.
Adding
é'fianuion RA¥ Dboards can increase 788K bytes. First, use the expansion iNtb the memory connector on the
the system memory to RAM option boards
motherboard. These
a total 6{ that plug boards are
avajlable in 64K~, 128K-, or 192K-byte capacities.
After adding
the
192K-byte board (bringing the total to 256K bytes), further expansion
requires that you add a 256K-byte board that plugs into the expansion
bus.
To reach the 768K-byte total, another 256K-byte board attaches
(piggybnck style) to the board on the expansion bus.
L
1.N 2.4 Y SsSynchronous-Asynchronous Communications Board
1
i
Thé'synchronous-anynchronous communications (sync-async
comm) Boh(&
option
`'allows either
synchronous
or asynchronous
commthcarioni
through an RS-232~C interface.
The sync-async
comm
board
qupfivrr{
asynchronous data rates from S0 bits per second (bps) to 19 200 bps.
1.2.5
Internal Modem Boards
Two
versions
of
the
internal modem board option are available:
a
300-bps board providing Bell 103-compatible communication, and a
300;1200 -bps board providing Bell 212A-compatible communications.
O
Natedgay
&
s
EA iy
)
il
.
Feoi ] i LB
05
¥
:
:
et R
TECHNICAL REFERENCE
INTRODUCTION
1.2.6 Graphics Video Controller Board
The graphics video controller board option is available in either one
or
three
planes.
It provides a resolution of 720 horizontal by-300
vertical picture elements (pixels).
1.2.7
Color Display Unit
The
13-in
color display unit permits the display of high-resolution
(720 x 300 pixels) colors.
The standard CRT controller
located
on
the
system
unit
board
supports
eight
colors for the unit, vhich
presents information in a 25-line x 80-column format.
Used with
the
graphics
video
controller
board
option,
the
color
display unit
produces high-quality raster and character graphics.
1.3 ENVIRONMENTAL CONDITIONS
The next four tables list
environmental
conditions
for
the Texas
Instruments
Professional
Computer.
Table
1-1
1lists
the storage
conditions for a standard system.
(Storage assumes that
the
system
is enclosed
in
the
shipping
container.)
Table
1~2
1lists
the
operating conditions for a standard
system.
Table
1~-3 1lists
the
storage
conditions
for a system
that includes a Winchester disk.
THaibnlcehes1t-e4r
lists
disk.
the
operating
conditions
for a system that
¢
includes
a
«
Table 1-1 Storage Conditions, Standard System
Temperature Relative humidity shock
Vibration
Altitude
~-30 C to +70 C (50 C maximum for diskette)
10% to 90%, no condensation
30 Gs, half-sinusoidal pulse with 30 ms duration along X and Y axes. 20 68, half-sinusoidal pulse with 30 ms duration along Z axis.
Sinusoidal, 5 to 250 Hz linear
swveep at 1 octave/minute with
0.50 input.
Dwell 15 minutes at
resonant points (2X input level.)
45 000 feet maximum
TESCOHVNEIICANL REFERENCE
INTRODUCTION -
Table 1-2 LRC N "Uf Temperature
Operating
Relative humidity
Shock or we GeolE `i !Vibration S
Altitude
Conditions, Standard System e e
+10 C to +40 C with gradient less than 10 C per hour
20% to 80%, no condensation
'
S 63, 10 ms three
half-sinusoidal pulse duration along any of perpendicular axes.
with the
.
0.5 Gs peak accelleration in range of S5 to 250 Hz, linear at 1 octave/minute.
the Bveep
]
10 000 feet maximum
wey n
o3
NOTE
et
ol B us
Derate
the upper
temperature
by 1 C
first S00 feet.
limit
of
the
for every 1000 feet
operating
above the 2
S
Table 1-3
Storage Conditions,
Temperature
* Relative
vy e
Shock
humidity
Vibration
LS Altitude
System with Hinchester Disk
-30 C to +60 less than 10
C with gradient C per hour
20% to 80%, no condensation
30 65, half-sinusocidal 11 ms duration.
pulse
with
20 68, half-sinusoidal
11 ms duration.
pulse
with
30 000 feet maximum 10 000 feet unpressurized
1-5
TECHNICAL REFERENCE
INTRODUCTION
Table 1-4 Operating Conditions,
System with WHinchester Disk
Temperature Relative humidity Shock
Vibration
tAltitude
+10 C to +40 C with gradient less than 10 C per hour
20% to 80%, no condensation
S Gs, 10 ms three
half-sinusoidal pulse duration along any of perpendicular axes.
wvith the
0.5 Gs peak acceleration in the range of S to 250 Hz, linear swveep at 1 octave/minute.
10 000 feet maximum
NOTE
Derate
the
temperature
upper by 1 C
girst 500 feet.
limit
of
the
for every 1000 feet
<
operating above the
TECHNICAL REFERENCE
SYSTEM HARDNARE
Section 2 SYSTEM HARDWARE
2.1
INTRODUCTION
This section describes the design and functions of
the
hardware
in
the
standard
Texas
Instruments
Professional
Computer
system.
Hardware described in this section includes the keyboard, the
system
unit
Dboard
and
its two logical subdivisions, and the display unit.
Figure 2-1 is a block diagram of
the
system
hardware
components, including some options.
showing
the
separate
The option hardware is
described in Section 3, "Hardware Options."
2-1
'[EQH)I!CAL REFERENCE
SYSTEM HARDWARE
WNTEIORPNTAILON:MO2D1E2M0R B1O0A3 RD CLOCK AND ANALOG INTERFACE
BOARD (OPTIONH GRAPHICS VIDEO CONTROLLER
10PTION)
"V
/
£
4
7
\
--_--
COLOR DISPLAY UNIT
L
FOPTIONY
PARALLEL PRINTER CABLE (OPTION)
&
320¢
DISKETTE DRIVE --"
RS
WINCHESTER DISKOPTION:
---- 320K DIOSAKIEVTETE QLY MOTHERBOARD ISYSTEM UNIT BOARD)
CRT CONTROLLER BOARD
e YNC-ASY!
10PTION)
EBXOPAARNDSI'OGNPTIROANM 128K 8O4RK 192K
B £ ~
e
a9 =
i
SERIAL PRINTER CABLE 1OPTION}
MONOCHROME DISPLAY UNIT STANDARD:
MODEM CABLE
10PTION:
@
3
yErT
,
Figure 2-1 System Block Diagram
2222181
N
cuyPedi odee A
menetd
TECHNICAL REFERENCE
SYSTEM HARDWARE
2.2 KEYBOARD
The electronic functions of the keyhoa?fi include:
* Scanning the key matrix and encoding Xeys depressed
by
the
operator
* Transmitting data to the system unit
* Receiving and responding to commands from the system unit * Implementing a software-switchable repeat-action function * Performing n-key rollover
* Locking/unlocking the keyboard
* Performing a self-test
2,2.3
Encoding Keystrokes
The encoder scans the keyswitch matrix, detects valid keyswitch state
changes,
looks
up the proper key code, and transmits the keycode as
part of an 11-bit stream to the system unit.
Each key causes
either
1 or 2 bytes
to be transmitted, based on the status of the SHIFT,
ALT, CAPS
LOCK,
and CTRL keys.
For
sgpecific
details
on byte
definitions, refer to subsection 4.12.
Some
wuser-programming
application level.
See
Encoding.""
of
the
function
Xxeys
the paragraph in Section
is possible 2 entitled,
at the "Custom
2.2,2
Transmission
The
Xkeyboard
percent.
The
is met:
transmits
data to the
keyboard transmits when
system one of
unit at 2440 baud x> 1.50 the following conditions
* HKWhen a valid key depression has been detected
* HWhen a system command is understood and acted upon
When the user presses a key, the keyioard
proper
Xkeycode
byte
or bytes
across
Keycodes
are
explained
in detail
in
"Keyboard
DSR."
Pressing
some
keys
transmissions.
responds
by sending
the
the keyboard transmit line.
subsection
4.12
entitled
can
signal
repeat-action
"HTECHNICAL REFERENCE
SYSTEM HARDWARE
2.2.3
Receiving and Responding to System Unit Commands
The system unit transmits to the keyboard at 30S baud * 1.50 percent.
To respond to a system
unit
command,
the keyboard
transmits
a
response code to the system unit, indicating that the required action
has been
taken.
The keyboard responds to every valid command.
For
certain conditions, such as
parity
errors,
unknown
commands,
and
start
bit
errors, the keyboard ingores the system unit commands and
sends no response.
If this happens,
the
system
unit
retries
the
command.
System
unit
commands
and
keyboard
responses
are
listed,
in
hexadecimal form, in Table 2-1.
Iin
column lists the codes sent to the
column
lists
the code
returned
this table,
the
"Command
Code"
keyboard.
The "Keyboard Response"
by
the keyboard microprocessor.
Typically, system unit
the microprocessor returns (except in the case of a
Self-test OK failure during
(code 70)
to
self-test).
the
NOTE
Throughout
this manual,
the symbol H denotes a
hexadecimal address or value.
TECHNICAL REFERENCE
SYSTEM HARDNWARE
Table 2-1 Keyboard Commands and Responses
' `System Unit `Command
Command Code
(H)
Keyboard Response
(H)
Response Meaning
Perform a power-up
self-test and install
default parameters
oox*
70
71
72
Turn repeat action ON
Ot*
70
Turn repeat action OFF
02
70
Lock keyboard Unlock keyboard
03
70
O4x
70
Turn keyclick ON Turn keyclick OFF
0S5%*%
70
06k*%
70
Reset (same as 00)
o7
70
71
72
Self-test oK Keyboard ROM Keyboard RAM
error error
Self-test OK Self-test oK
Self-test 0K Self-test OK
Self-test OK Self-test OK
Self-test OK Keyboard ROM Keyfioard RAM
error error
Return version
-
o8
(of keyboard ROM).
70,73
* Indicates default values. *%* Keyclick requires a hardware modification.
It is not presently supported.
Yz-byte code)
TECHNICAL REFERENCE
SYSTEM HARDWARE
2.2.4
Implementing a Software-sSwitchable Repeat-Action Function
A repeat-action key is one that automatically repeats when
depressed
for one-half second (s) or longer.
As long as the xey is held down,
repeat-action transmissions from the Xeyboard
to the
system
unit
continue at a rate of 15 per second.
2.2.5
Performing n-Key Rollover
Repeat-action
interacts with n-key rollover in the following manner.
Pressing more than one nonmode
key
does
not
cause
repeat-action.
Instead,
the most
recent ey pressed transmits to the system unit.
When repeat-action is enabled and one key is pressed,
that
key
1is
acted
upon
by the repeat-action function.
The following examples
clarify the relationship between rollover,
repeat-action,
and mode
byte changes.
Example 1:
Assume that the following sequence of events occurs:
1. No mode bits are on.
<
2. The a key is depressed and held down for more than one-half second.
3. The b key is depressed.
4. The SHIFT key is depressed.
(The SHIFT key can be held
or
released without altering the characters transmitted to the
system unit.)
S. The b key is released.
6. The a key has not yet been released.
The result transmitted to the system unit and displayed is:
asaaasaaaaaaaaabaaaaaaaaaas...
TECHNICAL REFERENCE
SYSTEM HARDWARE
C
Example 2:
Assume that the following sequence of events occurs:
1. No mode bits are on.
2, The a key is depressed and held dowvn for more than one-half second.
3. The SHIFT key is depressed and held.
4, The b key is depressed.
(At this point, the SHIFT key
can
be
held
or released
without
altering
the characters
transmitted to the system unit.)
5. The b key is released.
6. The a key has not yet been released.
The result transmitted to the system unit and displayed is: aaaaaaaaaasaaaBAAAAAAAAAAA...
2.2.6
Locking/Unlocking the Keyboard
2
<
At certain times during system operation, the keyboard locks.
Buring
these times, all normal functions
of
the
kxeyboard
are
sugspended.
That
is, the keyboard does not scan, encode, or transmit data to the
system unit.
The keyboard locks if:
* The pelf-test is in progress.
* The self-test fails.
* The keyboard receives the LOCK KEYBOARD command.
The keyboard remains locked until one
of
the
following
occurs:
conditions
* The self-test successfully completes. * The keyboard receives the UNLOCK KEYBOARD command.
2.2,7
Performing a Self-Test
The
keyboard
performs a self-test when it receives code 00 from the
system unit, interrupting any keyboard operation
in progress.
The
TECHNICAL REFERENCE
SYSTEM HARDWARE
self-test transmits paragraph Commands.
completely
checks
the Xxeyboard system RAM and ROM, then.
the results to the system unit using a code
explained
in
2.2.3,
entitled
"Receiving and Responding to System Unit
2.3 SYSTEM UNIT BOARD
The system unit board, or motherboard, is the heart of the
computer.
It
is
mounted
on
the
bottom
of
the system
unit chassis.
The
motherboard is divided into
two logical
function
areas,
one for
system
support
and
one for the expansion bus.
Refer to Section 5,
drawing 222300S, for logic diagrams of the system unit board.
Figure
2-2 is a block diagram of the separate subsystems of the motherboard.
2-8
SYSTEM HARDKWARE
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TECHNICAL REFERENCE
EBFHNKCAL REFERENCE
SYSTEM HARDHWARE
2.4 SYSTEM SUPPORT
That section of the motherboard hardware and logic for the:
dedicated
to system
support
contains
* Keyboard port
* System
CPU
(including
microprocessors,
clocks,
bus
controllers, and buffers)
;, * Motherboard input/output (1/0) system
* Motherboard interrupt system
4.;* Motherboard memory system
. % ©
r
+ * A
oz
PDC subsystem (including buffers, write precompensation, and diskette drive interface)
.
CRT controller
é;4.1
Keyboard Port
s
The
Intel
82S1A,
a wuniversal
asynchronous
receiver-transmitter
KUART),
is
the port
for
serial
data
transmission
between
the
motherboard and the keyboard.
Data
received
by
the
UART
alvays
generates
an
interrupt
to the interrupt controller.
The transmit
ready line does not generate an interrupt unless the
transmitter
in
t¢he UART
is enabled.
The keyboard port interrupt is ORed with the
"interrupt reguest 7" line from the numeric coprocessor.
An SN7S5189A line receiver with a slowdown
capacitor
conditions
the
receive
data
signal
to protect
the
signal from transients.
The
receiver hysteresis is approximately 1 V centered around 1.4 V, which
improves the noise immunity.
Another SN75189A buffers
the
transmit
data
1line,
providing a good voltage swing and drive to the keyboard
cable.
This buffer consists internally of an output transistor
with
a 2-kilo ohms (kohms) pullup resistor.
fo; improve
diagnostics,
the data
set
ready
(DSR)
1line on the
uwpiversal
synchronous/asynchronous
receiver
transmitter
(USART)
gppnects
to the Xxeyboard connector through a SN75189A buffer.
The
transmit data line connects to the DSR-line at
the xkeyboard,
which
allows detection of a disconnected or defective keyboard.
el The: inrput
divides. this
input
clock
clock
to
frequency
for
the
the transmit section is 19 S31.25 Hz.
The 8251
by 64 to generate a baud
rate
of
305.
The
receiver
is 156 250 Hz.
This frequency is
TECHNICAL REFERENCE
SYSTEM HARDWARE
divided by 64 to generate a baud rate of rates are close to the standard 300- and instruments can simulate a keyboard with
2441.
Because
these
2400-baud rates, system
standard eguipment.
baud test
2.4.2 System CPU
EA
The
system
CPU consists of an Intel 8088 16-bit microprocessor,
CPU clock circuits, several CPU bus buffers and latches,
a CPU
controller,
and
the reset
circuit.
A special
socket
on
motherboard makes it easy to add the optional Intel 8087 numeric
processor (also called a numeric coprocessor).
the bus the data
The Intel microprocessors work together
appear to be a single chip.
Therefore,
manual) refers to both devices.
and, to attached the term CPU (as
components, used in this
2,4.2.1
Optional Numeric Coprocessor.
The user can choose to add an
8087
numeric coprocessor to the system unit board at any time.
Once
the 8087 is inserted into the socket provided, both the 8008 and
the
8087
decode
the special
escape
instructions.
The 8088 does any
memory-access computations required and accesses the
first
byte
of
memory
according
to
the instruction.
The 9087 decodes the
instruction, "catches" the memory
address
generated
by
the
8088,
requests
the bus
from
the 8088, and completes the required memory
access.
After finishing with the bus, the coprocessor releases it so
that the 8088 can continue with the next instruction.
If necessary,
the
8088
sends
a HWAIT instruction
to
the 8087, ensuring theil
synchronization.
«
2.4.2.2
CPU Clock Generator.
The CPU clock generator consists of ah
Intel-designed 8284, & crystal, and
some
discrete
components.
To
generate
the
5.0
MHz clock frequency, the 9284 divides the crystail
frequency (15.0 MHz + 0.01 percent) by 3.
The
9284
also
contains
logic to synchronize the WAIT- line from the expansion bus and memor}
subsystems with the RESET- line from the power-good circuit.
NOTE
i3
Signal names followed by a dash, such as HWAIT-,
At
are active low signals.
B
2.4.2.3 CPU Bus Buffering.
The CPU operates in the so-called
"maximum"
mode
of
this
integrated
circuit.
(For
additional
information,
see
the
1Intel
1literature
on
the
8088
and
208y
microprocessors.)
order to reduce
The
the
CPU uses
number of
a pimnusltirpelqeuxierded
address
on the
and data
processor
bus" in
chip:
For this reason, and to provide adequate buffering
for
the
address
and data lines on the expansion bus, a set of address latches (U5}
U6, U7) and a data bus buffer (UB) are an integral part of the CPUYI"
gJ let
3".l`!Cl-ulICAI.. REFERENCE
SYSTEM HARDHWARE
2.4.2.4
CPU Bus Controller.
The CPU bus controller chip
(U3
8288)
receives
the status
information from the processor and converts it
into the lines MRDC- (memory read), AMWC-
(advanced
memory
write),
IORC-
(X/0
read),
AIORC-
(advanced
1I1/0 write),
INTA (interrupt
acknowledge),
DEN
(data
buffer
enable),
and
DTR
(data
buffer
direction control).
A simple open-loop signature analysis (SA) arrangement is provided to
check
out the CPU.,
Connecting pins E17 and E180 (on the motherboard)
with a jumper and resetting
the system
(power
up)
causes
the
processor
to execute a OBFH opcode.
The jumper disables the system
data bus buffer Us, and the pullup resistors in U66 pull the
bus
up
to a high state.
Transistor Qi pulls down data line AD6 to provide
the "0" bit in the opcode.
The segmented
architecture
then
causes
the processor to cycle from address FFFFOH through address FFFFFH and
from 00000H through OFFFOH during the SA loop.
The
symbol
value.
NOTE ""H" denotes a hexadecimal address or
2.4.2.5
Reset Detection Circuit.
The power-good
(reset
detection)
circuit discovers insufficient power conditions on the motherboard by
monitoring
the 12-volt
(V) power line.
Hhen the power drops, but
does not shut down
completely,
this
circuit
causes
an automatic
restart.
If
the
voltage
falls
to approximately
11 Vde,
a
resistor/capacitor
combination
and a
voltage
comparator
with
transistor
inverter hold
the RESET
1line true
for at
least
3
milliseconds (ms).
2.4.3
Motherboard Input/Output System
The motherboard input/output (I/0)
for all
the devices on the board.
output latches are also components
shows a map of the motherboard I/0
system decodes the
1I/0 addresses
The input buffer and the various
of
the
I/0
system.
Table
2-2
addresses.
The
various I/0 devices have available 16 /0 address bits.
Only 10
of these bits, a total of 1024 bytes,
are decoded.
Beginning
at
address
OOOCH,
the motherboard
uses
48 bytes of this space.
This
leaves 976 bytes available for the expansion bus.
Table 2-2 lists the motherboard devices that are
addresses
within
the CPU 1/0 space.
Appendix A
map of all system I/O addresses.
decoded provides
and
their
a complete
TECHNICAL REFERENCE
SYSTEM HARDWARE
Hex Address
Table 2-2 Map of the Motherboard I/0O Addresses
Device
Bit/Use
00000
00001
00002 00003
00004
U47 Latch
U48 Input buffer
U49 Latch
o
USO Latch
NOUIWNERO I ~ N
NOUNEW M NO
NOWUEWNO
Speaker timer enable Timer 1 interr upt enable Timer 2 interr upt enable Single-density (FM) enable Track greater than 1/2 (TG43) Diskette side one enable (FSID-) Diskette mode control (Mi) Diskette mode control (MO)
Option Option Option Parity Printer Printer Printer Printer
jumper E1-E2 jumper E3-E4 jumper ES-E6 interru pt pending
port B usy port p aper out port p rinter selected port N O fault
Printer port data outputs LED 1 OFF LED 2 OFF LED 3 OFF Parity interru pt enable Printer port n ot autofeed Printer port n ot strobe Printer port n ot initialize Printer ACK in terrupt enabdble
*PWNOKFEWON-
US1 Latch
N O
s WNO
Diskette Diskette Diskette Diskette Diskette Diskette Diskette Diskette
drive drive drive drive drive drive drive drive
SELECT SELECT SELECT SELECT MOTOR MOTOR MOTOR MOTOR
2-13
TEGHNICAL REFERENCE
SYSTEM HARDWARE
Table Hex Address
2-2.
Map of the Motherboard Device
I/0 Addresses (Concluded) Bit/Use
00005--0000F 60010 00011 00012~-00013 00014 00015 o006 00017 00018 00018 00020 00021 00022 00023
00024--0002F
Reserved U44 8251 USART U444 8251 USART Reserved U4S 82S3 timer U4S 82S3 timer U4S 8253 timer U4s B2S53 timer U46 8259A interrupt U46 82S9A interrupt FDC command register FDC track register FDC sector register FDBC data register Reserved
controller controller
or RAM
or RAM reset
Data register Control register
Counter Counter Counter Control
© 1 2 register
TECHNICAL REFERENCE
SYSTEM HARDWARES
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Input/Output Signals - HAL12LE Integrated Circuit
ALC L0
Xs2
Xso
XA9
XA7
XAS
IORC-
Output
Xs1
DEN~
XA®
XA6
XA4
------- P
e bt e b b a b e b
bt e
AIOHC-
Comment
b e rmrr e e e r e e s e e, e
------
IEN-
L L H L L
or L H L L L
(X3 05 L BS A% PR 4
or .
.
0
a
o
-------
e ee
L
L
L
L
LL L L
A% H N
s
6o . S
et e b e b
.
.
.
. . 3
a1 g, b
. L L
b be
Read 1/0
Hritq`l/o
Interrupt acknowledge
Inactive term
e
e
Xcs -
L' LIRS H R
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OB LN HIENL U
LR IO LR T, Sy,
FEty
------- Pt
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-- b r el
et m b m el
o diie o o o
e eb
B3
e
Read I/0 at 74L3S139
Write I/O at 74LS139
e mmccc e e m--m e
Read I/0
------------
O AL H IS LU
o o a o a
------- P
FICS- L L
et e bbb
e b
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g
b me
L .
L
e e e e
.
Write I/0
r e
e e e, r e c e
Read diskette
------
O i L BE HIRN L S TSR
------- Pt et
U DN TN LR H e T
b et et bbb r
.
e e
Hrite diskette
m e
m s e s s mcm e m---- e -- -
YCs -
L LERH
orBLENHIN LA
------- Pt
XX XX H
BT
N LI
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bbbt
L OO 1,0 L LN T
DR D 2 LT
T
m b et r e b e r b e e e
Read 1/0 at 74LS138 HWrite I/0 at 74LS138
r e e m e d e r e e ------ e ---- -
Halt
or .
L
.
.
.
.
.
.
.
.
.
.
or . a 'Y
i bl @ B B VY w TR
or .
.
I I
.... ...
------- P
b et e b et e
b e e e et r
e e b
r e
e e E R e, rr S ---------------- - -------
Legend
L = =
Low signal, High signal.
TECHNICAL REFERENCE
SYSTEM HARDWARE
2.4.3.2
Parallel Printer Port.
Printers with Centronics-compatible
_interfaces
wuse the parallel printer port.
This port contains a 25-
pin female, D-type connector.
The basic signals are the output data
1lines from U444,
the PTSTR-
. signal
that
strobes
the
data
into the printer, and the PBUSY and
., PACK- lines, which indicate to the CPU
the printer''s
readiness
to
receive
a character.
In regular printer operation, the PBUSY line
goes high wvhen the printer is not ready to receive
a character
and
lov when the printer can accept a character.
The PACK- line goes low
for a short
time
wvhen
the printer
finishes
with
the
current
character.
The rising edge of this line generates an interrupt
when
printer
interrupts
are enabled by the PTEN line.
This interrupt is
ORed with the ""interrupt request S" line on the expansion bus.
The pin-out of the port is given in Table 2-4.
Pin numbers
for
the
36-pin
printer connector (at the printer end of the cable) are given
in parentheses.
The extra lines are used
for various
control
and
status functions associjiated with the printer port.
= =
R TN
e
e
e eB
TECHNICAL REFERENCE
SYSTEM HARDWARE
(-
Table 2-4 Printer Port Pin-Out
----------- Pmt r e m e e --a e
Source
|
Signal
|
----------- P m e e, --, e _, e e
e ---- 4
System
| Data is sampled when
§
| signal is low.
----------- e
e e
e --
|
e
System
| Data output bit.
|
----------- P m e e et e e e, n - ¢
System
I
I
-----------
e e et --m--r e
System
|
----------- P r st e, e e
|
m----------
System
i
----------- e r e --,---- e,
}
------
System
|
---------------------- P
e et
|
e, ------------g
System
{
----------- P e e
e M rr cc et e, -- e
|
e
System
}
|
----------- e e e
c e e mc r
ee --
System
|
}
-----------
e e e e et e, e --------
Printer
| Another character
|
___________
|
can e e
be o o
received. B SRR
|
Printer
| No data`can be seant
|
| when signal is high.
|
----------- P -
e e
e re
--
Printer
| Printer is out of paper
|
| when signal is high.
|
-----------
e e e,
r e, ------ e ------------ ¢
| 13
}
|
|
] sLcT
| Printer
| Printer is online
|
| (ON LINE)
|
| when signal is high.
}
o -------- o -------- er e~
e
---- - P
et e,
ee e
------ .
| 14
|
i
-
f1s(32)
|
e --
i
{
| AUTO FEED~
|
| System
{
| Printer is to line feed
|
| on carriage return
|
{
|
i
| when signal is low.
}
m------mm- e
- ---- L
e c e e ----r e
+
§
| FAULT-
| Printer
| Indicates a fault
|
}
|
|
| vhen signal is low.
}
e m--m-- e
e m e
------ P e et
e
e +
{16(31) I
J25(30) }
| INIT{
| System
| Resets printer when
|
§
| signal is low,.
j
m-------- - R R i e
a - Pm e --
117(36) |18(33) | SELECTION-
| System
Pmmm e m - mme e
tmmmm e
* The numbers in parentheses are the pin
P
e et --rmr e
| Always low.
P
e
e e e
numbers for the 36-pin
m - - +*
}
+
Centronics-type connector.
STECHNICAL REFERENCE
SYSTEM HARDWARE
"2.4.3.3
Timers.
timing wunits.
oscillator, and
The 8253-5 counter/timer IC provides three separate In this system, one is used as a programmable speaker the other two are programmable interval timers.
The speaker timer is clocked by a square wvave of 1.25 MHz.
Divisors
-up to 6S 536 can generate output frequencies as low as 15 Hz.
The
"high input frequency creates output tones
that are more musically
accurate.
The
speaker
timer
clock
is internally gated with the
speaker enable (SPKEN), an output of latch U47.
This
signal
allows
the interruption of tones without a reprogramming of the timer.
The second timer (Timer A) is used in system-timing applications and
as & real-time clock.
It generates an interrupt signal on the rising
edge of the timer output wvhen the enable line (address O bit 1) is
set high.
Toggling this line low resets the interrupt; holding this
line low disables the interrupt completely.
The interrupt
level
|is
3. The input clock frequency to the timer is 625 kilohertz (kHz).
A
divisor
of
62 S00 generates a pulsewidth of 100 ms, while a divisor
of 1S 625 generates a pulsewidth of 25 ms.
The
third
timer
(Timer
B)
is used
for special-purpose
timing
applications.
It generates
an interrupt on the rising edge of the
timer output when the enable line (address ¢ bit
2)
is set
high.
Toggling
this
line
1low resets the interrupt; holding this line low
disables the interrupt completely.
This
1line is shared with
the
expansion
interrupt
1line IR2.
The interrupt level is 2. The input
clock frequency to this timer is 625 kHz.
¢
2.4.3.4
Speaker Amplifier.
The speaker
timer
output
goes
to an
amplifier
(LM
396)
that
drives
the ©6-ohm speaker,
providing
sufficient volume
and allowing mixing
of signals
from external
sources
(option
expansion
cards).
To mix other signals with this
signal, connect any other signal source (such as
the
speech
option
board) to P12, the summing input.
2.4.4 Motherboard Interrupt System
The motherboard interrupt system can encode eight separate interrupts
and
vector
the
central
processor
to eight
separate
interrupt
routines.
A nonmaskable interrupt (NMI) (which produces the highest-
priority interrupts) is also available.
The majority of the interrupt logic is contained
within
the
Intel
82S9A
interrupt controller chip.
The 8259A is programmed for level-
sensitive input
and
is the master
(only)
interrupt
controller.
puring
the
INTA
cycle, the decoding logic array always enables the
contents of the
I/0 data
bus
onto `the
system
data
bus.
This
information
is the vector
from
the
8928A chip, and the system,
therefore, requires only one controller.
The 98289A chip assigns priority to the
incoming
interrupts,
allows
masking
of interrupts, and provides the vector to the CPU during the
TECHNICAL REFERENCE
SYSTEM HARDWARE
interrupt acknowledge (INTA) flops permit some interrupt be edge-triggered, and cause
cycle. levels
others
A series of OR gates
and
lip-
to be shared, cause some inputs to
to be level-triggered.
-4
The
interrupts
that
come
from
the
expansion
bus
are
active
high
LA
and
are, therefore, terminated
ground.
All the pulled-down
either
directly or through
the gate input current from
with
a 4.7-kohm
pulldown
resistor to
inputs are connectied to the 8259A chip,
a CMOS OR gate.
This connection prevents
raising the input voltage above the legal
"low" level through the pulldown resistor.
CAUTION
Even though the system is protected,
programmers
and
designers
wusing interrupts on the expansion
bus should be sure to "mask off" unused interrupt
lines as a matter of good programming practice.
The NMI detects parity errors on
the motherboard
RAM
system.
To
generate
this interrupt with software, set the DTR line on the 82S1A
USART.
The RAM can then be tested without parity-error interruption.
i
The interrupt levels and their expected uses are given in Table 2-5,
B
Table 2-5
Interrupt Level Assignments
Ifiterrupt
NMI IRO IR1 IR2
Bus Line
AO1L BO4 B24 B2S
IR3
na
IR4
B23
IR6
B21
IR7
na
Use
.
System parity error, CRT interrupt Communications port 1 Communications port 2 Communications port 3 System board timer 2 Local area net board buffer full/empty System board timer 1 (clock) Communications port 4 Diskette drive, Winchester disk Keyboard, numeric coprocessor
na = Not applicable.
2-19
2 TECHNICAL REFERENCE
SYSTEM HARDHARE
2.4.5
Motherboard Memory System
The memory system on the motherboard consists of 64K bytes (K = 1024)
of dynamic RAM, up to 16K bytes of ROM, decoding logic
to establish
" the addresses, and timing and refresh logic to operate the system.
A
connector
and
the necessary logic permit the addition of one of the
expansion RAM boards.
These boards are available in 64K-, 128K-, and
192K-byte capacities.
After adding the 152K-byte board (bringing the
total to 256K bytes), further expansion requires the
addition
of a
256K-byte
board
that plugs into the expansion bus.
(This board and
another memory expansion board are fully described in Section 3.)
2.4.5.1
Hotherdboard Memory Addressing.
The memory
space
of
the
processor devices used by the motherboard is given in Table 2-6.
The
balance of the system memory is given in Appendix B.
Table 2-6 Motherboard Memory Map
Address
Device
Dynamic RAM:
O0000O0-OFFFF 10000-1FFFF 20000-2FFFF 30000-3FFFF
ROM Usage:
FCOOO-FDFFF FECOO-FFFFF
< 64K-bytes motherboard RAM 64K-bytes expansion RAM board bank 1 64K-bytes expansion RAM board bank 2 64K-bytes expansion RAM board bank 3
8K ROM space, one wait state (XU62) 8K system ROM, one wait state (U63)
TECHNICAL REFERENCE
SYSTEM HARDWARE
2.4.5.2
Memory
Control
Logic.
A Dbidirectional
buffer
(Us1)
separates the main system data bus
from
the motherboard
expansion
memory,
thereby
providing
sufficient
drive and margin to the data
transfers.
U288,
the
memory
hard
array
logic
chip
HAL16R4,
in
combination
with US3,
the 74LS139
decoder,
handles decoding and
timing for the ROMs.
Because ROMs and EPROMs (erasable
programmable
read-only memories) are generally slow devices, a wvait state is added
to all accesses to these devices.
The ROM access times are listed in Table 2-7.
Table 2-7 Function
ROM Access Times Time Required
(in Nanoseconds)
CS-ROM access
410
ROM address access
577
1/0 Hait States.
The HAL chip alsc contains the logic to add a wait
state to all 1/0 accesses
made
by
the
CPU.
The wait
state
is
necessary because many of the I/0 devices operate too slowly when the
system buffer and setup and decode times are included.
With the wait
state, the control lines are active for approximately 600 nanoseconds
(ns).
Memory Refresh lLogic.
The RAM refresh logic operates synchronously
with the accesses to the RAM memory.
Refresh cycles begin only when
a RAM memory
cycle
is not in progress.
This implies that the RAM
refresh can occur at the same time as accesses to other system memory
(ROMs) or I/O space.
Each time a refresh
cycle
begins,
a refresh
timer
(one-shot
U29)
starts,.
When
it times out, it provides the
signal to begin another refresh cycle.
This
timer
is set
to 15
microseconds
(us)
maximum, which allows for the worst-case refresh-
regquest latency.
To maintain the contents of the
RAM
under
worst-
case
conditions,
the refresh must occur at least 128 times within 2
ms.
(The average refresh timing is once per 15.625 us).
case latency for a refresh request is about 600 ns.
The worst-
Once a refresh cycle has begun, it must be completed (including the
precharge) before the next cycle begins.
If a RAM access
cycle
starts before the refresh cycle completes, the HAL state machine puts
the CPU into a wait state until the refresh operation completes.
In
the worst case, this delay could extend the normal memory access time
by four wait states, or 800 ns,.
Assuming slowdown
a refresh
of
the
timer CPU,
value
of
14 us and
the
refresh
overhead
an average
600-ns
is approximately 4.3
TECHNICAL REFERENCE
SYSTEM HARDWARE
percent average or 5.7 percent wvorst case.
2.4.5.3
CAS and Address Multiplexer Switch.
A delay line
from
the
RASI-
(row address strobe input) line produces the SWM (the address
multiplexer control).
SKM ensures an adequate rowv address hold
time
(40 ns) and
s8till
operates
the RAM guickly enough to finish the
access within the system cycle time.
The CAS1- (column address strobe input) timing depends on whether the
cycle is a read or a vrite.
If the cycle is a read, the CASI- signal
is taken from the delay line 20 ns after the SHM signal
to produce
the ACAS- (advance column address strobe).
ACAS- ensures an adequate
column address setup time to the RAM and still gives fast RAM access,.
If the cycle
is a write, then the CASI- signal is taken from the
falling edge of the system clock, which is about
150 ns after
the
occurrence
of RASI-.
This delay allows time for the data from the
processor to propagate
through
the data buffers
and
the parity
generator chip (U31i 74LS280).
To control the generation of the CASI- pulse, flip-flop U33 is timed
with CLK- (the system clock), samples the delay line (ACAS-), and
is
reset by MRDC- (the memory read signal).
The output of the flip-flop
is
then
logically ANDed (U34) with the ACAS- signal to generate the
actual CASI- signal.
To prevent the generation
of a CASI-
pulse
during
refresh,
the refresh row address strobe (RRAS-) line holds
flip-flop U33 in the preset state during a refresh.
This forces
the
output of OR gate U34 (CASI-) to a high level.
a
2.4.5.4
Parity
Generation
and
Checking.
The
parity
generator/checker chip (74LS280) generates a "1" to the parity RANM
bit whenever
there
is an even number of 1's in the data byte being
written,
The parity RAM chip has a separate data bus
to drive
the
output
1line.
A pullup resistor holds this line high wvhen it is not
driving the output
(as in a write cycle).
The parity data is then
taken
from
the "odd sum" output of the parity generator and used to
write to the RANM.
.
This method of parity checking does not cause a parity error whea the
system attempts to read from nonexistent RANM.
(To determine the size
of system memory, the system software sometimes
"feels"
for memory
not present.)
When
the RAM
is read, all of the data bits and the parity bit are
presented to the generator/checker and the parity output
is sampled
at
the
end
of
the
read cycle.
If parity checking is enabled and
discovers a parity error, flip-flop U333 is set to interrupt the CPU.
Once
set, this flip~flop must be reset by software before additional
interrupts can be given.
If the enable bit (address 3 bit 3) is held
low, then no parity interrupts (PINT) are generated.,
To distinguish
the parity
interrupt
from other NMIs, the PINT line is fed to U4s
(address 1 bit 3) and can be tested by software.
TECHNICAL REFPERENCE
SYSTEM HARDWARE
2.4.5.5 (HAL16R4
Memory U28),
Control State Machine.
A
set up as a state machine,
hard
array
logic
device
drives the memory control.
This device has four outputs equipped with a set
of
clocked
£lip-
flops
and
four
outputs that are direct combinations of the inputs.
The AND of the terms on a line ORed with the AND of
terms
on other
lines
results in low-going outputs.
This occurs either directly, on
those outputs without registers, or after the clock on those
outputs
with registers.
The
signal
RASI-
activates
RAS-
out
of
the AM2964B RAM address
apmTrTithhhdreuneeedoflsrgrttereirwsssesupaiisshcligg.sttenn,sxaaselltrsat.TtahMRteetDMhTseeEhS.eNETs-Lhit-eogAnMTasah2cisslte9gthei6enigl4avneslBaaciRClttPgRseUnAsaSSaXl-YdWaa-dAfctrItchSeTeeeXir-ss-nss(dumsiopo(ecnutudeathsmtsteeouedrlcsbtyitoichniatlpethnreleet.dterehpxnarretanomrRlacOellMemylssoa.ysrytoortortoepsufyTtitrhshnteeetthsoeeohmuHtAHasLAid)LgaRw)ttnAahaSaeiiltncudbrtiuesiscsfftRafraFteetSoreesHf.s.ih-fn
Table 2-8 gives the logic for the memory control state
A timing diagram of the memory system, shown the major operations of the memory system.
in Figure
machine. 2-3, indicates
TECHNICAL REFERENCE
SYSTEM HARDWARE
Table 2-8 Memory Control State Machine Logic - HAL1G6R4 Input
Output
MRD-
XAL8
RASI-
RFSH-
MHR-
RMX-~
XWAIT- RRAS-
RFRQ
IORC-
MDEN-
sSY-
XA18
AIOHC-
RMSEL- SX-
Comment
------- bbb obobotbrbrmm bbb m b e b o b o b o e w oo
>
- e>
e
RASI=guLp. - L oL
s
- -
H
H .
Memory read
or . L
BLLILS. g
.
(' 5 B o d o.d 6 ©
oo
o tdia Lfo
- n R LELE T
Memory write Refresh
(37 o8 a0 o A 4 o
e
O LALG. s
All other OR terms
------- et bafeb b et ob bbb bbb b b E r r mE-- e r e rr r---- ---------------------- - - -----
XHAIT-HLWC UL s o
e
S IR DI
Refresh+read RF1,2,3
Or L R L
R
el SR
- L.
Refresh+read RF3,4
O
L
or 'L, .sLaL g,
(P o o o B'Ei% o o
Bl
LR T
o
o R
LS
- LTt
Refresh+write RF1,2,3 Refresh+write RF3,4 ROM read/vrite
(7 s oron omo ot o (Y7 °F o & oo ol ot
R
o o]
TRl
R
1/0 read I1/0 write
------- Potmbrt bbbt
b et
b
b PP
ee e
e
-------------- - -
MDEN
SIS SR R
LYo S H
HEF?
RAM read/write
or L .. HHL . .
R
B
ROM read
or . L . HHL . .
S SR
S
or . . . . . .LL
SRS
.o
ROM write All other OR terms
------- e e
s
e
RMSEL- L . . HH L . .
SO
e
ROM read
or . L . HHL . .
ond o o g o g O
ROM write~
or
R Ll
R
R
All other OR terms
------- bbb bbbt
b e bbb b bt R e
r rr r r ,r
e,
-- e -- - m--- -
The following four outputs have flip-flops:
------- bbb
bbbt mrm b e bt et m b b e e P E
e
m e rC S r e e m e -- e - ---- o s
RFSH-
HHH . . . . .
d | onviom
o 0Y s
Refresh RF1; no memory cycle
or . . HH . . . .
8 o & oo b SiHh
Refresh RF1i; no RAM cycle
P 0% o0 =o o B o
Sl
R L
H
Refresh RF2,3
O
-------
RRAS-
e I
. S
bbbt b
. . . . .
0 -8
b
o bt rrm bbb
. ..
A e
ol
b r bebe P
1% o B o
All other OR terms
R,
e
e
e e e e e --m e
Refresh RF2,3,4
-- === =
O A
B W
Tl
L
All other OR terms
------- et b
oot r b e bbb e bbb P e E r e, e, et rc e e r
e
---- -- - -
sSY-
B
R
O
e - -
-
50 <9 © hdh o CRN . B LT
Refresh RF3,4 All other OR terms
------- O S S ok L o e R
et
L T
SX-
L. .HHL . .
o o 4
.
..
ROM read wait cutoff
or . L . HHL . .
X o Bl ow o
g
o
R
I
s I TR
SR
ROM write wait cutoff 1/0 read wvait cutoff
O,
o L.
BT
I/0 write wait cutoff
or . .
s L
N
R
All other OR terms
------- Pobo bbb et b e bbb bbb b
P rree
e
e cm s e --m e --------
L = Low signal.
H = High signal.
TECHNICAL REFERENCE
SYSTEM HARDWARE
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Figure 2-3 Memory System Timing Diagram 2-25
TECHNICAL REFERENCE
SYSTEM HARDWARE
2.4.6
Floppy Disk Controller
The floppy disk controller
(FDC)
section
contains
a floppy
disk
controller
IC (FD1793-02), a floppy disk support logic IC (WD1691),
and a pulse delay IC (WD2143), all made by Western Digital.
The
FDC
also has a voltage-controlled
oscillator
(VCO) and one-half of a
7415221 one-shot.
Two 2114 static RAMs, addressed by a CMOS
4040,
act as a sector
buffer,
and a programmable array logic (PAL) IC
decodes and controls operations.
Miscellaneous logic handles
signal
timing and buffering.
The logic described in this section includes:
* Floppy disk controller IC
* Sector buffer
% Data write precompensation circuit
* `Data separator
* Diskette drive interface
2.4.6.1
Floppy
Disk
Controller IC.
The Western Digital FD1793-02
chip is the FDC IC.
This IC does
serial/parallel
data
conversion,
locates
sectors
on the disk, seeks the diskette drive, and performs
other high-level functions.
A complete description of the FD1793-02
chip can be found in the literature available from Western Digital.
The 1.0-MHz controller input clock provides the correct data rate for
standard S 1/4-in diskettes.
Because U20 divides the clock down from
15.0 MHz, the duty cycle is 467 ns low, S33 ns high.
2.4.6.2
Sector Buffer.
During read or write operations,
data must
be
transmitted
at
a rate between 23 us per byte and 32 us per byte
nominal (for double-density operation).
A sector
buffer,
operating
independently of the processor during a read or a write, ensures that
the diskette drive performs properly.
This buffer consists of:
* A 1K x 8 static RAM device
* A counter (to address the RAM sequentially)
* Control
Jlogic and a bus buffer (so that the CPU and the FDC
can access the buffer)
TECHNICAL REFERENCE
SYSTEM HARDHARE
Two bits (MO, M1) in latch U47 control the basic operating
modes
of
the sector buffer.
These four modes are as follows:
Latch U47 Bits MO M1
Mode
1
1
o
1
o
o
1
o
FDC reads RAM and writes data to diskette. FDC reads diskette and writes data to RAM. CPU reads or writes RAMN sequentially. CPU reads or writes the FDC directly.
The
counter
that addresses the buffer increments automatically each
time either the CPU or the FDC accesses the RAM.
To set up a fixed
starting
address
wvithin
the RAM, the CPU writes to the FDC sector
register while the MO, M1 bits are set to O, o.
This
resets
the
address
counter.
The FDC is not affected because the CPU can access
the FDC only in mode MO, M1.
The PAL provides the control logic for the sector buffer, aided by a
flip-flop
that provides
a 1-us FDC clock-synchronized signal.
The
PAL uses this signal, derived from the FDC data request
(DRQ)
line,
to generate
the
read
or write command for the FDC when the sector
buffer is in modes 1, 1 or 1, 0.
The FDC activates the DRQ line when
a sector write requires a byte or when a byte is ready
in a sactor
read.
This
control logic and the CPU generate other signals to control the
RAM and the counter.
These signals are given
in Table
2-9.
The
timing
diagram` in Figure
2-4 defines the usage of these signals.
When the logical AND of terms from one row is ORed with
the AND
of
terms from another row, the output goes lowv when the result is true.
TECHNICAL REFERENCE
SYSTEM HARDWARE
Table 2-9 Programming for the HAL1OLS® Device
Input
IORQXAL
M1 MO
IORCAIOHWC~
DEN-
Output
XAO
DRQD
FLCS
Comment
e --m--e e mpr b med
YAO
LRl et I
be b e be
P
I
S almmL
e ee
.
E CERne me Eee
------------
CPU <---> FDC Mode 0,1
or . s 5
S 5 e
L LR
o
(Unused)
------- R
LT e
R
L
R
e R
L
e
T
YAl
S L
LB .
o A8 15
.
CPU <---> FDC Mode 0,%
or . S B
o a o
L LY
b
(Unused)
------- B
e
it T
e
R PR
DD R Rl et b
i
FRD-
o o w
LH .
L .L
s
CPU <-- FDC
Mode 0,1
or . . .
H L H
. . .
.
FDC =--> RAM
Mode 1,0
------- Prm et
FWR-
I
(I igt ' wo e ©
e
mfr e e b e b
LR 1
L L
H H H
R
e eEP EC
2
CPU
s
FDC
- --
e ee---
.-
--> FDC
¥ode 0,1
<-- RAM
Mode 1,1
------- Pommbmm b r e
ee e m b
e
e R
.
------ S E e -
- ------oe
RHE-
a 85 =
LL .
. L L
o
O I
R
H L H
Ol
.
CPU --> RAM FDC --> RAM
Mode 0,0 Mode 1,0
------- mmbom b r b mm b
b
m b mpm e e
e o
e
e
= e v
RCS -
LU L&
O bR
LL .
UL
.
H .H
. o4
.
CPU <--> RAM FDC <--> RAM
Mode 0,0 Mode 1,X
-------
b -- bb e m e eb e e e e -- e m e --m oo m e meosoe
RRST-
. H L
LL .
. L L
o
Reset counter
Mode 0,0
or . Rt
3 . &
51 5
4
(Unused)
------- Pommpumtmm e
FDEN- L L . LI
or . . .
L
mm
oo
D
H .
ob me
T R L
.
. .+ L
L
-
ee e
CPU <--> RAM
CPU <--> FDC
- -
-
Mode 0,0
Hode 0,1
Legend: L = H =
Low signal. High signal.
TECHNICAL REFERENCE
SYSTEM HARDWARE
1 -MHZ CLK
DRQ
J__\_
--\--
CONTROLLER WRITING TO RAM _\----/__\
|
_ --_--__\L__________________
DRQD
FRD -, RWE-, RCS-
\\
f_`
MO - LOW, M1--HIGH
RS
VALID }
READ FOC WRITEIRAM
1--MHZ CLK
~J]
DRG
DRQD
FWR, RCS
DATA
\ VY
;
CONTROLLER READING RAM
J
\
\\
j_%
VALID >--_
READ RAM WRITE [FDC
MO --HIGH, M1 - HIGH 2232164
Figure 2-4
Floppy Disk Timing Diagrams
TECHNICAL REFERENCE
SYSTEM HARDWARE
2.4.6.3
HWrite Precompensation
Circuit.
Using modified frequency
modulation (MPM) to write certain
double-density
data
patterns
on
magnetic
media
causes . a
"bit
shift",
requiring
disk
write
precompensation.
Compensating for the bit shift
prevents
the read
data
transitions from moving outside the detection range of the read
circuitry.
As track length shortens toward the center of
the
disk,
data
bits
are stored closer together, so the bit shift problem gets
worse.
The ideal compensation gradually adjusts the write
hardwvare
as
the
track
number
increases.
However,
a compromise solution
produces nearly the same results.
The precompensation is turned
off
while
the head
is over the outer half of the disk, then turned on
vhen the head is over the inner half of the disk.
Disk
drives
can
have either 40 or 80 tracks, so the software checks the type of drive
installed,
then determines the halfway point.
For this reason, U47
(rather than the FDC) controls the TG43 signal.
(Halfway
point
for
an 8-in diskette = TG43 - track number greater than 43.)
The write precompensation and data separator circuits are controlled
by Ui4, R17, R18, and R19 on the motherboard.
When the RDDATA-
line
(pin
11
of Ul4) is high, it forces the PU and PD- outputs from the
WD1691 to a tristate condition.
R17 adjusts
the
PUMP
line
(pins
13/14 of Uia) voltagel*o'lug vde.
R18 generates a square wave of 2.0
MHz + S.0 percent
from the
VCO (pin 16 of Ul4).
The pulsewidth
(monitored from pin 5 of Ul4) should be 750 ns, giving a write
pulse
width of 187.5 ns.
The waveform is visible only when the computer is
writing data to a diskette.
R19 controls
the write pulsewidth
through 15
a (the WD2143 IC),
determining
the amount
of
precompensating
bit
shift.
The
precompensation
pulsewidth
(monitored
from pin -1 of ULS during a
write operation) should be set to approximately 200 ns.
The FDC signals EARLY and LATE control the direction
of bit
shift.
These
signals
cause
WD1691 to select the appropriate tap along the
WD2143 (adjustable delay line) for the bit pattern being written.
If
precompensation is not needed
on outer
tracks,
the
TG43
signal
inhibits the precompensation process.
Because
single-density
frequency
modulation (FM) encoded data does
not
reguire
precompensation,
the
FD1631
also
disables
the
precompensation
when
the double-density
enable
signal {DDEN-) is
inactive (high).
2.4.6.4
Data Separator.
The
data
separator
1is composed
of two
parts:
clock
recovery
and
separation of the data from the clock.
The actual separation of data from clock signals takes place
in
the
FD1793-02 FDC.
The HWD1651 contains the digital circuits necessary to
implement
a phase-locked loop (PLL), the VCO is a 74LSé28 chip, and
external components
provide
the
1loop
filter.
The
one-shot
U2¢
shortens and stabilizes the pulsewidth of the incoming read pulses so
that the PLL and data recovery operations operate properly during the
lockup interval.
TECHNICAL REFERENCE
SYSTEM HARDWARE
TrtthhheeeelathfiiaPogLlnLhls-iohnrgipproelvodwiwgidetehpsuolftsreaathnesofictoRinDtotDhneAisTnAuR-oCuiLnsKsitghsenicagllnoiacnlkc.sohmoiu1nllgdockedbdeatan.eian rlaFyorspectcheiinsftiecrseydsptheams,oen
When train
the
PLL
is adjusted correctly,
in a frequency range from 217 kHz
it locks to an incoming pulse
to 294 kHz
(+ 15 percent)
within to the
150 us.
The
RDDATA- input
pulses should be (P9 pin 30), and
low-going, 2 us maximum applied the DDEN- line must be low.
Because of governs the regulator
the analog nature of the
power-supply voltage to
prevents
digital noise
PLL circuits, a the VCO and the on the 5-V supply
linear
regulator
loop filter.
The
from interfering
wvith the PLL operation.
The data separator works
density (MFM) data.
The
with either single-density (FM)
or double-
choice is controlled by the DDEN- line.
2.4.6.5 through cables diskette driven drivers pullup
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terminated at the drive.
If another drive is installed internally,
SELECT
on pin
12
(drive
1) with only
With two drives installed, the terminating
on the right-hand drive (drive 1) only.
it should the select
resistor
be strapped
for
line terminated.
must be installed
NOTE
The
floppy
disk
controller
and
individual
diskette
drive logic signals assign drives using
the convention of:
DRIVE 0, DRIVE
and
DRIVE
3 (for
a four-drive
1,
DRIVE
2,
system).
The
diagnostics diskette uses the convention:
DRIVE
1, DRIVE 2, DRIVE 3, and DRIVE 4 for a four-drive
system.
Operating
systems
may use yet another
convention, such as DRIVE A, DRIVE
B,
DRIVE
C,
and
DRIVE
©D.
Be sure to use the correct drive
designator.
2-31
TECHNICAL REFERENCE
SYSTEM HARDWARE
Connector P13 interfaces with a 40-vire ribbon cable ending in a 37-
pPin, D-type connector.
The user mounts the mate to this connector on
the back panel of the system unit chassis.
When external drives are
installed, all lines used must terminate at the external drive.
»
-
All diskette drives must be of the same type.
That is, all must
be
either
320K-byte
drives (double-sided, 48 tracks per inch [tpi]) or
all must be 640K-byte drives (double-sided, 96 tpi).
A jumper
from
E1Ll
to E2 selects
320K-byte drives; a jumper from E3 to E4 selects
640K-byte drives.
The absence of a jumper selects 160K-byte
drives.
A jumper can be on either Ei1-E2 or E3-E4, but not both.
The
diskette
drives
do
operation.
However,
if
solenoids, they should be
not need head-load
solencids for proper
the drives
are
equipped
with
head-load
strapped for head load with the motor on.
The
signals STEP, DIRC, HG, and WDOUT are buffered by the 74LS244 in
order to drive the two standard 7416 loads.
This buffer is necessary
because the FD1793-02 and the HWD1i691i can drive
only
one
TTL
load.
The
input
signals
KWRITEPROT-,
INDEX-,
TRKOO-,
and RDDATA- are
buffered by the 74L3S244, providing more static
protection
than
the
MOS-device inputs, and a small amount of hysteresis.
To install external diskette drives, a short cable assembly links the
motherboard connector P13 with a 37-pin, d-type connector on the back
of
the
system unit chassis.
Section 5 contains the wiring assembly
diagrams for
this
cable.
external power source.)
(External
diskette
drives
regquire
an
2
Table 2-10 gives the pin-outs for the internal diskette drive
connector on the motherboard.
Table 2-11 gives the pin-outs for
the
external
diskette
drive
connector
on the motherboard.
D-type
connector pin numbers are given in parentheses.
TECHNICAL REFERENCE
SYSTEM HARDWARE
Table 2-10
Internal Diskette Drive Connector Pin-Out
|] 24
| 23
| KRITE GATE~ | System | Enables writing to drive]
|
}
|
i
| when iignal is low
|
- P ------- L R
e P m - ---- e
m e eeme
c e, c----------- +
| 26
| 25
| TRACK 00-
| Drive
| 1Indicates head is over
|
|
]
R
§
|
i
| track 00 when signal
|
}
|
]
] is low
]
tm------------ mmmmm--me -- -- = bmmmme-- e m e e
e, e e
+
| 28
i 27
| HWRITE PROT- | Drive
| Indicates diskette
}
§
|
|
f
{ i3 write-protected
§
Fmm------ o ------ Fmmm e m m m
- d o m e m e, s cn et e -- e --
e +
] 30
| 29
| READ DATA-
| Drive
| Serial data from drive
|
b
P
tmmmm e mm
mmmm-------- e
- - +*
| 32
| 31
| SIDE 1-
| system | sSide select (0,1 =
{
J
1
-e o
|
|
|
---- e mmm--= mmem -------- e
high, low) r e, e e e e m e
1
------- +
| 3 4 B { 3 3U |
--
| NC
}
--
|
e
fm-------m tPmm e -- e -- e
Pmm
- ----
e, e, e e
e _,_,--, - ---------------- +
* NC = Not connected.
TECHNICAL REFERENCE
SYSTEM HARDWARE
Table 2-11
External Diskette Drive Connector Pin-Out
B
P --------- Prrmcmec--r--------- -
- ----
|signal|Return| Signal Name | Source |
e -------- R
bt e - Pmm-- - Pt
b 2 (1)) 1(20))
--
I NCx
|
b ------ o --------e Fmm--mree e
e rme o P
I 4 (2)1 3(21)4
S
I Nc
|
R
- e
m- P
---- P
I & (3)] s(22)]
s
| K¢
)
---------- b -------- e
b mem---- P
I 8 (4)) 7(23)]
=
I NC
|
m------------
- e ccc s e e b
P
110 (S)| 9(24)}
s
| NC
|
P
---- o m---- Pem - --m --------- _---- e --m--
- ---- -
Function
------------ - - - ------ *
|
e
r e r e, e~ -- . ---------- +*
--
e m e et
|
e ------ - +
=
I
e e
--, e -- e e . ---------------- +
--
e, et e e
|
e
= - +
as
r e
s se
)
------ - +
E
|
e e e e e e r et e
- +
{12 (6))11(25S)}
INDEX-
| Drive
| 1Indicates index hole
|
R
R
D R
mmm---------- Le
e *
fr14 (7)§13(26)| MOTOR
3~
| System | Drive motor 3 enable
|
Prmmwo-
oo wm- P
- mm--m---------- P
e rrcrr e r e
-- .. -------------- +
16 (8))115(27)} SELECT 4-~
| System | Drive select 4
|
mr -
o -------- P mmm e ------------
e -------- b, e e ------,r --,--,---------------- +
{18 (9)}17(28)) SELECT 3-
{ System | Drive select 3
|
O
R
btrcmc e rc m ec e
ma - P c e mr e c e c e c e e m-- . ------------ +
{20(10)}19(29)| MOTOR
4-
j System | Drive motor 4 enable
{
mm-------- m---------- e
me re
-~ P mm-------- P
e,
e --
- ---------------- +*
122(11))21(30)] DIRECTION-
| System | Step IN/OUT direction
|
e
e ------ R
e cmm--- e
e e
e *
|24(12))123(31)}
m---------- ----------
STEP-
e m e e
| System |
oo - P
Step IN/OUT command
mrm e, e
et m e
r e
--
|
- = +
§26(13))25(32)| WRITE DATA- | System |
- e m--mm Pomrm - ---n ------ Pmm
e ------ P
Serial_data to drive
|
e ee e e e=
- +
{28(14)}27(33)| WRITE GATE- | System | Enables write when low
|
e ------ mm-------- e
----------
- - Pmmmmm----------
e
e -- e -- . --------------- +
|30(1S)|29(34)| TRACK 00-
| Drive
| 1Indicates head is over
|
}
}
|
{
| track 00 when low
|
------------ tm---------- mmm
e e bmmmmm - P
e e m s cee e
+
|132(16)[31(35)| WRITE PROT- | Drive
| Indicates diskette
{
|
|
|
|
{ is write-protected
|
Frmm - R
brmmem , m ----m ------ P ------------ P
rcmr e r e e r e
e --c e e - oo---- -
§134(17)|33(36)| READ DATA~-
| Drive
|
m------------ b
Pmm e
--
e -- e cmm--- Pm
Serial
data from drive
|
e e, e -------- - +
|36(18))35(37)| SIDE 1-
| System | Side select (0 = high)
|
e
-
Frmr
e -- e ------- Frm--mmm-- P
e, e e
s
e e m e --------- +*
13s(19)}37
- ------ R
|40
|39
|
X3
o mm e rr e .-
|
--
| NC
]
e ---------- P
{ NC
|
£=
§
m e --,--------- ~ -- ----- -- +
N
|
b
Pm - bmmm e
R
et
st
e r e, -- e m e -- == *
TECHNICAL REFERENCE
SYSTEM HARDWARE
2.4.6.6
Diskette Drive.
The
is equipped with one S 1/4-in,
self-contained
unit
consists
Texas Instruments Professional Computer
double-sided,
diskette
drive.
The
of a spindle drive, a head positioner,
and a read-write-erase system.
Plastic slot. things begins,
guides help to position
the diskette
inside
the diskette
After you insert the diskette and close the access door, three
happen:
the diskette clamps to the drive hub; a 500-ms delay
and the servo-controlled drive motor starts.
The head positioner is a 4-phase stepper-motor and band assembly with
some related electronics. to cause a one-track linear
diskette.
It moves the head movement) to the
]
(using one-step
proper
track
rotation
of
the
The following sensor systems are built into the unit.
* The
track
00 sensor.
This
switch
head/carriage system is at track 00.
determines
that the
* The index sensor.
HWhen the phototransistor
sees
the LED
light source through an index hole, it sends out a signal,
* The
write-protect
sensor.
When this switch finds a write-
protect head.
tab applied
to a diskette,
it
disadbles
the write
The
diskette
drive
reads
and
write operation records a 0.33-mm
writes (0.013
digital dat; using
in)
data
track,
MFM. which
The is
later
tunnel-erased
to
0.30
mm
(0.012
in). .The track-to- track
access time is 6 mes.
The drive speed is 300 rpm.
Table 2-12 gives the specifications for the diskette drive.
TECHNICAL REFERENCE
SYSTEM HARDWARE
Table 2-12
Diskette Drive Specifications
Physical Dimensions:
Height Width Depth Height
85.85 mm (3.38 in)
143.10 mm (S.87 in) 203,20 mm (8.00 in) 2.04 kg (4.50 1b)
Environmental Parameters:
Temperature
Operating
o
o
10
C to
40
C
o
o
(S0 F to 104 F)
Relative Humidity o
(@ 40 F wet-buld temperature,
no condensation
20 % to 80 %
Altitude
Mean sea level to 10 000 £t
Power Requirements
Voltage
+S vde
(+/- 0.25 V)
+12 Vde
(+«/- 0.6 V)
Current 600 mA
800 mA
Storage
o
o
-40
C to
65
¢C
o
°
(-40 F to 149 F)
S % to 55 %
¢ Mean sea level to 45 000 ft
-
TECHNICAL REFERENCE
SYSTEM HARDWARE
2.4.7
CRT Controller Board
The CRT controller board drives either a monochrome analog or a color
TTL display and makes the Texas Instruments Professional
Computer
a
complete alphanumeric and raster graphics system.
As
a stand-alone
option, the controller board provides one page of
high-resolution (80 columns x 25 lines) alphanumeric
display.
This
board
also supports the optional graphics video controller piggyback
board, which is described in Section 3.
The
system makes
no physical
distinction
between
color
and
monochrome;
the board
supports
output
in either eight-level gray
scale or eight-color RGB (red, green, blue).
Color is determined
by
the monitor
wused.
Refer
to Section 6, drawing 2223011, for logic
diagrams.
Figure 2-5 is a block diagram of the alphanumeric CRT controller board.
Table 2-13 lists the video ac parameters.
Figure 2-6 shows the timing diagram for the Alphanumerics State Machine PAL.
Figure 2-S Alphanumeric CRT Controller Board Block Diagram 2-38
SYSTEM HARDWARE
2
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TECHNICAL REFERENCE
TECHNICAL REFERENCE
'
SYSTEM
HARDWARE
Ref* Parameter
Table 2-13 Video AC Parameters
Value
Valuexx
Tolerance
A
Video dot freguency
B
Video dot pulsewidth
c
Character block
horizontal
D
Character block
vertical
E
Number of character
lines
;
F
Characters/character
line
G
Number of active
scan lines
H
Total scan lines
J
Vertical sync width
K
Vsync front porch
L
Vsync back porch
M
Vertical blanking
interval
il N
Active vertical
display time
Total vertical time
Q
Vertical rate
R
Hsync- width
s
Hsync front porch
T
Hsync back porch
u
Horizontal blanking
interval
v
Active horizontal
display time
W
Total horizontal time
X
Horizontal rate
18.000 MH=z $5.55 ns
9 dots 12 dots 2S rows 80 columns 300 320
0.156 ms 0 ms 0.884 ms 1.040 ms 15.60 ms 16.63 ms
60.10 Hz
4.50 us
2,00 us 5.50 us 12.00 us 39.99 us $1.98 us 19231 Hz
oo
1%
S
1%
--
--
14 scan lines
--
-
-~
-
-
350
S
385
SIS
0.156 ms
1B
0 ms
1Ry
1.664 ms
1%
1.82 ms
1IB%
18.20 ms
20.02 ms
49 .95 Hz
.
--
-
5
1% 1%
+ 2 Hz
1%
13 19
o
1IR%
--
19
S
1P%
S
100 Hz
* Letters refer to areas on the timing diagram in the next figure.
** These values reflect the vertical timing adjustments for SO0-Hz refresh.
CAUTION
S0-Hz operation can be used only
in
run
on
S0-Hz
1line
frequency.
operation in any
other
area
can
computer.
To select SO0-Hz operation,
ES-E6 on the motherboard.
areas Using damage
jumper
that SO-Hz
your pins
TECHNICAL REFERENCE
SYSTEN HARDWARE
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Figure 2-6 Alphanumerics State Machine Timing Diagram 2-40
TECHNICAL REFERENCE
SYSTEM HARDWARE
The CRT controller paragraphs include:
board
features
described
in the
following
Display characteristics
* o
Character attributes
Character sets
Cursor
Scrolling
Video connector
CRT controller IC
CRT screen/CPU arbjitration logic
CRT address decode logic
Character sets and attribute logic
* CRT interrupt logic
* Diagnostic loopback
2.4.7.1 follows:
Display Characteristics.
&
The display characteristics are as
TM
* A 7 x 9 character in a 9 x 12 image cell
* Twenty-five lines of 80 characters
* A resolution vertically
of 720
pixels
horizontally
x 300
pixels
* A horizontal scan rate of 19 200 lines per second * A vertical scan rate of 60 (50 frames per second) * A dot rate of 18.0000 MHZz
NOTE
The horizontal
scan
rate
is
an
important
consideration.
Many monitors
available
today
have a horizontal scan rate of
15 750.
Oonly
monitor
having
a horizontal scan rate of 19 200
lines per
second
can
operate
with
the
Texas
Instruments Professional Computer,
TECHNICAL REFERENCE
SYSTEM HARDWARE
2.4.7.2
Character
Attridutes.
organized as 2K bytes x 16 bits.
information.
The second 9 bits
character basis:
The
controller's
video memory is
The first 8 bits
convey
character
select the following attributes on a
* Bit 0, intensity level 1 (blue)
* Bit 1, intensity level 2 (red)
* Bit 2, intensity level 4 (green)
* Bit 3, character enable
* Bit 4, reverse
* Bit S, underline
* Bit 6, blink
* Bit 7, alternate character set
NOTE
The three intensity bits (bit 0 through
bit
2)
determine
the gray scale intensity level and. the
RGB outputs for .color.
Thus,
hi/norm
video in
monochrome is handled by a one-of-eight intensity
select instead of a high-intensity bit.
~
To access
the attributes, the software writes
into an attribute latch.
The attribute value is
character each time that character is written to
screen read is dons).
the attribute values
then assigned to the
the screen (until
a
When
any
character on
to the attribute latch.
latch read operation.
the screen is read, its attributes These values are then read by a
are copied subsequent
Handling
the attributes by
(moving data from one screen
their attributes.
this area
method ensures that, in block moves
to another), the characters
retain
TECHNICAL REFERENCE
SYSTEM HARDWARE
2.4.7.3
Character
Sets.
The
video
<controller
contains
a 4K
character generator ROM, which contributes 256 characters.
Use
the
socket
provided
character set to
to add an optional 2K or 4K the maximum Si2 characters.
ROM/EPROM and expand the Attribute bit 7 selects
the expanded character set.
Refer
ROM.
to subparagrahph
2.4.8.4
for more
information
on the
character
2.4.7.4
Cursor.
Programming can change the cursor appearance.
The
possibilities include blinking, non-blinking,
block,
underline
and
reverse-video.
Hardware
set
of registers
in
software can position the
handles the cursor display through a special
the
controller.
Using these registers, the
cursor anywhere on the screen (or
off
the
screen if no visible cursor is desired).
2.4.7.5
Scrolling.
The hardvare maintains
that supports character
1line scrolling
in
software
determines the need for a scroll,
a screen start register
four
directions.
The
then changes the value of
this register by one line.
The screen appears to jump by one
line.
The
scrolling operation always affects all of the screen.
possible to scroll one region without affecting another.
It is not
Because the controller contains
only
2K
bytes
scrolling
results
in a "wrap";
the original
of screen memory, top line of screen
contents moves to the bottom of the screen.
Therefore, the
softvare
must
clear the top line
up (or -down) operation.
operation, the 2K bytes
space.
of the screen (or bottom) before the
To simplify programming of the
1line
of memory is phantomed over a 4K-byte
scrollclear
address
Status lines must be implemented
operations,
the status line must
before writing.
The screen start
memory correspondence.
in software.
That is, during scroll
be moved to its new memory position
register
changes
the
screen-to-
TECHNICAL REFERENCE
SYSTEM HARDWARE
2.4.7.6
Video
Connector.
The video connector located on the
.edge of the PWB is a standard, 9-pin, female, D-type connector.
connector is for a color display unit.
The signals available on
connector are given in Table 2-1i4.
All signals are at
standard
levels.
rear This this
TTL
Table 2-14 Color Video Connector Pin-Out
`-v s
VWONOALEWON-
Function
Ground Logic ground Red video Green video Blue video Logic ground NC (no connection) Horizontal drive (NEGATIVE TRUE) Vertical drive (POSITIVE TRUE)
The
other
video
connector, on the lower rear edge of the
standard RCA phono jack.
This connector is for a monochrome
The signal avajilable at this connector is a composite type,
to-peak, 7S-ohm load.
a
PWB, is a display.
1 V peak-
2.4.8
CRT Controller IC
The CRTC IC (6S545A-1) contains the logic for:
* Generating the horizontal and vertical synchronizing signals
* Blanking display during retrace
* Addressing screen memory during screen refresh
% Cursor coincidence
* Starting screen display registers for use in scrolling
The CRTC contains eighteen registers that must be appropriately
set
before
board
operation
begins.
To access these registers, the CPU
first writes the address of the register to be accessed into the CRTC
address register.
Then information can be written to that
register.
When
writing
to or reading
from
(where
appropriate)
the data
register, the information is accessebdy the address latched
in
the
address register.
TECHNICAL REFERENCE
SYSTEM HARDWARE
Table
2-15S
shows
how to program these registers, using the
chip select
(CS),
register
select
(RS),
and
read/write
Assume the following conditions:
signals (R/W-).
* A character rate (SWM-) of 2.0 MHz
* 12 lines per character block
* 25 rows on the display
t 24 character times of horizontal blanking (12.0 us)
* 20 line times of vertical blanking (1.04 ms)
For more detailed programming information, refer to The Synercom Data
TECHNICAL REFERENCE
SYSTEM HARDWARE
Table 2-15 CRTC Programming Values
Signal Name
Register Address
cCsS- RS
R/K-
H
X
X
-
L
L
L
=
L
L
H
==
L
H
L
0o
L
H
L
1
L
H
L
2
L
H
L
3
L
H
L
4
L
H
L
S
L
H
L
6
L
H
L
7
L
H
L
8
L
H
L
8
L
H
L
10
L
H
L
11
L
H
L
12
L
H
L
13
L
H
X
14
L
H
X
1S
L
H
H
16
L
H
H
17
Legend H = L = X =
High signal. Low signal. Don't care.
Register Name
Refresh Rate Value
60 Hz
SO Hz
No register selected
-
Set address register
-
Set status register
Cs
Horizontal total characters
minus one
103
Horizontal displayed
characters
80
Horizontal sync position
84
VSYNC width, HSYNC width
39H
Vertical total rows minus 1
24
Vertical adjust lines
20
Vertical displayed rows
2S
Vertical sync position
2S
Mode control
OOH
Scan lines per row minus 1
11
Cursor start line and BLINK
40H
Cursor end line
11
Display start address high
O0H
Display start address low
OCH
Cursor position address high
O0H
Cursor position address low _
OCH
Light pen position address high
--
Light pen position address low
-
--- --
103
80 84 S9H 31 o0 2S 28 00H 11 40H 11 OO0H CO0H OO0H COH -
TECHNICAL REFERENCE
SYSTEM HARDWARE
2.4.8.1
CRT
Screen/CPU
Arbitration
Logic
Subsystenm.
The CRT
controller arbitration logic gives the programmer free
access
to the
CRT display.
There
is
1little
overhead
time caused by arbitration
conflicts, because the refresh memory and its control logic
allow
two
complete
memory cycles between esach character displayed on the screen.
One cycle accesses the character for display; the CPU
uses
the other
cycle for read or write operations.
Therefore, the CPU waits less than
tvo
display-character
times
for memory access.
Because a character
time is 500.8 ns and the CPU clock is 200 ns, a synchronization
delay
can occur.
The total time for a worst-case CPU access is 1.0 us.
The
usual access time is 600 ns (3 to O wait states).
The logic that generates this arbitration
scheme
includes
a counter
(which
also
counts
the
internal registers and gets
alphanumerics state machine
nine
dots
per character), a PAL (which has
feedback from the outputs),
and
a small
(vhich provides RAM buffer control, control
outputs
for
the RAM,
and
the vait state control for the CPU).
The
counter uses cycle of the
inputs to the PAL to identify the
state machine.
The internal PAL
state within the display
registers
define
other
states
used
during
the CPU read and write cycles.
cycle type being executed, the PAL uses
the
inputs
(character select), and ATSEL-(attribute select).
To define the CPU
RD-,
WR-,
CSEL-
The outputs from the PAL are:
* COE-, the RAM output enable
* CHE-, the RA{{ vrite enable
* AEN-, the attribute bus buffer enable
* AOE-~, the attribute latch output enable
* ACK-, the attribute latch clock
* MIE-, the character bus input buffer enable
* SHM-,
the. signal
that
from the CRTC to the CPU
switches the RAM address multiplexer
* HWAIT-, the CPU wait control line
The
counter
(U24,
8,9,10,11,12,13,14,15,0,
a
74LS163)
and repeat.
goes
through
states
aRLwdAaahvMttiaaccihhlafibsoUlr1ec0loatchvfikesarsoimlCiaPnbUclttlhheeeu)udnetRadiAtilMst.rbiertbchaueatTtuhheseeeerndloausttthohcepfohu,rt wttvh.iecinsldooCwcTPehkUinssa{bwrlhelteeaahdnditschrocenylatcacdoltaecp.htdtuahretweahseTlnhofecraaonrlmdeaAdChbtKuohselddastvb1ayliidnteehoi,esa combination of CSEL- and RD-.
TECHNICAL REFERENCE
SYSTEM HARDWARE
The CRT arbitration PAL programming is given in Table
2-16.
In the
"comment" column, the states generated by the AND of inputs are listed
according to the counter state number.
When the logical AND
of
terms
from one row is ORed with the AND of terms from another row, the output
goes low when the result is true.
Refer
to Figure
2-6 for an illustration of the timing produced for
typical cycles by the alphanumerics state machine.
TECHNICAL REFERENCE
SYSTEM HARDWARE
Table 2-16
Alphanumerics State Machine PAL
Input
X3
RD-
SHMUX
AEN~
X2
WR-
MIE-
ACK-
X4
CSEL~
CWE~
AOE-
Output
LD-
ATSEL-
COE-
HWAIT~
Comment
------ Rl Ak Bl e e
i Ak
e
P
ELLIRY ool
g
O Nl S
T ISR
% 8 86 .
4 5.0 LD S
0 & o
$8,9,10,11,12 X4 delayed All other terms
------ Rt e e e e el el e e e e R
e
el
Uy
MIE- ST LULEHIE. S LY LR
Ly
OF . - . e . I .I R
R LT
el
s
O
Il
i AR E R
S9 RAM write begins S10,11,12 RAM write All other terms
continues
------ e
o At
CHE L, Ly LUH S Y Ly LR A
T e
e -
Aem LWL
L
T
e ee
e e
S9 RAM write begins
.
OrRHALBL & H G
ONSLEHU LY H RIS
or
n
% 's
------ ot et
P
COE-
d o Ll 579
or ., L L HL
LT LEFRRCETE L
BT S
LS L= [0S LS
65H' o b d 6
b &
bt bbb e b e et b
SR
. R R
LT T
IS
s o6
b be
ey DS L
S10 RAM write continues
S11 RAM write continues
All other terms inactive
e cm et cmm e --cacccm e mm . ----
S13,14,15,0 screen £9,10 RAM read
refresh
e e
o LEF ori
------
SR
L
L
UENHEL
e
gio oo % o g g
TN
eI
S10,11,12 RAM read continues All other: terms inactive
o-0-o-o-¢-0--0-¢-0-¢-¢-¢-~--+-¢-«------------------~--1---------------------
AEN- L LLH.LL
5 d b 6 obh ik
OnMS -
<l TR
E, SR e
(7 a3t
iy o
e sig a8 4 0
'ty
S9 RAM write begins
S$10,11,12 RAM write $9,10 RAM read
continues
ONEF W HELBH L VI S
SR
SE 1
e
$11,12 RAM read
O LR URCIRH N L BT U
S TR S
A ---C ---KP =t SNLeH Bt EePH bStH Se bCb Ybet H r Neb b
e
All other terms
m e cctmc
e e m
S12 RAM read
inactive
e e
me e
e
(P 5l o« 5 d 1%
LAt
B
|-
(X o o808 5 5 o
o
T
Write attribute All other terms
latch inactive
------------ 0-0--0-0-0-0--#-#-0-#-0-~--0-¢-0--§-------------------------------------~---
AOE R L LT LHLIE N LA LR T
S HiL
S8 RAM write
I Cle O VUl ©
------
LENEES
Or (XY
o0' @ B gid M nima 48 46
K
g 1B & odb% & Ul 8 Bl o 18 R 555
S N S LW
TR
ST e L
Ol
W TL
LR
TeT Y L
P
b bt e b e b b b
b mbm
67674 8 0 BB 6
6 an e o 5.4
L. WE. SRS L
LY
R 1)L
a0 81V 0 'S 9,00 g 0 g
oo B
SS9 till not write
Read attribute latch
S13 till not read
S13 till not read
e e e e ee
eee e
RAM write before S9
RAM read before S9
All other terms inactive
m e
------ 0-0-0--0-0-0-0-&--0-0-o-v-¢~§-¢-¢-----------------------------~-------~-
Legend:
L = Low signal.
H = High signal.
TECHNICAL REFERENCE
SYSTEM HARDHARE
2.4.8.2
CRT Address
Decode lLogic.
The CRT controller board handles
both alphanumeric- and graphics- address decode for the CRT subsystem.
All
of
the
screen
data
is mapped into the processor memory address
space including the assorted latches and I1/0 ports.
The decoding is done with three 74L820, and a 74LS1SS decoder.
ICs:
a HALiIOL8
The PAL produces
PAL,
one-half
of a
the following signals:
* ZBEN-, the master expansion bus buffer enable
* XBEN-, the secondary bus buffer enable
* RD-, a decoded and buffered read control
%+ WR-, a buffered and decoded write control
* GSEL-, the graphics screen memory select
* CSEL-, the alphanumerics screen memory select
* CR/AT-,
selects
one half of the 74LS1iS55 (which decodes the
CRTC and the attribute latch)
* XSEL-, selects the other half of the
74LS15SS
(which
decodes
the graphics latch and the miscellaneous input buffer)
The XBEN- signal develops an enable
delaying
the
signal that provides
the 6545a-1 CRTC.
The CRTE
(CRT
greater than 266 ns, satisfying the
setup and hold times are easily met.
clock for the CRTC by inverting and
the required setup time {90 ns) for
enable)
signal
has
a pulsewvidth
requirement of the CRTC.
The other
The 74LS155 decodes the following signals:
* ATSEL~, the attribute latch select
% CRTSEL-, the CRTC chip select
* LAT-
LAT-
combines
with H®HR- and clocks
the interrupt enable and screen
enable latches.
The other
half
of
the
74LS15S5
decodes
the
three
graphics
board latches and the buffer enable for miscellaneous inputs.
The address space that each of these devices occupies is given in Table
2-17.
TECHNICAL REFERENCE
SYSTEHM HARDWARE
The red, blue, and green outputs are buffered by a 74LS244 before being
sent to the 9-pin connector.
The color outputs and composite sync
are
buffered
by a 74S00,
which
has an isolated power supply.
They are
combined by a resistor network and buffered by a transistor to make
up
the
composite video output.
The mapping of colors to intensity in the
composite video output is given in Table 2-19,
Table 2-19
Color Map
Code
Composite
oo
001 010
11 100 101 110 111
sync
Color
Black Blue Red Magenta Green Cyan Brown White
Composite Video Output (in Volts)
0.47 0.70 0.88 0.97 1.07 i1.10 1.28 1.37 1.47
To blank the alphanumerics display to black, set the CRT ENABLE bit
in
the miscellaneocus output latch to low.
The board enters this state on
pover-up.
<
2.4.8.7 contains
CRT Interrupt
Logic
a logic
subsystem
Subsystem.
The CRT
controller
board
that
allows
the CRTC
to generate an
interrupt during
the vertical
interval.
The processor
uses
this
interrupt
when
doing
scrolls
with a status line or other operations
that must be done during the vertical
blanking
interval.
To enable
this interrupt, set the interrupt enable bit in the miscellaneous latch
to high.
Vertical blanking causes the CPU nonmaskable interrupt, and
the
interrupt
pending
bit
is set.
This
Dbit
is
read
from
the
miscellaneous buffer.
To reset the interrupt, set the interrupt enable
bit to low.
2.4.9.8
Diagnostic
Loopback.
One diagnostic requires
color outputs be looped back to the miscellaneous input
the
CPU can
read them.
Using a program with careful
vertical interval, the CPU can check the action of
the
and the graphics board palette circuits.
that the three
buffer so
that
timing from the
atribute
bits
2.5 EXPANSION BUS
The bus.
the
other
logical
function
area of the motherboard
It provides space for the different option boards
Texas Instruments Professional Computer.
is the expansion
available
for
TECHNICAL REFERENCE
SYSTEM HARDWARE
2.4.8.5 Attribute Interaction.
The attributes available
the character
display
can be used
in any of
the
combinations.
The
following
paragraphs
explain
what
several attributes are active at once.
for use with
128 possible
happens
when
The attributes
have a priority
in
their
priority attributes affect all attributes that
The order of priority is as follows.
effects, and the highest have a lower priority.
Highest Lowest
Color attributes Reverse video and Character enable Blink Underline
- red, cursor
blue,
green
For example,
when
the wunderline and blink attributes are set, both
character and underline blink.
When the character
enable
is set
to
disable,
no character,
underline,
or blinking activity is present.
When reverse video and dlink are set, the character goes
on and
off,
the background
is lighted,
and the foreground is dark and blinking.
When the character enable is set to disable and reverse video
is set,
the entire cell is lighted (according to the color attributes).
The <color attributes define the characteristics of the "light" éortion
of the character, that is, either the color (when a color monitor
is
used) or the intensity (vhen & monochrome monitor is used).
When
the
graphics board is used
board, the graphics screen "shows
alphanumeric character display.
with the through"
alphanumerics CRT controller
the "dark"
portion
of
the
n
2.4.8.6
Attribute
Hardware.
The attribute
logic design is of the
"pipeline" type because the activity of the attributes must occur
with
dot-~timing precision (within 5SS ns).
To get data from a latch, through
several
levels of logic, and set up into the next latch, some SCHOTTKY
logic is used.
The attribute data from
the RAM 1latches
is latched
again
by
two 74S17Ss
(Ul16, Ul7).
This latching allows for the one-
character delay through the character ROM and
provides
tightly
timed
outputs
to
the logic.
The cursor (CUR) and display enable (DE) lines
are also
delayed
twice
to Xeep
them
synchronous
with
the
other
information (U1s).
Propagation delay through the logic can cause timing skews greater than
a dot
time, so the outputs of the first logic level are relatched one
dot-time later.
After going through the second logic level (MUX U20),
the
outputs
are
latched
again for presentation to the video outputs
(U39 748174).
TECHNICAL REFERENCE
SYSTEM HARDWARE
Two encoding examples are showvn in Figure 2-8
Example 1 character, and binary
is
the
letter
=Bty
Example 2,
meaningless
graphic
illustrates
some
specific applications.
Both hexadecimal
encoding are shown beside each character.
Example 1:
Example 1:
Dot Count 987654321
Bit Count 76543210 Hexadecimal
888FBBBBBBFF070FFFFFFFFFHHHHHHHHHHHH
Example 2: 67H A6H C5H E3H E7H 00H 6DH 92H CDH E8H F7H F7H
Binary 1 10000000 10111111 1011 101 10000111 10111111 10111111 10111111 10000000 1M1 1111111
0110011 10100110 11000101 11100011 11100111 00000000 01101101 10010010 11001101 11101011 11110111 1111011
LR oE
Notes: Column 1 and column 9 must be the same. Column 1 and column 2 must be the same if the high bit is 0. Column 8 and column S must be the same if the high bitis 0. No capability exists for a half-dot shift. Each character must have sixteen bytes; otherwise, strange characters result.
2232168
Figure 2-8 Encoding Examples
TECHNICAL REFERENCE
SYSTEM HARDWARE
Row RR1O RSRRRRR73264
RRRo810
Ril1(Underline)
Copied When Bit 7 is Low
e
e
b| t 6543210 I |
e
e
ij 6543210I|
n
RN .. B
B
-nEEEEER n
.........
P N
n
-
= n
n [
223216-7
Figure 2-7 Sample Character Font Definition
2.4.8.4
Generating a Character ROM.
To generate a character
ROM
(or
EPROM), assemble and link the source code, then program the device.
The source file for a character ROM is organized into 16 bytes for
of
the
256
characters (4056 bytes).
When assembled and linked,
file fits into a 4K ROM.
Each character can contain _only
12 rows
dots, and the last 4 bytes o; each character must be set to FFH.
each this
ot
Each character
on the monitor fits within a 9-column by i12-row block.
Each byte corresponds to the 9 columns within
one
row.
For regular
characters,
the first row is blank (reserved for ascenders), the last
two rows are blank (reserved
for descenders),
and
the
two outside
columns
are
wusually blank
(for intercharacter spacing).
Generally,
then, a typical character fits within a 7~column by 9-row block.
For esach character at the left.
block,
column
i is at
the right
side and column
9 is
Each byte is encoded as follows:
* Bit 0 (the low bit) is at the
right
side
of
the
character
block and bit 7 (the high bit) is at the left.
* Setting a bit to 0 means to put a dot at that location.
* Setting a bit to 1 means do not put a dot at that location.
* Setting
the high bit to 0 encodes column 1 the same as column
2 and encodes column 9 the same as column 8.
* Bit O encodes column 2; bit 1 encodes column 3; and so on.
TECHNICAL REFERENCE
SYSTEM HARDWARE
Table 2-18 Alphanumeric Decoding PAL
Input
MRDC-
A1S16-
A8
Als
Al12
Output:
AMWRC- A19
Al7
Al3
All
Comment
-------
e m e et
b
mm b
b e mr e c e r e -- e m e ------
ZBEN-
L
4
S
H
H
L
e
o
S
o
or .
L
s
H
H
L
a
S
P
o
CRT space read CRT space write
------- P m b mm e
e
e m b e m b mmd mwanmm
>
e -- -- --------
XBEN-
L
.
L
H
H
L
H
H
H
H
or .
L
L
H
H
L
H
H
H
H
CRTC/ATT CRTC/ATT
read write
------- P mm b m b et
m eb eb
me mb
p o
m
- --------
RD-
L
g
o
H
H
L
s
g
o
B
or L
L
3
s
o
.
5
5
o
e
CRT space read {Inactive term)
------- Prmmb e s
m b
m b mm-- b e, m--m b m b
--m b e md m e ------ St
----
e= -
WR~
o
L
o
H
H
L
5
S
5
o
or L
L
5
o
e
g
S
S
S
e
CRT space write (Inactive term)
------- L
e
R R
R
R
R
T R PR
GSEL~
e
3
H
H
H
L
e
5
a
.
or L
L
s
5
.
i
o
a
5
S
Graphic access {Inactive term)
------- et
CSEL-
.
.
L
or L
L
o
m
be e e
e e
H
H
L
H
H
L
E
B
.
o
.
s
-
-- -
- .- -
o
Character access
0
(Inactive term)
------- D R
it ittt
e
e e L ee
CR/AT- .
o
L
H
H
L
H
H
H
H
CRTCYATT access
or L
L
o
B
a
B
5
.
5
a
(Inactive term)
------- e m-- b mm
XSEL- . L Y
or L
o
L
b mm
N I
H
H
b et e b
e be eb
£
R HR £
m b T
L
H
H
H
L
e
m---- e
Extra I/O
Extra I1/0
-- =
write
read
Legend: L = Low signal. H = High signal,.
2.4.8.3
Character
Set and Attribute Logic.
Two 74LS374s8 (Ul4, ULlS)
latch the RAM output (both character and attribute) at the end of each
screen
refresh access cycle.
This allows a full character cycle time
(S00.8 ns) to access the character ROM and EPROM and
set
up
the
dot
shift register.
The required ROM access time is 452.8 ns.
So that the
character
set can include the ability for block graphics, bit 7 out of
the ROMs indicates that the leftmost and rightmost character
dots
are
to be copied
to
the left and right character-cell border dots.
The
character ROMs should be programmed with active-low data; that is, when
a dot is to appear, the ROM should be grogrammed with a zero.
Figure 2-7 the cursor appears on only one
underline,
shows some sample characters.
The reverse video
block and
affect
the entire
9 x 12 character cell; the underline
row 11.
The descenders of lowercase
letters
should
drop
dot line below the level of the other characters so that the
cursor, and reverse video will appear in an acceptable form.
TECHNICAL REFERENCE
SYSTEM HARDWARE
Table 2-17 CRT System Memory Map
Address
COO00-C7FFF C8000-CFFFF DOOOO-D7FFF D80CO-DDFFF
DEOOO-DE7FF DESOCO-DEFFF
BFO0CO Dbit
DF000
Dbit
DF000
Dbit
DF000 Dbit
DFOL10 DFO0O20 DF030 DFBOO
DF810 DF8i1 DFBe12 DF813
DF820 DFB20
Dbit 7?7 Dbit 6
WN e
Device
Graphics RAM Bank A Graphics RAM Bank B Graphics RAM Bank C Unusable
Active character memory Phantom character memory
Misc Misc Misc Misc
input input input input
buffer, buffer, buffer, buffer,
blue feedback, read only red feedback, read only green feedback, read only interrupt pending, read only
Graphics Graphics Graphics Attribute
blue palette latch, write only green palette latch, write only red palette latch, write only
latch
CRTC CRTC CRTC CRTC
address register, write only status register, read only registers vrite access, write only registers read access, read only
Miscellaneous Miscellaneous
output output
latch, latch,
inte;rupt enable alphanumerics screen
enable
PAL coding is given in Table 2-18.
When the logical AND of terms
from
one row is ORed with the AND of terms from another row, the output goes
low vhen the result is true.
TECHNICAL REFERENCE
SYSTEM HARDWARE
The
expansion
bus
interface
consists
making it easy to add memory-mapped
or
system.
The expansion bus supports devices
efficient
operation.
The system does not
hardware required by direct memory access
of five card-edge connectors,
1/0-mapped
options
to the
that require interrupts for
provide the special-purpose
(DMA) devices.
The expansion bus pin-outs are given in fable 2-20,
Table 2-20
Expansion Bus Pin-Outs
Pin
AO1L
AOD2
AO03 AO4 A0S
AO6
AO7 AO8
ACS
AiOQ ALl
AL2
AlL3
Ald
AlS
Ale
AtLt7
AL®
AlS A20 A21
A22
A23
A24
A2S
A26
A27
A28 A29
A30
A31
* MSB
Signal
NMI-
DATA 7
DATA 6
DATA S
DATA 4
DATA 3
DATA 2
DATA 1
DATA ©
WAIT-
Logic ground
ADDRESS 19 (MSB)«*
ADDRESS 18
ADDRESS 17
ADDRESS 16
ADDRESS 1S
ADDRESS 14
ADDRESS 13
ADDRESS 12
ADDRESS 11
ADDRESS 10
ADDRESS 9
ADDRESS 8
ADDRESS 7
ADDRESS &
ADDRESS S
ADDRESS 4
ADDRESS 3
ADDRESS 2
ADDRESS 1
ADDRESS o©
(LSB)*
= Most significant bit;
Pin
Signal
BC1
Ground
BO2
RESET
BO3
+S V power
BO4
IRO
(interrupt 0)
BOS
No connection
(bussed)
BO6
No connection
(bussed)
BO7?
-12 V power
Bo8
Reserved
BOS
+12 V power
BioO
Ground
Bii
B12
AMWC-
MRDC-
(memory write)
(memory read)
B13
AIOHC- (I/0 write)
Bi4
IORC-
(I1/0 read)
B1S
No connection (bussed)
B1i6
No connection (bussed)
B17
No connection (bussed)
Bis
No connection (bussed)
Bi9
No connection (bussed)
B20
PCLK
(S-MHz clock)
B21
IRG
(interrupt 6)
B22
IRS
(interrupt S)
B23
B24
IR4
(interrupt 4)
IR1
(interrupt 1)
B2S
IR2
(interrupt 2)
B26
B27
RNoFSHconn(ercetfiroenshing()bussed)
B28
ALE
(address latch)
B29
+S V powver
B30
B31
oscC
{15-MHz
Ground
clock)
LSB = Least significant bit.
TECHNICAL REFERENCE
SYSTEM HARDHWARE
2.5.1
Expansion Bus Signal Descriptions
* NMI-.
The nonmaskable interrupt signal can be driven
by any
of
the expansion
boards
to interrupt the system processor.
Typically, it is used to alert the processor to a parity error
in memory devices
residing
in
the
I/0 channel.
An open
collector
device
pulls this line low when it is being driven
by an expansion board.
Othervise, it is held high by a pullup
resistor.
* DATA 0-7.
These lines form the 8-bit system data bus and
can
be driven
by the processor,
memory
devices,
I1/0, or the
expansion interface.
These bidirectional
1lines are active
high.
DO is the least-significant bit, (LSB) and D7 is the
most-significant bit (MSB).
* WAIT-.
This signal indicates when a device
is holding
the
system
processor,
thereby
extending
the length of a memory
refresh or 1/0 cycle.
When a slow device is addressed on the
expansion bus, the signal asserts this line low, which extends
the cycle-completion time.
This line should never be held low
longer
than
10 processor
clock
cycles.
When driven by an
expansion board, an open collector device pulls this line low.
Otherwise, a pullup resistor helds it high.
«
* ADDRESS 0-19.
These lines form a 20-bit system
address
bus,
which
can address
up to 1 megabyte
of memory.
They are
normally driven by the system processor to address memory and
1/0 devices within the system.
(Only XAO trough XA9 are used
for 1/0 addressing.)
These lines are active high.XA0
is the
LSB and XAl9 is the MSB.
* RESET.
This line injitializes or resets system logic at power-
up
or after
a power fajilure.
It is active high.
A power-
supply monitoring device generates RESET immediately when
the
12-V
line
drops
below
11.1
V.
It returns low 3 ms after
regulation resumes.
No operator intervention is required.
* INTERRUPT 0-6.
These lines signal the processor that
an
I/0
device
requires
attention.
When
several
devices
require
service at the same time, the device
asserting
the
lowest-
numbered
1line gets
serviced
first.
These lines are active
high.
The interrupt regquest signal must be held
high until
the interrupt request has been acknowledged.
* AMHC~ (or MHRITE-).
The memory write signal is usually driven
by
the
system ubdex(AMWC-) processor.
It indicates that the
information on the data bus should be written
to the memory
address given on the address bus.
This signal is active low.
* MRDC-
(or MREAD-).
The memory read signal is driven by the
TECHNICAL REFERENCE
SYSTEM HARDWARE
system processor.
It
the address bus should
indicates be placed
that on
the memory the data bus.
addressed
by
This signal
is active low.
*
AIOHC-
system
by
the
or
(IOWRITE-).
The I/O write signal
processor.
It indicates that the 1/0
address
bus
should accept the data
is driven by the
device addressed
on the data bus.
This signal is active low.
*
IORC- or (IOREAD-).
The I/0 read
processor.
It indicates that the
address
bus
should
place
its
line is driven by the system
I/0 device addressed by
the
data
on the data bus.
This
signal is active low.
* PCLK (processor clock).
This is the system clock.
It
is
a
one-third division of the 0SC clock and
(S.0
MHz).
The clock has a duty cycle
has a period of of 37.6 percent
200 ns (+ 3.0
percent).
* RFSH (refreshing).
This line indicates that a memory
refresh
cycle is taking place.
It is positive true.
When this
is asserted,
all
expansion bus activity is ignored.
signal Do not
use this line for any purpose.
* ALE (address latch).
This line indicates that
is placing a valid address on the address bus.
valid on the falling edge of this signal.
the processor The address is
* O0SC
(clock).
This signal describes a high-speed
a 66.7-ns period (15.0 MHz).
It has a SO0-percent
clock having duty cycle.
2.5.2
Loading and Driving Requirements
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2.5.3
Memory Timing
The
memory
bus
cycles
CLK cycle time (200 ns)
timing relationships of
can be lengthened in integral multiples of
using the WAIT- line.
Figure
2-9
shows
the expansion bus memory interface.
the the
SYSTEM HARDWARE
Figure 2-9 Expansion Bus Memory Interface Timing Diagram 2-60
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TECHNICAL REFERENCE
TECHNICAL REFERENCE
SYSTEM HARDWARE
2.5.4
1I/0 Timing
Figure
2-10
shows the expansion bus timing relationships for standard
I/0 cycles.
This timing
includes
the
single
wait
state
that
the
motherboard always inserts in I/O cycles.
--+| 67 le-- 133 --sle-- 200 --
1 ! 1
ALE
'I
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Figure 2-10
Expansion Bus I/0 Interface Timing Diagram
2-61/62
= i
TECHNICAL REFERENCE
HARDWARE OPTIONS
Section 3 HARDWARE OPTIONS
3.1
INTRODUCTION
This section describes the
Instruments
Professional
following options:
hardware options available
Computer.
Subsections
for
the Texas
describe
the
* Expansion Memory
* Synchronous-Asynchronous Communications Board * Internal Modems
* Graphics Video Controller Board
* Hinchester Disk Drive
The optional diskette drive is
identical
to the
diskette drive.
Therefore, it is not described in
Jinformation, refer to subparagraph 2.4.6.6.
factory-installed
this section.
For
3.2 EXPANSION MEMORY, S512/768 K BYTES
Section
2 describes the expansion memory boards that connect to the
motherboard, increasing the memory to
2S6K
bytes
(K = 1024).
Two
additional
expansion
memory
boards (each 256K bytes) are available
for the Texas Instruments Professional
Computer.
One
board
plugs
into
the
expansion
bus,
increasing the memory to S12K bytes.
The
second board mounts on the first (piggyback style so
that
they use
only
one of the expansion bus slots), increasing the memory capacity
to 768K bytes.
This additional memory operates at the same speed
as
the motherboard
memory,
so
that there is no increase in execution
time when the memory is increased.
NOTE
The 512/768
after
the
installed.
K byte
expansi'on
boards
motherboard
192K-byte
are added
board
is
TECHNICAL REFERENCE
HARDWARE OPTIONS
The first expansion contains thirty-six
£
memory card is the controller
64K-biéesdynamic RAM ICs.
The
* Decoding logic to estadblish the addresses
card.
This
card
card -
also
holds:
* Parity check logic for error detection
* Timing
and
system.
refresh
logic
to operate ;
the expansion
memory
Connectors and logic for the addition of the are also part of the controller card.
second
expansion
card
The
second
Becausge the
this second
card
also
contains thirty-six
controller card contains all the
card is smaller.
64K-bit dynamic RAM ICs.
logic
for
both
cards,
3.2.1
Addressing the Expansion Memory
The
expansion
memory
operates at a fixed address in the computer's
memory space.
Addresses 040000H through 07FFFH
are
for
the first
256K bytes;
addresses
O08B0000H
through
OBFFFFH are for the second
256K bytes.
If the second card is not installed, its assigned memory
space can be used by other hardware products.
$.2.2
Expansion Memory Control Logic
The expansion bus contains a bidirectional
buffer
to separate
the
data
bus
from
the
expansion
memory, thereby providing sufficient
drive and margins to the data transfers.
The hard array logic
(HAL)
chip HAL1I6R4
(U2) handles address decoding, buffer control, as well
as timing and refresh.
The refresh timer (U4) is a one-shot, and the
delay line (U3) provides the multiplexer timing.
3.2.2.1
Expansion Memory Refresh Logic.
The
dynamic
RAM
refresh
logic
operates
synchronously
with
the accesses to the RAM memory.
Refresh cycles begin only when a RAM cycle is not in progress.
This
means
that the RAM refresh can occur at the same time as accesses to
other system memory (ROMs or the main system memory)
or
I/O space.
Each
time a refresh cycle begins, a refresh timer (U4) starts.
When
it times out, it provides the signal beginning another refresh cycle.
This timer is set to 15 us maximum, which allows for
the worst-case
refresh
request
latency.
To maintain the contents of the RAM under
worst-case conditions, the refresh must
occur
at
1least
128
times
within
2 ms.
(The average refresh timing is once per 15.625 us.)
The worst-case latency for a refresh request is about 600 ns.
Once a refresh cycle has
precharge)
before
the
starts before the refresh
the CPU into a wait state
begun, next
cycle until
it must be completed
(incliluding
cycle
begins.
If a RAM access
completes, the HAL state machine
the refresh operation completes.
the cycle
puts In
TECHNICAL REFERENCE
HARDHARE OPTIONS
the worst case, this delay could by three wait states or 600 ns.
extend
the usual
memory e
access
time
Assuming slowdown percent.
a refresh time; r
of
the
CPU,
The worst case
value
of
14
wus,
and
BT
an
o
`average
400-ns
the average
refresh
overhead is about 2.9
is about 4.3 percent.
1
3.2.2.2
CAs and Address MUX Switch Generation.
A delay
the
Column Address Strobe X (CASX-) produces the address
1line from multiplexer
control (MSEL).
The delay line is set at
CASI-
1line,
and the RAM buffers are taken
after CASX-.
This ensures the maintenance
hold, and enough column address setup time.
quickly enough to finish an access within
40 ns.
Ul Dbuffers
the
from the delay line 60 ns
of an adequate row address
The RAM
still
operates
the system cycle time.
The CASX-
timing depends on wvhether the cycle
If the cycle is a read, the CASX- signal
from
equivalent
to the RASI- signal.
This provides
time for the RAM chip to access it's
data
and
expansion
bus.
The
delay
line
guarantees
CASI- to the dynamic RAMs.
is a read or a write.
the logic
array
is
the maximum available
present
it
to the
the timing of MSEL and
If the cycle is a write, edge of the first system
then the CASX-
signal
clock during the write
follows
the
cycle.
This
130 ns after the occurrence of RASI~. data from the processor to propagate the parity generator chip (74LS280).
This delay allows time through the data buffers
rising is about
for the and Ue,
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When the RAM
presented
to
at the end of
flop US is set
clears on the
this board.
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Using the "odd sum" method of parity
error, even vhen the system attempts
(To determine
the
size of system
"feels" for memory not present.
checking does
to read
from
memory, system
not cause a parity
nonexistent
RAM.
software sometimes
TECHNICAL REFERENCE
HARDWARE OPTIONS
3.2.2.4
Expansion Memory Control State Machine.
A hard array
1logic
device
(HAL16R4),
set up as a state machine (U2), drives the memory
control.
This device has four outputs egquipped
with
clocked
flip-
flops
and
four
outputs that are direct combinations of the inputs.
Table 3-1 gives the logic for the memory control state machine.
The
logical
AND of the
terms
on a line ORed with the AND of terms on
other
lines
results
in low-going
outputs.
This
occurs
either
directly,
on
those outputs without registers, or after the c%ock on
those outputs having registers.
!
TECHNICAL REFERENCE
HARDWARE OPTIONS
Table 3-1
Expansion Memory Control State Machine Logic - HAL16R4
Input
MRD-
XA18
RASI-
RFSH-
MHR-
LGND-
XWAIT- RRAS-
Output
RFRQ XA19
XXXX B2IN-
CASX- WCASBUFE- ZzZZ-
-------------- ottt bbb b
m P
-- b
m =
Comment
RASI-
L
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IRHEHE
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L IHELL
L
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LR HE LR
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or L
M HELA LT
.
.
o B
--_------ - et
e b m bbb mc bbb bbb
------
BUFE-
LR U 1 R DA
o 0 m
or or or
_______
. L
HLL .L
L
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L .
HLL . L
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IR
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Memory read low bank Memory read high bank Memory write low bank Memory write high bank Refresh
Refresh+memcycle 1, 2 Refreshrmemcycle 2, 3
Write, either bank Read low bank Read high bank
Write low bank Write high bank Read low bank Read high bank
The
_______ Pmd
following four outputs
e bbb
bbb
m b e b
have flip-flops:
m
=&
RFSH-
H H H
or
HELW LS VR,
or .
HEH S H ST
or
W HEHE LS SRS H
(P 9 o 00 o ld' o b
(12 6 0 o o 8.0 D g
.
T
.
.
SR
S
.
B
H
H RS
H RS
B
o
W H
.
LRHET
Refresh Refresh Refresh
Refresh Refresh Refresh
no memcycle motherboard cycle graphic cycle 1; high bank not in 1; illegal cycle RF2,3
CY2e% % o g0 0 b
.
H.
-------e -- - Por bbb
m b m b
RRAS SO
. IR -
b
bbb b
-
L
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.
.
.
.
---------- Pebm bbbk
WCAS -
LR S H N LI
bbb
e
b b m b b e ==
. HH
orE LIS HELEL NS I
o
SR S HR H
O KRN LT S
o
-
o
------ -
bbb e bb rm bb b e b
-
ZZZZ -- S Ul 7 NS
3D .
Reset
Refresh RF2,3,4 Reset
Write low bank Write high bank Reset
--_--------- - Pt bbb b --
Legend
L = Low signal.
e bbb
bbb
m bbb ==
) s
H = High signal.
3-5
TECHNICAL REFERENCE
HARDWARE OPTIONS
Notes for Table 3-1
Ofl..Q_
The signal RASI- activates 'RAS- from the RAM address
multiplexer of the 2364.
;
The signal XWAIT- puts the processor into a wait state,
The signal BUFE- activates the expansion memory system data
buffer.
The signal CASX- controls the CAS and MSEL generation.
The signal RFSH- instructs the 2964 address multiplexer to
put out the refresh address.
:
The signal RRAS~ combines with RFSH- to indicate that a
refresh RAS is in progress.
The signal WCAS~ delays CASX- during a write cycle.
The signal ZZZZ-
is not used.
A timing diagram of the memory system, shown the major operations of the memory system.
in Figure
3-1,
indicates
HARDWARE OPTIONS
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Figure 3-1 Expansion Memory Timing Diagram
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TECHNICAL REFERENCE
TECHNICAL REFERENCE
HARDHWARE OPTIONS
3.3 SYNCHRONOUS-ASYNCHRONOUS COMMUNICATIONS BOARD
This subsection describes the theory of operation and
the
functtons
of
the
synchronous-asynchronous
communications
(sync-async
comm)
board.
Figure 3-2 is a block diagram of the sync-async
comm board.
Refer to Section 6, drawing 22230986, for logic diagrams.
SAECLKECT
ADADDDRREESSSS ]
SEL--E_--CT INPUT SELEC--T OUTPUT
ALODoEDGCRIOECDSES SCEOLMECMT
INPUSCTEY/LCOELUCETTPUT
SYiSsTteEM BOARD Cj
DATA BUS
INTERRUPT
ACIKNNTLOEOWRGLAICUEPDTGE
INT ACK
CcLOCK
(\SELE10CT
CHIP SELECTOR
1/08US
>
DATA BUS
¥ COMCMOUNNTIROCLALTEIRONS
1 INRTSS-E2:3B2F-ACCE
2 DAvTA BUS
Recs.n.`vens +:- }
5
: |
|I®j EDXETVEIRCNEA£SL
|
TRANSMITTERS
G
INTERRUPT LOGIC
2223216-12
Figure 3-2 Sync-Async Comm Board Block Diagram
The
sync-async
comm board
is
Communications Controller (SCC).
based
upon
This device
the Zilog ZBS30 Serial
automatically
handles
asynchronous protocols.
It also services most synchronous protocols,
including
data
link control
(HDLC), (both bit-oriented.)
(SDLC) Cyclic
and high-level data 1link
redundancy
check
(CRC)
control is an
automatic function and can be included in any transmission.
A sample procedures
NOTE
program,
showing
general
and recommended use of the
programming sync-async
TECHNICAL REFERENCE
HARDHARE OPTIONS
comm board,
is included
in Appendix
manual.
For more detailed information,
the Zilog 8530 Technical Manual.
E of this
refer
to
The functions of the sync-async comm board are:
* System interface * Baud rate generation * Port addresses
3.3.1
System Interface
Most
of
interface
the
components
on
the board are involved in handling
between the system bus and the 2Z8530.
Of special
note
the is
the logic
that
generates the interrupt acknowledge (INTACK) signal
that the Z8530 requires in response to an
interrupt
request,
The
INTACK~
signal
is software-generated.
It is not part of the system
interrupt acknowledge signal because of the setup time
because
the
system expansion bus does not provide for
required expanding
aad the
number of interrupt levels.
To generate the
the I/0 address
(read)
from the
interrupt vector
INTACK- signal, the software does
for interrupt
acknowledge
and
same address.
The data received
from the Z8530.
~
a AIOWC- (write) to
then
does
a
IORC-
on this read is the
The AIOWC- signal clears US5B, activating the INTACK-
signal
Z8530.
Hhen
the
IORC-
occurs, the vector from the Z8530
onto the data bus.
The rising
edge
of
IORC-
clocks
USB
inactive state which releases the INTACK-.
to
the
is gated
to
the
Other logic on the system side of the board delays the read and write
commands
to the SCC so that the address and data setup times and the
hold-time requirements of the part can be met.
IORQ is connected
to
the
input of a flip-flop 74LS74 (USA).
The clock input is connected
to the system CLK line.
The rising edge of the clock occurs
133
ns
after
the
IORC-
or AIOWC- signal occurs.
The output of USA, gated
with IORC- and AIOWC-, delays the start
of
the SCCRD-
and SCCKR-
signals.
The
clear input to USA is connected to BDCS, allowing the
SCCRD- and SCCWR- signals to occur only when the board is selected.
Resetting the
held
active
and U6D with
lines.
Z8530 requires simultaneously. the RESET signal
that This from
the SCCRD- and the SCCWR- lines
be
results from the logical OR of U6C
the bus and the SCCRD- and
SCCHR-
U4C
inverts
and
buffers
the
interrupt output from the SCC.
signal then goes to a set of stake pins and is used to determine
This the
3-9
TECHNICAL REFERENCE
HARDWARE OPTIONS
interrupt level at which the board is operated.
3.3.2
Baud Rate Generation
The 4.915S2-MHz
<c¢rystal
provides a clock for the
generate a specific baud
oscillator
on
the board,
divided
by 2,
SCCs (internal baud
rate
generators).
To
rate, program the values given in Table 3-2.
Table 3-2 Sync-Async Comm Board Baud Rate
Baud Rate
i9 200 9 600 7 200 4 800 3 600 2 400 2 000 1 800 1 200 600 300 200 150 134.5
110
75 SO
Sync Value
62 126 169 254 338 S10 612 681 1022 2046 4094 6142 8130 9134
11169
16382 24574
Percentage of Error
6.000 0.000 -0.196 0.000 0.088 0.000 0.065 -0.045 6.000 0.000 0.000 0.000 0.000 0.001
~0.001-
0.000 0.000
Async Value
2 6 8 14 19 30 36 41 62 26 54 82 10 69
96
1022 1534
Percentage of Error
0.000 0.000 -3.030 0.000 1.587 c.000 1.053 -0.775 0.000 0.000 0.000 0.000 0.090 0.001
0.026
0.000 0.000
TECHNICAL REFERENCE
HARDWARE OPTIONS
3.3.3
Addressing
A 74LS139
decoder
(U3)
and several gates (to qualify the address)
comprise the address selection logic.
The board
design
preseats
a
choice
of four address locations, permitting the addition of several
communications boards to the system.
As with other
are
decoded.
1/0 devices for U3 provides
this two
bus, only 10 of the address
decoded
outputs:
INTCS-,
lines which
activates the INTACK logic; and SCCCS-, which
activates
the Z8530.
The
logical
OR of INTCS~ and SCCCS- creates the board select signal
(BDCS).
The logical AND of IORC- and AIOWC~ creates IORQ.
BDCS
and
IORQ combined enable the bus buffer U7.
3.3.4
Programming
The
sync-async
comm
board
port
number
is
jumpers on the board.
Five I/0 addresses and
level control each port.
programmed a distinct
by placing interrupt
Table 3-3 gives the board addresses is the board connector.
for
the four possible
ports.
P60
TECHNICAL REFERENCE
HARDWARE OPTIONS
Table 3-3 Sync-Async Comm Board Port Addresses
Jumper Locations E1-E2 E7-E8
P6C Pin No. 8 (INTO)
Port 1 Interrupt
Address
OOEOC 00E4 00ES O0E6 00E7
Function
Interrupt acknowledge CHB command CHB data CHA command CHA data
E4-ES E10-Ei1
Port 2 Interrupt
SO0 (INTL)
OOCES 00EC OO0ED OOEE OOEF
Interrupt acknowledge CHB command CHB data CHA command CHA data
E2-E3 E8S-E9
Port 3 Interrupt
48 (INT2)
OOFO COF 4
COFS OOF6 GCF7
Interrupt acknowledge CHB command
CHB data CHA command CHA data
ES-E6 E11-E12
Port 4 Interrupt
46 (INT4)
OOF8 OOFC O0FD COFE OOFF
Interrupt acknowledge CHB command CHB data
CHA command
CHA data
- y
TECHNICAL REFERENCE
HARDWARE OPTIONS
Two channels
(A and
B) from each port control the Z8530 operations.
Channel A, the main communications channel through which data
transfer
takes
place,
also monitors or controls some of the RS-232-C signals.
Channel B does nothing but control or monitor signals.
It is not
wused
for data transfer.
i
Each channel
can be accessed by two addresses:
The command address for either channel is used to
read
or write
registers that control the Z8S30
address for channel A is used
to read
received
transmitted data.
The data address for channel B
"command" and "data."®
access any of the
1§
operations.
The data
data and
to write
is not used.
Because
the
2Z8S30
does not contain pin-outs for the DSR, SCF, and RI
signals, unused pins from channel B are used for these signals.
Table
3-4
lists the specific pin-out for these signals.
Table 3-S5 lists the
Channel B pin-out for the Z8530 interrupt enables.
Table 3-4 Channel B Pin-Out for Z8S530
Z8530 Signal
Channel B Pin-~Out
DSR
DCD
SCA
DTR
SCF
SYNC/HUNT
RI
CTs
Table
3-S5 Channel B Pin-Out for Z8530 Interrupt
28539 Interrupt
Channel B Pin-Out
Enable
DSR
DCcp
SCA
none
SCF
SYNC/HUNT
RI
CTS
Each port has an I/0 address used to acknowledge the 28530
interrupts.
An
I/0 write followed by an I/0 read done at this address acknowledges
the interrupt.
The data written during the I/0 write
is
irrelevant.
After
the
1I/0 read, the Z8530 returns the code for the interrupt that
occurred.
These
codes
are
explained
in the
Zilog 8530 Technical
Manual.
:
TECHNICAL REFERENCE
HARDWARE OPTIONS
TthheefMegxmtaeirlnsal a*t contnhiesctorconn`e9c6t9o)r. is an RS-232-C type.
Tabl. e,3-6
ident®ifies
Table 3-6 RS-232-C Connector Signals
e --m------ P
--
e, m e, e e ----r e,
-- === D
et +*
{ Pin
|
Signal Name
} signal
i
r------------ e m e
et mm e e tmm
+
1
i Chassis ground
2
| Transmitted data
3
| Received data
4
| Request to send
S
| Clear to send
6
| Data set ready
7
} Signal ground
8
| Data carrier detect
9
| Ko connection
10
| No connection
| sSecondary request to send
i AA
1
i BA
|
| 8B
i
i RTS/CA
|
| CTS/CB
|
| DSR/CC
|
| AB
|
] DCD/CF
|
i
oo
|
|
-
|
| sca/cCH
§
{ Secondary clear to send
| scF/cCI
f
13
| No connection
|
--
f
14
| No connection
15
| Transmitter clock in
16
| No connection
17
i Receiver clock in
18
| No connection
19
| Xo connection
20
| Data terminal ready
21
| No connection
22
| Ring indicator
23
| Same as pin 11
24
| External transmitter clock
25
| No connection
|
=
|
i TXC/DB
|
|
S
|
i RSC/DD
|
1
-
|
|
S
|
| DTR/CD
l
| A
)
1 RI/CE
i
i SCA/CH
|
i DA
|
1
2o
|
o ---- P m e m e, --,--
e e
-
- ---------- tmmmm== -
3.4
INTERNAL MODEMS
Texas
Instruments
offers
two internal modems for the Professional
Computer.
One is a Bell 103-compatible type, which operates
at
300
baud.
The
other
is Bell 212-compatible and operates at 1200 baud.
Both are full-duplex modems, and the Bell 21i2-compatible can
operate
in full-duplex,
synchronous,
1200 baud.
These are "smart" modems,
and can handle a variety of commands for establishing communications.
Both modems have automatic dialing capability using either
pulse
or
tone
dialing.
The modem also
provides
status
indications
for
monitoring the progress of the dialing procedure.
The following subsections describe the architecture and interface
of
the modems to the system for those users who want to write their own
communication program, and who want to use an internal modenm.
TECHNICAL REFERENCE
HARDWARE OPTIONS
3.4.1 Architecture
.
»
The interface hardware for the modem board
is identical
to
that
created
for
the sync-async
c¢omm board.
Therefore, it is easy to
adapt software written for the sync-async comm board so that
it can
operate
with
either of the modems.
Adding code to handle the modem
dialing procedure is
the major
change
required.
The
same
port
addresses
and interrupt levels used by the sync-async comm board are
used by the modem bdoards.
Figure 3-3 shows a block
diagram
of modem
hardware. : The
serial
controller
(Zilog
8530)
sends
the modem commands during the modem
initialization and dialing procedure.
Then the 28530 transfers
data
between the modem and the remote system.
(1 Z8I5L3O0G
MICROPROCESSOR (2)
MODEM
RJ 1 3) RJ
Figure 3-3 Modem Hardware Interface
223218-13
3.4.2
Zilog 8530--Modem Signals
Two special control signals,
(acknowledge
control mode),
passed by the Z8530.
/RNCTL
while /ACNTL information is
/RNCTL (request control mode) and /ACNTL
tell the modem how to handle information
information is processed
as
commands,
interpreted as data to be transmitted.
The
signals that appear at the Zilog 8530--modem interface are shown
in Figure 3-4,
TECHNICAL REFERENCE
HARDWARE OPTIONS
Zilog 8530
Modem
15 (/TD) 13 (/RD}
----
BA
<------
BB
18 (/CTS)
«~-------- /CB
16 (/DTR) 21 (/DSR)
----> /CD <------ /CC
29 (/sbCD) <«-------- /CI
19 (/DCD) 22 {/RI}
<------ /CF <«------ /CE
23 (/RTSB} ----
/RCNTL
11 {/SYNCA)} «-------- /ACNTL
12 /RTXCA) <------ /RX CLOCK 22 (/TRXCA} «-------- /TX CLOCK
27121614
Figure 3-4
2Zilog 8530--Modem Interface Signals
The following paragraphs give brief descriptions of these signals.
NOTE In the following descriptions, "ON" refers to an active~-low TTL voltage level.
(/TD) -> BA The
Z8S30
sends
condition of /RCNTL determines
data or command data).
BB -> (/RD)
The
modem
sends
condition of /RCNTL determines
data
to the modem on this line.
The
the type of data
(either
transmitted
data
to the Z8530 on this line.
The
the type of data
(either
transmitted
TECHNICAL REFERENCE
HARDWARE OPTIONS
data . or command R data).
=> /CTS
.Hhen
this
signal is on, the modem is ready to receive
transmitted
Z8530
can
data from the 28530.
Even when this signal is off,
the
9till
send command data if /ACNTL is on and /CD (DTR) is
off.
No transmitted data is sent while this signal is off.
{/DTR) -> /CD When this
the communication.
This
command mode, but before
start-dial
command
is
"command failed"" status.)
signal signal giving given
is on, the terminal is ready
is turned on while the unit
the
start-dial
command.
before /DTR is on, the modem
to start
is in the
(If
the
returns a
/C -> (/DSR)
The modem completes dialing, then turns this
while waiting for
the answer
tone and
the carrier.
indicates
three
things
by turning
this
electrically connected to the communication
signal
on:
line;
that
it
hook; and that it is ready to start communication activity.
signal on The modem that it is
is off-
/CI_-> (/SDCD)
After answering
a
signal to
indicate
how
fast
data
terminal,
Turning
the
line
on
transmitted at high speed.
Turning
is being transmitted at low speed.
signal represents the selected rate
call,
the modem generates
is being
transmitted
to
indicates
that
data
is
the line off indicates that
During the originate modes,
of data transfer.
this the
being data
this
[CE _-> (/DCD)
data
signal
begin.
When from
this the
signal is on, communications
&
the modem
line
and
is receiving communications
the can
The modem generates
indicate
the
ringing
activity.
ringing.
Between rings, or when
off.
The
software
detects the
and asserts DTR if the call is to
the voltage levels on this line
to
When the signal is on, the line is
there is no ringing, the
signal
is
ringing activity through the zss30,
be answered.
(/RTSB) -> /RCNTL
The software uses this signal to change
the mode
of data terminal
transfer.
When
this
signal
wants to enter into the command
is on, mode.
it indicates that In command mode,
the the
modem
does
it uses the
not data
transmit the data received on the line BA. for command and status information exchange
Instead, between
the
terminal
and
the modem.
During
initialization
and dialing
procedures, the modem uses the command mode commands and to receive status information.
to send modenm dialing
Once
the data transfer mode is initiated, the command mode cannot be
invoked again unless the line is disconnected.
/ACNTL -> (SYNCA)
The modem generates this signal in response to the
/RCNTL signal from software.
The software does not send any
command
data
on
line
BA
until
this signal is turned on.
When the /RCNTL
signal goes away and the modem enters the data
transfer
mode,
this
signal
is
turned
off.
The /ACNTL signal is usually pulled high on
the RS-232 interface board.
When both /RCNTL and /ACNTL are on,
the
TECHNICAL REFERENCE
HARDWARE OPTIONS
terminal can exchange commands and information with the modem.
The /ACNTL
signal combined with the /RCNTL signal can differentiate
between the modem board and a sync-async comm board.
To check for an
installed modem, the software first activates the RCNTL,
then
waits
for
the modem to return the /ACNTL signal.
If no acknowledge signal
returns, then a sync-async comm board is installed,
rather
than a
modem board.
RX CLOCK -=>
RTXCA
This
asynchronous communication.
is the
receive
data c¢lock
1line for
TX CLOCK ->
TRXCA
This is the
transmit
data clock
line
for
asynchronous communication.
3.4.3 Modem Initialization
At power-up,
the RESET
modem, using the operating
these same defaults at any
signal
on
the system bus initializes the
defaults.
The user can reset the modem to
time with the software reset command.
The default parameters are listed in Table 3-7.
Table 3-7 Modem Default Parameters
-
Parameter
Dialing Line termination Modem transmitter Modem mode Data/command mode Communication
Default
«
Setting
Pulse dial on hook Squelched Originate Data mode
Asynchronous
3.4.4
Command Mode Operation
The modem has two modes of operation, data transfer
(also
called
control)
mode.
The
terminal
communicates with the processor on the modem board,
mode and system either
data
transfer
or
the
command mode.
All data and command
passes through the USART.
command
software
for
the
transfer
At power-up, the default setting is for the data transfer mode.
For
various
reasons,
such as a software request for diagnostic status
information, it is necessary to place the unit in command mode.
The
terminal
and
the modem
are in master-slave configuration, and the
modem cannot initiate the command mode.
TECHNICAL REFERENCE
HARDWARE OPTIONS
To prepare for command mode operation, the Z8530 must be set
up
300-baud
operation,
no parity, 8 bits per character, one stop
for bit,
and ons start bit.
The 2Zilog 8530 Technical Manual contains
on setting the Z8530.
Also, refer to subsection 3.3
Appendix F contains "RCNTL"", a sample subroutine that
of this checks
details manual. for an
installed modem.
Once enter line modem until
the appropriate signals are set, the modem and the terminal can
into a command status transfer dialogue.
The software
asserts
/RCNTL,
requesting
the
modem to enter the command mode.
The
responds by asserting the line /ACNTL.
The software then waits
/ACNTL is turned on by the modem before sending any commands.
To find the status
"send diagnostic
the
first
byte
of the modenm,
the computer
transmits
status" (44H).
The modem returns a 2-byte
indicating
that
the "status byte followsTM
the code response,
and the
second byte giving the status,
The commands and status codes
are
Appendix
F contains
"DIAGST",
a
dialogue in the command mode.
listed sample
later
in
routine
this
section.
for
starting a
After the modem completes a
"command
complete"
(A=41H)
After sending a command, the
command,
expecting
either
command code or computer a
from the computer,
it sends
a "command failed" (Z=SAH) code.
waits
before
sending
another
direct
response
or a command
a
complete/failed status.
The terminal software a command to the modem against possible modem
can insert a fail-safe time-out between
and receiving the command
status
to
malfunction.
issuing protect
After the software
the
/RCNTL
1line.
The system is now
completes the command/status dialogue, The modem responds by releasing the
in the data transfer mode.
it releases /ACNTL line.
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3.4.5
Dialing Procedure
Tdiioninasletbtqrhedeugicnttieo(laniesnpcchlaoluonldne,ingthnteuhemabnmeyerttehrsomTedip(na7ar1loaf3t)o-drt8ir9aa5lns-isy0hmm0gib0to1slXs(,sutchsheuT chatserleasqeT upeho(sortn)se
P).
number -, +,
For tone
and
X
is
the
telephone
number
terminator.
The number
maximum of 23 digits long.
complete""
status,
then
"Dialer"", a sample routine
The
dials for
modem
the dialing
responds
with
the
number.
Appendix
F
a telephone number.
to be or @) and
example, dialing, can be a
"command
contains
3-19
TECHNICAL REFERENCE
HARDWARE OPTIONS
The ( ) and They have
- separators are used for no meaning to the modem.
number-grouping The modem reads
purposes
only.
the + separator
as tandem dialing.
Each time the modem
finds
& +,
it waits
for
another
dial
tone before continuing.
The @ symbol represents blind
dialing.
When the modem finds the @ separator, it waits 2.0 + 0.1
s
after
the command is received, then dials the number without waiting
for a dial tone.
The
dialing
methods
include
tone
dialing,
pulse
dialing,
and
automatic
selection.
The modem is able to alternate dialing methods
during the dialing procedure.
Simply insert the proper characters (T
for tone dialing, P for pulse dialing) in the telephone number.
For
example, in the number
T8-50-33333344-P(713)-895-0001,
the
modem
dials all the digits to P using the tone mode; all digits
after P are dialed using the pulse mode.
The modem echoes the number
back to the terminal (without separators) as
it dials
each
digit,
then
sends status to the terminal for full call-progress monitoring.
The status can be ringing, busy, no answver, or voice.
The
terminal
screen displays the appropriate message.
When
the connection attempt is successful, the modem does not
a status indicator.
Instead, the computer monitors the signal
The modem asserts /DCD, indicating a successful connection.
return /DCD.
The dialing procedure is aborted any time the DTR signal is dropped. The modem sees this as a command to stop dialing, and goes on hook.
The modem waits
through
10 rings
before
reporting
a no-answer
condition.
The default
time
to wait between retries is 11 s, the
default number of retries is 0.
Ten rings as a no-answer
condition
is a fixed number; however, the time to wait between retries and the
number of retries can be programmed into the terminal software.
3.4.6 Time-Outs
Both the terminal and the modem can cauge
time-outs
are:
loss
of
carrier,
long
response.
The two types of modem time-outs
abort timer.
time-outs.
The
terminal
space
received,
and
no
are:
loss of carrier and
Table 3-8 summarizes the time-outs.
TECHNICAL REFERENCE
HARDWARE OPTIONS
Table 3-8
Types and Durations of Disconnects
Terminal
Modem
Type Loss of carrier Long space received No response time-out
Duration 200 ms
1.5 s 1 s
Type Abort timer Loss of carrier
Duration 17 s 50 ms
The following conditions.
paragraphs
give
brief
descriptions
of all
time-out
3.4.6.1
Terminal or Software Time-Outs.
*
Loss of Carrier.
If
safe disconnects vhen
before disconnecting.
the
terminal is programmed for fail-
the carrier goes off, it vaits
S0 ms
*
Long Space command to the /ACNTL
within 1.5
Received.
At
the modem, then
signal.
If the
s, the terminal
start-up,
the
terminal
sends a
waits for the modem
to
turn
on
modem fails to return the signal
disconnects.
¥
*
No Response.
then
waits
disconnects,
The terminal for the modem
sends a response.
command
to the modem,
After 1 s, the terminal
3.4.6.2
HMHodem Time-Outs.
*
LstttootuisarmsynerssrecoofogfhonffoCiflazdrefsrotirheerth.SteOhDeCDmlsoDsuDssrCi(Dignnotgafhle1latihnlteeoetnegmcttphatheorrrrueiaZo.erf8ryS.3t0hH,leooswsecvaetuirosfm,ienrg),cifartrhtiehteehre,socfatrmwrotadihereinersm
*
Abort Timer procedure,
tone. The
status and
- Originate Mode.
the
modem
goes
modem waits 17 s,
goes on hook.
The
During the automatic off hook to listen for
then sends the "command
terminal responds by
dialing the dial
failed"
dropping
DTR.
The
abort
timer
resets
after
the
complete.
If the modem being used is
type, the abort timer is set for Bell
dialing
procedure is
a Bell 212A-compatible
212 high-band carrier.
*
Abort Timer procedure,
- Answer Mode. the answver-tone
BDuring
a
abort timer
manual is used
the dial-tone abort timer.
The originating modem
dialing
instead of
looks
for
3-21
TECHNICAL
A REFEEfiNCB
.
HARDWARE OPTIONS
an answer
from
the remote modem.
The answver depends upon
the type of modem installed in the remote
system.
If the
remote
is
Bell
103-compatible,
the modem
1looks for the
carrier.
If the remote is Bell
212-compatible,
the modem
looks
for
the scrambled mark or the unscrambled mark.
The
modem waits 17 s for the answer tone, then drops DSR.
3.4.7
Modem Software
The modem software is very simple.
Some commands
are only 1 byte
long,
such as the "Manual Disconnect" command.
Field commands, such
as "Telephone Number" (an op code followed by a field), are longer.
The terminal sends a command to
direct
response
or a status
failed).
The terminal does not
handshake is completed.
the modem.
The modem
byte
(command
complete
send additional commands
returns
a
or command
until
this
Table 3-9 lists the software commands from the terminal to the modem.
TECHNICAL REFERENCE
HARDWARE OPTIONg
Table ,3-9
Commands from .the Software to the Modem
B+ HHUICHUIDVDOXIPTQTUMMEBU
ASCII Code A B c
Command
Dial following telephone number, select dialing mode
Next byte contains number of retries (ASCII, 0-9)
Next 2 bytes contain time (in s) between
retries (ASCII, 0-399 s)
Request diagnostic status
Disconnect on loss of carrier
Do not disconnect on loss of carrier
Manual answer
Select 1200- bps option
Select 300~ bps option
What modem type?
Manual originate
Dial following telephone number using pulse dialing
Start RDLB test*
Synchronous communication mode
Dial following telephone number using tone dialing
Asynchronous communication mode
i
Software reset
Telephone number terminator
Start ALB test*x
5
Tandem dialing (wait for another dial tone)
Blind dial (wait 2.0 s, then dial)
i
* The
RDLB
compatible
lines. received
The data
(Remote
Digital
Loopback)
test
is for
a Bell 212-
modem.
It checks the condition
of
the
communication
originating modem makes the answvering modem echo all back to the originating modem.
** The ALB (Analog Loopback) test causes the modem's internal
logic
to connect the transmitter to the receiver and loopback the data.
Table 3-10C lists the possible responses from the modem.
TECHNICAL REFERENCE
HARDHARE OPTIONS
Table 3-10 Response from the Modem to the Software
NSTOZITTHOW»
ASCII Code
Command
Command completed Busy tone Diagnostic status follows Phone number terminator Phone number follows Bell 212A option installed Bell 103 option installed No answver Lost call Ringing from ringback Voice reception Command failed
One
possible
modem
Immediately after the
diagnostic indicators
response
is D, diagnostic
status
modem sends this reply, it
sends
one
from Table 3-11.
follows.
of
the
Byte Value
o0 o1 02 o4 08 i0 20 40 80
Table 3-11
Diagnostic
Heanifig
Good check ROM error RAM error Processor error Timer error Not used Not used Not used Not used
Status
Indicators 4
3.5 GRAPHICS VIDEO CONTROLLER BOARD
The
graphics video controller board operates with the CRT controller
board.
It is mounted
(piggyback
fashion)
on the CRT controller
board,
and all
its connections
are
to the CRT controller board.
Figure 3-5 is a block diagram of the graphics video controller board.
(Refer to Section 6 for logic diagrams.)
TECHNICAL REFERENCE
HARDWARE OPTIONS
ADOcRPEySS.
AEFAESH ADURESS PADCESSOR ADDRESS BUS
S2MTER
a1 8MUx
41 MU
i
[T
RAM ADDRESS BUS
PIXEL ATTRIBUTE A
&1 Mux
41MUX
JL I
PiXEL ATTRIBUTEB PIXEL ATTRIBUTEC
SHIFT REG|--{SHiFT REG | | sHiFT ReG--{ sHiFT REG|
8R1A6xKM
N«B1R6AKM
|
16K aRAM
A
T
16K BRAM
LATEW I
PALETTE DATA IRED!
PALETTE DATA (BLUET
RED PIXEL
BLUE PIXEL GREEN PIXEL
ML81UX
M8u1 x
M8U1X
PALETTE DATA IGREEN? LATCH
CON8T0CRATAO0TRLDLER
T0CPY
HROELADD-LDAATTCAH
ATCH
OATA 8US TICMOLINONTGGIRCOALND
PALETTELATCHES.
2223216-15
Figure 3-5 Graphics Video Controller Board Block Diagram
The graphics video controller board uses the same
number
of pixels
(720
horizontal
X 300 vertical)
on
the
screen
as
does
the
alphanumerics board.
Each pixel
can
contain
a maximum
of
three
attribute
Dbits
(labeled
A,
B, and C). These attribute bits are
converted by a palette look-up table to three colors - red, blue, and
green.
Aspects section
of the graphics include:
video
controller
Dboard described
in this
TECHNICAL REFERENCE
HARDWHARE OPTIONS
* Pixel addressing * Color selection * Timing and synchronization. * Graphics logic array program
3.5.1
Pixel Addressing
Each dot
on the graphics screen is a pixel.
Each pixel has a 3-bit
value associated with it that selects one of eight palettes (0 - 7).
Each palette
is assigned one of eight colors, as determined by the
contents of the latch.
The latch is simply an array of eight
3-bit
values.
The
palette
number
of
each
pixel is an index into that
array.
So, the color of a pixel is the color
value
of
the latch
entry
that corresponds to the palette number of the pixel.
Changing
either the palette or the color assigned to the palette
changes
the
color
of
that
pixel.
Changing
the color
assigned to a palette
changes the color of every pixel with the same palette number.
A plane is a block of memory containing 1 bit for each pixel
in
the
disgsplay.
Each
of
the 3 bits assigned to a pixel is in a different
plane.
All three planes are formatted identically; only the
segment
address
differs
from plane to plane.
The segment addresses of the
three planes are C000,
800,
and
DO0OO.
For example,
it a Dbit
assigned
to pixel
(x, y)
is
the
fifth
bit
of.memory location
C000:mmmm, then the other two bits assigned to
that
pixel
are
the
fifth bits of locations C8CO:mmmm and DOOOC:mmmm.
-
In
the following explanation, memory addresses refer to offsets into
the segment of any of the three graphics planes.
The diagram below
shows the organization of graphics screen memory into pixels,.
Pixels
are numbered (x coordinate, y coordinate) and are zero relative.
Byte Address
0000-00SB 005C-0087
{ Pixels Represented
{(8,0) |(8,1)
- (15,08)}(0,0) - (15,1)j(0,1)
- (7,0)](24,0) - (31,0)}(16,0) - (7,3)}. . . . .
- (23,0)
Pixel (0,0) is the MSB of location 0001. The LSB of location 0001 is pixel (7,0). Pixel (9,0) is the MSB of location 0000. The LSB of location 0000 is pixel (15,0). Pixel (16,0) is the MSB of location 0003.
The bytes are flip-flopped in this way so that if a move instruction ic executed from a word in the graphics plane to a word: register, the
TECHNICAL REFERENCE
HARDWARE OPTIONS
register then contains 16 consecutive pixel bits in order from MSB to
LSB.
For example, if a MOV AX,
ES:0000
is executed
(where
ES
contains
the segment address of the desired graphics plane), the MSB
of AX is pixel (0,0) and the LSB is pixel (15,0).
With this
scheme,
4S5 words are necessary to represent the 720 pixels in each row of the
display.
There is one unused word at the end of each line, so a new
row begins every 46 words, or 82 bytes.
Line
one
(zero-relative)
begins
at byte address 92 decimal, O00SCH.
Therefore, pixel (0,1) is
the MSB of location 0O0SDH and pixel (8,1)
is the MSB
of 1location
OOSCH (because the bytes are flip-flopped).
Example:
To
find
the values of the rightmost 16 pixels on the bottom line of
the display,
299 (zero-relative number of last line on display)
X
92 (bytes per line)
+
88 (first word = 0, second word = 2, so 45th word = 88)
= 27596 (6BCC hex)
So, MOV AX, ES:6BCC puts the values of the
last
16 pixels
on
the
display corner.
in AX, with the LSB of AX being the pixel in the lower right
The three graphics planes
are
named
A,
addresses
of
the planes
A,
B,
and C
recpectively.
In determining the palette
from the C plane is the most significant,
the least significant, and the B plane bit
B, and C.
The
are C000, 800,
number of a pixel,
the b{t from the A
is in the middle.
segment and DOOO,
the bit plane is
Example:
To find display,
the first
color
of
the
pixel in the lower right
find the palette number assigned to it.
corner
of
the
The MSB of the palette number is the LSB of D00O:6BCC; the middle bit of the palette number is the LSB of 800:6BCC; the LSB of the palette number is the LSB of C000:6BCC
Say,
for
example,
respectively.
Then
color is assigned to
in effect, the color
that
these
the
color
palette 5.
of the pixel
three
bits
are
1,
o,
and
198
of the lower right pixel is whatever
If the default color assignments are
is cyan.
3.5.2
Color Selection
Each of the eight entries in the
three
primary
colors:
green,
colors are formed by combinations
Table 3-12.
latch has red, and of those
one bit for
each
of
the
blue.
The eight available
three colors, as listed in
TECHNICAL REFERENCE
HARDWARE OPTIONS
Table 3-12 Color Combinations
Green
Red
Blue
Color
Color
i
o
o
o
black
c
o
0
1
blue
1
0
1
0
red
2
o
1
1
magenta
3
i
o
0
green
4
1
o
1
cyan
s
1
1
o
yellow
6
1
1
1
white
7
To access the latch, you must write all eight bits
of a particular
primary color to the appropriate memory location for that color.
You
cannot change all three bits corresponding to one palette number in a
single
write.
The latch consists of three memory locations, one for
each of the primary colors.
These locations are:
Blue latch Green latch
Red latch
DF00:0010 DF00:0020
DF00:0030
-
You can write to these locations, but you cannot read from them.
For
this reason, it is necessary to maintain a memory image of the
three
color
latches ifindividual palettes are to be changed.
You are then
able to change a single palette by setting the
appropriate
bits
in
the memory
image
to the desired value and updating all three color
latches.
Each of the three color bits of a palette is in the same bit position
in all which
three color latches.
However,
bit
in
the latch is addressed
the
scheme
for
by a pixel is not
determining the same as
that for determining the palette number.
In determining
the latch
bit addressed by the three-bit value assigned value is the most significant and the C plane
to a pixel, value is in
the the
B plane middle.
The and the
A plane value bit 0 is the LSB
correspondence
is still of the between
the color
the
least significant.
Bit 7 is the MSB
latch byte.
Table
3-13
displays
bits assigned to a pixel and the bit
positions in any of the three color latches, and shows the comparison
of these bit positions to the palette numbers.
TECHNICAL REFERENCE Table 3-13 Bit Correlations
HARDWARE OPTIONS
B Plane Bit
c o 0 0
1
1 1 1
Plane Bit
o o 1 1
o
o 1 1
A Plane Bit
o 1 o 1
o
1 o 1
Latch 8it Addressed
C 1 2 3
4
S 6 7
Palette Number
o 1 4 S
2
3 3 7
Figure 3-6 shows this correspondence horizontally, latch byte appears as a byte register.
so that the
color
8 plane bit C plane bit
A plane bit
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
"
0
Latch bit addressed
7,
6
5
4
3
2
1
0
Palette number
7
6
5
4
3
2
Figure 3-6 Color Latch Byte
1
0
222321618
Example
This example of the three
shows color
how to create latches.
a memory
image
of
the default
values
Combining information from Table 3-12 with information from Table 3-13 (thé the information necessary to construct
(the Color Combinations Bit Correlations table),
Table 3-14.
table), yields
TECHNICAL REFERENCE
HARDWARE OPTIONS
Table 3-~14 Default Values of Color Latches
Latch
Palette Number
Green
Red
Bit
(= Color Number)
Bit
Bit
7
7 (white)
6
6 {(yellow)
S
3 (magenta)
4
2 (red)
3
S (cyan)
2
4 (green)
1
1 (blue)
0
0 (black)
1
k9
1
1
0
1
0o
1
1
1]
1
[
o
o
0
o
Blue Bit
1 0 £ 0 1 o 1 o
The
default
condition
is palette number = color number;
the color latches are set as follows:
therefore,
Green latch = 11001100 binary = CC hexadecimal at DF00:0020 Red latch = 1111000 binary = FO hexadecimal at DF00:0030 Blue latch = 10101010 binary = AA hexadecimal at DF00:00l10
Example: #
This example lists the s;eps necessary to <change palette
three
to
yellow from the default condition (magenta).
TM~
1. Find find
the desired palette number (three) the associated latch bit (five).
in Table
3-14,
then
2. Find the desired color (yellow) in Table
3-14,
the bit settings (red = 1, green = 1, blue = 0).
then
find
3. Set bit five in each of the color
latches
to the values
determined
in the previous step.
This change creates the
new values:
Green latch = 11101100 binary = EC hexadecimal Red latch = 11110000 binary = FO hexadecimal Blue latch = 10001010 binary = 8A hexadecimal.
4, Write the new values (from the previous step) to the
three
color
latch addresses.
{In- this
example,
it is not
necessary to change the red latch, because
the value
did
not change.)
TECHNICAL REFERENCE
HARDWARE OPTIONS
3.5.3
Timing and Synchronization
The
same `at
clock
that
generates
internal
timing
for the CRT
controller
©board <clocks
the graphics
video
controller
board.
Monitoring
the
display
enable
(DE) signal from the CRT controller
board helps to synchronize the pixel outputs from the two boards.
If
the DE signal has been low for a long period,
the
graphics
board
assumes that the scan is in the vertical interval. When DE goes high
again, the graphics board resets the graphic memory and scan counters
to zero.
When DE is low for a short period (horizontal retrace, for
example), the scan counters are stopped.
This places the last
pixel
on a line adjacent to the first pixel on the following line.
The
graphics
video
controller board gives the CPU essentially free
access to the screen memory.
During a single screen
display
cycle,
the hardware can access the refresh memory twice -- once to read the
data for screen display, and once for the CPU to read or write data
if needed.
To provide enough time for this access, a display cycle
accesses 16 adjacent pixels of 3 attribute bits each.
These are read
in parallel and loaded into three 16-bit shift registers for display.
After the memory has been read for screen display,
the CPU access
cycle
starts
when a read or write cycle is requested.
The accessed
memory is broken up into
one
of six
separate
bytes
by properly
decoding memory.
the enabling of bus buffers and write enable signals to the
Dynamic memory is used on the graphics video
board
because
of
the
large amount of memory required.
The memory chips are organized into
16k x 4 bits and are packaged in an 18-pin, dual inline package
(DIP).
The 8 address lines are multiplexed into
256 row addresses
and
64
column addresses to get to the 16 K locations in the memory.
The addresses to the RAM also need to be multiplexed between the
CPU
and
the refresh counter.
Performing this four-way multiplexing are
four 74LS153 dual 4-to-~1 multiplexers (U33 through U36).
Figure 3-7 is a timing diagram
for
the graphics
video
controller
board.
A 74LS163
4-bit counter (U39) and a HAL16RBA-1 logic array
(U41) generate the timing.
A 74LS163 counter connected as a one-shot
(U40), a 75LS00 gate (U44), and a 74LS04 gate (U45) provide the stop,
start, and reset logic for the refresh counter.
HARDWARE OPTIONS
Figure 3-7 Graphics Video Controller Timing Diagram 32
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TECHNICAL REFERENCE
HARDWARE OPTIONS
3.5.4 Graphics Logic Array Program
Programming for the logic array is given in Table 3-15.
Table 3-15
Programming for the Graphics State Machine HAL Input
RD~
X1
LATEN-
BUFEN-
Ooutput
WR-
GSELDE
X2
ROWGRCLK
LATOE-
SRLD-
RAS-
GHAIT-
CAS-
DED-
------- et b b et m bt m bbb b=t
b m
LATEN- L . L . . . HL
or
g 15150 o oo B
L
T
R
or
. LL
TR
L
- L -
or L L .
R
% 0.0 D @ o W o
-------------- P
bmb b m e bt m b b m bt m bbb
LATOE- L . L
HHHL
T L
R
CF
holh'8
48 8 o
O N LS LR
N
&M s plb & d slo o b g'vewo
------- Poebmbmb et
mb et bbb m b=
RAS -~
. . LHLH
VIR
or
R LBLIE SN R
Y N L
or 'L,
¢L
L HLL
o
L
HES
R
or
. .
or
TRIECR
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DRI Rl
%o 0o O 0
or
NI
L HiH
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R
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da.
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b m bbb m bb bb bb ==
U TR
H
B8
s o lF o9
or
85 6 8.0 o3 B
ERRE L
T
------- otttk m bbb m b
BUFEN T N TSI A
v
b -- bbb==
o 2 D o 4ot
Or
NLBLOE
MHSLSLR L
O R
eL I
or
L LR
e |
oo oy o dBeo
OR L L
- I
-
-
G- il
------- Por bbb b et bbbt
SRLD- . . . LHHH
e R
IL- AR
O N LN L
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T
------- ot b m btt -- t b m bbb
--r =
CHA'IT NI RTINS
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or
o 5% d b 6 b w
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Fobb m bb bm m bbb b m -- b -- b b =
5 5 00l b
e
Y
]
-
PR
Li'e o.g o
Tl
-------------- Pttt
Legend:
m bb b b b bb --r ==
L = Low signal.
H = High signal.
Comment
Read S85,6,7,8 Hrite S3 Hrite S4 till All other ORs
not write inactive
Read s8 Read S9 till not read All other ORs inactive
Refresh screen Sil1
Write sS3
Read
S3
CPU sS4, :refresh s12
CPU 85,6, refresh .S13,14
CPU S7, refresh s15
(Inactive term)
$13,14,15,0,5,6,7,8 All other ORs.
Read $4,5,6,7,8 Write s2 Write 83,4,5,6,7,8 All other ORs inactive
S1is All other ORs inactive
Delayed DE All other ORs.
TECHNICAL REFERENCE
HARDHARE OPTIONS
When the logical the AND of terms result is true.
AND of terms from another
from row,
one row of Table 3-15 is ORed
the
output
goes
low
when
with the
3.6 WINCHESTER DISK DRIVE AND CONTROLLER OPTION
The
Winchester
disk drive and controller board option consists of a
controller board,
cable
and
hardware,
and a S- or 10-megabyte
Hinchester
drive.
Aspects of this option described in the followving
paragraphs include:
* HWinchester hardvare theory of operations * Register assignments * Bit definitions for registers and ports * Controller status bit combinations * Normal command sequence operation
3.6.1
Winchester Hardware Theory of Operation
4
The Winchester controller is addressed by the 8088 as a block of four
I1/0 ports:
0030H through O0033H.
1/0 reads are indicated by the bus
signal IORC, and I/O writes are indicated by the bus signal AIOWC-.
The controller can generate an interrupt following conditions:
to the host under one of the
* When
data
controller
is ready
to be
read
from
or written to the
* When the operation
is completed,
and
the
controller
is
requesting a status read (C/D- = 1, [/0 = 1)
Both
of the interrupt conditions can be individually disabled.
the interrupt is active, the computer's interrupt line 6 is held
until it is cleared by a read to the controller status register.
When high
3.6.1.1
On-Board EPROM/ROM.
A 4K x
8-bit
EPROM/ROM
driver
routines
for
the controller. Addressing this
the output to drive the data bus
through
a tristate
EPROM/ROM
is at memory address OFB8O0O00H.
Access time
EPROM or the ROM is less than 350 ns.
contains
the
device causes
Dbuffer.
The
to either the
TECHNICAL REFERENCE
HARDWARE OPTIONS
3.6.1.2
Commands and Command Testing.
block
to the'controller to specify the
device control block (DCB). the DCB.
Table 3-16
The computer sends
a 6-byte
operation.
This block is the
gives the bit definition
for
hi
Table 3-16 Device Control Block Bit Diagram
B
Yrm----m-------- SEESS +~B I T
N UMBER --+-~nw-u-o S
S
+*
t}
7
§
6
{
S
{
4
|
3
|
2
|
1
|
0
Q-g0-=======0=======¢=======¢=======4-=======0=======¢=======0=======0
|0] COMMAND CLASS |
OP CODE
|
e ------------
e =
- ----- e ----------- P ------------- O
------
- *m---------- b ------ - +*
j1}
LOGICAL UNIT NUMBER
I
b mmm----- Fmm--m------
- -------- P m -
HIGH
ADDRESS
( See Note 1 ) |
b
---- o
---- tmmem---- e
------ +
{24
MIDDLE ADDRESS
( See Note 1 ) |
R
13}
F------------ o --m----------
------------ b m-------------- P m----------
LOW ADDRESS
-
- -------- +*
( See Note 1 ) |
et mm
e -- - e --------- o -------- o m--------
-
R
e
- ---- o ---------- +
jai
INTERLEAVE OR NUMBER OF BLOCKS
( See Note 2 ) |
P
- -
= -
e ------- P ------------ -
- e
-------- -------------- P -------------- *
|s| b e m-------
CONTROL
FIELD
bmm------
e = o -------- e
-
e
------ P
| m-------- +*
Notes:
1. Refer to paragraph 3.6.1.6. 2. Interleave factor for FORMAT,
CHECK TRACK,
and READ
ID commands.
-
3.6.1.3 bytes that
Explanation
of Bytes
in the Device Control
comprise the device control block are defined
Block.
The
as follows:
§
Byte
Definition
o
Bits 7, 6, and 5 identify the class of the command. Bits
4 through 0 contain the opcode of the command.
1
Bits 7, 6, and S identify the logical unit number (LUN).
Bits 4 through O contain logical disk address 2.
2
Bits 7 through 0 contain logical disk address 1.
3
Bits 7 through 0 contain logical disk address 0.
4
Bits 7 through 0 specify the interleave or block count.
5
Bits 7 through O contain the control field.
TECHNICAL REFERENCE
'
HARDHARE OPTIOKNS
3.6.1.4
Control Field Detailed Description.
Byte
S5,
the
field
of
the DCB,
allows
the user to choose options for
different types and makes of
disk
drives.
The following
defines
the Dbits of the control byte.
The step options are
in control byte S of the command descriptor.
The
encoding
with bits 0 through 3 as given in Table 3-17.
control several listing encoded is done
Table 3-17 Command Descriptor Byte
Description
Default 3-ms step rate
Seagate STS06 (MLC2)
Tandon fast-step Texas Instruments fast-step 200-us buffered-step 70-us buffered-step 30-us buffered-step 15~-us buffered-step Olivetti 2 ms/step (561) Olivetti (S62) fast-step
(1.1 ms typical) Spare (for future use)
Bit No.
3
2
1
0
o
o
o
o
o
o
o
1
o
o
1
o
o
o
i
1
0o
1
o
o
0
1
0
1
0
1
1
o
o
1
1
1
1
o
o
o
1
o
o
1
1
1
1
1
4
To configure
a drive
for fast-step or buftered-step; refer to the
manufacturer'''s manual for instructions.
If the drive
is hardware-
configured
for fast-step,
all
commands
requiring the seek option
selection must use the fast-step option for that drive.
NOTE
The step option bits
exclusive.
Select
configuration.
(3 through 0) are
only
one
option
mutually for any
Bits 4 and S are reserved for future use.
Set bit 6 to O for regular operation.
When this
bit
is
set
to
during
a read sector command, any failing sectors are not reread on
the next revolution.
Set bit 7 to 0 for regular operation.
`Setting this bit to 1 disables
the four retries by the controller on all disk-access commands.
Set
bit 7 to 1 only during the performance evaluation of a disk drive,.
B.E`-CHNeICAL REFER".E. NCE
HARDHARE OPTIONS
3.6.1.5
Command
Completion .Status Byte.
the controller feturns a completion
status
This
Dbyte
indicates
whether
or not
an
command execution.
(If the error bit is set,
wvhat
caused
command.)
the
error,
you must
send
At byte error
and the
the end of a command,
to
the
computer.
has occurred during
you
want., to know
REQUEST SENSE STATUS
The format of the completion status byte is
1/0
Port
(MSB)
b
7
6 |
'0::
T+===S
e
Bit Number
(LsB)
|
4 |
3}
2 | 1]
e |
R TR R4S SR ST+ S S S S S 4SS SIS eSS SIS
Address||Don't
0030
J|care
(read) ||
{Don't |care
{
|Dri |No.
j
|pon't {Don't |Don't {(Error|Don't |
jcare
|care
|care
| bit jcare
{
|
i
|
§
1
|
I§======§======0======0======0======0====:=0=====0======0'
3.6.1.6
Logical Address
of the drive is computed
(HIGH, MIDDLE and LOK).
The logical
by using the following equation:
address
Logical Address = (CYADR x HDCYL « HDADR) x SETRK + SEADR
Where:
CYADR HDCYL HDADR SETRK SEADR
= Cylinder address = Number of heads per = Head address
cylinder
= Number of sectors per track
= Sector address
3
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TECHNICAL REFERENCE
HARDWARE OPTIONS
3.6.2 Register Assignments
The
register
assignments
for ¢t he
controller are given in Table 3-18.
1/0 ports
of D the
Hinchester
Table 3-18
HWinchester Controller 1/0 Port Assignment
P
-------- P
e
e
i
Address
}
+
Pt
m
e e
dd e e mm e m e -- e --mm------m o +
Functions
|
---------------- P
rrc et --
e, e ---- = +
|
}
|
|
P m-------------------- e
In
r e ---- e, e
|
|
-- -
out
{
|
e e,
m e e e c---- .- +
|
0030H
f
Data IN port
}
Data OUT port
|
e m e~ - R
R
et
e e
e ------, ---- - - *
|
0031H
{
Status register
{
RESET
o
m-- e ---- e -- e
r e
--r e, r e -------- e mr et _--r----
e -------------- +
|
0032H
§
Not used
|
Not usead
|
mr v, -- - -- P e, r e e ------,-------- e e
m e, ------, - -------- +
|
0033H
|
Kot used
§ Interrupt mask
{
et
e
mme
et
e, e, e,
------ +
An
IN function
gets
data from the Winchester controller board and
puts it on the compute r's 1/0
expansion
bus.
Conversely,
an ouT
function
sets
data from
the computer's /0 expansion bus onto the
Hinchester disk contro ller board.
~
For byte definitions of the registers, refer to the
1I1/0 memory
map
given in Table 2-1.
For pin-outs
of the
Electrical Interface.
Hinchester
cable, refer to paragraph 3.6. 20,
TECHNICAL REFERENCE
i
HARDWARE OPTIONS
3.6.2.1
Data Input Port.: Disk read data and controller sense
Dbytes
. pass
through
this
register
to the computer.
The data is held for
each handshake cycle.
The format is as follows:
1/0
Port
(MSB)
Bit Number
(LsB)
Il
7 1
6 |
s |
4 |
3 |
2 | 1|
c |
|¢======0======o======0======¢======0======¢======¢======b
Address||
i
!
1
i
|
|
|
|
0030
J IDATA 7|DATA 6|{DATA S|DATA 4|DATA 3|DATA 2|DATA 1|DATA 0}
H
I
]
J
|
|
1
|
|
l0======#======0======0======0======§======*======#======0
3.6.2.2
Data Output Port.
Command
this
register
to the controller.
the CPU.
The bit arrangement is as
bytes and disk data pass
through
Data is latched until updated by
follows:
MSB
BIT NUMBER
LSB
1/0
Port
i1
7 |
6 |
5 |
4 |
3 |
2 |
1
0 i
'¢======¢======0======0======§======o======0======¢ Zz===+
Address||
]
)
}
|
]
|
|
i
0030 ||DATA 7|DATA 6|DATA S|DATA 4|DATA 3|DATA 2|DATA 1|DATA O}
(write) |
1
f
|
|
}
|
i
l#======Q======0======0======0======0======0======#======0~
3.6.2.3
Controller
Status
Register.
controller
status.
It enables the CPU
and to monitor the controller operation.
is defined as follows:
This
register
stores
the
to read the controller status
The controller status
byte
MSB
BIT NUMBER
LSB
1/0
Port
1l
7 |
|+===a==+
6 |
s | 4!
=
3 |
2 |
=
1
f
=
o |
Address||Don't
0031
|J|care
(read) |}
|Don't |care
|
|Don't |jcare
}
|Don't IDon't
|care
|care
|
|
| COMMAND| INPUT/| DATA
|
|/DATA
|OUTPUT{REQUEST)
|
|
|
|
"======Q-======§======0======0======O=======0======#=======0~
3.6.2.4
Reset Port.
This byte resets the controller.
Any write to
port 0031 causes a reset.
Reset clears each error status, aborts all
operations, and places
the Winchester
controller
in the command
receive mode.
The byte definition follows:
1/0
Port
MSB
BIT NUMBER
LSB
i
7 |
s |
s |
AP
3 |
2| 1
o
l¢======¢======0======0======¢======0======0=====#======+
Address||{Don''t |Don't |Don't |Don't |Don''t |Bon't {Don't|Don't |
0031
|jcare
|care
|care
|care
|care
|care
|care |care
|
(write)||
)
i
}
!
§
!
|
|
l*======5======`======#======0======0======0====="======Q
TECHNICAL REFERENCE
HARDHARE OPTIONS
3.6.2.5
Interrupt Mask.
interrupts
are
to be
definition follows:
This is a serviced by
2-bit field that determines which
the CPU.
The interrupt mask byte
MSB8
BIT NUMBER
LsB
1/0
Port
b
ZH
s |
s |
4 |
3 |
2 |
1
o
|
'¢======0======0~======¢==:===4-======0======¢======¢=======9
Address|}Don't |Don't |Don''t |Don't {Don't {Don't |DATA
|STATUS |
0033
|}|care
Hi
|care
§
jcare
|
|care
}
|care
|
|care
§
{INTR. |JINTR.
}
JENA|BELNAE BLE |
"0-======§======#======§======Q======§======0-======Q=======&
3.6.2.6
Error Status Byte.
This
special
byte
1is available
only
after
the
completion of a command.
The controller sets the I/0 and
C/D bits with DRQ
to indicate
that
this
byte
is available.
A
definition of the error status byte follows:
MSB
BIT NUMBER
LSB
1/0
N
7
Port
i
6| s|
zez====2=
Address||Don't |Don't |Drive |Don't |Don't
0030
||care
|care
|No.
jcare
|Jcare
(read) ||
§
|
|
|
l0======0======§======`======#======#======#=====#======Q`
3.6.3
Bit Definitions for Registers and Ports
Table
3-19
gives
the definitions
controller registers and ports.
of bits
-
for
the
Winchester
TECHNICAL RE FERENCE
.
b H}RDHARE OPTIONS
.
i
» Teble 3-1 8 Bit Definitions for Controller Registers and Ports
{DATA 0-7 { READ or
| WRITE || DARTEAQUEST
| INPUT/ | OUTPUT| COMMAND/ | DATA| I ] |
§
Logical sState
|
Pt
M
e e e e m e e m e e mcc e e cccmmrm----mm---- - = +
| Data true ; data high ;
| Data false ; data low
§
| logical one »= 2.4 V
] logical zero <= 0.7 V
§============================*============================é
|
}
bata bit = 1
|
i
i
Data bit = ©
§
|
R
R
e
e kR
1
P R
R
|
e
+*
| Commands, status, or data
| No command, status, or
}
| ready to be transferred
| data transfers to or from
|
| to or from controller.
| controller.
R
Y et
] P
m et e e c et e --cr e -- e m e - +
| The CPU reads data or
| The CPU writes data or
| status from the controller.| commands to the controller.|
e
| When
R
R
INPUT/OUTPUT-
is
]
high,|
e
When
e, e St e
mr-------- .. - ------ -
INPUT/OUTPUT- is high,|
| status
PR
R
is sent to the CPU. | data is sent to the
KR KRR KKK KRR KRIRRRKK | kAR AR KKK KRR KRR AR
CPU.
]
RRRRAR |
When INPUT/OUTPUT- is low, | When INPUT/OUTPUT~ is low, |
commands are sent to the
| data is sent to the
controller.
{ controller.
¢ -
| Controller interrupts the
|
|| STATUS
| CPU after the CPU completes| | the current command and is |
.
| | |
| INTERRUPT { ready to return the status
No status interrupt
|
| ENABLE
| byte.
permitted.
i
||| DIAENTNTAAEBRLREUPT
| | |
Controller interrupts the CPU when data needs to be read from or written to
| | | No data interrupt
| |
i
§
| the controller.
| permitted.
i
TECHNICAL REFERENCE
HARDHARE OPTIONS
3.6:2
g #
CSntroller'status Bit Combinations
Table 3-20 gives all valid controller status bit combinations.
Table 3-20
Valid Bit Combinations for Controller Status
____________________________________________________________________ o
{ COMMA|NINDPU/T/ | DATA
i
{ DATA
| OUTPUT|REQUEST||
Meaning of Pattern
|
Q-========§=======Q======="Q============================:============0
j
|
|
1
i
0
}
o
f
0
|
}
}
Not valid
§ !
0========§=======0=======Q{-::======================================='
§
|
{
{§{ A data byte may be sent from the CPU
|
o
{
0
§
1
|| to the Winchester controller. The
|
|
§
§
{{ controller waits for data to be written.}
0========#=======#=======#Q=========================================f
!
i
]
i
0
{
1
i
o
|
|
i
Not valid
|
§
J
§========0=======4:======00========================================='
§
j
|
{{ A data byte may be sentfto the CPU
{
0
}
1 ¢
1
{| from the Winchester controller. The
|
{
}
|
|{ controller waits until data is read.
|
§
i
|{
Command bytes may be sent to the
|
1
|
o
|
1
| Winchester controller from the CPU.
|
|
)
|
i
§
|
0========#=======#=======00=========================================1-
}
|
|
1
§
1
{
1
{
0
Naot valid
|
{
|
|
|
i
}
¢========Q-=======§=======§0=========================================Q~
|
§
§
|}
A status byte may be sent from the
|
i
1
|
1
|
1
j1
Winchester controller to the CPU.
{
i
|
f
i
|
0========0=======0=======0¢=========================================Q
TECHNICAL REFERENCE
2 6.5 Normal Command
Sequence
Figure 3~B8 depicts the logical
C o)
Operation flow of the
HARDWARE OPTIONS
controller
J
functions
--_-- WAIT1
RESET THE WINCHESTER
CONTROLLER WRITE TO PORT 31
READ STATUS PORT 0031
WRITE OR READ CONTROLLER DATA
{READ/WRITE TO PORT - 0030)
1S RAECQTUIEVSE T
OUTCPOU(PBNOTWYTRRTTRIECOTSOLE00TLMT3OE0MO)RAND
WAIT1
READ STAT us FROM PORT 0030
HAFRADUWLATRE
ANOCCDEIURDRR?OR
WISk
DO REQUEST STATUSANCDOMMAND
DECODE ERROR END
Figure 3-8 Controller Operational Flowchart
2223216-20
TECHNICAF REFERENCE
" HARDHARE OPTIONS
3.6.6
Detailed Descrifiiibn of Commands
The commands fall into eight classes -- 0 through
classes O and 7 are used.
Classes i through 6 are
commands
are
data, non-data transfer, and status
commands perform diagnostics.
7; however,
only
reserved. commands.
Class O Class 7
Each command description are shown as
is described in the following includes class, opcode, and "unused."
paragraphs.
The command
format.
"Don't care" bits
3.6.6.1
TEST DRIVE READY Command.
This command selects a particular
drive and verifies that the drive is ready.
The
following
diagram
shows the format of the device control block for this command:
B
Y R
e| 7
e et
6 |
Bit Number--------ec~-eecmcccceca +
S | 4 | 3 |2
b1
| o
|
O'-V-O======0======0======Q======0======0======0======0======0
| o
o
Pomm e
|
o |o
] o
I o
] o
I o
I o
- -------- m----------m m---------- tm---------- ----------- m-------- m---------- +
IRl
o
0 | DRIVE|unused|unusedjunusedfunused|unused]|
e mm---------- m--mm------ mmm------ m------------ e ---------- m---------- e ------ rm-------- +
| 2 junusedfunused|unusedjunusedjunusedjunusedjunused|/unused]j
tmmmb mm----= tm---------- ------------ b
e
=
pmm----- e -------- +*
| 3 |unusedfunused|unused|unusedjunusedfunused|unused|unused|
P
-
om - tmm-------- $------------ -
b
rm---------- +
| 4 junusedfunused|unusedfunused|unusedjunused|unusediunused]j
b mm b ---------- b ---------- -
mm-------- ------------ m------------ -
o -------- +
{ § |unused|unusedjunused|{unusedjunusedfunusedjunusedfunused|
mmmb--m---- == tmm-------- rm---- -
-
r------------ m------------
- R
+
To determine
that
a drive has completed seeking before issuing the
next command, use the TEST DRIVE READY command with overlapped seeks.
(Refer to the paragraph entitled "SEEK Command" in this section.)
If
the drive is still seeking, the end-of-command status byte
indicates
an error, and the sense status indicates "drive still seeking."
This
is a type
O error,
code 8. Sequential TEST DRIVE READY commands
determine when the drive is ready to accept another command.
TECHNICAL REFERENCE
HARDWARE OPTIONS
3.6.8.2
RECALIBRATE
read/write
(R/W) arm
are as follows:-
DRIVE Mommand.
at tratk 000.
Bit
This
command
'pléces
the
definitions for this command
YB b
e
e BIT NUMBER=------c-coeooomoceoo .
t
7 |} Bit 6| Bit 5| Bit 4| Bit 3| Bit 2| Bit 1] Bit o
Q--e--0-======Q======0======0======0======0======Q======Q=====30
o |
o |
o
Pmm--pm--m------ P
| o
i o
o --.------- R
| o
i o
i o
i1
§
Pmm-------- o --------- b -------- o -------- +
f 1|
o |
0 | DRIVE|unusedjunused|unused|unusedjunused]
b
= Fmm---------- tm--mmeaa m--------a o ---- e tmmw----e temmee
o +
} 2 |unusedfunusedfunusedjunusedjunusedfunusedfunused|unused]
boemmmm-- L
rmm--mae b
D
Fmmm-------- t--------ea Pm---------- +*
} 3 lunusedjunusedfunused|unusedjunusedjunusedjunusedjunused]
e
m e
tm----e--e bm---------- e
m---- - tm------ - t---------- o ---- - +
| 4 |unused|unused|unusedjunused|unusedjunusedjunusedjunused}
tm--m e m e
| 5 |RETRY?{
o
tmmm mmm rem-------- L
m-------- - rm------------ +
|
o |
0 [STEP 3|STEP 2|STEP 1|STEP 0}
e~
Pm--------- e ---------- mrmmm--- P ------- P ------ - Pmcmm----
o m--- +*
3.6.6.3 command returns these follow.
REQUEST SENSE
STATUS
Command.
The computer
sends. this
immediately
after it detects an error.
The controller then
4 bytes of drive and the controller status.
The formats
for
4 Dbytes
are shown after the DCB.
Definitions of these bytes
B
<
Y 4o t
7
mmm e | Bit
6]
Bit
S|
BIT Bit
4}NUMBBitER-3~|~--B-it---2-|=
e Bit 1]
Bit
. 0}
0--e--0======0'======#==`====0======'======0~======Q======`======Q
] o|
o |
e ------
o |o
] o
i o
| o
I 1
o1
i
- - rm---------- o m------ m--mmm- m------------ rm-------- rm---------- +
f 1
o |
0 | DRIVE|unusediunusedjunusedjunused|unused|
R
e
- tmm-------- P ------ Fmmm - ---------- o -------- P
*
| 2 junusedjunusedjunused|unusedfunused|unused|unused|unusedj
e m b m---------- bm---------- tmm-------- o -------- mm-------- tm------------ e
------ m---------- +
f 3 junused|unusedfunused|unusedjunused|unused|unused|unused]|
tmmmb e ------ Fm---------- o ------ tmmmmme remm-- o m-------- o -- torm-------- +
| 4 {unused|unusedjunusedjunused|unused|unused|unused|unusedj}
Pm b
m- o
b
b
Pmmm------ tmm-- - ------------ o
---- +*
| S |lunused|unusedjunused{unusedfunused|unused|junused|unused]|
R
e
tom e --m---- Fmmme- Pmm-------- e -------- tmmm------ tmmmm- +
Bit 7, the address valid bit in the error code byte, is relevant only
vhen the previous command required a logical block address.
In this
case,
it is always returned as a 1; otherwise, it is set to 0. For
instance, assume that a RECALIBRATE command is followed
immediately
by
a REQUEST
SENSE STATUS command.
The address valid bit could be
returned as 0 because the command does not require
a 1logical
block
address to be passed in its DCB.
TECHNICAL REFERENCE
HARDHWARE OPTIONS
The format for the sense bytes returned is as follows:
B
yty
7 | e § S | 4 § 3 § 2 { 1+ 4 o
e
o
NOTE: Refer to paragraph 3.6.1.6.
Hhen
an error
occurs
on a multiple-sector data transfer (read or
write), the REQUEST SENSE STATUS command returns the logical
address
of
the failing
sector
in bytes 1, 2, and 3.
If the REQUEST SENSE
STATUS command is issued after any of
the
format
commands
or
the
CHECK TRACK
FORMAT command,
and
if no error exists, the logical
address returned by the controller points to one
sector
beyond ' the
last track formatted or checked.
If an error does exist, the logical
address
returned points to the track in error.
Table 3-21i, Table 3-
22, and Table 3-23 list the types 0, 1, 2, and 3 error codes.
Table
3-24
summarizes the error codes returned by the REQUEST SENSE STATUS
command.
"
<
Code OH 1H 2H 3H 4H SH 6H
Table 3-21
Type O Error Codes, Hinchester Disk
Definition
The controller detected no error of the previous operation.
during
the execution
The controller did not detect an index signral from the drive.
The controller did the drive after
not get a SEEK COMPLETE seek operation.
signal
from
The controller detected last operation.
a write
fault
from drive
during
After the controller selected the drive, not respond with READY signal.
the drive did
Not used.
After stepping maximum number of cylinders, controller did not receive track 00 signal from the drive.
TECHNICAL REFERENCE
HARDWARE OPTIONS
Hex Code
OH
1H
2H 3H 4H
SH
6H 7H B8H SH
AH
Table 3-22 Type 1 Error Codes, Controller Board
Message ID Read Error Data Error
Address Mark Not used. Sector Not Found Seek Error Not used. Not used. Correctable Data Error Bad Track
Format Error
Definition
The controller detected an ECC error in the target ID field on the disk.
The controller detected ECC error in the target during a read operation.
an uncorrectable sector
The controller did not detect the target
address mark (AM) on the disk.
The controller found the correct cylinder and head, but not the target sector. The controller detected an incorrect cylinder or track, or both.
The controller detected a correctable ECC error in the target data field.
The controller detected the bad flag during the last operation.
track
During a CHECK TRACK FORMAT command, the controller detected one of the following:
* Track not formatted * HWrong interleave * ID ECC error on at least one sector
3-47
TECHNICAL REFERENCE
HARDWARE OPTIONS
Table 3-23 Types 2 and 3 Error Codes, Command and Miscellaneous
Code OH 1H OH
Type
Message
Invalid Command
tllegal Address
Disk
RAM Error
iH
Program Memory
Checksum Error
2H
ECC Polynominal
Error
Definition
The controller received an invalid command from the host.
The controller detected an address beyond the maximum range.
The controller detected a data error during the RAM sector buffer diagnostic.
During its internal diagnostics, the controller detected a program memory checksum error.
During the controller''s internal diagnostics, the hardware ECC generator failed its test.
TECHNICAL REFERENCE
HARDWARE OPTIONS
Error Code
Table 3-24 Meaning
Error Code Summary
Illegal (direct) access to an alternate track.
TECHNICAL REFERENCE
HARDWARE OPTIONS
Error Code 1DH 1EH
1FH
Table 3-24 Error Code Summary Meaning
(Concluded)
f"._ X4t,',
On a FORMAT ALTERNATE TRACK command, the track is already assigned or is flagged as a bad track.
When the controller attempted to access an alternate track from a spared track, the alternate track was not flagged as an alternate.
On a FORMAT ALTERNATE TRACK command, the bad track equaled the alternate track.
Note:
The Address Valid bit (bit ?) may or may not be set and is
not included here.
=
TECHNICAL REFERENCE
HARDWARE OPTIONS
f!%.s.c
FORMAT
DRIVE
Command.
This
command
uses
the
selected
-interleave
factor
to format all `sectors having ID and data fields,
and writes 6CH into data fields. -The
controller
formats
from
the
starting
address,
which is passed in the command, to the end of the
disk.
Setting FORMAT pattern
bit S (from control byte DRIVE command causes the written on the disk data
S of the
command
block)
with
sector buffer to be used as the
fields.
the data
To initialize the
sector
buffer,
command
before
the FORMAT
DRIVE
follows:
issue
the WRITE
SECTOR
command.
Byte definitions
BUFFER are as
Notes: ¥ Refer to paragraph 3.6.1.6. 24 Factor is number of sectors per track minus one.
TECHNICAL REFERENCE
HARDWARE OPTIONS
3.6.6.5
on
the
does not
CHECK TRACK FORMAT Command.
This command checks the format
specified
track for correct ID and interleave.
The command
read the data field.
The byte configuration is as follows:
B
Y atam S e S RS TIT +-B I T
t]
7
| 6
|
S
t
NUMDBER
4
|
3
-4------- o
}
2
§
-------- tm--m-------- *
1
| o
030-=======§=======Q=======0~=======0=======+=======0=======#=======Q'
lof
o
-
I
o
|
o
bmmmem---- -
}
o
|
o
------------
-
]
1
|
o
|
i
{
e m------------ m---------- Fmmmmm == +-
t1)
o
§
o
|DRIVE
|
HIGH
ADDRESS (See note 1)/}
- ---------- bm--em------ em e
e mm---- mm--mm- e ------ o
m------ - +
|2}
MIDDLE ADDRESS
(See note 1)
}
tmb -
tme m rm-- e ---- tm--mmm---- mm
mm---------- b-- - m----------- +
13}
b mmmm=
141
o
mmmm------
| o
b m
- L
|S| RETRY?)
o
b -------------- P m---------
LOK ADDRESS
(See note 1)
rm-------------- mmme------ e m------ Pm
-
|
o
i
INTERLEAVE FACTOR
b m
- -
m----m.---- Am-------------- m--------------
§
0
{ o
| STEP 3] STEP 2|
e ---- m----m-------- R
o ------------
§ ------------ -------------- +
(See note 2)
mm---------- trmm-------- *
STEP 1| STEP 0|
-------------- m------------ +
Notes:
1. Refer to paragraph 3.6.1.6. 2. Factor is number of sectors per track minus one.
s
TECHNICAL REFERENCE
HARDWARE OPTIONS
3.6.6.6
FORMAT TRACK Command.
The FORMAT TRACK
command
reformats
the
track,
eliminating
all references to bad and alternate tracks.
Setting bit S from control byte S of the
command
block
causes
the
sector
buffer
to be used
as the data pattern in the data fields.
Otherwise, the command writes 6CH
in
the
data
fields.
The byte
definitions are as follows:
141
0
|
o
}
o
}
INTERLEAVE FACTOR (See note 2) |
L
e -------- e
{s] RETRY?|
o
| o
-
- --------- P ---------- e ----
- P
+
]
o
| STEP 3| STEP 2| STEP 1] STEP 0]
P
Notes:
------
-
P
------ P --------- b
-------- Cmm
.- b m-------------- P ---------- - +*
1. Refer to paragraph 3.6.1.6.
2. Factor is number of sectors per track minus one.
TECHNICAL REFERENCE
HARDWARE OPTIONS
3.6.6.7
FORMAT BAB TRACK Command.
This
track, setting the bad sector flag in the
are written.
The byte definitions are as
command fdrmats a specified
ID fields.
No data
fields
follows:
B
VRt el Bl GoooEccts +-B I T
NREUNMEBNERRES S So st e
SESS e +
t
7 |6
|s }4 !3
|2!1 }o
|
e P
jol
P
11}
T S S L S+ S S I T S C R e R
IT I S d T T
o Jo ]o !
---------- P -------- Fmmm-------- b
o
{
o
|DRIVE |
T T S R A S S ST S S S 4SS S S S SS 4SS S S E SR 4SS SR EEE S
o !o )1 !1 )1 }
-------- o m------ Fmmmmmm--== m---------- e mm - +
HIGH ADDRESS (See note 1) |
e
12)
e ------------ e
rm e ------ b= -------- mm
=
MIDDLE ADDRESS (See note 1)
e mm-------- P--
- - +*
|
mbmmmm === tmmm - *------------ -
e mm--- - .-
e
134
LOW ADDRESS (See note 1)
- -------- +
|
et m e -- - e m - P ---------- m------------ mmmm - tmmmm-- Pmm--m-------- T
+*
ja]
o
|
o
| [}
|
INTERLEAVE FACTOR (See note 2) |
P -------------- P ---------- e
-
P
P
e
----- T
------ +
|5} RETRY?{
o
|
o
{
0
{ STEP 3} STEP 2| STEP 1} STEP O}
e m e ---- - mmmm-- tmmm-------- m------------
e e
- P mm - P ---------- +
NOTES :
1. Refer to paragraph 3.6.1.6.
2. Factor is number of sectors per track minus one.
TECHNICAL REFERENCE
HARDWARE OPTIONS
3.86.6.8
READ Command.
Starting
this command, the controller reads a
The byte definitions are as follows:
with the sector address
specified number of
given in sectors.
Notes: 1. Refer to paragraph 3.6.1.6. 2. If this bit is set in the READ command and an ECC error is
found, retry the command.
3.6.6.9
HRITE Command.
This command writes the
sectors, starting with the initial sector address
DCB.
Byte definitions are as follows:
specified number of
contained
in the
)
S
|S| RETRY?|
o
J 0
1
o
| STEP 3| STEP 2| STEP 1} STEP 0|
Note:
Refer to paragraph 3.6.1.6.
TECHNICAL REFERENCE
e
b
;
HARDHARE OPTIONS
»
3.5.6.10.',SEEK
Command.
This command initiates a seeklto the track
" specifieidn the DCB.
The
drive
must
be
formatted.
The byte
definitions are as follows:
Note:
Refer
HUMBER -+4------~ e
tm------------ .
|
3
i
2
}
1
|
o
e mccma
T
USR SSISRII S S LIS
| 1
| o
|
1
i 1
om -
e mr e -- - rm----------
e m------- +
HIGH ADDRESS (See note)]
P
tm----m------ tmm---------- = S T
+
MIDDLE ADDRESS (See note)
i
P --
e~ ------ o ------------
e m-------- Fmm---------- +
LOW ADDRESS
(See note)
|
S --------- mm--m-- Fmmmm = mmm= ---- +
|
P -------- tm--m--m------ tmmm-----
mmm------ +
| STEP 3| STEP 2| STEP 1| STEP 0|
mm---------- o
o ---------- mm--m-- +
to paragraph 3.6.1.6.
For drives
using buffered
seeks, SEEK commands can be overlapped.
After the controller issues a SEEK to the drive, it does not wait for
the drive to complete the SEEK, but returns a completion status.
If
the return status shows no error, then the SEEK was issued correctly.
If
there
is an error,
then
the SEEK was
not
fssued.
After
transferring the status, another command `can
be
issued
to either
drive.
If a drive with an outstanding SEEK receives a new command,
the controller waits (holding BUSY active) until the
SEEK
completes
before
executing
the new command.
(See the section entitled "TEST
DRIVE READY Command" for a special
case.)
There
is no time-out
condition
in the controller
waiting for the buffered-step SEEK to
complete.
TECHNICAL REFERENCE
.
.
HARDWARE OPTIONS
3.§.6.11
INITIALIZE DRIVE
CHARACTERISTICS
Command.
This
command
'enables
the controller
to work
with drives
thfi} have different
capacities and characteristics.
However, both Winchéster drives must
" be of the same manufacturer and model number.
b
After the computer sends the command
(pcB)
to the
controller,
it
sends
an B-byte block of data containing the drive parameters.
Some
of
the parameters
occupy
2 bytes;
all
2-byte
parameters
are
transferred are:
with the most significant byte (MSB) first.
The 8 bytes
9T mAa o o
Maximum Maximum Maximum Starting Starting
number of cylinders (2 bytes) ECC data burst length (1 byte) number of heads (1 byte)
write precompensation cylinder reduced write current cylinder
(2 bytes) (2 bytes)
When the controller values are set:
is powered up or reset,
the following default
Maximum Maximum Maximum Starting Starting
number of cylinders (C)= 153 ECC data burst length (E)= 11 bits number of heads (H)= 4
write precompensation cylinder (P)=64 reduced write current cylinder (W)= 129
The parameter for the maximum ECC burst length defifes the length
of
a burst
error
in the data field that the controller is`to correct.
The burst length is defined as the number
of bits
from
the
first
error
bit
to
the
last
error bit.
For example, if the controlier
detects a S-bit ECC error and
the
erroneous
data
appears
(before
correction)
as
S
(1100
0101),
it could appear as D4 (1101 0100)
after the correction.
However, if the CPU has set
the maximum
ECC
burst
length
at 4 Dbits,
the
controller
might flag this data as
uncorrectable.
This is a type i1, code 1 error.
TECHNI CAL REFERENCE
- WARDWARE OPTIONS
: -
9 '
£
`Byte d efinitions for the INITIALIZE DRIVE CHARACTERISTICS command are
as fol lows:
.
i 7 | Bit 6| Bit S| Bit 4] Bit 3] Bit 2§ Bit 1} Bit 0|
Byte d efinitions
for
the drive
parameter
Dbytes
{passed
to the
contro ller
after
the
INITIALIZE
DRIVE CHARACTERISTICS command has
been i ssued) are as follows:
------- +--===m=-+=-B I T
7
}
6
}
S
i
NS URMEBRENRE - &
4
i
3
|
+ ee = -
2
|
e S oS oo s s = --
1
|
o
§
EEE
SSE 4 SS
SSE 4 TS I TS
4 S S TS S
S 4SS IR ST SIS SRS S SASNIRISSS SIS SRS
MAXIMUM NUMBER OF CYLINDERS: MSB
i
-------
e ee
e, m el r e
e e-
ee o
------
MAXIMUM NUMBER OF CYLINDERS: LSB
-------
ee m
e et mm
e e c e dec e mc e b e m e m
f -
o
|
0o
i
]
|
o
| MAXIMUM NUMBER OF HEADS
|
-------
e m
e ee
e mmmm e
m e m e dmmcm b m-------- b m e
b
STARTING REDUCED WRITE CURRENT
--------------
e m
e, --c e e --, e, e b
CYLINDER:
--, e b e rm----,
MSB
i
e ---- ------ b -----------
STARTING REDUCED WRITE CURRENT CYLINDER:
LSB
-------
e m----
e, e, b e, m
b e m, e ----m b, --,-- ---- b
------
STARTING HRITE PRECOMPENSATION CYLINDER:
Msa
------- W
=
e
e
e
i
- ----------
§
STARTING HRITE PRECOMPENSATION CYLINDER:
LsSB
------- e
et e
r ee
b m e --c b --
i e ----------
o
]
o
------- o m
f
0
i
e e
b
0
| MAXIMUM ECC DATA BURST LENGTH |
-- b e e e r ---- fm e
r b
----
-
- ----
TECHNICAL REFERENCE
HARDWARE OPTIONS
3.6.6.12
READ ECC
transfers 1 byte to
burst
length
that
command.
This byte
type 1, code B.
Byte
BURST
ERROR
LENGTH
Command.
the CPU.
This byte contains the
the
controller
detected
during
is valid only after a correctable
definitions are as follows:
This
command
value of the EcCC
the last READ
ECC data error,
e
e 6] Bit
S|
BiBtIT
4]NUMBiBtER=3-| -=Bcict--c2]omeBiotocc1o| mmBointn.
. 0|
S+=Z=SaTTe=e =S I===S T 4
Fmm et m e - ----------a
e m------ tm--mm-- L
Pm--m e
e ---- re-------- +
P
m e
bmm P mm - tem--m - -
Pem e tmmm e
r------me *
be | mm4 mb]m unmm uese --edlb P unumems--em--detjtuo--nm--mmum--s----e----dlm P umn--u-- semmd-- ]rL u--n--u--sm--e--dlP o unumsme----d--lut tmnmmu-- ms--m--em --d--lurnmmu--m--s----e----d----l
+ +
e m e ---- - b----em--
e mm--- t------mm-- e
---- r------m----
m--mmm---- Po--mm- +
TECHNICAL REFERENCE
e
>
.
HARDWARE OPTIONS
3.6.6.13 =FORMAT ALTERNATE TRACK Command.
The FORMAT ALTERNATE TRACK
command formats the header fields of the "bad track" with the.
alternate
track
information
(assigned
by the CPU).
The alternate,.
track is formatted to identify it as an alternate.
The command
byte
definitions for FORMAT ALTERNATE TRACK are as follows:
IS} RETRY?|
0 f(Note 3) 0 | STEP 3| STEP 2| STEP 1| STEP 0}
Notes: 1. Refer
to paragraph
3.6.1.6.
2. Factor is number of sectors per track minus one.
-
3. If this bit is set, the data in the existing sector buffer
is used to fill the data field. If this bit is cleared,
the data field is written with 6CH.
-
The
interleave
command, and is
byte (S) is set,
the data field.
byte
(4)
is programmed
the same as in the FORMAT
used on the alternate track.
If bit S of the control
the data in the existing sector buffer is written to
If not, the data field is written with 6CH.
After issuing the
Alternate
Address
assigned alternate
ignored.
command, data
logical
the controller
block.
These
3
address.
Again
asks
for
the
Assigned
bytes
point to the CPU-
the
sector
address
is
TECHNICAL REFERENCE
.
HARDWARE OPTIONS
The byte definitions
are as follows:
'
for
the
Assigned
b
Alf!}nate
Address
Data
Block
>
Note: Refer to paragraph 3.6.1.6.
3.6.7
Alternate Track Assignment
The computer both assigns alternate tracks and locks out bad
tracks.
Bad
areas
on
the
disk are
labeled defective on a track basis by
issuing a FORMAT BAD TRACK command (command code 07).
One procedure
for assignment and handling of alternate tracks is given below.
1. Give the FORMAT
DISK
command
(command
code
04).
formats
the
entire
disk
drive starting at logical
00,
This track
a. If any errors occur, give the command .
REQUEST
SENSE
STATUS
b. If a format error is indicated, bytes 1, 2, and 3 of
the returned
status
give
the address
of the bad
track.
. Give a FORMAT BAD TRACK command (command code 07)
to
the track.
d. Reissue the FORMAT DISK command.
e. If any
other
errors
occur
during
the
subsequent
formatting,
reissue the REQUEST SENSE STATUS, FORMAT
BAD TRACK, and FORMAT DISK commands until the
entire
disk is formatted.
2. Give the RECALIBRATE command (command code 01) to the heads over track 000.
position
All
sectors
on
the disk
errors occurred in the data.
are read to see if any uncorrectable ECC The FORMAT command places a 6CH pattern
in the data fields of all
sectors,
and
the
computer
program
can
verify
this
data
pattern
after
the data
is read
into memory .
However, verifying the data byte for byte is not
usually
necessary,
because
the
error
detection
and
correction
circuitry
flags all
TECHNICAL REFERENCE
HARDWARE OPTIONS
'
uncorrectable errors. multiple sector reads
e
£
If a la;gé block of host memory is
can be issued to speed up the verify
o
available, process,.
When
an
wuncorrectable
error
is found, issuing a FORMAT BAD TRACK
command (command code 07) to the failing track
writes
a bad
track
flag
into all
identifier
fields.
Later
accessing of this track
results in an error, causing the sense status that follows to show an
error code 15H.
NOTE
WHhenever a user program
accesses
the disk,
be
sure that the operating system does not allow the
program
to issue a READ or WRITE command to the
alternate tracks.
The disk controller has no way of knowing when an alternate track
is
being
read.
The alternate tracks are sometimes assigned at the end
of the disk (highest track numbers), but they can be assigned to any
tracks
so
long
as
the
track label is maintained by the computer.
Given the error correction capability of the controller, four
tracks
reserved
as alternates
should
be adequate
for all disk drives
currently available.
However, the system programmer
should
consult
the disk drive manual for the hard-defect specifications.
3.6.8
Alternate Address Protocol
s
After
receiving
the FORMAT ALTERNATE TRACK command and the assigned
alternate, the controller performs the following steps:
1. Seeks to the "alternate assigned track" and verifies
that
it
is
not
already an assigned alternate or a flagged bad
track.
NOTE
If the track has
already
been
assigned
as
an
alternate
or is flagged "bad", then error code
1DH is given and the command
is aborted.
This
usually
implies
that the computer is attempting
to assign two bad tracks to
the
same
alternate
track.
2., Formats the track as an assigned alternate track.
3. Seeks to the bad track and formats the header
as a spare
TECHNICAL REFERENCE E
.
»
o .
v
track pointing to the assigned altq;nate.
4. Destroys - data fields on both the bad-»'track
track.
:
HARDWARE OPTIONS and alternate
The procedure follows:
for wusing
the
FORMAT ALTERNATE TRACK command is as
1. Format the entire disk, including spare tracks.
2. Verify the disk.
3. Assign each media defect an alternate track.
4. Assign alternate tracks list.
for
drive
manufacturer's
defect
The wvhen
controller
automatically
seeks
an access is made to a flagged
to the assigned alternate track
defective
track.
Consecutive
accessing controller
does
not result in reseeking to the alternate
maintains position on the alternate track.
track.
The
NOTE
When using the FORMAT ALTERNATE TRACK command, be
sure
to
< include
(in
the
controller
initialization)
cylinder and head ranges for the
alternate tracks.
7
Generally, the actual disk space is greater
the
system
software.
This
extra
space
tracks as needed.
The alternate tracks are
than the amount fixed
by
can be used for alternate
invisible to the host.
The number of spare tracks depends on the drive
of defects
allowed by the drive manufacturer.
track is allotted for each S0 to 100 tracks.
size and
the
number
Generally, one spare
Direct access track results
(attempted data transfers or
seeks)
in an error code 1CH, and no transfer
to an alternate takes place.
TECHNICAL REFERENCE
HARDWARE OPTIONS
_,,_.,_. > s M
3.6.9
HWRITE SECTOR BUFFER Command
-
This command
pattern.
No
The
command
buffer.
The
is used to f£fill the sector buffer with a host-given data data is transfered between the drive and the controller.
accepts S12 bytes of data and stores them in the sector byte definitions are as follows:
Ao 6] Bit S| BiBtIT 4|NUMBiBtER-3-| -=B-i=t=---2§==mBoit=-=1~{ =--B--i--to--© +
3.6.10
READ SECTOR BUFFER Command
This command sends 512 bytes of data from the
CPU.
The byte definitions are as follows:
~
sector
buffer 0
to
the
8
y t e
+| emm7mmm|mmBmitmmm6]mmBmimt mmSe|ooo
BIT Bit
4]NUMBBitER-3-§--=Bi--t=--2=| -=-Bi--t------1|=meBoiot----0}+
v
o
TECHNICAL REFERENCE
HARDHARE OPTIONS
.
-
20
3.6.11 RAM DIAGNOSTICS Command
This
command
performs
a data pattern test on the RAM buffer.
The
byte definitions are as follows:
B
Y t +omcm
e
v o
e
Bit
e e
S|
BIT
Bit
NUMBER-~=-------c-meccace--ao
4| Bit 3| Bit 2| Bit 1| Bit
0| +
(i
3.6.12
DRIVE DIAGNOSTICS Command
* B
This
command
tests both
the drive
and
the`~ drive-to-controller
interface.
The controller sends RECALIBRATE and SEEK commands to the
selected
drive
and verifies sector 0 of all the tracks on the disk.
The controller does not
perform
any
write
operations
during
the
command; it assumes the disk has been previously formatted.
The byte
definitions for the command are as follows:
B
y
P 4 mrmmmcec e ee BIT NUMBER--~--~----=--
s *
e |
7
| Bit 6| Bit S| Bit 4) Bit 3} Bit 2§ Bit 1] Bit of
0--v--`-======fi-======0======§======§======§======0'======0`======0
| o | 1}
LIRSl B 1
e m b -- oo b
D
| o | o j o ] £ 13 2 |
Fm------ tommm-- mme e tommmm m--m - +
TECHNICAL REFERENCE
HARDWARE OPTIONS
3.6.13
CONTROLLER INTERNAL DIAGNOSTICS Command
This
command
causes
the
controller
to perform a
controller
checks
its
internal
processor,
data
circuitry,
and
the checksum of the program memory.
does not access the disk drive.
The byte definitions
self-test.
The
buffers,
ECC
The controller
are as follows:
o mmm7 o | Bit o 6§ Bit S| BiBtIT 4]NUMBiBtER-3-| ==B-i-t=-2-|--cBi-t-om1o| --oBoimtooO}*
3.6.14 READ LONG Command
i,
This command transfers the target sector and 4 bytes of data
ECC
to
the CPU.
If an ECC error occurs during the read, the controller does
not
attempt
to correct the data field.
This command is useful for
recovering data from a sector with an uncorrectable ECC error and for
diagnostic operations.
The byte definitions are as follows:
B
Yt
S
Commoona +-B I T
NUMBER -+------- Soooooo) Sl +
t]
7
}
6
|
s
|
4
§
3
§
2
|
1
f
o
§
+ B+ S S S S S E S+ I ST T
104
1
) 1
b=
|2
o
e ----------
|
c
b --=
o ----------
eSE S SS
] 1
r--------------
|DRIVE
L
4 S S E S T E S+ S S ESS TS 4SS SESSS4ASSSSSRSEISSSSSS
| 0
| o
l 1
i o
j 1
R
e
Y e
e
------ -
o m------ +
|
HIGH ADDRESS (See note)|
e --
- ----
o ------ e
e
e
+
j214
MIDDLE ADDRESS
(See note)
|
b
-- --
m------------ e
------ mm---------- Pm--m-------- e ---------- o ---------- e
------ +
13)
LOW ADDRESS (See note)
|
P
14}
---------- e
b ---------- *mmm-------- e
BLOCK COUNT
---- m------------ mmmmm= b m-------- +
(See note)
ot
-- = m---- e
e -------- e -------- mmm-------- -
- -
e
+
|S| RETRY?{
c
§
0
|
o
| STEP 3} STEP 2} STEP 1| STEP 0}
e R
-------- e -------- rm------------ b mmm -
m--------------- o
e
+
Note: Refer to paragraph 3.6.1.6.
TECHNICAL REFERENCE
HARDWARE OPTIONS
3.6.15 WRITE LONG Command
This command transfers a sector
to
the
disk
drive.
During
supplies the 4 ECC bytes instead
bytes.
This
command is useful
byte definitions are as follows:
of data and four appended
ECC Dbytes
this
write
operation,
the computer
of using the hardware-generated
EgCC
only for diagnostic operations.
The
Note:
Refer
T
NUMBER -+------- S
SESS +
|
4
|
3
|
2
I
1
|
o
|
===0=:=====0=======0=======O=======0=======0
| o
|
o
------- Pt
et e --
|{DRIVE |
|
1
|
i
|
o
|
b mm--rrm e m b e e
b e m----------¢
HIGH ADDRESS (see Note)]
-------
e
Mt e
e me e meb
e mr--r -- e ------
MIDDLE ADDRESS
(see Note)}
------- P e
e pee
e e, e b r e m---- e b e ---- e ---- g
LOW ADDRESS
(see Note)|
------- P r et
et e et e
rbe e e
-- e ------g
BLOCK COUNT
}
------- P e et
eee e
r e e
mr e et e ------
§
0
| STEP 3| STEP 2| STEP i} STEP 0}
------- e e e e e
to paragraph 3.6.1.6.
bt
r e bt
-- e
--------d
a
&4
TECHNICAL REFERENCE
HARDHWARE OPTIONS
3.6.16
Execution Order of Remaining Diagnostics
Kot all of the diagnostics are executed
The remaining
diagnostics
should
be
following order.
by the computer on powver-up.
<called
by
the
CPU
in the
1. CONTROLLER INTERNAL DIAGNOSTICS (command
code
E4).
This
command
tests
all
the
logical
and
decision-making
capabilities
of the controller,
the
program
memory
checksum,
and
the error detection and correction circuits
(ECC).
Executing
this
diagnostic
ensures
that
the
controller can communicate with the computer.
2. RAM DIAGNOSTICS {(command code EO0O).
This
command
verifies
that
the sector buffer is operational by writing, reading,
and
verifying
various
data patterns
to and
from
all
locations.
3. INITIALIZE DRIVE CHARACTERISTICS (command code
O0C).
This
command sends the new drive configuration to the controller
when the parameters of the connected drives differ from the
defaults. The INITIALIZE DRIVE CHARACTERISTICS command must
be igssued before executing the DRIVE DIAGNOSTIC command.
4. TEST DRIVE READY (command code 00).
This
command,
issued
before the DRIVE DIAGNOSTIC is executed, finds out when the
drive is ready to accept a command.
S. DRIVE DIAGNOSTIC (command code E3).
This command issues
a
RECALIBRATE
to the disk drive and then steps though all
tracks, verifying the ECC on the identifier fields
of
the
first
sector of each track.
If this diagnostic passes, it
implies that the disk has been formatted and that the first
ID field of each track is good.
3.6.17
Error Correction Philosophy
The typical error-correction time of the controller is approximately
S0 ms, which is greater than the time for one revolution of the disk.
The sector
in error can be reread (if bit 6 is not set in byte S of
the READ command DCB) on the next revolution during a READ
command.
In most cases, the error is soft and does not reappear on the reread.
This initial reread of the failing sector is in addition to the retry
count passed in the DCB (bit 7, byte 5),.
The
controller presets the error retry count to 4 each time a sector
is read succegsfully.
Sometimes, an error labeled
uncorrectable
is
later
found
to be correctable.
If this happens during a multiple-
sector transfer, the controller resets the retry count
to 4 Dbefore
another sector is read.
TECHNICAL REFERENCE
HARDWARE OPTIONS
3.6.18
Sector Field
Table 3-25 describes
Description the sector information
fields.
Table 3-2S5 Sector Field Format
Field
AM GAP1L SYNC GAP2 coM CYLH CYLL HEAD SEC FLAG ZER ECC GAP3 SYNC2 GAP4 DATA ECC2 GAPS
£WE -nANNM -OAKMMEELEBENEO
Kumber of Bytes
A
Field Description
Address mark
Zero byte gap
ID sync byte
ID zero byte gap
ID compare byte
Cylinder high (MsB)
Cylinder low (LSB)
Head number
Sector number
Flag byte
Zero byte
ID ECC bytes
Zero byte gap
5
Data field sync byte
Data field zero byte gap
Data field
-~
Data field ECC bytes
Inter-record zero gap
Notes: 1., Cylinder (track) numbering is O-based. 2. Sector numbering is i-based. 3. Disk surface numbering is O-based
The
track layout for the Si12 bytes/sector, 17 sectors/track is given
in Table 3-26.
TECHNICAL REFERENCE
e»,
HARDWARE OPTIONS
-
Table 3-26
S12-Bytes-Per-Sector Format
BYTE
MSB
LSB
dmmmemmmeeeem BIT NUMBER--~-=we-wmcomacoooo--o +
T Z0
6 S
S T SR AR | 3 | S 2 S e L | JE R0
EEEEEEREE
1-4
--------
s-13
--------
A R EEE A R R AR
R
|
ADDRESS
et e e, e r e e b e
§o {o |o |
e m e, e, et
22 A
MARK b
o } b
s R
RS
e e e b e ------ b e
o }o {o
e
e be
b me
RSEE TR EY
|
-- ==
§o |
m b m-- == 4
14
i
-------- b m
1s-16 | ©
ID SYNC BYTE
|
e e
e e ee e bree
{4 o } o }j o
b e m e mm------fmmmm e -- === &
| o J o } o |} o |
-------- P e e m e b e e r e b m e
-- b m e -- b m---- ==}
17
|
-------- P m e
ID COMPARE BYTE --mr e b e mr e b rr e e b e e e b
i cc e b m e -- e -- = --------
i8
§
--------
e e
CYLINDER NUMBER ( MSB )
{
e
e e ee
e e,
m e m e -- b m e m b m--------
i85
§
-------- P
20
|
--------
m vm b et m
CYLINDER NUMBER ( LSB )
m e
b
HEAD NUMBER
b
e mbe
e r e, e
mm e
e m e bee ce
{ == ---- -
|
e ------
21 --------
22
] e
f
e e,
SECTOR
NUMBER
b, e, e e b e,
b r
FLAG BYTE
e b e
§
b e
-- - --------
}
--------
23
FE
-------- A
e e, c e, e e b
e b m,r
08 | N0 SN I 0 S
RO SN 8 O
e e
e e e e o e e ey v e
e e
b m e-- be --
b ----------
[R Ol
.0 14 o |
e m
e e e o e e e ee
24-27 --------
28-43
--------
|
ID ERROR CORRECTION CODE BYTES
§
&-----~-¢----~----¢--------+--~------¢---------¢--------0--:--0---------+
| o | © § o |} o f o | o t o | o |
Fmmmmc e m e
c-- e mmm---- e m b
-- b ----
=== &
44 --------
45-46
§
DATA FIELD
Fmm e m b e mm e
|© }o
mc b
|o |
SYNC BYTE mcm b e mmc b e m e
o |} o § o
m b e m e
4 ©
i m == &
|o }
---------------- Prmmmm b e
et e m b
c b eme e
-- b mm------ bk ---- == 4
47-558 | --------
e, et e
512 BYTES DATA e b r e, --r e b e, r e b e m e
rm e b
{ m -- - --------
$59-562 |
DATA FIELD ERROR CORRECTION CODE BYTES
§
--------
e et e, e r e rr e b
cm e
e me
--- -
s63-605 §j o § o | o } o | o } o | o | o |
---------------- P e e
e
e bt e e e et m
= --------
60S bytes/sector including ID and overhead
Track Capacity
= 10416
10285 +131
= 17 sectors of 605 bytes/sector = Speed tolerance gap
10416
TECHNICAL REFERENCE
HARDWARE OPTIONS
3.6.19
Specifications ~ Controller Board
Table 3-27 gives the Winchester controller
board
specifications.
Table 3-27
HWinchester Controller Board Specifications
Environmental Paramsters:
Temperature Relative Humidity
o (@ 40 F wet-bulb temperature, no condensation) Altitude
Operating
o
o
10 C to 40 ¢
°
o
(32 F to 131 F)
10% to 950%
Mean sea level to 10 000 ft
Storage
[}
o
-~10 C to 60 C
o
o
(-40 F to 167 F)
10% to 90%
Mean sea level to 4S5 000 £t
Power Reguirements:
Voltage
Range
+5.0 vade
4.75 to S§.25 vdc
-12.0 vde
-10.8 to -13.2 vde
Current 2.5 A maximum 2.0 A typical 66.0 mA maximum 48.0 mA typical
3-71
TECHNICAL REFERENCE
HARDKWARE OPTIONS
3.6.20
Electrical Interface
This paragraph specifies the electrical
interface
requirements
for
the S 1/4-in Winchester disk drive.
All
Winchester
controller
boards
use
header
interchangeable with the AMP type 87215-7 for the 20-pin
(to J2/P2),
and type 1-87215-7 for the 34-pin connector
Section S5 contains assembly drawings showing the pin-outs
connectors.
The connector layout is shown in Figure 3-9.
assemblies
connectors
(to J1/P1).
for
these
WINCHESTER CONTROLLER
BOARD
TAAYMSPPSEEMH8BE7LA21YD5E7R OR EQUIVALENT
AMP HEADER TAYSPSEEM1B-L87Y215-7
OR EQUIVALENT
RIBBON CABLE TO WINCHESTER DRIVE
ATCRYMEOPPCNEENPET8CA8T3CO7L7RE-4 OR EQUIV.
ATRCYMIOPBPNEBNOEN8C8T37O3R-6| 5, OR EQUIV.
20-PIN RIBBON CABLE
RIBBON CABLETO WINCHESTER DRIVE
oARCMEOPCNENPETCATCOLRE 88377-6
OR EQUIV.
oARCMIO5BPNBNOENCTOR
883733
OR EQUIV.
J
WINCHESTER DISK DRIVE
34-PIN RIBBON CABLE
223216-21
Figure 3-9
Control and Data Cabling for the Winchester Disk Drive
TECHNICAL REFERENCE
DEVICE SERVICE ROUTINES
Section 4 DEVICE SERVICE ROUTINES
4.1 ROM INTERFACE INFORMATION
ahdTicnheanodivrtmsidepcwraeaftRraiOescMbeceicoltniitotiorfunynosflagoer.tmhpowaefirttoihvotihTTndeheeexsfausisttnuacsrnlyedusIiadtnnreesfdsmtoprrrumoRIimadO/netMu0tnicetotrdcssnreouvnpittcaPaeinrsondnovsfeecitsnoiosnnwrirsstoiht,netraiiulnnctssgteyyirssottfnCeeaosmmcmsiponufmugftoneetrimwrtov..arrhwyeiatrhdmwaapTfrtshohe,ere Tadcuhnsiaedesrkefoftufhulunoscpttehtireoaosarneetasivnoagsivaddmaeeisslcycarsafbituulbesneemicdntgit(ooDanOraseSn.a)yllicmisopunlsefeirlmnsiescntttasoelfdledwt.ihwetihthsyHsocttwhoeeedmever,roinpeegrattarhhtdee ilneugsssysesrteosmfmyusstwtehRmiO'cMbs,he
paTTafiosnoyundipntnicertctrekairpeeloulyxtlnpaboesytcoc,eaurtthmdoiefe,anlcgtlhhauaesnseadDoienrSrisR-smwp.pIlraNafairTruytten,tceE(tanaoiifccnohctaneenacsdsromsrdaDeuejS.dpoRtad,rri)esbkyd,jueisvpnatilsccacthecerapsisuansctgsetceadihrovanuinnttcihheeqrooufopeucrigoonthduthveeteeirctnrthaeiuoenpprp.tlBi0r(cBeDa8SgvIbRieil)scne,sttdoeoifrrvtitwdysaupuraecAe.tlhHo
For
specific
microprocessor,
Manual.
information
read
the
on
the
architecture
IAPX 88 Book
or
the
of
the Intel 8088
IAPX 86,88 User's
4.2
HWRITING SOFTWARE FOR COMPATIBILITY WITH FUTURE PRODUCTS
Tserlhaoxeerfplgteeewnaasssriioevnfegit,nwvtaehrasaettnnmdeewcnatysnohuoubvleeodfrdseuisvboeeeyndlosouaprvwoiitofhdfoetridm.feustthouifrstTaewnhadiprsrTeoexdmgauouscnitiedsye.InusnwwitudlsroluuuMambaletlkhnyeietdnlslgpydipyofrcrufoheidapcunrtucgeotlesstse.cnrtesaaatnnedda
4.2.1
Compatibility Levels
In order for the software to work
compatibility
must exist at some
level, the system ROM interface
level.
on more level: level,
than one hardware
product,
either the operating system
or the hardware
interface
TECHNICAL REFERENCE
DEVICE SERVICE ROUTINES
4.2.1.1
Opefgring System.
system level is compatible
system, including products
Software that interfaces at the with all products using the samé of other manufacturers.
operating operating
4.2.1.2
System
ROM
Interface.
Software that interfaces with the
Texas Instruments-supplied system ROMs through the interface
vectors
is compatible with other hardware products having the same functional
characteristics.
These products can differ in physical or electrical
characteristics
from
the
standard
Texas
Instruments
product.
Programs compatible at this level or at the DOS level are more likely
to be compatible with future products.
4.,2,1.3
Hardware
Interface.
Programs
that
use
directly
(for
example,
input or output to hardware
least likely to be usable in another computer system.
the
hardware
addresses) are
4.2.2
Areas of Hardware Compatidbility
Texas Instruments recognizes that the system ROM
interface
is not
sufficient
for all applications.
Products
wusing
the advanced
capabilities of the hardware cannot be restricted to
wusage
of
this
interface.
The
following
paragraphs
descridbe
the hardware
compatibility that can be expected in future subsystems or subsystems
accessed from ROM only.
4,2.2.1
Alphanumeric CRT.
The alphanumeric CRT is wéfil--supported by
the system ROM.
Accessing the screen directly can speed
processing,
lets you use "windowing", and lets you use horizontal scrolling.
You
should
restrict
direct access to the alphanumeric CRT screen to the
attribute latch and to address ODEOOOH, the actual memory buffer
for
the
screen.
(The
"H"
represents
hexadecimal.)
Before using the
screen directly, these programs should issue a Clear Screen
function
call
to ensure that the hardware is set up for direct access.
Refer
to paragraph 2.4.7 for information about the CRT hardware.
Using the ROM functions to put data on the screen while accessing the
screen directly
can
cause
undesirable
hardware
actions.
It is
possible,
for instance, that the screen can be hardware-scrolled, so
that the logical upper left position is no longer the physical
upper
left
position.
All
operations
on the cursor should use the ROM
interface calls.
This will ensure that possible redesigning
of the
cursor logic does not prevent the program from running.
TECHNICAL REFERENCE
DEVICE SERVICE ROUTINES
4.2.2.2
Graphics
CRT.
The graphics screen is not
system ROM; therefore, all graphics screen functions
to the hardware.
The graphics screen size is 720 by
supported by the must go directly 300.
To simplify modification,
all
routines
hardware
should be arranged in a modular
constants should be given symbolic names.
for more information.
that access
the graphics
fashion.
Hardware-specific
Refer
to
subsection
3.5
Texas
Instruments
will
endeavor
to keep future graphics hardware
fully compatible with the current hardwvare.
4.2.2.3
Disk Subsystem.
The disk subsystem is fully
supported
in
the
ogystem
AROM,
with
the
exception
of
the -ability
to format
diskettes.
For normal operations, direct access to any of
the
disk
hardware
should
not be necessary.
Upon request, Texas Instruments
will supply a format routine to gqualified software vendors.
4.2.2.4
Keyboard System.
The keyboard
the
system
ROM.
Direct
access
to
necessary for normal operations.
system is fully supported
in
the keyboard interface is not
4.2.2.5
Interrupt Controller.
The interrupt
controller
system
is
used
by
the system ROM, but it is not supported in a fashion usable
by software writers.
In future
products,
Texas
Instruments
will
attempt
to Xkeep
the same
interrupt
levels,
usage, and hardware
addresses for accessing the device.
However, the constants
uged
to
access this hardware should be symbolic to facilitate modification.
4.2.2.6
System Timers and Speaker.
The system
that allow
other
software
to intercept
the
interrupts.
The extra timer is reserved for use
software products.
ROMs contain vectors
2S-ms
system
timer
by Texas Instruments
The
speaker
access is not
(or bell) necessary.
is well-supported
by the system ROM.
Direct
4.2.2.7
Parallel Printer
fully
supported
in the
for normal operation.
Port. system
The parallel
RONM.
Direct
printer port system
is
access is not necessary
4.2.2.8
Serial Communications.
is not
directly
supported
by
compatibility, Texas Instruments
hardwvare.
The serial
communications
hardwvare
the
system
ROM.
To ensure future
does
not
intend
to change
this
TECHNICAL REFERENCE
DEVICE SERVICE ROUTINES
4.3 SYSTEM ROM INTERRUPT VECTOR USAGE
The
system ROM uses interrupt vector locations in the first 1K bytes
of memory.
These vector locations are used for hardware
interrupts,
as
interfaces to the ROM functions, and other uses as given in Table
4-1,
ROM.
The vectors marked with an asterisk are actually
used
by
the
The other vector locations cause a "wild"" interrupt if vectored
to, and the usual display is:
"*% SYSTEM ERROR ** - 1042"
To patch
in replacement routines for those in the ROM, any of these
vectors can be changed by the disk operating
system
(DOS)
or by
applications
software.
Table
4-1
gives
vector usage in terms of
"interrupt type," which is the number used in an INT instruction.
To
calculate the absolute address of the vector, multiply the
interrupt
type by four.
For example,
the keyboard print screen interrupt
vector (type
SEH)
would
be a double
word
at
location
0:0178H
{(SE x 4 = 178H).
NOTE The symbol "H"" denotes a hexadecimal value.
*
TECHNICAL REFERENCE
DEVICE SERVICE ROUTINES
Table 4~1 System Interrupt Vector Usage.
Yector
Descri
ion
Re
oc 01 02% 03
04 0S5-1F 20-3F 40 41 42 43% 44 4s 46% 47 % 48% 49% 4A% 4B% 4ac 4Dx* 4E% 4F % S0 Six%x S52% S3% S4% 55-56 S7% S8% S9% SAx
SB* SC* SDx* SE* SF*
Divide~-by-zero trap Single-step trap Non-maskable interrupt Break (single-byte)
software interrupt Overflow trap (Reserved by Intel) (Reserved for MS-DOS) 8259 interrupt ¢ 8259 interrupt 1 8259 interrupt 2 8259 interrupt 3 (Timer 1) 8259 interrupt 4 8259 interrupt S 8259 interrupt 6 (Disk controller) 8259 interrupt 7 (Keyboard UART) Speaker DSR interface CRT DSR interface Keyboard DSR interface Parallel port DSR interface (Reserved for future use) Disk DSR interface Time-of~day clock DSR interface System configuration call Fatal software erfror trap Restart timing event
Cancel timing event SVC interface subroutine Activate task subroutine (Reserved for future use) CRT mapping vector System timing, 25 ms (time slicing) Common interrupt exit vector (ROM) System timing, 100 ms
(timing serv.) Keyboard mapping vector Keyboard program pause key vector Keyboard program break key vector Keyboard print screen vector Keyboard queueing vector
IAPX 88 Book ! IAPX 88 Book ! IAPX 88 Book !
IAPX 88 Book ! IAPX 88 Book ! IAPX 88 Book ! MS~-DOS Operating System @ Component Data Catalog ! Component Data Catalog ! Component Data Catalog ! Component Data Catalog ! Component Data Catalog ! Component Data Catalog ! Component Data Catalog ! Component Data Catalog ! Section 3 !! Section 3 !! Section 3 !! Section 3 !!
*k Section 3 !! Section 3 !! Section 3 !
* & keR * % * & * % *x Section 3 !! Section 3 !! Section 3 !!
Section 3 !! Section 3 !! Section 3 !! Section 3 !! Section 3 !! Section 3 !!
Notes:
* Vector actually used by ROM. ** Texas Instruments use only - not to be changed.
Texas Instruments Incorporated pubfication ! Intel Incorporated publication ! This manual
TECHNICAL REFERENCE
DEVICE SERVICE ROUTINES
Table 4-1 System Interrupt Vector Usage (Concluded)
Vector
Description
Reference
60* 61% 62% 63% 64% 6S5* 66%
67%
68-9F AC-DF EO-E3
System ROM
DS pointer
(F400:A000)
DS size in bytes
Factory ROM DS pointer
(F400:0000)
DS size in bytes
Option ROM
DS pointer
(F400:2000)
DS size in bytes
Option ROM
DS pointer
(F400:4000)
DS size in bytes
Option ROM
DS pointer
(F400:6000) Option ROM
DS size in bytes DS pointer
(F400:8000)
DS size in bytes
Memory size in paragraphs
Outstanding interrupt count
Installed drive types
Extra system configuration
(word 1)
Extra system configuration
(word 2)
Reserved for Texas Instruments
User interrupt vectors
Reserved for CP/M {tm]
(180H) (182H) (184H)
(186H) (188H) (18BAH) (18CH) (18EH) {190H) (152H) (194H) (196H) (198H) (word) (19AH)(byte) (19BH) (byte)
Section Section Section
Section Section Section Section Section Section Section Section Section Section Section Section
3 !! 3 !! 3 !!
3 !! 3 !! 3 !! 3 !! 3 !! 3 !!
3 !!
3 !! 3 !! 3 !! 3 !! 3 !!
{19CH)
Section 3 !!
(19EH)
Section 3 !
CP/M 86 Progpammer's Guide @
E4-FF
«
Reserved for Texas `Instruments
Notes: * Vector actually
* % Texas Instruments e Texas Instruments f Intel Incoporated
1! This manual
used by RONM. use only - not to be changed. Incorporated publication publication
4.3.1
Hardware Interrupt Service Routines
All
standard
interrupt service routines (ISR) have limited internal
stacks.
They provide four levels (B bytes),
which
is the amount
required
by any application
program
or subroutine that runs with
interrupts enabled.
An ISR needs 8 bytes
of
the
wuser's
stack;
2
bytes
to push
the
wuser's
code
segment
(CS),
2 bytes
for the
instruction pointer (IP), 2 bytes for flags, and 2 bytes to push
the
data
segment (DS).
The ISR saves the user's stack segment and stack
pointer in the RAM data area of the system ROM.
The ISR then changes
the stack segment and
stack
pointer
so
that
they point
to the
internal
stack
of the interrupt routine.
W®hen the ISR is complete,
it executes a long jump to the common interrupt exit vector.
TECHNICAL REFERENCE
DEVICE SERVICE ROUTINES
4.3.2
Common Interrupt Exit Vector
All ISRs (in the ROM and in Texas Instruments applications
programs)
use a common
interrupt
exit vector.
The ISR executes a long jump
(LONG JMP) to the routine pointed out by the common
interrupt
exit
vector.
The common
interrupt
exit routine restores the stack and
commonly used registers, decrements the outstanding interrupt counter
(INTCTR), sends the end-of-interrupt (EOI) command to the interrupt
controller,
and
returns to the interrupted code with a return-from-
interrupt instruction (IRET).
A real-time operating system (0S),
communication
programs,
uses
the
outstanding interrupts.
Be sure to
creating an ISR.
such as
the O0S kernel
of TI
INTCTR
to keep
track
of
the
include the appropriate code when
A sample interrupt service routine,
with
installation
and
removal
instructions, is included in Appendix G.
The
common interrupt exit routine is contained in ROM, but an OS can
patch it so that all interrupt
service
routines
exit
through
the
operating system.
Because the interrupt structure is complex (due to
interaction
between
the shared interrupts and the requiremenfotr a
common exit point), the potential
wuser should
read
the following
paragraphs, carefully studying the examples given.
4.3.3 «
Timer Interrupts
*
The
system
timer
ticks
every
25 ms.
The ISR for this timer is
located in the ROM, and it processes events such as disk motor
time-
outs and date/time-keeping.
Software interrupts are performed at two
points
during this interrupt service routine, allowing access to the
timing services.
One interrupt occurs every count (every 25 ms), and
the other occurs every
four
counts
(100-ms
intervals).
UYsually,
these interrupt vectors point to an IRET instruction in the ROM.
The
user
can
patch
one
or
both
of
the
vectors to point to his own
routines.
These routines are free to use the AX,
BX,
DI,
and ES
registers,
but
they must
preserve
any other registers used.
The
stack used is the internal
stack
of
the .timer
interrupt
service
routine
and
it is limited in depth.
If the user does not re-enable
interrupts (the INT instruction disabled them), there
are
8 levels
(16 bytes) of stack available.
If the interrupts are re-enabled, the
user has only four levels (8 bytes) available.
If more stack size is
required, the user should switch to an internal stack of the required
size (allotting 8 bytes for higher priority interrupts).
It
is
important
to remember
that
the routines installed in this
manner are executing at the interrubt level.
Interrupts must not
be
disabled
for
any significant length of time, because any time spent
in these routines directly affects system efficiency.
The user must
also
understand
how some other mechanism (such as a timing event in
the handler routine of the OS)
can
patch
the
timing
vectors
ang
install
itz
own routines.
Instead of using the IRET instruction to
TECHNICAL REFERENCE
DEVICE SERVICE ROUTINES
end the routine, make a long jump
to
the
original
(which was saved when the routine was installed.)
vector
address
4.4 ROM STRUCTURE
The
following
paragraphs
describe
sequences for optional ROMs.
the wuse,
format,
and calling
4.4.1
ROM Usage
Optional ROMs provide an interface
between
the hardware
and
the
system
software.
With this interface installed, modification of the
hardware requires changing only the ROM software,
not
all
of
the
applications programs.
The
system
system ROM.
board)
for
which can be
defines
locations
for
six ROMs.
One of these is the
Texas Instruments has
reserved
another
(on
the
main
future
use.
The four remaining are the optional ROMs,
used by any of the available operating systems.
Table 4-2 shows the ROM addresses and suggestions for their use.
Table 4-2 ROM Addresses and Suggested Uses
é.
Absolute
Address
Cs:Offset
F4000H
F400:0000H
F6000H
F400:2000H
FB80O0O0H FAOOOH
FCCOOH
F400:4000H F400:6000H
F400:8000H
FEOOOH
F400:ACO00H
Use
Miscellaneous I1/0 option
Local area network
Mass storage Oopen System ROM
expansion System ROM
Comments
Reserved for Texas Instruments
Reserved for Texas Instruments Texas Instruments Winchester card Oopen
Reserved Reserved
for Texas for Texas
Instruments Instruments
4.4.2
ROM Format
The ROM format must be known to:
* Identify the ROM
* Use a standard calling sequence
* Use the diagnostics
. "TECHNICAL -
REFERENCE
DEVICE SERVICE ROUTINES
e
ROMs can be one of the following sizes:
* 256 bytes
.
* 512 bytes
* 1024 bytes
L
* 2048 bytes
* 40896 bytes
* B192 bytes
The ROM size, word value is convention.
in binary, stored low
is stored in the first word in the ROM.
The
byte first, following the INTEL Corporation
The
second
word
in
the
option ROM is the power-up initialization
address.
The system ROM uses a NEAR call to this address during
the
power-up
process,
The
user must
ensure
that the initialization
address is calculated as an offset from the segment address F400.
The next location
ROM.
The
first
(1 byte).
This
displayed.
in the ROM stores a text
string
identifying the
entry
in
this string is the length of the string
information
determines
how
much
material
is
The rest of the string consists of a five-character version number, a
space
character,
a six-character
name,
and any descriptive text
(copyright, for example) that the vendor requires:
The option ROM code and fixed data (in a format
determined
by
the
vendor) follows the text string.
The
last word in the ROM stores the cyclic redundancy check (CRC-16)
remainder from all the previous bytes in the RONM.
Both the power-up
test
and
the advanced diagnostics test read this word to see if the
ROM is working properly.
The CRC-16 routine, available in the system
ROM, calculates this remainder.
When the CRC remainder is correctly
placed,
running
the CRC~16 routine through the entire length of the
ROM (including the CRC) results in a zero remainder.
The CRC-16
routine available in the system ROM calculates the remainder.
4.4.3 Option ROM Interrupt Vector Usage
The
system ROM uses interrupt vector locations in the first 1K bytes
of RAM for hardware interrupts, interface to the ROM functions,
and
other ISRs.
See paragraph 4.3.1 for more information.
Interrupt
vectors
access
the option ROM entry points.
The option
software can use the vectors above 80H (vector address 200H).
TECHNICAL REFERENCE
-
¥
DEVICE SERVICE ROUTINES
NOTE
Conflicting chtor
assignments
can
loss
or
data errors.
Be extremely
making these assignments.
cause careful
data when
4.4.4
RAM Usage by Option ROM
Each ROM has a separate RAfi.data area' assigned
to
it.
These
data
areas
float; therefore, the ROM does not require a dedicated area in
RAHM.
Copying the data area and updating the pointer moves
the data
area.
The ROM accesses these data areas using the pointers and sizes
in
the
interrupt vector area, so that moving the data area does not
affect the ROM.
The ROM initializes the pointers and data
areas
at
boot~up
time,
so the system ROM data area pointer is the only one
used.
All option ROMs are addressed at absolute
segment
addresses
F400H,
with an offset
from 0000 to AOOOH.
The ROM code is linked so that
its code segment is F400H.
This code
segment
was chosen
so `that
option ROMs can be addressed with the same code segment as the system
ROM.
This
enables
the option ROM to access the ROM powverup entry
routines as NEAR instead of FAR.
The first location
of
the
system
ROM, described in segment:offset notation, is F400:A090.
There
is another
advantage
to linking
the ROMs . this way.
The
interrupt vector area at location 0000:0000 is now also accessable as
F400:C000.
This simplifies slightly the code sequence used to assign
a local data area.
4.4.5
Initializing the Option ROM
The power-up sequence executed by the main ROM tests each option ROM
address in sequence.
Address OF400:0000H is tested first and address
OF400:8000H
(the main board option ROM) is tested last.
When a ROM
is found, the diagnostics performs a CRC-16 calculation.
The
system
displays an error message if the ROM is bad.
If the ROM is good, the
system initializes the option ROM.
The initialization code saves the
BX, DX.
SI, SP, CS, Ss, and DS registers so that using a NEAR return
instruction returns control to the system ROM.
4.5
BOOTING UP THE SYSTEM
.
Most
system
software
is contained
in some mass-storage
system
(diskette, Winchester disk, or local network server).
The user must
be able to find and load the system software from these devices.
The
Texas
Instruments
Professional
Computer
loads
a single sector of
program information from a known point on the specified device.
The
TECHNICAL REFERENCE
DEVICE SERVICE ROUTINES
. 't
system
then
calls
the code that was loaded, which
rest of the programs.
i
The
location
loaded
at
available.
For diskettes
cylinder (track) 0, surface
start at 1.)
power-up
is
the
1lowest
and Winchester
disks,
(side) 0, and sector 1.
"bootstraps" the
logical
sector
this location is
(Sector
numbers
4.5.1
Boot Sequence
The options installed in the system determine the boot sequence,
The
sequence proceeds
starts at the highest-priority option address (OGF400:0000H), to the lowest (OF400:8000H), then boots the diskette system.
The boot sequence is:
1. Local Area Network (LAN)
2. Winchester disk subsystem
3. Diskette drive A
4. Diskette drive B
S. Diskette drive C
6. Diskette drive D
5
«
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4.5.2
Loading and Calling the Boot Code
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TECHNICAL REFERENCE
i ;?
DEVICE SERVICE ROUTINES
which the system boots is placed in register BL.
Before
loading
the operating
required initializations such as
(single
or double sided, 40 or
Winchester drive.
{(The DSR must
for further loading.)
system, the boot code performs other
setting up the type of
floppy
disk
80 track), or setting up the type of
be able to recognize the disk format
The boot code then loads any system files needed by the 0S and
jumps
to the O0S code.
If the OS requires RAM where the system ROMs are
using it, the RAM data areas used by
the
ROM
can
be
moved.
The
pointers
to the RAM segments must be modified accordingly.
If a ROM
is not using a RAM data area, its pointer is 0000.
This pointer must
remain zero even if the area is moved.
Table 4-3 gives the addresses
of these pointers.
Table 4-3 Pointer addresses and Descriptions
Address Pointer Description ROM Address
00600:0180 0000:0182
System System
ROM data ROM data
segment pointer length in bytes
0000:0184 0000:0186
Option ROM data segment pointer Option ROM data length in bytes
0000:0188 0000:018A
Option ROM data segment pointer Option ROM data length in bytes
0000:018C 0000:018E
Option ROM data segment pointer Option ROM data length in bytes
0000:0190 00600:0192
Option ROM data segment pointer Option ROM data length in bytes
0000:0194 0000:0196
Option ROM data segment pointer Option ROM data length in bytes
F400:A000
F4oo:gooo 3
F400:2000
F400:4000
F400:6000
F400:8000
If any errors occur during the loading and initializing
of the Os,
the Dboot
code returns to the caller.
The registers BX, ES, CS, and
the stack must be preserved.
unless
the
ROM
data areas
The
register
DS must
bDe preserved
are moved.
If the data areas are moved,
adjust the DS register
by
the
amount
of
difference
Dbetween
the
original
position and the new position.
A DSR error code returns to
the caller displayed
as & system
error
message.
This
code
is
presented in register AH.
Appendix
H gives
boot sector.
a sample source program that could be used in the
TECHNICAL REFERENCE
DEVICE SERVICE ROUTINES
4.5.3
Booting From an Option Device
When an option device is to be booted up, it maust
be
the
1last
one
called called
in and
the power-up seguence.
Otherwise, othér options must be
initialized during the boot sequence.
Appendix G contains
a sample assembly code showing the boot seguence.
If more than one bootable option
must
have
the DX register set
is present to OFFFFH.
in the system,
each
The bootable option
one then
calls all lower priority ROMs in the system.
Any ROM called in
this
manner
performs
all
reguired
initialization
except
for booting.
Because the system ROM sets the DX register to 0OCO0OH when
it calls
the
option
ROMs, an option device will boot if called by the system
ROM, but not if called by another ROM.
If booting appropriate BX, DX, SI, options. Floppy Disk
from an option
device
fails,
error
messages and returns to
and DS intact.
The
system
ROM
If none
of
the
options
boot,
system.
the ROM displays
the
the caller with registers
then
calls
the other
the system ROM boots the
This procedure can causgse multiple
initializations
of
the
However,
no
harm
results,
Entering
the
warm
boot
(CTRL/ALT/DEL)
from
the
keyboard
also
causes
initializations.
options. seguence multiple
4.6
SYSTEM CONFIGURATION FUNCTION CALLS
«
The
following
paragraphs
describe
the
types of system configuration information,
function calls which are:
for
the two
* Function calls that return the
information
(System Configuration Function)
in a register
* Function
calls
that
return the address of the information
(Extra System Configuration Function)
The first type, System Configuration Function, returns
most
of
the
information
required
for
application
programs.
Extra System
Configuration Function, the second type, is intended for use
at
the
system level.
This method contains additional information usable for
changing the configuration of devices set by software.
4.6.1
System Configuration Function
This function is used to determine the installation status of certain
system options.
It is invoked by executing an INT 4FH instruction.
Upon
return,
register
BX contains
the size of
(starting at 00000H) in paragraphs
(16-byte blocks).
system, for example, would return 2000H in BX.
«contiguous
RAM
A 128K-byte
TECHNICAfi L REFERENCE
DEVICE SERVICE ROUTINES
Register
AX contains
the system
the installation status of various
word are defined in Table 4-4.
configuration word, which
system options.
The bits
reflects of the
Table 4-4 System Configuration Word-Bit Definition
Bit
Definition
ox
Diskette drive 0 (internal) installed
1
Diskette drive 1 (internal) installed
2
Diskette drive 2 (external) installed
3
Diskette drive 3 (external) installed
4
E1-E2 jumper (O indicates Drive A is double-sided)
S
E3-E4 jumper (0 indicates Drive A has 80 tracks)
6
ES-E6 jumper (0 indicates a SO0-Hz system)
7
Winchester disk controller installed
8
Serial port 1 installed
]
Serial port 2 installed
10
Serial port 3 installed
11
Serial port 4 installed
12
Graphics RAM bank A installed
13
Graphics RAM bank B installed
14
Graphics RAM bank C installed
is
Reserved
* Bit
O is the least-significant bit.
Unless othetwise stated, a
statement is true when its corresponding bit is a 1. <
Y
4.6.2
Extra System Configuration Function
This function determines the installation status
of
system
options
that
are
not
covered
in
the
standard system configuration call.
Hhereas
the
standard
system
configuration
call
returns
a word
containing the information necessary for most applications, the extra
system
configuration
function
is used primarily
for
systems
programming purposes.
The extra system configuration function is invoked by placing
a O0BH
in register AH and executing an INTerrupt 48H.
Upon return, register
AL contains the drive-type byte (AH is undefined).
BX contains extra
system
configuration
word
1%
and CX contains
extra
system
configuration word 2.
The bits of extra system configuration word
1
are defined in Table 4-5.
-
TECHNICAL REFERENCE
:
DEVICE SERVICE ROUTINES
Table 4-5
Bit
Extra System
pefinftion
Configuration
Word
1 (BX)
ox
8087 numeric coprocessor is installed
1
\
2
|
3
|
4
>
Reserved
s
|
6
i
7
/
8
300/1200 baud modem in port 1
9
300/1200 baud modem in port 2
10
300/1200 baud modem in port 3
11
300/1200 baud modem in port 4
12
300 baud modem in port 1
13
300 baud modem in port 2
14
300 baud modem in port 3
1s
300 baud modem in port 4
Bit
©0
stated,
1.
is the least-significant
bit,
Unless
a statement is true when its corresponding
s
otherwise
bit is
a
Word
2 of the Extra System Configuration function call is contained
in CX.
This word is currently undefined, and is being
reserved
for
later expansion.
TECHNICAL REFERENCE
DEVICE SERVICE ROUTINES
The drive-type
byte defines
the
types
of the installed diskette
drives.
This information, combined with the "installed
drive"
bits
in
the
standard
system
configuration
word,
yields
complete
information about the drives in the system.
At power-up, the drive A
definition jumpers (Ei - E2 and E3 - E4) are read.
The
information
is stored in memory as a byte of four identical, 2-bit fields.
This
byte is read
during
the extra
configuration
function
«call and
returned
in register
AL.
The
drive
byte
(in AL) is the 2-bit "
configuration code for all four of
the
diskette
drives,
which
is
shown in Figure 4-1.
7
6
Drive D
5
4
Drive C
3
2
Drive B
1
0
Drive A
Each 2-bit field is defined as:
MSB* LSB
Definition
*MSB
0
0
=
Single-sided
0
1
= Double-sided
1
0
= Single-sided
1
1
=
Double-sided
= Most significant bit; LSB = Least significant bit. .
-~
40 track 40 track 80 track 80 track
zrnen
Figure 4-1 Register AL Drive Byte
The
operating
diskette files.
system
uses this drive byte
It is possible to mix drive
to format, copy, and use types in one system (for
example, one single-sided and one double-sided drive) by setting
the
drive-type
byte with
the pertinent
information; but, this is not
recommended.
Mixed-drive
type
systems
are
confusing.
Users
frequently insert the wrong diskettes, thereby losing data.
4.6.3
Get Pointer to System Configuration
This
function
is invoked
by placing
a O09H in register AH and
executing an BX contains (hereafter,
interrupt 48H.
on return, ES contains
the
offset
of
the standard system
the notation for this is ES:BX).
This
the segment,
configuration
function
is
and word wused
by system
software
that has
a need
information.
Although
an
application
to change the configuration
program
can
access
the
information in this manner, the configuration must not be changed.
TECHNICAL REFERENCE
DEVICE SERVICE ROUTINES
4.6.4 g:t Pointer to Extra System Configuration
This
function
1is invoked
by
placing
a OAH
in
register
executing an INTerrupt 48H.
On return, ES:BX
points
to the
system configuration information, formatted as follows:
AH and extra
ES:[BX-3}=(word) ES:{BX+0]=(byte) ES:{BX+1]}=(word) ES:[BX+3]=(word)
Size of memory in 16-byte blocks Drive-type byte Extra system configuration word 1 Extra system configuration word 2
This
function
is wused by system software
the configuration information.
Although an
access
the information in this manner, the
changed.
that has a need to change
application
program
can
configuration must not be
4.7 GENERAL-PURPOSE ROM FUNCTIONS
The following paragraphs
describe
some
summarize
the ROM interface interrupts,
the ROM.
general-purpose
functions,
and explain how the RAM uses
4.7.1
Delay
s
This function causes a delay, in milliseconds, of the value placed in
register CX.
To invoke the function, place the delay
value
in CX,
OSH in AH, and execute an INT 48H.
The delay is approximate, but can
be
wused
wherever
an
inexact
software
delay
is acceptable.
All
registers except CX are preserved.
4.7.2
CRC Calculation
This function calculates the cyclic redundancy check
(CRC~16)
value
for
a specified
block
of memory.
It
is invoked by placing the
address of the memory block in ES:BX, the size of the
block
in BP,
and
the value
O06H in AH, then executing an INT 48H.
On return, DX
contains the CRC value; if DX=0000, the Z-flag is
set.
For memory
blocks
that
follow the convention of the CRC being the last word in
the block, this routine allows easy CRC checking.
First, the CRC of
the memory block is calculated, with the size of the block set to the
actual size minus two.
The CRC word is then written to the last word
of
the block.
Subsequently, the CRC of this block can be checked by
calling this function with
the actual
size
of
the
memory
Dblock
(including
the previously
calculated CRC).
By definition, the CRC
result of this block is zero (if the CRC matches the data) and the z-
flag is set; otherwise, the CRC fails and the Z-flag is
reset.
All
registers are used except DI, SI, and DS.
ES remains unchanged.
4-17
TECHNICAL REFERENCE
DEVICE SERVICE ROUTINES
4.7.3
Print ROM Message
This
function
displays a ROM CS-relative message.
placing the offset of the zero-terminated message in
and
executing an INT 48H.
This function is used by
because all the ROMs share a common CS.
It is not a
routine.
it is invoked by
SI, 07H
in AH,
the option ROMs,
general-purpose
4.7.4
Display System Error Code
This
function
format:
is used
to display
a system error in the standard
*% System Error*kx - xxxXx
It is invoked by placing the error
displayed
message
above)
in BX,
executing an INT 4BH.
code
{(the xxxx value
in the
placing the value 08H in AH, and
4.8 SPEAKER DSR
The following paragraphs describe the speaker DSR and
the
functions
it provides
to the system or application programs that use it.
The
functions are:
)
* Sound the Speaker
* Get Speaker Status
TM
* Set Speaker Frequency
* Speaker ON
* Speaker OFF
The speaker DSR functions are located
in
the
system
ROM
and
are
accessed
through
the
software
interrupt
mechanism
of
the
8088
microprocessor.
The desired function is chosen by placing an
opcode
in
register
AH and executing an INT 48H instruction.
All registers
are preserved except AX.
4.8.1
Sound the Speaker - AH = O
This function turns the speaker on (at the current frequency) for the
length of time specified in register AL.
Time is measured
in 2S-ms
increments.
For
example, a value of 40 in AL causes the speaker to
sound for 1 second.
Timing is handled in the ROM with
the
result
that
the
reguest
turns
on
the
speaker,
starts
the
timer, and
immediately returns to the user.
The sound continues until timed out
by the ROM code.
Because this function
<c¢all
occurs
asynchronously
TECHNICAL REFERENCE
DEVICE SERVICE ROUTINES
with the 25-ms system timer, the time can be "off"" by as much as 25
ms.
For example, specifying a single 25-ms unit of
time
can cause
the speaker to sound for a period of 0 to 25 ms.
If there is need to
synchronize
with
the
sound
or simply to know when sound is turned
off, use the Get Speaker Status (AH=1i) function.
4.8.2 Get Speaker Status
- AH = 1
This function returns the status of the speaker in
the
Z-flag.
If
the speaker is currently enabled (sound), the Z-flag is set at 0.
If
the speaker is currently disabled (no sound), the Z-flag is set at 1.
This function can be used to find out when a sound requested with the
Sound the Speaker (AH=0) function has been completed.
4.8.3
Set Speaker Freguency
=~ AH = 2
This
function
sets
the
frequency
of
the
speaker.
Usually this
function is called only when the speaker is disabled.
The value
ir
CX sets
the frequency
of
the timer that drives the speaker.
The
input frequency of the timer is 1.25 MHz, and the value in CX becomes
a divider for this frequency.
For example, the system
beep
routine
(800 Hz) uses a value of 1563 (1 250 000 Hz / 1563 = 800 Hz).
4.8.4 Speaker ON - AH = 3
This
function enables the speaker (turns on
remains on until it is turned off by either
(1) the Speaker OFF (AH=4) function or
s
the sound).
-
The speaker
(2) by the ROM timing routine, which results from
either
the Speaker (AH=0) function or a normal system beep.
the Sound
4.8.5
Speaker OFF
- AH = 4
This
function performs the reverse of the Speaker ON (AH=3) function
by disabling the speaker (turning off the sound).
TECHNICAL REFERENCE
DEVICE SERVICE ROUTINES
4.9 TIME-OF-DAY CLOCK DSR
The following paragraphs describe the time-of-day clock DSR and
the
functions
it provides to the system or application programs that use
it.
The functions are:
* Set the date
* Set the time
* Get the date and time
The clock DSR consists of routines to set and read the
time
of day
and date
information kept by the timing services of the system ROM.
At power-up, the time is set to 00:00:00.00, and the date is set
to
0000.
These can be reset by system or user programs.
Once set with
a valid time,
the clock keeps
the correct
time with a 1/10-s
resolution.
The
time
is Xxept
in 24-hour format and the date is
simply a cumulative count of days since
matter
of convenience
(for MS-DOS),
the clock was started.
As a
the date is specified as the
number of days since January 1, 1880.
For example,
the
date
value
for September 10, 1982, is 983.
The
three
clock
functions
are
1located
in the system ROM and are
accessed
through
the software
interrupt
mechanism `of
the
8088
microprocessor.
The desired function is chosen by placing an opcode
in register AH and executing an INT 4EH instruction.
All registers
are preserved except AX and any other registers in which information
is returned.
4.9.1
Set the Date
=~ AH = 0O
This function sets the date to the value in the BX register.
The
date
is simply a count
of days since the clock was started.
8y
convention, this is the number of days since 1-1-80.
The
count
is
incremented when the hour rolls over from 23 to 00.
4.9.2
Set the Time
- AH = 1
To set the time, the registers must be initialized as follows:
CH = Hours (00 - 23)
CL = Minutes (00 - S3)
DH = Seconds (00 - S9) DL = Hundredths of seconds
.
(00 - 99)
It
is
the
wuser's responsibility to make sure the values passed are
within the ranges specified.
These values are not checked for
range
and
can
be set to represent a meaningless time.
The time, however,
TECHNICAL REFERENCE
DEVICE SERVICE ROUTINES
eventually -
4.9.3 Get
counts .
into
the normal
seguence.
the Date and Time
- AH = 2
This time
function returns the current date in registers CX/DX in the formats
in register AX and the described previously.
current
4.10 CRT DSR
The following paragraphs describe the CRT
provides
to
the
system
or application
major
functions
are
(1)
video
mode
handling.
DSR and
the
programs that
control
and
functions
it
use it.
The
(2)
character
For
information
about
2.4.7, and to subsection
the
system ROM and are
the CRT graphics hardware, refer
3.5.
The CRT DSR functions are
accessed through the use of the
to paragraph
located
in
8088 software
interrupt mechanism
call).
A typical
interface code (the
(essentially
an address-independent
subroutine
wuser
of
this
DSR
is
the OS-dependent sygstem
BIOS), which resides on a particular O0S disk and
is loaded
into
RAM during
disk boot up.
chosen by placing an opcode in register
AH.
The desired function is
The
CRT
opcodes
and
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TECHNICAL REFERENCE
DEVICE SERVICE ROUTINES
Table 4-6 CRT DSR Opcodes and Functions
Function
(Null function)
Set cursor type
Set cursor position
Read cursor position (Null function)
(Null function)
Scroll text block
Scroll text block
Read character and attribute at current cursor position
Write character and attribute at current cursor position
Write character only at current cursor position
(Kull function)
{Null function)
(Null function)
Write ASCII teletype
{Null function)
Write block of characters at current cursor with attribute
Hrite block of characters only at current cursor
Set entire screen to specified attribute(s)
Clear text screen and home the cursor
Clear graphics screen
T
Set TTY status line beginning
:
Set attribute latch to specified attribute(s)
Read physical display begin pointer
_
Print TTY string
TECHNICAL REFERENCE
DEVICE SERVICE ROUTINES
4.10.1
Set Cursor Type - AH = OlH
This function allows an application to define the
scan
line for the cursor and its characteristics
no cursor).
Required input for this function is
4-2,
starting (either described
and ending blinking or
in Figure
CH = 7
6
5
4
3
2
1
0
Byte1
Start scan line of cursor
Cursor type: 00 = no blink 01 = no cursor 10 = fast blink 11 = slow blink
Not used
CL =
7
6
5
4
3
2
1
0
Byte2
*
End scan line of cursor
Bits 7 through 5 not used
(Valid values for scan line are 0 through 11 decimal.)
223216-23
Figure 4-2 Byte Definition - Set Cursor Type
TECHNICAL REFERENCE.:
DEVICE SERVICE ROUTINES
4.10.2
Set Cursor Position - AH = O2H
NOTE
The user should be aware that screen coordinates
use the 0,0 coordinate
as
the
wupper
left-hand
corner of the display.
All routines that require
a coordinate parameter use this convention.
The
screen should look to the user as though he were
working
with
the absolute
value
of fourth-
guadrant
coordinates
of
a
tvo-dimensional
coordinate system,
This
function
causes
the cursor (of the current type) to be set at
the specified x,y (column/row) coordinate of the display.
Required input for this function is as follows:
DH = x
Column coordinate (valid values are
0 through
79 decimal.)
DL = y
Row coordinate
.
{Valid values are 0 through 24 decimal.)
+
4.10.3
Read Cursor Position - AH = O3H
o
This function returns the current position and type
of
the
Output from the read cursor position routine is as follows:
cursor.
DH, DL = x, y f{column/row) location of the cursor
CH, CL = current cursor type
Refer CL.
to paragraph
4.10.1
for an explanation
of the values
for CH and
The
"phantom""
position of the cursor in column Bl creates a special
situation in reading the cursor postion.
If a character
is written
in the last column of the screen by a TTY write, it can be read, even
though it is not visible.
This position, column 81 of the last line,
becomes
visible
after
another
character is written and the screen
scrolls.
The position returns as column 0, rov 25. This is invalid
input to the Set Cursor Position (AH=02H) routine.
See paragraph 4.10.18 for additional information on the cursor.
TECHNICAL REFERENCE
DEVICE SERVICE ROUTINES
4.10.4
Scroll Text Block - AH = 06H and O7H
The
ROM
contains
only
one
general-purpose
scroll routine, which
handles both upward and
coordinates
are less
and to the left; when
the source coordinates,
downward
scrolling.
When
the destination
than the source coordinates, the scroll is up
the destination coordinates
are greater
than
the scroll is down and to the right.
The
scrolling
functions
allow
block of text, then move or copy
the screen.
Specifying a scroll
an application program to specify a
that block to another
location
on
with blanking causes the source text
bllsctttohlhoopheeacceanaacrkttiadbeiifceadsooitt.onneeau..drr.bclbeaeinisTnkhTTgeihhadrsienesndamdopvrmaesoeddtvthetiheosodtdeiitsonracahstaafiirsotcotraionecspmtfipmaeieoordervsnleaoodrcn.yadbittesehiesotrnrepsrDrugrueecireqwtsisuraitneiirvgeretrervteeemdnetthhmneiotasvnedsitnoaptmrhieaonitcti,iesttatsssnhsde,inlodbdecvleesteaasshcntenttrtikiiooinnlnsnaalogtituniitrhgooca,nneiitss
Required input for this function is as follows:
" nouwon o
AL
0 (Blank out source text.
This is a move block.)
or
AL = >0 (Don't blank source text.
This is;a copy block.)
(fiH,DL) (BH,BL)
Source begin column/row location -
= Destination begin column/row location
CH
Column length of block
(valid values are 1 through 80 decimal.)
CL = Line length of block (Valid values are 1 through 25 decimal.)
The source text block boundaries in (x,y) coordinates are as follows:
Upper Upper Lower
Lower
left right left
right
(DH,DL) (BH + CH , BL) (DH , DL + CL) (DH +«+ CH , DL + CL)
TECHNICAL REFERENCE
DEVICE SERVICE ROUTINES
The following
items
further
describe
explain the segquence of operation.
the
scrolling routines and
* A sentence is considered the smallest logical block of text.
Therefore, with this
scrolling
capability,
the wuser can
specify
a block
to be a sentence.
This may (or may not)
wrap to a new line and "unwrap" as it is moved
(or copied)
to
its
destination
(that
is, the column length parameter
would bypass line boundaries and pick up characters from the
next line).
The wuser
should
note
that
this
is quite
effective
wvhen the 1line length is equal to one but might
cause unwanted block movement if the line length is greater
than one.
* Boundary
checking
for
the
scrolling routine is done on a
character basis as the characters are being moved.
When
a
scroll
down
is
in progress,
the
=croll copies the last
character in the source block to the last character position
in
the
destination
block.
The processing
is backwvard
through
the Dblocks while checking character positions for
out-of-bound characters.
This means that in the scroll-down
action, no scroll takes place if any
destination
position
lies
beyond
the end of the screen.
Asymmetrically, when a
scroll up is in progress,
the
scroll
copies
the first
character
in
the
source
block
to the first
character
position in the destination
block.
The
scroll
proceeds
forward,
through
the blocks,
while
checking
character
positions for out-of-bound
characters.
In
the
scroll-up
action,
the
scroll
takes place until it reaches a source
character position that lies beyond the end of the screen.
* When the user requests scrolling with blanking,
the
status
of the attribute latch at entry is preserved.
The character
attributes
follow
the character
as
it is moved on the
screen, and the blanked area is
written
with
the default
attributes
(that
is,
high
intensity
for a monochrome
monitor, and white for a color monitor).
* HWhen the wuser requests
scrolling
without
blanking,
the
attribute
latch
is set to the same status as the attribute
of the last
character
that
was
scrolled
(that
is,
the
attribute
of
the first character of the source block when
scrolling down, or the attribute of the 1last character
of
the source block vhen scrolling up).
TECHNICAL REFERENCE
DEVICE SERVICE ROUTINES
4.10.5
Read Character/Attribute at Cursor Position ~ AH = O8H
This
function
returns a character and its associated
the current cursor position on the screen as follows.
4.10.15
for attribute
values
and a description of
supported.
attribute from See paragraph the attributes
AH
n
Attribute value
AL = Character read
NOTE The attribute latch remains set to the that is returned.
attribute
4.10.6
Write Character/Attribute at Cursor Position - AH = 09H
This
function
enables
the writing
of a character with the given
attribute at the current
cursor
position.
(The attribute
1latch
remains set to the attridbute specified in register BL.)
The user can
specify
a count and cause the character to be writtenca given number
of times starting at the cursor's current
position.
This
function
does
not
increment the cursor automatically, and the cursor remains
at
its
current
position
while
the characters
are written
in
succession from that location.
If an application uses this method of
writing
characters,
it is assumed that the application also handles
the
cursor
positioning.
Therefore,
no
cursor
movement
is
implemented.
Control characters (CR,LF, and so on) are not executed
as such when using this function; their symbols are
printed
on
the
display.
For more information, refer to paragraph 4.10.15,
The required input for this function is as follows:
AL = Character to write
BL = Attribute of character(s)
CX = Number of times to write the character
TECHNICAL REFERENCE
DEVICE SERVICE ROUTINES
4.10.7
MWrite Character at Cursor Position - AH = OAH
This
function
is similar
is that the character being
in the attribute latch from
refer to paragraph 4.10.6.
to the preceding function.
The difference
written takes on the attributes remaining
the last CRT call.
For more information,
The required input for this function is as follows:
AL
Character to write
cX
1
Number of times to write the character
4.10.8
HKHrite ASCII Teletype - AH = OEH
This function allows
TTY output
to
the
screen
from application
programs.
Writing
begins
at
the current cursor position, and the
cursor is advanced automatically to its next position on the screen.
For more
information,
refer
to paragraph 4.10.18.
The screen is
scrolled automatically when needed (such as writing past the end of
the screen).
The control characters CR, LF, BS, and BEL are executed
rather than written.
NOTE
=
:
If a status
region
is currently
in use, the
scroll starts one line before
the beginning
of
the
status
region, exactly as if that line were
the end of the screen.
Because the contents of the attribute latch
remain
character
written
with
this function assumes the
previously written character.
-
unchanged, attributes
each of the
The required input for this function is as follows:
AL = Character to write
TECHNICAL REFERENCE
DEVICE SERVICE ROUTINES
4.10.9
Hrite Block of Characters at Cursor With Attribute - AH=10H
This function writes a given block of data with a specified attribute
to the
screen,
starting
at
the
current
cursor position.
This
function
reqguires less screen I/0 overhead if an application program
has a ""known" block of data to be written to the screen.
"Known"
means
that
the
block
is
of
a
given
1length,
and is in a given
contiguous area of memory.
As with the Write/Character Attridbute
at
Cursor
Position
function,
the
cursor
is not automatically
incremented.
For more information, see paragraph 4.10.1S.
The required input for this function is as follows:
AL = Attribute(s) of characters *
DX = Segment location of character block
BX = Offset location of character block
CX = Block length *x*
4.10.10
Hrite Block of Characters Only at Cursor Position - AH=s11lH
This
function
is similar
to
the
preceding
difference that
the attribute
parameter
is
characters
assume
the attribute(s) remaining
from the last CRT call.
funqgtion,
with
not
specified.
in the attribute
*
the The latch
The required input for this function is as follows:
AL = Don't care
.
DX
Segment location of character block
BX = Offset location of character block
CX = Block length *x
%
The attribute(s) specified is in effect for the entire
block and the attribute latch remains set to the attribute
specified in register AL.
*x
This routine "clips" any characters that do not fit on the
screen,
Characters are written to the end of the screen, then
all other characters are lost/not written.
To prevent losing
characters, the user should place the cursor so that the
number of character positions from the cursor to the end of
the screen is greater than or equal to the block length.
TECHNICAL REFERENCE
DEVICE SERVICE ROUTINES
4.10.11
Change Screen Attribute(s) - AH = 12H
This
function
specifies
attribute(s)
that
affect
all
of
the
characters
on the display.
The attribute
latch
is set to the
attribute specified in register AL on exit.
This
routine
does
not
change
the position
of any characters on the screen.
Two examples
are blinking of the entire screen and reverse
video
of
the
entire
screen.
For more information, see paragraph 4.10.1S.
The required input for this function is as follows:
AL = Attribute(s) to use
4.10.12
C(Clear Text Screen and Home the Cursor - AH = 13H
This
routine clears the text screen and sends the cursor to the home
position (0,0 coordinates).
NOTE
This function ""erases"" any data contained
status
region
but
leaves
the
status
implementation in effect.
in the region
<
»
The required input for this function is as follows:
AH = 13H (function number)
4.10.13
Clear Graphics Screen(s) - AH = 14H
This function clears the graphics screen.
Required input for this function is as follows:
XH = 14H (function number)
4.10.14
Set TTY Status Region Beginning - AH = 1SH
This function specifies a beginning line on
the
screen.
The
text
from
this
beginning line to the end of the screen is considered the
status region.
This fucnction can define a status region of
one
or
more lines.
This region remains in effect until it is reset.
During
TTY writes,
this area remains intact and everything above this line
TECHNICAL REFERENCE
DEVICE SERVICE ROUTINES
scrolls should:
1.
as necessary.
'@
.
. i
Read and save
In order
A
the current
to write
to this
cursor position.
area,
the wuser
2. Locate the cursor within the status region.
3. Use one of the write).
write
character
functions
(not
the TTY
4. Restore the cursor to its original position.
Required input for this function is as follows:
CH
i
0 (must always be zero)
cL
"
Start line of status region
(valid values are 0 through 24.)
A value
of zero
(0) for
the start
implementation.
The start line must be
cursor position, or no status region is
line resets the
a line
after
implemented.
status region
the
current
4.10.15
Set Attridute(s) - AH = 1i6H
This
function provides an alternate method with which to control the
following attribute(s).
* Intensity levels 1, 2, and 3 (blue, red, and green) * Character enable/disable
* Reverse/normal video
* Underline
*
Blink
* Alternate character set
aTCbletohaluftitorftsccesrthkcoih,trebfuuotrnaPectoaa(tstnsssidri)iotin.nibgoutlhntseeue)sbeCtsoH(semraAsqtibHputi=eeten0chnCi9eiutnHfr)CgisheoadsrrpcftaehhuiccnaPisictrnoftaesiicrirfeott/eundeiAgn.roticsntstrtiaieotTrnb(htAwuerHrti=iewBbOtLia.AutttHetht)ne(re(iiasbt)ftuhouHteWnerrcittthiieenblotlanootCscchckhraerhteaahoncserrteemarsasiatisnthnuegts(mlreeeii)btsuhatstemehearetet
Although more than
not
make
sense.
one attribute For instance,
can be used, certain combinations if the character enable attribute
do is
4-31
TECHNICAL REFERENCE
DEVICE SERVICE ROUTINES
set to a zero, then the character will not appear nor will any of the other attributes except for reverse video. The required input for this function is shown in Figure 4-3.
BL = Attribute(s) to set (BL is used to distinguish this function from the change screen attributes function).
|--> L----» L L
% »
Intensity level 1 (biue}
intensity level 2 {red)
Intensity level 3 (green)
Character enable (second dominant)*
Reverse video (first dominant)*
Underline
Blink
.
Alternate character set
* The user can specify more than one attribute. For instance, it is possible to have reverse video with an underlined, blinking, red character. The user can mix the intensity (color) bits for different intensities or colors for a given character.
223216-24
Figure 4-3 Byte Definition - Set Attribute(s)
TECHNICAL REFERENCE
DEVICE SERVICE ROUTIKES
4.10.16
Get Physical Display-Begin Pointer - AH = 17H
This function is used to return the physical display-begin pointer to
an application.
Logically, the display-begin pointer
is alwvays
at
0,0,
but
there
is a physical address (offset) associated with the
beginning of the display that changes from time to time as the screen
is scrolled, cleared, or otherwise
changed.
This
routine
returns
that
offset
address
relative
to the CRT memory area whose segment
address is DEOCH.
The screen memory is a 2K-byte contiguous block of
RAM.
Once the starting location
of
this block
is known
to the
application,
any character
on the screen
can be accessed.
For
example,
the 1last
character
on
the
screen
is
located
at
(DEOOH: display-begin
+2000)
and
the eightieth
character
on the
screen
(top line,
(DEOOH:display-begin
as follows:
last
character
on
the
line)is
located
at
+ 80).
This returns the display-begin pointer
DX = 16-bit display-begin pointer (offset)
Example:
DX = 0 implies that the first character on the display resides in memory location DEOO:0000H
DX
1S0H implies that the first character on the
display resides in memory location DE0OG:01SO0H
4.10.17
Print TTY String - AH = 18H
HWith this
function,
the user
can have
a contiguous
string
of
characters,
of a given
length,
1located
in a code segment to be
printed (starting at the current cursor position) in a TTY
fashion.
As with
the Hrite
TTY function, this routine executes the control
characters CR, LF, BS, and BEL and scrolls the screen if necessary.
Reguired input for this function is as follows:
BX = Address (offset) of the string*
Where: (BX) byte ©
(BX) byte 1
"
length of the string first character of the string
* The user's code segment address is obtained from the stack and therefore does not need to be passed as a parameter.
4.10.18
CRT TTY Mode Behavior
e
The following
used
in
the
"mixed"" modes.
especially if
is a brief description of the behavior of the CRT when
TTY mode as well as its behavior when being used in
The user
should
read
this
information
carefully,
the user mixes non-TTY functions with TTY functions.
TECHNICAL REFERENCE
DEVICE SERVICE ROUTINES
Internally,
the CRT DSR
implements
a "phantom" column 81 on each
?'line, which is actually
column
1 of
the
following
line.
This
"phantom"
column
occurs
vwvhen a TTY write puts a character in the
eightieth column of the current line.
If a carriage
return
(<CR>)
command
is issued at this point, the cursor moves from the column 81
of the current line back to column 1 of the current
1line.
However,
if the cursor
is in column B8l, reading the cursor position returns
(current line + 1, column 0), instead of (current line,
<column
81).
The user must be aware of this before attempting to restore a cursor
position which logically came from column 81, because the Set Cursor
Position
function
has no concept
of a column 81.
This concept
disturbs the TTY mode and it restores the cursor
to a new logical
position, that is, to column I of the next line.
Although the column
1 position
has only one physical location, it can be interpreted as
two different logical locations, depending on the current CRT action
{mode).
4.10.19
Custom Encoding of the CRT
It is possible for the user to custom encode the characters displayed
on
the
CRT,
wusing the CRT "mapping" function.
This mapping allows
the applications first to intercept characters (and
CRT actions
if
necessary) then to encode them.
:
Upon
entry
to
the CRT DSR, a software interrupt is executed, which
points to an IRET instruction.
An application program can reprogram
the
IRET to intercept calls to the CRT DSR.
The program can thereby
"take over" the CRT.
This
is the
typical
method
used
to remap
characters
to the screen.
For instance, this feature can be used to
scan through a table, converting English characters to characters
in
some other language.
Another use is intercepting "function calls"
(such as scroll
or attribute
handling)
so
that
the application
program
can
custom
encode CRT functions.
The user must be careful
when performing this operation, however, because it
is possible
to
disturb the data structures of the CRT DSR.
NOTE
After finishing with this function, the user must
restore
the
vector
to its
original
value.
Otherwise, the system could "go away."
After the user enters his mapping routine, he can use all registers
except
ES,
bs,
and BP.
To use these registers, he must save them,
then restore them upon exit.
Before using this mapping feature,
the
user must
look at the opcode in register AH to determine if it is a
write character request.
If so, he must also preserve
register AH
and any
registers
associated
with
the write
function contained
therein.
For example, to map all dollar
sign
symbols
($§) to the
percent
sign
(%),
the routine monitors register AH on each call to
TECHNICAL REFERENCE
DEVICE SERVICE ROUTINES
the CRT DSR.
If AH contains a write character
opcode,
the routine
then looks at register AL.
If register AL contains 24H (the ASCII
code for "$"), the user changes that register to 25H (the ASCII
code
for
"%"), then executes an IRET instruction, returning to the screen
with the new character.
(The currency symbol returned depends on the
internation keyboard being used.)
All registers are preserved,
but
register AL has been changed.
4.1t
DISK DSR
Table
4-7 describes
the
disk
device
service routines (disk DSR)
supported by the Texas Instruments Professional Computer.
To access
a function,
place the proper opcode in register AH, then execute an
INT 4DH.
On return, all registers are preserved except where stated.
Table 4-7 Disk DSR Opcodes and Functions
Aldb Code
Description
OO0H 01iH 02H
O3H 04H OSH O6H* O7H* OBH*
O9H* OAH*® OBH*
Reset disk system
Return status code (for last operation)
Read sectors
Hrite sectors
¢
Verify sector CRCs
Null operation
Verify data
o
Return retry status
Set standard disk interface Set DIT address for unit
table
(DIT)
for unit
Return DIT address for unit
Turn off diskette drive motors
* These functions are primarily for the use of syatem-level software and utilitiss,
4,11,1 BReset Disk System - OOH
Input:
AH = QOH
Quiputlt! AH = OOH
This function causes
state.
The actions
the requirements of
general, the function
the disk system to restore
itself
performed for each supported device
the device and the device~-dependent
causes the disk controller(s)
to
to a known
varies with
software.
In
reinitialize
before their next use.
TECHNICAL REFERENCE
DEVICE SERVICE ROUTINES
4.11.2 Return Status CodeS - OlH
3 :
Input:
AH = 0O1H
Output:
AH = OOH AL = Status code for last CF = 0 (Ko change)
disk
I/O operation
Not
all
disk
DSR
instance).
A status
status
of
the last
(via this function),
functions
are
I/0 operations
(this
one, for
is returned in AH for
each
function,
but
the
/0 request is always retained for later access
if desired.
4,11.3
Read Sectors - O2H
Input:
AH
02H
AL = Number of sectors
CH = Cylinder number
CL = Sector number
DH = Track (surface or
DL = Drive number
ES:BX = Segment:offset
to transfer
side) number of buffer
Qutput:
AH = I/0 status code (For more information,
AL = Number of unprocessed ES:BX = Segment:offset of
refer to sectors
the last
i paragraph 4.11.13.) sector processed*
This function reads data from the disk. transferred subject to memory boundary boundary and disk boundaries cannot be
Any number limitations crossed.)
of sectors can be (The segment''s 64K
* "Last sector processed" means exactly that.
Even if the
read
was
in error, the data is transferred to memory.
TECHNICAL REFERENCE
DEVICE SERVICE ROUTINES
4.11.4
Write Sectors -03H
Input:
AH
O3H
AL = Number of sectors
CH = Cylinder number
CL = Sector number
DH = Track (surface or
DL = Drive number
ES:BX = Segment:offset
to transfer
side) number of buffer
Output:
AH = I1/0 status code
(For more AL = Number
information, refer to paragraph of unprocessed sectors
4.11.13.)
ES:BX = segment:offset of the last sector processed*
This
function writes
transfered subject to
64K boundary and disk
data to the disk.
Any number of sectors can be
memory boundary
limitations.
(The
segment's
boundaries cannot be crossed. )
*
"Last
sector
error, ES:BX
to transfer.
processed"
means exactly
points to the
data
which
that. the
If DSR
the write is in is attempting
4.11.5
Verify Sector CRCs - 04H
4
Input:
AH
O4H
.
non
AL
Number of sectors to transfer
CH = Cylinder number
CL = Sector number
DH = Track (surface or side) number
DL = Drive number
ES:BX = Segment:offset of buffer
Qutput:
AH = I/0 status code (For more information, see paragraph 4.11.13.)
AL = Number of unprocessed sectors ES:BX = Segment:offset of the last sector processedx
This
function
verifies
the
this function is handled like
though
a
transfer
is
to
transferred.
Any number of
memory
boundary
limitations.
boundaries cannot be crossed.)
CRCs of the specified sectors.
Because
an I/0 function, ES:BX must be
set
as
take
place although no data is actually
sectors
can
be
processed
subject
to
(The segment''s 64K boundary and disk
:
* "Last sector processed"" has little meaning this function does not actually transfer
in this data.
case
because
TECHNICAL REFERENCE
DEVICE SERVICE ROUTINES
4.11.6
Null Operation - OSH
LFre
This function is not currently gupported.
.
4.11.7 Verify Data - O6H
;
Input:
AH
O6H
=
AL = Number of sectors
CH = Cylinder number
CL = Sector number
DH = Track (surface or
DL = Drive number
ES:BX = Segment:offset
to process ¥
side) number
of buffer
Output:
AH = (For AL = ES:BX
I[/0 status code more information, see paragraph Number of unprocessed sectors
= On error, segment:offset of
4.11.13.) WORD in error
This
function
of sectors can
(The
segment's
crossed.)
verifies disk data against data
be processed subject to memory
64K boundary
and
the disk
in memory.
Any number
boundary
limitations.
boundaries
cannot be
4.11.8 Return Retry Status -~ O7H
£
<
Iinput:
AH = O7H
Output:
AH = OOH AL = Soft error
status
of last
[/0 operation
This function
returns
the
refers to an
retried.
is similar to
"soft"
error
error that did
the Return
Status
Code
function.
It
status of the last operation.
Soft error
not recur when
the
last
operation
was
TECHNICAL REFERENCE
DEVICE SERVICE ROUTINES
4.11.9
Set Standard Disk Interface Table - O8H
Input:
AH
O8H
AL
Standard DIT number
(valid values are 0 through 3.)
DL = Diskette drive number
(valid values are 0 through 3.)
Qutput:
AH = Error status (For more information,
see paragraph 4.11.13.)
(Note:
This function is used by the operating system software.)
Disk
interface
tables
{DITs)
are
information that
the device-dependent
interface with the device-dependent code
data part for a
structures
containing
of
the DSR
wuses
to
specific disk device.
With
this function, the user can set a diskette
standard configurations by setting the drives''s
DIT numbers are defined as follows:
drive DIT.
to one of four
The
standard
Number
Description
o
Single sided, 48 tpi,
1
Double sided, 48 tpi,
2
Siqgle sided, 986 tpi,
3
Double sided, 86 tpi,
sectors/track, sectors/track, sectors/track, sectors/track,
S1i2-byte Si2-byte Si2-byte S12-byte
sectors sectors sectors sectors
uon ® OO
4.11.10
Set DIT Address for Drive - 038H
Input:
AH
0SH
bL
Disk drive number
(valid value is 0 through 7.)
ES:BX = Segment:offset of DIT for drive
Qutput:
AH = Error status (For more information,
see paragraph 4.11.13.)
(Note:
This function is used by the operating system software.)
Disk
interface
tables
(DITs)
are
information that
the device-dependent
interface with the device-dependent code
data part for a
structures
containing
of
the
DSR
uses
to
specific disk device.
With
this
function,
the
user
can
set
any
configuration.
The disk drives are dynamically
by this mechanism.
disk to a linked to
nonstandard the system
TECHNICAL REFERENCE
DEVICE SERVICE ROUTINES
4.11.11 Return DIT Address for Drive - OAH
-
input:
AH
DL
OAH Disk drive number
{valid value is 0 through 7.)
Output: AH ES:BX
= Error status (For more information, see paragraph
= Segment:offset of DIT for drive
4.11.13.)
(Note:
This function is used by the operating system software.)
Disk
interface
tables
(DITs)
are
information that the device-independent
interface with the device-dependent code
data part for a
structures
containing
of
the DSR uses
to
specific disk device.
Hith this function, the user can access a drive's DIT for information and verification purposes.
4.11.12
Turn Off All Diskette Drives - OBH
Input:
AH = OBH
OQutput: AH = 0
s
ES:BX = not preserved
(Note:
This function is used by the operating system software.)
During regular operation, the diskette drive motors are left ON for a
short
period following a read or write operation, thereby saving the
time the motor would use to come up to speed.
notably
diagnostics,
require
assurance
that
Some
applications,
the
motors
are not
running.
4.11.13
Status Codes
All functions return a status code in register AH and an
error
flag
in CF.
If
the
carry condition is set (CF = 1), then an error has
occurred and AH contains the error code.
If the
no-carry
condition
is set
(CF = 0), no error has occurred and AH contains a zero.
The
error codes are given in Table 4-8.
TECHNICAL REFERENCE
now W
DEVICE SERVICE RéUTINBS
Value
OOH 80H 40H 20H 10H 08H 04H O2H O1H O3H OSH 09H
Table 4-8 Error Codes
Description
No error Time-out - drive not ready or hardware Seek failed - track not found Controller hardware failed CRC error Data request error - controller failure Record (sector) not found No data - bad disk format Command error - bad opcode or parameter Disk write protected Data did not verify I/0 transfer crosses 64K byte boundary
failed
4.11.14
Disk Interface Tables (DITs)
The Disk Interface Table (DIT) structure
interfaces
code with the generalized disk driver code.
device-specific
Because in ROM.
DITs
contain read-only data exclusively,
The gtructure of a DIT is shown in Figure 4-4.
they can be placed
s
TECHNICAL REF*kE:REZNCE
DEVICE SERV&CE ROUTINES
<---- 16 bits ---->
00H DITDIR
02H
04H
DITSEC
06H
DITTRK DITCYL
08H
DITDSK DITERR
Long pointer to disk interface routine
Sector size in bytes Track size in sectors; cyclinder size in tracks Disk size in cylinders; error retry limit
All other fields depend on the code requirements of the specific device.
A. General DIT Structure
\
<4--16 bits ---->
00H FLPDIR
02H
Long pointer to diskette interface routine
04H
DITSEC
Sector size in bytes
06H
DITTRK
DITCYL
Track size in sectors; cyclinder size in tracks
08H
DITDSK
DITERR
0AH PRCOMP
Disk size in cylinders; error retry limit Threshold track number for changing write precompensation
B. Diskette Drive DIT Structure
223216-25
Figure 4-4 DIT 'Structure
e ;
-,
Tscu_n,x.&pfnk%&aucz =
o
DEVICE SERVICE ROUTINES
The following procedure shows how to set up the disk DSR in
access
a 'flexible disk
(floppyii with a "nonstandard"
("Nonstandard" is a®format that usudlly is not supported by
Instruments Professional Computer.)
order
to
format.
the Texas
MOV
AH, OAH
; Set "return DIT address"" opcode
MOV
DL, <unit number>
; Any floppy disk unit (0 - 3)
INT
4DH
; Call disk DSR
LES
BX, ES:(DWORD PTR [BX]
; ES:BX := address of floppy code
MoV
<your DIT>+0,BX
; Put address of floppy-specific
MoV
<your DIT>+2,ES
8
code in your own DIT
<initialize your DIT>
; Do whatever else you need to your BDIT
MOV ES,SEG<your DIT>
MOV BX, OFFSET<your DIT>
MOV AH,9 MOV DL, <unit INT 4DH
number>
; EX:BX = address of your DIT
Set Unit Call
"SET DIT ADDRESS" number disk DSR
opcode
-
NOTE
-
The floppy-specific code comprehends only double-
density (MFM) recording format.
it does not know
how
to access
single-density
(FN)
recording
format diskettes.
-~
_TECHNICAL REFERENCE
. DEVICE SERVICE ROUTINES
4.12
KEYBOARD DSR
This
subsection
describes
the Xxeyboard DBSR and the functions it
provides to the system or application programs that use it.
It also
shows
the various
codes
returned
by the DSR for
the standard
configuration of the keyboard.
The keyboard DSR functions are located in the system ROM and are
accessed
through
the 8088 software interrupt mechanism (essentially
an address-independent subroutine call).
The
typical
wuser
of the
keyboard
DSR
is
the system
interface
code
(the
BIOS).
Each
operating-system~-dependent BIOS resides
on a particular
operating
system diskette and is loaded into RAM during disk boot.
The
functions
described
in this subsection access a buffer that is
controlled by the keyboard interrupt service routine.
All
encoding
and any special handling (described in subsequent paragraphs) occurs
in the
interrupt
service
routine.
All discussions
of keyboard
mapping
vectors
refer
to actions occurring during the servicing of
the keyboard hardware (not software) interrupt.
Placing an opcode
desired function.
functions
of
the
paragraphs.
in register AH and executing an INT 4AH chooses the
All
registers
except
AX are preserved.
The
keyboard
DSR
are
described
in the following
.
<
4.12.1
Initialization Logic
-
The code for this function is automatically executed during
power-up
or reboot
and
is not directly. available to the user.
It performs
diagnostics on the Xxeyboard hardware,
sends
to
it
the
required
initialization
sequences,
and
initializes
the DSR
internal data
areas.
4.12.2
Read Keyboard Input - AH = O
This function reads and removes the current character (if
any)
from
the keyboard buffer.
The character value is returned in register AX.
I1f no character is ready, the DSR waits until one is received before
it returns to the caller.
This
character
has already
been
fully
encoded
(Table
4-10 lists the ASCII codes.)
Typically, the encoded
ASCII character is returned in register AL, and register AH contains
00.
If AL = 0, then the coded value in AH corresponds to one of the
various function keys.
(Table 4-11 lists the non-ASCII codes for the
function keys.)
Yihr ety - NICAL REFERENCE
-
4.12.3
»
Read Keyboard
Status
- AH = 1
DEVICE SERVICE ROUTINES
This "function determines that a character is ready
at
the
keyboard
but
does not
actually
read
it.
If no character is waiting, it
returns with the
2Z-flag
set
(ZF = 1).
It
the
2-flag
is
reset
(ZF = 0),
a character is available to be read.
The character
is returned in AX, but is not removed from the keyboard buffer.
value
4.12.4
Read Keyboard Mode
- AH = 2
This function determines the current mode
value
is
returned in register AL in the
The definition of the byte is as follows.
of the format
keyboard.
The
shown in Figure
mode 4-5.
7
6
5
4
3
2
1
0
Reg AL
Figure 4-S
l--» 1 = CTRL key depressed
`-------- `------------ `------------------&
1 = ALT key depressed 1 = SHIFT key depressed 1 = Last key was result of
repeat-action sequence
000 (always zero)
--» 1=CAPS LOCK key depressed
Byte
Definition
- Keyboard
Modes
282
-~
- TECHNICAL REFERENCE
S
DEVYICE SERVICE ROUTINES
fecause the
"mode"" applies -to
the
1last
character
typed
and
not
necessarily to the one at the front of the queue, this function returns
valid
information ,only, ,_di.fl ti'ie_ '&b&)'board buPfer contains one or less
characters.
In order to use this function., read the key normally, then
make a status check to ensure that the buffer is empty.
When the
buffer is empty, the mode reading will be valid.
Use
this
mode when
"Custom
remapping
function
only if it';s necessary
the last character was;/'typed.
See
Encoding
of the CRT"
in Section
the keyboard.
to know the
4 for
the state of the section entitled an explanation of
4.12.5 Flush Keyboard Buffer - AH = 3
This function is used
buffer.
It
simply
empties the buffer.
to "flush"
resets
the
(empty)
the Xkeyboard
type-ahead
queue
pointers, which effectively
4.12.6
Keyboard Output
-~ AH = 4
This function sends the keyboard
command
in AL directly
to the
keyboard,
with
appropriate
handshaking.
On return, the Z-flag has
the status of the operation.
If
the
2Z-flag
is set
(ZF=1),
the
command was performed correctly; otherwise (ZF=0), an error was made.
The keyboard commands sent by the CPU are given in Table 4-9.
Table 4-9 @eyboard Commands
<
Register AL
Function Performed
[sX¢]
o1% 02 03 04% oS 06%* 07 os
Performs a power-up reset and installs default parameters
Turns repeat-action feature ON Turns repeat-action feature OFF Locks the keyboard Unlocks the keyboard
Turns keyclick ON#*%x Turns keyclick OFF«x%t Resets Returns keyboard ROM version
* Indicates the default value. ** Keyclick requires a hardware modification.
(It is not presently supported.)
TECHNLCAL REFERENCE
DEVICE SERVICE AOUTINES
These
Eommands
are intended for "one-shot"
mode at power-up.
Although they may be sent
use, to set the keyboard
at any other
time,
the
overhead of receinng several commands can cause the keyboard to miss
fast A CRT
Xkeystrokes.
There are
emulator program may be
other ways to implement these commands.
required to turn repeat-action
on and
off
in response
application
needs
lock/unlock
the
programmed into a
to escape sequences
to set/reset
Xkeyboard
in real
keyboard
mapping
from a host.
For example, if an
the
repeat-action
mode,
or
to
time,
these
functions
can be
routine.
Refer
to paragraph
4.10.19.
4.12,7
Put Character Into Keyboard Buffer - AH = §
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To
place a normal ASCII character
call with the character value
in
function
keys
into
the buffer,
extended function
Table 4-11.)
value
in 8H,
and
@
into the buffer; make the function
BL and
zero
in BH.
To place
make
the ~function call with the
zero in BL.
(See Table
4-10
and
This though
function they had
is useful when been typed.
a Two
program needs characters examples follow.
to appear as
*
aAci"nnehnocaithrtaohaip"ecaprtlleiirzckfaaeettyaiitoo(unanCrn.TedRLcatnubyrNTnhsedifiosnorafsofbeplreetrMtiaShnte-giDntOhgeSec)htoh.eosypisenttraoeapmtpirnogtphsreeieastsyebsutftefhmeir*s"echaposrdiunrojtifuenfsrg"t
*
pMfisttahrnuieenovnmryogcumkrtilkeainaeomoatypntibeaenorsgaa,srttede«iccraanonmfgnilbdnuutasfypshtfprpyeeeorssrdvot,,tieghdmreesaamcn,oktdmhelemyaoabcnptnkeoeho.dareprfreadoerrbamyitnsbcIituhmnofamg"fiectendhhriaia,stntiahygntesietncltegohym"embf"nmueafatnftappbdeuklerrreafo.escog,e(rrweahoimvcceshaaHhr)nha,d.erpnarcocrtgoeetruahrtaldihsmdsse
' TECHNICAL REFERENCE
DEVICE SERVfCE'ROQTIHES
4.12.8
General Keyboard Layout
The
outline
of the kXeyboard and the key-position numbers associated
with each of the keys are shown in Figure 4-6.
The numbers
in
the
upper
right-hand corner of the keys are the scan codes sent from the
keyboard.
These codes are used internally by the xeyboard
DSR
to
encode
a key
when
pressed.
The
mode
keys
(marked **t) do not
generate a scan code.
=) I () @
©
G
& ) &
& )
® @ & ) & ) & B B
&@)
OEBAeEEEEe6M0
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23218-27
Figure 4-6
General Keyboard Layout Showing Scan Codes
TECHNICAL REFERENCE
.
DEVICE SERVICE ROUTINES
4.12.9
Character Codes
Table 4-10 lists
by
the
keyboard
keyboard DSR, and
this table,
the character
DsSR.
The
the returned
and extended function
codes
returned
modes
are handled
internally by the
code reflects
the mapping
shown
in
Table 4-10
sStandard Keyboard Character Codes
|
] £S
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23
24|
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25 | ---
SE | RS
26 | ---
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08 | DEL
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1E | alté ~-- | alt? -~ | alts
----
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aalltto9
1F | alt-
-- | alt=
7F | =--
3D | pR fi
2B
20
| pf2
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09 | pfe
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F9
{
F10
F11
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| § | |
Back space
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Numeric =
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Numeric
Numeric
+
SPACE]
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Numeric TAB |
N(uumneursiecd) 1
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Numeric 0
|
Kumeric
Kumeric Numeric
ENTER|
4
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§
}
Numeric 9
|
Numeric -
Numeric 2
|
}
TECHNICAL REFERENCE
- DEVICE SERVICE ROUTINES
Table 4-10.
Standard Keyboard Character Codes (Continued)
______________________________________ e
-- e
| Key #|
Normal | SHIFT
| CTRL
|
ALT
|
Comments
f
j 36 | 37 | 38
§ 39
{ 40
} 41
L2
| -== } -== | ---
| 7
| 8
| 6
|
==} === ==} === --j -=--
378 | R" 7.
38| 8
36 |} 6
'l b
== | ===
== | ===
--{ ---
37N
7
38 | 8
3¢ | 6
2 |,
-- | #-~- | === ~-- | =---
37 | ---
38 | ---
36 | ---
2¢ | ---
-- | (Unused)
=-- | (Unused)
-- | (Unused)
==
-~
| Kumeric
| Numeric
7
8
=-- | Numeric 6
-- | Numeric ,
| 1 |
i
|
{
|
{ 43
| 3
33 | 3
33 | 3
33 } ---
~-- | Numeric 3
}
{| 4454 || ==s= 2=E= || ==o= 2=E= || === 2=E= || -=-=-= ---~ || N(uUmneursiecd) .
} i
| 46
| C-rt 4Dx}sC-rt B8A%*|cC-rt 74%jaC-rt 4Ex| Right Arrow
}
] 47
| Ins
5S2x| sIns 28%] cIns 29%| aIns 2A%| INS
]
j 48
| Del
S53%| sDel 38+%| cDel 39%| aDel 3A*| DEL
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§
49
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| s2
j s3
i s4
| ss
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| ---
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195 | altY 15%]|
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1B | --- -- | 1D | --- -- | =~
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| }
| 82 | 63
| LF } =--
OA | LF OA | cLF
--}
br =-- | -==-
75%| aLF == ] ===
4F*| Line Feed -~ | (Unused)
i |
| 64
| 65
| C-up
| ESC
41B8%|s| 5CE-SCup
18B8%|| cCE-SuCp
84%|aC-up
1B | ---
49%| Up Arrow
=-- | ESC
§
|
|
66
{ a
61 | A
41 | SOH
01 | altA 1Ex|
|
{ 67
| 68
|
s
| 4
73 | S
64 | D
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13
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| alts
| altD
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66 | F
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47 | BEL
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TECHNICAL REFERENCE
DEVICE SERVICE ROUTINES
Table 4-10.
Standard Keyboard Character Codes (Concluded)
| Key #] Normal
| SHIFT
| CTRL
|
ALT
|
Comments
i
]| 77+2 || h§
8A || JH
448A || LBFS O08A || aallttHJ 2234%%||
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| 73 | X 6B | K 4B | VT 0B | altK 25|
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f
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4C | FF
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|
| 78
SC.l |
7C §{ FS 1C | === == }
| 79 | C-1f 4Bx|sC-1f 8B*|cC-1f 73*|acC-1f 4C*| Left Arrow
j
| 80
| Home 47*|sHome 86*|cHome 77*}jaHome 8S5*| HOME
{
f 81
| sP 20|
SP 20|
SP 20 | SP 20 | Space bar
|
| 82 | =z JA | Z SA | SUB 1A | altZ 2C*|
|
| 83 | x 78 | X S8 | CAN 18 | altX 2Dx|
§
84
|l 8
§
c
| v
63 | c
76 | V
43 | ETX
56 | SYN
03 | altC 2Ex|
16 | altVv 2F«|
}
86
| b
62 | B
42 | STX
02 | altB 30|
{
|
87
§
n
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| C-dn SO*|{sC-dn 89%|cC-dn 76%]|aC-dn Si%*} Down Arrow
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| =-- o
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Re B
R (Unused)
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{ 100
| 101
s st
| Ppau
| £1
dt)
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** | Pbrk
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** | ---
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| 102 | £2 3Cx|sf2
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Notes to Table 4-10:
1.
Key # is shown in Figure 4-6.
2.
In
the
"Normal","SHIFT",
"GTRL",
and "ALT"" columns, both the
"graphic" and the hexadecimal values of the character
are given
in
the form:
GGG HH.
Mnemonics are used for the "graphic" descriptions
of
the
function
keys.
These
are
generally self-explanatory:
a
leading a, s, or c indicates ALT, SHIFT, or CTRL, respectively.
For
example,
f1
4is the F1 function key:; afl is the F1 key pressed while
TECHNICAL REFERENCE
DEVICE SERVICE ROUTINES
holding down the ALT key.
C-rt means cursor right (right arrow), and
cLF = CTRL linefeed.
?
.
~ »
3. Entries consisting of "--- --" " indicate that the
combination
is
suppressed within the kxeyboard DSR.
4.
Entries
consisting of "xxx **" indicate special handling in the
form of direct
action
by the xeyboard
DSR.
(For details,
see
paragraph 4.12.14.)
B0
Normal
(ASCII)
characters are returned in register AL with the
scan code key number in AH.
6. Entries consisting of "xxx yy" are returned
with AL=0
and
the
indicated value (yy) in AH.
78
An asterisk after 2 number means extended codes, listed in Table
4.12.10
Extended Codes
The "extended"" codes are non-ASCII
codes.
They
represent
special
function
keys on the keyboard.
To distinguish these codes, register
AL contains 00 upon returning from a Read Keyboard
(AH=1
or AH=2)
function
«c¢all,
and
the
extended code is in register AH.
The code
range (OOH through FFH) includes normal ASCII
codes.
The
extended
codes
are given in Table 4-11.
Use the mnemonics to cross-reference
with Table 4-10.
<
Table 4-11
Extended
Function
Lt
Codes
Tresl -
S
I S DR
eo e
} © |Pbrk JaltQ
j 1 {Ppau jaltW
P2
faltE
| 3 | 4
|Fnul |
|altR |altT
JI
.
Jalty
f6 | 1 7
faltU lalty
{ 8 |}(sfil |alto
} 9 { A
| B
|{sfi2 jecfii
jcfi2
jaltP |
|
I ¢ lafiyr |
| D |afi2 |
JIRSEIRE
faltAa
{ F {Bktablalts
s
e e
|altp jaltF jaltG jaltH falts |altK jaltL f |sIns jcins jains
j
laltz faltXx
|altc jaltv
e
|altB jaltN |altM | | } | | |sDel {cDel |aDel
| £1
| £2 | £3 | f£f4 | £S
e nlye L2
el
R
e e
e
| £6
| C-dnf c£3 | af9 jalt9 |
| £7
Jac-dn| cf4 Jaflio |alto |
| £8
| Ins | cfS jPtogllalt- |
{ £9 | £10
| Del | sf1
| cf6 | cf7
|cC-1fjalt= | jeC-rtjeC-up]|
| £11 | sf2 |} cf8 | cLF }aHome|
| £f12 | s£f3 | c£9 |cC-dn}sHome|
| Home| sf4 | cf£10|cHomej
i
| C-up| sfS | afi |Jaltl |sC-up]
jaC-up} sf6
|
| s£7
| c-1£} sfs
| af2 } af3
| af4
{alt2 |alt3
jalt4
jsC-dnj |sC-rtf
|sC-1f}
Jac-1f} 'sf5 | af5 lalts | pfi |
| C-rt{ sfio] afé jalte | pf2 |
lac-rt| cfl | af7 Jjalt7 | pf3 |
{ aLF | cf2 | afg jalts | pfa |
* MSD = most significant digit; LSD = least significant digit
TECHNICAL REFERENCE
DEVICE SERVICE ROUTINES
4.12.11
Keyboard Modes
In the standard keyboard, the mode keys
have
the effect
shown
in
Table
4-11.
The
latching
(push-push)
CAPS LOCK key affects the
alphabetic keys (S0-S9, 66-74, and 82-88 on the standard keyboard) by
forcing
the SHIFT mode.
Normally
the alphabetic
keys
produce
lowercase characters, and the SHIFT key temporarily causes them to be
uppercase.
When the CAPS LOCK mode is invoked (the CAPS LOCK key is
latched down and the LED in the CAPS LOCK key lights), the alphabetic
keys produce uppercase and the SHIFT key has no
further
effect
(on
the alphabetic keys).
In
the standard encoding, the
CTRL/ALT/DEL,
which
is wused
only for
valid combination
system
reset.
of mode keys is Simultaneously
pressing
the
CTRL,
ALT,
and DEL keys results in the keyboard DSR
initiating the equivalent of a system pover-up reboot.
The action is
handled internally by the DSR and
does
not
return
a code.
This
function
is
"hardwired" and cannot be disabled.
In any other cage,
when two or more mode keys are pressed simultaneously,
only
one
is
recognized.
The order of precedence, beginning with the highest, is
as follows:
fAdLeTd CTRL, SHIFT, and CAPS LOCK
The ALT key has a special
use,
letting
s the user enter
any
character
code (COH-OFFH) from the keyboard.
When the ALT key is held down and
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nothing to the ALT/NUM value.
Pressing
the accumulated value and starts a new
more than
three
keys
three-keystroke seguence.
sends
Example:
ALT 003 places the value for an ETX in the keyboard buffer. ALT 3, followed by any non-ALT key performs the same function.
4.12.12
Type-Ahead Buffer
The
DSR
implements a circular type-ahead queue,
to 1S keystrokes.
(Each keystroke is 2 bytes.)
filled,
entering
further
characters
from
the
which can If the
keyboard
buffer queue sounds
up is the
TECHNICAL REFERENCE
DEVICE SERVICE ROUTINES
system beeper. queue pointers,
The Flush Keyboard Buffer (AH=3) effectively emptying the buffer.
function
resets
the
e
4.12.13
Repeat-Action Feature
If the repeat-action
feature
(the default) is enabled, th;re is a
half-second delay and all keys become repeat-action at a 1S-cps rate.
Repeat-action
characters
are
ignored
when
the queue
currently
contains
more
than one pending
character.
This
means that the
application does not have to worry about the repeat-action "coasting""
problem.
That is, if the application does not
or cannot
read
the
keyboard
input
faster
than
the repeat-action rate, the undesired
repeat-action characters are not queued and the keyboard does not get
ahead of the application.
4.12.14
Special Handling
These paragraphs describe functions
handled
by
the
Xkeyboard
DSR.
Several of these require immediate reaction (for example, pausing the
output
routine so a fast-scrolling screen can be read).
Most of the
keyboard DSR functions are implemented with
the
software
interrupt
facility of the 8088 microprocessor.
Fach of the defined interrupt vectors points to some default piece of
code
that
either
does
nothing
(for
example,
a single
IRET
instruction)
or performs
some
system
function.
fAn application
program
can
change
these interrupt `vectors in order to gain direct
access to a function.
However, the
application
must
preserve
the
original contents of the vector and restore it before terminating and
returning to the system.
If the application routine is used, it must
end with an IRET or the equivalent (FAR) RET 2, which allows flags to
be passed.
The
stack
used
is
the
internal
stack
of the keyboard interrupt
service routine and only 10 levels (20 bytes) of stack are
available
to the user's routine.
Interrupts are disabled when the user routine
is entered (by the INT instruction).
Interrupts should be re-enabled
immediately
wunless
it
is necessary
for
Registers AX, BX, CX, DI, and BES can be used
them to remain disabled.
(information
is passed
in AX);
any
others must be preserved.
Hhen the available stack is
too small, the routine must switch to an internal stack of sufficient
size (including © bytes for possible interrupts).
Also, the routine
is executed
as
a part
of the keyboard interrupt service routine,
which means that routine finishes
no other keystrokes
are
and returns.
The normal
accepted
until
the user
way to communicate with the
outside
world
watch for it in
(outside
the service
the application.
This,
routine) is to set a flag and for example, is how the BREAK
function is implemented in MS-DOS.
Control should not be retained by
the user's routine unless a complete system initialization is
to
be
performed.
TECHNICAL REFERENCE
DEVICE SERVICE ROUTINES
4.12.15
User-Available Interrupts
The
following
is a summary of the software interrupts (performed by
the keyboard DSR) that can be
used
by application
programs.
The
interrupts
are presented in their order of execution.
The number in
parentheses, instruction.
the
"interrupt
type,"
is used
in
an
interrupt
The absolute address of the corresponding vector.is the
interrupt
type
times 4.
As an example, the address of the keyboard
mapping vector is SBH x 4 = 16CH.
Any of the special
key
interrupt
functions
can
be
Dbypassed
by
re-encoding the key code.
For more
information on the key code, refer to paragraph 4.10.19.
The keyboard DSR interrupts and their mapping vectors are:
* Keyboard mapping (SBH) * Program pause (SCH) x * Program break (SDH) * * Print screen (SEH) * * Keyboard queueing (SFH)
*
»
These interrupts occur after internal encoding.
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TECHNICAL REFERENCE
DEVICE SERVICE ROUTINES
for
the program
pause
function is placed in AX.
Therefore, if an
IRET instruction is used to return instead of the default
ROM
pause
routine,
the
DSR
returns
the
program
pause function code to the
application.
Because the carry flag is usgsed to pass information, the
IRET instruction must be simulated with a (FAR) RET
2 if
the
user
needs
to return
with
the
carry
flag set.
(The IRET instruction
restores flags to their pre-interrupt state.)
4,12.15.3
Program Break.
Pressing the (shifted) BRK/PAUS key causes
a software interrupt and allows the user
to perform an action
or
return
a key
code.
It can be set to return an extended code (see
Table
4-11)
to
the
caller,
if
desired.
Buring
powver-up
initialization,
this
interrupt
vector
is set to point to an IRET
instruction so that the BRK key sequence
is ignored
other
than
returning
the break
code.
An application program can change the
interrupt vector in order to support a break
function
of
its
own.
However,
the program
is responsible
for preserving the original
contents of the vector and restoring it before terminating.
For more
information
on
the
encoding/software~interrupt
technigue,
see
paragraph 4.12.1S5.
4.12.15.4
Print
Screen.
Pressing
another software interrupt.
The user
a key code.
This interrupt normally
within
the ROM.
The DSR checks
described in paragraph 4.12.1S.
the SHIFT and PRNT keys causes
can perform an action or return
vectors to an
IRET
instruction
the carry flag upon return, as
The carry flag is set before the interrupt is executed,*so that
when
the routine consists only of an IRET, the key is effectively ignored.
This
can
be (and is, by the MS-DOS BIOS) patched so that it vectors
to an actual print screen routine.
This routine executes as a part
of
the
keyboard interrupt service routine and, therefore, cannot be
interrupted by another keystroke.
The preferred way
to handle
the
Print
Screen
function
is to use this interrupt to start the Print
Routine
(in
the
background)
then return
immediately,
thereby
reenabling the keyboard.
4.12.15.5
Keyboard
Queueing.
This software interrupt occurs every
time a character, whether encoded by the DSR or by the user,
is
placed
in the type-ahead buffer.
This interrupt lets the real-time
0S know when there is a character to read.
The user
can choose
to
ignore
the Xkxey (not
queueing
the keycode).
Refer to paragraph
4.12.15 for keyboard queuing interrupt conditions.
4.12.16
Custom Encoding
An application program can encode the keyboard using
this
function.
Each time a key is pressed on the keyboard, the keyboard sends one or
two Xey codes
to the DSR.
The mode Xeys are handled internally.
(For more information, refer to paragraph 4.12.17.)
The DSR performs
a software interrupt each time it receives a key code (not
including
the mode keys).
Normally
the interrupt vector points to an IRET
instruction.
An application program
can
reprogram
the
vector
to
TECHNICAL REFERENCE
:
:
DEVICE SERVICE ROUTINES
kkvrieeeenyysctsete,torrc,ceoctpdhoteemstnbheinetaxhatteepyiscppoeulinticeacslakl(teyCiyaToRnLs(/cFcAaAocRnLda)senTs/,DREttEahLTkr)eo.u.2ngEehocinanTthussretsodmrgeugrcé8tyUitetaofribnnyl.eetevsheirnygtttohhaticenongmceoisdbneuttetrhictrtesohpeutgsshpseycstithtaeihlmse
NOTE
It is essential that the application restore
the
vector
to
its
original value after completion.
Otherwise, the system will crash when the special
encoding routine is later written over.
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If
the
scan code is
the user
must
strip
instruction
is AND
the IRET instruction
pass flags back.
used in a table look~up
off
the
(possible)
AL, 7FH).
Because this
must be simulated with a
or a direct repeat-action is a software
(FAR) RET 2
comparison,
bit
(the
interrupt,
in order to
4.12.17
Keyboard Interface Protocol
kApfPtLheoorTeslye,lis-otspmwiiooCeondsAdngeiPStibkoayenLtyoOksCe.tKyhb,teyhteoenkTahnekedyeit-syhepbmCoooTpasdRrkeriLeed)tcyiebbodoynhDeataSdersRd.bybcityshseae.Innfangdesevbdteyhrteeasissnetscnahbtetoyetweiatnlhogeof nre.elttahhpeesrtesmcIetoundrketrewieiynnlsktglterysoaskltetwah,(ateSyuHssIFktTehb,oyeef
The mode
byte
is never
because it is sent only if
transmission.
The mode
function,
sent the cannot
during a
mode
has
change
repeat-action transmission,
changed
since
the
last
during
the repeat-action
4-57
TECHNICAL REFERENCE
DEVICE SERVICE ROUTINES
The 7).
second This
byte bit
(key position) contains a repeat-action key bit
(bit
is set to 1 during a repeat-action key transmission,
and reset to O during a non-repeat-action transmission.
If
the
Xkey
is still this time
pressed with bit
after 7 set
a half-second delay, the code to 1. The keyboard remapping
is sent again,
routine
wuses
this bit to suppress the repeat-action key function when necessary.
All communication with the keyboard is:
* Asynchronous
* Serial
* 8 data bit
% 1 stop bit
* Even parity.
The keyboard at 30S bps.
transmits
its data at 2440 bps and receives
its commands
Both bits
bytes
have
similar formats, as shown
3 through 6 of the mode key status byte
in Figure 4-7. are all set to
However, 1.
TECHNICAL REFERENCE
DEVICE SERVICE ROUTINES
8
7
6
5
4
3
2
1
0
e
L
FIRST BYTE (Not always sent)
Control Alternate Shift = 1111 (denotes first byte) Caps lock {uppercase) Parity
8
7
6
5
4
2
1
SECOND BYTE
Scan code
Repeated character
{repeat-acstion keys)
Parity
«
22321628
Figure 4-7 Byte Definition - Keycode
TECHNICAL REFERENCE
DEVICE SERVICE ROUTINES
The keyboard
understands
Keyboard
OCutput
(AH=4)
acknowledges each command.
several
commands,
function,
and
`as the,
5
explained
in. the
keyboard
generally
The codes sent by the keyboard (refer to Tables 4-10 and 4-11)
range
from scan code 01 through scan code 104 (OlH through 68H).
The spare
scan
codes
(from
69H through 6FH) will possibly be assigned in the
future.
If 3o, the size of the standard encoding tables will also be
increased.
Codes 70H through 73H are status codes
returned
by
the
keyboard
in response to commands.
Codes 74H through 77H are unused
but reserved, and codes 78H through 7FH are for encoding the mode key
status byte.
For more specific information, refer to the paragraph
entitled
"Receiving and responding to commands from the system unit"
in Section 2.
4.13 PARALLEL PRINTER PORT DSR
The following
printer
port
use it.
paragraphs describe the
functions
that
DSR provides to the system or application
the parallel programs that
The printer compatible characters,
DSR provides
routines
to implement
a
Centronics~
parallel
port
interface.
The
wuser
is able to output
get printer status, and initialize the printer.
The printer DSR functions, located in the system ROM, `*are accessed
through
the software interrupt mechanism of the 8088 microprocessor.
To choose a function, place the opcode in register AH, place zeros in
register DL, and execute an INT 4BH instruction.
(For an explanation
of register DL, see paragraph 4.13.4.)
All registers
are preserved
except
AH,
which always
returns
with
the printer status.
(See
paragraph 4.13.3.)
The functions available are:
Output Character to Printer (AH=0, Initialize Printer (AH=1, DL=0) Return Printer Status (AH=2, DL=0)
DL=0)
4.13.1
Output Character to Printer
-~ AH = 0, DL = 0O
This function sends the character in AL to the printer
port.
The
BUSY signal from the printer is checked before sending the character.
If the printer is still busy after approximately 0.33 s, the DSR sets
the
time-out
Dbit
in the
status byte (in AH) and returns.
If the
printer is not busy, the DSR returns with
the
time-out
bDbit reset.
Any unusual
conditions on the status signals from the printer cause
the printer to go BUSY.
Time-out also occurs
if the printer
sets
FAULT,
PAPER OUT,
or NOT SELECT.
The printer can also set BUSY,
causing a time-out.
TECHNICAL REFERENCE
DEVICE SERVICE ROUTINES
It generally is not advisable output routine during regular
to rely on the time-out of the use, especially if one is using
printer the DSR
from the printer task of a real-time OS.
This time-out is a software
loop and causes the application
The preferred
method
has
the
through the printer status call
to "hang" during the time-out period. application watching the BUSY signal
so that the application can implement
and control a time-out.
The standard sequence used to print a character is:
REPEAT Interrupt 4BH with AH = 2 and "Return Printer Status."
UNTIL
STATUS = NOT BUSY END
DL = 0 (see
paragraph
4.13.3,
INTerrupt 4BH with AH =
IF STATUS
THEN
= (time-out)
<handle the error> END
0, DL = 0 (FAULT or
and AL = <character> PAPER OUT or (NOT SELECTED) )
Note:
Refer to Figure 4-8 for byte definition of the
Return Printer Status function.
5
4.13.2
Initialize Printer
- AH = 1, DL = ©
~
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4.13.3
Return Printer Status
- AH = 2, DL = 0
This
function
reads
the
information
in register
returned after the Output
and the Initialize Printer
printer
status
port
and
returns
the
AH.
This is the same information as that
Character to Printer (AH=0, DL=0) function,
(AH=1, DL=0) function.
The bits of AH are encoded as shown in Figure 4-8.
TECHNICAL REFERENCE
)
DEVICE SERVICE ROUTINES
Figure 4-8
--
Time Out {on busy) {not used)
----
Busy
Paper Qut
Selected (online)
Fault
22321829
Byte Definition - Return Printer Status
4.13.4
VUse Under an Operating System
When the software interrupt technique interfaces with ROM routines, a
DSR can be enhanced or replaced by patching its
interface
interrupt
vector.
Ynder
MS-DOS,
for example,
the
serial
printer support
emulates the parallel printer functions of the ROM.
s
The printer interface is implemented by patching a small
routine
in
front
of the printer
interrupt
vector.
This" routine
1looks at
register DL to determine the desired printer.
If DL=0, a jump to the
ROM routine is made, and the user is unaware of the patch.
If BDL=1,
AH is decoded
to perform
the appropriate function on the serial
printer.
If DL = FFH, then the desired function is performed on the
default (currently configured) printer.
Because
the
serial
support
emulates
the status
returned by the
parallel routines of the ROM, the user knows of
the
operation
only
because
he
set
register DL.
Some operating systems do not require
that register DL be set.
In the case of MS-DOS, however, the DSR
is
extended
in a manner that requires the setting of DL.
Refer to the
documentation appropriate for the operating system in use.
TECHNICAL REFERENCE
DEVICE SERVICE ROUTIKES
4.14 HWINCHESTER ROM
&
The Winchester ROM, on the Winchester
controller
board,
interfaces
with
the system ROM software, specifically the system disk DSR.
The
Winchester ROM is addressed by the system processor.
Iits address, as
determined by the hardware, is OF8000H.
The convention
1locates
the
ROM at the address (as seen by the software) of OF400:4000H.
In addition to the disk DSR software, the Winchester ROM contains the
software necegsary to drive the Winchester controller, to boot up the
system
from
the
Winchester
disk,
to format the disk, and to run
diagnostics (both power-up and advanced) on the controller and disk.
After initialization, all regular operations of
the
Winchester
(read, write, verify, and so on) are done through the disk DSR.
subsection 4.11.)
ROM (see
4.14.1
Limitations
The DSR
and
other
utilities
provided by the system ROM limit the
types of Winchester drives that can
be
used
by
the
system.
The
limits are as follows:
* X x Y cylinders per drive where 1 < X < 256 ard 1 < Y < 1§ i
*+ 16 surfaces per drive
* 17 sectors per track
* 512 bytes per sector
* 2SS error retries
* 11-bit error-burst length
Most
of
the
that describe
the following
routines
within
the type of drive.
drive parameters:
the ROM are driven by data structures
The system is powered
up assuming
1S3 cylinders 4 surfaces
125 first track of 64 first track of 1 error retry 131-bit error-burst 3-ms step option
reduced write current write precompensation
length
If
the
use, an
install
default
parameters are not correct for
Initialize Winchester Disk System option
the correct parameters.
The system can
the call boot
type of drive in must be made to
the first sector
TECHNICAL REFERENCE
DEVICE SERVICE ROUTINES
with the default parameters.
%
4.14.2
System Interface
The Winchester controller board ROM is initialized to the system when
it is called by the system ROM following the power-up self-test.
The
system ROM tests the Winchester disk controller ROM to make
certain
the
controller
is functioning properly before calling it.
To allow
the system ROM to test and call it, the
HWinchester
disk
controller
ROM
contains
a header defining the ROM size, the entry point of the
ROM, a version number for the ROM,
and
an
identification
message
preceded by the message length.
The
entry
point
called
by
the system ROM is required to
device- dependent initialization and, optionally, to boot the
from the device that the called ROM serves.
For the Winchester
the operations are as follows:
do any system
disk,
* Set
the RAM area of the ROM in the system.
Set the device-
installed bit in the system configuration word.
This second
step permits the system unit to "sense" that the controller
is installed,
and,
under the diagnostics diskette Display
System Configuration test, to display all options
installed-
in the system unit.
* If
the
caller has passed the "do not boot flag" (OFFFFH in
register DX), return control to the caller.
Othegwise (with
0 in register DX), the initialization segquence continues.
.
* If the user has pressed the ESC key, control gxeturns to the system ROM and the system boots from the diskette.
* oOtherwise,
display the Hinchester disk controller ROM sign-
on message and execute the controller's power-up tests.
* Test all ROMs that have a lower priority than the Winchester
disk controller ROM and then call them.
The "do
not
boot""
flag
(DX
= OFFFFH) must be set so that the ROM can do any
regquired initialization of associated hardware.
* Read in
the
boot
sector
from
the disk,
check
usability, and jump to the code in the boot sector.
it for
* If
any
errors occur in the above area, control is returned
to the system ROM.
4.14.3
System RAM Usage
.
The HWinchester disk ROM uses 30 bytes of RAM in the system
This
RAM
is allocated
as
a contiguous block of memory
previously called ROMs have been allocated their RAM space.
block is pointed to by a word in the system vector
area.
RAM area. only after
This RAM The data
4-64
TECHNICAL REFERENCE
DEVICE SERVICE ROUTINES
structure of this vector area is given in Table 4-12.
Address
User
Table 4-12
RAM Segment Pointers-
Value
Address
0000:0180 0000:0182 0000:0184 0000:0186 0000:0188 0000:018A
0000:018C C000:018E
0000:0184 0000:0186 0000:0184 0000:0186
System ROM U663 System ROM U63 F400:0000 ROM ¥F400:0000 ROM F400:2000 ROM F400:2000 ROM MHindisk ROM Windisk ROM F400:6000 ROM F400:6000 ROM Option ROM U62 Option ROM U62
RAM segment address for ROM Length of RAM segment in bytes RAM segment address for ROM Length of RAM segment in bytes RAM segment address for ROM Length of RAM segment in bytes
RAM segment address for ROM Length of RAM segment in bytes
RAM segment address for ROM Length of RAM segment in bytes RAM segment address for ROM Length of RAM segment in bytes
F400:A000 F400:0000 F400:2000
F400:4000 (30H) F400:6000 F400:8000
All
accesses
to the Winchester disk controller RAM area are through
the segment pointer
at
0000:018CH.
Because
the :Winchester
adisk
controller
ROM
is located
at
segment OF400H, the segment painter
location can also
be reached
from
the
code
segment
at address
OF400:C18CH.
.
The segment pointer allows the Winchester disk controller RAM area to
be located
anywhere,
but
care must be taken if the area is moved
after the system is initialized.
If this
is done,
the HWinchester
disk
system
must
be
reinitialized with the Winchester disk option
call "0" (Initialize System) after the RAM area
is
moved
and
the
vectors
are set to the new values.
To do this, pass the nev segment
address in DS and 00O0CH as the pointer to
the
initialization
data.
(See paragraph 4.14.318.1.)
4.14.4
Power-up Testing
To determine that the Winchester disk controller is working properly,
it is tested by its own
Fajlures
are
reported
internal diagnostics and the as system errors 1lixx, where
RAM diagnostics. xx indicates the
error received.
If an error
occurs,
control
is returned
to
the
system ROM,
F
TECHNICAL REFERENCE
DEVICE SERVICE ROUTINES
4.14.5
Booting from the Winchester
After
the
power-up
testing
of
the controller
completes,
the
Winchester goes through the boot sequence.
Only drive 4 (E:
for MS~-
DOS) can be booted.
I£ drive S5 is connected to
the
controller,
it
can be used for data only.
First,
the
If the drive
on), the ROM
condition.
wait, control
conducts the
boot
procedure polls the drive for the
is not ready (as would be true after the
routines wait approximately 30 seconds
If
the user presses the ESC key at any
is returned to the system ROM, and the
initialization boot.
ready condition.
power is turned
for
the
ready
time during this
diskette
drive
4.14.6
Error Recovery
The
error
recovery
procedures
depend
on the
controller errors
(time-outs),
the controller
retries
are
attempted.
A hardware error code
disk DSR.
error.
For
is reset,
is returned
hardware and no
from the
For disk retries code.
drive errors (seek incomplete, write fault, and so on),
no
are
reported,
and
the disk DSR returns the hardware error
Read Data operations have
two
types
of
errors:
uncorrectable.
1f
the data is correctable, it is
error is reportgd directly.
A DSR Read
Soft
Retry
this error.
correctable
and
corrected, and no
Status
reports
-
For
uncorrectable errors, a "restore" is done before each retry.
If
the retry does not succeed, the data buffer is filled; with CCH when
the
data
cannot be read at all, or with the uncorrected data if the
data can be read but contains an ECC error.
For other operation errors, a "restore" is placed before each retry.
TECHNICAL REFERENCE
DEVICE SERVICE ROUTINES
4.14.7
Error Reporting
The disk boot can reported
DSR is report by the
capable of reporting only a few errors.
The power-up
more but not all.
Table 4-13 is a listing of errors
digk controller and the codes reported by the DSR.
Table 4-13
Winchester DSR Error Codes
Reported Error
20H Hardware failure
20H Hardware failure
20H Hardware failure
20H Hardware failure
20H Hardware failure
10H CRC error
10H CRC error
O02H Disk format error
04H Record not found
40H Seek error
O0H
No error (on RETURN)
10H CRC error (soft stat)
01H Command error
02H Disk format error
C1H
Command error
OiH Command errorx*
O02H
Disk format error
GiH Command error*
CiH Command errort%
0iH Command errorx
20H Hardware failurex 20H Hardware failurex
20H Hardware failurex
Controllier
Error
O01lH No index detected
O02H No seek complete
O3H HWrite fault
O04H DRIVE NOT READY during operation
06H Track 00 not found
10H
ID field read error
1iH VUncorrectable data error
12H Address mark not found
14H Record not found
1SH Seek error
18H
Correctable data error
18H Correctable data error
19H Bad track flag detected
1AH Format error
1CH
Illegal access'to alternate track
1DH
Illegal alternate track for format
1EH
Expected alternate track, isn`'t
1FH Alternate track = bad track
20H
1Invalid command
2iH
Illegal disk address
30H RAM diagnostic failure
31H Program memory checksum error 32H ECC diagnostic failure
* This error should never be encountered by the DSR.
TECHNICAL REFERENCE
DEVICE SERVICE ROUTINES
The errors that can be reported during given in Table 4-13 and Table 4-14.
boot are
the controller
errors
Table 4-14
Displayed Error Codes
All errors have the following message displayed: *% SYSTEM ERROR -~ 1llxx *%*
Where xx = the extended error
Extended Error
Explanation
33H
Status error on REQUEST SENSE STATUS command
40H
Time-out
wvhile waiting for WRITE DATA mode
41H
READ
MODE
while waiting for WRITE DATA mode
42H
COMMAND MODE
while waiting for WRITE DATA mode
43H
STATUS
MODE
while waiting for WRITE DATA mode
44H
HWHRITE
MODE
while waiting for READ DATA mode
4SH
Time-out
while waiting for READ DATA mode
46H
COMMAND MODE
while waiting for READ DATA mode
47H
STATUS
MODE
while waiting for READ DATA mode
48H
WRITE
MODE
while waiting for COMMAND mode
48H
READ
MODE
while waiting for COMMAND mode
4AH
Time-out
while waiting for COMMAND mode
4BH
STATUS
MODE
vhile waiting for COMMAND mode
4CH
WRITE
MODE
while waiting for STATUS mode
4DH
READ
MOBE
while waiting for STATUS mode
4AEH
COMMAND MODE
while waiting for STATUS mode
4FH
Time-out
while waiting for STATUS mode
S1H
Disk not ready
S2H
CRC error
S3H
Seek error
S4H
Sector-not-found error
SS5H
Disk (unknown) error (controller failure)
S6H
Not a TI-system disk
S7H
Disk format error
S8H
Bad boot sector CRC or bad controller
S9H
System ROM version doesn't support Winchester
TECHNICAL REFERENCE
DEVICE SERVICE ROUTINES
4.14.8
Hardwvare Interface Routines
This
interface
to the Winchester disk system implements additional
functions in a straightforward way.
The calls provide
a method
of
interfacing with the hardware that is almost hardvare-independent.
To use this interface, do a long call through
the RAM area of the Winchester disk controller
for
the
operation
in register
AH.
Other
explained with each operation.
the first doubleword in
ROM.
Place the opcode
register
wusages are
For more information, refer to paragraph 4.4.4 and to
the
table
in
paragraph 4.5.2,
The programming steps required to do the long call are given below.
WINROM DD
00000000
:LOCAL PLACE TO STORE VECTOR ;TO ROM.
; The next steps get the entry vector for the Winchester ROM ; code from the ROM data area and put it into local storage
PUSH ES
XOR AX,AX
MOV ES,AX
"
MOV ES,ES:WORD PTR 18CH
LES AX,ES:DWORD PTR 0000
MOV WORD PTR WINROM+2,ES
MOV WORD PTR WINROM,AX
POP ES
;SAVE ES ;SET ES TO 000QH ;GET WINCH RAM SEGMENT INTO ES ;GET VECTOR FOR WINCH ROM ;SAVE IN OUR DATA AREA B ;RESTORE ES
; The following steps access the Winchester ROM functions ; after the above initialization is completed
MOV
AH,OPCODE
CALL WINROM
{SET OPCODE INTO AH ;GO DO THE OPERATION
The
following
entry point.
paragraphs explain the operations available from this
TECHNICAL REFERENCE
DEVICE SERVICE ROUTINES
.
4.14.8.1
Initialize Winchester Disk System.
=
opcode:
AH = OOH
b
Entry:
PS:SI = POINTER TO DATA BLOCK
offset
Value/Use
OOH
(Word) Sector size in bytes
02H
(Byte) Track size in sectors
O3H
(Byte) Number of surfaces
04H
(Byte) Number of cylinders on disk
OSH
(Byte) Number of error retries
C6H
(Word) Reduced write current cylinder
08H
(Word) Write precomp start cylinder
OAH
(Byte) Step option
OBH
(Byte) Error-burst corrected length
Exit: Used:
AL = Error code AX, BX
This operation
being
used.
tells the disk subsystem the type of Hinchester
drive
It
sets
the hardware and software data structures so
that a user can simply call the DSR to use the drive.
4.14.8.2
Check WHinchester ROM Version.
Opcode:
AH = Ol1H
Entry:
None
Exit:
AX = BCD ROM version number
.
Used:
AX
Example:
If ROM is V1.23, then AX returns O123H
This operation returns the Winchester ROM version often useful for software-compatibility checks.
number.
This
is
TECHNICAL REFERENCE
DEVICE SERVICE ROUTINES,
4.14.8.3
Request Controller Error Sense.
Opcode: Entry: Exit: Used:
AH = O2H DsS:SI = Address of AL = Error code Z = Set if no error Data block contains AX,CX,81,DI
6-byte what
data block controller
returned.
This operation gets error information
an
error
code.
If
the controller
error codes are returned.
from the hardware
controller is broken,
and returns appropriate
4.14.8.4
Send Winchester Controller Command.
Opcode: Entry: Exit:
Used:
AH = O3H
DS:SI = Address of 6-byte data block containing command and other data (see hardware spec) AL = Error code if Carry flag is set Z = Set, C = Reset if no error Z = Set, C = Set if time-out Z = Reset, C = Set if improper controller mode AX,CX,sI
This operation sends a command for a response.
to the controller.
It does
not
wait
4.14.8.5
Get Data From the Winchester Controller.
Opcode: Entry: Exit:
Used:
AH = O4H
ES:DI = Address of buffer to receive data CX = Number of bytes of data to get
AL = Error code if Carry flag is set
Z = Set, C = Reset if no error
Z = Set, C = Set if time-out
Z = Reset, AX,CX,DI
C = sSet
if improper
controller
mode
This operation waits for the controller to provide data and then puts
it into the user's buffer.
The operation waits about 1 second before
returning
a
state or the
time-out
error.
If
the controller is in the command
status state, an appropriate error code is returned.
TECHNICAL REFERENCE
DEVICE SERVICE ROUTINES
4.14.8.6
Hrite Data to the Winchester Controller.
Opcode: Entry: Exit:
Used:
AH = O0SH ES:DI = Address of data buffer to transmit CX = Number of bytes of data to put AL = Error code if Carry flag is set Z = Set, = Reset if no error Z = Set, C = Set if time-out Z = Reset, C = Set if improper controller
AX,CX,DI
mode
This operation waits for the controller to ask
for
data
and
then
writes from the user's buffer to the controller.
The operation waits
about
1 second before returning a time-out error.
If the controller
is in the command state or the status
state,
an
appropriate
error
code is returned.
&
4.14.8.7
Get Status From Winchester Controller.
Opcode: Entry: Exit:
Used:
AH = O6H
None
AL = Error code if Carry flag is set
Z = Set, C = Reset if no error
2 = Set, C = set if time-out
Z = Reset, C = Set if controller mode is
Z = Reset, C = Reset if status indicates
has an error
«
AX,CX Sy
not status controller
This
operation waits for the status return from the controller.
The
operation waits about 1 second before returning a time-out error.
If
the controller is in the command state or the data-transfer state, an
appropriate error code is returned.
TECHNICAL REFERENCE
y
DEVICE SERVICE ROUTINES
4.14.8.8
Get and Compare Data From the Winchester Controller.
Opcode: Entry: Exit:
Used:
AH = O7H
ES:DI = Address of buffer to receive data
X = Number of bytes of data to get
AL = Error code if C flag is set
Z = Set, C = Reset if no error
Z = Set, C = Set if time-out
Z = Reget, Z = Reset,
C = Set if improper controller mode C = Reset if data does not compare;
if no compare, DI to the miscompared data
AX,CX,DI
This operation waits for compares it with the data compare, the data pointer
the controller
to provide
in the user's buffer.
If
(DS:DI) is set to point at
data
and
then
the data does not
the data address
that
does
not
compare.
After a wait of about
returns a time-out error.
If the controller is in
or the status state, an appropriate error code is
1 s, the controller
the command
state
returned.
4.14.98.9
Enable Data and Status Interrupt From Controller.
Opcode:
AH = O08H
Entry:
None
Exit:
None
Used:
AX
+
This
operation
enables
the Winchester controller interrupts to the
system bus,
However, this
operation
does
not
enable
the
system
interrupts
from
the
interrupt
controller
or from
the processor
interrupt.
4.14.8.10
Enable Status Interrupt From Controller.
Opcode: Entry: Exity: Used:
AH = OSH None None AX
This operation
system
Dbus.
interrupts from
interrupt,.
enables the Winchester controller
However,
this
operation
does
the
interrupt
controller
or
interrupts
to the
not enable the system
from
the processor
TECHNICAL REFERENCE
DEVICE SERVICE ROUTIKES
4.14.8.11
Disable
Opcode: Entry: Exity: Used:
Data and Status
AH = OAH None None AX
Interrupt
From- Controller.
c e
This
operation
disables the Winchester controller interrupts to the
system bus.
However, this operation
does
not
disable
the
system
interrupts
from
the interrupt
controller
or from
the processor
interrupt.
4.14.8.12
Poll for Controller Request.
Opcode: Entry: Exit:
Used:
AH = OBH None Z = Set if request is not active Z = Reset if request is active
AX
This operation determines when the controller is ready
for
command,
status, data in, or data out.
4.14.8.13
Format a Track.
Opcode:
AH = OCH
Entry:
DL = Drive number (4,5)
PH = Interleave factor
TM~
CX = Logical track number to format
The drive parameters must have been set using operation O.
Exit:
AL = Error code, 0 if OK
CX = Track number of error, if there is an error
Used:
AX,BX,CX,DX,s1,DI
This
operation
formats
a track on the Winchester disk.
The drive
parameters must be set up by a call to operation 0. Multiplying
the
cylinder number by the number of surfaces, then adding in the surface
number
yields
the Jlogical
track number.
The interleave factor is
typically 12 or 13 for optimum use of the DSR in reading
sequential
sectors.
The
error code returned is the controller error code with
extentions for such conditions as time-outs.
This
operation
always
does
a RESTORE
operation before the track format, so it is slow to
format a disk.
TECHNICAL REFERENCE
DEVICE SERVICE ROUTINES
4.14,8,14
Farmat an Alternate Track.
Opcode:
AH = ODH
Entry:
DL = Drive number (4,S5)
DH = Interleave factor
CX = Logical track number to format
BX = Logical track number of alternate
The drive parameters must have been set using operation 0
Exit: |
AL = Error code, 0 if OK
CX = Track number of error, if there is an error
Used:
AX,BX,CX,DX,SI,DI
Formatting routines use this operation to map a bad
track
to an
alternate
track.
The drive parameters must be set up by a call to
operation 0. Multiplying
the cylinder
number
by the number
of
surfaces,
then adding
the
surface number yields the logical track
number.
The interleave factor is typically 12 or 13 for optimum
use
of the DSR in reading sequential sectors.
The error code returned is
the controller
error
code with
extensions for such conditions as
time-outs.
4.14.8.15S
Format a Track as Bad.
Opcode:
AH = OEH
Entry:
DL = Drive number (4,S)
DH = Interleave factor
',
CX = Logical track number to format
s
The drive parameters must have been set using operation ©
Exit:
AL = Error code, 0 if OK
~
CX = Track number of error, if there is an error
Used:
AX,BX,CX,DX,S%,DI
This operation formats a defective track so that read
operations
do
not
miss
the defect.
The drive parameters must be set up by a call
to operation 0.
Multiplying the cylinder number
by
the number
of
surfaces,
then adding
the
surface number yields the logical track
number.
The factor is typically 12 or 13 for optimum use of the
DSR
in reading
sequential
sectors.
The
error
code
returned is the
controller error code with extentions for such
conditions
as
time-
outs.
This
operation
always
does
a RESTORE operation before the
track format.
TECHNICAL REFERENCE
DEVICE SERVICE ROUTINES
4.14.8.16
Check the Track Format.
Opcode:
AH = OFH
Entry:
DL = Drive number (4,5)
DH = Interleave factor
CX = Logical track number to check
The drive parameters must have been set using operation 0.
Exit:
AL = Error code, O if OK
Used:
CX = Track number AX,BX,CX,DX,sI,BI
of error,
if there
is an error
This operation checks a track for proper format.
This
routine
does
not
report
errors for tracks that have been formatted as bad tracks
or alternate tracks unless the ID fields are
incorrect.
The drive
parameters
must be set up by a call to operation 0.
Multiplying the
cylinder number by the number of surfaces, then
adding
the
surface
number,
yields
the
1logical track number.
The interleave factor is
typically 12 or 13 for optimum use of the DSR in
reading
sequential
sectors.
The
error code returned is the controller error code with
extentions for such conditions as time-outs.
4.14.8.17
Format a Winchester Drive.
Opcode:
AH = 10H
Entry:
DL = Drive number (4,S)
DH = Interleave factor
a
CX = Logical track number to begin format
The drive parameters must have been set using operation 0.
Exit:
AL = Error code, 0 if OK
n
CX = Track number of error, if there is an error
Used:
AX,BX,CX,DX,sI,DI
This operation formats a Winchester drive.
The drive parameters must
be set by a call to operation 0.
Multiplying the cylinder number
by
the number
of surfaces, then adding the surface number, yields the
logical track number.
The interleave factor is typically
12 or 13
for
optimum use of the DSR in reading sequential sectors.
The error
code returned is the controller error code with extentions
for
such
conditions
as
time-outs.
If an error
occurs
during
the drive
formatting operation, register CX returns the track in error.
If the
formatting operation must be completed, increment
the
track
number
and call
the routine again.
This could be necessary, for instance,
.if a drive defect falls directly on an address mark or ID field.
TECHNICAL REFERENCE
ASSEMBLY DRAWINGS AND LISTS OF MATERIJIALS
Section S
ASSEMBLY DRAWINGS AND LISTS OF MATERIALS
This section
contains
applicable to the Texas
assembly
drawings
and
Instruments Professional
lists
of
Computer.
materials
Title
TI Drawing No.
Page No.
Motherbeoard Assembly
Alphanumeric CRT Controller Board
Option RAM Board
IC, Numeric Coprocessor
Power Supply Assembly
Main Enclosure
Keyboard (Domestic)
System Assy,Domestic
System Assy,International
Graphics Video Controller
Electrical Pin Configuration
Communication Card
Cable Assembly (motherboard
to Floppy disk)
o
Option Kit, RAM Chips
Video CRT Controller
Cable, Video Monochrome
Cable, Parallel Printer
Wire List, Parallel Printer
Color Display Unit
Winchester Disk Controller
Outline Specification, Option Soard
Configuration, Power Cord AC
Diskette Drive
Cable Assembly, Daisy Chain
Cable Assembly, Radial
Cable Assembly, (motherboard
to external floppy)
Cable Assy, External Drive
Speech Electronics
Telephone Electronics
256/512 RAM Expansion
256 RAM Expansion
Speech/Telephone Assembly
.
Keyboard, Low Profile
Communications Loopback Plug
2223003
2223009
2223015
2221021
2223037
2223038
2223038
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2223051
2223061
223082
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2223087
:
2223088
2223100
2223105
2223106
2223107
2223219
2223220
2223231
2223278
0986289
2232326
2232327
2232329
2232332 2232373 2232403 2234243
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List of Materials
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2223005-0001
DTAGRAM,LAGIC, MOTHFRPOARD
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HEADER, SOCKFT, SHORT SOLNER T 6 CIRCUITS EA
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2210293-0003
DELAY MODULE, TAPPED, 3NS RISF TIME MAX
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ROM, SYSTEMS
EA
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ITEM 118 (2223031-0005) IN
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CONJUNCTION WITH ITEM 119
0000-0000-000
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AM ACCEPTABLE SUBSTITUTE
0000-0000-000
FOR ITEM 34,
0000-0000-000
2210188-0016
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SEE Y -1 DRAWING
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SEE T -1 DRAWING
0996151-0005
HFADER,17 PINS PER ROW,STPAIGHT ,NBL ROW
A
5935-0900-000
56
12/14/83
PART HUMBER
REV
2223093-2001
AG
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QUANTITY,
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0C001.000
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0¢001.000 0co001.000
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0090 00904 0093 00934 0093R
00001.000 0Cc002.000
0093¢C 0095
0C002.%500
0096 0097 0098
00002.000 ccool.000 00007.000
List of Materials
DESCRIPTION.ccsccesssovasecscacscsaccncns MOTHFRADAPD - PEGASUS COMPONFNT.. DESCRIPTION.ccccoocesosssscocccercsssscse UM
0996151-0002 0996151-0008 2211348-0002 2211079-0006 222049 5-0001 2220488-0003 0972537-0003 0972227-0013 0972227-0009 0972927-0025 2211700-0002 2211873-0002
0532348-0400 00R5936-0064 22231036-0001 09724870001
J9
5$935-0900-000
HEADER,20 PINS,STRATGHT,NNUBLE ROW
EA
22526--65611-140
J13
22576--65611-140
HEADER,PIN,3 PINS, STR, DOUBLF ROW
A
022526-65611-106
1-F6
022526-65611-106
HEADE1 R-R,OW 2-PNS,100 CENTER GOLD
A
SEE TI- DRAWING
17-18,F19-F20,J11-J12
SFE TI- DRAWING
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EA
SEE Ti- DRAWING
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SEE TI- DRAWING
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072619-550-0406
CR1
a
072619-550-0406
RESISTOR, SO000 OHM, 22-TURN TRIMMER
EA
SEE TI- MRAWING
R18
SEE TI- DRAWING
RES,VAR, 5000 OHMS,1/2 WATT, CERMET
EA
032997-3292W-1-502
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CAP, 220UF, 6.3V, 20%
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TRAMS MPS 6602, NPN,COMPLEMENTRY DR VER
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SEE TI- DRAWING
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*1TEM 140 IS AN ACCEPTABLE
SEE TI- DRAWING
*SURSTITUTE
SEF TI- DRAWING
STUD, EXTENSION-CRFS #4-40 X .188
EA
EYFLET-ROLLED FLANGE,. 116 0.0.4.219 L
A
PLATE,KEYBOARD PLUG
EA
1678-3036-033
JUMPER PLUG,CONNECTNR BLACK
EA
5935-0900-000
5-6
12/714/83
PART NUMBER
REV
2223003-~0001
AG
ITEM.
QUANTITY,
0100 0103 0103A 0104 0104A 0109 01094
REF 00001.000
00001.000
00001.000
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REF 00002,000 00000.002
0114 o116 0116A o117 01174 olts 01184 a1188 otisc o118p oti9 01194 01198 o119c 01190 0136 01364 01368
AR 00002.000 00001.000 00001.000
00001.000
00000.000
List of Materials
DESC . ccR evavI seoP cccsT escsI nsosO ccsN cscsse MOTHFRBOARD - PEGASUS COMPONENT.. OFSCRIPTIONcasccececovecscscoccnscncsces UM
0994396-0001
PROC.+ SITE/ODATE CODE AND SERTALTZATION
EA
0972537-C004
LED, YELLOWsRT ANG PCB MTGe2.3V,5.0VR
EA
SEE TI- DRAWING
CR2
SEE TI- DRAWING
0972537-0002
DINDE,LED GREEN RT ANGLE
EA
072619-550-0206
CR3
072619-550-0206
0972934-0011
DIODE,IN7S6A 8.2 V S% SIL VOLT REG
EA
QPL
- INT56A
CRS
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= INT56A
2223270-0001
SPECIFICATION,UNIT TEST-MOTHERBOARD
EA
0411104-0135
WASHER, LOCK-SPRING, HELICAL, #4
EA
QPL
- M535338-135
0411435-0408
TAPE, INSULATION,ELECT1/.4 IN
RL
MMM
~ S56-1/4&
0415804-0005
SFAL COMP,A*ROBIC-BLUE,GD C,10CC BOTTLE
EA
2211348-0003
HEA 1 -D ROW E ,3-R P0S,,.,100 CENTERS,GOLD
EA
SEE TI- DRAWING
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SEE T~ DRAWING
?2232425-0001
HEADER,2 X 2,MODIFIED
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EPROM, SYSTEM ROM, U62
FA
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=
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ITEM 118 USED WITH ITEM 119
0000-0000-000
IS AN ACCEPTABLE SUBSTITUTE
0000-0000-000
FOR ITEM 34,
0000-0000-000
2223031-0006
EPROM, SYSTEM ROM, U63
EA
0000-0000-000
us3
0000-0000-000
ITEN 119 USED WITH ITEM 118
0000-0000-000
IS AN ACCEPTABLE SUBSTITUTE
0000~0000~000
FOR ITEM 34,
0000-0000-000
2210704-0001
1C,LS280,9-BIT ODD/EVEN PARITY GEN/CHK
EA
V-L1ST-1$280 BURN-TN
U3l
V-LIST-LS280 BURN-IN
SUBSTITUTE FOR ITEM 24
V-L1ST-LS280 BURN-IN
57
T 12714783
PART NUMBER
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2223003-0001
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QUANTITY.
0137
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0138
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00001.000
List of Materials
DESCRIPTIONccooccrososcacase MOTHERBOARD - PEGASUS
COMPONENT,. DESCRIPTIONcccscsovavsesossscscccassscae
0535978-0058
WIRE ELEC. +SOLTD,"KYNARTM INSUL #30 AWG
2232440-0001
SPECIFICATION, TIPC MOTHERBOARD
2211415-0001
TRANSISTOR NPM
*ITEM 140 IS AN ACCEPTABLE
*SUBSTITUTE FOR ITEM 93
2223003-5001 0239999-9999
MOTHERBOARD -~ PEGASUS 1254-3004-069 CNST, SHRINKAGE
= AUTD
INSERT
UM FT A EA
EA EA
12/14/83
PART NUMBER
REV
2223003-5001
AG
ITEM.
QUANTITY.
0001
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0010
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DESCRIPTIONcccosccosscccoosasssvsssvsssse MOTHERBNARD ~ PEGASUS = AUTO INSERT
COMPONENT..« 2223004-0001 2220419-0001 2220424-0001 2220414-0001 0996420-0001
0996029-0001
2220435-0001 2220412-0001
DESCRIPTIONccecrssenssccscssvesoccccccee UM
SP11ECW6yEB69M-TMI0IO-C0T0RH0EOD-RRP0BA0ROW0AIORNCDGESSCOPRU
EA EA
USS11CEEl,EE MITTIC~-ROPDDRRROAACWWEIISNNGSGOR
BUS CONTROLLER
5
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DRTVER FLIP/FLOP
EA
EA
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TUTT11IlISC4T,ETM4APUNR4O192G~~A~,2RSCSSUANCNN5MTETT1(M4PA4PATLNLLBASSSLB2222ELTTT2EI331NNN0I7NS0TU2EB-RS0RT0UI0PT1TU)TECONTROLLER
uSS1CsEEyEsE
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INTERFERENCE
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List of Materials
DMOETSHCERRIBPOTAIRODNcc- esPsEsGcAcSUrSocs-csAsUsTsOsccINaScEcRoTscans
COMPONENT..
2220626-0001 0972900-7138
0972900-7139
2223052-0002 2211984-0007
2211102-0001 0972141-0057 2220445-0001 2223053-0001 2211984-0011 0972810-0001
ODESCRIPTION.. seccsevessessssncsscvssas UM
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TIMER .
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SEE TI-DRAWING
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EA
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~ B99-1-R4,7K
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EA
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*U28,ALTERNATE FOR ITEM 22
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NETHORK-SNT4LS221N
EA
u29
ITEM 125 (PN 2210689-0001}
1s AN.ACCEPTABLE SUBSTITUTE
0219402-7410
ICy, SNT4S10N
EA
ue
5-9
12/16/83
PART NUMBER
REV
2223003-5001
AG
ITEM,
QUANTITY.,
0028
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00001.000
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List of Materials
DESCRIPTION :ccecscvecccocsosscsssscsvases MOTHERBOARD - PEGASUS = AUTO INSERT
COMPONENT.. DESCRIPTION:ccooossvseococcasccccccccnss UM
0972900-7420
NETWORK SN74LS20N
EA
u32
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IS AN ACCEPTABLE SUBSTTITUTE
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EA
TI
~SNT4LS32N
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ITEM 127 (PN 2210621-0001}
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2211118-0005
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U35,u36,U3T,U38,uU39
U40,U41,U42,U43
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0996755-0001
IC,SN74LS245N BUS XCVR TRANSITION
EA
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-
ug,Ul12,U52,U61
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2220415-0001
IC+FLOPPY DISX CONTROLLER,PLASTIC
EA
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2223054-0002
ROM FLOPPY SYSTEM CONTROL
EA
u1l9
2211984~0006 2211771-0001
1CeBLANK PROGRAMMABLE ARRAY OF GATES
EA
SEE TI- DRAWING
*U19, ALTER FOR ITEM 39
SEE TI- DRAWING
1C, SNT4LS620N,EXTERNAL, TEMPERATURE COMP EA
SEE TI- DRAWING
5-10
12/14/83
PART NUMBER
REV
2223003-5001
AG
ITEM. 00454
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00538
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0055
00001.000
List of Materials
DESCRIPTIOMccaosvcasscccccsse MDTHERADARD - PEGASUS - AUTD
COMPDONENT.,. 2211126-0001 0972999-4040 0972669-0001
DESCRIPTIONcceccscsoncacecccsanscecasass
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SEE TI- DRAWING
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=
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u20
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IS AN ACCEPTABLE SUBSTITUTE
0222222-7416
NETWORK SNT416N
EA
=SN7416N
U23,U24 ~SNT416N
0222222-7407
NETWORK-SNT4OTN
FA
TI-
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0972900-7404
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EA
uto
TTEM 133 {PN 2210604-0001) 1S AN ACCEPTABLE SUBSTITUTF
0996%508-0001
IC,T4LS393N DUAL BINARY COUNTER
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0D1295-74LS393N
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ITEM 134 (PN 2210727-00011
001 295-74L5393N
3
1S AN ACCEPTABLE SUBSTITUTE
001295-74LS393N
0222225-2311 . NETWNRK,COMPARATORSE,F DRAWING
A
SEE
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12/14/83
PART NUMBER
REV
2223003-5001
AG
ITEM.,
QUANTITY,
00554
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00001.000
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00001.000
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0070
00002.000
00704
0071
00001.0C0
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0072
00008.000
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00728
0073
00002.000
List of Materials
DESCRIPTION.ccsossscccanscoencnscocccanses MOTHERBOARD - PEGASUS - AUTD INSERT
COMPONENT.. DESCRIPTIONcccecsoenscacscaccscsccoscccs
2211349-0001 0996304-0001
U6%
SEE
= T1 DRAWING
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IC+LM386,AMPPWLR,,A uon10
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0972946-0089 0972946-0081 0972946-0085 0972946-0057 0972946-0065 972496-0001
RES FIX 10K OHM 5% «25 W CARBON FILN
1658~
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RES FIX 6.8K DHM 5 % 25 W CARBON FILMW
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UM
EA EA EA EA FA EA EA EA A EA EA EA EA
EA
5-12
12/14/83
PART NUMBER
REV
2223003-5001
AG
ITEM,
QUANTITY,
0073a 0074 00744 0075 0075A
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List of Materials
DESCRIPTIONccocevcvsococcssecossssocance MOTHERBOARD - PEGASUS - AUTO INSERT COMPONENT.. DESCRIPTION.ccescosencscvncsasccasrasnee UM
0972946-0049 13972934-0010
0539370-0465
0539370-0430 0972757-0019 0972924-0038 0972757-0009 0972924-0021 0972757-0043 0972763~0013 0972763-0025
0972763-0021 0972763-0001
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EA
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DIODE, INTS5A 7.5 V 5% SIL VOLY REG
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RES FIX FILM 6.81K OHM 1% .25 WATT
EA
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CAPoFIXED CER 3300PF 10% S0V
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EA
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CAPACITOR, .10UF 50V FX,CERAMIC DIEL
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COR CA-CO3Z5U104Z050A
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5-13
12/146/83
PART NUMBER
REV
2223003-5001
AG
1TEM,
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DESCRIPTION svececossocosscccsasanacanns MOTHERBOARD ~ PEGASUS - AUTO INSERT
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DESCR e ceI conP scsT sonI cascO savN once ncnne HOTHEPRNARD - PFEGASUS - AUTD INSFRT
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DESCRIPTION.eecccoscosnsvsaccscsoasncssscsns MOTHERBDARD - PEGASUS - AUTO INSFRT
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DESC e ssR occI essoP oncT csesI csaC cacoM scses ALPHA CRT CONTROLLER
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DESCo R cccI eossP vosT ssccI sscO sccvN ancon ALPHA CRT CONTROLLER
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List of Materials
DESCRIPTIONGsocecoevvcovenccccncsncscocs ALPHA CRT CONTROLLER - AUTO INSERT
COMPONEN.To DESCRIPTION acecssossccscncsee
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List of Materials
DALEPSHCARIPCRTTIONC.OcNcTRcOsLsLsEcRsso-scAcUaTsOassINcSsEsRsTsacsan
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0219402-7486 0219402-7610 0972900-7432 0219402-7400 0219402-7404 0972900-7404 0972900-71T4
1S AN ACCEPTABLE SUBSTITUTE
NETWORK SNT4S86N U3 ITEM 117 (PN 2210749-0001}) 1S AN ACCEPTABLE SUBSTITUTF IC, SNT4SION u33 ITEM 118 (PN 2210740-0001) IS AN ACCEPTABLE SUASTITUTE TUTTTI1I11SN4NTEEETTMHAWNOORR1KK1--A-9-SCSSSNCNNSNTETTNS(T4P44PTN4LNTLL4TLSASSL4S3BIISS3I2L223O222ENNN2ON1NN06S2U1B-S0T0I0T1U)TE. u3s
ITEM 120 (PN 2210735~0001) IS AN ACCEPTABLE SUBSTITUTE NETWORK SNT4S04N u3s ITEM 121 (PN 2210738-00011 1S AN ACCEPTARLE SUBSTITUTE NETWORK SNT4LSO4N u3? ITEM 122 (PN 2210604-0001) 1S AN ACCEPTABLE SUBST ITUTE NETHORK SNT4LS1T4N
u18
ITEM 123 (PN 2210674-0001}
UM EA
EA FA "EA EA « A EA EA
5-23
12/14/83
PART NUMBER
REV
2223009-5001
R
ITEM.
QUANTITY.
0026C
0029 00294
00001.000
0030
00001.,000
0030A
0031
00002.000
00314
0032
00001,000
0032A
0033
00001.000
00334
0034
0C001.000
00344
0035
00006 .000
00354
0036
00002.000
00364
0037
00001. 000
00374
0039
00014,000
00394
00398
0040
00010,000
00404
00408
0047
00001,000
00474
00478
List of Materials
DESCRIPTION ccssccscasesvsosnnssoscasscses ALPHA CRT CONTROLLER - AUTO INSERT
COMPONENT., o DESCRIPTIONGcceveccsccncasannssscsssssees
0972946-0041 0972946-0074 0972946-0066 0972946~0091 0972946-0076 09729646-0084 0972946-0081 0972946-0057 0972757-0009
TS AN ACCEPTABLE SUBSTITUTE
RRRRRRRRRRRRRRCRRRRRRRRRRRRRRRRRR146OS2EEEOAOOEEEOOOOOEEOOOOOO1O3THSSSHPHHSSSHHHHHSSHHHHWHH2,4R,R1RBFFFFFFFFF01I,IIIIIIII3XXXXXXXXXR-----==----==--= I,CRRR3RRRRR4RRRRRR6RR12141RE2-7-.----0---=----.--...R0102202222222222222224715555K55%55555K555KK51KK,4RTOOOOODOO1OHHHHHHHH4PMMMMMMMMF,R5LS55555S %%E10T%%%%%%..22......55222222S555555OVWW
W W
W W W W
CARBON CARBON CARBON CARBON CARBON CARBON CARBON CARBON
3
FILM FILM FILM FILM FILM FILM FILM F+ ILM
c1
0972763-0013 0972763-0025 0219402-7174
CAP,FIXED .010UF 50 VOLTS
004222-MC10SE0132
4,C5,C7,(8,(9,010,C11,C12
004222-MC1051032
C13,C14,C15+C16,C17,C18
004222-MC105E1032
CAPACITOR, .10UF 50V FX,CERAMIC
COR CA-CO3Z5U1042Z050A
27,30,C31,C32,C33,C34
COR CA-CO3Z5U1042050A
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NETWORK SMT4S174N
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ITEM 124 (PN 2210763-00011%
TI-
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DIEL
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A
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5-24
12/14/ 83
PART NUMBER
REV
2223009-5001
R
ITEM,
QUANTITY,
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00001.000
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ni13e
List of Materlals
DESCRIPTION ecoovvovoscsssscssansosscsse ALPHA CRT CONTROLLER = AUTO INSERT
COMPONEMTo. NESCRIPTIDNccesococossscecosassssnsccccs UM
1S AN ACCEPTARLE SUBSTITUTF
TI=-
~SNT4S1T4N
0219402-7157
NETHWORK SNT4S1S5TN
EA
0972946-0079 2210660-0001 2210695-0001 2210721-0001 2210764~0001 2210694-0001 2210669-0001 2210662-0001 2210761-0001
u20
ITEM 125 (PN 2210759-0001)
1S AN ACCEPTABLE SUBSTITUTE
RES FIX 3.9K OHM S % .25 W CARBON FILNM
EA
ROH
- R=25
R1S
ROH
= R=2S
ICyLS155,DUAL 2-LINE TO 4-LINE DECODER
EA
V-LIST-t.5155 BURN-IN
us
V-LIST-LS155 BURN-TN
SUBSTITUTE FOR ITEM 7
V-LIST-LS15% BURN-IN
IC,LS245,0CTAL BUS.XCIVER,3ST.OUTPUY
EA
V-LIST-LS245 BURN-IN
urT,U8,U?
V-LIST=LS245 BURN=-IN
SUBSTITUTE FOR ITEM 8
V-L1ST-15243 BURN~IN
1C,LS374,0CTAL D-TYPE FLIP=-FLOP
EA
V-LIST=LS374 BURN-IN U10,UL1,UI4,UL5
V-L1ST-1.$374 BURN-IN
>
SUBSTITUTE FOR ITEM 9
V-LIST=L5374 BURN-IN
1C,S179,QUADF/F,DOUBLE RATL QUTPUT
A
V-LTS5T=S173 BURN-IN
>
Ut6,uUl17,u27
V-LIST=S175 BURN=-IN
SUBSTITUTE FOR ITEM 10 V=L I5T=5175 BURN-IN
1C,1.5264,0CTAL BUF/LINE DRIVER/RECEIVER
EA
V-LTST-L5244 BURN-IN
uUlz,ul3
V-LIST-LS244 BRURN-TN
SUBSTITUTE FOR ITEM 11
V-LIST-L5244 BURN-IN
IC+LS166,8-BIT PARALLFL/SERTAL INPUT
EA
V-LIST~LS166 BURN-IN
u19
V-LIST-LS166 BRURN-IN
SUBSTITUTE FOR ITEM 12
V-LTST-LS166 BURN-IN
IC+LS157,QUAD 2-LINE TD 1-LIME DATA SELE EA
V-LIST=-L5157 BURN-~IN
u2t,022,u23
V-LIST-LS187 BURN-IN
SUBSTITUTE FOR ITEM 13
V-LIST=-LS157 BURN-TN
1Cy S163, SYNCHRONOUS 4-BIT COUNTER
EA
V=LIST~S163 BURN=-IN
u24
V-LIST-S163 BURN-IN
SUBSTITUTE FOR ITEM 14
V-L1ST-S163 BURN=-IN
5-25
12/14/83
PART NUMBER
REV
2223009-5001
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ITEN,
QUANTITY,
0114
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01144
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01228
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0000.200
01234
01230
0124
0000C.000
List of Materials
ADLEPSHCARIPCRTTIONCcOaNvTReOcLsLsEsRace-ssAsUsTcQcscIcNSnEnRcTosance
COMPONFENT.. DESCRIPTINM.cucececsssocccncscsssencanse UM
2210631-0001 2210649-0001 2210614-0001 2210749-0001 2210740-0001 2210621-0001 2210735-0001 2210738-0001 2210604-0001 2210674-0001 2210763-0001
IC,LS74,0UAL D FLIP-FLOP W/PSFT & CLR
EA
V-LIST-LS74
BURN-IN
u28,029
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BURN-IN
SUBSTITUTE FOR ITEM 16
V-LIST-LST4
BURN-IN
1C,15125,QUAD BUS BUFFER W/3-STATE OUTPU EA
V-LIST-LS125 BURN-IN
u3o
V-LIST-LS125 BUPN-IN
SURSTITUTE FOR ITEM 17
V-LIST-LS125 BURN-IN
IC,LS20,4D4 UIANPLUT NAND
EA
V-LIST-LS20
BURN-TN
U3l
V-LIST-L520
RURN-TN
SUBSTITUTE FOR ITEM 13
V-LIST-LS20
BURN-TN
1C,S86,QUAD, 2-INPUT EXCLUSIVE 0R
A
V-LIST-S86 BURN-IN
u32
V-L1ST-5S86 BURN-IN
SUBSTITUTE FOR ITEM 19
V-LIST-586 BURN-IN
1C,yS10, TRIPLE, 3-INPUT PNSITIVE AND
EA
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SUBSTITUTE FOR ITEM 20
V-LIST-S10 BURM-IN
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V-L1ST-S00 BURM-IN
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V=-LIST~-S04 BURN~TN
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SURSTITUTE FOR ITEM 23
V-LIST-S04 BURM-IN
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SUBSTITUTE FOR ITEM 26
V=LIST-LS174 BURN-IN
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V-LIST-5174 BURN-IN
5-26
2/14/84
PART MNUMAER
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2223009-5001
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ITEM,
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0000.700
01254
01253
List of Materials
OALFPSHCARIPCTRITNN,CONsTuRuOvLeLeFsRs
sesscsescsersoscns AUTD INSFRT
COMPONTNT.. 2210759-0001
DESCRIPTION..ceeeoneeenscasasoncosencees UM
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List of Materials
DESCRIPTIOMNeescesenvoscccssassancccccnce FXPANSTION RAM
COMPONENT.. 2223017-C001 2210147-0012
0974396-N001L 2223212-n001 2223015-5001 7239999-9999
NESCRIPTINN.ccceccoosvocscscsccascsesaas
SCHEMATIC, EXPANSION RAM
SOCKETDIP,16-PIMNS,L(M PROFILF SEE T -1 DRAWING XULO,XULT,XUL2,XUL3,XUL4 SFE T -1 NRAWING XULS, XUL16, XULT, XUJ18, XULD SEE T -1 DRAWIMNG XU20, X214 XU22,XU23,XU24 SEE T -1 DRAWING XU254XU26,XU27 SEE T -1 DRAWING PROC ., STTF/DATE CONE AND SFRIALTZATINN
SPEC,UMIT TEST-E£XPANSION RAM
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12/14/83
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DESCRIPTION ceeaacsoscssvocnccsscacsacces
EXPANSION RAM (12AK)
-
COMPNNENTe 2223017-0001 2211118-0004
2210188-0012
0994396-C001 2223272-0001 2223015-5002 02319999-9979
DESCRIPTFIOM.cceccacccavovssoacncoscsacnoe
SCHEMATIC,EXPANSION RAM
IC,64K-BIT DYNAMIC RAM,150NS TA/ROW TMS416-4-15NL 1110,U11,U12,U13,U14,U15,U16 THMS416-4-15NL ui7,u18 TMS416-4-15SNL SOCKET,DIP,16-PINS,LOW PROFILE SEE T ~1 DRARING XULO XUY 1, XUL2XUL3X1,14 SEE T -1 DRAWING XUL1S,XUL6,XULT,XU18,XU19 SEF T -1 DRAWING XU20¢XU21¢XU224X112X312,4 SFF T -1 DRAWING XU25y XU26, XU27 SFE T -1 DRAWING PPNC.s STTE/DATE CODE AND SERTALIZATION
SPEC,UNIT TE%Y-EXPANSIHN RAM
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[128K)-AUTO
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12/14/83
PART NUMBER
REV
2223015-0003
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QUANTITY.
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List of Materials
DESC s seR ecesI avsP acnaT sascI cssO scsaN vocnes EXPANSION RAM (192K}
COMPONENT.. DESCRIPTION:csocaceoncacscccscssssocscscss UM
2223017-0001
SCHEMATIC,EXPANSTION RAM
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TMS416-64-15NL
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TM5416-4-15NL
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2223272-0001
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12714783
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COMPONENT.. DESCRIPTIONeseccocsscess
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2223017-0001
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0994396-0001
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5-31
12714/83
PART NUMBER
REV
2223015-5001
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00084
List of Materials
DESCRIPTIONeeececsacossaansascssccccocce EXPANSTOMN RAM ~AUTO INSERT
COMPONENT.. DESCRIPTION.ecsevscseosonoesnonassananss UM
2223016-0001 2211118-0004 2220360-0002 0972763-0001
0972763-0025
0972924-0018
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2223015-5002
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COMPONENT., DESCRIPTION.ceccrvacvsnsscovscssnoscocas UM
2223016-0001 2211118-0004 2220360-0002 0972763-0001
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EA
1669-0000-000
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12/14/83
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12/14/83
' PART NUMBER
RFV
2223015-5004
J
ITEM.
QUANTITY.
cootl
00001.000
0003
00027.000
00034
00038
0003C
0003n
0005
00002, 000
00054
0006
00010.000
00064
00068
oco7
00011.000
0007A
00078
0008
00002.000
0008A
List of Materials
DESCRIPTION.cccosossessccacacsaans EXPANSION RAM (192K)-AUTO INSERT
COMPONENT. DESCRIPTION cessacsnacsascacsvocssnnsace UM
2223016-0001 2211118-0004 2720360-0002 0972763-0001
0972763-0025
0972924-0018
PHB JEXPANSION RAM
EA
1669-0000-000
101 64K=-BIT DYNAMIC RAM, 1SONS TA/ROW
A
TMS416=4~15NL
ULyU24UUS4311644 U UT & 4UR,oD
TMS416=-4=~15NL
1C,OCTAL DRAM DRIVFR, 3-STATE NUTPUTS
A
SFE TI- DRAWING
uz8,u29
SEE TI- DRAWING
CAPACITOR,,001UF S0V FX CERAMIC OTEL
A
COR CA-CO02Z5U1022100A
C1,C2+C34C49CS54C6,CT79CB4CO
COR CA-C0225U1022100A
clo
COR CA-C02I5U10271004A
CAPACITOR,.lOUF 50V FX,CERAMIC DTEL
EA
COR CA-C0325U1042050A
C11,C12,C13,C14,C15,C16,C17
COR CA-CO3IZ5UL1042050A
18,19,C20,C21
COR CA-CO325U104Z050A
CAP FIX TANT SOLID 6.8 MFD 10 % 35 VOLT A
QpPL
-M39003/1-2304
Cc22,23
QPL
~M39003/1-2304
DESCRIPTIONc coosverccsccacscecccnsscnnse AUTO INSERT TAPF FOR-0004 COMPONENT.o DFSCRIPTION.ccsccccccccsacaasscnsssscacss UM
2223016-0001 2211118-0004
2220360-0002 0972763-0001 0972763-0025 0972924~0018
PHB ,EXPANSINON RAM
2
EA
1669-0000-000
1C, 64K-BIT DYNAMIC RAM,]150NS TA/ROW
EA
TMS416-4~15NL
Ul,U2,U3,U4,U5,U6,UT,U8,U9
TMS416-6-15NL
U10,U11,U12,U13,Ul4,Ul5,U16
TMS416~4-15NL
Ul7,U18,U19,U20,U21,U22,U23
TMS416-4-15NL
U24,U25, U269 U27
TMS416~4~15NL
IC,OCTAL DRAM DRIVER, 3-STATE OUTPUTS
EA
SEE TI- DRAWING
1y28,u29
SEE TI- DRAWING
CAPACITOR,.001UF S0V FX CERAMIC DIEL
EA
COR CA-CO21I5UL027100A
C14C2,C3,4C44C5,C6,4C7,C8,C9
COR CA-C02Z5U102Z100A
clo
COR CA-C02Z5U1027100A
CAPACTTN. RLO,UF 50V FX,CERAMIC DTEL
EA
COR CA-CO315U1047050A
Cl14C12,C13,4C14,4C15,C16,C1L7
COR CA-CO3I5U10420504
C18,19,C20+C21
COR CA-C0375U1042050A
CAP FTX TANT SOLID 6.8 MFD 10 % 35 VOLYT EA
QrPL
-M39003/1-2304
22,C23
QPL
=M39003/1~2304
6-33
12/14/83
PART NUMBER
REV
2223015-8001
J
ITEM,.
QUANTITY,
0001
00001.000
List of Materials
DESCRIPTIONcercovsovevsccccsccsscssccsccas EXPANSION RAM - SFARFS
COMPONENT,, DESCRIPTINMN eecosscncnsosssossscsscsasnce
2223015-0001
FXPANSION PAM 1254-3015-042
UM EA
12/714/83
PART NUMBER
REV
2223015-8002
J
ITEM.
QUANTITY.
0001
0C001.000
NESCRIPTION ceoescacoacecsssvoccccncccncse EXPANSION RAM (128K) - SPARES
COMPDONENT.. OESCRIPTION:ccaccasessesasccassssoscasss
2223015-0002
EXPANSION RAM (128K) 1254-3017-006
UM EA
12714793
PART NUMBER
REV
2223015-8003
J
ITEM.
QUANTITY.
0001
00001.000
< «
DESCRIPTION . ceveovas
.............-.:-
EXPANSION RAM {192K) - SPARES
COMPONEMT.. DESCRIPTION.cseesscscascccocaccssssscccs
2223015-0003
EXPAMSION RAM (192K} 1254-3019-008
UM EA
12/14/78)
PART NUMBER
REV
2223715-8004
J
ITEM.
QUANTITY.
0001 0002
00001.500 REF
DESCRIPTINNceeseoscoasacsccnccacanssscas RAMJEXPANSION 192K COMPLETE/SPARES
COMPONENT.. DESCRIPTIONGccescensccccascsscsasscccsce
2223015-0004 2231993-0001
EXPANSION RAM (192K} COMPLETE 1254-3021-023 SERVICF PACK INDEX~RMR
UM EA EA
5-34
v
2221021
L,. 1 |
APPLICATION
NEXT ASSY
USED ON 8501
REVI
+ LEVEL 2
I
REVISIONS
l 5962 2500
DESCRIPTION
I
DATE
I APPROVED
1.0
SCOPE:
£e
THIS SPECIFICATION COVERS THE REQUIREMENTS FOR AN N-CHANNEL, DEPLETION
LOAD MOS NUMERIC DATA PROCESSOR INTEGRATED CIRCUIT WHICH EXECUTES TRANS-
CENDENTAL FUNCTIONS AND PROVIDES ARITHMETIC AND LOGICAL INSTRUCTION
SUPPORT FOR NUMERIC DATA.
1))
ABSOLUTE MAXIMUM RATINGS: SEE TABLE I.
2.0
APPLICABLE DOCUMENTS:
WHERE THIS SPECIFICATION REFERS TO ANOTHER DOCUMENT, THAT DOCUMENT IS
OF THE ISSUE IN EFFECT ON THE DATE OF INVITATION TO BID OR REQUEST FOR
PROPOSAL. REFERENCED DOCUMENTS APPLY TO THE EXTENT SPECIFIED HEREIN.
THIS SPECIFICATION GOVERNS WHEN A REFERENCED DOCUMENT CO&FLICTS.
CAUTION: & STATIC SENSITIVE
EZLECTROSTATIC DISCHARGE CAM DAMAGE THIB COMPONENT, PRODUCT MUST BE BHIPPED IN ANTISTATIC CONTAINER AND MAINTAINED IN ANTISTATIC PACKAGING, INDIVIDUAL DEVICKS BSHOULD BE HANDLED ONLY AT STATIC-FREE WORK "A`I'lo_fl.
REV
SHEET
REV STATUS OF SHEETS
REV SHEET
5
11213
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|7 |8 {9 |10]11f12|13}14]|15]16]17
{@"~ TEXAS INSTRUMENTS SI-METRIC Oightsi Sywtame Growp
INTEGRATED CIRCUIT, NUMERIC DATA PROCESSOR
| THRD ANGLE
[V mre----.
SIZE Fseuuo
/g
SCALE NONE
£ o
DRAWING NO
2221021 sHEET 1 OF 17
FlLiacl
5-35
PIN (TCOOPNNEVCITEIW)ONS
GNDE 1
{M1g) ap14 [1f 2
(A13) A013 [ 3
(((AAA11102)))
012 oAp11yo
[ [
4 )6
((nagg)) aanogg [[}}|7e
Aoy Q|9
asoosg [[ fu110
ADg E 12
ADrAo3zr [[Jffa1s13
Ao [ 16
ne [
ne [J]1s
Lk ] 19
GNO [t 20
40 :] Vee
19 |[] a015
328|3|[J ma1r6//s5q3
3356 ||[3J AA1e8//s5s5
u | swessy 33 |[J mseT,
2|0
u |3
mvwrET,
30 |3 ne
29 11 e
22286|100|H 5%%
25 {17 aso
26|17 o5y 23|[3 susy
22 |[J ReAoy
21 |[J Reser
FIGURE 2
(@x\ TEXAiBalSTelctlaatIlSaNrltoSronTleaRlAaUtvoMlEeiNoTS
A SHeer 22210421
[REV)
Ti-e280.4
f
5-36
DC CHARACTERISTICS (Ty = 0 9C TO 70 ©C, Vgg = 5V + 10%)
SYMBOL
PARAMETER
TEST CONDITIONS
VIL |INPUT LOW VOLTAGE
Viy |INPUT HIGH VOLTAGE
VoL |OUTPUT LOW VOLTAGE
ToL = 2.0 mA
VoH [|OUTPUT HIGH VOLTAGE
Igy = -400 wA
TcC |POWER SUPPLY CURRENT
TA = 25 OC
TLr |INPUT LEAKAGE CURRENT
0V < VN < Ve
1,0 |OUTPUT LEAKAGE CURRENT
0.45 V < VouT < Vg
VCL |CLOCK INPUT LOW VOLTAGE
VCH |CLOCK INPUT HIGH VOLTAGE
CIN |CAPACITANCE OF INPUTS
fo = 1 MHz
Cio |CAPACITANCE OF I1/0 BUFFER
fc = 1 MHz
[(RAQD/0G-T1)5, ANAD16-CALlK9, BHE, S2-S0,
CouT |BCUSAYP,ACITIANNTCE OF OUTPUTS
fe = 1 MHz
TABLE 11
MIN
MAX | UNITS
-0.5 0.8
v
2.0 |Vect0.5 | v
0.45
v
2.4
v
475
mA
+10
uA
+10
vA
-0.5
0.6
v
3.9 |veerl.0| v
10
pF
15
pF
10
pF
AC CHARACTERISTICS (Tp = 0 ©C TO 70 ©C, Vge = 5 V + 10%)
TIMING REQUIREMENTS
SYMBOL
PARAMETER
TEST CONDITIONS
TCLCL | CLK CYCLE PERIOD
TCLCH | CLK LOW TIME
TCHCL CLK HIGH TIME
TCHICHZ | CLK RISE TIME TCL2CL1 | CLK FALL TIME TOVCL | DATA IN SETUP TIME TCLDX | DATA IN HOLD TIME TRYHCH | READY SETUP TIME TCHRYX | READY HOLD TIME TRYLCL | READY INACTIVE TO CLK TGVCH | RQ/GT SETUP TIME TCHGX | RQ/GT HOLD TIME TQVCL | QSg-1 SETUP TIME TCLQX | QSp-1 HOLD TIME TSACH | STATUS ACTIVE SETUP TIME
FROM 1.0 V T0 3.5 V FROM 3.5 V T0 1.0 V
TABLE "111
Ti--e230.
@TEXAS INSTRUMENTS INCORPORATEOD T oe ?
? MIN ~ 200 (2/3 TCLCL) - 15
(1/3 TCLCL) + 2
30 10 (2/3 TCLCL) - 15 30 -8 30 40 30 10 30
MAX [UNITS 500] ns
4 10 10
v ns
2221021
REV
A
SHEET 5
6-37
|
TABLE 111 - CONT
AC CHARACTERISTICS (T4 = 0 9C T0 70 OC, Vgc = 5 V + 10%)
TIMING REQUIREMENTS
SYMBOL
PARAME TER
TEST CONDITIONS
TSNCL | STATUS INACTIVE SETUP TIME
TILIH | INPUT RISE TIME (EXCEPT CLK)
FROM 0.8 V T0 2.0 V
TIHIL | INPUT FALL TIME (EXCEPT CLK)
FROM 2.0 V T0 0.8 V
TCLML | COMMAND ACTIVE DELAY [2]
TCLMH | COMMAND INACTIVE DELAY [2
TRYHSH | READY ACTIVE TO STATUS PASSIVE
TCHSY | STATUS ACTIVE DELAY
TCLSH | STATUS INACTIVE DELAY
TCLAV | ADDRESS VALID DELAY
TCLAX | ADDRESS HOLD TIME
TCLAZ | ADDRESS FLOAT DELAY
TSVLH | STATUS VALID 10 ALE HIGH [2]
CL = 20 - 100 pF (FOR ALL
TCLLH | CLK LOW T0 ALE VALID [2)
MOl E IoAb
TCHLL | ALE INACTIVE DELAY [2
TCLDV | DATA VALID DELAY
TCHDX | DATA HOLD TIME
TCVNV | CONTROL ACTIVE DELAY [2]
.
TCVNX | CONTROL INACTIVE DELAY
.
"
TCHBY | BUSY AND INT VALID DELAY
TCHDTL [ DIRECTION CONTROL ACTIVE DELAY
=
TCHDTH | DTRECTION CONTROL INACTIVE DELAY [2
TCLGL | RQ/GT ACTIVE DELAY _
CL = 40 pF (IN ADDITION
TCLGH | RQ/GT INACTIVE DELAY
T0 NDP' SELF-LOAD)
TOLOH |OUTPUT RISE TIME
FROM 0.8 V T0 2.0 V
TOHOL | OUTPUT FALL TIME
FROM 2.0 V T0 0.8 V
NOTES: [1] APPLIES ONLY TO T2 STATE (8 ns INTO T3)
SIGNAL AT BUS CONTROLLER SHOWN FOR REFERENCE ONLY, SEE FIGURE 3
APPLIES ONLY TO T3 AND WAIT STATES
[4] REFERS TO THE NUMERIC DATA PROCESSOR SPECIFIED BY THIS DOCUMENT
TABLE 111
MIN [mAx |units
30
ns
20 | §
12
10 | 3
10 | 35
110
10 {110
10 |13
10 [110
10
TCLAX | 80
15
15
15
10 {110
10
5 | a5
10 | 45
10 [150
50
30
0| 8
o | 8s
20 |y
12 | ns
Ti-ezss-t
=
f[LEAXS RNS TRR UMETSR [P
SHEET 22210621
REV
5-38
6.0 6.1
Ti-a2se.q
|
APPLICATIONS INFORMATION: (FOR REFERENCE ONLY)
PIN DESCRIPTIONS:
NOP REFERS TO THE NUMERIC DATA PROCESSOR SPECIFIED BY THIS DOCUMENT.
SYMBOL
TYPE
NAME AND FUNCTION
IAD15-ADg
AAA111789///555456,, A16/S3
1/0
ADORESS DATA: THESE LINES CONSTITUTE THE TIME
MULTIPLEXED MEMORY ADDRESS (T)) AND DATA (T2,
T3, T, T4) BUS
1/0
AMTMTANS(3RAO6IADH,,ELSOTDITNIRGSOEHHT.SNIS)y4INSS,,,CPIRUG1TOSNMDAWASPIENNHURDDMFIRAOLOIIVWECRNCAHTSYEGAII43:SN.CLSTSHA5MOABRERLEMATEDFIOHSDOURERDRYR1RISOAENENLSNNGSWEDDOSIPPARNPTYVEHTSEyREMLCCDSAIOOOETNNNNTLIETITOHASORTWERNLN.OOSDOISLERLN,FSLEOCESRUATDRRHWSEERHTMDSEEAEUBENNTMURTTUSOIHSLRNEALYYGNICNYFIECOONOTESLUpNFPXR,EEOETSRRE,-AR--
1/0
BUS HIGH ENABLE: DURING Ty THE BUS HIGH ENABLE
SIGNAL (BHE) SHOULD BE USED TO ENABLE DATA ONTO
THE MOST SIGNIFICANT HALF OF THE DATA BUS, PINS
D15 - Dg
1/0
STATUS: FOR NDP DRIVEN BUS CYCLES, THESE STATUS
LINES ARE ENCODED AS FOLLOWS:
52
ST S
0 (LOW) X X UNUSED
1 (HIGH) 0 O UNUSED
1
1 READ MEMORY
4
---- O
1
0 WRITE MEMORY
1
1 PASSIVE
RQ/GTo RQ/GT]
STATUS IS DRIVEN ACTIVE DURING T4, REMAINS VALID DURING T1 AND T2, AND IS RETURNED TO THE PASSIVE STATE (1, 1, 1) DURING T3 OR DURING Ty WHEN READY IS HIGH
1/0
REQUEST/GRANT: THIS REQUEST/GRANT PIN IS USED BY
THE NPX TO GAIN CONTROL OF THE LOCAL BUS FROM THE
CPU FOR OPERAND TRANSFERS OR ON BEHALF OF ANOTHER
BUS MASTER. IT MUST BE CONNECTED TO ONE OF THE
TWO PROCESSOR REQUEST/GRANT PINS.
1/0
ARNEOQTUHEESRT/GLROACNATL: BUSTHIMSASTREERQUETOST/FGORRACNET THPEIN NDIPS UTOSEDREQBUYEST THE
LOCAL BUS. TIF THE NDP IS NOT IN CONTROL OF THE BUS
WHEN THE REQUEST IS MADE THE REQUEST/GRANT SEQUENCE
IS PASSED THROUGH THE NDP ON THE RQ/GTg PIN ONE
CYCLE LATER. SUBSEQUENT GRANT AND RELEASE PULSES
ARE ALSO PASSED THROUGH THE NDP WITH A TWO AND ONE
CLOCK DELAY, RESPECTIVELY, FOR RESYNCHRONIZATION.
RQ/GT] HAS AN INTERNAL PULLUP RESISTOR, AND SO MAY
BE LEFT UNCONNECTED
dpTeasannaTe DIGITAHLOUSSYTSOTNE.MSTEOXIAVSISION
Al e
SHEET
15
IREV
T;
5-39
6.1
PIN DESCRIPTIONS: CONT
SYMBOL
QQss1o,
INT BUSY
READY RESET CLK vVee GND
TYPE
NAME AND FUNCTION
1
QS1, QSo: QS1 AND QSo PROVIDE THE NDP WITH STATUS TO ALLOW TRACKING OF THE CPU INSTRUCTION QUEUE
0 Qs(LOW)
Qs0o NO OPERATION
0
1 FIRST BYTE OF OP CODE FROM QUEUE
1 (HIGH) 0 EMPTY THE QUEUE
1
1 SUBSEQUENT BYTE FROM QUEUE
0
INTERRUPT: THIS LINE IS USED TO INDICATE THAT AN
UNMASKED EXCEPTION HAS OCCURRED DURING NUMERIC
INSTRUCTION EXECUTION WHEN NDP INTERRUPTS ARE
ENABLED. INT IS ACTIVE HIGH
0
BUSY: THIS SIGNAL INDICATES THAT THE NDP NEU IS
AATEIONCCXTTEIICTTVVUHHEEETEINCCUHGIAPNGSUTHE`IASL NOFUTTHEMESEATRNIECXPUICNINEMNPASTSTTIKOROENUDPCRTOIEIVSOXICNDE.CEPLTEIASORYNIETNDC.HBIRSUOSYNCBIUOZSNRAYNETEMICAOITISNEN.DS
1
READY: READY IS THE ACKNOWLEDGMENT FROM THE ADDRESSED
MEMORY DEVICE THAT IT WILL COMPLETE THE DATA TRANSFER.
THE RDY SIGNAL FROM MEMORY IS SYNCHRONIZED BY A CLOCK
GENERATOR TO FORM READY. THIS SIGNAL IS ACTIVE HIGH
1
RESET: RESET CAUSES THE PROCESSOR TO IMMEDIATELY
TERMINATE ITS PRESENT ACTIVITY. THE SIGNAL MUST BE
ACTIVE HIGH FOR AT LEAST FOUR CLOCK CYCLES. ,RESET
IS INTERNALLY SYNCHRONIZED
©
1
CLOCK: THE CLOCK PROVIDES THE BASIC TIMING FOR THE
PROCESSOR AND BUS CONTROLLER. IT IS ASYMMETRIC WITH
A 33% DUTY CYCLE TO PROVIDE OPTIMIZED INTERNAL TIMING
POWER: Ve IS THE 5 V POWER SUPPLY PIN
GROUND: GND ARE THE GROUND PINS
Ti-e2se.L
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2221021
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5-42
12/14/83
PART NUMBER
REV
2223037-0001
W
ITEM. 0001 0002 0003
QUANTITY, 00001 .000 0000t.000 000901.000
0004 0005
00001.000 00001.000
0006 0007
00001.000 00000.500
0010
00004.000
0011
00004.000
0012
00003.000
0018 0020 0025
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00092.000
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0040 0041
00001.000 00000.167
List of Materials
DESCRIPTION ccoccssoovscsococecnes
POWER SUPPY ASSY-115V
ESTIC
COMPONENT,. DESC G ccR tccI ssovP ccrT osssI sscO csssN oncns UM
2223091-0001 2223025-0001 2223026-0001 2211949-0001 2221478-0005 2221479-0001 0418082-0001
PNWER SUPPLY, PEGASUS SEE TI- NRAWING
EA
CHASSIS ,POWER SUPPLY 1678-3025-903
EA
COVER,POWER SUPPLY 1678-3026-044
EA
SWITCH,ROCKER,DPST, 104,250V
SEE TI- DRAWING
RECEPVACLE+AC PDWER,UL/CSA/VDE APPROVED
SEE TI- DRAWING
AUX RECEPTACLE,POWER,SINE FLANGF MOUNTIN
SEE TUI- DRAWING
GROMMET, PLASTIC, FNGING
0972831-0004 0972684-0018
RIVET,1/8X.275, TUBULAR,STEFL,BLIND 019738-1821-0410 SCREW 8-32 X 3/8 THD FRM,SLOT HX WSR HD
01726A4~0011
SCREW, THREAD FORMING,6-32 X ,.375
1658-
=000
2232997-0001
WIRE, GROUND, LUGGED, GRN/YEL
SEE TI- DRAWING
2233003-0001
CABLE, POWER SUPPLY, TIPC
SEE T1- DRAWING
2223000-0001
PIWER SUPPLY, 115V
1254-1000-000
*MAY BE USED AS AN
1254-1000-000
*ALTFRNATE TO ITEM 1
1254-1000-000
2207869-0001
LABEL,WARMING HIGH VOLTAGF
A
1234-1869-000
0411115-0084
NUT,PLAIN 8-32 UNC-28 HEX CRES
EA
QPL
- M$35649-284
0411100-0072
LOCKWASHER #B, [NTERNAL TONTH CRES
EA
QrL
= M535333-72
2220354-0001
CARLE CLAMP 3M 348-4-1000
EA
0996810-0007
CAPACTTNR, 3900PF 400V DRALNR-SDPJ1 B40OVN
20%
CER,DIN
TYPE
A
2221327-0001
CORF,MAGNETIC,FERRITF
1293~
=000
EA
0972632-0001
STRAP,TIE DOWN,CABLE-NON-STD,0-1-1/4 D,
A
02421302499997--00. 000027
SQEPWIEILNRSE,UTLIA-TGI-ROAOD1NUR3N4AD9WS,ILNEGELVUIGNGGE,D,
GRN/YFL TEFLON #20
NATURAL
EA FT
5-43
12714783
PART NUMBER
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2223037-0002
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List of Materials
DESCRYPTION<ccosecsscsasosccncasesaconns POWER SUPPLY ASSY, INTERNATIONAL
COMPONENT.s DESCRIPTION:esessscsvssscccncscscccscescs UM
2223091-0001 2223025-0001 2223026-0001 2220637-0001 2221478-0005 2221479-0001 0418082-0001
POWER SUPPLY, PEGASUS
EA
SEE TI- OrAWING
CHASSIS,POWER SUPPLY
A
1678-3025-903
COVER,POWER SUPPLY
A
1678-3026-044
ROCKER SWITCH FOR EURNPFAN ASSEMBLIES
EA
SEE TI- DRAWING
PECEPTACLAEC POWER,UL/CSA/VDE APPROVED
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SEE TI- DRAWING
GROMMET, PLASTIC, EDGING
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0972831-0004 0972684-0018
RIVET91/8X.275, TUBULAR,STEEL +BLIND
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019738-1821-0410
SCREW 8-32 X 3/8 THD FRM,SLOT HX WSR HD
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0972684-0011
SCREW, THREAD FORMING,6-32 X .375
FA
1658~
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2232997-0001
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SEE T1- DRAWING
2233003-0002
CABLE, POWER SUPPLY, TIPC
EA
SEE TI- DRAWING
2223000-0002
PONER SUPPLY-RPO
EA
1254-2000-000
*MAY RE USED AS AN
1254-2000-000
*ALTERNATE TO ITEM 1
1254-2000-000
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2207869-0001
LABEL WARNING HIGH VNLTAGE
EA
1234-1869-000
0411115-0084
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EA
QPL
- MS535649-284
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0411100-0072
LNCKWASHER #8, INTERNAL TOOTH CRES
EA
QPL
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2220354-0001
CARLE CLAMP
EA
IM 348-4-1000
0996810-0007
CAPACITNR,3909PF 400V 20% CFR,DIN TYPE
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DRALOR-50P J18400VN
2221321-0001
CORE,MAGNFTIC, FFRRITE
EA
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STRAP,TIF DOWN,CABLE-MNON-STN,0-1-1/4 0.
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2232997-0002
WIRF, GROUND, LUGGEDs GRN/YEL
EA
SEE TI- DRAWING
0410499-0007
INSULATINN SLEEVING, TEFLON #20 NATURAL
FT
QrL
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12/14/83
PART NUMBER
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2223037-0003
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List of Materials
DESC e eR sccI cvseP sovT ecccI cacO ccccN cncas IMACTIVE PER ECN 501607
COMPONFNT. o 2223091-0001 2223025-0001 2223026~0001 2211535-0001 0996260-0001 2229485-0001 041R082-0001
PESCRIPTIONccecccassocessossccsssasnasss
POWER SUPPLY, PEGASUS
SEF TT1- DRAWING
CHASSIS,POWFR SUPPLY
1678-2025-903
COVFR, POMER SUPPLY
1678-3026-044
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0972831-0004 0972988-0041
RIVET,1/ TUB8ULX AR .yS2 TEE7L 5 , B, LIND 0197398-1821-0410 SCREW 8-32 X .250 PAN HEAD CRES
0972684-0011 0411101-0059 0416622-0024 2232997-000) 2232995-0002 2232996-0002 2223000-0003
2207R69-0001 2223088-0001 0411115-0064 2223048-0001 0411101-0058 2220354-0001
SCRENW, THREAD FORMING,6-32 X ,37%
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PNWER SUPPLY-VDE
1254-3000-000
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1234-1869-000
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CABLE CLAMP
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12/714/83
PART NUMBER 2223037-8001
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2223037-0001
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UM EA
12/14/83
PART NUMBER 2223037-8002
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DESCRIPTION POWER SUPPLY
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2223037-0002
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12/14/83
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List of Materials
DMAETSINCRIEPNTCILODNS.UcREo,sSvUcBeAvSeSsYscscossvassncnansne
COMPONENT.. DESCRIPTION:cessvccsscecsccscssscsscanes uM
2223024-0001
CHASSIS, TERMINAL
EA
1678-3024-054
2223037-0001
POWER SUPPY ASSY-115V DOMESTIC
EA
1669-1037-000
2220632-0003
FAN, 115 VAC, 71 CFM, 13 W, TUBEAXTAL
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0000-9009-000
2223003-0001
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EA
1254-3003-069
2211907-0005
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EA
SEE TI- DRAWING
2220484-0001
SUPPORT ,PC BOARD, SELF-MOUNT
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EA
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0972969-0013
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0972684-0018
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2211896-0012
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FA
2210006-0003
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2220956-0001
SPACFR NUT
A
2232335-0001
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1678-2335-037
12/14/83
PART NUMBEPR
REV
2223038~0002
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List of Materials
DESCRIPTINNGcsvoevrsonsscvscocessscsssses MAIN FNCLNSURE SUNASSY-RPN
COMPONENTee DESCRIPTINMeccrccocscccccccncsssnnsascss UM
2223024-0001
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1669-2037-000
223232R-0001
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2223003-0001
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EA
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22204R4-0001
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FA
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0972684-0018
SCREW 8-32 X 3/8 THD FRM,SLOT HX WSR HD
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2211R96-0012
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2210006-0003
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0972373-0001
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2223198-0001
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2211909-0003
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2220956-0001
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2232335-0001
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1678-2335-037
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DSYESSTCER'IPTAISOSNY-cSvTeAeNcNsAeRaDvacnansssscccsscccces
COMPONENT.o DESCRIPTINNecocesocsscscoscsccaccssnnacs UM
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2223029-0001
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22213033-0001
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1212-3203-000
2223279-0001
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5-57
12/14/83
List of Materials
PART NUMBER
REV
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AH
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List of Materials
DSYESSTCERMIPTAISOSNY-«BsAcSeIsCeecacscscassasecnanonnes
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List of Materials
DESCRIPTION cccosescscvsvssecscccsssccccs SYSTEMS ASSY STANDARD-320K COMPONFNT.. DESCRIPTION..cevcccccscsscrcvscccacaanes UM
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DFSCRIPTION .cccccccsencsecccsassccascsns SYSTFM ASSY-TNT*L-320K
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PAPT NUMBER
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DESCRIPTION eoccasoscenscssscssencannsnas GRAPHICS,CRT CONTROLLER~-AUTN INSERT
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DESCRIPTIONecevecacaccsoenscsoenasccnsass GRAPHICS,CRT CONTROLLER 3 PLANE-AUTO INS
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List of Materials
DESCRIPTIONcccacssscccosccsvscesosscscne COMMUNTICATION CARD ASSEFMBLY
COMPOMENT.. DESCRIPTION:cccocccscccccssssocsccaccass UM
2223096-0001
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2220519-0001
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2210288-0006
HEADER, 6-PINS .600 L,SNG ROW,STRT-POST
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2220488-0003
CONNECTOR, RECEPTACLEPCB,25-PINS
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PRACENURE, STTE & DATE CNDF SERTALIZATION A
2223033-0002
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1678-3223-023
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JUMPER PLUG,COMNNECTNR BLACK
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PART NUMBER
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12/14/83
PART NUMBER
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2223094-5001
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5-86
12714/ 83
List of Materials
PART NUMBER
REV
2223 094-5001
R
DESCRIPTION:vcossvosvcccacstvannsacnnsas AUTO- [NSEFRTED PARYS LIST FOR -0001
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12714/ 93
PART NUNBER
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2223094-8001
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List of Materials
DESCRIPTION.cceseonccreoesscosesssscanscs COMMUNICATION CARD ASSY - SPARFES
CONPONFNTes DFSCRIPTIONceesevccccescssancootscnnscass
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Parts other than those
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TI retains
Fig. 1 Item
Description
TI Part #
1
Connector, Cable,
2220042-0015
Female
2
Connector, Ribbon
2211341-0001
Cable, 34 Posttion
3
Cable, Mulci-Cond., 0996491-0003
34 Conductor
4
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(Fig 2)
0983903-0002
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2211340-0001
Vendor Name 3M 3M M 3M M
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2223099-0001
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List of Materials
DESCRIPTION:ccvessceavscaveccsscacmsscss OPTION KIT - RAM CHIPS
COMPONENT.. OESCR.I - eP eesT ccI cosO cnN cnss
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2211118-0004
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List of Materials
DESCRIPTION.cseacscoas VIDED CRT CONTROLLER
COMPONENT.. DESCRIPTION.ceccnceacnsscosoescacccncsss UM
2223102-0001
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List of Materials
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List of Materials
NESCRIPTION. ccecosesscscsvscncsnsccanccnse VINDED CRT COMTROLLER, AUTO-INSERT
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List of Materials
DESCRIPTION.eoeceas VIDEO CRT CONTROLLER,
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List of Materials
DESCRIPTIONceeceesososesonscescovascsses VIDEO CRT CONTRNLLER, AUTO-TNSERT COMPONFNT, » DESCRIPTION ceccccsscsccosooscsscancsase UM
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PART NUMBER
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List of Materials
DESCRIPTION ccocscecsccosecssscsscosscns TEST PLUG, EIA, MODEL 767
COMPONENT,. DESCRIPTIOMeccesonccccacancasccssccancss
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FIN0I3V0LIvZ3IHLHON3O9PHL1SNAT31S3MN3AA1W1DO2S>5 _IN._
1
.
SZ$°°00FF == SSTTiVYSWWIIIODDN3IVQdHII330DDVLV1dd VHOIIMNNLOID [Z] SUILINITUN N1 3wy SNOISNAwG Ty [T)
`GNIOWMS ISNYIIO SSTN "SHON
v
12/14/83
PART NUMBER
REV
2230528-8001
L
ITEM.
QUANTITY.
0001
00001.000
List of Materials
DESCRIPTION. .
secsccsscenccsscsnssss
KEYBNARD, TILTING,LOW PROFILE - SPARES
COMPONENT.. DESCRIPTIONcsecsscveccsnscsccncnssssssee
2230528-0001
KYBD, TILTING,LOW PROFILE,DNMESTIC STN 1665-1528-002
UM EA
5-200
12/14/83
PART NUMBER
REV
2230528-0008
L
ITEN.
QUANTITY.
0001
00001 .000
0002
00001.000
0003
00001.000
0004
00002.000
0005
00001.000
0006
00001.000
0007
00001.000
0008
00001.,000
0009
00001.000
0010
00001.000
ool1
00001 .000
0012
00002.900
0013
00002.000
0014
00002.0C0
0015
00001.000
0017
00002,009
oo1s
00006.000
0019
00003.000
0020
00002.000
0022
00002.000
0023
n0006.000
0025
00001.000
0026
00001.000
0027
00004.000
0028
00000.048
0029
00001.000
00294
00298
0029¢C
00290
List of Materials
NKYERSDC,RITPITLITOINN.G,cLoOMcvePvReOsFcIsLsEo,oSoWnIsToZoEcRnLaAcNsDncnss
COMPONEMT.. DESCRIPTINMNcccescocsvsae
ecsnscsscss UM
2230529-0001
BAS E,KEYROARD
FA
1255-7500-015
2230536-0001
HNUSTNG ¢ SHAFT 4R IGHT
EA
1255-7504-006
2230534-0001
HOUSTNG »SHAFT (LFFT
fA
1255-7503-006
2230532-0001
SHAFT,CLUTCH SPRING
A
1255-7502-007
2210546-0001
SPRING, CLUTCH
FA
2230546-0002
SPRING, CLUTCH
A
2230547-0001
SPRING, RETURN
£A
2230547-0002
SPRING, RETURN
FA
2230540-0001
2230527-0008
2239530-0001
2230538-0001
2230554-0001 2230552-0001 2230549-0001 09726 79-0029 0972679-0012 0972679-0015 2230555-0007 2230556-0001 0972679-0013 0936643-0001 0936664-0002 04111010058 0972436-0011
227%609-0004
FOOT,TILT ADJUSTMENT 1255-7506~008 KEYBOARD,LOW PROFILE,SWITZERLAND SEE TU- DRAWING COVER,KEYBNARND, PERSONAL COMPUTER 1255-7501-015 BUTTOM, REL,TILT FOOT,PERSONAL COMPUTER
B~1R--CCm2aAALm5mCBImL5mKPFm-mE,e7mTCe5aLAa0eUS,=e5TSS=m-CYP00H0R,000IK007NEGYB,OBAURTDTON
SCREW
.
*
A
EA
EA
EA
z EA £A FA EA
SCREW # 6-19 X 3/8 SLOTTED HEX
£a
SCREW #6-19 X 3/4 THD SLOTTED HEX
A
RING,RETAINING
A
PAD,NONSKID,P/T
FA
SCREW # 6-19 X 1/2 SLOTTED HEX
EA
LSSQPOLEEPCIFELWONCSCKULWTPTL1AAIRA--SMTO-HSIFEHNIDDRMNELRRSLEAA3LWW5#SII36LKNN3EETGG5EYH-VBEE5OIRX8ANMTRGOED,FRPONVRACBMLOX
STYRENE
TONTH CRES 8 X.133
£A A
EA FY
003A90-HT-105C-8
10, SERTAL NO LABEL, BLANK, COLLEGE STA
FA
* D= {OW PROFILE KEYRNARD,
* SWISS, N= 2230528-0008,
* A= 0,35, W= 4.2, V= 12,
* F= 0y P= O
6-199
12714783
PART NUMBER
REV
2230528~0007
L
ITEN,
QUANTITY,
0001
00001.000
0002
00001.000
0003
00001.900
00C4
00002.000
0005
00001,000
0006
00001.000
0007
00001.000
0008
00001.000
0009 0010
00001.000 00001.000
0011
00001.000
0012
00002.000
0013
00002.000
0014
00002.000
0015
0000t.000
0017
00002.000
0018
00006.000
0019 0020
00003.900 00002,000
0022
90002.000
0023
00006,000
0023 0026
00001.000 00001.000
0027 0028
00004.000 00000.048
0029
00001.000
00294
00298
0029¢C
00290
List of Materials
DESCRIPTION:ccoccoocacssoavocsassacscnnsne KYBDo TILTING,LOW PROF JLE, DENMARK/NORWAY
COMPONEMT.. DESCRIPTIMNccccceccacccoscacsscaccscanss
2230529-0001 2230536-0001 2230534-0001 2230532-0001 2230546-0001
BASE,KEYBOARD 1255-7500-015 HOUS ING y SHAFT,RIGHT 1255-7504-006 HOUSTING o SHAFT,LEFT 1255-7501-006 SHAFT,CLUTCH SPRING 1255-7502-007 SPRING, CLUTCH
2230546-0002
SPRING, CLUTCH
2230547-0001
SPRING, RETURN
2230547-0002
SPRING, RETURN
2230540-0001 2230527-0007 2230530-0001 2230538-0001 2230554-0001 2230552-0001 2230549-0001
FOOT,TILYT ADJUSTMENT
1255-7506-008
KEYBOARD,LOW PRNFILEDENM/HAORRWKAY
SFE TI- DRAWING
COVER yKEYB»OPA ERR SOD NAL COMPUTFR
1255-7501-015
BUTTON,REL,,TILT FOOT,PERSONAL COMPUTER
1255-7505-007
BRACKET,SPRING,BUTTON
e 00 0|
CLIP, CLUTCH
N 000
CABLE ASSY,KEYBOARD
4
0972679-0029
SCREW
g
0972679-0012
SCREW # 6~19 X 3/B SLOTTED HEX
0972679-0015
SCREW #6-19 X 3/4 THD SLOTTED HEX
2230555-0007
RING,RETAINING
2230556-0001
PAD, NONSKID, P/ T
0972679-0013
SCREFW # 6-19 X 1/2 SLOTTED HEX
0936643-0001 0936664-0002 0411101-0058 0972436-0011 22756 09-0004
PC CLAMSHELL THERMOFORM STYRENE
SEE TI- DRAWING
LOW PROFILE KEYBOARD ROX
SEE TI- DRAWING
LOCKWASHER #6 EXTERNAL TOOTH CRES
QPL
= M$25335-58
INSULATIOM SLEEVING,PVC R X.133
00N3890-HT-105C-8
10, SERIAL NO LABEL, BLANK, COLLEGE STA
*D= LOW PROFILE KEYBOARD,
* DEN/NORN,= 2230528-0007,
* A= 0,35y W= 4,2,
* F= 0, P= 0
V= 12,
UM EA EA A EA A EA EA EA FA EA EA A A £A EA EA A EA A EA EA A FA £A FT FA
6-198
12714783
PART NUMBER
REV
2230 528-0906
L
ITEM,
QUANTITY,
0001 0002
00001.000 00001.000
0003
00001.000
0004
00002.000
0005
00001.000
0006
00001.000
0007
00001.000
0008
00001.,000
0009 0010
00001.000 00001,000
ool
00001.000
0012
00002,000
0013
00002.000
0014
00002,000
0015
00001.000
0017
00002.000
oolr8
00006.000
0019
00003.000
0020
00002.000
0022
00002.000
0023
00006.000
0025
00001,000
0026
00001.000
0027
00004.000
0028
00000.048
0029
00001.000
00294
00290
0029C
00290
List of Materials
DESCRIPTIONccecevcscnvnncocse
ccesoe
KYBDs TILTING,LOW PROFILE,
DEN/F INLAND
COMPONENT.. DESCRIPTINN.cesescsvoscocssocsccacssoscce
2230529-0001 2230536-0001 2230%534-0001 2230532-0001 2230546-0001
BASE,KEYBOARD 1255-7500-015 HOUS TNGy SHAF T, RIGHT 1255-7504-006 HOUSING » SHAF T, LEFT 1255-7503-006 SHAFT,CLUTCH SPRING 1255-7502-007 SPRING, CLUTCH
2230546-0002
SPRING, CLUTCH
2230547-0001
SPRING, RETURN
2230547-0002
SPRINGs RETURN
2230540-0001 2230527-0006 2230%30-0001 22230538-0001 2230554-0001 2230552-0001 2230549~0001
FOOT,TILT ADJUSTMENT 1255-7506-008 KFYROARD,LOW PROFILE,SWEDFN/FINLAND SEE T1- DRAWING COVER KEYBOARDy PERSONAL COMPUTER 1255-7301-01% BUTTON,REL,TILT FOOT,PERSONAL COMPUTFR 1255-7505-007 B--R--AnCmKmEwTme¢=S=P0R0I0NGy BUTTON
CLIP,CLUTCH
---------- 000
CABLE ASSY,KEYBNARD
A
0972679-0029
SCREW
0972679-0012
SCREW # 6-19 X 3/8 SLOTTED HEX
0972679-0015%
SCREW #6-19 X 3/4 THD SLNTTED HEX
2230555-0007
RING,RETAINING
2230556~0001
PADGNONSKIN.P/T
0972679-0013
SCREW # 6-19 X 1/2 SLOTTED HEX
0936643-0001 0936664~-0002 0411101-0058 0972436-0011 2275609-0004
PC CLAMSHELL THERMOFORM STYRENE
SEE TI- DRAWING
LOW PROFILE KEYBNARD BOX
SEE TI- DRAWING
LOCKWASHER #6 EXTERNAL TOOTH CRES
QPL
- M535335-34
INSULATTON SLEEVING,PVC 8 X.133
003490-HT-105C-9
1Dy SERTAL NO LABEL, BLANK, COLLFRE STA
* D= LOW PROFILE KEYBOARD,
* SWE/FINy N= 2230528-0006,
* As 0.35 H= 4.2, V= 12,
® F=0, P= 0
UM EA EA FA EA A EA EA FA A EA EA EA A A FA EA EA A A A A EA A A FT FA
5-197
12/14/83
PART NUMBER
REV
2230528-0005
L
ITEM,
QUANTITY.
0001
00001.000
0002
00001.000
0003
90001.000
0004
00002.000
0005
00001.000
0006
00001.000
0007
00001.000
0008
00001.000
0009
00001.000
0010
00001.000
00l
00001.000
0012
00002.000
0013
00002.000
0014
00002.000
0015
00001.000
0017
00002.000
0018
00006.000
0019
00003.000
0020
00002.900
0022
00002.0C0
0023
00006.000
0025
00001.000
0026
00001.000
Q027
00004.000
o028
00000. 048
0029
00001.,000
00294
00298
0029¢C
00290
List of Materials
DESCRIPTIONccaceccosasascsvosonccoscnsses KYBD,TILTING,LNW PROFILE,SPANISH
COMPONENT.e DESCRIPTTONccecacscoacssassscconssssnces UM
2230529-0001
BASE.KFYBOARD
FA
1255-7500-015%
2230536-0001
HOUSTMG ¢ SHAFT, R IGHT
A
1255-7504-006
:
2230534-0001
HOUSING » SHAFT,LEFT
EA
1255-7503-006
2230532-0001
SHAFT,CLUTCH SPRING
EA
1255-7502-007
2230546-0001
SPRING, CLUTCH
A
2230546-0002
SPR ING, CLUTCH
EA
2230547-0001
SPRIMNG, RETURN
EA
2230547-0002
SPRING, RETURN
A
2230540-0001
FOOT,TILT ADJUSTMENT
EA
1255-7506-008
2230527-0005
KEYBOARD,LOW PROFILE,SPANISH
EA
SEE TI- DRAWING
2230530-0001
COVER,KEYBOARD, PERSONAL COMPUTER
EA
1255-7501-015
2230538-0001
BUTTON,PEL,TILT FOOT,PERSONAL COMPUTER
EA
1255-7505-007
2230554-0001
BRACKET 4 SPRING,BUTTON
A
g
--000
2230552-0001
CLIP,CLUTCH
FA
-------------------- 000
2230549-0001
CARLE ASSY,KEYROARD
s
EA
0972679-0029
SCREW
EA
0972679-0012
SCREW # 6-19 X 3/8 SLOTTED HEX
EA
0972679-0015
SCREW #6-19 X 3/4 THD SLOTTED HEX.
EA
2230555-0007
RING,PETAINING
EA
2230556-0001
PAN,NONSKID.P/T
FA
0972679-0013
SCREW # 6-19 X 1/2 SLOTTED HEX
FA
0936643-0001
PC CLAMSHELL THERMOFORM STYRENF
EA
SEE TI- DRAWING
0936664-0002
LOW PROFILE KEYROARD BOX
EA
SEE TI- DRAWING
0411101-0058
LOCKWASHER #6 EXTERNAL TDOTH CRFS
EA
QrPL
- M$35335-58
0972436-0011
TNSULATION SLEFVING,PVC B X.133
FT
003890-HT-105C-8
2275609-0004
10, SFRIAL MO LABEL, BLANK, CNLLEGE STA
FA
* D= LOW PROFILE KEYBOARD,
* SPN, N= 2230528-0005,
* A= 0,35, M= 4.2, V= 12,
*F= 0, P= 0
5-196
12/14/83
PART NUMBER
REV
2230528-0004
L
ITEM,
0001 0002 0003 0004 0005 0006 0007 0008 0009 0010 onit 0012 0013 0014 0015 0017 0018 0019 0020 0022 0023 0025 0026 0027 0028 0029 00294 0029A 0029¢C 00290
QUANTITY.
00001.000 00001.000 00001.000 00002.000 00001.000 00001.000 00001.000 00001.000 00001.000 00001,000 00001.000 00002,000 00002.000 00002.000 00001.000 00002,000 00006.000 00003,000 00002,000 00002.000 00006.000 00001.000 00001.000 00004.000 00000.048 00001,000
List of Materials
DESCRIPTIONccocesococcsscassnsvscsncasnns KYBD,TILTING,LOW PROFILE,GERMANY/AUSTRIA
COMPONFNT..
2230529-0001 2230536-0001 2230534-0001 2230532-0001 2230566-0001 2230546-0002 2230547-0001 2230547-0002 2230540-0001 2230527-0004 2230530-0001 2230538-0001 2230554-0001 2230552-0001 2230549-0001 0972679-0029 0972679-0012 0972679-0015 2230555-0007 2230556-0001 0972679-0013 0936643-0001 0936664-0002 0411101-0058 0972436-0011 2275609-0006
ODESCRIPTION:ccescoccccevsescccsccanscsses UM
HH11O1O1SSB222UU2PHA555SS5RAS5555IIIFEN----NNT,G7777GG,,K5555,,CE0000LY4302UBCSS----TOLHH000C0AAUA001H0FRTF665T7DCTH,S4LRPERFIIGTNHGT .
£A EA A EA EA
SPRING, CLUTCH
A
SPRING, RETURN
A
SPRING, RETURN
£A
C--CS1--11AECFKROB=222mEBOLEURVm555mLOIYTAEm555ETPBmTCm-R--T,,OOKmm7,I77TCAN-Em555KImLRA,T=0L00EUDSRn,Te561YT,ESDSmu---CBLLYRP00H00aOO,,0ARA0001HAT0mKWID07850IREINJLDNYGUPTG,B,SRNPTBOAEMUFFRRETTODSNTOLTOOTENN,,APGLEERRSMCOAONNMAYPL/UATUECRSOTMRPIUATER
A EA A FA FA A EA
SCREW
s
EA
SCREW # 6-19 X 3/8 SLOTTED HEX
EA
SCREW #6-19 X 3/4 THD SLOTTFD HEX
EA
RING,RETAINING
FA
PAN,NOMSKTD,P/T
A
SCREW # 6-19 X 1/2 SLOTTED HEX
FA
LL0SSQP1NCEDEPO0IO,EELNWC3SK8CSUW9ELTPTLA0RIAIRAS--I-MOT-HAHSFIELOHTIRDDMNEL-RR§EL1AA3NL0WWO5#S5II36LCKNN3LEE-GGT5AYE8H-BBVEE5EOIX8RLANT,MRGEOD,RFPNBRVALBMCLAONXK,8TSNTOVXTR.CHE1ON3LE3LCERGEES
STA
EA EA EA FT FA
* D= LOW PROFILE KEYBOARD,
* GER/AUS, N= 2230528-0004,
* A= 0.35, W= 4.2, V= 12,
* f= 0, P= 0
5-195
12/14/83
PART NUMBER
REV.
2230528-0003
L
ITEM.
QUANTITY,
0001
0C001.000
0002
00001.000
0003
00001.000
0004
00002.000
0005
00001.000
D006
00001.000
0007
00001.000
0008
90001.000
0009
00001.000
ooi0
00001.000
o011
00001.000
0012
00002,000
0013
00002.000
0014
00002.000
0015
0000%t.C00
0017
n0002,000
o0o18
00006.000
0019 0020
00003.000 00002.000
0022
00002,000
0023
10006.000
0025
00001.000
0026
00001,000
0027
00004.000
0028
00000.048
0029
00001.000
00294
00298
0029C
00290
List of Materials
NESCRIPTIONceecscoosns KYBN, TILTING,LOW PROFI
COMPONENT.. DESCRIPTIONceoccosceccseacsssevecsnccccnes
2230529-0001 2230536~-0001 2230534-0001 2230532-0001 2230546-0001
BASE,KEYBNARD 1255-7500-015 HOUS ING y SHA4FRITGHT 1255-7504-006 HOUS ING o SHAFTLE,FT 1255-7503-006 SHAFT,CL UTCH SPRING 1255-7502-007 SPRING, CLUTCH
2230546~0002
SPRING, CLUTCH
22305471-0001
SPRING, RETURN
2230547-0002
SPRING, RETURN
2230540~0001 2230527-0003 2230530-0001 2230538-0001 2230554-0001 2230552-0001 2230%549~0001
FOOT,TILT ADJUSTMENT 1255-7506-008 KEYBOARLDOW PROFTILE,FRANCF SEE TI- DRAWING COVER,KEYBDARD,PERSONAL COMPUTER 1255-7501~-015 BUTTRO EL N,T, ILT FOOT,PERSONAL COMPUTER 1255-7505-007 BRACKET, SPRING, BUTTON --==--e===-==000 CLIP,CLUTCH
e 000 CABLE ASSY,KEYBOARD
>
0972679-0029
SCREW
«
0972679-0012
SCREW # 6-19 X 3/8 SLOTYED HEX
0972679-0015 2230555-0007
SCREW #6-19 X 3/4 THD SLOTTED HEX RING,RETAINING
2230556-0001
PAD,NONSKID,P/T
0972679-0013
SCREW # 6-19 X 1/2 SLDOTTED HEX
0936643-0001 0936664-0002 0411101-0058 0972436-0011 2275609-0004
PC CLAMSHELL THERMOF(ORM STYRENF
SEE TI- NRAWIMG
LOW PROFILE KEYBOARD BOX
SEE TT- DRAWING
LOCKWASHER #6 EXTERNAL TNOTH CRFS
QPL
- M535335-58
INSULATION SLEEVING,PVC 8 X.133
003890-HT-105C~8
ID,SFRIAL NO LABEL, BLANK, COLLFGE STA
* D= LOW PROFILE KEYBOARD,
* FRENCH, N= 2230528-0003,
* A= 0.35, W= 4,2, V= 12,
* F= 0, P=0
UM Fa EA FA EA EA EA EA EA EA EA EA A FA EA EA EA A EA EA FA EA Ea EA EA FT FA
5-194
12714783
PART NUMBER
REV
2230528-0002
t
ITEM,
QUANTITY,
0001
00001.000
0002
00001.000
0003
00001.000
0004
00002,000
0005
00001.000
0006
00001.000
0007
00001 .000
0008
00001.000
ooc9
00001,000
0010
00001.000
0011
00001.000
0012
00002.000
0013
00002.000
0014
00002.000
0015
00001,000
0017
0C002.000
0018
00006.000
0019
00003.000
0020
00002.000
0022
00002.000
0023
00006.000
0025
00001.000
0026
00001.000
0027
00004.000
o028
00000.048
0029
00001.000
G029A
00298
0029¢C
00290
List of Materials
DESCRIPTION cccacvoscsavscevssosccasscss KYRD, TILTING,LOW PROFILE,VU.K.
COMPONENT,» DESCRIPTION.coscscccosovcvcconccsccsssas
2230529-0001 22305360001 2230534-0001 2230532-0001 2230546-0001
BASE,KFYBOARD 1255-7500-015 HOU»SSHI AF M T, RG IGHT 1255-7504-006 HOUSTNG SHAFT 4 LEFT 1255-7503-006 SHAFT,CLUYCH SPRING 1255-7502-007 SPRING, CLUTCH
2230546-0002
SPRINGs CLUTCH
2230547-0001
SPRING, RETURN
223054 T-0002
SPRINGs RETURN
2230540-0001 2230527-0002 2230530-0001 2230538-0001 2230554-0001
FOOT,TILT ADJUSTMENT 1255~7506-008 KEYBOARD+LOW PROFILE,UNITED KINGDOM SEE TI- DRAWING COVER ,XEYROARD, PERSONAL COMPUTER 1255-7501-015 BUTTONREL,TILT FOOT, PERSONAL COMPUTER 1255-7505-007 BRACKETY ySPRING,BUTTON
2230552~0001
2230549-0001
CABLF ASSY,KEYBOARD
&
0972679-0029
SCREW
0972679-0012
SCREW # 6-19 X 3/8 SLOTTED HEX
0972679-0015
SCREW #6-19 X 3/4 THD SLOTTED HEX
2230555-0007
RINGLRETAINING
2230556-0001
PAD ¢ NONSKIDP/, T
0972679-0013
SCREW # 619 X 1/2 SLOTTED HEX
0936643-0001 0936664-0002 0411101-0058 0972436-0011 2275609-0004
PC CLAMSHELL THERMOFORM STYRENE
SEE TI- DRAWING
LOW PROFILE KEYBOARD BOX
SEE TI- NRAWING
LOCKWASHER #6 EXTERNAL TOOTH CRES
QPL
- M$35335-58
INSULATION SLEEVING, PVC 8 X.133
003890-HT-105C.-8
10, SERTAL NO LABEL, BLANK, COLLEGE STA
* D= LOW PROFILE KEYBOARD,
* UK, N= 2230528-0002,
* A= 0.35, W= 4.2, V= 12,
*F=0P,= 0
UM EA EA EA EA EA A EA EA EA EA EA EA EA FA EA EA A EA EA EA EA EA EA EA FT EA
6-193
12/14/83
PART NUMBER
REV
2230528-0001
t
ITEM.
QUANTITY,
0001 0002
00001 .000 00001.000
0003
00001.,000
0004
00002.000
0005
00001.000
0036
00001.000
0007
00001.000
0008
00001.000
0009
00001.000
0010
00001.000
0011
00001.000
00L2
00002,000
0013
00002.000
0014
00002.,000
0015
00001.000
0017
00002.000
0018
00006 .090
0019 0020
00003.000 00002.000
0022
00002,.000
0023
00006.000
0025
00001.000
0026
00001.000
2027
00004.000
0028
00000, 048
0029
00001.000
00294
00298
0029¢C
Q030
00001.000
0031
00001.000
List of Materials
DESCRIPTION.ccvacsvosccoccascnnn KYBD, TILTING,LOW PROFILE, DOMESTIC
COMPDOMENT.e DESCRIPTINNceeecccacscncscnsscscsncsscss
2230529-0001% 2230536-0001 2230534-0001 2230532-0001 2230546~0001
BASE.KEYBOARD 1255-7500-015 HOUS ING y SHAFT o RIGHT 1255-7504-006 HOUS ING, SHAFT, LEFT 1255-7503-006 SHAFT,CLUTCH SPRING 1255-7502-007 SPRING, CLUTCH
2230546~0002
SPRING, CLUTCH
2230547-0001
SPRING, RETURN
2230547~0002
SPRING, RETURN
2230540-0001 2230527-0001
FOOT,TILT ADJUSTMENT 1255-7506-008 KEYROA4RLDOW PROFILE,NOMESTIC STD
2230530-0001
2230538-0001
2230554-0001 2230552-0001 2230549-0001 0972679-0029 0972679-0012 0972679-0015 22305550007 2230556-0001 0972679-0013 0936643-0001 0936664=-0002 0411101-0058 0972436-0011
2275609-000%
COVERKEYBOARD, PERSONAL COMPUTER
1255-7501-015
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DESCRIPTION veeseessccsvsvccossossssssasse TELEPHONE ELECTRONICS-AUTO INSFRTED
COMPONENT..
2210600-0001 2210604-0001 2210606-0001 2210631-0001 2210636-0001 2210644-0001 2210649-0001 2210752-0001 2210665-0001 2210718-0001 2210651-0001 2210663-0001
DESCRIPTIONccocecsovecsvesoccessscsccsns UM
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DTEELSECPRHIOPNTEIONE.LcEeCcToRvOvNeIvCcSc-sAsUnTsOrsnIcNsSsEsRsTsEnDscoce
COMPONENT.. DESCRIPTION.sescessoncccesvvssncaccssoes UM
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List of Materials
DESCRIPTIONccacsvssccacccncncscconcocncs TELEPHONE ELEC TRONICS-AUTO INSERTED
COMPOMENT.. OESCRIPTIONccccccecrcsssscsccccsacacaccs UM
C84C53+C58,C6T7,LT1,C72,C73
COR CA-C0225VU1022100A
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RRRRRRRRRRRRRRRRRRRRRRRRRRRRRR RRRRRRRRRRRRRRRRRRR1111EREOREOOOOEOOE2R1OE4EE3O5OOOOOOOOEE15OOSOO41OOO16363966EEESHSSHHHHS6SHHSHSHSS7HHHHHHHHSSHM4HH,HHH10,455SSS5518581S67R81,R888T,,,=47+,,R-4-y-R4RR"FFRFFFFRFFFFFF3RRFRS,6I3IR92IIII6IIIII&I3IS6SRXXTXXXXX969XXXXX69X281=-------------=---=--1=--~,,3, ,,,4R,R,R1RRRRR2RRRSRRRRR6RRRR52RRR3RR4RRR2R4112RR11R5673.=----=.===--872R ---=-1=-4.7-==---0.,010T926-2222220012222T22..3222229.~22222220~--0,T20047S-55S55-K55055055550K0S550555555KKK,5K00K6 0,K00o0R000RR0RR3O6IOOOO&OONO4OOOO04HHHEHH8HHHH2HHHH1,MMMMY,MMMMBMMMM,,R, yRR3RR4955S55BS5SS5552$SSR 30%T%2,,,,4R%TT¥XR%%XR6 RG3..R1.312.26S..2.....1..,05522522222222,2-0S555,5555555
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FILM
FILM FILM FILM FILM FILM FELM FILM FILM FILM FILM FILM FILM
A
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2232403-5001
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0039
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List of Materials
DESCRIPTIONesevovescssocavsacnascccosans TELEPHONE ELECTRONICS-AUTO INSERTED
COMPONENT.. 2221005-0001 0972686-0002
DESCRIPTIONcceccccssosscaccsscsscssveces UM
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List of Materials
DESCRIPTIONcevoccsocsancsscvossoncsscncs TELEPHONE ELECTROMICS-AUTO INSERTED
COMPONENT. o DESCRIPTION.cececccoccsvacccasrssccncane UM
*ITEM 206(P/N 2210631-1)1S
*AN ACCEPTABLE SUBSTITUTE
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EA
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5-175
12/14/83
PARY NUMBER
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00194 0020 00204 002t 00214 0022 00224 0023 00234 0024 00244 0025 00254 00258
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00003.000 C0001.000 00091.000 00002.000 00001.000 00001.000
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0026 00264 00268 0026C 0027 00274 00278 0027¢C 0028 00284 00288 0028¢ 0029 00294 0030 0030A
N0001.000 00002.000 00001,000 00001.000 00005.000
List of Materials
DESCRIPTION.cooesee TELEPHOME ELECTRONI
esescassoccsccsss UTO INSERTED
COMPONENT,,
2221100-0001 2220999-0001 2221098-0001 2221099-0001 2221247-0001 0996755-0001 L 0972900-7400
0972900-7406
DESCRIPTINMicovecsvoosceoscoscsccscssncsae UM
ICSUSUEE,32EE3M8,0,UUSTT321,I4--9,DUFND3CRR0NAANWWEIIPNNGG
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List of Materials
DESCRIPTION: cososcveencosnssscsncosnscose TELEPHONE ELECTRONICS
COMPONENT.. DNESCRIPTIOMcoesecoconcccccoscconccscnnce UM
2211348-0002
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INSULATION,SLEEVING #16 NATURAL
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INSULATION SLEEVING, TEFLON #10 NATURAL
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PART NUMBER
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2232404-0001 2221071-0001
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2210594-0002
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221107; 7-0001 0996437-0001
2221063-0001
DESCPIPTIONcessocovrcccccconcecocccances UM
ICuuVSU1SSSSSSIS[,Is44FsEEEPEEEECO2CC932EsEEE,EECEEH,P5oWH4T8BM=N~,TTTMTTTTTNA-,RSII1IIIIIKSM0PCI--------SPE0TOOLE2U,BCI0PDDDDDDDDD9HF-TR.RRRRRRRMNI0MA3AAAAAAA,UFF0WW0WWWWWWLPR0II0IIIIIITI,NN0NNNNNNIGRTGGGVGGGGGGPNEYLNCJIF.FFI,ERBS5TAGOVC-ELK,IMAD6NEAT2PRCI~5UA,ONTT.NW,O5i ,,R%10<L10O8L0PWITI-NNCN,TO4RISP,SOLEPNALWSSTTICC
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List of Materials
DESCRIPTIONcsecccoososcnnssssssssvaccans TELEPHONE ELEC TRONICS
COMPONENT,. DNESCRIPTIOM.ceeccccscsncccnnascossssasas UM
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List of Materials
DESCRIPTION.cesosoocsosacssavoscssocncscns SPEECH ELECTRONICS, AUTO INSERTED
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DESCPIPTION: coee. SPEECH ELFCTRANICS,
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List of Materials
DESCRIPTIONccscessscecssesssocosnssconcnca SPFECH ELECTRNNICS, AUTO INSERTED
COMPONENT. o 2232374-0001 0972900~ 7400
0972900-7404
DESCRIPT IONcscevoocevccocccasnscsacncess PWR, SPEECH 1254-0000-000 NFTHORK SNT4LSOON 1233-7564-000 usT,Us8 1233-7564-000 *ITEM 201(P/N 2210600-1)1S 1233-7564-000 *AN ACCFPTABLF SUBSTITUTE 1233-7564-000 NETWORK SN74LS04M
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DESCRIPTION ccssnvecoccascsccsocsvacssancse SPEECH ELECTRNNICS
COMPONENT.. DESCRIPTION .cceesccavcsse
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DESCRIPTION.ceeoccvccsnccscosccsasscnscs CABLE ASSY,MOTHFRBD TO EXTERNAL FLNPPY
COMPONENT.. DESCRIPTIOM.ceecosccsccssovsoccssccnsscs UM
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List of Materials
DESCRIPTIONceecosccsvcnsonscscsscacccsns CABLE ASSY,MOTHERBOARD-EXTERNAL FLOPPY
COMPNINEN.T. DESCRIPTINNceecccccasanas
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OFSCRIPTIONcoeosaosssccsceccssssaccnsccss CABLE ASSY,RADIAL
COMPONENT.. DESCRIPTION.acecsoscssccscssccccansnsase UM
2220042-0022 2210149-0001 0996491-C006 09R3903-0002 2211340-0001
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CONTACTS: BERYLLIUM COPPER WLTF ENTIRE CONTACT UNRERPLATED WITH 0,76 mmNICKEL. CONTA'TS TO 0.76 mmGOLD PLATED.
CABLES: Mo. 28 AWC, 7 STRAND, TINNED, ANNEALED COPPER, ONE EDGE
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NUMBFRS FOR COKNECTORS AND CABLE ARE SHOWN IN
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3.2.2 IMPEDCNCE: 105 OHM NCMINAL
3.2.3 CAPACTTANCE: O0.045pf/mm NONINAL
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3.2.4 PROPACATION DELAY: 4.6ns/m
3.3
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3.3.1
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DESCRIPTION.eo csosocssnccasncensacscosss CABLE ASSY,DAISY CHAIN
COMPONENT. & NESCRIPTIONcecooeososaccccscseccananasce UM
2220042-0024 2211341-0001 099649 1-0003 0983903-0002 2211340-0001
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REQUIREMENTS
PHYSICAL: SEE FiGURE 1
MATERTALS: FLAMMABILITY
HOUSING, RATING
COVERS, 94V~2 OR
CLASS BETTER
REINFORCED
THERMOPLASTIC,
UL
CONTACIS: BERYLLIUM COPPER 0.76 m NICKEL. CONTACTS TO
WITH ©.76
ENTIRE m GOL[
CONTACT PLATED.
UNDERPLATED
WITH
CABLES: 0. 28 AUG, 7 STRAND, TINNED,
TO HAVE (OLOR
STRIPE.
POLYVINYL
CONDUCTORZ, UL STYLE 2651,
ANNFALED COPPER, ONE ELGE CHLORLDE INSULATION, 34
VEYDOR PART PARENTHESIS DPRAVINGS.
NUMBFRS AFTER
FOR THEIR
CONMECTORS AND DESCRIPTIONS
CABLE ARE SHOWN IN IN APPLICABLE FIGURE
3982 3.2.1 3.2.2 3.2.3 3.2.4
ELECTRICAL VOLTAGE/CURRENT RATING: 320 VOLTS/l AMP IMPEDENCE: 105 ORM NOMIXAL CAPACITANCE: 0.046pf/mm NOMINAL PROPAGATION DNELAY: 4.fns/w
343 3.3.1
3.3.2
ENVIRONMENT AMPRIENT TEMPFRATURE: T0 76 ¢
OPERATING
o
5
RELATIVE HUMIDITY:
10 TO 90%
o
TO 40 C,
by'
NON-GPERATING
o
=30
Ny l"i`
?("II.NNL'\KER T 6"2"/ `14/? 3
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sAcaie N9ON6E 214
A
2
5-150
12714783
PART NUMBFR
REV
0996289-8001
AB
ITEM, 0001
QUANTITY, 00001.000
List of Materials
DESCRIPTION.cocccessscosoonrssccscsccccss CORD SET,3-PIN PWR-DOMESTIC BLACK
COMPONENT., (©996289-C001
OESCRIPTIONcceessscecvcscscsocacassssanes UM
CORD SET,3-PIN PWR-DNMESTIC BLACK
EA
080126-0-7889-008-GY
5-149
SUGGESTED SOURCE(S) OF SUPPLY:
i 5
.
SGHAHREBSETMAR--ECSAE--H--E0O0-2B4EFACH--OLVE-
2
BPR.EILDC0E.HNMOBOCNXODRIP,1N101
{16428) 47374
:
S SRDBNH2BLRE5E3E7HL0ES-VOEBATOREEIO-BT5EEFHT--EEEOREPBNREELAHETAU--O--RHNUdIBDS4E~EA7B--3AE5BIE37RL94EE8T LE5CE--TR{O5I3H6E--7EBEES
4------£OFTRROBAE-MESIEPGREHAC--NHPIAA--IRAHKEE--SH{--C6a0R1D3S1P)
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HHNSE8ECMSFATOTHRNA--SERTHWREHECEETITRIG-E--HRA--E-----S--0C3A6B9L3EERE,
8.6------ESV6W6CSE.1IH8NE2CIBTH3CWOHA-A5MRSGRAG5OTIHR,NIRECEIHLKAYEA,SCILRPTL.RE----.EHR{MH.W--F6IRI0.ARIE6VEE--3E8PT0R2P&.8O9BC3UABELTES(--2B9C8HO7R.0P.)
Ti--e230.8
TI PART NUMBER
996289-0001 996289-0002 996289-0003 996289-0004
TI PART
N
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996289-0001 996289-0002
MF p URCE
SQURCE 2
0-803
BK
37-008
33561
SOURCE_3
99 89-
TI PART NUMBER 996289-0001 996289-0002
SOURCE B 996289-0001 996289-0002
x\ TEXAS INSTRUMENTS
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1 sreus OIvIIoN O':HIC"GID..I'POIAYID WOUSTON TEXAS
5-148
996289
[REV
SHEET
4
AB
O
4.0
QUALITY ASSURANCE PROVISIONS:
4,1
RESPONSIBILITY FOR INSPECTION:
UNLESS OTHERWISE SPECIFIED IN THE CONTRACT OR PURCHASE ORDER, THE
SUPPLIER SHALL BE RESPONSIBLE FOR PERFORMING INSPECTIONS THAT ARE
SUFFICIENT TO ASSURE THAT THE PARTS SUPPLIED MEET THE REQUIREMENTS
SPECIFIED HEREIN.
--AT--------TOT-ACCERTAMCET DELETED
TUTO ORI -- o
5.0
PREPARATION FOR DELIVERY:
5.1
PACKAGING:
PACKING AND WRAPPING SHALL BE SUFFICIENT TO PROTECT AGAINST DAMAGE
OR LOSS DURING SHIPMENT FROM THE SgPPLIER TO THE DESTINATION SPECI-
FIED IM THE PURCHASE ORDER. (BULK PACK IS ACCEPTABLE)
5.2
MARKING:
THE PRIMARY WRAPPING OR PACKAGING SHALL BE MARKED WITH THE TI PART
NUMBER (SEE PART NUMBER BLOCK) AND THE COUNT CONTAINED. ADDITION-
AL MARKINGS ARE PERMITTED.
5321
REGULATORY MARKING:
EACH SEPARATE SHIPPING CARTON MUST INCLUDE MANUFACTURER'S U.L. CORD SET
LABELS AFFIXED TO THE SURFACE OF THE SHIPPING CARTON, OR ON A TAG OR THE
EQUIVALENT INSIDE THE CARTON. EACH SEPARATE CORD SET MUST INCLUDE
MANUFACTURER'S C.S.A., LR, OR LL NUMBER PRINTED ON A DOUGHNUT-FLAG OR
BRACELET-TYPE LABEL
Timaz30-8
Jp TR ENATS --OIaITAL evareus Division
| Al s SHEET 3
I EV|
5-147
FIGURE 1 - CONT P~ 650 TYP.
ALTERNATE GRIP
TI DASH NUNBER
COLOR (REF)
ELECTRICAL RATING
WIRE SIZE,
A
AUG (STRANDING) | MIN
B
¢ DIA
MIN
" -0001
GRAY OR BLACK | 10 A MAX AT 125 V| 18 (41 X 34) |[86.0
3]
-0002
GRAY
10 A MAX AT 125 V§ 18 (41 X 34)
86.0
.32
.
~-0003
BLACK
15 A MAX AT 125 V| 14 (41 X 30)
116
.39
-0004
GRAY OR BLACK| 10 A MAX AT 125V | 18 (41 X 34)
116 | .32
NOTE:
CORD GRIP DESIGNED T CLIP TO BODY (CABLE) OF CORD ASSY TO RESTRICT SLIPPING, -0002 ONLY
FIGURE 1
3.4 3.4.1
MECHANICAL RETENTION FORCE, FEMALE PLUG: 3LB MINIMUM, 20LB MAXIMUM AFTER 10 CONDITIONING CYCLES TO A MATING RECEPTACLE.
Timaz30-C
B
XIABINSGICTA"OLIOURSSNYTPSOSTNOETH®SRTAEXDUAiTSvMIESIEODNNTS ?
5-146
996289
REV|
SHEEY
2.1
AB
382 383 3.3.1
RENUIREMENTS:
PHYSICAL:
SEE FIGURE 1
PLUG: PVC B80-86A SHORE. DURCMETER HARDNESS .. 60°C SERVICE,
CORD: =38=aUG, 3 CONDUCTOR, TYPE SJUTMEETING U/L STANDARD 62
REQUIREMENTS.
MARKING: PARTS SHALL BE MARKED WITH THE NMAHUFACTURER'S IDENTIFICATION,
WIRE TYPE (SJ7),YIRE SIZETIEARG), AND NUMBER OF WIRES (3CONDUCTOR).
FLASH IN WELL OF RECEPTACLE CONTACT SHOULD BE RESTRICTED TO BOTTOM 20% OF WELL
ELECTRICAL: SEE FIGURE 1 ENVIROMENTALSTORAGE TEMPERATURE RANGE:
-400 C TO 80° C
(SCéi
! = |
b e
A MIN
--
c DIA.--+
l]
) J¢
SEE FIGURE 2
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5-145
REVISIONS CONTINUED FROM PAGE 1
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DESCRIPTION
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SCOPE:
SEE PAGE 1.1 FOR FURTHER REVISIONS
THIS SPECIFICATION COVERS THE REQUIREMENTS FORA 3 PIN POYER CORD,
UNDERURITERS LABORATORIES AND CSA APPROVEG.
2.0
APPLICABLE DOCUMENTS:
THE FOLLOWING DOCUMENTS OF ISSUE IN EFFECT ON THE DATE OF INVITATION
TO BID OR REQUEST FOR PROPOSAL FORM A PART OF THIS SPECIFICATION TO .
THE EXTENT SPECIFIED HEREIN. 1IN THE EVENT OF ANY CONFLICT BETWEEN
THIS DOCUMENT AND THE REFERENCE DOCUMENTS, THIS DOCUMENT SHALL GOVERN,
MIL-STD-105
4
SAMPLING PROCEDURES AND TABLES FOR INSPECTION
BY ATTRIBUTES
N
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FLEXIBLE CORD AND FIXTURE WIRE
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(® - MOVE 12 PIN SHUNT 70 POSITION CUNNECTING REF. DES. 1G SOCKET PINS 2 THRU 13.
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REVISIONS
DESCRPTION
DATE
APPROVED
1.V SCOPE: THIS DOCUMENT DESCRIBES REQUIRED CONFIGURATION UF A FLOPPY DISK ODRIVE, SEE FIGURE 1
"»
REV SHEET
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5-133
12/14/83
List of Materials
PART NUMBER
RFY
2223220-8001
o
DESCRIPTIONccc cacccasscssscas WINCHESTFR DISK CONTROLLER -
ITEM.
QUANTITY,
COMPONENT., DESCRIPTIOM.csaces
0001
00001.000 2223220-0001
"WmIeMmCeHmEmST-E-R=00D0ISK CONTROLLER
£A
5-132
DWG
2223220
ISH 12
!
+ :
-
==
------------
e e
e ":
3.2 | =======
Interface =====
Bu=s===Timinsgm--zDsisassmr=asm=s=smsmsocs=ssssssssssossssossssssSssssoo==S=s
P] 3e .2.1
Timine relae tive to 0SC: --------mm
e
!
e
g
! The timine diasram for the interface bus relative to 0SC
ii. is shown in fisure 2.
=
-- Timine- relat-ive to CLKP:
N S SV SV S S SN :
The timine diasram for the interface bus retative to CLKP
is shown in fisure 3.
The resister assignment far the cantroller will ke as followss
R i HEXLA Addre--ss
N ! Q020 0031
. ! + . ' + ' !
+ ¢ {
+ ' '
+
IN Function Not used
' '
QUT Function
+ . |
+ ' .
+ ! '
+ ` ' +
__I_nt_e_r_r_u_pr_t___m_a_s _______
- i
an IN Function gets data from the winchester contfibller toard,
and driVes it onte the TIPC I/0 e¢xpansion bus. An OUT Function sets
from the TIPC I/0 expansion bus and drives it anto the winchester
controller board,
d
data
.! 2.3.2
Winchester
' 3.3.2.1
! ' ! ' ' ' ! . !
OATA INPUT
1/0
'
Port 1
FORT M3B
-
! Address
' !
0030
!
' ! ' ' ! ' !
: ' ! ' !
:
=
STRLIMENT:S
'
OATA
STEMS
!
SROUP
ot
oot ioccs o e seo ot
Contreller Resister Definition Disk read data and controller
| TN
RICO
:
W DATE
T
&
.-
DATE 1221028
ALE:D
+ ) i
NONG
-
VEHEET
e
=
ENETE T ER Y
5-131
NON-MASKABLE INTERRUPT DATA 7 ( msb ) DATA & OATA S DATA 4 OATA 3 DATA 2 DATA 1 DATA O ( sk ) WAIT SROLIND ADDR 19 ( msb ) ADDR 1= ADDR 17 ADDR 16 ADOR 1S ADDR 14 ADDR 12 ADOR 12 ADDR 11 ADDOR 10 ADDR ¥ ADDR % ADDR 7 ADDR & ADDR S ADDR 4 ADDR = ADDR = ADDR 1 ADDR © ( 1sb )
GNI : RESET 2 +5
IRO NC . NC = 12 = DMA~ +12 GND AMWC~ MROC~ AIOWCIDRCN NC NC NC NC CLEF IRA IRS IR4 IRZ IR1 & NG RF2H ALE +5 QS GND
GROUND
RESET
+3 VOLTS FOWER
INTERRUFT O
not connected
not connected
-12 VOLT3S FOWER
DIRECT MEMORY ACCESS F12 VOLTS POWER
GROLIND
ADVANCED MEMORY WRITE
MEMORY READ
ADVANCED I/0 WRITE
I/0 READ
not connected
naot connected
ot connected
not connected
not cennected
FROCESZSOR CLOCK (S MHZ) INTERRUPT &
INTERRLFT S
INTERRUFT 4
INTERRUFT 2
INTERRUFT 1§
not cannected
REFRESH
AODDRESS |LATCH ENAEBLE +3 VOLT POWER
CeSC CLOCK GRIZLIND,
(1S MHZ)
t TIPC Expansion Bus
Descrirtions
» CLOCK.
This
&b607 nsec period
sisnal is a hish speed =)
(15.0 MHz).
It has a SOY% du
FRUCEZZSOR CLOCK. This is third of the 050 frequency (5.00 MHz), The clock has
the svstem clock. It and has a periad of
a 37.4% nominal duty
is ane-- 200 nses cwviole (+=32%),
aumRtsiTsfhEoineatZoegateEnnitarTaictc.ltetetnirhrdevieewinasspdTeteuhe1nli2adsacrdtteeviivsooilviltPnimetcaonmewreee,trdshhlia.iiisasnsDhetu.uerwrPluiesnvdaesrRgduoEmpoZraesEndptTdo.odwubererirrilseeTnotshewieusbstrrenonsa1we1onr.rwP1aioltlwoloeiewuvdnrtaisltttihabfsayrlaoellrieiolatwzuhoeretmePhio.elwfrleoRisrrEvZsTtEthisTeimumsepaspnPtdlisvne
5-128
BACK OF CHASSIS--\
J5
J4
J3
J2
WINCHESTER CONTROLLER BOARD CONNECTOR FIGURE 1
viarea.s
-
TEXAS INSTRUMENTS INCORPORATED DIGITAL SYSTEMS DIVISION HOUSTON. TEXAS
5-127
2223220
REN
SHEET
8
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--_----
2223220
#*
'SH 11
|
IOWRITE~.
The I/ write sisnal is rnormallvy driven
b
the svstem eprocessar and indicates that the [/0 device
addressed bv the address bus should accert the data on
the data bus. This sismal can be driven by an expansicn
card after the CPILI ENABLE line is asserted.,
This sional
is active low.
IOREAD-.
The I/0 read tine is normally driven by the
svstem processor and indicates that the I/0 device
addressed by the address bus should place its data on
the data bus. This sisnal can be driven by an exPansion
card after the CPU ENABLE line is asserted.
This sisnal
is active low,
REFREZHING.
This Vine indicates that a memorv refresh
cvcle is takine place.
It is positive true.
While this
line is asserted all bus activity should be isnored,
P
ENABLE.
This line, when asserted low kv an
exPansion card, causes the pProcesser to cive wp
the
svstem busses and enter a wait state. This allows an
expansicon card to imPlement IMA
ar another
Processor.
When asserting
this line, the expansion card must wait
until the svstem busses are inactive
(MWRITE,
MREALD,
ITWRITE,
IOREAD all
inactive).
When deassertina CPU
ENABLE the expansion card must first wait until the bus
has been inactive for two pProcessor clack eweles, assert
the WAIT- tline, deassert the CPU ENABLE line, and
cantinue to hold the WAIT- Tine far one addtional
clack
zvcle.
This
will allow the swstem Processar
to
correctly execute its next bus cvale.
*
INSTRLUMENTS
DATA
EMZ
SR
DWG
2223220
1SH 10
:
# DATA 0-7. These bidirectional sisnpals carry the data
between
the processar,
memory, I/0, and the expansion
interface., These lines are active hiah.
i
# ANDR 0-19. These lines are normally driven by the
svstem pProcessor to
address memoary and I/0 devices
within the svstem. Thev can be driven bv an
exPansion
card by asserting the CFU ENABLE line low., These lines
are active hish. Onlwv XA0-XA? are used for I/0 addressins.
: '
# ADDRES3S LATCH. This line indicates when the pProcessor is placins a valid address on the address bus. The address is valid on the fallins edoe of this signal.
# SYSTEM FAULT-. This si=nal is driven bv one of the
expansion cards te interrupt the svstem pProcessor.
Its
' !
normal vse is to indicate a swvstem error condition.
:
# WAIT-.
This sional is used te indicate when a device in
i
the svstem or expPansion bus is to held or holding
the
'
system processor to extend the lenath of a memory or I/
!
crcle.
A slow device an the exPansiaon bus can assert
:
this line low when it is addressed to extend the time it
|
has to complete a cycle. An expansion card which takes
!
aver the bus must monitor this line when accessins
|
memsry or 1/0 devices within the svstem.
This line.
!
should never be held lTow longser than 10 PROCEZSZOR CLOCK
§
cvoles.
!
# INTERRIPT O-&. These lines are wused to signal
the
pracessor that an I/0 device resuires attentivn.
In the
event wof several devices reauiring service at the same
time, the device assertine the lowest numbersd line sets
serviced first. These lines are active hish.
# MWRITE-.
The memorv write signal is noermallv driven by
the svystem processor and indicates that the information
on the data bus should be written to memory at
the
address siven on the address bus. This signal is active
Tow,
This sisnal «can be driven by an expPansien card
! ' ' '
after the CFU ENABLE tine is asserted.
# MREAD-., The memory read sizgnal is normally
driven
bev
the svstem eprocessor and indicates that the memarwy
addressed by the address bus should be pPlaced on
the
data bus.
This sisnal
can be driven by an exPansion
card after the CFU ENARLE line is asserted. This siznal
!
is active low.
TATE
DATE 12--10~
5-129
12/14/83
PART MNUMBER
REV
2223219-8001
8
ITEM.
QUANTITY.
0001
00001.000
List of Materials
DESCRIPTIONsss evsooccsoccoenssccasccccss COLOR ,MONITOR,120,VAC/SPARES
COMPNENT.. DESCRIPTION.ceccscocrcrsssaccocccsscsnas
2223219-0001
MONITNR, COLOR 1669-0000-000
UM FA
12/14/83
PART NUMBER
REV
2223219-8002
8
ITEM,
QUANTITY.
0001
00001.000
DESGRIPTION,ccosescososcccoccscnasascnce COLOR 4MONI 222T , VN AC/R SP, ARES
COMPONENT.. DESCRIPTINN . cceccsccsnsnccss
2223219-0002
COLORMONTTOR,222 VAC 1669-0000-000
ccsccas
UM FA
-
5-126
REQUIREMENT
3.12 CONNECTORS
)
3.12.1 VIDEO CABLE.
THE VIDEO CABLE CONNECTOR TO THE COMPUTER
SYSTEM UNIT
SHALL
BECPSVEAHIIQBADNULLEOIELOUVATALWCEIOMNBITENASTHLN.EESCHTTTOHEOEWRR9TNHM.EINPMIAINOVTNNECEINATDTDBaOOLbDRREleINSUSLBHET3A AN-ME6LGIRC.LTNMOHIINANNPTAERTUTCOHRIETEVSEDOIRDMEOCMNEOWCIANIOATTSNMOHUEPR1RCAETTMDOIEETRBTNHLEDIERSAASMOPF+W/IC-TOPOTH/HNVNENE1ER0TCACH2VTLMEI0OLD5RE2.SVQ0EH4NIL-DEEC4OLNARDGB'TETL'HODHESER
INCLUDING CONNECTORS.
Table 3-& SYSTEM SIGNAL CONNECTOR PINOUT
PIN 1 2 3 4 S o 7 8 9 SHELL
SIGNAL
LOGIC GROUND (TIED TO PIN 2)
LOGIC GROUND (TIED TO PIN 1)
RED VIDEO
GREEN VICDEQ
BLUE VIDEO
N CONNECT
NO CONNECT
4
HORIZOMTAL SYNC
VERTICAL SYNC
CHASS1S (EARTH) GROUND
TM
< (:)
3.12.2 POWER. TCACUALAQ5(.NFANROEEICDTBIENGNR0HELTAGN1NMARESS0TAEISMFHLCNSATT1AHXAFOSTEIRPRRSGEIMORHERNDCUMIAOCSZGMLLUEIARMLNPDIOOTAD(EVUNHOCOI1ENERI,FNIDDTT)BBOOEYMTRR11OH9.2AAEN82POWAI30NPIT,6MRRG0PV1MEOO0OI5MR#VWCAOTOTFEETR-HNH,WSDRODETIHHERHSTEANMONL.CCBRLLAECEACOBFNAGAPMLSDOB/GUEWBEURLNLEIAH.EEREVSI5EACWULTTLHRHEEAE1EENRSSNTA3DGOMHSPT6ARTAIRE3)REHLIENM-.SFTMLLBA2IHRAL0TESOXSYEIMTIHSDO1M,AOBERULENLOOTSMLDARNHH1TTEAG9OEL8ABOLL3IFEN,BUEM1XNEE2IITL2GATFBTTAD0EHR3TPSLEMEO-HAMMNMECRI.IOANPRCCNNLIOOHETDMTLMINAECHUIPEUMNEGSCE/NELMTRNTSIICTAGIVMTHLMRSEUE3ODOMIFSOwRMFi.FGTITH3RCA9CTHTT-OA1AH3UOB4BITSTNLMLRRH'HOT8DEEMDESIENA UNIT AMD PROVIDED BY TiE VENTZOR. ©
T xAD
INGTRUMENMTS, TNC.
owWN
DATE
ISSUE DATE
01 /04, G
3-295
SIZE | FSCM NG
Al 96214
SCALE A
5-1256
DRAWING NO
222321
SHEET
~
REk)
A
1
REQUIREMENTE
Table 3-5 SERVICE CONTROLS HORIZONTAL HOLD VERTICAL HOLD SUB BRIGHT VERTICAL SIZE VERTICAL LINEARITY FOCUS VERTICAL CENTERING HORIZONTAL WIDTH RGB DRIVE RGB BACKGROUND
3.9.2 OPERATOR CONTROLS.
THE POSITION ENCLOSURE. GR OFF,
MONITOR SHALL HAVE SEPARATE
INTENSITY,
AND POWER ON/OFF CONTROLS LOCATED GM THE
AN INDICATOR LAMP SHALL INDICATE WHETHER
HORIZONTAL FRONT OF THE POWER IS ON
3. 10 PELIABILITY
3.10.1 MEAN TIME BETWEEN FAILURES.
1
THE EXCLUDING
MTBF FOR THE CRT.
THIS
MODULE
SHALL
BE GREATER THAN
«
20, 00 HDURS
3.10.2 PREVENTATIVE MAINTEMANCE. NO PREVENTATIVE MAINTENANCE SHALL BE REQUIRED FORF THE
MOMITOR ELECTRONICS.
Y
TEXAS JHSTRUMENTS, INC.
N15
DWN
DATE
3-20 SAIZlE | FS9CM 6NG214
DRAWING NO C22521
A REw
TEXAS oIkNST RAtUMs UNTS
Daras Toavas
5s0eoaTe
01/0a/3" Yo
SCALE
SHEE T
A
5-124
REGQUIREMENTS
3.6.2 VIDEO INPUT IMPEDANCE. THE HSYNC AND VSYNC INPUTS SHALL HAVE IMPEDANCES IN EXCESS
OF 1500 OHMS. VIDEO INPUTS SHALL BE 1 SCHOTTKY TTL LOAD EACH AND BE TERMINATED TO GROUND BY A 1000 OHM RESISTOR.
3.6.3 VIDED AMPLIFIER BANDWIDTH. THE VIDED AMPLIFIER BANDWIDTH SHALL BE A MINIMUM OF 25MHZ AT
THE -3DB POINTS OF THE AMPLITUDE/FREQUENCY RESPONSE CURVE.
3.7 CRT ARCING
ADEQUATE PROTECTION SHALL BE INHERENT IN THE DESIGN OF THE
MONITOR
TGO PRECLUDE
ANY CIRCUIT DAMAGE AS A CONSEQUENCE OF CRT
ARC(S).
3.8 POWER TURN ON
AFTER POWER RESULT DUE TO VERTICAL SYNC.
TURN ANY
ON, NO PERMANENT MONITOR FAILURE INSTABILITY OR LOSS OF HORIZONTAL
SHALL AND/DR
3.8.1 POWER OFF. WHEN THE MONITOR IS TURNED OFF, NO IMAGE SHALL REMAIN ON THE
SCREEN WHICH COULD CAUSE PHOSPHOR BURNING.
3.9 CONTROLS
3.9.1 SERVICE CONTROLS. SERVICE ADJUSTMENTS SHALL BE PROVIDED AS SHOWN IN Table 2-E.
TExat (HETRUMENTS, INC.
-[5%
DWN
TEXAS INSTRUMENTS [S508 DATE
DATE
fio sy
01/irk 4835
Al 96214 SIZE |S=FS1C9M NO
DRAWING NO 2223215
. A
sl
Seet
Z
5-123
DWG NO
|
REQUIKEMENTS
Table 3-4 VIDEO AC PARAMETERS
REF
PARAMETER
VaLUE
A
A~ VIDEO DOT FREQUENCY
B~ VIDED DOT PULSE WIDTH
C~ CHARACTER BLOCK HORIZUONTAL
D- CHARACTER BLOCK VERTICAL
E- NUMBER OF CHARACTER LINES
F~ NUMBER OF CHARS/CHAR LINE
G- NUMBER OF ACTIVE SCAN LINES
H- TOTAL SCAN LINES
J- VERTICAL SYNC WIDTH
K~ VSYNC FRONT PORCH
L~ VSYNC BACK PORCH
MN-
VERTICAL DLANKING INTERVAL ACTIVE VERTICAL DISPLAY TIME
P-- TOTAL VERTICAL TIME
G- VERTICAL RATE
R-- HSYNC WIDTH
S~ HSYNC FRONT PORCH
T- HSYNC BACK PORCH
UVW-
AHCOTRIIVZEONTHAOLRIZBOLNATNAKLINGDISIPNLTAEYRVATLIME TOTAL HORIZONTAL TIME
X- HORIZONTAL RATE
18. 000
i%
95%55
1%
9
12
(13)
25
80
300
(350)
320
(383)
0.156
(.156)
1%
0
(0)
1%
0.884 (1.6644) 17
1.040
(1.82)
1%
15.60 (18.20) 1%
16.63 (20.02) 1%
60.10 (49.9%) 2
4.50
1%
2. 00
1%
5. 50
1%
12.00
17
39. 99
1%
51.99
%
19231
100
NOTE NOTE
1: 2:
TAVI"NIASREMLSFIUEF"NEMIGSBGLULYREAEITNDTJOEUN3PRLS-ASY7TR.MEENRANTNETHDFSEERSREEFSOFTRLO E4CPTSTPOILHMYZIVNEGRRTTOEIFDCRI-AEA0LSG0HR0.2AM
~
UNE Y MHZ NS¢ DOTS SCAN L {WHEE ROWS COLUMNS SCAN LINES SCAN LINES MS MS MS MS MG MS HZ us us us us us us HZ
TEXAS [MNQTRUMENTS. ING,
3-163
r .
MI o
EXAS INICoNHESmTE RATUMY ENTS
Dartas Tewas
OWN
DATE
ISSUE DATE
01 /08, e
Al 96214 SIZE | FSCM NI
SCALE
2223219 DRAWING NO
SHEF
oRE'
5-122
HORIZONAL VIDEO
HORIZONAL SYNC
VERTICAL VIDEO
VERTICAL SYNC
--e
K --enf p--
e
b
|
FIGURE 3-7 VIDEO TIMING DIAGRAMS
P
TEXAS INSTRUMENTS INCORPORATED DIGITAL SYSTEMS DIVISION HOUSTON. TEXAS
5-121
2223219
REV
SHEET
25
REQU Tr Mz iR
3.5 3.2 BRIGHTNESS LEVEL.
WITH THE BRIGHTNESS CONTROL SET AS SPECIFIED IN THE PREVIOUS
PARAGRAPH,
ALL VIDEO INPUTS ON,
AND A FULL SCREEN OF WHITE
REVERSE VIDED GCCUPYING THE VIEWABLE AREA, THE BRIGHTNESS LEVEL
SHALL BE GREATER
THAN
15 FOOT-LAMBERTS
IN THE CENTER OF THE
SCREEN.
BRIGHTNESS UNIFORMITY OVER THE ENTIER SCREEN SHALL
CONFORM TO SPECIFICATIONS IN THE NEXT PARAGRAPH
3.5.3.3 BRIGHTNESS UNIFORMITY.
OVER THE ENTIRE VIEWABLE AREA THE
CONSTANT WITHIN
+/-20%,
AT A BRIGHTNESS
LAMBERTS.
BRIGHTNESS SHALL BE MEASURED
LOCATIONS (CENTER AND FOUR CORNERS).
BRIGHTNESS SHALL BE LEVEL OF 10 FODOT-
AT A MINIMUM OF 5
3.5.3.4 FOCUS
THE MONITOR SHALL EXHIBIT A SHARP FOCUS OVER THE ENTIRE
VIEWABLE AREA.
THERE WILL BE NO BLURRING OR FUZZINESS OF
INDIVIDUAL DOTS WHEN OPERATED AS SPECIFIED IN THIS DOCUMENT
3.5.3.5 JITTER.
UNDER NORMAL OPERATING CONDITIONS, NO MOVEMENT GREATER THAN ITS OWN DIAMETER.
PIXEL
SHALL 2
EXHIBIT
3.6 SIGNAL TIMING
THE MONITOR SHALL BE REGUIRED TO OPERATE AT THE RATES SPECIFIED IN Figure 3-7 AND Table 3-4
3.6.1 SIGNAL LEVELS.
VERTICAL SYNC SHALL BE A NEGATIVE TRUE
TTL
SIGNAL.
HORIZONTAL SYNC AND THE RED/GREEN/BLUE VIDED INPUTS SHALL ALL BE
POSITIVE TRUE TTL SIGNALS.
A TRUE OR "ON" CONDITION SHALL BE
DEFINED AS A "OFF" CONDITION
VOLTAGE BETWEEN 2.4 AND 5. 25 VOLTS.
A FALSE OR
IS A VOLTAGE BETWEEN 0.0 AND 0.4 VOLTS.
DRIVE
CURRENT IS PROVIDED BY A 74L.5244 BUFFER ON EACH VIDED LINE AND
HSYNC, AND BY A 74586 DEVICE ON VSYNC.
THE MONITOR SHALL OPERATE
OVER THE WORST CASE OUTPUT CHARACTERISTICS FOR THESE DEVICES AS
DEFINED IN THE TI TTL DATA BOOK
TEXAS INSTRUMENTS. INC.
Ili i
g TExAS oI:;¥RrIs`kME.\'TS
owN
DATE
SSUE DATE
01/06/8
Te 204594
3-16
SIZE | FSCWTM NC
A 9621 4
ORAWING NO
223M%
A REV
gt
St
=4
A
5-120
REGUIAEMENTS
3.5 DISPLAYED COLORS AND BRIGHTNESS
3.5.1 COLORS THE MONITOR WILL BE CAPABLE OF DISPLAYING THE COLORS SHOWN
IN Table 3-3
Table 3-3 DISPLAYED COLORS
VIDEQ INPUT {GREEN! BLUE
! DISPLAYED
'
COLOR
OFF IOFF
OFF IOFF
OFF {ON
OFF 10N
ON {OFF
ON (OFF
ON {ON
ON
ION
| OFF ! ON i OFF i ON | OFF | ON { OFF t ON
i
BLACK
!
BLUE
'
GREEN
{
CYAN
!
RED
!
MAGENTA
!
YELLOW
i
WHITE
U3CWCMIO.OITL5NTHO.T.R2RONLOWLSIECTVOTHELROLOFASRC,AELTSLHAEDIJVONUFIAMSDDOTEENOMDIQTETUHNOAETRRTI.NEPUSCTOODSLEOGTARSHAOSENU,STSOSDIUUTNEPHGIEPNLSTIUOSOERRCRERMEIOEUSSTNTHAHEADLJSOLUFHCSAOTLLASLMODPERJENUCBTSEIPTFUIRAOCIFTTAHPYTEUIIRNOEDNIIONFVTIEWCDROHNULITAAOTHLLREE CONVERGENCE.
3.5.3 BRIGHTNESS
BRIGHTNESS MEASUREMENTS SHALL BE MADE WITH A
759 FOOT-LAMBERT METER, OR EQUIVALENT.
BRIGHTNESS IS
MEASURED FROM THE
AT THE CENTER OF THE RASTER AT A DISTANCE
CRT FACEPLATE.
AMBIENT LIGHT SHALL BE SUCH
WESTON MODEL DEFINED AND
OF 50.8 MM THAT IT DOES
NOT AFECT THE BRIGHTNESS MEASUREMENTS.
3.5.3.1 BRIGHTNESS SETTING.
WITH THE FRONT PANEL MAXIMUM, AND NO RGB VIDEO BRIGHTNESS SERVICE CONTROL
BRIGHTNESS INPUTS APPLIED
SHALL BE SET
(INTENSITY) CONTROL SET AT (BLACK SCREEN), THE SUB-
S0 THAT THE BACKGROUND
RASTER 1S5 NOT VISIBLE.
-- TEXAS INSTRUMENTS, INC.
S
DWN
DATE
5
ot 11/05/82 TEXAS INSTRUMENTS [1550F OATE
T1-20458A
3-15 SIZE | FSCM NO A 9 6 2 `| 4
DRAWING NO 2223219
soms
sat 23
`
5-119
-
REVISIONS
DESCRIST-ON
T "vare
'"-':_
i
o
| aeproven :r`?:; o
-
BEY,
SHEET
REV STATUS OF SHEETS
or»«mu%ssssgscsso
2223219-0002
COLOR MONITOR, 220 VAC
2223219-0001 PART NUMBER
COLOR MONITOR, 120 VAC DESCRIPTION
A
23124125
REV SHEET TWR A,
ALAIATALA
AlA
AlB|B
A
(26 (27 |28 [29 (3013} [32]3334 | 3536|237 {38] 3P4 o4l (42
8 AlATA
AlAJAIALA
A
A
A
A
tl213lals|elrlalolo |v2[rahalis|ic]i7|igfiof2o]2|212
ROY D DATXBY,/19/82
@ °
TEXAS INSTRUMENTS
INCORPORAIED
) A/82
|
.
Digta) Systema Group
SI-METRIC
QA` <
L
& £ [ LTHISD ANGLE PROJECTION]
(o gy APVE-MFG
o
LT
S
7 7
" COLOR MONITOR SPECIFICATION
S|ZEA[FlSCoM 6NOees
2 SCALE NONE 40) 5-118
DRAWING NO
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5 A
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7
TEXAS INSTRUMENTS INCORPORATED
REV
A
2223107
DIGITAL SYSTEMS OIVISION HOUSTON, TEXAS
SHEET
T1-132186
5-117
¢
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TH-132148
5-116
12/14/83
PART NUMBER 2223106-5001
REY G
ITEM.
QUANTITY,
0003
00025.000
0004
00002.000
0005
00006.500
0011
00000,003
List of Materials
DESCRIPTIONceacessosocccosossocsncssnncns BULK CABLE ASSY,PARALLEL,PRINTER
COMPONENT.. DESCRIPTION:cocsscoccossscoscnvosccssscs
0539430-0003 221031 7-0001 2210505-0007 0972361-0003
CAMOPNTACT,-20P5I2N 02-2
24-20AWG ST
068
INSUL DIA
L0A8B5E4L8»0~B-LSALNPKF,-C1A9B3L1F9-4MARKFR
CABLE,SHIFLDED,25 CONDUCTORS
SEE TI- DRAWING TAPEFNAM, VINYL,SELF~ANH.25THK
.50WIDE
012624-V548
UN EA EA FT RL
12/714/83
PART NUMBER 2223106-5002
REV G
iTEM,
QUANTITY.
0004
00002.000
0005
00007.000
0007
00001 .000
0011
00000.003
DBUELSKCRICPATBILEONcAcSoScYossPcAoRcAaLsLoEvLasoscaconscsnccns
COMPONENT..
DESCRIPTINNeecccscsssa-csessscccsccascns
2210317-0001 2210505-0007 2211389-0001 0972361-0003
OLARB5E4L80y-BSLLAPNFK-,1C9A3B1L9F~4 MARKER
CABLE,SHTELDEN,25 CONDUCTORS
SEE TI- DRAWING
LUG, SEE
RING TI~-
TOMGUE,20-24 DRAWINMG
AWG
TAPE FOAM, VINYL, SELF-ADH,25TUK
012626-V548
<
.SOMNTDE
UM Fa FT EA PL .
5-115
12714783
PART HUMBER
REV
222310 6-0001
G
ITEM,
QUANTITY.,
0001
00001.000
0002
C0001.000
0006
00001.000
0007
00001.000
0008
00001.,000
00909
REF
0010 0012
00091.000 REF
o101
00001.000
List of Materials
DCAEBSLCERIPATSISEOMNR.LsYe,coPsAcRvAoLsLsFcLc,sPsRsIsNcTnERcccnnssone
COMPONENT.. 2220401-0003 2220380-0008 0414127-0001 2220555-0001
DESCRIPTINNcecescnsoscsncconnccscsancane UM
CONNECTLUO G,R2, 5X{ 420 ANG
EA
CABLE CLAYP ASSY,.400 SEF TI- DRAWING
IN. DIA.
CARLE ACC
FaA
CONNECTOR, PLUG=36 CONTACTS
EA
LUG,BARE,45 DEGRFF,R4 SCRFW HOLF,LOCKING FA
2223107-0001
WIRE LIST PT TO PT PRL PTR CARLE ASSY
EA
2265070-0001
SPEC, PRE-PRINTED CABLE MARKER
FA
2220797-0012 2362997-0001
FERRULE, 4 175" SEE TI- DWG ASSEMBLY +PACK,CABLE
FA FA
2223106-5001
B1U6L5K0-0C0A0B0LE~000ASSY,PARALLEL,PRINTER
EA
12714/83
PART NUMBER
RFYV
2223106-0002
G
ITEM,
QUANTITY.
0001
00001.000
00014
0002
00901.000
0006
00001.000
00064
0008
REF
0009
REF
0ol0
00001.000
0013
00000,000
0014
00001.000
0101
00001.000
NDESCRIPTIONcesaveeccncanssoscoccancasscne
CABLE ASSY,PARALLEL,PRINTER/850
2
COMPONENT . . DESCeR cocY cosI essP asosT scnI ccaN cnaN scces (M
2220767-0002
2220380-0008 2220674-0001
2223107-0001
CONNECTOR, PLUG¢25 CONTACTS ,2-POW,22~26AG FA
SEE T1- DRAWING
P2
SEE TI- DRAWING
CABLE CLAMP ASSY,.400 IN. DIA, CARLE ACC EA
SEF TI- DRAWING
CONNECTOR,RND CA T0 PANFL, PLUG,STL SHFELL FA
SEE TI- DWG
Pl
SEE TI- DWG
WIRE LIST PT TO PT PRL PYP CARLE ASSY
EA
2265070-0001
SPEC, PRF-PRINTED CARLF MARKFR
Ea
2220797-0012
FERRULE,.175TM
FA
SEE TI- DWG
0414127-0001
CONNECTOR, PLUG-36 CONTACTS
FA
2220827-0003
CONNECTOR,COVER,CAP,DR HOOD
EA
SEE TI- DRAWING
2223106-5002
RULK CABLF ASSY PARALLFL
EA
1620-0006-004
5-114
15t
TARLE #2: RECOMMENDED PARTS LIST
Note:
This Parts List does not include incidental hardware. This hardware and any substitutions for the assemblies listed are at the discretfon of the vendor, but the completed cable meet the requirements set forth elsewhere in this drawing and must be approved by TI.
Item
Reference Desig.
Vendor
T1 part #
Vendor Part #
5
Cable
Beldon Corp. P.0O. Box 1331 Richmond, In,
47374
2210505-0007
9543
Amphenol Connector Div. Bunker Ramo Corp. 2801 South 25th Ave. Broadview, I1, 60133
2220674-0001
157-32360
AMP Iac. P.0. Box 3608 Harrisburg, Pa,
17105
2220767-0002
745496-2
2
Cable Clamp
AMP Inc.
P.0. Box 3608
2220380-0008
745173-3
Harrisburg, Pa, 17105
«
4
Marker, Cable W.H. Brady Co.
2210317-0801
SLPF-19319-4
2221 W. Campen Rd.
P.0. Box 2131
Milwaukee, Wi, 53201
NOTE:
Item #2 may be replaced with a foil EMI shield and thermoplastic shell per section #3.
p f b 24 TexAs INIvNaRSeTORRATUIMD ENTS
0.4 o105
2590
OKWLN UNKERT
ISSUE DATE
0 ATE 07-06-83
SI2 FSCM NO
A 96214
DRAWING NO 2223106
scate NONE
12
A
REV
5-113
[>=c0)
y
TABLE #1:
WIRE LIST FOR CABLE 2223106
Vire #
1 2 3 4 5
6 7 8 9 10 1 12 13 14 15 16 17 18 19 20 21 22 23 24 215!
Calor Rlack White Red Creen Orange Blue White / BRlack Red / Black Green / Black Orange / Black Blue / PRlack Black / White Red / White Green / White Blue / White Black / Red White / Red Orange / Red Blue / Red Red / Green Orange / Green Black / White / Red White / Black / Red Red / Black / White Green / Black / White
P} Pin # L 2 3 4 5 6 7 8 9
10 11 12 13 14 32 31 36 33 19 <21 23 25 27 29 30
P2 Pin #
1 2 3 4 5
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 ~ 21 22 23 24 25
f e
DWN
GATE
SiZE | FSCM NO
DRAWING NO
REv
C
KLUNKE RT 07-06-83
A 96214
2223106
G
TEXAS INICNakSeToRRAUTIMD ENTS
D115 Terss 25910
Fesre sy
2 scate NONE
SHEET
11
5-112
0
| Fanoid
G
sueet (O
2223106
DRAWING NO
5111
scate IJONE
Jv'f' 1.6 S3 A 96214
ZE FECM AT
--=--i0"1570°20!
e
i e e
G OO O i i e o)
DATE
RUMENTS 1SSUE DATE
DwWN
(NOTLVDTATINIGL
"dWY1) 379YD Y3IONN 03¥NJ3S ANV 319vD ONNOYY G3ddviM 39 OL 11 W3LI (NOTLVIT4IINIAL S ¥IYNLIVANNYW)<~ Ay *90TE22Z WIGWNN Lyvd 11 `2d $1X3l
B B
S, ¥FUNLOVANNYIW¢) AJ¥ 901222 ¥ISWNN L¥Vd 11°Td "¥IINI¥d 137IV8vd 1x3L | v
£ W3LT 907 ¥3070S A9 M3YIS dWv13 318YD 01 QILYNIWYIL 38 01 JYIM NIVYQ Td
[2] TATEWISSY dWY1) 378YD 40 STI3HS WYTD Y¥3IANN Q30704 IYIM NIVYO 24
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N
Marhing
The warling texts listed in Vigure #1 shall be (ixed on the cable using the marker described in TT drawing 2210317, Marbaicg method js optional.
favirarmental
\nhient temperaturo:
Dperatine: 5 to 6N deprecs ,
Yor-operating: -30 to 70 deprees C.
Relative humidity:
iv to 90% i(non-coondensing)
Apency Requirements
Cable reels within the manufacturers facility per UL 83, UL 62, CSA 22.2 no 127, CSA no 299 requirments
shall be marked and CSA 329a
The cable assembly shall be UL listed under UL 478 for use
with electronic data processing units and systems. Vendor 1is
responsible for obttaining and maintaining UL approval of the
cable assembly.
All cab'es shall bear the UL listing mark.
The manufacturers fdentification and date code shall appear
on the jacket or molded connector housing portfon of the cable
wherever convenient and clearly visable.
The UL listing mark
is to be placed within 6 inches of the connector marked Pl,
QUALITY ASSURANCE PROVISIONS
>
Responsibility for Inspection
Unless otherwise specified in thke contract or purchase order,
the supplier is respoasible for the performance of all fas-
pection requirements specified herein.
Except as otherwise
specified in the contract or order, the supplier may use his
own or any other facilities suitable for the performance of
the {nspection requirements specified herein, unless dfs--
approved by the procuring activity. The procuring activity
reserved the right to perform any of the inspections set forth
in the specification where such inspections are deemed
necessary to assure supplies and services conform to
prescribed requirements.
It
oWy
DATE
KLUNKERT 07-06-83
BN R
A 96214
O AWING NO
2223106
REV
c
Trxas INSTRUMENTS 155UE DATE
scate NONE
SHEET
7
A
5-110
.2.2 .2.3
Connectors
Materfal: Housing and covers for Pl will be metal, and thermoplastic overmolding, UL flammability rating 94V2
for or
P2
hetter, CSA 356R stacdard UL 478,
compinents. (NOTF:
CSA certified
in primarv circuits).
and shall be UL recognized components are required only
Cortacts: A1l contacts will be Gold Plated
surfaces.
Crimp-type plns shall be bkright
the surface that the wire is crimped to.
on thelr cating ti{n plated on
Connector Current Rating: 5 Amps / Contact
Contact Resistance after Durability Testing: 5.5
maximum.
DNurabilfty testing shall consist of 50
tions and removals of mating connectors.
wOhms fnser---
Assembly
Shielding:
Fach connector shall be continuously shielded to
conform with FCC Part 15, Subpart J, concerning EMI emmis-
sions of computing machines.
This may be accomplished
through the use of a metal shell to which the cable "drain"
wire is attached by means of of foil surrounding it which
solder lug, is soldered
or through the use to hoth the connector
body and the drain wire.
If the foll method is used there
nust be a protective plastic cover over 1t.
Strain Relief: Both coanectors shall be be provided with
strain relief through the use of either metal backshells
or thermoplastic backshells.
If metal backshells are used,
provision must be made to insure that the clamp does not
break the outer jacket of the cable.
Dielectric Withstanding Voltage: 50-60 Hz.
1000 Volts RMS minimum,
Mechanical: Table 2 are by the same etc. ), and
If hardware other than the ones recommended in used, they must be secured to mating connectors method ( I.E. springclamps, machines screws, must be dimensionally equivalent.
Voltage Rating:
300 VAC RMS for continuous use.
g
DwWh
DATE
KLUNKERT 07-06-83
SIZE | FSCM NO
A 96214
DRAWING NQ
2223106
fAEV
G
TEXAS nLIoNkPSuTARTHUYMENTS
3 ax Taust 0.769:0
Freereraee
2scate NONE
SHEET
6
5-109
3.0
RFYUIREMENTS
ST
Physical
See Figure i1, Talle L and Table 2.
312 320!
Materfals and Comstruction
MM4osabstre7rhahap8eeatteleecealrridnandiifnovveaaitdevilbleirersdcso,CseenSpfplmAeieyhecnretnfiirmoit2fesa2naaiihn.ilfemne2esfe.dsnhee,ttecNcstoo,aennWaadaddnlh1ldei5mant4namw.idthawtoeerhintnrekthsmiiehaansrlegrtkxsmesalpaqpnnoteudsgsecibsseriarhdlffeaelailmxfleleopsdtnrootbsesnuocotirtrnhaeuecsohefcbtdlhlstiaoitptsssoahwstrrihsetsaiodrgclr,oehvfa,dsewrhniaawmctnlwiragolilat.pnlceegpkrre.,biraeeatnMliaasUafnbLsrlglkoewi,ng
Cable
UL Style 2464 Cable, capable of passing VW-1 Vertical Flame Test.
All wire & cable material used must be UL recognized CSA certified, and must meet UL - VW-1 Flammability
and
standards.,
Capacitance between conductors: 30 picofarads / foot.
Conductors:
Tinned copper, standard
lated by PVC 0.25 mm thick nominal.
24 AWG,
(7 x 32),
insu-
Shield: wire.
100Z coverage, aluminum polyester, number 24 drain
`
\.I\i~L\2 e
owN
DATE
KLUNKFRT 07--0066--83
Si2E | FSCM NI
A 96214
DRAWING NO
22 23106
REY G
FExAs (NICoNuSraTnaRcUrnMENTS s
2 was Teas T sg
3scae NONE
SMEET
5
6-108
______
n
CONVERSION CLART
|
----------- Fommmemee
KRB
| INCHES
|
---------------------- fomemme ¢
0.25
} 0.010
|
0.5
| 0.02
|
3.18
| 0.125
|
102.0 +/- | 4.0 +/- |
51.0
| 210
|
1066.8
| 42.0
|
----------- Fommmm et
11823109..02 +/- || 724.80.0 +/- ||
15.0
| 0.6
|
----------- dommmemmea
---K-IL-O-S----- t| ommmmmLBS
|
e m--a}
14
|
31
|
THIS IS A COMPUTER GENERATED DOCUMENT,
(_L)e--
23
I
51
|
DO NOT REVISE MANUALLY. CONTACT
----------- oot
COMPUTER-AIDED-DOCUMENTATION GROUP.
mmmmc--me e m e
--ndm bbb e e b oo m b mp e m b eb e b e b
REV. sTATUS | REV. | G| 6l 6l 6l ¢l ¢l ¢} ¢l ¢l el 6l 6t | I
| -- | e e p1 mm | == ]
OF SHEETS
Fomme e e e o
e b
mm e e e m b mp e et b m o -- e
| sHeeT!| 1) 2! 3] 4] s| el 71 81 gfrofrrir2y |+ | + | | |
------------ oo --b o bbb mt bbb o bbb b m-- - --
unless other- |
DATE |
Texas Instruments
|
wdiismeenssipoencsifiaedre|l
in millimete tolerance:
Ors| |
CDWHNK_MD.UBNIHAEMHL____0065--0194--8822]] EANPGVR__MM..KKEENNDDFELL___0066--1100--8822]|
Incorporated Data Systems Group
| SI-METRIC
angles +/- 1 | QA R.cAPAM__~~ 06-10-82]| 21 ppllaaccee ++//--0.25.=5| MRFELG__MSI.KBERIDWGOELNF___0066--1101--8822]}
CABLE ASSEMBLY, PARALLEL, PRINTER
s
¢ Trxas INSTRUMENTS
oA
oW
KLUNKFRT FgsteoaTe
26910
540
DATE
07-06-83
SIZE | FSCM NO
A 9621 4 scaie NONE
A
5-107
DRAWING NO
2223106 SHEET
REV
G 1 oF 12
DB /
SUGGESTED SOURCE{S) OF SUPPLY: 1. BELDEN CORPORATION
P.0. BOX 1980 RICHMOND, INDIANA 47374
2. VICTOR ELECTRIC WIRE & CABLE CO. 618 MAIN ST. WEST WARWICK,R.I. 02893
TEXAS INSTRUMENTS PART NUMBER
2223105-0001
SOURCE 1 IF-4310
MANUFACTURER®S PART NUMBERS
SOURCE 2
SOURCE 3
T80
Ti~4239.E
{'ib TexaOsN COOIRNMaSnPTOTRRerAUnTMaoEENDNTS
A
2223105
SHEET
3
IREV
*
6-106
ROIRFMENTS:
P+ ICAL. "TH FIGURE ]
3 CABLE FATICLSE CIFCORGETION S22 At CONSISTING OF 7 STRANDS OF #56 AWG
PARE COPPLw WIRE OR 7 STRANDS OF =35 BARE COPPER COVERED SIFEL WiRY. SHELS CONSISTS OF 4 ENDS CF #36 AWG TINNED COPPER SRIRAL WRAPFED OR BRAIDED COPPER WIRE. INTERNAL TNSULATION CF POLYETHYLENE WITH QUTER JACKET AND CONNECTOR MOLDING TO BE L{GHT TAN IN COLOR MATCHING TI COLOR NUMBER 972939-21C1. CABLE ASSEMBLY TO MEET THE REQUIREMENTS OF UL AND CSA.
3.1.¢
MARKINGS PARTS OR WRAPPtR SHALL BE MARKED WITH TEXAS INSTRUMENTS PART NUMBER .
3H]1M3
IMPEDANCE: CABLE IMPEDANCE SHALL BE 755 NOMIMAL.
3.1.4
CONNECTORS: BOTH ENDS OF THE SHIELDED CABLE SHALL BE WITH VICTOR PC-103 PHONO PLUGS OR BELDEN STRAIGHT HANDLE PHONO PLUGS.
TERMINATED EITHER STYLE PHG761 SHORT
=alij
TimezsoE
B a1 210 2 B
e i
==
CABLE DIA. 3.81 NOM
FIGURE 1
[4 if. i
TeExAs INSTRUMENTS INCORPORATED TO S Garan veanss "
5-105
[
2223105
[REV]
A
SHEET
2
12/14/83
PART NUMBER
REV
2223100-5001
R
ITEN.
QUANTITY,
0086
00000.000
00864
00868
12/14/83
PART NUMBER
REV
2223100~8001
R
ITEM.
QUANTITY,
0001
00001.000
0002
REF
List of Materlals
VDIEDSECQRIPCTRIT OMCeOeNsTeRe{cLcLvFcRe,snAnUsTsDe-
COMPONENT. 2210759-0001
DESCs sR eenI ncecP ocnT nsvsI ancO nnsaN nsens UM
1Cy5157,QUAD+2/1 LIME uV2-0LIST-S$157 BURN-IN
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A
VS-ULBISSTITT-UST1E57
BURN-IN FOR ITEM
49
V=LIST-S1S7 BURN-IN
VDIENSECDRIPCRTTIDOCNOGMeToReOeLcLaEsRo/eSoPsAnRcEnScecccnonscnnae
COMPONENT.. 2223100-0001 2231993-0001
DESCRIPTIONececetasseconscnsrssacnacaces VIDED CRT CONTROLLER 1254~3100-060 SERVICE PACK INDEFX-RMR
UM FA EA
12714783
PART NUMBER
REV
2223100-5001
R
ITEM.
QUANTITY.
0076 00764 00768 0077 00774
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00000.000 00000.000 00.00.000 0C000.000 00000.000 00000, 000 0C070.000 00000.000
List of Materials
DESCRIPTION.caccses VIDEN CRT COMTROLL
COMPONENT.. DESCRIPTION:cecsasccscccacncasccccsacsss UM
2210649-0001 2210614-0001 2210749-0001 2210740-0001 2210621-0001 2210735-0001 2210738-0001 2210604~0001 2210674-0001 2210763-0001
IC+L5125,QUAD BUS BUFFER W/3-STATE OUTPU EA
V- IST-L5125 BURN-IN
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5-103
12/14/83
PART NUMBFR
REV
2223100-5001
R
ITEM.
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List of Materials
DESCRIPTION.ssesceovccanccsccnson VINEG CRT CONTROLLER, AUTO-INSERT
COMPOMENT.. DESCRIPTINNe.vcocossoconcs
esesecvscas UM
2210739-0001 2210660-C001 2210695-0001 2210721-0001 2210764-0001 2210694-0001 2210669-0001 2210662-0001 2219761-0001 2210631-0001
TIS AN -ASCNC7E4P5T0A8BNLE SUBSTITUTE f
IC+ 508, QUAN, 2-INPUT PNSITIVE AND
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12/14/83
List of Materials
PART NUMBER
REV
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DESCRIPTINNcocecscsovoscocvsssscssnssses VIDED CRT CONTRMLLER, AUTO-INSERT
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5-101
TECHNICAL REFERENCE
SCHEMATICS ANfi LOGIC DRAWINGS
Section 6
SCHEHMATICS AND LOGIC DRAWINGS
This section contains schematic and logic drawings applicable to
the
Texas Instruments Professional Computer.
Title
Motherboard, Logic Logic, Alphanumeric CRT Controller Logic, Option RAM Logic, Graphics Video Board Logic, Communications Board Logic, Video CRT Controller Logic, Speech Logic, Telephone Logic, 256/512k RAM Expansion Logic, 256k RAM Expansion
TI Drawing No.
2223005 2223011 2223017 2223063 2223096 2223102 2232375 2232405 2234245 2234248
Page No.
6-3 6-8 6-11 6-14 6-18 6-20 6-24 6-29 6-24 6-40
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TECHNICAL REFERENCE
SYSTEM I/O MAP
Appendix A SYSTEM I/0 MAP
Address Motherbdoard:
00000
-
00001
00002 00003
Table A-1 System I/O Map
Device
Bit/Use
U47 Latch
U48 Input buffer
U49 Latch US0 Latch
NOWMLENO
3
DA WN U O
N 0
haWwNO
Speaker timer enable Timer 1 inter rupt enable Timer 2 inter rupt enable Single-densit y (FM) enable Track greater than 1/2
(TG43)
Diskette side one enable
(FS1bp-) Diskette mode Diskette mode
control control
(M1) (MO)
Option
4 jumper
E1-E2
Option jumper E3-E4
Option- jumper ES-E6
Parity interr upt pending
Printer port BUSY
Printer port paper out
Printer port printer
selected
Printer port NO fault
7 Printer port data outputs
LED i1 OFF
LED 2 OFF
LED 3 OFF Parity interr upt enable Printer port not auto feed Printer port not strobe Printer port not
initialized
TECHNICAL REFERENCE
SYSTEM I/O MAP
NOAOUNAWNKO b R WWN
Table A-1 System
Address
Device
1/0 Map (Comtinued)-
Bit/Use
Motherboard(Continued):
00004
Usi Latch
Piskette Digskette Diskette Diskette Diskette Diskette Diskette Diskette
Drive Drive Drive Drive Drive
Drive Drive Drive
SELECT SELECT SELECT SELECT MOTOR MOTOR MOTOR MOTOR
00005~-0000F
Reserved
00010 00011
U44 8251 USART U44 B82S1 USART
Data Register Control Register
00012-00013
Reserved
00014 00015 00016 00017 00018
00019
00020
00021 00022
0023 00024-0002F
U4S B8253 Timer
Counter ©
U4s 8253 Timer
Counter 1
U4S 8253 Timer U4S 8253 Timer
Counter Control
2 register
U46 B2SS9A Interrupt
oy
controller
i
U46 8259A Interrupt
controller
-
FDC Command register
or RAM
FDC Track register
FDC Sector register
or RAM reset
FDC Data register
Reserved
Winchester Controller Board:
00030
Winchester I/0 port
Input: 0-7
Don't care. held for handshake
Data is each
cycle.
Outpat:
0-7 Don't care. Data is latched til updated.
TECHNICAL REFERENCE
SYSTEM I/O MAP
Table A-1 System 1/0 Map (Continued)
Address 00031
Davice Winchester
reset
Bit/Use register
Winchester
Controller
Board
W N
O
Read: Data request Input/Output Command/Data Interrupt pending (Level 6)
Write: 0-7 Don't care (Any
write will do a
RESET)
(Continued):
00032 00033
Future Options: 00034-0003B 0003C-0003F 00040-0008F
&
Not used Interrupt Mask
0 Status interrupt enable
1 Data interrupt disable
Reserved
Local Area Net I/O
Reserved
»
TECHNICAL REFERENCE
SYSTEM I/O MAP
Table A-1 System
Address
Device
I/0 Map (Continued) Bit/Use
Clock and Analog Interface:
000CO
Clock/Analog Interface
N A VWN
o
=N WA
End of conversion
(EOC)(Active HIGH) Not used (tied LOW) Lightpen interrupt latch ON Battery low
Switch Switch Switch Switch
000C1 000C2
¢oocCs 000Cso oooca 000CB 00o0CC 000CD 000CE O0COCF 000DO
000D1-000D7 ooobDs 000D9-000DF
Do not allow light
pen interrupt
(tri-state signal)
Allow light pen
interrupt (Pass
interrupt signal)
Joystick port Xi
(Current sense)
Joystick port Y1
{Current sense) Joystick port X2
(Current sense)
Joystick port Y2
(Current sense)
Analog input 4
(SW4) (Voltage Analog input 3
sense)
(SW3) (Voltage Analog input 2
sense)
(SW2) (Voltage Analog input 1
sense)
(SW1) Clock Control
(Voltage
sense)
NOUhRWN K
W N O
0 Address Bit Address Bit Address Bit Address Bit
MSHMS832
MSMS5832 MSMS5832 MSKS5832
clock
clock clock clock
HOLD
WRITE
READ
+ or - 30 sec adjust
Reserved
Clock data
(low nibble only) Reserved
TECHNICAL REFEREKCE
Table A-1 System /0 Map (Concluded')
Address
Device
Bit/Use
SYSTEM I/0 MA}
Sync-Async Comm Board:
O0OOEQG-000E3 000E4 OCOES 000E6
O00E7
COMM Port 1 IR1
OOOE8-000E8 000EC COCED COOEE
O00EF
COMM Port 2 IR2
O000F0~000F3 000F4 O0O0O0FS OO0O0OF6 O00O0F7
COMM Port 3 IR3
000F8-000FB 000FC O000FD COOFE
OO0OFF
COMM Port 4 IR4
00100-~003FF
Interrupt Acknowledge CHB command CHB data CHA command
CHA data
Interrupt Acknowledge CHB command CHB data CHA command
CHA data
Interrupt Acknowledge CHB command CHB data CHA command CHA data
Interrupt Acknowledge
CHB Command
CHB Data
e
CHA Command
CHA Data
Available for future products
A-S/¢
TECHNICAL REFERENCE
SYSTEM MEMORY MAP
C
Table B-1.
System Memory Map, Concluded
Address
Devices
DFOC1-DFOOF DFO10-DFOLF DF0O20-DFO2F DF030-DFO3F DF040-DF7FF DF800-DF8OF DF810 DF811l DFB12 DF813 DFB814-DFBLF DFB2¢C
Other Peripherals: DF821-DFFFF ECQOO-E7FFF EB8COO0-F3FFF
ROM Usage: F4000-FSFFF F6000-F7FFF F800C0-FSFFF FAOOO-FBFFF FCOOO-FDFFF FEQOO-FFFFF
Miscellaneous input buffer Graphics RED palette
latch, write only Graphics GRN palette
latch, write only Graphics BLU palette
latch, write only Reserved Attribute latch
CRT controller address register, write only
CRT Controller status register,
read only CRT Controller address register,
write only CRT Controller address register,
write only
Reserved
Bit 7 Bit 6
Miscellaneous output latch, interrupt enable =
Miscellaneous output latch, alphanumerics screen enable
Reserved Reserved for speech storage RAM Reserved
8K ROM space(Clock/Analog Interface)
8K ROM space(Local Area Net Option Board)
8K ROM space(Winchester Controller) 8K ROM space(Reserved) 8K ROM space, 1 wait state (XUs2)
(motherboard) 8K system ROM, 1 wait state (U63)
(motherboard)
TECHNICAL REFERENCE
SYSTEM MEMORY MAP
Appendix B SYSTEM MEMORY MAP
Table B-1 System Memory Map
Dynamic RAM:
Address
Q00CO-OFFFF 10000-1FFFF 20000-2FFFF 30000-3FFFF
40000-BFFFF
Devices
64-kbytes motherboard RAM 64-kbytes expansion RAM board Bank 1 64-kbytes expansion RAM board Bank 2 64-kbytes expansion RAM board Bank 3
Expansion bus memory
CRT Controller:
CO0000-C7FFF CB000O-CFFFF DOOOOC-D7FFF D800CO-DDFFF
DECOO-DE7FF DESOO-DEFFF
DFO000
Graphics RAM Bank A
Graphics RAM Bank B Graphics RAM Bank C Reserved
Active character memory Phantom character memory
Bit 0 Bit 1 Bit 2 Bit 3
2
Miscellaneous input buffer, BLUE feedback, read only
Miscellaneous input buffer, RED feedback, read only
Migscellaneous input buffer,
GREEN feedback, read only Miscellaneous input buffer,
interrupt pending, read only
TECHNICAL REFERENCE
CHARACTER SET
Appendix C CHARACTER SET
ACK BEL BS CAN CR DC1 BC2 DC3 DC4 *DEL DLE EM ENQ EOT ESC ETB ETX
From
Table C-1t USA standards
ASCII Control Characters Institute Publication X3.4-1968
acknowledge bell backspace cancel carriage return device control 1 device control 2 device control 3 device control 4 delete data link escape end of medium enquiry end of transmission escape end of transmission end of text
block
FF FS GS HT LF NAK NUL RS SI so
SOH « 8TX
sSub SYN us vT
form feed file separator group separator horizontal tabulation line feed negative acknowledge null record separator shift in shift out start of heading start of text substitute synchronous idle unit separator vertical tabulation
*
Not strictly a control character
TECHNICAL REFERENCE Table C-2. Numeric Cross Reference for Character Sets
CHARACTER SET
Decimal
0 1 2 3
4 5
6 7 8
9 10
1 12 13
14 15 16
17
18 19
20 21
Hexadecimal
00 01 02 03
04 05
06 07 08
09 0A
08 oc 0D
OF oF
10
1
12 13
1 15
Keystroke(s)
CTRL2 CTRLA CTRLB CTRLC
CTRLD
CTRLE
CTRLF CTRLG BBAACCCSKTKHSRISPLFPTHAA,,CCEE,
CTRLI CTRLLICNTERRLEFJTE,UERDN,
CTRLK CTRLL SHIFRCTETTRURLREMNT,,URN
CTRLN CTRLO CTRLP
CTRLQ
CTALR CTRLS
CTALT CTRLU
ASCII Character
NUL SOH STX ETX
EOT ENQ
ACK BEL
BS
HT LF
VT FF CR
) st DLE
DCi
DC2 DC3
DC4 NAK
Displayed Character
Comments
B B »
» %
& +
&
s
3
_
d
Q
F
3 It >
-4
3 i
q g
TEGHNICAL REFERENCE
CHARACTER S8BT
Table C-2. Numeric Cross-Reference for Character Sets {Continued)
Decimal
22
23 2
2
26
27
Hexadecimal
16
17 18
19
1A
iB
28
1c
29
1D
30
1
31
1F
2
20
33
21
4
22
35
23
36
24
37
25
38
26
39
27
40
28
M
29
42
2A
43
28
Keystroke(s}
CTRLV
CTRLW CTRLX
CTRLY
CTRLZ CTRLI,
ESC, SHIFTESC, CTRLESC
CTRL\ CTRL]
CTRLG
CTRL --
CTRL SPACE,
SPACE BAR, ALT SPACE, SHIFT SPACE
! -
# $ % & ¥ ( } . +
ASCH Character
SYN
ETB CAN
EM
SUB
ESC
Displayed Character
-
3 1
J
-+
4
Comments
FS
|
GS
+
RS
A
us
Y
SP
' Blank space
.
!
|
Exclamation point
=
"
Quotation marks
#
#
Number, Pound
$
$
Doltar sign
%
%
Percent sign
&
Ampersand
<
-
Apostrophe
(
{
Open parenthesis
)
}
Close parenthesis
v
5
Asterisk
+
+
Plus
TECHMICAL REFERENCE
CHARACTER SET
Table C-2. Numeric Cross-Reference for Character Sets (Continued)
Decimal 44 45 46 47 48 49 50 51 52 53 54 55 56 57 68 59 60 61 62 63 64 65 66 67 68
Hexadecimal 2C 2D 2E 2F 30 31 32 3 34 35 36 37 38 39 3A 38 3C 30 3E 3F 40 41 42 43 44
Keystrokel(s) , -
/ 0 1 2 3 4 5 6 7 8 9
A < = > ? @ A B C D
ASCIl Character
0 -
/ 0 1 2 3 4 5 6 7 8 9
h < = > ? @ A B C ' D
Displayed Character
D -
/ 0 1 2 3 4 5 6 7 8 9
B < = > ? @ A B C D
Comments Comma Minus, Hyphen Period, Decimal point Slash, Virgule Zero One Two Three Four Five Six Seven Eight Nine Colon Semicolon Less than Equals sign Greater than Question mark Commercial "`at" A (uppercase} B {uppercase} C (uppercase) D (uppercase)
TECHNICAL REFERENCE
CHARACTER BET
Table C-2. Numeric Cross-Reference for Character Sets {Continued)
Decimal 69 70 71 72 73 74 75 76 77 78 79 80
81
82 83 84
85 86
87
88 89 90 9N 92 93
Hexadecimal 45 46 47 43 49 4A 48 4Cc 4D 4E 4F 50.
51
52 53 54
55 56
57
58 59 5A 68 5C 5D
Keystroke(s} E F G H | J K L M N 0 P
a -
R S T
v v
w
X Y 4 { \ ]
ASCll Character
E F G H | J] K L M N o] P
Q
R S T
U v
w
X Y Z ( l \ ]
Displayad Character
Comments
E
E {uppercase}
F
F {uppercase}
G
G (uppercase)
H
H {uppercase}
|
| (uppercase)
J
J (uppercase}
K
K {uppercase)
L
L (uppercase}
M
M-{uppercase)
N
N (uppercase)
0
O {uppercase}
P
_f'(uppercase)
Q
Ql(uppercase)
R'
R {uppercase)
S
S'{uppercase}
T
T {uppercase)
U
U: {uppercase}
Vv
V:(uppercase)
w
W {uppercase}
X
X {uppercase}
Y
Y {uppercase}
z
Z (uppercase)
[
Open bracket
\
Left slash
]
Close bracket
TECHNICAL REFERENCE
CMARACTER SET
Table C-2. Numeric Cross-Reference for Character Sets {Continued}
Decimal 94 95 96 97 98 9 100 101 102 103 104 105 106 107 108 109 110 11 112 113 114 115 116 117 18
Hexadecimal SE 5F 60 61 62 63 64 65 66 67 68 69 6A 68 6C 6D 6E 6F 70 7 72 73 74 75 76
Keystroke(s} s M a b c d e f g h i je k | m n o p q r s t u v
ASCl Character
2 > a b c d e f g h i j k | m n o P q r s t u v
Displayed Character . Comments
o
Circumflex
-
Underline
S
Graves accent
a
a (lowercase)
b
b (lowercase)
c
¢ (lowercase)
d
d (lowercase)
e
e (lowercase}
f
f {lowercase)
g
g (lowercase)
h
h (lowercase)
i
i (lowercase)
i
j (Io-wercase)
k
k (lowercase}
i
| {lowercase)
m
m {lowercase)
n
n {lowercase)
o
o {lowercase}
P
p (lowercase}
q
q (lowercase}
r
{lowercase)
s
s {lowercase)
t
t (lowercase)
u
u {lowercase)
v
v (lowercase)
TECHNICAL REFERENCE
CHARACTER SET
Table C-2. Numeric Cross Reference for Character Sets (Continued)
Decimal
119
120
121
122
123
124
125
126 127
128 129 130 131 132
133 134
135 136 137 138 139
140
141 142
Hexadecimal
77
78
79
7A
78
7C
70
7 7F
80 8t 82 83 84
85 86
87 88 89 8A 8B
sc
8D 8E
Keystrokels)
w
X
y
z
{
!
}
~ CTRL-- BACKSPACE ALT 128 ALT 129 ALT 130 ALT 131 ALT 132
ALT 133 ALT 134
ALT 135 ALT 136 ALT 137 ALT 138 ALT 139
ALT 140
ALT 141 ALT 142
ASCII Character
w X Y
z
{
|
}
~ DEL
Displayed Character
w X y z {
!
}
~
Comments
w {lowercase} x {lowercase) y (lowercase) z {lowercase) Open brace
Vertical rule, Bar
Close brace
Tilde ASCII DEL
G U § 5 i
3 a
§ 8 g 3 T
1
3 A
TECHNICAL REFERENCE
CHARACTEBR SET
Table C-2. Numeric Cross-Reference for Character Sets (Continued}
Decimal
143 144 145 16 147 148 149
150
151 152
163 154 155¢ 156 157 158 159 160
161 162 163 164 165 166 167
Hexadecimal
8F %0 N 92 93 94 95
96
97 98
99 9A 98 9C 9D 9E 9F A0
Al A2 A3 A4 A5 A6 A7
Keystroke(s)
ALT 143 ALT 144 ALT 145 ALT 146 ALT 147 ALT 148 ALT 149
ALT 150
ALT 151 ALT 152
ALT 153 ALT 154 ALT 155 ALT 156 ALT 157 ALT 158 ALT 159 ALT 160
ALT 161 ALT 162 ALT 163 ALT 164 ALT 165 ALT 166 ALT 167
ASCII Character
'
Displayed Character
A E 2 & 8 s 3
o
U ¥
0 U ¢ £ X P+ f 3
i g o rT i B u
Comments
. 2
TECHNICAL REFERENCE
CHARACTER BETY
Table C-2. Numeric Cross-Reference for Character Sets {Continued)
Decimal
168 169 170 17 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192
Hexadecimal
A8 A9 AA AB AC AD AE AF BO B1 B2 B3 <« B4 B5 B6 B7 88 B9 BA BB BC BD BE BF co
Keystroke(s)
ALT 168 ALT 169 ALT 170 ALT 171 ALT 172 ALT 173 ALT 174 ALT 175 ALT 176 ALT 177 ALT 178 ALT 179 ALT 180 ALT 181 ALT 182 ALT 183 ALT 184 ALT 185 ALT 186 ALT 187 ALT 188 ALT 189 ALT 180 ALT 191 ALT 192
ASCII Character
:
Displayed Character
£ 1 % % g < >
Comments
1 '
Il 1
TECHNICAL REFERENCE
CHARACTER SET
Table C-2. Numeric Cross-Reference for Character Sets {Continued)
Decimal 193 194 195 196 197 198 199 200 201 202 203 204
205 206
207 208 209 210 n 212 213 214 215 218 217
Hexadecimal c1 c2 C3 c4 C5 ce c7 c8 c9 CA CB cC
co ° CE
CF Do D1 D2 D3 D4 D5 D6 07 08 D9
Keystroke(s} ALT 193 ALT 194 ALT 185 ALT 196 ALT 197 ALT 198 ALT 199 ALT 200 ALT 201 ALT 202 ALT 203 ALT 204
ALT 205 ALT 206
ALT 207 ALT 208 ALT 209 ALT 210 ALT 211 ALT 212 ALT 213 ALT 214 ALT 215 ALT 216 ALT 217
ASClH Character
Displayed Character
i
T
Comments
"
.
n
;
TECHNICAL REFERENCE
CHARACTER SET
Table C-2. Numeric Cross-Reference for Character Sets (Continued)
Decimal 218 219 220 21
222
223
224 225 226 227 228 229 230
231
232
233
234 235
236
237 238
239
240
241
242
Hexadecimal DA DB DC DD DE DF EO E1 E2 3 E4 E5 E6 . E7 E8 E9 EA EB . EC ED EE EF FO F1 F2
Keystroke(s) ALT 218 ALT 219 ALT 220 ALT 221 ALT 222 ALT 223 ALT 224 ALT 225 ALT 226 ALT 227 ALT 228 ALT 229 ALT 230 ALT 231 ALT 232 ALT 233 ALT 234 ALT 235 ALT 236 ALT 237 ALT 238 ALT 239 ALT 240 ALT 241 ALT 242
ASClI Character
*
Displayed Character
« B r n z o u
T
¢
9
Q d
©
@
n
=
+
>
Comments £
TECHNICAL REFEREXNCE
CHARACTER SET
Table C-2. Numeric Cross-Reference for Character Set (Concluded)
Decimal 243 244
245
248 247 248 248 250 251 252 253 254 255 «
Hexadecimal F3 F4
F5
F6 F7 F8 F8 FA FB FC FD FE FF
Keystroke{s) ALT 243 ALT 244
ALT 245
ALT 246 ALT 247 ALT 248 ALT 249 ALT 250 ALT 251 ALT 252 ALT 253 ALT 254 ALT 255
AsCH Character
Displayed Character
< r
2
=
2 ° . v n Z
B
Comments .
TECHNICAL REFERENCE
CURRENT REQUIREMENTS
Appendix D CURRENT REQUIREMENTS
This appendix contains information on the current allocations
for
the
Texas
Instruments Professional Computer.
Current requirements for the
options and the printed wiring boards are listed below.
Total current available:
*
S Volt line 10.0 A
* 12 Volt line 4.5 A
* -5 Volt line 0.5 A
Table D-1 Current Allocations
Device Name
Motherboard CRT Controller RAM Expansion Graphics Diskette Drive KWinchester Drive Winchester Controller Communications Modem Speech
H OO MKEOGIMK
WONNKFEFODODNWO
12 Volt Line
0.1 0.0 ¢.0 0.0 1.2 1.8 0.0 0.1 0.1 0.1
-12 Volt Line
0.0 .0 .0 0.0 c.0 0.0 0.0 0.1 0.1 .1
bD-1/2
M el ._I-:
EERLMEC (lme - FRESl 2
:N| K A| i ¥ [
A e o~
setl
|y S
. -
[ 3
=
M
e
g4
by
=P
g¥1 ro prad PLt oy
=
L
)
_
oy
]
L
SHaEPCE- o,
.
At
RSelS e
RN
o T
B = gy e
|
4"
AR
oL'
1 -y
N
e +
y
!
TECHNICAL REFERENCE
ASYNCHRONOUS COMMUNICATIONS SAMPLE PROGRANM
OUT DX,AL LOOP INIA
; MHrite it to 8530 until ; all registers are programmed.
;
;
Now to initialize channel B,
'
MOV SI,OFFSET PARMTB ; sSI=Address of Chn B
MOV CX,PARMBS
g CX=Parameter table size.
MOV DX ,0E4H
; DX=Port 1,Channel B
INIB: LODS DS:BYTE PTR[SI]
; Get byte from
OUT DX,AL
; Write it until all registers
LOOP INIB
; are programmed.
RET
COMMEX ENDP SEJECT
parm table.
Command address. parameter table.
TECHNICAL REFERENCE
ASYNCHRONOUS COMMUNICATIONS SAMPLE PROGRAM
TRk
R AR R R R AR R AR R A A KRR R R AR AR R R KRR AR R R R AR KA KA R R AR KRR KR KRR R AR KR &
8
This area contains the initialization parameters for channels A and B
;
of port 1.
TR KR KRR KRR R R A KR AR ARk K AR AR AR K KRR R R AR R AR R AR KKK AR AR R KA R AR KA KRR KRRk kR
; ; Initialization parameters for channel A.
PARMTA
LABEL NEAR
DB 09
; Select WRS code.
DB 110000008
; Reset BS30.
DB 11
; Select WR1l code.
DB 010100108
; Rev clock=Baud rate generator.
; Xmt clock=Baud rate generator.
DB 14
; Select HR14.
DB 00000011B
; Enable baud rate generator.
DB 12
; Select HWR12.
DB 6
; Baud rate (low byte)= 9600 baud.
DB 13
; Select
HWR13.
D8 O
; Baud rate (high byte)= 9600 baud.
Da 1S5
; Select HWR1S.
DB O
; Disable external status interrupts.
DB 1 DB O
; Select WR1. ; Disable all other interrupts.
D8 3
; Select HWR3.
D8 010000018
; Rcv=7 bits of data + parity bait.
DB 4
; Select WR4.
DB 010001108
; x16 clock input,l stop bit,
; even parity enabled.
DB §° ; Select HRS.
DB 101010108
; Turn on DTR and RTS,
; Transmit enable, ; Xmt=7 bits of data + parity bit.
PARMAS EQU $-PARMTA
; ' Initialization parameters for channel B.
PARMTB DB 1S DB 00 DB 01 DB 00
PARMBS
LABEL NEAR ; Select WR1S. ; Disable external ; Select WR1. ; Disable all other
EQU $-PARMTB
status interrupts. interrupts.
SEJECT
TECHNICAL REFERENCE
ASYNCHRONOUS COMMUNICATIONS SAMPLE PROGRAM
Appendix E
ASYNCHRONOQUS COMMUNICATIONS SAMPLE PROGRAM
Control and Status signals
Listed below are the RS232-C
control
and
status
signals,
with
corresponding
8530
functions
wused to control and monitor them.
table is a summary of information available from
the
sync-async
board schematic.
the This comm
Table E-1 RS232-~C Control and Status signals
Rs232-C
Pin
Signal
Number
Data TermReaidy n(DTaR) l20
Request~to-Send (RTS)
4
Data Set Ready (DSR)
6
Data Carrier Detect (DCD)
8
Clear-To~Send (CTS)
s
Ring Indicator (RIX)
22
Speed Selector (CH)
11, 23
Speed Indicator (CI)
12
8530 Function
praa
RTSA
DCpB
DCDA
=
CTSA
CTSB
DTRB
SYNCSB
Accessed through
ChaAn, nWRSe, lBit
Channel A, WRS, Bit éhannel B, RRO, Bit Channel A, RRO, Bit Channel A, RRO, Bit Channel B, RRO, Bit Channel B, WRS, Bit Channel B, RRO, Bit
TECHNICAL REFERENCE
ASYNCHRONOUS COMMUNICATIONS SAMPLE PROGRAM
$ERRORPRINT SXREF PR A AR A AR A R ARk kR
Rk
R AR KR A AR A A AR R A AR KA A R R AR R A R Rk kA AR A AR AR N AR AR R R AR A KRk A
; TITLE
- COMMEX - Example of Async communications
; COMPUTER - 8088 ASSEMBLY LANGUAGE
; ABSTRACT -~ This a sample program showing typical initialization
B
of the TIPC communications board in asynchronous, polled mode.
PRk Ak R
R R AR kAR KRR R R R AR AR AR R AR R KRR AR R AR R AR A AR RN AR Rk kkhkkhk kAR XA KA X
NAME COMMEX
STITLE(COMMEX - ASYNC COMMUNICATIONS EXAMPLE)
SEJECT
TR
R A AR AR R AR RN R AR R AR R A AR R AR AR AR AR A AR R AR R A A A KA AR AR R A AR R KRR AR ARk kR kR
;
PUBLIC DEFINITIONS
AR AR AR AR R A A A R A R AR A A KA AR KA R A A AR KA A AR R AR R AR A A KRR A AR RR AR AR AR AR KRR
PUBLIC COMMEX
SEJECT R AR KA AR AR R R R A KRR Ak R R AR A KR AR R R R Ak AR AR ARk AR AR KRR KA AR X R Ak kR AR A AR AR kR AR KR
:
LOCAL CONSTANTS
-
PR A A A AR AR R R KRR AR KRR AR R AR KRR AR AR AR R AR R A KA R AR A AR AR R AR AR AR KK Akt k bk kA k kA
PI1CMDA EQU OE6H
; PORT 1, CHANNEL A COMMAND ADDRESS.
P1CMDB
EQU OE4H
; PORT 1, CHANNEL B8 COMMAND ADDRESS.
$SEJECT
E S
BIOCODE SEGMENT BYTE PUBLIC ASSUME CS:BIOCODE,DS:BIOCODE kA A AT I AR AR AR KRR
<
A
AR A AR AR R KRR KRR AR IR A AR A AR AR KRRk A AR Ak bk
; 8530 Initialization Routine
This routine initializes Port 1 according to a table of initialization
3
parameters stored in PARMST.
PARMST contains an image of the contents
;
of the various 8530 registers.
The contents of each register is pre-
i
ceeded by the number of the register itself.
This number is used to
4
select the appropriate register on the 8530.
; This
B B B
initialization programs the port for asynchronous, polled
operations where all interrupts from channel A (i.e., receive,
transmit and external status interrupts) and channel B (i.e., external
status interrupts) are disabled.
The software is to poll read
register RRO in channel A to determine when data has been received
and whether transmission of data has completed.
TRk K AR KRR AR AR R AR R Kk kKA AR A KRR AR KR KA R R kAR KKK kAR Rk AR AR A RR KR KRR
COMMEX PROC NEAR
'
;
First, the 8530 channel A is initialized.
AR A RAAR
KRR
R KKK
MOV MOV
MOV INIA:
SI,OFFSET PARMTA ; SI=Address of Chn A
DX ,0E6H
; DX=Port 1,Channel A Command
CX,PARMAS
e CX=Parameter table size.
LODS DS:BYTE PTR[SI]
; Get byte from
parm table. address.
parameter table.
TECHNICAL REFERENCE
ASYNCHRONOUS COMMUNICATIONS SAMPLE PROGRAM
R
R R R KA AR R R R R R A AR AR AR R R Kk
8530 Receive Character Routine
kR R Rk A AR R AR Rk R R R KA AR AR R ARk k%
This routine is called to read a single received character from the
; 8530 receive receive fifo.
If no character is available in the fifo,
i this routine waits until a character is received before returning to
o the caller.
TR KRR KA A kAR R A kR R R R R R R Rk kAR R AR R AR R AR AR R KRR AR AR KRR A AR A ARk
READCH PROC NEAR
MOV DX,0E6H
; DX=Port 1, Chn A, command address,
TRYRAG: IN AL,DX
; Read RRO contents.
AND AL,000000018B
,Q: Any characters
JZ TRYRAG
B No, try again.
in rcv fifo ?
MOV DX ,0E7H
e Yes, DX=data port address.
IN AL,DX
; AL=character received.
RET
READCH ENDP
SEJECT
kkkkk kK2
TECHNRICAL REFERENCE
ASYNCHRONOUS COMMUNICATIONS SAMPLE PROGRAM
KRR IR KRR KRR AR AR R R KR AR KRR AR AR AR R A A R AR AR A KRR AR A AR AR R AR R R KRR AA RN AR AR KAk 8530 Transmit Character Routine
This routine is called to write & single character (in AL register) to
the 8530 for transmission.
I£ a character is currently being transmitted
this routine waits until transmission of that character completes before
attempting to transmit the next character.
AR AR AR AR KRR KRR A AR KRR AR AR KR KA AR AR AR AR R kAR A KA AR kAR
fRITEC PROC NEAR
MOV DX ,0E6H
; DX=Port 1, Chn A, command address.
RYXAG: IN AL,DX
; Read RRO contents.
AND AL,00000100B
;Q: Character being transmitted ?
JZ TRYXAG
8 Yes, try again.
MOV DX ,0E7H
3 No, DX=data port address.
OUT DX,AL
; AL=character received.
RET
fRITEC ENDP
V\IOCODE ENDS
R ARk
ARk
R kAR AR R R KA KAk AKX
TECHNICAL REFERENCE
MODEM SAMPLE ROUTINES:
Appendix F MODEM SAMPLE ROUTINES
RCNTL
ARk AR A R R R AR R R R R ARk A AR AR KRR R RN R AR AR A kAR R AR AR RR AR AR
;
RCNTL - This subroutine determines whether a modem is
installed in port 1 and if so, activates the
'
RCNTL signal to initiate the modem Control Mode.
SRRk kA Rk kR AR R AR AR AR AR AR R R AR AR KRR AR AR AR AR AR AR AR Rk k
RCNTL PROC
NEAR
MOV
DX,00E4H
; DX = PORT 1 CHANNEL B ADDRESS.
MoV
AL,0S
; HWRS SELECT.
ouT
DX, AL
; SELECT REGISTER S.
MOV
AL,02
; TURN ON RCNTL (RTS IN CHANNEL B).
ouT
DX, AL
; ; LOOP:
RCNTL
NOHW TO DETERMINE IF
MOV MOV ouT IN TEST JZ RET ENDP
DX ,00E6H AL, 10H DX, AL AL, DX AL,000100008B LoOoOP
MODEM IS INSTALLED.
; DX = PORT 1 CHANNEL A ADDRESS.
; RESET EXTERNAL STATUS INTERRUPTS.
;
<
; READ RRO.
.
;Q: IS ACNTL (SYNCA) ACTIVE ?
; NO, CONTINUE TO LOOK FOR ACNTL.
; YES, RETURN TO CALLER IN CONTROL
MODE.
TECHNICAL REFERENCE
MODEM SAMPLE ROUTINES
DIAGST
R AR AR R KRR R AR KRR R AR R R AR R KRR AR KRR R AR AR AR AR AR AR AR
; DIAGST - This routine requests the diagnostics status from
the modem and returns the result in register AL.
It is assumed that the Zilog 8530 has been previously initialized and that the modem has been placed in
;
Control Mode.
TR KRR R R R AR AR KRR RN KRR AR AR R AR A kAR Rk kA kkkk kA A XX AL L
DIAGST
PROC
NEAR
MoV
DX ,00E7H
; DX = PORT 1, CHANNEL A DATA PORT ADDRESS.
MOV
AL,'D'
ouT
DX,AL
; AL = DIAGNOSTIC COMMAND CODE. REQUEST MODEM DIAGNOSTICS STATUS.
LOOP:
MOV IN TEST
DX ,00E6H AL, DX AL,00000001B
DX =PORT 1, CHANNEL A COMMAND ADDRESS. : READ CHANNEL A'S RRO. ;Q: HAS A CHARACTER ARRIVED FROM MODEM ?
JZ
LOOP
MOV
DX ,00E7H
IN
AL, DX
; NO, WAIT FOR COMMAND RESPONSE. ¢ YES, BX = PORT 1 DATA PORT ADDRESS.
READ DATA FROM RCV FIFO.
DIAGST
RET ENDP
; RETURN WITH STATUS IN AL.
TECHNICAL RE FERENCE
MODEM SAMPLE ROUTINES
DIALER
PR
R AR
R A AR R KRR R R R AR AR R AR AR AN AR R AR KRR R AR ARk kX
; DIALER - This routine dials a typical phone number. It
does not monitor the progress of the call and
it assumes the Zilog 8530 has been previously
initialized and that the modem has been placed
in Control Mode.
.
.
R .
R
DIALER
The phone number to be dialed is contained in
a buffer (phonum) and is terminated by a null,. KRR R R KRR R R kAR AR AR R AR AR R A KAk AR KRR KRR KRR K
PROC
NEAR
MoV
DX,00E7H
; DX = PORT 1, CHANNEL A DATA
MoV
DI ,OFFSET PHONUM ; DI=ADDRESS OF PHONE NUMBER
MOV
AL,'T*
;Use T for touch tone
ouT
DX, AL
;Transmit - command to modem
PORT ADDRES: BUFFER.
Nest send the strip of telephone numbers
LOOP:
' SENDPT:
' '
¢ LOOP1L:
DIALER
MoV
AL,{DI}
XOR
AL, AL
JoEuT
SDXE,NDAPLT
INC
DI
IMP
LOOP
MOV
AL,'X'
ouT
DX, AL
; GET PHONE NUMBER DIGIT.
;Q: END OF PHONE NUMBER ?
; YES, SEND PHONE NUMBER TERMINATOR.
; NO, SEND DIGIT TO MODENM.
; POINT TO NEXT DIGIT.
; CONTINUE IN LOOP.
)
; AL = PHONE NUMBER TERMINATOR COMMAND. ; SEND TO MODEM.
NOW TO WAIT FOR THE DIAL COMMAND COMPLETION.
AL RETURNS THE STATUS OF THE DJIAL COMMAND.
MOV
DX ,00E6H
; DX =PORT 1, CHANNEL A COMMAND ADDRESS.
IN
AL,DX
; READ CHANNEL A'S RRO.
TEST
AL,00000001B
;Q: HAS A CHARACTER ARRIVED FROM MODEM ?
JZ
LOOP1
;: NO, WAIT FOR COMMAND RESPONSE.
MOV
DX ,00E7H
; YES, DX = PORT 1 DATA PORT ADDRESS.
IN
AL, DX
; READ DATA FROM RCV FIFO.
RET
ENDP
F-3/4
TECHNICAL REFERENCE
BOOT ROUTINE AND SAMPLE ASSEMBLY CODE
Appendix G BOOT ROUTINE AND SAMPLE ASSEMBLY CODE
Appendix G gives a sample source program that
could
bdbe in
the boot
sector.
This example is excerpted from the MS-DOS V1.1i0 boot sector.
e me e ne ne we we
TECHNICAL REFERENCE
=
3 E
L
BOOT ROUTINE AND SAMPLE ASSEMBLY CODE
SRR
R R R KRR R R R R AR R R R R R A AR AR R AR AR R R AR AR R R R AR R R AR AR R AN R R k&
TITLE
- BOOT -~
SAMPLE BOOT ROUTINE FOR THE TI PROFESSIONAL COMPUTER
ABSTRACT ~ This routine is responsible for loading the system files
from the disk.
This routine resides in the 'boot®' sector
;t***ii**l(ot*cr*aa*ct*ki*o*n*0 **OstCeOctGt*oO*rH**xb1)oto*t:oft*c*otdthee***di:ni*skrt*he*w*h*is*cyh*sttteim*s**RltOoxMatd*eadrn*d ta*ttth*ea*nb*s*oe*lxtuettc*eu*tre*d.*********
NAME
BOOT
TITLE
TIPC BOOT LOGIC)
PAGE AR R ARk Ak Rk
o PR KRR KRR Rk kR
;
VERS
EQU
o
REV
- EQU
o
R kAR AR R kA AR K K AR AR KKk kAR R AR R R KRR AR KA KR KRR AR AR R KRR E R K& LOCAL CONSTANTS kKR kAR AR AR R R A R KA R R A kAR A A AR R AR R AR AR AR AR AR AR R AR AR kR
; Current version of BOOT logic . Revision level
°R
EqQu
0DH
&
(o]
OAH
+ WINCHESTER disk DIT (Disk ;
JITSTRC STRUC
JITDIR
DD
0
JITSEC
DW
S12
JITTRK
D8
17
JITCYL
DB
4
JITDSK DB
153
)
JITERR
DB
e L
JITWRC
DW -~
64
JITPRC
DW
64
JITSTP
DB
JITBUR
DB
DKW
100000008 i1 0000
JITSTRC ENDS
PAGE
Interface Table) equates ; Disk Interface Routine vector (dword) ; Sector size in bytes (word) ; Track size in sectors (byte) ; Cylinder size in tracks (byte) ; Disk size in cylinders (BYTE) ; Maximum number of error-retries ; reduced write current ; Write pre-comp threshold cylinder i Step option ; Error burst length ; reserved for expansion
ROM BIOS interface vectors:
ELINT
EQU
RTINT
EQU
EYINT
EQU
RTINT
EQU
AMINT
EQU
SKINT
EQU
LKINT
EQU
ONINT
EQU
48H"'
49H
4AH
4BH
4CH
.
4DH
:
4EH
4FH
; System beeper I/0 and general ROM interface ; Screen /0 ; Keyboard [/0 ; Parallel port I/0 ; Analog Input/Clock I/0 ; Floppy disk 1/0 ; Time-of-day clock I/0 ;: System configuration
TECHNICAL REFERENCE
BOOT ROUTINE AND SAMPLE ASeSEMBLeY NTRGYeO1DS E
;
v
XA R
e A
[ R
T eI TI L I
X O I X T2 T O L
L X RR L
X XA
3
FIXED ROM DATA AREA - (absolute offsets from absolute 0)
2 T Aot
;
These equations define the ROM communications area, containing. data;.
!
3
that must be accessed by both the ROM and user/appl;catipnflproqrams.
This data is accessed from the ''user' program by setting DS . 5.0,
5
DSADDR EQU
4%60H
; (WORD) pointer to DS for System ROM,(RQOMDAT)
DSSIZR
EQU
DSADDC
EQU
4%60H+2 4%*61H
; (WORD) ; (WORD)
size of DS for System ROM (RQ&DAT) pointer to DS for ROM..at BOMGOD: 0000
DSSIZ0
EQU
4*%*61H+2
; (WORD) size of DS for ROM at ROHCQQ;QOOO
DSADD2
EQU
4%62H
; (WORD) pointer to DS for ROM at ROMCQD:20Q0
DSS1Z2
EQU
DSADD4 EQU
4%x62H+2
4%63H
; (HORD)
; (WORD)
size of DS for ROM at ROMCOD:2000
pointer to DS for ROM at ROMCOD:4000
DSS1IZ4
EQU
4%*63H+2
; (HORD) size of DS for ROM at ROMCOD:4000
DSADDE6
EQU
4%x64H
; (WORD) pointer to DS for ROM at RO&QQp:GOOO
DSsSI1Z6
EQU
4%64H+2
; (HORD) size of DS for ROM atfROHCODtfiOOO
:
DSADD8
EQU
4%6SH
; (WORD) pointer to BS for ROM at ROMCOD:8000
DsSsi1zs8
EQU
4%6SH+2
MEMSIZ
EQU
4*66H
; DISK TDSR e OPERATIOe N CODES
;
DKRSET EQU
o
; (WORD) size of DS for ROM ai ROMCOD 8000
:
; (HORD) memory size (number of 16-byte blocks)
R
ee e
e L T = t o eay
¥
; Reset
disk
system,
. drive parms must..be preset
DKSTAT
EQU
1
DKREAD
EQU
2
DKWRIT
EQU
3
DKVERF EQU
4
; Get disk status in (al)
¢
; Read sectors into memory
oD
; Hrite memory to disk seckofi;
; Verify crc on disk sectors
»
a-
-
i
2
410
84 .
DKVRFY
EQU
6
DKSSTA
EQU
7
DKFSET EQU
8
DKXSET EQU
8
DKRDIT EQU
10
DKKMOT
EQU
11
DKBADC
EQU
12
; Verify memory against disk.;;ptors
G
YRS
; Get disk status for pre-retry. (if any)
. -
; Set UNIT & standard DIT for A drive
e
; Set UNIT & DIT address for a drive
.
- -
; Return DIT address for driyve
N ot
; Turn off Floppy Disk Motors ,
O
; 0ld >= this is a bad command..
o
;***t********t********t*t**********************k*********t***k******g*}t***t
)
e B
8
10 segment - defines load address and entry point for BIOS
I0
SEGMENT AT 40H
ASSUME
Cs:IO
; absolute location 400H
I0osyYs IosYs
;
Io
CODE
PROC ENDP
ENDS
RSAECGEMENT ASSUME
FAR AT 0000
CS:CODE,
; 10.8YS loaded here (40:000095:
jaE &
GA;
20D
ot
HT
; Absolute location
DS:CODE, SS:CODE, ES:CODE
0000H
:
Jog s
10E
Ues
104
ey
foi
yps Thiea
V6
1
e
NRE
TECHRICAL REFERENCE
BOOT ROUTINE AND SAMPLE ASSEMBLY CODE
TR
AR R R AR R R R R AR KRR R KRR AR AR AR R A AR AR R
R A AR A AR AR R AR RRRRR AR A AR T h A b
5
Data area for ROM definitions
Ak R R AR R R Ak Rk Ak kAR AR AR Ak kA AR Ak Ak AR R A AR R R AR A AR KRR KRR AR AR KRR KR KA Kk &
`ORG OLDRMD ~ LABEL
400H HORD
; Initial location of ROM data area
1; 051z'2 `EQU ORG
7 1200H
; Number of sectors in I0.SYS ; (OLDRMD+7%512)
ROMDAT
LABEL
ORG
BYTE
1200H+13CH
; Location of rom data area
MOVDST EQU
TR AR KRR KRR AR
; SRR KRR Rk
(ROKDAT-OLDRMD/1)6
R AR AR AN R AR AR A A R AR AR A R A R AR
MODULE ENTRY kR kAR kR R AR R AR R A AR R AR
R A AR RN R kR A
POINT K AR AR AR R AR
A kR Ak
A kAR
A AR A AR
R AR AR
KRR R KA AR AR AR
KA KRR R AR
AR
A kAR
AR AR
KRR
BOOT ;
ORG
PROC JIMP
O0CO00H
FAR - - 'BOOTST
LT
e ey
B
e R e
ORG
e iy
OCOO03H
¢
3
File access table -
; Entry point for boot logic
gLy
HEADER
DATA AREA
e
; Always
U
R
start here
e e se e
Shows the loader where to find 10.SYS
S
2 S Sl isls S s S
IOSEC IOTRK IOHEADTM
7
i
3
.
DSKTYP
D8
8
DB
0
BB ""¢ "¢g "
:
: ¥ side 40 track load sector ; 1 side 40 track load track ; 1 side 40 track load head
THE-FOLLOWINBGYT'E INDIC THA E TDREIVE
MUST TYPE
BE SET UP FOR WHICH
BY THE FORMAT COMMAND TO THE DISK IS FORMATTED.
TFHLEOP"PPYERMBIISSSKTITBYLPEE. VALUES ARE 0-3 WHICH CORRESPOND
WITH THE
DB e 00400 E s
; Disk formatted type
QOODRV D;_ o 091_
;.. iNcHESTER DIT
; Storage for boot drive
iINDIT nf&§¥R¢_<>' rte gl
; 18 BYTES LONG
'
=BT ma RETE
eyt
AR
;.
SIGNON. DB.. .
-GR,LF, 'BOOT. V'
DB
VERS/10+'0',',.V"E'RS MOD 10+'0' ,REV+'0"
DB
' (ec) 1983 Texas Instruments, Inc.',0
number
PR AR
P
PAGE
o
.
KA R AR AR KRR KR KRR R A A AR
NCLITHES
LHLEEL
i
v4 i e rapnooari
A AR AR AR A KA KRR R AR A KRR AR AR AR AR AR AR A AR KA KKK
oisy = xQC"23
TECHNICAL REFERENCE
ITATYHAEORT BOOT ROUTINE AND SAMPLE ASSEMBLY CODE
> bw e
£
;
DISK
BOOT LOGIC address 400H) 1200H). This found, it can same manner as
ROMDAT
is mo ved
from
its
initial
-
AVt
AN
locatxon (absolute
to its worki ng location under MSDOS (abs oLute,addral
code is call ed (FAR) by the ROM.
If an error is
:
perform a RE Turn to let the ROM handle it in the,
the other boot-time errors.
X 8
INPUT:
BL = Floppy drive from which to stack is set up below this code
attempt the by the ROM
boot
8; 0OTST: MOV
SI,OFFSET SIGNON; Signon the boot sector
CALL
MSG
TR
- s Al %
NiLdEeu
5
;
First, move the ROM data area out of the way.
BOO2:
PUSH
MOV MOV MOV MOV MOV MOV OR JINZ suUB JMP
ES
AX,Cs DS ,AX ES ,AX BOODRYV, BL BX,DSADDS AX,[8Xx]) AX,AX BOO4 BX, 4 BOO2
; Save the ROM's ES
: Note that ¢S = CODE = COOOH)
; DS = CS = CODE = 00QOOH
; ES = CS = CODE = 0000H
-
; Save boot drive
£
e
; Point to last possible
; Get data pointer
:Q:
Data area in use?
rom data area £
; ¥: Jump and calc data length
o
Lp
; N: Point to next data area polnter
;
And check it
r
3
2l
point
BOO4:
MOV
SHL
ADD
sSuB
MOV
MOV
MOV
MOV ADD
CL,4 AX,CL AX,[BXx+2] AX,offset CX,Ax SI,offset DI,offset BP,CX BP,DI
;
` ¢ OLDRMD; ; OLDRMD; ROMDAT; ;
1
Convert dsaddX pointer to absolute -addre
And add Subtract
in the last data area the original locaflon
length
Results in total length to.move-
DS:SI = source for the. mnve
.
ES:DI = destination for the move
Get length + ROMDAT
of move into BP = lowest avaflable
& memory
MoV CHP
JE
:
ADD ADD
DEC DEC
STD
CLI REP
CLD MoV BOOS: CMP
DX,Ds:word DX,(offset BOO7 s1,CXx DI,cx
s DI
HOVSB BX,DSADDR
ptr DSADDR ROMDAT/16)
; Pick up the ROMDAT pointer
; B
Q: Has the (True if
move already taken plac ROM is retry:ng the boo
B
g
Y:
N:
Then
Then
skip the move
do the `mové'
thls
txme
; ;
; i
Do the move in reverse in case ROM
area is larger
O relative. O relative: [
khan
move`&ength
2 £a
o
+; Protect the move
ansa
;:: Do the -move -1
g Av
;:; RESET STRING DIRECTION
i::; Set up the rest - start with DSA
vord ptr [BX]},0000
;7: Q! ROM'g DSADDx = zero ?
G-S
TEGHNICAL REFERENCE
BOOT ROUTINE AND SAMPLE ASSEMBLY CODE
BOO6 : e
BOO7:
e ADD
CHMP I E ADD JIMP
STI
BOOSG word ptr [BX],MOVDST
BX,DSADDS8 BOO7 BX, 4 SHORT BOOS
H
N: Not installed, go to next one
;;:;
Y: Then adjust it
e
::: Q: Are we all done ?
XT
Y: Continue with boot
ol
N: Point to the next ROM's DSADDx
;:, and loop for next one
;:: Shields down
]
HERE ROMDAT HAS BEEN MOVED AND BP CONTAINS LOWEST AVAILABLE MEM ADDRESS
;
TELL DSR ABOUT THIS DISK TYPE
;
MOV
DL, BOODRV
;: Drive number
MOV
AL, DSKTYP
MOV
AH,DKFSET
: Get ; Set
the disk formatted type the floppy DIT opcode
INT
DSKINT
; Go do it.
)
Set up the WINCHESTER if it is installed.
. ©
100T20:
MOV OR JZ
PUSH
MOV MOV MOV CALL Pop
AX,DS:WORD PTR DSADD4 AX,AX
BOOT20
ES
-
ES,AX
SI,OFFSET WINDIT+4 AH,O
., (ES:DWORD ES
PTR
0000
;check for winchester
:Q:; winchester installed?
; N; jump
: Y, save Ds
;get winchester ROM ES
;get pointer to new DIT
;copy and «set new winchester
;call the ;retrieve
winchester
ES
"
ROM
DIT
Load I10.SYS first - 7 sectors (3.SK) loaded, have to
If a disk error occurs,
it
returns to the caller the routine DKBOOT in
for the
error handling System ROM) .
(the
caller
miss the ROM data is assumed to be
area
MoV MOV MOV Hov
KoV INT JB MOV MOV JMP
register
JBOOT: POP
BX,offset OLDRMD CX,word ptr IOSEC DH, IOHEAD DL, BOODRYV
AX,DKREAD*256+I0SIZ DSKINT NOBOOT BL,DL AX,BP 108Ys
AH contains an error code
Transfer Starting
.. and
offset (ES already set) at proper track and sector head
From boot disk.
7 sectors
Select disk read function
Disk DSR
If error, die
Tell BIOS init about the boot drive
And, the lowest available address
Else, go to BIOS init code
to be reported by the ROM
ES
; Restore original ES before ROM gets at it
G-6
TECHNICAL REFERENCE
BOOT ROUTINE AND SAMPLE ASSEMBLY 'CODE
BOOT
MOV RET ENDP
DS ,DS:word ptr DSADDR
; And point DS at the nev flOHDAT
FAR Return to DKBOOT
v
PAGE
S
**itk*t******************k*******k*****************t***************
3
MSG - Output string of characters in the current ¢S to" the CRT
The string should be terminated with a zero byte.
.
INPU T:
SI = offset of string in current Cs
B
OUTP uT: (screen)
khkhkkkk:
;
USED:
AX,SI
:
STAC K:
MSGLl:
MSG
CODLEN CODFIL
` CODE
21 ] DH
ENDS END
CS:byte ptr [sI];
AL, AL
;
MSG1
]
AH,CRTHTY
CRTINT
;
HMSGO
:
$-800T
8
$12-CODLEN-4
:
CODFIL DUP (0) ;
TR
:
0000H
Get the char
:
AL T
Q: Last char?
St
N: Jump and print ft. -
¥: *%x RETURN #%%
Else print it
S0l
And loop
T R
o
LENGTH OF THE CODE
STPOATCAEL SFPIALCLEER AVAIL FOR- coneo
*
g
Disk Boot
identifier
SiF
sector CRC (Calculaf!d
=
i X?t iy TV.
T RS S
VoK
5C
ik `\o',"2
A%
by J@EY`2u(G}stylility)<
G~-7
5D wJeMizRs Hakncs
C
TECHRICAL REFERENCE
BOOT ROUTINE AND SAMPLE ASSEMBLY CODE
The following pages show a sample assembly code. ., @& 2048 byte ROM at address F400:6000.
This code will set up
DATASIZ EQU~
30H
;ROMDS ;ROMDS ;ROMDS
ROMDS :ROMDS
EQU EQU EQU
EQU EQU
184H 188H 18CH
'192H 196H
CODE
SEGMENT AT OF400H
ASSUME CS:CODE
ORG
6000H
;length of required data area ;can be zero but must be multiple of 16
;for ROM at F400:0000 ;for ROM at F400:2000
ifor ROM at F400:4000 ;for ROM at F400:6000
;for ROM at F400:8000 (main board)
; ROM
'
MSGBEG
HEADER DH DHW DB DB DB
DB MSGLEN EQU
2048 ENTRY MSGLEN ODH, OAH 'V1.23 XMPROM, example ROM ODH, OAH $-MSGBEG
;ROM size
;entry point address
imessage length
;carriage iversion,
return, line feed 6-character name,
;
message
;carriage return, line feed
;: ENTRY POINT
3
ENTRY
PUSH PUSH PUSH
PUSH
FOR POWERUP
<
BX DX SI Ds
CODE
;save : ; g
important
registers
; ALLOCATE OPTION ROM DATA
'
XOR
AX,AX
MOV
DS ,AX
MOV
BX,180H
AREA
MOV MOV
SHL
ENT0O:
ADD
ABD CMP
JINZ SHR MoV MOV
AX,[8X) CL,4
AX,CL AX,[BX+2] BX,4 BX,ROMDS ENTGCO AX,CL [BX],AX [BX+2],DATASIZ
IN RAM
;setup segment to point
3
to vector area
;check for RAM in use starting ; with system area
;get segment address ;convert to absolute ;
for ROM address
;add in length of segment
;point to next ROMS RAM seg pointer
iQ:
is this the pointer for my ROM?
; N: continue adding up RAM usage
; Y: convert address to segment
9
store my segment address
:
and the segment length
: SET UP MY i EACH TIME
'
DS AS REQUIRED TO MY THIS ROM IS CALLED.
DATA
AREA.
THIS CAN BE DONE
TECHNICAL REFERENCE
BOOT ROUTINE AND SAMPLE ASSEMBLY CODE
IVLINSTIT
MOV DS,CS: (WORD PTR ROMDS+0COOOH)
Tt RS T
"
;additional init coed as réguirad
POP
bs
POP
st
POP
DX
POP
BX
;retrieve
o
B ;
the calling
ROMS regs.
o fig i
.. .-
ORG DW
ENDS END
6000H+2048-2 ROMCRC
;address for the fiQfiECRC
3
Triwy
.
é-98/10
TECHNICAL REFERENCE
SAMPLE INTERRUPT SERVICE ROUTINE
Appendix H
SAMPLE INTERRUPT SERVICE ROUTINE
An ISR example, with the appropriate routines to install and remove it,
follows.
The source of the common interrupt exit routine and the code
to count the number of outstanding interrupts (INTCTR) are also given.
Using this code is not mandatory, but is recommended to maintain future
compatibility.
H-1
TRSHNISAY, REFRBENGE.
SAMPLE INTERRUPT SERVICE ROUTINE
. ~
;
Exit logic
POP
ES
"POP
BP
" _PpOoPp
SI DI
POP
bXx
pop
cX
poP
BX
Restore environment
"., "AMoChouLToIm
% Nv.dom L AiXgHAXAL.
]
;. Disable interrupts Reset 8259 interrupt
; AX = 0000
controller
3 "xPDMoOwET QPCvY
=ri~.'pDSs:
,Ax
(byfé
ptr
Point to vector area INTCTR) ; Decrement interrupt
: | §A5X .Cs:STKSAV+2
; Restore original SsS:SP
counter
T, sp ,CS : srxg@y
gy E2 T2: BT
3 P
da%
r iy
Lk ; Restore original DS
. ** INTERRUPT RETURN +*x
INTSRV ENDP =
-
i
TECHNICAL REFERENCE Example 3
SAMPLE INTQR&UPT SERVICAnEiuLRaOTUYTINE
I;: NTINS
PPRUOSCH
ANXEAR
PUSH
BX
o
- i 23&
gc , = V]
PUSH MOV
DS CS:DATSEG,DS = '
'; Set up CS-relative ;" the local DS
poinferi
8
necessary b§¢°";° the g nly
;
;
5 &l;iF'
`1rt efeisrenicnevoktehde-
é? 19
has\ihen the Cfi;
o
Patch the interrupt vector to point to the Interrupt Service
i
Routine, saving the original vector. Tfixs ilrustrates the
B
`brute force' method of settlng and gef%xng Vecfors.
o
8088 Operating Systems (e `'g. MS-DOS) have systefi call
B
accomplish this feat.
THeir use is preferable, becauss `some
s
Operating Systems attempt to arbitrate vector usage.
XOR
AX,AX
MOV
Ds ,AX
CLI
; Clear AX
; Ds <-- Q0000 ; Protect the
vector
operation
N
Pick up original vector
i'
MOV
AX,DS:(word ptr (INTNUM*4))
MOV
BX,DS:(word ptr (INTNUMXx4+2))
4
8
Save original vector in local save area
MOV
CS:VECSAV,AX
MOV
CS:VECSAV+2,BX
8
Install vector to Interrupt Service Routine
INTINS
MOV MOV STI POP POP
POP
RET ENDP
DS:(word ptr (INTNUMX4)),o0ffset INTSRV DS:(word ptr (INTNUM*4+2)),CS
; Interrupts OK again Ds BX
AX
; k% RETURN #*x+%
S ve ns
. v we
TECHNICAL REFERENCE
SAMPLE INTERRUPT SERVICE ROUTIKE
Exdipre &°°7 7
e
e B
e
T 1-fir---9--- ----- R e
B
Interrupt Service Routine REMoval routine
SO0
5 -
fifififirfifl""'L ------------ e e e Ss
s e
bedie 'Pbsy e ANXEYAR
22
ng Ty
,n:;.-7 5 SSU`flx-
SN
3
i
uUs
XOR
AX,AX
; Clear AX
MOV
DS ,AX
; DS <-~ 0000
CLI iEas 2
i
i
; Protect the vector operation
Get original vector from local save;
2 fia
b
MoV' Hov') fa
1QBXX3,CCASSL::yVVIECCSS%AVVe`+32A »
Byt
R p
Restore original -vector'
area .
S i
INTREM
INTSEG
MOV, DS :¢vord BEr "( INTNUMY)4, )AX
MOV
DS:(word ptr (INTNUMx4+2)),BX
STI
; Interrupts OK again
POP
Ds
;
PPOOPP
BX AX
P
RET
; *x% RETURN %%t
ENDP
TTrae s
e
z
1
Jmv e
L
ENRS . gqinc>
b' "3a
END
int s vemann el
nad
B i
Y.
(&
o gt nal
3
b5 ey
T
e oae Buen
Mot
)
>
12
sr AnpiS pkaooetil° woox RERTER Sos
i
¥
4
:
1
'
H-6
TECHNICAL REFERENCE
SAMPLE INTERRUPT SERVICE RQUTINE
This is the source for the comnmon interrupt exit routiine as"?3¥. e}):is
in ROM.
Any other common: exit routine installed-her@`Vill erfo;mflanu
identical function.
The user should use this
exit 4%
the xnutalled
interrupt service routine will be running concurrently'{ith a zal time
Operating
System
(for instance, during the exacutionkot an?
the TI
communication packages).
Example S
" AR R
¥zfi,.A2Al
Ve o e
4
Common Interrupt Exit logic
o i
o KB
;
= mend 103 -
e
3
INPUT:
ES:BX = SS:SP of the- interrupted code
H
o
Interrupt stack contains saved ES,BX,AX. (ES''at top
8
of stack)
CaVaLDIVIED.YE
2
5
Stack N
of S inN terrupted
codeecontazns
saved g oo
DS gkmeeEILL
ey IR E
ROHDAT
SEGMENT BYTE PUBLIC
"
ROMDAT
EXTRN EXTRN
ENDS
IXSSSV:HORD IXSPSVY:RORD
gl
1
Al (e e
o Temporary stpgfi_pobnror saveY;:
S B Lfl
AR U
s RS
`:;
& `( 4`..`
i
.'.'».»,-;
& R
2%
-
ROMCOD
I: NTXIT
SEGMENT ASSUME
PROC
BYTE PUSBLIC CS:ROMCOD, DS:ROMDAT
FAR
TSR
X
'Oi
LA
"f;
RLte
e :
CLI
oMuOTV
A1L8,H,2A0LH
; Disable interrupts
o33
C g
; Reset 8255 interrupt4 controllé2r)-
DEC_
CS:(byte ptr INTCTR+0COOOH) ; Decrement interrupt
d
counter (remember, this is in
:
ROM, so access to the vector
o
area is CS-relative)
MOV
DS ,Cs:(word ptr DSADDR+CCOOOH) ; Get ROM's DS
MOV
IXsSssV,Es
Save SS,SP of original code
MOV
IXspsv,BX
POP
ES
; Restore commonly used registers
POP
BX
B
from interrupt stack
POP
AX
MOV
8S,I1Xsssv
; Restore original Ss,sp
MOV
SP,IXSPSV
POP
Ds
; Restore DS from original stack
INTXIT
IRET ENDP
; *k% INTERRUPT RETURN #%#%
; ROMCOD
ENDS
END
B
H-7/8
TECHNICAL REFERENCE
INDEX
A
abort timer: answer mode
originate mode
address:
counter
it
decode
.
o
.
latch
5
s
lines
o
o
B
multiplexer switch
MUX switch generat
register
.
valid bit
o
s
address, logical
addressing.
o
.
AIOHWC .
s
g
.
ALB
s
o
s
.
ALE
P
.
alphanumeric:
CRT
decode
-
graphics.
e
o
alternate character
analog loopback
arbitration
s
assigning alternate attribute:
bits.
hardware.
interaction
latch
logic
attributes.
ion
set track
bit:
correlations definitions position
shift blanking
5 display
blink
o
.
blinking
block
buffer.
buffered-step burst length
bytes, byte:
device
contro
command completion
error status
1 block status
Index-1
Cve g
INDEX
.3-29, .3~431, «2-42,
TECHNICAL REFERENCE
R
1/0 decoding
.
.
o
.
1/C ports .
5
x
e
.
I1/0 wait states
2
=
o
K
&;xboard:
: mapping
.
queueing
.
system .
a
L
.
.
.
.
.
.
.
o
J
logical address, HIGH, MIDDLE,
logic::
expansion memory control.
. memory refresh
.
g
o
leng space received .2..:0:"
lgopback
.
o
o
.
.
loss of carrier
.
.
.
LOW: logical address
.
.
¥
<
M. -
mask, interrupt
=
.
o
memory adddressing.
%
%
memory control:
`logice
o
o
5
S
state machine
a
o
o
state machine, expansion,
memory refresh logic
.
0
MPFM
.
.
S
.
MIDDLE logical address.
.
miscellaneous error codes .
modem:
responses
s
&
o
:
software
0
.
.
.
time-outs
.
.
modified frequency modulatxon
motherboard: `memory .
o
3
memory addressing
.
.
MRDC- .
5
.
.
.
MREAD~ .
g
.
:
mu)tiplexer svitch
.
3§
multiplexers
.
.-
%
%
MHRITE~-
5
o
x
`
.
N
NMI-
a
&
.
no' response
3
.
C
&
nonmaskable interrupt .
:
non---blinking
Index-6
PyINDEX
2-15 S Jd-35, `3-39
2-21
rea
:
o
tr
'
N
1
w LW W NWWNN
1
.
L2-31,
.
2-30,
T
'
3-23 3-22
2-20 2-20 2-58 2-58 2-22 3-32 2-58
2-58 3-22
2-58
1o2-43
N W
b WWN
an o w
AaNN W
N o
TE&HN ICAL REFERENCE
TiLhanoEy
'
INDEX
numeric. goprocessor
-
5 .»
. :i4
.
N
S Xy
2T
Y
odd sum
a
o
g
o
5
on~board EPROM/ROM.
3
¢
operating system
.
5
s
output port
S
5
5
4
OSC clock .
.
.
-
.
5 e . S .
.
4
e
)
.
.,
S
S
£
.
e
5
.
.
.
0 o & e .
.
2=22
. ihrat@--as
S
34-2
W
~ig=-40
il 258
P
g
palette
5
.
.
2
I
palette number.
d
o
3
5
parallel printer port .
g
R
parity generation and checking.
parity
PCLKIN
generation
.
.
and
g
checking,
-
,
A
phase-locked loop .
pixel .
A
,
h
" Y
" .
g .
pixel addressin
o
.
5
T
pixels. plane .
a .
o .
0 .
a .
5 .
& .
poll for controller request
.
port:
data output .
b
a
5
2
input data
o
o
o
g
a
reget
s
b
o
o
&
4
precompensation
.
5
.
&
print screen
&
o
5
.
o
processor-clock
d
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SECTOR BUFFER
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TECHNICAL REFERENCE
register assignments
o
register, controller status
remote digital loopback
request controller error sense
"REQUEST SENSE STATUS command
reset:
detection circuit
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line.
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resolution.
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scan rate .
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screen display.
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scrok¥ling .
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sector buffer .
s
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sector .interleaving -
SEEK command .
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16 3
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séisé, controller error
separator
e
serval communicatxons d
ser;al/parallel data conversion
software:
commands.
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speaker
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state machine .
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status register
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system ROM interface
system timers and speaker
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TEST DRIVE READY
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TEST DRIVE READY command
Index-8
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3-39 3-40 3~23 4-72 3-46
2-12 2~-58 3-40 2-41 2-42 2-5S5 2-43 2-59 2-53 4-2
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2-30
~
=
2-31 3-22 3-69 3-45S
TECHNICAL REFERENCE
testing, command
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timer, abort
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i
timers.
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s
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S
scan rate
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5
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3
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memory .
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.
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.
.
S
disable data and status interrupt .
.
enable data and status interrupt..
cenable status interrupt
o
,get and compare data
get status
5
o
.
- poll for regquest .
s
.
write data Winchester:
.
e
o
.
S
-disk system
.
o
s
.
drive format .
a
e
error codes
.
0
o
o
1/0 ports
S
o
ROM
S
.
.
.
wrap
.
s
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e
5
o
WRITE command .
6
5
9
Write data WRITE LONG
to the Winchester
command.
o
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contréllef
write preconpensation circuit
WRITE SECTOR BUFFER command
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