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i.MX RT1064 Crossover Processors Data Sheet for Consumer Products

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i.MX RT1064

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i.MX RT1064 Crossover Processors Data Sheet for Consumer ...

29 avr. 2021 — Two 10/100M Ethernet controller with support for IEEE1588 ... With touch controller to support 4-wire and 5-wire resistive touch panel.

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NXP Semiconductors Data Sheet: Technical Data

Document Number: IMXRT1064CEC Rev. 3, 03/2021

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products

MIMXRT1064DVL6A MIMXRT1064DVJ6A

MIMXRT1064DVL6B MIMXRT1064DVJ6B

Package Information Plastic Package
196-pin MAPBGA, 10 x 10 mm, 0.65 mm pitch 196-pin MAPBGA, 12 x 12 mm, 0.8 mm pitch

Ordering Information

1 i.MX RT1064 Introduction

See Table 1 on page 6

The i.MX RT1064 is a new processor family featuring 1. i.MX RT1064 Introduction . . . . . . . . . . . . . . . . . . . . . . . . 1

NXP's advanced implementation of the Arm Cortex�-M7 core, which operates at speeds up to 600 MHz to provide high CPU performance and best

1.1. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2. Ordering information . . . . . . . . . . . . . . . . . . . . . . . 6 2. Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

real-time response.

3. Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1. Special signal considerations . . . . . . . . . . . . . . . 16

The i.MX RT1064 processor has 4 MB on chip Flash and

3.2. Recommended connections for unused analog interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

1 MB on-chip RAM. 512 KB SRAM can be flexibly 4. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 19

configured as TCM or general-purpose on-chip RAM, while the other 512 KB SRAM is general-purpose

4.1. Chip-Level conditions . . . . . . . . . . . . . . . . . . . . . 19 4.2. System power and clocks . . . . . . . . . . . . . . . . . . 26 4.3. I/O parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 31

on-chip RAM. The i.MX RT1064 integrates advanced power management module with DCDC and LDO that reduces complexity of external power supply and

4.4. System modules . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.5. External memory interface . . . . . . . . . . . . . . . . . 43 4.6. Display and graphics . . . . . . . . . . . . . . . . . . . . . . 53 4.7. Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

simplifies power sequencing. The i.MX RT1064 also provides various memory interfaces, including SDRAM,

4.8. Analog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.9. Communication interfaces . . . . . . . . . . . . . . . . . . 66 4.10. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

RAW NAND FLASH, NOR FLASH, SD/eMMC, Quad 5. Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

SPI, and a wide range of other interfaces for connecting

Boot mode configuration . . . . . . . . . . . . . . . . . . . . . . . . 82 6.1. Boot mode configuration pins . . . . . . . . . . . . . . . 82

peripherals, such as WLAN, BluetoothTM, GPS,

6.2. Boot device interface allocation . . . . . . . . . . . . . . 82

displays, and camera sensors. The i.MX RT1064 has rich audio and video features, including LCD display, basic

Package information and contact assignments . . . . . . . 87 7.1. 10 x 10 mm package information . . . . . . . . . . . . 87 7.2. 12 x 12 mm package information . . . . . . . . . . . . 99

2D graphics, camera interface, SPDIF, and I2S audio 8. Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.

i.MX RT1064 Introduction
interface. The i.MX RT1064 has analog interfaces, such as ADC, ACMP, and TSC.
The i.MX RT1064 is specifically useful for applications such as: � Industrial Human Machine Interfaces (HMI) � Motor Control � Home Appliance
1.1 Features
The i.MX RT1064 processors are based on Arm Cortex-M7 Core Platform, which has the following features:
� Supports single Arm Cortex-M7 Core with: -- 32 KB L1 Instruction Cache -- 32 KB L1 Data Cache -- Full featured Floating Point Unit (FPU) with support of the VFPv5 architecture -- Support the Armv7-M Thumb instruction set
� Integrated MPU, up to 16 individual protection regions � Tightly coupled GPIOs, operating at the same frequency as Arm core � Up to 512 KB I-TCM and D-TCM in total � Frequency of 600/528 MHz � Cortex M7 CoreSightTM components integration for debug � Frequency of the core, as per Table 10, "Operating ranges," on page 21.
The SoC-level memory system consists of the following additional components: -- Boot ROM (128 KB) -- On-chip Flash (4 MB) -- On-chip RAM (1 MB) � 512 KB OCRAM shared between ITCM/DTCM and OCRAM � Dedicate 512 KB OCRAM
� External memory interfaces: -- 8/16-bit SDRAM, up to SDRAM-133/SDRAM-166 -- 8/16-bit SLC NAND FLASH, with ECC handled in software -- SD/eMMC -- SPI NOR/NAND FLASH -- Parallel NOR FLASH with XIP support -- Two single/dual channel Quad SPI FLASH with XIP support
� Timers and PWMs: -- Two General Programmable Timers (GPT) � 4-channel generic 32-bit resolution timer � Each support standard capture and compare operation

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 3, 03/2021

NXP Semiconductors

i.MX RT1064 Introduction
-- Four Periodical Interrupt Timers (PIT) � Generic 32-bit resolution timer � Periodical interrupt generation
-- Four Quad Timers (QTimer) � 4-channel generic 16-bit resolution timer for each � Each support standard capture and compare operation � Quadrature decoder integrated
-- Four FlexPWMs � Up to 8 individual PWM channels per each � 16-bit resolution PWM suitable for Motor Control applications
-- Four Quadrature Encoder/Decoders
Each i.MX RT1064 processor enables the following interfaces to external devices (some of them are muxed and not available simultaneously):
� Display Interface: -- Parallel RGB LCD interface � Support 8/16/24 bit interface � Support up to WXGA resolution � Support Index color with 256 entry x 24 bit color LUT � Smart LCD display with 8/16-bit MPU/8080 interface
� Audio: -- S/PDIF input and output -- Three synchronous audio interface (SAI) modules supporting I2S, AC97, TDM, and codec/DSP interfaces -- MQS interface for medium quality audio via GPIO pads
� Generic 2D graphics engine: -- BitBlit -- Flexible image composition options--alpha, chroma key -- Porter-duff blending -- Image rotation (90, 180, 270) -- Image size -- Color space conversion -- Multiple pixel format support (RGB, YUV444, YUV422, YUV420, YUV400) -- Standard 2D-DMA operation
� Camera sensors: -- Support 24-bit, 16-bit, and 8-bit CSI input
� Connectivity: -- Two USB 2.0 HS OTG controllers with integrated PHY interfaces

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NXP Semiconductors

i.MX RT1064 Introduction
-- Two Ultra Secure Digital Host Controller (uSDHC) interfaces � MMC 4.5 compliance with HS200 support up to 200 MB/sec � SD/SDIO 3.0 compliance with 200 MHz SDR signaling to support up to 100 MB/sec � Support for SDXC (extended capacity)
-- Two 10/100M Ethernet controller with support for IEEE1588 -- Eight universal asynchronous receiver/transmitter (UARTs) modules -- Four I2C modules -- Four SPI modules -- Two FlexCAN modules -- FlexCAN (with Flexible Data-Rate supported) -- Three FlexIO modules � GPIO and Pin Multiplexing: -- General-purpose input/output (GPIO) modules with interrupt capability -- Input/output multiplexing controller (IOMUXC) to provide centralized pad control
The i.MX RT1064 processors integrate advanced power management unit and controllers: � Full PMIC integration, including on-chip DCDC and LDO � Temperature sensor with programmable trim points � GPC hardware power management controller
The i.MX RT1064 processors support the following system debug: � Arm CoreSight debug and trace architecture � Trace Port Interface Unit (TPIU) to support off-chip real-time trace � Cross Triggering Interface (CTI) � Support for 5-pin (JTAG) and SWD debug interfaces
The i.MX RT1064 processors support the following analog interfaces: � Two Analog-Digital-Converters (ADC), 16-channel for each, 20-channel in total, 1MSPS � Four Analog Comparators (ACMP)
Security functions are enabled and accelerated by the following hardware: � High Assurance Boot (HAB) � Data Co-Processor (DCP): -- AES-128, ECB, and CBC mode -- SHA-1 and SHA-256 -- CRC-32 � Bus Encryption Engine (BEE) -- AES-128, ECB, and CTR mode -- On-the-fly QSPI Flash decryption � True random number generation (TRNG) � Secure Non-Volatile Storage (SNVS)

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 3, 03/2021

NXP Semiconductors

i.MX RT1064 Introduction
-- Secure real-time clock (RTC) -- Zero Master Key (ZMK) � Secure JTAG Controller (SJC)
NOTE The actual feature set depends on the part numbers as described in Table 1. Functions such as display and camera interfaces, connectivity interfaces, and security features are not offered on all derivatives.

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 3, 03/2021

NXP Semiconductors

i.MX RT1064 Introduction

1.2 Ordering information
Table 1 provides examples of orderable part numbers covered by this Data Sheet.
Table 1. Ordering information

Part Number

Features

Package

MIMXRT1064DVL6A MIMXRT1064DVL6B

� 600 MHz, commercial grade for general purpose, with MPU/FPU
� 4 MB Flash � eDMA � Boot ROM (128 KB) � On-chip RAM (1 MB) � SEMC � GPT x2 � 4-channel PIT � Qtimer x4 � PWM x4 � ENC x4 � WDOG x4 � LCD/CSI/PXP � SPDIF x1 � SAI x3 � MQS x1 � USB OTG x2 � eMMC 4.5/SD 3.0 x2 � KPP x1 � SPI x4

MIMXRT1064DVJ6A MIMXRT1064DVJ6B

� XBAR/AOI � Ethernet x2

10 x 10 mm, 0.65 mm pitch, 196-pin MAPBGA

� UART x8

� I2C x4

� FlexSPI x1

� CAN x2

� FlexCAN (with Flexible

Data-Rate supported)

� FlexIO x3

� 127 GPIOs (124 tightly

coupled)

� HAB/DCP/BEE/CSU

� TRNG

� SNVS (with RTC

supported)

� SJC

� ADC x2

� ACMP x4

� TSC

� DCDC

� Temperature sensor � GPC hardware power
management controller

� XBAR/AOI � Ethernet x2

12 x 12 mm, 0.8 mm pitch, 196-pin MAPBGA

� UART x8

� I2C x4

� FlexSPI x1

� CAN x2

� FlexCAN (with Flexible

Data-Rate supported)

� FlexIO x3

� 127 GPIOs (124 tightly

coupled)

� HAB/DCP/BEE/CSU

� TRNG

� SNVS (with RTC

supported)

� SJC

� ADC x2

� ACMP x4

� TSC

� DCDC

� Temperature sensor � GPC hardware power
management controller

Junction Temperature Tj
(C) 0 to +85
0 to +85

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 3, 03/2021

NXP Semiconductors

i.MX RT1064 Introduction
Figure 1 describes the part number nomenclature so that characteristics of a specific part number can be identified (for example, cores, frequency, temperature grade, fuse options, and silicon revision). The primary characteristic which describes which data sheet applies to a specific part is the temperature grade (junction) field.
Ensure to have the proper data sheet for specific part by verifying the temperature grade (junction) field and matching it to the proper data sheet. If there are any questions, visit the web page nxp.com/IMXRT or contact an NXP representative for details.

M IMX X X @ ## % + VV $ A

Qualification Level Prototype Samples Mass Production Special
Part # series i.MX RT
Family First Generation RT family Reserved
Sub-Family RT101x RT102x RT104x RT105x RT106x

M P M S
XX RT
@ 1 2-8
## 01 02 04 05 06

Tie

Standard Feature

Full Feature

4MB Flash SIP

Enhanced Feature

Far Field AFE

Facial Recognition

Local Voice Control (audio input models)

Local Voice Control (text input models)

Silicon Rev

Core Frequency

400 MHz

500 MHz

600 MHz

Package Type

225MAPBGA, 13 x 13 mm, 0.8 mm pitch

196MAPBGA, 12 x 12 mm, 0.8 mm pitch

196MAPBGA, 10 x 10 mm, 0.65 mm pitch

169MAPBGA, 11 x 11 mm, 0.8 mm pitch

169MAPBGA, 9 x 9 mm, 0.65 mm pitch

144LQFP, 20 x 20 mm, 0.5 mm pitch

100LQFP, 14 x 14 mm, 0.5 mm pitch

80LQFP, 12 x 12 mm, 0.5 mm pitch

Temperature (Tj)

Consumer: 0 to + 95 �C

Industrial: -40 to +105 �C

Extended Industrial: -40 to +125 eC

Figure 1. Part number nomenclature--i.MX RT10XX family

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 3, 03/2021

NXP Semiconductors

Architectural Overview
2 Architectural Overview
The following subsections provide an architectural overview of the i.MX RT1064 processor system.
2.1 Block diagram
Figure 2 shows the functional modules in the i.MX RT1064 processor system.

System Control Secure JTAG PLL / OSC RTC and Reset Enhanced DMA IOMUX GP Timer x6
Quadrature ENC x4 QuadTimer x4 FlexPWM x4 XBAR/AOI Watch Dog x4
Internal Memory 512 KB SRAM 4 MB Flash 128 KB ROM
Power Management DCDC
LDO Temp Monitor
Ciphers and RNG

CPU Platform Arm Cortex-M7

32 KB I-cache

32 KB D-cache

FPU

MPU

NVIC

512 KB TCM/OCRAM

HS_GPIO

FlexIO

Multimedia 8 / 16 / 24-bit Parallel CSI
24-bit Parallel LCD
PXP 2D Graphics Acceleration Resize, CSC, Overlay, Rotation

External Memory
Dual-channel QuadSPI Octal/Hyper Flash/RAM x1

External Memory Controller 8-bit / 16-bit SDRAM Parallel NOR FLASH NAND FLASH PSRAM

Secure RTC

Security

eFuse

Connectivity eMMC 4.5 / SD 3.0 x2
UART x8
8 x 8 Keypad
I2C x4
SPI x4 FlexIO x2
GPIO
I2S / SAI x3 S/PDIF Tx / Rx FlexCAN x2 + FlexCAN ( with Flexible Data-Rate supported) USB 2.0 OTG with PHY x2 10 / 100 ENET x2
with IEEE 1588 ADC
ADC x2 (16-Channel) 20-Channel in total
ACMP x4
HAB

.
Figure 2. i.MX RT1064 system block diagram

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 3, 03/2021

NXP Semiconductors

Modules List

3 Modules List

The i.MX RT1064 processors contain a variety of digital and analog modules. Table 2 describes these modules in alphabetical order.
Table 2. i.MX RT1064 modules list

Block Mnemonic

Block Name

Subsystem

Brief Description

ACMP1 ACMP2 ACMP3 ACMP4 ADC1 ADC2
AOI
Arm
BEE CCM GPC SRC CSI
CSU
DAP

Analog Comparator

Analog

The comparator (CMP) provides a circuit for comparing two analog input voltages. The comparator circuit is designed to operate across the full range of the supply voltage (rail-to-rail operation).

Analog to Digital Converter

Analog

The ADC is a 12-bit general purpose analog to digital converter.

And-Or-Inverter

Cross Trigger

The AOI provides a universal boolean function generator using a four team sum of products expression with each product term containing true or complement values of the four selected inputs (A, B, C, D).

Arm Platform

Arm

The Arm Core Platform includes one Cortex-M7 core. It

includes associated sub-blocks, such as Nested

Vectored Interrupt Controller (NVIC), Floating-Point

Unit (FPU), Memory Protection Unit (MPU), and

CoreSight debug modules.

Bus Encryption Engine

Security

On-The-Fly FlexSPI Flash Decryption

Clock Control Module, General Power
Controller, System Reset Controller

Clocks, Resets, and Power Control

These modules are responsible for clock and reset distribution in the system, and also for the system power management.

Parallel CSI

Multimedia Peripherals

The CSI IP provides parallel CSI standard camera interface port. The CSI parallel data ports are up to 24 bits. It is designed to support 24-bit RGB888/YUV444, CCIR656 video interface, 8-bit YCbCr, YUV or RGB, and 8-bit/10-bit/16-bit Bayer data input.

Central Security Unit

Security

The Central Security Unit (CSU) is responsible for setting comprehensive security policy within the i.MX RT1064 platform.

Debug Access Port

System Control Peripherals

The DAP provides real-time access for the debugger without halting the core to: � System memory and peripheral registers � All debug configuration registers The DAP also provides debugger access to JTAG scan chains. The DAP module is internal to the Cortex-M7 Core Platform.

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 3, 03/2021

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Modules List

Table 2. i.MX RT1064 modules list (continued)

Block Mnemonic

Block Name

Subsystem

Brief Description

DCDC
eDMA
ENC ENET1 ENET2 EWM
FLEXCAN1 FLEXCAN2

DCDC Converter
enhanced Direct Memory Access
Quadrature Encoder/Decoder
Ethernet Controller
External Watchdog Monitor
Flexible Controller Area Network

Analog
System Control Peripherals
Timer Peripherals
Connectivity Peripherals
Timer Peripherals
Connectivity Peripherals

The DCDC module is used for generating power supply for core logic. Main features are: � Adjustable high efficiency regulator � Supports 3.3 V input voltage � Supports nominal run and low power standby modes � Supports at 0.9 ~ 1.3 V output in run mode � Supports at 0.9 ~ 1.0 V output in standby mode � Over current and over voltage detection
There is an enhanced DMA (eDMA) engine and two DMA_MUX. � The eDMA is a 32 channel DMA engine, which is
capable of performing complex data transfers with minimal intervention from a host processor. � The DMA_MUX is capable of multiplexing up to 128 DMA request sources to the 32 DMA channels of eDMA.
The enhanced quadrature encoder/decoder module provides interfacing capability to position/speed sensors. There are five input signals: PHASEA, PHASEB, INDEX, TRIGGER, and HOME. This module is used to decode shaft position, revolution count, and speed.
The Ethernet Media Access Controller (MAC) is designed to support 10/100 Mbit/s Ethernet/IEEE 802.3 networks. An external transceiver interface and transceiver function are required to complete the interface to the media. The module has dedicated hardware to support the IEEE 1588 standard. See the ENET chapter of the reference manual for details.
The EWM modules is designed to monitor external circuits, as well as the software flow. This provides a back-up mechanism to the internal WDOG that can reset the system. The EWM differs from the internal WDOG in that it does not reset the system. The EWM, if allowed to time-out, provides an independent trigger pin that when asserted resets or places an external circuit into a safe mode.
The CAN protocol was primarily, but not only, designed to be used as a vehicle serial data bus, meeting the specific requirements of this field: real-time processing, reliable operation in the Electromagnetic interference (EMI) environment of a vehicle, cost-effectiveness and required bandwidth. The FlexCAN module is a full implementation of the CAN protocol specification, Version 2.0 B, which supports both standard and extended message frames.

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 3, 03/2021

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Modules List

Table 2. i.MX RT1064 modules list (continued)

Block Mnemonic

Block Name

FLEXCAN (FD) Flexible Controller Area Network

FlexIO1 FlexIO2 FlexIO3

Flexible Input/output

FlexPWM1 FlexPWM2 FlexPWM3 FlexPWM4

Pulse Width Modulation

FlexRAM

RAM

FlexSPI
GPIO1 GPIO2 GPIO3 GPIO4 GPIO5
GPT1 GPT2

Quad Serial Peripheral Interface
General Purpose I/O Modules
General Purpose Timer

Subsystem

Brief Description

Connectivity Peripherals

The CAN with Flexible Data-Rate protocol and the CAN 2.0 version B protocol supports both standard and extended message frames, both of them have long payloads up to 64 bytes transferred at faster rates up to 8 Mbps.

Connectivity and Communications

The FlexIO is capable of supporting a wide range of protocols including, but not limited to: UART, I2C, SPI, I2S, camera interface, display interface, PWM waveform generation, etc. The module can remain functional when the chip is in a low power mode provided the clock it is using remain active.

Timer Peripherals

The pulse-width modulator (PWM) contains four PWM sub-modules, each of which is set up to control a single half-bridge power stage. Fault channel support is provided. The PWM module can generate various switching patterns, including highly sophisticated waveforms.

Memories

The i.MX RT1064 has 1 MB of on-chip RAM which could be flexible allocated to I-TCM, D-TCM, and on-chip RAM (OCRAM) in a 32 KB granularity. The FlexRAM is the manager of the on-chip RAM array. Major functions of this blocks are: interfacing to I-TCM and D-TCM of Arm core and OCRAM controller; dynamic RAM arrays allocation for I-TCM, D-TCM, and OCRAM.

Connectivity and Communications

FlexSPI acts as an interface to one or two external serial flash devices, each with up to four bidirectional data lines.

System Control Used for general purpose input/output to external ICs.

Peripherals

Each GPIO module supports up to 32 bits of I/O.

Timer Peripherals

Each GPT is a 32-bit "free-running" or "set and forget" mode timer with programmable prescaler and compare and capture register. A timer counter value can be captured using an external event and can be configured to trigger a capture event on either the leading or trailing edges of an input pulse. When the timer is configured to operate in "set and forget" mode, it is capable of providing precise interrupts at regular intervals with minimal processor intervention. The counter has output compare logic to provide the status and interrupt at comparison. This timer can be configured to run either on an external clock or on an internal clock.

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Modules List

Table 2. i.MX RT1064 modules list (continued)

Block Mnemonic

Block Name

Subsystem

Brief Description

KPP
LCDIF
LPI2C1 LPI2C2 LPI2C3 LPI2C4
LPSPI1 LPSPI2 LPSPI3 LPSPI4
LPUART1 LPUART2 LPUART3 LPUART4 LPUART5 LPUART6 LPUART7 LPUART8
MQS
PXP

Keypad Port
LCD interface
Low Power Inter-integrated Circuit
Low Power Serial Peripheral Interface
UART Interface

Human Machine Interfaces
Multimedia Peripherals
Connectivity and Communications
Connectivity and Communications
Connectivity Peripherals

The KPP is a 16-bit peripheral that can be used as a keypad matrix interface or as general purpose input/output (I/O). It supports 8 x 8 external key pad matrix. Main features are: � Multiple-key detection � Long key-press detection � Standby key-press detection � Supports a 2-point and 3-point contact key matrix
The LCDIF is a general purpose display controller used to drive a wide range of display devices varying in size and capabilities. The LCDIF is designed to support dumb (synchronous 24-bit Parallel RGB interface) and smart (asynchronous parallel MPU interface) LCD devices.
The LPI2C is a low power Inter-Integrated Circuit (I2C) module that supports an efficient interface to an I2C bus as a master. The I2C provides a method of communication between a number of external devices. More detailed information, see Section 4.9.2, LPI2C module timing parameters.
The LPSPI is a low power Serial Peripheral Interface (SPI) module that support an efficient interface to an SPI bus as a master and/or a slave. � It can continue operating while the chip is in stop
modes, if an appropriate clock is available � Designed for low CPU overhead, with DMA off
loading of FIFO register access
Each of the UART modules support the following serial data transmit/receive protocols and configurations: � 7- or 8-bit data words, 1 or 2 stop bits, programmable
parity (even, odd or none) � Programmable baud rates up to 20 Mbps.

Medium Quality Sound Pixel Processing Pipeline

Multimedia Peripherals
Multimedia Peripherals

MQS is used to generate 2-channel medium quality PWM-like audio via two standard digital GPIO pins.
A high-performance pixel processor capable of 1 pixel/clock performance for combined operations, such as color-space conversion, alpha blending, and rotation. The PXP is enhanced with features specifically for gray scale applications. In addition, the PXP supports traditional pixel/frame processing paths for still-image and video processing applications.

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NXP Semiconductors

Modules List

Table 2. i.MX RT1064 modules list (continued)

Block Mnemonic

Block Name

Subsystem

Brief Description

QuadTimer1 QuadTimer2 QuadTimer3 QuadTimer4
ROMCP
RTC OSC
RTWDOG
SAI1 SAI2 SAI3 SA-TRNG SEMC

QuadTimer

Timer Peripherals

The quad-timer provides four time channels with a variety of controls affecting both individual and multi-channel features.Specific features include up/down count, cascading of counters, programmable module, count once/repeated, counter preload, compare registers with preload, shared use of input signals, prescaler controls, independent capture/compare, fault input control, programmable input filters, and multi-channel synchronization.

ROM Controller with Patch

Memories and The ROMCP acts as an interface between the Arm Memory Controllers advanced high-performance bus and the ROM. The
on-chip ROM is only used by the Cortex-M7 core during boot up. Size of the ROM is 96 KB.

Real Time Clock Oscillator

Clock Sources and Control

The RTC OSC provides the clock source for the Real-Time Clock module. The RTC OSC module, in conjunction with an external crystal, generates a 32.768 kHz reference clock for the RTC.

Watch Dog

Timer Peripherals

The RTWDG module is a high reliability independent timer that is available for system to use. It provides a safety feature to ensure software is executing as planned and the CPU is not stuck in an infinite loop or executing unintended code. If the WDOG module is not serviced (refreshed) within a certain period, it resets the MCU. Windowed refresh mode is supported as well.

Synchronous Audio Interface

Multimedia Peripherals

The SAI module provides a synchronous audio interface (SAI) that supports full duplex serial interfaces with frame synchronization, such as I2S, AC97, TDM, and codec/DSP interfaces.

Standalone True Random Number Generator

Security

The SA-TRNG is hardware accelerator that generates a 512-bit entropy as needed by an entropy consuming module or by other post processing functions.

Smart External Memory Controller

Memory and Memory Controller

The SEMC is a multi-standard memory controller optimized for both high-performance and low pin-count. It can support multiple external memories in the same application with shared address and data pins. The interface supported includes SDRAM, NOR Flash, SRAM, and NAND Flash, as well as 8080 display interface.

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 3, 03/2021

NXP Semiconductors

Modules List

Table 2. i.MX RT1064 modules list (continued)

Block Mnemonic

Block Name

SJC

System JTAG Controller

SNVS SPDIF Temp Monitor

Secure Non-Volatile Storage
Sony Philips Digital Interconnect Format
Temperature Monitor

TSC USBO2

Touch Screen Universal Serial Bus 2.0

Subsystem System Control
Peripherals
Security Multimedia Peripherals
Analog Human Machine
Interfaces Connectivity Peripherals

Brief Description
The SJC provides JTAG interface, which complies with JTAG TAP standards, to internal logic. The i.MX RT1064 processors use JTAG port for production, testing, and system debugging. In addition, the SJC provides BSR (Boundary Scan Register) standard support, which complies with IEEE 1149.1 and IEEE 1149.6 standards. The JTAG port is accessible during platform initial laboratory bring-up, for manufacturing tests and troubleshooting, as well as for software debugging by authorized entities. The i.MX RT1064 SJC incorporates three security modes for protecting against unauthorized accesses. Modes are selected through eFUSE configuration.
Secure Non-Volatile Storage, including Secure Real Time Clock, Security State Machine, and Master Key Control.
A standard audio file transfer format, developed jointly by the Sony and Phillips corporations. Has Transmitter and Receiver functionality.
The temperature sensor implements a temperature sensor/conversion function based on a temperature-dependent voltage to time conversion.
With touch controller to support 4-wire and 5-wire resistive touch panel.
USBO2 (USB OTG1 and USB OTG2) contains: � Two high-speed OTG 2.0 modules with integrated
HS USB PHYs � Support eight Transmit (TX) and eight Receive (Rx)
endpoints, including endpoint 0

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 3, 03/2021

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Modules List

Table 2. i.MX RT1064 modules list (continued)

Block Mnemonic

Block Name

Subsystem

Brief Description

uSDHC1 uSDHC2
WDOG1 WDOG2
XBAR

SD/MMC and SDXC Enhanced Multi-Media Card / Secure Digital Host
Controller
Watch Dog Cross BAR

Connectivity Peripherals
Timer Peripherals Cross Trigger

i.MX RT1064 specific SoC characteristics: All four MMC/SD/SDIO controller IPs are identical and are based on the uSDHC IP. They are: � Fully compliant with MMC command/response sets
and Physical Layer as defined in the Multimedia Card System Specification, v4.5/4.2/4.3/4.4/4.41/ including high-capacity (size > 2 GB) cards HC MMC. � Fully compliant with SD command/response sets and Physical Layer as defined in the SD Memory Card Specifications, v3.0 including high-capacity SDXC cards up to 2 TB. � Fully compliant with SDIO command/response sets and interrupt/read-wait mode as defined in the SDIO Card Specification, Part E1, v3.0 Two ports support: � 1-bit or 4-bit transfer mode specifications for SD and SDIO cards up to UHS-I SDR104 mode (104 MB/s max) � 1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards up to 52 MHz in both SDR and DDR modes (104 MB/s max) � 4-bit or 8-bit transfer mode specifications for eMMC chips up to 200 MHz in HS200 mode (200 MB/s max)
The watchdog (WDOG) Timer supports two comparison points during each counting period. Each of the comparison points is configurable to evoke an interrupt to the Arm core, and a second point evokes an external event on the WDOG line.
Each crossbar switch is an array of muxes with shared inputs. Each mux output provides one output of the crossbar. The number of inputs and the number of muxes/outputs are user configurable and registers are provided to select which of the shared inputs are routed to each output.

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 3, 03/2021

NXP Semiconductors

Modules List

3.1 Special signal considerations
Table 3 lists special signal considerations for the i.MX RT1064 processors. The signal names are listed in alphabetical order.
The package contact assignments can be found in Section 7, Package information and contact assignments." Signal descriptions are provided in the i.MX RT1064 Reference Manual (IMXRT1064RM).
Table 3. Special signal considerations

Signal Name

Remarks

CCM_CLK1_P/ CCM_CLK1_N

One general purpose differential high speed clock Input/output (LVDS I/O) is provided. It can be used: � To feed external reference clock to the PLLs and further to the modules inside SoC. � To output internal SoC clock to be used outside the SoC as either reference clock or as a
functional clock for peripherals. See the i.MX RT1064 Reference Manual (IMXRT1064RM) for details on the respective clock trees. Alternatively one may use single ended signal to drive CLK1_P input. In this case corresponding CLK1_N input should be tied to the constant voltage level equal 1/2 of the input signal swing. Termination should be provided in case of high frequency signals. After initialization, the CLK1 input/output can be disabled (if not used). If unused either or both of the CLK1_N/P pairs may remain unconnected.

DCDC_PSWITCH

PAD is in DCDC_IN domain and connected the ground to bypass DCDC. To enable DCDC function, assert to DCDC_IN with at least 1ms delay for DCDC_IN rising edge.

RTC_XTALI/RTC_XTALO

If the user wishes to configure RTC_XTALI and RTC_XTALO as an RTC oscillator, a 32.768 kHz crystal, (100 k ESR, 10 pF load) should be connected between RTC_XTALI and RTC_XTALO. Keep in mind the capacitors implemented on either side of the crystal are about twice the crystal load capacitor. To hit the exact oscillation frequency, the board capacitors need to be reduced to account for board and chip parasitics. The integrated oscillation amplifier is self biasing, but relatively weak. Care must be taken to limit parasitic leakage from RTC_XTALI and RTC_XTALO to either power or ground (>100 M). This will debias the amplifier and cause a reduction of startup margin. Typically RTC_XTALI and RTC_XTALO should bias to approximately 0.5 V. If it is desired to feed an external low frequency clock into RTC_XTALI the RTC_XTALO pin must remain unconnected or driven with a complimentary signal. The logic level of this forcing clock should not exceed VDD_SNVS_CAP level and the frequency should be <100 kHz under typical conditions. In case when high accuracy real time clock are not required system may use internal low frequency ring oscillator. It is recommended to connect RTC_XTALI to GND and keep RTC_XTALO unconnected.

XTALI/XTALO

A 24.0 MHz crystal should be connected between XTALI and XTALO. The crystal must be rated for a maximum drive level of 250 W. An ESR (equivalent series resistance) of typical 80 is recommended. NXP SDK software requires 24 MHz on XTALI/XTALO. The crystal can be eliminated if an external 24 MHz oscillator is available in the system. In this case, XTALO must be directly driven by the external oscillator and XTALI mounted with 18 pF capacitor. The logic level of this forcing clock cannot exceed NVCC_PLL level. If this clock is used as a reference for USB, then there are strict frequency tolerance and jitter requirements. See OSC24M chapter and relevant interface specifications chapters for details.

GPANAIO

This signal is reserved for NXP manufacturing use only. This output must remain unconnected.

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 3, 03/2021

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Signal Name JTAG_nnnn
NC POR_B ONOFF
TEST_MODE WAKEUP

Modules List
Table 3. Special signal considerations (continued)
Remarks
The JTAG interface is summarized in Table 4. Use of external resistors is unnecessary. However, if external resistors are used, the user must ensure that the on-chip pull-up/down configuration is followed. For example, do not use an external pull down on an input that has on-chip pull-up.
JTAG_TDO is configured with a keeper circuit such that the non-connected condition is eliminated if an external pull resistor is not present. An external pull resistor on JTAG_TDO is detrimental and should be avoided.
JTAG_MOD is referenced as SJC_MOD in the i.MX RT1064 reference manual. Both names refer to the same signal. JTAG_MOD must be externally connected to GND for normal operation. Termination to GND through an external pull-down resistor (such as 1 k) is allowed. JTAG_MOD set to hi configures the JTAG interface to mode compliant with IEEE1149.1 standard. JTAG_MOD set to low configures the JTAG interface for common SW debug adding all the system TAPs to the chain.
These signals are No Connect (NC) and should be disconnected by the user.
This cold reset negative logic input resets all modules and logic in the IC. May be used in addition to internally generated power on reset signal (logical AND, both internal and external signals are considered active low).
ONOFF can be configured in debounce, off to on time, and max time-out configurations. The debounce and off to on time configurations supports 0, 50, 100 and 500 ms. Debounce is used to generate the power off interrupt. While in the ON state, if ONOFF button is pressed longer than the debounce time, the power off interrupt is generated. Off to on time supports the time it takes to request power on after a configured button press time has been reached. While in the OFF state, if ONOFF button is pressed longer than the off to on time, the state will transition from OFF to ON. Max time-out configuration supports 5, 10, 15 seconds and disable. Max time-out configuration supports the time it takes to request power down after ONOFF button has been pressed for the defined time.
TEST_MODE is for NXP factory use. The user can leave this signal floating or tie it to ground.
A GPIO powered by SNVS domain power supply which can be configured as wakeup source in SNVS mode.

JTAG JTAG_TCK JTAG_TMS JTAG_TDI JTAG_TDO JTAG_TRSTB JTAG_MOD

Table 4. JTAG Controller interface summary
I/O Type Input Input Input
3-state output Input Input

On-chip Termination
100 kpull-down 47 kpull-up 47 kpull-up
Keeper
47 kpull-up 100 kpull-down

3.2 Recommended connections for unused analog interfaces
Table 5 shows the recommended connections for unused analog interfaces.

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 3, 03/2021

NXP Semiconductors

Modules List

Table 5. Recommended connections for unused analog interfaces

Module

Pad Name

CCM USB
ADC

CCM_CLK1_N, CCM_CLK1_P
USB_OTG1_CHD_B, USB_OTG1_DN, USB_OTG1_DP, USB_OTG1_VBUS, USB_OTG2_DN, USB_OTG2_DP, USB_OTG2_VBUS
VDDA_ADC_3P3

Recommendations if Unused
Not connected
Not connected
VDDA_ADC_3P3 must be powered even if the ADC is
not used.

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 3, 03/2021

NXP Semiconductors

Electrical Characteristics
4 Electrical Characteristics
This section provides the device and module-level electrical characteristics for the i.MX RT1064 processors.

4.1 Chip-Level conditions
This section provides the device-level electrical characteristics for the IC. See Table 6 for a quick reference to the individual tables and sections.
Table 6. i.MX RT1064 chip-Level conditions

For these characteristics Absolute maximum ratings Thermal resistance Operating ranges External clock sources Maximum supply currents Low power mode supply currents USB PHY current consumption

Topic appears on page 19 on page 20 on page 21 on page 22 on page 23 on page 25 on page 25

4.1.1 Absolute maximum ratings
CAUTION
Stress beyond those listed under Table 7 may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Table 7 shows the absolute maximum operating ratings.

Table 7. Absolute maximum ratings

Parameter Description Core supplies input voltage VDD_HIGH_IN supply voltage Power for DCDC Supply input voltage to Secure Non-Volatile Storage and Real Time Clock USB VBUS supply
Supply for 12-bit ADC

Symbol VDD_SOC_IN VDD_HIGH_IN
DCDC_IN VDD_SNVS_IN
USB_OTG1_VBUS USB_OTG2_VBUS
VDDA_ADC

Min

Max

Unit

-0.3

1.6

-0.3

3.7

-0.3

3.6

-0.3

3.6

5.5

-0.3

3.6

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 3, 03/2021

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Electrical Characteristics

Table 7. Absolute maximum ratings (continued)

IO supply for GPIO in SDIO1 bank (3.3 V mode) IO supply for GPIO in SDIO1 bank (1.8 V mode) IO supply for GPIO in SDIO2 bank (3.3 V mode) IO supply for GPIO in SDIO2 bank (1.8 V mode) IO supply for GPIO in EMC bank (3.3 V mode) IO supply for GPIO in EMC bank (1.8 V mode)

NVCC_SD0 NVCC_SD1 NVCC_EMC

-0.3

3.6

-0.3

1.95

-0.3

3.6

-0.3

1.95

-0.3

3.6

-0.3

1.95

ESD damage Immunity:

Vesd

Human Body Model (HBM) Charge Device Model (CDM)
Input/Output Voltage range
Storage Temperature range 1 OVDD is the I/O supply voltage.

Vin/Vout TSTORAGE

1000

500

-0.5

OVDD + 0.31

-40

150

o C

4.1.2 Thermal resistance

4.1.2.1 10 x 10 mm thermal resistance

Table 9 shows the 10 x 10 mm package thermal resistance data.
Table 8. 10 x 10 mm thermal resistance data

Rating

Board type1

Symbol

Value

Unit

Junction to Ambient Thermal Resistance2

JESD51-9, 2S2P

RJA

39.5

oC/W

Junction-to-Top of Package Thermal Characterization Parameter2

JESD51-9, 2S2P

2.65

oC/W

1 Thermal test board meets JEDEC specification for this package (JESD51-9). 2 Determined in accordance to JEDEC JESD51-2A natural convection environment. Thermal resistance data in this report is
solely for a thermal performance comparison of one package to another in a standardized specified environment. It is not meant to predict the performance of a package in an application-specific environment.

4.1.2.2 12 x 12 mm thermal resistance

Table 9 shows the 12 x 12 mm package thermal resistance data.
Table 9. 12 x 12 mm thermal resistance data

Rating

Board type1

Symbol

Junction to Ambient Thermal Resistance2

JESD51-9, 2S2P

Junction-to-Top of Package Thermal Characterization Parameter2

JESD51-9, 2S2P

1 Thermal test board meets JEDEC specification for this package (JESD51-9).

RJA JT

Value 39.0
2.75

Unit oC/W
oC/W

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 3, 03/2021

NXP Semiconductors

Electrical Characteristics
2 Determined in accordance to JEDEC JESD51-2A natural convection environment. Thermal resistance data in this report is solely for a thermal performance comparison of one package to another in a standardized specified environment. It is not meant to predict the performance of a package in an application-specific environment.

4.1.3 Operating ranges
Table 10 provides the operating ranges of the i.MX RT1064 processors. For details on the chip's power structure, see the "Power Management Unit (PMU)" chapter of the i.MX RT1064 Reference Manual (IMXRT1064RM).
Table 10. Operating ranges

Parameter Description

Symbol

Operating Conditions

Min Typ Max1 Unit

Comment

Run Mode

VDD_SOC_IN

Overdrive

1.25 -- 1.3 V --

VDD_SOC_IN M7 core at 528 1.15 -- 1.3 V -- MHz

M7 core at 132 1.15 -- 1.3 MHz

M7 core at 24 0.925 -- 1.3 MHz

IDLE Mode

VDD_SOC_IN

M7 core

1.15 -- 1.3 V --

operation at 528

MHz or below

SUSPEND (DSM) Mode

VDD_SOC_IN

0.925 -- 1.3 V Refer to Table 13 Low power mode

current and power consumption

SNVS Mode

VDD_SOC_IN

-- 1.3 V --

Power for DCDC
VDD_HIGH internal Regulator

DCDC_IN VDD_HIGH_IN2

Backup battery supply range

VDD_SNVS_IN3

3.0 -- 3.6 V --

3.0 -- 3.6 V Must match the range of voltages

that the rechargeable backup

battery supports.

2.40 -- 3.6 V Can be combined with

VDD_HIGH_IN, if the system does

not require keeping real time and

other data on OFF state.

USB supply

USB_OTG1_VBUS

voltages

USB_OTG2_VBUS

4.40 -- 5.5 V -- 4.40 -- 5.5 V --

GPIO supplies

NVCC_GPIO NVCC_SD0
NVCC_SD1

3.0 3.3 3.6 V All digital I/O supplies

1.65

1.8

1.95

(NVCC_xxxx) must be powered (unless otherwise specified in this

3.0 3.3 3.6 V data sheet) under normal conditions whether the associated

1.65 1.8 1.95 V I/O pins are in use or not.

3.0 3.3 3.6 V

NVCC_EMC

1.65 1.8 1.95 V

3.0 3.3 3.6 V

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 3, 03/2021

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Electrical Characteristics

Table 10. Operating ranges (continued)

A/D converter

VDDA_ADC_3P3

3.0 3.3 3.6 V VDDA_ADC_3P3 must be powered even if the ADC is not used. VDDA_ADC_3P3 cannot be powered when the other SoC supplies (except VDD_SNVS_IN) are off.

System frequency FSYS/FBUS

/Bus frequency

600/ 528/ 24/ 150 132 24

MHz --

Temperature Operating Ranges

Junction temperature

Standard

85 oC See the application note, i.MX

Commercial

RT1064 Product Lifetime Usage

Estimates for information on

product lifetime (power-on years)

for this processor.

1 Applying the maximum voltage results in maximum power consumption and heat generation. NXP recommends a voltage set point = (Vmin + the supply tolerance). This result in an optimized power/speed ratio.
2 Applying the maximum voltage results in shorten lifetime. 3.6 V usage limited to < 1% of the use profile. Reset of profile limited to below 3.49 V.
3 In setting VDD_SNVS_IN voltage with regards to Charging Currents and RTC, refer to the i.MX RT1064 Hardware Development Guide (IMXRT1064HDG).

4.1.4 External clock sources
Each i.MX RT1064 processor has two external input system clocks: a low frequency (RTC_XTALI) and a high frequency (XTALI).
The RTC_XTALI is used for low-frequency functions. It supplies the clock for wake-up circuit, power-down real time clock operation, and slow system and watch-dog counters. The clock input can be connected to either external oscillator or a crystal using internal oscillator amplifier. Additionally, there is an internal ring oscillator, which can be used instead of the RTC_XTALI if accuracy is not important.
The system clock input XTALI is used to generate the main system clock. It supplies the PLLs and other peripherals. The system clock input can be connected to either external oscillator or a crystal using internal oscillator amplifier.
Table 11 shows the interface frequency requirements.
Table 11. External input clock frequency

Parameter Description

Symbol

Min

Typ

Max

Unit

RTC_XTALI Oscillator1,2

fckil

32.7683/32.0

kHz

XTALI Oscillator2,4

fxtal

MHz

1 External oscillator or a crystal with internal oscillator amplifier. 2 The required frequency stability of this clock source is application dependent. For recommendations, see the Hardware
Development Guide for i.MX RT1064 Crossover Processors (IMXRT1064HDG). 3 Recommended nominal frequency 32.768 kHz. 4 External oscillator or a fundamental frequency crystal with internal oscillator amplifier.

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 3, 03/2021

NXP Semiconductors

Electrical Characteristics
The typical values shown in Table 11 are required for use with NXP SDK to ensure precise time keeping and USB operation. For RTC_XTALI operation, two clock sources are available.
� On-chip 40 kHz ring oscillator--this clock source has the following characteristics: -- Approximately 25 �A more Idd than crystal oscillator -- Approximately �50% tolerance -- No external component required -- Starts up quicker than 32 kHz crystal oscillator
� External crystal oscillator with on-chip support circuit: -- At power up, ring oscillator is utilized. After crystal oscillator is stable, the clock circuit switches over to the crystal oscillator automatically. -- Higher accuracy than ring oscillator -- If no external crystal is present, then the ring oscillator is utilized
The decision of choosing a clock source should be taken based on real-time clock use and precision time-out.

4.1.5 Maximum supply currents

The data shown in Table 12 represent a use case designed specifically to show the maximum current consumption possible. All cores are running at the defined maximum frequency and are limited to L1 cache accesses only to ensure no pipeline stalls. Although a valid condition, it would have a very limited practical use case, if at all, and be limited to an extremely low duty cycle unless the intention were to specifically show the worst case power consumption.
See the i.MX RT1064 Power Consumption Measurement Application Note for more details on typical power consumption under various use case definitions.
Table 12. Maximum supply currents

DCDC_IN

Power Rail

VDD_HIGH_IN
VDD_SNVS_IN
USB_OTG1_VBUS USB_OTG2_VBUS
VDDA_ADC_3P3

Conditions

Max Current

Unit

Max power for chip at 95 oC with core

110

mark run on FlexRAM

Include internal loading in analog

250

25 mA for each active USB interface

3.3 V power supply for 12-bit ADC, 600

A typical, 750 A max, for each ADC.

100 Ohm max loading for touch panel,

cause 33 mA current.

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 3, 03/2021

NXP Semiconductors

Electrical Characteristics
Power Rail NVCC_GPIO NVCC_SD0 NVCC_SD1 NVCC_EMC

Table 12. Maximum supply currents (continued)

Conditions

Max Current

Unit

Imax = N x C x V x (0.5 x F) Where: N--Number of IO pins supplied by the power line C--Equivalent external capacitive load V--IO voltage (0.5 x F)--Data change rate. Up to 0.5 of the clock rate (F) In this equation, Imax is in Amps, C in Farads, V in Volts, and F in Hertz.

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 3, 03/2021

NXP Semiconductors

Electrical Characteristics

4.1.6 Low power mode supply currents
Table 13 shows the current core consumption (not including I/O) of i.MX RT1064 processors in selected low power modes.
Table 13. Low power mode current and power consumption

Mode

Test Conditions

Supply

Typical1 Units

SYSTEM IDLE � LDO_2P5 set to 2.5 V, LDO_1P1 set to 1.1 V

DCDC_IN (3.3 V)

4.04

� CPU in WFI, CPU clock gated � 24 MHz XTAL is ON

VDD_HIGH_IN (3.3 V)

7.66

� System PLL is active, other PLLs are power down VDD_SNVS_IN (3.3 V) � Peripheral clock gated, but remain powered

0.032

Total

38.72

LOW POWER IDLE � LDO_2P5 and LDO_1P1 are set to Weak mode

DCDC_IN (3.3 V)

1.11

� WFI, half FlexRAM power down in power gate mode

VDD_HIGH_IN (3.3 V)

0.309

� All PLLs are power down � 24 MHz XTAL is off, 24 MHz RCOSC used as

VDD_SNVS_IN (3.3 V) 0.048

clock source

Total

4.84

� Peripheral clock gated, but remain powered

SUSPEND (DSM)

� LDO_2P5 and LDO_1P1 are shut off � CPU in Power Gate mode � All PLLs are power down � 24 MHz XTAL is off, 24 MHz RCOSC is off � All clocks are shut off, except 32 kHz RTC � Peripheral clock gated, but remain powered

DCDC_IN (3.3 V)

0.19

VDD_HIGH_IN (3.3 V)

0.029

VDD_SNVS_IN (3.3 V) 0.020

Total

0.789

SNVS (RTC)

� All SOC digital logic, analog module are shut off

DCDC_IN (0 V)

� 32 kHz RTC is alive

VDD_HIGH_IN (0 V)

VDD_SNVS_IN (3.3 V)

0.02

Total

0.066

1 The typical values shown here are for information only and are not guaranteed. These values are average values measured on a typical process wafer at 25oC.

4.1.7 USB PHY current consumption

4.1.7.1 Power down mode
In power down mode, everything is powered down, including the USB VBUS valid detectors in typical condition. Table 14 shows the USB interface current consumption in power down mode.
Table 14. USB PHY current consumption in power down mode

Current

VDD_USB_CAP (3.0 V) 5.1 A

VDD_HIGH_CAP (2.5 V) 1.7 A

NVCC_PLL (1.1 V) < 0.5 A

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 3, 03/2021

NXP Semiconductors

Electrical Characteristics
NOTE The currents on the VDD_HIGH_CAP and VDD_USB_CAP were identified to be the voltage divider circuits in the USB-specific level shifters.
4.2 System power and clocks
This section provide the information about the system power and clocks.
4.2.1 Power supplies requirements and restrictions
The system design must comply with power-up sequence, power-down sequence, and steady state guidelines as described in this section to guarantee the reliable operation of the device. Any deviation from these sequences may result in the following situations:
� Excessive current during power-up phase � Prevention of the device from booting � Irreversible damage to the processor (worst-case scenario)
4.2.1.1 Power-up sequence
The below restrictions must be followed: � VDD_SNVS_IN supply must be turned on before any other power supply or be connected (shorted) with VDD_HIGH_IN supply. � If a coin cell is used to power VDD_SNVS_IN, then ensure that it is connected before any other supply is switched on. � When internal DCDC is enabled, external delay circuit is required to delay the "DCDC_PSWITCH" signal 1 ms after DCDC_IN is stable. � Need to ensure DCDC_IN ramps to 3.0 V within 0.2 x RC, RC is from external delay circuit used for DCDC_PSWITCH and must be longer than 1 ms. � POR_B should be held low during the entire power up sequence.
NOTE The POR_B input (if used) must be immediately asserted at power-up and remain asserted until after the last power rail reaches its working voltage. In the absence of an external reset feeding the POR_B input, the internal POR module takes control. See the i.MX RT1064 Reference Manual (IMXRT1064RM) for further details and to ensure that all necessary requirements are being met.
NOTE Need to ensure that there is no back voltage (leakage) from any supply on the board towards the 3.3 V supply (for example, from the external components that use both the 1.8 V and 3.3 V supplies).

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Electrical Characteristics
NOTE USB_OTG1_VBUS, USB_OTG2_VBUS, and VDDA_ADC_3P3 are not part of the power supply sequence and may be powered at any time.
4.2.1.2 Power-down sequence
The following restrictions must be followed: � VDD_SNVS_IN supply must be turned off after any other power supply or be connected (shorted) with VDD_HIGH_IN supply. � If a coin cell is used to power VDD_SNVS_IN, then ensure that it is removed after any other supply is switched off.
4.2.1.3 Power supplies usage
All I/O pins should not be externally driven while the I/O power supply for the pin (NVCC_xxx) is OFF. This can cause internal latch-up and malfunctions due to reverse current flows. For information about I/O power supply of each pin, see "Power Rail" columns in pin list tables of Section 7, Package information and contact assignments."
4.2.2 Integrated LDO voltage regulator parameters
Various internal supplies can be powered ON from internal LDO voltage regulators. All the supply pins named *_CAP must be connected to external capacitors. The on-board LDOs are intended for internal use only and should not be used to power any external circuitry. See the i.MX RT1064 Reference Manual (IMXRT1064RM) for details on the power tree scheme.
NOTE The *_CAP signals should not be powered externally. These signals are intended for internal LDO operation only.
4.2.2.1 Digital regulators (LDO_SNVS)
There are one digital LDO regulator ("Digital", because of the logic loads that they drive, not because of their construction). The advantages of the regulator is to reduce the input supply variation because of its input supply ripple rejection and its on-die trimming. This translates into more stable voltage for the on-chip logics.
The regulator has two basic modes: � Power Gate. The regulation FET is switched fully off limiting the current draw from the supply. The analog part of the regulator is powered down here limiting the power consumption. � Analog regulation mode. The regulation FET is controlled such that the output voltage of the regulator equals the target voltage.
For additional information, see the i.MX RT1064 Reference Manual (IMXRT1064RM).

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 3, 03/2021

NXP Semiconductors

Electrical Characteristics
4.2.2.2 Regulators for analog modules
4.2.2.2.1 LDO_1P1
The LDO_1P1 regulator implements a programmable linear-regulator function from VDD_HIGH_IN (see Table 10 for minimum and maximum input requirements). Typical Programming Operating Range is 1.0 V to 1.2 V with the nominal default setting as 1.1 V. The LDO_1P1 supplies the USB Phy, and PLLs. A programmable brown-out detector is included in the regulator that can be used by the system to determine when the load capability of the regulator is being exceeded to take the necessary steps. Current-limiting can be enabled to allow for in-rush current requirements during start-up, if needed. Active-pull-down can also be enabled for systems requiring this feature.
For information on external capacitor requirements for this regulator, see the Hardware Development Guide for i.MX RT1064 Crossover Processors (IMXRT1064HDG).
For additional information, see the i.MX RT1064 Reference Manual (IMXRT1064RM).
4.2.2.2.2 LDO_2P5
The LDO_2P5 module implements a programmable linear-regulator function from VDD_HIGH_IN (see Table 10 for minimum and maximum input requirements). Typical Programming Operating Range is 2.25 V to 2.75 V with the nominal default setting as 2.5 V. LDO_2P5 supplies the USB PHY, E-fuse module, and PLLs. A programmable brown-out detector is included in the regulator that can be used by the system to determine when the load capability of the regulator is being exceeded, to take the necessary steps. Current-limiting can be enabled to allow for in-rush current requirements during start-up, if needed. Active-pull-down can also be enabled for systems requiring this feature. An alternate self-biased low-precision weak-regulator is included that can be enabled for applications needing to keep the output voltage alive during low-power modes where the main regulator driver and its associated global bandgap reference module are disabled. The output of the weak-regulator is not programmable and is a function of the input supply as well as the load current. Typically, with a 3 V input supply the weak-regulator output is 2.525 V and its output impedance is approximately 40 .
For information on external capacitor requirements for this regulator, see the Hardware Development Guide for i.MX RT1064 Crossover Processors (IMXRT1064HDG).
For additional information, see the i.MX RT1064 Reference Manual (IMXRT1064RM).
4.2.2.2.3 LDO_USB
The LDO_USB module implements a programmable linear-regulator function from the USB VUSB voltages (4.4 V�5.5 V) to produce a nominal 3.0 V output voltage. A programmable brown-out detector is included in the regulator that can be used by the system to determine when the load capability of the regulator is being exceeded, to take the necessary steps. This regulator has a built in power-mux that allows the user to select to run the regulator from either USB VBUS supply, when both are present. If only one of the USB VBUS voltages is present, then, the regulator automatically selects this supply. Current limit is also included to help the system meet in-rush current targets.
For information on external capacitor requirements for this regulator, see the Hardware Development Guide for i.MX RT1064 Crossover Processors (IMXRT1064HDG).

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For additional information, see the i.MX RT1064 Reference Manual (IMXRT1064RM).
4.2.2.2.4 DCDC DCDC can be configured to operate on power-save mode when the load current is less than 50 mA. During the power-save mode, the converter operates with reduced switching frequency in PFM mode and with a minimum quiescent current to maintain high efficiency. DCDC can detect the peak current in the P-channel switch. When the peak current exceeds the threshold, DCDC will give an alert signal, and the threshold can be configured. By this way, DCDC can roughly detect the current loading. DCDC also includes the following protection functions:
� Over current protection. In run mode, DCDC shuts down when detecting abnormal large current in the P-type power switch.
� Over voltage protection. DCDC shuts down when detecting the output voltage is too high. � Low voltage detection. DCDC shuts down when detecting the input voltage is too low. For additional information, see the i.MX RT1064 Reference Manual (IMXRT1064RM).
4.2.3 PLL's electrical characteristics
This section provides PLL electrical characteristics.
4.2.3.1 Audio/Video PLL's electrical parameters

Table 15. Audio/Video PLL's electrical parameters

Parameter Clock output range
Reference clock Lock time

Value 650 MHz ~1.3 GHz
24 MHz < 11250 reference cycles

4.2.3.2 System PLL

Table 16. System PLL's electrical parameters

Parameter Clock output range
Reference clock Lock time

Value 528 MHz PLL output
24 MHz < 11250 reference cycles

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4.2.3.3 Ethernet PLL

Table 17. Ethernet PLL's electrical parameters

Parameter Clock output range
Reference clock Lock time

Value 1 GHz 24 MHz < 11250 reference cycles

4.2.3.4 USB PLL

Table 18. USB PLL's electrical parameters

Parameter Clock output range
Reference clock Lock time

Value 480 MHz PLL output
24 MHz < 383 reference cycles

4.2.3.5 Arm PLL

Table 19. Arm PLL's electrical parameters

Parameter Clock output range
Reference clock Lock time

Value 648 MHz ~ 1296 MHz
24 MHz < 2250 reference cycles

4.2.4 On-chip oscillators

4.2.4.1 OSC24M
This block implements an amplifier that when combined with a suitable quartz crystal and external load capacitors implement an oscillator. The oscillator is powered from NVCC_PLL.
The system crystal oscillator consists of a Pierce-type structure running off the digital supply. A straight forward biased-inverter implementation is used.
4.2.4.2 OSC32K
This block implements an amplifier that when combined with a suitable quartz crystal and external load capacitors implement a low power oscillator. It also implements a power mux such that it can be powered from either a ~3 V backup battery (VDD_SNVS_IN) or VDD_HIGH_IN such as the oscillator consumes

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power from VDD_HIGH_IN when that supply is available and transitions to the backup battery when VDD_HIGH_IN is lost.
In addition, if the clock monitor determines that the OSC32K is not present, then the source of the 32 K will automatically switch to a crude internal ring oscillator. The frequency range of this block is approximately 10�45 kHz. It highly depends on the process, voltage, and temperature.
The OSC32k runs from VDD_SNVS_CAP supply, which comes from the VDD_HIGH_IN/VDD_SNVS_IN. The target battery is a ~3 V coin cell. Proper choice of coin cell type is necessary for chosen VDD_HIGH_IN range. Appropriate series resistor (Rs) must be used when connecting the coin cell. Rs depends on the charge current limit that depends on the chosen coin cell. For example, for Panasonic ML621:
� Average Discharge Voltage is 2.5 V � Maximum Charge Current is 0.6 mA
For a charge voltage of 3.2 V, Rs = (3.2-2.5)/0.6 m = 1.17 k.
Table 20. OSC32K main characteristics

Min

Typ

Max

Comments

Fosc

-- 32.768 KHz

-- This frequency is nominal and determined mainly by the crystal selected. 32.0 K would work as well.

Current consumption --

4 A

-- The 4 A is the consumption of the oscillator alone (OSC32k). Total supply consumption will depend on what the digital portion of the RTC consumes. The ring oscillator consumes 1 A when ring oscillator is inactive, 20 A when the ring oscillator is running. Another 1.5 A is drawn from vdd_rtc in the power_detect block. So, the total current is 6.5 A on vdd_rtc when the ring oscillator is not running.

Bias resistor

-- 14 M

-- This integrated bias resistor sets the amplifier into a high gain state. Any leakage through the ESD network, external board leakage, or even a scope probe that is significant relative to this value will debias the amp. The debiasing will result in low gain, and will impact the circuit's ability to start up and maintain oscillations.

Crystal Properties

Cload

10 pF

-- Usually crystals can be purchased tuned for different Cloads. This Cload value is typically 1/2 of the capacitances realized on the PCB on either side of the quartz. A higher Cload will decrease oscillation margin, but increases current oscillating through the crystal.

ESR

50 k 100 k Equivalent series resistance of the crystal. Choosing a crystal with a higher

value will decrease the oscillating margin.

4.3 I/O parameters
This section provide parameters on I/O interfaces.

4.3.1 I/O DC parameters
This section includes the DC parameters of the following I/O types:

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� XTALI and RTC_XTALI (Clock Inputs) DC Parameters � General Purpose I/O (GPIO) � LVDS I/O DC Parameters
NOTE The term `NVCC_XXXX' in this section refers to the associated supply rail of an input or output.

Figure 3. Circuit for parameters Voh and Vol for I/O cells

4.3.1.1 XTALI and RTC_XTALI (clock inputs) DC parameters Table 21 shows the DC parameters for the clock inputs.
Table 21. XTALI and RTC_XTALI DC parameters1

Parameter

Symbol Test Conditions

XTALI high-level DC input voltage

Vih

XTALI low-level DC input voltage

Vil

RTC_XTALI high-level DC input voltage

Vih

RTC_XTALI low-level DC input voltage

Vil

1 The DC parameters are for external clock input only.

Min 0.8 x NVCC_PLL
0 0.8 0

Max

Unit

NVCC_PLL

0.2

1.1

0.2

4.3.1.2 Single voltage general purpose I/O (GPIO) DC parameters
Table 22 shows DC parameters for GPIO pads. The parameters in Table 22 are guaranteed per the operating ranges in Table 10, unless otherwise noted.

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Table 22. Single voltage GPIO DC parameters

Parameter

Symbol

Test Conditions

Min

Max

Units

High-level output voltage1 Low-level output voltage1

VOH

Ioh= -0.1mA (ipp_dse=001,010) NVCC_XXXX-

�

Ioh= -1mA

0.15

(ipp_dse=011,100,101,110,111)

VOL

Iol= 0.1mA (ipp_dse=001,010)

�

Iol= 1mA

(ipp_dse=011,100,101,110,111)

0.15

High-level output current

IOH

VDDE = 3.3 V, VOH = VDDE - 0.45

V, ipp_dse as follows:

001

010

011

110

101

110

111

mA
-1 -1 -2 -2 -2 -4 -4

Low-level output current

IOL

High-Level input voltage1,2

VIH

Low-Level input voltage1,2

VIL

VDDE = 3.3 V, VOL = 0.45 V, ipp_dse as follows: 001 010 011 110 101 110 111
--
--

1 1 2 2 2 4 4

0.7 x

NVCC_XXXX V

NVCC_XXXX

0.3 x

NVCC_XXXX

Input Hysteresis (NVCC_XXXX= 1.8V)

VHYS_LowVDD

NVCC_XXXX=1.8V

250

Input Hysteresis (NVCC_XXXX=3.3V) Schmitt trigger VT+2,3
Schmitt trigger VT-2,3

VHYS_HighVDD VTH+ VTH-

NVCC_XXXX=3.3V -- --

250

0.5 x

NVCC_XXXX

0.5 x

NVCC_XXXX

Pull-up resistor (22_k PU)

RPU_22K

Vin=0V

212

Pull-up resistor (22_k PU)

RPU_22K

Vin=NVCC_XXXX

Pull-up resistor (47_k PU)

RPU_47K

Vin=0V

100

Pull-up resistor (47_k PU)

RPU_47K

Vin=NVCC_XXXX

Pull-up resistor (100_k PU) RPU_100K

Vin=0V

Pull-up resistor (100_k PU) RPU_100K

Vin=NVCC_XXXX

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Table 22. Single voltage GPIO DC parameters (continued)

Parameter

Symbol

Test Conditions

Min

Max

Units

Pull-down resistor (100_k PD)

RPD_100K

Vin=NVCC_XXXX

Pull-down resistor (100_k PD)

RPD_100K

Vin=0V

Input current (no PU/PD)

IIN

VI = 0, VI = NVCC_XXXX

-1

Keeper Circuit Resistance

R_Keeper VI =0.3 x NVCC_XXXX, VI = 0.7 x

105

NVCC_XXXX

175

1 Overshoot and undershoot conditions (transitions above NVCC_XXXX and below GND) on switching pads must be held below 0.6 V, and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/ undershoot must be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other methods. Non-compliance to this specification may affect device reliability or cause permanent damage to the device.
2 To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC level through to the target DC level, Vil or Vih. Monotonic input transition time is from 0.1 ns to 1 s.
3 Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.

4.3.1.3 LVDS I/O DC parameters
The LVDS interface complies with TIA/EIA 644-A standard. See TIA/EIA STANDARD 644-A, "Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits" for details.
Table 23 shows the Low Voltage Differential Signaling (LVDS) I/O DC parameters.
Table 23. LVDS I/O DC characteristics1

Parameter

Symbol Test Conditions

Output Differential Voltage

VOD

Rload-100 Diff

Output High Voltage

VOH

IOH = 0 mA

Output Low Voltage

VOL

IOL = 0 mA

Offset Voltage

VOS

1 Note: The LVDS interface is limited to CCM_CLK1_P and CCM_CLK1_N.

Min 250 1.25 0.9 1.125

Typ 350 1.375 1.025 1.2

Max

Unit

450

1.6

1.25

1.375

4.3.2 I/O AC parameters
This section includes the AC parameters of the following I/O types: � General Purpose I/O (GPIO)
Figure 4 shows load circuit for output, and Figure 5 show the output transition time waveform.

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FUronmdeOr uTtepsutt

Test Point CL

CL includes package, probe and fixture capacitance Figure 4. Load circuit for output

Electrical Characteristics

Output (at pad)

80%

20%

Figure 5. Output transition time waveform

OVDD 80%
20%0 V

4.3.2.1 General purpose I/O AC parameters
The I/O AC parameters for GPIO in slow and fast modes are presented in the Table 24 and Table 25, respectively. Note that the fast or slow I/O behavior is determined by the appropriate control bits in the IOMUXC control registers.
Table 24. General purpose I/O AC parameters 1.8 V mode

Parameter

Symbol

Test Condition

Min Typ

Max

Unit

Output Pad Transition Times, rise/fall (Max Drive, ipp_dse=111)

tr, tf

15 pF Cload, slow slew rate 15 pF Cload, fast slew rate

2.72/2.79 1.51/1.54

Output Pad Transition Times, rise/fall (High Drive, ipp_dse=101)

tr, tf

15 pF Cload, slow slew rate 15 pF Cload, fast slew rate

3.20/3.36 1.96/2.07

Output Pad Transition Times, rise/fall (Medium Drive, ipp_dse=100)

tr, tf

15 pF Cload, slow slew rate 15 pF Cload, fast slew rate

3.64/3.88 2.27/2.53

Output Pad Transition Times, rise/fall (Low Drive. ipp_dse=011)

tr, tf

15 pF Cload, slow slew rate 15 pF Cload, fast slew rate

4.32/4.50 3.16/3.17

Input Transition Times1

trm

1 Hysteresis mode is recommended for inputs with transition times greater than 25 ns.

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Table 25. General purpose I/O AC parameters 3.3 V mode

Parameter

Symbol

Test Condition

Min Typ

Max

Unit

Output Pad Transition Times, rise/fall (Max Drive, ipp_dse=101)

tr, tf

15 pF Cload, slow slew rate 15 pF Cload, fast slew rate

1.70/1.79 1.06/1.15

Output Pad Transition Times, rise/fall (High Drive, ipp_dse=011)

tr, tf

15 pF Cload, slow slew rate 15 pF Cload, fast slew rate

2.35/2.43 1.74/1.77

Output Pad Transition Times, rise/fall (Medium Drive, ipp_dse=010)

tr, tf

15 pF Cload, slow slew rate 15 pF Cload, fast slew rate

3.13/3.29 2.46/2.60

Output Pad Transition Times, rise/fall (Low Drive. ipp_dse=001)

tr, tf

15 pF Cload, slow slew rate 15 pF Cload, fast slew rate

5.14/5.57 4.77/5.15

Input Transition Times1

trm

1 Hysteresis mode is recommended for inputs with transition times greater than 25 ns.

4.3.3 Output buffer impedance parameters
This section defines the I/O impedance parameters of the i.MX RT1064 processors for the following I/O types:
� Single Voltage General Purpose I/O (GPIO)
NOTE GPIO I/O output driver impedance is measured with "long" transmission line of impedance Ztl attached to I/O pad and incident wave launched into transmission line. Rpu/Rpd and Ztl form a voltage divider that defines specific voltage of incident wave relative to NVCC_XXXX. Output driver impedance is calculated from this voltage divider (see Figure 6).

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ipp_do predriver
U,(V) VDD

OVDD PMOS (Rpu)
pad
NMOS (Rpd) OVSS

Electrical Characteristics

Ztl , L = 20 inches

Cload = 1p

Vin (do)

0 U,(V)
OVDD
Vref

Vref1

Vref2

t,(ns) Vout (pad)

0 Rpu =

Vovdd - Vref1 Vref1

Ztl

Rpd =

Vref2

Vovdd - Vref2

t,(ns) Ztl

Figure 6. Impedance matching load for measurement

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4.3.3.1 Single voltage GPIO output buffer impedance Table 26 shows the GPIO output buffer impedance (NVCC_XXXX 1.8 V).
Table 26. GPIO output buffer average impedance (NVCC_XXXX 1.8 V)

Parameter Symbol
Output Driver Rdrv Impedance

Drive Strength (DSE)
001 010 011 100 101 110 111

Typ Value Unit

260

130

Table 27 shows the GPIO output buffer impedance (NVCC_XXXX 3.3 V).
Table 27. GPIO output buffer average impedance (NVCC_XXXX 3.3 V)

Parameter Symbol
Output Driver Rdrv Impedance

Drive Strength (DSE)
001 010 011 100 101 110 111

Typ Value Unit

157

4.4 System modules
This section contains the timing and electrical parameters for the modules in the i.MX RT1064 processor.

4.4.1 Reset timings parameters
Figure 7 shows the reset timing and Table 28 lists the timing parameters.

POR_B (Input)

CC1

Figure 7. Reset timing diagram

Table 28. Reset timing parameters

Parameter

CC1 Duration of POR_B to be qualified as valid.

Min Max 1--

Unit
RTC_XTALI cycle

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4.4.2 WDOG reset timing parameters
Figure 8 shows the WDOG reset timing and Table 29 lists the timing parameters.

WDOGn_B (Output)

CC3
Figure 8. WDOGn_B timing diagram

Table 29. WDOGn_B timing parameters

Parameter

Min Max

Unit

CC3 Duration of WDOGn_B Assertion

RTC_XTALI cycle

NOTE
RTC_XTALI is approximately 32 kHz. RTC_XTALI cycle is one period or approximately 30 s.
NOTE
WDOGn_B output signals (for each one of the Watchdog modules) do not have dedicated pins, but are muxed out through the IOMUX. See the IOMUX manual for detailed information.

4.4.3 SCAN JTAG Controller (SJC) timing parameters
Figure 9 depicts the SJC test clock input timing. Figure 10 depicts the SJC boundary scan timing. Figure 11 depicts the SJC test access port. Signal parameters are listed in Table 30.

JTAG_TCK (Input)

VIH SJ3

SJ2
VM VIL

SJ1 SJ2 VM
SJ3

Figure 9. Test clock input timing diagram

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JTAG_TCK (Input)
Data Inputs
Data Outputs
Data Outputs
Data Outputs

VIL SJ6 SJ7

VIH

SJ4

SJ5

Input Data Valid

Output Data Valid

SJ6 Output Data Valid
Figure 10. Boundary Scan (JTAG) timing diagram

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JTAG_TCK (Input)
JTAG_TDI JTAG_TMS
(Input) JTAG_TDO
(Output)
JTAG_TDO (Output)
JTAG_TDO (Output)

VIL SJ10 SJ11

VIH

SJ8

SJ9

Input Data Valid

Output Data Valid

SJ10 Output Data Valid
Figure 11. Test access port timing diagram

JTAG_TCK (Input)

JTAG_TRST_B

SJ13

(Input)

SJ12

Electrical Characteristics

Figure 12. JTAG_TRST_B timing diagram

Table 30. JTAG timing

Parameter1,2

SJ0 JTAG_TCK frequency of operation 1/(3�TDC)1 SJ1 JTAG_TCK cycle time in crystal mode SJ2 JTAG_TCK clock pulse width measured at VM2 SJ3 JTAG_TCK rise and fall times SJ4 Boundary scan input data set-up time SJ5 Boundary scan input data hold time SJ6 JTAG_TCK low to output data valid SJ7 JTAG_TCK low to output high impedance SJ8 JTAG_TMS, JTAG_TDI data set-up time

All Frequencies

Min

Max

0.001

22.5

Unit
MHz ns ns ns ns ns ns ns ns

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Table 30. JTAG timing (continued)

Parameter1,2

SJ9 JTAG_TMS, JTAG_TDI data hold time SJ10 JTAG_TCK low to JTAG_TDO data valid SJ11 JTAG_TCK low to JTAG_TDO high impedance SJ12 JTAG_TRST_B assert time SJ13 JTAG_TRST_B set-up time to JTAG_TCK low 1 TDC = target frequency of SJC 2 VM = mid-point voltage

All Frequencies

Min

Max

100

4.4.4 Debug trace timing specifications

Table 31. Debug trace operating behaviors

Symbol T1 T2 T3 T4 T5 T6 T7 T8

Description ARM_TRACE_CLK frequency of operation ARM_TRACE_CLK period Low pulse width High pulse width Clock and data rise time Clock and data fall time Data setup Data hold

Min

Max

1/T1

0.7

Unit
ns ns ns ns ns
Unit MHz MHz
ns ns ns ns ns ns

!2-?42!#%?#,+

4
Figure 13. ARM_TRACE_CLK specifications

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ARM_TRACE_CLK ARM_TRACE0-3

Figure 14. Trace data specifications
4.5 External memory interface
The following sections provide information about external memory interfaces.

4.5.1 SEMC specifications
The following sections provide information on SEMC interface. Measurements are with a load of 15 pf and an input slew rate of 1 V/ns.

4.5.1.1 SEMC output timing There are ASYNC and SYNC mode for SEMC output timing.

4.5.1.1.1 SEMC output timing in ASYNC mode Table 32 shows SEMC output timing in ASYNC mode.
Table 32. SEMC output timing in ASYNC mode

Symbol

Parameter

Min.

Max.

Unit

Comment

Frequency of operation

166

MHz

TCK

Internal clock period

TAVO

Address output valid time

ns These timing parameters

TAHO

Address output hold time

(TCK - 2) 1

apply to Address and ADV# for NOR/PSRAM in ASYNC

TADVL ADV# low time

(TCK - 1) 2

mode.

TDVO TDHO TWEL

Data output valid time Data output hold time WE# low time

ns These timing parameters

(TCK - 2) 3

apply to Data/CLE/ALE and WE# for NAND, apply to

(TCK - 1) 4

ns Data/DM/CRE for NOR/PSRAM, apply to

Data/DCX and WRX for DBI

interface.

1 Address output hold time is configurable by SEMC_*CR0.AH. AH field setting value is 0x0 in above table. When AH is set with value N, TAHO min time should be ((N + 1) x TCK). See the i.MX RT1064 Reference Manual (IMXRT1064RM) for more detail about SEMC_*CR0.AH register field.

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2 ADV# low time is configurable by SEMC_*CR0.AS. AS field setting value is 0x0 in above table. When AS is set with value N, TADL min time should be ((N + 1) x TCK - 1). See the i.MX RT1064 Reference Manual (IMXRT1064RM) for more detail about SEMC_*CR0.AS register field.
3 Data output hold time is configurable by SEMC_*CR0.WEH. WEH field setting value is 0x0 in above table. When WEH is set with value N, TDHO min time should be ((N + 1) x TCK). See the i.MX RT1064 Reference Manual (IMXRT1064RM) for more detail about SEMC_*CR0.WEH register field.
4 WE# low time is configurable by SEMC_*CR0.WEL. WEL field setting value is 0x0 in above table. When WEL is set with value N, TWEL min time should be ((N + 1) x TCK - 1). See the i.MX RT1064 Reference Manual (IMXRT1064RM) for more detail about SEMC_*CR0.WEL register field.
Figure 15 shows the output timing in ASYNC mode.

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4#+ 4!6/

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Figure 15. SEMC output timing in ASYNC mode

4.5.1.1.2 SEMC output timing in SYNC mode Table 33 shows SEMC output timing in SYNC mode.
Table 33. SEMC output timing in SYNC mode

Symbol
TCK TDVO TDHO

Parameter Frequency of operation Internal clock period Data output valid time Data output hold time

Min. -- 6 -- -1

Max. 166 --
1 --

Unit MHz ns ns ns

Comment
--
--
These timing parameters apply to Address/Data/DM/CKE/control signals with SEMC_CLK for SDRAM.

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Figure 16 shows the output timing in SYNC mode.

Electrical Characteristics

3%-#?#,+ $!4!

4$6/

4$(/
$

Figure 16. SEMC output timing in SYNC mode

4.5.1.2 SEMC input timing There are ASYNC and SYNC mode for SEMC input timing.

4.5.1.2.1 SEMC input timing in ASYNC mode Table 34 shows SEMC output timing in ASYNC mode.
Table 34. SEMC output timing in ASYNC mode

Symbol TIS TIH

Parameter Data input setup Data input hold

Min.

Max.

Unit

Comment

8.67

ns For NAND/NOR/PSRAM/DBI,

these timing parameters apply to RE# and Read Data.

Figure 17 shows the input timing in ASYNC mode.

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.!.$NON
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Figure 17. SEMC input timing in ASYNC mode

4.5.1.2.2 SEMC input timing in SYNC mode Table 35 and Table 36 show SEMC input timing in SYNC mode.
Table 35. SEMC input timing in SYNC mode (SEMC_MCR.DQSMD = 0x0)

Symbol TIS TIH

Parameter Data input setup Data input hold

Min.

Max.

Unit

Comment

8.67

ns --

Table 36. SEMC input timing in SYNC mode (SEMC_MCR.DQSMD = 0x1)

Symbol

Parameter

Min.

TIS

Data input setup

0.6

TIH

Data input hold

Figure 18 shows the input timing in SYNC mode.

Max. -- --

Unit ns -- ns

Comment

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Electrical Characteristics

3%-#?#,+

$!4! 3%-#?$13

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Figure 18. SEMC input timing in SYNC mode

4.5.2 FlexSPI parameters
Measurements are with a load 15 pf and input slew rate of 1 V/ns.

4.5.2.1 FlexSPI input/read timing
There are four sources for the internal sample clock for FlexSPI read data:
� Dummy read strobe generated by FlexSPI controller and looped back internally
(FlexSPIn_MCR0[RXCLKSRC] = 0x0)
� Dummy read strobe generated by FlexSPI controller and looped back through the
DQS pad (FlexSPIn_MCR0[RXCLKSRC] = 0x1)
� Read strobe provided by memory device and input from DQS pad
(FlexSPIn_MCR0[RXCLKSRC] = 0x3)
The following sections describe input signal timing for each of these four internal sample clock sources.

4.5.2.1.1 SDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1
Table 37. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X0

Symbol
TIS TIH

Parameter Frequency of operation Setup time for incoming data Hold time for incoming data

Min

Max

Unit

MHz

8.67

Table 38. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X1

Symbol
TIS TIH

Parameter Frequency of operation Setup time for incoming data Hold time for incoming data

Min

Max

Unit

133

MHz

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SCK SIO[0:7]

TIS

TIH

TIS

TIH

Internal Sample Clock
Figure 19. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X0, 0X1
NOTE Timing shown is based on the memory generating read data on the SCK falling edge, and FlexSPI controller sampling read data on the falling edge.
4.5.2.1.2 SDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x3 There are two cases when the memory provides both read data and the read strobe in SDR mode:
� A1--Memory generates both read data and read strobe on SCK rising edge (or falling
edge)
� A2--Memory generates read data on SCK falling edge and generates read strobe on SCK rising edgeSCK rising edge

Table 39. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (case A1)

Symbol
TSCKD TSCKDQS TSCKD - TSCKDQS

Parameter
Frequency of operation Time from SCK to data valid Time from SCK to DQS Time delta between TSCKD and TSCKDQS

Value

Min

Max

166

-2

Unit
MHz ns ns ns

SCK SIO[0:7]
DQS

TSCKD TSCKDQS

Figure 20. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X3 (case A1)

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NOTE Timing shown is based on the memory generating read data and read strobe on the SCK rising edge. The FlexSPI controller samples read data on the DQS falling edge.

Table 40. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (case A2)

Symbol
TSCKD TSCKDQS TSCKD - TSCKDQS

Parameter
Frequency of operation Time from SCK to data valid Time from SCK to DQS Time delta between TSCKD and TSCKDQS

Value

Min -- -- -- -2

Max 166 -- -- 2

Unit
MHz ns ns ns

SCK SIO[0:7]
DQS

TSCKD

TSCKDQS

TSCKD

TSCKDQS

TSCKD

TSCKDQS

Internal Sample Clock
Figure 21. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X3 (case A2)
NOTE Timing shown is based on the memory generating read data on the SCK falling edge and read strobe on the SCK rising edge. The FlexSPI controller samples read data on a half cycle delayed DQS falling edge.

4.5.2.1.3 DDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1

Table 41. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0

Symbol
TIS TIH

Parameter Frequency of operation Setup time for incoming data Hold time for incoming data

Min

Max

8.67

Unit MHz ns ns

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Table 42. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x1

Symbol
TIS TIH

Parameter Frequency of operation Setup time for incoming data Hold time for incoming data

Min

Max

Unit MHz ns ns

SCLK SIO[0:7] Internal Sample Clock

TIS

TIH

TIS

TIH

Figure 22. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1
4.5.2.1.4 DDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x3
There are two cases when the memory provides both read data and the read strobe in DDR mode:
� B1--Memory generates both read data and read strobe on SCK edge � B2--Memory generates read data on SCK edge and generates read strobe on SCK2
edge

Table 43. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (case B1)

Symbol
TSCKD TSCKDQS TSCKD - TSCKDQS

Parameter Frequency of operation Time from SCK to data valid Time from SCK to DQS Time delta between TSCKD and TSCKDQS

Min -- -- -- -1

Max 166 -- -- 1

Unit MHz ns ns ns

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SCK SIO[0:7]
DQS

TSCKD TSCKDQS

Figure 23. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (case B1)

Table 44. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (case B2)

Symbol
TSCKD TSCKD - TSCKDQS

Parameter Frequency of operation Time from SCK to data valid Time delta between TSCKD and TSCKDQS

Min -- -- -1

Max 166 -- 1

Unit MHz ns ns

SCK SIO[0:7]

TSCKD

SCK2 DQS

TSCK2DQS

Figure 24. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (case B2)

4.5.2.2 FlexSPI output/write timing
The following sections describe output signal timing for the FlexSPI controller including control signals and data outputs.

4.5.2.2.1

SDR mode

Table 45. FlexSPI output timing in SDR mode

Symbol
Tck TDVO TDHO

Parameter Frequency of operation SCK clock period Output data valid time Output data hold time

Min -- 6.0 -- -1

1661 -- 1 --

Max

Unit MHz ns ns ns

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Table 45. FlexSPI output timing in SDR mode (continued)

Symbol

Parameter

Min

Max

Unit

TCSS

Chip select output setup time

3 x TCK - 1

TCSH

Chip select output hold time

3 x TCK + 2

1 The actual maximum frequency supported is limited by the FlexSPIn_MCR0[RXCLKSRC] configuration used. Please refer to the FlexSPI SDR input timing

specifications.

NOTE
TCSS and TCSH are configured by the FlexSPIn_FLSHAxCR1
register, the default values are shown above. Please refer to the i.MX RT1064 Reference Manual (IMXRT1064RM) for more details.

SCK

T CSS

T CK

TCSH

TDVO

SIO[0:7]

TDHO

Figure 25. FlexSPI output timing in SDR mode

4.5.2.2.2

SDR mode

Table 46. FlexSPI output timing in SDR mode

Symbol

Parameter

Min

Max

Unit

Frequency of operation1

166

MHz

Tck

SCK clock period (FlexSPIn_MCR0[RXCLKSRC] = 0x0) 6.0

TDVO

Output data valid time

2.2

TDHO

Output data hold time

0.8

TCSS

Chip select output setup time

3 x TCK /2 - 0.7 --

TCSH

Chip select output hold time

3 x TCK /2 + 0.8 --

1 The actual maximum frequency supported is limited by the FlexSPIn_MCR0[RXCLKSRC] configuration used. Please refer to the FlexSPI SDR input timing

specifications.

NOTE
TCSS and TCSH are configured by the FlexSPIn_FLSHAxCR1
register, the default values are shown above. Please refer to the i.MX RT1064 Reference Manual (IMXRT1064RM) for more details.

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SCK
T CSS
CS

TDVO

T CK

TDVO

TCSH

SIO[0:7]

TDHO

Figure 26. FlexSPI output timing in DDR mode

4.6 Display and graphics
The following sections provide information on display and graphic interfaces.

4.6.1 CMOS Sensor Interface (CSI) timing parameters
The following sections describe the CSI timing in gated and ungated clock modes.
4.6.1.0.1 Gated clock mode timing
Figure 27 and Figure 28 shows the gated clock mode timings for CSI, and Table 47 describes the timing parameters (P1�P7) shown in the figures. A frame starts with a rising/falling edge on CSI_VSYNC (VSYNC), then CSI_HSYNC (HSYNC) is asserted and holds for the entire line. The pixel clock, CSI_PIXCLK (PIXCLK), is valid as long as HSYNC is asserted.

CSI_VSYNC CSI_HSYNC CSI_PIXCLK

P1 P2 P3 P4

P7 P5 P6

CSI_DATA[23:00]

Figure 27. CSI Gated clock mode--sensor data at falling edge, latch data at rising edge

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CSI_VSYNC CSI_HSYNC CSI_PIXCLK

P1 P2

P7 P6 P5

P3 P4

CSI_DATA[23:00]

Figure 28. CSI Gated clock mode--sensor data at rising edge, latch data at falling edge

Table 47. CSI gated clock mode timing parameters

Parameter

P1 CSI_VSYNC to CSI_HSYNC time P2 CSI_HSYNC setup time P3 CSI DATA setup time P4 CSI DATA hold time P5 CSI pixel clock high time P6 CSI pixel clock low time P7 CSI pixel clock frequency

Symbol tV2H tHsu tDsu tDh tCLKh tCLKl fCLK

Min. 33.5
1 1 1 3.75 3.75 --

Max. -- -- -- -- -- -- 80

Units ns ns ns ns ns ns MHz

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4.6.1.0.2 Ungated clock mode timing
Figure 29 shows the ungated clock mode timings of CSI, and Table 48 describes the timing parameters (P1�P6) that are shown in the figure. In ungated mode the CSI_VSYNC and CSI_PIXCLK signals are used, and the CSI_HSYNC signal is ignored.

CSI_VSYNC P1

CSI_PIXCLK

P2 P3

P6 P4 P5

CSI_DATA[23:00]

Figure 29. CSI ungated clock mode--sensor data at falling edge, latch data at rising edge

Table 48. CSI ungated clock mode timing parameters

Parameter

P1 CSI_VSYNC to pixel clock time P2 CSI DATA setup time P3 CSI DATA hold time P4 CSI pixel clock high time P5 CSI pixel clock low time P6 CSI pixel clock frequency

Symbol tVSYNC
tDsu tDh tCLKh tCLKl fCLK

Min. 33.5
1 1 3.75 3.75 --

Max. -- -- -- -- -- 80

Units ns ns ns ns ns MHz

The CSI enables the chip to connect directly to external CMOS image sensors, which are classified as dumb or smart as follows:
� Dumb sensors only support traditional sensor timing (vertical sync (VSYNC) and horizontal sync (HSYNC)) and output-only Bayer and statistics data.
� Smart sensors support CCIR656 video decoder formats and perform additional processing of the image (for example, image compression, image pre-filtering, and various data output formats).

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4.6.2 LCD Controller (LCDIF) timing parameters
Figure 30 shows the LCDIF timing and Table 49 lists the timing parameters.

LCDn_CLK (falling edge capture)

LCDn_CLK (rising edge capture)

LCDn_DATA[23:00] LCDn Control Signals

L4 L5 L6 L7
Figure 30. LCD timing

Table 49. LCD timing parameters

Parameter

Symbol

Min

L1 LCD pixel clock frequency

tCLK(LCD)

L2 LCD pixel clock high (falling edge capture)

tCLKH(LCD)

L3 LCD pixel clock low (rising edge capture)

tCLKL(LCD)

L4 LCD pixel clock high to data valid (falling edge capture)

td(CLKH-DV)

-1

L5 LCD pixel clock low to data valid (rising edge capture)

td(CLKL-DV)

-1

L6 LCD pixel clock high to control signal valid (falling edge capture) td(CLKH-CTRLV) -1

L7 LCD pixel clock low to control signal valid (rising edge capture) td(CLKL-CTRLV) -1

Max Unit

75 MHz

4.7 Audio
This section provide information about SAI/I2S and SPDIF.

4.7.1 SAI/I2S switching specifications
This section provides the AC timings for the SAI in master (clocks driven) and slave (clocks input) modes. All timings are given for non-inverted serial clock polarity (SAI_TCR[TSCKP] = 0, SAI_RCR[RSCKP] = 0) and non-inverted frame sync (SAI_TCR[TFSI] = 0, SAI_RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal (SAI_BCLK) and/or the frame sync (SAI_FS) shown in the figures below.

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Num S1 S2 S3 S4 S5 S6 S7 S8 S9 S10

Table 50. Master mode SAI timing

Characteristic SAI_MCLK cycle time SAI_MCLK pulse width high/low SAI_BCLK cycle time SAI_BCLK pulse width high/low SAI_BCLK to SAI_FS output valid SAI_BCLK to SAI_FS output invalid SAI_BCLK to SAI_TXD valid SAI_BCLK to SAI_TXD invalid SAI_RXD/SAI_FS input setup before SAI_BCLK SAI_RXD/SAI_FS input hold after SAI_BCLK

Min 15 40% 40 40% -- 0 -- 0 15 0

Electrical Characteristics

Max -- 60% -- 60% 15 -- 15 -- -- --

Unit ns MCLK period ns BCLK period ns ns ns ns ns ns

Num S11 S12 S13 S14 S15 S16

Figure 31. SAI timing--Master modes

Table 51. Slave mode SAI timing

Characteristic SAI_BCLK cycle time (input) SAI_BCLK pulse width high/low (input) SAI_FS input setup before SAI_BCLK SAI_FA input hold after SAI_BCLK SAI_BCLK to SAI_TXD/SAI_FS output valid SAI_BCLK to SAI_TXD/SAI_FS output invalid

Min 40 40% 10 2 -- 0

Max -- 60% -- -- 20 --

Unit ns BCLK period ns ns ns ns

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Table 51. Slave mode SAI timing

Num S17 S18

Characteristic SAI_RXD setup before SAI_BCLK SAI_RXD hold after SAI_BCLK

Min 10 2

Max -- --

Unit ns ns

Figure 32. SAI timing--Slave mode

4.7.2 SPDIF timing parameters
The Sony/Philips Digital Interconnect Format (SPDIF) data is sent using the bi-phase marking code. When encoding, the SPDIF data signal is modulated by a clock that is twice the bit rate of the data signal.
Table 52 and Figure 33 and Figure 34 show SPDIF timing parameters for the Sony/Philips Digital Interconnect Format (SPDIF), including the timing of the modulating Rx clock (SPDIF_SR_CLK) for SPDIF in Rx mode and the timing of the modulating Tx clock (SPDIF_ST_CLK) for SPDIF in Tx mode.
Table 52. SPDIF timing parameters

Characteristics
SPDIF_IN Skew: asynchronous inputs, no specs apply
SPDIF_OUT output (Load = 50pf) � Skew � Transition rising � Transition falling
SPDIF_OUT1 output (Load = 30pf) � Skew � Transition rising � Transition falling
Modulating Rx clock (SPDIF_SR_CLK) period

Timing Parameter Range

Symbol

Unit

Min

Max

0.7

1.5

24.2

31.3

-- -- --

srckp

40.0

1.5

13.6

18.0

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Table 52. SPDIF timing parameters (continued)

Characteristics
SPDIF_SR_CLK high period SPDIF_SR_CLK low period Modulating Tx clock (SPDIF_ST_CLK) period SPDIF_ST_CLK high period SPDIF_ST_CLK low period

Timing Parameter Range

Symbol

Unit

Min

Max

srckph srckpl stclkp stclkph stclkpl

16.0 16.0 40.0 16.0 16.0

SPDIF_SR_CLK (Output)

srckpl VM

srckp

srckph VM

Figure 33. SPDIF_SR_CLK timing diagram

SPDIF_ST_CLK (Input)

stclkpl VM

stclkp

stclkph VM

Figure 34. SPDIF_ST_CLK timing diagram

4.8 Analog
The following sections provide information about analog interfaces.

4.8.1 DCDC
Table 53 introduces the DCDC electrical specifications.
Table 53. DCDC electrical specifications

Mode Input voltage Output voltage
Max loading Loading in low power modes

Buck mode, one output 3.3 V 1.1 V
500 mA 200 A ~ 30 mA

Notes
Min = 2.8 V, Max = 3.6 V Configurable 0.8 - 1.575 with 25 mV one step in Run mode -- --

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Mode Efficiency Low power mode Run mode Inductor Capacitor Over voltage protection Over Current protection
Low DCDC_IN detection

Table 53. DCDC electrical specifications (continued)

Buck mode, one output 90% max Open loop mode � Always continuous mode � Support discontinuous mode 4.7 H 33 F 1.55 V
1 A
2.6 V

Notes
@150 mA Ripple is about 15 mV in Run mode Configurable by register
-- -- Detect VDDSOC, when the voltage is higher than 1.6 V, shutdown DCDC. Detect the peak current � Run mode: when the current is larger than
1 A, shutdown DCDC. Detect the DCDC_IN, when battery is lower than 2.6 V, shutdown DCDC.

4.8.2 A/D converter
This section introduces information about A/D converter.

4.8.2.1 12-bit ADC electrical characteristics The section provide information about 12-bit ADC electrical characteristics.

4.8.2.1.1 12-bit ADC operating conditions

Table 54. 12-bit ADC operating conditions

Characteristic

Conditions

Symb

Min

Typ1

Max

Supply voltage
Ground voltage Ref Voltage High Ref Voltage Low Input Voltage Input Capacitance Input Resistance

Absolute Delta to VDDA_ADC_3P3 (VDD-VDDA)2 Delta to VSS (VSS-VSSAD) -- -- -- 8/10/12 bit modes ADLPC=0, ADHSC=1 ADLPC=0, ADHSC=0 ADLPC=1, ADHSC=0

VDDA VDDA
VSSAD
VDDA VSS VADIN CADIN RADIN

3.0 -100
-100
1.13 VSS VSS -- -- -- --

3.6

100

0
VDDA VSS -- 1.5 5 12.5 25

100
VDDA VSS VDDA 2 7 15 30

Unit V mV
mV
V V V pF kohms kohms kohms

Comment -- --
--
-- -- -- -- -- -- --

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Table 54. 12-bit ADC operating conditions (continued)

Characteristic

Conditions

Symb

Min

Typ1

Max

Unit Comment

Analog Source

12 bit mode fADCK =

RAS

Resistance

40MHz ADLSMP=0,

ADSTS=10, ADHSC=1

kohms

Tsamp=150 ns

RAS depends on Sample Time Setting (ADLSMP, ADSTS) and ADC Power Mode (ADHSC, ADLPC). See charts for Minimum Sample Time vs RAS

ADC Conversion Clock ADLPC=0, ADHSC=1 fADCK

Frequency

12 bit mode

MHz

ADLPC=0, ADHSC=0 12 bit mode

MHz

ADLPC=1, ADHSC=0 12 bit mode

MHz

1 Typical values assume VDDA = 3.0 V, Temp = 25�C, fADCK=20 MHz unless otherwise stated. Typical values are for reference only and are not tested in production.
2 DC potential differences

Figure 35. 12-bit ADC input impedance equivalency diagram

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12-bit ADC characteristics

Characteristic

Table 55. 12-bit ADC characteristics (VREFH = VDDA, VREFL = VSSAD)

Conditions1

Symb

Min

Typ2

Max

Unit

Comment

Supply Current

ADLPC=1, ADHSC=0

IDDA

ADLPC=0, ADHSC=0

ADLPC=0, ADHSC=1

Supply Current

Stop, Reset, Module IDDA

Off

ADC Asynchronous ADHSC=0

Clock Source

ADHSC=1

fADACK

Sample Cycles

ADLSMP=0, ADSTS=00

Csamp --

ADLSMP=0, ADSTS=01

ADLSMP=0, ADSTS=10

ADLSMP=0, ADSTS=11

ADLSMP=1, ADSTS=00

ADLSMP=1, ADSTS=01

ADLSMP=1, ADSTS=10

ADLSMP=1, ADSTS=11

350

460

750

1.4

�A

ADLSMP=0

ADSTS=10 ADCO=1

�A MHz

-- tADACK = 1/fADACK

cycles --

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Table 55. 12-bit ADC characteristics (VREFH = VDDA, VREFL = VSSAD) (continued)

Characteristic

Conditions1

Symb

Min

Typ2

Max

Unit

Comment

Conversion Cycles ADLSMP=0 ADSTS=00

Cconv --

cycles --

ADLSMP=0

ADSTS=01

ADLSMP=0

ADSTS=10

ADLSMP=0

ADSTS=11

ADLSMP=1

ADSTS=00

ADLSMP=1

ADSTS=01

ADLSMP=1

ADSTS=10

Conversion Time

ADLSMP=1, ADSTS=11
ADLSMP=0 ADSTS=00

Tconv --

0.7

�s

Fadc=40 MHz

ADLSMP=0

0.75

ADSTS=01

ADLSMP=0

0.8

ADSTS=10

ADLSMP=0

0.85

ADSTS=11

ADLSMP=1

0.95

ADSTS=00

ADLSMP=1

1.05

ADSTS=01

ADLSMP=1

1.15

ADSTS=10

ADLSMP=1,

1.25

ADSTS=11

Total Unadjusted Error

12 bit mode 10 bit mode 8 bit mode

TUE

3.4

1.5

1.2

LSB 1 LSB = (VREFH VREFL)/2 N

AVGE = 1, AVGS = 11

Differential Non-Linearity

12 bit mode 10bit mode

DNL

0.76

0.36

LSB

AVGE = 1, AVGS =

8 bit mode

0.14

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Table 55. 12-bit ADC characteristics (VREFH = VDDA, VREFL = VSSAD) (continued)

Characteristic

Conditions1

Symb

Min

Typ2

Max

Unit

Comment

Integral Non-Linearity

12 bit mode 10bit mode

INL

2.78

0.61

LSB

AVGE = 1, AVGS =

8 bit mode

0.14

Zero-Scale Error

12 bit mode 10bit mode

EZS

-1.14

-0.25

LSB

AVGE = 1, AVGS =

8 bit mode

-0.19

Full-Scale Error

12 bit mode 10bit mode

EFS

-1.06

-0.03

LSB

AVGE = 1, AVGS =

8 bit mode

-0.02

Effective Number of 12 bit mode Bits

ENOB 10.1

10.7

Bits

AVGE = 1, AVGS =

Signal to Noise plus See ENOB Distortion

SINAD SINAD = 6.02 x ENOB + 1.76 dB

AVGE = 1, AVGS = 11

1 All accuracy numbers assume the ADC is calibrated with VREFH = VDDA 2 Typical values assume VDDA = 3.0 V, Temp = 25�C, Fadck = 20 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.

NOTE The ADC electrical spec is met with the calibration enabled configuration.

Figure 36. Minimum Sample Time Vs Ras (Cas = 2 pF)

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 3, 03/2021

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Figure 37. Minimum Sample Time Vs Ras (Cas = 5 pF)

Figure 38. Minimum Sample Time Vs Ras (Cas = 10 pF)

4.8.3 ACMP
Table 56 lists the ACMP electrical specifications.
Table 56. Comparator and 6-bit DAC electrical specifications

Symbol VDD IDDHS
IDDLS
VAIN VAIO

Description

Min.

Supply voltage

3.0

Supply current, High-speed mode -- (EN = 1, PMODE = 1)

Supply current, Low-speed mode -- (EN = 1, PMODE = 0)

Analog input voltage

VSS

Analog input offset voltage

Typ. -- 347
42
-- --

Max. 3.6 --
--
VDD 21

Unit V A
A
V mV

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Table 56. Comparator and 6-bit DAC electrical specifications (continued)

Symbol

Description

Min.

Typ.

Max.

Unit

Analog comparator hysteresis1

� CR0[HYSTCTR] = 00

� CR0[HYSTCTR] = 01

� CR0[HYSTCTR] = 10

108

� CR0[HYSTCTR] = 11

184

VCMPOH VCMPOI tDHS

Output high Output low

VDD - 0.5

Propagation delay, high-speed --

mode (EN = 1, PMODE = 1)2

0.5

tDLS

Propagation delay, low-speed

mode (EN = 1, PMODE = 0)2

tDInit

Analog comparator initialization --

1.5

delay3

IDAC6b

6-bit DAC current adder (enabled) --

RDAC6b

6-bit DAC reference inputs

VDD

INLDAC6b

6-bit DAC integral non-linearity -0.3

0.3

LSB4

DNLDAC6b

6-bit DAC differential non-linearity -0.15

0.15

LSB4

1 Typical hysteresis is measured with input voltage range limited to 0.7 to VDD - 0.7 V in high speed mode. 2 Signal swing is 100 mV. 3 Comparator initialization delay is defined as the time between software writes to the enable comparator module and the
comparator output setting to a stable level. 4 1 LSB = Vreference / 64

4.9 Communication interfaces
The following sections provide the information about communication interfaces.

4.9.1 LPSPI timing parameters
The Low Power Serial Peripheral Interface (LPSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The following tables provide timing characteristics for classic LPSPI timing modes.
All timing is shown with respect to 20% VDD and 80% VDD thresholds, unless noted, as well as input signal transitions of 3 ns and a 30 pF maximum load on all LPSPI pins.

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Electrical Characteristics

Table 57. LPSPI Master mode timing

Number Symbol

Description

Min.

Max.

Units

Note

fSCK

Frequency of operation

tSCK

SCK period

fperiph / 2

2 x tperiph

tLead

Enable lead time

tperiph

tLag

Enable lag time

tperiph

tWSCK Clock (SCK) high or low time

tSCK / 2 - 3

tSU

Data setup time (inputs)

tHI

Data hold time (inputs)

Data valid (after SCK edge)

tHO

Data hold time (outputs)

1 Absolute maximum frequency of operation (fop) is 30 MHz. The clock driver in the LPSPI module for fperiph must be guaranteed this limit is not exceeded.
2 tperiph = 1 / fperiph

1 PCS (OUTPUT)

SCK (CPOL=0) (OUTPUT)

SCK (CPOL=1) (OUTPUT)
SIN (INPUT)
SOUT (OUTPUT)

2 MSB IN

2 MSB OUT

BIT 6 . . . 1 8 BIT 6 . . . 1

LSB IN LSB OUT

1. If configured as an output. 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 39. LPSPI Master mode timing (CPHA = 0)

4 9

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 3, 03/2021

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Electrical Characteristics

1 PCS (OUTPUT)

SCK (CPOL=0) (OUTPUT)
SCK (CPOL=1) (OUTPUT)
SIN (INPUT)

2 3

MSB IN2

SOUT (OUTPUT)

PORT DATA

2
MASTER MSB OUT

BIT 6 . . . 1
9 BIT 6 . . . 1

LSB IN

MASTER LSB OUT

PORT DATA

1.If configured as output 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 40. LPSPI Master mode timing (CPHA = 1)

Table 58. LPSPI Slave mode timing

Number Symbol

Description

Min.

Max.

Units

Note

fSCK

Frequency of operation

tSCK

SCK period

fperiph / 2

2 x tperiph

tLead

Enable lead time

tperiph

tLag

Enable lag time

tperiph

tWSCK Clock (SCK) high or low time

tSCK / 2 - 5

tSU

Data setup time (inputs)

2.7

tHI

Data hold time (inputs)

Slave access time

tdis

Slave MISO disable time

3.8

tperiph

Data valid (after SCK edge)

14.5

tHO

Data hold time (outputs)

1 Absolute maximum frequency of operation (fop) is 30 MHz. The clock driver in the LPSPI module for fperiph must be guaranteed this limit is not exceeded.
2 tperiph = 1 / fperiph 3 Time to data active from high-impedance state 4 Hold time to high-impedance state

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 3, 03/2021

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PCS (INPUT)

Electrical Characteristics

SCK (CPOL=0) (INPUT)
SCK (CPOL=1)
(INPUT)
8
SIN (OUTPUT)
SOUT (INPUT)

see note
6

SLAVE MSB 7

10 BIT 6 . . . 1

SLAVE LSB OUT

9
SEE NOTE

MSB IN

BIT 6 . . . 1

LSB IN

NOTE: Not defined

Figure 41. LPSPI Slave mode timing (CPHA = 0)

PCS (INPUT)

SCK (CPOL=0) (INPUT)
SCK (CPOL=1)
(INPUT)
SIN (OUTPUT)

2 3

10 see note SLAVE MSB OUT

11 BIT 6 . . . 1

4
9 SLAVE LSB OUT

8
SOUT (INPUT) NOTE: Not defined

MSB IN

BIT 6 . . . 1

LSB IN

Figure 42. LPSPI Slave mode timing (CPHA = 1)

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 3, 03/2021

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Electrical Characteristics

4.9.2 LPI2C module timing parameters
This section describes the timing parameters of the LPI2C module.
Table 59. LPI2C module timing parameters

Symbol

Description

Min

fSCL

SCL clock frequency

Standard mode (Sm)

Fast mode (Fm)

Fast mode Plus (Fm+)

Ultra Fast mode (UFm)

High speed mode (Hs-mode) 0
1 Hs-mode is only supported in slave mode. 2 See General switching specifications.

Max 100 400 1000 5000 3400

Unit kHz

Notes
1, 2

4.9.3 Ultra High Speed SD/SDIO/MMC Host Interface (uSDHC) AC
timing
This section describes the electrical information of the uSDHC, which includes SD/eMMC4.3 (Single Data Rate) timing, eMMC4.4/4.41/4.5 (Dual Date Rate) timing and SDR104/50(SD3.0) timing.
4.9.3.1 SD/eMMC4.3 (single data rate) AC timing Figure 43 depicts the timing of SD/eMMC4.3, and Table 60 lists the SD/eMMC4.3 timing characteristics.
SD4
SD2 SD1
SD5

SDx_CLK

SD3 SD6

Output from uSDHC to card SDx_DATA[7:0]

SD7 SD8

Input from card to uSDHC SDx_DATA[7:0]
Figure 43. SD/eMMC4.3 timing

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 3, 03/2021

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Electrical Characteristics

Table 60. SD/eMMC4.3 interface timing specification

Parameter

Symbols

Min

Max

Unit

SD1
SD2 SD3 SD4 SD5

Card Input Clock

Clock Frequency (Low Speed) Clock Frequency (SD/SDIO Full Speed/High Speed) Clock Frequency (MMC Full Speed/High Speed) Clock Frequency (Identification Mode) Clock Low Time Clock High Time Clock Rise Time Clock Fall Time

fPP1

fPP2

fPP3

fOD

100

tWL

tWH

tTLH

tTHL

uSDHC Output/Card Inputs SD_CMD, SDx_DATAx (Reference to CLK)

400 25/50 20/52 400
-- -- 3 3

kHz MHz MHz kHz
ns ns ns ns

SD6 uSDHC Output Delay

tOD

-6.6

3.6

uSDHC Input/Card Outputs SD_CMD, SDx_DATAx (Reference to CLK)

SD7 uSDHC Input Setup Time

tISU

2.5

SD8 uSDHC Input Hold Time4

tIH

1.5

1 In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.
2 In normal (full) speed mode for SD/SDIO card, clock frequency can be any value between 0�25 MHz. In high-speed mode, clock frequency can be any value between 0�50 MHz.
3 In normal (full) speed mode for MMC card, clock frequency can be any value between 0�20 MHz. In high-speed mode, clock frequency can be any value between 0�52 MHz.
4 To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.

4.9.3.2 eMMC4.4/4.41 (dual data rate) AC timing
Figure 44 depicts the timing of eMMC4.4/4.41. Table 61 lists the eMMC4.4/4.41 timing characteristics. Be aware that only DATA is sampled on both edges of the clock (not applicable to CMD).

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 3, 03/2021

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Electrical Characteristics

SD1

SDx_CLK

SD2

Output from eSDHCv3 to card SDx_DATA[7:0]

......

SD3 SD4

Input from card to eSDHCv3

SDx_DATA[7:0]

......

Figure 44. eMMC4.4/4.41 timing Table 61. eMMC4.4/4.41 interface timing specification

Parameter

Symbols

Min

Max

Card Input Clock

SD1 Clock Frequency (eMMC4.4/4.41 DDR) SD1 Clock Frequency (SD3.0 DDR)

fPP

uSDHC Output / Card Inputs SD_CMD, SDx_DATAx (Reference to CLK)

SD2 uSDHC Output Delay

tOD

2.5

7.1

uSDHC Input / Card Outputs SD_CMD, SDx_DATAx (Reference to CLK)

SD3 uSDHC Input Setup Time SD4 uSDHC Input Hold Time

tISU

1.7

tIH

1.5

Unit
MHz MHz
ns
ns ns

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 3, 03/2021

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Electrical Characteristics
4.9.3.3 SDR50/SDR104 AC timing Figure 45 depicts the timing of SDR50/SDR104, and Table 62 lists the SDR50/SDR104 timing characteristics.

SCK 4-bit output from uSDHC to card
4-bit input from card to uSDHC

SD1

SD2

SD3

SD4/SD5

SD6

SD7

SD8

Figure 45. SDR50/SDR104 timing

Table 62. SDR50/SDR104 interface timing specification

Parameter

Symbols

Min

Max

Unit

Card Input Clock

SD1 Clock Frequency Period SD2 Clock Low Time SD3 Clock High Time

tCLK

5.0

tCL

0.46 x tCLK 0.54 x tCLK

tCH

0.46 x tCLK 0.54 x tCLK

uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR50 (Reference to CLK)

SD4 uSDHC Output Delay

tOD

�3

uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR104 (Reference to CLK)

SD5 uSDHC Output Delay

tOD

�1.6

uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR50 (Reference to CLK)

SD6 uSDHC Input Setup Time

tISU

2.5

SD7 uSDHC Input Hold Time

tIH

1.5

uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR104 (Reference to CLK)1

SD8 Card Output Data Window 1Data window in SDR104 mode is variable.

tODW

0.5 x tCLK

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 3, 03/2021

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Electrical Characteristics
4.9.3.4 HS200 mode timing Figure 46 depicts the timing of HS200 mode, and Table 63 lists the HS200 timing characteristics.

SCK 8-bit output from uSDHC to eMMC

SD1

SD2

SD3

SD4/SD5

8-bit input from eMMC to uSDHC SD8

Figure 46. HS200 mode timing

Table 63. HS200 interface timing specification

Parameter

Symbols

Min

Max

Unit

Card Input Clock

SD1 Clock Frequency Period SD2 Clock Low Time SD3 Clock High Time

tCLK

5.0

tCL

0.46 x tCLK 0.54 x tCLK

tCH

0.46 x tCLK 0.54 x tCLK

uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)

SD5 uSDHC Output Delay

tOD

�1.6

0.74

uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)1

SD8 Card Output Data Window

tODW

0.5 x tCLK

1HS200 is for 8 bits while SDR104 is for 4 bits.

4.9.3.5 Bus operation condition for 3.3 V and 1.8 V signaling
Signaling level of SD/eMMC4.3 and eMMC4.4/4.41 modes is 3.3 V. Signaling level of SDR104/SDR50 mode is 1.8 V. The DC parameters for the NVCC_SD1 supply are identical to those shown in Table 22, "Single voltage GPIO DC parameters," on page 33.
4.9.4 Ethernet controller (ENET) AC electrical specifications
The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface.

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 3, 03/2021

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Electrical Characteristics
4.9.4.1 ENET MII mode timing This subsection describes MII receive, transmit, asynchronous inputs, and serial management signal timings.
4.9.4.1.1 MII receive signal timing (ENET_RX_DATA3,2,1,0, ENET_RX_EN, ENET_RX_ER, and ENET_RX_CLK)
The receiver functions correctly up to an ENET_RX_CLK maximum frequency of 25 MHz + 1%. There is no minimum frequency requirement. Additionally, the processor clock frequency must exceed twice the ENET_RX_CLK frequency. Figure 47 shows MII receive signal timings. Table 64 describes the timing parameters (M1�M4) shown in the figure.
M3
ENET_RX_CLK (input)

ENET_RX_DATA3,2,1,0 (inputs)

ENET_RX_EN ENET_RX_ER

Figure 47. MII receive signal timing diagram

ID M1
M2
M3 M4

Table 64. MII receive signal timing

Characteristic1

Min.

ENET_RX_DATA3,2,1,0, ENET_RX_EN, ENET_RX_ER to ENET_RX_CLK setup
ENET_RX_CLK to ENET_RX_DATA3,2,1,0, ENET_RX_EN, ENET_RX_ER hold
ENET_RX_CLK pulse width high
ENET_RX_CLK pulse width low

5
5
35% 35%

Max.

Unit

65% 65%

ENET_RX_CLK period ENET_RX_CLK period

1 ENET_RX_EN, ENET_RX_CLK, and ENET0_RXD0 have the same timing in 10 Mbps 7-wire interface mode.

4.9.4.1.2 MII transmit signal timing (ENET_TX_DATA3,2,1,0, ENET_TX_EN, ENET_TX_ER, and ENET_TX_CLK)
The transmitter functions correctly up to an ENET_TX_CLK maximum frequency of 25 MHz + 1%. There is no minimum frequency requirement. Additionally, the processor clock frequency must exceed twice the ENET_TX_CLK frequency.

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 3, 03/2021

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Electrical Characteristics
Figure 48 shows MII transmit signal timings. Table 65 describes the timing parameters (M5�M8) shown in the figure.
M7

ENET_TX_CLK (input)

ENET_TX_DATA3,2,1,0 (outputs)
ENET_TX_EN ENET_TX_ER

M5 M8
M6 Figure 48. MII transmit signal timing diagram

ID M5
M6
M7 M8

Table 65. MII transmit signal timing

Characteristic1

Min.

ENET_TX_CLK to ENET_TX_DATA3,2,1,0, ENET_TX_EN, ENET_TX_ER invalid
ENET_TX_CLK to ENET_TX_DATA3,2,1,0, ENET_TX_EN, ENET_TX_ER valid
ENET_TX_CLK pulse width high
ENET_TX_CLK pulse width low

5
--
35% 35%

Max. --
20
65% 65%

Unit ns
ns
ENET_TX_CLK period ENET_TX_CLK period

1 ENET_TX_EN, ENET_TX_CLK, and ENET0_TXD0 have the same timing in 10-Mbps 7-wire interface mode.

4.9.4.1.3 MII asynchronous inputs signal timing (ENET_CRS and ENET_COL)
Figure 49 shows MII asynchronous input timings. Table 66 describes the timing parameter (M9) shown in the figure.

ENET_CRS, ENET_COL

Figure 49. MII asynchronous inputs timing diagram

Table 66. MII asynchronous inputs signal timing

ID M91

Characteristic ENET_CRS to ENET_COL minimum pulse width

Min. 1.5

Max. --

1 ENET_COL has the same timing in 10-Mbit 7-wire interface mode.

Unit ENET_TX_CLK period

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 3, 03/2021

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Electrical Characteristics
4.9.4.1.4 MII serial management channel timing (ENET_MDIO and ENET_MDC)
The MDC frequency is designed to be equal to or less than 2.5 MHz to be compatible with the IEEE 802.3 MII specification. However the ENET can function correctly with a maximum MDC frequency of 15 MHz. Figure 50 shows MII asynchronous input timings. Table 67 describes the timing parameters (M10�M15) shown in the figure.

ENET_MDC (output)

M14 M15

M10

ENET_MDIO (output)

M11

ENET_MDIO (input)

ID M10
M11
M12 M13 M14 M15

M12 M13 Figure 50. MII serial management channel timing diagram

Table 67. MII serial management channel timing

Characteristic
ENET_MDC falling edge to ENET_MDIO output invalid (min. propagation delay) ENET_MDC falling edge to ENET_MDIO output valid (max. propagation delay) ENET_MDIO (input) to ENET_MDC rising edge setup ENET_MDIO (input) to ENET_MDC rising edge hold ENET_MDC pulse width high ENET_MDC pulse width low

Min. 0
--
18 0 40% 40%

Max. --
5
-- -- 60% 60%

Unit ns
ns
ns ns ENET_MDC period ENET_MDC period

4.9.4.2 RMII mode timing
In RMII mode, ENET_CLK is used as the REF_CLK, which is a 50 MHz � 50 ppm continuous reference clock. ENET_RX_EN is used as the ENET_RX_EN in RMII. Other signals under RMII mode include ENET_TX_EN, ENET_TX_DATA[1:0], ENET_RX_DATA[1:0] and ENET_RX_ER.

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 3, 03/2021

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Electrical Characteristics
Figure 51 shows RMII mode timings. Table 68 describes the timing parameters (M16�M21) shown in the figure.

ENET_CLK (input)

M16 M17

M18
ENET_TX_DATA (output) ENET_TX_EN

ENET_RX_EN (input) ENET_RX_DATA[1:0] ENET_RX_ER

M19
M20 M21 Figure 51. RMII mode signal timing diagram

Table 68. RMII signal timing

ID M16 M17 M18 M19 M20
M21

Characteristic
ENET_CLK pulse width high ENET_CLK pulse width low ENET_CLK to ENET0_TXD[1:0], ENET_TX_DATA invalid ENET_CLK to ENET0_TXD[1:0], ENET_TX_DATA valid ENET_RX_DATAD[1:0], ENET_RX_EN(ENET_RX_EN), ENET_RX_ER to ENET_CLK setup ENET_CLK to ENET_RX_DATAD[1:0], ENET_RX_EN, ENET_RX_ER hold

Min. 35% 35%
4 -- 2
2

Max. 65% 65%
-- 13 --

Unit ENET_CLK period ENET_CLK period
ns ns ns

4.9.5 Flexible Controller Area Network (FLEXCAN) AC electrical specifications
Please refer to Section 4.3.2.1, General purpose I/O AC parameters.

4.9.6 LPUART electrical specifications
Please refer to Section 4.3.2.1, General purpose I/O AC parameters.

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 3, 03/2021

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Electrical Characteristics
4.9.7 USB PHY parameters
This section describes the USB-OTG PHY parameters.
The USB PHY meets the electrical compliance requirements defined in the Universal Serial Bus Revision 2.0 OTG with the following amendments.
� USB ENGINEERING CHANGE NOTICE -- Title: 5V Short Circuit Withstand Requirement Change -- Applies to: Universal Serial Bus Specification, Revision 2.0
� Errata for USB Revision 2.0 April 27, 2000 as of 12/7/2000 � USB ENGINEERING CHANGE NOTICE
-- Title: Pull-up/Pull-down resistors -- Applies to: Universal Serial Bus Specification, Revision 2.0 � USB ENGINEERING CHANGE NOTICE -- Title: Suspend Current Limit Changes -- Applies to: Universal Serial Bus Specification, Revision 2.0 � USB ENGINEERING CHANGE NOTICE -- Title: USB 2.0 Phase Locked SOFs -- Applies to: Universal Serial Bus Specification, Revision 2.0 � On-The-Go and Embedded Host Supplement to the USB Revision 2.0 Specification -- Revision 2.0 plus errata and ecn June 4, 2010 � Battery Charging Specification (available from USB-IF) -- Revision 1.2, December 7, 2010 -- Portable device only

4.10 Timers
This section provide information on timers.

4.10.1 Pulse Width Modulator (PWM) characteristics
This section describes the electrical information of the PWM.
Table 69. PWM timing parameters

Parameter PWM Clock Frequency

Symbo

Min

Typ

Max

Unit

150

MHz

4.10.2 Quad timer timing
Table 70 listed the timing parameters.

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 3, 03/2021

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Electrical Characteristics

Table 70. Quad timer timing

Characteristic

Symbol

Min1

Max

Unit

Timer input period

TIN

2T + 6

Timer input high/low period

TINHL

1T + 3

Timer output period

TOUT

Timer output high/low period

TOUTHL

16.7

1 T = clock cycle. For 60 MHz operation, T = 16.7 ns.

4IMER)NPUTS 4 ).

4).(,

See Figure

4IMER/UTPUTS

4 /54

4 /54(,

Figure 52. Quad timer timing

4 /54(,

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 3, 03/2021

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5 Flash

This section introduces the on-chip flash electrical parameters. Table 71 shows the operating ranges of on-chip flash power supply by NVCC_GPIO.
Table 71. Operating ranges

Parameter

Symbol

Conditions

Spec.

Min

Max

Supply voltage

NVCC_GPIO FR = 133 MHz, fR = 50 MHz

3.0

3.6

For details about the flash AC parameters, refer to the following link.

Flash
Unit V

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 3, 03/2021

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Boot mode configuration
6 Boot mode configuration
This section provides information on boot mode configuration pins allocation and boot devices interfaces allocation.

6.1 Boot mode configuration pins
Table 72 provides boot options, functionality, fuse values, and associated pins. Several input pins are also sampled at reset and can be used to override fuse values, depending on the value of BT_FUSE_SEL fuse. The boot option pins are in effect when BT_FUSE_SEL fuse is `0' (cleared, which is the case for an unblown fuse). For detailed boot mode options configured by the boot mode pins, see the i.MX RT1064 Fuse Map document and the System Boot chapter in i.MX RT1064 Reference Manual (IMXRT1064RM).
Table 72. Fuses and associated pins used for boot

Pad GPIO_AD_B0_04 GPIO_AD_B0_05 GPIO_B0_04 GPIO_B0_05 GPIO_B0_06 GPIO_B0_07 GPIO_B0_08 GPIO_B0_09 GPIO_B0_10 GPIO_B0_11 GPIO_B0_12 GPIO_B0_13 GPIO_B0_14 GPIO_B0_15

Default setting on reset

eFuse name

100 K pull-down 100 K pull-down 100 K pull-down 100 K pull-down 100 K pull-down 100 K pull-down 100 K pull-down 100 K pull-down 100 K pull-down 100 K pull-down 100 K pull-down 100 K pull-down 100 K pull-down 100 K pull-down

BOOT_MODE0 BOOT_MODE1 BT_CFG[0] BT_CFG[1] BT_CFG[2] BT_CFG[3] BT_CFG[4] BT_CFG[5] BT_CFG[6] BT_CFG[7] BT_CFG[8] BT_CFG[9] BT_CFG[10] BT_CFG[11]

Details
Boot Options, Pin value overrides fuse settings for BT_FUSE_SEL = `0'. Signal Configuration as Fuse Override Input at Power Up. These are special I/O lines that control the boot up configuration during product development. In production, the boot configuration can be controlled by fuses.

6.2 Boot device interface allocation
The following tables list the interfaces that can be used by the boot process in accordance with the specific boot mode configuration. The tables also describe the interface's specific modes and IOMUXC allocation, which are configured during boot when appropriate.
Table 73. Boot trough NAND

PAD Name GPIO_EMC_00 GPIO_EMC_01 GPIO_EMC_02

IO Function semc.DATA[0] semc.DATA[1] semc.DATA[2]

ALT ALT 0 ALT 0 ALT 0

Comments -- -- --

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 3, 03/2021

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GPIO_EMC_03 GPIO_EMC_04 GPIO_EMC_05 GPIO_EMC_06 GPIO_EMC_07 GPIO_EMC_30 GPIO_EMC_31 GPIO_EMC_32 GPIO_EMC_33 GPIO_EMC_34 GPIO_EMC_35 GPIO_EMC_36 GPIO_EMC_37 GPIO_EMC_18 GPIO_EMC_19 GPIO_EMC_20 GPIO_EMC_22 GPIO_EMC_41
PAD Name GPIO_EMC_00 GPIO_EMC_01 GPIO_EMC_02 GPIO_EMC_03 GPIO_EMC_04 GPIO_EMC_05 GPIO_EMC_06 GPIO_EMC_07 GPIO_EMC_30 GPIO_EMC_31 GPIO_EMC_32 GPIO_EMC_33

Table 73. Boot trough NAND semc.DATA[3] semc.DATA[4] semc.DATA[5] semc.DATA[6] semc.DATA[7] semc.DATA[8] semc.DATA[9] semc.DATA[10] semc.DATA[11] semc.DATA[12] semc.DATA[13] semc.DATA[14] semc.DATA[15] semc.ADDR[9] semc.ADDR[11] semc.ADDR[12] semc.BA1 semc.CSX[0]
Table 74. Boot trough NOR
IO Function semc.DATA[0] semc.DATA[1] semc.DATA[2] semc.DATA[3] semc.DATA[4] semc.DATA[5] semc.DATA[6] semc.DATA[7] semc.DATA[8] semc.DATA[9] semc.DATA[10] semc.DATA[11]

Boot mode configuration

ALT 0

ALT ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0

Comments -- -- -- -- -- -- -- -- -- -- -- --

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 3, 03/2021

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Boot mode configuration
GPIO_EMC_34 GPIO_EMC_35 GPIO_EMC_36 GPIO_EMC_37 GPIO_EMC_09 GPIO_EMC_10 GPIO_EMC_11 GPIO_EMC_12 GPIO_EMC_13 GPIO_EMC_14 GPIO_EMC_15 GPIO_EMC_16 GPIO_EMC_19 GPIO_EMC_20 GPIO_EMC_21 GPIO_EMC_22 GPIO_EMC_41
PAD Name GPIO_SD_B1_00 GPIO_SD_B1_01 GPIO_SD_B1_02 GPIO_SD_B1_03 GPIO_SD_B1_04 GPIO_SD_B0_05 GPIO_SD_B0_04 GPIO_SD_B0_01 GPIO_SD_B1_05 GPIO_SD_B1_06 GPIO_SD_B0_00 GPIO_SD_B1_07 GPIO_SD_B1_08 GPIO_SD_B1_09

Table 74. Boot trough NOR semc.DATA[12] semc.DATA[13] semc.DATA[14] semc.DATA[15] semc.ADDR[0] semc.ADDR[1] semc.ADDR[2] semc.ADDR[3] semc.ADDR[4] semc.ADDR[5] semc.ADDR[6] semc.ADDR[7] semc.ADDR[11] semc.ADDR[12] semc.BA0 semc.BA1 semc.CSX[0]

ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0

Table 75. Boot through FlexSPI
IO Function flexspi.B_DATA[3] flexspi.B_DATA[2] flexspi.B_DATA[1] flexspi.B_DATA[0]
flexspi.B_SCLK flexspi.B_DQS flexspi.B_SS0_B flexspi.B_SS1_B flexspi.A_DQS flexspi.A_SS0_B flexspi.A_SS1_B flexspi.A_SCLK flexspi.A_DATA[0] flexspi.A_DATA[1]

Mux Mode ALT 1 ALT 1 ALT 1 ALT 1 ALT 1 ALT 4 ALT 4 ALT 6 ALT 1 ALT 1 ALT 6 ALT 1 ALT 1 ALT 1

-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Comments -- -- -- -- -- -- -- -- -- -- -- -- -- --

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 3, 03/2021

NXP Semiconductors

PAD Name GPIO_SD_B1_10 GPIO_SD_B1_11
PAD Name GPIO_SD_B0_00 GPIO_SD_B0_01 GPIO_SD_B0_02 GPIO_SD_B0_03 GPIO_SD_B0_04 GPIO_SD_B0_05
PAD Name GPIO_SD_B1_00 GPIO_SD_B1_01 GPIO_SD_B1_02 GPIO_SD_B1_03 GPIO_SD_B1_04 GPIO_SD_B1_05 GPIO_SD_B1_06 GPIO_SD_B1_08 GPIO_SD_B1_09 GPIO_SD_B1_10 GPIO_SD_B1_11
PAD Name GPIO_SD_B0_00 GPIO_SD_B0_02 GPIO_SD_B0_03 GPIO_SD_B0_01

Boot mode configuration

Table 75. Boot through FlexSPI (continued)

IO Function flexspi.A_DATA[2] flexspi.A_DATA[3]

Mux Mode ALT 1 ALT 1

Comments -- --

Table 76. Boot through SD1
IO Function usdhc1.CMD usdhc1.CLK usdhc1.DATA0 usdhc1.DATA1 usdhc1.DATA2 usdhc1.DATA3

Mux Mode ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0

Comments -- -- -- -- -- --

Table 77. Boot through SD2
IO Function usdhc2.DATA3 usdhc2.DATA2 usdhc2.DATA1 usdhc2.DATA0
usdhc2.CLK usdhc2.CMD usdhc2.RESET_B usdhc2.DATA4 usdhc2.DATA5 usdhc2.DATA6 usdhc2.DATA7

Mux Mode ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0

Comments -- -- -- -- -- -- -- -- -- -- --

Table 78. Boot through SPI-1
IO Function lpspi1.SCK lpspi1.SDO lpspi1.SDI lpspi1.PCS0

Mux Mode ALT 4 ALT 4 ALT 4 ALT 4

Comments -- -- -- --

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 3, 03/2021

NXP Semiconductors

Boot mode configuration
PAD Name GPIO_SD_B1_07 GPIO_SD_B1_08 GPIO_SD_B1_09 GPIO_SD_B1_06
PAD Name GPIO_AD_B0_00 GPIO_AD_B0_01 GPIO_AD_B0_02 GPIO_SD_B0_03
PAD Name GPIO_B0_03 GPIO_B0_02 GPIO_B0_01 GPIO_B0_00
PAD Name GPIO_AD_B0_12 GPIO_AD_B0_13

Table 79. Boot through SPI-2 IO Function lpspi2.SCK lpspi2.SDO lpspi2.SDI lpspi2.PCS0
Table 80. Boot through SPI-3 IO Function lpspi3.SCK lpspi3.SDO lpspi3.SDI lpspi3.PCS0
Table 81. Boot through SPI-4 IO Function lpspi4.SCK lpspi4.SDO lpspi4.SDI lpspi4.PCS0
Table 82. Boot through UART1 IO Function lpuart1.TX lpuart1.RX

Mux Mode ALT 4 ALT 4 ALT 4 ALT 4
Mux Mode ALT 7 ALT 7 ALT 7 ALT 7
Mux Mode ALT 3 ALT 3 ALT 3 ALT 3
Mux Mode ALT 2 ALT 2

Comments -- -- -- --
Comments -- -- -- --
Comments -- -- -- --
Comments -- --

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 3, 03/2021

NXP Semiconductors

Package information and contact assignments
7 Package information and contact assignments
This section includes the contact assignment information and mechanical package drawing.
7.1 10 x 10 mm package information
7.1.1 10 x 10 mm, 0.65 mm pitch, ball matrix
Figure 53 shows the top, bottom, and side views of the 10 x 10 mm MAPBGA package.

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 3, 03/2021

NXP Semiconductors

Package information and contact assignments

Figure 53. 10 x 10 mm BGA, case x package top, bottom, and side Views

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 3, 03/2021

NXP Semiconductors

Package information and contact assignments

7.1.2 10 x 10 mm supplies contact assignments and functional contact assignments
Table 83 shows the device connection list for ground, sense, and reference contact signals.
Table 83. 10 x 10 mm supplies contact assignment

Supply Rail Name

Ball(s) Position(s)

DCDC_IN

L1, L2

DCDC_IN_Q

DCDC_GND

N1, N2

DCDC_LP

M1, M2

DCDC_PSWITCH

DCDC_SENSE

GPANAIO

N10

NGND_KEL0

NVCC_EMC

E6, F5

NVCC_GPIO

E9, F10, J10

NVCC_PLL

P10

NVCC_SD0

NVCC_SD1

VDDA_ADC_3P3

N14

VDD_HIGH_CAP

VDD_HIGH_IN

P12

VDD_SNVS_CAP

M10

VDD_SNVS_IN

VDD_SOC_IN

F6, F7, F8, F9, G6, G9, H6, H9, J9

VDD_USB_CAP

VSS

A1, A14, B5, B10, E2, E13, G7, G8, H7, H8, J7, J8, K2, K13, L9, N5, N8, P1, P14

Remark -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --

Table 84 shows an alpha-sorted list of functional contact assignments for the 10 x 10 mm package.
Table 84. 10 x 10 mm functional contact assignments

Ball Name
CCM_CLK1_N CCM_CLK1_P

10 x 10 Ball
P13 N13

Power Group
-- --

Ball Type
-- --

Default Setting

Default Mode

Default Function

CCM_CLK1_N

CCM_CLK1_P

Input/ Output
--
--

Default setting on Reset

Value

Input/ Output

Value

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 3, 03/2021

NXP Semiconductors

Package information and contact assignments

GPIO_AD_B0_00 GPIO_AD_B0_01 GPIO_AD_B0_02 GPIO_AD_B0_03 GPIO_AD_B0_04 GPIO_AD_B0_05 GPIO_AD_B0_06 GPIO_AD_B0_07 GPIO_AD_B0_08 GPIO_AD_B0_09 GPIO_AD_B0_10 GPIO_AD_B0_11 GPIO_AD_B0_12 GPIO_AD_B0_13 GPIO_AD_B0_14 GPIO_AD_B0_15 GPIO_AD_B1_00 GPIO_AD_B1_01 GPIO_AD_B1_02 GPIO_AD_B1_03 GPIO_AD_B1_04

Table 84. 10 x 10 mm functional contact assignments (continued)

M14 NVCC_GPIO Digital GPIO

ALT5

GPIO1.IO[0]

Input Keeper

H10 NVCC_GPIO Digital GPIO

ALT5

GPIO1.IO[1]

Input Keeper

M11 NVCC_GPIO Digital GPIO

ALT5

GPIO1.IO[2]

Input Keeper

G11 NVCC_GPIO Digital ALT5 GPIO

GPIO1.IO[3]

Input Keeper

F11 NVCC_GPIO Digital ALT0 SRC.BOOT.MOD Input

GPIO

E[0]

100 K PD

G14 NVCC_GPIO Digital GPIO

ALT0 SRC.BOOT.MOD Input E[1]

100 K PD

E14 NVCC_GPIO Digital ALT0 JTAG.MUX.TMS Input 47 K PU GPIO

F12 NVCC_GPIO Digital ALT0 JTAG.MUX.TCK Input 47 K PU GPIO

F13 NVCC_GPIO Digital ALT0 JTAG.MUX.MOD Input GPIO

100 K PU

F14 NVCC_GPIO Digital GPIO

ALT0

JTAG.MUX.TDI

Input 47 K PU

G13 NVCC_GPIO Digital GPIO

ALT0 JTAG.MUX.TDO Input

Keeper

G10 NVCC_GPIO Digital GPIO

ALT0 JTAG.MUX.TRS TB

Input 47 K PU

K14 NVCC_GPIO Digital ALT5 GPIO

GPIO1.IO[12]

Input Keeper

L14 NVCC_GPIO Digital ALT5 GPIO

GPIO1.IO[13]

Input Keeper

H14 NVCC_GPIO Digital GPIO

ALT5

GPIO1.IO[14]

Input Keeper

L10 NVCC_GPIO Digital ALT5 GPIO

GPIO1.IO[15]

Input Keeper

J11 NVCC_GPIO Digital ALT5 GPIO

GPIO1.IO[16]

Input Keeper

K11 NVCC_GPIO Digital ALT5 GPIO

GPIO1.IO[17]

Input Keeper

L11 NVCC_GPIO Digital ALT5 GPIO

GPIO1.IO[18]

Input Keeper

M12 NVCC_GPIO Digital GPIO

ALT5

GPIO1.IO[19]

Input Keeper

L12 NVCC_GPIO Digital ALT5 GPIO

GPIO1.IO[20]

Input Keeper

Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input

Keeper
Keeper
Keeper
Keeper
100 K PD
100 K PD
47 K PU
100 K PD
100 K PD
47 K PU
Keeper
47 K PU
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 3, 03/2021

NXP Semiconductors

GPIO_AD_B1_05 GPIO_AD_B1_06 GPIO_AD_B1_07 GPIO_AD_B1_08 GPIO_AD_B1_09 GPIO_AD_B1_10 GPIO_AD_B1_11 GPIO_AD_B1_12 GPIO_AD_B1_13 GPIO_AD_B1_14 GPIO_AD_B1_15 GPIO_B0_00 GPIO_B0_01 GPIO_B0_02 GPIO_B0_03 GPIO_B0_04 GPIO_B0_05 GPIO_B0_06 GPIO_B0_07 GPIO_B0_08 GPIO_B0_09

Package information and contact assignments

Table 84. 10 x 10 mm functional contact assignments (continued)

K12 NVCC_GPIO Digital GPIO
J12 NVCC_GPIO Digital GPIO
K10 NVCC_GPIO Digital GPIO
H13 NVCC_GPIO Digital GPIO
M13 NVCC_GPIO Digital GPIO
L13 NVCC_GPIO Digital GPIO
J13 NVCC_GPIO Digital GPIO
H12 NVCC_GPIO Digital GPIO
H11 NVCC_GPIO Digital GPIO
G12 NVCC_GPIO Digital GPIO
J14 NVCC_GPIO Digital GPIO
D7 NVCC_GPIO Digital GPIO
E7 NVCC_GPIO Digital GPIO
E8 NVCC_GPIO Digital GPIO
D8 NVCC_GPIO Digital GPIO
C8 NVCC_GPIO Digital GPIO
B8 NVCC_GPIO Digital GPIO
A8 NVCC_GPIO Digital GPIO
A9 NVCC_GPIO Digital GPIO
B9 NVCC_GPIO Digital GPIO
C9 NVCC_GPIO Digital GPIO

ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5

GPIO1.IO[21] GPIO1.IO[22] GPIO1.IO[23] GPIO1.IO[24] GPIO1.IO[25] GPIO1.IO[26] GPIO1.IO[27] GPIO1.IO[28] GPIO1.IO[29] GPIO1.IO[30] GPIO1.IO[31] GPIO2.IO[0] GPIO2.IO[1] GPIO2.IO[2] GPIO2.IO[3] GPIO2.IO[4] GPIO2.IO[5] GPIO2.IO[6] GPIO2.IO[7] GPIO2.IO[8] GPIO2.IO[9]

Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input

Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
100 K PD
100 K PD
100 K PD
100 K PD
100 K PD
100 K PD

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 3, 03/2021

NXP Semiconductors

Package information and contact assignments

GPIO_B0_10 GPIO_B0_11 GPIO_B0_12 GPIO_B0_13 GPIO_B0_14 GPIO_B0_15 GPIO_B1_00 GPIO_B1_01 GPIO_B1_02 GPIO_B1_03 GPIO_B1_04 GPIO_B1_05 GPIO_B1_06 GPIO_B1_07 GPIO_B1_08 GPIO_B1_09 GPIO_B1_10 GPIO_B1_11 GPIO_B1_12 GPIO_B1_13 GPIO_B1_14

Table 84. 10 x 10 mm functional contact assignments (continued)

D9 NVCC_GPIO Digital ALT5 GPIO

A10 NVCC_GPIO Digital ALT5 GPIO

C10 NVCC_GPIO Digital GPIO

ALT5

D10 NVCC_GPIO Digital GPIO

ALT5

E10 NVCC_GPIO Digital ALT5 GPIO

E11 NVCC_GPIO Digital ALT5 GPIO

A11 NVCC_GPIO Digital ALT5 GPIO

B11 NVCC_GPIO Digital ALT5 GPIO

C11 NVCC_GPIO Digital ALT5 GPIO

D11 NVCC_GPIO Digital ALT5 GPIO

E12 NVCC_GPIO Digital ALT5 GPIO

D12 NVCC_GPIO Digital GPIO

ALT5

C12 NVCC_GPIO Digital GPIO

ALT5

B12 NVCC_GPIO Digital ALT5 GPIO

A12 NVCC_GPIO Digital ALT5 GPIO

A13 NVCC_GPIO Digital ALT5 GPIO

B13 NVCC_GPIO Digital ALT5 GPIO

C13 NVCC_GPIO Digital GPIO

ALT5

D13 NVCC_GPIO Digital GPIO

ALT5

D14 NVCC_GPIO Digital GPIO

ALT5

C14 NVCC_GPIO Digital GPIO

ALT5

GPIO2.IO[10] GPIO2.IO[11] GPIO2.IO[12] GPIO2.IO[13] GPIO2.IO[14] GPIO2.IO[15] GPIO2.IO[16] GPIO2.IO[17] GPIO2.IO[18] GPIO2.IO[19] GPIO2.IO[20] GPIO2.IO[21] GPIO2.IO[22] GPIO2.IO[23] GPIO2.IO[24] GPIO2.IO[25] GPIO2.IO[26] GPIO2.IO[27] GPIO2.IO[28] GPIO2.IO[29] GPIO2.IO[30]

Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input

100 K PD
100 K PD
100 K PD
100 K PD
100 K PD
100 K PD
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 3, 03/2021

NXP Semiconductors

GPIO_B1_15 GPIO_EMC_00 GPIO_EMC_01 GPIO_EMC_02 GPIO_EMC_03 GPIO_EMC_04 GPIO_EMC_05 GPIO_EMC_06 GPIO_EMC_07 GPIO_EMC_08 GPIO_EMC_09 GPIO_EMC_10 GPIO_EMC_11 GPIO_EMC_12 GPIO_EMC_13 GPIO_EMC_14 GPIO_EMC_15 GPIO_EMC_16 GPIO_EMC_17 GPIO_EMC_18 GPIO_EMC_19

Package information and contact assignments

Table 84. 10 x 10 mm functional contact assignments (continued)

B14 NVCC_GPIO Digital ALT5 GPIO
E3 NVCC_EMC Digital ALT5 GPIO
F3 NVCC_EMC Digital ALT5 GPIO
F4 NVCC_EMC Digital ALT5 GPIO
G4 NVCC_EMC Digital ALT5 GPIO
F2 NVCC_EMC Digital ALT5 GPIO
G5 NVCC_EMC Digital ALT5 GPIO
H5 NVCC_EMC Digital ALT5 GPIO
H4 NVCC_EMC Digital ALT5 GPIO
H3 NVCC_EMC Digital ALT5 GPIO
C2 NVCC_EMC Digital ALT5 GPIO
G1 NVCC_EMC Digital ALT5 GPIO
G3 NVCC_EMC Digital ALT5 GPIO
H1 NVCC_EMC Digital ALT5 GPIO
A6 NVCC_EMC Digital ALT5 GPIO
B6 NVCC_EMC Digital ALT5 GPIO
B1 NVCC_EMC Digital ALT5 GPIO
A5 NVCC_EMC Digital ALT5 GPIO
A4 NVCC_EMC Digital ALT5 GPIO
B2 NVCC_EMC Digital ALT5 GPIO
B4 NVCC_EMC Digital ALT5 GPIO

GPIO2.IO[31] GPIO4.IO[0] GPIO4.IO[1] GPIO4.IO[2] GPIO4.IO[3] GPIO4.IO[4] GPIO4.IO[5] GPIO4.IO[6] GPIO4.IO[7] GPIO4.IO[8] GPIO4.IO[9] GPIO4.IO[10] GPIO4.IO[11] GPIO4.IO[12] GPIO4.IO[13] GPIO4.IO[14] GPIO4.IO[15] GPIO4.IO[16] GPIO4.IO[17] GPIO4.IO[18] GPIO4.IO[19]

Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Output1 Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 3, 03/2021

NXP Semiconductors

Package information and contact assignments

GPIO_EMC_20 GPIO_EMC_21 GPIO_EMC_22 GPIO_EMC_23 GPIO_EMC_24 GPIO_EMC_25 GPIO_EMC_26 GPIO_EMC_27 GPIO_EMC_28 GPIO_EMC_29 GPIO_EMC_30 GPIO_EMC_31 GPIO_EMC_32 GPIO_EMC_33 GPIO_EMC_34 GPIO_EMC_35 GPIO_EMC_36 GPIO_EMC_37 GPIO_EMC_38 GPIO_EMC_39 GPIO_EMC_40

Table 84. 10 x 10 mm functional contact assignments (continued)

A3 NVCC_EMC Digital ALT5 GPIO
C1 NVCC_EMC Digital ALT5 GPIO
F1 NVCC_EMC Digital ALT5 GPIO
G2 NVCC_EMC Digital ALT5 GPIO
D3 NVCC_EMC Digital ALT5 GPIO
D2 NVCC_EMC Digital ALT5 GPIO
B3 NVCC_EMC Digital ALT5 GPIO
A2 NVCC_EMC Digital ALT5 GPIO
D1 NVCC_EMC Digital ALT5 GPIO
E1 NVCC_EMC Digital ALT5 GPIO
C6 NVCC_EMC Digital ALT5 GPIO
C5 NVCC_EMC Digital ALT5 GPIO
D5 NVCC_EMC Digital ALT5 GPIO
C4 NVCC_EMC Digital ALT5 GPIO
D4 NVCC_EMC Digital ALT5 GPIO
E5 NVCC_EMC Digital ALT5 GPIO
C3 NVCC_EMC Digital ALT5 GPIO
E4 NVCC_EMC Digital ALT5 GPIO
D6 NVCC_EMC Digital ALT5 GPIO
B7 NVCC_EMC Digital ALT5 GPIO
A7 NVCC_EMC Digital ALT5 GPIO

GPIO4.IO[20] GPIO4.IO[21] GPIO4.IO[22] GPIO4.IO[23] GPIO4.IO[24] GPIO4.IO[25] GPIO4.IO[26] GPIO4.IO[27] GPIO4.IO[28] GPIO4.IO[29] GPIO4.IO[30] GPIO4.IO[31] GPIO3.IO[18] GPIO3.IO[19] GPIO3.IO[20] GPIO3.IO[21] GPIO3.IO[22] GPIO3.IO[23] GPIO3.IO[24] GPIO3.IO[25] GPIO3.IO[26]

Input Keeper

Input Input

100 K PD
Keeper

Input Keeper

Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input

Keeper Keeper Keeper Keeper Keeper Keeper Keeper 100 K
PD Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 3, 03/2021

NXP Semiconductors

GPIO_EMC_41 GPIO_SD_B0_00 GPIO_SD_B0_01 GPIO_SD_B0_02 GPIO_SD_B0_03 GPIO_SD_B0_04 GPIO_SD_B0_05 GPIO_SD_B1_00 GPIO_SD_B1_01 GPIO_SD_B1_02 GPIO_SD_B1_03 GPIO_SD_B1_04 GPIO_SD_B1_05 GPIO_SD_B1_06 GPIO_SD_B1_07 GPIO_SD_B1_08 GPIO_SD_B1_09 GPIO_SD_B1_10 GPIO_SD_B1_11 ONOFF PMIC_ON_REQ

Package information and contact assignments

Table 84. 10 x 10 mm functional contact assignments (continued)

C7 NVCC_EMC Digital ALT5 GPIO3.IO[27] Input Keeper Input Keeper GPIO

J4 NVCC_SD0 Digital ALT5 GPIO3.IO[12] Input Keeper Input Keeper GPIO

J3 NVCC_SD0 Digital ALT5 GPIO3.IO[13] Input Keeper Input Keeper GPIO

J1 NVCC_SD0 Digital ALT5 GPIO3.IO[14] Input Keeper Input Keeper GPIO

K1 NVCC_SD0 Digital ALT5 GPIO3.IO[15] Input Keeper Input Keeper GPIO

H2 NVCC_SD0 Digital ALT5 GPIO3.IO[16] Input Keeper Input Keeper GPIO

J2 NVCC_SD0 Digital ALT5 GPIO3.IO[17] Input Keeper Input Keeper GPIO

L5 NVCC_SD1 Digital ALT5 GPIO3.IO[0] GPIO

Input Keeper Input Keeper

M5 NVCC_SD1 Digital ALT5 GPIO

GPIO3.IO[1]

Input Keeper Input Keeper

M3 NVCC_SD1 Digital ALT5 GPIO

GPIO3.IO[2]

Input Keeper Input Keeper

M4 NVCC_SD1 Digital ALT5 GPIO

GPIO3.IO[3]

Input Keeper Input Keeper

P2 NVCC_SD1 Digital ALT5 GPIO

GPIO3.IO[4]

Input Keeper Input Keeper

N3 NVCC_SD1 Digital ALT5 GPIO

GPIO3.IO[5]

Input Keeper Input Keeper

L3 NVCC_SD1 Digital ALT5 GPIO3.IO[6] GPIO

Input Keeper Input Keeper

L4 NVCC_SD1 Digital ALT5 GPIO3.IO[7] GPIO

Input Keeper Input Keeper

P3 NVCC_SD1 Digital ALT5 GPIO

GPIO3.IO[8]

Input Keeper Input Keeper

N4 NVCC_SD1 Digital ALT5 GPIO

GPIO3.IO[9]

Input Keeper Input Keeper

P4 NVCC_SD1 Digital ALT5 GPIO3.IO[01] Input Keeper Input Keeper GPIO

P5 NVCC_SD1 Digital ALT5 GPIO3.IO[11] Input Keeper Input Keeper GPIO

M6 VDD_SNVS_I Digital ALT0

GPIO

ONOFF

Input

100 K PU

Input

100 K PU

K7 VDD_SNVS_I Digital ALT0 SNVS_LP.PMIC_ Output 100 K Output 100 K

GPIO

ON_REQ

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 3, 03/2021

NXP Semiconductors

Package information and contact assignments

Table 84. 10 x 10 mm functional contact assignments (continued)

PMIC_STBY_REQ L7 VDD_SNVS_I Digital ALT0 CCM.PMIC_VST Output 100 K Output 100 K

GPIO

BY_REQ

(PKE

disabled

)

POR_B

M7 VDD_SNVS_I Digital ALT0

GPIO

SRC.POR_B

Input

100 K PU

Input

100 K PU

RTC_XTALI

RTC_XTALO

TEST_MODE

K6 VDD_SNVS_I Digital ALT0 TCU.TEST_MO Input

GPIO

100 K PU

Input

100 K PU

USB_OTG1_CHD N12

USB_OTG1_DN

USB_OTG1_DP

USB_OTG1_VBU N6

USB_OTG2_DN

USB_OTG2_DP

USB_OTG2_VBU P6

XTALI

P11

XTALO

N11

WAKEUP

L6 VDD_SNVS_I Digital ALT5

GPIO

GPIO5.IO[0]

1 This pin output is in a high level until the system reset is complete.

Input

100 K PU

Input

100 K PU

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 3, 03/2021

NXP Semiconductors

Package information and contact assignments
7.1.3 10 x 10 mm, 0.65 mm pitch, ball map
Table 85 shows the 10 x 10 mm, 0.65 mm pitch ball map for the i.MX RT1064.
Table 85. 10x10 mm, 0.65 mm pitch, ball map

NXP Semiconductors

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 3, 03/2021

GPIO_EMC_10 GPIO_EMC_22 GPIO_EMC_29 GPIO_EMC_28 GPIO_EMC_21 GPIO_EMC_15

VSS

GPIO_EMC_23 GPIO_EMC_04

VSS

GPIO_EMC_25 GPIO_EMC_09 GPIO_EMC_18 GPIO_EMC_27 2

GPIO_EMC_11 GPIO_EMC_01 GPIO_EMC_00 GPIO_EMC_24 GPIO_EMC_36 GPIO_EMC_26 GPIO_EMC_20 3

GPIO_EMC_03 GPIO_EMC_02 GPIO_EMC_37 GPIO_EMC_34 GPIO_EMC_33 GPIO_EMC_19 GPIO_EMC_17 4

GPIO_EMC_05 NVCC_EMC GPIO_EMC_35 GPIO_EMC_32 GPIO_EMC_31

VSS

GPIO_EMC_16 5

VDD_SOC_IN VDD_SOC_IN

NVCC_EMC GPIO_EMC_38 GPIO_EMC_30 GPIO_EMC_14 GPIO_EMC_13 6

VSS

VDD_SOC_IN

GPIO_B0_01

GPIO_B0_00 GPIO_EMC_41 GPIO_EMC_39 GPIO_EMC_40 7

VSS

VDD_SOC_IN

GPIO_B0_02

GPIO_B0_03 GPIO_B0_04 GPIO_B0_05 GPIO_B0_06 8

VDD_SOC_IN VDD_SOC_IN

NVCC_GPIO

GPIO_B0_10 GPIO_B0_09 GPIO_B0_08 GPIO_B0_07 9

GPIO_AD_B0_11 NVCC_GPIO

GPIO_B0_14 GPIO_B0_13 GPIO_B0_12

VSS

GPIO_B0_11 10

GPIO_AD_B0_03 GPIO_AD_B0_04 GPIO_B0_15

GPIO_B1_03 GPIO_B1_02 GPIO_B1_01 GPIO_B1_00 11

GPIO_AD_B1_14 GPIO_AD_B0_07 GPIO_B1_04

GPIO_B1_05 GPIO_B1_06 GPIO_B1_07 GPIO_B1_08 12

GPIO_AD_B0_10 GPIO_AD_B0_08

VSS

GPIO_B1_12 GPIO_B1_11 GPIO_B1_10 GPIO_B1_09 13

GPIO_AD_B0_05 GPIO_AD_B0_09 GPIO_AD_B0_06 GPIO_B1_13 GPIO_B1_14 GPIO_B1_15

VSS

Package information and contact assignments Table 85. 10x10 mm, 0.65 mm pitch, ball map (continued)

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 3, 03/2021

VSS

DCDC_GND

DCDC_LP

DCDC_IN

GPIO_SD_B0_03 GPIO_SD_B0_02 GPIO_EMC_12

2 GPIO_SD_B1_04

DCDC_GND

DCDC_LP

DCDC_IN

VSS

GPIO_SD_B0_05 GPIO_SD_B0_04

3 GPIO_SD_B1_08 GPIO_SD_B1_05 GPIO_SD_B1_02 GPIO_SD_B1_06 DCDC_PSWITCH GPIO_SD_B0_01 GPIO_EMC_08

4 GPIO_SD_B1_10 GPIO_SD_B1_09 GPIO_SD_B1_03 GPIO_SD_B1_07 DCDC__IN_Q GPIO_SD_B0_00 GPIO_EMC_07

5 GPIO_SD_B1_11

VSS

GPIO_SD_B1_01 GPIO_SD_B1_00 NVCC_SD1

DCDC_SENSE GPIO_EMC_06

6 USB_OTG2_VBUS USB_OTG1_VBUS

ONOFF

WAKEUP

TEST_MODE

NVCC_SD0

VDD_SOC_IN

7 USB_OTG2_DP

USB_OTG2_DN

POR_B

PMIC_STBY_REQ PMIC_ON_REQ

VSS

8 VDD_HIGH_CAP

VSS

USB_OTG1_DN USB_OTG1_DP VDD_USB_CAP

VSS

RTC_XTALO

RTC_XTALI

VDD_SNVS_IN

VSS

NGND_KEL0

VDD_SOC_IN VDD_SOC_IN

NVCC_PLL

GPANAIO

VDD_SNVS_CAP GPIO_AD_B0_15 GPIO_AD_B1_07 NVCC_GPIO GPIO_AD_B0_01

XTALI

XTALO

GPIO_AD_B0_02 GPIO_AD_B1_02 GPIO_AD_B1_01 GPIO_AD_B1_00 GPIO_AD_B1_13

12 VDD_HIGH_IN USB_OTG1_CHD_B GPIO_AD_B1_03 GPIO_AD_B1_04 GPIO_AD_B1_05 GPIO_AD_B1_06 GPIO_AD_B1_12

13 CCM_CLK1_N

CCM_CLK1_P GPIO_AD_B1_09 GPIO_AD_B1_10

VSS

GPIO_AD_B1_11 GPIO_AD_B1_08

VSS

VDDA_ADC_3P3 GPIO_AD_B0_00 GPIO_AD_B0_13 GPIO_AD_B0_12 GPIO_AD_B1_15 GPIO_AD_B0_14

NXP Semiconductors

Package information and contact assignments
7.2 12 x 12 mm package information
7.2.1 12 x 12 mm, 0.8 mm pitch, ball matrix
Figure 54 shows the top, bottom, and side views of the 12 x 12 mm MAPBGA package.

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 3, 03/2021

NXP Semiconductors

Package information and contact assignments

Figure 54. 12 x 12 mm BGA, case x package top, bottom, and side Views

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Package information and contact assignments

7.2.2 12 x 12 mm supplies contact assignments and functional contact assignments
Table 86 shows the device connection list for ground, sense, and reference contact signals.
Table 86. 12 x 12 mm supplies contact assignment

Supply Rail Name

Ball(s) Position(s)

DCDC_IN

L1, L2

DCDC_IN_Q

DCDC_GND

N1, N2

DCDC_LP

M1, M2

DCDC_PSWITCH

DCDC_SENSE

GPANAIO

N10

NGND_KEL0

NVCC_EMC

E6, F5

NVCC_GPIO

E9, F10, J10

NVCC_PLL

P10

NVCC_SD0

NVCC_SD1

VDDA_ADC_3P3

N14

VDD_HIGH_CAP

VDD_HIGH_IN

P12

VDD_SNVS_CAP

M10

VDD_SNVS_IN

VDD_SOC_IN

F6, F7, F8, F9, G6, G9, H6, H9, J9

VDD_USB_CAP

VSS

A1, A14, B5, B10, E2, E13, G7, G8, H7, H8, J7, J8, K2, K13, L9, N5, N8, P1, P14

Remark -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --

Table 87 shows an alpha-sorted list of functional contact assignments for the 12 x 12 mm package.
Table 87. 12 x 12 mm functional contact assignments

12 x

Ball Name

Ball

CCM_CLK1_N P13 CCM_CLK1_P N13

Power Group
-- --

Ball Type
-- --

Default Setting

Default Mode
--
--

Default Function
CCM_CLK1_N
CCM_CLK1_P

Input/ Output
--
--

Default setting on Reset

Value

Input/ Output

Value

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Package information and contact assignments

GPIO_AD_B0_0 0
GPIO_AD_B0_0 1
GPIO_AD_B0_0 2
GPIO_AD_B0_0 3
GPIO_AD_B0_0 4
GPIO_AD_B0_0 5
GPIO_AD_B0_0 6
GPIO_AD_B0_0 7
GPIO_AD_B0_0 8
GPIO_AD_B0_0 9
GPIO_AD_B0_1 0
GPIO_AD_B0_1 1
GPIO_AD_B0_1 2
GPIO_AD_B0_1 3
GPIO_AD_B0_1 4
GPIO_AD_B0_1 5
GPIO_AD_B1_0 0
GPIO_AD_B1_0 1
GPIO_AD_B1_0 2
GPIO_AD_B1_0 3
GPIO_AD_B1_0 4

Table 87. 12 x 12 mm functional contact assignments (continued)

M14 NVCC_GPIO Digital GPIO
H10 NVCC_GPIO Digital GPIO
M11 NVCC_GPIO Digital GPIO
G11 NVCC_GPIO Digital GPIO
F11 NVCC_GPIO Digital GPIO
G14 NVCC_GPIO Digital GPIO
E14 NVCC_GPIO Digital GPIO
F12 NVCC_GPIO Digital GPIO
F13 NVCC_GPIO Digital GPIO
F14 NVCC_GPIO Digital GPIO
G13 NVCC_GPIO Digital GPIO
G10 NVCC_GPIO Digital GPIO
K14 NVCC_GPIO Digital GPIO
L14 NVCC_GPIO Digital GPIO
H14 NVCC_GPIO Digital GPIO
L10 NVCC_GPIO Digital GPIO
J11 NVCC_GPIO Digital GPIO
K11 NVCC_GPIO Digital GPIO
L11 NVCC_GPIO Digital GPIO
M12 NVCC_GPIO Digital GPIO
L12 NVCC_GPIO Digital GPIO

ALT5

GPIO1.IO[0]

Input Keeper Input Keeper

ALT5

GPIO1.IO[1]

Input Keeper Input Keeper

ALT5

GPIO1.IO[2]

Input Keeper Input Keeper

ALT5

GPIO1.IO[3]

Input Keeper Input Keeper

ALT0 ALT0 ALT0

SRC.BOOT.MOD E[0]
SRC.BOOT.MOD E[1]
JTAG.MUX.TMS

Input 100 K PD Input 100 K PD Input 100 K PD Input 100 K PD Input 47 K PU Input 47 K PU

ALT0 JTAG.MUX.TCK Input 47 K PU Input 100 K PD

ALT0 JTAG.MUX.MOD Input 100 K PU Input 100 K PD

ALT0 JTAG.MUX.TDI Input 47 K PU Input 47 K PU

ALT0 JTAG.MUX.TDO Input Keeper Input Keeper

ALT0 ALT5

JTAG.MUX.TRST B
GPIO1.IO[12]

Input Input

47 K PU Keeper

Input Input

47 K PU Keeper

ALT5 GPIO1.IO[13] Input Keeper Input Keeper

ALT5 GPIO1.IO[14] Input Keeper Input Keeper

ALT5 GPIO1.IO[15] Input Keeper Input Keeper

ALT5 GPIO1.IO[16] Input Keeper Input Keeper

ALT5 GPIO1.IO[17] Input Keeper Input Keeper

ALT5 GPIO1.IO[18] Input Keeper Input Keeper

ALT5 GPIO1.IO[19] Input Keeper Input Keeper

ALT5 GPIO1.IO[20] Input Keeper Input Keeper

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Package information and contact assignments

GPIO_AD_B1_0 5 GPIO_AD_B1_0 6 GPIO_AD_B1_0 7 GPIO_AD_B1_0 8 GPIO_AD_B1_0 9 GPIO_AD_B1_1 0 GPIO_AD_B1_1 1 GPIO_AD_B1_1 2 GPIO_AD_B1_1 3 GPIO_AD_B1_1 4 GPIO_AD_B1_1 5 GPIO_B0_00
GPIO_B0_01
GPIO_B0_02
GPIO_B0_03
GPIO_B0_04
GPIO_B0_05
GPIO_B0_06
GPIO_B0_07
GPIO_B0_08
GPIO_B0_09

Table 87. 12 x 12 mm functional contact assignments (continued)

ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5

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Package information and contact assignments

Table 87. 12 x 12 mm functional contact assignments (continued)

D9 NVCC_GPIO Digital GPIO
A10 NVCC_GPIO Digital GPIO
C10 NVCC_GPIO Digital GPIO
D10 NVCC_GPIO Digital GPIO
E10 NVCC_GPIO Digital GPIO
E11 NVCC_GPIO Digital GPIO
A11 NVCC_GPIO Digital GPIO
B11 NVCC_GPIO Digital GPIO
C11 NVCC_GPIO Digital GPIO
D11 NVCC_GPIO Digital GPIO
E12 NVCC_GPIO Digital GPIO
D12 NVCC_GPIO Digital GPIO
C12 NVCC_GPIO Digital GPIO
B12 NVCC_GPIO Digital GPIO
A12 NVCC_GPIO Digital GPIO
A13 NVCC_GPIO Digital GPIO
B13 NVCC_GPIO Digital GPIO
C13 NVCC_GPIO Digital GPIO
D13 NVCC_GPIO Digital GPIO
D14 NVCC_GPIO Digital GPIO
C14 NVCC_GPIO Digital GPIO

ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5

Input 100 K PD Input 100 K PD Input 100 K PD Input 100 K PD Input 100 K PD Input 100 K PD Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper

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Package information and contact assignments

Table 87. 12 x 12 mm functional contact assignments (continued)

B14 NVCC_GPIO Digital GPIO
E3 NVCC_EMC Digital GPIO
F3 NVCC_EMC Digital GPIO
F4 NVCC_EMC Digital GPIO
G4 NVCC_EMC Digital GPIO
F2 NVCC_EMC Digital GPIO
G5 NVCC_EMC Digital GPIO
H5 NVCC_EMC Digital GPIO
H4 NVCC_EMC Digital GPIO
H3 NVCC_EMC Digital GPIO
C2 NVCC_EMC Digital GPIO
G1 NVCC_EMC Digital GPIO
G3 NVCC_EMC Digital GPIO
H1 NVCC_EMC Digital GPIO
A6 NVCC_EMC Digital GPIO
B6 NVCC_EMC Digital GPIO
B1 NVCC_EMC Digital GPIO
A5 NVCC_EMC Digital GPIO
A4 NVCC_EMC Digital GPIO
B2 NVCC_EMC Digital GPIO
B4 NVCC_EMC Digital GPIO

ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5 ALT5

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Package information and contact assignments

Table 87. 12 x 12 mm functional contact assignments (continued)

Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input 100 K PD Input 100 K PD Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper

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NXP Semiconductors

GPIO_EMC_41
GPIO_SD_B0_0 0
GPIO_SD_B0_0 1
GPIO_SD_B0_0 2
GPIO_SD_B0_0 3
GPIO_SD_B0_0 4
GPIO_SD_B0_0 5
GPIO_SD_B1_0 0
GPIO_SD_B1_0 1
GPIO_SD_B1_0 2
GPIO_SD_B1_0 3
GPIO_SD_B1_0 4
GPIO_SD_B1_0 5
GPIO_SD_B1_0 6
GPIO_SD_B1_0 7
GPIO_SD_B1_0 8
GPIO_SD_B1_0 9
GPIO_SD_B1_1 0
GPIO_SD_B1_1 1
ONOFF
PMIC_ON_REQ

Package information and contact assignments

Table 87. 12 x 12 mm functional contact assignments (continued)

C7 NVCC_EMC Digital GPIO

J4 NVCC_SD0 Digital GPIO

J3 NVCC_SD0 Digital GPIO

J1 NVCC_SD0 Digital GPIO

K1 NVCC_SD0 Digital GPIO

H2 NVCC_SD0 Digital GPIO

J2 NVCC_SD0 Digital GPIO

L5 NVCC_SD1 Digital GPIO

M5 NVCC_SD1 Digital GPIO

M3 NVCC_SD1 Digital GPIO

M4 NVCC_SD1 Digital GPIO

P2 NVCC_SD1 Digital GPIO

N3 NVCC_SD1 Digital GPIO

L3 NVCC_SD1 Digital GPIO

L4 NVCC_SD1 Digital GPIO

P3 NVCC_SD1 Digital GPIO

N4 NVCC_SD1 Digital GPIO

P4 NVCC_SD1 Digital GPIO

P5 NVCC_SD1 Digital GPIO

M6 VDD_SNVS_I Digital

GPIO

K7 VDD_SNVS_I Digital

GPIO

ALT5 GPIO3.IO[27] Input Keeper Input Keeper

ALT5 GPIO3.IO[12] Input Keeper Input Keeper

ALT5 GPIO3.IO[13] Input Keeper Input Keeper

ALT5 GPIO3.IO[14] Input Keeper Input Keeper

ALT5 GPIO3.IO[15] Input Keeper Input Keeper

ALT5 GPIO3.IO[16] Input Keeper Input Keeper

ALT5 GPIO3.IO[17] Input Keeper Input Keeper

ALT5

GPIO3.IO[0]

Input Keeper Input Keeper

ALT5

GPIO3.IO[1]

Input Keeper Input Keeper

ALT5

GPIO3.IO[2]

Input Keeper Input Keeper

ALT5

GPIO3.IO[3]

Input Keeper Input Keeper

ALT5

GPIO3.IO[4]

Input Keeper Input Keeper

ALT5

GPIO3.IO[5]

Input Keeper Input Keeper

ALT5

GPIO3.IO[6]

Input Keeper Input Keeper

ALT5

GPIO3.IO[7]

Input Keeper Input Keeper

ALT5

GPIO3.IO[8]

Input Keeper Input Keeper

ALT5

GPIO3.IO[9]

Input Keeper Input Keeper

ALT5 GPIO3.IO[01] Input Keeper Input Keeper

ALT5

GPIO3.IO[11]

Input Keeper Input Keeper

ALT0

ONOFF

Input 100 K PU Input 100 K PU

ALT0 SNVS_LP.PMIC_ Output 100 K PU Output 100 K PU ON_REQ

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Package information and contact assignments

Table 87. 12 x 12 mm functional contact assignments (continued)

PMIC_STBY_RE L7 VDD_SNVS_I Digital

GPIO

ALT0

CCM.PMIC_VST Output 100 K PU Output 100 K PU

BY_REQ

(PKE

disabled)

POR_B

M7 VDD_SNVS_I Digital

GPIO

ALT0

SRC.POR_B

Input 100 K PU Input 100 K PU

RTC_XTALI

RTC_XTALO

TEST_MODE

K6 VDD_SNVS_I Digital

GPIO

ALT0 TCU.TEST_MOD Input 100 K PU Input 100 K PU E

USB_OTG1_CH N12

D_B

USB_OTG1_DN M8

USB_OTG1_DP L8

USB_OTG1_VB N6

USB_OTG2_DN N7

USB_OTG2_DP P7

USB_OTG2_VB P6

XTALI

P11

XTALO

N11

WAKEUP

L6 VDD_SNVS_I Digital

GPIO

ALT5

GPIO5.IO[0]

1 This pin output is in a high level until the system reset is complete.

Input 100 K PU Input 100 K PU

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Package information and contact assignments
7.2.3 12 x 12 mm, 0.8 mm pitch, ball map
Table 85 shows the 10 x 10 mm, 0.8 mm pitch ball map for the i.MX RT1064.
Table 88. 12 x 12 mm, 0.8 mm pitch, ball map

NXP Semiconductors

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 3, 03/2021

GPIO_EMC_10 GPIO_EMC_22 GPIO_EMC_29 GPIO_EMC_28 GPIO_EMC_21 GPIO_EMC_15

VSS

GPIO_EMC_23 GPIO_EMC_04

VSS

GPIO_EMC_25 GPIO_EMC_09 GPIO_EMC_18 GPIO_EMC_27 2

GPIO_EMC_11 GPIO_EMC_01 GPIO_EMC_00 GPIO_EMC_24 GPIO_EMC_36 GPIO_EMC_26 GPIO_EMC_20 3

GPIO_EMC_03 GPIO_EMC_02 GPIO_EMC_37 GPIO_EMC_34 GPIO_EMC_33 GPIO_EMC_19 GPIO_EMC_17 4

GPIO_EMC_05 NVCC_EMC GPIO_EMC_35 GPIO_EMC_32 GPIO_EMC_31

VSS

GPIO_EMC_16 5

VDD_SOC_IN VDD_SOC_IN

NVCC_EMC GPIO_EMC_38 GPIO_EMC_30 GPIO_EMC_14 GPIO_EMC_13 6

VSS

VDD_SOC_IN

GPIO_B0_01

GPIO_B0_00 GPIO_EMC_41 GPIO_EMC_39 GPIO_EMC_40 7

VSS

VDD_SOC_IN

GPIO_B0_02

GPIO_B0_03 GPIO_B0_04 GPIO_B0_05 GPIO_B0_06 8

VDD_SOC_IN VDD_SOC_IN

NVCC_GPIO

GPIO_B0_10 GPIO_B0_09 GPIO_B0_08 GPIO_B0_07 9

GPIO_AD_B0_11 NVCC_GPIO

GPIO_B0_14 GPIO_B0_13 GPIO_B0_12

VSS

GPIO_B0_11 10

GPIO_AD_B0_03 GPIO_AD_B0_04 GPIO_B0_15

GPIO_B1_03 GPIO_B1_02 GPIO_B1_01 GPIO_B1_00 11

GPIO_AD_B1_14 GPIO_AD_B0_07 GPIO_B1_04

GPIO_B1_05 GPIO_B1_06 GPIO_B1_07 GPIO_B1_08 12

GPIO_AD_B0_10 GPIO_AD_B0_08

VSS

GPIO_B1_12 GPIO_B1_11 GPIO_B1_10 GPIO_B1_09 13

GPIO_AD_B0_05 GPIO_AD_B0_09 GPIO_AD_B0_06 GPIO_B1_13 GPIO_B1_14 GPIO_B1_15

VSS

109

Package information and contact assignments Table 88. 12 x 12 mm, 0.8 mm pitch, ball map (continued)

110

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 3, 03/2021

VSS

DCDC_GND

DCDC_LP

DCDC_IN

GPIO_SD_B0_03 GPIO_SD_B0_02 GPIO_EMC_12

2 GPIO_SD_B1_04

DCDC_GND

DCDC_LP

DCDC_IN

VSS

GPIO_SD_B0_05 GPIO_SD_B0_04

3 GPIO_SD_B1_08 GPIO_SD_B1_05 GPIO_SD_B1_02 GPIO_SD_B1_06 DCDC_PSWITCH GPIO_SD_B0_01 GPIO_EMC_08

4 GPIO_SD_B1_10 GPIO_SD_B1_09 GPIO_SD_B1_03 GPIO_SD_B1_07 DCDC__IN_Q GPIO_SD_B0_00 GPIO_EMC_07

5 GPIO_SD_B1_11

VSS

GPIO_SD_B1_01 GPIO_SD_B1_00 NVCC_SD1

DCDC_SENSE GPIO_EMC_06

6 USB_OTG2_VBUS USB_OTG1_VBUS

ONOFF

WAKEUP

TEST_MODE

NVCC_SD0

VDD_SOC_IN

7 USB_OTG2_DP

USB_OTG2_DN

POR_B

PMIC_STBY_REQ PMIC_ON_REQ

VSS

8 VDD_HIGH_CAP

VSS

USB_OTG1_DN USB_OTG1_DP VDD_USB_CAP

VSS

RTC_XTALO

RTC_XTALI

VDD_SNVS_IN

VSS

NGND_KEL0

VDD_SOC_IN VDD_SOC_IN

NVCC_PLL

GPANAIO

VDD_SNVS_CAP GPIO_AD_B0_15 GPIO_AD_B1_07 NVCC_GPIO GPIO_AD_B0_01

XTALI

XTALO

GPIO_AD_B0_02 GPIO_AD_B1_02 GPIO_AD_B1_01 GPIO_AD_B1_00 GPIO_AD_B1_13

12 VDD_HIGH_IN USB_OTG1_CHD_B GPIO_AD_B1_03 GPIO_AD_B1_04 GPIO_AD_B1_05 GPIO_AD_B1_06 GPIO_AD_B1_12

13 CCM_CLK1_N

CCM_CLK1_P GPIO_AD_B1_09 GPIO_AD_B1_10

VSS

GPIO_AD_B1_11 GPIO_AD_B1_08

VSS

VDDA_ADC_3P3 GPIO_AD_B0_00 GPIO_AD_B0_13 GPIO_AD_B0_12 GPIO_AD_B1_15 GPIO_AD_B0_14

NXP Semiconductors

Revision history

8 Revision history

Table 89 provides a revision history for this data sheet.
Table 89. i.MX RT1064 Data Sheet document revision history

Rev. Number

Date

Substantive Change(s)

Rev. 3

03.2021

� Updated the Figure 1, "Part number nomenclature--i.MX RT10XX family" � Updated baud rate of LPUART in the Table 2, i.MX RT1064 modules list � Updated the descriptions of TEST_MODE in the Table 3, Special signal considerations � Added system and bus frequencies in the Table 10, Operating ranges; updated the maximum value
of 3.3 V NVCC_EMC in the Table 10, Operating ranges � Updated the values and units of high-level and low-level output current in the Table 22, Single voltage
GPIO DC parameters � Added Default setting on reset columns and a footnote in the Table 84, 10 x 10 mm functional contact
assignments and Table 87, 12 x 12 mm functional contact assignments

Rev. 2

08/2020

� Changed the MPCore to core in the Section 1.1, Features � Added new part numbers in the Table 1, Ordering information � Updated the Figure 1, "Part number nomenclature--i.MX RT10XX family" � Updated the frequency of RTC OSC in the Table 2, i.MX RT1064 modules list � Updated conditions and maximum current of DCDC_IN in the Table 12, Maximum supply currents � Added a restrictions in the Section 4.2.1.1, Power-up sequence � Added IOH and IOL in the Table 22, Single voltage GPIO DC parameters � Updated the minimum and maximum values in the Table 33, SEMC output timing in SYNC mode � Updated the VDDAD to VDDA in the Table 54, 12-bit ADC operating conditions and Table 55, 12-bit
ADC characteristics (VREFH = VDDA, VREFL = VSSAD)

Rev. 1

12/2019

� Updated ADC and SPI NAND Flash in the Section 1.1, Features; removed DAC from Section 1.1, Features
� Updated ADC and RAM in the Figure 2, "i.MX RT1064 system block diagram" � Updated the RT website link in the Section 1.2, Ordering information � Updated FlexSPI, LCD/CSI/PXP, and SNVS in the Table 1, Ordering information; added KPP, SPI,
XBAR/AOI, CSU, and second package information in the Table 1, Ordering information � Removed tamper detection from the Table 2, i.MX RT1064 modules list � Updated the on-chip termination values of JTAG_TCK and JTAG_MOD in the Table 4, JTAG
Controller interface summary � Updated the Section 4.1.2, Thermal resistance � Changed 528 MHz PLL to System PLL in the Table 16, System PLL's electrical parameters � Changed 480 MHz PLL to USB PLL in the Table 18, USB PLL's electrical parameters � Updated the VDD name of supply voltage conditions column in the Table 54, 12-bit ADC operating
conditions � Updated the Section 4.9.1, LPSPI timing parameters � Updated the Table 82, Boot through UART1 and removed the Table, Booth through UART2 � Updated the Figure 53, "10 x 10 mm BGA, case x package top, bottom, and side Views" � Added the Section 7.2, 12 x 12 mm package information

Rev. 0.1 01/2019 � Removed the word "no" from LCD/CSI/PXP row in the Table 1, Ordering information � Added the Figure 36, "Minimum Sample Time Vs Ras (Cas = 2 pF)", Figure 37, "Minimum Sample Time Vs Ras (Cas = 5 pF)", and Figure 38, "Minimum Sample Time Vs Ras (Cas = 10 pF)"

Rev. 0 10/2018 � Initial version

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 3, 03/2021

NXP Semiconductors

111

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In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors' warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors' specifications such use shall be solely at customer's own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors' standard warranty and NXP Semiconductors' product specifications.
Suitability for use � Automotive Product (Functional Safety) Suitability for use in automotive applications --This NXP product has been qualified for use in automotive applications. It has been developed in accordance with ISO 26262, and has been ASIL-classified accordingly. If this product is used by customer in the development of, or for incorporation into, products or services (a) used in safety critical applications or (b) in which failure could lead to death, personal injury, or severe physical or environmental damage (such products and services hereinafter referred to as "Critical
Table continues on the next page...

Applications"), then customer makes the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, safety, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. As such, customer assumes all risk related to use of any products in Critical Applications and NXP and its suppliers shall not be liable for any such use by customer. Accordingly, customer will indemnify and hold NXP harmless from any claims, liabilities, damages and associated costs and expenses (including attorneys' fees) that NXP may incur related to customer's incorporation of any product in a Critical Application.
Non-automotive products for restricted use in automotive onlySuitability for use in automotive applications -- The use of this NXP Semiconductors product is restricted to automotive applications only. It has not been fully qualified for use in automotive applications. The customer of this NXP Semiconductors product therefore understands and accepts that:
� The Customer shall only use this NXP Semiconductors product for automotive applications.
� This product was not originally designed for automotive use. It will therefore, not be possible to achieve the levels of quality and failure analysis that are normally associated with products explicitly designed for automotive use.
� With respect to test-coverage, this product is not fully compliant to AEC-Q100.
� All product manufacturing locations are certified according to ISO/TS16949.
� Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk.
Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer's sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer's applications and products planned, as well as for the planned application and use of customer's third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products.
NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer's applications or products, or the application or use by customer's third party customer(s). Customer is responsible for doing all necessary testing for the customer's applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer's third party customer(s). NXP does not accept any liability in this respect.
Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device.
Terms and conditions of commerical sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer.
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No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
Hazardous voltage -- Although basic supply voltages of the product may be much lower, circuit voltages up to 60 V may appear when operating this product, depending on settings and application. Customers incorporating or otherwise using these products in applications where such high voltages may appear during operation, assembly, test etc. of such application, do so at their own risk. Customers agree to fully indemnify NXP Semiconductors for any damages resulting from or in connection with such high voltages. Furthermore, customers are drawn to safety standards (IEC 950, EN 60 950, CENELEC, ISO, etc.) and other (legal) requirements applying to such high voltages.
Bare die -- All die are tested on compliance with their related technical specifications as stated in this data sheet up to the point of wafer sawing and are handled in accordance with the NXP Semiconductors storage and transportation conditions. If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post-packing tests performed on individual die or wafers.
NXP Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. Accordingly, NXP Semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify their application in which the die is used. All die sales are conditioned upon and subject to the customer entering into a written die sale agreement with NXP Semiconductors through its legal department.
Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.
Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities.
Evaluation products --This product is provided on an "as is" and "with all faults" basis for evaluation purposes only. NXP Semiconductors, its affiliates and their suppliers expressly disclaim all warranties, whether express, implied or statutory, including but not limited to the implied warranties of non-infringement, merchantability and fitness for a particular purpose. The entire risk as to the quality, or arising out of the use or performance, of this product remains with customer. In no event shall NXP Semiconductors, its affiliates or their suppliers be liable to customer for any special, indirect, consequential, punitive or incidental damages (including without limitation damages for loss of business, business interruption, loss of use, loss of data or information, and the like) arising out the use of or inability to use the product, whether or not based on tort (including negligence), strict liability, breach of contract, breach of warranty or any other theory, even if advised of the possibility of such damages.
Notwithstanding any damages that customer might incur for any reason whatsoever (including without limitation, all damages referenced above and all direct or general damages), the entire liability of NXP Semiconductors, its affiliates and their suppliers and customer's exclusive remedy for all of the foregoing shall be limited to actual damages incurred by customer based on reasonable reliance up to the greater of the amount actually paid by customer for the product or five dollars (US$5.00). The foregoing limitations, exclusions and disclaimers shall apply to the maximum extent permitted by applicable law, even if any remedy fails of its essential purpose.
Translations -- A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions.
NXP, the NXP logo, NXP SECURE CONNECTIONS FOR A SMARTER WORLD, COOLFLUX,EMBRACE, GREENCHIP, HITAG, ICODE, JCOP, LIFE, VIBES, MIFARE, MIFARE CLASSIC, MIFARE DESFire, MIFARE PLUS, MIFARE FLEX, MANTIS, MIFARE ULTRALIGHT, MIFARE4MOBILE, MIGLO, NTAG, ROADLINK, SMARTLX, SMARTMX, STARPLUG, TOPFET, TRENCHMOS, UCODE, Freescale, the Freescale logo, CodeWarrior, ColdFire, ColdFire+, the Energy Efficient Solutions logo, Kinetis, Layerscape, mobileGT, PEG, PowerQUICC, Processor Expert, QorIQ, QorIQ Qonverge, SafeAssure, the SafeAssure logo, StarCore, Symphony, VortiQa, Vybrid, Airfast, BeeKit, BeeStack, CoreNet, Flexis, MXC, Platform in a Package, QUICC Engine, Tower, TurboLink, EdgeScale, EdgeLock, eIQ, and Immersive3D are trademarks of NXP B.V. All other product or service names are the property of their respective owners. AMBA, Arm, Arm7, Arm7TDMI, Arm9, Arm11, Artisan, big.LITTLE, Cordio, CoreLink, CoreSight,
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Cortex, DesignStart, DynamIQ, Jazelle, Keil, Mali, Mbed, Mbed Enabled, NEON, POP, RealView, SecurCore, Socrates, Thumb, TrustZone, ULINK, ULINK2, ULINK-ME, ULINK-PLUS, ULINKpro, �Vision, Versatile are trademarks or registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. The related technology may be protected by any or all of patents, copyrights, designs and trade secrets. All rights reserved. Oracle and Java are registered trademarks of Oracle and/or its affiliates. M, M Mobileye and other Mobileye trademarks or logos appearing herein are trademarks of Mobileye Vision Technologies Ltd. in the United States, the EU and/or other jurisdictions.

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For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 29 April 2021 Document identifier: IMXRT1064CEC