Home › FT245R USB FIFO IC Datasheet

FT245R USB FIFO IC Datasheet

File info: application/pdf · 35 pages · 1.15MB

USB FIFO IC

FT245R USB FIFO IC Datasheet - FTDI

FT245R USB FIFO IC Datasheet USB FIFO IC Datasheet Version 2.15 No.: FT 000052 Clearance No.: FTDI# 39 1.3 USB Compliant The FT245R is fully compliant with the USB 2.0 specification and has been given the USB-IF Test-ID…

Full PDF Document

If the inline viewer fails, it will open the original document in compatibility mode automatically. You can also open the file directly.

Extracted Text

FT245R USB FIFO IC Datasheet USB FIFO IC Datasheet Version 2.15
Document No.: FT_000052 Clearance No.: FTDI# 39
Future Technology Devices International Ltd.
FT245R USB FIFO IC Datasheet

The FT245R is a USB to parallel FIFO interface with the following advanced features:

Single chip USB to parallel FIFO bidirectional data transfer interface.

Entire USB protocol handled on the chip. No

USB specific firmware programming required.

Fully integrated 1024 bit EEPROM storing

device descriptors and FIFO I/O configuration.

Fully integrated USB termination resistors.

Fully integrated clock generation with no

external crystal required.

Data transfer rates up to 1Mbyte / second.

128 byte receive buffer and 256 byte transmit

buffer utilising buffer smoothing technology to

allow for high data throughput.

FTDI's royalty-free Virtual Com Port (VCP) and

Direct (D2XX) drivers eliminate the

requirement for USB driver development in

most cases.

Unique USB FTDIChip-IDTM feature.

Configurable FIFO interface I/O pins.

Synchronous and asynchronous bit bang

interface options.

Device supplied pre-programmed with unique USB serial number.
Supports bus powered, self-powered and highpower bus powered USB configurations.
Integrated +3.3V level converter for USB I/O.
Integrated level converter on FIFO interface for interfacing to external logic running at between +1.8V and +5V.
True 5V/3.3V/2.8V/1.8V CMOS drive output and TTL input.
Configurable I/O pin output drive strength.
Integrated power-on-reset circuit.
Fully integrated AVCC supply filtering - no external filtering required.
+3.3V (using external oscillator) to +5.25V (using internal oscillator) Single Supply Operation.
Low operating and USB suspend current.
Low USB bandwidth consumption.
UHCI/OHCI/EHCI host controller compatible.
USB 2.0 Full Speed compatible.
-40�C to 85�C extended operating temperature range.
Available in compact Pb-free 28 Pin SSOP and QFN32 packages (both RoHS compliant).

Neither the whole nor any part of the information contained in, or the product described in this manual, may be adapted or reproduced in any material or electronic form without the prior written consent of the copyright holder. This product and its documentation are supplied on an as-is basis and no warranty as to their suitability for any particular purpose is either made or implied. Future Technology Devices International Ltd will not accept any claim for damages howsoever arising as a result of use or failure of this produ ct. Your statutory rights are not affected. This product or any variant of it is not intended for use in any medical appliance, device or system in which the failure of the product might reasonably be expected to result in personal injury. This document provides preliminar y information that may be subject to change without notice. No freedom to use patents or other intellectual property rights is implied by the publication of this document. Future Technology Devices International Ltd, Unit 1, 2 Seaward Place, Centurion Business Park, Glasgow G41 1HH United Kingdom. Scotland Registered Company Number: SC136640

FT245R USB FIFO IC Datasheet USB FIFO IC Datasheet Version 2.15

1 Typical Applications
Upgrading Legacy Peripherals to USB Cellular and Cordless Phone USB data transfer
cables and interfaces Interfacing MCU/PLD/FPGA based designs to
USB USB Audio and Low Bandwidth Video data
transfer PDA to USB data transfer USB Smart Card Readers USB Instrumentation
1.1 Driver Support
Royalty free VIRTUAL COM PORT (VCP) DRIVERS for... Windows 7 32,64-bit Windows XP and XP 64-bit Windows Vista and Vista 64-bit Windows XP Embedded Windows 98, 98SE, ME, 2000, Server 2003, XP
and Server 2008 Windows CE 4.2, 5.0 and 6.0 Mac OS 8/9, OS-X Linux 2.4 and greater

Document No.: FT_000052 Clearance No.: FTDI# 39
USB Industrial Control USB MP3 Player Interface USB FLASH Card Reader and Writers Set Top Box PC - USB interface USB Digital Camera Interface USB Hardware Modems USB Wireless Modems USB Bar Code Readers USB Software and Hardware Encryption
Dongles
Royalty free D2XX Direct Drivers (USB Drivers + DLL S/W Interface) Windows 7 32,64-bit Windows XP and XP 64-bit Windows Vista and Vista 64-bit Windows XP Embedded Windows 98, 98SE, ME, 2000, Server 2003, XP
and Server 2008 Windows CE 4.2, 5.0 and 6.0 Linux 2.4 and greater

The drivers listed above are all available to download for free from FTDI website (www.ftdichip.com). Various 3rd party drivers are also available for other operating systems - see FTDI website (www.ftdichip.com) for details. For driver installation, please refer to the application note AN232B-10.

For driver installation, please refer to http://www.ftdichip.com/Documents/InstallGuides.htm

1.2 Part Numbers

Part Number FT245RQ-xxxx FT245RL-xxxx

Package 32 Pin QFN 28 Pin SSOP

Note: Packaging codes for xxx is: -Reel: Taped and Reel, (SSOP is 2,000pcs per reel, QFN is 6,000pcs per reel). - Tube: Tube packing, 47pcs per tube (SSOP only) - Tray: Tray packing, 490pcs per tray (QFN only) For example: FT245RQ-Reel is 6,000pcs taped and reel packing

FT245R USB FIFO IC Datasheet USB FIFO IC Datasheet Version 2.15

1.3 USB Compliant

Document No.: FT_000052 Clearance No.: FTDI# 39

The FT245R is fully compliant with the USB 2.0 specification and has been given the USB-IF Test-ID (TID) 40680005 (Rev B) and 40770019 (Rev C).

FT245R USB FIFO IC Datasheet USB FIFO IC Datasheet Version 2.15

2 FT245R Block Diagram
VCC

Document No.: FT_000052 Clearance No.: FTDI# 39

3V3OUT

3.3 Volt LDO
Regulator

USBDP USBDM

USB Transceiver
with Integrated
Series Resistors and 1.5K
Pull-up

USB DPLL

PWREN#
FIFO RX Buffer 128 bytes

Serial Interface Engine ( SIE )

USB Protocol Engine

To USB
Transceiver Cell

Internal EEPROM

VCCIO
FIFO Controller with
Programmable High Drive
3V3OUT

D0 D1 D2 D3 D4 D5 D6 D7
RD# WR RXF# TXE#

OSCO (optional)
OCSI (optional)

Internal
12MHz Oscillator

Clock Multiplier

48MHz

FIFO TX Buffer 256 bytes

RESET#

To USB Transceiver Cell

RESET GENERATOR

TEST GND
Figure 2.1 FT245R Block Diagram
For a description of each function please refer to Section 4.

Table of Contents

FT245R USB FIFO IC Datasheet USB FIFO IC Datasheet Version 2.15
Document No.: FT_000052 Clearance No.: FTDI# 39

1 Typical Applications....................................................... 2
1.1 Driver Support ........................................................................... 2 1.2 Part Numbers............................................................................. 2 1.3 USB Compliant ........................................................................... 3
2 FT245R Block Diagram .................................................. 4 3 Device Pin Out and Signal Description ........................... 7
3.1 28-LD SSOP Package.................................................................. 7 3.2 SSOP Package Pin Out Description............................................. 7 3.3 QFN-32 Package ........................................................................ 9 3.4 QFN-32 Package Signal Description ........................................... 9 3.5 FT245R FIFO READ Timing Diagrams ....................................... 11 3.6 FT245R FIFO WRITE Timing Diagrams ..................................... 12
4 Function Description ................................................... 13
4.1 Key Features ............................................................................ 13 4.2 Functional Block Descriptions .................................................. 14
5 Devices Characteristics and Ratings ............................ 15
5.1 Absolute Maximum Ratings...................................................... 15 5.2 DC Characteristics.................................................................... 15 5.3 EEPROM Reliability Characteristics .......................................... 17 5.4 Internal Clock Characteristics .................................................. 17 5.5 Thermal Characteristics ........................................................... 18
6 USB Power Configurations........................................... 19
6.1 USB Bus Powered Configuration ............................................. 19 6.2 Self Powered Configuration ..................................................... 20 6.3 USB Bus Powered with Power Switching Configuration ........... 21 6.4 USB Bus Powered with Selectable External Logic Supply ......... 22
7 Application Examples .................................................. 23
7.1 USB to MCU FIFO Interface ...................................................... 23 7.2 Using the External Oscillator.................................................... 24
8 Internal EEPROM Configuration ................................... 25 9 Package Parameters.................................................... 26
9.1 SSOP-28 Package Dimensions ................................................. 26

FT245R USB FIFO IC Datasheet USB FIFO IC Datasheet Version 2.15
Document No.: FT_000052 Clearance No.: FTDI# 39
9.2 QFN-32 Package Dimensions ................................................... 27 9.3 Solder Reflow Profile ............................................................... 28
10 Alternative Parts ......................................................... 29 11 Contact Information .................................................... 30 Appendix A - References .................................................... 31
Document References ...................................................................... 31 Acronyms & Abbreviations ............................................................... 31
Appendix B - List of Figures and Tables ............................. 32
List of Figures .................................................................................. 32 List of Tables.................................................................................... 32
Appendix C - Revision History ............................................ 34

FT245R USB FIFO IC Datasheet USB FIFO IC Datasheet Version 2.15
Document No.: FT_000052 Clearance No.: FTDI# 39
3 Device Pin Out and Signal Description

3.1 28-LD SSOP Package

VCCIO

GND

PWREN#

RD#

FTDI
YYXX-A XXXXXXXXXXXX
FT245RL

4 VCCIO

OSCO

20 VCC

OSCI

16 USBDM

TEST AGND

15 USBDP

D0 1 D1 5 D2 3 D3 11

NC RXF# TXE# GND VCC RESET#

FT245RL
8 NC
19 RESET# 24 NC 27 OSCI 28 OSCO

D4 2 D5 9 D6 10 D7 6 RXF# 23

GND 3V3OUT

17 3V3OUT A

TXE# 22

RD# 13

USBDM

GGGGE NNNNS

WR 14

USBDP

T PWREN#

25 7 18 21 26

Figure 3.1 SSOP Package Pin Out and Schematic Symbol

3.2 SSOP Package Pin Out Description

Note: The convention used throughout this document for active low signals is the signal name followed by a #

Pin No. 15 16

Name Type USBDP I/O USBDM I/O

Description USB Data Signal Plus, incorporating internal series resistor and 1.5k pull up resistor to 3.3V. USB Data Signal Minus, incorporating internal series resistor.
Table 3.1 USB Interface Group

Pin No. Name Type

VCCIO PWR

7, 18, 21

GND

PWR

3V3OUT Output

VCC

PWR

Description +1.8V to +5.25V supply to the FIFO Interface group pins (1...3, 5, 6, 9...14, 22, 23). In USB bus powered designs connect this pin to 3V3OUT pin to drive out at +3.3V levels, or connect to VCC to drive out at 5V CMOS level. This pin can also be supplied with an external +1.8V to +2.8V supply in order to drive outputs at lower levels. It should be noted that in this case this supply should originate from the same source as the supply to VCC. This means that in bus powered designs a regulator which is supplied by the +5V on the USB bus should be used.
Device ground supply pins
+3.3V output from integrated LDO regulator. This pin should be decoupled to ground using a 100nF capacitor. The main use of this pin is to provide the internal +3.3V supply to the USB transceiver cell and the internal 1.5k pull up resistor on USBDP. Up to 50mA can be drawn from this pin to power external logic if required. This pin can also be used to supply the VCCIO pin. +3.3V to +5.25V supply to the device core. (see Note 1)

FT245R USB FIFO IC Datasheet USB FIFO IC Datasheet Version 2.15

Pin No. Name

AGND

Type PWR

Document No.: FT_000052 Clearance No.: FTDI# 39
Description Device analogue ground supply for internal clock multiplier
Table 3.2 Power and Ground Group

Pin No. 8, 24
19

Name NC
RESET#

Type NC
Input

TEST

Input

OSCI

Input

OSCO Output

Description No internal connection Active low reset pin. This can be used by an external device to reset the FT245R. If not required can be left unconnected, or pulled up to VCC. Puts the device into IC test mode. Must be tied to GND for normal operation, otherwise the device will appear to fail. Input 12MHz Oscillator Cell. Optional � Can be left unconnected for normal operation. (see Note 2) Output from 12MHZ Oscillator Cell. Optional � Can be left unconnected for normal operation if internal Oscillator is used. (see Note 2) Table 3.3 Miscellaneous Signal Group

Pin No. 1 2 3 5 6 9 10 11

Name D0 D4 D2 D1 D7 D5 D6 D3

PWREN#

RD#

TXE#

RXF

Notes:

Type Description

I/O

FIFO Data Bus Bit 0

I/O

FIFO Data Bus Bit 4

I/O

FIFO Data Bus Bit 2

I/O

FIFO Data Bus Bit 1

I/O

FIFO Data Bus Bit 7

I/O

FIFO Data Bus Bit 5

I/O

FIFO Data Bus Bit 6

I/O

FIFO Data Bus Bit 3

Goes low after the device is configured by USB, then high during USB suspend. Can be used to control power to external logic P-Channel logic

Output level MOSFET switch. Enable the interface pull-down option when using

the PWREN# pin in this way. Should be pulled to VCCIO with 10k resistor.

Enables the current FIFO data byte on D0...D7 when low. Fetched the

Input

next FIFO data byte (if available) from the receive FIFO buffer when RD# goes from high to low. S

Input

Writes the data byte on the D0...D7 pins into the transmit FIFO buffer when WR goes from high to low. See Section 3.6 for timing diagram.

When high, do not write data into the FIFO. When low, data can be Output written into the FIFO by strobing WR high, then low. During reset this

signal pin is tri-state. See Section 3.6 for timing diagram.

When high, do not read data from the FIFO. When low, there is data available in the FIFO which can be read by strobing RD# low, then high

again. During reset this signal pin is tri-state..

Output

If the Remote Wakeup option is enabled in the internal EEPROM, during USB suspend mode (PWREN# = 1) RXF# becomes an input. This can be

used to wake up the USB host from suspend mode by strobing this pin

low for a minimum of 20ms which will cause the device to request a

resume on the USB bus.

Table 3.4 FIFO Interface Group (see note 3)

1. The minimum operating voltage VCC must be +4.0V (could use VBUS=+5V) when using the internal clock generator. Operation at +3.3V is possible using an external crystal oscillator.
2. For details on how to use an external crystal, ceramic resonator, or oscillator with the FT245R, please refer Section 7.2
3. When used in Input Mode, the input pins are pulled to VCCIO via internal 200k resistors. These pins can be programmed to gently pull low during USB suspend (PWREN# = "1") by setting an option in the internal EEPROM.

3.3 QFN-32 Package

FT245R USB FIFO IC Datasheet USB FIFO IC Datasheet Version 2.15
Document No.: FT_000052 Clearance No.: FTDI# 39

Figure 3.2 QFN-32 Package Pin Out and schematic symbol

3.4 QFN-32 Package Signal Description

Pin No. Name

USBDP

USBDM

Type I/O I/O

Description
USB Data Signal Plus, incorporating internal series resistor and 1.5k pull up resistor to +3.3V. USB Data Signal Minus, incorporating internal series resistor.
Table 3.5 USB Interface Group

Pin No.
1
4, 17, 20 16

Name
VCCIO
GND 3V3OUT

Type
PWR
PWR Output

Description
+1.8V to +5.25V supply for the FIFO Interface group pins (2, 3, 6, 7, 8, 9, 10 11, 21, 22, 30, 31, 32). In USB bus powered designs connect this pin to 3V3OUT to drive out at +3.3V levels, or connect to VCC to drive out at +5V CMOS level. This pin can also be supplied with an external +1.8V to +2.8V supply in order to drive out at lower levels. It should be noted that in this case this supply should originate from the same source as the supply to VCC. This means that in bus powered designs a regulator which is supplied by the +5V on the USB bus should be used.
Device ground supply pins.
+3.3V output from integrated LDO regulator. This pin should be decoupled

FT245R USB FIFO IC Datasheet USB FIFO IC Datasheet Version 2.15

Pin No. Name

VCC

AGND

Type
PWR PWR

Document No.: FT_000052 Clearance No.: FTDI# 39
Description
to ground using a 100nF capacitor. The purpose of this output is to provide the internal +3.3V supply to the USB transceiver cell and the internal 1.5k pull up resistor on USBDP. Up to 50mA can be drawn from this pin to power external logic if required. This pin can also be used to supply the VCCIO pin. +3.3V to +5.25V supply to the device core. (see Note 1). Device analogue ground supply for internal clock multiplier.
Table 3.6 Power and Ground Group

Pin No. 5, 12, 13, 23, 25, 29 18
26
27
28

Name NC RESET# TEST OSCI OSCO

Type NC Input Input Input Output

Description
No internal connection. Do not connect.
Active low reset. Can be used by an external device to reset the FT245R. If not required can be left unconnected, or pulled up to VCC. Puts the device into IC test mode. Must be tied to GND for normal operation, otherwise the device will appear to fail. Input 12MHz Oscillator Cell. Optional � Can be left unconnected for normal operation. (see Note 2). Output from 12MHZ Oscillator Cell. Optional � Can be left unconnected for normal operation if internal Oscillator is used. (see Note 2).
Table 3.7 Miscellaneous Signal Group

Pin No. Name

PWREN#

RD#

TXE#

RXF#

Type

Description

I/O

FIFO Data Bus Bit 0

I/O

FIFO Data Bus Bit 4

I/O

FIFO Data Bus Bit 2

I/O

FIFO Data Bus Bit 1

I/O

FIFO Data Bus Bit 7

I/O

FIFO Data Bus Bit 5

I/O

FIFO Data Bus Bit 6

I/O

FIFO Data Bus Bit 3

Goes low after the device is configured by USB, then high during USB

Output

suspend. Can be used to control power to external logic P-Channel logic level MOSFET switch. Enable the interface pull-down option when using the PWREN# pin in this way. Should be pulled to VCCIO with 10k

resistors.

Enables the current FIFO data byte from D0...D7 when low. Fetched the

Input next FIFO data byte (if available) from the receive FIFO buffer when RD#

goes from high to low..

Writes the data from byte from D0...D7 pins into the transmit FIFO

Input

buffer when WR goes from high to low. See section 3.6 for timing

diagram.

When high, do not write data into the FIFO. When low, data can be

Output written into the FIFO by strobing WR high, then low. During reset this

signal pin is tri-state. See Section 3.6 for timing diagram.

When high, do not read data from the FIFO. When low, there is data

available in the FIFO which can be read by strobing RD# low, then high again. During reset this signal pin is tri-state..

Output

If the Remote Wakeup option is enabled in the internal EEPROM, during USB suspend mode (PWREN# = 1) RXF# becomes an input. This can be used to wake up the USB host from suspend mode by strobing this pin

low for a minimum of 20ms which will cause the device to request a

resume on the USB bus.

Table 3.8 FIFO Interface Group (see note 3)

Notes:

FT245R USB FIFO IC Datasheet USB FIFO IC Datasheet Version 2.15
Document No.: FT_000052 Clearance No.: FTDI# 39
1. The minimum operating voltage VCC must be +4.0V (could use VBUS=+5V) when using the internal clock generator. Operation at +3.3V is possible using an external crystal oscillator.
2. For details on how to use an external crystal, ceramic resonator, or oscillator with the FT245R, please refer to Section 7.2
3. When used in Input Mode, the input pins are pulled to VCCIO via internal 200k resistors. These pins can be programmed to gently pull low during USB suspend ( PWREN# = "1") by setting an option in the internal EEPROM.

3.5 FT245R FIFO READ Timing Diagrams

RXF#

T6 T5

RD#

T2 T1

D[7...0]

Valid Data

Figure 3.3 FIFO Read Cycle

Time Description

Minimum

RD# Active Pulse Width

RD# to RD# Pre-Charge Time

50 + T6

RD# Active to Valid Data*

Valid Data Hold Time from RD# Inactive*

RD# Inactive to RXF#

RXF# Inactive After RD Cycle

Table 3.9 FIFO Read Cycle Timings

*Load = 30pF

Maximum 50 25 -

Unit ns ns ns ns ns ns

FT245R USB FIFO IC Datasheet USB FIFO IC Datasheet Version 2.15
Document No.: FT_000052 Clearance No.: FTDI# 39
3.6 FT245R FIFO WRITE Timing Diagrams
T12 T11

TXE#

WR D[7...0]

T10

Valid Data

Figure 3.4 FIFO Write Cycle

Time

Description

Minimum

WR Active Pulse Width

WR to WR Pre-Charge Time

Valid data setup to WR falling edge*

T10

Valid Data Hold Time from WR Inactive*

T11

WR Inactive to TXE#

T12

TXE# Inactive After WR Cycle

Table 3.10 FIFO Write Cycle

*Load = 30pF

Maximum 25 -

Unit ns ns ns ns ns ns

FT245R USB FIFO IC Datasheet USB FIFO IC Datasheet Version 2.15

4 Function Description

Document No.: FT_000052 Clearance No.: FTDI# 39

The FT245R is a USB to parallel FIFO interface device which simplifies USB to FIFO designs and reduces external component count by fully integrating an external EEPROM, USB termination resistors and an integrated clock circuit which requires no external crystal, into the device. It has been designed to operate efficiently with a USB host controller by using as little as possible of the total USB bandwidth available.

4.1 Key Features

Functional Integration. Fully integrated EEPROM, USB termination resistors, clock generation, AVCC filtering, power-on-reset (POR) and LDO regulator.
Asynchronous Bit Bang Mode. In asynchronous bit-bang mode, the eight FIFO lines can be switched from the regular interface mode to an 8-bit general purpose I/O port. Data packets can be sent to the device and they will be sequentially sent to the interface at a rate controlled by an internal timer (equivalent to the baud rate pre-scaler. This option will be described more fully in a separate application note available from FTDI website (www.ftdichip.com).
Synchronous Bit Bang Mode. The FT245R supports synchronous bit bang mode. This mode differs from asynchronous bit bang mode in that the interface pins are only read when the device is written to. This makes it easier for the controlling program to measure the response to an output stimulus as the data returned is synchronous to the output data. An application note, AN232R-01, available from FTDI website (www.ftdichip.com) describes this feature.
TDIChip-IDTM. The FT245R also includes the new FTDIChip-IDTM security dongle feature. This FTDIChipIDTM feature allows a unique number to be burnt into each device during manufacture. This number cannot be reprogrammed. This number is only readable over USB and forms a basis of a security dongle which can be used to protect any customer application software being copied. This allows the possibility of using the FT245R in a dongle for software licensing. Further to this, a renewable license scheme can be implemented based on the FTDIChip-IDTM number when encrypted with other information. This encrypted number can be stored in the user area of the FT245R internal EEPROM, and can be decrypted, then compared with the protected FTDIChip-IDTM to verify that a license is valid. Web based applications can be used to maintain product licensing this way. An application note, AN232R-02, available from FTDI website (www.ftdichip.com) describes this feature.
High Output Drive Option. The parallel FIFO interface and the four FIFO handshake pins can be made to drive out at three times the standard signal drive level thus allowing multiple devices to be driven, or devices that require a greater signal drive strength to be interfaced to the FT245R. This option is configured in the internal EEPROM.
Programmable FIFO RX Buffer Timeout. The FIFO RX buffer timeout is used to flush remaining data from the receive buffer. This timeout defaults to 16ms, but is programmable over USB in 1ms increments from 2ms to 255ms, thus allowing the device to be optimised for protocols that require fast response times from short data packets.
Wake Up Function. If USB is in suspend mode, and remote wake up has been enabled in the internal EEPROM (it is enabled by default), the RXF# pin becomes an input. Strobing this pin low for a minimum of 20ms will cause the FT245R to request a resume from suspend on the USB bus. Normally this can be used to wake up the host PC from suspend.
The FT245R is capable of operating at a voltage supply between +3.3V and +5V with a nominal operational mode current of 15mA and a nominal USB suspend mode current of 70�A. This allows greater margin for peripheral designs to meet the USB suspend mode current limit of 2.5mA. An integrated level converter within the FIFO interface allows the FT245R to interface to FIFO logic running at +1.8V, 2.5V, +3.3V or +5V.

FT245R USB FIFO IC Datasheet USB FIFO IC Datasheet Version 2.15

4.2 Functional Block Descriptions

Document No.: FT_000052 Clearance No.: FTDI# 39

The following paragraphs detail each function within the FT245R. Please refer to the block diagram shown in Figure 2.1.
Internal EEPROM. The internal EEPROM in the FT245R is used to store USB Vendor ID (VID), Product ID (PID), device serial number, product description string and various other USB configuration descriptors. The FT245R is supplied with the internal EEPROM pre-programmed as described in Section 8. A user area of the internal EEPROM is available to system designers to allow storing additional data. The internal EEPROM descriptors can be programmed in circuit, over USB without any additional voltage requirement. It can be programmed using the FTDI utility software called MPROG and FT_PROG, which can be downloaded from FTDI Utilities on the FTDI website (www.ftdichip.com).
+3.3V LDO Regulator. The +3.3V LDO regulator generates the +3.3V reference voltage for driving the USB transceiver cell output buffers. It requires an external decoupling capacitor to be attached to the 3V3OUT regulator output pin. It also provides +3.3V power to the 1.5k internal pull up resistor on USBDP. The main function of the LDO is to power the USB Transceiver and the Reset Generator Cells rather than to power external logic. However, it can be used to supply external circuitry requiring a +3.3V nominal supply with a maximum current of 50mA.
USB Transceiver. The USB Transceiver Cell provides the USB 1.1 / USB 2.0 full-speed physical interface to the USB cable. The output drivers provide +3.3V level slew rate control signalling, whilst a differential input receiver and two single ended input receivers provide USB data in, Single-Ended-0 (SE0) and USB reset detection conditions respectfully. This function also incorporates the internal USB series termination resistors on the USB data lines and a 1.5k pull up resistor on USBDP.
USB DPLL. The USB DPLL cell locks on to the incoming NRZI USB data and generates recovered clock and data signals for the Serial Interface Engine (SIE) block.
Internal 12MHz Oscillator. The Internal 12MHz Oscillator cell generates a 12MHz reference clock. This provides an input to the x4 Clock Multiplier function. The 12MHz Oscillator is also used as the reference clock for the SIE, USB Protocol Engine and FIFO controller blocks.
Clock Multiplier / Divider. The Clock Multiplier / Divider takes the 12MHz input from the Internal Oscillator function and generates the 48MHz. The 48Mz clock reference is used by the USB DPLL and the Baud Rate Generator blocks.
Serial Interface Engine (SIE). The Serial Interface Engine (SIE) block performs the parallel to serial and serial to parallel conversion of the USB data. In accordance with the USB 2.0 specification, it performs bit stuffing/un-stuffing and CRC5/CRC16 generation. It also checks the CRC on the USB data stream.
USB Protocol Engine. The USB Protocol Engine manages the data stream from the device USB control endpoint. It handles the low level USB protocol requests generated by the USB host controller and the commands for controlling the functional parameters of the FIFO in accordance with the USB 2.0 specification Section 9.
FIFO RX Buffer (128 bytes). Data sent from the USB host controller to the FIFO via the USB data OUT endpoint is stored in the FIFO RX (receive) buffer and is removed from the buffer by reading the contents of the FIFO using the RD# pin. (Rx relative to the USB interface).
FIFO TX Buffer (256 bytes). Data written into the FIFO using the WR pin is stored in the FIFO TX (transmit) Buffer. The USB host controller removes data from the FIFO TX Buffer by sending a USB request for data from the device data IN endpoint. (Tx relative to the USB interface).
FIFO Controller with Programmable High Drive. The FIFO Controller handles the transfer of data between the FIFO RX, the FIFO TX buffers and the external FIFO interface pins (D0 - D7). Additionally, the FIFO signals have a configurable high drive strength capability which is configurable in the EEPROM.
RESET Generator. The integrated Reset Generator Cell provides a reliable power-on reset to the device internal circuitry at power up. The RESET# input pin allows an external device to reset the FT245R. RESET# can be tied to VCC or left unconnected if not being used.

FT245R USB FIFO IC Datasheet USB FIFO IC Datasheet Version 2.15
Document No.: FT_000052 Clearance No.: FTDI# 39

5 Devices Characteristics and Ratings

5.1 Absolute Maximum Ratings

The absolute maximum ratings for the FT232R devices are as follows. These are in accordance with the Absolute Maximum Rating System (IEC 60134). Exceeding these may cause permanent damage to the device.

Parameter

Value

Storage Temperature
Floor Life (Out of Bag) At Factory Ambient (30�C / 60% Relative Humidity)
Ambient Temperature (Power Applied) MTTF FT245RL

-65 to 150 168
(IPC/JEDEC J-STD-033A MSL Level 3 Compliant)*
-40 to 85
6607685

MTTF FT245RQ

4464815

VCC Supply Voltage

-0.5 to +6.00

DC Input Voltage � USBDP and USBDM

-0.5 to +3.8

DC Input Voltage � High Impedance Bidirectional

-0.5 to + (VCC +0.5)

DC Input Voltage � All Other Inputs

-0.5 to + (VCC +0.5)

DC Output Current � Outputs

Power Dissipation (VCC = 5.25V)

500

Table 5.1 Absolute Maximum Ratings

Units �C
Hours
�C hours hours
V V V V mA mW

* If devices are stored out of the packaging beyond this time limit the devices should be baked before use. The devices should be ramped up to a temperature of +125�C and baked for up to 17 hours.

5.2 DC Characteristics

DC Characteristics (Ambient Temperature = -40�C to +85�C)

Parameter VCC1 VCC1 VCC2 Icc1 Icc2 3V3

Description

Minimum Typical Maximum Units

VCC Operating Supply Voltage

4.0

---

5.25

VCC Operating Supply Voltage

3.3

---

5.25

VCCIO Operating Supply Voltage

1.8

---

5.25

Operating Supply Current

---

Operating Supply Current

100

3.3v regulator output

3.0

3.3

3.6

Table 5.2 Operating Voltage and Current

Conditions Using Internal
Oscillator Using External
Crystal
Normal Operation
USB Suspend

Parameter

Description

Minimum Typical Maximum Units

Conditions

Voh

Output Voltage High

3.2

4.1

4.9

I source = 2mA

Vol

Output Voltage Low

0.3

0.4

0.6

I sink = 2mA

Vin

Input Switching Threshold

1.0

1.2

1.5

VHys

Input Switching Hysteresis

Table 5.3 UART and CBUS I/O Pin Characteristics (VCCIO = +5.0V, Standard Drive Level)

FT245R USB FIFO IC Datasheet USB FIFO IC Datasheet Version 2.15

Document No.: FT_000052 Clearance No.: FTDI# 39

Parameter

Description

Minimum Typical Maximum Units

Conditions

Voh

Output Voltage High

2.2

2.7

3.2

I source = 1mA

Vol

Output Voltage Low

0.3

0.4

0.5

I sink = 2mA

Vin

Input Switching Threshold

1.0

1.2

1.5

VHys

Input Switching Hysteresis

Table 5.4 UART and CBUS I/O Pin Characteristics (VCCIO = +3.3V, Standard Drive Level)

Parameter

Description

Minimum Typical Maximum Units

Conditions

Voh

Output Voltage High

2.1

2.6

2.8

I source = 1mA

Vol

Output Voltage Low

0.3

0.4

0.5

I sink = 2mA

Vin

Input Switching Threshold

1.0

1.2

1.5

VHys

Input Switching Hysteresis

Table 5.5 UART and CBUS I/O Pin Characteristics (VCCIO = +2.8V, Standard Drive Level)

Parameter

Description

Minimum Typical Maximum Units

Conditions

Voh

Output Voltage High

1.32

1.62

1.8

I source = 0.2mA

Vol

Output Voltage Low

0.06

0.1

0.18

I sink = 0.5mA

Vin

Input Switching Threshold

1.0

1.2

1.5

VHys

Input Switching Hysteresis

Table 5.6 UART and CBUS I/O Pin Characteristics (VCCIO = +1.8V, Standard Drive Level)

Parameter

Description

Minimum Typical Maximum Units

Conditions

Voh

Output Voltage High

3.2

4.1

4.9

I source = 6mA

Vol

Output Voltage Low

0.3

0.4

0.6

I sink = 6mA

Vin

Input Switching

1.0

1.2

1.5

Threshold

VHys

Input Switching

Hysteresis

Table 5.7 UART and CBUS I/O Pin Characteristics (VCCIO = +5.0V, High Drive Level)

Parameter

Description

Minimum Typical Maximum Units

Conditions

Voh

Output Voltage High

2.2

2.8

3.2

I source = 3mA

Vol

Output Voltage Low

0.3

0.4

0.6

I sink = 8mA

Vin

Input Switching Threshold

1.0

1.2

1.5

VHys

Input Switching Hysteresis

Table 5.8 UART and CBUS I/O Pin Characteristics (VCCIO = +3.3V, High Drive Level)

Parameter

Description

Minimum Typical Maximum Units

Conditions

Voh

Output Voltage High

2.1

2.6

2.8

I source = 3mA

Vol

Output Voltage Low

0.3

0.4

0.6

I sink = 8mA

Vin

Input Switching Threshold

1.0

1.2

1.5

VHys

Input Switching Hysteresis

Table 5.9 UART and CBUS I/O Pin Characteristics (VCCIO = +2.8V, High Drive Level)

FT245R USB FIFO IC Datasheet USB FIFO IC Datasheet Version 2.15
Document No.: FT_000052 Clearance No.: FTDI# 39

Parameter

Description

Minimum Typical Maximum Units

Conditions

Voh

Output Voltage High

1.35

1.67

1.8

I source = 0.4mA

Vol

Output Voltage Low

0.12

0.18

0.35

I sink = 3mA

Vin

Input Switching Threshold

1.0

1.2

1.5

VHys

Input Switching Hysteresis

Table 5.10 UART and CBUS I/O Pin Characteristics (VCCIO = +1.8V, High Drive Level)

** Only input pins have an internal 200K pull-up resistor to VCCIO

Parameter Vin VHys

Description

Minimum Typical Maximum Units

Input Switching Threshold

1.3

1.6

1.9

Input Switching Hysteresis

Table 5.11 RESET# and TEST Pin Characteristics

Conditions

Parameter UVoh
UVol UVse UCom UVDif UDrvZ

Description
I/O Pins Static Output (High)

Minimum Typical Maximum

2.8

3.6

Units V

I/O Pins Static Output (Low)

0.3

Single Ended Rx Threshold

0.8

2.0

Differential Common Mode

0.8

2.5

Differential Input Sensitivity

0.2

Driver Output Impedance

Ohms

Table 5.12 USB I/O Pin (USBDP, USBDM) Characteristics

Conditions RI = 1.5k to 3V3OUT (D+) RI = 15K to GND (D-) RI = 1.5k to 3V3OUT (D+) RI = 15k to GND (D-)
See Note 1

5.3 EEPROM Reliability Characteristics

The internal 1024 Bit EEPROM has the following reliability characteristics:

Parameter Data Retention
Write Read

Value 10
10,000 Unlimited Table 5.13 EEPROM Characteristics

Units Years Cycles Cycles

5.4 Internal Clock Characteristics

The internal Clock Oscillator has the following characteristics:

Parameter
Frequency of Operation (see Note 1) Clock Period Duty Cycle

Minimum

Value Typical

Maximum

11.98

12.00

12.02

83.19

83.33

83.47

Table 5.14 Internal Clock Characteristics

Note 1: Equivalent to +/-1667ppm

Unit
MHz ns %

FT245R USB FIFO IC Datasheet USB FIFO IC Datasheet Version 2.15
Document No.: FT_000052 Clearance No.: FTDI# 39

Parameter
Voh Vol
Vin

Description

Minimum Typical Maximum Units

Output Voltage High

2.1

2.8

3.2

Output Voltage Low

0.3

0.4

0.6

Input Switching Threshold

1.0

1.2

1.5

Table 5.15 OSCI, OSCO Pin Characteristics � see Note 1

Conditions
I source = 3mA I sink = 8mA

Note1: When supplied, the FT232R is configured to use its internal clock oscillator. These characteristics only apply when an external oscillator or crystal is used.

5.5 Thermal Characteristics

The FT245RL package has the following thermal characteristics:

Parameter
Theta JA (JA) Theta JC (JC)

Value
55.82 24.04

Units

Conditions

�C/W

Still air

�C/W

Table 5.16 FT245RL Thermal Characteristics

The FT245RQ package has the following thermal characteristics:

Parameter
Theta JA (JA) Theta JA (JA) Theta JC (JC)

Value

Units

Conditions

31.49 62.31

�C/W

Still air, center pad soldered to PCB, 9 vias to another plane

�C/W

Still air, center pad unsoldered

�C/W

Table 5.17 FT245RQ Thermal Characteristics

FT245R USB FIFO IC Datasheet USB FIFO IC Datasheet Version 2.15

6 USB Power Configurations

Document No.: FT_000052 Clearance No.: FTDI# 39

The following sections illustrate possible USB power configurations for the FT245R. The illustrations have omitted pin numbers for ease of understanding since the pins differ between the FT245RL and FT245RQ package options.

All USB power configurations illustrated apply to both package options for the FT245R device. Please refer to Section 3 for the package option pin-out and signal descriptions.

6.1 USB Bus Powered Configuration

5 SHIELD

1 2 3 4
10nF

Ferrite Bead

GND

100nF

VCC 4.7uF +

Vcc

100nF

VCC USBDM USBDP
VCCIO NC RESET# NC OSCI OSCO

FT245R

D0 D1 D2 D3 D4 D5 D6 D7 TXE# RXF#

3V3OUT

RD#

G GGGE

N N N S PWREN#

D DDDT

Vcc 10K

GND

Figure 6.1 Bus Powered Configuration

Figure 6.1 illustrates the FT245R in a typical USB bus powered design configuration. A USB bus powered device gets its power from the USB bus. Basic rules for USB bus power devices are as follows �

On plug-in to USB, the device should draw no more current than 100mA.

ii)

In USB Suspend mode the device should draw no more than 2.5mA.

iii)

A bus powered high power USB device (one that draws more than 100mA) should use the

PWREN# to keep the current below 100mA on plug-in and 2.5mA on USB suspend.

iv)

A device that consumes more than 100mA cannot be plugged into a USB bus powered hub.

No device can draw more than 500mA from the USB bus.

The power descriptors in the internal EEPROM of the FT245R should be programmed to match the current drawn by the device.

A ferrite bead is connected in series with the USB power supply to reduce EMI noise from the FT245R and associated circuitry being radiated down the USB cable to the USB host. The value of the Ferrite Bead depends on the total current drawn by the application. A suitable range of Ferrite Beads is available from Steward (www.steward.com), for example Steward Part # MI0805K400R-10.

Note: If using PWREN#, the pin should be pulled to VCCIO using a 10k resistor.

FT245R USB FIFO IC Datasheet USB FIFO IC Datasheet Version 2.15
Document No.: FT_000052 Clearance No.: FTDI# 39
6.2 Self Powered Configuration

Figure 6.2 Self-Powered Configuration

Figure 6.2 illustrates the FT245R in a typical USB self-powered configuration. A USB self-powered device gets its power from its own power supply, VCC, and does not draw current from the USB bus. The basic rules for USB self-powered devices are as follows �

A self-powered device should not force current down the USB bus when the USB host or hub

controller is powered down.

ii)

A self-powered device can use as much current as it needs during normal operation and USB

suspend as it has its own power supply.

iii)

A self-powered device can be used with any USB host, a bus powered USB hub or a self-

powered USB hub.

The power descriptor in the internal EEPROM of the FT245R should be programmed to a value of zero (self-powered).

In order to comply with the first requirement above, the USB bus power (pin 1) is used to control the RESET# pin of the FT245R device. When the USB host or hub is powered up an internal 1.5k resistor on USBDP is pulled up to +3.3V (generated using the 4K7 and 10k resistor network), thus identifying the device as a full speed device to the USB host or hub. When the USB host or hub is powered off, RESET# will be low and the FT245R is held in reset. Since RESET# is low, the internal 1.5k resistor is not pulled up to any power supply (hub or host is powered down), so no current flows down USBDP via the 1.5k pull-up resistor. Failure to do this may cause some USB host or hub controllers to power up erratically.

Figure 7.2 illustrates a self-powered design which has a +4V to +5.25V supply.

Note:

1. When the FT232R is in reset, the UART interface I/O pins are tri-stated. Input pins have internal 200k pull-up resistors to VCCIO, so they will gently pull high unless driven by some external logic.
2. When using internal FT232R oscillator the VCC supply voltage range must be +4.0V to 5.25V. 3. When using external oscillator the VCC supply voltage range must be +3.3V to 5.25V
Any design which interfaces to +3.3 V or +1.8V would be having a +3.3V or +1.8V supply to VCCIO.

FT245R USB FIFO IC Datasheet USB FIFO IC Datasheet Version 2.15
Document No.: FT_000052 Clearance No.: FTDI# 39

6.3

USB Bus Powered with Power Switching Configuration

P-Channel Power

MOSFET

0.1uF g

0.1uF

Switched 5V Power to External Logic

5 SHIELD

Soft Start Circuit

Ferrite

Bead

4 +
10nF

1k 5V VCC

GND

5V VCC

100nF 4.7uF +

100nF

VCC
USBDM
USBDP
VCCIO NC RESET# NC OSCI OSCO

D0 D1 D2 D3
FT245R D4 D5 D6 D7 TXE#

RXF#

3V3OUT A

RD#

GGGGE

N N N N S WR#

DDDDT PWREN#

GND

5V VCC 10K

GND
Figure 6.3 Bus Powered with Power Switching Configuration
A requirement of USB bus powered applications, is when in USB suspend mode the application draws a total current of less than 2.5mA. This requirement includes external logic. Some external logic has the ability to power itself down into a low current state by monitoring the PWREN# signal. For external logic that cannot power itself down in this way, the FT245R provides a simple but effective method of turning off power during the USB suspend mode.
Figure 6.3 shows an example of using a discrete P-Channel MOSFET to control the power to external logic. A suitable device to do this is an International Rectifier (www.irf.com) IRLML6402, or equivalent. It is recommended that a "soft start" circuit consisting of a 1k series resistor and a 0.1F capacitor is used to limit the current surge when the MOSFET turns on. Without the soft start circuit it is possible that the transient power surge, caused when the MOSFET switches on, will reset the FT245R or the USB host/hub controller. The soft start circuit example shown in Figure 6.3 powers up with a slew rate of approximaely12.5V/ms. Thus supply voltage to external logic transitions from GND to +5V in approximately 400 microseconds.
As an alternative to the MOSFET, a dedicated power switch IC with inbuilt "soft-start" can be used. A suitable power switch IC for such an application is the Micrel (www.micrel.com) MIC2025-2BM or equivalent.
With power switching controlled designs the following should be noted:
i) The external logic to which the power is being switched should have its own reset circuitry to automatically reset the logic when power is re-applied when moving out of suspend mode.
ii) Set the Pull-down on Suspend option in the internal FT245R EEPROM. iii) The PWREN# pin should be used to switch the power to the external circuitry. iv) For USB high-power bus powered applications (one that consumes greater than 100mA, and up
to 500mA of current from the USB bus), the power consumption of the application must be set in the Max Power field in the internal FT245R EEPROM. A high-power bus powered application uses the descriptor in the internal FT245R EEPROM to inform the system of its power requirements.
v) PWREN# gets its VCC from VCCIO. For designs using 3V3 logic, ensure VCCIO is not powered down using the external logic. In this case use the +3V3OUT.

FT245R USB FIFO IC Datasheet USB FIFO IC Datasheet Version 2.15

Document No.: FT_000052 Clearance No.: FTDI# 39
6.4 USB Bus Powered with Selectable External Logic Supply

3.3V or 5V Supply to External Logic

Vcc
100nF

5
SHIELD

Ferrite

Bead

4
10nF +

1 2 3
Jumper

GND
Vcc

100nF

4.7uF +

GND

VCCIO

VCC
USBDM
USBDP
VCCIO NC RESET# NC OSCI OSCO

FT245R

D0 D1 D2 D3 D4 D5 D6 D7 TXE#

100nF

RXF#

3V3OUT A

RD#

GGGGE

NNNNS

WR#

DDDDT PWREN#

GND

VCCIO 10k

GND
Figure 6.4 USB Bus Powered with +3.3V or +5V External Logic Power Supply

Figure 6.4 illustrates a USB bus power application with selectable external logic supply. The external logic can be selected between +3.3V and +5V using the jumper switch. This jumper is used to allow the FT245R to be interfaced with a +3.3V or +5V logic devices. The VCCIO pin is either supplied with +5V from the USB bus (jumper pins1 and 2 connected), or from the +3.3V output from the FT245R 3V3OUT pin (jumper pins 2 and 3 connected). The supply to VCCIO is also used to supply external logic.

With bus powered applications, the following should be noted:

To comply with the 2.5mA current supply limit during USB suspend mode, PWREN# or

SLEEP# signals should be used to power down external logic in this mode. If this is not

possible, use the configuration shown in Section 8.

ii)

The maximum current sourced from the USB bus during normal operation should not exceed

100mA, otherwise a bus powered design with power switching (Section 6.3) should be used.

Another possible configuration could use a discrete low dropout (LDO) regulator which is supplied by the 5V on the USB bus to supply between +1.8V and +2.8V to the VCCIO pin and to the external logic. In this case VCC would be supplied with the +5V from the USB bus and the VCCIO would be supplied from the output of the LDO regulator. This results in the FT245R I/O pins driving out at between +1.8V and +2.8V logic levels.

or a USB bus powered application, it is important to consider the following when selecting the regulator:

The regulator must be capable of sustaining its output voltage with an input voltage of

+4.35V. An Low Drop Out (LDO) regulator should be selected.

ii)

The quiescent current of the regulator must be low enough to meet the total current

requirement of <= 2.5mA during USB suspend mode.

A suitable series of LDO regulators that meets these requirements is the MicroChip/Telecom (www.microchip.com) TC55 series of devices. These devices can supply up to 250mA current and have a quiescent current of under 1A.

FT245R USB FIFO IC Datasheet USB FIFO IC Datasheet Version 2.15

7 Application Examples

Document No.: FT_000052 Clearance No.: FTDI# 39

The following sections illustrate possible applications of the FT245R. The illustrations have omitted pin numbers for ease of understanding since the pins differ between the FT245RL and FT245RQ package options.

7.1 USB to MCU FIFO Interface
VCC

Microcontroller

5
SHIELD Vcc 100nF

VCC

Ferrite

Bead

10nF

GND 4.7uF +

GND

100nF GND

VCC
USBDM
USBDP
VCCIO NC RESET# NC OSCI OSCO

FT245R

D0 D1 D2 D3 D4 D5 D6 D7 RXF#

TXE#

3V3OUT

RD#

GGGGE

NNNNS

WR#

DDDDT PWREN#

Vcc

I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16 I/O17 I/O20 I/O21 I/O22 I/O23 I/O24

10k GND

Figure 7.1 USB to MCU FIFO Interface
A typical example of using the FT245R as a USB to Microcontroller (MCU) FIFO interface is illustrated in Figure 7.1. This example uses two MCU I/O ports: one port (8 bits) to transfer data and the other port (4 or 5 bits) to monitor the TXE# and RXF# status bits and generate the RD# and WR strobes to the FT245R, when required.
Using PWREN# for this function is optional.
If the Remote Wakeup option is enabled in the internal EEPROM, during USB suspend mode RXF# becomes an input which can be used to wake up the USB host controller by strobing the pin low.

FT245R USB FIFO IC Datasheet USB FIFO IC Datasheet Version 2.15

7.2 Using the External Oscillator

Document No.: FT_000052 Clearance No.: FTDI# 39

The FT245R defaults to operating using its own internal oscillator. This requires that the device is powered with VCC (min)=+4.0V. This supply voltage can be taken from the USB VBUS. Applications which require using an external oscillator, VCC= +3.3V must do so in the following order:

1. When device powered for the very first time, it must have VCC > +4.0V. This supply is available from the USB VBUS supply = +5.0V.

2. The EEPROM must then be programmed to enable external oscillator. This EEPROM modification cannot be done using the FTDI programming utility, MPROG and FT_PROG. The EEPROM can only be re-configured from a custom application. Please refer to the following applications note on how to do this:

http://www.ftdichip.com/Documents/AppNotes/AN_100_Using_The_FT232_245R_With_External_ Osc(FT_000067).pdf

3. The FT245R can then be powered from VCC=+3.3V and an external oscillator. This can be done using a link to switch the VCC supply.

The FT245R will fail to operate when the internal oscillator has been disabled, but no external oscillator has been connected.

FT245R USB FIFO IC Datasheet USB FIFO IC Datasheet Version 2.15

8 Internal EEPROM Configuration

Document No.: FT_000052 Clearance No.: FTDI# 39

Following a power-on reset or a USB reset the FT245R will scan its internal EEPROM and read the USB configuration descriptors stored there. The default factory programmed values of the internal EEPROM are shown in Table 8.1 Default Internal EEPROM Configuration.

Parameter

Value

Notes

USB Vendor ID (VID)

0403h

FTDI default VID (hex)

USB Product UD (PID)

6001h

FTDI default PID (hex)

Serial Number Enabled?

Yes

A unique serial number is generated and

Serial Number

See Note

programmed into the EEPROM during device final

test.

Pull down I/O Pins in USB Suspend

Disabled

Enabling this option will make the device pull down on the FIFO interface lines when in USB suspend mode (PWREN# is high).

Manufacturer Name

FTDI

Product Description

FT245R USB FIFO

Max Bus Power Current

90mA

Power Source

Bus Powered

Device Type

FT245R

Returns USB 2.0 device description to the host.

USB Version

0200

Note: The device is a USB 2.0 Full Speed device (12Mb/s) as opposed to a USB 2.0 High Speed

device (480Mb/s).

Remote Wake Up

Enabled

Taking RXF# low will wake up the USB host controller from suspend in approximately 20 ms.

High Current I/Os

Disabled

Enables the high drive level on the FIFO data bus and control I/O pins.

Load VCP Driver

Enabled

Makes the device load the VCP driver interface for the device.

Table 8.1 Default Internal EEPROM Configuration

The internal EEPROM in the FT245R can be programmed over USB using the FTDI utility program MPROG and FT_PROG which can be downloaded from FTDI Utilities, on the FTDI website (www.ftdichip.com). Version 2.8a or later is required for the FT245R chip. Users who do not have their own USB Vendor ID but who would like to use a unique Product ID in their design can apply to FTDI for a free block of unique PIDs. Contact FTDI support for this service.

FT245R USB FIFO IC Datasheet USB FIFO IC Datasheet Version 2.15

9 Package Parameters

Document No.: FT_000052 Clearance No.: FTDI# 39

The FT245R is available in two different packages. The FT245RL is the SSOP-28 option and the FT245RQ is the QFN-32 package option. The solder reflow profile for both packages is described in Section 9.3.

9.1 SSOP-28 Package Dimensions

Figure 9.1 SSOP-28 Package Dimensions
The FT245RL is supplied in a RoHS compliant 28 pin SSOP package. The package is lead (Pb) free and uses a `green' compound. The package is fully compliant with European Union directive 2002/95/EC.
This package is nominally 5.30mm x 10.20mm body (7.80mm x 10.20mm including pins). The pins are on a 0.65 mm pitch. The above mechanical drawing shows the SSOP-28 package.
All dimensions are in millimetres.
The date code format is YYXX-A where XX = 2 digit week number, YY = 2 digit year number, A = single letter corresponding to the revision of the device (e.g. A or B or C).
The code XXXXXXXXXXXX is the manufacturing LOT code. This only applies to devices manufactured after April 2009.

FT245R USB FIFO IC Datasheet USB FIFO IC Datasheet Version 2.15

9.2 QFN-32 Package Dimensions

Document No.: FT_000052 Clearance No.: FTDI# 39

Figure 9.2 QFN-32 Package Dimensions
The FT245RQ is supplied in a RoHS compliant leadless QFN-32 package. The package is lead ( Pb ) free, and uses a `green' compound. The package is fully compliant with European Union directive 2002/95/EC.
This package is nominally 5.00mm x 5.00mm. The solder pads are on a 0.50mm pitch. The above mechanical drawing shows the QFN-32 package. All dimensions are in millimetres.
The centre pad on the base of the FT245RQ is not internally connected, and can be left unconnected, or connected to ground (recommended).
The date code format is YYXX-A where XX = 2 digit week number, YY = 2 digit year number, A = single letter corresponding to the revision of the device (e.g. A or B or C).
The code XXXXXXX is the manufacturing LOT code. This only applies to devices manufactured after April 2009.

FT245R USB FIFO IC Datasheet USB FIFO IC Datasheet Version 2.15
Document No.: FT_000052 Clearance No.: FTDI# 39
9.3 Solder Reflow Profile
The FT245R is supplied in Pb free 28 LD SSOP and QFN-32 packages. The recommended solder reflow profile for both package options is shown in 9.3.

Temperature, T (Degrees C)

Tp
TL TS Max
TS Min

Ramp Up
tS Preheat

tp tL

Critical Zone: when T is in the range TL to Tp
Ramp Down

25 T = 25� C to TP
Time, t (seconds)

Figure 9.3 FT245R Solder Reflow Profile
The recommended values for the solder reflow profile are detailed in Table 9.1. Values are shown for both a completely Pb free solder process (i.e. the FT245R is used with Pb free solder), and for a non-Pb free solder process (i.e. the FT245R is used with non-Pb free solder).

Profile Feature

Pb Free Solder Process

Non-Pb Free Solder Process

Average Ramp Up Rate (Ts to Tp)

3�C / second Max.

3�C / Second Max.

Preheat - Temperature Min (Ts Min.) - Temperature Max (Ts Max.) - Time (ts Min to ts Max)

150�C 200�C 60 to 120 seconds

100�C 150�C 60 to 120 seconds

Time Maintained Above Critical

Temperature TL: - Temperature (TL) - Time (tL)

217�C 60 to 150 seconds

183�C 60 to 150 seconds

Peak Temperature (Tp)

260�C

240�C

Time within 5�C of actual Peak Temperature (tp)

20 to 40 seconds

Ramp Down Rate

6�C / second Max.

Time for T= 25�C to Peak Temperature, Tp

8 minutes Max.

6 minutes Max.

Table 9.1 Reflow Profile Parameter Values

FT245R USB FIFO IC Datasheet USB FIFO IC Datasheet Version 2.15

10 Alternative Parts

Document No.: FT_000052 Clearance No.: FTDI# 39

The following list of parts are not all direct drop in replacements but offer similar features as an alternative to the FT245R. The FT-X series is the latest device family offering reduced power and pin count with additional features such as battery charge detection, while the Hi-Speed solution offers faster interfacing.

FT245R

FT240X

FT232H

Description

Single channel USB
to asynchronous
FIFO

Single channel USB to
asynchronous FIFO

Single channel USB to
asynchronous FIFO (Need MTP
to configure)

USB Speed

USB 2.0 full speed

USB 2.0 hispeed

UART Data Rates

1 Mbyte/s

1Mbyte/s

8 Mbyte/s

MTP for

storing

Internal

External

descriptors

Package

32 pin QFN

24 pin QFN

48 pin QFN

options

28 pin SSOP 24 pin SSOP

48 pin LQFP

Datasheet

FT245R

FT234XD

FT232H

Table 10.1 FT245R Alternative Solutions

FT245R USB FIFO IC Datasheet USB FIFO IC Datasheet Version 2.15

11 Contact Information

Document No.: FT_000052 Clearance No.: FTDI# 39

Head Office � Glasgow, UK
Future Technology Devices International Limited Unit 1, 2 Seaward Place Centurion Business Park Glasgow, G41 1HH United Kingdom Tel: +44 (0) 141 429 2777 Fax: +44 (0) 141 429 2758
E-mail (Sales) sales1@ftdichip.com E-mail (Support) support1@ftdichip.com E-mail (General Enquiries) admin1@ftdichip.com Web Site URL http://www.ftdichip.com Web Shop URL http://www.ftdichip.com

Branch Office � Taipei, Taiwan

Future Technology Devices International Limited (Taiwan) 2F, No 516, Sec. 1 NeiHu Road Taipei 114 Taiwan, R.O.C. Tel: +886 (0) 2 8791 3570 Fax: +886 (0) 2 8791 3576

E-mail (Sales) tw.sales1@ftdichip.com

E-mail (Support) tw.support1@ftdichip.com

E-mail (General Enquiries) tw.admin1@ftdichip.com

Web Site URL

http://www.ftdichip.com

Branch Office � Tigard, Oregon, USA

Future Technology Devices International Limited (USA) 7130 SW Fir Loop Tigard, OR 97223-8160 USA Tel: +1 (503) 547 0988 Fax: +1 (503) 547 0987

E-Mail (Sales) E-Mail (Support) E-Mail (General Enquiries)

us.sales@ftdichip.com us.support@ftdichip.com us.admin@ftdichip.com

Branch Office � Shanghai, China
Future Technology Devices International Limited (China) Room 1103, No. 666 West Huaihai Road, Shanghai, 200052 China Tel: +86 21 62351596 Fax: +86 21 62351595
E-Mail (Sales): cn.sales@ftdichip.com E-Mail (Support): cn.support@ftdichip.com E-Mail (General Enquiries): cn.admin1@ftdichip.com

Web Site URL: http://www.ftdichip.com
Distributor and Sales Representatives Please visit the Sales Network page of the FTDI Web site for the contact details of our distributor(s) and sales representative(s) in your country.

System and equipment manufacturers and designers are responsible to ensure that their systems, and any Future Technology Devices International Ltd (FTDI) devices incorporated in their systems, meet all applicable safety, regulatory and system-level performance requirements. All application-related information in this document (including application descriptions, suggested FTDI devices and other materials) is provided for reference only. While FTDI has taken care to assure it is accurate, this information is subject to customer confirmation, and FTDI disclaims all liability for system designs and for any applications assistance provided by FTDI. Use of FTDI devices in life support and/or safety applications is entirely at the user's risk, and the user agrees to defend, indemnify and hold harmless FTDI from any and all damages, claims, suits or expense resulting from such use. This document is subject to change without notice. No freedom to use patents or other intellectual property rights is implied by the publication of this document. Neither the whole nor any part of the information contained in, or the product described in this document, may be adapted or reproduced in any material or electronic form without the prior written consent of the copyright holder. Future Technology Devices International Ltd, Unit 1, 2
Seaward Place, Centurion Business Park, Glasgow G41 1HH, United Kingdom. Scotland Registered Company Number: SC136640.

FT245R USB FIFO IC Datasheet USB FIFO IC Datasheet Version 2.15

Appendix A - References

Document No.: FT_000052 Clearance No.: FTDI# 39

Document References
http://www.ftdichip.com/Documents/AppNotes/AN232R-01_FT232RBitBangModes.pdf http://www.ftdichip.com/Documents/AppNotes/AN_107_AdvancedDriverOptions_AN_000073.pdf http://www.ftdichip.com/Documents/AppNotes/AN232R-02_FT232RChipID.pdf http://www.ftdichip.com/Documents/AppNotes/AN_121_FTDI_Device_EEPROM_User_Area_Usage.pdf http://www.ftdichip.com/Documents/AppNotes/AN_120_Aliasing_VCP_Baud_Rates.pdf http://www.ftdichip.com/Documents/AppNotes/AN_100_Using_The_FT232_245R_With_External_Osc(FT_ 000067).pdf http://www.ftdichip.com/Resources/Utilities/AN_126_User_Guide_For_FT232_Factory%20test%20utility. pdf http://www.ftdichip.com/Documents/AppNotes/AN232B-05_BaudRates.pdf http://www.ftdichip.com/Documents/InstallGuides.htm

Acronyms & Abbreviations

Terms EEPROM
FPGA LED MCU PLD QFN RoHS SIE UART USB VCP

Description Electrically Erasable Programmable Read-Only Memory Field Programmable Gate Array Light Emitting Diode Micro Controller Unit Programmable Logic Device Quad Flat No-leads Restriction of Hazardous Substances Directive Serial Interface Engine Universal Asynchronous Receiver/Transmitter Universal Serial Bus Virtual Communication Port

FT245R USB FIFO IC Datasheet USB FIFO IC Datasheet Version 2.15
Document No.: FT_000052 Clearance No.: FTDI# 39
Appendix B - List of Figures and Tables
List of Figures
Figure 2.1 FT245R Block Diagram ................................................................................................... 4 Figure 3.1 SSOP Package Pin Out and Schematic Symbol................................................................... 7 Figure 3.2 QFN-32 Package Pin Out and schematic symbol ................................................................ 9 Figure 3.3 FIFO Read Cycle .......................................................................................................... 11 Figure 3.4 FIFO Write Cycle ......................................................................................................... 12 Figure 6.1 Bus Powered Configuration ........................................................................................... 19 Figure 6.2 Self-Powered Configuration........................................................................................... 20 Figure 6.3 Bus Powered with Power Switching Configuration ............................................................ 21 Figure 6.4 USB Bus Powered with +3.3V or +5V External Logic Power Supply .................................... 22 Figure 7.1 USB to MCU FIFO Interface ........................................................................................... 23 Figure 9.1 SSOP-28 Package Dimensions ....................................................................................... 26 Figure 9.2 QFN-32 Package Dimensions......................................................................................... 27 Figure 9.3 FT245R Solder Reflow Profile ........................................................................................ 28

List of Tables
Table 3.1 USB Interface Group ....................................................................................................... 7 Table 3.2 Power and Ground Group................................................................................................. 8 Table 3.3 Miscellaneous Signal Group .............................................................................................. 8 Table 3.4 FIFO Interface Group (see note 3) .................................................................................... 8 Table 3.5 USB Interface Group ....................................................................................................... 9 Table 3.6 Power and Ground Group............................................................................................... 10 Table 3.7 Miscellaneous Signal Group ............................................................................................ 10 Table 3.8 FIFO Interface Group (see note 3) .................................................................................. 10 Table 3.9 FIFO Read Cycle Timings ............................................................................................... 11 Table 3.10 FIFO Write Cycle ......................................................................................................... 12 Table 5.1 Absolute Maximum Ratings ............................................................................................ 15 Table 5.2 Operating Voltage and Current ....................................................................................... 15 Table 5.3 UART and CBUS I/O Pin Characteristics (VCCIO = +5.0V, Standard Drive Level) .................. 15 Table 5.4 UART and CBUS I/O Pin Characteristics (VCCIO = +3.3V, Standard Drive Level) .................. 16 Table 5.5 UART and CBUS I/O Pin Characteristics (VCCIO = +2.8V, Standard Drive Level) .................. 16 Table 5.6 UART and CBUS I/O Pin Characteristics (VCCIO = +1.8V, Standard Drive Level) .................. 16 Table 5.7 UART and CBUS I/O Pin Characteristics (VCCIO = +5.0V, High Drive Level) ......................... 16 Table 5.8 UART and CBUS I/O Pin Characteristics (VCCIO = +3.3V, High Drive Level) ......................... 16 Table 5.9 UART and CBUS I/O Pin Characteristics (VCCIO = +2.8V, High Drive Level) ......................... 16 Table 5.10 UART and CBUS I/O Pin Characteristics (VCCIO = +1.8V, High Drive Level) ....................... 17 Table 5.11 RESET# and TEST Pin Characteristics ............................................................................ 17 Table 5.12 USB I/O Pin (USBDP, USBDM) Characteristics................................................................. 17 Table 5.13 EEPROM Characteristics ............................................................................................... 17 Table 5.14 Internal Clock Characteristics ....................................................................................... 17

FT245R USB FIFO IC Datasheet USB FIFO IC Datasheet Version 2.15
Document No.: FT_000052 Clearance No.: FTDI# 39
Table 5.15 OSCI, OSCO Pin Characteristics � see Note 1 ................................................................. 18 Table 5.16 FT245RL Thermal Characteristics .................................................................................. 18 Table 5.17 FT245RQ Thermal Characteristics.................................................................................. 18 Table 8.1 Default Internal EEPROM Configuration............................................................................ 25 Table 9.1 Reflow Profile Parameter Values ..................................................................................... 28 Table 10.1 FT245R Alternative Solutions ........................................................................................ 29

FT245R USB FIFO IC Datasheet USB FIFO IC Datasheet Version 2.15

Appendix C - Revision History

Document No.: FT_000052 Clearance No.: FTDI# 39

Document Title:

FT245R USB FIFO IC Datasheet

Document Reference No.:

FT_000052

Clearance No.: Product Page: Document Feedback:

FTDI# 39 http://www.ftdichip.com/FTProducts.htm Send Feedback

Revision

Changes

Version 1.00 Initial Release

Version 1.02 Minor revisions to datasheet release

Version 1.03 Manufacturer ID added to default EEPROM data

Version 1.04 Buffer Sizes Added

Version 1.05 QFN-32 Package pad layout and solder paste diagrams added

Version 2.00

Reformatted, added notes for 3.3V operation; Part numbers, TID, corrected; QFN Package drawing corrected. Added FIFO characteristics for +1.8V; Added MTTF data Corrected the input switching threshold and input hysteresis figures for VCCIO=+5V

Version 2.01

Corrected the RX and TX Buffer data flow direction in the block Diagram Figure 2.1

Version 2.02

Removed repeated section of table 8.1 Improved graphics on Figures 6.2, 6.3, 6.4 and 7.1 Add Packing details Changed USB suspend current spec from 500uA to 2.5m Corrected Figure 9.2 QFN dimensions.

Version 2.03

Amended definition of FIFO TX and RX buffers to be consistent Updated company contact information

Version 2.04

Corrected Tape and Reel quantities Added LOT numbers to the device markings. Clarified VCC operation and added section headed "Using an external Oscillator" Added 3V3 regulator output tolerance

Version 2.05 Corrected Tx and RX buffer sizes on front page

Version 2.06 Additional Dimensions added to QFN Solder Profile

Version 2.07

Changed label `D6' to 'D7' (pin 3) on FT245RQ schematic symbol
Updated to latest TID number
Added Window 7 support

Date December 2005 December 2005
January 2006 January 2006 January 2006
June 2008
July 2008
August 2008
February 2009
April 2009
June 2009 June 2009 October 2009
34

FT245R USB FIFO IC Datasheet USB FIFO IC Datasheet Version 2.15
Document No.: FT_000052 Clearance No.: FTDI# 39

Revision

Changes

Date

Version 2.08

Modified package dimensions to 5.0 x 5.0 +/-0.075mm and Solder paste diagram to 2.50 x 2.50 +/-0.0375mm Added FT_PROG utility references Added Appendix A-references Corrected USB-IF TID

December 2009

Version 2.09

Updated section 6.2, Figure 6.2 and the note, Updated section 5.3, Table 5.13, EEPROM data retention time

May 2010

Version 2.10

Removed RD# and WR# references on BitBang modes
Corrected US Support email address. Added USB Compliance logo

July 2010

Version 2.11 Updated USB-IF TID for Rev C

April 2011

Version 2.12 Corrected TID for Rev C

April 2011

Version 2.13

Added Thermal Characteristics (Section 5.5) Added document information and feedback to revision history Added section 10 on alternative parts

February 2015

Version 2.14

Updated Fig. 3.2 QFN-32 Package Pin Out and schematic symbol
Updated Fig. 9.1 SSOP-28 Package Dimensions Updated Fig. 9.2 QFN-32 Package Dimensions
Deleted QFN-32 Package Typical Pad Layout and QFN-32 Package Typical Solder Paste Diagram sections.

2019-04-04

Version 2.15

Added note about revision letter in the package marking pages (Package Parameters section 9)

2020-05-21