Home › MPC5777C , MPC5777C Microcontroller Data Sheet

MPC5777C , MPC5777C Microcontroller Data Sheet

File info: application/pdf · 90 pages · 1.06MB

MPC5777C, This document provides electrical specifications, pin assignments, and package diagram information for the MPC5777C series of microcontroller units (MCUs).

NXP Semiconductors Data Sheet: Technical Data

model, see the MPC5777C Reference Manual. NXP Semiconductors Number: MPC5777C Data Sheet: Technical Data Rev. 14, 01/2020 NXP reserves the right to change the proudction detail specifications as may be required to permi…

Datasheet

NXP Semiconductors SPC5777CDK3MMO3 | IBS Electronics

NXP Semiconductors SPC5777CDK3MMO4 | Microcontrollers | IBS Electronics

Full PDF Document

If the inline viewer fails, it will open the original document in compatibility mode automatically. You can also open the file directly.

Extracted Text

NXP Semiconductors Data Sheet: Technical Data
MPC5777C Microcontroller Data Sheet
Features � This document provides electrical specifications, pin
assignments, and package diagram information for the MPC5777C series of microcontroller units (MCUs).

Document Number: MPC5777C Rev. 14, 01/2020
MPC5777C
� For functional characteristics and the programming model, see the MPC5777C Reference Manual.

NXP reserves the right to change the proudction detail specifications as may be required to permit improvements in the design of its products.

Table of Contents

1 Introduction...............................................................................3

3.11.1 Power management electrical characteristics40

1.1 Features summary..........................................................3

3.11.2 Power management integration.....................43

1.2 Block diagram..................................................................4

3.11.3 Device voltage monitoring..............................44

2 Pinouts......................................................................................5

3.11.4 Power sequencing requirements....................46

2.1 416-ball MAPBGA pin assignments................................5

3.12 Flash memory specifications...........................................47

2.2 516-ball MAPBGA pin assignments................................6

3.12.1 Flash memory program and erase

3 Electrical characteristics............................................................7

specifications..................................................48

3.1 Absolute maximum ratings..............................................7

3.12.2 Flash memory Array Integrity and Margin

3.2 Electromagnetic interference (EMI) characteristics.........9

Read specifications........................................48

3.3 Electrostatic discharge (ESD) characteristics.................9

3.12.3 Flash memory module life specifications.......49

3.4 Operating conditions.......................................................9

3.12.4 Data retention vs program/erase cycles.........50

3.5 DC electrical specifications.............................................12

3.12.5 Flash memory AC timing specifications.........50

3.6 I/O pad specifications......................................................13

3.12.6 Flash memory read wait-state and address-

3.6.1

Input pad specifications..................................13

pipeline control settings..................................51

3.6.2

Output pad specifications...............................15

3.13 AC timing.........................................................................52

3.6.3

I/O pad current specifications.........................19

3.13.1 Generic timing diagrams................................52

3.7 Oscillator and PLL electrical specifications.....................19

3.13.2 Reset and configuration pin timing.................53

3.7.1

PLL electrical specifications...........................20

3.13.3 IEEE 1149.1 interface timing..........................54

3.7.2

Oscillator electrical specifications..................21

3.13.4 Nexus timing..................................................57

3.8 Analog-to-Digital Converter (ADC) electrical

3.13.5 External Bus Interface (EBI) timing................59

specifications...................................................................23

3.13.6 External interrupt timing (IRQ/NMI pin)..........63

3.8.1

Enhanced Queued Analog-to-Digital

3.13.7 eTPU timing...................................................64

Converter (eQADC)........................................23

3.13.8 eMIOS timing.................................................65

3.8.2

Sigma-Delta ADC (SDADC)...........................25

3.13.9 DSPI timing with CMOS and LVDS pads.......66

3.9 Temperature Sensor.......................................................34

3.13.10 FEC timing.....................................................78

3.10 LVDS Fast Asynchronous Serial Transmission (LFAST)

4 Package information.................................................................83

pad electrical characteristics...........................................34

4.1 Thermal characteristics...................................................83

3.10.1 LFAST interface timing diagrams...................34

4.1.1

General notes for thermal characteristics......84

3.10.2 LFAST and MSC/DSPI LVDS interface

5 Ordering information.................................................................87

electrical characteristics.................................36

6 Document revision history.........................................................88

3.10.3 LFAST PLL electrical characteristics.............39

3.11 Power management: PMC, POR/LVD, power

sequencing......................................................................40

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Introduction

1 Introduction
1.1 Features summary
On-chip modules available within the family include the following features:
� Three dual issue, 32-bit CPU core complexes (e200z7), two of which run in lockstep � Power Architecture embedded specification compliance � Instruction set enhancement allowing variable length encoding (VLE), optional encoding of mixed 16-bit and 32-bit instructions, for code size footprint reduction � On the two computational cores: Signal processing extension (SPE1.1) instruction support for digital signal processing (DSP) � Single-precision floating point operations � On the two computational cores: 16 KB I-Cache and 16 KB D-Cache � Hardware cache coherency between cores
� 16 hardware semaphores � 3-channel CRC module � 8 MB on-chip flash memory
� Supports read during program and erase operations, and multiple blocks allowing EEPROM emulation
� 512 KB on-chip general-purpose SRAM including 64 KB standby RAM � Two multichannel direct memory access controllers (eDMA)
� 64 channels per eDMA � Dual core Interrupt Controller (INTC) � Dual phase-locked loops (PLLs) with stable clock domain for peripherals and
frequency modulation (FM) domain for computational shell � Crossbar Switch architecture for concurrent access to peripherals, flash memory, or
RAM from multiple bus masters with End-To-End ECC � External Bus Interface (EBI) for calibration and application use � System Integration Unit (SIU) � Error Injection Module (EIM) and Error Reporting Module (ERM) � Four protected port output (PPO) pins � Boot Assist Module (BAM) supports serial bootload via CAN or SCI � Three second-generation Enhanced Time Processor Units (eTPUs)
� 32 channels per eTPU � Total of 36 KB code RAM � Total of 9 KB parameter RAM

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Introduction
� Enhanced Modular Input/Output System (eMIOS) supporting 32 unified channels with each channel capable of single action, double action, pulse width modulation (PWM) and modulus counter operation
� Two Enhanced Queued Analog-to-Digital Converter (eQADC) modules with: � Two separate analog converters per eQADC module � Support for a total of 70 analog input pins, expandable to 182 inputs with offchip multiplexers � Interface to twelve hardware Decimation Filters � Enhanced "Tap" command to route any conversion to two separate Decimation Filters
� Four independent 16-bit Sigma-Delta ADCs (SDADCs) � 10-channel Reaction Module � Ethernet (FEC) � Two PSI5 modules � Two SENT Receiver (SRX) modules supporting 12 channels � Zipwire: SIPI and LFAST modules � Five Deserial Serial Peripheral Interface (DSPI) modules � Five Enhanced Serial Communication Interface (eSCI) modules � Four Controller Area Network (FlexCAN) modules � Two M_CAN modules that support FD � Fault Collection and Control Unit (FCCU) � Clock Monitor Units (CMUs) � Tamper Detection Module (TDM) � Cryptographic Services Engine (CSE)
� Complies with Secure Hardware Extension (SHE) Functional Specification Version 1.1 security functions
� Includes software selectable enhancement to key usage flag for MAC verification and increase in number of memory slots for security keys
� PASS module to support security features � Nexus development interface (NDI) per IEEE-ISTO 5001-2003 standard, with some
support for 2010 standard � Device and board test support per Joint Test Action Group (JTAG) IEEE 1149.1 and
1149.7 � On-chip voltage regulator controller (VRC) that derives the core logic supply voltage
from the high-voltage supply � On-chip voltage regulator for flash memory � Self Test capability

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

1.2 Block diagram

Pinouts

The following figure shows a top-level block diagram of the MPC5777C. The purpose of the block diagram is to show the general interconnection of functional modules through the crossbar switch.

COMPUTATIONAL SHELL

e200z7 (dual issue)
FPU VLE 16K I-Cache 16K D-Cache MMU

SWT STM INTC

e200z7 checker core complex e200z7 (dual issue)
FPU

SWT STM INTC

VLE

16K I-Cache

16K D-Cache

MMU

DEBUG JTAG MMU Nexus 3+ DTS
64ch eDMA 64ch eDMA
Ethernet

Crossbar Switch with ECC MPU

Flash Control

EBI

Flash w/ EEPROM

SRAM Control SRAM

Security Tamper Detection
CSE

Safety Monitor Bridge B Bridge A

FLEXCAN_A-B MCAN_0-1
DSPI_A-C eSCI_A-C ETPU_C
w/RAM eMIOS_0 eQADC_A & Temp Sensors DECFILTER_A-L SDADC_1/3
SRX_0
PSI5_0 REACM2 Zipwire/ SIPI/LFAST Dual PLL/ OSC/IRC
CRC PCM/ERM

SIU/SIU_B CMU_0-8 EBI registers
FCCU STCU PMU/PMC PIT-RTI FlexCAN_C-D DSPI_D-E eSCI_D-F ETPU_A/B (w/RAM) eMIOS_1 eQADC_B SDADC_2/4 SRX_1 PSI5_1

Figure 1. MPC5777C block diagram

2 Pinouts

2.1 416-ball MAPBGA pin assignments
Figure 2 shows the 416-ball MAPBGA pin assignments.

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Pinouts

Figure 2. MPC5777C 416-ball MAPBGA (full diagram)
2.2 516-ball MAPBGA pin assignments
Figure 3 shows the 516-ball MAPBGA pin assignments.

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Electrical characteristics

Figure 3. MPC5777C 516-ball MAPBGA (full diagram)
3 Electrical characteristics
The following information includes details about power considerations, DC/AC electrical characteristics, and AC timing specifications.
3.1 Absolute maximum ratings
Absolute maximum specifications are stress ratings only. Functional operation at these maxima is not guaranteed.
CAUTION Stress beyond listed maxima may affect device reliability or cause permanent damage to the device. See Operating conditions for functional operation specifications.

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Electrical characteristics

Table 1. Absolute maximum ratings

Symbol

Parameter

Conditions1

Cycle VDD VDDEHx VDDEx VDDPMC
VDDFLA VSTBY VSSA_SD VSSA_EQ VDDA_EQA/B VDDA_SD VRL_SD VRL_EQ VRH_EQ VRH_SD VREFBYPC
VDDA_MISC VDDPWR VSSPWR
VSS � VSSA_EQ VSS � VSSA_SD VSS � VRL_EQ VSS � VRL_SD
VIN
IINJD
IINJA
IMAXSEG8, 9
TSTG
STORAGE
TSDR

Lifetime power cycles

1.2 V core supply voltage2, 3, 4

I/O supply voltage (medium I/O pads)5 --

I/O supply voltage (fast I/O pads)5

Power Management Controller supply -- voltage5

Decoupling pin for flash regulator6

RAM standby supply voltage5

SDADC ground voltage eQADC ground voltage eQADC supply voltage SDADC supply voltage SDADC ground reference eQADC ground reference eQADC alternate reference SDADC alternate reference eQADC reference decoupling capacitor pins

Reference to VSS Reference to VSS Reference to VSSA_EQ Reference to VSSA_SD Reference to VSS Reference to VSS Reference to VRL_EQ Reference to VRL_SD REFBYPCA25, REFBYPCA75, REFBYPCB25, REFBYPC75

TRNG and IRC supply voltage

SMPS driver supply pin

SMPS driver supply pin
VSSA_EQ differential voltage VSSA_SD differential voltage VRL_EQ differential voltage VRL_SD differential voltage I/O input voltage range7

Reference to VSS -- -- -- -- --

Relative to VDDEx/VDDEHx
Relative to VSS
Maximum DC injection current for digital Per pin, applies to all digital pins pad

Maximum DC injection current for analog pad

Per pin, applies to all analog pins

Maximum current per I/O power

segment

Storage temperature range and non- -- operating times

Maximum storage time, assembled part No supply; storage temperature in

programmed in ECU

range �40 �C to 60 �C

Maximum solder temperature10

Pb-free package

Table continues on the next page...

Value Unit
Min Max -- 1000k -- �0.3 1.5 V �0.3 6.0 V �0.3 6.0 V �0.3 6.0 V

�0.3 4.5 V �0.3 6.0 V �0.3 0.3 V �0.3 0.3 V �0.3 6.0 V �0.3 6.0 V �0.3 0.3 V �0.3 0.3 V �0.3 6.0 V �0.3 6.0 V �0.3 6.0 V

�0.3 6.0 V

�0.3 0.3 V

�0.3 6.0 V

-- 0.3 V

�0.3 --

�5

�120 120 mA

�55 175 �C

-- 20 years

-- 260 �C

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Symbol MSL

Electrical characteristics
Table 1. Absolute maximum ratings (continued)

Parameter Moisture sensitivity level11

Conditions1 --

Value Unit
Min Max

1. Voltages are referred to VSS if not specified otherwise 2. Allowed 1.45 V � 1.5 V for 60 seconds cumulative time at maximum TJ = 150 �C; remaining time as defined in note 3 and
note 4 3. Allowed 1.375 V � 1.45 V for 10 hours cumulative time at maximum TJ = 150 �C; remaining time as defined in note 4 4. 1.32 V � 1.375 V range allowed periodically for supply with sinusoidal shape and average supply value below 1.275 V at
maximum TJ = 150 �C 5. Allowed 5.5 V � 6.0 V for 60 seconds cumulative time with no restrictions, for 10 hours cumulative time device in reset, TJ
= 150 �C; remaining time at or below 5.5 V 6. Allowed 3.6 V � 4.5 V for 60 seconds cumulative time with no restrictions, for 10 hours cumulative time device in reset, TJ
= 150 �C; remaining time at or below 3.6 V 7. The maximum input voltage on an I/O pin tracks with the associated I/P supply maximum. For the injection current
condition on a pin, the voltage will be equal to the supply plus the voltage drop across the internal ESD diode from I/O pin to supply. The diode voltage varies greatly across process and temperature, but a value of 0.3V can be used for nominal calculations. 8. The sum of all controller pins (including both digital and analog) must not exceed 200 mA. A VDDEx/VDDEHx power segment is defined as one or more GPIO pins located between two VDDEx/VDDEHx supply pins. 9. The average current values given in I/O pad current specifications should be used to calculate total I/O segment current. 10. Solder profile per IPC/JEDEC J-STD-020D 11. Moisture sensitivity per JEDEC test method A112

3.2 Electromagnetic interference (EMI) characteristics
Test reports with EMC measurements to IC-level IEC standards are available on request.
To find application notes that provide guidance on designing your system to minimize interference from radiated emissions, go to nxp.com and perform a keyword search for "radiated emissions."

3.3 Electrostatic discharge (ESD) characteristics
Table 2. ESD Ratings1, 2

Symbol VHBM VCDM

Parameter ESD for Human Body Model (HBM) ESD for Charged Device Model (CDM)

Conditions All pins
Corner pins Non-corner pins

Value

Unit

2000

750

500

1. All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. 2. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification
requirements.

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Electrical characteristics
3.4 Operating conditions

The following table describes the operating conditions for the device, and for which all specifications in the data sheet are valid, except where explicitly noted.

If the device operating conditions are exceeded, the functionality of the device is not guaranteed.

Table 3. Device operating conditions

Symbol
fSYS fPLATF fETPU
fEBI fPER fFM_PER tCYC tCYC_ETPU tCYC_PER
TJ TA (TL to TH)
VDD
VDDA_MISC VDDEx
VDDEHx11
VDDEH1
VDDPMC12 VDDPWR VDDFLA VSTBY

Parameter

Conditions

Frequency

Device operating frequency1

Platform operating frequency --

eTPU operating frequency

EBI operating frequency

Peripheral block operating

frequency

Frequency-modulated peripheral -- block operating frequency

Platform clock period

eTPU clock period

Peripheral clock period

Temperature

Junction operating temperature Packaged devices range

Ambient operating temperature Packaged devices range

Voltage

External core supply voltage6, 7 LVD/HVD enabled

LVD/HVD disabled8, 9, 10, 11

TRNG and IRC supply voltage --

I/O supply voltage (fast I/O pads) 5 V range

3.3 V range

I/O supply voltage (medium I/O 5 V range

pads)

3.3 V range

eTPU_A, eSCI_A, eSCI_B, and 5 V range configuration I/O supply voltage (medium I/O pads)

Power Management Controller Full functionality (PMC) supply voltage

SMPS driver supply voltage Flash core voltage

Reference to VSSPWR --

RAM standby supply voltage --

Table continues on the next page...

Min
-- -- -- -- --
--
-- -- --
�40.0
�40.0
1.2 1.2 3.5 4.5 3.0 4.5 3.0 4.5
3.15
3.0 3.15 0.9513

Value Typ

Unit Max

264/3002 MHz

132/1503 MHz

200/2404 MHz

MHz

132/1503 MHz

1/fPLATF ns

1/fETPU

1/fPER

150.0 �C

125.05 �C

1.32

1.38

5.5

3.6

5.5

3.6

5.5

3.6

5.5

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Electrical characteristics
Table 3. Device operating conditions (continued)

Symbol

Parameter

Conditions

VSTBY_BO
VRL_SD
VDDA_SD VDDA_EQA/B
VRH_SD VDDA_SD � VRH_SD
VSSA_SD � VRL_SD VRH_EQ
VDDA_EQA/B � VRH_EQ
VSSA_EQ � VRL_EQ VSSA_EQ � VSS VSSA_SD � VSS VRAMP
IIC

Standby RAM brownout flag trip point voltage SDADC ground reference voltage SDADC supply voltage15 eQADC supply voltage SDADC reference SDADC reference differential voltage VRL_SD differential voltage eQADC reference eQADC reference differential voltage VRL_EQ differential voltage VSSA_EQ differential voltage VSSA_SD differential voltage Slew rate on power supply pins
DC injection current (per pin)16,
17, 18

--
--
-- -- -- --
-- -- --
-- -- -- --
Current Digital pins and analog pins

Min --
4.5 4.75 4.5 --
�25 4.75 --
�25 �25 �25 --
�3.0

Value Typ --
VSSA_SD -- -- VDDA_SD --
-- -- --
-- -- -- --
--

Max 0.914
5.5 5.25 5.5 25
25 5.25 25
25 25 25 100
3.0

Unit
V
V
V V V mV
mV V mV
mV mV mV V/ms
mA

IMAXSEG

Maximum current per power

segment19, 20

�80

1. Maximum operating frequency is applicable to the computational cores and platform for the device. See the Clocking chapter in the MPC5777C Microcontroller Reference Manual for more information on the clock limitations for the various IP blocks on the device.
2. If frequency modulation (FM) is enabled for the operating frequency of 264MHz, the maximum frequency still cannot exceed this value (frequency modulation must spread below nominal frequency). If frequency modulation is enabled for the operating frequency of 300MHz, this maximum frequency can be exceeded (frequency modulation can be center spread from 300MHz).
3. 132 MHz applies to the MPC5777C part number with 264 MHz operating frequency. 150 MHz applies to the version with 300 MHz operating frequency.
4. 200 MHz applies to the MPC5777C part number with 264 MHz max operating frequency. 240 MHz applies to the version with 300 MHz operating frequency.
5. The maximum specification for operating junction temperature TJ must be respected. Thermal characteristics provides details.
6. Core voltage as measured on device pin to guarantee published silicon performance 7. During power ramp, voltage measured on silicon might be lower. Maximum performance is not guaranteed, but correct
silicon operation is guaranteed. See power management and reset management for description. 8. Maximum core voltage is not permitted for entire product life. See absolute maximum rating. 9. When internal LVD/HVDs are disabled, external monitoring is required to guarantee device operation. Failure to monitor
externally supply voltage may result in erroneous operation of the device. 10. This LVD/HVD disabled supply voltage condition only applies after LVD/HVD are disabled by the application during the
reset sequence, and the LVD/HVD are active until that point. 11. This spec does not apply to VDDEH1. 12. When internal flash memory regulator is used:
� Flash memory read operation is supported for a minimum VDDPMC value of 3.15 V. � Flash memory read, program, and erase operations are supported for a minimum VDDPMC value of 3.5 V.

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Electrical characteristics
When flash memory power is supplied externally (VDDPMC shorted to VDDFLA): The VDDPMC range must be within the limits specified for LVD_FLASH and HVD_FLASH monitoring. Table 29 provides the monitored LVD_FLASH and HVD_FLASH limits. 13. If the standby RAM regulator is not used, the VSTBY supply input pin must be tied to ground. 14. VSTBY_BO is the maximum voltage that sets the standby RAM brownout flag in the device logic. The minimum voltage for RAM data retention is guaranteed always to be less than the VSTBY_BO maximum value. 15. For supply voltages between 3.0 V and 4.0 V there will be no guaranteed precision of ADC (accuracy/linearity). ADC will recover to a fully functional state when the voltage rises above 4.0 V. 16. Full device lifetime without performance degradation 17. I/O and analog input specifications are only valid if the injection current on adjacent pins is within these limits. See the absolute maximum ratings table for maximum input current for reliability requirements. 18. The I/O pins on the device are clamped to the I/O supply rails for ESD protection. When the voltage of the input pin is above the supply rail, current will be injected through the clamp diode to the supply rail. For external RC network calculation, assume a typical 0.3 V drop across the active diode. The diode voltage drop varies with temperature. 19. The sum of all controller pins (including both digital and analog) must not exceed 200 mA. A VDDEx/VDDEHx power segment is defined as one or more GPIO pins located between two VDDEx/VDDEHx supply pins. 20. The average current values given in I/O pad current specifications should be used to calculate total I/O segment current.

3.5 DC electrical specifications

NOTE IDDA_MISC is the sum of current consumption of IRC, ITRNG, and ISTBY in the 5 V domain. IRC current is provided in the IRC specifications.

NOTE I/O, XOSC, EQADC, SDADC, and Temperature Sensor current specifications are in those components' dedicated sections.

Table 4. DC electrical specifications

Symbol IDD
IDD_PE IDDPMC
IREGCTL

Parameter

Conditions

Operating current on the VDD core logic supply1
Operating current on the VDD supply for flash memory program/erase Operating current on the VDDPMC supply2
Operating current on the VDDPMC supply (internal core regulator bypassed) Core regulator DC current output on VREGCTL pin

LVD/HVD enabled, VDD = 1.2 V to 1.32 V LVD/HVD disabled, VDD = 1.2 V to 1.38 V --
Flash memory read Flash memory program/erase PMC only Flash memory read Flash memory program/erase PMC only --

Table continues on the next page...

Value Unit
Min Typ Max -- 0.65 1.35 A

-- 0.65 1.4

-- -- 85 mA

-- -- 40 mA

-- -- 70

-- -- 35

-- -- 10 mA

-- -- 40

----

-- -- 25 mA

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Symbol ISTBY
IDD_PWR IBG_REF ITRNG

Electrical characteristics
Table 4. DC electrical specifications (continued)

Parameter Standby RAM supply current
Operating current on the VDDPWR supply Bandgap reference current consumption3 True Random Number Generator current

Conditions
1.08 V, TJ = 150�C 1.25 V to 5.5 V, TJ = 150�C 1.25 V to 5.5 V, TJ = 85�C 1.25 V to 5.5 V, TJ = 40�C --
--

Value Unit
Min Typ Max -- -- 1140 A
1170 360 -- -- 120 -- -- 50 mA -- -- 600 A -- -- 2.1 mA

1. IDD measured on an application-specific pattern with all cores enabled at full frequency, TJ = 40�C to 150�C. Flash memory program/erase current on the VDD supply not included.
2. This value is considering the use of the internal core regulator with the simulation of an external transistor with the minimum value of hFE of 60.
3. This bandgap reference is for EQADC calibration and Temperature Sensors.

3.6 I/O pad specifications

The following table describes the different pad types on the chip.

Table 5. I/O pad specification descriptions

Pad type General-purpose I/O pads EBI pads
LVDS pads Input-only pads

Description
General-purpose I/O and EBI data bus pads with four selectable output slew rate settings; also called SR pads
Provide necessary speed for fast external memory interfaces on the EBI CLKOUT, address, and control signals; also called FC pads
Low Voltage Differential Signal interface pads
Low-input-leakage pads that are associated with the ADC channels

NOTE Each I/O pin on the device supports specific drive configurations. See the signal description table in the device reference manual for the available drive configurations for each I/O pin.
NOTE Throughout the I/O pad specifications, the symbol VDDEx represents all VDDEx and VDDEHx segments.

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Electrical characteristics
3.6.1 Input pad specifications Table 6 provides input DC electrical characteristics as described in Figure 4.

V IN V DD V IH
V IL

V HYS

V INTERNAL (SIU register)

Figure 4. I/O input DC electrical characteristics definition

Table 6. I/O input DC electrical characteristics

Symbol Parameter

Conditions

VIHCMOS_H Input high level CMOS (with hysteresis)
VIHCMOS Input high level CMOS (without hysteresis)
VILCMOS_H Input low level CMOS (with hysteresis)
VILCMOS Input low level CMOS (without hysteresis)
VHYSCMOS Input hysteresis CMOS

ILKG ILKG_FAST
ILKGA
CIN

Digital input leakage
Digital input leakage for EBI address/control signal pads
Analog pin input leakage (5 V range)
Digital input capacitance

3.0 V < VDDEx < 3.6 V and 4.5 V < VDDEx < 5.5 V 3.0 V < VDDEx < 3.6 V and 4.5 V < VDDEx < 5.5 V 3.0 V < VDDEx < 3.6 V and 4.5 V < VDDEx < 5.5 V 3.0 V < VDDEx < 3.6 V and 4.5 V < VDDEx < 5.5 V 3.0 V < VDDEx < 3.6 V and 4.5 V < VDDEx < 5.5 V
Input Characteristics1 VSS < VIN < VDDEx/VDDEHx VSS < VIN < VDDEx/VDDEHx
VSSA_SD < VIN < VDDA_SD, VSSA_EQ < VIN < VDDA_EQA/B GPIO and EBI input pins

Min 0.65 * VDDEx

Value Typ --

Max VDDEx + 0.3

Unit V

0.55 * VDDEx -- VDDEx + 0.3 V

�0.3

-- 0.35 * VDDEx V

�0.3

-- 0.4 * VDDEx V

0.1 * VDDEx

2.5

220

1. For LFAST, microsecond bus, and LVDS input characteristics, see dedicated communication module sections.
Table 7 provides current specifications for weak pullup and pulldown.

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Symbol IWPU
IWPD

Electrical characteristics
Table 7. I/O pullup/pulldown DC electrical characteristics

Parameter Weak pullup current
Weak pulldown current

Conditions
VIN = 0.35 * VDDEx 4.5 V < VDDEx < 5.5 V VIN = 0.35 * VDDEx 3.0 V < VDDEx < 3.6 V VIN = 0.65 * VDDEx 4.5 V < VDDEx < 5.5 V VIN = 0.65 * VDDEx 3.0 V < VDDEx < 3.6 V

Value

Unit

Min

Typ

Max

120

The specifications in Table 8 apply to the pins ANA0_SDA0 to ANA7, ANA16_SDB0 to ANA23_SDC3, and ANB0_SDD0 to ANB7_SDD7.

Table 8. I/O pullup/pulldown resistance electrical characteristics

Symbol Parameter

Conditions

RPUPD PUPD

Analog input bias / diagnostic pullup/ pulldown resistance

200 k 100 k

5 k

RPUPD pullup/pulldown resistance mismatch --

Value

Unit

Min

Typ

Max

130

200

280

100

140

1.4

7.5

3.6.2 Output pad specifications Figure 5 shows output DC electrical characteristics.

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Electrical characteristics
core side input
tPD (low to high)

VDD/2

tPD (high to low)

VDDEx Voh

PAD

Vol

VSSEx

Rise Time

Fall Time

Figure 5. I/O output DC electrical characteristics definition

The following tables specify output DC electrical characteristics.

Table 9. GPIO and EBI data pad output buffer electrical characteristics (SR pads)1

Symbol Parameter IOH GPIO pad output high current
IOL GPIO pad output low current

Conditions2

VOH = 0.8 * VDDEx PCR[SRC] = 11b or 01b

4.5 V < VDDEx < 5.5 V PCR[SRC] = 10b or 00b

VOH = 0.8 * VDDEx PCR[SRC] = 11b or 01b

3.0 V < VDDEx < 3.6 V PCR[SRC] = 10b or 00b

VOL = 0.2 * VDDEx

PCR[SRC] = 11b or 01b

4.5 V < VDDEx < 5.5 V PCR[SRC] = 10b or 00b

VOL = 0.2 * VDDEx

PCR[SRC] = 11b or 01b

3.0 V < VDDEx < 3.6 V PCR[SRC] = 10b or 00b

Table continues on the next page...

Min 25 15 13 8 48 22 17 10.5

Value3 Typ -- -- -- -- -- -- -- --

Max -- -- -- -- -- -- -- --

Unit mA
mA

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Electrical characteristics
Table 9. GPIO and EBI data pad output buffer electrical characteristics (SR pads)1 (continued)

Symbol Parameter

Conditions2

tR_F GPIO pad output transition time (rise/fall)
tPD GPIO pad output propagation delay time
|tSKEW_W| Difference between rise and fall time

PCR[SRC] = 11b

CL = 25 pF

4.5 V < VDDEx < 5.5 V CL = 50 pF

CL = 200 pF

PCR[SRC] = 11b

CL = 25 pF

3.0 V < VDDEx < 3.6 V CL = 50 pF

CL = 200 pF

PCR[SRC] = 10b

CL = 50 pF

4.5 V < VDDEx < 5.5 V CL = 200 pF

PCR[SRC] = 10b

CL = 50 pF

3.0 V < VDDEx < 3.6 V CL = 200 pF

PCR[SRC] = 01b

CL = 50 pF

4.5 V < VDDEx < 5.5 V CL = 200 pF

PCR[SRC] = 01b

CL = 50 pF

3.0 V < VDDEx < 3.6 V CL = 200 pF

PCR[SRC] = 00b

CL = 50 pF

4.5 V < VDDEx < 5.5 V CL = 200 pF

PCR[SRC] = 00b

CL = 50 pF

3.0 V < VDDEx < 3.6 V CL = 200 pF

PCR[SRC] = 11b

CL = 50 pF

4.5 V < VDDEx < 5.5 V CL = 200 pF

PCR[SRC] = 11b

CL = 50 pF

3.0 V < VDDEx < 3.6 V CL = 200 pF

PCR[SRC] = 10b

CL = 50 pF

4.5 V < VDDEx < 5.5 V CL = 200 pF

PCR[SRC] = 10b

CL = 50 pF

3.0 V < VDDEx < 3.6 V CL = 200 pF

PCR[SRC] = 01b

CL = 50 pF

4.5 V < VDDEx < 5.5 V CL = 200 pF

PCR[SRC] = 01b

CL = 50 pF

3.0 V < VDDEx < 3.6 V CL = 200 pF

PCR[SRC] = 00b

CL = 50 pF

4.5 V < VDDEx < 5.5 V CL = 200 pF

PCR[SRC] = 00b

CL = 50 pF

3.0 V < VDDEx < 3.6 V CL = 200 pF

Value3

Unit

Min

Typ

Max

1.2

2.5

1.7

3.25

8.25

19.5

12.5

100

1. All GPIO pad output specifications are valid for 3.0 V < VDDEx < 5.5 V, except where explicitly stated.

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Electrical characteristics
2. PCR[SRC] values refer to the setting of that register field in the SIU. 3. All values to be confirmed during device validation.

The following table shows the EBI CLKOUT, address, and control signal pad electrical characteristics. These pads can also be used for GPIO.

Table 10. GPIO and EBI CLKOUT, address, and control signal pad output buffer electrical characteristics (FC pads)

Symbol CDRV
fMAX_EBI IOH_EBI
IOL_EBI
tR_F_EBI tPD_EBI

Parameter

Conditions1

Min

EBI Mode Output Specifications: valid for 3.0 V < VDDEx < 3.6 V

External bus load

PCR[DSC] = 01b

capacitance

PCR[DSC] = 10b

PCR[DSC] = 11b

External bus maximum CDRV = 10/20/30 pF

operating frequency

GPIO and EBI Mode Output Specifications

GPIO and external bus VOH = 0.8 * VDDEx PCR[DSC] = 11b

pad output high current 4.5 V < VDDEx < 5.5 V PCR[DSC] = 10b

PCR[DSC] = 01b

PCR[DSC] = 00b

VOH = 0.8 * VDDEx PCR[DSC] = 11b

3.0 V < VDDEx < 3.6 V PCR[DSC] = 10b

PCR[DSC] = 01b

PCR[DSC] = 00b

GPIO and external bus VOL = 0.2 * VDDEx

PCR[DSC] = 11b

pad output low current 4.5 V < VDDEx < 5.5 V PCR[DSC] = 10b

PCR[DSC] = 01b

PCR[DSC] = 00b

VOL = 0.2 * VDDEx

PCR[DSC] = 11b

3.0 V < VDDEx < 3.6 V PCR[DSC] = 10b

PCR[DSC] = 01b

PCR[DSC] = 00b

GPIO and external bus PCR[DSC] = 11b

CL = 30 pF

pad output transition time (rise/fall)

CL = 50 pF

PCR[DSC] = 10b

CL = 20 pF

PCR[DSC] = 01b

CL = 10 pF

PCR[DSC] = 00b

CL = 50 pF

GPIO and external bus PCR[DSC] = 11b

CL = 30 pF

pad output propagation delay time

CL = 50 pF

PCR[DSC] = 10b

CL = 20 pF

PCR[DSC] = 01b

CL = 10 pF

PCR[DSC] = 00b

CL = 50 pF

Value Typ
-- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --

Unit Max

MHz

1.5

2.4

1.5

1.85

4.2

5.5

4.2

4.4

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

1. PCR[DSC] values refer to the setting of that register field in the SIU.

Electrical characteristics

3.6.3 I/O pad current specifications

The I/O pads are distributed across the I/O supply segments. Each I/O supply segment is associated with a VDDEx supply segment.
Table 11 provides I/O consumption figures.

To ensure device reliability, the average current of the I/O on a single segment should remain below the IMAXSEG value given in Table 1.
To ensure device functionality, the average current of the I/O on a single segment should remain below the IMAXSEG value given in Table 3.
NOTE The MPC5777C I/O Signal Description and Input Multiplexing Tables are contained in a Microsoft Excel� file attached to the Reference Manual. In the spreadsheet, select the I/O Signal Table tab.

The EBI power segments have been designed to operate within the maximum persegment current specification when the pins on the segment are used for EBI function. If the pins are used instead for GPIO function, the user must ensure the sum of the current used on each pin in the segment does not exceed the spec.

Table 11. I/O consumption

Symbol IAVG_GPIO
IAVG_EBI

Parameter

Conditions

Average I/O current for GPIO pads CL = 25 pF, 2 MHz

(per pad)

VDDEx = 5.0 V � 10%

CL = 50 pF, 1 MHz

VDDEx = 5.0 V � 10%

Average I/O current for external bus output pins (per pad)

CDRV = 10 pF, fEBI = 66 MHz VDDEx = 3.3 V � 10%

CDRV = 20 pF, fEBI = 66 MHz

VDDEx = 3.3 V � 10%

CDRV = 30 pF, fEBI = 66 MHz

VDDEx = 3.3 V � 10%

Value

Unit

Min

Typ

Max

0.42 mA

0.35

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Electrical characteristics
3.7 Oscillator and PLL electrical specifications
The on-chip dual PLL--consisting of the peripheral clock and reference PLL (PLL0) and the frequency-modulated system PLL (PLL1)--generates the system and auxiliary clocks from the main oscillator driver.

IRC XOSC

PLL0

PLL0_PHI PLL0_PHI1

PLL1
Figure 6. PLL integration

PLL1_PHI

3.7.1 PLL electrical specifications
Table 12. PLL0 electrical characteristics

Symbol fPLL0IN PLL0IN fPLL0VCO fPLL0PHI tPLL0LOCK |PLL0PHISPJ| |PLL0PHI1SPJ|
PLL0LTJ
IPLL0

Parameter
PLL0 input clock1, 2 PLL0 input clock duty cycle2 PLL0 VCO frequency PLL0 output frequency
PLL0 lock time PLL0_PHI single period jitter fPLL0IN = 20 MHz (resonator) PLL0_PHI1 single period jitter fPLL0IN = 20 MHz (resonator) PLL0 output long term jitter4 fPLL0IN = 20 MHz (resonator), VCO frequency = 800 MHz
PLL0 consumption

Conditions
-- -- -- --
-- fPLL0PHI = 200 MHz, 6-sigma

Min 8 40 600 4.762
-- --

fPLL0PHI1 = 40 MHz, 6-sigma

10 periods accumulated jitter (80 MHz -- equivalent frequency), 6-sigma pk-pk

16 periods accumulated jitter (50 MHz -- equivalent frequency), 6-sigma pk-pk

long term jitter (< 1 MHz equivalent

frequency), 6-sigma pk-pk)

FINE LOCK state

Value

Typ Max

-- 1250

-- 200/24 03

110

200

3004

-- �250

-- �300

-- �500

7.5

Unit MHz
% MHz MHz
s ps
ps
ps
ps
ps
mA

1. Ensure that the fPLL0IN frequency divided by PLLDIG_PLL0DV[PREDIV] is in the range 8 MHz to 20 MHz. 2. PLL0IN clock retrieved directly from either internal IRC or external XOSC clock. Input characteristics are granted when
using internal IRC or external oscillator is used in functional mode. 3. 200 MHz applies to the MPC5777C part number with 264 MHz operating frequency. 240 MHz applies to the version with
300 MHz operating frequency

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Electrical characteristics

4. Noise on the VDD supply with frequency content below 40 kHz and above 50 MHz is filtered by the PLL. Noise on the VDD supply with frequency content in the range of 40 kHz � 50 MHz must be filtered externally to the device.

Table 13. PLL1 electrical characteristics

Symbol

Parameter

Conditions

fPLL1IN PLL1IN fPLL1VCO fPLL1PHI tPLL1LOCK |PLL1PHISPJ|
fPLL1MOD |PLL1MOD|
IPLL1

PLL1 input clock1 PLL1 input clock duty cycle1 PLL1 VCO frequency PLL1 output clock PHI PLL1 lock time PLL1_PHI single period peak-topeak jitter PLL1 modulation frequency PLL1 modulation depth (when enabled)
PLL1 consumption

-- -- -- -- -- fPLL1PHI = 200 MHz, 6sigma -- Center spread Down spread FINE LOCK state

Min 38 35 600 4.762 -- --
-- 0.25 0.5 --

Value Typ -- -- -- -- -- --

Max 78 65 1250 264/3002 100 5003

Unit
MHz %
MHz MHz s ps

250

kHz

1. PLL1IN clock retrieved directly from either internal PLL0 or external XOSC clock. Input characteristics are granted when using internal PLL0 or external oscillator in functional mode.
2. 264 MHz applies to the MPC5777C part number with 264 MHz max operating frequency. 300 MHz applies to the version with 300 MHz operating frequency
3. Noise on the VDD supply with frequency content below 40 kHz and above 50 MHz is filtered by the PLL. Noise on the VDD supply with frequency content in the range of 40 kHz � 50 MHz must be filtered externally to the device.

3.7.2 Oscillator electrical specifications

NOTE All oscillator specifications in Table 14 are valid for VDDEH6 = 3.0 V to 5.5 V.

Table 14. External oscillator (XOSC) electrical specifications

Symbol

Parameter

Conditions

fXTAL tcst trec VIHEXT VILEXT CS_EXTAL
CS_XTAL

Crystal frequency range

Crystal start-up time1, 2 Crystal recovery time3

TJ = 150 �C --

EXTAL input high voltage (external reference) VREF = 0.28 * VDDEH6 EXTAL input low voltage (external reference) VREF = 0.28 * VDDEH6 Total on-chip stray capacitance on EXTAL pin4 416-ball MAPBGA

516-ball MAPBGA

Total on-chip stray capacitance on XTAL pin4 416-ball MAPBGA

516-ball MAPBGA

Table continues on the next page...

Value

Min

Max

0.5

VREF + 0.6 -- 2.3

-- VREF � 0.6
3.0

2.1

2.8

2.3

3.0

2.2

2.9

Unit
MHz ms ms V V pF
pF

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Electrical characteristics
Table 14. External oscillator (XOSC) electrical specifications (continued)

Symbol

Parameter

Conditions

gm
VEXTAL VHYS IXTAL

Oscillator transconductance5
Oscillation amplitude on the EXTAL pin after startup6 Comparator hysteresis XTAL current6, 7

Low Medium High --
-- --

Value

Min

Max

0.5

1.6

0.1

1.0

Unit mA/V
V V mA

1. This value is determined by the crystal manufacturer and board design. 2. Proper PC board layout procedures must be followed to achieve specifications. 3. Crystal recovery time is the time for the oscillator to settle to the correct frequency after adjustment of the integrated load
capacitor value. 4. See crystal manufacturer's specification for recommended load capacitor (CL) values.The external oscillator requires
external load capacitors when operating in a "low" transconductance range. Account for on-chip stray capacitance (CS_EXTAL/CS_XTAL) and PCB capacitance when selecting a load capacitor value. When operating in a "medium" or "high" transconductance range, the integrated load capacitor value is selected via software to match the crystal manufacturer's specification, while accounting for on-chip and PCB capacitance. 5. Select a "low," "medium," or "high" setting using the UTEST Miscellaneous DCF client's XOSC_LF_EN and XOSC_EN_HIGH fields. "Low" is the setting commonly used for crystals at 8 MHz, "medium" is commonly used for crystals greater than 8 MHz to 20 MHz, and "high" is commonly used for crystals greater than 20 MHz to 40 MHz. However, the user must characterize carefully to determine the best gm setting for the intended application because crystal load capacitance, board layout, and other factors affect the gm value that is needed. The user may need an additional Rshunt to optimize gm depending on the system environment. Use of overtone crystals is not recommended. 6. Amplitude on the EXTAL pin after startup is determined by the ALC block (that is, the Automatic Level Control Circuit). The function of the ALC is to provide high drive current during oscillator startup, while reducing current after oscillation to reduce power, distortion, and RFI, and to avoid over-driving the crystal. The operating point of the ALC is dependent on the crystal value and loading conditions. 7. IXTAL is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded. This is the maximum current during startup of the oscillator. The current after oscillation is typically in the 2�3 mA range and is dependent on the load and series resistance of the crystal. Test circuit is shown in Figure 7.

Table 15. Selectable load capacitance

load_cap_sel[4:0] from DCF record 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010

Load capacitance1, 2 (pF) 1.8 2.8 3.7 4.6 5.6 6.5 7.4 8.4 9.3 10.2 11.2

Table continues on the next page...

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Electrical characteristics
Table 15. Selectable load capacitance (continued)

load_cap_sel[4:0] from DCF record 01011 01100 01101 01110 01111

Load capacitance1, 2 (pF) 12.1 13.0 13.9 14.9 15.8

1. Values are determined from simulation across process corners and voltage and temperature variation. Capacitance values vary �12% across process, 0.25% across voltage, and no variation across temperature.
2. Values in this table do not include the die and package capacitances given by CS_XTAL/CS_EXTAL in Table 14.
VDDEH6

ALC

Bias Current

IXTAL

XTAL

A V

EXTAL VSSOSC VSS

Z = R + jL

Tester

PCB GND

Figure 7. Test circuit

-
+
OFF

Comparator

Conditions
VEXTAL = 0 V VXTAL = 0 V ALC INACTIVE

Symbol
fTarget fvar_T

Table 16. Internal RC (IRC) oscillator electrical specifications

Parameter
IRC target frequency IRC frequency variation

Conditions
-- T < 150 �C

Value Unit
Min Typ Max

-- 16 -- MHz

�8 --

3.8 Analog-to-Digital Converter (ADC) electrical specifications

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Electrical characteristics
3.8.1 Enhanced Queued Analog-to-Digital Converter (eQADC)
Table 17. eQADC conversion specifications (operating)

Symbol

Parameter

fADCLK CC TSR -- INL DNL
OFFNC OFFWC GAINNC GAINWC
IINJ EINJ TUE GAINVGA1
GAINVGA2
GAINVGA4
IADC IADR

ADC Clock (ADCLK) Frequency Conversion Cycles Stop Mode Recovery Time2 Resolution3 INL: 16.5 MHz eQADC clock4 INL: 33 MHz eQADC clock4 DNL: 16.5 MHz eQADC clock4 DNL: 33 MHz eQADC clock4 Offset Error without Calibration Offset Error with Calibration Full Scale Gain Error without Calibration Full Scale Gain Error with Calibration Disruptive Input Injection Current6, 7, 8, 9 Incremental Error due to injection current10, 11 TUE value12, 13 (with calibration) Variable gain amplifier accuracy (gain = 1)14 INL, 16.5 MHz ADC INL, 33 MHz ADC DNL, 16.5 MHz ADC DNL, 33 MHz ADC Variable gain amplifier accuracy (gain = 2)14 INL, 16.5 MHz ADC INL, 33 MHz ADC DNL, 16.5 MHz ADC DNL, 33 MHz ADC Variable gain amplifier accuracy (gain = 4)14 INL, 16.5 MHz ADC INL, 33 MHz ADC DNL, 16.5 MHz ADC DNL, 33 MHz ADC Current consumption per ADC (two ADCs per EQADC) Reference voltage current consumption per EQADC

Value

Min

Max

2 2 + 13

33 128 + 151

1.25

�4

�6

�3

140

�8

�150

�8

�3

�8

�4

�8

�315

315

�315

315

�5

�8

�3

�7

�8

�4

200

Unit MHz ADCLK cycles s mV LSB5 LSB LSB LSB LSB LSB LSB LSB mA Counts Counts Counts16
Counts
Counts
mA A

1. 128 sampling cycles (LST=128), differential conversion, pregain of x4 2. Stop mode recovery time is the time from the setting of either of the enable bits in the ADC Control Register to the time
that the ADC is ready to perform conversions. Delay from power up to full accuracy = 8 ms. 3. At VRH_EQ � VRL_EQ = 5.12 V, one count = 1.25 mV without using pregain. Based on 12-bit conversion result; does not
account for AC and DC errors 4. INL and DNL are tested from VRL + 50 LSB to VRH � 50 LSB.

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Electrical characteristics
5. At VRH_EQ � VRL_EQ = 5.12 V, one LSB = 1.25 mV. 6. Below disruptive current conditions, the channel being stressed has conversion values of $3FF for analog inputs greater
than VRH and $000 for values less than VRL. Other channels are not affected by non-disruptive conditions. 7. Exceeding limit may cause conversion error on stressed channels and on unstressed channels. Transitions within the limit
do not affect device reliability or cause permanent damage. 8. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor,
calculate resistance values using VPOSCLAMP = VDDA + 0.5 V and VNEGCLAMP = �0.3 V, then use the larger of the calculated values. 9. Condition applies to two adjacent pins at injection limits. 10. Performance expected with production silicon. 11. All channels have same 10 k < Rs < 100 k Channel under test has Rs = 10 k, IINJ=IINJMAX,IINJMIN. 12. The TUE specification is always less than the sum of the INL, DNL, offset, and gain errors due to cancelling errors. 13. TUE, Gain, and Offset specifications do not apply to differential conversions. 14. Variable gain is controlled by setting the PRE_GAIN bits in the ADC_ACR1-8 registers to select a gain factor of �1, �2, or �4. Settings are for differential input only. Tested at �1 gain. Values for other settings are guaranteed as indicated. 15. Guaranteed 10-bit monotonicity. 16. At VRH_EQ � VRL_EQ = 5.12 V, one LSB = 1.25 mV.

3.8.2 Sigma-Delta ADC (SDADC)

The SDADC is a 16-bit Sigma-Delta analog-to-digital converter with a 333 Ksps maximum output conversion rate.

NOTE The voltage range is 4.5 V to 5.5 V for SDADC specifications, except where noted otherwise.

Table 18. SDADC electrical specifications

Symbol Parameter

Conditions

Min

VIN

ADC input signal

VIN_PK2PK1

Input range peak to peak
VIN_PK2PK = VINP2 � VINM, 3

Single ended VINM = VRL_SD Single ended VINM = 0.5*VRH_SD

GAIN = 1

Single ended

VINM = 0.5*VRH_SD GAIN = 2,4,8,16

Differential

0 < VIN < VDDEx

fADCD_M

SD clock frequency4 --

fADCD_S

Conversion rate

Oversampling ratio Internal modulator

RESOLUTION SD register resolution5 2's complement notation

Table continues on the next page...

Value

Typ

Max

VDDA_SD

VRH_SD/GAIN

�0.5*VRH_SD

�VRH_SD/GAIN

14.4

333

256

Unit V V
MHz Ksps
-- bit

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Electrical characteristics
Table 18. SDADC electrical specifications (continued)

Symbol GAIN |GAIN|
VOFFSET

Parameter ADC gain Absolute value of the ADC gain error6, 7
Conversion offset6, 7

Conditions Min

Defined through

SDADC_MCR[PGAN]. Only integer

powers of 2 are valid gain values.

Before calibration (applies to gain

setting = 1)

After calibration

VRH_SD < 5%, VDDA_SD < 10%

TJ < 50 �C

After calibration

VRH_SD < 5%, VDDA_SD < 10%

TJ < 100 �C

After calibration

VRH_SD < 5%, VDDA_SD < 10%
TJ < 150 �C
Before calibration (applies to all gain -- settings: 1, 2, 4, 8, 16)

After calibration

VDDA_SD < 10%

TJ < 50 �C

After calibration

VDDA_SD < 10%

TJ < 100 �C

After calibration

VDDA_SD < 10% TJ < 150 �C

Table continues on the next page...

Value Typ -- -- --
--
--
10*(1+1/ gain) --
--
--

Max 16 1.5 5
7.5
10
20 5
7.5
10

Unit -- % mV
mV

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Electrical characteristics
Table 18. SDADC electrical specifications (continued)

Symbol Parameter

Conditions

SNRDIFF150 SNRDIFF333

Signal to noise ratio in 4.5 V < VDDA_SD < 5.5 V8, 9

differential mode, 150 Ksps output rate

VRH_SD = VDDA_SD

GAIN = 1

4.5 V < VDDA_SD < 5.5 V8, 9

VRH_SD = VDDA_SD

GAIN = 2

4.5 V < VDDA_SD < 5.5 V8, 9

VRH_SD = VDDA_SD

GAIN = 4

4.5 V < VDDA_SD < 5.5 V8, 9

VRH_SD = VDDA_SD

GAIN = 8

4.5 V < VDDA_SD < 5.5 V8, 9

VRH_SD = VDDA_SD

GAIN = 16

Signal to noise ratio in 4.5 V < VDDA_SD < 5.5 V8, 9

differential mode, 333 Ksps output rate

VRH_SD = VDDA_SD

GAIN = 1

4.5 V < VDDA_SD < 5.5 V8, 9

VRH_SD = VDDA_SD

GAIN = 2

4.5 V < VDDA_SD < 5.5 V8, 9

VRH_SD = VDDA_SD

GAIN = 4

4.5 V < VDDA_SD < 5.5 V8, 9

VRH_SD = VDDA_SD

GAIN = 8

4.5 V < VDDA_SD < 5.5 V8, 9

VRH_SD = VDDA_SD

GAIN = 16

Value

Unit

Min

Typ

Max

Table continues on the next page...

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Electrical characteristics
Table 18. SDADC electrical specifications (continued)

Symbol Parameter

Conditions

Min

SNRSE150 Signal to noise ratio in 4.5 V < VDDA_SD < 5.5 V8, 9

single ended mode, 150 Ksps output rate

VRH_SD = VDDA_SD

GAIN = 1

4.5 V < VDDA_SD < 5.5 V8, 9

VRH_SD = VDDA_SD

GAIN = 2

4.5 V < VDDA_SD < 5.5 V8, 9

VRH_SD = VDDA_SD

GAIN = 4

4.5 V < VDDA_SD < 5.5 V8, 9

VRH_SD = VDDA_SD

GAIN = 8

4.5 V < VDDA_SD < 5.5 V8, 9

VRH_SD = VDDA_SD

GAIN = 16

SINADDIFF150 Signal to noise and Gain = 1

distortion ratio in differential mode, 150

4.5 V < VDDA_SD < 5.5 V

Ksps output rate

VRH_SD = VDDA_SD

Gain = 2

4.5 V < VDDA_SD < 5.5 V

VRH_SD = VDDA_SD

Gain = 4

4.5 V < VDDA_SD < 5.5 V VRH_SD = VDDA_SD Gain = 8

68.8

4.5 V < VDDA_SD < 5.5 V VRH_SD = VDDA_SD Gain = 16

64.8

4.5 V < VDDA_SD < 5.5 V VRH_SD = VDDA_SD

Table continues on the next page...

Value Typ -- -- -- -- -- -- -- -- -- --

Max -- -- -- -- -- -- -- -- -- --

Unit dB
dBFS

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Electrical characteristics
Table 18. SDADC electrical specifications (continued)

Symbol Parameter

Conditions

Min

SINADDIFF333 Signal to noise and Gain = 1

distortion ratio in differential mode, 333

4.5 V < VDDA_SD < 5.5 V

Ksps output rate

VRH_SD = VDDA_SD

Gain = 2

4.5 V < VDDA_SD < 5.5 V

VRH_SD = VDDA_SD

Gain = 4

4.5 V < VDDA_SD < 5.5 V

VRH_SD = VDDA_SD

Gain = 8

4.5 V < VDDA_SD < 5.5 V

VRH_SD = VDDA_SD

Gain = 16

4.5 V < VDDA_SD < 5.5 V

VRH_SD = VDDA_SD

SINADSE150 Signal to noise and Gain = 1

distortion ratio in single-ended mode,

4.5 V < VDDA_SD < 5.5 V

150 Ksps output rate VRH_SD = VDDA_SD

Gain = 2

4.5 V < VDDA_SD < 5.5 V

VRH_SD = VDDA_SD

Gain = 4

4.5 V < VDDA_SD < 5.5 V

VRH_SD = VDDA_SD

Gain = 8

4.5 V < VDDA_SD < 5.5 V

VRH_SD = VDDA_SD

Gain = 16

4.5 V < VDDA_SD < 5.5 V VRH_SD = VDDA_SD

Table continues on the next page...

Value

Typ

Max

Unit dBFS
dBFS

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Electrical characteristics
Table 18. SDADC electrical specifications (continued)

Symbol THDDIFF150
THDDIFF333

Parameter

Conditions

Min

Total harmonic

Gain = 1

distortion in differential mode, 150 Ksps

4.5 V < VDDA_SD < 5.5 V

output rate

VRH_SD = VDDA_SD

Gain = 2

4.5 V < VDDA_SD < 5.5 V

VRH_SD = VDDA_SD

Gain = 4

4.5 V < VDDA_SD < 5.5 V

VRH_SD = VDDA_SD

Gain = 8

4.5 V < VDDA_SD < 5.5 V

VRH_SD = VDDA_SD

Gain = 16

4.5 V < VDDA_SD < 5.5 V

VRH_SD = VDDA_SD

Total harmonic

Gain = 1

distortion in differential mode, 333 Ksps

4.5 V < VDDA_SD < 5.5 V

output rate

VRH_SD = VDDA_SD

Gain = 2

4.5 V < VDDA_SD < 5.5 V

VRH_SD = VDDA_SD

Gain = 4

4.5 V < VDDA_SD < 5.5 V

VRH_SD = VDDA_SD

Gain = 8

4.5 V < VDDA_SD < 5.5 V

VRH_SD = VDDA_SD

Gain = 16

4.5 V < VDDA_SD < 5.5 V VRH_SD = VDDA_SD

Table continues on the next page...

Value Typ -- -- -- -- -- -- -- -- -- --

Max -- -- -- -- -- -- -- -- -- --

Unit dBFS
dBFS

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Symbol THDSE150
SFDR ZDIFF
ZCM
RBIAS VINTCM
VBIAS VBIAS CMRR RCaaf fPASSBAND RIPPLE

Electrical characteristics
Table 18. SDADC electrical specifications (continued)

Parameter

Conditions

Min

Total harmonic

Gain = 1

distortion in singleended mode, 150

4.5 V < VDDA_SD < 5.5 V

Ksps output rate

VRH_SD = VDDA_SD

Gain = 2

4.5 V < VDDA_SD < 5.5 V

VRH_SD = VDDA_SD

Gain = 4

4.5 V < VDDA_SD < 5.5 V

VRH_SD = VDDA_SD

Gain = 8

4.5 V < VDDA_SD < 5.5 V

VRH_SD = VDDA_SD

Gain = 16

4.5 V < VDDA_SD < 5.5 V

VRH_SD = VDDA_SD

Spurious free dynamic Any GAIN

range

Differential input impedance10, 11

GAIN = 1 GAIN = 2

1000 600

GAIN = 4

300

GAIN = 8

200

GAIN = 16

200

Common Mode input GAIN = 1

impedance11, 12

GAIN = 2

1400 1000

GAIN = 4

700

GAIN = 8

500

GAIN = 16

500

Bare bias resistance --

110

Common Mode input --

�12

reference voltage13

Bias voltage

Bias voltage accuracy --

�2.5

Common mode

rejection ratio

Anti-aliasing filter

External series resistance

Filter capacitances

220

Pass band9

0.01

Pass band ripple14

0.333 * fADCD_S

�1

Table continues on the next page...

Value

Typ

Max

Unit dBFS

1250 800 400 250 250 1800 1300 950 650 650 144 --

1500

1000

500

300

2200

1600

1150

800

180

+12

VRH_SD/2

+2.5

0.333 * fADCD_S kHz

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Electrical characteristics
Table 18. SDADC electrical specifications (continued)

Symbol Frolloff GROUP
fHIGH tSTARTUP tLATENCY

Parameter

Conditions

Min

Stop band attenuation [0.5 * fADCD_S, 1.0 * fADCD_S]

[1.0 * fADCD_S, 1.5 * fADCD_S]

[1.5 * fADCD_S, 2.0 * fADCD_S]

[2.0 * fADCD_S, 2.5 * fADCD_S]

[2.5 * fADCD_S, fADCD_M/2]

Group delay

Within pass band: Tclk is fADCD_M / 2 --

OSR = 24

OSR = 28

OSR = 32

OSR = 36

OSR = 40

OSR = 44

OSR = 48

OSR = 56

OSR = 64

OSR = 72

OSR = 75

OSR = 80

OSR = 88

OSR = 96

OSR = 112

OSR = 128

OSR = 144

OSR = 160

OSR = 176

OSR = 192

OSR = 224

OSR = 256

Distortion within pass band
High pass filter 3 dB Enabled frequency

�0.5/ fADCD_S
--

Startup time from

power down state

Latency between input HPF = ON

data and converted

data when input mux does not change15

HPF = OFF

Value

Typ

Max

235.5

275

314.5

354

393.5

433

472.5

551.5

630.5

709.5

696

788.5

867.5

946.5

1104.5

1262.5

1420.5

1578.5

1736.5

1894.5

2210.5

2526.5

+0.5/ fADCD_S

10e�5*

fADCD_S

100

GROUP +

fADCD_S

GROUP

Table continues on the next page...

Unit dB -- Tclk
-- -- s --

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Electrical characteristics
Table 18. SDADC electrical specifications (continued)

Symbol Parameter

Conditions

Min

tSETTLING Settling time after mux Analog inputs are muxed

change

HPF = ON

HPF = OFF

tODRECOVERY Overdrive recovery

After input comes within range from

time

saturation

HPF = ON

HPF = OFF

CS_D

SDADC sampling

GAIN = 1, 2, 4, 8

capacitance after sampling switch16

GAIN = 16

IBIAS

Bias consumption

At least one SDADC enabled

IADV_D

SDADC supply

Per SDADC enabled

consumption

IADR_D

SDADC reference

Per SDADC enabled

current consumption

Value

Typ

Max

2*GROUP +

3*fADCD_S

2*GROUP +

2*fADCD_S

2*GROUP +

fADCD_S

Unit --
--

2*GROUP

75*GAIN

600

3.5

4.325

1. For input voltage above the maximum and below the clamp voltage of the input pad, there is no latch-up concern, and the signal will only be "clipped."
2. VINP is the input voltage applied to the positive terminal of the SDADC 3. VINM is the input voltage applied to the negative terminal of the SDADC 4. Sampling is generated internally fSAMPLING = fADCD_M/2 5. For Gain = 16, SDADC resolution is 15 bit. 6. Calibration of gain is possible when gain = 1. Offset Calibration should be done with respect to 0.5*VRH_SD for differential
mode and single ended mode with negative input = 0.5*VRH_SD. Offset Calibration should be done with respect to 0 for single ended mode with negative input = 0. Both Offset and Gain Calibration is guaranteed for +/�5% variation of VRH_SD, +/�10% variation of VDDA_SD, +/�50 C temperature variation. 7. Offset and gain error due to temperature drift can occur in either direction (+/�) for each of the SDADCs on the device. 8. SDADC is functional in the range 3.6 V < VDDA_SD < 4.0 V: SNR parameter degrades by 3 dB. SDADC is functional in the range 3.0 V < VRH_SD < 4.0 V: SNR parameter degrades by 9 dB. 9. SNR values guaranteed only if external noise on the ADC input pin is attenuated by the required SNR value in the frequency range of fADCD_M � fADCD_S to fADCD_M + fADCD_S, where fADCD_M is the input sampling frequency and fADCD_S is the output sample frequency. A proper external input filter should be used to remove any interfering signals in this frequency range. 10. Input impedance in differential mode ZIN = ZDIFF 11. Input impedance given at fADCD_M = 16 MHz. Impedance is inversely proportional to SDADC clock frequency. ZDIFF (fADCD_M) = (16 MHz / fADCD_M) * ZDIFF, ZCM (fADCD_M) = (16 MHz / fADCD_M) * ZCM. 12. Input impedance in single-ended mode ZIN = (2 * ZDIFF * ZCM) / (ZDIFF + ZCM) 13. VINTCM is the Common Mode input reference voltage for the SDADC. It has a nominal value of (VRH_SD - VRL_SD) / 2. 14. The �1% passband ripple specification is equivalent to 20 * log10 (0.99) = 0.087 dB. 15. Propagation of the information from the pin to the register CDR[CDATA] and the flags SFR[DFEF] and SFR[DFFF] is given by the different modules that must be crossed: delta/sigma filters, high pass filter, FIFO module, and clock domain synchronizers. The time elapsed between data availability at the pin and internal SDADC module registers is given by the following formula, where fADCD_S is the frequency of the sampling clock, fADCD_M is the frequency of the modulator, and fFM_PER_CLK is the frequency of the peripheral bridge clock feeds to the SDADC module:
REGISTER LATENCY = tLATENCY + 0.5/fADCD_S + 2 (~+1)/fADCD_M + 2(~+1)fFM_PER_CLK
The (~+1) symbol refers to the number of clock cycles uncertainty (from 0 to 1 clock cycle) to be added due to resynchronization of the signal during clock domain crossing.

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Electrical characteristics
Some further latency may be added by the target module (core, DMA, interrupt) controller to process the data received from the SDADC module. 16. This capacitance does not include pin capacitance, that can be considered together with external capacitance, before sampling switch.

3.9 Temperature Sensor

The following table describes the Temperature Sensor electrical characteristics.

Table 19. Temperature Sensor electrical characteristics

Symbol

Parameter

Conditions

-- TSENS TACC ITEMP_SENS

Temperature monitoring range Sensitivity Accuracy VDDA_EQA power supply current, per Temp Sensor

-- -- �40�C < TJ < 150�C --

Value

Min

Typ

Max

�40

150

5.18

�5

700

Unit
�C mV/�C
�C A

3.10 LVDS Fast Asynchronous Serial Transmission (LFAST) pad electrical characteristics
The LFAST pad electrical characteristics apply to the SIPI interface on the chip. The same LVDS pad is used for the Microsecond Channel (MSC) and DSPI LVDS interfaces, with different characteristics given in the following tables.

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

3.10.1 LFAST interface timing diagrams
Signal excursions above this level NOT allowed
Max. common mode input at RX
|Vo D| Max Differential Voltage = 285 mV p-p (LFAST) 400 mV p-p (MSC/DSPI)
Minimum Data Bit Time Opening = 0.55 * T (LFAST) 0.50 * T (MSC/DSPI)

Electrical characteristics
1743 mV 1600 mV

|Vo D| Min Differential Voltage = 100 mV p-p (LFAST) 150 mV p-p (MSC/DSPI)

"No-Go" Area

VOS = 1.2 V +/- 10% TX common mode
VICOM

|PEREYE

Data Bit Period T = 1 /FDATA

|PEREYE

Min. common mode input at RX Signal excursions below this level NOT allowed

150 mV 0 V

Figure 8. LFAST and MSC/DSPI LVDS timing definition

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Electrical characteristics H
lfast_pwr_down L

Differential TX Data Lines

pad_p/pad_n

tPD2NM_TX Data Valid

Figure 9. Power-down exit time

VIH
Differential TX Data Lines

90%

pad_p/pad_n

VIL

10%

tTR

Figure 10. Rise/fall time

3.10.2 LFAST and MSC/DSPI LVDS interface electrical characteristics

The following table contains the electrical characteristics for the LFAST interface.

Table 20. LVDS pad startup and receiver electrical characteristics1

Symbol

Parameter

Conditions

tSTRT_BIAS

Bias current reference startup time4

STARTUP2,3 --

Table continues on the next page...

Value Unit
Min Typ Max

0.5

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Electrical characteristics
Table 20. LVDS pad startup and receiver electrical characteristics1 (continued)

Symbol tPD2NM_TX
tSM2NM_TX
tPD2NM_RX
tPD2SM_RX
ILVDS_BIAS
Z0
ZDIFF
VICOM |VI| VHYS RIN CIN ILVDS_RX

Parameter

Conditions

Transmitter startup time (power down to -- Normal mode)5

Transmitter startup time (Sleep mode to Not applicable to the MSC/DSPI

Normal mode)6

LVDS pad

Receiver startup time (power down to -- Normal mode)7

Receiver startup time (power down to Sleep mode)8

Not applicable to the MSC/DSPI LVDS pad

LVDS bias current consumption

Tx or Rx enabled

TRANSMISSION LINE CHARACTERISTICS (PCB Track)

Transmission line characteristic

impedance

Transmission line differential impedance --

RECEIVER

Common mode voltage

Differential input voltage

Input hysteresis

Terminating resistance Differential input capacitance11

VDDEH = 3.0 V to 5.5 V --

Receiver DC current consumption

Enabled

Min --
--
--
--
--
47.5
95
0.159 100 25 80 -- --

Value Typ

Unit Max

0.4 2.75 s

0.2

0.5 s

40 ns

50 ns

-- 0.95 mA

50 52.5 100 105

1.610 V

-- mV

125 150

3.5

6.0 pF

0.5 mA

1. The LVDS pad startup and receiver electrical characteristics in this table apply to both the LFAST and the MSC/DSPI LVDS pad except where noted in the conditions.
2. All startup times are defined after a 2 peripheral bridge clock delay from writing to the corresponding enable bit in the LVDS control registers (LCR) of the LFAST and High-Speed Debug modules.
3. Startup times are valid for the maximum external loads CL defined in both the LFAST/HSD and MSC/DSPI transmitter electrical characteristic tables.
4. Bias startup time is defined as the time taken by the current reference block to reach the settling bias current after being enabled.
5. Total transmitter startup time from power down to normal mode is tSTRT_BIAS + tPD2NM_TX + 2 peripheral bridge clock periods.
6. Total transmitter startup time from sleep mode to normal mode is tSM2NM_TX + 2 peripheral bridge clock periods. Bias block remains enabled in sleep mode.
7. Total receiver startup time from power down to normal mode is tSTRT_BIAS + tPD2NM_RX + 2 peripheral bridge clock periods. 8. Total receiver startup time from power down to sleep mode is tPD2SM_RX + 2 peripheral bridge clock periods. Bias block
remains enabled in sleep mode. 9. Absolute min = 0.15 V � (285 mV/2) = 0 V 10. Absolute max = 1.6 V + (285 mV/2) = 1.743 V 11. Total internal capacitance including receiver and termination, co-bonded GPIO pads, and package contributions. For bare
die devices, subtract the package value given in Figure 11.

Table 21. LFAST transmitter electrical characteristics1

Symbol fDATA Data rate

Parameter

Conditions

-- Table continues on the next page...

Value

Unit

Min Typ

Max

240 Mbps

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Electrical characteristics
Table 21. LFAST transmitter electrical characteristics1 (continued)

Symbol

Parameter

VOS |VOD|
tTR CL

Common mode voltage Differential output voltage swing (terminated)2,3 Rise/fall time (10% � 90% of swing)2,3 External lumped differential load capacitance2

ILVDS_TX Transmitter DC current consumption

Conditions
-- -- -- VDDE = 4.5 V VDDE = 3.0 V Enabled

Value

Unit

Min Typ

Max

1.08

1.32

110

200

285

0.26

1.5

12.0

8.5

3.2

1. The LFAST pad electrical characteristics are based on worst-case internal capacitance values shown in Figure 11. 2. Valid for maximum data rate fDATA. Value given is the capacitance on each terminal of the differential pair, as shown in
Figure 11. 3. Valid for maximum external load CL.

Table 22. MSC/DSPI LVDS transmitter electrical characteristics1

Symbol

Parameter

fDATA VOS |VOD| tTR CL

Data rate Common mode voltage Differential output voltage swing (terminated)2,3 Rise/Fall time (10%�90% of swing)2,3 External lumped differential load capacitance2

ILVDS_TX Transmitter DC current consumption

Conditions
-- -- -- -- VDDE = 4.5 V VDDE = 3.0 V Enabled

Value

Unit

Min

Typ

Max

80 Mbps

1.08

1.32

150

200

400 mV

0.8

4.0

1. The MSC and DSPI LVDS pad electrical characteristics are based on the application circuit and typical worst-case internal capacitance values given in Figure 11.
2. Valid for maximum data rate fDATA. Value given is the capacitance on each terminal of the differential pair, as shown in Figure 11.
3. Valid for maximum external load CL.

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Electrical characteristics

GPIO Driver

bond pad

1pF 2.5pF

LVDS Driver

CL
100 terminator

bond pad

GPIO Driver 2.5pF

CL 1pF

Die

Package

PCB

Figure 11. LVDS pad external load diagram

3.10.3 LFAST PLL electrical characteristics

The following table contains the electrical characteristics for the LFAST PLL.

Table 23. LFAST PLL electrical characteristics1

Symbol

Parameter

Conditions

fRF_REF ERRREF DCREF
PN
fVCO tLOCK

PLL reference clock frequency

PLL reference clock frequency error

PLL reference clock duty cycle

Integrated phase noise (single side band) fRF_REF = 20 MHz

fRF_REF = 10 MHz

PLL VCO frequency

PLL phase lock3

Table continues on the next page...

Value Unit
Min Nominal Max

26 MHz

�1

�58 dBc

�64

4802

-- MHz

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Electrical characteristics
Table 23. LFAST PLL electrical characteristics1 (continued)

Symbol

Parameter

Conditions

Value Unit
Min Nominal Max

PERREF Input reference clock jitter (peak to peak) Single period, fRF_REF = 10 MHz

Long term, fRF_REF = 10 MHz

�500

PEREYE Output Eye Jitter (peak to peak)4

300 ps 500 400 ps

1. The specifications in this table apply to both the interprocessor bus and debug LFAST interfaces. 2. The 480 MHz frequency is achieved with a 10 MHz or 20 MHz reference clock. With a 13 MHz or 26 MHz reference, the
VCO frequency is 468 MHz. 3. The time from the PLL enable bit register write to the start of phase locks is maximum 2 clock cycles of the peripheral
bridge clock that is connected to the PLL on the device. 4. Measured at the transmitter output across a 100 Ohm termination resistor on a device evaluation board. See Figure 11.

3.11 Power management: PMC, POR/LVD, power sequencing

3.11.1 Power management electrical characteristics
The power management module monitors the different power supplies. It also generates the internal supplies that are required for correct device functionality. The power management is supplied by the VDDPMC supply.

3.11.1.1 LDO mode recommended power transistors

Only specific orderable part numbers of MPC5777C support LDO regulation mode. See Ordering information for MPC5777C parts that support this regulation mode.

The following NPN transistors are recommended for use with the on-chip LDO voltage regulator controller: ON SemiconductorTM NJD2873. The collector of the external transistor is preferably connected to the same voltage supply source as the output stage of the regulator.

The following table describes the characteristics of the power transistors.

Table 24. Recommended operating characteristics

Symbol
hFE PD ICMaxDC VCESAT VBE Vc

Parameter DC current gain (Beta) Absolute minimum power dissipation Maximum DC collector current Collector to emitter saturation voltage Base to emitter voltage Minimum voltage at transistor collector

Value

Unit

60-550

1.60

2.0

300

0.95

2.5

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Electrical characteristics

The following table shows the recommended components to be used in LDO regulation mode.

Table 25. Recommended operating characteristics

Part name Part type

Nominal

Description

NPN BJT hFE = 400

NJD2873: ON Semiconductor LDO voltage regulator controller (VRC)

Capacitor 4.7 �F - 20 V

Ceramic capacitor, total ESR < 70 m

Capacitor 0.047�0.049 �F - 7 V Ceramic--one capacitor for each VDD pin

Capacitor 22 �F - 20 V

Ceramic VDDPMC (optional 0.1 �F)

Capacitor 22 �F - 20 V

Ceramic supply decoupling capacitor, ESR < 50 m (as close as possible

to NPN collector)

Capacitor 0.1 �F - 7 V

Ceramic VDDPWR

Resistor Application specific Optional; reduces thermal loading on the NPN with high VDDPMC levels

The following diagram shows the LDO configuration connection.

VDDPMC REGSEL VSSPMC (clean ground) VDDPWR

REGCTL

VSSPWR

VDD VSS

Figure 12. VRC 1.2 V LDO configuration

3.11.1.2 SMPS mode recommended external components and characteristics
The following table shows the recommended components to be used in SMPS regulation mode.

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Electrical characteristics
Table 26. Recommended operating characteristics

Part name Part type

Nominal

p-MOS 3 A - 20 V

Schottky 2 A - 20 V

Inductor 3-4 H - 1.5 A

Capacitor 22 F - 20 V

Capacitor 0.1 F - 7 V

Capacitor 22 F - 20 V

Resistor 2.0-4.7 k

Capacitor 22 F - 20 V

Description
SQ2301ES / FDC642P or equivalent: low threshold p-MOS, Vth < 2.0 V, Rdson @ 4.5 V < 100 m, Cg < 5 nF
SS8P3L or equivalent: VishayTM low Vf Schottky diode
Buck shielded coil low ESR
Ceramic capacitor, total ESR < 70 m
Ceramic--one capacitor for each VDD pin Ceramic VDDPMC (optional 0.1 F capacitor in parallel) Ceramic supply decoupling capacitor, ESR < 50 m (as close as possible to the p-MOS source)
Pullup for power p-MOS gate
Ceramic, connect 100 nF capacitor in parallel (as close as possible to package to reduce current loop from VDDPWR to VSSPWR)

The following diagram shows the SMPS configuration connection.

CD
D1 L
CI

CV
R Q1
CB
CE

VDDPMC REGSEL VSSPMC (clean ground) VDDPWR
REGCTL VSSPWR
VDD VSS

Figure 13. SMPS configuration
NOTE The REGSEL pin is tied to VDDPMC to select SMPS. If REGSEL is 0, the chip boots with the linear regulator. See Power sequencing requirements for details about VDDPMC and VDDPWR.

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

The SMPS regulator characteristics appear in the following table.

Electrical characteristics

Table 27. SMPS electrical characteristics

Symbol
SMPSCLOCK SMPSSLOPE
SMPSEFF

Parameter
SMPS oscillator frequency SMPS soft-start ramp slope SMPS typical efficiency

Conditions
Trimmed -- --

Value

Unit

Min

Typ

Max

825

1000 1220 kHz

0.01 0.025 0.05 V/s

3.11.2 Power management integration To ensure correct functionality of the device, use the following recommended integration scheme for LDO mode.
C HV_PMC

C SMPSPWR

2 HV_IO

VDDPWR VSSPWR VDDE(H)x VSS

VDDPMC VDDFLA
VSS

C HV_FLA

MPC5777C

VDD VSS REF BYPC VSS

1 LV

C REFEQ

VDDA_SD VSSA_SD VDDA_EQA VSSA_EQ VDDA_EQB VSSA_EQ

C HV_ADC_D C HV_ADC_EQA C HV_ADC_EQB

1 One capacitance near each VDD pin 2 One capacitance near each VDDE(H)x pin

Figure 14. Recommended supply pin circuits

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Electrical characteristics
The following table describes the supply stability capacitances required on the device for proper operation.

Table 28. Device power supply integration

Symbol CLV

Parameter Minimum VDD external bulk capacitance2, 3

CSMPSPWR CHV_PMC

Minimum SMPS driver supply capacitance Minimum VDDPMC external bulk capacitance4, 5

CHV_IO

Minimum VDDEx/VDDEHx external capacitance2

CHV_FLA

Minimum VDD_FLA external capacitance7

CHV_ADC_EQA/B Minimum VDDA_EQA/B external capacitance8

CREFEQ

Minimum REFBYPCA/B external capacitance9

CHV_ADC_SD Minimum VDDA_SD external capacitance10

Conditions
LDO mode SMPS mode -- LDO mode SMPS mode -- -- -- -- --

Value1 Unit
Min Typ Max 4.7 -- -- F 22 -- -- F 22 -- -- F 22 -- -- F 22 -- -- F -- 4.76 -- F 1.0 2.0 -- F 0.01 -- -- F 0.01 -- -- F 1.0 2.2 -- F

1. See Figure 14 for capacitor integration. 2. Recommended X7R or X5R ceramic low ESR capacitors, �15% variation over process, voltage, temperature, and aging. 3. Each VDD pin requires both a 47 nF and a 0.01 F capacitor for high-frequency bypass and EMC requirements. 4. Recommended X7R or X5R ceramic low ESR capacitors, �15% variation over process, voltage, temperature, and aging. 5. Each VDDPMC pin requires both a 47 nF and a 0.01 F capacitor for high-frequency bypass and EMC requirements. 6. The actual capacitance should be selected based on the I/O usage in order to keep the supply voltage within its operating
range. 7. The recommended flash regulator composition capacitor is 2.0 F typical X7R or X5R, with -50% and +35% as min and
max. This puts the min cap at 0.75 F. 8. For noise filtering it is recommended to add a high frequency bypass capacitance of 0.1 F between VDDA_EQA/B and
VSSA_EQ. 9. For noise filtering it is recommended to add a high frequency bypass capacitance of 0.1 F between REFBYPCA/B and VSS. 10. For noise filtering it is recommended to add a high frequency bypass capacitance of 0.1 F between VDDA_SD and
VSSA_SD.

3.11.3 Device voltage monitoring
The LVD/HVDs for the device and their levels are given in the following table. Voltage monitoring threshold definition is provided in the following figure.

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

V DD_xxx V HVD(rise) V HVD(fall) V LVD(rise) V LVD(fall)
HVD TRIGGER
(INTERNAL)

Electrical characteristics

t VDASSERT

t VDRELEASE

LVD TRIGGER
(INTERNAL)

t VDRELEASE

t VDASSERT

Figure 15. Voltage monitor threshold definition

Table 29. Voltage monitor electrical characteristics1, 2

Symbol

Parameter

POR098_c3 LV internal supply power on reset

LVD_core_hot LV internal4 supply low voltage monitoring

LVD_core_cold LV external5 supply low voltage monitoring
HVD_core LV internal cold supply high voltage monitoring

Conditions
Rising voltage (powerup) Falling voltage (power down) Rising voltage (untrimmed) Falling voltage (untrimmed) Rising voltage (trimmed) Falling voltage (trimmed) Rising voltage Falling voltage Rising voltage Falling voltage

Configuration

Value

Trim Mask Pow. bits Opt. Up

Min

Typ

Unit Max

N/A No Enab. 960 1010 1060 mV

940 990 1040

4bit No Enab. 1100 1140 1183 mV 1080 1120 1163 1142 1165 1183 1122 1145 1163
4bit Yes Disab. 1165 1180 1198 mV 1136 1160 1178
4bit Yes Disab. 1338 1365 1385 mV 1318 1345 1365

Table continues on the next page...

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Electrical characteristics
Table 29. Voltage monitor electrical characteristics1, 2 (continued)

Symbol

Parameter

Conditions

Configuration

Value

Trim Mask Pow. bits Opt. Up

Min

Typ

Unit Max

POR_HV

HV VDDPMC supply power on reset threshold

Rising voltage (powerup)
Falling voltage (power down)

N/A No Enab. 2444 2600 2756 mV 2424 2580 2736

LVD_HV

HV internal VDDPMC supply Rising voltage (untrimmed) 4bit

low voltage monitoring

Falling voltage (untrimmed)

No Enab. 2935 3023 3112 mV 2922 3010 3099

Rising voltage (trimmed)

2946 3010 3066

Falling voltage (trimmed)

2934 2998 3044

HVD_HV

HV internal VDDPMC supply Rising voltage high voltage monitoring Falling voltage

4bit Yes Disab. 5696 5860 5968 mV 5666 5830 5938

LVD_FLASH FLASH supply low voltage Rising voltage (untrimmed) 4bit

monitoring6

Falling voltage (untrimmed)

No Enab. 2935 3023 3112 mV 2922 3010 3099

Rising voltage (trimmed)

2956 3010 3053

Falling voltage (trimmed)

2944 2998 3041

HVD_FLASH FLASH supply high voltage monitoring6

Rising voltage Falling voltage

4bit Yes Disab. 3456 3530 3584 mV 3426 3500 3554

LVD_IO

Main I/O VDDEH1 supply low voltage monitoring

Rising voltage (untrimmed) 4bit Falling voltage (untrimmed)

No Enab. 3250 3350 3488 mV 3220 3320 3458

Rising voltage (trimmed)

3347 3420 3468

Falling voltage (trimmed)

3317 3390 3438

tVDASSERT

Voltage detector threshold -- crossing assertion

-- -- -- 0.1 -- 2.0 s

tVDRELEASE

Voltage detector threshold -- crossing de-assertion

------

-- 20 s

1. LVD is released after tVDRELEASE temporization when upper threshold is crossed; LVD is asserted tVDASSERT after detection when lower threshold is crossed.
2. HVD is released after tVDRELEASE temporization when lower threshold is crossed; HVD is asserted tVDASSERT after detection when upper threshold is crossed.
3. POR098_c threshold is an untrimmed value, before the completion of the power-up sequence. All other LVD/HVD thresholds are provided after trimming.
4. LV internal supply levels are measured on device internal supply grid after internal voltage drop. 5. LV external supply levels are measured on the die side of the package bond wire after package voltage drop. 6. VDDFLA range is guaranteed when internal flash memory regulator is used.

3.11.4 Power sequencing requirements Requirements for power sequencing include the following.

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Electrical characteristics
NOTE In these descriptions, star route layout means a track split as close as possible to the power supply source. Each of the split tracks is routed individually to the intended end connection.
1. For both LDO mode and SMPS mode, VDDPMC and VDDPWR must be connected together (shorted) to ensure aligned voltage ramping up/down. In addition:
� For SMPS mode, a star route layout of the power track is required to minimize mutual noise. If SMPS mode is not used, the star route layout is not required. VDDPWR is the supply pin for the SMPS circuitry.
� For 3.3 V operation, VDDFLA must also be star routed and shorted to VDDPWR and VDDPMC. This triple connection is required because 3.3 V does not guarantee correct functionality of the internal VDDFLA regulator. Consequently, VDDFLA is supplied externally.
2. VDDA_MISC: IRC operation is required to provide the clock for chip startup.
� The VDDPMC, VDD, and VDDEH1 (reset pin pad segment) supplies are monitored. They hold IRC until all of them reach operational voltage. In other words, VDDA_MISC must reach its specified minimum operating voltage before or at the same time that all of these monitored voltages reach their respective specified minimum voltages.
� An alternative is to connect the same supply voltage to both VDDEH1 and VDDA_MISC. This alternative approach requires a star route layout to minimize mutual noise.
3. Multiple VDDEx supplies can be powered up in any order.
During any time when VDD is powered up but VDDEx is not yet powered up: pad outputs are unpowered.
During any time when VDDEx is powered up before all other supplies: all pad output buffers are tristated.
4. Ramp up VDDA_EQ before VDD. Otherwise, a reset might occur.
5. When the device is powering down while using the internal SMPS regulator, VDDPMC and VDDPWR supplies must ramp down through the voltage range from 2.5 V to 1.5 V in less than 1 second. Slower ramp-down times might result in reduced lifetime reliability of the device.

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Electrical characteristics
3.12 Flash memory specifications

3.12.1 Flash memory program and erase specifications

NOTE All timing, voltage, and current numbers specified in this section are defined for a single embedded flash memory within an SoC, and represent average currents for given supplies and operations.

Table 30 shows the estimated Program/Erase times.

Table 30. Flash memory program and erase specifications

Symbol
tdwpgm tppgm tqppgm t16kers t16kpgm t32kers t32kpgm t64kers t64kpgm t256kers t256kpgm

Characteristic1

Typ2

Doubleword (64 bits) program time 43

Page (256 bits) program time

Quad-page (1024 bits) program 268 time

16 KB Block erase time

168

16 KB Block program time

32 KB Block erase time

217

32 KB Block program time

64 KB Block erase time

315

64 KB Block program time

138

256 KB Block erase time

884

256 KB Block program time

552

Factory Programming3, 4

Field Update

Unit

Initial Max

Initial Max, Full
Temp

Typical End of Life5

Lifetime Max6

20�C TA -40�C TJ -40�C TJ 1,000 250,000

30�C

150�C 150�C cycles cycles

100

150

500

200

300

108

500

800

1,200

396

2,000

290

320

250

1,000

360

390

310

1,200

100

110

1,200

490

590

420

1,600

180

210

170

1,600

1,520

2,030

1,080

4,000 --

720

880

650

4,000 --

1. Program times are actual hardware programming times and do not include software overhead. Block program times assume quad-page programming.
2. Typical program and erase times represent the median performance and assume nominal supply values and operation at 25 �C. Typical program and erase times may be used for throughput calculations.
3. Conditions: 150 cycles, nominal voltage. 4. Plant Programing times provide guidance for timeout limits used in the factory. 5. Typical End of Life program and erase times represent the median performance and assume nominal supply values.
Typical End of Life program and erase values may be used for throughput calculations. 6. Conditions: -40�C TJ 150�C, full spec voltage.

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Electrical characteristics
3.12.2 Flash memory Array Integrity and Margin Read specifications
Table 31. Flash memory Array Integrity and Margin Read specifications

Symbol Characteristic

Min

Typical Max1 Units

tai16kseq

Array Integrity time for sequential sequence on 16 KB block.

tai32kseq

Array Integrity time for sequential sequence on 32 KB block.

tai64kseq

Array Integrity time for sequential sequence on 64 KB block.

tai256kseq Array Integrity time for sequential sequence on 256 KB block.

tmr16kseq tmr32kseq tmr64kseq tmr256kseq

Margin Read time for sequential sequence on 16 KB block. Margin Read time for sequential sequence on 32 KB block. Margin Read time for sequential sequence on 64 KB block. Margin Read time for sequential sequence on 256 KB block.

--
--
--
--
73.81 128.43 237.65 893.01

512 x

Tperiod x

Nread

1024 x --

Tperiod x

Nread

2048 x --

Tperiod x

Nread

8192 x --

Tperiod x

Nread

110.7

192.6

356.5

1,339.5 s

1. Array Integrity times need to be calculated and is dependent on system frequency and number of clocks per read. The equation presented require Tperiod (which is the unit accurate period, thus for 200 MHz, Tperiod would equal 5e-9) and Nread (which is the number of clocks required for read, including pipeline contribution. Thus for a read setup that requires 6 clocks to read with no pipeline, Nread would equal 6. For a read setup that requires 6 clocks to read, and has the address pipeline set to 2, Nread would equal 4 (or 6 - 2).)
2. The units for Array Integrity are determined by the period of the system clock. If unit accurate period is used in the equation, the results of the equation are also unit accurate.

3.12.3 Flash memory module life specifications
Table 32. Flash memory module life specifications

Symbol Array P/E cycles
Data retention

Characteristic Number of program/erase cycles per block for 16 KB, 32 KB and 64 KB blocks.1 Number of program/erase cycles per block for 256 KB blocks.2 Minimum data retention.

Conditions --

Min 250,000

1,000

Blocks with 0 - 1,000 P/E 50 cycles.
Blocks with 100,000 P/E 20 cycles.
Blocks with 250,000 P/E 10 cycles.

Typical -- 250,000 -- -- --

Units P/E cycles P/E cycles Years
Years
Years

1. Program and erase supported across standard temperature specs. 2. Program and erase supported across standard temperature specs.

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Electrical characteristics
3.12.4 Data retention vs program/erase cycles Graphically, Data Retention versus Program/Erase Cycles can be represented by the following figure. The spec window represents qualified limits. The extrapolated dotted line demonstrates technology capability, however is beyond the qualification limits.

3.12.5 Flash memory AC timing specifications
Table 33. Flash memory AC timing specifications

Symbol Characteristic

Min

Typical

tpsus

Time from setting the MCR-PSUS bit until MCR-DONE bit is set

9.4

to a 1.

plus four

system

clock

periods

tesus

Time from setting the MCR-ESUS bit until MCR-DONE bit is set

to a 1.

plus four

system

clock

periods

tres

Time from clearing the MCR-ESUS or PSUS bit with EHV = 1

until DONE goes low.

Table continues on the next page...

Max
11.5
plus four system clock periods
20.8
plus four system clock periods
100

Units s
s
ns

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Symbol tdone tdones
tdrcv
taistart taistop
tmrstop

Electrical characteristics
Table 33. Flash memory AC timing specifications (continued)

Characteristic

Min

Time from 0 to 1 transition on the MCR-EHV bit initiating a

program/erase until the MCR-DONE bit is cleared.

Time from 1 to 0 transition on the MCR-EHV bit aborting a

program/erase until the MCR-DONE bit is set to a 1.

Time to recover once exiting low power mode.

plus seven system clock periods.

Time from 0 to 1 transition of UT0-AIE initiating a Margin Read

or Array Integrity until the UT0-AID bit is cleared. This time also

applies to the resuming from a suspend or breakpoint by

clearing AISUS or clearing NAIBP

Time from 1 to 0 transition of UT0-AIE initiating an Array

Integrity abort until the UT0-AID bit is set. This time also applies

to the UT0-AISUS to UT0-AID setting in the event of a Array

Integrity suspend request.

Time from 1 to 0 transition of UT0-AIE initiating a Margin Read abort until the UT0-AID bit is set. This time also applies to the UT0-AISUS to UT0-AID setting in the event of a Margin Read suspend request.

10.36
plus four system clock periods

Typical -- 16
plus four system clock periods
--
--
--
--

Max 5
20.8 plus four system
clock periods
45 plus seven
system clock periods
5
80 plus fifteen
system clock periods 20.42 plus four system clock periods

Units ns s
s
ns ns
s

3.12.6 Flash memory read wait-state and address-pipeline control settings

The following table describes the recommended settings of the Flash Memory Controller's PFCR1[RWSC] and PFCR1[APC] fields at various flash memory operating frequencies, based on specified intrinsic flash memory access times of the C55FMC array at 150�C.

Table 34. Flash memory read wait-state and address-pipeline control combinations

Flash memory frequency RWSC

0 MHz < fPLATF 33 MHz

33 MHz < fPLATF 100 MHz

APC
0 1

Flash memory read latency on mini-cache miss (# of fPLATF clock periods)
3
5

Table continues on the next page...

Flash memory read latency on mini-cache hit (# of fPLATF clock
periods)
1
1

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Electrical characteristics
Table 34. Flash memory read wait-state and address-pipeline control combinations (continued)

Flash memory frequency RWSC APC

100 MHz < fPLATF 150 MHz

Flash memory read latency on mini-cache miss (# of fPLATF clock periods)
6

Flash memory read latency on mini-cache hit (# of fPLATF clock
periods)
1

3.13 AC timing
3.13.1 Generic timing diagrams The generic timing diagrams in Figure 16 and Figure 17 apply to all I/O pins with pad types SR and FC. See the associated MPC5777C Microsoft Excel� file in the Reference Manual for the pad type for each pin.

D_CLKOUT
A B
I/O Outputs

VDDE / 2 VDDEn / 2 VDDEHn / 2

A � Maximum Output Delay Time

B � Minimum Output Hold Time

Figure 16. Generic output delay/hold timing

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Electrical characteristics

D_CLKOUT

VDDE / 2
B A

I/O Inputs

VDDEn / 2 VDDEHn / 2

A � Maximum Input Delay Time

B � Minimum Input Hold Time

Figure 17. Generic input setup/hold timing

3.13.2 Reset and configuration pin timing
Table 35. Reset and configuration pin timing1

Spec Characteristic

Symbol

Min

1 RESET Pulse Width

tRPW

2 RESET Glitch Detect Pulse Width

tGPW

3 PLLCFG, BOOTCFG, WKPCFG Setup Time to RSTOUT Valid

tRCSU

4 PLLCFG, BOOTCFG, WKPCFG Hold Time to RSTOUT Valid

tRCH

1. Reset timing specified at: VDDEH = 3.0 V to 5.25 V, VDD = 1.08 V to 1.32 V, TA = TL to TH. 2. For further information on tcyc, see Table 3.

Max -- -- -- --

Unit
tcyc2 tcyc2 tcyc2 tcyc2

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Electrical characteristics 2

RESET

RSTOUT
PLLCFG BOOTCFG WKPCFG

3
4
Figure 18. Reset and configuration pin timing

3.13.3 IEEE 1149.1 interface timing
Table 36. JTAG pin AC electrical characteristics1

Symbol

Characteristic

tJCYC

TCK cycle time

tJDC

TCK clock pulse width

tTCKRISE

TCK rise and fall times (40%�70%)

tTMSS, tTDIS TMS, TDI data setup time

tTMSH, tTDIH TMS, TDI data hold time

tTDOV

TCK low to TDO data valid

tTDOI

TCK low to TDO data invalid

tTDOHZ

TCK low to TDO high impedance

tJCMPPW

JCOMP assertion time

tJCMPS

JCOMP setup time to TCK low

tBSDV

TCK falling edge to output valid

tBSDVZ

TCK falling edge to output valid out of high impedance

tBSDHZ

TCK falling edge to output high impedance

tBSDST

Boundary scan input valid to TCK rising edge

tBSDHT

TCK rising edge to boundary scan input invalid

Value

Unit

Min

Max

100

162

100

6003

600

1. These specifications apply to JTAG boundary scan only. See Table 37 for functional specifications. 2. Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay. 3. Applies to all pins, limited by pad slew rate. Refer to I/O delay and transition specification and add 20 ns for JTAG delay.

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

TCK 3

Electrical characteristics

2 2

Figure 19. JTAG test clock input timing

TCK TMS, TDI

4 5

7 TDO

6 8

Figure 20. JTAG test access port timing

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Electrical characteristics
TCK 10
JCOMP
9
Figure 21. JTAG JCOMP timing

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Electrical characteristics

TCK

Output Signals
12

Output Signals

14 15

Input Signals

Figure 22. JTAG boundary scan timing

3.13.4 Nexus timing
Table 37. Nexus debug port timing1

Spec Characteristic 1 MCKO Cycle Time 2 MCKO Duty Cycle 3 MCKO Low to MDO Data Valid2 4 MCKO Low to MSEO Data Valid2 5 MCKO Low to EVTO Data Valid2 6 EVTI Pulse Width 7 EVTO Pulse Width 8 TCK Cycle Time

Symbol
tMCYC tMDC tMDOV tMSEOV tEVTOV tEVTIPW tEVTOPW tTCYC
Table continues on the next page...

Min 2 40 �0.1 �0.1 �0.1 4.0 1 23

Max 8 60 0.2 0.2 0.2 -- -- --

Unit
tCYC % tMCYC tMCYC tMCYC tTCYC tMCYC tCYC

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Electrical characteristics
Table 37. Nexus debug port timing1 (continued)

Spec Characteristic

Symbol

Min

8 Absolute minimum TCK cycle time4 (TDO sampled on

tTCYC

405

posedge of TCK)

Absolute minimum TCK cycle time4 (TDO sampled on

205

negedge of TCK)

9 TCK Duty Cycle 10 TDI, TMS Data Setup Time6 11 TDI, TMS Data Hold Time6 12 TCK Low to TDO Data Valid6 13 RDY Valid to MCKO7

tTDC

tNTDIS, tNTMSS

TNTDIH, tNTMSH

tNTDOV

14 TDO hold time after TCLK low6

tNTDOH

Max --
--
60 -- -- 18 -- --

Unit ns
% ns ns ns -- ns

1. All Nexus timing relative to MCKO is measured from 50% of MCKO and 50% of the respective signal. Nexus timing specified at VDD = 1.08 V to 1.32 V, VDDE = 3.0 V to 3.6 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA = TL to TH, and CL = 30 pF with DSC = 0b10.
2. MDO, MSEO, and EVTO data is held valid until next MCKO low cycle. 3. This is a functionally allowable feature. However, it may be limited by the maximum frequency specified by the absolute
minimum TCK period specification. 4. This value is TDO propagation time plus 2 ns setup time to sampling edge. 5. This may require a maximum clock speed that is less than the maximum functional capability of the design depending on
the actual system frequency being used. 6. Applies to TMS pin timing for the bit frame when using the 1149.7 advanced protocol. 7. The RDY pin timing is asynchronous to MCKO. The timing is guaranteed by design to function correctly.

MCKO
MDO MSEO EVTO
EVTI

2
3 4 5
Output Data Valid
7 6

Figure 23. Nexus timings

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

TCK

Electrical characteristics 8
9

TMS, TDI

10 11

TDO

Figure 24. Nexus TCK, TDI, TMS, TDO Timing

3.13.5 External Bus Interface (EBI) timing
Table 38. Bus operation timing1

Spec

Characteristic

1 D_CLKOUT Period

2 D_CLKOUT Duty Cycle 3 D_CLKOUT Rise Time 4 D_CLKOUT Fall Time

Symbol tC

66 MHz (Ext. bus freq.)2, 3

Min

Max

15.2

tCDC tCRT tCFT

45% -- --

55% --4 --4

Table continues on the next page...

Unit Notes
ns Signals are measured at 50% VDDE.
tC -- ns -- ns --

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Electrical characteristics
Table 38. Bus operation timing1 (continued)

Spec

Characteristic

Symbol

5 D_CLKOUT Posedge to Output tCOH Signal Invalid or High Z (Hold Time)

D_ADD[9:30]

D_BDIP

D_CS[0:3]

D_DAT[0:15]

D_OE

D_RD_WR

D_TA

D_TS

D_WE[0:3]/D_BE[0:3]

6 D_CLKOUT Posedge to Output tCOV Signal Valid (Output Delay)

D_ADD[9:30]

D_BDIP

D_CS[0:3]

D_DAT[0:15]

D_OE

D_RD_WR

D_TA

D_TS

D_WE[0:3]/D_BE[0:3]

7 Input Signal Valid to D_CLKOUT tCIS Posedge (Setup Time)

D_ADD[9:30]

D_DAT[0:15]

D_RD_WR

D_TA

D_TS

8 D_CLKOUT Posedge to Input

tCIH

Signal Invalid (Hold Time)

D_ADD[9:30]

D_DAT[0:15]

D_RD_WR

D_TA

D_TS

9 D_ALE Pulse Width

tAPW

66 MHz (Ext. bus freq.)2, 3

Min

Max

1.0/1.5

8.5/9.0

11.5 8.5/9.0

7.5

1.0

6.5

Unit Notes ns Hold time selectable via
SIU_ECCR[EBTS] bit: EBTS = 0: 1.0 ns EBTS = 1: 1.5 ns
ns Output valid time selectable via SIU_ECCR[EBTS] bit: EBTS = 0: 8.5 ns EBTS = 1: 9.0 ns -- Output valid time selectable via SIU_ECCR[EBTS] bit: EBTS = 0: 8.5 ns EBTS = 1: 9.0 ns
ns --
ns --
ns The timing is for Asynchronous external memory system.

Table continues on the next page...

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Table 38. Bus operation timing1 (continued)

Electrical characteristics

Spec

Characteristic

10 D_ALE Negated to Address Invalid

Symbol tAAI

66 MHz (Ext. bus freq.)2, 3

Min

Max

2.0/1.0 5

Unit Notes
ns The timing is for Asynchronous external memory system. ALE is measured at 50% of VDDE.

1. EBI timing specified at VDD = 1.08 V to 1.32 V, VDDE = 3.0 V to 3.6 V, TA = TL to TH, and CL = 30 pF with SIU_PCR[DSC] = 11b for ADDR/CTRL and SIU_PCR[SRC] = 11b for DATA/ALE.
2. Speed is the nominal maximum frequency. Max speed is the maximum speed allowed including frequency modulation (FM).
3. Depending on the internal bus speed, set the SIU_ECCR[EBDF] bits correctly not to exceed maximum external bus frequency. The maximum external bus frequency is 66 MHz.
4. Refer to D_CLKOUT pad timing in Table 10. 5. ALE hold time spec is temperature dependant. 1.0 ns spec applies for temperature range -40 to 0�C. 2.0ns spec applies to
temperatures > 0�C. This spec has no dependency on the SIU_ECCR[EBTS] bit.

VOH_F

D_CLKOUT

VOL_F

3 4

2 2
1

Figure 25. D_CLKOUT timing

VDDE / 2

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Electrical characteristics

D_CLKOUT

6 5

Output Bus

VDDE / 2

Output Signal

5 VDDE / 2

VDDE / 2 5
5

Output Signal

6
Figure 26. Synchronous output timing

VDDE / 2

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

D_CLKOUT
Input Bus

VDDE / 2 7
VDDE / 2

Electrical characteristics 8

7 8

Input Signal

VDDE / 2

ipg_clk D_CLKOUT
D_ALE D_TS
D_ADD/D_DAT

Figure 27. Synchronous input timing

ADDR 9

DATA 10

Figure 28. ALE signal timing

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Electrical characteristics
3.13.6 External interrupt timing (IRQ/NMI pin)
Table 39. External Interrupt timing1

Spec Characteristic 1 IRQ/NMI Pulse Width Low 2 IRQ/NMI Pulse Width High 3 IRQ/NMI Edge to Edge Time3

Symbol

Min

tIPWL

tIPWH

tICYC

Max -- -- --

Unit
tcyc2 tcyc2 tcyc2

1. IRQ/NMI timing specified at VDD = 1.08 V to 1.32 V, VDDEH = 3.0 V to 5.5 V, TA = TL to TH. 2. For further information on tcyc, see Table 3. 3. Applies when IRQ/NMI pins are configured for rising edge or falling edge events, but not both.

IRQ

3
Figure 29. External interrupt timing

3.13.7 eTPU timing
Table 40. eTPU timing1
Spec Characteristic 1 eTPU Input Channel Pulse Width 2 eTPU Output Channel Pulse Width

Symbol

Min

tICPW

tOCPW

Max -- --

Unit tCYC_ETPU2 tCYC_ETPU2

1. eTPU timing specified at VDD = 1.08 V to 1.32 V, VDDEH = 3.0 V to 5.5 V, TA = TL to TH, and CL = 200 pF with SRC = 0b00. 2. For further information on tCYC_ETPU, see Table 3. 3. This specification does not include the rise and fall times. When calculating the minimum eTPU pulse width, include the
rise and fall times defined in the slew rate control fields (SRC) of the pad configuration registers (PCR).

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

eTPU Input and TCRCLK

Electrical characteristics

eTPU Output

1 2
Figure 30. eTPU timing

3.13.8 eMIOS timing
Table 41. eMIOS timing1

Spec 1 2

Characteristic eMIOS Input Pulse Width eMIOS Output Pulse Width

Symbol

Min

tMIPW

tMOPW

Max -- --

Unit tCYC_PER2 tCYC_PER2

1. eMIOS timing specified at VDD = 1.08 V to 1.32 V, VDDEH = 3.0 V to 5.5 V, TA = TL to TH, and CL = 50 pF with SRC = 0b00. 2. For further information on tCYC_PER, see Table 3. 3. This specification does not include the rise and fall times. When calculating the minimum eMIOS pulse width, include the
rise and fall times defined in the slew rate control fields (SRC) of the pad configuration registers (PCR).

eMIOS Input

eMIOS Output

1 2
Figure 31. eMIOS timing

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Electrical characteristics

3.13.9 DSPI timing with CMOS and LVDS pads

NOTE The DSPI in TSB mode with LVDS pads can be used to implement the Micro Second Channel (MSC) bus protocol.

DSPI channel frequency support is shown in Table 42. Timing specifications are shown in Table 43, Table 44, Table 45, Table 46, and Table 47.

Table 42. DSPI channel frequency support

CMOS (Master mode) LVDS (Master mode)

DSPI use mode Full duplex � Classic timing (Table 43) Full duplex � Modified timing (Table 44) Output only mode (SCK/SOUT/PCS) (Table 43 and Table 44) Output only mode TSB mode (SCK/SOUT/PCS) (Table 47) Full duplex � Modified timing (Table 45) Output only mode TSB mode (SCK/SOUT/PCS) (Table 46)

Max usable frequency (MHz)1, 2 17 30 30 30 30 40

1. Maximum usable frequency can be achieved if used with fastest configuration of the highest drive pads. 2. Maximum usable frequency does not take into account external device propagation delay.

3.13.9.1 DSPI master mode full duplex timing with CMOS and LVDS pads

3.13.9.1.1 DSPI CMOS Master Mode -- Classic Timing Table 43. DSPI CMOS master classic timing (full duplex and output only) � MTFE = 0, CPHA = 0 or 11

# Symbol Characteristic

Condition2

Pad drive4

Load (CL)

Value3

Unit

Min

Max

tSCK SCK cycle time

PCR[SRC]=11b

25 pF

33.0

PCR[SRC]=10b

50 pF

80.0

PCR[SRC]=01b

50 pF

200.0

tCSC PCS to SCK delay

PCR[SRC]=11b PCR[SRC]=10b

PCR[SRC]=01b

PCS: PCR[SRC]=01b

25 pF 50 pF 50 pF 50 pF

(N5 � tSYS, 6) � 16 (N5 � tSYS, 6) � 16 (N5 � tSYS, 6) � 18 (N5 � tSYS, 6) � 45

SCK: PCR[SRC]=10b

Table continues on the next page...

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Electrical characteristics
Table 43. DSPI CMOS master classic timing (full duplex and output only) � MTFE = 0, CPHA = 0 or 11 (continued)

# Symbol Characteristic

tASC After SCK delay

Condition2

Pad drive4

Load (CL)

PCR[SRC]=11b

PCS: 0 pF

Value3 Min (M7 � tSYS, 6) � 35

Max --

Unit ns

SCK: 50 pF

PCR[SRC]=10b

PCS: 0 pF

(M7 � tSYS, 6) � 35

SCK: 50 pF

PCR[SRC]=01b

PCS: 0 pF

(M7 � tSYS, 6) � 35

SCK: 50 pF

PCS: PCR[SRC]=01b PCS: 0 pF (M7 � tSYS, 6) � 35

SCK: PCR[SRC]=10b SCK: 50 pF

tSDC SCK duty cycle8

PCR[SRC]=11b

0 pF

PCR[SRC]=10b

0 pF

PCR[SRC]=01b

0 pF

PCS strobe timing

1/2tSCK � 2 1/2tSCK � 2 1/2tSCK � 5

1/2tSCK + 2

1/2tSCK + 5

5 tPCSC PCSx to PCSS time9

PCR[SRC]=10b

25 pF

13.0

tPASC PCSS to PCSx

time9

PCR[SRC]=10b

25 pF

13.0

SIN setup time

tSUI

SIN setup time to

PCR[SRC]=11b

25 pF

29.0

SCK10

PCR[SRC]=10b

50 pF

31.0

PCR[SRC]=01b

50 pF

62.0

SIN hold time

tHI

SIN hold time from

PCR[SRC]=11b

0 pF

�1.0

SCK10

PCR[SRC]=10b

0 pF

�1.0

PCR[SRC]=01b

0 pF

�1.0

SOUT data valid time (after SCK edge)

tSUO SOUT data valid

PCR[SRC]=11b

25 pF

time from SCK11

PCR[SRC]=10b

50 pF

7.0

8.0

PCR[SRC]=01b

50 pF

18.0

SOUT data hold time (after SCK edge)

tHO

SOUT data hold

time after SCK11

PCR[SRC]=11b PCR[SRC]=10b

25 pF 50 pF

�9.0 �10.0

PCR[SRC]=01b

50 pF

�21.0

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Electrical characteristics
SCK clock mode is selected, in which case, N is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge of DSPI_CLKn). 6. tSYS is the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 100 MHz (min tSYS = 10 ns). 7. M is the number of clock cycles added to time between SCK negation and PCS negation and is software programmable using DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. The minimum value is 2 cycles unless TSB mode or Continuous SCK clock mode is selected, in which case, M is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge of DSPI_CLKn). 8. tSDC is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time. 9. PCSx and PCSS using same pad configuration. 10. Input timing assumes an input slew rate of 1 ns (10% � 90%) and uses TTL / Automotive voltage thresholds. 11. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same value.

t CSC

PCSx
SCK Output (CPOL = 0)
SCK Output (CPOL = 1)

t SDC t SDC t SUI t HI

SIN SOUT

First Data First Data

Data t SUO
Data

t ASC t SCK
Last Data t HO
Last Data

Figure 32. DSPI CMOS master mode � classic timing, CPHA = 0

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Electrical characteristics

PCSx

SCK Output (CPOL = 0)

SCK Output (CPOL = 1)
SIN
SOUT

t SUI t HI First Data
First Data

Data t SUO
Data

Last Data
t HO Last Data

Figure 33. DSPI CMOS master mode � classic timing, CPHA = 1

PCSS

tPCSC

PCSx

tPASC

Figure 34. DSPI PCS strobe (PCSS) timing (master mode)

3.13.9.1.2 DSPI CMOS Master Mode � Modified Timing Table 44. DSPI CMOS master modified timing (full duplex and output only) � MTFE = 1, CPHA = 0 or 11

# Symbol Characteristic

Condition2

Pad drive4

Load (CL)

Value3

Unit

Min

Max

tSCK SCK cycle time

PCR[SRC]=11b

25 pF

33.0

PCR[SRC]=10b

50 pF

80.0

PCR[SRC]=01b

50 pF

200.0

tCSC PCS to SCK delay

PCR[SRC]=11b PCR[SRC]=10b

PCR[SRC]=01b

PCS: PCR[SRC]=01b

25 pF 50 pF 50 pF 50 pF

(N5 � tSYS, 6) � 16 (N5 � tSYS, 6) � 16 (N5 � tSYS, 6) � 18 (N5 � tSYS, 6) � 45

SCK: PCR[SRC]=10b

Table continues on the next page...

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Electrical characteristics

Table 44. DSPI CMOS master modified timing (full duplex and output only) � MTFE = 1, CPHA = 0 or 11 (continued)

# Symbol Characteristic

tASC After SCK delay

tSDC SCK duty cycle8

5 tPCSC PCSx to PCSS time9

tPASC PCSS to PCSx

time9

tSUI

SIN setup time to

SCK

CPHA = 010

SIN setup time to SCK
CPHA = 110

tHI12 SIN hold time from

SCK

CPHA = 010

SIN hold time from SCK
CPHA = 110

tSUO SOUT data valid

time from SCK

CPHA = 013

SOUT data valid time from SCK
CPHA = 113

Condition2

Pad drive4 PCR[SRC]=11b

Load (CL) PCS: 0 pF

SCK: 50 pF

PCR[SRC]=10b

PCS: 0 pF

SCK: 50 pF

PCR[SRC]=01b

PCS: 0 pF

SCK: 50 pF

PCS: PCR[SRC]=01b PCS: 0 pF

SCK: PCR[SRC]=10b SCK: 50 pF

PCR[SRC]=11b

0 pF

PCR[SRC]=10b

0 pF

PCR[SRC]=01b

0 pF

PCS strobe timing

PCR[SRC]=10b

25 pF

Value3 Min (M7 � tSYS, 6) � 35

Max --

(M7 � tSYS, 6) � 35

1/2tSCK � 2 1/2tSCK � 2 1/2tSCK � 5

1/2tSCK + 2 1/2tSCK + 2 1/2tSCK + 5

13.0

Unit ns
ns ns

PCR[SRC]=10b

25 pF

13.0

SIN setup time

PCR[SRC]=11b

25 pF

29 � (P11 � tSYS, 6)

PCR[SRC]=10b

50 pF

31 � (P11 � tSYS, 6)

PCR[SRC]=01b

50 pF

62 � (P11 � tSYS, 6)

PCR[SRC]=11b

25 pF

29.0

PCR[SRC]=10b

50 pF

31.0

PCR[SRC]=01b

50 pF

62.0

SIN hold time

PCR[SRC]=11b PCR[SRC]=10b PCR[SRC]=01b PCR[SRC]=11b

0 pF

�1 + (P11 � tSYS, 6)

0 pF

�1 + (P11 � tSYS, 6)

0 pF

�1 + (P11 � tSYS, 6)

0 pF

�1.0

PCR[SRC]=10b

0 pF

�1.0

PCR[SRC]=01b

0 pF

�1.0

SOUT data valid time (after SCK edge)

PCR[SRC]=11b PCR[SRC]=10b PCR[SRC]=01b PCR[SRC]=11b

25 pF 50 pF 50 pF 25 pF

7.0 + tSYS6

8.0 + tSYS6

18.0 + tSYS6

7.0

PCR[SRC]=10b

50 pF

8.0

PCR[SRC]=01b

50 pF

18.0

SOUT data hold time (after SCK edge)

Table continues on the next page...

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Electrical characteristics
Table 44. DSPI CMOS master modified timing (full duplex and output only) � MTFE = 1, CPHA = 0 or 11 (continued)

# Symbol Characteristic

tHO

SOUT data hold

time after SCK

CPHA = 013

SOUT data hold time after SCK
CPHA = 113

Condition2

Pad drive4

Load (CL)

Value3

Unit

Min

Max

PCR[SRC]=11b

25 pF

�9.0 + tSYS6

PCR[SRC]=10b

50 pF

�10.0 + tSYS6

PCR[SRC]=01b

50 pF

�21.0 + tSYS6

PCR[SRC]=11b

25 pF

�9.0

PCR[SRC]=10b

50 pF

�10.0

PCR[SRC]=01b

50 pF

�21.0

1. All output timing is worst case and includes the mismatching of rise and fall times of the output pads. 2. When a characteristic involves two signals, the pad drive and load conditions apply to each signal's pad, unless specified
otherwise. 3. All timing values for output signals in this table are measured to 50% of the output voltage. 4. Pad drive is defined as the PCR[SRC] field setting in the SIU. Timing is guaranteed to same drive capabilities for all
signals; mixing of pad drives may reduce operating speeds and may cause incorrect operation. 5. N is the number of clock cycles added to time between PCS assertion and SCK assertion and is software programmable
using DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The minimum value is 2 cycles unless TSB mode or Continuous SCK clock mode is selected, in which case, N is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge of DSPI_CLKn). 6. tSYS is the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 100 MHz (min tSYS = 10 ns). 7. M is the number of clock cycles added to time between SCK negation and PCS negation and is software programmable using DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. The minimum value is 2 cycles unless TSB mode or Continuous SCK clock mode is selected, in which case, M is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge of DSPI_CLKn). 8. tSDC is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time. 9. PCSx and PCSS using same pad configuration. 10. Input timing assumes an input slew rate of 1 ns (10% � 90%) and uses TTL / Automotive voltage thresholds. 11. P is the number of clock cycles added to delay the DSPI input sample point and is software programmable using DSPI_MCR[SMPL_PT]. The value must be 0, 1 or 2. If the baud rate divide ratio is /2 or /3, this value is automatically set to 1. 12. The 0 pF load condition given in the DSPI AC timing applies to theoretical worst-case hold timing. This guarantees worstcase operation, and additional margin can be achieved in the applications by applying a realistic load. 13. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same value.

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Electrical characteristics

t CSC

PCSx
SCK Output (CPOL = 0)
SCK Output (CPOL = 1)

t SDC t SDC t SUI t HI

SIN SOUT

First Data First Data

Data t SUO
Data

t ASC t SCK
Last Data t HO
Last Data

Figure 35. DSPI CMOS master mode � modified timing, CPHA = 0

PCSx

SCK Output (CPOL = 0)

SCK Output (CPOL = 1)
SIN
SOUT

t SUI t HI First Data

Data

t HI Last Data

First Data

t SUO Data

t HO Last Data

Figure 36. DSPI CMOS master mode � modified timing, CPHA = 1

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

PCSS

tPCSC

PCSx

Electrical characteristics tPASC

Figure 37. DSPI PCS strobe (PCSS) timing (master mode)

3.13.9.1.3 DSPI LVDS Master Mode � Modified Timing Table 45. DSPI LVDS master timing � full duplex � modified transfer format (MTFE = 1), CPHA = 0 or 1

# Symbol Characteristic

Condition1

Pad drive3

Load (CL)

Value2

Unit

Min

Max

tSCK SCK cycle time

LVDS

15 pF to 25 pF

33.3

differential

tCSC PCS to SCK delay PCS: PCR[SRC]=11b

(LVDS SCK)

PCS: PCR[SRC]=10b

25 pF 50 pF

(N4 � tSYS, 5) � 10 (N4 � tSYS, 5) � 10

PCS: PCR[SRC]=01b

50 pF

(N4 � tSYS, 5) � 32

tASC After SCK delay

(LVDS SCK)

PCS: PCR[SRC]=11b

PCS: 0 pF SCK: 25 pF

(M6 � tSYS, 5) � 8

PCS: PCR[SRC]=10b PCS: 0 pF

(M6 � tSYS, 5) � 8

SCK: 25 pF

PCS: PCR[SRC]=01b PCS: 0 pF

(M6 � tSYS, 5) � 8

SCK: 25 pF

tSDC SCK duty cycle7

LVDS

15 pF to 25 pF differential

1/2tSCK � 2

1/2tSCK +2

tSUI

SIN setup time to SCK

LVDS

SIN setup time
15 pF to 25 pF differential

23 � (P9 � tSYS, 5)

CPHA = 08

SIN setup time to

LVDS

15 pF to 25 pF

SCK

differential

CPHA = 18

tHI

SIN hold time from SCK

LVDS

SIN hold time 0 pF differential

�1 + (P9 � tSYS, 5)

CPHA = 08

SIN hold time from

LVDS

0 pF differential

�1

SCK

CPHA = 18

Table continues on the next page...

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Electrical characteristics
Table 45. DSPI LVDS master timing � full duplex � modified transfer format (MTFE = 1), CPHA = 0 or 1 (continued)

# Symbol Characteristic

tSUO

SOUT data valid time from SCK

CPHA = 010

SOUT data valid time from SCK

CPHA = 110

tHO

SOUT data hold time after SCK

CPHA = 010

SOUT data hold time after SCK

CPHA = 110

Condition1

Pad drive3

Load (CL)

Value2

Unit

Min

Max

SOUT data valid time (after SCK edge)

LVDS

15 pF to 25 pF

differential

7.0 + tSYS5

LVDS

15 pF to 25 pF

differential

7.0

SOUT data hold time (after SCK edge)

LVDS

15 pF to 25 pF differential

�7.5 + tSYS5

LVDS

15 pF to 25 pF

�7.5

differential

1. When a characteristic involves two signals, the pad drive and load conditions apply to each signal's pad, unless specified otherwise.
2. All timing values for output signals in this table are measured to 50% of the output voltage. 3. Pad drive is defined as the PCR[SRC] field setting in the SIU. Timing is guaranteed to same drive capabilities for all
signals; mixing of pad drives may reduce operating speeds and may cause incorrect operation. 4. N is the number of clock cycles added to time between PCS assertion and SCK assertion and is software programmable
using DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The minimum value is 2 cycles unless TSB mode or Continuous SCK clock mode is selected, in which case, N is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge of DSPI_CLKn). 5. tSYS is the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 100 MHz (min tSYS = 10 ns). 6. M is the number of clock cycles added to time between SCK negation and PCS negation and is software programmable using DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. The minimum value is 2 cycles unless TSB mode or Continuous SCK clock mode is selected, in which case, M is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge of DSPI_CLKn). 7. tSDC is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time. 8. Input timing assumes an input slew rate of 1 ns (10% � 90%) and LVDS differential voltage = �100 mV. 9. P is the number of clock cycles added to delay the DSPI input sample point and is software programmable using DSPI_MCR[SMPL_PT]. The value must be 0, 1 or 2. If the baud rate divide ratio is /2 or /3, this value is automatically set to 1. 10. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same value.

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

t CSC

PCSx
SCK Output (CPOL = 0)
SCK Output (CPOL = 1)

t SDC t SDC t SUI t HI

SIN SOUT

First Data First Data

Data t SUO
Data

t ASC t SCK
Last Data t HO
Last Data

Electrical characteristics

Figure 38. DSPI LVDS master mode � modified timing, CPHA = 0

PCSx

SCK Output (CPOL = 0)

SCK Output (CPOL = 1)
SIN
SOUT

t SUI t HI First Data

Data

t HI Last Data

First Data

t SUO Data

t HO Last Data

Figure 39. DSPI LVDS master mode � modified timing, CPHA = 1

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Electrical characteristics
3.13.9.1.4 DSPI Master Mode � Output Only Table 46. DSPI LVDS master timing -- output only -- timed serial bus mode TSB = 1 or ITSB = 1, CPOL = 0 or 1, continuous SCK clock1, 2

# Symbol

Characteristic

Condition3

Pad drive5

Load (CL)

Value4

Unit

Min

Max

tSCK SCK cycle time

LVDS

15 pF to 50 pF

differential

tCSV PCS valid after SCK6

PCR[SRC]=11b

25 pF

(SCK with 50 pF differential load cap.)

PCR[SRC]=10b

50 pF

tCSH PCS hold after SCK6

(SCK with 50 pF

differential load cap.)

PCR[SRC]=11b PCR[SRC]=10b

0 pF 0 pF

�4.0 �4.0

tSDC SCK duty cycle (SCK

with 50 pF differential

load cap.)

LVDS

15 pF to 50 pF differential

1/2tSCK � 2

1/2tSCK + 2

SOUT data valid time (after SCK edge)

tSUO SOUT data valid time

from SCK7

LVDS

15 pF to 50 pF

differential

SOUT data hold time (after SCK edge)

tHO

SOUT data hold time

after SCK7

LVDS

15 pF to 50 pF

�7.0

differential

1. All DSPI timing specifications apply to pins when using LVDS pads for SCK and SOUT and CMOS pad for PCS with pad driver strength as defined. Timing may degrade for weaker output drivers.
2. TSB = 1 or ITSB = 1 automatically selects MTFE = 1 and CPHA = 1. 3. When a characteristic involves two signals, the pad drive and load conditions apply to each signal's pad, unless specified
otherwise. 4. All timing values for output signals in this table are measured to 50% of the output voltage. 5. Pad drive is defined as the PCR[SRC] field setting in the SIU. Timing is guaranteed to same drive capabilities for all
signals; mixing of pad drives may reduce operating speeds and may cause incorrect operation. 6. With TSB mode or Continuous SCK clock mode selected, PCS and SCK are driven by the same edge of DSPI_CLKn. This
timing value is due to pad delays and signal propagation delays. 7. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same
value.

Table 47. DSPI CMOS master timing � output only � timed serial bus mode TSB = 1 or ITSB = 1, CPOL = 0 or 1, continuous SCK clock 1, 2

# Symbol

Characteristic

tSCK SCK cycle time

tCSV PCS valid after SCK6

Condition3

Pad drive5 PCR[SRC]=11b

Load (CL) 25 pF

PCR[SRC]=10b

50 pF

PCR[SRC]=01b

50 pF

PCR[SRC]=11b

25 pF

PCR[SRC]=10b

50 pF

PCR[SRC]=01b

50 pF

PCS: PCR[SRC]=01b

50 pF

SCK: PCR[SRC]=10b

Value4

Unit

Min

Max

33.0

80.0

200.0

Table continues on the next page...

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Electrical characteristics
Table 47. DSPI CMOS master timing � output only � timed serial bus mode TSB = 1 or ITSB = 1, CPOL = 0 or 1, continuous SCK clock 1, 2 (continued)

# Symbol

Characteristic

tCSH PCS hold after SCK6

Condition3

Pad drive5 PCR[SRC]=11b

Load (CL) PCS: 0 pF

SCK: 50 pF

Value4

Unit

Min

Max

�14

PCR[SRC]=10b

PCS: 0 pF

�14

SCK: 50 pF

PCR[SRC]=01b

PCS: 0 pF

�33

SCK: 50 pF

PCS: PCR[SRC]=01b PCS: 0 pF

�35

tSDC SCK duty cycle7

SCK: PCR[SRC]=10b SCK: 50 pF

PCR[SRC]=11b

0 pF

PCR[SRC]=10b

0 pF

PCR[SRC]=01b

0 pF

SOUT data valid time (after SCK edge)

1/2tSCK � 2 1/2tSCK � 2 1/2tSCK � 5

1/2tSCK + 2

1/2tSCK + 5

tSUO SOUT data valid time

PCR[SRC]=11b

25 pF

from SCK

PCR[SRC]=10b

50 pF

CPHA = 18

PCR[SRC]=01b

50 pF

7.0

8.0

18.0

SOUT data hold time (after SCK edge)

tHO

SOUT data hold time

after SCK

CPHA = 18

PCR[SRC]=11b PCR[SRC]=10b PCR[SRC]=01b

25 pF 50 pF 50 pF

�9.0 �10.0 �21.0

1. TSB = 1 or ITSB = 1 automatically selects MTFE = 1 and CPHA = 1. 2. All output timing is worst case and includes the mismatching of rise and fall times of the output pads. 3. When a characteristic involves two signals, the pad drive and load conditions apply to each signal's pad, unless specified
otherwise. 4. All timing values for output signals in this table are measured to 50% of the output voltage. 5. Pad drive is defined as the PCR[SRC] field setting in the SIU. Timing is guaranteed to same drive capabilities for all
signals; mixing of pad drives may reduce operating speeds and may cause incorrect operation. 6. With TSB mode or Continuous SCK clock mode selected, PCS and SCK are driven by the same edge of DSPI_CLKn. This
timing value is due to pad delays and signal propagation delays. 7. tSDC is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide
ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time. 8. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same
value.

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Electrical characteristics

PCSx
tCSV
SCK Output (CPOL = 0)

tSDC

tSCK

tCSH

SOUT

First Data

tSUO
Data

tHO
Last Data

Figure 40. DSPI LVDS and CMOS master timing � output only � modified transfer format MTFE = 1, CHPA = 1

3.13.10 FEC timing

3.13.10.1 MII receive signal timing (RXD[3:0], RX_DV, and RX_CLK)

The receiver functions correctly up to a RX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency requirement. The system clock frequency must be at least equal to or greater than the RX_CLK frequency.

Table 48. MII receive signal timing1

Symbol
M1 M2 M3 M4

Characteristic
RXD[3:0], RX_DV to RX_CLK setup RX_CLK to RXD[3:0], RX_DV hold RX_CLK pulse width high RX_CLK pulse width low

Value

Min

Max

35%

65%

35%

65%

Unit
ns ns RX_CLK period RX_CLK period

1. All timing specifications valid to the pad input levels defined in I/O pad current specifications.

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

M3 RX_CLK (input)

Electrical characteristics

M4 RXD[3:0] (inputs)
RX_DV

Figure 41. MII receive signal timing diagram

3.13.10.2 MII transmit signal timing (TXD[3:0], TX_EN, and TX_CLK)

The transmitter functions correctly up to a TX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency requirement. The system clock frequency must be at least equal to or greater than the TX_CLK frequency.

The transmit outputs (TXD[3:0], TX_EN) can be programmed to transition from either the rising or falling edge of TX_CLK, and the timing is the same in either case. This options allows the use of noncompliant MII PHYs.

Refer to the MPC5777C Microcontroller Reference Manual's Fast Ethernet Controller (FEC) chapter for details of this option and how to enable it.

Table 49. MII transmit signal timing1

Symbol
M5 M6 M7 M8

Characteristic
TX_CLK to TXD[3:0], TX_EN invalid TX_CLK to TXD[3:0], TX_EN valid TX_CLK pulse width high TX_CLK pulse width low

Value2

Min

Max

4.5

35%

65%

35%

65%

Unit
ns ns TX_CLK period TX_CLK period

1. All timing specifications valid to the pad input levels defined in I/O pad specifications. 2. Output parameters are valid for CL = 25 pF, where CL is the external load to the device. The internal package capacitance
is accounted for, and does not need to be subtracted from the 25 pF value.

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Electrical characteristics M7

TX_CLK (input) M5

TXD[3:0] (outputs)

TX_EN

M6
Figure 42. MII transmit signal timing diagram

3.13.10.3 MII async inputs signal timing (CRS)
Table 50. MII async inputs signal timing

Symbol M9

Characteristic CRS minimum pulse width

Value

Min

Max

1.5

Unit TX_CLK period

CRS M9
Figure 43. MII async inputs timing diagram

3.13.10.4 MII and RMII serial management channel timing (MDIO and MDC)

The FEC functions correctly with a maximum MDC frequency of 2.5 MHz.

Table 51. MII serial management channel timing1

Symbol
M10
M11 M12 M13 M14 M15

Characteristic
MDC falling edge to MDIO output invalid (minimum propagation delay) MDC falling edge to MDIO output valid (max prop delay) MDIO (input) to MDC rising edge setup MDIO (input) to MDC rising edge hold MDC pulse width high MDC pulse width low

Value2

Min

Max

-- 10 0 40% 40%

25 -- -- 60% 60%

Unit
ns
ns ns ns MDC period MDC period

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

MDC (output) MDIO (output)

M14

M15

M10

Electrical characteristics

M11 MDIO (input)

M12 M13
Figure 44. MII serial management channel timing diagram

3.13.10.5 RMII receive signal timing (RXD[1:0], CRS_DV)

The receiver functions correctly up to a REF_CLK maximum frequency of 50 MHz +1%. There is no minimum frequency requirement. The system clock frequency must be at least equal to or greater than the RX_CLK frequency, which is half that of the REF_CLK frequency.

Table 52. RMII receive signal timing1

Symbol
R1 R2 R3 R4

Characteristic
RXD[1:0], CRS_DV to REF_CLK setup REF_CLK to RXD[1:0], CRS_DV hold REF_CLK pulse width high REF_CLK pulse width low

Value

Min

Max

35%

65%

35%

65%

Unit
ns ns REF_CLK period REF_CLK period

1. All timing specifications valid to the pad input levels defined in I/O pad specifications.

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Electrical characteristics R3
REF_CLK (input)

R4 RXD[1:0] (inputs)
CRS_DV

Figure 45. RMII receive signal timing diagram

3.13.10.6 RMII transmit signal timing (TXD[1:0], TX_EN)

The transmitter functions correctly up to a REF_CLK maximum frequency of 50 MHz + 1%. There is no minimum frequency requirement. The system clock frequency must be at least equal to or greater than the TX_CLK frequency, which is half that of the REF_CLK frequency.

The transmit outputs (TXD[1:0], TX_EN) can be programmed to transition from either the rising or falling edge of REF_CLK, and the timing is the same in either case. This options allows the use of non-compliant RMII PHYs.

Table 53. RMII transmit signal timing1

Symbol
R5 R6 R7 R8

Characteristic
REF_CLK to TXD[1:0], TX_EN invalid REF_CLK to TXD[1:0], TX_EN valid REF_CLK pulse width high REF_CLK pulse width low

Value2

Min

Max

35%

65%

35%

65%

Unit
ns ns REF_CLK period REF_CLK period

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

REF_CLK (input) R5

TXD[1:0] (outputs)

TX_EN

R6
Figure 46. RMII transmit signal timing diagram

Package information

4 Package information
To find the package drawing for each package, go to http://www.nxp.com and perform a keyword search for the drawing's document number:

If you want the drawing for this package 416-ball MAPBGA 516-ball MAPBGA

Then use this document number 98ASA00562D 98ASA00623D

4.1 Thermal characteristics
Table 54. Thermal characteristics, 416-ball MAPBGA package

Characteristic Junction to Ambient 1, 2 Natural Convection (Single layer board) Junction to Ambient 1, 3 Natural Convection (Four layer board 2s2p) Junction to Ambient (@200 ft./min., Single layer board) Junction to Ambient (@200 ft./min., Four layer board 2s2p) Junction to Board 4 Junction to Case 5 Junction to Package Top 6 Natural Convection

Symbol
RJA RJA RJMA RJMA RJB RJC
JT

Value 28.8 19.6 21.3 15.1 9.5 4.8 0.2

Unit �C/W �C/W �C/W �C/W �C/W �C/W �C/W

1. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
2. Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification. 3. Per JEDEC JESD51-6 with the board horizontal. 4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package. 5. Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method
(MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature.

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Package information

6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2.

Table 55. Thermal characteristics, 516-ball MAPBGA package

Symbol
RJA RJA RJMA RJMA RJB RJC
JT

Value 28.5 20.0 21.3 15.5 8.8 4.8 0.2

Unit �C/W �C/W �C/W �C/W �C/W �C/W �C/W

4.1.1 General notes for thermal characteristics An estimation of the chip junction temperature, TJ, can be obtained from the equation:

where:
TA = ambient temperature for the package (�C)
RJA = junction-to-ambient thermal resistance (�C/W)
PD = power dissipation in the package (W)
The thermal resistance values used are based on the JEDEC JESD51 series of standards to provide consistent values for estimations and comparisons. The difference between the values determined for the single-layer (1s) board compared to a four-layer board that has two signal layers, a power and a ground plane (2s2p), demonstrate that the effective thermal resistance is not a constant. The thermal resistance depends on the:
� Construction of the application board (number of planes)
� Effective size of the board which cools the component

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

� Quality of the thermal and electrical connections to the planes � Power dissipated by adjacent components

Package information

Connect all the ground and power balls to the respective planes with one via per ball. Using fewer vias to connect the package to the planes reduces the thermal performance. Thinner planes also reduce the thermal performance. When the clearance between the vias leave the planes virtually disconnected, the thermal performance is also greatly reduced.
As a general rule, the value obtained on a single-layer board is within the normal range for the tightly packed printed circuit board. The value obtained on a board with the internal planes is usually within the normal range if the application board has:
� One oz. (35 micron nominal thickness) internal planes
� Components are well separated
� Overall power dissipation on the board is less than 0.02 W/cm2

The thermal performance of any component depends on the power dissipation of the surrounding components. In addition, the ambient temperature varies widely within the application. For many natural convection and especially closed box applications, the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the local ambient conditions that determine the temperature of the device.
At a known board temperature, the junction temperature is estimated using the following equation:

where:
TB = board temperature for the package perimeter (�C)
RJB = junction-to-board thermal resistance (�C/W) per JESD51-8
PD = power dissipation in the package (W)
When the heat loss from the package case to the air does not factor into the calculation, the junction temperature is predictable if the application board is similar to the thermal test condition, with the component soldered to a board with internal planes.
The thermal resistance is expressed as the sum of a junction-to-case thermal resistance plus a case-to-ambient thermal resistance:

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Package information
where:
RJA = junction-to-ambient thermal resistance (�C/W)
RJC = junction-to-case thermal resistance (�C/W)
RCA = case to ambient thermal resistance (�C/W)
RJC is device related and is not affected by other factors. The thermal environment can be controlled to change the case-to-ambient thermal resistance, RCA. For example, change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. This description is most useful for packages with heat sinks where 90% of the heat flow is through the case to heat sink to ambient. For most packages, a better model is required.
A more accurate two-resistor thermal model can be constructed from the junction-toboard thermal resistance and the junction-to-case thermal resistance. The junction-to-case thermal resistance describes when using a heat sink or where a substantial amount of heat is dissipated from the top of the package. The junction-to-board thermal resistance describes the thermal performance when most of the heat is conducted to the printed circuit board. This model can be used to generate simple estimations and for computational fluid dynamics (CFD) thermal models. More accurate compact Flotherm models can be generated upon request.
To determine the junction temperature of the device in the application on a prototype board, use the thermal characterization parameter (JT) to determine the junction temperature by measuring the temperature at the top center of the package case using the following equation:

where:
TT = thermocouple temperature on top of the package (�C)
JT = thermal characterization parameter (�C/W)
PD = power dissipation in the package (W)
The thermal characterization parameter is measured in compliance with the JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. Position the thermocouple so that the thermocouple junction rests on the package. Place a small amount of epoxy on the thermocouple junction and approximately

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Ordering information
1 mm of wire extending from the junction. Place the thermocouple wire flat against the package case to avoid measurement errors caused by the cooling effects of the thermocouple wire.
When board temperature is perfectly defined below the device, it is possible to use the thermal characterization parameter (JPB) to determine the junction temperature by measuring the temperature at the bottom center of the package case (exposed pad) using the following equation:

where: TT = thermocouple temperature on bottom of the package (�C) JT = thermal characterization parameter (�C/W) PD = power dissipation in the package (W)

5 Ordering information

Figure 47 and Table 56 describe orderable part numbers for the MPC5777C.

M PC 5777C X K3 M ME 3/4 R

Qualification status Core code
Device number Optional features field
Fab/Revision Temperature range
Package identifier Operating frequency Tape and reel status

Temperature range

Package identifier

Tape and reel status

Qualification status

M = �40 �C to 125 �C ME = 416 MAPBGA Pb-Free R = Tape and reel P = Pre-qualification

Operating frequency MO = 516 MAPBGA Pb-Free 3 = 2 x 264 MHz

(blank) = Trays

M = Fully spec. qualified, general market flow S = Fully spec. qualified, automotive flow

4 = 2 x 300 MHz

Optional features field

(blank) = ISO-compliant CAN FD not available, trimmed for SMPS or external regulator, and includes SHE-compliant security firmware version 2.07

A = ISO-compliant CAN FD not available, trimmed for SMPS or external regulator, and includes SHE-compliant security firmware version 2.08

R = ISO-compliant CAN FD not available, trimmed for LDO regulator, and includes SHE-compliant security firmware version 2.08

C = ISO-compliant CAN FD available, trimmed for SMPS or external regulator, and includes SHE-compliant security firmware version 2.07

D = ISO-compliant CAN FD available, trimmed for SMPS or external regulator, and includes SHE-compliant security firmware version 2.08

L = ISO-compliant CAN FD available, trimmed for LDO regulator, and includes SHE-compliant security firmware version 2.08

S = ISO-compliant CAN FD available, trimmed for SMPS or external regulator, and includes RSA-enhanced security firmware

T = ISO-compliant CAN FD available, trimmed for LDO regulator, and includes RSA-enhanced security firmware

Note: Not all options are available on all devices.

Figure 47. MPC5777C Orderable part number description

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Document revision history
Table 56. Example orderable part numbers

Part number1 SPC5777CCK3MME3 SPC5777CK3MME3 SPC5777CCK3MMO3 SPC5777CK3MMO3

Package description
MPC5777C 416 package Lead-free (Pb-free)
MPC5777C 416 package Lead-free (Pb-free)
MPC5777C 516 package Lead-free (Pb-free)
MPC5777C 516 package Lead-free (Pb-free)

Speed (MHz)2 264 264 264 264

Operating temperature3

Min (TL) �40 �C

Max (TH) 125 �C

�40 �C

125 �C

�40 �C

125 �C

�40 �C

125 �C

1. All packaged devices are PPC5777C, rather than MPC5777C or SPC5777C, until product qualifications are complete. The unpackaged device prefix is PCC, rather than SCC, until product qualification is complete.
Not all configurations are available in the PPC parts. 2. For the operating mode frequency of various blocks on the device, see Table 3. 3. The lowest ambient operating temperature is referenced by TL; the highest ambient operating temperature is referenced by
TH.

6 Document revision history

The following table summarizes revisions to this document since the previous release.

Revision 14
13

Table 57. Revision history

Date 01/2020
08/2018

Description of changes
In Table 17, updated the footnote from "TUE does not apply to differential conversions" to "TUE, Gain, and Offset specifications do not apply to differential conversions".
In Table 4 added Max value 120 A for 40�C and 360 A for 85�C for ISTBY. In Table 3, added information for 300 MHZ frequency:
� fSYS � fPLATF � fETPU � fPER � ffFM_PER

In Table 12 added Max value 240 MHz for fPLL0PHI and Table 13 added Max value 300 MHz for fPLL1PHI. In Table 34 updated the row from "100 MHz > fPLATF 133 MHz" to "100 MHz > fPLATF 150 MHz" under "Flash memory frequency" column.
In Figure 47 added 300 MHz frequency orderable part number.

Table continues on the next page...

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

Table 57. Revision history (continued)

Document revision history

Revision 12

Date 08/2018

Description of changes
In Table 12 of PLL electrical specifications, changed text of footnote 1: � from: "fPLL0IN frequency must be scaled down using PLLDIG_PLL0DV[PREDIV] to ensure PFD input signal is in the range 8 MHz to 20 MHz." � to: "Ensure that the fPLL0IN frequency divided by PLLDIG_PLL0DV[PREDIV] is in the range 8 MHz to 20 MHz."

In Table 17 of Enhanced Queued Analog-to-Digital Converter (eQADC), added footnote about Max value of Conversion Cycles (CC): "128 sampling cycles (LST=128), differential conversion, pregain of x4"
In Table 38 of External Bus Interface (EBI) timing, changed text of footnote 1: � from: "EBI timing specified at VDD = 1.08 V to 1.32 V, VDDE = 3.0 V to 3.6 V, TA = TL to TH, and CL = 30 pF with SIU_PCR[DSC] = 10b for ADDR/CTRL and SIU_PCR[DSC] = 11b for CLKOUT/DATA." � to: "EBI timing specified at VDD = 1.08 V to 1.32 V, VDDE = 3.0 V to 3.6 V, TA = TL to TH, and CL = 30 pF with SIU_PCR[DSC] = 11b for ADDR/CTRL and SIU_PCR[SRC] = 11b for DATA/ ALE."

In I/O pad current specifications added the text "The EBI power segments have..........segment does not exceed the spec".

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

NXP Semiconductors

How to Reach Us:
Home Page: nxp.com
Web Support: nxp.com/support

Information in this document is provided solely to enable system and software implementers to use NXP products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. NXP reserves the right to make changes without further notice to any products herein.
NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including "typicals," must be validated for each customer application by customers technical experts. NXP does not convey any license under its patent rights nor the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the following address: nxp.com/SalesTermsandConditions.
While NXP has implemented advanced security features, all products may be subject to unidentified vulnerabilities. Customers are responsible for the design and operation of their applications and products to reduce the effect of these vulnerabilities on customer's applications and products, and NXP accepts no liability for any vulnerability that is discovered. Customers should implement appropriate design and operating safeguards to minimize the risks associated with their applications and products.
NXP, the NXP logo, NXP SECURE CONNECTIONS FOR A SMARTER WORLD, COOLFLUX, EMBRACE, GREENCHIP, HITAG, I2C BUS, ICODE, JCOP, LIFE VIBES, MIFARE, MIFARE CLASSIC, MIFARE DESFire, MIFARE PLUS, MIFARE FLEX, MANTIS, MIFARE ULTRALIGHT, MIFARE4MOBILE, MIGLO, NTAG, ROADLINK, SMARTLX, SMARTMX, STARPLUG, TOPFET, TRENCHMOS, UCODE, Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, Layerscape, MagniV, mobileGT, PEG, PowerQUICC, Processor Expert, QorIQ, QorIQ Qonverge, Ready Play, SafeAssure, the SafeAssure logo, StarCore, Symphony, VortiQa, Vybrid, Airfast, BeeKit, BeeStack, CoreNet, Flexis, MXC, Platform in a Package, QUICC Engine, SMARTMOS, Tower, TurboLink, and UMEMS are trademarks of NXP B.V. All other product or service names are the property of their respective owners. AMBA, Arm, Arm7, Arm7TDMI, Arm9, Arm11, Artisan, big.LITTLE, Cordio, CoreLink, CoreSight, Cortex, DesignStart, DynamIQ, Jazelle, Keil, Mali, Mbed, Mbed Enabled, NEON, POP, RealView, SecurCore, Socrates, Thumb, TrustZone, ULINK, ULINK2, ULINK-ME, ULINK-PLUS, ULINKpro, Vision, Versatile are trademarks or registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. The related technology may be protected by any or all of patents, copyrights, designs and trade secrets. All rights reserved. Oracle and Java are registered trademarks of Oracle and/or its affiliates. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org.
� 2013�2020 NXP B.V.
Document Number MPC5777C Revision 14, 01/2020