Index of /components/unitrode/ dataBooks
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About the Cover
The Hummingbird is amazing. It's incredibly fast, astonishingly energetic, and phenomenally efficient.
It's remarkably versatile--it can even fly backwards. It can survive in any kind of environment.
And it's a tough little bird that masters every challenge and easily out performs much bigger competitors.
In fact, it's so much like UICC and our products that we've adopted it as our mascot.
So when you consider qualities like speed, efficiency, dependability, versatility, toughness, and top performance in a small package, remember the hummingbird ... and UICC.
Unitrode Integrated Circuits Corporation (U.l.C.C.) makes no representation that the use or interconnection of the circuits described herein will not infringe on existing or future patent rights, nor do the descriptions contained herein imply the granting of licenses to make, use or sell equipment constructed in accordance therewith.
©1993, by Unitrode Integrated Circuits Corporation. All rights reserved. This book or any part or parts thereof, must not be reproduced in any form without permission of the copyright owner.
NOTE: The information presented in this book is believed to be accurate and reliable. U.l.C.C. reserves the right to make changes to the products contained in this databook to improve performance, reliability, or manufacturability. However, no responsibility is assumed by Unitrode Corporation for its use.
LIFE SUPPORT POLICY
U.l.C.C.'s products are not authorized for use as critical components in the life support devices or systems without express written approval.
Bus BossTM is a trademark of Unitrode Corporation Miller KillerTM is a trademark of Unitrode Corporation MULTIWATT® is a registered trademark of SGS Corporation Printed in U.S.A. - June, 1993
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Introduction
Unitrode Integrated Circuits Corporation - U.l.C.C. - is a world leader in the design and manufacturing. of high performance integrated circuits for power supplies, motor controls and power interface applications that demand high reliability, extraordinary quality and innovative technology.
Backed by a linear design team that we consider the best in the industry, by a total quality process designed and driven by our employees, by state-of-the-art manufacturing facilities, by a dynamic spirit of innovation and by the countless number of Continuous Improvement Teams passionately dedicated to customer satisfaction - the Company provides outstanding products and services globally. U.l.C.C serves customers around the world from:
· its recently expanded headquarters and principal manufacturing facility in Merrimack, New Hampshire;
· its design center in Raleigh, North Carolina;
· its extensive test, assembly subcontractor coordination and customer service facility in Singapore;
· and from its European distribution, quality and customer service facility in Ireland.
Process Capabilities U.l.C.C.'s strengths include a number of production process capabilities that complement its design expertise and enhance its product offerings.
Its BIPOLAR process, optimized for both precision analog and power functions, is constantly updated to incorporate leading edge process options such as:
· Schottky and integrated injection logic;
· ion implant;
· thin film resistors with laser trimming;
· double-level metallization for high density, high current layouts;
· and buried zener reference.
Its BICMOS process is ideal for high density linear and mixed mode designs, especially where speed and low power are of primary importance. Process options include:
e 3-m!cron, N-'Nel! process \AJ!th double po!y;
· double level metallization;
· fully isolated, vertical NPN transistors;
· and thin film resistors with laser trim capability.
New process capabilities include a complementary bipolar process that dielectrically isolates substrates using a low cost proprietary technique for direct bonding of silicon wafers. It is an extremely cost effective way of replacing junction isolation with dielectric isolation, leading to dramatic size reductions and performance enhancements unobtainable with conventional IC technologies.
Many of U.l.C.C.'s new processes will be manufactured in its new Class 10 Wafer Fab that will be completed by mid-1993.
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Introduction (Cont'd)
An ISO 9001 Firm In October 1992, U.l.C.C. became one of the very few U.S. electronics companies to achieve IS/ISO 9001/EN29001 registration.
The ISO 9000 quality system was developed to establish an international standard of quality. In order to be registered, a company must pass a rigorous assessment of its quality systems -- from design of its product through shipment. Registration thus assures customers all over the world that the company is adhering to very high, precisely defined standards.
Meeting Demanding Market Needs In the development of custom and semi-custom parts, U.1.C.C. design engineers work very closely with customer personnel. This close cooperation assures that all requirements are accurately understood, that all possibilities are fully explored, and that the resulting products meet and exceed specified needs.
U.l.C.C. pays careful attention to customers and markets to help guide its development of catalog parts. Continuing close contact makes it possible to anticipate industry requirements, and to create devices that will satisfy them.
A Resource You Can Count On Unitrode Integrated Circuits Corporation has earned its reputation for excellence in computer, communications, automotive, industrial, commercial and military markets. It is totally committed to continuing that excellence in everything it does.
With products and services that are among the most innovative in the industry, with proven quality and reliability, and with superb design engineering and the industry's best applications technical support, U.1.C.C. is a resource you can depend on.
This databook describes new as well as previously introduced products, and it includes detailed applications information. We welcome your inquiries about our products and services, and we look forward to working with you.
iii
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iv
Part Number Index General Information
Military/Aerospace Products Automotiue Products
Power Supply Circuits Intelligent Motion Circuits
Power Driuer & Interface Circuits Packaging Information
Application Notes Sales Offices
v
TABLE OF CONTENTS
1. Part Number lndex ...........................................................................1-3 2. General Information
- About this Databook ............................................................................2-3 - Ordering Information ...........................................................................2-4 - Quality..................................................................................................2-5 - New Products ....................................................................................2-11 - Package Cross Reference ................................................................2-14 - Die and Wafers ..................................................................................2-15
3. Military/Aerospace Products
- Capabilities ..........................................................................................3-4 - Standardized Military Drawings (SMDs) .............................................3-5 - Packages .............................................................................................3-8 - Military Die Capability ..........................................................................3-9
4. Automotive Products
- Capabilites ...........................................................................................4-4 - Products ..............................................................................................4-5
5. Power Supply Circuits
- Selection Guides .................................................................................5-3 - Datasheets ........................................................................................5-15
6. Intelligent Motion Circuits
- Selection Guides .................................................................................6-3 - Datasheets ..........................................................................................6-6
7. Power Driver & Interface Circuits
- Selection Guides .................................................................................7-3 - Datasheets ..........................................................................................7-7
vi
8. Packaging Information
- lndex ....................................................................................................8-3 - Device Temperature Management......................................................8-5 - Thermal Characteristics of
Surface Mount Packages .................................................................8-8 - Mechanical Drawings ........................................................................8-13
9. Application Notes
-Table of Contents ................................................................................9-3 - Application Notes ................................................................................9-5 - Design Notes ...................................................................................9-485
10. Sales Offices .....................................................................................1o-3
vii
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viii
Part Number Index
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1-2
PART NUMBER INDEX
PART NUMBER INDEX
PAGE 6-6 6-6 7.7
6-11
.6-15 .
.
5-15 5-15
..5-15 . .
. .
. .
.
5-19
5-19
5-19
5-19
6-19 5-23
5-28
5-34
5-41
5-47
5-54
5-34
5-41
PART NUMBER DESCRIPTION
l293
Push-Pull Four Channel Driver
L293D
Push-Pull Four Channel Driver
L295
Dual Switchmode Solenoid
Driver
l298
Dual Full-Bridge Powe,r Driver
l298D
Dual Full-Bridge Powe'r-Driver
UC117
1.5A, Three Terminal Adj .
Voltage Regulator
UC137
1.5A, Three Terminal Adj .
Negative Voltage Regulator
UC150
3A, Three Terminal Adj.
Positive Voltage Regulator
UC161A
Micropower Quad Comparator
UC161B
Micropower Quad Comparator
UC161C
Micropower Quad Comparator
UC195
Smart Power Transistor
UC217
1.5A, Three Terminal Adj .
Voltage Regulators
UC237
1.5A, Three Terminal Adj .
Negative Voltage Regulator
UC250
3A, Three Terminal Adj .
Positive Voltage Regulator
UC295
Smart Power Transistor
UC317
1.5A, Three Terminal Adj.
Voltage Regulators
UC337
1.5A, Three Terminal Adj .
Negative Voltage Regulator
UC350
3A, Three Terminal Adj .
Positive Voltage Regulator
UC395
Smart Power Transistor
UC494A
Advanced Regulating Pulse
Width Modulators
UC494AC
Advanced Regulating Pulse
Width Modulators
UC495A
Advanced Regulating Pulse
Width Modulators
UC495AC
Advanced Regulating Pulse
Width Modulators
UC1517
Stepper Motor Drive Circuit
UC1524
Advanced Regulating Pulse
Width Modulators
UC1524A
Advanced Regulating Pulse
Width Modulators
UC1525A
Regulating Pulse Width
Modulators
UC1525B
Regulating Pulse Width
Modulators
UC1526
Regulating Pulse Width
Monitor
UC1526A
Regulating Pulse Width
Modulator
UC1527A
Regulating Pulse Width
Modulators
UC1527B
Regulating Pulse Width
Modulators
PAGE
PART NUMBER DESCRIPTION
5-62
UC1543
Power Supply Supervisory
Circuit
5-62
UC1544
Power Supply Supervisory
Circuit
5-67
UC1575-5
Simple 1 Amp Step-Down
Fixed Voltage Regulators
5-67
UC1575-12 Simple 1 Amp Step-Down
Fixed Voltage Regulators
5-67
UC1575-15 Simple 1 Amp Step-Down
Fixed Voltage Regulators
5.73
UC1575-ADJ Simple 1 Amp Step-Down
Voltage Regulator
5-80
UC1576-5
Simple 3 Amp Step-Down
Fixed Voltage Regulators
5-80
UC1576·12
Simple 3 Amp Step-Down
Fixed Voltage Regulators
5-80
UC1576-15 Simple 3 Amp Step-Down
Fixed Voltage Regulators
5-87
UC1576-ADJ Simple 3 Amp Step-Down
Voltage Regulator
5-94
UC15n-12
Simple Step-Up Fixed Voltage
Regulators
5-94
UC1577-15
Simple Step-Up Fixed Voltage
Regulators
5.99
UC15n-ADJ Simple Step-Up Voltage
Regulator
6-26 & 5-106 UC1610
Dual Schottky Diode Bridge
6·28 & 5-108 UC1611
Quad Schottky Diode Array
6-31 & 5-111 UC1612
Dual Schottky Diode
6-33
UC1620
Swltchmode Driver for 3-0
Brushless DC Motors
6-39
UC1625
Brushiess DC Motor Controller
6-50
UC1633
Phase Locked Frequency
Controller
6-57
UC1634
Phased Locked Frequency
Controller
6-61
UC1635
P~ased Locked Frequency
Controller
6-65
UC1637
Switched Mode Controller for
DC Motor Drive
7-11
UC1705
High Speed Power Driver
7-14
UC1706
Dual Output Driver
7-19
UC1707
Dual Channel Power Driver
7-25
UC1708
Dual Non-Inverting Power
Driver
7-29
UC1709.
Dual High-Speed FET Driver
7-32
UC1710
High Current FET Driver
7.35
UC1711
Dual Ultra High-Speed FET
Driver
6-71
UC1717
Stepper Motor Drive Circuit
7.37
UC1724
Isolated Drive Transmitter
7-40
UC1725
Isolated High Side FET Driver
7-44
UC1726
Isolated Drive Transmitter
7-49
UC1727
Isolated High Side IGBT Driver
7.55
UC1730
Thermal Monitor
5-113
UC1823
High Speed PWM Controller
5-119
UC1823A
High Speed PWM Controller
*Consult Factory 1·3
PART NUMBER INDEX
PAGE 5-119 5-127 5-134 5-119 5-119 5-141
5-142
5-142
5-149
5-155
5-155
5-159 5-163
5-171
5-179 5-186 5-179 5-186 5-179 5-186 5-179 5-186 5-192 5-192 5-199
5-207
5-213
5-218
5-226
5-226
5-229
5-237
5-245
5-245
5-245
5-245
PART NUMBER DESCRIPTION
UC18238
High Speed PWM Controller
UC1824
High Speed PWM Controller
UC1825
High Speed PWM Controller
UC1825A
High Speed PWM Controller
UC18258
High Speed PWM Controller
UC1828
Current Mode PWM Controller
IC
UC1832
Precision Low Dropout Linear
Controllers
UC1833
Precision Low Dropout Linear
Controllers
UC1834
High Efficiency Linear
Regulator
UC1835
High Efficiency Regulator
Controller
UC1836
High Efficiency Regulator
Controller
UC1838A
Magnetic Amplttier Controller
UC1840
Programmable, Off-Line, PWM
Controller
UC1841
Programmable, Off-Line, PWM
Controller
UC1842
Current Mode PWM Controller
UC1842A
Current Mode PWM Controller
UC1843
Current Mode PWM Controller
UC1843A
Current Mode PWM Controller
UC1844
Current Mode PWM Controller
UC1844A
Current Mode PWM Controller
UC1845
Current Mode PWM Controller
UC1845A
Current ModePWM Controller
UC1846
Current Mode PWM Controller
UC1847
Current Mode PWM Controller
UC1848
Average Current Mode PWM
Controller
UC1851
Programmable, Off-Line, PWM
Controller
UC1852
High Power-Factor
Preregulator
UC1854
High Power Factor
Preregulator
UC1854A
Enhanced High Power Factor
Preregulator
UC18548
Enhanced High Power Factor
Preregulator
UC1856
Improved Current Mode PWM
Controller
UC1860
Resonant Mode Power Supply
Controller
UC1861
Resonant-Mode Power Supply
Controllers
UC1862
Resonant-Mode Power Supply
Controllers
UC1863
Resonant-Mode Power Supply
Controllers
UC1864
Resonant-Mode Power Supply
Controllers
PAGE 5-245 5-245 5-245 5-245 5-251 5-256 5-256 5-256 5-256 5-265 5-265 5-265 5-265 5-269 5-274 5-281 5-286 5-23 5-28 5-34 5-41 5-47 5-54 5-34 5-41 5-62 5-62 5-67 5-67 5-67
*Consult Factory 1-4
PART NUMBER INDEX
PART NUMBER DESCRIPTION
UC1865
Resonant-Mode Power Supply
Controllers
UC1866
Resonant-Mode Power Supply
Controllers
UC1867
Resonant-Mode Power Supply
Controllers
UC1868
Resonant-Mode Power Supply
Controllers
UC1871
Resonant Fluorescent Lamp
Driver
UC1875
Phase Shift Resonant
Controller
UC1876
Phase Shift Resonant
Controller
UC1877
Phase Shift Resonant
Controller
UC1878
Phase Shift Resonant
Controller
UC1891
Two Stage Power Factor
Converter
UC1892
Two Stage Power Factor
Converter
UC1893
Two Stage Power Factor
Converter
UC1894
Two Stage Power Factor
Converter
UC1901
Isolated Feedback Generator
UC1903
Quad Supply and Line Monitor
UC1904
Precision Quad Supply and
Line Monitor
UC1907
Load Share Controller
UC2524
Advanced Regulating Pulse
Width Modulators
UC2524A
Advanced Regulating Pulse
Width Modulators
UC2525A
Regulating Pulse Width
Modulators
UC25258
Regulating Pulse Width
Modulators
UC2526
Regulating Pulse Width
Monitor
UC2526A
Regulating Pulse Width
Modulator
UC2527A
Regulating Pulse Width
Modulators
UC25278
Regulating Pulse Width
Modulators
UC2543
Power Supply Supervisory
Circuit
UC2544
Power Supply Supervisory
Circuit
UC2575-5
Simple 1 Amp Step-Down
Fixed Voltage Regulators
UC2575-12
Simple 1 Amp Step-Down
Fixed Voltage Regulators
UC2575-15
Simple 1 Amp Step-Down
Fixed Voltage Regulators
PART NUMBER INDEX
PAGE 5-73
5-67
5-67
5-67
5-73
5-80
5-80
5-80
5-87
5-80
5-80
5-80
5-87
5-94
5-94
5-99
6-50
6-57
6-61
6-65
7-11 7-14 7-19 7-37 7-40 7-44 7-49 7-55 5-113 5-119 5-119 5-127 5-134 5-119 5-119 5-141
PART NUMBER DESCRIPTION
UC2575-ADJ Simple 1 Amp Step-Down
Voltage Regulator
UC2575HV-5 Simple 1 Amp Step-Down
Fixed Voltage Regulators
UC2575HV-12 Simple 1 Amp Step-Down
Fixed Voltage Regulators
UC2575HV-15 Simple 1 Amp Step-Down
Fixed Voltage Regulators
UC2575HV-ADJ Simple 1 Amp Step-Down
Voltage Regulator
UC2576-5
Simple 3 Amp Step-Down
Fixed Voltage Regulators
UC2576-12
Simple 3 Amp Step-Down
Fixed Voltage Regulators
UC2576-15
Simple 3 Amp Step-Down
Fixed Voltage Regulators
UC2576-ADJ Simple 3 Amp Step-Down
Voltage Regulator
UC2576HV-5 Simple 3 Amp Step-Down
Fixed Voltage Regulators
UC2576HV-12 Simple 3 Amp Step-Down
Fixed Voltage Regulators
UC2576HV-15 Simple 3 Amp Step-Down
Fixed Voltage Regulators
UC2576HV-ADJ Simple 3 Amp Step-Down
Voltage Regulator
UC2577-12
Simple Step-Up Fixed Voltage
Regulators
UC2577-15
Simple Step-Up Fixed Voltage
Regulators
UC2577-ADJ Simple Step-Up Voltage
Regulator
UC2633
Phase Locked Frequency
Controller
UC2634
Phased Locked Frequency
Controller
UC2635
Phased Locked Frequency
Controller
UC2637
Switched Mode Controller for
DC Motor Drive
UC2705
High Speed Power Driver
UC2706
Dual Output Driver
UC2707
Dual Channel Power Driver
UC2724
Isolated Drive Transmitter
UC2725
Isolated High Side FET Driver
UC2726
Isolated Drive Transmitter
UC2727
Isolated High Side IGBT Driver
UC2730
Thermal Monitor
UC2823
High Speed PWM Controller
UC2823A
High Speed PWM Controller
UC2823B
High Speed PWM Controller
UC2824
High Speed PWM Controller
UC2825
High Speed PWM Controller
UC2825A
High Speed PWM Controller
UC2825B
High Speed PWM Controller
UC2828
Current Mode PWM Controller
IC
PAGE 5-142
5-142
5-149
5-155
5-155
5-159 5-163
5-171
5-179 5-186 5-179 5-186 5-179 5-186 5-179 5-186 5-192 5-192 5-199
5-207
5-213
5-218
5-226
5-226
5-229
5-237
5-245
5-245
5-245
5-245
5-245
5-245
5-245
5-245
1-5
PART NUMBER INDEX
PART NUMBER DESCRIPTION
UC2832
Precision Low Dropout Linear
Controllers
UC2833
Precision Low Dropout Linear
Controllers
UC2834
High Efficiency Linear
Regulator
UC2835
High Efficiency Regulator
Controller
UC2836
High Efficiency Regulator
Controller
UC2838A
Magnetic Amplifier Controller
UC2840
Programmable, Off-Line, PWM
Controller
UC2841
Programmable, Off-Line, PWM
Controller
UC2842
Current Mode PWM Controller
UC2842A
Current Mode PWM Controller
UC2843
Current Mode PWM Controller
UC2843A
Current Mode PWM Controller
UC2844
Current Mode PWM Controller
UC2844A
Current Mode PWM Controller
UC2845
Current Mode PWM Controller
UC2845A
Current Mode PWM Controller
UC2846
Current Mode PWM Controller
UC2847
Current Mode PWM Controller
UC2848
Average Current Mode PWM
Controller
UC2851
Programmable, Off-Line, PWM
Controller
UC2852
High Power-Factor
Preregulator
UC2854
High Power Factor
Preregulator
UC2854A
Enhanced High Power Factor
Preregulator
UC2854B
Enhanced High Power Factor
Preregulator
UC2856
Improved Current Mode PWM
Controller
UC2860
Resonant Mode Power Supply
Controller
UC2861
Resonant-Mode Power Supply
Controllers
UC2862
Resonant-Mode Power Supply
Controllers
UC2863
Resonant-Mode Power Supply
Controllers
UC2864
Resonant-Mode Power Supply
Controllers
UC2865
Resonant-Mode Power Supply
Controllers
UC2866
Resonant-Mode Power Supply
Controllers
UC2867
Resonant-Mode Power Supply
Controllers
UC2868
Resonant-Mode Power Supply
Controllers
PART NUMBER INDEX
PAGE
PART NUMBER DESCRIPTION
5-251
UC2871
Resonant Fluorescent Lamp
Driver
5-256
UC2875
Phase Shift Resonant
Controller
5-256
UC2876
Phase Shift Resonant
Controller
5-256
UC2877
Phase Shift Resonant
Controller
5-256
UC2878
Phase Shift Resonant
Controller
5-265
UC2891
Two Stage Power Factor
Converter
5-265
UC2892
Two Stage Power Factor
Converter
5-265
UC2893
Two Stage Power Factor
Converter
5-265
UC2894
Two Stage Power Factor
Converter
5-269
UC2901
Isolated Feedback Generator
5-274
UC2903
Quad Supply and Line Monitor
5-281
UC2904
Precision Quad Supply and
Line Monitor
5-292
UC:?!J06
Sealed Lead-Acid Battery
Charger
5-286
UC2907
Load Share Controller
7-59
UC2950
Hatt-Bridge Bipolar Switch
6-79
UC3173A.
Full Bridge Power Amp!Hier
6-89
UC3174B
Full-Bridge Power Amplifier
6-89
UC3175B
Full-Bridge Power Amplifier
6-94
UC3176
Full Bridge Power Amplifier
6-94
UC3177
Full Bridge Power Amplttier
6-98
UC3178
Full Bridge Power Amplttier
6-19
UC3517
Stepper Motor Drive Circuit
5-23
UC3524
Advanced Regulating Pulse
Width Modulators
5-28
UC3524A
Advanced Regulating Pulse
Width Modulators
5-34
UC3525A
Regulating Pulse Width
Modulators
5-41
UC3525B
Regulating Pulse Width
Modulators
5-47
UC3526
Regulating Pulse Width
Monitor
5-54
UC3526A
Regulating Pulse Width
Modulator
5-34
UC3527A
Regulating Pulse Width
Modulators
5-41
UC3527B
Regulating Pulse Width
Modulators
5-62
UC3543
Power Supply Supervisory
Circuit
5-62
UC3544
Power Supply Supervisory
Circuit
6-26 & 5-106 UC3610
Dual Schottky Diode Bridge
6-28 & 5-108 UC3611
Quad Schottky Diode Array
6-31 &5-111 UC3612
Dual Schottky Diode
PAGE 6-33
6-103
6-107
6-39 6-50
6-57
6-61
6-65
6-110
7-61 7-65 7-11 7-14 7-19 7-25
7-29 7-32 7-35
.6-71
6-115*
7-37 7-40 7-44 7-49 7-55 6-123
6-123
5-113 5-119 5-119 5-127 5-134 5-119 5-119 5-141
5-142
5-142
5-149
*Consult Factory 1-6
PART NUMBER INDEX
PART NUMBER DESCRIPTION
UC3620
Switchmode Driver for 3-0
Brushless DC Motors
UC3622
Switchmode Driver for 3-0
Brushless DC Motors
UC3623
Low Noise Switchmode Driver
for 3-0 Brushless DC Motors
UC3625
Brushless DC Motor Controller
UC3633
Phase Locked Frequency
Controller
UC3634
Phased Locked Frequency
Controller
UC3635
Phased Locked Frequency
Controller
UC3637
Switched Mode Controller for
DC Motor Drive
UC3655
Low Saturation, Linear
Brushless DC Motor Driver
UC3657
Triple Tri-State Power Driver
UC3704
Bridge Transducer Switch
UC3705
High Speed Power Driver
UC3706
Dual Output Driver
UC3707
Dual Channel Power Driver
UC3708
Dual Non-Inverting Power
Driver
UC3709
Dual High-Speed FET Driver
UC3710
High Current FET Driver
UC3711
Dual Ultra High-Speed FET
Driver
UC3717
Stepper Motor Drive Circuit
UC3717A
Stepper Motor Drive Circuit
UC3722
Five-Channel Programmable
Current Switch
UC3724
Isolated Drive Transmitter
UC3725
Isolated High Side FET Driver
UC3726
Isolated Drive Transmitter
UC3727
Isolated High Side IGBT Driver
UC3730
Thermal Monitor
UC3770A
High Performance Stepper
Motor Drive Circuit
UC3770B
High Performance Stepper
Motor Drive Circuit
UC3823
High Speed PWM Controller
UC3823A
High Speed PWM Controller
UC3823B
High Speed PWM Controller
UC3824
High Speed PWM Controller
UC3825
High Speed PWM Controller
UC3825A
High Speed PWM Controller
UC3825B
High Speed PWM Controller
UC3828
Current Mode PWM Controller
IC
UC3832
Precision Low Dropout Linear
Controllers
UC3833
Precision Low Dropout Linear
Controllers
UC3834
High Efficiency Linear
Regulator
PART NUMBER INDEX
PAGE 5-155
5-155
5-159 5-163
5-171
5-179 5-186 5-179 5-186 5-179 5-186 5-179 5-186 5-192 5-192 5-199
5-207
5-213
5-218
5-226
5-226
5-229
5-237
5-245
5-245
5-245
5-245
5-245
5-245
5-245
5-245
5-251
5-256
5-256
PART NUMBER DESCRIPTION
UC3835
High Efficiency Regulator
Controller
UC3836
High Efficiency Regulator
Controller
UC3838A
Magnetic Amplifier Controller
UC3840
Programmable, Off-Line, PWM
Controller
UC3841
Programmable, Off-Line, PWM
Controller
UC3842
Current Mode PWM Controller
UC3842A
Current Mode PWM Controller
UC3843
Current Mode PWM Controller
UC3843A
Current Mode PWM Controller
UC3844
Current Mode PWM Controller
UC3844A
Current Mode PWM Controller
UC3845
Current Mode PWM Controller
UC3845A
Current Mode PWM Controller
UC3846
Current Mode PWM Controller
UC3847
Current Mode PWM Controller
UC3848
Average Current Mode PWM
Controller
UC3851
Programmable, Off-Line, PWM
Controller
UC3852
High Power-Factor
Preregulator
UC3854
High Power Factor
Preregulator
UC3854A
Enhanced High Power Factor
Preregulator
UC3854B
Enhanced High Power Factor
Preregulator
UC3856
Improved Current Mode PWM
Controller
UC3860
Resonant Mode Power Supply
Controller
UC3861
Resonant-Mode Power Supply
Controllers
UC3862
Resonant-Mode Power Supply
Controllers
UC3863
Resonant-Mode Power Supply
Controllers
UC3864
Resonant-Mode Power Supply
Controllers
UC3865
Resonant-Mode Power Supply
Controllers
UC3866
Resonant-Mode Power Supply
Controllers
UC3867
Resonant-Mode Power Supply
Controllers
UC3868
Resonant-Mode Power Supply
Controllers
UC3871
Resonant Fluorescent Lamp
Driver
UC3875
Phase Shift Resonant
Controller
UC3876
Phase Shift Resonant
Controller
PAGE 5-256
5-256
5-265
5-265
5-265
5-265
5-269 5-274 5-281
5-292
5-286 7-69 7-73 7-77 7-81 7-84 7-87 7-91 7-96 7-101
5-299 5-300
.5-299 .
.
. . .
5-301
5-306 5-301
5-306 5-301
5-306 5-312
5-319
·consult Factory 1-7
PART NUMBER INDEX
PART NUMBER DESCRIPTION
UC3877
Phase Shift Resonant
Controller
UC3878
Phase Shift Resonant
Controller
UC3891
Two Stage Power Factor
Converter
UC3892
Two Stage Power Factor
Converter
UC3893
Two Stage Power Factor
Converter
UC3894
Two Stage Power Factor
Converter
UC3901
Isolated Feedback .Generator
UC3903
Quad Supply and Line Monitor
UC3904
Precision Quad Supply and
Line Monitor
UC3906
Sealed Lead-Acid Battery
Charger
UC3907
Load Share Controller
UC5170C
Octal Line Driver
UC5171
Octal Line Driver
UC5172
Octal Line Driver
UC5180C
Octal Line Receiver
UC5181C
Octal Line Receiver
UC5601
SCSI Active Terminator
UC5602
SCSI Active Terminator
UC5603
9-Line SCSI Active Terminator
UC5661
Ethernet Coaxial Impedance
Monitor
UC7501
Primary Side Controller
UC7502
Error Signal Isolator
UC7503
Primary Side Controller
UC7805
Three Terminal Fixed Voltage
Positive Regulators
UC7812
Three Terminal Fixed Voltage
Positive Regulators
UC7815
Three Terminal Fixed Voltage
Positive Regulators
UC7905
Three Terminal Fixed Voltage
Negative Regulators
UC7912
Three Terminal Fixed Voltage
Negative Regulators
UC7915
Three Terminal Fixed Voltage
Negative Regulators
UC19431
Precision Adjustable Shunt
Regulator
UC19432
Precision Analog Controller
UC29431
Precision Adjustable Shunt
Regulator
UC29432
Precision Analog Controller
UC39431
Precision Adjustable Shunt
Regulator
UC39432
Precision Analog Controller
UCC1570
Low Power Pulse Width
Modulator
UCC1800
Low-Power Bi CMOS
Current-Mode PWM
PART NUMBER INDEX
PAGE 5-319 5-319 5-319 5-319 5-319 5-323 5-326 5-309 5-309 5-309 5-327 5-337 5-312 5-319 5-319 5-319 5-319 5-319 5-319 5-323
PART NUMBER DESCRIPTION
UCC1801
Low-Power BiCMOS
Current-Mode PWM
UCC1802
Low-Power BiCMOS
Current-Mode PWM
UCC1803
Low-Power BiCMOS
Current-Mode PWM
UCC1804
Low-Power BiCMOS
Current-Mode PWM
UCC1805
Low-Power Bi CMOS
Current-Mode PWM
UCC1806
Low Power, Dual Output,
Current Mode PWM Controller
UCC1810
Low-Power Bi CMOS Dual
Current-Mode PWM
UCC183-0
Low Drop Out 3 Ampere
Linear Regulator Family
UCC183-3
Low Drop Out 3 Ampere
Linear Regulator Family
UCC183-5
Low Drop Out 3 Ampere
Linear Regulator Family
UCC1883
Micropower Peak Current
Mode Controller
UCC1885
Micropower Secondary
Regulation IC
UCC2570
Low Power Pulse Width
Modulator
UCC2800
Low-Power BiCMOS
Current-Mode PWM
UCC2801
Low-Power BiCMOS
Current-Mode PWM
UCC2802
Low-Power BiCMOS
Current-Mode PWM
UCC2803
Low-Power BiCMOS
Current-Mode PWM
UCC2804
Low-Power BiCMOS
Current-Mode PWM
UCC2805
Low-Power BiCMOS
Current-Mode PWM
UCC2806
Low Power, Dual Output,
Current Mode PWM Controller
PAGE 5-326 5-309 5-309 5-309 5-327 5-337 5-312 5-319 5-319 5-319 5-319 5-319 5-319 5-323 5-326 5-309 5-309 5-309 5-327 5-337
PART NUMBER INDEX
PART NUMBER DESCRIPTION
UCC2810
Low-Power BiCMOS Dual
Current-Mode PWM
UCC283-0
Low Drop Out 3 Ampere
Linear Regulator Family
UCC283-3
Low Drop Out 3 Ampere
Linear Regulator Family
UCC283-5
Low Drop Out 3 Ampere
Linear Regulator Family
UCC2883
Micropower Peak Current
Mode Controller
UCC2885
Micropower Secondary
Regulation IC
UCC3570
Low Power Pulse Width
Modulator
UCC3800
Low-Power BiCMOS
Current-Mode PWM
UCC3801
Low-Power BiCMOS
Current-Mode PWM
UCC3802
Low-Power BiCMOS
Current-Mode PWM
UCC3803
Low-Power BiCMOS
Current-Mode PWM
UCC3804
Low-Power BiCMOS
Current-Mode PWM
UCC3805
Low-Power BiCMOS
Current-Mode PWM
UCC3806
Low Power, Dual Output,
Current Mode PWM Controller
UCC3810
Low-Power BiCMOS Dual
Current-Mode PWM
UCC383-0
Low Drop Out 3 Ampere
Linear Regulator Family
UCC383-3
Low Drop Out 3 Ampere
Linear Regulator Family
UCC383-5
Low Drop Out 3 Ampere
Linear Regulator Family
UCC3883
Micropower Peak Current
Mode Controller
UCC3885
Micropower Secondary
Regulation IC
*Consult Factory 1-8
General Information
n n INTEGRATED
~CIRCUITS
-UNITROOE
2-2
n n INTEGRATED
~CIRCUITS
-UNITRODE ABOUT THIS DATABOOK
PRODUCT CLASSIFICATION STATUS
liiiiii~F~o~rm~a;ti~ve~or11fT~h~is~d;oc~u;,ment
contains the design
111:1
Design
specifications for product under
development. Specifications may be
changed in any manner without
notice.
First Production
Supplementary data may be published at a later date. U.1.C.C. reserves the right to make changes at any time without notice, in order to improve design and supply the best product possible.
Full Production
Product in Full Production
This databook contains complete data and applications information about Unitrode Linear Integrated Circuits for industrial and military applications. It includes all our latest new products including products that will be introduced throughout the year 1993.
For more information about any new products or any of U.l.C.C. service capabilities, please call, write or fax.
2-3
n nINTEGRATED
~CIRCUIT&
-UNITRODE
GENERAL INFORMATION
PART NUMBER DESIGNATORS
PREFIX "UC" Linear Integrated Circuits
PARTNUMBER ·4Piw==M *Generic P/N's (See Data Sheets For Descriptions) *5 Digit In-House Number To Spec. Control Drawings
OPTIONAL GRADES A - Improved Version C- "Commercial " Temperature Range
l.-«<ic.~<i*'~.,, Compliant "C" Indicator
Per MIL-STD-883. SCREEN/PROCESSING OPTIONS 883 - MIL-STD-883
ClassB JAN - MIL-M-38510
(Integrated Circuits) SMD- STD Military Drawing
(DESC)
Glass-Sealed Ceramic DIP 14 Pin Narrow Body SO (150 ml) 16 Pin Narrow Body (150 ml) Power SO 16120 Pin Wide Body SO Surface Mount (300 ml) 28 Pin Wide Body Power SO Ceramic leadless Chip Carrier Plastic Molded Quad PlCC 15 Pin Power SIP T0-39 Metal Can T0-3 Steel-Base Power T0-220 Plastic Power Ceramic Power T0-257 Hermetic (T0-220 Style) T0-257 Hermetic Isolated Tab 16 Pin Power ZIP For More Information See Packaging Section 2-4
n n L::::::::J
INTEGRATED CIRCUITS
-uNITRODE
QUALITY STATEMENT
Since its founding, Unitrode Integrated Circuits Corp. (U.l.C.C.) has structured its development to fully respond to customer requirements in areas of quality and overall product assurance, with particular emphasis on enhanced design and reliability.
As part of its total quality planning, U.l.C.C. has progressed through the traditional techniques of control by appraisal to a more mutually satisfying statistically based process monitoring. However, immature process nodes may still require the use of universally accepted sampling plans, such as those referenced in MIL-STD-105 and MIL-M-38510.
UNITRODE INTEGRATED CIRCUITS REGISTERED AS ISO 9001 FIRM (Registration Number M667)
In the fall of 1992, Unitrode Integrated Circuits Corporation (U.l.C.C.) announced that it achieved IS/ISO 9001/EN 29001 Registration. Adopted in 1987 by the International Organization for Standardization in Geneva, Switzerland, the ISO 9000 quality system was developed in order to establish an international standard of quality systems--from design of its product through shipment. Therefore, when a firm is registered to meet ISO 9000, customers all over the world are assured that the firm is adhering to very specific quality standards.
U.l.C.C. attributes the ISO 9001 achievement in great part to its Total Quality Excellence (TOE) process, designed entirely by a team of employees representing all levels of the organization. The theme of U.l.C.C.'s quality program, "Building Customer Loyalty", focuses on internal and external customer satisfaction.
l.S./ISO 9001/EN 29001
2-5
n n L.::::::J
INTEGRATED CIRCUIT&
-UNITRODE
GENERAL INFORMATION
Quality
TOTAL QUALITY EXCELLENCE
A key element of the Company's strategy and an important factor in its success has been its focus on customer satisfaction. Everything the Company does is aimed at providing its customers with the highest possible levels of quality, reliability and technical support.
Quality, Reliability and Innovation
Quality and reliability are the hallmarks of all U.l.C.C. products - standards of excellence are woven tightly into the Company's corporate fabric, implemented through a Total Quality Excellence process which permeates everything the Company does.
Total Quality Excellence - TOE - impacts each and every department, each and every activity, and each and every product - from initial concept to enduse installation and operation.
Continuous Improvement
The aim of the TOE process is continuous improvement - it is a never ending search for ways to improve everything the Company is and does, and a pledge to ultimately translate improvements into better products and services for customers. For example, goals include:
· improved designs that meet the broadest spectrum of application needs;
· improved translation of customer requirements into actual product performance characteristics;
· improved understanding of process capabilities to improve the product introduction process;
· higher productivity, less scrap and rework, and lower production costs, all which can be passed along to customers.
Employee Teams
To make continuous improvement a reality, through total involvement, there are more than 20 employee teams focused on product, process and service improvement. Using Statistical Process Control methods as the quantitative tools to facilitate the process, these teams help make it possible for the Company to attain the milestones on the road of continuous improvement.
The entire process was put together and is now operated by the employees; its initial structure was developed by an employee team; issues are identified by staff members and teams are formed by those who feel thay can make a contribution to the effort.
The concern for quality extends beyond the Company itself. Total Quality Excellence includes suppliers as well as U.l.C.C. employees. In fact, U.l.C.C. provides a TOE education program for vendors' personnel. Again, the focus is on the customer - the improvement of products and services in any and all ways possible.
A Living Process
TOE is a flexible, living process that was created and has been nurtured by the people who are the Company. It is an expression of their drive to be the best.
And for U.l.C.C. customers, it is an assurance of superior products; designed, made, sold and supported by people who care about them.
2-6
n n INTEGRATED
~ CIACUIT8
-uNITRDDE GENERAL INFORMATION
Quality
Process improvement has become an aggressive daily pursuit in manufacturing. Just meeting specification is no longer good enough. U.l.C.C.'s goal is to achieve a 6o process.
Simply; many benefits to the customer have been realized in the form of ontime-delivery, superior quality and unprecedented levels of sustained reliability. Organizationally, a ''total commitment" to quality has manifested itself in the form of:
· Improved customer satisfaction
· Improved designs
· Known process capabilities
· Increased yields
· Improved product flow
· Reduction in quality costs such as scrap and rework
· Prevention orientation and quality consciousness
· Reduction in operating costs
U.1.C.C.'s unique self-auditing approach makes certain quality ownership is an intrinsic part of the manufacturing community with no one faction having full responsibility. Documentation at U.l.C.C. has been developed to truly reflect a "Real Time" status through master matrixing and planning whereas design, fabrication, assembly and test and their many detailed process steps are tied together relationally.
Reliability assurance at U.l.C.C. has specific goals to demonstrate product reliability of the various functional families that make up this primarily bipolar product base. It is important to note the existence of feedback to design and process engineering that ensures all products receive continuing reviews, thus enhancing even the most mature family of products.
2-7
n n INTEGRATED
~CIRCUIT&
-UNITRCDE GENERAL INFORMATION Quality
QUALJQCI FLOW FOR JANB, 8838 MIL-STD-883 METHOD 5005
GROUP A ELECTRICALS -55°, +25°, +125°, +150"C
I
GROUPS SUBGROUP2 Resistance To Solvents SUBGROUP3 Solderability SUBGROUPS Bond Strength
I
GROUPC SUBGROUP1 Steady State Life End Point Electricals
Note: Unitrode Integrated Circuits also performs testing to source control drawings for Class S devices in accordance with MIL-STD-883
2-8
GROUPD
SUBGROUP1 Physical Dimensions
SUBGROUP2 Lead Integrity Seal (Fine And Gross)
SUBGROUP3 Thermal Shock Temperature Cycling Moisture Resistance Seal (Fine And Gross) Visual Examination End Point Electricals
SUBGROUP4 Mechanical Shock Vibration, Variable Frequency Constant Acceleration Seal (Fine And Gross) Visual Examination End Point Electricals
SUBGROUPS Salt Atmosphere Seal (Fine and Gross) Visual Examination
SUBGROUP& Internal Water Vapor Content
SUBGROUP7 Adhesion of Lead Finish
SUBGROUPS
Lid Torque
I
GROUPE RADIATION HARDNESS ASSURANCE
(WHEN APPLICABLE)
SUBGROUP1 Neutron Irradiation End Point Electricals
SUBGROUP2 Steady State Total Dosf! Irradiation End Point Electricals
SUBGROUP3 Transient Ionizing Irradiation End Point Electricals
n n L::::J INTEGRATED CIRCUITS
-uNITRDDE GENERAL INFORMATION
Quality
QUALIFICATION FLOW FOR COMMERCIAL - INDUSTRIAL DEVICES
Non-Hermetic
SUBGROUP 1 Group A Electricals -40°, 0°, +25°, +70°, +85° C, Visual Exam
l
SUBGROUP2 Humidity Life (85°C/85%RH) 1000 Hours Post Electricals
I
SUBGROUP3 Temperature Cycling (1000 Cycles) Post Electricals
l
SUBGROUP4 Thermal Shock (500 cycles) Post Electricals
I
SUBGROUPS Autoclave 96 Hours 2 Atmospheres Post Electricals
l
SUBGROUP& Electrostatic Sensitivity Discharge Post Electricals
Hermetic
SUBGROUP1 Group A Electricals -55°, +25°, +125°C, Visual Exam
l
SUBGROUP2 Thermal Shock (500 Cycles) Seal (Fine and Gross) Post Electricals External Visual
I
SUBGROUP3 Temperature Cycling (1000 Cycles) Seal (Fine and Gross) Post Electricals External Visual
l
SUBGROUP4 Steady State Life 1000 Hours
I
SUBGROUPS Constant Acceleration Seal (Fine and Gross) Post Electricals
l
SUBGROUP& Electrostatic Sensitivity Discharge
2-9
n n L::::J INTEGRATED CIRCUITS
-UNITRDDE GENERAL INFORMATION
Quality
Should failure occur either in the field or during the course of reliability testing, in-depth failure analysis is performed to identify and understand the failure rnechanism(s) involved. Immediate feedback to design or process for the purpose of corrective action is systematically accomplished.
Levels of long-term device reliability, through the accumulation of millions of hours of testing at accelerated temperatures have demonstrated 15 fit or lower failure rates within a functional family. With the ever-growing demand for greater system reliability, this is a major factor.
U.l.C.C. has planned and developed reliability goals for the decade of the 90's that realistically test the technology.
UNITRODE RELIABILITY ASSURANCE
RELIABILITY REPORTING: Failure Rates/Dev. Hours/Functional Families %/1000 Hours and FIT
FUNCTIONAL FAMILY: 1) Controllers 2) Drivers 3) Support Functions
Data Generation · Steady-State Life ·Temperature Cycling · 85/85 · Autoclave · High Temperature Storage· Herrneticity ·Thermal Shock· Mechanical Shock and Vibration ·
PINO· Device Specific Tests ·QuaVQCI
2-10
n n L:::::j
INTEGRATED CIRCUITS
-UNITRDDE
New Quality Products from U.1.C.C.
PULSE WIDTH MODULATORS
Part Number
UCC3570 UCC3802 UCC3803 UCC3804 UCC3805 UCC3806 UCC3810 UC3824 UC3828 UC3848 UCC3856 UCC3883 UCC3885
Description
Page Number
High Performance Voltage Mode PWM .......................... 5-312 High Frequency BICMOS PWM 3842 Type .................... 5-319 High Frequency BICMOS PWM 3842 Type .................... 5-319 High Frequency BICMOS PWM 3842 Type .................... 5-319 High Frequency BICMOS PWM 3842 Type .................... 5-319 High Frequency BICMOS PWM 3846 Type .................... 5-323 Dual BICMOS PWM ........................................................ 5-326 Complementary Output UC1825 ..................................... 5-127 Enhanced Current Mode PWM ....................................... 5-141 Average Current Mode PWM .......................................... 5-199 High Performance Current Mode PWM .......................... 5-229 ISDN Micro Power PWM ................................................. 5-327 ISDN Micro Power PWM ................................................. 5-337
Part Number
UC3866 UC3875
RESONANT CONTROLLERS
Description
Page Number
ZVS Resonant Controller ................................................ 5-245 Phase Shift Resonant PWM ............................................ 5-256
SPECIAL FUNCTION CIRCUITS
Part Number
UC3612 UC3852 UC3871 UC5661
Description
Page Number
Dual Schottky Diode Array ..................................... 5-111, 6-31 Electronic Ballast Power Factor ...................................... 5-213 Fluorescent Lamp Driver ................................................. 5-251 Ethernet Coaxial Impedance Monitor.............................. 7-101
Note: Only commercial part numbers are indicated· see military section for military versions
2·11
n nINTEGRATED
~CIRCUITS
-UNITRCDE
New Quality Products from U.1.C.C.
MOTOR CONTROLLERS/DRIVERS
Part Number
UC3173A UC31758 UC3178 UC3612 UC3726 UC3727
Description
Page Number
.45A Voice Coil Motor Driver..............................................6-79 .SA Voice Coil Motor Driver................................................6-89 .45A Voice Coil Motor Driver..............................................6-98 Dual Schottky Diode Array ..................................... 5-111, 6-31 IGBT Driver- Primary ........................................................7-44 IGBT Driver- Secondary....................................................7-49
Part Number
UC5171 UC5172 UC5601 UC5602 UC5603 UC5661
INTERFACE CIRCUITS
Description
Page Number
Modified Octal Single Ended Line Driver ...........................7-73 Enhanced Octal Single Line Driver....................................7-77 18 Line SCSl-2 Active Terminator .....................................7-87 Versatile 18 Line SCSI Active Terminator..........................7-91 9 Line SCSl-2 Active Terminator .......................................7-96 Ethernet Coaxial Impedance Monitor...............................7-101
Part Number
UC3724 UC3725 UC3726 UC3727
HIGH POWER DRIVERS
Description
Page Number
Isolated Drive Transmitter..................................................7-37 Isolated High Side Driver ...................................................7-40 IGBT Driver- Primary Side ................................................7-44 IGBT Driver- Secondary Side ...........................................7-49
2-12
n n L':=:'..J INTEGRATED CIRCUITS
-UNITRODE
New Quality Products from U.1.C.C.
POWER SUPPLY SUPPORT CIRCUITS
Part Number
UC19431 UC19432 UC2575 UC2576 UC2577 UC3612 UCC183-0,-3,-5 UC3854A UC3891 UC3904 UC3907
Description
Page Number
Shunt Precision Reg./Opto Driver....................................5-301 Versatile Shunt Precision Reg./Opto Driver.....................5-306 1A Fixed or Adjustable Buck Converter .................... 5-67, 5-73 3A Fixed or Adjustable Buck Converter .................... 5-80, 5-87 1A Fixed or Adjustable Boost Converter...................5-94, 5-99 Dual Schottky Diode Array ...................................... 5-111, 6-31 Low Drop Out CMOS Regulators .................................... 5-309 Enhanced UC3854 Power Factor .................................... 5-226 Two Stage Power Factor Converter ................................ 5-265 Enhanced Quad Output and Line Monitor ....................... 5-281 Load Sharing Controller ................................................... 5-286
2-13
n nINTEGRATED
~CIRCUITS
-UNITRODE
General Information
PACKAGE CROSS-REFERENCE CHART
·..;;:~
l · II ·
PLASTIC DIP CERAMIC DIP ~ULTIWATI PLCC LCC
SOIC
~ .
T0-3*
.
' I
1111, T0-220
UNITRODE
N
Linear Tech Cherry
N, N-8 N
SGS - Thompson Silicon General
B,N,P M,N,W
Texas Instruments Signetics National Motorola Fairchild
N, NT,NW, P N
N, N-8, N-14 N, P, P1, P2
T, p
Sprague Micro Linear
A,M,B p
Samsung
N
Philips
N
Seagate
N
Silicon ix
J, N
Teledyne
p
·consult factory for availability.
J J, J-8
J
--
J, y J, JG F, FE J, J-8, J-14 J, J-8, L, U D,R
R J J F J K,O J
v
Q,QP L D, DP, OW, DWP K
T
-- L
S,S-8
K
T
v
FN --
D,DW
--
T
v -- --
D
K
--
a
L
D,DW,DWW K
p
v
FN
FK
D, DB, OW
K KC,KV
A
G
D
-- u
v
y
E
M
K
T
FN --
D,DW
K
KC
a
L
s
K
u
EP EK,EL L, LB, LW
v
z
a
L
s
-- --
PL
L
A --
-- --
N,P --
L
N
D
M
T
D
-- --
D
K
T
y
-- --
0
--
--
2-14
n n C_j
INTEQRATliD CIRCUIT&
-UNITRODE
Die And Wafers
DESCRIPTION
Unitrode Integrated Circuits Corp., U.l.C.C., offers most of its products described in this data book in die and/or wafer form. Products include all Pulse Width Modulators (PWMs), Motor Controls, Low-Drop Regulators, fixed, and adjustable industry standard Voltage Regulators, Power Drivers and Switches, Active Terminators, and Special Function Circuits. Most U.l.C.C. products are designed with military temperature range operation capability.
U. I.C.C. die utilize linear bipolar technology featuring tight beta control and resistor matching techniques. Also, other enhancements used implement thin film resistor and Schottky process, as well as in-house epitaxial capability for unique voltage flexibility. All products are protected by CVD Oxide plus Nitride layers to make a sandwich passivation system that offers superior coverage over all junctions.
Die thicknesses vary by product type, however, they fall into the catagories; 12 mils± 1 mil, or 15 mils± 1 mil. Interconnects are an alloy of copper (2%) and aluminum (to reduce possibility of metal migration). Backside metallization is Titanium- Nickel - Silver, suitable with various common eutectic and thermal epoxy mount- down techniques used today.
TESTING
All products are tested at two separate points. 1) In-line probing and 2) Final test probing.
Final test probe utilizes state-of-the-art high speed/power ATE equipment Die are 100% tested to low power DC limits.
INSPECTION
U. l.C.C. performs visual inspections on military grade die to MIL-STD-750B, Method, 2072 and to MIL-STD-883C Method 2010, condition A or B, or to customer supplied requirements.
Die can be supplied in "waffle pack" or single wafer form. Standard wafers are 100 mils (generic 4 inch diameter).
ORDERING INFORMATION
PART NUMBER
UCXXXX: .c.tf.l.E WEB
CHIP O+RDER
~
WAFER+ORDER
UNITRODE INTEGRATED CIRCUITS
7 CONTINENTAL BLVD. · MERRIMACK. NH 03054 TEL (603) 424-2410 ·FAX (603) 424-3460
2-15
n n INTEGRATED
~CIRCUITS
-UNITROOE
2-16
Military/Aerospace Products
n n INTEGRATED
~CIRCUITS
-UNITRODE
n n INTEGRATED
~CIRCUITS
-UNITRODE
.. ----
..._,.
..,....,
---
_-==---
.........
Military/Aerospace Products Selection Guide
3-3
n n INTEGRATED
~CIRCUITS
-UNITRDDE
MILITARY/AEROSPACE PRODUCTS
U.l.C.C. has been committed to producing military/aerospace and high reliability products for several years and continues to support this key market segment. Our product offering includes: · STANDARD MILITARY DRAWING (SMD) - Conformance to Class B
process requirements per the SMD selected item drawings. · SCD-CLASS S - conformance to all Class S process requirements of
MIL-STD-883 and individual customer source control documents.
· SCD - CLASS B - Conformance to Class B process requirements of MIL-STD-883 and individual customer source control documents
· JAN-LEVEL B - full compliance to MIL-M-38510 JAN program and QPL listings as published by DESC.
U.l.C.C. has had DESC facility certification continuously since November 1985. This certification allows us to produce JAN Class B linear microcircuits for the military marketplace. U.l.C.C. has been a leader in producing linear ICs to customers' Class S specifications for the last several years. Our abilities in the area include all processing standards of Class S, as well as an extensive library of radiation data on our most popular devices. Our superior design support and customer service make us the be.st choice for customers with Class S requirements.
JAN PRODUCT LINE
Unitrode Integrated Circuits Corporation presently has DESC line certification to MIL-M-38510 to produce Jan Class B linear microcircuits. Unitrode is the originator of the 702 current mode PWM slash sheet (UC1846/UC1847) and in January of 1990 received JAN qualification.
In a continued effort to meet and produce the highest military grade devices, Unitrode Integrated Circuits reviews all existing slash sheets applicable to our product base in the effort to either add device types or develop new slash sheets for industry use.
Unitrode Integrated Circuits also has lab suitability to perform MIL-STD-883 method 5004 and 5005 screening/QUAUQCI issued by DESC, with the exception of internal water vapor content and vibration variable frequency. In addition we have full self-auditing programs to ensure compliance to all specifications. Our SPC program has enhanced the process of all product through continuous improvement teams whose purpose is to reduce variation in the process.
Unitrode Integrated Circuits is committed to producing military grade linear monolithic devices in full compliance to MIL-M-38510. MIL-STD-883, SMD and SCD requirements and at all times focusing on quality and reliability enhancements.
3-4
n nINTEGRATED
~CIRCUITS
-UNITRODE
Military/Aerospace Products
STANDARDIZED MILITARY DRAWINGS (SMDs) LISTING U.l.C.C. AS AN APPROVED SOURCE OF SUPPLY
"Consult factory for availability
117AH/883BC 117AIG/883BC 117AK/883BC 117G/883BC
117H/883BC 1171G/883BC 117K/883BC 117U883BC 137AG/883BC 137AH/883BC 137A31G/883BC 137AK/883BC 137G/883BC 137H/883BC 1371G/883BC 137K/883BC 150AK/883BC 150K/883BC 1834J/883BC 7805AG/883BC 7805AIG/883BC 7805AK/883BC 7812AG/883BC 7812AIG/883BC 7812AK/883BC 7815AG/883BC 7815AIG/883BC 7815AK/883BC
Positive Adjustable Reg. Positive Adjustable Reg. Positive Adjustable Reg. Positive Adjustable Reg. Positive Adjustable Reg. Positive Adjustable Reg. Positive Adjustable Reg. Positive Adjustable Reg. Negative Adjustable Reg. Negative Adjustable Reg. Negative Adjustable Reg. Negative Adjustable Reg. Negative Adjustable Reg. Negative Adjustable Reg. Negative Adjustable Reg. Negative Adjustable Reg. Positive Adjustable Reg. Positive Adjustable Reg. Low Dropout Regulator
Positive 5V Reg. Positive 5V Reg. Positive 5V Reg. Positive 12V Reg. Positive 12V Reg. Positive 12V Reg. Positive 15V Reg. Positive 15V Reg. Positive 15V Reg. 3-5
7703405XA 7703405UA 7703405YA 7703401TA 7703401XA 7703401UA 7703401YA 77034012A 7703406TA 7703406XA 7703406UA 7703406YA 7703403TA 7703403XA 7703403UA 7703403YA 5962-8767502XA 5962-8767501XA 5962-8774201 EA 5962-8778201TA 5962-8778201 UA 5962-8778201YA 5962-8777601TA 5962-8777601 UA 5962-8777601YA 5962-8855301TA 5962-8855301 UA 5962-8855301 YA
n n LL:::::Jj
INTEGRATED CIRCUIT&
-UNITRODE
Military/Aerospace Products
STANDARDIZED MILITARY DRAWINGS (SMDs) LISTING U.1.C.C. AS AN APPROVED SOURCE OF SUPPLY (Cont'd)
'Consult factory for availability
7905AG/883BC 7905AIG/883BC 7905AK/883BC 7912AG/883BC 7912AIG/883BC 7912AK/883BC 7915AG/883BC 7915AIG/883BC 7915AK/883BC
1823J/883B 1823U883B 1524J/883B 1524AJ/883BC 1525AJ/883BC 1527AJ/883BC 1525AJ/883BC 1527AJ/883BC 1526AJ/883BC 1526AJ/883BC 1825J/883BC 1825U883BC 1842J/883BC 1843J/883BC 1844J/883BC 1845J/883BC 1846J/883BC 1847J/883BC
Negative 5V Reg. Negative 5V Reg. Negative 5V Reg. Negative 12V Reg. Negative 12V Reg. Negative 12V Reg. Negative 15V Reg. Negative 15V Reg. Negative 15V Reg. High Speed PWM High Speed PWM
PWM PWM PWM PWM PWM PWM PWM PWM High Speed PWM High Speed PWM Current Mode PWM Current Mode PWM Current Mode PWM Current Mode PWM Current Mode PWM Current Mode PWM
5962-8874601TA 5962-8874601 UA 5962-8874601YA 5962-8874701TA 5962-8874701 UA 5962-8874701YA 5962-8874801TA 5962-8874801 UA 5962-8874801YA 5962-8990501 EA 5962-89905012A
7802801EA 5962-8764502EA 5962-8951103EA 5962-8951104EA 5962-8951101EA 5962-8951102EA
8551502VA 8551501VA 5962-8768101 EA 5962-87681012A 5962-8670401 PA 5962-8670402PA 5962-8670403PA 5962-8670404PA 5962-8680601 EA 5962-8680602EA
3-6
n n INTEGRATED
~CIRCUITS
-UNITRODE
Military/Aerospace Products
STANDARDIZED MILITARY DRAWINGS (SMDs) LISTING UJ.C.C.
-AS AN APPROVED SOURCE OF SUPPLY (Cont'd)
1543J/883BC
Power Supply Supervisory
1544J/883BC
Power Supply Supervisory
1903J/883BC
Quad Supply+ Line Monitor
1903U883BC
Quad Supply+ Line Monitor
L293DSP/883B
4-Channel Driver
1706J/883BC
Dual Output Driver
1707J/883BC
Dual Channel Power Driver
195H/883BC
Smart Power Transistor
195K/883BC
Smart Power Transistor
1611 J/883BC
Quad Schottky Array
1633J/883
Brushless DC Motor Cont.
1625J/883
Phase Lock Controller
1637J/883BC
PWM DC Servo Control
1838AJ/883B
Magnetic Amplifier Circuit
1864J/883
Resonant Mode Cont.
1901J/883B
lso. Feedback Generator
5962-8774001 EA 5962-8774002VA 5962-8869701 VA 5962-88697012A 5962-9235001 MEA 5962-8961101 EA 5962-8761901 EA 5962-8777801 XA 5962-8777801 XA 5962-8995701 EA 5962-9168901 MEX 5962-9098701 MEX 5962-8995701VA 5962-8989901 MEA 5962-9203101 MEX 5962-8944101 CA
3-7
n nINTEGRATED
~CIRCUITS
-UNITRODE
Military/Aerospace Products
PACKAGE AVAILABILITY
·consult factory
NOTES: 1. This data is Junction to Tab 2. Junction to Bottom Plate 3. With finned heat sink 4. Junction to top plate
T0-257 Isolated
T0-5
Ceramic OIL 8-pin 14-Pin 16-Pin 18-Pin
Side-Brazed Power 16-pin
24-pin
T0-3
Ceramic Leadless Chip Carrier (CLCC)
3.7(2) 20
40 30 30 30
5 TBD 3(2)6 (4) 15
NIA 130
130 80 80 75
65 45(3) TBD 35
70
3-8
n n INTEGRATED
~CIRCUITS
-UNITRODE
Military/Aerospace Products
Military Die Capability
Unitrode's military product offering includes all catalog circuits in unencapsulated form. Unencapsulated (chips) are supplied screened to MIL-STD-883B, method 2010, conditional A or B. Product is electrically tested at ambient room temperature. Shipment of this product is in individual waffle packs or as complete wafers.
Radiation Tolerant Products
Unitrode recognizes the increasing market demand for radiation tolerant and radiation hardened high reliability products. Because of this, we - in conjunction with customers - have characterized our key products. Full radiation data reports are available on the following products.
UC1524A UC1526 UC1526A UC1825 UC1842 UC1843 UC1844 UC1845
UC7805 UC7905
UC1711 UC1707
UC1834 UC1835/36
Below is a summary of radiation data U.l.C.C. has collected:
ll!!i re :le Bi >o h!.!J t!!_lsol
}
l!I
Process
i~o
Iii ~ti' i·II'·'
~~
UC1707J
2.9E12
2.0E5
UC1711J
1E13
8.77E9
UC1825J
4E5
3E12
UC1834J
1E6
UC1836J
6E4
UC1840J
1.7E10
UC1842J
1.7E10
UC1845J
1E6
UC3825N
3E5
UC7805K
2E13
UC7815K
2E13
UC7905K
1E6
Note: Radiation levels represented are from independent customer test results.
3-9
n n INTEGRATED
~CIRCUITS
-UNITRODE
3-10
Autamati11e Products
n n INTEGRATED
~CIRCUITS
-UNITRODE
4-2
n nINTEGRATED
~CIRCUITS
-UNITRODE
Autamati11e Products
4-3
n nINTEGRATED
~CIRCUIT&
-UNITRDDE
Automotive Products
A Dedication to Automotive Customers
Unitrode Integrated Circuits is a leader in innovative analog circuits that meet the needs of advanced automotive applications. The circuits presented in this section are used in numerous automobile applications including: systems multiplexing, electric vehicles, HID lighting, Instrumentation, motor controls, fuel management and airbag systems.
Unitrode is committed to the rigorous requirements of automotive customers.
Utilizing a Total Quality Management (TQM) program based on the Baldridge
model, maximum customer satisfaction is achieved. The TQM program includes
-'"--M«ilAIJ~llemcgntinuous improvement teams. These teams are empowered to champion the p~and. ·to make changes which will enhance any facet of the
operation. In on.:i~r t?~re TOM techniques are employed by our vendors,
Unitrode established Unit University. Unitrode University is an important
element which enables the
e TOM culture to be transferred to our vendor
base. As a result of our q ·
Quality we have recently received IS0-9000
J<ft:!lifi~cat·iOll~nit·rodfrexceeds you ,~ality expectations.
. '\
\.
'
dvanced Technologies order to maintain our leadership
posi\tio~~e
have
a
team
of
dedicated
process
velopment engineers who are w~o e latest technologies. Unitrode
very proud of ou~~nt pro
velopment, Direct Wafer
Deueloped'm conjunction with o la as our partner, Direct
Wafer Bonding will enable us to offer prod · t · ing junction isolation.
This will increase speed, power capabilities and . gra densities. Technologies like bt~ Wafer Bonding will enable U ode t be a leader in the
automotive ma~,
'\ Packaging
'~\
\,
\.
JJnilrode offers a complet ·
foPtiC s include conventional
ineOoafndau6t0o0mmotiilvtehrpoaucgh'g~oele
"'~ration as well as the latest s ace mount solutions~
\includ pl
ower leadles .hip carrier (PLCC) n
·~all
e (
~
~r
aged automotiv ~re~
s. Packaging -line configuount options 0 and300 mil are supplied to rees C to +105
\
4-4
n n INTEGRATED
~CIRCUIT&
-UNITRDDE
-Automotive Products
Power Management
UC2842,3,4,5
· Low start~yp currenr ''
·_J)ptfrTli;~ for offline and DC to
_. /' DC converters
.,
_,.~, ~~. 'i"
· ~~~~a~:~~.~~rward
· Pu~e-by-pulse curtf!ntllrnttth-g""'
~.
'
t
'%.
1
......\..\~-,~1:~:,
uc~~46
Current Mode PWM Controller
\ · Programmables~ulse-by-Pulse
current limiting '\ ,,.,,'-~
· Automatic symmet~clrrecitq_n in
push-pull configuratidf
\
t
· Enhanced load respon{;e
h t
characteristics
1,
t
· Parallel operation capatliiity
"t
UCC2802,3,4,5 Low Power BiCMOS (Current Mode) PWM
· 1OOµA typical starting supply current
· 500µA typical operating supply · Internal soft start · Internal leading edge blanking of
the current sense signal
output
UC2852 High Power-Factor Preregulator
· Low cost power factor correction · Power factor >.99 · Few external parts required · Zero current switching
~...........·.···
'·'·'·'·'·'·'·._.,···,·,·,·,-.·,·,·,·,-.·,·,·,·,·,·,·,·,·,·,-.·,·, ·,·,·,·,·,·.-.·~.-.-,..................................w.·.-.·.-.·.·,·,·,-.·,·,·.·.-.·.....·.·.·,·,·,·~.·.-.·.-.·.·,-.·,-.·,·.-.·.·,·.-.·.-.~
·tw
UC2854 High Power-Factor Preregulator
· Control boost PWM to .99 power factor
· Limit line current distortion to <5%
· World-wide operation without switches
· Feed forward line regulation
For more information on these products, refer to detailed data sheets. 4-5
n nINTECIRATED
~CIRCUITS
-UNITRDDE
Automotive Products
Power Management
~
UCC2806
Low Power BICMOS PWM
..... .. ·,·.v.....·.·~················-·.·.v.- ~ ·-~ ··················..·::
UC2575 Step-Down Voltage Regulator
· 5V output, ±3% max over line and load conditions
· Guaranteed 1A output current · Voltage range 7V to 40V · 4 external components required · 2.5V precision reference
Easy Switcher 1 Amp Step
Down Volt"a' ~ Regulator
'\.
· Adjustable oilif,>ut, reference
voltage ± 2% rfi@x ov~e and
load co.nditions
'\ ·~.
t I
'\ ~
· Wide input and out~ volta ·
range
1
· Low power standby lq typically <200 µA
· Efficiency typically o
Motor Control
L293
Push-Pull 4-Channel Driver
· Output current 1A per channel ··Peak output current 2A per
switchmode channel · Inhibit facility · High noise immunity
For more information on these products, refer to detailed
data sheets.
4-6
\, ';
u1tci\ ~-x
't
'%,
Low Drop C\)ut 3A~ositive
Re~lator ' \
· Precisio~\>o.sitive s pass
voltage r~ulation
· 0.45V Dro~~u
·Drop out un
·.·.·.·.·.·········-·.·.·.·.·.·,·.·.·.·.·.·.··,·.·.··.·.·.·.·.·.·.·.·.·,·.·.·.·.·.·.·.·.·····-·.·.·.·.·.·.·······-·. ·.·.·.·.·.·.·.·····-::
I UC2611
Quad Schottky Diode Array
· Matched, 4-diode monolithic array · High peak current
· Low forward voltage
ItiI¥
n n INTEGRATED
~CIRCUIT&
-uNITRODE Automotive Products
Motor Control
UC2637
Switched Mode Controller for DC Motor Driy:~
· Single ofdual supply operation <t Pulse-by-pulse current limiting
UC2625
Brushless DC Motor Controller
· Drives power MOSFETS or power Darlingtons directly
· SOV open collector high side drivers
· Latched soft start
Stepper
Driver/Special Fun~ti
UC2722
Five-Channel Programmable Current Switch
· Five current-sinking switches · Peak current-sinking switches · Internal current sensing
For more information on these products, refer to detailed data sheets.
4-7
UC2730
Thermal Monitor
· On-chip temperature transducer · Temperature comparator gives
threshold temperature alarm · Precision 2.SV power reference
n nINTEGRATED
~CIRCUITS
-UNITROCE Automotive Products
Driver/Special Function
UC2704 Bridge Transducer Switch
· Dual matchedcumml sources · Hrgh gain differential sensing '' circuit · Wide COmq1on-mode input
capability · Externally programmable time
UC2705 High Speed Power Driver
· 1.5A source/sink drive · 100 nsec delay · 40 nsec rise and fall into 1OOOpF · Inverting and non-inverting inputs
UC2707
Dual ChanneN>ower Driver
· Two independ11nt drivers
· 1.sA totem pole o.utputs · · 40nsec rise and fall J~to 1OOOpF
· High speed, power MOSFET':
Compatible
·
UC2708, Dual Non-Inverting Povver Driver
· 3.0A peak current tot&m pole outputs
· 5 to 35V oparatiim , · Wide 25 nsec'Rise a~ Fall times
UC2709 Dual High-Speed FET Driver
· 1.5A source/sink drive · Pin compatible with 0026 products · 40nsec rise and fall into 1OOOpF · Low quiescent current
For more information on these products, refer to detailed data sheets. 4-8
UC2710 High Current FET Driver
· Totem pole output with 5A source/sink drive
· 35nsec delay · 25nsec rise and fall time into
2.2 nF · 85nsec rise and fall time into 30nF
n n INTEGRATED
L:::::J CIRCUIT&
-UNITROOE
Automotive Products
Driver/Special F unction
......................................,....tW......,.,..............v.......v.v.·.v.·.-.·.v.v.·.·...·................................................,.,.................................................. ............................·~
UC2724
111·:
Isolated Drive Tra_nsmitter
ll!ll]i
· soomA output gove,,souroErOF'"'·"·" .......
s~~~ "" ,_, ,_.,~·'
.
.!"'·s to 35V operation
· rranslhits.(ogic signal instantly
i
"<«:.,,
· Rrogrammabl~'operating
freq~ency
\ ·\
··.-.·.=·_.,.......,.......,.,.,·..,.......,.,.·.,......·.-.w.-.·.v.·.-.·.-.-.v.-.·.-.·_.,.,.......,.............,.......................,........-......,.··,··.,.,.,._.··,.,.,.,··.,.,.,.,·.....·.-.-.·...·.-.·.-.·.-.···...·.-.·.·.-.~
'
UC2725
Isolated High Side FET Driver
· Receives both power and signal across the isolation boundary
· 9 to 1SV high level gate drive guaranteed
· Under-voltage lockout · Output enable function
'\ ·~.-·.· · · · ·.·,·,·.-.·.·.·.·,·...·.·.-.·,·,·....................................................'.{.......·.·.-.·.·.·.l..
\"·'*', U02726
! °"<=»
<'!~ ,,-:::;;«
@,t:" 0"
~\"""=».
~ ;h'"' ':>"W·'»'·. ;_:(. ·'.".-.·~~). -~."_· .-" \ ' ...>..O·.·<.···.'·v.,·.·,-.·,.··.·v.··...........,........".-.·:<"='= ~· ..
' ··· ····."_·. ;·,-· ···························· ...........(;4., r·"·'·\·.·t.,. ~:·~..................................................~ ~
U~7
Isolated Driv~1transmitter
Isolated High ~de IG 1° Driver
· 750mA outpuf'Q[ive, source or
r .,\ sink
'4
· 8 to 35V operation\\.
.~
§,
· Receives Pi;>wer and signal from
single iso · n transfo~er
· Generates
f' f
· · peak
· Transmits logic signaf'fistantl~;
bipolar gate
· Programmable operati~g
· 16V high level
frequency
\
· Complete drive and control circuitry for lamp and LCD
· Zero voltage switched topology · Open lamp protection circuitry · 4.SV to 20V operation
For more information on these products, refer to detailed data sheets. 4-9
n nINTEGRATED
~CIRCUITS
-UNITRODE
4-10
i \ I ~U~~ Indicates Application Nate Available
~ _ ~ See Section 9.
Power Supply Circuits
n .n L:::'..J
INTEGRATED CIRCUITS
-UNITRCDE
5-2
n nINTEGRATED
~CIRCUITS
-UNITRODE
Power Supply Controls PWM Performance Chart
SWITCHING REGULATOR CONTROL ICs
L
VOLTAGE MODE PWMs
Note: Most series available screened to /8838 Rev. C PERFORMANCE CHARACTERISTICS
Regulating
PW Ms
UC 1524/2524/3524
x
x x 100mA 300KHz
16 Pin N, J, *
Advanced Regulating PWMs UC 1524A/2524A/3524A
x x x x x 200mA x SOOKHz
x
16 Pin N, J, *
Advanced Regulating PWMs UC 1525A/2525A/3525A UC1527A/2527A/3527A
x x x x
100mA 0.4A
x Pulse
500KHz
x x x
16 Pin N, J, *
Regulating PW Ms UC 152612526/3526
x x x x x x 100mA 400KHz
xxx x
18 Pin N, J, *
Advanced Regulating PWMs UC 1526A/2526A/3526A
x x x x x x 100mA 550KHz
xxx x
18 Pin N, J, *
High Frequency PWM Controllers UC1823/2823/3823 UC1825/2825/3825
x x x x x x x x x x
500mA
x 1.5A
x xxx
Pulse
x 2MHz
x x x
x x x x 16 Pin N, J, *
Regulating
PW Ms
UC494
x
200mA
x 300KHz
x x
16PinN,J
Advanced Regulating PWMs UC494A/UC494C UC495A/UC495AC
x
x
200mA
x 300KHz
x x
16PinN,J 18 Pin N, J
Programmable Primary Side PWMs UC1840/2840/3840
x x x x x x 200mA X 500KHz
x
x x x N/A
18 Pin N, J,*
Note 1: All Current Mode Control ICs can be used in "Voltage Mode" Also; Consult Current Mode PWM Selection Guide.
. Note 2: N = Plastic Package J = Ceramic Package
=Surface Mount Available, Consult Factory
5-3
n nINTEGRATED
~CIRCUITS
-UNITRODE
Power Supply Controls
PWM Performance Chart
SWITCHING REGULATOR CONTROL ICs (Cont'd)
Note: Most series available screened to /8838 Rev. C
VOLTAGE MODE PWMs
Programmable Primary Side PWMs UC184112841 /3841
Advanced Programmable, Off-Line PWM UC1851/3851
X X X X X X 200mA X 500KHz X X X X X X 200mA X 500KHz
x
X X NIA X 18 Pin N, J,*
x x X X NIA X 18 Pin N,J,*
Power Supply Control Systems· UC285013850
x X X X X X 50mA
200KHz X
xx x
24 Pin N, J, *
Enhanced Voltage Mode UCC3570 (BICMOS)
X X X X X X 500mA X 500KHz
X X X X X NIA X 14Pin N, J, D
Note 1: All Current Mode Control ICs can be used in "Voltage Mode" Also; Consult Current Mode PWM Selection Guide. Note 2: N = Plastic Package
J =Ceramic Package
=* Surface Mount Available, Consult Factory
5-4
n n L:::::::!J
INTEGRATED CIRCUITS
-uNITRODE
Power Supply Controls PWM Performance Chart
SWITCHING REGULATOR CONTROL ICs
z
CURRENT MODE PWMs
Note: Most series available screened to /883B Rev. C PERFORMANCE CHARACTERISTICS
BICMOS High Frequency
PWM Controllers UCC180212802/3802
UCC180312803/3803 UCC180412804/3804
ucc 18051280513805
x x x x x
500mA
1.0A
x Pulse
1MHz
x x
x x x 8 Pin N, J, 0 *
BICMOS High Frequency
PWM Controllers
ucc 18061280613806
500mA 1.0A
x x x x x x Pulse x 1MHz x
x x x x x 16 Pin N, J, OW
Dual BICMOS Current Mode UC181012810/3810
x x x x x
x 1MHz
x (2)X
x x x 16 Pin N, J, OW
High Frequency PWM Controllers UC 182312823/3823 UC18251282513825
x x x x x x x x x x
500mA
x 1.5A
x xxx
Pulse
x 2MHz
x x x
16 Pin N, J, *
x x x x
High Frequency PWM Controllers UC 1823A/2823A/3823A UC1825A/2825A/3825A
x x x x x x x x x x x x
500mA
x 1.5A
x xx
Pulse
x 2MHz
x x x
x x x x 16 Pin N, J, *
Complementary Output PWM Controllers UC 182412824/3824
500mA 1.5A
x x x x x x Pulse x
x
x x x x x x 16 Pin N, J, OW
Programmable Primary Side PWMs UC184012840/3840
x x x x x x 200mA X 500KHz
x
x x x NIA
16 Pin N, J, *
Programmable Primary Side PWMs UC184112841/3841
x x x x x x 200mA X 500KHz
x
x x x NIA
18 Pin N, J, *
Economy Primary SidePWMs UC 1842/2842/3842 UC 18431284313843 UC 184412844/3844 UC184512845/3845
100mA
1A
x xxx
Pulse X 500KHz
x
x x NIA
8 Pin N, J, *
Note: N = Plastic Package J = Ceramic Package *=Surface Mount Available, Consult Factory 5-5
n n INTEGRATED
~CIRCUITS
-UNITRODE
Power Supply Controls
PWM Performance Chart
SWITCHING REGULATOR CONTROL ICs (Cont'd)
z
Note: Most series available screened to /8836 Rev. C PERFORMANCE CHARACTERISTICS
CURRENT MODE PW Ms
Economy Primary SidePWMs UC1842A/2842A/3842A UC1843A/2843A/3843A UC1844A/2844A/3844A UC1845A/2845A/3845A
100mA
x xxx
1A
Pulse X 500KHz
x
x
NIA X 8 Pin N, J, *
Current Mode PWM Controllers UC18461284613846 UC18471284713847
X X X X X X 200mA X 500KHz
X X X X X X 16 Pin N,J, *
Average Current Mode PWM UC18481284813848
Advanced Programmable, Off-line PWM UC185113851
Advanced High Performance PWM UC 18561285613856
x x x x x
500mA 2.0A Pulse
1MHz
x x X X X X 16 Pin N, J, DW
X X X X X X 200mA X 500KHz
x x X X NIA X 18 Pin N, J, *
500mA 1.5A
X X X X X X X Pulse
1MHz X
x x x
x
16 Pin N, J, DW
Note: N =Plastic Package J = Ceramic Package *=Surface Mount Available, Consult Factory
5-6
n n L::::J INTEGRATED CIRCUIT&
-UNITRODE
Power Supply Controls CURRENT MODE CONTROL IC APPLICATION GUIDE
UCC1800 UCC1801 UCC1802 UCC1803 UCC1804 UCC1805 UCC1806 UCC1810 UC1823 UC1823A UC1823B UC1824 UC1825 UC1825A UC1825B UC1828 UC1840 UC1841 UC1842 UC1842A UC1843 UC1843A UC1844 UC1844A Note: Most series available screened to /8838 Rev. C
5-7
n n l=:J INTEGRATED CIRCUITS
-UNITRDDE
Power Supply Controls
Current Mode Application Guide CURRENT MODE CONTROL IC APPLICATION GUIDE (Cont'd)
UC1845 UC1845A UC1846 UC1847 UC1848 UC1849 UC1851 UC1852 UC1854 UC1854A UC1855 UC1856 UC1871 UC1875 UC1876 UC1877 UC1878 UCC1883 UCC1885 UCC1891 UCC1892 UCC1893 UCC1894
Note: Most series available SCl8ened to 18838 Rev. C 5-8
n n INTEGRATED
~CIRCUITS
-UNITROOE
Power Supply Controls RESONANT MODE CONTROLLERS
DEVICE UC1824 UC1852 UC1855 UC1860 UC1861 UC1862 UC1863 UC1864 UC1865 UC1866 UC1867 UC1868 UC1875 UC1876 UC1877 UC1878 Note: Most series available screened to /8838 Rev. C
5-9
n nINTEGRATED
~CIRCUITS
-UNITROCE
Power Supply Controls POWER FACTOR CORRECTION ICs
UC1852 UC1854 UC1854A UC1855 UC1891 UC1892 UC1893 UC1894 1 can be obtained
LOW CURRENT BICMOS CONTROLLERS
UCC1800 UCC1801 UCC1802 UCC1803 UCC1804 UCC1805 UCC1806 UCC1810 UCC1883 UCC1885
1 can be obtained
5-10
n n LL::::::J_j
INTEGRATED CIRCUITS
-UNITRODE
Power Supply Controls
POWER SUPPLY SUPPORT FUNCTIONS
./ r(. ····
········
Two Stage Power Factor Converter
==
= =
· Single Chip Solution For Power Factor Corrected
Power Systems
· World Wide Voltage Operation Without Switches
· Fixed Frequency PWM Drive for Both Pre and
Post Regulators
· Low Offset Analog Multiplier/Divider
Enhanced Quad Supply and Line Monitor
· Inputs for Monitoring up to Four Supply Voltages · Two Inputs Preset for -5V and -12V Monitoring,
or Programmable Positive Levels · Precision 2.5V Reference · Separate Inputs for Over-Current and Line Fault
Sensing
Dual Schottky Diode Array
· Monolithic Two Diode Array · Exceptional Efficiency · Low Forward Voltage · High Peak Current (3A) ·Small Size
Shunt Precision Reg./Opto Driver
· Multiple On-Chip Programmable Reference Voltages · 0.4% Initial Accuracy · 1.0% Overall Ref. Tolerance · 2.2V to 36V Operating Supply Voltage and User
Programmable Reference ·Known Linear Transconductance@ 5%Tolerance
Precision Analog Reg./Opto Driver
· Programmable Transconductance for Optimum Current Drive
· Accessible 1.3V Precision Reference · Both Error Amplifier Inputs Available · 0.4% Initial Accuracy · 1.0% Overall Reference Tolerance · 2.2V to 36.0V Operating Supply Voltage · Reference Accuracy Maintained for Entire Range of
Supply Voltage · Superior Accuracy and Easier Compensation for
Opto-lsolator Application · Low Quiescent Current (0.55mA Typ.)
Load Share Controller
· Fully Differential High Performance Voltage Sensing · Accurate Current Amplifier for Precise Current
Sharing · Opto Coupler Driving Capability · 1.25% Trimmed Reference
EZSwitcher
· 1A Fixed or Adjustable Step Down Converter · Up to 60V Input · High Efficiency · Pin Compatible with LM2575
28 Pin PLCC or
24 Pin OIL
18 Pin DIL or
20 Pin SO-IC
8 Pin SO-IC (Power PKG)
or 8 Pin DIL
8 Pin DIL or
8 Pin SO-IC
8 Pin DIL or
8 Pin SO-IC
16 Pin DIL or
16 Pin SO-IC or
20 Pin PLCC 5 Pin T0-220
5-11
n nINTEGRATED
~CIRCUITS
-UNITRDDE Product Selection Guide
POWER SUPPLY SUPPORT FUNCTIONS
EZ Switcher
EZ Switcher
Low Dropout 3A Positive Linear Regulator
Enhanced UC3854 Power Factor Controller
· Same Features as UC2575 · 3AOutput · Pin Compatible with LM2576
· 1A Fixed or Adjustable Step Up Converter · Up to GOV Input · High Efficiency · Pin Compatible with LM2577
· Drop Out < 0.6V@ 3A · Drop Out <2mV@ 1OmA · Quiescent current < 250µA Irrespective of Load · Adjustable (5 Lead) Output Voltage Version · Fixed (3 Lead) Version @ 2.85V, 3.3V and 5V · Protection Features
· Controls Boost PWM to Near Unity Power Factor · Limits Line Current Distortion to < 3% · Accurate Power Limiting · Enhanced Multiplier Improvements · High Bandwidth (5 MHz) Low Offset Current
Amplifier · Faster/Improved Accuracy 'Enable Comparator'
5 Pin T0-220
5 Pin T0-220
5 Pin T0-220 or
3 Pin T0-220
16PinDIL or
16 Pin SO-IC or
20 Pin PLCC
5-12
n n INTEGRATEC
~CIRCUITS
-uNITRODE
Power Supply Controls
PRODUCT APPLICATIONS CIRCUITS
· Matched, Four Diode Monolithic Array · High Peak Current · Low Cost MINIDIP Package · Low Forward Voltage · Parallelable for Lower VF or Higher VF · Fast Recovery Time · Military Temperature Range Available
Any Analog to Digital monitoring system; coupled with any of a wide range of sensors almost
any type of physical phenomena may be monitored. Samples:
·Air-Flow Sensor Circuits · Liquid or Gas Flow Circuits · Passing Object Circuits
"IC Circuitry that results in optimized charge cycles for specific battery applications." · Uninterruptable Power Supplies · Portable Electrical Equipment · Emergency Power and Light Systems · Volatile Data Handling Computers-Power Back-Up
By combining a temperature monitor and heater, this IC permits airflow velocity past the IC package to be monitored. · On-Chip Temperature Transducer · Temperature Comparator Gives Threshold Temp-Airflow Alarm · Low 2.5mA Quiescent Current
· Can Function as a General-purpose Low-power Controller · Fully Synchronizing Oscillator · Synchronization to Secondary Side Logic · Leading Edge Blanking of Current Sense · 50% Maximum Duty Cycle · Undervoltage Lockout · Programmable Low Line Sensing · Programmable Softstart · Programmable Fault/Restart Delay ISDN FEATURES · Zero-power Startup Capability · Restricted Mode Detection · Frequency Agile PWM in Restricted Mode · Precision Programmable Quiescent Current · Very Low Quiescent Power for CCITI 25mW Restricted Mode · Accurate, Programmable Input Power Limit or Input Current Limit
·Wide Operating Range ·Fully Synchronized Oscillator ·Temperature Stable Oscillator ·Logic Level Synchronization Input · Precision Reference ·Error Amplifier for Loop Regulation and Compensation · Undervoltage Lockout ISDN FEATURES ·Low Line Logic Output ·Restricted Mode Logic Output ·Precision Programmable Quiescent Current ·Very Low Quiescent Power for CCITI 25mW Restricted Mode
5-13
n nINTEGRATED
~CIRCUITS
-UNITROOE
5-14
n n INTEGRATED
~CIRCUITS
-UNITRCDE
Micropower Quad Comparator
UC161A UC161B UC161C
FEATURES Programmable Output Drive Capability Direct CMOS Logic Compatibility Low Power Direct Wire-OR of Outputs Wide Input Common Mode Range
CONNECTION DIAGRAM DIL-16 (TOP VIEW) N or J Package
DESCRIPTION
The UC161 family of quad comparators feature programmable DC and AC parameters. A single external resistor can set the comparators to operate in the microwatt region for battery applications, or higher current levels can be set to obtain improved speed or drive capabilities. The outputs on these devices can be wire OR'd together, simplifying external logic requirements in some applications.
These devices are available in three temperature ranges, the UC161A is specified for the full military range, -55° C to +125°C, the UC161 B for the industrial range, -25°C to +85°C, and the UC161 C for the commercial range of 0°C to +70°C.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (+V to -V) . . . Differential Input Voltage . . . .
. . . . . . . . . . . . . . . . . . 36V . . . . . . . . . . . . . . . . . . ±30V
Input Voltage . . . . . . . . . .
. . . . . . . . . . . . . -V-0.3V to +V
Power Dissipation at TA = 25°C
= Power Dissipation at Tc 25°C
. . . . . . . . . . . . . . . 1000 mW . . . . . . . . . . . . . . . 2000 mW
Operating Junction Temperature . . . . . . . . . . . . . . . -55°C to+150°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . -65°C to +15o·c Lead Temperature (Soldering, 10 Sec.) . . . . . . . . . . . . . . . . +300°C
Note: Consult Packaging Section of Databook for thermal limitations and considerations ofpackage.
SIMPLIFIED SCHEMATIC ONE COMPARATOR OUTPUT
,---------,
+V
BIAS NETWORK (COMMON TO
I ~i: RSET
ALL FOUR
?.
COMPARATORS) I I (EXTERNAL)
.--~~~~_,_,ii SET
(-) (+) ( ~--+---+--------<---+--~
6/93
L_ _ _ _ _ _ _ _ _J
5-15
UC161A UC161B UC161C
ELECTRICAL CHARACTERISTICS: Temperature range is -55°to+125°C for the UC161A, -25°C to +85°C for the
uc161 B, and o·c to +1o·c tor the uc161 c.
LOW POWER ELECTRICAL CHARACTERISTICS: Unless Otherwise Stated: Vs= ±3V, 1sd = 1OµA, R2=10MQ,
CL= 10pF, TA= 25°C, TA= TJ.
PARAMETER
SYMBOL TEST CONDITIONS
!5 Input Offset Voltage
D. Input Offset Current ;\!!; l~ut Bias Current
!5
§
DC Open Loop Voltage Gain
Low Output Voltage1
High OutputVoltage1
I
Common Mode Range Response lime CommonModeRejection
Ratio
~ PowerSupplyRejection
D. Ratio D.
:::> Supplpurrent
fl)
Vos los IB'f AVOL
VOL RL=20kQ VoH AL =200kQ CMR
t 1OOmV Overdrive, CL= 1OpF CMRR VIN =CMR
PSRR
Is AlllnputsGrounded,RL = oo
UC161A
MIN TVP MAX
1
3
1
20
20 100
20 30
UC161B/C
MIN i"VP MAX
1
6
1
25
20 200
10 30
UNITS
mV nA nA V/mV
-2.95 -2.6
-2.95 -2.6 v
2.5 2.9
2.5 2.9
v
+1.3/-3
+1.3/-3
v
5
5
~
75 90
75 90
dB
65 80
65 80
dB
210 300
210 300 µA
Input Offset Voltage DC Open Loop Voltage Gain Supply Current
Vos
AVOL
10
Is All Inputs Grounded, AL = oo
TA = Over Temperature Range
5
mV
5
V/mV
350
350 µA
HIGH POWER ELECTRICAL CHARACTERISTICS: Unless Otherwise Stated: Vs= ±15V, lsd = 100µA, AL =2MQ,
CL= 10pF, TA= 25°C, TA= TJ.
PARAMETER
SYMBOL TEST CONDITIONS
UC161A
UC161B/C
UNITS
MIN TYP MAX MIN TVP MAX
I- Input Offset VoltaJl_e
Vos
:::>
D. Input Offset Current
los
;\!!; l~ut Bias Current
IB'f
1.5
3
5
60
100 400
1.5
6
mV
5
90 nA
100 800 nA
!5 DC Open Loop
D. Voltage Gain
:I::-> Low Output Voltage1 0 High O~ut Voltage1
AVOL
VOL AL =20kQ VoH AL =200kQ
50 100
30 100
V/mV
-14.9 -14.6
v -14.9 -14.6
14.5 14.9
14.5 14.9
v
0 Common Mode Range CMR
j Response lime
t 1OOmV Overdrive,
<z (
CL= 10pF
i5 Common Mode
CMRR VIN=CMR
Rejection Ratio
+13/-15 1
+13/-15
v
1
J.IS
75
90
75
90
dB
~ Power Supply
D.
D:::>.
fl)
Rejection Ratio Supply Current
PSRR
65 80
65
80
dB
Is All Inputs Grounded, AL = oo
2100 3500
2100 3500 µA
Note 1: The output current drive of the UC161 Is non-symmetrical. This facilitates the wlre-ORing of two comparator outputs. The outputpull-down cu"ent capability is typically 75-150 times the pull-up cu"ent.
Note 2: Set current (lsET) and supply current (/SUPPLY) can be determined by the following formulas:
/SET· ((+V) - (~VBE) - (-V)] : {SUPPLY· 21 X {SET.
SET
5-16
UC161A UC161B UC161C
HIGH POWER ELECTRICAL CHARACTERISTICS (Continued): TA= TJ.
TA= Over Temperature Range
PARAMETER
Input Offset Voltage Input Bias Current DC Open Loop Voltage Gain Supply Current
SYMBOL TEST CONDITIONS
Vos IBT AVOL
Is All Inputs Grounded AL= oo
UC161A
MIN TYP MAX 6 500
25
UC161B/C
UNITS
MIN TYP MAX
mV
nA
15
V/mV
4000
4000 !AA
Note 1: The output current drive of the UC161 is non-symmetrical. This facilitates the wlre-DRing of two comparator outputs. The output pull-down current capability is typically 75--150 times the pull-up current.
Note 2: Set current (/SET) and supply current (/SUPPLY) can be determined by the following formulas:
/SET- [(+\I) - (~VBE) - (-\I)) : /SUPPLY- 21 x /SET.
SET
APPLICATION AND OPERATION INFORMATION DESCRIPTION
The UC161 is a monolithic quad micropower comparator with an external control for varying its AC and DC characteristics. The variation of a single programming resistor will simultaneously alter parameters such as supply current, input bias, current slew rate, output drive capability, and gain. By making this resistor large, operation at very small supply current levels and power dissipations is possible. The UC161 is therefore ideal for systems requiring minimum power drain, such as battery-powered instrumentation, aerospace systems, CMOS designs, and remote security systems.
SETTING THE SET CURRENT
The set current can be expressed as:
/SET= [(+\/)- (2VBE)-(-\I)] RsET
where +V is the voltage to which the control resistor is connected, -V is the negative supply voltage, VBE is the base emitter drop of 09 or 010 (about 0.7V), and RsET is the value of the external control resistor or set resistor. Equation 1 is simply a derivative of ohms law. There is also an analytical relationship between ISET and the total supply current:
The circuit (see Simplified Schematic) is composed of five major blocks-four comparators and a common bias net-
work. 01-0s, and 01 from a darlington differential ampli-
fier with double-to-single ended conversion. Os is a dual current source whose outputs are exactly twice the current flowing through Os. The collector current of Os is a function of the current supplied externally to 09-010, which in turn is known as the set current of ISET. This set current is established by a resistor connected between the ISET terminal and a voltage source, most commonly the positive supply. 011 prevents excessive current from flowing through 09 and 010 in the event the lsET terminal is shorted to the positive supply; it has no effect on circuit operation under normal conditions.
/SUPPLY= [/SET (current sourced by 06 to Qs)
+2 /SET (current sourced to the differential
amplifier by 06)
+2 /SET (current sourced to the comparator output by 06)
x 4 {the total number of comparators)
+/SET (current sourced through Q11, Q10, and Q9 to-V)
= [/SET+ 2 /SET+ 2 /sE'lj x 4 + /SET
= 21 /SET
The output current pulldown capability (loL) of the UC161 is about 2 orders of magnitude greater than the high output drive current, (loH), which allows wire-ORing the outputs. loH is simply the current sourced by Os:
/OH= 2x lsET
IOL is found by multiplying the current sourced by the collector of Os by the gain 07:
/OL = (3 (Q7) X 2 /SET
The beta of 01 is about 75-150.
5-17
APPLICATION AND OPERATION INFORMATION (Continued) Input Bias Current vs Supply Current
100 i=i=mi:im=oo
UC161A UC161B UC161C
0.1 ~~~~~~~~~=
1
10 100 1K 10K
ISU'PLv - SUPPLY CURRENT ( µA)
Transfer Characteristics
15 v~v ~ t1~v 1
10 H TA = 25"C
v k"
~ :
y
IL
_L
~ -5
lL
-10
IL
-15
-200 100 0 100 200
\AN -DIFFERENTIAL (µ V)
t2 ts
tlO
tl5
Vs-SUPPLY VOLTAGE (VOLTS)
Slew Rate vs Supply Current
200
10
180
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. · MERRIMACK; NH 03054 TEL (603) 424-2410 · FAX (603)-424·3460
5-18
n n ~CIRICNTUEIGTRSATEC
,.i~
~
..
- UNITROOE
Advanced Regulating Pulse Width Modulators
~
UC494A/AC UC495A/AC
FEATURES Dual Uncommitted 40V, 200mA Output Transistors
1% Accurate 5V Reference
Dual Error Amplifiers
Wide Range, Variable Deadtime
Single-ended or Push-pull Operation
Under-voltage Lockout With Hysteresis
Double Pulse Protection
Master or Slave Oscillator Operation
UC495A: Internal 39V Zener Diode
UC495A: Buffered Steering Control
DESCRIPTION
This entire series of PWM modulators each provide a complete pulse width modulation system in a single monolithic integrated circuit. These devices include a 5V reference accurate to ±1 %, two independent amplifiers usable for both voltage and current sensing, an externally synchronizable oscillator with its linear ramp generator, and two uncommitted transistor output switches. These two outputs may be operated either in parallel for singleended operation or alternating for push-pull applications with an externally controlled dead-band. These units are internally protected against doublepulsing of a single output or from extraneous output signals when the input supply voltage is below minimum.
The UC495A contains an on-chip 39V zener diode for high-voltage applications where Vee would be greater than 40V, and a buffered output steering control that overrides the internal control of the pulse steering flip-flop.
The UC494A is packaged in a 16-pin DIP, while the UC495A is packaged in an 18 pin DIP. The UC494A, UC495A are specified for operation over the full military temperature range of -55°C to +125°C, while the UC494AC, UC495AC are designed for industrial applications from 0°C to +70°C.
BLOCK DIAGRAM
OUTPUT CONTROL
j (UC495A)
(SEE FUNCTION TABLE)
jSrE'ERitiG______
01
I CONTROL
C1
L-------
E1
C2
E2
FUNCTION TABLE
Output Control Connected to:
Ground
VREF
Output Function
Single-Ended or Parallel Operation
Push-Pull Alternating Outputs
UC495A
NON INV. INPUT----t·'INV. INPUT-------
ERROR AMPLIFIERS NON INV. INPUT----r·'INV. INPUT --1
PWM COMPARATOR
r---
1
I 39V REFERENCE
I
REGULATOR
I 3K I
I
I
IL_v!._JI
(UC495A)
Steering Control (Output Control
at VREF)
Output Function
Vs < 0.4V
PWM Output at 01
Vee
Vs > 2.4V
PWM Output at 02
REF our
6/93
5-19
UC494A/AC UC495A/AC
ABSOLUTE MAXIMUM RATINGS (Note 1, 2, 3)
Supply Voltage, Vee (Note 2) ........................ 45V Amplifier Input Voltages ...................... Vee + 0.3V Collector Output Voltage ........................... 41 V Collector Output Current. . . . . . . . . . . . . . . . . . . . . . . . . 250mA Continuous Total Dissipation .................... 1OOOmW
@(or below) 25°C free air temperature range (Note 3) Storage Temperature Range ............... -65° to +150°C Lead Temperature 1/16" (1.6mm) from case for 60 seconds,
J Package ................................... 300°C Lead Temperature 1/16" (1.6mm) from case for 10 seconds,
N Package .. . . . . . . . . . . . . . .. . . . . . .. . . . . . . . . .. 260°C Note 1: Over operating free air temperature range unless
otherwise noted. Note 2: All voltage values are with respect to network
ground terminal 3. Note 3: Consult Packaging Section of Databook regarding
thermal specifications and /imitations ofpackages.
RECOMMENDED OPERATING CONDITIONS
Supply Voltage Vee . . . . . . . . . . . . . . . . . . . . . . . . . . 7V to 40V Error Amplifier Input Voltages . . . . . . . . . . . . . -0.3V to Vee-2V Collector Output Voltage ........................... 40V Collector Output Current (each transistor). . . . . . . . . . . 200mA Current into Feedback Terminal. ................... 0.3mA Timing Capacitor, CT ................. 0.47nFto 10,000nF Timing Resistor, RT . . . . . . . . . . . . . . . . . . . . . 1.8kQ to 500kQ Oscillator Frequency . . . . . . . . . . . . . . . . . . . . 1kHz to 300kHz Operating Free Air Temperature
UC494A, UC495A .................... -55°C to+125°C UC494AC, UC495AC. . . . . . . . . . . . . . . . . . . . 0°C to +70°C
CONNECTION DIAGRAMS
DIL-18 (TOP VIEW) J or N Package
ERROR AMP
NON-INV INPUT 1
INV INPUT 2
COMPEN/PWM COMP INPUT DEAD TIME CONTROL 4
UC494A/AC
DIL-18 (TOP VIEW) J or N Package
ERROR AMP
gg::~~~(!uv.tM 3 i-:,-.,...,...,~
DEAD TIME CONTROL 4
UC495A/AC
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, over recommended operating free-air temperature range,
Vee= 15V, f= 10kHz, TA=TJ.
PARAMETER Reference Section
Ou.!E_ut Vol~e VREF li:!E_ut R~ulation
O~ut ~ulation
Output Voltage Over TemJ>_erature
TEST CONDITIONS
lo= 1mA, TA= 25°C Vee = 7V to 40V lo= 1mA to 10mA iffA =Min. to Max.
MIN TVP MAX UNITS
4.95
5
5.05
v
2
25 mV
1
15 mV
4.90
5.10 v
Short Circuit Output Current
VREF = 0, TA= 25°C__lNote 1)
Oscillator Section
Frequen~Note ~
CT= 0.01-.!!:f, RT= 12kQ
Standard Deviation Of Fr~uen9'_(Note 3) Ail Values of Vee, CT, RT, TA Constant
Frequen~Chan_g_e With Volt~
Vee= 7V to 40V, TA= 25°C
Fr~uen9'_Chan_g_e With Tem~rature
CT= 0.01-.l!:f, RT= 12kQ, ATA =Min. to Max.
Deadtime Control Section__lOutJ>_ut Control Connected to VREF)
10
35
50 mA
10
kHz
10
%
0.1
%
2
%
Input Bias Currentj!'in 4) Maximum Duty-Cycle (Each Output)
V(PIN 4) = OV to 5.25V
V(PIN4) = ov
-2
-10 ~
45
%
5-20
UC494A/AC UC495A/AC
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, over recommended operating free-air temperature range,
- Vcc-15V f--10kHz TA--TJ
PARAMETER
TEST CONDITION
MIN TYP MAX UNITS
Deadtime Control Section~ont.:110u.!2_ut Control Connected to VRE!l_
Input Threshold Voltage (Pin 4)
Zero Dl!!}'::qy_cle
Maximum DU_!y:qy_cle
3
3.3
v
0
v
Am_.!!ifler Section
11!2.ut Offset VoltaJl_e
Vo (PIN 3) = 2.5V
2
10 mV
11!2.ut Offset Current
Vo (PIN 3) =2.5V
25 250 nA
11!2.Ut Bias Current Common-Mode Input Voltage Range
Vo (PIN 3) = 2.5V Vee = 7V to 40V
-0.2 -1
!IA
.03to
v
Vcc-2
qii_en LoOI>_Volta_ge Gain
/'No= 3V, Vo= 0.5V to 3.5 V
70
95
dB
Ul!_i!y_Gain Bandwidth
800
kHz
Common-Mode RE!i_ection Ratio
Vee = 40V, TA= 25°C
65
80
dB
01.ltj>_ut Sink CurrentJPin 3}_ Output Source CurrentjPin 3}_
VID = -15mV to -5V, V(PIN 3) = 0.7V VID = 15mV to 5V, V(PIN 3) = 3.5V
0.3 0.7
mA
-2
mA
Output Section
Collector Off-State Current Emitter Off-State Current
I Collector - Emitter lcommon-Emltter
Saturation Voltage Emitter-Follower Ou~ut Control l~t Current
VcE = 40V, Vee = 40V Vee= Ve = 40V, VE = 0 VE = 0, le = 200mA Ve= 15V, IE= -200mA VI =VREF
2 100 !IA
-100 !IA
1.1
1.3
v
1.5 2.5
v
3.5 mA
PWM Com__e_arator Section
l~t Threshold Voltl!9_ejPin 3}_
Zero Duty-qy_cle
4
4.5
v
11!2.ut Sink CurrentJPin 3}_
V(PIN3) = 0.7V
Steerl'!i_Contro1J_UC495A, See Function Tabl~
Input Current
V(PIN 13) = 0.4V, Q1 ACTIVE
V(PIN 13) = 2.4V, O:!ACTIVE
0.3 0.7
mA
-200 ~ 300 µA
Deadband
500
mV
Zener Diode Circuit1UC495A)_ Breakdown Voltag_e
Vee= 45V, lz = 2mA
36
39
45
v
Sink Current
V(PIN 15) = 1V
0.2 0.3 0.6 mA
Total Device Standby Supply Current
Under Vol~e Lockout
1 Pin 6 at VREF, All other inputs and
Vee= 15V
6
10 mA
outputs open
j VCC=40V
9
15 mA
3.5
6.5 v
~teresis
300
mV
Switchi'!ll Characteristics_IT_A = 25°Q)_
01.ltj>_ut Volta_g_e Rise Time 01.ltj>_ut Voltajj_e Fall Time
Common-Emitter Confi_g_uration AL= 680, CL= 1~
100 200 ns 25 100 ns
01.ltj>_ut VoltaJl_e Rise Time
Emitter-Follower Configuration
100 200 ns
Output Voltage Fall Time
AL= 680, CL=15pF
40 100 ns
Note 1: Duration of the short circuit should not exceed one second.
Note 2: Frequency for other values of Cr and RT;s approximately t- R~
Note 3: Standard deviation is a measure of the statistical distribution about the mean as derived from the formula:
5-21
VAEF 12
Vee n - - - - - - - - - - -
UC494A/AC UC495A/AC
----<1VAEF
12
RT
Voe Slave
(Addltlonal
circuits)
Figure 1. Slaving Two or More Control Circuits
TO REMAINDER OF ERROR AMPLIFIER CIRCUIT
TO REMAINDER OF ERROR AMPLIFIER CIRCUIT
TO COMPENSATION/PWM . i . - - - - - - - - 0 COMPARATOR INPUT
(PIN 3)
~O.ElmA
Figure 2. Output Circuit of Error Amplifiers
OUTPUT CONTROL
C1
(:o soomA
GND OR A VOLTAGE UP TO 0.4V
E2 SINGLE · ENDED CONFIGURATION
TIE TO VREF OR A VOLTAGE AS LOW AS 2.4V
OUTPUT CONTROL
(to C1
~
01
E1
250mA
02
cC2
to 250mA
~--..{)
E2
PUSH - PULL CONFIGURATION
Figure 3. Output Connections for Single-Ended and Push-Pull Configurations
OND
Figure 4. Internal Buffer with Deadband for Steerin Control on UC495A
Vo
TO OUTPUT
VOLTA.GE OF
SYSTEM
R1
Rs
12
VIN >40V-",A1~~....- - - - - < ' > - - - - l - I - -....--_.,.
Vee 39V
15
IC
SUPPLY
Vz
GND
7
VOLTAGE 3K
GND
Figure 5. Operation with VIN > 40V Using Internal Zener
R2
R2
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. ·MERRIMACK, NH 03054 TEL. (603) 424-2410 · FAX (603) 424·3460
POSITIVE OUTPUT VOLT AGE
Vo·V""' (1+~)
NEGATIVE OUTPUT VOLTAGE
R1
Vo·VIEF (1+~)
Vo
Figure 6. Error Amplifier Sensing Techniques
TO OUTPUT VOLTAGE OF SYSTEM
5-22
n n L:::::j
INTEIJRATED CIRCUITS
-UNITRODE
Advanced Regulating Pulse Width Modulators
UC1524 UC2524 UC3524
FEATURES Complete PWM Power Control Circuitry
Uncommitted Outputs for Single-ended or Push-pull Applications
Low Standby Current. .. BmA Typical
Interchangeable with SG1524, SG2524 and SG3524, Respectively
DESCRIPTION
The UC1524, UC2524 and UC3524 incorporate on a single monolithic chip all the functions required for the construction of regulating power supplies, inverters or switching regulators. They can also be used as the control element for high-power-output applications. The UC1524 family was designed for switching regulators of either polarity, transformer-coupled de-to-de converters, transformerless voltage doublers and polarity converter applications employing fixed-frequency, pulse-width modulation techniques. The .dual alternating outputs allow either single-ended or push-pull applications. Each device includes an on-chip reference, error amplifier, programmable oscillator, pulse-steering flip-flop, two uncommitted output transistors, a high-gain comparator, and current-limiting and shut-down circuitry. The UC1524 is characterized for operation over the full military temperature range of -55°C to +125°C. The UC2524 and UC3524 are designed for operation from -25°C
to +as·c and o· to +70°C, respectively.
CONNECTION DIAGRAM
BLOCK DIAGRAM
5
INV NON OSC (+) (-) RT
INPUT INV OUT C.L. C.L.
INPUT
SENSE
CT GND
VREF
16
REFERENCE
+5V to all
VIN 15il---O------l REGULATOR 1----+--1nternal circuitry
+SV RT 6 ! - - - - - - - - - ' - - - - ,
CT 71----------L-~---'
(RAMP)
Ca
c
Ea
ERROR AMP
_J, GROUND@.
(Substrate) -
COMPENSATION
6/93 5-23
UC1524 UC2524 UC3524
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA= -55°C to
+125°C for the UC1524, -25°C to +85°C for the UC2524, and o·c to +70°C for the UC3524, VIN = 20V, and f = 20kHz, TA:TJ.
PARAMETER
TEST CONDITIONS
Reference Section
Output Voltage
Line Regulation
VIN= 8 to 40V
Load Regulation
IL= Oto 20mA
Ripple Rejection
t = 120Hz, TJ = 25°C
Short Circuit Current Limit
VREF = 0, TJ = 25°C
Temperature Stability
Over Operating Temperature Range
Long Term Stability
TJ = 125·c, t = 1000 Hrs.
Osclllator Section
Maximum Frequency
CT= .001mfd, RT= 2kQ
Initial Accura<'.}'_
RT and Cr Constant
Voltage Stability
VIN = 8 to 40V, TJ = 25°C
Temperature Stabll!!i
Over Operating Temperature Range
Output Amplitude
Pin 3, TJ = 25°C
Output Pulse Width
CT= .01 mfd, TJ = 25°C
Error Ampllfler Section
Input Offset Voltage
VeM=2.5V
Input Bias Current
VeM=2.5V
Open Loop Volta~ Gain
Common Mode Voltage
TJ=25°C
Common Mode Rejection Ratio TJ=25°c
Small Signal Bandwidth
Av= OdB, TJ = 25°C
Output Voltage
TJ=25°C
Comparator Section
Duty-Cycle
% Each Output On
Input Threshold
Zero Duty-Cycle
Maximum Duty-Cycle
Input Bias Current
Current Limiting Section
Sense Voltage
Pin 9 = 2V with Error Amplifier Set for Maximum Out, TJ = 25°C
Sense Voltage T.C.
Common Mode Voltage
Output Section (Each Output)
Collector-Emitter Voltage
Collector Leakage Current
VCE=40V
Saturation Voltage
le=50mA
Emitter Output Voltage
VIN =20V
Rise Time
Re= 2k ohm, TJ = 25°C
Fall Time
Re= 2k ohm, TJ = 25°C
Total Standby Current
VIN=40V
(Excluding oscillator charging current, error and current limit dividers, and with outputs open)
UC1524/UC2524 MIN TVP MAX
4.8 5.0 5.2
10 20
20
50
66
100
0.3
1
20
300 5 1 5 3.5 0.5
0.5
5
2
10
72 80
1.8
3.4
70
3
0.5
3.8
0
45
1
3.5
1
190 200 210
0.2
-1
+1
40
0.1
50
1
2
17 18
0.2
0.1
8
10
UC3524
UNITS
MIN TVP MAX
4.6 5.0 5.4
v
10 30 mV
20 50 mV
66
dB
100
mA
0.3
1
%
20
mV
300
kHz
5
%
1
%
5
%
3.5
v
0.5
µs
2
10 mV
2
10 µA
60
80
dB
1.8
3.4
v
70
dB
3
MHz
0.5
3.8
v
0
45
%
1
v
3.5
v
1
µA
180 200 220 mV
0.2
mvrc
-1
+1
v
40
v
0.1
50
µA
1
2
v
17
18
v
0.2
µs
0.1
µs
8
10 mA
5-24
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage, Vee (Notes 2 and 3) .................. 40V Collector Output Current. . . . . . . . . . . . . . . . . . . . . . . . . 1OOmA Reference Output Current . . . . . . . . . . . . . . . . . . . . . . . . 50mA Current Through CT Terminal ....................... -5mA
Power Dissipation at TA= +25°C (Note 4) .......... 1000mW Power Dissipation at Tc= +25°C (Note 4) .......... 2000mW
Operating Junction Temperature Range ..... -55°C to +150°C Storage Temperature Range .............. -65°C to +150°C
Note 1: Over operating free-air temperature range unless otherwise noted.
Note 2: All voltage values are with respect to the ground terminal, pin 8.
Note 3: The reference regulator may be bypassed for operation from a fixed 5V supply by connecting the Vee and reference output pins both to the supply voltage. In this configuration the maximum supply voltage is 6\1.
Note 4: Consult packaging section of databook for thermal limitations and considerations of package.
UC1524 UC2524 UC3524
RECOMMENDED OPERATING CONDITIONS
Supply Voltage, Vee . . . . . . . . . . . . . . . . . . . . . . . . . 8V to 40V Reference Output Current ..................... Oto 20mA Current through CT Terminal ............. -0.03mA to -2mA Timing Resistor, RT . . . . . . . . . . . . . . . . . . . . . 1.8kQ to 100kQ Timing Capacitor, CT ................... 0.001µFto 0.1µF Operating Ambient Temperature Range
uc1524 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°c uc2524 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25°c to +85°C
UC3524 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . o·c to +1o·c
TYPICAL CHARACTERISTICS
Open-Loop Voltage Amplification
of Error Amplifier vs Frequency
! 90
~
<
~
80 70
60
RF=
J]I[ ll!lJ
RF·1MO
rnmr nnn
v111 -2ov TJ·25'C
~ 50 RF·300k0
!!j 40 RF=100k0 N
~ :~ RF=30k0
J.ILJll~Js~A Ce FROM ~
9 TO GROlN:l
&~ -~ ~& I~ OF R BELOW 30K WU ~~~°ITtfil~
100 1k
10k 100k 1M 10M
FREQUENCY (Hz)
Oscillator Frequency vs
Timing Components
t.1
~
~> 100K
cuc. 10K
VN · 20V
IS
TJ · 2s·c
bd t-1 !'O..onw_.:.
Cn
·Ooa.
bd
'IS I:in:diw.c-
;:p'.SJ..,
b,.
!5
I<-
:uJ 1K
"0 '
~c~ ,w_n.:..;.
~
100 1
2
5 10 20
50 100
TIMING RESISTOR - R T (kn)
Output Dead Time vs Timing Capacitance Value
10r==+:=+:=H=H++i==f=-...,-----,-"''r:i:l' r---+--+--+-+-+-++++---+- v111 -2ov '
<ii"
r---+--+--+-+--+-++++---+- TJ =25" C
.;:, 4 f---+----1--+-+++H+--+-+-+-+-H+I
~
I-
~
A.r n1nw_ l l lllil NOTE: DEAD TM:-eLAlll<NG PULSE WIDTH
0.1
0.001
0.004 0.01
0.04 0.1
Cr- CAPACITANCE (OF)
5-25
Output Saturation Voltage vs Load Current
3·5 f----'v.-cc---2-0-'-v--+---+----1 3.0 f----+---+--+---+----1
2.5 r----+---+--r---+--"""
2.0 f---+---+--
1.5
1.0
.5
0
0
20 40 60
80 100
LOAD CURRENT (mA)
UC1524 UC2524 UC3524
PRINCIPLES OF OPERATION
The UC1524 is a fixed-frequency pulse-width-modulation voltage regulator control circuit. The regulator operates at a frequency that is programmed by one timing resistor (RT), and one timing capacitor (CT), RT establishes a constant charging current for CT. This results in a linear voltage ramp at CT, which is fed to the comparator providing linear control of the output pulse width by the error amplifier. The UC1524 contains an on-board 5V regulator that serves as a reference as well as powering the UC1524's internal control circuitry and is also useful in supplying external support functions. This reference voltage is lowered externally by a resistor divider to provide a reference within the common-mode range of the error amplifier or an external reference may be used. The power supply output is sensed by a second resistor divider network to generate a feedback signal to the error amplifier. The amplifier output voltage is then compared to the linear voltage ramp at CT. The resulting modulated pulse out of the
high-gain comparator is then steered to the appropriate output pass transistor (01 or 02) by the pulse-steering flip-flop, which is synchronously toggled by the oscillator output. The oscillator output pulse also serves as a blanking pulse to assure both outputs are never on simultaneously during the transition times. The width of the blanking pulse is controlled by the valve of CT. The outputs may be applied in a push-pull configuration in which their frequency is half that of the base oscillator, or paralleled for single-ended applications in which the frequency is equal to that of the oscillator. The output of the error amplifier shares a common input to the comparator with the current limiting and shutdown circuitry and can be overridden by signals from either of these inputs. This common point is also available externally and may be employed to control the gain of, or to compensate, the error amplifier or to provide additional control to the regulator.
TYPICAL APPLICATIONS DATA
Oscillator
The oscillator controls the frequency of the uc1524 and is
programmed by RT and CT according to the approximate formula:
,_ 1.18 RrCr
mum duty cycle by clamping the output of the error amplifier. This can easily be done with the circuit below:
VREF
Comp
where RT is in kilohms CT is in microfarads f is in kilohertz
Practical values of CT fall between 0.001 and 0.1 microfarad. Practical values of RT fall between 1.8 and 100 kilohms. This results in a frequency range typically from 120 hertz to 500 kilohertz.
Blanking
Gnd
Synchronous Operation
When an external clock is desired, a clock pulse of approximately 3V can be applied directly to the oscillator output terminal. The impedance to ground at this point is approximately 2 kilohms. In this configuration RT CT must be selected for a clock period slightly greater than that of the external clock.
The output pulse of the oscillator is used as a blanking pulse at the output. This pulse width is controlled by the value of CT. If small values of CT are required for frequency control, the oscillator output pulse width may still be increased by applying a shunt capacitance of up to 1OOpF from pin 3 to ground. If still greater dead-time is required, it should be accomplished by limiting the maxi-
If two or more UC1524 regulators are to operated synchro-
nously, all oscillator output terminals should be tied together, all CT terminals connected to single timing capacitor, and the timing resistor connected to a single RT, terminal. The other RT terminals can be left open or shorted to VREF. Minimum lead lengths should be used between the CT terminals.
5-26
Single-Ended LC Switching Regulator Circuit
V+
+28V<>-~~-t-~~~~--~~~-+....-.
UC1524 UC2524 UC3524
82CM -
Push Pull Transformer Coupled Circuit
V+
+2BV0-~~-1-~~~~~-.-~~~~....-~~~~,
Open Loop Test Circuit
VIN
B-40V
0.1
R1 C1
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD.· l.ERRIMACK, NH 08054 TEL 003-424-2410 · FAX603-424-3460
UC1524 2k
5-27
CURRENT
LMT
n n L:::::!_j
INTEGRATED CIRCUITS
-UNITRCDE
Advanced Regulating Pulse Width Modulators
UC1524A UC2524A UC3524A
FEATURES
DESCRIPTION
Fully Interchangeable with Standard UC1524 Family
Precision Reference Internally Trimmed to ±1%
High-Performance Current Limit Function
The UC1524A family of regulating PWM ICs has been designed to retain the same highly versatile architecture of the industry standard UC1524 (SG1524) while offering substantial improvements to many of its limitations. The UC1524A is pin compatible with "non-A" models and in most existing applications can be directly interchanged with no effect on power supply performance. Using the UC1524A, however, frees the designer from many concerns which typically had required additional circuitry to solve.
Under-Voltage Lockout with Hysteretic Turn-on
Start-Up Supply Current Less Than 4mA
Output Current to 200mA
The UC1524A includes a precise 5V reference trimmed to ±1 % accuracy, eliminating the need for potentiometer adjustments; an error amplifier with an input range which includes 5V, eliminating the need for a reference divider; a current sense amplifier useful in either the ground or power supply output lines; and a pair of 60V, 200mA uncommitted transistor switches which greatly enhance output versatility.
60V Output Capability
Wide Common-Mode Input Range for both Error and Current Limit Amplifiers
PWM Latch Insures Single Pulse per Period
Double Pulse Suppression Logic
200ns Shutdown through PWM Latch
An additional feature of the UC1524A is an under-voltage lockout circuit which disables all the internal circuitry, except the reference, until the input voltage has
risen to av. This holds standby current low until turn-on, greatly simplifying the
design of low power, off-line supplies. The turn-on circuit has approximately 600mV of hysteresis for jitter-free activation.
Other product enhancements included in the UC1524A's design include a PWM latch which insures freedom from multiple pulsing within a period, even in noisy environments, logic to eliminate double pulsing on a single output, a 200ns external shutdown capability, and automatic thermal protection from excessive chip temperature. The oscillator circuit of the UC1 524A is usable beyond 500kHz and is now easier to synchronize with an external clock pulse.
Guaranteed Frequency Accuracy
Thermal Shutdown Protection
The UC1524A is packaged in a hermetic 16-pin DIP and is rated for operation from -55°C to +125°C. The UC2524A and 3524A are available in either ceramic or plastic packages and are rated for operation from -25°C to +85°C and 0°c to 10°C, respectively. Surface mount devices are also available.
BLOCK DIAGRAM
+5V
V1N 15 > - - - - - - - - - - - - - - - - < RReefgeurelantcoer l - - - - - - - - f 1 6 VREF
Power to
Internal Circuitry
EA
6/93
Inv. Input 1)---1 N.I. Input
CL (+) CL (-)
Ce Ee
5.5V Gnd
5-28
UC1524A UC2524A UC3524A
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VIN) ............................... 40V Collector Supply Voltage (Ve) ....................... 60V Output Current (each Output) ..................... 200mA Maximum Forced Voltage (Pin 9, 10). . . . . . . . . . . . . -3 to +5V Maximum Forced Current (Pin 9, 10) ............... ±1 OmA Reference Output Current . . . . . . . . . . . . . . . . . . . . . . . . 50mA Oscillator Charging Current . . . . . . . . . . . . . . . . . . . . . . . . 5mA Power Dissipation at TA= +25°C ................. 1ooomw
Power Dissipation at Tc =+25°C ................. 2000mW
Operating Temperature Range ............ -55°C to +125°C Storage Temperature Range .............. -65°C to+150°C Lead Temperature, (Soldering, 10 seconds) ......... +300°C Note: Consult packaging section of Databook for thermal limitations and considerations ofpackage.
DIL-16, SOIC-16 (TOP VIEW) J or N Package, DW Package
Inv Input 1 Non-Inv Input 2
OSCISync 3 C.L. (+) Sense 4 C.L. (-) Sense 5
+SV VREF
Emitter B Collector B
CONNECTION DIAGRAMS
PLCC-20, LCC-20 (TOP VIEW)
Q or L Package
PACKAGE PIN FUNCTION
FUNCTION
PIN
N/C
1
Inv. l~ut
2
L3 2 1 2019
Non-Inv. l~ut
3
4
18
OSC/SYNC
4
C.L._(+) sense
5
5
17
N/C
6
6
16
C.L.J:l. sense
7
7
150
RT
8
8
14p
9 10 11 12 13
Cr
9
~~
Ground
10
N/C
11
Com_.e.ensation
12
Shutdown
13
Emitter A
14
Collector A
15
N/C
16
Collector B
17
Emitter B
18
+VIN
19
+5VVREF
20
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA= -55°C to +125°C for the UC1524A, -25° to +85°C for the UC2524A, and o·c to + 10°c for the UC3524A; V1N
=Ve= 20V, TA= TJ.
PARAMETER
TEST CONDITIONS
UC1524A I UC2524A
UC3524A
UNITS
MIN TVP MAX MIN TVP MAX
Tum-on Characteristics Input Voltage Tum-on Threshold
Operating Range after Tum-on
8
40
8
40 v
6.5 7.5 8.5 6.5 7.5 8.5
v
Tum-on Current
VIN =6V
2.5
4
2.5
4
mA
Ciperatil]l_ Current Tum-on Hysteresis*
VIN =8to40V
5
10
0.5
5
10 mA
0.5
v
Reference Section Output Voltage
TJ=25°C Over Operatirig_Range
v 4.95 5.00 5.05 4.90 5.00 5.10
4.9
5.1 4.85
5.15 v
Line Regulation
VIN= 10 to 40V
10 20
10 30 mV
Load R~ulation
IL=Oto20mA
20 25
20 35 mV
Temperature Stability*
Over Operating Range*
20 25
20 35 mV
Short Circuit Current
VREF = 0, 25°C :5TJ"125°C
80 100
80 100 mA
Output Noise Voltage*
10Hz :sf :s 10kHz, TJ =25°C
40
40
µVrms
Long Term Stability*
TJ =125°C, 1000 Hrs.
20 50
20 50 mV
,. These parameters are guaranteed by design but not 100% tested in production.
5-29
UC1524A UC2524A UC3524A
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA= -55°C to +125°C for the UC1524A, -25° to +85°C for the UC2524A, and o·c to+ 10°c for the UC3524A; V1N
=Ve= 20V, TA= TJ.
PARAMETER
TEST CONDITIONS
UC1524A I UC2524A
UC3524A
UNITS
MIN TYP MAX MIN TYP MAX
Oscillator Section (Unless otherwise specified, RT = 2700Q, CT = 0.01 mfd)
Initial Accuracy
TJ= 25°C
41
43
45
39
43
47 kHz
Over Operating Range
40.2
45.9 38.2
47.9 kHz
Temperature Stability*
Over Operating Temperature Range
1
2
1
2
%
Minimum Frequency
RT= 150kQ, CT= 0.1mfd
140
120 Hz
Maximum Frequency Output Amplitude*
RT = 2.0kQ, CT = 470pF
500
500
kHz
3
3.5
3
3.5
v
Output Pulse Width* Ramp Peak Ramp Valley
TJ = 25°C
0.29 0.5 1.0 0.3 0.5 1.0 flS
3.3 3.5 3.7 3.3 3.5 3.7
v
0.7 0.8 0.9 0.7 0.8 0.9
v
Ramp Valley T.C.
-1.0
-1.0
mVfC
Error Amplifier Section (Unless otherwise specified, VeM = 2.5V)
Input Offset Voltage
0.5
5
2
10 mV
ln_e_ut Bias Current
1
5
1
10 µA
Input Offset Current
.05
1
0.5
1
µA
Common Mode Rejection Ratio VeM = 1.5 to 5.5V
70
80
70
80
dB
Power Supply Rejection Ratio VIN= 10to 40V Output Swing (Note 1)
70
80
70
80
dB
5.0
0.5 5.0
0.5 v
Open Loop Voltage Gain
!NO= 1 to 4V, RL :.: 1OMQ
72
80
64
80
dB
Gain-Bandwidth*
TJ = 25°C, Av = OdB
1
3
1
3
MHz
DC Transconductance*§
TJ = 25°C, 30kQ s AL s 1MQ
1.7 2.3
1.7 2.3
ms
P.W.M. Comparator (RT= 2kQ, CT= O.Q1 mfd)
Minimum Duty Cycle
VeOMP=0.5V
0
0
%
Maximum Duty Cycle
VeOMP =3.8V
45
45
%
.current Limit Amplifier (Unless otherwise specified, Pin 5 = OV)
Input Offset Voltage
TJ = 25°C, E/A Setfor Maximum Output
190 200 210 180 200 220 mV
Over Operating Temperature Range 180
220 170
230 mV
Input Bias Current
-1
-10
-1
-10 µA
Common Mode Rejection Ratio V(pin 5) = -0.3V to + 5.5V
50
60
50
60
dB
Power S~R~ection Ratio VIN = 10 to 40V
Output Swing (Note 1)
Minimum Total Range
50
60
50
60
dB
5.0
0.5 5.0
0.5 v
Open-Loop Voltage Gain
!No= 1to4V, AL:.: 10MQ
70
80
70
80
dB
Delay Time*
Pin 4 to Pin 9, AVIN = 300mV
300
300
ns
Output Section (Each Output) Collector Emitter Voltage
le= 100µA
60
80
60
80
v
Collector Leakage Current
VeE = 50V
.1
20
.1
20 µA
* These parameters are guaranteed by design but not 100% tested in production.
§DC transconductance (gM} relates to DC open-loop voltage gain according to the following equation: Av= gMRL where RL is the resistance from pin 9 to the common mode voltage. The minimum gM specification is used to calculate minimum Av when the error amplifier output is loaded.
Note 1: Min Limit applies to output high level, max limit applies to output low level.
5-30
UC1524A UC2524A UC3524A
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA= -55°C to+125·c for the uc1524A, -25° to +85°C for the UC2524A, and o·c to + 10°c for the UC3524A; V1N
=Ve= 20V. TA =TJ.
PARAMETER
TEST CONDITIONS
Out_e._ut Section_{_confilEach Ou~u!l_
Saturation Voltage
le=20mA le=200mA
Emitter Outi>_ut Volta~e
IE=50mA
Rise Time*
TJ=25°C R = 2ko
Faff Time*
TJ = 25·c R = 2ko
ComJ18rator Del~
TJ = 25°C Pin 9 to outi>_ut
ShutdownD~
TJ = 25°C Pin 1o to ol!!l!.ut
Shutdown Threshold
TJ = 25°C Re= 2ko
S/D Threshold Over Tem_1>.
Over Qi>_erati11g_Tem~ature Rang_e
Thermal Shutdown*
UC1524A I UC2524A MIN TYP MAX
.2
.4
1
2.2
17
18
120 400
25 200
300
200
0.6 .7 1.0
0.4
1.2
165
UC3524A
UNITS
MIN lYP MAX
.2
.4
v
1 2.2 v
17 18
v
120 400 ns
25 200 ns
300
ns
200
ns
v 0.6 .7 1.0
0.4
1.0 v
165
·c
*These parameters are guaranteed by design but not 100% tested in production.
OPEN-LOOP CIRCUIT
+VIN
Sync
VREF
VIN
Osc.
VREF
RT
+VC
2k 1W
UC1524A D.U.T.
Collector A Collector 8
Error Amp
Current Limit
-----N.I. Inv
--...,..._.-... (+) (·)
Emitter
Input Input Comp Sense Sense S/D
0.1
5-31
Supply Current vs Voltage
10
!I1 ::~
--i.-::::
TJ · -55°C_ TJ · 25"C._
TJ · 125°C -
3
2
Note: Outputs Off, RT·CD
t 1
1 l 0
0 10 20 30 40 50
SlJIPLY VOLTAGE - VN M
Pulse Width Modulator Transfer Function
50 ~-~-~-~-~~
~
UC1524A UC2524A UC3524A
Error Amplifier Voltage Gain and Phase vs Frequency
iii' :!.
:zc
Cl
w
<..C......l
>0 20
a.
0
.z0...
aw . 0
0 i--::,,.-,--,-,--,,-+-t--t-+-t...., -180° 1-+-+"'P'=t-+-'-if-'-"t-+-k::+-"I ·270. ~~~~~~~~~~ -360°
100 1k 10k 100k 1M 10M
FREQUENCY - (hZ)
Oscillator Frequency vs Timing Components
2 3. 4 5 PWM N'UT VOCTAGE (PIN 8) · (VJ
Output Dead lime vs Timing Capacitor Value
~
10 50
·
f--+-+-i-+-1++1+--+-""'··n · 20V -'-~'i
RT· 27000 TJ · 25"C;;;i
~ 2.0
k'
~ 1.0
~ 0.5
a 0· 2
0.1
Note: r--+- Dead Time-oec OU!P!JI piN&'-1
width iWs output dillay
2
5 1020 50100
TMING CAPACITOR · CT (nF)
2
5 1020
50 100
TWIG RESISTOR · RT (rf)
Output Saturation Voltage
~ 5 ~
~ 4
50 100 150 200 250
OUTPUT COLLECTOR ~ (mA)
5-32
Current Limit Amplifier Delay
~ ~
~ 4 3 0 2
1 0
I I T TT
Output At Pin 9
I~ Overdrive
11
5% VllL 10% Z7/L
~2%04%v£=~11='7=7;~".1''iU._"",'-./+,_---++---i+------jj
J ln,!!!Jt At Pin 4 I
I_ I ]
v~ · 20v, T' · 25 C
f--+--+--+--1Pln 2 Tied To Pin 16
Pin 5 Grounded
0
2
3
4
DELAY TIME ( µ, s)
UC1524A UC2524A UC3524A
Shutdown Delay From PWM Comparator - Pin 9
l Jl
-~ 20
VN · 20V
~
15
10 5
t--+---+-++---+-t---+-RL · 2kO -
± t TJ · 25°0
OutputAt Pin 12 OR 13
0
~ ~
I I I
!;; fZ
g1
t---t--t::±:::::t- Input At Pin 9
,
Note: Minimum input
-
o r-r--1
pulse width to _
latch Is 200ns
0
2
3
DELAY TIME (µ s)
Turn-Off Delay From Shutdown - Pin 1O
~ 20
~ 15 10
5
0
~ 1.0
~ o.~
VN · 20V f--+--H-+--+-t--+-RL · 2k0 >--+--++-+---+-t---+- TJ · 25°0
Output At Pin 12 or 13
Note: Minimum input pulse width to latch Is 200ns
0
2
3
DELAY TIME (µ,s)
UNITROOE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. · r.ERRIMACK, NH 03054 TEL (603) 424·2410 · FAX (603) 424-3460
5-33
n nINTEGRATED
~CIRCUITS
-UNITRODE
Regulating Pulse Width Modulators
UC1525A/27A UC2525A/27A UC3525A/27A
FEATURES
8 to 35V Operation
5.1V Reference Trimmed to :1%
1OOHz to 500kHz Oscillator Range
Separate Oscillator Sync Terminal
Adjustable Deadtime Control
Internal Soft-Start
Pulse-by-Pulse Shutdown
Input Undervoltage Lockout with Hysteresis
Latching PWM to Prevent Multiple Pulses
Dual Source/Sink Output Drivers
DESCRIPTION
The UC1525A/15Z7A series of pulse width modulator integrated circuits are designed to offer improved performance and lowered external parts count when used in designing all types of switching power supplies. The on-chip +5.1 V reference is trimmed to ±1 % and the input common-mode range of the error amplifier includes the reference voltage, eliminating external resistors. A sync input to the oscillator allows multiple units to be slaved or a single unit to be synchronized to an external system clock. A single resistor between the CT and the discharge terminals provides a wide range of dead-time adjustment. These devices also feature built-in soft-start circuitry with only an external timing capacitor required. A shutdown terminal controls both the soft-start circuitry and the output stages, providing instantaneous turn off through the PWM latch with pulsed shutdown, as well as soft-start recycle with longer shutdown commands. These functions are also controlled by an undervoltage lockout which keeps the outputs off and the soft-start capacitor discharged for sub-normal input voltages. This lockout circuitry includes approximately 500mV of hysteresis for jitter-free operation. Another feature of these PWM circuits is a latch following the comparator. Once a PWM pulse has been terminated for any reason, the outputs will remain off for the duration of the period. The latch is reset with each clock pulse. The output stages are totem-pole designs capable of sourcing or sinking in excess of 200mA. The UC1525A output stage features NOR logic, giving a LOW output for an OFF state. The UC1527A utilizes OR logic which results in a HIGH output level when OFF.
BLOCK DIAGRAM
6/93 5-34
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage, (+VIN) ............................ +40V Collector Supply Voltage (Ve) ...................... +40V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +5.5V Analog Inputs ............................ -0.3V to +VIN Output Current, Source or Sink . . . . . . . . . . . . . . . . . . . 500mA Reference Output Current . . . . . . . . . . . . . . . . . . . . . . . . 50mA Oscillator Charging Current . . . . . . . . . . . . . . . . . . . . . . . . 5mA Power Dissipation at TA= +25°C (Note 2) .......... 1000mW Power Dissipation at Tc = +25°C (Note 2) .......... 2000mW Operating Junction Temperature ........... -55°C to +150°C Storage Temperature Range .............. -65°C to +150°C Lead Temperature (Soldering, 10 seconds) .......... +300°C Note 1: Values beyond which damage may occur. Note 2: Consult packaging Section of Databook for thermal
limitations and considerations ofpackage.
UC1525A/27A UC2525A/27A UC3525A/27A
RECOMMENDED OPERATING CONDITIONS (Note 3)
Input Voltage (+VIN) ........................ +8V to +35V
Collector Supply Voltage (Ve) . . . . . . . . . . . . . . +4.SV to +35V
Sink/Source Load Current (steady state) . . . . . . . . 0 to 1OOmA
Sink/Source Load Current (peak) . . . . . . . . . . . . . . 0 to 400mA
Reference Load Current . . . . . . . . . . . . . . . . . . . . . . 0 to 20mA
Oscillator Frequency Range .............. 1OOHz to 400kHz
Oscillator Timing Resistor ................... 2kQ to 150kQ
Oscillator Timing Capacitor. .
. ..001 µF to 0.1 µF
Dead Time Resistor Range . . . . . . . . . . . . . . . . . . . . 0 to 5000
Operating Ambient Temperature Range
UC1525A, UC1527A .................. -55°C to +125°C
UC2525A, UC2527A ................... -25°Cto +85°C
UC3525A, UC3527A ..................... 0°Cto +70°C
Note 3: Range over which the device is functional and
parameter limits are guaranteed.
CONNECTION DIAGRAMS DIL-16 (TOP VIEW) J or N Package
Inv Input N.I. Input
Sync Osc Output
CT RT Discharge Soft-Start
VREF +VIN Output B Ve Ground Output A Shutdown Compensation
PLCC-20, LCC-20 (TOP VIEW)
Q, LPackage
PACKAGE PIN FUNCTION
FUNCTION
PIN
N/C
1
Inv. Input
2
N.l. lf!e_ut
3
L3 2 1 20 19
SYNC
4
4
18
OSC. ol!!e_ut
5
5
17~
N/C
6
6
16
CT
7
7
15
RT
8
Discham_e
9
8
14
9 10 11 12 13
Softstart
10
N/C
11
Com~nsation
12
Shutdown
13
OU!e_utA
14
Ground
15
N/C
16
Ve
17
Outi>_ut B
18
+VIN
19
VREF
20
5-35
UC1525A/27A UC2525A/27A UC3525A/27A
ELECTRICAL CHARACTERISTICS: +VIN= 20V, and over operating temperature, unless otherwise specified, TA= TJ
PARAMETER
TEST CONDITIONS
Reference Section
Output Voltage
TJ =25°C
Line Regulation
VIN= 8 to 35V
Load Regulation
IL= Oto20mA
Temperature Stability (Note 5) Over Operating Range
Total Output Variation (Note 5) Line, Load, and Temperature
Shorter Circuit Current
VREF = 0, TJ = 25°C
Output Noise Voltage (Note 5) 10Hz"' 10kHz, TJ - 25°C
Long Term Stability (Note 5)
TJ = 125°C
Osclllator Section (Note 6)
Initial Accuracy (Notes 5 & 6) TJ =25°C
Voltage Stability (Notes 5 & 6) VIN= 8to35V
Temperature Stability (Note 5) Over Operating Range
Minimum Frequency
RT= 200kQ, CT= 0.1µF
Maximum Frequency
RT = 2kQ, CT = 470pF
Current Mirror
IRT=2mA
Clock Amplitude (Notes 5 & 6)
Clock Width (Notes 5 & 6)
TJ =25°C
Sync Threshold
Sync Input Current
Sync Voltage= 3.5V
= Error Amplifier Section (VcM 5.1 V)
Input Offset Voltage
lf'!I>_Ut Bias Current
Input Offset Current
DC Open Loop Gain
RL ;i: 10MQ
Gain-Bandwidth Product (Note 5)
DC Transconductance (Notes 5 & 7)
Av= OdB, TJ = 25°C
= TJ 25°C, 30kQ"' RL"' 1MQ
Output Low Level
Output High Level
Common Mode Rejection
VcM = 1.5 to 5.2V
Supply Voltage Rejection
VIN =Bio 35V
UC1525A/UC2525A UC1527A/UC2527A
MIN TYP MAX
UC3525A UC3527A
UNITS
MIN TYP MAX
5.05 5.10 5.15 5.00 5.10 5.20 v
10 20
10
20 mV
20
50
20
50 mV
20 50
20
50
5.00
5.20 4.95
5.25 v
80 100
80 100 mA
40 200
40 200 µVrms
20
50
20
50 mV
±2 ±6
±2 ±6 %
±0.3 ± 1
±1 ±2 %
±3 ±6
±3 ±6 %
120
120 Hz
400
400
kHz
1.7 2.0 2.2 1.7 2.0 2.2 mA
3.0 3.5
3.0 3.5
v
0.3 0.5 1.0 0.3 0.5 1.0 µs
1.2 2.0 2.8 1.2 2.0 2.8
v
1.0 2.5
1.0 2.5 mA
0.5
5
2
10 mV
1
10
1
10 µA
1
1
µA
60
75
60
75
dB
1
2
1
2
MHz
1.1 1.5
1.1 1.5
ms
0.2 0.5
0.2 0.5
v
3.8 5.6
3.8 5.6
v
60
75
60
75
dB
50
60
50
60
dB
Note 5: These parameters, although guaranteed over the recommended operating conditions, are not 100% tested in production.
= Note 6: Tested at fosc 40kHz (RT= 3.6kQ, CT= 0.01µF, Ro= 00). Approximate oscillator frequency is defined by:
f-
1
CT(0.7RT + 3Ro)
Note 7: DC transconductance (gM) relates to DC open-loop voltage gain (Av) according to the following equation: Av= gMRL where RL is the resistance from pin 9 to ground.. The minimum gM specification is used to calculate minimum Av when the error amplifier output is loaded.
5-36
UC1525A/27A UC2525A/27A UC3525A/27A
ELECTRICAL CHARACTERISTICS: +V1N = 20V, and over operating temperature, unless otherwise specified, TA= TJ
PARAMETER
TEST CONDITIONS
UC1525A/UC2525A UC1527A/UC2527A
UC3525A UC3527A
UNITS
MIN TYP MAX MIN TYP MAX
PWM Comparator
Minimum Duty-Cycle Maximum Duty-Cycle Input Threshold (Note 6)
Zero Duty-Cycle Maximum Duty-Cycle
0
0
%
45
49
45
49
%
0.7 0.9
0.7 0.9
v
3.3 3.6
3.3 3.6
v
Input Bias Current (Note 5) Shutdown Section
.05 1.0
.05 1.0 fiA
Soft Start Current Soft Start Low Level Shutdown Threshold
Vso = OV, Vss = OV VSD=2.5V
25
50
80
25
50
80
fiA
0.4 0.7
0.4 0.7
v
To outputs, Vss = 5.1V, TJ = 25°C
0.6 0.8
1.0 0.6 0.8
1.0
v
Shutdown Input Current
VSD=2.5V
0.4 1.0
0.4 1.0 mA
Shutdown Delay (Note 5)
Vso = 2.5V, TJ = 25°C
Output Drivers (Each Output) r.;c = 20V)
Output Low Level
ISINK=20mA
!SINK= 100mA
Output High Level
!SOURCE = 20mA
!SOURCE = 1OOmA
Under-Voltage Lockout
VCOMP and Vss = High
0.2 0.5
0.2
0.5
flS
0.2 0.4
0.2 0.4
v
1.0 2.0
1.0 2.0
v
18 19
18 19
v
17 18
17 18
v
6
7
8
6
7
8
v
Ve OFF Current (Note 7) Rise Time (Note 5)
Vc=35V CL= 1nF, TJ = 25°C
200 100 600
200 fiA
100 600 ns
Fall Time (Note 5)
CL= 1nF, TJ = 25°C
50 300
50 300 ns
Total Standby Current
Supply Current
VIN=35V
14 20
14 20 mA
Note 5: These parameters, although guaranteed over the recammended operating conditions, are not 100% tested in production.
= Note 6: Tested at fosc 40kHz (RT= 3.6/<Q, CT= 0.01µF, Ro= 00).
Note 7: Collector off-state quiescent current measured at pin 13 with outputs low for UC1525A and high for UC1527A.
UC1525A Error Amplifier
Q1
Inv.
Input
N.1.
Input
µ1A00
To PWM Comparator 1000
Comp
UC1525A/27A UC2525A/27A UC3525A/27A
PRINCIPLES OF OPERATION AND TYPICAL CHARACTERISTICS
UC1525A Output Circuit (1/2 Circuit Shown)
UC1525A Output Saturation Characteristics
4 f---+-+-+-1--+-+--+--+-l-I--+-~
Clack F/F PWM
+VSUPPLY 0-+-~
To Output Filter
+Ve A
UC1525A
B Gnd
12
Return o------<>------+-For single-ended supplies, the driver outputs are grounded. The Ve terminal is switched to ground by the totem-pole source transistors on alternate oscillator cycles.
+15V
Output Current, Source Or Sink - (A)
+VSUPPLY 0------------~
II
Return In conventional push-pull bipolar designs, forward base drive is controlled by R1-R3. Rapid turn-off times for the power devices are achieved with speed-up capacitors C1 and C2.
Return
The low source impedance of the output drivers provides rapid charging of power FET Input capacitance while minimizing external components.
Low power transformers can be driven by the UC1525A. Automatic reset occurs during dead time, when both ends of the primary winding are switched to ground.
5-38
UC1525A Oscillator Schematic
UC1525A/27A UC2525A/27A UC3525A/27A
RT 6
03
Cr 5 1--------<>---1
Ramp
To PWM
014
Blank Ing To Output
Gnd
PRINCIPLES OF OPERATION AND TYPICAL CHAR· ACTERISTIC SHUTDOWN OPTIONS (See Block Diagram)
Since both the compensation and soft-start terminals (Pins 9 and 8) have current source pull-ups, either can readily accept a pull-down signal which only has to sink a maximum of 1OOµA to turn off the outputs. This is subject to the added requirement of discharging whatever external capacitance may be attached to these pins.
An alternate approach is the use of the shutdown circuitry of Pin 1O which has been improved to enhance the available shutdown options. Activating this circuit by applying
a positive signal on Pin 1O performs two functions; the PWM latch is immediately set providing the fastest turnoff signal to the outputs; and a 150µA-current sink begins to discharge the external soft-start capacitor. If the shutdown command is short, the PWM signal is terminated without significant discharge of the soft-start capacitor, thus, allowing, for example, a convenient implementation of pulse-by-pulse current limiting. Holding Pin 1O high for a longer duration, however, will ultimately discharge this external capacitor, recycling slow turn-on upon release.
Pin 10 should not be left floating as noise pickup could conceivably interrupt normal operation.
Oscillator Charge Time vs RTand CT
200~~~~~~~~~~
e 100 --+---+---+--+-+-Eiff+--1+#+-#+I-~
1-
q:: 50
·~ 20
£
~ 10 5
~ 2
- N in 12 ~ 15 ~ ~ ~ ~ ~ ~~
Charge Time ( µ s)
Oscillator Discharge Time vs Ro and CT
~~-NII)~~ :58~
Discharge Time ( µ s)
5-39
Maximum Value Ro vs Minimum Value Rr
500,--,--,--,--....-~....-~~---.
Ii
IC<
.i ~ 100 t--.1<-t---1---+--<--<--+--+--+----<
i 0 2 4 6 8 10 12 Mlnlmun Recommended RT For A Given Ro (K 0)
LAB TEST FIXTURE
UC1525A/27A UC2525A/27A UC3525A/27A Error Amplifier Voltage Gain and Phase vs Frequency
100 1< 10k 100k 1M Frequency (Hz)
AL is impedance from pin 9 to ground. Values below 30kQ will begin to limit the maximum duty cycle.
Reference Regulator
L
D.U.T.
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. · MERRIMACK; NH 03054 TEL (603) 424-2410 · FAX (603) 424-3460
5-40
VREF
_J
nL.:::nJ INTEGRATED CIRCUITS
-UNITRODE
Regulating Pulse Width Modulators
UC1525B UC1527B UC2525B UC2527B UC3525B UC3527B
FEATURES 8 to 35V Operation 5.1 V Buried Zener Reference Trimed to± .75% 1OOHz to 500kHz Oscillator Range Separate Oscillator Sync Terminal
· Adjustable Deadtime Control Internal Soft-Start Pulse-by-Pulse Shutdown Input Undervoltage Lockout with Hysteresis Latching PWM to Prevent Multiple Pulses Dual Source/Sink Output Drivers Low Cross Conduction Output Stage
· Tighter Reference Specifications
BLOCK DIAGRAM
DESCRIPTION
The UC1525B/1527B series of pulse width modulator integrated circuits are designed to offer improved performance and lowered external parts count when used in designing all types of switching power supplies. The on-chip +5.1 V buried zener reference is trimmed to±.75% and the input common-mode range of the error amplifier includes the reference voltage, eliminating external resistors. A sync input to the oscillator allows multiple units to be slaved or a single unit to be synchronized to an external system clock. A single resistor between the Cr and the discharge terminals provide a wide range of dead time adjustment. These devices also feature built-in soft-start circuitry with only an external timing capacitor required. A shutdown terminal controls both the softstart circuitry with only an external timing capacitor required. A shutdown terminal controls both the soft-start circuitry and the output stages, providing instantaneous turn off through the PWM latch with pulsed shutdown, as well as soft-start recycle with longer shutdown commands. These functions are also controlled by an undervoltage lockout which keeps the outputs off and the softstart capacitor discharged for sub-normal input voltages. This lockout circuitry includes approximately 500mV of hysteresis for jitter-free operation. Another feature of these PWM circuits is a latch following the comparator. Once a PWM pulse has been terminated for any reason, the outputs will remain off for the duration of the period. The latch is reset with each clock pulse. The output stages are totem-pole designs capable of sourcing or sinking in excess of 200mA. The UC1525B output stage features NOR logic, giving a LOW output for an OFF state. The UC15278 utilizes OR logic which results in a HIGH output level when OFF.
UV LOCKOUT
I - - - - - - - - - - - - - - - - - - - -1
I
I
GNO
To Internal
Circuitry
SHUTDOWN
12/92
UC1S27B OUTPUT STAGE 1___________________ _
5-41
CONNECTION DIAGRAMS
DIL-16, SOIC-16 (Top View) J or N Package, OW Package
PLCC-20, LCC-20 (Top View) Q, L Packages
L 3 2 1 20 10
4
18
5
17
6
16
7
15
8
14
910111213
UC1525B UC1527B UC2525B UC2527B UC3525B UC3527B
PACKAGE PIN FUNCTION
FUNCTION
PIN
N/C
1
INV INPUT
2
N.l. INPUT
3
SYNC
4
OSC. OUTPUT
5
N/C
6
c.
7
A·
8
DISCHARGE
9
SOFT-START
10
N/C
11
COMPENISATION
12
SHUTDOWN
13
OUTPUT A
14
GROUND
15
N/C
16
Ve
17
Qli_it'U B
18
+V1N
19
VAE,
20
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage, (+V1N) .......,................................................ +40V Collector Supply Voltage (Ve) ............................................ +40V Logic Inputs ......................................................... -0.3V to +5.SV Analog Inputs .........................................................-0.3V to +V,N Output Current, Source or Sink ....................................... SOOmA Reference Output Current ................................................. 50mA Oscillator Charging. Current ................................................. 5mA Power Dissipation at TA= +25°C (Note 2) .................... 1000mW Power Dissipation at Tc= +25°C (Note 2) .................... 2000mW Operating Junction Temperature ..................... -55°C to+150°C Storage Temperature Range ........................... -65°C to +150°C Lead Temperature (Soldering, 10 seconds) ................... +300°C Note 1: Values beyond which damage may occur. Note 2: Consult packaging section of databook for thermal
limitations and considerations of package.
RECOMMENDED OPERATING CONDITIONS (Note 3)
Input Voltage (+V1N) ................................................ +8Vto +35V Collector Supply Voltage (Ve) .............................. +4.5V to +35V Sink/Source Load Current (steady state) ................. 0 to 1OOmA Sink/Source Load Current (peak) ............................ 0 to 400mA Reference Load Current.. ........................................... 0 to 20mA Oscillator Frequency Range ........................... 1OOHz to 400kHz Oscillator Timing Resistor .................................... 2k.Q to 150k.Q Oscillator Timing Capac~or ................................001 µF to 0.1 µF Dead Time Resistor Range ........................................ 0 to 500Q Operating Ambient Temperature Range
UC1525B, UC1527B ................................. -55°C to +125°C UC2525B, UC2527B ................................... -40°C to +85°C UC3525B, UC3527B ...................................... 0°C to +70°C Note 3: Range over which the device is functional and parameter limits are guaranteed.
ELECTRICAL CHARACTERISTICS: +VrN = 20V, and over operating temperature, unless otherwise specified
PARAMETER
TEST CONDITIONS
UC1525BIUC2525B UC1527BIUC2527B
MIN TYP MAX
UC3525B UC3527B
MIN TYP MAX
Reference Section Output Voltage line Regulation Load Regulation Temperature Stability (Note 5) Total Output Variation Short Circuit Current Output Noise Voltage (Note 5) Long Term Stability (Note 5)
TJ = 25°C V1N = 8 to 35V IL= 0 to 20mA Over Operating Range Line, Load, and Temperature VREF = 0, TJ =25°C 10Hz s; f s; 10kHz, TJ = 25°C TJ = 125°C, 1000 Hrs.
5.062 5.10 5.138 5.036 5.10 5.164
5
10
5
10
7
15
7
15
10
30
10
30
5.036
5.164 5.024
5.176
80
100
80
100
40
200
40
200
3
10
3
10
UNITS
v
mV mV mV
v
mA µVrms
mV
5-42
UC1525B
UC2525B
UC3525B ELECTRICAL CHARACTERISTICS: +V1N = 20V, and over operating temperature, unless otherwise specified
PARAMETER
TEST CONDITIONS
UC1525B/UC2525B UC1527B/UC2527B
UC3525B UC3527B
MIN TYP MAX MIN TYP MAX
Oscillator Section (Nola 6)
Initial Accuracy (Notes 5 & 6) Voltage Stability (Notes 5 & 6)
TJ = 25°c VIN=8T035V
±2
±6
±0.3 ±1
±2
±6
±1
±2
Temperature Stability (Note 5) Minimum Frequency
Over Operating Range RT = 2001<.n, Cr = 0. 1µF
±3
±6
120
±3
±6
120
Maximum Frequency
RT = 21<.n, Cr= 470pF
400
400
Current Mirror Clock Amjllitude_lNotes 5 & fil_
IRT=2mA
1.7
2.0
2.2
1.7
2.0
2.2
3.0
3.5
3.0
3.5
Clock Width (Notes 5 & 6)
TJ= 25°c
0.3
0.5
1.0
0.3
0.5
1.0
Sync Threshold
1.2
2.0
2.8
1.2
2.0
2.8
Sync Input Current
Sync Voltage = 3.5V
1.0
2.5
1.0
2.5
Error Amplifier Section (VCM = 5.1 V)
11}!1!Jt Offset Volll!llil
0.5
5
2
10
11}!1!Jt Bias Current l~t Offset Current DC Open Loop Gain
RL~10Megn
1
10
1
10
1
1
60
75
60
75
Gain-Bandwidth Product (Note 5) Ou!fillt Low Level
Av = OdB, TJ = 25°C
1
2
1
2
0.2
0.5
0.2
0.5
Ou!f>Ut Hjg_h Level
3.8
5.6
3.8
5.6
Common Mode Rejection
VcM = 1.5 to 5.2V
60
75
60
75
Supply Voltage Rejection
V1N = 8 to 35V
50
60
50
60
PWM Comparator Minimum Duty-Cycle
0
0
Maximum Duty-Cysle
45
49
45
49
Input Threshold (Note 6)
Zero Duty-Cycle
0.7
0.9
0.7
0.9
Input Threshold (Note 6)
Maximum Duty-Cycle
3.3
3.6
3.3 3.6
Input Bias Current (Note 5) Shutdown Section
.05
1.0
.05
1.0
Solt Start Current
Vso = OV, Vss = OV
25
50
80
25
50
80
Soft Start Low Level
Vso = 2.5V
0.4
0.7
0.4
0.7
Shutdown Threshold
To outputs, Vss= 5.1V, TJ=25°C
0.6
0.8
1.0
0.6
0.8
1.0
Shutdown Input Current Shutdown Delay (Note 5)
Vso = 2.5V Vso = 2.5V, TJ = 25°C
0.4
1.0
0.2
0.5
0.4
1.0
0.2 0.5
Output Drivers (Each Output) (Ve= 20V)
Output Low Level
ISINK = 20mA ls1NK = 1OOmA
0.2
0.4
1.0
2.0
0.2 0.4 1.0 2.0
Output High Level Undervoltage Lockout
!SOURCE = 20mA lsouRCE = 1OOmA VcoMP and Vss = high
18
19
17
18
6
7
8
18
19
17
18
6
7
8
Collector Leakage
Ve= 35V
200
200
Rise Time (Note 5)
CL= 1nF, TJ = 25°C
100 600
100 600
Fall Time (Note 5)
CL= 1nF, TJ= 25°C
50
300
50
300
Cross conduction charge
Per cycle, TJ = 25°C
30
30
Total Standby Current
Supply Current
VIN= 35V
14
20
14
20
Notes: 5. These parameters, although guaranteed over the recommended operating conditions, are not 100% tested in produ~tion.
6. Tested at lose= 40khz (Rr = 3.6!2, CT= .01µF, Ro= On). Approximate oscillator frequency is defined by: f = CT(0.7RT+3Ro)
UC1527B UC2527B UC3527B
UNITS
% % o/o Hz kHz mA
v
µs
v
mA
mV ~ ~ dB MHz
v v
dB dB
o/o o/o
v v
µA
µA
v v
mA µS
v v v v v
µA ns ns nc
mA
5-43
PRINCIPLES OF OPERATION AND TYPICAL CHARACTERISTICS
UC15258 UC1527B UC25258 UC2527B UC3525B UC3527B
UC1525B OUTPUT CIRCUIT (1/2 Circuit Shown)
UC15256 OUTPUT SATURATION CHARACTERISTICS
= VrH 20Y
CLOCK FIF
PWM
OUTPUT CURRENT, SOURCE OR SINK (A)
12
For single-ended supplies, the driver outputs are grounded. The VC terminal is switched to ground by the totem-pole source transistors on alternate oscillator cycles.
In conventional push-pull bipolar designs, forward base drive is controlled by R1-R3. Rapid turn-off times for the power devices are achieved with speed-up capacitors C, and C2.
+VSUPPLY
RETURN
=
The low source impedance of the output drivers provides rapid charging of power FET input capacitance while minimizing external components.
Low power transformers can be driven directly by the UC1525A. Automatic reset occurs during dead time, when both ends of the primary winding are switched to ground.
5-44
PRINCIPLES OF OPERATION AND TYPICAL CHARACTERISTICS
SHUTDOWN OPTIONS {See Block Diagram} Since both the compensation and soft-start terminals (Pins 9 and 8) have current source pull-ups, either can readily accept a pull-down signal which only has to sink a maximum of 1OOµA to turn off the outputs. This is subject to the added requirement of discharging whatever external capacitance may be attached to these pins.
An alternate approach is the use of the shutdown circuitry of Pin 10 which has been improved to enhance the available shutdown options. Activating this circuit by applying a positive signal on Pin
o1 performs two functions: the PWM latch is immediately set
providing the fastest turn-off signal to the external soft-start capacitor. If the shutdown command is short, the PWM signal is terminated without significant discharge of the soft-start capacitor, thus, allowing, for example, a convenient
implementation of pulse-by-pulse current limiting. Holding Pin 10 high for a longer duration, however, will ultimately discharge this external capacitor, recycling slow turn-on upon release.
Pin 10 should not be left floating as noise pickup could conceivably interrupt normal operation.
OSCILLATOR CHARGE TIME VS. RT AND CT
UC1525B UC1527B UC2525B UC25278 UC3525B UC3527B
UC1525B OSCILLATOR SCHEMATIC
OSCILLATOR DISCHARGE TIME VS. Ro AND CT
~~~~~~~!!j
CHARGE TIME (JJs)
UC1525B ERROR AMPLIFIER
oN~~~~~~~~~~~o~--+--<--...
o 0
· N ~~~
DISCHARGE TIME lµs)
ERROR AMPLIFIER OPEN-LOOP FREQUENCY RESPONSE
~ 60 ,___ ___,.._........, .-+--+--+---I
z
<( Cwl 40 1-----+--_.,,__....,...__,f-----+--I
~
~ rol-,,-..,,.---l---!--'lo.===11'1.--+---1
=
8
~
FREQUENCY (Hz)
5-45
LAB TEST FIXTURE
UC1525B UC1.527B UC2525B UC2527B
UC3525B UC3527B
3.lk
.CI09 !-0--C>--<l->----t f-OCy
0.1
1 =Vos 2=1t1-) hit-I 1
I I
~GND
_ _ _ _ _ _Sl_lA_,_ _ _ _ __, 8 r--.-.,..S-O-F-T\,SJTART
D.U.T.
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD.· MERRIMACK, NH 03054 TEL (603) 424-2410 , FAX (603) 424-3460
5-46
n nINTEGRATED
~CIRCUITS
-UNITRODE
Regulating Pulse Width Monitor
UC1526 UC2526 UC3526
FEATURES 8 To 35V Operation 5V Reference Trimmed To ±1% 1Hz To 400kHz Oscillator Range Dual 1OOmA Source/Sink Outputs Digital Current Limiting Double Pulse Suppression Programmable Deadtime Under-Voltage Lockout Single Pulse Metering Programmable Soft-Start Wide Current Limit Common Mode Range TTLJCMOS Compatible Logic Ports Symmetry Correction Capability Guaranteed 6 Unit Synchronization
DESCRIPTION
The UC1526 is a high performance monolithic pulse width modulator circuit designed for fixed-frequency switching regulators and other power control applications. Included in an 18-pin dual-in-line package are a temperature compensated voltage reference, sawtooth oscillator, error amplifier, pulse width modulator, pulse metering and setting logic, and two low impedance power drivers. Also included are protective features such as soft-start and under-voltage lockout, digital current limiting, double pulse inhibit, a data latch for single pulse metering, adjustable deadtime, and provision for symmetry correction inputs. For ease of interface, all digital control ports are TTL and 8-series CMOS compatible. Active LOW logic design allows wired-OR connections for maximum flexibility. This versatile device can be used to implement single-ended or push-pull switching regulators of either polarity, both transformerless and transformer coupled. The UC1526 is characterized for operation over the full military temperature range of -55°C to +125°C. The UC2526 is characterized for operation from -25°C to +85°C, and the UC3526 is characterized for operation from 0° to +10°c.
BLOCK DIAGRAM
Sync Ro RT CT
Reference Regulator
-
Internal Circuitry
Clock
Under Voltage Lockout
Thermal Shutdown
Reset Css
Comp
+EA -EA +Cs -Cs
6/93
Solt Start
VIN
s R a
s
PWM Latch
a
a
Toggle F/F
5-47
18 VREF Ve
Output -B-
Gnd
-
8
Shut Down
ABSOLUTE MAXIMUM RATINGS (Note 1, 2)
Input Voltage (+VIN) ··...·.·...................··. +40V Collector Supply Voltage (+Ve) . . . . . . . . . . . . . . . . . . . . .. +40V Logic lnpu1s ............................. -0.:r./ to +5.5V Analog lnpu1s . . . . . . · . . . . . . . . . . . . . . . . . . . . . . -0.3V to +VIN Source/Sink Load Current (each output) .··....·..... 200mA Reference Load Current .........·...........·..... 50mA Logic Sink Current ............................. , . 15mA Power Dissipation at TA = +25°C (Note 2) . . . . . . . . . . 1OOOmW Power Dissipation at Tc = +25°C (Note 2) . · . . . . . . . . 3000mW Operating Junction Temperature . . . . . . . . . . . . . . . . . · +150°C Storage Temperature Range · · . . . . . . . . · . . . -65°C to +150°C Lead Temperature (soldering, 1O$econds) . · . . . . . . . . +300°C Note 1: Values beyond which damage may occur. Note 2: Consult packaging section of databook for thermal
/Imitations and considerations ofpackage.
UC1526 . UC2526
UC3526
RECOMMENDED OPERATING CONDITIONS (Note 3)
Input Voltage .........·.................· , · +SV to +35V Collector Supply Voltage · . . . . . . . · . . . . . . . . . . +4.5V to +35V Sink/Source Load Current (each output) . . . . . . · · · O.to 1OOmA Reference Load Current · . . · . . . .. . . . .. . . .. . . . . Oto 20mA Oscillator Frequency Range ...............· 1Hz to 400kHz Oscillator Timing Resistor .............·..... 2k0 to 1.50k0 Oscillator Timing Capacitor . · . . . . . . . . . . · . . · · · . 1nf to 20µF Available Deadtime Range at 40kHz. . . . . · . · . · · . . 3% to 50% Operating Ambient Temperature Range
uc1526 . . . . . . . . .. . . . . . . . . .. . . . . .. . . ..55·c to +125·c UC2526 . . . . . . . . . . . · . . · . . . . . · . . . . . . . . -25°C to +85°C UC3526 . . . . . . . . . . . · . . . . . . . . · . . . . . . . . . -0°c to +10°c Note 3: Range over which the device Is functional and
parameter limits are guaranteed.
CONNECTION DIAGRAMS
DIL-18, SOIC:-18 (TOP VIEW) J or N Package, DW Package
+Error -Error
Comp
Css Reset -Current Sense +Current Sense Shutdown RTIMING
VREF +VIN Output B Ground Ve Output A Sync Ro CT
PLCC-20, LCC-20 (TOPVIEW) Q and L Packages
L3 2 1 2019
4
18
5
17
6
16
7
15
8
14
9 10 11 12 13
PACKAGE PIN FUNCTION
FUNCTION
PIN
N.lQ.
1
+Error
2
-Error
3
Com__ll,
4
Css
5
Reset
6
- Current Sense
7
+ Current Sense
8
Shutdown
9
RTIMING
10
CT
11
Ro
12
$y_nc
13
Output A
14
Ve
15
NLC
16
Ground
17
OutDutB
18
+VIN
19
VREF
20
ELECTRICAL CHARACTERISTICS: +V1N = 15V, and over operating ambient temperature, unless otherwise specified, TA= TJ.
PARAMETER
Reference Section (Note 41 Output Volta_g_e Line R~ulation Load Regulation Tem_e_erature Stabil~ Totai Output Volta_g_e Ra11ge Short Circuit Current
Under -Volte_g_e Lockout RESET Output Voltage
TEST CONDITIONS
TJ= + 25°C +VIN= 8 to 35V IL = 0 to ;20mA Over O_e_erati'!9_TJ · Over Recommended O~eratill9_ Conditions VREF=OV
VREF=3.8V VREF =4.8V
UC1526 / UC2526
UC3526
UNllS
MIN TYP MAX MIN TYP MAX
v 4.95 5.00 5.05 4.90 5.00 5.10
10 20
10 30 mV
10 30
10 50 mV
15 50
15 50 mV
v 4.90 5.00 5.10 4.85 5.00 5.15
25 50 100 25 50 100 mA
0.2 0.4
0.2 0.4 v
2.4 4.8
2.4 4.8
v
Note 4: IL= OmA.
5-48
ELECTRICAL CHARACTERISTICS: +VIN = 15V, and over operating ambient temperature, unless otherwise
specified, TA= TJ.
UC1526 UC2526 UC3526
PARAMETER
TEST CONDITIONS
Oaclllator Section 1Note 5) Initial Accu~
TJ= + 25·c
VoltaJ!!_Stabl!.!!}t_
+VIN= 8 to 35V
Temj>_erature Stability_
Over O(lElratlng TJ
Minimum Fr~ue~
RT = 150kD, CT = 20µF
Maximum Fre_g_uen_91_ Sawtooth Peak Volta~
RT = 2kD, CT = 1.0nF +VIN=35V
Sawtooth Valley Voltage
+VIN=8V
Error Am_.e!lfter SectionJ_Note 6)
Input Offset Voltage
Rss2kQ
Input Bias Current
Input Offset Current
DC Open Loop Gain
RL:.:10MQ
HIGH Output Voltage LOW Output Volta~
VPIN1·VPIN2:.: 150mV, ISOURCE = 100!-IA VPIN2-VPIN1 :.: 150mV, ISINK = 1OOIJA
Common Mode Rejection
Rs s 12kD
Supply Vo~e Rej_ection
+VIN= 12to 18V
PWM Comparator (Note 5)
Minimum D_llly_Cycle Maximum D~~cle
VCOMPENSATION = +0.4V VCOMPENSATION = +3.6V
[)lg_Hal Porta (SYNC, SHUTDOWN, and RESET)
HIGH O~ut VoltaJl_e
ISOURCE =40!JA
LOW O~ut Voltage
ISINK = 3.6mA
HIGH Input Current
VIH =+2.4V
LOW lf!e!ll Current
VIL= +0.4V
Current Umlt Comparator (Note 7)
Sense Voltage
Rss50Q
l'!e_Ut Blas Current
Soft-Start Section
Error Clar'!e_Vo~e
RESET = +0.4V
Cs Charging Current
RESET =+2.4V
Output Drivers (Each Output) (Note 8)
HIGH Output Voltage
!SOURCE = 20mA
lsouRCE = 1OOmA
LOW Output Voltage
ISINK=20mA
ISINK = 100mA
Collector Leakll_!le
Vc=40V
Rise Time
CL= 1000pF
Fall Time
CL= 1000pF
Power Consum_e_tlon (Note 9)
Standby Current
SHUTDOWN · +0.4V
UC1526 / UC2526
MIN TYP MAX
:t3 :t8
0.5
1
7
10
1
400
3.0 3.5
0.5 1.0
2
5
-350 -1000
35 100
64 72
3.6 4.2
0.2 0.4
70 94 66 80
0
45
49
2.4 4.0 0.2 0.4 -125 -200 -225 -360
90 100 110
-3 -10
0.1 0.4 50 100 150
12.5 13.5
12
13
0.2 0.3
1.2 2.0
50 150
0.3 0.6
0.1 0.2
18 30
UC3528
UNITS
MIN TYP MAX
:t:3 :t8 %
0.5
1
%
3
5
%
1
Hz
400
kHz
3.0 3.5
v
0.5 1.0
v
2
10 mV
-350 -2000 nA
35 200 nA
60 72
dB
3.6 4.2
v
0.2 0.4
v
70 94
dB
66 80
dB
0
%
45 49
%
2.4 4.0
v
0.2 0.4
v
-125 -200 !AA
-225 -360 !AA
80 100 120 mV
-3 -10 !AA
0.1
0.4
v
50 100 150 !AA
12.5 13.5
v
12
13
v
0.2 0.3
v
1.2 2.0
v
50 150 µA
0.3
0.6
µS
0.1
0.2
µS
18 30 mA
Note 4: IL= OmA. Note5: FOSC=40kHz(Rr=4.12kQ:r.1%, CT=0.1µ.F:t:.1%,
RD= OQ)
Note 6: VcM = 0 to +5.2V NoteB: Ve= +15V Note9: +VIN=+35V. Rr=4.12/<Q.
5-49
UC1526 UC2526 UC3526
APPLICATIONS INFORMATION
Voltage Reference
The reference regulator of the UC1526 is based on a ternperature compensated zener diode. The circuitry is fully active at supply voltages above +BV, and provides up to 20mA of load current to external circuitry at +5.0V. In systems where additional current is required, an external PNP transistor can be used to boost the available current. A rugged low frequency audio-type transistor should be used, and lead lengths between the PWM and transistor should be as short as possible to minimize the risk of oscillations. Even so, some types of transistors may require collector-base capacitance for stability. Up to 1 amp of load current can be obtained with excellent regulation if the device selected maintains high current gain.
VREF
To Reset To Driver A x:~-+:::;.._- To Driver B Figure 2. Under-Voltage Lockout Schematic
Soft-Start Circuit
c·T
*May with
be required some types
--" oi transistors
UC1526A
Reference Regulator
VAEF
10µF
Figure 1. Extending Reference Output Current
Under-Voltage Lockout The under-voltage lockout circuit protects the UC1526 and the power devices it controls from inadequate supply voltage, If +VIN is too low, the circuit disables the output
The soft-start circuit protects the power transistors and rectifier diodes from high current surges during power supply turn-on. When supply voltage is first applied to the
UC1526, the under-voltage lockout circuit holds RESET LOW with 03. 01 is turned on, which holds the soft-start capacitor voltage at zero. The second collector of 01 clamps the output of the error amplifier to ground, guaranteeing zero duty cycle at the driver outputs. When the
supply voltage reaches normal operating range, RESET will go HIGH. 01 turns off, allowing the internal 1OOmA
current source to charge Cs. 02 clamps the error amplifier output to 1VBE above the voltage on Cs. As the soft-
start voltage ramps up to +5V, the duty cycle of the PWM linearly increases to whatever value the voltage regulation loop requires for an error null.
drivers and holds the RESET pin LOW. This prevents spurious output pulses while the control circuitry is stabi-
VAEF
lizing, and holds the soft-start timing capacitor in a discharged state.
The circuit consists of a +1.2V bandgap reference and comparator circuit which is active when the reference voltage has risen to 3VBE or +1.BV at 25°C. When the reference voltage rises to approximately +4.4V, the circuit
·~Error
-Error Reset
enables the output drivers and releases the RESET pin, allowing a normal soft-start. The comparator has 200mV of hysteresis to minimize oscillation at the trip point. When +VIN to the PWM is removed and the reference drops to +4.2V, the under-voltage circuit pulls RESET LOW again. The soft-start capacitor is immediately discharged, and the PWM is ready for another soft-start cycle.
The UC1526 can operate from a +5V supply by connecting the VREF pin to the +VIN pin and maintaining the supply between +4.8 and +5.2V.
Figure 3. Soft-Start Circuit Schematic
Digital Control Ports
The three digital control ports of the UC1526 are bi-directional. Each pin can drive TTL and 5V CMOS logic di-
rectly, up to a fan-out of 1o low-power Schottky gates.
Each pin can also be directly driven by open-collector
5-50
APPLICATIONS INFORMATION (cont.) TTL, open-drain CMOS, and open-collector voltage comparators; tan-in is equivalent to 1 low-power Schottky gate. Each port is normally HIGH; the pin is pulled LOW to activate the particular function. Driving SYNC LOW initiates a discharge cycle in the oscillator. Pulling SHUTDOWN LOW immediately inhibits all PWM output pulses. Holding RESET LOW discharges the soft-start capacitor. The logic threshold is +1.1 V at +25°C. Noise immunity can be gained at the expense of tan-out with an external 2k pull-up resistor to +5V.
VREF
To Internal
Logic
From Internal
Logic
Shutdown Or Reset
Figure 4. Digital Control Port Schematic
Oscillator
The oscillator is programmed tor frequency and dead time with three components: RT, CT and RD. Two waveforms
are generated: a sawtooth waveform at pin 1o tor pulse
width modulation, and a logic clock at pin 12. The following procedure is recommended tor choosing timing values:
1. With RD = O (pin 11 shorted to ground) select values tor RT and CT from Figure 7 to give the desired oscillator period. Remember that the frequency at each driver output is half the oscillator frequency, and the frequency at the +Ve terminal is the same as the oscillator frequency.
2. If more dead time is required, select a large value of RD. At 40kHz dead time increases by 400ns/Q .
3. Increasing the dead time will cause the oscillator frequency to decrease slightly. Go back and decrease the value of RT slightly to bring the frequency back to the nominal design value.
The UC1526 can be synchronized to an external logic clock by programming the oscillator to tree-run at a frequency 10% slower than the sync frequency. A periodic LOW logic pulse approximately 0.5µs wide at the SYNC pin will then lock the oscillator to the external frequency.
UC1526 UC2526 UC3526
Multiple devices can be synchronized together by programming one master unit tor the desired frequency and then sharing its sawtooth and clock waveforms with the slave units. All CT terminals are connected to the CT pin of the master, and all SYNC terminals are likewise connected to the SYNC pin of the master. Slave RT terminals are left open or connected to VREF. Slave Ro terminals may be either left open or grounded.
Error Amplifier
The error amplifier is a transconductance design, with an output impedance of 2MQ . Since all voltage gain takes place at the output pin, the open-loop gain/frequency characteristics can be controlled with shunt reactance to ground. When compensated tor unity-gain stability with 1OOpF, the amplifier has an open-loop pole at 800Hz.
The input connections to the error amplifier are determined by the polarity of the switching supply output voltage. For positive supplies, the common-mode voltage is +5.0V and the feedback connections in Figure 6A are used. With negative supplies, the common-mode voltage is ground and the feedback divider is connected between the negative output and the +5.0V reference voltage, as shown in Figure 68.
Output Drivers
The totem-pole output drivers of the UC1526 are designed to source and sink 100mA continuously and 200mA peak. Loads can be driven either from the output pins 13 and 16, or from the +Ve, as required.
Since the bottom transistor of the totem-pole is allowed to
saturate, there is a momentary conduction path from the
+Ve terminal to ground during switching. To limit the re-
sulting current spikes a small resistor in series with pin 14
is always recommended. The resistor value is deter-
mined by the driver supply voltage, and should be chosen
for 200mA peak currents.
n 12 Sync
RTiCT~
Figure 5. Oscillator Connections and Waveforms
5-51
VREF~1 ::
VREF
2 Rl
Po1ltlva
Gnd
Output
Volt·o·
R1
3 2
Gnd
~~,:~:··
Voltage
(R1 + R2\ VouT· Vo1F \~)
=~) VOUT· VREF (
RS·
(
R1R2 ) R1+R2
RS·
(
R1R2 ) R1+R2
UC1526 UC2526 UC3526
To Output Fiiter
Figure 6. Error Amplifier Connections
Figure 8. Single-Ended Configuration
+V Supply o---+-----------.
+15V u------.
Return
Figure 7. Push-Pull Configuration
TYPICAL CHARACTERISTICS
200 100 50 20 10 5 2
T1 Return
Figure 9. Driving N-channel Power Mosfets Oscillator Period vs RT and Cr
01, 02 1N5819
2 5 10 20 50 100 200 500 1ms 2ms 5ms 20ms 100ms 500ms 2S 5S 10ms soms 200ms 1S
Oscillation Period
5-52
TYPICAL CHARACTERISTICS
Output Driver Deadtime vs Ro Value
10
1
9 8
7
v 0
JL
~
~
~
k'.'.1
~ v ....-1
; ],,'.'.'
2
d 1
v Pl
Fosc=40kHz (CT=.01µ F)
J_ J_ J_ J_ J_
0 2 4 6 810121416182022 Ro - (0)
UC1526 UC2526 UC3526
Under Voltage Lockout Characteristic
I
5
-!'-
4
3
2
lL~ 1 J
0 12345
REFERENCE VOLTAGE - (V)
Error Amplifier Open Loop Gain vs Frequency
10 100 1K 10K 100K 1M 10M FREQUENCY - (Hz)
Current Limit Transfer Function
~ 5 f-+-+--+--1--1---t-+--+-+--1
4 f-+---t--+---1--t--+---t--+---t--j 3 >---+-+--+--!-+-+---+-+--+-~ 2 f-+-t--t---l-1---t-t--t--+--1
0 40 80 120 160 200 20 60 100 140 180
DIFFERENTIAL INPUT VOLTAGE - (mV)
Shutdown Delay ~ 1.4 f--+--+--+--~
.a. 1.2 >-----<----<----
-75 -50 -25 0 25 50 75 100 125 150 JUNCTION TEMPERATURE - ('C)
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD.· MERRIMACK, NH 03054 TEL. (603) 424-2410 ·FAX (603) 424-3460
5-53
Output Driver Saturation Voltage
~ ~ 2.0 f--f-+-++++++++--+-+I++++++t--1
~><
0
1.S f---l+l+-H+++++--+-+++t+HfL.,-111
1.0 _I
l-1
.. o.sIIk ~
Source V
CJ)~ O 2
SlnkHl-1
5 10 20 50 100 200
OUTPUT CURRENT
SOURCE OR SINK - (mA)
n. n ~CIRIC NTUEIGTRS ATED
-UNITRODE
Regulating Pulse Width Modulator
UC1526A UC2526A UC3526A
FEATURES Reduced Supply Current Oscillator Frequency to 600kHz Precision Band-Gap Reference 7 to 35V Operation Dual 200mA Source/Sink Outputs Minimum Output Cross-Conduction Double-Pulse Suppression Logic Under-Voltage Lockout Programmable Soft-Start Thermal Shutdown TTLJCMOS Compatible Logic Ports
5 Volt Operation (VIN =Ve =VREF =5.0V)
DESCRIPTION
The UC1526A Series are improved-performance pulse-width modulator circuits intended for direct replacement of equivalent non- "/J\' versions in all applications. Higher frequency operation has been enhanced by several significant improvements including: a more accurate oscillator with less minimum dead time, reduced circuit delays (particularly in current limiting), and an improved output stage with negligible cross-conduction current. Additional improvements include the incorporation of a precision, band-gap reference generator, reduced overall supply current, and the addition of thermal shutdown protection.
Along with these improvements, the UC1526A Series retains the protective features of under-voltage lockout, soft-start, digital current limiting, double pulse suppression logic, and adjustable deadtime. For ease of interfacing, all digital control ports are TTL compatible with active low logic.
Five volt (5V) operation is possible for "logic level" applications by connecting VIN, Ve and VREF to a precision 5V input supply. Consult factory for additional information.
BLOCK DIAGRAM
RREEGFEURLEANTCOER i----...-----...---------------118 VREF
INTERNAL CIRCUITRY
UNDER VOLTAGE LOCKOUT
THERMAL SHUTDOWN
RESET Css
COMP
+EA ·EA +Cs -cs
SOFT START
VIN
6/93
s R
a
s
PWM
a
LATCH
a
5-54
-
8 SHUT
DOWN
ABSOLUTE MAXIMUM RATINGS (Note 1, 2)
Input Voltage (+VIN) .·............................ +40V Collector Supply Voltage (+Ve) ..................... +40V Logic Inputs . . . . · . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +5.5V Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +VIN Source/Sink Load Current (each output) ............ 200mA Reference Load Current .......................... 50mA Logic Sink Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15mA Power Dissipation at TA= +25°C (Note 2) ......... 1000mW Power Dissipation at Tc = +25°C (Note 2) .......... 3000mW Operating Junction Temperature .................. +150°C Storage Temperature Range .............. -65°C to +150°C Lead Temperature (soldering, 1Oseconds) .......... +300°C
Note 1: Values beyond which damage may occur. Note 2: Consult packaging Section of Databook for thermal
limitations and considerations ofpackage.
UC1526A UC2526A UC3526A
RECOMMENDED OPERATING CONDITIONS
(Note 3) Input Voltage .............................. +7V to +35V Collector Supply Voltage . . . . . . . . . . . . . . . . . . +4.5V to +35V Sink/Source Load Current (each output) . . . . . . . . O to 1OOmA Reference Load Current. . . . . . . . . . . . . . . . . . . . . . Oto 20mA Oscillator Frequency Range . . . . . . . . . . . . . . . . 1Hz to 600kHz Oscillator Timing Resistor................... 2kO to 150k0 Oscillator Timing Capacitor................. 400pF to 20µF Available Deadtime Range at 40kHz ..... , . , . , , , 1% to 50% Operating AmbientTemperature Range
UC1526A. . .. .. . . .. . . . . . . . . . . . . . . . . . . -55°C to +125°C UC2526A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25°C to +85°C UC3526A. . . . . . . . . . . . . . . . . . . . . . . · . . . . . . . 0°c to +10°c
Note 3: Range over which the device Is functional and parameter limits are guaranteed.
CONNECTION DIAGRAMS
DIL-18, SOIC-18 (TOP VIEW) J or N Package, DW Package
+ERROR -ERROR
COMP Css
-CURRENT SENSE
+CURRENT SENSE
SHUTDOWN RTIMING
VREF +VIN OUTPUT B GROUND Ve OUTPUT A SYNC RD CT
PLCC-20, LCC-20 (TOPVIEW) Q and L Packages
L3 2 1 2019
4
18~
5
17~
6
16~
7
15~
8
14~
9 10 11 12 13
PACKAGE PIN FUNCTION
FUNCTION
PIN
N/C +ERROR
1..._ ,
2
-ERROR
3
COMP.
4
Css
5
RESET
6
- CURRENT SENSE
7
+ CURRENT SENSE
8
SHUTDOWN
9
RTIMING
10
CT
11
Ro
12
SYNC
13
OUTPUT A
14
Ve
15
N/C
16
GROUND
17
OUTPUTB
18
+VIN
19
VREF
20
5-55
UC1526A UC2526A UC3526A ELECTRICAL CHARACTERISTICS: +V1N = 15V, and over operating ambient temperature, unless otherwise specified TA= TJ.
PARAMETER
TEST CONDITIONS
UC1526A I UC2526A
UC3526A
MIN TYP MAX MIN TYP MAX UNITS
Reference Sectionj!'!ote 4)
OutRut Volta_g_e
TJ=+25°C
4.95 5.00 5.05 4.90 5.00 5.10
v
Line R~ulation
+VIN= 7 to 35V
2
10
2
15 mV
Load R~ulation
IL= Oto 20mA
5
20
5
20 mV
Temperature Stabil!!Y_
Total Output Voltage Ran~
Over O_.e.erati'!9_TJ (Note 5)
Over Recommended Operating Conditions
15
50
15 50 mV
v 4.90 5.00 5.10 4.85 5.00 5.15
Short Circuit Current
VREF=OV
25
50 100 25
50 100 mA
Under-Von~ Lockout RESET Output Voltage
VREF:3.8V VREF= 4.7V
0.2 0.4
0.2 0.4
v
2.4 4.7
2.4 4.8
v
Osclllator SectionJt!ote 6)
Initial Accur~
TJ= +25°C
:t3
:1:8
:t3
:1:8
%
Voltage Stability
+VIN = 7 to 35V
0.5
1
0.5
1
%
Tem_.e.erature Stabi'!!l_
Over Operating TJ (Note 5)
2
6
1
3
%
Minimum Freg_uen~
Rr = 150kQ, CT = 20f!F (Note 5)
1
1
Hz
Maximum Freg_ue~ Sawtooth Peak Volta_g_e Sawtooth Vall~Voltage
RT= 2kQ, Cr= 47~ +VIN=35V +VIN=7V
550
650
kHz
3.0 3.5
3.0 3.5
v
0.5 1.0
0.5 1.0
v
SYNC Pulse Width
TJ = 25°C, RL = 2.7kQ to VREF
Error Amplifier Section {Note 7)
1.1
1.1
f.lS
Input Offset Voltage
Rs:s:2kQ
2
5
2
10 mV
Input Bias Current
-350 -1000
-350 -2000 nA
Input Offset Current
35 100
35 200 nA
DC Open Loop Gain HIGH Output Vol~ LOW Output Volt~e
RL:. 10MQ
64
72
60
72
dB
VPIN 1-VPIN2:.150mV, !SOURCE= 100f'A 3.6 4.2
3.6 4.2
v
VPIN 2 - VPIN 1 :. 150mV, ISINK = 10~
0.2 0.4
0.2 0.4
v
Common Mode Rejection Rs:s:2kQ
70
94
70
94
dB
Sue.!'IY_Voltage Rejection +VIN= 12to 18V
66 80
66
80
dB
PWM Comparator (Note ~
Minimum Duty Cycle
VCOMPENSATION = +0.4V
0
0
%
Maximum Duty Cycle
VcoMPENSATION = +3.6V
D_!i.ltal Ports~YNC, SHUTDOWN, and RESffi
HIGH Output Voltage
!SOURCE = 40f'A
LOW Output Voltage
!SINK= 3.6mA
45
49
45
49
%
2.4 4.0
2.4 4.0
v
0.2 0.4
0.2 0.4
v
HIGH l~ut Current LOW Input Current
VIH= +2.4V VIL= +0.4V
-125 -200 -225 -360
-125 -200 f.lA -225 -360 f.lA
Shutdown Delay
From Pin 8, TJ = 25°C
160
160
ns
Current Limit Comparator (Note 8)
Sense Voltage
Rs:s:50Q
90 100 110 80 100 120 mV
Input Bias Current
-3
-10
Shutdown Delay
From pin 7, 100mV Overdrive, TJ = 25°C
260
Note 4: IL= OmA. Note 5: Guaranteed by design, not 100% tested in production.
= Note 6: Fosc 40kHz, {RT= 4.12kQ :1: 1%, CT= 0.01f.'F± 1%,
Ro=0'2).
= Note 7: VcM O to +5.2V = Note 8: VcM 0to+12V.
Note 9: Ve= +15V.
= Note 10:\IJN +35\1, RT= 4. 12kQ.
-3 -10 f.lA
260
ns
5-56
UC1526A UC2526A UC3526A
ELECTRICAL CHARACTERISTICS: +V1N = 15V, and over operating ambient temperature, unless otherwise specified TA= TJ.
PARAMETER
TEST CONDITIONS
Soft-Start Section
Error Clam...e_VOltaJte
RESET = +0.4V
Cs Charging Current
RESET = +2.4V
Output Drivers (Each Output) (Note 9)
HIGH Output Voltage
!SOURCE = 20mA
!SOURCE = 1OOmA
LOW Output Voltage
!SINK= 20mA
Collector Leak~e Rise Time Fall Time
!SINK= 1OOmA Vc:40V CL= 100~ (Note ~ CL= 100~j_Note 5)
Cross-Conduction Charge Per cycle, TJ = 25°C
Power Consumption (Note 10)
Standby Current
SHUTDOWN = +0.4V
Note 4: IL= OmA. Note 5: Guaranteed by design, not 100% tested in production. Note 6: Fosc = 40kHz, (RT= 4.12/<Q :1: 1%, CT= 0.01µF:1: 1%,
Ro=OQ). Note 7: VcM = 0 to +5.2V Note 8: VCM = 0 to +12V. Note 9: Ve= +15V.
Note 10:1/iN = +35\1, RT= 4. 12/<Q.
UC1526A UC2526A
MIN TYP MAX
UC3526A
UNITS
MIN TYP MAX
0.1 0.4
0.1 0.4 v
50 100 150 50 100 150 !IA
12.5 13.5
12.5 13.5
v
12
13
12 13
v
0.2 0.3
0.2 0.3
v
1.2 2.0
1.2 2.0
v
50 150 0.3 0.6
50 150 !IA
0.3 0.6 µs
0.1 0.2
0.1
0.2 _IA:ll_
8
8
nC
14 20
14 20 mA
Open Loop Test Circuit UC1526A
Ro r-..--...-----1 11
17
+VIN
18
VREF
12
-SY-NC-
5
RESET
4
~SOFT START
7µF
"'="" Ve 14
13
16
15 8
~
APPLICATIONS INFORMATION
Voltage Reference
The reference regulator of the UC1526A is based on a precision band-gap reference, internally trimmed to ±1 % accuracy. The circuitry is fully active at supply voltages above +7V, and provides up to 20mA of load current to external circuitry at +5.0V. In systems where additional current is required, an external PNP transistor can be used to boost the available current. A rugged low frequency audio-type transistor should be used, and lead lengths between the PWM and transistor should be as short as possible to minimize the risk of oscillations. Even so, some types of transistors may require collector-base capacitance for stability. Up to 1 amp of load current can be obtained with excellent regulation if the device selected maintains high current gain.
c·T
"May with
be required some types
__, of transistors
UC1526A REFERENCE
REGULATOR
VREF
15
10µ, F
Figure 1. Extending Reference Output Current
Under-Voltage Lockout
The under-voltage lockout circuit protects the UC1526A and the power devices it controls from inadequate supply voltage, If +VIN is too low, the circuit disables the output drivers and holds the RESET pin LOW. This prevents spurious output pulses while the control circuitry is stabilizing, and holds the soft-start timing capacitor in a discharged state.
The circuit consists of a +1.2V bandgap reference and comparator circuit which is active when the reference voltage has risen to 3VBE or +1.BV at 25°C. When the reference voltage rises to approximately +4.4V, the circuit enables the output drivers and releases the RESET pin, allowing a normal soft-start. The comparator has 350mV of hysteresis to minimize oscillation at the trip point. When +VIN to the PWM is removed and the reference drops to +4.2V, the under-voltage circuit pulls RESET LOW again. The soft-start capacitor is immediately discharged, and the PWM is ready for another soft-start cycle.
The UC1526A can operate from a +5V supply by connecting the VREF pin to the +VIN pin and maintaining the supply between +4.8 and +5.2V.
UC1526A UC2526A UC3526A
VREF
TO RESET TO DRIVER A :>Cl>--~-- TO DRIVER B
,...._,___,~_...
Figure 2. Under-Voltage Lockout Schematic Soft-Start Circuit The soft-start circuit protects the power transistors and rectifier diodes from high current surges during power supply turn-on. When supply voltage is first applied to the UC1526A, the under-voltage lockout circuit holds RESET LOW with 03. 01 is turned on, which holds the soft-start capacitor voltage at zero. The second collector of 01 clamps the output of the error amplifier to ground, guaranteeing zero duty cycle at the driver outputs. When the supply voltage reaches normal operating range, RESET will go HIGH. 01 turns o'f, allowing the internal 1OOµA current source to charge Cs. 02 clamps the error amplifier output to 1VBE above the voltage on Cs. As the soft-start voltage ramps up to +5V, the duty cycle of the PWM linearly increases to whatever value the voltage regulation loop requires for an error null.
VREF
Figure 3. Soft-Start Circuit Schematic Digital Control Ports The three digital control ports of the UC1526A are bi-directional. Each pin can drive TTL and 5V CMOS logic directly, up to a fan-out of 10 low-power Schottky gates. Each pin can also be directly driven by open-collector TTL, open-drain CMOS, and open-collector voltage comparators; fan-in is equivalent to 1 low-power Schottky gate. Each port is normally HIGH; the pin is pulled LOW to activate the particular function. Driving SYNC LOW initiates a discharge cycle in the oscillator. Pulling SHUTDOWN LOW immediately inhibits all PWM output pulses. Holding RESET LOW discharges the soft-start
5-58
APPLICATIONS INFORMATION (cont.) capacitor. The logic threshold is +1.1 V at +25°C. Noise immunity can be gained at the expense of fan-out with an external 2K pull-up resistor to +5V.
VREF
TO INTERNAL
LOGIC
INTEFRRNOAML _ _,___ _,
LOGIC
SHUTDOWN OR RESET
Figure 4. Digital Control Port Schematic
Oscillators The oscillator is programmed for frequency and dead time with three components: RT, CT and RD. Two waveforms are generated: a sawtooth waveform at pin 1Ofor pulse width modulation, and a logic clock at pin 12. The following procedure is recommended for choosing timing values:
1. With RD= OQ (pin 11 shorted to ground) select values for RT and CT from the graph on page 4 to give the desired oscillator period. Remember that the frequency at each driver output is half the oscillator frequency, and the frequency at the +Ve terminal is the same as the oscillator frequency.
2. If more dead time is required, select a larger value of RD. At 40kHz dead time increases by 400ns/Q.
3. Increasing the dead time will cause the oscillator frequency to decrease slightly. Go back and decrease the value of RT slightly to bring the frequency back to the nominal design value.
The UC1526A can be synchronized to an external logic clock by programming the oscillator to free-run at a frequency 10% slower than the SYNC frequency.
A periodic LOW logic pulse approximately 0.5µs wide at
UC1526A UC2526A UC3526A
the SYNC pin will then lock the oscillator to the external frequency.
Multiple devices can be synchronized together by programming one master unit for the desired frequency, and then sharing its sawtooth and clock waveforms with the slave units. All CT terminals are connected to the CT pin of the master and all SYNC terminals are likewise connected to the SYNC pin of the master. Slave RT terminals are left open or connected to VREF. Slave RD terminal may be either left open or grounded.
VAEF~:
VREF
POSITIVE
GND
~gm~E
R1
3 2
GND
egm~:
(R Vour - VREF 1 ~2A2)
~ ~! ) VoUT VREF (
Ra ·
(
R1R2 ) R1 + R2
Ra ·
(
R1R2 ) R1 + R2
Figure 6. Error Amplifier Connections
Error Amplifier
The error amplifier is a transconductance design, with an output impedance of 2MQ. Since all voltage gain takes place at the output pin, the open-loop gain/frequency characteristics can be controlled with shunt reactance to ground. When compensated for unity-gain stability with 1OOpF, the amplifier has an open-loop pole at 800Hz.
The input connections to the error amplifier are determined by the polarity of the switching supply output voltage. For positive supplies, the common-mode voltage is +5.0V and the feedback connections in Figure 6A are used. With negative supplies, the common-mode voltage is ground and the feedback divider is connected between the negative output and the +5.0V reference voltage, as shown in Figure 68.
Figure 5. Oscillator Connections and Waveforms
Figure 7. Push-Pull Configuration 5-59
APPLICATIONS INFORMATION (cont.) Output Drivers
The totem pole output drivers of the UC1526A are designed to source and sink 1OOmA continuously and 200mA peak. Loads can be driven either from the output pins 13 and 16, or from the +Ve, as required.
Since the bottom transistor of the totem-pole is allowed to saturate, there is a momentary conduction path from the
UC1526A UC2526A UC3526A
+Ve terminal to ground during switching; however, improved design has limited this cross-conduction period to less than 50ns. Capacitor decoupling at Ve is recommended and careful grounding of Pin 15 is needed to insure that high peak sink currents from a capacitive load do not cause ground transients.
- - - TO OUTPUT FILTER R2
+15Vn-----
II
Figure 8. Single-Ended Configuration
RETURN
01, 02 1N5819
Figure 9. Driving N-Channel Power MOSFETs
TYPICAL CHARACTERISTICS OSCILLATOR PERIOD vs RT and CT
100 50
a 20
~
"al-: 10 5 2
2 5 10 20 50 100 200 500 1ms 2ms 5ms 10ms OSCILLATION - µsec
OUTPUT BLANKING
20 10 r 5
2 i
r
5
2
v
7
I
i _!:!T -iiD
= =
2KO 00
TJ = 25"C
1
":'t
II)
OUTPUT DEADTIME
5-60
TYPICAL CHARACTERISTICS (Cont.)
Output Driver Deadtime vs. Ro Value
10
~
9 8
7
v lZl
IL
w 6 ::! 5
v k'.'
j:: 4
lLl
5!w
0
3 2
k". J7
1 l7
Fosc = 40kHz-1 (CT = .01µ~j J_ L i _l_ _l_
0 2 4 6 810121416182022 Ro - ( 0)
UC1526A UC2526A UC3526A
Under Voltage Lockout Characteristic
5 r----r---,----t----t_-/_.IL~
~
4 t----t--1---t----l+.--+---<
Im
3 t----t--1---t----l+.--+---< I
IM!
2 t----t--t---t----l+.--+---<
0 1234 5 REFERENCE VOLTAGE - (V)
Error Amplifier Open Loop Gain vs. Frequency
zw
w <!>
ll.. c(
g 0 l-
10 100 1K 10K 100K 1M 10M FREQUENCY - (HERTZ)
Current Limit Transfer Function
~ 5
z 4
~ 3
'
:::c:> 2
(/)
li l
0 40 80 120 160 200 20 60 100 140 180
DIFFERENTIAL INPUT VOLTAGE - (mV)
Shutdown Delay
-75 -25 25 75 125 -50 0 50 100 150
JUNCTION TEMPERATURE - ('C)
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. · MERRIMACK, NH 03054 TEL. (603) 424-2410 · FAX (003) 424-3400
5-61
Output Driver Saturation Voltage ~
~ 2.0
I_<-, 1.5
0 >
~ 1.0
< 0.5
~ I 0
<
Ill
1 2
,~,
5 10 20 50 100 200
OUTPUT CURRENT
SOURCE OR SINK - (mA)
n nINTEGRATED
~CIRCUITS
-UNITRDDE
Power Supply Supervisory Circuit
UC1543 UC1544 UC2543 UC2544 UC3543 UC3544
FEATURES Includes Over-voltage, Under-voltage, And Current Sensing Circuits Internal 1% Accurate Reference Programmable Time Delays SCA "Crowbar" Drive Of 300mA Remote Activation Capability Optional Over-voltage Latch Uncommitted Comparator Inputs For Low Voltage Sensing (UC1544 Series Only)
BLOCK DIAGRAM
DESCRIPTION The monolithic integrated circuits contain all the functions necessary to monitor and control the output of a sophisticated power supply system. Over-voltage (O.V.) sensing with provision to trigger an external SCA "crowbar" shutdown; an undervoltage (U.V.) circuit which can be used to monitor either the output or to sample the input line voltage; and a third op amp/comparator usable for current sensing (C.L.) are all included in this IC, together with an independent, accurate reference generator.
Both over- and under-voltage sensing circuits can be externally programmed for minimum time duration of fault before triggering. All functions contain open collector outputs which can be used independently or wire-or'ed together, and although the SCA trigger is directly connected only to the over-voltage sensing circuit, it may be optionally activated by any of the other outputs, or from an external signal. The O.V. circuit also includes an optional latch and external reset capability.
The UC1544/2455/3544 devices have the added versatility of completely uncommitted inputs to the voltage sensing comparators so that levels less than 2.5V may be monitored by dividing down the internal reference voltage. The current sense circuit may be used with external compensation as a linear amplifier or as a highgain comparator. Although nominally set for zero input offset, a fixed threshold may be added with an external resistor. Instead of current limiting, this circuit may also be used as an additional voltage monitor.
The reference generator circuit is internally trimmed to eliminate the need for external potentiometers and the entire circuit may be powered directly from either the output being monitored or from a separate bias voltage.
U.V. Sense N.I. Input
VREF
U.V. Delay
U.V. Indicate
Ground Inv. Input O.V. Sense
Inv.
N.I.
Remote Reset Activate
(Ground To Activate)
Note: For each terminal, first number refers to 1543 series, second to 1544 series. ·On 1543 series, this function is internally connected to VREF.
6/93
5-62
S.C.R. Trigger O.V. Indicate
ABSOLUTE MAXIMUM RATINGS
Input Supply Voltage, VIN ...................................... 40V Sense Inputs, Voltage Range .............·.................. Oto VIN SCA Trigger Current (Note 1) . . . . . . . .. . . . . . . . . . . .. . . . . . . .. . -600mA Indicator Output Voltage ....................................... 40V Indicator Output Sink Current. . . . . . . . .. .. . . .. . . . . . . . . .. . . . . . . . 50mA Power Dissipation (Package Limitation) ....................... 1000mW Operating Temperature Range
UC1543, UC1544 ................................ -55°C to +125°C UC2543, UC2544 ................................. -25°C to +85°C UC3543, UC3544 .................................. o·cto +10°c Storage Temperature Range ......................... -65°C to +150°C Note 1: At higher input voltages, a dissipation limiting resistor, RG, is required. Note 2: Currents are positive-into, negative-out of the specified terminal. Consult Packaging section of Databook for thermal limitations and considerations of package.
CONNECTION DIAGRAMS
OIL-16, SOIC-16 (TOP VIEW) J or N, OW Package
SCR Trigger 1 Remote Activate
VIN VREF
Ground
UC1543 UC2543 UC3542
OIL-18, SOIC-18 (TOP VIEW) J or N, OW Package
SCR Trigger 1 Remote Activate
C.L. Output
U.V. Input 7 . U.V. Delay
Offset/Comp 11 C.L. N.I. Input
C.L. INV. Input 9 U.V. Indicate
o.V. N.I. Input 6
O.V. Inv. Input 7
UC1543 UC1544 UC2543 UC2544 UC3543 UC3544
UC 1544 UC2544 UC3544
VIN VREF
Ground C.L. Output Offset/Comp C.L. N.I. Input C.L. Inv. Input 11 U.V. Indicate U.V. Delay
PLCC-20, LCC-20 (TOPVIEW) Q or L Package
/3 2 1 2019
4
18~
5
17
6
16
7
15
8
14
9 10 11 .12 13
PACKAGE PIN FUNCTION
FUNCTION
PIN
N/C
1
SCRT[igger
2
Remote Activate
3
Reset
4
O.V. Indicate
5
t-iL_c
6
O.V. Del<W
7
O.V. lr:m.ut
8
i'lL_C
9
i'lL_C
10
U.V. lrm_ut
11
U.V.Del~
12
U.V. Indicate
13
C.L. INV. lrm_ut
14
C.L. N.I. lrm_ut
15
Offse:::U:com_Q_
16
C.L. Out_Q_ut
17
Ground
18
VREF
19
VIN
20
PLCC-20, LCC-20 (TOPVIEW) Q or L Package
L 3 2 1 2019
I 4
18
I 5
17
6
16
7
15
8
14
9 10 11 12 13
5-63
PACKAGE PIN FUNCTION
FUNCTION
PIN
NLC
1
SCRT!jg,Qer
2
Remote Activate 3
Reset
4
O.V. Indicate
5
r::M,C
6
o.V.Del~
7
O.V. N.I. ll}Q_ut
8
O.V. INV. l111Wt
9
U.V. N.I. l!!Q.ut
10
U.V. INV. lrm_ut
11
U.V. Del~
12
U.V. Indicate
13
C.L. INV. lrm_ut
14
C.L. N.I. lrm_ut
15
Offs~Com-2..
16
C.L. Out_Q_ut
17
Ground
18
VREF
19
VIN
20
UC1543 UC1544 UC2543 UC2544 UC3543 UC3544
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA= -55°C to+125°C for the
UC1543 and UC1544; -25°C to +85°C for the UC2543 and UC2544; and o·c to +70°C for the UC3543 and UC3544; and for V1N =
5 to 35V. Electrical tests are performed with VIN= 10V and 2k0 pull-up resistors on all Indicator outputs. All electrical specifications for the UC1544, UC2544, and UC3544 devices are tested with the inverting over-voltage Input and the non-Inverting under-voltage input externally connected to the 2.5V reference. TA = TJ.
PARAMETER
TEST CONDITIONS
Input Voltage Range
TJ = 25°C to TMAX
TMINtoTMAX
Supply Current
VIN = 40V O~ut OJ!.en TJ = 25°C
TMIN :s; TJ :s; TMAX
Reference Section
O~utVo~e O~ut Volta_g_e
TJ = 25°C OverTemJ!.erature Aal!Q_e
Line R1!9_ulatlon
VIN =5to30V
Load Regulation
IREF = 0 to 1OmA
Short Circuit Current
VREF=O
Temperature Stabl[i!y_
SCR Truer Section
Peak Outj:>_ut Current
VIN = 5V AG = 0, Vo= 0
Peak Output Voltage O~ut Off Vo~e
VIN= 15V lo= -100mA VIN =40V
Remote Activate Current A/A Pin= Gnd
Remote Activate Vol11!9.e R/APinQQen
Reset Current
Reset = Gnd, A/A = Gnd
ResetVo~e
Reset ~n A/A= Gnd
Output Current Rise Time AL= 500 TJ = 25°C Co= 0
PrQE.. Del~from A/A
AL=500 TJ=25°C,Co=0
PrQE. Del~from ON i!_!Q_ut AL=500 TJ=25°C Co=O
Comparator Section
Input Threshold (Input voltage rising on O.V. and falling on U.V.)
TJ =25°C Over Temperature Range
UC1543/UC1544 UC2543/UC2544
MIN TVP MAX
4.5
40
4.7
40
7
10
15
UC3543/UC3544 UNITS
MIN TVP MAX
4.5
40 v
4.7
40 v
7
10 mA
15 mA
2.48 2.50 2.52 2.45 2.50 2.55
v
2.45
2.55 2.40
2.60 v
1
5
1
5
mV
1
10
1
10 mV
-12 -20 -40 -12 -20 -40 mA
50
50
l.m!.rnrc
-100 12
-300 13 0 -0.4 2 -0.4 2 400 300 500
-600
0.1 -0.8
6 -0.8
6
-100 12
-300 13 0 -0.4 2 -0.4 2 400 300 500
-600 mA
v
0.1
v
-0.8 mA
6 v
-0.8 mA
6 v
mALI!!. ns
ns
2.45 2.50 2.55 2.40 2.50 2.60
v
2.40
2.60 2.35
2.65 v
l~ut ~steresis
Input Bias Current Del~ Saturation Del~ High Level Del~ Ch~il!Q_ Current Indicate Saturation Indicate Leak~ Propagation Delay
Current Limit Section ln_put Voltage Range ln_2!Jt Bias Current Input Offset Voltage
CMRR AVOL
Ou!Q__ut Saturation
25
25
mV
Sense ll_!Q_ut = OV
-0.3 -1.0
0.2 0.5
6
7
-0.3 -1.0 ~
0.2 0.5
v
6
7
v
Vo=O IL= 10mA
-200 -250 -300 -200 -250 -300 ~
0.2 0.5
0.2 0.5
v
VIND= 40V
.01 1.0
.01
1.0 ~
Input Over Drive= 200mV, TJ = 25°C Co = 0
400
Input Over Drive= 200mV TJ = 25°C, Co= !!!f
10
400
ns
10
ms
Offset Pin Qe_en VcM = O Offset Pin Qe_en, VcM = 0 1OkO from Offset Pin to Gnd 0 :s VCM :s; 12V, VIN = 15V Offset Pin Open, VcM = OV, AL= 10k to 15k0, AVOUT = 1to6V IL= 10mA
0
VIN-3V 0
v V1N:3V
-0.3 -1.0
-0.3 -1.0 ~
0
10
0
10 mV
80 100 120 80 100 120 mV
60 70
60 70
dB
72
80
72
80
dB
0.2 0.5
0.2 0.5
v
Output Leakage Small S!g_nal Bandwidth Pr~ation Del~
VIND= 40V
c Av = OdB TJ = 2s0
VOVERDRIVE = 100mV, TJ = 25°C
.01 1.0 5 200
.01 1.0 µA
5
MHz
200
ns
5-64
SCR Trigger Power Limiting c:
200 t----,RE===cOMMEN:>~===Eo~SERE==='s~GA=-=T=e~-<
RESISTANCE, Ro FOR USE WITH HIGIER SUPPLY VOLTAGES
0 0 5 1015 2025303540 Vt1 SUPPLY VOLTAGE - (V)
UC1543 UC1544 UC2543 UC2544 UC3543 UC3544
Comparator Input Hysteresis
~ I 6JE~ I I ~6~RI
I. VOLTA<¥: INPUT
VOLTAGE HUT
::!..
~ 3
v
~ 0
_}\
v
SENSE INPUT VOLTAGE - (V)
Activation Delay vs Capacitor Value
i
1.0 ~-~--~-~--~ Delay· 2·5 C lo
0.1 f----+ ·10ms I µF
'
~
I
~ .0001 --~~~~-~~-~
.001 .01
0.1
to
10
DELAY TIME - (Miltiseconds)
Current Limit Input Threshold RT THRESHOLD SETTING RESISTOR - ( O)
Current Limit Amplifier Gain
f 80RT~co
RT · 100k
~ 70 RT= ~kO ~ 60 RT· 10k0
1k
10k 100k 1M
FREQUENCY - (Hz)
Note: RT is connected from Offset Pin to Gnd. Values of RT below5.0k may cause Amplifier Cutoffat -55°C.
5-65
Current Limit Amplifier Frequency Response
i 80 ,--........._
VIN· 10V AL· 2kn
ii:
TJ · 25·c
1~ 80 ,.._,......,;::T.1;---j--'~---j---j 180 ~
40
270i
§ 20
360Ilil
~
5M
GAIN MAGlllTUDE - - - PHASE ANGLE - - __ _
UC1543 UC1544 UC2543 UC2544 UC3543 UC3544
APPLICATIONS (Pin numbers given for UC1543 series devices)
Typical Application
The values for the external components are determined
as follows:
Current limit input threshold, VrH = 1~O
cs is determined by the current loop dynamics
Peak current to load, IP· -VR rH +-VRo (~R- 2 ) sc SC ru+R3
Short Circuit Current, lsc = "/:s~
Low output voItage l1.m1.t, .v,o (Low,,1 = 2.5(RR4 +Rs+ R6) 5+ R6
High output voltage limit, Vo (High) - 2·5 (R4 ~:5 + R6)
Voltage sensing delay, to= 10,000Cd
SCR
tn.gger power
11. m.lt.ing
resi.stor,
R
G
>
0VIN2-5
Sensing Multiple Supply Voltages
--------1-- BIAS SUPPLY
TO LM139 COMPARATORS
MAIN POSITIVE
SUPPLY
--------------uC15.i3l
I I I
TO SHUTDOWN CIRCUIT
GROUND
ADDITIONAL POSITIVE SUPPLY
NE~ifpW~ - - - - - " I V V - - + {
VOLTAGE
MASTER POWER SUPPL V CONDITION INDICATOR
Input Line Monitor
INLPUINT EJll
Overcurrent Shutdown
MAIN
SUP:b;
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
<
o
-
BIAS - - - - - - - - - - . VOLTAGE
SCR "CROWBAR"
PIN8~- 2.SV
DELAY
ou~%,----, I OFF
L__J ON
UNITROOE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. · MERRIMACK. NH 03054 TEL (603) 424-2410 · FAX 503-424·3460
SUPPLY
BUS
_ _.._..,,.,,--l~-------------_.~
RETURN
5-66
11 n ·NTElilRATEC
~CIRCUITS
-uNITROCE
UC1575-5/12/15 UC2575-5/12/15 UC2575HV-5/12/15
Simple 1 Amp Step-Down Fixed Voltage Regulators
PRELIMINARY
FEATURES 5V, 12V and 15V Output, ±3% Max Over Line and Load Conditions Guaranteed 1A Output Current Wide Input Voltage Range From VoUT+2V to 40V (60V for HV) Requires Only 4 External Components 52 kHz Fixed Frequency Internal Oscillator Low Power Standby Mode, la Typically < 200 µA Efficiency Typically Over 80% Uses Readily Available Standard Inductors Thermal Shutdown and Current Limit Protection 100% Electrical Thermal Limit Burn-in Replacement for LM2575 Series
APPLICATIONS · Simple High-Efficiency Step-Down (buck)
Regulator · Efficient Pre-Regulator for Linear
Regulators · On-Card Switching Regulators · Positive to Negative Converter (Inverting,
Buck-Boost) · Isolated Flyback Converter using Minimum
Number of External Components · Negative Boost Converter
DESCRIPTION The UC1575/UC2575 family of devices provides all the active functions necessary to implement a simple step-down (buck) switching regulator. Utilizing a minimum number of external components, these regulators offer a simple, high efficiency replacement for popular three-terminal adjustable linear regulators, greatly reducing, and in many cases eliminating, the need for a heat sink.
The UC1575/UC2575 series features an output voltage of 5V, 12V or 15V (see Table 1) and is capable of driving a 1A load while maintaining excellent line and load regulation. Other features include internal frequency compensation, an on-chip fixed frequency oscillator with a ±3% tolerance, and output voltage with ±2% tolerance within specified input voltages and output load conditions. External shutdown with a standby current of 200µA is provided. The output switch includes cycleby-cycle current limiting and thermal shutdown for full protection under fault conditions.
A standard series of inductors and capacitors are available from several manufacturers optimized for use with the UC1575/UC2575 series. This feature greatly simplifies the design of switched mode power supplies.
CONNECTION DIAGRAM
5-PIN T0-220 (TOP VIEW) T-PACKAGE
BLOCK DIAGRAM
Vour
L 0 A D
Note: Pin numbers are tor the T0-220 package
5193
5-67
ABSOLUTE MAXIMUM RATINGS (Note 1) If Military/Aerospace specified devices are required, please contact the UICC Sales Office/Distributors for availability and specifications. Maximum Supply Voltage
UC 1575/UC2575 ..................................................45V UC2575HV ...........................................................63V ON/OFF Pin Input Voltage ......................-0.3 $ V $ +40V Output Voltage to Ground (Steady State) .................. -1V Power Dissipation ................................Internally Limited Storage Temperature Range ................-65°C to +150°C Minimum ESD Rating (C = 100 pF, R = 1.5 kfl) .....................................2 kV FB Pin (Pin 4) ...................................................... 1 kV Lead Temperature (Soldering, 10 sec.) ..........................................260°C
TEST CIRCUIT AND LAYOUT GUIDELINES (Figure 1) C1N .............................. 100 µF, 75V Aluminum Electrolytic Cour ...........................330 µF, 15V Aluminum Electrolytic
220 µF, 15V Aluminum Electrolytic for UC2575-5 D1 ........................................................Schottky, MBR360 L1 .................................330 µH (PE-52627) for UC2575-5
470µH (AIE-430-0634) for UC2575-12 680µH (AIE-415-0935) for UC2575-15 5-Pin T0-220 Socket. ................2936 (Loranger Mfg. Co.) 4-Pin T0-3 Socket... ......................8112-AG7 (Augat Inc.)
UC1575-5/12/15 UC2575-5/12/15 UC2575HV-5/12/15
OPERATING RATINGS Maximum Junction Temperature ...........................150°C Temperature Range
UC1575 ......................................-55°C $ TJ $ +150°c UC2575/UC2575HV ..................-40°C $ TJ $ +125°C
Supply Voltage UC 1575/UC2575 ..................................................40V UC2575HV ...........................................................60V
Order Number For:
Output
Standard Voltage High Voltage Voltage
Rating (40V) Rating (60V)
UC2575T-5.0
UC2575HVT-5.0 5.0
Temperature Range
UC2575T-12
UC2575HVT-12 12.0 ·40°C:<;TJ:<;+125°C
UC2575T-15
UC2575HVT-15 15.0
UC1575K·5.0
5.0
UC1575K·12
12.0 -55°C:<;TJ:<;+150°C
UC1575K·15
15.0
TABLE 1
UC2575HV
FEEDBACK 4
L1
UNREGULATED
3 ON/OFF 5
L
DC INPUT*
0
A
D
FIGURE 1
Note: Pin numbers are for the T0-220 package
* 7-40V (60HV) for-5, 15-35V (60HV) for-12, 17-40V (60HV) for-15
As in any switching regulator, layout is very important. Rapidly switching currents associated with wiring inductance generate voltage transients which can cause problems. For minimal stray inductance and ground loops, the length of the leads indicated by heavy lines should be kept as shon as possible. Single-point grounding (as indicated) or ground plane construction should be used for best results.
5-68
UC1575-12 UC2575-12 UC2575HV-12
ELECTRICAL CHARACTERISTICS: (Unless otherwise stated, these specifications apply for TA=-55°C to + 150°C for UC1575-12 and -40°C to +125°C for the UC2575-12/UC2575HV-12, TA=TJ). Unless otherwise specified, V1N = 25V, and ILOAD = 200mA.
UC1575-12
PARAMETER
TEST CONDITIONS
SYSTEM PARAMETERS (Note 2) Test Circuit Figure 1
Output Voltage ----
Output Voltage UC1575/UC2575
Output Voltage UC2575HV
VIN = 25V, ILOAD = 0.2A Circuit of Figure!, TJ =_25°C_
4ov- 0.2A $ ILOAD $ 1A,15V $VIN$
Circuit of Figure 1 TJ = 25°c
0.2A s ILOAD s 1A, 15V s VIN s 60V
Circuit of Figure 1 TJ = 25°C
Efficiency
VIN= 15V, ILOAD = 1A, VouT = 12V
-- -·-- ------· .
- ·-------·-·---~
DEVICE PARAMETERS
Oscillator Frequency
(Note 9)
TJ = 25°c
Saturation Voltage
t--· Max Duty Cycle (ON) Current Limit
louT = 1A (Note 3) TJ = 25°
(Note 4) TJ = 25° Peak Current (Note 3) TJ = 25°C
Output Leakage Current
VIN= 40V, TJ = 25°C, Output= OV
VIN = 60V for HV
Output= -1 V
(Note 6)
Output= -1V
Quiescent Current
(Note 6)
t· - - - - - - - - - - - Standby Quiescent
TJ = 25°c
- · - - - · - --~-·-·-
·-- --- --
------
ON/OFF Pin = 5V (OFF)
Current
TJ = 25°c
- -- - - - - - - - - - --------·
Thermal Resistance
K Package, Junction to Ambient
K Package, Junction to Case
T Package, Junction to Ambient (Note 7)
T Package, Junction to Ambient (Note 8) T Package, Junction to Case
ON/OFF CONTROL Test Circuit Figure 1
ON/OFF Pin Logic Input Level
VouT= ov
VoUT= 5V
ON/OFF Pin Input Current
TJ = 25°c
I ON/OFF Pin = 5V (OFF) {!~=?~·C) 0N10Fl=f>in·:av(o-N)- (TJ = 25°C)
MIN. 11.88 11.52 11.64
43 47 93 1.3 1.7
2.4 2.2
TYP. 12.0 12.0
88
52 0.9 98 2.2 7.5 5 50 35 1.5
1.5 1.4 12 0
MAX.
12.12 12.48 12.36
62 58 1.4 1.2 3.2 3.0 2 30 12 10 500 200
0.8 1.0 30 10
UC2575-12 UC2575HV-12
MIN. TYP. MAX.
11.76 11.40 11.52 11.40
11.52
12.0 12.0 12.0
88
12.24 12.60 12.48 12.65
12.52
42
63
52
47
58
0.9
1.4
- 1.2
93 -~~-
1.3
3.2
1.7
2.2
3.0
2 7.5
30
5
12
10
500
50
200
65 45 2
2.4
1.5
1.4
0.8
2.2
1.0
12
30
0
10
UNITS
v v v
%
KHz
v
% -
A mA mA µA
0 c1w
v
µA µA
5-69
UC1575-15 UC2575-15 UC2575HV-15
ELECTRICAL CHARACTERISTICS: (Unless otherwise stated, these specifications apply for TA=-55°C to +150°C for UC1575-15 and -40°C to +125°C for the UC2575-15/UC2575-15HV, TA=TJ). Unless otherwise specified, V1N = 30V, and ILOAD = 200mA.
UC1575-15
UC2575-15 UC2575HV-15
PARAMETER
TEST CONDITIONS
SYSTEM PARAMETERS (Note 2) Test Circuit Figure 1
Output Voltage
Output Voltage UC1575/UC2575
VIN = 30V, ILOAD = 0.2A Circuit of Figure1, TJ = 25°C
0.2As ILOAD s 1A,18Vs V1NS40V Circuit of Figure 1 TJ = 25°c
Output Voltage UC2575HV
0.2A S !LOAD S 1A, 18V S VIN S GOV Circuit of Figure 1
TJ = 25°c
Efficiency
VIN= 18V, !LOAD= 1A, VOUT = 15V
DEVICE PARAMETERS
Oscillator Frequency
(Note 9)
TJ = 25°c
Saturation Voltage
l"" Max Duty Cycle (ON) Current Limit
louT = 1A (Note 3) TJ = 25°
(Note 4) TJ = 25° Peak Current (Note 3) TJ = 2s0 c
Output Leakage Current
VIN= 40V,TJ = 25°C, Output= OV
VIN = GOV for HV
Output= -1V
(Note G)
Output= -1V
MIN. TYP. MAX. MIN. TYP. MAX. UNITS
14.85 15.0 15.15 14.70 15.0 15.30
v
14.40
15.GO 14.25
15.75
15.0
15.0
v
14.55
15.45 14.40
15.GO
14.25
15.83
15.0
v
14.40
15.G8
88
88
%
43
G2
42
G3
52
52
KHz
47
58
47
58
0.9
1.4
1.2
0.9
1.4
v
1.2
93
98
93
98
%
1.3
3.2
1.3
3.2
2.2
2.2
A
1.7
3.0
1.7
3.0
2 7.5
30
2
7.5
mA
30
Quiescent Current
Standby Quiescent Current Thermal Resistance
(Note G) TJ = 25°c
ON/OFF Pin = 5V (OFF) TJ = 25°C
K Package, Junction to Ambient K Package, Junction to Case T Package, Junction to Ambient (Note 7) T Package, Junction to Ambient (Note 8) T Package, Junction to Case
5
12
10
50
500
200
35 1.5
5
12
mA
10
50
500
µA
200
G5
0 c1w
45
2
ON/OFF CONTROL Test Circuit Figure 1
~
ON/OFF Pin Logic
Input Level
Vour= ov
VouT= 5V
2.4 1.5
2.4
1.5
1.4
0.8
1.4
0.8
v
ON/OFF Pin Input Current
TJ = 2s0 c ON/OFF Pin= 5V (OFF) (TJ = 25°C) ON/OFF Pin= OV (ON) (TJ = 25°C)
2.2
1.0
2.2
1.0
12
30
12
30
µA
0
10
0
10
µA
5-70
UC1575-5/12/15 UC2575-5/12/15 UC2575HV-5/12/15
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics.
Note 2: External components such as the catch diode. Inductor, input and output capacitors can affect switching regulator system performance. When the UC15751UC2575 ls used as shown in the Figure 1 test circuit, system performance will be as shown in system parameters section of Electrical Characteristics
Note 3: Output (pin 2) sourcing current. No diode, inductor or capacitor connected to output.
Note 4: Feedback (pin 4) removed from output and connected to OV.
Note 5: Feedback (pin 4) removed from output and connected to 12V to force the output transistor OFF.
Note 6; Feedback (pin 4) removed from output and connected to 25V to force the output transistor OFF.
Note 7: Junction to ambient thermal resistance (no external heat sink) for the 5 lead T0-220 package mounted vertically, with 112 inch leads in a socket, or on a PC board with minimum copper area.
Note 8: Junction to ambient thermal resistance (no external heat sink) for the 5 lead T0-220 package mounted vertically, with 114 inch leads soldered to a PC board containing approximately 4 square inches of copper area surrounding the leads.
Note 9: The oscillator frequency reduces to approximately 18 kHz in the event of an output short or an overload which pulls the output lower than 3V for UC2575-5.0, or lower than 7.2V for UC2575-12 and lower than 9V for UC2575-15. This self protection features lowers the average power dissipation of the IC by lowering the minimum duty cycle from 5% down to approximately 2%.
Note 10: Refer to RETS UC1575K For current revision of military RETSISMD.
Typical Performance Characteristics (Circuit of Figure 1)
UC1575-5.0/UC2575-5.0
Normalized
>
Output Voltage
s_+100~~~~~--~
~ +?S
ILOA(~~N2~;~
~ +50 !--+--+-+-+-< NOJmalized at
:c
T .. 25°C
u +251-1-+-+--t--+--,r-T-r-I
;~: ot-ti-,+.:.t:";"l..-t-'1"'11-tN~~
~ -25
>-- ·50 l-l-+-+-+-+-1r-t-+-I
~ -751-+-+-+--+-+-ll-+-+-l
f--
6 -10Ss -50 -25 0 25 fl) 75100125150
JUNCTION TEMPERATURE (;C)
Supply Current
20
.s<C 18 16
§ 14
l
MEASURED AT GROUND PIN
l
TJ·25"C
l
~
u
~ g;
"'
~ iLOAO·lA
12 10
~
~ 8 ILOAD · 200mA
6 4
l
r-=F"
0 10 20 30 40 50 60
INPUT VOLTAGE (V)
Line Regulation
~ 60 Normakzea To V1N .. lOV
~ ~
u ~
~
§;
50 ~Jo:~.~OOmA ~P-'
40
v
30
v 20
10
!J 0
t;
~ -10 -20
0 10 20 30 40 50 60
INPUT VOLTAGE (VJ
Efficiency
100
J..,. 25·c
95
-~
90 85
G 80
~ 75
~ 70
65
60
1
ILOAD· 1A
:JI t::::I I r-
~
I " ILOAO · 200mA
l
0 10 20 30 40 50 60
INPUT VOLTAGE (VJ
UC1575-12/UC2575-12
Normalized
> Output Voltage
.s +100
VIN a25V
"'UJ +75 ILOAO· 20<mA
~
+50
Normalized at
TJ .2s·c
~ +25
w
~
§;
-25 -50
IL J:a
1-N
~
~ -75
::> -100
0
·75-50 ·25 0 25 50 75100125150
JUNCTION TEMPERATURE (;C)
Supply Current
20~~~~-.,..~~~
<
.S.151-t-+-+-+-+-+--+--1 !;;:
g~:;
i u 51-t-+-+-I O'--'--'--'-'----~ 0 5 10 15 20 25 30 35 40 INPUT VOLTAGE (V)
Lina Regulation
~ +100 NormalizedToV1N·25V
+75 ILOAO · 200mA ~~-1--i
~
TJ·25°C
~
+501--~~-+-t--+--t
u +251--+--+-+-..-1-1-11--tt-1=:1
~ or-+.....-1--i+-'bo-l""'+-+--t
'.:; -251----+-+-l--+--l
§; t;
.501---+--+-+-l--+--t
~
0
-751---+--+-+-l--+--I · 100 .__....__.___.__.___,___.
0 5 10 15 2025 30 35 40
INPUT VOLTAGE (V)
Efficiency
100
..1 ..1
iLOA0· 1A
90
,~.. 80 t--it--i IL~~-20CmA ~
u
iE 70
'3
tt 60
50
10 15 20 25 30 35 40 INPUT VOLTAGE (VJ
5-71
UC1575-15/UC2575-15
Normalized
> +100 Output Voltage
~ VIN ·'ZN
+75 lto110·200mA
~
Normalzed at
+50 TJ·WC
~ +25
(.)
~ -2~
~
171 I"
~ -50 ~ -75
~ -1 ~~5-50-25 0 25 5075100125150
JUNCTION TEMPERATURE (Cl)
Supply Current
20
MEASURED AT
- 18
§. 16
GROUND PIN TJ· 25°C
~ 14
~ 12
v :(:.:J) 10
~
""" g;~ 8
~
ILOAO · 20DmA
6
ILOAO ·IA
"' 4 0 10 20 30 40 50 60
INPUT VOLTAGE (V)
UC1575-5/12/15 UC2575-5/12/15 UC2575HV-5/12/15
Una Regulation
_751-4--4-+--l---I
- 10~0 20 30 40 50 60
INPUT VOLTAGE (V)
Efficiency
100
-r;;;f·IA
90
1i:
~BO
E.T.-
iii 70
<3
~ 60
50 10 20 30 40 50 60 INPUT VOLTAGE (V)
Other Characteristics:
Current Limit 3
\IN· 25V
g
!'-.
!z
~
"-H-
B
'::;
~
0 0
-75 -50-25 0 25 50 75100125150
JUNCTION TEMPERATURE (°C)
Switch Saturation Voltage 1.2 .-.~~.-r~~.-r-.
~ ~ 1.0
~ l-+-1$=F'1Ffc±....ir-to~ ~ 0.8 1--+c:;_~~
0>~= 0.6 H~S-IF+-f-+--11-+-i
~
0.4 L.....l.-'-.L.....IL.....1.--'-.L.....IL.....L-.J 0 0.2 0.4 0.6 0.8 1.0
SWITCH CURRENT (A)
Standby
Quiescent Current
~200
., ·..,vT::P
i 150
cc
1--1 I l IITJ
:::J
(.) 100
15 ffi 50
~
~ 0
"""
VmJ'IOFF a5V
TTT
vu~ · Vour + 2V i...-
:Hf
~ -75-50-25 0 25 50 75100125150 JUNCTION TEMPERATURE ("C)
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD· MERRIMACK, Nfl 03054 TEL. 603-424-2410 ·FAX 603-424-3460
5-72
n n l'.:::::::'.._!
INT&GiRATliD CIRCUITS
-UNITRODE
UC1575-ADJ UC2575-ADJ UC2575HV-ADJ
Simple 1 Amp Step-Down Voltage Regulator
PRELIMINARY
FEATURES
· Adjustable Output · Reference Voltage ±2% Max Over Line
and Load Conditions · Guaranteed 1A Output Current · Wide Input Voltage Range, 4V to 40V
(60Vfor HV) · Wide Output Voltage Range, 1.23V to
37V (57V for HV) · Requires Only 6 External Components · 52 kHz Fixed Frequency Internal
Oscillator Low Power Standby Mode, lo Typically < 200 µA Efficiency Typically Over 80% Uses Readily Available Standard Inductors · Thermal Shutdown and Current Limit Protection 100% Electrical Thermal Limit Burn-in · Replacement for LM2575 Series
DESCRIPTION The UC 1575-ADJ family of devices provides all the active functions necessary to implement a simple step-down (buck) switching regulator. Utilizing a minimum number of external components, these regulators offer a simple, high efficiency replacement for popular three-terminal adjustable linear regulators, greatly reducing, and in many cases eliminating the need for a heat sink.
The UC1575-ADJ series features an output voltage which is adjustable from 1.23V to 37V (57V for the HV version) and is capable of driving a 1A load while maintaining excellent line and load regulation. Other features include internal frequency compensation, an on-chip fixed frequency oscillator with a ±10% tolerance, and output voltage with ±2% tolerance within specified input voltages and output load conditions. External shutdown with a standby current of 200µA is provided. The output switch includes cycle-by-cycle current limiting and thermal shutdown for full protection under fault conditions.
A standard series of inductors and capacitors are available from several manufacturers optimized for use with the UC1575-ADJ series. This feature greatly simplifies the design of switched mode power supplies.
APPLICATIONS · Simple High-Efficiency Step-Down (buck)
Regulator · Efficient Pre-Regulator for Linear
Regulators · On-card Switching Regulators · Positive to Negative Converter (Inverting,
Buck-Boost) · Isolated Flyback Converter Using
Minimum Number of External Components · Negative Boost Converter
CONNECTION DIAGRAM
5-PIN T0-220 (TOP VIEW) T-PACKAGE
BLOCK DIAGRAM
Your
L 0 A 0
Note: Pin numbers are for the T0-220 package
5193
5-73
ABSOLUTE MAXIMUM RATINGS (Note 1) If Military/Aerospace specified devices are required, please contact the UICC Sales Office/Distributors for availability and specifications.
Maximum Supply Voltage UC 1575/UC2575..................................................45V UC2575HV ...........................................................63V
ON/OFF Pin Input Voltage ......................-0.3:::; V:::; +40V Output Voltage to Ground (Steady State) ..................-1V Power Dissipation ................................Internally Limited
Storage Temperature Range ................-65°C to+ 150°C Minimum ESD Rating
(C = 100 pF, R = 1.5 kQ) .....................................2 kV FB Pin (Pin 4) ......................................................1 kV
Lead Temperature (Soldering, 10 sec.) ..........................................260°C
UC1575-ADJ UC2575-ADJ UC2575HV-ADJ
OPERATING RATINGS Maximum Junction Temperature ...........................150°C Temperature Range
UC1575 .....................................-55°C:::; TJ:::; +150°C UC2575/UC2575HV ..................-40°C:::; TJ :::; +125°C
Supply Voltage UC 1575/UC2575 ..................................................40V UC2575HV ...........................................................60V
TEST CIRCUIT AND LAYOUT GUIDELINES (Figure 1)
CiN ............................. 100 µF, 75V Aluminum Electrolytic Cour ..........................470 µF, 15V Aluminum Electrolytic D1 .......................................................Schottky, MBR360 L1 ...............................................330 µH, 415-0926 (AIE)
R1 .......................................1k, 0.1%, R2 = 3.065k, 0.1% 5-Pin T0-220 Socket... .............2936 (Loranger Mfg. Co.) 4-Pin T0-3 Socket ........................8112-AG7 (Augat Inc.)
7V-60V UNREGULATED
DC INPUT
FEEDBACK
4
UC2575HV-ADJ
L1
3 ON/OFF
Cour
470 µF
Vour
5.00V
R2 L 0 A
R1 D
Note: Pin numbers are for the T0-220 package
FIGURE 1
As in any switching regulator, layout is very important. Rapidly switching currents associated with wiring inductance generate voltage transients which can cause problems. For minimal stray inductance and ground loops, the length of the leads indicated by heavy lines should be kept as short as possible. Single-point grounding (as indicated) or ground plane construction should be used for best results.
5-74
UC1575-ADJ UC2575-ADJ UC2575HV-ADJ
ELECTRICAL CHARACTERISTICS: (Unless otherwise stated, these specRications apply for TA=-55°C to+150°C for UC1575
and -40°C to +125°C for the UC2575/UC2575HV, TA=TJ). Unless otherwise specified, VIN = 12V and ILOAD = 200 mA.
UC1575-ADJ
PARAMETER
TEST CONDITIONS
SYSTEM PARAMETERS (Note 2) Test Circuit Figure 1
Feedback Voltage
Feedback Voltage UC1575/UC2575
VIN= 12V, ILOAD = 0.2A VouT = 5V, TJ = 25°C Circuit of Figure1
0.2A,, ILOAD $ 1A, av$ VIN $ 40V VouT = 5V, Circuit of Figure 1 TJ = 25°C
Feedback Voltage UC2575HV
0.2A,, ILOAD $ 1A, av$ VIN $ GOV VouT = 5V, Circuit of Figure 1 TJ = 25°C
Efficiency
VIN= 12V, ILOAD = 1A, VouT = 5V
DEVICE PARAMETERS
Feedback Bias Current
VouT= 5V TJ = 25°C
Oscillator Frequency
(Note a)
TJ = 25°C
Saturation Voltage
M_<i~_Duty Cycle (ON) Current Limit
louT = 1A (Note 3) TJ = 25°
(Note 4) TJ = 25° Peak Current (Note 3) TJ = 25°C
Output Leakage Current
VIN= 40V, TJ = 25°C, Output= OV
VIN = GOV for HV
Output= -1V
(Note 5)
Output= -1V
Quiescent Current
Standby Quiescent Current
(Note 5)
TJ = 25°C ON/OFF Pin = 5V (OFF) TJ = 25°C
Thermal Resistance
K Package, Junction to Ambient K Package, Junction to Case T Package, Junction to Ambient (Note G) T Package, Junction to Ambient (Note 7) T Package, Junction to Case
ON/OFF CONTROL Test Circuit Figure 1
ON/OFF Pin Logic Input Level
VouT = OV VoUT= 5V
ON/OFF Pin Input Current
TJ = 25°C ()f\J1()£F Piri =-~V'_L()Ef')__(,T_J_=__25°CJ_ ON/OFF Pin = OV (ON) (TJ = 25°C)
MIN. 1.217 1.193 1.205
43 47 93 1.3 1.7
2.4 2.2
TYP.
1.230 1.230
a2
50 52 0.9 9a 2.2 7.5 5 50 35 1.5
1.5 1.4 12 0
MAX.
1.243 1.2G7 1.255
500 100 G2 5a 1.4 1.2 3.2 3.0
2 30 12 10 500 200
o.a 1.0 30 10
UC2575-ADJ UC2575HV-ADJ
MIN. TYP. MAX.
1.217 1.230 1.243
1.1ao 1.193 uao 1.193
1.230
1.230 a2
1.2ao 1.2G7 1.2aG 1.273
50
500
100
42
G3
52
47
5a
0.9
1.4
1.2
93
9a
1.3
3.2
1.7
2.2
3.0
2 7.5
30
5
12
10
50
500 200
G5 45 2
2.4
1.5
1.4
o.a
2.2
1.0
12
30
0
10
UNITS
v
v v % nA KHz v % A mA mA µA
·cNoJ
v ~ µA
5-75
UC1575-ADJ UC2575-ADJ UC2575HV-ADJ
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics.
Note 2: External components such as the catch diode. Inductor, input and output capacitors can affect switching regulator system performance. When the UC15751UC2575 Is used as shown in the Figure 1 test circuit, system performance will be as shown in system parameters section of Electrical Characteristics.
Note 3: Output (pin 2) sourcing current. No diode, inductor or capacitor connected to output.
Note 4: Feedback (pin 4) removed from output and connected to OV.
Note 5: Feedback (pin 4) removed from output and connected to 12V to force the output transistor OFF.
Note 6: Junction to ambient thermal resistance (no external heat sink) for the 5 /ead T0-220 package mounted vertically, with 112 inch leads in a socket, or on a PC board with minimum copper area.
Note 7: Junction to ambient thermal resistance (no external heat sink) for the 5 lead T0-220 package mounted vertically, with 114 inch
leads soldered to a PC board containing approximately 4 square inches of copper area surrounding the leads.
Note 8: The oscillator frequency reduces to approximately 18 kHz in the event of an output short or an overload which pulls the feedback voltage lower than .lV. This self protection feature lowers the average power dissipation of the IC by lowering the minimum duty cycle from 5% down to approximately 2%.
Note 9: Refer to RETS UC1575K-ADJ For current revision of military RETS!SMD.
Typical Performance Characteristics (Circuit of Figure 1)
S~ly Current 20
MEASURED AT
1 18 16
GROUND PIN TJ= 25'C
vour =5V
~ 14
~\.oAO·lA
aa::
~
:"::->
12 10
~ ~
8 lt.o ~· 200mA
6
(/)
4
0 10 20 30 40 50 60
INPUT VOLTAGE (V)
Supply Current
vs Duty Cycle 20.0
< 17.5
~ 15.0
iagi:si:
12.5
10.0
(.)
'.'.:; 7.5
~ 5.0
7
~
V1N= 7V lL.
~~ ~ ~ V1N= 40V
I LOAD= 200 mA
~ 2.5
0 0 20 40 60 80 100
DUTY CYCLE(%)
Normalized
~
Feedback Voltage
25
w
~
g -
20 H
I-+-
VIN= 12V I LOAD = 200 mA
15 t--H 10 t- H-
Normalized to TJ
=25°c
5
~"" -5 ~
1-1
~Q -10 -15
~ -20
_, -25
~ -75-50-25 0 25 50 75100125150
~ JUNCTION TEMPERATURE ('C)
Switch
Saturation Voltage
l 1.2
~
I w
~C!J 1.0 55°CH ..-i-i
I-
i.d--
> 0 ~ ;::: ~
:::>
~
0.8 0.6 0.4
!g§lC i.-1-1
_r
h_5o·c i.A-1
J"J
I
~i -
0 0.2 0.4 0.6 0.8 1.0
SWITCH CURRENT (A)
Standby
1 200 Quiescent Current
~
aa:::: 150
:::>
....-t"'""
VIN= 40V i--
]_
I
(.)
!Z 100
w
(.)
ViiNtoFF= 5V
I
ffi
5
0
>a>
Q
~
VIN= 12V I---
50 H i-
I
0
I
-75 -50 -25 0 25 50 75100125150
"' JUNCTION TEMPERATURE (°C)
100 Efficiency
..., - 95
1--!!J 1i 90
~ 85
iii 80
Vour = 12v
t-1t......
200 mA--j~
200mA
t:5 75
Hi 70 1~
r-.... Vour .:w
65
60 0 10 20 30 40 · 50 60
INPUT VOLTAGE (V)
5-76
UC1575 Serles Buck Regulator Design Procedure
PROCEDURE
Given: Vour = Regulated Output Voltage VIN (max) = Minimum Input Voltage ILOAD (max) = Maximum Load Current F = Switching Frequency (52kHz)
Example: Vour = 10V, VIN (max)= 25V, ILOAD (max)= 1A, F = 52kHz.
UC1575-ADJ UC2575-ADJ UC2575HV-ADJ
1. Programming Output Voltage (Selecting R1 and R2J
The following formula can be used to select the resistor values for a given voltage:
Vour = VREF (1 + =~)
And for a given R1 (between 1Kand 1OK),
1) R2 = R1 (VOUT VREF
) Example:
Vour = 1.23 ( 1+ =~
select R1 = 1K:
- R2 = R1 { ~~~; - 1) = 1k { 1~g:v 1 ) = 7.13K, use closest 1% value 7.15K.
2. Inductor Selection (L1)
A. Calculate E·T(V·µS), from the following formula:
E·T
=(VIN
-
Vour)
·
VVOIUNT
·
1000 F(in kHz)
(V·µS)
B. Use the E·T value from above and match it with the E·T number on the vertical axis of the Inductor value selection
guide shown in Figure 2.
C. On the horizontal axis, select the minimum load current. Find the region intersected by the E·T value and the maximum load current value and note the .inductor code for the region.
D. Match the inductor code to the inductor value, using Fig. 3.
Example:
Calculating E·T (V·µS):
E·T = (25 - 10) .1-0 .10- 00 = 115 V·µS 25 52
For ILoAo = 1A and E·T = 115V·µS, Inductor code is H470 and the inductor value is 470µH.
3. Output Capacitor Selection (Cour) A. The dominant pole-pair of the switching regulator loop is defined by the value of the output capacitor and the inductor. In order to achieve stable operation the capacitor must satisfy the following requirement.
VIN (max) Cour > 7,785 · Vour · L(µH) (µF)
Example:
25 Cour > 7,785 · - - - = 130µF
10. 150
For acceptable ripple voltage, select Cour = 220µF electrolytic capacitor.
5-77
UC1575-ADJ UC2575-ADJ UC2575HV-ADJ The ESR (Equivalent Series Resistance) of the output capacitor is the primary cause of the output ripple voltage and the value and the type of the output capacitor determine the amount of ESR and thus the output ripple voltage. In general lower capacitor values have higher ESR ratings.
Capacitor values larger than 680µF will produce an output ripple voltage of 35mV to 50mV, while smaller capacitors (220µF to 680µF) will typicaly cause a ripple of 50mV to 150mV. The following approximate relationship could be used in determining the output ripple:
VRIPPLE p-p > 0.3 x ILOAD(max) x ESR
It is possible to reduce the output ripple to 1OmV-20mV by using several standard electrolytic capacitors in parallel or by using higher grade capacitors with low ESR and low inductance. However, ESR values lower than 0.05 Ohms can cause instability. The capacitor's ripple current rating at 52kHz should be at least 50% higher than the inductor current ripple:
IRIPPLE(max) > 1.5 x 0.3 x ILOAD(max)
B. The voltage rating of the output capacitor should be at least 1.2 times greater that the output voltage. For a 1OV output, a rating of 15V is appropriate, and a 20V rating is recommended.
4. Catch Diode Selection (01)
The current rating of the catch diode must be at least 1.2 times greater than the maximum load current, unless the diode is expected to withstand a continuous output short, in which case the current rating of the diode should be equal to the maximum current rating of UC2575.
A. The reverse voltage rating of the diode should be at least 1.25 times the maximum input voltage.
B. Schottky diodes with fast switching speed and a low forward voltage drop are the most efficient. Some types of diodes with an abrupt turn-off characteristic may cause instability and EMI problems. Therefore in general, a fastrecovery diode with soft recovery characteristics is recommended.
See Figure 4 for Schottky and "soft" fast-recovery diode selection guide.
5. Input Capacitor (CIN)
To assure stability, the regulator input pin must be bypassed with a by-pass capacitor of at least 47µF, low ESR (electrolytic type). If an operation at low temperatures (for example -25°C) is intended, then addition of a ceramic or solid tantalum capacitor near the input pin may be required to maintain the capacitance value and low ESR at low temperature.
200
150 125
100
.ti) 80
:::!. 70
.c 60
I- 50
UJ
40
30
20 ~--~-~~~-~~~~~
0.2
0.3 0.4 0.5 0.6 0.70.80.91.0
MAXIMUM LOAD CURRENT (A)
Figure 2. Inductor Value Selection Guide {for Continuous Mode Operation)
5-78
UC1575-ADJ UC2575-ADJ UC2575HV-ADJ
Inductor Code
L47 L68
Inductor Value
47 µH 68 µH
AIE (Note 1) 415-0932
415-0931
Pulse Eng. (Note 2) PE-53112
PE-92114
Renco (Note 3) RL2442
RL2443
L100 L150 L220 L330 1-- -- --- --L--4--7--0-- L680
100 µH 150 µH 220 µH 330 µH
----+------ 470 µ~
680 µH
415-0926 415-0953 415-0922 415-0926
PE-52627 PE-53113 PE-52626 PE-52627
RL 1952 RL 1954 RL 1953 RL i 952
___ +--41_5_-0_9_2_7_+-__P_E_-5_3_11_4_--+__R_L_19_5_1__1
415-0928
PE-52629
RL 1950
H150
150 µH
415-0936
PE-53115
RL2445
l-----------H2_2_0- - - - - - - - - 1 -_ _ _ _2_2_0~µ_H_ _ _ _ _4_ _4_3_0_-0_6_36_---1_ _ _P_E_-_53_1_1_6_---1-_ _R_L2_4_4_6_____,
H330
330 µH
430-0635
PE-53117
RL2447
1-----H4_7_0 _ -----+----4_7_0~µ_H_ _ _-+--_43_0_-0_6_3_4_-1--__P_E_-5_3_11_8_--+__R_L_19_6_1_ __,
H680 H1000
,
680 µH __ _ 415-0935
I
1000 µH
415-0934
PE-53119 PE-53120
RL 1960 RL 1959
H1500 H2200
1500 µH 2200 µH
415-0933 415-0945
PE-53121 PE-53122
RL1958 RL2448
Note 1: AIE Magnetics, Div. Vernitron Corp. Passive Components Group, (813) 347-2181 2801 72nd Street North, St. Petersburg, FL 33710
Note 2: Pulse Engineering, (619) 268-2400 P.O. Box 12235, San Diego, CA 92112
Note 3: Renea Electronics Inc., 60 Jeffnyn Blvd. East, Deer Park, NY 11 729 (516) 586-5566
FIGURE 3. Inductor Selection by Manufacturer's Part Number
VIN (max)
20V
Schottky
--
1A 3A --- -·--------·-- -------
1N5817 1N5820
MBR120P MBR320P
SR102
SR302
Fast Recovery
1A
3A
30V
40V
50V 1----
60V
1N5818 MBR130P 110003
SR103
1N5819 MBR140P 110004
SR104
MBR150 110005 SR105
MBR1601 110006 SR106
1N5821 MBR330 310003 SR303
1 N5822 MBR340 310004 SR304
MBR350 310005 SR305
MBR3603 310006 SR306
The following diodes are all rated to 100V
11DF1 MUR110 HER102
The following diodes are all rated to 100V
31 DF1 MUR310 HER302
Figure 4. Diode Selection Chart
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD.· MERRIMACK, NH 03054 TEL 603-424·2410· FAX 603-424-3460
5-79
n n INTEG.RATED
~CIRCUITS
-UNITRODE
UC1576-5/12/15 UC2576-5/12/15 UC2576HV-5/12/15
Simple 3 Amp Step-Down Fixed Voltage Regulators
PRELIMINARY
FEATURES · 5V, 12V and 15V Output, ±3% Max
Over Line and Load Conditions · Guaranteed 3A Output Current · Wide Input Voltage Range, from
Vour+2V to 40V (GOV for HV) · Requires Only 4 External Components · 52 kHz Fixed Frequency Internal
Oscillator · Low Power Standby Mode,
lo Typically < 200 µA · Efficiency Typically Over 80%
Uses Readily Available Standard Inductors · Thermal Shutdown and Current Limit Protection · 100% Electrical Thermal Limit Burn-in · Replacement for LM2576 Series
APPLICATIONS · Simple High-Efficiency Step-Down (buck)
Regulator · Efficient Pre-Regulator for Linear
Regulators · On-Card Switching Regulators · Positive to Negative Converter (Inverting,
Buck-Boost) · Isolated Flyback Converter using Minimum
Number of External Components · Negative Boost Converter
DESCRIPTION The UC1576/UC2576 family of devices provides all the active functions necessary to implement a simple step-down (buck) switching regulator. Utilizing a minimum number of external components, these regulators offer a simple, high efficiency replacement for popular three-terminal adjustable linear regulators, greatly reducing, and in many cases eliminating, the need for a heat sink.
The UC1576/UC2576 series features an output voltage of 5V, 12V or 15V (see Table 1) and is capable of driving a 3A load while maintaining excellent line and load regulation. Other features include internal frequency compensation, an on-chip fixed frequency oscillator with a ±10% tolerance and feedback voltage with ±3% tolerance within specified input voltages and output load conditions. External shutdown with a standby current of 200µA is provided. The output switch includes cycle-by-cycle current limiting and thermal shutdown for full protection under fault conditions.
A standard series of inductors and capacitors are available from several manufacturers optimized for use with the UC1576/UC2576 series. This feature greatly simplifies the design of switched mode power supplies.
CONNECTION DIAGRAM
5-PIN T0-220 (TOP VIEW) T-PACKAGE
~O~N~/~OBFAF CK
OUTPUT VIN
BLOCK DIAGRAM
Your
L 0 A D
Note: Pin numbers are for the T0-220 package 5193
5-80
ABSOLUTE MAXIMUM RATINGS (Note 1) If Military/Aerospace specified devices are required, please contact the UICC Sales Office/Distributors for availability and specifications. Maximum Supply Voltage
UC 1576/UC2576................................................. .45V UC2576HV ...........................................................63V ON/OFF Pin Input Voltage ......................-0.3 $ V $ +40V Output Voltage to Ground (Steady State) ..................· 1V Power Dissipation ................................Internally Limited Storage Temperature Range ................-65°C to +150°C Minimum ESD Rating
(C = 100 pF, R = 1.5 kn) .....................................2 kV
FB Pin (Pin 4) ...................................................... 1 kV Lead Temperature
(Soldering, 10 sec.) ..........................................260°C
TEST CIRCUIT AND LAYOUT GUIDELINES (Figure 1)
C1N .............................. 100 µF, 75V Aluminum Electrolytic Cour ......................... 1000 µF, 15V Aluminum Electrolytic D1 ........................................................Schottky, MBR360 L1 ................................. 100 µH (PE-92108) for UC2576-5
.220 µH (PE-53116) for UC2576-12, and UC2576-15 5-Pin T0-220 Socket... ..............2936 (Loranger Mfg. Co.) 4-Pin T0-3 Socket .........................8112-AG? (Augat Inc.)
UC1576-5/12/15 UC2576-5/12/15 UC2576HV-5/12/15
OPERATING RATINGS Maximum Junction Temperature ........................... 150°C Temperature Range
UC1576 .....................................-55°C $ TJ $ +150°C UC2576/UC2576HV ..................-40°C $ TJ :$ + 125°C
Supply Voltage UC1576/UC2576 ..................................................40V UC2576HV ...........................................................60V
Order Number For:
Output
Standard Voltage High Voltage Voltage
Rating (40V) Rati~60Vl
UC2576T·5.0
UC2576HVT·5.0 5.0
Temperature Range
UC2576T·12 UC2576T·15
UC2576HVT· 12 UC2576HVT· 15
12.0 15.0
·40°CSTJs;+125°C
UC1576K·5.0
5.0
UC1576K·12
12.0 ·55°CSTJs;+150°C
UC1576K-15
15.0
TABLE 1
I
UNREGULATED DC INPUT*
+VIN
UC2576HV
FEEDBACK 4
L1
2 3 ON/OFF 5
D1 MBR360
VouT
L 0 A D
FIGURE 1 Note: Pin numbers are for the T0-220 package
* 7-40V (60HV) for-5, 15-35V (60HV) for-12, 17-40V (60HV) for-15
As in any switching regulator, layout is very important. Rapidly switching currents associated with wiring inductance generate voltage transients which can cause problems. For minimal stray inductance and ground loops, the length of the leads indicated by heavy lines should be kept as short as possible. Single-point grounding (as indicated) or ground plane construction should be used for best results.
5-81
UC1576-5 UC2576-5 UC2576HV-5
ELECTRICAL CHARACTERISTICS: (Unless otherwise stated, these specifications apply for TA=-55°C to+150°C tor UC1576-5 and -40°C to+ 125°C tor the UC2576-5/UC2576HV-5, TA=TJ). Unless otherwise specified, VIN= 12V and ILOAD = 500mA.
UC1576-5
UC2576-5 UC2576HV-5
PARAMETER
TEST CONDITIONS
SYSTEM PARAMETERS1Note 2) Test Circuit Figure 1
Output Voltage
Output Voltage UC1576/UC2576
Output Voltage
VIN= 12V, ILOAD = 0.5A Circuit of Figure 1, TJ = 25°C
0.5A S ILOAD S 3A, 8V SVIN 5 40V
Circuit of Figure 1 TJ = 25°C
0.5A S ILOAD S 3A, 8V 5 VIN S 60V
UC2576HV
Circuit of Figure 1 TJ = 25°C
Efficiency
VIN= 12V, ILOAD = 3A, VouT = 5V
DEVICE PARAMETERS
Oscillator Frequency
(Note 9)
Saturation Voltage
Max Duty Cycle (ON) Current Limit
Output Leakage Current
TJ = 25°C
lour= 3A (Note 3) TJ = 25°
(Note 4) TJ = 25°
Peak Current (Note 3) TJ = 25°C
VIN= 40V, (TJ = 25°C), VIN = 60V tor HV (Note 5)
Output= OV Output= -1V Output= -1V
Quiescent Current
(Note 5) TJ = 25°C
Standby Quiescent Current
Thermal Resistance
ON/OFF Pin = 5V (OFF) TJ = 25°C
K Package, Junction to Ambient K Package, Junction to Case T Package, Junction to Ambient (Note 7) T Package, Junction to Ambient (Note 8) T Package, Junction to Case
ON/OFF CONTROL Test Circuit Figure 1
ON/OFF Pin Logic Input Level
VouT = OV VouT = 5V
ON/OFF Pin Input Current
TJ = 25°C ON/OFF Pin= 5V (OFF) (TJ = 25°C) 00/0FF Pin = OV (ON) (TJ = 25°C)
MIN. 4.950 4.800 4.850
43 47 93 3.5 4.2
24 2.2
TYP.
5.0 5.0
77
52 1.4 98 5.8 7.5 5 50 35 1.5
1.5 1.4 12 0
MAX.
5.050 5.200 5.150
62 58 2.0 1.8 7.5 6.9 2 30 12 10 500 200
0.8 1.0 30 10
MIN. 4.900 4.750 4.800 4.750 4.800
42 47 93 3.5 4.2
2.4 2.2
TYP.
5.0 5.0
5.0 77
52 1.4 98 5.8
7.5
5 50
65 45 2 1.5 1.4 12 0
MAX.
5.100 5.250 5.200 5.275
5.225
63 58 2.0 1.8
7.5 6.9 2 30 12 10 500 200
0.8 1.0 30 10
UNITS
v v
v
%
KHz
v
% A mA mA µA
oc;w
v
µA µA
5-82
UC1576-12 UC2576-12 UC2576HV-12
ELECTRICAL CHARACTERISTICS: (Unless otherwise stated, these specifications apply for TA=-55°C to + 150°C for UC1576-12 and -40°C to+ 125°C for the UC2576-12/UC2576HV-12, TA=TJ). Unless otherwise specified, V1N = 25V and ILOAD = 500mA.
PARAMETER f.----·
.J . . TEST CONDITIONS ----··----·---
SYSTEM PARAMETERS (Note 2) Test Circuit Figure 1
------.--
UC1576-12 MIN. TVP. MAX.
UC2576-12 UC2576HV-12
MIN. TVP. MAX.
UNITS
Output Voltage
VIN = 25V, ILOAD = 0.5A Circuit of Figure 1, TJ = 25°C
11.88 12.0 12.12 11.76 12.0 12.24
v
Output Voltage UC1576/UC2576
0.5A S ILOAD S 3A, 15V s VIN S 40V Circuit of Figure 1 TJ = 25°C
11.52
12.48 11.40
12.60
12.0
12.0
v
11.64
12.36 11.52
12.48
Output Voltage UC2576HV
0.5A s ILOAD S 3A. 15V s VIN s 60V Circuit of Figure 1 TJ = 25°C
11.40
12.65
12.0
v
11.52
12.52
Efficiency
VIN= 15V, ILOAD = 3A. VouT = 12V
88
---·-·
DEVICE PARAMETERS
88
%
Oscillator Frequency
(Note 9)
Saturation Voltage
TJ = 25°c -
IOUT = 3A (Note 3)
TJ = 25°
43
62
42
63
52
47
58
47
52
58
KHz
2.0 1.4
1.8
2.0 1.4
1.8
v
Max Duty Cycle (ON)
(Note 4) TJ = 25°
93
98
93
98
%
Current Limit
Peak Current (Note 3) TJ = 25°c
3.5
7.5
3.5
7.5
5.8
4.2
6.9
4.2
5.8
6.9
A
Output Leakage Current VIN = 40V, TJ = 25°C,
VIN = 60V for HV
Quiescent Current
(Note 6)
· - r-·------ ·- ---------
(Note 6)
TJ = 25·c
Output= OV Output= -1V
Output= -1V
--------
2 7.5
30
12 5
10
2
7.5
A
30
12
5
mA
10
Standby Quiescent Current
ON/OFF Pin = 5V (OFF) TJ = 25°C
500
50
200
500
50
200
µA
Thermal Resistance
K Package, Junction to Ambient
35
K Package, Junction to Case
1.5
T Package, Junction to Ambient (Note 7)
T Package, Junction to Ambient (Note 8)
T Package, Junction to Case
··--·
ON/OFF CONTROL Test Circuit Figure 1
65
·c!W
45
2
ON/OFF Pin Logic Input Level
ON/OFF Pin Input Current
VouT = OV VouT = 12V
·-t-cT:=J = -2-5·°·c-··-··-·-· ON/OFF Pin= 5V (OFF) (TJ = 25°C) ON/OFF Pin = OV (ON) (TJ = 25°C)
2.4 1.5
2.4
1.5
1.4
0.8
1.4
0.8
v
2.2
1.0
2.2
1.0
12
30
12
30
µA
0
10
0
10
µA
5-83
UC1576-15 UC2576-15 UC2576HV-15
ELECTRICAL CHARACTERISTICS: (Unless otherwise stated, these specifications apply for TA=-55°C to +150°C for UC1576-15 and -40°C to +125°C for the UC2576-15/UC2576HV-15, TA=TJ). Unless otherwise specified, VIN= 30Vand ILOAD = 500mA..
UC1576-15
PARAMETER
TEST CONDITIONS
SYSTEM PARAMETERS (Note~ Test Circuit Figure 1
Output Voltage
Output Voltage UC 1576/UC2576
Output Voltage UC2576HV
VIN = 30V, ILOAD = 0.5A Circuit of Figure 1, TJ = 25°C 0.5A :<;; ILOAD :<;; 3A, 18V :<;; VIN :<;; 40V Circuit of Figure 1 TJ = 25°C
0.5A S ILOAD S 3A, 18V S VIN S 60V Circuit of Figure 1 TJ = 25°C
Efficiency
VIN= 18V, !LOAD= 3A, VouT = 15V
DEVICE PARAMETERS
Oscillator Frequency
(Note 9)
TJ = 25°C
Saturation Voltage
[OUT= 3A (Note 3) TJ = 25°
Max Duty Cycle (ON) (Note 4) TJ = 25°
Current Limit
I--Output Leakage Current
Peak Current (Note 3)
TJ = 25°C
·-
V1N = 40V, TJ = 25°C, VIN = 60V for HV (Note 6)
Output= OV Output= -1 V Output= -1 V
Quiescent Current
(Note 6)
-··
Standby Quiescent
TJ = 25°C ON/OFF Pin = 5V (OFF)
Current
TJ = 25°C
Thermal Resistance
1K Package, Junction to Ambient K Package, Junction to Case T Package, Junction to Ambient (Note 7) T Package, Junction to Ambient (Note 8)
T Package, Junction to Case
----
ON/OFF CONTROL Test Circuit Figure 1
ON/OFF Pin Logic Input Level
VouT = ov
VouT= 12V
TJ = 25°C
ON/OFF Pin Input Current
ON/OFF Pin= 5V (OFF) (TJ = 25°C)
!-·==--···-----····
ON/OFF Pin = OV (ON) (TJ = 25°C)
MIN. 14.85 14.40 14.45
43 47 93 3.5 4.2
2.4 2.2
TYP. 15.0 15.0
88
52 1.4 98 5.8 7.5
5 50 35 1.5
1.5 1.4 12 0
MAX.
15.15 15.60 15.45
62 58 2.0 1.8 7.5 6.9 2 30 12 10 500 200
0.8 1.0 30 10
UC2576-15 UC2576HV-15
MIN. TYP. MAX.
14.70 14.25 14.40 14.25 14.40
15.0 15.0 15.0 88
15.30 15.75
15.60 15.83 15.68
42
63
52
47
58
2.0
1.4
1.8
93
98
3.5
5.8
7.5
4.2
6.9
2 7.5
30
5
12
10
50
500 200
65 45 2
2.4
1.5
1.4
0.8
2.2
1.0
12
30
0
10
UNITS
v v v
%
KHz
v
% A mA mA µA
°CNI
v
µA µA
5-84
UC1576-5/12/15 UC2576-5/12/15 UC2576HV-5/12/15
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. Note 2: External components such as the catch diode. Inductor, input and output capacitors can affect switching regulator system performance. When the UC15761UC2576 ls used as shown in the Figure 1 test c1rcuit, system performance will be as shown in system parameters section of Electrical Characteristics
Note 3: Output (pin 2) sourcing current. No diode, inductor or capacitor connected to output. Note 4: Feedback (pin 4) removed from output and connected to OV.
Note 5: Feedback (pin 4) removed from output and connected to 12V to force the output transistor OFF. Note 6: Feedback ipin 4) removed from output and connected to 25V to force the output transistor OFF.
Note 7: Junction to ambient thermal resistance (no external heat sink) for the 5 lead T0-220 package mounted vertically, with 112 inch leads in a socket, or on a PC board with minimum copper area.
Note 8: Junction to ambient thermal resistance (no external heat sink) for the 5 lead T0-220 package mounted vertically, with 114 inch leads soldered to a PC board containing approximately 4 square inches of copper area surrounding the leads. Note 9: The oscillator frequency reduces to approximately 18 kHz in the event of an output short or an overload which pulls the output lower than 3V for UC2576-5.0, or lower than 7.2V for UC2576-12 and lower than 9V for UC2576-15. This self protection features lowers the average power dissipation of the IC by lowering the minimum duty cycle from 5% down to approximately 2%.
Note 10: Refer to RETS UC1576K For current revision of military RETS!SMO.
Typical Performance Characteristics (Circuit of Figure 1)
UC1576-5.0/UC2576-5.0
Normalized
>
Output Voltage
.§.+100
~ +75
~ +50
~ +25
VrN ~ 12V LOAO· sotmA Normalized at
T .. 25°C
">:''j
0
0 -25
vl-1
r-..
;". -50
~ -75
1-
6 - 10~s .f.O -25 0 25 50 75100125150
JUNCTION TEMPERATURE (°C)
.s"' 181--T----t--i 161-----+--+-~~-; ~ 141--...---+-->--I---+-~
~ 121---t't'<-+--+-l--+--i
G 1or---i-o;i.;~-r---i--;
~ 81-;-:+-"'':±::7!'"""=1;;:;:;±=~
~ 61---1--+--+-l--+--i
4~~~~-~~~
0 10 20 30 40 50 60 INPUT VOLTAGE (V)
Line Regulation
~ ;~l---H.L"+-+-1--+-,
~ Ot---+--+-+-1--+-,
!~; -10 0 -20 ~0~10--2~0~30-4~0~50~60
INPUT VOLTAGE (V)
100 Efficiency
_ilJ .. 25°C
95
c- 90 85
G BO ..!'.
I
1~·3A
JJ
0f5 75
§ 70
65
!""--- J_ t:::I
[L"'}... ~ ILOAO a20()nA
J_ J_
60 0 10 20 30 40 50 60
INPUT VOLTAGE (V)
UC1576-12/UC2576-12
Normalized
> Output Voltage
.s +100
Vtr.i a25V
UJ +75 ILOA0·500mA
"':z;i;
+50
Normalized at TJ ·25°C
w +25
~
~""'
> 0
5
0
~ -25
-50 -75
v
I-
!'-,.
i=
::>
-100
0 -75-50-25 0 25 50 75100125150
JUNCTION TEMPERATURE ("C)
."s' 15~--+--+-+-+-+--+--i
I-
~
a: ::> '-'
~ s~--+--+-+-'--'--'--i
::>
~ OL-J-'-'--'----~ 0 5 10 15 20 25 30 35 40 INPUT VOLTAGE (V)
Line Regulation
~ +100 Normalized To 'vlN"'25V
t!! +75 LOAD" 50tmA TJ .. 2s·c
~
'-'
+50 +25
~
0
~
~ !;
-25 -50
L
-+-1
~ -75
0 ·100
0 5 10 15 2025 30 35 40
INPUT VOLTAGE (V)
Efficiency 100 r-r-,-,-,-,.-.-...,--,
95
"l. 90 H-T-t;*=lct:::f.Fl
- 851--~-!-
~ 80 u 751---~~s=o+~..i--+-~
~ 70
60~~~~~~~~
0 510152025303540 INPUT VOLTAGE (V)
5-85
UC1576-15/UC2576-15
Normalized
> +100 Output Voltage
E
YIN ·25V
~ +75 ILOAO·SOcmA,__.-+--+-+-'
~C> ~ ~
++S2O51N-or~~;-~z-;+:.-~ +1----++-+-++--+..-..-.l. -20511l-H-..-.+..._....,..,.,...1i...7.-1q.-.l+---1+t..-..-.-"+'1--+..-+-~l
§; -5011--hl'l-+-+-++-+-+--l
~ -75
§ ·10-915L--so'---'25-'-0_2.5..-so'--'1s-100.._..125.L-J1so
JUNCTION TEMPERATURE (C")
Supply Current
20 :;;(" 18 .§.. 16
MEASURED AT
GROUND PIN TJa25°C
~ 141--+--11---11--"4~-,-.~~--I
ii' 121---1--"~-'---"'17==-1
~ 101---l--/--b~'l'iOl!l.-..4---I-~
~ al---!-.Ll-~~$1;-l==::l
a..
ILOAO · 200mA
::> 6
"' 4'---'--'----''---'--'---' 0 10 20 30 40 50 60
INPUT VOLTAGE (VJ
Lina Regulation
! r---+-- ~ +100 N0<m·i'6d To VNo25V
- +75 ILOAD·500mA
+501-T~··~~r·~c-+--+--+---<
5 +251--+--+-_,,,...-b-l"-=-i
~ ol--llZ-.1£-+--+---<
i~'.5
-2s 1---#'~+--+-+--< -50 l--+--+--+-+--1
~ -75
0 · 1°~o.._~20~30_,__4_._0_5~0__,60
INPUT VOLTAGE (VJ
UC1576-5/12/15 UC2576-5/12/15 UC2576HV-5/12/15
Efficiency
1:!'.3A :r :r 100
- 90
II
llOA-;;t"1A
[7
!:.
-rr
~ 80 i-+-+-lcoAO · 200mA-
z
~ 70
ffi 60
50 10 15 20 25 30 35 40 INPUT VOLTAGE (VJ
Other Characteristics:
Currant Llmil
6.5
V1N .. 25V
~
~
6.0
I ...
0: 5.5
~
~ 5.0
~
lh I\
'=> 45
0
40 -75 -50-25 0 25 50 75 100125150
JUNCTION TEMPERATURE ("C)
Switch
Saturation Voltage
~11..6 4]]
~
~ ~
12 1.0
--ss1·c/1!.-''./: ~
~ 0.8 2s·C.J:7
~ 0.6 7150"C
1 gj 04
~ 021---1]-+-+--+--+---!
"' 0 '--'----'-'----'---'----' 0 0.5 1.0 1.5 2.0 2.5 3.0
SWITCH CURRENT (A)
Standby
_ ~
200
Quiescent Currant
VIN·40V
o'--''-'-'--'--'--'-.._'-75-50-25 0 25 50 75100125150
JUNCTION TEMPERATURE ("C)
UNITRODE INlEGRAlED CIRCUITS 7 CONTINENTAL BLVD· MERRIMACK, NH 03054 TEL. 603424-2410 · FAX 603-424-3460
5-86
n n L::::J INTl!llFIATED CIRCUITS
-UNITRODE
UC1576-ADJ UC2576-ADJ UC2576HV-ADJ
Simple 3 Amp Step-Down Voltage Regulator
PRELIMINARY
FEATURES · Adjustable Output · Reference Voltage ±2% Max Over Line
and Load Conditions · Guaranteed 3A Output Current · Wide Input Voltage Range, 4V to 40V
(60Vfor HV) · Wide Output Voltage Range, 1.23V to
37V (57V for HV) · Requires Only 6 External Components · 52 kHz Fixed Frequency Internal
Oscillator · Low Power Standby Mode,
la Typically < 200 µA · Efficiency Typically Over 80% · Uses Readily Available Standard
Inductors · Thermal Shutdown and Current Limit
Protection · 100% Electrical Thermal Limit Burn-in · Replacement for LM2576 Series
APPLICATIONS · Simple High-Efficiency Step-Down (Buck)
Regulator · Efficient Pre-Regulator for Linear
Regulators · On-Card Switching Regulators · Positive to Negative Converter (Inverting,
Buck-Boost) · Isolated Flyback Converter Using
Minimum Number of External Components · Negative Boost Converter
BLOCK DIAGRAM
DESCRIPTION The UC 1576-ADJ family of devices provides all the active functions necessary to implement a simple step-down (buck) switching regulator. Utilizing a minimum number of external components, these regulators offer a simple, high efficiency replacement for popular three-terminal adjustable linear regulators, greatly reducing, and in many cases eliminating, the need for a heat sink.
The UC1576-ADJ series features an output voltage which is adjustable from 1.23V to 37V (57V for the HV version) and is capable of driving a 3A load while maintaining excellent line and load regulation. Other features include internal frequency compensation, an on-chip fixed frequency oscillator with a ±10% tolera.nce, and output voltage with ±2% tolerance within specified input voltages and output load conditions. External shutdown with a standby current of 200µA is provided. The output switch includes cycle-by-cycle current limiting and thermal shutdown for full protection under fault conditions.
A standard series of inductors and capacitors are available from several manufacturers optimized for use with the UC1576-ADJ series. This feature greatly simplifies the design of switched mode power supplies.
CONNECTION DIAGRAM
5-PIN T0-220 (TOP VIEW) T-PACKAGE
5
8
4 3 2
1
ON/OFF FEEDBACK GND
OUTPUT
VIN
Note: Pin numbers are for the T0-220 package 5193
5-87
Your R2
R1
-= -=
UC1576-ADJ UC2576-ADJ UC2576HV-ADJ
ABSOLUTE MAXIMUM RATINGS {Note 1) If Military/Aerospace specified devices are required, please contact the UICC Sales Office/Distributors for availability and specifications. Maximum Supply Voltage
UC1576/UC2576 .................................................. 45V UC2576HV ........................................................... 63V ON/OFF Pin Input Voltage ......................-0.3 s Vs +40V Output Voltage to Ground (Steady State) ..................-1V Power Dissipation ................................ Internally Limited Storage Temperature Range ................-65°C to +150°C Minimum ESD Rating
(C = 100 pF, R =1.5 k.Q) .............·.......................2 kV
FB Pin (Pin 4) ......................................................1 kV Lead Temperature
c (Soldering, 10 sec.) ..........................................2so0
TEST CIRCUIT AND LAYOUT GUIDELINES (Figure 1)
C1N ............................. 100 µF, 75V Aluminum Electrolytic
CouT·······················1000 µF, 15V Aluminum Electrolytic D1 ........................................................Schottky, MBR360 L1 ...................................... 100 µH, Pulse Eng. PE-92108
OPERATING RATINGS Maximum Junction Temperature ........................... 150°C Temperature Range
UC1576......................................-55°C s TJ s +150°C UC2576/UC2576HV ..................-40°C s TJ S. +125°C Supply Voltage UC1576/UC2576 ..................................................40V UC2576HV ...........................................................60V
R1 ........................................ 1k,0.1%, R2.= 3.065k, 0.1% 5-Pin T0-220 Socket.................2936 (Loranger Mfg. Co.) 4-Pin T0-3 Socket .........................8112-AG7 (Augat Inc.)
7V-60V
UNREGULATED DC INPUT
FEEDBACK
4
UC2576HV-ADJ
L1
3 ON/OFF 5
CouT 1000 µF
VouT 5.00V
R2 L 0 A
R1 D
FIGURE 1
Note: Pin numbers are for the T0-220 package As in any switching regulator, layout is very important. Rapidly switching currents associated with wiring inductance generate voltage transients which can cause problems. For minimal stray inductance and ground loops, the length of the leads indicated by heavy lines should be kept as short as possible. Single-point grounding (as indicated) or ground plane construction should be used for best results.
5-88
UC1576-ADJ UC2576-ADJ UC2576HV-ADJ
ELECTRICAL CHARACTERISTICS: (Unless otherwise stated, these spec~ications apply for TA=-55°C to+150°C for UC1576
and -40°C to +125°C for the UC2576/UC2576HV, TA=TJ). Unless otherwise specified, VIN= 12V and ILOAD =500 mA.
UC1576-ADJ
UC2576·ADJ UC2576HV-ADJ
PARAMETER
TEST CONDITIONS
MIN. TYP. MAX. MIN. TYP. MAX. UNITS
SYSTEM PARAMETERS (Note 2) Test Circuit Figure 1
Feedback Voltage
Feedback Voltage UC1576/UC2576
VIN= 12V, ILOAD = 0.5A VouT - 5V, TJ - 25°C Circuit of Ffgpret
0.5A :S ILOAD :S 3A, aV :S VIN :S 40V VouT = 5V, Circuit of Figure 1 TJ = 25°C
1.217 1.230 1.243 1.217 1.230 1.243
v
1.193
1.267 1.1ao
1.2ao
1.230
1.230
v
1.205
1.255 1.193
1.267
Feedback Voltage UC2576HV
0.5A :S ILOAD :S 3A, aV :S VIN :S 60V VouT = 5V, Circuit of Figure 1
1.1ao
1.2a6
1.230
v
t---- TJ = 25°C 1.193 1.273 --------------------t-------------------------------+----+------+----+----+---t----~----<
Efficiency
VIN= 12V, ILOAD = 3A, VOUT = 5V
a2
a2
%
DEVICE PARAMETERS
Feedback Bias Current VouT = 5V TJ = 25°C
50
500
100
50
500
nA
100
Oscillator Frequency
(Note a)
TJ = 25°C
-· ·--------------+----
Saturation Voltage
louT = 3A (Note 3)
TJ = 25°
43
52
62
42 52
63
KHz
47
5a
47
5a
1.4
2.0
1.a
1.4
2.0
v
1.a
Max Duty Cycle (ON) J_N_ote 4) TJ = 25°
93
9a
93
9a
%
t-- Current Limit
--
Peak Current (Note 3) TJ = 25°C
3.5
7.5
3.5
7.5
4.2 5·a
6.9
4.2
5·a
6.9
A
-- ------- ---- ---- -------- - -- -------------------ll--'-=--+---+--'--'-''----f----=------li----+---'"-'----1------l
Output Leakage Current VIN= 40V, TJ = 25°C, Output= OV
2
2
VIN = 60V for HV
Output = -1 V
7.5
7.5
mA
(Note 5)
Output= -1V
30
30
Quiescent Current
(Note 5) TJ = 25°C
5
12
10
5
12
mA
10
Standby Quiescent
ON/OFF Pin = 5V (OFF)
Current
TJ = 25°C
-····-···-·----------+-----
Thermal Resistance
K Package, Junction to Ambient
K Package, Junction to Case
T Package, Junction to Ambient (Note 6)
50
500
200
35 1.5
50
500
µA
200
65
°C/W
_ ·:c..:.= ___
T Package, Junction to Ambient (Note 7)
45
___J_T_P__a__c_k_a_,._ge_~,__Ju__nc_t1_·o_n_to_C_a_s_e_ _ _ ___.___----"-------'-----_,_--_,__-2_,___ _..___----l
ON/OFF CONTROL Test Circuit Figure 1
ON/OFF Pin Logic Input Level
VouT = ov Vour = 5V
2.4 1.5
2.4 1.5
1.4 o.a
1.4 o.a
v
TJ = 25°C
2.2
1.0
2.2
1.0
ON/OFF Pin Input Current
ON/OFF Pin= 5V (OFF) (TJ = 25°C) Of\ltOFF Pin= OV (ON) (TJ = 25°C)
12
30
0
10
12
30
µA
0
10
µA
5-a9
UC1576 UC2576-ADJ UC2576HV-ADJ
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics.
Note 2: External components such as the catch diode. Inductor, input and output capacitors can affect switching regulator system performance. When the UC15761UC2576 ls used as shown in the Figure 1 test ctrcuit, system performance will be as shown in system parameters section of Electrical Characteristics.
Note 3: Output (pin 2) sourcing current. No diode, inductor or capacitor connected to output.
Note 4: Feedback (pin 4) removed from output and connected to OV.
Note 5: Feedback (pin 4) removed from output and connected to 12V to force the output transistor OFF.
Note 6: Junction to ambient thermal resistance (no external heat sink) for the 5 /ead T0-220 package mounted vertically, with 112 inch leads in a socket, or on a PC board with minimum copper area.
Note 7: Junction to ambient thermal resistance (no external heat sink) for the 5 lead T0-220 package mounted vertically, with 114 inch leads soldered to a PC board containing approximately 4 square inches of copper area surrounding the leads.
Note 8: The oscillator frequency reduces to approximately 18 kHz in the event of an output short or an overload which the feedback voltage lower than .7V. This self protection features lowers the average power dissipation of the IC by lowering the minimum duty cycle from 5% down to approximately 2%.
Note 9: Refer to RETS UC1576K-ADJ For current revision of military RETS!SMD.
Typical Performance Characteristics (Circuit of Figure 1)
20 Supply Current
MEASUREOAT
;;( 18
E.. 16
GROUNO PIN T J=25"C
v0ur=5V
Iz LaaU::
u:::> ~
0.. 0..
14
~ILOAo=3A
12 10 8
~ ~
l~O = 200 mA
:::> 6
"' 4
0 10 20 30 40 50 60
INPUT VOLTAGE (V)
~ >
C>
=Normalized Feedback Voltage
25..-..-r-..------'------.
20t-+-+- VIN= 12V
15
ILOAD =500mA
; 10
NormalizedtoTJ=25"C
~ 51--+-t-+->--~·,__.......,........
~~ -o5l~-~,-LT.--Jl--4-~T--11--o-:+f:-:t:-t-=++-:+:~I
fa ·10 t-t-1--1--1--1--1--......,t-t
~ · 15 1--1-t~t-t>-il-il-il-i-I
fa -201-+-t-+-1--1--1--1--t-t
N::; -25 ,__._.._.._.__._,__........,__.
~ -75·50-25 0 25 50 75100125150
g JUNCTION TEMPERATURE (°C)
Supply Current vs Duty Cycle
20.0 r-~-'---r------..--.
V1N =7V
~;:::- 175..50 t-t-==~===~==~:~~:~~
~~ 1102..05,1__-_--_+_--_+~_~_~-_t_.'_._'._"_-_I,
u ~ 7.5 ~ 5.0 1---+---i---..----~
~ 2.5 t--+---1---+---+-~
o,____..___.___..___..___.
0 20 40 60 80 100
DUTY CYCLE(%)
1 Standby 200 Quiescent Current
1z LaaU:: 150
:u::>
1-
i'ij
100
u
....+-'
VIN= 40V i -
:1
l
VON/OFF= 5v
j_
"'LU
5
0
>-
"0 ' ~
....- VIN =12V i-
50
I
0
I
-75 -50 -25 0 25 50 75100 125150
"'
JUNCTION TEMPERATURE (°C)
Switch
Saturation Voltage
1.6
~ 1.4
LU Cl
t_!_i,
0z>
0
a~ :
:::>
1.2
v 1.0 ...v 0.8
-55°C
-
c;;;
~.....L. ~
25°C
lL 0.6 71 5o·c
0.4
!;:;: 0.2
"' 0
100 Efficiency
95
VouT = 12V
~ 90
z>u-
LU
85 80
200 mA
1A
ts 200 mA-1~....3A
v "" 0
it
75 1A
LU 70
3A_/_
Vour = 3V
65
TJ=25"C
60
0 0.5 1.0 1.5 2.0 2.5 3.0
0 10 20 30 40 50 60
SWITCH CURRENT (A)
INPUT VOLTAGE (V)
5-90
UC1576 Serles Buck Regulator Design Procedure
PROCEDURE Given:
Vour = Regulated Output Voltage V1N (max) = Minimum Input Voltage ILOAD (max) = Maximum Load Current F = Switching Frequency (52kHz)
Example: VOUT = 10V, VIN (max)= 25V, ILOAD (max)= 3A, F = 52kHz
UC1576-ADJ UC2576-ADJ UC2576HV-ADJ
1. Programming Output Voltage (Selecting R1 and R2)
The following formula can be used to select the resistor values for a given voltage:
~~ VouT = VREF (1 + )
And for a given R1 (between 1K and 10K),
1) R2 = R1 (VOUT VREF Example:
Vour = 1.23 (1 + ~~) select R1=1K:
R2 = R1 ( ~~~; - 1 ) = 1k ( 1~~~V - 1) = 7.13K, use closest 1% value 7.15K.
2. Inductor Selection (L1)
A. Calculate E·T(V·µS), from the following formula:
E·T = (VIN - VOUT). ~ VOUT ·
1000 F(in kHz)
(V·µS)
B. Use the E·T value from above and match it with the E·T number on the vertical axis of the Inductor value selection guide shown in Figure 2.
C. On the horizontal axis, select the minimum load current. Find the region intersected by the E.T value and the maximum load current value and note the inductor code for the region.
D. Match the inductor code to the inductor value, using Fig. 3.
Example:
Calculating E·T (V·µS):
E·T = (25 - 10). _!Q .lOOO = 115 V·µS 25 52
For ILOAD = 3A and E·T = 115V·µS, Inductor code is H150 and the inductor value is 150µH.
3. Output Capacitor Selection (Cour)
A. The dominant pole-pair of the switching regulator loop is defined by the value of the output capacitor and the inductor. In order to achieve stable operation, the capacitor must satisfy the following requirement.
V1N (max) Cour > 13,300 · VOUT· L(µH) (µF)
Example:
25 Cour > 13,300 · - - - = 221µF
10. 150
For acceptable ripple voltage, select Cour = 680µF electrolytic capacitor. 5-91
UC1576-ADJ UC2576-ADJ UC2576HV-ADJ The ESR (Equivalent Series Resistance) of the output capacitor is the primary cause of the output ripple voltage and the value and the type of the output capacitor determine the amount of ESR and thus the output ripple voltage. In general lower capacitor values have higher ESR ratings. Capacitor values larger than 680µF will produce an output ripple voltage of 35mV to 50mV, while smaller capacitors (220µF to 680µF) will typicaly cause a ripple of 50mV to 150mV. The following approximate relationship could be used in determining the output ripple: VRIPPLE p-p > 0.3 x ILOAD(max) x ESR It is possible to reduce the output ripple to 10mV-20mV by using several standard electrolytic capacitors in parallel or by using higher grade capacitors with low ESR and low inductance. However, ESR values lower than 0.05 Ohms can cause instability. The capacitor's ripple current rating at 52kHz should be at least 50% higher than the inductor current ripple: IRIPPLE(max) > 1.5 x 0.3 x ILOAD(max) B. The voltage rating of the output capacitor should be at least 1.2 times greater that the output voltage. For a 1OV output, a rating of 15V is appropriate, and a 20V rating is recommended.
4. Catch Diode Selection (01) The current rating of the catch diode must be at least 1.2 times greater than the maximum load current, unless the diode is expected to withstand a continuous output short, in which case the current rating of the diode should be equal to the maximum current rating of UC2576.
A. The reverse voltage rating of the diode should be at least 1.25 times the maximum input voltage. B. Schottky diodes with fast switching speed and a low forward voltage drop are the most efficient. Some types of
diodes with an abrupt turn-off characteristic may cause instability and EMI problems. Therefore in general, a fastrecovery diode with soft recovery characteristics is recommended. See Figure 4 for Schottky and "soft" fast-recovery diode selection guide.
5. Input Capacitor (CIN) To assure stability, the regulator input pin must be bypassed with a by-pass capacitor of at least 47 µF, low ESR (electrolytic type). If an operation at low temperatures (for example -25°C) is intended, then addition of a ceramic or solid tantalum capacitor near the input pin may be required to maintain the capacitance value and low ESR at low temperature.
1oo~~~~~~~~~~~*m~ 90~~~~~~N#*I"'~~~~~~~
1.5 MAXIMUM LOAD CURRENT (A)
2.0 2.5 3.0
Figure 2. Inductor Value Selection Guide {for Continuous Mode Ooeration)
5-92
UC1576-ADJ UC2576-ADJ UC2576HV-ADJ
Inductor Code
Inductor Value
AIE
Pulse Eng.
Renco
1--~~~----~-1-~~--·-~~-+-~(N_o_t_e_1~>___,c--__,(~N_ot_e_2~>~-+--<~N_o_te_3~)'--l
L47
47µH
415-0932
PE-53112
RL2442
L68
68 µH
415-0931
PE-92114
RL2443
,_____ _L_1o_o _
l150
100 µH 150µH
415-0926 415-0953
PE-52627 PE-53113
RL 1952 RL1954
L220
220 µH
415-0922
PE-52626
RL 1953
L330
330 µH
415-0926
PE-52627
RL 1952
L470
470 µH
l--~~~----f-----
L680
680 µH
415-0927 415-0928
PE-53114 PE-52629
RL1951 RL 1950
f---~_fi!-~~ ----t----150 µ__H_ _ _--r--_4_15_-_09_3_6_--+--__P_E_-5_3_1_1_5 __,r--_R_L2_44_5_-j
H220
220 µH
430-0636
PE-53116
RL2446
f----
1-j330_ H470 H680 H1000
----+---- __ 3~~_fl_f:1___ ______,__4_30_-_06_3_5_-+-__P__E_-5_3_1_1_ 7 _,____R_L2_4_4_7 _,
470µH
--+4-3-0--0-6-34-------P1E-5-3-1-18----+-R-L-19-6-1 --'
680µH
415-0935
PE-53119
RL1960
- -- -----------1-------+--------+--------j
1000µH
415-0934
PE-53120
RL1959
H1500
1500µH
415-0933
PE-53121
RL1958
H2200
2200 µH
415-0945
PE-53122
RL2448
Note 1: AIE Magnetics, Div. Vernitron Corp. Passive Components Group, (813) 347-2181 2801 72nd Street North, St. Petersburg, FL 33710
Note 2: Pulse Engineering, (619) 268-2400 P.O. Box 12235, San Diego, CA 92112
Note 3: Renea Electronics Inc., 60 Jeffnyn Blvd. East, Deer Park, NY 11729 (516) 586-5566
FIGURE 3. Inductor Selection by Manufacturer's Part Number
VIN
(max) 20V
30V
40V
50V
Schottky
3A
1N5820 MBR320P
SR302
4A-6A 1N5823
1N5821 MBR330 31 D003 SR303
50W003 310003 1N5824
1N5822 MBR340 310004 SR304
MBR340 310004 50W004 1N5825
MBR350 310005 SR305
50W005
Fast Recovery
3A
4A-6A
The following diodes are all rated to 100V
The following diodes are all rated to 100V
31DF1 HER302
50WF10 MUR410 HER602
MBR360 50W006
60V
D006 5080060
SR306
Figure 4. Diode Selection Chart
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD ·MERRIMACK, NH 03054 TEL 603-424·2410 ·FAX 603-424-3460
5-93
ii[. n L::_::'.j
IN.. TEGRATEC CIRCUITS
-UNITROOE
Simple Step-Up Fixed Voltage Regulators
UC1577-12/15 UC2577-12/15
ADVANCED INFORMATION
FEATURES
Requires Few External Components · NPN Output Switches 3.0A, Can Stand
Off 65V · Extended Input Voltage Range: 2.9V
to 40V Current-Mode Operation for Improved Transient Response, Line Regulation and Current Limiting Sleep Mode Feature with Low Quiescent Current Soft Start Function Provides Controlled Start-up 52kHz Internal Oscillator Output Switch Protected by Current Limit, Under-Voltage Lockout and Thermal Shutdown Improved Replacement for LM2577 Series
DESCRIPTION The UC 1577 family of devices provides all the active functions necessary to implement step-up (boost), flyback, and forward converter switching regulators. Requiring only a few components, these simple regulators efficiently provide fixed output voltages of 12V or 15V as stepup regulators.
The UC1577 series features a wide input voltage range of 2.9V to 40V. An on chip 3.0A NPN switch is included with undervoltage lockout and thermal protection circuitry and current limiting. A sleep mode is provided with low quiescent current, as well as soft-start mode operation to reduce current during start-up. Other features include a 52kHz fixed frequency on-chip oscillator with no external components and current mode control for better line and load regulation.
A standard series of inductors and capacitors are available from several manufacturers optimized for use with these regulators. (See specifications for UC1577-ADJ/UC2577-ADJ for part lists.)
TYPICAL APPLICATIONS · Simple Boost and Flyback Converters · Transformer Coupled Forward Regulators · Multiple-Output Designs
CONNECTION DIAGRAM
5-PIN T0-220 (TOP VIEW) T-Package
BLOCK DIAGRAM
v"~----------+'
r--'l------1"--0 Vou1
c.
5193
5-94
UC1577-12/15 UC2577-12/15
ABSOLUTE MAXIMUM RATINGS (Note 1) If Military/Aerospace specified devices are required, please contact the UICC Sales Office/Distributors for availability and specifications.
Supply Voltage ..........................................................45V Output Switch Voltage ...............................................65V Output Switch Current (Note 2) ................................6.0A Power Dissipation ................................. Internally Limited Storage Temperature Range ................-65°C to+ 150°C
o Lead Temperature (Soldering, 1 sec.) .................260°C
Maximum Junction Temperature ........................... 150°C Minimum ESD Rating
(C = 100 pF, R = 1.5 k0.) .....................................2 kV
RECOMMENDED OPERATING RANGE Supply Voltage ........................................2.9 :;;; VIN :;;; 40V
Output Switch Voltage .....................ov:;;; VSWITCH :;;; 60V
Output Switch Current .............................lsw1TcH:;;; 3.0A
Junction Temperature Range
UC1577 ...........................................-55°C:;;; TJ:;;; +150°C
c UC2577 ..........................................-40°C:;;:TJ:;;:+12s0
ELECTRICAL CHARACTERISTICS: (Unless otherwise stated, these specifications apply for TA = -55°C to +150°C for UC1577 and -40°C to+ 125°C for the UC2577,TA =TJ.) Unless otherwise specified, VIN= 5V, and ISWITCH = 0.
UC1577-12
UC2577-12
PARAMETER
_i_
TEST CONDITIONS
---------------------~-----
SYSTEM PARAMETERS Circuit Figure 1 (Note 3)
MIN.
Output Voltage
VIN= 5V to 10V
ILOAD = 100 mA to 800 mA
TJ = 25°C
Line Regulation
VIN = 2.9V to 12V, ILOAD = 300 mA
TJ = 25°C
Load Regulation
VIN= 5V, ILOAD = 100 mA to 800 mA
__ JJ = 25°C ___________________________
---~--·-·---·-
Efficiency
·----··-·-···-
DEVICE PARAMETERS
VIN = 5V, ILOAD = 800 mA - - -------------·-- --- -- --------·-
-
------
Input Supply Current
VFEEDBACK = 14V (Switch Off)
11.40 11.60
TJ = 25°C
ISWITCH = 2.0A, VCOMP = 2.0V (Max Duty Cycle)
TJ = 25°C VCOMP = o.1s1e~ V1N=5V,lNote 51
Input Supply
ISWITCH = 100 mA
2.60
Undervoltage Lockout TJ = 25°C
2.65
Oscillator Frequency
Measured at Switch Pin
42
ISWITCH = 100 mA
TJ = 25°C
48
Output Reference
Measured at Feedback Pin
11.64
Voltage
VIN= 2.9V to 40V, VcoMP = 1.0V
TJ = 25°C
11.76
Reference Voltage
VIN= 2.9V to 40V
Line Regulation
Feedback Pin
I
Input Resistance
I -----··-
Error Amp
ICOMP = -30 µA to + 30 µA
145
Transconductance
VCDMP = 1.0V
t---Error Amp
TJ = 25°C
225
---
-~--------·~-
VCOMP = 1.1 V to 1.9V, RcoMP = 1.0 Mn (Note 4) 25
Voltage Gain
TJ = 25°C
50
-~
Error Amplifier
Upper Limit VFEEDBACK = 1o.ov
2.0
Output Swing
TJ = 25°C TowerTimltVFEEDBACK,;;f5.ov
------ 2.2
TJ = 25°C
TYP.
12.0 20 20 80
7.5 25 250 2.70 52
12 7 9.7 370
80 2.4 0.3
MAX.
12.60 12.40 100
50 100 50
14 10 85 50 400 2.80 2.75 62 56 12.36
12.26
615
515
0.55 0.40
MIN. 11.40 11.60
2.60 2.65 42 48 11.64 11.76
145 225 25 50 2.0 2.2
TYP.
12.0 20
80
7.5 25 250 2.70 52
12
7
9.7 370
80 2.4 0.3
MAX.
12.60 12.40 100
50 100 50
14 10 85 50 400 2.80 2.75 62 56 12.36
12.26
615
515
0.55 0.40
UNITS
v mV mV %
mA mA _ll._A v kHz
v
mV
--Kn
µmho
VN v v
5-95
UC15n-12/15 UC25n-12/15
ELECTRICAL CHARACTERISTICS: (Unless otherwise stated, these specttications apply for TA = -55°C to +150°C for UC1577 and-40°C to +125°C for the UC2577,TA =TJ.) Unless otherwise specttied, VIN= 5V, and lsw1rcH = 0.
PARAMETER
TEST CONDITIONS
DEVICE PARAMETERS Continued
Error Amp
VFEEDBACK = 10.0V to 15.0V
Output Current
VcoMP = 1O.OV
TJ = 25°C
Solt Start Current
VFEEDBACK = 10.0V
VCOMP = 0.5V
r-
TJ = 25°c
-~
Maximum Duty Cycle
VCOMP = 1.5V
- ---- ----
ISWITCH = 1OOmA
TJ = 25°c
Switch Transconductance
Switch Leakage Current
VSWITCH = 65V VFEEDBACK = 1.5V (Switch Off) TJ = 25°c
Switch Saturation Voltage
ISWITCH = 2.0A VcOMP = 2.0V (Max Duty Cycle) TJ = 25°c
NPN Switch
r--C-urrent Limit
Thermal Resistance
VCOMP = 2.0V TJ = 25°c
K Package, Junction to Ambient K Package, Junction to Case
T Package, Junction to Ambient T Package, Junction to Case
COMP Pin Sleep Threshold
Vour = O TJ = 25°c
COMP Pin Current
VCOMP = 0 TJ =25°C
uc1sn-12 MIN. TYP. MAX.
UC2577·12 MIN. TYP. MAX. UNITS
±90
±130 1.5
2.5 90 93
±200 5.0 95
12.5
±400
±300 9.5
7.5
600 10
300
0.9
0.5 0.7
3.0
6.0
3.7
4.3
5.3
35 1.5
110
190
130 150 170
35 40
50
65 60
±90
±130 1.5
2.5 90 93
±200 5.0
95 12.5
10
0.5
3.0 3.7
4.3
65 2
110 130
150
35 40
50
±400 ±300 9.5 7.5
600 300 0.9 0.7 6.0 5.3
190 170 65 60
µA µA % AN µA
v
A 0 c1W
mV µA
VIN
220µF
0.1 µF
+Cour
680µF
10k
Vour
L = 415-0930 (AIE) D = Any Manufacturer
Cour = Spraque Type 673 D Electrolytic 680µF, 20V
Note: Pin numbers shown are for T0-220 (T) Package.
Figure 1. Circuit used for System Parameters Specifications
5-96
ABSOLUTE MAXIMUM RATINGS (Note 1)
If Military/Aerospace specified devices are required, please contact the UICC Sales Office/Distributors for availability and specifications.
Supply Voltage ..........................................................45V Output Switch Voltage ...............................................65V Output Switch Current (Note 2) ................................6.0A Power Dissipation ................................. lnternally Limited Storage Temperature Range ................-65°C to+150°C Lead Temperature (Soldering, 10 sec.) .................260°C Maximum Junction Temperature ........................... 150°C Minimum FSD Rating
(C = 100 pf, R = 1.5 k.0) .....................................2 kV
uc1sn-1211s UC25n-12/15
RECOMMENDED OPERATING RANGE
Supply Voltage ........................................2.9 s VIN s 40V
ov Output Switch Voltage ..................... s VSWITCH s 60V
Output Switch Current ............................ .lsw1rcH s 3.0A
Junction Temperature Range
c UC1577...........................................-ss0 ~ TJ s +150°C c UC2577 ..........................................-40°C s TJ s +12s0
ELECTRICAL CHARACTERISTICS: (Unless otherwise stated, these specifications apply for TA = -55°C to +150°C for UC1577
= and -40°C to +125°C tor the UC2577,TA =TJ). Unless otherwise specified, V1N = 5V, and lsw1rcH o.
uc15n-15
uc25n-1s
PARAMETER
TEST CONDITIONS
MIN. TYP. MAX.
SYSTEM PARAMETERS Circui1 Figure 2 (Note 3)
Output Voltage
Line Regulation Load Regulation Efficiency
VIN= 5V to 12V ILOAD = 100 mA to 600 mA TJ = 25·c
VIN= 2.9V to 12V, ILOAD = 300 mA TJ = 25·c
VIN= 5V, ILOAD = 100 mA to 600 mA TJ = 25·c VIN = 5V, ILOAD = 600 mA
14.25 15.0
14.50 20
20 80
15.75
15.50 100 50 100 50
DEVICE PARAMETERS
Input Supply Current
Input Supply Undervoltage Lockout Oscillator Frequency
Output Reference Voltage
Reference Voltage Line Regulation Feedback Pin Input Resistance
VFEEDBACK = 1.5V (Switch Off)
TJ = 25·c
ISWITCH = 2.0A, VCOMP = 2.0V(Max Du1y Cyde) TJ = 25·c
VCOMP = 0 J_Slel!l!1_ VIN = 5V J_Note 5.l
ISWITCH = 100 mA
2.60
TJ = 25·c
2.65
Measured at Switch Pin ISWITCH = 100 mA TJ = 25·c Measured at Feedback Pin
42
48 14.55
VIN= 2.9V to 40V
VCOMP = 1.0V, TJ = 25°C VIN= 2.9V to 40V
14.70
7.5 25 250 2.70 52
15
10
14 10 85 50 400 2.80 2.75 62
56 15.44
15.30
12.2
Error Amp Transconductance
ICOMP = -30 µA to+ 30 µA VCOMP = 1.0V TJ = 25·c
110
500
300
170
420
Error Amp
Voltage Gain Error Amplifier Output Swing
Vc:<:N.P= 1.1Vto 1.9V,RCOMP= 1.0Mn(Nole4} 20
TJ = 25·c
40
Upper Limit VFEEDBACK = 12.0V
2.0
TJ = 25·c
2.2
Lower Limit VFEEDBACK = 18.0V
TJ = 25·c
65 2.4
0.55 0.3 0.40
MIN. 14.25 14.50
2.60 2.65 42 48 14.55 14.70
110 170
20
40 2.0 2.2
TYP. MAX.
15.75 15.0
15.50
20
100 50
100 50 80
7.5 25 250 2.70
52
15
14 10 85 50 400 2.80 2.75 62
56 15.44
15.30
10
12.2
500 300
420
65
2.4
0.55
0.3
0.40
UNITS
v
mV mV %
mA mA
iA
v
kHz
v
mV Kn
µmho
VN
v v
5-97
UC1577-12/15 UC2577-12/15
ELECTRICAL CHARACTERISTICS: (Unless otherwise stated, these specifications apply for TA= -55°C to +150°C for UC1577
and -40°C to+ 125°C for the UC2577,TA =TJ.) Unless otherwise specified, VIN = 5V, and !SWITCH = 0.
uc1sn-1s
uc2sn-1s
PARAMETER
TEST CONDITIONS
MIN. TYP. MAX. MIN. TYP. MAX. UNITS
DEVICE PARAMETERS Continued
Error Amp Output Current
Soft Start Current
VFEEDBACK = 12.0V to 18.0V VCOMP = 1.0V TJ = 25°C VFEEDBACK = 12.0V VcoMP = 0.5V TJ = 25°C
Maximum Duty Cycle
VcoMP = 1.5V !SWITCH = 1OOmA TJ = 25°C
Switch Transconductance
Switch Leakage Current
VSWITCH = 65V VFEEDBACK = 1.5V (Switch Off) TJ = 25°C
Switch Saturation Voltage
NPN Switch Current Limit
!SWITCH = 2.0A
VcoMP = 2.0V (Max Duty Cycle)
TJ = 25°C ___ __,.
---- ----- -------- ··-----·----·---------
··---~··----~-
VCOMP = 2.0V
TJ = 25°C
Thermal Resistance
K Package, Junction to Ambient K Package, Junction to Case
COMP Pin Sleep Threshold
T Package, Junction to Ambient T Package, Junction to Case
VouT = o
TJ = 25°C
COMP Pin Current
COMP=O TJ =25°C
±90
±130 1.5
2.5 90 93
±200 5.0 95
12.5
±400
±300 9.5
7.5
600
10 300
0.9 0.5
0.7
3.0
4.3
3.7
6.0 5.3
35 1.5
120
180
130 150
170
35
50
65
40
60
±90
±130 1.5
2.5 90 93
±200 5.0
95 12.5
±400
±300 9.5
7.5
600
10 300
0.9 0.5
0.7
3.0
4.3
6.0
3.7
5.3
65 2
120
150
180
130
170
35
50
65
40
60
µA µA % AN µA
v
A oc/W
mV µA
10k
VouT
150 +680 µF
220µF
Cou1
0.1 µF
L = 415-0930 (AIE) D = Any Manufacturer
T
GOUT = Spraque Type 6730 ~---------+--------+---+---+--~
Electroly1ic 680 µF, 20V
Figure 2. Circuit used for System Parameter Specifications
Note: Pin numbers shown are for T0-220 (T) package.
Note 1: Absolute Maximum Ratings indicate /imirs beyond which damage to the device may occur. Operating ratings indicate conditions the device is intended to be functional, but device parameter specifications may not be guaranteed under these conditions. For guaranteed specifications and test conditions, see the Electrical Characteristics.
Note 2: Output current cannot be internally limited when the UGI 577/UC2577 is used as a step-up regulator. To prevent damage to the
switch, its current must be externally limited to 6.0A. However, output current is internally limited when the UC1577/UC2577 is used as a flyback or forward convener regulator in accordance to the Application Hints.
Note 3: External components such as the diode, inductor, input and output capacitors can affect switching regulator performance. When the UC1577!UC2577 is used as shown in the Test Circuit, system performance will be as specified by the system parameters.
Note 4: A 1.0 Mn resistor is connected to the compensation pin (which is the error amplifier's output) to ensure accuracy in measuring AvoL. In actual applications, this pin's load resistance should be~ 10 Ma, resulting in AVOL that is typically twice the guaranteed minimum limit.
Note 5: Comp pin is externally forced to OV. Supply current during sleep mode is tested at VIN = 5V and could increase with increasing VIN, however, it should typically be less than 500µA within the specified range of VIN.
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD.· MERRIMACK, NH 03054 TEL 603-424·2410 .. FAX 603-424-3460
5-98
n n INTEORATECJ
L~_J CIRCUITS
.... UNITRCCE
Simple Step-Up Voltage Regulators
UC1577-ADJ UC2577-ADJ
ADVANCED INFORMATION
FEATURES Requires Few External Components NPN Output Switches 3.0A, Can Stand Off 65V Extended Input Voltage Range: 2.9V to 40V Current-Mode Operation for Improved Transient Response, Line Regulation and Current Limiting Sleep Mode Feature with Low Quiescent Current Soft Start Function Provides Controlled Start-up 52kHz Internal Oscillator Output Switch Protected by Current Limit, Under-Voltage Lockout and Thermal Shutdown Improved Replacement for LM2577-ADJ Series
DESCRIPTION The UC 1577-ADJ family of devices provides all the active functions necessary to implement step-up (boost), flyback, and forward converter switching regulators. Requiring only a few components, these simple regulators efficiently provide up to 60V as a step-up regulator, and even higher as a flyback or forward converter regulator.
The UC1577-ADJ series feature a wide input voltage range of 2.9V to 40V and an adjustable output voltage. An on chip 3.0A NPN switch is included with undervoltage lockout and thermal protection circuitry and current limiting. A sleep mode is provided with low quiescent current, as well as soft-start mode operation to reduce current during start-up. Other features include a 52kHz fixed frequency on-chip oscillator with no external components and current mode control for better line and load regulation.
A standard series of inductors and capacitors are available from several manufacturers optimized for use with these regulators and are listed in this data sheet.
TYPICAL APPLICATIONS · Simple Boost and Flyback Converters · Transformer Coupled Forward Regulators · Multiple-Output Designs
CONNECTION DIAGRAM
5-PIN T0-220 (TOP VIEW) T-Package
BLOCK DIAGRAM
5/93
5-99
ABSOLUTE MAXIMUM RATINGS (Note 1) If Military/Aerospace specified devices are required, please contact the UICC Sales Office/Distributors for availability and specifications.
Supply Voltage ..........................................................45V Output Switch Voltage ...............................................65V Output Switch Current (Note 2) ................................6.0A Power Dissipation ................................. Internally Limited Storage Temperature Range ................-65°C to +150°C Lead Temperature (Soldering, 10 sec.) .................260°C Maximum Junction Temperature ........................... 150°C Minimum ESD Rating
(C = 100 pF, R = 1.5 kQ) .....................................2 kV
UC1577-ADJ UC2577-ADJ
RECOMMENDED OPERATING RANGE Supply Voltage ......................................2.9V :<;; V1N :<;; 40V Output Switch Voltage .....................OV :<;; Vsw1rcH :<;; 60V
Output Switch Current .............................lsw1rcH :<;; 3.0A
Junction Temperature Range
c UC1577 ...........................................-55°C :<;; TJ :<;; + 1so0
UC2577 ..........................................-40°C :<;; TJ :<;; +125°C
ELECTRICAL CHARACTERISTICS: (Unless otherwise stated, these specifications apply for TA = -55°C to+ 150°C for UC1577 and -40°C to+ 125°C for the UC2577, TA=TJ.) Unless otherwise specified, VIN= 5V, VFEEDBACK = VREF, and !SWITCH = 0.
UC1577-ADJ
UC2577-ADJ
PARAMETER
TEST CONDITIONS
MIN. TYP.
SYSTEM PARAMETERS Circuit Figure 1 {Note 3)
Output Voltage
Line Regulation Load Regulation Efficiency
VIN= 5V to 10V ILOAD = 100 mA to 800 mA TJ = 25°C
VIN= 2.9V to 1OV, ILOAD = 300 mA TJ = 25°C VIN= 5V, ILOAD = 100 mA to 800 mA TJ = 25°C VIN= 5V, ILOAD = 800 mA
11.40 12.0
11.60 20
20 80
1--D.E. VICE PARAMETERS Input Supply Current VFEEDBACK = 1.5V (Switch Off)
Input Supply Undervoltage Lockout Oscillator Frequency
Reference Voltage
TJ = 25°C
!SWITCH = 2.0A
VcoMP = 2.0V {Max Duty Cycle)
! -T-J- ·=· -2·.-5-°- - - - · · · · · VcoMP = 0lSle~ Vin = 5V,1Note ~ !SWITCH = 100 mA
TJ = 25° -------
...
Measured at Switch Pin
!SWITCH = 100 mA
TJ = 25°C
Measured at Feedback Pin
VIN= 2.9V to 40V, VCOMP = 1.0V
Reference Voltage Line Regulation
TJ = 25°C VIN = 2.9V to 40V
7.5
25
2.60 2.65 42
48 1.206
1.214
250 2.70 52
1.230
0.5
Error Amp Input Bias Current
..
Error Amp Transconductance
Error Amp Voltage Gain ·Error Amplifier Output Swing
VCOMP = 1.0V
TJ = 25°C
---- ----···------ - ---------
- ------
ICOMP = -30 µA to+ 30 µA, VCOMP = 1.0V
1600
TJ = 25°C
2400
v VCOMP = 1.1 to 1.9V, RCOMP = 1.0 Mn (Note4 250
TJ = 25°C
500
Upper Limit VFEEDBACK = 1.0V
2.0
TJ = 25°C
2.2
Lower Limit VFEEDBACK = 1.5V
TJ = 25°C
100 3700 800
2.4 0.3
MAX.
12.60 12.40 100
50 100 50
14 10 85
50 400 2.80 2.75 62
56 1.254
1.246
800 300 5800 4800
0.55 0.40
MIN. TYP. MAX.
11.40 11.60
12.0
20 20 80
12.60
12.40 100 50 100 50
2.60 2.65 42
48 1.206
1.214
7.5 25 250 2.70 52
1.230 0.5
14 10 85
50 400 2.80 2.75 62
56 1.254
1.246
100
1600 2400
250 500 2.0 2.2
3700 800 2.4
0.3
800 300 5800 4800
0.55 0.40
UNITS
v
mV mV %
mA mA µA
v
kHz
v
mV nA µmho VIV
v v
5-100
UC1577-ADJ UC2577-ADJ
ELECTRICAL CHARACTERISTICS: (Unless otherwise stated, these specifications apply for TA = -55°C to +150°C for UC1577 and -40°C to+ 125°C for the UC2577, TA=TJ.) Unless otherwise specified, V1N = 5V, and lsw1TCH = 0.
-l ·- PARAMETER
TEST CONDITIONS
DEVICE PARAMETERS Continued
--
--·
~-------·
---- ----
Error Amp
VFEEDBACK = 1.0V to 1.5V
Output Current
VCOMP = 1.0V
Soft Start Current
TJ = 25°C
VFEEDBACK =1.0V
VcoMP = 0.5V
TJ = 25°C
Maximum Duty Cycle
Switch Transconductance
VcoMP = 1.5V lsWITCH = 1OOmA TJ = 25°C
---------- ------------ ·--··--
Switch Leakage Current
f--Switch Saturation Voltage
VSWITCH = 65V VFEEDBACK = 1.5V (Switch Off) TJ = 25°C
--+-------
ISWITCH = 2.0A VcoMP = 2.0V (Max Duty Cycle) TJ = 25°C
NPN Switch
Current Limit -
Thermal Resistance
t-1/coMP = 2.0V TJ = 25°C
K Package, Junction to Ambient K Package, Junction to Case
T Package, Junction to Ambient
T Package, Junction to Case
.
--~---------
-···-·
---
--
-
--- -
COMP Pin
VOUT = 0
Sleep Mode Threshold TJ = 25°C
...
---- - - - - - - -... ---------
-·-·-
COMP Pin Current
VcoMP = o
TJ =25°C
UC1577-ADJ MIN. TVP. MAX.
UC2577-ADJ MIN. TYP. MAX. UNITS
±90
±130 1.5
2.5 90 93
±200 5.0 95
±400
+300 9.5
7.5
12.5
600 10
300
0.9 0.5
0.7
3.0
6.0
3.7
4.3
5.3
35 1.5
120
180
130 150 170
35
50
65
40
60
±90
+130 1.5
2.5 90 93
±200 5.0 95
±400
i-300 9.5
7.5
12.5
600 10
300
0.9 0.5
0.7
3.0 3.7
4.3
6.0 5.3
65 2
120
180
130
150 170
35
50
65
40
60
µA µA % AN µA
v
A
°CNV
mV µA
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions the device is intended to be functional, but device parameter specifications may not be guaranteed under these conditions. For guaranteed specifications and test conditions, see the Electrical Characteristics.
Note 2: Output current cannot be internally limited when the UC1577!UC2577 is used as a step-up regulator. To prevent damage to the switch, its current must be externally limited to 6.0A. However, output current is internally limited when the UC1577!UC2577 is used as a f/yback or forward converter regulator in accordance to the Application Hints.
Note 3: External components such as the diode, inductor, input and output capacitors can affect switching regulator performance. When the UC1577!UC2577 is used as shown in the Test Circuit, system performance will be as specified by the system parameters.
Note 4: A 1.0 MQ resistor is connected to the compensation pin (which is the error amplifier's output) to ensure accuracy in measuring AvoL. In actual applications, this pin's load resistance should be~ 10 Mil, resulting in AVOL that is typically twice the guaranteed minimum limit.
Note 5: Comp pin is externally forced to OV. Supply current during sleep mode is tested at VIN= 5Vand could increase with increasing V1N, however, it should typically be less than 500µA within the specified range of VIN.
5-101
Note: Pin numbers shown
VIN
are for T0-220 (T) package
10k
220µF 0.1 µF
4
VIN
SWITCH
1 COMP UC1577/UC2577
2k GND
F.B. 2
0.33µF
3
R1
120 60 24
+
Cour
SBOµF
SW1 SW2
R2
UC1577-ADJ UC2577-ADJ
VouT
L = 415-0930 (AIE) D = any manufacturer
Cour =Sprague Type 673D Electrolytic 680 µF, 20V
Figure 1. Circuit Used to Specify System Parameters
R1 = 48.7k in series with 51 Hl(1%) R2 = 5.62k (1 %)
STEP-UP (BOOST) REGULATOR The Block Diagram shows a Step-Up switching Regulator utilizing the UC1577/UC2577. The regulator produces an output voltage higher than the input voltage when the UC1577 turns its switch on and off at a fixed frequency of 52kHz, thus storing energy in the inductor (L). When the NPN switch is on, the inductor current is charged at a rate of V1N/L. When the switch is turned off, the lower terminal of the inductor rises above Vin, discharging the stored current through the output diode (D) into the output capacitor (Cour) at a rate of (Vour VIN)/L. The energy stored in the inductor is thus transferred to the output.
The output voltage is controlled by the amount of energy transferred, which is controlled by modulating the peak inductor current. This modulation is done by feeding a portion of the output voltage to an error amplifier which amplifies the difference between the feedback voltage and an internal 1.23V precision reference voltage. The output of the error amplifier is than compared to a voltage proportional to the switch current, or the inductor current, during the switch on time. The comparator terminates the switch on time when the two voltages are equal and thus controlling the peak switch current to maintain a constant output voltage. Figure 2 shows voltage and current waveforms for the circuit. Formulas for calculation are shown in Figure 3.
SWITCH VOLTAGE
,--Y VSW(OFF) - ~ - ·
J - VSAT L,_j - L ov - - - - - - - - ·
DIODE VOLTAGE
w
ov
,- ---y-
--
---
~
--
. .
VRJ_L,_J_L__
INDUCTOR CURRENT
SWITCH CURRENT
-~ +t= IND(AVE)
AllND
o--------·
r--1" - ISW(PK) - - ,....._, -
o_J_LJ__L
DIODE CURRENT
ID(PK) IT_- N--- -
ID(AVE)
-
-
-
0 -
-
Figure 2. Step-Up Regulator Waveforms
5-102
UC1577·ADJ UC2577·ADJ
Duty Cycle
D
Average Inductor Current
Inductor Current Ripple
Peak Inductor Current
I----·
Peak Switch Current
Switch Voltage When Off
Diode Reverse Voltage
llND(AVE) AllND llND(PK) lsw(PK) Vsw(OFF)
VA
Vour +VF - VIN Vour - VIN
VoUT + VF - VSAT
Vour
ILOAD 1-D
VIN - VSAT L
5-2,D0-00
ILOAD AllND TD+-2-
-·------1
ILOAD ll.llND
---,---:-0
+--
2
---
·---------!
Vour + VF
Vour - VSAT
D(max) Vour + VF - VIN (min) Vour + VF - 0.6V
where VF = 0.5V for Schottky diodes and 0.8V for fast recovery diodes (typically); E·T, the product of volts x time that charges the inductor:
D(max) (VIN(min) - 0.6V)106
E·T
52,000 Hz
(V·µs)
hND, DC, the average inductor current under full load;
1.05 x ILOAD(max) hND, DC=
1 - D(max)
Average Diode Current
Peak Diode Current
t---
Power Dissipation
Of UC1577/2577
ID(AVE) ID(PK) Po
ILOAD
-IL1O--ADD+ll.-llN2D-
·-
or'a5ne--O-,--A:-[D) ro
+
ILOAD D VIN 50 (1 - D) ~--·-~--~-
VF = Forward Biased Diode Voltage LOAD = Output Load Current
8. Identify Inductor Value:
1. From Figure 4, identify the inductor code for the region indicated by the intersection of E·T and hND, DC. This code gives the inductor value in microhenries. The L or H prefix signifies whether the inductor is rated for a maximum E·T of 90 V·µs (L) or 250 V·µs (H). 2. If D < 0.85, go on to step C. If D ~ 0.85, then calculate the minimum inductance needed to ensure the switching regulator's stability:
Figure 3. Step-Up Regulator Formulas
STEP-UP REGULATOR DESIGN PROCEDURE Given:
VIN (min) = Minimum input supply voltage Vour = Regulated output voltage ILOAD (max) = Maximum output load current First, determine if the UC 1577/ UC2577 can provide these values of Vour and ILOAD (max) when operating with the minimum value of V1N. The upper limits for Vour and ILOAD (max) are given by the following equations.
VOUT:S60V and VOUT $ 10 x VIN (min)
- 6.4 (VIN(min) - 0.6V) (2D(max) -1)
Lmm=
(µH)
1 - D(max)
If LMIN is smaller than the inductor value found in step 81, go on to step C. Otherwise, the inductor value found in step 81 is too low; an appropriate inductor code should be obtained from the graph as follows:
ILOAD(max) $ 2.1 Ax VIN (min) VOUT
These limits must be greater than or equal to the values
specified in this application.
1. Output Voltage Selection
Resistors R1 and R2 are used to select the desired output
voltage. These resistors form a voltage divider and present a
portion of the output voltage to the error amplifier which
compares it to an internal 1.23V reference. Select R1 and R2
such that:
R1
VOUT _ 1
R2 1.23V
2. Inductor Selection (L)
A. Preliminary Calculations:
To select the inductor, the calculation of the following three parameters is necessary: D(max), the maximum switch duty cycle (0 :SD :S 0.9):
~~~~~~~~~~~~~~~~ 70~f-~:7f"-f~'-t~~-~>'-~~+-~
501--~t-+-¥--+-+..+-+-+-.>''---+-+--+--.+-~
~ ......+ -........'-+---+---+--I-«---_,.~-+-+-+-~
40~;:.:.;1£J1.,:+:::::.,..f!:.sJ:=+::.PC.::..::::......ai.::.:.=~-....:+:-..~ ~l---'~l-t~'-+-+-'M--+-.._,~-+-¥-+---'11'-~
20"--'--L....<'-L--L__.__.__._.___
0.3 0.35 0.4 0.45 0.5 0.6 0.7 0.8 0.9 1.0
_...._-"--'--~
1.5 2.0 2.5 3.0 l1ND, DC(A)
Note: This chart assumes that the inductor ripple current inductor is approximately 20% to 30% of the average inductor current (when the re11ulator is under lull load). Greater ripple current causes higher peak switch currents and greater ouput ripple voltage; lower ripple current is achieved with larger-value inductors. The factor of 20 to 30% is chosen as a convenient oalance between the two extremes. Figure 4. Inductor Selection Graph
5-103
uc1sn-ADJ UC25n-ADJ
1. Find the lowest value inductor that is greater than LMIN.
2. Find where E·T intersects this inductor value to determine if it has an L or H prefix. If E·T intersects both the L and H regions, select the inductor with an H prefix.
C. Select an inductor from the table of Figure 5 which cross references the inductor codes to the part numbers of three different manufacturers. Complete specifications for these inductors are available from the respective manufacturers. The inductors listed in this table have the following characteristics:
AIE: ferrite, pot-core inductors; Benefits of this type are low electro-magnetic interference (EMI), small physical size, and very low power dissipation (core loss). Be careful not to operate these inductors too far beyond their maximum ratings for E·T and peak current above rated value better than ferrite cores.
Pulse: powdered iron, torrid core inductors; Benefits are low EMI and ability to withstand E·T and peak current above rated value better than ferrite cores.
Renco: ferrite, bobbin-core inductors; Benefits are low cost and best ability to withstand E·T and peak current above rated value. Be aware that these inductors generate more EMI than the other types, and this may interfere with signals sensitive to noise.
Inductor Code
L47 L68 L100 L150 L220 L330 L470 L680 H150 H220 H330 H470 H680 H1000 H1500 H2200
Manufacturer's Part Number
r----·---·--.-----------------1
AIE
Pulse
Renco
415 - 0932 415-0931 415 - 0930 415 - 0953 415 - 0922 415 - 0926 415 - 0927 415 - 0928 415 - 0936 430 - 0636 430 - 0635 430 - 0634 415 -0935 415 - 0934 415- 0933 415 - 0945
PE-53112 PE-92114 PE - 92108 PE-53113 PE- 52626 PE - 52627 PE- 53114 PE - 52629 PE-53115 PE-53116 PE-53117 PE-53118 PE-53119 PE- 53120 PE- 53121 PE - 53122
RL2442 RL2443 RL2444 RL1954 RL1953 RL1952 RL 1951 RL1950 RL2445 RL2446 RL2447 RL1961 RL1960 RL1959 RL 1958 RL2448
AIE Magnetics, div. Vernitron Corp., (813) 347-218
2801 72nd Street North, St. Petersburg, FL 33710 Pulse Engineering, (619) 268-2400 P.O. Box.12235, San Diego, CA 92112 Renco Electronics Inc., (516) 586-5566 60 Jeffryn Blvd. East, Deer Park, NY 11729
Figure 5. Table of Standardized Inductors and Manufactuers' Part Numbers
3. Compensation Network (Re, Cc) and Output Capacitor (CouT) Selection The compensation network consists of resistor Re and capacitor Cc which form a simple pole-zero network and stabilize the regulator. The values of Re and Cc depend on voltage gain of the regulator, ILOAD(max), the inductor Land output capacitance Cou1. A procedure to calculate and select the values for Re, Cc and CouT which ensures stability is described below. It should be noted, however, that this may not result in optimum compensation. To guarantee optimum compensation a standard procedure for testing loop stability is recommended, such as measuring VouT transient responses to pulsing ILOAD.
A. First, calculate the maximum value for Re.
750 x ILOAD(max) x Vou12
VIN(min)2
Select a resistor less than or equal to this value, and it should also be no greater than 3 kn.
B. Calculate the minimum value for CouT using the following two equations.
0.19 x L x Rex ILOAD(max)
Cour~
V1N(min) x Vour
and VIN(min) x Rex (VIN(min) + (3.74 x 105 x L))
Cour ~ - - - - - - - - - - - - - - - 487,800 x Vour3
The larger of these two values is the minimum value that ensures stability.
C. Calculate the minimum value of Cc.
Cc ~ 58.5 x Vour2 x CouT
Rc2 x VIN(min)
The compensation capacitor is also used in the soft start function of the regulator. When input supply to the part is turned on, the switch duty cycle is increased slowly at a rate defined by the compensation capacitor and the soft start current, thus eliminating high input currents. Without the soft-start circuitry, the switch duty cycle would instantly rise to about 90% and draw large currents from the input supply. For proper soft-starting, the value for Cc should be equal or greater than 0.22µF.
Figure 6 lists several types of aluminum electrolytic capacitors which could be used for the output filter. Use the following parameters to select the right capacitor: Working Voltage (WVDC): Choose a capacitor with a working voltage at least 20% higher than the regulator output voltage.
5-104
Ripple Current: This is the maximum RMS value of current that charges the capacitor during each switching cycle. For step-up and flyback regulators, the formula for ripple current is.
ILOAD(max) x D(max)
IRIPPLE(RMS) =
----
1 - D(max)
Choose a capacitor that is rated at least 50% higher than this value at 52 kHz.
Equivalent Series Resistance (ESR): This is the primary cause of output ripple voltage, and it also affects the values of Re and Cc needed to stabilize the regulator. As a result, the preceding calculations for Cc and Re are only valid if ESR doesn't exceed the maximum value specified by the following equations.
ESR$ 0.01x15V and$8.7x(10)-3XVIN
IRIPPLE(P-P)
ILOAD(max)
where
IRIPPLE(P-P)= 1.15 X ILOAD(MAX) 1 - D(MAX)
Select a capacitor with ESR, at 52 kHz, that is less than or equal to the lower value calculated. Most electrolytic capacitors specify ESR at 120 kHz which is 15% to 30% higher than at 52 kHz. Also, be aware that ESR increases by a factor of 2 when operating at -20°C.
In general, low values of ESR are achieved by using large value capacitors (C ~ 470 µF), and capacitors with high WVDC, or by paralleling smaller-value capacitors.
4. Input Capacitor Selection (C1N) To reduce noise on the supply voltage caused by the switching action of a step-up regulator (ripple current noise), the Input Voltage pin should be bypassed to ground. A good quality 0.1µF capacitor with low ESR should provide sufficient decoupling. If the UC 1577 is located far from the supply source filter capacitors, an extra electrolytic (47µF, for example) is required.
Cornell Dublier-Types 239. 250. 251, UFT, 300, or 350 P.O. Box 128, Pickens, SC 29671 (803) 878-6311
Nichicon-Types PF, PX, or PZ 927 East Parkway, Schaumburg, IL 60173 (708) 843-7500
Sprague-Types 6720, 6730, or 6740 Box 1, Sprague Road, Lansing, NC 28643 (919) 384-2551
United Chemi-Con-Types LX, SXF, or SXJ 9801 West Higgins Road, Rosemont, IL 60018
(708) 696-2000
Figure 6. Aluminum Electrolytic Capacitors Recommended for Switching Regulators
UC1577-ADJ UC2577-ADJ
5. Output Diode Selection (D) In the step-up regulator, the switching diode must withstand a reverse voltage and be able to conduct the peak output current of the UC2577. Therefore a suitable diode must have a minimum reverse breakdown voltage greater than the circuit output voltage, and should also be rated for average and peak current greater than ILOAD (max) and ID(PK). Because of their low forward voltage drop (and thus higher regulator efficiencies,) schottky barrier diodes are often used in switching regulators. Refer to Figure 7 for recommended part numbers and voltage ratings of 1A and 3A diodes.
VouT
(max) 20V 30V
40V 50V
Schottky
1A
3A
1N5817 1N5820 MBR120P MBR320P
1N5818 MBR130P 110003
1N5819 MBR140P 110004
MBR150 110005
1N5821 MBR330P 310003
1N5822 MBR340P 310004
MBR350 310005
100V
Figure 7. Diode Selection Chart
Fast Recovery
1A
3A
1N4933 MUR105
1N4934 HER102 MUR110 10DL1
MRB51 30DL1 MR831 HER302
6. Sleep Mode The UC1577/2577 has a unique feature of Sleep Mode. When the COMP pin is externally forced below the Sleep Threshold of 150 mV, the internal regulator to the IC is disabled, thus substantially reducing Input Supply Quiescent current to 250µA typically, for VIN=5V. This current, however, is dependent on the input supply voltage V1N and will increase with increasing VIN. For the specified range of V1N (2.9V to 40V), the Input Supply Current should be typically less than SOOµA.
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD ·MERRIMACK, NH 03054 TEL 603-424-2410 · FAX 603·424·3460
5-105
n nINTEGRATED
~CIRCUITS
-UNITROCE
Dual Schottky Diode Bridge
i#;~l· ·C· ·u..·.._·..·~·R
~····.············~
UC1610 UC3610
FEATURES Monolithic Eight-Diode Array Exceptional Efficiency Low Forward Voltage Fast Recovery Time High Peak Current Small Size
DESCRIPTION This eight-diode array is designed tor high-current, low duty-cycle applications typical of flyback voltage clamping for inductive loads. The dual bridge connection makes this device particularly applicable to bipolar driven stepper motors.
The use of Schottky diode technology features high efficiency through lowered forward voltage drop and decreased reverse recovery time.
This single monolithic chip is fabricated in both hermetic CERDIP and copper-
leaded plastic packages. The UC161 o in ceramic is designed tor -55°C to +12s0 c o environments but with reduced peak current capability; while the UC361 in plas-
o·c tic has higher current rating over a to +70°C temperature range.
CONNECTION DIAGRAMS
DIL-8 (TOP VIEW) N or J Package
1
ABSOLUTE MAXIMUM RATINGS
Peak Inverse Voltage (per diode) ........................................... 50V Peak Forward Current
UC1610 .............................................................. 1A UC3610 .............................................................. 3A Power Dissipation at TA= +70°C ........................................... 1W Storage Temperature Range.................................... -65°C to +150°C Lead Temperature (Soldering, 1OSeconds) ................................. 300°C
Note: Consult Packaging Section of Databook for thermal /imitations and considerations of package.
SOIC-16 (TOP VIEW) OW Package
PLCC-20 (TOP VIEW) Q Package
3 2 1 20 19
:~~~
6
16
7
15
8
14
9 10 11 12 13
6/93
5-106
UC1610 UC3610
ELECTRICAL CHARACTERISTICS: All specifications apply to each individual diode. TJ = 25°C except as noted. TA= TJ.
PARAMETER Forward Voltage Drop
Leakage Current
Reverse Recov~ Forward Recove_ry_ Junction C~citance
TEST CONDITIONS
IF= 100mA IF= 1A VA =40V VA= 40V TJ = +100°C 0.5A Forward to 0.5A Reverse 1A Forward to 1.1V Recov~ VR=5V
MIN TYP MAX UNITS
0.4 0.5 0.7
v
0.8 1.0 1.3
v
.01 0.1 mA
0.1 1.0 mA
15
ns
30
ns
70
_pf
Note: At forward currents of greater than 1.0A a parasitic current of approximately 1OmA may be collected by adjacent diodes.
Reverse Current vs Voltage
3000 l---+---+---+----+---1 2000 1000 ! - - - ! - - - ! - - _ _ _ _ ,_ ____,_ ___,
500 1---1---f------jr------j---j
1aazw::-
::::>
300
Z 200
100
r----+-_TJ =125 'C
~
50
z
(.)
30 l---+---+---+----+---1
w
20 r---+----+----+--+--~
(.!>
<
lil::
10
w <
...J
5 3
TJ=75'C ..Ll
2 1
1----1-.....T.J,=.2:5.":.:.Q....:~~-t--1
0 10 20 30 40 50
REVERSE VOLT AGE - (V)
Forward Current vs Voltage
3.0 2.0
Z & .,..... LIL.
to
_Lj ILi L
1z -
aaw : :
cit 0.5 l--+-+--W--+--V--V-+---+-+--1
0.3
7
0. 2
V ~ TJ =-55 'C
::::>
(.)
0.1 1--+-l+--c---l-1t-lf~+--~T-J=_2_5_C' --,--<
c .o5 T I
~ .03 r-t--t-t--.....--tt'::=T-=t-TJ = 125 ' C t---1
~ ·-~~ l--++-!'<=1J_4-f--f+--l---t-+-+--+----I
u. .005
.003
IL1
.002 t---+-1-+1-++--+-+--+-+-+-~
.001 0 .2 .4 .6 .8 1.01.21.41.61.8 2.0
FORWARD VOLTAGE - (V)
Reverse Recovery Characteristics
Forward Recovery Characteristics
TIME, 2ns/DIV
r VODLIOTDAEGE
1.0V/DIV
TA·25"C DIODE
..,,VOLTAGE
OV l""'+-'fl'H-tf+++tf+++WH+t+H+f+"t+f+tt+f+t~
'DIODE CURRENT
t DIODE
I CURRENT 500mA/DIV
OA
UC1610 FORWARD RECOVERY
CH1 · Vo CH2 · lo · 1A
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. · !.ERRIMACK, NH 03054 TEL (603) 424-2410 · FAX (603) 424-3460
5-107
n n INTEGRATED
~CIRCUITS
-UNITRODE
Quad Schottky Diode Array
UC1611 UC3611
FEATURES Matched, Four-Diode Monolithic Array High Peak Current Low-Cost MINIDIP Package Low-Forward Voltage Parallelable for Lower VF or Higher IF Fast Recovery Time Military Temperature Range Available
DESCRIPTION
This four-diode array is designed for general purpose use as individual diodes or as a high-speed, high-current bridge. It is particularly useful on the outputs of high-speed power MOSFET drivers where Schottky diodes are needed to clamp any negative excursions caused by ringing on the driven line.
These diodes are also ideally suited for use as voltage clamps when driving inductive loads such as relays and solenoids, and to provide a path for current free-wheeling in motor drive applications.
The use of Schottky diode technology features high efficiency through lowered forward voltage drop and decreased reverse recovery time.
This single monolithic chip is fabricated in both hermetic CERDIP and copper-leaded plastic packages. The UC1611 in ceramic is designed for -55°C to +125°C environments but with reduced peak current capability: while the UC3611 in plastic has higher current rating over a 0°C to +70°C ambient temperature range.
CONNECTION DIAGRAM
DIL-8 (TOP VIEW) N or J Package
SOIC-16 (TOP VIEW) OW Package
PLCC-20 (TOP VIEW) Q Package
3 2 1 20 19
4 I I 1a
534*-1~7
6
16
; r1 ~:
9 10 11 12 13
6/93
5-108
ABSOLUTE MAXIMUM RATINGS
Peak Inverse Voltage (per Diode) ................................. 50V Diode-to-Diode Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80V Peak Forward Current
UC1611 .................................................... 1A UC3611 .................................................... 3A Power Dissipation atTA= +70°C .................................. 1W Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C Lead Temperature (Soldering, 10 Seconds) ....................... +300°C Note: Please consult Packaging Section of Databook for thermal limitations and
considerations ofpackage.
UC1611 UC3611
ELECTRICAL CHARACTERISTICS: All specifications apply to each individual diode. TJ = +25°C except as noted.
TA= TJ.
PARAMETER Forward Voltage Drop
Leakage Current
Reverse Recovery Forward Recovery Junction Capacitance
TEST CONDITIONS IF= 100mA IF= 1A VA= 40V VR = 40V, TJ = +100°C 0.5A Forward to 0.5A Reverse 1A Forward to 1.1V Recovery VR=5V
MIN. 0.3
TYP. 0.4 0.9 0.01 0.1 20 40 100
MAX. UNITS
0.7
v
1.2 v
0.1 mA
1.0 mA
ns
ns
pf
Note: At Forward currents ofgreater than 1.0A, a parasitic current of approximately 1OmA may be collected by adjacent diodes.
Reverse Current vs Voltage
3000 2000
1000
500
1aazw::-
::>
300 200
~ z 100 1---t-- TJ-125'C
L
50
0
30
w
20 1---+--+---+---+--j
C)
<
~
10
< w
5
...J
3
TJ =75 'C
2
2
TJ =25 '..Q.
1 ~-+----+---+---+-~
0 10 20 30 40 50
REVERSE VOLTAGE - (V)
Forward Current vs Voltage
3.0 1--+-+-+--+I -L_._Z~lZhI --+-+-__,___,
~ ~
2.0 1.0
r--+-+--+t1r-tJ-7~"~ +"y~-+---+--+:__,I
1-
ffi
0.5
o.3
:=:=:111_:7:JzZ::~:=1 ===~=~=T~==
g:: 0·2
ITJt-HTJ =-55 'C
5
ac : <
=g=j
.o50.1 l 1.v+---+--TJ=25°C 1---1-I-++-I-l"l![!j:.....j--1-~~~-l---j
.03
L I.
TJ =125 ° C+-1
LII .02 1--1--J.<Oi'f..,.--+--+--+--+--+--+--+--I
.01
u. .005 l---ll-+-11+1--1--1-1--T+-,_T+1-+--1
.003 1--~l+-++--+--+--+--+--+-+--j .002 1--.........,>+-++--+--+--+--<--+-+--I
.001 -~~~-~~~~~~0 .2 .4 .6 .8 1.0 1.21.4 1.61.8 2.0
FORWARD VOLTAGE - (V)
5-109
TYPICAL APPLICATIONS
A. Clamp Diodes - PWMS and Drivers
UC1611 UC3611
PWM/Driver
B. Transformer Coupled Drive Circuits
Ve
UC3611
r-----1
I I
r~60
HZ
I I I
_ _ _ _ _ _J
0.1µ F
C. Linear Regulations
r--------------,
I
UC3611
+
L_J
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD.· MERRIMACK, NH 03054 TEL. (603) 424-2410 · FAX (603) 424-3460
5-110
nL.::::nJ INTEGRATED CIRCUITS
-UNITRODE
UC1612 UC3612
Dual Schottky Diode
FEATURES · Monolithic Two Diode Array · Exceptional Efficiency · Low Forward Voltage · Fast Recovery Time · High Peak Current · Small Size
ABSOLUTE MAXIMUM RATINGS Peak Inverse Voltage (per diode) ........................... 50V Peak Forward Current, UC3612 ............................... 3A Peak Forward Current, UC1612 ............................... 1A Power Dissipation at TA= 70°C .............................. 1W
Derate 12.5mW/°C above 70°C Storage Temperature Range .............. -65°C to +150°C
Lead Temperature (Soldering, 1o Seconds) ....... 300°C
DESCRIPTION The two-diode array is designed for high-current, low duty-cycle applications typical of flyback voltage clamping for inductive loads.
The use of Schottky diode technology features high efficiency through lowered forward voltage drop and decreased reverse recovery time.
This single monolithic chip is fabricated in hermetic CERDIP as well as copper leaded plastic MINIDIP and SOIC surface mount power pack. The UC1612 in ceramic is designed for -55°C to +125°C environments, but with reduced peak current capability; while the UC3612 has higher current rating over a 0°C to +70°C ambient temperature range.
CONNECTION DIAGRAM
J, N or DP PACKAGE (TOP VIEW)
Pins 2,3,6,7 are connected to substrate and must be electrically isolated.
12/92 5-111
UC1612 UC3612
Electrical Characteristics (All specifications apply to each individual diode. TJ =25°C except as noted).
PARAMETER
Forward Voltage Drop
TEST CONDITIONS
IF= 100mA IF= 1A
MIN TYP MAX UNITS
0.49
.55
v
0.90
1.0
v
Leakage Current
VR= 40V V" = 40V, TJ= 100°c
.01
0.1
mA
0.1
1.0
mA
Reverse Recovery
.SA Forward to .5A Reverse
15
nSec
Forward Recovery
1A Forward to 1.1 V Recovery
30
nSec
Junction Capacitance
VR=5V
70
pF
Note: At forward currents of greater than 1.0A, a parasitic current of approximately 1OmA may be collected by adjacent diodes.
Reverse Current vs Voltage
Forward Voltage vs Current
TJ-25C __,
0 10 20 30 40
50
REVERSE VOLTAGE (V)
0 .1 .2 .3 .4 .5 .6 .7 .8 .9 1.0 1.1 1.2 1.3 .001A FORWARD VOLTAGE (V)
5-112
n nINTEGRATED
~CIRCUITS
-UNITRODE
High Speed PWM Controller
UC1823 UC2823 UC3823
FEATURES Compatible with Voltage or Current-Mode Topologies
Practical Operation @ Switching Frequencies to 1.0MHz
50ns Propagation Delay to Output
High Current Totem Pole Output (1.5A peak)
Wide Bandwidth Error Amplifier
Fully Latched Logic with Double Pulse Suppression
Pulse-by-Pulse Current Limiting
Soft Start/Max. Duty Cycle Control
DESCRIPTION
The UC1823 family of PWM control ICs is optimized for high frequency switched mode power supply applications. Particular care was given to minimizing propagation delays through the comparators and logic circuitry while maximizing bandwidth and slew rate of the error amplifier. This controller is designed for use in either current0 mode or voltage-mode systems with the capability for input voltage feed-forward.
Protection circuitry includes a current limit comparator with a 1V threshold, a TIL compatible shutdown port, and a soft start pin which will double as a maximum duty cycle clamp. The logic is fully latched to provide jitter free operation and prohibit multiple pulses at the output. An under-voltage lockout section with SOOmV of hysteresis assures low start up current. During under-voltage lockout, the output is high impedance.
Under-Voltage Lockout with Hysteresis Low Start Up Current (1.1 mA) Trimmed Bandgap Reference (5.1V ±1%)
These devices feature a totem pole output designed to source and sink high peak currents from capacitive loads, such as the gate of a power MOSFET. The on state is defined as a high level.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (Pins 15, 13) ........................ 30V Output Current, Source or Sink (Pins 11, 14)
DC .......................................... 0.5A Pulse (0.5µs) .................................. 2.0A Analog Inputs (Pins 1, 2, 7, 8, 9) .............. -0.3V to +6V Clock Output Current (Pin 4) ....................... -5mA Error Amplifier Output Current (Pin 3) . . . . . . . . . . . . . . . . 5mA Soft Start Sink Current (Pin 8) . . . . . . . . . . . . . . . . . . . . . 20mA
Oscillator Charging Current (Pin 5) .................. -5mA
= Power Dissipation at TA 60 ·c . . . . . . . . . . . . . . . . . . . . . 1W
Storage Temperature Range .............. -65°C to+150°C
Lead Temperature (Soldering, 10 seconds) .......... 300°C Note: All voltages are with respect to ground, Pin 10.
Currents are positive into the specified terminal. Consult Packaging Section of Databook for thermal limitations and considerations ofpackages.
BLOCK DIAGRAM
6/93
Soft Start
1· 1 - - - - - -........
ILIMREF
~---n;,o Ve
~---4 ::>---IHI Out
5.1V >+---------~~~---m· Raf
5-113
CONNECTION DIAGRAMS DIL-16, SOIC-16 (TOP VIEW)
J or N, OW Package
Inv. N.I. E/A Out Clock RT CT Ramp Soft Start
VREF 5.1V Vee Out Ve Pwr Gnd ILIM REF Ground ILIMtS.D.
UC1823 UC2823 UC3823
PLCC-20, LCC-20 (TOP VIEW) Q, LPackage
L a~~~
~
2 1 2019
4
18
5
17
6
16
7
15
8
14
9 10 11 12 13
PACKAGE PIN FUNCTION
FUNCTION
PIN
N/C
1
Inv.
2
N.I.
3
E/AOut
4
Clock
5
N/C
6
RT
7
CT
8
Ram_R
9
Soft start
10
N/C
11
IUM/S.D.
12
Ground
13
ILIM REF
14
PWRGnd
15
N/C
16
Ve
17
OUT
18
Vee
19
VREF 5.1V
20
ELECTRICAL CHARACTERISTICS: Unless otherwise noted, these specifications apply for Rr = 3.65k, Cr =
1nF, Vee= 1sv, 0°c <TA< +10°c for the UC3823, -2s0 c <TA< +ss0 c for
the UC2823, and-55°C <TA< +125°C for the UC1823, TA= TJ.
PARAMETER
TEST CONDITIONS
UC1823 UC2823
MIN TVP MAX
Reference Section
Output Voltage
TJ = 25°C, lo= 1mA
5.05 5.10 5.15
Line Regulation
10 <Vee< 30V
2
20
Load Regulation
1<10<10mA
5
20
Temperature Stability* Total Output Variation*
TMIN < TA< TMAX Line, load, Temp.
0.2 0.4
5.00.
5.20
Output Noise Voltage*
10Hz <f < 10kHz
50
long Term Stability*
TJ = 125°C, 1000 hrs.
5
25
Short Circuit Current
VREF=OV
-15 -50 -100
Osclllator Section
Initial Accuracy*
TJ=25°C
360 400 440
Voltage Stability*
10 <Vee< 30V
0.2
2
Temperature Stability*
TMIN <TA< TMAX
5
Total Variation*
line, Temp.
340
460
Clock Out High
3.9 4.5
Clock Out Low
2.3 2.9
Ramp Peak*
2.6 2.8 3.0
Ramp Valley*
0.7 1.0 1.25
Ramp Valley to Peak*
1.6 1.8 2.0
* These parameters are guaranteed by design but not 100% tested in production.
UC3823
UNITS
MIN TVP MAX
5.00 5.10 5.20 v
2
20 mV
5
20 mV
0.2 0.4 mV!°C
4.95
5.25
50
µV
5
25 mV
-15 -50 -100 mA
360 400 440 kHz
0.2
2
%
5
%
340
460 kHz
3.9 4.5
v
2.3 2.9 v
2.6 2.8 3.0
v
0.7 1.0 1.25 v
1.6 1.8 2.0 v
5-114
UC1823 UC2823 UC3823
ELECTRICAL CHARACTERISTICS: Unless otherwise noted, these specifications apply for RT= 3.65k, Cr= 1nF, Vee = 1sv, o·c < TA < +10°c for the UC3823, -2s0 c < TA < +ss·c for the
UC2823, and -ss·c < TA < +12s0 c for the uc1823, TA = TJ.
PARAMETER
TEST CONDITIONS
UC1823 UC2823
MIN TVP MAX
Error Ampllfler Section
Input Offset Voltage
10
Input Bias Current
0.6
3
Input Offset Current
0.1
1
Open Loop Gain
1<VO<4V
60
95
CMRR
1.5 < VcM < 5.5V
75
95
PSRR
10< Vee< 30V
85 110
Output Sink Current
VPIN 3 =1V
1
2.5
Output Source Current
VPIN3 = 4V
-0.5 -1.3
Output High Volta_[e
IPIN3 = -0.5mA
4.0 4.7 5.0
Output Low Voltage
IPIN3=1mA
0
0.5 1.0
Unity Gain Bandwidth*
3
5.5
Slew Rate*
6
12
PWM Comparator Section
Pin 7 Bias Current
VPIN7 =OV
-1
-5
Duty Cycle Range
0
80
Pin 3 Zero D.C. Threshold
VPIN7 = OV
1.1 1.25
Delay to Output*
50 80
Soft-Start Section
Charge Current
VP1Ns=0.5V
3
9
20
Discharge Current
VPIN8 = 1V
1
Current Limit/Shutdown Section
Pin 9 Bias Current
0 <VPIN9 < 4V
±10
Current Limit Offset
VPIN 11 = 1.1V
15
Current Limit Common Mode Range (VPIN 11)
1.0
1.25
Shutdown Threshold
1.25 1.40 1.55
Delay to Output*
50
80
Output Section
Output Low Level
lour= 20mA
0.25 0.40
lour= 200mA
1.2 2.2
Output High Level
lour= -20mA
13.0 13.5
lour = -200mA
12.0 13.0
Collector Leakage
Ve= 30V
100 500
Rise/Fail Time*
CL= 1nF
30
60
Under-Voltage Lockout Section
Start Threshold
8.8 9.2 9.6
UVLO Hysteresis
0.4 0.8 1.2
Supply Current Start Up Current
Vee= av
1.1 2.5
Ice
VPIN 1, VPIN 7. VPIN 9 =0V, VPIN 2 = 1V
22 33
* These parameters are guaranteed by design but not 100% tested in production.
UC3823
UNITS
MIN TVP MAX
15 mV
0.6
3
µA
0.1
1
µA
60 95
dB
75 95
dB
85 110
dB
1
2.5
mA
-0.5 -1.3
mA
4.0 4.7 5.0
v
0
0.5 1.0
v
3
5.5
MHz
6
12
V/µS
-1
-5
µA
0
85
%
1.1 1.25
v
50
80
ns
3
9
20 µA
1
mA
±10 µA
15 mV
1.0
1.25 v
v 1.25 1.40 1.55
50 80 ns
v 0.25 0.40
1.2 2.2
v
13.0 13.5
v
12.0 13.0
v
100 500 µA
30
60
ns
8.8 9.2 9.6
v
0.4 0.8 1.2
v
1.1 2.5 mA 22 33 mA
5-115
UC1823 PRINTED CIRCU~T BOARD LAYOUT CONSIDERATIONS
High speed circuits- demand careful attention to layout and component placement. To assure proper performance of the UC1823, follow these rules. 1) Use a ground plane. 2) Damp or clamp parasitic inductive kick energy from the gate of driven MOSFET. Don't allow the output pins to ring below ground. A series gate resistor or a shunt t Amp Schottky diode at the output pin will serve
UC1823 UC2823 UC3823
this purpose. 3) Bypass Vee, Ve, and VREF. Use 0.1µF monolithic ceramic capacitors with low equivalent series inductance. Allow less than 1 cm of total lead length for each capacitor between the bypassed pin and the ground plane. 4) Treat the timing capacitor, CT, like a bypass capacitor.
ERROR AMPLIFIER CIRCUIT
Simplified Schematic
ruC1823- - - - - -
VREF 5.1V
Error Amp Output
Open Loop Frequency Response
100
80 ~
60 ~
Av (d8)40
~ i{V
20
0 -20
~
G
~
0
G (')
"!--
-90 -180
Freq (Hz)
5
4 3 (V) 2
Unity Gain Slew Rate
0 0.2 0.4 0.6 0.8 1.0 TIME (µ$)
PWM APPLICATIONS
Conventional (Voltage Mode)
luc1823
Oscillator 1.25V
1 'IW
L_Fr~m E/A
Current-Mode
!SWITCH
RSENSE
*A small fllter may be required to suppress -Itch 5-116
OSCILLATOR CIRCUIT
CT
~
Timing Resistance vs Frequency 100 1K 10K 100K 1M
Freq (Hz)
Deadtlme vs CT (3 '.ORT '.O 100K)
4.70
~
2.20
l2J
., 1.00
0
r ~
f=
0.47
,I.../.
I i
0.22
0.10 P"" 0.047 L~~~~~~~
~~~~~~ td:$3
CT (nF)
Deadtlme vs Frequency
~:~~.OnF
! 120
~ 100
470 F
80
10K
100K
1M
Freq (Hz)
SYNCHRONIZED OPERATION
Two Units in Close Proximity
I
~r I RT 5
=
I Cr 6
LMasterJ
C
T
~
Local Ramp
LSlave .J
Generalized Synchronization
lUC1823
!
fuc1a23l
~CT
CT e
J L Master Local Ramp
I! I I 2N2222
i:f~ I 43 0.1tF ():$
~ I ~ T 43 0.1iµ:F-
' ..... 24
I I 43 0.1F/..1,F- To ,
J 470
Other
24
Slaves ,
I ....- =
RT
CT~ Cr
L Local Slave
Ramp
5-117
UC1823 UC2823 UC3823
CONSTANT VOLT-SECOND CLAMP CIRCUIT
The circuit shown here will achieve a constant volt-second product clamp over varying input voltages. The ramp generator components, RT and CR are chosen so that the ramp at Pin 9 crosses the 1V threshold at the same time the desired maximum volt-second product is reached. The delay through the inverter must be such that the ramp capacitor can be completely discharged during the minimum deadtime.
UC1823 UC2823 UC3823
OUTPUT SECTION
Rise/Fall Time (CL·1NF}
Vee
bl0.2 (A)
Ve
~
> 7
15
10
·
-0.2
8 5
Out
> 0 0~2~~~
Time - (ns}
Pwr Gnd
Saturation Curves
Gnd
Rise/Fall Time (CL-10NF}
R ~L(A)
15
-2
~ 10
~ 5
> 0
o~~~~~
Time - (ns}
5
>
0.5 1.0 1.5 lour - (A)
FEED FORWARD TECHNIQUE FOR OFF-LINE VOLTAGE MODE APPLICATION
VIN
RFF
UC1823l - - - - - - H 7 1 Ramp
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. · !.ERRIMACK, NH 03054 TEL (603) 424-2410 ·FAX (803) 424·3480
5-118"
n nINTEGRATED
~CIRCUITS
-UNITRODE
High Speed PWM Controller
(8)
UC1823A,B/1825A,B UC2823A,B/2825A,B UC3823A, B/3825A, B
PRELIMINARY
FEATURES
"Bold Type" Denotes improved or new
features
· Improved versions of the UC3823/UC3825 PWMs
· Compatible with Voltage or Current-Mode Topologies
· Practical Operation at Switching Frequencies to 1MHz
· sons propagation delay to Output
·High Current Dual Totem Pole Outputs (2A Peak)
·Wide Bandwidth Error Amplifier ·Trimmed Oscillator Discharge Cur-
rent for Accurate Frequency & Dead Time Control
· Fully Latched Logic with Double Pulse Suppression
· Soft Start Control
·Pulse by Pulse Current Limiting Comparator
· Latched Over-Current Comparator With Full Cycle Restart
· Low Start Up Current - 1 OOuA typ. ·Under Voltage Lock Out -16V/10V
On & Off ("B" versions) · Outputs Active Low During UVLO ·Trimmed Bandgap Reference ·Adjustable Blanking For Leading Edge Noise Tolerance
DESCRIPTION
The UC3823A & Band the UC3825A & B family of PWM control ICs are improved versions of the standard UC3823 & UC3825 lamily. Performance enhancements have been made to several of the circuit blocks. Error amplifier gain bandwidth product is 12MHz while input offset voltage is 2mV. Current limit threshold is guaranteed to a tolerance of 5%. Oscillator discharge current is specified at 10 mA for accurate dead time control. Frequency accuracy is improved to 6%. Start up supply current, typically 100uA, is ideal for off-line applications. The output drivers are redesigned to actively sink current during UVLO at no expense to the start up current specification. In addition each output is capable of 2A peak currents during transitions.
Functional improvements have also been implemented in this family. The UC3825 shutdown comparator is now a high-speed over-current comparator with a threshold of 1.2V. The over-current comparator sets a latch that ensures full discharge of the soft start capacitor before allowing a restart. While the fault latch is se~ the outputs are in the low state. In the event of continuous faults, the soft start capacitor is fully charged before discharge to insure that the fault frequency does not exceed the designed soft start period. The UC3825 Clock pin has become Clk/LEB. This pin combines the functions of clock output and leading edge blanking adjustment and has been buffered for easier interfacing.
The UC3825A,B has dual alternating outputs and the same pin configuration of the UC3825. The UC3823A,B outputs operate in phase with duty cycles from zero to less than 100%. The pin configuration of the '23A,B is the same as the UC3823 except pin 11 is now an output pin instead of the reference pin to the
current limit comparator. "A" version parts have UVLO thresholds identical to the original UC3823/25. The
"8" versions have UVLO thresholds of 16 and 10V, intended for ease of use in off-line applications.
Consult Application Note U-128 for detailed technical and applications information. Contact the factory for further packaging and availability information.
Device
UVLO(V)
D(MAX)
UC3823A UC38238 UC3825A UC3825B
9.2/8.4 16110 9.218.4 16/10
< 100% < 100% <50% <50%
6193
*Note: 1823A,B Version Toggles Q and Qare always low
5-119
UC1823A,B/1825A,B UC2823A,B/2825A,B UC3823A,B/3825A,B
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (Pins 15, 13)
................ 22V
Output Current, Source or Sink (Pins 11-14)
DC..................................
.......................... .
... 0.5A
Pulse (0.5µs) ...... .
. .. 2.2A
Power Ground (Pin 12) .......... .
. ...... +/-0.2V
Analog Inputs
(Pins 1,2,7).....................
..... ·0.3V to 7V
(Pin 9, 8) ............................
........... ·0.3V to 6V
Clock Output Current (Pin 4)... ....................
............. ·5mA
Error-Amplifier Output Current (Pin 3) ...............................................5mA
Soft Start Sink Current (Pin 8) ..... .
...............................20mA
Oscillator Charging Current (Pin 5) ............ Power Dissipation at TA=60°C ..................
.............................. -5mA ........... :................ 1W
Storage Temperature Range ............................
.-65°C to +150°C
Lead Temperature (Soldering 10 seconds) ..., ..............
. ...... 300°C
Note: All voltages are with respect to ground Pin 1O
Currents are positive into the specified terminal.
Consult packaging section of Databook for thermal
limitations and considerations of package.
CONNECTION DIAGRAMS
TOP VIEW DIL-16 J or N Package; SOIC-16, OW Package
INV. 1 N.I. 2
E/A OUT 3 CLK/LEB ·
TOP VIEW PLCC-20, LCC-20 Q&L Packages
L3 2 20 19
4
18
5
17
6
16
7
15
8
14
9 10 11 12 13
PACKAGE PIN FUNCTION
FUNCTION
PIN
N/C
1
Inv.
2
N.I.
3
E/AOut
4
Clk/LEB
5
N/C
6
RT
7
CT
8
Ram~
9
SS
10
N/C
11
I LIM
12
GND
13
Out A
14
PGND
15
N/C
16
Ve
17
OutB
18
Vee
19
VREF
20
Electrical Characteristics: Unless otherwise specified, these specifications apply for RT= 3.65k, CT= 1nF, Vee= 12V, and -55° <TA<125°C
for the UC18xxX, -40"<TA<85°C for the UC28xxX, 0° <TA<70°C for the UC38xxX. TJ=TA.
PARAMETER
TEST CONDITION
MIN
TYPE
MAX
UNITS
REFERENCE SECTION Output Voltage Line Regulation Load Regulation Total Output Variation Temperature Stability Output Noise Voltage Long Term Stability Short Circuit Current
TJ = 25°C, lo= lmA 12<VCC<20V 1<1o<10mA Line, Load, Temp TMIN<TA<lMAX, (NOTE 1) 10Hz<k10kHz, (Note 1) TJ = 125°C, 1000 hours, (Note 1) VREF = OV
5.05
5.1
5.15
v
2
15
mV
5
20
mV
5.03
5.17
v
0.2
0.4
mV/"C
50
µVRMS
5
25
mV
30
60
90
mA
OSCILLATOR SECTION Initial Accuracy Total Variation Voltage Stability Temperature Stability Initial Accuracy Total Variation
TJ = 25°C, (Note 1) Line, Temp, (Note 1) 12<VCC<20V TMIN<TA<TMAX, (NOTE 1) RT= 6.6k, CT= 220pF, TA= 25"C, (Note 1) RT= 6.6k, CT= 220pF, (Note 1)
375 350
0.9 0.85
400
425
kHz
450
kHz
1
%
5
%
1
1.1
MHz
1.15
MHz
5-120
UC1823A,B/1825A,B UC2823A,B/2825A,B UC3823A,B/3825A,B
Electrical Characteristics (Continued) Unless otherwise specified, these specifications apply for Rr = 3.65k, Cr= 1nF, Vee= 12v,
and -55° <TA<125'C for the UC18xxX, -40'<TA<85°C for the UC28xxX, 0° <TA<70'C for the
UC38xxX. TJ=TA.
PARAMETER
TEST CONDITION
OSCILLATOR SECTION (CONTINUED)
Clock Out High
Clock Out Low
Ramp Peak
Ramp Valley
Ramp Valley to Peak
Osc Discharge Current
RT= open, V(CT) = 2V
ERROR AMPLIFIER SECTION
Input Offset Voltage
Input Bias Current
Input Offset Current
Open Loop Gain
1<Vo<4V
CMRR
1.5<VCM<5.5V
PSRR
12<VCC<20V
Output Sink Current
Vpin3 = 1V
Output Source Current
Vpin3 = 4V
Output High Voltage
I pin3 = ·0.5mA
Output Low Voltage
I pin3 = 1mA
Gain Bandwidth Product
F = 200KHz
Slew Rate
(Note 1)
PWM COMPARATOR SECTION
Pin 7 Bias current
Vpin7 =OV
Minimum Duty Cycle
Maximum Duty Cycle
Leading Edge Blanking
R = 2k, C = 4 70pF
LEB Resistor
Vpin4 = 3V
Pin 3 Zero D.C. Threshold
Vpin7 =av
Delay to Output·
Vpin3 = 2.1V, Vpin7 = 0 to 2V step, (Note 1)
CURRENT LIMIT I START SEQUENCE I FAULT SECTION
Soft Start Charge Current
Vpin8 = 2.5V
Full Soft Start Threshold
Restart Discharge Current
Vpin8 = 2.5V
Restart Threshold
Pin 9 Bias Current
0<Vpin9<2V
Current Limit Threshold
Over Current Threshold
I LIM Delay to Output
Vpin9 =Oto 2V step, (Note 1)
OUTPUT SECTION
Output Low Saturation
lour= 20mA
lour= 200mA
Output High Saturation
lour= 20mA
lour= 200mA
UVLO Output Low Saturation
lo= 20mA
Rise/Fall Time
CL= 1nF, (Note 1)
MIN
3.7
2.6 0.7 1.6 9
60 75 85 1 ·0.5 4.5 0 6 6
85 300 8.5 1.1
8 4.3 100
0.95 1.14
TYPE
4 0 2.8 1 1.8 10
2 0.6 0.1 95 95 110 2.5 ·1.3 4.7 0.5 12 9
·1
375 10 1.25 50
14 5 250 0.3
1 1.2 50
0.25 1.2 1.9 2 0.8 20
MAX
UNITS
v
0.2
v
3
v
1.25
v
2
v
11
mA
10
mV
3
µA
1
µA
dB
dB
dB
mA
mA
5
v
1
v
MHz
Vlµ.s
·8
µA
0
%
%
450
ns
11.5
kohm
1.4
v
80
ns
20
µA
v
350
µA
0.5
v
15
µA
1.05
v
1.26
v
80
ns
0.4
v
2.2
v
2.9
v
3
v
1.2
v
45
ns
5·121
UC1823A,B/1825A,B UC2823A,B/2825A,B UC3823A,B/3825A,B
Electrical Characteristics (Contlnued):Unless otherwise specified, these specifications apply for RT= 3.65k, CT= 1nF, Vee= 12V, and ·55° <TA<125°C for the UC18xxX, -40°<TA<85°C tor the UC28xxX, 0° <TA<70°C for the UC38xxX. TJ=TA.
PARAMETER
TEST CONDITIONS
UNDER VOLTAGE LOCKOUT
Start Threshold
UCX823B and X825B only
Stop Threshold
UCX823B and X825B only
UVLO Hysteresis
UCX823B and X825B only
Start Threshold
UCX823A and X825A only
UVLO Hysteresis
UCX823A and X825A only
SUPPLY CURRENT
Start Up Current
Ve= Vee= VTH(start) · 0.5V
Ice
Note 1: This parameter is guaranteed by design but not 100% tested in production.
MIN
TYPE
MAX
UNITS
16
17
v
9
10
v
5
6
7
v
8.4
9.2
9.6
v
0.4
0.8
1.2
v
100
300
µA
28
36
mA
APPLICATIONS INFORMATION
OSCILLATOR
The 3823A,Bl3825A,B oscillator is a saw tooth. The rising edge is governed by a current controlled by the RT pin and value of capacitance at the CT pin. The falling edge of the sawtooth sets dead time tor the outputs. Selection of RT should be done first, based on desired maximum Duty Cycle. CT can then be chosen based on desired frequency, RT, and DMAX. The design Equations are:
RT= ____sv_ _ __
(10mA)(1 · DMAX) CT= --~(1_.6_·_D_M_AX~)_ _
(RT·F)
Recommended values for RT range from 1K to 100K. Control of DMAX less than 70% is not recommended.
OSCILLATOR
RT : ..,.... l_F!
5
3V
CT
G1 - - - - - + - -.... .11"
CLK
~ ID=10mA
'---------------
OSC. FREQ vs RT & Cr CURVE
DMax(%)
MAX. DUTY CYCLE vs RT CURVE
100.0
l.l/..-470pF ..........
FREQ (kHz)
100~= 1~
C=22nF
-= -
95.0
k'.'. V1
kj
-r85.0
80.0
l75.0
rH ~
101~--~-~~~~~~10~--~-~-~~~~~100 70.01
10
100
Rt(kohms)
Rt{kohms)
5-122
APPLICATIONS INFORMATION (Continued)
UC1823A,B/1825A,B UC2823A,B/2825A,B UC3823A,B/3825A,B
LEADING EDGE BLANKING
The UC3823A,B/3825A,B performs fixed frequency pulse width modulation control. The '23A,B outputs operate together at the switching frequency and can vary from Oto some value less than 100%. The '25A,B outputs are alternately controlled. During every other cycle, one output will be off. Each output, then, switches a one-half oscillator frequency, varying in duty cycle from 0 to less than 50%.
To limit maximum duty cycle, the internal clock pulse blanks both outputs low during the discharge time of the oscillator. On the falling edge of the clock, the appropriate output(s) is driven high. The end of the pulse is controlled by the PWM comparator, current limit comparator, or the over current comparator.
Normally the PWM comparator will sense a ramp crossing a control voltage (error amp output) and terminate the pulse. Leading edge blanking (LEB) causes the PWM comparator to be ignored for a fixed amount of time after the start of the pulse. This allows noise inherent with switched mode power conversion to be rejected. The PWM ramp input may not require any filtering as result of leading edge blanking. After the LEB interval, the PWM comparator can terminate the pulse.
To program a Leading Edge Blanking period, connect a capacitor, C, to Clk/LEB. The discharge time set by C and the internal 1Ok resistor will determine the blanked interval. The 10k resistor has a 10% tolerance. For more accuracy, an external 2k 1% resistor, R, can be added, resulting in an equivalent resistance of 1.66k with a tolerance of 2.5% The design equation is:
tLEB =0.5 ·(R [ [ 10k) · C.
Values of R less than 2k should not be used.
LEB OPERATIONAL WAVEFORMS
CT
RAMP INPUT BLANKED RAMP TOPWM
Leading edge blanking is also applied to the current limit comparator. After LEB, if the Ill M pin exceeds the one volt threshold, the pulse is terminated. The over current comparator, however, is not blanked. It will catch catastrophic over current faults without a blanking delay. Any time the I LIM pin exceeds 1.2V, the fault latch will be set and the outputs driven low. For this reason, some noise filtering may be required on the I LIM pin.
UVLO, SOFT START AND FAULT MANAGEMENT
Soft start is programmed by a capacitor on the SS pin. At power up, the SS pin is discharged. When the SS pin is low, the error amp output is forced to also be low. As the internal 9uA source charges the SS pin, the error amp output follows until closed loop regulation takes over.
SOFT START AND FAULT WAVEFORMS
1.2V ·· ·············-··
----------------------1---1-----
FAULT
Any time that the I LIM pin exceeds 1.2V, the fault latch will be set and
the output pins will be driven low. The soft start cap is then discharged
by a 250uA current sink. No more output pulses are allowed until soft
Vss
start is fully discharged, and the I LIM pin is below 1.2V. At this point
the fault latch will be reset and the chip will execute a soft start.
Should the fault latch be set during soft start, the outputs will be immediately terminated, but the soft start cap will not be discharged until it has been fully charged. This results in a controlled hiccup interval for continuous fault conditions.
ON ··
PWM
5-123
APPLICATIONS INFORMATION (Continued)
ACTIVE LOW OUTPUTS DURING UVLO
The UVLO function forces the outputs to be low and considers both Vee and Vref before allowing the chip to operate.
OUTPUTV & I DURING UVLO
·55'CL.
I
Vout
X
i...--r- 25'C
(V)
Vee- OPEN
0 0'--''--'~-o~.2_.._.._.__o~.4_.__._.....__~o.-s_,__,__,_o~.a_.__.__._~1.o Current (Amps)
UC1823A,B/1825A,B UC2823A,B/2825A,B UC3823A,B/3825A,B
SIMPLIFIED SCHEMATIC
vcc
OUT
PGND
SYNCHRONIZATION
The oscillator can be synchronized by an external pulse inserted in series with the timing capacitor. Program the free running frequency of the oscillator to be 10 to 15% slower than the desired synchronous frequency. The pulse width should be greater than 1Ons and less than half the discharge time of the oscillator. The rising edge of the Clk/LEB pin can be used to generate a synchronizing pulse for other chips. Note that, the Clk/LEB pin will no longer accept an incoming synchronizing signal.
GENERAL OSCILLATOR SYNCHRONIZATION
VSYNC
RT :
~
=
I
(
39Q
CT I
,.---NV--4==:;!1===t--AN'--T--~~
100 ·- -... ---.
SQQ External
Clock
OPERATIONAL WAVEFORMS
VSYNC _fl.______.n.____
VCT
TWO UNITS
I
I
---39~p·F1~~.1~2~020~2-nlC.T_...I~I
4.7K
..
I
I
I
:slave
' I
1.15RT :
~
5-124
APPLICATIONS INFORMATION (Continued)
PWM APPLICATIONS
CURRENT MODE
.........-v: ISWITC-H
~r---4CTt----fi!lC--T-.-JI Oscillator
;RA)rr> ..J'1..J" i 125V
R~&
:
FromfJA
UC1823A,B/1825A,B UC2823A,B/2825A,B UC3823A,B/3825A,B
VOLTAGE MODE
Oscillator
:er
'
;
1~5~
~RAMP ~
:
FromE/A
·---- --- --------- --- ---
HIGH CURRENT OUTPUTS
Each totem pole output of the UC3823A,B and UC3825A.B can deliver a 2 amp peak current into a capacitive load. The output can slew a 1000pF capacitor 15 volts in approximately 20 nanoseconds. Separate collector supply (Ve) and power ground (PGND) pins help decouple the ICs analog circuitry from the high power gate drive noise. The use of 3 Amp SCHOTTKY diodes (1N5120, USD245 or equivalent) as shown in the figure from each output to both Ve and PGND are recommended. The diodes clamp the output swing to the supply rails, necessary with any type of inductive/capacitive load, typical of a MOSFET gate. SCHOTIKY diodes must be used because a low forward voltage drop is required, and most 3 amp devices will suffice. 00 NOT USE standard silicon diodes.
Although a "single ended" device, two output drivers are available on the UC3823A,B devices. These can be "paralleled" through a series one-half ohm (noninductive) resistor for a combined peak current of 4 amps.
GROUND PLANES
POWER MOSFET DRIVE CIRCUIT
Ve 10uf
= GND
D1,D2,=1N5820
Each output driver of these devices is capable of 2A peak currents. Careful layout is essential for correct operation of the chip. A ground plane must be employed. A unique section of the ground plane must be designated for high ci/dt currents associated with the output stages. This point is the power ground to which the PGND pin is connected. Power ground can be separated from the rest of the ground plane and connected at a single point, although this is not strictly necessary if the high diidt paths are well understood and accounted for. Vee should be bypassed directly to power ground with a good high frequency capacitor. The sources of the power MOSFET should connect to power ground as should the return connection for input power to the system and the bulk input capacitor. The output should be clamped with a high current Schottky diode to both Vee and PGND. Nothing else should be connected to power ground.
Vref should be bypassed cirectly to the signal portion of the ground plane with a good high frequency capacitor. Low esr/esl ceramic 1uF capacitors are recommended for both Vee and VREF. All analog circuitry should likewise be bypassed to the signal ground plane.
----S-IG-N-A-L-G-R-O-U-ND---
5-125
:_------------~~~=~~~~~~0---------_j
APPLICATIONS INFORMATION (Continued) OPEN LOOP TEST CIRCUIT
l lCill
Rr 3.65K Cr
= l
50 22K
27K
10K , ...._-a
3.3K
UC3823NB, UC3825NB
Clk/LEB vcc
E/A OUT )
NON INV !~~OR
INV SOFT START
PWR GNO GND
ILIM
5.1V
UC1823A,B/1825A,B UC2823A,B/2825A,B UC3823A,B/3825A,B
This test fixture is useful for exercising many of the UC3823A,B, UC3825A,B functions and measuring their specifications.
As with any wideband circuit, careful grounding and bypass procedures should be followed. The use of a ground plane is highly recommended.
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD.· MERRIMACK, NH 03054 TEL.(603) 424-2410 ·FAX (603) 424-3460
5-126
n n L:::::::!J
INTEIJRATED CIRCUITS
-UNITROCE
High Speed PWM Controller
UC1824 UC2824 UC3824
FEATURES Complimentary Outputs
Practical Operation Switching Frequencies to 1MHz 50ns Propagation Delay to Output
High Current Dual Totem Pole Outputs (1.5A Peak) Wide Bandwidth Error Amplifier
Fully Latched Logic with Double Pulse Suppression Pulse-by-Pulse Current Limiting
Soft Start I Max. Duty Cycle Control
Under-Voltage Lockout with Hysteresis
Low Start Up Current (1.1 mA)
DESCRIPTION
The UC1824 family of PWM control ICs is optimized for high frequency switched mode power supply applications. Particular care was given to minimizing propagation delays through the comparators and logic circuitry while maximizing bandwidth and slew rate of the error amplifier. This controller is designed for use in either currentmode or voltage mode systems with the capability for input voltage feed-forward.
Protection circuitry includes a current limit comparator with a 1V threshold, a TTL compatible shutdown port, and a soft start pin which will double as a maximum duty cycle clamp. The logic is fully latched to provide jitter free operation and prohibit multiple pulses at an output. An under-voltage lockout section with 800mV of hysteresis assures low start up current. During under-voltage lockout, the outputs are high impedance.
These devices feature totem pole outputs designed to source and sink high peak currents from capacitive loads, such as the gate of a power MOSFET. The on state is designed as a high level.
Trimmed Bandgap Reference (5.1 V ± 1%)
BLOCK DIAGRAM
CT
1.25V
Soft Start
Vee
Gnd 1/93
G
~---<a REF,_.---------------n
e I
Gen
5-127
UDG-92034
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage (Pins 13, 15) ........................ 30V Output Current, Source or Sink (Pins 11, 14) DC ........·.................................. 0.5A Pulse (0.5ms). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0A Analog Inputs (Pins 1, 2, 7) . .. . . . . .. .. . . . . .. . . .. . . .. . . .. . . -0.3V to 7V (Pin 8, 9) .................................. ·0.3V to 6V Clock Output Current (Pin 4) ....................... -5mA Error Amplifier Output Current (Pin 3) . . . . . . . . . . . . . . . . 5mA Soft Start Sink Current (Pin 8) . . . . . . . . . . . . . . . . . . . . . 20mA Oscillator Charging Current (Pin 5) .................. -5mA Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W Storage Temperature Range .............. -65°C to+150°C Lead Temperature (Soldering, 10 seconds) .......... 300°C Note 1: All voltages are with respect to GND (Pin 1O); all currents are positive into, negative out ofpart; pin numbers refer to DIL-16 package. Note 3: Consult Unitrode Integrated Circuit Databook for thermal /imitations and considerations ofpackage.
SOIC-16 (Top View) DW Package
CONNECTION DIAGRAMS
DIL-16 (Top View)
J Or N Package
~
INV ~
P!I VREF 5.1V
NI[!!
E/A Out(I
Clock [I
RT~
cr(!j
Ramp[!j
Solt Start [I
li!Jvcc
~INVOUT
l!!Jvc
l!!IPwr Gnd
~Out ~Gnd ~ILIM/SD
UC1824 UC2824 UC3824
PLCC-20 & LCC-20 (Top View) Q & L Packages
L3 2 1 2019
4
18
5
17
6
16
7
15
8
14
9 10 11 12 13
~~~~~
PACKAGE PIN FUNCTION
FUNCTION
PIN
NC
1
INV
2
NI
3
~Out
4
Clock
5
NC
6
Rr
7
Cr
8
Ran:m_
9
Soft Start
10
NC
11
ILIM.§D
12
Gnd
13
Out
14
PwrGnd
15
NC
16
Ve
17
INVOUT
18
Vee
19
VREF 5.1V
20
ELECTRICAL CHARACTERISTICS: Unless otherwise stated.these specifications apply for, Rr = 3.65k, Cr= 1nF, Vee
= 15V, -55°C<TA<125°C for the UC1824, -40°C<TA<85°C for the UC2824, and
0°C<TA<70°Cforthe UC3824, TA=TJ.
PARAMETERS
Reference Section OutQut Voltage Line Regulation Load RE19_ulation Tell_!E_erature Stabi~ Total Out_E_ut Variation* OU!e_ut Noise VoltCIQ_e* Lo'!9_Term Stabil~ Short Circuit Current
Oscillator Section Initial Accura~ Volt!IQEl Stabili_ty*
Tem~rature Stabi~
Total Variation*
TEST CONDITIONS
= TJ 25°C, lo= 1mA
10V < Vee < 30V 1mA <lo< 10mA TMIN <TA< TMAX Line, Load, Tem_E_erature 10Hz <f < 10kHz
= TJ 125°C, 1OOOhrs.
VREF =OV
TJ=25°C 10V < Vee < 30V TMIN <TA< TMAX Line, Temperature
UC1824 UC2824 MIN TYP MAX
UC3824 MIN TYP MAX UNITS
5.05 5.00 -15
5.10 2 5 0.2
50 5 -50
5.15 20 20 0.4 5.20
25 -100
5.00 4.95 -15
5.10 2 5 0.2
50 5 ·50
5.20 20 20 0.4 5.25
25 -100
v
mV mV mVl°C
v
-2:._V mV mA
360 400 440 360 400 440 kHz
0.2
2
0.2
2
%
5
5
%
340
460 340
460 kHz
5-128
ELECTRICAL CHARACTERISTICS (cont.)
UC1824 UC2824 UC3824
Unless otherwise stated,these specifications apply for, RT= 3.65k, Cr= 1nF, Vee = 15V, -55°C<TA<125°C for the UC1824, -40°C<TA<85°C for the UC2824, and 0°C<TA<70°C for the UC3824, TA=TJ.
PARAMETERS
TEST CONDITIONS
Oscillator Sectlon_{!:ontl_
Clock Out H.!g_h
Clock Out Low
Ram_e._Peak*
Ram_e._Vall~
Ram..E_Vall~to Peak* Error A~lfler Section
l~t Offset Volta_g_e
ll1f.l_ut Bias Current
ll1f.l_ut Offset Current
O~n Loe>e_Gain
1V <VO< 4V
CMRR
1.5V < VeM < 5.5V
PSRR
10V <Vee< 30V
Out_e._ut Sink Current
VPIN3=1V
Out_e._ut Source Current
VPIN3 = 4V
Out_e._ut H.!g_h Volt~e Out_e._ut Low Volt~e
IPIN 3 = -0.5mA IPIN3 = 1mA
Un!!¥_Gain Bandwidth*
Slew Rate*
PWM Com_J)_arator Section
Pin 7 Bias Current
VPIN7 = OV
Duty_Qycle Range
Pin 3 Zero DC Threshold VPIN7 = OV
Del~to OU!E!Jt*
Soft-Start Section
Cha!:9._e Current
VPINB = 0.5V
Discha!:9._e Current
VPINB = 1V
Current Limit I Shutdown Section
Pin 9 Bias Current
0 < VPIN9< 4V
Current Limit Threshold
Shutdown Threshold
Del~to OU!E!Jt
Out_e._ut Section
Output Low Level
lour =20mA
lour =200mA
Output High Level
lour= -20mA
Collector Leak~e
lour= -200mA Ve=30V
Rise/Fall Time*
CL= 1nF
Under-VoHqe Lockout Section
Start Threshold
UVLO l:Jysteresis
Supply Current Section
Start Ujl_Current
VCC=6V
ICC
VPIN 1, VPIN 7, VPIN 9 = OV; VPIN 2 = 1V
* This parameter not 100% tested in production but guaranteed by design.
UC1824 UC2824
MIN TYP MAX
3.9 4.5 2.3 2.9
2.6 2.8 3.0 0.7 1.0 1.25 1.6 1.8 2.0
10
0.6
3
0.1
1
60 95
75
95
85 110
1
2.5
-0.5 -1.3
4.0 4.7 5.0
0
0.5 1.0
3
5.5
6
12
-1
-5
0
80
1.1 1.25
50
80
3
9
20
1
0.9 1.25
1.0 1.40 50
15 1.1 1.55 80
13.0 12.0
0.25 1.2 13.5 13.0 100 30
0.40 2.2
500 60
8.6 9.2 9.6 0.4 0.8 1.2
1.1 2.5 22 33
UC3824
MIN TYP MAX UNITS
3.9 4.5
v
2.3 2.9
v
2.6 2.8 3.0
v
0.7 1.0 1.25 v
1.6 1.8 2.0
v
15 mV
0.6 0.1 60 95
3
~
1 ~
dB
75
95
dB
85 110
dB
1
2.5
mA
-0.5 -1.3
mA
4.0 4.7 5.0
v
0
0.5 1.0
v
3
5.5
MHz
6
12
V!.JE!.
-1
-5 mA
0
85
%
1.1 1.25
v
50
80
ns
3
9
20 µA
1
mA
10 µA
0.9 1.0 1.1
v
1.25 1.40 1.55 v
50
80
ns
0.25 0.40 v
1.2 2.2
v
13.0 13.5
v
12.0 13.0
v
10 500 ~
30
60
ns
6.8 9.2 9.6
v
0.4 0.8 1.2
v
1.1 2.5 mA 22 33 mA
5-129
UC1824
UC1824 Printed Circuit Board Layout Considerations
UC2824 UC3824
High speed circuits demand careful attention to layout and component placement. To assure proper performance of the UC1824 follow these rules: 1) Use a ground plane. 2) Damp or clamp parasitic inductive kick energy from the gate of driven MOSFETs. Do not allow the output pins to ring below ground. A series gate resistor of a shunt 1 Amp Schottky diode at the output pin will serve this purpose. 3)
Bypass Vee, Ve, and VREF. Use 0.1 µF monolithic ceramic capacitors with low equivalent series inductance. Allow less than 1 cm of total lead length for each capacitor between the bypassed pin and the ground plane. 4) Treat the timing capacitor, CT, like a bypass capacitor.
Error Amplifier Circuit
Open Loop Frequency Response
100
Unity Gain Slew Rate
Av
40f----+-+-~---+--r-
(dB)
20f----+-+---t~'<-l---t---
0 I---+-+---+--+--_,..+-- 0 .0' (')
-20 f---"'1---1---';;.......i--4.,--t--- -90
~~~~~~-J-1ao
100 1K 10K 100K 1M 10M 100M
FREQ (Hz)
0.2 0.4 0.6 0.8 1.0 TIME (µs)
Synchronized Operation
Two Units in Close Proximity
jUc1e24
uc1e24]
I Clock 4
I
I
RT
~ I
I
~Local
CT 6
Ramp
Irr U,.aster -!-CT
_
~aveJ
I ue1a24
VREF 1
I
I
I
Generalized Synchronization
I
I
I
I ue1a24 J
I I
I
I
Local Ramp
5-130
Local Ramp
Oscillator Circuit
juc1e24 - - -
UC1824 UC2824 UC3824
Primary Output Deadtime vs CT (3k s RT s 100k)
70--1 4.70 t-----t---t--+---+-----+-1-----¥-
2~ 1-----t---+---+--+-~~~:__-+-~
j, 1.00 r---+--+--]7+--v-j/-+-1-+---1
{:. 0.47 1-----t---+-v--,,l(L-+- 1-t- -, - + - -
0.22 r---.L'.'1-+v---+-----+~>-------l-----___j 0.10 f'~"'-t---+---+--+--+-----+--1 0.047 ~----cCc--~~-c--'-----'---"---_[_____J
0.047 1.0 2.2 4.7 10.0 22 47 100 CT (nF)
Timing Resistance vs Frequency
l 1Ok t----t--l-'<-~__,,._,f.-"<----"1.-".+'.~cl-----l--_;
ii:
1k FREQ(Hz)
Primary Output Deadtime vs Frequency
160 140
10nF
v
:g 120
100
80 10k
470pF
100k FREQ(Hz)
_./
1M
Typical Dead Time (TD) Over Temperature
80 70 80 50 40 To(ps) 30
20 10 0
-75 -50 -25
IL
v /1
./
............
~
0
25 50 75 100 125
T("C)
Non-Overlap Time (TNo) Over Temperature
Out-
-SO%
-SO%
TNO
TNO
5-131
Forward Technique for Off-Line Voltage Mode Application CFF-;J:-
UC1824 UC2824 UC3824
Constant Volt-Second Clamp Circuit
The circuit shown here will achieve a constant volt-second product clamp over varying input voltages. The ramp generator components, RT and CR are chosen so that the ramp at Pin 9 crosses the 1V threshold at the same time the desired maximum volt-second product is reached. The delay through the functional nor block must be such that the ramp capacitor can be completely discharged during the minimum deadtime.
juc1s24
VIN
I I LIM
RR Shutdown
t-----19
Output Section
Simplified Schematic
Rise/Fall Time (CL=10nF)
-------~2IL(A)
l--"-+-"-+---1--.----h,......,0
15 I---+-.-+-"""'...-+--< -2
~ 101-----tl--+---t~H---I
~
5 1---1+--f---+-___,1'---<
100 200 300 400 500 Time(ns)
Rise/Fall Time (CL=1 nF)
-~-----~0.2
IL(A)
l--"'-+--'-+---1--.--1-r__,o
~ 101---+1--+---+--t-+---I
~
5 l---t+---+---+--tt---1
0 0 40 80 120 160 200
Time(ns)
Saturation Curves
3
2
~
5-132
0.5
1.0
1.5
lour (A)
Open Loop Laboratory Test Fixture
UC1824
Clock} RT Oscillator
UC1824 UC2824 UC3824
27k 22k
27k
10k~~-{)
3.3k
Ramp
:~: Out} ~~~r
INV INV
Solt Start
ILIM
Shutdown
-
_ _J
UDG-92036·1
This test fixture is useful for exerc1s1ng many of the As with any wideband circuit, careful grounding and byUC1824's functions and measuring their specifications. pass procedures should be followed. The use of a
ground plane is highly recommended.
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL Bl.VD. · MERRIMACK, NH 03054 TEL. (603) 424-2410 · FAX (603) 424-3460
5-133
n. n INTEGRATED
~CIRCUITS
-UNITRCDE
High Speed PWM Controller
UC1825 UC2825 UC3825
FEATURES Compatible with Voltage or Current Mode Topologies
Practical Operation Switching Frequencies to 1MHz
50ns Propagation Delay to Output
High Current Dual Totem Pole Outputs {1.5A Peak)
Wide Bandwidth Error Amplifier
Fully Latched Logic with Double Pulse Suppression
Pulse-by-Pulse Current Limiting
Soft Start I Max. Duty Cycle Control
Under-Voltage Lockout with Hysteresis
Low Start Up Current (1 .1 mA)
DESCRIPTION
The UC1825 family of PWM control ICs is optimized for high frequency switched mode power supply applications. Particular care was given to minimizing propagation delays through the comparators and logic circuitry while maximizing bandwidth and slew rate of the error amplifier. This controller is designed for use in either currentmode or voltage mode systems with the capability for input voltage feed-forward.
Protection circuitry includes a current limit comparator with a 1V threshold, a TTL compatible shutdown port, and a soft start pin which will double as a maximum duty cycle clamp. The logic is fully latched to provide jitter free operation and prohibit multiple pulses at an output. An under-voltage lockout section with BOOmV of hysteresis assures low start up current. During under-voltage lockout, the outputs are high impedance.
These devices feature totem pole outputs designed to source and sink high peak currents from capacitive loads, .such as the gate of a power MOSFET. The on state is designed as a high level.
Trimmed Bandgap Reference (5.1 V ± 1%)
BLOCK DIAGRAM
CT
Soft Start
Vee
Gnd 2/93
9µA
A B
G ~--a
I
8
REFl-<~-------------11 Gen
5-134
UOG-92030
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage (Pins 13, 15) ........................ 30V Output Current, Source or Sink (Pins 11, 14) DC ........................................... 0.5A Pulse (0.5ms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0A Analog Inputs (Pins 1, 2, 7) ............................... -0.3V to 7V (Pin 8, 9) .................................. -0.3V to 6V Clock Output Current (Pin 4) ....................... -5mA Error Amplifier Output Current (Pin 3) . . . . . . . . . . . . . . . . 5mA Soft Start Sink Current (Pin 8) . . . . . . . . . . . . . . . . . . . . . 20mA Oscillator Charging Current (Pin 5) .................. -5mA Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W Storage Temperature Range .............. -65'C to +150°C Lead Temperature (Soldering, 10 seconds) .......... 300'C Note 1: All voltages are with respect to GND (Pin 1O); all currents are positive into, negative out ofpart; pin numbers refer to DIL-16 package. Note 3: Consult Unitrode Integrated Circuit Databook for thermal /imitations and considerations of package.
SOIC-16 (Top View)
DW Package
CONNECTION DIAGRAMS
DIL-16 (Top View) J Or N Package
UC1825 UC2825 UC3825
PLCC-20 & LCC-20 (Top View) Q & L Packages
La 2 1 20 19
4
18~
5
17~
6
16~
7
15~
8
14~
9 10 11 12 13
PACKAGE PIN FUNCTION
FUNCTION
PIN
N..LC
1
INV
2
NI
3
EJ_AOut
4
Clock
5
N]C
6
RT
7
CT
8
Ram...Q.
9
Soft Start
10
Nj_C
11
ILIM/SD
12
Gnd
13
Out A
14
Pwr Gnd
15
NJ_C
16
Ve
17
OutB
18
Vee
19
VREF 5.1V
20
ELECTRICAL CHARACTERISTICS: Unless otherwise stated.these specifications apply for, RT= 3.65k, CT= 1nF, Vee
= 15V, -55'C<TA<125'C for the UC1825, -40'C<TA<85°C for the UC2825, and O'C<TA<70'C for the UC3825, TA=TJ.
PARAMETERS
TEST CONDITIONS
UC1825 UC2825
UC3825
MIN TYP MAX MIN TYP MAX UNITS
Reference Section
O~utVoltag_e
TJ = 25'C, lo= 1mA
v 5.05 5.10 5.15 5.00 5.10 5.20
Line R~ulation
10V <Vee< 30V
2
20
2
20 mV
Load Regulation Tem~rature Stabi!i!r Total Out_p_ut Variation*
1mA < lo < 1OmA TMIN <TA< TMAX Line, Load, Tem_£_erature
5
20
5
20 mV
0.2 0.4
0.2 0.4 mV/°C
5.00
5.20 4.95
5.25 v
O~ut Noise Voltag_e*
10Hz < f < 10kHz
50
50
E_V
Lor:!9_Term Stabil.!!r_
TJ = 125°C, 1OOOhrs.
5
25
5
25 mV
Short Circuit Current
VREF = OV
-15 -50 -100 -15 -50 -100 mA
Oscillator Section
Initial Accura~
TJ= 25°C
360 400 440 360 400 440 kHz
Voltag_e Stabil.!!r_
10V < Vee < 30V
0.2
2
0.2
2
%
Tem_£_erature Stabili!Y:_
TMIN <TA< TMAX
5
5
%
Total Variation*
Line, Temperature
340
460 340
460 kHz
5-135
ELECTRICAL CHARACTERISTICS (cont.)
UC1825 UC2825 UC3825
Unless otherwise stated,these specifications apply for, RT= 3.65k, CT= 1nF, Vee = 15V, -55°C<TA<125°C for the UC1825, -40°C<TA<85°C for the UC2825, and 0°C<TA<70°C for the UC3825, TA=TJ.
PARAMETERS
TEST CONDITIONS
Oeclllator Section~ontl_
Clock Out 'i!9_h
Clock Out Low
Ram_p_Peak*
Ram_p_Vall~ Ram_p_Vall~to Peak*
Error A~lflar Section
ll!Qllt Offset Volta_g_e
ll!Qllt Blas Current
I~ Offset Current O~n LoQE_Gain
1V<V0<4V
CMRR
1.5V < VeM < 5.5V
PSRR Out~ Sink Current
10V <Vee< 30V VPIN3=1V
Outj>Ut Source Current
VPIN3 = 4V
Output High Volta_g_e
IPIN 3 = -0.5mA
O~t Low Volt~e
IPIN3=1mA
Un_!!rGain Bandwidth*
Slew Rate*
PWM Com..e_arator Section
Pin 7 Bias Current
VPIN7 = OV
Duty C2i'!:le Ra1!9.e
Pin 3 Zero DC Threshold VPIN7 = OV
Del~toO~
Soft-Start Section
Cha!9_e Current
VPIN8 = 0.5V
Discha!9_e Current
VPIN8=1V
Current UmH I Shutdown Section
Pin 9 Bias Current
0 <VPIN9< 4V
Current Limit Threshold
Shutdown Threshold
Del~toO~ut
Out..e_ut Section
Output Low Level
lour =20mA
lour =200mA
Output High Level
lour= -20mA
lour = -200mA
Collector Leakage
Ve=30V
Rise/Fall Time*
CL= 1nF
Under-VoH119_e Lockout Section
Start Threshold
UVLO H~eresis
Supply Current Section
Start l.J!'_Current
Vee=8V
ICC
VPIN 1, VPIN 7, VPIN 9 = OV; VPIN 2 = 1V
* This parameter not 100% tested in production but guaranteed by design.
UC1825 UC2825 MIN TVP MAX
3.9 4.5 2.3 2.9
2.6 2.8 3.0 0.7 1.0 1.25 1.6 1.8 2.0
10
0.6
3
0.1
1
60
95
75
95
85 110
1
2.5
-0.5 -1.3
4.0 4.7 5.0
0
0.5 1.0
3
5.5
6
12
-1
-5
0
80
1.1 1.25
50 80
3
9
20
1
0.9 1.25
1.0 1.40 50
15 1.1 1.55 80
13.0 12.0
0.25 1.2 13.5 13.0 100 30
0.40 2.2
500 60
8.8 9.2 9.6 0.4 0.8 1.2
1.1 2.5 22 33
UC3825 MIN TVP MAX UNITS
3.9 4.5
v
2.3 2.9
v
2.6 2.8 3.0
v
0.7 1.0 1.25 v
1.6 1.8 2.0
v
15 mV
0.6
3
µA
0.1
1
µA
60
95
dB
75
95
dB
85 110
dB
1
2.5
mA
-0.5 -1.3
mA
4.0 4.7 5.0
v
0
0.5 1.0
v
3
5.5.
MHz
6
12
v~
-1
-5 mA
0
85
%
1.1 1.25
v
50 80 ns
3
9
20 ~
1
mA
10 ~
0.9 1.0 1.1
v
1.25 1.40 1.55 v
50
80
ns
0.25 0.40 v
1.2 2.2
v
13.0 13.5
v
12.0 13.0
v
10 500 µA
30
60
ns
8.8 9.2 9.6
v
0.4 0.8 1.2
v
1.1 2.5 mA 22 33 mA
5-136
Printed Circuit Board Layout Considerations
High speed circuits demand careful attention to layout and component placement. To assure proper performance of the UC1825 follow these rules: 1) Use a ground plane. 2) Damp or clamp parasitic inductive kick energy from the gate of driven MOSFETs. Do not allow the output pins to ring below ground. A series gate resistor of a shunt 1 Amp Schottky diode at the output pin will serve this purpose. 3)
UC1825 UC2825 UC3825
Bypass Vee, Ve, and VREF. Use 0.1 µF monolithic ceramic capacitors with low equivalent series inductance. Allow less than 1 cm of total lead length for each capacitor between the bypassed pin and the ground plane. 4) Treat the timing capacitor, Cr, like a bypass capacitor.
Error Amplifier Circuit
Open Loop Frequency Response
100
-20 I'-..
100 1K 10K 100K 1M 10M 100M
FREQ (Hz)
PWM Applications
/ ' l / I Conventional (Voltage Mode) UC18~ CT Oscillator
Unity Gain Slew Rate
lL (V)
4 3
>-V-<INIh·-,:--"--+--+---+--;.-~-+----+---+----<
2t-Hij_'-+-v_,~_ur-+--+-~·7\~li---\t---+
t-'I/
· ·lv-t--
1~~~~~~~~~~
0 0.2 0.4 0.6 0.8 1.0
TIME (µs)
Current-Mode
5-137
· A small filter may be required to suppress switch noise.
Oscillator Circuit
juc1s2s -- --
liming Resistance vs Frequency
w
~ 1 Ok f-----t---+-_.___,.___..+-"c--'I<-~-"<-~--+---<
~
1k
100
1k
10k
100k
FREQ(Hz)
1M
S nchronized 0 eration
UC1825 UC2825 UC3825
Deadtime vs CT (3k s RT s 1OOk)
,.
~
1m ~ 2.20 f-----j---+--+--+--~--+---1
0.47
~
. Y 0.22
0.10 r--l-:7""'-t--J---t--1----+--t----I
0.047 "=-~o----='co--~-~--=--~~ 0.047 1.0 22 4.7 10.0 22 47 100 Cr(nF)
Deadtime vs Frequency
:g 120 f----+-----+------+------1------1
~
L_ __J~4~70p~F~::::::::t:::::::::c::::__J
80
10k
100k
1M
FREQ(Hz)
Two Units in Close Proximity
I UC1825
Clock 4 1
I RT~
I
I CT 6
LM!_ster
Generalized Synchronization
I
I I UC1825
2N222
I
I I
n 43 o.1~'rt1.1p.~r+RT
i C~ 430.1r;
43 0.1f1Fl
=24
I I
~To 1
6 CT~
470 SOlathve·r·I 24
Slave
Local - Ramp
-::;::- Local Ramp
5-138
Forward Technique for Off-Line Voltage Mode Application
I RFFVIN~ ~ ~ UC1825 --------17 4
UC1825 UC2825 UC3825
Constant Volt-Second Clamp Circuit
The circuit shown here will achieve a constant volt-second product clamp over varying input voltages. The ramp generator components, RT and CR are chosen so that the ramp at Pin 9 crosses the 1V threshold at the same time the desired maximum volt-second product is reached. The delay through the functional nor block must be such that the ramp capacitor can be completely discharged during the minimum deadtime.
VIN
RR
IUC1825
Out ut Section
Simplified Schematic
Rise/Fall Time (CL=10nF)
~~-~~-~~2
IL(A)
t--~_.._-+---+--.:--t-ir--10
~ 10t---+<--t---t~.-+-----i
~
5 t---lt--t---+---1\----1
_J__.__, 0 ........'-L_..J.____l_
0 100 200 300 400 500
Tlme(ns)
Rise/Fall Time (CL=1 nF)
~~-~~-~~0.2
IL(A)
15 1---+--+---+-~---1-0.2
~ 10t---+t--t---t-;--t----1
~
51---lt--+-+---H---I
0 0 40 80 120 180 200
Tlme (ns)
Saturation Curves
3
2
~
5-139
0.5
1.0
1.5
lour(A)
Open Loop Laboratory Test Fixture
Clock} UC1825 RT Oeclllator
UC1825 UC2825 UC3825
27k 22k
27k
E/A Out}
Error
Non
Amp
INV
10k<-E- - -O -..----I
3.3k
UDG-82032·1
This test fixture is useful for exercising many of the As with any wideband circuit, careful grounding and byUC1825's functions and measuring their specifications. pass procedures should be followed. The use of a
ground plane is highly recommended.
Design Example: sow, 48V to 5V DC to DC Converter - 1.5MHz Clock Frequency
++-------------------------.
VIN 42-56V -~=.--~___,f--~~~~~~--~~~---+ VourSV
1-10A
4.3k
1=150pF
UNITRDDE INTEGRATED CIRCUITS 7 CONTINENTAL Bl.VD. · MERRIMACK, NH 03054 TEL (603) 424-2410 · FAX (803) 424-3460
5-140
UDG-92033-1
n n L::::_)
INT&lilAATED CIRCUITS
-UNITRDDE
Current Mode PWM Controller IC
UC1828 UC2828 UC3828
ADVANCED INFORMATION
FEATURES Wide Operating Range Programmable Triangle Wave Generator Low ISENSE Delay Low Start-up Current Built-in Programmable Blanking Latched Shutdown Pin Programmable Start-up Threshold with Default Setting Fully Synchronizing Oscillator Soft-Start·Capability Open-collector Totem Pole Output can Drive High-Side Switch
BLOCK DIAGRAM
DESCRIPTION The UC1828 family of PWM controller ICs builds on the features offered in the UC1842 family. This new family has improved speed and accuracy, added functionality, and lower power requirements.
The oscillator is programmed by the user's selection of external resistors and a capacitor. One resistor accurately sets the charge current in the capacitor, while the other accurately sets the discharge current. This allows highly accurate frequency and duty cycle programming.
The S/D Latch pin, when given a high positive input command, will latch the output off until reset by the Enable pin. The S/D Latch function is designed to operate with very low delay times.
The Enable pin, when given a high positive input command, will reset the flipflop set by the S/D Latch pin. If the Enable pin is connected directly to Vee, the device will default to the settings of the internal UVLO circuitry.
The S/S Cap pin is used for programming soft-start capability. The user simply applies a small capacitor to this pin to set the soft start function. Each time the device is forced into a current-fault situation, it will go through a full soft start cycle, thus preventing current runaway.
The Clk/Sync pin can be used to easily synchronize two UC1828 devices to the same frequency.
Vee
5V REF
Enable SID Latch
SIS Cap Comp
Feedback
VeOL
PWM Out
Cur Sense ClklSync Charge Disch
CT
5/93
5-141
Pwr Gnd
Gnd
UDG.fl208Q.1 UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. · MERRIMACK, NH 03054 TEL (603) 424-241 O · FAX (603)424-3480
n nINTEGRATED
~CIRCUITS
-UNITRODE
Precision Low Dropout Linear Controllers
(®)
UC1832/3 UC2832/3 UC3832/3
FEATURES Precision 1% Reference Over-Current Sense Threshold Accurate to 5% Programmable Duty-Ratio Over-Current Protection 4.5V to 36V Operation 1OOmA Output Drive, Source or Sink Under-Voltage Lockout
Additional Features of the UC1832 series:
Adjustable Current Limit to Current Sense Ratio Separate +VIN terminal Programmable Driver Current Limit Access to VREF and E/A(+) Logic-Level Disable Input
BLOCK DIAGRAMS
DESCRIPTION
The UC1832 and UC1833 series of precision linear regulators include all the control functions required in the design of very low dropout linear regulators. Additionally, they feature an innovative duty-ratio current limiting technique which provides peak load capability while limiting the average power dissipation of the external pass transistor during fault conditions. When the load current reaches an accurately programmed threshold, a gated-astable timer is enabled, which switches the regulator's pass device off and on at an externally programmable duty-ratio. During the on-time of the pass element, the output current is limited to a value slightly higher than the trip threshold of the duty-ratio timer. The constant-current-limit is programmable on the UCx832 to allow higher peak current during the on-time of the pass device. With duty-ratio control, high initial load demands and short circuit protection may both be accommodated without extra heat sinking or foldback current limiting. Additionally, if the timer pin is grounded, the duty-ratio timer is disabled, and the IC operates in constant-voltage/constant-current regulating mode.
These IC's include a 2 Volt (±1 %) reference, error amplifier, UVLO, and a high current driver that has both source and sink outputs, allowing the use of either NPN or PNP external pass transistors. Safe operation is assured by the inclusion of under-voltage lockout (UVLO) and thermal shutdown.
The UC1833 family includes the basic functions of this design in a low-cost, 8pin mini-dip package, while the UC1832 series provides added versatility with the availability of 14 pins. Packaging options include plastic (N suffix), or ceramic (J suffix). Specified operating temperature ranges are: commercial (0°C to 70°C), order UC3832/3 (Nor J); industrial (-25°C to 85°C), order UC2832/3 (N or J); and military (-55°C to 125°C), order UC1832/3J. Surface mount packaging is also available.
UCx832
UCx833
+2V REF
12/92
Comp/ Shutdown
5-142
Comp/ Shutdown
UDG·9204-0
ABSOLUTE MAXIMUM RATINGS
Supply Voltage +VIN ............................... 40V Driver Output Current (Sink or Source) . . . . . . . . . . . . . 450mA Driver Sink to Source Voltage ....................... 40V TAC Pin Voltage.......................... -0.3V to 3.2V Other Input Voltages ...................... -0.3V to +VIN Operating Junction Temperature (note 2) . . . --55°C to +150°C Storage Temperature. . . . . . . . . . . . . . . . . . . -65°C to +150°C Lead Temperature (Soldering, 10 Seconds) .......... 300°C
UC1832/3 UC2832/3 UC3832/3
Note 1: Unless otherwise indicated, voltages are referenced to ground and currents are positive into, negative out of, the specified terminals. Note 2: See Unitrode Integrated Circuits databook for information regarding thermal specifications and limitations of packages.
CONNECTION DIAGRAMS
UC1832 OIL-14 (Top View) J Or N Package
+VIN
Shu'W:'-E~ 2
+2V REF Gnd
Logic Disable
Limit 7
UC1833
OIL-8 (Top View)
J Or N Package
····og,,. . C/S(+) 1
B ense(-)
ShuCtdoomwpn/ 2
7 Timer RC
Gnd 3 Source 4
6 Sink 5 E/A(-)
SOIC-16 (Top View) OW Package
+VIN 1
Shu'f3g1:~ 2
EIA(+) 3 +2V REF 4
18 ~~~s8e(~) 5 i~~rs8e(~)
Timer RC
SOIC-16 (Top View) OW Package
IT C+/VSI(N+~) 1
--er
ShuCtodomwp~n[!2
NIC[!
N/C(i
Gnd@: NIC~
NtC(l
Source[!
~N/C
~Currant Sen1e(-)
~Timer AC ~NIC ~NIC
lmNIC
~Sink ~E/A(·)
LCC-20 & PLCC-20 L& Q Package (Top View)
3 2 1 20 19
18 17 16 15 14 9 10 11 12 13
PACKAGE PIN FUNCTION
FUNCTION
PIN
NC
1
2
3
4
5
6
7
Lo ic Disable
8
Limit
9
10
11
12
Sink
13
VADJ
14
NC
15-17
Timer RC
18
Current Sense -
19
Current Sense + 20
LCC-20 & PLCC-20 L&Q Package (Top View)
La =~ 2 1 2019
4
18
5
17
6
16
7
15
8
14
9 10 11 12 13
5-143
PACKAGE PIN FUNCTION
FUNCTION
PIN
+VIN & QLSJtl
1
Nie
2
t-ll:c
3
N/C
4
ComQ/.Shutdown
5
Gnd
6
~c
7
N/C
8
Nie
9
Source
10
NLC
11
i;LAB
12
N}C
13
~c
14
Sink
15
Timer RC
16
Current Sensei+l 17
~c
18-20
UC1832/3 UC2832/3 UC3832/3
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, specifications hold for TA = o·c to 10°c for the
UC3832/3, -25°C to 85°C for the UC2832/3, and -55°C to 125°C for the
UC1832/3, +VIN= 15V, Driver sink= +VIN, C/S(+) voltage= +VIN. TA=TJ.
PARAMETER Input Supply
Supply Current
Reference Section Output Voltage (Note 3)
Load R~ulationJ_UCx832 only}_ Line Regulation Under-Voltage Lockout Threshold Logic Disable Input (UCx832 only) Threshold Voltage Input Bias Current Current Sense Section Comparator Offset
Amplifier Offset (UCxB33 only) Amplifier Offset (UCx832 only)
Input Bias Current l~t Offset Current (UCx832 only) Am_ellfier CMRR (UCx832 only) Transconductance VAoj Input Current (UCx832 only) Timer Inactive Leakage Current Active Pullup Current Duty Ratio (note 4) Period (notes 4,5) Uee_er Trip Threshold~u) Lower Tr~Threshold_(\& Trip Threshold Ratio Error Amplifier Input Offset Voltage (UCx832 only) Input Bias Current Input Offset Current (UCx832 only) AVOL CMRR (UCx832 only) PSRRlUCx832 on!Y}_ Transconductance VOH VOL IOH
TEST CONDITIONS
+VIN=6V +VIN=36V Logic Disable = 2V (UCxB32 only)
TJ = 25°C, IDRIVER = 10mA overtemperature, IDRIVER = 10mA IOUT=0to10mA +VIN= 4.5 to 36V, IDRIVER = 10mA
Pin 6= OV
Over Tem_.E..erature
VADJ =Open VADJ= 1V VADJ = OV VcM =+VIN VcM =+VIN VcM = 4.1Vto +VIN+0.3V ICOMP = :t1 OOµA VADJ = OV
C/S(+) = C/S(-) = +V1N; TAC pin= 2V C/S(+) =+VIN, C/S(-) =+VIN - 0.4V; TAC pin= OV ontime/period, RT = 200k, CT = .27µF ontime + offtime, RT = 200k, CT= .27µF
VuNI
VCM = VCOMP = 2V VCM = VCOMP = 2V VcM = VCOMP = 2V VcOMP = 1V to 13V VCM = OV to +VIN - 3V VcM = 2V, +VIN= 4.5 to 36V ICOMP = :t10µA ICOMP = 0, Volts below +VIN (COMP =0 VCOMP=2V
MIN TYP MAX UNITS
6.5 10 mA
9.5 15 mA
3.3
mA
1.98 2.00 2.02
v
v 1.96 2.00 2.04
-10 -5.0
mV
0.033 0.5 3.6 4.5
mVN
v
1.3 1.4 1.5
v
-5.0 -1.0
µA
95 100 105 mV
93 100 107 mV
110 135 170 mV
110 135 170 mV
180 235 290 mV
250 305 360 mV
65 100 135 µA
-10
10 µA
BO
dB
65
ms
-10
-1
µA
0.25 1.0 µA
-345 -270 -175 µA
4.8
%
36
ms
1.8
v
0.9
v
2.0
VN
-8.0
8.0 mV
-4.5 -1.1
µA
-1.5
1.5 µA
50
70
dB
60
BO
dB
90
dB
4.3
ms
.95 1.3
v
.45 0.7
v
-700 -500 -100 µA
5-144
ELECTRICAL CHARACTERISTICS (cont.)
UC1832/3 UC2832/3 UC3832/3
Unless otherwise stated, specifications hold tor TA= o·c to 70°C for the UC3832/3, -25°C to 85°C for the UC2832/3, and -55°C to 125°C for the uc1832/3, +V1N = 15V, Driver sink= +VIN, C/S(+) voltage= +VIN. TA=TJ.
PARAMETER
TEST CONDITIONS
MIN TVP MAX UNITS
Error Ampllfler (cont)
IOL
VCOMP = 2V, C/S(-) =+VIN
100 500 700 µA
VCOMP = 2V, C/S(-) =+VIN - 0.4V
2
6
mA
Driver
Maximum Curren1
Driver Limit & Source pins common; TJ = 25°C
200 300 400 mA
Over Temperature
100 300 450 mA
Limiting Voltage
Driver Limit to Source voltage at current limit, lsouRcE = -10mA; TJ = 25°C_(Note ~-
.72
v
Internal Curren1 Sense Resistance TJ = 25°C (Note 6)
2.4
Q
Pull-Up Current at Driver Sink
Compensation/Shutdown= 0.4V; Driver Sink= +VIN - 1V -800 -300 -100 µA
Compensation/Shutdown= 0.4V, +VIN= 36V; Driver
Sink =35V
-1000 -300 -75 mA
Pull-Down Current at Driver Source Compensation/Shutdown = 0.4V; Driver Source = 1V
Saturation Voltage Sink to Source Driver Source = OV; Driver Current = 1OOmA
150 300 700 µA
1.5
v
Maximum Source Voltage
Driver Sink= +VIN, Driver Current= 1OOmA Volts below +VIN
3.0
v
UVLO Sink Leakage Maximum Reverse Source Voltage Thermal Shutdown
+VIN= C/S(+) = C/S(-) = 2.5V, Driver Sink= 15V, Driver
Source= OV, TA= 25°C Compensation/Shutdown = OV; lsouRCE = 1OOµA,
. -·I------
+VIN= 3V
___ .__1~ -
__, , I- f'A
1.6
v
160
·c
Note 3: On the UCx833 this voltage is defined as the regulating level at the error amplifier inverting input, with the error amplifier
driving VSOURCE to 2\f. Note 4: These parameters are first-order supply-independent, however both may vaty with supply for+ \!IN less than about 4 V. This
supply variation will cause a slight change in the timer period and duty cycle, although a high off-time/on-time ratio will be main-
tained.
Note 5: With recommended RT value of 200k, ToFF- RT Cr* /n{Vu/VI) ±10%. Note 6: The internal current limiting voltage has a temperature dependence of approximately-2.0mV!°C, or -2800ppm/°C. The internal 2.4 Q sense resistor has a temperature dependance of approximately +1500ppm/°C.
APPLICATION AND OPERATION INFORMATION NPN Pass (Local 100mA Regulator) (UCx833)
+15V
1.0
- - - - - - - - - · V1O2UVT
22
l 0.033
5-145
UDG-92041
APPLICATION AND OPERATION INFORMATION cont.
PNP Pass (Low Drop-Out Regulator) (UCx833)
+15V 0.1
,.-------------,.+ VOUT 12V
UC1832/3 UC2832/3 UC3832/3
I
I
I , cs
I 100mV
Comp
_uc_._e_33 _ _ --"~- -~"'--
10k 22
NPN Pass (Medium Power, Low Drop-Out Regulator) (UCx832)
0.02
12V <>-r---+---'1-----.---.
HI VIN (·U11)
,.----------OVOUT 5V
1N4148
10µF
UDG-92042
UDG-92043
Estimating Maximum Load Capacitance For any power supply, the rate at which the total output capacitance can be charged depends on the maximum output current available and on the nature of the load. For a constant-current current-limited power supply, the output will come up if the load asks for less than the maximum available short-circuit limit current.
To guarantee recovery of a duty-ratio current-limited power supply from a short-circuited load condition, there is a maximum total output capacitance which can be charged for a given unit ON time. The design value of ON time can be adjusted by changing the timing capacitor.
Nominally, TON =0.693 x 1Ok x CT.
Typically, the IC regulates output current to a maximum of
= IMAX K x ITH, where ITH is the timer trip-point current,
and
K = Current Sense AmplifierOffset Voltage
100mA
..1.35 for UCx833, and is variable from 1.35 to 3.05 with VADJ for the UCx832.
For a worst-case constant-current load of value just less than ITH, CMAX can be estimated from:
TON CMAX = ((K-1 )/TH) ( Vou?·
where Vour is the nominal regulator output voltage.
For a resistive load of value RL, the value of CMAX can be estimated from:
CMAX= ToN. _ _ _ _ _ _ _ __
RL In [(1- Vour ) _11
K· lrH· RL
5-146
APPLICATION AND OPERATION INFORMATION (cont.) Current Sense Am lifier Offset Volta vs VADJ
320
~
300
1--1
::::sl
280
~
f :' 260
i 200 8 180
180 140
i........
~ ~
~ ~
_, ~ r---1
120
o.oo 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50
VADJ (Pin 11 - UCx832 only) - V
UCx832/33 limer Function
Internal 2.7V
10
m
omp
UCx832/33 Current Sense In
C/S(+)
UC1832/3 UC2832/3 UC3832/3
C/S(·)
TRC Pin
1.8V/0.95V
- To Timer To E/A Input Override
·Note: Vos-35mV for UCx833 Vos=205 to 35mV for UCx832
Load current, timing capacitor voltage, and output voltage of the regulator under fault conditions.
Output VSENSE· ,r--O-v-e-rl-oa-d--,,
Current 135mV~
roomv~
' '
lo (nom)
CT Voltage
Vo (nom) 1----+-l Output Ro1 lcL--+~---------+ Voltage '------'-------I.-'\.--'-..._,""...__ _
5-147
APPLICATION AND OPERATION INFORMATION (cont.)
UC1832/3 UC2832/3 UC3832/3
UCX832 Error Ampllfler
AVOL vs Frequency and CC
Frequency - (Hz)
UCX832 Current Sense Ampllfler
AVOL vs Frequency and CC
' 100
80 r-
60 40 20 0 -20
11 ll~Jll
F
N
II
~ F
1:::.-1
I
~
-40 0 0.001 0.01 0.1 1 10 100 1000 10000
Frequency - (Hz)
UCX832 Error Amplifier
Transconductance and Phase vs Frequency
10 Gm(mmho)
Phase Shift (degrees)0
T~uctance
·~··········· .... -50
~'DJ
0.1 ~~~~~~-~~~~~-~~~~"-Y-200
10
100
1000
10000
Frequency - (kHz)
UCX832 Current Sense Amplifier
Transconductance and Phase vs Frequency
100 Gmjmmho)_
Phase Shift (o rees 0
.......... ····eininscondu.ct.~....b>J...... z!haseSbllt ..... _50
µi -+-I .............................................~............................. -100
~
·············~·····
........ -150
10 +---~----L-LJ...'-LJ.j-J~'~..LJ..Ll--4--~~L..L.Li-Lj.200
10
100
1000
10000
Frequency - (kHz)
UNITAODE INTEGRATED CIRCUITS 7 CONTINENTAL Bl.VO. · MERRIMACK, NH 03054 TEL. (603) 424-2410 · FAX (603) 424-3480
5-148
n n LL=:'.j
INTEGIRATED CIRCUITS
-UNITRODE
High Efficiency Linear Regulator
(®)
UC1834 UC2834 UC3834
FEATURES Minimum VIN - VOUT Less Than 0.5V At 5A Load With External Pass Device
Equally Usable For Either Positive or Negative Regulator Design
Adjustable Low Threshold Current Sense Amplifier
Under And Over-Voltage Fault Alert With Programmable Delay
Over-Voltage Fault Latch With 1OOmA Crowbar Drive Output
DESCRIPTION
The UC1834 family of integrated circuits is optimized for the design of low input-output differential linear regulators. A high gain amplifier and 200mA sink or source drive outputs facilitate high output current designs which use an external pass device. With both positive and negative precision references, either polarity of regulator can be implemented. A current sense amplifier with a low, adjustable, threshold can be used to sense and limit currents in either the positive or negative supply lines.
In addition, this series of parts has a fault monitoring circuit which senses both under and over-voltage fa·Jlt conditions. After a user defined delay for transient rejection, this circuitry provides a fault alert output for either fault condition. In the over-voltage case, a 1OOmA crowbar output is activated. An over-voltage latch will maintain the crowbar output and can be used to shutdown the driver outputs. System control to the device can be accommodated at a single input which will act as both a supply reset and remote shutdown terminal. These die are protected against excessive power dissipation by an internal thermal shutdown function.
BLOCK DIAGRAM
DRIVER SINK
+1.5V REFERENCE
.____ _._41 CROWBAR GATE
'-----<~------11151 O.V. LATCH & RESET
------+-+------------11141 COMPENSATION/SHUTDOWN
SENSE+ 7 ,___ _,_ THRESHOLD 141 - - - - - - t
ADJ.
, - - - - - - - 1 1 FAULT ALERT
6/93 5-149
UC1834 UC2834 UC3834
ABSOLUTE MAXIMUM RATINGS (Note 1)
Input Supply Voltage, V1N + ......................... 40V Driver Current. . . . . . . . . . . . . . . . . . . · . . . . . . . . . . . . . 400mA Driver Source to Sink Voltage ....................... 40V Crowbar Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -200mA +1.5V Reference Output Current . . . . . . . . . . . . . . . . . . -1 OmA Fault Alert Voltage ................................ 40V Fault Alert Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15mA Error Amplifier Inputs ....................... -0.5V to 35V Current Sense Inputs ....................... -0.5V to 40V O.V. Latch Output Voltage ................... -0.5V to 40V O.V. Latch Output Current . . . . . . . . . . . . . . . . . . . . . . . . 15mA
Power Dissipation at TA= 25°C . . . . . . . . . . . . . . . . . . 1OOOmW Power Dissipation at Tc= 25°C.................· 2000mW Operating Junction Temperature ........... -55°C to +150°C Storage Temperature .................... -65°C to +150°C Lead Temperature (soldering, 10 seconds) ........... 300°C Note 1: Voltages are reference to VtN-, Pin 5.
Currents are positive into, negative out of the specified terminals. Consult Packaging section ofDatabook for thermal limitations and considerations ofpackage.
CONNECTION DIAGRAMS
DIL-16, SOIC-16 (TOP VIEW) J or N Package, OW Package
VIN+ -2.0V Rel.
+1.5V Rel. Threshold
Adj. VIN-
Sense-
Sense+
N.lnv.lnput
Crowbar Gate O.V. Latch Output/Reset ComP,ensatlon/ Shutdown Driver Source Driver Sink
Fault Delay Fault Alert
Inv. Input
PLCC-20, LCC-20 (TOP VIEW) Q, L Packages
L 3 2 1 2019
4
18
5
17
6
16
7
15
8
14
9 10 11 12 13
PACKAGE PIN FUNCTION
FUNCTION
PIN
N/C
1
VIN+
2
-2.0VREF
3
+1.5V REF
4
Threshold A«lliJst
5
N/C
6
VIN-
7
Sense-
8
Sense+
9
N.lnv.11!.E>_ut
10
N/C
11
lnv.11'!1?._ut
12
Fault Alert
13
Fault Del~
14
Driver Sink
15
N/C
16
Driver Source
17
Compensation/ Shutdown 18
O.V. Latch Ou.!Q_ut/Reset 19
Crowbar Gate
20
5-150
UC1834 UC2834 UC3834
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA=-55°C to +125°C for the UC1834, -40°C to +85°C for the UC2834, and 0°c to +70°C for the UC3834. VIN= 15V, VIN= OV, TA= TJ.
PARAMETER
TEST CONDITIONS
UC1834 UC2834
UC3834
UNITS
MIN TYP MAX MIN TYP MAX
Tum-on Characteristics
Standl:!l_S~Current
+1.5 VoH Reference
Output Voltage
TJ = 25°C
5.5 7
5.5 10 mA
v 1.485 1.5 1.515 1.47 1.5 1.53
TJ(MlfllJ_ s TJ s TJ(MAX)
1.47
1.53 1.455
1.545
Line R~ulation
VIN+ = 5 to 35V
1
10
1
15 mV
Load R~ulation
IOUT "' 0 to 2mA
1
10
1
15 mV
·2.0 Volt Reference~ote ~
Output Voltage (Referenced to VIN+)
TJ= 25°C TJ(MIN) "TJ" TJ(MAX)
2.04 -2 1.96 2.06 -2 1.94 v
2.06
1.94 2.08
1.92
Line R~ulation
VIN+ = 5 to 35V
1.5 15
1.5 20 mV
O~ut lm~dance
2.3
2.3
kQ
Error Am~lfler Section
l'!E_ut Offset Volt~e
VCM= 1.5V
1
6
1
10 mV
l'!E_Ut Bias Current
VCM= 1.5V
-1
-4
-1
-8 µA
ln_e_ut Offset Current
VCM= 1.5V
Small Signal Open Loop Gain Output @ Pin 14, Pin 12 =VIN+ Pin 13, 20Q to VIN-
0.1
1
0.1
2 --j -~-
50 65
50 65
dB
CMRR
VcM = 0.5 to 33V, V1N+ = 35V
60 80
60 80
dB
PSRR
VIN+ = 5-35V, VcM = 1.5V
70 100
70 100
dB
Driver Section
Maximum Ou.!E_ut Current Saturation Volt~e
IOUT = 100mA
200 350
200 350
mA
0.5 1.2
0.5 1.5 v
Ol!!e_ut Leak~e Current
Shutdown Input Voltage at Pin 14
Pin 12 = 35V, Pin 13 =VIN-, Pin 14 =VIN-
0.1
IOUT = 1OOµA, Pin 13 =VIN-, Pin 12 =VIN+ 0.4 1
50
0.1
0.4 1
50 ~
v
Shutdown Input Current at Pin 14 Thermal ShutdownlNote ~
Pin 14 =VIN-, Pin 12 =VIN+ IOUT = 1OOµA, Pin 13 = VIN-
-100 -150 165
-100 -150 µA
165
oc
Fault Am_e!ifier Section
Under- and Over-Voltage Fault Threshold
VCM = 1.5V, @ E/A Inputs
120 150 180 110 150 190 mV
Common Mode Sensiti'®'._ VIN+= 35V, VcM = 1.5 to 33V
-0.4 -0.8
-0.4 -1.0 %/v
S~Sensiti'®'._
VcM = 1.5V, VIN+ = 5 to 35V
-0.5 -1.0
-0.5 -1.2 %N
Fault Del~
30 45 60 30 45 60 msll!:!'
Fault Alert Outi>_ut Current Fault Alert Saturation Voltage IOUT = 1mA
2
5
2
5
mA
0.2 0.5
0.2 0.5 v
O.V. Latch 01Jtput Current O.V. Latch Saturation Volt~e IOUT = 1mA
O.V. Latch Output Reset
Vol~e
2
4
2
4
mA
1.0 1.3
1.0 1.3 v
0.3 0.4 0.6 0.3 0.4 0.6
v
Crowbar Gate Current
-100 -175
-100 -175
mA
Crowbar Gate Leakage
VIN+= 35V, Pin 16 =VIN-
-0.5 -50
-0.5 -50 µA
Current
Note 2: When using both the 1.5V and -2.0V references the current out of ptn 3 should be balanced by an eqwvalent current mto
Pin 2. The -2.0V output will change -2.3mV per µA of imbalance.
Note 3: Thermal shutdown turns off the driver. If Pin 15 (0. V. Latch Output) is tied to Pin 14 (Compensation/Shutdown) the 0. V. Latch will be reset.
5-151
UC1834 UC2834 UC3834
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA=-55°C to +125°C for the UC1834, -40°C to +85°C for the UC2834, and 0°C to +70°C for the UC3834. VIN· 15V, VIN= OV. TA= TJ
PARAMETER
TEST CONDITIONS
current Senae Am_Rllfler Section
Threshold Voltage
Pin 4 Opel!...VcM ·VIN+ or V1N-
= Pin 4 ... 0.5V V...ma_ VIN+ or VIN-
= = Threshold Sucolv Sensltlvltv Pin 4 Coen VcM V1N- V1N+ 5 to 35V
Adj, l!J2_ut Current
Pln4=0.5V
Sense Input Blas Current VCM·VIN+
VCM=VIN·
UC1834 UC2834
UC3834
UNITS
MIN TYP MAX MIN TYP MAXl
130 150 170 120 150 180 mV
40 50 60 30 50 70
-0.1 -0.3
-0.1 -0:5 %N
-2 -10
-2 -10 uA
100 200
100 200 µA
-100 -200
-100 -200
current Sense Threshold Adjustment
Current Umiting Knee Characteristics
.5 1.0 1.5 > 1.5V Or Open
Voltage At Threshold Adjust Pin (P"n 4) - (V)
! i 200~-~-~~--~ 120 1----+---t----+-----fi
m>i
c j~ 80
1140
t-------+--1~
I i o .-=----'---L---.---' -10 .-7.5 -5.0 -2.5 Currant Sense Ttl'eshald
Differential Voltage at Current Sense Inputs - mV (reference to sense - Input)
Error Amplifier Gain and Phase Frequency Response
I 0 l -90 · ' 0 0 r---i-----t---t--+~--i 180 _.
-20 _ ~-~~ __.._ _..._ __. 10 100 1K 10K 100K 1M Frequency - (Hz)
cur.rent Sense Amplifier Gain and Phase Frequency Response
0 l = 90
'
- 20 r---t-----tt-----tt-----t~---t 180 ....!
100 1< 10K 100K 1M Frequency - (Hz)
5-152
APPLICATION INFORMATION
Foldback Current Umlting R2
....!:._ RSENSE
Pass Device
R1
R1
UC1834 UC2834 UC3834
Current Threshold
Ad/ust Vo tage (VAOJ)
ILMAX (Typical)
0.1(VAOJ) (VIN+- VOUT) R1 RSENSE (R1 + R2) RSENSE
s: For: R1 + R2 >> RSENSE, VADJ 1.5V,
R1 · R1
Both the current sense and error amplifiers on the UC1834 are transconduelance type amplifiers. As a result, their voltage gain is a direct function of the load impedance at their shared output pin, Pin 14. Their small signal voltage gain as a function of load and frequency is nominally given by;
ZL (1)
a (1)
Av &A = 7000 and Av c. s.1A = 700
for: f s 500kHz and /a(f)/ s 1 MQ
Where: Av=Small Signal \bltage Gain to pin 14. ZL(f) = Load Impedance at Pin 14.
The UC1834 fault delay circuitry prevents the fal.dt outputs
from responding to transient fault conditions. The delay reset latch insures that the full, user defined, delay passes before an
over-voltage fault response occurs. This prevents unnecessary
cro.Nbar, or latched-off conditions, from occurring follONing sharp under-voltage to over-voltage transients.
The cro.vbar output on the UC1834 is activated following a sustained over-voltage condition. The crowbar output remains high as long as the fault condition persists, or, as long as the over-voltage latch is set. The latch is set with an over-voltage fault if the voltage at Pin 15 is above the latch reset ttveshold, typically 0.4\1. When the latch is set, its Q- oulpti will pUI Pin 15 low through a series diode. As long as a nominal pull-up load exisls, the series diode prevents Q- from pulfing Pin 15 below the reset threshold. However, Pin 15 is pulled low enough to disable the driver outputs if Pins 15 and 14 are tied together. With Pin 15 and 14 common, the reguator will latch off in response to an over-voltage fault. ff the fault condition is deared and Pins 14 and 15 are momentarily pulled below the latch reset threshold, the driver outputs are re-enabled.
Setting the Threshold Adjust Voltage (VADJ)
VIN+
+ 2.0V R3*
+
R1 1.5V
R2
VIN-
VADJ - 1.5V · R1R! R2 *To Maintain -2.0V Output
R3 · t2S.0 · (R1 + R2)
5-153
TYPICAL APPLICATIONS
5-1 OAmp Positive Regulator
UC1834
Fault Logic
UC1834 UC2834 UC3834
VouT
Thermal Shutdown
Shutdown/Comp Fault
Remote Shutdown/ Reset
Ground
5-10 Amp Negative Regulator
UC1834 Fault Logic
Thermal Shutdown
Foldback Current Limiting
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. · MERRIMACK, NH 03054
TEL (603) 424-2410 ·FAX (603) 424-3480
5-154
Remote Shutdown/ Reset
Faull Monitoring Vour
n nINTEGRATED
~CIRCUITS
-UNITRCDE
High Efficiency Regulator Controller
UC1835 UC1836 UC2835 UC2836 UC3835 UC3836
FEATURES Complete Control for a High Current, Low Dropout, Linear Regulator
Fixed 5V or Adjustable Output Voltage
Accurate 2.5A Current Limiting with Fold back
Internal Current Sense Resistor
Remote Sense for Improved Load Regulation
External Shutdown
Under-Voltage Lockout and Reverse Voltage Protection
Thermal Shutdown Protection
8 Pin Mini-Dip Package (Surface Mount also Available}
DESCRIPTION
The UC1835/6 families of linear controllers are optimized for the design of low cost, low dropout, linear regulators. Using an external pass element, dropout voltages of less than 0.5V are readily obtained. These devices contain a high gain error amplifier, a 250mA output driver, and a precision reference. In addition, current sense with fOldback provides for a 2.5A peak output current dropping to less than 0.5A at short circuit.
These devices are available in fixed, 5V, (UC1835), or adjustable, (UC1836}, versions. In the fixed 5 volt version, the only external parts required are an external pass element, an output capacitor, and a compensation capacitor. On the adjustable version the output voltage can be set anywhere from 2.5V to 35V with two external resistors.
Additional features of these devices include under-voltage lockout for predictable start-up, thermal shutdown and short circuit current limiting to protect the driver device. On the fixed voltage version, a reverse voltage comparator minimizes reverse load current in the event of a negative input to output differential.
BLOCK DIAGRAM
Sense Resistor
Out
40mn Sense Resistor
Driver Sink
6
+VIN
Reverse Voltage Comparator (UC1835 Family Only)
1oomv-12mv
2k
100'1
+VIN 1
VouT Sense 5 (UC1635 Family)
20k (UC1835 Family Only)
20k (UC1835 Family Only)
Note: Pin numbers refer to 8-Pin DIL Package
6/93
5-155
ABSOLUTE MAXIMUM RATINGS (Note 1)
Input Supply Voltage (+VIN} ................ -1.0V to+ 40V Driver Output Current (Sink or Source) ............. 600mA Driver Source to Sink Voltage ..................... + 40V Maximum Current Through Sense Resistor.............. 4A Vour Sense Input Voltage .................. -.3V to+ 40V Power Dissipation at TA= 25°C (Note 2) ........... 1000mW Power Dissipation at Tc= 25°C (Note 2) ........... 2000mW
CONNECTION DIAGRAMS
DIL-8, SOIC-8 (TOP VIEW)
N or J Package, D Package
+VIN
comp~~~fJ~~~
Ground
Sense Resistor Out VouT Sense
SOIC-16 (TOP VIEW) DW Package
N/C 1
+VIN 3
Compensation/ Shutdown N/C ·
Resistor Out
UC1835 UC1836 UC2835 UC2836 UC3835 UC3836
Operating Junction Temperature ........... -55°C to +150~C Storage Temperature .................... -65°C to +150°C Lead Temperature (Soldering, 1OSeconds) .......... 300°C Note 1: Voltages are referenced to ground, (Pin 3). Currents are
positive into, negative out of, the specified terminals. Consult Packaging Section of Databook for thermal considerations and limitations ofpackages.
PLCC-20, LCC-20 (TOPVIEW) Q, L Packages
L3 2 1 2019
~ 4
18
j 5
17
~ 6
16
p
15
8
14
9 10 11 12 13
PACKAGE PIN FUNCTION
FUNCTION
PIN
N/C
1
+VIN
2
+VIN
3
N/C
4
Compensation/
5
Shutdown
N/C
6
Ground
7
N/C
8
N/C
9
Driver Source
10
N/C
11
VourSense
12
N/C
13
N/C
14
Driver Sink
15
N/C
16
Current LimitJ:l
17
N/C
18
Sense Resistor Out 19
Sense Resistor Out 20
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, specifications hold for TA= 0°C to+ 70°C for the
UC3835/6, -25°C to + 85°C for the UC2835/6, and -55°C to +125°C for the UC1835/6, +VIN= 6V, Driver Source= OV, Driver Sink= 5V, TA= TJ.
PARAMETER
TEST CONDITIONS
ln~utS~
Supply Current
+VIN= 6V
+VIN= 40V
UVLO Threshold
+VIN Low to Hjg!l, VOUT Sense = OV
Threshold ~teresis
Reverse Current
+VIN= -1.0V, Driver Sink O__e_en
Reg_ulatln_g_Volteg_e and Error Am_.2!1flerJ_UC1835 Fam!!Y._Onhl_
Regulating Level at Vour Sense (VREG)
Driver Current = 1OmA, TJ = 25°C
Over Tem~erature
Line R~ulation
+VIN= 5.2V + 35V
Load R~ulation
Driver Current = 0 to 250mA
Bias Current at Vour Sense
VOUT Sense = 5.0V
Error Am_!) Transconductance
± 1OOJ!:.A at Compensation/Shutdown Pin
Maximum Compensation Out~t Current
Sink or Source, Driver Source O~n
MIN. TYP. MAX. UNITS
2.75 4.0 mA
3.75 6.0 mA
v 3.9 4.4 4.9 v 0.1 0.35
6.0 20 mA
v 4.94 5.0 5.06
4.9
5.1 v
15 40 mV
6.0 25 mV
75 125 210 -~
0.8 1.3 2.0 ms
90 200 260 µA
5-156
UC1835 UC1836 UC2835 UC2836 UC3835 UC3836 ELECTRICAL CHARACTERISTICS: Unless otherwise stated, specifications hold for TA= o·c to+ 10°c for the
UC3835/6, -25°C to + 85°C for the UC2835/6, and -55°C to +125°C for the UC1835/6, +VIN= 6V, Driver Source= OV, Driver Sink= 5V, TA= TJ.
PARAMETER
TEST CONDITIONS
R~ulatlng Volt1!9.8 and Error Am_2!1fler(UC1836 Fami!Y_ Only}
Regulating Level at VouT Sense (VREG)
Driver Current= 1OmA TJ = 25°C
Over Tem_E_erature
Line Regulation
+VIN= 5.2Vto35V
Load R~ulation
Driver Current= 0 to 250mA
Bias Current at VouT Sense
VouT Sense =2.5V
Error Am_E_Transconductance
±100µA at Com_E_ensation/Shutdown Pin
Maximum Com~nsation OtJ!E.ut Current
Sink or Source, Driver Source ~
Driver
MIN. TYP. MAX. UNITS
v 2.47 2.5 2.53
2.45
2.55 v
6.0 20 mV
3.0 15 mV
-1.0 -0.2
~
0.8 1.3 2.0 mS
90 200 260 µA
Maximum Current Saturation Voltl!S_e Pull-U_E_Current at Driver Sink Driver Sink Leakage
Thermal Shutdown Foldback Current Limit
Current Limit Levels at Sense Resistor Out
Driver Current= 250mA Driver Sink Com_E_ensation/Shutdown=0.45V In UVLO In Reverse Voltl!S_e_lUC1835 Fami!Y_On.!l:)_
VOUT Sense =l0.9!!)__VREG
VOUT Sense =j9.fil_VREG
250 500
mA
2.0 2.8
v
140 250 300 ~
10 ~
10
µA
165
·c
2.2 2.5 2.8
A
1.3 1.5 1.7
A
Current Limit Amp Tansconductance
VOUT Sense = OV
±1 OOµA at Compensation/Shutdown,
VOUT Sense =lO.!l)_ VREG
0.25 0.4 0.55 A
12
24
42
mS
Limiting Voltage at Current Limit(-)
lNote~
VOUT Sense = (0.9) VREG Volts Below +VIN, TJ = 25°C
80 100 140 mV
Sense Resistor Value (Note 3)
VouT Sense = (0.9) VREG,
40
mQ
..
. . IOUT = IA, TJ = 25°C
Note 2: This voltage has a pos1t1ve temperature coeff1c1ent of approximately 3500ppm/°C.
Note 3: This resistance has a positive temperature coefficient of approximately 3500ppm/°C.
The total resistance from Pin 1 to Pin 8 will include an additional 60 to 100mQ ofpackage resistance.
APPLICATION AND OPERATION INFORMATION
UC 1835- Typical configurations for a 2A, Low Dropout SV Regulator
PASS DEVICE (NOTE 4)
5V (0 TO 1)
UC1836-Typical Configuration for a 2A, Low Dropout Adjustable Regulator
PASS DEVICE (NOTE 4) Vour(O TO 2A)
VOUT · 2.5 (1+ ~)
-------,
UC1836
I
I I
Note 4: Suggested Pass devices are TIP 328. (Dropout Voltage :s:O. 7511) or; D45H, (Dropout Voltage :s:0.5V), or equivalents. 5-157
APPLICATION AND OPERATION INFORMATION (cont.)
UC1835/6 Foldback Current Limiting
v J
~
y _Lj y
t ~
100%
80% ~
~
60% 'lil
i40% .,.
20%
o.5 to t5 2.0 2.5 3.o Output ClJ'rent Through RSENSE - (A)
UC1835 UC1836 UC2835 UC2836 UC3835 UC3836
UC3835/36 TYPICAL APPLICATIONS
Low Current Application using the UC3836 internal drive transistor
+VIN
R1
+VOUT
-VIN
Typical Output Current vs VIN and Vour of the UC3836 internal drive transistor for PDISS = 5.5W (approx.)
I VIN
Volts 5 9 12 15 18 24
2_ 1501-tiO_ 40 _30_ 20 12
VOUT 5 9
I105 55 35 25 15 130 60 35 20
12
120 55 25
t5 ~urrent In mA 110 30
High Current Application using drive transistor 02 to increase 01 base drive
and reduce UC3836 power dissipation
+VIN
R1
Parallel Pass Transistors can be added for high current or high power dissipation applications
To 02 Emitter
+VOUT
-VIN
EQUATIONS: R1 =0.100V/IOUT(MAX) R2 = (Vour - 2.5V/1 mA) Ra =((VIN - VBE - VSAT)*BETA(min))/IOUT (max) UNITRODE INTEGRATEO CIRCUITS 7CONTINENTAL BLVD. · MERRIMACK, NH 03054
TEL (603) 424-2410 · FAX 603-424-3460
5-158
n n L=::'.J INTEGRATED CIRCUITS
-UNITROOE
Magnetic Amplifier Controller
UC1838A UC2838A UC3838A
FEATURES Independent 1% Reference
Two Uncommitted, Identical Operational Amplifiers
1OOmA Reset Current Source with -120V Capability
5V to 40V Analog Operation
5W DIL Package
DESCRIPTION
The UC1838A family of magnetic amplifier controllers contains the circuitry to generate and amplify a low-level analog error signal along with a high voltage-compliant current source. This source will provide the reset current necessary to enable a magnetic amplifier to regulate and control a power supply output in the range of 2A to 20A.
By controlling the reset current to a magnetic amplifier, this device will define the amount of volt-seconds the magnetic amplifier will block before switching to the conducting state. Magnetic amplifiers are ideal for post-regulators for multiple-output power supplies where each output can be independently controlled with efficiencies up to 99%. With a square or pulse-width-modulated input voltage, a magnetic amplifier will block a portion of this input waveform, allowing just enough to pass to provide a regulated output. With the UC1838A, only the magnetic amplifier coil, three diodes, and an output L-C filter are necessary to implement a complete closed-loop regulator.
The UC1838A contains a precision 2.5V reference, two uncommitted high-gain op amps and a high-gain PNP-equivalent current source which can deliver up to 1OOmA of magnetic amplifier reset current and with -120 volt capability.
These devices are available in a plastic "bat-wing" DIP for operation over a -20°C to +85°C temperature range and, with reduced power, in a hermetically sealed cerdip for -55°C to +125°C operation. Surface mount versions are also available.
This improved "N' version replaced the non "A" version formerly introduced.
BLOCK DIAGRAM
Inv. In N.I. In E/A Out Inv. In N.I. In C/L Out
6/93
Reset DR DR 2
~ j4,5,12,13j Gnd
5-159
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, Vee ................................................ 40V Magnetic Amp. Source Voltage, VM .................................... 40V Reset Output Voltage, VR .......................................... ·120V Total Current Source Voltage, VM · VR................................ -140V Amplifier Input Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to Vee Reset Input Current, IDR ........................................... ·1OmA
Q, N Package J Package Power Dissipation at TA= 25°C ........................ 2W. . . . . . . . . . 1W . Power Dissipation at T (leads/case) = 25°C............... 5W.......... 2W . Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to+125°C .. Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C .. Lead Temperature (Soldering, 10 sec)......................... 300°C ..... . Note: All voltages are with respect to ground pins.
All currents are positive into the specified terminal. Consult Packaging section of Databook for thermal limitations and considerations of package.
UC1838A UC2838A UC3838A
CONNECTION DIAGRAMS
DIL-16 {TOP VIEW) J or N Package
C/L Out C/L N.I. In C/L INV. In
Gnd Gnd E/A Inv. In E/A N.i. In E/A Out
DR 2 DR Reset Gnd Gnd VM Vee VREF
Note: All four ground pins must be connected to a common ground
PLCC-20, LCC-20 {TOP VIEW) Q, L Packages
L 3 2 1 201e
4
18
~ 5
17
6
16
7
15
8
14
9 10 11 12 13
PACKAGE PIN FUNCTION
FUNCTION
PIN
N/C
1
C/LOut
2
C/LN.l. In
3
C/L Inv. In
4
GND
5
N/C
6
N/C
7
E/ADiv. In
8
E/A N.1. In
9
E/A Out
10
N/C
11
VREF
12
Vee
13
VM
14
GND
15
N/C
16
N/C
17
Reset
18
DR 1
19
DR2
20
5-160
UC1838A UC2838A UC3838A
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA = -55°C to +125°C for the uc1838A, -20°c to +85°C for the UC2838A, and o·c to +10°c for the UC3838A,
Vee = 20V, VM = 5V, TA= TJ.
PARAMETER
TEST CONDITIONS
UC1838A I UC2838A
UC3838A
UNITS
MIN TVP MAX MIN TVP MAX
Reference Section
Supply Current Reference Output Line Regulation
Vee=VM =40V TA= 25°C Vee= 5to30V
4
8
4
8
mA
2.47 2.5 2.53 2.45 2.5 2.55
v
1
5
1
10 mV
Load Regulation Short Circuit Current
lo= Oto-2mA VREF = OV
5
20
-30 -60
5
20 mV
-30 -60 mA
Temperature Stability*
Over Operating Temp. Range
15
25
10
25 mV
Am_p_llfler Section (Each Amplifier)
Offset Voltage Input Bias Current
VCM =2.5V VIN=OV
5
10 mV
-1
-1
µA
Input Offset Current Minimum Output Swing Output Sink Current Output Source Current AVOL CMRR PSRR Gain Bandwidth*
Vo=5V Vo=OV Vo= 1to11V VIN= 1to11V Vee= 10 to 20V
100
100 nA
0.4
18 0.4
18 v
1
10
30
1
10
30 mA
-1
-10 -20
-1
-10 -20 mA
100 120
100 120
dB
70
80
70 100
70
80
70 100
- 1----d--B dB
0.6 0.8
0.6 0.8
MHz
Reset Drive Section
Input Leakage
VDR = 40V
10
10
µA
Output Leakage
VR = -120V
-100
-100 µA
Input Current
IR= -50mA
-1
-2
-1
-2
mA
Maximum Reset Current
IDR =-3mA
-100 -120 -200 -100 -120 -200 mA
Transconductance
IR= -10 to -50mA
.03 .042 .055 .03 .042 .055 AN
* These parameters are guaranteed by design but not 100% tested m production.
TYPICAL APPLICATION +12V, 4A Output With Switching Frequency = 50 kHz
UES2403
100µH
.020
II 12V Secondary Winding
15V Auxllllary
Supply
5-161
+ 1000
Gnd
Amplifier Open Loop Response
i ~==~:=:=::=======:::: ~:~ § 120>--=""'1..--1-----1--1---+--!-~ 180 fil
w 100
225
BO
B
"""
--+-__.,~-+---f 360 ~
z 20
~
~ 0 l---+--1---+-~1---1---J-~ ~
0.1
10 100 1K 10K .1M 1M
SIGNAL FREQUENCY - {Hz)
Reset Driver Response
UC1838A UC2838A UC3838A
Reset Driver- Input Current
~
~ -100 1----l--l---l--l---l-~~~:::i'l
!z -80
w I a: -60 r---+---1-~
0 -40 r---+---+--cF-t__,_- /.
1ff-i -20
a:
0 '----""'-'--------'---'------'--__L_-
-0.2 -0.4 -0.6 -0.8 -1.0 -1.2
INPUT CURRENT - (mA)
Reset Driver- Input Voltage INPUT VOLTAGE - V(W.R.T. Vm)
Reset Driver- Output Impedance
-40
~1w- -20
-20 -40 -60 -80 -100 RESET VOLTAGE - (V)
Reference Temperature Coefficient
2.55
2.54
I
I
2.53
2.52
2.51
2.50 2.49
i--
~
2.48
2.47
2.46
2.45
-50 0 +50 +100 +150 JUNCTION TEMPERATURE - (C)
UNITAODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD.· !JEAAIMACK, NH 03054 TEL (603) 424-2410 ·FAX (603) 424-3460
5-162
n nlNTEGRATEC
~CIRCUITS
-UNITRODE
Programmable, Off-Line, PWM Controller
UC1840 UC2840 UC3840
FEATURES
DESCRIPTION
All Control, Driving, Monitoring, Although containing most of the features required by all types of switching and Protection Functions Included power supply controllers, the UC1840 family has been optimized for highly-ef-
Low-Current, Off-Line Start Circuit ficient boot-strapped primary-side operation in forward or flyback power con-
Feed-Forward Line Regulation over 4 to 1 Input Range
verters. Two important features for this mode are a starting circuit which requires little current from the primary input voltage and feed-forward control
PWM Latch for Single Pulse per for constant volt-second operations over a wide input voltage range.
Period
In addition to startup and normal regulating PWM functions, these devices of-
Pulse-by-Pulse Current Limiting plus Shutdown for Over-Current Fault
fer built-in protection from over-voltage, under-voltage, and over-current fault conditions. This monitoring circuitry contains the added features that any fault will initiate a complete shutdown with provisions for either latch off or auto-
No Start-Up or Shutdown Transients
matic restart. In the latch-off mode, the controller may be started and stopped with external pulsed or steady-state commands.
Slow Turn-On and Maximum Duty-Cycle Clamp
Shutdown Upon Over-or Under-Voltage Sensing
Latch Off or Continuous Retry after Fault
Remote, Pulse-Commandable Start/Stop
PWM Output Switch Usable to 1A Peak Current
1% Reference Accuracy
500kHz Operation
Other performance features of these devices include a 1% accurate reference, provision for slow-turn-on and duty-cycle limiting, and high-speed pulse-by-pulse current limiting in addition to current fault shutdown.
The UC1840's PWM output stage includes a latch to insure only a single pulse per period and is designed to optimize the turn off of an external switching device by conducting during the "OFF' time with a capability for both high peak current and low saturation voltage. These devices are available in an 18-pin dual-in-line plastic or ceramic package. The UC1840 is characterized for operation over the full military temperature range of -55°C to +125°C. The UC2840 and UC3840 are designed for operation from -25°C to +85°C and 0°c to +70°C, respectively.
NOTE: THIS DEVICE NOT RECOMMENDED FOR NEW DESIGNS.
18-pin DIL package
BLOCK DIAGRAM
14 DRIVER BIAS 12 PWM OUTPUT
NOTE: Positive true logic, latch outputs high with set, reset has priority. 6/93
5-163
400mV
CUR LIMIT THRESHOLD
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage, +VIN (Pin 15) Voltage Driven ................................ +32V CurrentDriven, 100mA maximum ........... Self-limiting
PWM Output Voltage (Pin 12) ....................... 40V PWM Output Current, Steady-State (Pin 12) . . . . . . . . . 400mA PWM Output Peak Energy Discharge ............ 20µJoules Driver Bias Current (Pin 14) . · . . . . . . . . . . . . . . . . . . . -200mA Reference Output Current (Pin16) . . . . . . . . . . . . . . . . -50mA Slow-Start Sink Current (Pin 8) . . . . . . . . . . . . . . . . . . . . 20mA VIN Sense Current (Pin 11 ). . . . . . . . . . . . . . . . . . . . . . . . 1OmA Current Limit Inputs (Pins 6 & 7) . . . . . . . . . . . . . -0.5 to +5.5V Comparator Inputs (Pins 2, 3, 4, 5, 17, 18) ...... -0.3 to +32V Power Dissipation at TA= 25"C .................. 1OOOmW Power Dissipation at Tc= 25°C .................. 2000mW Thermal Resistance, Junction to Ambient .......... 100°C/W Thermal Resistance, Junction to Case.............. 60°C/W Operating Junction Temperature ........... -55°C to +150°C Storage Temperature Range .............. -65°C to +150°C Lead Temperature Range (Soldering, 10 sec) ........ +300°C Note: 1. All voltages are with respect to ground, Pin 13.
Currents are positive-into, negative-out of the specified terminal.
CONNECTION DIAGRAM DIL·18 (TOP VIEW) J or N Package
COMPENSATION 1 START/UV 2 OV SENSE 3
CURRENT THRESHOLD 6 CURRENT SENSE 7 SLOW-START 8
UC1840 UC2840 UC3840
18 NON-INV. INPUT 17 INVERTING INPUT 1 5.0V REF 4 DRIVER BIAS 1 GROUND
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA= -55°C to+125°C for the uc1840, -25°C to + 85°C for the UC2840, and o·c to + 10°c for the UC3840; V1N =
20V, RT= 20k, CT = .001 mfd, CR = .001 mfd, Current Limit Threshold = 200mV, TA=TJ.
PARAMETER Power Inputs
TEST CONDITIONS
UC1840 I UC2840
UC3840
UNITS
MIN TYP MAX MIN TYP MAX
Start-Up Current
VIN= 30V, Pin 2 =2.5V, TJ = 25°C
4
5.5
4
5.5 mA
Start-Up Current T.C.*
VIN = 30V, Pin 2 = 2.5V
-0.1 -0.2
-0.1 -0.2 %/°C
Operating Current Supply OV Clamp
VIN = 30V, Pin 2 = 3.5V llN =20mA
5
10 15
5
10 15 mA
33
40
45
33
40
48
v
Reference Section Reference Voltage
TJ= 25·c
4.95 5.0 5.05 4.9 5.0 5.1
v
Line Regulation
VIN =8to30V
10
15
10 20 mV
Load Regulation
IL= 0 to 20mA
10 20
10 30 mV
Temperature Coefficient*
Over Operating Temperature Range
±0.4
±0.4 mV/°C
Short Circuit Current
VREF = 0, TJ = 25°C
-80 ·100
-80 -100 mA
Oscillator
Nominal F!equency
TJ=25°C
47
50
53
45
50
55 kHz
Voltage Stabi!!!¥_
VIN =8to30V
0.5
1
0.5
1
%
Temperature Coefficient*
Over Operating Temperature Range
±.08
±.08 %/°C
Maximum Frequency
RT = 2kQ, CT = 330pF
500
500
kHz
Ramp Generator
Ramp Current, Minimum
ISENSE = ·10µA
-14 -11
-14 -11
~
Ramp Current, Maximum
ISENSE = 1 .OmA
-.95 -0.9
-.95 -0.9 mA
Ramp Valley
0.3 0.5 0.7 0.3
0.5 0.7
v
Ramp Peak
Clamping Level
3.9 4.2 4.5 3.9 4.2 4.5
v
* These parameters are guaranteed by design but not 1DO% tested m production.
5-164
UC1840 UC2840 UC3840
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA= -55°C to+ 125°C for the
uc1840, -25°C to + 85°C for the UC2840, and o·c to + 10°c for the UC3840; V1N = 20V, RT= 20k, CT= .001mfd, CR= .001mfd, Current Limit Threshold= 200mV, TA= TJ.
PARAMETER Error Ampllfler
TEST CONDITIONS
UC1840 I UC2840
UC3840
UNITS
MIN TVP MAX MIN TVP MAX
Input Offset Voltage
VcM = 5.0V
Input Bias Current
Input Offset Current
Open Loop Gain
!No= 1 to3V
Output Swing (Max. Output "' Minimum Total Range Ramp Peak - 1OOmV)
CMRR
VcM = 1.5 to 5.5V
PSRR
VIN= 8to30V
Short Circuit Current
VCOMP = OV
Gain Bandwidth*
TJ = 25°C, AVOL = OdB
Slew Rate*
TJ = 25°C, AVCL = OdB
PWM Section
0.5
5
2
10 mV
0.5
2
1
5
µA
0.5
0.5 µA
60 66
60 66
dB
0.3
3.5 0.3
3.5 v
70 80
70 80
dB
70 80
70 80
dB
-4 -10
-4 -10 mA
1
2
1
2
MHz
0.8
0.8
V/µs
Continuous Duty Cycle Range· (other than zero) Output Saturation
Output Leakage Comparator Delay· Sequencing Functions Comparator Thresholds Input Bias Current Start/UV Hysteresis Current Input Leakage Driver Bias Saturation Voltage, VIN - VoH
Minimum Total Continuous Range, Ramp Peak < 4.2V IOUT = 20mA IOUT = 200mA VoUT = 40V Pin 8 to Pin 12, TJ = 25°C, RL = 1kQ
Pins 2, 3, 4, 5 Pins 3, 4, 5 = OV Pin 2 = 2.5V, TJ = 25°C l_nput V = 20V IB = -50mA
5
95
5
95
%
0.2 0.4
1.7 2.2
0.1
10
300 500
0.2 0.4
v
1.7 2.2
v
0.1
10
µA
300 500 ns
--- --
2.8 3.0 3.2 2.8 3.0 3.2
v
-1.0 -3.0
-1.0 -3.0 µA
180 200 220 170 200 230 µA
0.1
10
0.1
10
µA
2
3
2
3
v
Driver Bias Leakage Slow-Start Saturation
VB=OV Is= 2mA
-0.1 -10 0.2 0.5
-0.1 -10 µA
0.2 0.5
v
Slow-Start Leakage
Vs= 4.5V
0.1 2.0
0.1 2.0 µA
Current Control
Current Limit Offset
0
5
0
10 mV
Current Shutdown Offset
370 400 430 360 400 440 mV
Input Bias Current Common Mode Range·
Pin 7 = OV
-2
-5
-2
-5
µA
-0.4
3.0 -0.4
3.0 v
Current Limit Delay*
TJ = 25°C, Pin 7 to 12, AL= 1k
200 400
*These parameters are guaranteed by design but not 100% tested m production.
200 400 ns
5-165
UC1840 UC2840 UC3840
FUNCTIONAL DESCRIPTION
PWMCONTROL 1. Oscillator
Generates a fixed-frequency internal clock from an external RT and CT.
Frequency= ~~where Kc is a first order correction factor- 0.3 log (CT X 1012).
2. Ramp Generator
Develops a linear ramp with a slope defined externally by ':;- sens~R~!tage. CR is normally
3. Error Amplifier 4. Reference Generator 5. PWM Comparator 6. PWM Latch 7. PWM Output Switch SEQUENCING FUNCTIONS 1. Start/UV Sense
2. Drive Switch 3. Driver Bias 4. Slow Start 5. Start Latch 6. Reset Latch
PROTECTION FUNCTIONS 1. Error Latch
2. Current Limiting
selected :s CT and its value will have some effect upon valley voltage. CR terminal can be used as an il'lJ'.lllt ~rt for current mode control. Conventional operational amplifier for closed-loop gain and phase compensation. Low ou!Q_ut im~dance· un~ain stable. Precision 5.0V for internal and external usage to 50mA. Tracking 3.0V reference for internal usage only with nominal accuracy of± 2%. 40V clam_E_zener for ch!E_OV_E!:otection, 1OOmA maximum current. Generates output pulse which starts at termination of clock pulse and ends when the ramp ir:!Q_ut crosses the lowest of two_E_ossible ir:!Q_uts. Terminates the PWM output pulse when set by inputs from either the PWM comparator, the pulse-by-pulse current limit comparator, or the error latch. Resets with each internal clock !J>ulse. Transistor capable of sinking current to ground which is off during the PWM on-time and turns on to terminate the power pulse. Current capacity is 400mA saturated with peak capacitance dischar_g_e in excess of one amp.
This comparator performs three functions With an increasing voltage, it generates a turn-on signal at a start threshold. With a decreasing voltage, it generates a UV fault signal at a lower level separated by a
200µA hysteresis current. At the UV threshold, it also resets the Error Latch if the Reset Latch has been set. Disables most of the chip to hold internal current consumption low, and Driver Bias off, until ir:!Q.ut volt<!.9.e reaches start threshold. Supplies drive current to external.J!9wer switch to_.Q!"OVide turn-on bias. Clamps low to hold PWM off. Upon release, rises with rate controlled by RsCs for slow increase of output pulse width. Also used to clam_E_maximum dl!!Y_~le with divider RsRoc. Keeps low input voltage at initial turn-on from being defined as a UV fault . Sets at start level to monitor for UV fault. When reset, this latch insures no reset signal to either Start or Error Latches· so that first fault will lock the PWM off. When set, this latch resets the Start and and Error latches at the UV low threshold, allowing a restart.
When set by momentary input, this latch insures immediate PWM shutdown and hold off until reset. Inputs to Error Latch are:
a. UV low (after turn-on) b. OVhigh c. Stop low d. Current Sense 400mV over threshold. Error Latch resets at UV threshold if Reset Latch is set. Differential input comparator terminates individual output pulses each time sense voltage rises above threshold. When sense vol~e rises to 400mV above threshold, a shutdown s_!g_nal is sent to error latch.
5-166
Start/UV Hysteresis Current
V1N -2ov Vp1N 2·2.5V f---+--+----+--'
;;
a. ~ 275 H--t---+--t---t--+--+----1
£ 0 250 H--+---t--+--1---+--+---I
.z:. 225
LU
~ 200 => 0 175 J,.i""'--t;....-'+--t---1--+-~+-=cJ
"'iii 150
aw : ~ 125 -+--+---t---t--1---+--+---I
:">c-'
-50 -25 0 25 50 75 100 125
JUNCTION TEMPERATURE-(OC)
UC1840 UC2840 UC3840
PWM Output Saturation Voltage
~
VtN ·20V
~ 4
<
Low duty-cycle pulse test
1-
..J
~ 3 f----+---+--+-----+---1
z
0 j:: 2
a< :
::::> I-
e<n
~ 0 .-=.__L__ __l_ __J__
__L_ _
~ 0 100 200 300 400 500
::::> 0 OUTPUT SINK CURRENT-(mA)
Oscillator Frequency
2 5 10 20 50100 200 500 RT TIMING RESISTER - (k 0 )
PWM Output Minimum Pulse Width
i1 w
~ 5.0
~
i c
3.0 2.0
(Pulse width ·goes to Zero I
below value Indicated}
l I
-+---' 1/2 Cr <CR <Cr ---
~ 1.0
..J
~ 0.5
::e 0.3 H---+--t--t---"'"-..P""=-t--~~:::--1
:::> ;!; 0.2 H---+-+-+---f--""j-.~"'='-""
z :ii 0.1~-~+-+--~-~~--
10 20 30 50 100 200 300 500
OSCILLATOR FREQUENCY-(k Hertz}
Error Amplifier Open-Loop Gain and Pulse
ao~-~-~---1--~~
VtN·20V
-s. !~ D60~
TJ ·25 C
~GAIN
"Q'I
cQI,
z 40
QI
< e. C>
' h w 20f----+----tl~---P<,.---t---I
1u-.
~ ~ s: 1-
..J
en
O r--<""~:::-t--r----r-P-H-AS-E-t---t'\t---i 1BO W
-r- >0
270 ~
100 1K 10K 100K 1M aso ~
FREQUENCY - (Hertz)
5-167
Shutdown Timing
Pin 4 Volts
5>-----+---1---t----+--___, Input to Ext. Stop !
oL-~t=::::::i====t===t:==_j
Pin 8 Volts
5>-----+---1-+-'~-t---+-___,
0>-----+---1---t----+--___,
20f-----+---l---t---+-___,
Pin 12 Volts
PWM Outpu
Of__~V~o~lta~g~e--l--.'=t=====i==---1
0 500 1000 1500 DELAY TIME - (n sec)
OPEN-LOOP TEST CIRCUIT
UC1840 UC2840 UC3840
0 SUPPLY VOLTAGE
®l
Rs 100K
RT 20K
CT .001
R1 20K ~
R2 9K
16 VREF
11 VIN SENSE
9 RT/CT 10
RAMP
2 START/UV
3 OV SENS
R3 3K
.001
-
-
COMP
10K
15 VIN
UC1840 D.U.T.
Rs
8 SLOW START
14 DRIV BIAS PWM OUT 12
13 GRID STOP RESET
INV NI C/L(·)
17
18
9
C/L(+) 7
180K
Roe 24K
~J RL · 1K
OUTPUT
MONITOR
-
VREF
48K
43K
NOMINAL FREQUENCY= RT~T = 50 kHz
START VOLTAGE= 3 (Rl + R2 +Ra)+ 0.2R1=12V R2+R3
2K
10K
~ CURRENT SENSE TEST
UV FAULT VOLTAGE= 3 (RI + R2 +Ra) =av R2+R3
CURRENT LIMIT= 200mV CURRENT FAULT LIMIT= 600mV
OV FAULT VOLTAGE= 3 (Rl + : : + R3) = 32V
DUTY CYCLE CLAMP= 50%
FLVBACK APPLICATION (A)
In this application (see Figure A, next page), complete control is maintained on the primary side. Control power is provided by RIN and CIN during start-up, and by a primary- referenced low voltage winding, N2, for efficient operation after start. The error amplifier loop is closed to regulate the DC voltage from N2 with other outputs following through their magnetic coupling - a task made even easier with the UC1840's feed-forward line regulation.
An extension to this application for more precise regulation would be the use of the UC1901 Isolated Feedback Generator for direct closed-loop control to an output. The UC1840 will readily accept digital start/stop commands transmitted from the secondary side by means of optical couplers.
Not shown are protective snubbers or additional interface circuitry which may be required by the choice of the highvoltage switch, Qs, or the application.
REGULATOR APPLICATION (B)
Although primarily intended for transformer-coupled power systems, the UC1840's advantages of feed-forward for high ripple-rejection, a fully contained fault monitoring system and remote start/stop capability make it worth considering for other types of regulators. Since the fault logic within the UC1840 requires recycling the voltage sensed by the Start/UV comparator to reset the error latch, a need for automatic restart must be addressed in a manner similar to that shown in Figure B (next page). In this simple, non-isolated, buck regulator; diode 01 provides a low-impedance bootstrapped drive power source after start-up is achieved through RIN and CIN. When a fault shutdown terminates switching action, the loading of 01 and RD will lower the voltage on pin 2 to effect an automatic re-start attempt which will continuously recycle until the fault is removed.
5-168
Uc1840 Programmable Pwm Controller in a Simplified Flyback Regulator (A)
DC INPUT LINE
CONTROL VOLT AGE
RR
AC INPUT
R7 R3
R1
R· R1
DRIVE BIAS
TURN ON PWM
UVF
UC1840 UC2840 UC3840
R2 UC1840
U1: UC3705/06/07 /09 MOSFET DRIVER
UC1840 Controls a High-Current Non-Isolated Buck Regulator (B)
V1N · 10-30V
RIN 3.3k
33k
D1
SES1105
Vo
10011H 0.1
Vo · SV SA
.;i:, SOµF
Sk
1k 8.2k
7.5k
5-169
2.4k 3k 2k
UC1840 POWER SEQUENCING FUNCTIONS
UC1840 UC2840 UC3840
TIME EVENT
i nnii i11 nnr iiii 1r1
Vc(NOTE 1)
WINDOW BIAS
SLOW START
PWM STOP (NOTE 2 ) - - - - . . . . ,
RESET-------------'
i i1i 1i i11 ii i1 IHi l11
Notes 1: Ve represents an analog of the output voltage generated by a primary referenced secondary winding on the power transformer. It is the voltage monitored by the start/UV comparator and, in most cases, is the supply voltage, VtN, for the UC1840.
Note 2: Although input to External Stop, Pin 4, is shown, results are the same for any fault input which sets the E"or Latch.
A Initial turn-on, Ve rises with load
B Start threshold. Driver Bias loads Ve
c Operating PWM regulates Ve
D Stop input sets Error Latch turning off PWM
E UV low threshold, Error Latch remains set
F Start turns on Driver bias but Error Latch still set
G H
} Ve and Driver Bias continue to cycle
Stop command removed
J Error Latch reset at UV low threshold
K Start threshold now removes slow-start clamp
L Return to normal run state
M Reset Latch set signal removed
N Error Latch set with momentary fault
0 Error Latch does not reset as Reset Latch is reset
ap } Ve and Driver Bias recycle with no tum-on.
R Reset Latch set is set with momentary
Reset signal
s Ve must complete cycle to tum-on
T Start and Error Latches reset
u Normal start initiated
v Return to normal run state
Power MOSFET Drive Circuit Using UC3705/3706/3707 or 3709 Drivers
14 DRIVER
BIAS
3K
12
INV
PWM
OUTPUT
3K
GND
13
1nFY1opF
D1
.,J
OUT
10
D2
1K
UC3706 Converts Single Output PWMs to High Current Push-Pull Configuration
14 DRIVER
BIAS
OUT 12 UC3840
OR UC3841
ON 13
D1, D2: UC3611 Schottky Diode
UC3611 Quad Schottky Diode Array
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5-170
n n INTEGRATED
~CIRCUITS
-UNITRODE
Programmable, Off-Line, PWM Controller
((Q))
UC1841 UC2841 UC3841
FEATURES All Control, Driving, Monitoring, and Protection Functions Included
Low-current, Off-line Start Circuit
Voltage Feed Forward or Current Mode Control
Guaranteed Duty Cycle Clamp
PWM Latch for Single Pulse per Period
Pulse-by-Pulse Current Limiting Plus Shutdown for Over-Current Fault
No Start-up or Shutdown Transients
Slow Turn-on Both Initially and After Fault Shutdown
Shutdown Upon Over- or Under-Voltage Sensing
Latch Off or Continuous Retry After Fault
DESCRIPTION The UC1841 family of PWM controllers has been designed to increase the level of versatility while retaining all of the performance features of the earlier UC1840 devices. While still optimized for highly-efficient bootstrapped primary-side operation in forward or flyback power converters, the UC1841 is equally adept in implementing both low and high voltage input DC to DC converters. Important performance features include a low-current starting circuit, linear feed-forward for constant volt-second operation, and compatibility with either voltage or current mode topologies.
In addition to start-up and normal regulating PWM functions, these devices include built in protection from over-voltage, under-voltage, and over-current fault conditions with the option for either latch-off or automatic restart.
While pin compatible with the UC1840 in all respects except that the polarity of the External Stop has been reversed, the UC1841 offers the following improvements:
1. Fault latch reset is accomplished with slow start discharge rather than recycling the input voltage to the chip.
2. The External Stop input can be used for a fault delay to resist shutdown from short duration transients.
PWM Output Switch Usable to 1A Peak Current
3. The duty-cycle clamping function has been characterized and specified.
1% Reference Accuracy 500kHz Operation 18 Pin DIL Package
The uc1 841 is characterized for -55°C to +125°C operation while the UC2841 and UC3841 are designed for -2s0 c to +85°C and 0°to +10°c, respectively.
BLOCK DIAGRAM
COMP 1 1 1 - - - - - - - , INV. INPUT
NI INPUT nai----i·-,,.
START/UV
CURRENT LIMIT THRESHOLD CURRENT SENSE
OV SENSE
EXT. STOP !'·~--------__.
Note: Positive true logic, latch outputs high with set, reset has priority. 6/93
5-171
5.0V REF
.-...------.01
SLOW-START/ DUTY CYCLE
CLAMP
+---------11-"l GROUND
ABSOLUTE MAXIMUM.RATINGS
Supply Voltage, +VIN (Pin 15) (Note 2) Voltage Driven ................................. +32V Current Driven, 1OOmA maximum. . . . . . . . . . . . Self-limiting
PWM Output Voltage (Pin 12) ....................... 40V PWM Output Current, SteadycState (Pin 12) . . . . . . . . . 400mA PWM Output Peak Energy Discharge ............ 20µJoules Driver Bias Current (Pin 14) . . . . . . . . . . . . . . . . . . . . . -200mA Reference Output Current (Pin 16) . . . . . . . . . . . . . . . . -50mA Slow-Start Sink Current (Pin 8) . . . . . . . . . . . . . . . . . . . . 20mA VIN Sense Current (Pin 11). . . . . . . . . . . . . . . . . . . . . . . . 1OmA Current Limit Inputs (Pins 6 & 7) . . . . . . . . . . . . . -0.5 to +5.5V Stop Input (Pin 4) . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +5.5V Comparator Inputs
(Pins 1, 7, 9-11, 16) ............ Internally clamped at 12V Power Dissipation at TA= 25°C (Note 3) ........... 1000mW Power Dissipation at Tc = 25°C (Note 3) ........... 2000mW
CONNECTION DIAGRAMS
DIL-18, SOIC-18 (TOP VIEW) J or N, DW Package
N.I. Input
Inv. Input
5.0V Rel.
+VIN Supply
Drive Blas
Ground
PWM Out
Ramp
UC1841 UC2841 UC3841
Operating Junction Temperature .......... -55°C to +150°C Storage Temperature Range. . . . . . . . . . . . . . -65°C to +150°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C Note 1: All voltages are with respect to ground, Pin 13.
Currents arf! positive-into, negative-out of the specified terminal. Note 2: All pin numbers are referenced to DIL-18 package. Note 3: Consult Packaging Section of Databook for thermal limitations and considerations of package.
PLCC-20, LCC-20
(TOPVIEW) Q or L Package
6
16
7
15
8
14
9 10 11 12 13
PACKAGE PIN FUNCTIONS
FUNCTION
PIN
Com_Q_
1
StaJ!LUV
2
OVSense
3
Sto...I!_
4
Reset
5
CUR Thresh
7
CUR Sense
8
Slow Start
9
Rri_CT
10
Ram_Q_
11
VIN Sense
12
PWMOut
13
Ground
14
Drive Bias
15
+VIN Supp.ht_
17
5.0V REF
18
Inv. 11111..ut
19
N .I. l'!!?_ut
20
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA= -55°C to +125°C for the
UC1841, -25°C to +85°C for the UC2841, and o·c to +70°C for the UC3841; V1N = 2ov, Rr = 20kQ, Cr= .001 mfd, RR= 10ko, CR= .001mfd, Current Limit Threshold= 200mV, TA= TJ.
PARAMETER
Power Inputs Start-Up Current Operating Current Supply OV Clamp
Reference Section Reference Voltage Line Regulation Load Regulation Temperature Stability Short Circuit Current
Oscillator Nominal Frequency Voltage Stability Temperature Stability Maximum Frequency
TEST CONDITIONS
UC1841 / UC2841 MIN TYP MAX
UC3841
UNITS
MIN TYP MAX
VIN = 30V, Pin 2 = 2.5V VIN = 30V, Pin 2 = 3.5V llN =20mA
4.5
6
4.5
6
mA
10
14
10
14 mA
33
40
45
33
40
45
v
TJ = 25·c
4.95 5.0 5.05 4.9 5.0 5.1
v
VIN= 8to 30V
10
15
10
20 mV
IL= Oto 10mA
10
20
10
30 mV
Over Operating Temperature Range 4.9
5.1 4.85
5.15 v
VREF = 0, TJ = 25°C
-80 -100
-80 -100 mA
TJ=25°C
47
50
53
45
50
55 kHz
VIN= 8to 30V
0.5
1
0.5
1
%
Over Operating Temperature Range 45
55
43
57 kHz
RT = 2kQ, Cr = 330pF
500
500
kHz
5-172
UC1841 UC2841 UC3841 ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA = -55°C to +125°C for the
UC1841, -25°C to +85°C forthe UC2841, and o·cto +70°C forthe UC3841; V1N = 2ov, RT= 20ko, CT= .001mfd, RR= 10k0, CR= .001 mfd, Current Limit Threshold= 200mV, TA= TJ.
PARAMETER Ramp Generator
TEST CONDITIONS
UC1841 / UC2841
UC3841
UNITS
MIN TYP MAX MIN TYP MAX
Ramp Current, Minimum Ramp Current, Maximum Ramp Valley Ramp Peak Error Amplifier Input Offset Voltage Input Bias Current Input Offset Current Open Loop Gain Output Swing (Max. Output :.: Ramp Peak - 1OOmV)
ISENSE = -1 OµA ISENSE = 1.0mA Clamping Level VCM=5.0V
!No= 1 to3V Minimum Total Range
-11 -14
-11 -14 µA
-0.9 -.95
-0.9 -.95
mA
0.3 0.4 0.6 0.3 0.4 0.6
v
3.9 4.2 4.5 3.9 4.2 4.5
v
0.5
5
2
10 mV
0.5
2
1
5
µA
0.5
0.5 µA
60 66
60 66
dB
0.3
3.5 0.3
3.5
v
CMRR PSRR Short Circuit Current Gain Bandwidth* Slew Rate* PWM Section
VcM = 1.5 to 5.5V VIN= 8 to 30V VCOMP=OV TJ = 25°C, AvoL = OdB TJ = 25°C, AVCL = OdB
70
80
70 80
dB
70
80
70 80
dB
-4 -10
-4 -10 mA
1
2
1
2
MHz
0.8
0.8 - --·· ·- Vj~s
Continuous Duty Cycle Range* (other than zero) 50% Duty Cycle Clamp Output Saturation
Output Leakage Comparator Delay* Sequencing Functions
Minimum Total Continuous Range,
4
Ramp Peak < 4.2V
95
4
95
%
RSENSE to VREF = 1Ok
42
47
52
42
47
52
%
IOUT=20mA
0.2 0.4
0.2 0.4
v
IOUT=200mA
1.7 2.2
1.7 2.2
v
VOUT= 40V
0.1 10
0.1
10
µA
Pin 8 to Pin 12, TJ = 25°C, AL= 1ko
300 500
300 500 ns
Comparator Thresholds Input Bias Current Input Leakage Start/UV Hysteresis Current
Pins2, 3, 5 Pins3, 5 =OV Pins 3, 5 = 10V Pin 2 =2.5V
2.8 3.0 3.2 2.8 3.0 3.2
v
-1.0 -4.0
-1.0 -4.0 µA
0.1 2.0
0.1 2.0 µA
170 200 220 170 200 230 µA
Ext. Stop Threshold
Pin4
0.8 1.6 2.4 0.8 1.6 2.4
v
Error Latch Activate Current Pin4=0V,Pin3>3V
Driver Bias Saturation Voltage, IB=-50mA VIN-VOH
-120 -200
2
3
-120 -200 µA
2
3
v
Driver Bias Leakage Slow-Start Saturation Slow-Start Lea~e Current Control
Vs=OV Is= 10mA Vs=4.5V
-0.1 -10 0.2 0.5 0.1 2.0
-0.1 -10 µA
0.2 0.5
v
0.1 2.0 µA
Current Limit Offset Current Shutdown Offset Input Bias Current
Pin 7 =OV
0
5
0
10 mV
370 400 430 360 400 440 mV
-2
-5
-2
-5
µA
Common Mode Range*
-0.4
3.0 -0.4
3.0
v
Current Limit Delay*
TJ = 25°C, Pin 7 to 12, AL= 1k
200 400
*These parameters are guaranteed by design but not 100% tested in production.
200 400 ns
5-173
FUNCTIONAL DESCRIPTION
UC1841 UC2841 UC3841
PWMCONTROL
1. Oscillator
Generates a fixed-frequency internal clock from an external RT and CT.
Frequency = R~ where Kc is a first order correction factor - 0.3 log (CT X 1o12).
2. Ramp Generator
3. Error Amplifier 4. Reference Generator 5. PWM Comparator 6. PWMLatch 7. PWM Output Switch SEQUENCING FUNCTIONS 1. Start/UV Sense
2. Drive Switch 3. Driver Bias 4. Slow Start PROTECTION FUNCTIONS 1. Error Latch
2. Current Limiting
3. External Stop
Develops a linear ramp with a slope defined externally by : - sense voltage RRCR
CR is normally selected :s CT and its value will have some effect upon valley voltage. Limiting the minimum value for ISENSE will establish a maximum duty cycle clamp. CR terminal can be used as an i11Q_ut..2_ort for current mode control. Conventional operational amplifier for closed-loop gain and phase compensation. Low output impedance; unity-gain stable. The out!!_ut is held low ~the slow start voltag_e at turn on in order to minimize overshoot. Precision 5.0Vfor internal and external usage to 50mA. Tracking 3.0V reference for internal usage only with nominal accuracy of± 2%. 40V clam_E>_zener for ch.!e_OVjl_l'Otection, 1OOmA maximum current. Generates output pulse which starts at termination of clock pulse and ends when the ramp
if!E.ut crosses the lowest of two_E2.Sitive i11Q_uts. Terminates the PWM output pulse when set by inputs from either the PWM comparator, the
pulse-by-pulse current limit comparator, or the error latch. Resets with each internal clock ....e_ulse. Transistor capable of sinking current to ground which is off during the PWM on-time and turns on to terminate the power pulse. Current capacity is 400mA saturated with peak c~acitance discham_e In excess of one amJ>.
With an increasing voltage, it generates a tum-on signal and releases the slow-start clamp at a start threshold.
With a decreasing voltage, it generates a turn-off command at a lower level separated by a 200µA ~teresis current.
Disables most of the chip to hold internal current consumption low, and Driver Bias OFF, until inj>_ut vol~e reaches start threshold.
SLJJllllies drive current to external_J)Ower switch to..m-ovide turn-on bias. Clamps low to hold PWM OFF. Upon release, rises with rate controlled by RsCs for slow
increase of output pulse width. Can also be used as an alternate maximum dl!!Y._~cle clam....e_with an external voltaJl..e divider.
When set by momentary input, this latch insures immediate PWM shutdown and hold off until reset. Inputs to Error Latch are:
a. OV > 3.2V (typically 3V} b. Stop > 2.4V (typically 1.6V} c. Current Sense 400mV over threshold (typical). Error Latch resets when slow start voltage falls to 0.4V if Reset Pin 5 < 2.8V. With Pin 5 > 3.2V, Error Latch will remain set. Differential input comparator terminates individual output pulses each time sense voltage rises above threshold. When sense voltage rises to 400mV (typical) above threshold, a shutdown signal is sent to Error Latch. A voltage over 1.2V will set the Error Latch and hold the output off. A voltage less than 0.8V will defeat the error latch and prevent shutdown. A capacitor here will slow the action of the error latch for transient protection by providing a _tyjlical delay of 13msM.
5-174
.
Start/UV Hysteresis
s ~
VIN· 20V t----iVPIN 2 - 2.5V
_j_
i 275
250 I-
ifi 225
200
§ t:::::r -- ::t::::- 175
FuCJ ~ 150
w
f' ffi 125
UC1841
UC1841-
Max
UC3841 Max l;;'..:::~=~=_.;::j
Max
Tu lcal Characteristic
1--
!:::_--'
\lQ'\S~ ~41 !Min-= ~41
l
Iii
~
-50 -25 0 25 50 75 100 125
JUNCTION TEMPERATURE - (°C)
UC1841 UC2841 UC3841
PWM Output-Saturation Voltage ~
~ 4
cS
> 3
~ ~ 2
Cl) 1
§ ~
o
o~--'-----'--....L__j 100 200 300 400 500
OUTPUT SN< CURRENT - (mA)
Oscillator Frequency
500~,__.......,-..+--+--+---+---+----+--l
£ 200
- 100 i-"c-l'r--"1----~-~+--+---+--l
I:. ,. ._ ,._~. I. C'-~~"'<--~~ 50 !--"<r"<-......--'lt---'k--~'fl.....
2
2 5 10 20 50 100 200 500 RT TIMING RESISTOR - (k fl )
PWM Output Minimum Pulse Width
¥
..:. 10
(Pulse width goes to zero
below value in<f1Cated)
i
.
F!= 5.0 ~-c---<-+-~-~~----i
~ 3.0 2.0 t-t-".--..t-n:'""-
~ 1.0
05 H--p.;:,_..;j'S~~......+"-..--!---1--1 ~ 0.3 H---+-+-~_,,,,,_,P....,-t'"'-1:=----1
I 00..12 ,~,.__L_L_---'----'-----'---'-= 10 20 30 50 100 200 300 500
OSCILLATOR FREQUENCY - (kHz)
Error Amplifier Open Loop Gain and Phase
80
! 60
~ 40
~ 20
i
g lll 0 1-==-+---+---+---~180 < 1---t---=""'i""--t-=:---t--1 270 iE
~~-~-~-~~350
100 t< 10K 100K 1M
FREQUENCY - (Hz)
5-175
Shutdown Timing
5 PIN 3 VOLTS
0
5 PIN 8 VOLTS
0
20 PIN 12 VOLTS
0
Input to OV Sense Cs>O
0 500 1000 1500 DELAY TIME - (n sec)
OPEN-LOOP TEST CIRCUIT
UC1841 UC2841 UC3841
Ol)-----,>----;=============~---------~
Supply Voltage
~.-+--~16 VREF
15 Rs
VIN
Slow Start 8
100k
RR 10k RT 20k CT
.001...,.I._.
R1 20k
11 VIN Sense
Driver Blas 14
g RT/CT
UC1841 D.U.T. PWM Out 12
10 Ramp
DIL-18
Package
2 Start/UV
R2 9k - - - - - 1 - . : : . -3i OV Sense
R3 3k
NI C/L(-)
10k
18 8
.io.V1REF
10k
10k 10k
48k
43k
"'ii'" PWM Adjust
2k
.,...
10k
.,... Current Sense Test
Nominal Frequency = ~Cr = 50 kHz
UV Fault Voltage= 3 (R1 R+2R+2R+3R3) = BV
Start Voltage = 3 (R1~:2; 3R3) +0.2R1 = 12V OV Fault Voltage = 3 (R1 + RR32 + R3) = 32V
= Current Limit 200mV
Current Fault Voltage= 600mV Duty Cycle Clamp = 50%
FLYBACK APPLICATION (A)
In this application (see Figure A, next page), complete control is maintained on the primary side. Control power is provided by RIN and CIN during start-up, and by a pri~ mary-referenced low voltage winding, N2, for efficient operation after start. The error amplifier loop is closed to regulate the DC voltage from N2 with other outputs following through their magnetic coupling - a task made even easier with the UC1841's feed-forward line regulation.
An extension to this application for more precise regulation would be the use of the UC1901 Isolated Feedback Generator for direct closed-loop control to an output.
Not shown, are protective snubbers or additional interface circuitry which may be required by the choice of the highvoltage switch, Qs, or the application; however, one example of power transistor interfacing is provided on the following page.
REGULATOR APPLICATION (B)
With the addition of a level shifting transistor, 01, the UC1841 is an ideal control circuit for DC to DC converters such as the buck regulator shown in Figure B opposite. In addition to providing constant current drive pulses to the PIC661 power switch, this circuit has full fault protection and high speed dynamic line regulation due to its feedforward capability. An additional feature is the ability to
5-176
AC Input
DC Input Line Control
UC1841 UC2841 UC3841
Turn On UVP R1
R2
Stop Reset
UC1841
Figure A. UC1841 Programmable PWM Controller In A Simplified Flyback Regulator
U1: UC3705 MOSFET Driver
Note: UC3707 Pini 1,4,15,7,12,13,19, To Gnd
See Application Note U-114 For Complete Circuit
Figure B. Overall Schematic For A 300 Watt, Off-line Power Converter Using The UC3841 For Control
5-177
ERROR LATCH INTERNAL CIRCUITRY
Internal 5V
To Shutdown
PROGRAMMABLE SOFT START AND RESTART DELAY CIRCUIT
UC1841 UC2841 UC3841
The Error Latch consists of Q5and Q6which, when both on, turnsoffthePWMOutputandpullstheSlow-Startpiniow.This latch is set by either the Over-Voltage or Current Shutdown comparators, or by a high signal on Pin 4. Reset is accomplished by either the Reset comparator or a low signal on Pin 4. An activation time delay can be provided with an external capacitor on Pin 4 in conjunction with the - 1001-!A collector current from 04.
Restart Delay = (.51)(RRD )(CRD)
CURRENT MODE CONTROL
VOLTAGE FEED-FORWARD COMBINED WITH MAXIMUM DUTY-CYCLE CLAMP
VIN
Since Pin 1O is a direct input to the PWM comparator, this point can also serve as a current sense port for current mode control. In this application, current sensing is ground referenced through Res. Resistor R1 sets a 400mV offset across R2 (assuming R2 > Res) so that both the Error Amplifier and Fault Shutdown can force the current completely to zero. R2 is also used along with CF as a small filter to attenuate leadingedge spikes on the load current waveform. In this mode, current limiting can be accomplished by divider R3/R4 which forms a clamp overriding the output of the Error Amplifier.
In this circuit, R1 is used in conjunction with CR (not shown) to establish a minimum ramp charging current such that the ramp voltage reaches 4.2V at the required maximum output pulse width.
The purpose of 01 is to provide an increasing ramp current above a threshold established by R2 and R3 such that the duty cycle is further reduced with increasing VIN.
The minimum ramp current is:
IR(MIN) · VREF - VIN SENSE - 4 V
R1
R1
The threshold where VIN begins to add extra ramp current is:
(R2; : VIN - 5.6V
3)
Abovethethreshol d,th eram pcurrentwill be:
IR (VARIAB) - ~1 +VIN;;.25.6 - ~~
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5-178
n n INTEGRATED
~CIRCUITS
-UNITROOE
Current Mode PWM Controller
(®)
UC1842/3/4/5 UC2842/3/4/5 UC3842/3/4/5
FEATURES Optimized For Off-line And DC To DC Converters
Low Start Up Current (<1mA)
Automatic Feed Forward Compensation
Pulse-by-pulse Current Limiting
Enhanced Load Response Characteristics
Under-voltage Lockout With Hysteresis
Double Pulse Suppression
High Current Totem Pole Output
Internally Trimmed Bandgap Reference
500khz Operation
Low Ro Error Amp
DESCRIPTION
The UC1842/3/4/5 family of control ICs provides the necessary features to implement off-line or DC to DC fixed frequency current mode control schemes with a minimal external parts count. Internally implemented circuits include under-voltage lockout featuring start up current less than 1mA, a precision reference trimmed for accuracy at the error amp input, logic to insure latched operation, a PWM comparator which also provides current limit control, and a totem pole output stage designed to source or sink high peak current. The output stage, suitable for driving N Channel MOSFETs, is low in the off state.
Differences between members of this family are the under-voltage lockout thresholds and maximum duty cycle ranges. The UC1842 and UC1844 have UVLO thresholds of 16V (on) and 10V (off), ideally suited to off-line applications. The corresponding thresholds for the UC1843 and UC1845 are 8.4V and 7.6V. The UC1842 and UC1843 can operate to duty cycles approaching 100%. A range of zero to 50% is obtained by the UC1844 and UC1845 by the addition of an internal toggle flip flop which blanks the output off every other clock cycle.
BLOCK DIAGRAM
S/R
5V REF
!-<~----+-------;
8
INTERNAL BIAS
VREF
5.0V 50mA
VFe
COMP CURRENT
SENSE
= = Note 1: ~A DIL-8 Pin Number. B S0-14 Pin Number.
Note 2: Toggle flip flop used only in 1844 and 1845.
6/93
5-179
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage (Low Impedance Source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30V Supply Voltage (Ice <30mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Self Limiting Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . :i:1A Output Energy (Capacitive Load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5µJ Analog Inputs (Pins 2, 3) ....................................... -0.3V to +6.3V Error Amp Output Sink Current ......................................... 1OmA
Power Dissipation at TA "25°C (DIL-8) .................................... 1W Power Dissipation at TA "25°C (SOIC-14) .............................. 725mW
Storage Temperature Range .................................. -65°C to +150°C Lead Temperature (Soldering, 10 Seconds) .............................. 300°C Note 1: All voltages are with respect to Pin 5.
All currents are positive into the specified terminal. Consult Packaging Section of Databook for thermal limitations and considerations of packages.
UC1842/3/4/5 UC2842/3/4/5 UC3842/3/4/5
CONNECTION DIAGRAMS
DIL-8, SOIC-8 (TOP VIEW)
N or J Package, 08 Package
PLCC-20 (TOP VIEW) Q Package
COMP
VFB I SENSE RT/CT
VREF
Vee OUTPUT
5 GROUND
SOIC-14 (TOP VIEW) D Package
OUTPUT e GROUND s PWR GND
La 2 1 20 19
4
18
5
17
6
16
~ 7
15
~ 8
14
9 10 11 12 13
~~~~
PACKAGE PIN FUNCTION
FUNCTION
PIN
N/C
1
COMP
2
N/C
3
N/C
4
VFB
5
N/C
6
ISENSE
7
N/C
8
N/C
9
RT/CT
10
N/C
11
PWRGND
12
GROUND
13
N/C
14
OUTPUT
15
N/C
16
Ve
17
Vee
18
N/C
19
VREF
20
5-180
UC1842/3/4/5 UC2842/3/4/5 UC3842/3/4/5
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for -55°C s TA s 125°C for the UC184X; -40°C s TA s 85°C forthe UC284X; o·c s TA" 70°C tor the 384X; Vee=
15V (Note 5); RT= 10k; CT =3.3nF, TA=TJ.
PARAMETER
Reference Section Output Voltage Line Regulation Load Regulation Temp. Stability Total Output Variation Output Noise Voltag_e Long Term Stability Output Short Circuit
Oscillator Section Initial Accuracy Voltage Stability Temp. Stability Amplitude
Error Amp Section Input Voltage Input Bias Current AVOL Unity Gain Bandwidth PSRR Output Sink Current Output Source Current VouT Hig_h VOUT Low
Current Sense Section Gain Maximum Input Signal PSRR Input Bias Current Delay to Output
TEST CONDITIONS
UC1842/3/4/5 UC2842/3/4/5
MIN TYP MAX
UC3842/3/4/5
UNITS
MIN TYP MAX
TJ = 25°C, lo = 1mA 12 s;VIN£25V 1slos20mA (Note 2) (Note 7) Line, Load, Temp. (Note 2) 1OHzsfs10kHz, TJ = 25°C(Note2) TA= 125°C, 1000Hrs. (Note 2)
4.95 4.9 -30
5.00 6 6 0.2
50 5 -100
5.05 20 25 0.4 5.1
25 -180
4.90 4.82 -30
5.00 6 6 0.2
50 5 -100
5.10 20 25 0.4 5.18
25 -180
v mV mV mvrc v -2:._V mV mA
TJ = 25°C (Note 6) 12 sVee s 25V TMIN s TA s TMAX (Note 2) VPIN 4 peak to peak (Note 2)
47
52
57
47
52
57 kHz
0.2
1
0.2
1
%
5
5
%
1.7
1.7
v
VPIN 1 =2.5V
2 sVos 4V (Note 2) TJ = 25°C 12 sVecs25V VPIN 2 = 2.7V, VPIN 1 = 1.1V VPIN 2 = 2.3V, VPIN 1 = 5V VPIN 2 = 2.3V, RL = 15k to ground VPIN 2 = 2.7V, RL = 15k to Pin 8
2.45
65 0.7 60 2 -0.5 5
2.50 -0.3 90
1 70 6 -0.8 6 0.7
2.55 -1
1.1
2.42
65 0.7 60 2 -0.5 5
2.50 -0.3 90
1 70 6 -0.8 6 0.7
2.58 -2
1.1
v µA dB MHz dB mA mA v v
(Notes 3 and 4) VPIN 1 = 5V (Note 3) 12 s Vee s 25V (Note 3) (Note 2)
VPIN 3 = 0 to 2V (Note 2)
2.85
3
3.15 2.85
3
3.15 VN
0.9
1
1.1 0.9
1
1.1
v
70
70
dB
-2
-10
-2 -10 µA
150 300
150 300 ns
Note 2: These parameters, although guaranteed, are not 100% tested in production. Note 3: Parameter measured at trip point of latch with VPtN 2 = 0. Note 4: Gain defined as
fl VPIN1 A· fl VP/NJ, 0 s VPIN3 s0.8V
Note 5: Adjust Vee above the start threshold before setting at 1511. Note 6: Output frequency equals oscillator frequency for the UC1842 and UC1843.
Output frequency is one half oscillator frequency for the UC1844 and UC1845. Note 7: Temperature stability, sometimes referred to as average temperature coefficient, is described by the equation:
Temp Stability· VREF(max) - VREF(min) TJ (max') - TJ (min)
VREF (max) and VREF (min) are the maximum and minimum reference voltages measured over the appropriate temperature range. Note that the extremes in voltage do not necessarily occur at the extremes in temperature.
5-181
UC1842/3/4/5 UC2842/3/4/5 UC3842/3/4/5
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for -55°C s TA s 125°C for the
UC184X; -40°Cs TA s 85°C for the UC284X; 0°C s TA s 70°C for the 384X; Vee= 15V (Note 5); RT= 10k; CT =3.3nF, TA=TJ.
PARAMETER
TEST CONDITION
UC1842/3/4/5 UC2842/3/4/5
MIN TVP MAX
Output Section
Output Low Level
ISINK= 20mA
0.1 0.4
ISINK = 200mA
1.5 2.2
Output High Level
!SOURCE = 20mA
13 13.5
ISOURCE = 200mA
12 13.5
Rise Time
TJ = 25°C, CL = 1nF (Note 2)
50 150
Fall Time
TJ = 25°C, CL= 1nF_{_Note 2}_
50 150
Under-voltage Lockout Section
Start Threshold
X842/4
15
16
17
X843/5
7.8 8.4 9.0
Min. Operating Voltage After Turn On
X842/4 X843/5
9
10
11
7.0 7.6 8.2
PWMSectlon
Maximum Duty Cycle
X842/3
95
97 100
X844/5
46
48
50
Minimum Duty Cycle
0
Total Standby Current
Start-Up Current
0.5
1
Operating Supply Current
VPIN 2 = VPIN 3 = OV
11
17
Vee Zener Voltage
ICC=25mA
30 34
Note 2: These parameters, although guaranteed, are not 100% tested m production.
Note 3: Parameter measured at trip point of latch with VPIN 2 = 0.
Note 4: Gain defined as:
IJ.VPIN1 A- /J, VPIN3; 0 s VPIN3 s 0.8V.
UC3842/3/4/5
UNITS
MIN TVP MAX
0.1
0.4
v
1.5 2.2
v
13 13.5
v
12 13.5
v
50 150 ns
50 150 ns
v 14.5 16 17.5
7.8 8.4 9.0
v
8.5
10 11.5
v
7.0 7.6 8.2
v
95
97 100
%
47
48
50
%
0
%
0.5
1
mA
11
17 mA
30
34
v
Note 5: Adjust Vee above the start threshold before setting at 15V. Note 6: Output frequency equals oscillator frequency for the UC1842 and UC1843.
Output frequency is one half oscillator frequency tor the UC1844 and UC1845.
ERROR AMP CONFIGURATION
2.SOV
O.SmA
Error Amp can Source or Sink up to O.SmA
5-182
UC1842/3/4/5 UC2842/3/4/5 UC3842/3/4/5
UNDER-VOLTAGE LOCKOUT
Vee
Vee
ON/OFF COMMAND
TO REST OF IC
I
I
I
I
I
UC1842 UC1843
I
UC1844 UC1845
I
I
VON
16V
8.4V
I I
VOFF
10V
7.6V
L-----------------
<17mA <1mA
VOFF
VON
During under-voltage lock-out, the output driver is biased to ground with a bleeder resistor to prevent activating the power sink minor amounts of current. Pin 6 should be shunted to switch with extraneous leakage currents.
CURRENTSENSECmcurr
Peak Current (Is) is Determined By The Formula
ISM
1.0V
AX-RS
A small RC filter may be required to suppress switch transients.
OSCILLATOR SECTION
I
y,~riR;
GR~H RT/CT
r{-L__j
~ _l_CT
____ J -
For RT> 5k f - t 72 RTCT
Deadtime vs CT (RT> 5k)
30 ~
10
~ 3
!! 0.3
..,. ~ ""0 ~
C\I C\I
,._ 0
..,. ;;!
Cr - (nF)
Timing Resistance vs Frequency 100
ea 30
I- 10
a:
3 100 1k 10k 100k 1M FREQUENCY - (Hz)
5-183
OUTPUT SATURATION CHARACTERISTICS
ERROR AMPLIFIER OPEN-LOOP FREQUENCY RESPONSE
UC1842/3/4/5 UC2842/3/4/5 UC3842/3/4/5
Vee · 15V
TA - +25'C -
TA · ·55 'C - -
1
I
c
I i
0
~ 11---+~t--t--t~+r--1-~+-~-+-tr---l
!:;
~ ol:::::o~:::::::t::r:::I~_l__l_~_l__LJ_j__l_J
.01 .02 .03 .04 .05 .07 .1 .2 .3 .4 .5 .7 1.0
Output Current, Source or Sink - (A)
OPEN-LOOP LABORATORY FIXTURE
-c
':T II>
"' .45 CD
t~ 40 f------t--1----",,,.,....o-.!:---+----1 .90 ~ ~1--~+-~--t--~--j~~-l".c~~~-j ·135
> 0
01--~+-~--t--~--j~~-+-~-"!c...__, ·180
10
100
...
10k 100k 1.1 10M
Frequency - (Hz)
VREF
4.7K 1K
ERROR AMP ADJUST
4.7K
COMP
VF a
ISENSE RT/CT
VREF Vee
OUTPUT GROUND
Vee OUTPUT
High peak currents associated with capacitive loads necessitate careful grounding techniques. liming and bypass capacitors should be connected close to pin 5 in a single point
GROUND
CT ground. The transistor and 5k potentiometer are used to sample the oscillator waveform and apply an adjustable ramp to pin3.
SHUT DOWN TECHNIQUES
COMP
L __
TO CURRENT SENSE RESISTOR
Shutdown of the UC1842 can be accomplished by two methods; either raise pin 3 above 1V or pull pin 1 below a voltage two diode drops above ground. Either method causes the output of the PWM comparator to be high (refer to block diagram). The PWM latch is reset dominant so that the output will remain low until the next clock cycle after the shutdown condition at
pin 1 and/or 3 is removed. In one example, an externally latched shutdown may be accomplished by adding an SCA which will be reset by cycling Vee below the lower UVLO threshold. At this point the reference turns off, allowing the SCA to reset.
5-184
OFFLINE FLYBACK REGULATOR
UC1842/3/4/5 UC2842/3/4/5 UC3842/3/4/5
T1
06
L1
(NOTE 2) US0945 (NOTE 2)
C1
250µF
250V R2 56K 2W
R4 4.7K
R3 20K
R12 4.7K 2W
02 1N3812
C9 3300pF 600V
NP 04 1N3613
03 1N3812
07 UFS1002
.-----;.;>t-t-C-12:----- +12V
· N12 !-"--
-
-
;
2200,uf
-1-8-v_ _
_
_
"!:
12V
COM
2 1
cs
.0114'
C6 .0022µF
C2 10,0 F
C3 R9 680
25V 22,<.F 3W
R7 220
USD1120
R13 20K
Q1 UFN833
R10 0.550 1W
UES1002
C8
680pF 800V
05 1N3813
R11 2.7K
2W
Power Supply Specifications
1. Input Voltage
95VAC to 130VA
2. Line Isolation 3. Switching Frequency 4. Efficiency @ Full Load
(50 Hz/60Hz) 3750V 40kHz 70%
5. Output Voltage: A. +5V, ±5%; 1A to 4A load Ripple voltage: 50mV P-P Max
B. +12V, ±3%; 0.1 A to 0.3A load Ripple voltage: 1OOmV P-P Max
C. -12V ,±3%; 0.1Ato 0.3Aload Ripple voltage: 1OOmV P-P Max
SLOPE COMPENSATION
RT/CT
UC1842/3
-J-0.1µF
J-c
~
n n J ISENSE
RSENSE
A fraction of the oscillator ramp can be resistively summed with the current sense signal to provide slope compensation for converters requiring duty cycles over 50%.
Note that capacitor, CT forms a filter with R2 to suppress the leading edge switch spikes.
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. · '-ERRIMACK. NH 03054 TEL (603) 424-2410 · FAX (603) 424·3460
5-185
n nINTEGR.ATED
~CIRCUITS
-UNITROOE
Current Mode PWM Controller
UC1842A/3A/4A/5A UC2842A/3A/4A/5A UC3842A/3A/4A/5A
FEATURES Optimized for Off.line and DC to DC Converters
Low Start Up Current (<0.5mA)
Trimmed Oscillator Discharge Current
Automatic Feed Forward Compensation
Pulse-by-Pulse Current Limiting
Enhanced Load Response Characteristics
DESCRIPTION The UC1842A/3A/4A/5A family of control ICs is a pin for pin compatible improved version of the UC3842/3/4/5 family. Providing the necessary features to control current mode switched mode power supplies, this family has the following improved features. Start up current is guaranteed to be less than 0.5mA. Oscillator discharge is trimmed to 8.3mA. During under voltage lockout, the output stage can sink at least 1OmA at less than 1.2V for Vee over 5V.
The difference between members of this family are shown in the table below.
Under-Voltage Lockout With Hysteresis
Double Pulse Suppression High Current Totem Pole Output Internally Trimmed Bandgap Reference 500kHz Operation Low Ro Error Amp
Part#
UC1842A UC1843A UC1844A UC1845A
UVLOOn
16.0V 8.5V 16.0V 8.5V
UVLOOff
10.0V 7.9V 10.0V 7.9V
Maximum Duty Cycle
<100% <100% <50% <50%
BLOCK DIAGRAM
VFe Comp
C/S
Note 1:!NBI A= DIL-8 Pin Number. B = S0-14 Pin Number. Note 2: Toggle flip flop used only in 1844A and 1845A. 6/93
5-186
PWM Latch
Pwr
Ground
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage (Low Impedance Source) .............. 30V Supply Voltage (Ice mA)..................... Self Limiting Output Current ................................... ±1A Output Energy (Capacitive Load) ..................... 5µJ Analog Inputs (Pins 2, 3) . . . . . . . . . . . . . . . . . . -0.3V to +6.3V Error Amp Output Sink Current .................... 10mA Power Dissipation atTA "'25°C (DIL-8) ................ 1W Storage Temperature Range . . . . . . . . . . . . . -65°C to +150°C Lead Temperature (Soldering, 10 Seconds) .......... 300°C Note 1. All voltages are with respect to Ground, Pin 5. Currents are positive into, negative out of the specified terminal. Consult Packaging Section of Databook for thermal limitations and considerations ofpackages. Pin numbers refer to DIL package only.
SOIC-14 (TOP VIEW) D Package
UC1842A/3A/4A/5A UC2842A/3A/4A/5A UC3842A/3A/4A/5A
CONNECTION DIAGRAMS
DIL-8; SOIC-8 (TOP VIEW) J or N, 08 Package
i--v--1
Comp [ I
~ VREF
VFB ~
~Vee
ISENSE [ I
~Output
RT /CT [ I
~ Gnd
PLCC-20, LCC-20 (TOPVIEW) Q, L Packages
L3 2 1 20 19
4
18~
5
17
6
16
7
15~
8
14
9 10 11 12 13
PACKAGE PIN FUNCTION
FUNCTION
PIN
NL_C
1
Com_Q_
2
N_L_C
3-4
VFB
5
NLC
6
I SENSE
7
N_LC
8-9
RTLCT
10
N_LC
11
PwrGnd
12
Gnd
13
N_LC
14
Ou_!Q_ut
15
N_LC
16
Ve
17
Vee
18
N_LC
19
VREF
20
ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply for -55°C :s TA"' 125°C for the
o uc184xA; -40°C :s TA"' 85°C for the UC284xA; "'TA"' 10°c tor the UC384xA; Vee=
15V (Note 5); RT= 10k; CT= 3.3nF; TA= TJ; Pin numbers refer to DIL-8.
PARAMETER
TEST CONDITIONS
UC184xA\UC284xA
UC384xA
UNITS
MIN. TYP. MAX. MIN. TYP. MAX.
Reference Section Output Voltage
TJ = 25°C, lo= lmA
4.95 5.00 5.05 4.90 5.00 5.10 v
Line Regulation
12 :<VIN :<25V
6
20
6
20 mV
Load Regulation
1 "'lo :<20mA
6
25
6
25 mV
Temp. Stability Total Output Variation
(Note 2, Note 7) Line, Load, Temp.
0.2 0.4
0.2 0.4 mV/°C
4.9
5.1 4.82
5.18 v
Output Noise Voltage
10Hz "'f"' 10kHz TJ = 25°C (Note 2)
50
50
µV
Long Term Stability
TA= 125°C, 1000Hrs. (Note 2)
5
25
5
25 mV
Output Short Circuit
-30 -100 -180 -30 -100 -180 mA
Oscillator Section
Initial Accuracy
TJ = 25°C (Note 6)
47
52
57
47 52
57 kHz
Voltage Stability
12:<Vcc :<25V
0.2
1
0.2
1
%
Temp. Stability AmJ>!itude Discharge Current
TMIN "'TA"' TMAX (Note 2) VPIN 4 peak to_E_eak (Note 2) TJ = 25°C, VPIN 4 = 2V
5
5
%
1.7
1.7
v
7.8 8.3 8.8 7.8 8.3 8.8 mA
5-187
UC1842A/3A/4A/5A
UC2842A/3A/4A/5A
UC3842A/3A/4A/5A
ELECTRICAL
Unless otherwise stated, these specifications apply for -55°C s TA s 125°C for the UC184xA;
o CHARACTERISTICS (cont.) -40°C s TA s 85°C for the UC284xA; s TA s 70°C for the UC384xA; Vee= 15V (Note 5); RT=
10k; CT= 3.3nF; TA= TJ; Pin numbers refer to DIL-8.
PARAMETER
TEST CONDITIONS
UC184xA\UC284xA
UC384xA
UNITS
MIN. TYP. MAX. MIN. TYP. MAX.
VPIN4 = 2V
7.5
8.8 7.6
8.8 mA
Error Amp Section Input Voltage
VPIN 1=2.5V
v 2.45 2.50 2.55 2.42 2.50 2.58
Input Bias Current
-0.3 -1
-0.3 -2
µA
AVOL
2 sVo s 4V
65
90
65
90
dB
Unity Gain Bandwidth
TJ = 25°C (Note 2)
0.7
1
0.7
1
MHz
PSRR
12 sVcc s 25V
60
70
60
70
dB
Output Sink Current
VPIN 2 = 2.7V, VPIN 1 = 1.1V
2
6
2
6
mA
Output Source Current VouTHigh VouTLow
VPIN 2 = 2.3V, VPIN 1 = 5V
-0.5 -0.8
-0.5 -0.8
mA
VPIN 2 = 2.3V, AL = 15k to ground
5
6
5
6
v
VPIN 2 = 2.7V, AL= 15k to Pin 8
0.7 1.1
0.7 1.1
v
Current Sense Section
Gain Maximum Input Signal
(Note 3, Note 4) VPIN 1 = 5V (Note 3)
2.85 3 3.15 2.85 3 3.15 VN
0.9
1
1.1 0.9
1
1.1
v
PSRR
12 s Vee s 25V (Note 3)
70
70
dB
Input Bias Current
-2
-10
-2 -10 µA
Del~to Output
VPIN 3 = 0 to 2V~ote 21
150 300
150 300 ns
Output Section Output Low Level
Output High Level
!SINK= 20mA ISINK = 200mA !SOURCE = 20mA !SOURCE = 200mA
0.1 0.4
0.1
0.4
v
15 2.2
15 2.2
v
13 13.5
13 13.5
v
12 13.5
12 13.5
v
Rise Time
TJ = 25°C, CL = 1nF (Note 2)
50 150
50 150 ns
Fall Time UVLO Saturation
TJ = 25°C, CL= 1nF (Note 2) Vee = 5V, ISINK = 10mA
50 150 0.7 1.2
50 150 ns
0.7 1.2
v
Under-Voltage Lockout Section Start Threshold
Min. Operation Voltage After Turn On
x842N4A x843N5A x842N4A x843N5A
15
16
v 17 14.5 16 17.5
7.8 8.4 9.0 7.8 8.4 9.0
v
9
10
11
v 8.5 10 11.5
7.0 7.6 8.2 7.0 7.6 8.2
v
PWM Section
Maximum Duty Cycle
x842N3A
94
96 100 94
96 100 %
x844N5A
47
48
50
47
48
50
%
Minimum Duty Cycle
0
0
%
Total Standby Current
Start-Up Current
0.3 0.5
0.3 0.5 mA
Operating Supply Current
VPIN 2 = VPIN 3 = OV
Note 2: These parameters, although guaranteed, are not 100%
tested in production. Note 3: Parameter measured at trip point of latch with VPIN2 = 0.
.
!!.VP/NI
Note 4: Gain defined as: A - I!. VPIN 3 ; 0 s VPIN 3 s O.BV.
Note 5: Adjust Vee above the start threshold before setting at 15\f.
Note 6: Output frequency equals oscillator frequency for the UC1842A and UC1843A. Output frequency is one half
11
17
11
17 mA
oscillator frequency for the UC1844A and UC1845A.
Note 7: "Temperature stability, sometimes referred to as aver-
age temperature coefficient, is described by the equa-
tion:
s 7i
b'/' VREF(m~ - VREF(min)
emp ta llty- TJ(msX)- TJ(min) ·
VREF (max) and VREF (min) are the maximum & minimum reference voltage measured over the appropriate temperature range. Note that the extremes in voltage
5-188
2.SOV
UC1842A/3A/4A/5A UC2842A/3A/4A/5A UC3842A/3A/4A/5A
O.SmA
Error Amp can Source and Sink up to 0.5mA, and Sink up to 2mA.
Under-Volta e Lockout
Vee
ON/OFF COMMAND
TO REST OF IC
I
I
I
I
I
UC1842A UC1843A
I
UC1844A UC1845A
I
I
VON
16V
8.4V
I I
VOFF
10V
7.SV
L-----------------
Ice
<17mA +-
VOFF
VON
During UVLO, the Output is low.
Current Sense Circuit
Peak Current (Is) is Determined By The Formula
I
SMAX-
1.0V Rs
A small RC filter may be required to suppress switch transients.
5-189
APPLICATIONS DATA (cont.)
Output Saturation Characteristics
UC1842A/3A/4A/5A UC2842A/3A/4A/5A UC3842A/3A/4A/5A
Error AmplHier Open-Loop Frequency Response
Output Current, Source or Sink - (A)
~ 80 t--.;;;:--t-------t---t----t---t-----j 0 "'II
! : : : : i ' 80
~~
-45 ::
~ .~5 40f----+---+-_:::,,,.,....::----:!:c---+--~-~
i _ __, Q)
~¢
20 t----+---+-----cr-A--v-1-_,r...,~-_.....~
-135
> o r---+----+---+-----t-~'l<Gc'-__, -180
10
100
...
10k 100k 'f.I 10M
Frequency - (Hz)
Oscillator Section
I
V~hRT
-$-_r RT/CTH
____ J -=--
For RT> 5k f- t 72 RTCT
Oscillator Frequency vs TI ming Resistance
Maximum Duty Cycle vs llming Resistor
100.0
~ 80.0
u.Q.). ...0
60.0
:;
Q
"E 40.0
·E;;
"':Ii 20.0 [!
.....,
t 12
7_
300 1.00k 3.00k 10.0k 30.0k 100k RT (ohms)
300 1.00k 3.00k 10.0k 30.0k 100k RT (ohms)
Open-Loop Laboratory Test Fixture
VREF
Vee
4.7k 1k
ERROR AMP ADJUST
VFB
VREF Vee
4.7k
-
ISENSE OUTPUT
-RT-/C-T --G-R-OU-N-D
OUTPUT GROUND
CT
High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypass capacitors should be connected close to pin 5 in a single point
ground. The transistor and 5k potentiometer are used to sample the oscillator waveform and apply an adjustable ramp to pin3.
5-190
APPLICATIONS DATA (cont.) Off-line Flyback Regulator
C1 250µF 250V
R4
R3
4.7k
20k
R2 56K 2W
C5 .01µF
UC1842A/3A/4A/5A UC2842A/3A/4A/5A UC3842A/3A/4A/5A
R12 4.7k 2W
02 1N3612
R7 22n
1k RB C7 470pF
T1
06
L1
(NOTE 2) USD945 (NOTE 2)
co
3300pF 600V
NP 04 1N3613
03 1N3612
NC
+SV
NS C10 4700µF 10V
C11
4700µF 10V
COM
07
UFS1002
..---1:::.1-...------ +12V C12
l"·._N_1_ 2 _ _~12=2-060Vµ'F----! 12V COM
N12
C13
2200µF
08 16V
_ _ _ _ ·12V ~-__..-,_...._
UES1002
01 UFN633
CB 6BOpF 600V
R13
RIO 0.550
20k
1W
05 1N3613
R11 2.7k 2W
Power Supply Specifications
1. Input Voltage
2. Line Isolation 3. Switching Frequency 4. Efficiency @ Full Load
95VAC to 130VA (50 Hz/60Hz) 3750V 40kHz 70%
5. Output Voltage: A. +5V, ±5%; 1A to 4A load
Ripple voltage: 50mV P-P Max B. +12V, ±3%; 0.1 A to 0.3A load
Ripple voltage: 1OOmV P-P Max C. -12V ,±3%; 0.1Ato 0.3Aload
Ripple voltage: 1OOmV P-P Max
Slope Compensation
.I_0.1µF
~c
I
! ~
R2
!SENSE
A fraction of the oscillator ramp can be resistively
summed with the current sense signal to provide slope compensation for converters requiring duty cycles over 50%. Note that capacitor, C, forms a filter with R2 to suppress the leading edge switch spikes.
l1n_
RSENSE
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. · MERRIMAC~ NH 03054 TEL. (603) 424·2410 · FAX (603)424-3400
5-191
n n L!:::::'.J
INTEGRATED CIRCUITS
-uNITRCOE
Current Mode PWM Controller
UC1846/7 UC2846/7 UC3846/7
FEATURES Automatic Feed Forward Compensation
Programmable Pulse-by-Pulse Current Limiting
Automatic Symmetry Correction in Push-pull Configuration
Enhanced Load Response Characteristics
Parallel Operation Capability for Modular Power Systems
Differential Current Sense Amplifier with Wide Common Mode Range
Double Pulse Suppression
500mA (Peak} Totem-pole Outputs
±1 % Bandgap Reference
DESCRIPTION The UC1846/7 family of control ICs provides all of the necessary features to implement fixed frequency, current mode control schemes while maintaining a minimum external parts count. The superior performance of this technique can be measured in improved line regulation, enhanced load response characteristics, and a simpler, easier-to-design control loop. Topological advantages include inherent pulse-by-pulse current limiting capability, automatic symmetry correction for push-pull converters, and the ability to parallel "power modules" while maintaining equal current sharing.
Protection circuitry includes built-in under-voltage lockout and programmable current limit in addition to soft start capability. A shutdown function is also available which can initiate either a complete shutdown with automatic restart or latch the supply off.
Other features include fully latched operation, double pulse suppression, deadline adjust capability, and a ±1% trimmed bandgap reference.
Under-voltage Lockout Soft Start Capability
The UC1846 features low outputs in the OFF state, while the UC1847 features high outputs in the OFF state.
Shutdown Terminal
500kHZ Operation
BLOCK DIAGRAM
5.1V
Reference 1 - - - - - - - - - - - - - 1 Regulator
2/93
. - - - + - - - ; - - - - - - - - - - - 1 1 1 1 Current Limit
Adjust
5-192
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage (Pin 15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +40V Collector Supply Voltage (Pin 13).................................. +40V Output Current, Source or Sink (Pins 11, 14)........................ 500mA Analog Inputs (Pins 3, 4, 5, 6, 16) ........................... -0.3V to +V1N Reference Output Current (Pin 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -30mA Sync Output Current (Pin 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5mA Error Amplifier Output Current (Pin 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5mA Soft Start Sink Current (Pin 1) .................................... 50mA Oscillator Charging Current (Pin 9) ................................. 5mA Power Dissipation atTA=25°C ................................. 1000mW Power Dissipation at Tc=25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000mW Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C Lead Temperature (soldering, 10 seconds......................... +300°C
Note 1. All voffages are with respect to Ground, Pin 13. Currents are positive into, negative out of the speficied terminal. Consult Packaging Section of Databook for thermal limitations and considerations of packages. Pin numbers refer to OIL and SO/C packages only.
CONNECTION DIAGRAMS
DIL-16, SOIC-16 (TOPVIEW) J or N Package, DW Package
PLCC-20, LCC-20 (TOPVIEW) Q, L Packages
E/A-
B Out
L3 2 1 2019
4
18
5
17~
6
16
7
15
8
14~
9 10 11 12 13
UC1846(l UC2846(l UC3846(l
PACKAGE PIN FUNCTION
FUNCTION
PIN
Nl_C
1
C.LL SS
2
VREF
3
QLS-
4
QJ._S+
5
"ll..C
6
J;.LA+
7
£JP.-
8
Corml._
9
CT
10
"ll..C
11
RT
12
$'inc
13
A Out
14
Gnd
15
"li..C
16
Ve
17
B Out
18
VIN
19
Shutdown
20
ELECTRICAL CHARACTERISTICS (Unless otherwise stated, these specifications apply for TA=-55°C to +125°C for
UC1846/7;-40°C to +85°C for the UC2846/7; and 0°C to +70°C for the UC3846(7; VIN=15V, RT=10k, CT=4.7nF, TA=TJ.)
PARAMElER
TEST CONDITIONS
Reference Section
Output Voltage
TJ=25°C, lo=1 mA
Line Regulation
VIN=8V to 40V
Load Regulation
IL=1 mA to 1OmA
Temperature Stability
Over Operating Range, (Note 2)
Total Output Variation
Line, Load, and Temperature (Note 2)
Output Noise Voltage
10Hzs f s10kHz, TJ=25°C (Note 2)
LOl1!1Term Stability
TJ=125°C, 1000 Hrs. (Note 2)
Short Circuit Output Current VREF:OV
UC1846/UC1847 UC2846/UC2847 MIN. TYP. MAX.
UC3846/UC3847 MIN. TYP. MAX. UNITS
5.05 5.00 -10
5.10 5 3 0.4
100 5 -45
5.15 20 15
5.20
5.00 4.95 -10
5.10 5 3 0.4
100 5
-45
5.20 20 15
5.25
v
mV mV
mV/°C
v
µV mV mA
5-193
UC1846/7 UC2846/7 UC3846/7
ELECTRICAL
(Unless otherwise stated, these specifications apply for TA=-55°C to +125°C for UC1846/7; -40°C
CHARACTERISTICS (cont.) to +85°C for the UC2846/7; and 0°C to +70°C for the UC3846/7; VIN=15V, Rr=10k, Cr=4.7nF,
TA=TJ.)
PARAMETER
TEST CONDITIONS
Osclllator Section
Initial Accuracy
TJ=25°C
Voltage Stability
VIN=8V to 40V
Temperature Stability
Over Operating Range (Note 2)
Sync O~ut High Level
Sync Output Low Level
Sync Input High Level
Pin8=0V
Sync ln_l)_ut Low Level
Pin8=0V
Sync Input Current
Sync Voltage=3.9V, Pin 8=0V
Error Amp Section
Input Offset Voltage
Input Bias Current
Input Offset Current
Common Mode Range
VIN=8V to 40V
Open Loop Voltage Gain !1Vo=1.2 to 3V, VCM=2V
Unity Gain Bandwidth
TJ=25°C (Note~
CMRR
VcM=OVto 38V, V1N=40V
PSRR
VIN=8V to 40V
Output Sink Current
VID=-15mV to -5V, VPIN 7=1.2V
Output Source Current
VID=15mV to 5V, VPIN 7=2.5V
High Level Output Voltage RL=(Pin 7) 15kQ
Low Level Output Voltage
Current Sense Ampllfler Section
Am...£1ifier Gain
VPIN 3=0V, Pin 1 ~enJ_Notes 3 & 4)
Maximum Differential Input Pin 1 Open (Note 3)
Signal (VPIN 4-VP1N 3)
AL (Pin 7)=15kW
Input Offset Voltage
VPIN 1=0.5V, Pin 7 Open (Note 3)
CMRR
VcM=1V to 12V
PSRR
VIN=8V to 40V
Input Bias Current
VPIN 1=0.5V, Pin 7 Open (Note 3)
Input Offset Current
VPIN 1=0.5V, Pin 7 Open (Note 3)
Input Common Mode Rai:!9.e
Delay to Outputs
TJ=25°C, (Note 2)
Current Umit Adjust Section
Current Lim it Offset
VPIN3=0V, VPIN4=0V, Pin 7 Open
(Note3)
Input Bias Current
VPIN 5=VREF, VPIN 6=0V
Shutdown Terminal Section
Threshold Voltage
l"!!>_utVoltag_e Ran_g_e
Minimum Latching Current (Note6)
(IPIN1)
UC1846/UC1847 UC2846/UC2847 MIN. TYP. MAX.
UC3846/UC3847 MIN. TYP. MAX. UNITS
39
43
47
39
43
47 kHz
-1
2
-1
2
%
-1
-1
%
3.9 4.35
3.9 4.35
v
2.3 2.5
2.3 2.5
v
3.9
3.9
v
2.5
2.5 v
1.3 1.5
1.3 1.5 mA
0.5
5
0.5
10
mV
-0.6 -1
-0.6 -2
µA
40 250
40 250 nA
0
VIN-2V 0
v VIN-2V
80 105
80 105
dB
0.7 1.0
0.7
1.0
MHz
75 100
75 100
dB
80 105
80 105
dB
2
6
2
6
mA
-0.4 -0.5
-0.4 -0.5
mA
4.3 4.6
4.3 4.6
v
0.7
1
0.7
1
v
2.5 2.75 3.0 2.5 2.75 3.0
v
1.1 1.2
1.1 1.2
v
5
25
5
25 mV
60 83
60 83
dB
60
84
60
84
dB
-2.5 -10
-2.5 -10 µA
0.08 1
0.08 1
µA
0
VIN-3 0
v VIN-3
200 500
200 500 ns
0.45 0.5 0.55 0.45 0.5 0.55
v
-10 -30
-10 -30 µA
250 350 400 250 350 400 mV
0
VIN
0
VIN v
3.0 1.5
3.0 1.5
mA
5-194
UC1846/7
UC2846/7
UC3846/7
ELECTRICAL
(Unless otherwise stated, these specifications apply for TA=-55°C to +125°C for UC1846/7; -40°C
CHARACTERISTICS (cont.) to +85°C for the UC2846/7; and 0°C to +70°C for the UC3846/7; VIN=15V, Rr=1 Ok, CT=4.7nF,
TA=TJ.)
PARAMETER
TEST CONDITIONS
UC1846/UC1847 UC2846/UC2847
UC3846/UC3847
MIN. TYP. MAX. MIN. TYP. MAX. UNITS
Shutdown Tennlnal Section (cont.)
Maximum Non-Latching
(Note 7)
CurrentJ!PIN 1) Delay_to OIJtilll_ts
TJ=25°CJ_Note :11_
1.5 0.8 300 600
1.5 0.8 mA
300 600 ns
Output Section Collector-Emitter Voltage Collector Leak~e Current Output Low Level
Output High Level
Rise Time Fall Time
Vc=40V (Note 5) ISINK=20mA ISINK=100mA ISOURCE=20mA ISOURCE=1 OOmA
CL=1nF, TJ=25°CJ_Note :11_
CL=1nF, TJ=25°C (Note 2)
40
40
v
200
200 µA
0.1 0.4
0.1
0.4
v
0.4 2.1
0.4 2.1
v
13 13.5
13 13.5
v
12 13.5
12 13.5
v
50 300
50 300 ns
50 300
50 300 ns
Under-Voltege Lockout Section Start-Up Threshold Threshold Hysteresis
7.7 8.0 0.75
7.7 8.0
v
0.75
v
Total Standby Current
Supply Current
17 21
17
21
mA
Note 2. These parameters, although guaranteed over the recommended operating conditions, are not 100% tested in production.
= = Note 3. Parameter measured at trip point of latch with VPIN s VREF, VPIN 6 011.
Note4. Amplifier gain defined as: G- A ViVPIN?; A VPIN4 - 0 to 1.0V. A PIN4
Note 5. Applies to UC1846/UC2846/UC3846 only due to polarity of outputs. Note 6. Current into Pin 1 guaranteed to latch circuit in shutdown state. Note 7. Current into Pin 1 guaranteed not to latch circuit in shutdown state.
APPLICATIONS DATA
Oscillator Circuit
V V Sawtooth . / ' \ . / ' \ / (Pina)/
RT
Oac
n
n
(Pin 10) __j L__j l _ _
__, ~
Output Deadtlme (td)
Sync
Output deadtime is determined by the external capacitor, CT, according to the formula: "td (µs) - 145Cr (µf) [
1~-6 ) .
12- RT(kO)
For large values of RT: "td (µs) - 145Cr (µf).
Oscillator frequency is approximated by the formula: fr (kHi) - RT (kQ~~2Cr (µf)
5-195
APPLICATIONS DATA (cont.) Error Amp Output Configuration
VREF
VREF
I 0.5mA
7 Comp
Error Amplifier can source up to 0.5mA.
UC1846/7 UC2846/7 UC3846/7
Error Amp Gain and Phase vs Frequency
! -.;;;:: 80 -.;;;::
VIN·20V TJ·25°C
z
~ 60
w
CJ ~ 40
...J
0 > ~ 20
0
-! 0
iii
Q.
0
['\
r"1
~
lS
~ m z
o0,l-,
N K K
3!
>
oo "m'
't......
-90° -180°
100 1k 10k 100k 1M
FREQUENCY (Hz)
Error Amp Open-Logic D.C. Gain vs Load Resistance
- 110
~
VIN·20V
z
TJ·25°C
~ 100
w
V1
<CJ
~ 90 0
v_%
+ >
gQ. 80
....
r
l I
hl· I-I--
if;
~ 70
TT ~ "'?"
0 10 20 30 40 50 80 70 80 90 100
OUTPUT LOAO RESISTANCE, RL (k-OHMS)
Parallel Operation
9 RT
MASTER
CT
RT
VREF E/A+ Sync Comp E/A-
I
2
10
7
VOUT
Output Filters
2
10
7
VREF E/A+ 8 CT
Sync
Comp E/A-
9 RT
SLAVE (Additional Units)
_I_
Slaving allows parallel operation of two or more units with equal current sharing.
5-196
APPLICATIONS DATA (cont.)
Is (+)4
Pulse by Pulse Current Limiting
I SENSE
VREF
I
I
I
R1
I
1 Current
I
Limit
Ra
IL----~- ---~~-------
7
R2 VREF -O.S Peak Cu"6flt (Is) is determined by the formula: Is - Ri +; s
Soft Start and Shutdown JReetart Functions
VREF
UC1846/7 UC2846/7 UC3846/7
1 I Currant
Limit
I I I I I I I I
16 1 Shutdown
I I IL _-=_==-_35_0m_V ________ _
Currant Limit
(Pin 1)
o.5v---
Shutdown With Auto-Restart
Shutdown Without Auto-Restart
~-:\~----
o
Shutdown (Pin 16)
o~~---i,_____~n~---------1 \'--~n~----
PWM
v~;F < O.BmA
11 v~;F < O.BmA, the shutdown latch will commutate when
Isa - o.BmA and a restart cycle will be Initiated.
s-flSL-v~;F > 3mA (Latched Off)
If V~;F > 3mA, the device will
latch off until power Is recycled.
5-197
APPLICATIONS DATA (cont.)
Is~ R c
Current Sense Amp Connection 3
UC1846/7 UC2846/7 UC3846/7
IL ____ _
A small RC filter may be required in some applications to reduce switch transients. Differential input allows remote, noise free sensing.
UC1846 Open Loop Test Circuit
Timing Resisto,_r_ _ _ _ _~
Max
Freq. Set & Duty Cycle RT
'
>-------------<
9
2 >---------< ·VREF (+5V Output)
.::J:::. 0.1µF
Sawtooth
Timing
Cap CT 0------------l 8
+12 151---------oVIN (+12V)
.::J:::. 0.1 µF 10 1---------oSync
I SENSE Adjust (""=1V PK)
Current Limit Adjust
t··:h,.dowo
+---+Is-+---------14 UC1846
7
13 ,___ _ _ _ _ _+1_2-c ,_ _ _ _......,,. (+12V)
+5V
Inv
6
Duty Cycle
Adjust
+5V
"'.:~
10 T u r i
0.1 µF .::J:::. IL Adj
.::J:::.1 µF
Out A _f1_
141---------o 150'1
Out B 111---------0
150'1
Gnd
121---------0--~
3 1---------uls+
X Ground tor Normal Operation
-Bypass Caps Should Be Low ESR & ESL Type -Short Pins 6 & 7 for Unity Gain Testing
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL Bl.VD. · MERRIMACK, NH 00054 TEL (603) 424·2410 · FAX (603)424-3480
5-198
n nINTEGRATED
~CIRCUITS
-UNITROOE
Average Current Mode PWM Controller
~#~>U\· .·..·..· ·.·.··_.·.· ~··.i R
~···········~
FEATURES Practical Primary Side Control of Isolated Power Supplies with DC Control of Secondary Side Current
Accurate Programmable Maximum Duty Cycle Clamp
BLOCK DIAGRAM
c1111co11--~~-+....;_~~~~~
.J,,- ----- IOFF [ill Current 1.1V
:;io.
Error Amp
IOFF
Maximum Volt-Second-Product Clamp to Prevent Core Saturation
Practical Operation Up to 1MHz
High Current (2A Pk) Totem Pole Output Driver
Wide Bandwidth (8MHz) Current Error Amplifier
Under Voltage Lockout Monitors VCC, VIN and VREF
Output Active Low During UVLO
Low Start-up Current (500µA)
Precision 5V Reference (1 %)
UC1848 UC2848 UC3848
PRELIMINARY
DESCRIPTION
UDG-93003
The UC1848 family of PWM control ICs makes primary faces with an opto-isolator from a secondary side voltage
side average current mode control practical for isolated sensing circuit.
switching converters. Average current mode control insures that both cycle by cycle peak switch current and maximum average inductor current is well defined and will not run away in a short circuit situation. The UC1848 can be used to control a wide variety of converter topologies.
A full featured Under Voltage Lockout (UVLO) circuit is contained in the UC1848. UVLO monitors the supply voltage to the controller (VCC), the reference voltage (VREF), and the input line voltage (VIN). All three must be good before soft start commences. If either VCC or VIN is
In addition to the basic functions required for pulse width low, the supply current required by the chip is only 500µA
modulation, the UC1848 implements a patented tech- and the output is actively held low.
nique of sensing secondary current in an isolated buck derived converter from the primary side. A Current Waveform Synthesizer monitors switch current and simulates the inductor current down slope so that the complete current waveform can be constructed on the primary side without actual secondary side measurement. This information on the primary side allows for full DC control of output current.
The UC1848 circuitry includes a precision reference, a wide bandwidth Error Amplifier for average current control, an Oscillator to generate the system clock, latching PWM comparator and logic circuits, and a high current Output Driver. The Current Error Amplifier easily inter-
Two on board protection features set controlled limits to prevent transformer core saturation. Input voltage is monitored and pulse width is constrained to limit the maximum volt-second-product applied to the transformer. A unique patented technique limits maximum duty cycle within 3% of a user programmed value.
These two features allow for more optimal use of transformers and switches, resulting in reduced system size and cost.
Both patents embodied in the UC1848 belong to Lambda Electronics Incorporated and are licensed for use in applications employing these devices.
6/93
5-199
ABSOLUTE MAXIMUM RATINGS Supply Voltage (Pin 15) ............................ 2'2>I
Output Current, Source or Sink (Pin 14) DC ..........................·.............. 0.5A Pulse (0.5µs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2A
Power Ground to Ground (Pin 1 to Pin 13) . . . . . . . . . . . ±0.2V Analog Input Voltages
(Pins3,4,7,8,12,16) ..................... -0.3to7V Analog Input Currents, Source or Sink
(Pins3, 4, 7, 8, 11, 12, 16) ...................... 1mA
UC1848 UC2848 UC3848
Analog Output Currents, Source or Sink (Pins 5 & 10) . . . 5mA Power Dissipation atTA = 60°C .........................1W Storage Temperature Range. . . . . . . . . . . . . . . -65°C to +150°C Lead Temperature (Soldering 10 seconds) .......... +300°C Notes: All voltages are with respect to ground {DIL and SOIC
pin 1). Cu"ents are positive into the specified terminal. Pin numbers refer to the 16 pin DIL and SOIC packages. Consult Packaging Section of Databook for thermal limitations and considerations ofpackages.
CONNECTION DIAGRAMS
DIL-16, .SOIC-16 (Top View) J or N, OW Packages
PLCC-20 & LCC-20 (Top View) Q&LPackage
L3 2 1 2019
4
18
~ 5
17
6
16
7
15
8
14
9 10 11 12 13
PACKAGE PIN FUNCTION
FUNCTION
PIN
NJQ:
1
GND
2
VREF
3
NI
4
INV
5
N}C
6
CAO
7
CT
8
vs
9
DMAX
10
NZ:c
11
CDC
12
Cl
13
IOFF
14
ION
15
~c
16
PGND
17
OUT
18
vcc
19
UV
20
ELECTRICAL CHARACTERISTICS Unless otherwise stated, all specifications are over the junction temperature range of
-ss·c to +125·c for the uc1848, -40°C to +85°C for the UC2848, and o·c to +10°c for the UC3848. Test conditions are: VCC = 12V, CT= 400pF, Cl= 100pF, IOFF = 100µA, CDC= 100nF, Cvs = 100pF, and lllS = 400µA, TA= TJ.
PARAMETER
TEST CONDrTIONS
MIN lYP MAX UNITS
Real Time Current Waveform ~theslzer
Ion AmpHfler
Offset Volta..9_e
Slew Rate (Note !l
0.95 1 1.05 v
20 25
V/!JS
lib
2
15 µA
IOFF Current Mirror
ll!))llt Voltage Current Gain
0.95 1 1.05 v
0.9
1
1.1 NA
Current Error Amplifier
AVOl.
60 80
dB
Vio
12V :s VCC :s 20V, OV :s VCM :s 5V
10 mV
lib
0.5
3 ~
Voh
lo=-200µA
3
3.3
v
Vol
lo=200µA
0.3 0.6
v
Source Current
VO= 1V
1.4 1.6 2.0 mA
GBWProduct
f =200kHz
5
8
MHz
Slew Rate (Note 1)
8
10
V/!JS
Note 1: Guaranteed by design, but not 100% tested in production.
5-200
UC1848
UC2848
UC3848
ELECTRICAL
Unless otherwise stated, all specifications are over the junction temperature range of -55°C
CHARACTERISTICS (cont.): to +125°C for the uc1848, -40°C to +85°C for the UC2848, and o·c to +1o·c for the
UC3848. Test conditions are: VCC = 12V, CT= 400pF, Cl = 1OOpF, IOFF = 100µA, CDC=
100nF, Cvs = 100pF, and lvs = 400µA, TA= TJ.
PARAMETER
TEST CONDITIONS
MIN TVP MAX UNITS
Osclllator
Frequency
TA= 25°C
240 250 260 kHz
Ramp_ Am_Qlitude
225
275 kHz
1.6 1.8 2.0
v
Duty~cle Clam_.e._
MaxDuty~le
V(DMAX) = 0.75 · VREF
72
75
78
%
Volt Second Clam_.e_
Max On Time
900
1100 ns
VCC Com_.e._arator Turn-on Threshold Turn-off Threshold
~teresls
13
14
v
9
10
v
2.5
3
3.5
v
UV Co"!e._arator Turn-on Threshold RHYSTERESIS
Vuv=4.2V
4.3 4.5 4.7
v
n
90 103 kQ
Reference VREF
TA= 25°C 0 <lo <10mA, 12 < VCC < 20
v 4.95 5 5.05
4.93
5.07 v
Line R~ulation
12<Vcc < 20V
2
10 mV
Load Regulation
0<IO<10mA
3
15 mV
Short Circuit Current
VREF =OV
30 50 70 mA
Outj)ut Stage
Rise & Fall Time (Note 1_l
Output Low Saturation
O~t H.!9_h Saturation UVLO Output Low Saturation
Cl= 1nF lo=20mA lo=200mA lo=-200mA lo=20mA
20 45 ns
0.25 0.4
v
1.2 2.2
v
2.0 3.0
v
0.8 1.2
v
Ice
ISTART
VCC= 12V
0.3 0.5 mA
IceJpre-stai:!l_
VCC = 15V, V(UV) = 0
0.5
1
mA
Ice (run)
22 27 mA
Note 1: Guarant88d by design, but not 100% tested in production.
UNDER VOLTAGE LOCKOUT The Under Voltage Lockout block diagram is shown in Figure 1. The VCC comparator monitors chip supply volt-
ov age. Hysteretic thresholds are set at 13V and 1 to
facilitate off-line applications. If the VCC comparator is low, ICC is low (500µA) and the output is low.
The UV comparator monitors input line voltage (V1N). A pair of resistors divides the input line to UV: Hysteretic input line thresholds are programmed by Rv1 and Rv2. The
thresholds are
VIN(on) =4.5V. (1 + Rv1/Rv2') and VIN(oft) =4.5V · (1 + Rv1/Rv2) where
Rv2' = Rv2l190k.
The resulting hysteresis is
V1N(hys) =4.5V · Rv1 I 90k.
When the UV comparator is low, Ice is low (500µA) and
the output is low.
5-201
UNDER VOLTAGE LOCKOUT (cont.) When both the lN and VCC comparators are high, the internal bias circuitry for the rest Of the chip is activated. The CDC pin (see discussion on Maximum Duty Cycle Control and Soft Start) and the Output are held low until VREF exceeds the 4.5V threshold Of the VREF comparator. When VREF is good, control of the output driver is transferred to
UC1848 UC2848 UC3848
the PWM circuitry and CDC is allowed to charge.
If any Of the three UVLO comparators go low, the UVLO latch is set, the output is held low, and CDC is discharged. This state will be maintained until all three comparators are high and the CDC pin is fully discharged.
Figure 1: Under Voltage Lockout
UDG-83004
Frequency Decreues as a Function of RT 1 r--,--,--,TTTTn---,--,--,"I:p:i=FI
~
0.951---+-+-HH+++t-v-7'"+--t-1r-HH-tti
0.9 l----l--l-l-++1-l7F:i--+--1--1-t--H-+H
yf
~ o.85 1---+--+--+-+:vH++t--+-+-+-r+ttti
lL 0.8 1----1--l-lµ++++l---+--t-t-+ttffi
J_ 0.75 l----1---lll-'4/-+~H+--+_,l-l-t-tt-H-1
0.7 L----L---1--1--L..J....L..W..L---'---'--'--'-................
10
100
1000
R(kohms)
UDG-93008
Oscillator Frequency as a Function of CT
2000 "I'
1000
N' 500
i
::....:
~
~
"'
20 50 100
JS:
500 1000
c (pF)
~ 5000
UDG93007
UDG-93005
Figure 2: Oaclllator Frequency
5-202
OSCILLATOR A capacitor from the CT pin to GND programs oscillator frequency, as shown in Figure 2. Frequency is determined by:
F = 1 I (10k ·Cl).
The sawtooth wave shape is generated by a charging
current of 200µA and a discharge current of 1SOOµA. The discharge time of the sawtooth is guaranteed dead time for the Output Driver. If maximum duty cycle control is de-
UC1848 UC2848 UC3848
teated by connecting DMAX to VREF, the maximum duty cycle is limited by the oscillator to 90%. If adjustment is required to overcome capacitor and chip tolerance, an additional trim resistor RT from CT to Ground can be used to adjust the oscillator frequency. RT should not be less than 40kohms. This will allow up to a 25% decrease in frequency.
50
80
40
30
.ii,i,"
>< 20
10
100
... 120 :":Vr rn
140 ~
2
160
0
180
-10 ~-~--~--~--~--~~~ 200
30k 100k 300k 1.0M
3M
10M 30M
Frequency (Hz)
Figure 3: Error Amplltler Gain Phase Response over Frequency
UDG-93008
INDUCTOR CURRENT WAVEFORM SYNTHESIZER
Average current mode control is a very useful technique synthesizes the off-time portion of the waveform. ION is
to control the value of any current within a switching con- the input to the follower. The discharge current is pro-
verter. Input current, output inductor current, switch grammed at IOFF.
current, diode current or almost any other current can be controlled. In order to implement average current mode control, the value of the current must be explicitly known at all times. To control output inductor current (IL) in a buck derived isolated converter, switch current provides inductor current information, but only during the on time of the switch. During the off time, switch current drops abruptly to zero, but the inductor current actually dimin-
ishes with a slope dll/dt = -Vo/L. This down slope must be synthesized in some manner on the primary side to provide the entire inductor current waveform for the control circuit.
The follower has a one volt offset, so that zero current corresponds to one volt at Cl. Best utilization of the UC1848 is to translate maximum average inductor current to a 4 volt signal level. Given N and Ns (the turns ratio of the power and current sense transformers), proper scaling of IL to V(CI) requires a sense resistor Rs as calculated from:
Rs= 4V · Ns · NI IL(max).
Restated, the maximum average inductor current will be limited to:
IL(max) = 4V · Ns · N/Rs. IOFF and Cl need to be chosen so that the ratio of
The patented Current Waveform Synthesizer (Figure 4) dV(Cl)/dt to dll/dt is the same during switch off-time as
consists of a unidirectional voltage follower which forces on-time. Recommended nominal off current is 1OOµA.
the voltage on capacitor Cl to follow the on-time switch This requires
current waveform. A programmable discharge current
Cl = (1 OOµA · N · Ns · L) I (Rs· Vo(nom))
5-203
UC1848
UC2848
INDUCTOR CURRENT WAVEFORM SYNTHESIZER (cont.)
UC3848
where Lis the output inductor value and Vo(nom) is the VREF. The discharge current is then 100µA. The disad-
converter regulated output voltage.
vantage to this approach is that the synthesizer continues
IOFF can be programmed in several manners. If accurate average current control is required during short circuit operation, the IOFF must track output voltage. The method in Figure 4 derives a voltage proportional to VIN · D (Duty Cycle). (In a buck converter, output voltage is proportional to VIN · D.) A resistive loaded diode connection to the bootstrap winding yields a square wave that is pro-
to generate a down slope when the switch is off even during short circuit conditions. Actual inductor down slope is closer to zero during a short circuit. The penalty is that the average current is understated by an amount approximately equal to the nominal inductor ripple current. Output short circuit is therefore higher than designed maximum output current.
portional in amplitude to VIN and is duty cycle modulated A third method of generating IOFF is to add a second
by the control circuit. Averaging this waveform with a filter winding to the output inductor core (Figure 6). When the
generates a primary side replica of secondary regulated power switch is off and inductor current is in the free
Vo. A single pole filter is shown, but in practice a two or wheeling diode, the voltage across the inductor is equal
three pole filter can do a better job of transient response. to the output voltage plus the diode drop. This voltage is
Filtered voltage is converted by ROFF to a current to the then transformed by the second winding to the primary
IOFF pin to control Cl down slope.
side of the converter. The advantages to this approach
If the system is not sensitive to short circuit requirements,
Figure 5 shows the simplest method of downslope gen-
eration: a single resistor (ROFF = 40k} from IOFF to
are it's inherent accuracy and bandwidth. Winding the second coil on the output inductor core while maintaining
required isolation makes this a more costly solution. In
the example, ROFF =Vo I 1OOµA. The 4 · ROFF resistor
I
VIN
I
I
I
I
I
Cl I
Current
JCI Amp
(OFF I
Input
I
I
I
I
I
I
I
' - - - - - - - - i :::>t-'ll'Vlr--.,_.Vcc I
I
Bootstrap Volts
IL __ __:: ___________ _JI
Figure 4: Inductor Current Waveform Synthesizer
UDG-93009
qROFF
I
VREF
40k
IOFF
I
Figure 5: Fixed IOFF
UDG-93010
UDG-93011
Figure 6: Second Inductor Winding Generation of IOFF
5-204
MAXIMUM VOLT-SECOND CIRCUIT A maximum Volt-Second-Product can be programmed by a resistor (Rvs) from VS to VIN and a capacitor (Cvs) from VS to ground (Figure 7). VS is discharged while the switch is off. When the output turns on, VS is allowed to charge. Since the threshold of the VS comparator is much less than VIN, the charging profile at Vs will be essentially linear. If VS crosses the 4.0V threshold before the PWM turns the output off, the VS comparator will turn the output off for the remainder of the cycle. The maximum Volt-Second-Product is
VIN · TON{max) = 4.0V · Rvs · Cvs.
MAXIMUM DUTY CYCLE AND SOFT START
A patented technique is used to accurately program maximum duty cycle. Programming is accomplished by a divider from VREF to DMAX (Figure 7). The value programmed is:
D(max) =Rd1 I (Rd1 + Rd2).
For proper operation, the integrating capacitor, Cd, should be larger than Cd{min) > T(osc) / 80k, where T(osc) is the Oscillator period. Cd also sets the soft start time constant, so values of Cd larger than minimum may be desired. The soft start time constant is approximately:
l{ss) =20k · Cd.
UC1848
UC2848
GROUND PLANES
UC3848
The output driver on the UC1848 is capable of 2A peak
currents. Careful layout is essential for correct operation
of the chip. A ground plane must be employed (Figure 8).
A unique section of the ground plane must be designated
for high di/dt currents associated with the output stage.
This point is the power ground to which to PGND pin is
connected. Power ground can be separated from the rest
of the ground plane and connected at a single point, al-
though this is not strictly necessary if the high di/dt paths
are well understood and accounted for. VCC should be
bypassed directly to power ground with a good high fre-
quency capacitor. The sources of the power MOSFET
should connect to power ground as should the return con-
nection for input power to the system and the bulk input
capacitor. The output should be clamped with a high cur-
rent Schottky diode to both VCC and PGND. Nothing else
should be connected to power ground.
VREF should be bypassed directly to the signal portion of the ground plane with a good high frequency capacitor. Low esr/esl ceramic 1µF capacitors are recommended for both VCC and VREF. The capacitors from CT, CDC, and Cl should likewise be connected to the signal ground plane.
r---------------
1
PWM
PWM
I
COMP
LATCH
I
OUT DAV
CLOCK
cC/DA 7c----vA.--A-v..-_-Ar
CT 1
I
I
I
I
I
I
I
I
Vs~
Vo rl__~ CONT
v V." C/A ::.:::-.:;Z-f
CDC/.
.:::-.A-_:-_:zlI-
CT 1
I
I
I
I
I
I
I
I
Vs~
Vo~CONT
v v" C/A ::.:::-.:;Z-f
CDC/.
.:::-.A-_:-_:zli-
CT I
I
I
I
I
I
V 1_4Vs I ~ I
Vo~ONT
UDG-93012
Figure 7: Duty Cycle Control 5-205
UDG-93013
~-------------------,
UC1848 UC2848 UC3848
1____Si_gn_al_G_ro_un_d ___ J1
I
I
; -=
Power Ground
1
-------------------~
FIGURE 8: GROUND PLANE CONSIDERATIONS
~ OPTO
FIGURE 9: TYPICAL APPLICATION· AN AVERAGE CURRENT· MODE ISOLATED FORWARD CONVERTER
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD.· MERRIMACK, NH 03054 TEL. ~24-2410· FAX 603-424-3460
5-206
n nINTEGRATED
~CIRCUIT&
-UNITROOE
Programmable, Off-Line, PWM Controller
UC1851 UC2851 UC3851
FEATURES All Control, Driving, Monitoring, and Protection Functions Included Low-Current Off Line Start Circuit Voltage Feed Forward or Current Mode Control High Current Totem Pole Output 50% Absolute Max Duty Cycle PWM Latch for Single Pulse Per Period Pulse-by-Pulse Current Limiting plus Shutdown for Over-Current Fault No Start-Up or Shutdown Transients Slow Turn-On Both Initially and After Fault Shutdown Shutdown Upon Over or Under Voltage Sensing Latch Off or Continuous Retry After Fault 1% Reference Accuracy 500kHz Operation 18 Pin OIL or 20 Pin PLCC Package
BLOCK DIAGRAM
DESCRIPTION
The UC1851 family of PWM controllers are optimized for offline primary side control. These devices include a high current totem pole output stage and a toggle flip-flop for absolute 50% duty cycle limiting. In all other respects this line of controllers is pin for pin compatible with the UC1841 series. Inclusion of all major housekeeping functions in these high performance controllers makes them ideal for use in cost sensitive applications.
Important features of these controllers include low current start-up, linear feed-forward for constant volt-second operation, and compatibility with both voltage or current mode control. In addition, these devices include a programmable start threshold, as well as programmable over-voltage, under-voltage, and over current fault thresholds. The fault latch on these devices can be configured for automatic restart, or latched off response to a fault.
These devices are packaged in 18-pin plastic or ceramic dualin-line packages, or for surface mount applications, a 20 Pin PLCC. The UC1851 is characterized for -55°C to +125°C operation while the UC2851 and UC3851 are designed for -25°C to +85°C and 0°c to +70°C, respectively.
COMP 1111--~~~~~ INV.
INPUT N.I.
INPUT
START/ UV
CURRENT LIMIT
THRESHOLD
6/93
EXT. STOP GROUND
5-207
RAMP
VIN
SUPPLY DRIVER BIAS 5.0V REF
PWM OUTPUT
SLOW START/ DUTY CYCLE CLAMP
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage, +VIN (Pin 15) Voltage Driven ·····..··..··................... +32\/ Current Driven, 1OOmA maximum. · . . . . . . · . . Self-limiting
PWM Output Voltage (Pin 12) ........·...·..·.·..··. 40V PWM Output Current, Steady-State (Pin 12) . . . . . . . . . 400mA PWM Output Peak Energy Discharge ...·........ 20µ.Joules Driver Bias Currelit (Pin 14) · · · · · . . . . . . . . . . . . . . . . -200mA Reference Output Currem (Pin 16) . · . . . . . . . . . . . · . . -50mA Slow-Start Sink Currelit (Pin 8) . , . . . . . . . . . . . . . . . . . . 20mA VIN Sense Current (Pin 11)........................ 10mA Current Limit Inputs (Pins 6 & 7) . . . . . . . . · . . . . -0.5 to +5.5V Stop Input (Pin 4) .. .. · .. . · .. .. .. . . .. . . .. . . -0.3 to +5.5V
CONNECTION DIAGRAMS
UC1851
UC2851
UC3851
Comparator Inputs (Pins 1-7, 9--11, 16) ·.····..···... Internally clamped at 12V Power Dissipation at TA = 25°C (Note 3). . · . . . · . . . . !OOOmW Power Dissipation at Tc= 25°C (Note 3)··....·...· 2ooomw Operating Junction Temperature .···.·····. -55°C to +150°C Storage Temperature Range .···..··...·.. -65°C to +150°C Lead Temperature (Soldering, 10 sec) ............· +300°C Note 1:All voltages are with respect to ground, Pin 13.
Cu"ents are positive-into, negative-out of the specified terminal Note 2:All pin numbers are referenced to DIL-18 package. Note 3:Consult Packaging Section of Databook for thermal /imitations and considerations ofpackage.
DIL-18, SOIC-18 (TOP VIEW) J or N, OW Package
COMP
CUR THRESH 6 CUR SENSE 7
SLOW START 8
N.I. INPUT INV. INPUT 5.0V REF +VIN SUPPLY 4 DRIVE BIAS 3 GROUND
VIN SENSE
PLCC-20, LCC-20 (TOPVIEW) Q,LPACKAGE
L3 2 1 2019
4
18
5
17
6
16
7
15
8
14
9 10 11 12 13
~
PACKAGE PIN FUNCTIONS
FUNCTION
PIN
COMP
1
START_l!J_V
2
OVSENSE
3
STOP
4
RESET
5
CUR THRESH
7
CUR SENSE
8
SLOW START
9
RTLCT
10
RAMP
11
V1NSENSE
12
PWM OUT
13
GROUND
14
DRIVE BIAS
15
+VIN SUPPLY
17
5.0VREF
18
!NV.INPUT
19
N.l. INPUT
20
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA= -55°C to+125°C for the
uc1ss1, .40·c to +ss·c for the UC2851, and o·c to 1o·c for the UC3851; V1N =
20V, RT= 20k0, CT= .001 mfd, RR= 10k0, CR= .001mfd. Current Limit Threshold = 200mV, TA= TJ.
PARAMETER
Powerl~uts
Start·Uj>_ Current 0_.29rati'!l!.. Current
S~OVClam...P_
Reference Section Reference VoltaJl_e Line Reg_ulation Load R~ulation Total Ref Variation Short Circuit Current
Oscillator Nominal F~uenc...Y. Volta_g_e Stability_ Total Ref Variation Maximum Frequency
TEST CONDITIONS
UC1851 / UC2851
UC3851
UNITS
MIN TYP MAX MIN TYP MAX
VIN= 30V, Pin 2 = 2.5V VIN= 30V, Pin 2 = 3.5V VIN=20mA
4.5 6
4.5
6
mA
15 21
15 21 mA
33
39
45
33
39
45
v
TJ=25°C
4.95 5.0 5.05 4.9 5.0 5.1
v
VIN=8to30V
10 15
10 20 mV
IL=Oto 10mA
10 20
10 30 mV
Over ~ati'!l!.. Tem_.29rature AanJle 4.9
5.1 4.85
5.15 v
VREF = 0, TJ = 25°C
-80 -100
-80 -100 mA
TJ=25°C
47 50 53 45 50 55 kHz
VIN:8to 30V
0.5
1
0.5
1
%
Over ~ati'!l!..Tem...P_erature Ran~ 45
55 43
57 kHz
RT = 2k0, CT = 330pF
500
500
kHz
5-208
UC1851
UC2851
UC3851
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA= -55°C to +125°C for the uc1851, -40°C to +85°C for the UC2851, and o·c to 10°c for the UC3851; V1N =
20V, RT = 20kQ, CT= .001 mfd, RR = 1OkQ, CR = .001 mfd. Current Limit Threshold
= 200mV, TA= TJ.
PARAMETER
TEST CONDITIONS
UC1851 I UC2851
UC3851
UNITS
MIN TVP MAX MIN TVP MAX
Ram_J>_ G e n e r a t o r
Ramp Current, Minimum
!SENSE = -10µA
-11 -14
-11 -14 µA
Ramjl_Current, Maximum
RamJ>_Vall~
RamJ>_Peak
!SENSE = 1.0mA Clam_.l)il'l9_ Level
-0.9 -.95
-0.9 -.95
mA
0.3 0.4 0.6 0.3 0.4 0.6
v
3.9 4.2 4.5 3.9 4.2 4.5
v
Error Am_e.!lfler
ll'!e_ut Offset Volta_.9.e
VCM=5.0V
0.5
5
2
10 mV
ll'!e_ut Bias Current
0.5
2
1
5
µA
Input Offset Current
0.5
0.5 µA
Open Loop Gain
Output Swing (Max Output :s
RamJ>_Peak-100~
!!No= 1to3V Minimum Total Range
60
66
60 66
dB
0.3
3.5 0.3
3.5 v
CMRR
VcM = 1.5 to 5.5V
70
80
70 80
dB
PSRR
VIN= 8to30V
70
80
70 80
dB
Short Circuit Current
VCOMP=OV
-4 -10
-4 -10 mA
Gain BandwidthJ.Note 1_l Slew Rate__(_Note !l_
TJ = 25°C, AVOL = OdB TJ = 25°C, AVCL = OdB
1
2
0.8
1
2
0.8
MHz v~
PWMSectlon
Continuous Duty Cycle Range
J_other than zero}J_Note 1l
Output High Level
Rise TimeJ_Note 1_l
Minimum Total Continuous Range Ramj>_Peak < 4.2V !SOURCE = 20mA ISOURCE = 200mA TJ = 25°C, CL= 1nF
2
46
2
46
%
18 18.5
18 18.5
v
17 18.5
17 18.5
v
50 150
50 150 ns
Fall TimeJ..Note 1_l
Output Saturation
TJ = 25°C, CL= 1nF IOUT =20mA IOUT = 200mA
50 150 0.2 0.4 1.7 2.2
50 150 ns
0.2 0.4
v
1.7 2.2
v
Comparator Delay (Note 1)
Pin 8 to Pin 12, TJ = 25°C, AL= 1kQ
300 500
300 500 ns
Sequencl'!S_ Functions Comparator Thresholds
Pins2, 3, 5
2.8 3.0 3.2 2.8 3.0 3.2
v
Input Bias Current
Pins3, 5 = OV
-1.0 -4.0
-1.0 -4.0 µA
Input LeakC199
Pins 3, 5 = 10V
0.1 2.0
0.1 2.0 µA
Start/UV HEteresis Current Ext. Stop Threshold
Pin2 = 2.5V Pin4
170 200 220 170 200 230 ~
0.8
1.6 2.4 0.8 1.6 2.4
v
Error Latch Activate Current Pin 4 = OV, Pin 3 > 3V
Driver Bias Saturation Voltage, IB = -50mA VIN-VOH
-120 -200
2
3
-120 -200 µA
2
3
v
Driver Bias Leakage Slow-Start Saturation
VB=OV Is= 10mA
-0.1 -10 0.2 0.5
-0.1 -10 ~
0.2 0.5
v
Slow-Start Leak~e
Vs=4.5V
0.1 2.0
0.1 2.0 µA
Current Control
Current Limit Offset
0
5
0
10 mV
Current Shutdown Offset
370 400 430 360 400 440 mV
Il'!e_ut Bias Current
Pin 7 = OV
!l Common Mode Ral'l9_eJ_Note
-2
-5
-2
-5
µA
-0.4
3.0 -0.4
3.0 v
Current Limit Delay (Note 1) TJ = 25°C, Pin 7to12, AL= 1k Note 1:Guaranteed by design. Not 100% tested m production.
200 400
200 400 ns
5-209
UC1851 UC2851 UC3851
FUNCTIONAL DESCRIPTION
PWMCONTROL 1. Oscillator
Generates a fixed-frequency internal clock from an external RT and Cr.
= Frequency ~~T where Kc is a first-order correction factor - 0.3 log (Cr x 1O12).
2. Ramp Generator:
Develops linear ramp with slope defined externally by ~
·
sense voltage ARCA
CR is normally selected s Cr and its value will have some effect upon valley duty cycle.
Limiting the minimum value for !SENSE into pin 11 will establish a maximum duty cycle clamp.
CR terminal can be used as an i'!E_ut...29rt for current mode control.
3. Error Amplifier
Conventional operational amplifier for closed-loop gain and phase compensation. Low output impedance; unity-gain stable. The oll!Q_ut is held low ~the slow start volt~e at turn on in order to minimize overshoot.
4. Reference Generator: Precision 5.0V for internal and external usage to 50mA. Tracking 3.0V reference for internal usage only with nominal accuracy of ±2%. 40V clam..E_zener for ch.!J:!. OV_E!"Otection, 1OOmA maximum current.
5. PWM Comparator:
Generates output pulse which starts at termination of clock pulse and ends when the ramp input crosses the lowest of two..E_Ositive irl(l_Uts.
6. PWM Latch:
Terminates the PWM output pulse when set by inputs from either the PWM comparator, the l£.ulse-~ulse com..E_arator, or the error latch. Resets with each internal clock~lse.
7. PWM Output Switch: Totem pole output stage capable of sourcing and sinking 1 amp peak current. The active "on" state is hig_h.
SEQUENCING FUNCTIONS
1. Start/UV Sense:
With an increasing voltage, this comparator generates a turn-on signal and releases the slow start clamp at a start threshold. With a decreasing voltage, it generates a turn-off command at a lower level separated by a 200µA ~teresis current.
2. Drive Switch:
Disables most of the chip to hold internal current consumption low, and Driver Bias OFF, until input volt~e reaches start threshold.
3. Driver Bias:
S~ies drive to external circu.!!1Y_~on start-l!E:
4. Slow Start:
Clamps low to hold PWM OFF. Upon release, rises with rate controlled by RsCs for slow increase of output pulse width. Can also be used as an alternate maximum dl!JY.~le clam..E_with an external volt~e divider.
PROTECTION FUNCTIONS
1. Error Latch:
When set by momentary input, this latch insures immediate PWM shutdown and hold off until reset. Inputs to Error Latch are: a. OV > 3.2V (Typically 3V) b. Stop > 2.4V (Typically 1.6V) c. Current Sense 400mV over threshold. (Typical). Error Latch resets when slow start voltage falls to 0.4V if Reset Pin < 2.SV. With Pin 5 > 3.2V, Error Latch will remain set.
2. Current Limiting:
Differential input comparator terminates individual output pulses each time sense voltage rises above threshold. When sense voltage rises to 400mV (typical) above threshold, a shutdown signal is sent to Error Latch.
3. External Stop:
A voltage over 2.4 will set the Error Latch and hold the output off. A voltage less than O.SV will defeat the error latch and prevent shutdown. A capacitor here will slow the action of the error latch for transient protection by providing a Typical
Delay of 13ms/µF.
5-210
Start/UV Hysteresis Current
!e'
~
0cc
~ 275
~ 250 225
~ 200
N · 20V PN2·2.5
~ 175
~ w
I-
150 125
(/)
>
J:
-50 -25 0
25 50
75 100 125
JUNCTION
TEMPERATURE
-
(C 0 )
UC1851 UC2851 UC3851
Output Saturation Characteristics
~ · 4
: ~
~
~
~ "'
0
o-.f::::'.::±::::J::C[__LJ~~~~~~ ~ a~~~.-: C\I ~"": 11P"': S
OUTPUT CURRENT, SOURCE OR SINK - (A)
Oscillator Frequency
500F"'-i-.-:-""k~:+------1-----1-----1--f-~
£ 200
-
100 ,.__,___.,..,r+--Tr----"t--'rl-"rl--t--+----<
20 f---'<+---.+--"<-t---------1---'< 10 5
2
2 5 10 20 50 100 200 500
RT TIMING RESISTOR · (k o )
PWM Output Minimum Pulse Width
~
(PULSE WIDTH GOES TO ZERO
~
BELOW VALUE INDICATED)
10
~ 5.0 H'<-----'<+--+----+----------1 ~ 3.0 f'lr-'.--+''rl
w 2.0
~
~ 0.5 :::? 0.3 rt--t--t--..C-~-t-"'-..c--P"o.C-----1
~ 0.2
0.1 L.L__L___L____J___L______[____[__
_J
10 20 30 50 100 200 300 500
OSCILLATOR FREQUENCY - (k HERTZ)
Error Amplifier Open-Loop Gain and Phase
80
~ 60
r------,
~
I
VIN = 20v TJ = 25°ct-
~z 40 f---+~-+-~-Q~~·~---+-
g "~ i t!j 20
>
0
lo=""="=--t't------tP=HA~S:E-:+:--~ f'---------t'----=---'t-------r"--.-;-;-;.:.:.:.-~-'+I--_-_1,
180 270
360
w
(/)
:!I$:
100 1K 10K 100K 1M
FREQUENCY - (HERTZ)
Shutdown liming
5 PIN 3 VOLTS
0
5 PIN 8 VOLTS
0
20 PIN 12 VOLTS
0
-
±
±Input to OV Sense
l
l
J.. o Duty cvcle ~~ ' ...... cs> a- __ Clamp oltag Cs ·
I
J
PWM Output
l Voltage
i l
l
0 500 1000 1500
DELAY TIME - (N SEC)
5-211
OPEN-LOOP CIRCUIT
UC1851 UC2851 UC3851
SlJ>Pl..Y VOLTAGE
RT
Rt R2 Ra
RN
91K 18 v-
VN SLOW START
11 VN SENSE
DRIVER BASE 14
9 RT/CT
UC1851 D.U.T.
12 PWM OUT
10 RAMP 2 START/UV
DL·18 PACKAGE
GROUND 13 5
RESET
3 OV SENSE
COM> INV N
...
17 18 10K
C/L · 8
IR&
~~ 100K
OUTPUT
10K
\/REF
l 0.1
10K
PWM ADJUST
48K
43K
2K
10K
CURRENT SENSE
TEST
Nominal Frequency =R~CT =50kHz
= = UV Fault Voltage 3 (R1 R+2R+2R+3R3) 8V
= Current Limit 200mV
= Current Fault Voltage 600mV
= = = = = Start Voltage 3 ( R1 R+2R+2R+3R3) +0.2R1 12V OV Fault Voltage 3 (R1 + :~ + R3) 32V Duty Cycle Clamp 50% = = @VIN 15V, Duty Cycle 48%
@VIN = 30V, Duty Cycle = 24%
High Peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypass capacitors should be connected close to pin 13 in a single ground point.
Programmable Soft Start and Restart Delay Circuit
UC1851 Power MOSFET Drive Interface
SOFT START
GROUND
For further application information see UC1840/UC1841 Data Sheets
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. · MERRIMACK, NH 03054 TEL (603) 424-2410 · FAX (603) 424-3460
5·212
TO CURRENT SENSE (A) OIRECT ORIVE
(B) TRANSFORMER COUPLED
n n INTEGRATED
~CIRCUITS
-UNITRDDE
High Power-Factor Preregulator
~~···.··.·~ i!J~··~ ··. · .< ..·
.... ·
~-,
UC1852 UC2852 UC3852
FEATURES · Low-Cost Power Factor
Correction · Power Factor Greater Than 0.99 · Few External Parts Required · Controlled On-Time Boost PWM · Zero-Current Switching · Limited Peak Current · Min and Max Frequency Limits · Starting Current Less Than 1mA · High-Current FET Drive Output · Under-Voltage Lockout
DESCRIPTION
The UC1852 provides a low-cost solution to active power-factor correction (PFC) for systems that would otherwise draw high peak current pulses from AC power lines. This circuit implements zero-current switched boost conversion, producing sinusoidal input currents with a minimum of external components, while keeping peak current substantially below that of fully-discontinuous converters.
The UC1852 provides controlled switch on-time to regulate the output bulk DC voltage, an off-time defined by the boost inductor, and a zero-current sensing circuit to reactivate the switch cycle. Even though switching frequency varies with both load and instantaneous line voltage, it can be maintained within a reasonable range to minimize noise generation.
While allowing higher peak switch currents than continuous PFCs such as the UC1854, this device offers less external circuitry and smaller inductors, yet better performance and easier line-noise filtering than discontinuous current PFCs with no sacrifice in complexity or cost. The ability to obtain a power factor in excess of 0.99 makes the UC1852 an optimum choice for low-cost applications in the 50 to 500 watt power range. Protection features of these devices include under-voltage lockout, output clamping, peak-current limiting, and maximum-frequency clamping.
The UC1852 family is available in 8"pin plastic and ceramic dual in-line packages, and in the 8-pin small outline IC package (SOIC). The UC1852 is specified for operation from -ss·c to +12s·c, the UC2852 is specified for operation from -40°C to +85°C, and the UC3852 is specified for operation from o·c to +70°C.
TYPICAL APPLICATION
ucass;l
12/92
5-213
UDG-92001
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (Low-imped~e Source) .......................... 30.0V Supply Current (High-Impedance Source) ...................... 30.0mA OUT Current, Peak ............................................................. :1:1.0A OUT Energy, Capacitiw Load........................,....................5.0µJ Input Voltage~ ISNS ............................................................ :1:5.0V Input Voltage, VFB ...............................,·.·.....·.·. -0.3Vto +10.0V COMP Current...............................................................:1:10.0mA ISET Current..................................................................-10.0mA Power Dissipation at Tas25°C (Note 3) .............................. 1.0W Storage Temperature ....................................... -65°C to +150-C Lead Temperature (Soldering, 1OSeconds) ................... +3000C Note 1: Al/voltages with respect to GND (Pin 1). Note 2: All cu"ents are positive into the specified terminal. Note 3: Refers to DIL-8 Package. Consult Packaging Section of Unitrode Integrated Circuits databook for thermal limitations and considerations ofpackage.
CONNECTION DIAGRAM
UC1852 UC2852 UC3852
DIL-8 (TOP VIEW) J or N Package
V F B o ·8· COMP
ISNS 2
7 voe
ISET 3
8 OUT
RAMP 4
& ONO
U.SOIC-8 (TOl> VIEW) D Package
VFB
ISNS 2
8 COMP
7 voe
ISET 3
. 8 OUT
RAMP 4
& ONO
UOG·ll2002
ELECTRICAL CHARACTERISTICS Unless otherwise stated, VCC=24V, ISET=50k0 to GND, RAMP=1 nF to GND, ISNS= -0.1 V, VFB connected to COMP, no load on OUT, -55°C<Ta<+125°C for the UC1852,
-40°C<Ta<+85°C for the UC2852, arid 0°C<Ta<+70°C for the UC3852, and Ta=Tj.
PARAMElER Timer SecUon
ISETVol~
RAMP Charge Current RAMP Disch~eCurrent RAMP Saturation Volta.Jl!. RAMP Threshold - Maximum Frequency RAMP Threshold - PWM Com_e..arator Current Senee Com~arator ISNS Restart Threshold ISNS Fault Threshold ISNS l~ut Current Error Am~Hler Section VFB Input Voltage VFB Input Blas Current COMP Sink Current COMP Source Current COMP Clamp Voltage OUT Output OUT Saturation Voltage High OUT Saturation Voltage Low OUT Saturation Voltage Low @ 1OmA OUT Clam_e..Voltage OUT Voltage during UVLO Overall Section Inactive Supply Current Active Supe!lCurrent VCC Clam_1>_Volta...9! VCC Tum-On Threshold VCC Tum-Off Threshold VCC Threshold Hysteresis
TEST CONDITIONS
RAMP=2.5V ISNS= -1.0V, RAMP=1.0V ISNS= -1.0V, IRAMP=1 OOµA VFB=10V, COMP ~n
COMP=7.5V COMP=2.5V VFB=O.OV, COMP ~en VCC=13V, IOUT=--200mA, RAMP=2V IOUT=200mA, ISNS= -1.0V IOUT=10mA, ISNS=-1.0V IOUT= -200mA, RAMP=2V IOUT=100mA, VCC=OV VCC=10V ICC=25mA
MIN. TYP. MAX. UNITS
4.5
5.0
5.5
v
88
98
108 !IA
12
28
50
mA
0.006 0.200 v
0.92 1.02 1.12
v
3.9
4.3
4.8
v
~18
-10
-4
mV
-550 -450 -350 mV
-100 -30
100
!IA
4.6
5.0
5.3
v
-5.00 -0.03 5.00 !IA
10
mA
-300 -175 -100 i.oA
9.2
10.0 10.6
v
0.5
1.7
2.5
v
0.5
1.6
2.2
v
0.05 0.40
v
10.0 12.0 14.5
v
0.5
1.0
2.2
v
0.2
0.4
1.0 mA
3.0
6.0
10.0 mA
30
33
36
v
14.5 16.3 17.5
v
10.5 11.5 13.0
v
3
5
7
v
5-214
DETAILED BLOCK DIAGRAM
UC1852 UC2852 UC3852
COMP 1 1 - - - - - - . . ,
VFB~- " 5V + 1DV
ONO~
RESET DOMINANT
9V
1V
UDG-92003
PIN DESCRIPTIONS
COMP: COMP is the output of the error amplifier and the input of the PWM comparator. To limit PWM on-time, this pin is clamped to approximately 1OV. To implement soft start, the COMP pin can be pulled low and ramped up with a PNP transistor, a capacitor, and a resistor.
GND: Ground for all functions is through this pin.
ISET: The dominant function is of this pin is to program RAMP charging current. RAMP charging current is approximately 5V divided by the external resistor placed from ISET to ground. Resistors in the range of 10kQ to 50kQ are recommended, producing currents in the range of 1OOµA to 500µA.
A second function of ISET is as reference output. The ISET pin is normally regulated to 5V ±10%. It is critical that this pin only see the loading of the RAMP programming resistor, but a high input-impedance comparator or amplifier may be connected to this pin or to a tap on the RAMP programming resistor if required.
The third function of the ISET pin is as a FAULT output. In the event of an over-current fault, the !SET pin is forced to approximately 9V by the fault comparator. This can be used to trip an external protection circuit which can disable the load or start a fault restart cycle.
ISNS: This input to the zero and over current comparators is specially built to allow operation over a :5V dynamic
a range. In noisy systems or systems with very high
inductors, it is desirable to filter the signal entering the ISNS input to prevent premature restart or fault cycles. For best accuracy, ISNS should be connected to a current sense resistor through no more than 200 ohms.
OUT: The output of a high-current power driver capable of driving the gate of a power MOSFET with peak currents exceeding ±500mA. To prevent damage to the power MOSFET, the OUT pin is internally driven by a 12V supply. However, lead inductance between the OUT pin and the load can cause overshoot and ringing. External current boost transistors will increase this overshoot and ringing. If there is any significant distance between the IC and the MOSFET, external clamp diodes and/or series damping resistors may be required. OUT is actively held low when the VCC is below the UVLO threshold.
RAMP: A controlled on-time PWM requires a timer whose time can be modulated by an external voltage. The timer current is programmed by a resistor from !SET to GND. A capacitor from RAMP to GND sets the on time in conjunction with the voltage on COMP. Recommended values for the timer capacitors are between 1OOpF and 1nF.
VCC: VCC is the logic and control power connection for this device. VCC current is the sum of active device supply current and the average OUT current. Knowing the maximum operating frequency and the MOSFET gate charge (Qg), average OUT current can be estimated by:
louT = Og x F
To prevent noise problems, bypass VCC to GND with both a ceramic and an electrolytic capacitor.
VFB: VFB is the error amplifier inverting input. This input serves as both the voltage sense input to the error amplifier and as the other compensation point for the error amplifier.
5-215
TYPICAL CHARACTERISTICS
Error Amplifier Gain and Phase
-rTTII 100 ,---,--,rrrrmr-,-,rrrmr~ ITITT
-,...,..1 80 ll +-+++++ittt--+-t-'~~t"-~---'--tlittt
f--r+-ttttttt----t-lH-H~.P~se
so+-+-+++ttttt--++~H~'-T-rttttt11
l"N _\ Gain
(dB)
Phase
(deg)
40 k-t---+-t-++ttiH-. Gain-l+H-H-~.\-1-+ri+ttjj
,..
\
0 +-++++++H+--+-Htt-ffll.Kl:-+-'t-iittffi
l DJ
UC1852 UC2852 UC3852
Max Frequency vs. Rset and Ct
1OOO r.;1~OO;;::o:r:F:-u:run==+:=i=tti+m 1-5oo_Qf
Maximum
Nl'l\
I\.
I\. ~
FreqkuHezncy, 100
t::=!=:E:ttMD.~~~=u.SSm~
r:::
13.
N :
10
100 1000 10000
Frequency, kHz
UDG-92005
10 Rset, kQ
100
UDG-92006
Max On-Time vs. Rset and Ct
1000 ~IHll~!ll lL
Maximum On-Time
µs
OUT Rise and Fall Time 200
150
10
Rset, kQ
100
UDG-92007
5-216
0
5
10
Load Capacitance, nF
UDG-92008
APPLICATION INFORMATION: A 100 Watt
C1 R3
UC1852 UC2852 UC3852
R2 UDG-92004
This circuit demonstrates a complete power factor preregulator based on the UC3852. This preregulator will supply up to 100 watts at 400VDC and exhibit power factor greater than 0.995 with less than 10% total harmonic distortion. Operating input range is 90V to 160V RMS at 50Hz to 60Hz.
This design is intentionally simple, yet fully functional. The UC3852 can also be used in designs featuring soft start, over-voltage protection, wide power-line voltage operation, and fault latching. For more information on applying the UC3852, refer to Unitrode Application Note U-132.
PARTS LIST
C1 0.47µF/250VACX2 Class Polyester
Q1 IRF830 4.5N500V 1.5Q Power FET
C2 1nF/16V Ceramic C3 68µF/35V Aluminum Electrolytic C4 180pF/16V Ceramic C5 0.1 µF/16V Polyester or Ceramic C6 82µF/450V Aluminum Electrolytic 01 2N500V Bridge Rectifier (Collmer
KBPC106 or Powertex MB11A02V60)
L1 680µH (Renco RL3792 with 10 Turn 24 AWG Secondary)
R1 150kQ, 1/4W R2 0.2Q, 112w Carbon Composition R3 100, 1/4W R4 13.3kQ, 1/4W R5 1MQ, 1/4W
02 100mN50V Switching Diode (1N4148) R6 20kQ, 1/4W
03 2N500V 250ns Recovery-Time Rectifier R7 200kQ, "'2.W
(Motorola MR856)
R8 200kQ, "'2.W
IC1 UC3852N Power Factor Controller IC
R9 5.1kQ, 1/4W R10 12Q, 1/4W
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. ·MERRIMACK; NH 03054 TEL (603) 424-2410 ·FAX (003) 424-3460
5-217
n.n l_::::J
INTEGRATED CIRCUITS
-UNITRDDE
High Power Factor Preregulator
UC1854 UC2854 UC3854
FEATURES Control Boost PWM to 0.99 Power Factor Limit Line Current Distortion To <5% World-Wide Operation Without Switches Feed-Forward Line Regulation Average Current-Mode Control Low Noise Sensitivity Low Start-Up Supply Current Fixed-Frequency PWM Drive Low-Offset Analog Multiplier/Divider 1A Totem-Pole Gate Driver Precision Voltage Reference
BLOCK DIAGRAM
DESCRIPTION
The UC1854 provides active power factor correction for power systems that otherwise would draw non-sinusoidal current from sinusoidal power lines. This device implements all the control functions necessary to build a power supply capable of optimally using available power-line current while minimizing line-current distortion. To do this, the UC1854 contains a voltage amplifier, an analog multiplier/divider, a current amplifier, and a fixed-frequency PWM. In addition, the UC1854 contains a power MOSFET compatible gate driver, 7.5V reference, line anticipator, load-enable comparator, low-supply detector, and over-current comparator.
The UC1854 uses average current-mode control to accomplish fixedfrequency current control with stability and low distortion. Unlike peak current-mode, average current control accurately maintains sinusoidal line current without slope compensation and with minimal response to noise transients.
The UC1854's high reference voltage and high oscillator amplitude minimize noise sensitivity while fast PWM elements permit chopping frequencies above 200kHz. The UC1854 can be used in single and three phase systems with line voltages that vary from 75 to 275 volts and line frequencies across the 50Hz to 400Hz range. To reduce the burden on the circuitry that supplies power to this device, the UC1854 features low starting supply current.
These devices are available packaged in 16-pin plastic and ceramic dual in-line packages, and a variety of surface-mount packages.
PK
LMT
REF
VSENSE IAC
VRMS
2/93A
ISENSE CT
RSET
5-218
UDG-92Cl615
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Vee . . . .. . . . . .. . . .. .. . . . . . . . . . . .. . . . . . . . 35V GT Drv Current, Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5A GT Drv Current, 50% Duty Cycle. . . .. . . . . . . .. . . . . .. . . . . . . . 1.5A Input Voltage, VSENSE, VRMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V Input Voltage, ISENSE, Mult Out . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V Input Voltage, PKLMT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V Input Current, RSET, IAe, PKLMT, ENA .................... 10mA Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
Storage Temperature ..................... --S5°C to+ 150°C Lead Temperature (Soldering, 10 Seconds) . . . . . . . . . . . . . . +300°C
UC1854 UC2854 UC3854
Note 1: All voltages with respect to Gnd (Pin 1). Note 2: All currents are positive into the specified terminal. Note 3: ENA input is internally clamped to approximately 14V. Note 4: Consult Unitrode Integrated Circuits databook for information regarding thermal specifications and limitations ofpackages.
CONNECTION DIAGRAM
DIL-16 & SOIC·16 (Top View) J, N & OW Packages
PLCC-20 & LCC-20 (Top View) Q & L Packages
La 2 1 20 19
4
18
5
17
6
16
7
15
8
14
9 10 11 12 13
PACKAGE PIN FUNCTION
FUNCTION
PIN
~
1 ..2._
PKLMT
3
CA Out
4
l~NSE
5
N]C
6
MultOut
7
IAe
8
VA Out
9
VRMS
10
l'll_C
11
VREF
12
ENA
13
VSENSE
14
ASET
15
N_l_C
16
SS
17
CT
18
Vee
19
GTDrv
20
ELECTRICAL
Unless otherwise stated, Vee=18V, RT=8.2k, CT=1.5nF, PKLMT=1 V, VRMS=1.5V, 1Ae=1 OOµA,
CHARACTERISTICS ISENSE=OV, CA Out=4V, VA Out=3.5V, VSENSE=3V, -55°C<TA<125°C for the UC1854NB,
-40°C<TA<85°C for the UC2854NB, and 0°C<TA<70°C for the UC3854NB, and TA=TJ.
PARAMElER OVERALL
Supply Current, Off Supply Current, On Vee Turn-On Threshold Vee Turn-Off Threshold ENA Threshold, Rising ENA Threshold Hysteresis ENA Input Current VRMs Input Current VOLTAGE AMPLIFIER Voltage Amp Offset Vol~e VSENSE Bias Current Voltage Amp Gain Voltag_e Am_pOut_e_ut Swi~ Voltage Amp Short Circuit Current SS Current
TEST CONDITIONS ENA=OV
ENA=OV VRMS=5V VA0ut=3.5V VSENSE=OV
VAOut=OV SS=2.5V
MIN
TYP
MAX
14.5 9 2.4 0.2
-5.0 -1.0
1.5 10 16 10 2.55 0.25 -0.2 -.01
2.0 16 17.5 11 2.7 0.3 5.0 1.0
-8
8
-500
-25
500
70
100
0.5to 5.8
--30
-12
-5
-20
-14
~
UNITS
mA mA
v v v v
µA µA
mV nA dB
v
mA µA
5-219
UC1854
UC2854
UC3854
ELECTRICAL
Unless otherwise stated, Vcc=18V, RsET=15k to ground, CT=1.5nF to ground, PKLMT=1V, ENA=7.5V,
CHARACTERISTICS VRMS=1.5V, IAC=100µA, ISENSE=OV, CA Out=3.5V, VA Out=5V, VsENSE=7.5V, no load on SS, CA Out,
VA Out, REF, GT Orv, -55°C<TA<125°C for the UC1854, -40°C<TA<85°C for the UC2854., and
0°C<TA<70°C for the UC3854, and TA=TJ.
PARAMETER CURRENT AMPLIFIER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Current Am_e_ Offset Voltage ISENSE Bias Current Input Range, ISENSE, Mult Out
-4
4
mV
-500
-120
500
nA
-0.3to2.5
v
Current Am_J)_Gain Current Am_J)_Output Swing
80
110
dB
0.5 to 16
v
Current Am_J)_Short Circuit Current CAOut=OV
-30
-12
-5
mA
Current Amp Gain-BW Product
TA=25°C
400
800
kHz
REFERENCE Reference Output Voltage
VREF Load ~ulation
IREF=OmA, TA=25°C IREF=OmA, Over Temp. -1 OmA<IREF<OmA
7.4
7.5
7.6
v
7.35
7.5
7.65
v
-15
5
15
mV
VREF Line Regulation
15V<VCC<35V
-10
2
10
mV
VREF Short Circuit Current MULTIPLIER
REF=OV
-50
-28
-12
mA
Mult Out Current IAc Limited
1Ac=1 OOµA, RsET=1 Ok
-220
-200
-180
µA
Mult Out Current Zero
IAC=OµA, RSET=15k
-2.0
-0.2
2.0
µA
Mult Out Current RsET Limited
IAC=450µA, RSET=15k
-280
-255
-220
µA
Mult Out Current
IAC=50µA, VRMS=2V, VA=4V IAC=100µA, VRMS=2V, VA=2V
-50
-42
-33
I-IA.
-38
-27
-12
µA
IAC=200µA, VRMS=2V, VA=4V
-165
-150
-105
µA
IAC=300µA, VRMS=1V, VA=2V
-250
-225
-150
µA
Multiplier Gain Constant
IAC=100µA, VRMS=1V, VA=2V {Note 5)
-95
-80
-00
µA
-1.0
v
OSCILLATOR
Oscillator Frequency
CT Ram_e_ Peak-to-Vall~Am_elitude CT Ramp Valley Voltage
RSET=15k RSET=8.2k
46
55
62
kHz
86
102
118
kHz
4.8
5.2
5.6
v
0.8
1.1
1.3
v
GATE DRIVER
Maximum GT Orv Output Voltage
OmA load on GT Orv, 18V<VCC<35V
13
14.5
18
v
GT Orv Output Voltage High
-200mA load on GT Orv, Vcc=15V
12
12.8
v
GT Orv Output Voltage Low, Off
Vcc=OV, 50mA load on GT Orv
0.9
1.5
v
GT Orv Output Voltage Low
200mA load on GT Orv
1.0
2.2
v
1OmA load on GT Orv
0.1
0.4
v
Peak GT Orv Current
10nF from GT Drvto Gnd
1.0
A
GT Orv Rise/Fall Time
1nF from GT Orv to Gnd
35
ns
GT Drv Maximum Duty Cycle
95
%
CURRENT LIMIT
PKLMT Offset Voltage
-10
10
mV
PKLMT Input Current
PKLMT=-0.1V
-200
-100
µA
PKLMT to GT Orv Delay
PKLMT falling from 50mV to -50mV
175
ns
Note 5: Multiplier Gain Constant (k) is defined by:
l
kx /ACx (VA Out-1)
Mull Out·
VRMfl
5-220
PIN DESCRIPTIONS (Pin Numbers Refer to DIL Packages)
UC1854 UC2854 UC3854
Gnd (Pin 1) (ground): All voltages are measured with respect to Gnd. Vee and REF should be bypassed directly to Gnd with an 0.1 µF or larger ceramic capacitor. The timing capacitor discharge current also returns to this pin, so the lead from the oscillator timing capacitor to Gnd should also be as short and as direct as possible.
PKLMT (Pin 2) (peak limit): The threshold for PKLMT is O.OV. Connect this input to the negative voltage on the current sense resistor as shown in Figure 1. Use a resistor to REF to offset the negative current sense signal up to Gnd.
CA Out (Pin 3) (current amplifier output): This is the output of a wide-bandwidth op amp that senses line current and commands the pulse width modulator (PWM) to force the correct current. This output can swing close to Gnd, allowing the PWM to force zero duty cycle when necessary. The current amplifier will remain active even if the IC is disabled. The current amplifier output stage is an NPN emitter follower pull-up and an Bk resistor to ground.
ISENSE (Pin 4) (current sense minus): This is the inverting input to the current amplifier. This input and the non-inverting input Mult Out remain functional down to and below Gnd. Care should be taken to avoid taking these inputs below --0.5V, because they are protected with diodes to Gnd.
VRMS (Pin 8) (RMS line voltage): The output of a boost PWM is proportional to the input voltage, so when the line voltage into a low-bandwidth boost PWM voltage regulator changes, the output will change immediately and slowly recover to the regulated level. For these devices, the VRMS input compensates for line voltage changes if it is connected to a voltage proportional to the RMS input line voltage. For best control, the VRMS voltage should stay between 1.5V and 3.5V.
REF (Pin 9) (voltage reference output): REF is the output of an accurate 7.5V voltage reference. This output is capable of delivering 10mA to peripheral circuitry and is internally short circuit current limited. REF is disabled and will remain at OV when Vee is low or when ENA is low. Bypass REF to Gnd with an 0.1 µF or larger ceramic capacitor for best stability.
ENA (Pin 10) (enable): ENA is a logic input that will enable the PWM output, voltage reference, and oscillator. ENA also will release the soft start clamp, allowing SS to rise. When unused; connect ENA to a +5V supply or pull ENA high with a 22k resistor. The ENA pin is not intended to be used as a high speed shutdown to the PWM output.
VSENSE (Pin 11) (voltage amplifier inverting input): This is normally connected to a feedback network and to the boost converter output through a divider network.
Mult Out (Pin 5) (multiplier output and current sense plus): The output of the analog multiplier and the non-inverting input of the current amplifier are connected together at Mult Out. The cautions about taking lsENSE below --0.5V also apply to Mult Out. As the multiplier output is a current, this is a high impedance input similar to lsENSE, so the current amplifier can be configured as a differential amplifier to reject Gnd noise. Figure 1 shows an example of using the current amplifier differentially.
IAC (Pin 6) (input AC current): This input to the analog multiplier is a current. The multiplier is tailored for very low distortion from this current input (IAc) to Mult Out, so this is the only multiplier input that should be used for sensing instantaneous line voltage. The nominal voltage on IAC is 6V, so in addition to a resistor from IAC to rectified 60Hz, connect a resistor from IAe to REF. If the resistor to REF is one fourth of the value of the resistor to the rectifier, then the 6V offset will be cancelled, and the line current will have minimal cross-over distortion.
VA Out (Pin 7) (voltage amplifier output): This is the output of the op amp that regulates output voltage. Like the current amplifier, the voltage amplifier will stay active even if the IC is disabled with either ENA or Vee. This means that large feedback capacitors across the amplifier will stay charged through momentary disable cycles. Voltage amplifier output levels below 1V will inhibit multiplier output. The voltage amplifier output is internally limited to approximately 5.8V to prevent overshoot. The voltage amplifier output stage is an NPN emitter follower pull-up and an Bk resistor to ground.
RsET (Pin 12) (oscillator charging current and multiplier . limit set): A resistor from RsET to ground will program oscillator charging current and maximum multiplier output. Multiplier output current will not exceed 3.75V divided by the resistor from RsET to ground.
SS (Pin 13) (soft start): SS will remain at Gnd as long as the IC is disabled or Vee is too low. SS will pull up to over
av by an internal 14µA current source when both Vee be-
comes valid and the IC is enabled. SS will act as the reference input to the voltage amplifier if SS is below REF. With a large capacitor from SS to Gnd, the reference to the voltage regulating amplifier will rise slowly, and increase the PWM duty cycle slowly. In the event of a disable command or a supply dropout, SS will quickly discharge to ground and disable the PWM.
CT (Pin 14) (oscillator timing capacitor): A capacitor from CT to Gnd will set the PWM oscillator frequency according to this relationship:
F= 1.25 RsETx Cr
Vee (Pin 15) (positive supply voltage): Connect Vee to a stable source of at least 20mA above 17V for normal operation. Also bypass Vee directly to Gnd to absorb supply current spikes required to charge external MOSFET gate capacitances. To prevent inadequate GT Drv signals, these devices will be inhibited unless Vee exceeds the upper under-voltage lockout threshold and remains above the lower threshold.
5-221
PIN DESCRIPTIONS (cont.)
GT Orv (Pin 16) (gate drive): The output of the PWM is a totem pole MOSFET gate driver on GT Drv. This output is internally clamped to 15V so that the IC can be operated with Vee as high as 35V. Use a series gate resistor of at least 5 ohms to prevent interaction between the gate im-
UC1854 UC2854 UC3854
pedance and the GT Drv output driver that might cause the GT Drv output to overshoot excessively. Some overshoot of the GT Drv output is always expected when driving a capacitive load.
TYPICAL CHARACTERISTICS at TA =TJ =25°C
Current Amplifier Gain and Phase vs Frequency
Phase Margin degrees
120 b.,
100
80 1--
60
Open-Loop 40
Gain 20
dB
0
-20 0.1
N
1"1
"""""1
10
100
Frequency kHz
1000 10000
Gate Drive Rise and Fall Time
700
600
500
ns
400
300
200
100
0 0
0.01
0.02
0.03
.0.04
0.05
Load Capacitance, µF
Multiplier Output vs Voltage on Mult
600
Voltage Amplifier Gain and Phase vs Frequency
120 Phase Margin 100
degrees 80 1'-
60
Open-Loop 40
Gain 20
dB
0
-20 0.1
"'1--
r--
N
10
100
Frequency kHz
'
t-....
1000 10000
Gate Drive Maximum Duty Cycle
100%
95%
~-~~~~~~-~~~~~~
~ 1---+--+--+-++++H~-""""+--+--+-+--+-+++I
90% l---+--+--+-++~-lkH----1---+-+-+-+-+-t-H
Duty
Cycle 853
JL'.
00%>----+--+-JL--l-+--+-++++-----'--+-+-+-+--++l-j
75% f---4---¥--+--+-+-++-H---+---!-+-+-++-++;
10
100
RSET, k!J
Oscillator Frequency vs RsET and CT
Multiplier Output 300 1---+-+----+-hi~-+--+--+---I
µA
100
0 1()() 200 300 400 500 600 700 800 IAC,µA
5-222
10
100
RSET, kQ
TYPICAL CHARACTERISTICS at TA= TJ = 25°C cont. Multiplier Output vs Multiplier Inputs with Mult Out::OV
600 VRMS=1.5V
500
400
300 MultOut
µA 200 l----+---.iL-+---+--=--"""'-+-----1
UC1854 UC2854 UC3854
0
100 200
300
400
500
IAC,µA
0
100
200
300
400
500
IAC,µA
160
140
120
100 MultOut
µA 80 80
40
20 0 0
100
200
300
IAC,µA
400
500
140 ~-~----~-----
VRMS=5V 120
100
MultOut,80
µA 60 1----+--7'1----t--=:s-~~---1
0
100
200
300
400
500
IAC,µA
APPLICATIONS INFORMATION
A250W PREREGULATOR
The circuit of Figure 1 shows a typical application of the UC3854 as a preregulator with high power factor and efficiency. The assembly consists of two distinct parts, the control circuit centering on the UC3854 and the power section. The power section is a "boost" converter, with the inductor operating in the continuous mode. In this mode, the duty cycle is dependent on the ratio between input and output voltages; also, the input current has low switching frequency ripple, which means that the line noise is low. Furthermore, the output Voltage must be higher than the peak value of the highest expected AC line voltage, and all components must be rated accordingly. In the control section, the UC3854 provides PWM pulses (GT Orv, Pin 16) to the power MOSFET gate. The duty
cycle of this output is simultaneously controlled by four separate inputs to the chip:
.1NeUI
eJN.1t
FUNCTION
VSENSE ..........;............. 11 ........... 0utput DC Voltage IAC ................................ 6........... LineVoltage Waveform ISENSE/Mult Out ......... 4/5........... Line Current VRMS ............................ 8 ........... RMS Line Voltage
Additional controls of an auxiliary nature are provided. They are intended to protect the switching power MOSFETS from certain transient conditions, as follows:
INPUT
f!N.1t
FUNCTION
ENA............................ 10........... Start-Up Delay SS .............................. 13........... Soft Start PKLIM .......................... 2 ........... Maximum Current Limit
5-223
APPLICATIONS INFORMATION (cont.)
UC1854 UC2854 UC3854
PROTECTION INPUTS
ENA (Enable): The ENA input must reach 2.5 volts before the REF and GT Orv outputs are enabled. This provides a means to shut down the gate in case of trouble, or to add a time delay at power up. A hysteresis gap of 200mV is provided at this terminal to prevent erratic operation. Undervoltage protection is provided directly at pin 15, where the on/off thresholds are 16V and 1OV. If the ENA input is unused, it should be pulled up to Vee through a current limiting resistor of 1OOk.
SS (Soft start): The voltage at pin 13 (SS) can reduce the reference voltage used by the error amplifier to regulate the output DC voltage. With pin 13 open, the reference voltage is typically 7.5V. An internal current source delivers approximately -14µA from pin 13. Thus a capacitor connected between that pin and ground will charge linearly from zero to 7.5V in 0.54C seconds, with C expressed in microfarads.
PKLIM (Peak current limit): Use pin 2 to establish the highest value of current to be controlled by the power MOSFET. With the resistor divider values shown in Figure 1, the O.OV threshold at pin 2 is reached when the voltage drop across the 0.25 ohm current sense resistor is 7.5V*2k/10k=1.5V, corresponding to 6A A bypass capaci-
tor from pin 2 to ground is recommended to filter out very
high frequency noise.
CONTROL INPUTS
VSENSE (Output DC voltage sense): The threshold voltage for the VsENSE input is 7.5V and the input bias current is typically 50nA The values shown in Figure 1 are for an output voltage of 400V DC. In this circuit, thevoltage amplifier operates with a constant low frequency gain for minimum output excursions. The 47nF feedback capacitor places a 15Hz pole in the voltage loop that prevents 120Hz ripple from propagating to the input current.
IAC (Line waveform): In order to force the line current waveshape to follow the line voltage, a sample of the power line voltage in waveform is introduced at pin 6. This signal is multiplied by the output of the voltage amplifier in the internal multiplier to generate a reference signal for the current control loop. This input is not a voltage, but a current (hence IAe). It is set up by the 220k and 91 Ok resistive divider (see Figure 1). The voltage at pin 6 is internally held at6V, and the two resistors are chosen so that the current flowing into pin 6 varies from zero (at each zero crossing) to about
400µA at the peak of the waveshape. The following formulas were used to calculate these resistors:
RAc = Vpk = 260VAC x v'2 = 91 Ok
/ACpk
400µA
ISENSE/Mult Out (Line current): The voltage drop across the 0.25 ohm current-sense resistor is applied to pins 4 and 5 as shown. The current-sense amplifier also operates with high low-frequency gain, but unlike the voltage amplifier, it is set up to give the current-control loop a very wide bandwidth. This enables the line current to follow the line voltage as closely as possible. In the present example, this amplifier has a zero at about 500Hz, and a gain of about 18dB thereafter.
VRMS (RMS llne voltage): An important feature of the UC3854 preregulator is that it can operate with a three-toone range of input line voltages, covering everything from low line in the US (85VAC) to high line in Europe (255VAC). This is done using line feedforward, which keeps the input power constant with varying input voltage (assuming constant load power). To do this, the multiplier divides the line current by the square of the RMS value of the line voltage. The voltage applied to pin 8, proportional to the average of the rectified line voltage (and proportional to the RMS value), is squared in the UC3854, and then used as a divisor by the multiplier block. The multiplier output, at pin 5, is a current that increases with the current at pin 6 and the voltage at pins 7, and decreases with the square of the voltage at pin 8.
PWM FREQUENCY: The PWM oscillator frequency in Figure 1 is 1OOkHz. This value is determined by CT at pin 14 and RSET at pin 12. RSET should be chosen first because it affects the maximum value of IMULT according to the equation:
-3.75V I M U L T M ARXsE=T- -
This effectively sets a maximum PWM-controlled current. With RSET=15k,
IMULTMAX =1-3.s75kV = -250µA
Also note that the multiplier output current will never exceed twice IAe.
With the 4k resistor from Mult Out to the 0.25 ohm current sense resistor, the maximum current in the current sense resistor will be
IMAX= -IMULTMAX x4k = _4A
0.250
Having thus selected RSET, the current sense resistor, and the resistor from Mult Out to the current sense resistor, calculate CT for the desired PWM oscillator frequency from the equation
Cr 1.25
Fx RsET
RREF = RAc =220k
4
(where Vpk is the peak line voltage)
5-224
UC1854
UC2854
FIGURE 1 - Typical Application
UC3854
This diagram depicts a complete 250 watt Preregulator. At full load, this preregulator will exhibit a power factor of 0.99
at any power line voltage between 80 and 260 VRMS. This same circuit can be used at higher power levels with minor
modifications to the power stage. See Design Note 398 and Application Note U-134 for further details.
+
1N4148
1mH
UHV806
+
385
voe
Out
1.6k 100
910k 91k
0.1µF O.SµF
20k 0.01µF
UDG~lt051M
NOTE: Boost Inductor can be fabricated with ARNOLD MPP toroidal core part numberA-438381-2, using a 55 tum primary and a 13 tum secondary.
UNITRODE INTEGRATED CIRCUITS
7 CONTINENTAL BLVD. · MERRIMACK. NH 03054 TEL (803) 424-2410 · FAX (803) 424-3"480
These products contain patented circuitry and are sold under license from Pioneer Magnetics, Inc.
5-225
n n L':::::::J
INTEGRATED CIRCUITS
-UNITRDDE
Enhanced High Power Factor Preregulator
UC1854A/B UC2854A/B UC3854A/B
PRELIMINARY
FEATURES Controls Boost PWM to Near Unity Power Factor
Limits Line Current Distortion To <3%
World-Wide Operation Without Switches
Accurate Power Limiting
Fixed Frequency Average Current Mode Control
High Bandwidth (5 mHz), Low Offset Current Amplifier
Integrated Current and Voltage Amp Output Clamps
Multiplier Improvements: Linearity, 500mV VAC Offset (eliminates external resistor), 0-5V Multout Common Mode Range
VREF "GOOD" Comparator
Faster and Improved Accuracy ENABLE Comparator
UVLO Threshold Options
(16/1 ov I 10.5/10V)
300µA Startup Supply Current
UVLOTumon UVLO Turn off
UC1854A
16V
10V
UC1854B
10.SV
10V
DESCRIPTION
.
The UC1854A/B products are pin compatible enhanced versions of the
UC1854. Like the UC1854, these products provide all of the functions
necessary for active power factor corrected preregulators. The control-
ler achieves near unity power factor by shaping the AC input line cur-
rent waveform to correspond to the AC input line voltage. To do this the
UC1854A/B uses average current mode control. Average current mode
control maintains stable, low distortion sinusoidal line current without
the need for slope compensation, unlike peak current mode control.
The UC1854A/B products improve upon the UC1854 by offering a wide bandwidth, low offset Current Amplifier, a faster responding and improved accuracy enable .comparator, a VREF "good" comparator, UVLO
threshold options (16/1 ov for Offline, 10.5/1 ov for startup from an auxil-
iary 12V regulator), lower startup supply current, and an enhanced multiply/divide circuit. New features like the amplifier output clamps, improved amplifier current sinking capability, and low offset VAC pin reduce the external component count while improving performance. Improved common mode input range of the Multiplier output/Current Amp input allow the designer greater flexibility in choosing a method for current sensing. Unlike its predecessor, RsET controls only oscillator charging current and has no effect on clamping the maximum multiplier
outpu(current. This current is now clamped to a maximum of 2 * IAC at
all times which simplifies the design process and provides foldback power limiting during brownout and extreme low line conditions.
A 1.% 7.5V reference, fixed frequency oscillator, PWM, Voltage Amplifier with softstart, line voltage feedforward (VRMS squarer), input supply voltage clamp, and over current comparator round out the list of features.
Available in the 16 pin N, DW, and J and 20 pin Land Q packages.
BLOCK DIAGRAM
5/93
ISENSE CT 5-226
RSET
UDG-93001
UC1854A/B UC2854A/B UC3854A/B
ELECTRICAL
Unless otherwise stated, Vcc=18V, Rr=8.2k, CT=1.5nF, PKLMT=1V, VRMS=1.5V, IAC=100µA,
CHARACTERISTICS ISENSE=OV, CA Out=4V, VA Out=3.5V, VsENSE=3V, -55°C<TA<125°C for the UC1854A/B,
-40°C<TA<85°C for the UC2854AJB, and o"C<TA<70°C for the UC3854AJB, and TA=TJ.
PARAMETER
TEST CONDITIONS
OVERALL
Supply Current, Off
CAO, VAO = OV, Vee = UVLO - 0.3V
S~ly Current, On
Vee Turn-On Threshold
UC1854A
UC1854B
Vee Tum-Off Threshold
UC1854A/B
VccClamJ!_
f.Wc_l_= Ice~!]_+ 5mA
VOLTAGE AMPLIFIER
I~ Offset Volta....!!!_
VSENSE Bias Current
Open Loop Gain
Vour = 2to5V
VOUT High
ILOAD = -500!1A
VourLow
ILOAD = 500µA
Oulj:llJt Short Circuit Current
VouT=OV
Gain Bandwidth Product
Fin = 1OOkHz, 1OmV p-p, (Note 1)
CURRENT AMPLIFIER
Input Offset Voltage
VcM=2.5V
I~ Bias Currentj_sense_l_
VCM=2.5V
Open Loop Gain
VcM = 2.5V, Your= 2 to 6V
VourH.!9._h
ILOAD = -500µA
VourLow
ILOAD = 500µA
Output Short Circuit Current
VOUT=OV
Common Mode Ran_ge
Gain Bandwidth Product
Fin = 1OOkHz, 1OmV e:ei (Note 1)
REFERENCE
Output Voltage
IREF = OmA, TA= 25°C
IREF=OmA
Load Regulation
IREF = 1to10mA
Line R~ulation
VCC= 12to18V
Short Circuit Current
VREF=OV
OSCILLATOR
Initial Accura~
TA=25°C
Voltage StabHlty
Vee= 12to 18V
Total Variation
Line, Tem...1!_
Ramp Anli>fltude (p:pJ
Ramp Valley Vol~
ENABLE I SOFTSTART I CURRENT LIMIT
Enable Threshold
Enable Hj'll!9resis
VFAULT = 2.5V
Propagation Delay to Disable
Enable overdrive =-100mV, (Note 1)
SS Char_ge Current
VSOFTSTART = 2.5V
PKLMT Offset Volta~
PKLMT Input Current
VPKLMT=-0.1V
PKLMT Propagation Delay
(Note 1)
MIN
9 18 -8
-500 70
-2 -500
80
-0.3 3
7.425 7.35 -15 -10 25 85 80 4.8 0.8 2.4
6 -10 -200
lYP
250 12 16 10.5 10 20
-25 100
6 0.3 1.5 1
110 8 0.3 1.5
5
7.5 7.5
35
100 1
2.55 500 300 14
-100 150
MAX
400 18 17.5 10.8
22
8 500
0.5 3
0 500
0.5 3 5
7.575 7.65 15 10 45
115
120 5.6 1.3
2.7 600
20 10
UNITS
µA mA
v v v v
mV nA dB
v v
mA mHz
mV nA ---1 dB
v v
mA
v
mHz
v v
mV mV mA
kHz % kHz
v v
v
mV ns
mV µA ns
5-2Z7
UC1854A/B UC2854A/B UC3854A/B
ELECTRICAL
Unless otherwise stated, Vee=18V, Rr=8.2k, CT=1.5nF, PKLMT=1V, VRMS=1.5V, 1Ae=100µA,
CHARACTERISTICS (cont.) lsENSE=OV, CA Out=4V, VA Out=3.5V, VsENSE=3V, --55°C<TA<125°C for the UC1854NB,
-40°C<TA<85°C for the UC2854NB, and 0°C<TA<70°C for the UC3854NB, and TA=TJ.
PARAMETER MULTIPLIER
Output Current - IAe Limited Out_.E_ut Current - Zero Output Current - Power Limited Output Current
Gain Constant GATE DRIVER
Output High Voltage Output Low Voltage
Out_.E_Ut Low_(UVLQ)_
Output Rise I Fall Time
Output Peak Current
TEST CONDITIONS
1Ae=100µA, VRMS = 1V IAe=O(.IA VRMS = 1.5V, Va= 6V VRMS = 1.5V, Va= 2V VRMS= 1.5V, Va= 5V VRMS = 5V, Va= 2V VRMS = 5V, Va= 5V (Note 2)
lour = -200mA, Vee = 15V lour= 200mA lour= 10mA lour = 50mA, Vee = OV CLOAD = 1nF,_Q-lote 1) CLOAD = 1OnF' (Note 1)
MIN -220 -2.0 -220
-1.1 12
TYP
-200 -0.2 -200 -22 -156 -2 -14 -1.0
12.8 1
300 0.9 35 1.0
MAX -180 2.0 -180
-0.9
2.2 500 1.5
UNITS
µA uA µA uA µA µA µA NA
v v
mV
v
ns A
Note 1: Guaranteed by design, not 100% tested in production.
. Note 2: Gain constant (K)
= /ACX
(Va-1.5V) 2
where
1.5V s
VRMS s
511.
VRMS x IMO
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. · MERRIMACK. NH 03064 TEL. (603) 424-2410 · FAX (603) 424-,._
These products contain patented circuitry and are sold under license from Pioneer Magnetics, Inc.
5-228
r1 nINTEGRATED
~CIRCUITS
-UNITRODE
Improved Current Mode PWM Controller
UC1856 UC2856 UC3856
FEATURES
· Pin for pin compatible with the UC1846
65ns typical delay from shutdown to outputs, and 50ns typical delay from sync to outputs.
Improved current sense amplifier with reduced noise sensitivity.
· Differential current sense with 3V common mode range.
· Trimmed oscillator discharge current for accurate deadband control.
· Accurate 1V shutdown threshold.
· High current dual totem pole outputs (1.5A peak).
· TIL compatible oscillator sync pin thresholds.
· 4kV ESD protection.
DESCRIPTION
The UC1856 is a high performance version of the popular UC1846 series of current mode controllers, and is intended for both design upgrades and new applications where speed and accuracy are important. All input to output delays have been minimized, andthe Current Sense output is slew rate limited to reduce noise sensitivity. Fast 1.5 amp peak output stages have been added to allow rapid switching of power FET's.
A low impedance TTL compatible sync output has been implemented with a tri-state function when used as a sync input.
Internal chip grounding has been improved to minimize internal "noise" caused when driving large capacitive loads. This, in conjunction with the improved differential current sense amplifier results in enhanced noise immunity.
Other features include a trimmed oscillator current (8%) tor accurate frequency
and dead time control; a 1 volt, 5% shutdown threshold; and 4kV minimum ESD protection on all pins.
BLOCK DIAGRAM
VIN SYNC
f-----------1_~2 VREF
(-)CUR SENSE (+)CUR 4 SENSE
NI /NV
12/92
5-229
OUTPUTS
GND
CURRENT LIMIT ADJUST SHUTDOWN
ABSOLUTE MAXIMUM RATINGS (Note 1) Supply Voltage (Pin 15) ...............................................................................................+40V Collector Supply Voltage (Pin 13) ................................................................................+40V Output Current, Source or Sink (Pins 11, 14)
DC ..................................................................................................................0.5A Pulse (0.5µs) ..................................................................................................2.0A
Error Amp Inputs (Pins 5, 6) ............................................................................-0.3V to +V1N Shutdown Input (Pin 16) .................................................................................-0.3Vto +10V
Current Sense Inputs (Pins 3,4) ......................................................................-0.3V to +3V Sync Output Current (Pin 10) ...................................................................................±1 OmA Error Amplifier Output Current (Pin 7) .........................................................................-5mA Soft Start Sink Current (Pin 1) ....................................................................................50mA Oscillator Charging Current (Pin 9) ...............................................................................5mA Power Dissipation at TA= 25°C (Note 2) ............................................................... 1000mW Power Dissipation at Tc= 25°C (Note 2) ...............................................................2000mW Storage Temperature Range ....................................................................-65°C to+150°C
Lead Temperature (soldering, 1oseconds) ............................................................. +300°C
Note: 1. All voltages are with respect to Ground, Pin 12.
Currents are positive into, negative out of the specified terminal. Pin numbers and thermal ratings refer to the DIL-16 Package. Note: 2. Consult packaging section of databook for thermal limitations and considerations of package.
UC1856 UC2856 UC3856
CONNECTION DIAGRAMS
DIL-16 (TOP VIEW)
J or N PACKAGE
Current Limit/ Soft Start VREF
(-) Current Sense
(+) Current Sense 4
(+) Error Amp 5 (-) Error Amp 6
Compensation
1 Output A Sync Rr
PLCC-Q PACKAGE (TOP VIEW)
1 - N/C 2 - Current Limit/Solt Start 3 - VREF 4 - (-) Current Sense 5 - (+) Current Sense 6-N/C 7 - (+) Error Amp 8 - (-) Error Amp 9 - Compensation 10 - Cr
SOIC-16 (TOP VIEW) OW PACKAGE
Current Limit/ Soft Start VREF
(-) Current Sense (+)Current Sense
(+) Error Amp (-) Error Amp Compensation
Cr
20 - Shutdown
19 - V1N 18 - Output B 17 - Ve 16 - N/C 15 - Ground 14- Output A 13 - SYNC 12 - Rr 11 - N/C
OTHER PACKAGES AVAILABLE:
28-PIN OP 28-PIN L
5-230
Shutdown
\1N
Output B
Ve Ground
Output A
Sync
RT
ELECTRICAL CHARATERISTICS (Unless otherwise stated, these specifications apply for T/\ = -55°C to +125°C for
v," UC1856; - 40°C to +85°C for the UC2856; and o·c to +70°C for the UC3856, =15V, R1=1 OK, C1=1 nF) TA=TJ, Pin No.'s
Refer to OIL Package.
UC1856 UC2856 UC3856
PARAMETER
TEST CONDITIONS
UC1856 UC2856
UC3856
UNITS
MIN TYP MAX MIN TYP MAX
Reference Section
Ou1put Voltage
Ti=25°C, lo=1mA
5.05 5.10 5.15 5.00 5.10 5.20
v
Line Regulation
Vin=8to 40V
20
20
mV
Load Regulation
lo=-1mA to -10mA
15
15
mV
Total Output Variation
Line, Load, and Temperature 5.00
5.20 4.95
5.25
v
Output Noise Voltage
10Hz<f<1 OKHz, Tj=25°C
50
50
uV
Long Tarm Stability
Ti= 125°C, 1OOOHrs (Note 2)
5
25
5 25
mV
Short Circuit Current Oscillator Section
Initial Accuracy Voltage Stability
Vref=OV
Ti=25°c Over Operating Range Vin= 8 to 40V
-25 -45 -65 -25 -45 -65
mA
180 200 220 180 200 220
KHz
170
230 170
230
KHz
2
2
%
Discharge Current
Sync Output High Level Sync Output Low Level Sync Input High Level Sync Input Low Level
Tj=25°C, Vpin8=2V Vpin8=2V lo=-1mA lo=+1mA Pin 8=0V, Pin 9=Vref Pin 8=0V, Pin 9=Vref
7.5 8.0
8.8
7.5 8.0 8.8
mA
6.7 8.0
8.8
6.7 8.0 8.8
mA
2.4 3.6
2.4 3.6
v
0.2
0.4
0.2 0.4
v
2.0 1.5
2.0 1.5
v
1.5
0.8
1.5 0.8
v
Sync Input Current
Pin 8=0V, Pin 9=Vref Vsync=5V
1
10
1
10
uA
Sync Delay to Outputs
Error Amp Section Input Offset Voltage Input Bias Current
Pin 8=0V, Pin 9=Vref Vsync=0.8V to 2V
Vcm=2V
50
100
5 -1
50 100
ns
10
mV
-1
uA
Input Offset Current Common Mode Range Open Loop Gain
Vin=8 to 40V Vo=1.2 to 3V
500
500
nA
0
Vin-2 0
Vin-2
v
80
100
80
100
dB
Unity Gain Bandwidth CMRR PSRR Output Sink Current
Tj=25°C Vcm=O to 38V, Vin=40V Vin=8to40V Vid=-15mV, Vpin7=1.2V
1
1.5
75
100
80
100
5
10
1
1.5
75
100
80
100
5
10
MHz dB dB mA
Output Source Current
Vid=15mV, Vpin7=2.5V
-0.4 -0.5
-0.4 -0.5
mA
Output High Level
Vid=50mV, RL (pin 7)=15K
4.3 4.6
4.9
4.3 4.6 4.9
v
Output Low Level
Vid=-50mV, RL (pin 7)=15K
0.7
1
0.7
1
v
Current Sense Amplifier Section
Amplifier Gain
Vpin3=0V, Pin1 Open (Notes 3,4) 2.5 2.75 3.0
2.5 2.75 3.0
VN
Maximum Differential
Pin 1 Open (Note 3)
Input Signal (Vpin4-Vpin3) RL (pin 7)=15K
1.1 1.2
1.1 1.2
v
Input Offset Voltage
Vpin1=0.5V Pin? Open (Note 3)
5
35
5
35
mV
CMRR PSRR Input Bias Current
Vern= o to 3V
60
60
dB
Vin= 8 to 40V
60
60
dB
Vpin1 =0.5V, Pin 7 Open (Note 3)
-1
-3
-1
-3
uA
5-231
ELECTRICAL CHARACTERISTICS (Unless otherwise stated, these specifications apply for T~ = - 55°C to+125°C for
UC1856; -40°C to +85°C for the UC2856; and o·c to +70°C for the UC3856, V," =15V, RT=1uK, CT=1nF) TA=TJ Pin No.'s
Refer to OIL Package.
UC1856 UC2856 UC3856
PARAMETER
TEST CONDITIONS
UC1856 UC2856
Current Sense Amplifier Section (Continued)
MIN
Input Offset Current
Vpin1 =0.5V, Pin 7 Open (Note 3)
Input Common Mode Range
0
Delay to Outputs
Vpin5=Vref, Pin6=0V Pin4 - Pin3= o to 1.5V
Current Limit Adjust Section
Current Lim~ Offset
Vpin3=0V Vpin4=0V, Pin7=0pen (Note 3)
Input Bias Current
Vpin5=Vref, Vpin6=0V
Shutdown Terminal Section
Threshold Voltage
Input Voltage Range
0.43
0.95 0
Minimum Latching
(Note 5)
3
Current (lpin1)
TYP
120 0.5 -10 1.00 1.5
MAX
1 3 250
0.57 -30 1.05 5
Maximum Non-Latching Current (lpin1)
(Note6)
Delay to Outputs Output Section
Vpin16=0 to 1.3V
Collector-Emitter Voltage Off-State Bias Current
Vc=40V
Output Low Level
Output High Level Rise Time Fall Time UVLO Low Saturation
lout=20mA lout= 200mA lout=-20mA lout= - 200mA C1= 1nF C1= 1nF Vin=OV, lout=20mA
PWMSection Maximum Duty Cycle Minimum Duty Cycle Under-Voltage Lockout Section Start-l!.e_Threshold Threshold Hysterisis Total Standby Current Supply Current
1.5
0.8
65
110
40 250
0.1
0.5
0.5
2.6
12.5 13.2
12 13.1
40
80
40
80
0.8 1.5
45
47
50
0
7.7
8.0
0.7
18
23
UC3856 MIN TYP MAX
1
0
3
120 250
0.43 0.5 0.57 -10 -30
0.95 1.00 1.05
0
5
3 1.5
1.5 0.8 65 110
40
250
0.1 0.5
0.5 2.6 12.5 13.2
12 13.1
40
80
40
80
0.8 1.5
45
47 50
0
7.7 8.0 0.7
18 23
UNITS
uA
v
ns
v
uA
v v
mA
mA
ns
v
uA
v v v v
ns ns
v
% %
v v
mA
NOTES:
1. All voltages are with respect to pin 12. Currents are positive into, negative out of the specified terminal.
2. This parameter, although guaranteed over the recommended operating conditions is not 100% tested in production.
3. Parameter measured at trip point of latch with VpinS=Vref, Vpin6=0V.
4. Amplifier gain defined as:
,6.Vpin7 G=---;
6Vpin4
,6.Vpin4=0 to 1.0V
5. Current into pin1 guaranteed to latch circuit into shutdown state
6. Current into pin 1 guaranteed not to latch circuit into shutdown state
5-232
APPLICATIONS DATA Oscillator Circuit
UC1856 UC2856 UC3856
9
SAWTOOTH
8
(PIN 8)
osc.
n n
(PIN 10)_ _ _~ ~--~ ~---
-1 1-
10
0UTPUT DEADTIME ( Td)
SYNC
-(~) Output deadtime is determined by size of the external capacitor, Cr , according to the formula: rd -
SmA-~
For large values of Rr: rd. 250C T
Rr
Oscillator frequency is approximated by the formula: fr= - 2RT CT
Error Amp Output Configuration
0.5mA 5
6
11 <0.5mA Error Amplifier can source up to 0.5mA.
7 COMP.
Error Amp Gain and Phase vs Frequency
ro- 80
~
z ~ 60
w CJ
~ 40
~
9"- 20
z
w
0
~
V1N = 2DV
ISl
,, TJ =25°C 0
JS.]
ts. ~ ~ ~
m z
§,,,,
~
CJ)
m
~
'b. o·
"0 -
-90°
N
-1so0
100 1K 10K 100K 1M
FREQUENCY (Hz)
Error Amp Open-Loop 0.C, Gain vs Load Resistance
110
V1N = 2DV
iD
~
z 100
~
!---":r--
TJ =2s0 c -
w
(!)
<(
~
> 0
90
~
J_
l Q_
g0 80
z
I
w
Q_
0
~L t--1-t - -1 - -
70
0 10 20 30 40 50 60 70 80 90 100
OUTPUT LOAD RESISTANCE, AL (K-OHMS)
5-233
Parallel Operation
9 Rr
8 CT
VREF
+E/A
MASTER SYNC
COMP -E/A
I
Rr
2
ICT
10
7
"::"
10
7
6 "::"
9 VREF +E/A
SYNC
COMP -E/A
Rr
SLAVE
(ADDITIONAL UNITS)
I
"::"
Slaving allows rarallel operation of two or more un~s with aqua current sharing.
Pulse by Pulse Current Limiting
Is (+) 4
Rs (-) 3 +
o.sv
1 CURRENT LIMIT
COMP 7
"""
~ Peak Current (Is) is detennined by the fonnula: Is= (
) - O.S
3Rs
UC1856 UC2856 UC31356
OUTPUT FILTERS
5-234
Soft Start and Shutdown/Restart Functions
r ':"
VREF R1
lss R2
':"
CURRENT LIMIT
UC1856 UC2856 UC3856
r- +
-::- 1.0V
SHUTDOWN WITH AUTO-RESTART
SHUTDOWN WITHOUT AUTO-RESTART (LATCHED)
CURRENT LIMIT (PIN 1)
0.5V- - - - - - - - - - - - - - - - -
---
- - - - - - - - ~.
o--~
SHUTDOWN
:;(P;IN-1-6-) i_____~n~-------
r---- ----------
PWM
[LJl_ _
If VAEF < 0.8mA, the shutdown latch will commutate R1
when 188 = O.BmA and a restart cycle will be initiated.
If VREF > 3mA, the device will latch off R1
until power is recycled.
5-235
Current Sense Amp Connections
Is~
R
Rs
C
UC1856 UC2856 UC3856
-=
A small RC filter may be required in some applications to reduce sw~ch transients. Differential input allows remote, noise free sensing.
UC1856 Open Loop Test Circuit
TIMING RESISTOR:
FREQ. SET& MAX DUTY CYCLE RT
2 9
15
SAWTOOTH
/ \ TIMING CAP CT 2N2222 1K
-= -= -=
1 I 1 _l _l _!_
0.1µF
1nF 4.?nF
::- Is+ -=
-=
SENSE ADJUST (=1VPEAK)
-=
COMP
DUTY CYCLE +SV INV ADJUST
10 8
UC1856 16 4
13 7
14 6
VREF (+5.1 V OUTPUT)
I-= 0.1µF
I-= 0.1µF
~'J 2K +0.1µF - lK
lfiN (+15V)
SYNC
SHUTDOWN Ve (+15V)
I1µF
::-
OUTA
+5V
11
400Q
CURRENT LIMIT 1K
ADJUST
10TURN
::-
"i NON INV -=
I 0.1fiF IL DJ ::-
+ 5
12
-=
3
Is-
GROUND FOR
_t NORMAL OPERATION
::-
-BYPASS CAPS SHOULD BE LOW ESR & ESL TYPE -SHORT PINS 6 & 7 FOR UNITY GAIN TESTING
THE USE OF A GROUND PLANE IS HIGHLY RECOMMENDED
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD.· MERRIMACK. NH 03054
TEL 603-424-2410 · FAX 603-424-3460
5-236
n .n L'.=:::J INTE!aRATED CIRCUITS
-UNITRCCE
Resonant Mode Power Supply Controller
(~)
UC1860 UC2860 UC3860
FEATURES 3MHz VFO Linear over 100:1 Range
5MHz Error Amplifier with Controlled Output Swing
Programmable One Shot TimerDown to 1oons
Precision 5V Reference
Dual 2A Peak Totem Pole Outputs
Programmable Output Sequence Programmable Under Voltage Lockout Very Low Start Up Current Programmable Fault Management & Restart Delay Uncommitted Comparator
DESCRIPTION
The UC1 860 family of control ICs is a versatile system for resonant mode power supply control. This device easily implements frequency modulated fixed-on-time control schemes as well as a number of other power supply control schemes with its various dedicated and programmable features.
The UC1860 includes a precision voltage reference, a wide-bandwidth error amplifier, a variable frequency oscillator operable to beyond 3MHz, an oscillator-triggered one-shot, dual high-current totem-pole output drivers, and a programmable toggle flip-flop. The output mode is easily programmed for various sequences such as A, off, B, off; A & B, off; or A, B, off. The error amplifier contains precision output clamps that allow programming of minimum and maximum frequency.
The device also contains an uncommitted comparator, a fast comparator for fault sensing, programmable soft start circuitry, and a programmable restart delay. Hie-up style response to faults is easily achieved. In addition, the UC1860 contains programmable under voltage lockout circuitry that forces the output stages low and minimizes supply current during start-up conditions.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (pin 19) . . . . .. .. . . . . . . . . .. . . . . .. . . . . 20V Output Current, Source or Sink (pins 17 & 20)
DC .......................................... 0.8A Pulse (0.5µs) .................................. 3.0A Power Ground Voltage ............................ ±0.2V Inputs (pins 1, 2, 3, 4, 8, 9, 11, 12, 13, 14, 21, 22, 23 &24) ...................... -0.4 to 6V Error Amp Output Current, Source or Sink (pin 5) ........ 2mA IVFO Current (pin 7) ................................ 2mA Comparator Output Current (pin 15) .................. 5mA
Comparator Output Voltage (pin 15) . . . . . . . . . . . . . . . . . . 15V Soft Start or Restart Delay Sink Current (pins 22 & 23) ... 5mA
Power Dissipation at TA= 50°C (DIP) . . . . . . . . . . . . . . . 1.25W
= Power Dissipation at TA 50°C (PLCC) . . . . . . . . . . . . . . . . 1W
Lead Temperature (Soldering, 10 seconds) ........... 300°C
Note: All voltages are with respect to signal ground and all currents are positive into the specified terminal. Pin numbers refer to the DIP. Refer to Packaging Section ofDatabook for thermal limitations and considerations ofpackages.
BLOCK DIAGRAM
Vee UVLO
1 - - - - - - - - - - - - 1 1 IVAEF
6/93
EA IN(+)
EA IN(-)
IVFO CvFo TRIG OSC DSBL
RC MODE CMP IN(+) CMP IN(-) SFT STRT RST DLY FLT(+) FLT(-)
S<H>O
:>------+----+-----! 1EA OUT OUT A OUT B PGND
·....---+-1------+-----; 1CMP OUT
5-237
CONNECTION DIAGRAM
OIL - 24 (TOP VIEW) J or N Package
FLT(·) 1 FLT(+) 2 EA IN(+) · EA IN(·) · EA OUT · S GND ·
CMP IN(·) 11 CMP IN(+) 12
1· CMP OUT 14 OSC DSBL 13 TRIG
UC1860 UC2860 UC3860
PLCC-28, LCC·28 (TOPVIEW) Q or L Package
L -=-=-=-=-=-= 4 3 2 1 292126
5
25~
6
24~
7
23~
8
22~
9
21~
10
20 ~
11
19 ~
12131415161718
~
~
PIN PACKAGE FUNCTION
FUNCTION
PIN
SGND
1
IVFO
2
CvFO
3
RC
4
VREF
5
CMP INJ:l_
6
CMP INJ±}_
7
TRIG
8
OSCDSBL
9
CMPOUT
10
N/C
11 12
OUTA
13
PGND
14
N/C
15
Vee
16
OUTB
17
N/C
18 19
MODE
20
SFTSTRT
21
RSTDLY
22
UVLO
23
FLT_B_
24
FLTJ±l
25
EAINJ±l
26
EAIN_B_
27
EA OUT
28
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, all specifications apply for -55°C :s TA :s 125°C for the
UC1860, ·25°C :sTA :s85°C for the UC2860, O:s TA:s 70°C forthe UC3860, Vee=
c 12V, CvFO = 330pF, IVFO = 0.5mA, = 330pF, and R = 2.7k, TA= TJ.
PARAMETER
CONDITIONS
Reference Section
Output Voltage
TA=25°C,lo=0
lo = 0, Over Tern..£_
Line R~ulation
10:sVee:s 20V
Load R~ulation
O:s lo :s 10mA
O~ut Noise Volta_g_e*
1OHz :sf :s 10kHz
Short Circuit Current
VREF =OV
Error Am_2.!ifier Section
l~t Offset Volt~e
2.8 :s VeM :s 4.5V
lni:>_ut Bias Current
Qe_en Lo~Gain
dVo = 1.5V
PSRR
10:sVee :s 20V
Ol!!Q_ut Low~-VIVF<?)_
-0.1:slo:s0.1mA
Ou~ut Hjg!l~-VIVFQ)_
·0.5 :s lo :s 0.5mA
Unjty Gain Bandwidth*
RIN = 2k
Oscillator Section
Nominal FrE!<I_uen~
df/dlose*
100 :s IVFO :s 500µA
*Guaranteed by design but not 100% tested.
MIN
4.95 4.93
·150
60 70 ·8 1.9 4 1.0 2
TYP
5.00
2 2 50
1 50 80 100 0 2 5
1.5 3
MAX UNITS
5.05
v
5.07
v
15
mV
25
mV
..!:!:._YAMS
·15
mA
8
mV
500
nA
dB
dB
8
mV
2.1
v
MHz
2.0
MHz
4
GHz/A
5-238
UC1860 UC2860 UC3860
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, all specifications apply for -55°C s TA s 125°C for the
o uc1860, -25° s TA s 85°C for the UC2860, s TA s 70°C for the UC3860, Vee= c 12V, CvFO = 330pF, IVFO = 0.5mA, = 330pF, and R = 2.7k, TA= TJ.
PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS
Oscillator SectionJ.cont'c!l Tr!g_ in Threshold Tr!g_ in O_Q_en Circuit Volt'!9.e Trig in Delta (VTH-VOC) Ti:!g_in lr:i.E._ut Resistance Minimum Tr!g_in Pulse Width* Osc. Disable Threshold
One Shot Timer
dV TRIG "' Voe to VTH
1.0
1.4
1.8
v
0.7
0.9
1.1
v
0.3
0.5
0.7
v
5
12
25
kQ
3
10
ns
1.0
1.4
1.8
v
On Time* Clamp Frequency* DeadTime* Ou!l!_ut St!9._e Output Low Saturation
Output High Saturation
IVFO = 1.5mA IVFO =1.5mA
20mA 200mA -20mA -200mA
150
200
250
ns
2.8
3.7
4.6
MHz
35
70
100
ns
0.2
0.4
v
0.5
2.2
v
1.5
2.0
v
1.7
2.5
v
Rise/Fall Time* UVLO Low Saturation Ou_!Q_ut Mode Low IQ.E>.Ut Output Mode High Input Under Volt~e Lockout Section Vee Comparator Threshold
UVLO Comparator Threshold
CLOAD = 1nF 20mA
On Off On '::l:t!>teresis
15
30
ns
0.8
1.5
v
0.4
v
2.0
v
16
17.3
18.5
v
9.5
10.5
12
v
3.6
4.2
4.8
v
0.2
0.4
0.6
v
UVLO lnQ.ut Resistance VREF Comparator Threshold
S~Current
UVLO = 4Ncc = 8 Vee = UVLO = VREF
10
23
50
kQ
4.5
4.9
v
Ice
Vee= 12V, Vose DSBL = 3V
30
40
mA
ISTART Fault Comparator
UVLO pin open Vee= VccJ.o~ -0.3V
0.3
0.5
mA
IQ.E>_ut Offset Volt<!!9_e IQ.E>_ut Bias Current Input Offset Current Pr~ation Del~To Ou_!Q_ut* Uncommitted Coll!l>.arator
-0.3 s VcM s 3V VcM =OV VcM =OV ±50mViQ.E>_ut
2
10
mV
100
200
~
10
30
µA
100
150
ns
Input Offset Voltage lr:!E_ut Bias Current lr:!E_ut Offset Current Ou!e._ut Low Volt"!9._e
Pr~ation Del~ToSat*
-0.3 s VcM s 3V VCM= OV VcM = OV lo=2mA ±50mV ir:!E_ut, 2.5k load to 5V
2
10
mV
100
200
~
10
30
~
0.3
0.5
v
50
100
ns
Soft Start/Restart Control Section
Saturation Volt"!9._e12~n~
ISINK = 1OOµA
Cha!:fl._e Current12~n~
Restart Del~Th~eshold
*Guaranteed by design but not 100% tested.
0.2
0.5
v
2
5
10
~
2.8
3.0
3.2
v
5-239
ERROR AMPLIFIER
The error amplifier is a high gain, low offset, high bandwidth design with precise limits on its output swing. The bandwidth of the amplifier is externally determined by the resistance seen at the inverting input. Unity gain bandwidth is approximately:
Frequency (OdB) = 1/{2n * RIN (-) * CCOMP)
The input common mode range of the amplifier is from 2.8 to 4.5V. As long as one pin is within this range, the other can go as Iowas zero.
The output swing with respect to the lvFo pin is limited from zero to 2V. Note that pulling Sft Strt (soft start) low will lower the reference of the upper clamp. The lower clamp, however, will dominate should the upper clamp reference drop below the lower reference.
/::,. V10 vs \CUT
UC1860 UC2860 UC3860
S2 0 I-
>
r-
<l
-1
0
2
V(E/A OUT) - VQVFO) (V)
Error Amplifier Frequency Response
-90 80.0
60.0
al
~
40.0
~
ej ~
20.0
0.0
~"!
0
f=
-120
~
::::
m
~ ~
,~t:::!
-150 CD UI Ill
-180 if
-20.0
~
3.3itlj:j j::s -210
0,01 0.03 0.1 0.3 1 3 10 20
F (MHz)
E/A IN (·) E/A IN (+)
UNDER VOLTAGE LOCKOUT SECTION
The under voltage lockout consists of three comparators that monitor Vee, UVLO and VREF. The VREF comparator makes sure that the reference voltage is sufficiently high before. operation begins. When the UVLO comparator is low, the outputs are driven low, the fault latch is reset, the soft start pin is discharged, and the toggle flip-flop is loaded for output A.
The Vee comparator is used for off-line applications by leaving the UVLO pin open. In this application the supply current is typically less than 0.3mA during start-up.
The UVLO comparator is used for DC to DC applications or to gate the chip on and off. To utilize its hysteretic threshold by an external resistive divider, the internal impedance of the pin must be accounted for. To run from a 5V external supply, UVLO, Vee, and VREF are tied together.
lee vs Vee
40
35
I !
30
j
25
UVLO
231<
0.5 0.4 0.3
l
1
0.2 0.1
1--'t'" ..J-lJvLO=OPEN~
0.0
' .l. .l. .l J
O
C
\
l
'
l
t
C
O
C
O
OC\l
.,.... ,...
'ltCO .,.... .,....
CT"'O" CO\I
Vee (V)
5-240
UC1860 UC2860 UC3860
VARIABLE FREQUENCY OSCILLATOR
The VFO block is controlled through 4 pins: CvFo, IVFO, Osc Dsbl (oscillator disable), and Trig (trigger input). Oscillator frequency is approximately:
Frequency= IVFO/{CVFO * 1V)
With a fixed capacitor and low voltage applied to Trig and Osc Dsbl, frequency is linearly modulated by varying the current into the IVFO pin.
The Trig and Osc Dsbl inputs are used to modify VFO operation. If Osc Dsbl is held high, the oscillator will complete the current cycle but wait until Osc Dsbl is returned low to initiate a new cycle. If a pulse is applied to Trig during a cycle, the oscillator will immediately initiate a new cycle. Osc Dsbl has priority over Trig, but if a trigger pulse is received while Osc Dsbl is high, the VFO will remember the trigger pulse and start a new cycle as soon as Osc Dsbl goes low.
Normally low trigger pulses are used to synchronize the oscillator to a faster clock. Normally high trigger pulses can also be used to synchronize to a slower clock.
ONE SHOT TIMER
The one shot timer performs three functions and is programmed by the RC pin. The first function is to control output driver pulse width. Secondly, it clocks the toggle flip-flop. Thirdly, it establishes the maximum allowable frequency for the VFO. One shot operation is initiated at the beginning of each oscillator cycle. The RC pin, programmed by an external resistor and capacitor to ground, is charged to approximately 4.3V and then allowed to discharge. The lower threshold is approximately 80% of the peak. On time is approximately:
t(on) = 0.2 * R * C.
After crossing the lower threshold, the resistor continues to discharge the capacitor to approximately 3V, where it waits for the next oscillator cycle.
OSC DSBL
Maximum Frequency vs R
~ 10M
iE C=100pF ~~ 1M ~ kc.1nF §
~
u..
100k
~~
c-1onF ~
.EE 10k
)(
CvFO·C
~ 1k
3 5 10 203050 100
R (kn)
On Time vs R
300µ 100µ
:§: 30µ
.! 10µ
I- 3µ
8 1µ
300n
100n 3 5
10 203050 100 R (kn)
VFO Frequency vs IVFO
5000
3000
'N 2000
:i:: 1000
~ 500
~
300 200
t 100 50 30
I.I. 20
10
Wl U4lU
ll1Jl CVFo=330p.
C·330pFjii R-2.7k
~I
.t:J I
J_ 3 10 30 100 300 1000
IVFO (µA)
5-241
FLT (+) FLT (-)
UC1860 UC2860 UC3860
TO ERROR AMP HIGH CLAMP
TO
..------1----t--- ONE SHOT
CLR
3V
FAULT MANAGEMENT SECTION
During UVLO, the fault management section is initialized. The latch is reset, and both Sft Strt (soft start) and Ast Dly (restart delay) are pulled low. When Sft Strt is low, it lowers the upper clamp of the error amplifier. As Sft Strt increases in voltage, the upper clamp increases from a value equal to the lower clamp until it is 2V more positive. A capacitor to ground from the Sft Strt pin will control the start rate.
UNCOMMITIED COMPARATOR
The uncommitted comparator, biased from the reference voltage, operates independently from the rest of the chip. The open collector output is capable of sinking 2mA. The inputs are valid in the common mode range of -0.3 to
3.0V. As long as one of the inputs is within this range, the other can be as high as 5V.
The high speed fault comparator will work over the input common mode range of -0.3 to 3.0V. When a fault is sensed, the one shot is immediately terminated, Sft Strt is pulled low, and Ast Dly is allowed to go high. Three modes of fault disposition can easily be implemented. If Ast Dly is externally held low, then a detected fault will shut the chip down permanently. If the Ast Dly pin is left open, a fault will simply cause an interruption of operation. If a capacitor is connected from Ast Dly to ground, then hie-up operation is implemented. The hie-up time is:
t (off) =600 kohm * C(Rst Dly).
Input Bias Current Input Voltage
:~ ~~:~----<~----DOUT
5-242
Input Voltage (mV)
UC1860 UC2860 UC3860
1.SK
1K
NOTE: PIN NUMBERS REFER TO THE DIP
OPEN LOOP LABORATORY TEST FIXTURE The open loop laboratory test fixture is designed.to allow familiarization with the operating characteristics of the UC3860. Note the pin numbers apply to the DIP.
To get started, preset all the options as follows:
Adjust the error amplifier variable resistor pot (R1) so the wiper is at a high potential. Open the IVFO resistor switch (S1). Throw the Trig switch (S2) to ground. Throw the Osc Dsbl switch ($3) to ground. Throw the uncommitted comparator switch (S4) to ground. Throw the UVLO switch (S5) to the resistive divider. Throw the Out Mode switch (S6) to ground. Open the restart delay switch (S7). Throw the fault switch (SB)to ground.
In this configuration, the chip will operate for Vee greater than 12V. Adjustment of the following controls allows examination of specific features.
R1 adjusts the output of the error amp. Notice the voltage at pin 5 is limited from Oto 2V above the voltage at pin 7.
S1 changes the error amp output to VFO gain. With S1 open, the maximum frequency is determined by the error amp output. With S1 closed, the one shot will set the maximum frequency.
S2 demonstrates the trigger. An external trigger signal
may be applied. When the switch is set to the resistive divider, the chip will operate in consecutive mode (ie: A,B, off, ... ) S3 allows input of an external logic signal to disable the oscillator.
S4 demonstrates the uncommitted comparator. When set to output A, the comparator will accelerate the discharge of pin 9, shortening the output pulse.
S5 shorted to ground will disable the chip and the outputs will be low. If the switch is open, the Vee start and stop thresholds are 17 and 1OV. Switched to the resistive divider, the thresholds are approximately 12 and 1OV.
S6 sets the mode of the toggle flip-flop. When grounded, the outputs operate alternately. Switched to 5V, the outputs switch in unison. (Note: If S6 and S2 are set for unison operation and triggered consecutive outputs, the chip will free run at the maximum frequency determined by the one shot.)
S7 open allows the chip to restart immediately after a fault sense has been removed. When grounded, it causes the chip to latch off indefinitely. This state can be reset by UVLO, Vee, or opening the switch. Connected to lµF programs a hie-up delay time of 600 ms.
SB allows the simulation of a fault state. When flipped to the RC network, the comparator monitors scaled average voltage of output B. Adjusting frequency will cause the comparator to sense a 'fault' and the chip will enter fault sequence.
5-243
UC1860 UC2860 UC3860
OUTPUT STAGE
BYPASS NOTE
The two totem pole output stages can be programmed by Mode to operate alternately or in unison. When Mode is low the outputs alternate. During UVLO, the outputs are low.
Extreme care needs to be exercised in the application of these outputs. Each output can source and sink transient
currents of 2A or more and is designed for high values of
dl/dt. This dictates the use of a ground plane, shielded interconnect cables, Schottky diode clamps from the output pins to Pwr Gnd (power ground), and some series resistance to provide damping. Pwr Gnd should not exceed ±0.2V from signal ground.
The reference should be bypassed with a 0.1 µF ceramic capacitor from the VREF pin directly to the ground plane near the Signal Ground pin. The timing capacitors on CvFo and RC should be treated likewise. Vee, however, should be bypassed with a ceramic capacitor from the Vee pin to the section of ground plane that is connected to Power Ground. Any required bulk reservoir capacitor should parallel this one. The two ground plane sections can then be joined at a single point to optimize noise rejection and minimize DC drops.
-I- CLOAD
Output Saturation Voltage vs Load Current 5
4
~ 3
I<-
I/)
2
>
-55'C
25'C ti
Vee-OPEN]
0 0 .20 .40 .60 .80 1.0
!LOAD (A)
Output Rise & Fall Time vs Load Capacitance
~ 500
CJ? 400 E 300 i= 200
~ 100
]]][
l
I[
F1[~ 1 ~l~EL~
od
Q) 50.0 Ul 40.0 ff 30.0 :; 20.0
8a. 10.0 0.1 0.3
i:.<r«r9
J..-1.1 ]RISE TIME
t/1 Jill[ T TI I
3 10 30 100
CLOAD (nF)
Output Saturation Voltage vs Load Current
3
2
~
-MJ_T{ bl 1~ 1 H~ ~ J1' i..-.
~ ~,.....,
l ~''-~ -25'C~
SOUR'cE
l
i.-1 0
I
l
l
J
0 0.5 1.0 1.5 2.0
!LOAD (A)
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD.· MERRIMACK, NH 03054 TEL. 603-424-2410 · FAX 603-424-3460
5-244
n nINTEGRATEO
~CIRCUITS
-UNITRODE
(9)
Resonant-Mode Power Supply Controllers ~ 'O"
UC1861-1868 UC2861-2868 UC3861-3868
FEATURES Controls Zero Current Switched (ZCS) or Zero Voltage Switched (ZVS) Quasi-Resonant Converters
Zero-Crossing Terminated One-Shot Timer
Precision 1%, Soft-Started 5V Reference
Programmable Restart Delay Following Fault
Voltage-Controlled Oscillator (VCO) with Programmable Minimum and Maximum Frequencies from 1O kHz to 1 MHz
Low Start-Up Current ( 150 µA typ.)
Dual 1 Amp Peak FET Drivers
UVLO Option for Off-Line or DC/DC Applications
Device UVLO Outputs 'Fixed'
1861 1862 1863 1864 1865 1866 1867 1868
16.5/10.5 16.5/10.5 8/7 8/7 16.5/10.5 16.5/10.5 8/7 8/7
Alternating Parallel Alternating Parallel Alternating Parallel Alternating Parallel
Off Time Off Time Off Time Off Time On Time On Time On Time On Time
DESCRIPTION The UC1861-1868 family of !Cs is optimized for the control of Zero Current Switched and Zero Voltage Switched quasi-resonant converters. Differences between members of this device family result from the various combinations of UVLO thresholds and output options. Additionally, the one-shot pulse steering logic is configured to program either on-time for ZCS systems (UC1865-1868}, or offtime for ZVS applications (UC1861-1864}.
The primary control blocks implemented include an error amplifier to compensate the overall system loop and to drive a voltage controlled oscillator (VCO), featuring programmable minimum and maximum frequencies. Triggered by the VCO, the one-shot generates pulses of a programmed maximum width, which can be modulated by the Zero Detection comparator. This circuit facilitates "true" zero current or voltage switching over various line, load, and temperature changes, and is also able to accommodate the resonant components' initial tolerances.
Under-Voltage Lockout is incorporated to facilitate safe starts upon power-up. The supply current during the under-voltage lockout period is typically less than 150 µA, and the outputs are actively forced to the low state. UVLO thresholds for the UC1861 /62/65/66 are 16.5V (ON) and 10.5V (OFF), whereas the UC1863/64/67/68 thresholds are 8V (ON) and 7V (OFF}. After Vee exceeds the UVLO threshold, a 5V generator is enabled which provides bias for the internal circuits and up to 1OmA for external usage. (continued}
~
BLOCK DIAGRAM
Fault
Fault and Logic
1 - - - - - - l Precision Reference
Blas and 5V Gen 1----+----1
Gnd
E/A Out
UVLO
vco
One Shot
Steering Logic
FET Drivers
5/93
Pin numbers refer to the J and N packages. 5-245
UOG-92018
UC1861-1868 UC2861-2868
DESCRIPTION (cont.)
··
. . . UC38&1-3868
A Fault comparator serves to detect fault conditions and set a latch while forcing the output drivers1ow. The Soft-Ref pin
serves three functions: previding soft start, restart delay, and the internal system reference.
Each device features dual 1 Amp peak totem pole output drivers for direct interrace to power MOSFETS. The outputs are programmed to alternate in the UC1861/63/65/67 devices. The UC1862/64/66/68 outputs operate in unison alllowing a 2 Amp peak current.
ABSOLUTE MAXIMUM RATINGS
Vee .............................................. 2~ Output Current, Source or Sink (Pins 11 & 14) DC ....... 0.5A
Pulse (0.5µs) ....................... 1.5A Power Ground Volage ............................ ±0.~ Inputs (Pins 2, 3, 10, & 15) . . . . . . . . . . . . . . . . . . . . -0.4 to 7V Error Amp Output Current. ........................ ±2mA Power Dissipation .....·........................... 1W Junction Temperature (Operating) ................. 150°C
Lead Temperature (Soldering, 1Oseconds) . . . . . . . . . . 300°C
Note 1: All voltages are with respect to signal ground and all currents are positive into the specified terminal. Pin numbers refer to the J and N package6. Note 2: Consult Unitrode Integrated Circuits databook for Information regarding thermal specifications and /Imitations ofpackages.
CONNNECTION DIAGRAMS
DIL-16, SOIC-16 (Top View) J or N, OW Packages
PLCC-20 & LCC-20 (Top View) Q&LPackage
3 2 1 20 19
4
18
5
17
8
18
7
15
8
14
9 10 11 12 13
PACKAGE PIN FUNCTION PIN
2
3
4
5
6
7
8
9
10
Zero
11
NC
12
NC
13
A Out
14
PwrGnd
15
PwrGnd
16
Vee
17
B Out
18
NC
19
Fault
20
ELECTRICAL CHARACTERISTICS Unless otherwise stated, all specifications apply for -55°C:s:TAS125°C for the uc186x,
-25°C.;TA:s85°Cfor the UC286x, and 0°C:s:TAS70°Cforthe UC386x, Vcc=1~,
CVco=1nF, Range=7.15k, RMIN=86.6k, C=200pF, R=4.02k, and Csr=0.1µF. TA:TJ.
PARAMETER
TEST CONDITIONS
MIN TVP MAX UNITS
5V Generator O~tVolta~
12V :sVcc :s 20V, -10mA :s lo :s OmA
4.8 5.0 5.2
v
Short Circuit Current
Vo=OV
-150
-15 mA
Soft-Reference
Restart Delay Current
V=2V
10
20
35
µA
Soft Start Current Reference Voltage
V=2V TJ = 25°C, lo = OA 12V :s: Vee" 20V, -200µA" lo" 200µA
-650 -500 -350 µA
4.95 5.00 5.05
v
4.85
5.15 v
Line Regulation
12Vo;Vcco; 20V
2
20
mV
Load ~ulation Error Am_.e!lfler (Note~
-200µA " lo " 200µA
10
30
mV
Input Offset Voltage
VcM = 5V, Vo = 2V, lo = OA
-10
10 mV
I~ Bias Current
VCM=OV
-2.0 -0.3
µA
Voltage Gain
Vern= 5V, 0.5V" Vo" 3.7V, lo= OA
70 100
dB
Power Supply Rejection Ratio
Vcm=5V,Vo=2V,12V,,; Vcc,,;20V
70 100
dB
5-246
UC1861-1868
UC2861-2868 UC3861-3868 ELECTRICAL CHARACTERISTICS Unless otherwise stated, all specifications apply tor-55°C:5T.u:125°C for the UC186x,
-25°C:sT.u:85°C for the UC286x, and 0°C:sT.u:70°C for the UC386x, Vee=12V, Cveo=1 nF, Range=7.15k, RMIN=86.6k, C=200pF, R=4.02k, and Csr=0.1 µF. TA=TJ.
PARAMETER
TEST CONDITIONS
Error Amplifier (Note 3) (cont.)
Common Mode R~ection Ratio OV :s Vern :s 6V, Vo = 2V
VouTLow
V10 = -100mV, lo= 200µA
VOUT High
VID = 100mV, lo= -200µA
Unity Gain Bandwidth
(Note 4)
Voltage Controlled Oscillator
Maximum Frequency
V10 (Error Amp)= 100mV, TJ = 25°C
V10 (Error Amp)= 100mV
Minimum Frequency
V10 (Error Amp) = -1 OOmV, TJ = 25°C
VID (Error Am.El_= -1 OOmV
One Shot
Zero Comparator Vth
Propagation Delay
(Note 4)
Maximum Pulse Width
VZERO = 1V
Maximum to Minimum Pulse
VZERO =OV UCx861 - UCx864
Width Ratio
VZERO= OV UCx865 - UCx868
Output Stage
Rise and Fall Time
CLOAD = 1nF_(_Note'!)__
Output Low Saturation
lo =20mA
lo=200mA
Output High Saturation
lo = -200mA, down from Vee
UVLO Low Saturation
lo=20mA
Fault Comparator
Fault Comparator Vth
Delay to Output
(Note 4) (Note 5)
UVLO
Vee Turn-on Threshold
UCx861, UCx862, UCx865, UCx866 .
UCx863, UCx864, UCx867, UCx868
Vee Turn-off Threshold
UCx861, UCx862, UCx865, UCx866
UCx863, UCx864, UCx867, UCx868
Ice Start
Vee = Vee(on) - 0.3V
Ice Run
VID = 100mV
Note 1: Currents are defined as positive into the pin.
Note 2: Pulse measurement techniques are used to insure that TJ = TA.
Note 3: VJD = V(NJ) - V(JNV).
Note 4: This parameter is not 100% tested in production but guaranteed by design.
Note 5: Vi= 0 to 4V
tr(Vi) :s 10ns tpd = t(Vo = 6V) - t(Vi = 3V)
MIN TYP MAX UNITS
65 100
dB
0.17 0.25
v
3.9 4.2
v
0.5 1.0
MHz
450 500 550 kHz
425
575 kHz
45
50
55
kHz
42
58 kHz
0.45 0.50 0.55
v
120 200 ns
850 1000 1150 ns
2.5
4
5.5
4
5.5
7
25
45
ns
0.2 0.4
v
0.5 2.2
v
1.7 2.5
v
0.8
1.5
v
2.85 3.00 3.15
v
100 200 ns
15 16.5 18
v
7
8.0
9
v
9.5 10.5 11.5
v
6
7.0
8
v
150 300 µA
25
32
mA
UVLO & SV GENERATOR (See Figure 1): When power is applied to the chip and Vee is less than the upper UVLO threshold, Ice will be less than 300µA, the 5V generator will be off, and the outputs will be actively held low.
When Vee exceeds the upper UVLO threshold, the 5V generator turns on. Until the 5V pin exceeds 4.9V, the outputs will still remain low.
The 5V pin should be bypassed to signal ground with a 0.1 µF capacitor. The capacitor should have low equivalent series resistance and inductance.
FAULT AND SOFT-REFERENCE (See Figure 1): The Soft-Ref pin serves three functions: system reference, restart delay, and soft~start. Designed to source or sink 200µA, this pin should be used as the input reference for the error amplifier circuit. This pin requires a bypass capacitor of at least 0.1 µF. This yields a minimum soft-start time of 1ms.
Under-Voltage Lockout sets both the fault and restart delay latches. This holds the outputs low and discharges the Soft-Ref pin. After UVLO, the fault latch is reset by the
5-247
UC1861-1868
UC2861-2868 UC3861-3868
low voltage on the Soft·Ref pin. The reset fault latch resets · a single fault event is longer than for. recurring faults since
the delay latch and Soft-Ref charges vi~ the 0.5mA current Soft-Ref must be discharged from 5V instead of 4V.
source.
The restart delay to soft-start time ratio is 24:1 for a fault
The fault pin is input to a high speed comparator with a occurring during normal operation and 19:1 for faults oc-.
threshold of 3V. In the event of a detected fault, the fault curring during soft-start. Shorter ratios can be
latch is set and the outputs are driven low. If Soft-Ref is programmed down to a limit of approximately 3:1 by the
above 4V, the delay latch is set Restart delay is timed as addition of a 20k'2 or larger resistor from Soft-Ref to
Soft-Ref is discharged by 20JIA. When Soft-Ref is fully discrnirged, the fault latch il:l reset if the fault input signal is low. The Fault piri can be used as a system shutdown pin.
If a fault is detected during soft-start, the fault latch is set and the outputs are driven low. The delay latch will remain reset until Soft-Ref charges to 4V. This sets the delay latch, and restart delay is timed. Note that restart delay ·for
ground.
A 1OOl<C resistor from Soft-Ref to 5V will have the effect of permanent shut down after a fault since the internal 20JIA current source can't pull Soft-Ref low. This feature can be used to require recycling Vee after a fault. Care must be taken to insure Soft-Ref is indeed low at start up, or the· fault latch will never be reset.
UVLO 5V Fault and Soft-Ref
Pwr Gnd
On/00 5V Generato SV
sv
(IC Blas) ·1--.....--------------~ ~--.
Inhibit Output(s) (UVLO)
l,.
Sig- Gnd
Soft-Ref
Latch
Latch
·ucx861/62/65/66 thresholds are 16.SV and 10.sv. UCx863/64/67/88 thresholds are av and 7V.
c 16.5V (8V) ······ ··
"" cmk
5V
Solt-Ref
· · · · · : r·~5.0V 00·-;-··---.. Solt Start
:11··· ...
Fault
Output( a)
Figure 1
5-248
UDG-92020
Error Amp, Voltage Controlled Oscillator, and One Shot
Error Amp SV
UC1861-1868 UC2861-2868 UC3861-3868
SV
JL Zero
vco
UDG·92022
Minimum Pul11
Maximum Pulse
Figure2
Zero Controlled Pulae
UDG-92023
Minimum oscillator frequency is set by Amin and Cvco. The minimum frequency is approximately given by the equation:
r=
4.3
·MIN·-----
RMtN· Cvco
Maximum oscillator frequency is set by Amin, Range &
Cvco. The maximum frequency is approximately given by
the equation:
r=
3.3
·MAX· (RMtN 11 Rangey · Cvco
The Error Amplifier directly controls the oscillator fre-
quency. E/A output low corresponds to minimum frequency and output high corresponds to maximum frequency. At the end of each oscillator cycle, the RC pin is discharged to one diode drop above ground. At the beginning of the oscillator cycle, V(RC) is less than Vth1 and so the output of the zero detect comparator is ignored. After V(RC) exceeds Vth1, the one shot pulse will be terminated as soon as the zero pin falls below O.SV or V(RC) exceeds Vth2. The minimum one shot pulse width is approximately given by the equation:
Tpw(min) .. 0.3 · R · C.
The maximum pulse width is approximately given by:
Tpw(max) · 1.2 · R · C.
5-249
Steerln
ic
Ono Shot
VCC Out A
One Shot Fault Latch
UVLO
UC1861-1868 UC2861-2868 UC3861-3868
vcc
Out A
Out B
Pwr Gnd
UDG-92013
The steering logic is configured on the UC1861,63 to result in dual non-overlapping square waves at outputs A & B. This is suited to drive dual switch ~S systems.
Out B
Pwr Gnd
UDG-920t4
The steering.logic is configured on the UC1862,64 to result in inverted pulse trains occurring identically at both output pins. This is suited to drive single switch ~S systems. Both outputs ~re available to drive the same MOSFET gate. It is advisable to join the pins with 0.5 ohm resistors.
vcc
Out A
Out B Pwr Gnd
UDG-92015
The steering logic is configured on the UC1865,67 to result in alternating pulse trains at outputs A & B. This is suited to drive dual switch ZCS systems.
One S'1ot Fault Latch
UVLO
VCC Out A
Output 0.50
Out B
Pwr Gnd
UDG-92018
The steering logic is configured on the UC1866,68 to result in non-inverted pulse trains occurring identically at both output pins. This is suited to drive single switch ZCS systems. Both outputs are available to drive the same MOSFET gate. It is advisable to join the pins with 0.5 ohm resistors.
Internal Ona Shot
__J Out A
UCx861,63
Out Bl._______.
,________L__,,
UCx862,64
_____ Out A _Jl~------~rl._
UCx865,67
outs _ _ _ _~rl~------~n_
UCx866,68
UNrrRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. · MERRIMACK, NH 03054 TEL (803) "24-2410 · FAX (803) "24-3480
5-250
UDG·920t7
n n INTEGRATED
~CIRCUITS
-UNITRODE
Resonant Fluorescent Lamp Driver
UC1871 UC2871 UC3871
FEATURES 1µA ICC when Disabled
PWM Control for LCD Supply
Zero Voltage Switched (ZVS) on Push-Pull Drivers
Open Lamp Detect Circuitry
4.5V to 20V Operation
Non-saturating Transformer Topology
Smooth 100% Duty Cycle on Buck PWM and 0% to 95% on FlybackPWM
DESCRIPTION The UC1871 Family of IC's is optimized for highly efficient fluorescent lamp control. An additional PWM controller is integrated on the IC for applications requiring an additional supply, as in LCD displays. When disabled the IC draws only 1µA, providing a true disconnect feature, which is optimum for battery powered systems. The switching frequency of all outputs are synchronized to the resonant frequency of the external passive network, which provides Zero Voltage Switching on the Push-Pull drivers.
Soft-Start and open lamp detect circuitry have been incorporated to minimize component stress. An open lamp is detected on the completion of a soft-start cycle.
The Buck controller is optimized for smooth duty cycle control to 100%, while the flyback control ensures a maximum duty cycle of 95%.
Other features include a precision 1% reference, under voltage lockout, flyback current limit, and accurate minimum and maximum frequency control.
BLOCK DIAGRAM
vee
REF Out Enable E/A 1
Comp Lamp
I SENSE
SS
Ramp
Zero Detect
Ve
A Out B Out C Out
E/A 2(+)
E/A 2(-) E/A 2
Comp
Flyback I SENSE
5/93
5-251
D Out Gnd
UOG-92061
ABSOLUTE MAXIMUM RATINGS
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1OV Zero Detect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +20V Power Dissipation at TA = 25°C ................... 1W Storage Temperature ................ -65°C to+150°C Lead Temperature .......................... 300°C Note 1: Currents are positive into, negative out of the specified terminal. Note 2: Consult Packaging Section of Databook for thermal limitations and considerations ofpackage.
DIL-18, SOIC-18 (TOPVIEW) J or N, DW Package
Flyback
I SENSE
UC1871 UC2871 UC3871
CONNECTION DIAGRAMS
PLCC-20 (Top View) Q Package
~
L 3 2 1 20 19
4
18
15
17
6
16
7
15
8
14
9 10 11 12 13
~~~
PACKAGE PIN FUNCTION
FUNCTION
PIN
Gnd
1
B Out
2
A Out
3
Ve
4
EA1 Out
5
Soft Start
6
EA1_{:l
7
~c
8
CT
9
Zero Detect
10
NI.c
11
VREF
12
EA21tl_
13
EA2J:)_
14
EA2 Out
15
VIN
16
Enable
17
FJY.back !SENSE
18
D Out
19
C Out
20
ELECTRICAL CHARACTERISTICS Unless otherwise stated, these parameters apply for TJ = -55°C to+125°C for the
UC1871; -25°Cto +85°C for the UC2871; 0°C to +70°C for the UC3871; Vee= 5V, Ve= 15V, VENABLE= 5V, CT= 1nF, Zero Det = 1V.
PARAMETER Reference Section
Output Voltage
Line Regulation Load Regulation Oscillator Section Free Running Freq Max ~nc Fr~uen~ Charge Current Voltage Stability Temperature Stability Zero Detect Threshold Error Amp 1 Section Input Volt1ill9 Input Bias Current O~nLo<>I>_Gain Output High Output Low Output Source Current Output Sink Current Common Mode Range Unity Gain Bandwidth
TEST CONDITIONS
TJ=25°C Overtemp Vee= 4.75V to 18V lo=Oto-5mA
TJ=25°C TJ=25°C Ver= 1.5V
Vo=2V
Vo= 0.5to3V VEA(-) = 1.3V VEA(-) = 1.7V VEA(-) = 1.3V, Vo= 2V VEA(-) = 1.7V, Vo= 2V
TJ = 25°C (Note 4)
MIN TYP MAX UNITS
v 2.963 3.000 3.037 v 2.940 3.000 3.060
10 mV 10 mV
57
68
78 kHz
160 200 240 kHz
180 200 220 µA
2
%
4
8
%
v 0.46 0.5 0.56
1.445
65 3.1
-350 10 0
1.475 1.505 -0.4 -2 90 3.5 3.9 0.1 0.2 -500 20
VIN-1V 1
v
µA
dB
v v
µA
mA
v
MHz
5-252
ELECTRICAL CHARACTERISTICS (cont.)
UC1871 UC2871
UC3871
Unless otherwise stated, these parameters apply for TJ = -55°C to+ 125°C for the UC1871;
-25°C to +85°C for the UC2871; o·c to +10°c for the UC3871; Vee= 5V, Ve= 15V,
VENABLE= 5V, CT= 1nF, Zero Det = 1V.
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNITS
Open Lamp Detect Section Soft Start Threshold Error Amp Threshold Soft Start Current
Error Amp 2 Section
VEA(-)= OV Vss=4.2V Vss=2V
2.9 3.4 3.8
v
0.3 0.5 0.7
v
10 20 40 !IA
Input Offset Voltage Input Bias Current IllJ'.>l!t Offset Current Open LOC£ Gain Output H.!ll_h Output Low Output Source Current Output Sink Current Common Mode Range Unity Gain Bandwidth lsenae Section Threshold
Vo=2V
Vo= 0.5to3V V10=100mV, Vo= 2V V10 = -100mv, Vo= 2V V10 = 1OOmV, Vo = 2V V10 = -100mV, Vo= 2V
TJ = 25°C (Note 4)
0
10 mV
-0.2 -1
!IA
0.5 llA
65
90
dB
3.6
4
4.4
v
0.1
0.2
v
-350 -500
!IA
10
20
mA
0
v VIN-2V
1
MHz
v 0.475 0.525 0.575
Output Section Output Low Level
Output High Level
RiseTime Fall Time
IOUT = 0, Outputs A and B IOUT= 10mA IOUT= 100mA
c IOUT = 0, Outputs and D
IOUT = -10mA IOUT = -1 OOmA TJ = 25°C, Cl= 1nF(Note 4) TJ = 25°C, Cl= 1nF(Note 4)
0.05 0.2
v
0.1
0.4
v
1.5 2.2
v
14.7 14.9
v
13.5 14.3
v
12.5 13.5
v
30
80
ns
30 80 ns
Output Dynamics Out A and B Duty Cycle Out C Max Duty Cycle
VEA1(-) = 1V
48 49.9 50
%
100
%
Out C Min Duty Cycle Out D Max Duty Cycle OutDMin~le
VEA1_{-}_ = 2V VEA2(+)- VEA2(-) = 100mV VEA2(+)-VEA2(-) = -100mV
0
%
92
96
%
0
%
Under Voltage Lockout Section Start-Up Threshold
3.7 4.2 4.5
v
Hysterisis
120 200 280 mV
Enable Section
Input High Threshold
l~ut low Threshold
Input Current
VENABLE=5V
Supply Current Section
VCC SupplyCurrent
Vee=20V
VC S~ Current ICC Disabled
Ve=20V
ov Vee = 20V, VENABLE =
Note 3: Unless otherwise specified, all voltages are with respect to ground. Currents are positive into, and negative out of the specified terminal.
Note 4: Guaranteed by design but not 100% tested in production.
2
v
0.8 v
150 400 !IA
8
14 mA
7
12 mA
1 10 !IA
5-253
TYPICAL APPLICATION
UC1871 UC2871 UC3871
+4.SV to +2f1V
..L
--+-+----!__;]. VCC
+4.SV to +2f1V
R1 C2 ..c--0 VREF
":" 0 SOK 1uF.::C. · ENABLE
vc
OutA
VREF R2
..i:----CJ SS
C2.:;:. 1uF :
.r--0 Ct
C3 ~ 0.001uF:
OutB UC3871
R4 40K
LAMP Brightness Control
1:150
T1 (lprimory=1 OUH)
·12V to ·24V
Contrast Adjuot
rLCD SUPPLY
Figure 1
APPLICATION INFORMATION Figure 1 shows a complete application circuit using the UC3871 Resonant Fluorescent lamp and LCD driver. The IC provides all drive, control and housekeeping functions to implement CCFL and LCD converters. The buck output voltage (transformer center-tap) provides the zero crossing and synchronization signal. The LCD supply modulator is also synchronized to the resonant tank.
The buck modulator drives a P-channel MOSFET directly, and operates over a 0-100% duty-cycle range. The modulation range includes 100%, allowing operation with minimal headroom. The LCD supply modulator also directly drives a P-channel MOSFET, but it's duty-cycle is limited to 95% to prevent flyback supply foldback.
The oscillator and synchronization circuitry are shown in Figure 2. The oscillator is designed to synchronize over a 3:1 frequency range. In an actual application however, the frequency range is only about 1.5:1. A zero detect
comparator senses the primary center-tap voltage, generating a synchronization pulse when the resonant waveform falls to zero. The actual threshold is 0.5 volts, providing a small amount of anticipation to offset propagation delay.
The synchronization pulse width is the time that the 4mA current sink takes to discharge the timing capacitor to 0.1 volts. This pulse width sets the LCD supply modulator minimum off time, and also limits the minimum linear control range of the buck modulator. The 200µA current source charges the capacitor to a maximum of 3 volts. A comparator blanks the zero detect signal until the capacitor voltage exceeds 1 volt, preventing multiple synchronization pulse generation and setting the maximum frequency. If the capacitor voltage reaches 3 volts (a zero detection has not occurred) an internal clock pulse is generated to limitthe minimum frequency.
5-254
APPLICATION INFORMATION cont.
UC3871 OSCILLATOR SECTION
UC1871 UC2871 UC3871
RAMP
CLK
ZERO DETECT
Figure2
A unique protection feature incorporated in the UC3871 is the Open Lamp Detect circuit. An open lamp interrupts the current feedback loop and causes very high secondary voltage. Operation in this mode will usually breakdown the transformer's insulation, causing permanent damage to the converter. The open lamp detect circuit, shown in Figure 3 senses the lamp current feedback signal at the error amplifiers input, and shuts down the outputs if insufficient signal is present. Soft-start circuitry limits initial turn-on currents and blanks the open lamp detect signal.
Other features are included to minimize external circuitry
requirements. A logic level enable pin shuts down the IC, allowing direct connection to the battery. During shutdown, the IC typically draws less than 1µA. The UC3871, operating from 4.5V to 20V, is compatible with almost all battery voltages used in portable computers. Under-voltage lockout circuitry disables operation until sufficient supply voltage is available, and a 1% voltage reference insures accurate operation. Both inputs to the LCD supply error amplifier are uncommitted, allowing positive or negative supply loop closure without additional circuitry. The LCD supply modulator also incorporates cycle-bycycle current limiting for added protection.
UC1871 Open Lamp Detect Circuitry
LAMP I SENSE
SS
UNITROOE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. · MERRIMACK, NH 03054 TEL. (803) "24-2410 · FAX (803) "24-3<!80
Low= Open Lamp ( Disable Outputs)
Open Lamp Datect
Figure3
5-255
n n Ll:::::::J
INTEGRATED CIRCUITS
-UNITRODE
Phase Shift Resonant Controller
UC1875/6/7/8 UC2875/6/7/8 UC3875/6/7/8
FEATURES
· Zero to 100% Duty Cycle Control ·Programmable Output Turn-On
Delay · Compatible with Voltage or Current
Mode Topologies ·Practical Operation @ Switching
Frequencies to 1MHz · Four 2A Totem Pole Outputs · 1OMHz Error Amplifier · Under Voltage Lockout · Low Start-Up Current -1 SOµA ·Outputs Active Low During UVLO ·Solt-Start Control · Latched Over-Current Comparator
With Full Cycle Restart ·Trimmed Reference
Device UVLO Tum-On
UC1875 10.75 UC1876 15.25V UC1877 10.75V UC1878 15.25V
UVLO Tum-Off 9.25V 9.25V 9.25V 9.25V
Delay Set Yes Yes No No
DESCRIPTION
The UC1875 family of inlegrated circuits implements control of a bridge power stage by phase-shifting the switching of one hall-bridge with respect to the other, allowing constant frequency pulse-width modulation in combination with resonant zero-voltage switching for high efficiency performance at high frequencies. This family of circuits may be configured to provide control in either voltage or current mode operation, with a separale over-current shutdown for fast fault protection.
A programmable time delay is provided to insert a dead-time at the IUm-on of each output stage. This delay, providing time to allow the resonant switching action, is independently controllable for each output pair (A-B, C-0).
With the oscillator capable of operation at frequencies in excess of 2MHz, overall switching frequencies to 1MHz are practical . In addition to the standard free running mode, with the CLOCK/SYNC pin, the user may configure these devices to accept an eXlemal clock synchronization signal, or may lock together up to 5 units with the operational frequency delermined by the faslest device.
Protective fealUres include an under-voltage lock-out which maintains all outputs in an active-low state until the supply reaches a 10.75V threshold. 1.5V hysleresis is built in for reliable, boot-strapped chip supply. Over-current prolection is provided , and will latch the outputs in the OFF stale within 70nsec of a fault. The current-fault circuitry implements luU-cycle restart operation.
Additional fealUres include an error amplifier with bandwidth in excess of 7MHz, a 5V reference, provisions for soft-starting, and flexible ramp generation and slope compensation circuitry.
These devices are available in 20-pin DIP, 28-pin 'bat-wing" SOIC and 28 lead power PLCC plastic packages for operation over both O"C to 70°C and -25"C to +85°C temperalUre ranges; and in hermetically sealed cerdip, and surface mount packages for -55"C to +125°C operation.
BLOCK DIAGRAM
FREQ. SET
CLOCK SYNC SLOPE
Hi h Speed Osciiator
SOFTSTART
5/93
DELAY ' - - - - - - - - - - 1 - - - - - 1 7 SET
C-D
6 - - - - - - - - - - - - l 1 v,.,
~GND
5-256
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (Ve. V1Nl ..............................................................20V Output Current, Source or Sink
DC ......................................................................................0.5A Pulse (0.5µs) .........................................................................3A Analog I/Os (Pins 1, 2, 3, 4, 5, 6, 7, 15, 16, 17, 18, 19) ..... -0.3 to 5.3V Operating Junction Tempera1Ure ............................................... 150°C Storage Tempera1Ure Range ....................................-65°C to+ 150°C Lead Temperature (Soldering, 10 seconds) .......................... 300°C
PACKAGE PIN FUNCTIONS
Function
PACKAGE TYPE and PIN NUMBER 20-pln N, J 28-pln QP 28-pln DWP
VREF
1
1g
1
E/A OUT (COMP)
2
20
2
E/A (-)
3
21
3
E/A (+)
4
22
4
C/S (+)
5
23
5
SOFT-START
6
24
6
DELAY SET CID
7
25
10
OUTD
8
26
12
OUTC
9
27
13
Ve
10
28
14
VIN
11
1
15
PWRGND
12
2
16
OUTB
13
3
17
OUTA
14
4
18
DELAY SET A/B
15
7
23
FREQ SET
16
8
24
CLOCK/SYNC
17
9
25
SLOPE
18
10
26
RAMP
19
11
27
GND
20
12-18 7-9, 11,19-22, 28
UC1875/617/8 UC2875/6/7/8 UC3875/6/7/8
Note: · Pin references are to 20 pin packages. ·All voltages are with respect to ground, OIL pin 20. · Currents are positive into, negative out of, device terminals. · Consult Unitrode Integrated Circuits databook for information regarding thermal specifications and limitations of packages.
CONNECTION DIAGRAMS
DIL-20 (TOP VIEW)
J or N PACKAGE
SOIC-28 (TOP VIEW) DWP PACKAGE
PLCC-28 (TOP VIEW) QPPACKAGE
L4 3 2 12e2126
5
25
6
24
7
23
8
22
9
21
~o
20
11 1213141516171d9
Electrical Characteristics: Unless otherwise stated, Ve= V1N = 12v, RFREOSET = 12kn, CFREasET = 330pF, RsLoPE = 12kn, CRAMP=
c 200pF, DELAYSETA-B = CDELAY SETe-o = 0.01µF, IDELAY SETA-B = IDELAY SETe-o = -500µA, -55°C<TA<125°C for the UC1875/617/8 -25°C<TA<85°C for
the UC2875/6/7/8 and 0°C<TA<70°C for the UC3875/617/8 TA=TJ.
PARAMETER Under-Voltage Lockout
Start Threshold
UVLO Hysteresis
Supply Currant l1N Startup le Startup llN le
TEST CONDITION
UC1875NC1877 UC1876NC1878 UC1875NC1877 UC1876/UC1878
VIN= sv. Ve= 20V, RSLDPE open, IDELAY =0 VIN= sv. Ve= 20V, RSLOPE open, IDELAY =0
MIN
TYP
10.75 15.25 1.25 6.0
150 10 30 15
MAX
600 100 40 30
UNITS
v v v v
µA µA mA mA
5-257
UC1875/617/8
UC2875/6/7/8
UC3875/6/7/8 Electrical Characteristics: Unless otherwise stated, Ve= VIN = 12V, RFREQ SET= 12k.Q, CFREQ SET= 330pF, RsLOPE = 12kn, CRAMP=
200pF, CDELAY SET A-B = CDELAY SET C-D = 0.01µF, IDELAY SET A-B =(DELAY SETC-D = -500µA, -55°C<TA<125°C for the UC1875/6/7/8, -25°C<TA<85°C for the UC2875/6/7/8, and 0°C<TA<70°C for the UC3875/6/7/8, TA=TJ.
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNITS
Voltage Reference Output Voltage Line Regulation Load Regulation Total Variation Noise Voltage Long Term Stability Short Circuit Current Error Amplifier Offset Voltage Input Bias Current AVOL CMRR PSRR Output Sink Current Output Source Current Output Voltage High Output Voltage Low Unity Gain BW Slew Rate PWM Comparator Ramp Offset Voltage Zero Phase Shift Voltage PWM Phase Shift (Note 1) Output Skew (Note 1) Ramp to Output Delay Oscillator Initial Accuracy Voltage Stability Total Variation Sync Pin Threshold Clock Out Peak Clock Out Low Clock Out Pulse Width Maxim um Frequency Ramp Generator/Slope Compensation Ramp Current, Minimum Ramp Current, Maximum Ramp Valley Ramp Peak - Clamping Level Current Limit Input Bias
TJ = + 25°C 11<VIN<20V IVREF = -10mA Line, Load, Temperature iOHz to 10kHz TJ = 125°C, 1000 hours VREF = OV, TJ = 25°C
1<VcoMP<4V 1.5 < VCM < 5.5V 11<VIN<20V VcOMP=1V VCOMP=4V (COMP = -0.5mA (COMP= 1mA
TJ = 25°C, Note 3 Note4 VCOMP > (Ramp Peak+ Ramp Offset) VCOMP < Zero Phase Shift Voltage VCOMP > Ramp Peak VCOMP<1V
TJ = 25' 11<VIN<20V Line, Temperature TJ = 25'C TJ = 25'C TJ = 25°C RCLOCK/SYNC = 3.9k.Q RFREQSET = 5k.Q
!SLOPE = 1OµA, VFREQ SET = VREF (SLOPE = 1mA, VFREQ SET = VREF
RFREO SET = 1OOk.Q
VC/S+ = 3V
4.95
5
5.05
v
1
10
mV
5
20
mV
4.9
5.1
v
50
µVrms
2.5
mV
60
mA
5
15
mV
0.6
3
µA
60
90
dB
75
95
dB
85
100
dB
1
2.5
mA
-1.3
-0.5
mA
4
4.7
5
v
0
0.5
1
v
7
11
MHz
6
11
V/µsec
1.3
v
0.55
0.9
v
98
99.5
102
%
0
0.5
2
%
5
±20
nsec
5
±20
nsec
50
100
nsec
0.85
1
1.15
MHz
0.2
2
%
0.80
1.20
MHz
3.8
v
4.3
v
3.3
v
30
100
nsec
2
MHz
-11
-14
µA
-0.8
-0.95
mA
0
v
3.8
4.1
v
2
5
µA
5-258
UC1875/617/8 UC2875/6/7/8 UC3875/6/7/8
Electrical Characteristics: Unless otherwise stated, Ve= VIN = 12V, RFREO SET= 12k!l, CFREQ SET= 330pF, RSLOPE = 12k!l, CRAMP=
200pF, CDELAY SET A·B = CDELAY SET C-D- 0.01µF, IDELAY SET A·B =!DELAY SETe-o = -500µA, -55°C<TA<125°C for the UC1875/617/8, -25°C<TA<B5°C for the UC2875/617/8, and 0°C<TA<70°C for the UC3875/617/8, TA=TJ.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Current Limit (continued) Threshold Voltage Delay to Output Soft-Start/Reset Delay Charge Current Discharge Current Restart Threshold Discharge Level Output Drivers
Output Low Level lour= 500mA
Output High Level lour = -500mA Delay Set (UC1875 and UC1876 only) Delay Set Voltage Delaynme
VsoFT-START = 0.5V VSOFT START= 1V
lour= 50mA lour =-50mA
IDELAY = -500µA IDELAY = -250µA (NOTE 5)
2.4
2.5
2.6
v
70
125
nsec
-20
-9
-3
µA
140
230
µA
4.3
4.7
v
300
mV
0.2
0.4
v
1.2
2.6
v
1.5
2.5
v
1.7
2.6
v
2.3
2.4
2.6
v
150
250
400
nsec
Note 1: Phase shift percentage (0% = 0°, 100% = 180°) is defined as
9= 2~0 <!>%,
e where is the phase shift, and<!> and Tare defined in Figure1.
At 0% phase shift, <!>is the output skew.
OutA 50% Out B
Out C 50% OutO
Note 2: Delay time is defined as delay= T (+-(duty cycle)), where T is defined in figure 1.
Note 3: Note 4:
Note 5:
Ramp offset voltage has a temperature coeffecient of about -4mV/°C. Zero phase shift voltage has a temperature coeffecient of about -2mV/°C.
Delay time can be programmed via resistors from the delay set pins to
= ground. Delay time 62.5x10·12 sec.
- IDELAY
Duty Cycle=+ Period = T ToHL<A to C) = ToHL (B to D) =<I>
Phase Shift, Output Skew & Delay Time Definitions
FIGURE1
Where IDELAY Delay set voltage The recommended range for IDELAY
=
RDELAY
is 25µA '.>IDELAY ,; t mA
PIN FUNCTIONAL DESCRIPTION
GND (signal ground): All volJages are measured with respect to GND. The timing capacitor, on the FREQ SET pin, any bypass capacitor on the VREF pin, bypass capacitors on VIN and the ramp capacitor, on the RAMP pin, should be connected directly to the ground plane near the signal ground pin.
Ve (output switch supply voltage): This pin supplies power to the output drivers and their associated bias circuitJy. Connect Ve to a stable source above 3V for normal operation, above 12V for best performance. This supply should be bypassed directly to the PWR GND pin with low ESR, low ESL capacitors.
PWR GND (power ground):
cV should be bypassed with a ceramic capacitor from the Ve pin to the section
of the ground plane that is connected to PWR GND. Any required bulk reser-
voir capacitor should parallel this one. Power ground and signal ground may be
joined at a single point to optimize noise rejection and minimize DC drops.
VIN (primary chip supply voltage): This pin supplies power to the logic and analog circuitry on the integrated circuit that is not directly associated with driving the output stages. Connect VIN
5.25g
PIN FUNCTIONAL DESCRIPTION (CONTINUED
to a stable source above 12V for normal operation. To ensure proper chip functionality, these devices will be inactive until VIN exceeds the upper under· voltage lockout threshold. This pin should by bypassed directly to the GND pin with low ESR, low ESL capacitors.
NOTE: When V1N exceeds the UVLO threshold the supply current (hN) will jump from about 100UA to a current in excess of 20mA. If the UC1875 is not connected to a well bypassed supply, it may immediately enter UVLO again.
FREQ SET (oscillator frequency set pin) A resistor and a capacitor from FREQ SET to GND will set the oscillator frequenc¥ according to the following relationship:
4
f~
RFREQSET · CFREQSET
CLOCK/SYNC (bi-directional clock and synchronization pin): Used as as outpu~ this pin provides a clock signal. As an input, this pin provides a synchronization point In its simplest usage, multiple devices, each with their own local oscillator frequency, may be connected together by the CLOCK/SYNC pin and will synchronize on the fastest oscillator. This pin may also be used to synchronize the device to an external clock, provided the external signal is of higher frequency than the local oscillator. A resistor load may be needed on this pin to minimize the clock pulse width.
SLOPE (set ramp slope/slope compensation): A resistor from this pin to Voc will set the current used to generate the ramp. Connecting this resistor to the DC input line voltage will provide voltage feedforward.
RAMP (voltage ramp): This pin is the input to the PWM oomparator. Connect a capacitor from here to GND. A voltage ramp is developed at this pin with a slope:
dV
sense voltage
dT
RSLOPE · CRAMP
Current mode control may be achieved with a minimum amount of external circuitry, in which case this pin provides slope compensation . see the applications infonnation section for further information. Because of the 1.3V offset between the ramp input and the PWM comparator, the error amplifier output voltage can not exceed the effective ramp peak volt· age and duty cyde clamping is easily achievable with appropriate values of
RsLOPE and CRAMP·
E/A OUT (COMP) (Error amplifier output): This is is the gain stage for overall feedback oontrol. Error amp~fier output volt· age levels below 1 volt will force 0° phase shift. Since the error amplifier has a
relatively low current drive capability, the output may be overridden by driving with a sufficienUy low impedance source.
ElA · (Error Amplifier inverting input): This is normally connected to the voltage divider resistors which sense the power supply output voltage level.
UC1875/617/8 UC2875/6/7/8
UC3875/6/7/8
E/A+ (Error Amplifier non-inverting input): This is normally oonnected to a reference voltage used for comparison with the sensed power supply output voltage level at the EIA· pin.
SOFT-START: SOFT-START will remain at GND as long as V1N is below the UVLO threshold.SOFT-START will be pulled up to about 4.BV by an internal 9µA current source when V1N becomes valid (assuming a non-fault condition). In the event of a current-fault (C/S+ voltage exceeding 2.5V), SOFT-START will be pulled to GND and them ramp to 4.8V. If a fault occurs during the SOFT-START cycle, the outputs will be immediately disabled and SOFT-START must charge fully prior to resetting the fault latch. For paralleled oontrollers, the SOFT-START pins may be paralled to a single capacitor, but the charge currents will be additive.
C/S+ (current sense): The non-inverting input to the current-fault comparator whose reference is set internally to a fixed 2.5V (separate from VREF). When the voltage at this pin exceeds 2.5V the current-fault latch is set, the outputs are forced OFF and a SOFT-START cycle is initiated. If a oonstant voltage above 2.5V is applied to this pin the outputs are disabled from switching and held in a low state until the
C/S+ pin is brought below 2.5V. The outputs may begin switching at o
degrees phase shift before the SOFT-START pin begins to rise .. this condition will not prematurely deliver power to the load.
OUT A-OUT D (outputs A·D): The outputs are 2A totem-pole drivers optimized for both MOSFET gates and level-shifting transformers. The outputs operate as pairs with a nominal 50% duty-cycle. The A-8 pair is intended to drive one half-bridge in the external power stage and is syncronized with the clock waveform. The C-D pair will drive the other half-bridge with switching phase shifted with recpect to the A-8 outputs.
DELAY SET A·B, DELAY SET C-0 (output delay control): The user programmed current flowing from these pins to GND set the tum-on delay for the corresponding output pair. This delay is introduced between turnoff of one switch and tum-on of another in the same leg of the bridge to provide a dead time in which the resonant switching of the external power switches takes place. Separate delays are provided for the two half-bridges to accommodate differences in the resonant capacitor charging currents.
VREF: This pin is an accurate 5V voltage reference. This output is capable of delivering about 60mA to peripheral circuitry and is internally short circuit current limited. VREF is disabled while V1N is low enough to force the chip into UVLO. The circuit is also in UVLO until VREF reaches approximately 4.75V. For best results bypass VREFwith a0.1uF, low ESR, low ESL, capacitor to the GND pin.
5-260
UC1875/617/8 UC2875/6/7/8 UC3875/6/7/8 APPLICATIONS INFORMATION UNDER VOLTAGE LOCKOUT SECTION
When power is applied to the circuit and VIN is below the upper UVLO threshold, l1N will be below GOOµA, the reference generator will be off, the fault latch is reset, the soft-start pin is discharged, and the outputs are actively held low.
When VIN exceeds the upper UVLO threshold, the reference generator turns on. All else remains in the shut-down mode until the output of the reference, VREF, exceeds 4. 75V
v,.
10.75/Q.25V
GND~
4.75V
To Soft-Start logic
OSCILLATOR
The high frequency oscillator may be either free-running or externally synchronized. For free-running operation, the frequency is set via an external resistor and capacitor to ground from the FREQ. SET pin.
SIMPLIFIED OSCILLATOR SCHEMATIC
ClocW Sync
04
05
To logic
4.3V Freq Set
3.3V 4.3V 3.3V
The CLOCK/SYNC pin of the oscillator may be used to synchronize multiple UC1875 devices simply by connecting the CLOCK/SYNC of each UC1875 to the others:
5-261
APPLICATIONS INFORMATION (CONTINUED) SYNCHRONIZING THE OSCILLATOR
1875/617/S's only
Freq Set IC1
Clk/Sync
Syncing to external TTUCMOS
Freq Set IC2
Clk/Sync
Freq Set ICN
Clk/Sync
UC1875/6n/8 UC2875/6n/8 UC3875/6n/8
All ICs will sync to chip with the fastest local oscillator.
R1 & RN may be needed to
keep sync pulse narrow due to capacitance on line.
R1 & RN may also be needed
to properly terminate rsync line.
Freq Set IC2
Clk/Sync
Freq Set ICN
Clk/Sync
ICs will sync to fastest chip or TTL clock if it is higher freq.
R & RN may be needed for same reasons as above
Although each UC1875/6/7/8 has a local oscillator frequency, the group of devices will synchronize to the fastest oscillator driving the CLOCK/SYNC pin. This arrangement allows the synchronizing connection between ICs to be broken without any local loss of functionality. Synchronizing the device to an external clock signal may be accomplished with a minimum of external circuitry, as shown in the previous figure. Capacitive loading on the CLOCK/SYNC pin will increase the clock pulse width, and may adversely effect system performance. Therefore, a resistor to ground from the CLOCK/SYNC pin is optional, but may be required to offset capacitive loading on this pin. These resistors are shown in the oscillator schematics as R1,RN.
DELAY BLOCKS AND OUTPUT STAGES In each of the output stages, transistors 03 through 06 form a high-speed totem-pole driver which will source or sink more than one amp peak with a total delay of approximately 30 nanoseconds. To ensure a low output level prior to turn-on, transistors 07 through 09 form a sell-biased driver to hold 06 on prior to the supply reaching its turn-on threshold. This circuit is operable when the chip supply is zero. Q6 is also turned on and held low with a signal from the fault logic portion of the chip.
SIMPLIFIED OUTPUT STAGES v.,,
Rro
vTM
OU1
From lo ic
Current
""It
PWR
GND
The delay providing the dead-time is accomplished with C1 which must discharge to Vth before the output can go high. The time is defined by the current sources, 11, which is programmed by an external resistor, RTD. The voltage on the Delay Set pins is internally regulated to 2.5V and the range of dead time control is from 50 to 200 nanoseconds. NOTE: There is no way to disable the delay circuity, and the delay time must be programmed.
5-262
APPLICATIONS INFORMATION (CONTINUED)
OUTPUT SWITCH ORIENTATION The four outputs of the UC1875/6/7/8 interace to the full bridge converter switches as shown below:
UC1875/6/7/8 UC2875/6/7/8 UC3875/6/7/8
UC1875161718
3 Winding Bifilar. AWG 30 Kynar Insulation FAULT LOGIC The fault control circuitry provides two forms of power shutdown:
· Complete tum-off of all four output power stages. · Clamping the phase shift command to zero. Complete turn-off is ordered for an over-currant fault or a low supply voltage. Whan the SOFT-START pin reaches its low threshold, switching is allowed to proceed while the phase-shift is advanced from zero to its nominal value with the time constant of the SOFT-START capacitor. The fault logic insures that a continuous fault will institute a low frequency "hiccup" retry cycle by forcing the SOFT-START capacitor to charge through its full cycle between each restart attempt.
FAULT/SOFT-START
UVLO VREF 9pA ToE/A
23011A
Vee
UVLO - - - - - i - - - - - - - - - - - - - - - - - - - - - - -
Active
5-263
APPLICATIONS INFORMATION (CONTINUED)
RAMP GENERATION The ramp generator may be configured for the following control methods:
· Voltage Mode · Voltage Feedforward · Current Mode · Current Mode with Slope Compensation
SLOPE/RAMP PINS
Voltage Mode Operation
Suppl'j Vottage fisLOPE
Slope
UC1875/617/8 UC2875/6/7/8 UC3875/6/7/8
1. Simple voltage mode operation achieved by placing RSLOPE between V1N&SLOPE
2. Voltage Feedforward achieved by placing RSLOPE between supply voltage and slope pin of UC1875.
Ramp dV
dT
VRSLOPE RSLOPE CRAMP
For current-mode control the ramp generator may be disabled by grounding the slope pin and using the ramp pin as a direct current sense input to the PWM comparator. Figure 7 shows a current-mode configuration with slope compensation. Res reconstructs the current wafeform from a current-sense transformer while the voltage across CR adds a compensating ramp. Note that Res should be of a sufficiently low value to allow CR to be fully discharged by the ramp circuitry.
Current Mode Slope Compensation/Operation
Supply Voltage
Added slope dV
dT
VRSLOPE RSLOPECR
]i
UNITRIDE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD.· MERRIMACK, NH 03054
TEL. (603) 424-2410 ·FAX (603) 424-3460
5-264
n n l::::::J
INTEGRATED CIRCUIT&
-UNITRCDE
Two Stage Power Factor Converter
UC1891/2/3/4 UC2891/2/3/4 UC3891 /2/3/4
PRELIMINARY
FEATURES Single Chip Solution for Power Factor Corrected Power Systems Worldwide Operation Without Switches Fixed Frequency PWM Drive for Both Pre- and Post- Regulators Low Offset Analog Multiplier/Divider 5 MHz, Low Offset Current Amplifier Trimmed :1:6% Oscillator Frequency Over Voltage Fault Comparator Low Ice Startup Current, 650µa Typical Trimmed :1:1 % 7.SV Reference Independent Maximum Multiplier Output Current Clamp 15/1 OV, 11 /1 OV UVLO Thresholds Single-Ended or Double-Ended Post-Regulator Output Configurations 1A Totem Pole MOSFET Drivers
BLOCK DIAGRAM
DESCRIPTION
The UC1891 /2/3/4 family of power supply controller ICs combine an active Power Factor corrected boost pre-regulator with a Voltage mode PWM down converter for post regulation. Line voltage feedforward in the preregulator allows the converter to achieve near unity power factor over the full international range of line voltages. The post regulator is configurable for either single-ended or push-pull topologies providing a true single chip solution.for PFC power systems.
The boost pre-regulator front end is implemented with line-compensated, average current mode control, for low distortion, continuous input current. Average current mode control accurately maintains sinusoidal line current without the need for slope compensation, unlike peak current mode control. The pre-regulator employs a low offset high bandwidth current amplifier, a separate voltage amplifier, an analog multiplier/divider, 1A totem pole MOSFET driver, and latched overvoltage and overcurrent comparators.
The PWM post-regulator section is configurable as either a single-ended or double-ended controller. A PWM comparator, PWM latch, toggle FF, and Dual 1A totem pole MOSFET drivers are included to realize the desired configurations. Voltage control can be implemented through an optical coupler from an isolated output.
An accurate fixed-frequency oscillator provides synchronization for both controllers. Restart delay and softstart circuits deliver highly predictable startup and fault management for the controllers. Part selectable UVLO thresholds provide the flexibility to start the controller from an auxiliary winding or a separate 12V regulator.
Additional features include low (1 mA} startup current, a 1% trimmed 7.SV reference, and an independent multiplier maximum output current clamp.
These devices are available in the 28-pin QP package as well as the 24pin J and 24-pin N packages.
Soft Start
Buck Output
Buck Output
6/93
5-265
BOOlt PFC Output
PRODUCT SCHEDULE
UVLO Thresholds L 15Von 10Voff
l 11V on 10V off
Post R1u1_ulator Outlluts
Alternating
Parallel
..LMaxDC<5~ _l_Mmt.!2_C < 100%.l_
1891
1893
1892
1894
UC1891/2/3/4 UC2891/2/3/4 UC3891/2/3/4
CONNECTION DIAGRAM
DIL-24 (TOP VIEW) N or J PACKAGE
PLCC-28 (TOP VIEW) QPPACKAGE
OUTa ~
OUTe II
N/C II
g PWM
Ro II Ss II
SNS~
VAO II N/C II
CT~ SGND~
RT @:
l!!J PGND
Iml!!J Vee OUTA
~ VREF ~ PKL ~ CAO ~ FLT
t!!l RMS
~CA~ VAC
l3!El CA+ IMAX
L4 ~ 3 2 1 28 27 26
~5
25
~6
24
~7
23
de
22p
9
21~
~o
20~
11
19~
12 13 14 15 16 17 18
PACKAGE PIN FUNCTIONS
Function
Pin#
IMAX
1
CA+
2
VAc
3
CA-
4
RMS
5
FLT
6
CAO
7
PKL
8
VREF
9
OUTA
10
Vee
11
PGND
12-18
OUTB
19
OUTe
20
Ro
22
Ss
23
SNS
24
VAO
25
CT
26
SGND
27
RT
28
ELECTRICAL CHARACTERISTICS:
Unless specified Vee=18V, RT=15k, CT=1.5nF, RIMAX=15k, PKL=1V, VRMS=1.5V, IVAe=100µA, VeA-=OV Olo=3V, VA0=5V, VSNS=3.0V, -55°C <TA< 125·c for the UC189X, -40°C <TA< 85°C for the UC289X, and o·c <TA< 10°c for the UC389X, TA=TJ.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNITS
Overall
Supply Current, Off
CAO, VAO = ov, Vee= UVL0-0.5V
600
1200
µA
Supply Current, On Vee Turn-on Threshold Vee Turn-off Threshold Vee Turn-on Threshold Vee Turn-off Threshold
1891, 1893 1892, 1894
25
30
mA
15
16
v
9
10
v
11
11.5
v
9
10
v
Volta_g_e Am_j)llfler Input Voltage
VAOUT =3.5V
2.9
3.1
v
VSENSE Bias Current
-500
25
500
nA
Open Loop Gain VourHigh VourLow
VAOUT=2 to 61/
ILOAD = ·200µA
= ILOAD 200µA
70
100
dB
5.8
v
0.3
0.5
v
Output Short Circuit Current
VAOUT = 0V
1.5
2.2
mA
Gain Bandwidth Product
FIN=1 OOkHz, 1OmV p-p
1
mHz
5-266
ELECTRICAL CHARACTERISTICS (cont.):
PARAMETER Current Amplifier
Input Offset Voltage Input Bias Current (sense) Gain Output Swing Short Circuit Current PSRR Common Mode Range Gain Bandwidth Product Reference Output Voltage
Load Regulation Line Regulation Short Circuit Current Oscillator Initial Accura~ Voltage Stability Total Variation Ram_E._Am~itude~ Ram_p Valley Voltage Fault Management Fault Comparator VTH Fault Comp Input Blas Fault Pro_e_agation Delay Ss Charge Current PK Limit Offset Voltage PK Limit l~ut Current PK Limit Prop. Dell!l_ Mult~er Output Current - IAe Limited Output Current - Zero Output Current - RMULT Limited Output Current - Power Limited Output Current Out~ Current Output Current Output Current Gain Constant Gate Drivers A, B, C Output High Clamp Voltage Output High Voltage Output Low Voltage Output Low (UVLO)
UC1891/2/3/4 UC2891/2/3/4 UC3891/2/3/4
Unless specified Vee=18V, RT,,;15k, CT=1.5nF, RIMAX=15k, PKL=1V, VRMS=1.5V, IVAe=1 OOµA, VeA-=OV CA0=3V, VA0=5V, VSNS=3.0V, -55°C <TA < 125°C for the uc189X, -40°C < TA< 85°C for the UC289X, and o·c < TA< 10°c for the UC389X, TA=TJ.
TEST CONDITIONS
MIN
TVP
MAX UNITS
0.5to 7.5V CAOUT=OV Vee= 12 to 24V
FIN= 100 kHz, 10mV p-p
-1
2
mV
-500
500
nA
80
110
dB
1.5
65
85
-0.3
2
3.5
2
mA
dB
4
v
mHz
IREF = OmA, TA= 25°C IREF = OmA IREF= 1to10mA Vee= 15to 35V VREF =OV
7.425
7.5
7.575
v
7.35
7.5
7.65
v
-15
15
mV
-10
10
mV
15
40
70
mA
TA= 25°C Vee= 12 to 18V Line, Temp
48
53
kHz
1
%
45
55
kHz
4.8
5.6
v
0.8
1.3
v
VFAULT = 2.5V VSOFTSTART = 2.5V VPKUMIT = -0.1V
1.9
2
2.1
v
0.3
3
µA
250
ns
3
10
20
µA
-10
10
mV
-200
-100
~
200
ns
IAe = 1OOµA, VRMS = 1V IAe=OµA 1Ae=500µA IAe = 1OOµA, VRMS = 1.5V, VA= 5.6V IAe= 100µA, VRMS= 1.5V, VA=2V IAe= 10~ VRMS= 1.5V, VA=5V IAe = 100µA, VRMS = 5V, VA= 2V IAe = 100µA, VRMS = 5V, VA= 5V Refer to Note 1
-220
-200
-180
µA
-2
-0.2
2
µA
-280
-250
-220
µA
-230
-205
-180
µA
-55
-45
-35
µA
-215
-180
-145
~
-20
-4
0
µA
-25
-16
5
µA
-1
No load, Vee= 18 to 35V IOUT = -200mA, Vee = 15V IOUT=200mA IOUT = 50mA, Vee = ov
14
15
16
v
12
12.8
v
1.6
2.2
v
0.9
1.5
v
5-267
UC1891/2/3/4 UC2891/2/3/4 UC3891/2/3/4
ELECTRICAL CHARACTERISTICS (cont.):
Unless specified Vcc=18V, RT=15k, Cr=1.5nF, RIMAX=15k, PKL=1V; VRMS=1.5V, IVAC=1 OOµA, VcA-=OV C'Ao=3V, VA0=5V, VSNS=3.0V, -55°C < TA< 125°C for the UC189X, -40°C <TA< 85°C for the UC289X, and 0°C <TA< 70°C for the UC389X, TA=TJ.
PARAMETER Gate Drlven1 A, B, C (cont.)
TEST CONDITIONS
MIN
TYP
MAX UNITS
Output RISE/FALL Time Output Peak Current Deadtime (B & C only)
CLOAD= 1nF CLOAD= 10nF CT= 1nF
35
ns
1
A
600
ns
= Note 1. Gain Constant (k) IAC (VA~ - 1V)
VRMS x IMO
where: IMO= Multiplier Ouput Current 1.5V:S VRMS :S 5.0V
2.0V :S VAO :S 5.0V
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. · MERRIMACK, NH 03054
TEL (803) 424-2410 · FAX (803)424-3480
5-268
n n INTEGRATED
~CIRCUIT&
-uNITRCDE
Isolated Feedback Generator
UC1901 UC2901 UC3901
FEATURES An Amplitude-Modulation System for Transformer Coupling an Isolated Feedback Error Signal
Low-Cost Alternative to Optical Couplers
Internal 1% Reference and Error Amplifier
Internal Carrier Oscillator Usable to 5mHz
Modulator Synchronizable to an External Clock
Loop Status Monitor
DESCRIPTION The UC1901 family is designed to solve many of the problems associated with closing a feedback control loop across a voltage isolation boundary. As a stable and reliable alternative to an optical coupler, these devices feature an amplitude modulation system which allows a loop error signal to be coupled with a small RF transformer or capacitor.
Tt1e programmable, high-frequency oscillator within the UC1901 series permits the use of smaller, less expensive transformers which can readily be built to meet the isolation requirements of today's line-operated power systems. As an alternative to RF operation, the external clock input to these devices allows synchronization to a system clock or to the switching frequency of a SMPS.
An additional feature is a status monitoring circuit which provides an active-low output when the sensed error voltage is within ±10% of the reference.
Since these devices can also be used as a DC driver for optical couplers, the benefits of 4.5 to 40V supply operation, a 1% accurate reference, and a high gain general purpose amplifier offer advanlages even though an AC system may not be desired.
UC1901 SIMPLIFIED SCHEMATIC
OSutatptuust 1 13 ------------.....,
Drivers
VIN
INV Input
5/93
5-269
ABSOLUTE MAXIMUM RATINGS (Note 1)
Input Supply Voltage, VIN ........................... 40V Reference Output Current . . . . . . . . . . . . . . . . . . . . . . . -1 OmA Driver Output Currents . . . . . . . . . . . . . . . . . . . . . . . . . . -35mA Status Indicator Voltage ............................ 40V Status Indicator Current ....... : . . . . . . . . . . . . . . . . . . 20mA
Ext. Clock Input................................... 40V
Error Amplifier Inputs ...................... -0.5V to +35V Power Dissipation at TA= 25°C .................. 1OOOmW Power Dissipation at Tc= 25°C .................. 2000mW Operating Junction Temperature ........... -55°C to +150°C Storage Temperature .......... , ......... -65°C to +150°C Lead Temperature (Soldering, 10 seconds)........... 300°C
CONNECTION DIAGRAMS
DIL·14, SOIC-14 (TOP VIEW)
J or N Package, D Package
UC1901 UC2901 UC3901
Note 1: Voltages are referenced to ground, Pin 7. Currents are positive into, negative out of the specified terminal.
Note 2: Consult Packaging section of Databook for thermal limitations and considerations ofpackage.
PLCC·20, LCC-20
PACKAGE PIN FUNCTION
(TOPVIEW) Q, L Packages
FUfiltTION
PIN
_N/C
1
CT
2
l'll.C
3
Ext. Clock
4
- Driver B
5
L3 2 1 2019
NLC
6
4
18
Driver A N_LC
7 8
5
17
NLC
9
6
16
Gnd
10
7
15
l'll.C
11
RT
12
8
14
VREF
13
9 10 11 12 13
N_LC
14
NI lrm..ut
15
NLC
16
INV IDQ.ut
17
Com_D_
18
Status Oull!_ut
19
+VIN
20
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA= 55°C to+125°C forthe uc1901; -40°C to +85°C for the uc2001 ; and o·c to +10°c for the UC3901 ; V1N = 10V, RT= 10kQ, CT= 820pF, TA= TJ.
PARAMETER
TEST CONDITIONS
Reference Section
Output Voltage
TJ=25°C
TMIN :s TJ :s TMAX
Line Reg_ulation Load R~lation
VIN = 4.5 to 35V IOUT = 0 to 5mA
Short Circuit Current
TJ =25°C
Error Am_elifier Sectionl!_o Com_e_ensation Termina.!}_
1'!2_ut Offset Volta_.lle
VcM = 1.5V
ll'!Q!Jt Bias Current
VcM = 1.5V
1'!2_ut Offset Current
VcM = 1.5V
Small S!g_nal O_Q_en Loo_Q_ Gain
CMRR
VcM = 0.5 to 7.5V
PSRR
VIN =2to25V
Out_Q_Ut Swir:!.9,_ A Vo
Maximum Sink Current
Maximum Source Current
Gain Band Width Product
Slew Rate
Modulators/Drivers SectionjFrom Com_J)llnsation Terminal)_ Volt~eGain
Out_Q_ut Swi~
UC1901/UC2901
UC3901
UNITS
MIN TYP MAX MIN TYP MAX
1.485 1.5 1.515 1.47 1.5 1.53
v
1.470 1.5 1.530 1.455 1.5 1.545
2
10
2
15 mV
4
10
4
15 mV
-35 -55
-35 -55 mV
1
4
1
8
mV
-1
-3
-1
-6 118_
0.1
1
0.1
2
~
40
60
40
60
dB
60
80
60
80
dB
80 100
80 100
dB
0.4 0.7
0.4 0.7
v
90 150
90 150
~
-2
-3
-2
-3
mA
1
1
MHz
0.3
0.3
vm_s
11
12
13
10
12
14
dB
±1.6 ±2.8
±1.6 ±2.8
v
5-270
UC1901
UC2901
UC3901
ELECTRICAL
Unless otherwise stated, these specifications apply for TA= 55°C to +125°C for the UC1901;
CHARACTERISTICS (cont.): -40°Cto +85°Cforthe UC2901; and o·cto +70°Ctorthe UC3901; VIN= 1ov, RT= 10kQ, CT=
820pF, TA=TJ.
PARAMETER
TEST CONDITIONS
UC1901/\IC2901
UC3901
UNITS
MIN TYP MAX MIN TYP MAX
Modulators/Drivers Section~ontj_
Driver Sink Current
500 700
500 700
µA
Driver Source Current
-15 -35
-15 -35
mA
Gain Band Width Product
25
25
MHz
Osclllator Section
Initial Accuracy
TJ= 25°C
140 150 160 130 150 170 kHz
TMIN :< TJ :< TMAX
130
170 120
180 kHz
Line Sensitivitv Maximum Fr~ue~
VIN= 5to35V RT= 10k, CT= 1~
.15 .35 5
.15 .60 o/oN
5
MHz
Ext. Clock Low Threshold
Pin 1j_C!)_= VIN
0.5
0.5
v
Ext. Clock Hj_g_h Threshold
Pin 1j_C!)_= VIN
1.6
1.6 v
Status Indicator Section
llll?._ut VoltaJle Window
l.@_E/A l'!e_uts VCM = 1.5V
±135 ±150 ±165 ±130 ±150 ±170 mV
Saturation Volt~e
E/A A l'!e_ut = OV, ISINK = 1.6mA
0.45
0.45 v
Max. O~ut Current
Pin 13 = 3V, E/A /1 ll]?_Ut = 0.0V
8
15
8
15
mA
Leak~e Current
Pin 13 = 40V E/A Allll?._Ut = 0.2V
.05
1
.05
5
µA
Supply Current
VIN=35V
5
8
5
10 mA
Transformer Coupled Open Loop Transfer Function
Input
Output 270pF
c "iii
80
l==+:::::::......,_--i--
VIN=10V Osc f=1Ml;iz
e> 70
,.._
TJ =25 C
!!!
"'S: G) 60
~!J: 0:
50 40
~ ~GAIN----1
-~
l"I..
0 ~
> ·c; 30 "--{,,_ PHASE
45 Q,
g.~ 20
~
.3 10
~ ~
90 ::I
135-&.
~ 0
180
Q.
0
10 100 1k 10k 100k 1M
Frequency-Hertz
Transformer Data: N1 = N2 = 20TAWG 26 Core= Ferroxcube 3E2A Ferrite, 0.5" O.D. toroid
= Carrier Frequency 1MHz
uc>.
.:I .O"
il: l:i
..·~a
0 103 ~~-~-~-~~ 105 104 103 102 10
Cr Value - Picofarads Oscillator Frequency
5-271
" ~>~
;§ ~
-'
3.4 3.2
3.0
~ ........
~ g' 2.8
5i "i 2.6
lii en 2.4
~
"h
;: :; 2.2
I
]"-,.
c §:: 2.0
b,,.
~ :; 1.8
D..
~ 0 1.6
LI) LI) LI) LI) LI) LI) LI) LI) LI) LI)
u;>'?"7 C\IVCO«>~~
Temperature - (° C)
Typical Driver Output Swing vs Temperature
APPLICATION INFORMATION The error amplifier compensation terminal, Pin 12, is Intended as a source of feedback to the amplifier's inverting input at Pin 11. For most applications, a series DC blocking capacitor should be part of the feedback network. The amplifier is internally compensated for unity feedback.
The waveform at the driver outputs is a squarewave with an amplitude that is proportional to the error amplifier input signal. There is a fixed 12dB of gain from the error amplifier compensation pin to the modulator driver outputs. The frequency of the output waveform is controlled by either the internal oscillator or an external clock signal. With the internal oscillator the squarewave will have a
UC1901 UC2901 UC3901
fixed 50% duty cycle; If the internal .oscillator is disabled by connecting Pin 1, CR, to VIN then the frequency and duty cycle of the output will be determined by the input clock waveform at Pin 2. If the oscillator remains disabled and there is not clock input at Pin 2, there will be a linear 12dB of signal gain to one or the other of the (!river outputs depending on the DC state of Pin 2. ·
The driver outputs are emitter followers which will source a minimum of 15mA of current. The sink current, internally limited at 700µA, can be increased by adding resistors to
ground at the driver outputs.
R.F. Transformer Coupled Feedback
I PowPerrimaanrdy Swltchea
:
.
-
-
-
-
-
~I
'
'
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
.
.
.
,
.
,
(
)
oSupply
utput
To Supply-WiJ...:.:::=---~ · Monitor
ToPWM~ll
Controller. ~ RF Coupling Transformer
Feedback Coupled at Switching Frequency
Power Transformer To Supply
Monitor
CToontPrWolMl~elr~l
RF Coupling Transformer
5.272
TYPICAL APPLICATIONS
Power Transformer To Supply
Monitor
Optically Coupled DC Feedback
UC1901 UC2901 UC3901
UNITROOE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. · MERRIMACK, NH 03054 TEL. (603) 424-2410 · FAX (603)424-3480
5-273
n n IN.TEGRATED
~CIRCUITS
-UNITRODE
Quad Supply and Line Monitor
UC1903 UC2903 UC3903
FEATURES Inputs for Monitoring up to Four Separate Supply Voltage Levels
Internal Inverter for Sensing a Negative Supply Voltage
Line/Switch Sense Input for Early Power Source Failure Warning
Programmable Under- and Over-Voltage Fault Thresholds with Proportional Hysteresis
A Precision 2.5V Reference
General Purpose Op-Amp for Auxiliary Use
Three High Current, >30mA, Open-Collector Outputs Indicate Over-Voltage, Under-Voltage and Power OK Conditions
Input Supply Under-Voltage Sensing and Start-Latch Eliminate Erroneous Fault Alerts During Start-Up
8-40V Supply Operation with 7mA Stand-By Current
BLOCK DIAGRAM
DESCRIPTION
The UC1903 family of quad supply and line monitor integrated circuits will respond to under- and over-voltage conditions on up to four continuously monitored voltage levels. An internal op-amp inverter allows at least one of these levels to be negative. A separate line/switcher sense input is available to provide early warning of line or other power source failures.
The fault window adjustment circuit on these devices provides easy programming of under- and over-voltage thresholds. The thresholds, centered around a precision 2.5V reference, have an input hysteresis that scales with the window width for precise, glitch-free operation. A reference output pin allows the sense input fault windows to be scaled independently using simple resistive dividers.
The three open collector outputs on these devices will sink in excess of 30mA of load current when active. The under- and over-voltage outputs respond after separate, user defined, delays to respective fault conditions. The third output is active during any fault condition including under- and over-voltage, line/switcher faults, and input supply under-voltage. The off state of this output indicates a "power OK" situation.
An additional, uncommitted, general purpose op-amp is also included. This op-amp, capable of sourcing 20mA of output current, can be used for a number of auxiliary functions including the sensing and amplification of a feedback error signal when the 2.5V output is used as a system reference.
In addition, these ICs are equipped with a start-latch to prevent erroneous un-
av der-voltage indications during start-up. These parts operate over an to
40V input supply range and require a typical stand-by current of only 7mA.
OUTPUT@6 INV. 18
N.I. 17 SENSE 1 9
SENSE 2 SENSE 3 SENSE 4
ENERAL PURPOSE
OP·AMP
'------+----I
SENSE 4 INVERT 51---+'..._ INPUT
VIN
SUPPLY UNDERVOLTAGE
SENSE
O.V.DELAY U.V.DELAY U.V.FAULT
VREF (2.5V)
WINDOW ADJUST
6/93
5.274
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage (+VIN) ............................. +40V Open Collector Output Voltages ..................... +40V Open Collector Output Currents. . . . . . . . . . . . . . . . . . . . 50mA Sense 1-4 Input Voltages ................... -0.3V to +20V Line/Switcher Sense Input Voltage ........... -0.3V to +40V Op-Amp and Inverter Input Voltages .......... -0.3V to +40V Op-Amp and Inverter Output Currents . . . . . . . . . . . . . . -40mA Window Adjust Voltage..................... O.OV to +10V Delay Pin Voltages . . . . . . . . . . . . . . . . . . . . . . . . . O.OV to +5V Reference Output Current . . . . . . . . . . . . . . . . . . . . . . . -40mA Power Dissipation at TA = 25°C (Note 1) ........... 1OOOmW Power Dissipation at Tc= 25°C (Note 1) ........... 2000mW Operating Junction Temperature ........... -55°C to +150°C Storage Temperature .................... -65°C to+150°C Lead Temperature (Soldering, 10 Seconds) .......... 300°C
DIL-18, SOIC-18 (TOP VIEW)
J or N, OW Package
+VIN
VREF (2.5V) 2
GROUND 3 WINDOW ADJUST
INVER5l~~~ui 5
G.P. OP-AMP INV. G.P. OP-AMP N.I. G:P. OP-AMP OUT LINE/SWITCHER SENSE
POWER OK
UV DELAY
UV FAULT
OV DELAY
UC1903 UC2903 UC3903
Note 1: Voltages are referenced to ground (Pin 3). Currents are positive into, negative out of, the specified terminals. Consult Packaging Section of Databook for thermal limitations and considerations of package.
CONNECTION DIAGRAMS
PLCC-20, LCC-20 (TOPVIEW) Q, L Package
L3 2 1 20 19
4
18
5
17
6
16
7
15
8
14
9 10111213
PACKAGE PIN FUNCTION
FUNCTION
PIN
+VIN
1
VREFj_2.5'{)_
2
GROUND
3
GROUND SENSE
4
WINDOW ADJUST
5
N/C
6
SENSE 4 INVERT
7
INPUT
SENSE4
8
SENSE3
9
SENSE2
10
SENSE 1
11
OVDELAY
12
OVFAULT
13
UV FAULT
14
UV DELAY
15
POWER OK
16
LINE/SWITCHER
17
SENSE
G.P. OP-AMP OUT 18
G.P. OP-AMP N.I.
19
G.P. OP-AMP INV.
20
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA= 55°C to +125°C for the UC1903; -40°C to +85°C for the UC2903; and 0°c to +70°C for the UC3903; +V1N = 15V; Sense Inputs (Pins 6--9 and Pin 15) = 2.5V; VPIN 4 = 1.0V, TA= TJ.
PARAMETERS
Supply Input Supply Current
Supply Under Voltage Threshold (Vsu-1_ Minimum Supply to Enable Power OK Output Reference Output Voltage (VREF)
Load R~ulation Line R~ulation Short Circuit Current Fault Thresholds OV Threshold Adj.
UV Threshold Adj.
TEST CONDITIONS
No Faults UV, OV and Line Fault Fault Outputs Enabled
UC1903 / UC2903 MIN TYP MAX
7
9
10 15
6.0 7.0 7.5
3.0 4.0
TJ = 25°C Over Te~rature IL= Oto 10mA +VIN= 8 to 40V TJ = 25°C
2.485 2.5 2.515
2.465
2.535
1
10
1
4
40
Offset from VREF as a function of VPIN 4 .230 .25 .270 lt!E_Ut =Low to High, 0.5V s VPIN 4 s 2.5V
Offset from VREF as a function of VPIN 4 -.270 -.25 -.230 Input= High to Low, 0.5V s VPIN 4 s 2.5V
UC3903
UNITS
MIN TYP MAX
7
11 mA
10
18 mA
5.5 7.0 8.0
v
3.0 4.0
v
v 2.470 2.5 2.530
2.465
v 2.535
1
15 mV
1
8
mV
40
mA
.230 .25 .270 VN -.270 -.25 -.230 VN
5-275
UC1903 UC2903 UC3903
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA = 55°C to +125°C for the
UC1903; -40°Cto +85°Cfor the UC2903; and 0°C to +70°C for the UC3903; +VIN= 15V; Sense Inputs (Pins 6-9 and Pin 15) = 2.5V; VPIN 4 = 1.0V, TA = TJ.
PARAMETERS
TEST CONDITIONS
UC1903/UC2903
UC3903
UNITS
MIN TYP MAX MIN TYP MAX
Fault ThresholdsJ.cont.:L
OV & UV Threshold ~t.
OV & UV Threshold Supply Sensitiv_i!y_
0.5V s VPIN 4 s 2.5V
av +VIN= to 40V
Adjust Pin (Pin 4) ln_put Bias Current
0.5V s VPIN 4 s 2.5V
Line Sense Threshold
l~ut = High to Low
Line Sense Threshold Hyst.
Sensel~ts
Sense 1-4 Input Bias Current
l~ut = 2.SVJ_Note 21 Input= 2.2 (Note 2)
Line Sense Input Bias Current
Input= 2.3V (Note 2)
10
20
30
.002 .01
10
20
30 mVN
.002 .02 %N
±1 ±10
±1 ±12 µAN
1.94 2.0 2.06 1.9 2.0 2.1
v
125 175 225 100 175 250 mV
1
3
-1
-3
1
3
1
6 ~
-1
-6
µA
1
6
µA
OV and UV Fault Delay Chargi11g_ Current Threshold Voltcig_e Threshold H~teresis
Delay Pin = Low to H.![h TJ = 25°C
60
60
~
1.8
1.8
v
250
250
mV
Delay
Ratio of Threshold Voltage to Charging
20
30
50
20
30
50 ms/µF
Current
Fault Outputs (OV, UV, & Power OK)
Maximum Current Satu ration Voltcig_e Leakcig_e Current Sense 4 InverterJ.Note ~ Input Offset Voltage Input Bias Current ~nLo~Gain
VOUT= 2V !OUT= 12mA VouT= 40V
30
70
30
70
mA
.25 .40
.25 .40
v
3
25
3
25 ~
2
8
2
10 mV
.1
2
.1
4
µA
65 80
65
80
dB
PSRR U~Gain F~uen<2'._ Slew Rate Short Circuit Current G.P. O_.e:-Am_ej_Note ~ ln_i:>_ut Offset Volt~ ln_i:>_ut Bias VoltaJ!_e ln_i:>_ut Offset Current Open Loop Gain CMRR PSRR Un_i!y_Gain Fr~uen<2'._ Slew Rate Short Circuit Current
+VIN = 8 to 40 V TJ = 25°C
VcM = 0 to +VIN= 2.0V +VIN= 8 to 40V TJ =25°C
65 100 1 .4 40
65 100 1 .4 40
dB MHz V/µs mA
1
5
.1
2
.01
.5
65 120
65 100
65 100
1
.4
40
1
8
mV
.1
4 ~
.01
1.0 ~
65 120
dB
65 100
dB
65 100
dB
1
MHz
.4
V/µs
40
mA
Note 2: These currents represent maximum input bias currents required as the sense inputs cross appropriate thresholds. Note 3: When either the G.P. OP-Amp, or the Sense 4 Inverter; are configured for sensing a negative supply voltage, the divider
resistance at the inverting input should be chosen such that the nominal divider current is s 1.4mA. With the divider current at or below this level possible latching of the circuit is avoided. Proper operation for currents at or below 1.4mA is 100% tested in production. Note 4: Reference to pin numbers in this specification pertain to 18 pin OIL N and J packages.
5-276
Typical 2.SV Reference Temperature Characteristic
~l~Mll: .2
.1 0 -.1
Q)
cC> .I.cll
-"2
I
I I
(.) -.3
Q) (..)
-.4
c
.Q...)
Q)
-.5
Qa:i -.6
-.7
-55 -35 -15 5 25 45 65 85 105125
Junction Temperature - (°C)
UC1903 UC2903 UC3903
Typical Fault Delay Temperature Characteristic (CDELAY "' 270pF)
40
1 1
1
~
I/)
E
35
~ ~
I
~II
1 I '
30
l'i--L I
J J
1
25
i
1 I
20
1 I
-55 -35 -15 5 25 45 65 85 105125
Junction Temperature - (°C)
OPERATION AND APPLICATION INFORMATION
I1Uc1003+VN
1.25V
+
VADJ
BIAS
L
CANCELLATION AND MIRROR CIRCUITS
TO OV HYSTERESIS CONTROL
OV THRESHOLD
FAULT WINDOW
THRESHOLD & HYSTERESIS
CIRCUITS
UV THRESHOLD
TO UV HYSTERESIS CONTROL
Figure 1. The UC1903 fault window circuitry generates OV and UV thresholds centered around the 2.5V reference. Window magnitude and threshold hysteresis are proportional to the window adjust input voltage at Pin 4.
5-277
OPERATION AND APPLICATION INFORMATION Setting a Fault Window The fault thresholds on the UC1903 are generated by creating positive and negative offsets, equal in magnitude, that are referenced to the chip's 2.5V reference. The resulting fault window is centered around 2.5V and has a magnitude equal to that of the applied offsets. Simplified schematics of the fault window and reference circuits are shown in Figure 1 (see previous page). The magnitude of the offsets is determined by the voltage applied at the window adjust pin, Pin 4. A bias cancellation circuit keeps the input current required at Pin 4 low, allowing the use of a simple resistive divider off the reference to set the adjust pin voltage.
The adjust voltage at Pin 4 is internally applied across R4, and an Bk resistor. The resulting current is mirrored four times to generate current sources loA, IOB, loc, and loo, all equal in magnitude. When all four of the sense inputs are inside the fault window, a no-fault condition, 04 and Os are turned on. In combination with D1 and D2 this prevents Los and Loo from affecting the fault thresholds. In this case, the OV and UV thresholds are equal to VREF + loA(Rs + Rs) and VREF - loc(R7 + Ra) respectively. The fault window can be expressed as:
(1)
2.5V ± VA4DJ.
In terms of a sensed nominal voltage level, Vs, the window as a percent variation is:
UC1903 UC2903 UC3903
hysteresis at the sense inputs which is always 8% of the window magnitude. This is shown graphically in Figure 2.
Fault Windows Can Be Scaled Independently In many applications, it may be desirable to monitor various supply voltages, or voltage levels, with varying fault windows. Using the reference output and external resistive dividers this is easily accomplished with the UC1903. Figures 3 and 4 illustrate how the fault window at any sense input can be scaled independently of the remaining inputs.
MONITORED SUPPLY VOLTAGE
(Vs)
R1
R2 R3
SENSE 1-4 INPUT
2.5V
REF. Fault window for the Sense Input, in percent, is:
± 10 (VAD~, R3 + R1R:~(R1 + R2i_
for:
Vs (NOM} · _R_1 i+::gR_2 =2.5V
Figure 3. Using the reference output and a resistive divider, a sense input with an independently wider fault window can be generated.
(2)
Vs± ( 10 · VADJ) %.
When a sense input moves outside the fault window given in equation(1), the appropriate hysteresis control signal turns off 04 or Os. For the under-voltage case, Os is disabled and current source loB flows through D2. The net current through R1 becomes zero as los cancels loc, giving an 8% reduction in the UV threshold offset. The overvoltage case is the same, with 04 turning off, allowing loo to cancel the current flow, JOA, through Rs. The result is a
~ 3.125
.. 3.0
:; 2.875
c. .5
2.750
....c 2.625
Cl) 2.50
;;; 2.375
.;0,i,: 2.25
c
it
;.;.
LL
1.5 2.0
25 20
!
.,,;i:
0 c
it
..-5 ;;
-10 LL
-15 ac..
" -20 Cl)
Window Adjust Voltage (VADJ) at Pin 4
Figure 2. The fault window and threshold hysteresis scale as a function of the voltage applied at Pin 4, the window adjust pin.
R1
Fault window for the sense input, in percent, is:
±10 (VAD~ · _R_1 i+::Rg2_
Figure 4. The general purpose op-amp on the UC1903 can be used to create a sense input with an independently tighter fault window. Figure 4 demonstrates one of many auxiliary functions that the uncommitted op-amp on the UC1903 can be used for. Alternatively, this op-amp can be used to buffer high impedance points, perform logic functions, or for sensing and amplification. For example, the G.P. op-amp, combined with the 2.5V reference, can be used to produce and buffer an optically coupled feedback signal in isolated supplies with primary side control. The output stage of this op-amp is detailed in Figure 5. The NPN emitter follower provides high source current capability. ;,;20mA while the substrate device, 03, provides good transient sinking capability.
5-278
UC1903
UC2903
OPERATION AND APPLICATION INFORMATION (continued}
UC3903
SENSE input goes from above to below 2.0V. The line
sense comparator has approximately 175mV of hystere-
75µA
sis requiring the line/switcher input to reach 2.175V before the POWER OK output device can be turned off,
allowing a no-fault indication. In Figure 7 an example
UC1903
ou~P~T 0s",:~~~ 01
showing the use of the LINE/SWITCHER SENSE input for early switcher-fault detection is detailed. A sample signal is taken from the output of the power transformer, rec-
tified and filtered, and used at the line/switcher input. By
adjusting the R2C time constant with respect to the
switching frequency of the supply and the hold up time of
the output capacitor, switcher faults can be detected be-
TO OP-AMP INPUT STAGE
fOre supply outputs are significantly affected.
R4 5000
150µA
Figure 5. The G.P. op-amp on the UC1903 has a high source current (~20mA) capability and enhanced transient sinking capability through substrate device Q3.
Sensing a Negative Voltage Level The UC1903 has a dedicated inverter coupled to the sense 4 input. With this inverter, a negative voltage level can be sensed as shown in Figure 6. The output of the inverter is an unbiased emitter follower. By tying the inverting input, Pin 5, high the output emitter follower will be reverse biased, leaving the sense 4 input in a high impedance state. In this manner, the sense 4 input can be used, as the remaining sense inputs would be, for sensing positive voltage levels.
R1
R2 NEGATIVE SUPPLY (-Vs)
R2
Vs(NOM) · 2.5V · fi2
Figure 7. The line/switcher sense input can be used for an early line or switcher fault indication.
OV and UV Comparators Maintain Accurate Thresholds The structure of the OV and UV comparators, shown in Figure 8 results in accurate fault thresholds even in the case where multiple sense inputs cross a fault threshold simultaneously. Unused sense inputs can be tied either to the 2.5V reference, or to another, utilized, sense input. The four under- and over-voltage sense inputs on the UC1903 are clamped as detailed on the Sense 1 input in
Figure 8. The series 2k resistor, R1, and zener diode Z1, prevent extreme under- and over-voltage conditions from inverting the outputs of the fault comparators. A parasitic diode, 01, is present at the inputs as well. Under normal operation it is advisable to insure that voltage levels at all of the sense inputs stay above -0.3V. The same type of input protection exists at the line sense input, Pin 15, except a 5k series resistor is used.
Note: A similar scheme withe G.P. op-amp will allow a second negative supply to be monitored. Figure 6. Inverting the sense 4 input for monitoring a negative supply is accommodated with the dedicated inverter.
Using The Line/Switcher Sense Output The line switcher sense input to the UC1903 can be used for early detection of line, switcher, or other power source, failures. Internally referenced to 2.0V, the line sense comparator will cause the POWER OK output to indicate a fault (active low) condition when the LINE/SWITCHER
The fault delay circuitry on the UC1903 is also shown in Figure 8. In the case of an over-voltage condition at one of the sense inputs 020 is turned off, allowing the internal 60µA current source to charge the user-selected delay ~acitor. When the capacitor voltage reaches 1.SV, the OV and POWER OK outputs become active low. When the fault condition goes away 020 is turned back on, rapidly discharging the delay capacitor. Operation of the under-voltage delay is, with appropriate substitutions, the same.
5-279
OPERATION AND APPLICATION INFORMATION (continued)
UC1903 UC2903 UC3903
SENSE 1 2K
R1
01
Z1
5.7V
(!J--SENSE 2 l!J--SENSE 3 l!J--SENSE 4
__3 __4
ov
TO
HYSTERESIS
ov
CONTROL
Tlf'IESHOLD
VOLTAGE
OV FAULT INDICATION TO OUTPUT LOGIC
UV FAULT INDICATION TO OUTPUT LOGIC
Figure 8. The OV and UV comparators on the UC1903 trigger respective fault delay circuits when one or more of the sense inputs move outside the fault window. Input clamps insure proper operation under extreme fault conditions. Terminating the UV delay capacitor to VREF assures correct logic at power up.
Start Latch and Supply Under-Voltage Sense Allow Predictable Power-Up The supply under-voltage sense and start-latch circuitry on the UC1903 prevents fault indications during start-up or low input supply (+VIN) conditions. When the input supply voltage is below the supply under-voltage threshold the OV and UV fault outputs are disabled and the POWER OK output is active low. The POWER OK output will remain active until the input supply drops below approximately 3.0V. With +VIN below this level, all of the open collector outputs will be off.
When the input supply is low, the under-voltage sense circuitry resets the start-latch. With the start-latch reset, the UV fault output will remain disabled until the input supply rises to its normal operating level (8-40V), and all of the sense inputs are above the under-voltage threshold. This allows slow starting, or supply sequencing, without an artificial under-voltage fault indication. Once the latch is set, the. UV fault output will respond if any of the sense inputs drop below the under-voltage threshold.
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. · MERRIMACK, NH 03054 TEL 603-<124-2410 · FAX 803-424-3460
5-280
n nINTEGRATED
~CIRCUIT&
-uNITRDDE
Precision Quad Supply and Line Monitor
UC1904 UC2904 UC3904
FEATURES Inputs for Monitoring Up to Four Supply Voltages Two Inputs Preset for -5V and -12V Monitoring, or Programmable Positive Levels Precision 2.5V Reference Separate Inputs for Over-Current and Line Fault Sensing Adjustable Under- to Over-Voltage Fault Windows Latched Over-Voltage and Over-Current Output Power Good and Power Warning Outputs Auto Restart Function with ON/OFF Control, and Programmable Delay Programmable Pwr On Reset Delay
BLOCK DIAGRAM
DESCRIPTION The UC1904 Quad Supply Monitor will respond to under- and over-voltage conditions on up to four continuously monitored voltage levels. Four independent positive voltages can be monitored or, alternatively, two of the sense inputs are preset to monitor -5V and -12V supplies. The device also monitors Over-Current and Line Sense inputs, both with precision input thresholds.
Four open collector outputs on the UC1904 give the following responses: 1. The OV/OC output is a latched over-voltage, or over-current response. 2. A Power Good signal responds low with any fault detection - on power-up a programmable delay is used to hold this output low for a system Power On Reset signal. 3. The PWRW output responds only to a Line Sense input, for early warning of power failures. 4. The last open collector, the ON/OFF output, generates a delayed supply OFF control signal in response to an OFF input command, under-voltage condition, or line fault detection.
The OV-UV fault window is adjustable with a programming input. The thresholds are centered around the precision 2.5V reference, with a scaled hysteresis for precise, glitch free operation. In the positive mode of operation, the fault windows at each of the sense inputs can be independently scaled using external resistors and the 2.5V reference output. An Auto Restart function couples with the under-voltage and line sensing circuits to allow controlled power supply start-up and shutdown.
This device will operate over a supply range of 4.75V to 18V. The device is available in a DIP, SOIC, or PLCC outline. This device is ESD protected on all pins.
oc
Input S1
2.0V/2.1V
Over Current
OV/OC Out
Supply UV Sense S3
'1..
POR Delay
VIN
Window
Thresholds
2.SV
REF
WADJ Gnd LS
Input
2.0V/2.1V
Note: Pin Numbers refer to J, N, and DW Packages.
5/93
2 POR DLY ARST Input
5-281
PG Out
PWRW Out
UC1904
ABSOLUTE MAXIMUM RATINGS (Note 1) Input Supply Voltage .....·.....··.......··.......· 20V Sense Inputs, S1 And S2, Other Analog And Logic Inputs
Maximum Forced Voltage ·......··.......·. -0.3V to 1OV Maximum Forced Current . . . . . . . · . . . . . . . . . . . . . . :t1 OrnA
UC2904
UC3904
Note 1: Unless otherwise indicated, voltages are reference to ground and currents are positive Into, negative-out of, the specified terminals.
Sense Input 83, (-12V Sense Input) Maximum Forced Voltage ...·......·....... -18Vto 10V Maximum Forced Current ...·................·. :t10rnA
Sense Input S4, (-5V Sense Input) Maximum Forced Voltage .................. -10Vto 10V Maximum Forced Current ...................... :t10rnA
CONNECTION DIAGRAMS
PLCC-20 (TOP VIEW) QPACKAGE
PACKAGE PIN FUNCTION
FUNCTION
PIN
2.5V
1
Open Collector Outputs
PORDLY
2
Maximum Voltage ............·.................· 'l.OV Maximum Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50rnA Reference Output Current · · . . . . · · . . . . . . . Internally Limited Operating Junction Temperature ..·.·...... -55°C to +150°C Storage Temperature ....··.............. -65°C to +150°C
L3 2 1 2019
4
18
5
17
6
16
N.C. S1 S2 S3 S4
3 4 5
6
7
DIL·18, SOIC-18 (TOP VIEW)
7
15
N.C.
8
J or N PACKAGE, OW PACKAGE
8
14
9 10 11 12 13
LS Input
9
OC l1!2_ut
10
PWRWOut
11
PG Out
12
OV/QCOut
13
VIN
14
ON/OFF Out
15
OFFDLY
16
LS Input 7
OC Input a PWRW Out I
Ot.f[OFF lm>_ut
17
ARST 11!2_ut
18
WADJ
19
Gnd
20
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications hold for TA= o to 10°c for the UC3904, -40 to +85°C for the UC2901._And -55 to +125°C for the UC1904, +VIN = 15V, WADJ = 0.5V, Sense Inputs 1-4, QC and LS Inputs= 2.5V. The ON/OFF Input and the ARST Input= OV.
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNITS
l!!e_ut Supply
VIN Supply Current VIN UVLO Threshold
VIN= 15V Low to High
3.2 4.5 mA
4.5 4.75 v
UVLO Threshold Hysteresis Minimum VIN to Enable PG Out
50
mV
0.8 1.5 v
Reference Output Voltage(VREF)
TJ =25°C Over Temperature, UC3904 Over Temperature, UC2904 & UC1904
2.475 2.5 2.525 v
2.47_
2.53 v
2.465
2.535 v
Load Regulation
IOUT = 0 to 4mA
6 mV
Line Regulation
VIN = 4.75 to 18V
5 mV
Short Circuit Current
VREF=OV
17
mA
OV UV Window, LS l!!e_ut, OC Input, ARST l!!e_ut, and ON/OFF l~t Thresholds
Over-Voltage Thresholds
WAOJ = 0.25V, Offset from VREF, Input L to H
110 125 140 mV
S1,S2
WADJ = 0.5V, Offset from VREF, I~ L to H
230 250 270 mV
WAOJ = 1V, Offset from VREF, Input L to H
460 500 540 mV
Over-Voltage Thresholds
WAOJ = 0.25V, Offset from VREF, Input L to H
110 125 145 mV
S3, S4 Positive Mode
WAOJ = 0.5V, Offset from VREF, Input L to H
v. WAOJ = 1 Offset from VREF, Input L to H
230 250 280 mV 460 500 550 mV
5-282
UC1904
UC2904
UC3904
ELECTRICAL
Unless otherwise stated, these specifications hold for TA = 0 to 70°C for the UC3904, -40 to
CHARACTERISTICS (cont): +85°Cforthe UC2904, and-55to +125°Cforthe UC1904, +VIN= 15V, WADJ = 0.5V, Sense
Inputs 1-4, OC and LS Inputs = 2.5V. The ON/OFF Input and the ARST Input = OV.
PARAMETER
TEST CONDITIONS
OV UV Window, LS Input, OC Input, ARST Input, and ON/OFF Input Thresholds (cont.)
MIN TYP MAX UNITS
Under-Voltage Thresholds
WADJ = 0.25V, Offset from VREF, Input H to L
S1, S2
WADJ = 0.5V, Offset from VREF, Input H to L
WADJ = 1V, Offset from VREF, Input H to L
Under-Voltage Thresholds
WADJ = 0.25V, Offset from VREF. lnputH t~L
S3, S4 Positive Mode
WADJ = 0.5V, Offset from VREF, Input H to L
WADJ = 1V, Offset from VREF, Input H to L
OV and UV Threshold ~teresis As a Function of WADJ
S3 Negative Mode Thresholds Over-Voltage, WADJ = 0.5V, Offset from VREF, Input H to L
Under-Voltage, WADJ = 0.5V, Offsetfrom VREF, Input H to L
Hysteresis, WADJ = 0.5V, Offset from VREF, Input H to L
S4 Negative Mode Thresholds Over-Voltage, WADJ = 0.5V, Offset from VREF, Input H to L
Under-Voltage, WADJ = 0.5V, Offsetfrom VREF, Input H to L
Hysteresis, WADJ = 0.5V, Offset from VREF, Input H to L
WADJ Input Bias Current
0.25V < WADJ <1.0V
LS Threshold
ll!E._Ut = H to L
Threshold hysteresis
OC Threshold
Input= H to L
Threshold hysteresis
ARST Input Threshold
Input= L to H
Input= H to L
ON/OFF Input Threshold
Input high level
Input low level
Sense and L~c l'!.e_ut Blas Currents
Sense 1-4, Positive Mode
Input= 2.8V
Input= 2.2V
Sense 3 Negative Mode
Input= -12V
Sense 4 Negative Mode
Input= -5V
Line, and OC Inputs
Input= 2.2V
-140 -270 -540 -150 -285 -555 30 -13.52 -11.06 80 -5.63 -4.61 30
-5 1.96 65 1.9 50 2.25 0.56
0.6
-1000 -700 -700
-125 -250 -500 -125 -250 -500 50 -13.2 -10.8 120 -5.5 -4.5 50
2 100
2 100 2.5 0.625 1.74 1.35
250 -250 -500 -500 300
-110 -230 -460 -110 -230 -460 70 -12.88 -10.54 160 -5.37 -4.39 70
5 2.04 125 2.1 150 2.75 0.69 2.4
800
-300 -300 1000
mV
mV
mV
mV
mV
mV
mVN
v v
mV
v v
mV µAN
v
mV
v
mV
v v v v
nA
nA
fl.A fl.A
nA
ON/OFF Input ARST Input
Input= 2.5V Input= 0.5
150 600 nA
-2000 -700
nA
Open Collector Ou!e_uts (OV/OC Out, PG Out, PWRW Out, ON/OFF Out)
Saturation Voltage
IOUT= 10mA
Leakage current
VOUT= 20V
POR Delay
Delay
Internal Pullup Current
Threshold Low to High
0.2 0.4
v
5 fl.A
160 250 350 mS/f!F
9
fl.A
2.25
v
OFF Delay Del~ Internal Pullup current Threshold Low to High
120 185 250 msfuf
12
fl.A
2.25
v
OV FauH Delay Delay
10
20
50
f!S
5-283
PIN FUNCTIONAL DESCRIPTION
2.5V: This is the output of the precision 2.5V reference.
ARST Input: This input, with a 4:1 hysteretic threshold, is used to sequence a power system through the Auto ReStarT cycle. A delayed representation of a supply output voltage is used at this pin to provide adequate startup time for the power system, and a minimum power-off period.
Gnd: Reference point for the internal reference and all thresholds, as well as the return for the remainder of the device.
LS Input: The Line Sense input is used to monitor a voltage that varies with the input line voltage to a system. The input is compared to a precision 2.0V level and is used to activate the PWRW and PG outputs, as well as triggering the Auto Restart sequence.
OC Input: The Over-Current input can be used to respond to an inverted over-current signal. A low level~ nal at this input latches in a fault indication at the OV/OC output.
OFF DLY: This pin functions similarly to the POR DLY pin to delay the turn-on of the ON/OFF output transistor. The charging current and upper threshold are 12µA and 2.1 V.
ON/OFF Input: With a high level at this input the ON/OFF Out pin is activated after a user-programmable delay. A high level also activates the PG Out pin, and resets the OV/OC fault latch.
On/Off Out: This ~ut is an open collector output that is activated by the ON/OFF Input, or the Auto Restart circuitry. Saturation voltage on this and all the open collector outputs is rated at 1OmA of current.
OV/OC Out: In response to either an Over-Voltage or Over-Current situation this output is latched active low. There is nominal 20µs delay in the OV path to the fault latch, providing rejection to transient overshooting on the monitored voltages. The low condition is cleared when
UC1904 UC2904 UC3904
the fault latch is reset by the ON/OFF Input, or a UVLO condition on the device.
POR DLY; This pin is used, with an external capacitor, to program a Power-On-Reset delay. This delay is reset whenever there is a UV condition at one of the S1-S4 inputs, and then triggered upon the clearing of the UV condition. When reset the voltage across the capacitor is quickly discharged to near zero volts, and the PG Out pin goes active low. Once triggered the capacitor is charged by a 9µA current source. The PG Out pin remains active low until the delay capacitor voltage reaches a 2.1 V threshold.
PG Out: During any fault, under-voltage, or UVLO condition this output is low. A Power Good indication (output off) is given when all supply conditions are within defined operating limits. During power-up the PG signal is delayed by a programmable Power On Reset delay. During UVLO the output is active low as long as the input supply, VIN, is above approximately 1.0V.
PWRW Out: When a low line condition is sensed by the LS Input this output goes low. This output is disabled (off) during a UVLO condition.
51-54: These are the sense inputs for OV and UV monitoring of external voltages. All four inputs can be used to sense positive voltages with a simple divider to scale the voltage level to the 2.5V centered window. The 53 and 54 inputs can also be used to sense -12V and -5V supplies respectively with no external components. This is done with internal precision resistor dividers and two source only op-amps that are disabled when the pins are used in the positive mode.
V1N: Input supply for the UC1904. The device is operational with 4.75V to 18V on this pin.
WADJ: The WADJ input is used to program the OV and UV window thresholds. The OV-UV window is centered around the 2.5V reference and is nominally ±20% per volt on the WADJ input pin.
5-284
Over Current Signal
UC1904 UC2904 UC3904
+5V +12V -5V-12V
r----------------------------------------------------------, 5V
: Oc
OV/OC I
l:_
In ut
Over Current
Out L-.L..---~
Reaponse
Input Supply
PWM Voltage RL1 RL2
Note: Pin Numbers refer to J, N, and OW Packa es.
Supply
ON/OFF Control
UNITROOE INTEGRATED CIRCUITS 7 CONTINTENTAL BLVD. · MERRIMACK. NH 03054 TEL: 603-424-2401 · FAX 603-424-3460
5-285
n n INTEGRATED
~CIRCUITS
-UNITRODE
Load Share Controller
UC1907 UC2907 UC3907
FEATURES · Fully differential high impedance voltage sensing. ·Accurate current amplifier for precise current sharing.
· Opto coupler driving capability.
· 1.25% trimmed reference ·Master status indication ·Compatible with JIAWG 88-M?A specification
· 4.5V TO 35V operation.
DESCRIPTION The UC3907 family of Load Share Controller IC's provides all the necessary features to allow multiple independent power modules to be paralleled such that each module supplies only its proportionate share to total load current.
This sharing is accomplished by controlling each module's power stage with a command generated from a voltage feedback amplifier whose reference can be independently adjusted in response to a common share bus voltage. By monitoring the current from each module, the current share bus circuitry determines which paralleled module would normally have the highest output current and, with the designation of this unit as the master, adjusts all the other modules to increase their output current to within 2.5% of that of the master.
ABSOLUTE MAXIMUM RATINGS (NOTE 11 Supply Voltage ..........................................+35V Opto Out Voltage.......................................+35V
Opto Out Current....................................+20mA
Status Indicate Sink Current... ................ +20mA C/S Input Voltage ......................................+35V
Share Bus Voltage ......................-0.3V to +35V
Other Analog Inputs and Outputs (Zener clamped) Maximum Forced Voltage -0.3V to +1OV Maximum Forced Current.. ...........±10mA
Ground Amp Sink Current ......................+50mA Pins 1, 9, 12, 15 Sink Current ................ +20mA
The current share bus signal interconnecting all the paralleled modules is a low-impedance, noise-insensitive line which will not intertere with allowing each module to act independently should the bus become open or shorted to ground. The UC3907 controller will reside on the output side of each power module and its overall function is to supply a voltage feedback loop. The specific architecture of the power stage is unimportant. Either switching or linear designs may be utilized and the control signal may be either directly coupled or isolated though the use of an opto coupler or other isolated medium. The load sharing technique implemented with the UC3907 is compatible with the requirements of JIAWG 88-M?A specifications.
Power Dissipation at TA=25°C (Note2) ... 1OOOmW Power Dissipation at Tc=25°C (Note21 ..2000mW Storage Temperature Range.- 65°C to+ 150°C Lead Temperature (Solder 10 Seconds)+300°C
Other features of the UC3907 inelude 1.25% accurate reference: a lowloss, fixed gain current sense amplifier, a fully differential, high-impedance voltage sensing capability, and a status indicator to designate which module is pertorming as master.
NOTE 1: Pin Nos. refer to 16 Pin OIL Package
NOTE 2:Consult packaging section of databook for thermal limitations and considerations of package.
BLOCK DIAGRAM
12/92
5-286
CONNECTION DIAGRAMS
DIL-16 (TOP VIEW) J or N PACKAGE
CISOut C/S(+) CIS(-) (-)Sense Power Reb.lrn ArtificialGND
VREF Iset
Status Jnoicate Current Share Bus ADJ Out ADJ Input Comp (+)Sense Vee Opto Drive
SOIC-16 (TOP VIEW) OW PACKAGE
CISOut CIS(+) CIS(-)
(-)Sense Power Return
ArtificialGND VREF Iset
UC1907 UC2907 UC3907
Status lnoicate Current Share Bus ADJ Out ADJ Input Comp
(+)Sense Vee Opto Drive
PLCC-20 Q PACKAGE (TOP VIEW) LCC-20 L PACKAGE
1 -N/C 2-CISOut 3-CIS (+) 4-CIS(-) 5-(-) Sense 6-N/C 7 - Power Return 8 - Artificial GND
9 -VREF 10 - lset
4 2 1 2019 4 ..., 18
5
17
6
16
7
15
8
14
910111213
20 - Status Indicate 19 - Current Share Bus 18 - ADJ Out 17 - ADJ Input 16-N/C 15 - Comp 14 - (+) Sense 13-Vee 12 - Opto Drive 11 -N/C
Electrical Characteristics: Unless otherwise stated these specifications apply for TA= -55°C to +125°C for UC1907; -40°C to +85°C for UC2907;
and 0°C to +70°C for UC3907; VIN= 15V, TA=TJ.
--
PARAMETER
TEST CONDITION
MIN
TVP
MAX
UNITS
VOLTAGE AMP SECTION Input Voltage
VIA out= 1V, TA= 25°C VIA out= 1V, Over Temp
1.975
2.000
2.025
v
1.960
2.000
2.040
v
Line Regulation
Vin = 4.5V to 35V
15
mV
Load Regulation
IL Reference= O.OmA to -10mA
10
mV
Long Term Stability
TA= 125°C, 1000hrs (Note 2)
5
25
mV
Total Output Variation
Line, Load, Temp
1.960
2.040
Input Adjust Range
AIA from max high to max low
85
100
115
mV
Input Bias Current
-1
uA
Open Loop Gain
VIA out= 0.75V to 1.5V
65
dB
Unity Gain Bandwidth
TA= 25°C (Note 2)
700
kHz
Output Sink Current
(+)Sense= 2.2V, VIA out= 1V
6
15
mA
Output Source Current Vout High VoutLow
(+)Sense= 1.8V, VIA out= 1V (+)Sense= 2.2V IL= - 400ua (+)Sense= 1.8V IL= +1mA
400
600
uA
1.85
2
v
.15
.40
v
REFERENCE SECTION Output Voltage
TA= 25°C Over Operating Temp
1.970
2.000
2.030
v
1.955
2.000
2.045
v
Short Circuit Current
VREF = O.OV
-15
-30
-60
mA
GROUND AMP SECTION
Output Voltage
200
250
300
mV
Common Mode Variation
(-) Sense from O.OV to 2V
5
mV
Load Regulation
IL= O.OmA to 20mA, TA= 25°C IL= 0.0mA to 20mA, Over Temp
10
mV
15
mV
NOTE 1: Unless otherwise specified all voltages are with respect to (-)sense. Currents are positive into, negative out of the specified terminal. NOTE 2: These parameters, although quaranteed over their recommended operating conditions are not 100% tested in production.
5-287
UC1907 UC2907 UC3907
Electrical Characteristics: Unless otherwise stated these specifications apply for TA= - 55°C to+ 125°C for UC1907; - 40°C to +85°C for UC2907; and 0°C to +70°C for UC3907; VIN = 15V, TA=TJ
PARAMETER ADJUST AMP SECTION Input Offset Voltage Input Bias Current Open Loop Gain Unity Gain Bandwidth Transconductance Output Sink Current Output Source Current Vout High Vout Low Common Mode Rejection Ratio
Output gain to VIA
CURRENT AMP SECTION
TEST CONDITION
AJA out= 1.5V, Vern= O.OV
1.5V s AJA outs 2.25V TA= 25°C, Cout =1uF (Note 2) lout =-10uA to +10uA, Vout = 1.5V Vid = O.OV, AJA out= 1.5V Vid = 250mV, AJA out= 1.5V Vid = 250mV, lout= - 50uA Vid = O.OV, lout = 50uA Vern= 0.0 to 10V Vout AJA = 1.5V to 2V d (+)Sensel dAJA out
MIN
40 -2 65
1.7 55 110 2.20 0.75 70
50
TYP 50
500 3 135
200 2.70
57
MAX
UNITS
60
mV
uA
dB
Hz
4.5
ms
225
uA
350
uA
2.90
v
1.15
v
dB
64
mVN
Gain Output Voltage
Vern = O.OV, Vid = 50mV to 100mV
19.2
11TA=25°C
Ve/A(+)= Vc1A (·) = O.OV
210
Over Temp
180
Input Offset Change with Common Mode Input
Vout High
Vid= 1V
10
Vout Low
Vid =-1V IL= 1mA
Power Supply Rejection Ratio
Vin= 4.5V to 35V, Vern = O.OV
60
Slew Rate
DRIVE AMP SECTION Asel= 500 ohms to Artificial Gnd, Opto Drive= 15V
19.6
20.1
VN
250
290
mV
250
330
mV
600
µVN
14.5
v
350
450
mV
dB
0.4
V/us
Voltage Gain Iset Vout High lset Vout Low Opto out Voltage Range Zero Current Input Threshold BUFFER AMP SECTION
VIA out= 0.5V to 1V (+) sense = 2.2V (+)sense= 1.8V
2.3
2.5
2.6
VN
3.8
4.1
4.4
v
270
300
mV
4
35
v
1.55
1.65
1.75
v
Input Offset Voltage Output Off Impedance Output Source Current Common Mode Rejection Ratio Power Supply Rejection Ratio UNDER VOLTAGE LOCKOUT SECTION Start-up Threshold Threshold Hystesis
Input= 1V Input= 1V, Output= 1.5V to 2V Input= 1V, Output= 0.5V Vern = 0.3Vto 10V Vin = 4.5V to 35V
5
mV
5
10
20
kn
6
15
mA
70
dB
70
dB
3.7
4.4
v
200
mV
NOTE 1: Unless otherwise specified all voltages are with respect to (-) sense. Currents are positive into, negative out of the specified terminal. NOTE 2: These parameters, although guaranteed over their recommended operating conditions are not 100% tested in production.
5-288
UC1907 UC2907 UC3907
STATUS INDICATE SECTION Vout Low Output Leakage
i
A/A-= Current Share Bus A/A out= 1V Vout = 35V
1 1 i 1 0.2
0.5
v
0.1
5
uA
TOTAL STAND BY CURRENT Start-Up Current Operating Current
j
Vin = UVLO -0.2V Vin= 35V
j
1 j j 3
5
mA
6
10
mA
NOTE 1: Unless otherwise specified all voltages are with respect to(-) sense. Currents are positive into, negative out of the specified terminal. NOTE 2: These parameters, although guaranteed over their recommended operating conditions are not 100% tested in production.
PIN/BLOCK DESCRIPTIONS (Pin Nos are for DIL-16 package)
NEGATIVE SENSE (Pin 4) - This is a high-impedance pin intended to allow remote sensing of the system ground, bypassing any voltage drops which might appear in the power return line. This point should be considered as the "true" ground. Unless otherwise stated, all voltages are with respect to this point.
ARTIFICIAL GROUND (Pin 6) - This is a low impedance circuit ground which is exactly 250 millivolts above the (-) Sense terminal. This offset allows the Ground Buffer Arnplttier negative headroom to return all the control bias and operating currents while maintaining a high impedance at the (-) Sense input.
POWER RETURN (Pin 5) - This should be the most negative voltage available and can range from zero to 5V below the (-) Sense terminal. It should be connected as close to the power source as possible so that voltage drops across the return line and current sensing impedances lie between this terminal and the(-) Sense point.
VREF (Pin 7) - The internal Voltage Reference is a band-gap circuit set at 2.0 Volts with respect to the (-) Sense input (1.75V above the Arttticial Ground). and an accuracy of +I 1.5%. This circuit, as well as all the other chip functions, will work over a supply voltage range of 4.5V to 35V allowing operation from unregulated DC, an auxiliary voltage, or the same output voltage that it is controlling. Under voltage lockout has been included to insure proper start-up by disabling internal bias currents until the reference rises into regulation.
VOLTAGE AMPLIFIER (Pins 11, 12) - This circuit is the feedback control gain stage for the power module's output voltage regulation, and overall loop compensation will normally be applied around this amplttier. Its output will swing from slightly above the ground return to an internal clamp of 2.0 Volts. The reference trimming is performed closed loop, and measured at pin 11, (+)sense. The value is trimmed to 2V ±1.25%.
DRIVE AMPLIFIER (Pins 8, 9, 12) - This amplttier is used as an inverting buffer between the Voltage Amplttier's output and the medium used to couple the feedback signal to the power controller. It has a fixed voltage gain of 2.5 and is usually configured with a current-setting resistor to ground. This establishes a current - sinking output optimized to drive optical
couplers biased at any voltage from 4.5V to 35V, with current levels up to 20mA. The polarity of this stage is such that an increasing voltage at the Voltage Amplttier's sense input (as, for example, at tum on ) will increase the opto's current. In a nonisolated application, a voltage signal ranging from 0.25V to 4.1V may be taken from the current-setting output but it should be noted that this voltage will also increase with increasing sense voltage and an external inverter may be required to obtain the correct feedback polarity.
CURRENT AMPLIFIER (Pins 1, 2, 3) - This amplttier has dttferential sensing capability for use with an external shunt in the power return line. The common-mode range of its input will accommodate the full range between the Power Return point and Vcc-2V which will allow undefined line impedances on either side of the current shunt. The gain is internally set at 20 giving the user the ability to establish the maximum voltage drop across the current sense resistor at any value between 50 and 500 millivolts. While the bandwidth of this amplttier may be reduced with the addition of an external output capacitor to ground, in most cases this is not required as the compensation of the Adjust Amplttier will typically form the dominant pole in the adjust loop.
BUFFER AMPLIFIER (Pins 1, 15) - This amplifier is a unidirectional buffer which drives the Current Share Bus - the line which will interconnect all power modules paralleled for current sharing. Since the Buffer Arnplttier will only source current, it insures that the module with the highest output current will be the master and drive the bus with a low-impedance drive capability. All other Buffer Amplttiers will be inactive with each exhibiting a 1O kohm load impedance to ground. The Share Bus terminal is protected against both shorts to ground and accidental voltages in excess of 50 Volts.
ADJUST AMPLIFIER (Pins 13, 14, 15) - This amplttier adjusts the individual module's reference voltage to maintain equal current sharing. It is a transconductance type in order that its bandwidth may be limited, and noise kept out of the reference adjust circuitry, with a simple capacitor to ground. The function of this amplttier is to compare its own module output current to the Share Bus signal - which represents the highest output current - and force an adjust command which is capable of increasing the reference voltage as seen by the voltage amplifier by as much as 100 millivolts. This number stems from the
5-289
17.5:1 internal resistor ratio between the Adjust Amplifier's clamped output and the reference, and represents a 5% total range of adjustment - a value which should be adequate to compensate for unit-to -unit reference and external resistor tol-
erances. The Adjust Amplifier has a built-in 50 mV offset on its inverting input which will force the unit acting as the master to have a low output resulting in no change to the reference. While this 50 mV offset represents and error in current sharing, the gain of the current amplifier reduces it to only 2.5 mV across the current sense resistor. It should also be noted that when the m6dule is acting independently with no connection to
UC1907 UC2907 UC3907
the Share Bus node, or when the Share Bus node is shorted to ground, its reference voltage will be unchanged. Since only the circuit acting as a master will have a low output from the Adjust Amplifier, this signal is used to activate a flag output to identify the master should some corrective action be needed.
STATUS INDICATE (Pin 16) - This pin is an open collector output intended to indicate the unit which is acting as the master. It achieves this by sensing when the adjust amp is in its low state and pulling the status indicate pin low.
CURRENT SHARE BUS
LOAD SYSTEM DIAGRAM
POSITIVE SENSE
LOAD SHARE CONNECTION DIAGRAM
Vee
0 -20 mA ISOLATED CONTROL
MODULE LOAD CURRENT
5-290
CURRENT SHARE BUS
UC1907 UC2907 UC3907
INPUT LINE
PRIMARY SIDE PWM
CONTROL
UC3907 IN A LOAD-SHARING FEEDBACK LOOP FOR AN OFF-LINE ISOLATED SUPPLY
----------1 I
y
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD.· MERRIMACK, NH 03054 TEL 603·424·2410 ·FAX 603-424-3460
5-291
n n INTEGRATED
~CIRCUITS
-UNITRODE
Sealed Lead-Acid Battery Charger
UC2906 UC3906
FEATURES Optimum Control for Maximum Battery Capacity and Life
Internal State Logic Provides Three Charge States
Precision Reference Tracks Battery Requirements Over Temperature
Controls Both Voltage and Current at Charger Output
DESCRIPTION
The UC2906 series of battery charger controllers contains all of the necessary circuitry to optimally control the charge and hold cycle for sealed lead-acid batteries. These integrated circuits monitor and control both the output voltage and current of the charger through three separate charge states; a high current bulk-charge state, a controlled over-charge, and a precision float-charge, or standby, state.
Optimum charging conditions are maintained over an extended temperature range with an internal reference that tracks the nominal temperature characteristics of the lead-acid cell. A typical standby supply current requirement of only 1.6mA allows these ICs to predictably monitor ambient temperatures.
System Interface Functions
Typical Standby Supply Current of only 1.6mA
Separate voltage loop and current limit amplifiers regulate the output voltage and current levels in the charger by controlling the onboard driver. The driver will supply up to 25mA of base drive to an external pass device. Voltage and current sense comparators are used to sense the battery condition and respond with logic inputs to the charge state logic. A charge enable comparator with a trickle bias output can be used to implement a low current turn-on mode of the charger, preventing high current charging during abnormal conditions such as a shorted battery cell.
BLOCK DIAGRAM
Other features include a supply under-voltage sense circuit with a logic output to indicate when input power is present. In addition the over-charge state of the charger can be externally monitored and terminated using the over-charge indicate output and over-charge terminate input.
SINK SOURCE COMPENSATION
+VIN
VOLTAGE SENSE
C/L
C/S OUT
TRICKLE BIAS
CHARGE ENABLE
POWER INDICATE
OVER-CHARGE TERMINATE
6/93
5-292
STATE LEVEL CONTROL
OVER-CHARGE INDICATE
UC2906
ABSOLUTE MAXIMUM RATINGS (Note 1)
CONNECTION DIAGRAMS
UC3906
Supply Voltage (+VIN) ........................... 40V Open Collector Output Voltages................... 40V Amplifier and Comparator Input Voltages ... -0.3V to +40V Over-Charge Terminate Input Voltage ...... -0.3V to +40V Current Sense Amplifier Output Current . . . . . . . . . . 40mA Other Open Collector Output Currents. . . . . . . . . . . . . 5mA Trickle Bias Output Current .................... -40mA Driver Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40mA Power Dissipation at TA= 25°C{Note 2) ........ 1OOOmW
PLCC-20, LCC-20 (TOPVIEW) Q, L Packages
PACKAGE PIN FUNCTION
FUNCTION
PIN
N/C
1
C/S OUT
2
C/S-
3
Power Dissipation at Tc= 25°C (Note 2) ........ 2000mW Operating Junction Temperature ........ -55°C to +150°C
La 2 1 2019
C/S+ C/L
4 5
Storage Temperature ................. -65°C to +150°C . 4
18
N/C
6
Lead Temperature (Soldering, 10 Seconds) ....... 300°C
5
Note 1: Voltages are referenced to ground (Pin 6). Currents
17
+VIN
7
are positive into, negative out of, the specified terminals.
6
16
GROUND
8
Note 2: Consult Packaging section ofDatabook for thermal
7
15
POWER INDICATE
9
limitations and considerations ofpackages.
8
14
OVERCHARGE
10
9 10 11 12 13
TERMINATE
DIL-16, SOIC-16 (TOP VIEW)
~~
N/C
11
J or N Package, DW Package
OVERCHARGE
12
INDICATE
C/S OUT 1
DRIVER SINK
STATE LEVEL
13
1 DRIVER SOURCE
CONTROL
C/S +
4 COMPENSATION
TRICKLE BIAS
14
CHARGE ENABLE
15
C/L
VOLTAGE SENSE
N/C
16
+VIN
1 CHARGE ENABLE
VOLTAGE SENSE
17
GROUND 6
~
iNiiiCffi 7
OVER-CHARGE TERMINATE
11 TRICKLE BIAS
1
STATE LEVEL CONTROL
9
OVER-CHARGE INDICATE
COMPENSATION
18
DRIVER SOURCE
19
DRIVER SINK
20
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA= -40°C to +70°C for the
UC2906 and 0°Cto +70°Cforthe UC3906, +VIN= 10V, TA= TJ.
PARAMETER
TEST CONDITIONS
Input Supply
Supply Current
+VIN=10V
+VIN=40V
Supply Under-Volta_!l_e Threshold +VIN= Low to High
Su~y Under-Volta_!l_e Hysteresis
Internal Reference {VREF)
Voltage Level (Note 2)
Measured as Regulating Level at Pin 13 w/ Driver Current = 1mA, TJ =25°C
Line RElll_ulation
+VIN = 5 to 40V
Temperature Coefficient
Voltage Ampllfler
Input Bias Current
Total Input Bias at Regulating Level
Maximum Output Current
Source
Sink
Open Loop Gain
Driver current = 1mA
Output Voltage Swing
Volts above GND or below +VIN
UC2906 MIN TYP MAX
1.6 2.5 1.8 2.7 4.2 4.5 4.8 0.20 0.30
2.275 2.3 2.325
3
8
-3.9
-0.5 -0.2
-45 -30 -15
30
60
90
50
65
0.2
UC3906
UNITS
MIN TYP MAX
1.6 2.5 mA
1.8 2.7 mA
4.2 4.5 4.8
v
0.20 0.30 v
2.270 2.3 2.330 v
3
8
mV
-3.9
mvrc
-0.5 -0.2
!IA
-45 -30 -15 !IA
30 60 90 !IA
50
65
dB
0.2
v
Note 2. The reference voltage will change as a function ofpower dissipation on the die according to the temperature coefficient of the reference and the thermal resistance, junction-to-ambient.
5-293
UC2906 UC3906
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA= -40°C to +70°C for the
UC2906 and 0°C to +70°C for the UC3906, +VIN= 10V, TA= TJ.
PARAMETER
TEST CONDITIONS
Driver
Minimum Supply to Source Differential
Pin 16 =+VIN, lo= 10mA
Maximum Output Current
Pin 16 to Pin 15 = 2V
Saturation Voltage
Current Limit Amplifier
Input Bias Current
Threshold Voltage
Offset below +VIN
Threshold Supply Sensitivity
+VIN = 5 to 40V
Voltage Sense Comparator
Threshold Voltage
As a function of VREF' L1 = RESET
As a function of VREF' L1 = SET
Input Bias Current
Total Input Bias at Thresholds
Current Sense Comparator
Input Bias Current
Input Offset Current
Input Offset Voltage
Referenced to Pin 2, lour= 1mA
Offset Supply Sensitivity
+VIN = 5 to 40V
Offset Com man Mode Sensitivity CMV = 2V to +VIN
Maximum Output Current
Vour =2V
Output Saturation Voltage
lour= 10mA
Enable Comparator
Threshold Voltage
As a function of VREF
Input Bias Current
Trickle Bias Maximum Output Current
Vour =+VIN -3V
Trickle Bias Maximum Output Voltage
Volts below +VIN, lour= 10mA
Trickle Bias Reverse Hold-Off Voltage
+VIN= OV, lour= -10µA
Over-Charge Terminate Input
Threshold Voltage
Internal Pull-Up Current
At Threshold
Open Collector Outputs (Pins 7, 9, and 10)
Maximum Output Current
Vour= 2V
Saturation Voltage
lour= 1.6mA
lour= 50µA
Leakage Current
Vour= 40V
UC2906
UC3906
UNITS
MIN TYP MAX MIN TVP MAX
2.0 2.2
2.0 2.2
v
25 40
25
40
mA
0.2 0.45
v 0.2 0.45
0.2 1.0
0.2 1.0 µA
225 250 275 225 250 275 mV
0.03 0.25
0.03 0.25 %N
0.945 0.95 0.955 0.945 0.95 0.955 VN
0.895 0.90 0.905 0.895 0.90 0.905 VN
-0.5 -0.2
-0.5 -0.2
µA
0.1 0.5
0.1 0.5 µA
0.01 0.2
0.01 0.2 µA
20
25
30
20
25
30 mV
0.05 0.35
0.05 0.35 %N
0.05 0.35
0.05 0.35 %N
25 40
25
40
mA
0.2 0.45
v 0.2 0.45
0.99 1.0 1.01 0.99 1.0 1.01 VN
-0.5 -0.2
-0.5 -0.2
µA
25 40
25
40
mA
2.0 2.6
2.0 2.6
v
6.3 7.0
6.3 7.0
v
0.7
1.0 1.3
0.7
1.0
1.3
v
10
10
µA
2.5
5
2.5
5
mA
0.25 0.45
v 0.25 0.45
0.03 0.05
v 0.03 0.05
1
3
1
3
µA
5-294
Internal Reference Temperature Characteristic and Tolerance
VREF GUARANTEED TOL. OVER TEMPERATURE
1o·c 2.so >-""<+-----+----< uc29os -4o·c TO
UC3906 o·c TO 70° c
I
UC2906 UC3906
the charger a low current turn on mode. The output current of the charger is limited to a low-level until the battery reaches a specified voltage, preventing a high current charging if a battery cell is shorted. Figure 2 shows the state diagram of the charger. Upon turn on the UV sense circuitry puts the charger in state 1, the high rate bulkcharge state. In this state, once the enable threshold has been exceeded, the charger will supply a peak current that is determined by the 250mV offset in the C/L amplifier and the sensing resistor Rs.
2.00 ~~~~--~~~~--~ ~~~~o~~g~:i!~~ TEMPERATURE - (°C)
OPERATION AND APPLICATION INFORMATION
Dual Level Float Charger Operations The UC2906 is shown configured as a dual level float charger in Figure 1. All high currents are handled by the external PNP pass transistor with the driver supplying base drive to this device. This scheme uses the TRICKLE BIAS output and the charge enable comparator to give
To guarantee full re-charge of the battery, the charger's voltage loop has an elevated regulating level, Voe, during state 1 and state 2. When the battery voltage reaches 95% of Voe, the charger enters the over-charge state, state 2. The charger stays in this state until the OVERCHARGE TERMINATE pin goes high. In Figure 1, the charger uses the current sense amplifier to generate this signal by sensing when the charge current has tapered to a specified level, IOCT. Alternatively the over-charge could have been controlled by an external source, such as a timer, by using the OVER-CHARGE INDICATE signal at Pin 9. If a load is applied to the battery and begins to discharge it, the charger will contribute its full output to the load. If the battery drops 10% below the float level, the charger will reset itself to state 1. When the load is removed a full charge cycle will follow. A graphical representation of a charge, and discharge, cycle of the dual lever float charger is shown in Figure 3.
Rs
+ INPUT SUPPLY
j_
r---- 1 UC2906 --------
I +VIN
I I
VOLTAGE AMP
SENSE COMP .
.9/.95 VREF
INPUT POWER MONITOR
STATE
CHARGE
LEVEL
ST A TE LOGIC1---~
I I I I1._ _ _ _ _ _ _ _ _ _ _ _ _ _ _
QC
I
oc
TERM.
IND.
-
I I
I
8 ______________ J
Figure 1. The UC2906 in a Dual Level Float Charger
5-295
UC2906 UC3906
OPERATION AND APPLICATION INFORMATION (continued)
--Voe
~V12
--VF --V31
- }vr
IMAX
STATE t BULK CHARGE
STATE ~ OVER CHARGE STATE 3: FLOAT CHARGE
CHARGER OUTPUT CURRENT
Design procedure 1.) Pick divider current, lo. Recommended value is
50µA to 1OOµA. 2.) Re= 2.3VI lo 3.) RA+ RB= RsuM=( VF-2.3VY/o 4.) Ro=2.3VRsuw(Voc- VF) 5.) RA= (RsuM+ Rx) (1 -2.3V/V7)
where: Rx= RcRol(Rc+ Ro) 6.) Ra= RsuM - RA 7.) Rs=0.25VllMAX 8.) RT= ( VIN - VT- 2.5V)llT
Note:V12 - 0.95Voc VJ1 =0.90VF
IMAX /OCT·W
For further design and application information see UICC Application Note U-104
Figure 2. State Diagram and Design Equations for the Dual Level Float Charger
INPUT SUPPLY VOLTAGE
CHARGE VOLTAGE
_J____________ _
==--T"""--,.~---'v_o_c-'--__,.___ VF
D E
t -V31
ABt-_VT_________F _G _
..--------,-- IMAX
CHARGE CURRENT
-IT
IOCT-
STATE LEVEL OUTPUT
oc
INDICATE OUTPUT
OFF ON
=1~---~-l_
____ OFF - - - - ___._
__._ - - - -
ON
oc
TERMINATE INPUT
(C/S OUT)
1, STATE 1 ,1, STATE 2 .!~TATE ~1. STATE 1
Explanatlon: Dual Level Float Charger
A. Input power turns on, battery charges at trickle current rate. B. Battery voltage reaches VT enabling the driver and turning
off the trickle bias output, battery charges at IMAX rate. C. Transition voltage V12 is reached and the charger indicates
that it is now in the over-charge state, state 2.
D. Battery voltage approaches the over-charge level voe and
the charge current begins to taper. E. Charge current tapers to IOCT. The current sense amplifier
output, in this case tied to the OC TERMINATE input, goes high. The charger changes to the float state and holds the battery voltage at VF. F. Here a load (IMAX) begins to discharge the battery. G. The load discharges the battery such that the battery voltage falls below V31. The charger is now in state 1, again.
Figure 3. Typical Charge Cycle: UC2906 Dual Level Float Charger
5-296
UC2906 UC3906
OPERATION AND APPLICATION INFORMATION (continued)
Compensated Reference Matches Battery Requirements at the current sense output to prevent excessive power
When the charger is in the float state, the battery will be dissipation on the UC2906.
maintained at a precise float voltage, VF. The accuracy of this float state will maximize the standby life Of the battery while the bulk-charge and over-charge states guarantee rapid and full re-charge. All of the voltage thresholds on the UC2906 are derived from the internal reference. This reference has a temperature coefficient that tracks the temperature characteristic Of the optimum-charge and hold levels for sealed lead-acid cells. This further guarantees that proper charging occurs, even at temperature extremes.
Dual Step Current Charger Operation
Figures 4, 5 and 6 Illustrate the UC2906's use in a different charging scheme. The dual step current charger is useful when a large string of series cells must be charged. The holding-charge state maintains a slightly elevated voltage across the batteries with the holding current, 1H. This will tend to guarantee equal charge distribution between the cells. The bulk-charge state is similar to that Of the float charger with the exception that when V12 is reached, no over-charge state occurs since Pin 8 is tied high at all times. The current sense amplifier is used to regulate the holding current. In some applications a series resistor, or external buffering transistor, may be required
A PNP Pass Device Reduces Minimum Input to Output Differential
The configuration of the driver on the UC2906 allows a good bit of flexibility when interfacing to an external pass transistor. The two chargers shown in Figures 1 and 4 both use PNP pass devices, although an NPN device
driven from the source output of the UC2906 driver can
also be used. In situations where the charger must operate with low input to output differentials the PNP pass device should be configured as shown in Figure 4. The PNP can be operated in a saturated mode with only the series diode and sense resistor adding to the minimum differential. The series diode, 01, in many applications, can be eliminated. This diode prevents any discharging of the battery, except through the sensing divider, when the charger is attached to the battery with no input supply voltage. If discharging under this condition must be kept to an absolute minimum, the sense divider can be referenced to the POWER INDICATE pin, Pin 7, instead of ground. In this manner the open collector off state of Pin 7 will prevent the divider resistors from discharging the battery when the input supply is removed.
+ INPUT SUPPLY
RsM
,! .U.C.2-90-8----------
I +VIN I I
+ BATTERY (VB) Re
CHARGE STATE LOGIC:i---~
I
I
1--------------- I
I
=
I
oc
I
TE_R_M.____________ JII
+VIN
Figure 4. The UC2906 in a Dual Step Current Charger
5-297
OPERATION AND APPLICATION INFORMATION (continued)
UC2906 UC3906
- Vtl
IMAX + IH
---- -- -- --
- - V12
STATE 2
IH STATE 1
m) = 1.) V12 .95 YREF (1+ ~~ +
2.) VF = VREF (1+~)
3.) V21 · .9 VF
4.) IMAX· ~~ 5.) IH = ·~2!V
STATE 1: BULK CHARGE STATE 2: HOLDING CHARGE
CHARGER OUTPUT CURRENT
Figure 5. State Diagram and Design Equations for the Dual Step Current Charger
INPUT SUPPLY
_L __________ _
VOLTAGE
CHARGE VOLTAGE
CHARGE CURRENT
l I'~+'"I _ lA_ - - - - - - - - - -
- - - - - - - --IH - - -
----'--- STATE
LEVEL
~:=-i-'----~-
~STATE 1+STATE 2fsTATE 1
Explanation: Dual Step Current Charger
A. Input power turns on, battery charges at a rate of IH + IMAX. B. Battery voltage reaches V12 and the voltage loop switches
to the lower level VF. The battery is now fed with the holding current IH.
C. An external load starts to discharge the battery.
D. When VF is reached the charger will supply the full current IMAX + IH.
E. The discharge continues and the battery voltage reaches V21 causing the charger to switch back to state 1.
Figure 6. Typical Charge Cycle: UC2906 Dual Step Current Charger
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5-298
n n L'.=::J INTEGRATED CIRCUITS
-UNITRODE
Primary Side Controller
UC7501/7503 ADVANCED
INFORMATION
FEATURES
· Optimized for Offline Operation · Toggle Option for45% (UC7501)
· 90% Duty Cycle Limit (UC7503)
· Over-Current Protection via
Frequency Reduction
· Low Standby Current for Current-Feed Startup
· Current-Mode or Voltage-Mode
Control
· Built-in User-Adjustable Slope Compensation
· Functionally Integrated &
Simplified 5-Pin Design
· Miniature Surface Mount U-PAK-5 (1 Watt) Package
BLOCK DIAGRAM
DESCRIPTION
The UC7501/7503 is a primary side controller for switching mode power supplies. It is suitable for both voltage-mode and current-mode control and has advanced features not available in controllers with an even higher pin count. The key to full functionality in a 5-pin package is that the current signal and the error signal are added together and fed into the feedback pin. A sawtooth current flowing out of the feedback pin provides slope compensation, in proportion to the resistance terminating that pin. If the sum of the current signal and error signal exceeds the Over Current Detector threshold, indicating that the Current Control Detector loses control of the switch current, the charging current of the timing capacitor will be reduced to 25% for the remainder of the period. The reduced charge current leads up to a four-fold reduction in switching frequency, effectively preventing short-circuit current runaway.
ABSOLUTE MAXIMUM RATINGS
Input Voltage VccMAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17V Power Dissipation
UC7501/7503 U&D (Note 1) ................................... 1000mW UC7501/7503J (Note 2) ....................................... 825mW Junction Temperature ............................................ 150°C Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55to+150°C Lead Soldering Temp. (1 Osec.) .................................... 300°C Operating Temperature Range
o (Commercial) ............................................. to +70°C
(Industrial). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 to +85°C (Military) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55to+125°C Note 1: Power dissipation must be derated at the rate of 8 mWl°C for operation at
TA= 25"C and above. Note 2: Power dissipation must be derated at the rate of 6.6 mw1°c for operation at
TA = 25"C and above.
~
-
U-PAK-5 J or N Package
DIL-8 (TOP VIEW) J or N Package
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DRVO·vcc
e GND 2
5 GND
CT 3
4 FB
DRVo·Vcc PWR GND ·
1 NC
GND ·
· NC
CT 4
5 FB
DAV
Note: 8-P/n Power SOJC also available-Designated "DP" suffix.
5-299
n n INTEGRATED
~CIRCUITS
-uNITROOE
Error Signal Isolator
UC7502 ADVANCED INFORMATION
FEATURES Eliminates Opto-Coupler in Feedback Design Replaces UC431 and Eliminates Parasitic Zero Pulse Transformer Driver Same Transformer for Any Output Voltage Peak Current Controlled Automatic Volt-Second Balancing Self-Running Oscillator Hi-Performance Op Amp & Bandgap Reference Functionally Integrated & Simplified 5-pin Design Miniature Surface Mount U-PAK-5 (1 Watt) Package
DESCRIPTION
The UC7502 is designed to monitor the output voltage of a power supply, generate an error signal, and transmit the error signal through an isolation barrier using a small pulse transformer. In conjunction with the pulse transformer, it replaces the UC431/optocoupler combination and eliminates the undesirable zero created by that combination. The transformer is driven with pulse amplitude modulation in a free-running oscillator configuration. The period of oscillation is proportional to the pulse transformer inductance. The voltage pulse magnitude is internally limited so that the pulse transformer design need not be changed for various output voltages.
ABSOLUTE MAXIMUM RATINGS
Input Voltage VccMAX................................... 17V Power Dissipation (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W Junction Temperature ................................. 150°C Storage Tern perature Range . . . . . . . . . . . . . . . . . . . . . -55 to +150°C Lead Soldering Temp. (10 sec.) .......................... 300°C Operating Temperature Range
(Commercial) ................................... Oto + 70°C (Industrial) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 to +85°C (Military). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 to +125·c Note 1: Power dissipation must be derated atthe rate ofB mW/°C for
operation at TA= 25"C and above.
BLOCK DIAGRAM
U-PAK-5 J or N Package
DIL-8 (TOP VIEW) J or N Package
COMP NV
D R V 08 Vcc GND2. SGND
DRVoe Vee
GND 2
7 NC
NC 3
e NC
INV 3
4 COMP
INV ·
s COMP
6/93
UNITRODE INTEGRATEO CIRCUITS 7 CONTINENTAL BLVD.· t.EARIMACK, NH 03054 TEL (603) 424-2410 ·FAX (603) 424·3460
Note: 8-Pln Power SOIC also available-Designated "DP" suffix. 5-300
n n·NTEGRATED
~CIRCUITS
-UNITRODE
Precision Adjustable Shunt Regulator
UC19431 UC29431 UC39431
PRELIMINARY
FEATURES · Multiple On-Chip Programmable Reference
Voltages
· 0.4% Initial Accuracy
0.7%0verall Reference Tolerance
2.2V to 36.0V Operating Supply Voltage and User Programmable Reference
· 36.0V Operating Supply Voltage
· Reference Accuracy Maintained For Entire Range of Supply Voltage
Superior Accuracy and Easier Compensation for Opto-lsolator Application
· Improved Architecture Provides a Known
Linear Transconductance with a + 5% Typical
Tolerance
ABSOLUTE MAXIMUM RATINGS
Supply Voltage: V ·.................................................36V Regulated Oulp'..l!: V ..............................................36V
Internal Resistors: R1. R2, R3 ............................... 13V
E/A Input: SENSE .................................................... 6V E/A Compensation: COMP ...................................... 6V Output Sink Current: I ....................................... 140mA Power Dissapation at TA:;; 25°C (DIL-8) ................. 1W Derate 8mW/°C for TA> 25°C Storage Temperature Range ............. -65°C to +150°C Lead Temperature (Soldering, 1O Seconds) .... +300°C Note: All voltages are with respect to GND
All currents are positive into the specified terminal
DESCRIPTION
The UC19431 is an adjustable shunt voltage regulator with 1OOmA sink capability. The architecture, comprised of an error amplifier and transconductance amplifier, gives the user separate control of the small signal error voltage frequency response along with a fixed linear transconductance. A minimum 3MHz gain bandwidth product for both the error and transconductance amplifiers assures fast response. In addition to external programming, the IC has three internal resistors that can be connected in six different configurations to provide regulated voltages of 2.82V, 3.12V, 5.1V, 7.8V, 10.42V, and 12.24V. A sister device (UC19432) provides access to the non-inverting error ampilifer input and reference, while eliminating the three internal resistors.
CONNECTION DIAGRAMS
DIL-8 (TOP VIEW) N or J Package
SOIC-8 (TOP VIEW) D Package
ISET
GND
SENSE Vee REF EA+
ISET
GND
SENSE REF
BLOCK DIAGRAM
5/93
20k
o.sv
REF 1.3V 4k
5.1k 2.BSk
5-301
5.1!2
UC19431 UC29431 UC39431
PIN DESCRIPTIONS COLL: The collector of the output transistor with a maximum voltage of 36V. This pin is the output of the transconductance amplifier. The overall open loop voltage gain of the transconductance amplifier is gm·RL, where gm is designed to be -140mS ±10% and RL represents the output load.
COMP: The output of the error amplifier and the input to the transconductance amplifier. This pin is available to compensate the high frquency gain of the error amplifier. It is internally voltage limited to approximately 2.0V.
GND: The reference and powergroundforthe device. The power ground of the output transistor is isolated on the chip from the substrate ground used to bias the remainder of the device.
SENSE: The inverting terminal of the error amplifier used as both the voltage sense input to the error amplifier and its other compensation point. The error amplifier uses the SENSE input to compare against the 1.3V on-chip reference.\
The SENSE pin is also used as the under-voltage lock out (UVLO). It is intended to keep the chip from operating until the internal reference is properly biased. The threshold is approximately 1V. It is important that once the UVLO is released, the error amplifier can drive the transconductance amplifier to stabilize the loop. If a capacitor is connected between the SENSE and COMP pins to create a pole, it will limit the slew rate of the error amplifier. Additional load current or a slower power turn-on than the error amplifier slew rate will be necessary to assure start-up. To increase the bandwidth and ensure start-up at low load current, it is recommended to create a zero along with the pole as shown in the shunt regulator application. The error amplifier must slew 2.0V to drive the transconductance amplifier initially on.
R1, R2, R3: Connection points to the three internal resistors.
VCC: The power connection for the device. The minimum to maximum operating voltage is 2.2V to 36.0V. The quiescent current is typically O.SOmA.
Electrical Characteristics: Unless otherwise stated, these specttications apply for TA= -55°C to+125°C and Pin 1 Output = 2.4V to 36.0V for the UC19431, TA= -25°C to +85°C and Pin 1 Output= 2.3V to 36.0V for the UC29431, and TA= 0°C to +70°C
and Pin 1 Output= 2.3V to 36.0V for the UC39431, Vee= 15V, leoLL = 1OmA, TA= TJ.
PARAMETER Reference Voltage Tolerance Reference Temperature Tolerance Reference Line Regulation Reference Load Regulation Sense Input Current Minimum Operating Current Collector Current Limit Collector Saturation Transconductance (gm) 5.1 V Reference 12.24V Reference Error Amplifier AvoL Error Amplifier GBW Transconductance Amplifier GBW
TEST CONDITIONS TA= 25°C VcoLL= 5.0V Vee= 2.2V to 36.0V, VcoLL = 5V leoLL = 1OmA to 50mA, VeoLL= 5V Vee= 2.2V to 36.0V Vee= 36.0V, VeoLL= 5V VeoLL =Vee= 36.0V, Ref= 1.35V Vee= 2.2V to 36.0V, lcoLL = 20mA Vee= 2.2V to 36.0V, VeoLL= 3V, lcoLL= 20mA Internal Divider Internal Divider
MIN 1295 1291
0.2
0.7 -153 5.05 12.12 60 3.0
TYP 1300 1300 1.2 1.2 0.5 0.50 130 1.1 -140 5.10 12.24
90 5 3
MAX 1305 1309 10.0 10.0 uA 0.80 140 1.5 -127 5.15 12.36
UNITS mV mV mV mV
mA mA
v
ms
v v
dB MHz MHz
Note: The internal divider can be configured to give six unique references. These references are 2.82V, 3.12V, 5.1 V, 7.BV, 10.42V,
12.24V.
5-302
1k 15V INPUT
6.8nF
UC19431 UC29431 UC39431
5.1V OUTPUT
FIGURE 1: Typical 5.1 V Shunt Regulator Application
MAG-AMP CONTROLLER APPLICATION
The 0.4% initial reference makes the UC19431 ideal as a programmable shunt regulator. By adding two external resistors, the on-chip 1.3V reference can be gained to any voltage between 2.2V (2.4V for the UC19431) and 36.0V. The input bias current is typically maintained at 0.2µA for the
output voltage range. Since the non-inverting error amplifier input is not available, a 5.1 k non-inverting input impedance is added to the input of the error amplifier. This allows the user to choose the SENSE pin input impedance to cancel the minimal offset voltage caused by the input bias current.
RESISTOR DIVIDER CONNECTION TABLE FOR SHUNT AND OPTO APPLICATIONS To obtain the shunt regulated or opto-coupler sensed voltage specified in the left column, connect the internal resistors (R1, R2, R3) as indicated.
REGULATED VOLTAGE
CONNECT R1 TO: CONNECT R2 TO: CONNECT R3 TO:
2.82V 3.12V 5.1V 7.8V 10.42V 12.24V
SENSE (pin 7) open
COLL (pin 1 COLL (pin 1) COLL (pin 1) COLL (pin 1)
COLL (pin 1) COLL (pin 1) SENSE (pin 7) SENSE (pin 7) SENSE (pin 7)
open
SENSE (pin 7) SENSE (pin 7)
open GND (pin8) SENSE (pin 7) SENSE (pin 7)
5-303
UC19431 UC29431 UC39431
FREQUENCY COMPENSATION
The UC19431 shunt regulator is designed with two independant gain stages. The error amplifier provides 90dB of gain with a typical gain bandwidth product of 5 MHz. The error amplifier provides sufficient gain in order for the sense voltage to be accurately compared to the 1.3V on-chip reference. Complete control of the frequency response of the error amplifier is accomplished with the COMP pin. By putting negative feedback across the error amplifier, either a pole or a pole-zero can be added.
The second gain stage is the transconductance (gm) amplifier. The gm amplifier is designed with a known linear 140mS of transconductance. The voltage gain is consequently gm·Ro, where Ro is the output impedance at the
collector pin. The frequency response of the transconductance amplifier is controlled with the COLL pin. The gain bandwidth product of the gm amplifier is typically 3MHz. A pole or pole-zero can be added to this stage by connecting a capacitor or a series capacitor and resistor between COLL and GND.
The compensation of a control loop containing the UC19431 is made easier due to the independant compensation capability of the error amplifier and gm amplifier. As shown in the applications information, a pole-zero is created with a series resistor and capacitor between SENSE and COMP. The pole created is dominant.while the zero is used to increase the bandwidth and cancel the effects of the pole created by the capacitor between the COLL and GND pins.
21k 40.2K
Vee
2k
FIGURE 2: 15.0V Shunt Regulator Application
OPTOCOUPLER APPLICATION
The two amplifier circuit architecture employed in the UC 19431 is most advantageous for the optocoupler application. The error amplifier provides a fixed open loop gain that is available to apply flexible loop compensation of either poles or zeroes. A fixed transconductance amplifier pro-
vides a linear current source compared to the typical transistor's exponential output characteristics. It also eliminates the traditional optocoupler's CTR variations with power supply and voltage, and the need to suffer the additional voltage drop of a series resistor.
5-304
I
7
02 01
Lo
1 co
-=-
UC19431 UC29431 UC39431
+Vo
R4
03
04
R1
R2
FIGURE 3: Mag Amp Controller Application
MAG-AMP CONTROLLER APPLICATION The UC19431 makes an excellent controller for mag amp regulated outputs. Workingfromeitherasquarewavedrive or from a PWM signal controlled by another output, a
saturable reactor provides highly efficient control, requiring only a reset current which can be generated from its own output.
1.310
1.305
~ wIL 1.300 >IC 1.295
1.290
l---1
r--
-50 -25 0
25 50 75 100 125
TEMPERATURE (C0 )
160
+
-
-......~ ..-.
----
PHASE
r
-
-
-
r
-
-
-
r
-
-
-
r
-
-
r
-
-
+
1
8
0
~
f:=:":~4N===1~~~--+--l----:l----l-4 120 +---+--+"r--+--+--+--t---t-----+135
m~ 80
I:::,,.
~l
90
h :cc 40 +----+---+----+--""'-+-:t::::_:._. __,__--+--~.,.._--+45
CJ
m
w
IC
eCw J .
w
!:::::,, [_l
I/)
i"f"
-40 +---+---+---+----tl-+----+---+----+--y---+- -45
10' 10 I
10' T10· 10· 10· 10 1 10·
FREQUENCY (HZ)
FIGURE 4: Internal 1.3V REF vs. Temperature
FIGURE 5: Error Amp Voltage Gain and Phase vs. Frequency
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7 CONTINENTAL BLVD.· MERRIMACK, NH 03054 TEL (603) 424·2410 ·FAX (603) 424-3460
5-305
n nINTEBAATEO
~CIRCUITS
-UNITRODE
Precision Analog Controller
UC19432 UC29432 UC39432 PRELIMINARY
FEATURES
· Programmable Transconductance for Optimum Current Drive
· Accessible 1.3V Precision Reference
· Both Error Amplifier Inputs Available
· 0.7% Overall Reference Tolerance
· 0.4% Initial Accuracy
· 2.2V to 36.0V Operating Supply Voltage and User Programmable Reference
· Reference Accuracy Maintained for Entire Range of Supply Voltage
· Superior Accuracy and Easier Compensation for Opto-lsolator Application
· Low Quiescent Current (0.50mA Typ)
ABSOLUTE MAXIMUM RATINGS
Supply Voltage: Vee ............................................ 36V Regulated Output: VcoLL ......................................................36V E/A Input: SENSE, E/A+ ........................................ 6V E/A Compensation: COMP .................................... 6V Reference Output: REF ......................................... 6V Output Sink Current: lcoLL .............................. 140mA Output Source Current: lsET ...................................... -140mA Power Dissapation at TA :o; 25°C (DIL-8) ............... 1W
Derate 8mW/°C for TA> 25°C Storage Temperature Range ........... -65°C to + 150°C Lead Temperature (Soldering, 1OSeconds) .. +300°C Notes: All voltages are with respect to GND
All currents are positive into the specified terminal
BLOCK DIAGRAM
DESCRIPTION
The UC19432 is an adjustable precision analog controller with 1OOmA sink capability if the lsEr pin is grounded. A resistor between lsET and ground will modify the transconductance while decreasing the maximum current sink. This will add further control in the opto-coupler configuration. The trimmed precision reference along with the non-inverting e.rror amplifier inputs are accessible for custom configurations. A sister device, the UC19431 adjustable shunt regulator, has an on-board resistor network providing six pre-programmed voltage levels, as well as external programming capability.
CONNECTION DIAGRAMS
DIL-8 (TOP VIEW) J or N Package
CGOMOP LLOB lsET
2
7 GND
SOIC-8 (TOP VIEW)
D Package
CCOMOP 2LL[]B7
lsET GND
Vee 3
6 SENSE V;;e 3
6 SENSE
EA+ 4
5 REF
EA+ 4
5 REF
REF
Vee COLL
EA+ SENSE COMP
GND
5.SQ
5/93
5-306
UC19432 UC29432 UC39432
PIN DESCRIPTIONS
COLL: The collector of the output transistor with a maximum voltage of 36V. This pin is the output of the transconductance amplifier. The overall open loop voltage gain of the transconductance amplifier is gm·RL, where gm is designed to be -140mS ±10% and RL represents the output load.
COMP: The output of the error amplifier and the input to the transconductance amplifier. This pin is available to compensate the high frquency gain of the error amplifier. It is internally voltage limited to approximately 2.0V.
GND: The reference and power ground for the device. The power ground of the output transistor is isolated on the chip from the substrate ground used to bias the remainder of the device.
SENSE: The inverting terminal of the error amplifier used as both the voltage sense input to the error amplifier and its other compensation point. The error amplifier uses the SENSE input to compare against the 1.3V on-chip reference.
The SENSE pin is also used as the under-voltage lock out (UVLO). It is intended to keep the chip from operating until the internal reference is properly biased. The threshold is approximately 1V. It is important that once the UVLO is released, the error amplifier can drive the transconductance
amplifier to stabilize the loop. If a capacitor is connected between the SENSE and COMP pins to create a pole, it will limit the slew rate of the error amplifier. Additional load current or a slower power turn-on than the error amplifier slew rate will be necessary to assure start-up. To increase the bandwidth and ensure start-up at low load current, it is recommended to create a zero along with the pole as shown in the shunt regulator application. The error amplifier must slew 2.0V to drive the transconductance amplifier initially on.
Vee: The power connection for the device. The minimum to maximum operating voltage is 2.2V to 36.0V. The quiescent current is typically 0.50mA.
lsEr: The current set pin for the transconductance amplifier. The transconductance will be -140mS as specified in the electrical table if this pin is grounded. If a resistance RL is added to the lsET pin, the resulting new transconductance is calculated using the following equation: gm= -0. 714/ (5.1 + RL). The maximum current will be approximately IMAX= 0.6VI (5.1 + RL).
REF: The output of the trimmed precision reference. It can source or sink 10 mA and still maintain the 1% temperature specification.
E/A+: The non-inverting input to the error amplifier.
ELECTRICAL CHARACTERISTCS: Unless otherwise stated, these specifications apply for TA= -55°C to+125°C and Pin 1
Output= 2.4V to 36.0V for the UC19432, TA= -25°C to +85°C and Pin 1 Output= 2.3V to 36.0V for the UC29432, and TA= 0°C to +70°C and Pin 1 Output= 2.3V to 36.0V for the UC39432, Vee= 15V, leoLL = 1OmA, TA= TJ.
PARAMETER
TEST CONDITIONS
Reference Voltage Tolerance
TA= 25°C
Reference Temperature Tolerance
VeoLL= 5.0V
Reference Line Regulation
Vee= 2.2V to 36.0V, VeoLL = 5V
Reference Load Regulation
leoLL = 1OmA to 50mA, VeoLL = 5V
Reference Sink Current
Reference Source Current
E/A Input Bias Current
Vee= 2.2V to 36.0V
E/A Input Offset Voltage
E/A Output Current Sink (Internally Limited)
E/A Output Current Source
Minimum Operating Current
Vee= 36.0V, VeoLL = 5V
Collector Current Limit (Note 1)
VeoLL =Vee= 36.0V, Ref= 1.35V, ISET = GND
Collector Saturation
Vee= 2.2V to 36.0V, leoLL = 20mA
Transconductance (gm) (Note 1)
Vee= 2.2V to 36.0V, VeoLL = 3V, leOLL = 20mA, ISET = GND
MIN 1295 1291
0.7 -153
TYP 1300 1300 1.2 1.2
0.2
0.50 130 1.1 -140
MAX UNITS
1305 mV
1309 mV
10.0 mV
10.0 mV
10
µA
-10
µA
0.5
µA
2.0
mV
16
µA
-1
mA
0.80 mA
140 mA
1.5
v
-127 mS
5-307
UC19432 UC29432 UC39432
ELECTRICAL CHARACTERISTICS (Continued)
PARAMETER Error Amplifier AvoL Error Amplifier GBW Transconductance Amplifier GBW
TEST CONDITIONS
MIN TYP MAX
60
90
3.0
5
3
Note 1: Programmed transconductance and collector current limit equations are specified in the lsET pin description.
UNITS dB MHz MHz
Sl!NSE l > - - . . - - - - - - - - - r - - - - - - - - ,
44.2K
6.tloF
·--~
' 1.,,
COLI.
3'~3·0
FIGURE 1: 5.0V Opto-coupler Application
OVER-VOLTAGE COMPARATOR APPLICATION:
The signal V1N senses the input voltage. As long as the input voltage is less than 5.5V, the output is equal to the voltage on V1N. During this region of operation, the diode is reversed biased which keeps the EA+ pin at 1.3V. When V1N exceeds the over voltage threshold of 5.5V, the output is driven low. This forward biases the diode and creates hysteresis by changing the threshold to 4.5V.
OPTO-COUPLER APPLICATION:
The opto-coupler application shown takes advantage of the accessible pins REF and ISET. The ISET pin has a 33 ohm resistor to ground that protects the opto-coupler by limiting the current to about 20mA. This also lowers the transconductance to approximately 19mS. The ability to adjust the transconductance gives the designer further control of the loop gain. The REF pin is available to satisfy any high precision voltage requirements.
V1N -----------------------~
20K
10K
10K 1N914
1 COLL
5.Hl
ISET
FIGURE 2: 5.5V Over-Voltage Comparator with Hysterysis
UNITROOE !INTEGRATED CIRCUITS 7 CONITNENTAL BLVD.· MERRIMACK, NH 03054 TEL (603) 424-2410 ·FAX (603) 424-3460
5-308
OUT
6 5 4
OUT
2
0123456 VIN
n n INTEGRATED
~CIRCUITS
-UNITRCDE
Low Drop Out 3 Ampere Linear Regulator Family
UCC183-0/-3/-5 UCC283-0/-3/-5 UCC383-0/-3/-5
FEATURES Precision Positive Series Pass Voltage Regulation
0.45V Drop Out at 3A
Drop Out Under 2mV at 1OmA
Quiescent Current Under 650µA Irrespective of Load
Adjustable (5 Lead) Output Voltage Version
Fixed (3 Lead) Versions for 3.3V and 5V Outputs
Logic Shutdown Capability
Short Circuit Power Limit of 3% · VIN · ISHORT
Low VouT to VIN Reverse Leakage
Thermal Shutdown
DESCRIPTION
ADVANCED INFORMATION
The UCC183-0/-3/-5 family of positive linear series pass regulators are tailored
for low drop out applications where low quiescent power is important. Fabri-
cated with a BiCMOS technology ideally suited for low input to output differen-
tial applications, the UCC183-5 will pass 3A while requiring only 0.45V of
typical input voltage headroom (guaranteed 0.6V drop out). These regulators
include reverse voltage sensing that prevents current flow in the reverse direc-
tion. Quiescent current is always less than 650µA. These devices have been
internally compensated in such a manner that the need for a minimum output
capacitor has been eliminated.
UCC183-3 and UCC183-5 versions are in 3 lead packages and have preset outputs at 3.3V and 5.0V respectively. The output voltage is regulated to 1.5% at room temperature. The UCC183-0 versions, in a 5 lead package, regulate the output voltage programmed by an external resistor ratio.
Short circuit current is internally limited. The device responds to a sustained over-current condition by turning off after a TON delay. The device then stays off for a period, ToFF, that is 32 times the TON delay. The device then begins pulsing on and off at the ToN/TOFF duty-cycle of 3%. This drastically reduces the power dissipation during short circuit and means heat sinks need only accommodate normal operation. On the 3 leaded versions of the device TON is fixed at 500µs, on the adjustable 5 leaded versions an external capacitor sets the on time -- the off time is always 32 times TON. The external timing control pin, CT, on the five leaded versions also serves as a shutdown input when pulled low.
Internal power dissipation is further controlled with thermal overload protection circuitry. Thermal shutdown occurs if the junction temperature exceeds 165°C. The chip will remain off until the temperature has dropped 40°C.
The UCC183 series is specified for operation over the full military temperature
range of -55°C to +125°C. The UCC283 series is specified for operation over
the industrial range of -40°C to +85°C, and the UCC383 series is specified from
0°C to +70°C. These devices are available in 3 and 5 pin T0-220 power pack-
BLOCK DIAGRAM
ages. For other packaging options please consult the factory.
f r = - - - - - i VIN 1------f+-------,
VOUT
Current Limit
Voltage Amplifier
3.5/5A Current Reference
ADJ*
6/93
0.45V
3% Duty Cycle Current Limit 1---,.---==i Timer
Reverse Voltage Sense
Thermal Shutdown
* 5 Leaded Version Only.
GND
UCC183-0 UCC183-3 UCC183-5
R2 R1
82k 50k 150k 50k
UDG-93002
5-309
ELECTRICAL CHARACTERISTICS:
UCC183-0/-3/-5 UCC283:-0/-3/-5 UCC383-0/-3/-5
Unless otherwise stated, these specifications hold forTA = 0°c to 10°c tor the UCC383-X series, -40°C to +85°C for the UCC283-X, and -55°C to +125°C for the UCC183-X, VIN= VOUT + 1.5V, IOUT = OmA, CIN = 10µF, CouT = 22µF, CT= 1500pfforthe UCC183-0, TJ =TA.
PARAMETER UCC183-5 Fixed 5V, 3A Family
Output Voltage
Line Regulation Load Regulation Output Noise VoltaJ!..e Drop Out Voltage, VIN - VOUT
Peak Current Limit · Over Current Threshold
Current Limit Duty Cycle Over Current Time Out, TON Ripple Rejection Quiescent Current Reverse Leakage Current
UCC183-3 Fixed 3.3V, 3A Family
TEST CONDITIONS
TJ =25°C Over Temperature VIN= 5.15Vto 10V IOUT = OmA to 3A TJ = 25°C, BW = 10Hz to 10kHz IOUT 3A, VOUT = 4.85V IOUT 10mA, VOUT = 4.85V VoUT=OV
VoUT=OV VOUT=OV f = 120Hz, VOUT - VIN > 1.5V, ILOAD = 3A
ov <VIN< VouT. VOUT< 5.1V, atVOUT
OV <VIN< VOUT, VOUT < 5.1V, at VIN
MIN TVP MAX UNITS
4.925 4.875
4.5 3 330 60
-50
5
2 10 200 0.45 50 5 3.5 3 500
400
v 5.075 v 5.125
10 mV
20 mV
~Vrms
0.6
v
100 mV
6
A
4
A
TBD %
µs
dB
650 µA
50
µA
µA
Output Voltage
Line Regulation Load Regulation 0ut2_ut Noise Voltage Drop Out Voltage, VIN - VOUT
Peak Current Limit
TJ=25°C Over Temperature VIN= 3.45Vto 10V IOUT = OmA to 3A TJ = 25°C, BW = 10Hz to 10kHz IOUT 3A, VOUT = 3.15V IOUT 1.5A, VOUT = 3.15V IOUT 10mA, VouT = 3.15V VOUT=OV
3.25 3.22
4.5
3.3
2 7 200 0.7 0.45 50 5
3.35 mA
3.38 v
7
mV
15 mV
µVrms
1 v 0.6 v
100 mV
6
A
Over Current Threshold Current Limit Duty Cycle Over Current Time Out, TON Ripple Rejection Quiescent Current Reverse Leakage Current
UCC183-0 Adjustable Output, 3A Family
VOUT =OV VOUT = OV f = 120Hz, VOUT - VIN > 1.5V, ILOAD = 3A
ov <VIN < VOUT, VoUT < 3.35V, at VoUT
OV <VIN< VOUT, VOUT < 3.35V, at VIN
3
3.5
4
A
3 TBD %
330 500
µs
60
dB
400 650 µA
50
µA
-50
µA
Regulating Voltage at ADJ Pin
Line Regulation, atADJ Input Load Regulation, at ADJ Input Output Noise Voltage Drop Out Voltage, VIN - Vour
Peak Current Limit Over Current Threshold
TJ = 25°C Over Temperature VIN= VOUT + 150mVto 10V IOUT = OmA to 3A TJ = 25°C, BW = 10Hzto 10kHz VIN> 4V, IOUT = 3A VIN > 3V, IOUT = 1.5A VIN> 3V, IOUT = 10mA VOUT = OV, VIN = 6.5V VIN=6.5V
1.23 1.22
4.5 3
1.25
1 2 200 0.45 0.45 50 5 3.5
1.27 mA
1.28 v
3
mV
5
mV
µVrms
0.6 v 0.6 v
100 mV
6
A
4
A
5-310
UCC183-0/-3/-5 UCC283-0/-3/-5 UCC383-0/-3/-5
ELECTRICAL CHARACTERISTICS (cont.):
Unless otherwise stated, these specifications hold for TA= 0°C to 70°C for the UCC383-X series, -40°C to +85°C for the UCC283-X, and -55°C to +125°Cfor the UCC183-X, VIN= VOUT + 1.5V, IOUT = OmA, CIN = 10µF, COUT = 22µF, CT= 1500pF for the UCC183-0, TJ = TA.
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNITS
UCC183-0 Adjustable Output, 3A Family (cont.)
Current Limit Duty Cycle Over Current Time Out, TON
VOUT= OV VOUT = OV, CT= 1500pF
3 TBD % TBD 660 TBD µs
Ripple Rejection
f = 120Hz, VOUT - VIN > 1.5V, ILOAD = 3A
60
dB
Reverse Leakage Current
OV <VIN< VOUT, VOUT < 10V, at VOUT
50
µA
OV <VIN< VOUT, VOUT < 10V, at VIN
-50
µA
Bias current at ADJ Input
100 250 nA
Quiescent Current Shutdown Threshold
At CT Input
400 650 µA
0.25 0.45
v
Quiescent Current in Shutdown
VIN= 10V
10 25 µA
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. · MERRIMACK; NH 03054 TEL. (603) 424-2410 c FAX (800)424-3460
5-311
n n L.::::::'.J
INTliGRA.TliD CIACUIT8
mllliliUNITRDDE
Low Power Pulse Width Modulator
FEATURES · Low Power BiCMOS Process · 85µA Start-up Current · 1mA Run Current · 1A Peak Gate Drive Output · Voltage Feed Forward · Programmable Duty Cycle
Clamp · Opto Coupler Interface · 500kHz Operation · Soft Start · Fault Counting Shutdown · Fault Latch Off or Automatic
Restart
BLOCK DIAGRAM
DESCRIPTION The UCC1570 family of pulse width modulator controllers is intended for application in isolated switching supplies using voltage mode feedback. Made with BiCMOS, this device features low start-up current for efficient bootstrap supply operation, while maintaining the ability to drive a power MOSFET gate at frequencies above 500kHz. Voltage feed-forward provides fast and accurate response to wide line voltage variations without the noise sensitivity of currentmode control. Fast cu.rrent limiting is included with the ability to latch off after a programmable number of repetitive faults has occurred. Additional versatility is provided with a mil)imum duty-cycle clamp programmable within a 20% to 80% range.
CU( ...L.....L
4.SV
15V
CURRENT LIMIT
CURUll ··2~~~~-------~
6/93
SHUTDOWN O.&V
5-312
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (Current Limited Supply 1OmA) . . . . . . . . . . . · . . . · . . . . Self Limiting Supply Current ..·....................... ·. . . . . . . . . . . . . . . . . . . . . . . . . 20mA Analog Inputs (CURUM, VFWD, FEEDBK) ................................ 6V Programming Current {I (SLOPE), l(ISET)) .............................. -1 mA OutputCurrent{l{OUl)) ........................... DC ............ 180mA
. . . . . . . . . . . · · . . · . . . . . . . · . . . Pulse (0.5µs) . . . . . . 1.2A
Note: Al/ voltages are with respect to GND. Cu"ents are positive into the specified terminal.
CONNECTION DIAGRAMS
DIL-14 (TOP VIEW) N or J PACKAGE
SOIC-14 (TOP VIEW) DPACKAGE
PLCC-20 (TOP VIEW) L Or Q PACKAGE
UCC1570 UCC2570 UCC3570
COUNT'--~
CURLIM
SOFT ST
N/C ----"""""-,_..., GND
N/C
N/C
VCC
VREF
OUT
FREQ
PGND 7
N/C
N/C
RAMP
N/C VFWD
ISET FEED BK
'----SLOPE
ELECTRICAL
Unless otherwise stated, these specifications apply for TA= Oto 70°C forthe UCC3570, TA= -40 to
CHARACTERISTICS 85°C for the UCC2570, TA=-55 to 125°C for the UCC1570, R(ISET)=1 OOk, R(SLOPE)=121 k,
C(FRE0)=180pF, C(RAMP)=150pF, VCC:10V and TA=TJ.
PARAMETER Reference
VREF Line Regulation Load R~ulation Short Circuit Current
vcc
Vth (On) Vth (Off)
vcc
I(VCC) Start l{VCC) Run Line Sense Vth Hig!I Line Comparator Vth Low Line Comparator
TEST CONDITIONS
VCC=10to 13V, l{VREF)=Oto2mA VCC=10to 13V I(VREF)=O to 2mA VREF=OV
l{VCC)=10mA VCC=11V, VCC Comparator Off VCC Comparator On
MIN TYP MAX UNITS
4.9
5
5.1
v
2
10 mV
2
10 mV
10 50 mA
12 13
v
8
9
10 v
13.5 15
16
v
85 150 iAA
1
1.5 mA
3.8
4
4.2
v
0.95 1 1.05 v
lib{VFWD)
0 100 nA
Oaclllator
F~uency
90 100 110 kHz
Ramp Generator l(RAMP)/(SLOPE) -.!.{_RAMP)[{!S_fil Peak Ramp Voltage Vall!tA~Voltage ISET
9
10
11 NA
9
10 11 NA
3.8
4
4.2
v
0.95 1 1.05 v 0.95 1 1.05 v
5-313
UCC1570 UCC2570 UCC3570
ELECTRICAL
Unless otherwise stated, these specifications apply for TA= 0 to 70°C for the UCC3570, TA=
ov CHARACTERISTICS ( t) -40 to 85°C for the UCC2570, TA=-55 to 125°C for the UCC1570, R(ISET)=1 OOk,
con . R(SLOPE)=121 k, C(FRE0)=180pF, C(RAMP)=150pF, VCC=1 and TA=TJ.
PARAMETER Soft Start
Saturation l(SOFTST)/l(ISET) Pulse Width Modulator lib(FEEDBK) FEEDBK
Current Limit lib(CURLIM) Vth Current Limit Vth Shutdown
Fault Counter Vth Vsat l(COUNT)/l(ISET)
Output Driver Vsat High VsatLow Rise/Fall lime
TEST CONDITIONS VCC=11V, VCC Comparator Off
Zero Duty Cycle Maximum Duty Cycle, Note 1
I(OUT)=-1 OOmA I (OUT)=1 OOmA C(OUT)=1 nF, Note 1
MIN TVP MAX UNITS
25 100 mV
0.8
1
1.2 NA
0
100 nA
0.9
1
1.1
v
3.8
4
4.2
v
0
100 nA
180 200 220 mV
500 600 700 mV
3.8
4
4.2
v
0
100 mV
0.8
1
1.2 NA
0.4
1
v
0.4
1
v
20 100 ns
Note 1: This parameter guaranteed by design but not 100% tested in production.
PIN DESCRIPTION VCC: Chip supply voltage pin. Bypass to PGND with a low esl/esr 0.1 µF capacitor. Lead lengths must be minimum.
PGND: Ground pin for the output driver. Keep connections less than 2cm. Carefully maintain low impedance path for high current return.
OUT: Gate drive output pin. Connect to the gate of a power MOSFET with a resistor greater than 2 ohms. Keep connection lengths under 2cm.
VFWD: Voltage Feed Forward and Line Sense pin. Connect to input DC line using a restive divider.
SLOPE: Program the charging current for RAMP with a resistor from this pin to GND. This pin will follow VFWD.
FEEDBK: Input to the pulse width modulation comparator. Drive this pin with an opto coupler and a resistor to VREF. Modulation input range is from 1 to 4V.
ISET: A Resistor from this pin to GND programs RAMP discharge current, FREQ current, SOFTST current, and COUNT Current.
RAMP: Ramp Pin. Connect a capacitor to GND. Rising slope is programmed by current in SLOPE. This slope is compared to FEEDBK for pulse width modulation. The falling slope is programmed by the current in ISET and used to limit maximum duty cycle.
FREQ: Oscillator pin. Program frequency with a capacitor to GND.
VREF: Precision 5V reference, and bypass point for internal circuitry. Bypass this pin with 0.1 µF to GND.
GNO: Chip ground. Connect to a low impedance ground plane containing all analog low current returns.
SOFTST: Soft start pin. Program with a capacitor to GND.
COUNT: Program the time that fault events will be tolerated before shut down occurs with a capacitor and resistor to GND.
CURLIM: Current Limit Sense pin. Terminates OUT gate drive pulse for inputs over 0.2V. Enables fault counting function (COUNT). For inputs over 0.6V, the chip is immediately shut down.
FUNCTIONAL DESCRIPTION
Power Sequencing VCC normally connects through a high impedance (R5) to the rectified line, with an additional path (R6) to a low-voltage, bootstrap winding on the power transformer. VFWD normally connects to a divider (R1 and R2) from the rectified line. For circuit activation, the following conditions are all required:
1.VFWD between 1 and 4V 2.VCC has been under 9V (to reset the shutdown latch) 3.VCC over 13V 4.VREF over 4.5V
5-314
FUNCTIONAL DESCRIPTION (cont.)
At this time, the circuit will activate. l(VCC) will increase from its start up value of 85µA to its run value of 1mA. The capacitor on SOFTST is charged with a current determined by
-l{SOFTS7J = 1V/R4.
When SOFTST rises above 1V, output pulses will begin and l(VCC) will further rise to a level dictated by gate charge requirements. With output pulses, the low voltage bootstrap winding should now power the controller. If VCC falls below 9V, the controller will turn off and the start sequence will reset and retry.
VCCClamp An internal shunt regulator clamps Vee so that it will not exceed 15V.
Output Inhibit
During normal operation, OUT is driven high at the start of a clock period and back low when RAMP either cross~s FEEDBK or ~q~als 4V. If, however, any of the following occur, OUT 1s immediately driven low for the remainder of the clock period:
1.VFWD outside the range of 1 to 4V 2.CURLIM greater than 0.2V 3.FEEDBK or SOFTST less than 1V Normal output pulses will not resume until the beginning of the next clock period free of the above conditions.
Current Limiting
CURLIM is monitored by two internal comparators. The current limit comparator threshold is 0.2V. If the current limit comparator is triggered, OUT is immediately driven low and held low for the remainder of the clock cycle providing pulse-by-pulse over-current control for excessive loads. This comparator also causes CF to be ~harged for the remainder of the clock cycle. The charging current is
-l(COUN7J = 1V/R4
If repetitive cycles are terminated by the current limit comparator ~using COUNT to rise above 4V, the Shutdown Latch 1s set. The COUNT integration delay feature can be bypassed by the Shutdown Comparator which h'.ls a 0.6V threshold. The Shutdown Comparator immediately sets the Shutdown Latch. RF in parallel with CF resets the COUNT integrator following transient faults.
RF must be greater than 4 * R4.
Latched Shutdown
If CURLIM rises above 0.6V, or COUNT rises to 4V, the
shutdown latch will be set. This will force OUT low, dis-
charge. SOFTST and COUNT, and reduce l(VCC) to
approximately the shutdown
1 mA. latch
When, and if, VCC falls below will reset and l(VCC) will fall
9tV~
85µA, allowing the circuit to restart. If VCC remains
above 9V, an alternate restart will occur if VFWD is mo-
mentarily reduced below 1V. External shutdown
commands from any source may be added into either
the COUNT or CURLIM pins.
Deadtime Control The voltage waveform on RAMP has independently
UCC1570
UCC2570
UCC3570
controlled rising and falling edges. At the start of the clock period, RAMP is at 1V and rises to 4V. It then discharges back to 1V and awaits the next clock period. OUT can only be high during the rising part of the waveform, while it is positively blanked off during the falling portion. Setting the -dV/dt slope by R4 from ISET to GND establishes a minimum deadtime. The minimum deadtime is:
tel= 0.3* R4* CR.
Choose R4 between 20k and 200k and CR greater than 50pF. In order to have a pulse at OUT in the next clock period, RAMP must fall to 1V prior to the end of the current period. If it does not, OUT will remain low for the entire next clock period.
Voltage Feed-Forward The +dV/dt on RAMP is made proportional to line voltage. The slope is
dV/dt= 10* VFWD/ (R3 *CR),
where VFWD is line voltage scaled by R1 and R2.
Therefore, a changing line voltage will accomplish an immedi~te proportionate pulse width change without any action from the feedback amplifier. This will result in ~~stant volt-s~cond d~ive to the power transformer providing both international voltage operation, and excellent dynamic line regulation. VFWD is intended to operate over a 4:1 range (1 to 4V) with under and over voltage sensors set to drive OUT low if this range is exceeded. Choose R3 between 20k and 200k.
~
Frequency Set
A capacitor from FREQ to GND will determine a constant clock frequency. Frequency is:
F= 1.8/{R4 *C7J.
If required, frequency can be trimmed down from the
above equation by the addition of RT from FREQ to
GND. The reduction in frequency is a function of the ra-
tio of RT/R4. RT should be greater than 2.4 * R4 for
reliable operation.
E~ernal ~ynchroniz'.ltion can be accomplished by cou-
pling a shver pulse mto a small value series resistor in
the ground side of CT. The pulse width should be less
than 5% of the oscillator period.
·
Gate Drive Output
The UCC1570 is capable of 1A peak output current. Bypass VCC with at least 0.1 µF directly to PGND. Use a capacitor with low equivalent series resistance and inductance. The connection from OUT to the MOSFET gate should have a 2 ohm or greater damping resistor and the length should be minimized. A low impedance connection must be established between the MOSFET Source (or the bottom of the current sense resistor), the VCC bypass capacitor and PGND. PGND should then be connected by a single path (shown as RGND in the application) to GND.
5-315
UCC1570 TYPICAL APPLICATION RGND
UCC1570 UCC2570 UCC3570
VIN
SUPPLY
V1N
RETURN
RAMP AND PWM WAVEFORMS
OSCILLATOR CLOCK
RAMP CAPACITOR
~
~
4V
r
FIXED SLOPE
·I· ·I ~ PWM
BLANKING
RANGE
-+----~ CLOCK !
'
JLJ ~F:::K~- ~
~ lL__r
HIGH VIN
LOW VIN
FAULTV1N
5-316
CLOCK GENERATOR
UCC1570 UCC2570 UCC3570
FREQ
3.5V
1.5V
x~
(j)as ·14
DETECT
FREQ
_ _L _ _ L
CLK
EXTERNAL CLOCK SYNCHRONIZATION
FRrtQ
~~. EXT
CT 1.SK
---ol!.-
~
TPW ~ 2~F
FREQUENCY DEPENDENCE ON RT/ R4 RATIO
1.0000
FREQ
~-3.5V
V--\---1.sv
.9500 .9000
~ <::::
IZ
''
F/Fo .8500
±
.8000
.7500
7
Fo-1.8/(R4"Cl)
.7000
_'[_
10
100
RT/R4
S..317
.P..'...8. c~ f~B <>Z:D
z~~ ,,mm
~r-m
0~·<~-0=<~i>! ~~~ ~~iii l,il::.D-C"
~~:zc
i
..R.T.1..
J1
~ L2
~ 1 c
* * 1N.fo:
~::cm
CR3 i- i- CR5
1N4005 .,.. · 1N4005
l ,...L. +4C7B
C8 2.2nF
«XN
..R.,1.,1,
l2.2Cn5 F
111
U2 UCC3570
R7
vcc -·~~~~~~--
"1/"%"W"'
our,--·~~~~~
""'-
J
01
(,,
o;
:110~
CUR2 Llll~
SOFTST 14
~~CR7
RAMP
FAULT 1
220
R9
.L
F
p
C21 .J..
C3..L R1 0.11' 4.7K
1::1
'T'1000P
C'2<,T
R15 , 1800P 10K
R16 10K
R G G E N N Q DD
R3 11w·
2.7K 1%
L---1
C19 4700P
R17 100K
0.1 "T"
.J..C22 1"0.1 I C18J
· .,,,.1
1K
R10 3K
C10 10 25V
R8 ;~.J..
0.1 1KVT
f;! R4 2.2K 1W
·---C-R-8-- -·
L1
~~H
+
+
C15 C18
2182V00 2126V00
,.J.._.+c13 C1
1000 0.1 15V
~
:0:!!
»I)">'"
"U
c"U
0 ~
-,
0 z
+12V
J2 R13
~I CON2
COii
U3 UC39431
v c c
R1~
R2µ..
COLL
G N
C2 0.01
D
+12V C14 0.1 R6 1K
COii
c: c: c: 000
000
~ ~ u; '--~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~--~~-'Cl Cl Cl
n nINTEGRATED
~CIRCUITS
-UNITRODE
#~ ~~ \.~ . ·-··.R·'
Low-Power BiCMOS Current-Mode PWM
UCC1800/1 /2/3/4/5 UCC2800/1 /2/3/4/5 UCC3800/1 /2/3/4/5
FEATURES
DESCRIPTION
· 1OOµA Typical Starting Supply Current The UCC1800/1/2/3/4/5 family of high-speed, low-power integrated
circuits contain all of the control and drive components required for off-line · 500µA Typical Operating Supply Current and DC-to-DC fixed frequency current-mode switching power supplies with
· Operation to 1MHz
minimal parts count.
· Internal Soft Start · Internal Fault Soft Start
These devices have the same pin configuration as the UC1842/3/4/5 family, and also offer the added features of internal full-cycle soft start and internal leading-edge blanking of the current-sense input.
· Internal Leading-Edge Blanking of the Current Sense Signal
The UCC1800/1/2/3/4/5 family offers a variety of package options, temperature range options, choice of maximum duty cycle, and choice of
· 1 Amp Totem-Pole Output
· 70ns Typical Response from Current-Sense to Gate Drive Output
critical voltage levels. Lower reference parts such as the UCC1 803 and UCC1805 fit best into battery operated systems, while the higher reference and the higher UVLO hysteresis of the UCC1 802 and UCC1 804 make these ideal choices for use in off-line power supplies.
· 1.5% Tolerance Voltage Reference
The UCC180x series is specified for operation from -55°C to +125°C, the
· Same Pinout as UC3842 and UC3842A UCC280x series is specified for operation from -40°C to +85°C, and the UCC380x series is specified for operation from o°C to +70°C.
ORDERING INFORMATION
Part Number UCCxBOO UCCx801 UCCx802 UCCx803 UCCx804 UCCx805
Maximum Duty Cycle 100% 50% 100% 100% 50% 50%
BLOCK DIAGRAM
Reference Voltage 5V 5V 5V 4V 5V 4V
Turn-On Threshold 7.2V 9.4 12.5V 4.1V 12.5V 4.1V
Turn-Off Threshold 6.9V 7.4V 8.3V 3.6V 8.3V 3.6V
FB COMP
cs
5/93
logic Power
8 REF
Full Cycle Soft Start
IV
4 RC
5-319
UDG92009·2
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage (Low Impedance Source) .................... .... 12.0V Supply Current ............................................................... 30.0mA OUT Current ...................................................................... :1:1.0A OUT Energy (Capacitive Load) ·......··.·..·..........·..·............ 20.0µJ Analog lnpu1s (FB, CS) .......................................... -0.3V to 6.3'1 Power Dissipation at Ta < +25°C (N or J Package) ....·..... 1.0W Power Dissipation atTa < +25°C (D Package) ............... 0.65W Storage Temperature Range ..........·...;.....·...... -65°C to +150°C
Note 1: All voltages are wllh respect to GND. All cummts are positive Into the specified terminal.
Note 2:Consult Unftrode Integrated Circuits databook for Information r6(JS.rding thermal speelffcations and /Imitations ofpackages.
CONNECTION DIAGRAM
DIL-8 (TOP VIEW) J or N PACKAGE
UCC1800/1/2/3/4/5 · UCC2800/1/2/3/4/5
UCC3800/1/2/3/4/5
S0-8 (TOP VIEW) DPACKAGE
COMPO· FB 2
VCCREF
CS
8 OUT
RC
GND
COMP[]8· FB 2
VCCREF
CS 3
8 OUT
RC
·· .
GND
IJDGllCI010
ELECTRICAL SPECIFICATIONS
Unless otherwise stated, these specifications apply for ·55°:STas+125°C for UCC180x; ·40°:ST8:S+85°C for UCC280x; 0°C:ST8:S+70°C for UCC380x; VCC=10V (Note 3); RT=100kfrom REF to RC; CT::330pF from RC to GND; 0.1µF capacitor from VCC to GND; 0.0111F capacitor from VREF to GND. Ta=Tj.
PARAMETER
TEST CONDITIONS
UCC180X UCC280X
UCC380X
UNITS
MIN TVP MAX MIN TVP MAX
Reference SecUon
Output Voltage
Load Rllg_ulation Total Variation
Output Noise Voltage Lo11g_ Term Stablli!Y Output Short Circuit
_!)_=+25°C, l=0.2mA, UCCxS00/1/2/4
v 4.925 5.00 5.075 4.925 5.00 5.075
Ti=+25°C, 1=0.2mA, UCCx803, UCCx805 3.94 4.00 4.06 3.94 4.00 4.06
0.2mA<l<5rnA
UCCx800/1/2/4,1Note_n UCCx803, UCCx805,J!llote_n
10 30
10 25 mV
v 4.88 5.00 5.10 4.88 5.00 5.10
v 3.90 4.00 4.08 3.90 4.00 4.08
10Hz:Sf:S1OkHz, Ti=+25°C.1Note ~
70
70
µV
Ta=+125°C, 1000 Hours_iNote ~
5
5.
mV
-5
-35 ·5
-35 mA
Oscillator Section
Oscillator Frequency
Tem~rature Stabll.itY_ Am..e!_itude
UCCx800, UCCx802, UCCx804,jNote 4)_ 40 46 52 40 46 52 kHz UCCx801, UCCx803, UCCx805,jNote 4)_ 26 31 36 26 31 36
_{_Note 9)
2.5
2.5
%
v 2.30 2.45 2.50 2.30 2.45 2.50
Error Ampllfler Section
Input Voltage
Input Blas Current O~n Loop VoltaJl_e Gain COMP Sink Current COMP Source Current
COMP=2.5V; UCCx800/1/2/4 COMP=2.0V; UCCx803, UCCx805
FB=2.7V, COMP=1.1V
FB=1 ;av. COMP.:REF-1V
2.44 2.50 2.56 2.44 2.50 2.56
v
1.95 2.0 2.05 1.95 2.0 2.05
-1
1 -1
1
µA
60 80
60 80
dB
.0.3
3.5 0.4
2.5 mA
-02 -0.5 -0.8 -0.2 -0.5 -0.8 mA
PWMSecUon
Maximum Duty Cycle Minimum Duty Cvcle
UCCx800, UCCx802, UCCx803 UCCx801, UCCx804, UCCx805 COMP=OV
97 99 100 97 99 100
%
48 49 50 48 49 50
0
0
%
Current Sense Section
Gain Maximum lnp_ut S.!inal Input Blas Current
.1Note~ COMP=5V (Note~
1.10 1.65 1.80 1.10 1.65 1.80 VN
0.9 1.0 1.1 0.9 1.0 1.1
v
-200
200 -200
200 nA
5-320
ELECTRICAL SPECIFICATIONS
UCC1800/1/2/3/4/5 UCC2800/1/2/3/4/5 UCC3800/1/2/3/4/5
Unless otherwise stated, these specifications apply for -55°sTas+125°C for UCC180x; -40°sTas+85°C for UCC280x; 0°CsTas+70°C for UCC380x; VCC=10V (Note 3); RT=100Kfrom REF to RC; CT=330pf from RC to GND; 0.1 µF capacitor from VCC to GND; 0.01 µF capacitor from VREF to GND. Ta=Tj.
PARAMETER
TEST CONDITIONS
UCC180X UCC280X
UCC380X
UNITS
MIN TYP MAX MIN TYP MAX
Current Sense Section (cont.)
CS Blank Time Over-Current Threshold COMP to CS Offset
CS=OV
50 100 150 50 100 150 ns
1.35 1.47 1.60 1.35 1.47 1.60
v
0.45 0.90 1.35 0.45 0.90 1.35
v
Output Section
OUT Low Level
1=20mA, all..e_arts 1=200mA, all parts 1=50mA, VCC=5V, UCCx803, UCCx805
0.1 0.4 0.35 0.90 0.15 0.40
0.1 0.4
v 0.35 0.90
0.15 0.40
OUT High VsAT (Vee-OUT)
1=20mA, VCC=OV, all parts l=-20mA, all parts l=-200mA, al~rts l=-50mA,VCC=5V, UCCx803, UCCx805
0.7 1.2 0.15 0.40 1.0 1.9 0.4 0.9
0.7 1.2
0.15 0.40
1.0 1.9
v
0.4 0.9
Rise Time Fall Time
CL=1nf CL=1nf
41 70 44 75
41 70
ns
44 75
ns
Under-Voltage Lockout Section
Start Threshold (Note 8)
UCCx800 UCCx801 UCCx802, UCCx804 UCCx803, UCCx805
6.6 7.2 7.8 6.6 7.2 7.8
8.6 9.4 10.2 8.6 9.4 10.2
11.5 12.5 13.5 11.5 12.5 13.5
v
3.7 4.1 4.5 3.7 4.1 4.5
Minimum Operating Voltage after Start (Note 8)
UCCx1800 UCCx1801
6.3 6.9 7.5 6.3 6.9 7.5 6.8 7.4 8.0 6.8 7.4 8.0
UCCx802, UCCx804 UCCx803, UCCx805
7.6 8.3 9.0 7.6 8.3 9.0
v
3.2 3.6 4.0 3.2 3.6 4.0
Hysteresis
UCCx800
0.12 0.3 0.48 0.12 0.3 0.48
UCCx801 UCCx802, UCCx804 UCCx803, UCCx805
1.6 2 2.4 1.6 2 2.4
3.5 4.2 5.1 3.5 4.2 5.1
v
0.2 0.5 0.8 0.2 0.5 0.8
v
Soft Start Section
COMP Rise Time
FB=1.8V, Rise from 0.5V to REF-1 V
4
4
ms
Overall Section
Start-~ Current Operati'1!._ S~Current VCC Zener Shunt Voltage Shunt to Start Difference
VCC<Start Threshold FB=OV, CS=OV ICC=10mA (Note 8) UCCx802, UCCx804
0.1 0.2
0.1 0.2 mA
0.5 1.0
0.5 1.0 mA
12 13.5 15 12 13.5 15
v
0.5 1.0
0.5 1.0
v
Note 3: Adjust VCC above the start threshold before setting at 1OV. Note 4: Oscillator frequency for the UCCxBOO, UCCx802 and UCCx803 is the output frequency.
Oscillator frequency for the UCCx801, UCCx804 and UCCx805 is twice the output frequency.
Note 5: Gain is defined by: A- 11 VcOMP 11 Vcs
o :S Vcs:S 0.8V.
Note 6: Parameter measured at trip point oflatch with Pin 2 at OV.
Note 7: Total Variation includes temperature stability and load regulation.
Note 8: Start Threshold and Zener Shunt thresholds track one another.
Note 9: Although guaranteed by design not 100% tested in production.
5-321
PIN DESCRIPTIONS
COMP: COMP is the output of the error amplifier and the
input of the PWM comparator.
-
Unlike other devices, the error amplifier in the UCC3800 family is a true, low output-impedance, 2MHz operational amplifier. As such, the COMP terminal can both source and sink current. However, the error amplifier is internally current limited, so that you can command zero duty cycle by externally forcing COMP to GND.
The UCC3800familyfeatures built-in full cycle Soft Start. Soft Start is implemented as a clamp on the maximum COMP voltage.
FB: FB is the inverting input of the error amplifier. For best stability, keep FB lead length as short as possible and FB stray capacitance as small as possible.
CS:· CS is the input to the current sense comparators. The UCC3800 family has two different current sense comparators: the PWM comparator and an over-current comparator.
The UCC3800 family contains digital current sense filtering, which disconnects the CS terminal from the current sense comparator during the 100ns interval immediately following the rising edge of the OUT pin. This digital filtering, also called leading-edge blanking, means that in most applications, no analog filtering (RC filter) is required on CS. Compared to an external RC filter technique, the leading-edge blanking provides a smaller effective CS to OUT propagation delay. Note, however, that the minimum non-zero On-Time of the OUT signal is directly affected by the leading~edge-blanking and the CS to OUT propagation delay.
The over-current comparator is only intended for fault sensing, and exceeding the over-current threshold will cause a soft start cycle.
RC: RC is the oscillator timing pin. For fixed frequency operation, set timing capacitor charging current by connecting a resistor from REF to RC. Set frequency by connecting a timing capacitor from RC to GND. For best performance, keep the timing capacitor lead to GND as short and direct as possible. If possible, use separate ground traces for the timing capacitor and all other functions.
UCC1800/1/2/3/4/5 UCC2800/1/2/3/4/5 UCC3800/1/2/3/4/5
The frequency of oscillation can be estimated with the
following equations:
UCCx800/1 /2/4:
F 1.5 = RxC
UCCx803, UCCx805:
F=-1.:Q__ RxC
where frequency is in Hz, resistance is in ohms, and capacitance is in farads. The recommended range of timing resistors is between 1Ok and 200k and timing capacitor is 1OOpFto1 OOOpF. Never use a timing resistor less than 1Ok.
GND: GND is reference ground and power ground for all functions on this part.
OUT: OUT is the output of a high-current power driver capable of driving the gate of a power MOSFET with peak currents exceeding ±750mA. OUT is actively held low when VCC is below the UVLO threshold.
The high-current power driver consists of FET output devices, which can switch all of the way to GND and all of the way to VCC. The output stage also provides a very low impedance to overshoot and undershoot. .This means that in many cases, external schottky clamp diodes are not required;
VCC: VCC is the power input connection for this device. Although quiescent VCC current is very low, total supply current will be higher, depending on OUTcurrent. Total VCC current is the sum of quiescent VCC current and the average OUT current. Knowing the operating frequency and the MOSFET gate charge (Qg), average OUT current can be calculated from:
lour= Q9 x F
To prevent noise problems, bypass VCC to GND with a ceramic capacitor as close to the chip as possible and an electrolytic capacitor.
REF: REF is the voltage reference for the error amplifier and also for many other functions on the IC. REF is also used as the logic power supply for high speed .switching logic on the IC.
When VCC is lower than the UVLO threshold, REF is actively held to GND. This means that REF can be used as a logic output indicating power system status.
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL Bl.VD. ·MERRIMACK, NH 03054 TEL (603) 424-2410 ·FAX (603) 424-3460
5-322
n nINTEGRATED
~CIRCUITS
-UNITRODE
Low Power, Dual Output, Current Mode PWM Controllers
UCC1806
UCC2806 UCC3806 ADVANCED INFORMATION
FEATURES
DESCRIPTION
BiCMOS Version of UC1846 Families
1.4 mA Max Operating Current
1OOµA Max Start-up Current
1.0 A Peak Output Current
125 nSec Circuit Delay
Easier Parallelability
Improved Benefits of Current-Mode Control
The UCC1806 family of BiCMOS PWM controllers offers exceptionally improved performance with a familiar architecture. With the same block diagram and pinout of the popular UC1846 series, the UCC1806 line features increased switching frequency capability while greatly reducing the bias current used within the device. With a typical start-up current of 50 µA and a well defined voltage threshold for turn-on, these devices are favored for applications ranging from off-line power supplies to battery operated portable equipment. Dual high-current, FET-driving outputs and a fast current sense loop further enhance device versatility.
Of course, all the benefits of current-mode control including: simpler loop closing, voltage feed-forward, parallelability with current sharing, pulse-by-pulse current limiting, and push-pull symmetry correction are readily achievable with the UCC1806 series.
These devices will be available with multiple package options for both thru-hole and surface-mount applications; and in commercial, industrial, and military temperature ranges. Contact factory for availability.
BLOCK DIAGRAM
15V
6/93
SHUTDOWN LOCKOUT
1-----__,..._ CURRENT LIMIT __,,_~,__-----..---u_i ADJUST
CURRENT LIMIT RESTAR UNDER VOLTAGE LOCKOUT
5-323
UCC1806 UCC2806 UCC3806
ABSOLUTE MAXIMUM RATINGS
CONNECTION DIAGRAM
Supply Voltage, Low Impedance (Pin 15) ·....·..·.........................+15V Supply Current, High Impedance (Pin 15)...............................+25mA Output Supply Voltage (Pin 13)..................................................+18V Output Current, Continuous Source or Sink........................+/-200mA Output Current, Gate Drive .................................................+/-500mA Analog Input Voltage (Pin 3,4,5,6, 16).................-0.3V to +VIN+ 0.3V Sync Output Current (Pin 10)...........:....................................+/-30inA Error Arrtplnier Output Current (Piri 7)...........+10mAI- is Sett Limiting Power Dissipation at Tc= 25°C (Note 3)..............................1000mW Power Dissipation at Tc· 25°C (Note 3)..............................2000mW Storage Temperature Range.............;......................-65°C to +150°C Lead Temperature (soldering, 10 seconds)............................+300°C
DIL-16 {TOP VIEW) N Package
Current Limit Adjust
{+)Current Sense 4 N.I. s
Shutdown VIN BOUT Ve GND
Note 1: All voltages are with respect to Ground, Pin 12.
Note 2: Currents are positive into, negative out of the specified terminal.
Note 3: Consult packaging section of databook for thermal limitations and considerations of package.
Note 4: Pin Numbers refer to DIL-16pkg.
AOUT Sync
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA. -55°C to +125°C for ucc1806; -40°c to +85°C for the UCC2806 and o·c to +70°c for the UCC3806; V1N = 12V, RT= 33k, CT= 330pF, CBYPASS on VREF - .01µF, TA= TJ.
PARAMETER
TEST CONDITION
REFERENCE SECTION
Output Voltag_e Load R~ulation
TJ = 25°C, lo= o.2mA 0.2mA < lo < 5mA
Tem_E!lrature Stabi!lli'._
Note5
Total Out_2Ut Variation Ou!E!Jt Noise Voltag_e Lol}g_ Term Stabili!Y.
Line, Load, Temperature
fill 10Hz s Is 10kHz, TJ = 25°CINote 5I Ti.= 125°C 1000 Hours_(_Note
Out.J!!lt Short Circuit OSCILLATOR SECTION
Initial Accurac:y_
TJ= 25·c
Tem_Q_erature Stabifily_
TMIN <TA< TMAX (NOTE 5)"
Am_.2!itude
Sync Delay to Outputs
Pin 8 = OV, Pin 9 = VREF
VsYNC = 0.8V to 2.0V
Discha~ Current
TJ = 25C VPIN B = 2.0V
~c Vol
lour= +1mA
~c VoH
IOUT= -5mA
~c VIL
Pin 8 = ov Pin 9 = VREF
fu'pc V1H
Pin 8 - ov Pin 9 = VREF
§y_nc l!JQ.ut Current
EBB.OB. AMPLIFIE_R_SECTION
IOQ_Ut Offset Volt~e
l!ll!._ut Bias Current
l!ll!._ut Offset Current
Common Mode RaQll.e ~en Loo__Q_ Gain U~ Gain Bandwidth
Vo= 1.0 to 4.0
Ou.!!!.ut Sink Current
V10 < -20mV VPIN 7 = 1.0V
Ou.!!!._ut Source Current Ou.!!!._ut Hjg_h Level Ou.!!>_ut Low Level
V10 < 20mV VPIN 7 = 3.0V VID = 50 mV V10 = -50mV
UCC1806 UCC2806 MIN TYP MAX
5.05 5.10 5.15
3
25
0.2 0.6
-150
150
70
5
25
-10
-30
41
49
57
5
2.35
50 100
2
0.4
2.4
0.8
2.0
-1
+1
5
-1
500
0
VIN-2
80 100
1
1
-80 -120
4.5
0.5
UCC3806 MIN TYP MAX
5.02 5.10 5.18
3
25
0.2 0.6
-150
150
70
5
25
-10
-30
37
49
60
5
2.35
50 100
2
0.4
2.4
0.8
2.0
-1
+1
10
-1
500
0
VIN-2
80 100
1
1
-80 -120
4.5
0.5
UNITS
v mV mV/°C mV
J!Y
mV mA
kHz o/o
v
NS
mA v v v v
J.LA
mV uA nA v dB MHz mA uA
v v
5-324
UCC1806 UCC2806 UCC3806
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA= -55°C to +125°C for UCC1806; -40°C to +85°C for the UCC2806; and 0°c to +70°C for the UCC3806;V1N-
12v, RT= 33k, CT= 330p F, CBYPASS on VREF = .01µF, TA= TJ.
PARAMETER
TEST CONDITION
CURRENT SENSE AMPLIFIER SECTION
Amplifier Gain
VPIN3 = ov, VPIN1 = VREF (Notes 3,4)
Maximum Differential Input
VPIN1 = VREF, VPIN5 = VREF,
Signal (Vpin4-Vpin3)
VPIN6 = OV
Input Offset Voltage
VPIN1 = 0.5V, VPIN7 = open
CMRR
VcM = Oto V1N - 3.5
PSRR
Input Bias Current
VP1N1 = 0.5, Pin 7 open (Note 3)
Input Offset Current
VPIN1 = 0.5V, Pin 7 open (Note 3)
Delay to Outputs
VPINS = VREF, Pin 6 = 0, Pin4-
Pin 3 = Oto 1.5V st~Note ~
CURRENT LIMIT ADJUST SECTION
Current Limit Offset
VPIN3 = 0, VPIN4 = 0, Pin7 =open
li:!E_ut Bias Current
SHUTDOWN TERMINAL SECTION
Threshold Voltage
Input Voltage Range
Minimum Latching Current
Maximum Non-Latching Current
Delay to Outputs
VPIN16 = 0 to 1.3V
OUTPUT SECTION
Output Supply Voltage
Output Low Level
!SINK= 20mA
!SINK = 1OOmA
Output High Level
!SOURCE = -20mA
!SOURCE= -1 OOmA
Rise Time
TJ = 25°C, CLOAD = 1OOQEF'
Fall Time
TJ = 25°C, CLOAD = 1000pF
UNDER VOLTAGE LOCKOUT SECTION
Startup Current
V1N < Start Threshold
Operating Supply Current
V1N Shunt Voltage
IVIN = 10mA
Startup Threshold
Threshold Hysteresis
UCC1806 UCC2806
MIN TYP MAX
UCC3806
MIN TVP MAX
2.7
3 3.3
1.1
10 30 60 60
-1 1 125 175
2.7
3
3.3
1.1
10
50
60
60
-1
1
125 175
I 0.40 0.5 o.so 0.40 0.5 0.60
1 j_
1
0.94 0
300
1.00 1.06 VIN
200 200 80 50 100
0.9 1.0 1.1
0
VIN
300 200
200 80
50 100
2.5
11.8 11
15 100 200 0.40 1.1 11.9 11.6 35 65 35 65
2.5
15
100 200
0.40 1.1
11.8 11.9
11 11.6
35
65
35
65
50 100
1 1.4
15
16.5
6.5 7.5 8
0.75
50 100
1
1.4
15
16.5
6.5 7.5
8
0.75
UNITS
VN
mV dB dB µA µA nS
mV
flA
v v
µA µA nS
v mV v v v nS nS
µA mA v v v
Note 1: All voltages are with respect to Ground, Pin 12. Note 2: Currents are positive into, negative out of the specified terminal. Note 3: Parameters measured at trip point of latch with Vpin5 = Vref, Vpin6 = OV. Note 4: Amplifier gain defined as:
G = delta change at pin lldelta change forced at pin 4
delta voltage at pin 4 = O to 1V. Note 5: Not 100% tested in production. Note 6: Current Sense amp output is slew rate limited to provide noise immunity.
UNITRIDE INTEGRATED CIRCUITS 7CONTINENTAL BLVD.· MERRIMACK, NH 03054 TEL. (603) 424·2410 · FAX (603) 424-3460
5-325
n n INTEIJRATED
~CIRCUIT·
..-UNITRODE
UCC1810 UCC2810 UCC3810
ADVANCED INFORMATION
Low-Power BiCMOS Dual Current-Mode PWM
FEATURES
100µA Typical Starting Supply Current .
DESCRIPTION
The UCCx810 high-speed dual PWM integrated circuits implement two synchronous pulse~width modulators for use in off-line and DC-to-DC power sup-
750µA Typical Operating Supply plies.
Current
These devices provide perfect synchronization between two PWMs by using
Operation to 1MHz
the same oscillator. This oscillator also provides a slow-rise, fast-fall wavetorm which can be used for slope compensation if required.
Internal Soft Start
Using a toggle flip flop to alternate between modulators, this IC ensures that
Internal Fault Soft Start
Internal Leading-Edge Blanking of the Current Sense Signal·
one PWM will not slave, interfere, or otherwise affect the other PWM. This toggle flip flop also ensures that each PWM will be limited to 50% maximum duty cycle, so that in most applications, stable current mode control will not require · slope compensation.
1 Amp Totem-Pole Outputs
These ICs contain many of the same elements of. the UC3842 current mode
70ns Typical Response from Current-Sense to Gate Drive Output
controller family, combined wiht the. enhancements of the UCC3800 family so that power supply parts count can be minimized. These enhancements include leading edge blanking of the current sense signals, full-cycle internal soft start,
CMOS output drivers, and outputs which remain low even when the supply 1% Tolerance Voltage Reference voltage is removed.
BLOCK DIAGRAM
CS1
CS2
Vee OK VREF
1.5V
1/93
VFB2 Comp2 5-326
Sync CT RT
Enable2 Pwr Gnd
UDG-92062
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. · MERRIMACK, NH 03054 TEL (803) 424-2410 ·TELEX 95-3040
n n L::::.Jj
INTEGRATED CIRCUITS
-UNITRCDE
UCC1883 UCC2883 UCC3883
Micropower Peak Current Mode Controller
ISDN 1.430 RELATED FEATURES Zero-Power Startup Capability
· Restricted Mode Detection Precision Programmable Quiescent Current
· Very Low Quiescent Power for CCITT 25mW Restricted Mode Programmable Continuous Input Current Limit
GENERAL FEATURES Low-Power Peak Current Mode Controller Oscillator Synchronizes to Secondary Side Clock Leading Edge Blanking of Current Sense Waveform
· 50% Maximum Duty Cycle · Undervoltage Lockout with
Hysteresis 5V Vdd Logic Supply Regulator Programmable Low Line Sensing · Programmable Soft Start · Programmable Fault/Restart Delay Programmable Output Overload Fault Detection
BLOCK DIAGRAM
DESCRIPTION The UCC 1883 is a peak current mode PWM controller designed to operate in conjunction with the UCC1885 secondary-side regulation IC. Together these devices provide the features to implement a fully isolated switch mode power supply with improved output regulation. In addition, this combination of ICs will allow a converter to meet the guidelines set forth in CCITT ISDN recommendation L430. The chip set is intended mainly for use in DC/DC discontinuous tlyback power converters, which are the most economical tor developing multiple output voltages. Peak current mode control offers the advantages of pulse-by-pulse current limiting, automatic feed forward, and improved load response characteristics. The UCC1885 companion IC provides feedback control voltage and oscillator synchronization information to the UCC1883 via an isolation pulse transformer. The UCC1883 uses the feedback voltage and frequency information from the UCC1885 to determine the current loop control voltage, i.e. the voltage analog of the current commanded by the voltage loop. This internal control voltage is, in turn, used by the UCC1883 in a conventional peak current mode PWM circuit. Internal leading edge blanking of the current sense waveform eliminates the need for an external filtering network on the ls·Ns· input. When in restricted mode or lightly loaded, the UCC 1883 operates with a minimum pulse width determined by the leading edge blanking circuit. This eliminates the spurious EMI generated if arbitrarily short output pulses are produced by the PWM.
In addition to pulse-by-pulse current limiting, an over current threshold is maintained. A fault condition may also be triggered by repeated peak current limit conditions, through the use of the programmable output overload detector. If either of these faults is detected, OUT is immediately disabled, and a programmable restart period occurs before a soft start sequence is initiated.
Vee
5V REFERENCE 9.5V
RUN
PWM CONTROL
LOGIC
&
BIAS CURRENT
c,
l1N
1/93
OSCILLATOR & TIMER
INPUT CURRENT
LIMIT
JI
1.2V
SIH
6 FB+
ISOLATION INTERFACE
7 FB-
~ Vss
5-327
ABSOLUTE MAXIMUM RATINGS Supply Voltage (Veel .................................................. 16.SV Maximum Vee Slew Rate ........................................ 10V/ms Maximum Voltage:
v RBIAS' CSTART' LINE'
IMODE' FB+, FB-, OUT, VREG ................. Vee+0.3Vto 18V VDO ..............................................................................7V COL' lseNsE· CT ......................................... Voo+ 0.3V to 7V VUMIT' l,N ....................................................................0.3V Minimum Voltage: VLIMIT ........................................................................ -Vee All Other Pins ........................................................- 0.3V Maximum DC Current, Any Pin, Source or Sink ...... 1OOmA Maximum Peak Current, Any Pin, Source or Sink ... SOOmA Total Package Dissipation (N package) ........................ 1W Total Package Dissipation (D package) ................. 725mW
so c Storage Temperature ..............................- 65°C to+1 0
Lead Temperature (Soldering, 10 seconds) ............. 300°C
UCC1883 UCC2883 UCC3883
DESCRIPTION (Continued) ISDN-specific features allow the UCC 1883/UCC1885 combination to be compatible with CCITT recommendation 1.430. The linear pre-regulator is intended to control a depletionmode NMOS pass transistor, such as a BSS129. Startup power drawn from the line can be reduced to zero if a bootstrap winding provides power to the UCC1883 Vee pin. An internal current comparator is provided to sense restricted mode directly from the input to the converter. Maximum input current may be accurately programmed and continuously limited with the use of an external PMOS pass transistor. Precision programming of the quiescent current used by the UCC1883 allows the system to meet the 25mW restricted mode power limit, or the current can be set to achieve higher operating frequencies at the cost of increased power consumption.
The UCC1883 is fabricated in Unitrode's 3um BiCMOS process. Even though the device contains internal clamping diodes on all pins, the part should still be considered static sensitive. Normal ESD handling procedures for CMOS devices should be observed when using the UCC1883.
Note 1: Note 2:
Note 3:
All voltages expressed with respect to pin 10, currents are positive into the specified terminal. All maximum signal pin voltage limits apply for cases of zero source impedance. Higher or lower voltages
may be impressed through a finite source impedance which causes the input current to be limited to the
values specified, with total package power dissipation at or below specified limits. Consult Packaging Section of Databook for thermal limitations and considerations of package.
Pin Pin Name Number
1
RBIAS
2
CST ART
Pin Type
Analog Program Analog Program
3
VLIHE
Analog Input
4
IMODE
Analog Input
5
VDD
Analog Output
6
FB+
Digital VO
7
FB-
Digital VO
B
Vee
Power Supply
9
OUT
Digital Output
10 v..
Power Supply
11
ISENSE
Analog Input
12
COL
Analog Program
13
c,
Analog Program
14
v, .. IT
Analog Output
15
1,.
Analog Program
16
VREO
Analog Output
Function
Quiescent Bias Current Set Soft Start and Restart Delay Timing Set Input Line Voltage Sense Input Line Polarity Sense 5V Logic Regulator Differential Feedback Communication Signal{+) Differential Feedback Communication Signal (-) Positive Power Supply Input Power Switch Control Voltage UCC1BB3 Ground Reference Primary Current Sense Output Overload Timing Set Oscillator Frequency Set Input Current Limit Control Voltage Input Current Limit Set 9.5V Pre-regulator Control Voltage
5-328
CONNECTION DIAGRAM
DIL-16 J or N Package, SOIC-16 D Package
R01AS CsTART Vu NE IMODE Voo FB + FBVee
VREG l1N Vu MIT CT Col lsENSE Vss OUT
UCC1883 UCC2883 UCC3883
ELECTRICAL CHARACTERISTICS : (Unless otherwise noted, all specifications apply for Ta =0°C to+ 70°C for the UCC3883, -40°C to+ 85°C for the UCC2883, -55°C to+ 125°C for the UCC1883; Vee= 12V, VDD = 5V, R.... = 200Kohms, c, = 100pF, Ta -Tj.)
PARAMETER
TEST CONDITIONS
UVLO SECTION
'!_g;_Start Threshold '!_g;_Threshold Hysteresis
LINEAR PRE-REGULATOR SECTION
Regulated Vcc Voltage
(See Note 1)
Regulated Vcc to UVLO Delta
Vcc Override Threshold
USER BIAS SECTION
R.... Voltage
Ti =25°C
R81·· Voltage Line Regulation Total R..,. Voltage Variation
10.0V<Vcc<13.5V lnitia,I + Line + Temperature
INPUT CURRENT LIMIT SECTION
11· Offset Voltage Output Reference Current
VLIMIT=-3V
Ti = 25·c. ~= ov
IREF Line Regulation
10.0V<Vcc<13.5V
Total IREF Variation
Initial + Line + Temperature
VLIMIT Low Level VLIMIT High Level VLIMIT Output Current OSCILLATOR SECTION
11· = 0.2V, )loutl <10nA
11· = -0.2V, I loutl <1 OnA
l1N · -0.2V, VLIMIT= - 3V
Initial Accuracy
Ti= 25°c
Voltage Stability
10.0V<Vcc<13.5V
Total Oscillator Variation
Initial+ Line+ Temperature
CT Ramp Amplitude
SOFT START SECTION
Soft Start Current (source) Restart- Delay Current (sink) FAULT HANDLING SECTION
CSTART = 2.5V CSTART = 2.5V
Overload Current Source Overload Current Sink
COL= 0.5V COL= 0.5V
Overload Fault Threshold
Over Current Threshold
Over Current Delay
(See Figure 1) (Note 3)
CURRENT SENSE SECTION
Peak Current Limit Threshold
PWM LOGIC and OUTPUT SECTION
Minimum Duty Cycle
ISENSE = ov
Maximum Duty Cycle
ISENSE = 1.3V
OUT Low Level
lout= 10mA lout= 100mA
OUT High Level
lout= -10mA lout = -1 OOmA
OUT Rise Time
Tj = 25°C, Cload = 1nF (See Figure 2)
OUT Fall Time
Ti= 25°C, Cload = 1nF (See Figure 2)
Min Typ Max Units
l 8.0 l 1.5
9.0 2.0
10.0 2.5
v v
8.6
9.5
10.3
v
200 500
700
mV
-
-
10.6
v
1.17 1.2
-
8
1.15
-
1.23
v
16
mV
1.25
v
-8
-
1.6
1.9
-
10
1.5
-
-10.5 -9
-
0.6
3
6
8
mV
2.1
uA
50
nA
2.2
uA
-v
1.0
v
14
mA
30
35
1
29,5
2.35 2.5
40
kHz
3
%
41.5 kl!z
2.65
v
17
30
0.5
1
1.4
2.2
1.4
2.2
1.4
1.5
1.4
1.5
-
100
1.1
1.2
-
49
-
11.85 10.5
-
-
-
50 0.05 0.5 11.95 11.5 25 25
43
uA
2 l uA
3.0
uA
3.0
uA
1.6
v
1.6
v
200
ns
1.3 l v
0
%
51
%
0.15
v
1.5
v
-v
-v
75
ns
75
ns
5-329
UCC1883 UCC2883
UCC3883
ELECTRICAL CHARACTERISTICS: (Unless otherwise noted, all specifications apply for Ta =0°C to+ 70°C for the UCC3883,
c, -40°C to+ 85°C for the UCC2883, -55°C to+ 125°C for the UCC1883; Vee - 12V, V0 D· 5V, R.... = 200Kohms, = 100pF, Ta= Tj.)
PARAMETER
TEST CONDITIONS
Min Typ
Max Units
ISOLATION INTERFACE SECTION FB Input High Voltage FB Input Low Voltage FB Input Pulse Width FB Output Pulse Width LOLINE Status Threshold RSMODE Status Threshold
V (FB+) - V (FB-), O< = FB < = V00 v (FB+) - v (FB-), 0 < = FB < = VOD (See Figure 3) (Note 3) (See Figure 3) (Note 3)
VOD REGULATOR VDo Output Voltage VDD Line Regulation VDD Load Regulation V0D Short Circuit Current Limit
No External Load 10.0V < Vee < 13.5V - 5mA < lout < OmA voo = ov
POWER SUPPLY
_u(.;_ Sup~urrent
CPD
Note 1: BSS129 (or equivalent) External Pass Element, 1uF Ceramic Bypass; see Figure 6. Note 2: Operating in Conjunction with UCCx885 Using Equal Valued R...5· Note 3: This Parameter Guaranteed but not 100% tested in production.
-
1.3
1.8
v
-1.8 -1.3
-
v
80
300
-
ns
75
ns
1.0
1.2
1.3
v
1
2
4
uA
4.75
5
5.25
v
-
10
30
mV
-
100
200
mV
10
50
80
mA
-
-
200 150
250
-
~
pF
lsENSE td
OUT
OVER CURRENT FAULT TIMING FIGURE 1
V(FB+) -V(FB-)
tr
tf
OUT
1.2V
OUTPUT RISE & FALL TIME FIGURE2
tpw,OUT
tpw,IN
tpw,IN
ISOLATION INTERFACE TIMING FIGURE3
5-330
APPLICATIONS INFORMATION UNDERVOLTAGE LOCKOUT and SOFT START
When power is first applied to the UCC1883, CsTAAT is held at Vss until Vcc exceeds 9.0V and VDD exceeds 4.4V. During this period of UVLO, the following state exists:
1) CsTAAT is held low,
2) OUT is held low,
3) VREG
is forced to Vee until Vee> 4V, and
4) VuMIT becomes a high impedance output.
Once adequate operating voltages have been established, the input current limit function is enabled. CsTART and OUT are still held low until the voltage on the VuNE pin exceeds 1.2V, indicating ample voltage is stored on the converter's bulk filter capacitor. At that time, CsTAAT is released and allowed to charge from an internal 25uAcurrent source. The UCC 1883 then begins to transfer energy to the secondary side of the converter by pulse width modulating the ramp voltage on CT against the charging voltage on CsTARr During this soft start period, all faultfunctions, pulse-by-pulse current limiting, and input current limiting are enabled. Note that the dV/dt established at the converter output by the positive dV/di of CsTAAT must be strictly less than the dV/dt established on the UCC1885 SOFTREF pin, if secondary-side soft start is utilized. The UCC 1883 continues the blind soft start procedure until the first set of communication pulses is received from the secondary side via the isolation interface. At that time, all control of the power switch is effectively transferred to the secondary-side regulation IC. Should communication
UCC1883 UCC2883 UCC3883
pulses never be received, or should they be discontinued during operation, blind PWM operation continues with the output pulse width limited by the internal 50% duty cycle clamp or pulse-by-pulse current limit with all fault processing enabled.
USER BIAS PROGRAMMING
The R81As pin may be used to set the amount of quiescent current consumed by certain analog circuits within the UCC1883. A resistor from this pin to Vss establishes a reference current according to the equation
IBIAS = 1.2V RBIAS
Recommended range for R81As is 39.2 Kn to 392 Kn. Internal circuits on the UCC1883 consume a total quiescent current of 9 · 181As' plus some fixed currents amounting to about 85uA at room temperature. Additional dynamic current consumption may be calculated with CPD (see specifications), given a certain oscillator frequency lose· from the equation
c v !DYNAMIC = PD · f CC · OSC
9.5V LINEAR PRE-REGULATOR
The UCC 1883 contains a control amplifier, which when used with a depletion-mode NMOS pass transistor such as the
J Vee 0
CsTART
J CT 0
J OUT 0
FB
1 0 r-- UVLO
' '
:
{SHOWS RANGE
'
OF POSSIBLE
. . - OUTPUT PULSE
WIDTHS
BLIND SOFT START
PEAK CURRENT _ _ _ _ _ ____,___ MODE REGULATION -
50% D.C. MAX
START UP WAVEFORMS FIGURE 4 5-331
UCC1883 UCC2883 UCC3883
BSS129, can provide a 9.5Vlinearpre-regulatorto supply Vcc directly from the input line. The depletion-mode device guarantees the regulator is self-starting. Bypass values less than 3.3uF are recommended w.hen the pre-regulator is utilized. The pre-regulator may subsequently be fully disabled by a tertiary bootstrap winding providing a minimum of 10.6Vtothe Vee pin. Note that the UCC1883 has 2Vof UVLO hysteresis to allow use of more conventional startup circuitry, if the power consumption of such implementations can be tolerated. In these cases, any value of bypass capacitance is acceptable, although a minimum value of 0.01uF is recommended for all configurations.
INPUT CURRENT LIMIT PROGRAMMING
The UCC1883 also incorporates the necessary control ampli-
fier and current reference to implement a continuous input
current limit mask conforming to CCITT recommendation
1.430. When using this feature, the ratio of a sense and
programming resistor determine the magnitude of the current
passed by an external PMOS transistor. The PMOS device
must be able to withstand the maximum input voltage seen by
the converter, and its R0 " will cause some reduction in efficiency during normal operation, due to conduction losses.
Referencing the application diagram of figure 7, the control
amplifier programs a peak input current according to the
equation
ILIMIT= (~ +1)·0.4
Rs
RBIAS
by moving the gate of the external PMOS device until equal voltage is impressed across RP and Rs. In addition to the input capacitance of the PMOS pass device, some compensation capacitance from VLIMIT to Vss may be required. However, too much capacitance on VLIMIT will increase the inrush current response time beyond that allowed by recommendation 1.430. A total capacitance of between 330pF and 2.2nF is recommended. A shunt bleeder resistor should be added across the PMOS pass transistor to facilitate converter startup. Due to the large· values of resistance which will typically be encountered, a 1OpF speedup capacitor across RP is suggested to help maintain good phase margin in the control loop. A clamping diode across Rs improves transient response by preventing excessive error voltage from being stored on the RP speedup capacitor during VLIMIT slewing. Finally, a 12V zener clamp from VLIMIT to Vss is recommended to protect the gate of the PMOS device from over voltage and to limitthe voltage slew which must occur before enteringthe current limit state. During normal converter operation, when less than the programmed current limit is being drawn from the line, the control loop opens and VUMIT moves to its maximum negative value, effectively turning the PMOS limit transistor into a series switch.
If a more accurate current reference than that supplied by the UCC 1883 is desired, a precision resistor may be wired from an appropriate reference voltage to 11". Since 11" is held at Vss
1000~~~~--y-~~,.--~~~~~~--.-.-.~~~---.~~.,--~.---,----,--,--,-,--,
S=100pF
~
ICC (uA)
10.0
100.0
1000.0
RaiAs (Kohms)
AVERAGE DC CURRENT VS. R81AS (V00= 12V) NOT INCLUDING POWER SWITCH GATE CURRENT FIGURES 5-332
(ground) by the current limit control amplifier, the additional current created in this case is equal to the reference voltage divided by the external resistor. A reference of at least 2V is recommended to decimate errors caused by the input offset voltage of the control amplifier. Because the reference current provided by the UCC 1883 still sums into the l,N pin, a minimum external reference current value of 4V/R81As is recommended to minimize errors caused by the initial tolerance of the internal current reference.
FAULT HANDLING
Three fault conditions which immediately disable the output are detected by the UCC1883 housekeeping circuitry. These are:
1) UVLO, 2) 1.5V or higher on the lsENsE pin, and 3) 1.5V or higher on the COL integrator pin.
Unlike the pulse-by-pulse current limit comparator, no leading edge blanking is applied to the over current fault comparator, which has a nominal 1.5V threshold. A capacitor to V55 may be used on the C0 L pin to program the output overload fault integrator. The polarity of the 2.2uA current sourced by the internal circuitry driving the C0 L pin potentially changes on each falling edge of OUT. If the output pulse was
UCC1883 UCC2883 UCC3883
terminated as the result of a peak current event, then current is sourced to C0 L, otherwise current is sunk from COL to Vss· If the voltage on C0 L ever reaches 1.5V, a fault condition is set.
If any fault condition is detected once UVLO has ended, the fault is latched and a restart delay elapses before a soft start is attempted. This delay is normally controlled by an internal 1uA discharge of the CsTART pin from V00 to 0.2V. If a fault occurs during soft start, the output is immediately disabled, but CSTART is fully charged (4.8V) before a restart delay begins. A fixed restart delay to soft start timing ratio of 25 :1 may be obtained with only acapacitorfrom CSTART to Vss· This ratio may be decreased by adding an external resistor between CSTART and Vss· The value of this resistor should be greaterthan the value of the current programming resistor on the R81As pin.
ISOLATION INTERFACE
In addition to receiving synchronization and duty cycle control information from the secondary side of the converter, the UCC1883 isolation interface also transmits digital status information to the secondary side. This digital information reflects the state of two internal analog comparators which monitor the VLINE and IMooE pins. A voltage of less than 1.2V on VLINE is indicated by atrue LOLINE bit, and an input current
BSS129, OR EQUIV.
n.-s-TERTIARY
LJ WINDING
1µF
·
13V 9.5V
UCC1883
9.5V PRE-REGULATOR APPLICATION FIGURE 6
5-333
of less than 2uA into the IMooe pin is interpreted as a true RSMODE (restricted power mode) condition. These digital bits are transmitted across the isolation barrier and appear as outputs on the UCC1885 secondary-side regulation IC. Recall that no UCC1883 output will occur until a voltage greater than 1.2V is initially established on VuNe·
vDD LOGIC SUPPLy
The internal CMOS logic on the UCC1883 runs from a regulated 5Vwhich is available externally atthe V00 pin. This pin should be bypassed to Vss with a high quality ceramic capacitor having a value of at least 0.01 uF. Values in excess of 1OuF are not recommended.
OSCILLATOR
A timing capacitor is connected between CT and Vss to program a natural oscillator frequency according to the equation
f
0.72
osc;~
T BIAS
A ramp voltage running from Vss to 2.5V is created on the CT pin. This oscillator is automatically synchronized to the
UCC1883 UCC2883 UCC3883
secondary-side clock frequency when data communication occurs across the isolation interface. Proper synchronization will only occur if the frequency of the secondary-side clock exceeds the natural frequency of the UCC 1883 oscillator. A new oscillator cycle (ramp returns to V55) will be initiated on the rising edge of each positive isolation interface input pulse, with a corresponding decrease in ramp amplitude. The UCC1883 is designed so that the dV/dt established on its CT pin will be nominally the same as that of the UCC1885 CT pin, if equivalent components are used on the R8,AS and CT pins of both devices. However, the natural frequency of the UCC1883 oscillator will automatically be lower, to allow synchronization. Proper CT ramp slope is important to the UCC1883, because it uses this information, along with the pulses received over the isolation interface, to reconstruct the analog output of the UCC1885 voltage error amplifier. This reconstructed voltage is in turn used to control the peak current mode PWM. The ratio of the slope of the UCC1883 timing ramp to the UCC1885 timing ramp sets the gain applied by the UCC 1883 to the UCC 1885 error amplifier output.
Other variations of the UCC1883 implementing voltage mode control, duty cycles greater than 50%, or faster natural oscillatorfrequencies may be available. Contact the factory for further information.
SWITCHER
10pF
Cc Rs
UCC1883
INPUT CURRENT LIMIT APPLICATION FIGURE7
5-334
UCC1883 UCC2883 UCC3883
l lsENSE
OJ
1111lllllllllllllllll1111111lllllllllll-1
2 .
v
~~_,....~......~1"~~i;~11111-_11.~5V~v~--+,-1-.5V:~~
I
I
I
I
I
I
I
I
I
CsTART51V ·---------~
I
5.,ov
r- --..r-- OUTPUT OVERLOAD INTEGRATION
t
RESTART DELAY
OVERLOAD FAULT
0.2V
~ SOFT START
~
t
PRIMARY
CURRENT FAULT
RESTART DELAY
-f-aESTAf!.r_ DELAY
t
PRIMARY CURRENT
FAULT
FAULT WAVEFORMS FIGURES
fosc(KHz)
10.0
100.0
RBIAS (Kohms)
OSCILLATOR FREQUENCY VERSUS RBIAS FIGURE 9
5-335
1000.0
:a:;;
ai
V+
VuNE
V-
IMODE
~
"O">''
UCC1883 UCC2883 UCC3883
,. :aw::E: ~"!a!:
~~
a:g<->::E::,''·,'''''''IaOo><z~:
''I"'
I I I
TYPICAL APPLICATION CIRCUIT FIGURE 10
UNITRODE INTEGRATED CIRCUITS
7 CONTINENTAL BLVD.· MERRIMACK, NH 03054 TEL 60:J.424-2410· FAX 6CXM24·3480
n n l_=:J
INTEGRATED CIRCUITS
-UNITRODE
Micropower Secondary Regulation IC
UCC1885 UCC2885 UCC3885
ISDN 1.430 RELATED FEATURES · Secondary-Side Voltage Sense for
Improved Regulation · Restricted Mode Status Output · Precision Programmable Quiescent
Current · Very Low Quiescent Power for CCITT
25mW Restricted Mode
GENERAL FEATURES · Wide Supply Voltage Range · Precision 2.0V Reference · Low Offset, High Gain Error Amplifier · Temperature Stable Oscillator · Logic Level Oscillator
Synchronization · Low Line Status Output · Under Voltage Lockout · Programmable Secondary-Side Soft
Start · 5V Vdd Logic Supply Regulator
BLOCK DIAGRAM
DESCRIPTION The UCC1885 supplies the necessary functions to implement a fully isolated, ISDN compatible SMPS meeting the guidelines of CCITT recommendation 1.430, when used in conjunction with the UCC1883 primary-side PWM controller. The UCC1885 secondary-side regulation IC provides improved regulation by allowing direct sensing of the output voltage on the secondary side of the DC/DC converter. The UCC1885 contains a precision system reference and a complete error amplifier. The output of the amplifier serves as the PWM control voltage and is provided to the primary-side via
an isolation pulse transformer. The UCC1885 also sends synchronization information to the primary-side with this transformer. Under voltage lockout circuitry operates in combination with the user programmable soft start function to prevent transmission of data across the isolation barrier until adequate secondary-side operating conditions are established.
ISDN specific features allow the UCC1883/UCC1885 combination to be compatible with CCITT recommendation 1.430. The UCC1885 receives two digital bits of status information from the UCC1883 via the isolation pulse transformer. These bits. which indicate restricted power mode and low input line voltage, are output on the secondaryside at CMOS logic levels. Precision programming of the quiescent
current used by the UCC1885 allows the system to meet the 25mW restricted mode power limit, or the current can be set to achieve higher operating frequencies at the cost of increased power
consumption.
The UCC1885 is fabricated in Unitrode's 3µm BiCMOS process. Even
though the device contains internal clamping diodes on all pins,
the part should still be considered static sensitive. Normal ESD
handling procedures for CMOS devices should be observed when using
the UCC1885.
.
Vee 1 4 > - - - - - - - - - e - - - - - - - ,
SOFT REF
2V REFERENCE
UVLO
LOGIC SUPPLY t-s~v-----r-t-t----i 13 Voo
REGULATOR
:czJJ
3/93
PWM LOGIC
UT
ISOLATION INTERFACE
TO ANALOG CIRCUITS
1.2V
~ GND
5-337
ABSOLUTE MAXIMUM RATINGS Analog Supply Voltage (Vccl ........................................... 18V Maximum V~ Slew Rate ............................................3V/mS Digital Supp1y Voltage (V00) 7V ···········.······.···········.·.··.·········· Maximum Voltage, All Signal Pins .............. V00 + 0.3V to 7V Minimum Voltage, All Pins ..........................................- 0.3V Maximum DC Current, Any Pin, Source or Sink ........ 1OOmA Maximum Peak Current, Any Pin, Source or Sink ..... SOOmA Total Package Dissipation (N package) ........................... 1W Total Package Dissipation (D package) .................... 800mW Storage Temperature ................................- 65°C to+150°C Lead Temperature (Soldering, 1Oseconds) ....,......... +300°C
Note 1: All voltages expressed with respect to pin 10, currents are positive into the specified terminal.
Note 2: All maximum signal pin voltage limits apply for cases of zero source impedance. Higher or lower voltages may be impressed through a finite source impedance which causes the input current to be limited to the values specified, with total package power dissipation at or below specified limits.
Note 3: Consult Packaging Section of Databook for thermal limitations and considerations of package.
UCC1885
UCC2885
CONNECTION DIAGRAM
UCC3885
DIL-14, J or N Package, SOIC-14, D-Package
Re1AS SOFT REF VAIN+ VAINVA OUT Cr LOLINE
Vee
Voo RS MODE FB+ GND FBSYNC
Pin Number
Pin Name
Pin Type
Function
1
RBIAS
Analog Program
Quiescent Bias Current Set
2
SOFTREF
Analog Program & Output
Soft Start Timing Set and 2.0V Reference Output
3
VAIN+
Analog Input
Voltage Error Amplifier Non-Inverting Input
4
VAIN-
Analog Input
Voltage Error Amplifier Inverting Input
5
VA OUT
Analog Output
Voltage Error Amplifier Output
6
CT
Analog Program
Oscillator Frequency Set
Low Primary-Side Line
7
LOLINE
Digital Output
Voltage Status Bit (High =
True)
8
SYNC
Digital Input
Oscillator SYNC (PositiveEdge Triggered)
9
FB-
Digitall/0
Differential Feedback Commu,nication Signal (-)
10
GND
Supply Return
System Ground
11
FB+
Digital 1/0
Differential Feedback Communication Signal(+)
12
RSM ODE
Digital Output
CCITT Restricted Power Mode
Status Bit (High =True)
13
voo
Logic Supply
5.0V Internal Regulator C:..utput or Logic Supply Input
14
Vee
Power Supply
Analog Power Supply Input
5-338
ELECTRICAL CHARACTERISTICS Unless otherwise noted, all specifications apply for TA -55°C to + 125°C for the UCC1885; -40°C to +85°C for the UCC2885; 0°c to +70°C for the UCC3885 Vee= V00 = SV, SYNC = OV, R81As = 200Kohms, Ct= 100pF, and TJ = TA(min) to TA(max)
UCC1885 UCC2885 UCC3885
PARAMETER UVLO Section Vcc Start Threshold Vcc Threshold Hysteresis VDD Start Threshold VA OUT Run Threshold Reference Section Reference Voltage Line Regulation Load Regulation
Total Reference Variation
Soft Start Current External Override Threshold Input Bias Current User Bias Section R01,s Voltage R01As Pin Line Regulation Total R..,. Pin Variation Error Amplifier Section Input Common Mode Range Input Offset Voltage Input Bias Current VA OUT Low Level
VA OUT High Level
VA OUT Short Circuit Current
Open Loop Voltage Gain
DC PSRR
DC CMRR
Unity Gain Bandwidth
Open Loop Output Impedance
VA OUT Slew Rate
Oscillator Section Initial Accuracy Voltage Stability Total Oscillator Variation Cr Ramp Amplitude SYNC Input Low Voltage SYNC Input High Voltage
TEST CONDITIONS
VDD= Vee VDD =Vee VDD <Vee VA OUT= VA IN(-)
Tj = 25°C, Rload > 50Mohm 3V < Vcc < 16.5V -500nA < lout < 500nA Initial+ Line+ Temperature Rload > 50Mohm SOFTREF = OV
SOFTREF = 5V
Ti= 25°C 3V <Vee< 16.5V Initial + Line + Temperature
VA OUT= 1V VA IN(+)= 2V, VA OUT= 1V VA IN(+)= 2V, VA OUT= 1V Vdm = -1 OmV, lout= 700uA R01,s = 200K, Vdm = 1OmV, lout = - 50uA R01,. = 39.2K, Vdm = 1OmV, lout= - 250uA VA OUT= OV, R01,s = 39.2 Kohms Vern= 2V, 0.1 <VA OUT=< 2.0V R01,. = 39.2 Kohms Vern= 2V, 0.1 <VA OUT= 1V RBl·s = 39.2K, 3V < Vee < 16.5V VA OUT= 1V, R.,,s = 39.2K 1V<Vcm<4V R..,. = 200 Kohms, Cout = 25pF (Note 1) R..,. = 39.2 Koh ms, Cout = 25pF (Note 1) R01,. = 200K (Note 1) R0,.s = 39.2K (Note 1) RBIAs = 200K, Cout = 25pF (Note 1) R01, 5 = 39.2K, Cout = 25pF (Note 1)
TJ = 25°C 3V<Vcc=VDD<7V lnital + Line +Temperature
Min Typ Max Units
2.4
2.7
3.0
v
260
400
600
mV
2.0
2.4
2.9
v
1.0
1.15
1.3
v
1.98
2
2.02
v
-
2
10
mV
-
12
35
mV
1.96
-
2.04
v
4
10
16
uA
-
-
2.45
v
-
-
50
nA
1.17
1.2
1.23
v
-
8
30
mV
1.15
-
1.25
v
1
-
4.5
v
-8
-
8
mV
-100
-
100
nA
-
0.05
0.15
v
2.0
2.6
-
v
2.0
2.7
-
v
-0.4
-1
-5
mA
80
110
-
dB
70
110
-
dB
70
100
-
dB
375
500
-
KHz
1.6
2.2
-
MHz
-
2.2
3.3 Koh ms
450
675 ohms
140
250
-
mV/us
0.7
1.25
-
Vius
42
48
-
1
41.5
-
1.65
1.8
-
-
3.5
-
56
KHz
3
%
58
KHz
1.9
v
1.5
v
-
v
5-339
ELECTRICAL CHARACTERISTICS : Unless otherwise noted, all specifications apply for TA -55°C to + 125°C UCC1885
v for the UCC1885; -40°C to +85°C for the UCC2885; 0°c to +70°C for the UCC3885 Vee= 00 = 5V, SYNC
UCC2885
= OV, R0,.s = 200Kohms, Ct= 100pF, and TJ = TA(min) to TA(max)
UCC3885
PARAMETER
TEST CONDITIONS
Min
Typ
Max
Oscillator Section (Continued) Maximum SYNC Rise, Fall Time
(See Figure 1 and Note 1)
500
-
-
Minimum SYNC Pulse Width
(See Figure 1 and Note 1)
10
15
nS
Isolation Interface Section FB Output High Voltage FB Output Low Voltage
Rload = 500 ohms
Rload =50 ohms to 5V
4.0
4.5
-
-
0.5
0.85
FB Output Pulse Width
FB Output PW Matching Minimum FB Input Pulse Width Digital Status Output High Digital Status Output Low
R.,·· = 200 Kohms (See Figure 2)
= R.,·· 39.2 Kohms (See Figure 2)
(See Figure 2 and Note 1) LOLINE, RSM ODE, lout = - 200uA LOLINE, RSMODE, lout = BOOµA
200
300
450
-
100
-
-
15
-
-
10
-
4.85
4.95
-
-
0.3
0.45
VDD Regulator
VDD Output Voltage VDD Line Regulator VDD Load Regulation VDD Regulator Dropout VDD Short Circuit Current Power Supplies DC Supply Current Cpd
VDD < Vcc· No External Load 7V <Vee< 16.5V - 3mA < lout < Orn A No Ex1ernal Load
VDD = ov
(Note 2)
4.75
5
5.25
-
10
50
-
100
250
-
0.9
1.7
8
30
70
-
100
150
-
150
-
Notes: 1. This parameter not 100% tested in production, but guaranteed by design.
2. Total power dissipation will be determined by associated isolation pulse transformer characteristics. A pulse transformer with a low loss core and at least 50µH of magnetizing inductance is strongly recommended.
Units
nS
v v
ns ns ns ns
v v
v
mV mV
v
mA
uA pF
SYNC FB+ or FB-
t,
OSCILLATOR SYNC TIMING
FIGURE 1
tpw,our
FEEDBACK 1/0 TIMING
FIGURE2
5-340
APPLICATIONS INFORMATION
UCC1885 UCC2885 UCC3885
UNDER VOLTAGE LOCKOUT
When power is first applied to the UCC1885, SOFTREF is
held at ground until Vcc exceeds 2.8V and VDD exceeds 2.4V. Once adequate operating voltages have been established, SOFTREF is released and allowed to charge from an internal 1OuAcurrent source. A capacitor from this pin to ground may be used to continue an output soft start after the UCC1885 takes control of the SMPS with feedback communication to the UCC1883. Inthis case, the dV/dt established on SOFTREF must exceed the dV/dt established on the regulated output by the blind soft start being provided by the UCC 1883. Normally the SOFTREF pin will charge to 2.0V, the value of the internal precision reference. Once the internal reference voltage is reached, the current source is disabled andthe SOFTREF pin maintains an output impedance of 30Kn, which, acting with
any soft start capacitance, will then form a single-pole reference noise filter.
If the use of an external reference (VREF> 2.5V) is desired, the soft start function can still be maintained on SOFTREF. In this case, the user must also supply a soft start resistor between the external reference and SOFTREF. The value of this resistor should be chosen such that the current sourced into the SOFTREF pin when the voltage reaches 2.0V is at least 20uA, which will allow the UCC 1885 to sense the presence of an external reference. Once the external reference is sensed, the internal reference is disconnected from SOFTREF, making it high impedance and eliminating any DC error across the soft start resistor. The minimum value of the soft start resistor
Vee
VDD
2.4 -
2 - - -1- - - - - - - - - - - -
I I
SOFT REF
~!!l!.=~
di
0sTART
TIME
SOFT START WITH INTERNAL REFERENCE FIGURE3
Rs TART 20KO
SOFT REF
CsrART
I
4
SOFT REF Voo
TIME
SOFT START WITH EXTERNAL REFERENCE FIGURE4 5-341
1000~--~-J'o-1..~~~~~~---~-~~~~~~
t-----t-~-ct""17pF ~
' II Ct· 100pF
la:(uA)
UCC1885 UCC2885 UCC3885
100+------'----'---'-'--'---'--'-'-+-----'----'---'-'--'--'--'"--'-l
10.0
100.0
1000.0
RalAS (Kohms)
AVERAGE DC CURRENT VERSUS R81AS (Not including Pulse Transformer Loses) FIGURES
should be limited to allow SOFTREF to pull low during UVLO. The output impedance of SOFTREF during this phase of operation is about 300 ohms to ground.
The final portion of the UCC1885 UVLO sequence occurs when the output of the error amplifier increases above 1.15V. Normally this will not occur until the system reference has charged to some intermediate value. Assuming that adequate operating voltage has also been established, then the isolation interface on the UCC 1885 begins transmitting output pulse width control information to the UCC 1883 via an isolation pulse transformer. The 1.15V required on the output of the error amplifier guarantees that the UCC1885 will initially begin transmitting information to the primary-side
PWM controller which keeps energy flowing to the secondary allowing the control loop to come into regulation. Once the isolation interface is enabled, the UVLO circuitry ignores all voltages appearing on the output of the error amplifier.
USER BIAS PROGRAMMING
The R81AS pin may be used to set the amount of quiescent current consumed.. by certain analog circuits within the UCC1885. A resistor from this pin to ground establishes a user bias current according to the equation
IBIAS = 1.2V
RBIAS
10K
30K
100K
300K
1.0M
3.0M
10M
Frequency (Hz)
ERROR AMPLIFIER GBW VERSUS RBIAS FIGURE&
5-342
C1·100pF 1'
""'
UCC1885 UCC2885 UCC3885
10
100
1000
A BIAS (Kohms)
OSCILLATOR FREQUENCY VERSUS RBIAS FIGURE7
Recommended range for R81AS is 39.2 Kn to 392 Kn. Internal circuits on the UCC 1885 consume a total quiescent current of 9 · 18,AS, plus some fixed currents amounting to about 50uA at room temperature. Additional dynamic current consumption may be calculated with CP0 (see specifications), given a certain oscillator frequency fosc· from the equation
lovNAM1c= Cpo · Voo · fosc
special circuitry on the UCC 1885 guarantees VA out will be very near ground to insure proper startup.
OSCILLATOR
A timing capacitor is connected between CT and ground to program a natural oscillator frequency according to the equation
Also note from the specifications that the voltage on R01N> is well controlled and thus may be effectively used as anotner reference voltage in the system.
vDO LOGIC SUPPLy
The internal CMOS logic on the UCC1885 requires a supply limited to 7V. If the value of Vcc is anticipated to be below 7V, then V00 should be wired directly to Vcc and bypassed with at least 0.01uF. If Vee exceeds 7V, the UCC1885 provides an internal 5V regulator to the V00 pin for running the onboard CMOS logic. Atthese higher Vcc voltages, the V00 pin should be disconnected and bypassed with at least O.01 uF. Forthis
case of internal regulation, v00 bypass capacitance should
not exceed 10uF.
ERROR AMPLIFIER
fosc=---Cr· R01As
A ramp voltage running from ground to 1.av is created on the
CT pin. This oscillator may be synchronized to a system clock applied to SYNC. Proper synchronization will only occur if the frequency of the SYNC signal exceeds the natural frequency programmed into the oscillator. A new oscillator cycle (ramp returns to ground) will be initiated on each rising edge of SYNC, with a corresponding decrease in ramp amplitude. SYNC should be wired to ground if this feature is not used. The ramp amplitude represents the maximum value of error amplifier output voltage which may be passed over the isolation interface to the UCC1883. Thus a minimum synchronized ramp amplitude of 1.3V is recommended. The UCC 1885 will accept a wide range of duty cycles on the SYNC pin, but rise and fall times of longerthan 200ns are not recommended.
The UCC1885 error amplifier is intended to be the control amplifier for the voltage loop of the ISDN SMPS. It is a low
offset, high gain design. Output swing is typically limited to a maximum of 2.7V. The GBW of the amplifier is controlled
by the value of R01AS supplied by the user on pin 1. Input common mode range is between 1V and Vee - 0.5V. If both inputs are beneaththe common mode range during soft start,
5-343
UCC1885 UCC2885 UCC3885
2-
0 SYNC
FLYBACK OUTPUT STAGE
h
OSCILLATOR WAVEFORMS FIGURES
6.2V 0.1µF
I I
lh ~
+5VOUT
OUTPUT GROUND
PRIMARY ""4.._..;-_._. SECONDARY
VA OUT VAINVAIN+
SOFTREF
"'CIO
CIO
0
(.) ::::i
LOLINE
SYNC
TO UCC1883
RBIAS Cr
1 :1 50µH
UNITRODE INTEGRATED CIRCUITS
7 CONTINENTAL BLVD.· MERRIMACK, NH 03054 TEL. ~2410 · FAX 603-424-3460
TYPICAL APPLICATION FIGURE9
1µF 3011<n 200KO
RESTRICTED MODE LOW LINE
SYNC
iTU\i ~.~.. ~ lndicates_Applicatian Nate Available ~~, See Section 9.
Intelligent Motion Circuits
n n INTEGRATED
~CIRCUITS
-UNITRODE
6-2
n n INTEGRATED
~CIRCUITS
-UNITRODE
Product Selection Guide
INTELLIGENT CONTROLS AND MOTOR CONTROL DESIGNERS GUIDE
PERFORMANCE CHARACTERISTICS
Linear
PWM
Fixed off-time
Fixed Frequency
Transconductance Ampl.
Low Noise
Number of Totem Pole
4 4
2
Outputs
Over 0.5A Output
Includes Output Diodes
Reversible Direction
Microstepping Capability
Hall Logic
Full-Step/Half-Step Logic
Phase-Lock Speed Control
Four Quadrant Output
Current Sense Capabillty
Brake Function
Tri-stable Outputs
Thermal Protection
Undervoltage Lockout
Driver Only: TTL Inputs
Note C: Also includes 3175, 3176, 3177, 3178, 3173A
6-3
n nINTEGRATECI
~CIRCUITS
-UNITRODE
Product Selection Guide
INTELLIGENT CONTROLS AND MOTOR CONTROL DESIGNERS GUIDE (Cont'd)
L
UNITRODE PART NUMBER
J
PERFORMANCE CHARACTERISTICS
APPLICATIONS A Unipolar Bi level Stepper Bipolar Stepper Three-Phase Brushless Two-Phase Brushless PWM Servo Solenoid Relay Voice-Coil
···················
STANDARD PACKAGE8
16-Pin Batwing
E 'I
f-----"-----+'=P£l:
16-Pin DIL
18-Pin DIL
20 Pin PLCC
24-Pin DIL
28-Pin Power PLCC
28-Pin DIL
5-Pin T0-220
16-Pin Power Ceramic
24-Pin Power Ceramic
PHILLIPS STYLE PACKAGE (Power OIL)
48QFP (Quad Flat PAC)
48QFP (Power)
Note A: See Application Section for more Note B: Alternate Packaging Available Note C: Also includes 3175, 3176, 3177, 3178, 3173A
6-4
:··········I
n n INTEGRATEC
~CIRCUITS
-UNITRODE
Product Selection Guide Intelligent Controls and Motor Control CROSS APPLICATION CHART
NOTE: It is often possible - and advantageous - to fit into one application an IC that was originally designed for another. Here are a few hints:
UNITRODE PART#
BRUSH SERVOMOTOR
STEPPING MOTOR
L293, 2930 UC2950 UC3173A, 4, 5,6,7,8 UC3517 UC3610,11,12 UC3620,22,23 UC3633,34 UC1657 UC3637 UC3717,17A UC3770A,B
MICRO· STEPPING
BRUSHLESS 10 30
VOICE COIL
SOLENOID
6-5
n n L:::::'.J
INTEGRATED CIRCUITS
-UNITRCCE
Push-Pull Four Channel Driver
L293 L293D
FEATURES Output Current 1A Per Channel (600mA for L293D)
Peak Output Current 2A Per Channel (1.2A for l293D)
Inhibit Facility
High Noise Immunity
Separate Logic Supply
Over-Temperature Protection
DESCRIPTION The L293 and L293D are quad push-pull drivers capable of delivering output currents to 1A or 600mA per channel respectively. Each channel is controlled by a TTL-compatible logic input and each pair of drivers (a full bridge) is equipped with an inhibit input which turns off all four transistors. A separate supply input is provided for the logic so that it may be run off a lower voltage to reduce dissipation.
Additionally the l293D includes the output clamping diodes within the IC for complete interfacing with inductive loads.
Both devices are packaged in 16-pin plastic and ceramic DIPs; both use the four center pins to conduct heat to the printed circuit boards. A 28-pin Power SOIC package is also available.
TRUTH TABLE
V1
VINH*
Vo
leach channe_!l_
H
H
H
L
H
L
H
L
X**
L
L
X**
*Relative to the considered channel
*"High output impedance
BLOCK DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Collector Supply Voltage, Ve ............................... 36V Logic Supply Voltage, Vss ................................. 36V Input Voltage, VI .......................................... N Inhibit Voltage, VINH ....................................... N Peak Output Current (Non-Repetitive). louT (L293) ............... 2A
IOUT (L293D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2A Total Power Dissipation
atTground-pins = 80°C, N pkg, (Note). . . . . . . . . . . . . . . . . . . . . . 5W Storage and Junction Temperature, Tstg, TJ ........... -40 to +150°C Note:Consult packaging section of Databook for thermal limitations and considerations ofpackage.
vc
Note: Output diodes are internal in l293D. 01/93
6-6
CONNECTION DIAGRAMS
DIL-16 (TOP VIEW) J or N Package
SOIC-28 (TOP VIEW) J or N Package
L293
L293D
vss
INPUT 4 OUTPUT 4 N/C N/C N/C GND
ELECTRICAL CHARACTISTICS: (For each channel, Ve= 24V, Vss = 5V, TAMB = 25°C, unless otherwise specified; TA= TJ)
PARAMETER Collector Su~y Voltage LoJl!c Su~ Voltage Collector Supply Current
Total Quiescent Logic Supply Current
Input Low Voltage Input High Voltage
Low Voltage l'!e_ut Current High VoltaJ!!.l'!e..ut Current Inhibit Low Voltage Inhibit High Voltage
Low Voltage Inhibit Current High Voltage Inhibit Current Source O~ut Saturation VoltaJ!..e Sink Out~ Saturation Volta_g_e Clamp Diode Forward Volta_9..e (L293D only) Risellme Fallllme Tum-on Delay Turn-off Delay
SYMBOL
TEST CONDITION
Ve
vss
le
VI = L, lo = 0, VINH = H
VI = H, lo= 0, VINH = H
VINH= L
lss
VI = L, lo = 0, VINH = H
VI= H, lo= 0, VINH = H
VINH = L
VIL
VIH
VSS"7V
Vss;i:7V
llL
Vl=OV
llH
VI =4.5V
VINH,L
VINH,H VSS"7V
Vss>7V
VINH,L
V1NH,H
VeEsatH lo= -1A (-0.6A for L293D)
VeEsatL lo = 1Aio.SA for L293D_l
VF
IF =0.6A
TR
0.1 to 0.9 Vo (See Figure 1)
TF
0.9 to 0.1 Vo (See Figure 1)
TON
0. 5 VI to 0.5 Vo (See Figure 1)
TOFF 0. 5 V1 to 0.5 Vo (See Figure 1)
MIN. 4.5
-0.3 2.3 2.3
-0.3 2.3 2.3
TVP.
2 16 44 16 16
30
-30 1.4 1.2 1.3 250 250 450 200
MAX. UNITS
36
v
36
v
6
mA
24 mA
4
mA
60 mA
22 mA
24 mA
1.5
v
Vss v
7
v
-10 _!AA
100 µA
1.5
v
Vss v
7
v
-100 µA
10 µA
1.8
v
1.8
v
v
ns
ns
ns
ns
6-7
SCHEMATIC DIAGRAM
L293 L293D
APPLICATION INFORMATION
..
~---~
-tr
.---i -"'I 0.9Vo
I +!;Ir--· ____,. ---1 k: 0.5Vo
R t+-t; ~ ~V~o_41,'11<T1--,-- - - ---t- __, µii. 0.1Vo l+-tR
-tt--j4-tON
l+--j4-tOFF
Figure 1: Switching Times
!
1-Vc-24v+--1--+--1--1--l VI-Low T
50 1-VINH-Hlgh -+--+--+~j./1--1....-1
< 481--t-+--t--l::,..i.o~..-i+-+-~ .s 461--+-.,J.£.....-141-1__.+-I--!--+-+--+ IL J 441---4'-+--+--+--+--+-+--t
421--+-+--+--+--+--+-+--t
401--+--+--+--+--+--+-+--t
0 10 20 30
V11 - (V)
Figure 2: Quiescent Logic Supply Current vs Logic Supply Voltage
1 1.5 2 2.5
V1 - (V)
Figure 3: Output Voltage vs Input Voltage
T 1-.vc-I4v VINHIBIT·V88·5V 3 l--+--+--+--+--+--+--t--1
~
j' 2 t--+V..C,E-a,a~t ~H~-~ +--T--t--1
~ 1
.%Yvcesat L
::F-
0 0.5 1 1.5 lo - (A)
0 50 100 TAMB - ("C)
Figure 4: L293 Saturation vs Output Currrent
Figure 5: L293 Source Saturation vs Ambient Temperature
NOTE: For L293D curves, multiply output cuffent by 0.6.
Vc-24V I I
1-VINHIBIT·VBl·&V -+-+-'
~ 3 t--t--+--+-+--+--+--+--i
..:.
..
2 t--t-t-+-+-+--+--:r:ot-.-1.t-~-A;
W:
~
1 t:-l-=--t+-:--t+:--=+-tri:--.:1T1l0o~--10~A.5~A~
O .__.__._._._._1~....-..-°i.._1·A_,
-50 0 50 100
TAMB - ('C)
Figure 6: L293 Sink Saturation Voltage vs Ambient Temperature
6-8
APPLICATION INFORMATION Cont.
L293 l293D
v..
Figure 7: DC Motor Controls (with Connection to Ground and to Supply Voltage)
VINH A H H H L
L x
M1
B
Fast Motor Sto~ H
Run
L
Free Running Motor St~
x
M2 Run Fast Motor Sto~ Free Running MotorSto...e_
L =Low H =High X =Don't Care
Figure 8: Bidirectional DC Motor Control
INPUTS
FUNCTION
C=H·D=L
Tum R.!g!lt
VINH =H
C=L· D=H C=D
Tum Left Fast Motor Sto_!!_
VINH=L C=X;D=X
Free Running Motor Sto...e_
L=Low H=High X=Don'tCare
l ! 0.22µF C1
= 300mA
IL1 J·u -6
01 - 08 + SES5001 Figure 9: Bipolar Stepping Motor Control
6-9
L293 L2930
MOUNTING INSTRUCTIONS The Rthj-amp of the L293 can be reduced by soldering the GND pins to a suitable copper area of the printed circuit board or to an external heatsink.
The diagram of Figure 13 shows the maximum package power Ptot and the 8JA as a function of the side "t" of two equal square copper areas having a thickness of 35µ (see
Figure 1O). In addition, it is possible to use an external heatsink (see Figure 11).
During soldering the pins' temperature must not exceed 260°C and the soldering time must not be longer than 12 seconds. The external heatsink or printed circuit copper area must be connected to electrical ground.
COPPER AREA 35 µ. THICKNESS
\
P.C. BOARD
Figure 10: Example of P.C. Board Copper Area which is used as Heatsink
Figure 11: External Heatsink Mounting Example
= (8JA 2s0 cJW)
4 ~,..__..-+--+-+-+-+--+-+-+---! 80
. ~
3
~ 1--1('-J~..,.G~JA_+-+--+--+--+-+-1 60
"\-...
i'
O
b '
Ii:.
2
.-1'i----.-.l:
...., 40
I __.
VPToT (TAMB ·70° C) r-+-i 20
~ d
..l..L..l..L..l..L
0 0 ~~~~~~~~~~
0 10 20 30 40
SldeJ - mm
Figure 12: Maximum Package Power and Junction to Ambient Thermal Resistance
! __ 4 ,__,___,.........
' 3
2 ~
t--+--+--t--,_._~1----.---1
a.
0 50 100 TAMB - (°C)
Figure 13: Maximum Allowable Power Dissipation vs Ambient Temperature
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. · MERRIMACK. NH 03054 TEL. (603) 424-2410 ·FAX (603) 424-3460
6-10
n n L::::::_J
INTEGRATED CIRCUITS
-uNITRDDE
Dual Full-Bridge Power Driver
L298
FEATURES · Operating Supply Voltage up to 46V
·Total Saturation Voltage 3.4V max at lA
· Overtemperature Protected ·Operates in Switched and UR
Regulation Modes
· 25W Power-Tab Package for low Installed Cost
· Individual Logic Inputs for Each Driver
· Channel-Enable Logic Inputs for Driver Pairs
DESCRIPTION The L298 is a power integrated circuit usable for driving resistive and inductive loads. This device contains four push-pull drivers with separate logic inputs. Two enable inputs are provided for power down and chopping. Each driver is capable of driving loads up to 2A continuously.
Logic inputs to the L298 have high input thresholds (1.85V) and hysteresis to provide trouble-free operation in noisy environments normally associated with motors and inductors. The L298 input currents and thresholds allow the device to be driven by TTL and CMOS systems without buffering or level shifting.
The emitters of the low-side power drivers are separately available for current sensing. Feedback from the emitters can be used to control load current in a switching mode, or can be used to detect load faults.
Separate logic and load supply lines are provided to reduce total IC power consumption. Power consumption is reduced further when the enable inputs are low. This makes the L298 ideal for systems that require low standby current, such as portable or batteryoperated equipment.
ABSOLUTE MAXIMUM RATINGS
Power Supply, Vs ........................................... 50V Logic Supply Voltage, Vss .................................... 7V Input and Inhibit Voltage, V;, V;nhlbit ................ -0.3V to +7V Peak Output Current (each channel), lo
Non-Repetitive (t = lOOµs) ................................ 3A Repetitive (80% on - 20% off; toN = lOms) .............. 2.5A DC Operation ............................................ 2A Sensing Voltage, Vsens ............................. -1 V to +2.3V Total Power Dissipation (Tease= 75°C), Ptot ................ 25W Storage and Junction Temperature, Tstg, Ti ..... -40°C to +150°C
THERMAL DATA
Thermal Resistance Junction-Case, Rlh 1-case ........ 3°C/W max. Thermal Resistance Junction-Ambient, Rth j-amb .... 35°C/W max.
CONNECTION DIAGRAM
CURRENT SENSING B OUTPUT 4 OUTPUT 3 INPUT 4 ENABLE B INPUT 3 LOGIC SUPPLY VOLTAGE V,9 GROUND INPUT 2 ENABLE A
11==:::::=-. ~tt];,~Iv1voLTAGE v. OUTPUT 2 OUTPUT 1 CURRENT SENSING A
L TAB CONNECTED TO PIN 8
BLOCK DIAGRAM
OUT!
OUT2
Vs
OUT3
OUT4
SENSE A
GND
SENSE B
6-11
L298
ELECTRICAL CHARACTERISTICS (for each channel, Vs= 42V, Vss = 5V, T; = 25'C) TA=TJ
PARAMETERS
TEST CONDITIONS
MIN.
Supply Voltage (Pin 4), Vs
Operating Condition
V1H+2.5
Logic Supply Voltage (Pin 9), Vss
4.5
V;nh. = H
V; = L
Quiescent Supply Current (Pin 4), Is
IL= 0
V; = H
V;nh. = L
V;nh. = H
V; = L
Quiescent Current from Vss (Pin 9), lss
IL= 0
V; = H
V;nh. = L
Input Low Voltage (Pins 5, 7, 10, 12), V; L
-0.3
Input High Voltage (Pins 5, 7, 10, 12). V; H
2.3
Low Voltage Input Current (Pins 5, 7, 10, 12), I; L
V; = L
High Voltage Input Current (Pins 5, 7, 10, 12), I; H
V; = H
Inhibit Low Voltage (Pins 6, 11), V;nh. L
-0.3
Inhibit High Voltage (Pins 6, 11), V;nh. H
2.3
Low Voltage Inhibit Current (Pins 6, 11), l;nh. L
V;nh. = L
High Voltage Inhibit Current (Pins 6, 11), hnh. H
V;nh. = H ::; Vss -0.6V
Source Saturation Voltage, VcE satlHI
IL= lA IL= 2A
Sink Saturation Voltage, VcE satlLJ
IL= lA IL= 2A
Total Drop, VcE sat
Sensing Voltage (Pins 1, 15), Vsens Source Current Turn-Off Delay, T,(V;) Source Current Fall Time, T2(V;) Source Current Turn-On Delay, T3(V;) Source Current Rise Time, T4 (V;) Sink Current Turn-Off Delay, Ts(V;) Sink Current Fall Time, Ts(V;) Sink Current Turn-On Delay, T7(V;) Sink Current Rise Time, Te(V;)
IL= lA IL= 2A
0.5 V; to 0.9 IL121 0.9 IL to 0.1 IL121 0.5 V; to 0.1 IL'21 0.1 IL to 0.9 1Lt2l 0.5 V; to 0.9 IL131 0.9 IL to 0.1 IL'31 0.5 Vt to 0.1 IL'31 0.1 IL to 0.9 IL'31
-1 (1)
Commutation Frequency, fc
IL= 2A
1) Sensing voltage can be -lV fort S 50µS; in steady state Vsens min;;: -0.5V. 2) See figure la. 3) See figure 2a.
TYP.
3 15
5 1.5 1
30
30 1.2 1.8 1.2 1.7
1.7 0.2 2.5 0.35 0.7 0.2 1.5 0.2 25
MAX. 46 7 7 20 1 10 3 1.5 1.5 Vss -10 100 1.5 7 -10 100 1.8 2.8 1.8 2.6 3.4 5.2 2
40
UNITS
v v
mA
mA
v
µA
v
µA
v
v
v v
µS µs µS µs µS µ:, µS µS KHz
6-12
SWITCHING CHARACTERISTICS Figure 1. Switching times test circuits.
Vss =5V Vs= 42V
NOTE: For INPUT chopper, set EN = H.
Figure 2. Switching Times Test Circuits.
Vss = 5V
Vs= 42V
L298
Figure la. Source Current Delay Times vs. Input or Enable Chopper.
IL
lmax (2A) 1 - - - . . . . - - - - - - - - - - - - - ; ; - - - -
90%
10%
V;(4V) 50%
Figure 2a. Sink Current Delay Times vs. Input or Enable Chopper.
IL
114 L298
NOTE: For INPUT chopper, set EN = H.
APPLICATIONS Figure 3. Bi-Directional DC Motor Control.
+V,
01
03
02
04
10
13
14
12
+Vss
V;nh. = H
INPUTS C = H; D = L C = L; D = H C=D
V1nh. = L C = X; D = C
L =Low H =High X = Don't Care
FUNCTION Turn right Turn left Fast motor stop Free running motor stop
15
TO CONTROL CIRCUIT
01 TO 04: UES1101 OR EQUIVALENT OR UC3610 DIODE ARRAY
6-13
L298
Figure 4. Bipolar Step Motor Driver.
+5V VMOTOR
.lµF
r--1
lDK lOK lOK lOK
STEP DIRECTION FULL/HALF
CURRENT LIMIT CONTROL
16
UC3517 ENCODER
t-------+---t 10 l----_.--112
11
CURRENT SENSE RESISTORS
L298 DRIVER
131-+-----+-----+-r---t--<>
14t-+-----+-+-..--i--r----t--r-~
15
0 MOTOR
UC3610 DIODE
ARRAY
STANDARD PACKAGES V Package
VH Package
Unitrode Integrated Circuits Corporation 7 Continental Boulevard. ·P.O. Box 399 ·Merrimack. New Hampshire· 03054-0399 Telephone 603-424-2410 ·FAX 603-424-3460
6-14
n n INTEGRATED
~CIRCUITS
-UNITRODE
Dual Full-Bridge Power Driver
L2980
FEATURES · Operating Supply Voltage up to 46V
· Overtemperature Protected
· Operates in Switched and L/R Current Regulation Modes
· 25W Power-Tab Package for Low Installed Cost
· Individual Logic Inputs for Each Driver
· Channel-Enable Logic Inputs for Driver Pairs
· Internal Diodes Minimize Parts Count
DESCRIPTION The L298D is a power integrated circuit usable for driving resistive and inductive loads. This device contains four push-pull drivers with separate logic inputs. Two enable inputs are provided for power down and chopping. Each driver is capable of driving loads up to IA continuously.
The L298D features internal diodes for clamping output excursions when driving inductive loads, such as motors and transmission lines. For most applications, these diodes can completely replace all external clamp diodes. In certain cases, however, additional output catch diodes may be valuable for reducing recovery time or power dissipation.
Logic inputs to the L298D have high input thresholds (1.85V) and hysteresis to provide trouble-free operation in noisy environments normally associated with motors and inductors. The L298D input currents and thresholds allow the device to be driven by TTL and CMOS systems without buffering or level shifting.
The emitters of the low-side power drivers are available in pairs for current sensing. Feedback from the emitters can be used to control load current in a switching mode, or can be used to detect load faults.
Separate logic and load supply lines are provided to reduce total IC power consumption. Power consumption is reduced further when the enable inputs are low. This makes the L298D ideal for systems that require low standby current, such as portable or batteryoperated equipment.
CONNECTION DIAGRAM (TOP VIEW)"
L TAB CONNECTED TO PIN 8
BLOCK DIAGRAM
OUT!
V PACKAGE
ABSOLUTE MAXIMUM RATINGS
Power Supply, Vs ........................................... 50V Logic Supply Voltage, V55 ·....·......···..····..··.·..·.··.·· 7V Input and Enable Voltage, V;, VEn .................. -0.3V to+7V Peak Output Current (each channel), 10
Non-Repetitive (t = lOOµs) .............................. 1.5A Repetitive (80% on - 20% off; toN = lOms) .....·........ 1.2A DC Operation ............................................ IA Sensing Voltage, Vsens ............................. -IV to +2.3V Total Power Dissipation (Tease= 75°C), Ptot ................ 25W Storage and Junction Temperature, Tstg, T; ..... -40'C to+ I50°C
THERMAL DATA
Thermal Resistance Junction-Case, Rth ;-case ........ 3°C/W max. Thermal Resistance Junction-Ambient, Rth ;-amb .... 35°C/W max.
OUT 2
Vs
OUT3
OUT4
SENSE A
GND
6-15
SENSE 8
L298D
ELECTRICAL CHARACTERISTICS (for each channel, Vs= 42V, V88 = 5V, Ti= 25°C) TA=TJ
PARAMETERS
TEST CONDITIONS
MIN.
Supply Voltage (Pin 4), Vs
Operating Condition
V1H+2.5
Logic Supply Voltage (Pin 9), V88
4.5
VEn = H
V1 = L
Quiescent Supply Current (Pin 4), Is
IL= 0
V1 = H
VEn = L
VEn = H
V1 = L
Quiescent Current from V88 (Pin 9), 188
IL= 0
V; = H
VEn = L
Input Low Voltage (Pins 5, 7, 10, 12), V1 L
-0.3
Input High Voltage (Pins 5, 7, 10; 12), V; H
2.3
Low Voltage Input Current (Pins 5, 7, 10, 12), h L
V1 = L
High Voltage lnput Current (Pins 5, 7, 10, 12), I; H
V1 = H
, Enable Low Voltage (Pins 6, 11), VEn L
I' Enable High Voltage (Pins 6, 11), Ven H
-0.3 2.3
Low Voltage Enable Current (Pins 6, 11), len L
VEn = L
: High Voltage Enable Current (Pins 6, 11), len H
Ven = H :5 Vss -0.6V
Source Saturation Voltage, Vee sst1H1
IL= lA
Sink Saturation Voltage, VcE satlLl
IL= lA
Total Drop, Vee sat
IL= lA
High-Side Diode Voltage, Vo1H1
IL= lA
Low-Side Diode Voltage, Vo1L1 Sensing Voltage (Pins 1, 15), Vsens Source Current Turn-Off Delay, T1(V;) Source Current Fall Time, T2(V1) Source Current Turn-On Delay, Ta(V1) Source Current Rise Time, T4(V1) Sink Current Turn-Off Delay, T5(V;) Sink Current Fall Time, Ts(V1) Sink Current Turn·On Delay, T7(V1) Sink Current Rise Time, Te(V1)
IL= lA
0.5 V; to 0.9 IL121 0.9 IL to 0.1 IL121 0.5 V; to 0.1 IL121 0.1 IL to 0.9 IL121 0.5 V; to 0.9 IL131 0.9 IL to 0.1 IL131 0.5 V1 to 0.1 IL131 0.1 IL to 0.9 IL131
-1111
Commutation Frequency, fc
'IL= lAI
1) Sensing voltage can be -lV fort :5 50µS; in steady state Vssns min 2: -0.5V. 2) See figure la. 3) See figure 2a.
TYP.
3 15
5 1.5 1
30
30 1.2 1.4 2.6 1.6 I 1.6
1.7 0.2 2.5 0.35 0.7 0.2 1.5 0.2 25
MAX. 46 7 7 20 1 10 3 1.5 1.5
v..
-10 100 1.5
7 -10 100 2.2 2.2 4.2
ill
2.1 1 2
40
UNITS
v v
mA
mA
v
µA
v
µA
v v v v v
v
µs µs µs µs µs µs µs µs KHz
6-16
SWITCHING CHARACTERISTICS Figure 1. Switching times test circuits.
Vss = 5V Vs =-42V
NOTE: For INPUT chopper. set EN = H.
Figure 2. Switching Times Test Circuits.
Vu= 5V
Vs= 42V
L298D
Figure la. Source Current Delay Times vs. Input.
IL
lmuj(lA)l"f---°"""-----------,.---
90%
10%
Tl
T3
V1(4V) 50%
Figure 2a. Sink Current Delay Times vs. Input.
IL
lmax ( l A ) l t l - - - ° " " " - - - - - - - - - - - - , , . - - -
gCJ%·
NOTE: For INPUT chopper, set EN = H.
T5
Vi(4V) 50%
APPLICATIONS
Figure 3. Bi-Directional DC Motor Control. +v,
10 4
13
14
VEn = H
INPUTS C = H; D = L C=L;D=H C=D
VEn = L C=X;D=C
D
L= Low
H =High
12
X = Don't Care
+Vas
15
TO CONTROL CIRCUIT
ll VEn
D1 TO D4: UESllOl OR EQUIVALENT OR UC3610 DIODE ARRAY
6-17
FUNCTION Turn right Turn left Fast motor stop Free running motor stop
Figure 4. Bipolar Step Motor Driver.
STEP DIRECTION FULL/HALF
CURRENT LIMIT CONTROL
+5V
VMOTOR
.lµF
_r-41
!OK !OK !OK !OK
16
UC3517 ENCODER
,t_-__-_- -_-_- -_-_+_- -_t_!,O 12
L298D DRIVER
11 15
CURRENT SENSE RESISTORS
MOTOR
L298D
STANDARD PACKAGES VPackage
VH Package
Unitrode Integrated Circuits Corporation 7 Continental Boulevard. ·P.O. Box 399 ·Merrimack, New Hampshire· 03054-0399 Telephone 603-424-2410 ·FAX 603-424-3460
6-18
n n L1='.J INTEGRATED CIRCUITS
-UNITRODE
UC1517 UC3517
Stepper Motor Drive Circuit
FEATURES
DESCRIPTION
Complete Motor Driver and Encoder
The UC3517 contains four NPN drivers that operate in two-phase
Continuous Drive Capability 350mA per Phase
fashion for full-step and half-step motor control. The UC3517 also contains two emitter followers, two monostables, phase de-
Contains all Required Logic for Full and Half Stepping
Bilevel Operation for Fast Step Rates
Operates as a Voltage Doubler
Useable as a Phase Generator and/or as a Driver
Power-On Reset Guarantees Safe, Predictable Power-Up
coder logic, power-on reset, and low-voltage protection, making it a versatile system for driving small stepper motors or for controlling large power devices.
The emitter followers and monostables in the UC3517 are configured to apply higher-voltage pulses to the motor at each step command. This drive technique, called "Bilevel," allows faster stepping than common resistive current limiting, yet generates less electrical noise than chopping techniques.
ABSOLUTE MAXIMUM RATINGS
Second Level Supply, Vss . . . . . . . . . . . . . . . . . . . . . . . . . . 40V Phase Output Supply, VMM . . . . . . . . . . . . . . . . . . . . . . . . . 40V Logic Supply, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Logic Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . -.3V to +?V Logic Input Current ............................. ±1 OmA Output Current, Each Phase ...................... 500mA Output Current, Emitter Follower . . . . . . . . . . . . . . . . . . -500mA Power Dissipation, (Note) ............................ 1W
Power Dissipation, (Note) ........................... 2W Junction Temperature ............................ 150°C Ambient Temperature, UC1517. . . . . . . . . . . . -55°C to +125°C Ambient Temperature, UC3517 .............. 0°C to +70°C Storage Temperature . . . . . . . . . . . . . . . . . . . -55°C to +150°C Note: Consult Packaging section of Databook for thermal
limitations and considerations ofpackage.
BLOCK DIAGRAM
Monostable
Monostable
STEP HSM
DIR
Vee
Pulse 8
Pulse A
11----------1_~ Clock Full/Half
PHASE LOGIC
Direction
Logic Power Power-On Reset
Reset~..-----.....----..-------.~
Phase A1 Phase A2 Phase 81 Phase 82
A Off 8 Off
INH 11
6/93 6-19
CONNECTION DIAGRAMS DIL-16 (TOP VIEW) J or N Package
Pe2 Pe1 GND PA1 PA2 DIR STEP
(llB
Vee Vss Le LA RC INH HSM (!IA
UC1517 UC3517
PLCC-20, LCC-20
(TOPVIEW) Q&LPACKAGE
- - L3 2 1 ~ 201s
4
18
5
17
~ 6
16
7
15
8
14
9 10 11 12 13
~~~~~
PACKAGE PIN FUNCTION
FUNCTION
PIN
N_LC
1
PB2
2
Pe1
3
GND
4
PA1
5
N_LC
6
PA2
7
DIR
8
STEP
9
12JB
10
NL
11
121A
12
HSM
13
INH
14
RC
15
N]C
16
LA
17
LB
18
Vss
19
Vee
20
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA= -55°C to +125°C for the
UC1517 and 0°Cto +70°Cforthe UC3517, Vcc=5V, Vss = 20V, TA=TJ. Pin numbers refer to DIL-16 package.
PARAMETER
Logic Supply, Vee Second Supply, Vss Logic Supply Current
Input Low Voltage Input High Voltage l'!e_ut Low Current Input High Current Phase Output Saturation Vol~ge_ Phase Output Leakage Current Follower Saturation Voltage to Vss
TEST CONDITIONS
Pin 16 Pin 15 VINH =0.4V VINH=4.0V Pins6, 7, 10, 11 Pins 6, 7, 10, 11 Plns6, 7, 10, 11;V=OV Pins 6, 7, 10, 11; V = 5V Pins 1, 2, 4, 5; I = 350mA Pins 1, 2, 4, 5; V = 39V Pins 13,14; I =350mA
UC1517 / UC3517
MIN TVP MAX
4.75
5.25
10
40
45 60
12
0.8
2.0
-400
20
0.6 0.85
500
-2
UNITS
v v
mA
mA
v v
~ µA
v
µA
v
Follower Leakage Current Output Low Voltage, 121A, 1210 Phase Tum-On Time Phase Tum-Off Time
Pins 13,14; V = OV Pins 8, 9; I = 1.6mA Pins 1, 2, 4, 5 Pins 1, 2, 4, 5
500 JU\.
v 0.1 0.4
2
µs
1.8
µs
Second-Level On Time. TMONO
Pins 13,14; Figure 3 Test Circuit
275 325 375 µs
Logic llJ2lll Set-up Time, ts L~c Input Hold Time, th STEP Pulse Width, IP
Pins 6, 10; Figure 4 Pins 6, 10; Figure 4 Pin 7; Figure 4
400
ns
0
ns
800
ns
Timing Resistor Value Timing C~itor Value Power-On Threshold Power-Off Threshold Power Hysteresis
Pin 12 Pin 12 Pin 16 Pin 16 Pin 16
1k
100k Q
0.1
500 nF
4.3
v
3.8
v
0.5
v
6-20
UC1517 UC3517
+5
+20
+20
6 16
7 OUT
10
15 2 4 5
+5
HSM. rv1t11V\/\NV\
DIR + - - - - + - - i - . , - - - - -
LA, L e + - - - - - ' PA1 , PA2 blJlil\JllllWGWIJU'JIJ---Pa1, Pe2 M/\NW\/\IV'i/VV\M
Figure 3. Test Circuit
Figure 4. Timing Waveforms
PIN DESCRIPTION
Vee: Vee is the UC3517's logic supply. Connect to a regulated 5VDC, and bypass with a 0.1 µF ceramic capacitor to absorb switching transients.
VMM: VMM is the primary motor supply. It connects to the UC3517 phase outputs through the motor windings. Limit this supply to less than 40V to prevent breakdown of the phase output transistors. Select the nominal VMM voltage for the desired continuous winding current.
Vss: Vss is the secondary motor supply. It drives the LA and LB outputs of the UC3517 when a monostable in the UC3517 is active. In the bilevel application, this supply is applied to the motor to charge the winding inductance faster than the primary supply could. Typically, Vss is higher in voltage than VMM, although Vss must be less than 40V. The Vss supply should have good transient capability.
GROUND: The ground pin is the common reference for all supplies, inputs and outputs.
RC: RC controls the timing functions of the monostables in the UC3517. It is normally connected to a resistor (RT) and a capacitor (CT) to ground, as shown in Figure 3. Monostable on time is determined by the formula TON 0.69 RT CT. To keep the monostable on indefinitely, pull RC to Vee through a 50k resistor. The UC3517 contains only one RC pin for two monostables. If step rates comparable to TON are commanded, incorrect pulsing can result, so consider maximum step rates when selecting RT and CT. Keep TON :ST STEP MAX.
IZJA and 12Je: These logic outputs indicate half-step position. These outputs are open-collector, low-current drivers, and may directly drive TTL logic. They can also drive CMOS logic if a pull-up resistor is provided. Systems which use the UC3517 as an encoder and use a different driver can use these outputs to disable the external driver,
as shown in Figure 8. The sequencing of these outputs is shown in Figure 5.
PA1, PA2, Pe1, and Pez: The phase outputs pull to ground sequentially to cause motor stepping, according to the state diagram of Figure 5. The sequence of stepping on these lines, as well as with the LA and LB lines is controlled by STEP input, the DIR input, and the HSM input. Caution: If these outputs or any other IC pins are pulled too far below ground either continuously or in a transient, step memory can be lost. It is recommended that these pins be clamped to ground and supply with high-speed diodes when driving inductive loads such as motor windings or solenoids. This clamping is very important because one side of the winding can "kick" in a direction opposite the swing of the other side.
LA and Le: These outputs pull to Vss when their corresponding monostable is active, and will remain high until the monostable time elapses. Before and after, these outputs are high-impedance. For detail timing information, consult Figure 5.
STEP: This logic input clocks the logic in the UC3517 on every falling edge. Like all other UC3517 inputs, this input is TTLJCMOS compatible, and should not be pulled below ground.
DIR: This logic input controls the motor rotation direction by controlling the phase output sequence as shown in Figure 5. This signal must be stable 400ns before a falling edge on STEP, and must remain stable through the edge to insure correct stepping.
HSM: This logic input switches the UC3517 between half-
stepping (HSM = low) and full-stepping (HSM = high) by
controlling the phase output sequence as show in Figure 5. This line requires the same set-up time as the DIR input, and has the same hold requirement.
6-21
UC1517 UC3517
INH: When the inhibit input is high, the phase and 0 .outputs are inhibited (high impedance). STEP pulses received while inhibited will continue.to update logic in the IC, but the states will not be reflected atthe outputs until inhibit is pulled low. In stepper motor systems, this can be used to save power or to allow the rotor to move freely.for manual repositioning.
OPERATING MODES
The UC3517 is a system component capable of many different operating modes, including:
used in conjunction with discrete power transistors or power driver ICs, like the L298. These can be connected as current gain devices that turn on when the phase outputs turn on.
Bipolar Motor Drive: Bipolar motors can be controlled by the UC3517 with the addition of bipolar integrated drivers such as the UC3717A (Figure 8) and the L298, or discrete devices. Care should be taken with discrete devices to avoid potential cross-conduction problems.
.LOGIC FLOW GRAPH
Unipolar Stepper Driver: In its simplest form, the UC3517 can be connected to a stepper motor as a unipolar driver. LA, LB, RC and Vss are not used, and may be left open. All other system design considerations mentioned above apply, including choice of motor supply VMM, undershoot diodes and timing considerations.
Unipolar Bilevel Stepper Driver: If increased step rates are desired, the application circuit of Figure 6 makes use of the monostables and emitter fOllowers as well as the configuration mentioned above to provide high-voltage pulses to the motor windings when the phase is turned on. For a given dissipation level, this mode offers faster step rates, and very little additional electrical noise.
The choice of monostable components can be estimated based on the timing relationship of motor current and volt-
age: V = Ldl/dt. Assuming a fixed secondary supply volt-
age (Vss), a fixed winding inductance (LM), a desired winding peak current (lw), and no back EMF from the. motor, we can estimate that RTCT = 1.449 lwLMNss. In practice, these calculations should be confirmed and adjusted to accommodate for effects not modeled.
Voltage-Doubled Mode: The UC3517 can also be used to generate higher voltages than available with the system power supplies using capacitors and diodes. Figure 9 shows how this might be done, and gives some estimates for the component values.
The UC3517 contains a bidirectional counter which is decoded to generate the correct phase and 0 outputs. This counter is incremented on every falling edge of the STEP input. Figure 5 shows a graph representing the counter sequence, inputs that determine the next state (DIR and HSM), and the outputs at each state. Each circle represents a unique logic state, and the four inside circles represent the half-step states.
The four bits inside the circles represent the phase outputs in each state (PA1, PA2, PB1, and PB2). For example, the circle labeled 101 O is immediately entered when the device is powered up, and represents PA1 off ("1" or high), PA2 on ("O" or low), PB1 off ("1" or high) and PB2 on ("O" or low). The 0A and 0B outputs are both low (unidentified).
The arrows in the graph show the state changes. For example, if the IC is in state 011 O, DIR is high, HSM is high, and STEP falls, the next state will be 0101, and a pulse will be generated on the LB line by the monostable.
Inhibit will not effect the logic state, but it will cause all phase outputs and both 0 outputs to go high (off). A falling edge on STEP will still cause a state change, but inhibit will have to toggle low for the state to be apparent.
A falling edge on STEP with HSM high will cause the counter to advance to the next full step state regardless of whether or not it was in a full step state previously.
Higher Current Operation: For systems requiring more No LA or LB pulses are generated entering half-states. than 350mA of drive per phase, the UC3717A can be
6-22
UC1517 UC3517
Figure 5. Logic Flow Grapl'l
MOTOR
µPROCESSOR
6 16 15 14 1311-----+-+-------11----=+-
7 UC
2 1 - - - - -.....- + - - - - - - + - - - - . ! - + - + - - .
10 3517 41------------+----ii+-+---+--
11
12 3 5 1 - - - - - - - - - - -.....-~"+--+-t---+--
RT
For applications requiring very fast step rates, a zener diode permits windings to discharge at higher voltages, and higher rates. Driver transistor breakdown must be considered when selecting Vss and zener voltage to insure that the outputs will
not overshoot past 40V. If the zener diodes are not used and UC361 Opin 2 is connected directly to Vss then higher Vss can be used.
Figure 6. Bilevel Motor Driver
6-23
WINDING CURRENT
/'-)'-...
- RT CT LONG'-............__
UC1517 UC3517
Experimental selection of RT and CT allow the designer to se-
lect a small amount of winding current overshoot, as shown above. Although the overshoot may exceed the continuous rated current of the winding and the drive transistors, the dura-
TIME
lion can be well controlled. Average power dissipation for the driver and motor must be considered when designing systems with intentional overshoot, a.nd must stay within conservative limits for short duty cycles.
Figure 7. Effects of Different RT & CT on Bilevel Systems
+5 10k
+5
+5 +5
DIR 6
16
10k
10k
STEP 7 UC3517 4
HSM 10
9
INH 11
3
8
+5
10k
-
()
PHASE GENERATOR
+5 +5 VMM VMM
11 6 3 14
8
7
UC3717
9 2
+5 +5 VMM VMM 11 6 3 14
UC3717
0 MOTOR
-
--
()
DRIVERS
In this application, the 0A and 08 outputs of the UC3517 are connected to the current program inputs of the UC3717. This allows the UC3517 inhibit signal to inhibit the UC3717, and
also allows half-step operation of the UC3717. Peak motor winding current will be limited to approximately .42V/R1 by chopping.
Figure 8. Interface to UC3717 Bipolar Driver
6-24
+5 VMM
UC1517 UC3517
STEP 7 INH 11 DIR 6
HSM 10
4
UC3517 5 2
MOTOR
0
12
3 14
JCr
RT
-
-
Although component values can be best optimized experimentally, good starting values speed development. For this design,
start with:
where:
RT Cr =3 LW/RW C1 =C2 = Lw IR/Rw
R1 =R2 =2.9 TMIN/C1
Lw is winding inductance, Aw is winding resistance, IR is rated winding current, and TMIN is minimum step period expected.
Figure 9. Using the UC3517 as a Voltage Doubler
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Dual Schottky Diode Bridge
(~)
UC1610 UC3610
FEATURES Monolithic Eight-Diode Array Exceptional Efficiency Low Forward Voltage Fast Recovery Time High Peak Current Small Size
DESCRIPTION This eight-diode array is designed for high-current, low duty-cycle applications typical of flyback voltage clamping for inductive loads. The dual bridge connection makes this device particularly applicable to bipolar driven stepper motors.
The use of Schottky diode technology features high efficiency through lowered forward voltage drop and decreased reverse recovery time.
This single monolithic chip is fabricated in both hermetic CERDIP and copper-
leaded plastic packages. The UC161 o in ceramic is designed for -55°C to +12s0 c
environments but with reduced peak current capability; while the UC361 o in plastic has higher current rating over a o·c to +70°C temperature range.
ABSOLUTE MAXIMUM RATINGS
Peak Inverse Voltage (per diode) ........................................... 50V Peak Forward Current
UC1610 ...................................................·.......... 1A UC3610 .............................................................. 3A
Power Dissipation atTA = +70°C ..............................·............ 1W
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to+1so·c
Lead Temperature (Soldering, 1OSeconds) ................·................ 300°C
Note: Consult Packaging Section of Databook for thermal limitations and considerations of package.
CONNECTION DIAGRAMS
DIL-8 (TOP VIEW) N or J Package
1
SOIC-16 (TOP VIEW) OW Package
PLCC-20 (TOP VIEW)
Q Package
-3= -=2- -=1- -2=0- -1=9-
H~ 5 ~1a17
[ 6
16
[ 7
15
[ 8
14
9 10 11 12 13
6/93 6-26
UC1610 UC3610
ELECTRICAL CHARACTERISTICS: All specifications apply to each individual diode. TJ = 25°C except as noted. TA= TJ.
PARAMETER Forward Voltage Drop
Leakage Current
Reverse Recov~ Forward Recov~ Junction C~acitance
TEST CONDITIONS
IF= 100mA IF= 1A VA =40V VA= 40V TJ = +100°C 0.5A Forward to 0.5A Reverse 1A Forward to 1.1 V Recov~ VR=5V
MIN TYP MAX UNITS
v 0.4 0.5 0.7 v 0.8 1.0 1.3
.01 0.1 mA
0.1 1.0 mA
15
ns
30
ns
70
_2f
Note: At forward currents of greater than 1.0A a parasitic current ofapproximately 1OmA may be collected by adjacent diodes.
Reverse Current vs Voltage
3000 2000
1000
500
zfwaa::
,__--+_TJ A 300
200
L
100
=125 'C
~
:J
50
(.)
30
w
2 0 r-~-t-~-t-~-t-~-+~--j
Cl
<::.::
10
< w
..J
5 23
r-::~:T:J:=7:5i'C;~~~2~J
b-
TJ -25 'C_ t----1
1 ~~~~~~~~~~~~
0 10 20 30 40 50
REVERSE VOLT AGE - (V)
Forward Current vs Voltage
3.0 2.0
1.0
faazw-::
0.5 0.3 0.2
:J
(.)
o.1
N .L
7 _h-1 TJ =-55 'C
1 TJ+-TJ =25 ·c
f--1-fH-__ ~ :~;
-+111=1:4-TJ =125 ° C t-1
~ .~~ 1--l-~1-!/-t-l+--+--+-I--+--+--l-
u. .005
I[_
I
.003
1
!
.002
rT
!
,001 L.},_jjj__
I- :
I
I
0 .2 .4 .6 .8 1.01.21.41.61.82.0
FORWARD VOLTAGE - (V)
Reverse Recovery Characteristics
TIME, 2ns/DIV
Forward Recovery Characteristics
I VODLIOTDAEGE
1.0V/DIV
ov
~ TA-25"C DIODE ,..-VOLTAGE
' DIODE CURRENT
+I DIODE CURRENT 500mA/DIV
OA
UC1610 FORWARD RECOVERY
CH1 · VD CH2 · ID · 1A
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UC1611 UC3611
Quad Schottky Diode Array
FEATURES Matched, Four-Diode Monolithic Array High Peak Current Low-Cost MINIDIP Package Low-Forward Voltage Parallelable for Lower VF or Higher IF Fast Recovery Time Military Temperature Range Available
DESCRIPTION
This four-diode array is designed for general purpose use as individual diodes or as a high-speed, high-current bridge. It is particularly useful on the outputs of high-speed power MOSFET drivers where Schottky diodes are needed to clamp any negative excursions caused by ringing on the driven line.
These diodes are also ideally suited for use as voltage clamps when driving inductive loads such as relays and solenoids, and to provide a path for current free-wheeling in motor drive applications.
The use of Schottky diode technology features high efficiency through lowered forward voltage drop and decreased reverse recovery time.
This single monolithic chip is fabricated in both hermetic CERDIP and copper-leaded plastic packages. The UC1611 in ceramic is designed for -55°C to +125°C environments but with reduced peak current capability:
while the UC3611 in plastic has higher current rating over a o·c to +70°C
ambient temperature range.
CONNECTION DIAGRAM
DIL-8 (TOP VIEW)
N or J Package
SOIC-16 (TOP VIEW) OW Package
PLCC-20 (TOP VIEW)
Q Package
w 3 2 1 2019
4
1~
~ ~~q:
9 10 11 12 13
6/93
6-28
ABSOLUTE MAXIMUM RATINGS
Peak Inverse Voltage (per Diode)................................. 50V Diode-to-Diode Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80V Peak Forward Current
UC1611 .................................................... 1A UC3611 .................................................... 3A Power Dissipation atTA= +70°C .................................. 1W Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C Lead Temperature (Soldering, 10 Seconds) ....................... +300°C Note: Please consult Packaging Section of Databook for thermal limitations and
considerations ofpackage.
UC1611 UC3611
ELECTRICAL CHARACTERISTICS: All specifications apply to each individual diode. TJ = +25°C except as noted.
TA =TJ.
PARAMETER Forward Voltage Drop
TEST CONDITIONS IF= 100mA IF= 1A
MIN. 0.3
TYP. 0.4 0.9
MAX. UNITS
0.7 v 1.2 v
Leakage Current
VR = 40V
0.01 0.1 mA
VR = 40V, TJ = +100°C
0.1 1.0 mA
Reverse Recovery
0.5A Forward to 0.5A Reverse
20
ns
Forward Recovery Junction Capacitance
1A Forward to 1.1 V Recovery VR=5V
- ---- 40
ns
100
-.l..--~---
pF
Note: At Forward currents ofgreater than 1.0A, a parasitic current of approximately 1OmA may be collected by adjacent diodes.
Reverse Current vs Voltage
3000 --+1 ---+-~Ti---+------1 Lr'
2000 i
1000
500 300
l
1z- 200 I
z
aaU::J 100
:::> 50
0
30
UJ
20 f---+--~1------<--~,-___,
(!)
<
~
10 -- ---1-----+---+----t-----j
< w
5
_J
3
l
TJ=75'C
2
TJ =25 '..Q. -!----'
1
0 10 20 30 40 50
REVERSE VOLTAGE - (V)
Forward Current vs Voltage
< l 3.0 2.0
.LIL!Zl '
_L1 J_LJ I i j
~ 1.0 !,__,~---HV'-+17-+,++-TT~--+--+_l1_____,
1z -
aaU::J
05
o:3
0. 2
:::> 0
0. 1
i riLh
J I I
i/__E..--+-1 TJ =-55 'C
1 li1J--+--TJ =25 'C
a<C:l 3a::
0
:~; r----++1I.HJ--it[o=t-'9-rJ =125 , c t---1
.02 e-+-I~T+-+---+--+--+--___,,__-+-+---1
.01
u. .005
.003
.002
.001
0 .2 .4 .6 .8 1.01.21.41.61.82.0
FORWARD VOLTAGE - (V)
6-29
TYPICAL APPLICATIONS
A. Clamp Diodes· PWMS and Drivers
UC1611 UC3611
PWM/Driver
B. Transformer Coupled DriveCircuits _
,-----, Ve
UC3611
I I
r~60
HZ
I I I
_____ _J
0.1µF
C. Linear Regulations
r---------------,
I
UC3611
I
+
L.....J
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UC1612 UC3612
Dual Schottky Diode
FEATURES · Monolithic Two Diode Array · Exceptional Efficiency · Low Forward Voltage · Fast Recovery Time · High Peak Current · Small Size
ABSOLUTE MAXIMUM RATINGS Peak Inverse Voltage (per diode) ........................... 50V Peak Forward Current, UC3612 ............................... 3A Peak Forward Current, UC1612 ............................... 1A Power Dissipation at TA = 70°C .............................. 1W
Derate 12.5mW/°C above 70°C Storage Temperature Range .............. -65°C to+150°C Lead Temperature (Soldering, 10 Seconds) ....... 300°C
DESCRIPTION The two-diode array is designed for high-current, low duty-cycle applications typical of flyback voltage clamping for inductive loads.
The use of Schottky diode technology features high efficiency through lowered forward voltage drop and decreased reverse recovery time.
This single monolithic chip is fabricated in hermetic CERDIP as well as copper leaded plastic MINIDIP and SOIC surface mount power pack. The UC1612 in ceramic is designed for -55°C to +125°C environments, but with reduced peak current capability; while the UC3612 has higher current rating over a 0°c to +70°C ambient temperature range.
CONNECTION DIAGRAM
J, N or DP PACKAGE (TOP VIEW)
Pins 2,3,6,7 are connected to substrate and must be electrically isolated.
6-31
UC1612 UC3612
Electrical Characteristics (All specifications apply to each individual diode. T, = 25°C except as noted).
PARAMETER Forward Voltage Drop
Leakage Current Reverse Recovery Forward Recovery
TEST CONDITIONS I,= 100mA I,= 1A VR= 40V V" = 40V, TJ= 100°c .5A Forward to .5A Reverse 1A Forward to 1.1 V Recovery
MIN TYP MAX UNITS
0.49
.55
v
0.90
1.0
v
.01
0.1
mA
0.1
1.0
mA
15
nSec
30
nSec
Junction Capacitance
VA= 5V
70
pF
Note: At forward currents of greater than 1.0A, a parasitic current of approximately 1OmA may be collected by adjacent diodes.
Reverse Current vs Voltage
~ ~
1z aaw : :
::J 0
w
~
)<'.
<wi:
...J
0
10
20
30
40
50
REVERSE VOLTAGE (V)
Forward Voltage vs Current
0 .1 .2 .3 .4 .5 .6 .7 .8 .9 1.0 1.1 1.2 1.3 .OOlA FORWARD VOLTAGE (V)
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\.\;;JI~ #tiffi·[J·(·'.'
Switchmode Driver for 3-0 Brushless DC Motors
UC1620 UC3620
FEATURES 2A Continuous, 3A Peak Output Current
BV to 40V Operation
Internal High Gain Amplifier for Velocity Control Applications
TTL Compatible Hall Inputs
Mask Programmable Decode Logic
Pulse-by-Pulse Current Limiting
Internal Thermal Shutdown Protection
Under-Voltage Lockout
Available in V, VH Multiwatt Plastic, and SP Hermetic Packages
DESCRIPTION
The UC3620 is a brushless DC motor driver capable of decoding and driving all 3 windings of a 3-phase brushless DC motor. In addition, an on-board current comparator, oscillator, and high gain Op-Amp provide all necessary circuitry for implementing a high performance, chopped mode servo amplifier. Full protection, including thermal shutdown, pulse-by-pulse current limiting, and under-voltage lockout aid in the simple implementation of reliable designs. Both conducted and radiated EMI have been grf;latly reduced by limiting the output dv/dt to 150V/JAS for any load condition.
The UC1620SP is characterized for operation over the full military temperature range of -55°C to +125°C, while the UC3620SP is characterized for 0°C to +70°C. Surface mount versions are also available.
BLOCK DIAGRAM
TIMING
.....-~~~~~~~~~~~~~~~---191--~~~~~~~~~~--t
-E/A +E/A
MONO
T
Ql--~-1-1-~1--~--..,
GND
6/93
!SENSE
6-33
HALL INPUTS
EMITTERS
UC1620 UC3620
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage, Vee .......................................... 40V
= Output Current, Source or Sink Non-Repetitive (t 100µsec), lo ............................... 3A Repetitive (80% on - 20% off; toN = 10ms) ..................... 2.5A DC Operation.............................................. 2A Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +Vee Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +Vee
= Total Power Dissipation (at TeASE 75° C)
for SP Package (Note 2). .. .. . . . . .. . . . . . . .. .. . . .. .. . . . . . . . . . . 15W Storage and Junction Temperature .................... -40°C to +150°C
Note 1: All vollages are with respect to ground. Currents are positive into, negative out of the specified terminal.
Note 2: Consull Packaging Section of Databook for thermal limitations and considerations ofpackage.
CONNECTION DIAGRAMS SP Hermetic Power OIL
EMITTERS 1 EMITTERS 2
VccPWR · VccLOGle 1 E/A
V and VH Packages
1e FWD/REV e
14 TIMING 13 GROUND
28-PIN LCC and (TOPVIEW) LPackage
L4 3 2 1 28 27 26
5
25
6
24~
7
23
~8
22
~9
21
~10
20
11
19
12 13 14 15 16 17 18
PACKAGE PIN FUNCTIONS
FUNCTION
PIN
N/C
1
EMITTERS
2
EMITTERS
3
N/C
4
N/C
5
AOUT
6
VeePWR
7
N/C
8
Vee LOGIC
9
+E/A
10
-E/A
11
N/C
12
E/ACOMP
13
I SENSE
14
GND
15
TIMING
16
HA
17
N/C
18
N/C
19
HB
20
He
21
FWD/REV
22
VecPWR
23
GOUT
24
N/C
25
N/C
26
EMITTERS
27
BOUT
28
6-34
UC1620 UC3620
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA= o·c to 10°c for 3620; TA
= 55°C to +125°Cfor UC1620; Vee= 20V, RT= 20V, RT= 10k, CT: -2.2nF. TA=TJ.
PARAMETER
Error Ampllfler Section Input Offset Volta.Jl.e Input Bias Current Input Offset Current Common Mode Range Open Loop Gain Unity Gain Bandwidth Output Sink Current Output Source Current
Current Sense Section Input Bias Current Internal Clamp Divider Gain Internal Offset Voltage
Timing Section Output Off Time Upper Mono Threshold Lower Mono Threshold
Decoder Section High-Level Input Voltage Low-Level Input Voltage High-Level Input Current Low-Level Input Current
Output Section Output Leakage Current VF1 Schottky Diode VF1 Substrate Diode Total Output Voltage Drop Output Rise Time Output Fall Time
Under VoHage Lockout Startup Threshold Threshold Hysteresis
Thermal Shutdown Junction Temperature
Total Standby Current Supply Current
TEST CONDITIONS
Vee = av to 40V
AVPIN6=1Vto4V TJ = 25°C, Note 2 VPIN6= 1V VPIN6= 4V
Vcc=40V lo=2A lo=2A lo = 2A, Note 3 RL=44Q AL= 440
UC3620
UC1620
UNIT
MIN TYP MAX MIN TYP MAX
1.5 10
1.5 10 mV
-.25 -2.0
-.25 -2.0 µA
15 250
15 250 nA
0
VIN-2 0
v VIN-2
80 100
75 100
dB
0.8
0.8
MHz
2
2
mA
8
8
mA
-2.0 -5
-2.0
-5
µA
.425 0.5 .575 .405 0.5 .595
v
.180 0.2 .220 .170 0.2 .230 VN
.8
1.0 1.2 .75
v 1.0 1.25
18
20
22
5.0
2.0
17
20
23 ~
5.0
v --- ----
2.0
v
.,--.-~~
2.2
2.5
v
0.8
0.8 v
10
10 µA
-10
-10
µA
500 1.5 2.0 2.2 3.0 3.0 3.6 150 150
1500 µA
1.5 2.0
v
2.2 3.0
v
3.0 3.6
v
150
ns
150
ns
8.0 0.5
8.0 v
0.5
v
150
180 150
180 ·c
32
55
32
55 mA
Note 2: These parameters, although guaranteed over the recommended operating conditions, are not 100% tested in production. Note 3: The total voltage drop is defined as the sum ofboth top and bottom side driver.
6-35
UC1620 UC3620
TABLE1
STEP FWD/ Ha Hb He REV
1
1 101
2
1 100
3
1 110
4
1 010
5
1 011
6
1 001
1
0 101
2
0 100
3
0 110
4
0 010
5
0 011
6
0 001
H =HIGH OUTPUT L =LOW OUTPUT 0 =OPEN OUTPUT
AOUT
H H 0 L L 0 L L 0 H H 0
BoUT
L 0 H H 0 L H 0 L L 0 H
COUT
0 L L 0 H H 0 H H 0 L L
CIRCUIT DESCRIPTION
The UC3620 is designed for implementation of a complete 3-0 brushless DC servo drive using a minimum number of external components. Below is a functional description of each major circuit feature.
DECODER Table 1 shows the decoding scheme used in the UC3620 to decode and drive each of three high current totem pole output stages. A forward/reverse signal, pin 13, is used to provide direction. At any point in time, one driver is sourcing, one driver is sinking, and the remaining driver is off or tri-stated. Pulse width modulation is accomplished by turning the sink driver off during the monostable reset time, producing a fixed off-time chop mode. Controlled output rise and fall times help reduce electrical switching noise while maintaining relatively small switching losses. Hall lines require pull-up resistors.
CURRENT SENSING Referring to Figure 1, emitter current is sensed across Rs and fed back through a low pass filter to the current sense pin 7. This filter is required to eliminate false triggering of the monostable due to leading edge current spikes. Actual filter values, although somewhat dependent on external loads, will generally be in the 1kQ and 1000pF range.
TIMING An R-C time constant on pin 9 is used by the monostable to generate a fixed off time at the outputs according to the formula:
TOFF· .916RTCT
As the peak current in the emitters approaches the value at the minus (-) input of the on-board comparator, the
~~··
CURRENT WAVEFORM
Figure 1. Current Sense Filter
monostable is triggered, causing the outputs to be turned off. On time is determined by the amount of time required for motor current to increase to the value required to retrip the monostable. A timing sequence of these events is shown in Figure 2.
ILTLTI EMITTER CURRENT (PIN 1+7)
-JtOFFj-
5V~ I \ I
TIMING (PIN 9) 2V - _J_+\J_ - - ~- - -
VOLTAGE
I
==I --uu=--
CHOPPED OUTPUTVOCCV
VOLTAGE
-- - - - - -
Figure 2. Chopped Mode llming Diagram
CURRENT LIMIT
Since peak current is being controlled at all times by the
internal comparator, a simple voltage clamp at its nega-
tive (-) input will limit peak current to a maximum value. A
fixed o.sv internal clamp has been included on the
UC3620, and any current spike in the output which gen-
o.sv erates a sensed voltage greater than
will immedi-
ately shut down the outputs. Actual peak current values
may be programmed by selecting the appropriate value
of Rs according to the formula:
Rs=
0.5
/CURRENTLIMIT
6-36
UC1620 UC3620
CIRCUIT DESCRIPTION (cont.)
ERROR AMPLIFIER LIMIT A high performance, on-board error amplifier is included to facilitate implementing closed loop motor control. Error voltage generation and loop compensation are easily accomplished by appropriately configuring the gain and feedback of this amplifier. To provide a larger dynamic signal range at the output of the error amplifier, a divide by 5 resistor network is used to reduce the error signal level before applying to the internal comparator. In addition, a one volt offset has been introduced at the output of the error amplifier to guarantee control down to zero current in the output stages. Since this offset is divided by
the open loop gain of the feedback loop, it has virtually no effect on closed loop performance.
PROTECTION FUNCTIONS Protective functions including under-voltage lockout, peak current limiting, and thermal shutdown, provide an extremely rugged device capable of surviving under many types of fault conditions. Under-voltage lockout guarantees the outputs will be off or tri-slated until Vee is sufficient for proper operation of the chip. Current limiting limits the peak current for a stalled or shorted motor, whereas thermal shutdown will tri-state the outputs if a temperature above 150°C is reached.
TYPICAL APPLICATIONS
+o-......-~~~~~~~~~~~~~~~~~~~~~~~-,
VMOTOR
r-------------------~~NG9 ---------------
1 I I I I I I
FWD/REVERSE
------ 3 FWD/
REVERSE
3-0 Brushless DC Open Loop Motor Drive
6-37
+o--e~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~--.
VMOTOR
Vee
UC1620 UC3620
FWD/REVERSE
FWD/ REVERSE
3-0 Brushless DC Open Loop Motor with Current Limit at 2A.
VMOTOA
TIMING
Vee
!~---------------------
I
I
I
I
I
COMP I
F/V CONVERTER
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Closed Loop Speed Control Servo 6-38
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Brushless DC Motor Controller
(®) UC1625 UC3625
FEATURES
DESCRIPTION
Drives Power MOSFETs or Power Darlingtons Directly
The UC1625 and UC3625 motor controller ICs integrate most of the functions required for high-performance brushless DC motor
50V Open Collector High-Side Drivers Latched Soft Start
control into one package. When coupled with external power MOSFETs or Darlingtons, these ICs perform fixed-frequency PWM motor control in either voltage or current mode while implementing
High-speed Current-Sense Amplifier with Ideal Diode
closed loop speed control and braking with smart noise rejection, safe direction reversal, and cross-conduction protection.
Pulse-by-Pulse and Average Current Sensing Although specified for operation from power supplies between 1OV
Over-Voltage and Under-Voltage Protection Direction Latch for Safe Direction Reversal
and 18V, the UC1625 can control higher voltage power devices with external level-shifting components. The UC1625 contains fast, high-current push-pull drivers for low-side power devices and 50V
Tachometer
open-collector outputs for high-side power devices or level shifting
Trimmed Reference Sources 30mA
circuitry.
Programmable Cross-Conduction Protection The UC1625 is characterized for operation over the military temperature range of -55°C to +125°C, while the UC3625 is
Two-Quadrant and Four-Quadrant Operation characterized from 0°c to 70°C.
BLOCK DIAGRAM
NOTE: ESD Protection to 2kV
5/93
Coast Chop Quad Decoder Brake
6-39
UDG-92029
ABSOLUTE MAXIMUM RATINGS
CONNECTION DIAGRAM
UC1625 UC3625
Vee Supply Voltage .............................. +20V Pwr Vee Supply Voltage .......................... +20V PWM In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 6V E/A IN(+), E/A IN(-) ......................... -0.3to12V ISENSE1, ISENSE2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.3 to 6V CV-Coast, Dir, Speed.in, H1, H2, H3,
SSTART, Quad Sel. . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 8V PU Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 50V PU Output Current . . . . . . . . . . . . . . . . . . +200 mA continuous PD Output Current . . . . . . . . . . . . . . . . . . ±200 mA continuous E/A Output Current............................. ±1 OmA I SENSE Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . "10 mA Tach Out Output Current ........................ ±1 OmA VREF Output Current. . . . . . . . . . . . . . . . . . . -50 mA continuous Operating Temperature Range UC1625 ...... -55°C to 125°C Operating Temperature Range UC3625 . . . . . . . . 0°C to 70°C
DIL-28 (TOP VIEW) J or N PACKAGE
Note 1: Currents are positive into and negative out of the speci·
tied terminal.
·
Note 2: Consult Unitrode Integrated Circuits databook for
information regarding thermal specifications and limitations of
packages.
Note 3: This pinout applies to the SOIC (OW), PLCC (Q), and LCC (L) packages (ie. pin 22 has the same function on all packages.)
ELECTRICAL
Unless otherwise stated, these specifications apply for: TA = 25°C; Pwr Vee =Vee= 12V; Rose= 20k
CHARACTERISTICS: to VREF; Cose= 2nF; RTAeH = 33k; CTAeH = 10nF; and all outputs unloaded. TA= TJ.
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNITS
Overall S~Jl_current Vee Turn-On Threshold Vee Turn-Off Threshold
Over Operating Range Over Operating Range Over Operating Range
14.5 30.0 mA
8.65 8.95 9.45 v 7.75 8.05 8.55 v
Overvoltage/Coast CV-Coast Inhibit Threshold CV-Coast Restart Threshold CV-Coast Hysteresis CV-Coast Input Current
L~c l'!P_uts H1, H2, H3 Low Threshold H1, H2, H3 High Threshold H1, H2, H3 ln...E._ut Current Quad Sel, Dir Thresholds
Over Operating Range
Over Operating Range Over Operating Range Over Operating Range, to OV Over Operating Range
1.65 1.75 1.85 v 1.55 1.65 1.75 v 0.05 0.10 0.15 v
-10
·1
0
µA
0.8 1.0 1.2
v
1.6 1.9 2.0
v
-400 -250 -120 µA
0.8 1.4 2.0
v
Quad Sel, Dir Hysteresis Quad Sel Input Current Dir Input Current PWM Am_p[Com~ator E/A In(+), E/A In(·) Input Current PWM In Input Current Error Amp Input Offset Error Amp Voltage Gain E/A Out Range SSTART Pull-up Current SSTART Discharge Current SSTART Restart Threshold Gain Level Shift
To2.5V To2.5V
ov < VeoMMON-MODE < 3V
ToOV To2.5V
ISENSE1 = .3V, ISENSE2 = .5Vto .7V ISENSE1 = .3V, ISENSE2 = .3V
70
mV
-30 50 150 µA
-30 ·1
30
µA
·5.0 -0.1 5.0 µA
0
3
30 µA
-10
10 mV
70
90
dB
0.25
3.50 v
-16 -10
·5
µA
0.1 0.4 3.0 mA
0.1 0.2 0.3
v
1.75 1.95 2.15 VN
2.4 2.5 2.65 v
6-40
UC1625 UC3625
ELECTRICAL
Unless otherwise stated, these specifications apply for: TA= 25°C; PWR-Vce =Vee= 12V; Rose=
CHARACTERISTICS: 20kto VREF; Cose= 2nF; RTAeH = 33k; CrAeH = 10nF; and all outputs unloaded. TA= TJ.
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNITS
Current Amp (cont.) Peak Current Threshold Over Current Threshold
ISENSE1 = ov, Force ISENSE2
ISENSE1 = OV, Force ISENSE2
0.14 0.20 0.26 v 0.26 0.30 0.36 v
ISENSE1' ISENSE2 Input Current
ToOV
-850 -320 0
µA
ISENSE1' ISENSE2 Offset Current Range ISENSE1' ISENSE2 Tachometer/Brake Tach-Out High Level Tach-Out Low Level
ToOV
Over Operating Range, 1Ok to 2.5V Over Operating Range, 1Ok to 2.5V
±2 ±12 µA
-1
2
v
4.7
5
5.3
v
0.2
v
On Time On Time Change With Temp
Over Operating Range
170 220 280 ~
.1
%
RC-Brake Input Current Threshold to Brake, RC-Brake Brake Hysteresis, RC-Brake
ToOV Over Operating Range
-4.0 -1.9
mA
O.B 1.0 1.2
v
0.09
v
Speed-In Threshold
Over Operating Range
220 257 290 mV
Speed-In Input Current
-30
-5
30 µA
Low-Side Drivers
Voh, -1mA, Down From Vee V Voh, -50mA, Down From Vee Vol, 1mA Vol, 50mA Rise/Fall Time
Over Operating Range Over Operating Range Over Operating Range Over Operating Range 10% to 90% Slew Time, into 1nF
1.60 2.1
1.75
2.2 -
.
v
0.05 0.4
v
0.36 O.B
v
50
ns
High-Side Drivers Vol, 1mA Vol, 50mA Leak!19.e Current Fall Time
Over Operating Range Over Operating Range Output Voltage = 50V 10% to 90% Slew Time, 50mA Load
0.1
0.4
v
1.0 1.8
v
25 ~
50
ns
Oscillator
Frequency
40
50
60 kHz
Frequency
Over Operating Range
35
65 kHz
Reference Output Voltage Output Voltage Load R~ulation
Over Operating Range OmA to -20mA Load
4.9 5.0 5.1
v
4.7 5.0 5.3
v
-40
-5
mV
Line Regulation Short Circuit Current
10Vto 18VVcc Over Operating Range
-10
-1
10 mV
50 100 150 mA
Miscellaneous
Output Turn-On Delay
1
µs
Output Turn-Off Delay
1
µs
PIN DESCRIPTIONS:
Dir, Speed-In: The position decoder logic translates the Hall signals and the Dir signal to the correct driver signals (PUs and PDs). To prevent output stage damage, the signal on Dir is first loaded into a direction latch, then shifted through a two-bit register. As long as Speed-In is less than 250mV, the direction
latch is transparent. When Speed-In is higher than 250mV, the direction latch inhibits all changes in direction. Speed-In can be connected to Tach-Out through a filter, so that the direction latch is only transparent when the motor is spinning slowly, and has too little stored energy to damage power devices.
6-41
PIN DESCRIPTIONS (cont.):
Additional circuitry detects when the input and output of the direction latch are different, or when the input and output of the shift register are different, and inhibits all output drives during that time. This can be used to allow the motor to coast to a safe speed before reversing. The shift register guarantees that direction can't be changed instantaneously. The register is clocked by the PWM oscillator, so the delay between direction changes is always going to be between one and two oscillator periods. At 40kHz, this corresponds to a delay of between 25µs and SOµs. Regardless of output stage, 25µs dead time should be adequate to guarantee no overlap crossconduction.
E/A In(+), E/A In(-), E/A Out, PWM In: E/A In(+) and E/A In(-) are not internally committed to allow for a wide variety of uses. They can be connected to the ISENSE, to Tach-Out through a filter, to an external command voltage, to a DIA converter for computer control, or to another op amp for more elegant feedback loops. The error amplifier is compensated for unity gain stability, so E/A Out can be tied to E/A In(-) for feedback and major loop compensation. E/A Out and PWM In drive the PWM comparator. For voltage-mode PWM systems, PWM In can be connected to RC-Osc. The PWM comparator clears the PWM latch, commanding the outputs to chop. The error amplifier can be biased off by connecting E/A In(-) to a higher voltage than E/A In(+). When biased off, E/A Out will appear to the application as a resistor to ground. E/A Out can then be driven by an external amplifier.
GND: All thresholds and outputs are referred to the GND pin except for the PD and PU outputs.
H1, H2, H3: The three shaft-position sensor inputs consist of hysteresis comparators with input pull-up resistors. Logic thresholds meet TTL specifications and can be driven by SV CMOS, 12V CMOS, NMOS, or open-collectors. Connect these inputs to motor shaft position sensors that are positioned 120 electrical degrees apart. If noisy signals are expected, zener clamp and filter these inputs with 6V zeners and an RC filter. Suggested filtering components are 1k and 2nF. Edge skew in the filter is not a problem, because sensors normally generate modified Gray code with only one output changing at a time, but rise and fall times must be shorter than 20µs for correct tachometer operation. Motors with 60 electrical degree position sensor coding can be used if one or two of the position sensor signals is inverted.
ISENSE1' ISENSE2, ISENSE: The current sense amplifier has a fixed gain of approximately two. It also has a built-
UC1625 UC3625
in level shift of approximately 2.5 volts. The signal appearing on ISENSE is:
/SENSE= 2.5V + ( 2 *ABS ( /SENSE1 - /SENSE2))
ISENSE1 and ISENSE2 are interchangeable and can be used as differential inputs. The differential signal applied can be as high as ±0.SV before saturation. If spikes are expected on ISENSE1 or ISENSE2, they are best filtered by a capacitor from ISENSE to ground. Filtering this way allows fast signal inversions to be correctly processed by the absolute value circuit. The peak-current comparator allows the PWM to enter a current-limit mode with current in the windings never exceeding approximately 0.2V/RsENSE. The over current comparator provides a fail-safe shutdown in the unlikely case of current exceeding 0.3V/RSENSE. Then, soft start is commanded, and all outputs are turned off until the high current condition is removed. It is often essential to use some filter driving ISENSE1 and ISENSE2 to reject extreme spikes and to control slew rate. Reasonable starting values for filter components might be 250Q series resistors and a SnF capacitor between ISENSE1 and lsENSE2. Input resistors should be kept small and matched to maintain gain accuracy.
OV-Coast: This input can be used as an over-voltage shutdown in put, as a coast input, or both. This input can be driven by TTL, SV CMOS, or 12V CMOS.
PDA, PDB, PDC: These outputs can drive the gates of N-Channel power MOSFETs directly or they can drive the bases of power Darlingtons if some form of current limiting is used. They are meant to drive low-side power devices in high-current output stages. Current available from these pins can peak as high as O.SA. These outputs feature a true totem-pole output stage. Beware of exceeding IC power dissipation limits when using these outputs for high continuous currents. These outputs pull high to turn a "low-side" device on (active high).
PUA, PUB, PUC: These outputs are open-collector, high-voltage drivers that are meant to drive high-side power devices in high-current output stages. These are active low outputs, meaning that these outputs pull low to command a high-side device on. These outputs can drive low-voltage PNP Darlingtons and P-channel MOSFETs directly, and can drive any high-voltage device using external charge-pump techniques, transformer signal coupling, cascode level-shift transistors, or opto-isolated drive. (See applications).
PWR Vee: This supply pin carries the current sourced by the PD outputs. When connecting PD outputs directly to the bases of power Darlingtons, the PWR Vee pin can be current limited with a resistor. Darlington outputs can also be "Baker Clamped" with diodes from collectors back to PWR Vee. (See Applications)
6-42
PIN DESCRIPTIONS (cont.):
Quad Sel: The IC can chop power devices in either of two modes, referred to as "two-quadrant" (Quad Sel low) and "four-quadrant" (Quad Sel high). When two-quadrant chopping, the pull-down power devices are chopped by the output of the PWM latch while the pull-up drivers remain on. The load will chop into one commutation diode, and except for back-EMF, will exhibit slow discharge current and faster charge current. Two-quadrant chopping can be more efficient than four-quadrant. When four-quadrant chopping, all power drivers are chopped by the PWM latch, causing the load current to flow into two diodes during chopping. This mode exhibits better control of load current when current is low, and is preferred in servo systems for equal control over acceleration and deceleration. The Quad Sel input has no effect on operation during braking.
RC-Brake: Each time the Tach-Out pulses, the capacitor tied to RC-Brake discharges from approximately 3.33V down to 1.67V through a resistor. The tachometer pulse
width is approximately T =0.67 RT CT, where RT and CT
are a resistor and capacitor from RC-Brake to ground. Recommended values for RT are 1Ok to 500k, and recommended values for CT are 1nF to 1OOnF, allowing times between 5µs and 1Oms. Best accuracy and stability are achieved with values in the centers of those ranges. RC-Brake also has another function. If RC-Brake pin is pulled below the brake threshold, the IC will enter brake mode. This mode consists of turning off all three highside devices, enabling all three low-side devices, and disabling the tachometer. The only things that inhibit lowside device operation in braking are low-supply, exceeding peak current, OV-Coast command, and the PWM comparator signal. The last of these means that if current sense is implemented such that the signal in the current sense amplifier is proportional to braking current, the low-side devices will brake the motor with current control. (See applications) Simpler current sense connections will result in uncontrolled braking and potential damage to the power devices.
RC-Osc: The UC3625 can regulate motor current using fixed-frequency pulse width modulation (PWM). The RCOsc pin sets oscillator frequency by means of timing resistor Rose from the RC-Osc pin to VREF and capacitor Cose from RC-Osc to Gnd. Resistors 1Ok to 1OOk and capacitors 1nF to 1OOnF will work best, but frequency should always be below 500kHz. Oscillator frequency is approximately:
F = 2 I RoscCosc
Additional components can be added to this device to cause it to operate as a fixed off-time PWM rather than a fixed frequency PWM, using the RC-Osc pin to select the monostable time constant.
UC1625 UC3625
The voltage on the RC-Osc pin is normally a ramp of about 1.2V peak-to-peak, centered at approximately 1.6V. This ramp can be used for voltage-mode PWM control, or can be used for slope compensation in current-mode control.
SsTART: Any time that Vee drops below threshold or the sensed current exceeds the over-current threshold, the soft-start latch is set. When set, it turns on a transistor that pulls down on SSTART. Normally, a capacitor is connected to this pin, and the transistor will completely discharge the capacitor. A comparator senses when the NPN transistor has completely discharged the capacitor, and allows the soft-start latch to clear when the fault is removed. When the fault is removed, the soft-start capacitor will charge from the on-chip current source. SsTART clamps the output of the error amplifier, not allowing the error amplifier output voltage to exceed SsTART regardless of input. The ramp on RC-Osc can be applied to PWM In and compared to E/A Out. With SsTART discharged below 0.2V and the ramp minimum being approximately 1.0V, the PWM comparator will keep the PWM latch cleared and the outputs off. As SSTART rises, the PWM comparator will begin to duty-cycle modulate the PWM latch until the error amplifier inputs overcome the clamp. This provides for a safe and ~ orderly motor start-up from an off or fault condition.
Tach-Out: Any change in the H1 , H2, or H3 inputs loads data from these inputs into the position sensor latches. At the same time data is loaded, a fixed-width 5V pulse is triggered on Tach-Out. The average value of the voltage on Tach-Out is directly proportional to speed, so this output can be used as a true tachometer for speed feedback with an external filter or averaging circuit. Whenever Tach-Out is high, the position latches are inhibited, such that during the noisiest part of the commutation cycle, additional commutations are not possible. Although this will effectively set a maximum rotational speed, the maximum speed can be set above the highest expected speed, preventing false commutation and chatter.
Vee: This device operates with supplies between 1OV and 1BV. Under-voltage lockout keeps all outputs off below 7.5V, insuring that the output transistors never turn on until full drive capability is available. Bypass Vee to ground with an 0.1 µF ceramic capacitor. Using a 1OµF electrolytic bypass capacitor as well can be beneficial in applications with high supply impedance.
VREF: This pin provides regulated 5 volts for driving Halleffect devices and speed control circuitry. VREF will reach +5V before Vee enables, ensuring that Hall-effect devices powered from VREF will become active before the UC3625 drives any output. Although VREF is current limited, operation over 30mA is not advised.
6-43
CROSS CONDUCTION PREVENTION
Edge
Finder
Shift
Reg
PWM Clk
From Decoder
UC1625 UC3625
PUA
The UC3625 inserts delays to prevent cross conduction due to overlapping drive signals. However, some thought must always be given to cross conduction in output stage design because no amount of dead time can prevent fast slewing signals from coupling drive to a power device through a parasitic capacitance.
The UC3625 contains input latches that serve as noise blanking filters. These latches remain transparent through any phase of a motor rotation and latch immediately after an input transition is detected. They
remain latched for two cycles of the PWM oscillator. At a PWM oscillator speed Of 20kHz, this corre-
sponds to SOµs to 1OOµs of blank time which limits maximum rotational speed to 100kRPM for a motor with six transitions per rotation or 50kRPM for a motor with 12 transitions per rotation.
This prevents noise generated in the first 50µs of a transition from propagating to the output transistors and causing cross-conduction or chatter.
The UC3625 also contains six flip flops corresponding to the six output drive signals; One of .these flip flops is set every time that an output drive signal is turned on, and cleared two PWM oscillator cycles after that drive signal is turned off. The output of each flip flop is used to inhibit drive to the opposing output. (see below) In this way, it is impossible to turn on driver PUA and PDA at the same time. It is also impossible for one Of these drivers to turn on without the other driver having been off for at least two PWM oscillator clocks.
TYPICAL CHARACTERISTICS: Oscillator Frequency vs Cose and Rose
1MHz
c ~
~ 100kHz
CD ::I
...._
O"
uI!.!
10kHz ~
N
5
jg
·c:;
0"'
1kHz
"'.·1~
S:~
~-1~
:..;.__, """' ~
100Hz
0.001
0.01
0.1
Tachometer On Time vs RT and CT
100ms
~
10ms
wI ·~
~
~
CD 1ms
b:::: -~-'~
b'.'.l
E F
0c 100m...
~
~
w-~
~
!:::'. ~-,(ff.~i--
~
~
10ms ~
1ps
0.001
0.01
0.1
6-44
TYPICAL CHARACTERISTICS (cont.):
UC1625 UC3625
Supply Current vs Temperature
20~~~-~~~-~~~
181---+---+-+--+----l-+--+----I
< 16 J::::,,,.1'.... I
E 14 >---+----+-L::od---4--~c--+j:-..._,--+---+____,____,
~ ~ c 121---+---+--t---t--=-+=--t--+----I
~ 101---+---+-+--~---l--t---=F"-....l
0...
Q.
a.
e~n
ff 1 1 1 1 1 1 1 1
. 75 -50 ·25 0 25 50 75 100 125 Temperature (°C)
Soft Start Discharge Current vs Temperature
1.25~~~-~~~-~~~
<.$ 1.00
'C
I'\:
~ .751---+--+L",.__.,,+---+--+-+--+---I
~
0
01---+--+-+--+--+-~--+--
·75 ·50 ·25 0 25 50 75 100 125 Temperature (°C)
POWER STAGE DESIGN: The UC3625 is useful in a wide variety of applications, including high-power in robotics and machinery. The power output stages used in such equipment can take a number of forms, according to the intended performance and purpose of the system. Below are four different power stages with the advantages and disadvantages of each shown.
For high-frequency chopping, fast recovery circulating diodes are essential. Six are required to clamp the windings. These diodes should have a continuous current rating at least equal to the operating motor current, since diode conduction duty-cycle can be high. For lowvoltage systems, Schottky diodes are preferred. In higher voltage systems, diodes such as Microsemi UHVP high voltage platinum rectifiers are recommended.
In a pulse-by-pulse current control arrangement, current sensing is done by resistor RT, through which the transistor's currents are passed (Figures A, 8, and C). In these cases, Ro is not needed. The low-side circulating
Soft Start Pull-Up Current vs Temperature
<.:; -7
c ·8
I /
v ~~ .91---+--+---l-+-7"'F-!--"'_---I-+-~
y 0 ·10 1----t--+-"1--,-"-'"+---+-+--+----i
~ _-1~ :=:v=:..d:v=::==:=:=====:=:
~ ·13 l--+--+-t---+--+-+--+---1
-14 1----t--+-+---+-·--+-+--+----I
·15 1---+--+-+---+--+-+--+-· 75 -50 ·25 0 25 50 75 100 125 Temperature (°C)
Current Sense Amplifier Transfer Function
N
~z 3.0
w
"'
\ 17
2.5 ~~~l-~~'~~~~~-cc'
·0.5
0.0
0.5
I SENSE2 · I SENSE {V)
diodes go to ground and the current sense terminals of the UC3625 (ISENSE1 and ISENSE2) are connected to RT through an Re filter. The input bias current of the current sense amplifier will cause a common mode offset volt· age to appear at both inputs, so for best accuracy, keep the filter resistors below 2k and matched.
The current that flows through RT is discontinuous because of chopping. It flows during the on time of the power stage and is zero during the off time. Consequently, the voltage across RT consists of a series of pulses, occurring at the PWM frequency, with a peak value indicative of the peak motor current.
To sense average motor current instead of peak current, add another current sense resistor (Ro in Figure D) to measure current in the low-side circulating diodes, and operate in four quadrant mode (pin 22 high}. The negative voltage across Ro is corrected by the absolute value current sense amplifier. Within the limitations imposed by Table 1, the circuit of Figure B can also sense average current.
6-45
POWER STAGE DESIGN (cont.):
TO +---+--+----+ MOTOR
UC1625 UC3625
TO +---+---+--.--+ MOTOR
CURRENT SENSE+-----+
FIGURE A
CURRENT SENSE+-----+
FIGURE B
TO
+---!---+--.--+ MOTOR
TO +---+---+--- MOTOR
CURRENT SENSE +----
FIGURE C
CURRENT SENSE+-----+--------1
FIGURED
FIGURE A FIGURE B FIGUREC FIGURED
2
QUADRANT
4
QUADRANT
YES YES YES YES
NO YES YES YES
SAFE BRAKING
NO NO YES YES
POWER REVERSE
NO
IN4QUAD MODE ONLY
IN4QUAD MODE ONLY
IN4QUAD MODE ONLY
CURRENT SENSE PULSE BY AVERAGE
PULSE
YES
NO
YES
YES
YES YES
NO YES
6-46
Fast High-Side P-Channel Driver
UC1625 UC3625
Optocoupled N-Channel High-Side Driver
For drives where speed is critical, P-Channel MOSFETs can be driven by emitter followers. Here, both the level shift NPN and the PNP must withstand high voltages. A zener diode is used to limit gate-source voltage on the MOSFET. Aseries gate resistor is not necessary, but always advisable to control overshoot and ringing.
High-voltage optocouplers can quickly drive high-voltage MOSFETs if a boost supply of at least 10 volts greater than the motor supply is provided. To protect the MOSFET, the boost supply should not be higher than 18 volts above the motor supply.
Power NPN High-Side Driver
Power NPN Low-Side Driver +12V
PWR Vee PDA
To Other Channels
Power Darlington
To Current Sense Resistor
For under 200V 2-quadrent applications, a power NPN driven by a small P-Channel MOSFET will perform well as a high-side driver. A high voltage small-signal NPN is used as a level shift and a high voltage low-current MOSFET provides drive. Although the NPN will not saturate if used within its limitations, the base-emitter resistor on the NPN is still the speed limiting component.
This power NPN Darlington drive technique uses a clamp to prevent deep saturation. By limiting saturation of the power device, excessive base drive is minimized and turn-off time is kept fairly short. Lack of base series resistance also adds to the speed of this approach.
6-47
Fast Hi h-Side N-Channel Driver with Transformer Isolation
VMotor
J
7
21--~,_.
UC3725N
8
6 34
100nF
UC1625 UC3625
To Motor
A small pulse transformer can provide excellent isolation between the UC3625 and a high-voltage N-Channel MOSFET while also coupling gate drive power. In this circuit, a UC3724 is used as a transformer driver/encoder that duty-cycle modulates the transformer with a 150kHz pulse train. The UC3725 rectifies this pulse train for gate drive power, demodulates the signal, and drives the gate with over 2 amp peak current.
Both the UC3724 and the UC3725 can operate up to 500kHz if the pulse transformer is selected appropriately. To raise the operating frequency, either lower the
timing resistor of the UC3724 (1 k minimum), lower the timing capacitor of the UC3724 (500pF minimum) or both.
If there is significant capacitance between transformer primary and secondary, together with very high output slew rate, then it may be necessary to add clamp diodes from the transformer primary to +12V and ground. Signal diodes such as 1N4148 are normally adequate.
The UC3725 also has provisions for MOSFET current limiting. Consult the UC3725 data sheet for more information on implementing this.
COMMUTATION TRUTH TABLE
This table shows the outputs of the gate drive and open collector outputs for given hall input codes and direction signals. Numbers at the top of the columns are pin numbers.
These ICs operate with position sensor encoding that has either one or two signals high at a time, never all low or all high. This coding is sometimes referred to as "120° Coding" because the coding is the same as coding with position sensors spaced 120 magnetic degrees about the rotor. In response to these position sense signals, only one low-side driver will turn on (go high) and one high-side driver will turn on (pull low) at anytime.
INPUTS
OUTPUTS
DIR H1 H2 H3 Low-Side
H!g_h-Slde
6 8 9 10 12 13 14 16 17 18
1 0 0 1 LHLLHH
0
L LHLHH
0
0 L LHHLH
0 HL LHLH
0 0HL LHHL
1
0 1 LHLHHL
0
0
L LHHLH
0
0 0 L LHLHH
0
0 LHL LHH
0 0
0 LHLHH L
0 0 1
H L LHHL
0 0 0
H L L H L H
x
L L LHHH
x 0 0 0 L L L HHH
6-48
TYPICAL APPLICATION: A 45V/BA Brushless DC Motor Drive Circuit
UC1625 UC3625
33k 3k
+5V For Hall Sensors
1
+15V
Quad
F~-+---+---+-..---122 D.~l~r-+---+----<l>------1 6
=
1k >ol>--------t
100nF
4k
28
27
'--------<11--125
2 UC3625
2200pF
rBrake 3nF
15 21 26 3 24 23
68k
8 9 10 4 5
VMotor
+
11001'F
IRF9530
To
Motor Required
'\7·-+-z:...- For Brake
And Fast Reverse
IRF532
240Q
------c: 2nF
240'1 From
2nF
SHealnl sors
2nF
o.1n RT
0_10 Required ~ For Average
Rs
Current
Sensing
N-Channel power MOSFETs are used for low-side drivers, while P-Channel power MOSFETs are shown for high-side drivers. Resistors are used to level shift the UC3625 open-collector outputs, driving emitter followers into the MOSFET gate. A 12V zener clamp insures that the MOSFET gate-source voltage will never exceed 12V. Series 1OQ gate resistors tame gate reactance, preventing oscillations and minimizing ringing.
The oscillator timing capacitor should be placed close to pins 15 and 25, to keep ground current out of the capacitor. Ground current in the timing capacitor causes oscillator distortion and slaving to the commutation signal.
The potentiometer connected to pin 1 controls PWM duty cycle directly, implementing a crude form of speed control. This control is often referred to as "voltage mode" because the potentiometer position sets the average motor voltage. This controls speed because steady-state motor speed is closely related to applied voltage.
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. · MERRIMACK; NH 03054 TEL (603) 424-2410 ·FAX (603) 424-3480
Pin 20 {Tach-Out) is connected to pin 7 (SPEED IN) through an RC filter, preventing direction reversal while the motor is spinning quickly. In two-quadrant operation, this reversal can cause kinetic energy from the motor to be forced into the power MOSFETs.
A diode in series with the low-side MOSFETs facilitates PWM current control during braking by insuring that braking current will not flow backwards through low-side MOSFETs. Dual current-sense resistors give continuous current sense, whether braking or running in four-quadrant operation, an unnecessary luxury for two-quadrant operation.
The 68k ohm and 3nF tachometer components set maximum commutation time at 140µs. This permits smooth operation up to 35,000 RPM for four-pole motors, yet gives 140µs of noise blanking after commutation.
6-49
n n INTEGRATED
~CIRCUITS
-UNITRDDE
Phase Locked Frequency Controller
(®)
UC1633 UC2633 UC3633
FEATURES Precision Phase Locked Frequency Control System
Crystal Oscillator
Programmable Reference Frequency Dividers
Phase Detector with Absolute Frequency Steering
Digital Lock Indicator
Double Edge Option on the Frequency Feedback Sensing Amplifier
Two High Current Op-Amps
5V Reference Output
DESCRIPTION The UC1633 family of integrated circuits was designed for use in phase locked frequency control loops. While optimized for precision speed control of DC motors, these devices are universal enough for most applications that require phase locked control. A precise reference frequency can be generated using the device's high frequency oscillator and programmable frequency dividers. The oscillator operates using a broad range of crystals, or, can func,1ion as a buffer stage to an external frequency source.
The phase detector on these integrated circuits compares the reference frequency with a frequency/phase feedback signal. In the case of a motor, feedback is obtained at a hall output of other speed detection device. This signal is buffered by a sense ampilfier that squares up the signal as it goes into the digital phase detector. The phase detector responds proportionally to the phase error between the reference and the sense amplifier output. This phase detector includes absolute frequency steering to provide maximum drive signals when any frequency error exists. This feature allows optimum start-up and lock times to be realized.
Two op-amps are included that can be configured to provide necessary loop filtering. The outputs of the op-amps will source or sink in excess of 16mA, so they can provide a low impedance control signal to driving circuits.
BLOCK DIAGRAM
Additional features include a double edge option on the sense amplifier that can be used to double the loop reference frequency for increased loop bandwidths. A digital lock signal is provided that indicates when there is zero frequency error, and a 5V reference output allows DC operating levels to be accurately set.
Div. 1024
Div. 4/5
Div.
Amplifier
Double Edge Logic
Phase Detector
Lock Indicator
02/93
+5V +VIN Gnd Out
6-50
ABSOLUTE MAXIMUM RATINGS
Input Supply Voltage (+VIN} ........................ +20V Reference Output Current ........................ -30mA Op-Amp Output Currents . . . . . . . . . . . . . . . . . . . . . . . . ±30mA Op-Amp Input Voltages . . . . . . . . . . . . . . . . . . . . . -.3V to +20V Phase Detector Output Current . . . . . . . . . . . . . . . . . . . ±1 OmA Lock Indicator Output Current .................... +15mA Lock Indicator Output Voltage ...................... +20V Divide Select Input Voltages . . . . . . . . . . . . . . . . . -.3V to +1OV Double Edge Disable Input Voltage ............ -.3V to +10V Oscillator Input Voltage ...................... -.3V to +5V Sense Amplifier Input Voltage . . . . . . . . . . . . . . . . .3V to +20V Power Dissipation at TA = 25°C (Note 2 . . . . . . . . . . . 1OOOmW Power dissipation at Tc = 25°C (Note 2) ........... 2000mW Operating Junction Temperature ........... -55°C to+150°C Storage Temperature .................... -65°C to +150°C Lead Temperature (Soldering, 1O Seconds) .......... 300°C
DIL-16 (TOP VIEW)
J or N Package
Div 4/5 Input
DIY 21418
Input Lock Indicator
Output
Phase Detector Output
Dbl Edge Citable Input
Sense Amp Input
SV Rel Output
Loop Amp Inv Input
11 ~~x 1:p~f 10 ~~~.,~:~nput 9 ~0u~~utmp
UC1633 UC2633 UC3633
Note1: Voltages are referenced to ground, (Pin 16). Currents are positive into, negative out of, the specified terminals. Note 2: Consult Packaging Section of Databook for thermal limitations and considerations ofpackage.
CONNECTION DIAGRAMS
PLCC-20 (TOP VIEW) Q Package
~
~
,L'3 2 1 2019
4
18
5
17
6
16
7
15
8
14
9 10 11 12 13
PACKAGE PIN FUNCTION
FUNCTION
PIN
N/C
1
Div4/5 Input
2
Div2J4/s Input
3
Lock Indicator Ou.m_ut
4
Phase Detector Cutout
5
N/C
6
Dbl Ee;!@ Disable Input
7
Sense Amp Input
8
SV Ref Output
9
Loop Amp Inv Input
10
NlC
11
Loop Amp Output
12
Aux Amp Non-Inv Input 13
Aux Am_Q_lnv Input ·-·- 14
Aux Am_Q_ Outi>_ut
1.5. -·
N_LC
16
+VIN
17
OSC Cutout
18
osc ll)Q!,lt
19
Ground
20
ELECTRICAL CHARACTERISTICS: (Unless otherwise stated, these specifications apply for TA= 0°c to +70°C for the
UC3633, -25°C to +85°C for the UC2633, -55°C to+125°C for the UC1633, +VIN =
12V; TA=TJ.)
PARAMETER Supply Current Reference Output Voltage (VREF) Load Regulation Line Regulation Short Circuit Current Oscillator
DCVolt~Gain
Input DC Level (VIB) Input Impedance (Note 3) Output DC Level Maximum Operating Frequency Dividers Maximum Input Frequency Div. 4/5 Input Current
Div. 4/5 Threshold
TEST CONDITIONS +VIN= 15V
ov IOUT = to 7mA
+VIN=8Vto15V VOUT = OV
Oscillator Input to Oscillator Output Oscillator Input Pin Open, TJ = 25°C VIN= VIB ±0.5V, TJ = 25°C Oscillator Input Pin Open, TJ = 25°C
Input= 1VPP at Oscillator Input Input = 5V (Div. by 4) Input = OV (Div. by 5)
MIN. TYP. MAX. UNITS
20
28
mA
v 4.75 5.0 5.25
5.0 20 mV
2.0 20 mV
12
30
mA
12
16
20
dB
v 1.15 1.3 1.45
1.3 1.6 1.9 kQ
1.2 1.4 1.6
v
10
MHz
10
MHz
150 500 µA
-5.0 0.0 5.0 µA
0.5 1.6 2.2
v
Note 3: These impedence levels will vaiy with TJ at about 1700ppm/°C
6-51
UC1633 UC2633 UC3633
ELECTRICAL
(Unless otherwise stated, these specifications apply for TA= 0°C to +70°C for the UC3633,
CHARACTERISTICS (cont.): -25°Cto +85°Cforthe UC2633, -55°Cto +125°Cforthe UC1633, +VIN= 12V; TA=TJ.)
PARAMETER
TEST CONDITIONS
Dividers (cont.) Div. 2/4/8 Input Current
Input = 5V (Div. by_8}_ Input = OV (Div. by 2)
Div. 2/4/8 Open Circuit Voltage
Input Current= OµA (Div. by 4)
Div. by 2 Threshold
Div. by 4 Threshold
Div. by 8 Threshold
Volts BelowVREF
Sense Amplifier
Threshold Voltage Threshold H~teresis Input Bias Current
Percent of VREF Input= 1.5V
Double Edge Disable Input
Input Current
Input = 5V (Disabled) Input = OV (Enabled)
Threshold Voltage Phase Detector
H_!g_h Output Level Low Ou!E_ut Level Mid Output Level
Positive Phase/Freq. Error, Volts Below VREF N~tive Phase/Fr~ Error Zero Phase/Freq. Error, PercentofVREF
High Level Maximum Source Current Low Level Maximum Sink Current Mid Level Output Impedance (Note 3) Lock Indicator Output
VOUT= 4.3V VOUT = 0.7V IOUT = -200 to +200µA, TJ = 25°C
Saturation Voltage
Freq. Error, louT = 5mA
Leakage Current Loo~ Am~ifier
Zero Freq. Error, VouT = 15V
NON INV. Reference Voltage
Percent of VREF
Input Bias Current AVOL
Input= 2.5V
PSRR Short Circuit Current
+V1N = 8Vto 15V Source, VouT = OV
Auxiliary Op-Amp ll!E_ut Offset Vol~e Input Bias Current Input Offset Current
Sink, VouT = 5V
VcM =2.5V VcM=2.5V VCM =2.5V
AVOL
PSRR CMRR Short Circuit Current
+V1N = 8Vto 15V VcM = OVto 10V Source, VouT = OV
Sink, VouT = 5V
Note 3: These impedence levels will val}' with TJ at about 1700ppm/°C
MIN. TYP. MAX. UNITS
150 500 µA
-500 -150
µA
1.5 2.5 3.5
v
0.20 0.8
v
1.5
3.5 v
0.20 0.8
v
27 30 33 %
10
mV
-1.0 -0.2
µA
150 500 µA
-5.0 0.0 5.0 µA
0.5 1.6 2.2
v
0.2 0.5
v
0.2 0.5
v
47
50
53
%
2.0 8.0
mA
2.0 5.0
mA
4.5 6.0 7.5 kQ
0.3 0.45 v
0.1 1.0 µA
47
50
53
%
-0.8 -0.2
µA
60 75
dB
70 100
dB
16 35
mA
16 30
mA
8 mV
-0.8 -0.2
µA
.01
0.1
µA
70 120
dB
70 100
dB
70 100
dB
16
35
mA
16 30
mA
6-52
APPLICATION AND OPERATING INFORMATION Determining the Oscillator Frequency
The frequency at the oscillator is determined by the desired RPM of the motor, the divide ratio selected, the number of poles in the motor, and the state of the double edge select pin.
fosc(Hz) =(Divide Ratio) ·(Motor RPM)· (1/60 SEC/MIN)·
(No. of Rotor Poles/2) · (x 2 if Pin 5 Low)
UC1633 UC2633 UC3633
The resulting reference frequency appearing at the phase detector inputs is equal to the oscillator frequency divided by the selected divide ratio. If the double edge option is used, (Pin 5 low), the frequency of the sense amplifier input signal is doubled by responding to both the rising and falling edges of the input signal. Using this option, the loop reference frequency can be doubled for a given motor RPM.
Recommended Oscillator Configuration Using AT Cut Quartz Crystal
r--1VPP /\/'
I .01µFf\ RMeaqyuiBreed
I
4700
TSopur~iroeuvsent
I ~ Oscillation
I
15
_ ____,
External Reference Frequency Input
7 External Reference
TO 2VPP J ' V+-1 .01µF
Or
-.2VPP to 2V J l . J
Jl.J-1VPP
l
I I
Method for Deriving Rotation Feedback Signal from Analog Hall Effect Device
VREF Output
232k 1%
*VPP
>300mVPP
1%
Low Level
Analog Hall
Output
1.SV
*This signal may require filtering if chopped mode drive scheme is used.
6-53
APPLICATION AND OPERATION INFORMATION Phase Detector Operation The phase detector on these devices is a digital circuit that responds to the rising edges of the detector's tw~ inputs. The phase detector output has three states: a high,
sv state, a low, OV state, and a middle, 2.5V state. In the
high and low states the output impedance of !he _detect~r is low and the middle state output impedence 1s high, typically 6.0kQ. When there is any static frequency difference between the inputs, the detector output is fixed at its high level if the +input (the sense amplifier signal) is greater in frequency, and fixed at its low level if the -input (the reference frequency signal) is greater in frequency.
When the frequencies of the two inputs to the detector are equal, the phase detector switches between its middle state and either the high or low states, depending on the relative phase of the two signals. If the +input is leading in phase then, during each period of the input frequency, the detector output will be high for a time equal to the time difference between the rising edges of the inputs, and will be at its middle level for the remainder of the period. If the phase relationship is reversed, then the detector will go low for a time proportional to the phase difference of the inputs. The resulting gain of the phase
UC1633 UC2633 UC3633
detector. k0, is 5V/4Jt radians or about 0.4V/radian. The dynamic range of the detector is ±2Jt radians.
The operation of the phase detector is illustrated in the figures below. The upper figure shows typical voltage waveforms seen at the detector output for leading and lagging phase conditions. The lower figure is a state diagram of the phase detector logic. In this figure, the circles
represent the 1o possible states of the logic, and the con-
necting arrows represent the transition events/paths to and from these states. Transition arrows that have a clockwise rotation are the result of a rising edge on the +input, and conversely, those with counter-clockwise rotation are tied to the rising edge of the -input signal.
The normal operational states of the logic are 6 and 7 for positive phase error, 1 and 2 for a negative phase error.
States a and 9 occur during positive frequency error, 3
and 4 during negative frequency error. States 5 and 1O occur only as the inputs cross over from the frequency error to a normal phase error only condition. The level of the phase detector output is determined by the logic state as defined in the state diagram figure. The lock indicator output is high, off, when the detector is in states 1, 2, 6, or 7.
Typical Phase Detector Output Waveforms
T
(One Period of
Reference Frequency)
r-1
5V 2.5V
? Sense Amplifier Input Leading Reference Frequency Input
OV ~~~~~~-"'--~~~~~~~
By 90 Degrees
5 V ~~~~~~~~~~~~~~ 2.5V
0
Sense Amplifier Input Trailing Reference
? Frequency Input By 90 Degrees
Phase Detector State Diagram
C on Pha~~slg~t!'~t~~ ~ ~~·l~~ai~g~etector
·Input J
+Input
(Reference) - + (Sense Amp)
Output·5V
I
I
IOutput-2.5VI
Output 0 0V
Digital Lock Indicator High During States 1, 2, 8 and 7.
6-54
APPLICATION AND OPERATION INFORMATION
UC1633 UC2633 UC3633
Suggested Loop Filter Configuration
R1
R2
From Ref.
c1
Filter o-.-'""'r--< >---+------+---<
VIN R2 ·R4 ~
+
I
Loop UC1633
I
Amp
I
VADJ 5V or OV
VOUT
R3 1 + 7wz
-(S)=-·--
V/N
RI 1 + 5/wp
1 W p = R2-C-1
1
Wz=~--~
(R1 + R21 C1
* The static phase error of the loop is easily adjusted by
adding resistor, R4, as shown. To lock at zero phase error R4 is determined by:
R 4 = 2.5V· R3
I tJ. VouTI
Where: ltJ.VouTI =IVouT- 2.5VI
and VouT = DC Operating Voltage At Loop Amplifier Output During Phase Lock
ov If: {VOUT - 2.5) > 0, R4 Goes to
(VouT - 2.5) < O, R4 Goes to 5.0V
Reference Filter Configuration
C1
From
Phase Detector
R1
R2
Output o---JIN'~-~""'~-+----<
VIN
__t_ VOUT
--
(s)
=
1
-~~-~
VIN
t + S 21;, +
WN (J)f.f
UC1633
Auxiliary Op-Amp
Reference Filter Design Aid - Gain Response
10f---~-+--+-+~-+---l--+-~11!---H
aJ
~~II
~ 0.0
~ ~~'50 ~t-::o,~20
-t-
t-
~ c
~
-10 -20
~~:::o.,....~_"1;0
t-----1---t--lf-+-t---+-~_,_'\,~2·1
ttt-
~ -30
~
> -4 0 '-----'---'----''--'-_.__ _.____..___.l___~,_,,
0.1 0.2 0.4 0.6 0.8 1 2 4 6 8 10
Normalized Frequency {co1coN)
Variable Is 1/~ 2 {For R1-R2, 1/~2=C1/C2)
' 1 [ Note: with R1 =Rz, !;, =
Reference Filter Design Aid - Phase Response
.-;;;- 0.0
~ -20
"'CD -40
~ -60
-80
:e.nc -100 -120
..."' -140
..c;
"- -160 -180 0.1 0.2 0.4 0.60.8 1 2
4 6 8 10
Normalized Frequency - (co1coN)
~F:r:a~l1:~~. 1~;2~2=C11C2)
6-55
APPLICATION AND OPERATION INFORMATION Design Example
Lock Indication Output
4.7k
UC1633 UC2633 UC3633
+Vee
KV = .022V-SEC/RAD
KT · 022NM/ AMP
J = 1.5E-3 NM-SEC2
(Includes 3-5" Platters)
~1µ r-- (TANT) -------,
3 -
I
4-Pole I
I
3·Phase Motor
1 I
I I I I I I Output_s ____ .JI
Precision phase locked frequency control of 3-phase motor at 3600 RPM. Drive scheme Is current fed using the UC3620
switch-mode driver for 3- .P motors.
Bode Plots - Design Example Open Loop Response
2 5 10 20 50100 Normalized Frequency · f/f µ - (f µ = 4Hz)
1.) KLF{s) · KRF(s)
N. K<i> · GPD · KT
2.*)
-2 I:>.
J
3.) Combined Overall Open Loop Response
Where:
KLF(s) =Loop Filter Response KRF(s) = Reference Filter Response N = 4 (Using Double Edge Sensing With 4 Pole
Motor) K<i> =Phase Detector Gain (.4V/RAD) GPD = Power Stage Transductance (1 AN) KT= Motor Torque Constant (.022NM/A) J = Motor Moment of Inertia (.0015NM/A- SEC2)
s =2n:jf
*Note: For a current mode driver the electrical time constant, LM I RM, of the motor does not enter into the small signal re-
sponse. If a voltage mode drive scheme is used, then the asymptote, plotted as 2 above, can be approximated by:
N·Kcfi·l<Pa·KT
s 2 ·J·RM
-fTii
KT 2
RM
if: RM>KrVj and, 2n·J·RM<f< 2:n:·LM
= Here: KPa Voltage gain of Driver Stage = RM Motor Winding Resistance = LM Motor Winding Inductance
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. · MERRIMACK, NH 03054 TEL. (603) 424·2410 · FAX (603) 424-3460
6-56
r n I LJ
INTEGRATED CIRCUITS
-uNITRODE
Phase Locked Frequency Controller
UC1634 UC2634 UC3634
FEATURES Precision Phase Locked Frequency Control System Communication Logic for 2-Phase Motors Disable Input for Motor Inhibit Crystal Oscillator Programmable Reference Frequency Dividers
Phase Detector with Absolute Frequency Steering Digital Lock Indicator Two High Current Op-Amps 5V Reference Output
DESCRIPTION
The UC1634 series of devices is optimized to provide precision phase locked frequency control for two phase DC brushless motors. These devices include most of the features of tile general purpose UC1633 Phase Locked Control family and also provide the out-of-phase commutation signals required for driving two phase brushless motors. Only an external power booster stage is required for a complete drive and control system.
The two commutation outputs are open collector devices that can sink in excess of 16mA. A disable input allows the user to simultaneously force both of these outputs to an active low state. Double edge logic, following the sense amplifier, doubles the reference frequency at the phase detector by responding to both edges of the input signal at Pin 7.
BLOCK DIAGRAM
Input
Output
Divide Select
Div. 1024
Div. 5
Div. 2/4/8
Amplifier Double Edge Logic
Two Phase Drive Logic
Phase .----+-i Detector
Lock Indicator '------l2
Buffer Op-Amp.
6/93 6-57
ABSOLUTE MAXIMUM RATINGS (Note 1, 2)
Input Supply Voltage (+VIN) ........................ +20V Reference Output Current . . . . . . . . . . . . . . . . . . . . . . . -30mA Op-Amp Output Currents . . . . . . . . . . . . . . . . . . . . . . . . ±30mA Op-Amp Input Voltages ..................... -.3V to +20V Phase Detector Output Current . . . . . . . . . . . . . . . . . . . ±1 OmA Lock Indicator Output Current . . . . . . . . . . . . . . . . . . . . +15mA Lock Indicator Output Voltage ...................... +20V Divide Select Input Voltage .................. -.3V to +1OV Disable Input Voltage ....................... -.3Vto +10V Oscillator Input Voltage ...................... -.3V to +5V SenseAmplifier Input Voltage ................ -.3V to +20V Driver Output Currents . . . . . . . . . . . . . . . . . . . . . . . . . . +30mA Driver Output Voltages ............................ +20V Power Dissipation at TA= 25°C(Note 2) ........... 1000mW
Power Dissipation at Tc= 25°C (Note 2) ........... 2000mW
Operating Junction Temperature ........... -55°C to +150°C Storage Temperature .................... -65°C to +150°C Lead Temperature (Soldering, 10 Seconds) .......... 300°C
DIL-16, SOIC-16 (TOP VIEW) J or N Package, OW Package
Div. 2/4/8 Input
Lock Indicator Output
Phase Detector Output
Disable Input
Driver A Output
Driver B Output
Sense Amp Input
SV Ref. Output
12
Buffer Output
Amp.
11
Bulfer Input
Amp.
10 Loop Amp. Output
9
Loop Amp. Inv. Input
UC1634 UC2634 UC3634
Note 1: Voltages are referenced to ground, {Pin 16, DIL Package). Currents are positive into, negative out of, the specified terminals. Note 2: Consult Packaging Section ofDatabook for thermal limitations and considerations ofpackage.
CONNECTION DIAGRAMS
PLCC-20 (TOP VIEW) Q Package
La 2 1 2019
4
18
5
17
6
16
7
15
8
14
9 10 11 12 13
PACKAGE PIN FUNCTION
FUNCTION
PIN
N/C
1
DIV 2/4/8
2
Lock Indicator O~ 3
Phase Detector
4
Ou!e_ut
Disable I!!e_ut
5
N/C
6
Driver A Output
7
Driver B Ou!e_ut
8
Sense Am--2_Out_Q_ut
9
5V Ref Ou!e_ut
10
LoQQ_Am_Q_ Inv IQQ!Jt 11
LoQQ_Am_Q_ Out_Q_ut
12
Buffer Am_p_ 11!2_ut
13
Buffer Am..R_O~ut
14
+VIN
15
N/C
16
OSCO~ut
17
OSC ll!E!_Ut
18
Ground
19
DIV 4/5 ll}Qllt
20
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA= 0°C to +70°C for the
UC3634, -25°C to+ 85°C for the UC2634 and -55°C to +125°C for the UC1634, +VIN= 12V. TA=TJ.
PARAMETERS
TEST CONDITIONS
MIN TYP MAX UNITS
S~Current
+VIN= 15V
20
29 mA
Reference Output Volta_g_ej\l_REF)_
v 4.75 5.0 5.25
Load R~ulation
lour = OmA to 7mA
5.0 20 mV
Line R~ulation
+VIN=8Vto15V
2.0 20 mV
Short Circuit Current
VOUT= OV
12
30
mA
Oscillator
DC Volt!l9_e Gain l'!E_Ut DC LevelJY!.aj_
Oscillator In to Oscillator Out Oscillator In Pin Open, TJ = 25°C
12
16
20
dB
v 1.15 1.3 1.45
l'!E_ut l~ance (Note~ Out1>_ut DC Level
VIN= VIB ± 0.5V, TJ = 25°C Oscillator In Pin Open, TJ = 25°C
1.3 1.6 1.9 kQ
1.2 1.4 1.6
v
Maximum 0_E!.rati~Fr~uen~
10
MHz
Dividers
Maximum l".!.2_ut Fr~en~
Input= 1VPP at Oscillator In
10
MHz
Div. 4/5 Input Current
Input= 5V (Div. by 4)
150 500 µA
(Q Package Only, Note 4)
Input = OV (Div. by 5)
-5.0 0.0 5.0 µA
6-58
UC1634 UC2634 UC3634 ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA= 0°C to +70°C for the
UC3634, -25°C to + 85°C for the UC2634 and -55°C to +125°C for the UC1634, +VIN=12V.TA=TJ
PARAMETERS Dlvlden1~ontl_
Div. 4/5 Input Threshold
_{.Q Pack~e On!}',_ Note 1l.
Div. 2/4/8 Input Current
Div. 2/4/8 O~n Current Vo~e Div. ~2 Threshold Div.~4 Threshold Div. bya Threshold Senee Am...e!_Hler Threshold Vo~e Threshold H_l'Steresis l'!E_ut Bias Current Two Phase Drive Out__p_uts, A and B Saturation Vo~ Leak~e Current Disable lnj>_ut Input Current
Threshold Volt~e Phaee Detector
H!9_h O~ut Level Low O~ut Level Mid Out(l_ut Level H!9!1 Level Maximum Source Current Low Level Maximum Sink Current Mid Level O~ut lm~ance_{.Note 3) Lock Indicator OIJ!l>_ut Saturation Volt~ Leak~e Current
Lo~Am~Hler
N INV. Reference Volta~ ln_E>_ut Bias Current AVOL PSRR Short Circuit Current
Buffer O~Am__p_ lr:!E._ut Offset Volt~e Input Bias Current PSRR CMRR Short Circuit Current
TEST CONDITIONS
lr:!E._Ut = 5V (Div. by l!l..
lr:!E._Ut = OV_{.Div. ~~
lr:!E._ut Current= OµAJ..Div. ~1l.
Volts Below VREF
MIN TVP MAX UNITS
0.5 1.6 2.2
v
150 500 ~
-500 -150
µA
1.5 2.5 3.5
v
0.20 0.8
v
1.5
3.5 v
0.20 0.8
v
Percent of VREF
lr:!E._Ut= 1.5V
IOUT= 16mA VOUT= 15V
27
30
33
%
10
mV
-1.0 -0.2
~
0.3 0.6
v
0.1
5.0 ~
l~ut = 5V_lDisabled, A and B Out_!l_uts Active LoY1_
150 500 ~
l~ut = OV_lEnable<&
-5.0 0.0 5.0 ~
0.5 1.6 2.2
v
Positive Phase I Fr1!9: Error, Volts Below VREF Negative Phase I Fr1!9: Error Zero Phase I Fr1!9: Error, Percent of VREF
VOUT= 4.3V VOUT = 0.7V lour= -200 to +200µA, TJ = 25°C
0.2 0.5
v
0.2 0.5
v
47
50
53
%
2.0 8.0
mA
2.0 5.0
mA
4.5 6.0 7.5 kQ
F~ Error, lour= 5mA Zero F~ Error, VOUT= 15V
0.3 0.45 v
0.1
1.0 ~
Percent of VREF Input= 2.5V
+VIN= 8Vto 15V Source, Vour = OV Sink, VoUT = 5V
47
50
53
%
-0.8 -0.2
µA
60 75
dB
70 100
dB
16 35
mA
16 30
mA
VCM=2.5V VCM=2.5V +VIN= 8 to 15V VCM =Oto 10V Source, Vour = OV Sink, VOUT = 5V
8
mV
-0.8 -0.2
~
70 100
dB
70 100
dB
16 35
mA
16 30
mA
Note 3: These impedance levels will val}' with TJ at about 1700ppm/'C.
.
Note 4: This part is also available in a 20 pin plastic leadless chip carrier, Q designator, where a divide by 4/5 select pin is available.
Consult facto!}' for details.
6-59
UC1634 UC2634 UC3634 APPLICATION AND OPERATION INFORMATION (For additional information see UC1633 data sheet)
Design Example:
Precision phased locked frequency control of a 2-phase motor at 3600 RPM. Using the commutation logic on the UC3634, a simple discrete drive scheme is possible.
Lock lndica ti on Output
Motor Disable
Input
4.91520MHz
R10
10pF
~H
+Vee
+12V IN
UC3634 Phased Lock Controller
RS
R7
ASENSE
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. · MERRIMACK, NH 03054 TEL. (603) 424-2410 · FAX(603) 424-3460
6-60
n n L:::::Jj
INTEGRATED CIRCUITS
-UNITRCDE
Phase Locked Frequency Controller
UC1635 UC2635 UC3635
FEATURES
DESCRIPTION
Precision Phase Locked Frequency Control System
The UC1635 family of integrated circuits was designed for use in precision speed control of DC motors. An extension to the UC1633 line of
Crystal Oscillator
phase locked controllers, these devices provide access to both of the
Programmable Reference Frequency Dividers
digital phase detector's inputs, and include a reference frequency divider output pin. With this added flexibility, this family of controllers can be used to obtain phase synchronization of multiple motors.
~re~Tn~etector with Absolute Frequency A reference frequency can be generated using the device's crystal oscil-
Separate Divider Outputs and Phase Detector Input Pins
lator and programmable dividers. The oscillator operates using a broad range of crystals, or, can function as a buffer stage to an external frequency source.
Double Edge Option on the Frequency Feedback Sensing Amplifier
Two High Current Op Amps
The phase detector responds proportionally to the phase error between the detector's minus input pin and the sense amplifier output. This phase detector includes absolute frequency steering to provide maxi-
5V Reference Output
mum drive signals when any frequency error exists. This feature allows optimum start-up and lock times to be realized.
Two op-amps are included that can be configured to provide necessary loop filtering. The outputs of these op-amps will source or sink in excess of 16mA, so they can provide a low impedance control signal to driving circuits.
BLOCK DIAGRAM
Additional features include a double edge option on the sense amplifier that can be used to double the loop reference frequency for increased loop bandwidths. A 5V reference output can be used to accurately set DC operating levels.
osc osc
Output
141-------------1
Div 10240
Phase 4 Detector
Output
Dbl Edge
Disable 5 t--"'-"""'""---1__./ Input
12/92
Loop Amp Output
1-------17
Loop Amp Inv Input
SV Rel +VINGround Output
6-61
Auxiliary Op-Amp
Aux Amp 10 Non-Inv Input 11 Aux Amp
Inv Input
Aux Amp Output
UDG-92019
UC1635 UC2635 UC3635
ABSOLUTE MAXIMUM RATINGS Input Supply Voltage (+VIN) .................... +20V Reference Output Current ..........·.......... -30mA Op-Amp Output Currents . . . . . . . . . . . . . . . . . . . . :t30mA Op-Amp Input Voltages . . . . . . .. . .. . .. . . . . -0.3 to +20V Phase Detector Input Voltage . . . . . . . . . . . . . -0.3V to +5V Phase Detector Output Current ......·......... :t10mA Lock Indicator Output Current . . . . . . . . . . . . . . . . . +15mA Lock l.ndlcator Output Voltage ................... +20V Divide Select Input Voltages . . . . . . . . . . . . -0.3V to +1OV Double Edge Disable Input Voltage . . . . . . . -0.3V to +1OV Oscillator Input Voltage ....... ; . . . . . . . . . . -0.3V to +5V Sense Amplifier Input Voltage . . . . . . . . . . . . -0.3V to +20V Power Dissipation at TA= 25°C, (Note 2)........ 1000mW Power Dissipation atTc = 25°C, (Note 2) ....... 2000mW Operating Junction Temperature . . . . . . . . . -55° to 150°C Storage Temperature . . . . . . . . . . . . . . . . . -65° to +150°C Lead Temperature,(Solderlng, 10 Seconds) ....... 300°C
Note 1: Voltages are referenced to ground, (Pin 16). Currents
are positive into, negative out of, the specified terminals.
Note 2: Consult Unitrode'/ntegrated Circuits databook for information regarding thermal specifications and.limitations of packages.
CONNECTION DIAGRAMS
501~16 (Top View) OW Package
Phase Detector -Input
~~::~1 3
Phase Detector 4 Output
Dbl Edge
Disable Input 5
Senae 1Anpmupt 8
11
Aux Amp Inv Input
5V Ref Output 7
Aux Amp 10 Non·lnv Input
Loop Amp 8
9 Loop Amp
Inv lnput-,1...L._ _ _ _ _ __ J - Output
DIL-16 (Top View) J & N Packages
Div 2/4
Phaaa Detector -Input
Divider Output Phase Detector Output Dbl Edge Dlaable Input Sense Amp
Input 5V Ref Output Loop Amp Inv Input
PLCC-20 & LCC-20
(Top View) Q & L Packages
La 2 1 2019
4
18
5
17
6
16
7
15
8
14
9 10 11 12 13
PACKAGE PIN FUNCTION
FUNCTION
PIN
Nic
1
DlviM
2
Phase Detector lnout
3
DMder OUtDut
4
Phase Detector OUtDut 5
N&
6
Dbl Eda!!_Dlsable lrnLut 7
Sense AmJtlrnLut
8
5V Ref 011tnut
9
Looo Amo Inv lnout
10
NJC
11
Looo Amo OUtDut
12
Aux Amo Non-Inv lnout 13
Aux Amo Inv lnout
14
Aux Amo Outout
15
I>!&:
16
+VIN
17
OSCOutDUt
18
OSClnout
19
Ground
20
ELECTRICAL
Unless otherwise stated, specifications hold for TA= 0°c to +70°C for the UC3635, ·25°C to +85°C for
CHARACTERISTICS: the UQ2635 and ·55°C to+125°C for the UC1635, +VIN = 12V. TA= TJ.
PARAMETER Supply Current Reference Output Voltage (VREF) Load Regulation Line Regulation Short Circuit Current
+VIN= 15V
TEST CONDITIONS
lour = Oto 7mA +VIN= 8to15V VOUT=OV
MIN TVP MAX UNITS 20 28 mA
v 4.75 5.0 5.25
5.0 20 mV
2.0 20 mV
15 35
mA
6-62
UC1635 UC2635 UC3635
ELECTRICAL
Unless otherwise stated, specifications hold for TA= o·c to +70°C for the UC3635, -25°C to +85°C
CHARACTERISTICS: for the UC2635 and -55°C to +125°C for the UC1635, +Vin= 12V. TA= TJ.
PARAMETER Oaclllator
DC Voltage Gain Input DC Level (VIB) Input Impedance (Note 2) Output DC Level Maximum Operating Frequency Dividers Maximum Input Frequency Div 2/4 Input Current
Div 2/4 Threshold Divider Output
TEST CONDITIONS
Oscillator Input to Oscillator Output Oscillator Input Pin Open, TJ = 25°C VIN= VIB ±0.5V, TJ = 25°C Oscillator Input Pin Open, TJ = 25°C
Input= 1Vpp at Oscillator Input Input = 5V (Div. by 2) Input = OV (Div. by 4)
High Level (w/6.8k Load to GND)
MIN TVP MAX UNITS
12
16
20
dB
1.15 1.3 1.45
v
1.3 1.6 1.9 kQ
1.2 1.4 1.6
v
10
MHz
10
MHz
150 500 µA
-5.0 0.0 5.0 µA
0.5
1.6 2.2
v
4.0 4.5
v
Sense Ampllfler Threshold Voltage
Sense Ampllfler (cont.) Threshold Hysteresis Input Bias Current
Double Edge Disable Input Input Current
Threshold Voltage Phase Detector
-Input Threshold
Low Level (Open Collector Leakage) Percent of VREF
Input= 1.5V Input= 5V (Disabled) Input = OV (Enabled)
Detector Responds to Falling Edge
10 µA
27
30
33
%
10
µV
-1.0 -0.2
µA
150 500 µA
-5.0 0.0 5.0 µA
0.5 1.6 2.2
v
0.5 1.6 2.2
v
-Input Current
Input= 2.2V
High Output Level
Positive Phase/Freq. Error, Volts Below VREF
Low Output Level
Negative Phase/Freq. Error
Mid Output Level
Zero Phase/Freq. Error, Percent of VREF
High Level Maximum Source Current
VOUT =4.3V
Low Level Maximum Sink Current VOUT 0.7V
Mid Level Output Impedance (Note 3)
IOUT = -200 to +200µA, TJ = 25°C
Loop Ampllfler
100 250 µA
0.2 0.5
v
0.2 0.5
v
47
50
53
%
2.0 8.0
mA
2.0 5.0
mA
4.5 6.0 7.5 kQ
Non-Inv Reference Voltage Input Bias Current AVOL PSRR Short Circuit Current
Percent of VREF Input= 2.5V
+VIN= 8 to 15V Source, VOUT = OV Sink, VouT = 5V
47
50
53
%
-0.8 -0.2
µA
60
75
dB
70 100
dB
16 35
mA
16
30
mA
Note 3: These impedance levels will vaty with TJ at about 1700ppm/°C.
6-63
UC1635 UC2635 UC3635
ELECTRICAL
Unless otherwise stated, specifications hold for TA= 0°C to +70°C for the UC3635, -25°C to +85°C
CHARACTERISTICS: for the UC2635 and-55°Cto +125°Cforthe UC1635, +Vin= 12V. TA= TJ.
PARAMETER Auxiliary Op-Amp
Input Offset Voltage Input Bias Current Input Offset Current AVOL PSRR CMRR Short Circuit Current
TEST CONDITIONS
VcM =2.5V VCM=2.5V VcM =2.5V
+VIN= 8 to 15V VcM =Oto 10V Source, VouT = OV Sink, VOUT = 5V
MIN TYP MAX UNITS
8
mV
-0.8 -0.2
t.IA
.01 0.1 t.IA
70 120
dB
70 100
dB
70 100
dB
16 35
mA
16 30
mA
Application and Operation lnfonnatlon {For Additional Application lnfonnatlon see the UC1633 Data Sheet)
(Pin numbers refer to OIL and SOIC packages)
Phase Detector Input
Phase Detector
Input - i = 2 . 2 TO 5V
0 TO 0.5V
Reference
To Load
I
20k
: UC1635
I
L--
UDG-92012
Reference Divider Out ut Detail
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. · MERRIMACK. NH 03054 TEL. (603) 424-2410 ·FAX (603) 424-3480
5V Reference 20k
From Logic
Divider
Output (Note)
I UC1635 I
I
2~--...J
I
- - _J
UDG-92011
6-64
n n Ll=:'.J INTECJRATEO CIRCUITS
- UNITROCE
((Q))
Switched Mode Controller for DC Motor Drive
UC1637 UC2637 UC3637
FEATURES Single or Dual Supply Operation ± 2.5V to ± 20V Input Supply Range ± 5% Initial Oscillator Accuracy; ± 10% Over Temperature Pulse-by-Pulse Current Limiting Under-Voltage Lockout Shutdown Input with Temperature Compensated 2.5V Threshold Uncommitted PWM Comparators for Design Flexibility Dual 1OOmA, Source/Sink Output Drivers
BLOCK DIAGRAM
DESCRIPTION The UC1637 is a pulse width modulator circuit intended to be used for a variety of PWM motor drive and amplifier applications requiring either uni-directional or bidirectional drive circuits. When used to replace conventional drivers, this circuit can increase efficiency and reduce component costs for many applications. All necessary circuitry is included to generate an analog error signal and modulate two bi-directional pulse train outputs in proportion to the error signal magnitude and polarity.
This monolithic device contains a sawtooth oscillator, error amplifier, and two PWM comparators with ±1 OOmA output stages as standard features. Protection circuitry includes under-voltage lockout, pulse-by-pulse current limiting, and a shutdown port with a 2.5V temperature compensated threshold.
The UC1637 is characterized for operation over the full military temperature range of -55°C to +125°C, while the UC2637 and UC3637 are characterized for -25°C to +85°C and 0°c to +70°C, respectively.
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage (±Vs) ................................................... ±20V Output Current, Source/Sink (Pins 4, 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mA Analog Inputs (Pins 1, 2, 3, 8, 9, 10, 11 12, 13, 14, 15, 16) ....................... ±Vs
Error Amplifier Output Current (Pin 17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20mA Oscillator Charging Current (Pin 18)................................ · · · · · · · -2mA Power Dissipation at TA = 25°C (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1OOOmW Power Dissipation at Tc = 25°C (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000mW Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C Lead Temperature (Soldering, 10 Seconds)................................ +300°C Note 1: Currents are positive into, negative out of the specified terminal. Note 2: Consult Packaging Section of Databook for thermal limitations and considerations
o f package.
~
I
SHUTDOWN
6/93
E/A OUTPUT
-C/L +C/L 9 8 Note: Fault latches are reset dominant. ·BIN +BIN
6-65
CONNECTION DIAGRAM DIL-18 (TOP VIEW) J or N Package
+VFH CT
-Vs +Vs
ISET E/A
OUTPUT
·EIA
+EIA
SHUT·
DOWN ·C/L
+C/L
·AIN
SOIC-20 (TOP VIEW) OW Package
+VTH 1
PLCC-20, LCC-20 (TOPVIEW) Q, L Packages
L3 2 1 2019
4
18
5
17
6
16
7
15
8
14
9 10 11 12 13
UC1637 UC2637 UC3637
PACKAGE PIN FUNCTION
FUNCTION
PIN
+VTH
1
Cr
2
-VTH
3
Aour
4
-Vs
5
N/C
6
+Vs
7
Bour
8
+BIN
9
·BIN
10
-AIN
11
+AIN
12
+C/l
13
-C/l
14
SHUTDOWN 15
N/C
16
+E/A
17
-E/A
18
E/AOUTPUT 19
ISET
20
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA= -55°C to+125°C for the
UC1637; -25°C to +85°C for the UC2637; and 0°c to +70°C for the UC3637; +Vs= +15V, -Vs= -15V, +VTH = 5V, -VTH = -5V, RT= 16.7kQ, Cr= 1500pF, TA=TJ.
PARAMETER
TEST CONDITIONS
Oscillator Initial Accuracy Voltage Stability
Temperature Stability +VTH Input Bias Current -VTH Input Bias Current +VTH, -VTH Input Range Error Amplifier Input Offset Voltage Input Bias Current Input Offset Current Common Mode Range Open Loop Voltage Gain Slew Rate Un~ Gain Bandwidth CMRR PSRR
TJ= 25°C Vs= ±5V to ±20V, VPIN 1 = 3V, VPIN3 = -3V Over Operating Range (Note 3) VPIN2 = 6V VPIN2= OV
VcM =OV VCM=OV VCM =OV Vs = ±2.5 to 20V AL= 10k
Over Common Mode Range Vs = ±2.5 to ±20V
UC1637/UC2637
UC3637
UNITS
MIN TYP MAXJ MIN TYP MAX
9.4 10 10.6 9
5
7
10
11
kHz
5
7
%
0.5
2
0.5
2
%
-10 0.1
10 -10 0.1
10
µA
-10 -0.5
-10 -0.5
µA
+Vs-2
-Vs+2 +Vs-2
-Vs+2 v
1.5
5
1.5 10 mV
0.5
5
0.5
5
µA
0.1
1
0.1
1
µA
-Vs+2
+Vs -Vs+2
+Vs v
75 100
80 100
dB
15
15
V/µs
2
2
MHz
75 100
75 100
dB
75 110
75 110
dB
6-66
UC1637 UC2637 UC3637
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA = -55°C to +125·c for the
uc1637; -25°C to +85°C for the UC2637; and o·c to +70°C for the UC3637: vs= +15V, -Vs= - 15V, +VTH = 5V, -VTH = -5V, RT= 16.7kQ, CT= 1500pF, TA=TJ.
PARAMETERS
TEST CONDITIONS
UC1637/UC2637
UC3637
UNITS
MIN TYP MAX MIN TYP MAX
Error Amplifier (Continued) O~ut Sink Current Output Source Current High Level Output Voltage Low Level Output Voltage
PWM Comparators
VPIN 17 = OV VPIN 17 = OV
-50 -20
5
11
13 13.6
-14.8 -13
-50 -20 mA
5
11
mA
13 13.6
v
-14.8 -13
v
Input Offset VoltaJ!..e
VCM=OV
20
20
mA
Input Bias Current ll!E_ut l!tsteresis Common Mode range Current Limit
VcM=OV VCM=OV Vs = ±5V to ±40V
-Vs+1
2
10
10
+Vs-2 -Vs+1
2
10 !AA
10
mV
+Vs-2 v
Input Offset Voltage Input Offset Voltage T.C. Input Bias Current Common Mode Range
VcM = ov, TJ = 25°C Vs = ±2.5V to ±20V
190 200 210 180 200 220 mV
-0.2
-0.2
mvrc
-10 -1.5
-10 -1.5
!AA
-Vs
+Vs-3 -Vs
+Vs-3 v
Shutdown
Shutdown Threshold Hysteresis Input Bias Current Under-Voltage Lockout
(Note 4) VPIN 14 = +Vs to -Vs
-2.3 -2.5 -2.7 -2.3 -2.5 -2.7 v
40
40
mV
-10 -0.5
-10 -0.5
~
Start Threshold
(Note 5)
4.15 5.0
4.15 5.0
v
Hysteresis
0.25
0.25
mV
Total Standby Current
Supply Current
8.5 15
8.5 15 mA
Output Section Output Low Level
ISINK=20mA
-14.9 -13
-14.9 -13
v
Output High Level Rise Time
ISINK = 1OOmA !SOURCE = 20mA !SOURCE= 100mA (Note 3) CL= Inf, TJ = 25°C
-14.5 -13
-14.5 -13
13 13.5
13 13.5
v
12 13.5
12 13.5
100 600
100 600 ns
Fall Time
(Note 3) CL= Inf, TJ = 25°C
100 300
100 300 ns
Note 3: These parameters, although guaranteed over the recommended operating conditions, are not .100% tested in production. Note 4: Parameter measured with respect to +Vs (Pin 6). Note 5: Parameter measured at +Vs (Pin 6) with respect to -Vs (Pin 5).
FUNCTIONAL DESCRIPTION
Following is a description of each of the functional blocks shown in the Block Diagram.
Oscillator The oscillator consists of two comparators, a charging and discharging current source, a current source set terminal, lsET and a flip-flop. The upper and lower threshold of the oscillator waveform is set externally by applying a voltage at pins +VTH and -VTH respectively. The +VTH ter-
minal voltage is buffered internally and also applied to the ISET terminal to develop the capacitor charging current through RT. If RT is referenced to -Vs as shown in Figure 1, both the threshold voltage and charging current will vary proportionally to the supply differential, and the oscillator frequency will remain constant. The triangle waveform oscillators frequency and voltage amplitude is determined by the external components using the formulas given in Figure 1.
6-67
UC1637 UC2637 UC3637
-7'\--7\.--+VTH
/ __ y_ __~-VTH
(+VTH )-(-Vs)
Is =
RT
Is f · 2Cr[(+VTH )-(-VTH ))
+VTH
= (-Vs)
+ (
((+Vs
)-(-Vs)} (R2+R3)) R1+R2+R3
/((+Vs)-(-Vs)) (R3)) -VTH = (-Vs) + \ R1+R2+R3
Figure 1. Oscillator Setup
PWM Comparators
Two comparators are provided to .perform pulse width
+Vs
modulation for each of the output drivers. Inputs are un-
committed to allow maximum flexibility. The pulse width of
the outputs A and B is a function of the sign and ampli-
tude of the error signal. A negative signal at Pin 1o and a
B
will lengthen the high state of output A and shorten the high state of output B. Likewise, a positive error signal re-
ERROR SIGNAL
(PIN 17)
verses the procedure. Typically, the oscillator waveform is
A
compared against the summation of the error signal and
the level set on Pin 9 and 11.
-Vs
MODULATION SCHEMES
Case A Zero Deadtime (Equal voltage on Pin 9 and Pin 11) In this configuration, maximum holding torque or stiffness and position accuracy is achieved. However, the power input into the motor is increased. Figure 3A shows this configuration.
Case B Small Deadti.me (Voltage on Pin 9 >Pin 11) A small differential voltage between Pin 9 and 11 provides the necessary time delay to reduce the chances of momentary short. circuit in the output stage during transitions, especially where power-amplifiers are used. Refer to Figure3B.
Case C Increased Deadtime and Deadband Mode (Voltage on Pin 9 > Pin 11) With the reduction of stiffness and position accuracy, the power input into the motor around the null point of the servo loop can be reduced or eliminated by widening the window of the comparator circuit to a degree of acceptance. Where position accuracy and mechanical stiffness is unimportant, deadband operation can be used. This is shown in Figure 3C.
Figure 2. Comparator Biasing
Output Drivers Each output driver is capabla of both sourcing and sinking
1OOmA steady state and up to 500mA on a pulsed basis
for rapid switching of either POWERFET or bipolar tran-
sistors. Output levels are typically -Vs + 0.2V @50mA
low level and +Vs - 2.0V @50mA high level.
Error Amplifier The error amplifier consists of a high slew rate (15V/fJS) op-amp with a typical 1MHz bandwidth and low output impedance. Depending on the ±Vs supply voltage, the common mode input range and the voltage Output swing is within 2V of the Vs supply.
Under-Voltage Lockout An under-voltage lockout circuit holds the outputs in the low state llntil a minimum of 4V is reached. At this point, all internal circuitry is functional and the output drivers are enabled. If external circuitry requires a higher starting voltage, an over-riding voltage can be programmed through the shutdown terminal as shown in Figure 4.
6-68
UC1637 UC2637 UC3637
(Pins 11,9) \
(Pins 8,11)
/
~
(A)
(Pin 9) -~-~-~
(Pin 11) L_:::..L_:::..L_~
BOUT------ADUT - - - - - - -
(Pins 9)~
_
_
(Plna11)~
siWL-n-
~ --f 1--DEADTIME
(B)
(Pin9)~
(Pin 11> --H---H---H--
~ eauT
(Pin 9)-------------
(Pln 11)~-
I II II I I II II I I BOUT I I I I I
AOUT - - - - - - -
AouTULJLJ-
(C)
Figure 3. Modulation Schemes Showing (A) Zero Deadtime (B) Deadtime and (C) Deadband Configurations
Shutdown Comparator The shutdown terminal may be used for implementing various shutdown and protection schemes. By pulling the terminal more than 2.5V below VIN, the output drivers will be enabled. This can be realized using an open collector gate or NPN transistor biased to either ground or the negative supply. Since the threshold is temperature stabi-
lized, the comparator can be used as an accurate low
voltage lockout (Figure 4) and/or delayed start as in Figure 5. In the shutdown mode the outputs are held in the low state.
UC1637
_2.,~w +Vs --------.,
+Vs
1------114 SHUTDOWN
-Vs
= VSTART
2.5(R1+R2) R1
UC1637
Figure 5. Delayed Start-Up
-Vs to within 3V of the +Vs supply while providing excellent noise rejection. Figure 6 shows a typical current sense circuit.
R1
R2 -Vs
Figure 4. External Under-Voltage Lockout
Current Umit A latched current limit amplifier with an internal 200mV offset is provided to allow pulse-by-pulse current limiting.
Differential inputs will accept common mode signals from
Figure 6. current Limit Sensing
6-69
+24V
0.111F
.....
a0 : Iz -
10k
0
0
cww
10k
Q.
U) 10k
Figure 7. Bi-Directional Motor Drive with Speed Control Power-Amplifier
UC1637 UC2637 UC3637
+5V
9,6,11
4
5,12
L298 7,10
1,15
8
1k
-
-
POSITION
COMMAND VOLTAGE
POSITION FEEDBACK VOLT AGE
Figure 8. Single Supply Position Servo Motor Drive
UNITROOE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. · MERRIMACK, NH 03054 TEL. (603) 424-2410 ·FAX (603) 424-3460
6-70
n n LL='._j
INTE13RATED CIRCUITS
-UNITRODE
Stepper Motor Drive Circuit
(®) UC1717 UC3717
FEATURES Half-step and Full-step Capability
Bipolar Constant Current Motor Drive
Built-in Fast Recovery Schottky Commutating Diodes
Wide Range of Current Control 5-1 OOOmA
Wide Voltage Range 10-45V
Designed for Unregulated Motor Supply Voltage
DESCRIPTION The UC3717 has been designed to control and drive the current in one winding of a bipolar stepper motor. The circuit consists of an LSTTL-compatible logic input, a current sensor, a monostable and an output stage with built-in protection diodes. Two UC3717s and a few external components form a complete control and drive unit for LSTTL or micro-processor controlled stepper motor systems.
The UC1717SP is characterized for operation over the full military
temperature range of -ss0 c to +125°C, while the UC3717 is charac-
terized for 0°c to +10°c.
Current Levels can be Selected in Steps or Varied Continuously
Thermal Overload Protection
ABSOLUTE MAXIMUM RATINGS (Note 1)
Voltage Logic Supply, Vee ........................................ 7V Output Supply, VM ....................................... 45V
Input Voltage Logic Inputs (Pins 7, 8, 9) .................................. 6V Analog Input (Pin 10) .................................... Vee Reference Input (Pin 11) .................................. 15V
Input Current
Logic Inputs (Pins 7, 8, 9) ............................... -10mA Analog Inputs (Pins 10, 11) .............................. -1 OmA Output Current (Pins 1, 15)................................. ±1A Junction Temperature, TJ ............................... +150°C Storage Temperature Range, Ts .................. -55°C to +150°C
Note 1: All voltages are with respect to ground, Pins 4,5, 12, 13. Pin numbers refer to DIL-16 package. Currents are positive into, negative out of the specified terminal. Note 2: Consult Packaging Section of Databook for information on thermal limitations and considerations of package.
BLOCK DIAGRAM
vcc
~------~61---------------~
Vee
3,14 VM
Monostable !OFF· 0.69 RTCT
~--------12 1-----------1161---U-C-37-1-7 --'
Current
Timing
Emitters
5/93
6-71
CONNECTION DIAGRAMS DIL-16 (TOP VIEW) JP or N Package
BOUT Timing
VM Gnd Gnd Vee
11 Phase
UC1717 UC3717
PLCC-20 (TOP VIEW) Q Package
L3 2 1 201e
4
18
5
17
6
16
7
15
8
14
9 10 11 12 13
PACKAGE PIN FUNCTION
FUNCTION
PIN
N_LC
1
BoUT
2
Timil'.!Q..
3
VM
4
Gnd
5
Nl_C
6
Gnd
7
Vee
8
11
9
Phase
10
Ill.LC
11
lo
12
Current
13
VA
14
Gnd
15
Ill.LC
16
Gnd
17
Vm
18
AoUT
19
Emitters
20
RECOMMENDED OPERATING CONDITIONS
PARAMETER Sllj)j)ly_Volta~. Vee
MIN TVP MAX 4.75 5 5.25
Sllj)j)ly_VoltaJl.e VM
10
40
Ou.!E_ut Current. IM
20
800
Rise Time l,Qgic 11.!Q.uts, tR
2
Fall Time LQgic lf!Q.uts, tF
2
Ambient Tem~rature TA
UC1717
-55
125
UC3717
0
70
UNITS
v v
mA
~ ~
·c ·c
ELECTRICAL CHARACTERISTICS Over recommended operating conditions, unless otherwise specified, TA= TJ.
PARAMETER
TEST CONDITIONS
MIN
Sl!E2!Y_Current Ice
H!g_h-Level IQE_utVolt~e Pins 7, 8, 9
2.0
Low-Level Input Vol~. Pins 7, 8, 9
H!g_h-Level IQE_ut Current, Pins 7, 8, 9
V1 =2.4V
Low Level IQE..ut Current Pins 7 8, 9
V1=0.4V
-0.4
Comparator Threshold Voltage
lo= 0, 11 = 0, VR = 5.0V
390
lo= 1, 11 = 0, VR = 5.0V
230
lo= 0 11 = 1 VR = 5.0V
65
Com~ator IQE_ut Current
-20
Out_Q.ut Leak~e Current
10=1, 11=1, TA= +25°C
Total Saturation Volta_g_e Drqf?_
IM= 500mA
Total Power Dissipation
IM= 500mA fs = 30kHz
IM = 800mA, fs = 30kHz
Cut Off Time tOFF
VM = 1OV, tON>: ~See F.!g_ure 5 and fil_
25
Turn Off DelliY, to
TA= +25°C; dVc/dt >: 50mV~See FJgure 5 and fil_
Thermal Shutdown Junction Tem_Q.erature
+160
TVP
420 250 80
1.4 2.9 30 1.6
MAX 25
0.8 20
440 270 90 20 100 4.0 2.1 3.1 35 2.0 +180
UNITS
mA
v v
~ mA
mV
mV
mV
~ µA
v w w
~ _IA._S
·c
6-72
Figure 1
Ambient Temperature - ('CJ
UC1717 UC3717
4 TA·25°C 1--+--+-+--+---+--+--+-~~-l
~ 3 1--+--+-+-+---+--+--+---+----+--l
!I:
0 ....J
":;j 2
I"""'
~ w
y l--t---+---+-+-+--:J..-~ir'------1-f---1
~ 1
0.1
0.5
0.8
Output Current (A)
Figure 3: Typical Sink Saturation Voltage vs Output Current
4 1--,__,---t---+---+--+-T~A_=~25_0~C_,
~
I
3 .t::.
1--+-+-+---+--+--+--+--+--+--l
C>
J:
0.1
0.5
0.8
Output Current (A)
Figure 2: Typical Source Saturation Voltage vs Output Current
4 TA-25°C 1--+--+-+---+--+--+---+--~~-f
~
.2 s l--+--+--+--+--+--+--4v~:A....._-+-_,
-:;;
..Ll '
l
o
2 l--+--+-+---+--.h'J.L~v___,_l--+----4
iii
!I: 1
0 D..
~
0.2 0.4 0.6 0.8 Output Current (A)
Figure 4: Typical Power Losses vs Output Current
FUNCTIONAL DESCRIPTION The UC3717 drive circuit shown in the block diagram includes the following functions:
(1) Phase Logic and H-Bridge Output Stage (2) Voltage Divider with three Comparators for current control (3) Two Logic inputs for Digital current level select (4) Monostable for off time generation
Input Logic: If any of the logic inputs are left open, the circuit will treat it as a high level input.
Phase Input: The phase input terminal, pin 18, controls the direction of the current through the motor winding. The Schmidt-Trigger input coupled with a fixed time delay assures noise immunity and eliminates cross conduction in the output stage during phase changes. A low level on the phase input will turn 02 on and enable 03 while a high level will turn 01 on and enable 04. (See Figure 7).
Output Stage: The output stage consists of four Darlington transistors and associated diodes connected in an H-Bridge configuration. The diodes are needed to provide a current path when the transistors are being switched. ·For fast recovery, Schottky diodes are used
Chopping Frequency· 1 toN+toFF
B VoltaO ge UtoT N -A toFF O~T
(Pin 1, 15) I I
- i11r t o
Emitter Voltage (Pin 16)
Figure 5: Connections and Component Values as in Figure 6.
across the source transistors. The Schottky diodes allow the current to circulate through the winding while the sink transistors are being switched off. The diodes across the sink transistors in conjunction with the Schottkys provide the path for the decaying current during phase reversal. (See Figure 7).
PHASE INPUT Low H!g_h
01,04 Off On
02,03 On Off
6-73
vee
..----------161--------------~
UC1717 UC3717
Timing
e
1k
RT
CT
56k
620pF
UC3717 Emitter a
Figure&
lo
h
CURRENT LEVEL
0
0
100%
1
0
60%
0
1
19%
1
1
Current Inhibit
Current Control: The voltage divider, comparators and
monostable provide a means for current sensing and
control. The two bit input (lo, 11) logic selects the desired
comparator. The monostable controls the off time and therefore the magnitude of the current decrease. The
time duration is determined by RT and CT connected to
the timing terminal (pin 2). The reference terminal (pin 11) provides a means of continuously varying the current for situations requiring half-stepping and microstepping. The relationship between the logic input signals at pin 7 and 9 in reference to the current level is
shown in Table 1. The values of the different current lev-
els are determined by the reference. voltage together
with the value of the external sense resistor Rs (pin 16).
ing causing the current to decay. The time is determined by the external timing components RT and CT as:
TOFF = 0.69 RTCT If a new trigger signal should occur during TOFF, it is ignored.
,.----Q3 OFF
Single-Pulse Generator: The pulse generator is a monostable triggered on the positive going edge of the comparator. Its output is high during the pulse time and this pulse switches off the power feed to the motor wind-
Note: Dashed lines indicate current decay ths. Figure 7: Simplified Schematic of Output Stage
6-74
FUNCTIONAL DESCRIPTION (cont.)
Overload Protection: The circuit is equipped with a thermal shutdown function, which will limit the junction temperature by reducing the output current. It should be noted however, that a short circuit of the output is not permitted.
Operation: When the voltage is applied across the motor winding the current rises linearly and appears across the external sense resistor as an analog voltage. This voltage is fed through a low pass filter Re, Cc to the voltage comparator (pin 1O}. At the moment the voltage rises beyond the comparator threshold voltage the monostable is triggered and its output turns off the sink transistors. The current then circulates through the source transistor and the appropriate Schottky diode. After the one shot has timed out, the sink transistsor is turned on again and the procedure repeated until a current reverse command is given. By reversing the logic level of the phase input (pin 8), both active transistors are being turned off and the opposite pair turned on. When this happens the current must first decay to zero before it can reverse. The current path then provided is through the two diodes and the power-supply. Refer to Figure 7. It should be noted at this time that the slope of the current decay is steeper, and this is due to the higher voltage build up across the winding. For better speed performance of the stepping motor at half step mode, the phase logic level should be changed at the same time the current inhibit is applied. A typical current wave form is shown in Figure 8.
I-
1
T
1 \ ~ ~ !\,...
VERT-200mA/OIV HORIZ·1me/OIV
j_
L
""'
Figures
APPLICATIONS A typical chopper drive for a two phase bipolar permanent magnet or hybrid stepping motor is shown in Figure 9. The input can be controlled by a microprocessor, TTL, LS or CMOS logic.
UC1717 UC3717
Phase A l1A IOA
+5 +5 +40
11
6
314
8 Ph VR Vee Vm 1
Bo AOUT
7 11
UC3717
9 12 T cs
Ao 15
E
BOUT
Stepping Motor
8
+5 +5 +40
11
6
314
Phase B 118 loB
8 Ph VR
7 11 9 12
Vee Vm 1 Bo AOUT
UC3717
Ao 15
E
BOUT
Figure9
The timing diagram in Figure 1Oshows the required signal input for a two phase, full step, stepping sequence. Figure 11 shows a one phase, full step, stepping sequence, commonly referred to as wave drive. Figure 12 shows the required input signal for a one phase-two phase stepping sequence called half-stepping.
The circuit of Figure 13 provides the signal shown in Fig-
ure 1o, and in conjunction with the circuit shown in Fig-
ure 9, will implement a pulse-to-step two phase, full step, bidirectional motor drive.
The schematic of Figure 14 shows a pulse to half step circuit generating the signal shown in Figure 12. Care has been taken to change the phase signal the same time the current inhibit is applied. This will allow the current to decay faster and therefore enhance the motor performance at higher step rates.
Using the UC3717 to drive the l298 provides a uniquely packaged state-of-the-art high power stepper motor control and drive. See Figure 15.
6-75
FUNCTIONAL DESCRIPTION (cont.)
PHASE A
PHASE B ----r---.
----FWD
----REV
Figure 10: Phase Input Signal for Two Phase Full Step Drive (4 Step Sequence)
UC1717 UC3717
PHASE PHASE
lo, 11 lo, 11
----<~FWD
~ '
~-t-!~
("
I
~
~
I
·
REV
Figure 11: Phase and Current-Inhibit Signal for Wave Drive (4 Step Sequence)
I 1 l213l4lslsl1lsl
~ PHASE A I
PHASE B~
I I
lo, 11 A~
~ lo, 11 B I
I
FWD
l1l213l4l5l617181
~ '
~
I
~
I
~
I
'
REV
Figure 12: Phase and Current-Inhibit Signal for Half Stepping (8 Step Sequence)
Direction Rev/Fwd
Phase A 1k
PR
D 1/2 a 7474
CK CLR
PR
D
a
1/2
7474
CK
a
CLR
Clear-+----+-----<1>--------+-----'
Clock-----e-----------~
Figure 13: Full Step Bidirectional Two Phase Drive Logic
Phase B
6-76
UC1717 UC3717
Direction Switch
+5V
1k
1k
9 10 11
So S1
L
1 .,,.
3 A 4 B
;.O..>.
5 c
6 D
QD 12 R
l1A loA
A
B 118 loB
Figure 14: Half-Step, Bidirectional Drive Logic
CONSIDERATION
Half-Stepping: In the halt step sequence the power input to the motor alternates between one or two phases being energized. In a two phase motor the electrical phase shift between the windings is 90 degrees. The torque developed is the vector sum of the two windings energized. Therefore when only one winding is energized the torque of the motor is reduced by approximately 30%. This causes a torque ripple and if it is necessary to compensate tor this, the VR input can be used to boost the current of the single energized winding.
Ramping: Every drive system has inertia and must be considered in the drive scheme. The rotor and load inertia plays a big role at higher speeds. Unlike the DC motor the stepping motor is a synchronous motor and does not change its speed due to load variations. Examining typical stepping motors, torque vs. speed curves indicates a sharp torque drop off tor the start-stop without error curve, even with a constant current drive. The reason tor this is that the torque requirements increase by the square of the speed change, and the power need increases by the cube of the speed change. As it can be seen, tor good motor performance controlled acceleration and deceleration should be considered.
Iron Cora Losses: Some motors, especially the lin-Can
type, exhibit high iron losses mostly due to eddy currents which rise in an exponential manner as the frequency or step rate is increased. The power losses can not be calculated by 12R where I is the chopping current level and A the DC resistance of the coil. Actual measurements indicate the effective resistance may be many times larger. Therefore, tor 100% duty cycle the current must be limited to a value which will not overheat the motor. This may not be necessary tor lower duty cycle operation.
Interference: Electrical noise generated by the chopping action can cause interference problems, particularly in the vicinity of magnetic storage media. With this in mind, printed circuit layouts, wire runs and decoupling must be considered. 0,01 to 0.1 µF ceramic capacitors tor high frequency bypass located near the drive package across V+ and ground might be very helpful. The connection and ground leads of the current sensing components should.be kept as short as possible.
Ordering Information
UNITRODE TYPE NUMBER UC3717N-16 Pin Dual-in-line (OIL) "Bat Wing" Package UC1717JP - 16 Pin Dual-in-line Power Ceramic Package
6-77
UC1717 UC3717
ENA A
Phase A
6,11
8 UC3717
3,14 1
4,5 12,13, 16
15 10
ENA B
Phase B
J.001 -
+5V
+VM
6,11
3,14
8 UC3717
4,5 rn.13,
15 10
RT
-
I.001
9
4
+VM
R1
5
7
VM +5V
8
L298 11
+VM
+VM
R1
10
13
1k -
14
NOTES:
1) R1 + R2 - VM
R2
5
-
2) RslM · 0.42V
3) R3 · 10k
Figure 15: UC3717 with L298 Power Amplifier
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. · MERRIMACK; NH 03054 TEL (603) 424·2410 · FAX (603)424·3460
6-78
n nINTEliRATEIJ
~CIRCUITS
-UNITRODE
UC3173A
Full Bridge Power Amplifier
FEATURES · Precision Current Control
· +I- 550mA Load Current
· 1.2V Typical Total Vsat at450mA
· Controlled Velocity Head Parking
Precision Dual Supply Monitor with Indicator
Range Control tor 4:1 Gain Change · Compensation Adjust Pin for Bandwidth Control
· Inhibit Input and UVLO
· 5V or 12V Operation
· 12mA Quiescent Supply Current
· PLCC, SOIC, and Low Profile Quad Flat Pack Packages
DESCRIPTION This full-bridge power amplifier, rated for continuous output current of 0.55 Amperes, is intended for use in demanding servo applications such as head positioning for high-density disk drives. This device includes a precision current sense amplifier that senses load current with a single resistor in series with the load. The UC3173A is optimized to consume a minimum of supply current, and is designed to operate in both 5V and 12V systems. The power output stages have a low saturation voltage and are protected with current limiting and thermal shutdown. When inhibited the device will draw less than 1.5mA of total supply current.
Auxiliary functions on this device include a dual-input under-voltage comparator, which can monitor two independent supply voltages and activate the built-in head park function when either is below minimum. The park circuitry allows a programmable retract voltage to be applied to the load for limiting maximum head velocity. A separate low-side parking drive pin permits a series impedance to be inserted to control maximum retract current. The parking drive function can be configured to operate with supply voltages as low as 1.2V.
The closed loop transconductance of the configured power amplifier can be switched between a high and low range with a single logic input. The 4:1 change in gain can be used to extend the dynamic range of the servo loop. Bandwidth variations that would otherwise result with the gain change can be controlled with a compensation adjust pin.
5193
Pin numbers shown are for "DW" PKG., ( ) numbers are for "OP" PKG.
6-79
UC3173A
ABSOLUTE MAXIMUM RATINGS
Input Supply Voltage, (+Vin, +Ve, +Vl) .....................................20V UV Comparator, Logic Inputs, and Ref Input
maximum forced voltage ...................................-0.3V to 10V maximum forced current... ......................................+/- 1OmA B Amplifier Inverting Input ..............................-0.3V to +Vin + 1.0V A Amplifier Inverting lnputs,(Aux. and normal).-0.3Vto +Ve+ 1.0V Open Collector Output Voltages ..............................................20V A and B Output Currents (continuous) source .......................·.....................·..........Internally Limited sink ................................................................................0.6A Parking Drive Output Current continuous .............................................·...................1SOmA pulsed ...............................................................................1A Output Diode Current (pulsed) ................................................O.SA Power OK Output Current(continuous) .................................30mA Operating Junction Temperature ........................- 55°C to +150°C Storage Temperature ..........................................- 65°C to+150°C Note 1: Unless otherwise indicated, voltages are reference to
ground and currents are positive into, negative out of, the specified terminals, "Pulsed" is defined as a less than 10% duty cycle pulse with a maximum duration of SOOuS.
THERMAL DATA
OP package: (see packaging section of UICC data book for more
details on thermal performance) Thermal Resistance Junction to Leads, ejl ............... 15°C/W Thermal Resistance Junction to Ambient, 0ja ....30°-40°C/W
OW package:
Thermal Resistance Junction to Leads, 0jl .............. 35°C/W Thermal Resistance Junction to Ambient, 0ja ....60°-70°C/W FQ package: Thermal Resistance Junction to Leads, ejl ...............60°C/W Thermal Resistance Junction to Ambient, eja .110-120°C/W
Note: The above numbers for 0jl are maximums for the limiting thermal resistance of the package in a standard mounting configuration. The 0ja numbers are meant to be guide lines for the thermal performance of the device/pc-board system. All of the above numbers assume no ambient airflow.
CONNECTION DIAGRAMS
SOIC - 24 (TOP VIEW) OW PACKAGE
~ ·· ·2·2
4··
21 20 10
7
18
· 8
17 16
10
15
"12
14 13
PLCC-28 (TOP VIEW) QPPACKAGE
~ 5
6
24
7
23
· 8
22 21
10
20
11
19
12 13 14 15 16 17 18
TQFP-48 (TOP VIEW) FQPACKAGE
1gDDDDDDDDDD~
13~
0 48
I
241
;;:;; 37
2~uuuuuuuuuu~.
PACKAGE PIN FUNCTIONS
FUNCTION ow QP FQ
INHIBIT
1
1
9
UV2
2
2
10
UV1
3
3
11
PARK
4
4
12
RANGE
5
5
13
C/S+
6
6
14
COMP ADJ
7
7
15
PARK VOLTS 8
8
16
A-IN
9
9
21
+Ve
10
10 22
A OUTPUT 11,12 11 26, 27
POWERGND 13 12-18 30, 31
BOUTPUT 14,15 19 34, 35
+Vin
16
20 39
B-IN
17
21
40
REF INPUT
18
22 45
C/S-
19
23 46
PWROK
20
24 47
PARK DRIVE 21
25 48
+VI
22
26
2
C/SOUTPUT 23
27
3
GROUND
24
28
4
Electrical Characteristics:
Unless otherwise stated specifications hold for Ta= oto 70'C, +Vin= 5V, +Ve= +Vin= +VI, Ref Input= +Vin/2, Range Input, Park Input, & Inhibit Input= OV.
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNITS
INPUT SUPPLY
+Vin Supply Current
10
13
mA
+Ve Supply Current
lout= OA
1.2
2.0
mA
+VI Supply Current
0.65
1.0
mA
Total Supply Current +VI UVLO Threshold
Supplies = 5V, lout = OA Supplies = 12V, lout = OA low to high
12
16
mA
13
18
mA
2.6
2.8
v
UVLO Threshold Hysteresis
300
mV
UNDER VOLTAGE (UV) COMPARATOR
Input Bias Current UV Thresholds
Max at either UV input low to h_i9-h, other input= 5V
-1.0
-0.25
uA
1.28
1.3
1.32
v
UV Threshold Hysteresis PWROKVsat
lout = 5mA, UV input low
19
24
29
mV
0.15
0.45
v
PWR OK Leakage
Vout = 20V
5
uA
6-80
UC3173A
Electrical Characteristics (Continued): Unless otherwise staled specifications hold for Ta· Oto 70°C, +Vin· 5V, +Ve= +Vin= +VI, Rel Input- +Vin/2, Range Input, Park Input, & Inhibit Input= OV.
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNITS
POWER AMPLIFIERS A AND B
Input Ollset Voltage
A Amplifier, Vcm = 2.5V B Amplifier, Vcm = 2.5V
4
mV
12
mV
Input Bias Current Input Blas Current at Rel. Input
Vcm = 2.5V, Inverting inputs only
(Rel. Input - C/S+Y48Kohms, 1J - 25°C
-500
-150
nA
15
21
27
uA/V
CMRR
Vcm = 1to10V, Supplies= 12V
70
90
dB
PSRR
+Vin= 4 to 15V, Vcm = 1.5V
70
90
dB
Large Signal Voltage Gain
Supplies= 12V, Vout = 1V, lout= 300mA to Vout = 11V, lout= -300mA
3.0
15.0
V/mV
Gain Bandwidth Product
Note 1, A Amplifier Note 1, B Amplifier
2.0
MHz
1.0
MHz
Slew Rate
Note 1
1.0
V/uS
High-Side Current Limit Output Saturation Voltage
High-Side, lout = -1 OOmA, Note 2 High-Side, lout = -300mA, Note 2 High-Side, lout= -550mA, Note 2 Low-Side, lout= 100mA Low-Side, lout= 300mA Low-Side, lout= 550mA Total Vsal, lout= 100mA Total Vsat, lout= 300mA Total Vsat, lout= 550mA
0.45
0.6
A
0.7
v
0.8
v
0.95
v
0.2
v
0.25
v
0.35
v
0.9
1..2
v
1.05
1.4
v
1.3
1.7
v
+Ve to +Vin Headroom
High-Side Diode, VI Low-Side Dlode, VI
Volts below +Vin, delta High-Side Vsal = 100mV, lout= -450mA, Note 2
0.33
0.5
v
ld=550mA
1.0
v
Id = 550mA, Inhibit activated, B ampliler only
1.0
v
CURRENT SENSE AMPLIFIER
Input Ollset Voltage
Vcm = 2.5V, Low range mode High range mode
2.0
mV
4.0
mV
Input Offset Change with Common Mode Input
Vcm = -1V to 13V, Supplies= 12V Low Range Mode
High Range Mode
2000 4000
uVN uVN
Voltage Gain Saturation Voltage
Vdill= +1.0to-1.0V, Vcm = 2.5V High range mode Low range mode Low-Side, lout= 1mA, H.!g!l-Side, lout = -1 mA, Referenced to +Vin
0.485
0.50
0.515
VN
1.95
2.0
2.05
VN
0.1
0.3
v
0.1
0.3
v
PARKING FUNCTION Park Input Threshold Voltage
0.6
1.1
1.7
v
Park Input Threshold Current Park Drive Saturation Voltage Park Drive Leakage Regulating Voltage at Park Volts Input
Internal pull-up, Vin = 0.6V lout=50mA Vout=20V
50
75
uA
0.15
0.35
v
50
uA
1.275
1.30
1.325
v
Note 1: This specification not tested in production Note 2: The high-side saturation performance of the UC3173A is referenced to the +Vin supply pin. The +Ve suppy pin can operate slighUy below
the +Vin supply input, about 400 mV, without affecting this performance.
6-81
UC3173A
Electrical Characteristics (Continued): Unless ollterwise slated specifications hold for Ta= Oto 70-C, +Vin= 5V, +Ve· +Vin· +VI, Ref Input· +Vln/2, Range Input, Park lnpu~ & lnhlbtt Input· OV.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
PARKING FUNCTION (CONTINUED)
Amplifier A Auxiliary Input Blas Current
-750
-300
nA
Amplifier A Parking High-Side Saturation Voltage
lout= -50mA, +Vin= OV, +Ve= +VI= 5V, Park Input Open, +Ve to Vout
0.8
0.95
v
Minimum Parking Supply
At +Ve and +VI; +Vin= OV, A Amplifier out - Vsat Parking Drive>D.5V
lpark=50mA
1.4
1.7
v
Minimum Supply for Parking Drive and Power OK Operation
At +VI, +Ve= +Vin= OV, Vsats < 0.5V, lout Parking Drive = 50mA, RI = 30ohms to 2V
lout Power OK= 5mA, RI = 300ohms to 2V
1.1
1.4
v
1.2
1.6
v
+Vi Parking Supply Current
ParklnputQpen,+Vl=5V, +Ve= 1.SV, +Vn=OV Power OK lout= 5mA, Parking Driw lout= 50mA
1.6
3;0
mA
AUXILIARY FUNCTIONS Inhibit Input Threshold Inhibit Input Current Range Input Threshold Range Input Current
Comp Adjust Pin Saturation Voltage
Comp Adjust Leakage Current
Total Supply Current when Inhibited Thermal Shutdown Temperature
= lnhlbillnpul 1.7V
Range Input = 1.7V Range Input = OV, Pin Current = +/-500uA Referenced to Aout Range Input = 1.7V, Supplies = 12V Aout-V Comp Adj = +/-6V +Vin, +Ve, and +VI currents Note 1
0.6
1.1
1.7
v
-1.0
-0.5
uA
0.6
1.1
1.7
v
50
100
uA
0.02
0.1
v
5
uA
1.0
1.5
mA
165
·c
Nole 1: This specifrcation not tested in production
PIN FUNCTIONAL DESCRIPTION
+Vin
Provides bias supply to both the power amplifiers and the
current sense amplifiers. The high-side drive to the power stages on both
the A and B amplifiers Is referenced to this pin. The high-side saturation
voltages are specified and measured with respect to this supply pin. The
parking function of the device is fully operational independent of the wit-
age at this pin.
+Ve
+Ve supply pin is the high current supply to the collectors of
the high-side NPN output devices on the A and B amplif19rs. This supply
should be powered whenever the A, or B amplifiers are to be activated.
This pin can operate approximately 400mV below the +Vin supply without
affecting the wltage available to the load. This supply pin provides drive
to the power amplifiers during a parking operation.
+VI
Logic portions of the UC3173A are powered by this supply
pin, including the reference, UVLO, the UV comparators, and the PARK-
ING DRIVE and POWER OK outputs. This pin is a low current supply that
would normally be lied to the +Ve pin, or to a parking hold-up capacitor
for extended parking operation with very low recovered back-emf.
GND
Reference point for the intemiil reference, UV comparator,
and other low-level circuitry.
PWR GND Current return for all high level circuitry, this pin should be connected ID the same potential as GND.
A Out
Output for the A power amplifier, providing one end of the
differential drive to the load during normal operation, and during park.
During a UVLO condition al the +Vin supply pin, this output Is forced to a
high, source only state.
B Out
Output for the B power amplif19r, providing one end of the
differential drive to the load during normal operation. During park and
while Inhibited thls pin is tri-stated.
A· In
Inverting input to the A amplifier. Used as the summing
node ID close the loop on the overall power amplifier.
B· In
Inverting input to the B amplifier. Used to program the gain
of the B amplifier ID guarantee maximum wltage swing to the load.
Ref Input Reference for Input control signals to the power amplifier, as well as, the non-inverting inputs to the A and B amplifiers, and the output level shift for the C/S amplifier.
C/S+
The non-inverting Input to the current sense amplifier is typ-
ically tied to the load side of the series current sense resistor. This pin
can be pulled below ground during an abrupt load current change with an
inductive load. Proper operation of the current sense amplifier will result If
this pin does not go below ground by an amount greater than:
Ref Input/ 2 - 0.3V, in low range mode, and 2 · Ref Input - 0.9V, in high range mode.
6-82
PIN FUNCTIONAL DESCRIPTION (CONTINUED)
UC3173A
C/S-
The inverting input to the current sense amplifier is
typically tied to the connection between the B amplifier output
and the current sense resistor that is in series with the load.
C/S Output The output of the current sense amplifier has a 1.5mA current source pull-up and an active NPN pull-down. The output will pull to within 0.3V of either rail with a load current of less than 1mA.
Range
When this pin is open or at a logic low potential,
the current sense amplifier will be in its low range mode. In this
mode the vo1ta11e gain of the amplifier will be 2. If this pin is
brought to a logic hlQh. the gain of the current sense amplifier
will change into its high range value of 0.5. This factor of four
change in gain will vary the overall transconductance of the
power amplifier by the same ratio, with the transconductance
being the highest in the high mode. This feature allows improved
dynamic range of load current control for a given control input
range and resolution.
Comp Adj The compensation adjust pin allows the user to provide an auxiliary compensation network for the A amplifier that is only active when the current sense amplifier is in the low range. With this option, the user can control the change in bandwidth that would otherwise result from the gain change in the feedback loop.
UV 1 & 2 Inputs to the UV comparator, these inputs are high impedance sensing points used to monitor external supply conditions. Either of the inputs going low will force the device into a
park condition, and force the Power OK output to an active low state. If either of these inputs is not used It should be connected
lo a voltage greater than 1.3V.
Power OK Indicates with an active low condition that either of
the UV inputs are low, or that the supply voltage at the +VI input
to the UC3173A has dropped below the UVLO threshold. This output will remain active low until the +VI supply has dropped to
below approximately 1.2V.
Park Volts The auxiliary inverting input to the A amplifier, activated during park conditions on the UC3173A. An internal auxil-
iary non-inverting input is connected to the 1.3V reference. When the auxiliary inputs are activated, the A amplifier will force
a programmed voltage at its output for a maximum backemf/velocity retract of the head. The park condition on the
UC3173A is always activated by any one of the following four conditions, 1: a low condition on either of the UV inputs, 2: a high input level at the Park input, 3: a UVLO condition at the +VI supply pin, and 4: activation of the TSO, (thermal shutdown) protection circuit. During a UVLO condition at the +VI pin the auxiliary inputs to the A amplifier are over-ridden, and the A amplifier
output is forced to its high state.
Park
Logic input that forces the park condition on the
UC3173A. This input has an internal pull-up that will force the
park condition if the pin is left open.
Park Drive A 1OOmA drive output that is active low durinQ a park operation. This pin is normally used to supply the low-side drive to the load during parking, in place of the B amplifier. A series resistor can be added between this pin and the load to
limlt current during park.
Inhibit
A high impedance logic input that disables the A
and B power amplifiers, as well as the Current Sense amplifier.
The UV comparators and logic functions of the UC3173A remain
active. This input has an internal pull-up that will inhibit the
device if the input is left open. The Inhibit function is over-ridden
by any condition that forces the park function to be activated.
CHARACTERISTIC CURVES
A AND B AMPLIFIER HIGH AND LOW VSATS
A AND B AMPLIFIER TOTAL VSAT
1.4
1.3
1.2
>""0"'
O' i
>"'
:CyD ~ 0.4
.£:;
.!2> I
1.1
1l > 0
Oi
>"' 0.9 a"iii
1-O.B
0.7 0.2
0.6
o'--~~--<'--~~--<'--~~--<~~~--'~~~--'
0
100
200
300
400
500
Output Current - mA 6-83
0.5 0
100
200
300
400
500
Output Current - mA
CHARACTERISTIC CURVES (CONTINUED)
UC3173A
+Vin TO +Ve HEADROOM lour=
45omA
o.ei------+------+-----1-------<
POWER OK SATURATION VOLTAGE
.,
"~" 0.6
~ ' +
>c' 0.4
+
0.2
.:! ~ 0.3
>t'i
lo::
0
a; 0.2
3:
a0..
0.1
O'-----'----........J-----'----_J
o
so
100
1so
200
A or B Amplifier High-Side Vsat Increase - mVolts
Power OK Output Current - mA
A AMPLIFIER HIGH-SIDE Vsat IN PARK MODE
1.2 . . . - - - - - - . - - - - - - - . - - - - - - - - . +Vin=OV
+Ve= +VI= 2V
1.11------1-------1--------l
.:!
0 ~ 1 t--------41--------1-----~
§" ~.2 0.9 1------ll---:::=o-""""'=--1--:,.,.,,.,,.,.:::;_--1
~~ o.e 1--.,,,:;;..--.,,......::::i1-----,~-I'------~
en
CD
~ 0.71------_.,.."'-------1-------1 1:.
.2' J: a. 0.61--,.'----1------1-------1
~
<C 0.51--------1-------1-------1
PARKING DRIVE SATURATION VOLTAGE
0.7 . . . - - - - - - . . - - - - - - . . . - - - - - - - .
0.6 t - - - - - - + - - - - - - + - - - - - - - ;
0·4 o.__ _ _ _ __.50.___ _ _ ___,1_ 00 _ _ _ _ ___,150
Output Current - mA 6-84
Output Current - mA
UC3173 CHARACTERISTIC CURVES (CONTINUED)
UC3173A
PARK DRIVE CURRENT vs. +V1 SUPPLY
POWER OK CURRENT vs. +VI SUPPLY
60
i--
50
Ir-I f
17
40
<
E
125°C
c:
.:I!;!
0 -~
30 20
Ci
~
"'0... 10
0
25°C
v I IL
A,= 3000 To2V
+Ve= OV +VN=OV
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
+VI Supply Voltage - Volts
11-1-1-::=t==t==t=:::::J=:r'F"'1F.--i 6·0
7 5.0 t----+--t---+-1--tt----i--~-+--+---<f----t
i
~25°C
4.o 1---1---+---H--*+-V~A.<.i--+----+--+--+---l
cJ'~E
RL=30QS
3.0
l
-
-
-
-
+
-
-
+
-
-
-
1
1
-
-
-
-
1
+
-
-
-
-
l
-
-
t
-
+
v
c
T
±
uonv
+---+--!
'.:!£
+\fiN=OV
0
Q;
~
0...
2.0 1.0
t---+--t-71-t-+-f-t---t--+---t-t--+---<
0.0 ..___._ _..,,_...J.<:._J_____J_ _.__ 0.0 0.2 0.4 0.6 0.8 1.0 1.2
__,__ _,_____JL____J
1.4 1.6 1.8 2.0
+VI Supply Voltage - Volts
+VI CURRENT VERSUS PARK DR CURRENT
+VI= 5V +Ve= 1.6V
+VI CURRENT VERSUS PWR OK CURRENT
+VI= 5V +Ve= 1.6V
<
E
c 4t-------t------+-~<-..,L-----l
~
0 "
~3i-------t------«-,---------I
a.
e"n
5 + 2t-------t-7"7"'---+--------l
1.5
<
E
c:
~
0 "
~ aa..
e"n
5
+
0.5
0 o'-_ _ _ _ _s'-0_ _ _ _ _ _1,,_,o_o------'1so
Parking Drive Output Current - mA
6-85
O'------'-------''--------'------'
0
5
10
15
20
Power OK Output Current - mA
APPLICATION INFORMATION
TYPICAL APPLICATION
R
Go =J.I:_ Rib
I
Vs · Ria · AVcs ·Rs
Re
Cc
AVcs = Current Sense
Amplifier Gain = 2.0 low Range,
0.5 High Range
UC3173A
SPINDLE BACK EMF
Rib
R
CURRENT SENSE AMPLIFIER
UC3173A
Maximizing the Voltage to the Load In order to assure that maximum voltage drive to the load is achievable there are some precautions that should be taken. In a
standard configuration, the B amplifier is slaved to the A amplifier. The bias point of the Ref Input and the gain of the B ampli-
fier, as well as the saturation voltages of the power output stages, will affect the voltage available to the load.
There are two simple procedures to follow, either will insure that the capabilities of the device are fully utilized. The first is to set
the Ref Input voltage at the center of the available voltage swing at the output of the power amplifiers. This optimum reference is defined by equation (1 ).
(l ) Vref (opf 1mum )
=
+_V_in_-_V_h_s~sa=t_+_V_ls~s~a~t
2
where: Vhssat =high-side Vsat at maximum load. Vlssat =low-side Vsat at maximum load.
Data for (1) can be taken off the characteristic curves showing Vsat performance versus output current. There will be a degree of temperature dependence to this solution since the low side Vsat of the power stages has a positive temperature dependence, and the high-side a negative. In some cases it might be worth interpolating between the 25°C and the 125°C curves to M a typical junction temperature.
A second approach is to raise the gain of the B amplifier to insure maximum swing. For a given Ref Input voltage the gain ,of the B amplifier, set by the ratio of the feedback resistors, can be made greater than unity as given by,
+Vin - Vhssat + Vref (2) Avs = Yref · Vlssat
or,
Vref - Vlssat
+Vin - Vhssat - Vref
whichever is greater than unity.
For a typical case, where Vref has been set at +Vin/2, the required gain for a 5 volt system will be about 1.5, and for a 12 volt system, 1.2.
It is worth noting that when using this method the B amplifier will saturate before the A amplifier on one polarity of the voltage swing. Durin~ the time when the B amplifier is saturated and the A amplifier is not, the small signal bandwidth of the loop will be reduced by a factor of (Avs+1).
6-86
APPLICATION INFORMATION {CONTINUED)
UC3173A
Setting and Maximizing the Loop Bandwidth
The normal configuration for compensation of the power amplifier
is shown in the Typical Application drawing. A simple RC net-
work. RcCc time constant is typically chosen to correspond to
the electrical time constant of the load, given by Rill. Where RI is
the total load and sense resistanace between the bridge outputs
and L is the load inductance.
'
The 3dB frequency(f3dBl of the closed loop amplifier is given by the following expression:
(3)f =(1+AyB)·AyCS·Rs·Rc
3dB
2JtL· Rib
assuming f3dB » (21tRc · Ccr1
where: AvB is the voltage gain of the B amplifier. AvCS is the CS amplifier voltage gain.
In the closed loop transconductance amplifier, the A amplifier
operates at the highest noise gain. Noise gain is a measure of
the feedback ratio at which the amplifier is operating. For the
configuration of the A amplifier in the typical application drawing,
the noise gain is given by the impedance ratio of the Re-Cc
series network, to the parallel combination of Ria and Rib. For
th~ A a~plifier to operate at its expected closed loop gain, the
noise gain at any frequency must not exceed its Gain Bandwidth
Product(GBW) divided by that frequency. Applying this to the
expression above will yield a result for the maximum 3dB band-
)1; width that can be achieved for a given configuration.
14) ladBmax =
( fgbwA · (1 +AyB) · AyCS · Rs ·Ria 2"L ·(Ria+ Rib)
2
where:
lgbwA is the GBW of the A amplifier.
In the UC3173A, to accommodate wider power amplifier bandwidths, the GBW Product of the A amplifier has been extended to 2MHz. A loop compensated in this manner will have a second order closed response with the poles split around the 3dB frequency given in (3). The loop phase margin will be approximately 45°. The value of Re required to set the above conditions is given by
(
lgbwA · 211L · Ria
) 1/2
(S) Rcmax = Rib " (AyB + 1) · AyCS · Rs· (Ria+ Rib)
Range Change Bandwidth Control When the range change feature of the UC3173A is used the closed loop bandwidth of the power amplifier will change according to (3). In other words, the bandwidth would be four times larQer during. the low range mode when AVCS is equal to 2, than during the high range mode when AVCS is equal to 0.5, unless the value of Re is adjusted to compensate. The Comp Adjust pin on the UC3173A can be used to do this. The Comp Adjust pin acts as a simple switch that allows a parallel compensation network to be applied around the A amplifier during low range operation. A simple network as shown here will keep the loop response constant independent of the range condition.
6-87
··INPlfT
REF
INPUT
RAN13E INPUT
UC3173A
The Comp Adjust pin switches in a parallel compensation net· work tostabilize the small signal bandwidth with range changes.
Head Parking In the application figure, Controlled Velocity Head Parking, the UC3173A is shown configured to force a programmed voltage at the A amplifier output upon the activation of a park condition. A pair of feedback resistors R1 and R2 set this voltage as defined by
(6) Vpark = 1.3 · (1+ ~!)
The B amplifier output is tri-stated during park, this side of the load is driven low by the Park Drive pin. A series resistor, Rp in the figure, can be inserted in series with the load to limit the peak current if required.
During park, supply to the load, and the UC3173A, is typically recovered from the back EMF of the spindle motor. When the supply voltage at the +VI supply pin drops below the UVLO voltage,(2.3V high-to-low), the output of the A amplifier is forced high, over-riding the programmed park voltage. The UC3173A will maintain drive to the load down to low supply levels. For example, with 1.5 Volts of recovered back EMF, the UC3173A can still deliver 50mA of drive to a 1Oohm load.
Parking With Very Low Back EMF The UC3173 can also be configured to get parking drive to the load with very low recovered back EMF. The figure titled Head Parking with Low Back EMF illustrates how the Power OK pin can be used to drive an external PNP device to achieve very low parking drive Vsat losses. With this configuration, the UC3173A will be able to force approximately one volt across the load with a recovered back EMF voltage of 1.3V.
During system commanded parking with the supplies present, the Park Volts pin is still used to set the maximum voltage to the load. The logic function of the Power OK pin is still available since the external PN P will provide isolation to this output when it is high.
Base drive to the Park Drive and Power OK pins are provided by the +VI supply pin. By using a hold up capacitor, CHOLD, the drive can be maintained to the load as the back EMF drops to below 1 volt. A variation on this approach is to add a connection between the +VI pin and the recovered back EMF, this will eliminate the need for the holdup capacitor and provide operation down to about 1.2V of back EMF recovery. Care with this approach should be taken in case the 5V volt supply hangs at just below the programmed UV threshold. In this situation large currents could flow from this supply through the external PNP and into the A output which, until the supply drops below a certain level, is' forcing a programmed voltage.
APPLICATION INFORMATION (CONTINUED)
CONTROLLED VELOCITY HEAD PARKING
UC3173A
RP R1
R2
12V
5V
R3
R5
r-6-.___u~ -- __ _J
R4
R6
HEAD PARKING WITH LOW BACK EMF
RB
RP
_ _ _ UC3173A _ _ __J
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD.· MERRIMACK, NH 03054 TEL. (603) 424-2410 · FAX (603) 424-3460
6-88
n nINTEIJAATED
~CIRCUITS
-UNITRODE
Full Bridge Power Amplifier
UC3174B UC3175B
FEATURES
DESCRIPTION
Precision Current Control
These full-bridge power amplifiers are rated for continuous output current of 0.8
±800mA Load Current
Amperes and are intended for use in demanding servo applications such as head positioning for high-density disk drives. Both of these devices include a
1.25V Total VSAT at 800mA
precision current sense amplifier that provides accurate control of load current.
The UC3174B is designed for ground referenced current sensing using the deControlled Velocity Head Parking vice's Current Sense pins, while the UC3175B is optimized for sensing current
Precision Dual Supply Monitor with a single resistor in series with the load. These power amplifiers have a
with Indicator
very low output saturation voltage and will operate down to 4V supply levels.
Limit Input to Force Output Extremes
Power output stage protection includes current limiting and thermal shutdown. Auxiliary functions on this device include a dual-input under-voltage compara-
Inhibit Input and UVLO
tor, which can monitor two independent supply voltages and force a built-in head park function when either is below minimum. When activated by either the
4V to 1SV operation
UV comparator, or a command at the separate PARK input, the park circuitry
will override the amplifier inputs to convert the power outputs to a programma-
ble constant voltage source which will hold regulation as the supply voltage
falls to below 3.0 Volts. Added features include a POWER OK flag output, a
LIMIT input to force the drive output to its maximum level in either polarity, and
a over-riding INHIBIT input to disable all amplifiers and reduce quiescent sup-
ply current.
BLOCK DIAGRAM
This device is packaged in a power PLCC surface mount configuration which maintains a standard 28-pin outline, but with 7 pins along one edge allocated to ground for optimum thermal transfer. And is also available in a 24-pin surface mount SOIC package.
Park Volts Limit
A· In A+ In/REF
Sen A Cur Sen
C/S
' UC3175B Values In O's.
Note: Pin numbers refer to PLCC package.
1/93
6-89
UDG-92054
ABSOLUTE MAXIMUM RATINGS
Input Supply Voltage, (+VIN,+Vc) ................................ 20V UV Comparator, and Digital Inputs
Maximum forced voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 1OV Maximum forced current ................................. ±10mA C/S Inputs Maximum forced voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 20V A and B Amplifier Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +VIN Open Collector Output Voltages ................................ 20V A and B Output Currents (continuous) Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally Limited Sink ................................................... 1.0A Parking Drive Output Current Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150mA Pulsed ....·.............................................. 1A Output Diode Current (pulsed) ................................... 1A Power OK Output Current(continuous) ......................... 30mA Operating Junction Temperature ...................... -55°C to +150°C Storage Temperature ............................... -65°C to +150°C
UC3174B UC3175B
Note 1: Unless otherwise indicated, voltages are referenced to ground and currents are positive into, negative out of, the specified terminals. "Pulsed" is defined as a less than 10% duty cycle pulse with a maximum duration of500µs. Note 2: See Unitrode Integrated Circuits databook for information regarding thermal specifications and limitations ofpackages.
Thermal Data QP Package: Thermal Resistance Junction to Leads,
IJJA..·.·.···.······....... 1s0 c;vv
Thermal Resistance Junction to Ambient,
IJJA ··..····...·.·.·....... 40°C/VV
SOIC-24 (Top View) DW Package
PLCC-28 (Top View) QP Package
4 CIS Out
11 +Ve Supply
4 3 2 1 28 27 26
5
25
6
24
7
23
8
22
9
21
20
11
19
12 13 14 15 16 17 18
PACKAGE PIN FUNCTION
FUNCTION
PIN
+VIN
1
INH
2
UV2
3
UV1
4
Limit
5
Park Volts
6
Qf_s-
7
A±LREF Input
8
A-In
9
A OU!Q_ut
10
A Cur Sen
11
GndJ.Heat Diss_im!!ion Pin~ 12-18
B Cur Sen
19
B OU!Q_ut
20
+Ve Supply
21
B-ln
22
B+ln
23
(jf__s+
24
PwrOK
25
Park
26
Park Drive
27
C/S Out
28
ELECTRICAL CHARACTERISTICS: Unless otherwise stated specifications apply for 0°c s TA s 10°c, +VIN = 12v, +Ve
=+VIN, A+/REF Input= 6\1. TA=TJ
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNITS
INPUT SUPPLY
+VIN Supply Current
All Amplifier Outputs = 6V
35
42 mA
+Ve Supply Current
lour= OA
1
mA
+VIN UVLO Threshold
Low to High
2.8 3.0
v
UVLO Threshold Hysteresis
200
mV
UNDER VOLTAGE (UV) COMPARATOR
Input Bias Current
-1.5 -0.5
µA
UV Thresholds
Low to High, Other Input= 5V
1.48 1.50 1.52 v
UV Threshold Hysteresis
15
25
40
mV
PwrOKVSAT
!OUT= 5mA
0.45 v
Pwr OK Leakage
VOUT =20V
5
µA
6-90
UC3174B UC3175B
ELECTRICAL
Unless otherwise stated specifications apply for 0°C :s TA :s 70°C, +VIN= 12V, +Ve= +VIN,
CHARACTERISTICS (cont.) A+/REF INPUT= 6V. TA=TJ.
PARAMETER POWER AMPLIFIERS A and B
Input Offset Voltage
Input Offset Drift Input Bias Current Input Offset Current Input Bias Current at A+/Ref Input
Differential Sense Error Current
CMRR PSRR Large Signal Voltage Gain
Slew Rate Unity Gain Bandwidth
High-Side Current Limit Output Saturation Voltage
High Side Diode VF Low Side Diode VF CURRENT SENSE AMPLIFIER Input Offset Voltage
Input Offset Change with Ref Input Input Offset Change with Common Mode 11!.e._Ut Input Offset Drift Voltage Gain
Output Saturation Voltage
Maximum A+/Ref Input
PARKING FUNCTION Park Input Threshold Park Input Current Park Drive Saturation Voltage, PDvsAT Parking Drive Leakage
TEST CONDITIONS
VCM = 6V, A Amplifier BAmplifier Note 1, A Amplifier Only VCM = 6V, except A+/REF Input VcM = 6V, B Amplifier Only (A+/Ref-C/S+)/36k, TJ = 25°C, UC3174B Only (A+/Ref-C/S+)/12k, TJ = 25°C, UC3175B On_ly_ Note 2, IL = 5mA IL= 500mA 1V :sVCM :s 10V +VIN= 4V to 15V, VcM = 1.5V VOUT = 1V, Sinking 500mA to VOUT = 11V, Sourcing 500mA 1 to 13V, 13 to 1V, TJ = 25°C Note 1, A Amplifier Note 1, B Amplifier
High-Side, !SOURCE = 250mA High-Side, !SOURCE = 800mA Low-Side, ISINK = 250mA Low-Side, ISINK = 800mA Total, IOUT= 250mA Total, lour = 800mA ID = 800mA, Inhibit Activated ID = 800mA, Inhibit Activated
VcM =6V VcM = OV, UC3174B Only 2V A+/Ref 10V, UC3174B Only OV :s VcM s 12V, UC3175B Only
Note 1
ov, -0.5V :5 VDIFF :5 +0.5V, Vern= UC3174B Only
-1 .OV :5 VDIFF :5 +1.0V, VcM = 6V' UC3175B Only Low-Side, ISINK = 1.5mA High-Side, !SOURCE = 1.5mA Volts Below +VIN, C/S+ & C/S- = BOUTPUT Max@ 10mA Output Current, +VIN= 4.5V, UC3175B only, C/S VIO :s 5mV
Park Input = 1.7V ISINK = 1OOmA VOUT= 20V
MIN
-500 20 60 -500 70 70 3.0 0.8
7.8 1.95
0.7
TYP MAX UNITS
-150
28 84
3 90 90
8
mV
12 mV
25 µV/°C
nA
200 nA
35 µA/V
105 ~ 500 µA
8
mA
dB
dB
15.0
V/mV
1
2.1 V/µs
2
MHz
1
MHz
1.0
A
0.7
v
0.85
v
0.3
v
0.4
v
1.0 1.2
v
1.25 1.6
v
1.0
v
1.0
v
2.0 mV 5.0 mV 500 µVN
1500 µVN
8 µV/°C
7.9
8.0
v
v 2.00 2.05
0.3 0.5
v
0.4 0.7
v
2.6 3.0
v
1.1
1.7
v
60 100 µA
0.3 0.5
v
100 µA
6-91
UC3174B UC3175B
ELECTRICAL
Unless otherwise stated specifications apply for 0°C:.: TA:.: 70°C, +VIN= 12V, +Ve= +VIN,
CHARACTERISTICSJ_contJ_ A+IREF Input= 6V. TA=~J.
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNITS
PARKING FUNCTION (cont.)
Amplifier A Aux Input Bias Current Amplifier A Saturation Voltage, AHVSAT Regulating Voltage at Park Volts Minimum Parking Supply Voltage
!SOURCE= 50mA, +VIN= 3V AHVSAT + PDVSAT s 1.3V @ 50mA
-500 -150
nA
0.65 0.8
v
v 1.47 1.50 1.53
1.7
1.9
v
AUXILIARY FUNCTIONS Limit Input Low Voltage Limit Input High Volta__g_e Limit Inactive Limit Open Circuit Voltage
A Output Forced Low A Output Forced High
0.7 0.8
v
2.2 2.3
v
1.2
1.8 v
v 1.45 1.50 1.55
Limit Input Resistance Inhibit Input Threshold
1.2V s Limit Inputs 1.8V
10
kQ
0.7 1.1
1.7
v
Inhibit Input Current
Inhibit Input= 1.7V
400 700 µA
SU££1Y._Current when Inhibited Thermal Shutdown Temperature
The sum of +VIN and +Ve currents
2
6
mA
165
oc
Note 1: This specification not tested in production.
Note 2: This specification is a measure of the accuracy of the differential current sense scheme using the Current Sense pins of the UC3174B. The error current specified is defined as /csA - /csa - IL, where /csA and Jcsa are respectively the currents out of the A and B current sense pins, with load current, IL, flowing out of the Band into the A amplifier outputs. Similarly, the error current is measured as /csa - /CSA - IL, with IL flowing from A into B.
UC3174B Ground-Referenced Current Sensing RC CC
10k
12V
Supply
+ vs
VREF Input
Rib
I
I
~
I
UC31748
-I =
L--------------------~
UDG-92057
For maximum voltage swing, Pin 23 should see +VIN/2. If VREF at Pin 8 is at this level, then the divider is not necessary and Pin 23 can also be connected to the VREF input.
Go = .!!:_ = Rfb
Vs Rfa · 8 ·Rs
6-92
UC3175B Series Current Sensin
UC3174B UC3175B
10k 12V
Supply
+ vs
VREF Input
I
~
I
UC31758
-==- I ~
L----------------------~
Parking Function
Go = .!!::_ = Rfb Vs Rfa· 2 ·Rs
R1
RP
R2 1.5V
Park CMD 26;r--------~
UDG-92058
Notes: Parking voltage= 1.5V · (Rt + R2) I R2 - (IL· RP)
RP is optional for current limiting. Inhibit and Park Inputs are active high. Pwr OK is low on power failure.
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. · MERRIMACK; NH 03054 TEL (603) 424·2410 · FAX (603) 424-3480
6-93
UDG-92059
n n L:::::::'.J
INTEGRATED CIRCUITS
-UNITRCCJE
Full Bridge Power Amplifier
UC3176 UC3177
FEATURES Dual Power Operational Amplifiers ±2A Output Current Guaranteed Precision Current Sense Amplifier Two Supply Monitoring Inputs Parking Function and Under-Voltage Lockout Safe Operating Area Protection 3V to 35V Operation
DESCRIPTION
The UC3176/7 family of full bridge power amplifiers is rated for a continuous output current of 2A. Intended for use in demanding servo applications such as disk head positioning, the onboard current sense amplifier can be used to obtain precision control of load current, or where voltage mode drive is required, a standard voltage feedback scheme can be used. Output stage protection includes foldback current limiting and thermal shutdown, resulting in a very rugged device.
Auxiliary functions on this device include a dual input under-voltage comparator that can be programmed to respond to low voltage conditions on two independent supplies. In response to an under-voltage condition the power Op-Amps are inhibited and a high current, 1OOmA, open collector drive output is activated. A separate Park/Inhibit command input.
The devices are operational over a 3V to 35V supply range. Internal under-voltage lockout provides predictable power-up and power-down characteristics. The parts are packaged in the 15 pin Multiwatt package with a maximum 0Jc of 3°C/Watt. For lower power applications a surface mount 28 pin PLCC package is available. Consult packaging section of databook for package details.
BLOCK DIAGRAM
A Output
B
..-~~~~~11--~~~~~~~~--1
A- Input A+ Input/ Ref Input
·e· Inhibits Tri-state
AISINK
UC3177 Only
Current Feedback
B· Input B+ Input (UC3176 Only)
BISINK Parking Drive
01/93
ULVO I 1.5V
_ Under-Voltage = Comparator Supply OK +VIN Gnd (UC3177 Only)
6-94
UV2 UV1
ABSOLUTE MAXIMUM RATINGS (Note 1)
Input Supply voltage, (+VIN) ....................... 40V Park/Inhibit, UV1 and UV2 inputs (zener clamped)
Maximum forced voltage ........·....... -0.3\/ to 1OV Maximum forced current .................... ±10mA Other Input Voltages . . . . . . . . . . . . . . . . . . . . -0.3V to +VIN AISINK and BISINK Voltages.................. -0.3V to 6V Open Collector Output Voltages ................... 40V A and B Output Currents (Continuous) Source . . · . . · . . · . . . . . . . . . . . . . . . . . Internally Limited Sink....................................... 2.5A Total Supply Current (Continuous) .................. 4A Parking Drive Output Current (Continuous). . . . . . . . 200mA Supply OK Output Current, UC3177 (Continuous) ... 30mA Operating Junction Temperature ......... -55°C to+150°C Power Dissipation at TC = +75°C QP package......·....·..................... 4W Storage Temperature ·................. -65°C to+15o·c
Note 1: Unless otherwise indicated, voltages are reference to ground and currents are positive into, negative out of, the specified terminals.
THERMAL DATA
OP package:
Thermal Resistance Junction to Leads, 0Jc ....... 15°C/W
Thermal Resistance Junction to Ambient, 0Jc ..... 50°C/W
CONNECTION DIAGRAM
UC3176 UC3177
PLCC-28 (Top View) QP Package
L4 3 2 1 28 27 28
5
25
6
24
7
23
8
22
9
21
10
20
11
19
12 13 14 15 16 17 18
PACKAGE PIN FUNCTION
FUNCTION
PIN
+VIN
1
BoutDUt
2
BISIN~Sens8l
3
BISINK
4
NtC
5-7
B- Input
8
*
9
P&rWinhiblt
10
Parking Drive
11
Gndo:leat Flow PlnSl 12-18
UV1
19
UV2
20
Current Feedback
21
A+ Input
22
A-ll'l!>ut
23
~
24
AISINK
25
AISINK(Sens8l
26
AOutDut
27
Gnd
28
"Pin 9: UC3176, B+ Input UC3177, Supply OK
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, specifications hold for TA= o to 10°c, +VIN = 12V, TA= TJ.
PARAMElER
TEST CONDITIONS
MIN.
lnputS~ly
Supply Current
+VIN= 12V
+VIN=35V
UVOL Threshold
+VIN low to high
Threshold Hysteresis
Power, Amplifier, A and B
Input Offset Voltage
VcM = 6V, VOUT = 6V
Input Bias Current
VCM = 6V, Except A+ Input
-500
Input Bias Current at A+/Reference Input (A+/Ref - BISINK)/36kohms; TJ = 25°C
23
Input Offset Current B Amp (UC3176 On1¥1.J VCM =6V
CMRR
VCM = 1 to 33V, +VIN =35V, VOUT = 6V
70
PSRR
+VIN = 5 to 35V, VcM = 2.5V
70
Large Signal Voltage Gain
VOUT = 3V, W/IOUT = 1A to VOUT = 9V, wAOUT = -1A 1.5
Thermal Feedback
+VIN= 20V, Pd= 2r:J.N at opposite output
Saturation Voltage
lour= -2A, High Side, TJ = 25°
CIOUT = 2A, Low Side, TJ = 25°C
Total VSAT at 2A, TJ = 25°C
Unity Gain Bandwidth
Slew Rate
Differential lour Sense Error Current
IOUT(A) = -lou!{_B)' /IOUT/- /AISINK - BISINK/
in Bridge Configuration
IOUT:s:200mA
IOUT:s:2A
High Side Current Limiting
=VIN - VOUT < 12V
TVP.
18 21 2.8 220
-100 28
100 100 4 25 1.9 1.6 3.5
1 1
3.0 5.0 -2.7
MAX. UNITS
25 mA 30 mA
3.0 v
300 mV
8
mV
nA
35 µAN
200 nA
dB
dB
V/mV
200 µVN/
v v 3.7 v
MHz
V/µs
6.0 mA 10 mA -2.0 A
6-95
UC3176 UC3177
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, specifications hold for TA= Oto 70°C, +V1N = 12V, TA= TJ.
PARAMETER Current Sense Amplifier
Input Offset Voltage
Thermal Gradient Sensitivity
PSRR Gain Slew Rate 3dB Bandwidth Max Output Current Output Saturation Voltage
Under-Voltage Comparator Threshold Voltage
lr:!E_ut Current Supply OK VsAT (UC3177 Only) Supp.!¥_OK Leakage (UC3177 Only) Park/Inhibit Park/Inhibit Thl'd Park/Inhibit Input Current Parking Drive Saturation Voltage Parking Drive Leakage Thermal Shutdown Shutdown Temperature
TEST CONDITIONS
VcM = OV, A+/Ref at 6V Ref= 2V to 20V, +VIN= 35, change with Ref
i~utvol~e
+VIN= 20V, Ref= 10V Pd= 20W@A or B output Ref= 2.5V, +VIN = 5 to 35V /AISINK - BISINK/.: 0.5V
lsouRcE = +VIN - Vour = 0.5V lsouRcE = 1.5mA, H!g!l Side ISINK = 5mA, Low Side
Low to High, other input at 5V Threshold Hysteresis Input = 2V, other input at 5V IOUT=5mA VOUT=35V
At threshold lour= 100mA Vour=35V
MIN. TVP. MAX. UNITS
3
mV
600 µVN
5.0 75 µVNI
70 100
dB
7.8
8
8.1 VN
2
V/µS
1
MHz
2.5 3.5
mA
0.15 0.30 v
1.4 1.7
v
1.44 1.50 1.56 v
50
70
80 mV
-2 -.05
µA
0.45 v
5
µA
1.1
1.3 1.7
v
60 100 µA
0.3 0.7
v
15 µA
165
·c
Output Saturation Voltage vs Current
4.0
;E: 3.5 J_Jt~ll JJA~
' 3.0 12s·c,
~
CD
~hslde ~2.5
~ 2.0
25·C~
H
i§ 1.5 H-1
~ 12 'c VSAT ~~~
~
1.0
~ 0.5
o.o
~ 1:,J
N
Lowelde VSAT 125·c 25·c
0 0.2 0.4 0.8 0.8 1 1.2 1.4 1.6 1.8 2
Output Current - (A)
Maximum Source Current
-. 2.8
l!! 2.4
!; 2.2
()
2
CD 0
1.8
!;
0
1.8
(/j 1.4
s-5 1.2
::J
1
0 0.8
..E
::J
0.8
~ 0.4
0.2
:Ii
00
VS +VIN · VOUT
~ ~ _:::::,i ~ ~
10
20
30
+YIN - VOUT - (V)
Crossover Current Error Characteristic
+8
.<s +2
! -2
-8
-10 -10
-8 ·2 +2 +8 +10 Va - (mV)
6-96
APPLICATION AND OPERATION INFORMATION
Compensation Nead Is Dependent
IL
O--n--L.o.a.d....-..
r- - _Q..C-11- ~'!.-
1
I
Signal
I
Input o-"""''"""-T-1
(VS)
Sign al Reference
Input
Park/Inhibit Control
xS Current Sense Amplifier
Park/Inhibit
UC3176 UC3177
Supply 2
WAVEFORMS FOR ABOVE APPLICATION
VS~C--VP ------~--~--~--- VP
IL~-VP·GO ---~--~-~~-~--~ VP·GO
IA ---"-A~,_____A_____A_~---------- VP· Go IB---~./"-.~....._-~,/"-._,___-._/"_\__ -VP·GO
DESIGN EQUATIONS
= Transconductance (Go) VILs = RRFF12 x ( B1Rs)
with: RSA = Ass and RF3 = RF4
Parking Current (IP) = ~N - ~5 P+ L where: AL =load resistance
Under-Voltage Thresholds, at Supplies
High to Low Threshold, (VLH) =1.425 (RA + RB)/RB
Low to High Threshold, (VHL) = 1.5 (RA + RB)/RB
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. · MERRIMACK, NH 03054 TEL (803) 424-2410 · FAX (803) 424-3460
6-97
n nINTEraRATliC
~ CIRCUIT8
-UNITRODE
UC3178
Full Bridge Power Amplifier
FEATURES Precision Current Control :t450mA Load Current 1.2V Typical Total Vsat at 450mA Programmable Over-Current Control Range Control for 4:1 Gain Change Compensation Adjust Pin for Range Bandwidth Control Inhibit Input and UVLO 3V to 15V Operation 12mA Quiescent Supply Current
BLOCK DIAGRAM
DESCRIPTION
The UC3178 full-bridge power amplifier, rated for continuous output current of 0.45 Amperes, is intended for use in demanding servo applications. This device includes a precision current sense amplifier that senses load current with a single resistor in series with the load. The UC3178 is optimized to consume a minimum of supply current, and is designed to operate in both 5V and 12V systems. The power output stages have a low saturation voltage and are protected with current limiting and thermal shutdown. When inhibited, the device will draw less than 1.5mA of total supply current
Auxiliary functions on this device include a load current sensing and rectification function that can be configured with the device's over-current comparator to provide tight control on the maximum commanded load current. The closed loop transconductance of the configured power amplifier can be switched between a high and low range with a single logic input The 4:1 change in gain can be used to extend the dynamic range of the servo loop. Bandwidth variations that would otherwise result with the gain change can be controlled with a compensation adjust pin.
This device is packaged a power PLCC, "OP" package which maintains a standard 28-pin outline, but with 7 pins along one edge directly tied to the die substrate for improved thermal performance.
5/93
6-98
UDG-92010
UC3178
ABSOLUTE MAXIMUM RATINGS
Input Supply Voltage, (VtN(+), Ve(+)) .................. 20V 0/C Sense, Logic Inputs, and REF Input
Maximum forced voltage. . . . . . . . . . . . . . . . . -0.3V to 1OV Maximum forced current ..................... ±10mA A & B Amplifier Inputs . . . . . . . . . . . . . -0.3V to {VIN(+) + 1.0V) 0/C Indicate Open Collector Output Voltage ............ 20V A and B Output Currents(continuous) Source. . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally Limited Sink ........................................ 0.6A Output Diode Current (pulsed)* . . . . . . . . . . . . . . . . . . . . . 0.5A 0/C Ind Output Current(continuous) . . . . . . . . . . . . . . . . 20mA Operating Junction Temperature . . . . . . . . . . . . . . . . . . + 150°C Storage Temperature. . . . . . . . . . . . . . . . . . . -65°C to +150°C
*Notes: Unless otherwise indicated, voltages are referenced to ground and cu"ents are positive into, negative out of, the specified terminals, "Pulsed" is defined as a less than 10% duty cycle pulse with a maximum duration of 500µs.
THERMAL DATA
OP package: (see packaging section of UICC data book for more details on thermal performance)
Thermal Resistance Junction to Leads, 8jl ........ 15°C/IN Thermal Resistance Junction to Ambient, 8ja . . . 30-40°C/IN
Note: The above numbers for8jl are maximums for the limiting thermal resistance of the package in a standard mounting configuration. The 8ja numbers are meant to be guidelines for the thermal performance of the device/pc-board system. All of the above numbers assume no ambient airflow.
CONNECTION DIAGRAM
PLCC - 28 {Top View) QP Package
L ~ 4 3 2 1 28 21 2s
5
25
6
24
7
23
8
22
9
21
10
20
11
19
12 13 14 15 16 17 18
PACKAGE PIN FUNCTION
FUNCTION
PIN
Inhibit
1
Qic Force
2
O_L_C Sense
3
Ra!Jrul
4
c.lfil±l
5
Com..Q.Mi.
6
0Ic1nd
7
AINJ±i
8
- A1ti!:l_
9
VQhlSY!mOC_
10
AOu!ll..ut
11
PwrGnd
12
PwrGnd
13
PwrGnd
14
PwrGnd
15
PwrGnd
16
Pwr Gnd
17
Pwr Gnd
18
B O\!!Q_ut
19
Vt~
20
BtNH
21
B1NJ±L
22
GZTM REF lllll..ut
23 24
Q§out
25
IDIFOut
26
IDIF REF
27
Ground
28
ELECTRICAL CHARACTERISTICS: Unless otherwise stated specifications hold for TA= 0°C to 70°C, Ve(+) = VtN(+) =
12V, REF Input= VtN(+)/2, 0/C Input & Inhibit Input= OV.
PARAMETER Input Supply
VIN (i-)Su~lyGurrent Ve(+) Supply Current Total Supply Current
VIN(+) UVLO Threshold UVLO Threshold Hysterisis Over-Current (0/C) Comparator Input Bias Current Thresholds Threshold Hysterisis 0/C INDVsat 0/C IND Leakage Power Amplifiers A and B Input Offset Voltage
Input Bias Current CMRR PSRR Large Signal Voltage Gain
TEST CONDITIONS
lour=OA Supplies= 5V,lour = OA Supplies= 12V,lour = OA low to high
v input= 0.8V
low to h.!9!1
lour = 5mA, V input low Vour=20V
A Amplifier, VeM = 6V B Amplifier, VeM = 6V VeM =6V VeM = 0.5 to 13V, Supplies = 15V VIN(+) = 4 to 15V, VeM = 1.5V Supplies= 12V, Vour = 1V, lour= 300mA to Vour = 10.5V, lour= -300mA
MIN TYP MAX UNITS
12
16 mA
1.2 2.0 mA
12
16 mA
13
18 mA
2.6 2.8
v
300
mV
-1.0 -.01
µA
v 0.97 1.0 1.03
85 100 115 mV
v 0.2 0.45
5.0 µA
4.0 mV
12.0 mV
-500 -50
µA
70 90
dB
70 90
dB
3.0 15.0
V/mV
6-99
UC3178
ELECTRICAL
Unless otherwise stated specifications hold for TA= 0°C to 70°C , Ve(+) = VIN(+) = 1'ZI/,
CHARACTERISTICS (cont.): REF Input= V1N(+)/2, 0/C Input & Inhibit Input= OV.
PARAMETER
TEST CONDITIONS
Power Ampllflera A & B (cont.)
Gain Bandwith Product
AAmplifler
BAmplifier
Slew Rate
High-Side Current Limit
Output Saturation Voltage
H.!9!1-Side, IOUT = -100mA
H!g!i-Side, loUT = -300mA
High-Side, louT = -450mA
Low-Side, IOUT = 100mA
Low-Side, IOUT = 300mA
Low-Side, IOUT = 450mA
Total Vsat, louT = 100mA
Total Vsat, IOUT = 300mA
Total Vsat, IOUT = 450mA
Hlll._h-Side Diode, Vf
ID=450mA
Current Sense Amplifier
Input Offset Voltage
VcM = 6V, Low range mode
High range mode
Input Offset Change
VeM = -1Vto 13V, Supplies= 1'ZV, Low Range Mode
with Common Mode Input
VeM = -1Vto 13V, Supplies= 12V, High Range Mode
Voltage Gain
VDIFF = +1.0 to -1.0V, Vern= 6V, High Range Mode
VDIFF = +1.0 to -1.0V, Vern= 6V, Low Ran_.9.e Mode
Saturation Voltage
Low-Side, IOUT = 1mA
High-Side, IOUT = -1 mA, Referenced to= VIN("!:}_
ln~ut Bias Current at Ref. Input
(REF Input - C/S(+))/48kohms, Tj = 25°C
Load Current Sense and Rectification
Sense Buffer Offset Voltage
REF lnputto IDIF REF, louT = ±1 mA
Sense Buffer CMRR
loUT = ±1 mA, REF Input= 2V to 10V
IDIF REF to IDIF Out Current
IDIF = ± 100µA, IDIF Out= 1V
Ratio
IDIF = ±1 mA, IDIF Out= 1V
IDIF Out SuH!Y_Sensitivity
IDIF Out = ± 1mA, V1N(t}_ = 4V to 15V,REF Input= 2V
IDIF Out Common Mode Sensitivity loUT = ±1 mA, REF Input= 'ZV to10V, IDIF Out= 1V
(delta IDIF Out/delta REF Input)
Auxiliary Functions
Inhibit Input Threshold
Inhibit Input Current
Inhibit Input = 1.7V
0/C Force l~ut Threshold 0/C Force I~ Current
0/C Force l'!e_ut = 1.7V
Ran_jje Input Threshold
Range l'!e_ut Current
Range Input= 1.7V
COMP ADJ Pin Saturation
Range Input= OV, Pin Current= ±500µA, Referenced
Voltage
toAoUT
COMP ADJ Leakage Current
Range Input = 1.7V, Supplies = 12V
AoUT-VCompAdj = ±6V
Total Supply Current When Inhibited VIN(+) and Ve(+) currents
Thermal Shutdown Temperature
MIN TYP MAX UNITS
2.0
MHz
1.0
MHz
1.0
V/µs
0.45 0.65
A
0.75
v
0.85
v
0.9
v
0.2
v
0.25
v
0.30
v
0.95 1.2
v
1.05 1.4
v
1.25 1.6
v
1.30
v
0.485 1.95
15
0.50 2.0 0.1 0.1 21
2.0 mV
4.0 mV
2000 y.VN
4000 µVN
0.515 VN 2.05 VN
0.3 v 0.3 v
27 µAN
10 mV
70 90
dB
0.95 1.0 1.05 NA
0.94 1.0 1.06 NA
1.0 5.0 J!N1_
1.0 5.0 µAN
0.6 1.1
1.7
v
-1.0 -0.5
µA
0.6 1.1
1.7
v
50 100 ~
0.6 1.1
1.7
v
50 100 µA
0.02 0.1
v
5.0 µA
1.0 1.5 mA
165
oc
6-100
UC3178
PIN DESCRIPTIONS: A & B OU"J: Outputs for the A & B power amplifiers, providing differential drive to the load during normal operation. During a UVLO, Inhibit, or 0/C condition both of these outputs will be in a high, source only state. Highside diodes are included to catch inductive load currents flowing into these pins, inductive kicks on the low-side are caught by the high-side output transistors.
AIN(+): Non-inverting input to the A amplifier. Normally tied to the REF Input when the current sense amplifier is used.
AIN(-): Inverting input to the A amplifier. Used as the summing node to close the loop on the overall power amplifier.
BIN(+): Non-inverting input to the B amplifier. This pin normally sets the reference point for the differential voltage swing at the load.
BIN(-): Inverting input to the B amplifier. Used to program the gain of the B amplifier.
COMP ADJ: The compensation adjust pin allows the user to provide an auxiliary compensation network for the A amplifier that is only active when the current sense amplifier is in the low range. With this option, the user can control the change in bandwidth that would otherwise result from the gain change in the feedback loop.
C/S(+): The non-inverting input to the current sense amplifier is typically tied to the load side of the series current sense resistor. This pin can be pulled below ground during an abrupt load current change with an inductive load. Proper operation of the current sense amplifier will result if this pin does not go below ground by an amount greater than:
(REF Input/2) - 0.311.
C/S(-): The inverting input to the current sense amplifier is typically tied to the connection between the B amplifier output and the current sense resistor that is in series with the load.
C/S Output: The output of the current sense amplifier has a 1.SmA current source pull-up and an active NPN pulldown. The output will pull to within 0.3V of either rail with a load current of less than 1mA.
GND: Reference point for the internal reference, 0/C comparator, and other low-level circuitry.
IDIF OU'r. Current source output pin. The value of the output current is nominally equal to the magnitude of the current through the IDIF REF pin.
IDIF REF: Output of the IDIF sense buffer. Voltage on this pin will track the applied voltage on the REF Input pin. Current through this pin is full wave rectified and appears as a current sourced from the IDIF OUT pin.
Inhibit : A high impedance logic input that disables the A and B power amplifiers, the IDIF sense buffer, and the Current Sense amplifier. This input has an internal pull-up that will inhibit the device if the input is left open.
0/C Force: Logic input that forces the 0/C condition.
0/C IND: Open collector ouput that indicates, with an active low state, an 0/C condition.
O/C Sense: Input to the Over Current Comparator. When this input is above its 1V threshold the low-side devices of both the A & B power amplifiers will be disabled forcing a high, source only, state at both outputs.
PWR GND: Current return for all high level circuitry, this pin should be connected to the same potential as GND.
Range: When this pin is open or at a logic low potential, the current sense amplifier will be in its low range mode. In this mode the voltage gain of the amplifier will be 2. If this pin is brought to a logic high, the gain of the current sense amplifier will change into its high range value of 0.5. This factor of four change in gain will vary the overall transconductance of the power amplifier by the same ratio, with the transconductance being the highest in the high mode. This feature allows improved dynamic range of load current control for a given control input range and resolution.
REF Input: Sets the Reference level at the C/S Output, and is normally tied to the system reference level for inputs to the power amplifier.
VIN(+): Provides bias supply to the device. The High-Side drive to the power stages on both the A and B amplifiers is referenced to this pin. The High-side saturation voltages, and UVLO are specified and measured with respect to this supply pin.
Ve(+): This supply pin is the high current supply to the collectors of the high-side NPN output devices on the A and B amplifiers. This supply should be powered whenever the A or B amplifiers are to be activated. This pin can operate approximately 400mV below the VIN(+) supply without affecting the voltage available to the load.
6-101
TYPICAL APPLICATION
CONTROL RA INPUT REFERENCE INPUT ---+--+-+-+---!
UC3178
INHIBIT IN 12V SUPPLY------!----!
Power amplifier transconductance
Go = .!]__ = RB · . 1 Vs RA AVcs· RS
Peak commanded load current
II -
MAX-
II. o/c
·
RS·
ARVDcs·
RE
UDG-92009
where: II is the load current Vs is the input command voltage AVcs is the current sense amplifier gain = 2.0 in low range mode
=o.s in high range mode
Vo;c is the 1.0V over-current comparator threshold
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD.' MERRIMACK. NH 03054 TEL (003) 424-2410 ·FAX (603) 424-3460
6-102
n n INTEGRATED
~CIRCUITS
-UNITROOE
UC3622
Switchmode Driver for 3-0 Brushless DC Motors
FEATURES 2A Continuous, 3A Peak Output Current BV to 40V Operation Fixed-Frequency 4 Quadrant PWM for SeNo Applications TIL Compatible Hall Inputs Pulse-by-Pulse Current Limiting Internal Thermal Shutdown Protection Under-Voltage Lockout
15 Lead, 25W Multiwatt Package
DESCRIPTION
The UC3622 is a brushless DC motor drive capable of decoding and driving all 3 windings of a 3-phase brushless DC motor. In addition, an on-board oscillator and latched PWM comparator provide the necessary circuitry for implementing a fixed-frequency, pulse width modulated seNo amplifier. Full protection, including thermal shutdown, pulse-bypulse current limiting, and under-voltage lockout aid in the simple implementation of reliable designs. Both conducted and radiated EMI have been reduced by limiting the output dv/dt to 150µs for any load condition.
The UC3622 will decode and drive all 3-phase motors with hall decode schemes compatible with Table 1. All other schemes can be decoded with the addition of a single external inverter. Consult factory for availability of military versions.
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage, Vee ............................................. 40V Output Current, Source or Sink
Non-Repetitive (t = 100µsec), lo ................................... 3A Repetitive (80% on - 20% off; toN = 1Oms)......................... 2.5A DC Operation ................................................. 2A Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +Vee Logic Inputs ............................................ -0.3 to +Vee Total Power Dissipation (at TCASE = 75°C) .......................... 25W Storage and Junction Temperature. . . . . . . . . . . . . . . . . . . . . . -40°C to +150°C Note 1: All voltages are with respect to ground, pin 8. Currents are positive into,
negative out of the specified terminal. Consult Packaging Section of Databook for thermal /imitations and considerations of package.
BLOCK DIAGRAM
U.V. LOCK 1---...-----...,
THERM. S.D.
VCONTROL
6/93
GND
1 INHIBIT LOCK DIR HA He H c
6-103
CONNECTION DIAGRAM
(TOPVIEW) V, VH PACKAGE
~
15
$
)__J
/
-$-1143
12
11
10
9
8 7
-
6
5
i-$-
1
Tab connected to Pin 8
COUT BOUT
DIRECTION
He He HA
INHIBIT GROUND ::::i LOCK
RT/CT VCONTROL
I SENSE
vcc
AOUT
EMITTERS
UC3622
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA= 0°c to 10°c; Vee
(PIN3) = 20V, RT = 47k, CT = .015µF, TA= TJ.
PARAMETER PWM Comparator Section
Input Offset Voltage 11!.E>_ut Bias Current Current Sense Section Input Bias Current Internal Offset Voltage Oscillator Section Initial Accuracy Temperature Stability Ramp Peak Ramp Valley Decoder Section High-Level Input Voltage Low-Level Input Voltage High-Level Input Current Low-Level Input Current Output Section
TEST CONDITION
TJ=25°C Over 0_.e_erating Range
MIN. TVP. MAX. UNIT
10 mV
5
µA
5
µA
.25 0.3 .35
v
9
10 11 kHz
2
%
3.6
v
1.3
v
2.5
v
0.8 v
10 µA
-10
µA
Output Leakage Current VF, Schottky Diode TOtal Output Voltage Drop
Vcc=40V lo=2A lo = 2A, Note 3
500 µA
1.5 2.0 v 3.0 3.6 v
Output Rise Time
RL=44Q
150
ns
Output Fall Time
AL= 44Q
150
ns
Under-Volt~e Lockout Start-up Threshold Threshold Hysteresis
8.0 v
0.5
v
Thermal Shutdown
Junction Temperature
150
180 oc
Total Standby Current
Supply Current
..
32 55 mA
Note 2: These parameters, although guaranteed over the recommended operating cond1t1ons, are not 100% tested m production.
Note 3: The total voltage drop is defined as the sum of both top and bottom side driver.
6-104
UC3622
TABLE 1
STEP
INHIBIT
DIR
1
0
1
2
0
1
3
0
1
4
0
1
5
0
1
6
0
1
1
0
0
2
0
0
3
0
0
4
0
0
5
0
0
6
0
0
-
1
x
-
0
x
H =HIGH OUTPUT L =LOW OUTPUT
HA
Ha
He
1
0
0
1
1
0
1
1
1
0
1
1
0
0
1
0
0
0
1
1
1
1
1
0
1
0
0
0
0
0
0
0
1
0
1
1
x
x
x
x
x
x
= l?J OPEN (TRISTATE) OUTPUT
LOCK
1 1 1 1 1 1 1 1 1 1 1 1
x
0
AouT
r2J L L r2J H H H H r2J L L r2J r2J H
BOUT H H
r2J L L r2J r2J L L r2J H H r2J r2J
CouT L
r2J H H r2J L L r2J H H r2J L r2J L
CIRCUIT DESCRIPTION The UC3622 is designed for implementation of a complete 3-phase brushless DC servo drive using a minimum number of external components. Below is a functional description of each major circuit function.
TIMING An RC circuit at Pin 6 is used to set the PWM frequency, as shown in Figure 2. The frequency is determined by the formula:
DECODER Table 1 shows the logic scheme employed to decode and drive each of three high current, totem pole, output stages. A torward/reverse signal, Pin 13, is used to provide direction. At any time, one driver is sourcing, one driver is sinking, and the remaining driver is off or tristated. Pulse width modulation is accomplished by chopping all drivers during current control (fixed-frequency PWM), producing a four-quadrant, regenerative mode drive. Controlled output rise and fall times help reduce electrical switching noise while maintaining relatively small switching losses.
HALL INPUTS The Hall input pins (#10, 11 , 12) are not provided with internal pull-up resistors. If these are required for the Hall devices, they must be added externally.
CURRENT LIMIT Referring to Figure 1, emitter current is sensed across RLIMIT and fed back through a low pass filter to the current sense, Pin 4. This filter is required to eliminate false triggering of the monostable due to leading edge current spikes. Actual filter values, although somewhat dependent on external loads, will generally be in the 1k and
1OOOpF range. An internal 0.3V reference voltage limits the motor current to
IMAX·~ RLIMIT
f .. Vose- 2.43 [H.zj
2.27RTCr
NOTE: RT should be chosen so that
SOµA Vose - 2.27 1mA
< 2.27Rr <
INHIBIT The INHIBIT input (Pin 9) must be low during normal operation. A high level at this pin forces all three outputs to the open state, and can be used to allow the motor to coast.
LOCK
A low level at LOCK (Pin 7), together with a low level at INHIBIT sets the following output condition:
AoUT ..... HIGH BOUT .... OPEN CoUT .... LOW
This can be used as part of a circuit intended to force the motor shaft to a desired parking position.
PROTECTION FUNCTIONS Protective functions including under-voltage lockout, peak current limiting, and thermal shutdown, provide an extremely rugged device capable of surviving under many types of fault conditions. Under-voltage lockout guarantees the outputs will be off or tri-stated until Vee is sufficient for proper operation of the chip. Current limiting limits the peak current for a stalled or shorted motor, whereas thermal shutdown will tri-state the outputs if a temperature above 150°C is reached.
6-105
APPLICATION MATERIAL
+
+ VMOTOR
UC3622
FORWARD/ REVERSE
Figure 1. Open Loop Speed Control with Current Limiting
HALL SENSORS
Vose
"'lPIN
CTI
6
Figure 2. PWM Oscillator Waveform
___ £~'" _=_;s~v
2.27V
j__
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. · MERRIMACK, NH 030!54 TEL. (603) 424-2410 ·FAX (803) 424-3460
6-106
n n L'.::::::'._J
INTEGRATED CIRCUITS
-UNITRDDE
UC3623
Low Noise Switchmode Driver for 3-0 Brushless DC Motors
FEATURES 1A Continuous, 2A Peak Output Current
SV to 40V Operation
Internal High Gain Amplifier for Velocity Control Applications
TTL Compatible Hall Inputs
Mask Programmable Decode Logic
Pulse-by-Pulse Current Limiting
Internal Thermal Shutdown Protection
DESCRIPTION
Designed specifically for noise-sensitive environments, the UC3623V monolithic driver IC offers the high efficiency of a chopper drive and the low EMI attainable with controlled output slew rates.
The UC3623 is a brushless DC motor drive capable of decoding and driving all 3 windings of a 3-phase brushless DC motor. In addition, an on-board current comparator, oscillator, and high gain Op-Amp provide all necessary circuitry for implementing a high performance, chopped mode servo amplifier. Full protection, including thermal shutdown, pulse-by-pulse current limiting, and under-voltage lockout aid in the simple implementation of reliable designs. Both conducted and radiated EMI have been greatly reduced by limiting the output dv/dt to 150V/µs for any load condition.
The UC3623 offers standard 120 electrical degree. Hall decoding per Table 1. Consult factory for availability of military versions.
BLOCK DIAGRAM
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage, Vee ................................................ 40V Output Current, Source or Sink
Non-Repetitive (t = 100µsec), lo ..................................... 2A Repetitive (80% on - 20% off; TON = 1Oms) . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5A DC Operation .................................................... 1A Analog Inputs .............................................. -0.3 to +Vee Logic Inputs................................................ -0.3 to +Vee
Storage and Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +150 ·c
Note 1: All voltages are with respect to ground, pin 8. Cuffents are positive into, negative out of the specified terminal.
TIMING
Vee
.-----------------i91-----------l
6/93
GND
I SENSE
,,___ ___, 11----~
FWD/ HA He He REVERSE HALL INPUTS
EMITTERS
6-107
CONNECTION DIAGRAM
V-VH PACKAGE (TOPVIEW)
UC3623
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA= 0°c to 10°c; Vee
(PIN 3) = 20V, RT= 1Ok,CT=2.2nf, TA= TJ.
PARAMETER Error Amplifier Section
TEST CONDITIONS
MIN TVP MAX UNIT
Input Offset Voltage Input Bias Current
1.5 10 mV -.25 -2.0 µA
Input Offset Current Common Mode Range
Vee = av to 40V
15 250 nA
0
v VIN-2
Open Loop Gain Unity Gain Bandwidth Output Sink Current
AVPIN6 = 1Vto 4V TJ = 25°C, Note 2 VPIN6= 1V
80 100 0.8 2
dB MHz mA
Output Source Current Current Sense Section
Input Bias Current Internal Clamp Divider Gain Internal Offset Volt~e
VPIN6 = 4V
8
mA
-2.0 -5
µA
v .425 0.5 .575
.180 0.2 .220 VN
.8
1.0 1.2
v
Timing Section Output Off Time Upper Mono Threshold Lower Mono Threshold
18 20 22 µs
5.0
v
2.0
v
Decoder Section High-Level Input Voltage Low-Level Input Voltage High-Level Input Current Low-Level Input Current
2.2
v
0.8 v
10 µA
-10
µA
Output Section
Output Leakage Current VF, Schottky Diode VF, Substrate Diode Total Output Voltage Drop Output Rise Time
Vee= 40V lo= 1A lo= 1A lo= 1A, Note 3 RL=44Q
500 µA
1.5 2.0
v
2.2 3.0
v
3.0 3.6
v
350
ns
.. Output Fail Time
AL =44Q
170
Note 2: These parameters, although guaranteed over the recommended operating cond1t1ons, are not 100% tested m
ns
production.
Note 3: The total voltage drop is defined as the sum of both top and bottom side driver.
6-108
UC3623
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA= o·c to 10°c; Vee (PIN 3)
= 20V, RT= 10k, CT= 2.2nF, TA= TJ.
PARAMETER
l
TEST CONDITIONS
I I I I MIN TYP MAX UNIT
Under-VoHage Lockout
Start-Up Threshold Threshold Hysteresis
f
I I I I 8.0 v l l l 0.5 l v
Thermal Shutdown
Junction Temperature
I
l 1150
J l 1ao ·c
Total Standby Current
Supply Current
l
l
l l l 32
55 mA
TABLE 1
STEP
FWD/REV
HA
He
He
Aour
BOUT
Cour
1
1
1
0
1
H
L
0
2
1
1
0
0
H
0
L
3
1
1
1
0
0
H
L
4
1
0
1
0
L
H
0
5
1
0
1
1
L
0
H
6
1
0
0
1
0
L
H
1
0
1
0
1
L
H
0
2
0
1
0
0
L
0
H
3
0
1
1
0
0
L
H
4
0
0
1
0
H
L
0
5
0
0
1
1
H
0
L
6
0
0
0
1
0
H
L
TYPICAL APPLICATIONS
VMOTOR
RT TIMING
I~--------------------- 9 I I I I I I
FWD/REVERSE
RSENSE
3-0 Brushless DC Open Loop Motor Drive with Current Limit
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6-109
n.. n l::::::J
·INTEGRATED
CIRCUIT9
-UNITRODE
·~ ·a· ·-·.·~···,·-....... ......,.···:·i~ :i··i·..·I.I
Low Saturation, Linear Brushless DC Motor Driver
UC3655
··FEATURES Total Saturation Voltage of Less Than 1 Volt Sink Current Capability of up to 3Amps Quiescent Current Less Than 1OmA Single Supply 5 Volt Operation Motor Voltage of 5 tci 40 Volts Full Decode for 3 Phase TTL Hall Sensors 120 Electrical Degree Logic Linear Closed-Loop Motor Current Control
BLOCK DIAGRAM
DESCRIPTION
The UC3655 DC motor driver achieves extremely efficient operation by using external PNP transistors selected for low saturation voltage as high side drivers. These are complemented with low side NPN drivers internal to the UC3655 which also have very low saturation losses. The PNP's can be low power devices as they are always switched into saturation by the action of internal 1OOmA base drivers, while the on-chip NPN's are driven linearly to control motor current. The result is a total source/sink saturation voltage drop of less than 1V at 1A load current
This controller offers further efficiency by using only a 5V supply with a current requirement proportional to motor current. The quiescent supply current with the outputs off is less than 1OmA
In addition to the power output stages, the UC3655 contains 120 electrical
degree hall logic decoding with forward, reverse, and inhibit functions se-
lectable by a single pin. Also included in control amplifier to drive the sink output current linearly response to an input command voltage. Finally, full protection is offered with under-voltage lockout, current limiting, and thermal shutdown. The UC3655 is packaged in both a high-power 15-pin Multiwatt® plastic package and, for low power requirements, a 28-pin PLCC surface mount configuration.
POSITION
11-----1 DECODE 1 - - - - - ' LOGIC
6/93
6-110
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage, Vs ................................. 7V Output Voltage, Ve (Source and Sink) ................. 40V Sink Output Current ................................ 3A Source Drive Current . . . . . . . . . . . . . . . . . . . Internally Limited Logic and Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 7V Total Power Dissipation (At TTAB = 75°C)
V Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25W QP Package.................................. 4.0W Storage and Junction Temperature .......... -40°C to 150°C
Note 1: All voltages are with respect to ground. Currents are positive into, negative out of the specified terminal. Consult Packaging Section of Databook for thermal limitations and considerations of packages.
UC3655V(H) (TOPVIEW)
r--iri==e==;i
UC3655
CONNECTION DIAGRAMS
PLCC-28 (TOPVIEW) QP Package
L4 3 2 1 28 27 26
5
25
6
24
7
23
8
22
9
21
10
20
11
19~
12 13 14 15 16 17 18
~=
PACKAGE PIN FUNCTIONS
FUNCTION
PIN
GND
1-2
COMP
3
FWD/REV
4
PHASE A
5
PHASE B
6
PHASEC
7
SOURCEOUTC
8
N/C
9
SINKOUTC
10
N/C
11
GNDJ_HEATFLOW}_ 12-18
CURRENT SENSE 19 lSENS.§_
CURRENT SENSE 20
JFORCI;}_
SINK OUT A
21
SOURCE OUT A
22
N/C
23
SINKOUTB
24
SOURCEOUTB
25
Vs +5V
26
N/C
27
INPUT
28
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA= 0°C to 70°C,
Vs= 5.0 Volts and RSENSE = 0.2Q, TA= TJ.
PARAMETER Sink Driver Section
Collector Leakage
Saturation Voltage
Coll. Diode Vt Source Driver Section
Collector Leakage Saturation Voltage Current Limit Amplifier Section Input Low Voltage Input High Voltage Closed Loop Transconductance Control Amp Transconductance Voltage Gain to Current Sense Input Bias Current Comp. Source Current Comp. Sink Current Decoder Section High-level Input Voltage Low-level Input Voltage High-level Input Current Low-level Input Current
CONDITIONS
Ve =40V le= 2A, Rs= 0 le=1A,Rs=0 It= -1A
Ve =40V le= 0.1A Ve= 5V, TA= 25°C
Sink Current= OA Sink Current = 2A Sink Current = 0-2A leOMP = ± 50µA VIN= 2-3V VIN=5V VIN= 5V, VeOMP = .9V VIN= OV, VeOMP = .9V
Phase Input Phase Input Phase Input Phase Input
MIN TYP MAX UNITS
500 µA
0.8
1.0
v
0.4 0.5
v
2.0 v
100 µA
1.9 2.3
v
100 175 300 mA
0.8 1.0 1.2
v
4.5 5.0 5.5
v
0.45 0.5 0.55 s
0.2
ms
-20
dB
0.5 1.0 mA
-50 -100 -150 µA
50 100 150 µA
2.2
v
0.8 v
10 µA
-10
µA
6-111
UC3655
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA= o·c to 70°C,
Vs= 5.0 Volts and RsENSE = 0.2"1, TA= TJ.
PARAMETER Decoder Section (cont.)
Input VOltaJLe to Inhibit Forward Command Input V Reverse Command Input V S~Sectlon Tum-on Threshold Threshold 1-fysteresis $~Current Su~Current Thermal Shutdown Shutdown Hysteresis
CONDITIONS
FWD/REV FWD/REV FWD/REV
Vs Low to High
Outputs Inhibited Sink Current = 2A Junction Temperature Junction Temperature
MIN TYP MAX UNITS
1.8
32 v
0.6 v
4.4
v
3.5 4.0 4.7
v
0.5
v
6.0 10 mA
25 100 mA
150
·c
5
·c
DECODE LOGIC TRUTH TABLE:
lnhlbH
FWD/REV
x x
Inhibit
Phase Input
A
B
c
0
0
0
1
1
1
x x x
Source Drive
A
B
c
Off
Off
Off
Off
Off
Off
Off
Off
Off
Sink Output
A
B
c
Off
Off
Off
Off
Off
Off
Off
Off
Off
Motor Tenn
A
B
c
0
0
0
0
0
0
0
0
0
L
1
0
1
On
Off
Off
Off
On
Off
H
L
0
L
1
0
0
On
Off
Off
Off
Off
On
H
0
L
L
1
1
0
Off
On
Off
Off
Off
On
0
H
L
L
0
1
0
Off
On
Off
On
Off
Off
L
H
0
L
0
1
1
Off
Off
On
On
Off
Off
L
0
H
L
0
0
1
Off
Off
On
Off
On
Off
0
L
H
H
1
0
1
Off
On
Off
On
Off
Off
L
H
0
H
1
0
0
Off
Off
On
On
Off
Off
L
0
H
H
1
1
0
Off
Off
On
Off
On
Off
0
L
H
H
0
1
0
On
Off
Off
Off
On
Off
H
L
0
H
0
1
1
·On
Off
Off
Off
Off
On
H
0
L
H
0
0
1
Off
On
Off
Off
Off
On
0
H
L
= = = (Note: X Don't Care; lnh 2.5 ± 1~ Hand L levels defined by applications; Motor Term O High Impedance).
TYPICAL MOTOR DRIVE APPLICATION
+5 VOLTS
VM · 5 TO 40V
R2 is only used to reduce UC3655 power dissipation or limit source current to less than 100mA
CH A SOR DRIVE
CH A SINK DRIVE
CURRENT FB (All 3 Channels)
---~~"'i
0.1A VIN
Rs -~
Note: Rs must be non-inductive and located as close as possible to the UC3655 to avoid parasitic oscillations. 6-112
Linear Transconductance Amplifier
UC3655
Source Drivers SOURCE DRIVE PINS 3,5,14
100µA
CHANNEL SELECT
LOGIC
3 OHMS
Forward/Reverse Input
5.0V
Phase Inputs
1.SV REF
TO
DECODE
LOGIC
6-113
Sink Output Vsat vs Current
0 0.2 0.4 0.6 0.6 1 1.2 1.4 1.6 1.6 2 SINK OUTPUT CURRENT · A
Vs Supply Current vs Sink Current
v
r..:'.l .k::'.
!:::'.'.
~
.k::'.
-1
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 SINK OUTPUT CURRENT · A
UC3655
Control Transfer Characteristics
<
I- 3.0 -+---~~--1,__-+---~---~
z
:aaw:::::>
2.0 +--+-+-_,_--1--Y-~-~~-~-1
0
I-
e::> 1.0 +--+-l--7"'--l-+~..c...-1-+-f--1
5
0.0 +--=-+--+---1-+--+-+--+--f---1
0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.o 8.0 9.0 10.0
INPUT CONTROL VOLT AGE · V
Source Driver Output Vsat vs Current
>
' 3.6
w
CJ
3.2
<
I..J
2.8
>0 2.4
z
Q 2.0
Ia<-: 1.6
::::>
I<- 1.2
I II
/ TJ=25°Cfj
TJ =125°C
l-
1-
17
IL
..;::;Ll !-'"
..... !-'"
~
l/J 0.8 i:;-
20 40 60 80 100 120 140 160 180
SOURCE DRIVER OUTPUT CURRENT · mA
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. · '-ERRIMACK, NH 03054 TEL 603·424-2410 ·FAX 603·424-3460
6-114
n n L::::::j
INTEGRATED CIRCUITS
-UNITRODE
Stepper Motor Drive Circuit
UC3717A·
FEATURES Full-Step, Half-Step and Micro-Step Capability
Bipolar Output Current up to 1A
Wide Range of Motor Supply Voltage 10-46V
Low Saturation Voltage with Integrated Bootstrap
Built-In Fast Recovery Commutating Diodes
Current Levels Selected in Steps or Varied Continuously
Thermal Protection with Soft Intervention
DESCRIPTION The UC3717A is an improved version of the UC3717, used to switch drive the current in one winding of a bipolar stepper motor. The UC3717A has been modified to supply higher winding current, more reliable thermal protection, and improved efficiency by providing integrated bootstrap circuitry to lower recirculation saturation voltages. The diagram shown below presents the building blocks of the UC3717A. Included are an LS-TTL compatible logic input, a current sensor, a monostable, a thermal shutdown network, and an H-bridge output stage. The output stage features built-in fast recovery commutating diodes and integrated bootstrap pull up. Two UC3717As and a few external components form a complete control and drive unit for LS-TIL or micro-processor controlled stepper motor systems.
The UC3717A is characterized for operation over the temperature range of 0°C to +70°C.
ABSOLUTE MAXIMUM RATINGS (Note 1)
Voltage Logic Supply, Vee ...................................... 7V
Output Supply, Vm ..................................... 50V
Input Voltage Logic Inputs (Pins 7, 8, 9) ................................ 6V Analog Input (Pin 10) ................................... Vee Reference Input (Pin 11) ................................ 15V
Input Current Logic Inputs (Pins 7, 8, 9) ............................. -10mA Analog Inputs (Pins 10, 11) ............................ -1 OmA
Output Current (Pins 1, 15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . :t1 .2A Junction Temperature, TJ ............................... +150°C Storage Temperature Range, Ts .................. -55°C to +150°C
Note 1: All voltages are with respect to ground, Pins 4, 5, 12, 13. Currents are positive into, negative out of the specified terminal. Pin numbers refer to DIL-16 package.
Consult Packaging Section of Databook for thermal limitations and considerations ofpackage.
BLOCK DIAGRAM
vee
.--~~~~~~~61--~~~~~~~~~~~~~-1
3,14 VM
*Consult Factory
Thermal Shuldown
1--~~~~~~--<21--~~~~~~~--1
Current
Timing
Emitters
UC3717A
6-115
CONNECTION DIAGRAMS DIL-16 (TOP VIEW) J or N Package
BOUT Timing
Vm Gnd Gnd
11 Phase
UC3717A
PLCC-20 (TOP VIEW) Q Package
4
18
5
17
6
16
7
15
8
14
9 10 11 12 13
PACKAGE PIN FUNCTION
FUNCTION
PIN
r:-U:c
1
BOUT
2
Timin!'.I
3
Vm
4
Gnd
5
r:-U:c
6
Gnd
7
Vee
8
h
9
Phase
10
r\ilc
11
lo
12
Current
13
VR
14
Gnd
15
N/C
16
Gnd
17
Vm
18
AouT
19
Emitters
20
ELECTRICAL CHARACTERISTICS (Refertothetestcircuit, Figure 6. Vm = 36V, Vee= 5V, VA= 5V, TA= 0°Cto 70°C,
unless otherwise stated, TA= TJ.)
PARAMETERS
TEST CONDITIONS
Supply Voltage, Vm (Pins 3, 14)
Logic Supply Voltage, Vee (Pin 6)
Logic Supply Current, Ice (Pin 6)
lo= 11 =0
Thermal Shutdown Temperature
Logic Inputs
Input Low Volt~e.JPins 7, 8, 9)
Input High Voltage, (Pins 7, 8, 9)
Low Voltage Input Current, (Pins 7, 8, 9)
VI= 0.4V, Pin 8
V1 = 0.4V, Pins 7 and 9
High Voltage Input Current, (Pins 7, 8, 9)
VI= 2.4V
Comparators
Comparator Low, Threshold Voltage (Pin 10) VA = 5V; lo = L; 11 = H
Comparator Medium, Threshold Voltage (Pin 10) VA = 5V; lo = H; 11 = L
Com_E>_arator H_!g_h, Threshold Voltage (Pin 10) VA= 5V; lo= L; 11 = L
Comparator Input, Current (Pin 10)
Cutoff Time, toFF
RT = 56kQ, CT = 820pF
Turn Off Delay, to
(See Figure 5)
Source Diode-Transistor Pair
Saturation Voltage, VsAT (Pins 1, 15)
Im= -0.5A, Conduction Period
(See Figure 5)
Im= -0.5A, Recirculation Period
Saturation Voltage, VsAT (Pins 1, 15)
Im= -1A,
Conduction Period
(See F_!9.ure ~
Im =-1A,
Recirculation Period
Leakage Current
Vm = 40V
Diode Forward Voltage, VF
Im= -0.5A
Im= -1A
MIN TYP MAX UNITS
10
46 v
4.75
5.25 v
7
15 mA
+160
+180 oc
0.8 v
2
Vee v
-100 µA
-400 µA
10 µA
66 80 90 mV
236 250 266 mV
396 420 436 mV
±20 µA
25
35
µs
2
µs
1.7 2.1
v
v 1.1 1.35
2.1
2.8
v
1.7 2.5
v
300 µA
1 1.25 v
1.3 1.7
v
6-116
UC3717A
ELECTRICAL
(Refer to the test circuit, Figure 6. VM = 36V, Vee= 5V, VR = 5V, TA= 0°C to 70°C, unless
CHARACTERISTICSJ_cont_J_ 0 therw1.se stated,TA= TJ.)
PARAMETERS
TEST CONDITIONS
MIN TYP MAX UNITS
Sink Diode-Translator Pair Saturation Voltage, VsAT (Pins 1, 15)
Im= 0.5A Im= 1A
8
1.1 1.35 v
1.6 2.3 v
Leakag_e Current Diode Forward Voltage, VF
Vm =40V Im =0.5A Im= 1A
300 ~
1.1 1.5 v
1.4 2
v
4 1--+--+---+--+-+---+-T_A_=~2_5_'C---<
~
.t:: 3 I--+--+--+-+--+--+---+---+---+-~
Cl
i: eiini 2 +--+-+--+--+---+---+---+---+--+----<
!wt
1-t""
0 '--~-'----'--'--'--'--'--'--'-~ 0.2 0.4 0.6 0.8
Output Current (A)
Figure 1: Typical Source Saturation VoHage vs Output Current (Recirculation Period)
4 1--t--+--+--+--+--+---+--T_A-·2_5~'--;C
. ~
""
3 1--t--+--+--+---+---+---+---+---+---<
:f
!:
iii
2 f--t--+--+-+~ -+--t---l::;;......-1"'-=i
w
t-1
~ 1
0.2 0.4 0.6 0.8 Output Current (A)
Figure 2: Typical Source Saturation VoHage vs Output Currant (Conduction Period)
4 TA=25'C +--+--+--+--+---+---+---+-~~___,
~ 3 +--+--+--+--+---+---+---+---+---+-___,
I
0
-'
iii 2
w ~ w
1---+--+-+-+-~ -+-~'-f-=J.--r-=l
0.2 0.4 0.6 0.8 Output Current (A)
Figure 3: Typical Sink Saturation VoHage vs Output Current
; v 17 g 3 l--+--+-+-+--+--+--+--+--7'1---1
z y -~
., 2 1---t---+-+-+--t---hJ-"'!---+--+--1 i5
z ~; 1 f--+--+--+...'9-~--+--t--tl--t--+---; ......
0.2 0.4 0.6 0.8 Output Current (A)
Figure 4: "fyplcal Power Dissipation vs Output Current
ill----u-., <·l voo''",~'I
* u · 0 iq2 . ~) 7, (CJ V.o"' (PO'
~-r
0
~· rSAT REF
t
(D) VBOUT (Pin 1) :h\.::.t7T CONci
~ M (E) VM=VBOUT-VAOUT
n TOFF
OV p
-\__--~I-
t:=· I
Figure 5: "fyplcal Wavefonna with MA Regulating (phase= 0)
6-117
UC3717A
38V +SV
c
1k
cc
820pF
CT 820pF
Thermal Shutdown
UC3717A
Figure 6: UC3717A Test Circuit
FUNCTIONAL DESCRIPTION
The UC3717A's drive circuit shown in the block diagram includes the following components.
(1) H-bridge output stage (2) Phase polarity logic (3) Voltage divider coupled with current sensing compa-
rators (4) Two-bit D/A current level select (5) Monostable generating fixed off-time (6) Thermal protection
saturation voltage of source transistor 02 during recirculation, thus improving efficiency by reducing power dissipation.
OUTPUT STAGE The UC3717A's output stage consists of four Darlington power transistors and associated recirculating power diodes in a full H-bridge configuration as shown in Figure 7. Also presented, is the new added feature of integrated bootstrap pull up, which improves device performance during switched mode operation. While in switched mode, with a low level phase polarity input, 02 is on and 03 is being switched. At the moment 03 turns off, winding current begins to decay through the commutating diode pulling the collector of 03 above the supply voltage. Meanwhile, 06 turns on pulling the base of 02 higher than its previous value. The net effect lowers the
Note: Dashed lines indicate current decay paths. Figure 7: Simplified Schematic of Output Stage
6-118
FUNCTIONAL DESCRIPTION (cont.)
PHASE POLARITY INPUT The UC3717A phase polarity input controls current direction in the motor winding. Built-in hysteresis insures immunity to noise, something frequently present in switched drive environments. A low level phase polarity input enables 02 and 03 as shown in Figure 7. During phase reversal, the active transistors are both turned off while winding current delays through the commutating diodes shown. As winding current decays to zero, the inactive transistors 01 and 04 turn on and charge the winding with current of the reverse direction. This delay insures noise immunity and freedom from power supply current spikes caused by overlapping drive signals.
PHASE INPUT LOW HIGH
Q1,Q4 OFF ON
Q2,Q3 ON OFF
CURRENT CONTROL The voltage divider, comparators, monostable, and twobit D/A provide a means to sense winding peak current, select winding peak current, and disable the winding sink transistors.
The UC3717Aswitched driver accomplishes current control using an algorithm referred to as "fixed off-time." When a voltage is applied across the motor winding, the current through the winding increases exponentially. The current can be sensed across an external resistor as an analog voltage proportional to instantaneous current. This voltage is normally filtered with a simple Re lowpass network to remove high frequency transients, and then compared to one of the three selectable thresholds. The two bit D/A input signal determines which one of the three thresholds is selected, corresponding to a desired winding peak current level. At the moment the sense voltage rises above the selected threshold, the UC3717A's monostable is triggered and disables both output sink drivers for a fixed off-time. The winding current then circulates through the source transistor and appropriate diode. The reference terminal of the UC3717A provides a means of continuously adjusting the current threshold to allow microstepping. Table 1 presents the relationship between the two-bit D/A input signal and selectable current level.
TABLE1
lo
11
0
0
1
0
0
1
1
1
CURRENT LEVEL 100%
60% 19%
Current Inhibit
OVERLOAD PROTECTION The UC3717Ais equipped with a new, more reliable thermal shutdown circuit which limits the junction tempera-
UC3717A
ture to a maximum of 180C by reducing the winding current.
PERFORMANCE CONSIDERATIONS In order to achieve optimum performance from the UC3717A careful attention should be given to the following items.
External Components: The UC3717A requires a minimal number of external components to form a complete control and switch drive unit. However, proper selection of external components is necessary for optimum performance. The timing pin, (pin 2) is normally connected to an RC network which sets the off-time for the sink power transistor during switched mode. As shown in Figure 8, prior to switched mode, the winding current increases exponentially to a peak value. Once peak current is attained the monosmble is triggered which turns off the lower sink drivers for a fixed off-time. During off-time winding current decays through the appropriate diode and source transistor. The moment off-time times out, the motor current again rises exponentially producing the ripple waveform shown. The magnitude of winding ripple is a direct function of off-time. For a given off-time TOFF, the values of RT and CT can be calculated from the expression:
TOFF= 0.69RTCr with the restriction that RT should be in the range of 10100k. As shown in Figure 5, the switch frequency Fs is a function of ToFF and TON. Since TON is a function of the reference voltage, sense resistor, motor supply, and winding electrical characteristics, it generally varies during different modes of operation. Thus, Fs may be approximated nominally as:
Fs = 111.s (ToFF). Normally, Switch Frequency Is Selected Greater than 20kHz to prevent audible noise, and lower than 1OOkHz to limit power consumed during the switching cycle.
I
17
[Z
I\
VERT ·200mA/DIV HORIZ·1ma/DIV
~
I\
I
~ II
!\,. .A
.A
Figure 8: A typical winding current waveform. Winding current rises exponentially to a selected peak value. The peak value la limited by switched mode operation
producing a ripple In winding current. A phase polarity reversal command la given and winding current decays to zero, then Increases exponentlally.
6-119
FUNCTIONAL DESCRIPTION (cont.)
Low-pass filter components Re Cc should be selected so that all switching transients from the power transistors and commutating diodes are well smoothed, but the primary signal, which can be in the range of 1{TOFF or higher must be passed. Figure 5A shows the waveform which must be smoothed, Figure 58 presents the desired waveform that just smoothes out overshoot without radical distortion. The sense resistor should be chosen as small as practical to allow as much of the winding supply voltage to be used as overdrive to the motor winding. VRs, the voltage across the sense resistor, should not exceed 1.5V.
Voltage Overdrive: In many applications, maximum
speed or step rate is a desirable performance charac-
teristic. Maximum step rate is a direct function of the time necessary to reverse winding current with each step. In
response to a constant motor supply voltage, the winding
current changes exponentially with time, whose shape is
determined by the winding time constant and expressed as:
I
Vm
m - R [1-EXP (-RJi'LJ]
as presented in Figure 9. With rated voltage applied, the
time required to reach rated current is excessive when
compared with the time required with over-voltage ap-
plied, even though the time constant UR remains con-
stant. With over-voltage however, the final value of
UC3717A
current is excessive and must be prevented. This is accomplished with switch drive by repetitively switching the sink drivers on and off, so as to maintain an average value of current equal to the rated value. This results in a small amount of ripple in the controlled current, but the increase in step rate and performance may be considerable.
Interference: Electrical noise generated by the chopping action can cause interference problems, particularly in the vicinity of magnetic storage media. With th.is in mind, printed circuit layouts, wire runs and decoupling must be considered. 0.01 to 0.1 µF ceramic capacitors for high frequency bypass located near the drive package across V+ and ground might be very helpful. The connection and ground leads of the current sensing components should be kept as short as possible.
Half-Stepping: In half step sequence the power input to the motor alternates between one or two phases being energized. In a two phase motor the electrical phase shift between the windings is 90°. The torque developed is the vector sum of the two windings energized. Therefore when only one winding is energized the torque of the motor is reduced by approximately 30%. This causes a torque ripple and if it is necessary to compensate for this, the VR input can be used to boost the current of the single energized winding.
1zw-
IC IC
::;)
0
Cz l E z i
IR 6.31N
/
/
" --/
..W.....i..t.h Over-Voltage Applied,
Iha Phaaa Currant Would
/
Become Excessive.
/
/
/
Safa Value Maintained
/
by Switching Circuit.
~ """~/'-..
/
Slower Rise with
Rated Voltage Applied
0
L/R
2L/R
3L/R
4L/R
TIME
Figure 9: With rated voltage applied, winding current does not exceed rated value, but takes L/R seconds to reach 63% of
Its final value - probably too long. Increased performance requires an Increase In applied voltage, of overdrive, and therefore a means to limit currenl The UC3717A motor driver performs this task efficiently.
6-120
MOUNTING INSTRUCTIONS
The RTHJ-AMB of the UC3717A can be reduced by soldering the GND pins to a suitable copper area of the printed circuit board or to an external heat sink. The diagram Of Figure 11 shows the maximum package
power PTOT and the 8JA as a function of the side " t " of two equal square copper areas having a thickness of 35µ
(see Figure 10).
UC3717A
Figure 14 shows the required input signal for a one phase-two phase stepping sequence called half-stepping. The circuit of Figure 15 provides the signal shown in Figure 13, and in conjunction with the circuit shown in Figure 12 will implement a pulse-to-step two phase, full step, bi-directional motor drive.
COPPER AREA 35 JI. THICKfESS
\
P.C. BOARD Figure 10: Example of P.C. Board Copper Area which la
used as Heatalnk. During soldering the pins' temperature must not exceed 260°C and the soldering time must not be longer than 12 seconds. The printed circuit copper area must be connected to electrical ground.
+5 +5 +40
11
6
314
Phase A l1A loA
8 Ph VR Vee Vm
Bo A our
7 11
UC3717A
9
Ao 15
E
Bour
16 4,5 12,13
Stepping Motor
8
+5 +5 +40
11
6
314
Phase B 11 B loB
8 Ph VR Vee Vm 1
Bo A our
7 11
UC3717A
9
Ao 15
E
BOUT
4rl\.l---+--+--+--+-,_.,r-+--+--+-~eo
! i 3 l--tl'-d--!'.._9J,...A-+--t--+---t-+-t-1 60
').... E ...
t 2
~
~
40
r-
~
t-4::1 PTOT(TAMB·70·C) t-+- 20
0 o~~,o~-2~0~~30~-4~0~~ 0
Sidel - mm
Figure 11: Maximum Package Power and Junction to Ambient Thennal Resistance vs Side "!".
APPLICATIONS A typical chopper drive for a two phase bipolar permanent magnet or hybrid stepping motor is shown in Figure 12. The input can be controlled by a microprocessor, TTL, LS, or CMOS logic.
The timing diagram in Figure 13 shows the required signal input for a two phase, full step stepping sequence.
Figure 12: 'fyplcal Chopper Drive for a 1\vo Phase Permanent Magnet Motor.
The schematic of Figure 16 shows a pulse to half step circuit generating the signal shown in Figure 14. care has been taken to change the phase signal the same time the current inhibit is applied. This will allow the current to decay faster and therefore enhance the motor performance at high step rates.
ORDERING INFORMATION UNITRODE TYPE NUMBER: UC3717ANE - 16 Pin Dual-in-line (OIL) "Bat Wing" Package 3717AJ · 16 Pin Dual-in-line Ceramic Package
6-121
UC3717A
PHASE A PHASE B---~
----FWD
----REV
Figure 13: Phase Input Signal for Two Phase Full Step Drive (4 Step Sequence)
l1 l21al4l5l6f7IBI
PHASE A~
PHASEB~
I I
lo,11A~
lo,11B~
I
FWD
l1l2lal4l5l6l7IBI
~
~ I
~
~
l
REV
Figure 14: Phase and Current-Inhibit Signal for HaH-Stepplng (8 Step Sequence)
Direction __________, . . . . - - - - - - - - - - Phase A
Rev/Fwd
1k
PR
0 112 ar--~L__,
7474
CK CLR
PR
112 a
7474
CK
Q
CLR
Clear-+----+----+-------+--~
Phase B
Clock----e--------~
Figure 15: Full Step, Bi-directional Two Phase Drive Logic
+sv
Direction Switch
111
1k
1k
'>--+---9-< SO L
10 S1 11
CLR - - - + - - - -1i .,..
3A ; 4 .... 5 B
c
6 D
11A .--------IOA
~------11e
IOB
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. · MERRIMACK, NH 03054 TEL. (603) 424-2410 · FAX (603)424-3460
Figure 16: Half-Step, Bl-directional Drive Logic 6-122
n n l_:::'.j
INTEGRATED CIRCUIT&
-uNITRODE
High Performance Stepper Motor Drive Circuit
UC3770A UC3770B
FEATURES Full-Step, Half-Step and Micro-Step Capability.
Bipolar Output Current up to 2A.
Wide Range of Motor Supply Voltage: 10--SOV
Low Saturation Voltage
Wide Range of Current Control: 5mA-2A.
Current Levels Selected in Steps or Varied Continuously.
Thermal Protection and Soft Intervention.
DESCRIPTION
The UC3770A and UC3770B are high-performance full bridge drivers that offer higher current and lower saturation voltage than the UC3717 and the UC3770. Included in these devices are LS-TIL compatible logic inputs, current sense, monostable, thermal shutdown, and a power H-bridge output stage. Two UC3770As or UC3770Bs and a few external components form a complete microprocessor-controllable stepper motor powersystem.
Unlike the UC3717, the UC3770A and the UC3770B require external high-side clamp diodes. The UC3770Aand UC3770B are identical in all regards except for the current sense thresholds. Thresholds for the UC3770A are identical .to those of the older UC3717 permitting drop-in replacement in applications where highside diodes are not required. Thresholds for the UC3770B are tailored for half stepping applications where 50%, 71%, and 100% current levels are desirable.
The UC3770A and UC3770B are specified for operation from o·c
to 10°c ambient.
BLOCK DIAGRAM
Vee
AOUT BOUT 3.14 VM
.--~~~~~s1--~~~~~~~~~~~~~~n~-;1r-~~4r-~~~,
Vee
12/92
Monostable IOFF · 0.69RTCT
Sense
n1-~~~~~~~~21--~~~~~~~~~-tt1RI-~~~~~~~~
Current
Timing
Emitters
UDG-82039
6-123
ABSOLUTE MAXIMUM RATINGS
Logic Supply Voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Output Supply Voltage, VMM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50V Logic Input Voltage (Pins 7, 8, 9). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V Analog Input Voltage (Pin 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Vee Reference Input Voltage (Pin 11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V Logic Input Current (Pins 7, 8, 9) ................................. -10mA Analog Input Current(Pins 10, 11) . . . . . .. . . . . . . . . . . . . . . .. . . . . . . . . -1 OmA Output Current (Pins 1, 15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 2A Junction Temperature, TJ..·.................................... +150°C
Note 1: All voltages are with respect to Gnd (OIL Pins 4, 5, 12, 13); all cuffents are positive into, negative out of the specified tenninal. Note 2: Consult Unitrode Integrated Circuits databook for thermal limitations and considerations ofpackages.
CONNECTION DIAGRAMS
DIL-16 (Top View) J Or N Package
PLCC-28 (Top View) Q Package
~
Bour!J:
~Emitters
IT: Timing
~ AOUT
VM[I
~Vt.4
Gnd8::
~Gnd
Gnd(I
~Gnd
vcc(I 11 ~
Phase[I
SvR ~Current
~lo
L a ~=
~=
4 2 1 28 21 2e
5
25
6
24
7
23
8
22
9
21
10
20
11
19
12 13 14 15 16 17 18
UC3770A UC3770B
PACKAGE PIN FUNCTION
FUNCTION
PIN
Gnd
1-3
VM
4
NlC
5
AOUT
6
f\ll.C
7
Emitters
8
Gnd
9
BOUT
10
Timioa
11
VM
12
Gnd
13-17
Vee
18
11
19
Phase
20
lo
21
f\ll.C
22
Current
23
VR
24
N.LC
25-27
Gnd
28
ELECTRICAL CHARACTERISTICS: (All tests apply with VM = 36V, Vee= 5V, VR = 5V, No Load, and 0°C<TA<70°C,
unless otherwise stated, TA= TJ.)
UC3770A
UC3770B
PARAMETER Supply Voltage VM (Pins 3, 14) Logic Supply Voltage Vee (Pin 6) Logic Supply Current Ice (Pin 6)
Thermal Shutdown Temperature Logic Threshold (Pins 7, 8, 9) Input Current Low (Pin 8) Input Current Low (Pins 7, 9) Input Current High (Pins 7, 8, 9) Comparator Threshold (Pin 10)
Comparator Input Current (Pin 10) Off Time
TEST CONDITIONS
lo = 11 = H, IM = 0 lo = 11 = L, IM = 0 lo= 11 = H, IM= 1.3A
Vi= 0.4V Vi= 0.4V VI= 2.4V VR = 5V, lo = L, 11 = L VR = 5V, lo= H, 11 = L VR = 5V, lo = L, 11 = H
RT = 56k, Cr = 820pF
MIN TYP MAX MIN TYP MAX UNITS
10
45
10
45 v
4.75 5
5.3 4.75 5
5.3
v
15 25
15
25
mA
18 28
18
28
mA
33
40
+170
33
40 mA
+170
oc
0.8
2.0 0.8
2.0 v
-100 -400
-100 ~
-400 µA
10
10
µA
400 415 430 400 415 430 mV
240 255 265 290 300 315 mV
70
80
90
195 210 225 mV
±20
±20 µA
25
30
35
25
30
35 ms
6-124
ELECTRICAL CHARACTERISTICS (cont.):
PARAMETER Tum Off Del~ Sink Driver Saturation Voltage
Source Driver Saturation Voltage ---------
Output Leakage Current
UC3770A UC3770B
(All tests apply with VM = 36V, Vee= 5V, VR = 5V, No Load, and 0°C<TA<70°C, unless otherwise stated, TA= TJ.)
TEST CONDITIONS
IM= 1.0A IM= 1.3A IM= 1.0A IM= 1.3A VM=45V
UC3nQA MIN lYP MAX
2 0.8 1.3 1.3 1.6 100
UC3770B
MIN lYP MAX UNITS
2
ms
0.8 v
1.3 v
1.3 v
1.6 v
100 µA
Figure 1: Typical Source Saturation Voltages vs. Load Current
Figure 2: Typical Sink Saturation Voltages vs. Load Current
>
.c 18 .!2' I 16
e1nil
w
14 12
>Ll 10
8
6
TA=+25· C
_...!.---'
1--1 1--1
2 4 6 8 10 1214 16 18 20 Output Current - A
>
;: 14
.3 12
e1nil
~
>
10 6 6
4
2
TA=+25· C
Vi
kd
17'
v IL
kd
2 4 68101214161620
Output Current -A
Figure 3: Typical Supply Current
vs. Load Current
50
~ :~
~ 35
30
25
20
TA=+25· C
L"
12
v .%"
kf"
2 4 6 8101214161820 Output Current - A
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. · MERRIMACK, NH 03054 TEL. (603) 424-2410 · TELEX 95-3040
6-125
n n L::::J INTEGRATED CIRCUITS
-UNITRODE
6-126
i.: :f~ (U.. · ...~~ ) Indicates Application Nate A11ailable , .... ~~ See Section 9. 'G"'
Power Driver & Interface Circuits
n n INTEGRATED
~CIRCUITS
-UNITRDDE
7-2
n n INTEGRATED
~CIRCUITS
-UNITRODE
Product Selection Guide POWER DRIVERS, SWITCHES AND INTERFACE CIRCUITS
These devices act as high gain power transistors and have on-chip, current limiting, power limiting, and thermal overload protection. · Greater than 1.0A Output · 3.0µA Typical Base Current (Adjustable) · 500ns Switching Time · 2.0V Saturation Voltage · Directly Interfaces with CMOS or TTL · Internal Thermal Limiting
PWM Dual Driver
Load Control and Status monitoring for two inductive loads up to 1A each. · PWM Current Control · Dual Floating Switches · Supply Voltage up to 60V · Tri-State Status Outputs · Low Saturation Voltage
Half-Bridge Bipolar Switch
· Source or Sink 4.0A · Supply Voltage to 35V · High-Current Output Diodes · Tri-State Operation · TTL and CMOS Input Compatability · Thermal Shutdown Protection · 300KHz Operation
Triple Half-Bridge Power · Three 2A Drivers
Driver
· On Board Clamp Diodes
Independent high and low side switching, up to 2.5A capability · Full Protection · Over- and Under-Current Fault Indication · 50V Operation
· Five Current-Sinking Switches · Programmable Currents from.5 to 2.5A · Internal Current Sensing · 40V Operation · Protection .Features
Isolated High Side Drive for N-Channel Power MOSFET Gates
· Fully Isolated Drive for High Voltage · 0% to 100% Duty Cycle · 600KHz Carrier Capability · Local Current Limiting Feature
IGBT Driver Primary Side IGBT Driver Secondary Side
· Transmits to UC3727 · Able to Pass D.C. Information · Transmits Logic Signal Instantly · Receives Power and Signal Across Simple Pulse
Transformer · +15V, -5V Gate Drive Voltage · 4Amp (PK) Output Current · De-Sat Detect with Programmable Fault Response
· Consult Factory for Commercial 15 Pin Power Tab Package
T0-220
28 Pin OIL 28 PLCC
5 Pin T0-220
24Pin Power OIL
24Pin Power OIL
24Pin Power OIL
8 Pin OIL (Pair)
16 Pin OIL 28 Pin PLCC
7-3
n nINTEGRATED
~ CIRCUITEI
-UNITROCE
Product Selection Guide POWER DRIVERS, SWITCHES & INTERFACE CIRCUITS
Advanced Octal Single Ended Line Driver
Octal Line Receiver
Ethernet Coaxial Impedance Monitor
Suited for Data Transmission Systems · Eight Drivers in One Package · Meets EIA Standards · Single External Resistor Controls Slew Rate · Tri-State Outputs · Low Power Consumption · TTL Compatible
· Single TTL Mode Select · Eight Drivers in One Package · Single External Resistor Controls Slew Rate · Tri-State Outputs
Suited for Data Transmission Systems · Eight Drivers in One Package · Operates in EIA-423 Mode · Can Operate from Supplies up to ±1 SV · Can Withstand EDS of up to 40V (up to 1mS)
Suited for Digital Communication Requirements · Eight Receivers in One Package · Meets EIA Standards · Single SV Supply · Differential Inputs Withstand± 25V · Low Noise Filter
· Detects Cable Impedance Errors · Detects Cable Termination Errors · Compatible with IEEE 802.3, 10Base5, 10Base2,
and 10BaseT. · Preset and Adjustable Data Thresholds · Protects DTE from Spurious Data · Prevents Erroneous Transmission Through
Repeaters · Acts as a FAST Receiver Squelch, even with
RX Data Transformers as Small as 16µH. ·Low Skew
28 Pin OIL 28 PLCC
28-Pin OIL 28 PLCC 28 Pin OIL 28 Pin PLCC
28 Pin OIL 28 PLCC
8 Pin OIL
7-4
n n l::::::l_j
INTEGRATED CIRCUITS
-UNITROCE
Product Selection Guide HIGH CURRENT FET DRIVER CIRCUITS
High Speed Power Driver (Single ended)
· 1.5ATotemPole Output · High Speed MOSFET Compatible · Low Quiescent Current · Low Cost Package
Dual High Current MOSFET Compatible Output Driver
Dual Uncommitted High Current MOSFET Compatible Output Driver
· Dual, 1.5A Totem Pole Outputs · Parallel or Push-Pull Operations · Single-Ended to Push-Pull Conversion (1706 Series) · Internal Overlap Protection · Analog, Latched Shutdown · High-Speed, Power MOSFET Compatible · Thermal Shutdown Protection · 5 to 40V Operation · Low Quiescent Current
Dual Non-Inverting Power Driver
· 3.0 Peak Current Totem Pole Output · 5 to 35V Operation · 25nSec Rise and Fall Times · 25 nSec Propagation Delays · Thermal Shutdown and Under-Voltage Protection · High-Speed, Power MOSFET Compatible · Efficient High Frequency Operation · Low-Cross-Conduction Current Spike · Enable and Shutdown Functions · Wide Input Voltage Range · ESD Protection to 2kV
Dual High Speed FET Driver
· 1.5A Source/Sink Drive · Pin Compatible with 0026 · 40ns Rise and Fall into 1OOOpF · Low Quiescent Current
High CurrenVSpeed FET Driver
· 10A Peak Current Capability · 40ns Rise and Fall Times · 40ns Delay Times (1 NI) · Low Saturation Voltage
Dual Ultra High Speed FET Driver
· 25nS Rise and Fall into 1OOOpF · 15nS Propagation Delay · 1.5Amp Source or Sink Output Drive · Operation with 5V to 35V Supply · High-Speed Schottky NPN Process · 8-PIN Mini-DIP Package · Radiation Hard
8 Pin OIL 5 Pin T0-220 Power SO-IC
16 Pin OIL "Batwing"
SMD Power SO-IC
8 Pin OIL 16 Pin OIL
SMD Power SO-IC
8 Pin OIL SMD
Power SO-IC
8 Pin OIL 5 Pin T0-220 Power SO-IC
8 Pin OIL SMD
Power SO-IC
7-5
n nINTEGRATED
~CIRCUITS
- UNITROCJE
Product Selection Guide SCSI BUS BOSSTM ACTIVE TERMINATORS
18 Line SCSl-2 Active Terminator
18 Line SCSl-2 Active Terminator
9 Line SCSl-2 Active Terminator
· Trimmed Regulator for Accurate Terminated Current · Logic Command Disconnects All Terminating
Resistors · Provides Active Termination for 18 Lines · Negative Clamping On All Signal Lines · Low Supply Current in Disconnect Mode · Low Dropout Voltage Regulator · Low Thermal Resistance SMD Packages
· Provides Active Termination for 18 Lines · Engineered for High Volume Applications · 6% Trimmed Max. Termination Current · 6% Termination Impedance · Low Dropout Voltage Regulator
· Two New Power SMD Packages for 1.8 in. HOD or Cable Applications
· Provides Active Termination for 9 Lines · Trimmed to Meet SCSl-3 Specifications · Low Capacitance · 300mA Source/Sink Current · 1OOµA Supply Current in Disconnect Mode · Negative Clamping on All Signal Lines
28 Pin Pwr. PLCC 28 Pin Pwr. SO-IC
28 Pin Pwr. PLCC 28 Pin Pwr. SO-IC
16 Pin Pwr. SO-IC 16 Pin Pwr. ZIP
Note: Look for other new SCSI product accouncements. Contact your UICC Representative
7-6
n n L'.::::'.J INTEGRATED CIRCUITS
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Dual Switchmode Solenoid Driver
L295
FEATURES · High current capability (up to 2.5A per
channel)
· High voltage operation (up to 46V for power stage)
· High efficiency switchmode operation · Regulated output current (adjustable) · Few external components
· Separate logic supply
· Thermal protection
DESCRIPTION The L295 is a monolithic integrated circuit in a 15 lead MULTIWATT® package; it incorporates all the functions for direct interfacing between digital circuitry and inductive loads. The L295 is designed to accept standard microprocessor logic levels and drive 2 independent solenoids. The output current is completely controlled by means of a switching technique allowing very efficient operation. Furthermore, it includes an enable input and separate power supply inputs for bilevel operation such as interfacing with peripherals running at higher voltage levels.
The L295 is particularly suitable for applications such as hammer driving in matrix printers, step motor driving and electromagnet controllers.
ABSOLUTE MAXIMUM RATINGS
Collector Supply Voltage, Ve ............................. 50V Logic Supply Voltage, Vss ............................... 12V Enable and Input Voltage,VEN. V; .......................... 7V Reference Voltage, VREF .................................. 7V Peak Output Current (each channel)
Non·Repetitive, (t = lOOµsec), lo ........................ 3A Repetitive (80% on -20% off; toN = lOms) ............. 2.5A DC Operation .......................................... 2A Total Power Dissipation (at Tease= 75°C) ............... 25W Storage and Junction Temperature ............. -40to+150°C
THERMAL DATA
Thermal Resistance Junction·Case, 8Jc .......... 3°C/W max Thermal Resistance Junction-Ambient, 8JA ...... 35°C/W max
BLOCK DIAGRAM
+Ve
+Vss
+Ve
THERMAL SHUTDOWN
10
VOLTAGE REGULATOR
OSCILLATOR
13 R.,
-:::
12
VReF2
11
V1N2
N
V1N 1
7-7
MECHANICAL DATA VPackage
VH Package
CONNECTION DIAGRAM (TOP VIEW)
$
Tab connected lo Pin 8
L295
ELECTRICAL CHARACTERISTICS (Refer to the application circuit, Vss = 5V, Ve= 36V, T; = 25°C; unless otherwise specified, L =Low; H =High) TA=TJ
PARAMETER
SYMBOL
TEST CONDITIONS
MIN. TYP. MAX. UNITS
Supply Voltage
Ve
12
46
v
Logic Supply Voltage
Vss
4.75
10
v
Quiescent Drain Current J(from Ve)_
le
'Ve= 46V; V;1 = vi2 = VEN = L
4
mA
Quiescent Drain Current (from Vss)
lss
'Vss = lOV
46
mA
Low Input Voltage
V;1L, Vi2L
-0.3
0.8
v
High Input Voltage
V;1H, V12H
2.2
7
v
Low Enable Input Voltage
VENL
-0.3
0.8
v
High Enable Input Voltage
VENH
2.2
7
v
Input Current
l;1. 1;2
V;1 = Vi2 = L V;1 = Vi2 = H
-100 µA 10
Enable Input Current
IEN
VEN= L
VEN= H
-100 µA 10
Input Reference Voltage
VREF1. VREF2
0.2
2
v
Input Reference Current
IREF1. IREF2
-5
µA
Oscillation Frequency
Transconductance (each channel)
fosc Ip
VREF
C = 3.9nF, R = 9.lKO VREF = 1V, Rs = 0.50
25
KHz
1.9
2
2.1 A/V
Total Output Voltage Saturation
(each channel)*
Vsat
10 = 2A
2.8
3.6
v
External Sensing Resistors Voltage Drop Vsens 1, Vsens 2
2
v
*Vsat = Vcesat01 + Vcesat02·
7-8
L295
APPLICATION CIRCUIT
04 -::-
+Vss
+v_r;
O.lµF
I'
10
L295
O.lµF 470µF
I I
12 11
VREF2
m
VREF1
-::-
V1N2
V1N1
02 ::- -::-
Dl, 04 = 2A HIGH SPEED DIODES (SES5001, or equivalent)
FUNCTIONAL DESCRIPTION
The L295 incorporates two independent driver channels with separate inputs and outputs, each capable of driving an inductive load (see block diagram).
The device is controlled by three microprocessor compatible digital inputs and two analog inputs. These inputs are;
EN chip enable (digital input, active low), enables both channels when in the low state.
V1N1. V1N2 channel inputs (digital inputs, active high), enable each
channel independently. A channel is activated when both EN and the appropriate channel input are active.
VREF1. VReF 2 reference voltages (analog inputs), used to program the
peak load currents. Peak load current is proportional to VREF·
Since the two channels are identical, only channel one will be described. The following description applies equally to channel two, replacing FF2 for FFl, VREF2 for VREF1 etc. When the channel is activated by a low level on the EN input and a high level on the channel input V1N1, the output transistors Ql and Q2 switch on and current flows in the load according to the exponential law:
I= :l (1 -e -~:t )
where: Rl and L1 are the resistance and inductance of the load and V is the voltage available on the load
The current increases until the voltage on the external sensing resistor, Rs1, reaches the reference voltage, VREF1. This peak current, 1p1, is given by:
VREF1 lp1=~
At this point the comparator output, Comp 1, sets the RS flip-flop, FFl, that turns off the output transistor, Ql. The load current flowing through 02, Q2, Rs1, decreases according to the law:
where: VA = Vcesat 02 + Vsansa 1 + Vo2
If the oscillator pin (9) is connected to ground the load current falls to zero as shown in Figure 1.
At time t2, channel 1 is disabled by taking the inputs V1N1 low and/or EN high, and the output transistor Q2 is turned off. The load current flows through 02 and 01 according to the law:
I= (
Ve
)
Rl+IT2
-Rlt
eu
Ve
Rl
where:
Ve= Ve+ Vo1 + Vo2 IT2 = current value at the time t._
Figure 2 shows the current waveform obtained with an RC network connected between pin 9 and ground. From lo to t1 the current increases as in Figure 1. A difference exists at the time t2 because the current starts to increase again. At this time a pulse is produced by the oscillator circuit that resets the flip flop, FFl, and switches on the output transistor, Ql. The current increases until the drop on the sensing resistor Rs1 is equal to VREF1 (13) and the cycle repeats.
The switching frequency depends on the values of R and C, as shown in Figure 4 and must be chosen in the range 10 to 30KHz.
It is possible with external hardware to change the reference voltage VREF in order to obtain a high peak current Ip and a lower holding current lh (see Figure 3).
The L295 is provided with a thermal protection that switches off all the output transistors when the junction temperature exceeds 150°C. The presence of a hysteresis circuit makes the IC work again after a fall of the junction temperature of about 20°C.
The analog input pins (VREF1, VREF2) can be left open or connected to V88; in this case the circuit works with an internal reference voltage of about 2.5V and the peak current in the load is fixed only by the value of Rs:
2.5 Ip=~
7-9
SIGNAL WAVEFORMS
I,
to
IV; ·EN
r-VREF
· t
ON QI
OFF
:tJ'
Q2
Figure 1. Load current waveform with pin 9 connected toGND
L295
I,
,,
v, ·TIJ
1--- VREF
I
I '
I
I
;
I 0 QI :F:r---1 DD
· t
" ::/ HI · t
Figure 2. Load current waveform with external R·C network connected between pin 9 and ground
I,
lnh ON
QI
n n
OFF
II 11 1I I 1
l:I
1
I I
I, 1' - - - - 1 I
I I
'' I
GJl
10
100
R - (KCl)
R(KCl)
Figure 3. With VREf changed by hardware
Figure 4. Switching frequency vs values of R and C
Unitrode Integrated Circuits Corporation 7 Continental Boulevard. ·P.O. Box 399 ·Merrimack, New Hampshire· 03054-0399 Telephone 603-424-2410 ·FAX 603-424-3460
7-10
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High Speed Power Driver
UC1705 UC2705 UC3705
FEATURES
1.5A Source/Sink Drive
100 nsec Delay
40 nsec Rise and Fall into 1000pF
Inverting and Non-Inverting Inputs
Low Cross-Conduction Current Spike
Low Quiescent Current
5V to 40V Operation
Thermal Shutdown Protection
MINIDIP and Power Packages
TRUTH TABLE
INV
N.I
OUT
H
H
L
L
H
H
H
L
L
L
L
L
DESCRIPTION
The UC1705 family of power drivers is made with a high speed Schottky process to interface between low-level control functions and high-power switching devices - particularly power MOSFETs. These devices are also an optimum choice for capacitive line drivers where up to 1.5 amps may be switched in either direction. With both Inverting and Non-Inverting inputs available, logic signals of either polarity may be accepted, or one input can be used to gate or strobe the other.
Supply voltages for both Vs and Ve can independently range from 5V to 40V. For additional application details, see the UC1707/3707 data sheet.
The UC1705 is packaged in an 8-pin hermetically sealed CERDIP for -55°C to +125°C operation. The UC3705 is specified for a temperature range of 0°c to +70°C and is available in either a plastic minidip or a 5-pin, power T0-220 package.
CONNECTION DIAGRAMS
DIL-8 MINIDIP, SOIC-8 (TOPVIEW) Jlloor J Package, D Package
5-PIN T0-220 (TOPVIEW) T Package
OUT= INVand N.I.
OUT= INV or NJ.
LOGIC GNO
JI
PWR GNO
BLOCK DIAGRAM
N.1. INPUT INV. INPUT
THERMAL S.D.
Vs
INTERNALLY
- - - CONNECTED - -1
IN T-PACKAGE
Ve
5V LOGIC REGULATOR
OUT
PWR
INTERNALLY
GND
- - - CONNECTED - - _J
LOGIC GND IN T-PACKAGE
7-11
UC1705 UC2705 UC3705
ABSOLUTE MAXIMUM RATINGS
N·Pkg
J.Pkg
T·Pkg
Supply Voltage, VIN · . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40V. . . . . . . . . . . . . . . . . . . 40V .........·......... 40V
Collector Supply Voltage, Ve ......................... 40V.................·. 40V ................... 40V
Output Current (Source or Sink)
Steady-State ....... , ....................... ,. ±500mA................ ±500mA................. ±1.0A
Peak Transient..·............................... :t1.5A.................. ±1.0A.................. ±2.0A
Capacitive Discharge Energy ...................... 2011-1 . .. .. . . .. .. .. .. .. . 1511-1 .. .. .. . . . . .. . . . . . . 5011-1
Digital Inputs (See Note) ............................ 5.5V . . . . . . . . . . . . . . . . . . 5.5V . . . . . . . . · . . . . . . . . . 5.5V
PowerDissipationatTA,,25°C(SeeNote) ............... 1W.................... 1W.................... 3W
Power Dissipation atTA (Leads/Case)= 25°C (See Note) ... 3W.................... 2W..........·........ 25W
Operating Temperature Range .................... 0°Cto +70°C .......... -55°Cto +125°C .......... 0°C to +70°C
Storage Temperature Range . . . . . . . . . . . . . . . . . . . . -65°C to +150°C . . . . . . . . -65°C to +150°C ......... -65°C to +150°C
Lead Temperature (Soldering, 10 seconds)............. aoo·c .................. aoo·c ................. aoo·c
Note: All currents are positive into, negative out of the specified terminal.
Digital Drive can exceed 5.5V if input current is limited to 1OmA
Consult Packaging Section ofDatabook for thermal limitations and considerations ofpackage.
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA= -55°C to+125·c for the
UC1705, -25°C to +85°C for the UC2705, and o·c to +70°C for the UC3705; Vs = Ve = 20V, TA= TJ.
PARAMETERS Vs Supply Current
Ve Sl.!l>l>IY_CurrentJN J Only}_ Ve Leak1!9..e CurrenU.N J Only}_
D.!gital 11}1!,ut Low Level D.!gital 11}1!,ut H.!g_h Level Il!Q_ut Current lr:!Q_ut Leak~e Output High Sat., Ve-Vo
Output Low Sat., Vo
Thermal Shutdown
TEST CONDITIONS Vs = 40V J..01!!1!._uts H.!g_h T Plgj)_ Vs= 40V J..01!!1!.,uts Low T P~ Ve = 40V 01.Jti11!.ts Low Vs=O Vc=30V
V1=0 Vi=5V lo= -50mA IO= -500mA lo=50mA lo=500mA
MIN TYP MAX UNITS
6
8
mA
8
12 mA
2
4
mA
.05 0.1 mA
0.8
v
2.2
v
-0.6 -1.0 mA
0.5 0.1 mA
2.0 v
2.5 v
0.4 v
2.5 v
155
·c
TYPICAL SWITCHING CHARACTERISTICS: Vs= Ve = 2ov, TA= 25"C. Delays measured to 10% output change.
PARAMETERS From Inv. ll!Q.ut to O~ut:
Rise Time Delll'l_ 10% to 90% Rise Fall Time Delll\l_
90% to 10% Fall From N. I. lr:!Q.ut to O~ut:
Rise nme Del~ 10% to 90% Rise Fall Time Delll\l_
90% to 10% Fall
Ve Cross-Conduction Current Spike Duration
TEST CONDITIONS
01.!I!..utRise Output Fall
OUTPUT CL=
~en 1.0
2.2
60 60 60
20
40
60
60
60
60
25 40 50
1 UNIT nF ns ns ns ns
90
90
90
ns
20
40
60
ns
60
60
60
ns
25 40 50 ns
25
ns
0
ns
7-12
APPLICATIONS Power MOSFET Drive Circuit
UC1705 UC2705 UC3705
Power MOSFET Drive Circuit using Negative Bias Voltage and Level Shifting to Ground Referenced PWMs.
Drive Input from PWM
Vz-VEE
>-:i
D1, D2: UC3611 Schottky Diodes
(VEE)
Negative Blas (-5 TO -10V)
D1, D2: UC3611 Schottky Diodes
Transformer Coupled MOSFET Drive Circuit
Charge Pump Circuits
1nFT1oµF
To Load
D1, D2: UC3611 Schottky Diodes
,...--,1------- Ve Vo=-Vf!I
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. · !.ERRIMACK NH 03054 TEL. (603 424-2410 · FAX (603) 424-3460
7-13
n n INTEGRATEC
~CIRCUITS
-UNITRODE
Dual Output Driver
(®) UC1706 UC2706 UC3706
FEATURES Dual, 1.5A Totem Pole Outputs 40nsec Rise and Fall into 1OOOpF Parallel or Push-Pull Operation Single-Ended to Push-Pull Conversion High-Speed, Power MOSFET Compatible Low Cross-Conduction Current Spike Analog, Latched Shutdown Internal Deadband Inhibit Circuit Low Quiescent Current
DESCRIPTION The UC1706 family of output drivers are made with a high-speed Schottky process to interface between low-level control functions and highpower switching devices - particularly power MOSFET's. These devices implement three generalized functions as outlined below.
First: They accept a single-ended, low-current digital input of either polarity and process it to activate a pair of high-current, totem pole outputs which can source or sink up to 1.5A each.
Second: They provide an optional single-ended to push-pull conversion through the use of an internal flip-flop driven by double-pulse-suppression logic. With the flip-flop disabled, the outputs work in parallel for 3.0A capability.
Third: Protection functions are also included for pulse-by-pulse current limiting, automatic deadband control, and thermal shutdown.
5 to 40V Operation Thermal Shutdown Protection 16-Pin Dual-In-Line Package
These devices are available in a two-watt plastic "bat-wing" DIP for operation over a 0°c to 70°C temperature range and, with reduced power, in a hermetically sealed cerdip for -55°C to +125°C operation. Also available in surface mount Q and L packages.
20-Pin Surface Mount Package
TRUTH TABLE
INV
N.I
H
H
L
H
H
L
L
L
OUT
OUT= INV and N.I.
L
OUT= INV or NT
H
L
L
BLOCK DIAGRAM
INVERTING INPUT
NON-IN1~~ni 3
+VIN
·SET DOMINANT 7-14
GROUND 4,5,12,13
ABSOLUTE MAXIMUM RATINGS
N-Pkg
J-Pkg
Supply Voltage, VIN ........................... 40V...................... 40V
Collector Supply Voltage, Ve . . . . . . . . . . . . . . . . . . . . 40V ...................... 40V
Output Current (Each Output, Source or Sink)
Steady-State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±500mA . . . . . . . . . . . . . . . . ±500mA
Peak Transient . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1.5A ................... ±1.0A
Capacitive Discharge Energy .................. 20µJ . . . . . . . . . . . . . . . . . . . . 15µJ
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V . . . . . . . . . . . . . . . . . . . . 5.5V
Analog Stop Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . VIN . . . . . . . . . . . . . . . . . . . . . . VIN
Power Dissipation at TA= 25°C (See Note) ......... 2W ...................... 1W
Power Dissipation at T (Leads/Case) = 25°C (See NoteJillll. . . . . . . . . . . . . . . . . . . . . . 2W
Operating Temperature Range .......................... -55°C to +125°C ...... .
Storage Temperature Range ............................ -65°C to +150°C ...... .
Lead Temperature (Soldering, 10 Seconds) .................... 300°C .......... .
Note: All voltages are with respect to the four ground pins which must be connected together. All currents are positive into, negative out of the specified terminal. Consult Packaging section of Databook for thermal limitations and considerations ofpackage.
UC1706 UC2706 UC3706
CONNECTION DIAGRAMS
DIL-16, SOIC-16 (TOPVIEW)
J or N Package, OW Package
~~ B INHIBIT
A INHIBIT
INV. INPUT ~
~ INHIBIT REF
N.I. INPUT~
~VIN
GROUND~
~ GROUND
GROUND (!
~GROUND
A OUTPUT @:
~ B OUTPUT
FLIP/FLOP [f
~ STOP NON-INV.
Ve @:
tID STOP INV.
Note: All four ground pins must be connected to a common ground.
PLCC-20, LCC-20 (TOPVIEW) Q, L Packages
L3 2 1 2019
4
18
5
17
6
16
7
15
8
14
9 10 11 12 13
PACKAGE PIN FUNCTION
FUNCTION
PIN
~c
1
B INHIBIT
2
INV INPUT
3
N.l. INPUT
4
GROUND
5
A OUTPUT
6
FLl~LOP
7
Ve
8
~c
9
STOP INV.
10
STOP NON-INV. 11
BOUTPUT
12
GROUND
13
Nl_C
14
GROUND
15
~c
16
GROUND
17
VIN
18
INHIBIT REF
19
A INHIBIT
20
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA= -55°C to+125°C for the
UC1706, -25°C to +85°C for the UC2706 and 0°C to +70°C for the UC3706; VIN=
- Ve - 20V TA - TJ
PARAMETERS
TEST CONDITIONS
MIN
TYP
MAX
UNITS
VIN S~Current
VIN=40V
8
10
mA
Ve S~Current
Ve = 40V, Ou!e._uts Low
4
5
mA
Ve Leakage Current D.!g!tal lllQ_ut Low Level D.!g!tal lllQ_ut High Level
VIN = 0, Ve = 30V, No Load
.05
0.1
mA
0.8
v
2.2
v
l11Q_ut Current
VI= 0
-0.6
-1.0
mA
IllQ_ut Leak<!9_e Output High Sat., Ve-Vo
V1=5V lo= -50mA lo= -500mA
.05
0.1
mA
2.0
v
2.5
v
7-15
UC1706
UC2706
UC3706
ELECTRICAL
Unless otherwise stated, these specifications apply for TA = -55°C to +125°C for the
CHARACTERISTICS (cont.): UC1706, -25°C to +85°C for the UC2706 and o·c to +70°C for the UC3706; VIN =Ve = 2CN.
TA=TJ.
· PARAMElERS Output Low Sat, Vo
Inhibit Threshold
TEST CONDmONS lo=50mA lo=500mA VREF=0.5V VREF=3.5V
MIN TVP MAX UNl1S
0.4 v
2.5 v
0.4
0.6 v
3.3
3.7 v
Inhibit l~ut Current Anal~Threshokl
VREF=O VCM=Oto 15V
-10 -20 ~ 100 130 150 mV
lnJllll Bias Current Thermal Shutdown
VcM=O
-10 -20 !AA
155
·c
TYPICAL SWITCHING CHARACTERISTICS: V1N =Ve= 20V, TA= 25°C. Delays measured to 10% output change.
PARAMElERS
TEST CONDITIONS
From Inv. 11!2,ut to Out_.e_ut:
Rise Time Del~
10% to 90% Rise
Fall Time Del~
90% to 10% Fall
From N. I. 11!2,ut to Out_.e_ut:
Rise Time Del~
10% to 90% Rise
Fall Time Del~
90% to 10% Fall
Ve Cross-Conduction Current Spike Duration Ol!!ll_utRise
Ol!!ll_utFall
Inhibit De!!l_
Inhibit Ref.= 1V Inhibit Inv.= 0.5 to 1.5V
Analog_Shutdown Del~
S!<>Q._Non-lnv. = OV, Stqp_lnv. =Oto 0.5V
OUTPUT CL= <lE!_n 1.0 2.2 110 130 140 20 40 60 80 90 110 25 30 50
UNIT nF ns ns ns ns
120 130 140 ns
20 40 60 ns
100 120 130 ns
25 30 50 ns
25
ns
0
ns
250
ns
180
ns
CIRCUIT DESCRIPTION Outputs The totem-pole outputs have been designed to minimize cross-conduction current spikes while maximizing fast, high-current rise and fall times. Current limiting can be done externally either at the outputs or at the common Ve pin. The output diodes included have slow recovery and should be shunted with high-speed external diodes when driving high-frequency inductive loads.
Flip/Flop Grounding pin 7 activates the internal flip-flop to alternate the two outputs. With pin 7 open, the two outputs operate simultaneously and can be paralleled for higher current operation. Since the flip-flop is triggered by the digital input, an off-time of at last 200nsec must be provided to allow the flip/flop to change states. Note that the circuit logic is configured such that the "OFF" state is defined as the outputs low.
Digital Inputs With both an inverting and non-inverting input available, either active-high or active-low signals may be accepted. These are true TTL compatible inputs--the threshold is
approximately 1.2V with no hysteresis; and external pullup resistors are not required.
Inhibit Circuit Although it may have other uses, this circuit is included to eliminate the need for deadband control when driving relatively slow bipolar power transistors. A diode from each inhibit input to the opposite power switch collector will keep one output from turning-on until the other has turned-off. The threshold is determined by the voltage on pin 15 which can be set from 0.5 to 3.SV. When this circuit is not used, ground pin 15 and leave 1 and 16 open.
Analog Shutdown This circuit is included to get a latched shutdown as close to the outputs as possible, from a time standpoint. With an internal 130mV threshold, this comparator has a common-mode range from ground to {VIN - 3V). When not used, both inputs should be grounded. The time required for this circuit to latch is inversely proportional to the amount of overdrive but reaches a minimum of 180nsec. As with the flip-flop, an input off-time of at least 200nsec is required to reset the latch between pulses.
7-16
CIRCUIT DESCRIPTION (cont.) Supply Voltage With an internal 5V regulator, this circuit is optimized for use with a 7 to 40V supply; however, with some slight response time degradation, it can also be driven from 5V. When VIN is low, the entire circuit is disabled and no current is drawn from Ve. When combined with a UC1840 PWM, the Driver Bias switch can be used to supply VIN
UC1706 UC2706 UC3706
to the UC1706. VIN switching should be fast as if Ve is high, undefined operation of the outputs may occur with VIN less than 5V.
Thermal Considerations Should the chip temperature reach approximately 155°C, a parallel, non-inverting input is activated driving both outputs to the low state.
APPLICATIONS Power MOSFET Drive Circuit
Power MOSFET Drive Circuit Using Negative Bias Voltage and Level Shifting to Ground Referenced PWMs.
Drive Input lrom PWM >--'V'\/V-.
VZ·VEE
~
(VEE)
Negative Bias
(-5 TO -10V)
D1, D2: UC3611 Schottky Diodes
D1, D2: UC3611 Schottky Diodes
Transformer Coupled MOSFET Drive Circuit
Charge Pump Circuits
1nfy10µF
To
Load
+ 100µF
D1, D2: UC3611 Schottky Diodes 7-17
01 t-;Hlf-1~Cl-...-Vo ·-Ve
02 - 100µF +
APPLICATIONS (cont'd) Power Bipolar Drive Circuit
Ve
1nFy10µF 01
UC1706 UC2706 UC3706
Transformer Coupled Push-Pull MOSFET Drive Circuit Ve
D1, D2: UC3611 Schottky Diodes
PGND U~3611 Quad Schottky Diode Array
D1, D2: UC3611 Schottky Diodes
UC3706 Converts Single Output PWMs to High Current Push-Pull Configuration
14
Driver Bias
14 UC3706
OUT 12
UC3840 Or
UC3841
GND 13
1µF
I
I
I
I
L
_J
\
UC3611 Quad Schottky Diode Array
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. · '-ERRIMACK, NH · 03054 TEL. (603) 424-2410 · FAX(603) 424-3460
7-18
n nINTEGRATED
~CIRCUITS
-UNITROCE
Dual Channel Power Driver
UC1707 UC2707 UC3707
FEATURES Two Independent Drivers 1.5A Totem Pole Outputs Inverting and Non-Inverting Inputs 40ns Rise and Fall into 1OOOpF High-Speed, Power MOSFET Compatible Low Cross-Conduction Current Spike Analog Shutdown with Optional Latch Low Quiescent Current 5V to 40V Operation Thermal Shutdown Protection 16-Pin Dual-In-Line Package 20-Pin PLCC and CLCC Package
BLOCK DIAGRAM
DESCRIPTION The UC1707 family of power drivers is made with a high-speed Schottky process to interface between low-level control functions and high-power switching devices - particularly power MOSFETs. These devices contain two independent channels, each of which can be activated by either a high or low input logic level signal. Each output can source or sink up to 1.5A as long as power dissipation limits are not exceeded.
Although each output can be activated independently with its own inputs, it can be forced low in common through the action either of a digital high signal at the Shutdown terminal or a differential low-level analog signal. The Shutdown command from either source can either be latching or not, depending on the status of the Latch Disable pin.
Supply voltage for both VIN and Ve can independently range from 5V to 40V.
These devices are available in two-watt plastic "bat-wing" DIP for opera-
tion over a 0°C to 70°C temperature range and, with reduced power, in a
hermetically sealed cerdip for -55°C to +125°C operation. Also available
in surface mount OW, a, L packages.
TRUTH TABLE {Each Channel)
INV.
N.I
OUT
H
H
L
L
H
H
H
L
L
L
L
L
OUT= INV and N.I. OUT= JNVor N.I.
INPUT A N.I.
INPUT A INVERT
INPUT B N.I.
l~~~JR~ 1 1 - - - - - - '
+VIN
5/93
s~-~
A SHUTDOWN 7 1 - - - - - - - '
Dl~'j.1\'.~ 3 1--H_·_No_LA_T_c_H_o_R_R_E_s_ET_~
L · LATCH ENABLED
7-19
ABSOLUTE MAXIMUM RATINGS
N-Pkg
J-Pkg
Supply Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40V. . . . . . . . . . . . . . . . . . . . 40V
Collector Supply Voltage, Ve . . . . . . . . . . . . . . . . . . . . . . . . . 40V. . . . . . . . . . . . . . . . . . . . 40V
Output Current (Each Output, Source or Sink)
Steady-State .................................. ±500mA............... ±500mA
Peak Transient .................................. ±1.5A .................. ±1.0A
Capacitive Discharge Energy. . . . . . . . . . . . . . . . . . . . . . . 20µJ . . . . . . . . . . . . . . . . . . 15µJ
Digital Inputs (See Note) ............................ 5.5V ................... 5.5V
Analog Stop Inputs .................................. VIN ..................... VIN
Power Dissipation at TA= 25°C (See Note) ............... 2W ..................... 1W
Power Dissipation at T (Leads/Case) = 25°C (See Note) .... 5W ......................2W
Operating Temperature Range .............................. -55°C to +125°C ..... .
Storage Temperature Range ................................ -65°C to +150°C..... .
Lead Temperature (Soldering, 10 Seconds) ........................ 300°C ......... .
Note: All voltages are with respect to the four ground pins which must be connected together. All currents are positive into, negative out of the specified terminal. Digital Drive can exceed 5.5Vif input current is limited to 10mA. Consult Packaging section of Databook for thermal limitations and considerations ofpackage.
UC1707 UC2707 UC3707
CONNECTION DIAGRAMS
DIL-16, SOIC-16 {TOPVIEW)
J or N Package, OW Package
rr-~ INPUT B INV.
INPUT A INV.
INPUT B N.1. [[j
!!ID INPUT A N.I.
LATCH @1
DISABLE 3
GROUND [!j
~+VIN ~GROUND
GROUND r?:1
OUTPUT A ~
~GROUND
till OUTPUT B
SHUTDOWN [1j
+Ve~
~ANALOG
lfil STOP NON-INV. SATNOAPLOIGNV.
Note: All four ground pins must be connected to a common ground.
PLCC-20, LCC-20 {TOPVIEW) Q, L Packages
L 3~~~~~ 2 1 201s
4
18~
5
17~
6
16~
7
15~
8
14~
9 10 11 12 13
~~~~~
PACKAGE PIN FUNCTION
FUNCTION
PIN
llli.C
1
INPUTB INV.
2
INPUTB N.I.
3
LATCH DISABLE
4
GROUND
5
f\!Lc
6
GROUND
7
OUTPUT A
8
SHUTDOWN
9
Ve
10
llli.C
11
ANALOG STOP INV.
12
ANALOG STOP NON INV. 13
OUTPUTS
14
GROUND
15
llli.C
16
GROUND
17
VIN
18
INPUT A NON INV.
19
INPUTAINV.
20
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA= -55°C to +125°C for the
UC1707, -25°C to +85°C for the UC2707 and 0°c to +70°C for the UC3707; VIN= Ve= 20V. TA= TJ.
PARAMETERS VIN S~Current Ve Supply Current Ve Leak~e Current D_ig_ital l~ut Low Level D.!g!tal lf!Q_ut H.!ll_h Level l~ut Current lf!Q_ut Leak~e Output High Sat., Ve-Vo
TEST CONDITIONS VIN= 40V Ve = 40V, Ol!!E_uts Low VIN = 0, Ve = 30V, No Load
V1=0 V1=5V lo= -50mA lo =-500mA
MIN
TVP
MAX
UNITS
12
15
mA
5.2
7.5
mA
.05
0.1
mA
0.8
v
2.2
v
-0.6
-1.0
mA
.05
0.1
mA
2.0
v
2.5
v
7-20
ELECTRICAL CHARACTERISTICS (cont.):
PARAMETERS Output Low Sat., Vo
Analog Threshold Input Bias Current Thermal Shutdown Shutdown Threshold Latch Disable Threshold
UC1707 UC2707 UC3707
Unless otherwise stated, these specifications apply for TA= -55°C to +125°C for the UC1707, -25°C to +85°C for the UC2707 and 0°C to +70°C for the UC3707; VIN= Ve= 20V. TA=TJ.
TEST CONDITIONS lo=50mA lo= 500mA
MIN TVP MAX UNITS
0.4 v 2.5 v
VeM= Oto 15V
100 130 150 mV
VeM=O
Pin 7 ll!E_Ut Pin 3 Input
-10 -20 µA
155
oc
0.4 1.0 2.2
v
0.8 1.2 2.2
v
TYPICAL SWITCHING CHARACTERISTICS: V1N =Ve= 20V, TA= 25°C. Delays measured to 10% output change.
PARAMETERS From Inv. IQE.ut to Ou!E_ut:
Rise Time Del~ 10% to 90% Rise Fall Time Del~ 90% to 10% Fall From N. I. lnj>_ut to Ou!Q._ut: Rise Time Del~ 10% to 90% Rise Fall Time Del~ 90%to10%Fall Ve Cross-Conduction Current Spike Duration
Analog Shutdown Delay
D!.g!tal Shutdown Delay
TEST CONDITIONS
O~utRise
Output Fall Stop Non-Inv. = OV St~lnv. =Oto 0.5V 2V lri.e._4ton Pin 7
OUTPUTCL.=
~en 1.0 2.2
40
50
60
25
40
50
30
40
50
25
40
50
I UNIT nF ns ns ns ns
30
40
50
ns
25
40
50
ns
45
55
65
ns
25
40
50
ns
25
ns
0
ns
180
ns
50
ns
SIMPLIFIED INTERNAL CIRCUITRY Typical Digital Input Gate
Internal 5 Volts
Analog Shutdown Comparator Circuit +VIN
The input zener may be used to clamp input signal voltages higher than 5V as long as the zener current is limited to 10mA max. External pull-up resistors are not required.
The input common-mode voltage range is from ground to (V1N-3V). When not used both inputs should be grounded. Activate time is a function of overdrive with a typical value of 180ns. Pin 7 serves both as a comparator output and as a common digital shutdown input. A high signal here will accomplish the fastest tum off of both outputs. Note that "OFF" is defined as the outputs low. Pulling shutdown low defeats the latch operation regardless of its status.
7-21
SIMPLIFIED INTERNAL CIRCUITRY (continued) Latch Disable
The Shutdown latch is disabled when pin 3 is open. An impedance of 4k or less from pin 3 to ground will allow a shutdown signal to set the latch which can then be reset by either recycling the VIN supply or by momentarily (>200ns) raising pin 3 high.
INT SV
LATCH DISABLE
Transformer Coupled Push-pull MOSFET Drive Circuit Ve
UC1707 UC2707 UC3707
To Shutdown Latch
Current Limiting
UC3611 Quad Schottky Diode Array
The Analog shutdown can give pulse-by-pulse current limiting with a reset pulse from the clock output of the UC1524. R1 C1 is used to filter leading edge spikes.
7-22
APPLICATIONS (continued)
Over-Voltage Protection
5.6V OVP
Reset
UC1707 UC2707 UC3707
Charge Pump Circuits ~1---+---- Ve
+-r-~r+'-+-;_>1-.,...-vo~2vc
20µF
+ 100µF
With an external reference, the shutdown comparator can be used for over-voltage protection. R1 and R2 set the shutdown level while R3 adds positive feedback for hysteresis.
When driven with a TTL square wave drive, the low output impedance of the UC1707 allows ready implementation of charge pump voltage converters.
OUTPUT STAGE COUPLING Power MOSFET Drive Circuit
Power Bipolar Drive Circuit
1nFT10µF
D1, D2: UC3611 Schottky Diodes
GND D1, D2: UC3611 Schottky Diodes
7-23
TRANSFORMER COUPLING Transformer Coupled MOSFET Drive Circuit
Ve 1nFy10µF
To Load
UC1707 UC2707 UC3707
D1, D2: UC3611 Schottly Diodes
Power MOSFET Drive Circuit Using Negative Bias Voltage and Level Shifting To Ground Reference PWM
Drive Input from PWM
VZ=VEE
>-=i_
(VEE) Negative Bias
(-5 TO -10V)
D1, D2: UC3611 Schottky Diodes
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD.· t.ERRIMAC~ NH 03054 TEL (603) 424-2410 ·.FAX (803) 424-3'1SO
7-24
n n L:::::_j
INTEGRATED CIRCUITS
-UNITRCDE
Dual Non-Inverting Power Driver
(~)
UC1708 UC3708
FEATURES 3.0A Peak Current Totem Pole Output
5 to 35V Operation 25ns Rise and Fall Times
25ns Propagation Delays Thermal Shutdown and UnderVoltage Protection High-Speed, Power MOSFET Compatible Efficient High Frequency Operation Low Cross-Conduction Current Spike Enable and Shutdown Functions Wide Input Voltage Range
ESD Protection to 2kV
DESCRIPTION
The UC1708 family of power drivers is made with a high-speed, highvoltage, Schottky process to interface control functions and high-power switching devices - particularly power MOSFETs. Operating over a 5 to 35 volt supply range, these devices contain two independent channels. The A and B inputs are compatible with TTL and CMOS logic families, but can withstand input voltages as high as VIN. Each output can source or sink up to 3A as long as power dissipation limits are not exceeded.
Although each output can be activated independently with its own inputs, they can be forced low in common through the action of either a digital high signal at the Shutdown terminal or by forcing the Enable terminal low. The Shutdown terminal will only force the outputs low, it will not effect the behavior of the rest of the device. The Enable terminal effectively places the device in under-voltage lockout, reducing power consumption by as much as 90%. During under-voltage and disable (Enable terminal forced low) conditions, the outputs are held in a self-biasing, low-voltage, state.
These devices are available in plastic 8-pin MINIDIP and 16-pin "batwing" DIP packages for operation over a 0°C to +70°C temperature range. For operation over a -55°C to +125°C temperature range, the device is available in hermetically sealed 8-pin MINIDIP and 16 pin DIP packages. Surface mount devices are also available.
BLOCK DIAGRAM
Shutdown
Note: Shutdown feature available only in JE, NE or DWpackages. 12/92
7-25
UDG·92024
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage VIN ................................ 35V Output Current (Each Output, Source or Sink)
Steady-State.................................. 0.5A Peak Transient. ................................. 3A Ouput Voltage ....................... -0.3 to {VIN + 0.3)V Enable and Shutdown Inputs .................. -0.3 to 6.2V A and B Inputs ....................... -0.3 to {VIN + 0.3)V Operating Junction Temperature (Note 2) ............. 150° Storage Temperature Range ................ -65° to 150°C Lead Temperature (Soldering, 10 Seconds) .......... 300°C
NOTE 1: All voltages are with respect to Logic Gnd pin. All currents are positive into, negative out of, device terminals. NOTE 2: Consult Unitrode Integrated Circuits databook for information regarding thermal specifications and limitations of packages.
SOIC-16 (Top View) OW Package
CONNECTION DIAGRAMS
DIL-8 (Top View) J Or N Package
UC1708 UC3708
DIL-16 (Top View) JE or NE Package
Logic Gnd 4 Logic Gnd s
Note: In JE package Pin 4 is logic ground. Pins 5, 12, and 13 are N/C.
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, V1N=10V to 35V, and these specifications apply for:
-55°C<TA<125°C for the UC1708 and o°C<TA<70°C for the UC3708. TA= TJ.
PARAMETER VIN Supply Current
A, Band Shutdown Inputs Low Level A, Band Shutdown Inputs High Level A, B Input Current Low A, B Input Current High A, B Input Leakage Current High Shutdown Input Current Low Shutdown Input Current High
Outputs Low Outputs High Enable =OV
TEST CONDITIONS
VA,B= 0.4V VA,B=2.4V VA,B= 35.3V VSHUTDOWN = 0.4V VSHUTDOWN = 2.4V VsHuroowN = 6.2V
MIN TYP MAX UNITS
18
26 mA
14
18 mA
1
4
mA
0.8 v
2.0
v
-1
-0.6
mA
-200
50 µA
200 µA
20 100 µA
170 500 µA
0.6 1.5 mA
7-26
UC1708 UC3708
ELECTRICAL CHARACTERISTICS (cont.):
Unless otherwise stated, V1N = 1OV to 35V, and these specifications apply for: --55°C<TA<125°Cfor the UC1708 and 0°C<TA<70°C for the UC3708. TA= TJ.
PARAMETER Enable Input Current Low Enable Input Current High Enable Threshold Rising Enable Threshold Falling Output High Sat., VIN - VOUT
Output Low Sat., VouT
Thermal Shutdown
VENABLE= OV VENABLE = 6.2V
TEST CONDITIONS
!OUT= -50mA !OUT= -500mA IOUT=50mA IOUT = 500mA
MIN TYP MAX UNITS
-600 -460 200 µA
200 µA
2.8 3.6
v
2.4 3.4
v
2.0 v
2.5 v
0.4 v
2.5 v
155
oc
SWITCHING CHARACTERISTICS (Figure 1)
(VIN = 20V, delays measured to 10% output change.)
PARAMETER From A,B Input to Output:
Rise Time Delay (TPLH)
10% to 90% Rise (TTLH)
Fall Time Delay (TPHL)
90% to 10% Fall (TTHL)
From Shutdown Input to Output Rise Time Delay (TPLH)
10% to 90% Rise (TTLH)
Fall Time Delay (TPHL)
90% to 10% Fall (TTHL)
Total Supply Current
TEST CONDITIONS
MIN
CL= OpF CL = 1OOOpF (Note 3) CL=2200pF CL= OpF CL = 1OOOpF (Note 3) CL=2200pF CL= OpF CL = 1OOOpF (Note 3) CL=2200pF CL=OpF CL= 1000pF (Note 3) CL=2200pF
CL= OpF CL = 1OOOpF (Note 3) CL= 2200pF CL= Opf CL = 1OOOpF (Note 3) CL=2200pF CL= OpF CL= 1000pF (Note 3) CL=2200pF CL= OpF CL= 1000pF (Note 3) CL=2200pF F = 200kHz, 500,4, duty cycle, both channels; CL= OpF F = 200kHz, 50% duty cycle, both channels; CL= 2200pF
TYP MAX UNITS
25
40
ns
25
40
ns
30
45
ns
55
75
ns
25
50
ns
40
55
ns
25 40 ns
25
45
ns
35
50
ns
15
20
ns
25 50 ns
40 55 ns
25
75
ns
30
65
ns
35
70
ns
50 75 ns
25 50 ns
40 55 ns
25
45
ns
30 50 ns
35
55
ns
25 60 ns
25 50 ns
40 55 ns
23
25 mA
38 45 mA
NOTE 3: These parameters, specified at 1OOOpF, although guaranteed over recommended operating conditions, are not tested in production.
7-27
Figure 1: AC Test Circuit and Switching lime Waveforms
UC1708 UC3708
20V
12V
_ l~PF
UC1708
AC lnputG----Ju.:6;.6:;.6=..:0'---+---1 ~>-WH,._-+--t >--l-....--{
J"l.....J 200kHz
tn:0.5VIRS""'"
tf~0.5/RS
Duty Cycle - 50%
Loglo Gnd
Output
4.3V-
INPUT
50%
ov
2fN 90%
OUTPUT
ov
1°"'
TPLH TTLH
TI\!L TTHL
90%
1°"-
UOG-92028
Figure 2: Equivalent Input Circuits
5 . e v - - - - - - - -. .
To MB Output
Enable
Note: Shutdown feature available only in JE, NE or DW Packages.
To A/B Output
UDG-92025
UNITRDDE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. · MERRIMACK, NH 03054 TEL. (603) 424-2410 · FAX (603) 424-3480
7-28
n n INTEIJRATEC
~CIRCUITS
-UNITRDDE
UC1709 UC3709
Dual High-Speed FET Driver
FEATURES 1.5 Amp Source/Sink Drive Pin Compatible with 0026 Products 40 ns Rise and Fall into 1000 pF Low Quiescent Current 5V to 40V Operation Thermal Protection
DESCRIPTION
The UC1709 family of power drivers is an effective low-cost solution to the problem of providing fast turn-on and off for the capacitive gates of power MOSFETs. Made with a high-speed Schottky process, these devices will provide up to 1.5 amps of either source or sink current from a totem-pole output stage configured for minimal cross-conduction current spike.
The UC1709 (3709) is pin compatible with the MMH0026 or DS0026, and while the delay times are longer, the supply current is much less than these older devices.
With inverting logic, these units feature complete TTL compatibility at the inputs with an output stage that can swing over 30V. This design also includes thermal shutdown protection and an under-voltage lockout circuit.
ABSOLUTE MAXIMUM RATINGS
N-Pkg
J-Pkg
Supply Voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . 40V . . . . . . . . . . . . . . . . . . . . . . . . 40V
Output Current (Source or Sink)
Steady-State .............................. ±500 ...................... ±500 mA
Peak Transient. ............................ ±1.5A. ...................... ±1.0A
Capacitive Discharge Energy ................. 20 µ.). . . . . . . . . . . . . . . . . . . . . . . 15 µ.)
Digital Inputs (See Note) ....................... 5.5V ........................ 5.5V
Power Dissipation at TA= 25°C ................... 1W.......................... 1W
Power Dissipation at Te = 25°C ................... 3W.......................... 2W
Operating Temperature Range ............. -55°C to +125°C . . . .... -55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . . . . -65°C to +150°C . . . . . . . . . -65°C to +150°C
Lead Temperature (Soldering, 10 Seconds) ....... 300°C ..................... 300 °c
Note: All currents are positive into, negative out of the specified terminals. Digital drive can
exceed 5.5V if input current is limited to 1OmA. Consult Packaging section of Databook
for thermal limitations and considerations ofpackage.
SIMPLIFIED SCHEMATIC (Only One Driver Shown)
Vee
5 Volt Regulator
UV
Sense
Thermal Sense
Input A or B
5.6V
5/93 7-29
Output A or B
Ground
CONNECTION DIAGRAMS 8 PIN OIL (TOP VIEW) N or J Package
SOIC-16 (TOP VIEW) DW Package
N/C OUTPUT A 4
N/C INPUT A
N/C GROUND
UC1709 UC3709
PLCC-20, LCC-20 (TOP VIEW) Q, L Packages
PACKAGE PIN FUNCTION
FUNCTION
PIN
N/C
1
N/C
2
INPUT A
3
L 3 2 1 2019
N/C
4
18
N/C
5
GROUND
6
17
N/C
7
16
N/C
8
15
INPUTS
9
14 9 10 11 12 13
N/C
10
N/C
11
OUTPUTS
12
N/C
13
N/C
14
B
N/C
15
Vee
16
B
N/C
17
N/C
18
N/C
19
OUTPUT A
20
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA = -55°C to +125°C for the
UC1709 and o·c to +70°C tor the UC3709; Vee= 2ov, TA= TJ.
PARAMETERS Supply Current
LQS!c O l~tVoltaJI.e LQgic 1 l~t VoltaJI.e l!!P._ut Current
l~tLeak~e
Output High Sat., Vee-Vo
Output Low Sat., Vo
Thermal Shutdown
TEST CONDITIONS Both Outi>_uts H!g!l Both Outi>_uts Low
Vi=O V1=5V lo= -50mA lo= -500mA lo=50mA lo=500mA
MIN TYP MAX UNITS
10 12 mA
7
10 mA
0.8 v
2.2
v
-0.6 -1.0 mA
0.05 0.1 mA
1.5 2.0 v
2.0 2.5 v
0.1 0.4 v
2.0 2.5 v
155
·c
TYPICAL SWITCHING CHARACTERISTICS: Vee= 20V, TA= 25°C. Delays measured to 10% output change.
PARAMETERS
TEST CONDITIONS
Rise Time Del~ 10% to 90% Rise Fall Time Del~ 90%to 10% Fall Vee Cross-Conduction Current Spike Duration
Outi>_ut Rise Output Fall
Note: Refer to UC1705 specifications for further information
OUlPUTCL=
Onf 2.2nf
80
80
20
40
60
80
20
40
25
0
UNIT
ns ns
ns
ns ns ns
7-30
APPLICATIONS Power Bipolar Drive Circuit
Ve
1nFy10µF 01
UC1709 UC3709 Transformer Coupled Push-Pull MOSFET Drive Circuit
Ve
1µF
D1, D2: UC3611 Schottky Diodes Power MOSFET Drive Circuit
UC3811 Quad Schottky Diode Array
D1, D2: UC3611 Schottky Diodes
Power MOSFET Drive Circuit Using Negative Bias Voltage and Level Shifting To Ground Referenced PWMS
Drive Input from PWM
Vz-Vee
>:i_
D1, D2: UC3611 Schottky Diodes Charge Pump Circuits
(Vee) Negative Blas
(-5 TO -10V)
D1, D2: UC3611 Schottky Diodes
Transformer Coupled MOSFET Drive Circuit
Ve
1nFy10µF
To
load
~"',, ~,aE
UNITROOE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. · !.ERRIMACK; NH 03054 TEL. (603) 424-241 O· FAX (603) 424 3460
D1, D2: UC3611 Schottky Diodes 7-31
n nINTEIJRATED
~CIRCUITS
.-UNITRCDE
High Current FET Driver
(~)
UC1710 UC3710
FEATURES Totem Pole Output with 6A Source/Sink Drive Sns Delay Sns Rise and Fall Time into 2.2nF 5ns Rise and Fall Time into 30nF 4.7V to 18V Operation Inverting and Non-Inverting Outputs Under-Voltage Lockout with Hysteresis Thermal Shutdown Protection MINIDIP and Power Packages
BLOCK DIAGRAM
DESCRIPTION The UC1710 family of FET drivers is made with a high-speed Schottky process to interface between low-level control functions and very high-power switching devices-particularly power MOSFET's. These devices accept low-current digital inputs to activate a high-current, totem pole output which can source or sink a minimum of 6A.
Supply voltages for both VIN and Ve can independently range from 4.7V to 18V. These devices also feature under-voltage lockout with hysteresis.
he UC171 O is packaged in an 8-pin hermetically sealed dual in-line
package for -ss·c to +12s°C operation. The UC371 o is specified for
a temperature range of 0°C to +70°C and is available in either an 8pin plastic dual in-line or a 5-pin, T0-220 package. Surface mount devices are also available.
TRUTH TABLE
INV
N.1.
H
H
L
H
H
L
L
L
Out
L
OUT= INV and N.I.
H
L
OUT= INV or N.I.
L
Internally Connected In T-Package
VIN 5 1 - - - - - - . . . . . - - - - - - - - - - - ,
Logic Bias
Output Bias
INV IN Logic Gnd
12/92
Internally Connected In T-Package
7-32
Pwr Gnd
UOG-92027
ABSOLUTE MAXIMUM RATINGS
H:fkg
.!.:fk11.
I£kll
Supply Voltage, Vin ............................... 20V ......... 20V ............ 20V Collector Supply Voltage, Ve ........................ 20V ......... 20V ............ 20V Operating Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18V ......... 18V ............ 18V Output Current (Source or Sink) Steady-State................................. ±500mA.......... ±500mA......... ±1A Digital Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V-VIN ......... -0.3V-VIN ........ -0.3V-VIN Power Dissipation at Ta=25°C. . . . . . . . . . . . . . . . . . . . . . . 1W ......... 1W ............. 3W Power Dissipation at T (Case) = 25°C. . . . . . . . . . . . . . . . . 2W ......... 2W ............. 25W Operating Junction Temperature ............. -55°C-+150°C ......... -55°C-+150°C .... -55°C-+150°C Storage Temperature ...................... -65°C-+150°C ......... -65°C-+150°C .... -65°C-+150°C
o Lead Temperature (Soldering, 1 seconds) .......... 300°C ......... 300°C .......... 300°C
Note 1: All currents are positive into, negative out of the specified terminal. Note 2: Consult Unitrode Integrated Circuits databook for information regarding thermal specifications and limitations ofpackages.
CONNECTION DIAGRAMS
DIL-8 MINIDIP (Top View) J or N Package
DIL-16 (Top View) SP Package
UC1710 UC3710
Pwr
Gnd
IQ I Jl====I~~" 5-Pin T0-220 (Top View)
T Package
SOIC-16 (Top View)
OW Package
.-....---.--....----.
PLCC-28 (Top View) QP Package
_,_ N/C
4 3 2 1 28 27 28
VIN 5
25 Ve
N/C 6
24 Ve
N/C 7
23 Out
Logic Gnd 8
22 Out
N.I. IN 9
21 Pwr Gnd
N/C O
20 Pwr Gnd
N/C 11
19 INV IN
12 1 14 15 16 17 1
~· N/C
ELECTRICAL CHARACTERISTICS: (Unless otherwise stated, these specifications apply for TA =- 55°C to +125°C for the
·c UC1710 and TA= 0 to +70°C for the UC3710; VIN= Ve= 15V, No load TA= TJ..)
PARAMETERS VIN Supply Current
Ve Supply Current
UVLO Threshold
UVLO Threshold Hysteresis D!gital l~ut Low Level Digital Input High Level
TEST CONDITIONS VIN=18V, Ve=18V, Output Low VIN=18V, Vc=18V, Output High VIN=18V, Vc=18V, Output Low VIN=18V, Vc=18V,Output High VIN High to Low VIN Low to High
MIN TYP MAX UNITS
26 35 mA
21
30 mA
1.5 5.0 mA
5.0
8
mA
3.8 4.1
4.4
v
4.1 4.4 4.8
v
0.1
0.3 0.5
v
0.8 v
2.0
v
7-33
UC1710 UC3710
ELECTRICAL
(Unless otherwise stated, these specifications apply for TA =- 55°C to +125°C for the
CHARACTERISTICS (cont.) UC1710 and TA= 0 °C to +70°Cfor the UC3710; VIN= Ve= 15V, No load. TA= TJ.)
PARAMETERS Digital Input Current Output High Sat., Ve-Vo Output Low Sat., Vo Thermal Shutdown From lnv.,lnput to Output (Note 3, 4): Rise Time Delay
10% to 90% Rise
Fall Time Delay
TEST CONDITIONS Digital lnput=O.OV lo=-100mA lo=-6A lo= 100mA lo=6A
CL=O CL= 2.2nF CL= 30nF CL=O CL= 2.2nF CL= 30nF CL=O
MIN TVP MAX UNITS
-70 -4.0
µA
1.35 2.2
v
3.2 4.5
v
0.25 0.6
v
3.4 4.5
v
165
oc
35
70
ns
35
70
ns
35
70
ns
20 40 ns
25 40 ns
85 150 ns
35
70
ns
90% to 10% Fall
From N.I. Input to Output (Note 3,4): Rise Time Delay
CL=2.2nF CL=30nF CL=O CL=2.2nF CL= 30nF
CL=O CL= 2.2nF
35
70
ns
35 80 ns
15 40 ns
20 40 ns
85 150 ns
35
70
ns
35
70
ns
10% to 90% Rise
CL=30nF CL=O CL= 2.2nF
35
70
ns
20 40 ns
25 40 ns
Fall Time Delay
CL=30nF CL=O CL=2.2nF
85 150 ns
35
70
ns
35
70
ns
90% to 10% Fall
CL= 30nF CL=O
35 80 ns 15 40 ns
CL= 2.2nF CL=30nF
20
50
ns
85 150 ns
Note: 3. Delay measured from 50% input change to 10% output change. Note: 4. Those parameters with CL = 30nF are not tested in production.
= = Note: 5. Inv. Input pulsed at 50% duty cycle with N.I. Input 311. or N.I. Input pulsed at 50% duty cycle with Inv. Input 011.
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL Bl.VD. · MERRIMACK. NH 03054 TEL (603) "24-2410 · FAX (603) 424-3460
7-34
n nINTEGRATED
~CIRCUITS
-UNITRODE
Dual Ultra High-Speed FET Driver
{CW) UC1711 UC3711
FEATURES
25ns Rise and Fall into 1000pF
15ns Propagation Delay
1.5A Source or Sink Output Drive
Operation with 5V to 35V Supply
High-Speed Schottky NPN Process
8-PIN MINIDIP Package
ABSOLUTE MAXIMUM RATINGS (note 1) Input Supply Voltage, Vee. . . . . . . . . . . . . . . . . . . . . 40V Output Current (Source or Sink)
Steady State ......................... +/-500mA Peak Transient ......................... +/-1.5A Inputs Maximum Forced Voltage. . . . . . . . . . . . . . . -0 .3V to 7V Maximum Forced Current . . . . . . . . . . . . . . . . . +/- 1OmA Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W Operating Junction Temperature . . . . . -55°C to +150°C Note 1: Unless otherwise indicated, voltages are reference to ground and currents are positive into, negative out of, the specified terminals. All reliability information for this device has been gathered at an ambient air temperature of 125"C, and a supply voltage of 2511. Note 2: Consult Unitrode Integrated Circuits databook for information regarding thermal specifications and /imitations ofpackages.
BLOCK DIAGRAM
DESCRIPTION
The UC1711 family of FET drivers are made with an all-NPN Schottky process in order to optimize switching speed, temperature stability, and radiation resistance. The cost for these benefits is a quiescent supply current which varies with both output state and supply voltage. For lower power requirements, refer to the the UC1709 family which is both pin compatible with, and functionally equivalent to the UC1711.
These devices implement inverting logic with TTL compatible inputs, and output stages which will either source, or sink in excess of 1.5A of load current with minimal cross-conduction charge. Due to their monolithic construction, the channels are well matched and can be paralleled for doubled output current capability.
CONNECTION DIAGRAMS
DIL-8 (Top View) J or N Package
N/Co·N/C
AIN(·) 2
1 A Out
Gnd ·
BIN(-) ·
· Vee s B Out
DIL-16 (Top View) J E or NE Package
12/92
UDG-92028
PLCC-20 (Top View) QP Package
3 2 1 20 19
4
18
5
17
6
16
7
15
8
14
9 10111213
7-35
UC1711 UC3711
o ELECTRICAL CHARACTERISTICS: Unless otherwise stated specifications hold for TA= to 70°C for the UC3711, and
TA= -55to125°C forthe UC1711, Vee= 15V. TA =TJ.
PARAMETER
l~Supply
Supply Current (Note 3)
Logic lnpu1s Logic 0 l'!e_ut VoltaJl_e Logic 1 l'!e_ut Voltage Input Current
Output Stagea Output High Level Output Low Level
SwltchlnaCharacteriatlca (Note 4) Rise lime Delay, TPLH
Fall Time Delay, TPHL
Rise lime, TLH
Fall Time, THL
Total Supply Current
TEST CONDITIONS
Both l'!E._uts = OV; Vee= 15V Both i'!E_uts = 5V; Vee= 15V Both Inputs = OV; Vee = 35V Both i'!e_uts = 5V; Vee = 35V
VIN=OV VIN=5V
lsouRcE = 20mA, below Vee lsouRcE = 200mA, below Vee (SINK= 20mA (SINK = 200mA
CLOAD =0
CLOAD = 1000pF, (Note 5)_
CLOAD = 2200pF CLOAD=O CLOAD = 1OOOpf, (Note 5) CLOAD = 2200pF CLOAD = 0, (Note 5) CLOAD = 1OOOpF, (Note ~ CLOAD = 2200pF CLOAD = 0,j_Note~ CLOAD = 1000pF, (Note~ CLOAD=220~ Freq = 200kHz, 50% Duty-cycle Both Channels Switching CLOAD= 0 CLOAD = 2200pF
MIN TYP MAX UNITS
11
15 mA
20 27 mA
15 20 mA
41
56 mA
0.8 v
2.2
v
-5.0 -2.7
mA
0.5 2.0 mA
1.5 2.0
v
2.0 3.0
v
.25 0.4
v
0.4 1.0
v
10 40 ns
15 50 ns
20
55
ns
3
20 ns
5 20 ns
5
20 ns
12 25 ns
25 40 ns
40 55 ns
7
15 ns
25 40 ns
40
55
ns
17
23 mA
29
35
mA
Note 3: Supply currents at other input supply votages can be calculated by extrapolating the 15Vand 35V supply currents. Theim-
pedance of the chip at the Vee pin is linear tot supply voltages from BV to 3511, the approximate value of this impedance is 4.3k for both inputs low, 0.941< for both inputs high, and 1.54k for one input high and one low.
= Note 4: Switching test conditions are, Vee 1511, Input voltage waveform levels are OV and 5\1, with transition times of <3ns. The
timing terms are defined as : TPHL Propagation delay 50% lhN to 90% VoUT; TPLH Propagation delay 50% \hN to 10% Vour; THL 90%VOUTto 10% Vour; TLH 10% Vourto90% VOUT.
Note 5: This specification not tested in production.Unless otherwise stated specifications hold for TA= 0 to 70°C for the UC3711,
= = and TA -55 to 125°C for the UC1711, Vee= 15\f. TA TJ.
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL 11..VD. · MERRIMACK, NH 03054 TEL (603) 424--2410 · FAX (603) 424-3480
7-36
n nINTEIJRATEO
~CIRCUITS
-UNITROOE
Isolated Drive Transmitter
(~)
UC1724 UC2724 UC3724
FEATURES 500mA Output Drive, Source or Sink 8 to 35V Operation Transmits Logic Signal Instantly Programmable Operating Frequency Under-Voltage Lockout Able To Pass DC Information Across Transformer Up To 600kHz Operation
BLOCK DIAGRAM
DESCRIPTION
The UC1724 family of Isolated Drive Transmitters, along with the UC1725 Isolated Drivers, provide a unique solution to driving isolated power MOSFET gates. They are particularly suited to drive the highside devices on a high-voltage H-bridge. The UC1724 devices transmit drive logic, and drive power, to the isolated gate circuit using a low cost pulse transformer.
This drive system utilizes a duty-cycle modulation technique that gives instantaneous response to the drive control transistions, and reliably passes steady-state, or DC, conditions. High frequency operation, up to 600kHz, allows the cost and size of the coupling transformer to be minimized.
These devices will operate over an 8 to 35 Volt supply range. The dual high current totem pole outputs are disabled by an uder-voltage lockout circuit to prevent spurious responses during startup or low voltage conditions.
These devices are available in 8-pin plastic or ceramic dual-inline packages, as well as surface mount packages.
Bias Gen. & Under Voltage
Lockout
Retrlggerable One-Shot
OS
Edge Detect
Note: Pin numbers refer to OIL-8 packages.
5/93
7-':rl
Gnd Pwr Gnd
UDG-92037
ABSOLUTE MAXIMUM RATINGS
Supply Voltage VIN ................................ 40V Source/Sink Current (Pulsed) . . . . . . . . . . . . . . . . . . . . . . . . 1A Source/Sink Current (Continuous). . . . . . . . . . . . . . . . . . . 0.5A Ouput Voltage (Pins 4, 6). . . . . . . . . . . . . . . -0.3 to {VIN +0.3)V PHI, RT, and CT inputs (Pins 1, 7, and 8) .......... -0.3 to 6V Operating Junction Temperature (Note 2) . . . . . . . . . . . . 150°C Storage Temperature Range ............... -65°C to 150°C Lead Temperature (Soldering, 1OSeconds) .......... 300°C
Note 1: All voltages are with respect to GND (Pin 2); all currents are positive into, negative out of part. Note 2: Consult Unitrode Integrated Circuit Databook for thermal limitations and considerations ofpackage. Note 3: Pin numbers refer to DIL-8 packages.
DIL-8 (Top View)
J Or N Package
UC1724 UC2724 UC3724
SOIC-16 (Top View) DW Package
B
PLCC-20 (Top View) Q Package
L3 2 1 2019
~ 4
18
5
17~
6
16~
7
15~
8
14~
9 10 11 12 13
~
PACKAGE PIN FUNCTION
FUNCTION
PIN
N].C
1
Vee
2
N_l_C
3-4
B Out
5
N].C
6
PwrGnd
7
N_l_C
8-9
A Out
10
N].C
11
PHI
12
N_l_C
13-14
RT
15
N_l_C
16
CT
17
N].C
18-19
Gnd
20
RECOMMENDED OPERATION CONDITIONS (Note 4}
Input Voltage .................................................................. +9Vto +35V Sink/Source Load Current (each output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oto 500mA Timing Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kQ to 10kQ Timing Capacitor .............................................................. 300pF to 3nF Operating Temperature Range (UC1724) ........................................ -55°C<TA<125°C Operating Temperature Range (UC3724). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C<TA<70°C Note 4: Range over which the device is functional and parameter limits are guaranteed.
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, Vee= 20V, RT= 4.3kQ, CT= 1000pF, no load on any
output and these specifications apply for: -55°C<TA<125°C for the UC1724,
-25°C<TA<85°C for the UC2724,and 0°C<TA<70°C for the UC3724. TA=TJ.
PARAMETER Under-Voltage Lockout
Start-Up Threshold Threshold Hysteresis Retriggerable One-Shot Initial Accuracy Temperature Stability Voltage Stability
Operatii:!il_Frequen~
Minimum Pulse Width Operating Frequency
TEST CONDITIONS
VIN Rising
TJ = 25°C Over Operating TJ VIN= 10to 35V LLOAD = 1.4mH RT= 2k CT= 300pF RT = 2k CT = 300pF LLOAD = 1.4mH
MIN TVP MAX UNITS
7.75 9.5
v
0.4 1.0 1.5
v
1.54 1.9 2.25 µs
1.0 0.2
2.9 µs
0.5 %N
100 150 200 kHz
500 ns
500 750 1100 kHz
7-38
UC1724 UC2724 UC3724
ELECTRICAL
Unless otherwise stated, Vee= 20V, RT= 4.3kQ, CT= 1000pF, no load on any output and
CHARACTERISTICS (cont.) these specifications apply for: -55°C<TA<125°C for the UC1724, -25°C<TA<85°C for the
UC2724,and 0°C<TA<70°C for the UC3724. TA=TJ.
PARAMETER Phi Input (Control Input)
HIGH f'!E_Ut Volta_g_e LOW Input Voltage HIGH Input Current LOW Input Current Delay to One-Shot Delay to Output Output Drivers Output Low Level
Output High Level (Volts Below Vee)
Rise/Fall Time Total Supply Current
Supply Current
TEST CONDITIONS
VIH = +2.4V VIL= +0.4V
!SINK = 500mA !SINK = 250mA !SOURCE = 250 mA !SOURCE = 250 mA No load CT= 1.4V
MIN TVP MAX UNITS
2.0
v
0.8 v
-220 -130
mA
-600 -300
µA
350 ns
250 ns
0.3 0.4
v
0.5 2.1
v
1.5 2.1
v
1.7 2.5
v
30
90
ns
15
30
mA
Typical Application
High Voltage Rail
UC3724
UC3725
To Power Gnd
UDG·92038
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL Bl.VD. · MERRIMACK, NH 03054 TEL. (603) 424-2410 · FAX (603) 424-3460
7-39
n n l'.::::::'._j
INTEGRATED CIRCUIT8
-UNITRCDE
Isolated High Side FET Driver
UC:1725 UC2725 UC3725
FEATURES Receives Both Power and Signal Across the Isolation Boundary
9 to 15 Volt High Level Gate Drive
Under-voltage Lockout
Programmable Over-current Shutdown and Restart
Output Enable Function
DESCRIPTION The UC1725 and its companion chip, the UC1724, provide all the necessary features to drive an isolated MOSFET transistor from a TTL input signal. A unique modulation scheme is used to transmit both power and signals across an isolation boundary with a minimum of external components.
Protection circuitry, including under-voltage lockout, over-current shutdown, and gate voltage clamping provide fault protection for the MOSFET. High level gate drive is guaranteed to be greater than 9 volts and less than 15 volts under all conditions.
Uses include isolated off-line full bridge and half bridge drives for driving motors, switches, and any other load requiring full electrical isolation.
The UC1725 is characterized for operation over the full military temperature range of-55°C to +125°C while the UC2725 and UC3725 are
characterized for -25°C to +85°C and o·c to +70°C respectively.
BLOCK DIAGRAM
Hysteresis Comparator
1/93
Internal Reference
0.5V +
15V Output Clamp
I SENSE
Timing
7-40
UOG-92051
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (pin 3) ............................. 30V Power inputs (pins 7 & 8) ........................... 30V Output current, source or sink (pin 2) DC ........................................... 0.5A Pulse (0.5 us) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0A Enable and Current limit inputs (pins 4 & 6) . . . . . . . -0.3 to 6V Power Dissipation atTA:s 25°C (DIL-8) ................ 1W Power Dissipation at TA :s 25°C (S0-14) ............ 725mW Lead Temperature (Soldering, 1OSeconds) .......... 300°C
Note 1: Unless otherwise indicated, voltages are referenced to ground and currents are positive into, negative out of, the specified terminals {pin numbers refer to DIL-8 package). Note 2: See Unitrode Integrated Circuits databook for information regarding thennal specifications and limitations of packages.
CONNECTION DIAGRAMS
UC1725 UC2725 UC3725
PLCC-20 (Top View) Q Package
L3 2 1 2019
4
18
5
17
6
16
7
15
8
14
9 10 11 12 13
~~~~
PACKAGE PIN FUNCTION
FUNCTION
PIN
N_LC
1
I SENSE
2
N_LC
3-5
Timi!:lQ..
6
Enable
7
N_LC
8-9
lr:m_utA
11
NLC
12-14
lr:m_ut 8
15
Gnd
16
Vee
17
NlC O~ut
18-19 20
DIL-8 (Top View)
J Or N Package
Gnd
Vee
I SENSE
SOIC-16 (Top View) DW Package
Input B Input A
DIL-16 (Top View)
JE Or NE Package
Gnd N/C Input B Input A
ELECTRICAL CHARACTERISTICS: (Unless otherwise stated, these specifications apply for -55°C:sTA:s+125°C for
UC1725; -25°C:sTA:s+85°C for UC2725; 0°C:sTA:s+10°c tor UC3725; Vee (pin 3) =
0 to 15V, RT=10k, CT=2.2nf, TA =TJ, pin numbers refer to DIL-8 package.)
PARAMETER POWER INPUT SECTION (PINS 7 & 8)
Forward Diode Drop, Schottky Rectifier
CURRENT LIMIT SECTION (PIN 4) Input bias current Threshold voltage Delay to outputs
TIMING SECTION~N~ Output Off Time Upper Mono Threshold Lower Mono Threshold
HYSTERESIS AMPLIFIER (PINS 7 & 8) Input Open Circuit Voltage Input Impedance Hysteresis Delay to Outputs
TEST CONDITIONS
IF= 50ma
IF =500ma
MIN TYP MAX UNITS
.55
.7
v
1.1
1.5
v
VPIN4:0V
= VPIN4 0 to 1V
-1
-10 µA
0.4 0.5 0.6
v
100 250 ns
Inputs (pins 7 & 8), Open Circuited, TA= 25°C TA= 25°C
VPIN7 - VPIN8 = Vee + 1v
27 30 33 µs
6.3 7.0 7.7
v
1.9 2.0 2.3
v
7.0 Vcc/2 8.0
v
23
28
33
kQ
v 26.5 2·Vcc 30.5
100 300 ns
7-41
ELECTRICAL CHARACTERISTICS (eont.)
PARAMETER ENABLE SECTION (PIN~
HJ9!1 Level Input Vo~ Low Level l~ut Voltag_e lr1E._ut Blas·Current OUTPUT SECTION Output Low Level
Output High Level
Rise/Fall Time UNDERVOLTAGELOCKOUT
UVLO Low Saturation Start-up_ Threshold Threshold H_ysteresis TOTAL STANDBY CURRENT Supply Current
UC1725 UC2725 UC3725
(Unless otherwise stated, these specifications apply for -55°C:sTAS:+125°C for UC1725;
-25°C:sTA:5+85°C for UC2725; 0°C:sTA:s+70°C for UC3725; Vee (pin 3) .; Oto 15V, Rt:10k,
Cr=2.2nf, TA=TJ, pin numbers refer to DIL-8 package.)
·
TEST CONDITIONS
MIN TYP MAX UNITS
2.1 1.4
v
1.4 .8
v
-250 -500 µA
IOUT=20mA loUT=200mA IOUT=-20mA IOUT = -200mA Vee = 30V, lout= -20mA Cr=1nf
0.35 0.5
v
0.6 2.5
v
13 13.5
v
12 13.4
v
14
15
v
30 60 ns
20mA, Vee =av
0.8 1.5 v 11.2 12 12.6 v .75 1.0 1.12 v
12
16 ma
APPLICATION AND OPERATION INFORMATION INPUTS: Figure 1 shows the rectification and detection scheme used in the UC1725 to derive both power and signal information from the input waveform. Vee is generated by peak detecting the input signal via the internal bridge rectifier and storing on a small external capacitor, C1 . Note that this capacitor is also used to bypass high pulse currents in the output stage, and therefore should be placed direclty between pins 1 and 3 using minimal lead lengths.
add a damping resistor across the transformer secondary to minimize ringing and eliminate false triggering of the hysteresis amplifier as shown in Figure 3.
ov ..............................................
CT
Output
FIGURE 2 - Input Waveform (DIL-8 Pin 7 - Pin 8)
FIGURE 1 - Input Stage
UDG-92047
Signal detection is performed by the internal hysteresis comparator which senses the polarity of the input signal as shown in Figure 2. This is accomplished by setting (resetting) the comparator only if the input signal exceeds Vee (-Vee). In some ca8es it may be necessary to
7-42
Output_J Output Pulsing Caused By Transformer Ringing
FIGURE 3 - Signal Detection
UDG-92048
UC1725 UC2725 UC3725
Output
FIGURE 4 - Current Limit
RSENSE
Load
UOG-92050
CURRENT LIMIT AND TIMING: Current sensing and shutdown can be implemented directly at the output using the scheme shown in Figure 4. Alternatively, a current transformer can be used in place of RsENSE. A small RC filter in series with the input (pin 4) is generally needed to eliminate the leading edge current spike caused by parasitic circuit capacitances being charged during turn on. Due to the speed of the current sense circuit, it is very important to ground CF directly to Gnd as shown to eliminate false triggering of the one shot caused by ground drops.
One shot timing is easily programmed using an external
capacitor and resistor as shown in Figure 4. This, in turn, controls the output off time according to the formula:
TOFF= 1.28· RC. If current limit feature is not required, simply ground pin 4 and leave pin 5 open.
OUTPUT: Gate drive to the power FET is provided by a totem pole output stage capable of sourcing and sinking currents in excess of 1 amp. The undervoltage lockout circuit guarantees that the high level output will never be less than 9 volts. In addition, during undervoltage lockout, the output stage will actively sink current to eliminate the need for an external gate to source resistor. High level output is also clamped to 15 volts. Under high capacitive loading however, the output may overshoot 2 to 3 volts, due to the drivers' inabitlity to switch from full to zero output current instantaneously. In a practical circuit this is not normally a concern. A few ohms of series gate resistance is normally required to prevent parasitic oscillations, and will also eliminate overshoot at the gate.
ENABLE: An enable pin is provided as a fast, digital input that can be used in a number of applications to directly switch the output. Figure 6 shows a simple means of providing a fast, high voltage translation by using a small signal, high voltage transistor in a cascade configuration. Note that the UC1 725 is still used to provide power, drive and protection circuitry tor the power FET.
FIGURE 5 - Output Circuit
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. · MERRIMACK NH 03054 TEL (603) 424·2410 · FAX (603) 424·3460
Load
UDG-92052
Jl
UDG-92053
FIGURE 6 - Using Enable Pin as a High Speed Input Path
7-43
n n INTEGRATED
~CIRCUITS
-UNITROCE
Isolated Drive Transmitter
UC1726 UC2726 UC3726 PRELIMINARY
FEATURES 750mA Output Drive, Source or Sink
8 to 35V Operation
Transmits Logic Signal Instantly
Programmable Operating Frequency
Able To Pass DC Information Across Transformer
Up To 750kHz Operation
Improved Output Control Algorithm Minimizes Output Jitter
Fault Logic Monitors Isolated Driver IC (UC1727) for Faults
User Programmable Fault Timing Screens False Fault Signals
Shutdown Mode Disables On Chip Logic Reference for Low Standby Power
Optional External Biasing of Logic Circuitry Can Reduce Overall Power Dissipation
DESCRIPTION
The UC 1726 family of Isolated Drive Transmitters, along with the UC 1727 Isolated Drivers, provide a unique solution to driving isolated power IGBTs. They are particularly suited to drive the high-side devices on a high-voltage H-bridge. The UC1726 device transmits the drive logic and drive power, along with transferring and receiving fault information with the isolated gate circuit using a low cost pulse transformer.
This drive system utilizes a duty-cycle modulation technique that gives instantaneous response to the drive control transitions, and reliably passes steady-state, or DC conditions. High frequency operation, up to 750kHz, allows the cost and size of the coupling transformer to be minimized.
The IC can be powered from a sole Vee supply which internally generates a voltage reference for the logic circuitry. It can be placed into a low power, shutdown mode that will disable the internal reference. The IC's logic circuitry can be powered from an external supply to minimize overall power dissipation. The fault logic monitors the Isolated Driver IC (UC1727) for faults. Based on user defined timing, the IC distinguishes valid faults which it responds to by setting the fault latch pin. This will also disable the gate drive information until the fault reset pin is toggled to a logic one.
These devices will operate over an 8 to 35 volt supply range. The typical Vee voltage will be above 28 volts to be compatible with the UC 1727. The under voltage lock out circuitry of the Isolated Driver IC (UC1727) will effectively lock out the drive information during its under voltage lockout.
BLOCK DIAGRAM
VL 9
BIAS GENERATOR & UNDER VOLTAGE LOCKOUT
SHTDWN 1ssr-------'
TO REST OF CHIP
7-44
CONNECTION DIAGRAMS DIL-16, 18 J, 28 DWP (TOP VIEWS)
FLArCH 1 FAULT 3
GND 7 GND s
UC1726 UC2726 UC3726
N!C N!C
N/C GND
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Vee
. 40V
Source/Sink Current (Pulsed) ............................................... 1.5A
Source/Sink Current (Continuous) ....................................... 1.0A
Output Voltage (pins 12, 14) ........................... -0.3 to (Vcc+0.3)V
CF, FRESEr, FAULT, SHTDWN,
FLArcH, VL, PHI, Rr ................................................... -0.3 to 6.0V
Cr
1.0 to 6.0V
Operating Junction Temperature (Note 2) ......................... 150°C
Storage Temperature Range ............................... -65°C to 150°C
Lead Temperature (Soldering, 10 Seconds) ..................... 300°C
Note 1: All voltages are with respect to GND (Pin 2); all currents
are positive into, negative out of part.
RECOMMENDED OPERATING CONDmONS (Note 3)
Input Voltage ...........................................................+9 to +35.0V Sink/Source Current (each output) ............................ 0 to 750mA Timing Resistor ................................................ 2.4k to 200k0hm Timing Capacitor (Cr) ............................................ 75pF to 2.0nF Timing Capacitor (CF) ............................................ 75pF to 3.0nF Note 2: See Unitrode Integrated Circuits databook for information
regarding thermal specifications and limitations of packages. Note 3: Range over which the device is functional and parameter limits are guaranteed.
PIN DESCRIPTIONS
FRESET: The inputto the fault logic that resets the tau It logic latch (FLATCH) and enables drive transmit data. This input should be powered up low and stay low until after the fault latch has been set.
GND: The signal and power ground for the device. The power ground of the output transistor is isolated on the chip from the substrate ground used to bias the remainder of the device.
FAULT: This input to the fault logic initiates the user programmable timer. This time interval specified by the capacitor on CF determines the validity of the fault. The pin is tied to a low cost opto-coupler, and is high until the UC 1727 powers up, and drives it low indicating proper power-up. The UC1726 sends drive information from the PHI pin through the transformer while the FAULT pin stays low. Once this pin goes high, it must stay high during the entire fault window to be accepted as a valid fault. A valid fault sets the FLATCH pin high and prevents the transmitting of gate drive information until the FRESET is toggled high.
CF: The timing input to the fault logic. A capacitor is placed across the input of CF and ground. The timing window is roughly determined by t= CF * RT * 2.1.
Cr: The input of the timing capacitor that controls the
operating frequency. A capaciior to ground is repetitively charged during the one shot pulse width. It is discharged when a comparator senses zero current in the primary side of the transformer. The one shot pulse width is consequently determined by the time it takes to charge the capacitor to a threshold voltage of VU2. This pin is intended to be tied to a capacitor.
Rr: The inputthat sets the CT and CF capacitor currents with
a resistor to ground. The voltage on RT is approximatelyVL* (0.3V). The resulting charge currents are: ICT = ICF = VL/(4 *RT).
7-45
UC1726 UC2726 UC3726
SHTDWN: This input shuts down the internal reference. A TTL logic one voltage will put the IC into a low standby current mode. This input has a pull down resistor on the chip to guarantee proper operation when left open. If an external logic voltage is applied to VL, this shutdown feature cannot be used without bringing the external voltage source to zero volts.
VL: The logic supply pin that biases all circuits exceptforthe totem pole outputs. A bypass capacitor is recommended on this pin when left unconnected. The internal reference is approximately 4.4V. A5.0V supply can be applied to this pin to assure minimum power dissipation. When an external supply higher than the VL voltage is applied to this pin, the internal reference turns off.
Vee: The input voltage that biases the outputs and the internal reference. It can vary between 8V to 35V. This supply pin will typically be above 28V to be compatible with the 1727 application.
the output will toggle between Vcc-1.5V during the oneshot charge time and approximately Vee* .6 during the rest of the period. When PHI is low the output will toggle between 0.3V during the oneshot charge time and approximately Vcc+0.4V during the remainder of the period.
OUTA: One output of the two totem pole outputs connected across the transformer primary winding. When PHI is high, the output will toggle between 0.3V during the oneshot charge time and approximately Vcc+0.4 during the rest of the period. When PHI is low the output will toggle between Vcc-1.5V during the oneshot charge time and approximately Vcc*.6 during the remainder of the period.
PHI: A logic control input to the isolated gate driver that changes the outputs as described above. This will change the duty-cycle of the voltage wave form applied across the transformer. The isolated drive IC (UC 1727) will sense the different duty-cycles as different drive commands.
OUTB: One output of the two totem pole outputs connected across the transformer primary winding. When PHI is high,
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, Vee=20V, RT=4.32k0, CT=330pF and CF=2.2nF, no
load on any output, and -55°C<TA <125°C for the UC1726, -25°C<TA<85°C for the UC2726 and 0°C<TA<70°C for the UC3726, TA= TJ.
PARAMETER RETRIGGERABLE ONE-SHOT
Initial Accuracy Temperature Stabil!!i'.. Volt~e Stability Operating Frequency PHI INPUT{CONTROL INPUT HIGH IQQ.ut Volt~e LOW Input Voltage HIGH IQQ.ut Current LOW Input Current Del~ to One-Shot Delay to Output OUTPUT DRIVERS Output Low Level
Output High Level (volts below Vee)
Rise/Fall Time LOGIC VOLTAGE REF.
VL-Logic Voltage Logic Supply Current
TEST CONDITIONS
TJ = 25°C Over Qe_erati~ TJ Vee= 10to 35V LLoAo = 1.5mH
CT= 1.4V lslNK = 50mA ls1NK = 750mA ISOUReE = 50mA lsouReE = 750mA No load Internal Voltage VL = 4.75V to 5.25V
7-46
MIN
TYP
MAX UNITS
1.250 1.010
1.350
0.2 200
1.450 1.990
µSec 1Sec
%/V kHz
2.0
v
0.8
v
10
~
-600
-300
µA
100
250
nSec
250
nSee
0.3
0.4
v
1.5
2.1
v
1.5
2.1
v
1.7
2.1
v
30
90
nSec
4.30
4.4
4.50
v
12.0
18.0
mA
UC1726 UC2726 UC3726
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, Vcc=20V, RT=4.32k0hm, CT=330pF and CF=2.2nF, no
load on any output, and -55°C<TA<125°C for the UC1726, -25°C<TA<85°C for the UC2726 and 0°C<TA<70°C for the UC3726, TA= TJ.
PARAMETER
SHUT DOWN CIRCUIT Logic Voltage-Off High Input Current Low Input Current
FAULT LOGIC Fault Reset High Input Current Low Input Current Fault High Input Current Fault Low Input Current Supply Current Min Fault Pulse Max Fault Pulse Fault Latch, VoH Fault Latch, VoL Fault Latch, VoH Fault Latch, VoL
TOTAL SUPPLY CURRENT Supply Current Supply Current
TEST CONDITIONS
V1H = 2.4 V1L = 0.4
V1H = 2.4 VIL= 0.4 V1H = 2.4 VIL= 0.4 CT= 1.4V, Shutdown= 5.0V CF= 330pF CF= 2.2nF ILoAo = -1 mA, Volts Below VL ILoAD = 1mA ILoAo ~ 0, Volts Below VL ILOAD = 0
CT= 1.4V CT= 1.4V, VL = 5.0V
MIN
TYP
MAX UNITS
0.5
v
-100
µA
-20
µA
-5
5
µA
-10
µA
-5
5
µA
-10
µA
2.5
mA
3.0
µS
20.0
µS
1.7
1.3
v
0.25
0.4
v
0.3
v
0.2
v
20
40
mA
10
16
mA
OPERATING FREQUENCY: The chip operating frequency is determined by both the Rr and Cr pins. A resistor between Rr and ground will set the charge current to ICT = VL/(Rr*4). The operating frequency varies slightly depending on the Vee and VL voltages. The following two equations are for Vee = 20V.
VL =Internal Reference (4.4V)
Fo = 1/(RT ·CT· (2.959) + 0.83 x 10··;
VL = External Reference (5V)
Fa= 1/(Rr ·CT· (2.700) + 0.46 x 10··)
7-47
TYPICAL APPLICATION
VL
Isolated IGBT Driver Pair
Ve
UC1726 UC2726 UC3726
FAULT
Drive Transmitter
vcc
Isolated Gate Driver
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. ·MERRIMACK, NH 03054 TEL. (603) 424-2410 ·FAX (603) 424-3460
7-48
n n C_j
INTEl3RATEC CIRCUITS
-UNITRODE
Isolated High Side IGBT Driver
UC1727 UC2727 UC3727
PRELIMINARY
FEATURES Receives Power and Signal from Single Isolation Transformer
Generates Split Rail for 4A Peak Bipolar Gate Drive
16V High Level Gate Drive
Low Level Gate Drive more Negative than -SV
Under Voltage Lockout
Desaturation Detection and Fault Processing
Separate Output Enable Input
Programmable Stepped Gate Drive for Soft Turn On
Programmable Stepped Gate Drive for Soft Fault
BLOCK DIAGRAM
DESCRIPTION The UC1727 and its companion chip, the UC1726, provide all the necessary features to drive an isolated IGBT transistor from a TTL input signal. A unique modulation scheme is used to transmit both power and signal across an isolation boundary with a minimum of external components.
Protection features include under voltage lockout and desaturation detection. High level gate drive signals are guaranteed to be 16V. Intermediate high drive levels can be programmed for various periods of time to limit surge current at turn on and in the event of desaturation due to short circuit.
The chip generates a bipolar supply so that the gate can be driven to a negative voltage to insure the IGBT remains off in the presence of high common mode slew rates.
Uses include isolated off-line full bridge and half bridge drives for motors, switches, and any other load requiring full electrical isolation.
B
BIAS AND
PVcc
REFERENCE
GENERATOR
UVLO
5/93
Vee -16
DSAT·
0SAT· Vee
7-49
ABSOLUTE MAXIMUM RATINGS
Supply voltage r.Jcc - VEE) ..................................... 40V Power Inputs (IA - Bl) ~- ................................... 45V Analog Input Voltage (ENBL, CLAMP) .................. -0.3 To Vcc+0.3 Analog Input Voltage (DSAT+, DSAT·) ................ VEE-0.3 to Vcc+0.3 Analog Input Current (DSAT+, DSAT-) ...................... -10to 10mA
I Output Current, I (OUl)
DC .................................................... 0.8A Pulse (0.5µs) .............................................. 4A FAPLY Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30mA
Note: Alf voltages are with respect to COM. Currents are positive into the specified terminal.
CONNECTION DIAGRAMS
DIL-16 (Top View) N or J Package
18 Pin Sidebrazed Ceramic Package
TAC FRO FRPLY Vee VEE COM CLAMP
B
ENBL DSAT· DSAT+ PVEE PVEE OUT Vee A
NC NC
DSAT+
DSAT· ENBL TRC FRC FRPLY
NC
UC1727 UC2727 UC3727
PVce OUT PVee Vee A B CLAMP COM
Vee
PLCC-28 (Top View) QP Package
L4 3 2 1 28 27 26
5
25p
6
24i
7
23p
8
22
9
21
10
20
11
19
12 13 14 15 16 17 18
~
PACKAGE PIN FUNCTION
FUNCTION
PIN
N/C
1
VEE
2
N/C
3-4
COM
5
CLAMP
6
B
7
A
8
Vee
9
PVcc
10
OUT
11
PVEE
12-18
DSAT+
19
DSAT·
20
ENBL
21
NC
22
TAC
23
FAC
24
FAPLY
25
N/C
26
N/C
27
N/C
28
LCC-28 (TOP VIEW) L Package
L -=-=--=-=-=-=4 3 2 1 28 21 2s
5
25
6
24
7
23
8
22
9
21 p
10
2op
11 12 13 14 15 16 17 18 19 p
~
PACKAGE PIN FUNCTION
FUNCTION
PIN
N/C
1
VEE
2
N/C
3-4
COM
5
CLAMP
6
B
7
A
8
Vee
9
PVcc
10
OUT
11
N/C
12-13
PVEE
14
N/C
15-18
DSAT+
19
DSAT·
20
ENBL
21
NC
22
TAC
23
FAC
24
FAPLY
25
N/C
26-28
7-50
UC1727 UC2727 UC3727
PIN FUNCTIONS A & B: Signal and power input pins. Connect these pins te the secondary of the transformer driven by UC1726.
FRPLY: Fault Reply pin. Open collector output. Normally shorted to COM. When desaturation is detected,
CLAMP: Analog Programming pin for intermediate drive the pin will open.
level to be used at turn on or in response to a desatura- OUT: Gate drive output. Connect to gate of IGBT with a
tion event. Requires a bypass capacitor to COM.
damping resistor >3 ohms.
COM: Self generated common for bipolar supply. This TRC: liming Resistor and Capacitor. Programs the du-
pin will be 16.SV below Vee.
ration that OUT will be held at CLAMP potential and the
DESAT+ & DESAT-: Inputs to the desaturation compara- period of time the desaturation comparator will be ignored
tor. Desaturation is detected when DESAT+> DESAT-.
during the rising edge.
ENBL: Negative-true enable input. lie to Vee to disable Vee: Positive supply voltage. Bypa8s to COM.
the chip. Short to COM to enable the Chip. If the ENBL VEE: Negative supply voltage. Bypass to COM.
pin is to be used as the primary input to the chip, short A PVEE: Output driver negative supply. Connect to VEE with
to Vee and B to VEE.
2.2 ohms and bypass to COM.
FRC: Fault Resistor and Capacitor. Programs the dura- PVcc: Output driver positive supply. Connect to Vee with tion that OUT will be held at CLAMP potential during a de- 2.2 ohms and bypass to COM. saturation event before it is driven fully low. Also sets the ·
period of time that OUT will be held low before allowing it to be driven high again.
o ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA = to 70°C for the
UC3727, TA= -25 to B5°C for the UC2727, TA= -55 to 125°C for the uc1121,
R(TRC) = 54.9k, C(CTC) = 180pF, R(FRC) = 309K, C(FRC) = 200pF, Vee - VEE= 25V, CLAMP= 9V, TA= TJ. and all voltages are measured with respect to COM.
PARAMETER POWER INPUT RECEIVERS
Forward Diode D!<>!>_
VCC REGULATOR Vee
HYSTERESIS COMPARATOR Input O~ Circuit Voltage l~ut lm..E!_dance H_ysteresis
ENABLE INPUT High Level Input Voltage Low Level l'!e_ut Voltage Input Bias Current
OUTPUT DRIVER Saturation to Vee Saturation to Vee Saturation to VEE Saturation to VEE Tum on Clamp Voltage Fault Clall!e_Voltage UVLO Saturation to VEE Rise/Fall Tlme
TEST CONDITIONS
IF=50mA IF=500mA
25 " (Vee - VEE) "36V,ll(COMU" 15mA (Measured with re51>_ect to VEE)
ENBL=COM
!iOUT) = -20mA I(OUT) = -500mA I(OUT) = 20mA !(_Olm_= 500mA l(OUT) = -100mA J!(OUT)l = 100mA !(OUT) = 20mA,Vee no connection Cl = 1n, CLAMP = Vee, ROUT = 3Q
MIN TVP MAX UNITS
0.4 0.6
v
1.2
2
v
15.5 16.5 17.5 v
12.5
v
50 100 180 kQ
45 47.5 50
v
12 v
5
v
-460 -900 µA
1.7 2.3
v
2
2.5
v
2
3
v
2.4 3.4
v
7
9
11
v
7
9
11
v
1.5
2
v
75 150 ns
7-51
UC1727 UC2727
UC3727
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA= o·c to 70"C for the
UC3727, TA= ·25to 85°C for the UC2727, TA= -55to 125°Cforthe UC1727, R(TRC) = 54.9k, C(CTC) = 180pF, R(FRC) = 3091<, C(FRC) = 200pF, Vee~ VEE= 25V, CLAMP= 9V, TA= TJ, and all voltages are measured with respect to COM.
PARAMETER
TEST CONDITIONS
TURN ON SEQUENCE TIMER
Clamped Driver Time
Blanki~Time
FAULT MANAGER Clam~ Drlwr Time
Fault Lock Off Time
FRPLY Saturation
l(FRPLY) = 10mA
FRPLY Leaka~
FRPLY=Vee
DESATURATION DETECTION COMPARATOR
Input Offset Voltage fi_viaj}
VeM = VEE+2, VeM = Vee-2
l~t Blas Current Del~to Output
Q{fRCl=O
UNDER VOLTAGE LOCK OUT
Vee Threshold
Vee Hysteresis
VEE Threshold
VEE Hysteresis
THERMAL SHUTDOWN
Threshold
Not tested
~teresis
Not tested
TOTAL STANDBY CURRENT
l(Vcc)
MIN TVP MAX UNITS
0.5
1
1.5 µs
3
5
7
~
0.5
1
1.5 ~
15 25 35 µs
v 0.8 1.2
0 10 liA
0 -1.5 . 150
20 mV
10 ~
ns
15
16
17
v
0.5
1
1.5 v
5
-5.5 -6
v
v 0.2 0.5 0.8
175
c
45
c
24 30 mA
APPLICATION INFORMATION
Figure 1 shows the rectification and detection scheme
used in the UC1727 to derive both power and signal infor-
mation from the input waveform. Vee-VEE is generated
A
by peak detecting the input signal via the internal bridge
rectifier and storing on external capacitors. COM is gen-
erated by an internal amplifier that strives to maintain
= Vee-COM 16.5\f. It is important to select Both Capaci-
tors of equal value and large enough so that Vee and VEE
ripple are small. Large ripple will cause the COM ampli-
fier to dissipate excessive power.
Signal detection is performed by the internal hysteresis comparator which· senses the polarity of the input signal as shown in figure 2. This is accomplished by setting (or resetting) the comparator only if the input signal exceeds 0.95*[Vee-VEE) (or 0.95*[VEE-Vee]). In some cases it may be necessary to add a damping resistor across the transformer secondary to minimize ringing and eliminate false triggering of the hysteresis comparator as shown in figure 3.
Figure 1. Input Stage & Bipolar Supply
7-52
SIGNAL
DETECT COMPARATOR
Vee COM
Yu
APPLICATION INFORMATION (cont'd)
----- ~t- 0.95 (Vee-VEE) -
··...,_.: =~m==-= ~~
OUT
1 V e e -
VEE
OUT
Vee CLAMP
OV VEE
TRC
Vee/2 Vee/4
Figure 2. Input Waveform
Figure 4. Rising Edge Waveform
UC1727 UC2727 UC3727
0.96 (Vee ·VEE)
B·A
OV
0.95 (Vee ·VEE)
_ I I Vee
OUT
VEE
--------
DESAT COMPARATOR
Yeo
OUT eLA::-t-±------
FAe ;;~
FPPLV
Vee
COM __j
Figure 3. Output Pulsing Caused By Transformer Ringing Figure 5. Transient Desaturation Response
GATE ORNE WAVEFORM
The rising edge of OUT can be programmed for a two step sequence as shown in figure 4. The plateau voltage is programmed by a resistive divider from Vee to COM applied at CLAMP. CLAMP must be bypassed to COM. The plateau voltage is approximately OUT= CLAMP. The plateau time is set by a resistor from TRC to Vee and a capacitor to COM as:
Tp = RC*ln((R-7.6k)!(R-12.4k)).
TRC also programs a blanking time during which the chip ignores the desaturation comparator. The blanking time is:
Tb = Tp + 0.4*RC.
In the event that desaturation is detected outside the blanking interval, OUT will be driven back to the CLAMP plateau for a fault time set by a resistor from FRC to Vee and a capacitor to COM as:
Tf = RC*/n((R-7.6k)!(R-12.4k)).
If the event is transient, OUT will return fully high at the end of Tf as shown in figure 5. During Tf, FRPLY is open. After Tf, FRPLYis shorted to COM.
Desaturation shown in figure 6 that persists longer than Tf will cause OUT to be driven fully low. The chip will not accept a command to drive OUT high for a delay period of
Td=0.4*RC
FRPLY will be open during this entire period.
7-53
_ J [ _ _ _ _ _ DESAT
COMPARATOR
ii- --- -- Vee
I I
OUT
CLAMP OV
VEE
FRC
~ 3- Vcc/2
Vee/4
~
TD
FPPLY
~ Vee
COM
EXTERNAL BIPOLAR SUPPLIES
UC1727 UC2727 UC3727
If it is desired to drive an emitter grounded IGBT from external supplies, the configuration in figure 8 should be used. COM should never be connected to ground. Vee must be <!: 12V and Vee-VEE must be <!: 23.SV.
Vee
V+ COM
Figure 6. Rising Edge Waveform
ENABLE V-
ENBL provides an alternate means of controlling the out-
put. If ENBL is to be used as the primary input, A should
Vee
be connected to Vee and B to VEE. ENBL can be driven
by the output of an opto-isolator from ENBL to COM as
shown in figure 7. If ENBL is not used, it should be Figure 8. Using External Supplies shorted to COM.
300
Figure 7. Using ENBLas Primary Input
UNITRODE INTEGRATEO CIRCUITS 7 CONTINENTAL BLVD. · MERRIMACK, NH 03054 TEL (603) 424-2410 ·FAX (603) 424-3460
CLAMP Vee
-55
125
TEMPERATURE
Figure 9. Input to Output Delay
7-54
n nINTEGRATED
~CIRCUITS
-uNITRODE
Thermal Monitor
UC1730 UC2730 UC3730
FEATURES On-Chip Temperature Transducer Temperature Comparator Gives Threshold Temperature Alarm Power Reference Permits Airflow Diagnostics Precision 2.5V Power Reference Permits Airflow Diagnostics Transducer Output is Easily Scaled for Increased Sensitivity Low 2.5mA Quiescent Current
BLOCK DIAGRAM
DESCRIPTION
The UC1730 family of integrated circuit devices are designed to be used in a number of thermal monitoring applications. Each IC combines a temperature transducer, precision reference, and temperature comparator allowing the device to respond with a logic output if temperatures exceed a user programmed level. The reference on these devices is capable of supplying in excess of 250mA of output current - by setting a level of power dissipation the rise in die temperature will vary with airflow past the package, allowing the IC to respond to airflow conditions
These devices come in an 8-Pin DIP, plastic or ceramic, a 5cPin T0-220 or a PLCC-20 version. In the 8-Pin version, a PTAT (proportional to absolute temperature) output reports die temperature directly. This output is configured such that its output level can be easily scaled up with two external gain resistors. A second PTAT source is internally referenced to the temperature comparator. The other input to this comparator can then be externally programmed to set a temperature threshold. When this temperature threshold is exceeded an alarm delay output is activated. Following the activation of the delay output, a separate open collector output is turned on. The delay pin can be programmed with an external RC to provide a time separation between activation of the delay pin and the alarm pin, permitting shutdown diagnostics in applications where the open collector outputs of multiple parts are wire OR'ed together.
The 5-Pin version in the T0-220 package is well suited for monitoring heatsink temperatures. Enhanced airflow sensitivities can be obtained with this package by mounting the device to a small heatsink in the airstream. This version of the device does not include the PTAT output or the open collector alarm output.
+VIN
PTAT
BUFFER
THERMAL
--1-~T PTAT+ @Jr-<N_A_l
c;:G
PTAT- [fil(NA)
/~-- ..... '-----~---
2.5V REFERENCE
PTAT VOLTAGES 5 mV/°K \
TEMPERA TU~~ \
ALARM DELAY
1
COMPARATOR !-'-;__~-,
_ =
GND
(NA) 2
ALARM THRESHOLD SET
ALARM OUTPUT
5/93
Pin numbers shown for 8-Pin DIP, () number for 5-Pin T0-220. 7-55
ABSOLUTE MAXIMUM RATINGS
Input Supply Voltage, (+VIN) ..·.................... 40V Alarm Output Voltage (8-Pin Version Only) . . . . . . . . . . . 40V Alarm Delay Voltage ............................. 10V
Alarm Threshold Set Voltage . . . . . . . . . . . . . . . . . . . . . . 1OV
2.5V Reference Output Current .................. -400 mA Alarm Output Current (8-Pin Version Only) . . . . . . . . . . O mA Power Dissipation at TA= 25°C (Note 2) ......... 1000 mW Power Dissipation at Tc= 25°C (Note 2) ......... 2000 mW Thermal Resistance Junction to Ambient N, 8-Pin Plastic DIP . . . . . . . . . . . . . . . . . . . . . . . . . 110°C/W J, 8-Pin Ceramic DIP .. · . .. .. . . . . . . . . . . .. . . .. 110°C/W
CONNECTION DIAGRAMS
DIL-8 (TOP VIEW) N or J Package
ALARM THRESHOLD SET 7 2.SV REFERENCE
+VIN GND
PTATPTAT+
5-PIN T0-220 (TOP VIEW) TPackage
1°11 i11=~=======· ~f~:: ~:~::HOLD L._J_I....J.lr-~
2.SV REFERENCE
SET
'Tab Is connected to GND
UC1730 UC2730 UC3730
T, 5-Pin Plastic DIP T0-220 .................... 65°C/W Thermal Resistance Junction to Case N, 8-Pin Plastic DIP ........................... 60°C/W J, 8-Pin Ceramic DIP .............·.......... , . 40°C/W T, 5-Pln Plastic T0-220 ·...........·.·.......... 5°C/W Operating Junction Temperature ......·.. -55°C to +150°C Storage Temperature ..........·....... -65°C to +150°C Lead Temperature (Soldering, 1OSeconds) ......... 300°C Note 1: Voltages are referenced to ground. Currents are positive into, negative out of, the specified terminals. Note 2: Consult Packaging section of Databook for thermal limitations and considerations ofpackage.
PLCC-20 (TOP VIEW) QPackage
L s==~2 1 201e
4
18
5
17
6
16
7
15
8
14
9 10 11 12 13
I I PACKAGE PIN FUNCTIO.N
FUNCTION
PIN
N/C
1-3
Al.ARM DELAY
il
ALARM OUTPUT
5
+VIN
6
GND
7
N/C
8-13
PTAT+
14
PTAT-
15
2.5V REFERENCE 16
2.5V REFERENCE 17
ALARM
18
THRESHOLD SET
N/C
19-20
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TJ = o·c to +100°c for the
UC3730, -25°C to + 1oo·c for the UC2730 and -55°C to +125·c for the uc1730,
+VIN=+ 5V, and PTAT- = OV. TA= TJ.
PARAMETERS
TEST CONDITIONS
MIN TYP MAX UNITS
INPUT SUPPLY
Supply Current
+VIN=35V
+VIN=5V
REFERENCE
Output Voltage
TJ=25°C
Load Regulation
Over Temperature
o lour= to 250mA
Line R~ulation
+VIN = 5 to 25V
TEMPERATURE COMPARATOR
Temperature Comparator Threshold at 300°K (26.85°C), Nominally 5mVfK, V1NPUT H_!9._h to Low
Temperature Error
Threshold Line R~ulation
+VIN= 5 to 25V
Temperature Linearity
Note2
Threshold Hysteresis
l~ut Bias Current
VINPUT at 1.5V
Max Output Current
Vour:1V
Output Sat Voltage
IOUT = 100µA
2.8 4.0 mA 2.3 3.5 mA
2.475 2.5 2.525 v
2.46
2.54 v
8.0 25 mV
1.0 5.0 mV
1.475 1.50 1.525 v
-10
10 ·c
0.005 0.02 %N
2.0 5.0 ·c
3.0 8.0 15 mV
-0.5 -0.1
~
1.2 3.0
mA
v 0.05 0.25
7-56
UC1730
UC2730
UC3730
ELECTRICAL
Unless otherwise stated, these specifications apply for TJ = o·c to+1OO°C for the UC3730,
CHARACTERISTICS (cont): -25°Cto + 100°Cforthe UC2730 and-55°Cto +125°Cforthe UC1730, +VIN=+ 5V, and
PTAT- = OV. TA= TJ.
PARAMETERS
TEST CONDITIONS
TEMPERATURE COMPARATOR (cont.)
O~ut Leakl!!l._e Current
Vour = 1V
PTAT BUFFER(8-Pin N, or J Version Only)
Output Voltage
at 300°KJ_26.85°CJ, Nominal_ly_5mVfK
In 10X Conflg. +VIN= 25V
Temperature Error
Tem_.2_erature Linear~ (Note 2)
Line REl!l_ulation
+VIN= 5 to 25V
Load RE19_ulation
lour= Oto 2mA
Dropout Voltage
PTAT +TO +VIN
l'!e_Ut Blas Current at PTAT- l~t
ALARM BUFFER COMPARATOR (8-Pin N, or J Version Only)
Threshold VoltageJY!!:!l.
Alarm Del~l'!e_ut Low to H.!9,h
Threshold Hysteresis Voltage
Alarm Delay Voltage > VTH
l'!e_ut Blas Current
Alarm Del~Voltage < VTH
Max O~ut Current
Vour = 1V
Output Sat Voltage
IOUT=3mA
Output Leakage
VoUT=35V
Note 2: This parameter is guaranteed by design and Is not tested In production.
MIN TVP MAX UNIT
0.01 1.0 µA
v 1.460 1.50 1.54
v 14.6 15 15.4
-12
12 ·c
·c 2.0 5.0
0.02 0.04 %N
1.0 3.0 mV
1.9 2.5
v
-3.0 -1.0
µA
1.1
1.2 1.3
v
100 250 mV
0.1 0.5 µA
7.0 15
mA
v 0.25 0.45
0.1 2.0 µA
APPLICATIONS AND OPERATION INFORMATION Scaling the PTAT Output (8 Pin Version Only)
----,
I
PTAT SOURCE
5mV/°K
1 - - . - 0 VOUT R1
R2
Vour-5x(t~mV/°K
(Recommended Range for R1 Is 2k to 41<)
< 500
.§.
E 400
~
::I
0
300
'a5. 200
'5 0 100
wLL
~
0 0
5 10 15 20 25 30 35 VIN (V)
VREF Maximum Output Current vs Input Supply
u 110 ~~~~~~J.~I~~~~·
100 ~
UC3730N ~+---1--1
., 90 T~NAMBIEN.2T1°TCE(M30P0EKR)ATURE
i 80
~\w ,...,
r--1--11--1-1
i ~
i!?
701--t--t--l--lf--:ir--l"""r"-":t--l---4+--I
60
so~f'..."d--+--+--+--+--+--+--+--+-~
N ~ 40
PD·500mW
:i 30~
~ 20 I '- f'D· 50mW
~· 10.__,__,__..__..__.._.._.._..._....__.
0 200 400 600 800 1000 100 300 500 700 900
Airflow (FT/MIN)
Junction Temperature Rise vs Airflow UC3730N (SPin Plastic Dip)
7-57
APPLICATIONS AND OPERATION INFORMATION.(Cont.) Setting a Temperature Threshold
-----,
UC1730 I
TEMPERATURE COMPARATOR
R3
UC1730 UC2730 UC3730
Temperature Threshold {°C)
2.5V
R2
- ( 0.005) x R1+R2- 273.15
I I . ____ _JI
C1 (OPTIONAL DELAY CAPACITOR)
DELA v - . 7R3C1
ALARM SIGNAL
Note:For airflow monitoring a power dissipation level can be set with a resistive load, RL, on the reference oulput. PD=(+ lhN-2.5vf/RL.
TEMPERATURE COMPARATOR
Dual Speed Fan Control
uc173o-l
R1
100kQ
R2
R3
.z<..J
CJ 2V Ci)
...J
0a: Iz -
+
0
0
z
OV
<
TL
TH
IL
TEMPERATURE
I I ____ _JI
FAN CONTROL SIGNAL ov-LOW SPEED 2V-HIGH SPEED
TH(°C)= ;.~x R~~2 -273.15
TL{°C)= ;.~x R;:Rx-273.15
R3 Where: RX= R2 >< R2 + R3
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7-58
n nINTEGRATED
~CIRCUITS
-UNITRODE
UC2950
Half-Bridge Bipolar Switch
FEATURES Source or Sink 4.0A Supply Voltage to 35V High-Current Output Diodes Tri-State Operation TTL and CMOS Input Compatibility Thermal Shutdown Protection 300kHz Operation Low-Cost T0-220 Package
DESCRIPTION
This device is a monolithic integrated circuit designed to provide high-current switching with low saturation voltages when activated by low-level logic signals. Source and sink switches may be independently activated without regard to timing as a built-in interlock will keep the sink off if the source is on.
This driver has the high current capability to drive large capacitive loads with fast rise and fall times; but with high-speed internal flyback diodes, it is also ideal for inductive loads. Two UC2950S can be used together to form a full bridge, bipolar motor driver compatible with high frequency chopper current control.
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage Range, Ve .................................... 8V to 35V Output Voltage Range, Vo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -3.0V to Vc+3V Input Voltage Range, VIN ..........·.··...·............... -0.3Vto +7.0V Peak Output Current (100 ms, 10% DC) ............................ ±4.0A Continuous Output Current. ...................................... ±2.0A Power Dissipation with Heat Sink................................... 15W Power Dissipation in Free Air ....................................... 2W Operating Temperature Range, TA ....................... -20°c to +100°c Storage Temperature Range, Ts ......................... -55°C to +125°C
Note 1: Consult Packaging section ofdatabook for thermal limitations and considerations ofpackage.
CONNECTION DIAGRAM
5-PIN T0-220 (TOP VIEW)
TPackage 5
4
0
3
2
1
SIMPLIFIED SCHEMATIC
Sink Drive Output Ground Source Drive Supply Ve
TRUTH TABLE
Source Drive Pln2
Low Low High HJg_h
Sink Drive Pln5
Low High Low H_!g_h
Output Pln4
Low Off High H.![h
Note: With no load, output voltage will be HIGH in the OFF state.
5V
Power to Internal Logic
. 5V Re ulator
Source Input
Thermal Shutdown
Sink Input
5/93 7-59
UC2950
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, Ve = 35V, TA= -2o·c to+1oooc, V1L ·~· o.av, V1H = 2.4V
for either i~ut TA =TJ.
PARAMETERS OujR_ut Leaka_g_e to Ve
TEST CONDmONS Oll!l!_utOff
MIN TYP...:J MAX UNITS 20 500 uA
Output Leak@ll.e to Ground
OujRutOff
-200 -500 _11A_
Output Sink Saturation Output Source Saturation
VOL, IL = 2.0A llYf:-Vo!:h_IL = -2.0A
1.2 I 2.0 .V
1.2 2.0
v
Sink Diode Forward Voltage
ID=-2.0A
1:4 2.0
v
Source Diode Forward VoltaJl_e
ID=2.0A
1.4 2.0
v
Input Current
Either l~t V1 = 5V Either ll'IQ_ut VI = OV
20 100 ~ -1.0 -1.6 mA
Supply Current .
OIJ!l!_utH.!9.h
20 30 mA
ou12utL<>w
10 20 mA
SWITCHING CHARACTERISTICS: See Test Circuit. Ve= 12V, AL= so, TA= 25°C. Guaranteed by design; not 100%
tested in production.
PARAMETERS Source Turn-On Del~to1 Source Turn-Off Del~tD2 Sink Tum-On Del~too Sink Tum-Off Del~tD4
Cros.s-Conduction Current Spike When Source and Sink are Activated T~ether
MIN TVP MAX UNITS 300 500 .ns
1.0 2.0 ~
200 4bo ns
100 300 ns
0.6 1.0 µs
SWITCHING TEST CIRCUIT
Ve = +12V
Source Drive
V1H----------Drive VIL--------
Sink Drive
VIH ------+---
I
I
I
VIL--t-----t----
1
Ve-VSAT - ~
Output with
I
RL to Ground
0
1
I
L i
I
-jT01I- -jT02I-
Sink VIH - - , .
r-
Drive
__ _L__j_ __ _
VIL - - 1
1 ---
1
Ve
I
Output with
:
RL to Ve VSAT - - I -
I
r_ I
L :
i
I
I
-jTos1- -jTD41-
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BOID. · MERRIMACK, NH 03054 TEL (803) '424-2410 ·FAX (803) 42+3<!80
7-60
n nINTEGRATED
~CIRCUITS
-UNITRCCE
UC3657
Triple Tri-State Power Driver
FEATURES Operating Supply Voltage to 32V
Load Current Capability to 3A
Built-In Thermal Protection
Clamp Diodes Included for Driving Inductive Loads
25W Multiwatt® Power-Tab Package
Individual Logic Inputs for Each Driver
Master Inhibit Input for Power-Down and Coast
DESCRIPTION The UC3657 triple power driver integrated circuit is well suited to driving three-phase motors, stepper motors, brush motors, inductors, incandescent lamps, resistive loads and long lines with controlled voltage slew rates. The UC3657 features minimum saturation voltage with light loads as well as low saturation voltage for loads in excess of 2A.
Each output contains two clamp diodes to conduct transient currents from inductive loads. The diode to Vee is a fast, low voltage-drop Schottky type, while the diode to ground is a slower P-N junction device.
The UC3657 is completely safe from destruction due to incorrect combinations of logic inputs. For best performance, however, it is recommended that the inputs are driven with logic signals that have transition times faster than 1OOns.
TTLJCMOS Compatible Inputs
ABSOLUTE MAXIMUM RATINGS
Power Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 35V Logic Input Voltage. . . . . . . . . . . . . . . . . . . . . -0.3 to +35V Peak Output Current (each channel)
Non-Repetitive 1OOµs . . . . . . . . . . · . . . . . . . . . . . . . 3A Repetitive, ams on, 2ms off................... 2.5A Continuous ................................ 2A Storage and Junction Temperature ..... -40°C to +150°C Note: Consult Packaging Section of Databook for thermal limitations and considerations of package.
CONNECTION DIAGRAM
(TOPVIEW)
15 ..l'.h._14 '1713
12 11 10 9 8 7 6 5 4
·~""" 1
/
Tab connected to Pin 8
C2 High to Sink C C1 Low to Source C B2 High to Sink B B1 Low to Source B A2 High to Sink A
A1 Low to Source A INH Inhibit GND Ground Vee Positive Supply AO Output A AE Emitter Sense A BO Output B BE Emitter Sense B
CO Output C CE Emitter Sense C
BLOCK DIAGRAM
6/93
7-61
UC3657
ELECTRICAL CHARACTERISTICS
(0°C <TA< 700°C, Vee= 12V unless otherwise noted.) TA= TJ
PARAMETER
CONDITIONS
Ice, O~uts Off
A1,81,C1 =H A2,82,C2=L INH=L
Ice, O~uts H.!9!1
A1, 81, C1 = L A2, 82, C2 = L INH = L
Ice, Outputs LoW
A1, 81, C1, = L A2, 82, C2 = H INH = L
Ice, Chip Inhibited
INH=H
Ice. One Output Low 2A
A2, 82, C2 = H INH = L
Vee Ran~. Operating
Tum-On Threshold
Tum-Off Threshold
Thermal Shutdown Tem~rature
Thermal Recovery Temperature
Logic Input Threshold
Input Low Current; A1, A2, 81, 82, C1, C2 atO.OV
Inhibit Low Current, INH
atO.OV
Input H.!9!1 Current; A1, A2, 81, 82, C1, C2 at3.0V
Inhibit High Current; INH
at3.0V
Output Low Voltage
A2, 82, C2 = H INH = L
100mA
AE, BE, CE Grounded
1A
2A
Output High Voltage, to Vee
A1,81,C1 =L INH=L
100mA
A2, 82,C2=L
1A
2A
Propagation Delay, off-Hjg_h
Test Circuit, DriveA1, 81, orC1
Propagation De~ Off-Low
Test Circuit, Drive A2, 82, or C2
Propagation Deli!}', H.!9!1-Low
Test Circuit, Drive A1+A2,81 + 82, or C1 + C2
Prop~ation Del~ Low-High
Test Circuit, Drive A1 + A2, 81 + 82, or C1 + C2
Propagation Delay, HiglJ-Off
Test Circuit, Drive A1, 81, or C1
Propagation Del~ Low-Off
Test Circuit, Drive A2, 82, or C2
Prop~ation Del~ Low-Inhibit
Test Circuit, Drive INH
Propagation Delay, Inhibit-Low
Test Circuit, Drive INH
Pr~ation Delay, High-Inhibit
Test Circuit, Drive INH
Prop~atlon De~ Inhibit-High
Test Circuit, Drive INH
Output Slew Rate, Output Rising
1OOQ Load to GND; Drive A1 + A2, 81 + 82, or C1 +C2
Output Slew Rate, Output Falling Output Leak~e Current
1OOQ Load to Vee; Drive A1 + A2, 81 + 82, or C1 +C2
INH = H, Vee= 32V, OV < 32V
High-Side Diode 2A D~
INH=H
Low-Side Diode 2A Drop
INH=H
MIN. 8 0.8
TYP. 10 10 40 0.5 100
7.5 7.0 170 160
4
0.2 .07 .37 .7 -.9 -1.2. -1.5 .1 3.2 .25 .51 .4 .35 1.5 .6 2.5 .5 50
MAX. UNITS
25 mA
28 mA
70 mA
5
mA
mA
32 v 8 v
v
·c
·c
2.0 v
20
~
20 !AA
10 .~.
1
mA
.12 .V
.75 v 1.25 v -1.3 v -1.5 v -1.9 v
µs
~ ms
µs
µs
~ µs
~ µs
~ V/µs
50
V/µs
-250
250 ~
1.3
2
v
1.6
3
v
7-62
UC3657
PROPAGATION DELAY TEST CIRCUIT (Connect only one channel at a time.)
+5V +5V +5V
1k
+12V
1kHz
Square Wave 0 to 3V Tr::: Tf
::: 20ns
A1 A2 81 82 C1 C2
INH GND
+12V
1oon _!OOpF
TYPICAL CHARACTERISTICS, 25°C, 12V
Saturation Voltage
0.5 1.0 1.5 2.0 Load Current - (A)
1.6
~ 1.2
w 0
~ 0.8 >
0.4
Diode Voltage
0.5 1.0 1.5 2.0 Diode Current
LOGIC TRUTH TABLE
EQUIVALENT INPUT CIRCUIT
·~ut1
l~ut2
INH
Out~ut
x
x
H
Off
H
L
x
Off
Vee
L
L
L
H!g!l
x
H
L
Low
L means mput voltage < O.BV.
H means input voltage > 2.0V.
Off means output is high impedance.
82,
Low means output is low impedance to "E. · High means output is low impedance to "Vee.·
10k
X means input voltage will not affect the output
(don't care).
7-63
TYPICAL APPLICATIONS
UC3657
Vee
Vee AO
AE
BO
From Controller
BE
co
CE
DC Motor
Vee Select B
UC3657
Select
-----1-------- Clear
This application features a fault latch to detect a shorted wire, stuck rotor, or other problem that can cause current to exceed some threshold. A single sense resistor is used with a voltage comparator to detect this fault. Emitter resistor "A" is used to sense total low-side current, and inhibit all devices in the event that current exceeds a
threshold. Resistor "B" sets the comparator threshold,
and a set-reset flip-flop latches the error signal to prevent
oscillation. Matched RC filters on the comparator inputs allow operation close to threshold with good supply-noise rejection.
To achieve high currents, UC3657 outputs have been paralleled. This is practical within the device current and power ratings, according to the derating specification for the package.
BRUSHLESS MOTOR DRIVER
Logic Inputs
Vee UC3657
Vee A1 A2
81 82
C1 C2
INH GND
--
D-+ D-+
D-+
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7-64
n n INTEGRATED
L::::J CIRCUITS
-uNITRDDE
Bridge Transducer Switch
FEATURES Dual Matched Current Sources
High-gain Differential Sensing Circuit
Wide Common-mode Input Capability
Complementary Digital Open-collector Outputs Externally Programmable Time Delay Optional Output Latch with Reset Built-in Diagnostic Activation Wide Supply Voltage Range High Current Heater Power Source Driver
UC3704 COMPATIBLE SENSORS
SENSOR TYPE
Thermistor Sensistor
Thermocou~e
Semiconductor Photo Voltaic Photo Resistive Strain GaQE!_ Piezoelectric M~neto Resistive Inductive Hall Effect
~acitive
Tem~erature
x x x x
Pressure
x x x
BLOCK DIAGRAM
UC3704
DESCRIPTION This integrated circuit contains a complete signal conditioning system to interface low-level variable impedance transducers to a digital system. A pair of matched, temperature-compensated cur-
rent sources are provided for balanced transducer excitation followed by a precision, high-gain comparator. The output of this comparator can be delayed by a user-selectable duration, after which a second comparator will switch complementary outputs separately activated for diagnostic operation and has an optional latch with external reset capability. An added feature is a high current power source useful as a heater driver in differential tempera-
ture sensing applications. The UC3704 is designed for o·c to
+70°C environments.
ACTIVATION SOURCE
Force
Position Di~acement
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Velo!!!OC
x x
x x x x x
Shock
-- ·-- ·-----··
x x x x
Current Set 2
Comp 2 11 Threshold
QouT Is High When Comp 2 In (+) > Threshold (-)
Gnd 1 t - - - - '
VREF 5 1 - - - - - - - - 1
Current 7 9 Current
Out 1
Out 2
6/93
Delay 1 7-65
UC3704
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (+VIN) .............................. 40V Output Current (each output) ...................... 50 mA Buffer Power Source Current. . . . . . . . . . . . . . . . . . . . . 200mA Comparator 1 Inputs....................... -0.5V to VREF Comparator 2 Inputs........................... 0 to 5.5V Remote Activation and Reset Inputs .............. 0 to 5.5V Power Dissipation at TA= 25°C .................. 1OOOmW Operating Junction Temperature ........... -55°C to+150°C Storage Temperature Range .............. -65°C to +150°C Lead Temperature (Soldering, 10 Seconds) ......... +300°C Note: Unless otherwise specified, all voltages are with respect
to ground (Pin 1). Cuffents are positive into, negative out of the specified terminal. Consult Packaging section ofDatabook for thermal imitations and considerations ofpackage.
CONNECTION DIAGRAM
DIL-16 (TOP VIEW)
J or N Package
Gnd Buffer Set Buffer Drive
+VIN VREF Cur. Set 1 6 Cur. Out 1 7 Cur. Set 2 e
QoUT QOUT Rem. Act. Reset
Comp 2 In 11 Comp 2 Thres.
Delay e Cur. Out 2
ELECTRICAL CHARACTERISTICS: Unle.ss otherwise stated, these specifications apply for TA= o·c to +70°C for the
UC3704: VIH = 15V, TA =TJ.
PARAMETERS Power Inputs
Supply Voltage Range Supply Current Reference Section (with respect to VIN) VREF ValuelVIN - VRE'1 VREF Temperature Coefficient Line Regulation Load Regulation Short Circuit Current Current Source (01 and 02) Output Current (Note 2)
Output Offset Current Comparator One
Input Offset Voltage Input Bias Current Input Offset Current CMRR Voltage gain Delay Current Source Output Rise Time
TEST CONDITIONS
VIN =36V TJ = 25·c Note 1 ti.VIN = 4.2 to 25V Alo= Oto 4mA VIN= 36V, VREF =VIN or Ground Current Set = 1OµA Current Set = 200µA RE6 = RES = 20kQ
VCM =Oto 12V RL>150kQ Overdrive= 10mV, Co= 15pF, TJ = 20°C
MIN TVP MAX UNITS
4.2
36 v
5
10 mA
2.1
2.2 2.3
v
-1
-2
-3 mVl°C
2
10 mV
2
10 mV
±25 mA
-9 -9.5 -10 µA
-180 -195 -200 µA
0
±1
µA
±1
±4 mV
-100 -300 nA
±60 nA
60
70
dB
70
85
dB
34
40
52
µA
2
V/µs
7-66
UC3704
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA= o·c to +70°c for the
UC3704: V1H = 15V, TA=TJ.
PARAMETER Comparator Two (Qour and Qour)
Threshold Voltage Threshold Resistance Input Bias Current Remote Activate Current Reset Current Remote Activate Threshold Reset Threshold Output Saturation
Output Leakage Output Response
TEST CONDITIONS
To Ground
VIN (Pin 12) = 5V
Pin 14 =OV
Pin 13 = OV
TA=25°C
TA=25°C
IOUT= 16mA
IOUT= 50mA
VOUT= 40V
I Comp. Overdrive= 1V 1Turn-on
AL= 5k to VIN
Turn-off
Buffer Set Voltage (V1N -Vs) Drive Current
TJ = 25°C, Is= 1OOmA TJ = 25°C, Rs= 2000, Vo= ov
Note 1: Parameter guaranteed by design, not tested in production.
VIN- VREF- VBE 1.5V
Note 2: Collector output cuffent -
RE
- RE
MIN TYP MAX UNITS
2.2 3.0 3.8
v
14
20
24
kQ
1
3
µA
0.2 0.5 mA
0.2 0.5 mA
0.8 1.2
v
0.8 1.2
v
0.2 0.5
v
0.7 2.0
v
0.2 10 µA
0.4
µs
1.0
µs
1.9 2.1
2.3
v
90 100 120 mA
APPLICATIONS INFORMATION
Sensor Section
The input portion of the UC3704 provides both excitation and sensing for a low-level, variable impedance transducer. This circuitry consists of a pair of highly matched PNP transistors biased for operation as constant current sources followed by a high gain precision comparator.
The reference voltage at the bases of the PNP transistors has a TC to offset the base-emitter voltage variation of these transistors resulting in a constant voltage across the external emitter resistors and correspondingly constant collector currents for balancing, offsetting, or to provide unique temperature characteristic.
With the PNP transistor's optimum current ranging from 10 to 200µA, and the common-mode input voltage of the comparator usable from ground to {VIN - 3V), a wide range of transducer impedance levels is possible.
The sensor comparator has a current source pull-up at the output so that an external capacitor from this point to
ground can be used to provide a programmable delay before reaching the second comparator's threshold. The low-impedance on-state of Comp 1's output provides quick reset of this capacitor. This programmable delay function is useful for providing transient protection by requiring that Comp 1 remain activated for a finite period of time before Comp 2 triggers. Another application is in counting repetitive pulses where a missing pulse will allow Comp 1's output to rise to Comp 2's threshold. This time delay function is:
Dela = Comp 2 Threshold X Co .. 175ms/ F
Y Delay Cu"ent
µ
If hysteresis is desired for Comparator 1, it may be accommodated by applying positive feedback from the delay terminal to the non-inverting input on Pin 7. This will aid in providing oscillation-free transitions for very slowly changing inputs.
7-67
UC3704
APPLICATIONS INFORMATION (cont.) Output Section
The output portion of the UC3704 is basically a second comparator with complimentary, open-collector outputs. This comparator has a built-in, ground-referenced threshold implemented with a high-impedance .current source and resistor so that it may be easily overridden with an external voltage source if desired. Comp 2's input transistors are NPN types which require at least 1V of common-mode voltage for accurate operation and should not see a differential input voltage greater than 6V.
For diagnostic or latching purposes, the output logic is equipped with a Remote Activate and Reset function. These pins have internal pull-ups and are only active when pulled low below a threshold of approximately 1V. A low signal at the Remote Activate Pin causes the outputs to change state in exactly the same manner as if Comp 2's input is raised above the threshold on Pin 11. If Pin 16 is connected to Pin 14, positive feedback results and the outputs will latch once triggered by Comp 2's input.
Pulling the Reset terminal low overrides the Remote Activate Pin releasing the latch.
Reference Buffer
This circuit is designed to provide up to 1OOmA to drive a high current external PNP transistor useful for powering a heater for differential temperature measurements. Care must be taken that power dissipation in 06 does not cause excessive thermal gradients which will degrade the accuracy of the sensing circuitry.
Using a heating element attached to a temperature sensitive resistor, RS1, in one leg of the input bridge implements a flow sensor for either gasses or liquids. As long as there is flow, heat from the element is carried away and the sensor voltage remains below threshold. Using an identical sensor, RS2, without a heater to establish this threshold compensates for the ambient temperature of the flow.
TYPICAL APPLICATION FOR MONITORING LIQUID OR GAS FLOW
+VIN
REB
Ly------- _
V1N @-VR2EFs·-c2.2V
r--- --.i·ll+·--- Heater Buffer
Input Sensor Section
+
---1 Output Section
UNITROOE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD.· MERRIMACK. NH 03054 TEL (603) 424-2410 ·FAX (603) 424·3460
7-68
n nINTEGRATED
~CIRCUITS
-UNITRCDE
Octal Line Driver
FEATURES Eight Single Ended Line Drivers in One Package Meets EIA Standards EIA232EN.28, EIA423A and CCITT V.10/X.26 Single External Resistor Controls Slew Rate Wide Supply Voltage Range Tri-State Outputs Output Short-Circuit Protection
UC5170C
DESCRIPTION The UC5170C is a single-ended octal line driver designed to meet both standard modem control applications (EIA232EN.28), and long line drive applications (EIA423AN.1 O/X.26). The slew rate for all eight drivers is controlled by a single external resistor. The slew rate and output levels in Low Mode are independent of the power variations. Mode selection is easily accomplished by taking the select pins (Ms+ and Ms-) to ground for low output mode (EIA232EN.28 and EIA423AN.10) or to their respective supplies for high mode (EIA232EN.28). High mode should only by used to drive adapters that take power from the control lines, or applications using high threshold receivers.
ABSOLUTE MAXIMUM RATINGS (Note 1)
V+ (Pin 20) ...................................... 15V V- (Pin 11)...................................... -15V
PLCC Power Dissipation, TA= 25°C (Note2) ...... 1000 mW DIP Power Dissipation, TA= 25°C (Note 2) . . . . . . . . 1250 mW Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.5V to +7V Output Voltage ........................... -12Vto+12V
Slew Rate Resistor. . . . . . . . . . . . . . . . . . . . . . . . . . 2k to 1OkQ Storage Temperature . . . . . . . . . . . . . . . . . . . -65°C to +150°C Note 1: All voltages are with respect to ground, pin 18. Note 2: Consult Packaging Section of Databook for thermal limitations and considerations ofpackages.
FUNCTIONAL TABLE
INPUTS
OUTPUTS
HIGH
LOW
EN DATA
EIA-232E(2l
EIA423A+EIA232E
0
0
JY:tl:-3V
5Vto6V
0
1
1
x
_fil-3V H.!g!i Z
-5Vto-6V Hig_h Z
Note 2: Minimum output swings.
CONNECTION DIAGRAMS N PACKAGE (TOP VIEW)
C1 01
Do 9
ENABLE V-
SRA NC NC
6/93
Ms+ GND MsNC NC
Q PACKAGE (TOP VIEW) 81 A1 AoNCHo H1 G1
Go
Fo
C1
F1
DI
E1
- -D-o 9
Eo
ENABLE
V+
MS+
SRA NC NC NC NCMS-GND
7-69
UC5170C
DC ELECTRICAL CHARACTERISTICS: Unless otherwise stated these specifications hold for IV+ I= Iv· I= 1ov,
ov, 0 <TA< +70°C, Ms+= Ms-= RsRA = +10k, TA:TJ.
PARAMETERS
SYMBOL
TEST CONDITIONS
POWER SUPPLY REQUIREMENTS
V+ Ran__ge
V-R~e
V+ SupJ>ly Current V- S~y Current
I+ RL = Infinite En = OV
I·
RL = Infinite En = OV
INPUTS
High Level l'!l!_ut Voltage
VIH
Low Level Input Voltage
VIL
Input Clamp Voltage
VIK 11=·15mA
H!l!_h Level l~t Current Low Level l~ut Current
llH VIH=2.4V Ill VIL=0.4V
OUTPUTS
High Level (Low Mode) Output Voltage VoH VIN=0.8V RL= Inf.
{EIA423AN.10, EIA232EN.28)
En=0.8V RL=3k
RL=450
Low Level (Low Mode) Output Voltage VOL V1N=2.0V RL= Inf.
(EIA423AN.10,EIA232EN.28)
En=0.8V RL=3k
RL=450
Output BalanceJ_EIA423AN.1 Q)_
VBAL RL = 450 VoH · VOL = VBAL
High Level {High Mode) Output Voltage VoH V1N:0,8V RL = Inf., Ms+ = V+, Ms- = V·
{EIA232EN.28)
En=0.8V RL = 3k, MS+ = V+, Ms-= V·
Low Level (High Mode) Output Voltage VOL VIN=2.0V RL = Inf., MS+ = V+, Ms- =V·
(EIA232E, V.28)
En= 0.8V RL = 3k, Ms+ = V+, Ms- = V-
Off-State Output Current
loz En= 2.0V, Vo= '!:.f.V, V+ = 15V, V· = ·15V
Short-Circuit Current
los VIN= OV, En= OV
VIN = 5V, En = OV
MIN
9 -9
2.0
-200
5.0 5.0 4.5 -5.0 ·5.0 -4.5
7.0 7.0 ·7.0 -7.0 -100 25 25
TYP
25 -23
-1.1 0.25 -8.0
5.3 5.3 5.2 -5.3 -5.3 -5.2 0.2 7.6 7.6 -7.7 -7.7
50 40
MAX UNITS
15
v
·15 v
42 mA
-42 mA
v
0.8
v
-1.8 v
40 µA
.~.
6.0
v
6.0
v
6.0
v
-6.0 v
-6.0 v
-6.0 v
0.4
v
10
v
10
v
-10
v
-10
v
100 µA
mA
mA
AC ELECTRICAL CHARACTERISTICS: atjV+I =IV-I = 10V, O<TA< +1o·c, Ms+= Ms-= ov, TA=TJ.
PARAMETERS Output Slew Rate
Output Slew Rate
Propagation Output to High Impedance Propagation High Impedance to Output
SYMBOL
TEST CONDITIONS
tR RsRA=2k
tF
RL = 450, CL = 50pF
tR RSRA= 10k
tF RL = 450, CL = 50pF
tHz RSRA= 10k
tLz RL = 450, CL = 5QeE_
tzH RSRA= 10k
tzL RL = 450, CL = 50pF
MIN 6.65 6.65 1.33 1.33
TYP 9.5 10 1.9 2.2 0.3 0.5 6.0 7.0
MAX UNITS
12.3 v~ 12.3 V/µs 2.45 V/µs 2.45 V/µs 1.0 µs 1.0 µs 15 µs 15 µs
7-70
UC5170C AC PARAMETER TEST CIRCUIT AND WAVEFORMS:....,__ _ _ _ _ _ _ _ _ _ _ _ _ _--,
+10V
.------iENABLE V+ D Ms+ GM> Ms-
INPUT
VEiii
OUTPUT
VII· OV
-10V
OUTPUT
VII - 5V
AC CHARACTERISTICS Driver Slew Rate
12.50
Ill 10.00
~
> .! 7.50
"'IC 5.00
ill .!! U) 1.50
0 0 2.00 4.00 6.00 8.00 10.00 RSRA k!.l
Low utput Driver tR & tF (10-90%) EIA232E + EIA423A Mode
5.00 ~ 4.00
CD
~ 3.00 ~-4--+---17"~of'--i
0 2.00 4.00 6.00 8.00 10.00 RSRA kn
APPLICATION INFORMATION
Slew Rate Programming
Slew rate for the UC5170C is set up by a single external
resistor connected between the SRA pin and ground.
Slew rate adjustments can be approximated by using
: ! the fellowing fermula:
Vlµs-
(RsRAink'2)
The slew rate resistor can vary between 2k and 1Ok which allows slew rates between 10 to 2.2V/µs, respectively. The relationship between slew rate and RSRA is shown in the typical characteristics.
Waveshaping of the output lets the user control the level of interference (near-end crosstalk) that may be coupled to adjacent circuits in an interconnection. The recommended output characteristics fer cable length and data rates can be feund in EIA standard EIA423A
o. +V.1 Approximations of these standards are given by
the fellowing equations:
= Max. Data Rate 300A (For data rates 1k to 1OOk bit/s) Max Cable Length (feeO =100xt (Male: length 4lXXJ feet)
where t is the transition time from 10% to 90% of the output swing in microseconds. For data rates below 1k bit/s t may be up to 300 microseconds.
Output Voltage Programming
The UC5170C has two programmable output modes, either a low voltage mode which meets EIA423A,
o EIA232EN.28N.1 specifications, or the high output
mode which meets the EIA232E, V.28 specifications.
The high output mode provides greater output swings,
av minimum of below and supply rails for driving higher,
attenuated lines. This mode is selected by connecting the mode select pins to their respected supplies, Ms+ to V+ and Ms- to V-.
The low output mode provides a controlled output swing and is accomplished by connecting both mode select pins to ground.
7-71
APPLICATIONS
UC5170C
SPECIFIC LAYOUT NOTES
The UC5170C layout must have bulk bypassing close to the UC5170C, peak slew currents when all 8 drivers slew at once in the same direction is over 500mA. Some applications mount the UC5170C on a bulkhead, or isolated plane for RFl/FCCNDE reasons. If bulk bypassing is not used the -1 o volt supply has gone below 8.5 volts causing the slew rate control circuit to become unstable.
The UC5170C mode control leads must be kept short to prevent the chip from oscillating.
Power Sequence issue, if the +10 volts is applied before
o the -1 volts, the output will oscillate at 1OOkHz; This is a
problem with some terminal designs where the +1Ovolts was derived from the power supply and the.-10 volts was developed off of the flyback, a 500 millisec difference.
system common ground point, with the ground reference tied to the common point to reduce RFIJEMI.
Filter connectors or transzorbs should be used to reduce the RFIJEMI, protecting the system from static (ESD), and electrical overstress (EOS). A filter connector or capacitor will reduce the ESD pulse by 90% typically. A cable dragged across a carpet and connected to a system can easily be charged to over 25,00 volts. This is a metal to
metal contact when the cable is connected to the system (no resistance), currents exceed 80 amps with less than a nanosecond rise time. A transzorb provides two functions, the device capacitance inherently acts as a filter capacitor, and the device clamps the ESD and EOS pulses which would pass through the capacitor and destroy the devices. The recommended transzorbforthe UC5170C is P6KEIOCA.
GENERAL LAYOUT NOTES
*Transzorb is a trademark of General Semiconductor
The drivers and receivers should be mounted close to the Industries.
UNITRODE INTEGRATEO CIRCUITS 7 CONTINENTAL BLVO. · llERRIMACK, NH 03054 TEL (803) 424-2410 · FAX(803) 424-3480
7.72
n nINTEGRATEC
~CIRCUITS
-UNITRODE
Octal Line Driver
UC5171
FEATURES Eight Single-Ended Line Drivers in One Package Digital Selection of High Mode EIA232E/CCl1T V.28 only, and Low Mode EIA232EN.28 & EIA423NCCl1T V10/X26 Single External Resistor Controls Slew Rate Wide Supply Voltage Range Tri-State Outputs Output Short-Circuit Protection Low Power Consumption 2kV ESD Protection on all Pins
CONNECTION DIAGRAMS N PACKAGE (TOP VIEW)
DESCRIPTION The UC5171 is a single-ended octal line driver designed to meet both standard modem control applications (EIA232E/V.28}, and long line drive applications (EIA423A/V.1 O/X.26). The slew rate for all 8 drivers is controlled by a single external resistor. The slew rate and output levels in Low Mode are independent of the power variations.
Mode selection is accomplished by the select pin Ms logic "low'' for low output mode (EIA232EN.28 & EIA423A/V.1 O} or pin Ms logic "high" for high mode (EIA232EN.28}. High mode should only be used to drive adapters that take power from the control lines, or applications using high threshold receivers.
ABSOLUTE MAXIMUM RATINGS (Note 1)
V+ (Pin 20) .................................................. 15V V- (Pin 11) .................................................. -15V PLCC Power Dissipation, TA = 25°C (Note 2) . . . . . . . . . . . . . . . . . . 1000 mW DIP Power Dissipation, TA= 25°C (Note 2) .................... 1250 mW Input Voltage .......................................... -1.5V to +7V Output Voltage ....................................... -12Vto +12V Slew Rate Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2k to 1OkQ Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C Note 1: All voltages are with respect to ground, pin 18. Note 2: Consult Packaging section of Databook for thermal limitations and
considerations ofpackage.
FUNCTIONAL TABLE
INPUTS
OUTPUTS
EN
DATA
EIA-232t;@_
EIA-232E/EIA-423A
0
0
_ffi}_-3V
5Vto 6V
0
1
_(VJ+3V
1 .. x
H!g_h Z
Note 3: Mmtmum output swings.
-5Vto -6V HighZ
Q PACKAGE (TOP VIEW) B1 Al Ao NC Ho HI G1
Bo
Go
Co
Fo
C1
F1
DI
E1
Do
Eo
ENABLE
V+
V-
MS
SRA NC NC NC NC NC GND 6/93
7-73
UC5171
DC ELECTRICAL CHARACTERISTICS: Unless otherwise stated these specifications hold tor IV+ I .;, IV - I= +1fN,
0 <TA< +70°C, Ms "0.8V, RsRA = +10k, TA =TJ.
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
POWER SUPPLY REQUIREMENTS V+ RanJ!e V-R11119_e
9
15 v
-9
-15 v
V+ Suee!}' Current
I+ AL = Infinite Erl= OV
25 42 mA
V- S~Current
I-
AL = Infinite En = OV
-23 -42 mA
INPUTS H_!9..h Level Input Voltage Low Level lni>_utVoltage Input Clam__e_Voltl!ll_e
VIH VIL VIK 11=-15mA
2.0
v
0.8 v
-1.1 -1.8 v
High Level Input Current Low Level Input Current
llH VIH=2.4V llL VIL=0.4V
0.25 40 ~
-200 -8.0
µA
OUTPUTS High Level Output Voltage EIA232E (EIM23A) Low Level Output Voltage EIA232E (EIA423A) O~ut Balance (EIA423A) High Level Oulj>ut Vol~eJ..EIA232El Low Level Output Voltage (EIA232~
VOH VIN=0.8V
AL= Inf.
5.0 5.3 6.0
v
En=0.8V
AL=3k
5.0 5.3 6.0
v
AL= 450
4.5 5.2 6.0
v
VOL VIN=2.0V
AL= Inf.
-5.0 -5.3 -6.0 v
En=0.8V
AL=3k
-5.0 -5.3 -6.0 v
RL=450
-4.5 -5.2 -6.0 v
VBAL AL=450
VoH + VOL = VBAL
0.2 0.4
v
VOH VIN= 0.8V, Ms= 2.0V AL= Inf.
7.0 7.6 10
v
En=O.BV
RL=3k
7.0 7.6 10
v
VOL VIN= 2.0V, Ms= 2.0V AL= Inf.
-7.0 -7.7 -10
v
En=0.8V
AL=3k
-7.0 -7.7 -10
v
Off-State Output Current
loz En = 2.0V, Vo= ~v. Ms= 2.0V
-100
100 µA
Short-Circuit Current
los En=OV
VIN:OV
25
50
mA
VIN=5V
25
40
mA
AC ELECTRICAL CHARACTERISTICS: atlV+I =IV-I = +10V, 0 <TA< +70°C, Ms :so.av, TA=TJ.
PARAMETERS Output Slew Rate
Output Slew Rate
Propagation Output to High Impedance Propagation High Impedance to Output
SYMBOL
TEST CONDITIONS
tR RsRA=2k
IF AL = 450, CL = 50pF
tR RsRA= 10k
IF AL = 450, CL = 50pF
!Hz RsRA= 10k
ILz AL = 450, CL = 50pF
lzH RsRA= 10k
lzL AL = 450, CL = 50pF
MIN 6.65 6.65 1.33 1.33
TYP 9.5 10 1.9 2.2 0.3 0.5 6.0 7.0
MAX UNITS
12.3 V/tJS
12.3 V/tJS
2.45 V/µs
2.45 V/µs
1.0 tJS
1.0 ~
15
JJS
15
tJS
7-74
UC5171
AC PARAMETER TEST CIRCUIT AND WAVEFORMS
.--~~~~~~~~~~~~~~~~~---.
+10V
V+
.-----1ENABi:E D
Ms GND
INPUT VEN
OUTPUT VIN. OV
b -10V
OUTPUT VIN· SV
AC CHARACTERISTICS Driver Slew Rate
Driver tR & tF (10-90%) EIA-423A Mode
12.50
5.00
Ill 10.00
~
>
.,! 7.50
IC 5.00 iii .!!
"' 1.50
0 0 2.00 4.00 6.00 8.00 10.00
RSRA kO
:. 4.00
·~ 3.00
~ 2.00
.".ci,i 1.00
I-
0 0 2.00 4.00 6.00 8.00 10.00
RSRA kO
APPLICATIONS INFORMATION Slew Rate Programming Slew rate for the UC5171 is set up by a single external resistor connected between the SRA pin and ground. Slew rate adjustments can be approximated by using the following formula:
IV'µs = R2S0RA (RsRA in kQ)
The slew rate resistor can vary between 2k and 1OkQ which allows slew rates between 1o to 2.2V/µs, respectively. The relationship between slew rate and RsRA is shown in the typical characteristics.
Waveshaping of the output lets the user control the level of interference (near-end crosstalk) that may be coupled to adjacent circuits in an interconnection. The recommended output characteristics for cable length and data rates can be found in EIA standard EIA-423A. Approximations of these standards are given by the following equations:
Max. Data Rate=300/t (For data rates 1k to 1OOk bit/s)
Max. Cable Length (feet)=100 x t (Max. length 4000 feet)
where tis the transition time from 10% to 90% of the output swing in microseconds. For data rates below 1k bit/s, t may be up to 300 microseconds.
Output Voltage Programming The UC5171 has two programmable output modes, either a low voltage mode which meets EIA-423A operational specifications, or the high output voltage mode which meetS the EIA-232E specifications.
The high output mode provides greater output swings, minimum of 3V below the supply rails, for driving higher, attenuated lines. This mode is selected by connecting the modes select pin, (Ms), to a TTL "low" level. The low output mode provides a controlled output swing and is accomplished by connecting the mode select pin, (Ms), to a TTL "low level."
EIA Standards The UC5171 meets or exceeds the EIA Standards for EIA-232E and EIA-423A modes of operation except under power down conditions. When powered down with the output attached to an active buss, the UC5171 has the potential to load the bus under transient conditions.
7-75
APPLICATIONS
UC5171
, - - - - - - , EIA232E I EIA423A
DATA TRANSMISSION
I
I
+v --, r
I
r VH --,
I
X>-+~~~-V~~L_J..---~~~~-1--~~-I
I VL L_J
TWISTED PAIR
OR FLAT CABLE
I
I
I i.
II~
* TIE TO GROUND
FOR EIA232E
I I I
L ______ _J
UC5171 Specific Layout Notes
The UC5171 layout must have bulk bypassing close to the UC5171, peak slew currents when all 8 drivers slew at once in the same direction is over 500mA. Some applications mount the UC5171 on a bulkhead, or isolated plane for RFl/FCCNDE reasons. If bulk bypassing is not used the -1 O volt supply has gone below 8.5 volts causing the slew rate control circuit to become unstable.
Power sequence issue, if the +1O volts is applied before the -10 volts the output will oscillate at 100kHz. This is a problem with some terminal designs where the +10 volts
was derived from the power supply and the -1 o volts was
developed off of the flyback, a 500 millisec difference.
General Layout Notes
The drivers and receivers should be mounted close to the system common ground point, with the ground reference tied to the common point to reduce RFl/EMI.
Filter connectors or transzorbs should be used to reduce the RFl/EMI, protecting the system from static (ESD), and electrical overstress (EOS). A filter connector or capacitor will reduce the ESD pulse by 90% typically. A cable dragged across a carpet and connected to a system can easily be charged to over 25,000 volts. This is a metal-tometal contact when the cable is connected to the system (no resistance), currents exceed 80 amps with less than a nanosecond rise time. A transzorb provides two functions, the device capacitance inherently acts as a filter capacitor, and the device clamps the ESD and EOS pulses which would pass through the capacitor and destroy the devices. The recommended transzorb for the UC5171 is P6KEIOCA
*Transzorb is a trademark of General Semiconductor Industries.
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. · r.ERRIMACK, NH 03054 TEL (603) 424-2410 · FAX603) 424-3460
7-76
n n L.::::JJ INTEGRATED CIRCUITS
-UNITRCDE
Octal Line Driver
UC5172
FEATURES Eight Single-Ended Line Drivers in One Package
Meets Standards EIA232E/CCITT V.28, and EIA423A/CCITT V.10/X.26
Single External Resistor Controls Slew Rate
Wide Supply Voltage Range
Tri-State Outputs
Output Short-Circuit Protection
Low Power Consumption
2kV ESD Protection on all Pins
EOS on all Output Pins 35V under all Output Conditions
High Current Output for Long Line Drive, Exceeds Standards
CONNECTION DIAGRAMS N PACKAGE (TOP VIEW)
NC Ao
Do 9
ENABLE V-
SRA
NC
NC
Eo
GND NC NC NC
DESCRIPTION The UC5172 is a single-ended octal line driver designed to meet both standard modem control applications (EIA232E/V.28), and long line drive applications (EIA423A/V.10/X.26). The slew rate for all 8 drivers is controlled by a single external resistor. The slew rate and output levels are independent of the power variations.
The UC5172 has high output current, and current balance for long line drive applications. EOS - Output parasitic SCRs powered on and off
are 35V, well above signal levels, allowing protection devices to work.
Inputs are compatible TTL+MOS logic families and are diode protected against negative transients.
FUNCTIONAL TABLE
INPUTS EN 0 0
..1
Note 2: M1mmum output swings.
DATA
0
1
x
OUTPUT EIA232E/EIA423A
5Vto6V -5Vto-6V
H.!9!1 Z
ABSOLUTE MAXIMUM RATINGS (Note 1)
V+ (Pin 20) .................................................. 15V V- (Pin 11) .................................................. -15V PLCC Power Dissipation, TA=25°C (Note 3) ................... 1000 mW DIP Power Dissipation, TA=25°C (Note 3) ..................... 1250 mW Input Voltage .......................................... -1.5V to +7V Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -6V to +6V Slew Rate Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2k to 1OkQ Storage Temperature ............................... -65°C to +150°C Note 1: All voltages are with respect to ground, pin 18. Note 3: Consult Packaging section of Databook for thermal limitations and
considerations ofpackage.
Q PACKAGE {TOP VIEW) 81 A1 Ao NC Ho Hr G1
Bo
Go
Co
Fo
Cr
Fr
DI
Er
Do
Eo
ENABLE
V+
V-
NC
SRANCNCNCNCNCGND
6/93 1-n
UC5172
ov, DC ELECTRICAL CHARACTERISTICS: Unless otherwise stated these specifications hold for IV+I = IV-I = 1
0°C <TA< +70°C, RsRA= +10k, TA:TJ.
PARAMETER POWER SUPPLY REQUIREMENTS
V+ Range V-R~e V+ Su~ Current V- Supply Current INPUTS High-Level I~ Volta__g_e Low-Level Input Voltage Input Clamp Volta~ High Level Input Current Low Level Input Current OUTPUTS High Level Output Voltage EIA232E
(EIA-423~
Low Level Output Voltage EIA232E J_EIA-423A) Output Balance (EIA-423A) Off-State Output Current Short-Circuit Current
Power Off Output Current
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
I+ AL = Infinite En = OV I- AL = Infinite En = OV
9
15 v
-9
-15 v
15
25
mA
-17 -25 mA
V1H V1L VIK li=-15mA llH VIH =2.4V Ill VIL=0.4V
2.0
v
0.8 v
-1.1 -18
v
-2 0.25 40 µA
-5 -8.0
VoH VOL VBAL
VIN=0.8V
AL= Inf.
En =0.8V
AL=3k
AL=450
VIN =2.0V
AL=lnf.
En= o.8V
AL=3k
AL= 450
AL = 450, VoH - Vol = VBAL
5.0
5.3
6.0
v
5.0 5.3 6.0
v
4.5 5.2 6.0
v
-5.0 -5.3 -6.0
v
-5.0 -5.6 -6.0
v
-4.5 -5.4 -6.0
v
0.2 0.4
v
loz En =2.0V, Vo=±6V, V+ = 15V, V-=-15V -100
100 µA
los En=OV
VIN=OV
25 65
mA
VIN=5V
25 70
mA
IPO Vo= ±SV, V+ = V- = OV
-100
100 mA
AC ELECTRICAL CHARACTERISTICS: at IV+I =IV-I= +10V, 0°C <TA< +70°C, TA= TJ.
.. PARAMETER Output Slew Rate
Output Slew Rate
Propagation Output to High Impedance Propagation High Impedance to Output
SYMBOL
TEST CONDITIONS
MIN
tR RsRA=2k
7.6
tF AL = 450, CL = 50pF
7.6
tR RsRA= 10k
1.5
tF AL = 450, CL = 50pF
1.5
tl-lz RsRA= 10k
tLz AL = 450, CL = 50pF
tzH RsRA= 10k
tzL AL = 450, CL = 50pF
TYP 8.5 8.5 1.7 1.7 0.8 0.5 2.0 1.0
MAX UNITS 9.4 V/!JS 9.4 V/!JS 1.9 V!JS 1.9 V/µs 2.0 !AS 2.0 !AS 7.0 ms 7.0 !AS
7-78
AC PARAMETER TEST CIRCUIT AND WAVEFORMS
+10V
~---tEl'iABi:E V+ D
INPUT VE'N
VOIUNT.PUoTv
OUTPUT
-10V
VIN · 5V
UC5172
AC CHARACTERISTICS Driver Slew Rate
12.50
~"' 10.00
>
a!a:s
7.50 5.00
~
.!!!
Cf)
1.50
0 0 2.00 4.00 6.00 8.00 10.00
RSRA kn
Driver tR & tF (10-90%) EIA-423A Mode
5.00
:. 4.00
GI
~ 3.00
c
~ 2.00
"caiisl
i=-
1.00
0 0 2.00 4.00 6.00 8.00 10.00
RSRA kn
APPLICATIONS Slew Rate Programming
Slew rate for the UC5172 is set up by a single external resistor connected between the SRA pin and ground. Slew rate adjustments can be approximated by using the following formula:
V!fi.s = R20 (RSRA in kQ) SRA
The slew rate resistor can vary between 2k and 1OkQ
which allows slew rates between 10 to 2.2V/µs, respectively. The relationship between slew rate and RsRA is shown in the typical characteristics.
Waveshaping of the output lets the user control the level of interference (near-end crosstalk) that may be coupled to adjacent circuits in an interconnection. The recommended output characteristics for cable length and data rates can be found in EIA standard EIA-423A. Approximations of these standards are given by the following equations:
= Max. Data Rate 300/t (For data rates 1k to 1OOk bit/s)
Max. Cable Length (feet) =100 x t (Max. length 4000
feet)
where t is the transition time from 10% to 90% of the output swing in microseconds. For data rates below 1k bit/s t may be up to 300 microseconds.
7-79
APPLICATIONS
UC5172
Specific Layout Notes
The UC5172 layout must have bulk bypassing close to the UC5172; peak slew currents when all 8 drivers slew at once in the same direction is over 500mA. Some applications mount the UC5172 on a bulkhead, or isolated place for RFl/FCCNDE reasons. If bulk bypassing is not used the -1 Ovolt supply has gone below 8.5 volts causing the slew rate control circuit to become unstable.
Power Sequence issue, if the +10 volts is applied before the -10 volts the output will oscillate at 100kHz. This is a
problem with some terminal designs where the +1o volts
was derived from the power supply and the -10 volts was developed off of the flyback, a 500 millisec difference.
General Layout Notes
Filter connectors or transzorbs should be used to reduce the RFl/EMI, protecting the system from static (ESD), and electrical overstress (EOS). A filter connector or capacitor will reduce the ESD pulse by 90% typically. A cable dragged across a carpet and connected to a system can easily be charged to over 25,000 volts. This is a metal to metal contact when the cable is connected to the system (no resistance), currents exceed 80 amps with less than a nanosecond rise time. A transzorb provides two functions, the device capacitance inherently acts as a filter capacitor, and the device clamps the ESD and EOS pulses which would pass through the capacitor and destroy the devices. The recommended transzorb for the UC5172 is P6KEIOCA.
The drivers and receivers should be mounted close to the *Transzorb is a trademark of General Semiconductor system common ground point, with the ground reference Industries. tied to the common point to reduce RFl/EMI.
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. · '-ERRIMACK. NH 03054 TEL (603) 424-2410 ·FAX 603) 424-3460
7-80
n nINTEllRATED
~CIRCUITS
-UNITRDDE
UC5180C
Octal Line Receiver
FEATURES Meets EIA 232E/423A/422A and CCITT V.1 O,V.11, V.28, X.26, X.27
Single +5V Supply--TTL Compatible Outputs
Differential Inputs Withstand± 25V
Low Open Circuit Voltage fOr Improved Failsafe Characteristic
Reduced Supply Current--35 mA Max
Input Noise Filter
Internal Hysteresis
DESCRIPTION
The UC5180C are octal line receivers designed to meet a wide range of digital communications requirements as outlined in EIA standards EIA232E, EIA423A, EIA422A, and CCITT V.10, V.11, V.28, X.26, and X.27. The UC5180C includes an input noise filter and is intended fOr applications employing data rates up to 200 KBPS. A failsafe function allows these devices to "fail" to a known state under a wide variety of fault conditions at the inputs.
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage, Vee · . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Output Sink Current......................................... 50 mA Output Short Circuit Time .. . . .. .. .. .. .. . . . . . . . .. . . . . . . . .. .. .. . 1 Sec Common Mode Input Range . . . . .. .. . . . . . . .. .. .. . . . . . . . . .. .. .. . . 15V Differential Input Range.. .. .. . .. . .. . . .. . . .. .. .. . . . . . . .. .. .. .. . . 25V Failsafe Voltage ......................................... -0.3 to Vee
PLCC Power Dlssipelion, TA= 25°C (Note 2) ................... 1ooo mW
DIP Power Dlsslpetion, TA = 25°C (Note 2) .................... 1200 mW Storage Temperature Range.......................... -65°C to +150°C
Lead Temperature (Soldering, 1oSeconds) ...................... -300°C
Note 1: All voltages are with respect to ground, pin 14. Currents are positive Into, negative out of the specified terminal
Note 2: Consult Packaging Section ofDatabook for thermal /imitations and considerations of package.
CONNECTION DIAGRAMS DIL-28 (TOP VIEW)
PLCC-28 (TOP VIEW)
B- Ao A+ A- Vee Ho H+
A+
Ao
H+
B-
H-
B+
Go
Bo si---~
G+
FS1
G-
C·
FS2
Fo
F+
F·
D+
Eo
Do
E+
GND
E·
B+
H-
Bo
Go
FS1
G+
C·
G-
C+
FS2
Co
Fo
D·
F+
D+ Do GND E· E+ Eo F·
5/93
7-81
UC5180C
DC ELECTRICAL CHARACTERISTICS: Unless otherwise stated these specifications apply for TA= o·c to +70°C, Vee
= 5V ± 5%, lr:!.11_ut Common Mode Ran_g_e :1: 7V, TA=TJ
PARAMETERS
SYMBOL
TEST CONDITIONS
DC I !]Q_ut Resistance Failsafe Output Voltage
Differential Input High Threshold Differential Input Low Threshold l:Jysteresis 0...E_en Circuit lr:!.11_Ut Volt~e Input Capacitance
RIN VOFS
VrH
VTL
VH Vice
C1
3V :s:J V1Nj:s: 25V Inputs Open or Shorted
0 :s: lour :s: 8mA, VFAILSAFE = ov
Together, or One Input Open and One Grounded
Vour = 2.7V, lour= 440 µA
O;i: lour ;i:-400 µA, VFAILSAFE = Vee
o Rs = J_Note ~
(See Figure 1)
Rs = 500J_Note ~
Vour = 0.45V, lour= 440 mA (See Figure 1)
Rs = OJ_Note ~ Rs = 500_Q!ote g)_
Fs = OV or VeeJ_See Fig_ure 1l
UC5180C
MIN MAX
3
7
0.45
2.7
UNITS
kQ
v
50 200 mV 400
-200 -50 mV -400 50 140 mV
75 mV 20 pF
HJg_h Level OU!fillt Vol~e Low Level Output Voltage
Short Circuit Output Current Supply Current Input Current
VcH V10 = 1V lour= - 44~ VOL V10 =-1V
(Note 3) los Note4
Ice 4.75V :s: Vee :s: 5.25V llN Other Inputs Grounded
Note 2: Rs Is a resistor in series with each Input.
Note 3: Measured after 100ms warm up (at 0°C) Note 4: Only 1 output may be shorted at one time
and then only for a maximum of 1 sec.
lour:4mA lour=8mA
VIN= +10V VIN= -10V
2.7
v
0.4 v
0.45
20 100 mA
35 mA 3.25 mA -3.25
Fs=Vcc
Vour Fs·GND
VH1
VH2
VtL 1 VtH1 0 Vt L2 VtH2 VIN
Figure 1. VIL, VtH, VH Definition
AC ELECTRICAL CHARACTERISTICS: Vee= 5V ± 5%, TA= o·c to+ 10°c, Figure 2, TA= TJ.
PARAMETERS
Pr~ation Del~- Low to Hjg!l Pr~ation Del~- Hjg_h to Low
Acc~tance I~ Fr~ue~
R~ectable Input Fr~ue~
SYMBOL
TEST CONDITIONS
= tPLH CL = 5Ql>!-l VIN ± 500mV
lPHL CL= 5~H, VIN= ± 500mV
fA Unused lr:!.11_ut Grounded, VIN = ± 200mV fR Unused lr:!.11_ut Grounded, VIN = :1: 500mV
UC5180C
MIN MAX 550 550 0.1
5.5
UNITS
ns ns MHz MHz
7-82
+0.5V _f1_
-0.SV
Vee IL
UC5180C
Figure 2. AC Test Circuit
VFAILSAFE
APPLICATIONS INFORMATION
Failsafe Operation These devices provide a failsafe operating mode to guard against input fault conditions as defined in EIA422A and EIA423A standards. These fault conditions are (1) drive in power-off condition, (2) receiver not interconnected with driver, (3) open-circuited. interconnecting cable, and (4) short-circuited interconnecting cable. If one of these four fault conditions occurs at the inputs of a receiver, then the output of that receiver is driven to a known logic level. The receiver is programmed by connecting the failsafe input to Vee or ground. A connection to Vee provides a logic "1" output
EIA232EN.28 / EIA423AN.10 DATA TRANSMISSION
I
VH _n__
VL
l+VLJ
1-v
under fault conditions, while a connection to ground provides a logic "O". There are two failsafe pins (Fs1 and Fs2) on the UC5180C where each provides common failsafe control for four receivers. Input Filtering (UC5180C) The UC5180C has input filtering for additional noise rejection. This filtering is a function of both signal level and frequency. For the specified input (5.5 MHz at ±500 mV) the input stage filter attenuates the signal such that the output stage threshold levels are not exceeded and no charge of state occurs at the output.
Vee VHLJ
*TIE TO GROUND FOR EIA232E/V.28
VFAILSAFE
EIA422AN.11 DATA TRANSMISSION
VH n
VL _J L
I I
+V
_n_
-V
~
I
+
I
I +V
;'
L J EIA422A/V.11 LINE
I
-V
DRIVER I
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. · MERRIMACK, NH 03054 TEL (603) 424-2410 ·FAX (603) 424-3410
7-83
Vee VH _f1_
VL
VFAILSAFE
n n L_:=..J
INTEGRATED CIRCUIT·
-UNITRODE
UC5181C
Octal Line Receiver
FEATURES
Meets EIA232E/423A/422A and CCITT V.10, V.11, V.28, X.26, X.27
Single +5V Supply-TTL Compatible Outputs
Differential Inputs withstand ±25V
Low Open Circuit Voltage for Improved Failsafe Characteristic
Reduced Supply Current---35mA Max
Internal Hysteresis
DESCRIPTION
The UC5181C are octal line receivers designed to meet a wide range of digital communications requirements as outlined in EIA standards EIA232E, EIA422A, EIA423A and CCITT V.10, V.11, V.28, X.26, and X.27. The UC5181 C is similar to the UC5180C, but without the input filtering. Thus, it covers the entire range of data rates up to 1OMBPS. A failsafe function allows these devices to "fail" to a known state under a wide variety of fault conditions. at the inputs.
ABSOLUTE MAXIMUM RATINGS (Note 1}
Supply Voltage, Vee .·.......·...·........................·..... 7V Output Sink Current. . . . . . · . . . · . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA Output Short Circuit Time . . . . . . . . . . . . . . . . . . . . . · . . . . . . . . . . . . . . . 1 Sec Common Mode Input Range ..................................... 15V Differential Input Range .......··...·....................··..... 25V Failsafe Voltage...................·...·...··...·.......· -0.3 to Vee PLCC Power Dissipation, TA=25° C (Note 2} .......···..··..... 1000 mW DIP Power Dissipation, TA=25° C (Note 2} ..........·..·...··.. 1200 mW Storage Temperature Range . . . . . . . . . . . . . . . · . . . . . . . . -65°Cto+150° C Lead Temperature (Soldering, 10 seconds} ........··..·.......·. -300° C Note 1: All voltages are with respect to ground, pin 14. Cu"ents are positive in,
negative out of the specified terminal.
Note 2: Consult packaging section ofDatabook for thermal limitations and considerations ofpackage.
CONNECTION DIAGRAMS DIL-28 (TOP VIEW)
PLCC-28 (TOP VIEW)
A-
D+ Do
GN)
B· Ao A+ A· Vee Ho H+ Vee
Ho
H+
H-
B+
H-
Go
Bo
Go
G+
FS1
G+
G-
C-
G·
FS2
Fo
C+
FS2
F+
Co
Fo
F·
D-
F+
Eo
E+
E·
D+ Do GND E- E+ Eo F·
5/93
7-84
UC5181C
DC ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA= 0°c to +70°C; Vee
= 5V ±5%, Input Common Mode Range :7V, TA=TJ.
PARAMETER
DC ll!ll_ut Resistance Failsafe Output Voltage
SYMBOL
TEST CONDITIONS
RIN VOFS
3V "lV1Nl"25V Inputs Open or Shorted Together, or One Input Open and One Grounded
O:.:lour:s8mAVFAILSAFE=0V 0:.:lour:.:-400µA, VFAILSAFE=Vcc
UC5181C
MIN MAX
3
7
0.45
2.7
UNITS
kO
v
Differential Input High Threshold Differential Input Low Threshold 1-ly_steresis QQ_en Circuit lr:m!!! Volta~ ll!ll_ut C&Q_acltance H.!g_h Level Out~ Volb!9.e Low Level Output Voltage
Short Circuit Output Current Supply current Input Current
VTL
VTL
VH V1oc
C1 VOH VOL
los
Vour= 0.45V, lour= -440µA (See Figure 1)
Vour = 0.45V, lour = 8 mA (See Figure 1)
Fs=OV or VeeJ_See Fig_ure 1l
Rs= 0J_Note3_l Rs = 500J_Note ~
Rs=O(Note~
Rs= 500J_Note ~
V10 = 1V, lour= ·440 µA VID-= ·1V (Note 4) Note5
iOUT=4mA IOUr=SmA
Ice 4.75V s:Vcc"5.25V IJN Other Inputs Grounded
VIN= +10V VIH = ·10V
50 200 mV
400
-200 -50 mV
-400
45 140 mV
75 mV
20 _.2f
2.7
v
0.4 v
0.45
20 100 mA
35 mA 3.25 mA -3.25
Note 3: Rs is a resistor in series with each input.
Note 4: Measure after 100 ms warm up (at U'C). Note 5: Only 1 output may be shorted at a time and then only for a
maximum of 1 sec.
Note 6: The delays, either IPLH or tPHL, shall not val}' from receiver to receiver by more than 35ns.
Fs=Vcc
Vour Fs-GND
VH2
VIL 1 VtH1 0 VIL2 VIH2 VIN
Figure 1. VTL, VTH,VH Definition
AC ELECTRICAL CHARACTERISTICS: Vcc=5V :5%. TA=0°C to +70°C, Figure 2 TA=TJ.
PARAMETER
SYMBOL
TEST CONDITIONS
Pr~atlon Del~ow to HJg_h Pr~ation Del~h to Low Acc~table l'!E_ut~ue~
tPLH CL=50~H. VIN= :500 mVJ_Note fil. IPHL CL=50~H VIN= :500 mVJ_Note fil.
fA Unused l'!E_ut Grounded, VIN= %200 mV
UC5181C MIN MAX
120 120 5.0
UNITS
ns ns MHz
Vee
IL
+O.SV_fl_
-o.sv
lPLH OUTPUT
Figure 2. AC Test Circuit
VFAILSAFE
7-85
UC5181C
APPLICATIONS INFORMATION
Failsafe Operation These devices provide a failsafe operating mode to guard
against input fault conditions as defined in EIA422A and
EIA423A standards. These fault conditions are (1) driver in power-off condition, (2) receiver not interconnected
with driver, (3) open-circuited ·interconnecting· cable, arid
(4) short-circuited interconnecting cable. If one of these four fault conditions occurs at .the inputs of a receiver,
then the output of that receiver is driven to a known logic level. The receiver is programmed by connecting the failsafe input to Vee or ground. A connection to Vee provides a logic ·1 · output under fault conditions, while a connec-
tion to ground provides a logic ·o·. There are two failsafe
pins (Fs1 and FS2) on the UC5181C where-each.provides common failsafe control for four receivers.
EIA232EN.28 / EIA423A/V.10 DATA TRANSMISSION
VH Sl_
VL
EIA423A/V.10
I
I
l+VLJ I Vee
1-v
I
VHLJ
VL
*TIE TO GROUND FOR EIA232E/V.28
VFAILSAFE
EIA422A/V.11 DATA TRANSMISSION
VH r1 VL _J L
I I
+V
.I1_
-V
~
+
Vee VH .I1_ VL
_vU I +V /f
EIA422A/V.11
LINE
1
DRIVER I
VFAILSAFE
GENERAL LAYOUT NOTES
The drivers and receivers should be mounted close to the system common ground point, with the ground reference tied to the common point to reduce RFl/EMI.
Filter connectors or transzorbs should be used to reduce the RFVEMI, and protecting the system from static (ESD), and electrical overstress (EOS). A filter connector or capacitor will reduce the ESD pulse by 90% typically. A cable dragged across a carpet and connected to a system can easily be charged to over 25,000 volts. This is a metal to metal contact when the cable is connected to the
system (no resistance), currents .exceed 80 amps with less than a nanosecond rise time. A transzorb provides two functions, the.device capacitance inherenUy·acts as a filter capacitor, and the device clamps the ESD and EOS pulses which would pass through the capacitor and destroy the devices. The recommended transzorb for the
c UC5180C and the UC5181 is P6KE22CA.
*Transzorb is a trademark of General Semiconductor
Industries ..
UNITRODE INTEGMrEO CIRCUITS
7 CONTINENTAL Bl.YD. · MERRIMACK, NH 03054 TB.. (603) "24-2410 · FAX (803) "24~480
7-86
n 1L1_L:::::Jj
INTEGRATEC CIRCUITS
-UNITRCDE
UC5601
SCSI Active Terminator
FEATURES Fully monolithic JC solution
Complies with SCSI and SCSl-2 standards
Provides active termination for 18 lines
Logic command disconnects all terminating resistors
· Low supply current in disconnect mode
· Negative clamping on all signal lines
· Trimmed regulator for accurate termination current
Current limit and thermal shutdown protection
Low dropout voltage regulator
Low thermal resistance surface mount packages
DESCRIPTION The UC5601 provides precision resistive pull-up to a 2.9V reference for all 18 lines in a Small Computer Systems Interface (SCSI) bus cable. The SCSl-2 standard recommends active termination at both ends of every cable segment utilizing single ended drivers and receivers.
Internal circuit trimming is utilized, first to reduce resistor tolerances to +/-3% and then to adjust the regulator's output voltage to insure termination current accuracy of +/- 3%.
The UC5601 provides a disconnect feature which, upon a logic command, disconnects all terminating resistors, and turns off the regulator; greatly reducing standby power.
Other features include negative clamping on all signal lines, 20mA of active negation sink current capability, regulator current limiting, and thermal shutdown protection.
This device is offered in low thermal resistance versions of the industry standard 28 pin wide body SOIC and PLCC, as well as a 24 pin DJL plastic package.
ABSOLUTE MAXIMUM RATINGS
Termpwr Voltage .............................................. + 7V Signal Line Voltage .................................. OV to+ 7V Regulator Output Current ..................................... 1A Power Dissipation ............................................ 2.SW Operating Junction Temperature ... -55°C to+150°C
Storage Temperature ..................... -65°C to+1so0 c
RECOMMENDED OPERATING CONDITIONS Termpwr Voltage ................................ 4.0V to 5.25V Signal Line Voltage .................................. OV to + 3V Disconnect Input Voltage .............. OV to Termpower
BLOCK DIAGRAM
TERMPWR
REGULATOR OUT
TERMPWA
1.5/1.3
12/92
GROUND
~ DISCONNECT (LOW= CONNECT)
7-frl
Circuit Design Patent Pending
CONNECTION DIAGRAM
23
22
c
21
0
2.0
01
19
a>
~
18
z 17
16
10
15
11
14
12
13
UC5601
25
"
28
v
26 25 24 23 22 21 20 10 18 17 16 15
UC5601 SCSI ACTIVE TERMINATOR PINOUT
PIN NAME
TermPower GND' GND' GND' GND' GND' GND' GND' Reg Out Disconnect Termination Line 1 Termination Line 2 Termination Line 3 Termination Lin& 4
OP PKG PIN#
1 12 13 14 15 16 17 18 2 19 20 21 22 23
DWP PKG NPKG PIN# PIN#
PIN NAME
QPPKG DWP PKG N PKG PIN# PIN# PIN#
14
12 Termination Line 5 24
7
24 Termination Line 6 25
8
Termination Una 7 26
9
Termination Line 8 27
20
Termination Line 9 28
21
Termination Line 1o 3
22
Termination Line 11 4
28
Termination Line 12 5
15
13 Termination Line 13 6
1
1 Termination Line 14 7
2
2 Termination Line 15 8
3
3 Termination Line 16 9
4
5 Termination Line 17 10
5
6 Tarminetion Line 18 11
6
7
10
8
11
9
12
10
13
11
16
14
17
15
18
16
19
17
23
18
24
19
25
20
26
22
27
23
·on the QP package pins 12-18 serve as both heatsink, and electrical ground. On the DWP package only pin 28 serves as the electrical ground with pins 7-9, 20-22 as heatsink.
ELECTRICAL CHARACTERISTICS (Unless otheiwise, stated these specifications apply for T, = 0°c TO 10°c. Termpwr = 4.75V Disconnect= OV)
PARAMETER
TEST CONDITIONS
Supply Current Section
Termpwr Supply Current.
All termination lines = Open All termination lines = 0.5V
Power down Mode
Disconnect = o...e..en
Output Section (Termination Lines)
Termination Impedance
A lterm = -5mAto-15mA
Output high voltllgEI Max Output Current
Term...e..wr = 4V (Note~ Vout = 0.5V
Vout = 0.5V, Termpwr = 4V (Note 2)
Output Clamp level
lout =-30mA
Output Leakage OulQUt Caiiacitance Regulator Section
Disconnect = Open, Vin = OV to 5.25V Disconnect = O...e..en J..Note ~
Regulator output voltage
Line Regulation Load Regulation
DrClfl_outvo~e
Short Circuit Current Current Sink Capability Thermal Shutdown Disconnect Section
Termpwr = 4V to 6V
I Reg = oto -400mA
All Termination lines= 0.5V AVout = 100mV Regulator ou!E._ut = OV Vout =3.5V
Disconnect Threshold
Threshold hysterisis
Input Current
Disconnect = OV
NOTE 1:
NOTE 2: NOTE 3:
Unless otherwise specified all voltages are with respect to Ground. Currents are positive into, negative out of the specffied terminal. Measuring each termination line while other 17 are low (0.5V). Guaranteed by design but not 100"/o tested in production.
7-88
MIN
107 2.65 -21.1 -19.8 -0.2
2.80
-450 8
1.3 100
TYP
17 400 100
110 2.9 -21.7 -21.7 -0.05 10 10
2.90 10 20 1.0 -650 20 170
1.5 160 10
MAX
25 430 150
113
-22.4 -22.4 0.1 400
3.00 20 50 1.2
-850
1.7 250 15
UNITS
mA mA uA
Ohms
v
mA mA
v
nA
_£_F
v
mV mV
v
mA mA
·c
v
mV uA
TYPICAL SCSI BUS CONFIGURATION USING THE UC5601
UC5601
TERMPWR
DISCONNECT ~E~~~TOR
UC5601
T18
T1
· ··
Bus Driver
Bus Driver
·
· ·
I ,_,,
SCSI CABLE
TERMPWR
~E~~~TOR DISCONNECT
UC5601
T1
T18
···
Bus Driver
To Recievers
Bus Driver
A LOOK AT THE RESPONSE OF A SCSl-2 CABLE
Figure 1 shows a single line of a SCSI cable. The driver is an open collector type which when asserted pulls low, and when negated the termination resistance serves as the pull-up.
Figure 2 shows a worst case scenario of mid cable deassertion with a close proximity receiver. The voltage Vstep is defined as:
Vstep = Vol + lo zo
Vol = Driver Output Low Voltage lo Current from receiving terminator
ZO = Cable characteristic impedance
lo= Vreg-Vol 110
In the pursuit of higher data rates, sampling could occur during this step portion, therefore it is important to ensure that the step is as high as possible to get the most noise margin. For this reason the UC5601 is trimmed so that the output current (lo) is as close as possible to the SCSI max current spec of 22.4mA. The Termination impedance is initially trimmed on the IC to 110 ohms typical, then the regulator voltage is trimmed for the highest output current to within 22.4mA.
Vreg
10 t11on
J[_ -{:?c~~~~~~ ~-[>-
Driver Figure 1. A Single Lina of a SCSI Cabla
Receiver
v,..,,
Figure 2. A Typical Response of a SCSI Cable
7-89
UC5601
THERMAL DATA (see packaging section of UICC data book formore details on thermal performance) QP package:
Thermal Resistance Junction to Leads, 0jL ................................... 15°C/W Thermal Resistance Junction to Ambient, 0ja ........................ 30°-40°C/W DWP package: Thermal Resistance Junction to Leads, 0jL ................................... 18°C/W Thermal Resistance Junction to Ambient, 0ja ...............,........ 33°-43°C/W .
NOTE: The above numbers for 0jL are maximums for the limiting thermal resistance of the package in a standard mounting configuration. The 0ja numbers are meant to be guidelines for the thermal performance of the device/pc-board system. All of the above numbers assume no ambient airflow.
POWER PLCC PACKAGE (QP SUFFIX)
PACKAGE INFORMATION
DIMENSIONS
SYMBOL INCHES MILLIMETERS
MIN MAX MIN MAX
A
.485 .495 12.32 12.57
A1 .450 .454 11.43 11.53
B
.013 .021 0.33 0.53
c
.170 .180 4.32 4.57
C1 .100 .110 2.54 2.79
D
.050
1.27
E
.026 .032 0.66 0.51
PIN NO. 1 PIN NO. 1 IDENTIFIER
I
D
POWER SOIC PACKAGE (DWP SUFFIX)
DIMENSIONS
SYMBOL INCHES MILLIMETERS
MIN MAX MIN MAX
A
.398 .414 10.11 10.51
A1
.291 .299 7.40 7.60
B
.698 .706 17.73 17.93
c
.096 .104 2.44 2.64
C1 .004 .012 0.10 0.30
E
.050 BSC 1.27 BSC
F
.013 .020 0.33 0.51
F1 .0091 .0125 0.23 0.32
F2 .020 .040 0.61 1.01
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD.· MERRIMACK, NH 03064 TEL 60!).424-2410 ·FAX 603-424-3460
7-90
PIN #1 IDENTIFIER
n n INTEGRATED
~CIRCUITS
-UNITROCE
SCSI Active Terminator
UC5602
PRELIMINARY
FEATURES
DESCRIPTIONS
· Fully Monolitic IC Solution
The UC5602 is a pin compatible version of its predecessor, the UC5601, and
· Complies with SCSI and SCSl-2 Standards
is targeted for high volume applications which require active termination, but not the high performance of the UC5601. The major differences are relaxed output current and termination tolerances, and the absence of low side
· Provides Active Termination for 18 Lines
clamps. The UC5602 provides 18 lines of active termination for a SCSI (Small
· Logic Command Disconnects all
Computers Systems Interface) parallel bus. The SCSl-2 standard recom-
Terminating Resistors
mends active termination at both ends of the cable segment, and SCSl-3 will
Low Supply Current in Disconnect Mode make it a requirement.
· Trimmed Regulator for Accurate Termination Current
The UC5602 provides a disconnect feature which, when opened or driven high, will disconnect all terminating resistors, and disables the regulator; greatly reducing standby power. The output channels remain high imped-
Current Limit and Thermal Shutdown Protection
ance even without Termpwr applied. Internal circuit trimming is utilized, first to trim the impedance to a 7%
Low Dropout Voltage Regulator
tolerance, and then most importantly, to trim the output current to a 7%
·
Low Thermal Resistance Surface Mount Packages
tolerance, as close to the max SCSI spec as possible, which maximizes noise margin in fast SCSI operation.
Other features include thermal shutdown, current limit, and 40mA of active
negation sink current capability.
This device is offered in low thermal resistance versions of the industry standard 28 pin wide body SOIC, PLCC and TQFP (thin quad flat pack).
ABSOLUTE MAXIMUM RATINGS
Termpwr Voltage ............................................. + 7V Signal Line Voltage ................................ OV to+ 7V Regulator Output Current.................................... 1A Power Dissipation ........................................... 2.SW Operating Junction Temperature .. -ss·c to +150°C Storage Temperature .................... -65°C to+1so·c
RECOMMENDED OPERATING CONDITIONS
Termpwr Voltage ...............................4.0V to 5.25V Signal Line Voltage ................................ OV to + 3V Disconnect Input Voltage ............. OV to Termpower
BLOCK DIAGRAM
TERM POWER
0
gGROUND
REGULATOR OUT
~---+-.....-~'~
SIGNAL LINE 1
6/93
DISCONNECT COMPARATOR
SOURCE/SINK POWER DRIVER
7-91
~ SIGNAL LINE 2
I
I
I
I
I
L_,...~
SIGNAL LINE 18
SWITCH CONTROL
Circuit Design Patent Pending
CONNECTION DIAGRAM
UC5602 SCSI ACTIVE TERMINATOR PINOUT
UC5602
2t
c:
0
"'OJ
0
"z '
13
PIN NAME
TermPower GND· GND· GND· GND· GND· GND· GND· Reg Out Disconnect Termination Line 1 Termination Line 2 Termination Line 3 Termination Line 4
OP PKG DWP PKG N PKG
PIN#
PIN# PIN#
PIN NAME
QPPKG DWP PKG N PKG PIN# PIN# PIN#
1
14
12 Termination Line 5
24
6
7
12
7
24 Termination Line 6
25
10
8
13
8
Termination Line 7 26
11
9
14
9
Termination Line 8 27
12
10
15
20
Termination Line 9
28
13
11
16
21
Termination Line 1o 3
16
14
17
22
Termination Line 11 4
17
15
18
28
Termination Line 12 5
18
16
2
15
13 Termination Line 13 6
19
17
19
1
1 Termination Line 14 7
23
18
20
2
2 Termination Line 15 8
24
19
21
3
3 Terrnination Line 16 9
25
20
22
4
5 Termination Line 17 10
26
22
23
5
6 Termination line 18 11
27
23
*On th13 QP package pins 12-18 serve as both heatsink, and electrical ground. On the DWP package only pin 28 serves as the electrical ground with pins 7-9, 20-22 as heatsink.
ELECTRICAL CHARACTERISTICS: Unless otherwise, stated these specifications apply tor TA= 0°c TO 70°C.
Termpwr= 4.75V Disconnect= OV
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNITS
Supply Current Section
Termpwr Supply Current
All termination lines = Open
20
29
mA
All termination lines = 0.5V
400
435
mA
Power Down Mode
Disconnect = C2E_en
100
150
uA
Output Section (Termination Lines)
Termination Impedance
11 lterm = - 5mA to - 15mA TJ=25°C
102
110
118
n
Overtemp
97
129
n
Output High Voltage
Termpwr = 4v, (Note 1)
TJ=25°C
2.6
2.9
3.1
v
Overtemp
2.55
3.2
v
Max Output Current
VouT = 0.5V
TJ=25°C
-19.5
-21.4
-22.4
mA
Overtemp
-18.5
-22.4
mA
Max Output Current
Vour = 0.5V
TJ=25°C
-18.0
-21.5
-22.4
mA
Termpwr = 4V, (Note 2)
Overtemp
-17.0
-22.4
mA
Output Leakage
Disconnect = Open, V1N = OV to 5.25V
10
400
mA
Output Capacitance
Disconnect = Open (Note 3)
10
pF
Regulator Section Regulator Output Voltage Regulator Output Voltage
TJ = 25°C
2.70
2.90
3.10
v
TJ=25°C
2.55
2.9
3.1
v
Overtemp
2.5
3.2
v
Line Regulation
Termpwr = 4V to 6V
10
20
mV
Load Regulation Drop Out voltage
I Reg = 0 to -400mA All Termination Lines= 0.5V 11VouT=100mV
20
50
mV
1.0
1.2
v
Short Circuit Current Current Sink Capability
Regulator Output = OV VouT = 3.5V
-450
-650
-850
mA
20
40
mA
Thermal Shutdown
170
·c
Disconnect Section Disconnect Threshold
1.1
1.4
1.7
v
Threshold hysterisis
100
mV
Input Current
Disconnect = OV
150
200
µA
NOTE 1:
NOTE 2: NOTE3:
Unless otherwise specified all voltages are with respect to Ground. Currents are positive into, negative out of the specified terminal. Measuring.each termination line while other 17 are low (0.5V). Guaranteed by design but not 100% tested in production.
7-92
UC5602
TYPICAL SCSI BUS CONFIGURATION USING THE UC5602
TERMPWR
~2.2µF
DISCONNECT ~~~~~TOR
UC5602
T18
T1
· · ·
~ 4.7µF
4.7µF ~
TERMPWR
~2.2µF
~~~~~TOR DISCONNECT
UC5602
T1
T18
· · ·
To Receivers------.
t - - - To Receivers
Bus Driver
Bus Driver
I · I ·
·
I ,_,,
SCSI CABLE
Bus Driver
Bus Driver
A LOOK ATTHE RESPONSE OF A SCSl-2 CABLE
Figure 1 shows a single line of a SCSI cable. The driver is an open collector type which when asserted pulls low, and when negated the termination resistance serves as the pullup.
Figure 2 shows a worst case scenario of mid cable deassertion with a close proximity receiver. The voltage VSTEP is defined as:
VSTEP = VOL + lo Zo
VOL
Driver Output Low Voltage
lo
Current from receiving terminator
Zo
Cable characteristic impedance
V,og
10~1100
_fl ~~-----~ 1~- [ > -
Driver Figure 1. A Single Una of a SCSI cable
Receiver
V,og . - - - - - .
V,og
v,...,
lo= VREG-VOL
110
In the pursuit of higher data rates, sampling could occur during this step portion, therefore it is important to ensure that the step is as high as possible to get the most noise margin. For this reason the UC5602 is trimmed so that the output current (lo) is as close as possible to the SCSI max current spec of 22.4mA. The Termination impedance is initially trimmed on the IC to 110 ohms typical, then the regulator voltage is trimmed for the highest output current to within 22.4mA.
,___ _ _ _ ____..______________ Vol Figure 2. A Typical Response of a SCSI Cable
7-93
UC5602
THERMAL DATA: (see packaging section of UICC data book for more details on thermal performance) QP package
Thermal Resistance Junction to Leads, OjL ................................... 15°C/W Thermal Resistance Junction to Ambient, 0jA ........................ 30°-40°C/W DWP package: Thermal Resistance Junction to Leads, OjL ................................... 18°C/W Thermal Resistance Junction to Ambient, 0jA ........................ 33°-43°C/W
NOTE: The above numbers for ejL are maximums for the limiting thermal resistance of the package in a standard mounting configuration. The 0jA numbers are meant to be guidelines for the thermal performance of the device/pc-board system. All of the above numbers assume no ambient airflow.
PACKAGE INFORMATION
POWER PLCC PACKAGE (QP SUFFIX)
DIMENSIONS
SYMBOL INCHES MILLIMETERS
MIN MAX MIN MAX
A
.485 .495 12.32 12.57
A1
.450 .454 11.43 11.53
B
.013 .021 _Q,33 0.53
c
.170 .180 4.32 4.57
C1
.100 .110 2.54 2.79
D
.050
1.27
E
.026 .032 0.66 0.51
POWER SOIC PACKAGE (DWP SUFFIX)
DIMENSIONS
SYMBOL INCHES MILLIMETERS
MIN MAX MIN MAX
A
.398 .414 10.11 10.51
A1
.291 .299 7.40 7.60
B
.698 .706 17.73 17.93
c
.096 .104 2.44 2.64
C1
.004 .012 0.10 0.30
E
.050 BSC
1.27 BSC
F
.013 .020 0.33 0.51
F1 .0091 .0125 0.23 0.32
F2
.020 .040 0.61 1.01
PIN #1 IDENTIFIER
7-94
Max Output Current vs Temp.
-20.4
-20.55
ffi -20.7
IC -20.85
~
-21
I-
~ -21.15 -21.3 0
<:x:I! -21.45
·21.6
-21.75 -55
0 25
80
125
TEM'ERA TURE
UC5602
VREF vs Temp.
3.2 3.15
3.1 3.05
3
~ 2.95
> 2.9 2.85 2.8
2.75 2.7
2.65
.55
0 25
80
125
TEMPERATURE
VREF VS VIN
0
1.5
3 4.5
6
7.5
VIN
Output Impedance vs Temp.
135 132 129 w 126
~ 123
I 120 117
I 114 111 108 105 102
.55
0 25
80
125
TEMPERATURE
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD.· MERRIMACK. NH 03054 TEL. (603) 424·2410 ·FAX (603) 424·3460
7-95
n n. INTEGRATED
~CIRCUITS
-UNITRDDE
9-Line SCSI Active Terminator
UC5603 PRELIMINARY
FEATURES Complies with SCSI and SCSl-2 Standards
Provides Active Termination for 9 Lines
Power Regulator Output Stage
-300mA Sourcing Current for Termination
+300mA Sinking Current for Active Negation
6pf Channel Capacitance during Disconnect
0.7V Dropout Voltage Regulator
Logic Command Disconnects all Termination Lines
1OOJAA Supply Current in Disconnect
Mode
Trimmed Termination Current to 3%
Trimmed Impedance to 3%
Negative Clamping on all Signal Lines
Current Limit and Thermal Shutdown Protection
DESCRIPTION The UC5603 provides 9 lines of active termination for a SCSI (Small Computers Systems Interface) parallel bus. The SCSI standard recommends active termination at both ends of the cable segment.
The UC5603 Provides a disconnect feature which, when opened or driven high, will disconnect all terminating resistors, and disables the regulator; greatly reducing standby power. The output channels remain high impedance even without Termpwr applied. A low channel capacitance of 6pf allows units at interim points of the bus to have little to no effect on the signal integrity.
Functionally the UC5603 is similar to its predecessor, the UC5601 - 18 line Active Terminator. Several electrical enhancements were incorporated in the UC5603, such as a sink/source regulator output stage to accommodate all signal lines at +SV, while the regulator remains at its nominal value, reduced channel capacitance to 6pf typical, and as with the UC5601, custom power packages are utilized to allow normal operation at full power conditions (1.2 watts).
Internal circuit trimming is utilized, first to trim the impedance to a 3% tolerance, and then most importantly, to trim the output current to a 3% tolerance, as close to the max SCSI spec as possible, which maximizes noise margin in fast SCSI operation.
Other features include negative clamping on all signal lines to protect external circuitry from latch-up, thermal shutdown and current limit.
Low Thermal Resistance Surface Mount and Zip Packages
BLOCK DIAGRAM
Reg Out
Term Power
Ground "'="
2 Disconnect
"'=" (Low · Connect)
I
I
I
I
I
I
I
I
I
I
LI .......
I
1100
Switch Control
2/93
Circuit Design Patent Pending 7-96
UC5603
ABSOLUTE MAXIMUM RATINGS
TermpwrVoltage .·............................... +7V Signal Line Voltage........................... OV to +7V Regulator Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5A Power Dissipation. .. .. . . . . .. . . . . . . . . . . . . . . .. . . . . .. 2W
so·c Operating Junction Temperature . . . . . . . . . . -55°C to+1 so·c Storage Temperature . . . . . . . . . . . . . . . . . . . -65°C to+1
RECOMMENDED OPERATING CONDITIONS Termpwr Voltage ......................... 3.8V to 5.25V
Signal Line Voltage........................... OV to +5V
Disconnect Input Voltage ................ OV to Termpower
CONNECTION DIAGRAMS
SOIC-16 (TOP VIEW) DP Package
DIL-16 (TOP VIEW) N or J Package
Line 8 Line 5 Reg Out Gnd" Gnd"
Line 6 Line 5 Reg Out N/C N/C Termpwr Line 4 Line 3
*DP package pin 5 seNes as electrical ground; pins 4,
12, 13 serve as heatsink.
PLCC-28 (TOP VIEW) OP Package
L ~ 4 a 2 1 28 21 26
15
25
16
24
17
23
18
22
19
21
110
20
111
19
12 13 14 15 16 17 16
PACKAGE PIN
FUNCTION
FUNCTION PIN
~c
1 -4
R!!!tOUt
5
Line 5
6
Line 6
7
Line 7
8
Line 8
9
Line 9
10
~c
11
Gnd*
~c
12-18 19
Disconnect
20
Line 1
21
Line2
22
Line 3
23
Line 4
24
Term..Q..wr
25
N/C
26-28
* QP package pins 12 - 18 seNe as both heatsink and electri-
cal ground.
ZIP-16 (TOP VIEW) ZPackage
~~
123 - - - - - - - 16
PACKAGE PIN
FUNCTION
FUNCTION PIN
R!!!tOUt
1
Line 5
2
Line 6
3
Line 7
4
Line 8
5
Line 9
6
Gnd
7
Gnd
8
Gnd
9
Gnd
10
Disconnect
11
Line 1
12
Line 2
13
Line 3
14
Line 4
15
Term_Q_wr
16
Note: Drawings are not to scale. 7-ffl
UC5603
ELECTRICAL CHARACTERISTICS (Unless otherwise, stated these specifications apply for TA=0°C to 10°c. Termpwr =
4.75V Disconnect= OV)
PARAMETER
TEST CONDITIONS
Supply Current Section
Term_Q_wr S~Current
All termination lines = O.J!!!n
TermJ>Y'r S~Current
All termination lines = 0.5V
Power Down Mode
Disconnect = QE_en
011!2._ut Section_@rmlnator Line!}_
Terminator lm_Q_edance Out_QUt HJgh Vol~
Item = =5mA to -15mA Term_JJ_wr = 4V_{_Note 2}_
Max Out_JJ_ut Current
VOUT =0.5V
Max OU!Q_ut Current Out_QUt Clam_JJ_ Level
Vout = 0.5V Term_Q_wr = 4VJ_Note 2}_ IOUT= -30mA
Out_.e.ut Leak~
Disconnect= QE_en, Term_Q_wr = OV to 5.25 V
Out_.e.ut ~acitance ~ulator Section
Disconnect = ~nJ_Note fil_
RE19_ulator OutQut VoltllQ_e
~ulator OU!E!Jt Volt~e
All Termination Lines= 5V
Line RE19__ulation
Term_JJ_wr = 4V to 6V
Load RE1Q__ulation
IREG = +100mA to -100mA
Dro_Q_Out Volta..9_e
All Termination Lines = 0.5V
Short Circuit Current Sinkil!!l. Current C~abil!!Y_
VREG =OV VREG = 3.5V
Thermal Shutdown
Thermal Shutdown H~teresis
Disconnect Section
Disconnect Threshold
Threshold l:!Y_steresis
l~tCurrent
Disconnect = OV
Note 1: Unless otherwise specified all voltages are with respect to Ground. Currents are positive into, negative out of the specified terminal. Note 2: Measuring each termination line while other 8 are low (0.5V). Note 3: Guaranteed by design but not 100% tested in production.
MIN TVP MAX UNITS
12 18 mA 200 220 mA 100 150 µA
107 2.7 -21.1 -19.8 -0.2
110 2.9 -21.9 -21.9 -0.05 10 6
113
-22.4 -22.4 0.1 400
10
Ohms
v
mA
mA
v
nA
_Qf
2.8 2.9
3
v
2.8 2.9 3
v
10 20 mV
20 50 mV
0.7
1
v
-200 -400 -600 mA
200 400 600 mA
170
·c
10
·c
1.3 1.5 1.7 v
100 160 250 mV 10 15 µA
THERMAL DATA QP package: (see packaging section of UICC data book for more details on thermal performance)
Thermal Resistance Junction to Leads, 0jL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15°CN/ Thermal Resistance Junction to Ambient, Oja . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30°-40°CN/ DP,Z packages: Thermal Resistance Junction to Leads, 0jL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20°CNJ Thermal Resistance Junction to Ambient, Oja . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°-50°CNJ N packages: Thermal Resistance Junction to Leads, 0jL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50°CN/ Thermal Resistance Junction to Ambient, Oja ............................... 95°-1os°CNJ J packages Thermal Resistance Junction to Leads, 0jL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°CN/ Thermal Resistance Junction to Ambient, Oja ................................ 75°-85°CN/
Note: The above numbers for 0jL are maximums for the limiting termal resistance of the package in a standard mounting configuration. The 0ja numbers are meant to be guidelines for the thermal performance of the device/pc-board system. All of the above numbers assume no ambient airflow.
7-98
PACKAGE INFORMATION POWER PLCC PACKAGE (QP SUFFIX)
SYMBOL
A A1 B
c
C1
DIMENSIONS INCHES MILLIMETERS MIN MAX MIN MAX .485 .495 12.32 12.57 .450 .454 i1 .43 11.53 .013 .021 0.33 0.53 .170 .180 4.32 4.57 .100 .110 2.54 2.79
UC5603
0
POWER SOIC PACKAGE (DP SUFFIX)
DIMENSIONS
INCHES
MILLIMETERS
MIN MAX MIN MAX
A
.228 .244 5.80 6.20
A1
.150 .158 3.80 4.00
B
.386 .393 9.80 9.98
c
.053 .069 1.35 1.75
C1
.004 .009 0.10 0.22
E
.050BSC
1.27 BSC
F
.014 .019 0.36 0.48
ZIG ZAG INLINE PACKAGE (Z SUFFIX)
PIN COUNT
A
a1
a2
D
·
·
E
w
16
9.9 0.386
7.0 0.287
2.9 0.114 19.5 0.768 1.27 0.05 19.05 0.75 2.75 0.108
2.8 0.110
""""~ PLANE
B
i'ICl
I~ I D ·I I~ t-a1 a2
~ .IL e
0.55 (0.022)
1 3
I:e
0.3 (0.012)
~aaa 0a0~~a 0a 0a 0 a 0d
2
n
7-99
APPLICATION INFORMATION
Termpwr
UC5603
~ 4.7J&F
Term wr
Disconnect Termpwr
Dlaoonneot Termpwr
UC5603 Regulator Output
R1
R9
· · ·
Control Bits
l2.2J&F -
UC5601 Regulator Output
R1
R9
· ··
Data Bits
l2.2J&F
To Drivers and Receivers
..........................................................................................................................................
To SCSI Bus Figure 1: Typical Wide SCSI Bua Configurations Utilizing 1 UC5601 and 1 UC5603 Device
Termpwr
Term wr
_ _...,_--tDlaconnect Termpwr
UC5603 Rt
Regulator Output
R9
2.2)1f
Dlaconnect Termpwr
UC5803 ~:?:~rr
Rt
R9
Dlaconnect Termpwr
UC5803 ~:?:~~··r
Rt
R9
Control Biia
Data Biia
Data Biia
To DrlYtll and Receivers
...........................................................................................................................
To SCSI Bua
Figure 2: 'fyplcal Wide SCSI Bua Configurations Utlllzlng 3 UC5603 Devices.
UNlTRODE INTEGRATED CIRCUITS
7 CONTINENTAL BLVD. · MERRIMACK, NH 03054
TEL (803) 424-2410 · FAX (eci:I) 424-:M&O
7-100
n nINTEGRATED
~j CIRCUITS
- UNITRODE
UC5661
Ethernet Coaxial Impedance Monitor
FEATURES Compatible with IEEE 802.3 1OBaseS, 10Base2, and 10BaseT
Preset and Adjustable Data Thresholds
Protects DTE from Spurious Data
Prevents Erroneous Transmission Through Repeaters
Detects Cable Termination Errors
Detects Cable Impedance Errors
DESCRIPTION The UC5661 is a monolithic integrated circuit which functions as an Ethernet Coaxial Impedance Monitor (CIM). This IC is intended to augment the receive (RX) function of IEEE 802.3 Coaxial Transceiver Interface (CTI) circuits. The UC5661 implements a hardware algorithm patented by Digital Equipment Corporation to detect reflections on the Ethernet coaxial cable or twisted pair which are caused by improper network termination or physical medium damage. If a physical problem is detected, the UC5661, whose receiver outputs operate in parallel with the CTI, immediately squelches the receive data, preventing the propagation of invalid network packets. During ordinary operation, the CIM RX outputs enable at the beginning of the data packet preamble, making it transparent to normal CTI functions. The valid data threshold, although preset for thick and thin-wire Ethernets, may be adjusted with the addition of one or two external resistors to meet 1OBaseT requirements.
A secondary system design feature is provided by the UC5661. A the completion of a normal data transmission, the CIM Squelch activates much faster than typical transceiver ICs. The receiver outputs of the UC5661 have been designed to properly terminate the data packet, even with RX data transformers as small as 16uH, possibly allowing for smaller and less expensive system implementations. In these cases, end-of-packet squelch overshoot will be held to less than 1OOmV.
BLOCK DIAGRAM
GND VNEG
VEE 12/92
.------i+ ~
.11
-=- 230mV
7-101
. - - - - - ; 2 PGND '---------; 1 PVEE
ABSOLUTE MAXIMUM RATINGS Supply Voltage (Pins 1 &8) .....................................- 15V Input Voltage (Pin 5) ....................................... +2 to - 1OV Operating Temperature Range UC5661 .........................................................0°c to 70°C Junction Temperature (Note 1) UC5661 .................................................................. 125°C Storage Temperature Range .................. - 55°C to 150°C Lead Temperature (Soldering, 10SEC) .................. 300°C
Note 1: The devices are guaranteed by design to be functional up to the absolute maximum junction temperature.
CONNECTION DIAGRAM
DIL-8 (Top View) J or N Package
UC5661
PVEE PGND 2 RX(+) 3 RX(-) 4
8 VEE 7 VNEG 6 GND 5 RXI
DC Electrlcal Characteristics: Unless otherwise stated, these specifications apply for TA=0°C to 70°C, Vee= PVee = -9.0V, and AL= 500 ohms, TA=TJ.
PARAMETER Supply Current
TEST CONDITIONS Outputs locked or Unlocked, Unloaded
Input Bias Current
RXl.OV
Input Shunt Resistance
RXI = - 2Vto OV
Input Shunt Capacitance
Note 1
Vneg (Valid Data Reference)
Pin 7 =open
RX Output Voltage High (Squelch)
RX Output Voltage Low (Enable)
Output Short Circuit Valid Data Threshold
RX(+)= RX(-)· 9V
Data Reflection Threshold
Note 1: This parameter guaranteed but not tested.
MIN
.200
-980 -1.2 -6 -150 -980 200
TYP 10 2 45 3 -900 -.9 -3.7
-900 230
MAX 20 5
4 -830
0 -3.2
-830 300
UNITS mA uA
Mohm pF mV
v v
mA mV mV
AC Electrlcal Characteristics: Unless otherwise stated, these specifications apply for TA=0°C to 70°C, Vee= PVee = -9.0V, and AL= 500 ohms, TA=TJ.
PARAMETER TEN RX Enable Delay T019 RX Disable Delay
r ·· RX(+) to RX(-) Falling Edge Skew
TFR RX(+) to RX (-) Rising Edge Skew TsaL RX Squelch Delay
TREL RX Release Delay
TEST CONDITIONS see figure 1, 2 see figure 1, 2 see figure 1, 2 see figure 1, 2 see figure 1, 3
see figure 1, 3
MIN TYP MAX 100 400
250 340 475
5
20
5
20
230 2000 500 1150 1500
UNITS ns ns ns ns
ns ns
7-102
"::"
6 2 RX(+) 3
5 RXI
RX(-) 4
8
500'1
500'1
UC5661
-9V FIGURE 1: SWITCHING TEST CIRCUIT
RXI (5MHz)
~-----OV
RX(+) ---+--='---. VoH (-1.2v)
Vneg
- - - - - - - - -1.1V To1s
--------------~~%
VoL (-3.2v)
~3-------------
-
RX(-) ------+--
!+--
TRs
RXI (oV)
TFs
FIGURE 2: INPUT/OUTPUT TIMING DIAGRAM
SM H z RX(+) I RX{-) --~
3.3MHz -1.2V VoH
TREL-
FIGURE 3: SHORT DETECT TIMING DIAGRAM 7-103
0.4V
ov
- - Vneg
-2.6V
-9V
DC TO DC CONVERTER
~ INPUT VOLTAGE FROM AUi CABLE
VEE RXI TXO
RX+ CTI
UC5661 CIM
RX+ 3
_ _ __,PVEE RX- f-4___,1--_
_ _ _8-;VEE
cRX DATA TOAUI CABLE
1 :1
_ - ; -_ _ _2_,PGND _ _,__ _ _6....,GND
500 500 Q Q
FIGURE 4: TYPICAL APPLICATION
UC5661
Figure 4 shows the UC5661 (SDI) being used with a Coaxial Transceiver Interface (CTI) device. The primary function of the SDI is to detect LAN cable shorts (or other impedance
matching problems) and appropriately squelch the RX outputs of the CTI device to prevent the transmission .of corrupted network data. The secondary function of the SDI is to provide improved RX squelching at the completion of a normal data transmission.
To perform the two functions, SDI uses two threshold voltages, Data Reflection Threshold (ORT), and the Valid Data Threshold (VDT). During transmission SDI looks for signal activity above ground and below ground. In the eventthatthe magitude of the input voltage exceeds DAT the outputs will be locked within 2µS and will remain locked for 0.5 to 1.5µS after the last edge below DAT (see figure 3). During signal activity below ground when the signal goes below VDT the outputs will unlock within 400ns. While unlocked, if the input exceeds VDT the outputs will lock within 250 to 475ns relative to the last positive going edge (figure 2).
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD.· MERRIMACK, NH 03054 TEL 603-424-2410 · FAX 603'424·3460
7-104
Packaging Information
8-1
n n INTEGRATED
~CIRCUITS
-UNITRODE
8-2
n n INTEGRATEC
~CIRCUITS
-UNITRODE
Packaging Information
Index
Device Temperature Management . . . . . . . . . . Thermal Characteristics of Surface Mount Packages Package Drawings: 8-Pin Plastic DIP (N) . . . . . . 14-Pin Plastic DIP (N) 16-Pin Plastic DIP (N) 18-Pin Plastic DIP (N) 20-Pin Plastic DIP (N) 24-Pin Plastic DIP (N) 28-Pin Plastic DIP (N) 20-Pin Plastic PLCC (Q) 28-Pin Plastic PLCC (Q) 8-Pin SOIC (D) .. 14-Pin SOIC (D) . 16-Pin SOIC (D) . 16-Pin SOIC (OW) 18-Pin SOIC (OW) 20-Pin SOIC (OW) 24-Pin SOIC (OW) 28-Pin SOIC (OW) 8-Pin Ceramic (J) . 14-Pin Ceramic (J) 16-Pin Ceramic (J) 1.8 Pin Ceramic (J) 24-Pin Ceramic (J) 28-Pin Ceramic (J) 3-Pin T0-3 Metal (K)* . . 3-Pin T0-5 Metal (H)* . . 3-Pin T0-220 Plastic (T) 5-Pin T0-220 Plastic (T) 3-Pin T0-257 Hermetic (G)* . 15-Pin Vertical Multiwatt (V) . 15-Pin Horizontal Multiwatt (VH) . 20-Pin CLCC (L) . . . . . . . . . 28-Pin CLCC (L) . . . . . . . . . 48 Pin TQFP (FQ) . . . . . . . . 16-Pin Sidebraze DIP (SP) 16-Pin Zig-Zag In-Line (Z)
*Consult factory for availability
8-3
Page
8-5 8-8
8-13 8-13 8-13 8-14 8-14 8-14 8-15 8-15 8-15
8-16
8-16 8-16 8-17 8-17 8-17 8-18 8-18 8-18 8-19 8-19 8-19 8-20 8-20 8-20 8-21 8-21 8-21 8-22 8-22 8-22 8-23 8-23 8-23 8-24 8-24
n n INTEGRATED
~CIRCUITS
-UNITROCE
8-4
n n INTEGRATED
~CIRCUITS
-UNITRODE
DEVICE TEMPERATURE MANAGEMENT
All circuit components will dissipate some power while operating and this causes their temperature to rise. Unitrode integrated circuits are designed to handle a considerable range of temperatures, but there are limits. Each part is characterized for a particular temperature range, and the user must see to it that the specified limits are not exceeded. This brief note will give a few hints on how to do this.
With the power turned off, all components of a given circuit will be at the same temperature as the ambient air (assuming, of course, that sufficient time has elapsed for all differences to settle). With the power on, the various components will be warmed up due to their internal power dissipation, until a new state of equilibrium is reached. In this state, some devices may be better than others, and the air temperature will also be higher than before, but for each device it will be true that the amount of heat transfer occurs between the device's case and the air, as well as by conduction through the P.C. board, of heatsink, and from there to the air.
Since all the heat is generated at the silicon chip, it is safe to assume that the chip must be hotter than the IC case; the case must be hotter than the air, or board, or heatsink; and the board or heatsink must be hotter than the air. In short, heat flows downhill, from points of higher temperature to cooler spots.
The rate of heat flow depends on the temperature difference(dT) between the two end points, and also on a quantity called "thermal resistance," which is represented by the symbol e. Heat is a form of energy, and if we choose the joule as the measuring unit we can specify the rate of heat flow in units of joules per second. Therefore,
Rate of heat flow deT Uoules per second]
and since joules per second is the same as watts (W), we have
wdT
e = [°C per watt]
(1)
The quantity 0 defines an important property of materials, with the better thermal conductors having
the lowest e values, Since IC chips must be protected by a variety of packages, it is important for the user to know the thermal resistance e of each type of package, in order to make certain predictions about the behavior of the device in his circuit.
Table 1 shows thermal resistance values for Unitrode IC packages. Thermal resistance junction to case (0jc) is measured by mounting the device to an essentially infinite heat sink. Power lead frame surface mount packages and the batwing DIP conduct the majority of the dissipated power through their leads rather than through the case. For these noted packages, the specified thermal resistance is junction to lead (0jl).
Junction to ambient (0ja) thermal resistance is measured on a 5.0 square inch single sided PC board in still air. Because surface mount devices, including those without power lead frames conduct a significant amount of heat out to the PC board through their leads, the device and PC board must be considered as a system. To indicate this effect, the lower eja given for surface mount packages is for the device mounted on a 5.0 square inch,0.062 inch thick aluminum PC board. The relative behavior of other PC board types and a more detailed discussion on surface mounted devices are covered in more detail in "Thermal Characteristics of Surface Mount Packages" found elsewhere in this section.
You will have noticed that Equation (1) is a sort of "thermal Ohm's law", and that if you know any of the quantities involved, you can calculate the third. With the 0 values given in Table 1, you can always calculate the junction temperature by measuring the net input power to the IC.
Now, consider a device such as the UC3620. The data sheet gives us the following Absolute Maximum Ratings:
Total Power Dissipation
{TCASE + 75°C) . . . . . Storage & Junction Temp
. . . . . . . 25W . 40°C to + 1SO°C
8-5
Packaging Information
UICC PACKAGE RATINGS
PACKAGE
PACKAGE SUFFIX
#PINS
DESCRIPTION
D
8
SO-IC
D DW
14 16
SO-IC
DP
8
SO-IC Power Lead Frame
DP
16
SO-IC Power Lead Frame
DWP
28
SO-IC Power Lead Frame
FQ
48
SQFP
FQP
48
SQFP Power Lead Frame
G
3
T0-257 Non-Isolated Tab
H
3
T0-39 T0-5
IG
3
T0-257 Isolated Tab
J
8
Ceramic D_iQ_
J
14 16
Ceramic D_iQ_
J
18
Ceramic D_iQ_
J
20
Ceramic D_iQ_
J
24 28
Ceramic D_iQ_
K
2
T0-3
L
20
CLCC
L
28
CLCC
N
8
Plastic DjQ_
N
14 16
Plastic D!Q_
N
16
Plastic Batwing DiQ
N
18
Plastic DjQ_
N
20
Plastic DjQ_
N
24 28
a
20
a
28
Plastic DjQ_ PLCC PLCC
QP
28
PLCC Power Lead Frame
R
2
T0-66
SP
16
Ceramic/Metal DjQ_
SP
24
Ceramic/Metal DjQ_
T
3 5
T0-220
V,VH
15
MultiwattlRl
Table 1. Thermal resistance of Umtrode IC packages
Ojc ("C/W)
NIA NIA 22_ill_ 20_(1_} 16fil NIA 25_(11 3.5 20 4.0 26 26 22 22 16
3 18 17 49 46 12fil 40 35 30 NIA NIA 14_ill_ 5 5 3 3 3
Oja ("C/W) (2)
84-160 50-120 40-70 36-58 30-50 76-140 39-100
42 130 130 160 110 88 85 65 35 70 65 110 90 25-50 85 79 58 43-75 40-65 28-50 40 63 40 60 35
Note 1: Specified thermal resistance is Oji (junction to lead) where noted. Note 2: Specified Oja (junction to ambient) is for devices mounted to 5. Osquare inch FR4 PC board with one ounce copper. When resistance range is given, lower values are tor 5.0 square inch aluminum PC board - see text.
8-6
Packaging Information
We can sketch the curve below:
ALLOWABLE POWER DISSP.
25W
slope
=
-25W 75°C
=
3-1-w/°C
-
-1 0JC
ow
o·c so·c 100°c 1so·c
CASE TEMPERATURE
Athough the data sheet does not specifically state the derating factor, we can calculate it from the information given; it is the slope of the line from +75°C + 150°C. In this case, the value is-1/3Wf'C at a case temperatures above +75°C. We note that the junction temperature anywhere along the curve is+150°C, and since this is the maximum allowable temperature, we must take steps to stay within the area below the curve.
The thermal resistance can be found simply taking the reciprocal of the derating factor. In the case of our UC3620 for example:
0JC =3°C/W
which is also the value given in Table 1 for the 15-pin Multiwatt package.
Suppose one intends to use the UC3620 at 2A continuous output current. The data sheet states that the total voltage drop at the output states is 3.6V maximum. At 2A, this will result in an internal dissipation of 7.2W. If the supply voltage is say, 36V, the quiescent current of 55mA maximum gives us an additional 2W of internal heating, for a total of 9.2W. Furthermore, we decide to provide sufficient cooling
to keep the junction temperature at a maximum of 100°C-for increased reliability. Suppose the ambient temperature is to be +50°C maximum. Then, our ~T is 100°C - 50"C = 50°C, and the required thermal resistance from junction to air will be
0CA = 950_2°WC = 5.430 C/W
We know already that 0JC = 3"C/W. Mounting the IC to a heatsink will result in an additional thermal resistance in series. If you decide to use a mica insulator coated with thermal grease, you insert an additional 0.3°C/W (see any Semiconductor Accessories Catalog). Therefore, we need a heatsink with a 0CA value of
0CA = 5.43 -3 -0.3 = 2.13°C/W
This is the maximum value of thermal resistance between mounting surface and air that will keep the junction temperature at or below the chosen value of 1OO"C. We need only to go through a heatsink manufacturer's catalog to find a suitable part or extrusion with the required 0CA value.
8-7
n n LL::::'._j
INTEGRATED CIRCUITS
-UNITROOE
THERMAL CHARACTERISTICS OF SURFACE MOUNT PACKAGES John A. O'Connor
INTRODUCTION
Surface mount packaging continues to expand market share, displacing dual in-line packages (DIPs) at an ever increasing rate. Smaller surface mount devices allow a significant increase in circuit density with a corresponding decrease in system size. Miniaturization is not without penalty however, as thermal management can quickly dominate system packaging design.
With the familiar DIP, the majority of heat is removed through the case. Typically, this is accomplished by convection air currents, although forced air or conduction cooling is often used in more demanding applications. Unlike the DIP however, the majority of heat is removed from surface mount packages through the leads. This means that the PC board design directly affects the thermal capability of surface mounted circuitry. For optimal thermal design, the integrated circuit, the package, and the PC board must be considered as a system.
Many designers use steady-state thermal behavior (thermal resistance) to predict IC junction temperature. While this approach certainly is valid for devices subjected to continuous power dissipation, it often results in an overly conservative design when dissipation varies over time. Generating a model which accounts for transient thermal behavior allows the designer to fully exploit the system's thermal mass. Instantaneous junction temperature can then be calculated, insuring reliability with minimal system size.
THERMAL MODEL
Figure 1 shows the basic model which is expanded for more complex situations. The power dissipated is represented by the current source. Resistance to heat flow is represented by the resistor, and the thermal mass is represented by the capacitor. The analogous thermal units for the current, thermal
resistance, and thermal capacitance are also shown in figure 1. Ground is ambient temperature, so all values are temperature rise above ambient. With more complex systems, it is usually easiest to initially convert to electrical units, analyze the circuit, then convert back to thermal units. This approach allows standard electrical circuit analysis tools and techniques to be used without unnecessary confusion.
A surface mounted device on a PC board can be modeled as in figure 2. Each R-C section roughly
t
l=P (W}
R=RT (°C/W}
I C=CT (J/oC}
".:"
".:"
-
Figure 1. Basic Thermal Model
correlates to the physical system. The first R-C is the device die. The second is the lead frame and package, and the third is the PC board. Other parameters such as the junction to case and case to ambient thermal resistances, are lumped into the three R-C sections. This simplification does cause transient thermal response errors, although normally these errors are small. The additional elements can be broken out separately if greater accuracy is required. Although the physical correlation is far from perfect for the 3 R-C model, the thermal correlation can be very good.
8-8
4 TJUNCTION
R1
C1
t
R2
C2
l!J. TLEAD FRAME 4 TBOARD
R3
AMBIENT
Figure 2: Surface Mounted Device on a PC Board Model
PARAMETER MEASUREMENT The circuit technique shown in figure 3 can be used to evaluate the thermal performance of almost any IC. Device power dissipation must be known and constant. This is achieved with resistive loading for devices such as voltage regulators or amplifiers. Other devices may require additional circuitry to insure constant dissipation.
The change in forward voltage of a diode is typically utilized for temperature measurement, although any temperature dependant parameter could also be used. Ideally, the diode should be close to the output transistors for maximum accuracy. In practice, this is not critical since the temperature drop across the die will only be a few degrees C in a surface mountable IC. During the test, the measurement diode must not have any current other than the fixed bias current. The bias current should be as small as possible to avoid self-heating the diode.
Many devices have a diode intended for forward biased operation in the actual application circuit such as an output stage clamping diode. If such a diode is not available it may be necessary to forward bias a parasitic diode for measurement. While this approach should be considered a last resort, it can yield acceptable data. If a parasitic diode is forward biased, erratic or unspecified behavior is likely, even with low bias currents. Evaluate the test circuit carefully, insuring that dissipation is constant over the measurement temperature range.
Kelvin all connections to avoid interconnect voltage drops. Every 2mV is approximately 1°C, so even small DC offsets can cause significant error. Without any power applied to the device other than the diode bias current, characterize the diode's forward voltage in an oven at several temperatures over the expected operating junction temperature range. The slope of a best-fit line gives the thermal coefficient (Tc) which is used in subsequent calculations.
Vee
Ice
t I
Vee
e------.
IBIAS
4VD 4T=--
Tc
+ 4Vo
-2mV
T C =·c- -
Figure 3: Typical-Thermal Test Circuit
VREF
8-9
Vour
PDISP = Vour (Vcc-VouT) +"vCC 1CC
AL
Thermocouples are used to sense PC board and ambient temperature. PC board temperature is measured as close to the device as possible.
Some parameters are measured directly while others are derived by curve fitting. Junction to PC board, and PC board to ambient thermal resistance are measured by dissipating a constant power. Allow 15 minutes for the temperature to stabilize. The change in diode forward voltage and PC board temperature give the junction to ambient and board to ambient thermal resistance:
Ru-al= tiVo I (Tc PrnsP) R(b-a) = l!..Ts I Po1sp
Note that these resistances are based on change in temperature - ambient is assumed constant for the duration of the test. These values correlate to R1, R2, and R3 by:
R1 + R2 =Ru-a) - R(b-a)
( 1)
R3 = R(b-a)
(2)
The thermal capacitance of the die is measured by applying a pulsed load and recording the junction temperature waveform. Varying the dissipation pulse width allows observation of each capacitance's effect, although only the die's thermal capacitance can be measured directly. A typical 1Oms transient dissipation waveform is shown in figure 4. The thermal time constant of the die is on the order of 30ms. To minimize exponential decay error, the slope of the waveform is measured at (t) = 3ms. The die's thermal capacitance is then:
C1 =Po1sptitTc/l!..Vo
(3)
...~---------ilt-------~~1
transient thermal behavior is critical beyond 10 seconds then additional curves must be taken. The thermal time constant of the PC board can go out to several minutes, so a strip chart recorder or computer based data acquisition system will be required. For most systems, this additional data is unnecessary.
The remaining parameters are determined by curve fitting. Visual comparison of measured versus calculated curves is easily done with a spread sheet program. Measured junction temperature versus time data (4 points per decade is sufficient) is entered into the spread sheet. Junction temperature is then calculated at each point with estimated values for R2 and C2 and C3 using:
T(t) = Po1sp [R1(1-e-V't1) + R2(1-e-thZ)
+ R3(1-ev 't 3J]
(4)
Data presented in the following section will help in estimating initial values. This procedure is iterated until an acceptable curve fit is achieved. C3's value is iterated only if the measured curve goes out to several minutes. Figure 5 is a typical measured and calculated junction temperature versus time curve. A logarithmic time axis aids in curve fitting by spreading data points evenly.
40
35
30
Si' 25 'i 20 a
1' 15
~ E 10 ~
&T(meas) &T(calc)
g 0
0 0
0
0
lime (sec.)
~
Figure 5: Junction Temperature versus Time for FQP48 Package Dissipating 1W.
Typical Data
The preceding technique was used to characterize
2
two devices in nine different packages. Five different
VERTICAL: (1) v0 , 1mv101v (2) PmsP· iw
HORIZONTAL: 2ms101v Figure 4: 10ms Transient Dissipation Waveform
PC board types were also tested to provide relative comparison. This information should be used to help initially determine package, PC board type, and layout. It must be stressed that this typical data
Transient waveforms should also be taken for should not substitute for a rigorous thermal analysis
1OOms, 1s, and 1Os dissipation intervals to generate of the actual application.
an accurate temperature versus time curve. If
8-10
4
0.0045 0.02
45
0.035
1.6
16
24
384
65
4
0.0045 0.02
44
0.070
3.1
15
24
360
63
4
0.011
0.04
34
0.11
3.7
13
24
312
51
2.5
0.008 0.02
13
0.13
1.7
15
24
360
30
3
0.010 0.03
26
0.12
3.1
14
24
336
43
2.5
0.008 0.02
25
0.12
2.9
13
24
312
40
2.5
0.009 0.02
12
0.25
3.0
14
24
336
28
4
0.006 0.02
57
0.07
4.0
15
24
360
76
4
0.005 0.02
21
0.08
1.7
14
25
350
39
Figure. 6 Model values Versus Package Type for 1W Dissipation on Aluminum PC Board.
Figure 6 shows model values and time constants versus package type, mounted on an aluminum PC board [1 ]. Junction to ambient thermal resistance is also shown to indicate overall steady state thermal performance. All data was taken with one watt dissipated. The values that were determined by curve fitting result in a fairly conservative model. Values were chosen which tended predict higher temperature than actually measured where errors could not be eliminated. As indicated, two devices were used for testing. At 7,500 square mils, the UC3730 is representative of the smaller dies typically packaged in 08, 014, and OW 16 packages. The UC3173 is 16,500 square mils, and is typical of the dies packaged in the other larger packages.
Both devices were packaged in the OW16 to isolate the effect of die size. The UC1730's smaller die increase R2 by about 30%. Interpolating between these two data points is difficult since the relationship between die size and thermal resistance is nonlinear. Curves are available which account for this dimensional difference [2], although the actual conditions differ and are more complicated than the configuration used to generate the curves. Fortunately, the resulting error will be small in most applications. Conservatively estimating R2 will minimally impact system size, but if a more accurate value is required the actual device can be characterized on a test PC board.
Figure 7 illustrates the power lead frame's dramatic improvement in thermal performance over standard lead frames by comparing the junction to ambient thermal resistances of the QP28 to the 028, and the FQP48 to the FQ48. Standard lead frames connect the die to the leads thermally through the epoxy molding compound. Power lead frame packages incorporate a single piece for die attachment and ground leads. This uninterrupted, high thermal conductivity path offers a significant improvement over standard lead frames. Occasionally a stiffer but less conductive alloy is use for standard lead frames. The FQ48's poorer thermal performance is partially caused by the lower conductivity alloy.
Printed circuit board design significantly affects the overall thermal performance of the system, particularly with the power lead frame packages. The UC3173 in the OWP28 package was used to
028
QP28
F048
FQP48
Package
Figure 7: Power lead frames significantly reduce thermal 8-11 resistance.
compare PC board thermal performance. Five different PC board types were evaluated with one watt dissipated: 1. Single side 1 oz. copper, 0.062 aluminum 2. Single side 1 oz. copper, 0.062 FR4 epoxy
fiberglass 3. Single side 2 oz. copper, 0.062 FR4 epoxy
fiberglass 4. Four layer (signal, ground, Vee, signal) 1 oz.
copper, 0.031 FR4 epoxy fiberglass 5. Four layer (signal, ground, Vee, signal) 1 oz.
copper, 0.062 FR4 epoxy fiberglass
Figure. 8 Board to ambient thermal resistance and capacitance versus PC board type for DWP28 package dissipating 1W.
The thermal resistance, capacitance, and time constants for the five PC boards are shown in figure 8. The PC board layouts used for testing are shown in figure 9. Only the component side is shown for the four layer boards. The back side, which has 1Omil
4 Layer-Component Side
traces on 50 mil centers to provide a typical amount of interconnect copper, and the Vee plane were unconnected. The inner ground plane is connected to the small component side ground plane through 16 feed-throughs.
As expected, the aluminum PC board's significantly higher specific heat results in nearly an order of magnitude increase in thermal capacitance. Surprisingly the four layer 0.062 board's thermal resistance is nearly as low as the aluminum board's, indicating good heat distribution through the inner planes. Note that although the Vee plane is unconnected, it does help distribute the heat across the board. Conduction or forced air cooling is necessary to fully exploit the aluminum board's capability.
Summary
A method for accurately modeling the thermal behavior of a surface mounted IC has been presented. The model relies on measured data, insuring excellent correlation to the physical system. Typical thermal behavior of nine different packages and five different PC boards were also presented, indicating relative thermal performance differences. Optimum thermal system design is achievable using the techniques and data presented.
References
1. Thermal Clad insulated metal substrates, The Bergquist Company, 5300 Edina Industrial Blvd., Minneapolis, MN 55439, 612-835-2322
2. R. Tummala, E. Rymaszewski, "Microelectronics Packaging Handbook", Van Nostrand Reinhold, 1989, pp173-179
Single Sided
r------~ 2.5"~-------
2.0·
Flgure9. Test PC Board Layouts (SOIC 28DWP)
8-12
n n l:::J INTEGRATED CIRCUITS
-uNITRODE
PACKAGING INFORMATION
8-PIN PLASTIC N PACKAGE SUFFIX
DIMENSIONS
INCHES MILLIMETERS NOTES
MIN MAX MIN MAX
A .245 .260 6.22 6.60
1
B .320 .400 OAO 10.16
1
.- - c
.210
5.33
C1 .125 .150 3.18 3.81
C2 .015 .055 0.38 1.40
2
D ,300 .325 7.62 8.26
3
E
.100 SSC
2.54 BSC
·
F .014 .022 0.35 0.56
F1 .045 .070 1.14 1.78
F2 .008 .014 0.20 0.35
G ,300 .400 7.62 10.16
5
- - H .005
0.13
L .115 .160 2.92 4.06
14-PIN PLASTIC N PACKAGE SUFFIX
DIMENSIONS
INCHES MILLIMETERS NOTES MIN MAX MIN MAX
A .245 .260 6.22 6.60
1
B .745 .775 18.92 19.68
1
c
- - .210
5.33
C1 .125 .150 3.18 3.81
C2 .015 .055 0.36 1.40
2
D .300 .325 7.62 8.26
3
E .100 BSC
2.54 BSC
4
F .014 .022 0.35 0.56 F1 ,045 .070 1.14 1.78
F2 .006 .014 0.20 0.35
G H
.300 ·400
- .005
- 7.62 10.16
0.13
·
L .115 .160 2.92 4.06
16-PIN PLASTIC N PACKAGE SUFFIX
DIMENSIONS
INCHES MILLIMETERS NOTES
MIN MAX MIN MAX
A .245 .260 6.22 6.60
1
B c
- - .745 .775 18.92 19.68
.210
5.33
1
c1 .125 .150 3.18 3.81
C2 .015 .055 0.38 1.40
2
D .300 .325 7.62 8.26
3
E
.100BSC
2.54 esc
·
F .014 .022 0.35 0.56
F1 .045 .070 1.14 1.78
F2 .008 .014 0.20 0.35
G .300 .400 7.62 10.16
5
- - H .005
0.13
L .115 .160 2.92 4.06
INDEX
# 2 L
~
E
&
INDEX
8-13
n n L.!:::::J
INTEGRATED CIRCUITS
-UNITRODE
PACKAGING INFORMATION
18-PIN PLASTIC N PACKAGE SUFFIX
DlllENSIOllS
INCHES ..LUllETERS NOTES
-
llAX lllN llAX
A .245 .21D &22 &IO
1
- .... B .890 .920 22.81 23.39
c - .210
1
.... .... C1 .125 .150 3.18 3.81
C2 .D15 .055
1.40
D .300 .321 7.82
2 3
.... E .1DOBSC 2.54BSC
F .014 .022 0.35
4
.... f1 .045 .070 1.14 1.78
F2 .008 .D14
0.35
G · · .400 7.82 10.11
5
H .005 - 0.13 L .115 .180 2.92 4.08
trnHll BASEPLANE-00 1u u uu u ·EATINGPU··
HHJ!~ ~
u~
H-1-
t -I el--
-i.-·- l--F1 &
20-PIN PLASTIC N PACKAGE SUFFIX
DIMENSIONS
INCHES lllLLllETERS NOTES
lltN MAX MIN MAX
.... .... .... A .245 ......... - B 1.010 1.030 25.85
c - ·210
1 1
C1 .125 .150 3.18 3.81
.... .... C2 .015 .055 0.31 1.40
2
D
.325 7.82
3
E .1ooasc 2.548SC
.... .... F ·014
D.35
.... F1
,070 1.14 1.78
.... .... F2
·014
0.35
.... G .... H
- - .400 7.82 10.11 0.13
4 5
L .115 .180 2.92 4.08
24-PIN PLASTIC N PACKAGE SUFFIX
DlllENSIONS
INCHES lllLUllETERS NOTES
lllN llAX lllN llAX
.... A
.550 12.70 13.87
..... B
1.270 31.24 32.21
- c
.210
5.33
..-.. C1 .125 .150
3.81
.... ........ .... C2 .015
1.40
D
15.24 15.87
1 1
2 3
E F F1 F2 G H L
.1DDBSC .014 .022
.... .870
........ .... .... .014
.... -.175
.... .115 .150
2.54 BSC 0.35 0.51 1.14 1.78
- 15.24 17.15
0.13 4.08
4 5
c:::::::::n-
1. · ·:I + r:= D:=J -~~~ti'LJ
F &
8-14
n nINTEGRATED
L.:::J CIRCUITS
-UNITRODE
PACKAGING INFORMATION
28-PIN PLASTIC N PACKAGE SUFFIX
DIMENSIONS
INCHES MILLIMETERS NOTES MIN MAX MIN llAX
A .500 .550 12.70 13.97
1
- - B 1.380 1A70 35.10 37.34
c
.210
5.33
1
.... .... C1 .125 .150 3.18 3.91
C2 ·015 .055
1AD
D
.825" 15.24 15.87
2 3
E .100 BSC 2.s.tBSC
4
.... F .014 .022 0.35 8.58
F1
.l170 1.14 1.71
F2 G H L
.....008
.005
·115
.014 0.20 0.35
.... - .875 15.24 17.15
- 0.13
.180
4.01
5
c:::::::::::~-
c 1.
·
~1 l
·:::::i
-ts==1 --~~C1 SEATINGPLANE
f
L
H
~t F
&E t
L_G_J
20-PIN PLASTIC PLCC SURFACE MOUNT Q PACKAGE SUFFIX
DIMENSIONS
INCHES MILUllE"FERS NOTES
..N MAX MIN MAX
.... A .315 .395 9.78 10.03
A1 .350 .356 9.88
1
B .013 .021 0.33 0.53
c .170 .180 4.32 4.57
C1 .100 .110 2.54 2.79
..., ... D .D50 BSC 1.27BSC
2
E ...0_[ .... 0.68 0.81
F .020::r -
-
G .2&0::I.aao 7.37 8.38
PINN0.1 PIN NO. 1 IDENTIFIER
28-PIN PLASTIC PLCC SURFACE MOUNT Q PACKAGE SUFFIX
DIMENSIONS
INCHES MIWMETERS NOTES
MIN MAX MIN MAX
A
A1
B
c
.... ..... ........ .485 .485 12.32 12.57
11A3 11.53
.013 .021
0.53
·170 .180
4.57
1
·C1 .100 .110 2.54 2.79
D .OSDBSC 1.27 BSC
2
E F
.D28J .032 o.aaj 0.81
- .02o::I - o.51!
3,4
G .390::r.43o 9.81 10.12
PINN0.1 PIN NO. 1 IDSmRER
J.LJ.L
8-15
n n L.:::::J INTEGRATED CIRCUITS
-UNITRODE
PACKAGING INFORMATION
8-PIN SOIC SURFACE MOUNT D PACKAGE SUFFIX
A
A1 B
c
C1
DIMENSIONS
INCIES lllWMETERS
1111 llAX lllN llAX
.... .221
5.80
.150 .151 5.80 4.00
-.... .... ·1n .1H
.... .D53
1.35 1.75
.... .DIM
0.10 0.23
E .OSOBSC 1.27BSC
F .01u .01· 0.35 OAI
· ...l ·. .. G .807_1.010 0.19 0.2&
H .011_1.035 OA1 0.19
o·
SEATING PLANE
1
=~I Ji Ji fUI -;i
~~~~~ ~
a. [ ],[
J.[
-, Jl" _l J'
l T r~-=r E ~
&.
I---- · -----I
~
)l--;\
14-PIN SOIC SURFACE MOUNT D PACKAGE SUFFIX
DlllENSIONS
A
A1
a c
INCHES Mlt llAX .221
.... -.150 .151
.... .....344
lllWllETERS
........ .... MIN MAX
.... 4.00 8.7&
1.35
1.75
C1 .004 .008
0.10
0.22
E .OSOBSC
F .014 .019
a
H
·
.007
.018
o·
...010
.035
1.27BSC
o.aa I o.41
..I 0.18
0.25
0.41 J_ 0.19
o· T
c::::tJj1
,--~ug
14
&.
=-~·-~4 ~
-
16-PIN SOIC SURFACE MOUNT D PACKAGE SUFFIX
DIMENSIONS
A
A1
a c·
-INCHES
MIN llAX .228
.150 .158
.... ....·38S .aaa
MILLIMETERS
l...l...lN......
M.A..X. ....4.00
1.35
1.75
C1 .004 .009
E .osoesc
0.10
0.22
1.27BSC
F .014_1 .011 G .007_1 .010 H .011_! ....
· D"_l ··
0.38
0.19 OA1
o·
....DAI
..0.25
c:::::tt1
,,~··n
18
=~ -·&.- ~ ~
8-16
n n L..:::_j
INTEGRATED CIRCUITS
-UNITRODE
PACKAGING INFORMATION
16-PIN SOIC SURFACE MOUNT DW PACKAGE SUFFIX
DlllENSIONS
A
A1
8
c
INCHES lllN llAX
- .... .212 .219
.... .403
.007 .104
·WMETERS
lllN
llAX
10.00 10.84
7.42
7.51
....1D.24
10.40 2.84
C1 ·004 .011
E .osoasc
F .11141_ ....
.... G
.012
H .tt·I .oos
· ..1·J_
0.10
0.28
1.278SC
0.31 .l 0.48
.... D.21 .l
.... I O.lt
.. o· .l
18-PIN SOIC SURFACE MOUNT DW PACKAGE SUFFIX
DlllENSIONS
INCHES
lllWUEIERS
A A1
.... .... lllN llAX
.114
.29t
lllN 10.00 7.42
llAX 10.84 7.51
8
c
C1
.453 .412 .ot7 ·104 .004 .011
....11.51
0.10
11.73
....2.14
.... E .osoasc
F .tt4I ..,.
1.278SC 0.48
· .. G .Oot_l .012
H .tts_l .oas o·I
...l 0.21
0.20
0.41_1 O.lt
o·
20-PIN SOIC SURFACE MOUNT DW PACKAGE SUFFIX
DIMENSIONS
INCHES
lllWllE1ERS
lllN llAX
lllN
llAX
.... .... A .184 .419 10.00 10.84
A1
7.42
7.59
.... 8 .&04 .511 12.80 12.99
c .007 ·104
2.84
C1 .004 .011
E .osoasc F .ll14I ..,,
· .. G .ooeI .012
H .011I .oos o·_L
0.10
0.28
1.278SC
o.11 I 0.48
..... 0.23
0.30
0.48 _l_
o·
8·17
INDEXAAEA INDEX AREA INDEX AREA
n nINTEGRATED
~CIRCUl'T'B
-uNITADDE
PACKAGING INFORMATION
24-PIN SOIC SURFACE MOUNT DW PACKAGE SUFFIX
DlllENSIOHS
..... INCHES
lllN MAX
lllWllETERS llAX
A .394 A19 10.DO 10.64
A1
8
c
C1
.... .212 .291
.588
.....0!11 .104 .011
7A2
....15.20
0.10
7.18 15.40
2.64 0.28
E F G H
·
- ..osossc
.014 .019 .012
o·.019 .035
1.27BSC
o.oeI oAt
..I 0.23 0.30
OA8 _l 0.99
.. I
+. . -- !JLILLILILLLlAJj~
.~. _J lfTTTTI UUUUU
l
fr.
ru:
1
i
·Lr.6~~fFu'=f+~4!c J~ . 7
SEATING PLANE
28-PIN SOIC SURFACE MOUNT DW PACKAGE SUFFIX
A
A1
8
c
C1
DlllENlllONS
..- ..... 1111 llAX
lllWllE'IER8 llAX
. A11 1o.ae 1D.64
.2111 .291
... .'IM
7A2 17.71
7.59 17.91
.... .0!11 .1114
2.11
.... .D11 0.10 0.21
E F
..D.,IO.BIS.C.,,
G -1. ....
·H A11J. .DU O" l. r
1.27 BSC
I O.H OA8
.. 0.231. ....
OMJ. D.11 .. l.
1
(:::::::::::Et--
28
fr.
fnnm = 1
i
·
i
ru~i~lFil=nn~~C
B
L~
fJ H 7
SEATING PLANE
8-PIN CERAMIC J PACKAGE SUFFIX
DlllENSICINS
INCHE9
llWllETERS
lllN llAX lllN llAX
0.210 D.120
..... --0.220
0,SIO 0-
0.011 O.DIO
1..:.n.
-
.-...
1.13 UT 10.01 I.DI 1.12
D.01· 0.1111 D.31 0.1111
o.oa D.ODI 1.1' 1.11
0.000 O.Dll D.20 OAI
0.100BSC
o.GD9I -
2.MBSC 0.13 _l_ -
o.111_18.200
rI 1r
3.19_1 I.DI r_l_ 1r
NOTES
7
· · · · · 3
I
·
I T __r..-... _j
J~;l. ~
8-18
n nINTEGRATED
~CIRCUITS
-UNITRDDE
PACKAGING INFORMATION
14-PIN CERAMIC J PACKAGE SUFFIX
DlllENSIOHS
INCHES
lllN llAX
0.2IO 0.320
--0.220
0.310 o.7H 0.200
0.011 0 -
0.1>14 0.021
llWllETERS
lllN llAX
.7..M..
--
1.13 7.87 11.14 1.08
0.38 1.12
0.38 0.11
0.048 0 0.- 0.1>11
0.100BSC
1.14 1.11 0.20 0.41
1.14BSC
o-I 0.111 I 0.200
uaI a.11I 1.08
O"I 1r
O"I 1r
NOTES
7
· ·
3
·
I
·
I
·
16-PIN CERAMIC J PACKAGE SUFFIX
DllENSIONS
INC-
llWllETERS
lllN llAX lllN llAX
0.2IO 0.320
--0.220
0.310 O.llO 0.200
.7..M..
--
1.13 7.87 11.34 1.08
0.011 0 - 0.38 1.12
0.1>14 0.011 0.38 0.11
0 - 0 - 1.18 1.11
0.- 0.1>11 0.20 0.41
- 0.1DOBSC
O.OOI
0.111 l_ 0.200 O" l_ 10"
Z.llBSC o.1a_l -
3.11 J. 1.08 O" l. 10"
NOTES
· · 7
a I
z
·
I I
18-PIN CERAMIC J PACKAGE SUFFIX
DIMENSIONS
INCHES
MILLIMETERS
lllN
llAX MIN
MAX
G.290 0.310 7.37 8.13
0.220
--
0.015
0.310 O.HO G.200 0.080
5.SI 717
--
18.38 5.0I
0.38 1.51
0.014 0.023 G.31 0.58
0.040 0.11115 1.18 1.11
O.OOI 0.018 0.20 0.41
0.100BSC
J 0.005 -
0.125 0.200
o· 15·
::r - 2.S4BSC
0.13
.I 3.18 5.0I
:I o·
15·
NOTES
7
· ·
3 8 2
·
I
·
a. -~] J IT A
liE. . E 0
I CT
l:l. " J
SEATINQPLANE
A
J~ [f
j;l. &,.
8-19
n nINTEGRATED
~CIRCUITS
-UNITRODE
PACKAGING INFORMATION
24-PIN CERAMIC J PACKAGE SUFFIX
DIMENSIONS
INCHES
MN.UMETERS
lllN llAX lllN llAX
O.HO 0.111
-1.180
G.121 0USO G.221
1c.lt 13.De
-2t.t7
....11.11
11.37 1.72
o.cn· o.on o.38 1.40
0.014 0.028 o.38 0.81
0.041 o.on 1.14 1.11
o.ooe o.cne o.ao OM
0.1008SC
o.ooeJ. 0.011
O'0.121.l G.200 .l 15"
2.l&ISC
0.127 . l 1.11 :1.11 . l 1.oe
.,. .l 15"
NOTES
7
· ·
3
·
2
· · ·
28-PIN CERAMIC J PACKAGE SUFFIX
DIMENSIONS
INCHES
lllN llAX
o.eeo 0.&11
O.l70 0 -
-1.380
0.011
1G.221 o.on
0.011 0.028
O.IMI o.on
lllLUllETERS
lllN
,-.-....1....
llAX 11.81 11.37 37.ot
1.72
0.38 1AO
.... 0.3' 0.88
1.1'
o.ooe o.cna 0.10DBSC
o.ooe:I o.on
:r 0.121 G.200 O':r 15"
o.ao 0.48 2.eaasc
.... o.121:I
:r 3.187 I.Ill o-:r 15"
NOTES
7
· ·
3
·
2
· · ·
3-PIN T0-3 METAL* K PACKAGE SUFFIX
DIMENSIONS
INCHES lllU.lllETERS NOlES
A
a c
C1
11111 llAX lllN
.... .... .285 .... .1to .230 ....- - .470 10.12
.050
MAX 7.24 5.84
· 11.94
1.27 ...!..·
D .785 .875 19.43 22.H
E 1.177 1.197 2t.to 30.40
F .lllO .1115 1.52 1.15
G H J K L
.855 .119 .495 .o38 .205
.875 16.84
.... ·171
.505 12.57 D.97
-.225 5.21
17.14 4.47 12.12 1.02 5.72
.. 7
.... .... L1 .420 .4&0 10.17 11.18
II .152 ·1IO
S.·
*Consult factory for avallablllty.
n nINTEGRATED
~CIRCUITS
-UNITRODE
PACKAGING INFORMATION
3-PIN T0-5 METAL* H PACKAGE SUFFIX
DIMENSIONS
INCHES
MILLIMETERS
MIN MAX MIN MAX NOTES
A .335 ,370 8,51
9.40
A1 .305 ,335 7.75 8.51
B .500
- 12.70
-
c
.165 .185
4.19
4.70
0 .250
-
6.35
-
3
01
- .050
-
1.27
3
E
- .040
-
1.02
F
.200 6SC
F1 .1ooesc
5.08 BSC 2.54 BSC
G .028 .034 0.71
0.86
G1 .029 .045 0.74 1.14
4
H .016 .019 0.41
0.48
3
H1 .016 .021 0.41
0.53
3
"
4s·esc
45· esc
3-PIN T0-220 PLASTIC T PACKAGE SUFFIX
DIMENSIONS
INCHES MIN MAX
MILLIMETERS
MIN
MAX
A .500 .562 12.70 14.27
A1
- .250
B .380 .420
....-
6.35
10.66
c
.560 .625
14.23
15.87
C1 .230 .270
5.85
6.85
0
.140 .190
3.56
4.82
01 .045 .055
1.14
1.39
E .020 .045
0.51
1.14
E1 .045 .070
1.14
1.n
F .139 .161
3.53
4.09
G .014 .022
0.36
0.56
H .090 .110
2.29
2.79
H1 .190 .210
4,83
5.33
I
.080 .115
2.04
2.92
5-PIN T0-220 PLASTIC T PACKAGE SUFFIX
DIMENSIONS
INCHES
MILLIMETERS
MIN MAX
MIN
MAX
A .soo .580 12.70 14.73
B .380 .420
9.65
10.67
c
.560 .650 14.22
16.51
C1 .230 .270
5.84
6.86
0 .140 .190
3.56
4.83
01 .045 .055
1.14
1.40
E .020 .045
0.51
1.14
F .139 .161
3.53
4.09
G .014 .022
0.36
0.56
H .057 .OTT
1.45
1.96
H1 .258 .278
6.55
7.06
I
.080 .115
2.03
2.92
*Consult factory for availability.
01 ..----i-D
REFERENCE PLANE
11F·:EATING PLANE
r rc L_
~.I
A
I
L'
I I ,-U---E
·-t_~
8-21
n n INTEGRATED
~CIRCUITS
-UNITRODE
PACKAGING INFORMATION
3-PIN T0-257 HERMETIC *
G PACKAGE SUFFIX
DIMENSIONS
INCHES
MIN MAX
A .645 .665
B A10 .420
c .410 .430
D .190 .200
E
.100 BSC
F .035 .045
G .027 .035
- H
.010
- J
.500
K .115 .121
L .140 .150
M
.120 BSC
MILLIMETERS
MIN MAX
16.38 16.89
10.41
10.62
10.41
10.92
4.83
5.06
.254 BSC
....0.89
1.14
0.89
-
12.70
0.25
-
2.92
3.07
3.56
3.81
3.05 BSC
NOTES
2
DIA. 3
r-:=;
.......- 1 - - - 1 - - - - i c - -. . .
1-:----- -----T__J
'-------ii--'"' J_
I ~~::;;;:-::;;:::;-----a-3G~ J
Lf=1: ~
J~i:::::I
f
M
15-PIN VERTICAL MULTIWATT V PACKAGE SUFFIX
15-PIN HORIZONTAL MULTIWATT VH PACKAGE SUFFIX
DIMENSIONS
INCHES
MILLIMETERS
MIN TYP MIN MAX TVP MAX
·A .413 .417 .783 .787
10.50 10.60 20.10
c .174
4.43 4.50
1A9 1.52 1.54
.... .689
17.40 17.50 17.60
.... .050
0.97 U7 1'7
F .026 .026
0.6' 0.70
Ff G H
H""3''
J
........
.707
.109
.....087
.700
.713 .110 .096
.... . .,,.712 17.48 17.78 20.57
, .719 rn
0.54
20.72
2.65 2.70 2.65
K .213 .219
5.55'
Kl .205 .211
5.50
.150 .151 3,73
3.82
*Consult factory for availability.
'--jr ·11·
1'
8-22
n n INTEGRATED
~CIRCUITS
-UNITRODE
PACKAGING INFORMATION
20-PIN CERAMIC LEADLESS SURFACE MOUNT L PACKAGE SUFFIX
DIMENSIONS
B1
B3 D/E
02/E2 03/E3
L1 L2 L3 N ND/NE
INCHES MINj_MAX .060l.100
J_ .050 .088
.022I .02e ·072 REF.
J_ .006 .022
.342_1 .358 .200 BSC .100 BSC
.045 .055 .045 .055 .075 .003 .015
20 5
.osoesc
MILLIMETERS
MAX
1.52
2.54
1.27
0.56
0.71
1.83 REF .
0.15
0.56
8.69
9.09
s.ae BSC
2.54BSC 9.09
1.40
1.40
1.90
2.41
0.08
0.38
20
5
1.27 BSC
NOTES 1.3
2 10
28-PIN CERAMIC LEADLESS SURFACE MOUNT L PACKAGE SUFFIX
.A1
,B1
B3 DIE 01/El 02/E2
""L"'
L1 L2 L3
NO/NE
DIMENSIONS
INCHES MIN MAX .060 .100 .050 .088 .022 .028
.072 REF. .006 .022 .442 .460
.300 BSC
.... .150 BSC
MILLIMETERS
MIN
MAX
...1.52
2.54
127
2.24
1.83 REF.
0.15
0.56
11.23 11.68
7.62BSC
3.81 BSC
.005 .055 045 .055 .075 .095 .003 .015
28
1.40
1.14
1.40
1.90
2.41
0.08
0.38
28
.050BSC
1.27BSC
NOTES 1,3
10
48-PIN TQFP FQ PACKAGE SUFFIX
DIMENSIONS
INCHES
MINj_MAX
.338I .370
.272J_ .280
Ml LU METERS
....:r .... MINj_MAX
NOTES SQ.
..l 6.90 7.10 SQ,
.012
0.30
c.~
.... .005 .009 0.13_.l 0.23
G
·094
REF.
.0197 SSC 0.50 SSC
.022 .094
....0.55
c .
REF .
.051 .059 1.30 1.50
M
.067
1.70
Q ,0035 .008 0.09 0.20
s ,0035
0.08
T .0035 .008 0.08 0.20
.002 .006 0.05 0.15
.012 .Q28 0.30 0.70
o· 10· o· 10·
RAD. RAD . 3, ·
8-23
r!«)er· SPACED u(!] EQUAL TO @:!)
i lEJ I - - NEG,'· SPACED AT(!] EQUAi m
i
ND<(."· SPACED AT[!) EQUAL TO @j
!I-- NEC[aSPAC£DATliJ
EQUAL TO iill
!
n n l:::.J INTEGRATED CIRCUn&
-UNITRODE
PACKAGING INFORMATION
16-PIN SIDEBRAZE DIP SP PACKAGE SUFFIX
DIMENSIONS
INCHES
MIN MAX
A
- .200
8
.014 .023
8 .045 .065
c .008 .015
D
- .840
E
.220 .310
E1 .290 .320
F
.100 BSC
L
.125 .200
L1 .150
-
Q .015 .060
S1 .005
-
- 52 .005
MILLIMETERS
MIN
MAX
-
5.08
0.36
0.58
1.14
1.65
0.20
0.38
-
21.34
5.59
7.78
7.37
8.13
2.s4 esc
3.18
5.08
3.81
-
0.38
1.52
0.13
-
0.13
-
NOTES
·
2,8 8 4 4 7 5,9
3 6
16-PIN ZIG-ZAG IN-LINE Z PACKAGE SUFFIX
DIMENSIONS
MILLIMETERS INCHES
MIN MAX MIN MAX
A 19.40 19.60 .764 .n2
A1
- - 2.00
.039
8 5.70 5.90 .224 .232
81 9.40 10.40 .370 .409
82 6.50 7.50 .258 .295
c 2.70 2.90 .106 .114
D 18.75 19.35 .738 .762
E 1.07 1.47 .042 .058
F 0.45 0.65 .018 .026
G 2.50 3.00 .098 .118
H 0.23 0.35 .009 .014
J
1.00 BSC
.0398SC
K 1.00 esc .0398SC
NOTES
RAD. CHAM.
BASE PLANE SEATING PLANE HEAT SINK
c
8-24
Application Notes
9-1
n n L::::J INTliGRATED CIRCUIT&
-UNITRDDE
9-2
n n L':::::J INTEGRATED CIRCUITS
-UNITROCE
APPLICATION/DESIGN NOTES TABLE OF CONTENTS
Publication
Number
IC Featured
Application · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · Page
U-93 U-94 U-95 U-96A U-97
U-99 U-100A U-102 U-104 U-106 U-107 U-109 U-110 U-111 U-112 U-113
U-114 U-115 U-116 U-117A U-117B U-118 U-119 U-120 U-121 U-122
U-127 U-128
U-129 U-130 U-131 U-132
U-133 U-134 U-135
UC3524A UC3901 UC3834 UC3844
UC3717 UC3842/3/4/5 UC3637 UC3906 UC3620 UC3825 UC3838 UC3825
UC3637
UC3841 UC3625 UC3832/33 UC3860 UC3860 UC3705/6/7/9 UC3655
UC3860
UC3724/3725 UC3823A,B/ UC3825A,B UC3907 UC3637 UC3906/3823 UC3852
UCC3800 UC3854 UC3848
Push-Pull . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 Isolated Feedback Generator .................................... 9-13 Linear Regulators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-25 Flyback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . · . . . . . . . . . . . . . . . . . . 9-47 Modeling, Analysis and Compensation of the Current Mode Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-52 Filter Reduces EMI and Chopping Losses in Step Motor ............... 9-58 Various Applications ........................................... 9-62 PWM DC Motor Drive .......................................... 9-76 Battery Charger - Lead Acid ..........................·.......... 9-87 3" Brushless DC Motor Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-98 Push-Pull Converter........................................... 9-103 Magnetic Amplifier Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-112 Push-Pull Converter........................................... 9-122 Practical Considerations in Current Mode Control. . . . . . . . . . . . . . . . . . . . 9-134 Microstepping................................................ 9-152 Design Notes of Precision Phase Locked Speed Control for DC Motors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-160 PWM, 300W Off-Line Power Supply .............................. 9-170 Advanced 3" Robust DC Motor Control ........................... 9-181 New Linear Low-Drop Regulator ................................. 9-189 New IC Controls Resonant Mode Power Circuits . . . . . . . . . . . . . . . . . . . . 9-201 Resonant Off-Line 150W Converter (1 MHz) ........................ 9-211 High Speed MOSFET Drivers ................................... 9-219 Low Loss 3" Brushless Motor Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . 9-235 Simplified Approach to DC Motor Modeling. . . . . . . . . . . . . . . . . . . . . . . . . 9-241 150W Resonant Design Review . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-245 A New Family of Integrated Circuits Controls Resonant Mode Power Converters............................... 9-263 Unique Chip Pair Simplifies High Side Switch Drive . . . . . . . . . . . . . . . . . . 9-272 The UC3823A,B & UC3825A, B Enhanced Generation of PWM Controllers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-287 UC3907 Load Share IC Simplifies Parallel Power Supply Design........ 9-296 Dedicated ICs Simplify Brushless DC Servo Amplifier Design . . . . . . . . . . 9-306 Simple Switchrnode Lead-Acid Battery Charger ..................... 9-319 Power Factor Correction Using the UC3852 Controlled ON-Time Zero Current Switching Technique....................... 9-328 UCC3800/1/2/3/4/5 BICMOS Current Mode Control ICs............... 9-344 UC3854 Controlled Power Factor Correction Circuit Design ............ 9-362 The UC3848 Average Current Mode Controller Squeezes Maximum Performance from Single Switch Converters . . . . . . . . . . . . . . 9-382
9-3
APPLICATION/DESIGN NOTES TABLE OF CONTENTS
Publication
Number
IC Featured
Application · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · Page
U-136
U-137
U-138 U-139
U-140 U-141
U-142
DN-19 DN-26
DN-27 DN-28 DN-29 DN-30 DN-31 DN-32 DN-33
DN-35 DN-36
DN-37 DN-38 DN-39D
DN-40
DN-41 DN-42
UC3875
UC170X
UC1861/64 UCC1883/5-8
UC1848 UC3871
UCC3570
UC3901 UC3842/42A
UC3842/42A UC3840/42/51 UC3842A UC3843A UC3864 UC3833 UC3901/ UC3903
UC2525B/27B
UC494 UC494 UC3854
UC3842
UC3854 UCC3802
Phase Shifted, Zero Voltage Transition Design Considerations and the UC3875 PWM Controller ......·..·...··.··..·........... 9-393 Practical Considerations in High Perlorrnance MOSFET, IGBT & MCT Gate Drive Circuits . . . · . . · · . · · . · · . · · . . . . . . . . . . . . . . . . . . . . 9-407 Zero Voltage Switching Resonant Power Conversion. . . . . . . . · . . . . . . . . 9-422 The UCC3883 and UCC3885 Meet ISDN Requirements in a Switch Mode Power Converter . . . · · . . · . . . . . . . . . · · . . . . . . . . . . . 9-449 Average Current Mode Control of Switching Power Supplies .......... 9-457 Resonant Fluorescent Lamp Converter Provides Efficient and Compact Solution ....·......··......·.·.·........·........... 9-471 Voltage-Mode Control Revisited - A New High-Frequency Controller Features Efficient Off-Line Perlorrnance . . . . . . . . . . . . . . . . . . 9-479 Simple Isolation AMP Controller .......·.....·................... 9-485 Frequency Foldback Technique Provides.Protection During Abnormal Operating Conditions ··.··...·..·..·......·........... 9-486 Summary ofFunctional Differences.·........·.................... 9-488 Summary of Functional Differences·..·..........·................ 9-489 Low Cost Start-Up and Fault Protection Circuit ...·..·...........·... 9-490 Programmable Electronic Circuit Breaker ..............·........... 9-491 Current Mode Resonant 'Z>/S Conversion . . . . · · · . . · . . . · . . . . . . . . . . . . 9-492 Optocoupler Feedback Drive Techniques .......................... 9-493 Optocoupler Feedback Drive Techniques Using the UC3901 and UC3903 ·.··...·......·............·.....·.............. 9-494 IGBT Drive Using MOSFET Gate Drivers ....·..·.·................ 9-496 UC1525B/1527B Devices; Comparison Summary to UC1525A/27A Devices.·........···.......·..·....·.·...·.·................ 9-498 PWM Operating with Low Input Voltages ...·.·.·.·................ 9-499 Unique "Cheap and Dirty" Converter for Low Power Bias Supplies . . . . . . 9-500 Optimizing Performance in UC3854 Power Factor Correction Applications . . . . · · . · · · . . . · . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-502 The Effects of Oscillator Discharge Current Variations on Maximum Duty Cycle and Frequency in UC3842 and UC3842 "A" PWM ICs ...... 9-507 Extended Current Transformer Ranges.....·.....·.·...·.......... 9-510 Design Considerations for Transitioning from UC3842 to the New UCC3802 Family ...................·........................ 9-512
9-4
n n INTEGIRATED
~CIRCUITS
-UNITRODE
APPLICATION NOTE
A NEW INTEGRATED CIRCUIT FOR CURRENT-MODE CONTROL
U-93
Abstract
The inherent advantages of current-mode control over conventional PWM approaches to switching power converters read like a wish list from a frustrated power supply design engineer. Features such as automatic feed forward, automatic symmetry correction, inherent current limiting, simple loop compensation, enhanced load response, and the capability for parallel operation all are characteristics of current-mode conversion. This paper introduces the first control integrated circuit specifically designed for this topology, defines its operation and describes practical examples illustrating its use and benefits.
1.0 Introduction
Over the past several years an increased interest in current-mode control of switching inverters has surfaced in the literature. Originally invented in the late 1960s, this scheme was not publicly reported until 1977'11 and has seen rapid development by many authors to date.12-e> In short, current-mode control uses an inner or secondary loop to directly control peak inductor current with the error signal rather than controlling duty ratio of the pulse width modulator as in conventional converters. Practically, this means that instead of comparing the error voltage to a voltage ramp, it is compared to an analogue of the inductor current forcing the peak current to follow the error voltage.
CLOCK _ _ ~~~-_.._
n n n LATCH
OUTPUT __J
LJ
L.J
L
FIGURE 1. A FIXED FREQUENCY CURRENT-MODE CONTROLLED REGULATOR.
Figure 1 illustrates a simplified block diagram of a fixed frequency buck regulator employing current-
mode control. As shown, the error signal, v., is
controlling peak switch current which, to a good approximation, is proportional to average inductor current. Since the average inductor current can change only if the error signal changes, the inductor may be replaced by a current source, and the order of the system reduced by one. This results in a number of performance advantages including improved transient response, a simpler, more easily designed control loop, and line regulation comparable to conventional feed-forward schemes. Peak current sensing will automatically provide flux balancing thereby eliminating the need for complex balance schemes in push-pull systems. Additionally, by simply limiting the peak swing of the error
voltage v., instantaneous peak current limiting is
accomplished. Lastly, by feeding identical power stages with a common error signal, outputs may be paralleled while maintaining equal current sharing.
Although the advantages of current-mode control are abundant, wide acceptance of this technique has been hampered by a lack of suitable integrated circuits to perform the associated control functions. This paper introduces a new integrated circuit designed specifically for control of current-mode converters. Circuit function and features are described in detail, and a comparative design example is used to illustrate the numerous advantages of this approach.
2.0 UC1846 Chip Architecture
In addition to all the functions required of conventional PWM controllers, a current-mode controller
9-5
APPLICATION NOTE
> - - - - - - - - - - - - - - < 2 VREF
,,--.----113 Ve
UC1846 OUTPUT STAGE
U-93
FIGURE 2. UC1 846 BLOCK DIAGRAM
must be able to sense switch or inductor current and compare it on a pulse-by-pulse basis with the output of the error amplifier. As may be seen in the block diagram of Figure 2, this is accomplished in the UC1 846 by using a differential current sense amplifier with a fixed gain of 3. The amplifier allows sensing of low level voltages while maintaining high noise immunity. A list of other features, while not unique to current-mode conversion, demonstrates the advanced, state-of-the-art architecture of the UC1846:
· A ± 1%, 5.1 V trimmed bandgap reference used both as an external voltage reference and internal regulated power source to drive low level circuitry.
· A fixed frequency sawtooth oscillator with variable deadtime control and external synchronization capability. Circuitry features an all NPN design capable of producing low distortion waveforms well in excess of 1MHz .
· An error amplifier with common mode range from ground to Vcc-2V.
· Current limiting through clamping of the error signal at a user-programmed level.
· A shutdown function with built in 350mV threshold. May be used in either a latching, or nonlatching mode. Also capable of initiating a "hiccup" mode of operation.
· Under-voltage lockout with hysteresis to guarantee outputs will stay "off" until reference is in regulation.
· Double pulse suppression logic to eliminate the possibility of consecutively pulsing either output.
· Totem pole output stages capable of sinking or sourcing 1OOmA continuous, 400mA peak currents.
These various features, along with their interrelationships and applications to switched-mode regulators, will be further discussed in the following sections.
3.0 UC1846 Functional Description
3.1 Current Sense Amplifier
The current sense amplifier may be used in a variety of ways to sense peak switch current for comparison with an error voltage. Referring to Figure 2, maximum swing on the inverting input of the PWM comparator is limited to approximately 3.5V by the internal regulated supply. Accordingly, for a fixed gain of 3, maximum differential voltages must be kept below 1.2V atthe current sense inputs. Figure 3 depicts several methods of configuring sense schemes. Direct resistive sensing is simplest, however, a lower peak voltage may be required to minimize power loss in the sense resistor. Transformer coupling can provide isolation and increase effi-
9-6
APPLICATION NOTE
ciency at the cost of added complexity. Regardless of scheme, the largest sense voltage consistent with low power losses should be chosen for noise immunity. Typically, this will range from several hundred millivolts in some resistive sense circuits to the maximum of 1.2V in transformer coupled circuits.
A.) RESISTIVE SENSING WITH GROUND REFERENCE
I
B.) RESISTIVE SENSING ABOVE GROUND CURRENT XFORMER
11~~·
U-93
series with the input is generally all that is required to reduce the spike to an acceptable level.
lk 500pl
, , /
/
""YL/
FIGURE 4. RC FILTER FOR REDUCING SWITCH TRANSIENTS
3.2 Oscillator Although many data sheets tout 300 to 500kHz operation, virtually all PWM control chips suffer from both poor temperature characteristics and waveform distortions at these frequencies. Practical usage is generally limited to the 100 to 200kHz range. This is a direct consequence of having slow
(f, = 2MHz) PNP transistors in the oscillator signal
path. By implementing the oscillator using all NPN transistors, the UC1846 achieves excellent temperature stabillity and waveform clarity at frequencies in excess of 1MHz.
C.) ISOLATED CURRENT SENSING
FIGURE 3. VARIOUS CURRENT SENSE SCHEMES
In addition, caution should be exercised when using a configuration that senses switch current (Figure 3A) instead of inductor current (Figure 38). As the switch is turned on, a large instantaneous current spike can be generated in the sense resistor as the collector capacitance of the switch is discharged. This spike will often be of sufficient magnitude and duration to trip the current sense latch and result in erratic operation of the PWM circuit, particularly at lower duty cycles. A small RC filter (Figure 4) in
--~ 12mA
10 SYNC
OSCILLATOR
/"\
~
___.,/\
(PIN 8) _ . /
\_../"
\_..../"
\
SYNC (PIN 10)
- I I - OUTPUT DEADTIME (Td)
FIGURE 5. OSCILLATOR CIRCUIT
Referring to Figure 5, an external resistor Rr is used to generate a constant current into a capacitor Cr to
9-7
APPLICATION NOTE
produce a linear sawtooth waveform. Oscillator frequency may be approximated by selecting RT and CT such that:
2.2
lose= - - -
RT CT
(1)
Where RT can range from 1K to SOOK and CT is above 1OOpF. For quick reference a plot of frequency versus RT and CT is given in Figure 6.
U-93
A plot of output deadtime versus CT for two values of RT is given in Figure 7.
Although timing capacitors as small as 1OOpF can be used successfully in low noise environments, it is generally recommended that CT be kept above 1OOOpF to minimize noise effects on the oscillator frequency (see Section 4.0).
Synchronization of one or more devices to either an external time base or another UC1846 is accomplished via the bi-directional SYNC pin. To synchronize devices, first, CT must be grounded to disable the internal oscillator on all slaved devices. Second, an external synchronization pulse must be applied to the SYNC terminal. This pulse can come directly from the SYNC terminal of a master UC1846 or, alternatively, from an external time base as shown in Figure 8.
FREQUENCY - KILOHERTZ
FIGURE 6. OSCILLATOR FREQUENCY AS A FUNCTION OF RT AND CT
Again referring to Figure 5, the oscillator generates an internal clock pulse used, among other things, to blank both outputs and prevent simultaneous cross conduction during switching transitions. This output "deadtime" is controlled by the oscillator fall time. Fall time, in turn, is controlled by CT according to the formula:
3 rd = 145 CT [; 2 _ .:~RT(kQ)J
(2)
For large values of RT:
rd= 145 CT
(3)
Jl
EXTERNAL TIMEBASE
FIGURE 8. SYNCHRONIZING THE 1846 TO AN EXTERNAL TIME BASE
3.3 Current Limit One of the most attractive features of a currentmode converter is its ability to limit peak switch currents on a pulse-by-pulse basis by simply limiting the error voltage to a maximum value. Referring to Figure 9, peak current limiting in the UC1846 is accomplished using a divider network, R, and R,, to set a pre-determined voltage at pin 1.
OUTPUT DEAD TIME, Td - MICROSECONDS FIGURE 7. OUTPUT DEADTIME AS A FUNCTION OF TIMING
CAPACITOR CT
9-8
FIGURE 9. PEAK CURRENT LIMIT SET UP
APPLICATION NOTE
U-93
This voltage, in conjunction with Q,, acts to clamp the output of the error amplifier at a maximum value. Since the base emitter drop of Q, and the forward drop of diode D1 very nearly cancel, the negative input of the comparator will be clamped atthe value VPtN 1 -0.5V. Following this through to the input of the current sense amplifier yields:
VPtN 1 -0.5
Vea= 3
(4)
Where Vcs is the differential input voltage of the current sense amplifier. Using this relationship, a value for maximum switch current in terms of external programming resistors can be derived, resulting in:
lcL =
3Rs
(5)
While still on the subject of resistor selection, it should be pointed out that R1 also supplies holding current for the shutdown circuit, and therefore should be selected prior to selecting R2 as outlined in the next section.
One last word on the current limit circuit. As may be seen from equation 5, any signal less than 0.5V at the current limit input will guarantee both outputs to be off, making pin 1 a convenient point for both shutting down and slow starting the PWM circuit. For example, both the under-voltage lockout and shutdown functions are connected internally to this point. If a capacitor is used to hold pin 1 low (Figure 10) then as the input voltage increases above the under-voltage lockout level, the capacitor will charge and gradually increase the PWM duty cycle to its operating point. In a similar manner if the shutdown amplifier is pulsed, the shutdown SCR will be fired and the capacitor discharged, guaranteeing a shutdown and soft restart cycle independent of input pulse width.
TO UNDER·VOLTAGE
LOCKOUT
TO PWM COMPARATOR
FIGURE 10. USING UNOER-VOLTAGE LOCKOUT AND SHUTDOWN TO INITIATE A SLOW START.
3.4 Shutdown The shutdown circuit, shown in Figure 11, was designed to provide a fast acting general purpose shutdown port for use in implementing both protection circuitry and remote shutdown functions. The circuit may be divided into an input section consisting of a comparator with a 350mV temperature compensated offset, and an output section consisting of a three transistor latch. Shutdown is accomplished by applying a signal greater than 350mV to pin 16, causing the output latch to fire, and setting the PWM latch to provide an immediate signal to the outputs. At this point, several things can happen. Q1 requires a minimum holding current, IH, of approximately 1.5mA to remain in the latched state. Therefore, if R1 is chosen greater than 5kQ, Q, will discharge any capacitance, Cs, on pin 1 to ground and commutate the output latch, allowing Cs to recharge. If R1 is chosen less than 2.5kQ, Q1 will discharge Cs and remain in the latched state until power is externally cycled off. In either case, Cs is required only if a soft-start or soft-restart function is desired.
FIGURE 11. SHUTDOWN CIRCUITRY
For example, the shutdown circuit of Figure 12, operating in a nonlatched mode, will protect the supply from overcurrent fault conditions. Many times, if the output of a supply is shorted, circulating currents in the output inductor will build to dangerous levels. Pulse-by-pulse current limiting with its inherent time delay, will in general not be able to limit these currents to acceptable levels. Figure 12 details a circuit which will provide shutdown and soft-restart if the overcurrent threshold set by R3 and R4 is exceeded. This level should be greater than the peak current limit value determined by R1 and R2 (see equation 5). Sometimes called a "hiccup mode", this overcurrent function will limit both power and peak current in the output stages until the fault is removed.
9-9
APPUCATION NOTE
U-93
R1
FIGURE 12. OVER CURRENT SENSING WITH THE SHUTDOWN CIRCUIT PRODUCES A SHUTOOWN - SOFT RESTART CYCLE TO PROTECT OUTPUT DRIVERS
4.0 Noise Immunity
As in all PWM circuits, some simple precautions should be observed td prevent switching noise from prematurely triggering the oscillator as it approaches its upper threshold. This is most evident when large capacitive loads - such as the gates of power FETS - are directly driven from outputs A and B. As the duty cycle approaches 100%, the current spike associated with this output capacitance can cause the oscillator to prematurely trigger with a resulting shift upward in frequency. By separating high current ground paths from low level analog grounds, using Cr values greater than 1OOOpF grounded directly to pin 12, and decoupling both V1N and VREFWith good quality bypass capacitors, noise problems can be avoided.
5.o Comparative Design Example
To more vividly illustrate the advantages of currentmode control, a relatively simple push-pull forward converter was designed using two interchangeable control sections, as shown in Figure 13. The control modules consist of (a) a UC1846 current-mode controller with associated circuitry, and (b) a conventional UC1 525A PWM controller with its support circuitry. Loop compensation of the UC1525A was implemented by placing a zero in the feedback loop to cancel one of the poles in the output stage, resulting in a unity gain bandwidth of approximately 3kHz - a commonly used technique. Compensating the current-mode converter requires somewhat of a different approach. Since the output stage contains only a single pole, in theory closing the loop will produce a stable system with no additional compensation .. In practice, however, it has been shown that subharmonic oscillation will result from excess gain at half the switching frequency151. Therefore, a pole-zero combination has been
placed in the feedback loop to reduce high frequency gain and allow the outp'Ut capacitor (low ESR) to roll off loop gain to OdB at 3kHz.
While not demonstrated in Figure 13, fixed frequency current-mode converters are known to be unstable above. 50% duty cycle without some form of slope compensation14-s1. By injecting a small current from the sawtooth oscillator into the positive terminal of the current sense amplifier, slope compensation is accomplished, and the converter can be operated in excess of 50% duty cycle. An alternate, but just as effective, scheme would be to inject the signal into the negative terminal of the error amplifier.
As may be seen, a similar parts count for both supplies was encountered. Topologically, using the UC1525A shutdown terminal provided only a crude current limit in contrast to the UC1846. Furthermore, internal double pulse suppression circuitry of the UC1 846 gave an added level of protection against core saturation - important if your regulator is prone to subharmonic oscillations. Since both regulators were over-designed to withstand a short circuit on the output with resultant high peak currents, the shutdown-restart mode of the UC1846 was not used.
It stlould be pointed out at this time that one of the main features of a current-mode converter of this type is its ability to be paralleled with similar units. By disabling the oscillator and error amplifiers (Cr grounded, +E/A to VREF, -E/ A grounded) of one or more slave modules, and connecting SYNC and COMP pins of the slave(s) respectively, the outputs may be connected together to provide a modular approach to power supply design.
Starting with Figure 14, a comparison of line and load step responses is made between the two converters. As a result of the feed-forward effect of the current-mode converter, response to a step input change shows more than an order of magnitude improvement (Figure 14a) when compared to the conventional converter (Figure 14b). Although not as pronounced, response to a step load change leaves the UC1846 converter (Figure 15) with a clear advantage in output response - 40mV as compared to 70mV for the UC1525A.
Virtually all conventional push-pull converters are prone to flux imbalance caused by mismatched storage delays, etc., in the output stage. Figure 16 shows both converters operating with the same power stage. No effort was made to match output devices. As may be seen, there is little noticeable
9-10
APPLICATION NOTE
difference between switch currents of the UC1846. However, the UC1 525A - with identical output
5k 005µf
15
v,"
VREF R,
UC1846
1800 2w
U-93
transistors - shows phase B driving the core close to saturation with 50% more current than phase A.
3.6k
(A) UC1846 CURRENT-MODE CONTROLLED REGULATOR
lOOµf
!µI !Ok
82k
(B) UC1525A VOLTAGE MODE CONTROLLER FIGURE 13. PUSH-PULL FORWARD CONVERTER WITH (A) CURRENT-MODE CONTROL AND (8) VOLTAGE MODE CONTROL
t = 2ms/DIV
.... OUTPUT· RESPONSE 50mV/DIV
(A)
(B)
FIGURE 14. RESPONSE TO A STEP INPUT CHANGE OF 25 TO 35V BY (A) UC1846 and (B) UC1525A CONVERTERS
9-11
APPLICATION NOTE
U-93
t.= 0 2ms/DIV
..C OUTPUT> RESPONSE 20mV/DIV
(A)
(Bi
FIGURE 15. RESPONSIVE TO A STEP LOAD CHANGE OF 1 AMP BY (A) UC1846 AND (B) UC1525A CONVERTERS
t = 5µs/DIV
..CSWITCH > CURRENTS (0.2A/DIV)
(A)
(B)
FIGURE 16. SWITCH CURRENTS SHOWING FLUX IMBALANCE IN (A) UC1846 AND (B) UC1525A CONVERTERS
6.0 Conclusion
Rarely do new design techniques evolve that can promise as much as current-mode control for the power supply engineer. We have shown this to be a simple technique easily extended from present converter topologies, that will increase dynamic performance and provide a higher degree of reliability while permitting new approaches to modular
design. Until recently, current-mode converters could not compete with the economics of conventional converters designed with l.C. controllers. Now, with the UC1846 designed specifically for this task, current-mode control can provide all of the above performance advantages on a cost competitive basis.
Unitrode Integrated Circuits Corporation 7 Continental Boulevard.· P.O. Box 399 ·Merrimack, New Hampshire· 03054-0399 Telephone 603-424-2410 ·FAX 603-424-3460
9-12
n n L.::::::J INTEGRATED CIRCUIT&
-UNITRDDE
APPLICATION NOTE
U-94
THE UC1901 SIMPLIFIES THE PROBLEM OF ISOLATED FEEDBACK IN SWITCHING REGULATORS
1. Introduction
The UC1901 simplifies the task of closing the feedback loop in isolated, primary-side control, switching regulators by combining a precision reference and error amplifier with a complete amplitude modulation system. Using the IC's amplitude modulated output, loop error signals can be transformer coupled across high voltage isolation boundaries, providing stable and repeatable closed-loop characteristics. Coupling across an isolation boundary is nothing new in transformer technology, and the UC1901 's ability to generate carrier frequencies of up to 5MHz keeps the transformer size and cost at a minimum. With a secondary reference and accurate coupling path for the feedback signal, isolated off-line supplies can reliably achieve the tolerances, regulation, and transient performance of their non-isolated counter parts and still take advantage of the benefits of primary-side control.
bility. The gain, or current transfer ratio, through an opto-coupler is loosely specified and changes as a function of time and temperature. This variation will directly affect the overall loop gain of the system, making loop analysis more difficult and the resulting design more conservative. In addition, limited bandwidth capability prevents the use of optical couplers when an extended loop response is required.
I /I Ys'bL~fff6N souNDARY
I ~~JR:
SECONDARY
I
Closing a feedback loop in a simple or complex system requires a thorough understanding of all of the loop elements. Worse case variations of each element must be taken into account when loop stability, dynamic response, and operating point are determined. Unpredictability in any of the loop components will affect the overall design by making it, necessarily, more conservative. The transient response of a control loop, for example, will usually suffer if a loop must be heavily compensated to guarantee stability with component variations.
To obtain high levels of load and line regulation, the output voltage of a power supply must be sensed and compared to an accurate reference voltage. Any error voltage must be amplified and fed back to the supply's control circuitry where the sensed error can be corrected. In an isolated supply, the control circuitry is frequently located on the primary, or line, side of the supply. As shown in Figure 1, the feedback signal in this type of supply must cross the isolation boundary. Coupling this signal requires an element that will withstand the isolation potentials and still transfer the loop error signal. Though some significant drawbacks to their use exist, optical couplers are widely used for this function due to their ability to couple DC signals. Primarily, optocouplers suffer from poor initial tolerance and sta-
RGURE 1: A Typical Closed-Loop Isolated PowerSupply With Primary-Side Control.
With reliability firmly situated as an important aspect of electrical design, the benefits of primary-side control are increasingly attractive in off-line designs. The organization of an off-line switcher with primaryside control (See Figure 1) puts the control function on the same side of the isolation boundary as the switching elements. Not only does this simplify the interface between the controller and switches, it makes the protection of these switches much easier. Sensing of the switch currents and voltage can avoid failures and improve over-all supply performance. The argument for primary-side control has been further strengthened by the introduction of a new generation of control IC's. The controllers incorporate such features as low current start-up, high speed current sensing for pulse-by-pulse current limiting, and voltage feed-forward. Low current start-up alleviates the problem of efficiently supplying power to a line-side controller, while fast current limit circuitry and voltage feed-forward take advantage of the proximity of a primary-side controller to both the power switch(es) and the input supply voltage.
Combining all of the necessary functions to generate an AM feedback signal on the UC1901 make it the
9-13
APPLICATION NOTE
first IC of its type. As will be seen, the UC1901 can be used in several modes to take full advantage of its functions. Recognizing the continuing evolution of power converter technology the UC1901 is intended to simplify the design of a new era of reliable and higher performance power converters.
2. The UC1901 Functions
The operation of the UC1901 is best undestood by considering a typical application. In Figure 2, the UC1901 is shown providing the feedback signal to close the loop in an isolated switching power supply. With any feedback system it is desirable to compare the system output to the system reference with a minimum of intermediate circuitry. With the UC1901 situated on the secondary, or output side of the supply, the output voltage is simply divided down and compared to the 1.5V reference using the chip's high gain erroramplifier. In this manner DC errors at the supply output are kept minimal even if significant non-linearities, or offsets, occur in the remainder of the power supply loop. Since the 1.5V output on the UC1901 is a trimmed, precision, reference, the need for a trim-pot to fine tune the output voltage is eliminated.
To make the UC1901 compatible with single output 5V power supplies it is designed to operate with input voltages as low as 4.5V. This allows the part to be powered directly from a TTL compatible 5V output. A nominal supply current of only 5mA allows the part to be easily operated at its maximum input voltage rating of 40V without worry of excessive power dissipation.
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The amplified error signal at the UC1901 's compensation output is internally inverted and applied to the modulator. The other input to the modulator is the carrier signal from the oscillator. The modulator combines these two signals to produce a square wave output signal with an amplitude that is directly proportional to the error signal and whose frequency is that of the oscillator input. This output is buffered and applied to the coupling transformer. With the internal oscillator, carrier frequencies into the megahertz range can be generated. Operating at high frequencies can reduce both the size and cost of the coupling transformer. The secondary winding on the coupling transformer drives a diode-capacitor peak detector. With a simple resistive load to allow discharging of the holding capacitor an effective amplitude demodulator is formed. The small signal voltage gain from the error. amplifier input to the detector output is a function of the feedback network around the error-amp, the modulator gain, the turns ratio of coupling transformer, and any loss in the demodulator.
In Figure 2 the relationship of the detector output to the sense supply voltage is non-inverting. This is necessary to guarantee start-up of the supply. Since the UC1901, as shown, is powered from the supply's output, the initial feedback signal back to the PWM controller will always be zero. The required 180° of DC phase shift is easily achieved by inverting the signal with the error amplifier that is present in most any PWM controller circuit.
In some applications it may be desirable to operate the carrier frequency of the UC1901 in synchroni-
~i~,,;-rLJ11
RF COUPLING TRANSFORMER
RGURE 2: With a Precision Reference, and a Complete Amplitude Modulation System, the UC1901 Lets Isolated Feedback Loops be Closed Using a Small Signal Transformer.
9-14
APPLICATION NOTE
CARRIER INPUT FROM OSCILLATOR
R4
Rs
4K
4K
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COMPENSATION a-----<...
INVERTING o - - - - - i INPUT
NON-INVERTING~
INPUT
__L
2.2V-=-
l R3 1K
a. Os
DRIVER A
AM WAVEFORM OUTPUT
MODULATOR
a,
AND DRIVER
OUTPUTS
I 700µA
R, 1K
700µA
3A
FIGURE 3: The Compensation Output on the UC1901 can be used to Accurately Control the AM Waveform Output. A Simplified Schematic, (a) Shows the internal Signal Split into the Modulator. Voltage Waveforms, (b) Across the Modulator Outputs, and at the Compensation Output show the Modulator Transfer Characteristic.
zation with a system clock, or reference frequency. In many situations, operation of the UC1901 at the switching frequency of the power supply can be beneficial. One such application is presented in this article. To accommodate this need the UC1901 has an external clock input.
One additional mode of operation is possible if the oscillator is left disabled and the external clock signal is kept low (or floated). In this condition the error amplifier can be used in a linear fashion with its output taken at the driver A output. The driver B output will be at a fixed DC voltage about 1.4V from the input supply voltage. If the external clock signal is tied high the roles oi the two driver outputs are reversed. With 15mA of output current capacity, the two outputs can easily be combined to reference and drive an optical cou pier. Although the instabilities of the coupler will still be present, the advantages of the UC1901 's precision reference, high gain amplifier-driver, and 4.5V supply operation can be utilized.
3. A Controlled Feedback Response
There are many different topologies which can be used when implementing a switching power supply. For off-line supplies, fly-back and forward convert-
ers are often designed. In the near future currentmode control versions of these may also be widely used. Each of these converter topologies has a different forward transfer characteristic and, within each type of converter, operating point, continuous or discontinuous inductor current, and voltage or current-mode duty cycle control are a few of the factors which can alter this characteristic. In short, the task of optimally designing a feedback network for one supply must usually be repeated when the next supply is designed.
9-15
APPLICATION NOTE
Once the forward transfer function of a particular converter has been determined, various factors such as stability, line regulation, load regulation, and transient response will determine the overall loop response, and therefore feedback response, required. One of the objectives of the UC1901, in addition to allowing a controlled isolated feedback response, is to make the task of implementing a given response as easy as possible. With the compensation node on the UC1901, local R-C feedback networks can be used to shape the small signal gain and phase frequency response of the overall feedback network.
The error amplifier on the chip has a typical open loop gain of 60dB and is internally compensated to have a unity gain bandwidth of just above 1MHz. Both of these characteristics are measured with respect to the compensation node (Pin12). As shown in Figure 3a, the amplified error signal is internally split, at the collectors of 0 1 and 0 2, and fed to both the modulator and the compensation output. Applying feedback from the compensation output to the error amplifier's inverting input controls the small
signal collector current through 0 1. Since 0 2
sees the same base voltage, and its emitter resistance is the same, its collector current will track that of 0 1. The collector current of 0 2 feeds the modulator and determines the amplitude of its output signal. The 4-to-1 ratio of resistors R4 (or R5) and R2 results in a fixed 12dB of small signal gain measured as the ratio of the amplitude of the differential signal at the modulator outputs to the compensation mode signal. This relationship, as well as the function of the modulator, is shown in Figure 3b. The scope traces show a 200mV peak to peak sinusoid at 2.5kHz, measured at the compensation output, and the resulting 800mV variations in the peak amplitude of a 25kHz square wave carrier as measured across the modulator's differential output.
The remaining factors influencing the response of the feedback path are the signal gain through the transformer, the detector circuit, and the circuitry between the detector output and the supply's PWM. The signal gain through the transformer is simply the turns ratio of transformer. The small signal detector gain can usually be assumed to be unity as long as the AC load presented to the detector is kept small. Some load on the detector is necessary to allow its output to slew in a negative direction. Figure 4 summarizes the transfer and output characteristics of a typical transformer and detector.
U-94
~
PEAK =NVo-V·o
t OV
AVG "'NVP-Wo-
t
~
Bfc·C
FIGURE 4: A Typical Defector Model and its Output Characleristics.
Here the load on the detector is modeled as a current source, simplifying the equations. In actual practice the operating point of the detector output will be determined by the circuitry which interfaces ii with the PWM input. Since the minimum recovery from the detector is zero volts a nominal positive operating level which provides adequate dynamic range for DC and transient conditions should be chosen.
The UC1901 is specified to generate maximum carrier levels equal to or in excess of 1.6V peak. This indicates that a turns ratio of greater than one-to-one will be "required for the coupling transformer if the detector output must exceed approximately 1V, (allowing for a detector diode drop of 0.6V). It should be noted that many switching power supplies now being designed include an integrated PWM control IC. A typical PWM IC includes a dedicated error amplifier which amplifies and buffers the input error voltage and applies it to the PWM ramp comparator. This amplifier can be readily used to fix a nominal detector operating point that is compatible with a one-to-one transformer. Additionally, the error amplifier on the UC1901 and the PWM's amplifier can be combined to achieve both large DC loop gains for improved load and line regulation, and the optimization of the loop gain and phase frequency response for improved transient and stability performance.
4. Transformer Requirements
The coupling transformer used with the UC1901 has two primary requirements. First, it must provide DC isolation. Secondly, it should transfer voltage information across the isolation boundary. Meeting the first requirement of DC isolation will depend on specific applications, In general, though, small signal transformers can be readily built lo meet the isolation requirements of today's line-operated systems.
9-16
APPLICATION NOTE
For the most stringent applications, E-type cores with bobbin carried windings are inexpensively available or built. Where small size is most important, a simple toroid core can be used.
The second requirement of the transformer primarily determines the amount of magnetizing inductance it must have. The magnetizing inductance of a transformer refers to the actual inductance formed by the windings around the core material. In many classical transformer examples, the magnetizing inductance is ignored. This is a valid approximation since, in these examples, the magnetizing current required is much less than the reflected load currents. In this case, the load currents are small and, as the transformer inductance is reduced, the magnetizing currents become dominant.
The driver outputs on the UC1901 are emitter followers which are biased at 700µA. Therefore, if the drivers are operated without additional bias current the peak current through the transformer's primary winding cannot exceed this value. Figure Sa illustrates the relationship of the magnetizing current to the voltage across the transformer's input. If the reflected load currents are neglected, it can be seen that the minimum magnetizing inductance required for linear transfer of the modulator squarewave is given by:
(1)
Where: VP
fc
Ip
the magnetizing inductance,
the peak carrier voltage across transformer inputs,
the UC1901 operating frequency, the bias current of the UC1901 drivers.
As an example, consider the case where Vp is equal to 2V, f0 is 1OOkHz, and the drivers are operating at their internal bias levels. Using equation 1, the inductance looking into the primary winding with no secondary load must be greater than 7.1 mH. Alternatively, if the carrier frequency is raised to 1MHz and the bias levels of the UC1901 drivers are increased to 3.SmA, then LM can be as low as 1SOµH. Using high permeability ferrite material, this level of magnetizing inductance can be realized with as little as 10 turns on a small toroid core.
Equation 1 sets a minimum limit on the magnetizing inductance for linear transfer of the carrier wave-
U-94
5A
Tl ME --------
58
TIME-
FIGURE 5: TheUC1901 DriverOutputsFoltowtheModulator Output Square Wave, (a.), Sourcing and Sinking Current Levels Dependent on Transformer Inductance, Carrier Frequency, and 1.bltage Level. When the Bias Level ofthe Driver Outputs, 1,,, is Reached, (b.), a Tri-state Waveform is Coupled Across the Transformer, the Peak 1.bltage Level Though, Remains Approximately the Same. The Reflected Load Currents are Assumed Negligible.
form. Actually, the amplitude information is still coupled even when the inductance is less than this minimum. In this case, the UC1901 drivers will support the voltage across the coil until the peak current is reached. The result, illustrated in Figure Sb, is a tri-state waveform at the transformer's input and output. Peak detection of this waveform yields the same amplitude information as the linear transfer case, although detection ripple will increase. Another situation which results in a tri-state waveform exists when the carrier duty cycle is not SO%. In this case, the volt-seconds across the transformer will be balanced by an "imbalancing" of the driver
9-17
APPLICATION NOTE
bias levels. The imbalance will be sufficient to cause the peak current to be reached during the > 50% portion of the carrier waveform.
5. The High Frequency Oscillator
The oscillator circuit on the UC1901 is designed to operate at frequencies of up to 5MHz. To achieve
this operating range the circuit shown in Figure 6
uses only NPN transistors in those parts of circuit which are dynamically involved in the actual oscillation. The standard bipolar process used to produce the UC1901 characteristically yields high fT, typically 250MHz, NPN devices. Conversely, the same process has PNP structures with f/s of only 1 to 2MHz. In the oscillator, PNP's are used only in determining quiescent operating points of the circuit.
The latched comparator formed by 0 1-04, diodes D1 and D2, and resistors R1 and R2 has a controlled
input hysteresis which determines the peak to peak
voltage swing on the timing capacitor Cr. The timing capacitor Cr is referenced to V1N since this is the
reference point for the latched comparator's thresholds. The comparator's outputs at 0 1 and 0 2 switch the 2X current source through 0 10 changing the net current into the timing capacitor from positive to negative, reversing the capacitor voltage's dv/dt.
U-94
When the resulting ramp reaches the comparator's
lower threshold, the current is switched back to
0 11 and the ramp reverses until the upper thres-
hold is reached and the process begins again. This
results in a triangle waveform at Cr and a squarewave
signal at D1 and 0 2·
The magnitude of the charging current is controlled
by the external resistor, Rr and the internally gener-
ated voltage across it. This voltage is compensated to track variations in the comparator hysteresis. The tracking characteristics of this voltage stabilize the oscillation frequency over temperature and enhance the initial frequency tolerance. Typically, repeatability and temperature stability ofthe operating frequency are both better than 5%.
The oscillator circuit has been optimized for a
nominal Rr of 1Ok.Q. A desired operating frequency
is obtained by choosing the correct value for Cr. As
shown in Figure 7, the oscillator frequency is give
by the relation:
(2)
fosc. = 1·24 ·
RrCr
for frequencies below 500kHz. Above 500kHz, the
solid line indicates appropriate Cr values. There is
14 UCl901 OSCILLATOR
Cr
RT (10K)
210
t-t-~~R5,..._+-~-+~C~L~O~C~KE~XITNE~PRUN:A..L:.jT 2
OUTPUT TO MODULATOR RGURE 6: UC1901 High Frequency OscillalOI" Simplified Schematic.
9-18
APPLICATION NOTE
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no upper limit on the size of the capacitor used, thus allowing the oscillator to have an arbitrarily long period if desired.
10'~-~----~----~
/ /
il10°
~ 1051----+-~r-----+--+-----I
~
10 Cr VALUE~ PICOFARADS
FIGURE 7: UC1901 Oscillator Frequenc}< To allow operation of the modulator with a carrier frequency that is driven from a system operating frequency or clock, the oscillator can be over-ridden. Tying CT to the input supply voltage disables the oscillator. The modulator circuit can now be switched in synchronization with a signal atthe external clock input. Internally, the clock signal is applied to the
RECTIFIED LINE VOLTAGE
latched comparator via the input device 0 9, and the differential pair 0 7 and 0 8· As the clock input goes high, 0 9 turns 0 8 off and 0 7 on, creating an offset across R3 that is sufficient to switch the comparator. The comparator then, as before, drives the modulator. When the clock input returns low, the process is reversed. Using the external clock input, both the frequency and duty cycle of the modulator outputs are controlled.
6. A Status Output is More Than Just a Green Light
Many systems today require a monitoring function on the supply output. The status output on the UC1901 can fill this need, a green light function, and can also be used to fill some more "sophisticated" needs. The circuit in Figure 8 takes advantage of the status output in the start-up of an off-line forward converter. The UC1901 is being used in an application where the switching supply must be synchronized to a system clock. The clock signal is generated on the secondary or output side of the supply. To allow start-up, the PWM oscillator is free-running when the line voltage is applied. As the supply voltage rises, the UC1901 's external clock input is driven at the switching frequency rate through resistors R1 and R2· When the supply output
OUTPUT FilTER
POWER
o,
TRANSFORMER
SUPPLY OUTPUT
PWM OUTPUT
START-UP CLOCK SIGNAL
R7
TO PWM
ERROR AMP.
Ra
COUPLING TRANSFORMER ~
MASTER CLOCK SIGNAL
SYSTEM MASTER CLOCK
FIGURE 8: The Status Output on the UC1901 is used in the Start-Up of a Power Supply Synchronized to a Secondary Referenced Master Clock. The Coupling Transformer Carries the Feedback and Clock Signals. The Status Output is used to Sequence Clock Signals to the UC1901 External Clock Input During Start-Up.
9-19
APPLICATION NOTE
reaches 90% of its operating level, the status output decouples the external clock input from the switcher and enables the UC1901 's clock input to be driven from the now operational system clock.
On the primary side, the output of the coupling
transformer is used before demodulation to provide
a synchronization pulse to the PWM control oscilla-
tor. Under normal operation, the entire power supply,
including the feedback system, will be synchronized
to the system clock
·
7. The UC1901 in an Off Line Flyback Converter
As alluded to previously, flyback converters see wide use in off-line applications. The flyback topology has some general cost benefits which have spurred its use in low cost, low power (< 150W), off-line systems. Perhaps the two most significant of which are the need for only a single power magnetic element in the supply (no output filter inductor is required), and the ability to easily obtain multi-output systems by adding one additional winding to the coupling power inductor for each extra output. Also, the flyback topology, especially when used in the discontinuous mode, lends itself very well' to the benefits of voltage feed-forward.
7a. 60 Watt Dual Output Converter
Shown in Figure 9 is a flyback converter designed with the UC1901 and a primary side control IC, the UC1840. The converter has two 30W outputs, one at 5V/6A, and another at 12V/2.5A. Minimum loads of 1A are specified at each output. The UC1901 is used to sense and regulate the 5V output. This output is specified at ±2 percent (untrimmed), with load and line regulation of better than 0.2 percent. Respectively, the 12V output is specified at ±5 percent with ±6 percent load and line regulation. Regulation of the 12V output relies on close coupling between the 5V and 12V output circuits.
The UC1840 controller has all of the features discussed previously for an off-line controller. In
addition, it has some advanced fault protection features. Only parts of the UC1840's capabilities are discussed here. For those desiring a more complete description, it can be found in the second reference mentioned at the end of this article. In the supply, the UC1840 sequences itself through startup using the energy stored in C4 by the trickle resistor R11 · Once the supply is up and running
W4, the auxiliary winding on Li, provides power to the
controller and the switch drive circuitry. The primary
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winding on the coupled inductor, W1 is applied across the rectified and filtered line voltage at a 60kHz rate via the FET switching device. L1 is referred to as a coupled inductor, rather than as a transformer, since the primary and secondary windings do not conduct at the same time. Energy is stored in the inductor core as the switching device conducts, and then "dumped" to the secondary outputs when the device is turned off.
The converter operates in the discontinuous mode. Operating in this mode, the total current in the coupled inductor goes to zero during each cycle of operation. In other words, the energy stored in the core during the beginning of a cycle is entirely expended to the load before the end of the cycle. This allows the inductor size to be minimized since its average energy level is kept low. The price paid for discontinuous operation is higher peak currents in the switching and rectifying devices. Also, high ripple currents at the supply's output(s) make ESR, (equivalent series resistance), requirements on the output filter capacitors more stringent.
7b. Discontinuous Flyback's Forward Transfer Function
The process of designing a feedback network for the supply begins with determining the small signal transfer function of the converter's forward control path. This path can be defined as the small signal dependency of the output voltage, V0 ur. to, Ve, the control voltage at the input to the PWM comparator. As defined, the control voltage on the UC1840 appears at the compensation output of its internal error amplifier. The transfer function of this path for the discontinuous converter is given by equation (3).
(3)
AA. 1 + s,CFRs
V'2L;; 1 + sCFRL
2
level of the rectified line voltage, The equivalent peak PWM ramp voltageequal to the extrapolated control voltage input which would result in a 100% switch duty cycle, One period of the switching frequency, Magnetizing inductance of the primary winding, A total effective output filter capacitor,
9-20
r
117V AC LINE
(0
~
l;6o
VREF 10K
R4
AUXILLARY SUPPLY
R5 150K
R11 10K (2W)
l
C4 100
II ~ f ;~00 e
D3 UES1402
f ;gooo f)A USD945
I~II~
L1
01 2N222
02
UFN 731
R7 1K
VREF
Rg 1-8K
R10 101<
R15 220K
C12 680pf
R17 120K
R15 10K
VREF
I · 05
1N914
II
T1 COILCRAFT E3493A
FIGURE 9: The UC1901 Combines With an Advanced PWM Controller in a 60W Off-Line Converter.
:z:.
"'ti "'ti I"""
0
~
:0z
:z
12V OUTPUT
0
~
l'T'I
SV OUTPUT
r C5 22
R13 4.?K
~R14 12K
C10 820pf
R15 2K
'::-
c
~
APPLICATION NOTE
RL
The total effective load, (assumed
resistive),
R5
ESR of the filter capacitor,
s
2rrjf, f is frequency in hertz.
The word effective is used in describing AL and CF since, although we are interested in calculating the response to the 5V output, the loads at the 12V and auxiliary outputs must be accounted for. This is easily done by reflecting these loads to the 5V output using the corresponding turns ratio on the inductor.
7c. Voltage Feedforward Steadies Response
Equation 3 indicates a substantial dependency of the control response to both the load AL, and the input voltage, V1N. This can slightly complicate the design of the feedback network since both the gain and phase response of the loop will vary with operating conditions.
The benefits of feed-forward are easily illustrated at this point by examining its effect in this circuit. The UC1840 controller uses resistor R5 to sense the input voltage and proportionately scale the charging current into the PWM ramp capacitor, C3· Scaling the ramp slope is the same as scaling VR· the equivalent peak ramp voltage. The result is a modeled ramp voltage given by:
(4)
When this expression for VR is substituted into equation 3, the result is a forward transfer function that is independent of the input voltage. Not only does this simplify the feedback analysis, it also vastly improves the supply's inherent rejection of line voltage variations.
The forward response of the converter, plotted in Figure 10, has a single pole roll-off occurring between 11 Hz and 38Hz depending on the load. The single pole roll-off allows the feedback network a bit of latitude since, from a stability standpoint, the loop bandwidth can be extended by simply adding broadband gain with an appropriate roll-off frequen-
U-94
+20
+10
~
~ .z , I "~' -10
g
-20
MAX. LOAD
-- MIN. LOAD
-
fil
a:
*J,
<fl
"6:'
-45
-30
-90
-40 10 20
50 100 200 500 1K 2K FREQUENCY-HERTZ
5K 10K
-135 20K
RGURE 10: Closing the Feedback Loop is Preceeded 17/ the Characteriration of the Converter's
Forward Small Signal Transfer Function.
cy. No mid-band zeros or led-lag networks are necessary, as might be for converters with double pole responses. Although, the zero resulting from the ESR of the filter capacitors can, if not taken into account, appreciably extend the loop bandwidth beyond its intended value.
7d. Wide Bandwidth Gives Fast Transient Response At SV Output
This supply was designed to have a unity gain loop bandwidth of between 5 and 1OkHz. With this bandwidth the supply's control response to step load and line changes occurs in fractions of a millisecond. This is only true with regard to the 5V output. There is no feedback from the 12V output therefore the output impedence of the 12V supply will be determined by IA losses, the dynamic impedence of the rectifying diodes, and the coupling efficiency between the inductor windings. This impedence is not reduced by the loop gain, as it is at the 5V output. As a result, the time constant of the response at this output will be considerably longer.
The fast response of the 5V output and the relatively slow response of the 12V output are illustrated in Figure 11 which shows three oscilliscope traces in response to a 3.0A load change at the 5V output. The upper trace is the response of the 5V output
9-22
APPLICATION NOTE
which has been expanded and lowpass (< 15kHz) filtered slightly so the small signal loop characteristics can be seen. The trace below this is the 12V output's deviation due to cross-regulation limitations, the longer time constants involved are obvious. Both the fast response of the 5V loop, and the longer settling time of the 12V output are apparent in the third trace. This trace is the fed back correction signal at the UC1840's error amplifier output. From the middle trace the output impedence of the 12V supply can be estimated by noting the approximate 1ms time constant and dividing it by the 2000µF value of the 12V output filter capacitor. This gives a value of 0.5Q for the output impedence. This agrees well with actual measurements of the 12V output's load regulation.
U-94
The UC1901 is operated with a carrier frequency of 500kHz. The coupling transformer, a Coilcraft E3493A, (double E core, bobbin wound construction), has a magnetizing inductance of 2.1 mH. At 500kHz the peak current required to drive the primary winding is only 475µA per peak volt. The reflected load current is kept much smaller. This allows the transformer to be easily driven from the UC1901 driver outputs. The E3493A is widely used as a common mode line choke, and is rated for V.D.E. and U.L. isolation requirements. The transformer has a current rating of 2A, greatly exceeding the requirements of this application. Even though the device is larger than some alternatives, its availability and high volume pricing, as well as its isolation capability, make ii a very suitable choice.
~OV/DV t
05 V/DIV
0.5 V/DIV
1ms/OIV
FIGURE 11: The Transient Response of the 5V Output (Top Trace), to a 3.0A Step Load Change Reflects the Extended Bandwidth of the 5V Loop. The Open-Loop 12VOutput (Middle),
Responds to the Effects of Cross Regula-
tion. The Feedback Error Signal (Lower) Coupled Through the UC1901 is Measured at the UC1840 Error Amp. Output
7e. The Feedback Response
Plotted in Figure 12 is the response of the feedback network. Also plotted are the asymptotic gain lines of the two contributing gain blocks, the UC1901 response (from 5V output to detector output) and the UC1840 error amp response (detector outputto the PWM control voltage). The UC1901 's error amplifier is run open loop at DC but is quickly rolled off to 8dB. With the 12dB of modulator gain, the UC1901 feedback system has a broadband gain of 20dB. A pole at 16kHz is added to reduce the gain through the UC1901 error amplifier at the 60kHz switching frequency. As mentioned earlier, excessive gain at the switching frequency can "use up" the dynamic range of the UC1901 's AM output.
Al the output of the transformer the diode-capacitor detector is referenced, along with the inverting input of the UC1840 error amplifier, to the UC1840's 5V reference. The operating point of the detector is fixed at 0.5V by the divider formed by R16 and R17 in Rgure 9. This in turn sets the operating point of the carrier, with a detector diode drop of 0.5V, at about 1V peak. This level is reflected back through the one-to-one transformer to the UC1901 outputs. A 1V operating point is approximately at the center of the devices dynamic range.
The load current at the detector output is 50µA, set by the 0.5V operating level and R16. The peak to peak detector ripple, at 500kHz, across the .0015µF nolding capacitor is about 35mV. The gain through the UC1840 error amplifier at 500kHz is -26dB,
.__.....__..._......._........_
10 20
50 100 200
' I', ' ........~.___.__.___.__. · 180
500 1K 2K
5K lOK 20K
FREQUENCY-HERTZ
FIGURE 12: Local Feedback Around the UC1901 and
1840 Error Amplifiers is Used to Obtain the
Desired Feedback Response.
9-23
APPLICATION NOTE
U-94
attenuating the ripple to less than 2mV at the error amplifier output.
The response of the UC1840 error amplifier is flat out to 1kHz where the gain is rolled off to set the loop's Odb frequency. The DC gain is kept as high as possible, to fix the detector operating point, without actually having a series integrating capacitor in the feedback. If both the UC1901 and the UC1840 error amplifiers are run open loop at DC, with series R-C networks to set the AC gain, the total phase margin at low frequencies can become small or nonexistent. The result can be instability or, more likely, a peaked closed loop response that can increase the low frequency noise level of the supply.
The distribution of gain between the UC1901 and UC1840 error amplifiers is somewhat, although not entirely, arbitrary. Keeping the 500kHz ripple at the PWM comparator input below a certain level puts restrictions on the AC gain of the PWM's error amplifier. To much AC gain through the UC1901 's amplifier can degrade the supply's transient response under large signal conditions. A suitable distribution for any application will, more than likely, be an iterative procedure. A simple computer or programmable calculator program can be a great tool when massaging these aspects of a design.
]'-~ ~:L~~: I~ +50 .---..--..-.,....,..---,.--.--...--.--..--....----.
'~ +40 1---+--+--+'..,.,._--+-t---t--+---+----t
'.'J
CONVERTER '
~ +30 t-- OPEN-LOOP --+v--'C.,.,f-'''<\----1+--t---t---1
~
RESPONSE
)'
i~ +20
'
GAIN.../
PHAS7
' r-.. \(_',. \~
-45
~+10l===+::==:t:=~;....i..,.....--1-__.j~~~~~---l--I
-~---1----N- ~ ~
-90
~ ·135
·10
'~ -180
10 20
50 100 -200 500 1K 2K 5K 10K 20K
FREQUENCY-HERTZ
FIGURE 13: The Over-All Open-Loop Response of the Supply Will Determine the Supply's OverAll Stability and Small Signal Transient Response.
The result is a supply with very repeatable, as well as stable, operating characteristics. The same type of analysis for determining the required feedback response can be used in applying the UC1901 to any type of isolated closed loop supply. The choice of coupling transformer and carrier frequency used with the UC1901 should be based on inaividual system requirements.
REFERENCES
1 1J.F. Kukielka and R.G. Meyer, "A High-Frequency Temperature-Stable Monolithic VCO", IEEE J. Solid-State Circuits, Vol SC-16, Dec. 1981.
21B. Mammano, "Applying the UC1840 to Provide Total Control For Low-Cost Primary-Referenced Switching Power Systems", Application Note U-91, Unitrode Corporation, Lexington, Mass., 1982.
31R.D. Middlebrook and S. Cuk, "Modeling and Analysis Methods for DC-to-DC Switching Converters'', Advances in Switched-Mode Power Conversion, TESLAco, Pasadena, Calif., 1981.
41R. Patel and G. Fritz, "Switching Power Supply Design Review-60 Watt Flyback Regulator, Unitrode Power Supply Design Seminar Manual, Unitrode Corporation, Lexington, Mass., 1983.
The overall open-loop responses, plotted in Figure 13, will not vary significantly except as indicated with load. The desired loop bandwidth has been achieved with an adequate phase margin of > 50°.
Unitrode Integrated Circuits Corporation
7 Continental Boulevard. ·P.O. Box 399 ·Merrimack, New Hampshire· 03054-0399
Telephone 603-424-2410 ·FAX 603-424-3460
9-24
n n C_j
INTEGRATED CIRCUITS
-UNITRDDE
APPLICATION NOTE
VERSATILE UC1834 OPTIMIZES LINEAR REGULATOR EFFICIENCY
U-95
Linear voltage regulator5 have long been an important resource to power supply designers. Three terminal, fixed-voltage linear regulators find extensive use as "spot" regulators and as post-regulation stages fed by switched-mode supplies. However, while inexpensive and simple to use, these devices have several performance limitations.
First, three terminal regulators are inefficient power converters. Power dissipation in a linear regulator is given by the relation:
p =Io . (VIN - VouT).
Most monolithic regulators now available require an input-to-output voltage differential of at least 2 to 3V. This requirement can result in substantial inefficiency, particularly in low voltage supplies. As switched-mode power technology matures, power losses incurred in linear post-regulation stages are becoming more significant in terms of overall system efficiency.
Second, fixed-voltage regulators, with fixed maximum output currents, lack versatility. The use of these devices requires that OEMs maintain large, diverse inventories in order to support a broad range of power supply requirements.
Third, fixed three-terminal devices lack the capability of remote voltage sensing, and therefore can exhibit poor load regulation.
Finally, the most common failure mechanism for linear regulators is a shorted pass transistor. All critical loads, therefore, require over-voltage protection not provided by three-terminal regulators.
IMPROVED PERFORMANCE WITH UC1834
The UC1834is a programmable linear regulator control IC which, with an external pass transistor, forms a complete linear power supply. This IC provides solutions to all the above-mentioned drawbacks of three-terminal devices.
Figure 1 shows the basic elements of positive and negative regulators implemented with the UC1834. An error amplifier monitors the output voltage and provides appropriate bias to the pass transistor (QI) through a driver stage. This high-gain error amplifier (E/ A) allows good dynamic regulation while allowing Ql to operate near saturation in the common-emitter mode. The circuits can achieve high efficiency by maintaining output regulation with an input-to-output voltage differential as low as 0.5V (at SA).
9-25
APPLICATION NOTE
The UC1834 has both positive and negative reference voltage outputs, as well as a sink-or-source driver stage, as shown in Figure 1. These features allow implementation of either positive or negative regulators with this single IC, as shown. Output voltages from l .SV to nearly 40V can be programmed by appropriate choice of remote sensing divider elements. Remote sensing also allows improved DC and dynamic load regulation.
VouT
U-95
VOLTAGE REF.
ViN a.
UC1834
VOLTAGE REF.
VouT b. Figure 1. Basic Elements of (a.) Positive and (b.) Negative Regulators implemented with a UC1834
9-26
APPLICATION NOTE
The UC1834 is intended to provide a complete linear regulation system. Therefore, many auxiliary features are included on this IC which eliminate the need for additional circuit elements. Figure 2 shows a more complete block diagram including on-chip provisions for current sensing, fault monitoring, remote voltage sensing, and thermal protection.
U-95
16 CROWBAR GATE ~~----<15 O.V. LATCH & RESET b------+-+--------~14 COMPENSATION/SHUTDOWN ~+-----_.--+----------ill FAULT DELAY
Figure 2. UC1834 Block Diagram
DRIVING THE PASS TRANSISTOR
Figure 3 shows suggested pass transistor configurations for implementing either positive or negative regulators with the UC1834. For those low current (:S:200mA) applications in which efficiency is not extremely critical, the UC1834 output transistor can serve as the pass element, resulting in the simple configurations of Figure 3a. An external pass transistor is needed for output currents greater than 200mA. With the circuits of Figure 3c, the UC1834 can maintain regulation while operating the pass transistor near saturation. Operation at very high output currents (to - 30A) is possible with the Darlington pass elements of Figure 3d.
9-27
APPLICATION NOTE
Positive Output
vi'Ncr--------
V6uT
U-95
Negative_ Output
GNDr~----~--------' GND
GND1 r - - - - - - - - - - - - < GND
a. louT: O - 200mA
V1N - VouT :2:1.0V
Vm'~-----__J
VouT
0
b. louT > 200mA V1N - VouT:2:1.2V
5la Q2
Q2
c. louT: O - 5A V1N - VouT:2:0.5V
d. louT >5A V1N - VouT :2:L2V
Figure 3. Pass Transistor Configurations
9-28
APPLICATION NOTE
Current in the UC1834 output transistor is self-limiting, for improved reliability. This limiting is achieved by Q3 and R 1 in Figure 4a. The resulting maximum output current is a function of temperature as shown in Figure 4b.
A resistor (RE) is shown in series with the drive transistor in Figures 3c, d. This resistor shares base-drive power with the transistor, allowing cooler, more reliable operation of the IC. RE should be as large as possible while still supporting adequate pass transistor base current under worst-case conditions of low input voltage and maximum output current;
VRE(min) = VIN(min) - VBE(maxXQ2) - VCE(sat)(max)(Ql) IB(max)(Q2) = lQ(max)/ /3(min)(Q2) RE(opt) = VRE(min)/ IB(max)(Q2)
where: VRE(min) is minimum voltage available to RE lB(max) (Q2) is maximum required base drive to Q2 RE(opt) is optimum value of RE.
RE also enhances stability by allowing operation of Q 1 as an emitter-follower, thereby eliminating /3Q1 from the loop transfer function:
= lC(Ql) lE(Ql) = (VE;Aout - VBE(Ql) - VBE(Q2j}/RE (/3 independent).
U-95
400
300
l[)(maxl
(mA) 200
100
!------
~ -
0 -55
25
125
T {OC)
a.
b.
Figure 4 a. Driver Current Limiting Circuit b. Resulting Maximum Current vs Temperature
9-29
APPLICATION NOTE
CURRENT SENSING
In order to protect the pass transistor from damage due to overheating, one must sense its emitter current (IE) and then decrease the base drive if IE is excessive. The UC1834 current sense amplifier (CS/ A) accomplishes these tasks.
The UC1834 CS/ A has a common mode range which includes both input supply "rails". This extended range is made possible by introducing matched voltage offsets in the differential input paths, as shown in Figure 5. Internal current sources bias the offset diodes in their appropriate direction. Which bias source(+ or·) is active is determined by whether the CS/ A positive(+) input is greater or less than VJ.N/2. Therefore, it is advisable to configure the sensing circuit such thatthe voltage at CS/ A(+) will not cross VIN/2 during operation. This precludes sensing in series with the load for most applications.
U-95
UC1834
RsENSE
at Figure 5. Two Diode-Drop Offset Allows Current Sensing Supply Rall
The CS/ A has a programmable current limit threshold which can be set between OmV and 150mV. Programming is achieved by setting the voltage at the "Threshold Adjust" terminal (pin 4) to 10 · VTH(desired)· The factor of 10 provides good noise immunity at pin 4 while allowing low power dissipation in the current sensing resistor. Figure 6 shows the guaranteed relationship between VPIN4 and the actual resulting threshold across the CS/ A inputs. Note that the threshold is clamped at l 50mV if pin 4 is open or
if VpJ.N4 > l .SV. The "Threshold Adjust" input is high impedance (bias current is less
than lOµA), allowing simple programming through a voltage divider from the l.SV reference output. However, loading the l.SV reference will affect the regulation of the -2.0V reference. Figure 7 shows how to compensate for this loading with a single resistor when the -2.0V reference is needed.
9-30
APPLICATION NOTE
U-95
.5
1.0
1.5 > l.5V OR OPEN
VOLTAGE AT THRESHOLD ADJUST PIN (PIN 4) - V
Figure 6. Guaranteed Tolerances on C/S Threshold Adjustment
UC1834
+ 2.0V
+
R, l.5V
V·OJ = l.5V · ~ R, *TO MAINTAIN -2.0V OUTPUT
R, =, ~:~ ·1(R1 + R.)
Figure 7. Setting the Current Threshold and Compensating the -2.0V Reference
The CS/ A functions by pulling the E/ A output low, turning off the output driver (Figure 8). As current approaches the threshold value, the E/ A attempts to correct for the CS/ A output, resulting in an E/ A input offset voltage.The supply output voltage can decrease a proportional amount. When the CS/ A input voltage differential reaches the current sense threshold, then the pass transistor is totally controlled by the CS[A. The combined CS/A and E/ A gains and output configurations result in the current limit knee characteristic of Figure 9.
9-31
APPLICATION NOTE
Nol.
INV.
DRIVER
U-95
SENSE-
SENSE+
THRESHOLD
ADJUST
----~
Figure 8. Current Sense Tied to E/A Output
> E
I
".~..'. ~ 120
a.:~
~~
o:-
00
O:>-
ffi~
80
>«-<zJ
""'"'"'
....<(~ "'
~~"~' 40
t;;
i£
0
oi....-~~~~-1..~~__J~~__J
-10
-7.5
-5.0
-2.5
CURRENT SENSE
THRESHOLD
DIFFERENTIAL VOLTAGE AT CURRENT SENSE INPUTS - mV
(REFERENCED TO SENSE - INPUT)
Figure 9. Current Limiting Knee Characteristic
FOLDBACK CURRENT LIMITING
It is desirable to put an upper limit on pass transistor power dissipation in order to protect that device. Ideally, for a constant power limit:
= IE(max) · VCE K
where K is a constant
or: IE(max) = K/(VIN - VoUT) (ignoring the sense resistor voltage drop).
As the input-to-out voltage differential increases, it is necessary to ''fold back" the maximum allowable current; This ideal foldback characteristic is shown in Figure 10, along with a practical characteristic achievable with the circuit of Figure l l.
9-32
APPLICATION NOTE
0.1 CVAoJ)
Rs EN SE
lc=lo
\
\
\ \
\ :\
!.
--- IDEAL -PRACTICAL
---- -"'""" .......
0-,'------------>----
Figure 10. Ideal (Dashed Line) and Practical (Solid Line) Foldback Current Limiting Characteristics
U-95
v,: '· RsE...,SE
PASS DEVICE
o--=...·_,...--MNrr-+---l~f---+-{ J Vour
UC1834
IEMAXITypicall
= 0. l(V.DJ)_ (V,/- Vour) R,
RseNsE (R1 + R2) RseNse
FOR: R, + R2 >> RsENSEo VA.DJ S l.5V, R,' = R,.
Figure 11. Foldback Current Limiting - Responds to Changes in V1N or VouT
This circuit responds to changes in either VIN or VoUT. The voltage differential VINVoUT causes proportional current flow through Ri and R2. The additional drop across Ri is interpreted by the CS/A as additional load current. The result is that the real current limit decreases linearly with VIN - VoUT:
O.l(V ADJ)
IE(max) = R
SENSE
(VIN - VouT) Ri (R1 + R2) RsENSE
for: Ri + R2 ~ RsENSE VADJ :5 l.5V
Ri'. = Ri.
9-33
APPLICATION NOTE
This technique can be susceptible to "latch-off". If a momentary short at the supply output causes IE to drop to zero (pass transistor cut off), then VouT cannot recover when the short is subsequentially removed. To prevent this undesirable operation, one
> must ensure that IE(max) 0 when VouT = 0 and VIN is at its minimum:
IE(max)
VoUT = 0
VrN(min)
O.l(VADJ)
=
RsENSE
> (VIN - VoUT) Ri O
(R1 + R2) RsENSE
> 0. l(VADJ)
Ri
VrN(min)
Ri + R2
(l _ > R2 VrN(min) Ri
0.1 (VADJ) )
0.1 (VADJ)
VrN(min)
Figure 12 shows an alternative foldback current limiting scheme which responds to decreased VouT only. This circuit gives the output characteristics of Figure 13, defined by the following relation:
U-95
This technique is immune to "latch-off" because the minimum current limit is always non-zero.
Figure 12. Foldback Current Limiting - Responds to Changes in VouT Only 9-34
APPLICATION NOTE
U-95
le1MAl() >-----+-v-.L. ~--+---T~--+------4
~
ov
VOUT Vounoeslgnedl
Figure 13. Foldback Current Limiting Characteristic
FAULT CIRCUITRY AND SYSTEM INTERFACING
In order to minimize the need for additional components, the UC1834 has on-chip provisions for fault detection and logic interfacing. These features are particularly useful when the linear regulator is part of a larger power supply system.
As shown in Figure 14, an internal comparator monitors the UC1834 E/ A inputs. This comparator has two thresholds, for over- and under-voltage detection. Comparator
thresholds are fixed at I VN.1. - Vrnv. I =150mV. The resulting output voltage windows
for non-fault operation are:
-±-.15-0V- = ± 10% for positive(+) supplies
l.SV
± .150V =± 7.5% for negative(-) supplies. 2V
A fault delay circuit prevents transient over- or under-voltage conditions (due to a rapidly changing load) being defined as faults. The delay time is programmable. An external capacitor at pin 11 is charged from an internal 75µA source. The delay period ends when the capacitor voltage reaches -3.5V. The delay time is therefore-47ms/ µF. The fault alert output (pin 10) becomes an active low if an out-of-tolerance condition persists after the delay period. When no fault exists, this output is an open collector.
An over-voltage fault activates a lOOmA crowbar gate drive output (pin 16) which can
be used to switch on a shunt SCR. Such a fault also sets an over-voltage latch ifthe reset voltage (pin 15) is above the latch reset threshold (typically 0.4V). When the latch is set
its Qoutput will pull pin 15 low through a series diode. As long as a nominal pull-up load exists, the series diode prevents Qfrom pulling pin 15 below the reset threshold.
However, pin 15 is pulled low enough to disable the driver outputs if pins 15 and 14are tied together. With pin 15 and 14 common, the regulator will latch off in response to an over-voltage fault. If the fault condition is cleared and pins 14 and 15 are momentarily pulled below the latch reset threshold, the driver outputs are re-enabled.
9-35
APPLICATION NOTE
U-95
16 CROWBAR GATE
' - - . . _ - - - - 1 1 5 O.V. LATCH & RESET
- - - - - - 1 - - 1 - - - - - - - - - - - - ' 14 COMPENSATION/SHUTDOWN
~+----+----+----------l11 FAULT DELAY
THERMAL SHUTDOWN
Figure 14. Fault Circuitry
An internal "delay reset latch" prevents crowbar turn-on when an under-voltage condition is immediately followed by a transient over-voltage condition. Such a situation could arise from a momentary short circuit at the supply output.
A thermal shutdown circuit pulls the E/ A output low when junction temperatures reach 165°C, in order to protect the IC from excessive power dissipation in the drive transistor.
COMPENSATING THE FEEDBACK LOOP
A reliable design for any feedback system must yield a closed-loop frequency response which ensures unconditional stability. An optimum power supply response provides this stability while maximizing broadband gain for good dynamic voltage regulation with changing loads. Figure 15 illustrates such a response. The OdB crossover frequency (fc) should be as high as possible while maintaining phase margin above -360° at all lower frequencies (Nyquist stability criterion). In practice, this critefion dictates a single-pole response below fc.
9-36
APPLICATION NOTE
U-95
Gain As high as possible
(dB) t '· ... 40-+-~---'o.
-20dB/dec 20
~ As high as possible
0-r-------~----"l<c-----~
Frequency (log scale)
~
Phase
fc
oo+-~----------+-·-----
-900 -180°
--z- -180° due to negative feedback
-270° -360°
phase margin
Circuit Oscillates if Phase
reaches -360° when Gain is > OdB
Figure 15. Desired Closed-Loop Response
Linear supplies using the UC1834 will usually have a current limiting loop in addition to the voltage control loop, as illustrated for two basic configurations* in Figure 16. Both loops must be stabilized for reliable operation. This is accomplished by appropriately compensating the E/ A and CS/ A at their common output (pin 14). Design of the compensation networks will often require an iterative procedure, since the compensation for one loop will affect the response of the other. A straightforward approach is outlined below:
I). Determine the frequency response of all voltage loop elements excluding the E/ A. Appendix I offers guidelines for this step.
2). Design E/ A compensation giving a frequency response which , when added to the response calculated in step I, will yield a total loop characteristic consistent with the objectives outlined above. (Appendix II.)
3). Calculate the current loop response and determine whether it satisfies the Nyquist stability criterion. (Appendix III.) If not, add additional compensation and then recalculate the voltage loop response.
4). Iterate if necessary.
*All other configurations of Figure 3 are variants of these two, and can be treated in essentially the same ways.
9-37
APPLICATION NOTE
CONFIGURATION I
VOLTAGE LOOP a.
CONFIGURATION II
U-95
b.
ReE
CURRENT LOOP
c.
d.
Figure 16. Voltage and Current Loops for Two Basic Configurations
EXAMPLE
Figure 17 shows a 5V, 5A (positive output) supply of the class shown in Figures 16a, c. This circuit tends toward instability when it is lightly loaded because of the high gain (~ = 200) of the pass transistor at low currents. Output capacitor C2 is needed to introduce a pole which rolls off the gain of the voltage loop to OdB at IOOkHz, avoiding instability due to the additional phase shift of a transistor pole at:
fT 50MHz
f = ---- =
=.250kHz
~
200
Assuming a minimum load of IA (RL = 50), the low frequency voltage loop gain, excluding the E/ A, is (from Appendix I):
I
0.5lk0
Av = 1- sn · 200 · 50 · (I.7 + o.51) kn = 20 = 26dB.
9-38
APPLICATION NOTE
V1N+
(5.Sto 12V)
R,
2.2µF c;I (TANTALUM) im
01 :GE D45VHI
U-95
Figure 17. O.SV Input-Output Differentlal SA Positive Regulator
A pole at 5kHz is required in order to roll offfrom 26dB to OdB at 1OOkHz. The required value of C2 is therefore given by:
1
1
C2 = 21r · RL · fp = 27r · 50. 5kHz = 6.4µF (6.8µF used).
The dashed curves ofFigure l 8a show the resulting voltage loop response, excluded the compensated E/A. Notice that the 5kHz pole Gustadded) itselfintroduces undesirable phase lag. This can be corrected by positioningthe compensation zero (see Appendix II) atthesamefrequency. With Ra=6800(providing-OdB E/ Again above 5kHz), then:
C5 =
1
= .041µF.
27r · 6800 · 5kHz
The gain and phase of the compensated E/ A (dotted lines) and complete voltage loop (solid lines) are also shown in Figure 18a.
The resulting current loop response (Figure 18b) is seen to meet the stability criterion. Gain above 5kHz is given by (from Appendix III):
1
1
A1=--·6800 · --··200·0.0180=2.3 =7.4dB.
700
150
9-39
APPLICATION NOTE
U-95
I
Key:
--- Without E/A
···· E/A alone +-
- Total loop
~ 60
20
r=;: 1 .......
0
~
t
40
GAIN
~
(dB)
20
I
0
""- ~
-20
-20
~
10 100 lk lOk lOOk lM lOM lOOM _ FRE?~z~Ncv_
10 100 lK lOK lOOK lM lOM lOOM
r--..... .. ... ·····... 0+--+-~.t--+-.,..-+----+----+-----+--
-65
.......
-90 b...
... ~
·· ...
-135
~' .....
-180+---+--+---+--;~----.------t~--i--t--
t
PHASE (degrees)
I
0 -90 -180
a.
b.
Figure 18. Loop Responses for Circuit of Figure 17 a. Voltage Loop b. Current Loop
Reasonable phase margin (-40°) is maintained as the transistor and CS/ A poles roll off this small gain to OdB.
Figure 19 shows the UC 1834 used to implement a negative output supply. A Darlington pass element provides adequate gain for operation at output current levels up to lOA.
CONCLUSION
Ever-increasing requirements for improved power supply economy and efficiency have produced a need for a versatile control IC capable of minimizing power losses in linear regulators. The UC1834 meets this need while also supporting all the auxilliary functions required of such supplies. This control circuit provides for optimized performance in a broad range of linear regulators, and in fact extends the range of applications for which such regulators are appropriate.
9-40
APPLICATION NOTE
U-95
j ,,~
39k lOk 20k
.47µF
FAULT .OOlµF
lk
UC1834
9
lk
V1N+
INV.
2 -2.0V
8 N.I. f - - - - - + - + - - - - > - - - -
3
12
+l.5V
D. SINK
4
16
6k
VTH
C.B. GATE
NC
5 V1N"
10 ALERT '-----------'
6 s-
15 RESET
7 S+
COMPf-1-4__..___.,.___ ___.
11 F. DELAY D. SOURCE
~RESET
2.2µF TANTALUM
13 .OOlµF
lOQ lW
lk
UPT721
V1N"
(-13 to -15V)
.om
UBT430
Figure 19. -12V, -10A Negative Regulator
.022µF CERAMIC
Vour·
(-12V)
9-41
APPLICATION NOTE
APPENDIX I· FREQUENCY RESPONSE OF VOLTAGE LOOP ELEMENTS
A. The configuration of Figure 16a has, in addition to the compensated E/ A, the following loop elements:
· Drive Transistor - RE allows operation of the driver as an emitter follower. Together these elements have an effective small signal AC conductance of I/RE.
· Pass Transistor - Low frequency gain (/3) and unity-gain frequency (ft) are usually specified. The pass transistor adds a pole to the loop transfer function at fp =fr/ f3. Therefore, in order to maintain phase margin at low frequencies, the best choice for a pass device is often a high frequency, low gain switching transistor. Further improvement can be obtained by adding a base-emitter resistor (RBE in Figure 16a) which increases the pole frequency to:
U-95
where:
re =
-kT
=
0.026mV ---
(at
T
=
300K).
qlc
le
· Load Impedance - Load characteristics vary greatly with application and operating conditions. The most commonly used models and their respective (s domain) transfer functions are given in Table 1. Note that there are no poles in the transfer functions of those loads which lack shunt capacitance. This can result in a loop transfer function which cannot be rolled off to OdB at a suitably low frequency using simple E/ A compensation networks. For this reason a shunt output capacitor is often added to supplies which must drive loads having low or indeterminant capacitance.
·Voltage Divider - The output sensing network introduces a gain of R2/(R1 + R2).
· Total Loop Gain, excluding the E/ A, is therefore given by:
A v = -Ve- =
1 -·f3pAss·ZL,·
R2 --
Vf RE
Ri + R2
/fre) forf<fr- ( 1 + - -
13
RBE
B. The circuit of Figure 16b has a more straightforward response, since the only element (other than the E/ A) which introduces any gain is the voltage divider:
9-42
APPLICATION NOTE
Load Model
o---i
0-{R
Transfer Function
ZL(s) =R
J]R R ZL(S) =1 + sRC
] } R(l + s(ESR)C) ZL(s) =1 + s(R + ESR)C
Poles @f =
--
-1-
21T RC
1 27T(R + ESR)C
U-95
Zeros@ f =
--
--
1 27T(ESR)C
]
ZL(s) =R + sL
--
-R -
21T L
TI ~ s(s + ) ZL(s) =
-R/L ±...) R2/L2 - 4/LC
R
1
41T
82 + - - s + - -
L
LC
0, -R-
21T L
Table 1. Load Models and their Transfer Functions
9-43
APPLICATION NOTE
APPENDIX II · ERROR AMPLIFIER RESPONSE
Figure 20 shows the open-loop gain and phase response of the UC1834 E/ A when lightly loaded. The gain curve represents an upper limit on the gain available from the compensated amplifier. Note that a second-order pole occurs near 800kHz. Stable circuits will require a OdB crossover well below this frequency (fc :S 500kHz).
The E /A can be compensated with or without the use oflocal feedback. When operated without such feedback (Figure 2la) the transconductance properties of the E/ A become evident; i.e. the voltage gain in given by:
where:
Av(E/A) = gM Zc
1
gM """ 700!1 = l .4mS
(f :S 500kHz)
U-95
60
~
al
8Cl 40
I z
"''"w 20
'":<:;(
~
OUTPUT AT PIN 14 WITH 820pF TO GND.
= T1 25°C
":i:
)>
~ I
0
90 8;g
m
180
-20~-~--~-~--~-~
10
100
lK
!OK
lOOK
lM
FREQUENCY - HERTZ
Figure 20. Error Amplifier Gain and Phase Frequency Response
When the E/A has local feedback (Figure 2lb), its gain is, to a first approximation, independent of transconductance:
AV(E/A) =-ZFZIN
(f$500kHz)
KVo
VREF
KVo
a.
b.
Figure 21. E/A Compensation (a.) Without and (b.) With Local Feedback
9-44
APPLICATION NOTE
However, the use of local feedback creates an additional loop which must be independently stable. The UC1834 has no internal compensation to ensure this stability, so additional external compensation is usually required. An 820pF capacitor
from the E/ A output to ground will stabilize this inner voltage loop while also
enhancing current loop stability.
An additional drawback to the use of local feedback is that ZF places a DC load on the
E/ A output. With a transconductance amplifier this results in additional input offset
voltage:
U-95
This offset results in degradation of DC regulation. The problem can be averted by taking local feedback from the emitter of the drive transistor if the driver is configured as an emitter-follower.
Whatever the compensation scheme, the UC1834 E/ A output can sink or source a
maximum of lOOµA.
Table 2 shows two typical compensation schemes and the resulting E/ A transfer
functions. The first of these circuits is most widely used.
Compensation Circuit
~o~
VREF
+
R
IC
-
E/ A Gain (AV(E/A)(s)
1gM,(l + sRC) Av=
sC
Poles@ f = 0
Zeros@ f = 21rRC
RF Av=
RIN (I + s RFCF)
211" RFCF
Table 2. E/A Compensation Circuits and Gain Response
9-45
APPLICATION NOTE
APPENDIX III- FREQUENCY RESPONSE OF THE CURRENT LOOP
· CS/A - Figure 22 shows the open-loop gain and phase response of the UC1834 CS/ A. This is also a transconductance amplifier, having~..., 1/700 = 14mS. The
voltage gain is analogous to that ofthe E/ A. The E/ A compensation impedance (Zc
or ZF(E/A)) is also seen by the CS/ A output. For purposes of small signal AC analysis, the CS/A will always see this impedance as being returned to ViN (as shown in Figures· 16c, d) when the E/ A is compensated by either of the methods shown in Table 2.
u~gs
OUTPUT AT PIN 14 WITH 820pf TO GND. T1 = 2 5 ' C
~.,
8
0
j! i-:::---+---+-~-+---+---i 0 ~
I I
z :;;:
""s""''
40 1-_;_+_......::::,,...._+~~r---l 90
I
> 0
20
Q..__ _.__ _..__ _.__ _..__ _.
10
100
lK
!OK
lOOK
lM
FREQUENCY - HERTZ
Figure 22. Current Sense Amplifier Gain and Phase Frequency Response
· Pass Transistor - Introduces current gain p to the loop transfer of both basic
configurations (Figures 16c, d).Considerations outlined in Appendix I also apply here.
· Sense Resistor - Resistance value RsENSE appears in transfer function for both configurations.
· Drive Transistor - In the circuit of Figure l 6c, RE allows operation of the driver as an emitter-follower. Effective conductance is I/RE.
Closed-loop responses are given by the following:
for circuit of Figure 16c:
A1
=·gM
· Zc
·
1 --
· P · RsENSE
RE
for circuit of Figure 16d:
( f < 500kHz,
f < ~ (1
/3
+
,Pre )) RBE
Zc
A1 =·~ · Zc + PZL · p · RsENSE
T ( f < 500kHz, f < f!T
·Unitrode Integrated Circuits Corporation
7 Continental Boulevard.· P.O. Box 399 ·Merrimack, New Hampshire· 03054-0399
Telephone 603-424-2410 · FAX 603-424-3460
9-46
( 1 + RP~reE ))
n n INTEGRATED
~CIRCUIT&
-uNITRODE
APPLICATION NOTE
U-96A
A 25 WATT OFF-LINE FLYBACK SWITCHING REGULATOR
Introduction
This Application Note describes a low cost (less than $10.00) switching power supply for applications requiring multiple output voltages, e.g. personal computers, instruments, etc...The discontinuous mode flyback regulator used in this application provides good voltage tracking between outputs, which allows the use of primary side voltage sensing. This sensing technique reduces costs by eliminating the need for an isolated secondary feedback loop.
The low cost, (8 pin) UC3844 current mode control chip employed in this power supply provides performance advantages such as:
1) Fast transient response 2) Pulse by pulse current limiting 3) Stable operation
To simplify drive circuit requirements, a T0-220 power MOSFET (UFN833) is utilized for the power switch. This switch is driven directly from the output of the control chip.
Power Supply Specifications
1. Input voltage: 95VAC to 130VAC (50Hz/60Hz)
2. Output voltage: A. + 5V, ±5%: 1A to 4A load Ripple voltage: 50mV P-P Max. B. +12V, ±3%: 0.1A to0.3A load Ripple voltage: 100mV P-P Max. C. -12V, ±3%: 0.1A to 0.3A load Ripple voltage: 100mV P-P Max.
3. Line Isolation: 3750 Volts
4. Switching Frequency: 40KHz
5. Efficiency @ Full Load: 70%
Basic Circuit Operation
The 117VAC input line voltage is rectified and smoothed to provide DC operating voltage for the circuit. When power is initially applied to the circuit, capacitor C2 charges throuqh R2. When the voltage
across C2 reaches a level of 16V the output of IC1 is enabled, turning on power MOSFET 01. During the on time of 01, energy is stored in the air gap of transformer (inductor) T1. At this time the polarity of the output windings is such that all output rectifiers are reverse biased and no energy is transferred. Primary current is sensed by a resistor, R10, and compared to a fixed 1 volt reference inside IC1. When this level is reached, 01 is turned off and the polarity of all transformer windings reverses, forward biasing the output rectifiers. All the energy stored is now transferred to the output capacitors. Many cycles of this store/release action are needed to charge the outputs to their respective voltages. Note that C2 must have enough energy stored initially to keep the control circuitry operating until C4 is charged to a level of approximately 13V. The voltage across C4 is fed through a voltage divider to the error amplifier (pin 2) and compared to an internal 2.5V reference.
Energy stored in the leakage inductance of T1 causes a voltage spike which will be added to the normal reset voltage across T1 when 01 turns off. The clamp consisting of D4, C9 and R12 limits this voltage excursion from exceeding the BVDSS rating of 01. In addition, a turn-off snubber made up of 05, C8 and R11 keeps power dissipation in 01 low by delaying the voltage rise until drain current has decreased from its peak value. This snubber also damps out any ringing which may occur due to parasitics.
Less than 3.5% line and load regulation is achieved by loading the output of the control winding, Ne, with R9. This resistor dissipates the leakage energy associated with this winding. Note that R9 must be isolated from R2 with diode D2, otherwise C2 could not charge to the 16V necessary for initial start-up.
A small filter inductor in the 5V secondary is added to reduce output ripple voltage to less than 50mV. This inductor also attenuates any high frequency noise.
9-47
APPLICATION NOTE
U-96A
25W OFF·LINE FLYBACK REGULATOR
RI 50 IW 117 VAC
DI
VARO VM68
Cl .
Rl2
~~~F
4.7K 2W
R2 56K 2W
R4
R3
4.7K
20K
R5 150K
C2
~g~F
UC3844
02 IN36!2
C5
4
.OlµF
C9 3300pF GOOV
Np 04 IN3613
03 !N3612
06 USD945
L1 (Note.2)
--
+5V
N5 CIO
Cll 4700µF
IOV
COM 07
+12V
Cl2 2200µF IGV
±12V COM
Cl3 2200µF
16V
-12V
RIO
0.550 IW
cs
680pF 600V
05 IN3613
Rli
2.7K 2W
Notes: 1. All resistors are 114 watt unless noted 2. See Appendix for construction details
BLOCK DIAGRAM
f---<>---+---e----------~8 14
VREF 5.0V 50mA
v,.
COMP CURRENT SENSE
Note: LlfiZill A= DIL-8 Pin Number. B = S0-14 Pin Number. 2. Toggle flip flop used only in 1844 and 1845.
UC3842/3/4/5 CURRENT MODE PWM CONTROLLER
9-48
APPLICATION NOTE
TYPICAL SWITCHING WAVEFORMS
U-96A
T0 n - Drive waveforms
T0 ff - Drive waveforms
5V/DIV - - - - - 200mA/DIV - - - - -
Upper trace: Q, - Gate to -source voltage Lower trace: Q, - Gate current
Upper trace: Q, - Gate to source voltage Lower trace: Q, - Gate current
100V/DIV 0.5A/DIV
5A/DIV 50mV/DIV
Upper trace: Q, - Drain to source voltage Lower trace: Primary current - 10
Upper trace: + 5V charging current Lower trace: +5V output ripple voltage
9-49
APPLICATION NOTE
PERFORMANCE DATA
CONDITIONS
Low Line (95VAC)
5Vout
12Vout
± 12@ 100mA
+5V@ 1.0A 4.0A
± 12@ 300mA
+5V@ 1.0A 4.0A
Nominal Line (120VAC)
5.211 4.854 5.199 4.950
12.05 12.19 11.73 11.68
± 12@ 100mA
+5V@ 1.0A 4.0A
± 12@ 300mA
+5V@ 1.0A 4.0A
High Line (130VAC)
5.220 4.875 5.208 4.906
12.07 12.23 11.73 11.67
± 12@ 100mA
+5V@ 1.0A 4.0A
± 12V@ 300mA
+5V@ 1.0A 4.0A
Overall Line and Load Regulation
5.207 4.855 5.200 4.902
±3.5%
12.06 12.21 11.71 11.66
±2.3%
U-96A
-12Vout
-12.01 -12.14 -11.69 -11.63
-12.03 -12.18 -11.68 -11.62
-12.02 -12.15 -11.67
11.61 ±2.4%
!C's
IC1
UC3844
POWER MOSFET
01
UFN833
RECTIFIERS
01
VM68 varo
02, 03 1N3612
04, D5 1N3613
D6
USD945
07, 08 UES1002
PARTS LIST
CAPACITORS
C1
250µF, 250V
C2
100µF, 25V
C3
0.22µF, 25V
C4
47µF, 25V
C5
.01µF, 25V
C6
.0047µF, 25V
C7
470pF, 25V
C8
680pF,600V
C9
3300pF,600V
C10, C11 4700µF, 10V
C12, C13 2200µF, 16V
C14
100pF,25V
RESISTORS
R1
5Q, 1W
R2
56K, 2W
R3
20K
R4
4.7K
R5
150K
R6
10K
R7
22Q
RB
1K
R9
6BQ, 3W
R10
0.55Q, 1W
R11
2.7K, 2W
R12
4.7K, 2W
R13
20K
MAGNETICS
T,
see appendix
L,
see appendix
9-50
APPLICATION NOTE
APPENDIX
POWER TRANSFORMER-T1
Core: Ferroxcube EC-35/3C8 Gap: 10 mil in each outer leg
NOTE: For reduced EM/ put gap in center leg only. Use 20 mil.
Ferroxcube EC-35/3C8
U-96A
TRANSFORMER CONSTRUCTION
Control Winding
N=10, AWG 30 2 in parallel
00000000 _..- 2 layers, 3M mylar tape
+ 5V out, N = 4, AWG 26, - 00000000
6 in parallel
00000000 - ±12V windings N = 9, AWG30
2
layers 3M
mylar
tape
~ ~
0
0
0
0
0
0
0
\r ''-
"'-.._
2 wires in parallel, bifilar wound
Bobbin-35PCB1
Primary N = 45, AWG 26
SV OUTPUT INDUCTOR
N=4, AWG 18
____ry-y-y'"'\_
Ferroxcube 204 T 250 - 3C8 (toroid)
Unitrode Integrated Circuits Corporation 7 Continental Boulevard. ·P.O. Box 399 ·Merrimack, New Hampshire· 03054-0399 Telephone 603-424-2410 · FAX 603-424-3460
9-51
Ln:::::nJ INTEGRATED CIRCUITS
-UNITRDDE
APPLICATION NOTE
MODELLING, ANALYSIS AND COMPENSATION OF THE
CURRENT-MODE CONVERTER
U-97
Abstract
As current-mode conversion increases in popularity, several peculiarities associated with fixed-frequency, peak-current detecting schemes have surfaced These include instability above 50% duty cycle, a tendencv towards subharmonic oscillation, non-ideal loop response, and an increased sensitivity to noise. This paper will attempt to show that the performance of any current-mode converter can be improved and at the same time all of the above problems reduced or eliminated by adding a fixed amount of" slope compensation" to the sensed current waveform.
1.0 INTRODUCTION
The recent introduction of integrated control circuits designed specifically for current mode control has led to a dramatic upswing in the application of this technique to new designs. Although the advantages of current-mode control over conventional voltage-mode coritrol has been amply demonstrated(l-5), there still exist sever8! drawbacks to a fixed frequency peak-sensing current mode converter. They are ( 1) open loop instability above 50% duty cycle, (2) less than ideal loop resP.Onse caused by peak instead of average inductor current sensing, (3) tendency towards subharmonic oscillation, and (4) noise sensitivity, particularly when inductor ripple current is small Although the benefits of current mode control wili in most cases, far out-weight these drawbacks, a simple solution does appear to be available. It has been shown by a number of authors that adding slope compensation to the current waveform (Figure 1) will stabilize a system above 50% duty cycle. If
one is to look further, it becomes apparent that this same compensation technique can be used to minimize many of the drawbacks stated above. In fact, it will be shown that any practical converter will nearly always perform better with some slope compensation added to the current waveform.
The simplicity of adding slope compensation - usually a single resistor adds to its attractiveness. However, this introduces a new problem - that of analyzing and predicting converter performance. Small signal AC models for both current and voltage-mode PWM's have been extensively developed in the literature. However, the slope compensated or "dual control" converter possesses properties of both with an equivalent circuit different from, yet containing elements of each. Although this has been addressed in part by several authors(!, 2), there still exists a need for a simple circuit model that can provide both qualitative and quantitative results for the power supply designer.
POWER SWITCH
Vo
SLOPE
I
COMPENSATION
---1..
L/V-1 A
f--T-1 1
INDUCTOR
I...L.J.-r'i:f::'::1-'- ~
CURRENT
SWITCH CURRENT
~T-1
FIGURE 1 - A CURRENT-MODE CONTROLLED BUCK REGULATOR WITH SLOPE COMPENSATION.
9-52
APPLICATION NOTE
U-97
The first objective of this paper is to familiarize the reader with the peculiarities of a peak-current control converter and at the same time demonstrate the ability of slope compensation to reduce or eliminate many problem areas. This is done in section 2. Second, in section 3, a circuit model for a slope compensated buck converter in continuous conduction will be developed using the state-space averaging technique outlined in( 1). This will pnwidc the analytical basis for section 4 where the practical implementation of slope compensation is discussed.
2.1 OPEN LOOP INSTABILITY
An unconditional instability of the inner current loop exists for any fixed frequency current-mode converter operating above 50% duty cycle regardless of the state of the voltage feedback loop. While some topologies (most notably two transistor forward converters) cannot operate above 50% duty cycle, many others would suffer serious input limitations if greater duty cycle could not be achieved. By injecting a small amount of slope compensation into the inner loop, stability will result for all values of duty cycle. Following is a brief review of this technique.
A.) DUTY CYCLE < 0.5
INDUCTOR CURRENT (IL)
AI1 =-Alo (m2 + m) m1 +m
(2)
Solving for m at 100% duty cycle gives
(3)
Therefore, to guarantee current loop stability, the slope of the compensation ramp must be greater than one-half of the down slope of the current waveforrn. For the buck regulator of Figure l , '"2 is a
constant equal to Vo Rs, therefore, the amplitude A of the compensating L
waveforrn should be chosen such that
A> T Rs Vo
(4)
L
to guarantee stability above 50% duty cycle.
2.2. RINGING INDUCTOR CURRENT
Looking closer at the inductor current waveform reveals two additional
phenomenon related to the previous instability. If we generalize equation
2 and plot I0 vs nT for all n as in Figure 3, we observe a damped
sinusoidal response at one-half !lie switching frequency, similar to that of
an RLC circuit This ring-out is undesirable in that it (a) produces a
ringing response of the inductor current to line and load transients, and
(b) peaks the control loop gain at \.2 the switching frequency, producing
a marked tendency towards instability.
c Veo-j~
/ lR
B) DUTY CYCLE> 05
C.) DUTY CYCLE > 0.5 WITH SLOPE COMPENSATION FIGURE 2 - DEMONSTRATION OF OPEN LOOP INSTABILITY IN A
CURRENT-MODE CONVERTER
Figure 2 depicts the inductor current waveform, k. of a current-mode converter being controlled by an error voltage v·. By perturbing the
current IL by an amountAI, it may be seen graphically thatAI will
decrease with time for D < 0.5 (Figure 2A), and increase with time for D > 0.5 (Figure 2B). Mathematically this can be stated as
(I)
0 nT.-
FIGURE 3
3T
4T
5T
- ANALOGY OF THE INDUCTOR CURRENT RESPONSE TO THAT OF AN RLC CIRCUIT.
It has been shown in (I), and is easily verified from equation 2, that by choosing the slope compensation m to be equal to -rn2 (the down slope of the indu~or current), the best possible transient response is obtained. This is analogous to critically damping the RLC circuit, allowing the current to correct itself in exactly one cycle. Figure' 4 graphically demonstrates this point Note that while this may optimize inductor current ringing. it has little bearing on the transient response of the voltage control loop itself.
Carrying this a step further, we can introduce a linear ramp of slope - m as shown in Figure 2C. Note that this slope may either be added to the current waveform, or subtracted from the error voltage. This then gives
=-mz, FIGURE 4 - FOR THE CASE OF m
A CURRENT PERTURBATION
WILL DAMP OUT IN EXACTLY ONE CYCLE.
9-53
APPLICATION NOTE
U-97
2.3 SUBHARMONIC OSCILLATION
For steady state condition we can write
Gain peaking by the inner current loop can be one of the most significant problems associated with current-mode controllers. This
Dm1 T=(l -D)m2T
(8)
or
peaking occurs at one-half the switching frequency, and - because of
(9)
excess phase shift in the modulator - can cause the voltage feedback
loop to break into oscillation at one-half the switching frequency. This instability, sometimes called subharmonic oscillation, is easily detected
By using (9) to reduce (7), we obtain
as duty cycle asymmetry between consecutive drive pulses in the power stage. Figure 5 shows the inductor current of a current-mode controller in subharmonic oscillation (dotted waveforms with period 2T).
fl.IL
1
(10)
Ll.V, = 1 -2D (1 + mlmi)
Now by recognizing thatLl.IL is simply a square wave of period 2T, we
------..,,.----====---'-1).V, can relate the first harmonic amplitude toll.IL by the factor 4/TT and
write the small signal gain at f = lifs as
i=
4T1
v, 1 - 2D (l + m/m2)
(II)
If we assume a capacitive load of C at the output and an error amplifier gain of A, then finally, the expression for loop gain at f = li fs is
1--- D
f).D
L>D
i--~~~~~~~~~-2T~~~~~~~~~~~~
Loop gain
(12) I - 2D (I + m/m2)
FIGURE 5 - CURRENT WAVE FORM (DOTTED) OF A CURRENT-MODE CONVERTER IN SUBHARMONIC OSCILLATION.
To determine the bounds of stability, it is first necessary to develop an expression for the gain of the inner loop at one-half the switching frequency. The technique used in (2) will be paralleled for a buck converter with the addition of terms to include slope compensation.
2.3.1 LOOP GAIN CALCULATION AT lif,
Referring to figures 5 and 6, we want to relate the input stimulus, Ll.V,, to an output current, fl.IL. From figure 5, two equations may be written
fl.IL = Ll. D m1 T -Ll.D m1 T (4) Ll.Ve = Ll.D m1 T +Ll.D m1 T (5)
Adding slope compensation as in figure 6 gives another equation
Ll.V, = fl.Ve + 2Ll.D m T
(6)
2.3.2 USING SLOPE COMPENSATION TO ELIMINATE SUBHARMONIC OSCILLATION
From equation 12, we can write an expression for maximum error amplifier gain at f = lifs to guarantee stability as
I - 2D (l + m/m2)
Amax =
4T
(13)
n2 C
This equation clearly shows that the maximum allowable error amplifier gain, Amax. is a function of both duty cycle and slope compensation. A normalized plot of Amax versus duty cycle for several values of slope compensation is shown in figure 7. Assuming the amplifier gain cannot be reduced to zero at f = li fg, then for the case of m = 0 (no compensation) we see the same instability previously discussed at 50% duty cycle. As the compensation is increased tom= -lim2, the point of instability moves out to a duty cycle of 1.0, however in any practical
m/'112 = -2
Using(S) to eliminate fl.Ve from (6) and solving forLl.ILfLl.V, yields
(7)
FIGURE 6 - ADDITION OF SLOPE COMPENSATION TO THE CONTROL SIGNAL
1.0 DUTY CYCLE (D)
FIGURE 7 - 'MAXIMUM ERROR AMPLIFIER GAIN AT·/, t, (NORMALIZED)
V.S. DUTY CYCLE FOR VARYING AMOUNTS OF SLOPE COMPENSATION. REFER TO EQUATION 13.
9-54
APPLICATION NOTE
U-97
system, the finite value of Amax will drive the feedback loop into subharmonic oscillation well before full duty cycle is reached If we continue to increase m, we reach a point, m = -lllz, where the maximum gain becomes independent of duty cycle. This is the point of critical damping as discussed earlier, and increasing m above this value will do little to improve stability for a regulator operating over the full duty cycle range.
2.4 PEAK CURRENT SENSING VERSUS AVERAGE CURRENT SENSING
True current-mode conversion, by definition, should force the average inductor current to follow an error voltage - in effect replacing the inductor with a current source and reducing the order of the system by one. As shown in Figure 8, however, peak current detecting schemes are generally used which allow the average inductor current to vary with duty cycle while producing less than perfect input to output - or feedforward characteristics. If we choose to add slope compensation equal tom= -l> mz as shown in Figure 9, we can convert a peak current detecting scheme into an average current detector, again allowing for perfect current mode control. As mentioned in the last section, however, one must be careful of subharmonic oscillations as a duty cycle of 1 is approached when using m = -l> mi.
2.5 SMALL RIPPLE CURRENT
From a systems standpoint, small inductor ripple currents are desirable for a number of reasons - reduced output capacitor requirements, continuous current operation with light loads, less output ripple, etc. However, because of the shallow slope presented to the current sense circuit, a small ripple current can, in many cases, lead to pulse width jitter caused by both random and synchronous noise (Figure IO). Again, if we add slope compensation to the current waveform, a more stable switchpoint will be generated To be of benefit, the amount of slope added needs to be significant compared to the total inductor current not just the ripple current This usually dictates that the slope m be considerably greater than mz and while this is desirable for subharmonic stability, any slope greater than m = -i> mz will cause the converter to behave less like an ideal current mode converter and more like a voltage mode converter. A proper trade-off between inductor ripple current and slope compensation can only be made based on the equivalent circuit model derived in the next section.
Ve '-=----------------
IAVG I 1------/-:,_.q--~~+-~-~:-- IAVG 2 l---7f~-+-+--'k:-4-::-~::- IAVG 3 1-~L-4---+-:-+--+-4--_..,~-"'~
IPf.DESTAL
FIGURE 10 - A LARGE PEDESTAL TO RIPPLE CURRENT RATIO.
FIGURE 8 - PEAK CURRENT SENSING WITHOUT SLDPE COMPENSATION ALLOWS AVERAGE INOUCTOR CURRENT TO VARY WITH DUTY CYCLE
3.0 SMALL SIGNAL AC. MODEL
As we have seen, many drawbacks associated with current-mode control can be reduced or eliminated by adding slope compensation in varying degrees to the current waveform. In an attempt to determine the full effects of this same compensation on the closed loop response, a small signal equivalent circuit model for a buck regulator _will now be developed using the state-space averaging technique developed in ( 1).
3.1 AC. MODEL DERIVATION
Figure 11 a shows an equivalent circuit for a buck regulator power stage. From this we can write two state-space. averaged differential equations corresponding to the inductor current and capacitor voltage as functions of duty cycle D
FIGURE 9 - AVERAGE INDUCTOR CURRENT IS INDEPENDENT OF DUTY CYCLE AND INPUT VOLTAGE VARIATION FOR A SLDPE COMPENSATION OF m = -'h "'2·
9-55
;L = (V1 - Vo) D - Vo (1 - D)
(14)
L
L
vo=.!!.._Yll..
(15)
C R
APPLICATION NOTE
U-97
'1
(A)
Rx
v,
t:No V1 (l·D)
( m Vo) 2L(-"2_ _ _v~)
Rs 2L
Rs 2L
AV, V1
c
RsT(_i:n_-~)
Rs 2L
(B)
FIGURE 11 - BASIC BUCK CONVERTER (A) AND ITS SMALL SIGNAL EQUIVALENT CIRCUIT MODEL (B).
If we now perturb these equations - that in substitute
V1 + t:N,, Vo + t::No, D + Ll.D and IL+ LI.IL for their respective
variables - and ignore second order terms, we obtain the small signal averaged equations
(16)
between Rx and L as the slope compensation, m is changed In most cases, the dependent source between Rx and C can be ignored
If Rx is much greater than L, as is the case for little or no compensation (m = 0), the converter will have a single pole response and act as a true
current mode converter. If Rx is small compared to L (m » R~~0).
then a double pole response will be formed by the LRC output filter similar to any voltage-mode converter. By appropriately adjusting m, any condition between these two extremes can be generated.
Of part1.cu1ar m. terest 1.s the case when m = ~ Rs Vo s·mce the down
slope
of the
m. ductor
current
(m2
from
Fi.gure
6 )
.
is
equal
t oR-sLV-o,
we
can write m = -Yim2. At this point, Rx goes to infinity, resulting in an ideal current mode converter. This is the same point, discussed in section. 2.4, where the average inductor current exactly follows the error voltage. Note that although this compensation is ideal for line rejection and loop response, maximum error amp gain limitations as higher duty cycles are approached (section 2.3) may necessitate using more compensation.
Having derived an equivalent circuit model, we may now proceed in its application to more specific design examples. Figure 12 plots open loop ripple rejection (LI.Vo/LI.Vi) at 120Hz versus slope compensation for a typical 12 volt buck regulator operating under the following conditions:
· =LI.IL_ LI.Vo
(17)
LI.Vo
C CR
A third equation - the control equation - relating error voltage, V,, to duty cycle may be written from Figure 6 as
(l -D)V0 TRs
(18)
ILRs = V, - mDT -
2L
Perturbing this equation as before gives
LI.IL= -L-l.-VL, I.OT (- m -V-o) - -T( ! - D)Ll.Vo (19)
Rs
Rs 2L 2L
By using 19 to eliminate LI. D from 16 and I 7 we arrive at the state-
space equations (20)
LI.Vo V1 (I - D)
2lJ (~-Vo) LT(-"2..- Vo)
Rs 2L
Rs 2L
(21)
An equivalent circuit model for these equations is shown in Figure 11 B and discussed in the next section.
3.2 A.C. MODEL DISCUSSION
The model of Figure 11 B can be used to verify and expand upon our previous observations. Key to understanding this model is the interaction
Vo
12V
v,
25V
L
200µH
c
300µf
T
20µS
Rs
.50
~
lo, 120
Again, as the slope compensation approaches -\Om2, the theoretical ripple rejection is seen to become infinite. As larger values of m are introduced, ripple rejection slowly degrades to that of a voltage-mode converter (-6.4dB for this example).
-70
'e°. -{)0
N
I
0
~
-50
>-
""z
;0::
-40
(w.) Ul -30
"w '
~
°'0. -20
-10..__~-'-~-'-~~'--~-'-~......L~~'--~-'-~-' 0 -0.5 -I -1.5 -2 -2.5 -3 -3.5 -4
SLOPE COMPENSATION (m/m2)
FIGURE 12 - RIPPLE REJECTION AT 120Hz V.S. SLOPE COMPENSATION FOR lAMP AND 12AMP LOADS.
9-56
APPLICATION NOTE
U-97
If a small ripple to D.C. current ratio is used, as is the case For Rt, =
I ohm in the example, proportionally larger ·values or slope compensation
may be injected while still maintaining a high ripple rejection ratio. In
other words, to obtain a given ripple rejection ratio. the allowable slope
compensation varies proportionally to the average D.C. current, not the
ripple current This is an important concept when attempting to
minimize noise jitter on a low ripple converter.
R1
UC1846
Figure 13 shows the small signal loop response (.6.Vo/.6.Ye) versus Frequency for the same example oF Figure 12. The gains have all been normalized to zero dB at low frequency to reflect the actual difference in Frequency response as slope compensation m is varied. At m = -\0 "'2, an ideal single-pole roll-off at 6dB/octave is obtained. As higher ratios are used. the response approaches that of a double-pole with a I 2dB/octave roll-off and associated 180° phase shift.
IL) Rs
--<1>-------------1
(a) SUMMING OF SLOPE COMPENSATION DIRECTLY WITH SENSED CURRENT SIGNAL
10
z
~ ~:, : -10
<:J <:J ~-20
~
a. -30
§
13 -40 '::!
:<:C:; ~o
~
VsENSE
10
100
lK
FREQUENCY (HERTZ)
(b) SUMMING OF SLOPE COMPENSATION WITH ERROR SIGNAL !OK
FIGURE 13 - NORMALIZED LOOP GAIN V.S. FREQUENCY FOR VARIOUS SLOPE COMPENSATION RATIO'S.
UC1846
(c) EMITTER FOLLOWER USED TO LOWER OUTPUT IMPEDANCE OF OSCIUATOR.
FIGURE 14 - ALTERNATIVE METHODS OF IMPLEMENTING SLOPE COMPENSATION WITH THE UC1846 CURRENT-MODE CONTROUER.
REFERENCES
(1) Shi-Ping Hsu, A. Brown, L Rensink, R Middlebrook, "Modelling
4.0 SLOPE COMPENSATING THE UC1846 CONTROL I.C.
and Analysis of Switching DC-tc>-DC Converters in Constant-
Implementing a practical, cost effective current~ritode converter has
Frequency Current-Programmed Mode," PESC '79 Record (IEEE Publication 79CH1461-3 AES), pp. 284-301. ·
recently been simplified with the introduction of the UC! 846 integrated
control chip. This I.C. contains all of the control and support circuitry
(2) E. Pivit, J. Saxarra, "On Dual Control Pulse Width Modulators for
required for the design of a fixed frequency current-mode converter. Figures 14A and B demonstrate two alternative methods of implementing
Stable Operation of Switched Mode Power Supplies", Wiss. Ber. AEG-Telefunken 52 (~79) 5, pp. 243-249.
slope compensation using the UC1846. Direct summing of the compensation and current sense signal at Pin 4 is easily accomplished,
(3) R Red!, I. Novak, "Instabilities in Current-Mode Controlled
however, this introduces an error in the current limit sense circuitry. The
Switching Voltage Regulators," PESC '81 Record (IEEE Publication
alternative method is to introduce the compensation into the negative
81CH1652-7 AES), pp. 17-28.
input terminal of the error amplifier. This will only work if (a) the gain of the error amplifier is fixed and constant at the switching frequency
(4) W. Bums, A. Ohri, "Improving Off-Line Converter Performan~e
(R1/R2 for this case) and (b) both error amplifier and current amplifier
gains are taken into consideration when calculating the required slope
case,. compensation. In either
once the value of Ri has been calculated,
with Current-Mode Control," Powercon IO Proceedings, Paper B-2, 1983.
the loading effect on Cr can be determined and, if necessary, a buffer
(5) B. Holland, "A New Integrated Circuit for Current-Mode Control,"
stage added as in Figure 14C.
Powercon 10 Proceedings, Paper C-2, 1983.
Unitrode Integrated Circuits Corporation
7 Continental Boulevard.· P.O. Box 399 ·Merrimack, New Hampshire· 03054-0399
Telephone 603-424-2410 · FAX 603-424-3460
9_57
n n L_::::J
INTEGRATED CIRCUITS
-UNITRODE
APPLICATION NOTE
U-99
UC3717 and L-C Filter Reduce EMI and Chopping Losses in Step Motor
Achopper drive which uses the inductance of the motor as Jhe controlling element causes a temperature rise in the motor due to hysteresis and eddy current losses. For most motors, espe:icially solid rotor constructions, this extra heat can force the designer to go to a larger motor and then derate it, or to a more expensive laminated construction in order to produce enough output torque for the job. Regardless of the motor type, any extra heat generated within a system will have to be removed or else other system components will be stressed unnecessarily. This could mean using a fan where convection cooling might otherwise have sufficed. In addition, the EM I generated from both the motor and its leads is of serious concern to the designer in view of ever-increasing EM I regulations.
These problems can be virtually eliminated by borrowing a simple technique from switching power supply designs, i.e., by placing a properly designed low-pass l.:C filter across the output and
using this L to control the UC3717. This removes the high fre-
quency AC chopping losses in the motor by providing it with almost pure DC current. It also confines the EM I-causing, high frequency AC components to within the driver where they are easier to handle. This could allow increased wire lengths and possibly free up some design constraints, but remember that even though DC emits no EMI, the driver will still commutate the windings and can produce some components of frequency as high as 10 kHZ. The design of the l.:C filter is straight-forward and its small additional cost can be recovered easily. The Unitrode UC3717.. a complete chopper drive for one phase winding on a monolithic IC, makes the design job simple. The end result, a cooler running and EMI quieter step motor, can be achieved with just a few additional passive components.
Preliminary Considerations
For our analysis, we will use a" 23" frame, bipolar motor with a solid rotor and the following specifications:
Pm,, = Ym,, =
9.0 Watts 3.75 Volts
1.25 Amps
3.0 Ohms 8.4 mH
=Maximum power dissipation at 25°C = Maximum voltage per motor phase at
25°C = Maximum current per motor phase at
25°C = Resistance of one phase at 25°C = Inductance of one phase winding
*It should be noted that Lm, as given in a manufacturer's data sheet, is not always true average inductance as seen at high current in a circuit, but rather the inductance reading you would obtain from a low current inductance bridge. This value can differ from in-circuit inductance by a factor of 2 or more! The in-circuit inductance for this motor is 5.0 mH.
We begin by calculating the electrical time constant of one
phase winding using the resistance value given above and the actual motor inductance:
Tm =.li,, = 5 .o mH = 1.67 msec
(1)
Rm 3.0 Ohms
If one were using a standard voltage drive then it would take approximately Tm or 1.67 msec to reach the current level required for proper operation. This places a severe restriction on motor
speed. Increasing the drive voltage will allow the motor to run taster but will cause it to draw too much current and overheat. Maximum motor speed may be increased by decreasing the time constant. Since Lm is fixed, the only parameter we can change is the effective value at Rm by placing a' resistor in series with it. If we place a resistor 4 times Rm in series such that total R is 5 times Rm and increase the drive voltage by a factor of 5 then we will have reduced the time constant by a factor of 5 to 330 µsec and also increased both the maximum motor speed and maximum power output by a factor of 5 each. Unfortunately, we will have increased wasted power by a factor of 5 also.
The Chopper Drive
Using a chopper drive enables one to run at a higher voltage and thus reach proper operating current faster while still protecting the motor from excessive current that would otherwise flow due to the higher voltage. The high voltage .is first applied across the motor winding and then, when Im,, is reached, it is switched off. (If it were not switched off then the maximum current rating of the motor would be quickly exceeded.) The current is then allowed to circulate in a loop within the driver and motor for a fixed time period (t011) after which the voltage is re-applied to the motor. The operating frequency, which is determined by both the motor
inductance and t,,, should be high enough that the resulting cur-
rent ripple is small compared to the average DC current. Power efficiency is relatively high because there is no external resistor used.
Nothing is free in the world of physics, however, and the price one pays for the extra power output capability is an increase in wasted heat due to hysteresis and eddy current losses within the motor instead of in an external resistor. Being within the motor, it can now cause overheating as well as reliability problems. Since the excess heat increases rapidly with the overdrive ratio, this means that at low overdrive ratios (less than 5-to-1) there will be almost negligible heating, but at higher overdrive ratios (more than 10-to-1) the induced motor losses can beome as great as, or actually exceed, the 12R losses! By placing a low-pass l.:C filter in the circuit these induced losses can once again become negligible. The L and C components selected should be capable of operating at frequencies of 25 kHz or higher without heating effects in the inductor core or inductive effects in the capacitor.
9-58
APPLICATION NOTE
U-99
UC3717 and L-C Filter
Designing with the UC3717
Using a supply voltage (vJ of 40 volts (approximately a 10/1 overdrive), the turn-on rise-time becomes:
= = t,;,. -Tm x Ln (1 - V./VJ -1.67 x 10-a x Ln (1 - 3.75 / 40)
= 164 µsec
(2)
or an improvement of approximately 10-to-1 in speed capability.
Using an off-time (t.,.) of 30 µsec as suggested on the UC3717
data sheet and limiting current (I.) to 850 mA establishes a voltage
across the resistive component of the winding (V..00).during the "on" time of:
v·.00 = 1. x R. = .85 x 3.0 = 2.55 Volts
(3)
and during the" off' time (due to a 2.6 volt drop across the upper transistor, as shown in the data sheet, and a 0.4 volt drop across
the Schottky" catch" diode) of:
= = = V..0· V,..,.,.01 + Vd"""' 2.6 + 0.4 3.0 Volts
(4)
Since the voltage and current changes are small, we can substitute a resistance (R.)equivalent to V..0.fl. in series with R.to adjust the lime constant and allow us to calculate the approximate current ripple (Al.) during i.,.:
Al.
=
I. ( 1 -
exp_
[-
t,,,,(R. +
Lm
R.)l )
J
= .85 x ( 1 - exp
[ - 3Qx10'6 x (3.~ + 3.5)] )
5x10
= 33 mA p-p
(5)
high frequencies and still pass normal commutation currents without any significant loss of motor performance.
Design of the L-C Filter
Figure 2 is a block diagram of a motor connected to 2 UC3717s with the low-pass l-C filters in place.
Again we will use a current of 850'mA in each winding, an offtime of 30 µsec, and an on-time of 4.4 µsec but now we will use an
PHASE A
'··
L
c
0
STEPPER MOTOR
PHASE B
..·
Figure 2- Low-pass L-C filters on outputs.
Knowing Al·· we can now calculate the on-time (!,,,):
v, - t.,, = ~ = = 33x10'3 x 5x10" 4.4 µsec
VW·OO
40 - 2.55
(6)
and can also find our operating frequency (f) by:
= f 1 I (t00 + !,,.) = 1 I (4.4 + 30) x 10 6 = 29.1 kHz
(7)
VERT= 10 mA I DIV
HORIZ = 5 µsec I
OJV
external inductance (L) to control the chopping. Vd·o· is the sum of
the source (V.;J and sink (V.) voltage drops at 850 mA:
Vd""' = V,,, + v. + V.,,,. = (2.6 + 1.9 + 0.36)
= 4.9 volts
(8)
In order to minimize the effects of Lon the motor current risetime we will make it 10 times smaller than Lm or 500 µH. In order to keep the peak current in the UC3717 below 1 amp we will use a 0.42 ohm sense resistor and also limit.IL to 300 mA. Using a variation of equation (6) we can checkUiet:
= = = L (V,-Vd,,0 )x !00 (40 -4.9) X 4.4x10'6 515 µH
(9)
·IL
300x10"
is in keeping with the constraints outlined above. Similarly, we would like to find a value for the capacitor (C) such
that it will have less than 1/10 the i11Jpedance of Lat 29.1 kHz:
c -
10
-
10
(10)
- (2 x n x f)2 x L - (2 x 3.14 x 29100)2 x 500x10..
= 0.6 µF
Figure 1. A-C component of motor current for standard chopper configuration.
Since this frequency is well above audible ranges, it will not cause any objectionable sound, but there are still the problems of EMI and excess motor healing to deal with. It is possible to generate EMI due to the current switching that occurs in the motor leads because they carry not only the primary frequency, but also many higher harmonics as well, so they require careful routing, shielding, or both. We can put in a low pass l:C filter to remove these
The test motor and driver, operated unloaded (nothing connected to the output shaft) and in the configuration of Figure 2, used values of 500 µH for the inductor and 0.47 µF for the capacitor. Figure 1 and Figures 3 through 6 are waveforms obtained from that motor.
The lower trace of Figure 3 (Figure 3b) shows the 330 mA current sawtooth in the inductor. while the upper trace (Figure 3a) .shows an 8 mA p-p current ripple in the motor winding. While this may seem to indicate only a 12 dB reduction in EM I over Figure 1, comparing the sinusoidal waveform of Figure 3a to the "noisy" sawtooth waveform of Figure 1 will quickly point out sources of
9-59
APPLICATION NOTE
U-99
UC3717 and L-C Filter
EMI. In Figure 1, the oscillations immediately following each switch of the driver are due to the motor's distributed capacitance resonating with its inductance and are a possible source of EM I. In addition, sharp current spikes are allowed to pass along the motor leads and through the motor's distributed capacitance unhindered, thus creating high frequency EM I. EM I spikes were virtually eliminated from Figure 3a by using a low ESR capacitor and connecting the motor leads close to the body of the capacitor.
Figure 4 shows motor current superimposed over the inductor current. Just to the left of the center graticle line a ringing occurs in the inductor current that also appears in the motor current, although attenuated. This ringing occurs at a frequency of:
the step motor are operated in quadrature and thus will generate 4 distinct states in the 2 phases which correspond to 4 mechanical steps for each electrical cycle.
FSPS = 4 x frequency (for a 2 or" 4" phase step motor) (12)
It is important to note at this time that 10.4 kHz is the highest frequency that can be passed to this motor without attenuation using the selected components, but that this corresponds to a step rate of 41,600 FSPS! The test motor was able to run at 17,000 full steps per second with the L-C filter in place, which is high enough for most situations.
Figures 5 and 6 are current waveforms for the motor running at 1600 FSPS and 16,000 FSPS respectively. The motor was operated with the L-C filter on only the lower trace winding so that the waveforms could be compared easily. Looking at Figure 5, one can see that the leading edges of both waveforms have the same
a) VERT = 2 mA/ DIV A-C component of Motor Current with L-C filter.
b) VERT ~ 100 mAI DIV A-C component of inductor current with L·C filter
HORIZ = 5 µS f DIV
VERT = 500mA I DIV Motor current without L:-C filter.
= VERT 500mA I
DIV Motor current with L-Cfilter.
HORIZ = 500µS I DIV
Figure 3. Motor and inductor current waveforms.
Figure 5. Motor currents at 1600 FSPS..
f,8, = 1 I 2 11 VLXC = 1 I 6.28 x V 500x1o-6 x 0.47x1o-6
= 10.4 kHz
(11)
which is the resonant frequency of the L-C filter. This frequency can be lowered by increasing the value of either Lor C, although at a cost of reducing the high speed performance of the motor.
The high frequency sawtooth waveforms at the upper, flat portion of the motor current waveform are the 29.1 kHz chopping currents in the inductor. They cause a small corresponding ripple in the motor current but, because the chopping frequency is more than twice the break frequency of the 2-pole L-C filter, we would expect, and can see, an attenuation greater than 12 dB.
In a 2 phase step motor (sometimes referred to as a 4 phase step motor because of the 4 windings used in the unipolar version) the STEP RATE, in full steps per second (FSPS), is 4 times the primary frequency of the motor current waveform. The two phases of
risetimes, although the filtered one has more suscepibility toward ringing. From Figure 6, one can see that torque is down only 3 dB at 16,000 FSPS and that there are "glitches" in the unfiltered waveform that do not appear in the filtered waveforms.
VERT = SOOmA I DIV Motor current without L-C 'filter. VERT ::::. 500 mA I DIV Motor current with L·C filter.
HOAIZ = 100mS/ DIV
Figur<;! 6. Motor currents at 16,000 FSPS.
VERT = 500 mA I DIV HORIZ = 200mS I DIV
Figure 4. Filter current waveform superimposed over motor current waveform.
Conclusions
The use of a low-pass filter can be an effective heat and EMI reduction mechanism when used with a step motor chopper driver such as the UC3717. The price one pays for a "clean" EMI environment is a small loss in very high speed performance. The technique may be applied equally well to non-IC chopper drivers but the peak currents must be accounted for and the minimum value of L adjusted accordingly. 500 µH is the smallest practical L that should be used with the UC3717 since we do not want the
9-60
APPLICATION NOTE
U-99
UC3717 and L-C Filter
peak of the ripple to exceed 1.0 amps. This limits the usefulness of the technique to motors with inductances of 2 mH or more. At average currents less than 300 mA, the value of L may have to be
larger in order to maintain continuous current in the inductor, but the physical size may be decreased. If an average current in excess of 850 mA is required, then a power amplifier may be added as shown in Figure 7. This will extend the peak current capabilities of the chopper drive to higher current and will also allow the value of L to be decreased.
'1
fl -'--
......
.
·SY II
Yo
!
1 ..
9 lo
·SY
·
Yoe
·40Y J, 14 .. I
UC3717
E 16
..... 15
12.13
r----
I '
I
I I 1 I
PIC900
16
I
14
10
12 I
Figure 7. UC3717 chopper drive with PIC900B Power Amplifier on one phase of step motor.
8
n
I
o
I
I
Unitrode Integrated Circuits Corporation 7 Continental Boulevard.· P.O. Box 399 ·Merrimack, New Hampshire· 03054-0399 Telephone 603-424-2410 · FAX 603-424-3460
9-61
n nINTEGRATED
eJ CIRCUITS
-UNITRODE
APPLICATION NOTE
U-100A
UC3842/3/4/5 PROVIDES LOW-COST CURRENT-MODE CONTROL
INTRODUCTION
The fundamental challenge of power supply design is to simultaneously realize two conflicting objectives: good electrical performance and low cost. The UC3842/3/4/5 is an integrated pulse width modulator (PWM) designed with both these objectives in mind. This IC provides designers an inexpensive controller with which they can obtain all the performance advantages of current mode operation. In addition, the UC3842 series is optimized for efficient power sequencing of off-line converters, DC to DC regulators and for driving power MOSFETs or transistors.
This application note provides a functional description of the UC3842 family and highlights the features of each individual member, the UC3842, UC3843, UC3844 and UC3845. Throughout the text, the UC3842 part number will be referenced, however the generalized circuits and performance characteristics apply to each member of the UC3842 series unless otherwise noted. A review of current mode control and its benefits is included and methods of avoiding common pitfalls are mentioned. The final section presents designs of power supplies utilizing UC3842 control.
CURRENT-MODE CONTROL
Figure 1 shows the two-loop current-mode control system in a typical buck regulator application. A clock signal initiates power pulses at a fixed frequency. The termination of each pulse occurs when an analog of the inductor current reaches a threshold established by the error signal. In this way the error signal actually controls peak inductor current. This contrasts with conventional schemes in which the error signal directly controls pulse width without regard to inductor current.
Several performance advantages result from the use of current-mode control. First, an input voltage feed-forward characteristic is achieved; i.e., the control circuit instantaneously corrects for input voltage variations without using up any of the error amplifier's dynamic range. Therefore, line regulation is excellent and the error amplifier can be dedicated to correcting for load variations exclusively.
For converters in which inductor current is continuous, controlling peak current is nearly equivalent to controlling average current. Therefore, when such converters employ current-mode control, the inductor can be treated as an
CLOCK
VERROR
I I I
VseNse
LATCH OUTPUT
Figure 1. Two-Loop Current-Mode Control System 9-62
0019-1
APPLICATION NOTE
U-100A
error-voltage-controlled-current-source for the purposes of small-signal analysis. This is illustrated by Figure 2. The two-pole control-to-output frequency response of these converters is reduced to a single-pole (filter capacitor in parallel with load) response. One result is that the error amplifier compensation can be designed to yield a stable closed-loop converter response with greater gainbandwidth than would be possible with pulse-width control, giving the supply improved small-signal dynamic response to changing loads. A second result is that the error amplifier compensation circuit becomes simpler, as illustated in Figure 3. Capacitor Ci and resistor Riz in Figure 3a add a low frequency zero which cancels one of the two control-tooutput poles of non-current-mode converters. For largesignal load changes, in which converter response is limited by inductor slew rate, the error amplifier will saturate while the inductor is catching up with the load. During this time, C; will charge to an abnormal level. When the inductor current reaches its required level, the voltage on C;
causes a corresponding error in supply output voltage. The recovery time is RizC;, which may be quite long. However, the compensation network of Figure 3b can be used where current-mode control has eliminated the inductor pole. Large-signal dynamic response is then greatly improved due to the absence of C;.
Current limiting is greatly simplified with current-mode control. Pulse-by-pulse limiting is, of course, inherent in the control scheme. Furthermore, an upper limit on the peak current can be established by simply clamping the error voltage. Accurate current limiting allows optimization of magnetic and power semiconductor elements while ensuring reliable supply operation.
Finally, current-mode controlled power stages can be operated in parallel with equal current sharing. This opens the possibility of a modular approach to power supply design.
YREF
VOLTAGE CONTROLLED CURRRENT SOURCE
I
Figure 2. Inductor Looks Like a Current Source to Small Signals
0019-2
Rt
0019-3
A) Direct Duty Cycle Control
B) Current Mode Control
Figure 3. Required Error Amplifier Compensation for Continuous Inductor Current Designs
0019-4
9-63
APPLICATION NOTE
U·100A
THE UC3842/3/4/5 SERIES OF CURRENT·MODE PWM IC'S
DESCRIPTION
The UC1842/3/4/5 family of control ICs provides the necessary features to implement off-line or DC to DC fixed frequency current mode control schemes with a minimal external parts count. Internally implemented circuits include under-voltage lockout featuring start up current less than 1 mA, a precision reference trimmed for accuracy at ·the error amp input, logic to insure latched operation, a PWM comparator which also provides current limit control, and a totem pole output stage designed to source or sink high peak current. The output stage, suitable for driving either N Channel MOSFETs or bipolar transistor switches, is low in the off state.
Differences between members of this family are the under-voltage lockout thresholds and maximum duty cycle ranges. The UC1842 and UC1844 have UVLO thresholds of 16V (on) and 10V (off), ideally suited to off-line applications. The corresponding thresholds for the UC1843 and UC1845 are 8.5V and 7.9V. The UC1842 and UC1843 can operate to duty cycles approaching 100%. A range of zero to <50% is obtained by the UC1844 and UC1845 by the addition of an internal toggle flip flip which blanks the output off every other clock cycle.
FEATURES
· Optimized for Off-Line and DC to DC Converters · Low Start Up Current ( < 1 mA) · Automatic Feed Forward Compensation · Pulse-By-Pulse Current Limiting ·Enhanced Load Response Characteristics ·Under-Voltage Lockout with Hysteresis · Double Pulse Suppression ·High Current Totem Pole Output · Internally Trimmed Bandgap Reference · 500 kHz Operation · Low Ro Error Amp
IC SELECTION GUIDE
RECOMMENDED USAGE
UVLO START
8.5V 16V
MAXIMUM DUTY CYCLE
<50%
<100%
UC3845
UC3843
UC3844
UC3842
APPLICATION (CIRCUIT)
FLYBACK FORWARD BUCK/BOOST
POWER SUPPLY INPUT (V)
HIGH (OFFLINE)
LOW(DC/DC)
UC3844
UC3845
UC3844/2
UC3845/3
UC3842/4
UC3843/5
COMP CURRENT SENSE
Note: l. !W] A= DIL-8 Pin Number. B = S0-16 Pin Number.
2. Toggle flip flop used only in 1844A and 1845A.
Figure 4
9-64
POWER GROUND
APPLICATION NOTE
U·100A
UNDER-VOLTAGE LOCKOUT
The UVLO circuit insures that Vee is adequate to make the UC3842/3/4/5 fully operational before enabling the output stage. Figure 5 shows that the UVLO tum-on and tum-off thresholds are fixed internally at 16V and 1OV respectively. The 6V hysteresis prevents Vee oscillations during power sequencing. Figure 6 shows supply current requirements. Start-up current is less than 1 mA for efficient bootstrapping from the rectified input of an off-line converter, as illustrated by Figure 6. During normal circuit operation, Vee is developed from auxiliary winding WAux with D1 and C1N· At start-up, however, C1N must be charged to 16V through R1N· With a start-up current of 1 mA, R1N can be as large as 100 kO and still charge C1N when VAc = 90V RMS (low line). Power dissipation in R1N would then be less than 350 mW even under high line (VAC = 130V RMS) conditions.
During UVLO; the output driver is in a low state. While it doesn't exhibit the same saturation characteristics as normal operation, it can easily sink 1 milliamp, enough to insure the MOSFET is held off.
Yee
ON/OFF COMMAND TO REST OF IC
UC1842 UC1843 UC1844 UC1845
16V
8.4V
10V
7.6V
..
0019-6
Figure 5
Ice
<17mA
<1 mA
~-----+--+----Vee
0019-7
Figure 6. During Under-Voltage Lockout, the output driver Is biased to sink minor amounts of current.
OSCILLATOR
The UC3842 oscillator is programmed as shown in Figure 8. Timing capacitor CT is charged from VREF (5V) through the timing resistor RT, and discharged by an internal current source.
The first step in selecting the oscillator components is to determine the required circuit deadtime. Once obtained, Figure 9 is used to pinpoint the nearest standard value of CT for a given deadtime. Next, the appropriate RT value is interpolated using the parameters for CT and oscillator frequency. Figure 1O illustrates the RT/CT combinations versus oscillator frequency. The timing resistor can be calculated from the following formula.
Fosc (kHz) = 1.72 I (RT (k) x CT (µ.f))
The UC3844 and UC3845 have an internal divide-by-two flip-flop driven by the oscillator for a 50% maximum duty cycle. Therefore, their oscillators must be set to run at twice the desired power supply switching frequency. The UC3842 and UC3843 oscillator runs AT the switching frequency. Each oscillator of the UC3842/3/4/5 family can be used to a maximum of 500 kHz.
START·UP CURRENT
BOOTSTRAPPED SUPPLY CURRENT
[
Vee
UC 3842/3/4/5
OUT
J
GND
Figure 7. Providing Power to the UC3842/3/4/5 9-65
0019-8
APPLICATION NOTE
U-100A
MAXIMUM DUTY CYCLE
The UC3842 and UC3843 have a maximum duty cycle of approximately 100%, whereas the UC3844 and UC3845 are clamped to 50% maximum by an internal toggle flip flop. This duty cycle clamp is advantageous in most flyback and forward converters. For optimum IC performance the deadtime should not exceed 15% of the oscillator clock period.
During the discharge, or "dead" time, the internal clock signal blanks the output to the low state. This limits the maximum duty cycle DMAX to:
DMAX = 1 - (toEAD I tpERIOD)
UC3842/3
DMAX = 1 - (toEAD I 2 X IPERIOD) UC3844/5
where TPERIOD = 1 I F oscillator
VRErQI
I
Rr
I
Rr/Cr 4
I
~ TCT
____G_R_O.UN -Dn
Figure 8
0019-9
Deadtime VS CT (RT > Sk)
vr
0.3~~~-~~~~
1 2.2 4.7 10 22 47 100
Cr-(nr)
Figure 9
0019-10
Timing Resistance vs Frequency
CURRENT SENSING AND LIMITING
The UC3842 current sense input is configured as shown in Figure 12. Current-to-voltage conversion is done externally with ground-referenced resistor Rs. Under normal operation the peak voltage across Rs is controlled by the ElA according to the following relation:
I _Ve - 1.4V P - 3Rs
where Ve = control voltage = E/A output voltage.
Rs can be connected to the power circuit directly or through a current transformer, as Figure 11 illustrates. While a direct connection is simpler, a transformer can reduce power dissipation in Rs, reduce errors caused by the base current, and provide level shifting to eliminate the restraint of ground-referenced sensing. The relation between Ve and peak current in the power stage is given by:
.
l(pk)
=
N (V~ R5(pk))
=
3 RN s
( Ve-1.4V)
where: N = current sense transformer turns ratio = 1 when transformer not used.
For purposes of small-signal analysis, the control-tosensed-current gain is:
~=~
Ve 3Rs
When sensing current in series with the power transistor, as shown in Figure 11, the current waveform will often have a large spike at its leading edge. This is due to rectifier recovery and/or inter-winding capacitance in the power transformer. If unattenuated, this transient can prematurely terminate the output pulse. As shown, a simple RC filter is usually adequate to suppress this spike. The RC time constant should be approximately equal to the current spike duration (usually a few hundred nanoseconds).
The inverting input to the UC3842 current-sense comparator is internally clamped to 1V (Figure 12). Current limiting occurs if the voltage at pin 3 reaches this threshold value, i.e., the current limit is defined by:
.
N x 1V
'max=~
h
UC 3842/3/4/5
3~~~~~~~~
100 1K
10K 100K 1M
FREQUENCY- (Hz)
Figure 10
0019-11
0019-13
Figure 11. Transformer-Coupled Current Sensing
9-66
APPLICATION NOTE
U-100A
R
c
Rs
R
IV
CURRENT SENSE
COMPARATOR
Figure 12. Current Sensing
0019-12
ERROR AMPLIFIER
The error amplifier (E/A) configuration is shown in Figure
R1
13. The non-inverting input is not brought out to a pin, but
is internally biased to 2.5V ± 2%. The E/A output is
c,
available at pin 1 for external compensation, allowing the
user to control the converter's closed-loop frequency re-
sponse.
Figure 14 shows an E/A compensation circuit suitabl& for stabilizing any current-mode controlled topology except for flyback and boost converters operating with inductor current. The feedback components add a pole to the loop
transfer function at fp = %11" RF.CF. RF and CF are cho-
sen so that this pole cancels the zero of the output filter capacitor ESR in the power circuit. R1 and RF fix the lowfrequency gain. They are chosen to provide as much gain as possible while still allowing the pole formed by the output filter capacitor and load to roll off the loop gain to unity (0 dB) at f z fswlTCHING/4. This technique insures converter stability while providing good dynamic response.
Figure 14. Compensation
0019-15
The E/A output will source 0.5 mA amd sink 2 mA. A lower limit for RF is given by:
R
_ VEA OUT (MAX) - 2.5V
F(MIN) -
0.5 mA
6V - 2.5V ----=7kfi.
0.5mA
2.50V
z,
Figure 13. E/A Configuration 9-67
0019-14
APPLICATION NOTE
U-100A
E/A input bias curret (2 µ.A max) flows through Ri. resulting in a DC error in output voltage <Vol given by:
liVo(MAX) = (2 µ.A) R1,
It is therefore desirable to keep the value of R1. as low as possible.
Figure 15 shows the open-loop frequency response of the UC3842 E/A. The gain represents an upper limit on the gain of the compensated E/A. Phase lag increases rapidly as frequency exceeds 1 MHz due to second-order poles at -10 MHz and above.
Continuous-inductor-current boost and flyback converters each have a right-half-plane zero in their transfer function. An additional compensation pole is needed to roll off loop gain at a frequency less than that of the RHP zero. Rp and Cp in the circuit of Figure 16 provide this pole.
TOTEM-POLE OUTPUT
The UC3842 PWM has a single totem-pole output which can be operated to ± 1 amp peak for driving MOSFET
gates, and a ± 200 mA average current for bipolar power
transistors. Cross conduction between the output transistors is minimal, the average added power with V1N = 30V is only 80 mW at 200 kHz.
Limiting the peak current through the IC is accomplished by placing a resistor between the totem-pole output and the gate of the MOSFET. The value is determined by dividing the totem-pole collector voltage Ve by the peak current rating of the IC's totem-pole. Without this resistor, the peak current is limited only by the dVI dT rate of the totem-pole switching and the FET gate capacitance.
The use of a Schottky diode from the PWM output to ground will prevent the output voltage from going excessively below ground, causing instabilities within the IC. To be effective, the diode selected should have a forward drop of less than 0.3V at 200 mA. Most 1- to 3-amp Schottky diodes exhibit these traits above room temperature. Placing the diode as physically close to the PWM as possible will enhance circuit performance. Implementation of the complete drive scheme is shown in the following diagrams. Transformer driven circuits also require the use of the Schottky diodes to prevent a similar set of circum-
80
iD
~ 60
;z;:
<!) 40 w
<!)
.<.. 20
..J
0 >
0
0
-45
"O
-90
I
)>
(/)
m
-135 ~
-180
10
100
1K
10K
100K
FREQUENCY - (Hz)
1M
10M
Figure 15. Error Amplifier Open-Loop Frequency Response
Vo
0019-16
c.
I
0019-17
Figure 16. E/A Compensation Circuit for Continuous Boost and Flyback Topologies
9-68
APPLICATION NOTE
U-100A
stances from occurring on the PWM output. The ringing below ground is greatly enhanced by the transformer leakage inductance and parasitic capacitance, in addition to the magnetizing inductance and FET gate capacitance. Circuit implementation is similar to the previous example.
Figures 18, 19 and 20 show suggested circuits for driving MOSFETs and bipolar transistors with the UC3842 output. The simple circuit of Figure 18 can be used when the control IC is not electrically isolated from the MOSFET
turn-on and turn-off to ± 1 amp. It also provides damping
for a parasitic tank circuit formed by the FET input capacitance and series wiring inductance. Schottky diode 01 prevents the output of the IC from going far below ground during turn-off.
4
Vee= 1svllJI[
~
TA=+25oC-
I
"C"l
TA =-55oC ---3
~
I
l.T
,
-- >0
2
z
;.0:.:.
·+-1
0::
..::..:.>..
Vl
0 --H-1
--.:1'4l.1.i '
'oo"''~J {Vee-VoH) I I 1111
SINK SAT (VOL
0.01 0.04 0.1 0.2 0.4 0.6 1.0
OUTPUT CURRENT SOURCE OR SINK - (A) 0019-18
Figure 17. Output Saturation Characteristics
20 TO 30V 7
UC 3842
GND 5
0019-20
Figure 19. lsloated MOSFET Drive
Figure 19 shows an isolated MOSFET drive circuit which is appropriate when the drive signal must be level shifted or transmitted across an isolation boundary. Bipolar transistors can be driven efficiently with the circuit of Figure 20. Resistors R1 and R2 fix the on-state base current while capacitor C1 provides a negative base current pulse to remove stored charge at turn-off.
Since the UC3842 series has only a single output, an interface circuit is needed to control push-pull half or full bridge topologies. The UC3706 dual output driver with internal toggle flip-flop performs this function. A circuit example at the end of this paper illustrates a typical application for these two ICs. Increased drive capability for driving numerous FETs in parallel, or other loads can be accomplished using one of the UC3705/6/7 driver ICs.
10 TO 20V 7
Vee
UC 3842
1--
GND 5
Figure 18. Direct MOSFET Drive
0019-19
12 TO 20V 7
Vee
UC 3842
GND 5
0019-21
Figure 20. Bipolar Drive with Negative Turn-Off Bias
9-69
APPLICATION NOTE
U·100A
NOISE
As mentioned· earlier, noise on the current sense or control signals can cause significant pulse-width jitter, particularly with continuous-inductor-current designs. While slope compensation helps alleviate this problem, a better solution is to minimize the amount of noise. In general, noise immunity improves as impedances decrease at critical points in a circuit.
One such point for a switching supply is the ground line. Small wiring inductances between various ground points on a PC board can support common-mode noise with sufficient amplitude to interfere with correct operation of the modulating IC. A copper ground plane and separate return lines for high-current paths greatly reduce common-mode noise. Note that the UC3842 has a single ground pin. High sink currents in the output therefore cannot be returned separately.
Ceramic monolythic bypass capacitors (o: 1 µ.F) from Vee
and VREF to. ground will provide low-impedance paths for high frequency transients at those points. The input to the error amplifier, however, is a high-impedance point which cannot be bypassed without affecting the dynamic response of the power supply. Therefore, care should be taken to lay out the board in such a way that the feedback path is far removed from noise generating components such as the power transistor(s).
Figure 21 illustrates another common noise-induced problem. When the power transistor turns off, a noise spike is coupled to the oscillator Ar/Or terminal. At high duty cycles the voltage at Rr/Cr is approaching its threshold level ( - 2.7V, established by the internal oscillator circuit) when this spike occurs. A spike of sufficient amplitude will prematurely trip the oscillator as shown by the dashed lines. In order to minimize the noise spike, choose Or as large as possible, remembering that deadtime increases with Or. It is recommended that Or never be less than -1000 pF. Often the noise which causes this problem is caused by the output (pin 6) being pulled below ground at turn-off by external parasitics. This is particularly true
when driving MOSFETs. A Schottky diode clamp from ground to pin 6 will prevent such output noise from feeding to the oscillator. If these measures fail. to correct the probelm, the oscillator frequency can always be stabilized with an external clock. Using the circuit of Figure 31 results in an Rr/Or waveform like that of Figure 21 B. Here the oscillator is much more immune to noise because the ramp voltage never closely approaches the internal threshold.
SYNCHRONIZATION
The simplest method to force synchronization utilizes the timing capacitor (Cr) in near standard configuration. Rather than bring Or to ground directly, a small resistor is placed in series with Or to ground. This resistor serves as the input for the sync pulse which raises the Cr voltage above the oscillator's internal upper threshold. The PWM is allowed to run at the frequency set by Rr and Cr until the sync pulse appears. This scheme offers several advantages including having the local ramp available for slope compensation. The UC3842/3/4/5 oscillator
SYNC CIRCUIT INPUT
j\_i~
24.ll.
UC
3842/3/4/5
PWM
0019-32
Figure 22. Sync Circuit Implementation
~'l~ -~,-
\
~V~N4_____.
\,,,,,
v.
'-._ NOISE INDUCED OSCILLATOR PRE-FIRING
J
I r
a.
b.
Figure 21. (L) Noise on Pin 4 can cause oscillator to pre-trigger. (b.) With external sync., noise does not approach threshold level.
0019-31
9-70
APPLICATION NOTE
U·100A
must be set to a lower frequency than the sync pulse stream, typically 20 percent with a 0.5V pulse applied across the resistor. Further information on synchronization can be found in "Practical Considerations in Current Mode Power Supplies" listed in.the reference appendix.
The UC3842 can also be synchronized to an external clock source through the RT/CT terminal (Pin 4) as shown in Figure 23.
In normal operation, the timing capacitor CT is charged between two thresholds, the upper and lower comparator limits. As CT begins its charge cycle, the output of the PWM is initiated and turns on. The timing capacitor continues to charge until it reaches the upper threshold of the internal comparator. Once intersected, the discharge circuitry activates and discharges CT until the lower threshold is reached. During this discharge time the PWM output is disabled, thus insuring a "dead" or off time for the output.
A digital representation of the oscillator charge/discharge status can be utilized as an input to the RT/~ terminal. In instances like this, where no synchronization port is easily available, the timing circuitry can be driven from a
digital logic input rather than the conventional analog mode. The primary considerations of on-time, dead-time, duty cycle and frequency can be encompassed in the digital pulse train input.
A LOW logic level input determines the PWM maximum ON time. Conversely, a HIGH input governs the OFF, or dead time. Critical constraints of frequency, duty cycle or dead time can be acurately controlled by anything from a 555 timer to an elaborate microprocessor controlled software routine.
EXTERNAL CLOCK
UC 3842 GNO
0019-34
DMax = tL (ft.I + Ii.} ft.I = 0.693 (RA + Re) C
IL = 0.693 ReC
Vee
7 _ _ _ _ _ _ _ _ _ _ _s""VREF Vee
4 RESET
CMOS 7555
8
4.7k
UC
Vee
3842
..-.-----4-tRT/Cr
GND 5
0.1
GND
c
CLOCK INPUT
J POWMUT'
Figure 23 Synchronization to an External Clock
0019-33
LOW
~
LOW
UPPER THRESHOLD LOWER
THRESHOLD
·Ld· ON
ON
OUTPUT A
0019-35
Ver (ANALOG)
::> VsYNC
(DIGITAL)
A
COMBINED
UPPER -THRESHOLD
Ver LOWER THRESHOLD
Figure 24
0019-36
9-71
APPLICATION NOTE
U-100A
SYNC PULSE GENERATOR
The UC3842/3/4/5 oscillator can be used to generate sync pulses with a minimum of external components. This simple circuit shown in Figure 25 triggers on the falling
edge of the Or waveform, and generates the sync pulse
required for the previously mentioned synchronization
scheme. Triggered by the master's deadtime, this circuit is useable to several hundred kilohertz with a minimum of delays between the master and slave(s). The photos shown in Figures 26 ·and 27' depict the circuit waveforms of interest.
+5
MAsn:R
10k
1k
y
1000pF·
SLAVE
INPUT 10k
GND Figure 25.iSync Pulse Generator Circuit
0019-37
Top Trace: Circuit Input
Bottom Trace: Circuit Output Across 24 Ohms
Vertical: 0.5V/CM Both Horizontal: 0.5,.SJCM
Figure 26. Operating Waveforms at 500 kHz
Top Trace: Slave Cr
Bottom Trace: Master Cr
Vertical: 0.5V/CM Both Horizontal: 0.5,,s/CM
Figure 27. Master/Slave Sync Waveforms at Or
9-72
APPLICATION NOTE
CHARGE PUMP CIRCUITS LOW POWER DC/DC CONVERSION
Step Up Vo::::: 2 X V1N
Inverting
Vo"" -v,N
U-100A
Four""' tOOKHz
= DUTY CM 50%
Four ... 100KHz DUTY%= 50
10k
1 nF
1 nF
Figure 28
0019-44
Figure 29
0019-45
Low Power Buck Regulator-Voltage Mode
+VIN~----------.....,
The basic buck regulator is described in the UNITRODE Applications Handbook.
·consult UNITRODE Power Supply Design Seminar Book for compensation details; see "Closing The Feedback Loop", Buck Topology.
L
0.1 nF
Cr 2.2nF
-VIN-------------------------__, 0019-47 Figure 30
9-73
APPLICATION NOTE
U·100A
CIRCUIT EXAMPLES
1. Off-Line Flyback
Figure 31 shows a 25W multiple-output off-line flyback regulator controlled with the UC3844. This regulator is low in cost because it uses only two magnetic elements, a primary-side voltage sensing technique, and an inexpensive control circuit. Specifications are listed below.
Also consult UNITRODE application note U-96 in the applications handbook.
R1
5.0.
01
1W
117VAC
C1 250µ.F 250V
R2 56k 2W
R4
R3
4.7k
20k
R12 4.7k
2W
C9 3300pF
600V
04 1N3613
02 1N3612
03 1N3612
- 06
USD945
L1 (NOTE 2)
+5V
C11 4700µ.F 10V
07 UFS1002
C12 2200µ.F 16V
C13 2200µ.F 16V
COM +12V ±12V COM -12V
CB 680pF 600V
R11 2.7k
2W
Figure 31
Power Supply Specifications
1. Input Voltage:
95 VAC to 130 VAC (50 Hz/60 Hz)
2. Line Isolation:
3750V
3. Switching Frequency:
40 kHz
4. Efficiency @ Full Load:
70%
5. Output Voltage:
A. +5V, ±5%: 1A to 4A load
Ripple voltage: 50 mV P-P Max.
B. +12V, ±3% 0.1A to 0.3A load
Ripple voltage: 100 mV P-P Max.
C. -12V ±3%, 0.1A to 0.3A load
Ripple voltage: 100 mV P-P Max.
0019-46
9-74
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4700
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63vp:63°1
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5000 4W
2k
4.30
viN
ViN
: .04,.
1.-1~
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6 z
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5V 25-IOOA
0
-rnI
3Qk 1- ·1
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(-40 -56V)
150 I 4W I
I
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(ISOLATION BOUNDARY)
I
1- -------------- ---- ---- -- --- -
I I
2. DC·to-DC Push·Pull Converter
22k
4·7k 1N914
I I I
I
8~~ CLOCK
UC290l
l.5k
4.7k 196
Figure 45 is a 500W push-pull DC-to-DC converter utilizing the UC3842, UC3706, and UC3901 \Cs. It operates from a standard telecommunications bus to produca 5V at up to 100A. Operation of this circuit is detailed in Reference 8.
IOOk 2J ±.1µ
)lit
1:1 I
I
I
A
12
SPECIFICATIONS:
. II
.133,. 12k
418 G~--
2.0k
lnpµt Voltage: Plitput Voltage: Output Current: Oscillator Frequency:
196
Line Regulation:
.____ _ _ _ _ _ __.,___.. Load Regulation:
.,,. Efficiency ® V1N = 48V lo= 25A: lo= 50A:
Output Ripple Voltage:
-48V ±8V +5V
25A to 100A 200 kHz 0.1% 1%
75% 80% 200 mV P-P
Also consult application note U-101 in the Unltrode Applications Handbook.
Figure 32. 500W Push·Pull DC-to-DC Converter
001 s-48
c
..I ..
~
A
n n INTEGRATED
~CIRCUITS
-UNITRDDE
APPLICATION NOTE
UC1637/2637/3637
SWITCHED MODE CONTROLLER FOR DC MOTOR DRIVE
U-102
INTRODUCTION
There is an increasing demand today for motor control circuits, as a result of the incredible proliferation of automated position control equipment, which is itself made possible by recent developments in the field of digital computation.
The UC1637 Switched Mode Controller for DC motors is one of several integrated circuits offered by Unitrode for motor controls. This Application Note presents the general principles of its operation and the circuit details that optimize its use. As an illustration we will carry out an actual design, which will involve not only the UC1637, but also a
power H-bridge using MOSFET transistors, and a modern DC motor tachometer. Using the tach output and UC1637's error amplifier, we will close the velocity control ioop after a brief analysis of the factors that affect the feedback loop stability.
To achieve high efficiency power amplification, the UC1637 uses pulse width modulation, or PWM. This technique is employed today in many different circuits where power losses must be minimized, and is most suitable in applications involving inductive loads such as motors, voice coils, etc.
+A1N -A1N
Q 1----1---~ SRB
E/Aour 17 1-------~ 21s
-B1N +81N
FIGURE 1. BLOCK DIAGRAM OF UC1637.
9-76
200mV
APPLICATION NOTE
U-102
PULSE WIDTH MODULATION (PWM)
The function of a power amplifier is to regulate the flow of energy from a power supply to a load, under the control of an input signal. A linear amplifier does this by interposing a controlled voltage drop in series with the load, while carrying the full load current. The product of this voltage and current represents the amount of power that must be dissipated by the amplifier itself, and it is easy to see that the method is not very efficient In fact. its usefulness diminishes rapidly as the amount of power to be controlled increases and, at some point, a more efficient method becomes imperative.
PWM is a switching technique in which the supply voltage is fully applied (switched) to the load and then removed, the "on" and "off" times being precisely controlled. The effect on the load is the same as if some lower voltage were continuously applied whose value depended on the duty-cycle, that is, the ratio of "on" time to the full switching period. Since supply current only flows during the "on" times, It is apparent that the efficiency should be much higher than in the linear amplifier, as in fact it is. Still, switching transistors have small but finite "on" voltages and transition times, all of which introduce losses, which limit practical PWM efficiencies to something between 75% and 90%.
THE UC1637
The diagram of Figure 1 shows in block form the internal organization of the device. The main functions are:
A) Triangular wave generator; GP, CN, S1, SR1 B) PWM comparators; CA, CB C) Output control gates; NA, NB D) Current limit; CL, SRA, SRB E) Error amplifier; EA F) Shutdown comparator; CS G) Undervoltage lockout; UVL
The two output Jines, Aour and Bour. are meant to drive the two legs of an H-bridge power amplifier, with the load driven in bipolar fashion. The Aour and Bour outputs themselves are rated at 500mA peak and 1OOmA continuous, which makes it easy to interface the device with most amplifiers.
In order to generate two PWM output signals, we first produce a triangular waveform, or linear ramp. This is done by charging a capacitor Cr (pin 2) with constant current Is until the comparator GP, with a fixed threshold voltage of +VTH, delivers a pulse to "set" the SR1 latch circuit. This forces Q high, which closes the switch S1 and adds a negative current, 2xls, to the node of pin 2. As a result, a net current equal to Is now flows out of Cr, discharging it linearly until the comparator CN resets SR1, and the cycle restarts. Thus, the voltage at pin 2 ramps continuously between -VrH and +VrH at a frequency that depends on these two threshold voltages, on Cr, and on Is.
The current Is is programmed by means of a resistor connected to pin 18. The voltage at this pin is equal to +VrH and an internal current mirror forces the charging current Is to be equal to the current flowing out of pin 18. If a resistor Rs is connected from pin 18 to -Vs (pin 5) instead of to ground, the ramp frequency becomes independent of power supply voltage variations, since Is will then change together with Vrn.
As Figure 2 shows, a triangular waveform can be compared with a reference voltage to generate a PWM signal. The UC1 637 uses two separate comparators to generate the two output signals Aour and Bour. The way the signals are handled, and the results, are shown in Figure 3 where it can be seen that !he difference between VA and Ve is the cause of the time intervals during which both outputs are low.
COMPARATOR
/
HI---
+VTH - - - - - - - -
LO FIGURE 2. HOW A PWM SIGNAL IS GENERATED.
PWM SIGNAL
LO
FIGURE 3. TWO PWM SIGNALS ARE GENERATED IN THE UC1637.
9-77
APPLICATION NOTE
U-102
The two nand gates, NA and NB, will be enabled if the following two conditions are met:
A) supply voltage +Vs is greater than +4.15 volts (typ) B) the shut-down input line (pin 14) is at least 2.5
volts (typ) negative with respect to +Vs.
If these are satisfied, the AoUT output line will be high if the CA output and Q of SRA are both high. Since SRA is set at each positive peak of the oscillator ramp, the output Aour can be controlled by CA singly - as long as a current-limit pulse from CL does not occur. The operation of the NB gate is similar.
The timing diagrams of Fig. 4 show the sequence of events before and after a current limit pulse occurs. Before time t1 the PWM action is smoothly controlled by the ramp comparisons with VA and Ve. The pulse from CL at time t1 resets both SRA and SRB; the output lines are now disabled until SRA is set (at time t2) and SRB is set (at time ta).
The current limit comparator CL provides a means to protect both driver and motor from the consequences of very high currents. If the current delivered by the driver to the motor is made to flow through a low value resistor (for example, see Rs in Figure 7) the voltage drop across this resistor will be a measure of motor current. This voltage is applied between pins 12 and 13 of the UC1637, with pin 12 positive. A 200mV threshold is provided internally (see Figure 1) so that when the Rs voltage is equal to 200mV, the output of CA goes high, resetting both SRA and SRB and, consequently, terminating any active output pulse. This pulse-by-pulse method of current limiting is very fast and provides effective protection, not only for the driver components, but also for the motor, where the possibiltty of demagnetization due to excessive current is a matter of serious concern.
Finally, the UC1637 contains also an operational amplifier, EA, that can be used to provide gain and phase compensation, as will be seen later.
I
I
I
+VTH
Ve .IL"-
RAMP WAVEFORM
b;J
[Z L;: z ~
~
I I I I
I
~
VA
~
-VrH
I
~
I~ /
I I
I I
______ J H
Q OF SRA
-
-- --- - --1 -
-- -
I
--- - - - - --
I
I
H
Q OF SRB
________ l
t--
-- ---- ---- ---- -
I
CL OUTPUT
I I
- -- ---1 ----- - ---- - - -------- I
J I
l - - -- - - -- ---
I
I
AouT
I
I
t---1
I
r---i
I
I
BoUT
I
I
I I I
I
I
deadtime
deadtime
I
I
FIGURE 4. TIMING DIAGRAM SHOWING THE GENERATION OF PWM PULSES AT AouT AND BouT· BEFORE TIME 1,, THE Q OUTPUTS OF SRA AND SRB ARE BOTH HIGH AND THE OUTPUT PULSES ARE CONTROLLED BY THE RAMP INTERSECTIONS WITH V, AND Ve. AT TIME 1,, THE CURRENT LIMIT COMPARATOR HAS SENSED EXCESS CURRENT AND THE CL OUTPUT HAS GONE HIGH, RESETTING BOTH SRA AND SRB. THIS TERMINATES THE AoUT PULSE THAT WAS ACTIVE AT THE TIME. AouT CAN RESUME ONLY AFTER SRA IS SET AT 12; BOUT CAN RESUME ONLY AFTER SRB IS SET AT 13·
9-78
APPLICATION NOTE
Figure 5 shows the connections needed to get the ramp generator and the two comparators ready to go. There is no great difficulty in calculating values for the various resistors, which are no more than two simple voltage dividers. Still, certain things should be considered before proceeding. The input impedance R1N, seen by the control voltage Ve will be
(1)
U-102
Vo
and this value may be specified or determined in advance. Also, It would be economical to have a minimum number of different values of resistors. If we make
(2)
we will have four resistors of equal value in the final circuit. There is also the question of deciding on the separation VG between the reference voltages +VA and -VA. The voltage gain of the PWM amplifier will have one of the four characteristics depicted in Figure 6, depending on your choice of reference voltage separation. You can get a linear response by making VG = 0, as in Curve #1, or by making Ve - VA= 2VTH, as in Curve #3. In Curve #2, there is a change in slope due to the contribution, near zero, of both VA and Ve to the output changes, which in some systems may be undesirable, but which may be of interest due to the fact that it results in zero losses at null.
+Vs
NOTE: Max. Vo is less than Vs oue to device saturation voltages, VsAT·
----- ------- ---- -Vs
FIGURE 6. PWM VOLTAGE GAIN CHARACTERISTICS OBTAINABLE WITH VARIOUS VALUES OF REFERENCE VOLTAGE SEPARATION, OR GAP VOLTAGE 2 VR.
1. LINEAR GAIN WITH VR = 0 (a= 0). 2. NON-LINEAR GAIN WITH VR GREATER THAN ZERO BUT LESS
THAN VrH (0 <a< 1). 3. LINEAR GAIN WITH VR = VrH (a= 1). 4. NON-LINEAR GAIN WITH VR GREATER THAN VTH (a> 1).
NOTE: THE SLOPE OF LINE 1 IS TWICE THAT OF LINE 3.
At .this point, this choice of PWM gain characteristic amounts only to the choice of the ratio between VA and VTH:
(3~
The values of VTH and VA, as well as R3 and R4, depend on the following:
±Vs: power supply voltages R1N: desired control input resistance Vemax: peak value or input voltage Ve. This is the
input voltage at which the output reaches 100% duty cycle a: ratio of VA to VTH
These values being known, the designer can proceed to calculate the following circuit values:
(4)
-Vs
FIGURE 5. SETIING UP THE A AND B COMPARATOR INPUTS.
(5)
9-79
APPLICATION NOTE
(6) (7) (8)
and, from Eq. (2), R1 = R3.
Having chosen a frequency fr for the PWM timing circuit, you can now calculate CT and RT. A suitable starting value for the charging current Is is 0.5mA which gives
RT= Vs+ VTH
(9)
.0005
Cy-- .0005
(10)
4h VTH
You will probably need to make an adjustment here, so as to get a standard value for capacitor CT, and it is best to keep Is in the range from 0.3mA to 0.5mA when you do this.
It may be desirable, or even necessary in some conditions,
U-102
to bypass the +VTH and -VTH inputs to ground, and for this, ceramic capacitors of 0.1µf should be adequate. Remember also that terminal 14, the shut-down line, must be held "low" (at least 2.5V below the positive rail) in order to enable the drive. With an external switch to ground, or to -Vs, and a pull-up resistor to +Vs, this line can be used to enable (low), and disable (high), the output. Both Ao1JT and Bouy-will be low when the shut-down line is high.
The next step is to connect the UC1637to a suitable power amplifier, and the amplifier to the motor. The UC1637 has provisions for current limiting, as discussed earlier, and you must make arrangements to develop a voltage proportional to motor current at the driver side. This can be done by adding to an H-bridge a low value resistor in series with rail connections. The current limit comparator has a common mode range that reaches all the way down to the negative rail (on the positive side the limit is 3V below the positive rail). A resistor Rs is then added at the bottom of the bridge, and its value is selected so as to give a voltage drop to 200mV when the desired limit current flows.
Rs=~ (ohms)
(11)
IMAX
where IMAX is the maximum desired motor current in amperes. In a breadboard, a twisted pair of wires should be used to make the connection from this resistor to pins 12 and 13, and an RC filter should be added, as shown in Figure 7.
On a PC board, it is a good idea to keep Rs close to the UC1637 to minimize the length of the connecting traces. The RC filter should still be used.
15K
lOK
15K INPUT ± lOV, R1N = !OK
J_ --
+VTH
Vs
15K 5K
-VTH
-B1N
UC1637
-A1N
11 +A1N
18 RT
15K 39K
SD 14
Rs = 0.025 ohm, 3W
L__ ___.__ _.__ _ _ _...___._ _ _ _ _ _ _ _ _ _ _ _ _ _ -15V FIGURE 7. CIRCUIT DIAGRAM OF PWM VOLTAGE AMPLIFIER WITH GAIN OF 3.
9-80
APPLICATION NOTE
U-102
AN EXAMPLE
We are ready now to design a current limited, PWM voltage amplifier to drive a small DC servomotor. Here are the requirements:
Incidentally, the voltage gain of the amplifier can be determined from the fact that a 1OV change atthe input results in a 30V change at the output; therefore, the gain from input to motor terminals is 3. The above circuit is shown in Figure 7.
Supply voltages: ±15V Input: ±1 OV max.; 1OK input res. PWM frequency: 30KHz Motor current limited at BA Minimum power losses at idle
We have: Vs= 15V Vcmax = 10V R1N = 104 ohm h=3X1Q4 Hz and IMAX= BA
and also, from the last requirement, a = 1.
FROM EQUATIONS
(4) Ra= 2x1Q4 X15x2 = 15K 10+15X2
(5)
(6)
(7) VTM = 3.75V (B)
(9) R = 15 + 3.75 = 37 5K
T .QQQ5
.
and of course, R1 = R3 = 15K.
(10) CT=
.0005
1.11 x1Q-sfd
4x30x103x 3.75
If we settle for RT = 39K, Is becomes slightly less than 0.5mA and if we then pick CT = 1OOOpf, the nominal frequency becomes 32KHz.
To limit the motor current at BA, we need, from Eq. 11,
Rs = ~ = 0.025 ohm
The peak power in the resistor will be Ps = B2 x .025 = 1.6 watts.
THE POWER AMPLIFIER
Where space is tight and motor current is less than five amperes, the Unitrode PIC900 offers a perfect solution to your power bridge design. This device comes in a DIL-1B package, requires only 5mA of input drive current, and is rated at 5A absolute maximum output current. It contains all you need for the output H-bridge - including the circulating diodes - and with only a few added parts, you are ready to go. A circuit diagram showing a velocity feedback loop using one UC1637 and one PIC900 appears in the UC1637 data sheet.
For higher currents, you will have to design your own amplifier, and for the purposes of this application note, a sample design is shown in Figure 8. Referring to that circuit, note that with +Vs and -Vs applied, if the inputs are left open, the power MOSFETs are all "off". If Drive A, for example, is driven to within 3.6V of either power rail, then the corresponding output is switched to that rail. Note that since the PNP and NPN junction transistors are by nature faster 'switching "on" than "off", while the MOSFETs are much faster than the junction transistors driving them, this connection provides a simple guarantee against crossconduction. Also working toward this goal is the fact that the junction transistor can discharge the MOSFET's input capacitance faster than the 1K, 1W resistor can charge it. The arrangement shown in Figure B results in a transition time of about 1.5µS during which both MOSFETs in a given leg are off. This amount of time is a very small portion of the 33µS period toward which we are designing our example.
The power MOSFET transistors, in T0-220 package, are rated at 60V and 12A. The channel "on" resistance is quite low, 0.25 ohms at BA, for the UFN533, resulting in low thermal losses. You can easily find other devices with even lower Ros values, if needed, but as always, the price you pay is that you must pay the price.
Finally, a word about circulating diodes - conspicuous in Figure B by their absence. All power MOSFETs have an intrinsic rectifier, or body diode, a junction rectifier whose current rating is the same as that of the transistor. With the drive format provided by the UC1637, the two bottom MOSFETs (N-channel) are "on" during the time when motor current circulates, and as a result, the reversed diode carries only a small portion of the current; most of it flows from source to drain through the channel. In fact, the diode fully conducts only during the 1.5µS when both devices in one bridge leg are off. You can add fast recovery diodes in shunt with the MOSFETs if you find that they are essential. The intrinsic MOSFET diode is not particularly fast, and as your output current requirements increase, the need for fast external diodes will become more and more apparent.
9-81
APPLICATION NOTE
+Vs
U-102
lK
lK
lK
lK
CURRENT [ SENSE
----~
TWISTED PAIR
Rs= 0.025 -Vs
Ql, Q2 - 2N2905A Q3, Q4 - 2N2219A 12Vz - 1N4742
FIGURE 8. THIS BA POWER AMPLIFIER IS SUITABLE FOR 30KHz OPERATION.
THE SERVOMOTOR
It is convenient to represent the DC servomotor by a simple equivalent circuit, and one such circuit is shown in Figure 9. Note that by expressing the moment of inertia J and the motor constant K in metric units (Nm sec2 and Nm/A respectively), we avoid the need to include a multiplying constant in the expressions for CM and ea. Also, the motor constant K, in metric units, defines both the voltage con-
eo =Kw
*
FIGURE 9. EQUIVALENT CIRCUIT OF MOTOR, WHERE J IS THE TOTAL MOMENT OF INERTIA OF ROTOR PLUS LOAD. RA= armature resistance; ohms. LA= armature inductance; hen·rys.
CM = equivalent capacitance: farads.
J = total moment of Inertia; Nm sec2. K =motor constant; volt sec/rad, or Nm/A. w = rotor angular velocity; rad/sec.
stant in volt-sec/rad, and the torque constant in Nm/A, as
one and the same number.
The ratio J/K2 has the dimensions of capacitance, with a value runnng to several thousand microfarads. The voltage across this capacitor is equal to Kw where w is the angular velocity of the rotor in rad/sec. Consequently, this voltage is the analog of shaft velocity.
Our equivalent circuit, then, is a simple series connection of RA. the armature resistance; LA, the armature inductance; and CM, the equivalent capacitance, equal to J/K2. It should come as no surprise that such a circuit will have a natural resonant frequency WN, and a resonant Q as well. This is indeed the case, and we have for its transfer function,
(S/WN)2 + S/0WN + 1
(12)
where
v K
WN=
LAJ
(13)
TO CONVERT FROM oz in sec2 volts/KRPM
TO Nm sec· volt sec/rad
MULTIPLY BY
7.06 x 10-·
9.55 x io-·
and Q= ~RAV~T
(14)
9-82
APPLICATION NOTE
We can now use these sample results in our sample design. Here are some of the data given by a motor manufacturer:
EG & G TORQUE SYSTEMS MODEL NO. MT-2605-102CE (motor - tach assembly)
MOTOR: KT= 4.7 oz in/amp
Kv = 3.5V /KRPM
RA= 0.7 ohms
JM =0.0018 oz in sec2
TM= 8.6 ms (mech. time const.) Te= 1.6 ms (el. time const.)
TACH: JT = 0.001 oz in sec2 Kv = 3V/KRPM
The several motors in this series and size have the same electrical time constant TE, and since we know RA,
~ = TE RA = 0.016 x 0.7 LA= 1.12 mH
The total moment of inertia is
J =JM+ JT = 0.0018 + 0.001
J = 0.0028 oz in sec2
In metric units,
J = 0.0028 (Nm sec2) 141.612
Putting KT in metric units,
K = 14~:~12 (Nm/amp)
The equivalent capacitance is
C _~ M- K2
_ -
141.612 X 0.0028 (4.7)2
= 18,00.0uF 1-''
For the equivalent circuit, then, the values are
RA= 0.7 ohms
~=1.12mH
CM = 18,000µf
The angular velocity will be proportional to the voltage eo across CM;
w= -eo
K
U-102
RA= 0.70
T = 0.857
eo =Kw
i JCM = 18,000µf
T= tach voltage canst. motor voltage canst.
FIGURE 10. THE TACH VOLTAGE e, IS PROPORTIONAL TO w.
If the motor has a tachometer attached, we can include it in the equivalent circuit by deriving an equivalent tach voltage proportional to eo. This is illustrated in Figure 10, where
T = Tach. voltage constant
Motor voltage constant
T =
3V/KRPM 3.5V/KRPM = ·857
From Eq. 13, From Eq. 14,
WN = 222.7 rad/sec
Q = 0.356
2 (Note: Since ( = ~ , the damping factor here is 1.4)
From Eq. 12 and the above data, we can write the ratio of tach voltage to input as
ei{s) _
·~·8_5_7_ __
(15)
e1(s) - /~\\ __s__ +1
\222.7 / 79.3
THE VELOCITY LOOP
Our objective is to put together a feedback loop using our
UC1637, H-bridge, and motor: the controlled variable is w,
the motor shaft's angular velocity. For high accuracy, we need a high loop gain, so that small velocity errors are magnified and corrected. The UC1 637 internal ERROR amplifier is appropriate for this purpose, and will be used as a summing amplifier. But before proceeding, let us take a look at Figure 11, where a plot of the motor-tach transfer function (Eq. 17) is shown. The plot shows that as the frequency increases, the tach output decreases and the phase lag increases towards a maximum of 180°. This means that although we can introduce plenty of gain at very low frequencies, where the phase lag is low, the added gain must be reduced at the higher frequencies, where the 180° phase lag tends to make our loop a regenerative one. If we want the closed loop response to be "snappy", that is, if we want a bandwidth of several tens of hertz, then the loop gain must be
9-83
APPLICATION NOTE
U-102
FREQUENCY - (rad/sec)
FIGURE 11. PLOT OF MAGNITUDE AND ANGLE OF EQ. 15, WHICH DESCRIBES PERFORMANCE OF OUR TEST MOTOR.
fairly high at all frequencies in the band: yet, for flat response and fast step response with no overshoot we must make certain that the overall phase shift is less than 180° at any frequency at which the gain is greater than unity.
somewhere at midrange, even though the high frequency asymptote is still at zero degrees (RA and CA introduce both a zero and a pole). The transfer function of the circuit shown in Figure 12 is plotted in Figure 13 for the following component values:
R,=9.1K RA= 1K CA= .22µ! Re= 470K Ce= .0047µ!
The break frequencies are:
Re Ce
- - - - - - = 450 rad/sec (R1 +RA) CA
R,~e = 23,400 rad/sec
RA~A = 4,500 rad/sec
A(s)
.Af§l _ (1 + sReCe) (1 + s<R1 + RA) CA]
B(s) -
sR 1Ce (1 + sRACA)
FIGURE 12. ERROR AMPLIFIER WITH ITS FREQUENCY COMPENSATION NETWORK.
THE MAGNITUDE AND ARGUMENT OF THE TRANSFER FUNCTION CAN BE EASILY PLOTTED WITH THE AID OF A PROGRAMMABLE CALCULATOR.
The plot shown in Figure 14 shows the result of cascading the compensation amplifier, PWM amplifier, and motortach. All gain contributions have been simply added together, and all phase contributions have also been added. The result, shown in Figure 14, shows the open loop frequency response of the complete velocity control system .
The high gain ERROR amplifier of the UC1637, together with
a few external components, is· shown in Figure 12. Without
RA and CA, the phase response of the circuit would go from
-90° at low frequencies to 0° at high frequencies. This
amount of phase correction is inadequate if we want a tight
loop with good transient response. With RA and CA shunting
R,, it becomes possible to have a leading phase angle
iD
~:9,
~
::~ - - 70 ,------.--.----.-----.---,,..-- +90"
+60°
4o
l-----l----~ -l--__:I ::'""'-~ 4IL-~+---+..-....-...l.. o+30 0"
c
".J
--7 ~ 30 t------+-+---TL--1--+----+---i -30 ~
20 t------+-+>'~~P_H_A_SE-t--t------+-; _600 1[
-----+-' 10 """"='---+-+-----j--+----+--4 -90"
_ __ _ ,_ o~---'--._L_
10
50 100
500
_ _ i __ _ _._L_~
lK
SK !OK
FREQUENCY - (rad/sec)
FIGURE 14. OVERALL OPEN-LOOP RESPONSE, INCLUDING +BdB DUE TO PWM AMPLIFIER GAIN AND MOTOR-TACH DC GAIN.
The inclusion of the ERROR amplifier with its compensation components has had the effect of introducing a large amount of gain at the lower frequencies, and also of reducing the phase lag at the higher frequencies. The loop gain is OdB at about ?KHz, and the phase margin is about 40°.
Moreover, since the phase never exceeds 180°, we have the needed indication of relative stability, and can proceed to close the loop as shown in Figure 15 and make measurements. Note that a noise filter has neen added at the output of the tachometer. Such a filter is usually necessary, especially in PWM control loops of relatively wide bandwidth, because of the inevitable AC coupling between the motor signal and the tach output. In our filter, the 3dB cut-off point
FIGURE 13. MAGNITUDE AND ANGLE OF COMPENSATION AMPLIFIER OF FIGURE 12.
is at 21 KHz, which is high enough not to affect the loop behavior.
9-84
APPLICATION NOTE
U-102
!K
22µf
9.!K
l
r-------------1
I
I
I
I
I
I
\ 0.70
l.12mh
I I
eo =Kw
MOTOR-TACH
,--------------,
I
470
I ~~~~~~1--<>----"!'\fV~~I---~---7-~~~~~~~~~~~c
J
T
I
I
I
I I
I
l_f1 ~o~~F~T~R I
.22
__- ___ J
:~ ~~IJ :
0
I
L_ ______
FIGURE 15. THE COMPLETE VELOCITY LOOP.
The oscilloscope trace shown in Figure 16 reveals that the step response of our loop is very well behaved. The motor shaft reaches full speed in less than 1OmS, and there is no noticeable overshoot. The net velocity change in Figure 16 amounts to 133 RPM, and the current trace shows that the current does not quite reach the chosen limit of BA. With larger input steps, the motor accelerates at constant BA current, and the acceleration rate is approximately 1OORPM per millisecond. The 3dB bandwidth of the loop measured about BOHz.
Top trace: 5A/cm Bottom trace: lOOmV/cm Horizontal: 5 msec/cm
CONCLUSIONS
We have discussed in some detail the characteristics of Unitrode's UC1 637 and have presented in detail a design approach which illustrates those points. The sample design was built and tested, with the measured results as presented above. These results show that excellent perfo;mance can be obtained with few components, and that the design technique is quite simple. Our velocity loop would perform well as an inner loop in a position control system, for example, although a different response might perhaps be desirable. However that may be, using the UC1637 a sizable portion to the job is completed beforehand.
FIGURE 16. STEP RESPONSE OF THE VELOCITY CONTROL LOOP OF FIGURE 15. THE UPPER TRACE SHOWS THE MOTOR CURRENT; THE LOWER TRACE SHOWS THE TACH OUTPUT VOLTAGE, I.E., MOTOR VELOCITY.
See Figure 17.
ACKNOWLEDGMENTS
We are grateful to EG & G Torque Systems for providing the motor-tachometer used in the sample design. The Electro-Craft Corporation generously supplied a copy of their engineering handbook on DC Motors, 5th Edition. This book is highly recommended.
9-85
--1--.JC
~b1~·
"":C:l :r:~:J-0.0..
O ::J CD
:o~:J ~!ClD1.~c-c
.Wi:.Cg!J~-,
rum[
~~~
-""a
~·
.
(c')
O~i;t
·. C1
-nae
$(in.a
OoJ x0 ~0 c.uWc-r.
.i:.ffig
I\) ·
ct~
e-n"":~:J. 03
Cl (')
!'
z
:C;D:
I
Cl
co 3
.C'ID ""eCnl
O> 2:
Cil
0
~
~
w
CD CD
T.lµf
0
~~~e-~~~~~~~~~~~..-~~~~~~~~~~..-~-...~-..-~~-..-~~~~~-.-~~-.~-.-~-..--~-+15v
lK
IK
>
PNP - 2N2905A, OR EQUIVALENT .,,
~f~z ~ '\%Wff'o~RE~<t,~~~~~~~T ~
cs
!I
6
0
15K
15K
+Vs
2
IRF9531
5.IK
5.IK
(2PL)
2
~
I +VrH
4 Aour
._~~~~-+~~~-+-~~+-~~~~~~~~~~~~~~'"
J
!OK
IK
IW
3
(
VTH
15K
5K
9
BoN
·-r 5.IK
UFN533 (2PL)
5.IK
39K
18
Rr
UC1637
5K
11
+A1N
IK
lK
Cr
+81N
15K
~J 1000µ1
-A1N
SD
12
IK
+C/L ~/\/\l'------i
-C/L~/\/\
.025K 3W
I I I I
1 I I
MOTOR-TACH: EG & G TORQUE SYSTEMS MODEL MT-2605·102CE
-!5V
')
+E/A
l 7 .0047µ1
-Vs -E/A
16
470K
9.IK
NOTES: ADEQUATE BYPASSING OF POS. & NEG. RAILS IS ESSENTIAL. PWM FREQUENCY IS 30KHz APPROX. INTRINSIC MOSFET DIODES HANDLE CIRCULATING CURRENTS. CURRENT LIMIT= BA APPROX. "'TWISTED PAIR
15V
I I
I I I I I
INPUT
R
(VELOCITY COMMAND)
.22µ1
.lµf
.22µ1
.-:z~Kµ/'-+-~~~~~~~~~~~~~~~
SELECT VALUE OF R FOR DESIRED GAIN.
WITH R = 9.IK, GAIN WILL BE 333.3 RPM PER VOLT.
c...:.
FIGURE ff COMPLETE VELOCITY CONTROL LOOP OF SAMPLE DESIGN.
2
n n L.::::::::J
INTEGRATED CIRCUITS
-UNITRDDE
APPLICATION NOTE
U-104
IMPROVED CHARGING METHODS FOR
LEAD-ACID BATTERIES USING THE UC3906
ABSTRACT
This paper describes the operation and application of the UC3906 Sealed Lead-Acid Battery Charger. This IC provides reductions in the cost and design effort of implementing optimal charge and hold cycles for lead-acid batteries. Described are the design and operation of several charging circuits using this IC. The charger designs use current and voltage sensing combined with sequenced current and voltage control to maximize battery capacity and life for various applications. The presented material provides insight into expected improvements in battery performance with respect to these specific charging methods. Also presented are uses of the many auxiliary functions included on this part. The unique combination of features on this control IC has made it practical to create charge and hold cycles that truly get the most out of a battery.
AN IC FOR CHARGING LEAD-ACID BATTERIES
Battery technology has come a long way in recent years. Driven by the reduction of size and power requirements of processing functions, batteries now are used to provide portability and failsafe protection to a new generation of
electronic systems. Although a number of battery technologies have evolved, the lead-acid cell remains the workhorse of the industry due to its combination of prolonged standby and cycle life with a high energy storage capacity. The makers of uninterruptible power supplies, portable equipment, and any system that requires failsafe protection are taking advantage of the improvements in this technology to provide secondary power sources to their products, for example, the sealed cell, using a trapped or gelled electrolyte, has eliminated the positional sensitivity and greatly reduced the dehydration problem.
The charging methods used to replenish or maintain the charge on a lead-acid battery have a significant effect on the performance of the cells. Building an optimum charger, one that gets the most out of a battery, is not a trivial task. Making sure that a battery undergoes the proper charge and hold cycle requires precision sensing and control of both voltage and current, logic to sequence the charger through its cycle, and temperature corrections - added to the charger's control and sensing circuits - to allow proper charging at any temperature. In the past this has required a significant number of components, and a substantial design effort as well. The UC3906 Sealed Lead-
UC3906 BLOCK DIAGRAM
STATE LEVEL CONTROL
g OVER·CHARGE INDICATE
OVER·CHARGE 8 TERMINATE
FIGURE 1. The UC3906 Seaieo Lead-Acid Battery Charger combines precision voltage and current sensing with vol· tage and current control to realize optimum battery charge cycles. Internal charge state logic sequences the device through charging C)Cles. Voltage control and sensing is referenced to an internal voltage that specially tracks the temperature characteristics of lead-acid cells.
9-87
APPLICATION NOTE
U-104
Acid Battery Charger has all the control and sensing functions necessary to optimize cell capacity and life in a wide range of battery applications.
The block diagram for the UC3906 is shown in figure 1. Separate voltage loop and current limit amplifiers regulate the output voltage and current levels in the charger by con~ trolling the onboard driver. The driver will supply 25mA of base drive to an external pass element. Voltage and current sense comparators are used to sense the battery condition and respond with logic inputs to the charge state logic. The charge enable comparator on this IC can be used to remotely disable the charger. The comparator's 25mA trickle bias output is active high when the driver is disabled. These features can be combined to implement a low current turn-on mode in a charger, preventing high current charging during abnormal conditions such as a shorted or reversed battery.
A very important feature of the UC3906 is its precision reference. The reference voltage is specially temperature compensated to track the temperature characteristics of lead-acid cells. The IC operates with very low supply current, only 1.7mA, minimizing on-chip dissipation and permitting the accurate sensing of the operating environmental temperature. In addition, the IC includes a supply under-voltage sensing circuit, used to initialize charging cycles at power on. This circuit also drives a logic output to indicate when input power is present. The UC3906 is specified for operation over the commercial temperature range of 0°C to 70°C. For operation over extended temperatures, -40°C to 70°C the UC2906 is available.
WHAT IS IMPORTANT IN A CHARGER?
Capacity and life are critical battery parameters that are strongly affected by charging methods. Capacity, C, refers to the number of ampere-hours that a charged battery is rated to supply at a given discharge rate. A battery's rated capacity is generally used as the unit for expressing charge and discharge current rates, i.e., a 2.5 amp-hour battery charging at 500mA is said to be charging at a C/5 rate. Battery life performance is measured in one of two ways; cycle life or stand-by life. Cycle life refers to the number of charge and discharge cycles that a battery can go through before its capacity is reduced to some threshold level. Standby life, or float life, is simply a measure of how long the battery can be maintained in a fully charged state and be able to provide proper service when called upon. The measure which actually indicates useful life expectancy in a given application will depend on the particulars of the application. In general, both aspects of battery life will be important.
During the charge cycle of a typical lead-acid cell, lead sulfate, PbS04, is converted to lead on the battery's negative plate and lead dioxide on the battery's positive plate. Once the majority of the lead sulfate has been converted, overcharge reactions begin. The typical result of over-charge is the generation of hydrogen and oxygen gas. In unsealed batteries this results in the immediate loss of water. In sealed cells, at moderate charge rates, the majority of the hydrogen and oxygen recombine ·before dehydration occurs. In either type of cell, prolonged charging rates significantly above C/500, will result in dehydration, accelerated grid corrosion, and reduced service life.
The onset of the over-charge reaction will depend on the
rate of charge. At charge rates of > C/5, Jess than 80% of
the cell's previously discharged capacity will be returned as the over-charge reaction begins. For over-charge to coincide with 100% return of capacity, charge rates must typically be reduced to less than C/100. Also, to accept higher rates the battery voltage must be allowed to increase as over-charge is approached. Figure 2 illustrates this phenomenon, showing cell voltage vs. percent return of previously discharged capacity for a variety of charge rates. The over-charge reaction begins at the point where the cell voltage rises sharply, and becomes excessive when the curves level out and start down again.
2.8
vj::f::
2.7
c{s- ~. I-
2.6
vr- c1:1~
2.5
2.4 H-++++-H-+M-~-+-++1-+-l
~ 2.· f-+-+++-Hi-+-.ll-llh,V,1-141.4"0!++-i>-l-l
~ l l v ~ 2.2 1++++-r;::""~'l-vi4v!i,J4+-1-1-1f.l..l.-w
2.1 IP V'
2.0 flb'+++-HH-++++-1-+-++l-+-l
1.9 f-+-+++-HH-++++-IH-J++..-1-l
25 50 75 100 125' 150
PERCENT OF PREVIOUS DISCHARGE CAPACITY RETURNED
VOLTAGE CURVES FOR CELLS CHARGED AT VARIOUS CONSTANT
(CURRENT) RATES AT ROOM TEMPERATURE
FIGURE 2. Depending on the charge rate, over-charge reactions begin, (indi· cated by the sharp rise in battery voltage), well below 100% return of capacity. (Reprinted with the permission of Gates Energy Products, Inc.)
9-88
APPLICATION NOTE
U-104
Once a battery is fully charged, the best way to maintain the charge is to apply a constant voltage to the battery. This burdens the charging circuit with supplying the correct float charge level; large enough to compensate for self-discharge, and not too large to result in battery degradation from excessive overcharging. With the proper float charge, sealed lead-acid batteries are expected to give standby service for 6 to 10 years. Errors of just five percent in a float charger's characteristics can halve this expected life.
To compound the above concerns, the voltage characteristics of a lead-acid cell have a pronounced negative temperature dependence, approximately -4.0mV/°C per 2V cell. In other words, a charger that works perfectly at 25°C may not maintain or provide a full charge at 0°C and conversely may drastically over-charge a battery at +50°C. To function properly at temperature extremes a charger must have some form of compensation to track the battery temperature coefficient.
To provide reasonable re-charge times with a full 1000/o return of capacity, a charge cycle must adapt to the state of charge and the temperature of the battery. In sealed, or recombinate, cells, following a high current charge to return the bulk of the expended capacity, a controlled overcharge should take place. For unsealed cells the overcharge reaction must be minimized. After the over-charge, or at the onset of over-charge, the charger should convert to a precise float condition.
A DUAL LEVEL FLOAT CHARGER
A state diagram for a sealed lead-acid battery charger that would meet the above requirements is shown in figure 3.
w
"~ '
I
locr
IS!
f-
:aJ_
f-
:J 0
STATE 1
wa:
"'a:
u:<r(:
STATE 1: BULK CHARGE
STATE2' OVERCHARGE
STATE3' FLOAT CHARGE
CHARGER OUTPUT CURRENT
FIGURE 3. The dual level float charger has three charge states. A constant current bulk charge returns 70-900/o of capacity to the battery with the remaining capacity returned during an elevated (constant) voltage over-charge. The float charge state maintains a precision voltage across the battery to optimize stand-by life.
This charger, called a dual level float charger, has three states, a high current bulk charge state, an over-charge state, and a float state. A charge cycle begins with the charger in the bulk charge state. In this state the charger acts like a current source providing a constant charge rate at IMAX· The charger monitors the battery voltage and as it reaches a transition threshold, V, 2, the charger begins its over-charge cycle. During the over-charge, the charger regulates the battery at an elevated voltage, Voe, until the charge rate drops to a specified transition current, locr. When the current tapers to locr, with the battery at the elevated level, the capacity of the cell should be at nearly 1000/o. At this point the charger turns into a voltage regulator with a precisely defined output voltage, VF. The output voltage of the charger in this third state sets the float level for the battery.
With the UC3906, this charge and hold cycle can be implemented with a minimum of external parts and design effort. A complete charger is shown in figure 4. Also shown are the design equations to be used to calculate the element values for a specific application. All of the programming of the voltage and current levels of the charger are determined by the appropriate selection the external resistors Rs, RA, Rs, Re.
Operation of this charger is best understood by tracing a charge cycle. The bulk charge state, the beginning, is initiated by either of two conditions. One is the cycling on of the input supply to the charger; the other is a low voltage condition on the battery that occurs while the charger is in the float state. The under-voltage sensing circuit on the UC3906 measures the input supply to the IC. When the input supply drops below about 4.5V the sensing circuit forces the two state logic latches (see figure 1) into the bulk charge condition (L1 reset and L2 set). This circuit also disables the driver output during the under-voltage condition. To enter the bulk charge state while power is on, the charger must first be in the float state(both latches set). The input to the charge state logic coming from the voltage sense comparator reports on the battery voltage. If the battery voltage goes low this input will reset L1 and the bulk charge state will be initiated.
With L1 reset, the state level output is always active low. While this pin is low the divider resistor, Rs is shunted by resistor Re, raising the regulating level of the voltage loop. If we assume that the battery is in need of charge, the voltage amplifier will be in its stops trying to turn on the driver to force the battery voltage up. In this condition the voltage amplifier output will be over-ridden by the current limit amplifier. The current limit amplifier will control the driver, regulating the output current to a constant level. During this
9-89
APPLICATION NOTE
U-104
time the voltage at the internal, non-inverting, input to the voltage sense comparator is equal to 0.95 times the internal reference voltage. As the battery is charged its voltage will rise; when the scaled battery voltage at PIN 13, the inverting input to the sense comparator, reaches 0.95Vref the sense comparator output will go low. This will reset the second latch and the over-charge state will be entered. At this time the over-charge indicator output will go low. Other than this there is no externally observable change in the charger. Internally, the starting of the over-charge state arms the set input of the first latch - assuming no reset signal is present - so that when the over-charge terminate input goes high, the charger can enter the float state.
In the over-charge state, the charger will continue to supply the maximum current. As the battery voltage reaches the elevated regulating level, Voe, the voltage amplifier will take command of the driver, regulating the output voltage at a constant level. The voltage at PIN 13 will now be equal to the internal reference voltage. The battery is completing its charge cycle and the charge acceptance will start to taper off.
As configured in figure 4, the current sense comparator continuously monitors the charge rate by sensing the voltage across Rs. The output of the comparator is connected to the over-charge terminate input. Whenever the
charge current is less than locr. (25mV/Rs), the open collector output of the comparator will be off. When this transition current is reached, as the charge rate tapers in the over-charge state, the off condition of the comparator output will allow an internal 10µA pull-up current at PIN 8 to pull that point high. A capacitor can be added from ground to this point to provide a delay to the over-charge-terminate function, preventing the charger from prematurely entering the float state if the charging current temporarily drops due to system noise or whatever. When the voltage at PIN 8 reaches its 1V threshold, latch L1 will be set, setting L2 as well, and the charger will be in the float state. At this point the state level output will be off, effectively eliminating Re from the divider and lowering the regulating level of the voltage loop to VF.
In the float state the charger will maintain VF across the battery, supplying currents of zero to IMAX as required. In addition, the setting of L1 switches the voltage sense comparator's reference level from 0.95 to 0.90 times the internal reference. If the battery is now discharged to a voltage level 10% below the float level, the sense comparator output will reset L1 and the charge cycle will begin anew.
The float voltage VF, as well as Voe and the transition voltages, are proportional to the internal reference on the UC3906. This reference has a temperature coefficient of
+
INPUT UPPLY
j_
+
BATIE RY
j_
INPUT
POWER~+--1
MONITOR
-=
&) ~ 1.) Voe= VREF(1 + ..i.
Ra :Re
3.) V12 = .95Voc
= 4.) V31 .9VF
5.) IMAX = ·25V Rs
6.) locr = .02sv Rs
FIGURE 4. Using a few external parts and following simple design equations the UC3906 can be configured as a dual level float charge'
9-90
APPLICATION NOTE
U-104
-3.9mV/°C. This temperature dependence matches the recommended compensation of most battery manufacturers. The importance of the control of the charger's voltage levels is reflected in the tight specification of the tolerance of the UC3906's reference and its change with temperature, as shown in figure 5.
INTERNAL REFERENCE TEMPERATURE CHARACTERISTIC AND TOLERANCE
>
I
:?
z 2.50 ii:
:..c. ~...
scz:J
::i
.Ill
IC
u
ill :f:f;i
IC
2·~40 -30 -20 -10
VREF GUARANTEED TOLERANCE
OVER TEMPERATURE
TEMPERATURE - °C
FIGURE 5. The specially temperature compensated reference on the UC3906
o is tightly specified over to 70°C, (-40 to 70°C for the UC2906), to allow proper
charge and hold characteristics at all temperatures.
IMAX. locr. Voe, and VF can all be set independently. IMAX, the bulk charge rate can usually be set as high as the available power source will allow, or the pass device can handle. Battery manufacturers recommend charge rates in the C/20 to C/3 range, although some claim rates up to and beyond 2C are OK if protection against excessive overcharging is included. locr, the over-charge terminate threshold, should be chosen to correspond, as close as possible, to 100% recharge. The proper value will depend on the over-charge voltage <Yoe) used and on the cell's charge current tapering characteristics at Voe.
IMAX and locr are determined by the offset voltages built into the current limit amplifier and current sense comparator respectively, and the resistor(s) used to sense current. The offsets have a fixed ratio of 250mV/25mV. If ratios other than ten are necessary separate current sensing resistors or a current sense network, must be used. The penalty one pays in doing this is increased input-to-output differential requirements on the charger during high current charging. Examples of this are shown in figure 6.
An alternative method for controlling the over-charge state is to use the over-charge indicate output, PIN 9, to initiate an external timer. At the onset of the over-charge cycle the over-charge indicate pin will go low. A timer triggered by this signal could then activate the over-charge terminate input, PIN 8, after a timed over-charge has taken place. This method is particularly attractive in systems with a centralized system controller where the controller can provide the timing function and automatically be aware of the state of charge of the battery.
The float, VF, and over-charge, Voe. voltages are set by the internal reference and the external resistor network, RA, Rs, and Re as shown in figure 4. For the dual level float charger the ranges at 25°C for VF and Voe are typically 2.~V-2.40V and 2.4V-2.7V, respectively. The float charge level will normally be specified very precisely by the battery manufacturer, little variation exists among most battery suppliers. The over-charge level, Voe, is not as critical and will vary as a function of the charge rate used. The absolute value of the divider resistors can be made large, a divider current of 50µA will· sacrifice less than 0.5% in accuracy due to input bias current offsets.
AUXILIARY CAPABILITIES OF THE CHARGER IC
Besides simply charging batteries, the UC3906 can be used to add many related auxiliary functions to the charger that would otherwise have to be added discretely. The enable comparator and its trickle bias output can be used in a number of different ways. The modification of the state diagram in figure 2 to establish a low current turn-on mode
INPUT SUPPLY
PASS ELEMENT
Rs
'·=~c~t;~=~r~~~·
I
+V1N
CIS+ UC39GI C/S-
I C/L
I
Rs1
R32
~+~~
IMAX
250mV I Rs
locr = 25mVI Rs
IJ.VMAX = 250mV
IMAX = 250mV I Rs1 locr = 25mV I (Rs1 + FiS2)
4VMAX = 250mV·IMAXi(101ocr)
IMAXllQCT >10
IMAX = 250mV I (Rs1 + RS2)
locr
25mV I As1
4VMAX = 250mV
FIGURE 6. Although the ratio ol input offset voltages on the current limtt and current sense stages is fixed at 10, other ratios for IMAicllocr are easily obtained. Note that a penalty for ratios greater than 10 is increased voltage drop across the sensing network at IMAX·
9-91
APPLICATION NOTE
U-104
of the charger (see figure 7) is easily done. By reducing the output current of the charger when the battery voltage is below a programmable threshold, the charging system protects against: One, high current charging of a string with a shorted cell that could result in excessive outgassing from the remaining cells in the string. Two, dumping charge into a battery that has been hooked up backwards. Three, excessive power dissipation in the charger's pass element. /ls shown in figure 7, the enable comparator input taps off the battery sensing divider. When the battery voltage is below the resulting threshold, Vr, the d(iver on the UC3906 is disabled and the trickle bias output goes high. A resistor, Ar, connected to the battery from this output can then be used to set a trickle current, (:;; 25mA) to the battery to help the charger discriminate between severely discharged cells and damaged, or improperly connected, cells.
In applications where the charger is integral to the system, i.e. always connected to the battery, and the load currents on the battery are very small, it may be necessary to absolutely minimize the load on the battery presented by. the charger when input power is removed. There are two simple precautions that, when taken, will remove essentially all reverse current into the charging circuit. In figure 8 the diode in series with the pass element will prevent any reverse current through this path. The sense divider should still be referenced directly to the battery to maintain accurate control of voltage. To eliminate this discharge
path, the divider in the figure is referenced to the open collector power indicate output, PIN 7, instead of ground. Connected in this mannerthe divider string will be in series with essentially an open when input power is removed. When power is present, the open collector device. will be on, holding the divider string end at nearly ground. The saturation voltage of the open collector output is specified to be less than 50mV with a load current of 50µA.
Figure 9 illustrates the use of the enable comparator and its output to build over-discharge protection into a charger. Over-discharging a lead-acid cell, like over-charging, can severely shorten the service life of the cell. The circuit monitors the discharging of the battery and disconnects all load from the battery when its voltage reaches a specified cutoff point. The load will remain disconnected from the battery until input power is returned and the battery recharged.
This scheme uses a relay between the battery and its load that is controlled by 01 and the presence of voltage across the load. When primary power is available 01 is on via 05. The battery is charging, or charged, and the trickle bias output at PIN 11 is off. When input power is removed, C2 provides enough hold-up time at the load to let 01 turn off, and the relay to close as current flows through R1. The battery is now providing power.to the load and, through 01, power to the charger. The charger current draw will typically be less than 2mA. /ls the battery discharges, the UC3906 will continue to monitor its voltage. When the vol-
STATE DIAGRAM' UC2906 DUAL LEVEL FLOAT CHARGER
PASS ELEMENT
- - ~C3908-,
i- BATTERY (Ve)
STATE 2 Voe
~ ---7-1----,.....;
~ Ir locr
STATE 3
"~' I
0 aw :
~ ~ u
STATE 1
STATE 1, BULK CHARGE STATE 2, OVER CHARGE STATE 3, FLOAT CHARGE
CHARGER OUTPUT CURRENT
DRIVER DISABLE
VOLTAGE SENSE INPUT
STATE LEVEL OUTPUT -
_ _ _ _ _ _J
RA(1-K)
"·
~ Vr = VREF + K-. - AA - ) (1-K)RA. +Rx
h = V1N -Vr - 2.0V
"'
WHERE: K IS A CONSTANT:S1 Ac Re
Rx=--· Re+ Re
WHERE: V1N 15 THE INPUT SUPPLY 2.0V IS THE DROP FROM +V1N TOPIN 11
FIGURE 7. The charge enable comparator, with its trickle bias output, can be used to build protection into the charger. The current fold back at low battery voltages prevents high current charging of batteries with shorted cells, or improperly connected batteries, and also protects the pass element from excessive power dissipation.
9-92
APPLICATION NOTE
U-104
tage reaches the cut-off level, set by the divider network, R5-R8, the trickle bias output, PIN 11, will go high. 01 will turn back on and the relay current will collapse opening its contacts. As the load voltage drops, capacitor C1 supplies power to the UC3906 to keep 01 on. Once the input to the charger has collapsed the power indicate pin, as shown in figure 8, will open the divider string. The battery will remain open-circuited until input power is returned. At thattime the battery will begin to recharge.
;~E~~~~ ~---f------,,-0+
_rBATTERY
STATE LOGIC
INPUT SUPPLY SENSE
'!£!90_L - -=--- - _J
FIGURE 8. By using a diode in series with the pass element, and referencing the divider string to the power indicate pm, pin 7, reverse current into the charger, (when the charger is tied to the battery with no input power), can be eliminated.
CHARGING LARGE SERIES STRINGS OF LEAD-ACID CELLS
When large series strings of batteries are to be charged, a dual step current charger has certain advantages over the float charger of figures 3 and 4. A state diagram and circuit implementation of this type of charger is shown in figure 10. The voltage across a large series string is not as predictable as a common 3 or 6 cell string. In standby service varying self discharge rates can significantly alter the state of charge of individual cells in the string if a constant float voltage is used. The elevated voltage, low current holding state of the dual step current charger maintains full and equal charge on the cells. The holding, or trickle current, IH, will typically be on the order of 0.005C to 0.0005C.
To give adequate and accurate recharge this charger has a bulk charge state with temperature compensated transition thresholds, V12, and V21 . Instead of entering an elevated voltage over-charge, upon reaching V12 the charger switches to a constant current holding state. The holding current will maintain the battery voltage at a slightly elevated level but not high enough to cause significant overcharging. If the battery current increases, the charger will attempt to hold the battery at the VF level as shown in the state diagram. This may happen if the battery temperature increases significantly, increasing the self-discharge rate beyond the holding current. Also, immediately following the transition from the bulk to float states, the battery will only be 80% to 900/o charged and the battery voltage will drop to the VF level for some period of time until full charging is achieved.
In this charger the current sense comparator is used to regulate the holding current. The level of holding current is determined by the sensing resistor, RsH. The other series
CHARGER'S PRIMARY
~---~POWER
SOURCE
o,
LOAD'S
PRIMARY POWER ----1~--,
SOURCE
o,
u~~9a06 !"('"'"''-----.
PASS ELEMENT
{13)
(10)
As
A,
(7)
LOAD SWITCH RELAY
D, qLOAD c,
Ro
(11)
( ) indicates UC3906 PIN NUMBER
FIGURE 9. Using the enable comparator to monitor the battery voltage a precise discharge cut-oft voltage can be set. When the battery reaches the cut-oft threshold the trickle bial output switches oft the load switch relay and the battery is left open circuited until input power is returned.
9-93
APPLICATION NOTE
U-104
resistor, RE, is necessary for the current sense comparator to regulate the holding current. Its value is selected by dividing the value of IH into the minimum input to output differential that is expected between the battery and the input supply. If the supply variation is very large, or the
holding current large, ( > 25mA), then an external buffering
element may be required atthe output of the current sense comparator.
The operating supply voltage into the UC3906 should be kept less than 45V. However, the IC can be adapted to charge a battery string of greater than 45V. To charge a large series string of cells with the dual step current charger the ground pin on the UC3906 can be referenced to a tap point on the battery string as .shown in figure 11. Since the charger is regulating current into the batteries, the cells will all receive equal charge. The only offset results from the bias current of the UC3906 and the divider string current adding to the current charging the battery cells below the tap point. Rs can be added to subtract the bulk of this current improving the ability of the charger to control the low level currents. The voltage trip points using this technique will be based on the sum of the cell voltages on the high side of the tap.
PICKING A PASS ELEMENT AND COMPENSATING THE CHARGER
There are four factors to consider when choosing a pass device. These are:
1. The pass device must have sufficient current and power handling capability to accommodate the desired maximum charging rate at the maximum input to output differential.
2. The device must have a high enough current gain at the maximum charge rate to keep the drive current required to less than 25mA.
3. The type of device used, (PNP, NPN, or FET), and its configuration, may be dictated by the minimum input to output differential at which the charger must operate.
4. The open loop gain of both the voltage and the current control loops are dependent on the pass element and its configuration.
Figure 12 contains a number of possible driver configurations with some rough break points on applicable current ranges as well as the resulting minimum input to output differentials. Also included in this figure are equations for the dissipation that results on the UC3906 die, equations for a resistor, Ro, that can be added to minimize this dissipation, and expressions for the open loop gains of both the voltage and current loops.
+
BATTERY
-VIN
IIMAX+ IH
- - - - - - -V12
STATE2
__.J
- LI - - - - - - ' i · < l " - v ,
IH
-V21
STATE1-
STATE 1: BULK CHARGE STATE 2: HOLDING CHARGE
CHARGER OUTPUT CURRENT
.95 VREF (1 + ~<mt- ~ )
Ac
Ro
4.) IMAX = ·25V
RsM
2.) v, = VREF (1 + ...&.._) Re
5.) IH
FIGURE 10. A dual step current charger has some advantages when large series strings must be charged. This type of charger maintains constant current during normal charging that results in equal charge distribution among battery cells.
9-94
APPLICATION NOTE
As reflected in the gain expressions in figure 12, the open loop voltage gains of both the voltage and current control loops are dependent on the impedance, Zc at the compensation pin. Both loops can be stabilized by adjusting the value of this impedance. Using the expressions given, one can go through a detailed analysis of the loops to predict respective gain and phase margins. In doing so one must not forget to account for all the poles in the open loop expressions. In the common emitter driver examples, 1 and 3, the equivalent load impedance at the output ot the charger directly affects loop characteristics. In addition, a pole, or poles, will be added to the loop response due to the roll-off of the pass device's current gain, Beta. This effect will occur at approximately the rated unity gain frequency of the device divided by its low frequency current gain. The transconductance terms for the voltage and current limit amplifiers, (1/1.3K and 1/300 respectively), will start to roll off atabout500KHZ. Asaruleofthumb, it is wise to kill the loop gain well below the point that any of these, not-so-predictable poles, enter the picture.
If you prefer notto go through a BODE ana!ysis of the loops to pick a compensation value, and you recognize the fact that battery chargers do not require anything close to optimum dynamic response, then loop stability can be assured by simply oversizing the value of the capacitor used at the compensation pin. In some cases it may be necessary to add a resistor in series with the compensation capacitor to put a zero in the response. Typical values for the compensation capacitor will range from 1000pF to 0.22µF depending on the pass device and its configuration. With composite common emitter configurations, such as example 3 in figure 12, compensation values closer to
COMMON EMITTER PNP
COMPOSITE FOLLOWER
l '·· __
INPUT SUPPLY
~·1SV+
ST!::P
~·lo DCURARL ENT
CHARGER
~:~ I
MATCH~~~ r~IR, LEVEL CURRENT
!
As=~
U-104
[irt=
V~+o
J~[ ~~
v,+_'
L
'---i!J
FIGURE 11. A dual step current charger can be configured to operate with input supplies of greater than 45V by using a tap on the battery to reference the UC3906. The charger uses the voltage across the upper portion of the battery to sense charging transition points. To minimize charging current offsets, R8 can be added to cancel the UC3906 bias and divider currents.
the 0.22µF value will be required to roll off the large open loop gain that results from the Beta squared term in the gain expression. Series resistance should be less than 1K, and may range as low as 100 ohms and still be effective.
The power dissipated by the UC3906 requires attention since the thermal resistance, (100°C/Watt) of the DIP package can result in significant differences in temperature between the UC3906 die and the surrounding air, (battery), temperature. Different driver/pass element configurations result in varying amounts of dissipation at the UC3906. The dissipation can be reduced by adding external dropping resistors in series with the UC3906 driver,
COMPOSITE COMMON EMITTER
NPN EMITTER FOLLOWER OV
TOPOLOGY UC3906 DRIVER
UC3906 DRIVER
UC3906 DRIVER
UC3906 DRIVER
CURRENT RANGE
MINIMUMt:N
UC3906 DRIVER DISSIPATl')N
EXPRESSION FOR Ro
OPEN LOOP" GAIN OF
THE VOLTAGE CONTROL LOOP
OPEN LOOP" GAIN OF
THE CURRENT LIMIT LOOP
25mA <I <1000mA tJ.V >0.5V
Po""' V1N-0.7V. I- I 2 Ro
iSa1
,fflo1
Ro"" V1NMJN-2.0V · .801 MIN IMAX
25mA <I <1000mA t:N >2.0V
Po"" V1N-0.7V-Vour ·I- 12 Ro
f3a1
{3 201
Ro"" V1NM1N-VOUTMAx-1.2V · .801 MIN IMAX
EiOOmA <I <15A
l:N >1.2V
Po"" V1N-0.7V ·I-~
.801 .Ba2
i92a1 fJ 2a2
Ro"" V1N MIN-0.7V. Pa1 MIN/3Q2MIN IMAX
Aov ""~. - 1- . /301 · Zo. VREF
1.3K Ro+ 12
VouT
Aov ""22.. ·.Yfil:.£ 1.3K Vour
Aov "" _IQ__. - 1- . Po1 · f102. Zo. VAEF
1.3K Ro+ 12
VouT
Aoc= Zc · -1-·.Ba1·Rs 300 Ro + 12
Aoc=~·--1--·Rs
300 121fJa1 + Zo
Aoc""~·-1-·fJa1·f3a2·Rs
300 Ro + 12
25mA <I <1000mA il.V >2.7'+/
Po"" V1N-0.7V-VouT ·I-I2 Ro
~01
~'a1
Ro"" VtNMIN-VouTMAX-1.2\1 ·{Ja1MIN IMAX
Aov_~. VAEF 1.3K Vour
Aoc,., ~ · - -1- - · Rs 300 121/301 + Zo
·zc · IMPEDANCE AT COMPENSATION PIN, PIN 14. · IMPEDANCE AT CHARGER OUTPUT.
FIGURE 12. There are a large number of possible driver/pass element configurations, a few are summarized here. The trade-offs are between current gain, input to output differential, and in some cases, power dissipation on the UC3906. When dissipation is a problem it can be reduced by adding a resistor in series with the UC3906 driver.
9-95
APPLICATION NOTE
U-104
(see figure 12). These resistors will then share the power with the die. The charger parameters most affected by increased driver dissipation are the transition thresholds, 0/12 and V21). since the charger is, by design, supplying its maximum current at these points. The current levels will not be affected since the input offset voltages on the current amplifier and sense comparator have very little temperature dependence. Also, the stand-by float level on the charger will still track ambient temperature accurately since, normally, very little current is required of the charger during this condition.
To estimate the effects of dissipation on the charger's voltage levels, calculate the power dissipated by the IC at any given point, multiply this value by the thermal resistance of the package, and then multiply this product by -3.9mV/°C and the proper external divider ratio. In most cases, the effect can be ignored, while in others the charger design must be tweaked to account for die dissipation by adjusting charger parameters at critical points of the charge cycle.
SOME RESULTS WITH THE DUAL LEVEL FLOAT CHARGER
In figure 13 the schematic is shown for a dual level, float charger designed for use with a fN, 2.5amp-hour, sealed lead-acid battery. The specifications, at 25°C, for this charger are listeq below. ·
Input supply voltage ............ 9.0V to 13V Operating temperature range .. ·. , .0°C to 70°C
Start-up trickle current (h) ........ 10mA 0/IN = 10V)
Start-up voltage 0/T) ............ 5.1V Bulk charge rate (IMAX) .......... 500mA (C/5) Bulk to OC transition voltage 0/1i) .. 7.125V QC voltage 0/oc) .............. 7.5V QC terminate current (IOCT) ....... 50mA (C/50) Float voltage 0/F) .............. 7.0V Float to Bulk transition
voltage 0/a1) .......... , ..... 6.3V Temperature coefficient on
voltage levels ............... -12mV/°C Reverse current at charger output
with the input supply at O.OV .... s.5µA
In order to achieve the low input to output differential, (1.5V), the charger was designed with a PN P pass device that can operate in its saturation region under low input supply conditions. The series diode, required to meet the reverse current specification, accounts for 1.0V of the 1.5V minimum differential. Keeping the reverse current under 5µA also requires the divider string to be disconnected when input power is removed. This is accomplished, as discussed earlier, by using the input power indicate pin to reference the divider string.
0.5.P
TIP 328
~~:~[v C>-<,_,,,11"1.--_ _ _ _ _,
1N4001
70K
19K ,-------
1
INPUT
I
SUPPLY
I
FULLY CHARGED
I
820ll
FIGURE 13. This dual level float charger was designed for a &I (thrae 'l!J cells) 2.5AH battery. A separate "fully charged" indicator was added for visual indication of charge completion.
9-96
APPLICATION NOTE
U-104
110%
1-eJKc.JRGE- v HID%
ovJ-eHAJ~
8.0V
:::r:··~~ DUAL ~~::aFLOAT
0.5A
-z,v- l1 i.. T
+J_ 1 ... L
ll
I
PR;~:~::E:---i
8 HOU:.~~~~ RATE -I
7.5V
0.4A
OAl"'T '1"' BATTERY VOLTAGE
" 7.0V c
0.3A
CHARGING
re ~mc 0.2A
1~.1R_ NEONfT CAPACITY
1-'°"
""
CURRENT
~
~ t-
6.0V 0.1A
5.SV
...z..
" u
."az.
c
u"'
10 HOURS ON CHARGE -
FIGURE 14. The nearly ideal characteristics of the dual level float charger are illustrated in these curves. The over-charge state is entered at about 80% return of capacity and float charging begins at just over 100% return.
120% 1-1 BULK~AR:I ~
110%
e.ov
FL~HARGE----i
DUAL~~FLOAT
O.SA
v 100%
CHA,_";io~~LE --j 7.SV
~
.. 90%
_L
=~~~~~~~~~y
0.4A
.... lL - , ~"~I .. ~u
T a,C
.... I " z~.~,
.ti,!. j_ 'iu5"<!u>!
70%
60% ,,_.-j ...-"'r/
50%
I
t GA~'i~~g:TYPE
I
7
-1 BA~~y';J;'AG"'; r--
lCHAAGING lCURRENT
7.0V 1
~ 0.3A
6.SV 0>
re ~ 0.2A
c
6.0V al
... - 'i~EPtCENT 30% 1-----i °£lATCUIRTYN1
0.1A
1 ~ 20%
5.SV
...z1..
" u
."~
u"'
10%
HOURS ON CHARGE -
FIGURE 15. At elevated temperatures the maximum capacity of lead-acid cells is increased allowing greater charge acceptance. To prevent excessive over-charging though, the charging voltage levels are reduced.
D.5A
The driver on the UC3906 shunts the drivecurrentfrom the pass device to ground. The 470ohm resistor added between PIN 15 and ground keeps the die dissipation to less than 100mW under worst case conditions, assuming a minimum forward current gain in the pass element of 35 at 500mA.
The charger in figure 13 includes a circuit to detect full charge and gives a visual indication of charge completion with an LED. This circuit turns on the LED when the battery enters the float state. Entering of the float state is detected by sensing when the state level output turns-off.
Figures 14-16 are plots of charge cycles of the circuit at three temperatures, 25°C, 50°C and 0°C. The plots show battery voltage, charge rate, and percent return of previously discharged capacity. This last parameter is the integral of the charge current over the time of the charge cycle, divided by the total charge volume removed since the last full charge. For all of these curves the previous discharge was an 800/o discharge, (2amp-hours), at a C/10, (250mA), rate. The discharges were preceded by an over-night charge at 25°C.
The less than 100% return of capacity evident in the charge cycle at 0°C is the result of the battery's reduced capacity at this temperature. The tapering of the charge current in the over-charge state still indicates that the cells are being returned to a full state of charge.
REFERENCES_
1. Eagle-Picher Industries, Inc., Battery Notes #200, #205A, #206, #207, #208.
2. Gates Energy Products, Inc., Battery Application Manual, 1982.
3. Panasonic, Sealed Lead-Acid Batteries Technical Handbook.
4. Yuasa Battery Co., Ltd., NP series maintenance-free rechargeable battery Application Manual.
0.4A
""I
0.1A
_tt- 5.SV
10
HOURS ON CHARGE
FIGURE 16. At lower temperatures the capacity of lead-acid cells is reduced as reflected by the less-than-100% return of capacity in this 0°C charge cycie, illustrating the need for elevated charging voltages to maximize returned capacity.
Unitrode Integrated Circuits Corporation
7 Continental Boulevard. ·P.O. Box 399 ·Merrimack, New Hampshire· 03054-0399
Telephone 603-424,2410 · FAX 603-424-3460
9.97
n n INTEGRATED
~CIRCUITS
-UNITRDDE
APPLICATION NOTE
U-106
UC3620
BRUSHLESS DC MOTORS GET A CONTROLLER IC THAT REPLACES COMPLEX CIRCUITS
A COMMUTATOR AND DRIVER CHIP, COMPLETE WITH THERMAL AND UNDER-VOLTAGE PROTECTION AND
TRANSIENT SUPPRESSION, RADICALLY SIMPLIFIES THE CONTROL OF BRUSHLESS DC MOTORS
INTRODUCTION
The popularity of the three-phase, brushless DC motor is on the rise for a number of good reasons: There are no brushes to wear out or to arc over, heat dissipation is better because the windings are on the stator, and good torque control is both possible and relatively easy to achieve with the availability of electronic circuits. The motor's main drawback has been the need to design and assemble a complex circuit consisting of six output power transistors with transient suppression diodes, a switching current control circuit, and a Hall logic decoder, plus loop control and P!Otection circuitry.
The advent of the UC3620 controller chip greatly simplifies the designer's problem, for it integrates all these elements. This chip easily and safely controls motors requiring up to 2A of continuous current, and has a peak rating of 3A. The device has a maximum Vee rating of 40V and is available in a 15-pin package rated at 25W. Only a half dozen external components are needed to get a motor running.
A three-phase brushless DC motor has two, four, or more permanent magnet poles mounted on its rotor. The required rotating field is produced by the stator's stationary windings, whose three phases must be commutated in the proper sequence. This sequence is governed by the rotor's angular position, and consequently, some means must be provided both to sense this position and to use that information to control the commutation sequence.
The sensing is accomplished by three Hall-effect devices mounted on the stator close to the rotor magnets, at the correct rotational angles. An electronic circuit decodes the Hall device signals and controls the direction of the currents applied to the three motor phases. This power switching is done by power transistors.
Another function must be added to the driving electronics, namely, that of controlling the motor current and maintaining it at the correct value. At high speed, the electric motor's back emf limits the phase currents. But at low speeds, the back emf is low (it is zero at stall), and therefore if the current is to be kept constant, the applied
voltage must be reduced. This is done by sensing the motor current and using its value to regulate the duty cycle of the applied voltage, thereby controlling the average motor voltage. In this way, a constant-current source of motor power is obtained.
HOW IT WORKS
In the controller chip, each of the three output stages is a totem-pole pair (Figure 1) capable of sourcing and sinking the motor's full rated current. Inductive transients from the load are clamped to Vee by Schottky diodes and to ground by the intrinsic substrate diodes, thus obviating the need for external clamping devices.
The power output stages have two functions. The first is to commutate the three motor phases in the proper sequence, producing unidirectional torque in the rotor. The second is to switch the applied motor voltage in the manner selected and programmed by the user, maintaining the output current at the desired level. This switching control of current is accomplished in a fixed-off-time, two-quadrant mode, providing the automatic peak current limiting and low ripple current essential to high electrical efficiency at the motor windings.
The emitters of the three bottom transistors of the totempole output stages are connected to Pin 1, through which all the motor current flows. If a low-value resistor is placed between this pin and ground, a usable voltage proportional to motor current is derived without appreciable l2R losses.
This current-sensing voltage serves as a feedback signal for the switching current control loop. It is applied to the lsENSE input through an RC filter, which prevents false triggering due to noise spikes in the current waveform.
An internal voltage comparator determines whether the voltage V1 SENSE is equal to VREF, a positive variable reference voltage dependent on the output of the chip's error amplifier. If Q of the monostable multivibrator (that follows the comparator) is high, the chip's output stages are enabled, the output current increases, and V1 sENsE also increases until it becomes positive with respect to VREF·
9-98
+Vee I0.1µF
·+5V
"
Vour
n~· 10k
TORQUE <,. ..
CONTROL
:h
<D
-
I
·+5V
COMPARATOR
III ~~I $~1 1..
T M't~~$il,T,j'_!3T~R Q
J_ ~1
V1 SENSE
THERMAL SHUTDOWN
111 I UNDER I 111
VOLTAGE
I LOCKOUT
!II 1,4
:r::
10k
-=
I
8
FROERVWERASRED/
SWITCH
7
1k
}001µF
FIGURE 1. THE UC3620 CHIP PROVIDES FULL CONTROL OF MOTOR CURRENTS UP TO 2A, WITH ROTATION IN BOTH DIRECTIONS. HALL-EFFECT DEVICES INTERNAL TO THE MOTOR PROVIDE POSITION INFORMATION THROUGH A DECODER TO THREE TOTEM-POLE DRIVERS. COMPARING THE CHANGING VOLTAGE ACROSS Rs WITH THE ERROR AMPLIFIER OUTPUT HELPS KEEP THE CURRENT CONSTANT.
:I>
"a
nr"a-
!j
0
2 2
~
'"
+5V 10k(3pl.J
c:
t,.. 0en
APPLICATION NOTE
At this point the comparator resets the monostable, forcing 0 low and disabling the output stages. The motor current now circulates through one of the Schottky diodes and the conducting upper transistor because of the stored inductive energy, until the monostable off-time has elapsed (Figure 2). 0 then returns to the high state and the cycle is repeated.
The switching off-time is fixed, since it is determined by the user's choice of timing components RT and CT. Atthe start of the off-time, capacitor CT is charged to +5V, and the monostable outputs are held in the off state until this voltage decays exponentially to a level of 2V. Since resistor RT supplies the only path for the discharging current, it is possible to calculate the time required, lo··· in seconds:
exp { -loFF ) = ~
RTCT
5
or:
Vee TO 40V
...C· · · ·
rI STEADY:
· I
' '
----1
I I
.SDs
____ ,.. I
....................... STEADY
U-106
-!OFF = In (2/5) = -0.916
RTCT
loFF = 0.916RTCT When the 2 volt level is reached, the monostable is set
again, and the cycle repeats. The reference voltage, VREF, then, is the controlling voltage of what is in effect a transconductance amplifier of which the controlled output is the motor current through resistor Rs. To repeat, the circuit controls the peak value of the current. If the switching frequency is high (low current ripple), the assumption may be made that the average value of motor current, IM, is approximately equal to the peak, and so: VPEF = IMRs
GT = ~ = - 1- Siemens
VREF Rs
Aour
FROM GATING CIRCUIT
Bour
.............L ..- ..-.- .
CouT
EMITTERS 0.25
· · · · · · · ... 002 ON - - - --~ Os20FF
FIGURE 2. WHEN 002 IS ON, CURRENT FLOWS THROUGH 0A1 AND TWO MOTOR WINDINGS TO GROUND (DOTTED ARROWS). DURING THE TIME THAT 002 IS OFF, THE STORED ENERGY IN THE WINDING INDUCTANCE FLOWS THROUGH SCHOTTKY DIODE SDe, TRANSISTOR OA1. AND BACK THROUGH THE WINDINGS (DASHED ARROWS).
9-100
APPLICATION NOTE
The maximum value of VREF is limited to 0.5V by a zener diode (Figure 1 again). This value sets a limit to the maximum motor current as well, since:
Rs IMAX =
0.5 amperes
Consequently, the proper selection of Rs protects both the motor and the chip from excess current.
The motor is connected to the chip's thmP. outputs AouT, BouT, and CouT. The motor windings are Y-connected, and the driver energizes two phases at a time, the third one being off. Thus each driver output will be in one of three states: high (Vee), off (high impedance), or low (OV), generating six possible combinations (Table 1).
Table 1. Terminal Conditions for Different Driver Output States
OUTPUT TERMINAL TERMINAL TERMINAL
STATE
A
B
c
ABZ
High
Low
High Z
AZC
High
High Z
Low
ZBC
High Z
High
Low
ABZ
Low
High
High Z
AZC
Low
High Z
High
ZBC
High Z
Low
High
SIX STATES
In each of the six possible states, one of the upper transistors is on, together with one of the bottom transistors. In any of the states, it is the bottom transistor that controls switching, while the upper device remains conducting. For example, in state ABZ, current flows continually through upper transistor QA,, but switches between lower transistor Q 82 and Schottky diode SDa (Figure 2 again). This switching action results in low current ripple through the motor and is known as two-quadrant operation, in which the power supply current flows only in one direction, namely, into the driver (Figure 3). One advantage of this unidirectionality is that a shunt regulator is not necessary to prevent an overvoltage at the Vee bus during motor deceleration.
A more significant advantage is that it results in the least current ripple for a given switching rate. More precisely, the current waveform's form factor (the ratio of its rms to its average value) is closer to unity. Since the amount of 12R heating depends on the rms value of I, whereas torque depends on the average value, a form factor approaching unity results in greater motor efficiency.
The current reference voltage VREF at the inverting input of the chip's comparator depends on the output voltage, VouT, of the error amplifier. The relationship between the two is:
U-106
VREF_- V-ouT5- -1
The offset of 1V between VoUT and the 5:1 voltage divider ensures that the error amplifier can always achieve zero current at the motor. The amplifier itself has a high gain of 80dB minimum, an f, of 0.8MHz; and is internally compensated for stable operation. In a feedback speed control application, even with a reduction in gain of 14dB due to the 5:1 resistive attenuator between the amplifier and the comparator, there is still a minimum DC gain of 66dB, which is more than adequate for most requirements. The same consideration applies to the 1V offset, which is overshadowed by the high-gain loop as well.
MOTOR CURRENT/ VOLTAGE
IPEAK
ITURN-OFF
VREF
VOLTAGE AT ISENSE
PIN
FIGURE 3. THE CHIP'S SWITCHING CIRCUIT CONTROLS MOTOR CURRENT ON A PULSE-BY-PULSE BASIS. WHEN THE BOTTOM TRANSISTOR OF AN OUTPUT STAGE IS ON, THE CURRENT AT FIRST RISES RAPIDLY AND THEN DECAYS SLOWLY AS IT CIRCULATES THROUGH THE TRANSISTOR'S ASSOCIATED DIODE. THE FORM FACTOR OF THE WAVEFORM IS THEREFORE CLOSE TO UNITY, SO THAT HEATING OF THE COILS IS REDUCED.
The chip also includes two protection circuits to help make it more reliable. The under-voltage lockout prevents the output stages from being energized unless the supply voltage can provide sufficient base current to the drive transistors. The maximum Vee start-up threshold is set at 8V and has a built-in hysteresis of 0.5V. A thermal shutdown circuit affords protection against excessive junction temperatures. This circuit disables the drive transistors when the chip's temperature is between 150°C and 180°C. When the temperature returns to a safe value, normal operation is automatically restored. When the power source for a motor is DC, a commutator is needed to, in a sense, alternate the power applied to the windings. A brushless DC motor uses an external power commutator. As a rule, however, the motor has an electronic device internal to it that generates information relative to angular position for use in controlling the commutator.
9-101
APPLICATION NOTE
CONTROLLING BRUSHLESS MOTORS TO 2A
The control chip was designed to drive any three-phase brushless DC motor of up to 2A and is particularly suited for motors with integral Hall-effect devices. HA, He, and He (Figure 1 again) are TTL-compatible inputs that, together with the Forward-Reverse input (FWD/REV), determinethe output states (Table 2).
The commutation logic built into the UC3620 is intended for use with motors with 120 electrical degree Hall codes. Motors that use the alternative 60 electrical degree code can be easily accomodated with the addition of an inverter to reverse polarity of one of the Hall signals.
When used as described, the device operates in a current feedback mode and acts as a current controller, or rather as a transconductance amplifier. This closed-loop circuit can be made part of another feedback loop to control the motor speed. Controlled speed loops are of interest in many applications, some of which require a very high degree of control accuracy. For example, a crystalreferenced phase-locked loop is needed to control the spindle speed of magnetic disk drives.
Table 2. Hall Device Logic Coding
HALL DEVICE INPUTS
HA
He
He
FORWARD/ REVERSE LINE
DRIVER OUTPUT
1
0
1
1
ABZ
1
0
0
1
1
1
0
1
AZC ZBC-
0
1
0
1
ABZ
0
1
1
1
AZC
0
0
1
1
ZBC
Note: A change of state in the Forward/Reverse line inverts the output states, thus reversing the direction.
U-106
Unitrode Integrated Circuits Corporation
7 Continental Boulevard.· P.O. Box 399 ·Merrimack, New Hampshire· 03054-0399
Telephone 603-424-2410 · FAX 603-424-3460
9-102
Ln.:::::n:J INTEGIRATED CIRCUITS
-UNITRDDE
APPLICATION NOTE
U-107
NEW PULSE WIDTH MODULATOR CHIP CONTROLS 1 MHz SWITCHERS
ABSTRACT
Controversy prevails as to the benefits of pushing switched mode pulse width modulated power supplies higher and higher in frequency. Two facts are undisputed though: the industry is pushing switching frequencies up daily and no PWM control IC has been available to optimally control circuits running above several hundred kilohertz. A new IC, the UC3825, has been developed with the top end of the PWM frequency spectrum in mind to simplify high speed control problems. This chip, suitable to either voltage or current mode control, addresses the speed critical paramete?S that have been glossed over in the past: error amp bandwidth, output drive capability, oscillator frequency range, and propagation delay. A one megahertz, 50 watt supply has been built to demonstrate the chip.
PWM CONTROLLER REVIEW
Briefly reviewing popular control IC's on the market today should serve to illustrate one source ofthe headaches belonging to designers of high frequency switching power supplies. The snaggle-toothed appearance of the table illustrates the fact that high speed parameters have generally been ignored. The entries in this table represent the tried and true first and second generation standbys (1524, 1525, 494), dedicated off line control (1840), and current mode (1846). All these architectural approaches have certainly proven sufficient for numerous converter designs, but all lack the processing speed required to keep track of a 1 MHz switcher, or even 200 kHz for that matter. Many specifications in the table are missing completely, some are only typical, and the few guaranteed limits leave much room for improvement.
Of prime importance here is the delay time between fault detection and turning off the power switch - the speed critical path. When a fault occurs, either the on chip over-current sense section or an off chip fault detector plus the shutdown section of the chip must
work fast enough to turn off the power switch before destructive current levels introduce an automatic (and permanent) power down feature to the supply. This feature, of course, is manifested in blown power devices. The problem is aggravated at the onset of core saturation, since switch currents then rise at much faster rates.
Also important is the drive capability of the output stage of the control chip chosen. Rise and fall times must be consistent with switching speeds or else an output buffer will have to be added. This, of course, adds delay to the speed critical path placing tighter demands on the delays through the chip or forcing the designer to over-specify the power elements to insure fault survival.Over-specifying, however, adds cost, weight and volume as transistors, heat-sinks, and transformers are beefed-up. These consequences are in direct opposition to the very motives for going to higher frequencies in the first place - reduced volume and lower cost.
On-chip error amplifiers have also been a design obstacle in the past. Why build a high frequency switcher and then over compensate the loop due to lack of error amp bandwidth? Designers have been forced to conser-
SPEED COMPARISON OF PWM CONTROLLER IC'S
563524 UC3524A UC3525A TL494 UC3840 UC3846
SHUTDOWN DELAY (ns)
TYP MAX
-
-
200
-
200 500
-
-
-
-
300 600
OVER-CURRENT SENSE DELAY (ns)
TYP
MAX
-
-
600
-
-
-
-
-
200
400
200
500
ERROR AMP BANDWIDTH
(MHz)
TYP MIN
3
-
3
-
2
1
0.8
-
2
1
1
0.7
ERROR AMP SLEW RATE
(V/ s)
TYP MIN
-
-
-
-
-
-
-
-
0.8
-
-
-
OOTPUT RISE/FALL TIME
(ns)
TYP MAX
200
-
200
-
100 600
200 400
-
-
50
300
UC3825
50
80
50
80
5.5
3
12
6
30
60
9-103
APPLICATION NOTE
U-107
vatively use the bandwidth available simply due to a lack of guaranteed specifications in many cases. Also, some characteristics which would prove useful haven't been specified at all. Siew rate is such a specification that has great bearing on the large signal response ofthe supply.
By comparison, the 3825 specifically addresses the speed critical parameters. Maximum propagation delays of 80 ns nearly belong in the "order of magnitude" improvement catagory. Slicing delays yielded a hefty output stage capable of 1.5 Amp peak currents. The guaranteed rise time is, in fact, more a function ofinternal slew rates than external loading in the 1000 pF range. The error amp guaranteed to 3 MHz and 6 V/µs promises ease of use when controlling wide-band loops.
UC3825 BLOCK DIAGRAM
The design philosophy for the 3825 was to build a chip faster than any other available and tailor it to fit neatly into high frequency converter designs. It includes a dual totem-pole output stage capable of driving most power mosfet gates stand-alone, and the versatility to be useful for DC to DC, off-line, bridge, flyback, push-pull, and even resonant mode converter topologies. The member of a family covering the conventional temperature ranges, the UC3825 is specified for zero to 70 degrees centigrade while the UC2825 spans -25 to 85, and the UC1825, -55 to 125.
The block diagram of the 3825 (figure 1) is architec-
turally similar in many respects to a number ofprevious PWM controllers. It includes an oscillator, undervoltage-lock-out circuit, trimmed bandgap voltage reference, wideband error amplifier, PWM comparator, PWM latch, toggle flip-flop, soft start section, comparators for over-current sensing and reinitializing soft start, and dual totem-pole outputs. The input to the PWM comparator is brought out to a separate pin so that it can be connected either to the timing capacitor for conventional PWM designs or a current sensing network for current mode control schemes.
In normal operation, the oscillator establishes a fixed clock frequency issuing blanking pulses to terminate one period and begin the next. These pulses serve to reset the PWM comparator while blanking the outputs off. After the blanking pulse, one output turns on until the ramp input (level shifted 1.25 Volts) exceeds the error amp output voltage. This sets the PWM latch which turns the output off and triggers the toggle flipflop, selecting the other output for the next period.
THE SPEED CRITICAL PATH
The blocks that set the 3825 aside as the controller best suited for frequencies over several hundred kilohertz are those in the speed critical path (high-lighted blocks in figure 1.): the PWM comparator and current limit comparator in the front end; the PWM latch and associated internal logic; and the ouput stage. Signal
FIGURE!. UC3825 BLOCK DIAGRAM. BOLDFACE INDICATES SPEED CRITICAL PATH.
ERROR AMP SOFT START
GND~
"OUTPUT INHIBIT"
_ _ _ _ _ _ _ _ _ _ _ ~~~1--.__.__4V
---116 ~~~
9-104
APPLICATION NOTE
U-107
propagation through these subcircuits makes or breaks a design during a fault condition. In the 3825, the propagation delay from either the Ramp input or the Current-limit sense input to the output pins is typically 50ns, very much faster than any chip available today.
Comparators
The PWM comparator is basically an npn differential pair with an emitter follower output (figure 2a). The pair is biased so that the output swing is one Vbe. This guarantees none of the transistors in the comparator will saturate while providing output voltage levels compatible with the internal logic. In order to assure that the input common mode range of the comparator is not exceeded (the range of an npn input pair cannot go below approximately one Volt), a 1.25 Volt level shift is included between the non-inverting input of the comparator and the input pin of the chip. This allows the ramp input to swing from zero to approximately three Volts. The inverting input is tied directly to the output of the error amplifier.
The benefit of this approach is ease of use. both in current mode and conventionalPWM applications. For the older PWM circuit approach, the ramp input pin can be tied directly to the oscillator Ct pin while current mode users can simply tie a ground referenced current sense network directly to the Ramp pin.
The current limit comparator is very similar in design tothe PWM comparator. Itsinvertmginput is referenced internally to a one Volt level derived from the 5.1 Volt reference allowing the non-inverting input to be brought directly to the current limit pin. Functionally, when a
= VREF 5.!V
fault causes the Current-limit pin to exceed one Volt, it acts just like the PWM comparator, setting the PWM latchandcausingtheoutputstoremainofffortheduration of the clock cycle.
The current-limit comparator can also be combined with the 3825 outputs and a few external components to form a constant volt-second product clamp (figure 2b). This clamp is useful in current mode systems to prevent core saturation during load transients. When either output turns on (goes high), capacitor, C, is charged from Vin through resistor, R. Normal circuit operation would turn off the outputs causing C to be discharged before it reaches one Volt. If, however, it does reach one Volt, the current-limit comparator terminates the output pulse. Since the charge rate is proportional to Vin (assuming Vin is much greater than one Volt), then a constant Volt-second product clamp of one Volt times RC is achieved.
Logic
All of the speed critical logic, including the PWM latch, the toggle flip-flop, and various gates are a cross · between emitter coupled logic and emitter function logic. In either case, their speed relies on emitter coupled pairs and emitter follower buffers biased to insure that no transistor saturates. Although two OR's, a NOR and the PWM latch are directly in the critical path between the input comparators and the output drivers, they account for only twenty percent of the total delay, the remainder being shared between the comparators and the output stage.
_fl_
l.25V-=..
I
RAMP INPUT
R
_fl_
--------COMPARATOR OUTPUT
t - - - - - - - - - - - - - TO ERROR AMP OUTPUT
VeE
fr
3
FIGURE 2a. PWM COMPARATOR SCHEMATIC.
9-105
APPLICATION NOTE
R
UC382!1
luM COMP
U-107
lV
"AORB"
-
"AORB" lV Vp1N9
n
I
I
Vi
-
-
I I
I
I
[/1
MAXIMUM VOLT-SECOND PRODUCT= RC X lV
FIGURE 2b. CONSTANT VOLT-SECOND PRODUCT CLAMP IMPLEMENTED USING THE CURRENT LIMIT COMPARATOR.
Outputs
Speed from one pin to another does little or no good unless the signal coming out ofthe chiphas the strength to do its job. The dual totem-pole drivers ofthe 3825 are capable of driving 1000 picofarads from one rail to the other in a mere 30 nanoseconds. In fact the peak current avilable is in excess of 1.5 Amps. This kind of brute strength is sufficient for driving a wide range of power ,mosfet's in a variety of applications.
Delays couid be inserted to guarantee zero cross conducted charge, but that would be contrary to the required propagation delays for high speed operation. The outputs have been adjusted to yield these rise and fall times at a penalty of only 20 nanocoulombs of cross conducted charge per transition. At a clockfrequency of 500 kHz, this only adds an additional 10 mA to the supply current.
Some older PWM controllers with totem-pole output stages are plagued with hefty amounts ofcross conducted charge during output transitions. This can
result i~ major self heating problems especially at
higher clock rates. The3825outputstage (figure3a) has been modeled after the successful designs ofthe UC3846 and UC3842. The differences are in bias values and the addition of Schottky diodes. This circuit guarantees the output transistors, Ql and Q2, are driven with complementary signals to keep cross conducted charge under control. This approach necessarily involves a compromise since speed is of the utmost concern.
Rather than dwell on cross conducted charge, which is measured with no load on the outputs, it is more appropriate to examine the performance with typical loads. The most anticipated load is a power mosfet. The impedence presented by the gate of the fet is application dependent, but is primarily capacitive. Therefore, consider the requirements of driving a capacitor with a square wave voltage. The charge required for one cycle is equal to the capacitance times the voltage. The average current taken from the supply is that charge times the switching frequency. This determines the power required from the supply to drive the cap. Since
the cap is an energy storage element, all the power
9-106
APPLICATION NOTE
U-107
-le
-----111 OUTPUT 14 (A OR B) Q2
FIGURE 3a. OUTPUT STAGE SIMPLIFIED SCHEMATIC.
taken from the supply is dissipated by the chip. An efficiency figure for the chip can be defined as the ratio of the theoretical power dissipation to the actual power dissipated by the chip. This can be determined for a given frequency and supply voltage by measuring the average supply current into the Ve pin (assuming the peak output voltage is approximately equal to the supply voltage). The figure of efficiency, then, is: (CVf)/Ic. The graph offigure 3b shows the 3825 optimized to drive capacitances above 200pF. Care should always be taken when driving high capacitive loads to make sure the maximum power dissipation level of the chip is not exceeded.
EFFICIENCY= ~~f (%)
100
FIGURE 3b
90
80
70
I= 1.0 MHz
Ve= 15V
60
50
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2 CL(nF)
Another side effect ofthe output stage should be considered. Any node in a circuit capable of driving large capacitances at these rates begins quickly to resemble an LC tank. Transmission lines, even one inch in length, can become troublesome. The trouble occurs when, on the falling edge at an output, the load rings and actually pulls the output pin below ground. For years IC manufacturers have been warning users not to allow certain pins to go below ground and the 3825 output pins carry the same warning. The collector of the pull down transistor becomes a parasitic npn emitter when pulled below the chip's substrate, which is grounded (figure 4). The collector, or collectors as the case is, are every other npn collector and pnp base on the chip. The ones that are closer to the parasitic emitter collect proportionally more current than ones further away. Physical size of the parasitic collectors also plays a similar role. The results of this phenomenon can range from nonobservable to severe. Resembling leakage current internally, reference voltages can be altered, oscillator frequency can jitter, or chip temperature can be elevated. Dummy collectors tied to ground are inserted into the 3825 chip which help to attenuate this problem but the designer still needs to be aware of it. The problem's potential is not a horror story, though. Among the easiest of solutions is some form of damping in the load circuit (for example ten ohms series resistance) and a good high speed diode, Schottky if possible, to clamp the output pin's negative going excursion.
9-107
APPLICATION NOTE
p
N PSUBSTRATE
N p
N
GROUND PIN
PARASITIC LATERAL NPN
TYPICALPNP
TYPICALNPN
U-107
p
OUTPUTNPN
FIGURE 4. PARASITIC NPN TURNS ON WHEN SUBSTRATE - EPI JUNCTION IS FORWARD BIASED.
IDGHSPEED COMPLEMENTARY BLOCKS
An integrated circuit controller with delays of 50ns through its speed critical path is certainly a leading candidate for high frequency switcher applications. There are a few blocks just off the race path that need also to be fast in order to fully qualify the chip for such applications. The oscillator and error amplifier are two such blocks.
Oscillator
From the users point of view, the oscillator looks identical to many that have gone before it (figure 5a). Composed of an all npn comparator, this oscillator has dual thresholds-the upper at 2.8 Volts and the lower at one Volt. Charging current forthe timing capacitor, Ct, is mirrored from the timing resistor, Rt. The Rt pin is held at a temperature stable 3 Volts. Temperature stability of the oscillator, then, is achieved by maintaining stable thresholds at the comparator. When Ct has charged to the upper threshold, Q3 turns on to sink a controlled current ofapproximately 10 mA. The effect of this action is that the discharge of Ct is done in an orderly manner allowing the comparator to reliably catch it when crossing the lower threshold. This also prevents Q3 from saturating, reducing delays in the oscillator and enabling it to operate at higher frequencies. The 3825 oscillatoris nominally specified at 400kHz with an initial guaranteed accuracy of 10%. Temperature stability is typically better than 5% while voltage stability (frequency shift over supply voltage) is 0.2%.
Oscillator dead time, which effects controller dynamic range, can typically be held to lOOns at lMHz, allowing 90% duty cycles.
In applications where two 3825's are used in close proximity and synchronization is desired (figure 5b), the oscillator in one chip can be disabled by tying Rt to the reference Voltage. That chip, then, must he clocked by joining the clock pins of both chips. Multiple 3825's also can be synchronized from a master 3825 or other external sync signal. The slave chips are programmed to run at a frequency somewhat lower than the master chip. The master then inserts a sync pulse forcing each slave's Ct over the top threshold and causing discharge action to occur. This way, each chip generates its own clock pulses synchronized to a master clock.
Error Amplifier
The 3825 error amplifier is a volt.age gain amp with premium bandwidth and slew rate. Again using only npn's in the signal path, a compensated unity gain bandwidth of 5.5 MHz is achieved. The simplified schematic (figure 6) shows the signal path of the amplifier. Note that while the compensation scheme is not extremely complex or brand new in nature, neither is it the simple dominant pole approach. Included are two zeros located beyond the unity gain frequency to enhance phase margin. One is created by a capacitor across the emitter degeneration resistors in the first stage and the second is formed by a resistor in series with the dominant pole capacitor.
9-108
APPLICATION NOTE _JLJl_
Rr 2.BV
FIGURE Sa. FIGURE Sb.
UC3825
U-107
I
2N2222
JL
I
SLAVE
_.,,,._43..,.__--IOr 0 (11---f-+--,
I - ~}L--~ 1 }--124
OTTHOER
-
-~V'---1~ SLAVES
24
470
LOCAL RAMP
..-"\.
LOCAL RAMP
.........-\..
FIGURES. OSCILLATOR SIMPLIFIED SCHEMATIC (a) AND TWO SYNCHRONIZATION METHODS (b).
9-109
APPLICATION NOTE
6.3V
U-107
~~N- 2 1 - - - - - - - + - - - - - - - '
5.lV
- - - + - - - + - - - 1 3 E/A
OUTPUT 200
FIGURE 6. SIMPLIFIED SCHEMATIC OF WIDE BAND ERROR AMPLIFIER SHOWING SOFT START CLAMP SCHEME.
By degenerating Gm, the emitter resistors allow an increased first stage bias current level. This contributes to a 12 V/µs typical slew rate. High slew rate, while desirable for good large signal transient response, is not enough to guarantee minimal response time. Often an amplifier may have high slew rates yet exhibit long delay times coming out of saturation when it has been driven to a rail. To defeat this problem, all critical nodes within the amp have been Schottky clamped.
GLUE BLOCKS
The remaining blocks, while not speed critical, mold the 3825 into a more complete PWM controller. The reference, a time proven design, is trimmed to guarantee 5.1 Volts at better than one percent tolerance. This voltage is then held over conditions of line, load, and temperature changes to a two percent total spread.
Soft-start is very simply implemented by a pnp clamp transistor merged into the output stage of the error amp (figure 6). During soft start, while the 9 µA current source is charging the external capacitance on pin 8, Q4 actively forces pin 3 to follow pin 8. In this manner a controlled slow start can be achieved for either voltage or current mode systems. When the error amp comes into regulation, Q4's emitter-base junction is reverse biased and offers no further interference to the normal operation of the amp.
In addition to slow starts, the soft-start pin can be used to other ends. Clamping the maximum voltage this pin is allowed to rise to will then effectively clamp the maximum swing of the error amplifier. In a conventional PWM scheme this results in a duty cycle clamp while in a current mode application, it establishes the maximum peak current level.
Fault conditions are sensed by the 3825 at pin 9 which is shared by the inputs of the current limit comparator and the shut down comparator. When this pin exceeds one Volt, the current limit comparator sets the PWM latch, terminating the output for the remainder of that cycle. As with normal operation, setting the PWM latch causes the toggle flip-flop to switch states. Ifthe pin is further raised to exceed 1.4 Volts, the shutdown comparator forces the soft-start pin to sink a guaranteed minimum of one milliampere rather than sourcing 9 microamperes. Thus the shut down comparator causes the soft start capacitor to be discharged rapidly. After the fault signal is removed the 3825 will then execute a normal soft-start sequence.
One method of combining current-limit and shutdown signals is shown in figure 7. Here, in a current mode control example, a current sense transformer is used to translate switch current to proper voltage analogs for optimal control at both the Ramp and Current-limit sense pins while the shut-down signal is inserted with a resistive summing technique.
9-110
APPLICATION NOTE
SHUT DOWN
U-107
!OK
1:50 lswtTcH 0-IOA
2200
lOOpF
100
I
220.Q
lK
50
}oopF
FIGURE 7. CURRENT LIMIT SENSE AND SHUT DOWN SIGNALS ARE COMBINED AT PIN 9 IN THIS CURRENT MODE EXAMPLE.
Starting the 3825 involves the Under-voltage lockout portion of the chip. This block acts like a comparator with it's inverting input biased to 9 Volts and having 0.8 Volts ofhysteresis. ITVcc is below the UVLO threshold, the reference generator and the internal bias are turned off, Keeping Ice at a typical 1.1 mA and the outputs in a high impedence state. When Vee exceeds the UVLO threshold, the reference is turned on and the chip comes alive. Bedlam is avoided, however, as a second comparator monitors the reference voltage and inhibits the outputs until the reference is high enough to ensure intelligent operation. This inhibit signal also holds the soft start pin at a low voltage. After the reference is sufficiently high, the chip begins a soft start sequence.
50 WATI' DC-DC PUSH-PULL CONVERTER
A 48 to 5 Volt, 50 Watt converter has been built as a test vehicle for the chip (U-110). Designed around a push pull, current mode controlled topology, the circuit runs from a 1.5 MHz clock. In the interest of simplicity, the ramp input and current limit pins were tied together
underutilizing the available dynamic range of the Ramp pin by a factor of 3. A ground plane, judicious bypass capacitors and tight layout technique yielded a circuit that could be easily interrogated without significant noise interference problems.
fu this simple application, the 3825 performs all the tasks required to regulate the 50 W power stage. The gate drive for the two power mosfets comes directly from the chip. Current loop slope compensation is resistively summed with the current sense signal at pin 7. Overall loop compensation is implemented with two resistors and a capacitor on the error amplifier. Taking advantage of the 1.5 MHz switching frequency and the wide bandwidth characteristics of the error amp, the control loop was compensated to zero dB at 300kHz.
CONCLUSION
Presenting an easy to use PWM architecture, the UC3825 possesses the necessary high speed characteristics to control switchers in the higher frequency ranges. This fills a void that has hindered high frequency applications in the past. A simple example running at 1.5 MHz points to a future of faster switching supplies.
Unitrode Integrated Circuits Corporation
7 Continental Boulevard. ·P.O. Box 399 ·Merrimack, New Hampshire· 03054-0399
Telephone 603-424-2410 · FAX 603-424-3460
9_111
n nINTEGRATED
~CIRCUITS
-UNITRDDE
APPLICATION NOTE
U-109
USING AN INTEGRATED CONTROLLER IN THE DESIGN OF MAG-AMP OUTPUT REGULATORS
By Robert A. Mammano, Unitrode IC Corp. Charles E. Mullett, Mullet Associates, Inc.
Magnetic amplifier technology dates back considerably further than transistors but its wide-spread use has been slow in developing. While many factors may have been responsible for this, at least one - the high cost of tape-wound magnetic cores - has been alleviated with significant recent price reductions and the introduction of less expensive materials. And now, another one - the problems in designing effective control loops utilizing mag amps as voltage regulators - has fallen with the introduction of an IC dedicated to mag amp control the UC1838.
While there are many types of power supply applications where mag amps may effectively be used, one of the most popular current uses is as a secondary regulator in multiple output power supplies configured as shown in Figure I. The problem with multiple outputs stems from the fact that the open-loop output impedance of each winding, rectifier, and filter is not zero. Thus, if one assumes that the overall feedback loop holds the output of Vo 1 constant, then increasing the loading on V01 will cause the other outputs to rise as the primary circuit compensates; similarly; increasing the loading on any of the other outputs will cause that output to droop as the feedback is not sensing those outputs. While these problems are minimized by closing the feedback loop on the highest power output, they aren't eliminated and auxiliary, or secondary regulators are the usual solution. A side benefit of secondary regulators, particularly as higher frequencies reduce the transformer turns, is to compensate for the fact that practical turns ratio may not match the ratio of output voltages. Clearly, adding any form of regulator in series with an output adds additional complexity and power loss. Mag amps are a hands down winner in both areas.
PRIMARY PWM
CONTROL
~ REG ~Vo2
~ REG ~V03 etc
Figure I. A typical multiple output power supply architecture with overall control from one output.
MAG AMP VOLTAGE REGULATORS
Although called a magnetic amplifier, this application really uses an inductive element as a controlled switch. A mag amp is a coil of wire wound on a core with a relatively square B-H characteristic. This gives the coil two operating modes: when unsaturated, the core causes the coil to act as a high inductance capable of supporting a large voltage with little or no current flow. When the core saturates, the impedance of the coil drops to near zero, allowing current to flow with negligible voltage drop. Thus a mag amp comes the closest yet to a true "ideal switch" with significant benefits to switching regulators.
Before discussing the details of mag amp design, there are a few overview statements to be made. First, this type of regulator is a pulse-width modulated down-switcher implemented with a magnetic switch rather than a transistor. It's a member of the buck regulator family and requires an output LC filter to convert its PWM output to DC. Instead of DC for an input, however, a mag amp works right off the rectangular waveform from the secondary winding of the power transformer. Its action is to delay the leading edge of this power pulse until the remainder of the pulse width is just that required to maintain the correct output voltage level. Like all buck regulators, it can only subtract from the incoming waveform, or, in other words, it can only lower the output voltage from what it would be with the regulator bypassed. As a leading-edge modulator, a mag amp is particularly beneficial in current mode regulated power supplied as it insures that no matter how the individual output loading varies, the maximum peak current, as seen in the primary, always occurs as the pulse is terminated.
MAG AMP OPERATION
Figure 2 shows a simplified schematic of a mag amp regulator and the corresponding waveforms. For this example, we will assume that Ns is a secondary winding driven from a square wave such that it provides a ± 10 volt waveform at v1· At time t = 0, V1 switches negative. Since the mag amp, LI, had been saturated, it had been delivering
+ lOV to v, prior tot = 0 (ignoring diode drops). If we
assume Ve = -6V, as defined by the control circuitry, when v1 goes to -lOV, the mag amp now has four volts across it and reset current from Ve flows through DI and the mag amp for the IOµS that V1 is negative. This net four volts for 10 µS drives the mag amp core out of saturation and resets it by an amount equal to 40V-µS.
9-112
APPLICATION NOTE
U-109
10
20 . .
@= 4V x 10µs = 40Vµs
® = 10V x 4µs = 40Vµs
Vo = V1nton = 10V x 6µ.S = 3VDC
T
20µ.S
Figure 2. A simplified mag amp regulator and characteristic waveforms.
When t = 10 µS and v, switches back to + lOV, the mag
amp now acts as an inductor and prevents current from flowing, holding v, at OV. This condition rema£,.~ until the voltage across the core - now 10 vo~ts - drives the core back into saturation. The important fact is that this takes the same 40 volt-µS that was put into the core during reset.
When the core saturates, its impedance drops to zero and v, is applied to v, delivering an output pulse but with the leading edge delayed by 4 µS.
Figure 3 shows the operation of the mag amp core as it switches from saturation (point 1) to reset (point 2) and back to saturation. The equations are given in cgs units as:
N = mag amp coil turns Ae = core cross-section area, cm' fe = core magnetic path length, cm B = flux density, gauss H = magnetizing force, oersteads
The significance of a mag amp is that reset is determined by
the core and number of turns and not by the load current.
Thus a few milliamps can control many amps and the total
power losses as a regulator are equal to the sum of the con-
trol energy, the core losses, and the winding l'R loss - each
term very close to zero relative to the output power.
r:-------- 1----&H------t '0
_TiI _J~TI--JL
&B I
_J~:
~
~) Vo· V1N(1 -
AT= NAe.68 x 10-8 V1N
le · 4.Hte 0.411'N
B
Figure 3. Operating on the B-H curve of the magnetic core.
Figure 4 shows how a mag amp interrelates in a two-output forward converter illustrating the contribution of each output to primary current. Also shown is the use of the UC1838 as the mag amp control element.
., _n
~___L
_
__In___L
..~f__1__L _ [r__1__L
Figure 4. Control waveforms for a typical two-output, secondary regulated, forward converter.
THE UC1838 MAG AMP .CONTROLLER
While bringing no major breakthroughs in either integrated circuit or power supply technology, the UC1838 provides a low-cost, easy-to-use, single-chip solution to mag amp control. The block diagrams of this device, as shown in Figure 5, includes three basic functions: 1. An independent, precise, 2.SV reference 2. 1\vo identical, high-gain operational amplifiers 3. A high-voltage PNP reset current driver.
4
4.5
,~
Figure 5. The block diagram of the UC1838 mag-amp control integrated circuit.
The reference is a common band-gap design, internally trimmed to 1%, and capable of operating with a supply voltage of 4.5 to 40 volts. The two op amps are identical with a structure as shown simplified in Figure 6. These amplifiers have PNP inputs for a common mode input range down to slightly below ground and have class A outputs with a 1.5 MA current sink pull down. The open loop voltage gain response, as shown in Figure 7, has a nominal 120 dB of gain at DC with a single pole roll-off to unity at 800 KHz. These amplifiers are unity-gain stable and have a slew rate of0.3 V/µS.
9-113
APPLICATION NOTE
Reset Driver DC Transfer Function
U-109
Figure 6. Simplified schematic of each of the operational amplifiers contained within the UC1838.
Amplifier Open-Loop Response
120
~ 100
I 0 80
".z... 60
<(
""'z 40
""'' 20
180
225 ~
~ 270
315 I
w
<(
360
I
~
0.1
10 100 lk lOk lM lM
SIGNAL FREQUENCY - (Hz)
Figure 7. Open-loop gain and phase response for the UC1838 op amps.
Two op amps are included to provide several design options. For example, if one is used to close the voltage feedback loop, the other could be dedicated to some protective function such as current limiting or over-voltage shutdown. Alternatively, if greater loop gain is required, the two amplifiers could be cascaded.
The PNP output driver can deliver up to 100 MA of reset current with a collector voltage swing of as much as 80 volts negative (within the limits of package power dissipation). Remembering that the mag amp will block more voltseconds with greater reset, pulling the input of the driver low will attempt to reduce the output voltage of the regulator. Thus, there are two inputs, diode "OR" ed to turn on the driver, turning off the supply output.
With internal emitter degeneration, this reset driver operates as a transconductance amplifier providing a reset current as a function of input voltage as shown in Figure 8. The frequency response of this circuit is plotted in Figure 9 showing flat performance out to one megahertz.
-2
-3
-4
-5
INPUT VOLTAGE - Volts (W.R_T VM)
Figure 8. Transconductance characteristics of the UC1838 reset current generator.
Reset Driver Response
rn
I 0 -10
"
z
'1
"z -20
~
Phase Gain
180
225
I270
31'.J I
~ <(
360 I ~
-30
lk
lOk
lOOk
lM
lOM
SIGNAL FREQUENCY - (Hz)
Figure 9. Reset driver frequency response.
Current limiting to protect the output driver is achieved by means of the 3.5 V Zener clamp (which is temperature compensated to match two VBE's) in conjunction with the 200 emitter resistor. It should be noted that thermal shutdown is purposely not included since protecting the driver by turning it off would mean losing control of the power supply output. Pin 11 - the emitter of the driver - can be connected to any convenient voltage source from 5VDC to the level used to supply the op amps. Note that the op amp supply must be at least 2 volts higher than the DC level on the inputs, a point to remember when selecting a location for current sensing. One possible configuration for a complete secondary regulator with shutdown control is shown in Figure 10.
9-114
APPLICATION NOTE
lOOµH
+12V. 4A OUTPUT WITH SWITCHING FREQUENCY " 50kHz
U-109
15V AUXILIARY SUPPLY
9 lk 1000
2.4k
Figure 10. Using the UC1838 to provide both voltage control and over-current shutdown in a typical 12V, 4A regulator.
MAG AMP DESIGN PRINCIPLES
One of the first tasks in a mag amp design is the selection of a core material. Tuchnology enhancements in .the field of magnetic materials have given the designer many choices while at the same time, have reduced the costs of what might have been ruled out as too expensive in the past. A comparison of several possible materials is given in Figure 11. Some considerations affecting the choices could be:
1. A lower Bmax requires more turns - less important at higher frequencies since fewer turns are required.
2. Higher squareness ratios make better switches 3. Higher IM requires more power from the control circuit 4. Ferrites are still the least expensive 5. Less is required of the mag amp if it only has to regulate
and not shut down the output completely
MATERIALS
Example: Similar Toroids. 1" o.o.. 0.75"' 1.0., 0.25" High, 25KHz, 20V.
Trade Name
Bmax Core Loss Squareness Tums iM
composition ~ @Bmax ~ ~ -®.
Sq. Permalloy eo
79%Ni, 17%Fe
1.2W
0.9
19 0.04
Supermalloy
78%Ni, 17%Fe,
5%Mo
1.0W
0.55
19 0.03
Orthonol
50%Ni
14
7.2W
0.97
10 0.39
50%Fe
Sq. Motglaas
Fe,B
16
7.BW
0.5
0.06
Power Ferrites
Mn,Zn
4.7
1.BW
0.4
11 0.1
Sq.Ferrite (Fair-Rite #83)
Mn
3.9
2.BW
0.9
13 0.4
Figure 11. A comparison of several types of core materials available for mag amp usage.
In addition to selecting the core material, there are additional requirements to define, such as:
1. Regulator output voltage 2. Maximum output current 3. Input voltage waveform including limits for both voltage
amplitude and pulse width 4. The maximum volt-seconds - called the "withstand
area;· A - which the mag amp will be expected to support
With these basic facts, a designer can proceed as follows:
1. Select wire size based on output current. 400 amp/cm' is a common design rule.
2. Determine core size based upon the area product:
AwAe = Ax X A X 10' where
AB x K
Aw = Window area, cm' Ae = Effective core area, cm' Ax = Wire area, (one conductor) cm' A = Required withstand area, V-sec AB = Flux excursion, gauss K = Fill factors "" 0.1 to 0.3
3. Calculate number of turns from
N=AxlO'
AB x Ae
4. Estimate control current from
le .. ~ where 0.4 7r N
le = core path length, cm
H is taken from manufacturer's curves. Note that it increases with frequency. 5. Check the temperature rise by calculating the sum of the core loss and winding loss and using
AT .,, __P_wa_t_ts_0_8·_
x 444°C
A (surface) cm'
6. Once the mag amp is defined, it can be used in the power supply to verify le and to determine the modulator gain so that the control requirements may be determined.
9-115
APPLICATION NOTE
U-109
COMPENSATING THE MAG AMP CONTROL LOOP
The mag amp output regulator is a buck-derived topology, and behaves exactly the same way with a simple exception. Its transfer function contains a delay function which results in additional phase delay which is proportional to frequency.
Figure 12 shows the entire regulator circuit, with the modulator, filter, and amplifier blocks identified. The amplifier, with its lead-lag network, is composed of the op-amp plus Rl, R2, R3, Cl, C2, and C3. The modulator, for the purpose of this discussion, includes the mag amp, the two rectifier diodes, plus the reset driver circuit which is composed of Dl, Ql, and R7.
r--------~~~~~,_;;;.--------1
II
MA
F=='
D1
L - 100,.H
-
R4 R5
'~J
I I I R6
I
- I ___:__j
Figure 12. Schematic diagram of a typical regulator control loop.
The basic filter components are the output inductor (L) and filter capacitor (C4) and their parasitic resistances R4 and RS. For this discussion, a 20 KHz, 10 Volt, 10 Amp regulator is used. The output inductor has been chosen to be 100 JLH, the capacitor is 1000 JLF and each has .01 ohms of parasitic resistance. The load resistor (R6) of 1 ohm is included since it determines the damping of the filter.
The purpose of proper design of the control loop is to provide good regulation of the output voltage, not only from a de standpoint, but in the transient case as well. This requires that the loop have adequate gain over as wide a bandwidth as practical, within reasonable economic constraints. These are the same objectives we find in all regulator designs, and the approach is also the same.
0
ID "C 3;
w -20
0 :::>
zt:: -40 ~
:ii
-60 1
GAIN PHASE
[fl aw : ----- 0 ~
3; -180 ~
J: 0..
10 100 1000 10K 100K 1M FREQUENCY, Hz
Figure 13. Output filter response.
Tu include the effects of the mag amp modulator, we must consider the additional phase shift inherent in its transfer function. This phase delay has two causes:
1. The output is produced after the reset is accomplished. We apply the reset during the "backswing" of the secondary voltage, and then the leading edge of the power pulse is delayed in accordance with the amount of reset which was applied.
2. The application of reset to the core is a function of the impedance of the reset circuit. In simple terms, the core has inductance during reset which, when combined with the impedance of the reset circuit, exhibits an L-R time constant. This contributes to a delay in the control function.
The sum of these two effects can be expressed as:
0m =-(20 +a)~ , where
Ws
0 M = Modulator phase shift D = Duty ratio of the "off" time a = resetting impedance factor: = 0 for a current
source; = 1 when resetting from a low-impedance source; and somewhere in between for an imperfect current source. ws = 2 'If fs, where fs = the switching frequency.
When the unity-gain crossover frequency is placed at or above a significant fraction (lOOfo) of the switching frequency, the resultant phase shift should not be neglected. Figure 14 illustrates this point. With a = 0, we insert no phase delay, and with a = 1 we insert maximum phase delay, which results from resetting from a voltage source (low impedance). The phase delay is minimized in the UC1838 by using a collector output to reset the mag amp.
O ~--~--~---~FU~L-L~W.~111.-!/E~
D = .55
A straightforward method is to begin with the magnitude and phase response of the filter and modulator, usually by examining its Bode plot. Then we can choose a desired crossover frequency (the frequency at which the magnitude of the transfer function will cross unity gain), and design the amplifier network to provide adequate phase margin for stable operation.
Figure 13 shows a straight-line approximation of the filter response, ig!!_oring parasitics. Note that the corner frequency is 11(2 'If '\/ LC), or 316 Hz, and that the magnitude of the response "rolls off" at the slope of -40 dB per decade above the. corner frequency. Note also that the phase lag asymptomatically approaches 180 degrees above the corner frequency.
-1ao· 1-----+-------1---4---"'"---I
0
.1
.2
.3
.4
FREQUENCY, JE.._
ws Figure 14. Mag amp phase shift.
It is difficult to include this delay function in the transfer function of the filter and modulator. A simple _way to handle the problem is to calculate the Bode plot of the
9-116
APPLICATION NOTE
U-109
filter/modulator transfer function without the delay function, and then modify the phase plot according to the modulator's phase shift.
Using this technique, the Bode plot for the modulator and output filter of this example has been calculated assuming a = 0.2 and D = 0.6 yielding the graph of Figure 15.
i]r-······---~-H~~~----~m ! r32
f al 24
MAGNITUDE ___/\
mm
1+90 J en
:
<( -16 ---- ---------------- ----- --- -180 <(
~~
f
-32
-270
I 1\1\ll
10
100
1K
10K
FREQUENCY, Hz
Figure 15. Filter-modulator response including the effects of mag amp phase delay.
If we now close the loop with an inverting error amplifier, introducing another 180 degrees of phase shift, and cross the unity gain axis above the corner frequency, we will have built an oscillator - unity gain and 360 degrees of phase shift.
An alternative, of course, is to close the loop in such a way as to cross the unity-gain axis at some frequency well below the corner frequency of the filter, before its phase lag has come into play. This is called "dominant pole" compensation. It will result in a stable system, but the transient response (the settling time after an abrupt change in the input or load) will be quite slow.
The amplifier network included in Figure 12 allows us to do a much better job, by adding a few inexpensive passive parts. It has the simplified.response shown in Figure 16. The phase shift is shown without the lag of lSO degrees inherent in the inversion. This is a legitimate simplification, provided that we use an overall lag of lSO degrees (not 360 degrees) as our criterion for loop oscillation.
DESIGN EXAMPLE
An SV, SA Output Derived from a 12V Output 20 KHz Push-Pull Converter
This example uses the UC1S3S to control a full-wave mag amp output regulator, with independent shutdown current limiting. Capsule specifications are as follows:
INPUT. PWM quasi-square wave which, without the magamp, produces 12 Vdc.
OUTPUT: 8.0 Vdc ±I% at load currents from 1 to SA.
OUTPUT RIPPLE: Less than 50 mV p-p.
TRANSIENT RESPONSE: For load changes of 6 to S and S to 6A, peak excursion of the output shall be less than ±20Jo and settle to within 1OJo of the final value within 500 /LS.
OUTPUT PROTECTION: The SV output shall have independent current limiting, so as not to shut down the 12V output when the SV output is overloaded or shortcircuited. It shall recover from the overload automatically when the overload is removed.
Figure 17 shows the proposed circuit approach. A current transformer has been used to sense the overload, simply to illustrate this approach. A simple series resistor of perhaps .01 or .02 ohms would do as well here, but the current transformer is preferred for high-current outputs.
-"Ls- F='
33TON 52002-D
II
R4 l=70µH@8A .012
.RS
02
5~~0 i-
Vour BV@BA
R6 HOO
R3 1.3K C3 .o1
4.55K
R1 10K
T1 1;100
.a,l,
ui
,_0
:::> +40
z +20
~
~
-20
_ _ _ _ _ _ _ _ _ _!_ ________ +90 ff1
PHASE
aw :
-90 IB 0 ui ~ I "-
f,
fc
t,
Figure 16. Compensated amplifier frequency and phase response.
The important point is that this circuit provides a phase "bump" - it can have nearly 90° of phase boost at a
chosen frequency, if we provide enough separation between the corner frequencies, fl and f2. This benefit is not free, however. As we ask for more boost (by increasing the separation between fl and f2) we demand more gain-bandwidth of the amplifier.
Figure 17. Control and current limiting for a SV, S amp, 20 KHz push-pull converter.
DESIGN APPROACH
With the input waveform already set by the converter design, and the above specifications to define the desired output, the new output circuit will be approached as follows: I. Draw the preliminary schematic. 2. Design the mag amp. 3. Design the feedback loop. 4. Design the current limiter. 5. Build the breadboard and test it.
PRELIMINARY SCHEMATIC
Figure 17 shows the preliminary circuit diagram. Parasitic resistance of the output filter inductor and capacitor (R4 and R5) are shown, along with the expected feedback com-
9-117
APPLICATION NOTE
U-109
pensation elements (RI, R2, R3, Cl, C2, and C3). These will be referenced in the mag amp design.
MAG AMP DESIGN
The information necessary to the design is as follows:
1. Input pulse: nominally 32V x 9 µS, = 2SS volt-microseconds.
2. Duty ratio of the "off" time: nominally (25 - 9 µS)/ 25 JLS = .76, since the frequency at the output is 40 KHz.
3. Output current: SA. 4. Regulation only, or complete shutdown required?
Shutdown.
Comments on the output filter
Design of the output filter is not complicated by the presence of the mag amp. In this case, it was designed with output ripple specs, and capacitor ripple current in mind. Although this design has adequate inductance for continuous conduction of the inductor at minimum load, this is not mandatory. The mag amp, when designed for shutdown, is capable of regulating the output in the discontinuous conduction mode.
Mag amp core selection
1. Wire size: The current waveform in the magamp can be analyzed as follows: During the power pulse, the current is approximately SA (inacciµate only due to the "tilt" of the top of the current pulse); the duty ratio of this pulse is half the ratio of the output voltage to the pulse height, or .5 x S/30 = .12. During the dead time between pulses, the inductor current is shared by the rectifier diodes and the "catch" diode. The duty ratio is I - 2 x .12 = .76, and the current during this interval is S/3A. During the remaining interval the current is zero, because the entire SA is flowing in the other mag amp.
The rms value of the current can now be computed:
Irms = .../s2 x .12 + (S/3)' x .76 = 3.62 A.
At 400 Amp/cm', a wire area of approx..0091 cm' is required. 16 gauge wire has an area of .0131 and is chosen for the mag amp.
2. Core selection: An appropriate material at this frequency is square-loop SOOJo nickel (Square Permalloy 80 or eq.) with a tape thickness of 1 mil. The saturation flux
density if this material is 7000 gauss. A fill factor of 0.2 is chosen for the winding. The required area product is:
AwAe = Ax x A x lj)' = .0131 x 288 x 10-' x 10' = .135 cm'
4BxK
2x7000x0.2
which can be divided by 5.07 x l~ cm'/C.M. in order
to refer to core manufacturer's tables.
An appropriate core is the Magnetics 52002-10, which (with 1 mil tape thickness) has an area product of .026 x 106 C.M. cm'. The core area of this core is 0.076 cm'.
3. Determine the number of turns: The mag amp must be able to withstand the entire area of the input pulse, which is 28S volt-microseconds.
N = A x 10' = 2S8 x 1~ x 10' = 27 turns.
2 x Bm x Ac 2 x 7000 x .076
Allowing an extra 200Jo for variations in Bm, pulse dimensions, etc., the winding is chosen to be 33 turns.
FEEDBACK LOOP DESIGN
The key steps in the design of the feedback loop are as follows: 1. Determine the modulator's de transfer function. 2. Plot the transfer function of the modulator and filter,
to determine the gain and phase boost required of the feedback amplifier. 3. Design the feedback amplifier. 4. Plot the results in the form of the closed-loop transfer function.
Plotting the modulator's transfer function can be easily done experimentally with the UC183S by opening the feedback loop at the input to the Reset Driver and driving this point (pin 15 or 16) directly. For interest, the reset current is also measured with the help of a 1 ohm resistor placed in series with the emitter of the reset transistor (pin 11 of the UC183S). The results are shown in Figure 18, with load resistors of 1 ohm and 10 ohms.
2.4
2.3
2.2
2.1
2.0
1.9
1.8 '---'-----'--'-----'--~~~~-'--~
9
4
REGUUITOR Vour
Figure 18. DC gain of the mag amp modulator.
Note that the results are practically the same at both load values. This is to be expected, since the output inductor is still in the continuous conduction mode at the minimum load.
In the region of the d.esired output (SV and SA load), the modulator de gain is approximately 12.5, or 22 dR In addition to the phase shift of the filter, the modulator con-
tributes additional phase lag! Assuming that we will not.
attempt to cross unity-gain at a frequency above one-tenth the switching frequency, we can neglect the phase lag due to the impedance of the core and the reset circuit. But we cannot neglect the phase lag resulting from the delay between the time of resetting the core and the time when the core delivers its output:
0M = 2D ~ , where ws
0M = Modulator phase shift D = Duty ratio of the "off'' time (.76 in this example) ws = 2 D fa, where fa = the switching frequency (40 KHz)
We can use any one of the common circuit analysis programs for analyzing the filter-modulator, neglecting the modulator phase lag when running the program, and then adding it later. Or, the lag may be included in a more sophisticated analysis program. The resultant response prediction is shown in Figure 19.
9-118
APPLICATION NOTE
U-109
rg
ui
24 MAGNITUDE
16 B
PHASE
:,0_:>. 0
z ~
::;;
-B -16 -24
-32
+90
"'w
aw :
"' - 90
w 0
ui
". -180 ':aI.:
-270
10
100
1000
10K
FREQUENCY. Hz
Figure 19. Calculated response plot for the modulator and filter.
Note the shape of the phase response. In the region of 2 KHz the phase lag is decreasing, due to the ESR of the output capacitor. Above 6 KHz the modulator's phase lag becomes important, and the phase lag increases.
Choosing one-tenth the switching frequency for the unitygain crossover frequency (4 KHz), we can determine the desired gain and phase boost of the feedback amplifier. At 4 KHz, the gain of the modulator is -15. dB (a factor of .179) and the phase shift is -135 degrees. It is generally recommended that there be at least 60 degrees of phase margin at the crossover frequency. This will require reduction of the phase lag to -120 degrees.
In accordance with the design procedure of Venable', the required boost is:
Be = M - P - 90, where
M = desired phase margin, and P = filter & modulator
phase shift.
In this case, Be = 60 - (-135) -90 = 105 degrees. This is
comfortably within the theoretical limit of 180 degrees, inherent in the amplifier configuration shown in Figure 17. The gain required at the crossover frequency is the reciprocal
of the modulator's gain, or +15dB = a gain of 5.6.
Continuing with the procedure, we can now compute the
amplifier components:
K = (Tun [ (Bc/4) + 45) )' = 8.65
C2 = 1/(21r fG RI)
= .00071 µF
Cl = C2 (K-1)
= .0055 µ,F
R2 = -v'K/(2 1r f Cl) R3 = Rl/(K - 1) C3 = 1/(2 1r f VK R3)
= 21,485 ohms = 1,302 ohms = .01 µF
where f = crossover frequency in Hz, G = amplifier gain at crossover (expressed as a ratio, not as dB), and K is a factor which describes the required separation of double poles and zeroes to accomplish the desired phase boost. These frequencies are:
fl = f/VK (double zero), and f2 = fVK (double pole),
In this example, fl = 1361 Hz and f2 = 11.76 KHz. With this information at hand, it is wise to check the gain-bandwidth required of the feedback amplifier to see that the circuit's needs can be met with one of the amplifers in the UC1838. Knowing that the amplifier rolloff is 20 dB per
decade, we can simply calculate the required gain-bandwidth at f2 and see that it is well below the gain-bandwidth of the amplifier.
The gain at f2 is:
Gf, = VK G, and hence the required gain-bandwidth is:
GBW = VK G f2 = K G f, where G is the desired gain at
crossover.
In this example, GBW = 8.65 x 5.6 x 4000 = 194 KHz.
This is comfortably below the gain-bandwidth of the amplifier, which is 800 KHz.
For interest, the response of the amplifier is plotted in Figure 20. Note that the gain reaches a minimum at 1.3 KHz, and that the phase boost peaks at 4 KHz, as intended.
44
rg 36
uj
,0:_:>. 28 z 20
~
::;; 12
+90
"'w
0 aw:
"' - 90
w 0
ui
-180
."':aI.:
-270
100
1000
10K
FREQUENCY, Hz
Figure 20. Compensated amplifier response.
Figure 21 shows the overall response, combining the filter-modulator's response with that of the feedback amplifier. Note the 60 degrees of phase margin at the crossover frequency.
70
rg 60
tzwi 50
::>
0aw: "-
+99
"' 0 aww:
"' - 90
w 0
uj
-180 ~
:aI.: -270
100
1000
10K
FREQUENCY, Hz
Figure 21. Total loop response with 60 degrees of phase margin at crossover.
CURRENT LIMITER DESIGN
Although a series sensing resistor might have been acceptable at this level of output current, a current transformer, Tl in Figure 17, has been used for the sake of interest. The secondary has 100 turns, and each primary winding is simply one pass through the toroid.
The amplifier performs as an integrator rather than as a comparator, the form found in many primary current limiters of switched-mode controllers. This is not an arbitrary choice. Since the current pulse occurs during the time that the core is obviously not being reset, the circuit must have "memory" - it must apply a shutdown command to the reset transistor during the next reset interval. Although many sophisticated schemes can be devised, the integrator is attractive because of its simplicity.
9-119
APPLICATION NOTE
U-109
A diode is placed across the input resistor of the integrator, to force its output down quickly when receiving the narrow pulses which occur when the circuit is in current limit. The circuit of this example was developed experimentally. A future goal is to explore this in detail and develop a more rigorous approach. The performance of this circuit is illustrated. with waveform photos later in the paper.
BREADBOARD TEST RESULTS
Figure 22 shows the waveform of the input voltage which is applied to the mag amp core, and the current of the two mag amps combined (by placing a current probe on the return leg of the secondary of the converter's transformer). The lower two traces are expanded versions of the top ones, and one can see clearly the effect of the transformer's leakage inductance: the voltage pulse has a "dent" in it during the rise of the current in the mag amp.
Control loop transient response
To test the response of the regulator to step changes in load, an electronic load was square-wave modulated at 500 Hz, between the values of 6A and SA. The results are shown in Figure 24. The upper trace is the regulator's output voltage, showing peak excursions of less than 50 mV, and recovery time of .5 ms. The lower trace is the reset current, measured with a current probe at the collector of the reset transistor in the IC. .
1-
23-
Output transient response 6-8A Jl.ILOAD Top: Output voltage, 50mV x .5 ms/div. Bot: Reset current, 20mA X .5 ms/div.
(Measured at collector of UC1838 transistor)
Figure 24. Dynamic regulator response to step change in load between 6 and 8 amps.
I. Secondary voltage, 50V, 5 µs/div. 2. Current in return (center tap) of secondary. 5A, 5 µs/div. 3. Secondary voltage, 50V, I µs/div. 4. Current in return (center tap) of secondary. 5A, 5 µs/div.
Figure 22. Input voltage and current to the mag amp.
Also note the "backswing" at the end of each voltage pulse. This is the discharge of the energy stored in the saturated inductance of the mag amp core. Finally, note the rate of rise of the current pulse, which is determined by the saturated inductance of the mag amp, in series with the leakage inductance of the transformer.
Response of the current limiter
To illustrate the dynamic operation of the limiter, the current limit was set at 7A, and then the electronic load was modulated between 5.7A and 8.7A at a rate of approximately 25 Hz. Figure 25 shows the output voltage in the top trace. The lower trace is the current in the output inductor. Note that the output voltage is well-behaved and that there is no overshoot of the inductor current.
Figure 23 illustrates the operation of the mag amp in more detail. The upper trace is the input voltage of the mag amp, and the lower trace is its output. The reset volt-second product is the difference between the negative pulses of the two traces. The shape of the negative pulse in the lower trace is due to the changing impedance of the mag amp core during reset.
Top: VouT, 2V x 20 ms/div. Bot: Inductor current, 2A x 20 ms/div.
Figure 25. Response of current limiter with·load switched between 5.7 and 8.5A; with current limit set at 7.5A.
Top: Secondary voltage (into mag amp), 20V x 5 µs/div. Bot: VouT of mag amp, 20V x 5 µs/div.
Figure 23. Mag amp operation.
Finally, Figure 26 shows the operation of the current-limiting amplifier. The upper trace is the inductor current, and the lower trace is the output voltage of the current-detecting amplifier. Note the output waveform of the amplifier. Although the amplifier performs as an integrator, it slews fast enough to keep up with the rate of rise of the inductor current, .thus adequately protecting the converter and output rectifiers.
9-120
APPLICATION NOTE
U-109
Thp: Inductor current, 2A x .I ms/div. Bot: VouT of C.L. amp (pin I), 2V x .I ms/div.
Figure 26. Response time of current limit amplifier.
APPLICATIONS AT HIGHER SWITCHING FREQUENCIES
As mag amp output regulators are applied at higher and higher switching frequencies, the second-order effects, of course, become more significant.' Leakage inductance of the transformer and saturated inductance of the mag amp rob the circuit of its control range, since these produce additional dead time at the leading edge of the output pulse. Even without the mag amp output regulator, this can be a problem in high-frequency switched-mode converters.
Diode storage time has the same result. If the output side of the mag amp "sticks" at ground (during reverse recovery of the rectifier) while its input voltage swings negative, some unwanted reset will be applied to the mag amp. There are techniques to deal with this problem, by providing a shunt recovery path around the mag amp to remove the stored charge in the diode.·
The control circuit of the mag amp regulator is not involved in the cycle-by-cycle operation of the circuit; hence, the control IC is not a major barrier to raising the operating frequency. It does affect the situation in an indirect way, however. Its gain-bandwidth may limit the speed of transient response such that the loop crossover frequency cannot be raised in proportion .to the switching frequency. In most applications this will not be objectionable. If it is, an outboard op amp can provide the additional gain-bandwidth. If the regulator is not required to have its own current limiter, then the second amplifier can be used in cascade with the first, to provide additional gain-bandwidth.
The integration of the circuit blocks required to implement mag amp output regulators is an important contribution. It is especially beneficial to have the reset transistor included, as this can even eliminate a small heat sink. Finally, it is helpful not only in the design process but also in production to have a single component which encompasses all of the active control functions. As more and more designers are working with the same component, the development of the technology will be more focused, and this will be universally beneficial.
REFERENCES
I. R. D. Middlebrook, "Describing Function Properties of a Magnetic Pulse-Width Modulator;· IEEE Power Electronics Specialists Conference, 1972 Record, pp. 21-35.
2. H. Dean Venable, "The K Factor: A New Mathematical Tool for Stability Analysis and Synthesis;· Proceedings of the Tenth National Solid-State Power Conversion Conference, Powercon IO Record, pp. H-1-1 - H-1-12.
3. C. E. Mullett, "Performance of Amorphous Materials in High-Frequency Saturable Reactor Output Regulators;· Proceedings of the First International High Frequency Power Conversion Conference, May, 1986, pp. 121-132.
4. C. E. Mullett and R. Hiramatsu, "An Improved Parallel Control Circuit for Saturable Reactor Output Regulators in High-Frequency Switched-Mode Converters;· Proceedings of The IEEE Applied Power Electronics Conference and Exposition, April, 1986, pp. 99-106.
5. Unitrode IC Corp. acknowledges and appreciates the support and guidance given by the Power Systems Group of the NCR Corporation, Lake Mary, FL in the development of the UCl838.
Unitrode Integrated Circuits Corporation
7 Continental Boulevard. ·P.O. Box 399 ·Merrimack, New Hampshire· 03054-0399
Telephone 603-424-2410 · FAX 603-424-3460
9_121
n n INTEGRATED
~CIRCUITS
-UNITRDDE
APPLICATION NOTE
U-110
1.5 MHZ CURRENT MODE IC CONTROLLED\
50 WATT POWER SUPPLY
Abstract This application note highlights the development of a 1.5 megahertz current mode IC controlled, 50 watt power supply. Push-pull topology is utilized for this DC to DC converter application of +48 volts input to +5 volts at 10 amps output. The beneficial increase in switching speed and dynamic performance is made possible by a new pulse width modulator, the Unitrode UC3825. Reductions in magnetic component sizes are realized and the selections of core geometry, ferrite material and flux density are discussed. The effects of power losses throughout the circuit on overall efficiency are also analyzed.
Introduction The switching frequencies of power supplies have been steadily increasing since the advent of cost effective MOSFETS, used to replace the conventional bipolar devices. Whilethetransitiontime in going from twenty to hundreds of kilohertz has been brief, few designers have ventured into, or beyond, the one megahertz benchmark. Until recently, those who have, had utilized discrete pulse width modulation designs due to the absence of an integrated circuit truely built for high speed. The 1.5 MHZ power supply shown schematically in figure 1 was designed to exemplify high frequency power conversion under the supervision of such an IC controller, the UC3825!
Figure 1. Schematic Diagram
J1 TP'A
C1 C2 A10 47,.F 47,..F 20K 63V 631/ Y2W
TP'W
TP'L
A1 1.5K· 1 W-1%
C4 TP'O 470p!·St:N
: UC 3825
TP'G
-V1N
PGNO
CA7 .
10A (3) 1µF - 50V
USD640C
TP'X
A22 A23 241l 240 'hW 'hW
TP'P
A4 1K- 112W
A5 A6 R7 R8 1.50 150 15tl 150
1W 1W 1W 1W
9-122
APPLICATION NOTE
U-110
II. POWER SUPPLY SPECIFICATIONS
Input Voltage Range: 42 to 56 voe
Switching Frequency: 1.5 MHz
Output Power: Output Voltage:
51 Watts Max.
5.1 voe Norn.
Output Current:
2-10 ADC
Line Regulation:
5MV
Load Regulation:
15 MV
Output Ripple:
100 MV Typ.
Efficiency:
750/oTyp.
Ill. OPERATING PRINCIPLES
Power can efficiently be converted using any of several standard topologies. Design tradeoffs of cost, size and performance will generally narrow the field to one that is most appropriate. For this demonstration application, the center-tapped push-pull configuration has been selected.
Current mode control provides numerous advantages over conventional duty cycle control, and has been implemented as the regulation method. In review, the error amplifier output (outer control loop) defines the level at which the primary current
A basic current mode controlled, mosfet switched push-pull converter is shown in figure 2. Transistor 01 is turned on by a drive pulse from the PWM, causing primary current Ip to flow through the transformer primary, mosfet 01 and sense resistor As. Simultaneously, diode 01 conducts current Ip x Np/Ns in the secondary, storing energy in inductor L1and delivering power to the outputload. When 01 receives a turn-off pulse from the PWM, it halts the current flow in the primary. Secondary current continues due to the filter inductor L1. Diodes 01 and 02 each conduct one-half the DC output current during these converter "off" times. This entire process is repeated on alternate cycles, as 02 next is toggled on and off. The basic waveforms are shown in figure 3 for reference.
VGs(01) 0
IG(01)0
VGs (02) 0 _ _ ____,
IG(02) 0
v
SENSE
+ CURRENT MODE
VIN CONTROL PWM
Ip 01
Vee
Vos (01) VsAr
+
2·Vee
Vo
Vos (02) Vee VsAT _ _ _ _ ,_ ___,
IPRI 0
I
SENSE Rs
VsEc 0
V01 0
Figure 2. Basic Diagram - Push-Pull Converter Using Current Mode Control
(inner loop) will regulate the pulse width, and output voltage. Pulse-by-pulse symmetry correction (flux balancing) is inherent to current mode controllers, and essential for the push-pull topology to prevent core saturation.
lo 101 lo/2
lo lsEC
0 -------------------------
Figure 3. Basic Push-Pull Waveforms
9-123
APPLICATION NOTE
U-110
IV. DESIGN CONSIDERATIONS
Auxiliary Supply Voltage The 9.2 volt minimum requirement of the UC3825 and 20 volt gate-source maximum of the mosfets imply an approximate 10 thru 18 volt range of inputs. The 10 volt value was selected to supply both Vee and Ve (totem pole outputs) while keeping power dissipation in the IC low. The circuit used is a simple resistor-zener dissipative network with ample bypassing capacitors located nearthe IC to reduce noise.
Oscillator Frequency The oSc:illator frequency selected is 1.5 MHz, resulting in a 670 nanosecond period. From the UC3825 data sheet, oscillator frequency versus Rt, Ct, and deadtime curves:
F0 = 1.5 mHz; T period = 670 ns Ct= 470pF Rt=1.5K Therefore; T(on) = 570 ns (max)
T(off) = 100 ns (min)
DUTY CYCLE d max = T (on) max = 570 ns = 850/o
'
T (period) 670 ns
NOTE: These times will determine the mosfet device selection and transformer turns ratio.
Preliminary Considerations Prior to designing the main transformer, several parameters need to be defined and determined.
Standard design procedures are used for this "first cut" approximation.
Input Power Input power, p (in) = Output power, P(out)
Efficiency, n
Let n = 750/o for a 5 v, single output power supply.
P(in) = 5.1 v. 10 a = 51 watts = 68 watts
0.75
0.75
Primary Current The primary current can be approximated using the low-line constraints of 42 volts DC input:
Primary Current (de) = Input power p (in) = 68 watts = 1.62 A Input voltage V (in) 42 volts
The primary current during the transistor on time is: 1(p) = ~ = 1·62 A = 1.9 amps, or approx. 2A
d(max) 0.85 The RMS primary current is:
Ip (rms) = Ip JduiY = 1.24A (rms)
Sense .Resistor R (s) Primary current is sensed and controlled in a current mode controller by first developing a voltage proportional to the primary current, used as an input to UC3825. This is accomplished by sense resistor R (s) with a calculated value of the I limit threshold value divided by the primary current at the desired current limit point, typically 120% I (max).
R(s) s V th (pin 9) = 1volt = 0.42ohm 1200/o ·I (pri) 1.2 · 2amps
Mosfet DC Losses A high quality mosfet is used to keep both DC and switching losses low, with an R (ds) on max of 0.8 ohms. Calculation of the voltage drops across the device are required for the transformer design.
V ds (on) = Rds (max)· I (p) = 0.8 · 2 = 1.6 v During an overload; V ds (max) = 0.8 · 2· 1.20 = 1.92 v(2 v)
Pde = I dc2 Rds max · duty = 22 · 0.8 · 0.85/2 = 1.35 watts
Selection of Core Material Few manufacturers provide core loss curves for frequencies above 500 khz. To minimize power dissipation in the core, the flux density must be drastically reduced in comparison to the 20 -150 khz versions. Typical operation is at a total flux density swing, delta B, of 0.030 Tesla (300 Gauss) while approaching the 1 megahertz region. TDK's H7C4 material was selected for it's low loss, high frequency characteristics.
Main Transformer Design The first step in transformer design is to determine the preliminary turns ratio. Once obtained, the minimum cross-sectional area core (Ae) can be calculated, and core selection made possible.
Calculation of Transformer Voltages and Turns Ratio V pri (min) = V in (min) - V xtor (max) - V (Rs) max
V p (min) = 42 v- 2.0 v - 1v = 39.0v
V sec (min) = V out (max) + V diode (max) + V choke (de) + V (losses)
V sec (min) = 5.1 + 0.65 + 0.1 + 0.05 (est) = 5.9 v
Turns ratio N = V pri (min) Duty (max) = 39.0 · 0.85 = 5.6:1
V sec (min)
5.9
9-124
APPLICATION NOTE
The secondary is designed for excellent coupling using copper foil, and the primary has been rounded to the nearest lower turns.
Turns ratio: N = N pri I N sec = 5:1
The actual number of both primary and secondary turns will be determined by the ferrite core characteristics as a function of operating frequency and Gauss level.
Minimum Core Size The minimum cross-sectional area core that can be used is calculated with the following equation for core loss limited applications.
,A...~., ( mi.n) = V (pri) min · Duty (max) · 104 (cm2) 2 · Freq. · N (p) · .::\8 (Tesla)
At first it would seem that the core area required for this 1.5 MHZ switcher would be ten times smaller than that of a 150 KHZ version. This would be true if the flux density, number of turns and core losses remained constant. However, losses are a function of both frequency and frequency squared2 and as it increases, the flux density swing (~B) must be drastically reduced to provide a similar core loss, hence temperature rise. In this example, an acceptable figure was selected of one percent of the total output power, or one-half watt. Empirically, this translates to a temperature rise of 25°C, at 325 Gauss (0.0325 Tesla) for cores with a cross-sectional area of 0.70 sq. cm, a ballpark estimate of the true core size.
This formula can be rewritten as:
Ac · Np = V pri · D max · 104
2 · F·.::\B
This is a more convenient formula because the right hand side of the equation contains all constants. Input voltage, frequency of operation and flux density have already been determined. The selection of core size (cross-sectional area) is inversely proportional to the number of primary turns, and vice-versa. Based on the five-to-one turns ratio, an original assumption of five turns for the primary would result in a large core Size forth is 50 watt application. Alternatively, a ten turn primary is used to minimize core size.
Substituting previous values for high line operation at 0.0325 Tesla (325 Gauss) and a magnetic operating frequency of 750 kHz:
Ac (min) =
39 ' 0·85 ' 104
= 0.68 cm2
2 · 750,000 · 10. 0.0325
U-110
Core Loss Limited Conditions As the switching frequencies are increased, generally a reduction of core size or minimum number of turns is realized. This is true, however, but only to the point at which the increasing core losses prevent a further reduction of either size or minimum turns. This crossover point occurs at different frequencies for each individual ferrite material based upon their losses and acceptable circuit losses, or temperature rise~
Core Geometry Selection A variety of standard core shapes are available in the cross-sectional area range of 0.62 to 0.84 cm2. Considerations of safety agency spacing requirements, physical dimensions, window area and relative cost of assembly must be evaluated.
Core Style PQ POT CORE LP TOROID EE
Description PQ20/20 P22/13 LP 22/13 T28/13 EE35/28
AC (cmt)
0.62 0.63 0.68 0.76 0.78
Weight (g)
15 13 21 26 28
The LP 22/13 style was selected to easily terminate (breakout) the high current output windings. For a given cross-sectional area, it occupies less PC board space, and has good shielding characteristics.
Wire Size Selection The single, most difficult task in high frequency magnetic design is to minimize the eddy current losses, or skin effects while optimizing wire sizes. Penetration depth refers to the thickness (or depth) into a copper conductor in which a wave will penetrate for a specific frequency. For copper at 100°C:
d pen = 7.5 / (frequency"5) (cm)
At 750 kHz, this corresponds to 8.66 · 103 cm, or about the thickness of an AWG #39 wire. Larger size wire can be used, however the AC current flows only in the depth penetrated at the switching frequency. Consult the UNITRODE DESIGN SEMINAR SEM-400 book, appendix M2 for additional information on this subject.
9-125
APPLICATION NOTE
U-110
For low current windings, several strands of thin wire can be paralleled, or twisted togetherforming a "bundle." Seven wires twisted around each other closely approximate a round conductor with a net diameter of three times the individual wire diameter. This twisting is commonly done at 10-12 turns per foot, and significantly reduces parasitics between wires at high frequencies.
Medium to high current windings require the use of Litz wire, a similar bundle of numerous conductors. Copper foil is also an excellent choice.
Industry practice is to operate at 450 amps (RMS) per centimeter squared, or 2.22 · 10-3 cm2/A. This applies to windings operating at an acceptable temperature rise.
Area required = I rms / 450A I cm2 Primary area (Axp) = 1.24A / 450A I cm2 = 2.75 · 10-3 cm2
Calculate Secondary RMS Current.
1rms (sec) = I sec2 (duty on) + I sec2 (2 · duty off)
2
2
I rms (sec) = 102 (.425) + ~ (2 · .075) 2
2 I rms (sec) = 4.81A
Secondary Area (Axs) = 4.81A / 450A I cm2 = 1.07 · 10-2 cm2
7STRANDS
3d
"'2.75
3d
! !
3LAYERS Figure4.
For a given bundle of 7 conductors, the cross-sectional area of each conductor equals:
Required area = Axp = 2.75 · 10-3 = 3.93 · 10_. cm2
#conductors
7
7
The cross-sectional area of an AWG #36 wire is 1.32 · 10-4 , therefore, three bundles of seven conductors each should be used. Two bundles were utilized as a compromise between practical winding considerations and acceptable eddy current losses.
Copper foil is used for the secondary, with a required width slightly less than the bobbin width, and thickness determined by:
Secondary area (Axs) 1.07 · 10-2 cm = 7.64 , 10_3 cm
Bobbin width
1.40 cm
This corresponds to 0.003" thick foil, a standard value. In practice, slightly thicker foil (0.004" to 0.005") may be required to minimize power losses in the transformer.
Transformer Assembly Standard practice to increase coupling between primary and secondary is position both as closely as possible to each other inside the transformer. In this design, the first layer wound is one primary, and the next layer is the corresponding secondary. This is again followed by the other secondary and primary. It is important to keep the secondaries in close proximity since both will be conducting simultaneously twice per period. The primaries do not conduct in this manner, so coupling from primary A to primary Bis not critical, only primary A to secondary C, and primary B to secondary D.
Referring to the transformer schematic, primary A is wound closest to the bobbin. After insulation, secondaries C and D are wound bifilar and insulated. Primary B is wound last, then terminated so that primaries A and Bare wired in series, likewise for secondaries C and D.
# 7 & # 8 - -A- - - - . 2 BUNDLES ·
10T
#3----# 5 & # 6 - -B- - - - .
2 BUNDLES ·
10T
ED D1 T D2
EC C1 T C2
#1-----
PRIMARY
SECONDARY
Figure 5. Transformer Schematic
9-126
APPLICATION NOTE
B
B
U-110
A
A
TAPE (INSULATION)
BOBBIN
Figure 6. Transformer - Exploded View
Calculation of Winding Resistances and Losses The mean length of turn for the bobbin can be determined from the specifications of O.D. and l.D., and for the BLP 22/13 a figure of 4.51 cm or 1.77 in. was obtained. AWG #36 wire has a resistance of 1.82 · 10-2 ohms/cm at 100°C for the following:
Primary resistance can be calculated:
Rpri =
R wire· M.LT. ·#turns = 0.0182 · 4.51 · 10 = 0.0586 ohm
#wires
14
Voltage drop and power loss in each half winding can be also calculated:
V (R pri) = lpri · Rpri = 2.0 · 0.58 = 0.116 volt (negligible)
P (Rpri) = R pri · I pri2 · duty = 0.0586 · 4 · 0.425 = 0.0996 watts
The resistance of the secondary can be approximated by using the wire tables, and substituting
the foil for wire of similar cross-sectional area. In this example, AWG #16 wire is used to obtain Rsec
= 1.58 · 10-4 ohms/cm.
Rsec = Rfoil·M.L.T.·#turns = 1.58·10-4 ·4.5·2 = 0.00143 ohm
V (Rsec) = 1.43 · 10-3 · 10 = 0.0143 volt (negligible)
P (Rsec) = R sec ( (ldc2 · D on) + ( {ldc/2)2 · 2 · D off) )
P (Rsec) = 0.00143 ( (102. 0.425) + (52 · 0.15) = 0.066watts
Transformer Power Losses
The total copper losses for two windings are then:
P cu = P (Rpri) + P (Rsec) = 2 · (0.066 + 0.0996)
= 0.332watts Estimated eddy current losses are approximately 50% of the copper losses. Pcu "" 0.50 watts.
Given the core material type, geometry, frequency and operating Gauss level, the ferrite losses can be calculated. From the manufacturers information, the typical loss coefficient for H7C4 material operating at a flux density swing of 0.035 Tesla (350 Gauss) at 750 kHz is 0.15 watts per cubic centimeter of core volume, which is 3.327 cm3 per LP 22/13 core set. Therefore:
P core = 3.327 · 0.15 = 0.50 watt
The total power lost is a summation of the copper and ferrite losses:
P xfmr = P cu + P core = 0.50 + 0.50 = 1.00 watts
OUTPUT SECTION
Output Choke Calculations Typically, the RMS output ripple current is less than 15% I de, or 1.5ampsinthiscase. Delta I, the peak to peak ripple therefore is twice the RMS, or 3 amps.
V = L di : L = V dt = 5.9 v (350) 10-9 s = 690 nanohenries
dt
di
3.0A
9-127
APPLICATION NOTE
U-110
Due to the small value of inductance required, the conventional approach will not be used. Instead, a simple RF type wound coil will be designed using the solenoid equation found in most reference texts. A thick pencil will be utilized as the coil form with a diameter of 0.425 inches, however any similar item will suffice.
The form factor, F, is a function of the form diameter divided by the length of the wound coil; or D/L. A few gyrations will take place before the exact values are obtained, however this goes quickly. The form factor is listed below for various practical values of D/L.
Coil Dia./Length
0.1 0.25 0.50 1.0 2.0 5.0
Form Factor "F"
0.0025 0.0054 0.010 0,0173 0.026 0.040
L (µH) = F · N2 · D (in), N = (L/F · 0)112 (turns)
For D = 0.425, D/L = 1 (approx); F = 0.0173 N = (0.690 I 0.0173 · 0.425) 112 = 9.76 turns
Rounding off to the nearest next number of turns, the. actual inductance for 10 turns can be calculated: L (!'h) = 0.0173 · 102 · 0.425 = 744 nanohenries
In an air core inductor the permeability "u" equals unity, therefore the flux density B equals the driving function H.
Output Capacitor
Q = I p-p ' T period ' ~ , Delta Q = I p-p I 8 · F
2
2
2
C = QI dV where dV (output ripple) equals 0.100 volts.
C = lp-p/8·F·dV = 3/8·1.5·106 ·0.10 = 2.5µF
Three 1 pi caps are used in parallel. With a typical
ripple voltage of < 50 mv due to ESR, the ESR
each (at 1.5 mHz) must be approximately 150
milliohms. The Unitrode ceramic monolithic
capacitor series was selected for their excellent high frequency characteristics.
Resonance, and its effect at these frequencies must be taken into account. In this case, the capacitor reaches resonance at 1.5 mHz, and the effective impedance is resistive.
Output Diodes Schottky diodes were selected for their short reverse recovery times to minimize switching losses, and low forward drop for high DC efficiency. The Unitrode USO 640C is a center-tapped T0-220 type, with ample margin to safely accommodate 40 volt reverse transients and 10 amp DC output currents. Also featured is a 0.65 volt maximum drop across each diode and 1 volt per nanosecond switching rate.
UC3825 PWM CONTROL SECTION
Current Limit I Shutdown Pulse-by-pulse current limiting is performed by the UC3825 by an input of the primary current waveform to the IC at pin 9. The small RC network of R3 and C8 are used to suppress the leading edge glitch caused by turn-on of the mosfet and transformer parasitics. The input must be below the 1 volt threshold or current limiting will occur. Once reached, an input above the threshold will narrow the pulse width accordingly. When this reaches a 1.4 volts amplitude, shutdown of the outputs will occur, and the UC3825 will initiate a soft start routine.
Ramp The UC3825 offers the flexibility of both Current Mode Control or conventional duty cycle control via the RAMP input pin. When connected to the timing capacitor, the UC3825 operates as a duty cycle control IC. Connecting the RAMP input to the current waveform changes the control method to Current Mode. In this application, the ramp waveform is tied through a small RC filter network to the primary current waveform. This network is defined in the next section - slope compensation. The dynamic range of this input is 1-3 volts, and is generally used for introducing slope compensation to the PWM.
Slope Compensation Slope compensation is requirad to compensate for the peak to average differences in primary current as a function of pulse width. Adding a minimum of 50% of the reflected downslope of the output current waveform to the primary current is required. See UNITRODE APPLICATION NOTE U-93 and U-97 for further information. Empirically, 60-75% should be used to accommodate circuit tolerances and increase stability?
9-128
APPLICATION NOTE
Resistors R2 and R4 in this circuit form a voltage divider from the oscillator output to the RAMP input, superimposing the slope compensation on the primary current waveform. Capacitor C6 is an AC coupling capacitor, and allows the 1.8 volt swing of the oscillator to be used without adding offset circuitry. Capacitor C7 has a two-fold purpose. During turn on it filters the leading edge noise of the current waveform. and provides a negative going pulse across R4 to the ramp input at the end of each cycle. This overrides any parasitic capacitance at the ramp input, (pin 7), that would tend to hold it above zero volts. This insures the proper voltage input at the beginning of the next cycle.
C7
U-110
STEP 1. Calculate Inductor Downslope
S (L) = di/dt = V sec I L = 5.9 VI .740 µH = 8.0 AJ,,s (1)
STEP 2. Calculate Reflected Downslope to Primary
S(L)' = S(L) IN (turns ratio) = 8.D/5 = 1.6 AJµS
(2)
STEP 3. Calculate Equivalent Ramp Downslope Voltage
V S(L)' = S(L)' · Rsense = 1.6 · 0.375 = 0.600 V/,,s (3)
STEP 4. Calculate Oscillator Slope
VS (osc) = d (V osc) IT on = 1.8 V / 570 ns = 3.15 V/,,s(4)
STEP 5 Generate the Ramp Equations Using superposition, the circuit can be configured as:
R4
R2 Sosc.
RAMP
Rs
R4
For the purposes of determining the resistor values, capacitors C4 (timing), C6 (ac coupling) and C7 (filtering) can be removed from the circuit schematic. The simplified model represented in figure 8 is used forthe calculations. These calculations can be applied to all Current Mode circuits using a similar scheme.
Rs
R4
Figures.
Flgure9.
V (ram ) = VS (L)' · R2 = VS (osc) · R4
p R2 + R4
R2 + R4
(5)
SUBSTITUTING,
V (ramp) = VS (L)" + VS (comp)
(6)
WHERE
vs (com ) = VS (osc) · R4 . VS (L)" = VS (L)' · R2
p
R2 + R4 '
R2 + R4
STEP 6. Calculate Slope Compensation
VS (comp) = m · S(L)"
(7)
Where m equals the amount of inductor downslope to be introduced. In this example, let m = 75%, or 0.75.
VS (osc) · R4 m · V S(L)' · R2
R2 + R4
R2 + R4
SOLVING FOR R2:
R2 = R4 · VS (osc) = R4 · 3.15
VS (L)' · m
0.600 · 0.75
(9)
USING CIRCUIT VALUES, R2 = 7.05 · R4
For simplicity, let R4 equal 1 K ohms and R2 therefore equals 7.05 K. Using the nearest standard value resistor of 6.8 K, the exact amount of downslope is minimally affected. Important, however, is that the series combination of R2 and R4 is high enough in resistance not to load down the oscillator and cause frequency shifting.
9-129
APPLICATION NOTE
U-110
CLOSING THE FEEDBACK LOOP
Error Amplifier Compensation of the high gain error amplifier in the UC3825 is straight forward. There is a single-pole at approximately 5 hertz. A zero will be introduced in the COfT1pensation network to provide gain once the zero db threshold is crossed. Using Current Mode control greatly simplifies the compensation task as the output choke is controlled by the inner current loop, thus making the output section appear as a single pole response with a zero at the ESR frequency~
Control to Output Gain The control to output gain will vary with output loading, and as the load is increased the gain decreases. Output capacitor ESR will determine the frequency at which the zero occurs, thus changing the gain as a function of ESR. To insure stability through all combinations of load and ESR, the amplifier will be compensated to cross zero db at approximately one-fifth of the switching frequency with ample phase margin.
The output filter pole and zero occur at Fp = 1/2,.. R (load) C (output)
Fz = 1/2 r R (esr) C (output)
CIRCUIT PARAMETERS:
C (output) = 3 µF; ESR (each) = 0.050 min - 0.300 max
For three capacitors in parallel, ESR = 0.016- 0.100 ohms
R (output) = 2.5 ohms at 2 A, 0.5 ohms at 10 A
Using the above equations; Fp (2A) = 1 I (2 · 3.14 · 2.5 · 3.10-6) = 21.2 kHz
Fp (10A) = 1 I (2 · 3.14 · 0.5 · 3°10-6) = 106.1 kHz
Fz (high) = 1 I (2 · 3.14 · 0.016 · 3°10-6) = 3.315 mHz Fz (low) = 1/(2·3.14 · 0.100 · 3·10-6) = 530.5 kHz
GAIN
V (output) = K. Ra, where K = lpri · Np/Ns = 2·5 = 11 .76
V (control)
V (control) 0.85
Therefore, at 2 amps and 10 amps,
Va/Ve = K·ro = 11.76 · 2.5 = 29.4 db (2A) Va/Ve = K·ro + 11.76 · 0.5 = 15.4 db (10A)
Error Amplifier Compensation The control to output gain can be plotted along with the desired zero db crossing point and an estimate of the error amplifier required compensation network can be made. The amp compensation should have a zero at approximately 100 kHz, and a gain of -16 db at this frequency. Resistor R9 has been selected to be 3.3 k ohms based on the output drive capability of the UC3825 amp. Complete specifications are contained in the UC3825 data sheet.
F zero (amp) = 1 I (2 · r · R9 · C12) therefore, C12 = 1 I (2 · ,,. · R9 · F zero) C12 = 1 I (2 · 3.14 · 3300 · 100.000) = 480 pF (use 560 pF)
R10 IR9 = approx -16 db (0.16), R10 = R9 /gain = 3.3 KI 0.16 = 20.4 K (use 20 K)
This compensated response can now be plotted, along with the control to output gain and the overall power supply response is a summation of the two curves, as seen in figures 11and12. Low frequency gains of 100 db at full load, and 115 db at light load are obtained, with a zero db crossing at approx. 100 kHz for both. Phase margin is generous with approx. 90 degrees for both light and 45 degrees at full load.
GAIN AND PHASE RESPONSE UC3825 DEMO KIT
UGHT
130
GAIN - LIGHT LOAD
120
FULL
130 120
GAIN - FULL LOAD
100
101
"" 10'
10·
FREQUENCY {HZ)
10·
"''
10'
PH~I
Figure 11.
100 10'
"" 10'
10· 100
FREQUENCY (HZ)
10· 10'
-~c=:
180
PHASE
Figure 12.
::1
9-130
APPLICATION NOTE
U-110
LIST OF MATERIALS
REFERENCE DESCRIPTION
Capacitors C1, 2 C3, 5 C4 C6 C7 CB C9-11, 17-19 C12 C13, 14 C15, 16
4.7 µF, 63 VOC Electrolytic 0.1 µF, 50 VOC Monolithic 470 pF, VOC Monolithic O.D1 µF, 50 VOC Monolithic 120 pF, 50 VOC Monolithic 15 pF, 50 VOC Monolithic 1 µF, 50 VOC Monolithic 560 pF, 50 VOC Monolithic 150 pF, 150 VOC Ceramic 5000 pF, 50 VOC Ceramic
Diodes CR1 CR2, 3 CR4, 5 CR6, 7
1N4465 US01140 UES1105 US0640C
10 V, 1.5 Watt Zener 40 V, 1 Amp Schottky 150 V, 2.5 Amp Ultrafast 40 V, 12 Amp Schottky
Integrated Circuits
U1
UC3825 Unitrode High Speed PWM
Transistors
01, 2
UFN633 150 V, 8A Mosfet
Resistors R1 R2 R3, 4, 14, 15 R5-8 R9 R10 R11, 12 R13 R16-19 R20-23 R24
1.5 K, 1/2 W, 10/o 6.8 K, 1/2 W, 50/o 1 K, 1/2 W, 5% 1.5R, 1 W,50/o 3.3 K, 1/2 W, 50/o 20 K, 1/2 W, 50/o 6.2 R, 1/2 W, 50/o 500 R, 5 W, 100/o 200 R, 1/2 W, 50/o 24 R, 1/2 W, 50/o 51R,1W,5%
Magnetics L1 T1
740 nH Wound Coil AIE Magnetics Custom Transformer, 5:1 Turns Ratio
Miscellaneous
H1
Heatsink-Mosfets (AAALL #57868)
H2
Heatsink-Oiodes (AAALL #52998)
Efficiency Measurements
V (In) 42 48 56
I (In) 1.707 1.483 1 .331
P (In) 71.7 71.2 73.2
P (Loss) Efficiency
20.2
71.8%
19.7
72.4%
21.7
70.4%
V (In)
v
42 48 56
Line
Vout (2A) 5.110 5.108 5.108
2mv
Vout (5A) 5.102 5.101 5.102
1 mv
Vout (10A)
5.093 5.092
5.089
Load Reg. MV
17 16
19
4mv
Dynamic Performance The power supply was pulse loaded from 5 amps to 10 amps at a frequency of 100 kilohertz. Recovery to within 50 mv was less than 2 microseconds with a total excursion of less than 200 millivolts. High speed FETS were used to switch the load current with typical rise/fall times of 50 nanoseconds.
Short Circuit The short circuit input current is approximately 0.75 amps, or an input power of 36 watts.
Circuit Power Losses The total circuit losses are approximated using both the calculated and measured losses throughout the power supply.
Power Losses Current Sense Circuit Output Diodes Switching Transistors Dropping Resistor Snubber Networks Transformer Losses Auxiliary Supply Miscellaneous
TOTAL LOSSES
1.2W 9.8W 3.2W 3.0W 1.0W 1.0W 0.8W 0.2W
20.2W
If a bootstrapped technique is utilized in the auxiliary supply to the IC and drive circuitry, the dropping resistor losses of three watts can be reduced to 0.1 watts in the bootstrap circuitry. In addition, the lossy resistive current sensing network can be replaced by a small current transformer, lowering the losses by a half-watt. Overall efficiency would then increase to 75%, fairly high for a five volt output application. Noteworthy is that the switching losses at this high of frequency can be minimized, and have little overall effect on circuit efficiency.
9-131
APPLICATION NOTE
U-110
Summary The demands of higher power densities will undoubtedly throttle many switch-mode power supply designs into and beyond the megahertz region in the near future. Designers will be facing the challenges of selecting switching devices, magnetic materials and IC controllers built exclusively for high efficiency at these frequencies. The thrust from contemporary hundreds of kilohertz designs to megahertz versions is rapidly making progress. This 1.5 MHZ current mode push-pull is an example of what can successfully be accomplished with existing high speed components and technology.
References 1. Woffard, Larry, - "New Pulse Width Modu-
lator Chip Controls, MHZ Switchers" - U-107; Unitrode Applications Handbook 1987/88.
2. Dixon, Lloyd Jr. - "Eddy Current Losses" Section M2-4, Unitrode Power Supply Design Seminar Book, SEM-500.
3. Andreycak, Bill - "1.5 MHZ Current Mode IC Controlled 50 Watt Power Supply," Proceedings of the High Frequency Power Conversion Conference, 1986.
4. Dixon, Lloyd Jr. - "Closing the Feedback Loop" Section C1 - Unitrode Power Supply Design Seminar Book, SEM-500.
5. Andreycak, Bill "Practical Considerations in Current Mode Power Supplies" Topic 1 Unitrode Power Supply Design Seminar Book, SEM-500.
UC3825 BLOCK DIAGRAM
CLOCK 4 1 - - - - - - - - - , Rr 5 1 - - - - - - - 1
Cr 6 1 - - - - - - - t
RAMP[I}
1.25V I
E/AOUT 3 t-----.,._Q./
ERROR! NI 2 AMP INV I ....--,,.,.
9-132
APPLICATION NOTE
TIMING WAVEFORMS
RAMP VOLTAGE
U-110
Top Trace Ramp Voltage TP 'H: 1 v/cm
Bottom Trace CT Waveform.
TP ·o: 1 v/cm
PRIMARY CURRENT
Top Trace Filtered Ip with Slope Compensation TP 'H: 1 v/cm
Bottom Trace
Unfiltered Ip
TP ·p; .5 v/cm
PRIMARY CURRENT
Top Trace
Filtered Ip
TP ·1: .5 v/cm
Bottom Trace
Unfiltered Ip TP ·p; .5 v/cm
SECONDARY WAVEFORMS
Top Trace J1. 2A/cm
Bottom Trace
TP ·p; 1 v/cm
OUTPUT WAVEFORMS
Top Trace Secondary Voltage TP T; 10 v/cm
Bottom Trace Secondary Current J2, 5 A/cm
Top Trace Output Voltage
w: Ripple & Noise
TP 100 mv/cm
Bottom Trace AC Output Current J2, 2 A/cm
Unitrode Integrated Circuits Corporation
7 Continental Boulevard.· P.O. Box 399 ·Merrimack, New Hampshire· 03054-0399
Telephone 603-424-2410 ·FAX 603-424-3460
9-133
n n l_::::::.J
INTEGRATED CIRCUITS
-UNITRODE
APPLICATION NOTE
U-111
PRACTICAL CONSIDERATIONS IN CURRENT MODE POWER SUPPLIES
Introduction This detailed section contains an in-depth explanation of the numerous PWM functions, and how to maximize their usefulness. It covers a multitude of practical circuit design · considerations, such as slope compensation, gate drive circuitry, external control functions, synchronization, and paralleling current mode controlled modules. Circuit diagrams and simplified equations forthe above items of interest are included. Familiarity with these topics will simplify the design and debugging process, and will save a great deal of time for the power supply design engineer.
Constant Output Current To maintain a constant AVERAGE current, independent of duty cycle, a compensating ramp is required. Lowering the error voltage precisely as a function of ToN will terminate the pulse width sooner. This narrows the duty cycle creating a CONSfANT output current independent of ToN, or V1N. This ramp simply compensates fcir the peak to average current differences as a function of duty cycle. Output currents 11 and 12 are now identical for duty cycles D1 and D2.
I. SLOPE COMPENSATION Current mode control regulates the PEAK inductor current via the 'inner' or current control loop. In a continuous mode (buck) converter, however, the output current is the AVERAGE inductor current, composed of both an AC and DC component.
While in regulation, the power supply output voltage and inductance are constant. Therefore, Vour I LsEc and dl/dT, the secondary ripple current, is also constant. In a constant volt-second system, dT varies as a function of V1N, the basis of pulse width modulation. The AC ripple current component, di, varies also as a function of dT in accordance with the constant Vour LsEc.
Average Current At high values of V1N. the AC current in both the primary and the secondary is at its maximum. This is represented graphically by duty cycle D1, the corresponding average current 11, and the ripple current d(l1). As V1N decreases to its minimum at duty cycle, the ripple current also is at its minimum amplitude. This occurs at duty cycle D2 of average current 12 and ripple current d(l2). Regulating the peak primary current (current mode control) will produce different AVERAGE output currents 11, and 12 for duty cycles D1 and D2. The average current INCREASES with duty cycle when the peak current is compared to a fixed error voltage.
Figure 2. Constant Average Current
Determining the-Ramp Slope Mathematically, the slope of this compensating ramp must be equal to one-half (50%) the downslope of the output inductor as seen from the control side of the circuit. This is proven in detail in "Modelling, Analysis and Compensating of the Current Mode Controller," (U nitrode publication U-97 and its references). Empirically, slightly higher values of slope compensation (75%) can be used where the AC component is small in comparison to the DC pedestal, typical of a continuous converter.
Circuit Implementation In a current mode control PWM IC, the error voltage is generated at the output of the error amplifier and compared to the primary current at the PWM comparator. At this node, subtracting the compensating ramp from the error voltage, or adding it to the primary current sense input will have the same effect: to decrease the pulse width as a function of duty cycle (time). It is more convenient to add the slope compensating ramp to the current input. A portion of the oscillator waveform available at the timing capacitor (Cr) will be resistively summed with the primary current. This is entered to the PWM comparator atthe current sense input.
Figure 1. Average Current Error
9-134
APPLICATION NOTE
Parameters Required for Slope Compensation Calculations Slope compensation can be calculated after specific parameters of the circuit are defined and calculated.
SECTION
PARAMETER
Control
T on (Max) Oscillator !l.V Oscillator (PK-PK Ramp Amplitude) I Sense Threshold (Max)
Output
V Secondary (Min) L Output
I AC Secondary (Secondary Ripple Current)
General
R Sense (Current Sensing Resistor)
M (Amount of Slope Compensation) N Turns Ratio (Np I Ns)
Once obtained, the calculations for slope compensation are straightforward, using the following equations and diagrams.
Ip
I~
Figure 3. General Circuit
Resistors R1 and R2 form a voltage divider from the oscillator output to the current limit input, superimposing the slope compensation on the primary current waveform. Capacitor C1 is an AC coupling capacitor, and allows the AC voltage swing of the oscillator to be used without adding offset circuitry. Capacitor C2 forms an R-C filter with R1 to suppress the leading edge glitch of the primary current wave. The ratio of resistor R2 to R1 will determine the exact amount of slope compensation added. For purposes of determining the resistor values, capacitors Cr (timing), C1 (coupling), and C2 (filtering) can be removed from the circuit schematic. The oscillator voltage (Vose) is the peak-to-peak amplitude of the sawtooth waveform. The simplified model is represented schematically in the following circuit. These calculations can be applied to all current mode converters using a similar slope compensating scheme.
U-111
Ip Rs
Figure 4. Simplified Circuit
Step 1. Calculate the Inductor Downslope
S(L) = di/dt = VsEcllsEC
(Amps/Second)
Step 2. Calculate the Reflected Downslope
to the Primary
S(L)' = S(L)/N
(Amps/Second)
Step 3. Calculate Equivalent Downslope Ramp
V S(L)' = S(L)' · R sense
(Volts/Second)
Step 4. Calculate the Oscillator Charge Slope
V Scosq = d (Vose) IT on
{Volts/Second)
Step 5. Generate the Ramp Equations Using superposition, the circuit can be illustrated as:
SL'.
R,
R2
? I """'
AN\
VRAMP
9.Sosc. 0~
Figure 5. Superposition
v v V(RAMP) = S(L)' · R2 + S(QSC) · R1 simplifying,
R1 + R2
R1 + R2
V(RAMPJ = V S(L)" + V SccoMPJ
where
v S(COMP) = v S(OSC) · R1 ' and v S(L)" = v S(L)' · R2
R1 + R2
R1 + R2
Step 6. Calculate Slope Compensation V S(COMP) = M · S(L)" where M is the amount of inductor downslope to be introduced.
Equating V S(OSC) · R1 = M · V S(L)' · R2
R1+R2
R1+R2
, solving for R2
R2 = R1 · V S(OSC) VS(L)'·M
9-135
APPLICATION NOTE Equating R1 to 1K ohm simplifies the above calculation
and selection of capacitor C2 for filtering the leading edge glitch. Using the closest standard value to the calculated value of R2 will minimally effect the exact amount of downslope introduced. It is important that R2 be high enough in resistance notto load down the l.C. oscillator, thus causing a frequency shift due to the slope compensation ramp to R2.
VREF
PWM
Cr
Ip
ISENSE
Figure 6. Emitter Follower Circuit
Design Example - Slope Compensation Calculations
Circuit Description and Parameter Listing:
Topology: Half-Bridge Converter Input Voltage: 85-132 VAC "Doubler Configuration" Output: 5 VDC/45 ADC Frequency: 200 KHz, T Period = 5.0 µS T Deadtime: 500 ns, T on Max = 4.5 µS Turns Ratio: 15/1, (Np/Ns) V Primary: 90 VDC Min, 186 Max V Sec Min: 6 VDC R Sense: 0.25 Ohm
I Sec k: 3.0 Amps (<10% I DC)
L Output: 5.16 µh
1. Calculate the Inductor Downslope on the Secondary Side
s (L) = di/dt = VsEcllsEC = 6 v/5.16 µh = 1.16 A/µS
2. Calculate the Transformed Inductor Slope to the Primary Side
S (L)' = S (L) · Ns/Np = 1.16 · 1115 = 0.0775 A/µS
3. Calculate the Transformed Slope Voltage at
Sense Resistor
V S(L)' = S (L)' · Rsense = 7.72 · 10-2 · 0.250 =
1.94·10-2 V/µS
.
U-111
4. Calculate the Oscillator Slope at the Timing Capacitor S(OSC) = d V osc/T on max= 1.8/4.5 = 0.400 V/µS
5. Let Amount of Slope Compensation (M) = 0.75 and R1 = 1K
R2 = R1 · V S(OSC) : R2 = 1K · 0.400
V S(L)' · M
0.0192 · 0.75
= 27.4 K ohms
II. GATE DRIVE CIRCUITRY Thetiigh currenttotem-pole outputs of most PWM ICs have greatly enhanced and simplified MOSFET gate drive circuits. Fast switching times of the high power FETs can be attained with nearly a "direct" drive from the PWM. Frequently overlooked, only two external components - a resistor and Schottky diode are required to insure proper operation of the PWM while delivering the high current drive pulses.
MOSFET Input Impedance Typical gate-to-source input characteristics of most FETs reveal approximately 1500 picofarads of capacitance in series with 15 nanohenries of source inductance. For this example, the series gate current limiting resistor will not be used to exemplify its necessity. Also, the totem pole transistors are replaced with ideal (lossless) switches. A dV/dT rate of 0.5 volts.per nanosecond is typical for most high speed PWMs and will be incorporated.
PWM
+15
FET INPUT
I I IMPEDANCE
1-----4~---.
1500 pF
15 NH
Figure 7. Ideal Circuit Gate Drive
Assuming no external circuit parasitics of R, L or C, the PWM is therefore driving an L-C resonant tank with no attenuation. The driving function is a 15 volt pulse derived from the auxiliary supply voltage. The resulting current waveform is shown in figure 8, having a peak current of approximately seven amps at a frequency of thirty-three megahertz.
9-136
APPLICATION NOTE
U-111
v
+7 -
0
-7--
Figure 8. Voltage & Current Waveforms at Gate
In a practical application, the transistors and other circuit parameters, fortunately, are less than ideal. The results above are unlikely to happen in most designs, however they will occur at a reduced magnitude if not prevented.
Limiting the peak current through the IC is accomplished by placing a resistor between the totem-pole output and the gate of the MOSFET. The value is determined by dividing the totem-pole collector voltage 0/c) by the peak current rating of the IC's totem-pole. Without this resistor, the peak current is limited only by the dV/dT rate of the totem-pole and the FET gate capacitance.
For this example, a collector supply voltage of 10 volts is used, with an estimated totem-pole saturation voltage of approximately 2 volts. Limiting the peak gate current to 1.5 amps max requires a resistor of six ohms, and the nearest standard value of 6.2 ohms was used. Locating the resistor in series with the collector to the auxiliary voltage source will only limit the turn-on current. Therefore it must be placed between the PWM and gate to limit both turn-on and turn-off currents.
Actual circuit parasitics also play a key role in the drive behavior. The inductance ofthe FETsource lead (15 nanohenries typical) is generally small in comparison to the layout inductance. To model this network, an approximation of 30 nanohenries per inch of PC trace can be used. In addition, the inductance between the pins ofthe IC and the die can be rounded off to 10 nanohenries per pin. It now becomes apparent that circuit inductances can quickly add up to 100 nanohenries, even with the best of PC lay-
outs. For this example, an estimate of 60 nh was used to
simulate the demonstration PC board. The equivalent circuit is shown in figure 10. A 10 volt pulse is applied to the network using 6.2 ohms as the current limiting resistance. Displayed is the resulting voltage and current waveform at the totem-pole output.
Figure 9. Circuit Parameters
10
v
(v)
0
0 (A)
-1
Figure 10. Circuit Response
The shaded areas of each graph are of particular interest. During this time, the lower totem-pole transistor is saturated. The voltage at its collector is negative with respect to it's emitter (ground). In addition, a positive output current is being supplied to the RLC networl< thru this saturated NPN transistor's collector. The IC specifications indicate that neither of these two conditions are tolerable individually, nevermind simultaneously. One approach is to increase the limiting resistance to change the response from underdamped to slightly overdamped. This will occur when: R (gate) ~ 2 · .JDC Unfortunately, this also reduces the peak drive current, thus increasing the switching times of the FETS - highly undesirable. The alternate solution is to limit the peak current, and alter the circuit to accept the underdamped network.
9-137
APPLICATION NOTE
The use of a Schottky diode from the PWM output to ground will correct both situations. Connected with the anode to ground and cathode to the output, it will prevent the output voltage from going excessively below ground, and will also provide a current path. To be effective, the diode selected should have a forward voltage drop of less than 0.3 volts at 200 milliamps. Most 1-to·3 amp diodes exhibit these traits above room temperature. The diode will conduct during the shaded part of the curve shown in figure xx when the voltage goes negative and the current is positive. The current is allowed to circulate without adversely effecting the IC performance. Placing the diode as physically close to the PWM as possible will enhance circuit performance. Circuit implementation of the complete drive scheme is shown in the schematic.
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inductance and parasitic capacitance, in addition to the magnetizing inductance and FET gate capacitance. Circuit implementation is similar to the previous example.
Transformer Coupled Push-Pull MOSFET Drive Circuit
Power MOSFET Drive Circuit
PGND
UC3611 Quad Schottky Diode Array ·
Figure 13.
01 .D2: UC3611 Schottky Diodes
Figure 11. Transformer driven circuits also require the use of the Schottky diodes to prevent a similar set of circumstances from occurring on the PWM outputs. The ringing below ground is greatly enhanced by the transformer leakage
Transformer Coupled MOSFET Drive Circuit
D1 .D2: UC3611 Schottky Diode Array
Figure 12.
Peak Gate Current and Rise Time Calculations
Several changes occur at the MOSFET gate during the turn-on period. As the gate threshold voltage is reached, the effective gate input capacitance goes up by about
fifteen percent, and as the drain current flows, the capacitance will double. The gate-to-source voltage remains fairly constant while the drain voltage is decreasing. The peak
gate current required to switch the MOSFET during a spec-
ified turn-on time can be approximated with the following
equation.
I pk = ~ { Ciss [ (2.5 · Vgth) + Id] + [Crss (VDD-Vgth) J l
Ton
gm
Several generalizations can be applied to simplify this equation. First, let Vgth, the gate turn-on threshold, equal 3 volts. Also, assume gm equals the drain current Id divided by the change in gate threshold voltage, dVgth. For most applications, dVgth is approximately 2.5 volts for utilization of the FET at 750/o of its maximum current rating. In most off-line power supplies, the gate threshold voltage is a small percentage of the drain voltage and can be eliminated from the last part of the equation. The formulas to determine peak drive current and turn-on time using the FET parameters now simplify to:
I pk = ~ · { (10 · Ciss) + (Crss · V drain) }
Ton
Ton = ~ · [ (10 · Ciss) + (Crss · Vdrain) }
I pk
Switching times in the order of 50 nanoseconds are attainable with a peak gate current of approximately 1.0 amps in many practical designs. Higher drive currents are obtainable using most Unitrode current mode PWMs which can source and sink up to 1.5 amps peak (UC1825). Driver ICs with similar output totem poles (UC1707) are recommended for paralleled MOSFET, high speed applications. SEE APPLICATION NOTE U-118
9-138
APPLICATION NOTE
Ill. SYNCHRONIZATION Power supplies have historically been thought of as "black boxes:· an off-the-shelf commodity by most end users. Their primary function is to generate a precise voltage, independent of load current or input voltage variations, at the lowest possible cost. In addition, end users allocate a minimal amount of system real estate in which it must fit. The major task facing design engineers is to overcome these constraints while exceeding the customers' expectations, attaining high power densities and avoiding thermal management problems. It is imperative, too, that the power supply harmonize and integrate with the system rather than cause catastrophic noise problems and last minute headaches. Products that had performed to satisfaction on the lab workbench powered by well filtered linear supplies may not fare as well when driven by a noisy switcher enclosed in a small cabinet.
Basic power supply design criteria such as the switching frequency may be designated by the system clock or CPU and thus may not be up to the power supply designer's discretion. This immediately impacts the physical size of the magnetic components, hence overall supply size, and may result in less-than-optimum power density. However, for the system to function properly, the power supply must be synchronized to the system clock.
There are numerous other reasons for synchronizing the power supply to the system. Most switching power noise has a high peak-to-average ratio of short duration, generally referred to as a spike. Common mode noise generated by these pulsating currents through stray capacitance may be difficult (if not impossible) to completely eliminate after the system design is complete. Ground loop noise may also be amplified due to the interaction of changing currents through parasitic inductances, resultng in crosstalk through the system. EMI filtering to the main input line is much simpler and more repeatable when power is processed at a fixed frequency.
In addition, multiple power stages require synchronization to reduce the differential noise generated between modules at turn-on. In unison, the converters begin their cycles at the same time, each contributing to common mode noise simultaneously, rather than randomly. This also simplifies peak power considerations and will result in predictable power distribution and losses. Compensation made for voltage drops along the bus bars, produced by both the AC and DC power current components, can be accomplished. Balancing of the loads and power bus losses also contributes to diminishing the differential noise and should be administered for optimum results.
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Operation of the PWM Oscillator In normal operation, the timing capacitor (Ct) is linearly charged and discharged between two thresholds, the upper and lower comparator thresholds. The charging current is determined by means of a fixed voltage across a user selected timing resistance (Rt). The resulting current is then mirrored internally to the timing capacitor Ct at the IC's Ct output. The discharge current is internally set in most PWM designs.
As Ct begins its charge cycle, the outputs of the PWM are initiated and turn on. The timing capacitor charges, and when its amplitude equals that of the error amplifier output, the PWM output is terminated and the outputs turn off. Ct continues to charge until it reaches the upper threshold of the timing comparator. Once intersected, the discharge circuitry activates and discharges Ct until the timing comparator lower threshold is reached. During this discharge time, the PWM outputs are disabled, thus insuring a "dead" time when each output is off.
\ Ver
~
~
SYNC
n
\
UPPETRHRCEOSMHPOALRDA1CR
- ERROR AMPUAER OUTPUT
- LOWER COMPARA10R
n
THRESHOLD
HIGH
DEAIJl1ME I.ml
OUTPUTi A
·OUTPUT
ON OFF
OFF
~
OFF
OUTPUT A OUTPUTB
Figure 14. Voltage Mode Control Normal Operation ·
UPPER
SVNC--,ow---r=H=IGH=i---,ow---1=H=IG=JH- -THRESHOLD
Ver
LOWER
"THRESHOLD
o~ FoN-.,.·-+l.·.. ~--OFF------- OUTPUT A
O~T ~OFF--··-<-1.·..--0N-==::::t.._ OUTPUTS
Figure 15.
The SYNC terminal provides a "digital" representation of the oscillator charge/discharge status and can be utilized as both an input or an output on most PWM's. In instances where no synchronization port is easily available, the timing circuitry (Ct) can be driven from a digital (OV, 5V) logic input rather than in the analog mode. The primary considerations of on-time, off-time, duty cycle and frequency can be encompassed in the digital pulse train. A LJJW logic level input determines the PWM ON time. Conversely, a HIGH;., input governs the OFF time, or dead time. Critical constraints of frequency, duty cycle or dead time can be accurately controlled by a digital signal to the PWM timing cap (Ct) input. The command can be executed by anything from a simple 555 timer, to an elaborate microprocessor
software controlled routine.
9-139
APPLICATION NOTE
Not all PWM IC's have a direct synchronization input/output connection available to the internal oscillator. In these applications, the slave oscillator must be disabled and driven in a different fashion. This approach may also be required when using different PWMs amongst the slave modules with different sync characteristics, or anti-phase signals.
Unfortunately, there are several drawbacks to this method, depending on the implementation. First, the PWM error amplifier has no control over the pulse width in voltage mode control. The error amplifier output is compared to a digital signal instead of a sawtooth ramp, rendering its attempts fruitless. The conventional soft start technique of clamping the error amp output, thereby clamping the duty cycle will not function. With no local timing ramp available, the supply is comp!etely under the direction of the sync pulse source. Should the pulse become latched or removed, the PWM outputs will either stay fully on, or fully off, depending on the sync level input (voltage mode). Also, without the local Ct ramp, the supply will not self-start, remaining off until the sync stream appears. Slope compensation for current mode controlled units requires additional components to generate the compensating ramp. Every supply must be produced as a dedicated master, or slave, and must be non-interchangeable with one another, barring modification. This is only a brief list of the numerous design drawbacks to this "open-ended" sync operation. To circumvent these shortcomings, a universal sync circuit has been developed with the following performance features and benefits:
- Sync any PWM to/from any other PWM - Sync any PWM to/from any number of other PWMs - Sync from digital levels for simple system integration - Bidirectional sync signal - Any PWM can be master or slave with no modifications - Each control circuit will start and run independently
of sync if sync signal is not present - Localized ramp at Ct for slope compensation - No critical frequency settings on each module - High speed - minimum delays - High noise immunity - Low power requirements - Remote off capability - Minimal effect on frequency, duty cycle, and dead time - Low cost and component count - Small size
Sync Circuit Operating Principles These optimal objectives can be obtained using a combination of both analog and digital signal inputs. The timing capacitor Ct input will be used as a summing junction for the analog sawtooth and digital sync input. The PWM is allowed to run independently using its own Rt and Ct components in standard configuration. When synchronization is required, a digital sync pulse will be superimposed on the Ct waveform.
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Wher1 applied, the sync pulse quickly raises the voltage at Ct above the PWM comparator upper threshold. This forces a change in the oscillator charge/discharge status and operation. The oscillator then begins its normal discharge cycle synchronized to the sync signal. This digital sync pulse simply adds to the analog Ct waveform, forcing the Ct input voltage above the comparator upper threshold.
/
Ver ,..,/"'\(\ANALOG~ )
~ UPPER
THRESHOLD,
n -v' VsYNC /
Ver LOWER
__JL(DIGITAL) COMBINED THRESHOLD
Figure 16.
In practice, this approach is best implemented by bringing Ct to ground through a small resistance, about 24 ohms. This low value was selected to have minimal offset and effects on the initial oscillator frequency. The sync pulse will be applied across the 24 ohm resistor. Since all PWMs utilize the timing capacitor in their oscillator section, it is both a convenient and universal node to work with.
SYNC CIRCUIT INPUT
PWM
240
Figure 17. Sync Circuit Implementation
Oscillator Timing Equations The oscillator timing components must be first selected to guarantee synchronization to the sync pulse. The sawtooth amplitude must be lower than the upper threshold voltage at the desired sync frequency. If not, the oscillator will run in its normal mode and cross the upper threshold first, before the sync pulse. This requirement dictates that the PWM oscillator frequency must be lower than the sync pulse frequency to trigger reliably. Typically, a ten percent reduction in free running frequency can be accommodated throughout the power supply. Adding the sync circuit will have minor effects on the PWM duty cycle, deadtime and ramp amplitude. (These will be examined in detail.)
9-140
APPLICATION NOTE
The Timing Ramp As mentioned, the timing ramp amplitude needs to be approximately ten percent lower in frequency than normal. Therefore, the MINIMUM sync pulse amplitude must fill the remaining ten percent of the peak-to-peak ramp amplitude to reach the upper threshold. Synchronization can be insured over a wide range of frequency inputs and component tolerances by supplying a slightly higher amplitude sync pulse.
Lowering the peak-to-peak charging amplitude also lowers the peak-to-peak discharge amplitude. This shortens the time required to discharge Ct since it begins at a lower potential. Consequently, this reduces the deadtime accordingly. However, the sync pulse width adds to the IC generated deadtime and increases the effective off, or deadtime due to discharge. This sync pulse width need only be wide enough to be sensed by the IC comparator, which is fairly fast. Additional sync pulse width increases deadtime which can be used to compensate for the 10% lower ramp, hence deadtime.
VTH -J£:..------+--'- ---t----;---"tVTH -
VTH +
VTH+
VTH --I""-----+-.>-+
ToNi------+-+i ToN"1----+< ATON
CHARGING RAMP
DISCHARGING RAMP
Figure 18. Oscillator Ramp Relationships
Oscillator Ramp Equations The timing components required in the oscillator section are generally determined graphically from the manufacturers' data sheets for frequency and deadtime versus Rt and Ct. While fine for most applications, a careful examination of the equations is necessary to analyze the impacts of the additional sync circuit components on the timing relationships.
Oscillator Charging Ramp Equations
AVosc = J..J1chgdT = I chg] t T
Ct
Ct O
T chg = [ AV osc · Ct ] I lchg where lchg = Vchg I Rt AV osc = Vth upper - Vth lower
AV osc' = AV osc (!chg') - V (24 ohm) t chg(o)
V (24 ohm) = I chg · 24 = [Vchg I Rt] · 24
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These equations can be reduced if an approximation is made that the deadtime is very small in comparison to the total period. In this case, the entire effect of changing the ramp voltage is upon the charging time of the oscillator. Synchronizing to a higher frequency simply reduces the charging time of Ct, {Tchg). The new charging time (Tchg') 1s the original charge time multiplied by the change in frequency between F original and F sync. This relative change will be used in several equations; it is labelled P, for percentage of change.
T chg· = 1 sync = F orig = P "relative F change"
T chg(o) T orig F sync
For small values of charging current, or large values of Rt, the voltage drop across the 24 ohm resistor is negligible. A current of 2 milliamps will result in a 2.5% timing error with a 2 volt peak to peak oscillator ramp at Ct. It is also preferrable to free-run the IC oscillator at about a 15% lower frequency than the synchronization frequency, where "P" = 0.85.
AVosc' (sync) = AVosc(o) · P = 0.85 · A[Vosc) orig.
T chg' = T chg(o) · P = 0.85 T chg(o)
V sync (minimum) amplitude = A [Vose) · (1-P) = 0.15 · A [Vosc(o))
With an approximate 2 volt peak to peak oscillator amplitude, the minimum sync pulse amplitude is 0.30 volts for synchronization to occur with a 15% latitude in frequencies.
Oscillator Discharge Ramp Equations Proper deadtime control in the switching power stage is required to safeguard against catastrophic failures. Adding the sync circuit to the oscillator reduce9 the discharge time of the timing capacitor Ct, hence reducing the deadtime of the PWM. There are two contributing factors. First, the peakamplitudeatthetimingcapacitoris lowered by AV osc(o) - AVosc', and the capacitor begins its discharge from a lower potential. Second, the 24 ohm resistor adds an offset voltage, dependent on its current. Typical IC discharge currents range from approximately 6 to 12 milliamps. This offset due to charging current (1-2 ma) is low in comparison to that of the discharge current (6 to 12 ma). While negligible during the charge cycle, its tenfold effects must be taken into account during the discharge, or deadtime.
The discharge time (T dchg) can be calculated knowing the discharge current of the particular IC. More convenient is to use the manufacturers' published deadtime listing for a known value of Ct, and to calculate the effects of the sync circuit. The discharge current has been averaged to 8 milliamps for brevity.
AV dschg' = [AVdchg(o) · P) - V (24 ohm) = [0.85 · AVosc(o)] - 0.2 volts
T dchg' = T dchg(o) - T loss (24 ohms) where T dchg(o) = initial deadtime from curve
= T dchg(o) ·[AV dchg' I AVosc(o)]
9-141
APPLICATION NOTE
The actual deadtime is a summation of both the discharge time of Ct and the width of the sync pulse. While being applied, the sync pulse disables the PWM outputs and must be added to the discharge time. The sync pulse width can be used to compensate for the "lost" deadtime, or as a deadtime extension.
T dead' = T dchg' + T sync pulse width
Top Trace: Master :Cr
Center Trace: Clock Output
Bottom Trace: V Sync Output
U-111
FOSC = 1 MHz
Figure 21. Circuit Timing Waveforms
Figure 19. Sync Circuit Schematic
Operating Principles A positive going signal is input to the base of transistor Q1 which operates as an emitter follower. The leading edge of the sync signal is coupled into the base of Q2 through capacitor C1, developing a voltage across R4 in phase with the sync input. This signal is driven through C2 to the slave timing capacitor and 24 ohm resistor network, forcing synchronization of the slave to the master. This high speed pulse amplifier circuit adds a minimum of delay ("" 50 ns) between the master to slave timing relationship.
Top Trace: Master Clock Output
Bottom Trace: Slave Clock Output
Both: 1 V/CM, 20 ns/CM
Top Trace: Clock Input
Center Trace: Base-to-Ground Voltage at 02
Bottom Trace: Output Voltage into 8ohms
Vertical: 1 Volt/CM
Horizontal:
FOSC = 1 MHz
Figure 20. Sync Circuit Waveforms
This photo displays the waveforms of the sync circuit in operation at a clock frequency of 1 megahertz. The top trace is the circuit input, a 2.5 volt peak-to-peak clock output signal from the UC3825 PWM. Any of several other PWMs can be used as the source with similar results at lower frequencies. The center trace depicts the base to ground voltage waveform attransistor Q2, biased at3 volts. The lower trace displays the output voltage across R4 while driving three slave modules, or about 8 ohms from the 5 volt reference.
Figure 22. Sync Circuit Delay; Input to Output
Trace 1: Master
Trace 2: Slave 1
Trace 3: Slave 2
Trace 4: Slave 3 Vertical: 1V/CM All
Horizontal:
Fo = 1 MHz
Figure 23. Oscillator Waveforms: Master and Slaves
9-142
APPLICATION NOTE
Trace 1: Master Trace 2: Slave 1 Trace 3: Slave 2 Trace 4: Slave 3
Vertical: 1 V/CM All
Horizontal: 20 ns/CM
Figure 24. 'fypical Sync Delay at C1: Master to Slaves
Synchronization ranges for the slaves were discussed in the previous text. The 1 volt sync pulse will accommodate most ranges in frequency due to manufacturers' tolerances. The following photo is included to display the outcome of trying to use the sync circuit on slaves with oscillator frequencies set beyond the sync circuit range. The upper trace is the master Ct waveform. The center trace is Ct of a slave free-running at approximately one half that of the master. The sync pulse alters the waveform, however does not bring it above the comparator's upper threshold to force synchronization. The lower trace shows a slave free running at approximately twice that of the master's oscillator. In this instance, the sync pulse forces synchronization at alternate cycles to the master.
Top Trace: Master Cr
FOSC = 1.0 MHz
Center Trace: Slave 1 FOSC = 500 KHz
Bottom Trace: Slave 2 FOSC = 1.7 MHz
Vertical: 1 V/CM All
Horizontal: 250 ns/CM
Figure 25. Nonsynchronous Operation
For voltage mode control, the free-running frequencies of the oscillator should be set as close to the master as tolerances will allow. One of the consequences of not doing so is the reduced amplitude of the Ct waveform, resulting in a lower dynamic range to compare against the error amplifier output. The top trace in the following photo shows that slave 1 has a much smaller ramp than slave 2, the lower
U-111
trace. The amplitude should be made as large as possible to enhance circuit performance.
Top Trace: Slave 1
dV Ramp = 1.25V T
FOSC < FSync dV1i
Tl Center Trace: Slave 2
J_ dV Ramp = 1.75V dV2
FOSC = FSYNC
Bottom Trace: Sync
Figure 26. CT Ramp Amplitude Waveforms
Sync Pulse Generation from the Osclllator Ct Waveform Not every PWM IC is equipped with a sync output terminal from the oscillator. This is certainly the case with most low cost, mini-dip PWMs with a limited number of pin, like the UC1842/3/4/5. These ICs can provide a sync output with a minimum of external components. Common to all PWMs of interest is the timing capacitor, Ct, used in the oscillator frequency generation. The universal sync circuit previously described triggers from the master deadtime, or Ct discharge time. A simple circuit will be described to detect this falling edge of the Ct waveform and generate the sync pulse required to the slave PWM(s).
~ Cr
Figure ZT. Sync Pulse Generator Circuit
Operating Principles Transistor 01 is an emitter follower to buffer the master oscillator circuit, and capacitively couples the falling edge of the timing waveform to the base of 02. Since the rising edge of the waveform is typically ten or more times slower, it does not pass through to 02, only the falling edge, or deadtime pulse is coupled. Transistor 02 inverts this sync signal at its collector, which drives 03, the power stage of this circuit. Similar to the universal sync circuit, the slave oscillator sections are driven from Q3's emitter. This circuit is useable to several hundred kilohertz with a minimum of delays between the master and slave synchronization relationship.
9-143
APPLICATION NOTE
Top Trace: Circuit Input
Bottom Trace: Circuit Output Across 24 Ohms
Vertical: 0.5 V/CM Both
Horizontal: 0.5 ,.S/CM
Figure 28. Operating Waveforms at 500 KHz
U-111
simply pulling the error amplifier output below the lower threshold of the PWM comparator of approximately 0.5 volts. This can be easily implemented via an NPN transistor placed between the E/A output and ground, used to short circuit the E/A output to zero volts. In most cases, this node is internally current limited to prevent failures. Another scheme is to pull the current limit or current sense input above its upper threshold. A small transistor from this input to the reference voltage will fulfill this requirement.
ACTIVE LOW
TTL/CMOS
VREF PWM
ILtM
Top Trace: Slave CT
Bottom Trace: Master CT
Vertical: 0.5 V/CM Both
Horizontal: 0.5 ,.S/CM
Figure 29. Master/Slave Sync Waveforms at CT
IV. EXTERNALLY CONTROLLING THE PWM Many of today's sophisticated control schemes require external control of the power supply for various reasons. While most of these requirements can be incorporated quite easily with a full functioned control chip, (typical of a 16 pin device), implementation may be more complex with a low cost, 8 pin PWM. Circuits to provide these functions with a minimum of external parts will be highlighted.
Shutdown One of the most common requirements is to provide a complete shutdown of the power supply for certain situations like remote on/off, or sequencing. Typically, a TIL level input is used to disable the PWM outputs. Both voltage and current mode control ICscan perform this task by
A. NONLATCHING Figure 30. PWM Shutdown Circuits
ACTIVE HIGH
1K 1K
E/AOUTPUT PWM
GND
B. NONLATCHING
Figure 31.
Latching Shutdown For those applications which require a latching shutdown mechanism, an SCR can be used in conjunction with the above circuits, or in lieu of them. The SCR can also be placed from the PWM E/A output to ground, provided the PWM E/A minimum short circuit current is greater than the maximum holding current of the SCR, ·and the voltage drop at l(hold) is less than the lower PWM threshold.
9-144
APPLICATION NOTE
VREF PWM
IUM
C. LATCHING
Figure32.
Soft Start Upon power-up, it is desirable to gradually widen the PWM pulse width starting at zero duty cycle. On PWMs without an internal soft start control, this can be implemented externally with three components. An R/C network is used to provide the time constant to control the I limit input or error amplifier output. A transistor is also used to isolate the components from the normal operation of either node. It also minimizes the loading effects on the R/C time constant by amplification through the transistors gain.
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Variable Frequency Operation Certain topologies and control schemes require the use of a variable frequency oscillator in the controlling element. However, most PWMs are designed to operate in a fixed frequency mode of operation. A simple circuit is presented to disable the ICs internal oscillator between pulses, thus allowing variable frequency operation.
Internal at the ICs timing resistor (Rt) terminal is a current mirror. The current flowing through Rt is duplicated at the Ctterminal during the charge cycle, or "on" time. When the Rt terminal is raised to V ref (5 volts), the current mirror is turned off, and the oscillator is disabled. This is easily switched by a transistor and external logic as the control element, for example, a pulse generator. The PWM'stiming resistor and capacitor should be selected for the maximum "ON" time and minimum "DEAD" time of the PWM output(s). The rate at which the PWM oscillator is disabled determines the frequency of the output(s).
The frequency can be varied in two distinct fashions depending on the desired control mode and trigger source. The "off" time of both outputs will occur on a pulseby-pulse basis when the PWM outputs are OR'd to the trigger source. In this configuration either output initiates the "off" time, triggered by its falling edge. The PWM output A is activated, then both outputs A and B are low during the "off" time of the pulse generator. This is followed by output B being activated, then both outputs A and Blow again during the next "off" time. This cycle repeats itself at a frequency determined by the pulse generator circuitry.
Another method is to introduce the "off" time after two (alternate A, then B) output pulses. Output A is activated, followed immediately by output B, then the desired "off" time. The pulse generator circuitry is triggered by the PWM's falling edge of output B. The specific control scheme utilized will depend on the power supply topology and control requirements.
VREF 2K
PWM Rss
2K
E/AOUTPUT
PULSE GENERATOR
=
B. USINGE/A Figure33.
Figure 34. Oscillator Disable Circuit Variable Frequency Operation
9-145
APPLICATION NOTE
VOLTAGE CONTROLLED OSCILLATOR GENERAL CONFIGURATION
VARIABLE FREQUENCY OPERATION FIXED 50% DUTY CYCLE
OSCILLATORS WITH SINGLE PIN PROGRAMMING
E/AINV INPUT
C FDBK R FDBK
5V REF
RT
SHUTDOWN INPUT
SOFT START CIRCUIT
UC3851 I UC3844A I UC3845A *GROUND RAMP OR CURRENT SENSE INPUT
OSCILLATORS WITH SEPARATE RT & CT PINS
E/AINV INPUT
CFDBK RFDBK
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At the beginning of an oscillator cycle, Ct begins charging and the PWM output is turned on. Transistor 01 is driven from the output and also turns on with the PWM output, thus discharging Ct and pulling th.is node to ground. As this occurs, the oscillator is "frozen" with the PWM output fully ON. On-time can be controlled in the conventional manner by comparing the error amplifier output voltage with the current sense input voltage. This results in a current controlled "on-time" and fixed "off-time" mode of operation. Other variations are possible with different inputs to the current sense input. When the PWM output goes low (off), transistor01 also turns off and Ct begins charging to its upper threshold. The off-time generated by this approach will be longer for a given Rt/ Ct combination than first anticipated using the oscillator"charging" equations or curves. Timing capacitor Ct now begins charging from Vsat of 01 (approx. OV) instead of the internal oscillator lower threshold of approximately 1 volt.
FIXED "OFF-TIME", CURRENT CONTROLLED "ON-TIME"
OUTPUT UC3842/3
VREF
TO
ISENSE CIRCUITRY
(PIN 3)
GND
SCHEMATIC
CFILTER
CURRENT LIMIT/
RT
SHUTDOWN INPUT
l SOFT START
CSS
UC3823 I UC3825 I UC3846 I UC3847 *GROUND RAMP OR CURRENT SENSE INPUT USE NONINV E/A INPUT FOR REVERSE V/F OPERATION
Fixed "Off-Time" Applications Obtaining a fixed "off-time" and a variable "on-time" can easily be accomplished with most current-mode PWM IC's. In these applications, the RV Ct timing components are used to generate the "off-time" rather than the traditional "ontime." Implementation is shown schematically in Figure 3 along with the pertinent waveforms.
OUTPUT
OFF
OFF
+- - PEAK - -
_! - +- - - -
OSC.
I
I
VALLEY - - -
VSAT01 --~
Ov - - - - - - - - - - - -
WAVEFORMS Flgure35.
9-146
APPLICATION NOTE
Current Mode ICs Used In Voltage Mode Most of today's current mode control ICs are second and third generation PWMs. Their features include high current output driver stages, reduced internal delays through their protection circuitry, and vast improvements in the reference voltage, oscillator and amplifier sections. In comparison to the first generation ICs (1524), numerous advantages can be obtained by incorporating a second or third generation IC (18XX) into an existing voltage mode design. In duty cycle control (voltage mode}, pulse width modulation is attained by comparing the error amplifier output to an artificial ramp. The oscillator timing capacitor Ct is used to generate a sawtooth waveform on both current or voltage mode ICs. To utilize a current mode chip in the voltage mode, this sawtooth waveform will be input to the current sense input for comparison to the error voltage atthe PWM comparator. This sawtooth will be used to determine pulse width instead of the actual primary current in this method.
1N 4148
2N 2222
2.?k
1k
U-111
VI. FULL DUTY CYCLE (100%) APPLICATIONS Many of the higher power (>500 watt) power supplies incorporate the use of a fan to provide cooling for the magnetic components and semiconductors. Other users locate fans throughout a computer mainframe, or other equipment to circulate the air and keep temperatures from skyrocketing. In either case, the power supply designer is usually responsible for providing the power and control.
The popularity of low voltage DC fans has increased throughout the industry due to the stringentagency safety requirements for high voltage sections of the overall circuit. In addition, it's much easier to satisfy dual AC inputs and frequency stipulations with a low cost DC fan, powered by a semi-regulated secondary output.
The most efficient way to regulate the fan motor speed (hence temperature) is with pulse width modulation. An error signal proportional to temperature can be used as the control voltage to the PWM error amplifier. While nearly full duty cycle can be easily attained, the circumstances may warrant full, or true 1000/o duty cycle.
This condition is highly undesirable in a switch-mode power supply, therefore most PWM IC designs have gone to great extent to prevent 1000/o duty cycle from occurring. There are simple ways to over-ride these safeguards, however. One method, presented below, "freezes" the oscillator and holds the PWM output in the ON, or high state when the circuit is activated. Feedback from the output is required to guarantee that the oscillator is stopped while the output is high. Without feedback, the oscillator can be nulled with the output in either state.
+12V
Figure 36. Current Mode PWM Used as a Voltage Mode PWM
Compensation of the loop is similar to that of voltage mode, however, subtle differences exist. Most of the earlier PWMs (15xx) incorporate a transconductance (current) type amplifier, and compensation is made from the E/A output to ground. Current mode PWMs use a low output resistance (voltage) amplifier and are compensated accordingly. For further reference on topologies and compensation, consult "Closing the Feedback Loop'' listed in this appendix.
FULL DUTY SWITCH Figure 37. Full Duty Cycle Implementation
9-147
APPLICATION NOTE
U-111
VII. HIGH EFFICIENCY START-UP CIRCUITS
Theory of Operation
FOR BOOTSTRAPPED POWER SUPPLIES
Prior to applying the high voltage DC, capacitor C1 is dis-
Many pulse width modulator I.C.s have been optimized for charged; switches 01, 02 and the main converter are off.
offline use by incorporating an under-voltage lockout cir- As the input supply voltage 0fdc) rises, resistors R1 and R2
cuit. Demanding only a milliamp or two until start-up, the
auxiliary supply voltage 01 aux) can be generated by a sim-
form a low current voltage divider. The voltage developed across R2 rises accordingly with +V de until switch 01
ple resistor/capacitor network from the high voltage de rail turns on, thuschargingC1 thru R start-up from +V de. This
(+V de). Once start-up is reached, the auxiliary power is continues as the UV lockout threshold of the I.C. is reached
supplied by means of a "boostrap" winding on the main and the main converter begins operation. Energy is deli-
transformer.
vered to C1 from the bootstrap winding in addition to that
While the start-up requirements are quite low, losses in the supplied through R start-up.
resistor to the high voltage DC can be significant in steady
state operation. This is especially true for low power ( < 35
After several cycles, the auxiliary voltage rises with the main converters increasing pulse width, typical of a soft-start rou-
watt) applications and circuits with high voltage rails (400 tine. Current flows through zener diode D1 and develops a
volts DC, for example). Oncethemainconverteris running, voltage across the 02's biasing resistor, R3. Transistor 02
switching the start-up resistor out of circuit would increase turns on when the auxiliary voltage reaches V zener plus
efficiency substantially. Circuits have been developed to 02's turn on threshold. As this occurs, transistor 01 is
use either bipolar or MOSFET transistors as the switch to turned off, thus eliminating the start-up resistor from the cir-
lower the start-up circuit power consumption, depending cuit power losses. In most applications, the auxiliary vol-
on the application. Selection can be based on optimizing tage is optimized between 12 and 15 volts for driving the
circuit efficiency (MOSFET) or lowest component cost main power MOSFETs, while keeping power dissipation in
(bipolar). The overall improvement in power supply effi- the PWM IC low.
ciency suggests this circuitry is a practical enhancement. If the main converter is shut down for some reason, Vaux
The high efficiency start-up circuit shown in figure 1 utilizes will decay until 02 turns off. Transistor 01 then turns back
two NPN bipolar transistors to switch the start-up resistor in on, and C1 is charged through R start-up from the high vol-
and out of circuit. It can be used in a variety of applications tage DC, as during start-up.
with minor modifications, and requires a minimum of com- NOTE: SEE DESIGN NOTE DN-26 FOR ADDITIONAL
ponents. Figure 2 displays a similar circuit utilizing N CIF!gl.JITS.
channel MOSFET devices to perform the switching.
+
90190VDC
RSTART (1K)
UPTA520
VIII. CURRENT MODE HALF BRIDGE APPLICATIONS As previously described (1), current mode control can cause a "runaway" condition when used with a "soft" cen-
+
C1N I 02
N2222
2K
01
R2
VAUX
D1 +
UZ712
R3
C1
FROM BOOTSTRAPPED
WINDING
2K
tered primary power source. The best example of this is the half bridge converter using two storage capacitors in series from the rectified line voltage. For 110 VAC operation, the input is configured as a voltage doubler, and one of the AC inputs is tied directly to the storage capacitor's centerpoint. This is considered a "stiff" source, since the centerpoint will remain at one-half of the developed voltage between the
upper and lower rail. However, during 220 VAC inputs, a
Figure 38. NPN Switches
bridge configuration is used for the input rectifiers, and the capacitors are placed in series with each other, across the
(90 - 190v)
+
+ Voe
RsrART ""2K
bridge. Their centerpoint potential will vary when different amounts of charge are removed from the capacitors. This is generally caused by uneven storage times in the switching transistors 01 and 02.
C1N
+
01 IRFD210 FROM
STIFF CENTERPOINT
BOOTSTRAPPED WINDING
l
IRFD210
110
01
02----
· Np
R3 3.9K
VAC
Figure39.
9-148
Figure40.
APPLICATION NOTE
SOFT CENTERPOINT
c,
220
o,
· Np
VAC
U-111
·
·
Figure41. The centerpoint voltage can be maintained at one-half +Vdc by the use of a balancing technique. In normal operation, transistor 01 turns on, and the transformer primary is placed across one of the high voltage capacitors, C1 for example. On alternate cycles the transformer primary is across the other cap, C2. An additional balancing winding, equal in number in turns to the primary, is wound on the transformer. It is connected also to the capacitor centerpoint at one end and thru diodes to each supply rail at the other end. The phasing is such that it is in series with the primary winding through the ON time of either transistor 01 or 02. +350 ---------------~
Figure 42. Schematic - Balancing Winding In this configuration, the center point of the high voltage caps is forced to one-half of the input DC voltage by nature of the two series windings of identical turns. Should the midpoint begin to drift, current flows thru the balancing winding to compensate.
+
Figure 44. Transistor Q2 On
In most high frequency MOSFET designs, the FET mismatches are small, and the average current in the balancing winding is less than 50 milliamps. A small diameter wire can be wound next to the larger sized primary for the balancing winding with good results.
IX. PARALLELING CURRENT MODE MODULES One of the numerous advantages of current mode control is the ability to easily parallel several power supplies for increased output power. This discussion is intended as a primer course to explore the basic implementation scheme and design considerations of paralleling the power modules. Redundant operation, failure modes and their considerations are not included in this text.
The prerequisites for parallel operation are few in number, but important to insure proper operation. First, each power supply module must be current mode controlled, and capable of supplying its share of the total output power. All modules must be synchronized together, and one unit can be designated as the master for the sake of simplicity. All remaining units will be configured as slaves.
The master will perform one function in addition to generating the· operating frequency. It provides a common error voltage 0Je) to all modules as the input to the PWM comparator. This voltage is compared to the individual module's primary current at its PWM comparator. The slaves are utilized with their error amplifier configured in unity gain. Assume there are identical primary current sense resistors in each module, and no internal offsets in the ICs amplifiers or other circuit components. In this case, the output voltages and currents of each module would be identical, and the load would be shared equally among the modules.
Figure 43. Transistor Q1 On
VR = Ip · Rs (±5%) ERROR AMPLIFIER Figure 45. PWM Diagram
9-149
APPLICATION NOTE
In reality, small offets of ± 10 millivolts exist in each PWM amplifier and comparator. As the common error voltage, 0fe) traverses through the IC's circuitry, its accuracy decreases by the number and quality of gates in its path. The maximum error occurs at the lowest common mode amplifier voltage, approximately 1 volt. The ± 20 millivolt offset represents a ± 2% error at the PWM comparator. At higher common mode voltages, typical of full load conditions, the error voltage 0fe) is closer to its maximum of 4 volts. Here the same ± 20 millivolts introduces only ± 0.5% error to the signal.
The other input to the PWM comparator, Vr, is the voltage developed by the primary current flowing through the current sense resistor(s). In many applications, a5%tolerance resistor is utilized resulting in a ± 5% error at the PWM comparator's "current sense" or ramp input.
Pulse width is determined by comparing the error voltage 0fe) with the current sense voltage, 0fr). When equal, the primary current is therefore the error voltage divided by the current sense resistance; Ip = Ve/Rs. Output current is related to the primary current by the turns ratio (N) of the transformer. Sharing of the load, or total output current is directly proportional to the sharing of the total prim·ary current. The previous equations'and values can be used to determine the percentage of sharing between modules.
U-111
Primary current, Ip = Ve/Rs. Introducing the tolerances, Ip' = Ve (±2%) I Rs (±5%); therefore Ip' = Ip(± 7%) The primary currents (hence output currents) will share within ±seven percent (7%) of nominal using a five percent sense resistor. Clearly, the major contribution is from the current sense circuitry, and the PWM IC offsets are minimal. Balancing can be improved by switching to a tighter tolerance resistor in the current sense circuitry.
The control-to-output gain (K) decreases with increasing load. At high loads, when primary currents are high, so is the error amplifier output voltage, 0fe). With a typical value offour volts, the effects of the offset voltages are minimized. This helps to promote equal sharing of the load at full power, which is the intent .behind paralleling several modules.
For demonstration purposes, four current mode push-pull power supplies were run in parallel at full power. The primary current of each was measured (lower traces) and compared to a precision 1 volt reference (upper trace). The voltage differential between traces is displayed in the upper right hand corner of the photos. Using closely matched sense resistors, the peak primary currents varied from a low of 2.230A to 2.299 amps. Calculating a mean value of 2.270 amps, the individual primary currents shared within two percent, indicative of the sense resistor tolerances.
1.000\/
Unit 1
Unit2
Unit3
Figure 46. Primary Currents - Parallel Operation
Unit4
9-150
APPLICATION NOTE
Other factors contributing to mismatch of output power are the individual power supply diode voltage drops. The output choke inductance reflects back to the primary current sense, and any tolerances associated with it will alter the primary current slope, hence current. In the control section, the peak-to-peak voltage swing atthetiming capacitor Ct effects the amount of slope compensation introduced, along with the tolerance of the summing resistor. These must all be accounted forto calculate the actual worst case current sharing capability of the circuit.
U-111
Cables should be of equal length, originating at the master and routed away from any noise sources, like the high voltage switching section. All input and output power leads should be exactly the same length and wire gauge, connected together at ONE single point. Leads should be treated as resistors in series with the load, and deviations in length will result in different currents delivered from each module.
MASTER
,----i+VIN
Top Trace: VE: Error Voltage with Noise
Lower Trace: VR: Primary
Current
PARALLEL
OPERIU'JON
L
EQUAL LEAD
D
LENGTHS FROM
A
MASTER AND -V1N
D
&J'~~&~~~§L
~--.... -VIN
Figure48.
Figure 47. Noise Modulating VE
Proper layout of all interconnecting wires is required to insure optimum performance. Shielded coax cable is recommended for distributing the error voltage among the modules. Any noise on this line will demonstrate its impact at the PWM comparator, resulting in poor load sharing, or jitter.
Unitrode Integrated Circuits Corporation
7 Continental Boulevard.· P.O. Box 399 ·Merrimack, New Hampshire· 03054-0399
Telephone 603424-2410 · FAX 603-424-3460
9-151
n nINTEGRATED
~CIRCUITS
-UNITRDDE
APPLICATION NOTE
U-112
A HIGH PRECISION PWM TRANSCONDUCTANCE AMPLIFIER FOR MICROSTEPPING USING UNITRODE'S UC3637
INTRODUCTION
If you ask a designer why he has chosen a stepping motor for a given application, chances are that his answer will include something about "open loop positioning." Stepping motors can provide accurate positioning without expensive position sensors and feedback loops, and this fact alone results in large savings.
are prone to behave erratically under certain conditions; for example, when the stepping rate is such as to excite a mechnical or electro-mechanical resonant mode. Furthermore, although the angular increments may be small-especially when half-stepping is used-the positioning resolution is restricted to a finite number of discrete points.
But there is more: steppers are tough and durable, easy to use, and high in power rate. And if you want to close a feedback loop around them, you can do that, too.
Still, there are certain problems. Steppers are incremental motion machines, and as such they tend to be noisy and
Therefore, this question arises: "Is there a method of driving stepping motors such that the resulting movement is smooth and quiet-that is, essentially continuous, as opposed to incremental? And would this result in improved positioning resolution?" We will try to answer these questions here.
r
HOLDING TORQUE AND DETENT TORQUE
· · · · - ~ TORQUE DUE TO THE CURRENT
DETENT TORQUE
r
SINUDOIDAL HOLDING TORQUE
LOW DETENT TORQUE
2 x TORQUE LOSSES
Figure 1. Static Torque Curves of Two Hybird Steppers
STATIC TORQUE CURVES
0017-1
The curves in Figure 1 illustrate how a stepping motor torque behaves as a function of rotor angle. The detent torque component is a consequence of the magnetic field produced by the rotor magnet (or magnets), and is present with or without phase currents applied. It can be seen that this component contributes a fourth harmonic distortion to the static torque curves. The energized torque curves, in general, have additional harmonic components, mostly the third and fifth. Note that the two motors depict-
ed in Figure 1 have very different characteristics in this respect. The distortion observed in the static torque characteristic is of no great consequence in the more usual applications of stepping motors, using either full step or half step sequences. It is when we start thinking about increasing the positioning resolution of these motors by some method of apportioning currents between the two phases, that we begin to be concerned about the effects of harmonic distortion. Even small amounts of added har-
9-152
APPLICATION NOTE
U·112
monies can have a very noticeable effect on the waveshape, as shown in Figure 2.
1.0 0.9
~ 2
0.8 0.7
~~ ~ ~
3
'"""'
II""
0.6
' I Y 0.5
0.4
(L_
~ 0.3
~ D.2
1. SINUSOID
~0.1
t-
2. +103 3. +203
3RD 3RD
HARMONIC HARMONIC
0.0ao 1ao 2ao 30" 4rJO sao sao 1aoaoo gao
DEGREES 0017-2
Figure 2. Effect of 10% and 20% Harmonic Content
Figure 3 shows the relationship between sine and cosine waveforms, and what it tells us is that if we can get a motor with a sinusoidal static torque characteristio-i.e., with no harmonic components-and drive phase A with a sine current function and phase B with a cosine current function, we would have smooth shaft rotation and accurate positioning at any angle.
Stepping motors having static torque curves with very low harmonic distortion are commercially available today. But most low-priced, mass produced hybrid steppers exhibit torque curves with enough harmonic components to require careful consideration in any attempt to improve resolution by what is known as microstepping. (The name microstepping originates from the fact that the required current waveforms are generated by a digital process that aproximates those waveforms incrementally. With thirty· two or sixty-four increments for an electical angle of Tr 12 radians, the resulting waveforms are hardly distinguishable from true sine or cosine signals.)
If the nonsinusoidal static characteristic of a given motor is known, it is possible to generate appropriate waveshapes for the phase currents so that the resulting torque curve becomes free of distortion, as required. Note that this involves no additional complexities, since it is just as easy-<>r difficult-to synthesize one waveform as anoth· er. Consequently, one can, in principle, linearize any motor for increased resolution and smoothness through microstepping.
Still, it should be noted that the best efficiency is obtained when the phase current waveshapes are undistorted, because of all suitable waveforms, the sine wave has the lowest form-factor.
0017-3
Figure 3. The sum of sine and cosine waveforms is a smoothly rotating vector.
9-153
APPLICATION NOTE
U-112
The form-factor of a waveform is the ratio if its rms to average values. For a sine wave, this ratio is:
0.707 (1) ffs = 0_637 = 1.111
Some manufacturers have used triangular waveforms-'largely because they can be implemented with great simplicity-and it is interesting to note that for such a waveform, the average value is 0.5 VpK, while the rms is 0.577 VPK· Thus the form factor is:
(2) ffr = Q0.5.757 = 1.155
As a consequence, for the same peak power applied to the motor, the rms power of a triangular waveform is 18% less than that of a sine wave, whereas the average current is 21 % less. It follows that microstepping with a triangular waveform does not use the full capabilities of the motor.
The same result is obtained with other-waveforms, as long as the peak power is limited, as it must be.
But regardless of all this, the fact remains that whether our motor has a sinusoidal torque curve or a very distorted one, the thing that will be inevitably required will be two amplifiers capable of converting the synthesized waveform into phase currents at the required power levels. In the next section, we will describe the design of one such amplifier, having a transconductance linearity of better than 1% and capable of delivering phase currents of up to ±6A.
UNITRODE'S UC3637 PWM CONTROLLER
Pulse width modulation (PWM) is a method of power control whose most attractive feature is the high level of efficiency that can be obtained. With careful design, and using power MOSFETs as output switches, one can easily achieve efficiencies higher than 80%.
The Unitrode UC3637 PWM controller, housed in an eighteen-pin DIL package, was originally intended to serve as a PWM amplifier for brush-type PM servomotors. But, because of its ingenious design, the device has found its way into various other uses as well, such as temperature control, uninterruptible power supplies, and even high fidelity sound reproduction. As we shall see, it can also be used in a high performance PWM transconductance amplifier.
BLOCK DIAGRAM AND LOOP EQUATIONS
A block diagram of the current feedback loop under consideration is shown in Figure 4, where the UC3637 is seen to contain the high-gain error amplifier and the main ingre-
dients of the PWM amplifier. Since we are looking for an output of 6A, an H-bridge power stage must be added. The motor current IM is sensed by means of a low value
resistor Rs. and the derived voltage Ve is used to com-
plete the feedback loop. Not shown in the block diagram is the back-EMF voltage, the product of motor shaft speed and Kv. the motor speed constant. Since this term does not contribute to the dynamics of the current feedback loop, it has purposely been left out.
0017-4
Figure 4. Block Diagram of the Complete CurrentControl Loop
The transfer functions of the error amplifier and motor are as follows:
(3)
Vo
-=
1 + sRC
Ve
IM (4) Vs = RM(1 + sTm)
where TM LM/RM, the motor's electrical time-constant (Rs is assumed to be low compared with RM). The forward transfer function is, then:
-KA Ks (1 + sRC) (5) G (s) = sR1 AMC (1 + sTm)
For the feedback transfer functions, we have simply:
(6) H (s) =
Ve
-=
Kc
IM
Thus, for the closed loop,
(7) ~ =
KA Ks (1 + sRC)
V1N KAKsKc(1 +sRC) + sR1RMC(1 + sTm)
9-154
APPLICATION NOTE
U-112
If we make the time-constant RC equal to the motor's time-constant TM· this becomes:
(8) ~ =
KAKs
V1N KAKsKc + sR1RMC
IM
1
(9)-=----
V1N Kc (1 + sT1)
where,
(10) T1 = R1RMC = R1LM KAKsKc KAKsKcR
By making RC = TM· we have eliminated one of the transfer function poles. The resulting closed-loop response, described by (7) has a gain of 1/Kc from w = O tow = 1/T1, and drops at -6 bd/octave thereafter.
DESIGNING THE HARDWARE
In designing circuits intended to handle power, it is customary to start with the output sti;ige. This is surely due to the fact that the power stage is more demanding of the designer's attention and care, whereas the low level circuits are far more adaptable to the requirements of the chosen output configuration.
In the present case, power MOSFETs were chosen for the H-bridge because of their low losses, and because of their compatibility with the UC3637 outputs. Each totempole leg of the bridge is made up of one N-channel and one P-channel device. Such a pair can be driven in many different ways, of which several were considered for this particular design. The method that was finally chosen, shown in Figure 5, requires a few comments.
0017-5
Figure 5. Totem-Pole Leg of Output H-Bridge
The first thing to notice is that the upper MOSFET, transistor OP, has its gate driven through a capacitor, C1. This is not always practical of course, but in the case of a chopper drive combined with a stepping motor, it turns out that a driving signal is always present. At stand-still and at low speeds, it is the chopping rate that appears; at higher speeds, it is the stepping rate itself, or both. The driver is never required to deliver continuous DC (unchopped) to the motor winding, as it would to the armature of a brushtype DC motor at full speed. Consequently, OP never needs to be held in the ON state for more than a few microseconds, and for this the time constant of C1 R4 is adequate. Also, resistor RA in parallel with CR1, together with the gate capacitance of ON, cause this transistor to turn off faster than it turns ON. Since the same thing is done for OP, the problem of cross-conduction is neatly taken care of. The Zener diode CR3 serves as a clamp for the OP gate voltage. Finally, an inhibiting line, INH, is provided as a protection for OP and ON during the power turn-on time, when the + VM voltage is rising and C1 must be charged. An auxiliary circuit senses a positive dVM/dt and holds the INH line low, thus keeping ON OFF during this time.
An important point in favor of this arrangement is that the gate-drive circuit losses are independent of VM and so this voltage can be set anywhere within the Vds rating of the power MOSFETs.
We can now consider the H-bridge with its motor winding load, as shown in Figure 6. The bridge is shown schematically with its driving circuits, but the action is still as shown in Figure 5. For example, when V1N is high, switch S1 is OFF and S3 is ON, and so forth. Furthermore, the opposite side of the bridge is driven by the complementary signal V1N· With V1N low, S1 and S4 will be conducting, and the load current IM will increase in the positive direc-
tion (indicated by the +IM arrow). Similarly, when v1N is
high, both S2 and S3 conduct, causing IM to increase in the negative direction. Remember that the load is inductive, and that inductance is an energy storing element. Therefore, if we have some positive IM. due to S1 and S4 being closed, and we switch to S2 and S3 closed, the previous value of IM will continue to flow "uphill," so to speak, while decreasing. At the time of switching, this current ceases to flow down through sense resistor Rs4 to ground and starts flowing up through Rs3 and back to the supply.
Switches S1 through S4 are able to conduct in either direction when in the ON state-a very neat feature of power MOSFETs. Furthermore, their intrinsic diode protects the devices from reverse voltage pulses during the switching no-overlap transition. Since we wish to control this current very closely in both magnitude and direction, it is
9-155
APPLICATION NOTE
VIN _ _ __
TO ERROR
AMP
U-112
0017-6
Figure 6. H-Bridge Configuration with Bidirectional Current Sensing
now necessary to generate a voltage Ve that gives an accurate indication of the current IM over the full range from maximum positive to maximum negative. This is done by the circuit section of Figure 6 which includes the op-amp A1.
In that circuit, the voltage Vos is meant to offset the output Ve of A1 to some. chosen value that will correspond to IM = 0. The value of Ve can be written as:
(11)Ve = Ves + nlMRs
This offset is necessary when the design requires a single polarity supply, as in our case. When two supply polarities are available for the control circuit, one can simply make Vos = 0. For the single supply case, the nR and Vos combination is implemented by a simple resistor divider from ±Vee to ground (a Thevenin equivalent) of the required impedance and open voltage.
To keep the circuit losses to a minimum, we should use low values for the sense resistors Asa and Rs4. Yet, they need to be accurate and temperature-stable. In our case, having decided on a Ve scale of 0.5V per motor ampere,
we have selected Rs = 0.1 n and a current sense amplifi-
er gain n = 5. We have also set Vos = Vee/2 = 7.5V, so that we will have Ve = 7.5 + 0.5 IM. This means that as the current IM varies from + 6A to - 6A, the analog voltage Ve will vary from +10.5V to +4.5V. At IM = 0, Ve will be equal to 7.5V.
SETTING UP THE PWM CONTROLLER
Having designed the power output stage (H-bridge) and the current-sense circuit, we can proceed to the PWM controller (UC3637) and its external components. The device itself has been described in great detail in its data sheet and in an application note (Publication U-102, available from Unitrode Integrated Circuits Corporation).
In the present design, we use the UC3637 to generate the two H-bridge driving signals V1N and VIN· at the device's output pins 7 and 4, respectively.
Figure 7 shows in block form the internal workings of the device. Since operation from a single + 15V supply is desired, pin 5 will be GROUND and pin 6 will be + 15V. We selected, for the ramp oscillator, a waveform as shown in Figure 8, which fits well in the + 15V headroom given by our Vee supply. The formulas given in Figure 8 show how the various components are calculated.
Next, we set up the two PWM comparators by tying the inverting inputs (pin 1O) of the A comparator, and the noninverting input (pin 8) of the B comparator together and apply the ramp (pin 2) to this line. The remaining comparator inputs (pins 9 and 11) are next connected together to become the PWM input point. It can be seen from the block diagram of Figure 7 that as the control voltage applied to this point varies from + 5V to + 1OV, the duty cycle of the output at pins 4 and 7 also varies. V4 and V7 are complementary signals; and the voltage swing of each of these signals is from a low value between OV and +2V, and a high value between (Vee -2V) and Vee-
9-156
APPLICATION NOTE
U-112
-E/A +E/A
Figure 7. Block Diagram of the UC3637. The two outputs can drive power MOSFETs directly.
0017-7
R1
6
V1
R1
V3
R3
UC3631
V2
lVOLTS - -- - - - - -~ ~~L~;G~ - -
' AT PIN 3 (V3)
1-+_J
-TIME
0017-8
f = ramp frequency
IT =
V10
-
=
V1
-
(should
be about 0.5 mA)
RT RT
then, RT = 2000 V1 (fi)
250 x 10-6
CT = f(V1 - V3) (fd)
Figure 8. Setting up the ramp oscillator requires only five external components.
9-157
APPLICATION NOTE
U-112
..----+--...- -....---4~-.....--~--.VM
+60V MAX.
620K
330K
-· !'..
+15V
NULL ADJ.~
_ 1K 1K
TO NULL: SHORT INPUT TO GROUND & SET NULL
POT TO IM= 0.
Figure 9. PWM Transconductance Amplifier UC3637
0017-9
The error amplifier is used as a source for the control signal. But because its output (pin 17) has a voltage range
greater than the + 5V to + 1OV range of the Vc ramp sig-
nal, and we want to prevent the modulation range from ever reaching 0% or 100% (because of the capacitively coupled P-channel MOSFET devices) we add a simple resistive network consisting of three equal resistors to serve as an attenuator. The final result can be seen in the complete schematic of Figure 9.
CURRENT LIMIT AND CONTROL
The current limit feature of the UC3637 is used to protect the output transistors and motor from excessive current (6A in this case). As the block diagram of Figure 7 shows, the current limit comparator (pins 12 and 13) of the UC3637 is internally biased to a threshold of 200 mV. The network that connects the two sense resistors to pin 12, consisting of two 1K and one 330!l resistors, causes a voltage of 200 mV to appear at pin 12 when the voltage at either sense resistor is about 1V, corresponding to a
current of 1OA. Consequently, the maximum output current will be limited to 1OA. The current feedback loop is closed by feeding the output of the current sense amplifier to pin 16, the inverting input of the error amplifier of the UC3637. An RC time constant of 3.6 msec is used for the zero in· this amplifier's transfer function (equations 8, 9, and 10) which is close to the effective electrical time constant of the motor. Also, a level-shift circuit is provided by means of op amp A2 to permit the use of a control input centered at zero volts, and a control range from - 6A to
+ 6A. The circuit allows this even though the op amp is
powered by a single positive supply.
TEST RESULTS
The design circuit, shown in Figure 9, was breadboarded for testing at Unitrode and also at Portescap. The assembly includes two amplifiers, one for each motor phase and a "power on" auxiliary circuit for protection of the power MOSFETs. The output devices are equipped with small sheet metal heat sinks.
9-158
APPLICATION NOTE
U-112
The circuit draws about 65 mA from the + 15V supply. The power output section operates with a supply ranging from + 20V to + 60V, with no damage occurring if this voltage is lower than +20V.
The circuit performed very well, with excellent linearity and phase matching. The various plots taken, showing output current versus input voltage, are quite straight, and the transconductance is accurate to within 1%. Furthermore, the PWM frequency was subsequently increased to slightly above 100 KHz (by reducing Cr) and the performance re-checked. The result was a marked increase in motor efficiency, due to reduced current ripple, with all other results remaining excellent.
CONCLUSION
Microstepping is a technique of considerable interest in the design of many products, particularly those in which the lower cost of open-loop positioning is an essential parameter. A motor such as Portescap's Model P-750, with its accurately sinusoidal torque curve, becomes even more attractive once its microstepping driver is shown to be fairly simple and inexpensive. The end result is not only precise open loop positioning, but quiet operation, freedom from resonance problems, and excellent electrical efficiency. Incidentally, the motor is available with two quadrature speed sensing coils that can be used for speed and position control, if desired.
Unitrode Integrated Circuits Corporation
7 Continental Boulevard. ·P.O. Box 399 ·Merrimack, New Hampshire· 03054-0399
Telephone 603-424-2410 ·FAX 603-424-3460
9-159
ln.=nJ INTEGRATED CIRCUITS
-UNITRODE
APPLICATION NOTE
U·113
DESIGN NOTES ON PRECISION PHASE LOCKED SPEED CONTROL FOR DC MOTORS
ABSTRACT
There are a number of high volume applications for DC motors that require precision control of the motor's speed. Phase locked loop techniques are well suited to provide this control by phase locking the motor 'to a stable and accurate reference frequency. In this paper, the small signal characteristics, and several large signal effects, of these loops are considered. Models are given for the loop with design equations for determining loop bandwidth and stability. Both voltage and current motor drive schemes are addressed. The design of a loop for a three phase brushless motor is presented.
PHASE LOCKING GIVES PRECISION SPEED CONTROL
The precise control of motor speed is a critical function in today's disc drives. Other data storage equipment, including 9 track tape drives, precision recording equipment, and optical disc systems also require motor speed control. As the storage density requirements increase for these media, so does the precision required in controlling the speed of the media past the read/write mechanism. One of the best methods for achieving speed control of a motor is to employ a phase locked loop.
With a phase locked loop, a motor's speed is controlled by forcing it to track a reference frequency. The reference input to the phase locked loop can be derived from a precision crystal controlled source, or any frequency source with the required stability and accuracy. A block diagram of the phase locked loop is shown in Figure 1.
Kpo (VOLTAGE) Gpo (CURRENT)
ROTATIONAL FEEDBACK
0018-1
Figure 1. PrRlae motor speed control ls obtained by phase locking the motor to a precision reference frequency.
In Figure 1, a precision crystal oscillator's frequency is digitally divided down to provide a fixed reference frequency. Alternatively, the motor could be forced to track a variable frequency source with zero frequency error. The motor speed is sensed by either a separate speed winding or, particularly in the case of the DC brushless motor, a Hall effect device. The two signals, motor speed and reference frequency, are inputs to a phase detector. The detector output is a voltage signal that is a function of the phase error between the two inputs. The transfer function of the phase detector, Kcf>, is expressed in volts/radian. A 1/ s multiplier accounts for the conversion of frequency to phase, since phase is the time integral of frequency.
Following the phase detector is the loop filter. This block contains the required gain and filtering to set the loop's overall bandwidth and meet the necessary stability criteria. The output of the loop filter is the control input to the motor drive. Depending on the type of drive used, voltage or current, the driver will have respectively, a VouTIVIN transfer characteristic, or an louTIV1N transconductance.
At first glance, it seems that the motor has simply replaced the Vea (voltage controlled oscillator), in the classic phase locked loop. In fact, it is a little more complicated. The mechanical and electrical time constants of the motor come into play, making the transfer function of the motor more than just a voltage-in, frequency-out block. In order to analyze the loop's small and large signal behavior it is essential to have an equivalent electrical model for the motor.
A SIMPLE ELECTRICAL MODEL FOR A DC MOTOR
Figure 2 is an electrical representation of a DC motor. The terms used are defined here:
LM Motor winding inductance in hel)ryS RM Motor winding resistance in ns J Total moment of inertia of the motor in Nm-sec2
(Note: 1 Nm = 141.6 oz-in) KT Motor torque constant in Nm/Amp Kv Voltage constant (back EMF) of motor in voltage-
sec/rad (Note: Kv = KT in SI units)
9-160
APPLICATION NOTE
U-113
0018-2
'N ~ Number of speed sense cycles per motor revolution
Figure 2. This simple electrical model is useful for determining the small and large signal characteristics of the motor. Capacitor, CM is used to model the mechanical energy storage of the motor.
In this model the winding inductance and resistance elements correlate directly with the corresponding physical parameters of the motor, with values taken directly off the manufacturer's data sheet. The capacitor, CM, models the mechanical energy storage of the motor. Current into the capacitor equates, via motor constant KT, to motor torque, and the voltage across the capacitor is equal to the motor back EMF. The back EMF voltage equates to motor velocity through the inverse of Ky. In the model, the term N is simply a multiplier equal to the number of feedback cycles obtained per revolution of the motor. For example, in a 4 pole brushless DC motor the commutation Hall effect device outputs will be at twice the rotational frequency of the motor, making N equal to 2.
The equation for the capacitor, given in Figure 2, has the units of Farads if J and KT are expressed in SI units. In modeling the overall transfer characteristic, it is important that the moment of inertia of the load on the motor be added to the moment of inertia of the motor itself.
It is worthwhile to note that the current into the motor, minus idling current, is proportional to acceleration of the motor. This is easily seen from the model by realizing that the time derivative of the capacitor voltage relates directly to acceleration. The effects of loads on the motor can be modeled by including a current source across the capacitor for constant torque loads, or a resistor for loads that are linearly proportional to motor speed.
TRANSFER FUNCTIONS FOR VOLTAGE AND CURRENT DRIVEN MOTORS
Using the electrical model, the small signal transfer function of the motor is easily derived. Equations 1a and 1b give the small signal frequency response for both the current and voltage driven cases respectively.
1a)
N X WM(S) N
1
=-X-
iM(S)
Ky sCM
1b)
N X WM(S) = ~ X - - - - - - - -
VM(S)
Ky 1 + sCMRM + s2 LMCM
The transfer function given in equation (1 a) describes the small signal response of motor speed, WM(s), to changes in the drive current. Equation (1b) relates the dependence of motor speed to motor drive voltage.
The small signal response of the motor for the current driven case has a DC pole that results from the relationship of motor torque to velocity, that is, motor velocity is proportional to the integral of motor torque over time. In the current driven motor neither the winding resistance nor inductance appear in the transfer function. This is because these elements are in series with the current source output of the driver stage. As long as the output impedance of the driver remains large relative to the impedance of these elements, the resistance and inductance of the motor will have a negligible effect on the small signal response.
The voltage driven response has a second order characteristic that results from the interaction of the series RLC. In many cases the transfer function of the voltage driven case can be simplified. If the quality factor of the series RLC of the motor model is much less than one, as defined in equation 2, then the response of the motor can be accurately approximated by equation 3.
2) QM = ~ (CM RM '/Cr:;
Kr RM
'
f{Cj M
:. QM< 1 If RM :t> K1~[_~
3) For QM < 1
N X WM(S) = ~ X
1
VM(s)
Ky (1 + sCMRM) (1 + SLM/RM)
CONSIDERING THE WHOLE LOOP
Figure 3 shows the complete speed control loop for the current driven case. The overall open loop response, AoLC· is easily written.
4)
- K<I> x KLF (s) x Gpo x N
AoLc(s) -
s2CM x Ky '
0018-3
'N ~ Number of feedback cycles per motor revolution
Figure 3. In this phase locked loop, with current mode drive to the motor, the motor winding resistance and Inductance can be ignored as long as the current driver maintains a high output Impedance.
9-161
APPLICATION NOTE
U-113
For this loop, note that there are two poles in the re-
sponse at DC, i.e., s = o. One pole is due to the response
of the current driven motor, the second pole is from the frequency to phase transformation of the phase detector. The 180 degrees of phase shift this pair of poles introduce force a phase lead configuration of the loop filter in order to obtain a loop phase margin greater than zero.
The complete voltage loop is shown in Figure 4, and its open loop response, AoLv(s), in equation 5.
5>
) AoLv(s =
sKv
K<f> X x (1
+KFs(s~) RXMKp+o
X
s2
N LMCM)
·N = Number of feedback cycles per
motor revolution
0018-4
Figure 4. With voltage mode drive to the motor the electrlcal time constant of the motor plays a part In the small signal response of the speed control loop.
This response has only one pole at DC, although the total number of poles is three versus two for the current driven case. For most motors, particularly those used in constant velocity applications, this transfer function can be simplified by applying the results of equations 2 and 3. This is best illustrated by looking at an example. Consider the following motor, (typical 3-phase brushless for disc drive applications):
Kr .............................. 1.5 x 10-2 Nm/Amp Kv ............................. 1.5 x 10-2 V-sec/rad J (including platters) ................ 1 x 10-a Nm-sec2
RM .............................................2.50
LM ...................·.........................2 mH
For this motor, the model capacitor, CM, is calculated using the equation in Figure 2 to be equal to 4.4 Farads. If we calculate the quality factor of the series RLC, using equation 2, we find it is equal to 42.4 x 10-a. This is considerably less than one, and the response closely approximates the non-complex response of equation 3 with poles at 0.014 Hz and 199 Hz.
Typical loop bandwidths will fall well inside this range of frequencies. As long as this is true, the loop response with a voltage driven motor can be approximated by:
6)
_ K<f> X KLF(S) X Kpo/RM X N
AoLv(s) -
s2CMKv
If QM < 1 and-1-- < f < ~ (f = l...!..ll
27TCMRM
27TLM
271'
This expression is the same as the current driven response, equation 4, with the transconductance of the current drive stage, Gp0 , replaced by the gain of the voltage drive stage divided by the motor winding resistance,
Kpo/RM·
CLOSING THE LOOP
When it comes to closing the loop the goal is to have a stable loop with the required loop bandwidth. The variables that must be considered are:
1) The motor 2) The power driver, type and gain 3) The phase detector gain 4) Loop bandwidth 5) The loop filter
The first four of the above variables are usually dictated by conditions other than the stabilizing of the loop. This leaves the loop filter as the tool for achieving the small signal loop requirements.
For many cases involving constant velocity loops for DC motor speed control, the following simple Bode analysis can be applied for determining the design of the loop filter. Assuming we know, or have preliminary guesses for the first four variables listed above, we can plot the Bode asymptotes for phase and gain of the combined response of the motor and power driver. Figure 5 shows, for a typical case, such a plot on a frequency scale that has been normalized to the desired loop bandwidth, or open loop unity gain frequency. This figure illustrates the small signal open loop response for the current driven case, equation 4, minus the response of the loop filter, KLF· If the previously noted assumptions hold, this plot will also apply to the voltage driven case i.e., equation 6.
9-162
APPLICATION NOTE
U-113
80
60 H
,, 40
~
1'
Iii 20
y 0
z
~ -20
-40
-60
-80 O.Q1
AoLc(s) K··Gpo·N
= KLr(s) s2cM·Kv
llJI lillllil
triAAG _rrHrsE
~
~
0
... ·90 ~
f"3 '
-1eoe
..I .
~ -210E
~
-360
0.1 1.0 10 100
NORMALIZED FREQUENCY - f/fu
0018-5
Figure 5. A Bode plot of the combined gain and phase response of the motor, motor drive, and phase dectector la useful In determining the requirements on ·the loop filter. This plot Is normalized to the desired open loop unity gain frequency.
From Figure 5 two restrictions on the loop filter are readily apparent. First, since the remaining portion of the loop has 180° of phase shift over the entire frequency range, the loop filter must have a phase lead at the unity gain frequency and at all frequencies below the unity gain frequency. By meeting this restriction the small signal loop will be unconditionally stable.
Secondly, in order to achieve the desired loop bandwidth, the loop filter must have a voltage gain at the desired unity gain frequency of 30 dB. This level is simply the inverse of the remaining loop's voltage gain at the unity gain frequency.
A loop filter configuration that will meet these restrictions is shown in Figure 6. Also shown in this figure is the small signal response equation for the filter. The response starts out from DC with a flat inverting gain that breaks
upward at the zero frequency, wz, and then flattens out
again at the pole, wp. The pole in this response is necessary to prevent .excess feedthrough of residual .reference frequency that is present at the outputs of many digital type phase detectors-in fact, as will be discussed in the design example, a separate reference filter is normally required.
A good choice for the relative positioning of the pole and zero of the loop filter response is to space them apart by 1 decade of frequency, and center them around the unity gain frequency. Figure 7 shows the Bode plots of this suggested positioning applied to the case illustrated in Figure 5. As shown, a phase margin of about 45° is obtained with this configuration.
BIAS~
.L
VOUT(s) = -R3 x 1 + slo>z
YIN
R1 1 + S/o>p
1
o>z = (R1 + R2) C1
1 o>p = R~1
0018-6
Figure 8. Thia loop filter configuration provides the required phase lead and gain at the loop crossover frequency.
80
0
60
40
I,i,i 20
y 0
z
~ -20
-40
-90 I..n....'
..."'(.!)
-1eoe
..I .
en
<(
-270il:
-60
-80
-360
O.Q1 0.1
1.0
10
100
NORMALIZED FREQUENCY - f/1u
0018-7
Figure 7. Using the criteria set forth for the design of the loop filter, the resulting Bode plot indicates a phase margin of 45".
If the above results are acceptable, then the following simple steps can be applied to pick the loop amplifier component values. Referring to Figure 6.
9-163
APPLICATION NOTE
U-113
1) Pick R3 to be as high in .value as acceptable for the Op-Amp and board restrictions.
2) R1 = (R3 x 3.33)/1QX120, where Xis the voltage gain,
in dB, required at the unity gain frequency.
3) R2 = R1/9, sets a 10:·1.ratio for "'P to "'Z·
c 4) 1 = (21T x R2 x 3.33 x f,:..i-1. where f,,_ is the loop
unity gain frequency.
Using this simple procedure the small signal loop is easily closed for stable static operation.
A DESIGN EXAMPLE
As an example, let us take a look at the complete design of a constant velocity speed control loop for a disc drive application. The performance characteristics for the circuit can be summarized as:
Motor speed ...·......... 3600 rpm ±60 ppm (0.006%) Speed stability .......·...................... ± 50 ppm Start-up lock time .·.......·...··..·..·..... 1Oseconds Input voltage .......·............. .'........... 12 Volts Motor idling current ..........................0.5 Amps
The schematic for this design is shown in Figure 8. The motor is a 4 pole 3-phase brushless with the electrical and mechanical specifications given in the figure. The motor is current mode driven with the UC3620 3-phase Switchmode Driver. The speed control function is realized with the UC3633 Phase Locked Controller.
5V OUT 4.7K
LOCK INDICATION OUTPUT
O.
UC3633 PHASE LOCKED CONTROLLER
OK
J? ~v ~~~H~HVOLT-SEC/RAD 12
MOTOR PARAMETERS
IN 1µ .
= .I,(TANT) Kr 0.022 NM/AMP
J = 1.5E-3NM-SEc2
":"
(INCLUDES 3-5" PLATIERS)
------ 8 ------
UC3620 SWITCHMODE 30
DRIVER
r·-----:-----------1
H--..., I 4-POLE II 3-PHASE I
MOTOR
t______ - - ______:l
10K PULL-UPS
0018-8 Figure 8. A precision si>eed control loop uses the UC3620 Swltchmode 3--phase Driver and the UC3633 Phase Locked Controller to spin Ii DC
bruahless motor at 3600 rpm, ±60 ppm.
9-164
APPLICATION NOTE
U-113
POWER DRIVER STAGE
In Figure 9 a detail of the driver IC and the associated circuitry is shown. The UC3620 is a current-mode, fixed offtime, chopper. Three 2-Amp totem pole output stages with catch diodes drive the three motor phases. The outputs are enabled by the internal commutation logic that responds to the three Hall logic signals from the motor. The motor is equipped with open collector Hall devices making the three 1Ok pull-up resistors on the UC3620 Hall inputs necessary.
Current is controlled by chopping the lowside drive to the phase winding under the command of the UC3620's current sense comparator. The RC combination on the timing pin of the driver sets the off-time at 22 µs. This results in
a chopping frequency of well over 20 kHz under normal operating conditions.
The transconductance of the driver is set by the value of current sense resistor used at the emitter pin of the UC3620. With a value of 0.20. the transconductance from the error amplifier output to the driver outputs is 1 Amp/ Volt. The UC3620 error amplifier is configured here as a unity gain buffer, thus the drive control signal is applied at the non-inverting error amplifier input with the same overall transconductance. An internal 0.5V clamp diode at the current sense comparator input results in a 2.5 Amp maximum drive current. There is a 1V offset internal to the UC3620 that is reflected to the drive control input at zero current. This offset combines with the 0.5 Amp idling current level of the motor to set the steady state DC voltage at the driver control input to be 1.5V.
12V
UC3620
TO LOOP FILTER
OUTPUT
4-POLE 3-PHASE BRUSHLESS
I 0.001µ
PULL-UPS
+---_. FEEDBACK
TO UC3633 HALL LOGIC
FROM MOTOR
0018-9 Figure 9. The UC3620 is a current mode fixed off-time driver. This device includes all the drive and commutation circuitry for a three phase
brushless motor. The 0.211 current sense resistor and the internal divide by five sets the transconductance of this power stage to 1 Amp/Volt.
9-165
APPLICATION NOTE
·------ 15
:
INPUT
I I
U-113
2.sv
sv
OUT
·--- 9
8 - - - - -R4- - 7
....----'VS~M,_.....,.sv
OUT 12V IN CONTROL VOLTAGE T00--11>--\il\llr----\f\/l,-----e--------------------------'
MOTOR DRIVER
C1 0.47µ
0018-10 Figure 10. Phase locking the motor to a precision reference frequency is achieved with the UC3633. The double edge sensing option on this
device doubles the loop gain and allows twice the reference frequency to be used for a given motor RPM by forcing the phase detector to respond to both edges of the Hall feedback signal.
PHASE LOCKED CONTROL CIRCUIT
A detail of the phase locked control portion of the design is given in Figure 10. The UC3633 contains all of the circuitry required for this function including: a crystal oscillator, programmable reference dividers, a digital phase detector, and op-amps for the required filtering. The UC3633 receives velocity feedback from the Hall signal applied at its sense amplifier input pin. The sense amplifier has a small amount of hysteresis that provides fast rising and falling input edges to the following logic. A double edge option is available on the UC3633 sense amplifier. When this option is enabled, as it is in this design, the phase detector is supplied with a short pulse on both the rising and falling edges of the feedback signal, effectively doubling the loop gain and reference frequency.
The required reference frequency for this loop is 240 Hz, given by the product of the motor rotation of 3600 rpm (60 Hz), the number of cycles/revolution at the Hall outputs (two for a 4 pole motor), and a factor of two as a result of the double edge sensing. The divider options on the UC3633 are set up such that standard microprocessor crystals can be used. In this instance, a 4.91520 MHz
( ± 50 ppm) AT cut crystal is divided by 20,480 to realize a
240 Hz reference frequency input to the phase detector.
The phase detector on the UC3633 responds to phase differences at its two inputs with output pulses at the reference frequency rate. The width of the pulses is linearly proportional to the magnitude of the phase error present.
9-166
APPLICATION NOTE
U-113
sv----~ T (ONE PERIOD OF REFERENCE FREQUENCY)
---1 PHASE DETECTOR OUTPUT, (SENSE AMPLIFIER INPUT
LEADING REFERENCE
FREQUENCY INPUT
BY 90 DEGREES)
ov~~~~~~~~~~~~~~~~~~~~~~~~~~
sv~~~~~~~~~~~~~~~~~~~~~~~~~~l
PHASE DETECTOR OUTPUT, (SENSE AMPLIFIER INPUT TRAILING REFERENCE FREQUENCY INPUT BY 90 DEGREES)
ov
0018-11
Figure 11. The phase detector on the UC3&33 is a digital circuit that responds to phase error with a pulsed output at the reference frequency rate. The width and potar1ty of the pulses depend respectively on the phase error magnitude and polarity. If any static frequency error Is present, the detector will respond with a constant 0 Volt or 5 Volt signal depending on the sign of the error present.
The pulses are always 2.5V in magnitude and are referenced to 2.5V at the detector output. The polarity of the output pulses tracks the polarity of the input phase error. This operation is illustrated in Figure 11. The resulting phase gain of the .detector is 2.5V12TT radians, or about 0.4V/rad, with a dynamic range of ±2TT radians.
The phase detector also has the feature of absolute frequency steering. If any static frequency error exists between the two inputs, the output of the detector will stay in a constant high, or low state; 5V, if the feedback input rate is greater than the reference frequency and OV, if the opposite frequency relationship exists. The lock indicator output on the UC3633 provides a logic low output when any static error exists between the feedback and reference frequencies.
A unity gain bandwidth of 4 Hz was chosen for this loop. This unity gain frequency is well below the effective sampling frequency, the 240 Hz reference, and is sufficently high to not significantly affect the start-up lock time of the drive system. The design of the loop filter follows the guidelines described earlier. The magnitude of the loop gain, minus the loop filter, at 4 Hz is equal to:
K<f> X Gpo X N _ (0.4)(1)(4)
(27Tf)2 X CM X Kv - (2TT4)2(3.1 )(0.022)
= 37.2 E-3 or -28.6 dB.
This dictates that the loop amplifier has a gain of 28.6 dB at 4 Hz. A value for the loop amplifier feedback resistor, R3, of 2 Mn was chosen. The values for R1. R2 and C1 were calculated as follows.
R1 = (2E6 x 3.33)/1028.6/20 = 248 kn (270 kn used).
R2 = 270/9 = 30 kn
C1 = (2TT x 30E3 x 3.33 x 4)-1
= 0.4 µ.F (0.47 µ.Fused).
The additional op-amp on the UC3633 is used to realize a second order active filter to attenuate the reference component out of the phase detector. The filter is a standard quadratic with a natural frequency of 17.2 Hz and a Q of about 2.3. This circuit provides 46 dB of attenuation at 240 Hz while adding only 5° of phase shift at the 4 Hz loop crossover frequency. In Figure 12 design guidelines and response curves for this filter are given.
9-167
APPLICATION NOTE
Reference Fiiter Configuration
U-113
FROM PHASE
DETECTORo-.l\l\,.,,_. . .-'\11,.,,_....._ - I
OUTPUT VIN
UC3633 AUXILIARY OP AMP
0018-12
Reference· Fiiter Design Aid-Gain Response
"'N = JR1R2C1C2
<=2~=~~
~ Note:. with R1 = R2, t =
Reference Filter Design Aid-Phase Response
~ -20
g -30
-40 ~~l~ill~ll~l~~
0.1 0.2 0.4 0.6 1 2 4 6 10
I
t:~c -20
.~ ...
!iEll -30 FVOARRIARBL1E=IRS21/~ ,.,.\.y.li~N;!§~..!-++++-H
Ul -40 1/f-C1/C2
0.1 0.2 0.40.6 1 2 4 6 10
NORMALIZED FREQUENCY-(IO/ION)
NORMALIZED FREQUENCY-('"/'°N)
0018-13
0018-14
Figure 12. To keep feedthrough of the residual reference frequency at the phase detector output to a minimum, a simple quadraUc filter csn be used. The design of this filter Is eaally accompllshed with the above equations and responae curves.
As mentioned earlier, a separate reference filter is required in this type of phase locked loop .to attenuate the reference frequency feedthrough at the output of the phase detector. With the active filter following the phase detector, the feedthrough to the loop amplifier is kept to less than 20mVpp under the worst case condition of ±'71"(180°) phase error. This is small compared to the 1.25V DC signal out of the detector at this phase error. If the reference ripple into the loop amplifier becomes large compared to the averaged phase error term, large signal instabilities may result. These are primarily the result of the unidirectional nature of the motor drive.
The static reference ripple at the motor drive input, during phase locked conditions, can be minimized by forcing the loop to lock at zero phase error-at zero phase error there is no reference frequency component at the detector output. The finite DC gain through the loop filter, dictated by the inherent second order nature of the loop, results. in a static phase error that is a function of: the .DC level required at the motor drive input, the DC gain and reference voltage of the loop amplifier, and the voltage levels out the phase detector. The addition of resistor R4, see Figure 10; from the loop amplifier's inverting input to
9-168
APPLICATION NOTE
U-113
the 5V reference sets the zero phase operating voltage at the loop filter output to 1.5V. This matches the nominal operating voltage required at the UC3620 control input, taking into account the 0.5 Amp idling current of the motor and the 1V offset of the driver. This cancellation is subject to variations due to shifts in DC operating levels, so, while it does significantly reduce static reference feedthrough, it can not be expected to reliably set exactly zero phase operation.
The oscilliscope traces in Figure 13 show the Hall input to the UC3633 along with the output waveform of the digital phase detector under static phase locked conditions. Notice that the phase detector output is alternating between positive and negative output pulses. This is a result of a slight asymmetry on the Hall input signal in conjunction with the use of the double edge sensing being used. In
this case, the asymmetry is due to differences in the rising and falling edges of the Hall signal that result from the RC filter at the sense amplifier input. This filter is required to keep high frequency noise from the motor drive out of the phase detector.
The startup response of the motor is pictured in Figure 14. Shown are the voltage waveforms at the lock indicator output, the loop amplifier output, and the phase detector output of the UC3633. At the moment the lock indicator goes high the motor has reached its operating velocity. The absolute frequency steering of the phase detector forces a slight overshoot in frequency that delays the settling of the loop by about 1 second. Without the frequency steering feature the phase detector would command a much lower average drive signal during startup, extending the start time by over 50%.
HALL FEEDBACK SIGNAL AT UC3633 INPUTj10Y I DIV)
ov
PHASE DETECTOR OUTPUT (2V/DIV)
ov
0016-15 Figure 13. This oscilloscope trace shows the static waveforms al the
Hall sensor input, and phase detector output of the UC3633. The static phase error has been adjusted, with R4 in Figure 10, to be very small. The alternating positive and negative pulses al the output of the phase detector is due to an asymmetry in the Hall signal.
5V LOCK INDICATOR (5V /DIV)
ov
10V
DRIVER INPUT ov CONTROL VOLTAGE rr;v I DIV]
5V
PHASF Dfll cron j!W / tllVJ OUTPUl
ov
2 SECONDS I DIV 0018-16
Figure 14. The startup lock time of the motor is minimized with the absolute frequency steering feature of the phase detector, keeping lock times under 10 seconds.
Unitrode Corporation makes no representation that the use or interconnection of the circuits described herein will not infringe on existing or future patent rights, nor do the descriptions contained herein imply the granting of licenses to make, use or sell equipment constructed in accordance therewith.
© 1987 by Unitrode Corporation. All rights reserved. This bulletin, or any part or parts thereof, must not be reproduced in any form without permission of the copyright owner.
NOTE: The information presented in this bulletin is believed to be accurate and reliable. However, no responsibility is assumed by Unitrode Corporation for its use.
Unitrode Integrated Circuits Corporation
7 Continental Boulevard. ·P.O. Box 399 ·Merrimack, New Hampshire· 03054-0399
Telephone 603-424-2410 ·FAX 603-424-3460
9-169
n n INTEGRATED
~CIRCUITS
-UNITRDDE
APPLICATION NOTE
U-114
UC 3841 PWM CONTROLS 300 WATT OFF-LINE POWER SUPPLY
by Bill Andreycak UICC Application Dept.
INTRODUCTION
With the introduction of the UC3841, Unitrode has provided a control chip uniquely optimized to implement primary side control for a broad range of power supply applications. This form of control requires significant programming and fault protection intelligence over and above the requirements for merely regulating an output voltage. These are included in the UC3841 in the form of over-voltage, under-voltage, and over-current sensing, in addition to low-current start-up, feed-forward line regulation, duty cycle limiting, slow turn-on, and optional fault latch-off.
Although all of these features are important to most off-line power supplies - and are incorporated in the design described herein - it is beyond the scope of this paper to discuss the inner workings of the control circuit. Rather, the reader is referred to the UC1841/3841 data sheet and to Unitrode Application Note U-91 describing its predecessor, the UC1840 for details of the IC implementation. This note describes the use of the UC3841 as the controller in a typical application - a 300 watt off-line power supply. ·
TOPOLOGY OVERVIEW
A buck-derived, two transistor forward topology was selected for this example for several important reasons: two 400 volt transistors are typically much less expensive than one 800 volt unit; peak currents and ripple are much less than with a flyback configuration; clamping is done to the bulk DC lines eliminating the need for dissipative high-voltage snubbers; and transformer reset is automatic requiring only a 50% maximum duty cycle limitation. The basic power stage configuration and typical operating waveforms are shown in Figure 1.
magnetic and storage components and achieving a high overall efficiency. This frequency is high enough to keep the number of transformer turns low and yet not so high as to incur significant switching or core losses. Standard commercial devices were used throughout to demonstrate the cost effectiveness of this design.
DESIGN SPECIFICATIONS The specification goals which were established - and met - for this design example are the following:
Input voltage (110 VAC input)= 85 min, 135 max VAC
Input voltage (220 VAC input)= 170 min: 275 max VAC
AC line frequency = 50 Hz min
DC bulk voltage = 200 min, 385 max voe
Output voltage = 15 volts
Output current = 20 amps max continuous
Switching frequency = 200 kilohertz
Line regulation = 1OmV
Load regulation= 10 mV
Output voltage ripple = 100 mV pk-pk, DC to 20 MHz
Efficiency = 85% at full load
CIRCUIT OVERVIEW The complete schematic for this 300 watt power supply is shown in Figure 2 but before discussing the details of the design, it is instructive to understand the overall approach.
While the UC3841 is compatible with either voltage or current mode control, this design is a voltage-mode configuration which takes advantage of the UC3841 's controlled PWM ramp waveform to accomplish fast feed-forward line regulation while also guaranteeing an absolute 50% maximum duty cycle clamp.
The design starts with a 110 volt input voltage doubler for a nominal 290 volt DC main allowing either 110 or 220 volt operation. The control and drive circuitry are configured for low start-up current so that starting energy is accumulated in a low voltage capacitor, C10 in Figure 2, which is charged from the high-voltage bulk DC through a large-valued resistor, R2. After starting,
SWITCHING FREQUENCY
the higher operating currents of the control and drive circuits are supplied from an efficient low-voltage
A design decision of equal importance to the power winding on the power transformer. This would normally
topology is the choice of switching frequency. For this be a separate primary-referenced axillary winding and
example, 200 kilohertz was selected as an optimum compromise between minimizing the sizes of the
isolation would be incorporated in the feedback path for output voltage control. For this example, isolation was
9-170
APPLICATION NOTE
TWO-TRANSISTOR FORWARD CONVERTER
VIN
t of---~~~~~--~01 OUTPUT
T1
· II
D1 D3
- - L- -1 - -
Vo
CONTROL
·
AND DRIVE
D4
CIRCUIT
n:1
OUTPUT RET
02
D2
~·~~~~~__.____---'
U-114
PWM OUTPUT
I
VDS 02
\...__.---JI
_ _ \....._
\L---
VIN - - - . - - - - - - .
T1 PRIMARY
0 -----------...-----'
-VIN ____________ ....__ ___,
VIN/N
VD4 SECONDARY
I
\...__ ___.!
\
Figure 1. Basic power topology and typical waveforms for the Two-Transistor Forward Converter
9-171
APPLICATION NOTE
U-114
ignored and operating power after start-up was taken from the 15 volt output - a simplification which can easily be remedied using common techniques which will not affect the remaining design.
The UC3841 provides the means to sense adequate energy in the start-up capacitor and initiate the turn-on sequence. It then activates the UC3707 Driver which boosts the PWM output from the UC3841 to a high peak current, source/sink drive command.
This signal is level-shifted bytransformerT1 and applied simultaneously to the gates of the two power MOSFET switching devices, 02 and 03. These two FET's drive the power transformer, T2, in the forward direction with reset provided by 06 and 09.
Additional features which are incorporated in this design include slow turn-on - both initially and after fault shutdown, over-voltage and over-current shutdown, pulse-by-pulse current limiting for light overloads, feed forward for fast line regulation, and a maximum duty cycle clamp.
CIRCUIT DESIGN DETAILS
INPUT STORAGE CAPACITANCE
The amount of input, or bulk storage capacitance for a given power supply design will be determined by the more stringent of three separate requirements:
1.Maintaining a minimum DC bulk voltage as the input capacitor supports the converter between AC cycles.
2.Providing a minimum hold-up time for operation after loss of the AC line voltage.
3.Meeting the requirements for AC RMS charging current.
In this case, the. value was calculated to support the primary voltage between AC cycles to a minimum of 200 VDC. In a dual voltage system, the most stringent case is the doubler configuration where there is a 180 degree phase shift between the voltage waveforms on each of the series capacitors. The minimum DC bulk voltage is then the sum of the minimum voltage on one series capacitor plus the average voltage on the other. The value of each capacitor is calculated from the following formula:
C1 = C2 =
Output power
-~--
Efficiency x AC frequency x (Ve peak' - Ve min')
Where, in this example,
AC frequency = 50 Hz,
Vcpeak=(80x1.414)-Vd=115V, and
Ve min = .33 ( 2 x 200 - Ve peak ) = 95 V
which determines a value for C1 and C2 of 1680 microfarads each. This was actually implemented as shown in Figure 2 by four 1000 uF units, C1 through C4.
PRIMARY AND SECONDARY CURRENT
An estimate of the maximum primary and secondary currents is needed to select the power switches, diodes, and transformer wire sizes. A first-order approximation can be calculated from the equation:
lpeak = -
Output power
------
Efficiency x Input voltage x Max duty cycle
300 = 0.85 x 200 x 0.50 = 3·52 Amps
For rectangular wave forms, RMS currents are calculated by multiplying peak current by the square root of the duty cycle yielding 2.5 Amps of primary current and 14 Amps for the secondary winding.
MOSFET SELECTION
As described in the Topology section, one advantage of the two-transistor forward converter is that the maximum voltage on the power switches does not exceed the peak input voltage. In this example, it allows the use of 500 Volt IRF 840 power MOSFETs which have a fairly low on resistance of 0.8 ohm, more than adequate current capability, and are available in plastic T0-220 packages. Heatsink requirements can be calculated by starting with the DC losses:
P loss = Ip peak2 x Rds on max x D max
Extrapolating the maximum Rds on value for the IRF
o c 840 to a junction temperature of 11 0 yields 1.75 ohms
which means a DC loss of 10.8 watts. Rounding up to 12 watts to include switching losses means that with a maximum ambient temperature of 70 °C, the junction will stay below 110 °C if the total thermal resistance, including the 1.0°C/W of the T0-220 package, is held to less than 3.3°C/W.
RESET DIODES
Since the current through the reset diodes, 09 and 010, returns to zero when the core completes reset, diode reverse recovery time is not critical. Forward turn-on time is still important, though, in order to catch the transformer energy when the power switches turn off, but this is a much simpler problem and LIES 1106 rectifiers are more than equal to the task.
9-172
AC
+
LINE VOLTAGE 1201220 VAC
D1
0 '
I AC
JUMPER FOR
R1 10K, 5W
R2 10K,5W
120V OPERATION PRIM RETURN
R7
SK
+ VIN
5 V REF
DC BULK R1 330K
R16 10K
OUTPUT SENSE D2
I I Rct~:I 11
i
10
i :' C10 220
'.f
+VIN
(j
C131 01
DC BULK
02
D ______ R22R~1.5 IRF840
7~7
D4 ,(> R23
1D55V_.<..."._1K
01
R25 1.5
03 IRF840
T1
D7 ~R26
18T
5V 5> 1K
DB
5
R20 1K
CURRENT SENSE
C15
270PF
RETURN
NOTE: UC3707PINS1, 4, 5, 7, 12, 13, 16, TO GND
J>
"Cl
r"C-l
~
0z:
sz:
m
D6 UES1306
RETURN D9 UES1306
Figure 2. Overall schematic for a 300 watt, off-line power converter using the UC 3841 for control
~,..,......
APPLICATION NOTE
U-114
TRANSFORMER DESIGN
The transformer turns ratio is defined as:
As a general guideline, operation at higher frequencies usually produces a transformer design which is core loss, rather than flux swing, limited. Under these conditions, it is best to start with the core area-product calculation using the formula:
J AP= AwAe =( -P-in x-1o· 1.ss x (Kh I+ Ke f2) ·66 cm'
120 K211 where:
Pin = Input Power= 353 Watts
K = Winding Factor = .141 (for a fwd conv)
ft= Transformer Frequency = 200 kHz
Kh = Hysteresis Coefficient = 4 x 1o-5 (3C6A)
Ke= Eddy Current Coefficient= 4 x 10-10 (3C6A)
Np = Dmax x Vp = Dmax x ~ = 12.025 Dmax
Ns
Vo+ Vd
15.8
At this point, there are two considerations to balance: The desire to make Dmax as close to 0.5 as possible so that the peak current is low, while keeping the number of turns to low, whole numbers. For this example, the best choice is
Np 22 Turns Ns 4 Turns
and Dmax = 0.46.
With this duty cycle, the peak primary current can be more accurately calculated as 3.84 Amps with an RMS value of 2.6 Amps.
The remaining transformer calculations are summarized below:
For this design, the area-product calculates to 2.9 cm4 allowing a comfortable selection of an ETD-44 ferrite core made of 3C6A material. Core selection is typically an iterative process with the first core choice used to define the windings which, in turn, allows calculation of both winding and core losses. If these answers are not acceptable, another core size is selected and the process repeated.
The manufacturer defines the ETD-44 core as having a volume of 18.0 cm3 and a thermal resistance of 12°C/W.
Selecting 40° C as a reasonable limit for the maximum
temperature rise of the transformer and recognizing that
core loss will be an important factor, an arbitrary starting
point for the transformer design is to allocate 30°C to
the core and 1o0 c to the copper. With this assumption,
the core power density can be calculated from:
Temp rise
,
Power Density=-----------= 140 mW/cm
Therm Resist x Vol_ume
The manufacturer's curves of core losses for the 3C6A material at an operating frequency of 200kHz show a corresponding peak flux density of approximately 600 Gauss which equates to a peak-to-peak value of 1200 Gauss, or 0.12 Tesla. Additional data needed to calculate the primary turns are the primary voltage, Vp =Vin - Vsat, and an estimate of the maximum duty cycle which, to provide some margin, is initially set at 0.47. With these inputs, the primary turns are defined by:
Np
VpxTonx10'
min=-~--
Flux swing x Core area
190 x 2.35 x 10··x 10'
=
= 21.3 turns
12x1.74
Primary inductance, Lp = Al x Np2 = 1.26 mH
Magnetizing current, Im = Vp x Ton I Lp = 347 mA (peak)
Primary conductor area, Axp = Ip rms I 450 = .00578 cm2 min
Secondar;y conductor area, Axs = Is rms I 450 = .0301 cm min
While the primary wire area corresponds to a wire size of AWG 19, and the secondary is equivalent to AWG 12, both have to be evaluated in terms of their active area at 200 kHz. From Eddy Current calculations it can be determined that the depth of penetration of current at 200 kHz is .017 cm which does not effectively utilize the .091 cm diameter of AWG 19 wire. While multiple strands of finer wire help, increasing the number of strands also increases the number of layers which forces the wire thickness to be substantially less than the penetration depth in order to minimize the AC loss.
A more effective solution - which is made more practical because of the relatively few number of turns - is the use of flat copper strip. For the primary, a strip .0044 cm thick (approximately 2 mils ) and 2.5 cm wide was insulated with 2 mil mylar between each turn and wound in two sections - eleven turns under and eleven turns over the secondary. The secondary was also made of copper strip, in this case .020 cm thick. A cross section sketch of the transformer winding technique is shown in Figure 3.
9-174
APPLICATION NOTE
U-114
2.96 cm
1- - - - - - - ; } 1/2 Primary - 11 turns
~EEirstrie .0044 ~_2~m
"'I -r
--;.,-.-.-.-;.-.-.-.-.-.-.-·· ~~i~~~;p~~r~~5 cm · - - - - -
I
1.72cm
I
Figure 3. Cross section of one-half of the power transformer illustrating the strip winding techniques which minimize both Eddy Current losses and leakage inductance.
With the windings defined, the total transformer losses may be calculated as follows:
Core loss = Power density x Volume = 2.52 Watts
Pn.mary resi.stance =
Copper ohm-cm x ave cm/turn x Np
------~---------
Strip cross-section area
2.29 x 10 6 x 7.6 x 22 = 35 milliohm
.0044 x 2.5
is capacitively coupled to the driver IC to prevent core saturation. Because of the DC offset voltage on the capacitor, the primary voltage will now be to some extent dependent upon pulse width. A step-up turns ratio was used to the secondary with 15 volt zener clamps to limit the gate-to-source voltage on each FET. Twelve turns were used for the primary resulting in a 500 Gauss flux swing. Each secondary winding consists of 18 turns and the total core loss is calculated at 0.13 Watt.
Wire loss (prim) = Ip rms2 x Rp = 0.24 Watts
OUTPUT INDUCTOR
2.29 x 10 6 x 7.6 x 4 Secondary resistance = - - - - - - - - - = 1.39 milliohm
.020 x 2.5 Wire loss (sec)= 0.26 Watts
Total power loss =2.52 + 0.24 + 0.26 = 3.02 Watts
The output inductor was designed for less than 1.8 Amps of ripple current at full load and minimum duty cycle using the equation:
L =
(Vo + Vd) x Taff ---------
L\ lo max
Temperature rise = 3.02 W x 12 °C/W = 36 degrees. GATE DRIVE TRANSFORMER
and from:
Dmin = Dmax x
Vin min
=
0.46
x
200
--~
= 0.239
and
Vin max
385
Since both the number of turns and the currents are
small for this gate drive transformer, a toroidal core shape is an efficient solution and the core selected was the Ferroxcube 846T250 made of 3C8 ferrite material with an outside diameter of 0.875 inches. The design
1 - Dmin Toft max= - - -
= -0-.76-1 -
= 3.81
us
11
0.2MHz
the inductance value is then defined as:
equations and guidelines are similar to the power transformer example. In this case, the primary winding
L = 15.8 x 3.81 = 33.4 uH Min 1.8
9-175
APPLICATION NOTE
U-114
Selected for this application was an ETD type core made from 3C8 material. This material was chosen because of its high saturation flux density of greater than 3000 gauss. Here again, it is necessary to determine whether the design will be core loss or saturation limited but since this is a forward converter with the inductor in the continuous mode, the AC ripple current is a small percentage of the DC load current and the core should be saturation limited.
The core selection process again starts with a calculation of window - area product using the equation:
AP = AwAe = ( L x !pk x_Ifl x 10·) 1·31 cm· 420x Kx Bmax
=
(
34 x 10·· x 25 x 20 x 104) 1·31 -
= 2.36 cm·
420 x 0.7 x 0.3
With this AP value, an ETD-39 core was selected with a value of Ae = 1.25 cm2· The minimum number of turns
can then be calculated from:
Nmin ~ L x Ipk x 1~ = 23 Turns Bmax x Ae
The gap length is then calculated using the classic inductance formula:
µ xµ xN2 x Aex10·2
lg= 0 ' L
· 0. 219 cm
with ua = 4 it x 10-7 and ur = 1. To obtain the desired inductance, however, the actual gap must be almost twice as large to account for.the fringing field which is· not included in the above formula.
This inductor was also wound with copper strip but in this application the task is easier as neither Eddy Current losses nor space for high-voltage insulation need be considered. A strip 2.5 cm wide of 10 mil ( .025 cm ) copper was used which, with a mean tum length of 6.7 cm, gave a DC resistance of
2.29 x 10··x 6.7 x 23
h
R =
= 5.65 mo ms
0.025 x 2.5
and a power loss at full load of 2.26 Watts.
OUTPUT CAPACITOR
There are two sources of ripple voltage which need to be considered in meeting the design goal of 100 millivolts and they are both caused by the inductor ripple current. The first is merely
!!,. Vo= !J,.Q/Co
and, for a given ripple current, is minimized by increasing the capacitor value. The minimum capacitance, if this was the only contributor, is
Cout min = _1_x_tJ,._l_o_x_1_x_1_ 2x2x2fxtJ,.Vo
- -1-·- 8 - = 11.25 microfarads 8 x 200k x 0.10
The second source of ripple voltage is the voltage drop across the ESR of the capacitor caused by the ripple current. The maximum ESR allowable for 100 mV ripple is
ESR max = 100 mV/ 1.8 A = 56 mohms.
The two contributors of ripple voltage do not add directly as there is a 90 degree phase difference between them. Typically, in order to achieve a reasonable ESR, the capacitance value becomes so much greater than the minimum value that the fl Q I Co term can be ignored. An added benefit of a large output capacitance is the improvement in load transient capability.
For this design, two 470 uF electrolytic units were used in parallel to achieve an ESR value of 3 to 15 mohms a broad range necessitated by the difficulty in getting specified high-frequency data from capacitor manufacturers.
A final component added to the output filter is a good, high-frequency capacitor to bypass the inductive components of the electrolytics and shunt any switching spikes which might get to the output A 1.0 uF ceramic monolythic capacitor is a good selection for this application.
OUTPUT RECTIFIERS
The output diodes need to be able to handle the output
current of 20 Amps, have 150 Volt reverse capability, and be extremely fast. Unitrode UES 703 rectifiers were selected for this application because of their 35 nsec reverse recovery specifications, as well as their low forward drop of 0.8 Volts max. Since one of the output diodes will always be conducting, it is advisable to mount both on the same heatsink designed to dissipate approximately 16 Watts with a 30 °C temperature rise. This will keep the junction temperature below 100 °C in a 70 °c ambient.
PROGRAMING THE CONTROL FUNCTIONS
With the completion of the power path design, the remaining tasks all relate to programing the many functions of the UC3841. In the interests of readability, the description which follows is a somewhat qualitative discussion of the methods for implementing the functions rather than a rigorous derivation of each component's value. Again, reference to the UC3841 data sheet is necessary for detailed specification limits and tolerances.
9-176
APPLICATION NOTE
U-114
POWER SUPPLY START UP
When line voltage is first applied, the UC3841 is in its OFF state and draws less than 5mA from the line through R1 and R2. While there is an additional 2.4 mA due to the various programing resistors, the UC3707 draws no current as it is powered from the Driver Bias output of the UC3841 which is off during start up. Therefore, resistors R1 and R2, which are necessary anyway to discharge the bulk storage capacitors, can easily provide the current to charge the start up capacitor, C1 O, without the power dissipation which would require complex circuitry to disconnect them after start up.
The resistor divider of RS and R6 performs two functions. The ratio of these resistors determines the actual turn-on voltage at C10 while their effective series impedance provides hysteresis such that turn-off occurs at a lower level than turn-on. In this circuit, the turn-on
voltage is 17V and the hysteresis is 3.5V. This means C1 O will charge to 17V while most of the circuit is off. When turn-on is initiated, the added load of the driver will cause this voltage to decay and it will fall either to 14.4V where the power supply output will catch it through D2, or, if start up does not take place, to 13.5V where the control will turn off and start a new cycle.
Prior to turn-on, and after a low-voltage turn off, the Soft-Start capacitor, C14 on Pin 8, is clamped low. At turn on, although the Driver Bias immeadiatly activates the UC3707, no power pulses are generated while Pin 8 is low. As C14 charges, PWM commands begin and the pulse width increases with a rate of increase defined by the time constant of C14 and R17. This time constant needs to be selected remembering that while start up is taking place, all the drive energy is coming from C1 Oso the charge of C14 has to be faster than the discharge of C10. These waveforms are shown in perspective in Figure 4.
START-UP WAVE FORMS
+Vin r=-------
PIN 15
DRIVER BIAS PIN 14
VSOFT START PIN 8
PWM OUTPUT PIN 12
VOUT 15~1..1---_-_-_-_-_~__=_c______
CONTROL
POWER PRIMARY i.-f----C10 CAPACITOR - - + - - - v o u T - - - ·
SOURCE
SOFT START STATUS
VOUT
START __ .J
CHG ~
1 - - PWM CONTROL_____,
L END I CHG
-----t·I - ZERO V ----RISING VOLTAGE
REG·15V _.
Figure 4. Initial start-up waveforms showing the slow turn on of the power output stage. 9-177
APPLICATION NOTE
U-114
OSCILLATOR AND RAMP
at The UC3841. operates a fixed frequency determined
by R9 and CG on Pin 9. The pulse width modulation is performed by comparing the Error Amplifier's output to a separate ramp waveform generated on Pin 10. The slope of this ramp is given a minimum value by R15 charging C11 from the 5.0V reference. These components define a rise time of 2.5 usec and thereby establish a maximum duty cycle clamp of 47 percent. The network of 01, R14, and R16 .sense the DC bulk 1101tage and provide ari increasing charge current to C11 - thereby increasing the slope of the ramp for bulk voltages above 200 volts. This increase in slope linearly tracks the input line voltage and modulates the PWM output signal providing fast, pulse-by-pulse, open-loop line regulation which greatly eases the requirements of the feedback control loop.
inductance and capacitance, it is important to ke~p any ringing which might appear on the output of the driver chip confined within the limits of the supply voltage to that chip. This is easily accomplished with the UC3611 Schottky diode array used for diodes D3A and D3B.
CLOSING THE LOOP
In this voltage-mode application, the output filter will exhibit a two pole response to the control loop. Loop compensation· at ·the Error Amplifier is designed to contain two pole-zero pairs by using the configuration shown in Figure 5. This will insure overall loop stability with maximum high frequency response while retaining a large low frequency gain.
RFP
FAULT PROTECTION
Load current is sensed through the power transformer by a sense resistor, R27, in series with the power switches. The value of R27, in conjunction with the
RFZ
CFZ
divider of R18 and R19, establish a threshold at Pins 6 and 7 of 23 Amps as related to the output. When this
threshold is exceeded, the UC3841 goes into a pulse-by-pulse reduction in width.to limit the energy and allow the power supply output to fall. Because of circuit delays, however, this limiting only works to a minimum pulse width which might allow too much energy to
VCOMP RREF VREF
protect against a short circuit. This eventuality is
covered by a second, higher threshold in the current
sensing circuit which triggers a Fault Latch for
immediate shut down. This Fault Latch is also activated by the Over-Voltage comparator which, in this case, is monitoring the input line voltage through R3 and R4..
Figure 5. A generalized two pole-zero compensation approach to providing good loop stability.
Once triggered, the Fault Latch immediately terminates the PWM signals and discharges the soft-start capacitor. If the Reset Pin 5 is high, once latched, the circuit will stay off until either the input line is recycled or Pin 5 is momentarily pulled low. If Reset is already low, the Fault Latch will reset when the soft-start capacitor completes its discharge, allowing an automatic restart. The Fault Latch may also be activated externally by forcing positive current into Pin 4.
The generalized approach to this compensation network is to place the first pole at a low frequency, typically around one Hertz. Two zeros are then introduced at approximately one-half the output filter break frequency to compensate for its two-pole rolloff. The amplifier's second pole is placed at a fairly high frequency to provide a predictable gain reduction; however, the amplifier will usually run out of
THE UC3707 DRIVER
gain-bandwidth prior to reaching this pole.
This device is used only as an interstage driver to take
The output filter response is defined by:
the pull-down output from the UC3841 and develop the high current turn-on and turn-off commands to the power MOSFETs. This is a dual driver but in this case the two channels are connected in parallel to provide a maximum peak current of 3 Amps, source or sink. Of course, the OIL package would provide a power limitation were it not for the fact that the high currents are needed only to charge and discharge the MOSFET gate capacitance. When driving a load which has both
Lout= 34 uH,
Cout = 1000 uF,
Rload = 0.75 to 10 ohms, ESR = 3 to 15 mohms 1
Pole freq = 2 7t ../ L C = 865 Hz
1 ESR zero = -2-n_x_C_x_E_S_R_ = 10.6 to 53.1 KHz
9-178
APPLICATION NOTE
U-114
The error amplifier compensation poles and zeros are located at the following frequencies referenced to the components of Figure 5:
Input zero = - - -1- - - = 568 Hz 2llxRizxCi
Rip+ Riz Input pole= - - - - - - = 23 kHz
2 ll x Rip x Riz x Ci
1 Feedback zero = 2 lt x Rfz x Cf = 970 Hz
1
Feedback pole =
= 1 Hz (approx)
2ll(Rfp+Rfz)Cf
The effect of these poles and zeros is shown graphically in Figure 6 where it can be seen that they provide an overall response with a single pole roll-off to 10 kHz. The gain crosses zero dB at approximately 8 kHz with more than adequate phase margin, regardless of the output capacitor's ESR.
POWER SUPPLY PERFORMANCE
The use of the UC3841 control IC has allowed a very straight forward and simple implementation of a relatively high performance power supply with a remarkedly small number of components. Representative waveforms of performance at several points within the supply are shown in Figures 7 - 10. All the initial performance goals defined for this design were0 met and it is hoped that with the information presented above, application to more sophisticated or specialized design tasks will be eased.
70
············································.·. ~-t,
60 50
:···· ?41,,
······.. .....................................
40
30
20 G A 10 I N 0
(db) -10
-20
-30
-40
-50
"',,," E/A COMPENSATION ,/'
/ / / /
',,' ' ' ',
REFERENCES
-- -O-U-T-PU-T-F-IL-T-ER-------, \ \
' ' ' ' ' '
1.ANDREYCAK, BILL; 1.5 MHz Current Mode IC Controlled 50 Watt Power Supply, Proceedings, High Frequency Power Conversion Conference,
\ \
1986
\
\MIN ESR
\
2.ITI CORP; Reference Data for Radio Engineers,
\
\MAXESR
4th Edition, 1956, Skin Effects
'~, ~
3.DIXON, LLOYD JR., Unitrode Power Supply
\'
' ' , MIN ESR _.,, \ ', \ \
Design Seminar, SEM-500, 1986 Sections M-2 and C-1
4.HANETK, EUGENE R., Design of. Solid State
10
100
1K
10K 100K 1M
Power Supplies, 1981, Van Nostrand
FREQUENCY
p 0
H A -90
OVERALL
s
E -180 L--------------======
5.CLEMMER, DUANE T., Ceramic Capacitors for Switching Power Supplies, Unitrode Capacitor Division
6.MAMMANO, ROBERT A., Applying the UC1840 to Provide Total Control for Low Cost, Primary Referenced Switching Systems, Unitrode Publication U-91
Figure 6. Total power gain and phase relationships showing the effects of loop compensation.
7.ANDREYCAK, BILL, Practical Considerations in Current Mode Power Supplies, Unitrode Publication U-111
9-179
APPLICATION NOTE
OPERATIONAL WAVEFORMS
U-114
o-o--
o-o--
PRIMARY
Top: VGs 01 101v/cm Bottom: Vos 01 100 v/cm Horizontal: 1 µs/cm
Figure 7. Gate-to-source and Drain-to-source voltage waveforms for the upper FET switch
FULL LOAD
Top: Vos 01 100 v/cm Bottom: lpri 2 1A/cm Horizontal: I µs/cm
Figure 8. Power switch voltage and current waveforms at full load.
0--
LIGHT LOAD
Top: Vos 01 100 v/cm Bottom: lpri 1 A/cm Horizontal: 1 µs/cm
SECONDARY
Top: Vsec 20 v/cm Bottom: Vout (AC) 10 mv/crn Horizontal: 1 µs/cm
Figure 9. Power switch voltage and current waveforms at light load.
Figure 10. Transformer secondary voltage and power supply output ripple.
Unitrode Integrated CircLits Corporation
7 Continental Boulevard. ·P.O. Box 399 ·Merrimack, New Hampshire· 03054-0399
Telephone 603-424-2410 ·FAX 603-424-3460
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- UNITAODE APPLICATION NOTE
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New Integrated Circuit Produces Robust, Noise Immune System For Brushless DC Motors
Bob Neidorff, Unitrode Integrated Circuits Corp., Merrimack, NH
Abstract
A new integrated circuit for brush less DC motor control is presented that implements many new techniques to enhance reliability and reduce the detrimental effects of noise. In addition to safety features and noise rejection circuitry, the new circuit contains a complete pulse-width modulator (PWM), a practical tachometer, a precision voltage reference, a high-speed current-sense amplifier, and high-voltage, high power, output stages.
Various applications of the IC are discussed in detail, including using the PWM for fixed frequency and fixed off-time control, driving power MOSFETs, driving bipolar power transistors, and sensing winding current. The IC is shown in applications that allow braking and direction reversal without damage to the motor or the power semiL;or1Uuctors.
BLOCK DIAGRAM OF THE UC3625
SVOLT REFERENCE
VREF
QUAD
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APPLICATION NOTE
U-115
The Problem
Conventional brush motors have proven reliable and versatile. They remain popular partly because the pressures to improve haven't been high, and partly because nothing better has been available that is practical. Brushless DC motors (BDCMs) can pack the same horsepower into smaller, lighter boxes. They can also accelerate faster due to inherently lighter rotor construction. Withoutthe friction and arcing of brushes, they are acoustically quieter. As they have permanent magnet rotors, they are faster to manufacture. Permanent magnet rotors also dissipate very little power, so BDCMs have far less heat dissipation problems.
One thing that has held the motor industry back has been the availability of economical control electronics. Recent price trends in power MOSFETs and monolithic motor controllers have reduced these limits. The final hurdle to broad acceptance is assurance of reliability. Brush motors proved their reliability not through design, but instead through over a hundred years of development of rugged brushes and slip rings.
Two problems with BDCMs today are performance and reliability in the presence of noise. Noise here can refer to externally generated electromagnetic noise, internally generated chopping noise, or inappropriate commands from the operator of the system.
The UC3625 specifically addresses the need for an economical, robust BDCM controller by specifically addressing these failure modes and also by implementing many functions and features desirable in high performance motor systems. The following table outlines some of the important features of the UC3625:
Push-Pull Low-Side Drivers
· Versatile High-Side Drivers
Complete PWM
· Two or Four-Quadrant Chopping
· Tachometer
Soft Start
· Undervoltage Protection
· Overvoltage Protection
· Active Safe Braking
· Differential Current Amp
· Hysteresis on all inputs
· Direction latch
· Cross Conduction prevention
Unique Features For Noise
All logic inputs to the UC3625 have hysteresis and /or latches for maximum noise rejection. The position sensor inputs specifically contain 0.8 volts of hysteresis, yet still meet TTL input thresholds. These inputs also contain pull-up resistors allowing them to directly interface to open-collector sensors.
Position sensor inputs are latched immediately following commutation, and remain latched through the on-time of the tachometer monostable (one-shot). This prevents commutation noise from reaching the decoder, latching outthe largest noise spike in the motor system. Although this sets a maximum motor speed, correct choice of pulse width guarantees operation up to the maximum speed of the motor while still affording excellent noise rejection.
The one-shot pulse also drives a low saturation-voltage driver connected to TACH OUT. The average value ofthe voltage on TACH OUT is directly proportional to motor speed, so that the pulse generator doubles as a simple tachometer.
DECODER
TACHOUT
Tachometer Doubles As Input Noise Gate Even with input latches, external noise filtering is often valuable. Chopping noise lends itself to analog low-pass filtering because of its dominant high-frequency components. As high-frequency noise energy can be very strong, zener clamping ahead of the filter can be very effective.
Suggested External Non-Linear Filter For PWM Noise
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Cross-Conduction Prevention To further assure noise immunity, the UC3625 contains latches and a shift register to guarantee that all power stages turn off and remain off for a minimum time before changing states. In addition to
FROM DECODER
PULL DOWN
Logic That Prevents Cross Conduction
used to enable the PWM latch every cycle, and also to clock the protection shift registers.
Another fundamental part of the PWM is the PWM latch. The output of this latch enables the power stages. The latch is set once per cycle
by the oscillator, and cleared by either the PWM comparator, a peak current signal generated in current-sense circuitry, or by a fault signal from the OV/COAST input. This latch is reset dominant, meaning that a steady reset signal from any of three sources completely inhibits the power stages.
POWER STAGE
The other elements in the PWM are the PWM comparator and the error amplifier. The PWM comparator is an NPN-input comparator dedicated to comparing the output of the error amplifier to some other signal such as a command voltage, ramp, or sensed signal. The error amplifier is a PNP-input op-amp compensated for unity-gain operation, who's inputs can operate linearly down to ground.
The PWM can be configured into any number of different loops that regulate winding current (torque is nearly proportional to winding current). regulate speed, or regulate some other parameter. The PWM is internally configured for peak current control as well, although this is not intended to be the principle feedback loop.
The approach above compares winding current to a DC voltage with the PWM comparator, and pulse-by-pulse
preventing noise-induced cross conduction, this prevents
cross conduction due to slow power stages.
5V
The delay time is only inserted when an output is commanded
UC3625
from high to low or vice versa. During normal three phase
commutation, outputs are turned off (opened) for a full cycle
before changing states, so this delay will not impede normal
operation. The only times that this delay will be inserted are during noise spikes, direction reversal, and braking.
r
OSCILLATOR
Pulse-Width Modulation System
Motors perform better with higher operating voltages
l.ATCH
because for a given value of inductance, higher voltages can
change winding current faster. A necessary adjunct to higher
supply voltages is current control, either by linear amplifiers of pulse-width modulation (PWM). The UC3625 uses fixed frequency PWM for chopping.
FROM CURRENT
AMP
At the heart of the PWM is a sawtooth oscillator. The oscillator is programmed up to 500kHz with one resistor to the reference and one capacitor to the ground. This oscillator is
SV SV SV
PWM Configured For Average Current Feedback
regulates winding current. This is similar to "current mode" in PWM power-supply systems, and offers the advantage of removing the pole caused by load inductance from the feedback loop.
The PWM can also be configured to use the error amplifier to amplify the difference between the winding current and a desired current, and to use the PWM comparator to compare the error amp output to the oscillator ramp. This current loop operates on average, rather than peak current.
FROM CURRENT
AMP
UC3625 PWM Block Diagram Configured For Pulse-By-Pulse Current Control
If the PWM comparator is used to compare the oscillator ramp to a DC voltage, then the load duty cycle is directly proportional to the applied DC voltage, as is the average load voltage. This "voltage mode" loop comes close to controlling speed because speed is nearly proportional to average winding voltage. If an overall speed feedback loop is required to regulate speed, this "voltage mode" topology can serve as a local feedback loop to make the system transfer function more linear, and the error amplifier can be used as the overall loop amplifier.
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APPLICATION NOTE
5V 5V
UC3625
I
U-115
OSCILLATOR ..._.,_____ _ _ _~.,. CLOCK
PEAK CURRENT OVERVOLTAGE
s a
OUTPUT STAGE ENABLE
R
PWM LATCH
FROM TACHOUT
Voltage Mode Speed Control
UC3625 5V
oRsC c
PDC
PWM
osc
TO POWER DEVICES
I
Circuit For Fixed Off-Time PWM Using the UC3625
The advantages of each topology must be weighed considering complexity, overall stability, and sensitivity to load. In cases where current feedback seems nearly impossible to compensate, some compromise between currrent feedback and voltage feedback is dictated.
The PWM is also configurable to fixed off-time PWM ratherthan fixed frequency PWM by adding a few external components that couple the output off signal back into the oscillator.
Fixed off-time control is sometimes desirable because it uses one of the easiest feedback loops to compensate. Its main drawback is that the modulation frequency varies with load and speed. This means that for some loads chopping noise can become audible (below 20kHz). This also allows variation in the dead time inserted to prevent output stage cross conduction.
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APPLICATION NOTE
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Different Chopping Techniques
Chopping capitalizes on the inductance of the load_!o maintain load current when the driving voltage is removed. The driving voltage is normally supplied through power switches, and diodes normally conduct across the load when the switches are opened.
Two different methods are common for chopping. The more efficient method chops one low-side power switch while one high-side switch is on. This is referred to as a two-quadrant PWM.
Two-quadrant PWM normally operates with a low duty cycle, as winding current is charged principally by the supply voltage, yet winding inductance is discharged by the voltage drop in the diode circuit (see figure below). Motor back EMF reduces the effective supply voltage and increases the effective diode voltage drop, so the duty cycle tends to increase with speed.
The main advantage of two-quadrant chopping is efficiency. Its main drawback is that it can't quickly decrease winding current. This can be very troublesome in position feedback systems.
Power Drivers
The overwhelmingly dominant power output device in new designs is the N-Channel Enhancement-Mode Power MOSFET. Bipolar power transistors and power darlingtons still have advantages in very high-voltage systems, but these advantages are being continuously eroded by developments in MOSFET structures and merged bipolar MOSFET devices. The UC3625 is able to drive both power MOSFETs and bipolar transistors. The low-side drivers in the UC3625 are totem-poles capable of greater than 250mA peak gate or base current, but the package and the die are not constructed for continuous power dissipation greater than 1 watt, which imposes an upper limit on the available current for bipolar device drive.
UC3625 +1SV
lo
lo
1~·11·~·1
~ ·· CO~ROL ~ CO~ROL
l·I
l·I
PWR-VCCLJ
__ I -~~ I
~VVv----" Driving Low-Side MOSFETs with the UC3625
VMOTOR
1-E---;
J I
I
~~o_:j
I C><Af·"!
J L
VMOTOR
Two-Quadrant vs. Four-Quadrant Chopping
The Power Vee pin is separated from signal Vee so that high gate current peaks can be isolated from signal Vee, and also so that Power Vee can be tailored to the power device. For fastest switching of power bipolar devices, the Power Vee pin can be limited and clamped, as shown in this example.
L
+SV
I UC3625
RCL
PWR·VCC
In contrast, four-quadrant PWM systems chop both switches, and circulate load currentthrough two diodes backwards into the supply.
Again ignoring back EMF, four-quadrant chopping produces a nearly symmetrical current waveform, as current rises due to the supply voltage impressed on the load inductance, and decays due to reverse supply and load inductance. With four-quadrant chopping, a motor can decelerate as quickly as it can accelerate.
To program the UC3625 for one approach or the other, apply a logic signal to the '-QUAD SEL input. QUAD SEL can also be changed during operation to tailor performance to specific requirements.
RS
Driving Low-Side Darlingtons with the UC3625
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APPLICATION NOTE
U-115
Driving high-side devices with the UC3625 requires level shifting if the motor supply is greaterthan 50V. The UC3625 high-side outputs are open collector NPN transistors which pull low to turn on high-side MOSFETs or bipolar transistors.
VMOTOR
Driving High-Side P-MOSFETs
VMOTOR +15V
Driving High-Side N-MOSFETs
VMOTOR
Driving High-Side PNP Darlingtons with the UC3625 Although capable of 50mA current sinking, the open collector outputs are normally operated with lower currents to minimize the power supplied by the high-voltage supply. As a high-side switch, P-channel power MOSFETs are far easier to drive than N-Channel power MOSFETs because the gate of P-channel MOSFETS need not be pulled above the positive supply to obtain low voltage drop. Unfortunately, P-channel power MOSFETs are more expensive and less available than N-channel devices, so the added supply in the N-channel design is often justified.
Current Sense
The UC3625 contains a high-speed gain-of-two differential amplifier dedicated to current sensing. This amplifier can be connected directly across a low-value current-sense resistor or between two different current-sense resistors. Since the amplifier common mode range allows operation one volt below ground, the amplifier has excellent common-mode noise rejection.
The current-sense amplifier also embodies an ideal diode that performs absolute value and level shifting of the input, giving a transfer function of:
Vo= 2.5 + 2 ABS (Vi2 - Vii)
If the low-side power devices and the lower catch diodes are returned to the same current-sense resistor, and the UC3625 is chopping in four-quadrant mode, then the winding current always flows through the current-sense resistor. The voltage on the current-sense resistor flips polarity every time the PWM chops, but the absolute value current-sense amplifier rectifies this, giving a smoother representation of continuous winding current, and requiring less filtering.
Some filtering of the current-sense signal is always required, however, and the output of the current-sense amplifier is the best place to filter. The amplifier is stable with all capacitive loads, and has approximately 250 ohms output impedance.
Filtering at the input of the current-sense amplifier is also valuable to remove spikes that are faster than the amplifier can track. However, to insure that the absolute value circuit continuously tracks current, use only a minimal amount of input filtering.
The output of the current amplifier drives two comparators through the filtering resistor: the peak current comparator andthe overcurrent comparator. The peak current comparator resets the PWM latch wheneverthe current-sensevoltage exceeds approximately 200mV. The overcurrent comparator initiates soft start if the current-sense voltage exceeds approximately 300mV.
The peak current comparator can be used to limit maximum peak winding current while a larger feedback loop limits winding current to control some other parameter, such as speed or position. The overcurrent comparator then functions as a fail-safe device that commands SOFT START if the peak current loop loses control, as might happen if a power device becomes shorted.
Is it Brake...or Break?
The UC3625 contains provisions for braking by way of a multifunction pin called "RC I BRAKE". This pin also serves as the timing pin for the internal tachometer, pulsing between 1.67V and 3.33V every time the position sensors commutate. To command BRAKE, pull RC/BRAKE low with an open collector gate or switch. The tachometer then stops pulsing and all three low-side drivers turn on.
Normal PWM configurations do not allow braking current to be modulated because the braking current does not normally flow through the sense resistor. The motor control circuit below includes three added diodes that, during BRAKE and all other circumstances causes winding currenttoflowthrough the sense resistor. Using this circuit, the UC3625 stops a motor as fast as the peak limit current setting allows and protects the output power devices and the motor.
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APPLICATION NOTE
U-115
PUAt----~
VMOTOR
also contains an uncommitted comparator that inhibits the outputs and clears the PWM latch whenever its input exceeds 1.75V. This can be used with a voltage divider for an over-voltage inhibit, or can be directly driven from TTL or CMOS for a logic controlled COAST input.
To prevent very high power supply current spikes and to limit average current during faults, the UC3625 contains latched soft start. The latch is set by low power-supply voltage or overcurrent fault, and is only cleared when the setting condition goes away and the soft start input discharges to below approximately 200mV
Normally, the UC3625 is configured with a capacitor from soft start to ground, which is charged by the soft start 10uA current source. The UC3625 can also be configured to latch soft start until cleared by connecting a 4.3 volt zener and a normallly closed switch from Vref to soft start. The switch then functions as a reset switch.
5V
Circuit For Safe Braking Series diodes guarantee that braking current will flow in the current-sense resistor
4.3V
0 RESET
ERROR AMP
Direction Reversal is Worse
As with braking, direction reversal can also force excessive current into power devices if not checked. Direction reversal forces two of thethree driver channels to go from high to low or low to high directly. With the UC3625, cross conduction is completely prevented, but high winding current is dependent upon the application. The higher the speed, the higher back EMF, and the higher the potential peak current.
The approach mentioned for braking also limits peak winding current during direction reversal. In addition, the direction latch and shift register in the UC3625 can be configured to prevent direction reversal until motor speed drops to a safe level. This latch also commands COAST whenever a direction reversal is commanded and motor speed is too high.
The easiest way to configure this protection is using the internal tachometer to drive "SPEED IN" through a low-pass RC filter. The "SPEED IN" threshold is set to prevent reversal whenever input voltage exceeds approximately 250mV.
Other Protection Features
To prevent confusion or insufficient drive to power MOSFETs, the UC3625 contains a comparator to lock off all six outputs until the Vee input exceeds 9V, called under-voltage lock-out. The UC3625
I PEAK CURRENT UNDERVOLTAGE_ _ __
Manual Fault Reset Circuit Uses Zener Diode to Latch Faults
Voltage Reference
Finally, the UC3625 contains a precision voltage reference trimmed
to 5V +f- 2%. This reference powers most of the internal circuitry for
supply rejection and is available on the ·"Vref" pin for driving other circuitry such as Hall-effect position sensors and bias circuits. Operation of the voltage reference is guaranteed with loads up to 30mA, and the reference is also short circuit current limited to approximately 1OOmA.
Unitrode Integrated· Circuits Corporation 7 Continental Boulevard. · P.O. Box 399 · Merrimack, New Hampshire · 030540399 Telephone 603-424-2410 · FAX 603-424-3460
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APPLICATION NOTE
U-116
A NEW LINEAR REGULATOR FEATURES SWITCH MODE OVERCURRENT PROTECTION Robert Mammano and Jonathan Radovsky, Unitrode IC Corp; and George Harlan, Power General
ABSTRACT
This paper presents a new linear control circuit which. in addition to offering benefits such as low input-out-put differential and a precise reference voltage. features a unique and innovative approach to overload protection. By using duty-ratill. switch-mllde protectilln. this circuit eliminates both the high internal dissipation of constant current limiting and the latch-up tendenciesllflimitingwith current foldback.
THE CURRENT LIMIT PROBLEM
As an opening statement, let us offer as a "given" that all linear power supplies need some form of over-current protection. Traditionally, this protection consists of configuring supply to control current - rather than output voltage - once an established threshold of maximum current has been exceeded. The method of current control can usually be classified as either "constant-current" or "current-foldback" current limiting and, while simple to classify, choosing between these two methods is often less than satisfying.
The protective method most acceptable to the user is constant current limiting with a characteristic as shllwn in Figure 1. With the knowledge that a power supply will only deliver a maximum current regardless of what he might do to it, the user's job of scaling his cables, switches, connectors, and other components associated with the power inputs to his system is greatly eased. He knows that no matter how non-linear his load may be. he can count on a regulated voltage whenever his current drain is within the supply's rating. Further, he knows that the maximum rated current is always available to meet any demand asked of the supply.
The "benefits" of constant current limiting are another matter to the power supply designer, however. For example, a regulator designed to deliver 12 Volts at a maximum load current of 5 Amps, would probably start with a bulk input voltage of approximately 15 Volts and a constant current limit of 5.5 Amps. Under maximum rated load, the internal dissipation of the regulator is 3V x SA or 15 watts but with a short to ground, this dissipation jumps to 15V x 5.5A or more than 80 Watts! This means that the thermal management and heat sinking must be sized for the short circuit condition resulting in a massive overkill in terms of volume, complexity, and cost with respect to normal operating conditions.
CONSTANT CURRENT LIMITING
Vo INTERNAL POWER DISSIPATION
Pd = Vin x lsc \
O'-~~~~~~~~~~~~_.
10-Figure 1: Constant current limiting.
A common solution to this problem is to design a current limiting scheme as illustrated in Figure 2. Here the protection is actuated at 5.5 Amps when the output voltage is at 12 Volts but the allowable current then "folds back" as the output voltage falls due to increasing overload, until it reaches some much lower value - say one Amp in this example - with a shortened output. Now the dissipation with a short circuit is close to the same as it was with rated current and our designer's thermal problems are solved.
FOLDBACK CURRENT LIMITING MAX LOAD CURRENT
i
f
Vo
SHORT CIRCUIT CURRENT
lo-
Figure 2: Foldback current limiiling
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APPLICATION NOTE
U-116
But what about his customer? His load may be complex, nonlinear, and often not even well understood. Figure 3 shows typical load characteristics for digital and analog circuitry but an actual system may include all of these pJUs motors which need to be started and capacitors which need to be charged. Any protection scheme which allows the static load line to intersect the foldback current curve as shown in Figure 4 is potentially subject to latch up because the load draws more current than the regulator can supply at the voltage where the curves cross.
TYPICAL LOAD LINES w
~
:0>:;
8:: i;i 1z -
w
(c.c) w
"-
PERCENT LOAD CURRENT Figure 3: Typical digital and analog load lines.
FOLDBACK LATCH - OFF AT START
lo--+ Figure 4: Latching at start-up with foldback.
An application particularly susceptible to latch up due to foldback current limiting occurs when two supplies are used to provide positive and negative voltages to a load where there is a path for "rail-to-rail" loading. As the regulators tum on, theiroutput capacitors are charged at rates determined by the values of the capacitors and the amount of current each regulator can provide as its output rises up the foldback curve. Since these curves are unlikely to be perfectly matched, one output will dominate the other. As the fasterone's output voltage increases, it provides more current through the common load. This forces the slower
one back down the foldback curve where it provides less current, compounding the problem and ultimately latching when its output is driven past zero to a reversed polarity. Thus a foldbacklimited regulator, which might be stable when used by itself, may latch when used as one-half of a dual-polarity system due to this "tum-on slew rate" phenomenon.
So what we have concluded is that while the power supply designer needs to incorporate foldback current limiting to reduce power dissipation, his customer needs constant-current limiting to insure reliable starting. It is the contention of this paper that what they both really need is duty-ratio protection.
DUTY-RATIO OVERCURRENT PROTECTION
Duty-ratio protection can be simply described as a constant current limiting regulator with a timer. The timer's function is to tum the regulator's power stage OFF and ON with an established duty cycle ratio such that the high internal power .dissipation of constant current limiting is reduced by the duty ratio to a much more manageable average value.
Referring back to our earlier example of a l 2V, 5A regulator, consider setting the constant current limit at 5.5 amps but additionally establish a duty ratio for the timer at I to 20 for "ON" to "OFF". If we set the "ON" time sufficiently long to charge whatever capacitance might be on the output, the regulator will power up with the constant current characteristic, insuring startup regardless of the loading. In the event of an overload or short circuit (defined in this device as remaining in current limiting for a period ofapproximately 2 x Ton), the regulator will periodically shut down for a time equal to 20 x Ton and then continue to cycle in a 1 to 20 duty cycle until the fault is removed. Although the peak power during Ton might be 80 Watts, the average fault dissipation at this duty ratio is only 4 Watts - less than the normal 15 watt operating power loss, and we have thereby satisfied both the designer and his customer.
INTRODUCING THE UC1833 / UC3833
The block diagram of this new linear regulator control IC is shown in Figure 5. This circuit can be used in many different ways but its primary intent is as a high-efficiency regulator implemented with an external PNP pass transistor as shown in the figure. The circuitry in the right half of the UC 1833 block generates the voltage error signal used to activate an NPN Darlington driver which, in tum, drives the base of the PNP pass device. This common-emitter pass transistor configuration allows this type of regulator to operate with a minimum input-output differential of well less than one Volt, even at high loads.
Duty-cycle current limiting is accomplished with the circuitry on the left half of the block diagram, where an Amplifier and a Comparator are seen, both monitoring the voltage drop across a single current sense resistor. The Comparator has an input threshold of 100 mV and, when activated, initiates a timer to alternately clamp and release the base of the driver to ground thereby switching the output of the regulator from Vout to Zero with a low duty ratio.
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APPLICATION NOTE
U-116
RI
...,Co
The current sensing portion of this circuit is to the left of this figure where the current-sense Comparator and Amplifier are shown sharing the same input sense pins. Note that their offset voltages are derived by a constant current through RI and R2 in series rather than independently as shown in the more simplified earlier block diagram. By adding 30 mV to the 100 mV offset of the Comparator, the Amplifier's offset will more accurately track that of the Comparator should any variations occur, and the criteria to have the Comparator always activate first is assured.
Figure 5: The new UC1833 / UC3833 Iinear regulator.
The Amplifier part of the current sense circuitry has an input threshold of 130 mV and overrides the output of the Error Amplifier to control the driver - when enabled by the ON-time of the timer - to regulate the supply's output current to a maximum amount determined by 130 mV divided by the value of the sense resistor. The 30 mV differential between the thresholds of the Amplifier and Comparator insures that current limiting can never occur without prior initiation of the timer.
OVERLOAD PROTECTION CIRCUITRY
The operation of the overload protection circuitry can be better understood by referring to the simplified schematic of Figure 6.
A characteristic important to current protection is the accuracy of its threshold as any tolerance represents a window of undefined operation which works to the disadvantage of both designer and user of the power supply. Recognizing this, the UC 1833's thresholds are derived from its precision reference resulting in a Timer activation threshold guaranteed to 5 percent over all operating conditions.
The output of the Current Amplifier connects into the output stage of the Error Amplifier where it can easily take command when activated. The compensation capacitor must compensate both the voltage and current feedback loops, and since the current loop must override the voltage control, its gain will be higher making the current loop the more difficult to stabilize. To evaluate the current loop, grounding the Timing pin will disable the Timer and allow continuous constant current operation. This can be useful either as a temporary measure while designing the current compensation network, or permanently to implement a constant-current limited power supply.
The Current Sense Com-
parator is phased such that its ac-
tivation turns off QI which turns
on Q2 and Q4 to start the timing
cycle. The timer is a gated astable
relaxation oscillator with ON and
OFF times independently
programmed using an external
resistor and capacitor, RT and CT.
The external components work in
conjunction with an internally
switched !Ok timing resistor
shown in the schematic as R3.
With RT much greater than !Ok,
the ON time is defined by R3 and
CT, while RT and CT determine
the OFF time. The thresholds for
the Timing Comparator are set at
1/3 and 2/3 of the internally regu-
~------------------------------------" lated2.7,Vsource by the values of
Figure 6: A simplified schematic of the UC 1833 control circuitry.
R4, RS, and R6.
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APPLICATION NOTE
U-116
Timing waveforms during an overload cycle are shown in Figure 7 where the upper graph shows the output current from the regulator, the center one plots the voltage on the timing components, and the regulator's output voltage is shown in the lower graph. Following the sequence of events as drawn in the figure, when the load current ramps up and crosses the 100 mV Comparator threshold, the initial ON time begins. This initial period is about twice the duration of successive ON-times as the timing capacitor starts its charge from zero initially, while subsequent ramps begin from the lower Comparator threshold. While the timing capacitor is charging, the regulator current is limited by the action of the Current-sense Amplifier to maintain a level of 130 mV across the sense resistor. While in current limiting, the regulator's output voltage falls to whatever value that current will allow across the faulted load impedance.
average power as reduced by the duty ratio. Heat sinks for the internal power devices must now only have adequate thermal mass to absorb the high peak power of the initial ON period.
REMAINING CONTROL CIRCUITRY
Other blocks within the UCJ833 include a 2.0 Volt band-gap reference internally trimmed to I% and a low input-offset Operational Transconductance Amplifier (OTA) to serve as the error sensing and amplifying circuitry. The OTA Error Amplifier has a gm of about 4 millimho and an output current capability of +/- 300 uA. This form of amplifier can usually be compensated with a simple network - often a single capacitor - from its output to ground; but more commonly, an R-C pole-zero pair is also added to compensate for an external PNP pass transistor's gain characteristics.
OUTPUT CURRENT
Vsense= 130mv -
lo (nom)
r------' OVERLOAD "'\
I I
____ \
\ \
\\ \.
CT VOLTAGE
Vo inom)
OUTPUT VOLTAGE
::::: 2 Ton 20 Ton Ton 20 Ton
Figure 7: Load current, timing capacitor voltage, and output voltage of the regulator under fault conditions.
The ON-time continues until the internal !Ok resistor charges the timing capacitor to the upper Timer threshold. At this point, both the ON-time of the regulator and the charging of the timing capacitor are terminated, and the capacitor now discharges through RT, while the regulator is held OFF until the voltage on CT reaches the lower threshold, at which point the cycle repeats. If the load fault is removed during an ON-time, the Timer is immeadiatly disabled allowing the regulator to recover and the timing capacitor to discharge back to zero. If the fault is removed during an OFF-time, the Timer must complete that cycle of capacitor discharge before allowing the regulator to tum back on. In special applications requiring an extended ON-time, the correspondingly long recovery may be accelerated by interrupting the input voltage, as the falling internal 5 V source will discharge CT through DI and an equivalent Jk impedance.
Duty-ratio protection has greatly eased the problem of heat sinking created with a constant-current solution since the area of the heat sink, or its thermal resistance, need only remove the
The Error Amplifier is followed by a unity-gain Buffer Amplifier which controls the Driver Stage consisting of a Dar.lington transistor pair with local current limiting. This Driver can either source or sink current, allowing its use as a driver for either NPN or PNP pass transistors. The Pullup and Pulldown currentsources shown at the Sink and Source terminals of Figure 6 are to provide tum-off bias to the pass transistor during duty-ratio switching so that it is not turned off into a BVCEO.condition.
Not shown on the schematic are two additional forms of protection built into the UCJ833: Thermal Shutdown (TSD), and Under Voltage Lockout (UVLO). While it could be argued that thermal protection on the control chip does nothing to protect the pass transistor, the fact that the Driver can conduct up to at least JOO mA with a large portion of the input supply voltage across it, can result in more than acceptable internal heating of the UC1833. A good practice, when voltage levels permit, is the addition of an external resistor in series with either the Source or Sink outputs of the Driver to remove some of the voltage - and therefore some of the dissipation - from the controller.
Under Voltage Lockout keeps the Error Amplifier output low until the supply voltage reaches approximately 4 Volts insuring that all internal circuits - particularly current limiting functions are intelligent before allowing the pass transistor to tum on. The UVLO function also disables the Pullup current feeding into the Sink terminal, for low input voltages, so that the pass transistor cannot be driven in the reverse direction should the input supply fall with a charged capacitor or other energy source on the output. The Source Pulldown current source is also disabled with UVLO but this terminal also has a two-diode path from the Source to the Compensation terminals. This is to allow any shutdown function which pulls the Comp pin low to discharge capacitance at the regulator's output without reverse-biasing the Driver's emitter-base junction.
THE UC1832 14-PIN CONTROLLER
An important objective in the design of the UCJ833 was that in addition to providing significant operating benefits over the omnipresent uA723, the resulting product should be cost-competitive with that device. Committing the UC1833 to an 8-pin
9-192
APPLICATION NOTE
U·116
Minidip package allows the potential for meeting the cost objective (plus the benefit of less PC board area), but in several important ways, also restricts the device's versatility. Recognizing this fact led to the introduction of the same chip in a 14-pin package with a UC 1832 designation. The block diagram of this device, in a uA723-type application, is shown in Figure 8.
NPN PASS STAGE
TYPICAL CIRCUIT APPLICATIONS
Unitrode's Power General Division has already utilized the UC3833 (the commercial version of the UC1833) in several successful power supply designs. A brief description of some of
----- ----=l these products will illustrate both the range of applications and the simplicity which this new device brings to power supply design.
R11
Co 10uF
The circuit of Figure 9 shows one of the simplest applications of the UC3833 repeated twice to implement a dual-polarity 12 volt, 200 mA supply. The timing components fordutyratio protection are determined from the following equations:
Ton = .69 x !Ok x CT
Toff = .69 x RT x CT
Duty-ratio = Ton/(Ton+Toff) = 1Ok/(l Ok + RT)
The values shown provide approximately
Figure 8: A 14-pin version, designated UC 1832 / UC3832, offers enhanced versatility.
7 mS ON time and 140 mS OFF. These fairly rapid time constants minimize the need for any
The characteristics of the UC 1832 include all the performance features of the UC 1833 plus the following:
significant thermal mass in the heat sinks and also allow fast recovery after an overload is removed. With the knowledge that the initial conducting time can be twice the ON
time, the maximum output capacitance can be calculated from:
1. Separating the+Vin line from the CS+ terminal so that the
controller could be supplied from a higher potential, low-current, auxiliary voltage while sensing current from the main
C =!max (dt/dV)
supply.
C = 130mV/.5ohm ( 14mS/12V) = 300 uF.
2. Separating the Reference from the Error Amplifier (+) input and making both accessible to the user. Among other things, this allows phase reversal, an external or divideddown reference, and a convenient access point for soft-start.
+12VOUT
10K
1%
3.3uf
25V
3. Providing a separate input to the Driver's local current limiter allows considerable
3
.022uF
flexibility in setting that limit either higher or
lower than the 300 mA (typical) defined by the
internal 2.4 ohm resistor.
1.74K 1%
COMMON
4. A separate logic-level digital shutdown function has been added to give more programming options such as accepting a shutdown command from an over-voltage sensor or implementing a tum-on delay. This input is fail-safe as it must be pulled low to allow the regulator to tum on.
Figure 9: A +/-12V. 200mA regulator is easily implemented with two UC3833 devices.
9-193
APPLICATION NOTE
U-116
A higher power application is shown in the schematic of Figure 10 which was designed to supply 5 Volts at 5 Amps. The UC3833, configured as shown, will meet this requirement with an input voltage as low as 6 Volts due to the low saturation voltage of the paralleled 2N6489 transistors and the fact that the maximum non-fault voltage on the sense resistor is less than JOO mV. Actually, a little more sense voltage was sacrificed in the interests of selecting a standard resistor value, with the excess divided down by the 56/100 ohm divider. The additional BD438 drive transistor was added to boost the UC3833 drive current and keep the internal power dissipation low.
+Vm
['°5V'
1K
.02 OHMS, 31111
10-0
56
.0022
1 +Vin cs- 8
UC3833
COMP
TRC
GND
SINK G
SORC
FIB 5
2N6489
+
i;soo
l35V
20.5K 1%
A third application of the UC3833 is one which took par-
.15
12.7K
ticular benefit from duty-cycle current limiting. This was for
220K
1%
a disk drive power supply which required considerable cur-
rent at tum-on to accelerate the disk. The circuit schematic is the same as that shown in Figure 10 with the voltage sense resistors selected for a 12 Volt output. The power requirements dictated a peak start current of 5 Amps decaying to
-------------------·-----
Figure I0: A high-efficiency configuration with added current boost will deliver 5V at 5A from a 6V source.
3 Amps in 30 seconds as the motor reached operating
velocity. The current sense resistor was chosen to give a Timer
initiation at 4.75 A and a constant current limit of 6.1 Amps. The
timing capacitor value was set at 3300 uF yielding an ON-time
of approximately 20 seconds, with 40 seconds for the initial tum
on period - during which time the motor current will decrease to
less than the lower threshold. With a duty-ratio of 20: I, when a
fault does occur, the OFF-time will now be greater than 6 minutes,
but, ifthis is excessive, recycling the input voltage to the regulator
will reset the timing capacitor.
CONCLUSION
While no one can deny the long-term success of the uA723 as a general-purpose linear regulator controller, there has also long been a call for a device to improve its many limitations. While other products have been marketed offering some parametric improvements, the UC1833 - and its companion UC1832 - are the first to offer an innovative solution to a very basic problem. By combining switch-mode protection with linear regulation, these devices answer the question of which form of protection is best for whom, with a solution that is best for everyone.
Unitrode Integrated Circuits Corporation
7 Continental Boulevard. ·P.O. Box 399 ·Merrimack, New Hampshire· 03054-0399
Telephone 603-424-2410 ·FAX 603-424-3460
9-194
APPLICATION NOTE
U-116
UC3833 Typical Applications
See appendix for component selection
LOW CURRENT APPLICATION using the UC3833 internal drive transistor
Il
TYPICAL OUTPUT CURRENT vs. Vin and Vout of the UC3833 internal drive transistor
ror Pd1.. = 0.5 W (approx.)
UC3833
CCOMP 2K
Vin
~olts 5 9 12 15 18 24
2 150 60 40 30 20 12
+
5
105 55 35 25 15
Cout
Vout 9
12
130 60 35 20 120 55 25
-Vout
15 Current in mA 110 30
Fi .3
LINEAR REGULATOR using en external power transistor
as a series regulator R1
+
HIGH CURRENT REGULATOR
using drive transistor 02 to increase 01 base drive end reduce UC3833 power dissipation
R1
01
P CHANNEL POWER MOSFETs cen also be used as the series pass transistor 01
: : r -- - -- -- _ .. _ - -- - - - - - -. r- - - - - - - - .. - - - - - - - - - - - ..,
:
a,
a,
:
! ' TI.L~:'
i1.··1·I
: ' '
P Channel
, :''
PNP
: ' '
I._____ ~<?~.!"-~ _____ _; !. ___________ -------- __;
Fig. 4
PARALLEL PASS TRANSISTORS
cen be added for high current or high power dissipation applications
+ Vout
to Qi emitter
Fig.5 9-195
APPLICATION NOTE
UC3832 Applications
See appendix for component selection
LOW DROPOUT REGULATOR The UC3832 features a separate supply input for operation from an
auxiliary power source. Useful in low dropout applications.
U-116
GND
S1 · Closed: Normal operation Open: Output disable
Fig. 6
+Vin
PRECISION LABORATORY POWER SUPPLY featuring adjustable voltage and current limiting
01
2K Current
+Vow. +
-Vin
S1 Remote on/off
S1 · Closed: Normal operation Open: Output disable
Fig. 7 9-196
2K
-Vout
S2 · Open: Duty ratio current limit Closed: Constant current output or IMAX adjust.
APPLICATION NOTE
U-116
APPENDIX
Design Equations and Component Selection
- Current Sense Resistor
R1 = 0.135 V/louT (max) UC1833 AND 1832 WITH VADJ = 2.5V
LOW CURRENT
louT mA
R1 ohms
10
13
20
6.5
30
4.3
40
3.3
50
2.7
60
2.2
70
1.8
80
1.6
90
1.5
GENERAL USE
louT
R1
A
ohms
0.10
1.30
0.25
0.52
0.50
0.27
0.75
0.17
1.0
0.13
2.0
0.065
3.0
0.043
4.0
0.032
5.0
0.026
HIGH CURRENT
louT
R1
A
mohm
5
26
6
21
7
18
8
16
9
14
10
13
15
8.6
20
6.5
25
5.2
.~~N.:·.2~.!P!J_!..Y..~.~!~9.!...Q.!Y!.~.!E..~!.~.~!!~r. _,...... .,...,........,,.~...,...,.........N,,~...,.·.·......__. .· ""·"···"N· ..... .._............................,..,.......
R2 = (Vour - 2.0V)/1 mA
VouT 5.0 9.0 12.0 15.0 18.0 24.0
FIXED
R2 3.0K 7.0K 10K 13K 16K 22K
ADJUSTABLE
VoUTI..MAXl 7.0
R2 5KPOT
12
10KPOT
22
20KPOT
. ... . . ...,__..,.,.........,.,.,.... ,......,..__.,....... ~;!,..:...~!~Y-~..,9~!.~!.!!! ~!~!t~!!!!!~!
.w...- ....................................................w ........... ,,,, .... ,, ···- ... ...
Rs = ((Vin - VsE - Vsat)* Beta (min))/louT (max)
louT A
0.10 0.25 0.50 0.75 1.0 2.0 3.0 4.0
9V 1.8K 680 330 220 180 82 57 43
VJn. 15V 3.2K 1.2K 650 430 330 160 100 82
24V 5.6K 2.2K 1.1K 750 560 270 180 120
For circuit diagram of Fig. 4,
Beta (min) =25, VeE = 0.7V, VsAT = 1.5V
louT
VJn.
A
9V
15V
24V
1.0
200
350
560
2.0
100
175
270
4.0
50
87
140
5.0
40
70
110
7.5
27
47
75
10.0
20
35
57
15.0
13
24
38
20.0
10
17
27
For circuit diagram of Fig. 5,
Beta (min) =25, VBE = 0.7V,
VSAT ;::: VeE (02)+ VsAT (UC3833)= 1.5V
9-197
APPLICATION NOTE
U-116
.~I.~.!l~L9.!.::.I~.~~!_'?~!Y....~~n~.!!~.~.,.!!!~. .~.~!.!,~.,~!~l!!!.~!. !!!.~,.~.!P!.~!!.~,~.............-.."'"'"'"'"."....,..,.,..,.... = Ton 0.693 * 1OK* Cr
Tott= 0.693 * Rr *Cr Duty Ratio= Ton/(Ton+ Tott)= 10K/(10K+ Rr)
NOTE: Typical duty ratios are between 0.5% and 5%
Duty Ratio
5% 4% 3% 2% 1% 0.5%
Rr ohms 180K 240K 330K 470K 1 MEG 2MEG
Ton
Cr*
Ton
msec
uf
sec
1
0.15
0.1
2
0.30
0.2
5
0.68
0.5
10
0.15
1.0
20
3.0
2.0
50
6.8
5.0
75
10
7.5
100
15
10.0
* Timing capacitor CT should have extremely low leakage current.
01 - Pass Transistor
lour A
< 1.0
2.5
5.0
7.5
10.0
15.0
PNP Transistor
TIP30 04104 TIP32,34 D45C2 D45H5,8 MJE6040 TIP36 2N6666*
TIP36,145* 2N6648*
20.0
2N6285*
* Darlington transistor
P Channel MO SF ET IRF9511 RFP5P12 IRF9521 RFP6P08 IRF9531 RFP12P08 IRF9541
IRF9541 RFK25P08
IRF9Z30 RFK25P08 RFK25P08
Cr* uf 15 30 68 150 300 680 1000 1500
N Channel MOSFET IRF511
IRF521
IRF531 IRFZ10 IRF541 IRFZ20 IRF540 IRFZ20 IRFZ30
IRFZ40
9-198
n fl INTEGRATED
~CIRCUITS
-UNITRODE
9-199
n n INTEGRATED
~CIRCUITS
-UNITROCJE
9-200
n nINTEGRATED
~CIRCUITS
-uNITRODE
APPLICATION NOTE
UC1860 - NEW IC CONTROLS RESONANT MODE POWER CIRCUITS
Larry Wofford
Unitrode Integrated Circuits Corporation 7 Continental Boulevard, Merrimack, NH 03054
U-117A
ABSTRACT
A new integrated circuit. the UC1860, is introduced. Its prime purpose is to provide the control function in resonant mode power supplies operating at frequencies up to 3 MHz. A frequency modulated. fixed on-time control scheme is implemented. Additional features include a programmable under voltage lockout circuit and a programmable softstart/hic-up circuit.
BACKGROUND
For years. rumblings of the coming 1or perhaps more correctly, reapplication) of resonance as a useful tool in the power control world have been ~owing progressively louder. Being a recognized manufacturer of pulse width modulation control !Cs, some of these noises have been focused directly at Unitrode Integrated Circuits Corporation. Receiving, conditioning, filtering, and discriminating these signals. however. has been somewhat of a frustrating chore. Information indeed has been ·ought to aid in the definition of chip to perform all required re·onant mode control functions. Too often the re·ponse was an inverse request: "Tell me what the chip looks like and then I can design my power supply." The immaturity of the technology has naturally made the sharing of information somewhat less than authorative. Finally there came a day when a best guess architecture and specification goals list had to be embraced as presumed gospel. It is that choice that has resulted in the chip to be discussed in this paper.
This paper. then, will describe the UCI860 with respect to its architecture and the specific features and performance of some of the sections. The chip is intended to fully implement all features necessary for the control function in a resonant mode power supply.
BLOCK DIAGRAM
The UC1860 control IC is designed to control power conversion circuits requiring frequency modulated fixed pulse widths such as resonant or quasi-resonant mode power supplies lfigure 1).
The central section of the system is composed of 6 main blocks. A precision reference is provided for the error amplifier. These serve as the basis to control a variable frequency oscillator (VFOl which in turn triggers a oneshot. The programmable one-shot determines the output pulse width of the output drivers which are specifically designed to drive power mosfet gates. Finally a toggle flip flop steers the one-shot signal to the appropriate output stage.
In a typical application, the error amplifier is used to compare power supply output voltage to the internal reference. The error amplifier is also used as a gain block with which to compensate the overall power supply control loop. The output of the amplifier is resistively coupled to the VFO to control frequency. VFO frequency is directly proportional to error amplifier output voltage. Output pulse width is selected by an external RC pair. Pulses are sequenced to the output pins to activate the switchea in the power circuit.
On chip peripheral housekeeping blocks are under voltage lockout (UVLOl, fault management, and start-up/ restart sequencing. The UVLO block forces the chip to wake up in a consistent and intelligent state when power is applied.
An additional uncommitted open collector comparator is on chip. This comparator can be used to accomplish s host of user defined functions.
ERROR AMPLIFIER
Understanding the chip requires considering the blocks one by one. The first block of interest in the main control section of the chip is the error amplifier. This amplifier is a high bandwidth, low offset, clamped swing design (figure 2l. The non-inverting input is internally connected to a resistive divider from the reference voltage. While the divider is set for 3V, the combination of offset voltage and divider accuracy is specified as a ratio of the reference voltage. This allows an external reference of greater accuracy to drive the chip reference for better system accuracy.
9-201
APPLICATION NOTE
Vee
UVLO
EA IN(+)
EAIN H
Cvm
TRIG OSC DBL
RC MODE CMP IN(+) CMP INH SFT STRT RST DLY FLT(+) FLT(-)
D i SGND
ONE-SHOT RC CLR
T STEER
s
R R
C55 SEQUENCE
R
FIGURE 1. UC 1860 SIMPLIFIED BLOCK DIAGRAM.
9-202
U-117A
EA OUT
PGND CMP OUT
APPLICATION NOTE
U-117A
With three gain blocks !transconductance. transresistance, and voltage), the amplifier is compensated by two capacitors. The first feeds forward around the first stage directly to the second stage. This is because the first stage is designed for high gain and low offset but has poor high frequency characteristics. The second capacitor. the main
lvFO
FIGURE 2. ERROR AMPLIFIER WITH OUTPUT SWING CLAMPS.
compensation capacitor, is connected from the output to the inverting input.
Amplifier bandwidth is controlled by the impedance seen by the inverting input terminal. To the first order, bandwidth in a simple feedback configuration is easily calculated by the equation
Co
(eq. l)
2n1Rinl<Ccompl
where Ccomp is the internal 16 pf compensation capacitor that appears between the output and inverting input pins. The amplifier is unity gain stable for unity gain bandwidths less than 5 MHz lie. Rin > 2 kohm).
Higher gain bandwidth products can be obtained by choosing Rin and closed loop gain appropriately. Figure 3
100
co 40 t::!~~=t:=t::Pi-..+-W---+~ so
~ z 30 ...._._.......+-_.......__,.,
60
~ 2of-j~+-'1~~1-"'1
(!)
40
~ w
10
20
0 1--l---+--+--+---+_.-+,,...P...l--t-+-1 0
~ - 10 l--l--+-t--'i'-'--..--.-1-"o;,+->~t---t-i - 20
40 L_L._.J.._J.._L,_.J.._J.._L,_..J....:"--'---'--' 10 kHz 100 kHz 1 MHz 10 MHz 100 MHz
FREQUENCY
FIGURE 3. ERl!OR AMPLIFIER FREQUENCY RESPONSE.
shows the gain and phase characteristics of the amplifier for various resistive input impedances. Note that the phase curve is the same at higher frequencies for all three values of Rin shown. This is to be expected, since the higher order poles are internal to the amplifier. The combination ofRin and Ccomp primarily adjust the first pole position leaving higher frequency phase response unchanged.
Since the error amplifier is intended to control the frequency of the VFO, the outputs are clamped to obtain predictable minimum and maximum frequency. Each clamp circuit is actually an independent amplifier that monitors the output of the error amplifier and compares it t.o a reference. The reference for the lower clamp amplifier is the voltage at the IvFO pin while the upper clamp is 2V higher. If the error amplifier attempts to exceed either ofthese levels, the appropriate clamp amplifier overrides the third stage of the error amplifier and the output is held at the clamped value. Figure 4 shows a plot of typical input offset voltage as a function of output voltage. In the figure, the horizontal axis is output voltage referenced t.o the IvFO voltage. Note the sharp edges at the two extremes indicating clamped operation.
a<~{..w(~!)
""w~"">O.:.:>..
az..
-1 t--+-+--+--+--+---+-+---t~t--t--t--1
0.0
1.0
2.0
NORMALIZED ERROR AMP OUTPUT VOLTAGE (V)
FIGURE 4. ERROR AMPLIFIER DC CHARACTERISTICS.
VARIABLE FREQUENCY OSCILLATOR
The variable frequency oscillat.or and one-shot functions are closely integrated to achieve the desired operating characteristics. ECL type logic gates and comparators are used t.o facilitate high frequency \3 MHz) operation. The oscillator will free run at a frequency of approximately
f(oscl
IVFo
(eq.2)
In no case, however, can the frequency of the oscillator ever exceed the frequency required to support a complete pulse width from the one-shot.
Figure 5 is a detailed block diagram of both the VFO and the one-shot. The frequency ofthe VFO is proportional
9-203
APPLICATION NOTE
OSC DBL
U·117A
RC
FIGURE 5A. DETAILED BLOCK DIAGRAM OF VFO ANO ONE-SHOT.
CvFO -~-Mt
~
RC AA~-
m J L J L OUTPUT
TRIG
~A:A-
_ll__fl_ _n__n_
_LJ_
OSC DBL
~
NORMAL VFO CONTROL
ONE-SHOT CONTROLLED MAXIMUM FREQUENCY
TRIGGERED VFO
FIGURE 58. TIMING DIAGRAMS FOR THE VFO ANO ONE-SHOT.
OSC DBL OPERATION
to the current into the lvro pin. This pin is the input to a Wilson style current mirror and exhibits the temperature coefficient of two diodes (approximately 1.4V at 25C with a temperature coefficient of -4mV/Cl. lvro current is mirrored about to discharge the timing capacitor, Cvro· Under
normal operation, when Cvro diacharges to the lower oscillator threshold, hyeteretic comparator Xl changes state caueing gate X3 to recharge both Cvro and the timing capacitor on the RC pin. Hysteretic comparator Xl then resets and the oscillator recycles.
9-204
APPLICATION NOTE
U·117A
The trigger !TRIGl and oscillator disable IOSC DBLl inputs can be used to modify the free running characteristics of the oscillator. If TRIG is raised above its threshold during the discharge time of the oscillator, the recharge sequence is immediately executed, resulting in synchronous operation. If, however, OSC DBL is true when either the lower threshold is crossed or the trigger input is received, Xl will change states, but X3 will not recharge the capacitors. They will continue to discharge until a lower retaining level is reached. As soon as OSC DBL returns false, then recharge action occurs immediately.
When the error amplifier output and the oscillator input, lvro are coupled with a resistor, R vro. then the oscillator frequency is determined by
f(oscl
Rvro·Cvro
(eq.3)
where VEA is the output voltage of the error amplifier and V1vro is the input voltage at the lvro pin. The VFO gain, dli'dVEA is
df(oscl dVEA
Rvro·Cvro
(eq.4)
With this simple arrangement the maximum frequency is given by
f(max)
2V Rvro·Cvro
(eq.6)
since the error amplifier maximum output is clamped two
volts above the IFVO pin. Likewise, the minimum fre·
quency should be zero. There is, however, an obvioua limi·
tation of minimum frequency in the input offset voltage
ofthe lower clamp amplifier. Actual minimum frequency is
f(minl
vio Rvro·Cvro
(eq.6)
For lower clamp offsets less than 5mV, the maximum range of frequency would be the ratio of 2V and 5mV, or 400 to one.
When a nonzero minimum frequency is desired, an additional current can be injected into the lvro pin independent from the error amplifier. This can be most easily accomplished by a single resistor from the Ivro pin to VREF (figure 6). In this case, minimum frequency is given by
f(minl
VREr-V1vro
(eq. 7)
f(min)
VREF-VIVFO RM* CvFO
f(min)
lV
FIGURE 6. MINIMUM OSCILLATOR FREQUENCY.
9-205
APPLICATION NOTE
U-117A
where R~ is the external resistor. It is important to note that this method is not inherently flat over temperature since the voltage at the Ivro pm varies as two diodes. If this variation is unacceptable. three resistors and a pnp transistor can overcome this problem resulting in a minimum frequency of
lV f(minl
leq.81
ONE SHOT
The one-shot capacitor at the RC pin is recharged concurrently with Cvrn· This sets the output of comparator X4 to a low state allowing SIR latch X6 to be reset. The latch is reset by the_ signal coming from the output of X2 in the oscillator section via gate XS. The output of XS also blanks the one-shot off. This is done for accuracy reasons so that the on time is solely a function of the resistive discharge of the RC pin. When both caps have been charged fully, the oscillator circuit drives the output of X2 low allowing both caps to discharge. The timing cap 1s discharged by an external resistor. The threshold of comparator X4 is set at 80% of the timing capacitor's full charge value. 0.22 time constants are required to reach this threshold making the on time
t(onl = 0.22 ·RC.
!eq.9)
When the lower threshold ie reached. X4 output goes high setting SIR latch, X6, and the one-·hot pulse i· terminated.
It is important to observe two interactions between the VFO and the one-shot. While the one-shot ishigh, gate XS prevents the oscillator from erroneou·ly blanking the output low. The high output also prevents X3 from recharging the timing capacitors in the same way that OSC DBL does. This insures that in no case can the oscillator period (the inverse of eq. 2) be shorter than the time required for the one-shot. In cases where the VFO attempts to overrun the one-shot, the one-shot dominates and establishes maximum frequency.
TOGGLE FLIP FLOP
The output of the one-shot, in addition to limiting the VFO from out running the one-ehot. performs two other functions (figure ll. A logic high level from the one-shot causes one or both of the outputs to drive high. The falling edge of the one-shot not only turns the outputtsl ofT, but it triggers the toggle flip flop to rhange state. The toggle flip flop selects the output to be driven 1f the output mode control pin is low. If the output pin 1s high, both toggle outputs are high causing outputs A and B to operate in
unison.
OUTPUTS
The output blocks are well suited to driving the active capacitive load presented by power mosfet gates. With this load in mind, they are designed to deliver currents up to 3A in both source and sink directions. Current rise times are in the order of 75Nus. This results in rise and fall times of 50 ns when driving series loads of lOnF and 2.4 ohms 1figure 7). Unloaded transitions are 12ns. Of course, cross conducted charge has been minimized within the constraints of high speed design goals.
It is well worth noting that careful attention to low inductance printed circuit board layout along with proper damping and application of schottky clamp diodes are necessary when driving a large capacitive load directly. Disregard for this caution will result in the output/load combination becoming a highly excited tank that will ring and inject current into the chip substrate. Such injection is almost always a sure cause of problems in bipolar ICs.
REFERENCE
The bandgap reference needs little mention since it is a standard, borrowed from many previous designs. Trimmed for precision at wafer probe to 5V, it is specified at 1% tolerance at room temperature with no more than a 2% spread over temperature. While intended as a reference, not a voltage regulator for external use. it has line and load rejection capabilities that will allow it to be used as such for loads under lOmA. A bypass capacitor is required on the reference.
UVLO
The UVLO block (figure 8) consists of three comparators arranged to allow for flexibility of application. They can accommodate ofT-line, DC to DC, and even operation from a 5V supply.
The first of the three comparators monitors Vcc· It has hysteretic thresholds of 17 and lOV. This spread is ideally suited to ofT-line applications. The output of the Vcc comparator is an emitte.r follower that can go no higher than approximately 6.SV.
The second comparator monitors the UVLO pin which is resistively driven from the output of the Vee comparator. This comparator turns the reference on or ofT, controlling the bias in the chip. When the reference is ofT, Ice is less than O.SmA. After operation commences, Ice increased to approximately 35mA. The thresholds of this second comparator are 4.0 and 3.5V.
The third comparator monitors VREF and has a threshold of 4.SV. If either this comparator or the second has a low output, then the chip is disabled and reset. When this is the case, both output are driven to a low state, the toggle
9-206
APPLICATION NOTE
U-117A
Vee ~ 2ov
OUT .__ _ _ _ _ _ _ __..._ _ Vo
t----+---_L-vf--::.--4---- SV/DIV
v;z
v z
v~
C7 ~ 1----.Jf-----l----~~--..: SV/DIV
SOnslDIV FIGURE 7 OUTPUT STAGE MEASURED PERFORMANCE.
Vee
UVLO
4/3.SV
4.5V
INTERNAL RUN/STOP
FIGURE 8. UVLO DETAILED BLOCK DIAGRAM
flip flop is preset to select ouput A. the soft-start capacitor 1s discharged. and the fault latch is re·et.
Application of the UVLO features is simple. With no connection to the UVLO pin. the behavior of the UVLO block is dominated by the Vcc comparator and is suited for off-line usage. DC to DC applications can be made by two external resistors. one from \ice to U\'LO and the other from UVLO to ground. This exploits the 4 V hystere-
tic threshold of the second comparator. Keep in mind that the UVLO pin has an input impedance of 23 kohm when selecting the two external resistors. Operation from e 5V supply is achieved by tying UVLO. VCC' and VREF all to the external 5V supply. The UVLO pin can also be used to disable the chip at any time by pullin!I' 1t below 3.5V. The UVLO pin will source no more than l.SmA when pulled to ground.
9-207
APPLICATION NOTE
U·117A
FAULT MANAGEMENT AND RESTART SEQUENCING
The fault comparator and latch along with the soft-start and restart delay functions are shown in !figure 9l. When the chip is powered up, UVLO resets the fault latch and discharges the soft-start capacitor, Css· The restart delay capacitor, CRD· is also discharged since the latch is reset. After UVLO, Css is charged by an internal 5µA current source. The voltage at the soft-start pin is used to modify the upper clamp voltage of the error amplifier. In this way, a slow frequency ramp is obtained from zero to the point where the control loop takes over.
The chip is designed for easy implementation of a hie-up style of fault management. The fault comparator will sense signals with a common mode range of -0.J to J.OV. If !hopefully never in your application I the input to the fault comparator causes its output to go high, the fault latch is set. Immediately the one-shot is cleared and the outputs
turn off. Css is also discharged. CRo is then allowed to be charged by an internal 5µA current source. This is the zero power dissipation time in the hie-up cycle. Until the restart delay capacitor charges to JV, the fault latch cannot be reset. When both the fault comparator output is low and CRo is over JV, the fault latch is reset. At this point in time, CRo is discharged and Css is allowed to soft-start the chip. If the cause of the original fault is still present, the chip will continue to hie-up until the fault condition is removed. when normal operation will resume.
Note that the internal 5µA sources are not tightly controlled. However, if either soft-start or restart delay time is critical, a 50k resistor to VREF will provide a precise current that is sufficient to swamp out any inaccuracies of the internal source.
Two variations of the hie-up are possible. Selecting a value of zero for CRo will cause the chip to immediately attempt to restart upon removal of the fault signal. If, on
SFT STRT
I Css
RST DLY
I
FLT(+) FLT(-)
5µA 5µA
s
TO ERROR AMP HIGH CLAMP
TO ONE SHOT CLR
R
3V
R
UVLO
FIGURE 9 FAULT MANAGEMENT AND RESTART SEQUENCING BLOCK DIAGRAM. 9-208
APPLICATION NOTE
U-117A
the other extreme, fully latched fault behavior is desired, then the restart delay pin lRST DLYl can either be grounded or tied to the open collector output of an external logic gate. This uncommitted comparator could be used for this application. When Restart Delay is held low, then the only ways to reset the fault latch and reinitiate operation of the chip are to remove Vcc (UVLO will clear the latch) or release RST DLY, allowing it U> exceed JV.
UNCOMMITTED COMPARATOR
The uncommitted comparator is similar in design and speed to the fault comparator except its output drives an open collector npn transistor. This output can be used in a variety of applications. One would be to shunt the RC pin with a second resistor causing a reduction in one-shot pulse width. The input common mode range is identical to the fault comparator, -0.3 to 3.0V.
SUMMARY
The UC1860 control chip has been designed with the necessary features to implement the control function in resonant mode power conversion c1rcu1ts operating at frequencies up to 3 MHz. While some publicized applications have been considered in the design of this chip. its versatility should accommodate many ~pec1fic adaptations of resonant mode power systems as well.
150 Watt Quasi-Resonant Power Supply
·~out
Unitrode Integrated Circuits Corporation
7 Continental Boulevard. ·P.O. Box 388 ·Merrimack, New Hampshire· 03054-0388
Telephone 603-424-2410 · FAX 603-424-3460
9-209
n nINTEGRATED
~CIRCUITS
-UNITRCDE
9-210
[UJ INTEGRATED CIRCUITS
- UNITRODE APPLICATION NOTE
U-1178
UC3860 RESONANT CONTROL IC REGULATES OFF-LINE 150 WATT CONVERTER SWITCHING AT 1 MHZ
ABSTRACT
This paper is intended to explore in significant detail the intricacies of the quasi-resonant half bridge topology. Voltage and current waveforms in addition to transferred charge and energy will be analyzed as functions of time, and input/output conditions. Specific and generalized equations are given for this example, also applicable to other topologies by those skilled in modern power supply design.
INTRODUCTION
The thrust towards resonant mode power supply designs has been fueled by the industry's demands for increasing power densities and high overall efficiency. Coupled with the additional requirements for low EMI, many designers are exploring the most likely candidate for todays sophisticated, high frequency power supplies; resonant mode power conversion.
amperes of load current, it operates from a 110/220 AC input, or 220
to 380 voe at high efficiency.
DESIGN CONSIDERATIONS AND OVERVIEW
Although several basic topologies deserve consideration in this off-line application, only the Half Bridge configuration offers numerous key advantages. As opposed to the single-ended Forward converters, the half bridge provides bidirectionial utilization of the transformer, thus eliminating the need to incorporate dissipative or complex flux reset mechanisms. In addition, the primary switched voltage is one-half that of its single ended or full-bridge counter-part, significantly reducing the turn-on losses. As a reminder, zero current switching minimizes ONLY the turn-off losses. During turn-on, however, the current rises linearly before resonance commences, and the half bridge results in lower turn-on losses due to the lower voltage.
AC IN
~~o_ _ _ _ _c_3J,,__,}·
While a bewildering selection of possible resonant mode topologies and configurations exist, this paper will focus on the quasi-resonant half bridge topology. Primary side resonance and zero current switching will be incorporated into the design, with the control circuit essentials performed by the UC3860 resonant mode control IC.
Described in the text is a 150 watt off line converter switching at maximum frequency of 1 megahertz resulting in an effective 500 kilohertz utilization of the main transformer. Delivering 15 volts at 10
Primary side resonance will be utilized in this design, but not as an attemptto minimize the core size. Instead, this technique will reduce the peak secondary currents and rectifier losses. transferrring them to the primary side where the diode voltage drop is less significant, thus enhancing overall efficiency. Additionally, this design can be compared to a previous example [ref. 1] which incorporated secondary side resonance and operated over similar line, load, frequency and power variations.
9-211
APPLICATION NOTE
U-1178
Half cycle conduction in both design examples accomplishes a undirectional current flow at each of the primary switches. Unlike its full counterpart, all the energy stored in the resonant capacitor must be transferred to the output, without returning the excess back to the primary storage capacitors.
~ +VIN c1 LR1
+VIN 2
T1
o,
c +
2
j_j
ov
Np,Ns
"2
Lo
I OUT
crv: 0 "'" .
The UC3860 resonant control IC will adjust the conversion frequency to regulate the fifteen volt output over all line and load combinations. Zero current switching is facilitated by modulating the programmed maximum on-time with the controller's uncommitted comparator. In addition, overload protection is provided by means of a programmable restart delay circuit (hiccup) which reduces the conversion retry rate following a fault detection.
DESIGN SPECIFICATIONS An off-line 150 watt, single output design has been selected as a typical application. Several items common to most designs will not be highlighted, for example, primary to secondary isolation and input filter calculations.
INPUT VOLTAGE
110 VAC INPUT= 85 MIN, 132 MAX (VAC)
220 VAC INPUT= 170 MIN, 270 MAX (VAC)
DC INPUT= 220 MIN, 380 MAX (VDC)
AC LINE FREQUENCY= 50 HZ MIN
OUTPUT VOLTAGE= 15 VDC
OUTPUT CURRENT= 10 AMPS MAXIMUM CONTINUOUS, 2.5AMPSMIN
LINE REGULATION= 15 MILLIVOLTS
LOAD REGULATION= 15 MILLIVOLTS
OUTPUT VOLTAGE RIPPLE=
100mV (Pk-Pk), DC-20 MHZ
EFFICIENCY= 75% TYP. AT FULL LOAD
TOPOLOGY FUNDAMENTALS AND OVERVIEW The general circuit diagram for a quasi-resonant half bridge converter using primary side resonance is shown with the corresponding waveforms. Transistors Q1 and Q2 are alternately driven from the control circuitry at a repetition rate determined by the UC3860's error amplifieroutputvoltageandturned off at zero current by the detection circuitry.
Transistor Q1 turns on at time t(O), connecting the series resonant L C tank across the bulk storage capacitor .C1, with a voltage potential of +Vin/2. The primary current ramps up linearly at the rate
of +Vin/(2*Lr) from zero to lout/N which is intersected at time t(1 ). During this interval dt(1-0) all primary current is delivered to the output, and no voltage is across the resonant capacitor Cr.
Beginning at time t(1 ), primary current can be expressed by adding the two individual components; the "constant" output current lout/N, andthe sinusoidal current {Ir) flowing through the resonant capacitor. The peak resonant current is determined by the iput voltage(+ Vin/2) divided by the characteristic tank impedance, Zn. Primary current rises to its peak of Ir plus lout/N, and decreases sinusoidaly. It intersects the output current (lout/N) again at time t(2), and crosses zero at time t(3) when the transistor switch is turned off.
In asinuosidal manner, the resonant capacitor voltage begins its rise at time t(1) and continues to its peak at time t(2). The voltage then decreases until time t(3) where it then begins a linear discharge at the rate of lout/Cr. Zero voltage is reached at time t(4) when all stored charge in the resonant capacitor has been transferred to the output. This waveform is also the transformer primary voltage, and is reflected to the secondary side by the turns ratio N.
Secondary current has a linear leading edge until reaching its plateau of lout, assuming a negligible magnetizing current for the output inductor. The resonant capacitor provides a constant current to the output until its charge is totally transferred. At this point, the energy is stored in the output LC section provides a regulated output until the next cycle is initiated. Consecutive switching cycles will repeat the conversion process and corresponding waveforms.
VGs10~ VGS2o~
V(Q1) IPRI
+V1N121--~-f--------,,- -- · -VIN/o 2 --~ 1 1-- ---- ----- ----~ ---
1PK - - 1 f - - - - - - - - - - - - - -
10/N
0 -IO/N
-lpK
+Vp
Vxfmr
lxfmr
-Vp lo;N
-lo;N
+Vp/N
Vxfmr
0
sec
-Vp/N
WAVEFORMS
9-212
APPLICATION NOTE
U-1178
QUASI-RESONANT CIRCUIT LIMITATIONS
In order to facilitate zero current switching, the peak resonant current component l(r) must always be greaterthan lout, or the zero inersect will not be reached. Specifically, the output impedance (Zo) must always be greaterthan the characteristic tank impedance, (Zn). This relationship also specifies the minimum input voltage (Vin min) and maximum output current (lout) limits for proper circuit operation.
The ideal ratio of the full output current (lout max) to the minimum resonant peak current lr(peak) min is unity. This insures resonance at all loads while preventing excessively high peak resonant tank currents, and losses. A twenty-five percent overload current will be used as a guardband in this design. Typical of many current limit thresholds, it corresponds to an 0.75:1 ration of lout(max) to lr(peak)min.
i ---------- -
IR(PK)
l_ -- ---
10
NOTE Zero crossing does not occur when I OUT >I R(PK)
11
12
To satisfy the required output volt-second product of this Buck derived converter at low line:
Vout = 'P_rh K(t>, or N = K(t) " [Vp (min) ::: V!os~ = 5.1: 1
2 * N
2 ,,, ( Vo + Vd + Vloss)
More specifically, the turns ratio can be calculated by examining the
total charge transferred per cycle, Q(t). This varies as a function of
Vin, lout and Vout, assuming C(r) is fixed and zero current switching.
[ref 2] Using the specified parameters for this design, the
relationships are combined and the quadratic equation is solved,
resulting in a turns ratio (Np/Ns) of 5.1: 1 also. The design will
proceed using a 5:1 ratio for simplicity.
j f'.f [ Lrs ,,, lo _Tc + N (Vpri -_\.:'XL + _f~_:.(Vp__::: \/~)2 = O
(Vo+Vd)
4·:·Fr,,(Vo+Vd) 2o(Vo+Vd),,/o
where Tc= 1/Fconv(max) = 1us; Vx= Vloss primary MOS switch
Vd=Vrectifier (output); lo=lout maximum
and Vpri=Vp(minimum)
MAIN TRANSFORMER DESIGN
Off-line transformers lend themselves to low, wide bobbin windows, typical of the ETD geometry. This shape window provides adequate room to accomodate the creepage and clearance distances required for international safety specifications. Transformer losses will be held around one-percent of the total input power, or approximately 2 watts with a temperature rise not to exceed 40 degrees Centigrade. A core size is selected with a thermal impedance R(t) in the neighborhood of 40°C/2W, or 20°C/W. The precise size will be calculated using the area-product formula for core-loss limited conditions, typical in a high frequency power supply.
Being a Buck derived topology, the secondary input and output volt-second products must be equal, thus defining Vin (secondary) minimum. The resonant tank inductor and capacitor can be transposed to the secondary also, and calculated knowing Vin min(sec), F(res) and Z(o)min. Once the transformer turns ratio has been determined, these can be appropriately scaled to the primary side.
The resonant L-C components are now uniquely defined by:
L("'
75* Vsec(min) 0.12Vsec(min) 175 H
,,sec- 2 *Ph Fres" lout- Fres" lout(max)
n
C(r)sec = 1 [(2*Pi*Fres)2*L(r)=91 nF
Z(r)sec = (L(r)/C(r))05 = 1.39 ohms,
and Fres = 1.25 MHz
TRANSFORMER TURNS RATIO
The determination of the transformer turns ratio for this design will begin similarly to that of conventional square wave converters. Obviously, the required output volt-second product must first be satisfied with the most difficult condition being low line and full load. A topology coefficient, K(t) is introduced to specify the maximum ratio between the conversion (switching) frequency and the resonant tank frequency. This is somewhat analagous to maximum duty cycle is a square wave converter. As K(t) approaches unity, the utilization is maximized and turns ratio is optimized.
Charge is taken from the bulk storage capacitors during each cycle and stored in the resonant capacitor. The output load discharges this at a rate determined by the output currrent, and the discharge time varies inversely with load current. Atfull load, the minimum discharge time is reached, reduceing the topology coefficient, K(t), to 0,8 in this application.
* AP=
[
P1;n20
K120f4
]
1 58 .
"(K
hf+Kef
2
o.66
)
cm 4
WHERE:
Pin = Input Power - 180 Watts
K =Winding Factor= 0.163 for a half bridge
f = Transformer Frequency = 500 KHZ
Kh =Hysteresis Coefficient= 4*10'-5 for 3C85
Ke= Eddy Current Coefficient= 4·10·10 for 3C85
A calculated area-product of 0 .543 cm4 steers the selection towards the ETD-34 geometry and size, and 3C85 material. Since the core volume is slightly larger than required, the actual core losses (per cm3) will be lower than first estimated.
Calculating the volt-second product for this primary side resonant design is more difficult than for that of its secondary side counterpart. Integrating the complex voltage waveform over the conversion period is the most exact method, as detailed in the charge transfer equations [ref2]. A less precise, yet fairly accurate technique is to assume a triangular voltage waveform, breaking the period into on-time and off-time sections. Addition of these geometric areas (V*1) results in an estimate of the actual primary volt-second product. Core losses will need to be analyzed over the full range of line, load and conversion frequency ranges. The minimum number of primary turns will be calculated using low line conditions, and the cross sectional core area of 0.971 cm2. A total flux density swing of 1 kiloGauss (per manufacturers data) is recommended not to exceed the allocated temperature rise.
Np(min)
PrimaryV * t product· 104 F/uxSwing * CoreArea
9-213
APPLICATION NOTE
U-1178
Using low line condition and 10V MOS drop.
N ( . ) 0.5·200·10-6·104 10 3 7i P mm - 0.100 T·0.971 crri3 = · urns
(Use 1OTurns)
The actual core power density is calculated from the following equation, allowing a 20 degree temperature rise due solely to core losses.
.
T,
2o·c
,., rri3
Power Density- Rr. Vol- 19 . 7.64 = 138m..1c
The manufacturers core data lists the thermal resistance of the ETD-34 core set as 19 degrees C per watt, with a core volume of 7.64 cm3. Several methods of dividing the power losses between core and copper loss can be used. The most common of these suggests an almost equal split between the two, allowing slightly more core than copper loss if possible. An even division of the total losses between the two will be utilized in this design as a first approximation. Later, an evaluation of the minimum number of turns and wire sizes may suggest that the 50/50 ratio be changed to favorably accommodate fewer turns, or less copper.
It has already been established in a previous section that the turns ratio for this design be 5:1, Npri: N sec. Minimization of the leakage inductance is obtained by "sandwiching" the secondaries between the primaries, or using a split primary winding technique.
In this example, one-half of the primary number of turns will be wound first, closest to the core center leg. Then, the corresponding secondary is wound directly above its primary, followed by the other secondary. The final winding is the remaining primary half, with good coupling to its corresponding secondary as shown in the following figure.
WINDING ORIENTATION
Copper strap or foil will be utilized for each winding to minimize "build-up" which increases the distance between windings, hence leakage inductance. The necessary primary and secondary copper areas are calculated using their respective currents divided by 450 amps/cm2 for a low temperature rise. Other transformer specifics are calculated below.
PRIMARY RMS CURRENT, I pri(rms) = 2.8 AMPS RMS
SECONDARY RMS CURRENT 1sec(rms) - 7.1 AMPS RMS (EACH WINDING)
PRIMARY CONDUCTOR AREA AXp = lpri(rms)/450 A/cm3 = 6.33*1 ff3cm2
SECONDARY CONDUCTOR AREA AXs = 1sec(rms)/450A/Cm3 =15.8*10"3cm2
PRIMARY INDUCTANCE, Lpri = Al*Np2 = 190 uH
SECONDARY INDUCTANCE, Lsec = Al*Ns2 = 7.6 uH (each)
The primary conductor area is approximately equal to that of an AWG #19 wire, while the secondary area is closest to an AWG #14 wire. From Eddy Current calculations is can be seen that the depth of penetration at 500KHZ is 10.6*10·13 cm, or about the thickness of an umber 37 AWG wire. The most practical technique to minimize the AC loss in a transformer winding is to incoporate copper strip, or foil, as in this design. Its width is determined by the bobbin width and safety spacing requirements of 8 mm per winding as shown.
An 8 millimeter primary to secondary spacing between the winding ends will be subtracted from the bobbin width of 2.1 cm, leaving 1.30 cm for the copper strap width. Allowing for tolerances, standard half-inch (0.500") width foil will be utilized in this design.
Standard 2 "mil" (0.002 in) foil will be used for the primary, which is slightly larger than the required thickness of 1.872 thousandths of
an inch. The calculated secondary thickness exceeds the depth of penetration, so twin foils each of half the required thickness (0.0085 cm) are mandated. Each of the three "mil" (0.003") foils will be thinly insulated from the other.
The resistance and power loss of each winding is summarized:
R pri = 2.29*1 o-6 · 5.99 *10 T/6.18 *10·3 = 22.2 milliohms. R sec = 2.29*1 o·6 *5.99*2T/21.91 *1 ff3 = 1.25 milliohms
Winding power loss = 1 rms2 (winding)· Resistance (winding
Ploss pri = 2.82 · 0.0222 = 174 milliwatts (each wdg)
P loss sec = 7.1 2 · .125*1"3 = 63 milliwatts (each wdg)
Ploss copper= 2*(174 + 126 mW)= 0.60 watts Transformer power loss = copper + core loss = 1.5 watt total
Temperature rise = R(O) ·Ploss total = 19°C/W · 1.5 = 28.5'C
I~
2.101 cm (.827") ~
'1 "" 1.30 cm (0.512")
. 1/2 Primary - 5 turns
·
-·- copper strip 0.002" x 0.500"
T
---== Secondaries - 2 turns x 2 turns copper strip 0.003" x 0.500"
-· · ·
-·-·· 1/2 Primary - 5 turns
copper strip 0.002" x 0.500"
ETD-34 Bobbin
Insulating mylar film 2 ml thick 0.8 in. wide between each turn
DESIGN PROCEDURE AND SUMMARY
The resonant components can now be transformed to primary side values using the caluclated turns ratio N.
L(r)p = L(r)s. N2 = 4.4 UH
C(r)p = C(r)s I N2 = 3.6 nF
Z(r)p - [ (L(r)p I C(r)p)0·5] = 35 ohms
Additionally, the peak primary current and rms currents at the transistor switch, transformer primary and secondary rectifiers are calculated by the following relationships:
l(p)pk =[lo(max)/N) + Vp(max)/(2*X(r)p) =5.2A
@220V, 7.4A@380V
l(p)rms = l(p)pk*[Ton/(2*Tconvo0·5 = 2.85 Arms at XFMR primary (assume pulsed sinusoid) = 2.01 Arms at each switch
l(s)rms = l(o)max*[(Ton/Tconv)0.5) = 7.8Arms at XFMR secondary
=5.5Arms per rectifier
The selection of semiconductors, rectifiers, heatsinking requirements and wire gauges follow standard design practices. For the purpose of this paper, no elaboration is included, however is detailed in references 1 and 2. Using this design equations listed previously and in the Appendix, these parameters can be calculated and plotted over the line and load ranges specified, and are summarized in the following graphs:
9-214
APPLICATION NOTE
U-1178
AVERAGE dV/uC = 5.935 V/uC; and the average dl/uC = 2.086NuC
The energy transferred per cycle is obtained by multiplying the
results from the charge calculations by Vin I 2 to convert from charge
to energy, with the results shown below.
lpri
(A)
ENERGY TRANSFERRED PER CYCLE
TIMING CONSIDERATIONS The operation of this quasi-resonant circuit has been described as requiring a variable frequency, FIXED on-time control pulsetrain. In actuality, the on-time must be varied to facilitate zero current switching with changes in input voltage and output current. Using the timing relationships presented in chapter five, the on-time is calculated and plotted for the ranges of Vin and lout.
ON-TIME vs. Vin AND lout
580 , - - - - - - - - - . - - - - - - - ,
420 :rl===~;;~=E==~lo~=2~.5~A=:d
220
300
380
V1N (V)
The charge transferred from the primary to the secondary per cycle is a function of both Vin and lout. Using the equations presented previously in section 5, the results are graphically represented in the following figure.
~~ fa~ a: u
ffi ffi 150 -+------+--""'-=..>-;~~""'-1
u. o._
<zJ>wen
<( _J
g>-: 5--, 100-+----~---~-+..,---------<
<a:!JaO: WU
ifi ~ 50 +':;_----+-------l
220
300
380
V1N (V)
The conversion period is obtained by dividing the energy transferred per cycle by the output power, accounting for an overall efficiency near 85%. Conversion frequency, its inverse, is graphically depicted for various input voltages and output currents below.
CONVERSION FREQUENCY
The control circuit adjusts the conversion frequency to maintain a
constant output voltage of V out over changing line and load
combinations. Maximum conversion frequency will occur at low line
and full load, where, by design, the frequency equals the resonant
tank frequency divided by K(t). Minimum frequency will occur at high
line (Vpri max) and light load (lout min), and the following equation
can be used to estimate the conversion frequency for various line
l and load possibilities.
Tconv = vpri [2·:·N:·Lrsdo2 + Vpn. -··C-rs + -lo-
2.,N·:·/O*VO
Vpri
N 2·:·Fr
which can be expanded to account for losses in both the primary switches (Vx) and output rectifiers (Vd) and reduced to:
Tconv = Lrs'-'ICJ_ + _ Crs".(\ff>::\ld_ + _____\lp-_\I)(__ Vo-Vd 2"N2·:·/o.,(Vo-Vd) 4·:#,FP(Vo-Vd)
Transferred Charge vs. Vin and lout
CONVERSION FREQUENCY vs. Vin & lout
For the selected values of voltage and current shown, the average change required in voltage or output current per micro Coulomb transferred have been calculated.
N 1Q r :>:'. 9
0
x0 8
z:> 7
u 0
u. wCl 5
~ 4 :g::> 3
(§
9-215
U-1178
OUTPUT FILTER DESIGN
The output inductor will be designed for one amp of ripple curr.ent at the minimum conversion frequency of approximately 200 KHZ equatingto90 uH. Duetothevariablefrequency operation, the ripple current will change inversely with operating frequency, as maximum load occurs, the ripple current is at its lowest. A 1.3" o.d. toroidal core of high frequency material was utilized, available as a standard product from Pulse Engineering.
For the output capacitance, two 100 uf electrolytic capacitors were used in parallel to achieve an ESR value of 3 to 15 milliohms - a broad range necessitated by the difficulty in getting specified high frequency data from capacitor manufacturers. A final component added to the outputfilter is a good high frequency capacitor to bypass the inductive components of the electrolytics and shunt any switching spikes which might get to the output. Unitrode "P" type ceramic monolythic capacitors are used for this application.
THE UC3860 RESONANT MODE CQNTROL IC
The versitile UC3860 resonant mode controller easily implements fixed on-time, frequency modulated control schemes while providing various user programmable features and unique fault protection. Specifically, this 3 MHz device includes dual 3 amp peak totem pole output drivers and precision clamps on the 5 MHz error amplifier output to accurately control minimum and maximum frequency. In addition, an uncommitted comparator is included for use with zero current switching techniques, and programmable fault thresholds and logic for reduced losses during over.load conditions. Preset undervoltage lockout thresholds of 17/10 volts are optimized for off-line designs, but are easily reprogrammed by the user for other applications.
Each of the UC3860 functions are utilized in this design and have been previously highlighted in the references. Zero current de.tection and switching is performed by connecting the uncommitted comparator's output to the one shot timing network, a technique which allows a programmed maximum on-time that can be modulated as zero current is crossed. Any propagation delays can effectively be "nulled-out" with the addition of anticipator circuit detailed in references 1 and 2. A programmable restart delay following the receipt of a fault condition, often referred to as "hie-cup" has been incorporated in addition to soft start,. which gradually increases the conversion frequency in a resonant converter. The UC3860 provides complete regulation and control for this 150 watt design over all line and load combinations.
CLOSING THE LOOP
There are several gain stages in the quasi-resonant control loop, and each. will be examined to obtain good closed loop circuit response. The block diagram below displays the various gain stages.
POWER STAGE
The small signal gain of the power stage will be approximated by analysis of the charge transferred at various line and load combinations. An assumption is made that the power switch on-time is constant, and any changes in frequency directly effect the off-time, or resonant capacitor discharge time. Additionally, both Vin and lout are assumed to be constant during the interval of interest.
Tabulated below at several points of interest are the values for this gain, obtained from the results of previous sections for work don~ in the references. The gain of the power stage (1n volts per hertz) vanes significantly over the input and output ranges, and the highest value will be used to approximate the worst case condition.
V IN sec(V) 22 38 22 38 22 38 22 38
I OUT (A) 2.5 2.5 5 5 7.5 7.5 10 10
Win uJ/cyc
50 140 60 160 78 185 91 205
F conv KHZ 450 180 730 320 900 450 1000 560
GAIN Vusec
9.0 10.1 8.76 10.7 9.65 11.3 9.55 11.8
GAIN (db) 19.1 20.1 18.9 20.6 19. 7 21.1 19.6 21.5
A slightly greater than worst case value of 23 volt-microseconds will be used for the power stage. Multiplying this by.the VFO gain of 0.4 Mhz/v results in an combined gain of 9.2 Vout I Vea out.
+40~~~~~~~~-.-~~.--~-..~---,
+20~~~1--~-+-~--1~~-+-~--11--~~
....... o~..,....,..=::1 -==-===--+-~~r,-,-.,-:;;ct-~--j
-20-===:t=::::::l===+~*==+===l
-40~~~-l--~-+-~--11--~-1"~~1--~~
...... -60~~~-l--~-+-~--11--~-r~
1--~~
-ao~~~~~-1-~-+~~+--~-flll;&..,..-i
10 100 1K 10K 100K 1MHZ FREQUENCY (HZ)
100.0
BLOCK DIAGRAM - CONTROL LOOI) REF
:a .o
:!!.
z
~
·100.0
1 K
FREQUENCY (HZ)
9-216
APPLICATION NOTE
U-1178
POWER SUPPLY PERFORMANCE
This 150 watt quasi-resonant supply performed flawlessly over its specified parameters, attaining the overall full load efficiency goal of 80%, however, only at low line. A decrease to 75% was seen as high line was approached, an indication that more attention to high dV/dt losses should be exercised. Nevertheless, low switching noise, quasi-sinusoidal power waveforms and substantially reduced EMI are worthwhile benefits, especially over conventional square wave converters. The relavent primary voltage and current, in addition to secondary voltage waveforms are displayed. These plots were obtained using a 250 MHz bandwidth digitizing scope, UHF measurement techniques and no bandwidth limiting or waveform averaging to distort the high frequency components.
SUMMARY AND CONCLUSIONS
The ultimate blend of high power density with high efficiency and low noise is realizeable today using quasi-resonant techniques, conventional topologies and existing components. In most applications, the upgrade is quite simple, as many of the devices go unchanged in the process. The control circuit. on the other hand, requires a far more sophisticated controller than for its square wave predecessors. Additionally, as switching frequencies are further pushed towards and beyond a megahertz, the needs for even higher performance and higher speed control logic become increasingly obvious. The UC3860 resonant mode controller exceeds these requirements, simiplifying and condensing the control circuit design process to resistor and capacitor value selections.
VPRI
100v 0
IPRI
2A
0
Vo
(AC) 50mv
T = 500NS
REFERENCES
1. ANDREYCAK, W. "3 MegaHertz Resonant Mode Control IC Regulates 150 Watt Off-line Power Supply"; HFPC 1988
2. ANDREYCAK, W. "1 MHz 150 Watt Resonant Converter Design Review", Unitrode Power Supply Design Seminar; SEM-600A
3. VINCIARELLI, P. "Forward Converter Switching At Zero Current", US. Patent #4,415,959
4. INTERTEC COMM. PRESS, "Recent Developments in Resonant Power Conversion ", 1988-various authors and papers
5. MAMMANO, R. "Resonant Mode Converter Topologies", Unitrode Power Supply Design Seminar: SEM-600A
6. WOFFORD, L. "UC1860 - New IC Controls Resonant Mode Power Circuits", APEC 1988
7. Unitrode IC Corp. acknowledges and appreciates the use of this paper from the 1990 "High Frequency Power Conversion" conference.
Construction ofthe power conversion stage was accomplished using the Unitrode UC3860 demonstration kit printed circuit board, with ample facilities to accomodate a variety of quasi-resonant topologies and configurations. The control section was built using the UC3860 evaluation kit p.c. board, and interconnections to the gate drive and current sense transformers made with 75 ohm coaxial cables. An auxiliary winding from the main transformer and opto-coupled feedback were later added to this design for complete primary to secondary isolation.
Unitrode Integrated Circuits Corporation 7 Continental Boulevard. ·P.O. Box 399 ·Merrimack, New Hampshire· 03054-0399 Telephone 603-424-2410 · FAX 603-424-3460
9-217
n nINTEGRATED
~CIRCUITS
-UNITRDDE
9-218
~
-
INTEGRATED CIRCUITS
UNITRODE
APPLICATION NOTES
U-118
NEW DRIVER ICs OPTIMIZE HIGH SPEED POWER MOSFET SWITCHING CHARACTERISTICS
Bill Andreycak UNITRODE Integrated Circuits Corporation, Merrimack, N.H.
ABSTRACT
Although touted as a high impedance, voltage controlled device, prospective users of Power MOSFETs soon learn that it takes high drive currents to achieve high speed switching. This paper describes the construction techniques which lead to the parasitic effects which normally limit FET performance, and discusses several approaches useful to improve switching speed. A series of drivers ICs, the UC3705, UC3706, UC3707 and UC3709 are featured and their performance is highlighted. This publication supercedes Unitrode Application Note U-98, origionally written by R. Patel and R. Mammano of Unitrode Corporation.
INTRODUCTION
An investigation of Power MOSFET construction techniques will identify several parasitic elements which make the highly-touted "simple gate drive" of MOSFET devices less than obvious. These parasitic elements, primarily capacitive in nature, can require high peak drive currents with fast rise times coupled with care that excessive di/dt does not cause current overshoot or ringing with rectifier recovery current spikes.
This paper develops a switching model for Power MOSFET devices and relates the individual parameters to construction techniques. From this model, ideal drive characteristics are defined and practical IC implementations are discussed. Specific applications to switch-mode power systems involving both direct and transformer coupled drive are described and evaluated.
POWER MOSFET CHARACTERISTICS
The advantages which power MOSFETs have over their bipolar competitors have given them an ever-increasing utilization in power
systems and, in the process, opened the way to new performance levels and new topologies.
A major factor in this regard is the potential for extemely fast switching. Not only is there no storage time inherent with MOSFETs, but the switching times can be user controlled to suitthe application. This, or course, requires that the designer have an understanding of the switching dynamics inherent in these devices. Even though power MOSFETs are majority carrier devices, the speed at which they can switch is dependent upon many parameters and parasitic effects related to the device's construction.
THE POWER MOSFET MODEL
An understanding of the parasitic elements in a power MOSE FT can be gained by comparing the construction details of a MOSFET with its electrical model as shown in Figure 1. This construction diagram is a simplified sketch of a single cell - a high power device such as the IRF 150 would have - 20,000 of these cells all connected in parallel.
In operation, when the gate voltage is below the gate threshold, Vg(th), the drain voltage is supported by the N-drain region and its adjacent implanted P region and there is no conduction.
When the gate voltage rises above Vg(th), however, the P area under the gate inverts to N forming a conductive layer between the N+ source and the N-drain. This allows electrons to migrate from source to drain where the electric field in the drain sweeps them to the drain terminal at the bottom of the structure.
SOURCE CONTACT
DRAIN
DEPLETION EDGE N+ DRAIN CONTACT
SOURCE
FIGURE 1 - SIMPLIFIED CROSS SECTION OF A POWER MOSFET CELL AND ITS ELECTRICAL EQUIVALENT. 9-219
U-118
In the equivalent model, the parameters are defined as follows:
1. Lg and Rg represent the inductance and resistance of the wire bonds between the package terminal and the actual gate, plus the resistance of the polysilicon gate runs.
2. C1 represents the capacitance from the gate to both the N+ source and the overlying source interconnecting metal. Its value is fixed by the design of the structure.
3. C2 + C4 represents additional gate-source capacitance into the P region. C2 is dielectric capacitance and is fixed while C4 is due to the depletion region between source and drain and varies with the gate voltage. Its contribution causes total gate-source capacitance to increase 10-15% as the gate voltage goes from zero to Vg(th).
4. C3 + C5 is also made up of a fixed dielectric capacitance plus a value which becomes significant when the drain to gate voltage potential reverses polarity.
5. C6 is the drain-source capacitance and while it also varies with drain voltage, it is not a significant factor with respect to switching times.
EVALUATING FET PARASITIC ELEMENTS
Although it is clearly not the best way to drive a power MOSFET, using a constant gate current to turn the device on allows visualization of the capacitive effects as they affect the voltage waveforms. Thus the demonstration circuit of Figure 2 is configured to show the gate dynamics in a typical buck-type switching regulator circuit. This simulates the inducitve switching of a large class of applications and is implemented here with a IRF-51 OFET, which is a 4 amp, 1OOV device with the following capacitances:
Ciss ~ C1 + C4 + C5; 135 -150 pF
Crss ~ C5
; 20 - 25 pF
Vgs ; OV
Coss= C5 + C6 ; 80-100 pF
CIN
100uf
IRF510
L;1mH
USO 945
Co;5V LOAD 2.50HMS
45V
o__fl____fl
l~suse/I
FIGURE 2- SWITCHING TIME EVALUATION CIRCUIT.
In this illustration, the load portion of the circuit is established with Vin ; 25V. lo ; 2A. and f; 25Khz. The resultant turn-on waveforms
are shown in Figure 3 from which the following observations may be made:
FIGURE 3-FET TURN-ON SWITCHING CHARACTERISTICS WHEN DRIVEN WITH A CONSTANT GATE CURRENT
1. For a fixed gate drive current, the drain current rise tiime is 5 times faster than the voltage fall time. 2. There is a 10-15% increase in gate capacitance when the gate voltage reaches Vg(th). 3. The gate voltage remains unchanged during the entire time the drain voltage is falling because the Miller effect increases the effective gate capacitance. 4. The input gate capacitance is approximately twice as high when drain current is flowing as when it is off. 5. The drain voltage fall time has two slopes because the effective drain-gate capacitance takes a significant jump when the drain-gate potential reverses polarity. 6. Unless limited circuit inductance, the current rise time depends upon the large signal QM and the rate of change of gate voltage as 8ld; QM 8Vg CHANGES IN EFFECTIVE CAPACITANCE The waveform drawings of Figure 4 illustrate the dynamic effects which take place during turn-on. As the gate voltage rises from zero to threshold. C2 is not significant since C4 is very small. At threshold, the drain current rises quickly while the drain voltage is unchanged. This, of course, is due to the buck regulator circuit configuration which will not let the voltage fall until all the inductor current is transfered from the free-wheeling diode to the FET. While the drain current is increasing, there is a slight increase in the gate capacitance due to the large current density underneath the gate in the N-region close to the P areas. As the drain voltage begins to fall, its slope depends upon gate to drain capacitance and not that from gate to source. During this time, all the gate current is utilized to charge this gate to drain capacitance and no change in gate voltage is observed. This capacitance initially increases slightly as the voltage across it drops but then there is a significant jump in value when the drain falls lower than the gate. When the polarity reverses from drain to gate, a surface charge accumulation takes place and the entire gate structure becomes part of the gate to drain capacitance. At this point the drain voltage fall time slows for the duration of its transition.
9-220
U-118
'_j_
Vgs
0
-t
Vcts
Ids
Vgs
0
0
tn---.
tct
Vgs
tr
@Vct2
1 .,...__tfv-.....
-. !fv +---
-C1+C2 +C3 ::;480 pF
GATE CURRENT @102
+--- C 1 + Cs + C 2"' 230 pF
0
Cgd
~~~~++-+-+-~~---1--~~ C1 -Cs::;150pF
C3 "'300 pF
Cgd
J
~~~~~~-'-~~~~ Cs"'25pF
FIGURE 4 - Parasitic CAPACITANCE VARIATION FOR A UFN51 O MOS FET DURING TURN-ON
AN OPTIMUM GATE DRIVE In most switching power supplly applications, if a step function in gate current is provided, the drain current rise time is several times faster than the voltage fall time. This can result in substantial switching power losses which are most often combated by increasing the gate drive current. This creates a problem, however, in that it further reduces current rise time which can cause overshoot, ringing, EMI and power dissipation due to recovery time for the rectifiers which are much happier with a more slowly changing drain current.
In an effort to meet these conflicting requirements, an idealized gate current waveform was derived based upon the goal of making the voltage fall time equal to the current rise time. This optimum gate current waveform is shown in Figure 5 and consists of the following elements
FIGURE 5 -AN "IDEAL" GATE CURRENT TURN-ON DRIVE TO PROVIDE EQUAL CURRENT RISE AND VOLTAGE FALL TIMES WITH AN INDUCTIVE LOAD
1. An initial fast pulse to get the gate voltage up to threshold.
2. A lesser amount to slow the drain current rise time. This value however, will also be a functiion of the required drain current.
3. Another increase to getthe drain voltage to fall rapidly with a large current pulse added when the drain gate potential reverses.
4. A continued amount to allow the gate voltage to charge to its final value.
Obviously this might be a little difficult to implement in exact form, however, it can be approximated by a gate current waveform which, instead of being constant, has a rise time equal to the desired sum of the drain current rise time and the voltage fall time, and a peak value high enough to charge the large effective capacitance which appears during the switching transition. The peak current requirement can be calculated on the basis of defining the amount of charge required by the parasitic capacitance through the switching period.
A linear current ramp will deliver a charge equal to
a~ Ip ·ton 2
where we define
ton~td+tn+tfv
The total charge required for switching is
Q ~
Ciss
[Vg (th)
-
_Jcl_]-Crss
QM
[Voo-Vg
(th)]-CrssV9 (th)
9-221
U-118
where Crss' is the gate-drain capacitance after the polarity has reversed during turn-on and is related to Ciss by the basic geometry design of the device. A reasonable approximation is that Crss'-1.5 Ciss. With this assamption.
Ip- -2t[Ciss (2.5Vg(th) + _lfl) + Crss(Voo-Vg(th) ))
on
gM
As an example, if one were to implement a 40 V. 1OA buck regulator with a UFN150, it would not be unreasonable to extend the total switching time to 50 nsec to accomodate rectifier recovery·time. An optimum drive current for this application would then take 50 nsec to ramp from zero to peal< value calculated from
Ciss - 2000pF Crss - 350pF Vg (th)= 3V
ton - 50nsec vaa = 40V Id= 10A
gM= 10A =4S 2.5V
as ·
Ip=
-50-x21-0--9
(2000x10-12
(2.5
x3
+
14°)
+
350x10-12
(40-
3))
:. Ip= 1.32 amps peak
The above has shown that while high peak currents are necessary for fast power MOSFET switching, controlling the rise time of the gate current will yield a more well-behaved system with less stress caused by rectifier recovery times and capacitance. This type of switching requirement can be fulfilled with integrated circuit technology and several ·iC's have been developed and applied as MOSFET drivers.
TOTAL GATE CHARGE (Qg)
Another approach used to quantify and understand MOSFET gate drive requirements is much simpler than that of examining the instantaneous voltages, currents and capacitances. The term "Total Gate Charge", or Qg specifies the amount of gate charge required to drive the FET gate-to-source voltage (Vgs) from zero·to ten volts; or vice-versa.. For most high voltage devices, these thresholds correspond to the FET being either completely on or off.
Charge (Q) · can be expressed as the product of either current multiplied by time (l"T), or capacitance multiplied by voltage (C*V) in the units of Coulombs. Most contemporary devices have total gate charge requirements in the tens to low hundreds of nano Coulombs, dependent almost entirely on die's geometry. For example, an IAF710 (size 1) FET has a total gate charge requirement of only 7. 7 nC whereas the IAFP460 (size 6) demands 120 nC, and both are typical values.
PARAMETER IRFP440
IRFP.450
IRFP4.60
Qgs (NC)
6.2
11
18
Qgd (NC)
22
43
62
Qg (NC)
42
86
120
Ciss(Nf)
1.3
2.7
4.1
There are two specified parameters contained within the total gate charge expression; Qgs, the gate-to-source charge, and Qgd the gate-to-drain, or "Miller" charge. Qgs is the amount of charge required to bring the gate voltage from zero up to its threshold VGS (th), of approximately 6 volts. Qgd defines the.amount ofcharge that must be input to overcome the "Miller" effect as the drain voltage falls. This occurs during the plateau of the gate-to-source voltage waveform where the voltage is "constant". Excess charge is added to lower the effecive Ads (on) until the gate voltage reaches 1Ovolts, wher Qg is specified. Further increases above this level do NOT lower Ads (on), so a 10-12 volt driver bias is ideal.
The total charge curve can be examined in sections to define the ideal driver's characteristics. Using a constant current of 1 ampere, the total charge curve (Qg=l*T) in nanoCoulombs also represents the MOSFET turn-on delay, drain current rise and drain voltage fall times in nanoseconds.
Gate-Source Voltage vs. Gate Charge
14
12
Vgs 10 (Volts) 8
6
4
2
0
0
40
80
120 160 200
I GATE CHARGE (NANO COULOMBS)
.. ·1 14---- Qg
logs<I ogd
-------.1 ·I
I
I
I
0
40
80
120 160 200
TIME (NANOSECONDS) WITH 1AMP DRIVE
First of all, and most importantly, the average capacitive load represented by the FET to the IC driver Is NOT the specified MOSFET input capacitance, Ciss. The effeclve Input capacitance, Ceff, Is the total charge divided by the final gate voltage, Vgs(f);
Ceff = Qg(total) I Vgs(f).
Using the total gate charge curve show above, the 460 FET with Vds (off) = 400 volts has an effective input capacitance (Ceff) of approximately 120nC/1 Ov, or 12 nF during the interval of O< Vgs < 1ov. The specified input capacitance of Ciss = 4.1 nF applies only at Vgs=O, and is often mistaken for the driver's actual load.
The Qgs portion of the curve is primarily governed by the driver's ability to quickly turn ON. Therefore, a sharp, fast transition of the totem-pole output from low to high is essential to minimize the delays from O < Vgs < VGS (th). In most applications the driver IC is not peak current limited during .this interval, since its is more likely to be dV/dT limited. The effective gate (load) capacitance is approximately
Qgs I VGS(th), or Ciss.
Evident from the charge specifications, most of the popular size FETs used in switch-mode power supplies (sizes 4. 5 and 6) have much larger Qgd demands than their gate-to-source counterpart, Qgs. During this Qgd interval, the gate voltage remains "constant" while gate charge accumulates and the drain voltage collapses. It is also during this period that most drive circuits are simply peak current limit, whether by the driver IC or an external resistor. High peak currents are necessary for fast transitions through this interval, especially when driving large geometry FETs.
Full drain current is flowing at the beginning of the Qgd portion of the Qg curve, and notjce that the drain voltage remains high. FET power loss is at its maximum here, and decreases linearly with Vds. A majority ofthe Qgd charge goes to combat the "Miller" effects as the drain voltage falls from that of its off condition to Vgs, or approximately Vgs(th). The remainder of the charge is used to bring the drain voltage down below that of the gate, decreasing the
9-222
U-118
effecive gate capacitance over the Qgd interval since there is relatively no change in gate voltage. The important fact, however, is that high peak currents are needed to minimize the FET power loss and transition time.
The remainder of the gate charge brings the gate voltage from VGS (th) to 10 volts. This "excess" charge reduces the FET "ON" resistance to its minimum, and raising the gate voltage above 10 volts has no further effect on reducing the Rds (on). The effective gate capacitance, which is high, can be obtained by dividing the charge input by the change in gate voltage during this region.
Ceff = [Qg - (Qgd+Qgd)] I (10v - VGS (th))= 40nC/4v = 10nF for the IRFP460
FET DRIVER ICS
In searching for IC's capable of providing the fast transitions and high peak currents required by power MOSFETs, one of the first devices which became popular was the DS0026. While this IC was origionally designed to be dual clock driver for MOS logic, it was capable of supplying up to 1.5 amps as either a source or sink. In addition, it was made with a gold doped, all NPN process which minimizes storage delays, and as a result, offers transition times of
approximately 20 nsec. Its disadvantages, however, are high cross conduction currents, as well as requiring excessive supply current when the output is in the low (OFF) state. This leads to higher power dissipation and junction temperature than optimum.
This brings us to newer ICs designed specifically as power MOSFET drivers for switchmode power supply applications. Several factors were taken into consideration while developing the new UC3705 /06 /07 /09 series of high current drivers; the most important of which, was to isolate the high power switching noise from the low level analog signals at the PWM. Seperate supply and return paths at the driver to its signal inputs and power outputs further enhances noise immunity. Additionally, several desireable features including an analog shutdown comparator have been incorporated inihe UC3706 and UC3707 devices, whereas the UC3705 and UC3709 drivers are optimized for low cost applications which incorporate this function elsewhere in the design. Each driver features TTL compatible input thresholds, undervoltage lockout, thermal shutdown and low cross-conduction, high speed output circuitry. The corresponding block diagrams and pin assignments are shown in figures 6 thru 9, and followed by the feature selection index.
UC3705 Block Diagram
N.l.INPUT N.l.INPUT
Vs
INTERNALLY CONNECTED
INT-PACKAGE
-,
Ve
SVLOGIC REGULATOR
OUT
LOGICGND
INTERNALLY CONNECTED
IN T-PACKAGE
PWR GND
Figure 6 9-223
FLIP FLOP ACTIVATE
A INHIBIT REF
B INHIBIT
INVERTING INPUT
NON-INVERT INPUT +VIN ANALOG STOP(+)
ANALOG STOP(-)
UC3706 Block Diagram Figure7
INPUT A N.I.
INPUT A INVERT
UC3707 Block Diagram
INPUT B N.1.
INPUT B INVERT
+VIN
ANALOG STOP(+)
ANALOG STOP(-)
SHUTDOWN 7 >--------~
LATCH DISAABLE
H=NO LATCH OR RESET L=LATCH ENABLED
Figure 8
9-224
U-118
GROUND 4,5,12,13
GROUND
Vee
UC3709 Block Diagram
U-118
OUTPUT AorB
5.6V
NOTE: One Output Shown
Figure 9
DRIVER FEATURES
1.5 Amp Peak Output Current (Per Output)
40 Nanosecond Rise & Fall Times into 1NF
Low Cross Conduction Current Spike
5 to 40 Volt Operation
High Speed Power MOSFET Compatable
Thermal Shutdown Protection
"':I::->
11. :I:>0 ..J <I: ::> 0
~
:::> 11. ~
;0z:: >aw:
~
"':I::->
11. ~
0z;:: >zaw: ~ 0 z
0 z
0
:..:.
.".'.
0 z
> 0 11.
w w
!;( !;(
aw: aw:
1w1. 1w1.
"' "'
UC3705
;z=
0
0
:I::c>-
"0 '
0
..J
<zI:
<I:
!::
:Ilcl
~ ..J
~
0
0
...
ii: w
..J
0 0
~
Iw-
"aw : '
:c
0
5
UC3706
UC3707
UC3709
1.5 AMP PEAK TOTEM-POLE OUTPUTS
The schematic of the UC3706 output drive circuit is shown in figure 10, which is similar to the other devices in this family. While first appearing as a fairly conventional totem-pole design, the subtleties
of this circuit are the slowing of the turn-off of 03 and the addition of 04 for rapid turn-off of 08. The result is shown in figure 11 where it can be seen that while maintaining fast transition times, the cross conduction current spike has been reduced to zero when going low and only 20 nsec with a high transition. This offers negligible increase in internal circuit power dissipation atfrequencies in excess of500KHz.
Typical Output Schematic
INPUT FROM LOGIC GATES
GROUND
Figure 10
9-225
U-118
Figure 11
The overall transition time through the UC3706 is shown in figure 12 with the upper photograph recording the results with a drive to the inverting input while the lower picture is with the non-inverting input driven. Note thatthe only difference in speed between the two inputs is an additional 20 nSec delay in turning off when the non-inverting input is used. Here, and in further discussions note that ON and OFF relate to the driven output switch, i.e., On is with the output HIGH, and vice versa. The shutdown, inhibit and protective functions all force the output LOW when active.
Note that the typical rise and tall times of the output waveform average 20 nsec with no load, 25 nsec with 1 nF, and 35 nsec when the capacitive load is 2.2 nF at room temperature. Multilayer ceramic
Figure12
capacitors are used in this test and located as physically close to the IC output as possible to minimize lead and connection inductance.
RISE TIMES INTO 0, 2.2 & 1()..iF.
{10T090% Vee)
V·2v/DlV H= 10NF/DIV
BOTH. fN·
FALL TIMES (90 TO 10% Vee)
1fN-
10 70
OV·
Figure 13 9-226
RISE TIMES
INTO 0, 2.2 & 10 lOvNF.
(1 Oto 90% Vee)
V: 2vlo1v H: 10Nslo1v
BOTH Ov-
FALL TIMES (90% to 10% Vee)
Figure 14
U-118
RISE TIME 1 NO LOAD 2 1ONF: 2 DRIVERS IN PARALLEL. 3. 10NF, 1 DRIVER! V 2v!DIV H: 1ONS/DIV.
(BOTH)
(10T090%Vcc}
FALL TIMES (90% TO 10% Vee)
50
Figure 15
The peak current of each totem-pole output, whether source or sink, is 1.5 amps. However, on dual output versions like the UC3706, UC3707 and UC3709, both of the outputs can be paralled for 3 amp peak currents. In close proximity on the same die, each output virtually shares identical electrical and thermal characteristics. Saturation voltage is high at this current level but falls to under 2V at 500ma per output. Examples of typical switching characteristics are displayed.
It should be noted that while optimized for driving power MOSFET device, the UC3705 /06 /07 /09 ICs perform equally well into bipolar NPN transistors. In a steady-state off condition, the output saturation voltage is less than 0.4 volts as currents to 50 milliamps.
DIRECT COUPLED MOSFET DRIVE The circuit of figure 17 shows the simplest interface to a power mosfet, direct coupling. In this example, an IRFP460 will be used to demonstrate the typical rise and fall times obtainable with a single 1.5 amp peak totem-pole driver. Further testing will include paralleling both outpus of a dual driver for a 3 amp peak capability. The IRFP460 device was selected, being the largest commercially
9-227
POWER MOSFET DRIVE CIRCUIT Ve
10uF
01~
02
1K
GND
D1 .D2:UC3611 SCHOTTKY DIODES Figure 16
U-118
available FET die (a size "6") at the time of this writing whose specifications were listed previously.
The typical values of each charge will later be used in conjunction with the measured driver performance to estimate the actual peak current delivered during each interval of turn-on. The tests shown
were conducted at room temperature with the FET located directly at the IC output pins to nullify any effects of series inductance. Additional tests and measurements will demonstrate the effects of circuit inductance on gate driver performance.
RISE TIME (Vgs) (Io to 90% Vee) I. OVAL DRIVERS 2. SINGLE DRIVER I Ov-
Vee"l 2v
V"2v/DIV H"IONS/CM
Ov·
FALL TIME (Vgs) (90% to 10% Vee) I. DUAL DRIVERS 2 SINGLE DRIVERS
Vee"l2v
v"2v/DIV H"20NS/DIV.
75
Figure 17
AVERAGE DRIVER CURRENTS DURING TURN-ON & TURN-OFF INTERVAL
EQUA T/ONS: Q = CV; Q = IT; ;AVG= CTV
During the transitions between 0 & 1OV over Tr & Tf intervals
SINGLE OUTPUT LOAD
RISE
-------- ···-
FALL
C =2.2NF C =10NF
0.49A --1
1.43A
0.67A 1.43A
IRFP460
1.26A
1.10A
DUAL OUTPUTS LOAD
C =2.2NF
---------- ------- --------
RISE
FALL
0.63A
0.88A
C = 10NF
f-----------·
---+---
2.0A
2.22A
·--------------+---------------!
IRFP460
1.6A
1.85A
9--228
U-118
While directly connecting the FET gate to the output of the driver is straightforward for testing purposes, it does not represent the "real" application which may include several inches or wire or printed circuit board traces. Here, wiring inductance will sharply degrade the transitions and cause substantial overshoot by ringing with the gate capacitance. Extreme examples ofthis can cause the gate-to-source voltage to overshoot beyond the specified maximum ratings.
Additionally, negative transitions (below ground) atthederiveroutput can raise havoc with the internal circuitry, leading to undesireable performance. While this is more of a concern with PWMs, (which use low level analog input signals) it will also detract from the drivers peak performance. Both of these conditions can easily be avoided by Schottky clamping the circuit to the auxiliary supply rails.
20-
15-
i= O"
10-
5Ov-
i= 5"
' '
i= O"
HORIZ: 10 NS/DIV VERT: 5V/DIV
Figure 18
DRIVER
Ve
OUTA OUTS
PGND.
+15V D2
.__ ~ ...
LENGTH >1" 01
10uF
rr1uF
TO POWER RETURN
01 ,D2 : UC3611 OR IN5820
Figure 19
9-229
ISOLATED GATE DRIVE In certain applications, the PWM is referenced to the load or secondary side of the power supply and the gate drive is transformer coupled across the isolation boundary to the power FETs. While this technique may work adequately at low switching frequencies, any series circuit inductance, as shown, will significantly degrade switching speeds and performance as the frequency is increased. An improved version of this circuit locates the drivers on the primary side, as close as possible to the FETs, and transformer couples only the low power input signals. Although somewhat more elaborate, significant improvements in turn-on and turn-off switching times are obtained and the FET switching losses are minimized.
TRANSFORMER COUPLED MOSFET DRIVE CIRCUIT Ve
TO LOAD
1K
D1 .D2:UC3611 SCHOTTKY DIODE ARRAY Figure 20
Figure 21
+15V
IMPROVED XFMR COUPLED DRIVE CIRCUIT
D2A
1uF
Ve
D1
Ve
· OUTPUTr---+-~--+----+--~ PWM
· IN ,.------9-----L~V\f\~--j
D2B
OUT DRIVER
PGND
PGND
D2C
Figure 22 9-230
PUSH-PULL TRANSFORMER COUPLING
The totem-pole outputs of the UC3706 can easily be configured for implementing the balanced transformer drive as shown in figure24. Outputs A and Bare alternating now as the internal flip-flop is active and the output frequency is halved. Note that when one UC3706 output goes high, the other is held low during the dead time between output pulses. With balanced operation, no coupling capacitor on the primary is necessary since there is no net DC in the primary. Schottky clamp diodes on the primary side and back-to-back zeners on the secondaries are necessary to minimize the overshoot causes by the ringing of the gate capacitance with circuit inductances. Waveforms of all significant points within this circuit are shown.
U-118
14
DRIVER BIAS
Figure 23
UC 3706 CONVERTS SINGLE OUTPUT PWMS TO HIGH CURRENT PUSH-PULL CONFIGURATION
1n~10uF
OUT 12
UC3840 PWMor UC3841
GND
13
Figure24
9-231
UC 3611 QUAD SCHOTTKY DIODE ARRAY
U-118
SUPPLYING POWER TO THE DRIVERS
From the block diagrams of figures 6 thru 8, note that the UC3705, UC3706 and UC3707 have two supply terminals, Vin and Ve. These pins can be driven from the same or different voltages and either can range from 5 to 40 volts. Viri drives both the input logic and the current sources providing the pull-up for the outputs. Therefore, Vin can also be used to activate the outputs and no current is drawn from Ve when Vin is low. This is useful in off-line applications where its desireable for the control circuit to have a low start-up current. Several PWM controllers, like the UC1840, UC1 841 and the UC1851 feature a Driver Bias output which goes high once the undervoltage lockout threshold is crossed, thus supplying bias to the driver. Adaptations of this technique can be made to work with a variety of other PWMs and control circuits.
USING "SPLIT" SUPPLIES
Many applications utilize a negative voltage rail in the drive circuit to guarantee complete turn-off of power MOSFETs, especially those with low gate threshold voltages, typical of"logic level" input devices. This is easy to implement with any of the UC3705 thru UC3709 drivers by offsetting the input signals with a zener diode equal in voltage to the negative supply, Vee. Although referenced at the driver IC to the Vee rail, these inputs are offset by an equal amount to the PWM controller, simulating a ground referenced input. This technique also offers moderate improvements in FET switching speeds at the penalty of slightly increased effective delay times from the driver inputs. The end results are listed below, which may be beneficial in applications where a tailored gate drive is required to alter the MOSFET switching charcteristics.
POWER MOSFET DRIVE CIRCUIT USING NEGATIVE BIAS VOLTOGE AND LEVEL SHIFTING
TO GROUND REFERENCED PWMS
Vee (+ 12to+ 15v)
1uF 10uF
DRIVE INPUT
D11if
(VEE) NEGATIVE
BIAS (-5to-15V)
D2
1K
GND D1 .D2:UC3611 SCHOTTKY DIODES Figure 25
RISE TIME (10to90%)
(10NF) (0,2.2,10NF)
10V·
V=2v/DIV H=SNS/DIV
0v-
FALL TIME (SOTO 10%) (0,2.2,10NF)
10v-
c, tFAll
(NF)
NS
0
15
2.2
20
10
35
Figure 26
9-232
U-118
RISE TIME
(10to 90%) Vee
10v-
1. Vce=12v
VEE=-12v
2. Vee=12v
VEE=-5v
3. Vee=12v
VEE=Ov
V=2v/DIV H=10NS BOTH
0v-
FALL TIME (90TO 10% Va)
10v-
VEE !FALL (v) NS 0 55
-5 40
-12 35
VEE IRISE (v) NS
0 70
-5 55
-15 45
VEE= (v)
0v-
Figure 27
VEE (V) 0 -5 -10 -12 -15
VEE (V) 0 -15V
VEE (V) 0 -5 -10 -15
td Rise to 'O"V
(NS)
56
70
86
93
100
TRise 0-10V (NS)
50
42
34
32
30
TdFall to begin
(NS)
50
50
50
50
50
TFall 10-0V (NS)I
45
33
29
28
27
T Delay total (NS)
106
120
136
143
150
Tr&Tf total (NS)
95
75
63
60
57
TTotal tr+tf+trd
(NS)
201
195
199
203
207
Delay trd+tfd (NS)
Minimum (106NS)
Maximum (143NS)
Transition Times tr+tf (NS)
Maximum (95NS)
Minimum (60NS)
Rise 2.4A 2.B6A 3.53A 4.0A
Fall 2.67A 3.64A 4.14A 4.4A
SUMMARY
This paper has presented an understanding of the dynamics of high speed power MOSFET switching in an attempt to define the optimum gate drive requirements to meet specific applications. The need for high peak gate currents with controlled rise times has led to the development of several integrated circuits aimed towards achieving these goals. The UC3705, UC3706, UC3707 and UC3709 drivers provide high speed response, 1.5 amps of peak current per output and ease the implementing of either direct or transformer coupled drive to a broad range of power MOSFETs. With these new devices, one more specialized function has been developed to further aid the power supply designer simplify his tasks and enhance power MOSFET switching characteristics.
Unitrode Integrated Circuits Corporation 7 Continental Boulevard. · P.O. Box 399 · Merrimack, New Hampshire · 03054-0399 Telephone 603-424-2410 ·FAX 603-424-3460
9-233
n n L.::::::J
INTEGRATED CIRCUITS
-UNITRDDE
9-234
n n INTEGRATED
~CIRCUITS
-UNITRODE
APPLICATION NOTES
U-119
DRIVING THREE-PHASE BRUSHLESS DC MOTORS - A NEW LOW LOSS LINEAR SOLUTION.
Robert A. Mammano, V.P. Adv Tech, Unitrode IC Corp and John J. Galvin, Control Systems Eng, Quantum Corp.
ABSTRACT
A new linear driver for small Brushless DC motors has been developed which has the capability of maximizing the voltage delivered to the motor while additionally providing commutation logic and full control. By using discrete PNP high-side transistor switches in conjunction with integrated saturable NPN low-side drivers, less than one volt total loss can be achieved at currents up to two amps, and complete motor control can be derived from only a five volt power source.
BRUSHLESS DC MOTORS
Although the world has long known of the myriad problems with brush-type DC motors, the development of electronically commutated, or "Brushless" (BOC), motors has not been a simple transition. While Hall Effect sensors have developed to the point where accurate and reliable armature position information can now be readily derived, the problems of amplifying these lowlevel signals, applying them to the appropriate winding, and then driving that winding with an efficient power transfer still represent a significant challenge. Particularly when this intervening circuitry - none of which was required with brush-type motors also has to be reliable, very low cost, noise free, and take up minimal space. The problem is further compounded by the need to provide three-phase drive for all but the simplest, specialized motors in order to accommodate bidirectional rotation and wide variations in speed and load.
For complete control of a brushless DC motor, the circuitry must provide at least three functions:
I. Commutation logic to generate the correct phase timing from the Hall sensors. In most cases, this is implemented as a digital decoding function.
2. Power drivers for each ofthe three output phases. The challenge here is finding a solid state switch as efficient as the old commutator brush.
3. Control circuitry to give the motor some intelligence. This usually means controlling motor current in response to commands based on speed, position, torque, or some other measurable output.
THE SPINDLE DRIVE PROBLEM Providing the above functions as a spindle driver for rotating memories represents an additional challenge as disk drive users have come to expect the package density and low costs of an integrated driver while at the same time demanding ever higher operating efficiencies to minimize the requirements on power supplies and heat sinks.
While discussing drive efficiency, it is worth noting that disk drives add a further restriction due to the magnetic media and low signal levels involved. This is that the use of switch-mode technology to increase power control efficiency is usually forbidden out of concerns for possible high-frequency EMI noise. Ruling out switch-mode techniques leaves the designer faced with the problem of providing maximum efficiency with linear current control, and thus his quest for power savings can only be directed toward minimizing the drop across the output switches in order to use the highest efficiency motor.
THREE PHASE MOTOR DRIVE The drive stage for a typical brushless DC motor is shown in Figure I where the motor is shown wound in the "Y" configuration. A "delta" form is equally applicable and would make no difference to the switches. The driving problem is immeadiatly apparent in that there are six separate switches required and two are in series with any current path through the motor. With a 12 volt supply and typical bipolar darlington switches - each with a probable 1.5 volt drop - the maximum voltage to the motor is nine volts and one fourth of the input power is lost in the switches.
HIGH-SIDE SWITCHES SOURCE CURRENT
LOW-SIDE SWITCHES SINK CURRENT
Figure I: Three phase, bipolar drive for a BDC motor showing one phase of current flow.
9-235
APPLICATION NOTES
U-119
These switch voltage drops have added sig-
nificance in terms of optimizing the motor design
since the maximum current through a given motor
is defined by the difference between the voltage ap-
plied to the motor and the back EMF generated
while it is running. Reducing the voltage drop
across the switches allows the use of a motor with
a higher torque constant and correspondingly higher
back EMF which results in a lower motor current
for the same load. Since the power loss in the motor
is equal to 12 times the wire resistance, the gain in
overall efficiency is more than proportional. For
example, with a three volt switch drop from a 12 V
supply, an optimum motor choice might have a back
EMF of 8 V and require 4 W of power from the
supply to do 2.7 W of work. Reducing the switch
drop to one volt would now allow a motor with a
back EMF of I0.2 V to be used which, with all other
factors remaining unchanged, would require only
3.16 W to do the same work. In other words, a 22%
increase in the voltage applied to the motor can result in a 27% increase in motor efficiency. This is in addition to saving 2/3 of the power loslin the
Figure 2: The UC3655 IC provides decode logic, high-current low-side linear drivers under the control of an internal amplifier, and switches to activate high-side, external PNP transistors.
switches.
devices is their saturation voltage for a given base drive. While
bipolar PNP transistors are used throughout in this paper, it
While power MOSFET technology has the potential of offer-
should be clear that this is a cost consideration and P-channel FET
ing lower switch losses in discrete form, an integrated monolithic
devices could be used as well with the benefit of reduced drive
FET structure, while technically feasable, may well be economi-
power losses.
cally impractical. An integrated bipolar transistor scaled for a
Vsat of 0.4 Vat one amp requires approximately 2000 square mils of silicon, while an integrated DMOS transistor with an Rds(on) value of0.4 ohms would be closer to 5000 square mils. And it takes six transistors to build a three phase driver. Therefore, a more cost-effective solution would indicate the use of bipolar transistors, but as single saturating switches - not darlingtons.
The current-limited darlington circuit used for each of the threePNPdrivers is shown in the upper portion of Figure 3. This driver is activated by the digital signal from the Channel Select Logic which is defined to allow only one PNP to be on at a time. Note that the total supply current for this stage is a constant 100 uA from the five volt supply for each output.
The low-side switches of Figure I are easily integrated in this
Each of the low-side motor drivers shown in Figure 3 are, of course, integrated power NPN transistors scaled for a maximum
form as power NPN transistors with their base currents derived
output current of three amps with a very low saturation voltage
efficiently from a five volt power supply. The high-side ~-------------------------~
devices are more of a problem, however, as these need to be PNP transistors to achieve the same low-sat performance, and
UC3655
t-------vs"+5V
isolated power PNP transistors are still not compatible with an integrated bipolar process. Thus the decision made for the
r - - -.......-vm ~ 5 TO 40V
motor driver described herein was to supply the PNP's as external, discrete saturating switches while the rest of the con-
D73F5T OR TIP32
trol circuitry was integrated into a single power IC. The result
is the UC3655 illustrated in the block diagram of Figure 2.
FROM
CHANNEL
SELECT
THE UC3655 LINEAR BDC MOTOR DRIVER
LOGIC
3
OHMS
This device achieves efficient operation by allowing the
CH B
external PNP's to be selected for the specific application, while internally generating a switched base drive of up to I00 mA - adequate for motor load currents of at least 3 Amps. Because the PNP's are always driven into saturation, their power
CH A SINK DRIVE
3PHASE B.D.C. MOTOR
CH C
dissipation will usually be low enough to require no special heat sinking and, in many cases, theymaynotevenneedpower ~-------------------------~
packages. The only specification of significance for these Figure 3: Interlacing the UC3655 to a BOC motor.
9-236
APPLICATION NOTES
U-119
drop. At full load, these transistors may need a base drive of up to 50 mA which must come from the five volt supply; however, since they are also used as the means to control the motor current, the action of the control amplifier reduces the base drive as it commands less motor current. The overall schematic of both the amplifier and one of the three low-side drivers is shown in Figure4.
3. A unity-gain output stage (to the sense r,esistor) provides the high current output drive with a high input impedance so that the transconductance amplifier is not unduly loaded. Note that the analog command input is gated by the Channel Select Logic so that only one output is on at a time with the other two drivers draining only 100 uA apiece from the supply.
11>--------'¥-_10__,__
TRANSCONDUCTANCE AMP
lCLAMP IUNITV-GAIN CURRENT AMPLIFIER!
Vs"5V
24 OHMS
4. A clamp on the output ofthe transconductance amplifier limits the voltage drop across the sense resistor to approximately 500 m V and thereby provides some measure of over-current protection.
··
INPUT
SINK OUTPUT
The remaining portion of the UC3655 consists of the decode logic to
lK 2K
generate the proper output switch timing from the Hall sensor position in-
dicators. This logic is easily mask
programable for other than the standard
60 degree output phasing. The input
circuitry to these Channel Select stages
900
SENSE
has a high impedance, stabilized
threshold of 1.5 V and is designed for
single-ended, digital-output Hall sen-
sors. For maximum flexibility, pull-up ~---------------------------------~ resistors are not included but in niosy
Figure 4: Control of the motor's current requires the four functions shown above, plus the decode logic to define environments, should probably be
which of the three outputs is active.
added externally. Where analog, two-
This circuitry includes an internal feedback loop to configure the transfer function as a transconductance amplifier controlling motor current from a voltage command. For full control, four functions are included:
terminal Hall sensors are used, the comparator circuit of Figure 5 can be used at each input to give fast, clean transitions.
I. An input divide-by-ten attenuator to scale a four volt input command range on Pin 7 to a 400 millivolt range across the current sense resistor connected to Pin I .
A fourth input to the decode logic is the direction function addressed through Pin I0. This input circuitry, shown schematicly in Figure 6, has three states:
2. An amplifier to provide voltage gain. This is also a transconductance type so that the feedback loop may be easily stabilized by a single capacitor from its output on Pin 9 to ground. There is a 100 mV offset built in so that, in conjunction with the input divider, zero output current is commanded with a one volt input.
I. A low input pulls REV low and FWD high, setting up the decoding for a forward rotation.
2. A high input reverses the states of REV and FWD, which the logic decodes as a command for the opposite direction of rotation.
+sv
BIAS
Figure 5: An external comparator added to each sense input will allow the use of low-level, analog Hall sensors.
FWD/REV
FWD/REV
LOW OPEN HIGH
DIR
FWD INH REV
20K
FWD
20K
REV
lOK
lOK
Figure 6: Internal circuitry allows the choice of direction of rotation - plus inhibiting - with a single device pin.
9-237
APPLICATION NOTES
U-119
3. If the input is open - or connected to a voltage between 1.8 and 3.2 volts - both FWD and REV are high which the logic defines as a coast condition with all six outputs off.
All outputs are also inhibited if the three Hall inputs are all in the same state, either high or low.
While no braking function is built into the UC3655, it is entirely feasible to provide a rapid deceleration by switching the direction command from FWD to REV with the only precaution being to allow the output transistors to tum off while the command is passing through the !NH region. Typically, this might require a l0 usec delay which is easily accommodated with either digital or analog techniques.
supply. Most PNP transistors will readily accept this as Jong as the voltages are low, but it should be evaluated for each application. Of course, the body diode of a P-channel PET provides this current path inherently.
Typical waveforms for voltage and current at one output are shown in Figure 7. While the voltage always switches to Vm on the high side due to the saturated PNP' s, the value on the low side will be determined by the motor resistance and the commanded current. The large negative glitch occurs when the active PNP turns off; the tall spike above Vm occurs with turnoff of the NPN. The two short negative transients which occur while the current sinking NPN is on are caused by state-changes on the other two outputs momentarily interrupting current flow.
It can be seen from the block diagram of Figure 2 that the only supply voltage connection to the UC3655 is a single 5 volt source. From this supply, the quiescent current is less than I0 mA with the outputs inhibited and increases with motor current to approximately 25 mA with a two amp load. The motor voltage is defined by the supply used for the emitters of the PNP transistors and can range from 5 V to 40 V. Note that with this design, a 5 V supply could deliver more than 4 V to the motor - a difficult task for any other integrated circuit topology.
MOTOR DRIVE VOLTAGE (WITH RESPECT TO GROUND)
Finally, this device includes the protection of under-
voltage lockout, with a threshold of 4.2 V, and thermal
shutdown when the junction temperature rises above
MOTOR CURRENT ON ONE LEG OF THE MOTOR)
150°C. Since the UC3655 is a linear driver, the poten- Figure 7: Voltage and current waveforms experienced at each output of the UC3655. tial for high dissipation is possible but a Multiwatt
power package with adequate heat sinking will accommodate up
For disk drive or other applications where EMI noise genera-
to 25 watts. For smaller motors, a power 28-pin surface-mount,
tion at phase changes could be a problem, some slope control
PLCC configuration with 4 watt capability will be offered.
should be used on the outputs. While there are several ways to
accomplish this, one effective technique is with R-C snubbers as
INTERFACING TO THE MOTOR
shown in Figure 8. The circulating currents which will flow in
The schematic of Figure 3 illustrates the added components necessary to interface the UC3655 to a typical BOC motor with the other two outputs identical to that shown. While resistor RI
these snubbers control the output rise and fall times and significantly reduce the higher frequency harmonics without contributing additional stress to the drive transistors.
serves merely to speed the tum off of the PNP transistors, R2,
while optional, serves two functions: It can reduce the PNP base
current to less than the internally limited I00 mA, and it absorbs
the PNP base drive power losses which would otherwise add to
the IC package dissipation.
In driving a BOC motor, there is no concern for cross-conduction current flow where both an NPN and a PNP experience overlapping conduction during switching transitions. This is because the commutation logic never switches any output from low to high or vice versa - there is always an off state in between. The inductance of the motor does force current transients when any transistor turns off, however. When a PNP turns off, residual current transfers to the internal diode at that output, pulling the output slightly below ground potential. When an NPN turns off, the transient current then flows through the PNP in the reverse direction, pulling the output voltage momentarily aJiove the motor
,,,,.....----
/
I
I
I
CH A --11--1---'~~
' \ \ I I I
I I
/
2.2 OHMS
1uf
2.2
OHMS
Figure 8: These three sets of R-C snubbers will help to reduce EM! noise.
9-238
APPLICATION NOTES
U-119
ALTERNATE CONFIGURATIONS
Although the primary goal in developing the UC3655 was the implementation of a linear, current controlled BOC drive, that is not the only way this device may be used. The benefit of very low saturation voltage drop across the conducting switches has obvious advantages for efficient motor drive without linear control. The internal transconductance amplifier can be disabled by merely connecting the input terminal to the 5 V supply which will pull the compensation terminal up to the internal clamp level and allow the NPN low-side transistors to be switched fully on through the action of the decode logic. Current limiting may still be included by appropriate selection of the sense resistor, or for maximum voltage to the motor, the sense terminal may be connected directly to ground.
PULSE WIDTH MODULATION OF MOTOR CURRENT
If the application will accept direct switch-mode control of motor current, this approach is also possible with the UC3655. Figure IO shows the use of a UC3843 Power Supply PWM IC as the control element. Since this device has a very low impedance output drive, it will override the output of the UC3655's control amplifier and apply the PWM signal to whichever output has been activated by the decode logic. To keep switching and motor losses low, the frequency should be limited to the 20-40 kHz range.
-----------------------------~
L296
Vm SUPPLY TO MOTOR
In this configuration, the circuit is only utilizing the
position decode and output drive circuitry, and the motor
will run open loop with its speed (or torque) determined
solely by the motor voltage. This suggests another
method of control. Since the UC3655 operates with
R2
only a 5 volt supply and is unaffected by the motor volt-
age, Vm, on the PNP emitters, controlling Vm will con-
trol motor speed. This can be done with either a linear
or switch-mode regulator with the regulator control loop
used to control the motor rather than hold the output
voltage constant. An example of switching regulator
control is shown inFigure9 where anL296PWM power ~---------------------------~
supply IC is used as a IOOkHz buck regulator. This cir- Figure 9: The L296 Buck Switching Regulator will efficiently control motor speed with the cuit offers several advantages over other control techni- internal control loop disabled, by controlling the motor voltage instead.
ques:
1. Since all power devices are used as switches, overall efficiency can be higher than with a linear approach.
2. The PWM frequency is converted back to DC before it gets to the motor minimizing the potential for harmful EM!.
+12v +sv . - - + - - - - V M TO MOTOR UC3655
3. High switching frequencies can be used in the regulator to keep the filter components small but with only ripple current through the motor, internal AC losses there are minimized.
VREF lOK
4. A boost configuration could also be used to raise
20K
the motor voltage above the supply for faster
response, lower currents, and a potentially sig- ~---------------------------~
nificant increase in efficiency.
Figure 10: The UC3843 PWM Power Supply Chip can be used as a switch-mode controller for motor current by overriding the UC3655's internal amplifier with a PWM command.
There are also some disadvantages:
1. The added complexity and components of the PWM regulator,
2. The additional switch in series with the motor.
9-239
APPLICATION NOTES
U-119
PHASE LOCK LOOP SPEED
CONTROL
Vs"'+5V
Vm=+12V
V REF
In many applications where very
accurate speed control is required -
disk drives, for example - a phase lock
loop, locked to a crystal frequency
reference, is often utilized. The
UC3633 PLL chip has been designed
to supply this capability and its use
with the UC3655 is shown in Figure
11. In this circuit, a4.9125 MHz crys-
tal is divided down and compared with
a signal from one of the motor's Hall
sensors to force rotation at exactly
3600 rpm, +/- 60 ppm. This figure
shows the UC3655 used in its conven-
tional linear control mode, but the
0.2
UC3633 is equally applicable to the
other modes of operation discussed above. For further information on the ~----------------------------------~
UC3633, refer to Unitrode's Applica- Figure 11: A UC3633 Phase Lock Loop IC can be used with the UC3655 to provide crystal-controlled speed ac-
tion Note U-113.
curacy.
SENSORLESS DRIVE
Finally, with the utilization of a microcontroller it should be
possible to implement a drive system without the need for Hall
position sensors and thus gain significant cost savings in the
motor. Utilizing techniques developed for
synchronous and stepper motors, commutation
+5V
could be done "open loop" without angular position
feedback but since the actual commutation point is
not likely to occur at the optimum point, motor ef-
MICRO CONTROLLER
ficiency will be poor and will vary with load. One approach to solving this problem is the use of a single sensor to generate a reference point, and a digital PLL locked to this reference to generate the correct commutation timing. While this can yield
Ph 1 t - - - - - -.. 11
Ph 2 1 - - - - - - - M 1 2
Ph 3 t - - - - - - M 1 3 CONTROL-
PWMI---..,.-~-~
14~---+---+~
commutation accuracy even higher than that ob-
AID
tainable with a typical sensor-type motor, the ob-
vious disadvantage is increased cost over a completely sensorless design.
I
I
__/'l___T
SAMPLE AJ
JI
15
SAMPLE B
By using the back EMF generated by the motor,
R·
a signal proportional to the torque angle (commutation error angle) may be derived which can be used
COMMUTATION ANGLE ERROR
=K [ ~ Va - Vb ]
-
BACK EMF
to correct the timing. However, simply forcing the commutation generator to deliver the correct timing will not control the speed of the motor. If instead,
Figure 12: This approach to sensor-less control digitizes the back EMF on one motor phase and computes the commutation angle error from measurements made during the middle of the "off-time".
this signal is used to control the motor current by
the approach shown in Figure 12, the commutation points are still
generated open loop but, instead of forcing the commutation gen-
erator to follow the motor, the motor now follows the commuta-
tion generator. If the motor leads or lags, drive current is
modified to force the torque angle to be optimum, yielding a PLL
motor control system requiring no position sensors.
9-240
n n L::::::'.J
INTEGRATED CIRCUITS
-UNITRODE
APPLICATION NOTE
U-120
A SIMPLIFIED APPROACH TO DC MOTOR MODELING FOR DYNAMIC STABILITY ANALYSIS.
By
Claudio de Sa e Silva
Applications Engineer
Unitrode Corporation
When we say that an electric motor is a device that transforms electric power into mechanical power, we say two things. First, that the motor 1s - and behaves as a transformer. Second, that 1t stands at the dividing line between electrical and mechanical phenomena. In the case of permanent magnet (PM) motors we know that this power transformation works 1n both directions so that the electrical impedance depends on the mechanical load, while the mechanical behavior of the motor depends on the conditions at the electrical end.
This being the case, it should be possible to represent a motor's mechanical load, on the electrical side, by a set of familiar electrical components such as capacitors or resistors.
THESE UNITS
TABLE 1. UNITS CONVERSION
{~ } .... = +- -
SI UNITS
oz
2.78 x 10- 1
N
lb
1n ft gt g cm2 ft lb sec2 oz 1n sec2
4.448 2.54 x 10-2 3048 x 10-1 9.807 x 10-3
10-7
1 356 7 063 x 10-3
N m m N Nm sec2 Nm sec2 Nm sec2
DIM.
MLr- 2 MLT- 2
L L MLT- 2 ML2 ML2 ML2
CHOOSING A UNIT SYSTEM
Before we get started, let us consider for a moment the system of measurement units that we have chosen.
The metric system of units has undergone a number of changes 1n its history, of which the latest 1s the SI (Systeme International d'Unites). This system has become popular in most of the industrialized world, largely because it is a coherent system. 1n which the product or quotient of two or more units 1s the unit of the resulting quantity. It will be seen here that certain simplifications result from using this form of the metric system.
ft lb oz 1n
1356
Nm
7 063 x 10- 3
Nm
ML2r 2 ML.2r 2
NOTE. The dimensions are M (mass). L (length). and T (time). The gram lg) 1s a unit of mass. and the gram-force (gf) 1s a unit of force. The pound (lb) and the ounce (oz) are included as units of force only
L,
In the SI system. force is measured 1n Newtons (N) and distance 1n meters (m). Consequently, the units of torque are Nm (see Conversion Table). If a motor shaft rotates at an angular velocity of wM radians per second, with torque TM· the mechanical power output will be equal to the product TM and wM and the units will be watts 1f TM is in Nm.
Motor manufacturers usually specify a torque constant (KT) and a voltage constant (Kv) for their motors. These constants have different values when the torque and speed are measured in English units, but they have the same numerical value when SI units are used. This becomes obvious when you consider that the electrical input power must be equal to the mechanical output power:
(1) VA IA = TM WM (watts)
wM "' motor speed 1n rad/sec
KTV m Nm/A or Vs8Clrad
Ci,1"'
~ K)v
(farads)
FIGURE 1. THIS SERIES RLC CIRCUIT IS AN EXCELLENT MODEL OF A DC MOTOR LOADED WITH AN ESSENTIALLY
INERTIAL LOAD. HERE, J IS THE TOTAL MOMENT OF INERTIA, INCLUDING THE ROTOR'S J,...
If we do the same thing with the familiar electrical transformer, we get the turns ratio:
v, (3)
11 = V2 12 (watts)
(4) ~ = l = ~
V2
11
N2
Thus, the non-dimensional turns ratio N1/N2 is analogous to the dimensional torque (or voltag~) constant KTV. Fur-
thermore. equations (2) and (4) give us a clear hint that
·where VA is the internally generated armature voltage, or
the angular velocity (wM) is analogous to voltage, while
back emf. and IA is the armature current. (See Fig. 1 for
the torque (TMl is analogous to current.
definition of motor terms.)
9-241
APPLICATION NOTE
U-120
The units of Krv may be either Nm/A, or V sec/rad. Thus,
specifying both Kr and Kv for a motor is like measuring
and specifying both the voltage ratio and the current ratio
of a transformer. and can only make sense where redun-
dancy is required.
· '
THE MOTOR AS A TRANSFORMER
We have established an analogy bet.ween Krv and a transformer's turns ratio; bet.ween angular velocity and voltage; and bet.ween torque and current If the motor
behaves as a transformer. then we would expect to find
the square of Krv involved in something analogous to impedance transformation.
Suppose we apply a constant current IA to the armature
of a motor whose load is its own moment of inertia JM (Nm sec2). We know that according to Newton's law for rotating objects,
(5) Tt.i = JM aM
where aM is the angular acceleration'dwM/dt.
A MOTOR MODEL
Once we can represent the mechanical load by means of electric elements, we can draw an equivalent circuit of
the motor and its mechanical load. The armature has a finite resistance RA and an inductance LA, through which the torque-generating current IA must flow. These components are not negligible, and must be included. An inertially loaded motor can be represented as in Fig. 1, where the moment of inertia J is the sum of the load's JL and the rotor's JM·
It turns out that in practice, the memento! inertia that the motor must work against - or with, depending on how you look at it - is by far the most important component of the mechanical load. A frictional component also exists, to be sure, but because it is largely independent of speed, it would be represented electrically as a constant current source, which could not affect the dynamic behavior of the motor. And since a torsional spring -
which would affect it - is rarely found in practice, we will
concentrate on the inertial problem only.
Since TM = IA Krv (Eq. 2)
(6) IA Krv = JM dwM
dt Furthermore, also from Eq. 2,
(7) WM= VA Krv
so that
(B) IA = ~. dVA
K~ dt
Equation 6 has a familiar form, and we recognize at once
the quantity JM/K~ as a capacitor. It follows that the motor "reflects" a moment of inertia JM back to the electrical primary as a capacitor of J~K~ farads.
A neat way to check this result is to equate the energy stored kinetically in JM with the electrical energy stored in a capacitor CM:
(9) V2 CMVi = 112 JM w~
w~ )2 (10) CM = JM (
Since ~=-1 -.
VA Krv
(11) CM = ~ (farads)
K~
Similarly, a torsional spring with spring constant Ks (Nm/rad) is reflected as an inductance of K~/Ks henries. And a viscous damping component B (Nm sec/rad) appears as a resistor of K~/B ohms.
MEASURING THE. COMPONENTS
The measurement of RA and LA is not difficult. A good ohmmeter will get you RA, and you can measure the
electrical time constant re to calculate LA:
= (12) LA re RA
Just make sure that the rotor remains stationary during these measurements.
In order to determine the value of the capacitor. CM, we
will need to measure the shaft speed. If the motor being
measured is a brushless DC motor, we can use the signal
from one of the Hall effect devices as a tachometer. If the
Hall frequency is fH, and the number of rotor poles is P.
the angular velocity wM is
(13) wM = 4n fH (rad/sec) p
With other motors you will need a strobe-light or some other means to measure speed.
A gocid way to measure CM is through a measurement
of the mechanical time constant TM. We do this by driv-
ing the motor with a constant voltage driver and measuring the time it takes to accelerate from zero speed to 630/o of the highest speed achievable at the voltage used. To
set a sate limit to the starting current we can reduce the
supply voltage or add a series resistor with the motor, or both. The set-up is shown in Fig. 2. Note that the armature
resistance RA is already known, and we add resistors Re.
if needed, to limit the armature current IA to a value that is safe for both driver and motor.
The first thing to do is let the motor run freely and measure WMAX and IMAX· and use these value,s to calculate the armature voltage VMAX:
(14) VMAX = Vee - VS>J - IMAX (RA + Re)
9-242
APPLICATION NOTE
U·120
Vee
10K
+5V 1. 713
-=-
UC3820
-=-
Re
A IM~
15
e 14
,, HA HB HC
10
12
-=-
TOTAL MOMENT OF INERTIA ISJ·JM-+-JL
10K
10K
L _ ~ 'H· FREQUENCY ""
WM "'
p
FIGURE 2. SET-UP FOR MEASUREMENT OF CM = J/Krv
OF A 3-PHASE BRUSHLESS DC MOTOR WITH
INERTIAL LOAD J1. THE MOTOR VOLTAGE VM = Vee - VSAr.
WHERE VSAT IS THE OUTPUT SATURATION VOLTAGE.
Here Vee is the supply voltage, VSAT is the saturation voltage of the driving circuit, and IMAX is the current drawn by the unloaded motor at maximum speed.
Thus we can calculate
(15) Krv = VMAX (Vsec/rad)
Next. set the oscilloscope time scale to that you can easily read a Hall frequency equal to 630/o of wMAX· so that:
(16) WM = 0.63 WMAX
By holding and releasing the motor shaft, take several readings of the time TM required to accelerate from zero to wM. Remember that these readings are taken "on the fly," since the motor continues to accelerate towards the maximum speed wMAX· Having obtained a good value of TM you can now calculate
(17) CM = __,-;_M__ (RA+ Ra)
(farads)
sinusoidaly at some frequency f, the speed wM will vary similarly, but the amplitude and phase will in general be different from those al the driving function. This fact is very important if we are to include the motor in a feedback loop, because the motor's contribution to the overall loop gain and phase shift is an important factor in determining stability. The motor's transfer function - i.e. Eq. 19 expressed as a function of frequency - gives us a precise description of how the amplitude and phase behave at different frequencies. To do this. we use the variable jw, where
j=~ and w = 2111.
(20) -VA-(jw-) -
V1 (jw)
(jwCm)- 1 )w2 LACM + )W RACM +1
(21) VA (jw)
V1(jw)
(jw)2 LACM + )W RACM+
1 (22) LACM =
w2n
where wn is the natural frequency of the circuit.
(23) RACM = RACMLA = ~ = _1_
LA
w~LA Own
since the circuit 0 is
Q = WnLA .
RA
Therefore, (24) VA (jw)
(-jW-)2 +-jw-+
Wn
Own
Furthermore, using Eq. 19,
(25)
This completes the RLC equivalent circuit, If the value of JM is also required, it too can be calculated:
(18) JM = CM K~
THE MOTOR'S TRANSFER-FUNCTION
In the circuit of Fig. 1, V1 is the voltage applied to the motor leads, and VA is the actual armature voltage, or back EMF This latter voltage is equal to wMKTV, as we have seen, so that if we want to derive an expression relating the speed to the applied voltage, we can write:
(19) -WM- = -1- ·VA- (radNsec)
V1
Krv V1
Since we know the values of Krv. wn and 0, we can
calculate the magnitude and phase angle of Eq. 25 for various values of jw. For a given w = w1, Eq. 25 can be evaluated into a complex number A1 + j81· whose angle is,
(26) e 1 = tan-1 ~ A,
and whose magnitude can be expressed in decibels as follows:
(27) M, = 20 IOQ10 VA~ + B~
If V1 is a constant voltage, the speed wM will also be constant. This is clear from the circuit of Fig. 1 as well as from our experience with motors. If, however, V1 varies
A plot of these quantities, using a logarithmic frequency scale, is called a Bode plot, and can be a handy tool 1n understanding how the device will affect the final loop
performance.
9-243
APPLICATION NOTE
U-120
A DISC - DRIVE EXAMPLE
A small three phase brushless DC motor, measured as above. has the following charactenstics:
Krv = 0.015 Nm/A, or Vsec/rad. RA = 2.5 ohm LA = 0.002 Hy J = 0.001 Nm sec2
The J value was measured with three magnetic discs mounted. and represents the actual value required for the application. Using Eq. 11.
J
.001
(28) CM = - - - = - - - = 4.44 Id
K~
(0015)2
This may seem like an unusually large value for a capacitor, but 1t simply reflects the large amounts of k1net1c energy that can be stored 1n the included inertia.
From Eq. 22
(29) wn= -v-==~ LA CM
v0.002 x 4.44
TABLE 2. CALCULATED VALUES OF EQUATION 31.
w (rad/sec)
WM (jw) V1 (jw)
GAIN PHASE (db) (deg)
0.01
65.9 - J 7.32
36.4 -6.3
0.03
60-120
36.0 -18.4
0.1
29.8 - J 33.2
33.0 -48.0
0.3
5.5 - J 18.4
25.7 - 73.3
1.0
0.53 - J 5.95
15.5 -84.9
3.0
0.06 - J 2.00
6.0 -88.4
10.0 30.0 100
0 - J 0.60 -4.2 x 10- 3 - J 0.20 -4.7 x 10- 3 - J 0.06
-4.4 -89.9 -14.0 -91 2 -24.5 -945
300 1000
-4.5 x 10- 3 - J 0.02
-34.2 -103.5
-2.9 x 10- 3 - J 3.7 x 10- 3 -46.6 -128.6
3000
-7.1 x 10- 3 - J 3 x 10-4 -62.3 -157.4
= 10.61 rad/sec
From Eq. 23
(30) 0 = wn LA = _1_0_.6_1_x_o._00_2_ = 0_0085
-20
RA
2.5
-40
(The quality factor Q has no units). The motor transfer function, given 1n Eq. 25, is
WM (jw) (31)
V1 (jw)
66.67
y (radNsec)
( 1~~1 + d.~9 + 1
iii
~
-60
I
~ -80
"'
~ -100
(_y,>_)2 G(Jw) " " - - -1' - - - -
10.61
+~+ 1
0.09
1----4--..+---I -150
f---+--+--_,.L._--;e----.---t--+----+--+----< -1ao
03
10 30 100 300 1K
A calculator that is pre-programed to operate with complex numbers (HP 28C, for example, or 15C) makes the
FREQUENCY - (rad/sec)
FIGURE 3. BODE PLOT OF MOTOR DATA IN EXAMPLE.
evaluation, of this equation an easy task. With the 28C you can set up a USER routine called BODE. as follows:
<<DEG DUP ABS LOG 20 X SWAP ARG>>
Note that up to about 100 rad/sec (15.9 Hz) the phase lag barely exceeds 90 degrees. The first pole occurs at w = 0.09 rad/sec, at which point the phase lag is 45
Y N This will convert a complex number x + jy into 20 log at level 2, and arc tan (y/x) at level 1. Table 2
degrees. T,he second pole, widely separated from the first in this ca!ie. occurs at a frequency in excess of 1000
shows a list of several such computations of Eq. 31:
At w = 0, the gain is simply 66.67 rad/Vsec. As w increases from zero up, the gain decreases as shown in the GAIN column of Table 2. For our Bode plot. we want to show the gain relative to the initial. or DC, gain. Therefore, we
subtract 66.67db from each gain value in Table 2 and plot
rad/sec, as we can see from the further bend in the phase curve. The gain, which was drooping at a rate of -20db per decade below 100 rad/sec, now begins to bend
towards a steeper droop of 40db/dec after the second pole
is reached. At very high frequencies, the phase lag will reach 180 degrees.
the result. This is the same as plotting only the function 1
(32) G(jw) = - - - - - - - - -
Used in a speed control feedback loop, this motor will perform well provided that the user takes this gain and phase behavior into account. This is done by incorporating the
( -jw-) 2+ -jw- + 1
10.61
0.09
which should be compared with Eq. 31. The results are shown in Fig. 3.
motor transfer function into the overall loop equation, which will include other components. One's understanding of the
motor's behavior improves with this ty'pe of analysis, which
makes comparisons between different motors more clear and articulate.
Unitrode Integrated Circuits Corporation
7 Continental Boulevard.· P.O. Box 399 ·Merrimack, New Hampshire· 03054-0399
Telaphone 603-424-2410 ·FAX 603-424-3460
9-244
n n1NTEGRATED
~CIRCUITS
-UNITRODE APPLICATION NOTES
U-121
1 MHz 1SOW RESONANT CONVERTER DESIGN REVIEW
Bill Andreycak
Abstract: This paper is intended to explore in significant detail the intricacies of the quasi-resonant half bridge topology. Voltage and current waveforms and transferred charge and energy will be analyzed as functions of time and input/output conditions. Specific and generalized design equations are given, which are also applicable to other topologies by those skilled in modern power supply design.
Introduction:
The pioneers of resonant mode power conversion have generated a tremendous amount of interest in this new and emerging technology and approach to power conversion. Expectations of lossless switching and multi-megahertz operation are rapidly approaching realization. Given this recent stimulus, a new control IC, the UC3860, has been introduced for controlling many of the various resonant and quasi-resonant design approaches.
Despite the differences among the numerous and quasi-resonant switching topologies, all have one common denominator--the need for a high speed, complete and versatile resonant mode control IC. The ideal candidate would incorporate modulator functions or building blocks that could be easily configured by the user to control various circuit topologies and implementations.
This paper will show one application of this resonant control IC in a typical power supply design example. Described in the text is a 150 watt off-line converter switching at a maximum frequency of 1 megaHertz. This results in an effective 500 kiloHertz utilization of the main transformer. Delivering 15 volts at 1O amperes, of load current, it operates from a 110/220 AC input or from a 220 to 370 V de bus at high efficiency.
Design Specifications:
An off-line 150 watt, single output design has been selected as a typical application for the purposes of this paper. Several items common to most designs will not be highlighted, for example, primary to secondary isolation and input filter calculations. However, this discussion will concentrate on relevant calculations and new material regarding tthe quasi-resonant converter.
Input Voltage:
(110 VAc): 85 - 132 VAc
(220 VAc): 170- 265 VAc
(DC Input) : 220 - 375 Voe
AC Line Frequency : 50 Hz min
Output Voltage: 15 Voe
Output Current: 2.5 - 1O Amps
Line Regulation: 16 mV
Load Regulation: 15 mV
Output Ripple: 100 mV p-p, dc-20 MHz Efficiency: 85 % at full load
Quasi-resonant Circuit Operation
The quasi-resonant Buck regulator circuit shown in Fig. 1 is applicable to high frequency power conversion systems and will be
dsescribed in detail. Initial conditions are given with the switch Q open, and no current flowing from the input source V. The resonant current Ir is zero and no voltage is acrosss either of the resonant components L, or C,. There is an output current lout and voltage Vaut delivered entirely by the output filter components L0 , C0 and D0 . For the purposes of this model, assume that each component is ideal.
Switch Q is closed at time to applying voltage VtN across the circuit input. The input current Im begins at zero and rises linearly at the rate of VtN!Lr until it reaches output current lout·
rl1N
LR
IR +I
VIN
=- v -1
CR
Lo louT
lo Co
+Vo Ro -Vo
Figure 1 - Quasi-Resonant Buck Regulator
Simultaneously, the output diode current Id which began at lout linearly decreases to zero. At this point, the input power source is supplying the full output current lout. This occurs at tiime t1 which will
vary linearly with lout and ViN. During the interval between to and t1,
no resonant current Ir flows in capacitor Cr.
Beginning at t1 the resonant circuit current component /,sinusoidally flows through Cr. This adds to the output current, making the input current the summation of both. Peak input current occurs at t1+ n/(2"'). It later intersects the lout level at t2, corresponding to t1+n /"'
The sinusoidal input current continues until t3 where it reaches zero. Here, the switch is opened and turn-off is initiated at zero current which facilitates lossless switching. Since t1 varies with lout and VtN, the zero current switch point t3 varies also with these changing parameters.
A zero current detection circuit can be used to facilitate turn-off at precisely zero current. Another technique utilizes a fixed on time at the primary switches. This time constant is set above the maximum required on time of the resonant network over all line and load combinations. While this technique is easier to implement, it may compromise overall design at the maximum conversion frequency. The inability to switch consecutively at maximum rate hurts transformer turns ratio optimization. Higher currents will result due to the lower turns ratio, degrading overall efficiency at all frequencies.
During the interval between 13 and t4, Cr discharges, providing a constant current lout to the load. The capacitor voltage decreases linearly, reaching zero at t4.
The output filter section releases its stored energy between t4 and ts. The conversion period ends at ts, which corresponds to the beginning of the next cycle, t0 . A detailed analysis of the voltages and currents during each interval is provided in the Appendix.
9-245
Figure 2 - Quasi-Resonant Waveforms
U-121
Quasi-Resonant Half-BridgeTopology Fundamentals and Overview
The general circuit diagram for a quasi-resonant half bridge converter using secondary side resonance is shown in Fig. 3. The resonant half bridge portion and its associated waveforms are shown in Figs. 4 and 5.
Transistors Q1 and Q2 are alternately driven from the control circuitry at a repetition rate, or frequency determined by the error voltage.
Q1 turns on, connecting the transformer primary across capacitor C1 with voltage V1N/2. This rectangular voltage waveform is divided by the turns ratio N (Npn/Nsec) and coupled to the secondary side(s) of the transformer. Diode D1 is fprward biased and secondary current /sec flows through Lr1 and D1. This can be expressed as two individual components, the "constant" output current lout and the sinusoidal current /,through Cr. During this interval, D2 is reversed biased and is essentially out of the picture.
The secondary current starts at zero attime to and ramps up linearly, reaching lout at t1. /sec then becomes sinusoidal, peaks at lsecfpeakJ;and intersects the output current again at t2. At ta, zero current is reached sinusoidally and Q, is turned off.
Peak voltage across Cr occurs at 12 and diminishes during the
remainder of the interval ending at ts. When the voltage across Cr
reaches zero, all of its stored charge has been transferred to the output load, thus completing the conversion cycle. This process is repeated for transistor Q2, resulting in similar operation.
Figure 3 - 150 Watt Off-Line Quasi-Resonant Half Bridge 9-246
U-121
+V1N
~
C1
+ V1N 2
ov I
Figure 4 - Quasi-Resonant Half Bridge
PRIMARY WAVEFORMS
Vos1 0 L..J::J~------- Vos2 0 L________J=:L_
+v1N12 5---,----------T 1-----
vPR1 0 ---
----
-VIN/2 --
-------------------
lpK
lo/N
IPR1 0 -lo1N
-lpK
SECONDARY WAVEFORMS
lo lsEC 0
-lo
-ls(PK) V1N (PK)/N
VcR Vo 0
tt tt t
t
01 23 4
5
Figure 5 - Primary and Secondary Waveforms
Unlike the single-ended forward converters, the half bridge provides bidirectional utilization of the tranformer. This eliminates the need to incorporate dissipative or complex flux reset mechanisms for the main transformer. Also, the primary switched voltage is one-half that of its single ended or full-bridge counterpart, halving the transistor voltage rating requirements.
In addition, the reduced voltage significantly reduces turn-on losses. Bear in mind that zero current switches minimizes on/ythe turn-off losses. During turn-on, however, the current rises linearly before resonance commences, and the half bridge has the lowest turn-off losses of all configurations.
Transformer size is smaller for the half bridge because the forward converter "wastes" half the period with no power transfer while the core is being reset. Also, all windings have half the number of turns compared to a forward converter approach. This could significantly lower the leakage inductance in certain designs where the low voltage, high current designs stand to benefit the most.
Half Wave Resonance: The half-wave resonant mode of operation facilitates a unidrectional current flow from the primary to the secondary. The major advantages of this can be seen near the primary switches. When a reverse current flows through the Mosfet, its parasitic drain-body diode conducts, exhibiting slow reverse recovery characteristics. To pre;vent this, tile reverse current is generally directed to an external fast recovery diode that shunts the Mosfet. A Schottky diode must be added in series with the Mosfet to guarante that the external diode will conduct. This "elaborate" network is not lossless, and can signifcantly impact the power supply overall efficiency.
Seconday side half wave resonance eliminates the need for these components. Reverse current flow is restricted on the secondary side of the tansformer by the series rectifiers. Serving a dual purpose, these diodes isolate the resonant tank from the primary in addition to rectifying the secondary waveform.
Full wave designs return excess thank energy back to the primary, and require bidirectional switches on the primary. One merit, however, is that the switching frequency range is fairly narrow over various line and load combinations. On the other hand, the half wave resonant approach must span a fairly wide range of switching frequencies to maintain regulation for the the same input and output variations, since all resonant tank energy must be delivered to the output.
Ql LR
Tl Dl
l~, ~:::D. tCON~~
T -
ON
Ql
OFF
2V1N
VpRI
Half Bridge Advantages and Alternatives
The thrust towards resonant mode power supply designs has been fueled by the demands for higher power densities and high overall efficiency. Although several basic topologies deserve consideration in this off-line application, the Half Bridge configuration offers many key advantages.
j- TON'-f.--- TOFF-----J
i . - - - - - TPERIOo---~
Figure 6 - Primary Side Half Wave Resonance
9-247
U-121
Secondary Side Resonance: Secondary side resonance helps minimize transformer size. With the resonant capacitor located on the transformer secondary side, the volt-second product depends only on the input voltage and transistor ontime. During the remainder of the period, or off time, the transformer is not supporting the resonant capacitor discharge. Lower core losses are attained with this configuration, and are easier to analyze. The waveform is rectangular and is a function of input voltage, on time and switching frequency.
Resonant Control Circuit
Refer to the simplified block diagram and waveforms of Fig.8.
Error ampllfler: The error amplifier is used to generate an output voltage proportional to the error between the amplifier inuts. A precision reference voltage is at the noninverting input, while the power supply output voltage is applied to the inverting input. The difference between the two is amplified and will respond to millivolt changes in power supply output voltage, providing tight regulation. The error amplifier output is high when the supply output voltage falls below its setpoint, and a low amplifier output indicates the output voltage is higher than ideal. This variable error amplifier output voltage indicates the need for correction to maintain regulation.
of the resonant switches with the proper on-time. In single ended applications like the Buck, Forward and Flyback topologies, toggle function is not used.
High power Mosfet drivers: High peak gate currents are required to deliver sharp Mosfet turn-on and turn-off transitions. The driver accepts low power (TTL} logic inputs and delivers high power (1 to 3 amp peak) Mosfet gate drive compatible outputs.
Zero current switching circuitry: Primary current is monitored and used to turn off the one shot-hence the outputs-when zero current is crossed. This minimizes the switching losses in the primary switches.
Vour
ON Ql
OFF
2V1N
- - - - - - - - . - -.....
0
i.ToN~I-- ToFF-------1
1 - - - - - - TP E R 1 0 0 · - - - . l
Figure 7 - Secondary Side Half Wave Resonance
Variable frequency oscillator: This device converts a variable input voltage to a variable frequency output pulse train. Increasing input voltage yields an increase in the frequency of the output pulses. Regulation of the output voltage is thus obtained over various line and load combinations by varying the switching (conversion) frequency. The VFO is driven by the error amplifier output voltage and is used to trigger the one-shot pulse generator.
One shot pulse generator: This module generates an accurate pulse width, or duration corresponding to the ontime required for the resonant tank circuit switches. In fixed on time quasi-resonant applications this time constant is set slightly longer than one-half of the full resonant period. Another approach utilizes zero current switching (ZCS) which turns off the switches at zero current. In this application, the one shot is programmed for the maximum circuit on-time and modulated to facilitate ZCS.
Toggle flip flop and gating circuitry: Alternating outputs for "bridge" applications require a toggle flip-flop to divide the VFO frequency by two. This provides out-of-phase drive signals to each
Figure 8 - Control Circuit Fundamentals
Quasi-Resonant Circuit Limitations
One obvious circuit constraint is that the peak resonant current component Ir must be greater than lout. Otherwise, zero current will not be reached as shown in the figure below. This relationship specifies the limits of VIN and lout Of the resonant tank as a function of the Lr-Cr resonant tank characteristic impedance, Zr.
Increasing the resonant currrent component far above lout max is one solution, but an inefficient one. The primary switch losses vary with primary current squared, and techniques to minimize this current are required.
The ideal ratio of the output current lout to the minimum resonant peak current lr(pk! min is unity. This insures resonance at all loads while preventing excessively high peak resonant tank currents and losses. The resonant component initial tolerances and temperature variations need to be analyzed and accommodated by adjusting the ratio of lout max to lr(pll)· A twenty-five percent safety margin is used in this design corresponding to a ration of 0.75:1.
The resonant L-C elements are now defined uniquely by the power supply output voltage and load current for a specirfic resonant tank frequency and current ratio lout max to lr(pk)·
9-248
U-121
NOTE: Zero crossing does not occur
when louT > IR (PK)
tl
t2
Figure 9 - lnut Current - No Zero Crossing
several of the references listed in the Appendix. The turns ratio can now be calculated from the volt second relationship described previously.
The transformer turns ratio N =
II: _ VIN Kt N= Kt V,Nmin
o- 2 N '
2 Vo
Accounting for the voltage drops, both the primary and secondary:
N = }5!_. ~"~~~.-: Vio~~!_r
2 Vo min + Vdiode + Vioss sec
The actual transformer secondary voltage has now been defined by
V:nputand the turns ratio N. The conversion period or frequency can
be extracted from the energy transfer equations in the Appendix by substituting Vsec for V1N in the given equations.
In mtn) = ViN min' or Zr :s: ViN min
Zr
lout max
Substituting Zr = wr Lr and V,N= Vsec for secondary resonance, the resonant inductor Lr and Cr are defined by:
1. L _ 0.75Vsecmin = 0.12Vsecmin
r - rnlout max
freslout max
2, Cr= 1 / (oi2L,) = .025/ (fres 2 L,)
3. Verify that Zr < Vout I lout max. If not, the ratio of the resonant to
output current may need to be altered.
Transformer Turn Ratio
The transformer turns ratio is derived by equating the circuit input and output volt-second products. A topology coefficient Kt is introduced which sepcifies the ratio of the maximum switching frequency to that of the resonant tank frequency. It is somewhat analagous to maximum duty cycle in a square wave converter. Allowing Kt to approach unity in a resonant converter maximizes the turns ratio, thus lowering the primary current.
L
~-~--+
D
c
Vo = V1N toN
tPERIOO
~tPERIOO~
Figure 10 & 11 - Square Wave Buck Regulator
As switching frequencies approach 1 MHz, diode recovery times and Mosfet rise and fall times prevent the topology coefficient from reaching unity. In addition, the resonant capacitor requires time to discharge into the output load. A Kt value of 0.8 is suggested by
\ /I
\
\ II
\
\ I I
\
TRES~
1 + - - - - - TCONV _ _ _ __,
Figure 12 & 13 - Resonant Mode Buck Regulator
Conversion Frequency
As the output load current lout and input voltage V1Nvary, the control circuit adjusts the conversion frequency to maintain a constant output voltage, Vout· The maximum conversion frequency will occur at low line and full load, where by design, the frequency equals the resonant tank frequency divided by Kt, the topology coefficient.
Kit =
fconv max
-----,;;;;-
·
'
fconv max = Kt fres
Minimum frequency will occur at high line V1N max and light load lout min which can be estimated by the following relationship:
1
I
fconv
mm
=
T conv
max
=
V1Nmin 2 NVolo
0
min
where
Q = [2NL,lo 2 min+ VIN min C, + rrlo min]
V,N min
N
2fres
9-249
Quasi-Resonant Circuit Relationships
SUMMARY OF APPENDIX1 Timing relationships:
to= time wt1en the cycle is initiated
= t1 Lr* lout I Vsec
dt21 = rr./(r)res
t2 = t1 + db dla2=1/0JresXSin"1(/outZr/Vsec)
HIGH-
t
V1N
~
LOW-
5. Calculate the resonant inductor value, Lr
Lr= 0.12V in min I Ires lout max= 176 nH
6. Calculate the resonant capacitor value, Cr
Cr= .025 I fres2 1out max= 90.9 nF
7. Calculate and check resonant impedance Zn
Zn = (Lr I Cr) 112 = 1.39Q (yes, < 1.5 ohms)
U-121
I
UH tll
I j I
t2L t2H t3L t3H
Figure 14 - Effects of Line Change on lin
Figure 15 - Effects of Load Change on lin
t3 = t2 + dt32
dt43 = V C(t3) Cr / lout t4 = ta + dt43 ts= [Vsec 01 /(Vout lout)] (approx)
The charge transferred per cycle, Qt, is approximated by:
= Ot Lrlout 2/Vsec + 2 Vsec Cr+ rrlout / '"
Design Procedure and Calculations
The design specifications listed on page 1 will be used for this 150 watt application. A maximum switching frequency of 1 MHz has been selected as a good compromise between the attempts to obtain high power density (small size) and high overall efficiency.
1. Select the maximum switching fequency:
fconv max= 1.0 MHz
This also determines the resonant tank circuit frequency using the topology conversion coefficient, K1·
= Kt fconv max/ fres. Use Kt = 0.8
2. Calculate the resonant tank frequency, fres
fres = fconv max / Kt = 1 MHz/0.8 = 1.25 MHz
3. Determine the transformer turns ratio, N
N = Npri/Nsec= KtVJNmin/(2Vout+ \/diode)
= 5.19 (use 5:1)
4. Calculate Vin min, the minimum input voltage referred to the secondary:
Vin min =Vs min/ 2N = 220V/(2 * 5) = 22V
The resonant inductor and capacitor values are calculated using the minimum input voltage to the secondary.
The basic sections of the circuit are now complete. Detailed analysis of the primary and secondary voltages and currents follow,
Peak Current calculations: The peak secondary current is approximated by :
lsec pk = lo + V;n / Zn = lo + Vs/ (2 * N * Zn)
= .072 Vs
The peak current is a function of both input voltage and output current, and is graphically shown in Fig. 16.
The need for high peak current devices in a resonant mode power supply is evident from the values shown below, especially compared with a square wave ·converter of similar output power.
g 40
zf-
w
35
0:: 0::
u::::> 30 :.::
<(
aw.. 25
~
<( 20
0 z
u0ewn
220
300 V1N(V)
8
" m
7
)> ~
-u
~
6
~:s::
--" 5 !!J 4
z:u;-
..__,
380
Figure 16 - Peak Secondary Current vs. Vin and lo
9--250
U-121
The peak current is a function of both input voltage and output current, and is graphically shown in Fig. 16.
The need for high peak current devices in a resonant mode power supply is evident from the values shown below, especially compared with a square wave converter of similar output power.
The peak secondary voltage is:
Vs pk= Vs max /2N = 370/2 * 5 = 37V
Rectifiers in the secondary circuit need to block at least twice the peak voltage, and are typically selected with a much higher rating. Schottky diodes can be ruled out in this 15V output application due to their 45 to 90 volt breakdown voltages, so an ultra to hyperfast diode is required. A 150 volt, 30 amp (DC) device provides ample safety margin. A low capacitance power package is also desired to minimize parasitics and power losses.
rms current calculations: The primary and secondary RMS currents can be approximated to a high degree of accuracy by a pulsed sinusoidal waveform. The relationships derived in the
previous section for peak currents, on times and conversion
frequencies will be used to calculate the RMS currents incorporating the following equation.
The transformer primary wire size will be calculated using the rms current components, in addition to thermal considerations of the transistor switches and rectifiers.
Each of the Mosfet switches, secondary rectifiers and transformer secondary windings conduct current only once per two conversion cycles. This results in a lower rms current through each device.
lrms = /peak [2 TTopner]2
220
300
380
V1NM
Figure 19 - Qt, Transferred Charge vs. V;n and lout
IRMS
0-ic-~~~~>--~~~~~--"'--~~----
~I
Figure 17 - rms Current Calculation
The primary current calculations will use the conversion period of 1/fconv due to the bidrectional switching of the primary. Secondary currents conduct only once per two conversion periods due to the bridge arrangement of the secondary windings. Both low and high input voltage conditions will be examined at full output load to determine worst case conditions.
ToN
(NS)
300
380
V1N(V)
Figure 18 - On Time vs. V;n and lout
200
§'w
~-'
638
0~0::a::.0w.:: 150
(/) (/)
zw
<(-' 0:: ::J
1>---0, 100
t.!lO 0:: 0::
W z w::(2-)! 50
220
300
380
VIN (V)
Figure 20 - Energy Transfer per Cycle vs. V;n and lout
10 ::.Nr:::: 9
x8..... 8
:z> 7
0
()
6
u.
Cl
5
·W
!(( 4
-' ::J
3
~
() 2
220
300
380
VIN {VJ
Figure 21 - Cale. Conversion Freq vs. Vin and lout
9-251
U-121
Low Line
High Line
lsec pk= 26 A lpri pk= 5.2A ton = 575 ns Tper =1.0 µs
lsec pk= 37A lpri pk= 7.4 A ton = 495 ns Tper= 1.82 µs
rms Transformer Primary Current:
lprirms= 2.78A lprirms= 2.72A
rms Current - Mosfet Switches and Secondary Rectifiers:
lrect rms = 9.86 A lrect rms = 9.65 A IMOS rms = 1.97 A IMOS nns = 1.93 A
Timing Considerations: The operation of this quasi-resonant circuit has been described as requiring a variable frequency, fixed on time control pulse train. Actually, the on time rriust be varied to facilitate zero current switching with changes in input voltage and output current. Using the timing relationships presented earlier, the on time is calculated and plotted for the ranges of Vin and lout in Fig. 18.
Transferred charge: The charge transferred from the primary to the secondary per cycle is a function of both Vin and lout. Using the equations presented in the Appendix, the results are graphically represented in Fig. 19.
For the selected values of voltage and current shown, the average change required in voltage or output current per microCoulomb transferred havd been calculated.
Avg dV/µC = 5.935, and Avg dl/ftC = 2.086
The energy transferred per cycle is obtained by multiplying the results from the charge calculations by Vin/2 to convert from charge to energy, with the results shown in Fig. 20.
The conversion period is obtained by dividing the energy transferred per cycle by the output power, accounting for an overall efficiency near 85%. Conversion frequency, its inverse, is graphically depicted for varius input voltages and output currents in Fig. 21.
Power Mosfet Switch Considerations
The power Mosfet selection process must take into account the three types of losses incurred by the high voltage switch. First, and probably the most predominant loss contributor is the FET on resistance, or Rds(on)· Conduction losses are minimized by using a FET with the lowest Rds(on) obtainable.
P1oss de= lpri rms 2 Ads (on) (Watts)
Generally the low resistance is attained by paralleling numerous FET cells of higher on resistance. The result is a single high current, low resistance device with a large die size, or geometry. This technique is greatfor lower frequency applications where the transition (turn-on and turn-off) times are a small percentage of the entire duty cycle. At high frequencies and especially with high voltages, this paralleling scheme introduces many difficulties in minimizing the switching transition losses.
Each cell has a finite output capacitance which quickly "adds up" when many are placed in parallel. The FET output capacitance is charged and discharged to the FULL input bulk voltage each cycle, contributing losses. At high frequencies, changing to a larger size FET could increase the total FET.losses, despite having a lower on resistance. The incremental gains of lower conduction losses are lost to the higher switching losses of the larer capacitance FET. For this reason,. it is a worthwhile exercise to examine several different size FETs over the line and load ranges of this design.
P1oss ac = 0.5Coss Vin2 fcom12 (watts)
The gate drive power losses are generally negligible with respect to the total losses, but can be calculated from:
P1oss gate= 0.5Vaux Ot fconv 12 (Watts)
where Q(t) is the FET total gate charge, accounting for the gate to source charge plus the Miller effect charge.
The greatest primary current occurs at full load, which will be used for the worst case evaluation of power losses. Both high and low input voltage were used to calculate the ac losses, then averaged. The following list is a summary ofthe total power loss for each Mosfet switch in this application. A 1OO'C junction temperature at the FET die was assumed, where the actual on resistance is double that of the published specification. Various size FETs have been analyzed to compare the ac and de losses to select one which exhibits the lowest total losses.
Circuit specifics (at the FET swlthces):
lpri rms = 1.97A at V;n = 220V, fconv = 1 MHz
lpri rms = 1.93A at 375V, 550 KHz Device Rds Coss Qg Pde Pac Pg Ptotal
ea)
IRF720 3.6
64
20 13.7 1.05 0.08 14.87
IRF730 2.0 100 35 7.62 1.57 0.11 9.30
IRF740 1.1 210 63 4.19 3.30 0.19 7.68
IRF820 6.0
54
19 22.8 0.85 0.07 23.78
IRF830 3.0 91
32 11.4 1.43 0.10 12.96
IRF840 1.7 180 63 6.47 2.83 0.19 9.49
IRFP440 1.7 180 63 6.47 2.83 0.19 9.49
IRFP450 0.8 350 130 3.04 5.51 0.39 8.95
IRFP460 0.54 480 190 2.05 7.56 0.57 10.19
The lowest overall losses are obtained with the 740 type devices which will be utilized in this application. This procedure will yield different results for each application, and is a recommended step towards minimizing power losses. ·
Rectifier Selection
Evident from Figures 16 and 17 is the need for high performance rectifiers to achieve an overall high efficiency power supply. Peak secondary currents approach 40 amps, with an rms component near 14 amps. Due to the high peak reverse voltages of nearly 100 volts, Schottky diodes cannot be used as the secondary rectifiers. Even the "freewheeling" diode must withstand 80 volt peaks at high line.
Reverse recovery times must be minimal to prevent reverse current from flowing in the primary switches in addition to enhancing efficiency. While the circuit currents are quasi-sinusoidal, the rectifier voltage is not. Parasitic inductances and capacitances of the device and its package must also be accounted for as part of the resonant L-C tank. This implies that the transformer will be designed for a lower leakage inductance than the resonant L and external inductance will be introduced to obtain the precise amount.
The To-247 package will be utilized for two reasons. First, it has lower parasitics and is better suited to high frequency applications than its To-3 metal case counterpart. Second, it is simple to heatsink this flat package, which can be mounted in various configurations.
Unitrode UES3015S ultrafast 30 amp, 150 volt rectifiers were selected for the secondary input diodes. Typical performance characteristics are 35 ns reverse recovery times and less than 1 V forward drop at 30 A and 125'C junction temperature. The "freewheeling" diode used is a Unitrode UES1615S ultrafast type, with 16 amp de capability and a forward drop of less than 0.85 V. It too exhibits a 25 ns reverse recovery time.
Power dissipation and heatsinking requirements for each device can be calculated using the secondary currents obtained previously in this power supply design. Snubbing of each diode will be left to the prototype stage when any parasitic circuit influences can be evaluated.
9-252
U-121
Main Transformer Design
The transformer design begins with a basic idea of the core geometry most applicable to the particular design. Off-line supplies lend themselves to low, wide winding windows, typical of the ETD geometry. This window shape provides adequate room to accomodate the creepage and clearance distances required for international safety specifications.
Switching of the transformer primary will occur at a maximum of 500 KHz, and standard ferrite materials will be utilized in this example. With numerous choices to consider, the3C6A material was selected.
To begin this 150 watt design, a fair estimate is to keep the transformer losses around 1% of the total input power, or approximately 2 watts. In addition, the transformer temperature rise is desired to be less than 40'C for combined copper and core losses. A core size can be approximated knowing that its thermal resistance, Rt. needs to be in the neighborhood of 40'C/2W, or less than 20'C/W. This is useful as a first iteration to determine the approximate operating flux density required. The precise size will be calculated using the area product formula for core-loss limited conditions, typical in a high frequency power supply.
P;n·104 ]1.sa
2 o.66 4
AP= [ 120K 2f ·(Khf+Kef) cm
where:
Pin - Input Power= 180 Watts K - Winding Factor= 0.163 for half bridge f- Transformer Frequency= 500 KHz Kh - Hysteresis Coeff. (3C6A) = 1.10·5 Ke - Eddy Current Coeff. (3C6A) = 4.10- 10
For this design, the area-product calculates to 0.543 cm4 , which is slightly less than the smallest standard core size, the ETD-34. Because the core volume is slightly larger than required, the actual core losses (per cm3) will be lower than first estimated.
The manufacturers core data lists the thermal resistance of the ETD-34 core set as 19°C/W, with a core volume of 7.64 cm3. Several methods of dividing the power losses between the core and copper can be used. The most common of these suggests an almost equal split between the two, allowing slightly more core than copper loss if possible. An even division of the total losses between the two will be utilized in this design asa first approximation. Later, an evaluation of the minimum number of turns and wire sizes may suggest that the 50/50 ratio be changed to favorably accomodate fewer turns, or less copper. The actual core power density, Pd, is calculated from the following equation, allowing a 20°C temperature rise, T,, due solely to core losses.
.
Tr
20'C
Power Density= Rt. Vol= 19.7.64
Referencing the manufacturers data sheet for the 3C6A material at a power loss density of approximately 140 mW/cm3 and a 500 KHz operating frequency, it is determined that an operating flux density of 300 gauss (0.030 T) be used. The total flux density swing, t.B, is twice that, or about 0.060 Tesla. The minimum number of primary turns is calculated assuming 5 V primary drops, low line conditions, and a cross-sectional core area, A0, of 0.971 cm2 .
. Vpri ton · 104 Power Density= t.B . Ae
A turns ratio N of 5:1 was previously established for this design. Minimized leakage inductance is obtained by "sandwiching" the secondaries between the two primary halves. In this example, one-half of the primary turns will be wound first, closest to the core center leg. Then, the entire secondary is wound directly above the primary half. The final winding is remaining primary half, as shown in Fig. 22.
Copper strip or foil will be used for each winding to minimize "build-up" which increases the distance between windings, hence increases leakage inductance. lfthetransformerleakage inductance is greater than the required resonant inductance, then the transformer must be redesigned for lower leakage.
The required primary and secondary copper cross-section areas are calculated using their respective currents divided by 450 amps/cm2 for a low temperature rise. Other transformer specifics are calculated below.
Primary current rms current, lpri rms = 2. 78 A rms Secondary rms current, Isac rms = 9.86 Arms Primary copper area, Axp = 1-0,; rms /4~0
= .0062 cm
Secondary copper area, Axs = Isec rms /450 = .022 cm2
Pri. inductance, Lpn = ALN/ = 190µH Sec (half) inductance, Lsec = AiN62 = 7.6ftH
The primary conductor area is approximately equal to the area of an AWG # 19 wire, while the secondary area is closest to AWG # 14. Eddy current calculations show that the depth of penetration at 500 KHz is .0106 cm, or about the thickness of anumber 37 AWG wire. The most practical technique to minimize the AC loss in a transformer winding! is to use copper strip or foil, as in this design. Its width is determined by the bobbin width and safety creepage requirements requirements of 8 millimeters as shown.
The required 8 mm primary to secondary spacing between winding ends will be subtracted from the bobbin width of 2.10 cm, leaving 1.30 cm (0.51 inch) for the copper strip width. Allowing for tolerances, standard 0.5 inch width foil will be used in this design. The strip thickness is calculated by dividing the required copper area by the 1.27 cm (0.5 inch) width.
I' 1-1.30 cm (0.512") 2.101 cm (.827")-l
:
1/2 Primary - 5 turns
·
_._copper strip O002" x 0 500" _
I
~
N
- Secondaries - 2 turns x 2 turns -
8
- copper strip 0.003" x 0.500"
§
~
: 1/2 Primar_y - 5 turns
:
"c'i
j'..!!::z:;:·~~~czozp2pe2r~~~r~1p~OZ.OOZZ2'Z'Zx20~.5t00~"--~·zz~l
ETD-34 Bobbin
Insulating mylar film 2 ml thick 0.8 in. wide between each turn
FIGURE 22 - Transformer Winding Layout
105-575·10-9 ·104 ·060·0 ·971
= 10.3turns
(use10)
Pri thickness= Axp/Width = 6.18·10'3/1.27 = .00475 cm, or .00187 in
Sec Thickness= AxsWidth = 2.19·10"3/1 .27 = .01685 cm, or .00663 in
9-253
U-121
Standard 2 mil (0.0051 cm) foil will be used for the primary. This [s slightly larger than the required thickness of .00475 cm, and is less than 1/2 the .0106 cm penetration depth. Secondary penetration is from both sides because of the interleaved primary, so the calculated secondary thickness should be and is less than twice the penetration depth. Two paralleled 3 mil foils are used as secondary conductors.
The resistance and power loss of each winding is calculated from the following relationships, based on the resistivity of copper at 100°C, Pcu= 2.29 · 10·6 Q-cm. Total copper and core losses are also highlighted, in addition to the toal temperature rise at the maximum conversion frequency.
Winding resistance = Pcu · avg te;;th turn · N
Rpri = 2.29 * 10·5 * 5.99 * 10/6.18 * 10"3 = 22.2 mQ Rsec = 2.29 * 10"6 * 5.99 * 2/2.19 * 10·3 = 1.25mQ Pioss winding ;;;;: lrm/ * R Pioss pri = 2. 782 * .0222 = 171 mW P1oss sec = 9.862 * .00125 = 121 .5 mW Pioss copper= 2 * 0.171 + 0.1215 = 0,4635 W
Total power loss = copper losses + core loss Ptotal = 0.464 + 1 (approx) s 1.5 W Temp. rise= Rt x P101a1 = 19°C/W x 1.5W
=2a.s0 c
Output Inductor Design
The output inductor will be designed for one amp of ripple current at the minimum conversion frequency of approximately 200 KHz. Due to the variable frequency operation, the ripple current will change inversely with operating frequency, as maximum load occurs, the ripple current is at its lowest. This mode of operation helps lower the overall losses at full load because with lower ripple the peak current that must be switched is less. In addition, it reduces the size of the output choke since the peak (DC + AC) and full load (DC) current are withinone percent of each other.
Lo= [(Vout+ V diode) *ton max] I Mout
= 15.BV x 5 us I 1 A = 80 ~tH (approx)
At the maximum conversion frequency and Iott min, the output ripple current reduces to:
Mout = [(Vout + Vdiode) X Iott min]/ 80 µH = .OBA
Referring to Section MS of the Unitrode Seminar Manual, core selection starts by calculating the area product:
AP=Aw Ae = [ Lo lpk /ff. 104 ]' .31 420' K· Bmax
A PO type geometry has been selected for the output choke application. The core set closest in size to the required area product is the PQ 32, which is available ih either a 20 or 30 mm height. Of the two, the PQ32/20 size will be used because its height is similar to the ETD34 core set used for the main transformer. Its magnetic area is 1.70 cm2 .
N
L · /pk/ff · 104
min= Bmax Ae
80·10-6·10.08·104 0.30·1.7
The cores will require gapping to store the required energy without saturation. Gap length is calculated from the inductance formula:
lg= (µ 0 µ, N 2Ae·10-21 IL ='0.68cm
using ~to= 4rr·10-7and µ, = 1(air)
Correcting the gap length for the fringing field, a gap of .082 cm (.032") should be used.
Again, copper strip is used to minimize losses. Winding resistance and power loss calculations are similar to those of the main transformer design, and total less than 1.5W.
OUTPUT CAPACITOR
There are two components of ripple voltage which need to be considered in meeting the design goal of 100 mV. They are both caused by inductor ripple current. The first is simply:
Ii Vout = DQ / Gout
For a given ripple current, this component is minimized by increasing the capacitor value. If this were the only contributor, the minimum capacitance required is:
Coutmin ~-12~M2o-u2-t,-1/i~V1:-0-01
This component varies with frequency. At fconv min. 6.25µF are needed, but at fconv max (1 MHz) only 0.1 ~tF is required to maintain the ripple voltage specification.
The second (and usually predominant) ripple voltage component is the voltage drop across the capacitor Equivalent Series Resistance (ESR) caused by the ripple current of Mout. The maximum ESR allowable for 100 mV ripple is:
ESRmax = 100 mV I 1.0 A = 1OOmQ
The two ripple voltage components do not add directly as they are in quadrature. With electrolytic capacitors, the ESR component dominates the capacitor selection. The resulting capacitance value is so much greater than the minimum value required that the /iQ/Cout term can be ignored. An added benefit of a large output capacitance is the improvement in load transient capability.
In this design, two 100 µF electrolytic units were used in parallel to achieve an ESR value of 3 to 15 milliohms - a broad range necessitated by the difficulty in getting specified high frequency data from capacitor manufacturers.
A final component added to the output filter is a good high frequency capacitor to bypass the inductive components of the electryolytics and shunt any switching spikes which might get to the output. Unitrode "P" type ceramic monolithic capacitors are used for this application. Different capacitor types and values can be paralleled to obtain a low impendance over a broad frequency range, useful in this variable frequency application.
Gate Drive Circuitry
The ideal gate drive circuit must deliver sharp turn-on and turn-off pulses to the high voltage power Mosfets. This is made possible by the UC3860 controller's high speed totem pole drivers. Delivering 3 amp peak currents, the drivers have typical rise and fall times of 25 ns into a 1 nF load.
Half bridge circuits require the use of a gate drive transformer to electrically isolate the "high-side" switching transistor from the control circuit. Driving both transistors from the ~ame transformer 180° out of phase offers nearly identical drive signals to each transistor. This tends to balance the switching losses and maintain a narrower band of the associated transition EMI.
The drive transformer must have low leakage inductance to provide crisp edges during the transitions with little overshoot. This makes zener clamps and snubbing circuits unnecessary at the transformer outputs. A 0.50" O.D. toroid is used, fitted with three identical windings of ten turns each. This helps minimize the transformer magnetizing current and maximizes the peak current delivered to the FET gates.
9-254
U-121
OUT A
OUT B
PWRGND
Figure 23 - Gate Drive Circuit
Resistors from gate to source at each FET provide a fairly low impedance to prevent turn-on during start-up while the IC may still be in undervoltage lockout. During regular operation, these resistors have negligible impedance. On the controller side, the UC3611 quad Schottky diode prevents the ICoutputs from going below ground, avoiding substrate biasing problems. A series resistor limits the peak current to the 3 A rating, and the transformer is reset while both outputs are low, between cycles. Zero Current Detection and Switching The primary currrent is used for two important functions in this design, fault protection ans zero current detection. A typical configuration is shown in Fig. 26. The generalized circuit starts with the use of a current transformer in series with the primary of the main transformer to detect primary current. A turns ratio of 1:25 reduces the switch current to a manageable level. It is full wave rectified by 1N4148 diodes (D6-D9) and converted to an appropriate unipolar voltage at the current sense resistor, R,,. In addition, zero current or zero voltage can be detected by using the UC3860 uncommitted comparator. Its open collector output can interface with the RC on timing pin of the one shot, pulling it below the turn off threshold at zero detection. As shown in Fig. 24, this reduces the on time of the one shot timer, allowing the Mosfets to switch at zero current for high efficiency. Implementation reqires shifting the noninverting input between two thresholds so that only the falling edge of primary current is an acceptable input for switching to occur. (See Fig. 25). This is done to prevent a false output from the comparator during the beginning of the cycle, where zero current also occurs. Primary current sensing
v, will be offset by the resistor divider network R21 and R16 from 0t10
ground. This is fed into the invering input of the uncommitted comparator.
PRIMARY CURRENT
COMPARATOR OUTPUT
ONF SHOT RC
£\ I1-, - _~_-_-_-,.~ ... =
I I
_____________ U______ _ I I I I
J______ _ OUTPUT
PRIMARY
CURRENT
I
I
THRESHOLD ----~
I
I
I
I
1- OUTPUT ---------~'~1UI
L_
Figure 24 & 25 - Zero Current Switching
Figure 26 ·Zero Current Switching Circuitry
9-255
U-121
In Fig. 26, adjustments can be made to provide a comparator output justprior to zero current by resistor R20. Propagation delays through the IC and drive circuitry, although minimal, can effectively be "nulled-out" along with Mosfet delays by this technique.
The UC3860 Resonant Mode Control IC
The block diagram of the UC3860 in Fig. 27 displays several key building blocks which together provide the functions necessary for precise resonant mode control. To begin, the undervoltage lockout
turn-on and turn-off thresholds are pre-programmed for 17 and 1o
volts respectively and are used in their standard configuration. This allows ample time for start-up and bootstrapping to occur in an off-line supply while providing adequate Mosfet gate drive voltages. The UVLO can also be reprogrammed for other turn-on and off thresholds. Also, it functions as an alternate· shutdown mechanism. While UVLO is invalid, the UC3860 reference voltage output is held low, deactivating the internal circuitry. The 1% accuracy 5.0 V bandgap reference is capable of driving ten milliamps maximum external loads.
The power supply output voltage will be divided down to deliver 3.0 volts at the inverting error amplifier inpl,Jt for the desired V0u1. With its high gain-bandwidth of 5 MHz, this voltage type op amp also features controlled output voltage excursions. The error amp output swings from 0.0 to 2.0 V above the voltage at the VFO lose input and tracks this node over temperature. This mechanism facilitates the maximum conversion frequency clamp in addition to the voltage (or current) to frequency conversion gain.
Variable frequency operation commences with the error amplifier providing a variable output voltage. This is transformed to a variable currentatthe VFOvariablecurrent input, /v1o. Internal circuitry mirrors
this current to the VFO timing capacitor, Cv1o. Maximum frequency occurrs at 2.0V/Rllfo · Cvto. which coincides with the error amplifier
upper clamp. Minimum frequency is also programmable via resistor Rm from V,erto the lv1o input. The frequency to voltage gain of the IC in MHz/V (orGHz/V) is also established by these timing components. Additionally, the VFO can be externally triggered and/or disabled at the respective input pin accomodations.
Vee UVLO EAIN(+) EAIN(-)
lvFo CvFo TRIG
osc
DSBL RC
MODE CMPIN(+) CMP IN(-)
SFT STRT RST DLY FLT(+) FLT(-)
VREF
EA OUT
c.o Css
SEQUENCE R
CMPOUT
Figure 27 - UC3860 Block Diagram
9-256
U-121
Fixed on-time pulse widths are generated by the programmable one-shot timing circuit. An RC network is charged by an internal source at the onset of a cycle, then self discharges during the on-time. This occurs between the precise thrsholds of the one-shot's comparators. On-time can easily be shortened by an external in fluence used to discharge the RC components below the comparator's turn-off threshold. This architecture simplifies interfacing with various forms of zero voltage or zero current type switching. The output of the UC3860 uncommitted comparator is an open collector which can interface directly to the one shot (RC) timing pin.
Programming the VFO and One-shot:
Let Cvto = 330 pF, Coneshot = 330 pF
frnax =1.05 MHz, frnin =200 KHz 1. frnax =2V/Rvto Cvto ; Rvto =2/(1.05MHz * 330 pF) =5. 77Q 2. frnin =1V/Rrn Cvto; Rm= 1/(0.2MHz * 330 pF) =15.5 kQ 3. ton =0.22 *Ron* Con ; Ron =600ns/(0.22 * 330 pF) =8.26 kQ
The output from the one-shot feeds another programmable module, the toggle flip-flop. Logic selection at the Output Mode pin either alternates the outputs for the dual-ended configurations, or unifies
outputs A with B for single ended applications. As v,.,becomesvalid,
the toggle flip-flop is always steered towards the A output. While this may be of little concern in some designs, a predictable sequence of events upon power-up is always facilitated.
Each totem-pole output is specified for 3 Amp peak drive pulses, sufficient to insure abrupt transitions at the Mosfet switches. When operating in unison, a 6 A peak current is obtained. Rise and fall times into a 1 nF load are typically 20 nanoseconds. As seen in previous high power IC's, the totem pole power ground is terminated through a separate pin which isolates its power ground noise from that of the IC's signal ground.
Soft start is accomplished by limiting the amplifiers output voltage to that of the soft start pin, typical in most IC controllers. An internal 5
v,., microamp current source from pulls up on the external soft start
capacitor, which gradually increases the conversion frequency upon start-up, as opposed to widening the pulse width in conventional PWMs.
Fault protection and management circuits included in the UC3860 are fully user programmable. A fault comparator which has both inverting and non inverting inputs is used to drive a programmable sequence latch. The operation of this latch is controlled at the programmable Restart Delay (AST DLY) pin, and has three unique modes. First, it can be oriented to latch the outputs off until UVLO or Vee are toggled, similar to firing a shutdown SCA. Secondly, it can
be used to cease operation until the fault input is removed from the comparator, then recommence operation. The third and most popular mode is often referred to as "hie-cup" mode. After receiving a fault, the outputs are turned off for a programmed time interval called the restart delay. Operation is then resumed, provided of course that the fault was removed. Implementation only requires a capacitor from AST DLY to ground.
____.n....___ __
FAULT
INPUT
I
I
I
DELAYED RESTART "HICCUP"
I I
FAULT ___In.I.._____ _
I I -----. I
I
NO RESTART DELAY "INTERRUPT"
Figure 29 - Fault Management Waverorms
Closing the Loop There are several gain stages in the quasi-resonant control loop, and each will be examined to obtain good closed loop circuit response. The block diagram below displays the various gain stages.
Error Amplifier: A reference voltage is applied to the non inverting input of the error amplilfier, and the power supply output voltage, through a voltage divider, is applied to inverting input. The error amplifier (E/A) output is commonly referred to as the error voltage
v·. which is an amplifier signal corresponding to the deviation of the
power supply output voltage from the desired level. The compensation network is designed last, after analyzing the other loop gain contributors. It will provide adequate phase margin at the desired zero dB crossover point to ensure circuit stability.
FAULT COMPARATOR
t INTERRUPT
I
s
E
Q
CRD
r 1 I
:
HICCUP
cRo
u
I I
--
E
~LATCH
N
-::- OFF
c
E
--:i_ SOFT
*START
Figure 28 - Fault Management Programming
REF
Figure 30 - Control Loop Block Diagram
9-257
U-121
The varying E/A output voltage Ve is used to gnerate a variable current to the VFO current input pin, lv10. As this current is varied, so is the power stage conversion frequency. A higher Ve corresponds to a higher conversion frequency. These values are designed to track each other over temperature, and a linear voltage to current transformation can be assumed. The voltage to current gain into the VFO equals the 2 volt maximum output swing of the error amplifier divided by the VFO input resistor.
Variable frequency oscillator: The variable frequency converter stage accepts an input current at the lv1o input and generates a proportional output frequency. The gain olthis stage is programmed by the E/A output voltage with the lv10 input resistor and the VFO timing capacitor, Cv10. The VFO output frequency is approximated by:
lose= lvto !Cvto, and fmax = 2V/(Rvto * Cv10)
The minimum frequency is programmed by a resistor from v,.1to the
lv10 input, and the transformation of the error amplifier output voltage to frequency is quite linear.
Error amplifier voltage swing = 2 Volts
fconv = 200KHz min = 1 MHz max
VFOgain:
Gv10 = il.800 kHz I il.2 V = 0.4 MHzN
Power stage: The small signal gain of the power stage is approximated by analysis of the charge transferred at various line and load combinations. An assumption is made that the power switch on time is constant, and any changes in frequency directly effect the off time, or resonant capacitor discharge time. In addition, both V1N and lout are assumed to be constant during the interval of interest.
Based on the relationship that the energy into the resonant circuit, W, equals the output power multiplied by the conversion period:
W = (O;n Vsec I 2) = Power * tconv
= Vout lout/fconv
therefore:
Vout = fconv W/ lout
This term is assumed constant for the interval of interest.
Tabulated below at several points of interest are the values for the values for the power stage gain, from the results ofa previous section in this presentation. The gain (in volts per MHz) varies significantly over the input and output ranges and the highest value will be used to approximate the worst case conditon.
\!IN secV 22 38 22 38 22 38 22 38
lout Win fconv Gain Gain
A µJ/cyc kHz V/MHz dB
2.5 50 450 9.0 19.1
2.5 140 180 10.1 20.1
5
60 730 8.76 18.9
5 160 320 21.4 26.6
7.5 78 900 19.3 25.7
7.5 185 450 22.6 27.0
10 91 1000 19.1 25.6
10 205 560 23.6 27.5
The worst case value of 23.6 V/MHz will be used forthe power stage. Multiplying this by the VFO gain of 0.4 MHzN results in a combined gain VouNe of 9.44 (19.5 dB).
Output Filter Section: The output filter response is defined by:
Lout = 80 ftH; Gout= 200 µF
Rout = 1.5 Q min to 10 Q max
ESR = 2 to 10 m Q
+40 +20
VFO ~ POW~R STAbE GAl1N (+19.5 db)
B
0
~OM~INE~AIN~b.. I
OUTPUT Fil ER ~I
(0 db) (-14db)
~
z
-20 -
ATTENUATOR
~
<(
(.'.)
-40
'\\._
-60 -80
~ ~ ... ~
10 100 lK lOK lOOK lMHZ FREQUENCY (HZ)
Figure 31 · Gains vs. Frequency
Pole frequency=
2rr
- -1-0- 5 (Lout Cout · )
=
1 . 25
kHz
ESR Zer0= 2rrCout ESR = 79.6 - 398 kHz
The output voltage divider shifts the level of the 15 V output to the required 3 V error amplifier input, resulting in a gain of -14 dB.
Compensating the quasi-resonant converter: The generalized approach to this compensation is to place the first pole at a low frequency, typically arond one hertz. Two zeros are then introduced at approximately the output filter break frequency to compensate for its two pole rolloff. A second pole is place at a fairly high frequency to roll off the loop gain in a predictable manner. Unlike their predecessors, the newer control !cs rarely run out of gain bandwidth and require this high frequency pole.
Most of the previously described elements can be lumped together into one gain vs. frequency Bode plot of everything except the error amplifier, as shown in Fig. 31. The VFO, power stage and level shifting voltage divider have gains that are independent offrequency, and are easily combined. The output filter section response is then multiplied by the combined gain of the previous calculation. One curve now depicts the entire loop response from the error amplifier output to its input.
The desired characteristic of overall loop including its zero dB crossover frequency can be shown in a Bode plot, as in Fig. 32. The E/A compensation network will include two zeros near the output filter break frequency to cancel these two poles. Assume for now that the high frequency pole of this circuitry will be around or above the overall zero dB crossover point. The required error amplifier response can now be approximated graphically from the curve and points plotted.
FREQUENCY (HZ)
Figure 32 · Closed Loop Elements
9-258
U-121
0 I
:E s
z
Of-~--+--t--1'--~"'-ci---___,,.
<i'.
('.)
:%s '
180 w
'!i
I
"-
- - =LOOP GAIN
- - - = LOOP PHASE
-200.0 ~~-~-~~-~--"----~---'-----'
1
1
K
M
Figure 33 · Loop Gain and Phase
3V
Figure 34 · E/A Compensation Newtork
In this example, two zeros will be introduced in the error amplifier response near the output filter break frequency of 1.25 kHz. A pole is located near the zero dB crossover point at 50 kilohertz. The actual gain and phase obtained in the overall loop is given in Fig. 33 The error amplifier with its compensation network is shown in Fig. 34. It provides high gain at low frequencies and good transient response. Zero 1:1 (2 rrR1C1) Zero 2: 1/(2rrR2C2) Pole 1: 1/(2rrR3C1) Max Gain: R2i(R1 & R3 in parallel) Input impedance is the parallel combination of R,, R2,and R3 The compensation network is designed to produce: Zero 1 and Zero 2 at 1.24 kHz Pole 1 at 70 KHz > 55 dB loop gain at 50 kHz Using the previous equations and solving:
R, = 6.03K R2 = 78.1 K R3 = 100Q
C1 =22 nF C2 =1.7 nF
From the Bode plot of the closed loop response, the supply is compensated to cross 0 dB at approximately 35 kHz, with ample phase margin.
Power Supply Performance
This 150 watt power supply was evaluated while being exercised over various line and load conditions, and exhibited excellent
regulation. Response to dynamic loading was well within reasonable limits with little overshoot. Short circuit input current is extremely low, due to the programmed restart delay time constant of 50 milliseconds and soft start of 5 milliseconds.
High efficiency (above 80%) is achieved over the operating ranges. This is quite respectable for a high frequency, off-line power supply. The power stage was constructed on a double sided printed circuit board used for a precious high frequency example (1 .5 MHZ current mode) in 1986.
The control circuit is constructed on the Unitrode UC3860 development PC board. The utilization of a ground plane precedes all circuit layout in megaHertz switch mode power designs, and is incorporated here. Coaxial cable interconnects the gate drive, current sense and output voltage signals between the control and power boards. Observation of the circuit waveforms requires the use of a UHF type scope probe socket, or chassis socket. Any length of ground or hook-up wire will distort the true waveforms.
Summary
Above several hundred kiloHertz, the square wave converter may not be optimal for off line designs. Losses associated with switching high voltages at high currents substantially reduce efficiency, power design and generate much EMI. The need for an alternative solution have resulted in various resonant and quasi-resonant approaches, each witih a unique set of merits, applications and control circuit requirements.
The UC3860 controller has integrated the numerous specific functions and "building blocks" required for resonant and quasi-resonant topologies. Configuration for fixed on-time, variable frequency operation is straightforward, and other adaptations are easily made possible. The uncommitted comparator interfaces well with zero current type switching arrangements. Thye UC3860's high speed logic, high power outputs and fault protection circuitry combine for an ideal mix of brains, brawn and speed.
REFERENCES
Unitrode Publications:
Unltrode Power Supply Design Seminar SEM-500:
A2 High Frequency Series Resonant Power Supply Design Review
MS Power Transformer Design For Switching Power Supplies
M2 Winding Data
C1 Closing The Feedback Loop and Appendices
Other Unitrode Papers:
W. Andreycak, "3 Megahertz Resonant Mode Control IC Regulates 150 Watt Off-Line Supply", High Frequency Power Conference, 1988.
R. Mammano, "Resonant Mode Converter Topologies", Unitrode Power Supply Design Seminar SEM600, Topic 1", 1988
L. Wofford, "UC1860 - New IC Controls Resonant Mode Power Circuits", Applied Power Electronics Conference, 1988.
Additional Referernces:
P. Vinciarelli, "Forward Converter Switching At Zero Current", U.S. Patent# 4,415,959
lntertec Communications Press, "Recent Developments In Resonant Power Conversion", 1988 (628 pages - various papers and authors)
9--259
U-121
Resonant Circuits-"Rust Remover" and Appendix
The abrupt transition from conventional square wave conversion to a resonant or quasi'resQnant approach can be softened by a review of certain fundamentals. Fig. A1 shows the sine and cosine waveforms along with the timing
..... +!-+---~~----------!
SIN wt
O-¥------->r----~1-------1
0-+---4------+-------l Coswt
-!-+------"'---''----------~
0 n/2 n 3n/2 2n i-----PERIOD---., Figure A1 - Sine, Cosine Relatlonshlps relatlonshlps
v
V1N
0 +lpK
l(t)
0
-lpK
v
VL(t)
0
-V 2V
Vc(t)
v
I
L
1'-. +
l~v___..vi'_~Vc___,f
* Switch closed at time t = t0
* Switch closed at time t =to
0
t= 0
rr/2
Tl
3rr/2 2rr
Figures A2, A3 - Serles Resonant Circuit
Resonant circuit timing relatlonshlps and waveforms: The waveforms of a series resonant, parallel loaded circuit will be analyzed in detail and used to generate the relationships between time, current, charge and energy transfer in a a resonant circuit application. Specifically, the buck topology will be used in this example, which can be applied to other topologies and configurations.
The cycle is initiated at time 10 Switch Q1 closes, delivering a rectangular voltage waveform to the resonant circuit. The input current rises linearly to lout at a slope equal to Villl'Lr. It reaches the constant output current level lout at time !1. The time for this to occur
= is .MO (!do). During this interval, all resonant inductor current is
directed to the output and none delivered to the resonant capacitor, Cr.
Alto:
Frequency= w/2rr Tperiod = 1/f = 2rr/t·l
More specific to power conversion, a series resonant LC network
driven by a DC voltage source is presented with its corresponding waveforms and equations in Figs. A2 and A3.
w = 1/(LC)112' Zr = (L/C) 112 ipk= ViNI Zr i = ipkSin(oit) = V1N sin(wt) I Zr
= VL ViN cos (wt)
Ve= ViN[1-cos(wt)]
From to to t1,
i;n = V1Nt I Lr
At !1, i;n =lout
8!10 = Lrlout I V1N
At time !1, the input current equals the fixed current lout. The resonant Lr & Cr tank components begin their resonant cycle at zero current, and the input current rises sinusoidally to its peak of lout + vlNIZr, It will later intersect the output current lout again at time 12 corresponding to 1/2 the resonant tank period, rr radians.
9-260
= = = lin lout, ier 0, Ver 0
From t1 to t2: i;n = lout+ (V1N/Zr)Sinrn(t-t1) t>t21=rn/rr=1/(2f) = 1/rr(LrCr)112
Z , l.cr""'
VIN
S.in
(t
(rJ -
t1)
Ver= ll1N(1-cos 0J(t-t1))
Once the input (inductor) current crosses lout at time t2 it continues sinusoidally until it reaches zero at time tJ. At th is point, switch 01 is turned off to facilitate zero current switching. The time required to reach zero current from lout is !>32, and depends upon the amplitude of lout and 11/N.
HIGH-
v!,. I
LOW-
1,.
lour-
I I
tO t1
I I t2 t3L
Figure A6 - i;n, ten vs. Line Variation
U-121
lpKt-8
llN(t)
lour
- --
I- - -
1
0~~1
I
(
t(O) t(l)
t(2) 1(3) t(4) !(PER
- Z- 0 - 2vlNF-
VcR(t) VR
--
-
-
v,N
I
I I
0
I I
t(O) t(l)
I
t(Z) 1(3) t(4) !(PER
Figures A4, AS - Quasi Resonant Buck Converter
1b I I QL'--'--~~~-'--'--'~~-
u1H
t2IL t2IH
UL
t3L t3H
= Figure A7 lln, ton vs. Load Variation
= iin = lout, i, 0, Ver - 2 \lfn
From t2 to tJ:
i'>f32 = _!_ sin-1 [!!!utZ,l
to
Vin
~~ i;n · lout+ sin OJ(t-t1)
Ver= V,N{1-cos w(t-!1))
The resonant capacitor voltage vc, discharges linearly during the interval of M43, beginning at time tJ. The capacitor voltage and t>t43 are determined from the following equations:
Atb:
i;n = 0, ier = 0
Frombto t4:
Ver= Vcrff3) - lodt - b)/Cr
= !>43 CrVc(t3) / lout
Evident from the previous equations is the need to vary the output
on time to respond to the various line, load and resonant tank circuit
influences.
t2 t3
tp
·I·LI;t3-·2I
Figure AS - Charge Transfer
The conversion frequency or repetition rate at the input switch is approximated following some intermediate calculations for total energy transfer from input to output, as follows:
Charge Transfer in the Resonant Circuit
During each resonant cycle a specific amount of charge (Q) is taken from the input supply and transferred to the output load. The corresponding energy (watt-sec) transferred is simply the charge (Q) multiplied by the input voltage ll1N. This relationship will be used to approximate the conversion frequencies required to regulate an output voltage for various ranges of input voltages and output currents.
The input current waveform will be divided into four specific intervals to simplify the calculations. The charge transferred in each interval will be calculated by integrating the current waveform throughout the interval.
Qa. The charge transferred during the time interval from to to t1 is
9-261
U-121
calculated from the equation for the area of the triangle formed:
i'.t1.o = L/JVJN
Qa: = t.t1.o/o/2 = Liou.2!(2ViN)
Qb: During this resonant half-period, the sinusoidal portion of the input current waveform is integrated over the interval t1 to 12.
i;n - lout= (ViN I Zr)sin rn(t-t1)
J VJN t2
Qb = - 2r
sin (rn(l-t1))dt t1
Ob=~vZrr n
[-coso]' 0
1/Zrrn =Cr
:.Qb = 2VIN Cr
Qc: The rectangular area of charge delivered to the output during interval I1to 12 is:
Qc = lou1 t. t21. where i'.T21 = rr/rn
Qc =rrfo<J.JW
Qd: The sinusoidal current decreases from lout lo zero during the 12 and !3 interval. The charge transferred is calculated by subtracting the sinusoidal component from the rectangular region formed by lout
and '3.
t3
Od= lout fl 1:32+ lrf sin (rn(t-t1))dt
l t2
Qd = lout fl 132 - ZVniN"' [ cosO rrrr +rnt.132
Od = lout fl 132 - ViN C, [ cos (rr + m t. l:i2) - cosrr) t. f32 - (1 / w)sin-1(/out Zn/ ViN)
For practical purposes, this area can be repesented by a linear approximation without a significant compromise in accuracy. The
area formed by lou1M32f2 is a reasonable estimate of the area, resulting in approximately 1% error in the total charge transferred. Qd - lout i'.'32/2 = (1/2m)ioul sin"1(lout Zn IViN)
Qt: The total charge transferred from the input to the output per cycle is the summation of charges Qa through Qd.
Qt = Qa + Qb + Qc + Qd
Qt
=
Lfout 2 2Vin
+
2
V C rr lout IN r+-w-
+
lout 2m
.
Sin
-1
loZn
'ffN
The approximation made to simplify the calculation of charge Qd also allows the substitution of charge Qa for Qd, thus reducing the total charge transfer to the following.
Qt = 2Qa + Qb + Qc
Q1 =Lfo-u-t 2+ 2 VINCr+rr-fou-t
VJN
OJ
Energy Transfer During the Resonant Cycle
The energy per cycle, W, can be calculated by multiplying the input voltage ViN by the total charge Qt transferred from the input to the output. Dividing the energy per cycle W by the output power Pout unveils the conversion period - the inverse of the switching frequency.
Tconv= W/cycle = ViN Ot
Pout Vout lout
VJN = Vout lout (Qa +Ob+ Qc+ Qd)
VJN
= Voutfout (2Qa + Qb + Qc)
~
conv""'
ViN Vout lout
[-L--r-l-o-uyt;;;2-
+
2
V:
INC,
+
rrfout] ----;-
Unitrode Integrated Circuits Corporation 7 Continental Boulevard. · P.O. Box 399 ·Merrimack, New Hampshire· 03054-0399 Telephone 603-424-241 O · FAX 603-424-3460
9-262
n n INTEGRATED
~CIRCUIT&
-UNITRODE
APPLICATION NOTE
A NEW FAMILY OF INTEGRATED CIRCUITS CONTROLS RESONANT MODE POWER CONVERTERS
Larry Wofford Unitrode Integrated Circuits Corporation
Southeast Design Center 1005 Slater Road, Suite 206
Morrisville, NC 27560 (919) 941-6355
U-122
ABSTRACT
A new family of integrated circuits is introduced. Devices from this family implement the necessary architecture to co~trol a broad range of resonant mode converters. Key features in the areas of switch timing, fault management, and soft-start technique are unique to this family. Individual devices are customized to handle off-line or DC to DC, single-ended or dual-switch, zero-voltagc-orcurrent-switched configurations. Specific application to three different resonant mode converters is mentioned.
SURVEY OF EXISTING CONTROL INTEGRATED CIRCUITS
Since 1986, interest in resonant mode power conversion has exploded in the technical conferences. IC makers have been quick to respond with offerings of control ICs. Table I is a list of chips available at the present time. To simplify thinking, the first three parts listed are essentially the same design as are the last two. There
are significant differences in features and performance levels between the three groups. However, a common operational philosophy is shared by all: fixed-pulse-width variable-frequency. This approach has been applied to zero-current-switched (ZCS), quasi-resonant mode converters with reported success.
Table I. List of Resonant Mode Control ICs
LD405 OP605 CS3805
UC3860
MC34066 CS360
Fault 3V
Soft-Ref
NI INV E/A Out
Range Rm in Cvco Zero
RC
Fault Logic and Precision Reference
Bias & SV Gen
sv
Gnd
UVLO
Vee
vco
One Shot
Steering Logic
Out A
1----l"J Out B
Pwr Gnd
Figure 1. Controller Block Diagram 9-263
APPLICATION NOTE
U-122
NEW FAMILY OF RESONANT MODE CONTROL INTEGRATED CIRCUITS
As the discipline is maturing, th~ advantage of some feature changes has become apparent. Versatility to control both ZCS and zero-voltage-switched (ZVS) converters is needed. The ability to control proper switch times (on or off) with changing line, load, or component values is needed. To address these needs, a family of controllers based on a common silicon die has been developed. Three members ofthefamily, lhe UCI861, UCI864, and UCI865 will be covered in detail.
The common block diagram of lhe family is illustrated in figure 1. These parts feature an error amplifier (E/A), voltage controlled oscillator (VCO), one shot timing generator with a zero wavecrossing detection comparator, steering logic to two output drivers, a 5V bias generator, and under voltage lockout (UVLO). A latched fault management scheme provides soft start, restart delay, and a precision reference.
Die options can be produced lhat give different UVLO levels, as well as different output properties. There arc two UVLO options. The first, suited foroff-Iin~ operation has lhresholds of 16 and !OV.
While UVLO is active, Ice is less than 0.3mA. The olher option is
8 and 7V, to accommodate lo.,,.er input voltage DC/DC converters.
The flavor of the outputs required by different resonant mode topologies requires lhe steering logic to be configured specially for each application. The basic options lhat can be built allow for single or dual switch drive, and controlled on or off times. Zero-currcntswitching applications require controlled switch on times while zero-voltage-switching applications require controlled switch off times. Figure 2 shows lhese options.
PRIMARY CONTROL BLOCKS
The fundamental control blocks essential for a majority of resonant mode converters arc an error amplifier, VCO, one shot timing generator, and output stage to drive power mosfets.
ERROR AMP & VOLTAGE CONTROLLED OSCILLATOR
Figure 3 details the E/A and VCO. The E/A output directly controls the VCO via the Irange generator. The VCO has inputs for
two resistori:, Range and Rmin' and one capacitor, Cvco· Rmin and Cvco determine mmimum frequency.
* Fm.m =
3.6
(Rmin C vco>
(1)
Ona Shot
SlnglaZCS
Clock
SlnglaZVS (UC1864)
DualZCS A (UC1865) . ' B
DualZVS A (UC1861)
B
Figure 2. Output Drive For Different Converters
Table 2 details lhe options implemented in lhe 1861, '64, and '65. Olher options can be bwlt from 1he same die.
Table 2. hnpiemented Options in lhe 1861, '64, '65.
Device
UC1861 UC1864 UCI865
UVLOVlh
i6/10V 8/7V 16/lOV
Outputs
Dual Single Dual
Zero-C?l-Switching
Voltage Voltage Current
Figure 3. Error Amplifier and Voltage Controlled Oscillator
When lheoutputof the E/A is less than or equal to one diode drop above ground, the VCO operates at minimum frequency. The E/A output can go as high as one diode drop below 5V. When at this potential, lhe VCO frequency is at its maximum.
3.6
(2)
(RangcllRmin) * C vco
Usable maximum frequency tops out aro~nd 1.5MHz. The Frequency range is the difference in equations 2 and 1.
6F=
3.6
(3)
Range *Cvco
9-264
APPLICATION NOTE
Since the nominal E/A output swing is approximately 3.6V for full variation in VCO frequency, the gain of the VCO block is
·c dF/dV =
Rangc
vco
(4)
In ZCS power supplies, an increase in frequency will correspond to an increase in the converter's output voltage. For these applications the E/A non-inverting input is connected to a reference voltage while the output voltage sense is fed back to the inverting input. For ZVS power supplies, a decrease in frequency corresponds to an increase in output voltage. For these systems, the inputs to the E/A are exchanged.
The common mode range of the E/A is from zero to 6V. This feature allows zero volts to be a valid reference voltage applied to the E/A. Soft start, covered later, takes advantage of this feature.
ONE SHOT TIMING REQUIREMENTS
The basic premise in resonant mode conversion is packets of energy delivered at varying repetition rates. Each energy packet dictates a basic switch on or off time, hence the one shot timer. In ZCS systems the switch is on. In ZVS systems the switch is off. The timer, then, should force the switch to conform to the resonant timing of lhe tank circuit. It is this conformance that achieves zero stress switching.
= L 16.4 µH
Load Oto 1A
z.
L=
= 16.4µH
2nF
0
U-122
(8)
C=
= 3.16nF
(9)
2nZ F
0 0
Figure 5 shows the pertinent current and voltage waveforms for the case of 125V input and 0.8A output. When the switch closes at zero time, the current starts to build linearly. Once the current reaches 0.8A, then load current is completely supplied through the inductor and D2 carries no current. At this point in time the Land C resonate together until inductor current returns to zero. At this time the switch is allowed to tum off, but itdoesn'tnccessarily have to. DI prevents reverse current in the switch. It isn't necessary to open the switch until the capacitor voltage decays to line voltage. It is acceptable to open the switch any time during this "switch window". If it is opened too soon, the circuit will suffer severe switching losses. Ifit is not opened, the tank will resume resonating, as shown by the dashed curves. Ifthe switch is opened later than the switch window, not only will the circuit suffer switching losses, but the transfer function becomes overly complex.
Inductor 2_5
Line= 125V Load: O.BA
= L 16.4 µH = C 3.16nF
1L00i n e [ 01
to
150V
02 E=3.16nF
Figure 4. ZCS Resonant Tank Example
For purposes of convenience, a simplified ZCS resonant tank is presented to illustrate the timing requirements of resonant converters in general. This is an example, not a rigorous theoretical presentation. It does, however, demonstrate the problems to overcome in properly controlling a resonant mode converter. The circuit of figure 4 is designed to operate from line inputs of 100 to 150V and 0 to lA load current. The tank frequency is arbitrarily selected to be 700kHz. A reasonable first guess for tank impedance is determined by
(5)
z = 0 I · 1.386 m.. 72ohms.
From the equations governing resonant tank natural frequency and impedance, L and C can be calculated.
F. =
=700kHz
(6)
2n'4LC
ff z =
=72ohms
0
(7)
2_0
1_5 1.0
...........
0.5
(µs)
o~-t"-~~~~~~-+-~~--1~~~~~~-
o
0.5
1.0
1.5
2.0
Figure 5. Typical Resonant Tank Waveforms
The graph in figure 6 plots the switch window as a function of load current for both high and low line voltage. For example, at a load current of 0.5A and high line, the switch must be closed for at least 0.80us and need not be opened until 1.61 us. Examination reveals the most stringent switch window, 1.03 to 1.21 us, occurs at low line and full load. Furthermore, this window is a subset of all other windows. This might lead to choosing a fixed on-time of l.12us underthe assumption that it is relatively easy to build a fixed time one-shot circuit with total variation.< less than +/-8%. However, further consideration will lead to a different conclusion.
In order to insure that the example in question can be produced, the variations of the resonant components and the possibility of output overload must also be examined. This example continues by assuming total variations for the capacitor are under 10% while under 20% for the inductor. A 20% overload is also allowed.
9-265
APPLICATION NOTE
U-122
Time (µs)
~0-----.-..---....--~----.----~
Minimum Switch 0.5 Times 1------t-----+-----+-~=~-1
L = 16.4 H C = 3.16nf
o . __ _ _..__ _ _.....__ _ _.....__ _ __,
0
0.25
0.5
0.75
1.0
Load Current (A)
Figure 6. Minimum/Maximum Switch Time vs Load Current
5V
Figure 7 shows the valid switch windows·at 1.2A and 1OOV for nominal component values as well as the four tolerance comen. Several observations can be made. Firstly, the window for the case of+20% inductor and -10% capacitorvariations has zero tolerance.
Time (µs)
1.5 I- Component Tolerance:
1.4 t-
Lt.20%
1.3 ICt.10%
1.2 I-
1.1 t-
1.0 I-~
I
~
~
Line = 100V Load= 1.2A
0.9 IL(·)C(·) L(·)C(+) NOM L(+)C(·) l(+)C(+)
Figure 7. Switch Window vs Component Value
Clock ·(Internal)
Vth2 RC Vth1
Zero 0.5V
One Shot
Figure 8. One Shot Timer.
Minimum Pulse
Maximum Pulse
Zero Controlled P11lse
9-266
APPLICATION NOTE
U-122
The switch must turn off at l.30us. This is because the tank impedance is exactly the ratio of low line voltage to overload current for these component values. This is the source of the 1.386 factor in equation 5. Secondly, and thcpointoftheillustralion, there is no possible value of fixed switch time that accommodates component variation.
ONE SHOT TIMING GENERATOR
In figure 8, details of the one shot timer arc seen. The clock signal from the VCO sets the latch, blanks the output, and causes tlte RC
timing pin to be discharged. The timing pin determines the mirtimum and maximum times the one shot output will be high.
Tmax R*C
(JO)
T . 0.3 *T
(11)
mm
max
Between these two limits, the zero detect comparator will terminate the one shot pulse whenever the Zero pin goes below
0.5V. By sensing the zero crossing of the resonant waveform, the
one shot adapts to different resonant component values and varying line/load conditions. The switch time will properly track the resonant tank assuring zero stress switching.
STEERING LOGIC & OUTPUT STAGE
Figures 9, 10, and II, are block diagrams of the steering logic and output stages. Each output stage is a totem pole driver optimized for driving power mosfet gates. Gate currents of IA can be obtained from each driver. Note the 1864 single driver is actually both drivers on the chip paralleled. Sample waveforms for the three configurations were shown in figure 2.
Fault and UVLO response ofthe three configurations is identical. These indications always force both drivers to the low state. During UVLO, the outputs can easily sink 20mA irrespective of Vee.
One Shot
Fault Latch------'
UVLO
Figure 9. UC1861 Steering Logic
1Pwr ·Gnd
One Shot Fault Latch
UVLO
·Pwr Figure 10. UC1864 Steering Logic :Gnd
One Shot
Fault
Latch----~
UVLO
Figure 11. UC1865 Steering Logic
SECONDARY BLOCKS
The secondary blocks on board are UVLO, a 5V bias generator, and fault management with a precision reference. The purpose of the 5V generator is to provide a stable bias environment for internal circuits and up to I OmA of current for external loads. The one shot timing resistor connects to 5V.
UVLO senses both Vee and 5V. It doesn't allow operation of the chip until botlt are above preset values. When Vee is below the UVLO threshold, the SY generator is off, the outputs are actively pulled low, me fault latch is set, and supply current is less than 300uA.
SOFT START, RESTART DELAY, PRECISION REFERENCE
A novel combination fault management ancl precision reference is shown in figure 12. One pin is dedicated to a fault sense comparator with a 3V threshold. A second pin does triple duty providing soft start, restart delay, and precision system reference. UVLO initializes the latches, forcing the chip output(s) to be low and the Soft-Ref pin to be discharged. After UVLO, Soft-Ref is charged by an internal 0.5mA current source until is it clamped at
9-267
APPLICATION NOTE
UVLO
0.2V
U-122
Force
. . . - - - - - - - - - - - - - - - - - - Output(s)
UVLO
Low
s
4V
s
S:O
R: 0.5mA
Soft-Ref
5.00V
20µA
UVLO
Fault
Output(s)
5V 4V Soft-Ref
0.2V Figure 12. Fault Comparator, Soft Start, Restart Delay And Precision Reference
5V. The soft start time is approximately given by:
* Tsoftstan = Csr 1Okohms.
(12)
The recognition of a fault causes the outputs to be driven low and the Soft-Ref pin to be discharged with a 20uA current source. This is the restart delay period. When Soft-Refreaches 0.2V, the outputs are enabled and the pin is recharged by the 0.5mA current. If a fault should occur before completion of the charge cycle, the outputs are immediately driven low, but the Soft-Ref pin is charged to 4 Volts before the 20uA restart delay current discharges the pin. The restart delay time during continuous fault operation is:
* T,.....n = C., 190kohms.
(13)
The ratio of restart delay to soft start is 19:1. If shorter restart delay times are desired, aresistorof20kor larger can be added from Soft-Ref to ground. The timing equations then become:
Tsoftstan = Rsr * Csr * In (
(0.48mA * Rsr) - 0.2 ) (0.48mA * Rsr) - 5
(14)
Time (ms) 200
150
Restart Delay Time
100 CSR: 1µF
50
Soft Start Time (~10ms)
o.___ __,.___---1.____.____,___.___ _,
20k 50k 100k 200k 500k 1M 2M Restart Delay Resistance (Q)
Figure 13. Soft Start And Restart Delay Times
9-268
APPLICATION NOTE
U-122
(20uA · Rsr) +4 )
(15)
T =
=tart
R sr
*
Csr *
ln
(
(20uA * Rsr) + 0.2
Soft and restart times are plotted in figure 13 for Csr = luF.
The restart feature can be defeated by the addition of a IOOk resistor from Soft-Ref to 5V. In this configuration, a fault detection will permanently shut down the converter until either Vcc is recycled and UVLO resets the fault circuit, the lOOk resistor is opened, or Soft-Ref is externally pulled to ground. The soft start time becomes:
Tsofistart = C., * 9.2kohm.
(16)
The Soft-Ref pin is the system reference pin. By ramping the reference from zero during soft start, the converter output will follow the ramp up under closed loop control. This technique allows controlled starts for both ZCS and ZVS systems with no significant overshoot.
The reference characteristic of the Soft-Ref pin is due to a trimmed 5V zener-type clamp circuit. Fifteen ohms resistance separates the Soft-Ref pin from the clamp to eliminate zen~r oscillations for any external capacitance value. The clamp zener is
designed to tolerate loading of +/- 200uA without degradation of
reference accuracy. Loading, however, will alter the soft start and restart delay times, and could even preclude restart delay action unless care is taken in the design.
DC/DC ZVS SINGLE ENDED FORWARD CONVERTER APPLICATION
A ZVS multi-resonant forward converter based on previously reported (ref. 4) work is shown in figure 14. An 1864 is used to control the converter. A 22k resistor from the input line is used to start the circuit, which boot-straps power from the output to the chip after start-up. Before start-up, the chip draws less than 300uA and starts operating when Vee reaches 8V. After start-up, the 22k resistor dissipates 70mW.
The switch voltage, V, is sampled with a 1001</5. lk divider network. The chip anticipates zero crossing when V = 1OV. In this power converter, switch voltages of200 to 300V areto be expected. A pnpis used to clamp the zero voltage, Vz to prevent damage to the chip. The I OOk resistor represents an insignificant load to the resonant circuit.
The paralleled outputs are connected, as good practice dictates, to the mosfct gate with a small-valued resistor. A schottky diode parallels the output pins to protect the chip from negative voltage spikes that might result from parasitic ringing in the gate circuit.
This power stage was demonstrated to have excellent short circuit tolerance when the minimum switching frequency is well controlled. For this reason, the fault input is not used.
Sensed output voltage is scaled & presented to the non-inverting pin of the E/A. The inverting input is DC referenced to the Soft-Ref
A B
PGND
Soft Ref
1864 Zero
sv
v.lL, 100k
-
Vz JJL0.5
Vz ·
0
5.1k
Fault
Gnd RC
I- I-
Figure 14. ZVS-MR Forward Converter Controlled By VC1864.
9-269
APPLICATION NOTE
AC
EMI
+ Bridge
220 to 380V
U-122
Figure 15. ZCS Off-Line Half-Bridge Converter With UC1865
pin, 5V. The compensationnetwork shown represents zero DC load
to the Soft-Ref pin. As long as C., is much largerthan the feedback capacitor, then soft start behavior will be essentially as described in equation 12.
V + -....-----..--..-...,
OFF-LINE ZCS HALF-BRIDGE CONVERTER APPLICATION
AZCS off-line half-bridge converter (ref. 1) with an 1865 control IC is shown in figure 15. Irrelevant details in the converter have been simplified. The wide UVLO hysteresis and low start current of the chip have been used in start-up. A single resistor from the high voltage bus is used to start the circuit which then sustains itself from output voltage.
This circuit samples resonant current with transformer Tl. Rectified secondary current, converted to an analog voltage, is applied to the fault and zero inputs of the 1865. Excessive current in the resonant tank will effect a shutdown and restart. The resistor between current sense transformer and the zero pin is to limit
I
Figure 16. ZVS Half-Bridge Converter
9-270
APPLICATION NOTE
U-122
current when the signal is at a high value. The allowable voltage range at the zero pin is zero to 9V, and resistive current limiting to less than lmA is sufficient.
The half bridge power mosfets arc transformer driven from the differentially eonneetod ou1pu1 drivers of Ute 186S. A UC3611 schottky diode array has been used to prevent the outputs from being forced too far above Vee or below ground.
The E/A non-inverting input is directly connected to the Soft-Ref pin to take advantage of all three features of the pin. This emphasizes the simplicity of application of the 1865 to this converter.
OFF-LINE ZVS HALF-BRIDGE CONVERTER APPLICATION
An off-line ZVS half-bridge converter (ref. 3) is shown in figure 16. An 1861 controls this converter in much the same manner as the two previous examples and is not shown here. The error amp configuration matches the ZVS example while the output ~tage is configured like the ZCS example.
This application does, however, present a difficulty in sensing zero voltage to control the one shot. In the first ZVS example, the voltage waveform was ground referenced and unipolar. The ZCS
V+
example had bipolar current, but a transformer and diode bridge conditioned Ute signal for Ute chip. In Utis example, zero switch voltage needs to be sensed for boUt Ql and Q2. This poses no real problem for Q2. Ql is another story. Some form of external circuitry must bo employed lo sonso Qt and transla.to tho information to the ground referenced chip.
An easily implemented high voltage comparator circuit is shown in figure 17. The pnp and diode are the only high voltage components used. The circuit dissipates only 300mW. The output of this circuit is applied directly to the zero input of the 1861.
CONCLUSION
A new family of integrated circuits to control resonant mode converters has been introduced that provides several improved features over Utosc previously available. This family has parts lhat arc suited not only to zero-current-switching, but also to zerovoltage-switching converters. The 1861, 1864, and 1865 are suited to off-line ZVS, DC/DC single ended ZVS, and off-line ZCS systems. Controllers for other specific converters can be built from lhis family. Adaptive control for resonant tank component variations as well as varying line arid load conditions is inherent in the chip due to its zero crossing detect circuitry. A unique one pin approach to soft start, restart delay, and system reference provides
as adjustablc restart delay to soft start time ratios as well closed loop
control during soft starts. Relative ease of application to lhrce previously reported converters was discussed.
39V 39k
45pF
REFERENCES
1) Andrcycalc, UC3860 Resonant Control IC Regulated Off-Line !SOW Converter Switching at IMH~ pp 472-481, HFPC'89
1M
Proceedings
i/s
2) Gontowski, Upadhyay, A Practjcal lMHz Resonant-Mode
1/2V+
Controller Integrated Circuit Features a Linearized VCO and Tcmnerature-Compcnsated One-Shot. pp 192-200, HFPC'89 Proceedings
I
---
--
3) Jovanovic, Tabisz, Lee, Zero-Voltage-Switching Technique jn High-Frequency Off-Linc Converters, pp. 23-32, Sixth Annual VPEC Power Electronics Scmiriar Proceedings, 1988
4) Tabisz, Lee, A Novel. Zero-Voltage-Switched Multi-Resonant Forward Converter, pp 42-51, Sixlh Annual VPEC Power Electronics Seminar Proceedings, 1988
5) Upadhyay, Harris, Pace, A New High Performance Resonant Mode Control IC, pp 181-191, HFPC'89 Proceedings
n I\ o.sv
~--U--V
Figure 17. Zero Voltage Sensing Scheme For ZVS Half-Bridge Converter
Unitrode Integrated Circuits Corporation
7 Continental Boulevard.· P.O. Box 399 ·Merrimack, New Hampshire· 030540399
Telephone 603424-2410 · FAX 603424-3460
9-271
n n L:::::J INTEGRATED CIRCUITS
-UNITRODE
APPLICATION NOTE
UNIQUE CHIP PAIR SIMPLIFIES ISOLATED HIGH SIDE SWITCH DRIVE
U-127
John A. O'Connor
Application Engineer Motor Control Circuits
Abstract
High voltage, high current N-channel MOSFETs, now widely accepted in the industry, have found their way into numerous high power designs. As their cost to performance ratio continually improves, gate drive circuitrybecomes amoresignificantfactorin overallswitch cost. This is mostnotable in "high-side"switching applications where an isolated gate drive is required. A new integrated circuit pair, the UC3l24/UC3725, will be presented which implements a simple, isolated MOSFET gate drive circuit. To achieve a cost effective high side switch drive, UNITRODEhas developeda unique modulation technique which transmits both signal and power across a small pulse transformer. This publication supercedes Unitrode Application Note U-124, originally written by C.S.Silva.
INTRODUCTION
Designers of power drives for PWM motor controls and switching power supplies often face the problem of driving· the high-side MOSFET transistor in a high voltage power stage. In many applications, for example, bridge and three phase configurations, there are several of these switch drives to implement, and the level of complexity can be discouraging. From a cost standpoint, it is advantageous to utilize N- channel MOSFET devices in comparison to their more expensive - yet easier to drive P-channel counterparts. However, these high-side switch gate drive circuits can quickly become extravagant, and frequently result in complicated or unreliable schemes.
Probably the most common technique used in high-side drive circuits is to generate an isolated, or "floating" auxiliary supply voltage. Referenced to the high-side MOSFET's source, this supply powers a conventional gate drive circuit. The average auxiliary power consumed is generally well below one watt, and varies with switching frequency, FET size and number of paralleled FETs used to configure "one" switch. A typical circuit using this method is shown in figure 1.
With the realization that average MOSFET gate drive power is quite small, charge pump circuits are frequently used to implement the floating supply. In these designs, .the storage capacitor can become large in an attempt to minimize the supply's ripple voltage and may impair the useable range of frequencies and duty cycles. Due to this constraint, the switch on-time must be limited by the control circuit, and preferably, undervoltage lockout incorporated in the driver circuit to assure reliable operation.
A simple alternative to this discrete approach can be obtained by using a high voltage IC provided that the maximum switch voltage and on-time are within it's capability. There is, however, a cost penalty for this single chip solution. While the basic gate drive and protection circuitry have a low voltage requirement, the level shifting transistors necessitate a high voltage IC process - an option which is inherently expensive. Additionally, many motor drive circuits cannottolerate an on-time limitation, and require an auxiliary power supply for continuous (DC) operation.
9-272
APPLICATION NOTE
Typically, an opto-coupler is used to translate the switch activation command from the ground referenced, or "low-side" control circuitry up to the high-side driver. Unfortunately, this technique comes with its own set of reliability issues which includes low common mode transient immunity, and performance degradation over time and temperature. High voltage MOSFET circuit slew rates
U-127
can easily exceed 20 kV/us causing opto-coupler self tum-on or turn-off. The opto-coupler's AC common mode rejection must be carefully evaluated, as this specification is usually influenced by common mode voltage as well as dv/dt. Power up and power down sequences also present potential failure without undervoltage lockout circuitry.
TYPICAL HIGH SIDE DRIVER APPLICATION
DRIVER
PWM
POWER PATH
REGULATOR
+
BRIDGE RECTIFIER
SIGNAL PATH
PROTECTION
TO LOAD
Figure 1.
UC3724 / UC3725 DRIVER PAIR - BASIC CIRCUIT
Vee 1 uf
1 uF(cer.) 3
2
UC3725
4
HIGH VOLTAGE RAIL
N-CHANNEL MOSFET
Figure 2.
9-273
......------. OUTPUT LOAD
APPLICATION NOTE
UC3724/UC3725 DRIVER PAIR The Unitrode UC3724/UC3725 IC pair offers a compact, and comparatively inexpensive design solution to the problem· of supplying both isolated power and command signals. Figure 2 shows the basic circuit implementation. The two ICs, a pulse transformer, and a few passive components form a complete isolated MOSFET driver. A unique modulation technique simultaneously transmits power and command information across the transformer.
Provided the operational voltage is low, integrated circuit technology allows sophisticated circuits to be implemented at low cost. Transformers can easily provide several thousand volts of isolation, while supplying both power and signal. By exploiting each device's strengths, a low cost, high performance solution is achieved.
The UC3724 transmitter IC generates the carrier signal, with one of two possible duty cycles as commanded by the TTL level input. A unique carrier oscillator design not only sets the operating frequency, but also prevents the transformer
U-127
from saturating, by assuring that the transformer magnetizing current is zero before initiating a subsequent oscillator cycle .. Average transformer voltage is always zero, even under the transient conditions ca.used by input command changes. Saturation of the transformer core is virtually impossible using this technique.
To minimize transformer size and cost, a high frequency carrier is used. Although the carrier frequency limits the maximum transmitted switching frequency, it has no effect on input to output delay, which is solely determined by circuit propagation time.
The UC3725 driver IC rectifies the transformer isolated carrier to power the driver circuitry. Additionally, comparator circuitry determines the input command by sensing which duty cycle is transmitted, driving the MOSFET gate accordingly with the high current output stage. A comparator with programmable off time circuitry implements local over-current protection, while an enable input provides additional control and protection flexibility.
UC3724 ISOLATED DRIVE TRANSMITTER - BLOCK DIAGRAM
BIAIG&NIRATDR l UNDER VOLTAGE
LOCKOUr
GND
PWR
GND
Figure 3.
UC3724 DRIVE TRANSMITTER
The UC3724 block diagram is shown in figure 3. The circuit consists of a bias voltage generator with under voltage lockout, control logic, a retriggerable one-shot, a TTL compatible input with hysteresis, two tri-level output drivers, and two
zero current sense comparators.
The under voltage lockout inhibits the output drivers when the input supply voltage is below 9 volts. Once adequate supply voltage is present,
9-274
APPLICATION NOTE
the bias generator supplies the appropriate internal voltages and currents, allowing the outputs to be enabled. This assures correct operation at power-up and power-down.
The carrier oscillator uses both a one-shot pulse width and the transformer core reset time to set the overall period. The one shot pulse width (TPW) equals one-third of the nominal carrier period, and is set by timing resistor (F\) and capacitor (CT).
1) TPw=0.51·Rr ·CT +150ns (sec)
"Full" supply voltage is applied to the transformer primary during this time by driving one output high and the other low. Transformer magnetizing current rises linearly at a rate determined by the primary inductance and applied voltage.
VA-VB 2)dildt= - - (amps/sec)
Lprt
When the one-shot pulse ends, the low output switches high, and the high output switches to
U-127
approximately one-half of the supply voltage. This applies "half' supply voltage to the primary, effectively in a reverse polarity to that of it's previous state. Internal offset circuitry compensates for output conduction voltage drops and maintains the full/half voltage ratio over temperature and supply voltage variations.
Power is transferred to the secondary circuit only while full voltage is applied to the primary. During this period the primary current is a composite of load and magnetizing current. The load current is interrupted when the half voltage is applied, so the residual primary current flowing is the magnetizing current.
With half voltage applied, the magnetizing current falls at one-half of the rate at which it had increased. An interval twice the programmed oneshot period is therefore necessary to reset the cores magnetizing current to zero and prevent any possibility of core saturation. The UC3724 incorporates a zero current detection circuit which guarantees that the magnetizing current has reached zero before initiating another oscillator cycle.
UC3724 OPERATIONAL WAVEFORMS (STEADY STATE)
Ct(2V/div) trace 1
Vpri A-B (20V/dlv) trace2
output A (20V/div)
trace3
outputs (20V/dlv)
trace4
Figure 4.
I mag (20ma/div)
trace 5 01
I sec (20ma/div)
trace&
01
lpri
(20ma/dlv) trace 7
Horizontal
(1 OuS/div) 01
to t1
t2
9-275
APPLICATION NOTE
Steady-state (continuous logic low input command) waveforms are shown in figure 4. The first trace shows timing capacitor(Cr) voltage, which is charged by a current set by the timing resistor (f\). At time t0 , the one-shot is triggered, discharging the timing capacitor. OutputA (trace 3) switches high, and outputs (trace 4) switches low, with the resulting differential voltage "ririA·s (trace 2) applied across the transformer primary. The transformer magnetizing current (trace 5) increases linearly at a rate described by equation 2.
Attirrie t1, the timing capacitorvoltage reaches the 2.5 voltthreshold, ending the one-shot period.
OutputA is switched to (V00/2) + V.,11981 , and outputs
is switched high, allowing it's catch diode to conduct. The primary voltage (VpriA-s), is inverted, and reduced in half, causing the magnetizing current to fall at half the rate at which it had increased.
U-127
OutputA's current sense comparator senses that the magnetizing current has reached zero at t2 , triggering the one-shot, thus initiating another oscillator cycle. If a continuous high is commanded, the waveforms for outputA and outputaare interchanged, and the magnetizing current is inverted.
At an input command transition, the existing oscillator cycle is terminated, the A and B outputs are reversed, and a new oscillator cycle is initiated. This applies full voltage of the appropriate polarity across the transformer primary for detection by the UC3725. Although the oscillator cycle has been terminated without allowing the core to reset, there is no danger of saturation. By reversing the outputs, the magnetizing current must first cross through zero before rising in the opposite polarity. The peak magnetizing current is actually less than a normal cycle, reducing the fall time, and hence the oscillator period.
UC3725 ISOLATED SIDE MOSFET DRIVER BLOCK DIAGRAM
...----------------1-1"13 Vee
HYSTERESIS COMPARATOR
INTERNAL REFERENCE
Figure 5.
9-276
APPLICATION NOTE
UC3725 ISOLATED MOSFET DRIVER The block diagram for the UC3725 is shown in figure 5. The circuit consists of a Schottky bridge rectifier, an internal reference with under voltage lock out, a differential hysteresis comparator, a high current totem-pole driver, a current sense comparator with programmable off time one-shot, and an enable input.
The Schottky bridge rectifies the isolated secondary voltage, providing power for the IC. A small capacitor, typically a 1uf ceramic, provides filtering and bulk storage to supply the high peak currents required to rapidly charge the MOSFET gate.
The undervoltage lockout inhibits the output driver when the supply voltage is below 12 volts. This assures that sufficient voltage is available to drive the MOSFET gate, preventing possible destructive linear operation.
The output driver is capable of delivering nearly two amps peak, which is more than adequate for most applications. The UC3725 features a self biasing drive arrangement which actively sinks gate current during under voltage lockout, preventing MOSFET self turn on. No additional gate to source resistor is required. The output voltage is clamped to 15 volts, which along with under voltage lockout, virtually eliminates the possibility of incorrect gate drive voltages
Over-current protection is provided by monitoring the voltage across a source resistor. The current sense comparator triggers a one-shot, which turns off the MOSFET, when the voltage
q" exceeds 0.5 volts. At power-up, is charged to
7 volts. When an over-current is detected, the output is latched off, and the 7 volt source is disabled allowing R0" to discharge C011 · When coif discharges to 2 volts, the output is enabled and C011 is charged back to 7 volts. Off time is typically selected to maintain safe MOSFET junction temperature with a continuous fault load, and is programmed by timing resistor (R011) and capacitor (C011 ) with the following equation.
3) 7;;11 =1.28·R,,11 -C011 (seconds)
An enable input allows direct output control for specialized applications. It can be used with level
U-127
shifting transistors, optocouplers, or other source referenced circuitry such as a UC3730 thermal monitor circuit for MOSFET over-temperature protection.
The input command, transmitted by the UC3724, is demodulated using a differential hysteresis comparator. The comparator senses whether the "full voltage" applied to the transformer is positive or negative, corresponding to an "off" or "on" input command. The bridge rectifier causes the peak secondary voltage to always be two diode drops above \te while the comparator hysteresis is internally set to twice Vee . The MOSFET is turned on when the secondary voltage is more negative than -(Vee), and turned off when more positive than Vee. Note that there is a logic inversion between the hysteresis comparator and the gate driver.
Referring to steady-state waveforms (figure 4), the secondary current (trace 6) charges the supply capacitor during the full voltage output segment of the oscillator cycle (time t0 thru t1 ). During the half voltage output segment (time t 1 thru t 2 ), no secondary current flows, thus only magnetizing current is present in the primary current (trace 7), allowing proper oscillatoroperation.
For this example, a 30% duty cycle input command was arbitrarily selected, and the associated waveforms are shown in figure 6. At time t0 , the input command (trace 1) transitions from low to high, immediately switching outputA low, outputs high, and retriggering the one-shot. The differential hysteresis comparator switches low, driving the output (trace 4) high, when the transformer secondary voltage ('{ecA-B' trace3), is more
negative than -('f:el· The primary current (trace 2)
is inverted from the outpu~ and outputs reversal, but power delivery to the IC is unaffected due to the bridge rectifier input.
The input command transitions low at time t1, switching outputA high, outputs low, and retriggering the one-shot. The hysteresis comparator switches high, driving the output low, when the
secondary voltage exceeds 'te. Note the reduced
magnetizing current fall time, and associated oscillator period reduction, after input command transitions.
9-Z77
APPLICATION NOTE
OPERATIONAL WAVEFORMS AT 30% DUTY CYCLE
input SV/div
ov
trace 1
lpri 50ma/div
trace 2
01
Vsec A-B 20V/div trace 3
ov output 20V/div
trace 4
Horizontal
ov
50 µS/Div
U-127
Figure 6.
PRACTICAL CONSIDERATIONS
The selection of carrier frequency (or more appropriately one-shot period since carrier frequency varies at switching transitions), is influenced more by transformer design than performance objectives. The minimum switching command period should be limited to four times the one-shot pulse width, to assure that adequate time is available to reset the core. Note that this limits the maximum switching frequency - but not the duty cycle range which is always 0 to 100%.
Waveforms for a command period approximately four times the one shot pulse width are shown in figure 7. The carrier oscillator has sufficient time to reset the transformer core and prevent saturation.
The one-shot period has no effect on input to output propagation delay, since the leading edge provides the output command information. Turnon and turn-off propagation delay waveforms are shown in figure 8.
Figure 7.
INPUT "'-+-----'
OUTPUT O V - - 1 - - - - - + - - - + - - '
INPUT OY
OUTPUT HONt 100nSIDIV 1
9-278
Figure 8.
APPLICATION NOTE
The maximum carrier frequency is limited to 600 Khz. Most circuits will operate between 200 and 600 Khz., allowing switching frequencies up to 450 Khz., and a simple low cost transformer design. Nominal carrier frequency is calculated using equation 4.
4)F0 = - - - - (Hz)
where Tpw = one-shot pulse width from equation 1.
Power supply voltage directly affects dissipation in the transmitter IC. Typical supply current verses voltage for the UC3724 is shown in figure 9. In most applications, bias power loss is about half of the total power dissipation.
U-127
becomes excessive, resulting in a large number of turns or larger core size. Therefore, the optimal range of peak magnetizing current is between 10 and40 mA.
In many applications, the average gate charge current delivered by the driver is insignificant in relation to the UC3725 bias current. When larger MOSFETs, particular1y large parallel assemblies, are driven at higher frequencies, the average gate charge current will have a considerable effect on the total transformer load. Average gate charge current is the product of gate charge (Qg), which is specified by the MOSFET manufacturer, and the switching frequency.
5) /9 (avg.) =09·F8 (amps)
where Og = gate charge
F8 = switching frequency
All of the charge delivered to the gate at tumon must be removed at tum-off. The resultant average power dissipated by the driver and gate resistor is described by equation 6.
"'+-----11-----+---+---+-----t
. ... . . . 10
"
(\1. . .)
Figure 9.
The UC3725 driver IC provides sufficient gate voltage with a 15 volt supply. Any further increase, although safe since the output is clamped to 15 volts, causes additional bias power dissipation. By adjusting the transformer turns ratio, a 15to18 volt secondary supply can be generated with any primary voltage, allowing maximum efficiency .
Magnetizing current also contributes towards increasing dissipation with supply voltage. Although the UC3724 outputs can handle several hundred milliamps of load current with the output transistors in saturation, nearly one-half Vee is across the upper transistors during the magnetizing current fall time. Dissipation during this period usually limits the peak magnetizing current, although catch diode current (which only conducts falling magnetizing current) is limited to 50 mA peak. When the peak magnetizing current falls below 10 ma, the required primary inductance
where vg =fully charged gate
voltage
The over-current input on the UC3725 has a typical delay time of 150 ns. Most applications require a small RC filter to attenuate leading edge current spikes caused by parasitic capacitance and catch rectifier reverse recovery. Careful attention to layout and component selection is necessary to prevent false triggering. The current sense resistor should be non-inductive to minimize spiking and ringing. The filter capacitor should be located as close to the IC as possible, with direct connections to the comparator input and common. The connection between the UC3725 common, and the MOSFET source resistor, must have relatively low impedance to prevent gate drive current from affecting current sense accuracy. In addition this should be a "Kelvin" connection, such that no load current flows through it. If the current sense feature is not required, the comparator input is simply connected to common, and the timing input is allowed to float.
9-279
APPLICATION NOTE
DESIGN PROCEDURE
Typically, the application dictates the MOSFET(s), switching frequency, and switch isolation voltage. For cost considerations, a supply voltage common with other circuitry, is usually chosen to power the UC3724. The designer is then left with the carrier frequency and peak magnetizing currentto select. A high carrier frequency is normally used to minimize transformer size and cost. Magnetizing current is initially set to a nominal value, such as 20 ma, and then adjusted if necessary to optimize the transformer design.
The one-shot pulse width is set to 1/3 the carrier frequency using equation 1. By rearranging equation 2, and allowing 2 volts for saturation, the transformer primary inductance can be calculated.
(Henries)
where Vee =supply voltage Tpw = one-shot pulse width
1ma9= peak transformer
magnetizing current
Transformer core selection is an iterative process based on the following two equations.
8) Li B=
vapplled. T,,n ·104
(Tesla)
Nturns ·Ac
9) Nturns =
(turns)
A toroid is usually the most cost effective core geometry for this application. The core material should be chosen for low losses and high permeability at the design frequency to minimize transformer size and number of turns. Thermal resistance and loss factors provided by the manufacturer are used to select the optimum core size. A flux density of .05 Tesla (500 Gauss) will cause approximately a 20 degree Crise at 500 KHz with common power materials such as Ferroxcube 3C8.
U-127
Typically most toroids used for this application have an AL between 1000 and 3000 mH/1000 turns. An estimated number of turns is calculated using an average AL value of 2000 mH/1000 turns in equation 8. By rearranging equation 7, an approximate core are is calculated using a flux density of .05 Tesla, and the estimated number of turns. This leads to a first core selection, and an actual AL value, which is used in equation 8 to calculate Ntums· The flux density is then checked using equation 7, and a larger or smaller core is selected if necessary.
The turns ratio is calculated using the following equation, which allows 2 volts for UC3724 output saturation, and 3 volts for UC3725 rectifier drop and output saturation.
10) Turns ratio= Vga1e+3
The power supplied by the transformer is the sum of the UC3725 bias loss and the average gate charge power. For minimum wire size, the resulting RMS winding currents can be calculated, although typically there sufficient space to use 24 to 28 AWG wire for ease of handling.
High voltage isolation is implemented by sleaving the primary winding with an insulation suitable for the required breakdown voltage. For low leakage inductance, bifilarwindings are used, with additional turns added to the primary or secondary for non 1:1 turns ratios.
DESIGN EXAMPLE
The following design example is a general purpose isolated MOSFET gate driver. Up to 200 milliwatts is available for gate drive, which is suitable for most applications. A 15 volt power supply provides sufficient secondary voltage by using a step-up transformer.
Driver specifications : * 200 milliwatts average gate drive power * 100 KHz. switching rate * 15 V supply voltage * 1KV minimum isolation voltage
A 600KHz. carrier frequency is selected to minimize transformer size and cost. The one-shot pulse width is calculated by rearranging equation 4.
9-280
APPLICATION NOTE
U-127
Tpw = - - - 3·600 KHz
= 556ns
Since the carrier frequency is near maximum, 2K will be used for RT . CT is calculated with equation 1.
241·109 1620
= 12.2 turns (use 12 turns)
The flux density is checked using equation 8.
(556-150) ns 0.51·2K
(15-2) V·556ns·104 AB=
12 turns·0.148 cm2
= 398pf (use 390pf)
= 0.041 Tesla
30mA is selected for the peak magnetizing current. The corresponding primary inductance is calculated with equation 7.
(15-2) V·556ns
Lpr1 = - - - - -
30mA
= 241µH
The estimated number of turns are calculated using equation 9 with an average value of 2000 mH/1000 turns for AL.
2000
= 11 turns
The approximate core area is calculated with equation 8, using a flux density of 0.05 Tesla.
13V·556ns·104
11 turns·0.05 Tesla
= 0.131 cm2
A one-half inch diameter toroid, Ferroxcube part number 204T250-3C8, is selected which has the following specifications.
Ac= 0.148 cm2 AL = 1620 mH/1000 turns
N,urns is calculated using the actual AL value in equation 9.
9-281
The turns ratio is calculated using equation 1Ofor a gate voltage of 12 to 14 volts.
Turns ratio
(15-2) v (12+3) v
= 0.867
Therefore Nsec= 14 turns
The transformer is wound with 26AWG magnet wire for ease of bandling. A teflon insulation sleeve is slipped over the primary winding to improve the primary to secondary breakdown voltage. The primary and secondary are wound bifilar, to minimize leakage inductance, then the two remaining secondary turns are wound.
To verify operation, the test circuit shown in figure 10 was built. The over current, gate and bulk storage components are selected per MOSFET and load requirements. Figure 11 and 12 show turn-on and turn-off waveforms respectively.
The lower MOSFET in figure 10 was configured to test self turn-on of the upper driver during high transformer dv/dt. With 300 volts slewing at a rate in excess of 25 kv/us, no evidence of driver self turn-on was observed.
APPLICATIONS
Although the lower MOSFET driver is configured for faster switching than would normally be required, figure 10 is typical of half bridge outputs, where two or three of these circuits could implement a full or three phase bridge respectively. Full isolation for UL or VOE requirements can be met
APPLICATION NOTE
by using isolated drivers for both upper and lower MOSFETs. This configuration can also greatly reduce noise in high current applications, by com-
U-127
pletely isolating the control circuitry from output devices.
TYPICAL HIGH SIDE DRIVE APPLICATION CIRCUIT SCHEMATIC
vcc
UC3724
UC3725
1 uF
INA
INPUT
INB OUT
QI
10ohm
TIM IS Roll
ENA COM
o.os VDD
1
RL
vcc
UC3705
vcc
+IN OUT -IN
GND
SO ohm
J:
GND IR1'740 QZ
UC3611 DIODES
LOW SIDE DRIVER
":"
Figure 10
v..
IOVIDIV
FULL BRIDGE OUTPUT
lo 1AIDIV
o.,__ _:rJ
2H0OnRllIDZ.IY ...._......._.___._..__ _.___._....__ _.
Figure 11
lo 1A/dlv
v.. 0
IOV/dlv 2HO0RnIZe·/D. ,,,.___.,__...._.._.............__...._.._.....___.,.......
Figure 12
Some circuits have multiple MOSFETs driven from the same command, which are isolated from each other. A most notable example is the full bridge, which is commonly used in brush and stepper motor drives. Multiple secondaries can drive additional isolated UC3725 circuits, from a single UC3724, further reducing cost and complexity.
Figure 13 shows a fully isolated bridge circuit. By isolating all of the MOSFETs and the current sense signal, complete control to output isolation is achieved. Dual secondaries on each transformereliminates the requirementfortwo additional transformers and UC3724s. For feedback and protection, a hall effect current sensor monitors load current directly, while providing high voltage isolation. The local over-current circuit in the upper FET drivers protects during load to ground shorts.
9-282
APPLICATION NOTE
FULL BRIDGE OUTPUT CIRCUIT
UC3724 T2
+15
UC3725
VDD
t
OUTPUT B
UC3637 CONTROL CIRCUIT
HALL EFFECT CURRENT
U-127
UC3725
T1
OUTPUT A
CURRENT FEEDBACK
vcc
Figure 13 HALF BRIDGE OUTPUT CIRCUIT
UC3724
SGND PGND RT CT PHI
UC3725 vcc
INA
INB RoffCoff
TIM
OUT IS
ENA COM
UC3725
VDD
J ' ' IN
5817 1'ohm
I-
IRF740
QI
RSI lµF
RL
INA
INB RoffCoff
TIM
vcc
IN 5817 OUT
IS
ENA COM
IRF740 Q2
RS2
VDD
!
J
GND
Figure 14
9-283
~
APPLICATION NOTE
HALF BRIDGE OUTPUT
By reversing the polarity of one of the secondary windings on a dual secondary transformer, two FETs are switched out of phase from each other. A typical application for this arrangement is the half bridge, and is shown in figure 14. Dead-time between turn-off and turn-on is difficult to implement using this technique. To turn off both FETs, the UC3724 supply voltage must be removed, or the UC3725 enable inputs driven high. While shutting down the supply voltage is suitable for power-up/power-down protection, it is to slow to control dead-time. Isolating or level shifting the enable inputs adds complexity and negates the advantage of using a dual secondary transformer. Cross conduction is easily minimized however, by the gate resistor arrangement which provides rapid turn-off and slow turn-on. This technique is also typically used. to minimize cross conduction caused by stored charge in the MOSFET body diode.
U-127
LEVEL SHIFT DRIVER
The UC3725 makes an excellent level shifted driverforlowervoltage, non-isolated applications. All of the necessary protection features which are often omitted in discrete designs are incorporated in the UC3725, assuring reliable operation under all conditions. Figure 15 shows a typical level shift circuit with a "boot·strap" supply. The MPS-U1 O level shift transistor has a maximum Vceo of 300 volts, although it's dissipation without a heatsink limits the maximum supply to approximately 200 volts. Figure 16 shows input to output propagation delay while switching 150 volts and 3 amps. A 20 mA current source with a voltage compliance 15 volts above the supply rail can be used in place of the boot-strap circuit, for applications which cannot tolerate an on-time limitation. The cost effectiveness of this approach will depend on supply voltage and number of high-side MOSFETs.
LEVEL SHIFT CIRCUIT
+15
IN
4936
T INPUT
MPSU10 1K 2N2222
100 uF 10K
1K 200
"::'
IN 4148
Roff
UC3725
INB vcc
INA OUT TIM IS ENA COM Coff
~JVD:DH1'
Q1
10
IRF
740
Rf
Rs
Cf
50
"::'
Figure 15
9-284
APPLICATION NOTE
INPUT 5V/OIV
OUTPUT 50V/OIV o
OUTPUT 50V/OIV
INPUT 0 5V/DIV O HORIZONTAL '----'-___J'--------'----'--L--'-___J'--------'----'-__J 100ns.IOIV
Figure 16.
LATCHED OVER-CURRENT FAULT Current limiting is provided by the control circuit in many applications. Local protection from the UC3725 is therefore only required for fault conditions which result in high di/dt such as output shorts. It may be desirable to latch the output off under such a fault, rather than enable after a fixed off-time. Figure 17 shows a simple circuit used in place of the timing resistor and capacitor which
U-127
will latch the output off after the over-current comparator is triggered. The 1Ouf capacitor resets the circuit at power-up by holding the timing input below the 2 volt one-shot threshold. When an over-current is sensed, the timing input voltage falls, and is clamped at 5.1 volts. The one-shot period normally ends when coif is discharged below 2 volts, but by clamping the voltage, the time constant effectively appears infinite.
TIMING VCC
COMMON Figure 17
FAST AC SWITCH
vcc
UC3724
UC3725 INA vcc
SGND PGND RT
CT
R1
UC3730T
V1N 2.5V
ALARM
THRESH.
GNO
INB OUT TIM IS ENA COM
Coif Rolf
20
IRF740 Q2
Figure 18 9-285
APPLICATION NOTE
FAST AC SWITCH
Fully isolated gate drive lends itself to unique power switching circuits which are otherwise extremely difficult to implement. Figure 18 is a fast AC switch with over-current and over-temperature protection. The MOSFETs are selected to withstand the peak AC voltage, with each FET blocking in the opposite polarity. Figure 19 shows a 100 ohm load switched across 115 VAC, 60 Hz. The diode network allows current sensing in both directions, with the 4.7K resistors functioning as current sources. Protection against excessive MOSFET junction temperature is accomplished by mounting both FETs and the UC3730T on the same heatsink. MOSFET thermal resistance Ounction to heatsink), and maximum FET dissipation must be considered when selecting the shut-down temperature set by R1 and R2. Refer to UC3730datasheetforadditional information. A 1OOOpf/20 ohm snubber is connected across the switch to reduce turn-off voltage spiking. The actual snubber values required are determined by load conditions.
SUMMARY
U-127
A unique integrated circuit pair, the UC3724/ UC3725 has been presented that provides a simple, low cost, isolated MOSFET gate drive solution. Protection features prevent abnormal gate drive voltage, and provide over-current limiting. Duty cycle or on time limitations typical of other techniques are avoided, and by utilizing a transformer for isolation, there are no inherent isolation voltage limitations. The circuit is suitable for fully isolated systems which must meet UL or VDE requirements, as well as typical high-side switch applications.
REFERENCES
1. c. de Sae Silva, "CHIP PAIR PROVIDES
ISOLATED DRIVE FOR POWER MOSFETS IN
PWM DRIVES REQUIRING 0TO100 % DUTY
CYCLE", UNITRODE APPLICATION NOTE# U124
2. W. Andreycak, "1.5 mHz CURRENT MODE IC CONTROLLED 50 WATT POWER SUPPLY", UNITRODE APPLICATION NOTE# U-110
3. W Andreycak, " A NEW GENERATION OF HIGH PERFORMANCE MOSFET DRIVERS FEATURES HIGH CURRENT, HIGH SPEED OUTPUTS", UNITRODE APPLICATION NOTE# U-126
Figure 19.
UNfTRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD.· MERRIMACK, NH 03054 TEL. 603-424-2410 · FAX 603-424-3460
9-286
n n INTEGRATED
~CIRCUITS
-UNITROOE
APPLICATION NOTE THE UC3823A,B AND UC3825A,B ENHANCED GENERATION OF PWM CONTROLLERS
BILL ANDREYCAK
U-128
ABSTRACT
This application note will highlight the enhancements incorporated in four new PWM control !Cs, the UC3823A, UC38238, UC3825A and UC3825B devices. Based upon the industry standard UC3823 and UC3825 controllers, this advancedgeneration features several key improvements in protection andperformance over theirpredecessors. Newly developed techniques such as leading edge blanking of the current sense input and full cycle soft start protection following a fault have been incorporated into the design. Numerous enhancements to existing standard functions and features have also been made.
INTRODUCTION
Higher degrees ofintegrated functions within PWM JC controllers are necessary to remain in pace with todays advancing powersupply technology. Many externalfeatures, used almostuniversally bydesigners, have been builtinto this new generation of UC3823A,B and UC3825A,B PWM controllers. These control enhancements can be classifiedas eithera performance orprotection improvement, and an itemized description ofeach will be presented. The new features are:
PERFORMANCE IMPROVEMENTS
- Lower startup current - Accurate oscillator frequency - Leading Edge Blanking - Higher current totempole outputs - Higher G.B.W. Error Amplifier
PROTECTION ENHANCEMENTS
- Active Low outputs during UVLO - Advanced undervoltage lockout - Latched fault logic - Full-cycle soft start - Restart delay after fault
Note: 3823A,B version toggles 0 and Qare always low
Figure 1 - UC3823A,B and UC3825A,B Block Diagram
9-287
APPLICATION NOTE
UC3823A,B AND UC3825A,B FEATURES PREVIEW AND APPLICATIONS GUIDE
In most applications, the UC3823Aand UC3825A devices are enhanced drop-in replacements for the UC3823 and UC3825 high speed PWMs. The "A" suffix versions (UC3823A and UC3825A) feature similar undervoltage lockout (UVLO) thresholds to the preceding generation which tum on at 9.2 volts and tum off at 8.4 volts. Off-line power supplies can benefit from the wider UVLO hysteresis of the "B" version devices (UC3823B and UC3825B) which tum on at 16 volts and off at 10 volts. This, in conjunction with the lower startup current of 100 microamps can streamline the IC's power supply and minimize startup circuitry power loss.
One significant difference will be found on the UC3823A and UC3823B controllers. Formerly, the UC3823 (non A or B version) provided access to the current limit comparator's threshold at pin 11. This could be accurately set by the user within the range of 1.0to1.25 volts with an external reference voltage. The UC3823A and UC3823B devices use pin 11 as a high current totempole output, identical to that found on pin 14. These outputs can be paralleled - effectively doubling the peak output current capability to 4 amps. No access to the previous current limit reference (I LIM REF) comparator is provided as this threshold is internally set to 1.0volts with a+/- 5% accuracy over all operating conditions. Existing applications can incorporate the UC3823A or UC3823B devices by simply removing any of the former external biasing components to pin 11.
U-128
high gain bandwidth error amplifier (12 MHz). Unity gain bandwidth is also up from 5.5 MHz to 9 MHz. This should not require changes to the PC board layout unless the compensation circuit design relied upon the older 5.5 MHz UGBW for high frequency roll-off.
STARTUP FEATURES
Since a majority of PWM applications are off-line converters, a low startup current is desirable. This attribute minimizes the complexity and power loss of the startup power supply once normal operation is attained. Every milliamp of additional startup current drawn by the controller results in a power loss of approximately 385 milliwatts in a power factor corrected application. Heat, PC board real estate and additional cost are unnecessary extras which can be eliminated with a lower startup current controller.
+400VDC
RsTART
15VDC
BOOTSTRAP
=
c TO OUTPUT
One other major difference to the prior generation of PWMs is the reduced maximum operating supply (Vee) and collector supply (Ve) voltages of 22 volts versus 30 volts. This characteristic is a principal consideration when determining the IC power supply, as nearly all applications utilize a supply voltage between 10 and 15 volts. Typical supply current is higher, 28 mAversus the former22 mA, however the maximum Ice is unchanged at 33 mA.
Since many of the enhancements in this new family of PWMs are executed using internal circuitry, most applications require no additional components externally to realize a performance or protection advantage. The list of improvements which includes latched fault protection and full cycle soft start should not require any PC board changes. The leading edge blanking feature, however, will require one capacitorfrom the CLOCK/LES (pin4) to ground to facilitate programming.
The improved oscillator section can be optimally programmed for the correct frequency and maximum duty cycle combination. No changes to the timing component values of Rt and Ct are necessary. Additionally, high frequency current mode applications can benefit from the
Figure 2 - Startup/Bootstrap Circuit
This new generation of UC3823A,B and UC3825A,B control ICs minimizes the startup current to 1OOuA typically. Once the IC crosses its undervoltage lockout threshold, the current drawn will increase to the typical running current
In an off-line converter, two things are necessary to get the main converter up and running when the control IC turns on. First, the IC should contain wide undervoltage lockout hysteresis. Second, the bootstrap supply should come up and into regulation very quickly before the auxiliary capacitorvoltage drops below the ICs lower (tum-off) undervoltage lockout threshold.
Undervoltage lockout thresholds are primarily determined by the allowable MOSFET gate voltage range. Operation with gate-to-source voltages above sixteen volts can cause overstress to the device, and voltages lower than about nine volts can cause linear FET operation. The ''8" suffix designator (UC3823B and UC3825B) is used to define devices which exhibit typical undervoltage lockout thresholds of
9-288
APPLICATION NOTE
16V (tum-on) and 1OV (tum-off) for off-line applications. The "A" suffix parts (UC3823A and UC3825A) incorporate 9.2V (tum-on) and 8.4V (tum-off) thresholds for DC to DC converter applications, and are compatible with existing UC3823 and UC3825 (non A,B) UVLO thresholds.
SUPPLY CURRENT
(mA)
TURN+ · TURN
OFF
ON
0.5 ""IL---------t·P 8.4 9.2
SUPPLY VOLTAGE (V)
Rgure 3 - 9.218.4VUVLO Thresholds-DC/DC Converters
SUPPLY CURRENT
(mA)
TURN. · TURN
OFF
ON
U-128
the DC (bulk) high voltage rises, a capacitive divider is formed at the MOSFET switch between the drain-to- gate and the gate-to-source capacitances. A quickly rising bulk supply can couple a problematic gate drive command to any FET driven without a gate pull down circuit. Since the control IC is below its tum on threshold, the unbiased output drivers of older PWMs cannot prevent the switch from turning on under these circumstances.
One solution to prevent this parasitic tum-on during under-
vottage lockout is to incorporate an active low, self biasing totem-pole design in the driver output. As shown in figure 5, a PNP drive transistor (02) is connected between the output pin of the IC and the lower NPN output transistor (03). As
the output voltage rises, transistorQ1 is biased on through the 50K ohm resistance. This causes the base of Q2 to go low, turning Q2 on. The output pin supplies drive bias to the main totem-pole transistor, 03, directly through the saturated PNP. Increasing voltage on the output pin provides more drive to transistors 01, Q2 and 03. The saturation voltage of this circuit at moderate currents (1 OmA) is well below the tum on thresholds of the power&Mtching MOSFETs. This circuit is removed from operation once the undervoltage lockout requirements have been satisfied. Transistor Q4 is turned on with a valid UVLO which voids the possibility of transistor Q1 from ever turning on during normal operation. Additionally, a 250 microamp current source from Vee
keeps the PNP predriver (Q2) off after UVLO.
vcc
0.5 IL:~---------~~ 10 16
SUPPLY VOLTAGE (V)
Rgure 4 - 16/10VUVLO ThresholdirotfLine Power Supplies
SELF BIASING, ACTIVE LOW OUTPUTS DURING UV LOCKOUT
Another enhancement to the new UC3823A,B and UC3825A,B controllers is found in the output stages. During undervoltage lockout almost all internal functions of the control IC are disabled, primarily to obtain a low startup current. Generally, this would result in little or no available bias to actively keep the outputs low during this power-up
condition, when ifs needed the most. Outputs are in a high
impedance state which is typically about 1 megohm. As
OUT
PGND
Figure 5 - UVLO SelfBiasing Outputs
Another benefit of this technique is obtained during power down. As the IC crosses below its lower UVLO threshold, the self biasing circuitry is enabled. Any residual voltage on the output will similarly tum the totempole stage on which
actively pulls the output low. This feature insures correct gate
drive operation regardless of the tum off sequence.
9-289
APPLICATION NOTE
3~~~~~~~~~~~~~~~~
I
P""
ILlL
0 0!--'-__._........,.~~2.._...__._~o.~4..___..__._~o.s,_._...._~o~.s_......._......,.1.o Current (Amps)
Figure 6 - Output Vand I During UVLO
OSCILLATOR ACCURACY
Fundamental to the design of any switchmode converter is maintaining an accurate switching frequency. The UC3823A/B and UC3825A/B ICs utilize two pins for the sawtooth oscillator; one each for the timing resistor (Rt) and timing capacitor (Ct). The resistor programs the c:harging current to the timing capacitor via an internal current mirror with high accuracy. Maximum switch on-time is determined by the rising capacitor voltage whereas deadlime, the programmed switch off time is determined by the timing capacitors discharge.
Considerable improvement has been made to the accuracy of the oscillator discharge current. The previous generation of UC3823125 devices endured variations of plus or minus forty percent(+/- 400/o) over the full military temperature range and production tolerances. This new generation of UC3823A/B and UC3825A/B PWM controllers features a well controlled oscillator discharge current which is "trimmed' at wafer probe testing to +/- 1 milliamp. Oscillator initial accuracy (400 KHz nominal) has been tightened to 375 KHz minimum and 425 KHz maximum. Total variation over all line and temperature ranges is limited to 350 and 450 KHz. A new specification for 1 MHz accuracy has been added, demonstrating a plus or minus fifteen percent total frequency variation at high frequency.
CLOCK OUTPUT
The UC3823A,B and UC3825A,B controllers also feature a TIUCMOS compatible CLOCK output pin. Specified ampli-
tudes are 3.7volls in the high (off) state and 0.2volts during
its le>w state. Additionally, this pin is also used for programming of the leading edge blanking function. Notice that unlike their non A,B predecessors, these enhariced versions cannot be externally synchronized by an input to the clock pin. Synchronization is obtained by forcing a SYNC pulse across a resistor in series with the timing capacitor.
U-128
6 OU M TA ~~ · Maxinjum Deacjtlme/lowest Frequency ,
v - 11MA...-'\.~ _i ·A -ii v~i ·~:~ OUT~ Typlc;I Deadtlte~ominal Fre~~ency '
16MA~
OUT~
Minimum Deadtime/Highest Frequency Figure 7 - Frequency and Deadtime Variations \IS. Discharge Current Tolerances
-- ---------- -- ---- ---- -------- -------- --
:''
'
CONTROLLED DISCHARGE CURRENT VARIATIONS
·''''-- ---- ------------------------ -- --- ---- -·
Figure 8- Controlled Discharge Current
LEADING EDGE NOISE INlHE CURRENT SENSING CIRCUIT
One of the most difficult tasks with peak current mode con-
trol is sensing the inductor current. Instead, switch current is generally sensed by means of either a series resistor or current sense transformer. There is some difficulty with using this technique accurately, especially at light current levels. As the switch turns on, circuit parasitics in the power stage, output rectifier reverse recovery characteristics and high current gate drive pulses can create significant noise pulses on the leading edge of the current sense signal. Traditionally, this problem has been overcome by adding a small R-C noise filler between the current sense resistor and the PWM controllers current sense input. At low operating frequencies and high output current levels this RIC filtering technique wil generally deliver satisfadory results. However, at higher switching frequencies, and almost always at lighter load currents the leading edge spike amplitude can greatly , exceed the peak current sense signal.
9-290
APPLICATION NOTE
VCT A:UPPER
ANALOG)
THRESHOLD
__.,.
ntn~SYNC
__J[GITAL)
COMBINED
Ver
LOWER THRESHOLD
SYNC CIRCUIT
INPUT
CT
PWM
Rgure 9 - Synchronization
The leading edge current sense noise shown in figure 10 will cause a premature, false triggering of the pulse width modulator. Additionally, this will lead to instability of the converter by causing the voltage loop to oscillate at light loads. When the PWM is triggered by the noise spike instead of the true current signal - a smaller (minimum) pulse width is delivered to the main switch. The power supply's output voltage subsequenUy falls which causes the voltage amplifier to command for a higher inductor (switch) current. Eventually this continues until the amplitude is sufficient to rise above the leading edge noise spike.
J [
TO OUTPUT FILTER
~I
RseNSE
TO CURRENT SENSE
Figure 10- CurrentSensing Technique
U-128
Pulse widths too wide for proper operation are now delivered and the output voltage climbs until the voltage amplifier commands less current. This oscillatory process continues at a rate determined by several factors. Noteworthy is that this has nothing at all to do with the instability caused by inadequate slope compensation, or peakto-average current error. The cause is leading edge noise, and even optimal loop compensation cannot protect against this problem.
LEADING EDGE BLANKING
The RC filter shown in figure 10 can be tailored to work well over a limited range of applications and power levels. Another technique, known as Leading Edge Blanking (LEB) essentially blindfolds (blanks) the PWM comparator for a specific amount of time during the beginning of the cyde. The blanking duration is user programmable and should correspond to the width of the leading edge noise spike. This eliminates the need for filtering of the current sense signal in peak current mode controlled circuits.
ERROR VOLTAGE
1~7r-:-7r-~1'1--:i--...t---:"/11.-;>il
I SENSE
PWM OUTPUT
HIGH VOUT TYP --------------·------------- -·-----·--------------------------
LOW
Figure 11 - InstabilityCaused ByLeading Edge Noise Triggering
OSCILLATOR Ct
INTERNAL SYNC SIGNAL
MODIFIED CLOCK (WITH LEB)
LEADING EDGE BLANKING
UNBLANKED SWITH CURRENT
BLANKED SWITCH CURRENT
Figure 12- Leading Edge Blanking Operational Wavefonns
9-291
APPLICATION NOTE LEBIMPLEMENTATION
The focal point of any fixed frequency PWM controller is its clock. Used to accurately program the switching frequency and maximum duty cycle, the clock serves as the trigger source for the leading edge blanking circuitry. A digital rep-
resentation of the timing capacitor charge/discharge status
is developed by internal logic. This is made available at the PWMs CLOCK pin for external purposes. The UC3823A,B and UC3825A,B all use a high output to indicate the OFF period of the switching cycle, and a low to indicate the maximum ON time. These levels will be incorporated into the design of the leading edge blanking circuitry.
The clock output of the UC3823A,B and UC3825A,B .is pulled high during the oscillatordeadtime to approximately 4 volts. A capacitor added. to the CLOCK output pin programs the leading edge blanking duration. An internal comparator with an accurate threshold set at SO°lo of the peak clock amplitude has been added. The LEB programming capacitor is discharged by an internal 1OK ohm resistance to ground. The LEB interval is defined by the time required for the capacitance to discharge from 4 volts to the 60% threshold. Once the LEB capacitor discharges below this threshold, the PWM operates normally without any blanking. Programming should accommodate the worst case of leading edge noise. With no programming capacitor added, the ICs function similarly to their predecessors and provide no blanking.
5.1V REFERENCE
~--------------------------
U-128 Because of the leading edge blanking, the PWM outPuls will exhibit a minimum ON time in normal operation. The duration corresponds directly to that of the LEB programming, so a minimum duty cycle has also been established. Resolution between zero ck.lty cycle and this minimum duty cycle cannot be obtained - which should also be taken into account when programming the LEB circuitry.
zero duty cycle is a valid operating condition which can be achieved by one of two methods. The most obvious tech-
nique is to bias the error amplifier such that its output is driven below the PWM zero duty cycle threshold of 1.1 V. The
ICs error amplifier can easily accomplish this while sinking
current up to 1 mA; worst case. The second technique utilizes the current limiting feature (ILIM) at pin 9. An ILIM input held above the 1.2V (typ) FAULT threshold will force the PWM's on-time and duty cycle to zero. More details of the interface between the PWM and fault circuitry will be found in the following fault protection section.
Ct RAMP~
I
o .
n . INTERNAL · . ·
l--t----:..- SYNC __J
I
I
I·
I
l
. . ···...
. .
.
I '
I I
I
I
I ---~------ 100o/o
CLK/LEB ------- ----~--- :
60%
CLK/LEB
LEADING EDGE BLANKING
COMPARATOR
I
I
PWMOUT
' I 'I'
I
' I
I
LEB ____.n._____
INTERVAL
: :
I
I
I
I
I
o
I
0
Figure 14- Blanking Wavefonns
Figure 13" LEB Circuitry
LATCHED FAULT PROTECTION
While the previous generation of control ICs offered fault protection circuitry, they did not feature a fully latched shutdown after detecting a fault. The unlatched technique only
9-292
APPLICATION NOTE
discharges the soft start capacitor during the duration of the fault - a duration which can be very brief with a high speed controller. k3 a result, the duty cycle is not significantly reduced, and the IC continues delivering output pulses at the the switching frequency. Typically, the switching components can easily be dangerously overstressed while also dissipating a significant amount of power.
The new UC3823A,B and UC3825A,B controllers feature a latched fault protection circuit as shown in figure 15. Two comparators are used to offertwo stage protection - depending on the amplitude of the fault. The first comparator has a one volt threshold for cycle-by-cycle current limiting, In normal operation this terminates the immediate switch drive pulse but does not trigger the latching fault logic. One volt has been selected as the peak amplitude of the current sense signal for normal operation and slight overloads to accommodate transients.
The second comparator has a slightly higher threshold of 1.20 volts, indicative of a twenty percent overload or fault. When this comparator is tripped, the fault latch is turned on and the soft start capacitor begins discharging. The present output pulse had already been terminated by the one volt comparator circuity while the signal was rising to cross the 1.20volt level. The over- current latch insures that the PWM latch is held off for an extended period of time, approximately equal to the soft start time constant.
Once this overcurrent latch is set, a second "restart'' latch is triggered which insures the proper restart of the control logic. First, a current sink (typically 200 uA) is turned on by the restart latch output which overpowers the 9 uA charging current source and begins discharging the soft start capacitor. The capacitor voltage is monitored by a restart comparator, looking for a decay to the threshold level of 0.2 volts. Once this occurs, the restart comparator resets the overcurrent comparator which sequentially resets the restart latch.
The restart latch can only be set with the right set of conditions as shown in the block diagram. First, undervoltage lockout must be satisfied to insure proper operation during initial power-up. Secondly, the overcurrent (1 .2 V) comparator must be triggered, indicative of avalid fault. Last, and most important, is that a full soft start cycle must be completed before the restart latch can be retriggered. A fourth comparator insures that the soft start capacitor voltage has charged to a 5 volt threshold. This indicates that a complete discharge followed by a complete charge has occurred.
U-128
TO ERROR AMPLIFIER
9pA
~~LM~~~---l~~---<~~~,U-ll-SO-~-STA-ITT~~~
5V
COMPLETE
COMPARATOR
CURRENT LIMIT
Figure 15 - Latched Fault And Full Cycle Soft Start Protection Circuitry
FULL CYCLE/ CONTINUOUS FAULTS
During a fault, many designers prefer to reduce the repetition rate at which the switch is driven rather than to continue at the normal switching frequency. Often called "hiccup", this delayed restart will significantly reduce the overstress and power dissipated during abnormal conditions. Implementation of the latched fault technology results in significantly lower povver dissipation during a continuous fault or shorted output stage. Instead of delivering minimum duty cycle pulses at the oscillator frequency, the retry sequence occurs at a repetition rate approximately equal to the soft start period with a continuous fault.
In the worst case, two PWM outputs can occur in a time less than the soft start time constant, but this happens only once with a 'true" fault input(>1.2 V). For example, assume that the converter is in normal operation when a fault is detected. The first valid fault immediately turns off the output and triggers the latching overcurrent circuitry. Since the soft start capacitor was fully charged (above 5 volts), the '1ull soft start complete" comparator allows the overcurrent latch to set the restart latch. Discharge begins and continues until the restart complete comparator is tripped at a soft start capacitor voltage of 0.2 volts. The restart latch is reset, and the soft start capacitor begins charging.
Note that a well defined time is required between this instant and the time when the first output pulse can next occur. The capacitor begins at 0.2 volts and the error amplifier output is internally clamped to the soft start capacitor voltage. Back at the PWM comparator, however, there is a 1.25 volt offset on the ramp pin to facilitate zero duty cycle. Therefore, the soft start capacitor must charge from 0.2 volts to 1.25 volts before the PWM comparator is active.
9-293
APPLICATION NOTE
This provides a slight interval between the worst case of suc-
cessive output pulses into a shorted load. From this point on, the soft start capacitor must fully charge up to the five volt threshold of the "full soft start complete" comparator. Once in this mode, only one PWM output per soft start period can be obtained into a fault as shown in figure 16.
LEB AND FAULT DETECTION
U-128
The overcurrent (fault) threshold, however, has been centered at 1.2 volts instead of the 1.4 volt midpoint of the non A,B versions. The new specifications are 1.14 volts minimum to 1.26 volls maximum. Applications converting to the newer controllers may need to adjust the current sens.e resistor value accordingly. Typical propagation delay is unchanged at 50 ns typical, and 80 ns maximum.
The leading edge blanking circuitry is interfaced to also blank some of the fault detection circuitry. While numerous arrangements are possible, only one configuration offers a reasonable compromise between quick response and noise immunity. As demonstrated in figure 12, leading . edge blanking does inhibit the one volt, cycle-by-cycle current limit comparator during the programmed interval. However, the blanking does not disable the 1.2 volt overcurrent comparator and fault logic. This adaptation will accommodate a moderate amount of leading edge noise without having to significantly filter the current sense, and fault signals. Even if a moderate amount of filtering is required, the latched full cycle shutdown protection minimizes the power dissipation.
FAULT
HIGHER GAIN-BANDWIDTH ERROR AMPLIFIER
Many of the critical UC3823/25 error amplifier specifica" lions have been improved. The characteristics which significantly differ are: input offset voltage - reduced from 10 to 7 mV, unity gain bandwidth - increased from 5.5 MHz to 9 MHz, typical slew rate- reduced from 12 to 9 V/us. Notice that the minimum slew rate is unchanged at 6 V/us.
HIGH POWER OUTPUTS
The industry need for higher switching frequencies and improved efficiency has directly effected the design of the totem-pole output drivers. Many of the capacitive loads (MOSFETS) placed directly on the PWM outputs require high peak currents to obtain adequate switching transitions. The high speed UC3823A,B and UC3825A,B controllers feature peak current ratings of 2 amps, and are capable of slewing 15 volts in 35 nanoseconds into 1OOOpF. Separate collector supply (Ve) and power ground connections (PGND) help decouple the analog circuitry from the high power gate drive noise.
OUTPUT OFF :__________________ L_~___ j ____ ; __________ J__ J___ J_______ .
TYPICAL APPLICATION
Figure 16 - Full Cycle Soft Start- Operational Waveforms
TIGHTER FAULT THRESHOLDS
This latest generation of IC controllers utilizes a thin film resistor process which provides improved control of the tolerance. These resistors are used to generate accurate voltage thresholds by dividing down the IC's reference voltage internally. Both of the current limiting comparator thresholds have been tightened in the "N' and "B" versions of controllers. The cycle-by-cycle current limit threshold range has been tightened to +/- 5% from its previous +/10% specification. The new limits are 0.95V minimum, 1.05V maximum with the center remaining at the previous 1.0 volts.
The 1.5 MHz, 50 Watt push-pull converter detailed in Application Note U-110 was redesigned to accept the UC3825"B" device. The basic power stage remained similar while an emphasis was placed on control circuit improvements. These enhancements included Leading Edge Blanking of the current sense signal and Restart Delay following a fault. Also, a current sense transformer was installed which not only reduced losses but allowed amplification of the current sense signal to approximately 2.5 volts, thus enhancing noise immunity.
Improvements to the power section of the converter indude the use of larger MOSFETS (IRF640's) and the addition of a bootstrap winding for the auxiliary bias supply. The startup resistor from the input supply was increased since the UC3825"B" device features a wide UVLO hysterisis of six volts.
9-294
APPLICATION NOTE
+Vin
U-128
47pF 3K
15
3
14
UC3825B
4
13
12
11
--+--11--+-l 8
C5 2.2nF
R2 2K7
R21 240
C17
R24 51il 1W
I/OUT
-Vin
PGNO
Figure 17 UC3825B Controlled 1.5 MHz Push Pull Converter
CONVERTER PERFORMANCE
The redesigned converter exhibited similar line, load and transient response to the original converter, which was excellent due to the high conversion frequency. A significant improvement~ made in the short circuit performance by comparison. While operating into a continuous short circuited output, the UC3825"B" controlled version reduced the converter input power (and dissipation) to approximately one-hundredth of the original design. Featuring the programmable Restart Delay circuitry, the redesigned 50 Watt converter draws only one-quarter of a Watt (1/4 W) of input power with a shorted circuited output.
SUMMARY
This new generation of UC3823A,B and UC3825A,B PWM controllers features a multitude of performance advan-
tages over ils predecessors. Higher precision, increased pro-
tection and programmable new functions are just a few of the benefits obtainable with these enhanced versions of PWMs. And as the level of sophistication in todays power supplies increases, so too must that of its components -
especially control ICs. Containing an expanded list of inte-
grated features, this new era ot enhanced UC3823A,B and UC3825A,B controllers overcomes the challenges of the power supply industry for higher levels of power, protection and performance.
ADDITIONAL INFORMATION AND REFERENCES
1. New Pulse Width Modulator Chip Controls 1 MHz Switchers; UNITRODEApplication Note# U-107
2. 1.5 MegaHertz Current Mode IC Controlled 50 Watt Power Supply; UNITRODE IC Databook, Application Note# U-110
3. "Practical Considerations in Current Mode Power Supplies"; UNITRODE IC Databook, Application Note # U-111
UNITROOE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD.· MERRIMACK, NH 03054 TEL. 603-424-2410· FAX603-424·3460
9-295
n n L'.=::J INTEGRATED CIRCUITS
-UNITROCJE
APPLICATION NOTE
UC3907 LOAD SHARE IC SIMPLIFIES PARALLEL POWER SUPPLY DESIGN
U-129
MARK JORDAN SENIOR DESIGN ENGINEER
INTRODUCTION
Manypowersupplymanufacturers have found it economically feasible to make standardmodularpowersupplies which are easilyparalleled for highercurrent applications. If special provisions are not made to equally distribute the load currentamong the paralleledsupplies, then one ormore units will hog the loadcurrent leaving the otherunits essentiallyidle. This results in greater thermal stresses on specific units and a reduction in the system reliability. For example, reliability predictions will indicate that a component operating at 50 degrees above ambient will have one-sixth the lifetime of the same component operating at25 degrees above ambient[1].
This paper will examine methods for load sharing presently being implemented discretely and then cover Unitrode's single chip solution, the UC3907 Load Share Controller, in several parallel power applications.
SYSTEM REQUIREMENTS
The basic requirements of a power supply system consisting of a number of sources paralleled to increase the total load current are:
· Maintain a regulated output voltage under variations in line or load.
· Control the output current of each supply so they share the total load current equally.
To maximize reliability of the system, there are the following features:
· Achieve redundancy, so that a failure of any one supply can be tolerated as long as there is sufficient current capacity available from the remaining power units.
· Implement a load sharing method without any external control system.
In addition, these are the following desirable features:
· To have a common, low bandwidth share bus interconnecting all power units.
· Achieve good load sharing transient response. · The ability to margin the system output voltage with one
control.
In other words, the combination of power supplies behave like one large supply with equal stress on each of the units. Also, reliability can be optimized by taking advantage of load sharing to incorporate modular redundancy.
LOAD SHARING TECHNIQUES
There are a number of schemes to achieve load sharing. Five approaches are discussed here, with an attempt made to investigate their application, highlighting features and concerns.
Tl-=IE DROOP METHOD
The simplest method to load sharing is referred to as the droop method. It is an open loop technique which programs the output impedance of the power supplies to obtain load sharing. This method exhibits very poor current sharing at low currents and improves at higher currents, but can still have large current imbalances between supplies. An example of this method is shown in Fig 1 where as the individual supply current increases, the feedback voltage will decrease. This will allow other supplies to distribute more current. The programmed output impedance is given by:
Rout= 0.01 Rs N
The disadvantages to the droop method are: degradation of load regulation, each module must be individually tweaked to achieve good current sharing, and difficulty in current sharing between parallel modules with different power ratings.
9-296
APPLICATION NOTE
+
Rs
Fig 1 - The Droop method programs the output impedance of the power supplies to achieve load sharing. It is a simple open loop method, but is not accurate.
DEDICATED MASTER Current mode supplies can accommodate several configurations to achieve a form of load sharing. One approach is to select a master module to perform the voltage control and force the remaining modules (slaves) to act as current sources, as shown in Fig. 2. This technique is facilitated with current mode control, since the error voltage is proportional to load current. If the units were similar in design then a given error voltage on the output of the voltage, or error amplifier will force all units to source the same load current. This technique achieves load sharing but does not achieve redundancy, since if the master fails, the entire system becomes disabled. Another concern with this technique is that the high bandwidth voltage loop is being bussed around the system and is prone to noise pick-up.
U-129
AUTOMATIC CURRENT SHARING - AVERAGE CURRENT METHOD
For Automatic current sharing no external controller is required and a single share bus interconnects all the supplies. This requires an adjustment amplifier that compares a current signal from the share bus to the individual units current, and adjusts the reference of the voltage amp until equal load current distribution is achieved.
The average Current method is a patented technique where each power module's current monitor drives a common share bus via a resistor, as shown in Fig 3. The adjust amplifier will sense if there is a differential across the resistor, equating to a load current imbalance, and adjusts the reference accordingly. The node where all resistors connect is a representation of the average load current contribution. While this scheme performs accurate current sharing, it can result in specific application problems. An example is when a supply runs into current limit, causing the share bus to be loaded down and the output voltage to regulate
to the lower adjust limit. A similar failure mode will exist if the
share bus is shorted or if any unit on the share bus is inoperative.
To l ood
Vbuo =Average all Vde
'-......:'
~----".;v-...--.--; ShareBus
~__...,,...,>-------~:--·-:
~bad(
v..1
_ __ . . . _ _.... ,>--+,-
_ ____,__ _..._,
.....
:_ ------ -----~'~~~~~~-j
. i ·:-------M--as-t-er-U--n-it·:'
·---------~~·-_,
-----------'
Ve
~ ---------- --~!!8-~'li~~ - ~
Fig2-A dedicatedMasterapproach with currentmode supplies will facilitate current sharing but does not achieve redundancy.
EXTERNAL CONTROLLER
Another method is to use an external controller to perform the load sharing. This is achieved by comparing all load sharing signals from the individual power units and adjust the corresponding feedback signal to balance the load currents. This system does perform well but requires an additional controller and multiple connections between the controller and each supply.
Fig. 3 - The average current method compares the individual load currents to the average load current.
AUTOMATIC CURRENT SHARING - HIGHEST CURRENT METHOD
This technique for automatic current sharing shown in Fig 4 compares the highest current module to each individual
current, and adjusts the reference voltage accordingly to cor-
rect the imbalance of load current. This technique is similar to the average current method except that the resistor is replaced with a diode, allowing only one unit to communicate on the share bus. This method provides for excellent sharing among the slaves with an error in the master's load current contribution because of the diode.
The UC3907 Load Share Regulator has improved on this method by replacing the diode with a unidirectional buffer to reduce the master's error. An inoperative or insufficient capacity supply will not effect the sharing of the operational units. A shorted share bus will disable the reference adjustment section used for load sharing, making the units operate as stand alone.
9-297
APPLICATION NOTE
U-129
USING THE UC3907 - LOAD SHARE REGULATOR IC
Voltage Feedback
To load
= VOOs Highest of all Vds
"--1
f-'-'-..--f--.,----1 Share Bus
Fig. 4 - The highest current method compares the individual load currents to that of the highest. This method has several advantages over the average currentmethod ofloadsharing. The
UC3907has implementedandimproved version ofthis technique.
A review of the current sharing technique used on the UC3907 and operating principles will help the reader to understand the application examples that follow and to use the IC in other examples.
A generic load share system with the basic bus connections required to perform accurate output voltage control and load sharing is shown in Fig 5. The output voltage is sensed with a fully differential, high-impedance voltage amplifier. Each individual power supply current is sensed with a differential current amplifier, and is used for the load share portion of the circuit. The share bus signal interconnecting all the paralleled modules is a low-impedance, noise insensitive line. The connection diagram is shown in FIG 6. The following discussion of the voltage and current sharing loops should help the reader understand the operation and features of the IC.
Current Share Bus
Positive Sense Positive Power
Control
Control
Control
'-------it t ~-----.! RSENSE
RsENsE
RsENSE ~---~·
Negative Power Negative Sense
Fig. 5 - System connections for modules with independent load sharing.
Input Line
Fig. 6 - The UC3907 will control output voltage and equally distribute load current among the power modules. 9-298
APPLICATION NOTE
THE VOLTAGE LOOP
THE VOLTAGE AMP
This Amplifier is the feedback control gain stage for the power modules output voltage regulation, and the overall voltage loop compensation will normally be applied around this amplifier. The output swing is limited to 2 Volts to improve ~e large sig~al respons~ of the system. The voltage amplifier accomplishes the high impedance positive sensing, and the ground amp, the high impedance negative sensing.
THE GROUND AMP
This amplifier is a unity gain buffer with a 0.250V offset. The offset allows the amplifier negative headroom to return all control bias and operating currents while maintaining a high impedance negative sense input (pin 4), where this input is referred to as ''true" ground. The output of this amplifier is referred to as Artificial Ground. The 0.250V offset is
U-129
added to the 1. 750V bandgap reference to obtain the 2.00V reference , as seen by the voltage amp, and is trimmed to +/-1.25%.
The ground return (pin 5) should be the most negative voltage available and can range from zero to 5V below the negative sense input. All the IC's current will return through the ground return pin.
THE DRIVE AMP
This amplifier is an inverting amplifier with a gain of -2.5, which couples the feedback signal to the power controller. The Current setting resistor Rset helps to establish the forward transfer function of the control loop and the maximum drive current. The polarity of the drive amp stage is such that an increasing voltage at the plus sense input (pin 11 ), will increase the opto-couplers current, thereby reducing the primary side PWM's duty cycle. This will insure proper startup since there is no energy on the secondary side during initialization of the power system.
'"-ill~----------+---~
From Power Supply
'"-ill~-------"'""'$~-....J---___J
Rg. 7 - The UC3907 Voltage Loop achieves high impedance differential sensing along with optical coupler driving capability.
THE CURRENT LOOP
THE CURRENT AMP AND BUFFER AMP
The current sharing portion of the IC utilizes the current amp, the buffer amp, and the adjust amp as shown in Fig. 8. The Output of the current amp is an analog representation of individual load current, where the output voltage is given by: Vca=20*Rs*lout. The current amp output feeds an input of a unidirectional buffer which drives the current ~hare bus. Since the buffer amp only sources current, it insures that the module with the highest load current will be the master, or communicator to all other modules and drives the bus through a low-impedance. All other buffer
amplifiers will be inactive with each exhibiting a 1OK ohm load impedance to ground.
THE ADJUST AMP
The adjust amplifier will compare its own load current with that of the highest current module, and force a command to adjustthe individual modules reference voltage, (as seen by the voltage amp) to maintain equal current sharing. It is a transconductance type amplifier in order that its bandwidth may be limited, and noise kept out of the reference adjust circuitry, with a simple capacitor to artificial ground. The ground referenced compensation will act similar to that of integral compensation, but without the non-inverting signal feedthrough problems, thereby filtering both inputs from
9-299
APPLICATION NOTE
unwanted noise. The adjust amplifier has a built in 50 millivolt offset on its inverting input, which forces the unit acting as a master to have a low output resulting in a zero adjust command. While the 50mv offset represents an error in current sharing, the gain of the current amplifier reduces it to 2.5 millivolts across the sense resistor. This results in all slave modules sharing equally and the master module running a few percent higher. The offset also provides some immunity from cycling, or fighting for master position due to low frequency noise.
STATUS INDICATE
U-129
The status indicate pin is designed to indicate which unit is acting as the master. Its open collector output is activated when the adjust amp output is in the low state. In a case of an overcurrent fault with one of the many paralleled units, this pin will indicate the unit with the highest current which will help diagnose the faulted module. A zero current or low current fault is transparent to the other supplies' and has no effect on voltage regulation and current sharing.
In~>------------..---~
From Power Supply
-- RS +
ln~:>-----.....---'t-v'VV'---.--t---~
+s.n..
-s.n..
To Voltage Sensing Circuitry
Fig. 8 - Current sharing is achieved with the UC3907 by comparing the individual module's current to that of the highest current
module. The necessary adjust command increases the voltage amp reference to accomplish equal load sharing.
START-UP FOR A PARALLEL POWER SYSTEM
Start-up conditions need to be considered in a parallel power supply architecture. A start-up timing example of four 5V power modules in parallel is shown in Fig. 9. Once the primary power is applied, the power stage will be requesting maximum duty cycle until the individual units feed back a signal to regulate the output voltage. Attime t1, supply #1 has become the master due to its higher reference voltage. This forces the output voltage to regulate above the other units. The other units will feedback a zero duty cycle signal to the power stage and remain idle. At this point the master unit is supplying all the supply current, and outputting the corresponding current signal on the share bus. The other units' adjust amplifiers sense the difference between their individual load currents and the master's, and start to slew up the adjust amp output to increase their references. At the same time the master's adjust amplifier output remains clamped below the adjust threshold having no effect on its original reference. At time t2 the other three adjust amps have exceeded the adjust threshold and have started to effect the reference as seen by the voltage amp.
At time t3 the unit with the closest reference to the master, supply #2, has reached the point where its references is essentially equal to the master's and the load current
becomes equally distributed between the two. The other two
modules, #3 and #4, are still adjusting their references and are not yet contributing to the load current. At time t4 the 3rd unit has reached the desired reference and the load current has been equally split between the three, and at time t5 the final unit has completed its reference adjustment, thereby completing the load sharing. If it is necessary to have the units come up sharing, then a soft-start scheme will need to be implemented on the primary side modulator which needs to be much slower than the adjust time. The total adjust time from t1 to t5 for this example is given by:
Cl Va t= - -
1
where Cl = adjust amp compensation Va = adjust amp swing I =Adjust amp max current - 220ua
9-300
APPLICATION NOTE
Cl is chosen from the desired bandwidth
gm Cl=
27tF
where typ gm = 3mS and F =Adjust amp bandwidth.
If the required adjust amp bandwidth were 500 Hz, then Cl will be 1uF. The adjust amp outputfor the lowest reference will adjust to a voltage calculated as follows:
Vadj = (VREFmax-VREFminl 17.5+1 = (30mv 17.5) + 1 = 1.53
The adjust amp must slew from approximately 0.7V to 1.53V at a slew rate of 220mV/ms which equates to a complete sharing delay time of 3.8 ms.
U-129
5.025V Vo<rt
Vout/~~ !.::+:==+.=,::r-1-1---
Load Currents
.. IF 11--1 50% #3 1~ 13-3_%_ _ _ 2s%
Adjust Amp Oot UC1907
. .~~=i==== 1.53V
~
11..3H5SVV
iV ---- ~- ---- ---- ---------------~;~~hold
J_
T1
T2 T3 T4 TS
Fig, 9- Start-up timing ofa four module power system using the UC3907 (without soft-start).
THE VOLTAGE AND SHARE LOOP DESIGN
A load sharing system is composed of two loops, the voltage loop and the current share loop. As in conventional designs, the voltage loop regulates the output voltage and is the faster responding loop. The current sharing loop is a lower bandwidth loop to eliminate noise pick-up on the share line, and should be low enough in bandwidth to eliminate interactions with the voltage loop.
A complete loop diagram is shown in Fig. 10. The voltage amp transfer function is designed to optimize the voltage loop response, which is determined by the modulator topology, filters, and other gain functions in the loop. We will work through each gain block for a flyback converter example using the UC3907, and from this the user should be able to expand the design to any topology.
C3 R3
C2 C1
R2
Vee
+V
Primary Secondary
Optical : Coupler :
R1 RB
20K Voltage Amplifier
Drive Amplifier
Range= 2.00V to 2. 1OV
UC3907
Vo<rt
Fig. 1O- The UC3907 can be easily implemented to perform voltage control, and optical coupler drive for isolated applications.
9-301
APPLICATION NOTE
Compensated as shown, the voltage amp response is given by:
UGF=
Pole=Origin
UGF = Unity Gain Frequency.
Pole2=
1
21tR1Ca
U-129
The CTR spread can vary from 0.4 to 2 on a given device type, but many manufacturers can sort them out to a+/- 30% tolerance. The CTR is also a function of the driving cur-
rent and therefore introduces a non-linearity in the feed-
back gain.
The control to output gain of the modulator for various topo~ is referenced in the Unitrode powersupply design seminar book. For example, the control to output gain for the discontinuous flyback with current mode control is:
zero 1 =
1
21tR2C1
1 zero2= - - - - -
~R1 +R3>Ca
The drive amp will convert the output of the voltage amp to an error current to be applied to the opto coupler. The current is given by:
Wherewz = Rec
wp = Roe
(1.25 - Ve)2.5 + 1.25
Iopto=
Rset
where Ve = output of the voltage amp - error voltage and the small signal gain is:
= -2.5 Rset
The control voltage for the UC3844 pulse width modulator is given by:
"6)(... ...,) V0 = (2.5- 'optoCTR
~
+2.5
where CTR is the currenttransfer ratio of the opto coupler. and the small signal gain is given by:
Re = esr of C's in parallel RO= Load resistance C= Total output Capacitance L= Primary inductance F= Switching frequency
The total voltage loop gain is given by:
~$)=~·)( ::j( ::j
where A(s) is the voltage amp transfer function
To bandwidth limit the share loop, the adjust amplifier is compensated where the unity gain frequency of the adjust amp is given by : ·
gm F=
21tC1 where typical gm = 3mS.
- Ve =-CTRAf> (. R8 )
lopto
R5+R7
AN OFF-LINE LOAD SHARE APPLICATION
therefore the UC3907 error voltage to PWM control voltage gain is given by:
An off-line power supply application utilizing the UC3907 Load Share Controller is shown in Fig. 11 fora flyback regulator. The UC3844 is the modulator and i1s switching fre-
~ 1~ j _:_ - CTR Rs Ra
2.5
vv e
Ra+ R1 Rset
quency is determined by Fs = 1.72/(Rt Ct). The resistor R5 will sense the primary inductor current, where the maximum peak current for the UC3844 is given by ISmax= 1.0V/R5. Startup is achieved with R1 and C5 until boot-
strap winding W2 can feedback to power the UC3844. The
snubber network D3, C4, and R2 prevents tum-off voltage
spikes from exceedng the FET breakdown voltage. The prt.
-iary soft-start circuit is comprised of Q1 , R9 and C1 O.
9-302
APPLICATION NOTE
Note that the resistor Rset and adjust compensation is connected to artificial ground (pin 6). Artificial ground is a replica of the "true" ground voltage on pin 4, negative sense, plus a 0.250V level shift. This allows a low impedance point for ground referenced elements to connect.
U-129
A master indicator lamp is included in the design so that the unit supplying the most load current and determining the output regulating voltage can be detected. There are many useful applications for this pin as in supply voltage margining or determination of a faulted supply which is supplying an excess voltage/current.
170V
OS
C3 R2 W1
03
D2
-+
"'
AB
r·
:' a= :'
' - - - - - - - - - - - - - ' ' ' 1' ----'-~·----~
Rg. 11 - The UC3907 in an off-line isolated application.
NON-ISOLATED CONVERTER APPLICATIONS
There are applications were non-isolated DC to DC converters are paralleled to make a power system. Fig. 12 shows a step down, or buck, regulator utilizing the UC3524A voltage mode PWM and the UC3907 Load share IC. For non-isolated parallel power supply applications the current sensing must be done on the high side. The reason for this is that if the sensing was performed on the low side where the power supply inputs and outputs are common, then all the current sense resistors will end up in parallel, defeating the indMdual sensing and load sharing. The only limitation to high side current sensing in a non-isolated application is that the current amplifier of the UC3907 has a common mode range of OV to Vin -2V, therefore a form of level shifting oraverage current sensing would be required.
Since the opto-coupler is not required, an inversion has been eliminated which the driving scheme must accommodate for. The lsetvoltage is a gained up inverted error voltage from the UC3907 voltage amp. The UC3524A error amp is set up as an inverter and cancels out the drive amp
inversion leaving the error voltage of the UC3907 to be
transposed to the UC3524A in proper phase. The iset voltage will swing from Ov to 3.8V min. Current limiting is achieved by taking the current amp output signal from the UC3907 and feeding it in to the UC3524A current limit amplifier, where the current limit is given by:
20Rsense
9-303
APPLICATION NOTE
U-129
R13
Fig. 12- The UC3907 in a non-isolated DC to DC converter application.
LINEAR REGULATOR EXAMPLE
A simple linear regulator with load sharing using the UC3907 IC and a few external components is shown in Fig. 13. The phasing of the opto drive pin facilitates darlington drive, and supply current limiting is achieved by Q3, C1, R11, and R12 with the current limit given by:
Vin 35V to (Vout + 2V)
R1
VBEQ3 ( 1+ -A11-) R12
lei= 20Rsense
+ Asense
C7
R1
RB RO
1----- To Other Moc!Ues
Fig. 13 - With a few external components the UC3907 can make a simple linear regulator with load shar'ng.
9-304
APPLICATION NOTE
EXTERNAL LOAD SHARING
The UC3907 can be easily incorporated outside the power module to achieve load sharing, as shown in Fig 14. The load sharing loop is similar to previous examples, but instead of adjusting the internal reference of the UC3907, this technique adjusts the(+) sense line of the power module to
U-129
force equal current sharing. The maximum adjust voltage is given by:
LOAD SHARING CAN BE EXTERNALLY ADDED TO EXISTING POWER MODULES
-- Power(+)
Modular
AC Power
IN
Supp~
(+) Sense
Power
(-)
(-)
Sense
R1 40.20
LOAD
!a to 5ma
Fig. 14 - The power supplies remote sense inputs are used to facilitate load sharing.
REFERENCES:
1. F.N. Sinnadurai "Handbook of Microelectronics Packaging and Interconnection Technologies" Electrochemical Publications Limited 1985.
2. Walter J. Hirschberg "Current Sharing of Parallel Power Supplies" The power electronics design conference Oct1985.
3. Bob Mammano "Isolating the Control Loop" Unitrode power Supply design seminar, SEM-7001990.
4. Kenneth T. Small "Single Wire Current Share Paralleling of Power Supplies" US Patent 4, 717 ,833 Jan 1988.
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD.· MERRIMACK, NH 03054 TEL. 603-424-2410 · FAX 603-424-3460
9-305
n n C::::J INTEGRATED CIRCUITS
-UNITRODE APPLICATION NOTE
DEDICATED ICs SIMPLIFY BRUSHLESS DC SERVO AMPLIFIER DESIGN
John A. O'Connor
U-130
INTRODUCTION
Brushless DC motors have gained considerable commercial success in high end four quadrant servo systems, as well as in less demanding, one and two quadrant requirements. Cost sensitive four quadrant applications thus far have not fared as well. Designs which meet cost goals often suffer from poor linearity, and cumbersome protection circuits to assure reliable operation in all four quadrants. Better performance entails more complex circuitry and the resulting additional components quickly increase size and cost. Part of the design challenge results from the lack of control !Cs tailored to tour quadrant applications. The other major obstacle has been implementing a reliable and cost effective high-side switch drive. With recently introduced integrated circuits in both areas, it is nowpossible to design a rugged, low cost, four quadrant brushless DC servo amplifier with relatively low component count and cost.
SERVO AMPLIFIER REQUIREMENTS
First, let's quickly review general servo amplifier requirements. Figure 1 displays motor speed versus torque, depicting four possible modes of operation. While a system may be considered four quadrant by simply having the ability to operate reliably in all four modes, a servo system generally requires controlled operation in
VELOCITY
cw
II
I
C C W - - - - - - TOcRwQUE
III IV
ccw
Figure 1- Four Quadrants of Operation all four modes. In addition, a smooth, linear transition between quadrants is essential for high accuracy position and velocity control. The major performance differences between brushless DC servo amplifiers are
related to accuracy, bandwidth, and quadrant transition linearity.
Most simple brush less DC amplifiers provide two quadrant control, since even the simplest output stages (typically 3 phase bridge) allow rotation reversal. Note that this is operation in quadrants one and three where torque and rotation are in the same direction. This differs from brush motor terminology where two quadrant control normally implies unidirectional rotation with torque control in either direction. Although limited to a single rotation direction, bidirectional torque allows servo velocity control, with rapid, controlled acceleration and deceleration. These characteristics are well suited to numerous applications such as spindle and conveyer drives. With the two quadrant brushless DC amplifier, there are no provisions other than friction to decelerate the load, limiting the system to less demanding applications. Attempting to operate in quadrants two and fourwill result in extremely nonlinear behavior, and under many circumstances, severe damage to the output stage will follow. This occurs because the two quadrant brushless DC amplifier is unable to completely control current during torque reversal.
TWO QUADRANT VERSUS FOUR QUADRANT CONTROL
Figure 2 shows a three phase bridge output stage for driving a brushless DC motor. Current flow is shown for two quadrant control when operation is in quadrants one or three. The switches commutate based on the motor's
9-306
APPLICATION NOTE
CURRENT SENSE
Figure 2 - Two Quadrant Chopping
111 I · llEMf. Vo1ooe. VSAT
OFF
luOTDR
'
+E
CURRENT SENSE
Figure 3 - Two Quadrant Reversal +E
CURRENT SENSE
Rgure 4 - Four Quadrant Reversal
U-130 rotor position, typically using Hall effect sensors for position feedback. Current is controlled by pulse width modulating (PWM) the lower switches. Figure 3 shows current flow if the direction of torque were reversed. The upper switch essentially shorts the motor's back EMF (BEMF), causing current to quickly decay and reverse direction. The current then rises to a value limited only.by the motor and drive impedance, yet is undetected by supply or ground sense resistors. As the motor speed rises, its BEMF proportionally increases, quickly escalating the potential circulating current. Even if the output stage is built rugged enough to withstand this abuse, the high uncontrolled current causes high uncontrolled torque, making this technique unsuitable for most servo control applications.
By pulse width modulating the upper switches along with the lower switches, uncontrolled circulating currents are avoided. With both upper and lower switches off during during the PWM off time, motor current will always decay as shown in figure 4. Additionally, motor current always flows through the ground sense resistor, allowing easy detection for feedback.The remainder of this article will feature this mode of control, as it is well suited for a variety of demanding requirements. It should be noted however, that a penalty in the form of reduced efficiency must be paid for the improvement in control characteristics. With two switches operating at the PWM frequency, as opposed to one with two quadrant control, switching losses are nearly doubled. Ripple current is also increased which results in greater motor core loss. Although this is a small price to pay under most circumstances, extremely demanding applications may require switching between two and four quadrant operation for optimum efficiency and control.
FOUR QUADRANT CONTROLLER REQUIREMENTS
In addition to switching both upper and lower transistors, a few supplementary functions are required from the control circuit for reliable four quadrant operation. With two quadrant switching, there is inherent dead time between conduction of opposing upper and lower switches, making cross conduction virtually impossible. Four quadrant control immediately reverses the state of opposing switches at torque reversal, thus requiring a delay between turning the conducting device off and the opposing device on to avoid simultaneous conduction and possible output stage damage.
When torque is reversed, energy stored in the rotating load is transferred back to the power supply, quickly charging the bus storage capacitor. A clamp circuit is
9-307
APPLICATION NOTE typically used to dissipate the energy and limit the maximum bus voltage. As a second line of defense, an over-voltage comparator is often employed to disable the output if the bus voltage exceeds the clamp voltage by more than a few vofts.
U-130 CURRENT LOOP CONTROL TECHNIQUE
A transconductance amplifier is normally used for brushless DC servo applications, providing direct control of motor torque. Average current feedback is usually employed rather than the more familiar peak current
UC3625
5VOLT ,___ ___, 2 VREF REFERENCE PWM CLK DIR COAST CHOP QUAD
DECODER
CROSS CONDUCTION PROTECTION
LATCHES
BRAKE +5V
Figure 5 - U.C3625 Block biagram
9-308
APPLICATION NOTE control for several reasons. Peak current control is subject to subharmonic oscillation at the switching frequency for duty cycles above 50%. This condition is easily circumvented in power supply applications by summing an appropriately scaled ramp signal derived from the PWM oscillator with the current sense signal. This technique is commonly refered to as slope compensation. It can also be shown [3] that for a given inductor current decay rate, which is esentially fixed in a power supply application, there is an optimal compensation level which will produce an output current independant of duty cycle. Unfortunately, the inductor current decay rate in a four quadrant motor control system varies with both speed and supply voltage, making an optimal slope compensation circuit fairly complex. Simpler circuits which provide over compensation assure stability but will degrade accuracy. Furthermore, severe gain degradation occurs when inductor current becomes discontinuous regardless of slope compensation, causing large nonlinearity at light load. This effect can be particularly troublesome for a position control servo. Average current feedback avoids these problems, and is therefore the prefered current control technique for servo applications.
UC3625 BRUSHLESS DC CONTROLLER
Figure 5 shows the UC3625 block diagram. Designed specifically for four quadrant operation, it minimizes the external circuitry required to implement a brushless DC servo amplifier. Flexible architecture and supplementary features make the UC3625 well suited to less demanding applications as well. The UC3625 is described in detail in references [4] and [?], however a few features critical for reliable four quadrant operation should be noted.
Cross conduction protection latches eliminate the possibility of simultaneous conduction of upper and lower switches due to driver and switch turn-off delays. Additional analog delay circuits normally associated with this function are eliminated allowing direct switch interface and reduced component count. An absolute value buffer following the current sense amplifier provides an average winding current signal suitable for feedback as well as protection. An over-voltage comparator disables the outputs if the bus voltage becomes excessive.
Although not absolutely necessary for four quadrant systems, a few additional features enhance two quadrant operation and simplify implementation of switched two I tour quadrant control tor optimized systems. A direction latch with analog speed input prevents reversal until an acceptably low speed is reached, preventing
U-130 output stage damage. Two or tour quadrant switching can be selected during operation with the Quad Select input. A brake input provides current limited dynamic braking, suitable tor applications which require rapid deceleration, but do not need tight servo control.
A SIMPLE BRUSHLESS DC SERVO AMPLIFIER
To demonstrate the relative simplicity with which a
brushless DC servo amplifier can be implemented, a 6 amp, off-line 115 VAC amplifier was designed and constructed. Note that current and voltage rather than horsepower are specified. Although theoretically capable of in excess of one horsepower, simultaneous high speed and torque are typically not required in servo applications, reducing the actual output power, and the corresponding power supply requirement. Average current feedback is employed, providing good bandwidth and power supply rejection, thus making the amplifier suitable for many demanding requirements. A complete
amplifier schematic is shown in figure 6.
A high performance brushless servo motor from MFM Technology, Inc. was used to evaluate the amplifier. While most of the design is independent of motor parameters, several functions should be optimized for a particular motor and operating conditions. The motor used has the following electrical specifications:
Model M -178
Kr
RM LM Poles
79 oz.in./Amp 1.3 ohms 5.5 mH 18
OUTPUT STAGE DESIGN
Having selected a four quadrant control strategy, we proceed to the output stage design, and work back to the controller. High voltage MOSFETs are well suited to this power level, however IGBTs may also be incorporated. MOSFETs were selected to minimize size and complexity, since the body diodes can be used tor the flyback rectifiers. Unfortunately, this places greater demands on the MOSFET, and increases the device dissipation. The MOSFETs body diode is typically slower and stores more charge than a discrete high speed rectifier, which necessitates a slower turn-on and a corresponding increase in switching losses. These losses are partially offsetby choosing a MOSFET with sufficiently low conduction losses which offers the secondary benefits of greater peak current capability and reduced thermal
9-309
APPLICATION NOTE
UC3724 DRIVE TRANSMITIER
m ··.·· IUU~n~n~UmUL r-__1_so_LA_TU_EC_3D7_G2A5_r_E_D_RJ_VE_R_~ ...
~~MM.0 11°_. ......:.=-d-1---'~--+_J ...
U-130
...
Figure 7 - UC3724/UC3725 Isolated MOSFET Driver
resistance. APT4030BN MOSFETs were selected for the output stage to handle the 6 amp load currents while providing good supply voltage transient immunity. Rated at 400 volts and 0.30 ohms, they allow high efficiency operation and have sufficient breakdown voltage for reliable off-line operation.
While the lower three FETs require simple ground refer-
enced drive, and are easily driven directly from the
UC3625, the design of the drive circuitforthe upper three
FETs has traditionally been challenging. Discrete imple-
mentation of the required power supply and signal trans-
mission is often bulky and expensive. In an effort to
reduce size opening the
and cost, critical door to potential
rfuenliacbtioilintysparroeboleftmens.oSmpeicttiefdi~
cally designed for high-side MOSFET drive in motor
control systems, the UC3724 I UC3725 IC pair shown in
figure 7, offers a compact, low cost solution. A high
frequency carrier transmits both power and signal across
a single pulse transformer, eliminating separate DC/DC
c~nverters, charge pump circuits, and opto-couplers.
Signal and power transmission function down to DC
imposing no duty cycle or on-time limitations typical of
commonly used charge pump techniques. Under-volt-
~ge lockout, gate voltage clamp, and over current protec-
tion assure reliable operation.
Design of the upper driver is a straight forward procedure, and is described in detail in reference [5]. For this application, the driver is designed with the following specifications:
500 V minimum isolation 300 kHz carrier frequency 10 Amp over-current fault 10 ms over-current off time
The pulse transformer uses a 1/2 inch O.D. toroid core (Philips 204T250-3E2A) with a 15 turn primary and 17 turn secondary. For high voltage isolation, Teflon insulated wire is used for both primary and secondary.
T? provide rapid turn-off for minimal switching losses, with slower turn-on for di/dt control, a resistor/resistordiode network is used in place of a single gate resistor. Although present generation MOSFETs can reliably commutate current from an opposing FETs body diode at high di/dt, the resulting high peak current and diode snap limit practical circuits to a more moderate rate. This increases dissipation, but significantly eases RFI filtering and shielding, as well as relaxing layout constraints. Additionally, a low impedance is maintained in the off state while turn-on dv/dt is decreased, dramatically reducing the tendency for dv/dt induced turn on. The same gate network is used for both upper and lower MOSFETs.
A sense resistor in series with the bridge ground return provides a current signal for both feedback and current limiting. This resistor, as well as the upper driver current sense resistors should be non-inductive to minimize ringing from high di/dt. Any inductance in the power circuit represents potential problems in the form of additional voltage stress and ringing, as well as increasing switching times. While impossible to eliminate, careful
9-311
APPLICATION NOTE layout and bypassing will minimize these effects. The output stage should be as compact as heat sinking will allow, with wide, short traces carrying all pulsed currents. Each half-bridge should be separately bypassed with a low ESR/ESL capacitor, decoupling itfrom the rest of the circuit. Some layouts will allow the input filter capacitor to be split into three smaller values, and serve double duty as the half-bridge bypass capacitors.
U-130 !SENSE 1 5 lsENSE 2
CONTROLLER SETUP
DIFFERENTIAL DIVIDER
The UC3625 switching frequency is programmed with a timing resistor and capacitor. Unless the motor's inductance is particularly low, 20 kHz will provide acceptable ripple current and switching losses while minimizing audible noise.
(1)
F = 2 I R0 scCosc
The relatively small oscillator signal amplitude requires careful timing capacitor interconnect for maximum frequency stability. Circuit board traces should to be as short as possible, directly connecting the capacitor between pins 25 and 15, with no other circuits sharing the board trace to pin 15 (ground).
When tight oscillator stability is required, or multiple systems must be synchronized to a master clock, the circuit shown in figure 8 can be used. As shown, the circuit buffers, and then differentiates the falling edge of the master oscillator. The last stage provides the necessary current gain to drive the 47 ohm resistor in series with the timing capacitor. If the master clock is from a digital source, the first two stages are omitted, and the clock signal is interfaced directly to the final stage through a restive divider as shown. The slaves are programmed to oscillate at a lower frequency than the master. The pulse injected across the 47 ohm resistor causes the oscillator to terminate its cycle prematurely, and thus synchronize to the master clock.
+15
+15 VREF (+5)
MASTER 1k
C~K~.:
RyJC.r PERIOD
11.3 ·MASTER PERIOD
Figure 8 - External Synchronization Circuit
,.-----------------
RADJ
:
Rg ~ 1SENSE1
RADJ «RF LOW VALUE DIVIDER
ISENSE 2
\.-----------------
Figure 9 - Balance Impedance Current Sense Input Circuits
The RC-Brake pin serves two functions: Brake command input (not used in this design), and tachometer I digital commutation filter one-shot programming. Whenever the commutation state changes, the one-shot is triggered, outputting a tach pulse and inhibiting another commutation state change until the one-shotterrninates. The one-shot pulse width is programmed for approximately 1/2 the shortest commutation period.
where the shortest commutation period= 20 I (RPMMAXNPOLesl
CURRENT SENSING AND FEEDBACK
For optimum current sense amplifier performance, the input impedance must be balanced. Low value resistors (1OOto500 ohm) are used to minimize bias current errors and noise sensitivity. Additionally, if the sense voltage must be trimmed, a low value input divider or a differential divider should be used to maintain impedance matching, as shown in figure 9.
An average current feedback loop is implemented by the circuit shown in figure 10. With four quadrant chopping, motor current always flows through the sense resistor. When PWM is off however, the flyback diodes conduct,
9-312
APPLICATION NOTE
10lc
Rea· l:C:~:
(NOMINAL)
~ YREf Uk
CURRENT COMMAND
OT05V
·------- ------ ... -...............
OJJ25
Rs
Figure 10 - Average Current Feedback Circuit Configuration
U·130 is suppressed using a NTC thermistor, while a bridge rectifier and capacitive filter complete the high voltage supply. A small 60 Hz. transformer supplies 15 Volts through a three pin regulator to power the control and drive circuits.
A bus clamp is easily designed around a UC3725 MOSFET driver, as shown in figure 11. As in the highside switch drive, the UC3725 assures reliable operation, particularly during power-up and power-down. The divider current is set to 1 mA at the threshold, which is a reasonable compromise between input bias current error and dissipation. An additional tap programs the over-voltage coast a few volts above the bus clamp, saving a resistor and some dissipation while reducing the tolerance between the bus clamp and the overvoltage coast. Setting the bus clamp discharge current equivalent to the maximum motor current will assure effective clamping under all conditions. The load resistor value is therefore:
causing the current to reverse polarity through the sense resistor. The absolute value amplifier cancels the current polarity reversal by inverting the negative current sense signal during the flyback period. The output of the absolute value amplifier therefore is a reconstructed analog of the motor current, suitable for protection as well as feedback loop closure.
When the current sense output is used to drive a summing resistor as in this application example, the current sense output impedance adds to the summing resistor value. The internal output resistor and the amplifier output impedance can both significantly effect current sense accuracy if the external resistance is too low. Although not specified, the total output impedance is typically 430 ohms at 25 degrees C. Over the military temperature range of ~55to+125 degrees C, the impedance ranges from approximately 350 to 600 ohms. An external 2 k resistor will result in an actual 2.43 k summing resistance with reasonable tolerance. A higher value external resistor and trim pot will be required if high closed current loop accuracy is required.
The current sense output offset voltage is derived from the +5 V reference voltage. By developing the command offset from the +5 V reference, current sense drift over temperature is minimized. The offset divider must be trimmed initially to accommodate the current sense amplifier offset tolerance.
POWER SUPPLV AND BUS CLAMP
Input power is filtered to reduce conducted EMI, and transient protected using MOVs. Power~up currentsurge
The load resistor dissipation is dependant on the energy removed from the load inertia, and the frequency with which the energy is removed.
where J = inertia in Nm sec2 w 1 = initial velocity in rad/sec w 2 =final velocity in rad/sec
Note that if the deceleration time approaches the load resistor's thermal time constant, a higher power resistor will be required to maintain reliability.
CURRENT LOOP OPTIMIZATION
The block diagram of the current control loop is shown in figure 12. The current sense input filter has minimal affect on the loop and can be ignored, since the filter pole must be much higher than the system bandwidth to maintain waveform integrity for over-current protection. The current sense resistor R8, is chosen to establish the peak current limit threshold, which is typically set 20% higher than the maximum current command level to provide over-current protection during abnormal conditions. Under normal circumstances with a properly compensated current loop, peak current limit will not be exercised. The input divider network provides both offset adjustment and attenuation, with R1N selected to accomodate the current command signal range.
9-313
APPLICATION NOTE
SA
V130LA20A
115 VAC
1 UF
1mH 0.47 UF
z
U-130 +E
+E
196k 1000pF
I 1mA ' VcoaAt ST
OV/ COAST
3.16k 1.75k
+15 3k
2N3906 (2)
1k
7815 ......---....-- +15
470Uf
25V
0.01 UF
VREF (+5)
+15
=
N/C
+E
r----...,~o UC3725
INPUTe
Vee
18
~
INPUTA
OUTPUT
ATP4040
TIMING ENABLE
lsENSE GND
0.1 UF
Figure 11 - Power Supply and Bus Clamp
All PWM circuits are prone to subharmonic oscillation if the modulation comparator's two input waveform slopes are inappropriately related. This behavior is most common in peak current feedback schemes, where slope compensation is typically required to achieve stability. Average current feedback systems will exhibit similar behavior if the current amplifier gain is excessively high at the switching frequency. As described by Dixon [2] to avoid subharmonic oscillation for a single pole system: The amplifiedinductor currentdownslope at one input of the PWM comparator must not exceed the oscillator ramp slope at the other comparator input. This criterion sets the maximum current amplifier gain at the switching frequency, and indirectly establishes the maximum current loop gain crossover frequency.
A voltage proportional to motor current, which is the inductor current, is generated by the current sense resistor and the current sense amplifier circuitry internal to the UC3625. This waveform is amplified and inverted by the current amplifier and applied to the PWM comparator input. Due to the signal inversion, the motor
Vps
Figure 12- Current Loop Block Diagram
9-314
APPLICATION NOTE
~· 60 ·.....LOO~ GAIN
40
.. ~~·
CAGAIN
p
20
~
GAIN
(dB) o
"-\
POWER~
CIRCUIT
GAIN
!'-,..
-20
~
-40
1
10
100
1k
10k 100k
~~)·.:I i l"'T:l.I
Figure 13- Open Loop Gain and Phase Versus Frequency
current downslope appears as an upslope as shown in figure 12. To avoid subharmonic oscillation, the current amplifier output slope must not exceed the oscillator ramp slope. A motor control system typically operates over a wide range of output voltages, and is usually powered from an unregulated supply. The operating conditions which cause the greatest motor current downslope must be determined in order to determine the maximum current amplifier gain which will maintain stability. When four quadrant chopping is used, the inductor discharge rate is described by:
U-130 Where: Vs is the oscillator ramp peak to peak voltage
(1.2 V for the UC3625) Ts is the switching period f5 is the switching frequency
The maximum current amplifier gain at the switching frequency is determined by setting the amplified inductor current downslope equal to the oscillator ramp slope.
(5)
The maximum BEMF and supply voltage for the design example are 87 and 175 Volts respectively, which translates to a motor speed of 1500 RPM, and a high-line supply voltage of 125 Volts AC. Using equation (5) with an oscillator voltage of 1.2 volts peak to peak at a frequency of 20 kHz, the maximum value for GcA is 20.2, or 26 dB. The current sense amplifier's gain of two is also part of GcA· With R1equal to 2.43 k, 20 k is selected for Rr to allow for tolerances, resulting in an actual GcA of 16.5, or24d8. The small-signal control to output gain of the current loop power section is described by:
(6)
Note that the factor of two in the numerator is a result of four quadrant chopping which only utilizes one-half of the modulator's input range for a given quadrant of operation.
Motor Current
Downslope
=
VPs~+
V
M
The greatest discharge slope therefore occurs when the supply and BEMF voltages are maximum.
The overall open loop gain of the current loop is the product of the actual current amplifier gain and the control to output gain of the power circuit. The result is set equal to one to solve for .the loop gain crossover frequency, fc:
The oscillator ramp slope is simply:
(7)
Oscillator Ramp Slope = Vs = Vs f s
Ts
(8)
9-315
APPLICATION NOTE At high line, where the supply is 175 Volts DC, fc is 3.5 kHz. The crossover frequency drops to 2.8 kHz at low line, where the supply is approximately 140 Volts DC. If greater bandwidth is required, the current amplifier gain must be increased, requiring a corresponding increase in switching frequency to satisfy equation (5).
Up to this point the motor's resistance (RM) has been ignored. This is valid since ~ predominates at the switching frequency. The motor's electrical time constant LjRM, creates a pole, which is compensated for by placing zero RFCFz at the same frequency. Additionally, pole RFCFPCFZ /(CFP+CFz) is placed at f5 to reduce sensitivity to noise spikes generated during switching transitions. The filter pole at f5 also reduces the amplitude and slope of the amplified inductor current waveform, possibly suggesting that the current amplifier gain could be increased beyond the maximum value from equation (5). Experimentally increasing GcA may incur subharmonic oscillation however, since equation (5) is only valid for a system with a single pole response at f5 . For the design example, standard values are chosen for CFz and CFP of 0.22 µF and 390 pF respectively, placing the zero at 36 Hz, and the pole at 20 kHz. Figure 13 shows open loop gain and phase verses frequency.
At very light loads, the motor current will become discontinuous - motor current reaches zero before the switching period ends. At this mode boundary, the power stage gain suddenly decreases, and the single pole characteristic ofcontinuous mode operation with its 90 degree phase lag disappears. The current loop becomes more stable, but much less responsive. Fortunately, the high gain of current amplifier is sufficient to maintain acceptable closed current loop gain and phase characteristics at typical outer velocity and/or position loop crossover frequencies.
When the current loop is closed, the output voltage of the current sense amplifier (2V Rs) is equal to the current programming voltage (Vcp) at frequencies below the crossover frequency. The closed current loop transconductance is simply:
(9)
At the open loop crossover frequency, the transconductance rolls off and assumes a single pole characteristic. The input divider network attenuates the current command signal to provide compatibility with typical servo controller output voltages, and decreases the closed loop transconductance by the ratio of
U-130
REa /(RE0 +R1N}. For the design example, the overall amplifier transconductance is 1.25 amps/volt, allowing full scale current (6 amps) with a 5 volt input command.
BIPOLAR TO SIGN/MAGNITUDE CONVERSION
The servo amplifier as shown in figure 6 requires a separate sign and magnitude input command. This is convenient for many microcontroller based systems which solely utilize digital signal processing for servo loop compensation. Analog compensation circuits however, usually output a bipolar signal and require conversion to sign/magnitude format to work with this amplifier. The circuit shown in figure 14 employs a differential amplifier for level shifting and ground noise rejection, and an absolute value circuit with polarity detection for conversion to sign/magnitude format. The current command signal is slightly attenuated and level shifted up 5 volts to allow single supply operation. The input divider circuit has been slightly modified from figure 9 to restore gain and provide a suitable offset adjustment range. Precision resistors (1 %) should be used for both the differential amplifier and the absolute value circuit to minimize DC offset errors. Figure 15 shows approximately 2 Amp peak motor current with a 500 Hz sinwave command. Motor current follows the input command with minimal phase lag, however some crossover distortion is present. This is not crossover distortion in the traditional sense, rather it is simply a fixed off-time caused by the cross conduction protection circuitry. Since this distortion is current amplitude independent, and decreases with frequency, its effect on overall servo loop performance is minimal.
10.0k
8.45k
CURRENT COMMAND +1·5V
10.0k
10.0k
10.0k
10.0k
LM324 QUAD OP· AMP ALL DIODES 1N4148 VREF"5V
33k Uk
Yep (PIN1)
DIRECTION (PIN6)
Figure 14 - Bipolar to Sign/Magnitude
9-316
APPLICATION NOTE
Figure 15 - 500Hz Sine Wave Command and Output Currents
DIRECT DUTY CYCLE CONTROL
There are many less demanding brushless DC servo applications which do not need a transconductance amplifier function yet require controlled operation in all four quadrants. For these systems, direct duty cycle control, also known as voltage mode control is often employed. Note that this is not voltage feedback, which requires additional demodulation circuitry to develop a feedback signal. With direct duty cycle control the amplifier simply provides open loop voltage gain. This technique is particularly advantageous when a microcontroller is used for servo loop compensation. By outputting a PWM signal directly, a digital to analog conversion is eliminated along with the analog pulse width modulator. While the simplicity of this technique is appealing, there are two major problems which must be addressed. The first and less severe problem is the complete lack of power supply rejection. Good supply filtering will often reduce transients to acceptable levels, while the servo loop compensates for slow disturbances. The second and more troublesome predicament is the output nonlinearity which occurs when transitioning between quadrants. This is best illustrated by examining the DC equations for the two possible cases. When operating in either quadrant one or three, rotation and torque are in the same direction. Assuming operation is above the continuous/discontinuous current mode boundary, the output voltage is described by:
U-130 When the direction command is reversed while the motor is rotating, operation switches to quadrant two or four, shifting the modulator's maximum output voltage point from full duty cycle to zero duty cycle.
(11) VM=2Vps(1-D)-Vps Note that the gain does not change, only the reference point has shifted. This occurs because the modulator only has a single quadrant control range - four quadrant operation results from the output control logic which is after the modulator. With the transconductance amplifier previously described, the error amplifier quickly slews during quadrant transitions, providing four quadrant control with minimal disturbance. When direct duty cycle control is used however, the servo loop filter must slew to maintain control. Unfortunately, this causes an immediate loop disturbance, with the greatest severity at the duty cycle extremes. This behavior can greatly effect the performance of an analog compensated servo, and therefore limits such systems to lower performance requirements.
With a microcontroller providing the servo loop compensation, nonlinear duty cycle changes can be accommodated, restoring linearity when transitioning between quadrants. Although nonlinear behavior still occurs when motor current becomes discontinuous, the effect on over.all system performance is usually minimal. By correcting for quadrant transition nonlinearities, the advantages of an all digital interface can be exploited without severely degrading system performance. The control system is fully digital right up to the output stage, where the motor's inductance finally makes the conversion to analog by integrating the output switching waveform.
The circuit shown in figure 16 uses a PWM input from a microcontroller to set the output duty cycle and synchronize the oscillator, while another input controls direction.
+15 VREF (+5)
lk
SET Rp'Cr PERIOD =1.3 · PWM PERIOD
where D = PWM duty cycle
Figure 16- Digital PWM Interface
9-317
APPLICATION NOTE Complete line isolation can easily be achieved by using opto-couplers. Although the performance of this technique falls short of the transconductance amplifier, the circuitry's simplicity while maintaining allofthe protection features of the UC3625 make it well suited to many cost sensitive applications.
SUMMARY
The application example demonstrates the relative simplicity in implementing a brushless DC transconductance servo amplifier using the latest generation controller and driver ICs. For less demanding applications, direct duty cycle control using a dedicated controller provides size and cost reduction, without sacrificing protection features. While more and more control functions are implemented in microcontrollers today, the task of interfacing to output devices, and providing reliable protection under all conditions will remain a hardware function. Dedicated integrated circuits offer considerable improvement over the discrete solutions used irrthe past, reducing both size and cost, while enhancing reliability.
UNITRODE DATA SHEETS
U-130
7. UC3625
8. UC3724
9. UC3725
ADDITIONAL REFERENCES:
10. APT40308N Data Sheet, Advanced Power Technology, Bend OR
11. M-178 8rushless Motor Data Sheet, MFM Technology, Inc., Ronkonkoma NY
12. "DC Motors - Speed Controls - Servo Systems", Electro-craft Corporation, Hopkins MN
REFERENCES Unitrode Publications:
1. W. Andreycak, "A New Generation of High Performance MOSFET Drivers Features High Current, High Speed Outputs", Application Note# U-126
2. L. Dixon, "Average Current Mode Control of Switching Power Supplies", Unitrode Power Supply Design Seminar SEM700, topic 5
3. 8. Holland, "Modelling, Analysis and Compensation of the Current-Mode Converter'', Application Note# U-97
4. 8. Neidorff, "New Integrated Circuit Produces Robust, Noise Immune System For 8rushless DC Motors", Application Note# U-115
5. J. O'Connor, "Unique Chip Pair Simplifies Isolated High Side Switch Drive", Applicatisn Note # U-127
6. C. de Sa e Silva, "A Simplified Approach to DC Motor Modeling For Dynamic Stability Analysis", Application Note # U-120
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD.· MERRIMACK, NH 03054 TEL. 603-424-2410 ·FAX 603-424-3460
9-318
n n Ll=:1_J
INTEGRATED CIRCUITS
-UNITROOE
APPLICATION NOTE
U-131
Simple Switchmode Lead-Acid Battery Charger John A. O'Connor
Abstract
Lead-acid batteries are finding considerable use as both primary and backup power sources. For complete battery utilization, the charger circuit must charge the battery to full capacity, while minimizing over-charging for extended battery life. Since battery capacity varies with temperature, the charger must vary the amount of charge with temperature to realize maximum capacity and life. Simple, low cost circuits are currently available for small, low power requirements, while more complex solutions are affordable only on larger more expensive systems. Often the greatest challenge is in designing mid-size, mid-price systems, where obtaining optimum performance at moderate cost and complexity may be nearly impossible withoutdedicated integrated circuits. This paper describes a compact lead-acid battery charger, which achieves high efficiency at low cost by utilizing switchmode power circuitry, andprovides high charging accuracy by employing a dedicated control IC. The circuit described can be easily adapted to lower or higher power applications.
Lead-Acid Basics
Lead-acid battery chargers typically have two tasks to accomplish. The first is to restore capacity, often as quickly as practical. The second is to maintain capacity by compensating for self discharge. In both instances optimum operation requires accurate sensing of battery voltage and temperature.
When a typical lead-acid cell is charged, lead sulfate is converted to lead on the battery's negative plate and lead dioxide on the positive plate. Over-charge reactions begin when the majority of lead sulfate has been converted, typically resulting in the generation of hydrogen and oxygen gas. At moderate charge rates most of the hydrogen and oxygen will recombine in sealed batteries. In unsealed batteries however, dehydration will occur.
The onset of over-charge can be detected by monitoring battery voltage. Figure 1 shows battery voltage verses percent of previous discharge capacity returned at various charge rates. Over charge reactions are indicated by the sharp rise in cell voltage. The point at which over-charge reactions begin is dependent on charge rate, and as charge rate is increased, the percentage of returned capacity at the onset of over-charge diminishes. For over-charge to coincide with 1OC% return of capacity, the charge rate must typically be less than C/100 (1/100 amps of its amp-hour capacity). At high charge rates, controlled over-charging is typically
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100 125 150
PERCENT OF PREVIOUS DISCHARGE CAPACITY RETURNED
Figure 1. Over-charge reactions begin earlier (indicated by the sharp rise in cell voltage) when charge rate is increased. (Reprinted with the permission of Gates Energy Products, Inc.,)
9-319
APPLICATION NOTE
U-131
employed with sealed batteries to return full capacity as quickly as possible.
To maintain capacity on a fully charged battery, a constant voltage is applied. The voltage must be high enough to compensate for self discharge, yet not too high as to cause excessive over-charging. While simply maintaining a fixed output voltage is a relatively simple function, the battery's temperature coefficient of -3.9mV/degree C per cell adds complication. If battery temperature is not compensated for, loss of capacity will occur below the nominal design temperature, and over-charging with degradation in life will occur at elevated temperature.
Charging Algorithm
To satisfy the aforementioned requirements and thus provide maximum battery capacity and life, a charging algorithm which breaks the charging cycle down into four states is employed. The charging algorithm is illustrated by the charger state diagram shown in figure 2. Assuming a fully discharged battery, the charger sequences through the states as follows:
1. Trjc!de-cbarge If the battery voltage is below a predetermined threshold, indicative of a very deep discharge or one or more shorted cells, a small trickle current is applied to bring the battery voltage up to a level corresponding to near zero capacity (typically 1.7V/cell @ 25 degrees C). Trickle charging at low battery voltages prevents the charger from delivering high currents into a short as well as reducing excessive out-gassing when a shorted cell is present. Note that as battery voltage increases, detection of a shorted cell becomes more difficult.
2. Bulk-charge Once the trickle-charge threshold is exceeded the charger transitions into the bulk-charge state. During this time full current is delivered to the battery and the majority of its capacity is restored.
3. Over-charge Controlled over charging follows bulk-charging to restore full capacity in a minimum amount of time. The over-charge voltage is dependent on the bulk-charge rate as illustrated by figure 1. Note that on unsealed batteries minimal over-charging should be
OVERCHARGE---..>
' - - - - - - CFLHOAARTG- E
I
/(..j~LKCHARGE
I----------- )
TRICKLECHARGE
J
CHARGER OUTPUT CURRENT
Figure 2. The charging algorithm Is broken down into four states
employed to minimize out-gassing and subsequent dehydration. Initially overcharge current is the same as bulk~charge current. As the over-charge voltage is approached, the charge current diminishes. Over-charge is terminated when the current reduces to a low value, typically one-tenth the bulk charge rate.
4. Float-Charge To maintain full capacity a fixed voltage is applied to the battery. The charger will deliver whatever current is necessary to sustain the float voltage and compensate for leakage current. When a load is applied to the battery, the charger will supply the majority of the current up to the bulk-charge current level. It will remain in the float state until the battery voltage drops to 90% of the float voltage, at which point operation will revert to the bulk charge state.
Charger Circuit Design
There are many possible circuit configurations which will provide the necessary control and output charging current. For efficient operation, particularly at higher output currents, switching power circuitry is preferred. To minimize cost as well as complexity each IC used must provide as much functionality as possible. A circuit topology was chosen which utilizes two special purpose ICs and a general purpose op-amp to provide all of the control
9-320
APPLICATION NOTE
U-131
functions, while a discrete MOSFET output stage handles the power. The circuit design is modular to simplify modification for different application requirements.
The charger circuit can be divided into three basic blocks. The first is the voltage loop control and state control logic which executes the control algorithm while providing temperature compensation. The second is the switch mode controller which regulates the current to the battery as commanded by the voltage loop control and state control logic. The third is the output power stage which is sized to efficiently deliver the charging current.
Voltage Loop Control and State Control Logic
Initially designed for charging small lead-acid batteries using a linear pass transistor for current control, the UC3906 directly implements the voltage loop control and state control logic while providing the appropriate temperature compensation. The block diagram of the UC3906 is shown in figure 3.
Battery voltage is monitored with a resistor divider string. This network establishes the float voltage, the over-charge voltage, and the trickle-charge threshold voltage by comparing to the precision temperature compensated reference. Since temperature is monitored on chip it is critical that the battery and the UC3906 are in close proximity, and
SINK
SOURCE COMPENSATION
VOLTAGE SENSE
POWER INDICATE
OVER-CHARGE 1181------1 >-+---t
TERMINATE
Figure 3. UC3906 Lead-Acid Battery Charger block diagram
9-321
TRICKLE BIAS
CHARGE ENABLE
STATE LEVEL CONTROL
OVER-CHARGE INDICATE
APPLICATION NOTE
U-131
that self-heating or heating from other components is minimized.
The differential current sense comparator is used to terminate over-charging and transition to the float state. The voltage amplifier provides gain and compensation for the voltage loop. The UC3906 is covered in detail in reference (3].
Switchmode Current Source
The charging algorithm places great demands on the current loop. during bulk charge full current must be supplied, yet during the float state the current draw may be only a few milliamps. This equates to a dynamic range in excess of 60 dB which can be very difficult to achieve with common peak current mode techniques. The wide dynamic range also requires operation with both continuous and discontinuous inductor current, potentially adding complication to voltage loop stabilization. Although load resistors can be employed to reduce the required dynamic range, their use can significantly degrade efficiency, particularly while in the float state. Note that a high value load resistor (1 O k) is employed to assure operation down to zero output current and to provide a discharge path for the output capacitor. Additionally, to provide precise bulk and trickle-charge current levels the closed current loop transconductance must be accurate. Average current feedback will circumvent these potential problems, and is the key to a successful implementation of the switching current source for this application.
Figure 4 shows the basic implementation of average current feedback. While slightly more complicated than typical peak current mode control schemes, average current feedback offers several critical performance enhancements. The high gain of the error amplifier at lower frequencies provides high closed current loop accuracy and accommodates the large output stage nonlinearity which occurs when the inductor current becomes discontinuous. Good switching spike noise immunity is inherent with this technique permitting stable operation at narrow duty cycles.
A UC3823 PWM controller shown in figure 5 was chosen for the current loop control circuit for several reasons. First and most importantly it is capable of operating linearly from very small duty cycles to near
Lo
Rs
CURRENT ERROR AMPLIFIER
Figure 4. Average Current Feedback Loop
100% duty cycle. Secondly the error amplifier bandwidth and configuration are well suited to the average current loop's requirements. Additionally, the output driver affords a simple interface to most discrete output power stages.
A separate op-amp configured as a differential amplifier senses the output current and level shifts the signal to the appropriate voltage. The offset and common mode rejection of this amplifier are the major source of current loop error.
Output Power Stage
To simplify development a simple buck regulator output stage was used. For further simplicity the high-side switch is implemented using a direct coupled P-channel MOSFET. A switched current sink provides gate charge, turning the MOSFET on while a zener diode limits the gate to source voltage to 12 volts. A second emitter switched current sink drives a PNP which removes gate charge, turning the MOSFET off. Undoubtedly this output stage is suitable for many applications, although higher power capability and efficiency can be achieved using N-channel devices. A relatively low value output inductor was chosen to minimize size and cost since operation in the discontinuous current mode is of no concern with average current feedback. Output ripple voltage is also not critical so the output capacitor was selected for ripple current capability. High frequency ringing caused by circuit parasitics is damped with a small RC snubber across the catch rectifier. A rectifier in series with the output
9-322
APPLICATION NOTE
U-131
1.25V
S~~~~ B t - - - - - - - L O - W - - t - - - CPRTR
1.4V
.-------m11 Ve
>-----1141 OUT A
'------11121 ~:~
av
UVLO
Figure 5. UC3823 High speed PWM Controller Block Diagram
prevents the battery from back driving the charger when input power is disconnected.
Complete Charger Circuit
A complete schematic for the switch-mode charger is shown in figure 6. Control circuit power is supplied from an emitter follower off a zener shunt regulator. The PWM frequency is set to 100 kHz as a reasonable compromise between output filter component size and switching loss. Output current is sensed in the battery return lead to minimize common mode voltage errors. This arrangement also allows direct current sensing for pulse by pulse current limiting adding further protection during abnormal conditions. The differential amplifier is set to a gain of 5 with the output signal referenced to the UC3823s 5.1V reference.
The current feedback signal is summed with the current command signal at the error amplifier's inverting input. To accommodate worst case offset
in both the error amplifier and the differential amplifier and allow zero output current, the non-inverting input of the error amplifier is biased 130 mV below the 5.1 V reference. Trickle bias is accomplished by injecting a small current into the differential amplifier's negative op-amp input, thus causing a proportional output current to balance the loop. Additionally, a 100 pF capacitor across the PWM comparator inputs enhances noise immunity, particularly at low duty cycles.
For maximum control and float voltage accuracy, the UC3906s ground is connected to the battery's negative terminal, thereby rejecting the current sense resistors voltage drop. The internal emitter follower output transistor interfaces to the current source as illustrated in figure 7. The voltage amplifier drives the output current command signal. The current command signal is limited by clamping the voltage amplifier output through a diode to 4.2 V. The clamp also prevents the emitter follower from
9-323
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APPLICATION NOTE
U-131
UC3906
CURRENT FEEDBACK SIGNAL
CURRENT ERROR AMPLIFIER
VOLTAGE ERROR AMPLIFIER
........................................
Figure 7. The UC3906's output transistor provides the interface to the switch mode current source.
saturating which would cause a large difference between collector and emitter currents due to excessive base drive.
Battery voltage is sensed by the resistor divider string, with the values shown for a typical 24 V (12 cell) application. Other battery voltages are easily accommodated by simply changing the divider values using the procedure presented in the UC3906 data sheet, although changes in input voltage may require modification of the output circuit and the control circuit power supply. The resistor divider establishes all of the state transitions with the exception of over-charge terminate, which is determined by detecting when the output current has tapered off to approximately one-tenth the bulk charge level. This is accomplished by the UC3906s current sense comparator which senses the appropriately scaled signal from the differential amplifier output.
Current and Voltage Loop Compensation
The charger circuit implements a two loop control
system with the current loop operating inside the
voltage loop. During trickle-charge, bulk-charge and
the beginning of over-charge the voltage loop is
saturated and the current loop is essentially driven
from a fixed reference.
·
With continuous inductor current the control to output gain of the current loop shown in figure 4 exhibits a single pole response from the output inductor. The error amplifier gain at the switching
frequency is set such that the amplified inductor current down-slope is less than the oscillator-ramp up-slope as seen by the PWM comparator. By setting the two slopes equal under worst case conditions (at maximum output voltage) maximum closed loop bandwidth is achieved without subharmonic oscillation.
Placing a zero below the minimum loop crossover frequency significantly boosts low frequency gain while a pole placed above the maximum crossover frequency enhances noise immunity. Note that since loop response is not particularly critical for battery charging, conservative compensation with plenty of phase margin is normally employed.
When inductor current becomes discontinuous, the power circuit gain suddenly drops, requiring large duty cycle changes to significantly effect output current. The single pole characteristic of continuous inductor current with its 90 degree phase lag disappears. The current loop becomes more stable, but less responsive. Fortunately the high gain of the error amplifier easily provides the large duty cycle changes necessary to accommodate changes In output current, thereby maintaining good average current regulation.
The block diagram of the voltage loop is shown in figure 8. With an inner transconductance loop the control to output gain of the voltage loop exhibits a single pole response from the output capacitor and equivalent load resistance. While it may Initially . appear that a simple fixed gain on the voltage amplifier would provide suitable loop compensation, further examination shows a severe drop in voltage gain at high loads, which would drastically reduce DC accuracy. A zero is placed in the voltage amplifier's transfer function to boost low frequency gain and therefore restore DC accuracy.
The current loop's single pole response above its crossover frequency cancels the output stage zero resulting from the output capacitor's capacitance. and ESR. Note again that since wide bandwidth is not required for battery charging, the voltage loop crossover frequency is well below both the current loop's pole and the output capacitor's zero. Low leakage capacitors must be used for the compensation network to maintain high DC gain
9-325
APPLICATION NOTE
U-131
since the voltage amplifier is a transconductance type. Loop stabilization is covered extensively in references [1] and [2].
Charger Performance Summary
The charger circuit properly executes the charging algorithm, exhibiting stable operation regardless of battery conditions including an open circuit load. The circuit was tested with 6, 12 and 24 V batteries by modifying only the battery voltage sense divider. As would be expected, circuit efficiency was best at high battery voltage, approaching 85% while bulk-charging a 24 V battery with a 40 V input supply voltage.
An analysis of circuit losses indicates several areas where efficiency could be improved. Any accuracy and offset improvement in the differential amplifier will allow a corresponding decrease in current sense r.esistor value and hence dissipation, while maintaining the same overall current loop accuracy. Replacing the output blocking rectifier with a Schottky would save a few watts if the Schottky's leakage could be tolerated. Further improvement could be made in that area by using a relay to disconnect the charger when input power is removed. A more conservative inductor design with less resistance would save a little over one watt. As expected, the greatest losses occur in the output switch. A lower on resistance FET and a higher peak current gate drive to reduce switching losses could save more than 5 watts. Incorporating a few of these improvements will easily increase circuit efficiency to greater than 90%.
Alternate Circuit Configurations
While the charger circuit as designed may be suitable for many applications, a few modifications should satisfy the majority of additional requirements. Higher voltage batteries can be charged by designing a higher voltage output stage. N~channel MOSFETs are preferable for cost and efficiency reasons, but are more difficult to drive than P-channels. Fortunately, the remainder of the circuit will require minimal modification.
Some applications may require both the battery and charger to share a common ground and thus prohibit current sensing in the batteries negative return. The differential amplifier can sense current at the inductor output if tighter tolerance resistors to improve CMRR are used. While this simple
modification renders a suitable signal for closing the current loop, another current sense signal referenced to ground must be developed for pulse by pulse current limiting. This signal is most easily derived by using a PNP level shift transistor, connecting the base to the 5.1 V reference and the emitter through a resistor to the differential amplifier output.
At higher battery voltages it may be desirable to float with a current rather than a voltage. Varying self-discharge rates of individual cells in high voltage batteries causes inevitable differences in cell charge levels. By employing a float current and applying a small continuous overcharge, variation of charge between cells is minimized. Precise output at float current levels places great demands on current loop accuracy, and will add unnecessary expense to the current sensing circuitry. A more cost effective alternative is to use a fixed linear current source which should be small and inexpensive considering the very low output current.
Thus far the input supply has not been addressed and is assumed to be from a voltage required elsewhere in the system or from a typical line frequency transformer, rectify bridge and filter capacitor. This may represent more than half the cost of the charger, and is certainly the majority of its size and weight. An obvious alternative is to replace the buck output section with a transformer coupled output, taking advantage of the switching control circuit already present. Buck derived circuits such as forward, half-bridge and full-bridge easily interface with the existing design, however resonant and flyback circuits are also applicable. A small (0. 75 W) auxiliary supply will be required to power the control circuitry since the modulator will output zero at times, prohibiting the use of a bootstrap winding commonly used on switching power supplies. This
VOLTAGE Cz .I..,,,._ ERROR AMPLIFIER
SWITCHMODE CURRENT
SOURCE
Figure 8. Voltage Control Loop block diagram
9-326
APPLICATION NOTE
approach is particularly cost effective tor stand-alone applications, allowing the design of a compact, light weight, high performance charger.
Summary
A practical switchmode lead acid battery charger circuit has been presented which incorporates all of the features necessary to assure long battery lite with rapid charging capability. By utilizing special function ICs, component count is minimized, reducing system cost and complexity. With the circuit as presented, or with its many possible variations, designers need no longer compromise charging performance and battery lite to achieve a cost effective system.
REFERENCES
1. L. Dixon, "Average Current Mode Control of Switching Power Supplies", Unitrode Power Supply Design Seminar, SEM?OO, Topic 5
2. L. Dixon, "Closing the Feedback Loop", Unitrode Power Supply Design Seminar, SEM700, Section C
3. R. Valley, "Improved Charging Methods for Lead-Acid Batteries Using the UC3906'', Unitrode Linear Integrated Circuits Data and Applications Handbook, IC600
4. L. Woffard, "New Pulse Width Modulator Chip Controls IMHz Switchers", Unitrode Linear Integrated Circuits Data and Applications Handbook, IC600
U-131
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. · MERRIMACK, NH· 03054 TEL. (603) 424·2410 FAX (603) 424·3460
9-327
n nINTEGRATEC
~CIRCUITS
-UNITRDDE APPLICATION NOTE
U-132
POWER FACTOR CORRECTION USING THE UC3852 CONTROLLED ON-TIME ZERO CURRENT SWITCHING TECHNIQUE
BILL ANDREYCAK
INTRODUCTION
The controlled on-time, zero current switching technique provides a simple and efficient solution to obtaining high power factor correction. This discontinuous inductor current approach essentially programs a constant switch on-time during one line half-cycle. It does not require any "complex" analog square, multiply and divide functions to control the instantaneous switch current as with other PFC techniques. Additionally, zero current switching limits the peak current to exactly twice that of the average inductor current over all line and load combinations. High efficiency operation is also achieved with no boost rectifier recovery concerns and power loss. In a typical 80 Watt application the UC3852 PFC technique delivers a power factor of 0.998 with 5.8% Total Harmonic Distortion at nearly 94% efficiency.
CIRCUIT SCHEMATIC
L2
05
Rl 01 02 INPUT
VOUT R5
R6 C2 85-132
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03 04
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R2
Ri'
Figure1.
9-328
APPLICATION NOTE
U-132
UC3852 FEATURES
The UC3852 PFC controller contains several features which minimize external parts count while providing excellent performance and protection. Optimized for this off-line PFC application, the UC3852 delivers high power factor (0.997 typical) and a low cost overall solution.
OFF-LINE PROTECTION
· undervoltage lockout with hysteresis 16V tumon, 11 V turn-off [1]
· clamped 12V gate drive output [2] · active low, self biasing output [3] · overcurrent protection [4]
CONTROL CIRCUIT ATTRIBUTES
· programmable maximum frequency (5] · programmable maximum on-time (6] · overcurrent indication output (7]
OPERATIONAL CHARACTERISTICS
· low operating current [8] · low start-up current (0.4 mA) (1) · few external required components · 30 V maximum supply input
CONTROL TECHNIQUE
· Zero Current Switching (9) · controlled on-time [6] · high noise immunity [6]
UC3852 POWER FACTOR CORRECTION CONTROL IC BLOCK DIAGRAM
s Q11--------1
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Figure2.
9-329
APPLICATION NOTE
U-132
UC3852 POWER FACTOR CORRECTION CONTROL IC BLOCK DIAGRAM
PFC TECHNIQUE OVERVIEW
Most power factor correction techniques incorporate the boost topology which can be operated in either the continuous or discontinuous inductor current modes and switched at a fixed or variable frequency. Generally, the fixed frequency, continuous inductor current variety is preferred for higher power ,applications to minimize the peak current. Below about 500 Watts, the discontinuous inductor current version operated in a variable· frequency mode offers several advantages. Benefits include reduced inductor size, minimal parts count and low cost of implementation. This paper will highlight the controlled on-time, zero current switched variety of discontinuous inductor current PFC operation.
by analyzing the .basic inductor waveform using specific attributes of this PFC tecl:mique for either charging and discharging of the inductor current. Since the inductor charging condition is being controlled by the UC3852 circuitry it will be used for the analysis.
INDUCTOR WAVEFORM
FUNDAMENTALS
CONTROLLED ON-TIME
On-time of the PFC switch is controlled by the voltage error amplifier of the UC3852 which is compared to a sawtooth waveform generated at the ICs RAMP function at pin 4. The PFC switch ontime varies with llne and load conditions but should be considered constant for one line half-cycle. A low frequency bandwidth is necessary in the voltage error amplifier loop compensation which is
typically rolled off to cross zero dB below the line
frequency.
ZERO CURRENT SWITCHING
Zero current switching facilitates three important advantages in this application. First, the inductor current must be zero before the next switching cycle is initiated inferring high efficiency and elimination of the boost rectifier recovery loss. Secondly, the change in inductor current (delta IL) is equal to the peak inductor current· (IL(pk)) since current starts and returns to zero each cycle. The discontinuous boost converter current waveform has a triangular shape with an area (charge) equal to one-half of the product of its height (peak current) multiplied by its base (time). Since the timebase can be considered as a series of consecutive triangles, the peak current is therefore limited to exactly twice that of the average current. This is valid for both the steady state and instantaneous switching cycle relationships. The converter operates right on the border between continuous and discontinuous current modes which results in variable frequency operation.
The "fixed" on-time in conjunction with zero current switching provide automatic power factor correction of the input current. This can be demonstrated
Flgure3.
v di 1·I=di
For the PFC boost converter operation, V can be replaced by Vin(!), the instantaneous voltage across the inductor. Also, it is assumed that the inductance and the switch on-time is constant tor the duration of one line-half cycle. The change in inductor current, delta I is actually the peak value of current (lpk(t)) since the inductor always begins charging at zero current, as forced by zero current switching. Substituting these relationships into the inductor wave from equation will demonstrate the simplicity of this specific technique when used tor power factor correction.
V=Vin(t)
L =constant
di= lpk(t)
di= constant
2. lpk(t) oc Vin(!)
This relationship demonstrates that the instantaneous line current will exactly track that of the instantaneous line voltage. Since the input voltage waveform is sinusoidal (Vin sin(wt)), then so is the input current (lpk sin (wt)). This controlled on-time, zero current switched technique provides automatic power factor correction with very simple control circuitry.
9-330
APPLICATION NOTE
U-132
PFC POWER STAGE DESIGN
It is advantageous to begin the power relationships from the AC line input of the preregulator and work towards the DC output section. The instantaneous primary voltage (Vp(t)) is related to the steady state peak input (VP) by the following relationship:
3. VP ( t ) = VP sin ( wt )
where VP= { 2x Vp ( rms )
The amplitude of Vp(t) varies between zero and VP as sin(wt) goes from zero to one for one line half-cycle. Note that Vp(t) and VP are always positive with respect to the PFC circuit common due to the bridge rectification of the AC input waveform. The input current can similarly be expressed as :
4. IP(t)=IPsin(wt)
where IP= "2"x Ip ( rms )}
Input power to the PFC converter is the Root Means Squared (RMS) component of the line voltage (Vp(RMS)) multiplied by the line current (lp(RMS)). This can also be expressed using the peak terms of each waveform which is simpler for this application.
5.
. Pin
=
V-./P2"
x
-I.P/2"
p· (VP x IP)
In
2
The average DC output current (lo) is determined by dividing the output power (Po) by the output voltage (Vo).
Vo 6. Po=IO
Converter efficiency (n) can also be factored into the design equations although it may typically be in the neighborhood of 94% at full load.
7. Pin= Po n
or Po= Pin x n
where Pin=( VP; IP)
7A. Po=(VPx~Pxn)
Equation 7A. can expressed with regard to primary
current.
78. IP ( 2 x Po ) (VP x n)
It has been already established that the peak inductor current is exactly twice that of the average inductor current due to zero current switching.
8. IL ( pk ) = 2 x IL ( avg )
The average input current must be equal to the average inductor current since they are in series.
9. lpri (avg)= IL (avg)
Combining equations yields the peak inductor current to the input current.
10.I ri( k) C4 xPo) p p (VP x n)
The inductor current can now be analyzed in its time variant form and over all line and load conditions.
11 _IL ( t) = ( 4 x Pox sin (wt)) (VP xn)
TIMING RELATIONSHIPS
Steady state conditions will be used to analyze the timing relationships of this controlled on-time PFC technique. The peak primary voltage (VP) will be
used as the starting point for the calculations, so
the input line must be specified.
The inductor relationship of equation 1. will be solved for the specific on-time required to charge the inductor to the correct peak current. This equation can be restated for a given set of operating
conditions as:
12. t (on)= IL (pk) x VLP
Substituting equation 10. for IL(pk) into equation 12 results in:
12A. t (on)= ( 4 x Po x L ) (VP 2 xn)
The instantaneous switch off-time varies not only with the line and load conditions, but also with the instantaneous line voltage. Off-time is analyzed by solving equation 1. for the inductor discharging where the voltage across the inductor is Vout mi" nus Vin. This should be solved for the time required to discharge the current from its instantaneous peak to zero, which can be expressed as:
_ (IL (pk) x L)
13· t (off) - (V<r-VP (sin (wt))
Substituting equation 1o. for IL(pk) above will ex-
pand the off-time equation to:
13A. t (off)= (4 x Pox L x sin ~wt)) VP x (Vo - (VP x sin (wt)
Due to the high efficiency during the boost inductor discharge and lack of rectifier recovery losses, the efficiency term (n) is essentially one. Loss can be ignored during the off-time since the boost diode forward voltage drop is very small in comparison to
9-331
APPLICATION NOTE
U-132
the high voltage DC output, and resistive losses at these lower powers and currents are minimal.
CONVERSION PERIOD
The total time for one switching cycle is obtained by adding the on-time with the instantaneous offtime. Switching frequency is the reciprocal of the cyclical switching period which varies with line, load and instantaneous line voltage.
14. t(per) = t(on) +!(off)
1
sin (wt)
t(per) = 4 x Po x L x VP2 + VP x [Vo - VPsin(wt)]
timing circuit. Both t(on)max .and t(off)max will be individually calculated and added together to obtain the maximum conversion period, t(per)max. This is required to obtain the inductor value. Equations 12A and 13A will be solved for their respective maximums.
128. t (on) max= 4 x L x Po (max) VP (min) 2
4 x L x Po (max) 138· 1(off) max= [VP (min) x (Vo - VP (min)]
SWITCHING FREQUENCY
15. f(conv) =1 I t(per)
Switching frequency varies with the steady state line and load operating conditions along with the instantaneous input line voltage. Generally, the PFC converter is designed to operate above the audible range after accommodating all circuit and component tolerances. Many applications can use thirty kiloHertz (30 kHz) as a good first approximation. Higher frequency operation should also be evaluated as this can significantly reduce the inductor size without negatively impacting efficiency or cost. In most applications, the minimum switching frequency will coincide with full load operation during the peak of the input voltage waveform at low line. In contrast, the highest frequency conversion occurs at light load and high line conditions, just as the input voltage waveform nears the zero crossing point. A plot of t(on), t(off), t(per) and switching frequency versus instantaneous line voltage is shown in figure 4 and for the specific application circuit of figure 1. Figure 5 demonstrates the typical changes incurred in conversion frequency from low to high line inputs.
SELECTING THE OUTPUT VOLTAGE
The boost converter output voltage should be designed to be at least thirty volts higher than the peak of the input voltage at high line. This will prevent long conversion cycles due to the small voltage across the discharging boost inductor. When this thirty volt margin is ignored, the minimum switching frequency will occur at the peak of high line operation and not at low line, but also at full load. This will require recalculation of the timing intervals.
INDUCTOR CONSIDERATIONS
The exact inductor value can determined by solving equation 14 for the required inductance at the selected minimum operating frequency. Maximum on-time needs to be programmed into the UC3852
o~~~~~~~~~~~~~~
0 5 ~ ~ ~ ~ ~ § ~ ~ ~~~
INSTANT ANEOUS LINE VOLTAGE (VAC)
Conversion Times vs Instantaneous Line Nominal Line Voltage Fig.4
N"10 :c 65. ~60.
>0ffi45555or,,.,..,.,,,,__--d__,___
5 40.
w35r.'.""'."-~,,-,.,._,...:~~~~.;..:;:_:~
If 30 . 25 . 20~~~~~~~~~~~~~~o 5 10 20 30 40 50 60 70 80 90 100110120130
INSTANT ANEOUS LINE VOLT AGE (VAC)
Conversion Frequency vs Instantaneous Line Fig.5.
14A. t(per)max = t(on)max + t(off)max The minimum conversion frequency (F(conv)min) corresponds to the reciprocal of the maximum conversion period, t(per)max.
15A. F(conv)min = 1 I t(per)max
9-332
APPLICATION NOTE
U-132
INDUCTOR VALUE
The inductance value necessary for an application can be obtained by substituting equations 128 and 138 into 15A. using the relationship of 14A.
16A L = VP (min) 2 x [Vo - VP (min)] · 4 x Po (max) x Vo x F (conv) min
This equation provides insight as to the possible ways to reduce the inductor value (size and cost) for a given set of design specifications. The most obvious approach is to increase the minimum conversion frequency above thirty kiloHertz if none of the other parameters (Vo, Po) can be varied.
INDUCTOR DESIGN SUMMARY
Generally, the size and cost of an inductor vary with its energy storage capacity, W(L). Although most of the energy is stored in the air gap (with a gapped ferrite design), the core set must support the necessary flux density (8)without saturating or exhibiting high core loss. The required energy storage of the boost inductor is:
17. W(L) =0.5*L*IL(pk)1'2
The number of turns required for a selected core size and material is:
18. N = L*IL(pk)*1CY'4/ (8max*Ae)
where 8max is in Teslas and Ae is in square centimeters (cm"2)
The center leg gap to achieve the correct
inductance and storage is expressed by:
19. l(gap)={Uo*Ur*W,2*Ae*1 QA-2}/L (cm)
where Uo=4*Pi*1QA-7 (permitivity of free space), and Ur=1 (relative permeability of air)
OUTPUT CAPACITOR
The value of output capacitance is a generally determined by the required hold-up time or the acceptable output ripple voltage for a given application. It may also be governed by the specified ripple current rating or capacitor temperature rise. Typically, an approximation of one microFarad per Watt (1 uF/W) is a good starting point. The exact value can later be changed depending on conversion frequency and other factors previously mentioned.
Electroly1ic capacitors are typically used near 80% of their working voltage. This will necessitate a 500 VDC rating for use in a 264 VAC PFC application which may not be practical from a cost perspective. One option is to connect two lower voltage capacitors in series, each having the same value and a 250VDC rating.
SEMICONDUCTOR SELECTION
Peak currents and voltages must first be known over all operating conditions to select the proper MOSFET switch and boost rectifier. Standard design practice is to derate all semiconductors to about 75% of their maximum ratings, indicating the use of 500+ volt devices.
Low cost bipolar transistors are an acceptable alternative to MOSFETs if the conversion frequency is maintained fairly low. Inexpensive high voltage diodes with recovery times of 200 nanoseconds, or less should be used for the boost rectifier. Two popular devices are the 1N4937 and MUR160. Speed is not an issue with the input bridge rectifiers where 1N4004 to 1N4006 types are acceptable. High frequency switching noise in the PFC converter should be well filtered before reaching the input bridge diodes due to their low speed characteristics. This is best accomplished by adding an UC filter between the bridge rectifier DC output and the boost converter.
CONTROL CIRCUIT DESIGN :
PROGRAMMING THE UC3852
STARTUP CIRCUITRY
The UC3852 design incorporates a low startup current feature and draws less than one milliamp ( mA ) from the Vee bias supply. This minimizes the power loss due to with the startup resistor after the converter begins operation when a bootstrap winding supplies the full DC supply current. The UC3852 IC turns on when Vee reaches approximately 16 volts, and IC supply current will increase to its operational level. Undervoltage lockout protection will turn the UC3852 device off when the supply voltage falls below the lower UVLO threshold of approximately 10 volts.
The startup circuitry for this off-line consists of a startup resistor from Vee to the input supply voltage and a storage capacitor from Vee to ground. Typically, select Rstart to supply around 1.5 milliamps (rms) of charging current (l(charge) at low line. The exact value can be obtained from the following approximations.
R(start) = VP(min) - V(turn--0n) 1.41 x l(charge)
The Vee bias supply filter capacitor value is determined by several factors, but primarily by the UC3852 undervoltage lockout hysteresis. Implementation and phasing of this boost inductor winding in addition to soft start circuitry will also effect the capacitance.
9-333
APPLICATION NOTE
U-132
C(Vcc) = (ICC - l(charge) x t~boot) UVLO hysteresis
For many applications, the following approximations can be used:
ICC=10mA
l(charge) = 1.5 mA
t(boot) = 10 ms ( one-half cycle at 50 Hz)
UVLO hysteresis = 5 volts
V(turn-on) = 15V
A standard 15 uF electrolytic with an adequate voltage rating (35V once derated) is used.
PROGRAMMING THE ON-TIME
The maximum switch on-time must be calculated to program the UC3852 oscillator. This maximum occurs when the line voltage, VP is at its minimum and the output power is at its maximum. This is more commonly known as the low line, full load condition.
t(on)max = 4*Pout(rnax)*L I Vp(min)"2
The UC3852 on-time is programmed by RIC components and uses two of the IC pins. A resistor from the ISET pin to ground programs the charging current into the RAMP pin. The lset pin has an output voltage of approximately 5 volts, so the ISET is 5 volts divided by Rset. Typical charging current should range between 100 and 600 microamps.
The RAMP pin is used as one input to the Pulse
Width Modulator of the UC3852. Internally, the RAMP voltage is compared to the error amplifier output (COMP) voltage to determine the exact ontime. The RAMP pin has a maximum amplitude of approximately 9 volts, and begins charging from approximately 0.2 volts, or an 8.8 volt swing.
The RAMP capacitor value is selected to program the maximum switch on-time as it charges from 0.2 to 9 volts by lset. It can be calculated from the capacitor charge equation, shown below.
C=(l*dt)/dV
C(RAMP) = [ lset * t(on)rnax] I 8.8 V
The RAMP capacitor should be selected first from a list of standard values within the 100pF to 1nF range. The resulting ISET programming resistor selection is much easier as standard values with an initial tolerance of one percent (1%) are readily available.
RSET = 5 x t(on)max 8.8 x C(RAMP)
or
RSET = 0.568 * t(on)max/ C(RAMP)
t(on)rnax = [ RSET*C(RAMP) ] I 0.568 UC3852 ON-TIME vs. RSET &C(RAMP) ERROR AMPLIFIER COMPENSATION Power Factor Correction using the ZCS controlled on-time technique requires a very low bandwidth voltage loop to deliver high power factor (). This is necessary to keep the switch on-time constant during any one line cycle. Other advantages to this approach are high noise immunity, and simplicity,
z
~10nF
.L
l t% .LJ IL'
.LJ 12' f- 3nF IL l7
10 us l kd
Z l"
r---1nF
us~~~~~~~~~~
1k
10k
100k
Rs et
Max On-Time vs Rset and Ct Fig.6
since no squarer, multiply or divide circuitry is needed.
Configuration of the compensation circuitry is shown in the UC3852 PFC application schematic. First, the PFC preregulator output voltage (Vout) is accurately divided down to 5.0 volts to interface with the error amplifier. Three standard one-half watt resistors are used to avoid needing more expensive, high voltage rated resistors for this application. This signal goes through a 20K ohm input resistor to the error amplifier inverting input. Feedback components are a 1 meg ohm resistor and a 0.1 uF capacitor in parallel from the ElA output to the inverting input.
This recommended amplifier compensation delivers one low frequency pole in the loop .response at 1.6 Hz, as programmed by 1 meg ohm and 0.1 uF components. Low frequency gain is determined by the 20 K ohm input resistor, the output voltage divider resistance and the 5.0 reference voltage seen at the amplifiers (internal) noninverting input.
9-334
APPLICATION NOTE
U-132
Many other compensation arrangements are possible.
Using this compensation network, a low frequency gain of approximately 34 dB is achieved. This rolls off with a single pole (-20 dB/decade) response centering at 1.6 Hz. The gain curve will intersect zero dB at about 120 Hz and result in excellent power factor correction. Better dynamic response and less overshoot of the output voltage can be obtained by adjusting the 20 K ohm input resistor to increase low frequency gain and move the zero dB crossing out to a higher frequency. Some slight degradation of the power factor is to be expected by increasing the loop response.
SOFT START
Soft starting of the output is optional, but recommended to minimize the output voltage overshoot upon power-up. This does not occur in applications which will always have some load on the output. However, most electronic ballast have either no load, or a very light load on the output at power-up and will see the overshoot. Soft start implementation requires only a diode and capacitor from the compensation pin to ground. Another diode from the capacitor to VCC discharges the soft start capacitor to the falling Vee voltage when the AC line power is removed. This will guarantee that the circuit will always start up in soft start if the line is AC plug is removed for a few seconds. Again, this is an optional feature which depends on the application.
One '1rick" to significantly reduce the size of the soft start capacitor is to replace the diode with a cheap PNP transistor. A capacitance multiplier can be obtained by connecting the PNP emitter to the error amplifier output and soft start capacitor from the base to ground. The collector of the transistor is connected to ground. This adaptation will scale the capacitance value up by beta of the transistor at the amplifier output. A 2N2907 or equivalent is a popular choice and will reduce the capacitance value by a factor of approximately 50.
A 1N914 or 1N4148 signal diode should be used from the base to emitter to prevent negative baseemitter voltages from damaging the transistor. Additionally, this transistor can easily be interfaced with any optional fault protection schemes to soft start the controller following a fault.
SOFT START IMPLEMENTATION
CURRENT SENSE
Current in the PFC design is sensed in the return line of the preregulator circuitry at the AC input bridge rectifiers. One side of the current sense resistor is referenced to the UC3852 "ground" con-
nection. The other end of the resistor develops the current sense voltage which is equivalent to minus IL(!) * Rsense. The UC3852 zero current detection circuitry incorporates two comparators, one for zero current detection and another for over current protection.
ZERO CURRENT DETECTION
The zero current detection circuitry uses a negative 10 millivolt (-10mV) threshold as its reference. This negative threshold guarantees that there are no
E/A OUT
CSS/B
- (PNP)i
Figure 7.
startup problems since this input must be pulled below ground for normal operation. Whenever the zero detect input is raised above the minus ten millivolt threshold, the comparator is triggered and the next switching cycle begins.
Inductor current can be sensed by a current sense resistor which develops minus 400mV maximum during an overcurrent condition. This should only occur at a twenty percent overload, or 1.2 * IL(pk).
R(shunt) = 0.4 VI ( 1.2 * IL(pk))
Power dissipated in the shunt can be calculated by using the RMS component of the line current. The peak input current (IP) is one half of the peak inductor current (IL(max). The RMS component of the line current (IP(rms)) is obtained by dividing the peak line current ( IP ) by the square root of two (1.41). IP(rms) = [ IL(pk) I (2*1.414)]
P (R(sense)) = IP(rms)1'2 · R(sense) Standard value, low resistance (1 ohm or less) one-eighth to one-quarter watt resistors can used alone or paralleled to obtain the exact value. Carbon composition or film resistors exhibit low series inductance and will work best. A small RIC filter can be added in the current sense circuitry to filter out switching noise caused by circuit parasitics. This delay will minimally effect the precise two-to-one ratio of the peak to average
9-335
APPLICATION NOTE
U-132
duce the. amount of EMl/RFI filtering required by minimizing the rectifier recovery noise. For best results, the filter delay time should match the rectific ers recovery time. A ten ohm resistor and a one nanoFarad (1 nF) capacitor are good starting values.
OVERC~RRENT FAULT PROTECTION
The UC3852 contains and overcurrent comparator (-400mV) which quickly terminates the PWM output. This comparator also drives circuitry connected to the ISET pin which raises its normal 5 volt amplitude to 9 volts during the overcurrent condition. In addition to programming the ramp capacitor charging current, the ISET pin can be used to drive external fault protection circuits. A resistor in series with a 5.6 volt zener diode to the ISET pin will develop approximately 3.4 volts across the resistor when an overcurrent fault is detected. This signal can be used to trigger external shutdown or hiccup circuitry.
RF
100
RCS
CF 1nF
inductor current and have an insignificant impact on power factor. However, this modification can re
ADVANCED PROTECTION CIRCUITRY
Certain applications of the UC3852 control IC may require sophisticated protection features. Some examples of these options are overvoltage protection and restart delay, soft start or latch-off following a fault. Each of these features can be added to the control circuit with a minimal amount of external parts, and often combined using shared components.
TO ISETCPIN3l
TO VCC CPIN7l
+VOUT
TO COMP CPI NB)
RI I
02
RI 0
DS
D6
C6
R9
RJ3
DB D7
Rl2
-VOUT
Figure a.
GATE DRIVE
The UC3852 PWM output section is MOSFET compatible and rated for a one amp peak current. This totem pole design also features a twelve volt (12V) clamped output voltage to prevent excessive gate voltage when used with unregulated (Vee) supply voltages. A twelve ohm resistor between the UC3852 and the MOSFET switch gate will limit the peak output current to its one amp maximum during normal operation.
Additionally, the UC3852 self biasing active low totem-pole design holds the MOSFET gate low during undervoltage lockout, preventing catastrophic problems at power-up and removal of the AC input.
Flgure9.
LIST OF COMPONENTS
C6=1 uF,35V 05,6 = IN4148 07 = 6.2 V ZENER 08 = 40 V ZENER 02,4 = 2N2907 03=2N2222 R9,10= 10K R11=1 MEG R12 =24 K R13 =Calculate for OVP R14=1 K
9-336
APPLICATION NOTE
U-132
TRANSFORMER COUPLED CURRENT SENSE
TO OUTPUT
CURRENT SENSE XFMR
+
REGULATED VOUT
Figure 10.
Soft start is programmed by R11, C6 and the beta of 02. Overcurrent protection starts at the UC3852 ISET pin which outputs a 9 V signal during a fault. This drives 03 on through 07 and discharges C6 causing a soft start. 04 also turns on with this arrangement which discharges Vee causing a "hiccup". This is optional, and replacing 03 with an SCR would latch the circuit off until power is reset. Overvoltage protection is attained via R11, R12, R13 and zener diode 08. When enough current flows through the zener (08), R11 biases transistor 03. Protection is similar to the overcurrent condition.
Regulated Auxiliary Bias Circuit
Flg.12 ciency. Two primary windings are needed to sense each component of the switched current. These may also be unequal in number of turns, depending on the input and output currents (or voltages). A single secondary winding and bridge rectification recreates the total inductor current. A small RIC filter network may be required to smoothen out spikes caused by the leakage inductance.
Universal AC Input Feedforward Circuit
VIN
R13 C(RAMP) l _ _
C11
BOOST INDUCTOR
~
+ VOUT
01 COUT -
Figure 11.
CURRENT SENSE TRANSFORMERS
A transformer can be used to sense current in most of the UC3852 applications for higher effi-
Figure 13.
REGULATED BOOTSTRAP SUPPLY
A regulated auxiliary supply is obtainable with a slight modification to the bootstrap interface and two inexpensive components. This circuit is advantageous in applications which incorporate other control ICs for the main converter or ballast drive sections. A regulated auxiliary voltage is NOT needed for the UC3852 which features a clamped twelve volt (typical) gate drive output voltage. This insures proper drive amplitude for power MOSFETs with an unregulated IC supply voltage to 30 volts.
9-337
APPLICATION NOTE
U-132
Dual AC Input Range (110/220 VAC) Feedforward Circuit
VIN
R
R
D
R
C(RAMP)l__
Figure 14.
OTHER PFC APPLICATIONS
The basic PFC schematic of Figure 1 can be used as a template for other PFC applications with dif· ferent input voltage ranges and output power levels. A majority of the changes will be to accommodate higher ( or lower ) voltages and currents. Once familiar with the complete design procedure as outlined in this application note, designers are encouraged to recalculate the values for their applications using the same guidelines.
UNIVERSAL AC INPUT RANGE
The UC3852 controlled-on time, zero current switched PFC technique can be used to accommodate wide AC input voltages with the addition of a simple feedforward circuit. This external circuitry is required to cancel out the line dependent changes in the switch on-time over the three-toone input range from 85 to 264 volts. Otherwise, the approximate nine-to-one control range of the UC3852 on-time would be fully used for line regulation allowing no accommodation for load changes.
CIRCUIT OPERATION
The rectified input voltage is applied across the network consisting of R10 through R12, 012 and C10. Capacitor C10 charges to the peak of the divided input voltage and is large enough to maintain this level over one line cycle. Diode 011 serves as an offset to bypass the range extender circuitry until a sufficient minimum line voltage has been es..
tablished, typically 80 VAC. Capacitor C11, a small filter capacitor and the base of transistor Q1 O reach a voltage of V(C 1O) minus the Zener forward voltage drop of diode 011. As this voltage rises, the emitter of Q10 and voltage across resistor R13 follows, offset by the base-emitter diode drop of 010. This increasing bias pulls more current from the UC3852 ISET pin which sits at a fixed voltage. The current in both resistor R13 and resistor RSET is pulled from the UC3852 ISET output. Within the UC3852, the ISET current is mirrored to the RAMP capacitor (Cramp) which is compared to the error amplifier output to determine the ON-time. As the input voltage increases bias to Q10, more current is pulled from ISET thus increasing the RAMP charging current. For a fixed output load, this circuit performs the function of voltage feedforward and can keep the error amplifier output voltage fixed regardless of AC input voltage. This allows the full use of the ICs ON-time control range to accommodate load variations.
FEEDFORWARD CIRCUIT DESIGN
LOW LINE:
ISET= 5V/RSET t(on)max=8.8*Cramp / ISET
HIGH LINE: ISET= 5V/(RSET II RSET')
GENERAL: V(C10)=1.41*VIN*R12/(R1 O+R11+R12) NOTE:V(C10)MAX=5V+Vzener ISET(MIN)=5VIRSET
ISET(MAX)=ISET(MIN)+5V/R13
FEEDFORWARD BEGINS WHEN :
V(C1 O)-Vzener-Vbe(Q10) OV
COMPONENTS:
C10=22uF/16V Q10=2N2222 C11 =1 nF/16V R10,11=100K
D10=1N4148 R12,13=5.1K Di 1=1 N5221 (2.4V) RSET=51 K
9-338
APPLICATION NOTE
CONTINUOUS CURRENT PFC BOOST CONVERTER
U-132
R1
R7
RS
C2 R9
Figure 15. CONTINUOUS PFC CURRENT IMPLEMENTATION
AC
RCS
Figure 16.
ON SWITCH
OFF
Figure 17.
9-339
.· APPLICATION NOTE
UC3852 CONTROLLED PFC FLVBACK CONVERTER
C1
U-132
C2 CF
Figure 18.
UC3852 AS A CAPACITIVE DISCHARGE DRIVER
C1
C2 CF
Figure 19. 9-340
APPLICATION NOTE
U-132
AUTORANGE (110/220) VOLTAGE
FEEDFORWARD CIRCUIT
Input line voltage feedforward can also be obtained with a simple circuit for dual AC input ranges with less demanding load variations. Shown below is a single step autorange circuit for use with the UC3852 timing circuitry. Basically, the TL431 is used as a comparator to switch in a second timing resistor (RSET') when the input voltage exceeds a preset threshold.
The AC input voltage 1s rectified by diode 020 and divided down by resistors R20 and R21. Capacitor C20 peak charges and filters this waveform to develop a DC voltage proportional to the input line. RSET is programming the initial charging current to the timing capacitor CRAMP. When the voltage across C20 exceeds the 2.5 V threshold of the TL431 comparator, its oU1put goes low. This places
MAIN SWITC~I--
RAMP
R
IPRI
CF R
SLOPEL__ COMP
Figure20.
a second timing resistor, RSET', in parallel with the original one thus increasing the current to CRAMP and performing line feedforward. Resistor values should be selected to switch in the feedforward compensation at approximately 155 VAC which is mid-range between high line of a 110 VAC input (130 VAC) and low line for a 220 VAC input (180 VAC). The value of RSET' must be selected to account for the TL431 output saturation voltage.
CONTINUOUS CURRENT PFC BOOST CONVERTER
The zero current switched PFC technique can also be modified to operate in the continuous inductor current mode. A positive amplitude, small offset signal is derived from the input voltage waveform. It gets added to the normal current sense signal which is negative with respect to ground. Summing these two signals to the ZEROinput biases the ac-
tual inductor current sense more positive. Therefore, the zero current detection threshold is crossed before the inductor current is actually zero, and the PFC preregulator operates with continuous ~urrent. The exact amplitude of both parts of the mdu~tor current ca~ be determined by adjusting the inductance, on-time, and current sense resistor.
OTHER PFC TOPOLOGIES
The UC3852 can also perform power factor correctio~ using the Flyback topology with a slight degradation to Power Factor. A Flyback topology is commonly used to generate a lower (or much higher) voltage output than the Boost converter. A nonisolated version of this is shown in Figure 18. for simplicity.
A resistor in series with the power return lead senses the inductor charging current while the switch is on, similar to that of the boost converter. However, the discharging current information is lost when the switch is off while the stored inductive energy is delivered to the output. A second current sense resistor is added in series with the secondary winding as shown to recover this information. A small amount of filtering may be necessary to smoothen out switching noise spikes while summing the current sense signals.
Good regulation of the output voltage will be obtained with this technique although some 120 Hz (2 x line frequency) ripple is to be expected. The flyback circuitry cannot fully transfer power when the input line voltage goes down near zero each cycle. This approach has numerous applications where a small amount of power supply ripple is acceptable. Post regulator circuits can be added to improve regulation if necessary.
CAPACITIVE DISCHARGE CIRCUITS
The UC3852 can also be used in capacitive discharge circuits, typical of photoflash and strobe applications. In fact, the circuit shown below will provide the minimum recharge time for a given peak input current. Zero current switching insures that the next switching cycle is initiated as soon as the inductor current discharges to zero. There is no deadtime between conversion cycles and the output is charged as quickly as possible for the programmed maximum inductor current.
Regulation is achieved by using a burst mode of operation where the UC3852 stops delivering output pulses when the outpU1 voltage setpoint is reached. Operation will begin again when the output voltage drops below the lower programmed threshold. Both of these thresholds are pro-
9-341
APPLICATION NOTE
U-132
grammed by Ra, Rb and Re according to the following formulas.
Vout(max) = (S*(Ra+Rx))/Rx
Vout(min) = (S*(Ra+Rb))/Rb
where Rx=(~b*Rc)/(Rb+Rc)
NON PFC APPLICATIONS USING VARIABLE FREQUENCY OPERATION
Conventional PWM (non PFC) applications using a variable frequency control techniques can also be implemented with the UC3852. This applies to both current mode and variable ON-Time control methods. Typical examples of these are discontinuous current boost and flyback converters. Variable frequency operation is popular in numerous applications as it can minimize the peak current in comparison to fixed frequency designs. The zero current detection and switching technique of the UC3852 should be used in its standard configuration with current sensed below ground, although a current transformer can be introduced.
IMPLEMENTING CURRENT MODE
The ICs RAMP input will be used as the current sense input to be compared to the error amplifier
output for current mode control. A current transformer is recommended to fully utilize the 9 volt compliance of this pin. This implementation allows for a wide load swing with maximum noise immunity. The RAMP pin gets discharged by internal IC logic to 0.2 V at the end of each ON-time. Therefore, some series impedance to the current sense resistor is recommended to keep load current outside of the IC. Any filter capacitor to suppress the switch leading edge. noise spike will also get discharged. The ramp pin does. not need a programming resistor, but one could be used to introduce optional slope compensation via the filter capacitor.
VARIABLE ON-TIME CONTROL
The switch ON-Time can also be controlled by comparing a sawtooth ramp to the error amplifier output. Configuration of this is basically identical to the standard PFC application using a RAMP capacitor and resistor to program the maximum ONTime. Error amplifier compensation is likely to be much different and utilize a much higher loop crossover frequency than its PFC counterpart. The ICs error amplifier is similar to a '741 type general purpose OP-AMP and is programmed accordingly.
REFERENCES and ADDITIONAL
INFORMATION:
1. ANDREYCAK, W.: "Controlled ON-Time, Zero Current Switched Power Factor Correction Technique"; UNITRODE Power SUpply Design Manual SEM-800.
2. AHMED, SAEED, : "Controlled On-time Power FActor Correction Circuit with Input Filter''; Thesis, Virginia Polytechnic Institute.
3. MAMMANO,BOB and DIXON,LLOYD: "Designing High Power Factor Systems - Choosing the Optimum Circuit Topology", PCIM Magazine, March 1991.
9-342
APPLICATION NOTE
PERFORMANCE EVALUATION
The UC3852 controlled PFC circuit shown in Figure 1 was constructed using the list of materials provided for this application. Power Factor and Total Harmonic Distortion to the 5oth harmonic were measured using a VOLTEC PM- 3000 AC power analyzer. Test results indicated a power factor of 0.998 and T.H.D. below 6% at nominal line and full load. Very similar readings were obtained over the complete input voltage range and a moderate load change. Zero Current Switching (ZCS) facilitates high overall efficiency with this PFC technique.
UC3852 PFC TEST CIRCUIT
SPECIFICATIONS: VIN= 85 TO 135 VAC
VOUT = 350 voe
POUT=86W
MEASURED PERFORMANCE:
P.F. =0.998
T.H.D. = 5.81 %
TEST CONDITIONS· (nominal line) VIN= 115.7 VAC llN = 0.799 AAC PIN= 92.13 W VA IN= 91.84 INRUSH lpk = 17.7 A VOUT = 355.6 VDC IOUT = 0.242 ADC POUT= 86.1 W EFFICIENCY= 93.45 %
CURRENT WAVEFORM : HARMONIC CONTENT 1st: 0.775 Amp 3rd: 3.91 % 5th: 0.82 % 7th: 0.38% 9th: 0.35 %
11th: 1.30 % 13th: 0.21 %
LIST OF MATERIALS
CAPACITORS C2 = 0.47 uF I 200 V C3 = 82 uF I 400 V
C4 = 22 uF I 35 V C5 = 0.1 uF I 35 V
C6 = 1 nF I 16 V C7=0.1 uF/16V
DIODES D1-4 = 1N4004, 1 A I 400V D5 = 1N4937, 1 A I 600V trr = 200ns
D6=1N4148, 0.2 Al 50 V
INDUCTORS L2 = 1 mH Boost inductor L3 = Several turns on L2 to provide 20 VDC supply voltage
RESISTORS R1=100kohms1 Watt R2 = 0.1 ohm 1 W non-inductive R3=18.2kohms1% 1/2 W R4 = 1 megohm 1/4 W R5 = 330 k ohms 1% 1/2 W R6 = 390 k ohms 1% 1/2 W R7 = 10 k ohms 1% 1/4 W R8 = 20 k ohms 1/4 W R9 = 10 ohms 1/2 W non-inductive
TRANSISTOR
01 = IRF830 500 VI 4 A
INTEGRATED CIRCUIT Uf = UC3852
U-132
9-343
n nINTEGRATED
~CIRCUITS
-UNITRODE
APPLICATION NOTE
UCC 3800/112/3/4/5 BiCMOS CURRENT MODE CONTROL ICs
U-133
BILL ANDREYCAK
INTRODUCTION
Power supply design has become increasingly more challenging as engineers confront the difficulties of obtaining higher power density, improved performance and lower cost. The control for many of these switchmode supplies was revolutionized with two significant introductions; an advance technique known as current mode control, and a novel PWM solution, the UC3842 controller. This IC contained several innovative features for general purpose current mode controlled applications. Included were high speed circuitry, undervoltage lockout, an op-amp type error amplifier, fast overcurrrent protection, a precision reference and a high current totem-pole output.
The popular UC3842 control circuit architecture has been recently improved upon to deliver even higher levels of protection and performance. Advanced circuitry such as leading edge blanking of the current sense signal, soft-start and full cycle restart have been built-in to minimize external parts count. Additionally, these integrated circuits have been developed on a BiCMOS wafer fabrication process geared to virtually eliminate supply power and propagation delays in comparison to the bipolar UC3842 devices. These sophisticated new BiCMOS controllers, the UCC3800 through UCC3805 pulse width modulators address the challenges presented by the upcoming generations of power supply designs. This application note will highlight the features incoporated into this new generation of PWM controllers in addition to realizeable enhancements in typical applications. The specific differences between members of the UCC3800/1/2/3/4/5 family are reflective of their maximum duty cycle, undervoltage lockout thresholds and reference voltage which are summarized in the following table.
Unitrode Part# UCC3800 UCC3801 UCC3802 UCC3803 UCC3804 UCC3805
Max Duty VRef UVLO UVLO
Cycle
(V) Turn-On Turn-Off
100%
5.0 7.2
6.9
50%
5.0 9.4
7.4
100%
5.0 12.5
8.4
100%
4.0 4.1
3.6
50%
5.0 12.5
8.4
50%
4.0 4.1
3.6
9-344
APPLICATION NOTE
U-133
UCC3800/1/2/3/4/5 PWM FEATURES
A. Low start-up current B. Undervoltage lockout C. Low operating current D. Internal soft start E. Self biasing output during UVLO F. Leading Edge Blanking G. Self regulating Vee supply H. Full cycle restart after fault I. Clamped gate drive amplitude J. Reduced propagation delays K. 5 Volt operation (UCC3803 & 05)
IN-CIRCUIT ADVANTAGES vs. UC3842
· Greatly reduced power requirements · Eliminates bootstrap supply · Fewer external components · Lower junction temperature · Reduced stress during faults · No current sense RIC filter network · Faster response to fault · Higher frequency operation · Higher maximum duty cycles
UCC3800/1/2/3/4/5 DEVICE OVERVIEW
The BiCMOS UCC3800/1/2/3/4/5 devices have similar standard features and pinouts to the bipolar UC3842/3/4/5 PWMs and are enhanced replacements in many applications. There are a few important differences however which may require minor modifications to existing applications.
APPLICATION DIFFERENCES
1.Maximum supply voltage from a low impedance source: 12V versus 30V
2.Undervoltage lockout thresholds 3. Start-up current 4. Operating current 5. Oscillator ti ming component values 6. Reference voltage (UCC3803 and 05) 7.Vcc supply self clamping zener voltage 8.1 nternal soft start 9. Internal full cycle restart 10. Clamped gate drive voltage 11 . Current loop gain 12. ElA reference voltage ('03 & '05)
UCC3800/1/2/3/4/5 BLOCK DIAGRAM
FB COMP
©
@
REF
RC
Figure 1
9-345
APPLICATION NOTE
U-133
SUPPLYING POWER
An internal Vee shunt regulator is incorporated in each member of the UCC3800/1/2/3/4/5 PWMs to regulate the supply voltage at approximately 13.5 volts. A series resistor from Vee to the input supply source is required with inputs above 12 volts to limit the shunt regulator current as shown in figure 2. A maximum of 10 milliamps can be shunted to ground by the internal regulator.
The internal regulator in conjunction with the device's low startup and operating current can greatly simplify powering the device and may eliminate the need for a regulated bootstrap auxiliary supply and winding in many applications. The supply voltage is MOSFET gate level compatible and needs no external zener diode or regulator protection with a current limited input supply. The UVLO start-up threshold is 1.0 volts below the shunt regulator level on the '02 and '04 devices to guarantee startup.
It is important to bypass the ICs supply (Vee) and reference voltage (Vref) pins with a 0.1 uF to 1uF ceramic capacitor to ground. The capacitors should be located as close to the actual pin connections as possible for optimal noise filtering. A second, larger filter capacitor may also be required in off-line applications to hold the supply voltage (Vee) above the UVLO turn-off threshold during start-up.
+400VDC
Undervoltage lockout thresholds for the UCC 3802/3/4/5 devices are different from the previous generation of UC3842/3/4/5 PWMs. Basically, the thresholds are optimized for two groups of applications; off-line power supplies and DC-DC converters. The UCC3802 and UCC3804 feature typical UVLO thresholds of 12.5V for turn-on and 8.3V for turn-off, providing 4.3V of hysteresis. For low voltage inputs which include battery and 5V applications, the UCC3803 and UCC3805 turn on at 4.1V and turn off at 3.6V with 0.5V of hysteresis. The UCC3800 and UCC3801 have UVLO thresholds optimized for automotive and battery applications.
During UVLO the IC draws approximately 100 microamps of supply current. Once crossing the turnon threshold the IC supply current increases typically to about 500 microamps, over an order of magnitude lower than bipolar counterparts.
SELF BIASING, ACTIVE LOW OUTPUT
0.5
SUPPLY CURRENT
(mA)
0.1
TURN OFF
TURN ON
0 VTURN
OFF ON
SUPPLY VOLTAGE (V)
RSTART
CAUX 0.1
TO OUTPUT
Device UCC3800 UCC3801 UCC3802, 4
Flgure3 Vton 7.2 9.4 12.5
Vtoff 6.9 7.4 8.3
UCC3803, 5
4.1
3.6
Figure 2
UNDERVOLTAGE LOCKOUT
The UCC3800/1/2/3/4/5 devices feature undervoltage lockout protection circuits for controlled operation during power-up and power-down sequences. Both the supply voltage (Vee) and the reference voltage (Vref) are monitored by the UVLO circuitry. An active low, self biasing totem pole output during UVLO design is also incorporated for enhanced power switch protection.
DURING UNDERVOLTAGE LOCKOUT
The self biasing, active low clamp circuit shown eliminates the potential for problematic MOSFET turn on. As the PWM output voltage rises while in UVLO, the P device drives the larger N type switch ON which clamps the output voltage low. Power to this circuit is supplied by the externally rising gate voltage, so full protection is available regardless of the ICs supply voltage during undervoltage lockout.
9-346
APPLICATION NOTE
vcc
OUT
UCC380X
R R
U-133
0.1µF BYPASS
2v VOUT
Flgure4
VCC = OPEN
--~~--- VCC
VCC
= =
2V OV
- - - - - - VCC = 1V
Figure 6
The noninverting input to the error amplifier is tied to one-half of the PWMs reference voltage, Vref. Note that this input is 2.0V on the UCC3803 and UCC3805 and 2.SV on the higher reference voltage parts, the UCC3800, UCC3801, UCC3802 and UCC3804.
4.0V
3.9V
50mA IOUT
100mA
Figure 5
REFERENCE VOLTAGE
The traditional 5.0V amplitude bandgap reference voltage of the UC3842 family can be also found on the UCC3800,1,2 and UCC3804 devices. However, the reference voltage of the UCC3803 and UCC3805 device is 4.0 volts. This change was necessary to facilitate operation with input supply voltages below five volts. Many of the reference voltage specifications are similar to the UC3842 devices although the test conditions have been changed, indicative of lower current PWM applications. Similar to their bipolar counterparts, the BiCMOS devices internally pull the reference voltage low during UVLO which can be used as a UVLO status indication.
REFERENCE DIFFERENCES
Note that the 4V reference voltage on the UCC3803 and UCC3805 is derived from the supply voltage (Vee) and requires about O.SV of headroom to maintain regulation. Whenever Vee is below approximately 4.SV, the reference voltage also will drop outside of its specified range for normal operation. The relationship between Vee and Vref during this excursion is shown in Figure 7.
3.8V
VREF 3.7V
3.8V
3.SV ~----------3.&V 3.8V 4.0V 4.2V 4.4V 4.8V 4.8V 5.0V
VCC
Figure7
OSCILLATOR SECTION
The oscillator section of the UCC3800 through UCC3805 BiCMOS devices has few similarities to the UC3842 type - other than single pin programming. It does still utilize a resistor to the reference voltage and capacitor to ground to program the oscillator frequency up to 1 MHz. Timing component values will need to be changed since a much lower charging current is desirable for low power operation. Several characteristics of the oscillator have been optimized for high speed, noise immune operation. The oscillator peak to peak amplitude has been increased to 2.45V typical versus 1.7V on the UC 3842 family. The lower oscillator threshold has been dropped to approximately 0.2 volts while the upper threshold remains fairly close to the original 2.8 volts at approximately 2.65V.
Discharge current of the timing capacitor has been increased to nearly 20 milliamps peak as opposed
9-347
APPLICATION NOTE
U-133
plications can utilize these new ICs to a 1 MHz switching frequency.
0.1µF
1300 DISCHARGE-I
Figures to roughly BmA. As shown, this can be represented by approximately 130 ohms in series with the discharge switch to ground. A higher current was necessary to achieve brief deadtimes and high duty cycles with high frequency operation. Practical ap-
OSC WAVEFORM
SYNCHRONIZATION
Synchronization of these PWM controllers is best obtained by the universal technique shown in figure 12. The ICs oscillator is programmed to free run at a frequency about 20% lower than that of the synchronizing frequency. A brief positive pulse is applied across the resistor in series to ground with the timing capacitor to force synchronization. Typically, a one volt amplitude pulse of 100 nanoseconds width is sufficient for most applications.
The ICs can also be synchronized to a pulse train input directly to the oscillator RVCt pin. Note that the IC will internally pull low at this node once the upper oscillator threshold is crossed. This 130 ohm impedance to ground remains active until the pin is lowered to approximately 0.2 V. External synchronization circuits should accommodate these conditions.
VCT
0.2V ,..__ _ _ _ _ ____,.~-----~0 ....r - - - - - -....
f CONV
Figure9
FREQUENCY vs. RT FOR SEVERAL CT
f, KHz
1000 800 600 400
200 CT=100p
100 80 60
40
CT=180p
CT=270p CT=390p CT=470p
20-+---------~·-----i
0 20 40 60 80 100 120
RT, KOhm
Figure 10
Td, ns
DEAD TIME WITH CT
200
180
160
140
120
100
80
60
40 -+---~'-,-----~--~------,
125
250
375
500
CT, pF
Figure 11
PWM SECTION : MAXIMUM DUTY CYCLE
Maximum duty cycle is higher for these devices than for their UC3842/3/4/5 predecessors. This is primarily due to the higher ratio of timing capacitor discharge to charge current which can exceed onehundred to one in a typical BiCMOS application. Attempts to program the oscillator maximum duty cycle much below the specified range by adjusting the timing component values of Rt and Ct) should be avoided. There are two reasons to refrain from this design practice. First, the !Cs high discharge current would necessitate higher charging currents than necessary for pro-
9-348
APPLICATION NOTE
U-133
VREF RT
RT/CT
CTh
~500
=
SYNC
Jl
Figure 12
gra~ming, defeating the purpose of low power operation. Secondly, a low value timing resistor will prevent the capacitor from discharging to the lower threshold and initiating the next switching cycle.
VREF
RT/CT
Figure 13
DEADTIME CONTROL
Deadtime is the term used to describe the guaranteed OFF time of the PWM output during each oscillator cycle. It is used to insure that even at maximum duty cycle, there is enough time to reset the magnetic circuit elements, and prevent saturation.
The deadtime of the UCC380x PWM family is determined by the internal 130 Ohm discharge impedance and the timing capacitor value. Larger capacitance values extend the deadtime whereas smaller values will result in higher maximum duty cycles for the same operating frequency. A curve for deadtime versus timing capacitor values is provided below.
Increasing the deadtime is possible by adding a resistor between the Rt/Ct pin of the IC and the timing components. The deadtime increases with the discharge resistor value to about 470 Ohms as indicated from the curve. Higher resistances should be avoided as they can decrease the deadtime and reduce the oscillator peak-to-peak amplitude. Sink-
ing too much current (1 mA) by reducing Rt will "freeze" the oscillator OFF by preventing discharge to the lower comparator threshold voltage of 0.2 V.
Reducing the maximum duty cycle can be accomplished by adding a discharge resistor (below 47 Ohms) between the ICs Rt/Ct pin and the actual Rt/Ct components. Adding this discharge control resistor has several impacts on the oscillator programming. First, it introduces a DC offset to the capaci_tor during t~e _discharge - but not the charging portion of the timing cycle, thus lowering the usable peak-to-peak timing capacitor amplitude.
Because of the reduced peak-to-peak amplitude, the exact value of Ct may need to be adjusted from UC3842 type designs to obtain the correct initial oscillator frequency. One alternative is keep the same value timing capacitor and adjust both the timing and discharge resistor values since these are readily available in finer numerical increments.
MAX DUTY CYCLE VERSUS RD
100
99
98
97
96
Mu
95
·· Duty Cycle ··
92
91
80
··
250
500
750
1000
RO, Ohme
Figure 14
LEADING EDGE BLANKING
Figure 15
9-349
APPLICATION NOTE
U-133
press the switching spike associated with tum-on of the power MOSFET. This 100 nanosecond period should be adequate for most switchmode de-
signs but can be lengthened by adding an external RIC filter.
Note that the 100 ns leading edge blanking is also applied to the cycle-by-cycle current limiting function in addition to the overcurrent fault comparator.
OSCILLATOR CT
L
I
-
-
-\~~~_,./
LE AOING
EDGE BLANKING
UNBLANKED SWITCH
CURRENT
BLANKED SWITCH
CURRENT
Figure 16
MINIMUM PULSE WIDTH
The leading edge blanking circuitry can lead to a minimum pulse width equal to the blanking interval under certain conditions. This will occur when the error amplifier output voltage (minus a diode drop and divided by 1.65) is lower than the current sense input. However, the amplifier output voltage must also be higher than a diode forward voltage drop of about O.SV. It is only during these conditions that a minimum output pulse width equal to the blanking duration can be obtained.
Note that the PWM comparator has two inputs; one is from the current sense input. The other PWM input is the error amplifier output which has a diode and two resistors in series to ground. The di-
IZERO DUTY CYCLE OFFSET
E/A 0.65 R
PWM
ISNS
Figure 17
Zero duty cycle is achievable by forcing the error amplifier output below the zero duty cycle threshold of one diode voltage drop.
ode in this network is used to guarantee that zero duty cycle can be reached. Whenever the E/A output falls below a diode forward voltage drop, no current flows in the resistor divider and the PWM input goes to zero, along with pulse width.
PROTECTION CIRCUITRY: CURRENT LIMITING
A 1.0 volt (typical) cycle-by-cycle current limit threshold is incorporated into the UCC3800 family. Note that the 100 nanosecond leading edge blanking pulse is applied to this current limiting circuitry. The blanking overrides the current limit comparator output to prevent the leading edge switch noise from triggering a current limit function. Propagation delay from the current limit comparator to the output is typically 70 nanoseconds. This high speed path minimizes power semiconductor dissipation during an overload by abbreviating the on time.
CURRENT SENSE OFFSET CIRCUITRY
For increased efficiency in the current sense circuitry, the circuit shown in figure 23 can be used. Resistors R1 and R2 bias the actual current sense
resistor voltage up, allowing a small current sense
amplitude to be used. This circuitry provides current limiting protection with lower power loss current sensing.
0.1µF
VRCB·200mV AT FULL LOAD
Figure 18
The example shown uses a 200 millivolt full scale signal at the current sense resistor. Resistor Rb biases this up by approximately 700 mV to mate with the 0.9V minimum specification of the current limit comparator of the IC. The value of resistor Ra changes with the specific IC used, due to the different reference voltages. The resistor values should be selected for minimal power loss. For example, a
so uA bias sets Rb = 13k ohms, Ra=75 k ohms
(UCC3800, 1,2,4) or Ra=56k ohms with the UCC3803 and UCC3805 devices.
9-350
APPLICATION NOTE
U-133
PWM 0
VRCS 0
VISNS0 '--'---~------!~~-
Figure 19
OVERCURRENTPROTECTION AND FULL CYCLE RESTART
A separate overcurrent comparator within the UCC 3800/1/2/3/4/5 devices handles operation into a short circuited or severely overloaded power supply output. This overcurrent comparator has a 1.5 volt threshold and is also gated by the leading edge blanking signal to prevent false triggering. Once triggered, the overcurrent comparator uses the internal soft start capacitor to generate a delay before retry is attempted. Often referred to as "hiccup", this delay time is used to significantly reduce the input and dissipated power of the main converter and switching components.
Internally, the ICs overcurrent comparator triggers latched circuitry to instantly turn the PWM output off and discharge the soft start capacitor to 0.5 volts. This capacitor is then allowed to slowly charge via a current source to 4 volts while the PWM output is held low. Once the 4V threshold is reached, the soft start capacitor is again discharged and the latch is reset. This brings the
ISl!NSE
Fl
COllP
PWM back into soft start which results in normal operation with the fault removed. This entire procedure is repeated every time the overcurrent comparator detects a fault.
Low leakage transformer designs are recommended in high frequency applications to activate the overcurrent protection feature. Otherwise, the switch current may not ramp up sufficiently to trigger the overcurrent comparator within the leading edge blanking duration. This condition would cause continual cyclical triggering of the cycle-bycycle current limit comparator but not the overcurrent comparator. This would result in brief high power dissipation durations in the main converter at the switching frequency. The intent of the over-
FAULT 1.5V : · ·
SOFT STAFIT
5.0V;
1.2V ·... 0.2V ; ·
OUTPUT
Figure21
current comparator is to reduce the effective retry rate under these conditions to a few milliseconds, thus significantly lowering the short circuit power dissipation of the converter.
FB
COMP
cs
voe
OK
1.IY 8LANKIN8 OYER· CURRENT
REF/I
LEADING EDGE
-~- BLANKING
···
OK 0. SY
FULL CYCLE SOFT START
-r. Ima
PWM
TO
1-,.....:dlJC>---~~=~T
css
1V
'T · Sma
Figure20
Figure22
9-351
APPLICATION NOTE
U-133
SOFT START
Internal soft starting of the PWM output is accomplished by gradually increasing error amplifier (ElA) output voltage. When used in current mode control, this implementation slowly raises the peak
above the voltage commanded by the error amplifier for normal PWM operation.
VREF
AT/CT
0 SOFT START
0
PWM 0
!SENSE
0
RT/CT ISNS
TO MAIN SWITCH
RF
CF -J:.
RCS
Figure 23
switch current each PWM cycle in comparison, forcing a controlled start-up. In voltage mode (duty cycle) control, this feature continually widens the pulse width.
The soft start capacitor (Css) is discharged following an undervoltage lockout transition or if the reference voltage is below a minimum value for normal operation. Additionally, discharge of Css occurs whenever the overcurrent protection comparator is triggered by a fault.
Soft start is performed within the UCC3800/1/2/3/4/5 devices by clamping the E/A amplifier output to an internal soft start capacitor (Css) which is charged by a current source. The soft start clamp circuitry is overridden once Css charges
+VIN ~
I
l
Figure 24
APPLICATIONS SECTION: CURRENT MODE CONTROL
Peak current mode control is obtained by feeding the converters switch current waveform into the current sense (lsens) input of a UCC3800/1/2/3/4/5 device. The sense resistor should be selected to develop a 0.9 V peak amplitude at full load, including slope compensation. Because of the internal 100 ns typical leading edge blanking, the traditional resistor-capacitor (Rf/Cf) filter to suppress the turnon noise spike may not be needed.
SLOPE COMPENSATION
Slope compensation can be added in all current mode control applications to cancel the peak to average current error. Slope compensation is neces-
RT
FOSC=
100KHz
0.1nF
CT
c
VO
Cl
RIZ
RIP
-VIN
Figure 27
9-352
APPLICATION NOTE
U-133
STEP UP
V0~2XVIN
RT RT/CT
R1
SENS R2
GND
CT
FOUT ~ 100KHz DUTY~· 50%
~---~-·~~·___,·~--~---J~·-v_o
-VIN
r
Figure 25
sary with applications with duty cycles exceeding 50%, but also improves performance in those below 50%.
Primary current is sensed using resistor Res in series with the converter switch. A RIC filter is also required as the capacitor will be charged from both the current sense and slope compensating circuits. The timing resistor can be broken up into two series resistors to bias up the NPN follower. This is needed to provide ample compliance for slope compensation at the beginning of a switching cycle, especially with continuous current converters. A NPN voltage follower drives the slope compensating programming resistor (Rsc) to provide a slope compensating current into Cf.
VOLTAGE MODE OPERATION
Any current mode control IC can be used as a direct duty cycle control (voltage mode) by applying a sawtooth ramp to the current sense input. The exponential charging of the timing capacitor (Ct) is used as an approximation of a sawtooth. This
INVERTING VO ~-VIN +VIN ---,.-------~
VO
Figure26 shape is obtained by using a high value timing resistance (Rt) to the reference voltage (Vref). The oscillator waveform is resistively divided down by R1 and R2 to a 0.9V maximum amplitude and fed into the current sense input for duty cycle control. A small capacitor across R1 might be necessary to completely bring the current sense input to
Vm =4 . 5 Io 1 l>V
Vo
C1+
7
6
RT 40K
8
ucc
3803
3 2
4
.1
100 CT
5
pf
51 0 51 0
7 0 pf
co
R1
Figure 28 9-353
APPLICATION NOTE
U-133
LOGIC
LEVEL
VIN
FET L
l~ 1N5819
100.+
4.T~+
t
~1
9.1V
l 7
,....-
---- ~~ ,____
IN5819
~
1J
INDUCTOR
2
8 ucc u50K
20K
4 270K ~
3803 1 8
5
.01
... 1
.i:
IRC 11A2
10o'" 100K
P7
l
T
1. 3K
l~ D
2K
Vo
+co ~
Flgure29
zero volts at the beginning of each PWM cycle. Current in the divider network should be kept around 50 microamps, a compromise between low power consumption and good noise immunity. A 15K ohm and 30 K ohm are used in the example.
This circuit can also be used to program the PWM maximum duty cycle. Values should be calculated to attain the 0.9V current sense voltage at the desired maximum duty cycle.
LOW POWER DC/DC CONVERTERS CHARGE PUMP CONVERTERS
Charge pump converters are popular for simple, low power applications. The two basic applications are free running step-up and inverting switchers which use few external components as shown.
VIN
LOW POWER BUCK REGULATOR
For voltage step down applications, the UCC 380x totem pole output can be used as both the switch and commutating diode of the buck regulator. Power dissipation and the one amp peak current
rating of the ICs output stage limit the range of ap-
plications to less than 1 amp of output current. High frequency operation permits the use of small and inexpensive surface mount components.
BUCK-BOOST CONVERTER for VOLTAGE STEP-UP andfor STEP-DOWN APPLICATIONS
A two-switch buck-boost converter can be controlled by the UCC380x family of PWMs. This specific converter is useful in applications where the input voltage can be both higher and lower than the de-
L
VO
R'
t----o-------'7
2 1 - - - - - - - 1 1 - - - - - + - - + - + - - -....
100
µ,F
T
8 ucc
3803
20K
1
D
co R 1
4.7
1----' 4
6 ----ii-.
2K
0. 1
5
100pF
RCS
"'='" G.
Flgure30
9-354
APPLICATION NOTE
U-133
SIMPLIFIED TWO SWITCH BUCK/BOOST CONVERTER
+ VOUT
DRIVE SWITCHES TOGETHER sired output voltage. Implementation combines the voltage step-down characteristic of the buck regulator with the voltage step-up of the boost converter. Both switches are driven simultaneously with this adaptation to simplify the control algorithm. Note that the PWM output of the IC will be used directly for the high side switch in a low power pplication thus requiring only one external switch. Also, the body diode of the lower side totem-pole output is used as one of the commutating rectifiers, further reducing complexity. As shown, this approach is ideal for low voltage, low power DC to DC applications. Higher voltage and higher power applications will require the use of discrete semiconductors for the high side switch and lower diode. Duty cycle is varied with input line voltage to provide a regulated output. A curve is provided to demonstrate the ideal converter voltage gain as a function of duty cycle. This non isolated buck-boost
ucc
380X
+ VOUT
converter can be operated in either the discontinuous and continuous inductor current modes. High frequency switching permits the use of very small and inexpensive surface mount inductors for most low power applications. The converter can be controlled by duty cycle modulation (voltage mode) or current mode control, and with or without overcurrent protection.
BOOST CONVERTERS
The UCC 3803 and UCC 3805 devices are fully operational from a 4.5 volt input supply and are ideally suited for 5VDC and battery input PWM boost converter applications. MOSFETs featuring "logic level" gate thresholds are the most likely candidates for the PWM switch as opposed to using standard devices which typically require a gate voltage near 12 volts to be fully on. Currently, many popular N channel MOSFETs are available with logic level gate inputs as an option. Note that many logic level FETs have maximum gate voltage ratings of +/- 10V as opposed to+/- 20V for most conventional FETs which limits their application. Also note that the UCC 380x devices will require a current limited supply when used above 12 volts from a low impedance source.
A basic current mode controlled boost converter application circuit is shown. Typical component values for 250 kHz operation are listed in the following tables for a 12V and 24V output applications. The boost converter design equations are summarized below.
BOOST DESIGN SUMMARY:
(Discontinuous inductor current)
Voutd'inx(~~~~~ +1)
(~~~ fin= loutx
+ 1 )
lp=
2
x
/m. x
,l(perio(/
t .",on)
1 _ 2 x If.period) x loutx (((,on)+ !(_off))
P-
[l(_on) x ((,off)]
where t(period) F(sw~tchiny
L _ Vout minus Vin (min) x ((,off)]
-
Ip
C out (lpx t (of~ mm<) 2x dVout
ESR (mm<)= dVout Ip
9-355
APPLICATION NOTE
U-133
BOOST CONVERTER DESIGN TABLE 1
VIN= 4.5 to 10 voe
VOUT= 12VDC IOUT = 0.2, 0.4, 1 ADC DISCONTINUOUS I MODE F(SWITCHING) = 250kHz
POUT
3W
6W
12W
01
3A/40V 3A/40V 6A/45V
1N5819 1N5822 6TQ045
L
12uH
6.8uH
1.8uH
PCH-(1) 27-123 27-682 27-182
Cout (2) 100uF
300uF
500uF
Rcs(ohm) 0.1
0.05
0.033
01* (3)
2A/50V IRLZ14 RFL2N05L
IRLZ14
NOTE 1: Coilcraft inductor part number. NOTE 2: Cout must be low ESR and ESL. NOTE 3: MOSFET ratings and part number.
LOGIC LEVEL gate threshold.
TABLE2
VIN= 4.5 to 10 voe
VOUT=24VDC IOUT = 0.1, 0.2, 0.5 ADC DISCONTINUOUS I MODE F(SWITCHING) = 250kHz
POUT
3W
6W
12W
01
3A/40V 3A/40V 6A/45V
1N5819 1N5822 6TQ045
L
12uH
6.8uH
3.9uH
PCH-(1) 27-123 27-682 27-392
Cout (2) 100uF
200uF
500uF
Rcs(ohm) 0.1
0.05
0.033
01* (3)
2A/50V 8A/50V RFL2N05L IRLZ14
IRLZ14
NOTE 1: Coilcraft inductor part number. NOTE 2: Cout must be low ESR and ESL. NOTE 3: MOSFET ratings and part number.
LOGIC LEVEL gate threshold.
TABLE3
VIN= 10to18 voe
VOUT=24VDC IOUT= 0.1, 0.2, 0.5ADC DISCONTINUOUS I MODE F(SWITCHING) = 250kHz
POUT
3W
6W
12W
01
1A/40V 3A/40V 6A/45V
1N5819 1N5822 6TQ045
L
22uH
12uH
3.9uH
PCH-(1) 27-223 27-123 27-392
Cout (2) 100uF
200uF
500uF
Rcs(ohm) 0.2
0.1
0.066
01* (3)
3A/60V 3A/60V IRFF133 IRFF113 IRFF113
NOTE 1: Coilcraft inductor part number. NOTE 2: Cout must be low ESR and ESL. NOTE 3: MOSFET ratings and part number.
LOGIC LEVEL gate threshold.
BUCK REGULATOR
The buck regulator is a more difficult design challenge than the boost converter due to the high side switch. A transformer coupled gate drive is typically required to deliver drive pulses to the switch, which requires about ten volts above the input voltage for proper drive. Current mode control further complicates the design by requiring a current transformer to level shift the high side current sense signal down to the ground based input of the IC. In many applications, direct duty cycle control (voltage mode) can be used to simplify the design although overcurrent protection is lost with common ground applications.
Several examples of common buck regulator application circuits are shown below. Direct duty cycle control is used for simplicity, however current mode control can be easily adapted as shown in the example. Tables listing component values and typical part numbers have been included.
9-356
APPLICATION NOTE
U-133
DESIGN EQUATIONS:
Vout = Vin · D (duty cycle) _ T(on)
where D- T(pen.od)
L==Voutx t (off) dlo
where: Delta lo is the inductor ripple current and equal to one-half of the minimum output current. Minimum output current has been selected as 10% of the full load current
/pk= lo+d2l-o
lin(DC) = lout · D
Gout==
d 10
(8xFxdVouf)
where F is the switching frequency and A Vout is the output ripple voltage
BUCK REGULATOR DESIGN TABLES
TABLE4
VIN= 4.S to 10 VDC VOUT = 3.3 VDC IOUT = 1, 3 and S ADC CONTINUOUS I MODE F(SWITCHING) = 2SOkHz lout(min) = lout(max)/10
TABLE 5 VIN = 10 to 18 VDC VOUT= SVDC IOUT = 1, 3 and S ADC CONTINUOUS I MODE F(SWITCHING) = 2SOkHz lout(min) = lout(max)/10
IOUT
1A
3A
SA
D1
3N40V 3N40V 12N40V
1NS822 1NS822 12T004S
L PCH-(1)
120uH 27-1243
39uH 45-393
22uH 45-223
Gout (2) 2uF
SuF
10uF
01* (3)
4N50V 8NSOV 12N50V IRF9Z12 IRF9Z22 IRF9Z30
NOTE 1: Coilcraft inductor part number. NOTE 2: Gout must be low ESR and ESL. NOTE 3: MOSFET ratings and part number.
LOGIC LEVEL gate threshold.
TABLES VIN = 10 to 18 VDC VOUT= 9VDC IOUT = 1, 3, S ADC
IOUT D1
L PCH-(1)
1A
3N20V 1NS820
39uH
27-393
3A
SA
12N4SV 12N4SV 12T004S 12TQ045
22uH
6.8uH
4S-223
4S-682
IOUT D1
L PCH-(1)
1A
3N40V 1NS822
39uH
27-293
3A
3N40V 1NS822
12uH
27-123
SA
12N40V 12TQ04S
6.9uH
27-682
Gout (2) 2uF
4.7uF
10uF
01. (3)
8N60V IRLZ14
8N60V IRLZ14
IRLZ14
NOTE 1: Coilcraft inductor part number. NOTE 2: Gout must be low ESR and ESL. NOTE 3: MOSFET ratings and part number.
LOGIC LEVEL gate threshold.
Gout (2) 1uF
3uF
SuF
01. (3)
4NSOV 8NSOV 12NSOV IRF9Z12 IRF9Z22 IRF9Z30
NOTE 1: Coilcraft inductor part number. NOTE 2: Gout must be low ESR and ESL. NOTE 3: MOSFET ratings and part number.
LOGIC LEVEL gate threshold.
9-357
APPLICATION NOTE
U-133
OFF-LINE APPLICATIONS: FORWARD AND FLVBACK CONVERTERS
Several benefits can be realized in off-line applications by using the low current, UC380x BiCMOS PWM controllers. First, the IC can be powered from a resistor to the rectified input voltage source, eliminating the bootstrap winding. This applies to most low frequency applications ( 50kHz) where the DC supply current required for the gate drive is
low. Soft start of the power supply and delayed re-
start following a fault requires no external parts.
~11ff "'f:
OUT ISNS
Flgure31
UCC380X OTHER APPLICATIONS: UNIVERSAL SYNC GENERATOR
The UCC3803 can be used as a synchronization (SYNC) pulse generator and driver for a variety of applications. Basically, one circuit shown uses the leading edge blanking duration as the SYNC output pulse width. The current limit input is biased at 1.25 volts to terminate the output pulse immediately after the ICs internal blanking pulse width. The oscillator is resistively programmed to a DC
5V
SLAVE1
13K
SYNC INPUT (TTL)
7
8
ucc
3803 8 .....1.Weolrn_
CT __,
son
The internal leading edge blanking eliminates filtering of the current sense signal. Also, the ICs undervoltage lockout thresholds, internal Vee shunt regulator and active low totem pole output eliminate any problematic gate drive operation.
The basic schematic of a forward converter is shown in figure 31, and a flyback is shown in figure 32. In each, the UCC3804 limits the maximum duty cycle to 50% by internal logic, allowing time for the main transformer to reset. Applications which util-
ucc
·
+
380X
11
OUT ISNS
Flgure32
ize higher maximum duty cycles, for example 65%, should use the UCC 3802 device without the internal toggle flip flop.
TO ADDITIONAL
SLAVES
SLAVE2
CT
180n son
Flgure33
level of 1.25 volts also, midway between its upper and lower thresholds. When a TIL compatible SYNC pulse is injected, the amplitude at the oscillator input is raised above its upper threshold. This turns on the internal discharge circuitry which pulls the pin to about 0.2 volts, crossing the lower oscillator threshold. Once this occurs, the discharge transistor is turned off and the ICs output is turned on, generating the SYNC pulse. Note that the current sense input is biased to turn the ICs output off following the leading edge blanking duration, which is used to program the SYNC output pulse width. This 100 nanosecond duration is ideal for synchronizing most PWMs used today with the technique shown.
This circuit can be adapted to generate other width pulses with minor modifications. A capacitor can be added across the lower resistor in the divider network to the current sense input for extending the pulse width. Note that the voltage must be limited below 1.4 volts or a full cycle soft start will be incurred. Also, this capacitor must be discharged before the beginning of each pulse for proper timing
9-358
APPLICATION NOTE
U-133
APPROX 12 VDC
::.::
.I..',-.
]II
R1
::.::
7 5V
ucc 6
110 VAC
~ R2
380X 8 2
::.::
0
PRI 12 VAC
~
RT
SEC.
ir~ ::.::
R4
3
4
I s I SELECT
1RF
D
C1 ~
FOR 1V
11A2
MAXIMUM
RESET
PROGRAMMABLE CURRENT ADJUST
Figure 34
to occur. One recommendation is to diode couple the current sense input to the oscillator Rt'Ct pin. External circuits can also be used for more precise programming.
per oscillator threshold of approximately 2.7 volts. The VFO current source can be generated by an external op-amp for general purpose applications as shown.
SYNC IN
RT/CT
OUTPUT
EXTERNAL OPAMP
ucc
380X
RT T >.---J\/V'V-----r----t
IC
SLAVES . CT .
Figure 35
VFO APPLICATIONS
Members of the UCC380x family of devices are adaptable for use in variable frequency applications. The most direct means of accomplishing this is to vary the charging current to the oscillator timing capacitor. Note that the minimum compliance voltage of the current source must exceed the up-
Figure 36
Some VFO applications can utilize the ICs internal error amplifier to vary the frequency over a programmed minimum and maximum frequency range. This is done by programming the minimum frequency by a resistor to Vref. Another current sink/source is formed by a resistor to the E/A output. This arrangement performs frequency modulation as the E/A output voltage is varied. Applications which require a fixed 50% duty cycle at varying frequencies, electronic ballasts, for ex-
9-359
APPLICATION NOTE
U-133
VFO INPUT (0-5V)
75K
VREF
ucc
RT
380X
E/A-
100K R'
COMP
RT/CT
_I_CT~----
FULL DUTY CYCLE APPLICATIONS
Any of the UCC380x PWM controllers can be used at full (100%) duty cycle. This mode of operation may be required in certain applications, including DC switch drivers. Implementation requires ''freezing" the oscillator so that the output stays high until it is time to turn off. Switch 01 insures that the PWM output is high when switch 02 is activated to stop the oscillator. Current limiting can still be ac-
Flgure37
ample, should use the UCC3804 or UCC3805 devices. Output frequency from these will be one-half of the ICs oscillator due to the internal divide-bytwo gating circuitry.
FIXED OFF-TIME APPLICATIONS
Obtaining a fixed off-time, variable on-time control technique is easily implemented with the UCC380x family. The oscillator Rt/Ct timing components are used to generate the off-time rather than the oper-
RT Figure 39
FULL DUTY CYCLE INPUT HI= ON
complished by using the current sense feature of the IC, in addition to modulating the peak current via the error amplifier.
HIGH SPEED, PROGRAMABLE ELECTRONIC CIRCUIT BREAKER
Figure38
ating frequency. Implementation is shown in the corresponding figure.
A high speed, programmable electronic circuit breaker can be built using the UCC380x family to perform the control and MOSFET drive functions. Basically, back-to-back power MOSFETS are used as the switching element although an SCR, TRIAC or bipolar switch can also be used. The MOSFETS are connected with the sources tied together to simplify the gate drive while providing a blocking path to current in either direction. Current limiting for an AC supply requires a current transformer, also shown, which can be simplified to a resistor for use in DC input applications. The current sense input to the IC can either be biased up for lower power loss in the current sense network, or programmed by adjusting the error amplifier output voltage to yield a similar result.
9-360
APPLICATION NOTE
U-133
SWITCHING COMPONENT NOTES: P CHANNEL MOSFET SWITCHES
Logic level P channel MOSFETs are unavailable today which limits their applications to those with input voltages greater than about ten volts for proper gate drive. The P channel switch will also require a small N channel device to invert its gate drive command, due to the active high output of the PWM. High speed PNP transistors are also a suitable choice for some applications.
N CHANNEL MOSFET SWITCHES
Proper gate drive for N channel switches will require a supply voltage which is several volts above the input voltage. This is not a problem in five volt input applications using logic level FETs if a nine volt (or higher) supply is also available. If not, one option is to construct a very low power boost converter to generate the nine volt supply to power the IC and gate drive. The boost converter switch can be driven from the UCC380x output which is switching the main output. Small, inexpensive surface mount inductors, switches and diodes are readily available. Another possibility is to build a charge pump circuit driven from the PWM output as shown, provided that only a few volts of headroom are required.
GATE DRIVE TRANSFORMER
Higher input voltage applications will require a gate drive transformer due to 12 volt maximum supply rating of the UCC 380x IC family. A small ferrite toroid with two windings and minimal insulation is typically used. A capacitor is placed in series with the primary and is needed for proper reset of the core. The DC offset introduced by the capacitor will effect the primary to secondary turns ratio of the transformer which is dependant on the application. A PULSE Engineering (phone 619-268-2400) model PE-64973 can be employed in a most Buck regulator designs.
CURRENT SENSE TRANSFORMER
A current sense transformer is required in the buck regulator application for current mode control. This transformer is used to level shift the current signal from the high side input supply to the ground referenced PWM circuitry. A high turns ratio should be incorporated to reduce power dissipation. Parasitic noise can be minimized by inserting the trans-
former in series with the drain of the power switch as opposed to its source. A PULSE Engineering (phone 619-268-2400) model PE-64978 current transformer with a one turn primary and 50 turn secondary can be used in most applications.
ADDITIONAL INFORMATION
1. UNITRODE Application Note U-1 OOA; ·The UC3842/3i4/5 Series of Current Mode PWM ICs" :
· UC3842/3/4/5 PWMs · Applications Information
2. UNITRODE Application Note U-111; " Practical Considerations in Current Mode Power Supplies" ;
· Fixed OFF-Time Implementation · Full Duty Cycle · Paralleling Power Supplies · Shutdown Techniques · Slope Compensation (implementation) · Soft Start · Synchronization · Variable Frequency Operation · Voltage Mode Operation
3. UNITRODE Application Note U-96A "A 25 Watt Off-Line Flyback Switching Regulator'':
· Flyback Converter Design
4. UNITRODE Application Note U-97 "Modelling, Analysis and Compensation of the Current Mode Converter "
· Current Mode Control · Slope Compensation
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. · MERRIMACK, NH 03054 TEL. 603-424·2410 · FAX 603-424-3460
9-361
n nINTEGRATED
~ CIRCUITB
-UNITRODE
APPLICATION NOTE
U-134
UC3854 Controlled Power Factor Correction Circuit Design
PHILIP C. TODD
ABSTRACT This Application Note describes the concepts and design of a boost preregulator for power factor co"ection. This note covers the important specifications for power factor co"ection, the boost power circuit design and the UC3854 integrated circuit which controls the converter. A complete design procedure is given which includes the tradeoffs necessary in the process. This design procedure is directly applicable to the UC3854AIB as well as the UC3854. The recommendations in Unitrode Design Note DN-39 cover other areas of the circuit and, while not discussed here, must be considered in any design. This application note supersedes Application Note U-125 "Power Factor Correction With the UC3854."
INTRODUCTION
The objective of active power factor correction is to make the input to a power supply look like a simple resistor. An active power factor corrector does this by programming the input current in response to the input voltage. As long as the ratio between the voltage and current is a constant the input will be resistive and the power factor will be 1.0. When the ratio deviates from a constant the input will contain phase displacement, harmonic distortion or both and either one will degrade the power factor.
The most general definition of power factor is the ratio of real power to apparent power. ·
PF
p
or PF= Watts
( Vrms x lrms)
V.A.
Where P is the real input power and Vrrns and lrms are the root mean square (RMS) voltage and current of the load, or power factor corrector input in this case. If the load is a pure resistance the real power and the product of the RMS voltage and current will be the same and the power factor will be 1.0. If the load is not a pure resistance the power factor will be below 1.0.
Phase displacement is a measure of the reactance of the input impedance of the active power factor corrector. Any amount of reactance, either inductive or capacitive will cause phase displacement of
the input current waveform with respect to the input voltage waveform. The phase displacement of the voltage and current is the classic definition of power factor which is the cosine of the phase angle between the voltage and current sinusoids.
PF=Cos 9
The amount of displacement between the voltage and current indicates the degree to which the load is reactive. If the reactance is a small part of the impedance the phase displacement will be small. An active power factor corrector will generate phase displacement of the input current if there is phase shift in the feedforward signals or in the control loops. Any filtering of the AC line current will also produce phase displacement.
Harmonic distortion is a measure of the non-linearity of the input impedance of the active power factor corrector. Any variation of the input impedance as a function of the input voltage will cause distortion of the input current and this distortion is the other contributor to poor power factor. Distortion increases the RMS value of the current without increasing the total power being drawn. A non-linear load will therefore have a poor power factor because the RMS value of the current is high but the total power delivered is small. If the non-linearity is small the harmonic distortion will be low. Distortion in an active power factor corrector comes from
9-362
APPLICATION NOTE
U-134
Power Factor Versus Distortion
0.995
.l;
0
u..
:.
0.99
II
0
II..
0.985
0.98 0
N
Total Harmonic Distortion, In Percent
Power Factor Versus Distortion
I
i
a. ·········-l!:·········-Iii··········i!r········· . -·····1!i···---:i!·-·····+!I ·-..···-IIr·-······+ll ·········
(5 O.
·········ti ·······jI···------i1-·--·-.··t·····-·ii···-·
!
I
I
i
-~---·····-t-···-····i······--·t·--·······
i i
i Ii !i I I I I
o.94 ·-·-··t·-·····1·········1··-·-·t·······1········t········! ··-·t·······t·········
Q.
a.
-·-·······lt·········t!···--·····t!··········t!····-····1!·..·-···-rl-·-·····t!·····-··1.--·-
!
--·-r·--·······
I I I I 0. ·····-·---~ J_ ______ ------t---·- ---~---------1---------~----------l---------l--------}------ -
i ;
1
l
10 15 20 25 30 35 40 45 50 Total Harmonic Distortion, in Percent
Harmonic Order
Permissible current
n
3 5 7 9 11 13 15 up
mA/W Odd harmonics
3.4 1.9 1.0 0.5 0.35 0.3 3.85/n
Even harmonics
2
1.8
4
0.7
6
0.5
>8
~
n
Maximum permissible
current
A
2.30
1.14
0.78
0.40
0.33
0.21
0.15
x
15 n
1.08
0.42
0.30 1.80
n
Table 1
several sources: the feedforward signals, the feedback loops, the output capacitor, the inductor and the input rectifiers. An active power factor corrector can easily achieve
a high input power factor, usually much greater than 0.9. But power factor is not a sensitive measure of the distortion or the displacement of the current waveform. It is often more convenient to deal with these quantities directly rather than with the power factor. For example, 3% harmonic distortion alone has a power factor of 0.999. A current with 30% total harmonic distortion still has a power factor of 0.95. A current with a phase displacement of 25 degrees from the voltage has a power factor of 0.90.
The trend among the world standards organizations responsible for power quality is to specify maximum limits for the amount of current allowed at each of the harmonics of the line frequency. IEC 555-2 specifies each harmonic up through and beyond the 15th and the amount of current permissible at each. Table 1 lists the requirements for IEC 555-2 as of the time of this writing. There are two parts to the specification, a relative distortion and an absolute distortion maximum. Both limits apply to all equipment. This table is included here as an example of a line distortion specification. It is not intended to be used for design purposes. The IEC has not finalized the requirements of IEC 555 at this time and major changes are possible.
Active Power Factor Correction
A boost regulator is an excellent choice for the power stage of an active power factor corrector because the input current is continuous and this produces the lowest level of conducted noise and the best input current waveform. The disadvantage of the boost regulator is the high output voltage required. The output voltage must be greater than the highest expected peak input voltage.
The boost regulator input current must be forced or programmed to be proportional to the input voltage waveform for power factor correction. Feedback is necessary to control the input current and either
9-363
APPLICATION NOTE
Vo
L
D
Co
Rs
U-134
Figure 1
Basic Configuration of High Power Factor Control Circuit
peak current mode control or average current mode control may be used. Both techniques may be implemented with the UC3854. Peak current mode control has a low gain, wide bandwidth current loop which generally makes it unsuitable for a high performance power factor corrector since there is a significant error between the programming signal and the current. This will produce distortion and a poor power factor.
Average current mode control is based on a simple
concept. An amplifier is used in the feedback loop around the boost power stage so that input current tracks the programming signal with very little error. This is the advantage of average current mode " control and it is what makes active power factor correction possible. Average current mode control is relatively easy to implement and is the method described here.
A block diagram of a boost power factor corrector circuit is shown in Figure 1. The power circuit of a
VjnJ\A_ .
1in
~ -, ,,,,-
o
ichg_~·lchg
'
0
Figure 2. Preregulator Waveforms 9-364
APPLICATION NOTE
U-134
boost power factor corrector is the same as that of a de to de boost converter. There is a diode bridge ahead of the inductor to rectify the AC input voltage but the large input capacitor which would normally be associated with the AC to DC conversion function has been moved to the output of the boost converter. If a capacitor follows the input diode bridge it is a small one used only for noise control.
The output of the boost regulator is a constant voltage but the input current is programmed by the input voltage to be a half sine wave. The power flow
Control Circuits
An active power factor corrector must control both the input current and the output voltage. The current loop is programmed by the rectified line voltage so that the input to the converter will appear to be resistive. The output voltage is controlled by changing the average amplitude of the current programming signal. An analog multiplier creates the current programming signal by multiplying the rectified line voltage with the output of the voltage er-
IVW!n HIGH POWER I y \ hn FACTOR .----....--....-iSWITCHING
PREREGULATOR
M Imo
lch
Vo lo
Co
Rvc
DIV
KJ
Rvd
Figure 3. High Power Factor
into the output capacitor is not constant but is a sine wave at twice the line frequency since power is the instantaneous product of voltage an current. This is shown in Figure 2. The top waveform shows the voltage and the current into the power factor corrector and the second waveform shows the flow of energy into and out of the output capacitor. The output capacitor stores energy when the input voltage is high and releases the energy when the input voltage is low to maintain the output power flow. The third waveform in Figure 2 shows the charging and discharging current. This current has a different shape from the input current and is almost entirely at the second harmonic of the AC line voltage. This flow of energy into and out of the capacitor results in ripple voltage at the second harmonic also and this is shown in the fourth waveform in Figure 2. Note that the voltage ripple is displaced by 90 degrees relative to the current since this is reactive energy storage. The output capacitor must be rated to handle the second harmonic ripple current as well as the high frequency ripple current from the boost converter switch which modulates it.
ror amplifier so that the current programming signal has the shape of the input voltage and an average amplitude which controls the output voltage. Figure 3 is a block diagram which shows the basic control circuit arrangement necessary for an active power factor corrector. The output of the multiplier is the current programming signal and is called Imo for multiplier output current. The multiplier input from the rectified line voltage is shown as a current in Figure 3 rather than as a voltage signal because this is the way it is done in the UC3854.
Figure 3 shows a squarer and a divider as well as a multiplier in the voltage loop. The output of the voltage error amplifier is divided by the square of the average input voltage before it is multiplied by the rectified input voltage signal. This extra circuitry keeps the gain of the voltage loop constant, without it the gain of the voltage loop would change as the square of the average input voltage. The average value of the input voltage is called the feedforward voltage or Vff since it provides an open loop correction which is fed forward into the voltage loop. It is squared and then divided into the voltage error amplifier output voltage (Vvea).
9-365
APPLICATION NOTE
U-134
The current programming signal must match the rectified line voltage as closely as possible to maximize the power factor. If the voltage loop bandwidth were large it would modulate the input current to keep the output voltage constant and this would distort the input current horribly. Therefore the voltage loop bandwidth must be less than the input line frequency. But the output voltage transient response must be fast so the voltage loop bandwidth must be made as large as possible. The squarer and divider circuits keep the loop gain constant so the bandwidth can be as close as possible to the line frequency to minimize the transient response of the output voltage. This is especially important for wide input voltage ranges.
The circuits which keep the loop gain constant make the output of the voltage error amplifier a power control. The output of the voltage error amplifier actually controls the power delivered to the load. This can be seen easily from an example. If the output of the voltage error amplifier is constant and the input voltage is doubled the programming signal will double but it will be divided by the square of the feedforward voltage, or four times the input, which will result in the input current being reduced to half its original value. Twice the input voltage times half the input current results in the same input power as before. The output of the voltage error amplifier, then, controls the input power level of the power factor corrector. This can be used to limit the maximum power which the circuit can draw from the power line. If the output of the voltage error amplifier is clamped at some value that corresponds to some maximum power level, then the active power factor corrector will not draw more than that amount of power from the line as long as the input voltage is within its range.
Input Distortion Sources
The control circuits introduce both distortion and displacement into the input current waveform. These errors come from the input diode bridge, the multiplier circuits and ripple voltage, both on the output and on the feedforward voltage.
There are two modulation processes in an active power factor corrector. The first is the input diode bridge and the second is the multiplier, divider, squarer circuit. Each modulation process generates cross products, harmonics or sidebands between the two inputs. The description of these mathematically can be quite complex. Interestingly enough, however, the two modulators interact and one becomes a demodulator for the other so that the result is quite simple. As shown later, virtually all of the ripple voltages in an active power factor corrector are at the second harmonic of the line frequency. When these voltages go through the
multiplier and get programmed into the input current and then go through the input diode bridge the second harmonic volt1;1ge amplitude results in two frequency components. One is at the third harmonic of the line frequency and the other is at the fundamental. Both of these components have an amplitude which is half ·of the amplitude of the original second harmonic voltage. They also have the same phase as the original second harmonic. If the ripple voltage is 10% of the line voltage amplitude and is phase shifted 90 degrees the input current will have a third harmonic which is 5% of the fundamental and is shifted 90 degrees and a fundamental component which is 5% of the line current and is displaced by 90 degrees.
The feedforward voltage comes from the rectified AC line which has a second harmonic component that is 66% of the amplitude of the average value. The filter capacitors of the feedforward voltage divider greatly attenuate the second harmonic and effectively remove all of the higher harmonics but some of the second harmonic is still present at the feedforward input. This ripple voltage is squared by the control circuits as shown in Figure 3. This doubles the amplitude of the ripple since it is riding on top of a large DC value. The divider process is transparent to the ripple voltage so it passes on to the multiplier and eventually becomes third harmonic distortion of the input current and a phase displacement. The doubling action of the squarer means that the amplitude of the input current distortion in percent is the same as the amplitude of the ripple voltage, in percent, at the feedforward input.
Needless to say, the feedforward ripple voltage must be kept small to achieve a low distortion input current. The ripple voltage could be made small with a single pole filter with a very low cutoff frequency. However, fast response to changes of the input voltage is also desirable so the response time of the filter must be fast. These two requirements are, of course, in conflict and a compromise must be found. A two pole filter on the feedforward input has a faster transient response than a single pole filter for the same amount of ripple attenuation. Another advantage of the two pole filter has is that the phase shift is twice that of the single pole filter. This results in 180 degrees of phase shift of the second harmonic and brings both the resulting third harmonic and the displacement component of the input current back in phase with the voltage. A second harmonic ripple voltage of 3% at the feedforward input results in a 0.97 power factor just from the displacement component if a single pole filter is used for the feedforward voltage. With a two pole filter there is no displacement component to the power factor because it is in
9-366
APPLICATION NOTE
U-134
phase with the input current. The third harmonic component of the input current resulting from the second harmonic at the feedforward input will have the same amplitude as the second harmonic ripple voltage. If 3% second harmonic is present on the feedforward voltage the line current waveform will contain 3% third harmonic distortion.
The output voltage has ripple at the second harmonic due to the ripple current flowing through the output capacitor. This ripple voltage is fed back through the voltage error amplifier to the multiplier and, like the feedforward voltage, programs the input current and results in second harmonic distortion of the input current. Since this ripple voltage does not go through the squarer the amplitude of the distortion and displacement are each half of the amplitude of the ripple voltage. The ripple voltage at the output of the voltage error amplifier must be in phase with the line voltage for the displacement component to be in phase. The voltage error am· plifier must shift the second harmonic by 90 degrees so that it will be in phase with the line voltage.
reference current
0
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Figure 4. Cusp Distortion
The voltage loop of a boost converter with average current mode control has a control to output transfer function which has a single pole roll off characteristic so it could be compensated with a flat gain error amplifier. This produces a very stable loop with 90 degrees of phase margin. However, it provides less than optimum performance. The ripple voltage on the output capacitor is out of phase with the input current by 90 degrees. If the error ampli· tier has flat gain at the second harmonic frequency the distortion and displacement generated in the input current will be 90 degrees out of phase with the rectified AC line. The power factor can be im· proved by introducing phase shift into the voltage error amplifier response. This shifts the displacement component of the power factor back into alignment with the input voltage and increases the power factor. The amount of phase shift which can be added is determined by the need to keep the
voltage loop stable. If the phase margin is reduced to 45 degrees the phase at the second harmonic will be very close to 90 degrees and this brings the displacement component back in phase with the input voltage.
The bandwidth of the voltage control loop is determined by the amount of input distortion to be contributed by the output ripple voltage. If the output capacitor is small and the distortion must be low then the bandwidth of the loop will be low so that the ripple voltage will be sufficiently attenuated by the error amplifier. Transient response is a function of the loop bandwidth and the lower the bandwidth the slower the transient response and the greater the overshoot. The output capacitor may need to be large to have both fast output transient response and low input current distortion.
The technique used to design the loop compensation is to find the amount of attenuation of the output ripple voltage required in the error amplifier and then work back into the unity gain frequency. The loop will have the maximum bandwidth when the phase margin is the smallest. A45 degree phase margin is a good compromise which will give good loop stability and fast transient response and which is easy to design. The voltage error amplifier response which results will have flat gain up to the loop unity gain frequency and will have a single pole roll off above that frequency. This gives the maximum amount of attenuation at the second harmonic of the line frequency from a simple circuit, gives the greatest bandwidth and provides a 45 degree phase margin.
Cusp Distortion
Cusp distortion occurs just after the AC line input has crossed zero volts. At this point the amount of current which is required by the programming signal exceeds the available current slew rate. When the input voltage is near zero there is very little voltage across the inductor when the switch is closed so the current cannot ramp up very quickly so the available slew rate is too low and the input current will lag behind the desired value for a short period of time. Once the input current matches the programmed value the control loop is back in operation and the input current will follow the programming signal. The length of time that the current does not track the programmed value is a function of the inductor value. The smaller the inductor value the better the tracking and the lower the distortion but the smaller inductor value will have higher ripple current. The amount of distortion generated by this condition is generally small and is mostly higher order harmonics. This problem is minimized by a sufficiently high switching frequency.
9-367
APPLICATION NOTE
U-134
UC3854 Block Diagram
A block diagram of the UC3854 is shown in Figure 5 and is the same as the one in the device data sheet. This integrated circuit contains the circuits necessary to control a power factor corrector. The UC3854 is designed to implement average current mode control but is flexible enough to be used for a wide variety of power topologies and control methods.
The top left corner of Figure 5 contains the under voltage lock out comparator and the enable comparator. The output of both of these comparators must be true to allow the device to operate. The inverting input to the voltage error amplifier is connected to pin 11 and is called Vsens. The diodes shown around the voltage error amplifier are intended to represent the functioning of the internal circuits rather than to show the actual devices. The diodes shown in the block diagram are ideal diodes and indicate that the non-inverting input to the error amplifier is connected to the 7.5Vdc reference voltage under normal operation but is also used for the slow start function. This configuration lets the voltage control loop begin operation before the output voltage has reached its operating point and eliminates the turn-on overshoot which plagues many power supplies. The diode shown between pin 11 and the inverting input of the error amplifier is also .an ideal diode and is shown to eliminate confusion about whether there 1ight be an extra diode drop added to the reference or not. In the actual device we do it with differential amplifiers. An internal current source is also provided for charging the slow start timing capacitor.
The output of the voltage error amplifier, Vvea, is available on pin 7 of the UC3854 and it is also an
VVEA
MULT OUT
input to the multiplier. The other input to the multiplier is pin 6, lac, and this is the input for the programming wave shape from the input rectifiers. This pin is held at 6.0 volts and is a current input. The feedforward input, Vff, is pin 8 and its value is squared before being fed into the divider input of the multiplier. The· lset current from pin 12 is also used in the multiplier to limit the maximum output current. The output current of the multiplier is Imo and it flows out of pin 5 which is also connected to the non-inverting input of the current error amplifier.
The inverting input of the current amplifier is connected to pin 4, the lsens pin. The output of the current error amplifier connects to the pulse width modulation (PWM) comparator where it is compared to the oscillator ramp on pin 14. The oscillator and the comparator drive the set-reset flip-flop which, in turn, drives the high current output on pin 16. The output voltage is clamped internally to the UC3854 at 15 volts so that power MOSFETs will not have their gates over driven. An emergency peak current limit is provided on pin 2 and it will shut the output pulse off when it is pulled slightly below ground. The reference voltage output is connected to pin 9 and the input voltage is connected to pin 15.
DESIGN PROCESS
Power Stage Design
This analysis of the power stage design makes use of a 250W boost converter as an example. The control circuit for a boost power factor corrector does not change much with the power level of the converter. A 5000 watt power factor corrector will have almost the same control circuits as a 50 watt
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9-368
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APPLICATION NOTE
U-134
corrector. The power stage will be different but the design process will remain the same for all power factor corrector circuits. Since the design process is the same and the power stage is scalable a 250 watt corrector serves well as an example and it can be readily scaled to higher or lower output levels. Figure 6 is the schematic diagram of the circuit. Please refer to this schematic in the discussion of the design process which follows.
Specifications
The design process starts with the specifications for the converter performance. The minimum and maximum line voltage, the maximum output power, and the input line frequency range must be specified. For the example circuit the specifications are:
Maximum power output: 250W
Input voltage range: 80-270Vac
Line frequency range: 47-65Hz
This defines a power supply which will operate almost anywhere in the world. The output voltage of a boost regulator must be greater than the peak of the maximum input voltage and a value 5% to 10% higher than the maximum input voltage is recommended so the output voltage is chosen to be 400Vdc.
Switching Frequency
The choice of switching frequency is generally somewhat arbitrary. The switching frequency must be high enough to make the power circuits small and minimize the distortion and must be low enough to keep the efficiency high. In most applications a switching frequency in the range of 20KHz to 300KHz proves to be an acceptable compromise. The example converter uses a switching frequency of 1OOKHz as a compromise between size and efficiency. The value of the inductor will be reasonably small and cusp distortion will be minimized, the inductor will be physically small and the loss due to the output diode will not be excessive. Converters operating at higher power levels may find that a lower switching frequency is desirable to minimize the power losses. Turn-on snubbers for the switch will reduce the switching losses and can be very effective in allowing a converter to operate at high switching frequency with very high efficiency.
Inductor Selection
The inductor determines the amount of high frequency ripple current in the input and its value is chosen to give some specific value of ripple current. Inductor value selection begins with the peak
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Figure7
9-370
APPLICATION NOTE
U-134
current of the input sinusoid. The maximum peak current occurs at the peak of the minimum line voltage and is given by:
.
.../2 x P
1 Ima ( pk ) Vin ( min )
For the example converter the maximum peak line current is 4.42 amps at a Vin of BOVac.
The maximum ripple current in a boost converter occurs when the duty factor is 50% which is also when the boost ratio M=Vo/Vin=2. The peak value of inductor current generally does not occur at this point since the peak value is determined by the peak value of the programmed sinusoid. The peak value of inductor ripple current is important for calculating the required attenuation of the input filter. Figure 7 is a graph of the peak to peak ripple current in the inductor versus input voltage for the example converter.
The peak-to-peak ripple current in the inductor is normally chosen to be about 20% of the maximum peak line current. This is a somewhat arbitrary decision since this is usually not the maximum value
of the high frequency ripple current. A !arger val~e
of ripple current will put the converter into the discontinuous conduction mode for a larger portion of the rectified line current cycle and means that the input filter must be larger to attenuate more high frequency ripple current. The UC3854, with average current mode control, allows the boost stage to move between continuous and discontinuous modes of operation without a performance change.
The value of the inductor is selected from the peak current at the top of the half sine wave at low input voltage, the duty factor D at that input voltage and the switching frequency. The two equations necessary are given below:
0 Vo-Vin Vo
L= VinxD fsxAI
Where Al is the peak-to-peak ripple current. In the example 250W converter D=0.71, Al=900ma, and L=0.89mH. For convenience the value of L is rounded up to 1.0mH.
The high frequency ripple current is added to the line current peak so the peak inductor current is the sum of peak line current and half of the peakto-peak high frequency ripple current. The inductor must be designed to handle this current level. For our example the peak inductor current is 5.0 amps. The peak current limit will be set about 10% higher at5.5amps.
Output Capacitor
The factors involved in the selection of the output capacitor are the switching frequency ripple current, the second harmonic ripple current, the DC output voltage, the output ripple voltage and the hold-up time. The total current through the output capacitor is the RMS value of the switching frequency ripple current and the second harmonic of the line current. The large electrolytic capacitors which are normally chosen for the output capacitor have an equivalent series resistance which changes with frequency and is generally high at low frequencies. The amount of current which the papacitor can handle is generally determined by the temperature rise. It is usually not necessary to calculate an exact value for the temperature rise. It is usually adequate to calculate the temperature rise due to the high frequency ripple current and the low frequency ripple current and add them together. The capacitor data sheet will provide the necessary ESR and temperature rise information.
The hold-up time of the output often dominates any other consideration in output capacitor selection. Hold-up is the length of time that the output voltage remains within a specified range after input power has been turned off. Hold-up times of 15 to 50 milliseconds are typical. In off-line power supplies with a 400Vdc output the hold-up requirement generally works out to between 1 and 2µF per watt of output. In our 250W example the output capacitor is 450µF. If hold-up is not required the capacitor will be much smaller, perhaps 0.2µF per watt, and then ripple current and ripple voltage are the major concern.
Hold-up time is a function of the amount of energy stored in the output capacitor, the load power, output voltage and the minimum voltaQe the load ~ill operate at. This can be expressed m an equation to define the capcitance value in terms of the holdup time.
Co= 2xPoutxAt Vo2 - Vo ( min )2
Where Co is the output capacitor, Pout is the load power, Al is the hold-up time, Vo is the output voltage and Vo(min) is the minimum voltage the loa_d will operate at. For the example converter Pout 1s 250W, Al is 64msec, Vo is 400V and Vo(min) is 300V so Co is 450µF.
Switch and Diode
The switch and diode must have ratings which are sufficient to insure reliable operation. The choice of these components is beyond the scope of this Application Note. The switch must have a current rating at least equal to the maximum peak current in
9-371
APPLICATION NOTE
UC3854
U-134
TO COMPARATOR
Figure 8. Current Transformers Used
with Negative Output
VREF
DIODE CURRENT
SWITCH CURRENT
TO COMPARATOR
Figure 9. Current Transformers Used
with Positive Output
9-372
APPLICATION NOTE
U-134
the inductor and a voltage rating at least equal to the output voltage. The same is true for the output diode. The output diode must also be very fast to reduce the switch tum-on power dissipation and to keep its own losses low. The switch and diode must have some level of derating and this will vary depending on the application.
For the example circuit the diode is a high speed, high voltage type with 35ns reverse recovery, 600Vdc breakdown, and BA forward current ratings. The power MOSFET in the example circuit has a 500Vdc breakdown and 23Adc current rating. A major portion of the losses in the switch are due to the turn-off current in the diode. The peak power dissipation in the switch is high since it must carry full load current plus the di6de reverse recovery current at full output voltage from the time it turns on until the diode turns off. The diode in the example circuit was chosen for its fast turn off and the switch was oversized to handle the high peak power dissipation. A turn on snubber for the switch would have allowed a smaller switch and a slightly slower diode.
Current Sensing
There are two general methods for current sensing, a sense resistor in the ground return of the converter or two current transformers. The sense resistor is the least expensive method and is most appropriate at low power or current levels'. The power dissipation in the resistor may become quite large at higher current levels and in that case the current transformers are more appropriate. Two current transformers are required, one for the switch current and one for the diode current, to produce an analog of the inductor current as is required for average current mode control. The current transformers must operate over a very wide duty factor range and this .can be difficult to achieve without saturating them. Current transformer operation is outside the scope of this paper but Unitrode has Design Note DN-41 which discusses the problem in some detail.
The current transformers may be configured for either a positive output voltage or a negative output voltage. In the negative output configuration, shown in Figure 8, the peak current limit on pin 2 of the UC3854 is easy to implement. In the positive output configuration, shown in Figure 9, this feature may be lost. It can be added back by putting another resistor in series with the ground leg of the current transformer which senses the switch current.
The configuration of the multiplier output and the current error amplifier are different depending on whether a resistor is used for current sensing or whether current transformers with positive output
voltages are used for current sensing. Both work equally well and the configurations of the current error amplifier are shown in Figures 8 and 9 respectively. The positive output current transformer configuration requires the inverting input to the integrator be connected to the sense resistor and the resistor at the output of the multiplier be connected to ground. (see Figure 9) The voltage at the output of the multiplier is not zero but is the programming voltage for the current loop and it will have the half sine wave shape which is necessary for the current loop.
The resistor current sense configuration is used in the example converter (Figure 6) so the inverting input to the current error amplifier (pin 4) is connected to ground through Rei. The current error amplifier is configured as an integrator at low frequencies for average current mode control so the average voltage at the non-inverting input of the current error amplifier (pin 5, which it shares with the multiplier output) must be zero. The non-inverting input to the current error amplifier acts like a summing junction for the current control loop and adds the multiplier output current to the current from the sense resistor (which flows through the programming resistor Amo). The difference controls the boost regulator. The voltage at the inverting input of the current error amplifier (pin 4) will be small at low frequencies because the gain at low frequencies is large. The gain at high frequencies is small so relatively large voltages at the switching frequency may be present. But, the average voltage on pin 4 must be zero because it is connected through Rei to ground.
The voltage across Rs, the current sense resistor in the example converter, goes negative with respect to ground so it is important to be sure that the pins of the UC3854 do not go below ground. Tbe voltage across the sense resistor should be kept small and pins 2 and 5 should be clamped to prevent their going negative. A peak value of 1 volt or so across the sense resistor provides a signal large enough to have good noise margin but which is small enough to have low power dissipation. There is a great deal of flexibility in choosing the value of the sense resistor. A 0.25 ohm resistor was chosen for Rs in the example converter and at the worst case peak current of 5.6 amps gives a maximum voltage of 1.40V peak.
Peak Current Limit
The peak current limit on the UC3854 turns the switch off when the instantaneous current through it exceeds the maximum value and is activated when pin 2 is pulled below ground. The current limit value is set by a simple voltage divider from the reference voltage to the current sense resistor.
9-373
APPLICATION NOTE
U-134
The equation for the voltage divider is given below:
= R k2 Vrs x Rpk1
P
Vref
Where Rpk1 and Rpk2 are the resistors of the voltage divider, Vref is 7.5 volts on the UC3854, and Vrs is the voltage across the sense resistor Rs at the current limit point. The current through Rpk2 should be around 1mA. The peak current limit in the example circuit is set at 5.4 amps with an Rpk1 of 10K and Rpk2 of 1.8K. A small capacitor, Cpk, has been added to give extra noise immunity when operating at low line and this also incr~ases the current limit slightly.
Multiplier Set-up
The multiplier/divider is the heart of the power factor corrector. The output of the multiplier programs the current loop to control the input current to give a high power factor. The output of the multiplier is therefore a signal which represents the input line current.
Unlike most design tasks where the design begins at the output and proceeds to the input the design of the multiplier circuits must begin with the inputs. There are three inputs to the multiplier circuits: the programming current lac (pin 6), the feedforward voltage Vff from the input (pin 8), and the voltage error amplifier output voltage Vvea (pin 7). The multiplier output current is Imo (pin 5) and it is related to the three inputs by the following equation:
lmo=Kmxlacx(Vvea-1) Vff 2
Where Km is a constant in the multiplier and is equal to 1.0, lac is the programming current from the rectified input voltage, Vvea is the output of the voltage error amplifier and Vff is the feedforward voltage.
Feedforward Voltage
Vff is the input to the squaring circuit and the UC3854 squaring circuit generally operates with a Vff range of 1.4 to 4.5 volts. The UC3854 has an internal clamp which limits the effective value of Vff to 4.5 volts even if the input goes above that value. The voltage divider for the Vff input has three resistors (Rff1, Rff2 and Rff3 - see Figure 6) and two capacitors (Cff1 and Cff2) and so it filters as well as providing two outputs. The resistors and capacitors of the divider form a second order low pass filter so the DC output is proportional to the average value of the input half sine wave. The average value is 90% of the RMS value of a half sine wave. If the RMS value of the AC input voltage is 270Vac
the average value of a half sine will be 243Vdc and the peak will be 382V.
The Vff voltage divider has two DC conditions to meet. At high input line voltage Vff should not be greater than 4.5 volts. At this voltage the Vff input clamps so the feedforward function is lost. The voltage divider should be set up so that Vff is equal to 1.414 volts when Vin is at its low line value and the upper node of the voltage divider, Vffc, should be about 7.5 volts. This allows Vff to be clamped as described in Unitrode Design Note DN-398. There is an internal current limit which holds the multiplier output constant if the Vff input goes below 1.414 volts. The Vff input should always be set up so that Vff is equal to 1.414 volts at the minimum input voltage. This may cause Vff to clip on the high end of the input voltage range if there is an extremely wide AC line voltage input range. However, it is preferable to have Vff clip at the high end rather than to have the multiplier output clip on the low end of the range. If Vff clips the voltage loop gain will change but the effect on the overall system will be small whereas the multiplier clipping will cause large amounts of distortion in the input current waveform.
The example circuit uses the UC3854 so the maximum value of Vff is 4.5 volts. If Rff1, the top resistor of the divider, is 91 OK and Rff2, the middle resistor, is 91 K and Rff3, the bottom resistor, is 20K the maximum value of Vff will be 4.76 volts when the input voltage is 270Vac RMS and the DC average value will be 243 volts. When the input voltage is 80Vac RMS the average value is 72 volts and Vff is 1.41 Vdc. Also at Vin=80Vac the voltage at the upper node on the voltage divider, Vffc, will be 7.83 volts. Note that the high end of the range goes above 4.5 volts so that the low end of the range will not go below 1.41 volts.
The output of the voltage error amplifier is the next piece of the multiplier setup. The output of the voltage error amplifier, Vvea, is clamped inside the UC3854 at 5.6 volts. The output of the voltage error amplifier corresponds to the input power of the converter. The feedforward voltage causes the power input to remain constant at given Vvea voltage regardless of line voltage changes. If 5.0V is established as the maximum normal operating level then 5.6V gives an overload power limit which is 12% higher.
The clamp on the output of the voltage error amplifier is what sets the minimum value of Vff at 1.414 volts. This can be seen by plugging these values into the equation for the multiplier output current given above. When Vff is large the inherent errors of the multiplier are magnified because Vvea/Vff becomes small. If the application has a wide input voltage range and if a very low harmonic distortion
9-374
APPLICATION NOTE
U-134
is required then Vff may be changed to the range of 0.7 to 3.5 volts. To do this an external clamp MUST be added to the voltage error amplifier to hold its output below 2.00 veils. In general, however, this is not a recommended practice.
Multiplier Input Current
The operating current for the multiplier comes from the input voltage through Rvac. The multiplier has the best linearity at relatively high currents, but the recommended maximum current is 0.6mA. At high line the peak voltage for the example circuit is 382Vdc and the voltage on pin 6 of the UC3854 is 6.0Vdc. A 620K value for Rvac will give an lac of 0.6mA maximum. For proper operation near the cusp of the input waveform when Vin=O a bias current is needed because pin 6 is at 6.0Vdc. A resistor, Rb1, is connected from Vref to pin 6 to provide the small amount of bias current needed. Rb1 is equal to Rvac/4. In the example circuit a value of 150K for Rb1 will provide the correct bias.
The maximum output of the multiplier occurs at the peak of the input sine wave at low line. The maximum output current from the multiplier can be calculated from the equation for Imo, given above, for this condition. The peak value of lac will be 182 microamps when Vin is at low line. Vvea will be 5.0 volts and Vff will be 2.0. Imo will then be 365 microamps maximum. Imo may not be greater than twice lac so this represents the maximum current available at this input voltage and the peak input current to the power factor corrector will be limited accordingly.
The lset current places another limitation on the multiplier output current. Imo may not be larger than 3.75 I Rset. For the example circuit this gives Rset = 10.27K maximum so a value of 10K is chosen.
The current out of the multiplier, Imo, must be summed with a current proportional to the inductor current to close the voltage feedback loop. Rmo, a resistor from the output of the multiplier to the current sense resistor, performs the function and the multiplier output pin becomes the summing junction. The average voltage on pin 5 will be zero under normal operation but there will be switching frequency ripple voltage which is amplitude modulated at twice the line frequency. The peak current in the boost inductor is to be limited to 5.6 amps in the example circuit and the current sense resistor is 0.25 ohms so the peak voltage across the sense resistor is 1.4 volts. The maximum multiplier output current is 365 microamps so the summing resistor, Rmo, must be 3.84K and a 3.9K resistor is chosen.
Oscillator Frequency
The oscillator charging current is lset and is determined by the value of Rset and the oscillator frequency is set by the timing capacitor and the charging current. The timing capacitor is determined from:
Ct=~
Rsetxfs
Where Ct is the value of the timing capacitor and fs is the switching frequency in Hertz. For the example converter fs is 1OOKHz and Rset is 1OK so Ct is 0.00125µF.
Current Error Amplifier Compensation
The current loop must be compensated for stable operation. The boost converter control to input current transfer function has a single pole response at high frequencies which is due to the impedance of the boost inductor and the sense resistor (Rs) forming a low pass filter. The equation for the control to input current transfer function is:
Vrs _ Vout x Rs Vcea - Vsxsl
Where Vrs is the voltage across the input current sense resistor and Vcea is the output of the current error amplifier. Vout is the DC output voltage, Vs is the peak-to-peak amplitude of the oscillator ramp, sL is the impedance of the boost inductor (also jwl), and Rs is the sense resistor (with a current transformer it will be Rs/N). This equation is only valid for the region of interest between the resonant frequency of the filter (LCo) and the switching frequency. Below resonance the output capacitor dominates and the equation is different.
The compensation of the current error amplifier provides flat gain near the switching frequency and uses the natural roll off of the boost power stage to give the correct compensation for the total loop. A zero at low frequency in the amplifier response gives the high gain which makes average current mode control work. The gain of the error amplifier near the switching frequency is determined by matching the down slope of the inductor current when the switch is off with the slope of the ramp generated by the oscillator. These two signals are the inputs of the PWM comparator in the UC3854.
The downslope of the inductor current has the units of amps per second and has a maximum value when the input voltage is zero. In other words, when the voltage differential between the input and output of the boost converter is greatest. At this point (Vin=O) the inductor current is given by the ratio of the converter output voltage and the inductance (Vo/L). This current flows through the current sense resistor Rs and produces a voltage
9-375
APPLICATION NOTE
U-134
with the slope VoRs/L (with current sense transformers it will be VoRs/NL). This slope, multiplied by the gain of the current error amplifier at the switching frequency, must be equal to the slope of the oscillator ramp (also in volts per second) for proper compensation of the current loop. If the gain is too high the slope of the inductor current will be greater than the ramp and the loop can go unstable. The instability will occur near the cusp of the input waveform and will disappear as the input voltage increases.
The loop crossover frequency can be found from the above equation if the gain of the current error amplifier is multiplied with it and it is set equal to one. Then rearrange the equation and solve for the crossover frequency. The equation becomes:
f. VoutxRsxRcz Cl Vs x 21tl x Rei
Where fci is the current loop crossover frequency and Rcz/Rci is the gain of the current error amplifier. This procedure will give the best possible response for the current loop.
In the example converter the output voltage is 400Vdc and the inductor is 1.0mH so the down slope of inductor current is 400mA per microsecond. The current sense resistor is 0.25 ohms so the input to the current error amplifier is 1OOmV per microsecond. The oscillator ramp of the UC3854 has a peak to peak value of 5.2V and the switching frequency is 1OOKHz so the ramp has a slope of 0.52 volts per microsecond. The current error amplifier must have a gain of 5.2 at the switching frequency to make the slopes equal. With an input resistor (Rei) value of 3.9K the feedback resistance (Rcz) is 20K to give the amplifier a gain of 5.2. The current loop crossover frequency is 15.9KHz.
The placement of the zero in the current error amplifier response must be at or below the crossover frequency. If it is at the crossover frequency the phase margin will be 45 degrees. If the zero is lower in frequency the phase margin will be
greater. A 45 degree phase margin is very stable,
has low overshoot and has good tolerance for component variations. The zero must be placed at the crossover frequency so the impedance of the capacitor at that frequency must be equal to the value of Rcz. The equation is: Ccz = 1 I (21t x fci x Rcz). The example converter has Rcz=20K and fci=15.9KHz so Ccz=500pF. A value of 620pF was chosen to give a little more phase margin.
A pole is normally added to the current error amplifier response near the switching frequency to reduce noise sensitivity. If the pole is above half the switching frequency the pole will not affect the frequency response of the control loop. The example converter uses a 62pF capacitor for Ccp which
gives a pole at 128KHz. This is actually above the switching frequency so a larger value of capacitor could have been used but 62pF is adequate in this case.
Voltage Error Amplifier Compensation
The voltage control loop must be compensated for stability but because the bandwidth of the voltage loop is so small compared to the switching frequency the requirements for the voltage control loop are really driven by the need to keep the input distortion to a minimum rather than by stability. The loop bandwidth must be low enough to attenuate the second harmonic of the line frequency on the output capacitor to keep the modulation of the input current small. The voltage error amplifier must also have enough phase shift so that what modulation remains will be in phase with the input line to keep the power factor high.
The basic low frequency model of the output stage is a current source driving a capacitor. The power stage and the current feedback loop compose the current source and the capacitor is the output capacitor. This forms an integrator and it has a gain characteristic which rolls off at a constant 20dB per decade rate with increasing frequency. If the voltage feedback loop is closed around this it will be stable with constant gain in the voltage error amplifier. This is the technique which is used to stabilize the voltage loop. However, its performance at reducing distortion due to the second harmonic output ripple is miserable. A pole in the amplifier response is needed to reduce the amplitude of the ripple voltage and to shift the phase by 90 degrees. The distortion criteria is used to define the gain of the voltage error amplifier at the second harmonic of the line frequency and then the unity gain crossover frequency is found and is used to determine the pole location in the voltage error amplifier frequency response.
The first step in designing the voltage error amplifier compensation is to determine the amount of ripple voltage present on the output capacitor. The peak value of the second harmonic· voltage is given by:
Vo k
Pin
P 21tfr x Co x Vo
Where Vopk is the peak value of the output ripple voltage (the peak to peak value will be twice this), fr is the ripple frequency which is the second harmonic of the input line frequency, Co is the value of the output capacitance and Vo is the DC output voltage. The example converter has a peak ripple voltage of 1.84Vpk.
The amount of distortion which the ripple contributes to the input must be decided next. This deci-
9-376
APPLICATION NOTE
U-134
sion is based on the specification for the converter. The example converter is specified for 3% THO so 0.75% THO is allocated to this CO"l>Onent. This means that the ripple voltage at the output of the voltage error amplifier is limited to 1.5%. The voltage error amplifier has an effective output range (1Wvea) of 1.0 to 5.0 volts so the peak ripple voltage at the output of the voltage error amplifier is
give by Vvea(pk) =%Ripple x t:Nvea. The example
converter has a peak ripple voltage at the output of the voltage error amplifier of 60mVpk.
The gain of the voltage error amplifier, Gva, at the second harmonic ripple frequency is the ratio of the two values given above. The peak ripple voltage allowed on the output of the voltage error amplifier is divided by the peak ripple voltage on the output capacitor. For the example converter Gva is 0.0326.
The criteria for the choice of Rvi, the next step in the design process, are reasonably vague. The value must be low enough so that the opamp bias currents will not have a large effect on the output and it must be high enough so that the power dissipation is small. In the example converter a 511 K resistor was chosen for Rvi and it will have power dissipation of about 300mW.
Cvf, the feedback capacitor sets the gain at the second harmonic ripple frequency and is chosen to give the voltage error amplifier the correct gain at the second harmonic of the line frequency. The equation is simply:
Cvf
1
27lfr x Rvi x Gva
The example converter has a Cvf value of 0.08µF. If this value is rounded down to Cvf=0.047µF the phase margin will be a little better with only a little more distortion so this value was chosen.
The output voltage is set by the voltage divider Rvi
and Rvd. The value of Rvi is already determined so Rvd is found from the desired output voltage and the reference voltage which is 7.50Vdc. In the example Rvd=10K will give an output voltage of 390Vdc. This could be trimmed up to 400VDC with
a 414K resistor in parallel with Rvd but for this ap-
plication 390Vdc is acceptable. Rvd has no effect on the AC performance of the active power factor corrector. Its only effect is to set the DC output voltage.
The frequency of the pole in the voltage error amplifier can be found from setting the gain of the loop equation equal to one and solving for the frequency. The voltage loop gain is the product of the error amplifier gain and the boost stage gain, which can be expressed in terms of the input power. The multiplier, divider and squarer terms can all be
lumped into the power stage gain and their effect is to transform the output of the voltage error amplifier into a power control signal as was noted earlier. This allows us to express the transfer function of the boost stage simply in terms of power. The equation is:
Gbst Pin x Xco !1VveaxVo
Where Gbst is the gain of the boost stage including the multiplier, divider and squarer, Pin is the average input power, Xco is the impedance of the out-
put capacitor, t:Nvea is the range of the voltage
error amplifier output voltage (4 volts on the UC3854) and Vo is the DC output voltage.
The gain of the error amplifier above the pole in its frequency response is given by:
Xcf Gva=Rvi
Where Gva is the gain of the voltage error amplifier, Xcf is the impedance of the feedback capacitance and Rvi is the input resistance.
The gain of the total voltage loop is the product of Gbst and Gva and is given by the this equation:
G Pin x Xco xXcf v !1Vvea xVox Rvi
Note that there are two terms which are dependent on f, Xco and Xcf. This function has a second order slope (-40d8 per decade) so it must be a function of frequency squared. To solve for the unity gain frequency set Gv equal to one and rearrange the equation to solve for fvi. Xco is replaced with 1/(2n:fCo) and Xcf is replaced with 1/(2nfCvf).
The equation becomes:
M2
Pin
t.Vvea x Vo x Rvi x Cox Cvf x ( 2it )2
Solving for fvi in the example converter gives fvi=19.14Hz. The value of Rvf can now be found by setting it equal to the impedance of Cvf at fvi. The equation is: Rvf=1/(27tfviCvf).
In the example converter a value of 1nK is calculated and 174K is used.
Feedforward Voltage Divider Filter Capacitors
The percentage of second harmonic ripple voltage on the feedforward input to the multiplier results in the same percentage of third harmonic ripple current on the AC line. The capacitors in the feedforward voltage divider (Cff1 and Cff2) attenuate the ripple voltage from the rectified input voltage. The
9-~7
APPLICATION NOTE
U-134
second harmonic ripple is 66.2% of the input AC line voltage. The amount of attenuation required, or the "gain" of the filter, is simply the amount of third harmonic distortion allocated to this distortion source divided by 66.2% which is the input to the divider. The example circuit has an allocation of 1.5% total harmonic distortion from this input so the required attenuation is Gff = 1.5 I 66.2 = 0.0227.
The recommended divider string impliments a second order filter because this gives a much faster response to changes in the RMS line voltage. Typically, It is about six times faster. The two poles of the filter are placed at the same frequency for the widest bandwidth. The total gain of the filter is the product of the gain of the two filter section so the gain of each section is the square root of the total gain. The two sections of the filter do not interact much because the impedances are different so they can be treated separately. In the example converter the gain of each filter section at the second harmonic frequency is 0.0227 or 0.15 for each section. This same relationship holds for the cutoff frequency which is needed to find the capacitor values. These are simple real poles so the cutoff frequency is the section gain times the ripple frequency or:
le=~ xfr
The example converter has a filter gain of 0.0227 and a section gain of 0.15 and a ripple frequency of 120Hz so the cutoff frequency is fe=0.15x120=18Hz.
The cutoff frequency is used to calculate the values for the filter capacitors since, in this applivation, the impedance of the capacitor will equal the impedance of the load resistance at the cutoff frequency. The two equations given below are used to calculate the two capacitor values.
Cff1
=
2n
1 x Ip x
Rff2
Cff2
=
2n
x
1 fp x
Rff3
In the example converter Rff2 .is 91 K and Rff3 is 20K; so,
Cff1=1/21tX18x91 K=0.1 µF;
Cff2= 1/21tX18x20K=0.44µF;
so choose Cff2=0.47µF.
This completes the design of the major circuits of an active power factor corrector.
DESIGN PROCEDURE SUMMARY
This section contains a brief, step-by-step summary of the design procedure for an active power factor corrector. The example circuit used above is repeated here.
1. Specifications: Determine the operating requirements for the active power factor corrector.
Example:
Pout (max): 250W Vin range: 80-270Vac Line frequency range: 47-65Hz Output voltage: 400Vdc
2. Select switching frequency:
Example:
100KHz
3. Inductor selection:
A. Maximum peak line current. Pin = Pout(max)
I k -ff x Pin
P Vin (min)
Example:
lpk=1.41 x250/80=4.42 amps
B. Ripple current.
Al =0.2x lpk
Example:
~=0.2x4.42= 0.9 amps peak to peak
C. Determine the duty factor at lpk where Vin(peak) is the peak of the rectified line voltage at low line.
D = Vo - Vin ( peak ) Vo
Example:
D=(400-113)/400=0. 71
D. Calculate the inductance. fs is the switching frequency.
L= VinxD fs x~I
Example:
L=(113x.71 )/(1 OO,OOOx0.9)=0.89mH
Round up to 1.0mH.
4. Select output capacitor. With hold-up time, use the equation below. Typical values for Co are 1µF to 2µF per watt. If hold-up is not required use the second harmonic ripple voltage and total capacitor power dissipation to determine minimum size of the capacitor. At is the hold-up time in seconds and V1 is the minimum output
9-378
APPLICATION NOTE
capacitor voltage.
Co 2xPoutxM Vo2 -V12
Example: Co=(2x250x34msec)/(400-350)=450µF
5. Select current sensing resistor. If current transformers are used then include the tu ms ratio and decide whether the output will be positive or negative relative to circuit common. Keep the peak voltage across the resistor low. 1.0V is a typical value for Vrs.
A. Find tlpk ( max ) = lpk + ~I
Example: lpk(max)=4.42+0.45 ~ 5.0amps peak B. Calculate sense resistor value.
Rs Vrs lpk( max)
Example:
Rs=1.0/5.0=0.20 ohms. Choose 0.25ohms
C. calculate the actual peak sense voltage.
Vrs (pk)= lpk (max) x Rs
Example:
Vrs(pk)=5.0x0.25=1.25V
6. Set independent peak current limit. Rpk1 and Rpk2 are the resistors in the voltage divider. Choose a peak current overload value, lpk(ovld). A typical value for Rpk1 is 1OK.
Vrs ( ovld) = lpk ( olvd) x Rs
Example:
Vrs(ovld)=5.6x0.25=1.4V
R k2 Vrs ( ovld ) x Rpk1
P
Vref
Example:
Rpk2=(1.4x1 OK)fl.5=1.87K. Choose 1.8K
7. Multiplier setup. The operation of the multiplier is given by the following equation. Imo is the multiplier output current, Km=1, lac is the multiplier input current, Vff is the feedforward voltage and Vvea is the output of the voltage error amplifier.
1 Km x lac x ( Vvea - 1 )
mo
Vff 2
A. Feedforward voltage divider. Change Vin from RMS voltage to average voltage of the rectified input voltage. At Vin(min) the voltage at Vff should be 1.414 volts and the voltage at
U-134
Vffc, the other divider node, should be about 7.5 volts. The average value of Vin is given by the following equation where Vin(min) is the RMS value of the AC input voltage:
Vin ( av ) =Vin ( min ) x 0.9
The following two equations are used to find the values for the Vff divider string. A value of 1 Megohm is usually chosen for the divider input impedance. The two equations must be solved together to get the resistor values.
Vff-
1.414V=
Vin(av)xRff3 Rff1 + Rff2 + Rff3
Vin ( av ) x ( Rff2 + Rff3) Vnode ~ 7.SV Rff1 + Rff2 + Rff3
Example: Rff1=910K, Rff2=91K,andRff3=20K
B. Rvac selection. Find the maximum peak line voltage.
Vpk (max)= "2x Vin (max)}
Example:
Vpk(max)=1.414x270--382Vpk
Divide by 600 microamps, the maximum multiplier input current. Rv Vpk(max)
ac 600E-6
Example:
Rvac=(382)/6E-4=637K. Choose 620K
C. Rb1 selection. This is the bias resistor. Treat this as a voltage divider with Vref and Rvac and then solve for Rb1. The equation becomes:
Rb1 =0.25 Rvac
Example:
Rb1 =0.25Rvae=155K. Choose 150K
D. Rset selection. Imo cannot be greater than twice the current through Rset. Find the multiplier input current, lac, with Vin(min). Then calculate the value for Rset based on the value of lac just calculated.
. Vin (pk) lac ( mm ) = Rvac
Example:
lac(min)=113/620K=182µA
Rs t
3.75
e 2 x lac ( min )
Example:
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APPLICATION NOTE
U-134
Rset=3.75V/(2x182µA)=10.3Kohms.
Choose 1OKohms
E. Rmo selection. The voltage across Rmo must be equal to the voltage across Rs at the peak current limit at low line input voltage.
R Vrs (pk) x 1.12
mo 2 x lac ( min )
Example: Rmo=(1.25x1.12)/(2x182E-6)=3.84K.
Choose 3.9Kohms
8. Oscillator frequency. Calculate Ct to give the desired switching frequency.
Ct=~
Rset xfs
Example:
Ct=1.25/(1OKx1 OOK)=1.25nF.
9. Current error amplifier compensation.
A. Amplifier gain at the switching frequency.
Calculate thevoltage across the sense resistor due to the inductor current downslope and then divide by the switching frequency. With current transformers substitute (Rs/N) for Rs. The equation is:
!Nrs= Vox Rs Lxfs
Example:
iWrs=(400x0.25)/(0.001x100,000)=1.0Vpk
This voltage must equal the peak to peak amplitude of Vs, the voltage on the timing capacitor (5.2 volts). The gain of the error amplifier is therefore given by:
Gca=~
l!Nrs
Example:
Gca=5.2/1.0=5.2
B. Feedback resistors. Set Rei equal to Rmo.
Rei= Rmo
Rcz = Gca x Rei
Example:
Rcz=5.2x3.9K=20Kohms C. Current loop crossover frequency.
f . Vout x Rs x Rcz ci Vs x 2nl x Rei
Example:
fei=(400x0.25x20K)/(5.2x2:nx0.001 x3.9K)
=15.7KHz
D. Ccz selection. Choose a 45 degree phase margin. Set the zero at the loop crossover frequency.
Ccz
~
2n x fc1 x Rcz
Example:
Ccz=1/(2itx15. 7Kx20K)=507pF.
Choose 620pF
E. Ccp selection. The pole must be above fs/2.
c
1
cp 2n xfs x Rcz
Example:
Ccp=1/(2nx100Kx20K)=80pf.
Choose 62pF
10. Harmonic distortion budget. Decide on a maximum THD level. Allocate THD sources as necessary. The predominant AC line harmonic is
third. Output voltage ripple contributes 1/2°/o third harmonic to the input current for each 1% ripple at the second harmonic on the output of the error amplifier. The feedforward voltage, Vff, contributes 1% third harmonic to the input current for each 1% second harmonic at the Vff input to the UC3854.
Example:
3% third harmonic AC input current is chosen as the specification. 1.5% is allocated to the Vff input and 0.75% is allocated to the output ripple voltage or 1.5% to Vvao. The remaining 0.75% is allocated to miscellaneous nonlinearities.
11. Voltage error amplifier compensation.
A. Output ripple voltage. The output ripple is given by the following equation where fr is the second harmonic ripple frequency:
xp6: x Vo ( pk ) = 27tlr
Vo
Example:
Vo(pk)=250/(2it120x450E-6x400)=1.84Vac
B. Amplifier output ripple voltage and gain.
Vo(pk) must be reduced to the ripple voltage allowed at the output of the voltage error amplifier. This sets the gain of the voltage error amplifier at the second harmonic frequency. The equation is:
Gva tNvao x %Ripple Vo (pk)
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APPLICATION NOTE
U-134
For the UC3854 Vvao is 5-1=4V
Example:
Gva=(4x0.015)/1.84=0.0326
C. Feedback network values. Find the component values to set the gain of the voltage error amplifier. The value of Rvi is reasonably arbitrary.
Example:
Choose Rvi=511K
Cvf -
1
27t x fr x Rvi xGva
Example: Cvf=1/(2n:x120x511 Kx0.0326)=0.08µF.
Choose 0.047µF
D. Set DC output voltage.
Rvd Rvi x Vref Vo-Vref
Example:
Rvd=(511 Kx7.5)/(400-7.5)=9.76K.
Choose 1O.OK E. Find pole frequency. fvi = unity gain fre-
quency of voltage loop.
fvi 2 =
. Pin
AVvao x Vo x Rvi x Cox Cvf x( 211: )2
Example:
!vi= ,/(250/(4X400x511 Kx450E-6x47E-9x39.5)) -
19.1 Hz
F. Find Rvf.
Rvf
1 2lt x fvi x Cvf
Example:
Rvf=1/(2n:x19.1 x47E-9)=177K. Choose 174K
12. Feedforward voltage divider capacitors. These capacitors determine the contribution of Vff to the third harmonic distortion on the AC input current. Determine the amount of attenuation needed. The second harmonic content of the rectified line voltage is 66.2%. %THO is the allowed percentage of harmonic distortion budgeted to this input from step 10 above.
Gff= %THD 66.2%
Example:
Gff=1.5/66.2=0.0227
Use two equal cascaded poles. Find the pole frequencies. fr is the second harmonic ripple frequency.
fp = ,JGttx fr
Example: fp=0.15x120=18Hz Select Cff1 and Cff2.
Cff1
1 27txfp x Rff2
= Cff2
1 27txfp x Rff3
Example:
Cff1=1/(27tX18x91K)=0.097µF. Choose 0.10µF Cff2=1/(27tX18x20K)=0.44µF. Choose 0.47µF
REFERENCES
L. H. Dixon, "High Power Factor Preregulator for Off-Line Supplies," Unitrode Power Supply Design Seminar Manual SEM600, 1988 (Reprinted in subsequent editions of the Manual.)
L. H. Dixon, "High Power Factor Switching Preregulator Design Optimization," Unitrode Power Supply Design Seminar Manual SEM700, 1990 (Reprinted in subsequent editions of the Manual.)
L. H. Dixon, "Average Current Mode Control of Switching Power Supplies," Unitrode Power Supply Design Seminar Manual SEM700, 1990 (Reprinted in subsequent editions of the Manual.)
S. Freeland, "Input-Current Shaping for SinglePhase Ac-De Power Converters," Ph.D. Thesis, California Institute of Technology, 1988
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. · MERRIMACK, NH 03054 TEL. 603-424-2410 · FAX 603-424-3460
9-381
n n INTEGRATED
~CIRCUITS
-UNITRODE
APPLICATION NOTE
U-135
The.UC3848 Average Current Mode Controller Squeezes Maximum Performance from Single Switch Converters
by JOHN A. O'CONNOR
ABSTRACT
This application note describes the UC3848 average current mode PWM controller. The unique features of this controller are discussed, which make primary side average current mode control practical for isolated converters. The UC3848 employs a current waveform synthesizer which monitors switch current and simulates the inductor current down slope, generating a complete current waveform without actual secondary sid" measurement. Primarily intended for single ended converters, several additional features such as accurate duty-cycle and volt-second limiting allow maximum transformer and switch utilization. A three output, 200 watt off-line design example is presented which also features planar magnetics and a coupled output inductor.
INTRODUCTION
The UC3848 represents a significant advance in the control of single switch forward converters. Generally considered simple and reliable, but nonoptimum in transformer and switch utilization, the ·single switch forward has previously been reserved for less demanding applications. Upon careful examination however, it is apparent that many of the perceived limitations actually result from the control circuitry rather than the converter topology itself.
The advantages that an inner current loop brings to power supply design and· performance are well known [1]. Current mode control is usually preferred over direct duty cycle control because of the superior input supply rejection and simplified voltage loop closure. Average current feedback provides additional advantages over the more common peak current feedback. Major benefits include inherent slope compensation, better noise rejection, and the ability to operate with both continuous and discontinuous inductor current. Additionally, average current feedback provides significantly better closed current loop accuracy. This further improves input supply rejection and current limit accuracy. Average current feedback is detailed in the references [2,3,4).
Maximum power component utilization requires carefully defined and controlled operating mode boundaries. While this can be said of many converter topologies, it is particularly critical with the single switch forward because of the transformer
reset mechanism. Energy in the transformer leakage and magnetizing inductance must be removed after each energy transfer cycle. Above all, the control circuit must insure that this condition is achieved. Total losses are generally minimized by bringing the peak power transfer as close to the average as possible. This indicates that improvements in efficiency and component utilization are obtainable by maximizing duty-cycle. Unfortunately, maximizing duty-cycle conflicts with assuring transformer reset, traditionally requiring an overly conservative design to assure reliability.
Previously, these characteristics have limited the single switch converter to low-power, low-end applications. The UC3848 Average Current Mode PWM Controller allows operation beyono conventional limitations by employing highly accurate circuitry to provide· programmable operating boundaries, and by implementing an inner average current feedback loop for improved control characteristics and accuracy. This control circuit advance capitalizes on unique, patented circuitry, and the precision achievable with Unitrode's thin-fil.m resistor process.
The UC3848 Average Current Mode PWM Controller
The block diagram of the UC3848 shown in figure 1, illustrates a number of unique functions. Although the IC can certainly be used for flyback,
9-382
APPLICATION NOTE
U-135
Figure 1 UC3848 Avera e Current Mode PWM Controller
C1
CURRENT
AMP
INPUT
Figure2 Inductor Current Waveform Synthesizer
9-383
APPLICATION NOTE
U-135
boost, as well as other buck derived converters [4], the UC3848 has been optimized for forward converter use. The UC3848s precision functions bring switching power supply control to a new level:
· Average Current Mode Control · Average Current Sense Signal Synthesizer · Programmable Maximum Duty-Cycle and
Volt-Second Control · Under Voltage Lockout (UVLO) monitors
Vee, Vin, and Vref · 2 Amp peak MOSFET Driver with Active
Low During UVLO · 8MHz gain-bandwidth Current Error Amplifier · Latched PWM comparator · Practical Operation up to 1MHz · Low Start-Up Current (SOOuA) · Precision Reference (1 % @ SV)
The sophistication and performance of the UC384B may at first appear contradictory to simple forward converter design. A truly simple implementation however, is best achieved by maintaining simple power circuitry, and placing the complexity and precision in the control circuitry where it can be integrated into a single IC.
Average Current Mode Control
niques are available for setting the discharge current, depending on the required accuracy of the current sense signal. If good short-circuit accuracy
is required, an analog of the output voltage is re-
quired to control the synthesizer capacitor discharge rate. There are two simple ways to derive this signal on the primary side.
The first method uses a transformer bootstrap winding voltage as shown in figure 2. The average value of the rectified output and bootstrap winding voltages are directly proportional. By adding a separate rectifier and filter to this winding, the capacitor discharge current can be programmed to track VouT. Typically, a bootstrap winding is employed with off-line converters to power the control circuitry after initial start-up, so the raw signal is
usually present at no additional cost. Note that an
error is present during transients since the filter creates a lag between the output and the filtered bootstrap voltages.
If the transient error is unacceptable, the technique shown in figure 3 can be used. A secondary winding on the output inductor provides a voltage directly proportional to the output without filtering. While the switch is off, VouT is across the output inductor. Any other winding on the inductor will have a voltage proportional to VouT by the turns
Average current loop implementation first requires an average current signal for the control variable. This immediately presents a problem with isolated converters since this signal is entirely on the secondary side. A current sense transformer cannot be used to directly sense output inductor current
with buck derived converters since the inductor normally has a continuous DC component. A potentially complex and expensive solution is avoided with the realization that output inductor current is
directly reflected to the primary during the switch
on time. Simply scaling the switch current by the
transformer turns ratio provides the rising portion of the inductor current waveform. When the switch is off, the inductor current decays at VouTIL. This information can be used to synthesize an analog of the actual output inductor current without any secondary connections.
Inductor current is synthesized by the UC3848 with a circuit that behaves similar to a track and hold amplifier, as shown in figure 2. While the switch is
on, a unity gain buffer charges an external capaci-
tor (C1), essentially following the rising input current
waveform. A one volt offset is also added to provide sufficient headroom for the buffer's output stage. When the switch turns off, a programmable current sink discharges the capacitor, simulating the actual inductor current decay. Several tech- ·
IOFF
Flgure3 IOFF Generation using Second Inductor Winding
ratio of the two windings. The sense winding rectifier drop cancels the output rectifier drop when the turns ratio is 1: 1, yielding excellent signal accuracy. While this approach is simple and accurate, ii does come at additional expense since this winding is not normally required. Additionally, high voltage agency approved isolation is required for off-line converters, adding further cost and manufacturing complexity to the inductor. With either of these techniques, an offset current may be added to compensate for the synthesizer's
.9.394
APPLICATION NOTE
U-135
RI CP
RF CZ
GAIN (dB) 0
FIGURE 4. AVERAGE CURRENT FEEDBACK LOOP
Flgure4 Average Current Feedback Loop
LOG F
one volt offset. Connecting a resistor with a value four times the loFF input resistor between the VREF and loFF pins cancels the offset.
~flen, a fixed discharge current is acceptable. This 1s programmed by connecting a resistor between the VREF and loFF pins. The synthesized current waveform is quite accurate when the output voltag.e is n~r the regulating value, however an error ~x1sts durmg start-up and output short-circuit. During a short, the current decays much slower since VouT is only the output rectifier and circuit resistance voltage drops. The current ripple also becomes a small fraction of its value at the regulating voltag~. The synthesizer however, discharges the capacitor as if the output were not shorted and therefore underestimates the output inducto; current. The short-circuit current will then exceed the programmed limit by almost one-half of the normal ~ak-to-peak ~ipple current. Typically, the inductor ripple current 1s 20% to 30% of the maximum DC value, corresponding to a short circuit current 10% to 15% higher than the maximum output current available at normal output voltage.
The current error amplifier has sufficient gain to
us~ a current sense resistor directly in most appli-
cations. A current sense transformer however re-
sults in better performance by allowing a 1a'rger
amplitude, lower noise signal. Ideally, the current
sense signal is scaled to 4 volts at the maximum
current level. The current transformer load resis-
tance is then:
7: Rs=4VxNx
(1)
where
N =transformer turns ratio Ns =current transformer ratio IL =maximum load current
Figures Open Current Loop Response
With multiple secondaries, normalize all other loads to the main output through the turns ratio directly. Note that for these calculations, output inductors and their effect on ripple current is not considered, since the UC3848 controls average, not peak current. Output inductances must be normalized to the main output through the turns ratio squared however, when calculating peak current and current ripple.
The recommended nominal loFF current is 100µ A, leaving C1 the remaining current synthesizer component.
Ci ( 100µA x Nx NsxLNORM)
(2)
( Rsx Vour( nom))
where
LNORM =normalized output
inductance
Fi~ur~ 5 shows ~he average current feedback loop. This inner loop 1s analogous to direct duty-cycle or voltage-mode control except that the control variable is output inductor current rather than output ~oltage. Properly compensated, the open loop gain 1s comparable to peak current-mode's at high fre-
quency, and becomes orders of magnitude higher as frequency decreases. The open current loop response shown in figure 6 illustrates this behavior. This high open loop gain translates into high
9-385
APPLICATION NOTE
.......v Jl nr
RAMP
CLK DMAX
U-135
VIN
TO PWM LATCH
UVLO
Figure&
Duty-Cycle Limit Programming
closed loop accuracy. In comparison, peak current mode relies entirely on it's transfer function accuracy, and has no means by which to reduce errors. This characteristic difference from peak currentmode is attributed to the current error amplifier's compensation, and is key to the resulting performance enhancements.
The increased gain at low frequency provides excellent closed current loop accuracy, even when the inductor current becomes discontinuous. High open loop gain also allows greater filtering of the current sense signal with no degradation in closed loop accuracy. It is this characteristic, along with the larger amplitude signals that provides significantly reduced noise susceptibility in comparison to peak current-mode control.
PWM Oscillator
Oscillator programming is simplified by providing
internally set charge and discharge currents. Ex-
cellent initial accuracy and temperature stability are assured by precision thin-film resistors. Since only a timing capacitor (Cr) is required to set the frequency, external component error contribution is minimal. The precision high speed oscillator combined with short propagation delay through the PWM circuitry allows practical operation up to 1MHz.
A 200µA charge current and a 1SOOµA discharge current generates a sawtooth waveform with a well defined rise/fall relationship and accurate frequency. During discharge, the output driver is disabled, limiting the maximum duty-cycle to 90%. Note that this maximum can be reduced by the aO' curate, duty-cycle limit and the volt-second product limit circuits, which are explained in following sec-'
Flgure7 Volt-Second Clamp
tions. Oscillator frequency is programmed by:
F= 1 ( 10k+ Cr)
(3)
If greater frequency accuracy is required, a trim resistor in parallel with Cr can be added to lower the frequency. The trim resistor should not be less than 40k.Q, limiting the maximum trim range to 25% below nominal. Frequency decrease as a function of trim resistance is· shown on the UC3848 data sheet.
Duty-Cycle Limiting and Soft Start
The conventional single switch forward converter design usually limits the maximum duty-cycle to 50%. This limit however,· is only required if a oneto-one clamp winding is employed to facilitate transformer core reset. While some designers still use this technique, a resistor/capacitor/diode
(RCD) .clamp has become more prevalent. The
RCD clamp eliminates a transformer winding and potentially offers a wider duty-cycle range. Currently, a 50"/o duty-cycle limit is primarily used because it can be accurately derived from a toggle flip-flop. To exploit a wider duty-cycle, an accurate, programmable duty-cycle clamp is required.
The UC3848 employs a unique, patented technique to limit the maximum duty-cycle to a value programmed by a resistive divider. The circuit utilizes a capacitor (Coe) for integration only, and does not rely on its absolute value for maximum duty-cycle accuracy. The absolute value of Coe does set the soft-start time constant, although high precision is not normally required for this function.
Internally, the UC3848 capitalizes on the excellent matching characteristics achievable on an IC to implement a charge balanced loop. A matched transconductance source and sink form a precision integrator circuit, as shown in figure 6. The current
9-386
APPLICATION NOTE
U-135
source is externally programmed to Gm x VoMAX and is on continually. The current sink is internally set at Gm x 5V, and is switched on and off. The resulting discharge current is Gm(5V - DMAX). The current source and sink charge and discharge Coe, while its voltage is compared with the oscillator voltage.
The current sink discharges Coe from the time that the switch is turned on until the oscillator voltage becomes greater than Coc's voltage. For the remainder of the period, Coe is charged by the current source. Note that Coc's voltage is essentially a DC level with a very small ripple component unless it is a particularly small value. Coe maintains a constant voltage only if the average applied charge is zero. The charge balanced loop therefore forces
loiseHARGE x TON(max) to equal leHARGE x TOFF(min). A large offset voltage between CT and Coe may be observed when measuring an actual circuit. This offset contributes negligible error since high DC loop gain reduces its effect by several orders of magnitude.
While the circuit's operation may seem complicated, it couldn't be easier to apply. A voltage divider from VREF to DMAX as shown if figure 6 sets the maximum duty-cycle. The circuit inherently provides soft-start.at initial power-up as Coe charges to it's steady state value. Increasing Coe extends the loop settling time, and hence the soft-start time constant, with no effect on the programmed maximum duty-cycle. Note that the single pole loop re· sponse avoids overshoot, regardless of t~e integrating capacitor value. Soft-start after fault 1s explained in the under-voltage lockout section. Maximum duty-cycle and soft-start are programmed by the following relationships:
Rm.
DMAx=(RD1+RD2)
(4)
'tss= 20kx Coe
(5)
down as the reset time increases.
If during a transient the duty-cycle is allowed to increase excessively, the MOSFET will be subjected to significantly higher voltages. This assumes that the reset circuit's clamp voltage can slew rapidly. If it cannot, the magnetizing current will ratchet up, possibly saturating the transformer. Both scenarios are easily prevented by simply limiting the maximum applied volt-second product.
The UC3848 generates a voltage proportional to the volt-second product with the circuit shown in figure 7. A current directly proportional to the supply voltage (ViNIRvs) charges a capacitor (Cvs) while the MOSFET is on. When the MOSFET is turned off, the capacitor is discharged. Volt-second limiting is accomplished by comparing the capacitor's voltage to a 4 volt reference, and terminating the pulse width for the remainder of the switching period. Normally, the worst case MOSFET voltage occurs during maximum input voltage at the voltsecond limited duty-cycle. However, high turns ratio designs which allow a very wide duty-cycle may actually generate the highest MOSFET voltage during low-line at the volt-second limited duty-cycle.
Since the volt-second product is constant it can be calculated at any input voltage. The effeetiveness
LOW VOLT AGE BOOTSTRAP
Volt-second Product Limit
During transients it may be desirable to limit the duty-cycle below the programmed maximum value. For example, active transformer reset circuits vary the clamp voltage inversely proportional to the input supply voltage [5]. During steady state operation the peak MOSFET voltage varies much. less than with passive clamp circuits. Unless the mput voltage range is large, the peak MOSFET voltage will be fairly constant. This occurs because the applied volt-second product remains constant over the entire operating duty-cycle range during steady state. Thus as the input voltage goes up and the duty-cycle decreases, the clamp voltage goes
Figures
Under Voltage Lockout
of the volt-second limit however, should be analyzed at minimum and maximum input voltage, in addition to a few more typical voltages. The voltsecond product clamp is programmed by:
ViNX ToN=4.0Vx Rvsx Cvs
(6)
Under Voltage Lockout
Programmable under voltage lockout (UVLO) further defines operating mode boundaries. Vee, V1N,
9-387
APPLICATION NOTE
U-135
and VREF are monitored to insure that the chip supply, main input supply, and reference are within specification before enabling the output stage. Figure 8 shows the. block diagram of the UVLO circuitry.
The Vee comparator monitors the chip supply voltage. Hysteretic thresholds at 13V and 1OV insure that sufficient voltage is available to power the chip and fully turn on the MOSFET. The V1N comparator monitors the input supply through a resistive divider. A small capacitor from UV to ground is usually required to filter noise from this high impedance node. Both the thresholds and the hysteresis are programmed by the divider values with the relationships:
Rv1 VtN(ON)=4.5Vx( 1 + RV2')
(7)
VtN(
OFF)=
4.5
Vx
(
1
+
RV1 RV2)
(8)
where
RV2' = RV2 II 90k
(9)
When either the Vee or the V1N comparator are low, the bias circuitry to the rest of the chip is off. The quiescent current (Ice) is nominally 500µ A to facilitate off-line applications. Once both Vee and V1N are within specification, the bias circuitry for the rest of the chip is activated. The output driver and Coe pin are still held low until VREF exceeds the 4.5V threshold of the VREF comparator. When the VREF comparator goes high, control of the output driver transfers to the PWM circuitry and Coe is allowed to charge, soft-starting the supply.
If any of the three monitored voltages falls below their threshold during start-up or normal operation, the UVLO latch is set, the output driver is held low, and Coe is discharged. This state is maintained until Coe is fully discharged, at which point operation is as described above.
Output Driver
High current transistors enable the output driver to deliver 2 amps peak allowing direct interface to any MOSFET typically used in single ended converters. The driver also incorporates self-biasing circuitry that maintains a low impedance to ground during UVLO. This assures that high dv/dt at V1N during power-up cannot inadvertently turn on the MOSFET through its miller capacitance.
The combination of high peak current, stray circuit inductance, and capacitive gate load result in reflections back to the driver, which if left unclamped, will cause erratic chip behavior. External schottky
diodes from the output to Vee and ground will divert the reflected current and assure reliable operation. A well designed layout with typical circuit values will normally require 1A, 20V schottky clamp diodes~ Looser layouts, longer gate drive traces, and lower gate resistor values all place greater demand on the output clamping circuit, and may necessitate higher current diodes.
Voltage Reference and Error Amplifier
Since the UC3848 is intended for primary side control, the voltage reference (VREF) does not affect output voltage stability. It does however, affect current limiting and the other precision circuits previously mentioned, and has therefore been designed for good initial accuracy and temperature drift. The reference should be capacitively bypassed to reduce high frequency output impedance and noise susceptibility.
To facilitate wide bandwidth current loops, the error amplifier has an 8Mhz gain bandwidth product. Even with small current feedback signals such as from a current sense resistor, loop bandwidth will almost always be limited by external circuit characteristics rather than error amplifier limitations. The amplifier's 8 V/s slew rate assures that even during large signal transients, external components will determine circuit behavior.
Design Example
A 200 watt off-line supply utilizing the UC3848 is shown in figure 9. It delivers a regulated +5V at 20A, and a semi-regulated +/-15V at 3.3A. The conversion frequency is 260kHz, which was determined to be a reasonable compromise between size and efficiency. A coupled output inductor improves dynamic cross regulation and steers some of the +5V ripple current to the +/-15V filter capacitors [9]. This results in minimal total output capacitor volume. A bridge/doubler input rectifier allows operation over an input range of 85 to 265VAC. For simplicity and cost, an RCD clamp is employed to facilitate transformer reset. This common configuration is typical of many commercial applications.
The transformer turns ratio is selected to minimize MOSFET stress. Ideally, the maximum duty-cycle should be as large as possible, allowing the highest turns ratio and lowest reflected load current. This must be balanced against the peak MOSFET voltage developed during transformer reset.
Since the UC3848 can accurately define operating mode boundaries, any practical duty-cycle range can be used. This allows maximum utilization of both current and voltage capability of a particular
9-388
APPLICATION NOTE
U-135
AC2 R32
RI
.-2
1
2
4 L3 3
~-+-~~ · .!.!.t"":t:=:=Dl~r":!'.'CC,.....,...~==-<·s C31,32
_ _.___ l~__,, _..._ _._--<+5 RET
R30
R15
C36
R31
C38
7 vs
9 CDC
ec
R14
R22
R23 C21 R24
RH C23
7
R25
.___ _..._ __.,___ ___,,,_,+6 RET
Flgure9 200W 3 OUTPUT FORWARD CONVERTER
MOSFET. The RCD clamp allows some trade-off in dissipation versus peak MOSFET voltage. Turns ratio and clamp optimization requires a good estimation of leakage inductance, ·switch capacitance, and transformer interwinding capacitance, since energy stored in these parasitics will be transferred or dissipated each switching cycle. RCD clamp optimization is covered in detail in reference [6).
The design example transformer uses a 16:1 turns ratio (primary to 5 volt), allowing a wide input sup-
ply range and reliable use of an aoov MOSFET.
The MOSFET, an APT801 R2BN from Advanced Power Technology [7], is rated at 800V and has 1.2n maximum on resistance at 25°C. A planar
transformer and coupled output inductor from Signal Transformer Co. [8] are used, which offer several advantages over custom wound components. Planar construction provides tighter parameter tolerance. Compact, low profile magnetics help achieve high power density. Their standard design provides agency approved insulation and known performance characteristics, greatly reducing the number of iterations to produce a good power supply design.
The duty-cycle is limited to 0.6, maintaining regulation down to approximately 160 VDC in. With the switching frequency programmed for 260 kHz, the nominal volt-second product is 345 Vs. The voltsecond clamp is programmed to 425 Vs to allow for tolerances and large signal transients.
A current transformer senses switch current resulting in minimal loss and good signal quality. A 1000pF capacitor shunts the high frequency turnon spike before feeding the current sense signal to the UC3848s current waveform synthesizer. A fixed loFF value renders an acceptable short circuit current for this application. Average short circuit losses are kept low by the hiccup action which occurs as the boot-strap supply colapses and the supply restarts. Highly accurate short circuit current is most advantageous when a continuous supply is available for the control circuit such as in low voltage DC to DC converter applications.
When the MOSFET is on, the current synthesizer's loFF current is increased through a resistor connected to the gate driver output (R13). This allows C1's voltage to better follow rectifier reverse recovery spikes present in the current waveform. This technique allows minimal filtering of the current
9-389
APPLICATION NOTE
U-135
Figure 10
Voltage Feedback Loop
sense signal, and thus preserves-accuracy.
The coupled output inductor provides good dynamic cross regulation, and steers some of the 5 volt ripple current to the +/-15 volt out~uts wh~re it is more efficiently filtered. Although this technique minimizes size and complexity, it does negate two major advantages of average current mode control. The average current loop maintains excellent regulation down to zero load for the fully regulated output. Unfortunately, the semi-regulated outputs will degrade quickly as the inductor current becomes discontinuous, forcing minimum loads for reasonable output voltage tolerance. Also, stray and lea_kage inductance between the secondary circuits introduces parasitic tank circuits, which if underdamped, will cause output ringing and instability. Generally, electrolytic output capacitors, low coupled inductor leakage inductance, and tight layout will allow successful implementation, although loop bandwidth must usually be compromised to maintain stability. Coupled output inductor design and application is detailed in reference [9].
Without the additional output circuitry parasitics, a single output supply with average current feedback has excellent regulation and transient response from zero to full load. There is also much less restriction on output capacitor type, allowing small ceramic or film capacitors in many applications. Although the design example's close~ loop b~nd width is not as high as would be achievable with a single output, the electrolytic output capacitors store enough energy to provide good transient response and low output impedance.
loop compensation is best described in the references (2,3], as a number of subtleties m~t be considered for optimal performance. The basic ap-
proach is easily summarized:
To avoid subharmonic oscillation of a single pole system, the amplified inductor current downslope at one input of the PWM comparator must not exceed the oscillator ramp slope at the other comparator input. This puts an upper limit on the current amplifier gain, and indirectly sets the loop gain crossover frequency. As derived in [2], the resulting unity gain crossover frequency will be:
f. Us VtN) _f,_s_ c (211VouT) (2110)
(10)
The crossover frequency must be reduced in a practical system to account for tolerances and additional waveform slope injected by output voltage ripple through the voltage error amplifier. For the design example, fc is approximately 50kHz at the maximum duty-cycle.
At the switching frequency, the average current loop's behavior is similar to peak current mode control. Placing a zero at one-half the crossover frequency increases the loop gain with decreasing frequency, providing high closed current loop accuracy. To further reduce noise susceptibil~, a pole is placed at the switching frequency. While such a low frequency filter is completely unacceptable with peak sensing, the high gain at low frequency assures accurate current limiting. It is these fundamental differences from peak current mode which provide the performance enhancements.
The voltage loop reference and error amplifier reside on the secondary side as typically configured in off:line power supplies. A UC19432 incorpor~!es a high precision reference, voltage error amphfler, and programmable transconductance amplifier for accurate opto-coupled feedback. Volta~e loop compensation is normally the same as with peak
current mode control and is described in detail in the references [2,9, 1O]. As previously noted, an additional LC pole resulting from leakage a!"Jd stray inductance requires additional compens'.'1t1on. Ul~1mately, this parasitic restricts the bandwidth of this coupled inductor design example, although transient response is still quite good. The same co~trol configuration with a single output ~upply provides optimal performance and allows simpler compen-
sation.
Control Loops
A block diagram of the voltage feedback loop is shown in figure 1O. For clarity, the inner average current feedback loop is shown as a transconductance amplifier, and is identical to figure 4. Current
Summary
The UC3848 clearly demonstrates the next level of switching power supply control achievable with improved techniques and precision circuitry. High
9-390
APPLICATION NOTE
U-135
performance and high power density objectives coupled with the need for simplicity and low cost have called for further refinement of single switch conversion. The UC3848 answers that call combining precision circuitry, average current mode control and function flexibility, allowing optimal power component utilization and performance.
References:
[1 ]V. Holland, "Modelling, Analysis and Compensation of the Current-Mode Converter" Unitrode application note U-97
[2]L. Dixon, "Control Loop Design", Unitrode Switching Regulated Power Supply Design Seminar Manual, SEM800, 1991
[3]L. Dixon, "Average Current Mode Control of Switching Power Supplies", Unitrode application note U-140
[4]B. Mammano, "Average Current-Mode Control Provides Enhanced Performance for a Broad Range of Power Topologies", PCIM conference proceedings, 1992
[5]B. Carsten, "Design Techniques for Transformer Active Reset Circuits at High Frequencies and
Power Levels", High Frequency Power Conversion conference proceedings, 1990
[6]C.S.Leu, G.C.Hua, F.C. Lee, C. Zhou, "Analysis and Design of RCD Clamp Forward Converter", Virgina Power Electronics Center seminar proceedings, 1992
[?]Planar Magnetics data sheet, Signal Transformer Co., Inwood, NY, 516-239-5777
[8]APT801 R2BN data sheet, Advanced Power Technology, Bend, OR, 503-382-8028
[9]L. Dixon, "Coupled Filter Inductors in Multi-Output Buck Regulators", Unitrode Switching Regulated Power Supply Design Seminar Manual, SEM800, 1991
[1 O]L. Dixon, "Closing the Feedback Loop", Unitrode Switching Regulated Power Supply Design Seminar Manual, SEM700, 1990
Unitrode Data Sheets:
UC3848 UC19432
9-391
APPLICATION NOTE
PARTS LIST FOR 200W CONVERTER
R1,2
825k
1%
R3,4
243k
1%
RS
422k
1%
R6, 7
10k
R8
10.0k
1%
R9
15.0k
1%
R10, 11 62k
1W
R12
68
R13
36k
R14
39k
R1S,23 2k
R16, 17 15k
3w
R18
10
2w
R19,20 33
1/2w
R21
33
R22
200
R24
18.7k
1%
R25
6.49k
1%
R26
1k
R27, 26 20
R29
100
R30,31 120k
1/2w
R32
SONTC thermistor
C1-C4
cs
C6, 20, 31, 32, 35, 36
390µF 20% 200V 100µF 20% 25V 1µF
C7, 14
ca
1nF 220pF 5%
C9
47nF
C10
390pF 5%
C11
22pF
C12
330pF
C13
220pF
C1S
10nF
C16
2.2nF
C17 C18, 19
4.7nF 470pF
100V
soov
C21,23
3.3nF
C24-C30
1000µF 20"k 10V
C32, 33, 36, 37 330µF
C39,40
2.2nF
20"k 2SV
20% soov
class x/y
C41,42
100nF 20% 100V
U-135
01 02,3 03
MB106-ND 1N5820 1N474SA
(Diodes, Inc.)
04,5
1N4148
06
10DF6
07
40CPQ060
09, 10 1DC1F20
(International Reclfler) (International Recifier) (International Reclfter)
01 L1,2 L3 TR1 TR2 U1 U2
APT801R2BN (Ad/anced Power Technology)
RL-1160-1.0
(Renco)
SHFl-2S15
(Signal Transformer Co.)
SHF-252S-16 (Signal Transformer Co.)
PE64978
(Pulse Engineering)
UC3848
UC19432
NOTE: All resistors 5%, 1/4 watt unless noted All capacitors 10%, SOV unless noted
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD.· MERRIMACK, NH 03054 TEL 603-424-2410· FAX603-424-3460
9-392
n n LL=::'._j
INTEGRATED CIRCUITS
-UNITRCDE
APPLICATION NOTE
U-136
PHASE SHIFTED, ZERO VOLTAGE TRANSITION DESIGN CONSIDERATIONS and the UC3875 PWM CONTROLLER
BILL ANDREYCAK
ABSTRACT
This Application Note will highlight the design considerations incurred in a high frequency power supply using the Phase Shifted Resonant PWM control technique. An overview of this switching technique including comparisons to existing fixed frequency non-resonant and variable frequency Zero Voltage Switching is included. Numerous design equations and associated voltage, current and timing waveforms supporting this technique will be highlighted. A general purpose Phase Shifted converter design guide and procedure will
be introduced to assist in weighing the various design tradeoffs. An experimental 500 Watt, 48 volt at 10.5
amp power supply design operating from a preregulated 400 volt DC input will be presented as an example. Considerations will be given to the details of the magnetic, power switching and control circuitry areas. A summary of comparative advantages, differences and tradeoffs to other conversion alternatives is included.
UC3875 CONTROL CIRCUIT SCHEMATIC
01 02 OS 04 T2
""
11
JI
iC3
..
··
··
cs cs C4
R12
SYNC CfS+
FREQ RAMP
Ol.Y Ml SIS
OLYC/D GND
Figure 1
9-393
APPLICATION NOTE
INTRODUCTION
The merits of lossless transitions using Zero Voltage Switching techniques have already been established in power management applications. (1-5] Effects of the parasitic circuit elements are used advantageously to facilitate the resonant transitions as opposed to being dissipatively snubbed. This resonant tank functions to position zero voltage across the switching device prior to turn-on, eliminating any power loss due to the simultaneous overlap of switch current and voltage at each transition. High frequency converters operating from high voltage input sources stand to gain significant improvements in efficiency with this technique. The full bridge topology as shown in figure 2. will be the specific focus of this presentation, with an emphasis placed on the fixed frequency, phase shifted mode of operation.
U-136 Conventional Full Bridge PWM Waveforms
A B
c
D
V1
Full Bridge Topology - General Circuit
T1
LR
01
Lo
02
Vo Co
Qo
Figure 2
SWITCH DRIVE COMMANDS
The diagonal bridge switches are driven together in a conventional full bridge converter which alternately places the transformer primary across the input supply, Vin, for some period of time, t(on) as shown in figure 3.
Power is only transferred to the output section during the ON times of the switches which corresponds to a specific duty cycle when operated at fixed frequency. Additionally, the complete range of required duty cycles is unique to the application, and can be estimated from the power supply input and output voltage specifications.
V2
Figure 3
Rather than driving both of the diagonal full bridge switches together, a deliberate delay will be introduced between their turn-on commands with the Phase Shifted approach. This delay will be adjusted by the voltage loop of the control circuitry, and essentially results as a phase shift between the two drive signals. The effective duty cycle is controlled by varying the phase shift between the switch drive commands as shown in figure 4.
Unique to this Phase Shifted technique, two of the switches in series with the transformer can be ON, yet the applied voltage to the transformer is zero. These are not diagonal switches of the full bridge converter, but either the two upper or two lower switches. In this mode the transformer primary is essentially short circuited and clamped to the respective input rail. Primary current is maintained at its previous state since there is no voltage available for reset to take place. This deadband fills the void between the resonant transitions and power transfer portion of the conversion cycle. Switches can be held in this state for a certain period of time which corresponds to the required off time for that particular switching cycle.
When the correct one of these switches is later turned off, the primary current flows into the switch output capacitance (Coss) causing the switch drain voltage to resonate to the opposite input rail. This aligns the opposite switch of the particular bridge "leg" with zero voltage across it enabling Zero Voltage Switching upon its turn ON.
9-394
APPLICATION NOTE
VEAR CT
SYNC FREQ
OUT A OUT B DLY AIB
OUT c
OUT D DLY CID PWM AID PWM BIC
Phase Shifted PWM Control Waveforms Figure 4
U·136
ZVS FUNDAMENTALS
An intentional dead-time can be introduced in the power conversion cycle whereby the switch remains off and is clamped at zero voltage by the resonant tank. Rather then tum the switch on instantly when zero voltage is attained, the switch is held off while the primary current circulates into the shorted primary through the body diode and the opposite leg switch, which is still on. This off time is used to fill in the voids between the point where zero voltage has been reached where the switch needs to turned on to achieve fixed frequency operation.
Fixed frequency operation is obtainable over an identified range of input voltages and output currents. For reference purposes, the variable frequency ZVS technique has similar limitations for proper operation which occur at minimum output load and maximum input line as shown in figure 5.
VPRI
zvs
IRANGE
I~
I
Figures
9-395
APPLICATION NOTE ZVS Limitations
U-136 Phase Shifted PWM Switch Orientation
D Q
D
c
-l
ZVS OCCURS
T1
LR
Lo
2
Vo
0
SWITCH POINT
Figure&
BB a
Qa
-l
PHASE SHIFTED FUNDAMENTALS
Switches within the Phase Shifted full bridge converter will be utilized differently than those of its nonresonant counterpart. Instrumental to this technique is the use of the parasitic elements of the MOSFET switch's constructuin. The internal body diode and output capacitance (Coss) of each device (in conjunction with the primary current) become the principal components used to accomplish and commutate the resonant transitions.
Figure7
age and magnetizing inductances and currents of the primary. The reflected secondary contributors to primary current are also shown for completeness, and divided into two components. The DC primary current (IP) is the secondary DC output current divided by the transformer turns ratio (N). The secondary AC current should also accounted for by multiplying the output inductance by the turns ratio squared (N"2), or dividing the secondary AC ripple current lsec(ac) by the turns ratio (N) as shown in figure 8.
CIRCUIT SCHEMATIC AND DESCRIPTION
Detailed operation of the Phase Shifted Converter operation will begin following a description of the circuit elements. The circuit schematic of this technique is shown in figure 7. including voltage and current designations.
The basic circuit is comprised of four switches labeled QA through QD and is divided up into two
"slheogws''n, tshheunritgehdt baynditslebftodhyanddioldeegs(.DEAatchhrosuwghitcDhDis) and parasitic output capacitance, (CA through CD). These have been identified separately to clarify the exact elements and current paths during the conversion interval.
A detailed model of the transformer primary section is presented which separately indicates the leak-
Primary Magnetic Components
LLKG
ET1
L M-AG-----~:~:_ 11 ·.
_
Figures
9-396
APPLICATION NOTE
INITIAL CONDITIONS : t = t(O)
The description of the Phase Shifted operation will begin with the conclusion of one power transfer cycle. This occurs when the transformer had been delivering power to the load and two of diagonal switches of the converter were conducting. The initial current flowing in the primary can be designated as lp(t(O)).
INITIAL CONDITIONS: time t<t(O)
OA = ON, Qo = ON
DA CA
De Cc
U-136
tjon wjl! refer to the lumped sum of these iDductors as the resonant inductance Lr In a practical application it may be difficult to accurately control the transformers leakage inductance within an acceptable ZVS range, necessitating an external "shim" inductor to control the accuracy. It's also possible that the transformer leakage inductance can be too low to provide the desired transition times for the application so an external inductor can be introduced to modify the resonant inductance.
With switch QD turned off, the primary current continues to flow using the switch output capacitance,
RIGHT LEG TRANSITION
time t(O)<t<t(1)
t OA ON, Qo = ON Cc = ~, Co ·
T1
LR
OA
D1
Lo
D2
Co
Vo
Qe
De Ce Qo
Do Co
-j
-j
DA CA
-l
De Cc
T1
LR
D1
Lo
D2
Co
Vo
Figure 9
RIGHT LEG RESONANT TRANSITION : INTER· VAL: t(O) <t <t(1)
The primary current flowing at time t(O) is equal to lp(t(O)) and was being conducted through the diagonal set of transistors QA in the upper left hand comer of the bridge and transistor QD in the lower right. Instantly, at time t(O) switch QD is turned off by the control circuitry which begins the resonant transition of the right hand leg of the converter.
The primary current flowing is maintained nearly constant at lp(t(O)) by the resonant inductance (Lp(res)) of the primary circuit, often referred to as the transformers leakage inductance. Since an external series inductance can be added to alter the effective leakage inductance yalue this presenta-
Qe
Ce Qo
Do Co
-l
-l
Figure 10
Coss to provide the path. This charges the switch capacitance of QD from essentially zero volts to the upper voltage rail, Vin+. Simultaneously, the transformer capacitance (Cxfmr) and the output capacitance of switch QC is discharged as its source voltage rises from the lower to the upper rail voltage. This resonant transition positions switch QC with no drain to source voltage prior to turn-on and facilitates lossless, zero voltage switching.
9-397
APPLICATION NOTE
The primary current causing this right leg transition can be approximated by the full load primary current of IP(t(O)). The small change due to the barely resonant circuit contribution is assumed to be negligible in comparison to the magnitude of the full load current.
During this right leg transition the voltage across the transformers primary has decreased lorn Vin to zero. At some point in the transition the primary voltage drops below the reflected secondary voltage, Vout*N. When this occurs the primary is no longer supplying full power to the secondary and the output inductor voltage changes polarity. Simultaneously, energy stored in the output choke begins supplementing the decaying primary power until the primary contribution finally reaches zero.
Once the right leg transition has been completed there is no voltage across the transformer primary. Likewise, there is no voltage across the transformers secondary winding and no power transferred, assuming ideal conditions. Note that the resonant transition not only defines the rate of change in primary and secondary voltages dV/dt, but also the rate of change in current in the output filter network, dl/dt.
U-136
previously turned ON and switch QA will now be turned OFF. The primary current will continue to
CLAMPED FREEWHEELING INTERVAL
time t(1)<1<1(2) OA · ON, Qc · ON, De · ON
DA CA
De Cc
T1
LR
Lo
Co
Vo
Ce Qo
Do Co
Qe
--j
--j
CLAMPED FREEWHEELING INTERVAL Time t(1) <t <t(2)
Once the right leg transition is complete the primary current free wheels through transistor QA and the body diode of switch QC. The current would remain constant until the next transition occurs assuming that the components were ideal. Switch QC can be turned on at this time which shunts the body diode with the FET Rds(on) switch impedance thus lowering conduction losses. Although current is flowing opposite to the normal convention (source to drain). the channel of QC will conduct and divide the current between the switch and body diode.
LEFT LEG TRANSITION : Time t(2) <t <t(3)
At time t(2) a residual current was flowing in the primary of the transformer which is slightly less than IP(t(O)) due to losses. Switch QC has been
Figure 11
flow but the path has changed to the output capacitance (Coss) of switch QA instead of its channel. The direction of current flowing causes the drain to source voltage of switch QA to increase and lowers its source from the upper to lower rail voltage. Just the opposite conditions have occurred to switch QB which previously had the full input across its terminals. The resonant transition now aligns switch QB with zero voltage across it, enabling lossless switching to occur.
Primary current continues to flow and is clamped by the body diode of switch QB, which is still OFF. This clamping into a short circuit is a necessary condition for fixed frequency, zero voltage switching. Once switch QB is turned ON, the transformer primary is placed across the input supply rails since switch QC is already ON and will begin to transfer power. Although zero voltage switching has already been established, turning ON switch QB the instant it reaches zero voltage will cause variable frequency operation.
9-398
APPLICATION NOTE
U-136
LEFT LEG TRANSITION time 1(2)<1<1(3)
t OA · OFF, Qc = ON, De · ON Ca = +, CA =
De Cc
T1
LR
VO
Qa
Co
-J
Figure 12
POWER TRANSFER INTERVAL
Time t(3) <t <1(4)
This interval of the phase shifted cycle is basically identical to that of conventional square wave power convesion. Two diagonal switches are ON which applies the full input voltage across the transformer primary. Current rises at a rate determined by Vin and the series primary inductance, however starts at a negative value as opposed to zero. The current will increase to a DC level equal to the output current divided by the turns ratio, loL't/N. The two time variant contributors to primary current are the magnetizing current (lmag) and the output inductor magnetizing contribution reflected to the primary, LoutfNA2. The exact switch ON time is a function of Vin, Vout and N the transformer turns ratio, just as with conventional converters.
POWER TRANSFER INTERVAL
time 1(3)<1<1(4)
Qa = ON, Qc = ON
Note that this left leg transition will require more time to complete than the right leg transition. Conduction losses in the primary switches, transformer winding and interconnections result in a net DC voltage drop due to the flowing primary current. Energy stored in the series resonant inductor and magnetizing inductance is no longer ideally clamped to zero voltage. This loss, in addition to the losses incurred during the previous transition, reduce the primary current below its initial (IP(t(O)) value, thus causing a longer left leg transition time than the right leg.
Unlike conventional power conversion, one transistor in the diagonal pair of the phase shifted full bridge converter is ON just before power is transferred which simplifies the gate drive. An additional benefit is realized by designating these commutating switches as the high side switches of the converter, usually far more difficult to drive than their lower side counterparts.
De Cc
T1
LA
D1
Lo
D2
Vo
Qo
Do Co
Qa
-J
-J
Figure 13
9-399
APPLICATION NOTE
SWITCH TURN OFF; TIME t(4)
One switching cycle is concluded at time t(4) when QC the upper right hand comer switch is turned OFF. Current stops flowing in QC's semiconductor channel but continues through the parasitic output capacitance, Coss. This increases the drain-tosource voltage from essentially zero to the full input supply voltage, Vin. The output capacitance of the lower switch in the left hand leg (QD) is simultaneously discharged via the primary current. Transistor QD is then optimally positioned for zero voltage switching with no drain-to-source voltage.
The current during this interval is assumed to be constant, simplifying the analysis. In actuality, it is slightly resonant as mentioned in the right leg transition, but the amplitude is negligible in comparison to the full load current. The power conversion interval is concluded at this point and an identical analysis occurs as for the opposite diagonal switch set which has thoroughly been described for the switch set QA and OD.
OPERATIONAL WAVE FORMS
VA
0
Ve
0
VPRI
0
t---
H
I-H t--
I---
H
H
IPRI
~ N
0
I--
1--' N
1014
0
1015 0
t---4 H
1--
'
~ N
l - - ' 1"--1
I--
J...---
~
I\~
t=
012 3 4
Figure 14
U-136
RESONANT TANK CONSIDERATIONS
The design of the resonant tank begins with the selection of an acceptable switching frequency; one selected to meet the required power density. Second, the maximum transition time must also be established based on achievable duty cycles under all operating conditions. Experience may provide the best insight for acceptable results.
The maxjmum transition time will occur during the conveners left leg transition operating at the mjnjmum output load current.
RESONANT CIRCUIT LIMITATIONS
Two conditions must be met by the resonant circuit at light load, and both relate to the energy stored in the resonant inductor. One, there must be enough inductive energy stored to drive the resonant capacitors to the opposite supply rail. Two, this transition must be accomplished within the allocated transition time. Lossy, non-zero voltage switching will result if either, or both are violated. The first condition will always be met when the latter is used as the resonant circuit limitation.
Designers can argue that some switching loss may be of little consequence in a practical application at very light loads - especially considering that there is a significant benefit at heavy loads; While this may be a pragmatic approach in many applications, and a valid concern, this presentation will continue using the fully lossless mode as the ultimate design goal.
The stored inductive energy requirement and specified maximum transition time have also defined the resonant frequency (Wr) of the tank circuit. Elements of this tank are the the resonant
inductor (Lr) and capacitor (Cr), formed by the two
switch output capacitors, also in parallel with the transformer primary capacitance Cxfmr. The maximum transition time cannot exceed one-fourth of the self resonant period, (four times the self resonant frequency) to satisfy the zero voltage switching condition.
The resonant tank frequency, Wr :
Wr=
(
Lrx
1 Cr)
A
0.5
t ( max ) transition= 4 x Wr
Coss, the specified MOSFET switch output capacitance will be multiplied by a 4/3 factor to accommodate the increase caused by high voltage operation. During each transition, two switch capacitances are driven in parallel, doubling the total capacitance to 813 · Coss. Transformer capacitance (Cxfmr) must also be added as it is NOT negligible in many high frequency applications.
9-400
APPLICATION NOTE
Theresonantcapacttance,Cr:
Cr= [ ( 38 Coss}+ Cxfmr)
The capacttive energy required to complete the transttion , W(Cr) is:
4 W( Cr) = x Cr x VPri"2
This energy can also be expressed as:
W( Cr)= [ ( ~ x Coss)+ Cxfmr) x Vin"2
STORED INDUCTIVE ENERGY
The energy stored in the resonant inductance must be greater than the energy required to charge and discharge the FET output and transformer capacitances of the leg in transttion wtthin the maximum transttion time.
Inside the transformer, all of the energy is stored in the leakage inductance since the secondary current has clamped the transformers primary voltage to essentially zero. This causes high circulating primary current (as shown in figure 8) in the physical winding but has no effect on the stored energy used to perform the ZVS transition. More detail about the tradeoffs and design optimization is presented in the Design Procedure.
The energy stored in the resonant inductor, Lr:
W(LI) =~ x Lr x lpri "2
RESONANT CIRCUIT SUMMARY
There are several ways to arrive at the solutions for the resonant inductor value and minimum primary current required for any application. Each of these is based upon the following fundamental relationships.
The resonant tank frequency must be at least four times higher than the transition time to fully resonate within the maximum transition time t(max) at light load.
Fres =4 x t ( max )
Fres = -t(-r1e-s) or
t(re
s
)
=Fr1-e-s
-
(4xt
(
1 max))
where Wr= 2 x 7t x Fres
Wr=~
t(res)
U-136
Reorganizing and combining these relationships;
Wr=[(4~~(x~~))]
Wr
1t
(2xt(max))
The resonant radian frequency (Wr) is related to the resonant components by the equation:
"2 Wr=
(
1 Lrx Cr)
Both sides of this can be squared to simplify the calculations and reorganized to solve for the exact resonant inductor value.
Lr=
1
( Wr"2 x Cr)
Previously outlined relationships for Wr and Cr can be introduced to result in the following specific equation.
Lr=
1
]"2 J [< - [
( 2
71
xt(max)
x 38 x Coss)+Cxfmr
Note that this figure indicates the exact resonant inductor value required to satisfy only the task of resonant transitions. This resonant inductor is in series with the transformer primary hence also defines the maximum primary current slew rate, dlldt as a function of input voltage.
d /Pri Vin
<it=u
If the resonant inductor value is too large it may take too long to reach the necessary load current within the conversion cycle. The calculated inductor value satisfies the light load condition, however full load operation must also be evaluated. Details of possible solutions to this are highlighted in the Practical Applications section of this paper.
STORED ENERGY REQUIREMENTS
As detailed, the energy stored in the resonant inductor must be greater than the capacitive energy required for the transition to occur within the allocated transition time. The governing equations are summarized below.
4 "2, x Lrx /Pri( min) A2 > ~ x Crx Vin (max) or
Lrx /Pri(min) A2 > Crx Vin (max) A2
Since Cr and Vin are known or can be estimated for a given application, this term becomes a constant and Lr has been quantified.
9-401
APPLICATION NOTE
MINIMUM PRIMARY CURRENT
The minimum primary current required for the phase shifted application can now be determined by reorganizing the previous equation.
= fPri ( min )
[
(
Crx VinA2 Lr
)]
1l.5
This value can be supported by the calculating the average current required to slew the resonant capacitor to the full rail voltage. Although this figure will be lower that IP(min) it can be used as a confirmation of the mathematics.
Vin /R( average)= Crx t( maxi
Obtaining the necessary amount of primary current can be done in several ways. The most direct approach is to simply limit the minimum load current to the appropriate level. One alternative, however, is to design the transformer magnetizing inductance accordingly. Also assisting the magnetizing current is the reflected secondary inductor current contribution which is modeled in parallel. Any duty cycle variations modifying the peak charging current must also be taken into account.
Generally the magnetizing current alone is insufficient in many off-line high frequency converters. The transformer is usually cores loss limited which means numerous primary turns and a high magnetizing inductance. Shunting the transformer pri-
U-136
mary with an external inductor to develop the right amount of primary current is one possibility. Incorporating the output filter inductor magnetizing current to assist resonance on the primary side is also an alternative.
PHASE SHIFTED PWM CONTROL CIRCUITRY
Probably the most critical control aspect in the phase shifted PWM technique is the ability to span the full 0 to 180 degree phase shift range. Falling short of performance on either end ofthe spectrum can place unnecessary burdens on the fault protection circuitry or primary switches. Loss of control at either extreme will result in catastrophic consequences by simultaneously turning on both transistors in a given "leg" of the converter. The UC3875 Phase Shifted controller features the required circuitry to deliver both zero and effectively full duty cycle - effortlessly. Additionally, the UC3875 controller is utilized to perform the necessary control, decoding, protection and drive functions for this application. Peak current mode control is implemented for this example although the IC is equally suited for conventional voltage mode control, with or without input voltage feed forward. When used in current mode, the IC accepts a zero to 2.7 volt amplitude maximum current senses input and makes adding slope compensation a simple function.
FRie~ 6 High Spead Oscillator
CLOCK W.1r l - - - - - ' SYNC
SLOPE 18 s~~:: g,·~:~~~o:u:n
UC3875 Block Diagram
Ve OUT A PWR GND
OUT B
..____ _,.___ __,__
DELAY
_,......-1,~SET
A·B
E/A OUT 1~2!1---__....., (COMP) E/A(·) 131---1-~,
EIA(+) 141---tt..-
.____..___ DELAY -+---~lf~~J
C/S(+)
Figure 16
~GND
9-402
APPLICATION NOTE
UNITRODE UC3875 PHASE SHIFTED PWM
CONTROL IC - BLOCK DIAGRAM
A synchronizable oscillator is programmed by a resistor capacitor network from the frequency set pin to ground. Synchronization is performed by driving the SYNC pin from another UC3875 or external circuitry. The precision 5.0 volt bandgap reference is available to program the noninverting input of the error amplifier as well as optional external functions. Output regulation is achieved using the 7 MHz gain-band width on-board error amplifier which feeds the high speed PWM circuitry Soft starting is accomplished with a capacitor to ground which gradually increases the error amplifier output, corresponding to pulse width, phase shift or peak current, depending on the exact implementation. This sighal is compared to the Ramp input of the IC having a usable input range from zero to 2.7 volts.
Delays between the output drive commands to facilitate Zero Voltage Switching are programmed at the Delay Set inputs. One unique feature of the UC3875 is the ability to separately program the AB output delays differently from the C-D outputs. This capability accommodates the different primary currents during one switching cycle which cause and result in different resonant transition times between the leading and falling edges. Inability to program each of these durations will generally result in lossy, non-zero voltage switching of the full bridge converters switches under some operating conditions.
The four UC3875 output totem poles can each deliver a two amp peak gate drive current, more than adequate in a high frequency transformer coupled gate drive application. To minimize noise transmitted back to the analog circuitry, the output section features its own collector power supply (Ve) and ground (PGND) connections. Local decoupling capacitors and series impedance to the auxiliary supply further enhances performance.
Fault protection is established by the programmable current limit circuitry. Full cycle restart corresponding to the time programmed by the soft start interval minimizes power dissipation in a short circuited output.
U-136
TYPICAL APPLICATION CIRCUIT SCHEMATIC
SUMMARY
The fixed frequency phase shifted control technique of the full bridge converter offers numerous performance advantages over the conventional approach. switching losses due to the simultaneous overlapof voltage and current disappear along with the dissipative discharge of the FET output capacitance. EMl/RFI is significantly lower, also due to the "soft" switching characteristics which incorporate parasitic elements of the power stage acvantageou sly For most applications, there is little reason to consider the traditional square wave counterpart of theis phase shifted PWM technique for future designs.
Very high frequency operation of this technique, beyond 500 KHz, is probable above the optimal operating point. Transition times quickly erode the usable duty cycle to a point where the transformer turns ratio has been compromised. This could result in unreasonably high primary currents and repower loss in the switches. Any incremental gains in cost or power density by reducting the size of the output filter are probably nullified by the needs for larger MOSFETs and heatsinks. This phase shifted PWM technique does excel in the overall majority of mid to high power, off-line applications. Peak efficiency will be obtained in applications with moderate load ranges, however excellent results can also be obtained in most designs with load ranges of ten-to one. A subgroup of applications may exist where non ZVS operation extremely light loads is acceptable, especially when the advantages under all other operating conditions are considered. Additionally, the Unitrode UC3875 Phase Shifted Controlller IC has been introduced to simplify the control circuit design challenge. Features of the UC3875 include 2 MHz operation and four 2 amp peak totem-pole output drivers for high frequency applications. Separate programming of the different AD and BC leg transition intervals has made available to optimize converter performance.
Finally, the flexible control logic permits current mode or voltage mode control, with or without input voltage feed forward. The complexity of control, drive and protection of the fixed frequency phase shifted converter has been fully addressed in a single integrated solution.
9-403
APPLICATION NOTE
UC3875 Phase Shifted PWM Converter Control and Output Circuit Schematic
Q·
PIO
v.
T4
L1 T1 Ct3
U-136
R18
R19
014
U3
Q8
OD
C18 C19 013 R20
Figure 17
UC 3875 Phase Shifted PWM Converter Control and Drive Circuit Schematic
c·i "'
T3
OUT C
OUT D
T1
~I
··
co C5 c·
POND SYNC FREQ
DlYC/D ONO
Figure 18
9-404
APPLICATION NOTE
UC387S F.B.P.S. CONVERTER
LIST OF MATERIALS
CAPACITORS
All are 20 VDC Ceramic Monolithic or Multilayer UNLESS "*" indicated.
C1= 1 µF C2= 47 µF/2SV ELECTROLYTIC C3= 1 µF C4= 1 µF CS= 7S pF/16V POLYSTYRENE C6= 0.001 µF C7, 8= 0.01 µF C9= 470 pF C10= 0.1 µF C11= 1 µF/4SOVDC POLY C12= 47µ/4SOVDC ELECTROLYTIC
C13= 1.2µF/4SO voe POLY
C14= 1µF/1 OOVDC C1 S, 16= 220µF/63VDC ELECTROLITIC C17=TBD C18= 1µF C19= 22 µF/2SVDC ELECTROLITIC C20= 1 µF C21= 2.7 nF/200V POLY/low ESL&ESR
DIODES 01 -8= 1NS820 3N20V SCHOTTKY 09-12= 1N4148 013= 12V 3W ZENER 014, 1S= 1SN200V FAST RECOVERY
INDUCTORS L1=47µH/3A L2= 1OOµH/1 SA
MOSFET TRANSISTORS QA-D=IRF840 NMOS
Bill Andreycak I UICC 2124/93
U-136
RESISTORS
All are 1/2 Watt, 1%, Metal Film UNLESS "*" indicated
R1= 7SK R2=2K R3=3K R4= 470 Ohm RS=3K R6= 100 Ohm R7, 8= 6.8K R9= 43K R10= 1SOK R11 , 12= 10 Ohm R13= 20 Ohm R14-17= 10K R18= 3.6K, 1WATT R19= 36K R20= 1K R21=TBD R22=TBD R23= 110 Ohms/SW Carbon
TRANSFORMER T1= 1 SENSE T2, 3= GATE DRIVERS T4= MAIN XFMR
INTEGRATED CIRCUITS U1= UC387S PMW U2=0PTO U3= UC19432
9-405
APPLICATION NOTE
One Switching Cycle
VA
100V/Div
IPAI
2A/Div
Vs 100V/Div
Figure 19
VA
100V/Div
Primary Waveforms
IPRI
2A/Div
VB
100V/Div
Figure 20
Secondary Waveforms
IDouT 10A/Div
tNour 100mV/Div
VsEc 50V/Div
U-136
REFERENCES
1. STEIGERWALD, R. and NGO, K; "Full Bridge Lossless Switching Converter"; United States Patent #4,864,479
2. DALAL, D.; "A 500 KHz Multi-Output Converter rogrammed by theft start interval minimizes power dissipation in twith Zero Voltage Switching"; IEEE 1990
3. FISHER, NGO and KUO; "A 500 KHz, 250 W DC-DC Converter with Multiple Outputs COntrolled by Phase SHifted PWM and Magnetic Amplifiers " HFPC 1988"; HFPC 1988
4. ANDREYCAK, W. "Zero Voltage Switching Resonant Power Conversion"; UNITRODE Power Supply Design Seminar SEM-700, 1990
5. MWEENE, WRIGHT and SCHLECHT, "A 1 KW, 500 KHz Front-End Converter for a Distributed Power Supply System"; IEEE 1989
6. ANDREYCAK, W. "Controlling Zero Voltage Switched Power Supplies"; HFPC Proceedings 1990
7. SABATE', VLATKOVIC', RIDLEY, LEE and CHO; "Design Considerations for High Voltage, High Power, Full Bridge, Zero Voltage Switched PWM Converter; IEEE APEC 1990
8. LOFT!, SABATE', and LEE; "Design Optimization of the Zero VOitage Switched PWM Converter"; VPEC Seminar 1990
9. CHEN, LOFT! and LEE; "Design Tradeoffs in 5V Output Off-line ZVS PWM Converters"; Proceedings of the International Telecommunications Energy Conference; Kyoto, Japan 1991
ACKNOWLEDGMENTS
This Application Note is an edited version of a paper presented at the 1992 High Frequency Power Conference sponsored by lntertec Communications and was first published in the Conference Proceedings.
The author acknowledges and appreciates the assistance of John A. O'Connor during the course of this project.
The works of the individuals listed in the references including Dr. Fred Lee from Virginia Power Electronics Center at Virginia Tech. are applauded.
Figure 21
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD.· MERRIMACK, NH 03054 TEL (603) 424-2410 ·FAX (603) 424-3460
9-406
n n Ll=:!J INTEGRATED CIRCUITS
-UNITROCE APPLICATION NOTE
PRACTICAL CONSIDERATIONS IN HIGH PERFORMANCE MOSFET, IGBT and MCT GATE DRIVE CIRCUITS
BILL ANDREYCAK
U-137
INTRODUCTION
The switchmode power supply industry's trend towards higher conversion frequencies is justified by the dramatic improvement in obtaining higher power densities. And as these frequencies are pushed towards and beyond one megahertz, the Mosfet transition periods can become a significant portion of the total switching period. Losses associated with the overlap of switch voltage and current not only degrade the overall power supply efficiency, but warrant consideration from both a thermal and packaging standpoint. Although brief, each of the Mosfet switching transitions can be further reduced if driven from from a high speed, high current totem-pole driver- one designed exclusively forthis application. This paper will highlight three such devices; the UC1708 and UC1710 high current Mosfet driver !Cs, and the UC1711 high speed driver. OtherMosfet driver /Cs and typical application circuits are featured in UNITRODE Application Note U-118.
EFFECTIVE GATE CAPACITANCE
The Mosfetinputcapacitance (Ciss) is frequently misused as the load represented by a power mosfet to the gate driver IC. In reality, the effective input capacitance of a Mosfet (Ceff) is much higher, and must be derived from the manufacturers' published total gate charge (Qg) information. Even the specified maximum values of the gate charge parameter do not accurately reflect the driver's instantaneous loads during a given switching transition. Fortunately, FET manufacturers provide a curve for the gate-tosource voltage (Vgs) versus total gate charge in their datasheets. This will be segmented into four time intervals of interest per switching transition. Each ofthese will be analyzed to determine the effective gate capacitance and driver requirements for optimal performance.
adjusting the gate charge numbers accordingly. Both turn-on and turn-off trasnsitions are shown with the respective drain currents and drain-to-source voltages.
TURN-ON WAVEFORMS Gate voltage vs time
Qgs Qgd
Vgs
Vgs (th)
Inadequate gate drive is generally the result of underestimating the effective load of a power mosfet to its driver.
TOTAL GATE CHARGE (Qg)
ll\J/ to t1 t2
ta t4 Id
First, a typical high power Mosfet "Gate Charge versus Gate-to-Source Voltage" curve will be examined. An IRFP460 device has been selected and this curve is applicable to most other Fet devices by
Figure 1.
9-407
APPLICATION NOTE
INTERVAL t0-t1
INTERVAL t2-t3
U-137
The time required to bring the gate voltage from zero to its threshold Vgs(th) can be expressed as a delay time. Both the voltage across the switching device and current through it are uneffected during this interval.
INTERVAL t1-t2
Beginning at time t2 the drain-to-source voltage starts to fall which introduces the "Miller" capacitance effects (Cgd) from the drain to the Mosfet gate. The result is the noticeable plateau in the gate voltage waveform from time t2 until t3 while a charge equal to Qgd is admitted. It is here that most drive circuits are taxed to their limits. The interval concludes at time t3 when the drain voltage approaches its minimum.
This period starts at time t1 when the gate voltage has reached Vgs(th) and drain current begins to flow. Current continues to rise until essentially reaching its final value at time t2. While this occured, the gate to source voltage had also been increasing. The drain-to-source voltage remains unchanged at Vds(off). Power in the Mosfet is wasted by the simultaneous overlap of voltage and current.
INTERVAL t3-t4
During this final interval of interest the gate voltage rises from the plateau of the prior region up to its final drive voltage. This increasing gate voltage decreases Rds(on), the Mosfet drain-to-source resistance. Bringing the gate voltage above 10 to 12 volts, however, has little effect on further reducing Rds(on).
SUMMARY OF INTERVAL WAVEFORMS AND DRIVER LIMITATIONS
INTERVAL
Vgs(t)
ID(t)
Vds(t)
DRIVER LIMITATIONS
t0-t1 t1-t2 t2-t3 t3-t4
0-threshold th rs-plateau V(plateau) rising
0 rising lon(dc) lon(dc)
Vds(off) Vds(off) falling lon*Rds(t)
Slew rate (dv/dt) Slew rate (dv/dt) Peak current l(max) Peak I & dv/dt
TURN-OFF WAVEFORMS Gate voltage vs time
Qgd Qgs _.j+--+!
Vgs
Vgs (th)
t4
INTERVAL t4-t3 The beginning of the tum-off cycle can be described as a delay from the final drive voltage (Vgs(on)) the the plateau region. Both the drain voltage and current waveforms remain unchanged while the devices effective resistance ( Rds(on) ) increases as the gate voltage decreases.
INTERVAL t3-t2 Once the plateau is reached at time t3, the gate voltage remains constant until time t2. Gate charge due to the Miller effect is being removed, an amount equal to Qgd. The drain voltage rises to its off state amplitude, Vds(off), while the drain current continues to flow and equals l(on). This lossy transition ends at time t2.
Figure 2
The intervals during turn-off are basically the same as those described for tum-on, however the sequence and corresponding waveforms are reversed.
INTERVAL t2-t1 Once the Miller charge is completely removed, the gate voltage is reduced from the plateau to the threshold voltage causing the drain current to fall from l(on) to zero. Transition power loss ends at time t1 when the gate threshold is crossed.
INTERVAL t1-t0 This brief period is of little interest in the tum-off sequence since the device is off at time t1.
9-408
APPLICATION NOTE
U-137
SUMMARY OF INTERVAL WAVEFORMS AND DRIVER LIMITATIONS
INTERVAL
Vgs(t)
ID(t)
Vds(t)
DRIVER LIMITATIONS
t4-t3
falling
lon(dc)
Ion* Rds(t)
Peak I and dv/dt
t3-t2
V(plateau)
lon(dc)
falling
Peak Current I (max)
t2-t1
Vplat-thrsh
falling
Vds(off)
Slew rate (dv/dt)
t1-t0
thrsh-0
0
Vds(off)
Slew rate (dv/dt)
FET Transition Power Loss
Ploss = Vds( off)*I( on)*t(trans)/t(period)
During each of the FET turn-on and tum-off sequences power is lost due to the switching device's simultaneous overlap of drain - source voltage and drain current. Since both the FET voltage and current are externally controlled by the application, the driver IC can only reduce the power losses by making the transition times as brief as possible. Minimization of these losses simply requires a competant driver IC, one able to provide high peak currents with high voltage slew rates.
A review of the prior transition waveforms indicates that power is lost between the times of t1 and t3. While t2 serves as the pivot pointforwhich waveform is rising orfalling, as the equations show its irrelavent in the power loss equation. For the purpose of brevity, the waveform of interest can be approximated as a triangle while the other waveform is constant. The duration between times t1 and t3 can now be defined as the nettransition time, t(tran), with a conversion period of t(period)
During the two intervals from t1 to t3:
Ploss=
0.5 * l(on) * Vds(off) * t(2-1) t(period)
Ploss=
0.5 * Vds(off) * l(on) *t(3-2) t(period)
Combininig the two equations with t(tran) = t3-1 results in a net loss of:
0.5 * Vds(off) * l(on) * t(trans) Ploss=
t(period)
Since these loses are incurred twice percycle, first at tum-on and then again at tum-off, the net result is a doubling of the power loss.
This relationship displays the need for fast transitions at any switching frequency, and is of significant concern at one megaHertz. Minimization of the FET transition power loss can be achieved with high current drivers.
GATE CHARGE
Each division of the transition interval has an associated gate charge which can be derived from the FET manufacturers datasheets. Since there are three basic shapes to the Vgs curve, the interval from tO to t1 can be lumped together with that of the t1 to t2 period. For most large FET geometries, the amount of charge in the to to - t1 span is negligible anyway. This simplification allows an easy calculation of the effective gate capacitance for each interval along with quantifying the peak current required to traverse in a given amount of time.
Charge can be represented as the product of capacitaoce multiplied by voltage, or current multiplied by time. The effective gate capacitance is determined by dividing the required gate charge (Qg) by the gate voltage during a given interval. Likewise, the current necessary to force a transition within a specified time is obtained by dividing the gate charge by the desired time.
Cgs (effective)= delta Qg I delta Vgs
lg(required) =delta Qg I t(transition)
UC1710 The "MILLER KILLER"
High peak gate drive currents are desirable in paralleled FET applications, typical of a high power switching section or power factor correction stage. Dubbed as "the Miller Killer'', the UC1710 boasts a guaranteed 6 amp peak output current. This hefty driver current minimizes the FET parasitic "Miller'' effects which would otherwise result in poor transi-
9-409
APPLICATION NOTE
tion performance. Higher currents are possible with this driver, however the limiting factor soon becomes the parasitic series inductance of the FET package (15 nH) and the layout interconnection of 20 nH/inch. An RF type arrangement of the PC board layout is an absloute MUST to realize this device's full potential.
UC 1708 BLOCK DIAGRAM
U-137
ENABLE E LOGICGND
UC 1710 BLOCK DIAGRAM
INTERNALLY CONNECTED " - - - - "" - - - - INT-PACKAGE - - - - - - - - - - - - - - - - 1
OUTPUT BIAS
NON--INV
"""'
ONV f l - - - + - {
'"'UT Lg~c [ ) - - - - + - - - -........- '
1_________ _ l~TERtlff-~~~~~CT£0 ______________ 1
The UC1710 has "no-load" rise and fall times of 20 nanoseconds (or less) which do not change significantly with any loads under 3 nanoFarads. It's also specified into a load capacitance of 30 nanoFarads, roughly equivalent to what is represented by three paralleled "size 6" FET devices. Propagation delays are brief with typical values specified at 35 nanoseconds from either input to a ten percent change in output voltage.
PWRGNO B
The UC1708 is a unique blend of the high speed attributes of the UC1711 along with the higher peak current capability of the UC1710. This dual non inverting driver accepts positive TIUCMOS logic from control circuits and provides 3 amp peak outputs from each totem pole.
Propagation delays are under25 nanoseconds while rise and fall times typically run 35 nanoseconds into 2.2 nanofarads. The output stage design is a "no float" version which incorporates a self biasing technique to hold the outputs lowduring undervoltage lockout, even with Vin removed.
In the 16 pin DIL package, the device features a remote ENABLE and SHUTDOWN function in addition to seperate signal and power grounds. The ENABLE function places the device in a low current standby mode and the SHUTDOWN circuitry is high speed logic directly to the outputs.
PARAMETER
UC1708/1710/1711 PERFORMANCE COMPARISON TABLE 1
LOAD
UC1708
UC1710
UC1711
Propagation Delay t(plh) input to 10% output
Raise time t(tlh) 10% to 90% rise
Propagation Delay t(phl) input to 90% output
Fall Time t(thl) 90% to 10% fall
0
25
30
10
1.0 nF
25
-
15
2.2 nF
25
30
20
30 nF
-
30
-
0
25
20
12
1.0 nF
30
-
25
2.2 nF
40
25
40
30 nF
-
85
-
0
25
30
3
1.0 nF
25
-
5
2.2 nF
25
30
30 nF
-
30
-
0
25
15
7
1.0 nF
30
-
25
2.2 nF
40
20
40
30 nF
-
85
-
9-410
APPLICATION NOTE
TRANSITION PERFORMANCE
Using the table above, the driver output slew rates and average current delivered can be calculated. The figures can be compared to lower power opamps or comparators to gain a perspective on the relative speed of these high performance drivers.
U-137
Optimization of a driver for this type of application can be difficult. In general, the MOSFET driver IC output stage is designed to switch as fast as the manufacturer's process will allow.
CROSS CONDUCTION
The UC 1708 delivers output slew rates (dv/dt) in the order of 300 to 480 volts per microsecond, at average load currents of under one amp, depending on the load. The high speed UC1711 exhibits similar characteristics under loaded conditions, but can achieve a no load slew rate of over 1700 volts per microsecond - nearly 2 volts per nanosecond.
For higher power applications, the UC1710 "Miller Killer" will produce an average current of 4.5 amps AT slew rates of 150 volts per microsecond. With lighter loads it will deliver an average current of 1.5 amps at a slew rate of approximately 500 volts per microsecond. In most applications, the UC171 Owill easily outperform "homebrew" discrete mosfet transistor totempole drive techniques.
Each device in this new generation of MOSFET drivers is significantly more responsive than the earlier counterparts for a given application - whether it's higher speed (UC1711 ), higher peak current (UC1710) or a combination of both (UC1708).
There are numerous tradeoffs involved in the design of these drivers beyond the obvious choices of number of outputs and peak current capability. Crossconduction is defined as the conduction of current through both of the totem pole transistors simultaneously from Vin to ground. It is an unproductive loss in the output stage which results in unnecessary heating of the driver and wasted power. Cross conduction is the result of turning one transistor ON before the opposing one is fully off, a compromise often necessary to minimize the input to output propagation delays.
An interesting observation is that cross-conduction is less of a concern with large capacitive loads ( FETs ) than with unloaded or lightly loaded driver outputs. Any capacitive load will reduce the slew of the output stage, slowing down its dv/dt. This causes a portion of the cross conduction cu rrentto flow from the load, rather than from the input supply through the driver's opposite output transistor. The power loss associated with a drivers inherent cross-conduction is unchanged with large capacitive loads, however it is not caused by a "shoot-through" of supply current.
DRIVER CONSIDERATIONS
DRIVER PERFORMANCE
As previously demonstrated, the ideal MOSFET gate drive IC is a unique blend of both high speed switching and high peak current capability. Initially, the high speed is required to bring the gate voltage from zero to the plateau, but the current is low. Once the plateau is intersected, the driver voltage is fairly constant, and the IC must switch modes. Instantly, the driver current snaps to its maximum as charge is injectedtoovercometheFET'sMillereffects. Finally, a combination of both high slew rate and high current is needed to complete the gate drive cycle.
At turn-off this sequence is reversed, first demanding both high slew rate and high current simultaneously. This is followed by the plateau region which is limited only by the maximum driver current. Finally, there is high speed discharge of the gate to zero volts.
There are a variety of applications for MOSFET drivers - each with its own unique set of speed and peak current requirements. Most general purpose drivers feature 1.5 amp peak totem-pole outputs which deliver rise and fall times of approximately 40 nanoseconds into 1 nanoFarad. Propagation delays are in the neighborhood of 40 to 50 nanoseconds, making these devices quite adaptable to numerous power supply and motor control applications. These specifications can be used for a comparison to those of a new series of higher speed and higher current devices, specifically, the UC1708, UC1710 and the UC1711 power MOSFET drivers. Each member in this group of "third" generation driver ICs features significant performance improvements over their predecessors with one parameter optimized for a specific set of applications.
9-411
APPLICATION NOTE
MOSFET DRIVER IC FEATURE AND PERFORMANCE OVERVIEW TABLE2.
Feature
UC1708
UC1710
Number of outputs Peak output current (per output)
2
1
3A
6A
Noninverting input-output logic Inverting input-output logic
YES
YES YES
Maximum supply voltage Vee Typical supply current Ice (1.)
35V 16ma
20V 30ma
Remote Enable Shutdown Input
YES YES
YES (2)
Seperate grounds, signal and power Seperate Vin and Ve pins
YES (3)
YES (3) YES (3)
8 pin Dllpackage 16 pin DIL package 5 pin T0-220 package
YES YES
YES YES YES
Note 1. Typical Ve plus Vee current measured at 200KHZ, 50 % duty cycle and no load Note 2. Using the device's other input Note 3. Package dependant
U-137
UC1711 2
1.5 A YES 40V 17ma
YES YES
PROPAGATION DELAYS
The power supply industry's trend towards higher
power densities has thrust switching frequencies
well beyond one megaHertz in many low to medium
power systems. With a one microsecond total con-
version period, or less, the FET switching transitions
should be in the order of low tens of nanoseconds
to yield high efficiency. Additionally, the propagation
delays from the driver input to output should be
around ten nanoseconds for quick response.
A -INPUT
UC1711
The UC1711 device features typical propagation delays of three and ten nanoseconds at no load, depending on the transition. Coupled with dual 1.5 amp peak totem-pole outputs, this device is optimized for high frequency FET drive applications. Its B
-INPUT
all NPN Schottky transistor construction is not only fast, but radiation tolerant as well.
9-412
UC1711 BLOCK DIAGRAM
3K 2.SK
OUTPUT A
APPLICATION NOTE
GATE DRIVE POWER CONSIDERATIONS
Perhaps the most popular misconception in the powersupply industry is that a FET gates require NO power from the auxiliary supply - that both tum-on and turn-off are miraculously power free. Another fallacy is that the driver consumes all the measured supply current, Ice, and none of it is used to transition the gates. Obviously, both of these statements are false.
In reality, the power required by the gate itself can be quite substantial in high frequency applications. Calculation of this begins by listing the specified total gate charge for the FET device, Qg.
U-137
The gate power utilized in charging and discharging a capacitor at frequency "F" is:
c P(cap) = * V"2 * F
Substituting the gate charge for capacitance multiplied by voltage (O=C*V) in this equation results in:
P(gate) = Qg * V * F
The gate power required verses FET size and switching frequencies is tabulated forsome common applications in Table 3. Table 4. transforms this power into driver input current at a nominal 12 volt bias.
FET SIZE
GATE POWER (mW) VS. SWITCHING FREQUENCY AND FET SIZE
SWITCHING FREQUENCY (kHz) 50 100 150 200 250 500 750 1MEG
SIZE 1
10 18 28
36 46 90 136 180
SIZE2
16 30 46
60 76 153 226 300
SIZE3
28 54 82
108 136 275 406 504
SIZE4
48 96 144 192 240 480 720 960
SIZE5
100 200 300 400 550 1W 1.5W 2W
SIZE6
144 288 432 576 720 1.4W 2W >2W
Table3.
DC SUPPLY CURRENT (mA) VS. SWITCHING FREQUENCY AND FET SIZE
SWITCHING FREQUENCY (kHz)
50 100 150 200 250 500 750 1MEG
SIZE1
1
1
2
4
5
6 10
12
SIZE2
1
2
4
5
6 10 16
20
SIZE3
2
4
6
8 10 16 26
36
SIZE4
4
8
10
12 16 32 48
64
SIZE5
8 14 20
26 32 66 100 130
SIZE6
10 20 28
38 48 96 144 190
Table4.
9-413
APPLICATION NOTE
The driver output stage can be modelled as a resistance to the respective auxiliary supply rail driving an ideal FET capacitor. All of the power used to charge and discharge the MOSFET gate capacitor is completely transferred into heat by the driver. This gate power loss adds to the driver's own power loss - resulting in a net driver power dissipation equal to it's inputvoltage, Vee, multiplied by the sum of the gate and driver currents, lg + Ice. This can be calculated or determined empirically by measuring the driver DC input voltage and current.
THERMAL CONSIDERATIONS
Proper IC package selection and/or device heatsinking is the only method available to insure a safe operating junction temperature, tj. All IC's are specified and graded forvarious junctiontemperatu re ranges, and priced accordingly. As a precaution, it should be noted that using a device outside its tested temperature range can result in poor performance, parameters which run outside their specifications, and quite possibly - no operation at all.
JUNCTION TEMPERATURE
The junction temperature of the driver IC is obtained by first calculating the device's thermal rise above the ambient temperature. This is obtained by multiplying the average input power (Vin*lin) by the device's thermal impedance to air, theta JA (Oja).
U-137
This term is then added to the ambient temperature to yield the resulting junction temperature, Tj.
If the driver is thermally attached to a heatsink or "cold plate", then the thermal impedance from the device junction to it's package case, theta JC (Ojc), is used to determine the thermal rise. Likewise, this thermal rise is added to the heatsink temperature to determine the junction temperature. In either case, the maximum junction temperature (tj(max)) should be determined and checked against the device's absolute maximum specification.
Average supply currents for each of the three drivers of interest varies primarily with the switching frequency. Rather than listing each driver independantly, an rough approximation of 25 milliamps will be used as the driver current, regardless of the specific device utilized and switching frequency. In addition, a typical supply voltage of 12 volts results in a power dissipation by the driver itself of 300 milliwatts.
The calculated gate power of Table 5. has been added to the estimated 300mW of device power to formulate Table 6. - the driver total power dissipation. This is of particular interest in selecting a driver package(8 pin, T0-220, etc) and heatsinkdetermination for a specific maximum junction temperature, or rise. Typical junction temperature rises vs. frequency and FET size for a IC package, and recommendations are shown in table 7.
AVERAGE POWER DISSIPATION (mW) VS. FREQUENCY AND FET SIZE
FET SIZE
SIZE 1 SIZE2 SIZE3 SIZE4 SIZES SIZE6
SWITCHING FREQUENCY (kHz)
50 100 150 200 250 500 750 1MEG
310 318 328 336 346 390 436 480
316 330 346 360 376 452 526
600
328 354 382 408 436 570 706
840
348 396 444 492 540 780 1.0W 1.3W
400 500 600 700 800 900 1.7W 2.4W
444 588 732 876 1.0W 1.7W 2.5W 3.1W
Table 5.
9-414
APPLICATION NOTE
PACKAGE RECOMMENDATIONS SWITCHING FREQUENCY (kHz)
U-137
50 100 150
For P(diss) =or< 500mW A: 8 pin DI L, <40 C rise
B: 8 pin DIL, <45 Crise
C: 8 pin DIL, <50 Crise
SIZE 1 SIZE2
A A B
A
B
B
For P(diss) =or> 500mW (using heatsink) D: 8 pin DIL, <40 C rise E: 8 pin OIL, <50 C rise
SIZE3 SIZE4 SIZES
B B c
B c D c D D
For P (diss) > 500mW F: T0-220 recommended
SIZE 6
D
D
E
HIGH POWER APPLICATIONS
Table 6.
200 250 500 750 1MEG
B B c D
D
Bc DD
D
D
D
D
E
F
D
D
F
F
F
E
F
F
F
F
F
F
F
F
F
Most high power applications require the use of "monster'' MOSFETs or several large FETs in parallel for each switch. Generally, these are low to medium frequency applications (less than 200kHz) where obtaining a low Rds(on) is of primary concern to minimize the DC switch loss. It is not uncommon to find two, three and even four large devices used in parallel, although some of these combinations are unlikely from a cost versus performance standpoint.
Table seven displays the individual FET device characteristics and several popular parallel arrangements. Listed in descending order is Rds (on) at room temperature and the total gate charge required. This will ultimately be used to determine the gate drive current in Table 8., total power dissipation in Table 9., and driver IC recommendation in Table 1Ofor various applications.
MOSFET ARRANGEMENT
PARALLELED MOSFET CHARACTERISTICS - TABLE 7.
Rds (on)
Qg (nC)
MOSFET
Rds (on)
effective
total
ARRANGEMENT
effective
Qg(nC) total
1XSIZE4
0.85
63
1XSIZE5 1XSIZE6
0.40
130
0.27
190
2XSIZE4(1)
0.425
126
3 X SIZE 4 (1)
0.283
189
4 X SIZE 4 (1)
0.213
252
1. Consider another selection 2. Consider a "Monster" FET
2X SIZE 5 2 X SIZE 6 3 X SIZE 5 (1) 4X SIZE 5 (1) 3 X SIZE 6 (2) 4 X SIZE 6 (2)
0.200 0.135 0.133 0.100 0.090 0.068
AVERAGE SUPPLV CURRENT (mA) VS. FREQUENCY AND FET SELECTION
SWITCHING FREQUENCY (kHz)
FET ARRANGEMENT
Rds
mohm
25
50
75
100
150
2 X SIZE 5
200
31
39
45
51
65
2 X SIZE 6
135
35
45
53
63
83
3XSIZE 6
90
39
53
69
73
91
4 X SIZE 6
68
*Includes 25mA of driver supply current
45
63
Table 8
9-415
82
101
139
260 380 390 520 570 760
200 77 101 139 177
APPLICATION NOTE
POWER DISSIPATION (mW) VS. FREQUENCY AND APPLICATION
SWITCHING FREQUENCY (kHz)
FET ARRANGEMENT
Ads
mohm
25
50
75
100
150
2XSIZE5
200
372
468
540
612
780
2XSIZE6
135
420
540
636
756
1.0W
3XSIZE6
90
468
636
828
876
1.1W
4XSIZE6
68
540
756
984
1.2W 1.7W
· Includes 300mW of driver dissipation
Table9.
U-137
200 924 1.2W 1.7W 2.1W
Selection Guide for< 50 Crise
A: 8 pin OIL or 20 pin PLCC
B: Spin OIL with heatsink. orT0-220.
C: T0-220 with heatsink
DRIVER IC AND PACKAGE SELECTION GUIDE
FET ARRANGEMENT 2XSIZE5 2XSIZE6 3XSIZE6 4XSIZE6
SWITCHING FREQUENCY (kHz)
Ads
mohm
25
50 75 100 150 200
200
A
B c c c c
135 B c c c c c
90
B ccccc
68 c c c c c c
Table 10.
UC1710 DRIVER PERFORMANCE
Although capacitive in nature, the FET "Miller'' effects and demands on the driver differ significantly than a true capacitor load as previously described.
Table 11. shows the typical response of the UC171 O "Miller Killer" driving a single APT5025BN (size 6) device and paralleled MOSFET combinations for reference.
UC1710 RISE, FALL AND DELAY TIMES VS. LOADS
TEST CONDITIONS
Tp Tt Tp Tt Tp Tt +Tt +Tp LH LH HL HL LH HL
NO LOAD VOS 28 12 36 12 40 50
ONE
0 28 26 38 30 54 68
APT5025 350 28 35 40 30 63 70
TWO
0 28 38 40 36 66 76
APT5025 350 28 48 42 38 76 80
THREE
0 28 48 42 48 76 90
APT5025 350 28 60 44 58 88 92 Table 11.
9-416
APPLICATION NOTE
PERFORMANCE COMPARISONS
"HOMEBREW" TOTEM-POLES VS INTEGRATED CIRCUIT DRIVERS
The prior lack of "off-the-shelf" high current or high speed drivers had prompted many to design their own gate drive circuits. Traditionally, an NPN-PNP emitter follower arrangement had been used in lower frequency applications as shown in Figure 7.
U-137
input drive waveform is above Vgs(th) of the N device and below that of the P device. One technique to minimize the cross conduction peak current is to add some resistance between the FETs. While this does minimize the "shoot-through" current, it also limits the peak current available to the load. This somewhat defeats the purpose of using the MOSFETs in the first place to deliver high currents. The resistor serves an additional purpose of damping the gate drive oscillations du ring the transitions. In a practical application, two resistors can be used in the place of one with the center-tap connecting to the FET gate.or load as shown in figure 9.
INPUT
TO LOAD
12V
INA
Figure 7
3 +12V ~
1 8 - - INPUT
PMOS TO LOAD
GND~NMOS
Figure 8
For higher speed applications, a P and N channel FET pair can be used as shown in figure 8. The circuit is configured with the P channel MOS as the upper side switch to simplify the auxiliary bias. Otherwise, a gate drive potential of ten volts above the auxiliary bias would required.
INB ~~~
GND
Figure 9
The performance of the circuit in figure 9 was evaluated and compared to that of the UC1710 driver into a 30 nanoFarad load. A size three P type FET and a size two N channel device were connected in series with two one-half ohm resistors to limit the shoot-through current. These FETs were driven from -the UC1711 dual driver which can deliver 3 Amp peak gate drive currents for rapid transitions. The results of this test are shown in figure 10.
Driver Performance into 30nF load
Unfortunately, this configuration has a few drawbacks. First, it leads to an inverting logic flow from the driver input to its output, complicating matters especially during power-up and power-down sequences. Without a clever undervoltage lockout circuit the main power switch will tend to be ON as the auxiliary supply voltage is raised or lowered while the PWM is OFF.
Cross conduction of both FETs is unavoidable with this configuration due to the difference between the gate threshold voltages of each device. Both P and N channel devices are cross conducting while their
Lines: solid=UC3710, dashed=discrete Figure 10. - VERT: 5V/DIV: HORIZ: 50 nS/DIV
9-417
APPLICATION NOTE
The test results indicate very similar performance into this load from either technique. Obviously, the "homebrew" approach utilizes a total of three devices in comparison to a single UC1710 driver to obtain essentially the same high speed performance. Additionally, the cost of the P channel FET alone may exceed the price of the UC1710 device, not to
U-137
mention the difference in PC board real estate. As a final note, the discrete FET approach required over 10 milliamps more supply current than the single UC1710 driver or a increase in supply current of twenty percent. Results of this test shown in figures 11 and 12.
RISE AND FALL TRANSITION PERFORMANCE INTO 30 nF
RISE TIMES (Fig 11.)
FALL TIMES (Fig 12.)
PHOTO SCALES (BOTH): VERT=2V/DIV, HORIZ=10 nS/DIV LINES: SOLID= UC3710; DASHED= DISCRETE CIRCUIT OF FIGURE 9.
POWER DEVICES
IGBTs and MCTs: While existing generations of power MOSFETs continue to be enchanced for lower RDS(on) and faster recovery internal diodes, alternative new devices have also been introduced. Among the most popular, and viable for high voltage high power applications are IGBTs (Insulated Gate Bipolar transistors) and MCTs (MOS Controlled Thyristors). Although frequently drawn as an NPN structure, the IGBT actually resembles a PNP bipolar transistor with an internal MOS device to control the base drive. Indicative by its description, the MCT is essentially an SCR structure also utilitzing a MOS drive stage. Both devices offer significant cost advantages over MOSFETs for a given power capability.
MOSFET, IGBT and MCT Gate Drives: There are numerous reasons for driving the MOSFET gate
to a negative potential during the device's off state. Degradation of the gate turn-on threshold over time and especially following high levels of irradiation are amongst the most common. However, with IGBTs, the important concern is the ability to keep the device off following turnoff with a high drain current flowing. On larger IGBT's with ratings up to 300 Amps, inductive effects caused by the device's package alone can "kick" the effective gate-to-emitter voltage positive by several Volts at the die - even with the gate shorted to the emitter at the package terminals. Actually, this is the result of the high current flowing in the emitter lead (package) inductance which can less than 1nH. The corresponding voltage drop changes polarity at turn off, thus pulling the emitter below the gate, or ground. If high enough, a fast turn off will be followed by a parasitic turn-on of the
9-418
APPLICATION NOTE
switch, and potential destruction of the semiconductor. Applying the correct amplitude of negative gate voltage can insure proper operation under these high current turn-off conditions. Also, the negative bias protects against tum-on from high dv/dt related changes that could couple into the gate through the "Miller" capacitance.
IGBT
MCT
COLLECTOR
ANODE
MTE~ MTE~
EMITIER
CATHODE
Figure 13 - IGBT and MCT Diagrams
Unlike power MOSFET switches, IGBT transconductance continues to increase with gate voltage. While most MOSFET devices peak with about 10 to 12 Volts at the gate, IGBT performance steadily improves up to the suggested 16 Volt maximum gate. voltage. Typically, most IGBT manufacturers recommend a negative drive voltage between -5 and -15V. Generally, it is most convenient to derive a negative voltage equal in amplitude to the positive supply rail, and ±15V is common.
U-137
capability. Recently introduced parts boast maximum ratings to one megawatt, ideal for large industrial motor drives and high power distribution-even at the substation level. These devices are essentially MOS controlled SCRs and are intended for low frequency switchmode conversion. They will most likely replace high power discrete transistors, Darlingtons and SCRs because of their higher efficiency and lower cost.
Gate Charge and Effective Capacitance with Negative Bias: While several MOSFET and IGBT manufacturers recommend negative gate voltages in the device's off state, few publish any curves or information about gate charge characteristics when the gate is below zero Volts. This complicates the gate drive circuit design as each IGBT, MOSFET or MCT switch must be evaluated by the user over the ranges of operation conditions. A test fixture as shown in Figure 14 can be used to provide empirical generalizations for devices of interest. A switched constant current source/sink has been configured using a .simple dual op-amp to drive a "constant" 1mA at the device under test (DUT). Gate voltage versus time can be monitored which provides the exact gate charge requirements for a given device. Any application specific requirements can also be accommodated by modifying the test circuit with external circuitry.
The gate charge required by an IGBT (for a given voltage and current rating) is noticeably less than that of a MOSFET. Part of this is due to the better utilization of silicon which allows the IGBT die to be considerably smaller than its FET counterpart. Additionally, the IGBT (being a bipolar transistor) does not suffer from the severe "Miller" effects of the MOS devices, easing the drive requirements in a given application. However, because of their advantages, most available IGBTs have fairly high gate charge demands - simply because of their greater power handling capability.
In contrast, MCTs (MOS Controlled Thyristors) exhibit the highest silicon utilization level among power switching devices. While relatively new to the market, these devices are quickly gaining acceptance in very high power (above several kilowatts) applications because of their high voltage (1000V) and high current (to 1OOOA)
Negative Gate Charge - Empirical Data: Several MOSFET, IGBT and MCT gate charge measurements were taken to establish the general characteristics with negative gate charge and effective capacitance during this third quadrant operation was calculated and compared to of the first quadrant specifications from the manufacturers data sheets. Figure 15 demonstrates the general relationships of gate charges for comparison.
Both the IGBT and MCT have similar negative bias gate charge requirements as with an applied positive bias. The MOSFET, however, exhibits a slightly reduced gate charge in its negative bias region, somewhere between 70 and 75 percent of its positive bias charge. The MOSFET's more significant "Miller'' effect in the first quadrant is responsible for this since the higher effective capacitance during the plateau region does not occur with negative bias.
9-419
APPLICATION NOTE
U-137
.----------~------a--J'v".;"----------ToouT
1K
,-- --- --- --- ~ -- --- ---- -- --- --- ~ --- -- .
1K
1K
'
NE5532
:
VCC 8' 1 - - - - - - - 1 - - - - - - 1 - - - +15V
5NF
+IN/-5PVUT':(::;i__
-=-
_lr--$. -15V ~
vEE
+
5
--------------------·------------j
10.1
0.11
51K 51K
Figure 14 - Gate Charge Test Circuit
VERT5V/DIV
HORIZ 50uS/DIV
Figure 15 - Gate Charge Comparison Low to
High Transition
+15 +10
Vgso11-+++++++1'f+-!+1+1+1~~+1Q.1+1+++M-i'1+1+++M-i'1+1++++++.j
(V) -5
-10
Total Gate Power - Negative Drive Voltage Applications: All of the previously presented gate power equations still apply, however they must be modified to include the additional charge requirements of the negative supply voltage. For the sake of simplicity, a multiplication factor can be used for recalculation of the exact figures. When identical amplitudes of positive and negative supply voltages are used, for example ±15V, then the gate power utilized can be simply multiplied by a factor of two. This completes the process for the IGBTs and MCTs. The total MOSFET gate charge, on the other hand, should only be multiplied by a factor of 1.7 to 1.75 to accommodate the reduced negative bias demands. Additionally, if a negative supply voltage different than the positive rail voltage is used, for example +15 and -5, then the scaling factor must be adjusted accordingly. In this case, the new total gate power would be 1+ (-5/-15) or 1.33 times the initial 0-15V gate power for IGBTs and MCTs. The negative drive voltage scaling factor (-5/15) would be multiplied by the 70 to 75% index if a MOSFET were used instead of an IGBT or MCT. This would result in a 1.23 to 1.25 times net increase over the initial (0-15V) gate power demand.
-15
VERT5V/DIV
HORIZ 50uS/DIV
Figure 16 - Gate Drive Comparison High to
Low Transition
9-420
APPLICATION NOTE
SUMMARY
The need for higher speed and higher current FET driver ICs has become increasingly apparent as power conversion switching frequencies are pushed towards and beyond one megaHertz. Likewise, the quest for higher overall efficiencies has resulted in creation of large, even "monster'' size MOSFET geometries. These industry trends have stimulated the development of innovative MOSFET driver ICs - ones which would significantly outperform any of their predecessors, including discrete versions.
A new generation of high speed and high current MOSFET drivers has been presented. Each optimized for a unique blend of these attributes, the UC1708, UC1710 and the UC1711 devices suc-
U-137
cessfully conquer the challenges of obtaining rapid transitions in MOSFET gate drive circuits.
REFERENCES UNITRODE Application Note U-118, " New Driver IC's Optimize High Speed Power MOSFET Switching Characteristics" , UNITRODE LINEAR IC DATABOOK, IC600
INTERNATIONAL RECTIFIER Application Notes AN-937, AN-947 and Datasheets, LR. HEXFET Power MOSFET Designers Manual HDB-4
ADVANCED POWER TECHNOLOGY Databook 1989
HIGH CURRENT FET DRIVER CIRCUITS
TYPE
DESCRIPTION
UC1705/3705
High Speed Power Driver (Single ended)
UC1706/3706
Dual High Current MOSFET Compatible Output Driver
UC1707/3707 UC1708/3708
Dual Uncommitted High Current MOSFET Compatible Output Driver
Dual Non-Inverting Power Driver
UC1709/3709 UC1710/3710 UC1711/3711
Dual High Speed FET Driver
High Current/Speed FET Driver
Dual Ultra High Speed FET Driver
UC3724 UC3725
(PAIR)
Isolated High Side Drive for N-Channel Power MOSFET Gates
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. · MERRIMACK, NH 03054 TEL. 603-424-2410 · FAX 603-424-3460
KEY FEATURES
· 1.5A TotemPole Output · High Speed MOSFET Compatible · Low Quiescent Current · Low Cost Package
· Dual, 1.5A Totem Pole Outputs · Parallel or Push-Pull Conversion
(1706 Series) · Internal Overlap Protection · Analog, Latched Shutdown · High-Speed, Power MOSFET Compatible · Thermal Shutdown Protection · 5 to 40V Operation · Low Quiescent Current
· 3.0 Peak Current Totem Pole Output · 5 to 35V Operation · 25n Sec Rise and Fall Times · 25n Sec Propagation Delays · Thermal Shutdown and Under-Voltage
Protection · High-Speed, Power MOSFET Compatible · Efficient High Frequency Operation · Low-Cross-Conduction Current Spike · Enable and Shutdown Functions · Wide Input Voltage Range · ESD Protection to 2kV
· 1.5A Source/Sink Drive · Pin Compatible with 0026 · 40ns Rise and Fall into 1OOOpF · Low Quiescent Current
· 10A Peak Current Capability · 40ns Rise and Fall Times · 40ns Delay Times {1 NI) · Low Saturation Voltage
· 25nS Rise and Fall into 1OOOpF · 15nS Propagation Delay · 1.5Amp Source or Sink Output Drive · Operation with 5V to 35V Supply · High-Speed Schottky NPN Process · 8-PIN Mini-DIP Package · Radiation Hard
· Fully Isolated Drive for High Voltage · 0% to 100% Duty Cycle · 600kHz Carrier Capability · Local Current Limiting Feature
9-421
PACKAGE
8 Pin DIL 5Pin T0-220 16 Pin DIL 'Batwing'
8-Pin DIL 16-Pin DIL
8Pin DIL
8 Pin DIL 5Pin T0-220 8-Pin DIL
8 Pin DIL (Pair)
n nINTEGRATED
~CIRCUITS
-uNITRODE
APPLICATION NOTE
Zero Voltage Switching Resonant Power Conversion
U-138
Bill Andreycak
Abstract
The technique of zero voltage switching in modern power conversion is explored. Several ZVS topologies and applications, limitations of the ZVS technique, and a generalized design procedure are featured. Two design examples are presented: a 50 Watt DC/DC converter, and an off-line 300 Watt multiple output power supply. This topic concludes with a performance comparison of ZVS converters to their square wave counterparts, and a summary of typical applications.
Introduction
Advances in resonant and quasi-resonant power conversion technology propose alternative solutions to a conflicting set of square wave conversion design goals; obtaining high efficiency operation at a high switching frequency from a high voltage source. Currently, the conventional approaches are by far, still in the production mainstream. However, an increasing challenge can be witnessed by the emerging resonant technologies, primarily due to their lossless switching merits. The intent of this presentation is to unravel the details of zero voltage switching via a comprehensive analysis of the timing intervals and relevant voltage and current waveforms.
The concept of quasi-resonant, "lossless" switching is not new, most noticeably patented by one individual [1) and publicized by another at various power conferences [2,3). Numerous efforts focusing on zero current switching ensued, first perceived as the likely candidate for tomorrow's generation of high frequency power converters [4,5,6,7,8). In theory, the onoff transitions occur at a time in the resonant cycle where the switch current is zero, facilitat-
ing zero current, hence zero power switching. And while true, two obvious concerns can impede the quest for high efficiency operation with high voltage inputs.
By nature of the resonant tank and zero current switching limitation, the peak switch current is significantly higher than its square wave counterpart. In fact, the peak of the full load switch current is a minimum of twice that of its square wave kin. In its off state, the switch returns to a blocking a high voltage every cycle. When activated by the next drive pulse, the MOSFET output capacitance (Coss) is discharged by the FET, contributing a significant power loss at high frequencies and high voltages. Instead, both of these losses are avoided by implementing a zero voltage switching technique [9,10].
Zero Voltage Switching Overview
Zero voltage switching can best be defined as conventional square wave power conversion during the switch's on-time with "resonant" switching transitions. For the most part, it can be considered as square wave power utilizing a constant off-time control which varies the conversion frequency, or on-time to maintain regulation of the output voltage. For a given unit of time, this method is similar to fixed frequency conversion which uses an adjustable duty cycle, as shown in Fig. 1.
Regulation of the output voltage is accomplished by adjusting the effective duty cycle, performed by varying the conversion frequency. This changes the effective on-time in a ZVS design. The foundation of this conversion is simply the volt-second product equating of the input and output. It is virtually identical to that of square wave power conversion, and vastly
9-422
APPLICATION NOTE
U-138
j v
SQUARE WAVE 0
I TON
Topp
TON
k- _J l':EX·D
FR:S:O
j1v
zvs
TON
r=- TOPP
0
Le- _J FCONV (VAR)
FcoNv - LOW
I TOH
I TOPP
TOH
k- _J l':EXSD FRBO
I I [ ~Torr To· Torr
Le- _J _J._ PcoNV
l'CoNV
FcoNv - H :r
Fig. 1 - Zero Voltage Switching vs. Conventional Square Wave
unlike the energy transfer system of its electrical dual, the zero current switched converter.
During the ZVS switch off-time, the L-C tank circuit resonates. This traverses the voltage across the switch from zero to its peak, and back down again to zero. At this point the switch can be reactivated, and lossless zero voltage switching facilitated. Since the output capacitance of the MOSFET switch (Coss) has been discharged by the resonant tank, it does not contribute to power loss or dissipation in the switch. Therefore, the MOSFET transition losses go to zero - regardless of operating frequency and input voltage. This could represent a significant savings in power, and result in a substantial improvement in efficiency. Obviously, this attribute makes zero voltage switch- · ing a suitable candidate for high frequency, high voltage converter designs. Additionally, the gate drive requirements are somewhat reduced in a ZVS design due to the lack of the gate to drain (Miller) charge, which is deleted when Vos equals zero.
The technique of zero voltage switching is applicable to all switching topologies; the buck regulator and its derivatives (forward, half and full bridge), the flyback, and boost converters, to name a few. This presentation will focus on the continuous output current, buck derived topologies, however a list of references describing the others has been included in the appendix.
+
v
01
Fig. 2 - Resonant Switch Implementation
&e~~~!~~o·- ._Fl_·__._or_r_.l__o_·_ __,.._o_rr_.l.___o·_
Fig. 3 - General Wavefonns ZVS Benefits · Zero power "Lossless" switching transitions · Reduced EMI / RFI at transitions · No power loss due to discharging Coss · No higher peak currents, (ie. ZCS) same as
square wave systems · High efficiency with high voltage inputs at
any frequency · Can incorporate parasitic circuit and compo-
nent L & C
9-423
APPLICATION NOTE
· Reduced gate drive requirements (no "Miller" effects)
· Short circuit tolerant
ZVS Differences:
· Variable frequency operation (in general)
· Higher off-state voltages in single switch, undamped topologies
· Relatively new technology - users must climb the learning curve
· Conversion frequency is inversely proportional to load current
· A more sophisticated control circuit may be required
ZVS Design Equations
A zero voltage switched Buck regulator will be used to develop the design equations for the various voltages, currents and time intervals associated with each of the conversion periods which .occur during one complete switching cycle. The circuit schematic, component references, and relevant polarities are shown in Fig. 4.
Typical design procedure guidelines and "shortcuts" will be employed during the analysis' for the purpose of brevity. At the onset, all components will be treated as though they were ideal which simplifies the generation of the basic equations and relationships. As this section progresses, losses and non-ideal characteristics of the components will be added to the formulas. The timing summary will expound upon the equations for a precise analysis.
Another valid assumption is that the output
Ic1t Vca .--..-e.....:-.· 1-·:.......e.___,
U-138
filter section consisting of output inductor L 0 and capacitor C0 has a time constant several orders of magnitude larger than any power conversion period. The filter inductance is large in comparison to that of the resonant inductor's value LR and the magnetizing current t:JLo as well as the inductor's DC resistance is negligible. In addition, both the input voltage ~N and output voltage V0 are purely DC, and do not vary during a given conversion cycle. Last, the converter is operating in a closed loop configuration which regulates the output voltage V0 .
Initial Conditions: Time interval < t0
Before analyzing the individual time intervals, the initial conditions of the circuit must be defined. The analysis will begin with switch Q1 on, conducting a drain current I 0 equal to the output current 10 , and V0 s = VcR = 0 (ideal). In series with the switch Q1 is the resonant inductor LR and the output inductor L 0 which also conduct the output current I 0 . It has been established that the output inductance L 0 is large in comparison to the resonant inductor LR and all components are ideal. Therefore, the voltage across the output inductor VLo equals the input to output voltage differential; VLo = ~N - V0 · The output filter section catch diode D 0 is not conducting and sees a reverse voltage equal to the input voltage; VDo = ~ , observing the polarity shown in Figure 4.
Table I - INITIAL CONDITIONS
COMP. STATUS
0 1 ON
00
OFF
LR
Lo
CIRCUIT VALUES Vos=VcR=O; lo=ILR=ILO=lo Voo=V1N ; loo=O ILR=lo; VLR=O VLO=V1N-Vo; ILO=O
+
Fig. 4 - Zero Voltage Switched Buck Regulator
Capacitor Charging State: t0 - t1
The conversion period is initiated at time t0 when switch Q1 is turned OFF. Since the
current through resonant inductor LR and
output inductor L 0 cannot change instantaneously, and no drain current flows in Q1 while
9-424
APPLICATION NOTE
Io
Fig. 5 - Simplified Model
to1 = -CR~-N
Io for t0<t <t1
Fig. 6 - Resonant Capacitor Waveforms it is off, the current is diverted around the switch through the resonant capacitor CR. The constant output current will linearly increase the voltage across the resonant capacitor until it reaches the input voltage (VcR = ViN)· Since the current is not changing, neither is the voltage across resonant inductor LR.
At time t0 the switch current 10 "instantly" drops from 10 to zero. Simultaneously, the resonant capacitor current IcR snaps from zero to 10 , while the resonant inductor current !LR and output inductor current lw are constant and also equal to 10 during interval t01 · Voltage across output inductor L 0 and output catch diode D0 linearly decreases during this interval due to the linearly increasing voltage across resonant capacitor CR. At time t1 , VcR equals
J.'JN, and D0 starts to conduct.
U-138
Table II - CAPACITOR CHARGING: to- t 1
COMP. STATUS
01
OFF
CR
Charging
LR Do OFF
Lo
CIRCUIT VALUES
ID=O; VDs(tJ =VcR(tl lcR=O; VcR(t) RISES LINEARLY VcR(tO)=O; VcR(t1)=V1N
ILR(t)=lo; VLR=O
Voo(t0)=V1N; VDO(t1)=0; DECREASES LINEARLY
VLO(t0)=V1wVo; VLO(t1)=-Vo DECREASES LINEARLY; ILO=lo
Resonant State: t1 - t2
The resonant portion of the conversion cycle begins at t1 when the voltage across resonant
capacitor VcR equals the input voltage J.'JN, and
the output catch diode begins conducting. At t1 , current through the resonant components IcR and !LR equals the output current 10 ·
The stimulus for this series resonant L-C circuit is output current 10 flowing through the resonant inductor prior to time t1· The ensuing resonant tank current follows a cosine function beginning at time tb and ending at time t2. At the natural resonant frequency wa, each of the L-C tank components exhibit an impedance equal to the tank impedance, ZR. Therefore,
the peak voltage across CR and switch Q1 are a function of ZR and 10 ·
The instantaneous voltage across CR and Q1 can be evaluated over the resonant time interval using the following relationships:
VCR(t) = VCR(tl)+~sin[w a(t-t1)J:2
wRCR
1
VCR(tl) = 1-jN
VCR(t) = VIN+/0ZRsin[w a(t-t1)J:~
Of greater importance is the ability to solve the equations for the precise off-time of the switch. This off-time will vary with line and load changes and the control circuit must respond in order to facilitate true zero voltage switching. While some allowance does exist for a fixed off time technique, the degree of lati-
9-425
APPLICATION NOTE
tude is insufficient to ·accommodate typical input and output variations. The exact time is obtained by solving the resonant capacitor voltage equations for the condition when zero voltage is attained.
Let VCR(t) = 0 ; IOZR SIN("' R(t-t1)) = -VIN
The equation can be further simplified by extracting the half cycle (180 degrees) of conduction which is a constant for a given resonant freque~cy, and equal to w/"'R.
The resonant component current (ICR = ILR)
is a cosine function between time t1 and t2, described as:
/CR(·) = locos [1-> R(t-t1)]:~
The absolute maximum duration for this interval occurs when Z70 degrees (3w/'lM>R) of resonant operation is required to intersect the zero voltage axis. This corresponds to the limit of resonance as minimum load and maximum line voltage are approached.
Contributions of line and load influences on the resonant time interval t12 can be analyzed individually as shown in F'igs. 7 and 8.
Prior to time t1, the catch diode D0 was not conducting. Its voltage, V"°' was linearly decreasing from VIN at time t0 to zero at t1 while input source VIN was supplying full output current, 10· At time t1, however, this situation changes as the resonant capacitor initiates resonance, diverting the resonant inductor current away from the output filter section. Instantly, the output diode voltage, V"°' changes polarity as it begins to conduct, supplementing the decreasing resonant inductor current with diode current I"°' extracted from stored energy in output inductor L 0 · The diode current waveshape follows a cosine function during this interval, equalling 10 minus la(t).
Also occurring at time t1, the output filter inductor L0 releases the stored energy required
U-138
Vea (t)V8 LINB CHANGES
Vur. HIGH
::; 1. . . Vea ( t)
HIGH
- ------------------
I 1
0I I
tO tlH
t2L t2H
cu.
Fig. 7 - Resonant Capacitor Voltage vs. Line
f HIGH
Io
l LOW
I 0 · HIGH
LOW
0 I
I Vea (t)v·
t 0 t 1 H LOAD t 2 L
tlL
CHANQBS
t 2H
Fig. 8 - Resonant Capacitor Voltage vs. Load to maintain a constant output current I 0 · Its reverse voltage is clamped to the output voltage V0 minus the diode voltage drop V00 by the convention followed by Figure 4.
Table III · RESONANT INTERVAL: t1 · ~
COMP. STATUS CIRCUIT VALUES
01 OFF
Vos et>· VcR(t)
CR Reaonant VcR(t)'"VIN +(loZR·ln(wR(M1)))
lc:R(t) · loe<>l(WR~·t1))
LR
Reaonant VLR(t). [loZR·ln(wR~·t1))
ILR(t) · lcR(t)
Do ON
loo(t) · lo·ILR(t)
Lo Discharge VLO =-~o+Voocfwd1)
9-426
APPLICATION NOTE
Inductor Charging State: t2 - t3
To facilitate zero voltage switching, switch QI is activated once the voltage VDS across QI and resonant capacitor VcR has reached zero, occurring at time t2· During this inductor charging interval fv resonant inductor current /LR is linearly returned from its negative peak of minus 10 to its positive level of plus 10 .
The output catch diode D0 conducts during the t23 interval. It continues to freewheel the full output current 10 , clamping one end of the resonant inductor to ground through D 0 · There
is a constant voltage, VrN -.V00 , across the
resonant inductor. As a result, !LR rises linearly, / 00 decreases linearly. Energy stored in output inductor L 0 continues to be delivered to the load during this time period.
A noteworthy peculiarity during this timespan can be seen in the switch drain current waveform. At time t2, when the switch is turned on, current is actually returning from the
resonant tank to the input source, VrN· This
indicates the requirement for a reverse polarity diode across the switch to accommodate the bidirectional current. An interesting result is that the switch can be turned on at any time during the first half of the t23 interval without affecting normal operation. A separate time interval could be used to identify this region if desired.
~N
LR
LRl::i.IR
~N
where l::i.IR =-10 to +/0 = 210
U-138
Table IV · INDUCTOR CHARGING: t2 · t3
COMP. STATUS CIRCUIT VALUES
01 ON
Ioctl =·lo+ ((ViN +Vool/LR)t
CR
VcR=O
LR
Charging VLR=V1N+Voo
ILR(t) =·lo+ fYLR/LR) (t-t2)
Do ON
looctJ = lo-ILRCtJ
'-o
lw=lo; VLo=·'Yo+Vool
the conversion period, most of the pertinent
waveforms approach DC conditions.
Assuming ideal components, with QI closed,
the input source supplies output current , and
the output filter inductor voltage VLO equals VrN
- V0 · The switch current and resonant inductor
current are both equal to 10 , and their respec-
tive voltage drops are zero (Vvs= VLR=O).
Catch diode voltage V00 equals VrN· and I00 = 0.
In closed loop operation where the output
voltage is in regulation, the control circuit
essentially varies the on-time of the switch
during the t34 interval. Variable frequency operation is actually the result of modulating
the on-time as dictated by line and load condi-
tions. Increasing the time duration, or lowering
the conversion frequency has the same effect as
widening the duty cycle in a traditional square
wave converter. For example, if the output
voltage were to drop in response to an
increased load, the conversion frequency would
decrease in order to raise the effective ON
period. Conversely, at light loads where little
energy is drawn from the output capacitor, the
control circuit would adjust to minimize the tJ4 duration by increasing the conversion frequen-
cy. In summary, the conversion frequency is
inversely proportional to the power delivered to
the load.
Power Transfer State: t3 · t4
Once the resonant inductor current /LR has reached 10 at time tJ, the zero voltage switched converter resembles a conventional square wave power processor. During the remainder of
9-427
APPLICATION NOTE
Table V · POWER TRANSFER: t3 · t4
COMP. STATUS CIRCUIT VALUES
01 ON CR LR
Vos=loRoscoN>; lo=lo VcR=O ILR=lo; VLR=O
0111
··· cou
VCR 0 (20V} I CR
0 (SA}
ID ((11) (SA} 0
VIN= 18 v
V0 = 5V 10 = 5A
JI.I e
(SA}
V LR (20v}
U-138
ON
100 (SA)
VLO ( 1 Ov}
Jl.O (SAAC) 0
Vo
(5v)
Vo 0 (SOmvac)
Fig. 9 -- ZVS Buck Regulator Wavefonns
9-428
APPLICATION NOTE
ZVS Converter Limitations:
In a ZVS converter operating under ideal conditions, the on-time of the switch (t23 +t34) approaches zero, and the converter will operate at maximum frequency and deliver zero output voltage. In a practical design , however, the switch on-time cannot go to zero for several reasons.
First of all, the resonant tank components are selected based on the maximum input
voltage Ji/.v....... and minimum output current
I°""" for the circuit to remain resonant over all
operating conditions of line and load. If the circuit is to remain zero voltage switched, then the resonant tank current cannot be allowed to go to zero. It can, however, reach 10,,,;,,.
There is a finite switch on-time associated with the inductor charging interval t23 where the
resonant inductor current linearly increases
from - 10 to + 10 · As the on-time in the power transfer interval t34 approaches zero, so will the
converter output voltage. Therefore, the minimum on-time and the maximum conversion
frequency can be calculated based upon the
limitation of/°""" and rero output voltage. The limits of the four zero voltage switched
time intervals will be analyzed when 10 goes to 10 minimum. Each solution will be retained in terms of the resonant tank frequency "'· for generalization.
U-138 2
:. l23
"'·
t34min = 0
Both the minimum on-time and maximum off-time have been described in terms of the resonant tank frequency , "'R· Taking this one step further will result in the maximum conversion frequency fcoNVmax, also as a function of the resonant tank frequency.
Minimum On-Time:
2 1 0.318
123. mm
=-=--=--
(J)R 1tfR
f R
Maximum Off-Time:
to1 +t12min = -1+-15-ir
w R
0.909
fa
The maximum conversion frequency corresponds to the minimum conversion period,
TcoN'hnin, which is the sum of the minimum on-
time and maximum off-time:
0.909+0.308 1.227
1.
fa
The maximum conversion frequency, fcoNVmax
= 1/TcoNVinin·equals
1 FcoNVmu = T
CONY{ min)
The ratio of the maximum conversion frequency to that of the resonant tank frequency
can be expressed as a topology coefficient, KT.
For this zero voltage switched Buck regulator
and its derivatives, K.rmu equals:
0.815
9-429
APPLICATION NOTE
U-138
conversion period where t34 equals zero. Topology coefficient KT will be incorporated to
define the ratio of the maximum conversion
frequency (minimum conversion period) to that
of the resonant tank frequency, wR.
w: IN
=
P
0
TCONV
'
Where TCONV =
7.71
WR
to tl
t2
~N = p Omin 7·71 WR
Fig. JO -- Wavefonns at F coNV = KT· fR In a realistic application, the output voltage of the power supply is held in regulation at V0 which stipulates that the on-time in the power processing state, t34 , cannot go to zero as in the example above. The volt-second product requirements of the output must be satisfied during this period, just as in any square wave converter design. Analogous to minimum duty cycle, the minimum on-time for a given design
will be a function of ViN· V0 and the resonant
tank frequency, wR. Although small, a specific amount of energy
is transferred from the input to the output during the capacitor charging interval t01· The voltage into the output filter section linearly decreases from ~N at time t0 to zero at ti> equal to an average value of VIN/2. In addition, a constant current equal to the output current I 0 was being supplied from the input source. The average energy transferred during this interval is defined as:
The equation can be reorganized in terms of CR and wR as:
This minimum energy can be equated to minimum output watts by dividing it by its
This demonstrates that a zero power output
is unobtainable in reality. The same is true for
the ability to obtain zero output voltage.
The equation can be rewritten as:
2 VIN
0.065
2 VIN
Vomin = 2(7 71) V:
·
IN max
V:
IN max
Solving for the highest minimum output
voltage, the worst case for occurs when I 0 equals IOmin and ~N is at its maximum, ~Nmm:·
VOmin = 0.065 VINmax ; ""' 6.5% ~Nmax
Under normal circumstances the circuit will be operating far above this minimum requirement. In most applications, the amount of power transferred during the capacitor charging interval t01 can be neglected as it represents less than seven percent (7%) of the minimum input power. This corresponds to less than one percent of the total input power assuming a 10:1 load range.
'ZVS Effective Duty Cycles:
A valid assumption is that a negligible amount of power is delivered to the load during the capacitor charging interval t01 · Also, no power is transferred during the resonant period from t12· Although the switch is on during period t23, it is only recharging the
9-430
APPLICATION NOTE
resonant and output inductors to maintain the
minimum output current, 10 ..un· In summary, NO output power is derived from ~N during
interval 103· The power required to support V0 at its
current of 10 is obtained from the input source during the power transfer period 134· Therefore, an effective "duty cycle" can be used to describe the power transfer interval 134 to that of the entire switching period, 104, or TcoNV.
ZVS - Effective Duty Cycle Calculations:
"Duty Cycle" = Vo 134
~N
l04
"Duty Cycle" =
101 +l12+t23+l34
And can be analyzed over line and load ranges using previous equations for each interval.
Accommodating Losses in the Design Equations:
Equations for zero voltage switching using ideal components and circuit parameters have been generated, primarily to understand each of the intervals in addition to computer modeling purposes. The next logical progression is to modify the equations to accommodate voltage drops across the components due to series impedance, like Rvs(onJ· and the catch diode forward voltage drop. These two represent the most significant loss contributions in the buck regulator model. Later, the same equations will be adapted for the buck derived topologies which incorporate a transformer in the power stage.
The procedure to modify the equations is straightforward. Wherever ~N appears in the equations while the switch is on it will be replaced by ~N-VDs(onJ , the latter being a function of the load current I 0 . The equations can be further adjusted to accept changes of Rvs(onJ and VF , etc. with the device junction temperatures. Resonant component initial tolerances, and temperature variations likewise
U-138
could optionally be evaluated. A computer program to calculate the numer-
ous time intervals and conversion frequencies as a function of line and load can simplify the design process, if not prove to be indispensable. Listed in the Appendix of this section is a BASIC language program which can be used to initiate the design procedure.
To summarize: When the switch is on, replace ~N with (~N-vDS(on)) = (VIN-lo. RDS(on))· When the free-wheeling diode is on, replace V0
with (V0 +Vp).
CR (~N-/ORDS(on»
Io
~ + _...!:_ arcsin [~N-/ORDS(on)lt2
wR wR
IoZR
i1
CVo+ VF)(lo1+f12+l23)
(~N-/ORDS(on»-(Vo+ VF)
~Nmax - RDS(on/Omin
/Omin
Transformer Coupled Circuit Equations:
The general design equations for the Buck topology also apply for its derivates; namely the forward, half-bridge, full-bridge and push-pull converters. Listed below are the modifications and circuit specifics to apply the previous equations to transformer coupled circuits. General Transformer Coupled Circuits. Maintaining the resonant tank components on the primary side of the transformer isolation boundary is probably the most common and simplest of configurations. The design procedure begins by transforming the output voltage and current to the primary side through the turns ratio, N. The prime (') designator will be used to signify the translated variables as seen by the primary side circuitry.
9-431
APPLICATION NOTE N= Primary Tums Secondary Tums
10'=10 /N; V0 '=V0 ·N; and Z0 '=Z0 ·N2 To satisfy the condition for resonance, IR<I0 '
IR:Sio'=Io/N; ZR :S V,N,,,,... __ V,Nmax N
lo min
Io
The resonant tank component equations now become:
Note: the calculated resonant inductance value does not include any series inductance, typical of the transformer leakage and wiring inductances.
Note: the calculated resonant capacitor value does not include any parallel capacitance, typical of a MOSFET output capacitance, Coss· in shunt. Multi-transistor variations of the buck topology should accommodate all switch capacitances in the analysis.
Timing Equations (including N):
CRV,NN
[ r '01 = Io
" '12
=
-f+t'
-
1 ar
c
s
.V,NN m --
wR wR
IoZR
123 = 2LRIO
V,NN
t34 = NV0 (t01 +t12+t23) J.jN-NVo
TCONV = '01 +t12+t23+t34
U-138
Determining Transformer Turns Ratio (N): The transformer turns ratio is derived from the equations used to define the power transfer interval t34 in addition to the maximum offtime, t03· While this may first seem like an iterative process, it simplifies to the volt-second product relationship described. The general equations are listed below.
The turns ratio N is derived by substituting N· V0 for the output voltage V0 in the power transfer interval t34 equation. Solving for N results in the relationship:
NVo /V,N = l34 /(tot +t12+!23+t34)
N = v/Nmin l34 VOt04
The transformer magnetizing and leakage inductance is part of the resonant inductance. This requires adjustment of the resonant inductor value, or both the resonant tank impedance ZR and frequency wR will be off-target. One
~~1 T e lTO OUTPUT
LPRI
FILTER
· : 9 0' LR
~ CI
----
Fig. 11 -- Transformer Inductance "Shim "
option is to design the transformer inductance to be exactly the required resonant inductance, thus eliminating one component. For precision applications, the transformer inductance should be made slightly smaller than required, and "shimmed" up with a small inductor.
9-432
APPLICATION NOTE
Expanding ZVS to Other Topologies
ZVS Forward Converter · Single Ended: The single ended forward converter can easily be configured for zero voltage switching with the addition of a resonant capacitor across the switch. Like the buck regulator, there is a high voltage excursion in the off state due to resonance, the amplitude of which varies with line and load. The transformer can be designed so that its magnetizing and leakage inductance equals the required resonant inductance. This simplifies transformer reset and eliminates one component. A general circuit diagram is shown in Fig. 12 below. The associated waveforms for when L,.Rr equals LR are shown in Fig. 13.
L SHIM
V gs(Oll ( lOV) 0
'DI (01)
VCR 0 (20V)
IcR 0
(SA)
ID(Ol) (SA) 0
U-138 ON
Fig. 12 -- ZVS Forward Converter
I DO (SA) 0
V LO 0 (lOv)
I LO
(51 lC)O Vo ( Sv)
0
Vo 0 (SOmvac)
Fig. 13 - Forward Converter Wavefonns
9-433
APPLICATION NOTE
ZVS Clamped Configurations -- Hair and Full Bridge Topologies: Zero voltage switching can be extended to multiple switch topologies for higher power levels, specifically the half and full bridge configurations: While the basic operation of each time interval remains similar, there is a difference in the resonant t12 interval.
While single switch converters have high offstate voltage, the bridge circuits clamp the switch peak voltages to the DC input rails, reducing the switch voltage stress. This alters the duration of the off segment of the resonant interval, since the opposite switch(es) must be activated long before the resonant cycle is completed. In fact, the opposite switch(es) should be turned on immediately after their voltage is clamped to the rails, where their drain to source voltage equals zero. If not, the resonant tank will continue to ring and return the switch voltage to its .starting point, the opposite rail. Additionally, this off period varies with line and load changes.
Examples of this are demonstrated in Figs. 14 and 15. To guarantee true zero voltage switching, it is recommended that the necessary sense circuitry be incorporated.
U-138 Fig. 14 - Clamped ZVS Configuration Fig. 15 - Clamped ZVS Wavefonns
9-434
APPLICATION NOTE
ZVS Half Bridge: The same turns ratio, N, relationship applies to the half bridge topology when V,N in the previous equations is considered to be one-half of the bulk rail-torail voltage. V,N is the voltage across the transformer primary when either switch is on.
Refer to the circuit and waveforms of Figs. 14 and 15. CR, the resonant capacitor becomes the parallel combination of the two resonant capacitors, the ones across each switch. Although the resonant inductor value is unaffected, all series leakage and wiring inductance must be taken into account.
The off state voltages of the switches will try to exceed the input bulk voltage during the resonant stages. Automatic clamping to the input bulk rails occurs by the MOSFET body diode, which can be externally shunted with a higher performance variety. Unlike the forward converter which requires a core reset equal to the applied volt second product, the bidirectional switching of the half (and full) bridge topology facilitate automatic core reset during consecutive switching cycles [11,12).
U-138
r··-------,
I
I
I
lcoNTROL icIRCUIT
I
LJ~1"« " II
I I I
Vo~
' I
I
!I ---------!
Fig. 16 -- ZVS Half Bridge Circuit
t0tlt2 t3 t4
t0tlt2 t3
ON
. . . ._ _ _ _ OFFl--~....._...._
._.__.._-!-----~--!i---!---
oOr·ri--................_______._.__...........____.....,__....._____
VIN ····.r··-.r··:: ........ :
! VIN
-2-
i~ i ~
0
VIN
VIS
2
0
Io
N
0
-Io
N
IOUT.
IOUT
0
to tl t2 tl
t'
t0tlt2 t3
tOtl t2 tS t·
Fig. 17 -- ZVS Half Bridge Wavefonns
9-435
APPLICATION NOTE
ZVS Full Bridge: The equations represented for the forward topology apply equally well for one conversion cycle of the full bridge topology, including the transformer turns ratio. Since the resonant capacitors located at each switch are "in-circuit" at all times, the values should be adjusted accordingly. As with the half bridge converter, the resonant capacitors' voltage will exceed the bulk rails, and clamping via the FET body diodes or external diodes to the rails is common [13].
U-138
Tl
·
Li
=
Vo
C:l
Co
n:l
Fig. 18 - ZVS Full Bridge Circuit
t0tlt2 t3 t4
to tl t2 tl
ON
OFFl--~--!!---!-~~!'"-!--!!---t-~~!'"-1--!!---!-~
ON
orr._~~r--+~~!-!--!1---!-~~!'-!--!!---t-~
VIN
0
VIN
0 Io N
0
·lo
N
IOUT.
IOUT
0
. : : .
to ti t2 tl
..
t4
t0tlt2 t3
t· tOtl t2 t3
Fig. 19 -- ZVS Full Bridge Wavefomis
9-436
APPLICATION NOTE
ZVS Design Procedure
Buck Derived Topologies - Continuous Output Current:
1. List all input/output specs and ranges.
VrN min & max ; V0 ; 10 min & max
2. Estimate the maximum switch voltages. For undamped applications (buck and forward):
Vos.- = JllN_.(1+(1(,,,,,,,,/l°""n)
Note: Increase 10 ,,,;n if VDS.- is too high if possible).
For clamped applications (bridges):
VDS.- =JllNM<u
3. Select a resonant tank frequency, wR (HINT: wR=21rfR).
4. Calculate the resonant tank impedance and component values.
5. Calculate each of the interval durations (t01 thru t34) and their ranges as a function of all line and load combinations. (See Appendix _ for a sample computer program written in BASIC)
Additionally, summarize the results to establish the range of conversion frequencies, peak voltages and currents, etc.
6. Analyze the results. Determine if the frequency range is suitable for the application. If not, a recommendation is to limit the load range by raising lo,,,;n and start the design procedure again. Verify also that the design is feasible with existing technology and components.
7. Finalize the circuit specifics and details.
D Derive the transformer turns ratio. (nonbuck applications)
D Design the output filter section based upon the lowest conversion frequency and output ripple current/0 (ac).
D Select applicable components; diode, MOSFET etc.
U-138 8. Breadboard the circuit carefully using RF
techniques wherever possible. Remember -parasitic inductances and capacitances prefer to resonate upon stimulation, and quite often, unfavorably. 9. Debug and modify the circuit as required to accommodate component parasitics, layout concerns or packaging considerations.
Avoiding Parasitics
Ringing of the catch diode junction capacitance with circuit inductance (and package leads) will significantly degrade the circuit performance. Probably the most common solution to this everyday occurrance in square wave converters is to shunt the diode with an R-C snubber. Although somewhat dissipative, a compromise can be established between snubber losses and parasitic overshoot caused by the ringing. Unsnubbed examples of various applicable diodes are shown in Fig. 20 below.
VERTICAL: 20V/OIV, HORIZONTAL: 2uSEC/OIV
o UH
Fig. 20 - Catch Diode Ringing
9-437
APPLICATION NOTE
Multiresonant ZVS Conversion
Another technique to avoid the parasitic resonance involving the catch diode capacitance is to shunt it with a capacitor much larger than the junction capacitance. Labelled C0 , this element introduces favorable switching characteristics for both the switch and catch diode. The general circuit diagram and associated waveforms are showm below, but will not be explored further in this presentation [14,15].
U-138
Yga (01) iLI-0::·-·:.,..lL;;0.;'.;I.'J..OR----'-O-P-P-I '·'-0-11--
v /
!\
+ Ro Vo
Fig. 21 - Multiresonant ZVS Circuit
Current Mode Controlled ZVS Conversion
Variable frequency power converters can also benefit from the use of current mode control. Two loops are used to determine the precise ON time of the power switch -- an "outer" voltage feedback loop, and an "inner" current sensing loop. The advantage to this approach is making the power stage operate as a voltage controlled current source. This eliminates the two pole output inductor characteristics in addition to providing enhanced dynamic transient response.
Principles of operation. Two control ICs are utilized in this design example. The UC3843A PWM performs the current mode control by providing an output pulse width determined by the two control loop inputs. This pulse width, or repetition rate is used to set the conversion period of the UC3864 ZVS resonant controll~r. Rather than utilize its voltage controlled oscillator to generate the conversion period, it is
Fig. 22 -- Multiresonant Waveforms
determined by the UC3843A output pulse width.
Zero voltage switching is performed by the UC3864 one-shot timer and zero crossing detection circuitry. When the resonant capacitor voltage crosses zero, the UC3864 output goes high. This turns ON the power switch and recycles the UC3843A to initiate the next current mode controlled period. The UC3864 fault circuitry functions, but its error amplifier and VCO are not used.
9-438
APPLICATION NOTE
ZVS Forward Converter ·· Design Example
1. List circuit specifications:
JiiN = 18to26V
V0 = S.O V ; 10 = 2.S to 10 A
2. Estimate the maximum voltage across the switch:
Vosn.r= 1iiNn.r(1 +(/on.r/Iorn1n))
=26· (1+(10/2.5)) = 26·5 = 130 v
3. Select a resonant tank frequency, wa·
A resonant tank period frequency of 500KHz will be used. It was selected as a compromise between high frequency operation and low parasitic effects of the components and layout.
IR= SOOKHz; "'R,=3.14·1a6 radians/sec
4. Calculate the resonant tank impedance and component values.
Resonant tank impedance, ZR > 1iiNrnaxfI0rn;,.
To accommodate the voltage drop across the MOSFET, calculate VDS(onJmin· which equals Ros(on/Ornin = 0.8 · 2.5 = 2V
ZR = (V,Nrnax -VDSmin)/ IOrnill ZR = (26-2)/2.5 = 10 0
CR = 1/(ZaWR.) = 1/(10. 3.14 · 1<>6} = 32nF
LR = ZRl"'R = 10/3.34 · la6 = 3.18µH
S. Calculate each of the interval durations (t"' thru tJf) and ranges as they vary with line and load changes. The rero voltage switched buck converter
"gain" in kiloHertz per volt of ViN and kHz
per amp of I 0 can be evaluatated over the specified ranges. A summary of these follows:
U-138 Table VI · Interval Durations vs. Line & Load
V1N·18 V1N·18 V1N·26 V1N·26 lo·UI 10 =10 10 ·2.5 10 ·10
t10 t12
t23 t34 TCONV fcoNv
0.217 0.055 1.29 1.06 0.93 3.72 1.39 6.88 3.83 11.151 261kHz 87kHz
0.314 o.078 1.49 1.08 0.84 2.158
o.78 1.78
3.23 5.152 310kHz 181kHz
Translator Switch Durations:
foN
2.32 10.4 1.42 4.36
foFF
1.151 1.11 1.80 1.16
11-
. , - - 10-
..=. · -
. .- 11<1 7 -
.- ~ 5 -
3 2 1 -
-·nr1:c.-.-:..-v---------------------=---------------·
0
~~.~~,~~-,~~-,~~.~~
18
20
22
2·
26
V:i:N(VOLTS)
Fig. 23 ~ Switch Times vs. Line & Load
dfcmw/dV,N vs /0
I0 = 2.SA SA 7.5A lOA avg df/dV = 6.1 11.2 11.9 11.7 10.2
Highest "gain" (11.9 kHz/V) occurs near full load.
dfcoNV/dlo vs V,N
ViN = 18 20 22 24 26 avg df/dV = 23.3 22.1 20.5 18.8 17.3 20.4 Highest "gain" (23.3 kHz/A) occurs at ViNmin·
It may be necessary to use the highest gain values to design the control loop compensation for stability over all operating conditions. While this may not optimire the loop transient response for all operating loads, it will guarantee stability over the extremes of line and load.
9-439
APPLICATION NOTE
31501t-
~ SOOlt -
=..,11>'4 2501t 2001t -
gI;:> 11501t -
~ l.OOlt -
79;1:-
--== ·--------- . . l··t~.·.~.------ · a· BA
~ .·:~~·.:.. ? ....
~
I
I
I
I
I
1.e
ao
22
24
2·
V;i:N(VOLTS)
Fig. 24 - Conversion Freq. vs. Line & Load
6. Analyze the results.
The resonant component values, range of conversion frequencies, peak voltage and current ratings seem well within the practical limits of existing components and technology.
7. Finalize the circuit specifics and details based on the information obtained above.
U-138
A. Output Filter Section: Select L0 and C0 for operation at the lowest conversion frequency and designed ripple current.
B. Heatsink Requirements: An estimate of the worst case power dissipation of the power switch and output catch diode can be made over line and load ranges.
C. Control Circuit: The UC3861-64 series of controllers will be examined and programmed per the design requirements.
Programming the Control Circuit
One-shot: Accommodating OtT-time Variations. The switch off-time varies with line and load by "" ± 35% in this design example using ideal components. Accounting for initial tolerances and temperature effects results in an much wider excursion. For all practical purposes, a true fixed off-time technique will not work.
Incorporated into the UC3861 family of ZVS controllers is the ability to modulate this off-
Fault
lott·Rel
rault LOIJiC
and
Precision l.efez:ence
Bias and
5V
SV Gen
NI
zn
B/A Out
Range bla Cvco
YCO
.,...,.
Logic
leso
Yoo
out 1.
Out B Pw:i: Gnd
ac Fig. 25 - The UC3861-64 ZVS Contollers - Block Diagram
9-440
APPLICATION NOTE
VCR
Ill
ur
c. Fig. 26 - Volts&: Off-time vs. Line & Load
time. Initially, the one-shot is programmed for the maximum off-time, and modulated via the ZERO detection circuitry. The switch drainsource voltage is sensed and scaled to initiate turn-on when the precision O.SV threshold is crossed. ThiS offset was selected to accommodate propogation delays between the instant the threshold is sensed and the instant that the switch is actually turned on. Although brief, these delays can become significant in high frequency applications, and if left unaccounted, can cause NONZERO switching transitions.
Referring to Fig. 26, in this design, the offtime varies between 1.11 and 1.80 microseconds, using ideal components and neglecting temperature effects on the resonant components. Since the ZERO detect logic will facilitate "true" zero voltage switching, the off-time can be set for a much greater period. The one-shot has a 3:1 range capability and will be programmed for 2.2 uS (max), controllable down to 0.75 uS. Programming of the one-shot requires a single R-C time constant, and is straightforward using the design information and equations from the data sheet. Implementation of this feature is shown in the control circuit schematic.
U-138
lated range of conversion frequencies spans 87 to 310 kHz. These values will be used for this "first cut" draft of the control circuit programming. Due to the numerous circuit specifics omitted from the computer program for simplicity, the actual range of conversion frequencies will probably be somewhat wider than planned. Later, the actual timing component values can be adjusted to accommodate these differences.
First, a minimum fc of 75 kHz has been selected and programmed according to the following equation:
Fvc°""" = 3.6/(R,,,,nCvco) The maximum/c of350 kHZ is programmed by:
Fvco"""' = 3.6/(R,,,;n II R,0,.)·Cvco
Numerous values of R,,,;n and Cvco will satisfy the equations. The procedure can be simplified by letting R,,,;n equal lOOK.
Cvco (µF) = 0.036/f,,,;n (kHz)
RRANGE (kO) = 100/<JcoNVmtuffcoNVrnin - 1)
where Rmin=lOOK, Cvc0 =410pF,RRANGE = 27K The VCO gain in frequency per volt from
the error amplifier output is approximated by:
dF/dV = 1/(RRANG8 Cvc0 ) = 78.2 kHz/V
with an approximate 3.6 volt delta from the error amplifier.
VOLTAGE CONTROLLED OSCILLATOR E/A
VCO
Programming the VCO. The calcu-
Fig. 27 - E/A - VCO Block Diagram
9·441
APPLICATION NOTE
Fault Protection · Soft Start & Restart Delay: One of the unique features of the UC 3861 family of resonant mode controllers can be found in its fault management circuitry. A single pin connection interfaces with the soft start, restart delay and programmable fault mode protection circuits. In most applications, one capacitor to ground will provide full protection upon power-up and during overload conditions. Users can reprogram the timing relationships or add control features (latch off following fault, etc) with a single resistor.
Selected for this application is a 1 uF softrestart capacitor value, resulting in a soft-start duration of 10 ms and a restart delay of approximately 200 ms. The preprogrammed ratio of 19:1 (restart delay to soft start) will be utilized, however the relevant equatio~s and relationships have also been provided for other applications. Primary current will be utilized as the fault trip mechanism, indicative of an overload or short circuit current condition. A current transformer is incorporated to maximize efficiency when interfacing to the three volt fault threshold.
Optional Programming of Tss and TRD :
Soft Start: Tss = CsR· lOK
Restart Delay: TRD = CsR· 190K
Timing Ratio: TRD:Tss ~ 19:1
Gate Drive: Another unique feature of the UC 3861-64 family of devices is the optimal utilization of the silicon devoted to output totem pole drivers. Each controller uses two pins for the A and B outputs which are internally configured to operate in either unison or in an alternating configuration. Typical performance for these 1 Amp peak totem pole outputs shows 30 ns rise and fall times into lnF.
Loop Compensation -- General Information. The ZVS technique is similar to that of conventional voltage mode square wave conversion which utilizes a single voltage feedback loop. Unike the dual loop system of current mode control, the ZVS output filter section exhibits
U-138
200
150 Time
(aa) 100
CsR·lllf 50
Soft Start TitH(".aOma) 0 ....__..___......__.....__ _.__ _ __
zot sot 1001c zoot soot 1M H ···tart Delay aeaiatence
Fig. 28 -- Programming Ta and TRD
PA ULT
OPERATIOR
I
I
I
I
I
I
t =?I I HIlOl'H!'~! IOlUL
llHU'l DIJ.11
- -IOn ITJ.l'l IOU
Fig. 29 - Fault Operational Wavefonns
a two pole-zero pair and is compensated accordingly. Generally, the overall loop is designed to cross zero dB at a frequency below one-tenth that of the switching frequency. In this variable frequency converter, the lowest conversion frequency will apply, corresponding to approximately 85 KHz, for a zero crossing of 8.5 KHz. Compensation should be optimized for the highest low frequency gain in addition to ample phase margin at crossover. Typical eKamples utilize two zeros in the error amplifier compensation at a frequency equal to that of the output filter's two pole break. An additional high frequency pole is placed in the loop to combat the zero due to the output capacitance ESR, assuming adequate error· amplifier gainbandwidth.
A noteworthy alternative is the use of a two loop approach which is similar to current mode control, eliminating one of the output poles. One technique known as Multi-Loop Control for Quasi-Resonant Converters (18] has been
9-442
APPLICATION NOTE
developed. Another, called Average Current Mode Control is also a suitable candidate.
1
w ,.1 = RF,.cF
1
w z1 = (RF,. llRn) CF
1
Gain at f w f.D.
Fig. 30 - Em>r Amplifier Compensation
U-138
Summary
The zero voltage switched quasi-resonant technique is applicable to most power conversion designs, but is most advantageous to those operating from a high voltage input. In these applications, losses associated with discharging of the MOSFET output capacitance can be significant at high switching frequencies, impairing efficiency. Zero voltage switching avoids this penalty by negating the drain-to-source, "off-state" voltage via the resonant tank.
A high peak voltage stress occurs across the switch during resonance in the buck regulator and single switch forward converters. Limiting this excursion demands limiting the useful load range of the converter as well, an unacceptable solution in certain applications. For these situations, the zero voltage switched multiresonant approach (14,15] could prove more beneficial than the quasi-resonant ZVS variety.
Significant improvements in efficiency can be obtained in high voltage, half and full bridge ZVS applications when compared to their square wave design complements. Clamping of
La Tl
L,
UC 1864
l l 100 UP
T2 11100 ~-r..f--------4 PA.ULT
OUTA 1--..---+--i--_,.--"./l/'v--il~ OUTB 1--1--+--+--+---'
"'
1-
llOk
o,
l
Yea. v DI
+
c,11000 UP
Voa'I > - - - - - - 1 B/A+
~------1 B/A-
svl---+----+---4--l
10IC
--11----",/\/\,--! CO·r
ltC
1-----ICSR
SORD
R
It
C
r . . r·;: RA.RGI MI· YCO
luF
au: oOJ:Ino pP
lM
SPECIFICATIONS
'Yz· · 11 TO JIY ·a
lo· 2, 5 TO 1 OJ.
Pu1 · 5001.HZ
Fig. 31 -- Zero Voltage Switched Forward Converter
9-443
APPLICATION NOTE
the peak resonant voltage to the input rails avoids the high voltage overshoot concerns of the single switch converters, while transformer reset is accomplished by the bidirectional switching. Additionally, the series transformer primary and circuit inductances can beneficial, additives in the formation of the total resonant inductor value. This not only reduces size, but incorporates the detrimental parasitic generally snubbed in square wave designs, further enhancing efficiency.
U-138
A new series of control ICs has been developed specifically for the zero voltage switching techniques with a list of features to facilitate lossless switching transitions with complete fault protection. The multitude of functions and ease of programmability greatly simplify the interface to this new generation of power conversion techniques; those developed in response to the demands for increased power density and efficiency.
.,
aa:rDOS
:ua 'lD :11ov
H
ea
·v
... ·Vz·----1\N.________ TO · 1w ...
.... YCUU
.
.
...
&&t IU
... Ion ... -------'=---1 £/A+
... >--AAJ'oo-----..1
E/t.
..__""'...__ co··
1..... ·... '---.AAl'-----1 IOft' llf
UI
111
......
Fig. 32 -- Zero Voltage Switched Half-Bridge Converter
9-444
APPLICATION NOTE
References
[1) P. Vinciarelli, "Forward Converter Switching At Zero Current," U.S. Patent # 4,4I5,959 (1983)
[2] K. H. Liu and F. C. Lee, "Resonant Switches - a Unified Approach to Improved Performances of Switching Converters," International Telecommumications Energy Conference,· New Orleans, 1984
[3) K. H. Lieu, R. Oruganti, F. C. Lee, "Resonant Switches - Topologies and Characteristics," IEEE PESC I985 (France)
[4) M. Jovanovic, D. Hopkins, F. C. Lee, "Design Aspects For High Frequency Off-line Quasi-resonant Converters," High Frequency Power Conference, 1987
[5] D. Hopkins, M. Jovanovic, F. C. Lee, F. Stephenson, "Two Megahertz Off-Line Hybridized Quasi-resonant Converter," IEEE APEC Conference, I987
[6] W. M. Andreycak, "1 Megahertz 150 Watt Resonant Converter Design Review, Unitrode Power Supply Design Seminar Handbook SEM-600A, I988
[7] A. Heyman, "Low Profile High Frequency Off-line Quasi Resonant Converter," IEEE I987
[8] W. M. Andreycak, "UC3860 Resonant Control IC Regulates Off-Line 150 Watt Converter Switching at 1 MHz," High Frequency Power Conference I989
[9] M. Schlect, L. Casey, "Comparison of the Square-wave and Quasi-resonant Topologies," IEEE APEC Conference, 1987
[10] M. Jovanovic, R. Farrington, F. C. Lee, "Comparison of Half-Bridge, ZCS-QRC and ZVS-MRC For Off-Line Applications," IEEE APEC Conference, I989
[11] M. Jovanovic, W. Tabisz, F. C. Lee, "Zero Voltage-Switching Technique in HighFrequency Off-Line Converters," IEEE PESC, I988
U-138
[12] R. Steigerwald, "A Comparison of HalfBridge Resonant Converter Topologies," IEEE I987
[13] J. Sabate, F. C. Lee, "Offline Application of the Fixed Frequency Clamped Mode Series-Resonant Converter," IEEE APEC Conference, 1989
[14] W. Tabisz, F. C. Lee, "Zero VoltageSwitching Multi-Resonant Technique - a Novel Approach to Improve Performance of High Frequency Quasi-Resonant Converters," IEEE PESC, I988
[15] W. Tabisz, F. C. Lee, "A Novel, ZeroVoltage Switched Multi-Resonant Forward Converter," High Frequency Power Conference, 1988
[16] L. Wofford, "A New Family of Integrated Circuits Controls Resonant Mode Power Converters," Power Conversion and Intelligent Motion Conference, 1989
[17] W. Andreycak, "Controlling Zero Voltage Switched Power Supplies," High Frequency Power Conference, I990
[18] R. B. Ridley, F. C. Lee, V. Vorperian, "Multi-Loop Control for Quasi-Resonant Converters," High Frequency Power Conference Proceedings, I987
Additional References:
· "High Frequency Resonant, Quasi-Resonant and Multi-Resonant Converters,'' Virginia Power Electronics Center, (Phone# 703-9614536), Edited by Dr. Fred C. Lee
· "Recent Developments in Resonant Power Conversion," Intertec Communication Press (Phone # 805-658-0933), Edited by K /(jt Sum
9-445
APPLICATION NOTE
10 ' Zero Voltage Switching Calculations and Equations 20 ' Using the Continuous Current Buck Topology
30 ' in a Typical DC/DC Converter Power Supply Application 40 ,
50 PRINTER$ = "lptl:": ' Printer at parallel port #1 ********** 60 ,
70 ' Sunmary of Variables and Abbreviations 80 ,
90 ' Cr = Resonant Capacitor 100 ' Lr · Resonant Inductor
110 ' Zr = Resonant Tank Impedance 120 ' Fres = Resonant Tank Frequency (Hz) 130 ,
140 ' VImin = Minimum DC Input Voltage
150 ' VImax = Maximum DC Input Voltage
160 ' Vdson = Mosfet On Voltage = Io*Rds
170 ' Rds = Mosfet On Resistance
180 ' Vdsmax = Peak MOSFET Off State Voltage
190 ' Vo = DC Output Voltage 200 ' Vdo · Output Diode Voltage Drop
210 220
' '
Iomax Iomin
· Maximum Output
= Minimum Output
Current Current
230 ,
240 ' Start with parameters for ·low voltage de/de buck regulator 250 ,
260 ' ****Define 5 Vi and 5 Io data points ranging from min to max*****
270 ' (Suggestion: With broad ranges, use logarithmic spread) 280 DATA 18,20,22,24,27 : 'Vi data
290 DATA 2.5,4,6,8,10 : 'Io data
300 FRES = 500000!
310 VO = 5!
320 VDO = .8
330 RDS = .8 340 SAFT = .95
350 '
360 FOR J = 1 TO 5: READ VI(J): NEXT
370 FORK= 1 TO 5: READ IO(K): NEXT
380 CLS
390 PRINT "For output to screen, enter 'S' or 'S' ,"
400 INPUT "Otherwise output wi 11 be sent to printer : ". K$ 410 IF K$ = "S" OR K$ = "s" THEN K$ = "scrn:" ELSE K$ = PRINTER$
420 OPEN K$ FOR OUTPUT AS #1: CLS
430 PRINT #1, "================================================"
440 PRINT #1, " Zero Voltage Switching Times (uSec) vs. Vi, Io"
450 PRINT #1, "================================================" 460. ,
U-138
9-446
APPLICATION NOTE
470 ' ···=·====HERE GOES======··===
480 '
490 VIMAX · VI(5): IOMIN · IO(l): IOMAX · I0(5)
500 ZR = (VIMAX - (RDS * IOMIN)) I (IOMIN * SAFT)
510 WR · 6.28 * FRES
520 CR · 1 I (ZR * WR)
530 LR · ZR I WR
540 '
550 FOR J · 1 TO 5: VI · VI(J)
560 PRINT #1, USING "
Input Voltage .. ###.## V"; VI
570 FOR K · 1 TO 5: IO · IO(K)
580 RSIN · (VI I (IO* ZR)): VDSON ·RDS* IO
590 I
600 D(O, K) · IO* .000001: ' Compensate for later mult. by 10"6
610 D(l, K) · (CR * VI) I IO: 'dtOl
620 0(2, K) · (3.14 I WR)+ (1 I WR)* ATN(RSIN I (1 - RSIN. 2)): 'dt12
630 D(3, K) · (2 *LR* IO) I VI: 'dt23
640 D(6, K) · D(l, K) + D(2, K) + D(3, K): 'dt03
650 D(4, K) ·((VO+ VDO) * D(6, K)) I ((VI - VDSON) - (VO+ VDO)): 'dt34
660 D(5, K) · D(l, K) + D(2, K) + D(3, K) + D(4, K): 'Tconv
670 NEXT K
680 I
690 PAR$(0) = "Io (A) ="
700 PAR$ (1) = "dtOl ="
710 PAR$(2) = "dtl2 ="
720 PAR$(3) = "dt23 ="
730 PAR$(4) = "dt34 ="
740 PAR$(5) = "Tconv ="
750 PAR$(6) = "dt03 ="
760 '
770 FOR P = 0 TO 6
780 PRINT #1, PAR$(P);
790 FOR K = 1 TO 5
800
PRINT #1, USING"####.###"; D(P, K) * 1000000!;
810 NEXT K: PRINT #1,
820 NEXT P
830 PRINT #1,
840 NEXT J
850 '
860 PRINT #1, "Additional Information:"
870 PRINT #1, "Zr(Ohms) ="; INT(lOOO! * ZR) I 1000
880 PRINT #1, "wR(KRads)="; INT(WR I 1000)
890 PRINT #1, "Cr(nF) ="; INT((lOOO * CR) I 10 - -9) I 1000
900 PRINT #1, "Lr(uH) ="; INT((lOOO * LR) I 10 - -6) I 1000
910 PRINT #1, "Vdsmax ="; VI MAX * (1 + IOMAX I IOMIN)
920 END
U-138
9-447
APPLICATION NOTE
================================================
Zero Voltage Switching Times CuSec) vs. Vi, Io
=================In=p=u==t =V==o=l=t=a=g=e==· ===1=8=.0=0==v=========
Io CA> = 2.500 4.000 6.000 8.000 10.000 dt01 = 0.218 0.136 0.091 0.068 0.054
dt12 = 1.290 1.153 1.096 1.070 1.056 dt23 = 0.931 1.490 2.235 2.980 3.725 dt34 = 1.387 1. 791 2.682 4.118 6.677
Tconv = 3.825 4.571 6.103 8.236 11.511
dt03 = 2.439 2.780 3.421 4.118 4.835
lo (A) = dt01 =
dt12 · dt23 · dt34 · Tconv · dt03 ·
Input Voltage · 20.00 v
2.500 4.000 6.000 8.000
0.242 0.151 0.101 0.076 1.339 1.175 1.108 1.079
0.838 1.341 2.011 2.682 1.150 1.406 1.987 2.852
3.569 4.074 5.207 6.688 2.419 2.667 3.220 3.836
10.000 0.061 1.062 3.352 4.186
8.661 4.475
lo (A) =
dt01 =
dt12 = dt23 = dt34 =
Tconv =
dt03 =
Input Voltage · 22.00 v
2.500 4.000 6.000 8.000 0.266 0.166 0.111 0.083 , .390 1.198 1.120 1.087
0.762 1.219 1.829 2.438
0.988 1. 153 1.557 2.136 3.406 3.737 4.616 5.744
2.418 2.584 3.060 3.608
10.000 0.067 1.069 3.048 2.958 7.141 4.183
Io CA) = dt01 dt12 dt23 dt34
Tconv dt03
Input Voltage= 24.00 v
2.500 4.000 6.000 8.000 0.290 0.182 0.121 0.091 1.442 1.223 1.133 1.096
0.698 1.117 1.676 2.235 0.870 0.975 1.268 1.682 3.301 3.498 4.199 5.103 2.431 2.522 2.930 3.421
10.000
0.073 1.075 2.794 2.241 6.183 3.941
Io (A) =
dt01 = dt12 dt23
dt34
Tconv = dt03
Input Voltage = 27.00 v
2.500 4.000 6.000 8.000 0.327 0.204 0.136 0.102 0.516 1.264 1.153 1.109 0.621 0.993 1.490 1.987
0.442 0.793 0.983 1.253 1.906 3.254 3.763 4.451 1.464 2.461 2.780 3.198
10.000 0.082 1.085 2.483
1.604 5.254
3.650
Additional Information: Zr(Ohms) = 10.526
wRCKRads)= 3140 CrCnF) = 30.254 Lr(uH) = 3.352
Vdsmax = 135
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9-448
U-138
n nINTEGFIATEC
~ CIRCUITS
-uNITRODE APPLICATION NOTE
U-139
THE UCC3883 AND UCC3885 MEET ISDN REQUIREMENTS IN A SWITCH MODE POWER CONVERTER
Larry Wofford Design Manager
ABSTRACT
The recommendations of Section 9 from CC/TT 1.430 include several requirements that make the design of /SON compatible power supplies complicated. This paper covers a set innovative solutions to simplify the design task using a new pair of integrated circuits. Specific areas addressed will include:
1) Providing a highly regulated output voltage while maintaining galvanic isolation, 2) Soft Starting a power converter with an isolation barrier in the voltage feedback loop, 3) Synchronization of an isolated power converter, 4) Providing continuous inrush current limit capability, 5) Communicating restricted mode and other status information to a secondary-side CPU or controller, 6) Handling output overload conditions in a flyback topology, and 7) Power consumption budgeting for /SON restricted mode operation.
ISDN POWER SUPPLIES
The design of ISDN terminal equipment (TE) power supplies, in many ways, is identical to the common garden variety 1OOW computer power supply... at least the physics of the power transfer comes from the same text book. However, ISDN supplies are typically very demanding in the areas of size, cost, and efficiency. A supply required to be fully compatible with the recommendations of CCITT 1.430 has significant additional complexity. Solutions to the specific technical hurdles will certainly be accepted as commonplace soon. For
the time being, however, they represent some new challenges.
Galvanic isolation is often required. Transformer coupled switching stages nicely address the isolation issue for power transfer, but other entities must cross the isolation boundary besides power. If tight output regulation is not at issue, then a tertiary winding can be used to achieve some level of regulation. However, many times output regulation must be controlled from
Vc=VA
Pulse Width to Voltage Decoder
Ramp
Sync
Oscillator
Voltage to Pulse
Width Encoder
Oscillator
+
Primary Side
Isolated Secondary Side
FIGURE 1A ISOLATION FEEDBACK BRIDGE
9-449
Vout Sense
APPLICATION NOTE
the secondary side of the circuit. This means a feedback signal must also cross the isolation boundary.
Common to any isolated supply with feedback across the isolation boundary is the problem of starting the supply. Some sensible fashion of primary side "blind" soft start followed by a secondary side take over must be carefully planned.
ISDN supplies have other bits of information that need to cross the boundary. If voice band aliasing is a key concern, then a synchronizing signal must cross the boundary from a secondary side frequency reference to slave the repetition rate of the power switch. In addition, restricted mode information from the Network Termination (NT) is conveyed to the TE via line polarity. This information then, is on the primary side of the power supply, but needs to be known on the secondary side. Another useful item of information is the status of the line voltage which presents the same problem as the restricted mode status information.
Another feature required of ISDN supplies is inrush current limiting. Again, though this is not a new concept topowersupplies, itisimportantfornewreasons. Highpower converters are fed from low impedance sources and inrush currents can be large enough to damage components if not properly managed. ISDN supplies, being fed from relatively high impedance lines, need to control inrush so as not to interfere with other TEs already connected to the network. Inrush events of concern occur when a TE is connected to a network or when the NT reverses polarity from normal mode to restricted mode or vice versa.
U-139
Of all the differences, perhaps one of the most dramatic is the requirement to process power over an extremely wide range. In restricted mode, when the TE can draw only 25mW, it is essential that both good output regulation be maintained while holding efficiency as high as possible. The discontinuous flyback is most often chosen as the topology to accomplish this feat.
SECONDARY SIDE REGULATION
The discontinuous flyback topology, chosen for it's efficiency at light load, naturally lends itselfto power transfer across an isolation boundary. In order to achieve tight output regulation over all conditions, the voltage reference and error amplifier must reside on the secondary side of the circuit. The output of the error amplifier must then be transmitted to the primary side of the circuit in order to close the feedback loop.
The UCC2885 and UCC2883 are new control chips designed specifically for ISDN supplies. A pulse width encoded scheme (Figure 1) is used by the chip set to bridge the isolation barrier.
TRANS-ISOLATION COMMUNICATIONS
Key to achieving good regulation with galvanic isolation is the trans-isolation communications scheme implemented by the 2885 and 2883. The isolation boundary is bridged by a pulse transformer which carries four distinct information entities across the boundary.
Secondary Side
UCC2885
Ramp
~v 1~· / v
VA
I
I
Pulse
I
Transformer I
I
I
I
I
Primary Side
UCC2883
Ramp
~ ~/ ~v
Ve
FIGURE1B ISOLATION FEEDBACK WAVEFORMS
9450
APPLICATION NOTE
The first bit of information is clock synchronization. At the beginning of a normal oscillator period on the secondary side, the 2885 will drive a very short duration positive polarity pulse through the transformer. This pulse is used to synchronize the oscillator on the 2883. The same timing components are used on both chips to achieve optimal tracking of the oscillator ramps. Since the 2883 frequency is slaved to the 2885, an external frequency reference introduced to the 2885 SYNC input will automatically lock the converter to a master frequency reference. The SYNC input is CMOS logic compatible.
It is important that both chips have similar oscillators, since they play a key role in transferring the error amplifier information across the boundary. The secondary side oscillator ramp is compared to the error amplifier output in classical pulse width modulation fashion. When the ramp crosses the amplifier output, a second pulse is applied to the transformer, this one of identical duration but opposite polarity. On the primary side,this pulse is used to sample and hold the 2883 oscillator ramp. This voltage is the decoded analog of the secondary side error amplifier output. Even if the oscillator ramps have a 20% mismatch, that represents only 2dB of gain error which has no impact on either loop compensation or output regulation accuracy.
A key benefit to this communications technique is the fact that the feedback signal is digitally encoded before it crosses the isolation boundary, resulting in excellent noise immunity in a naturally noisy environment. Another noteworthy item is that the short pulses driven into the transformer allow minimum power loss in the technique while requiring as little as 50uH of magnetizing inductance.
What if the 2885 error amplifier is temporarily driven fully low by a negative load step? Contrary to the description above, the 2885 will ship a single negative polarity pulse at the beginning of each oscillator cycle. The 2883 understands this as a request for zero duty cycle while maintaining oscillator synchronization. This confirms to the 2883 that the 2885 is still in control.
The other two bits of information flow from the primary to the secondary. The 2883 has two comparators to monitor restricted mode status and line voltage. When the 2883 receives the first pulse to mark the beginning of the oscillator period, if the NT is in normal mode, the 2883 will shunt a low value of resistance across the pulse transformer. This sudden impedance change is detected by the 2885 and it latches this data which will then appear at the RMODE pin of the 2885 indicating
U-139
the system is not in restricted mode. If the NT changes polarity for restricted mode, then the shunting action will not take place and the 2885 will appropriately decode this fact and change the RMODE status output.
Likewise, if the 2883 detects low input line voltage then the same shunting action occurs during the second communications pulse. The 2885 interprets this action and drives the LOLINE status output accordingly.
Implemented this way, the Low Line information actually has priority over restricted mode information, since it is carried on the second pulse instead of the first. (Recall the first will not occur when the 2885 is requesting zero duty cycle.) The power loss caused by the shunting resistor is small, but even so, the convention chosen requires no shunting action when the system is in restricted mode and the line is sufficiently high. This is the set of circumstances where efficiency is most critical.
Note the magnetizing current in the pulse transformer is not going to become unwieldy. For normal operation, the widths of the first and second pulses track and so there is first ordervolt second balance. Between pulses the 2885 drives both terminals of the transformer low. Any mismatch in communication pulses will result in a circulating current between pulses. Two things limit this current. First is the selection of the magnetizing inductance. While the chips will function with 50uH, larger values will obviously reduce circulating current and lower the power loss. Secondly, the 2885 driver has finite impedance, and will tend towards a compensating offset voltage to keep the core balanced. For reasonable values of magnetizing inductance, this offset voltage will not materially affect the noise immunity of the communications scheme.
PRIMARY SIDE "BLIND" SOFT START
Orderly start up using the 2885 and 2883 is a relatively simple task. When line voltage is first applied (Figure 2), a depletion mode NMOS controlled by a linear preregulator amplifier in the 2883 supplies initial start up current. The control amplifier will regulate Vee to 9.5V. Afterthe power supply is operational, a boot strap winding will more efficiently supply power to the IC by raising Vee above 9.5V. The control amplifier, driven out of regulation, will hold the gate of the NMOS at ground. When the rising supply voltage (Figure 3) to the 2883 exceeds 4.4V, the chip will initiate a blind soft start. The capacitor on the CSTART pin is slowly charged by a
9-451
APPLICATION NOTE
9.5V
BSS129, OR EQUIV.
11+5""" TERTIARY
LI WINDING
·
16V
U-139
FIGURE2 9.SV PRE-REGULATOR
25uA current. The rising voltage on CSTART is compared to the free running local oscillator to pulse width modulate the output switch.
As the duty cycle increases, progressively more and more energy is delivered to the secondary side and the output voltage begins to rise. The 2885 will remain donnant until it's Vee exceeds 2.8V. This is the point at which it starts charging the capacitor on SOFT REF. The 2885 issues no feedback pulses, however, until the SOFT REF catches the sense voltage fed back to the inverting input of the error amplifier forcing the amplifier
output high.
Upon receipt of thefirstfeedbacksignals from the 2885, the 2883 immediately ceases it's blind soft start and begins obeying the feedback signal from the 2885. Orderly soft start is then completed under closed loop control as SOFT REF finishes charging to 2.0V.
TRANSIENT LINE CURRENT
J.430 strictly addresses the surge current a TE may
'",J
J CSTART c,. 0
J OUT 0
{SHOOF PWOSSSRIBALNEGE OUTPUT PULSE WIDTHS
FB
1 0 r- UVLO ---.------
PEAK CURRENT
BLIND SOFT START - - - - - - - o - M O D E REGULATION50% D.C. MAX
FIGURE3 START UP WAVEFORMS
9-452
APPLICATION NOTE
require of the NT. For practical purposes, it is sufficient to discuss a current mask composed of an undefined current for an initial period of 5us followed by a limited current of 55mA. There is more that must be considered to achieve full compliance, but solving this part of the exercise will make the remainder rather trivial.
The 2883 is used to control (Figure 4) a PMOS device in series with the return of the power feed. Current programmed by an external resistor RBIAS is scaled and forced into the input current limit resistor RP. TE return current is sensed by resistor RS. As long as the drop across RS is less than the drop on RP, the control amplifier will saturate in the negative direction causing the PMOS to behave as a low resistance switch. If return current attempts to increase without bound, the amplifier takes over and the current is held to a value programmed as:
ILIMIT =(RP/RS+ 1) * 0.4V I RBIAS.
RP and RS should be chosen for a voltage drop large enough to render control amplifier offset inconsequential. Remember, however, that large values of RS represent power loss. This is most likely only a full load concern, and has little effect on restricted mode. For example, if the current limit value is 55mA and RS is chosen for a 150mV drop, then when running at 24V in
U-139
restricted mode, the loss in RS is only 3uW. Efficiency at full load (assuming 1W) is impacted by a loss of 4.7mW (less than 0.5%).
The 1OpF capacitor across RP is added to maintain good phase margin in the control loop. The diode shunting RS will limit any error voltage stored on the 10pF cap during the initial inrush transient.
Note that resistor RI shunting the PMOS is essential to start up. When power is first applied, the control amplifier output cannot go to a negative potential. RI will bleed charge onto the input bypass capacitor until there is enough voltage for the 2883 to operate properly.
RESTRICTED MODE POWER BUDGET
Blanc [Reference 2] has carefully analyzed the power consumption budget of a supply intended to be partially compatible with 1.430. Essentially there is no change in that evaluation for the 2885 and 2883 and it need not be repeated here. When operating with 25mW of input power, a fully 1.430 compatible supply built with the 2885 and 2883 can supply approximately 13mW of regulated power.
i
I REF =---2.:£_
RBIAS
10pF
SWITCHER
Cc Rs
CsuLK
UCC1883
FIGURE4 INPUT CURRENT LIMIT
9-453
APPLICATION NOTE
1.430 recommendations also allow for supplies operating at higher input line voltage, and at power levels up to SW. The bias current in the chip set is programmable and the power switch is external to allow for evolving 1.430 specification.
U-139
shut down. A restart delay period will be observed before switching may again commence. This method will effectively limit the duty cycle of the stress on the output diode, allowing the diode to be specified for full load operation instead of over specified for short circuit operation.
OVERLOAD MANAGEMENT
Perhaps a drawback of the discontinuous flyback converter is the current stress the output diode must ehdure during short circuit. If the diode is chosen to survive this condition, then it is vastly over designed for nominal full load conditions. A means to alleviate this problem is to never allow the converter to operate for extended periods of time in a current limit condition.
The 2883 has a pin to time overload conditions (Figure 5). A current will charge or discharge a capacitoron the overload pin, COL. As long as each pulse is terminated by normal PWM action, the current discharges the pin. When ever the output is terminated due to lsense exceeding the peak current limit threshold, the COL pin is charged. If a number of consecutive cycles are terminated for this cause, then the COL voltage will exceed an internal 1.5V threshold causing the chip to
On any cycle that the lsense pin exceeds the peak current limitthreshold by 25%, the chip will immediately shut down and initiate restart delay.
SUMMARY -A SAMPLE ISDN 1W SUPPLY
Power supplies for ISDN applications can be designed without inordinate pain where the special requirements of 1.430 are concerned (Figures 6, 7 and 8). The primary and secondary are galvanically isolated in a supply using the UCC2883/2885 chip set. Better than 3% output regulation can be achieved for input power ranging from 25mW to 1W. Efficiency at 25mW will exceed 50%. Inrush current can accurately be limited to 55mA both for line transients and for hot connection to the line. Initial inrush transient currents in excess of 55mA will be suppressed within 5us. Input line polarity and amplitude can be known on the secondary side via two CMOS logic compatible status bits.
-1.2V
lseNSE OJ 1111lllllllll1111111lllll
I
I
I
I
J COL
0
sv
CSTART
t
-
-
-
-
-
-
-
-
-
-
-
-
~·"~1 ~i~ 1~1m v-____,.......,...
-1.SV
-1.SV
.1.l.l1.._ _v.___-+--_
s . ov
~ --..j.-- OUTPUT OVERLOAD INTEGRATION
i
OVERLOAD FAULT
RESTART DELAY
0.2V
--+i1 SOFT START
r--
i
PRIMARY CURRENT
FAULT
RESTART DELAY
--l-8ESTA~l. DELAY
i
PRIMARY CURRENT
FAULT
FIGURES OVERLOAD WAVEFORMS
9-454
V+O
V-
I
I
m
4.
BS107A
+ 220µF I
I 6.2V I 0.1 µF
..J,,>,,
r-
~
~
0 z
z
+5VOUT
~
m
OUTPUT GROUND
1µF 301Kn
200Kn
~
§
~ I
1:1
RESTRICTED MODE
: ~~:CLINE
FIGURES ISDN 1W SUPPLY
.c.I.:.
Ct.)
co
APPLICATION NOTE
Vee VREG Yoo RelAS
5V REFERENCE 9.5V
BIAS CURRENT
RUN
FAULT LOGIC
Cr
Col ~N VLIMIT
VLINE
3
IMOoE 4
OSCILLATOR &TIMER
INPUT CURRENT
LIMIT
ff
1.2V
SAMPLE &HOLD
S/H
VAOUT
FIGURE7 UCC2883 BLOCK DIAGRAM
PWM CONTROL
LOGIC &
OUTPUT DRIVER
LEADING EDGE
BLANKING
ISOLATION INTERFACE
U-139
2 CsrART 6 FB+ 7 FB-
SOFT REF
2V REFERENCE
UVLO
~----- UVLO
PWM LOGIC
OUT
ISOLATION INTERFACE
1------. TO ANALOG CIRCUITS 1.2V
~ GND
FIGURES UCC2885 BLOCK DIAGRAM
ACKNOWLEDGEMENT
REFERENCES
Grateful acknowledgement is extended to Ray Orr and Dave Cooper of Bell Northern Research for help
1) CCITT Recommendation 1.430, Section 9
understanding 1.430 and it's ramifications.
2) J. Blanc, "ISDN DC/DC conversion to the CCITT
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standards", Communications International, June 1989 9-456
n n INTEGRATED
~CIRCUITS
-UNITROCE
APPLICATION NOTE
Average Current Mode Control of Switching Power Supplies
Lloyd Dixon
U-140
Abstract
Current mode control as usually implemented in switching power supplies actually senses and controls peak inductor current. This gives rise to many serious problems, including poor noise immunity, a need for slope compensation, and peak-to-average current errors which the inherently low current loop gain cannot correct. Average current mode control eliminates these problems and may be used effectively to control currents other than inductor current, allowing a much broader range of topological application.
is nearly equivalent to average inductor current control.
In a conventional switching power supply employing a buck derived topology, the inductor is in the output. Current mode control then is actually output current control, resulting in many performance advantages. On the other hand, in a high power factor preregulator using the boost topology, the inductor is in the input. Current mode control then controls input current, allowing it to be easily conformed to the desired sinusoidal waveshape.
General Perspective
Peak Current Mode Control Problems
Current mode control is a two-loop system as shown in the simple example of Fig. 1. The switching power supply inductor is "hidden" within the inner current control loop. This simplifies the design of the outer voltage control loop and improves power supply performance in many ways, including better dynamics. The objective of this inner loop is to control the state-space averaged inductor current, but in practice the instantaneous peak inductor current is the basis for control. (Switch current --equal to inductor current during the "on"
Poor noise immunity. The peak method of inductor current control functions by comparing the upslope of inductor current (or switch current) to a current program level set by the outer loop-see Fig. 1. The comparator turns the power switch off when the instantaneous current reaches the desired level. The current ramp is usually quite small compared to the progi-amming level, especially when ~N is low. As a result, this method is extremely susceptible to noise. A noise spike is generated each time the switch turns on. A fraction of a volt
time--is often sensed.) If the inductor ripple current is small, peak inductor current control
coupled into the control circuit can cause it to turn off immediately, resulting in a subhar-
monic operating mode
with much greater ripple.
0
v.]1([([ Circuit layout and bypassing are critically important
ill CLOCK
VI
n n n GATE
DRIVU
Li
Li
L
Fig. 1 - Peak Current Mode Control Circuit and Wavefonns
to successful operation. Slope compensation
required. The peak current mode control method is inherently unstable at duty ratios exceeding 0.5,
9-457
APPLICATION NOTE
resulting in sub-harmonic oscillation. A compensating ramp (with slope equal to the inductor current downslope) is usually applied to the comparator input to eliminate this instability. In a buck regulator the inductor current downslope equals VOf'L. With V0 constant, as it usually is, the compensating ramp is fixed and easy to calculate-but it does complicate the design. With a boost regulator in a high power factor application, the downslope of inductor current equals (J'IN-Vo)/L and thus varies considerably as the input voltage follows the rectified sine waveform. A fixed ramp providing adequate compensation will overcompensate much of the time, with resulting performance degradation and increased distortion.
Peak to average current error. The peak to average current error inherent in the peak method of inductor current control is usually not a serious problem in conventional buckderived power supplies. This is because inductor ripple current is usually much smaller than the average full load inductor current, and because the outer voltage control loop soon eliminates this error.
In high power factor boost preregulators the peak/avg error is very serious because it causes distortion of the input current waveform. While the peak current follows the desired sine wave current program, the average current does not. The peak/avg error becomes much worse at lower current levels, especially when the inductor current becomes discontinuous as the sine wave approaches zero every half cycle. To achieve low distortion, the peak/avg error must be small. This requires a large inductor to make the ripple current small. The resulting shallow inductor current ramp makes the already poor noise immunity much worse.
Topology. problems. Conventional peak current mode control actually controls inductor current. As normally used for output current control, it is most effective when applied to a buck regulator where the inductor is in the output. But for flyback or boost topologies the ~doctor is not in the output, the wrong current is controlled, and much of the advantage of
U-140
current mode control is lost. Likewise, the boost topology with its induc-
tor at the input is well suited for input current control in a high power factor preregulator, but buck and flyback topologies are not well suited because the inductor is not in the input and the wrong current is controlled.
Average Current Mode Control
Peak current mode control operates by directly comparing the actual inductor current waveform to the current program level (set by the outer loop) at the two inputs of the PWM comparator. This current loop has low gain and so cannot correct for the deficiencies noted above.
Referring to Fig. 2, the technique of average current mode control overcomes these problems by introducing a high gain integrating current error amplifier (CA) into the current loop. A voltage across Rp (set by the outer loop) represents the desired current program level. The voltage across current sense resistor Rs represents actual inductor current. The difference, or current error, is amplified and compared to a large amplitude sawtooth (oscillator ramp) at the PWM comparator inputs.
The gain-bandwidth characteristic of the current loop can be tailored for optimum performance by the compensation network around the CA. Compared with peak current mode control, the current loop gain crossover fre-
quency, fc, can be made approximately the
same, but the gain will be much greater at lower frequencies.
The result is: 1) Average current tracks the current program with a high degree of accuracy. This is especially important in high power factor preregulators, enabling less than 3% harmonic distortion to be achieved with a relatively small inductor. In fact, average current mode control functions well even when the mode boundary is crossed into the discontinuous mode at low current levels. The outer voltage control loop is oblivious to this mode change. 2) Slope compensation is not required, but
9-458
APPLICATION NOTE
U-140
there is a limit to loop gain at the switching
Example 1: Buck Regulator Output Current.
frequency in order to achieve stability.
The simple buck regulator shown in Fig. 2 has
3) Noise immunity is excellent. When the the following operating parameters:
clock pulse turns the power switch on, the oscillator ramp immediately dives to its lowest level, volts away from the corresponding current error level at the input of the PWM comparator. 4) The average current mode method can be used to sense and control the current in any circuit branch. Thus it can control input current
Switching Frequency, fs = 100 kHz
Input Voltage, ~N "" 15 - 30V
Output Voltage, V0 = 12V
Output Current, I0 = SA (6A O.L.) Inductance, L = 60 µH
max. M 0 @ 30V (100 kHz) = 1.2A
Sense Resistance, Rs = 0.10
accurately with buck and flyback topologies, and can control output current with boost and flyback topologies.
CFP is temporarily omitted. Zero RF Cn is well below the switching frequency. Near fs, the amplifier gain is flat. The overall current
Designing the Optimum Control Loop
Gain Limitation at f5: Switching power supply control circuits all exhibit subharmonic oscillation problems if the slopes of the waveforms applied to the two inputs of the PWM comparator are inappropriately related.
With peak current mode control, slope compensation prevents this instability.
Average current mode control has a very similar problem, but a better solution. The oscillator ramp effectively provides a great amount of slope compensation. One criterion applies in a single pole system: The amplified inductor cu"ent downslope at one input of the PWM comparator must not exceed the oscillator
loop has only one active pole (from the inductor).
The inductor current is sensed through Rs. (How this is accomplished will be discussed later.) The inductor current waveform with its sawtooth ripple component is amplified and inverted through the CA and applied to the comparator. The inductor current downslope (while the switch is oft) becomes an upslope, as shown in Fig. 2. To avoid subharmonic oscillation, this off-time CA output slope must not exceed the oscillator ramp slope. In Fig. 2, the off-time CA output slope is much less than the oscillator ramp slope, indicating that the CA gain is less than optimum.
ramp slope at the other comparator input. This Calculating the slopes:
criterion puts an upper limit on the current
amplifier gain at the switching frequency,
indirectly establishing the maximum current
loop gain crossover frequency, fc· It is the first
thing that needs to be considered in optimizing
Inductor Cu"ent Downslope = Vo/L
Oscillator Ramp Slope = Vs /Ts = Vs fs
Where Vs is the oscillator ramp p-p voltage, Ts and fs are the switching period and frequency.
the average current mode
control loop.
e;:--i .,---_,...---"~---f+--.---.--~
In the following exam- Vin
pies, we assume that the
power circuit design has
been completed, and only
the CA compensation remains to be worked out.
RI Ra
+ Vcp
n r GATEll
ORIV~ lJ LJ
Fig. 2 - Average Current Mode Control Circuit and Wavefonns
9-459
APPLICATION NOTE
The inductor current downslope is translated into a voltage across current sense resistor Rs and multiplied by the C4 gain, GCA. This is set equal to the oscillator ramp slope to determine
the C4 gain allowed at Is=
(Vo/L)RsGCA = Vsls
. . max GCA = 9CA = VslsL (1)
9RS VoRs
Applying the values given in the example, and
with Vs of 5Vpp, the maximum GCA at the
switching frequency is 25 (28dB). The current
error amplifier gain at Is is set to this optimum
value by making the ratio RF/R1 = 25.
The small-signal control-to-output gain of
the buck regulator current loop power section
(from vCA at the C4 output, to vRs, the voltage
across Rs) is:
9RS = Rs ~N = 1590 (@30V) (l)
9CA Vs sL
I
The overall open loop gain of the current loop is found by multiplying (1) and (2). The result is set equal to 1 to solve for the loop
gain crossover frequency, I c :
Rs ~N VslsL 1 Vs 21flcL V0 Rs
IC = ls~N = _.!.!.__
(3)
21fV0 21fD
Setting the C4 gain at the limit found in (1), the crossover frequency will never be less than one sixth of the switching frequency. (This is exactly the same result reported by Middlebrook (1) for peak current mode control with recommended slope compensation.) In this example, fc is 20 kHz with VIN at 15V (D=.8), and 40 kHz when VIN at 30V (D=.4).
If the error amplifier had a flat gain characteristic, the phase margin at crossover would be 90°-much more than required-and the gain at lower frequencies wouldn't be much better than with peak current mode control. But zero RFCFZ placed at 10 kHz, below the minimum crossover frequency, reduces the phase margin
U-140
to 63 °, and boosts the low frequency gain dramatically, with an integrator gain of 250K/f. It is this characteristic which causes the current loop to rapidly and accurately home in on the average current called for by the outer loop. Even though the comparator actually turns off the power switch when a peak inductor current is reached, this peak current level is adjusted by the current amplifier so that the average
current is correct. Fig. 3 shows the start-up waveforms of the
voltages at the PWM comparator inputs and the inductor current with V1N at 30V and full load. Note how the amplified and inverted inductor current downslope virtually coincides with the oscillator ramp, because the CA gain was set at the optimum level according to Equation (1). Note also that if the CA gain is increased further, not only will the off-time slope exceed the oscillator ramp slope, but the positive excursion may reach the CA compliance limit, clipping or clamping the waveform.
at··------------....·--------·---+--------------+--------------+--------------.,.
v. :
i
i
I
I
o·--------------+--------------·--------------+·-------------·-------------1
lt··------------...-------------+--------------+--------------+--------------t
4l
i
1, i
2f
Vln·30 Vo·12
t :
01 ------------··tu··-------···tcs··-;;;-;,···tc;···-------·-&o·---------,-~
Fig. 3 - Buck Wavelonns, Optimized Gain
Pole RFCFPCn/(CFP+Cn) is set at switch-
ing frequency Is (100 kHz). This pole has one
purpose-to eliminate noise spikes riding on the current waveform, the nemesis of peak current mode control. The sawtooth CA output waveform is also diminished, especially the higher order harmonics, and shifted in phase as shown in Fig. 4. The pole-zero pair (at 100 kHz and 10 kHz) reduces the phase margin at crossover to a very acceptable 45°-see Fig. 5.
The reduced amplitude and slopes of the CA waveform resulting from the 100 kHz pole might suggest that the C4 gain could be in-
9-460
APPLICATION NOTE
a t--------------+--------------+--------------+--------------·--------------t
Ve._!
!
'
.i06t+----------------------------·~------------------------+-+---------------------------+----------------------------·+-------------------------"-tl !
IL i
Vln=30
!
2f
Vo=12
i
i
I
0 0. -------------2-0+------------4--0+---.u--·-e-c-----8-0-------------8-·0-----------1-0-~0
Fig. 4 - Buck with Additional Pole at fs 60
20 GAIN
0 dB
- 2 0 1--~-+~~-1-~--.>.d->.-~-+-~--I
10 100 1k 10k 100k 1M
Fig. 5 - Buck Regulator Bode Plot
creased beyond the maximum value from Equation (1), but beware-Eq. (1) is valid only for a system with a single pole response at fs , but with CFP added there are now two active poles at/5 · Experimentally, increasing GCA may incur subharmonic oscillation.
U-140
Discontinuous Operation. When the load current 10 becomes small, the inductor current becomes discontinuous. The current level at the continuous/discontinuous mode boundary is:
Io = IL = Vo(YrN-Vo)
(4)
YrN2fsL
Worst case is at max VJN, when ripple
current is greatest. In this example, the mode
boundary occurs at 10 (=IL) of 0.2A when V/N is 15V, and at 0.6A when VJN is 30V.
In the discontinuous mode, below the mode boundary, changes in 10 require large duty cycle changes. In other words, the power circuit gain suddenly becomes very low. Also, the single pole characteristic of continuous mode operation with its 90° phase lag disappears, so the power circuit gain is flat-independent of frequency. The current loop becomes more stable, but much less responsive.
With peak current mode control in the discontinuous mode, peak/avg current error becomes unacceptably huge. But with average current mode control, the high gain of the current error amplifier easily provides the large duty cycle changes necessary to accommodate changes in load current, thereby maintaining good average current regulation.
Referring to Fig. 2, when the current loop is closed, the voltage across current sense resistor VRS equals the current programming voltage Vcp (from the voltage error amplifier) at frequencies below fs· The transconductance of the closed current loop is a part of the outer voltage control loop:
1
(5)
Rs
The closed loop transconductance rolls off and assumes a single pole characteristic at the open loop crossover frequency, fs·
9-461
APPLICATION NOTE
Example 2: Boost Regulator Input Current. A 1 kW off-line preregulator (Fig 6) operates with the following parameters: Switching Frequency, fs = 100 kHz
Input Volts, JIJN = 90 - 270V rms
Output Volts, V0 = 380Vdc Max. 0.L. [IN (@90V) = 12A rms, 17A pk
L = 0.25mH ML, MIN @90V = 3.4A
Rs= 0.050
The max. overload line current at min. JIJN
corresponds to 1080W input. The max. peak overload 60Hz line current (17A) should-by design-correspond to a limit on the current programming signal, ICP. The max peak lOOkHz current through the switch and rectifier is 17A plus one-half ML: 17 + 3.4/2 = 18.7A
lo Vo
Vs
Fig. 6 - Boost Preregulator Circuit
The current downslope occurs when the power switch is off: Inductor Cu"ent Downslope = (V0 -VrN)/L
Worst case when VrN = 0: = V0 /L
Oscillator Ramp Slope = Vs /Ts = Vs f.
Multiply the downslope by Rs and CA gain and set equal to the oscillator ramp slope, theri solve for maximum CA gain:
Wo/L)RsGCA = Vsfs
(6)
Note the form of Equation (6) is identical to the buck regulator in (1). Using the values for
U-140
this application, the maximum GcA is 6.58,
accomplished by making Rp/R1 = 6.58. The small-signal control-to-input gain of the
current loop power section (from vCA at the CA output, to vRs , the voltage across Rs) is:
j)RS = Rs Vo = 2420
(7)
PCA Vs sL
f
Note that (7) is nearly identical to (2) for
the buck regulator, except the gain depends on
V0 (which is constant), rather than ViN.
The overall current loop gain is found by
multiplying (6) and (7). The result is set equal
to 1 to solve for the crossover frequency, fc:
-Rs- -Vo- -V-sfs-L = 1
Vs 21ffcL V0 Rs
fc = ~
(8)
21f
With the CA gain at the limit found in (6), the current loop fc is fixed at fs/6 (16.7 kHz).
As with the earlier example, with a flat gain error amplifier the phase margin at crossover is 90°-larger than necessary. So zero RFCn is set at 1/2 of the minimum crossover frequency <fc/2 = fs/12 = 8.33 kHz), providing a low frequency boost with an integrator gain of 55K/f. Pole RF CFP Cn/(CFp+Cn) is set at 6 times the zero frequency (50 kHz) to eliminate noise spikes. Together, the zero at 8.33 kHz and the pole at 50 kHz leave a phase margin at crossover of 40°. Startup waveforms are shown in Fig. 7, and the Bode plot in Fig. 8.
v~··············<-·············+·············-+-·············+·············1
4:
0 l--------------+--------------+--------------+---------------+--------------l.
1Ot·-------------+--------------+-------------.......·------------+-;.___________ "t
l~i
i
1:,
VVoin==318700 Pln=1000W ·j
0 ·············2r;;············tcr···········&o············&o----····---i~o
µ.tee
Fig. 7 - Boost Regulator Wavefonns
9-462
APPLICATION NOTE
U-140
Referring back to Fig. 6 - when the current
loop is closed, the voltage across current sense
resistor VRS equals the voltage across current
programming resistor VRCP· In this case, pro-
grammed with a current source I Cl'> the current
gain of the closed current loop is:
.l. G =
= 9RS/Rs = RCP (9)
iCP 9RCP/RcP Rs
The closed loop current gain rolls off and assumes a single pole characteristic at the open
loop crossover frequency, fs·
60
\ \
40
20
GAIN
0 dB - 2 0 f--~-+-~~+-~--+-"<-~+-~--1
10 100 1k 10k 100k 1M
·:~:1 I l/J I I Fig. 8 - Boost Regulator Bode Plot
In a high power factor preregulator application, the current is programmed to follow the rectified line voltage. As the rectified sine wave voltage and current approache the cusp at zero, the inductor current becomes discontinuous. Discontinuous operation can occur over a substantial portion of the line cycle, especially when line. current is low at high line voltage and/or low power input. With peak current mode control, discontinuous operation results in a large peak/average current error. A large inductance is required to make ripple current small and put the mode boundary at a low
current level. However, average current mode control eliminates the peak/average error. A small inductance can and should be used to reduce cost, size and weight and improve current loop bandwidth.
Figure 9 shows a boost preregulator programmed to follow a 60 Hz (rectified) sine wave input. The lower waveforms show the programmed and actual line current waveforms. (The programmed waveform has been increased by 5% to make the two waveforms visible. The actual waveform leads the programmed waveform by a small amount and has less than 0.5% 3rd harmonic distortion! The upper waveforms show the duty cycles of the switch and diode throughout the line cycle. The inductor current is continuous when the current is high, and the switch and diode duty cycles add up to 1. But as the current approaches zero crossing, operation becomes discontinuous as shown by the appearance of "dead" time (when neither the switch, the diode, or the inductor are conducting).
c~~~:-·······+-::·-+········+········+-·······+········+········+-·······;
o.5t
.
. t
i
SWITC
i
:
:
O ' H · · · ··
H
+It--------·--------+--------+--------+--------... ·-------+--------+--------~
1111! Aj
60 Hz
i i
Vln=270
Oi
Yo=390
-&±!' --------·-------A-CTV--A-----+R--O-G--I-W--I+(-x·-l.-0--5-)-...·--P--l-n--:+1-O--O--O-W--+--------+!
0
4 mHC 8
12
18
Fig. 9 - Boost 60Hz Sine Wave Input Cu"ent
Note that the switch duty cycle does not change as much when operation becomes discontinuous. With the boost (and flyback) topology . in the discontinuous mode, average input current tends to follow input voltage at a constant duty cycle. Even though plenty of CA gain is available to change the duty cycle, little change is required for perfect tracking.
Figure 10 shows how the actual input current sine wave tracks the programming signal at 400 Hz. The distortion is worse -- 4.5% 3rd harmonic. This is for two reasons:
9-463
APPLICATION NOTE
Fig. 10 - Boost 400Hz Sine Wave Input Current
1. The .harmonic components of the rectified 400 Hz waveform are at higher frequencies and closer to the ClµTent loop crossover frequency where the loop gain is less, compared with the 50 or 60 Hz harmonics.
2. The inductor current has difficulty rising off zero because the input voltage is so very low at that point. So the inductor current lags coming off zero, then catches up and overshoots the programmed level. (This effect is much worse with peak current mode control because of the large inductor required.)
Controlling Average Switch Current
In the previous examples, average current mode control was applied to controlling inductor current (buck output current and boost input· current). This is relatively easy because the inductor current is mostly DC with only a
small amount of ripple to deal with. But if it is
desired to use a buck or flyback topology to control input current in a high power factor application, then the chopped current waveform through the power switch must be averaged, a more difficult task.
Example 3: Flyback Regulator Input Current: A 1000 W off-line preregulator uses a flyback circuit in order to achieve a standard 300V output bus even though the input voltage ranges above and below 300V (Figs. 11,12).
The· flyback wnverter could be designed to operate in. the discontinuous inductor current mode in this application. The discontinuous flyback converter is not difficult to ·control (crudely) by fixing the duty cycle during each line half-cycle, but the peak currents through the power switch and rectifier are nearly twice as high as 'with continuous mode operation.
0 M""'"''
·111
U-140
lo Yo
+
Rop
Va
lcp
Fig. 11 - Flyback PreregUlator Circuit
The high peak current lowers efficiency and requires devices with higher current ratings.
Continuous mode operation suffers the problem that the boundary is crossed into the discontinuous mode at light loads and high input voltage, unless a large filter inductor is used, which hurts the frequency response and the power factor as well as the pocketbook.
This dilemma disappears with average current mode control because it functions well in the discontinuous as well as the continuous mode, enabling the use of a small inductance value. In this example, the flyback converter operates in the continuous mode when it is important do so--at high current levels, to keep the maximum peak current to half that of a strictly discontinuous flyback converter. The operating parameters are:
Switching Frequency, fs = 100 kHz
Input Volts, ViN = 90 - 270V rms
Output Volts, V0 = 300V de
Max. 0.L.11N (@90V) = 12A rms, 17A pk
L = 0.25mH ML @90V = 3.6A
Rs= 0.0250
The max. overload rms line current at min.
ViN equates to 1080W input (2160Wpk 60Hz).
The max. overload peak 60 Hz line current (17A) should be made to correspond to a limit on the current programming input, lcP· Unlike the boost converter, the flyback input current is chopped, so the peak lOOkHz current through
9-464
APPLICATION NOTE
the switch, the inductor, and the rectifier are much greater than the 60 Hz peak current-see Fig. 12. The worst case, at low line and max. overload input current is:
I
= I PK(«Jllr) = _E_ = 24.2A
PK(lOOkllz)
D
.702
Add to this one-half ML to obtain the absolute max. peak current through the switch,
inductor, and rectifier: 24.2 + 3.6/2 = 26A.
Compared to the boost converter, the flyback topology requires higher current and higher voltage devices and generates a lot more input noise because of the chopped waveform. In its favor, the flyback converter can operate with any input/output voltage ratio, can provide current limiting, and input/output isolation.
As discussed in the previous example, the
boost converter amplifier gain at Is was limited
only by the criteria that the inductor current downslope must not exceed the oscillator ramp slope. The power circuit control-to-input current gain had a simple -1 slope from zero to
Is, making it very easy to compensate.
But with the flyback converter, the chopped switch current waveform will be averaged. This results in a lower crossover frequency, fc, and lower gain-bandwidth for two reasons:
1. The large amplitude chopped current waveform must be integrated by the CA. The upslope of the resulting triangular waveform at the CA output must not exceed the oscillator ramp slope.. (The inductor current downslope is not relevant.)
2. There is a zero (conventional left half-plane) in the control-to-input current gain characteristic. This zero moves with output current level. Loop gain crossover cannot be much higher than the lowest zero frequency.
The small-signal control-to-input gain of the flyback current loop power circuit (from vCA at the CA output, to vRS , the voltage across Rs ) is:
U-140
This is the characteristic of a "normal"
zero-a -1 slope with 90° phase lag below lz and flat gain with no phase shift above Iz· The
zero frequency may be calculated:
Vo
(11)
lz = 2wL/L
Note that the zero moves inversely with inductor current and inductance value. This zero has a big effect on loop compensation. To
obtain the best loop response, it is important
that IZlllin be as high as possible, by.making the
inductance small. Fortunately, with average current mode control, there is no need to worry about crossing into discontinuous operation. The limit on making the inductance too small is when the inductor ripple current becomes too large, increasing peak switch and rectifier currents an undesirable amount.
Using the specific values of this example, the power circuit gain is:
IL . 960
-200
1I-
The minimum zero frequency is 8 kHz,
which occurs at 24.2A, the max. overload inductor current at 90V low line. The gain
above lz is 0.12 (-18.4dB). The power circuit
gain is shown in the Bode plot of Fig. 13.. Turning now to the current error amplifier
(Fig. 11), the chopped input (switch) current waveform shown in Fig. 12 flows through R5. The average value of this waveform, chopped at 100 kHz, is compared to the current program level across Rep and amplified. Assu~e for the moment that CP2 is zero and CFZ is shorted. The CA gain in the vicinity of 100
kHz is determined by integrator (R1+Rn)Cpp· Averaging is accomplished because the DC
gain is high, but the 100 kHz rectangular waveform with its harmonics is amplified
relatively little. The rectangular waveform _is
converted into a triangular wave as shown m
Fig. 12.
9-465
APPLICATION NOTE
a1H·---------------... ·---------------·cp:z-;;o·---------+-----------------1
VcA!
:
4
15 !vi~-~-110·-----v<;;;,;300----------+-----,j;;;;~~aaA·+-----------------1
i Pln=1kW
10+ ~!
+ ; ;
5f
Fig. 12 - Flyback Regulator Wavefonns
The optimum C4 integrator gain at 100 kHz is the gain at which the maximum C4 output upslope equals the oscillator ramp slope. This is the same principle used in the previous two examples, but in those cases the inductor (whose current was being controlled) did most of the averaging. The inductor did the integration to provide the triangular ripple current waveform and the CA gain was flat in the vicinity of fs· But in this flyback preregulator example, the chopped switch current is being controlled so the averaging and the triangular waveshape are achieved by an integrating amplifier.
The upslope of the CA output occurs when the switch is off and the 100 kHz current
waveform is at zero. The CA inputs are both at program voltage VCP . VcPmax equates to the
max. overload peak 60Hz input current (17A) through R5· Therefore, during the switch "off" time, the maximum current through
R = (R1+Rn) is:
= VCPmax = I/NpkRS
IRimax
R
R
The upslope of the CA output is determined by the current through R1 charging Cpp:
max C4 Upslope = ~ /Rl = IINpkRS
CFP
CFPRI
Oscillator Ramp Slope = Vs /Ts = Vsfs
U-140
Equating the slopes and solving for CFP:
l1Np1cRs - - - Vsfs CFPR
c - _ln"r_...J,....R._s
(12)
FP YsfsR
Using the values from this example, and assuming R = lOK (R1=9K, RP2=1K):
C = 17x.025
85 F
FP 5xO.lxla6x lOK = p
The CA integrator gain may now be calculated and entered in the Bode plot:
G =
1
CA 21rfRCFP
187,000 (l3) f
The compensation circuit as designed so far (with Cn zero and CFZ open) has high loop gain and is very stable only when the inductor current is high, maintaining the power circuit zero near the position shown in Fig. 13, so that
its gain is flat at fc· At lower current levels, the
power circuit zero slides down to the right and
40
20 GAIN
0
dB
-20
P wer C rcult
Oln
CA Goin
P2
~
' ' ' ' \
' \ \ \
--'--I = 4A
\ \ \
-40
10 100 1k 10k 100k 1M
0 PHASE
J
-90
I
..,,...,,..... - --ILJ=24A
I I
i
-180
l;'----"-"
',,
I
i
Fig. 13 - Flyback Regulator Bode Plot
9-466
APPLICATION NOTE
the power circuit gain at/e has a -1 slope. With the -1 slope of the CA gain, the overall current loop gain has a slope of -2 at crossover, and will .ring excessively. It is necessary to add a pole-zero pair to the CA gain to reduce the
slope to -1 in the vicinity of fc. Offsetting the
integrator gain by a factor of 5, as shown in the Bode plot, provides a phase bump which increases the actual phase margin to 42°, a slightly underdamped condition (the Bode
approximation is 31 °, as shown).
The offset factor of 5 is provided by Cn = 4·CFP = 340pF. Cn and CFl' in parallel set the integrator gain at low frequencies to 37,CX'IJ/f.
The location of the flat portion of the CA gain characteristic is determined by RF- It is easiest to solve this graphically using the Bode plot. Ideally, Zl and Pl should bracket the crossover frequency. Simply slide the flat portion up and down between the integrator slopes until its gain is equal (but opposite in sign) to the power circuit gain at the same frequency as the center of the flat portion. That frequency is
the crossover frequency, fe· In Fig 13, the CA
gain in the flat portion is 10 (20dB). This is accomplished by:
RF = lOR = 10 (R1 +Rn) = lOOK (14)
The precise value of R, (and/c) is not at all critical. The phase bump is broad, and the loop response is really determined by the integrator
gain below fe (37,CX'/J/f).
Finally, an additional pole RnCn is placed at lOOkHz to filter out noise spikes. This pole frequency is too high to significantly affect phase margin at crossover.
Referring back to Fig. 11 - when the current loop is closed, the voltage across current sense resistor VRS equals the voltage across current programming resistor VRCP· Programmed with a current source le,., the current gain of the closed current loop is identical to Eq. 9:
G = lL le,,
PRs /Rs PRePfRe,,
Re,, (15) Rs
U-140
Just as in the previous examples, the closed loop current gain rolls off and assumes a single pole characteristic at the open loop crossover frequency, fs· The moving zero of the flyback power circuit is hidden within the inner current loop, and is invisible to the outer voltage control loop. In fact-regardless of the power circuit topology-with average current mode control, the external characteristics of the current loops are identical: flat gain, rolling off with a single pole characteristic above the open loop crossover frequency.
Example 4: Buck Regulator Input Current: The buck regulator is sometimes used in high power factor preregulator applications. It can only function when V0 is less than V,N, so the output bus voltage must be low. Normally, a low output voltage should be avoided, because the bus filter capacitor becomes large and expensive, but in applications such as telephone or battery charging this is not a problem and/or there is no choice. With 120V line input and 48 volt output bus, the input current will drop to zero for a substantial portion of each line cycle, each time the instantaneous line voltage goes below 48V. Third harmonic distortion will be 7 - 8% at low line, but the power factor of 0.99 is good enough for most applications.
Although the flyback topology might be used in the same low voltage output application, the buck topology operates with lower inductor current and lower peak current through the switch and rectifier. Peak voltages on the switch and rectifier are also much lower. But the flyback topology can provide line isolation in the preregulator by using a flyback transformer instead of simple inductor.
The buck circuit can be almost the same as the flyback circuit of Fig. 11, interchanging the inductor and the rectifier (cathode up).
The control loop design procedure is the same as for the flyback in Example 3. The buck regulator has the same left half-plane zero. In fact, the power circuit control-to-input gain equation is identical to Eq. 10 for the flyback circuit.
9-467
APPLICATION NOTE
Controlling Average Rectifier Current
Peak current mode control has been used with great success in conventional power supplies using buck-derived topologies. It works well because peak current mode control actually controls inductor current, and the inductor is located in the output of all buck topologies. When boost or flyback topologies are used, peak current mode control functions poorly, because the wrong current is controlled-the inductor current is not in the output. Although peak current mode control eliminates the inductor from the small-signal characteristic of the outer loop, the right half-plane zero present in boost and flyback outputs remains to plague outer loop compensation.
In boost or flyback circuits, the diode is in the output side, and ideally the diode current should be controlled, not inductor current. This is no problem for average current mode control. Its integrating current error amplifier can average the rectangular diode current waveform in the same way that it averages the switch current in the input of the buck or flyback preregulators discussed earlier. The right halfplane zero forces a lower current loop crossover frequency, but the RHP zero is "buried" within the current loop. The outer voltage control loop sees only a flat gain characteristic with a single pole roll-off at the crossover frequency-just the same as all the other topologies previously discussed. A flyback circuit using average current mode control is shown in Figure 14.
Yep
Fig. 14 - Flyback Output Cummt Control The circuit is almost identical to the flyback preregulator of Fig. 11, except output current
U-140
is sensed and controlled. The small-signal control-to-output gain of
the flyback current loop power circuit (from vCA at the CA output, to vRS, the voltage across Rs) is:
The same equation applies to controlling the output current of a boost circuit. Note the similarity with Eq. 10 for flyback or buck input current control. In Eq. 16, low frequency gain depends on J.jN rather than V0 , but more importantly, the inductor current IL has a minus sign, which represents 180° phase lag above the zero frequency. This is the characteristic of a right half-plane zero, and it makes the loop compensation much more difficult. It is usually necessary to cross over at a frequency one half to one fourth of the RHP zero frequency in order to cross .over with adequate phase margin. This results in lower closed loop bandwidth for the current loop than the previous examples. However, once this is accomplished, the RHP zero does not appear in the outer loop.
It is very important to make the inductance small to achieve the highest possible RHP zero frequency. Fortunately, average current mode control allows the mode boundary to be crossed. This permits a much smaller inductance than with peak current mode control, resulting in a much higher RHP zero frequency and higher crossover frequency.
Current Sensing
One important advantage of having a high gain current error amplifier is that it permits a very small current sense resistor value resulting in low power dissipation. The CA can make up for the gain lost with the small resistor.
In many applications, however, using a current sense resistor in the direct path of the current to be measured is not practical. The tiny Rs value may be difficult to implement, and the power dissipation in a practical sense
9-468
APPLICATION NOTE
resistor is too great. Often, the Rs circuit location is at a large potential difference from the control circuit. This is especially a concern when current must be sensed on the other side of the isolation boundary.
A current sense transformer (C.T.) can provide the necessary dielectric isolation and eliminate the need for an extreme low-value resistor. As shown in Fig. 15, this technique
ofl f l lsWlftlt
CA
~llf..----l[>I Rsl ,.
0
Fig. 15
works well for average current mode control when the current to be sensed and averaged is a pulse which returns to zero within each switching period-such as switch current (buck or flyback input current) or diode current (boost or flyback output current). Although "transformers can't couple DC", a C.T. does couple the entire instantaneous current waveform including its DC component if the core is reset to zero baseline each time the pulse goes to zero.
Total reset requires the same volt-seconds (of opposite sign) that were applied to "set" the core. At duty cycles approaching 1.0--which can occur temporarily with most topologies-the time available for reset may be only a tiny fraction of the switching period. Achieving total reset in a short time requires a large backswing of voltage across the C.T., so don't use low voltage diodes to couple the C.T. to Rs.
With a boost converter controlling input current in a high power factor preregulator application, a current sense resistor easily ties in directly with the control circuit, as shown in Fig. 6. Nevertheless, many designers would prefer to use a current transformer to minimize power loss and allow the use of a much higher Rs value. However, since the input current of a boost converter is the inductor current, the input current never goes to zero when operating in the continuous mode. Therefore, a C.T. can't be used to sense input current of a boost
U-140
converter because the DC value is lost, and the C.T. cannot reset-it will saturate. The same problem occurs in a buck regulator circuit, where the C.T. can't directly sense average output (inductor) current.
The answer to this problem is to use two C.T.s-one sensing switch current, the other sensing diode current. By summing their outputs as shown in Fig. 16, the true inductor current is reconstituted. Each C.T. has plenty of time to reset.
JJli~ll
oJ1J11~il====Rs._..,..C.A.O-----
Fig. 16
Using Current Sense Transformers: It is not difficult to achieve excellent results using low cost commercially available pulse transformers. A current sense "inductor" such as Pulse Engineering 51688 is a toroidal core wound with 200 secondary turns for a secondary inductance of 80 mH. A 0.18" hole is provided to slip the primary wire through.
The pulse voltage across the windings of a current transformer generates a magnetizing current which starts at zero and increases fairly linearly with time. The magnetizing current subtracts from the pulse current delivered to the secondary. Initially, the current through Rs is precisely lpRJ/N, but as time passes, the secondary current drops off more rapidly than it should. This effect is called "droop". It is usually not a problem if certain precautions are observed. The amount of current droop through the current sense resistor can be calculated:
(17)
where N is the turns ratio, Vs the voltage across the secondary, Ls the secondary inductance and .M is the max. pulse width. As the
9-469
APPLICATION NOTE
equation shows, droop· is minimized by maximizing secondary inductance-use the largest you can get. Don't use a large Rs value to obtain a large secondary voltage-its not necessary and makes reset more difficult. Make the turns ratio as low as possible by using two or three primary turns if space allows. Don't reduce the turns ratio by reducing the secondary turns-this is counter-productive because the inductance goes down with the turns squared.
For example, consider the flyback input current preregulator of Fig. 11, using a current transformer in series with switch instead of the 0.0250 sense resistor shown. Using the Pulse Engineering #51688 current sense inductor with one turn primary, the turns ratio is 1:200. Secondary inductance is 80 mH. The 24A max. overload pulse current becomes a 0.12A current pulse on the secondary side. A 100 sense resistor will have a max. voltage of 1.3V sent to the CA, and the max. secondary voltage including diode forward drop is 2.0V. The maximum pulse width is 7.02µsec.
Applying these values to Eq. 17:
IllPRI<"""'1>
=
200 1
2·0 sox10-3
7x10-6
= .035A
Only 35mA droop out of 24A isn't bad!
When two C.T.s are used-one on either side of isolation boundary-their turns ratios must be proportioned the same as the power transformer pri/sec turns ratio so that currents through
Rs will be equalized.
All of the equations containing Rs given earlier in this paper assume the sense resistor is measuring current directly. When using a current sense transformer, reflect the actual Rs on the C.T. secondary side into the primary by ~ubstituting RsNi/Ns·
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References:
[1) S.Hsu, A.Brown, L.Rensink, R.D.Middlebrook, "Modelling and Analysis of Switching DC-to-DC Converters in Constant Frequency Current Programmed Mode, "IEEE PESC Proceedings, 1979
[2] R.D.Middlebrook, "Topics in MultipleLoop Regulators and Current-Mode Programming," IEEE PESC Proceedings, June 1985
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD.· MERRIMACK, NH 00054 TEL. 603-424-2410· FAX603-424-3460
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APPLICATION NOTES
Resonant Fluorescent Lamp Converter Provides Efficient and Compact Solution
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Mark Jordan
Senior Design Engineer
John A. O'Connor
Applications Engineer
Unitrode Integrated Circuits
Merrimack, NH 03054
Abstract - This paper describes a zero voltage switched (ZVS) resonant con.verter for driving cold cathode fluorescent lamps. Primarily intended for liquid crystal display (LCD) back-lighting. the circuit features minimal component count and size. A specially designed integrated circuit provides all control functions for a current fed push-pull ZVS converter, and also contains an auxiliary pulse width modulated (PWM) controller to develop a programmable supply voltage for the LCD. Analysis and simulation of the converter, and a complete circuit schematic are presented. The analysis and simulation results are validated by experimental circuit waveforms and critical performance parameters.
Introduction
The proliferation of laptop and notebook computers places an ever increasing demand on display technology. High resolution and contrast are required to run today's graphics based programs, increasing the conflict between display performance, size and efficiency. The LCD with cold cathode fluorescent back lighting best satisfies this design requirement, however the lamp and its high voltage AC supply still remain the major contributor to battery drain.
The.cold cathode fluorescent lamp (CCFL) requires 1-2 kV to fire. Sine wave drive is preferred to minimize RF interference and maximize lamp efficiency over time. Converter efficiency and size are extremely critical. These formidable requirements demand a highly efficient conversion topology and maximum circuit integration.
A zero voltage switched resonant topology will maximize efficiency by eliminating losses associated with charging parasitic capacitances to high voltages. This topology can be controlled
using discrete circuitry. The most common implementation is a Royer oscillator modified to provide ZVS operation. While this at first appears to be a good solution, and is commonly used today, it suffers from several limitations.
High voltage DC to AC conversion is only part of the display supply. The average output current must be programmable for lamp intensity control, and the LCD requires a programmable low voltage supply for contrast adjustment. This additional circuitry, implemented discretely or with multiple ICs results in a large number of components, significantly impacting size and reliability. Synchronization is also preferred to eliminate beat frequency effects such as lamp intensity modulation, further complicating the design. Minimizing circuit complexity and bulk are best achieved through integration.
Cold Cathode Lamp Characteristics
The CCFL presents a highly nonlinear load to the converter as illustrated in fig. 1. ·initially when the lamp is cold (inoperative for some finite time), the voltage to fire the lamp is typically more than three times higher than the sustaining voltage. The lamp characterized in fig. 1 fires at 1600V and exhibits an average
sustaining voltage (Vi:J of 300V. Notice that the
lamp initially exhibits a positive resistance and then transitions to a negative resistance above lmA. These characteristics dictate a high output impedance (current source) drive to suppress the negative load resistance's effect and limit current during initial lamp firing. Since the ZVS converter has a low output impedance, an additional "lossless" series impedance such as a coupling capacitor must be added.
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APPLICATION NOTES
U-141
I
I
...
Q3
L1
""
·
COHTIIOL
j1
8uct&Dfl¥ie Vt
COLD CATHODE LAMP
~~·
PUlft.PullDftve
vz
~i··
1:N Tt
.,.
Fig. 1 Cold Cathode Lamp Current as a function of Voltage Vertical: 2mA/div. Horizontal: "JOOV/div.
To facilitate analysis, the equivalent CCFL circuit shown in figure 2 is used. VFL is the average lamp sustaining voltage over the operating range. The lamp impedance (Ri:t.) .is a complex function but can be considered a fixed negative resistance at the sustaining voltage. Stray lamp and interconnect capacitance are lumped together as CFL.
VII Cll
Fig. 2 CCFL equivalent circuit
ZVS Resonant Converter Topology
The current fed push-pull convertei: shown in fig. 3 is driven at it's resonant frequency to provide ZVS operation. The push-pull output MOSFE"IS (QI & Q2) are alternately driven at 50% duty cycle. Commutation occurs as VI and V2 resonate through zero thereby insuring zero voltage switching. This virtually eliminates switching losses associated with charging MOSFET output and stray capacitance, and reduces gate drive losses by minimizing gate charge.
Fig. 3 Current Fed Push-Pull ZVS Resonant Converter
Current is supplied to the push-pull stage by a buck regulator (Q3). The control circuitry forces the average voltage across the current sense resistor (RS+RS) and rectifier (02) to equal
a reference voltage. Adjusted RS varies the
current and the lamp's brightness. The nonlinearity introduced by 02 is insignificant since RS is adjusted for a particular brightness with no concern of the actual current level.
Winding inductance, La, and Ca, the combined effective capacitance of C7 and the reflected secondary capacitances make up the resonant tank. The secondary side of the transformer exhibits a symmetrical sine wave voltage varying from about 300V to ISOOV peak. Capacitor C6 provides ballasting and insures that the converter is only subjected to positive impedance. loadS.
Waveform Analysis
Simulated converter voltage and current waveforms are shown in fig. 4. At time to, the primary current (11 & 12) has reached it's peak value. The push-pull drain voltages (Vl & V2) have resonated to zero. The primary voltage (V3) has also resonated to zero, and through the control circuitry commutated QI off and Q2 on. The energy stored in LR is also at it's peak. This energy is transferred from LR to the effective
resonant capacitance (CJ during time to to t1,
causing CR's voltage to sinusoidally increase.
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APPLICATION NOTES
······ ······ ······ ······ ·····························ooOnoo.·······
2VP
------
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V2
,;; .. ·--:.,.:------:
11
.1: 11-
v:z 1:N '1
)
Tt · - - - - . , - - - - - - ...'
az
12
Cr
~
~ 1, I.
Fig. 4 Converter Voltage and Current Waveforms
At time tv all of the inductive energy in LR has transferred to CR, resulting in zero current through LR and maximum voltage acrpss CR. From time t1 to t2, the energy transfers from CR back to LR, decreasing CR's voltage while LR's current increases.
The resonant current through LR at time t2 is
equal and opposite to it's value at to. The
reflected load current flows during the MOSFET on time, and is observed as a slight current amplitude asymmetry. The voltages at Vl, V2, and V3 have resonated back to zero, causing the control circuitry to commutate Q2 off and Ql on. The cycle continues symmetrically during the ti through t4 interval, producing fully sinusoidal voltage and current waveforms.
Simplified Converter Model
The converter model shown in fig. 5, which is valid for one half cycle simplifies analysis by reflecting all impedances to the primary and eliminating the transformer. The differential voltage developed across the push-pull stage primary (Vl-V2) exhibits twice the voltage excursion as the center;tap (V3). This reflects Cl to V3 through the turns ratio squared; resulting in 4(C7) at V3. The secondary winding
Fig. 5 Simplified converter model
capacitance is also reflected by the square of the turns ratio (n). Reflected winding capacitance is usually significant due to the high turns ratios typically employed. The buck stage operates in continuous current mode and is synchronized to the push-pull stage.
Lamp current is proportional to lamp intensity, and is used as the feedback variable. Buck current (le) is the response variable, which in tum regulates the average push-pull primary voltage. The coupling capacitor's high impedance transforms the secondary voltage to lamp current.
Control Equations
Variable Summary:
CR = Effective resonant tank capacitance Cw = Secondary interwinding capacitance FL =Average lamp voltage le =Average Buck output current LR = Primary Winding Inductance n = Transformer turns ratio
z_ = Secondary impedance
Fig. 6 shows the buck output stage and forced output voltage wavefonn. The output voltage is a rectified sine wave, corresponding to the synchronous, resonant push-pull stage input
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APPLICATION NOTES
voltage. The inductor output configuration exhibits high impedance at the resonant frequency and averages the output voltage throughout the cycle. The buck output voltage as a function of time is:
V"'"(t) =VP sin(ca>t)
Where the angular frequency is:
(a) = 21t/ = -21t
2tl
Q3
L1
Vln~Tvo
I
01
Vo rm· Vp Buck1Drlve
T1
Fig. 6 Buck converter stage
The volts-second product across the inductor must be zero during steady state. Setting the on and off volt-second products equal and integrating gives the buck's transfer function:
-J.tl r1.. v dt
Jo LR
t ...
v dt LR
2:.Vi D
(1)
2
This transfer function is identical to the familiar DC output buck transfer function, with the rc/2 term accounting for peak versus average output voltage. As with the DC buck, primary voltage varies linearly with duty-cycle.
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The peak primary voltage is also related to peak lamp current by:
(2)
Setting (1) and (2) equal and solving for IFL (avg) expresses lamp current as a function of dutycycle:
2V
z_ IFL(avg)
=
DV.r
--
n-___!!
- - -1t -
(3)
As expected from fig. 5, the lamp sustaining voltage, VFL introduces a nonlinearity.
Buck output current is related to lamp current be equating input and output powers. The input power is:
P lll{Jfd
=
!tJPdt
= - 1- ("12 I V sin(t)dt 1t/2 Jo P
The power to the load is:
For analytical purpose, 100% power transfer is assumed:
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.tYI0+20V
+
··········································································.
+1Vto+20Y
+
>
'U
'rU
8
0 z z
m $
CCFL
~
. VREF
....
··
':' Tl (1.prl,...,.·10utl)
.
"'
':'
.......,
~-~· ~ FLYIACK DRI~
___r."'1
·;... ' ......... ·.....
NHANNEL ·
-!- ~
.. .............................................:....:
':'
Fig. 7 UC3871 Application circuit
A
·11Ylo·l4Y
...... rConlrut
LCDIUPPLY
':'
c: .!..
~
APPLICATION NOTES
(4)
Substituting (2) for Vp in (4) gives the buck output current as a function of lamp current:
nVFL
v 1. = - - - - - -
z + FL
(S)
sec 1t IFU..GY6>
The resonant frequency is approximately:
J R " " -1- - -
(6)
21tJLRCR
The nonlinearity introduced by VFL causes the resonant frequency to vary with load. At very low lamp intensity the secondary voltage barely crests above VFL. The effective resonant capacitance, CR> is primarily the sum of C7 and Cw reflected to the primary. As the secondary voltage increase above VFtJ the reflected C6 value adds to the resonant capacitance, decreasing the frequency. The frequency range is approximated by assuming C6 has negligible effect at minimum lamp intensity, and fully adds to CR at maximum intensity.
The peak resonant inductor current is the sum of the reflected load current from (5) and the resonant current:
(7)
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Although relatively large currents are circulated through the resonant tank, the switches operate at low current levels. This is a direct result of the continuous resonant topology; the switches only must handle the energy that is removed by the load and lost in parasitics. The peak switch current is:
(9)
The UC3871 A Completely integrated Solution
a Fig. 7 shows complete application circuit
using the UC3871 Synchronous Resonant
Fluorescent lamp and LCD driver. The IC
provides all drive, control and housekeeping
functions to implement CCFL and LCD
converters. The buck output voltage (transformer
center-tap) provides the zero crossing and
synchronization signal. The LCD supply
modulator is also synchronized to the resonant
tank.
.
The buck modulator drives a P-channel
MOSFET directly, and operates over a 0-lOOo/o
duty-cycle range. The modulation range includes
100%, allowing operation with minimal
headroom. The LCD supply modulator also
directly drives a P-channel MOSFET, but it's
duty-cycle is limited to 95% to prevent flyback
supply foldback.
The tank impedance is detennined by setting the resonant energy storage tenns equal:
Solving for VR/IR gives the tank impedance:
(8)
Fig. 8 UC3871 Oscillator Block Diagram
The Oscillator and synchronization circuitry are shown in fig. 8. The oscillator is designed to synchronize over a 3:1 frequency range. In an actual application however, the frequency range is only about 1.5:1. A zero detect comparator senses the primary center-tap voltage, generating
9-476
APPLICATION NOTES
a synchronization pulse when the resonant waveform falls to zero. The actual threshold is 0.5 volts, providing a small amount of anticipation to offset propagation delay.
The synchronization pulse width is the time that the 4mA current sink takes to discharge the timing capacitor to 0.1 volts. This pulse width sets the LCD supply modulator minimum off time, and also limits the minimum linear control range of the buck modulator. The 200µA current source charges the capacitor to a maximum of 3 volts. A comparator blanks the zero detect signal until the capacitor voltage exceeds 1 volt, preventing multiple synchronization pulse generation and setting the·maximum frequency. If the capacitor voltage reaches 3 volts (a zero detection has not occurred) an internal clock pulse is generated to limit the minimum frequency.
A unique protection feature incorporated in the UC3871 is the Open Lamp Detect circuit. An open lamp interrupts the current feedback loop and causes very high secondary voltage. Operation in this mode will usually breakdown the transformer's insulation, causing permanent damage to the converter. The open lamp detect circuit~ shown in fig. 9 senses the lamp 'current feedback signal at the error amplifiers input, and shuts down the outputs if insufficient signal is present. Soft-start circuitry limits initial tum-on currents and blanks the open lamp detect signal.
;····················.
lo··Op911U-. I DINbM OutpulllJ
Open Ump o.t8cl
'· · · · · · · · · · · · · · · - · · · · ·'
Fig. 9 Open Lamp Detect Circuit
Other features are included to mmmuze external circuitry requirements. A logic level enable pin shuts down the IC, allowing direct connection to the battery. During shut-down, the IC typically draws less than lOOnA. The UC3871, operating from 4.5V to 20V, is compatible with almost all battery voltages used in portable computers. Under-voltage lockout circuitry
U-141
disables operation until sufficient supply voltage is available, and a 1% voltage reference insures accurate operation. Both inputs to the LCD supply error amplifier are uncommitted, allowing positive or negative supply loop closure without additional circuitry. The LCD supply modulator also incorporates cycle-by-cycle current limiting for added protection.
Application Circuit Example
The application circuit shown in fig.7 resonates at approximately SOkhz. This frequency allow a reasonable compromise between size and efficiency. This relatively low frequency by today's standards results from high voltage insulation and spacing requirements, and practical limitations in reducing stray and interwinding capacitance. The half wave current sense signal is sensed by Error Amp 1 and averaged by integral compensation. The range of current control is 500µA to lOmA.
A flyback converter generates the LCD supply, outputting -12V to -24V to bias monochrome LCDs. Color displays normally require a positive bias voltage. Since this voltage typically must also be stepped up, a coupled inductor flyback is normally used.
Actual circuit waveform5 agree with the spice simulated waveforms in fig. 4. Distortion caused by lamp nonlinearity is dearly visible at the operating extremes. At more nominal levels, the waveforms are more ideal, with only a small amount of observable distortion.
All of the following waveforms were taken at minimum and maximum lamp intensity to indicate .worst case conditions. Nominal measured efficiency was 80%. Further improvement is possible with lower resistance magnetics and lower on resistance MOSFETs. Fig. 10 shows secondary output voltage, fig 11 shows lamp voltage, and fig. 12 shows lamp current. Notice that the lamp voltage is fairly constant .with widely varying current. A frequency shift from about 48kHz to 57kHz is also observed over the lamp intensity range. The lamp current exhibits additional harmonics induced by it's nonlinearity. Push-pull MOSFET drain to source voltage is shown in fig. 13, and drain current is shown in fig. 14. The transformer center-tap voltage (buck output) is shown in fig. 15. All waveforms are sinusoidal, exhibiting minimal harmonic content.
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APPLICATION NOTES
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Fig. 10 Semndary output voltage Vertical: SOOV/div. Horizontal: Sµs/div.
Fig. 13 Push-Pull MOSFET drain to source voltage Vertical: lOV/div. Horizontal: Sµs/div.
Fig. 11 lamp voltage Vertical: 200V /div. Horizontal: Sµs/div.
Fig. 14 Push-pull MOSFET drain current Vertical: 200mA/div. Horizontal: Sµs/div.
f
.1
Fig. 12 Lamp current Vertical: lOmA/div. Horizontal: Sµs/div.
SOOµA/div.
Summary
The current fed push-pull ZVS converter efficiently develops high voltage, sinusoidal power for driving cold cathode fluorescent lamps. Design
Fig. 15 Buck output voltage Vertical: 200mA/div. Horizontal: Sµs/div.
equations have been derived, and verified experimentally, simplifying application circuit design and analysis. The UC3871 provides a complete solution for high performance back-light and LCD power supplies.
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VOLTAGE-MODE CONTROL REVISITED A NEW HIGH-FREQUENCY CONTROLLER FEATURES
EFFICIENT OFF-LINE PERFORMANCE
by
Robert A. Mammano, V.P. Adv. Tech. Unitrode Integrated Circuits Corp. Merrimack, NH
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ABSTRACT
With modern day emphasis on advanced power supply topologies, the advantages of voltagemode control have been neglected. A new control IC optimizing this topology for highfrequency, off-line applications brings voltage-mode control into the modern era and combines the efficiencies and high frequency performance of a BiCMOS design with a noise resistant, low-cost circuit solution.
INIRODUCTION
With all the interest in advanced power control topologies such as peak and average currentmode, resonant and quasi-resonant approaches, soft switching and phase shift control, it is easy to lose sight of the fact that "old-fashioned" voltage-mode still has a lot to offer. Specifically, in applications where control is needed over wide variations in line and load, the use of voltagemode control will maintain stable, noise-free performance over a wider range of operating conditions than any other circuit topology. When more recent circuit enhancements such as voltage feed-forward, programmable duty-cycle clamping, fast current limiting, and low-power BiCMOS processing are included, a very effective and yet easy-to-use power control component is the result.
LIMITATIONS OF CURRENT-MODE CONTROL
With the introduction of current-mode control back in 1983, several important performance enhancements were featured, including:
* Instant response to line variations * Inherent pulse-by-pulse current limiting
* Faster loop response
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APPLICATION NOTE
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While these characteristics were quite significant compared to the technology of the day in 1983, more recent developments have shown that current-mode control is not the only way of achieving them. Specifically, voltage feed-forward can be added to voltage-mode circuits to accomplish the same instant response to line voltage, and the fast current feedback loop necessary for effective current limiting of current-mode circuits is equally applicable to voltage mode. While current-mode does minimize the effect of the output filter inductance - a characteristic which can be used to improve overall gain bandwidth - increasing the switching frequency can push the output filter resonant frequency to the point where excellent response can still be achieved, even with a two-pole output filter.
Before discussing the positive aspects of voltage-mode control, it is worth spending a little more time on current-mode. Although the past 10 years have seen many highly successful designs which have utilized peak current-mode topologies, few would argue with the contention that the design process is more complex. For example, some of the design considerations which are unique to peak current- mode control are:
* Dealing with the leading-edge current spike usually
present on the current ramp waveform.
* Dealing with additional noise or ringing on the current
waveform when the power switch turns off.
* Adding the appropriate amount of slope compensation for
stable operation.
* Analyzing circuit performance with two feedback loops.
* Providing good regulation with multiple outputs.
* Obtaining an adequate amplitude ramp waveform for stable
pulse-width modulation at light load and minimum input voltage.
Although solutions can and have been found for all the above issues, they do not come without a good deal of difficulty, and since none of them apply to voltage-mode control, there is a growing incentive to readdress this topology.
VOLT AGE-MODE REYISITED
The typical voltage-mode circuit will use a fixed-frequency, constant-amplitude ramp waveform to compare against the output from an error amplifier. As the error amp's output moves up and down the ramp, a corresponding change is made to the power switch's on- time. With a largeamplitude ramp waveform which is disassociated from the supply's power stages, noise-free pulse-width modulation is much more readily achievable. The traditional problem with this form of control is that a change in the input voltage must go through the output filter, be sensed as an error at the output, and be fed back to change the modulation and provide a correction.
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APPLICATION NOTE
U-142
Current-mode control bypasses this process as a change of input voltage is directly impressed across the output inductor, which immediately changes the slope of inductor current, and since this is the ramp which controls the PWM, response within one switching period is achieved.
The same result can be achieved with voltage-mode control, however, by making the slope of the oscillator-derived ramp proportional to input voltage. This is voltage feed-forward which means input variations are fed directly to the modulator, bypassing the output filter and the error amplifier. In addition to providing instant response, the input voltage term is canceled from the forward transfer function, resulting in constant gain and a simpler feedback compensation problem. Since the voltage ramp waveform is typically derived from the timing oscillator, the trick is to provide this variable slope while maintaining a constant switching frequency. Another feature which is ·highly desirable, and often implemented in this same section of the control circuitry is the ability to limit the maximum switch duty-cycle to insure non- saturation of the magnetic components of the power supply. The combination of all these features was a major goal in the development of a new voltage-mode control integrated circuit - the UCC3570.
INTRODUCING THE UCC3570
The objective in the design of the UCC3570 was to develop an easy- to-use controller, optimized for low~power off-line applications, free of the noise and stability issues of current-mode control, but allowing equal or better power supply performance to be achieved. An important technique in achieving this objective was the utilization of a BiCMOS manufacturing process which offered high speed circuitry with low internal current consumption and small overall die size. This last characteristic has allowed the full- featured UCC3570 to be offered in the 14-pin small outline, surface mount package.
The overall block diagram of the UCC3570 is shown in Figure 1. Remembering again that this device is optimized for low-power, off- line applications, it can be seen from Figure 1 that the basic architecture includes the following features in addition to voltage feed-forward:
* A fixed-frequency pulse-width modulator
* Provisions for low-current off-line startup
* A single high-current totem pole output driver
* Unique voltage and current fault protection
Other performance features which have been included in this design include programmable deadband control, soft-start turn on, highspeed current limiting, latched shutdown capability, a synchronizable oscillator, and the availability of a five-volt bias source. A voltage error amplifier is not included as off-line power supplies almost always require isolation and the optimum location for the error amplifier is on the secondary side of the isolation boundary. Here the feedback gain can be incorporated with voltage sensing and the system reference in an IC such as the UC39431 which combines these functions with an optimum drive circuit for an
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APPLICATION NOTE
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optocoupler. Figure 2 illustrates the use of this device with the opto as an ideal means of providing an isolated feedback signal to the primary side UCC3570.
The following discussion will provide a better understanding of the unique features of the UCC3570.
RAMP GENERATION CIRCUITRY
The ramp generation portion of the UCC3570, which is shown in Figure 3, actually performs several circuit functions. The ramp waveform is formed on an external capacitor which is charged with a current source proportional to the input line voltage and discharged with a usersetable constant current sink. The circuit is clocked from a constant-frequency, separate oscillator which, in turn, can be either free running or externally synchronized. Switching between the charging and discharging currents is accomplished by a flip-flop which is set with the constant- frequency clock signal, and reset when the ramp reaches four volts. To accomplish a constant ramp amplitude, the bottom of the ramp is held at one volt while awaiting the clock command to start the next charge cycle. The logic is defined such that an output drive pulse can only occur during the rising portion of the ramp waveform and is held off for both the fall time and any wait time prior to the start of the next switching period.
This operation can be visualized with the aid of Figure 4 which shows the three regions in the ramp waveform: the variable rise time, the programmed constant fall time, and the wait time which is the remainder of the constant overall switching period. Figure 5 shows the effect of changing operating conditions on the ramp waveform. With the assumption of a constant feedback voltage, a high line voltage yields a fast rise time arid a narrow output pulse, while a low line voltage reduces the rise time to produce a wider output pulse. The relationship is linear so that the result is a constant volt-second product to the power transformer, regardless of input voltage. If the fall time is. set to. provide a minimum output deadtime at the minimum input voltage - as in Figure 5B - a higher voltage will increase the minimum deadtime - as in Figure 5A. If the input voltage should fall below the expected minimum such that the ramp has not reached l V by the end of the period, then the ramp will miss the clock signal and remain reset with the output off for the entire next period - as shown in Figure 5C.
Note that the ramp discharge current is determined by external current-setting resistor R4. In addition to the output deadtime, this resistor also programs the currents for the timing oscillator, the soft-start, and fault shutdown circuits.
One last function contained within the ramp circuitry is that the Vfwd terminal which monitors the input line voltage to control the ramp up-slope has boundary limits established by a pair of shutdown comparators which define a 4: 1 operating range. Should the voltage at this pin rise above 4V, or fall below IV, the PWM output will be forced off. More about this feature in the Fault Protection section.
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APPLICATION NOTE
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START-UP FEATURES
The features in the UCC3570 associated with startup and shutdown are shown in Figure 6. Npte ~hat there are two terminals which are connected (through an impedance) to the high voltage DC bus, Vin, and both contain voltage monitoring functions. Vfwd measures the bus voltage directly through divider Rl/R2 and, with no capacitance, this pin will respond instantly to line voltage changes. The Vee pin, on the other hand, responds to line voltage changes with a delay caused by the Cl/RS time constant. Since the voltage at both pins must be above minimum for operation, the usual process is that tum on is initiated by the voltage at Vee while turn off is triggered by a falling voltage at Vfwd. The tum on sequence should proceed as follows:
1. Vfwd rises above 1.0V. Ice will be less than lOOuA. 2. Vee rises above 13V and activates the internal reference. At this point, Ice will
increase to approximately lmA plus any loads on the reference. 3. When Vref rises above 4.5V, the Soft-start clamp is released and as the voltage on Cs
rises, the output will start switching with increasing pulse-widths. With the onset of switching, Ice will rise to a value determined by the power switch gate charge requirements and the switching frequency.
As Ice increases, Vee will probably fall but with 5V of hysteresis, significant energy may be drawn from Cl before tum off is initiated by the UVLO comparator. If this should occur, the circuit is reset, reducing Ice back to 80uA, and thus allow another attempt to start.
FAULT PROTECTION
The circuitry within the UCC3570 associated with fault protection is shown in Figure 7. The potential faults which have been considered and provided for include the following:
* Over and under voltage on the input line.
* Excessive load current of a temporary nature.
* A continuous overload or shorted output.
In addition, there are several ports where a shutdown command may be inserted, either directly or through an optical coupler from load-related faults.
Note from Figure 7 that there are four inputs to the PWM-stop OR gate, any one of which will immediately terminate output pulses and hold them off for as long as that signal is high. Three of these come from the line over- and under-voltage comparators and the current limit comparator and provide for pulse-by-pulse shutdown. The fourth comes from a shutdown latch which provides for a permanent shutdown until reset by a low signal from either Vfwd or Vee. These two pins allow several operating options. By appropriately selecting the source impedance to Vee, the circuit can be made to permanently latch off or automatically restart depending on whether the load with no bootstrap energy will pull the voltage on Vee below its
9-483
APPLICATION NOTE
U-142
low threshold. If Vee falls below 9V, the shutdown latch will reset and the circuit will restart. If it does not, reset must come from Vin, either by temporally removing input power or by momentarily pulling Vfwd low.
Setting the shutdown latch also can come from two sources. If the current limit pin sees a level of 0.6V (as distinguished from the pulse-by-pulse threshold of 0.2V) the latch will be set. In addition, every time the 0.2V level is exceeded, an increment of current will be delivered to the Count pin. This current will be integrated by means of the external capacitor, Cf, and when the voltage exceeds 4V, the shutdown latch will also be set providing for a delayed shutdown with user selectable time constants. Note that any time .the shutdown latch is set, the soft-start capacitor is discharged providing for a controlled restart.
A 50-WATT FLYBACK EXAMPLE
Figure 8 is the schematic for a l2V, 4A supply capable of operating from an 85 Vrms to 265 Vrms power line. This circuit incorporates all the protective features described and is most noteworthy by the minimum number of active devices needed. With a switching frequency of 100 kHz, the efficiency is close to 90% over the full line voltage range, allowing the circuit to be packaged in a very small module with minimal heat sinking requirements. A contributor to the high efficiency is allowing the duty-cycle to extend to 60% with the assurance of an absolute clamp at that level. Automatic restart after a shutdown is provided with a time constant of approximately 25 msec defined by the value of the soft-start capacitor, and the delayed shutdown is set to accept 5000 over- current pulses before activation. (approximately 60 msec)
The transformer consists of a total of 79 turns on a EI375 core with a 36 mil gap. The 1.2 cu in size of this design was greatly aided by the fact that a minimum of 4 usec of reset time is assured, allowing maximum utilization of the core. With a 12V output, the rectifiers allow as little as 5% reset voltage under short circuit conditions which would normally let the transformer ratchet up to saturation, a problem which the shutdown latch effectively alleviates.
SUMMARY
While the modern power supply designer today has innumerable choices available from which to select the configuration and the components to satisfy his requirements, .the combination of efficient operation, simple control algorthym, high level of protection, ease of programmability, and low cost all point to the UCC3570 as the controller of choice for for a broad range of offline power requirements.
Acknowledgement: This Application Note was originally presented in a paper at the 1993 High Frequency Power Conference sponsored by INTERTEC Communications and was published in the Conference Proceedings.
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-UNITRCDE Design Note
DN-19
A SIMPLE ISOLATION AMPLIFIER USING THE UC1901
The UC1901 Isolated Feedback Generator has other applications besides providing isolated feedback in switching power supplies. This IC's amplitude modulation system and error amplifier can be used to implement a very low cost, high bandwidth, isolation amplifier. Isolation amplifiers of this type find use in switching power supplies, motor controls, instrumentation, industrial controls and medical systems.
The UC1901 generates a programmable high frequency carrier signal (up to 5MHz) with an amplitude that is controlled by a high gain error amplifier. In a typical feedback application, this amplifier and modulator are used, in conjunction with the UC1901 's 1.5\/ reference and a small signal coupling transformer, to provide precision regulation for an isolated switching power supply. Capacitively coupled feedback around the UC1901 error amplifier determines the device's small signal AC response, but the DC operating point is determined by the requirements of the overall power supply loop. By adding an additional winding on the coupling transformer and a demodulator circuit for this winding, local DC feedback can be provided to the UC1901 's error amplifier. In this mode very accurate DC, as well as small signal, AC, transfer functions can be established across the Isolation boundary.
The configuration of an isolation amplifier using the UC1901 is shown In the figure below. The drivers on the
UC1901 couple an amplitude modulated carrier to two matched windings fY'l2. and W3 ) on a small signal transformer. The demodulated signal from winding W2 Is
used to provide feedback to the UC1901 's error amplifier while the demodulated signal from W3 is the Isolated output signal. The use of the feedback winding linearizes the transfer function of the overall amplifier and allows DC signals to be accurately transferred. Matching of the two demodulator windings and demodulator circuits Is important to maximize linearity and minimize DC offsets. An optional output buffer and filter will reduce residual carrier ripple and Isolate the output demodulator from its load. The internal gain compensation on the UC1901 is sufficient for stable operation with overall gains down to 12dB. This circuit requires a supply voltage to the UC1901 that, if not available In the system already, can be generated using a second slmiiar circuit operating in the reverse direction.
The primary features of this circuit are:
1. Good Signal Linearity
2. Wide Bandwidth (3dB Bandwidths > 500kHz)
3. High Isolation Capability
4. Low Cost
10 II
1 Eu· .... ~.1
··
(!Ok)
vi,soouL/oTN/
I
IUF/El
FILTER
.,...... v.
CI
Eur
hn. 11·11
TU -..--
A Low Cost, High Bandwidth, lsolatlon Amplifier: An additional feedback winding linearizes the transfer func-
tion of the ampllfler by matching the coupllng characteristics to the Isolated output.
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DN-26
-UNITRDDE Design Note
UC3842A LOW COST START-UP AND FAULT PROTECTION
CIRCUIT
Thia circuit optimizes control circuit performance to Include:
· Low Start-up Current, Lesa Than 0.5 ma
· MOSFET Compatible Undeivoltage Lockout
Threaholda 16V Turn-on, 1ov Turn-on
· Programmable Restart Delay HICCUP Fault Protection
· Auxlllary 5V Precision Reference
· Oveivoltage/Overtemperature Protection
Initiates a clock cycle and the PWM output at pin 6 goes high. This is fed to transistor C1 which pulls the RtlCt input at pin 4 low, thus ''freezing· the oscillator, while keeping the PWM output high. Once a valid fault (greater than 1 volt) Is received at the current sense Input (pin 3), the output at pin 6 will go low. Transistor C1 Is then turned off, and the oscillator generates an o1f period, or delay as programmed by the Rt/Ct componenls. This procedure wiH repeat as often as dictated by the fault conditions, but significantly reduces the average short circuit currents and power dissipation.
CIRCUIT DESCRIPTION AND OPERATION:
The UC3842A Controller is featured in this design NOT as the power supply control IC, but In a supervisory function to assist the principal PWM. It will be utilized to facilitate a low current start-up of less than 0.5 milliamp from the high voltage bulk supply. Addlllonally, the UC3842A features 16 volt tum-on and 10 volt tum-off thresholds, Ideally suited for power mesfet gate drive circuits. The 1 amp output of .the UC3842A is used to switch the auxiliary supply voltage to the principal PWM controller, a UC3825 or UC3846 for example.
The oscillator of the UC3842A is configured to generate a constant off time, corresponding to the desired restart delay Interval. At the beginning of Its operation, the UV
The UC3842A'.s current sense node is used as the fault Input, and can be configured to provide numerous safeguards. Primary overvoltage protection Is accomplished by using a simple resistor divider network or series string of zener diodes to the high voltage rall. Overtemperature protection is possible by Including the UC3730 Precision Thermal Monitor IC, or a variable Impedance thermistor. In a simple configuration, the fault circuit is designed to dellver a 1 volt Input to pin 3 of the UC3842A when a fault response is necessary. The error amplifier can also be biased to accept lower amplitudes of valid fault inpuls at the current sense Input. A precision five volt auxiliary supply is made available at the IC's reference output, pin 8 and can supply 20 mllliamps maximum.
UC3842A Supervisory Function Circuits
LOW COST START-UP and FAULT PROTECTION CIRCUIT
I STAIT +HIC >----<,__'l/V'lrl,__------------k~-----< IDOTSTIAP
Tl !--------~ PIR
II
SET
fu
Fii
: Ill
u
u
llDFIU
·lflC >-----<,___ ___.,___ _ _ _ _ _ ___.._ _ __._ _ _ _ _.._
9-486
Design Note
COMBINED LATCH/RESET/HICCUP FUNCTIONS General Circuit
. ,_________.._ ,"
DN-26
OVER·TEMPERATURE PROTECTION
using 50 to 1000 thermocouples
FAULT llPIT
UC
3842A
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Design Note
DN-27
UC1842/UC1842A FAMILY SUMMARY OF FUNCTIONAL DIFFERENCES
The industry standard series of UC1842/43/44/45 devices has been improved for higher frequency, off-line power supplies. This new "A" series of controllers,
UC1842A/43N44N45A, feature three major advantages over their predecessors as shown in the summary below.
Start Up Current
Typical (TJ = 2s°C)
= Maximum (TJ 2s°C)
UC1842/45 0.5ma 1.0ma
UC1842A/45A 0.3ma 0.5ma
Oscillator Discharge Current
= At TJ 2s·cJ.mAJ_
Overtemp. Range
UC1842/45
MIN TYP MAX
7
10 13
6 -
14
UC1842A/45A
MIN TYP MAX
7.8 8.3 8.8
7.5 -
8.8
Output Saturation DuringUVLO
UC1842/45 1V@0.2ma
UC1842/45A 1V@10ma
The reduced start-up current is of particular concern in offline supplies where the IC is "powered-up" from the high voltage DC rail, then bootstrapped to an auxiliary winding on the main transformer. Power is then dissipated in the start-up resistor which is sized by the IC's start-up current. Lowering this by 50% in the "A" version family will reduce the resistors power loss by the same percentage.
Precision operation at high frequencies with an accurate maximum duty cycle can now be obtained with the "A"
family of devices due to its trimmed oscillator discharge current. This nullifies the effects of production variations in the initial discharge current or deadtime.
Another significant improvement has been made in the output section, specifically to the lower totem-pole transistor's operation during undervoltage lockout. The "A" series of devices prevent the power MOSFETs from parasitically turning-on at powerup due to the "Miller" effect. This new technique allows the IC to sink higher currents at lower saturation voltages than it's predecessors.
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DN-28
UC3840/UC3841/UC3851 PWM CONTROLLERS SUMMARY OF FUNCTIONS AND DIFFERENCES
The UC3840/UC3841 and UC3851 PWM controllers incorporate numerous protection features for switch mode power supplies. The list includes programmable undervoltage lockout thresholds, programmable current limit thresholds, overvoltage protection, soft-start and external stop/reset capability. While these controllers are similar in concept, there are subtle differences amongst
them in the operation of the error latch circuitry, specifically, the external stop and reset inputs. The UC3841 and UC3851 ICs feature an improved circuit design which simplifies the interface to the internal protection circuitry. A summary of the functions and modes of operation is listed below.
EXTERNAL STOP
Low~O.~
H_!g_h Open Cap.toGND D u r l ' ! i _ Power-~
RESET
H_!g_h_{_>3.m Low(<2.8V)
UC3840 St~
Normal Normal
Not Recommended
UC3840 Latch
Requires UV Cycle to Reset
UC3841/51
Defeat E/L O_[l_eration
StQ!!. Normal
Delay E/L Operation at· 13msec:M::_ E/L= Error Latch
UC3841/51 Latch
Reset
SOFT START After UV or Reset
UC3840 Unlatched
The UC3851 controller incorporates two additional features, a toggle flip-flop for an accurate 50% maximum duty cycle clamp, and a 1 amp peak totem-pole output for
driving power MOSFETs. Maximum duty cycles and output configurations for each device is shown below.
= MAXIMUM DUTY CYCLE (TJ 25°C)
I
I
UC3840/41
UC3851 0-46%
PWMOUTPUT 1A
UC3840/41
UC3851
0 en Collector Active Low Totem Pole Active Hi h
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DN-29
UC3842A FAMILY FREQUENCY FOLDBACK TECHNIQUE PROVIDES PROTECTION
Excessive power dissipation in switching devices can occur during start-up and overload conditions In many swltchmode power supplies. Many sophisticated PWM controllers provide the means for protection against these conditions; however, simple low-cost controllers will require additional circuitry. The circuit described below utilizes only one additional resistor and transistor to enhance the performance of the UC3842A family of controllers.
The power supply output voltage is fed to the error amplifier inverting input {pin 2) at a 2.5 volt amplitude under normal operating conditions. During start-up or overload,
however, this voltage can drop to zero. The circuit shown uses this feedback voltage to divert normal charging current from the IC's timing capacitor to ground whenever the feedback voltage is below the 2.5 volt nominal. A linear three-to-one reduction of oscillator frequency is obtainable for most applications. This technique lengthens the potential maximum on-time and reduces the programmed deadtime. In many circuits, however, the peak current limit threshold is reached early In the cycle under these overload conditions, and this Is not a problem. For most applications, the foldback resistor value {RF) should equal that of the timing resistor (RT).
EXAMPLE:
= = = = 100 kHz operation, RT 15k, Cr 1 nF, RF 15k, Q1 2N2907A
OPERATING MODE VEIA·_.m!n~
Oscillator Freq.
NORMAL 2.50V 105 kHz
OVERLOAD
o.oov
36kHz
FREQUENCY FOLDBACK TECHNIQUE CIRCUIT
UC
3842A
1.sv tu teal
OSCILLATOR FREQUENCY
TO 0IT f , _ _. . . . . . .~\I\/\,__
z.u
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DN-30
PROGRAMMABLE ELECTRONIC CIRCUIT BREAKER
The design of a programmable electronic circuit breaker is shown below which utilizes the UC3843A control IC to facilitate a high speed turn-off following an overcurrent condition. This low cost, industry standard IC contains the required protection features and drive capability in a single 8 pin device.
CIRCUIT OPERATION
Power to the controller is provided by a simple, low cost 60Hz transformer from the AC line which delivers 12 VAC at the secondary. The output current is determined primarily by the relay used with an additional 1O mllliamps, or so, drawn by the IC. Undervoltage lockout prevents any operation until 10 VDC is obtained across capacitor C1, when the UC3843A will turn on. The PWM
output at pin 6 goes high which drives the relay ON and switches the load across its respective power source. The load current is sensed by the current transformer T2, multiplied by its turns ration(N) and develops a voltage across the sense resistor R4. This resistor is scaled to delivery 1 volt maximum at the full load current and is one input to the PWM comparalDr.
While the output at pin six is high transistor Q1 is also turned ON which disables the ICs oscillator, locking the output high until IDggles by the PWM. A 1Ok resistor (R5) to the supply voltage (pin 7) supplies bias to Q1 after the output has gone low, providing a latched OFF condition. This can easily be reset by pulling Q1 's gate low through 1k ohms ID ground as shown.
SCHEMATIC DIAGRAM ELECTRONIC CIRCUIT BREAKER FEATURES HIGH SPEED CURRENT LIMITING
Jll
110 YAC PR!
12 VAC SEC.
":
RI .......
R2
2 UC 3843A
R3
Cl ": R4
SFOELi EfYf
MAXUUR
PRO&RAMMABLE CURREIT ADJUST
APPROX 15YDC 5¥
......
RESET
12 YDC TO AC
~
"'-.
LllE
The other input to the PWM comparator Is represented by the vonage at pin 1, the error amplltler output .which can be adjusted by resistor R2. Internally, this voHage Is reduced by two diode drops then attenuated to onethird Its amplitude. The PWM circuitry compares this voHage wHh that of the current sense Input at pin 3. When the current sense input exceeds the threshold set by resistor R2, the comparator Is trtpped and the ouptput at pin 6 Is latched OFF.
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DN-31
-UNITROCE Design Note
CURRENT MODE CONTROLLED QUASI-RESONANT ZERO VOLTAGE SWITCHING POWER CONVERSION
Variable frequency power converters can also benefit from the use of current mode control. Two loops are used to determine the precise switch ON time, an "outer" voltage feedback loop, and an "inner" current sensing loop. The advantage to this approach is making the power stage operate as a voltage controlled current source. This eliminates the two pole output inductor characteristics in addition to providing enhanced dynamic transient response.
PRINCIPLES OF OPERATION
Two control ICs are utilized in this design example. The UC3843A PWM performs the current mode control by providing an output pulse width determined by the two control loop inputs. This pulse width, or repetition rate is
used to set the conversion period of the UC3864 ~S resonant controller. Rather than utilize its voltage controlled oscillator (VCO) to generate the conversion period, it is determined by the UC3843A output pulse width.
Zero voltage switching is performed by the UC3864 oneshot timer and zero crossing detection circuitry in their standard configuration. When the resonant capacitor voltage crosses zero, the UC3864 output goes high. This turns ON transistor 01 and recycles the UC3843A which initiates the next current mode controlled period. The UC3864 error amplifier and VCO are not used, however the fault protection circuitry will still respond to an overcurrent fault.
CURRENT MODE CONTROLLED ZVS FORWARD CONVERTER
VARIABLE FREQUENCY OPERATION
UC3864 ZERO
VOLTAGE SWITCHING
II
I
l
ll
UC3864
OUTS
-l
UC3843 ,.__..,..__ __, I SE IS EI A
OUT
ZERO
FLT
vco
SY
-l
RC
l
UC3843: CURREil MODE CDITROLLED
ON-TIME
~
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DN-32
OPTOCOUPLER FEEDBACK DRIVE TECHNIQUES
The use of optocouplers in the feedback path of switchmode power supplies is probably one of the most common practices in the industry. Benefits of this method include low component cost, high voltage isolation and simplicity of design and implementation. Although adequate for many existing designs, the need for additional loop gain bandwidth occurs as switching frequencies are pushed towards the megahertz region.
One of the most popular ways to drive an optocoupler utilizes a TL431 Adjustable Shunt Regulator. It is configured on the output side of the power supply to modulate the optocoupler's photo diode current as a function of the power supply output voltage. Across its isolation boundary, the optocoupler transistor is connected to the PWM controller's error amplifier on the primary side of the power supply. Variations in the output voltage are optically transferred back to the error amplifier and control loop for correction. Providing additional features like over current protection or external shutdown require extra optocouplers and drive mechanisms, thus increasing the circuit complexity.
A linear regulator control IC, such as the UC3832, UC3833 or UC3836 can be substituted for the '431 while providing numerous additional features besides regulating the output. Overcurrent limiting and fault protection can be combined with the error voltage to drive the optocoupler and override it when necessary. Handshaking with external control logic, such as shutdown and sequencing is greatly simplified since the control IC is referred to the same ground. The most obvious benefit, however, is the introduction of the supplementary error amplifier in the feedback loop with programmable compensation.
Depending on the specific application, current limiting can be tailored to accommodate a programmable foldback characteristic, constant current or complete overcurrent shutdown. The UC3832 and UC3833 provide an addition level of versatility by offering a programmable duration event timer in the current limit circuitry. An adjustable trip threshold to accommodate varying load demands can be facilitated with the UC3832. For additional information, please consult application note U-116 and the respective device data sheets.
UC3833 LINEAR CONTROL IC DRIVES OPTOCOUPLED FEEDBACK +VOUT
PRIT MARYO · > PllM
OPTOCDUPLER
-YOUT
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Design Note
OPTOCOUPLER FEEDBACK DRIVE TECHNIQUES USING THE UC 3901 AND UC3903
DN-33
Numerous techniques and devices are available to the designers of optocoupler feedback circuits. The more traditional approaches utilize either an adjustable shunt regulator like. the TL431 device or an op-amp and voltage reference as the optocoupler driver. While these approaches do satisfy the basic requirements in many applications, quite often they lack the performance that is achievable from a more sophisticated circuit. Too often, these low cost solutions necessitate additional protection circuitry elsewhere in the control circuit to overcome the deficiencies in the feedback path.
A variety of low cost supervisory ICs contain the required building blocks for the more demanding optocoupler feedback drive applications. Initially developed to address other specific power supply tasks, several control ICs excel in the role as precision optocoupler control and drivers.
The basic building blocks necessary for optocoupler feedback control are a precision reference, an error
amplifier and a drive stage capable of approximately 20 milliamps. In a typical application, the power supply output voltage is monitored and compared to a reference voltage to the error amplifier inputs. Loop compensation and gain are programmed around the amplifier, and the resultant error voltage (Ve) modulates the optocouplerdrive current, hence feedback.
In addition to the simple regulation of output voltage, several other housekeeping functions can be performed on the secondary side of the power supply - all with a single integrated controller. Fault protection, for example, from an over voltage or an over current condition can be detected and used to override the normal optocoupler drive. An undervoltage lockout feature could prevent false feedback information during power-up and power down sequences of the power supply. Also, a POWER-OK indicator could separately communicate with the primary side controller, or used to gate the optocoupler drive at the secondary side.
Basic Optocoupler Driver Circuit OP AMP
REF
Vour
COMPENSATION Figure 1.
OPTO COUPLER
TO PWM
9-494
Design Note
DN-33
THE UC 3901 ISOLATED FEEDBACK GENERATOR Many isolated feedback applications required higher performance than can be obtained from an optocoupler feedback technique. Generally, these fall into one of two categories; high frequency switchers (above 250kHz) and those with very high voltage isolation requirements (greater than 5kV). The UC 3901 was developed to amplitude modulate a high frequency carrier applied to a transformer in place of the optocoupler. A peak detection circuit is used to reconstruct the error voltage waveform across the isolation boundary.
By disabling the internal oscillator, no chopping occurs and the outputs operate as linear drivers. When placed across an optocoupler this
configuration yields similar results to other drive techniques - with two advantages. First, a closed loop startup of the power supply can be obtained since both inputs to the error amplifier are made available. Rather than using the traditional approach of soft-starting the error amplifier output, the noninverting, or reference input is gradually ramped up. This technique prevents a large overshoot from occurring as the output approaches regulation. In contrast to the prior method, the amplifers loop compensation network is not abnormally biased during startup - causing the output excursions. Additionally, an over and under voltage detection is available at the UC3901 "Status output" pin. This open collector output can drive a separate fault indication optocoupler for communication to the PWM controller.
Optocoupler Drive Circuit Features Additional Protection
Vee
Vee E/A OUTPUT
Cr b-
EIA -
OUT A
E/A +
OUT B
VREF
l
UC3901
RT tJ
~ ~'"'' STATUS
FEEDBACK Vee
FEED BACK
-
TO PWM
Vee
TO FAULT CIRCUIT
~
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Design Notes
DN-35
IGBT DRIVE USING MOSFET GATE DRIVERS John A. O'Connor
IGBT Drive Requirements
Insulated gate bipolar transistors (IGBTs) are gaining considerable use in circuits requiring high voltage and current at moderate switching frequencies. Typically these circuits are in motor control, uninterruptible power supply and other similar inverter applications. Much of the IGBTs popularity stems from its simple MOSFET-like gate drive requirement. In comparison to bipolar transistors which were formally used in such designs, the IGBT offers a considerable reduction in both size and complexity of the drive circuitry. Recent improvements in IGBT switching speed has yielded devices suitable for power supply applications, thus IGBTs will compete with MOSFETs for certain high voltage applications as well. Many designers have therefore turned to MOSFET drivers for their IGBT drive requirements.
opposing devices can occur in such circuits, often with catastrophic results if proper gate drive and layout precautions are not followed. This behavior is caused by parasitic collector to gate (miller) capacitance, effectively forming a capacitive divider with the gate to emitter capacitance and thus inducing a gate to emitter voltage as illustrated in figure 1.
When high off-state dv/dt is not present, the IGBT can be driven like a MOSFET using any of the gate drive circuits in the UC37XX family as well as from the drivers internal to many switching power supply controllers. Normally 15 volts is applied gate to emitter during the on-state to minimize saturation voltage. The gate resistor or gate drive current directly controls IGBT turn-on, however turn-off is partially governed by minority carrier behavior and is less effected by gate drive.
There are several techniques which can be
COLLECTOR
employed to eliminate simultaneous conduction
when high off-state dv/dt is present. The most
fCca
GATE
important technique, which should always be
employed, is a Kelvin connection between the IGBT
emitter and the driver's ground. High di/dt present in
the emitter circuit can cause substantial transient
Cce
voltages to develop in the gate drive circuit if it is not
properly referenced. The Kelvin drive connection
also minimizes the effective driver impedance for
maximum attenuation of the dv/dt induced gate
CGE
voltage. This requirement adds complication to
driving multiple ground referenced' IGBTs due to
finite ground circuit impedance. Substantial voltages
EMITTER
may develop across the ground impedance during
Figure 1. High dv/dt at the collector couples to the gate through parasitic capacitance.
switching, requiring level shift or isolation circuitry at the command signal to allow Kelvin drive circuit
IGBT drive requirements can be divided into two connections.
basic application categories: Those that do not apply high dv/dt to the collector/emitter of the IGBT when
Bipolar Gate Driver
it is off, and those that do. Examples of the former A Kelvin connected unipolar driver may often be
are buck regulators and forward converters, where adequate at lower switching speeds, however
only one switch is employed or multiple switches are negative gate bias must be applied during the
activated synchronously. High dv/dt is applied off-state to utilize the IGBT at higher rates. This
during the off-state in most bridge circuits such as becomes apparent when one considers that the gate
inverters and motor controllers, when opposing to emitter threshold voltage drops to approximately
devices are turned on. Simultaneous conduction of 1.4 volts at high temperature. With high dv/dt at the
collector, a very low and impractical drive
9-496
Design Notes
DN-35
impedance is required to assure that the device remains off. By utilizing a negative turn-off bias, an adequate voltage margin is easily achieved, allowing the use of a more practical gate drive impedance. Fortunately most gate drivers have sufficient voltage capability to be used with bipolar
TTL
+Vee
1µF 2,4
1µF
IN5822
·VEE Figure 2. Blpolar IGBT gate drive using the U3708
power supplies. The UC3708 shown in figure 2 can deliver up to 6 amps peak with both output's paralleled, and is particularly suited to driving IGBTs. For added reliability during power sequencing, its output's "self bias", actively sinking current when
insufficient supply voltage is present. The positive supply,+Vcc, is normally 15 to 16 volts and the negative supply, -VEE, typically ranges between -5 and -15 volts depending on circuit conditions. A PNP level shift circuit references the drive signal to ground. Opto-couplers are also commonly employed, and may be interfaced directly to the gate driver by referencing the signal to the negative supply. Note that this is a very demanding application for optocouplers, and only devices rated for high CMRR should be used.
Isolated Gate Driver
A bipolar IGBT gate driver with over-current protection can be implemented using the UC3724/UC3725 isolated gate driver pair as shown in figure 3. The UC3724/UC3725 transmits both power and signal across a small pulse transformer, thereby achieving low cost, high voltage isolation. An additional transformer winding develops a negative voltage, providing a bipolar supply for the UC3708. The UC3724/UC3725 can also be used for circuits which do not require negative turn-off bias by simply eliminating the negative supply and external driver, and using the UC3725 to drive the IGBT gate directly. Application note U-127 covers the UC3724/UC3725 in depth.
·15
3
8 ·
UC3724
l111F
4
7 INPUT
a
Rr
·
ROFF
7
3
UC3725
a
2
111F
2N3801
2,4
3.llK 750
5 COF·
4 I 1 CF
~
Re
UC3111
·
2,4 AC
1,1
+
* 5,7
3,8
111F
AC
Figure 3. Power and signal are coupled to the UC3708 through the UC3724 / UC3725 Isolated Gate Driver Pair.
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Design Note
DN-36
UC1525B/UC1527B DEVICES Comparison Summary to UC1525A/27A Devices
The UC1525B and UC15278 devices are enhanced versions of the previous generation of UC1525A and UC1527A devices. They are pin-for-pin compatible and direct replacements for the "A" versions in
almost all applications. Significnt improvements have been made in the 5.1 V reference voltage and the output drivers as itemized in the tables below.
REFERENCE VOLTAGE VREF (min) VREF (max) Line Regulation (max) Load Regulation (max) Temperature Stability (max) Total Output Variation (max) Long Term Stability (max) Temperature Coefficient (typ) PWM OUTPUT SECTION Minimum On-Time (typ) Cross Conduction SUPPLY CURRENT ICC Increase (40 kHz to 400 kHz) ESD PROTECTION Discharge Withstand Voltage (typ)
5.062 v 5.138 v
+/-10 mV +/-15 mV +/-30 mV 5.036 V to 5.164 V +/-10 mV
8 ppm/deg. c
350 nS 30nC
15mA(max)
2 kV (typ all pins)
5.05 v 5.15 v
+l-20 mV +/-50 mV +/-50 mV 5.00 V to 5.20V +/-50 mV
600nS 150 nC
40 mA(typ)
no protection
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Design Notes
DN-37
PWM OPERATION WITH LOW INPUT VOLTAGES Bill Andreycak
Many of the PWM control ICs available today feature undervoltage lockout circuitry (UVLO) which requires minimum of 8 to 16 volts for turn-on to occur. This protection feature also makes them unsuitable for many low input voltage, or battery powered applications. A few of the mature ICs, however, can be "tricked" into operation by simply overriding their undervoltage lockout protection. The list includes the UC494A, UC1524 (non A), UC1526A, UC1841 and UC1851 PWM controllers.
5 VOLT INPUT PWM OPERATION
These devices relied primarily on the reference voltage (VREF) to be within its normal operating range to determine UVLO. Whenever the input voltage (VIN) is too low, the reference voltage, derived from the input, would also be too low. These devices can be brought into operation by pulling VREF, VIN and Ve (or collector supplies) above approximately 4. 7 volts. Operation from a fixed 5 volt input supply can be achieved with a slight degradation of performance.
A simple modification to this technique will allow operation with a variable low voltage DC input. A limiter circuit shown in figure 2 pulls VREF up to Vee when the input voltage is below about 5.5 volts. This circuitry then breaks the connection allowing Vee to rise without pulling VREF any higher. This is necessary to prevent VREF from exceeding its maximum rating of about 6 volts. Most of the PWMs listed will supply adequate bias to VREF with Vee above 6 volts. The limiter circuit can be modified to accommodate each individual controller and application, typically by adjusting the 20 K ohm base-to-emitter resistor. Another choice to the list of PWMs is the UC1860 controller which is fully functional at an input of 5 volts. This high speed device features operation to 3 MHz with dual 2 amp peak outputs. Although intended for variable frequency resonant mode conversion, it can be operated at a fixed frequency and pulse width modulated. (END)
VREF LIMITER CIRCUIT
+5 Voe
PWM
VIN
Ve
VREF
Figure 1.
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VAEF LIMITER CIRCUIT
VIN
4.5V MIN
2N 20K 2907
GND
10K
TO
VAEF
4.3V
ON:V1N-4.5V OFF:V1N·5.5V
Figure 2.
9-499
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Design Notes
DN-38
UNIQUE "CHEAP AND DIRTY" CONVERTER FOR LOW POWER BIAS SUPPLIES Bill Andreycak
Regulated output voltage is obtained - regardless of input voltage
Most power supply designs use PWM controller ICs and MOSFET switches which require 10 to 15 volt bias supplies for proper operation. A common application problem is to first generate an auxiliary supply within this range. Although simple in many applications, developing this supply with a variable low voltage input can be challenging especially when the input amplitude goes both below and above the desired output voltage. The circuit shown below is a unique, inexpensive solution to this problem.
Basically, the topology is a two transistor flyback (buck-boost) converter which provides a noninverting output polarity. By varying the duty cycle, the output voltage can be either higher or lower than the input amplitude. This attribute makes this approach ideally suited for many widerange input or automotive applications. Likewise, this technique is equally applicable to power factor correction applications. Additionally, the inductor can be operated in either the continuous or discontinuous current modes.
BUCK-BOOST CONVERTER (2 XTOR)
+
VouT
Figure 1,
Implementation of this technique will require a "high side" switch connected to the input voltage {VIN) and a low side switch to ground. Both of these are activated together, placing the inductor across the input supply while the switches are on. At turn off, the inductor is placed across the output capacitor
and the two diodes conduct until the current reaches zero (discontinuous mode) or the next switching cycle is initiated (continuous mode). lnductorvoltage and current waveforms are shown at maximum duty cycle for clarity.
INDUCTOR VOLTAGE AND CURRENT
IL
0
VL
0
Figure 2. At first, most PWM controllers may seem to be likely candidates for implementation of this technique. However, only one PWM features the ability to simultaneously switch both outputs together. The UC494A provides this operational mode by grounding its output control (0/C) input. Also limiting the IC selection is the fact that one IC output must go high and the other low each cycle. This is accomplished by connecting each of the UC494A's output collectors and emitters as required. Switching at 200kHz in this application, the UC494A is programmed by a 9.1 K timing resistor (RT) and 470 pF capacitor (CT). High frequency conversion facilitates the use of a small (surface mount) inductor and output storage capacitor. Output voltage is regulated by using the ICs "A" amplifier as the voltage error amplifier. The 15 volt output is divided
9-500
Design Notes
DN-38
down to 5 volts across the 15 K ohm resistor at pin 1 and compared to the reference voltage at pin 14. The 30K ohm resistor to Vout can be changed to provide different output voltages if required. Amplifier "B" is not used, but can be configured to provide overcurrent or overvoltage protection if desired. Schottky (1 N5820) diodes are used in the
power stage to maximize efficiency. Standard silicon diodes can be substituted in cost sensitive applications with some performance degradation. Efficiency for the 400 mW converter shown in figure 3 is approximately 50% for inputs between 7 and 16 volts and decreases slightly at higher and lower inputs. Consult Unitrode Design Note DN-37 for further information about 5 volt PWM operation.
BUCK BOOST CONVERTER USING THE UC 494A PWM CONTROLLER
12 VIN
COL A
11
F(OSC) - 200KHZ
VIN -5 TO 40 voe
VouT -15VOC
louT -25MA
10nF 10K
3 COMP
2 INVA
EMI A
UC494A
15 INVB
VREF
8 1N5820(2X)
VouT
NOTE VouT RISES FROM 12 TO 15VDC WHILE VIN RISES FROM
s TO s voe
RT
NONA
CT
NONB
15K
10µF
DEAD GND 0/C
1µF
9.1 470
K pF 4
Figure 3.
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Design Notes
OPTIMIZING PERFORMANCE IN UC3854 POWER FACTOR CORRECTION APPLICATIONS
by Bill Andreycak
DN-390
The performance of the UC3854 Power Factor Correction IC in the 250 watt application example has been evaluated using a precision PFC/THO instrument. The result was a power factor of 0.999 and Total Harmonic Distortion (THO) of 3.81%, measured to the 50th line frequency harmonic at nominal line and full load. Users should get similar results at these conditions. as well as over most line and load ranges. Summarized next are the circuit modifications which will improve the performance of most UC3854 PFC applications.
AMPLIFIER CLAMPS
There are a few ways to improve the obtainable power factor and performance in an application circuit. First, both the voltage and current amplifier outputs should have a "clamp" circuit to limit the output voltage swing and prevent saturation of the amplifier. Without the clamps, overshoot of the respective voltage or current loop could result thus degrading optimal performance. The current amplifier should be clamped with a 7.5 volt zener diode from the output (pin3) back to the inverting input ISENSE(pin4). Similarly, the voltage amplifier is clamped by installing a 1N4148 signal diode from its output (pin?) to the inverting input (pin11 ). Both examples are shown in figure 1. Each amplifier is self protected with internal current limiting, however the IC power consumption may increase during this interval.
1N4148 DIODE
TO Vour
VOLTAGE AMPLIFIER
--'\/v\r-------
COMPENSA TION
4 3
CURRENT
5
AMPLIFIER
CURRENT AMPLIFIER
OFFSET VOLTAGE CANCELLATION
The current amplifier maximum input offset voltage is specified as +/- 4 millivolts. Failing to accommodate the offset voltage can causes a spike in the leading edge of the line current following the zero voltage crossing. The spike will occur until the current amplifier comes out of saturation and then
Figure 1.
resumes normal operation. The worst case offset voltage can be canceled by adding a small current to the biasing resistor (R3) located from I SENSE (pin 4) to ground. This cancellation current (1.1 µA), when multiplied by the bias resistor value (3.9K) should be designed to provide the four millivolt offset.
9-502
Design Notes
DN-39D
This offset cancellation current should be obtained from the UC3854 supply voltage. Although a constant current source is optimal, a resistor from Vee to the I SENSE input will provide acceptable results as shown also in figure 1. An 8.2 megohm resistor will develop a 1.1 microamp current into the 3.9 Kohm resistor used in the design example. This will generate a 4.28 millivolt offset at the worst case of operation where Vee is 9 volts. It is adviseable to generate this bias from Vee and not the UC3854 reference which is inactive until the undervoltage lockout threshold is reached. Bias cancellation circuits from the reference could cause the current amplifier to saturate before the devices crosses its UVLO turn-on threshold. This condition will increase the start-up current of the UC3854 above its 2 milliamp specification and may prevent start-up in certain off-line applications.
CURRENT SENSE AMPLITUDE
The current sense signal should be made as high as possible, and a one volt full scale signal is recommended. Since resistive sensing can cause high power loss many users elect to generate only 100 to 200 millivolts at full load. In comparison, ground noise and slight amplifier offset voltages represent a higher percentage of the total current sense signal. Best results are obtained with the one volt (max) input and lower performance could be incurred with lower current sense signals. especially at light loads and high line voltages. Alternatives to resistive current sense are given below .
CURRENT SENSE TECHNIQUES
An optional technique to resistive current sensing should be considered to reduce power loss in the current sense circuitry. Two current sense transformers can be installed to sum both the switch and diode currents which will recreate the actual inductor current as shown in figure 2. These transformers must be designed to operate over the full range of duty cycles for the PFC converter design which approaches 100% as the line voltages nears zero.
Another current sensing option is to use a DC current sense module or transformer which is typically Hall Effect based. Two application concerns are the cost and accuracy of this technique which may limit its usage to only specialized applications.
PFC BOOST CONVERTER
TO
~
VIN
~3
<J
I t>
TRANSFORMER COUPLED CURRENT SENSE
TO PIN 4
TO PIN 5
Figure 2.
A single current sense transformer in series with the PFC switch can also be used. This technique will require some additional circuitry to accurately reconstruct the primary current signal as shown in figure 3. Generating the inductor current signal while the switch is on is a simple task. The difficulty is in reconstructing the inductor current while the switch is off while no current is flowing in the current sense transformer.
Inductor current sensing can be simplified to use only one current sense transformer and a current sink circuit. The current sense signal is developed across resistor RI through diode DI while the switch is on. A second diode to the current sense transformer develops an identical voltage across capacitor Cl as determined by the current sense resistor primary current and turns ratio. When the PFC switch turns off capacitor Cl maintains the peak amplitude of the previous current sense signal.
9-503
Design Notes
DN-39D
Charge is removed by an ideal current sink circuit which lowers the capacitor voltage linearly during one switching cycle. The current is scaled to discharge at the rate proportional to Vout minus
PFC BOOST CONVERTER
TO VIN
TO VREF
TO CF+
I IN
IREF
Vour
TO
~3 I~ VIN
<Ji---------,_
~NGLE TRANSFORMER CURRENT SENSE
+
T1
TO PIN 4
TO PIN 5
Figure 3.
Vin(t) divided by the inductor value, L. The input voltage (Vin) is constantly varying throughout the AC line cycle and so must the capacitor discharge current. The circuitry shown in figure 4 will modulate the current sink inversely with the instantaneous line voltage. This will result in the correct discharge of capacitor C1 to reconstruct the actual inductor current. Polarity has been optimized for use with the UC3854 which requires a current sense signal below the ground reference. Another option is to develop a few volts of current sense signal to improve noise immunity and resistively divide this down to the one volt maximum input to the UC3854 controller. Transistors QI through Q4 should be identical for best results. Transistors QI and Q3 are for temperature compensation of the base emitter
TO
CFILT ·
Figure 4.
junctions of Q2 and Q3. Emitter ballasting (50 to 100 mV) will also improve performance. The emitter currents of QI and Q2 should be similar and equal to Vin/Rin. This current is diverted away from the bases of Q3 and Q4 which limits the total range of sink current to the current sense filter capacitor, CFILT.
SCHOTTKY PROTECTION DIODES
Each pin of the UC3854 must be protected from negative voltages exceeding minus three hundred millivolts (·0.3V) maximum. In most applications, only three pins of the IC need external protection Schottky diodes. The gate drive output (pin 16) requires a 1N5820 3 amp Schottky diode to protect against parasitic inductive effects with high speed switching. The multiplier output (pin 5) and peak current limit (pin 2) need Schottky diode protection during abnormal overcurrent conditions and during the initial inrush currents upon power-up. A 1N5817 Schottky diode will provide adequate clamping since
PFC BOOST CONVERTER
· Vour
~~ TO
VIN
AUXILIARY WINDING
9-504
Design Notes
REGULATED AUXILIARY BIAS
0.1µF A
T CAUX
0.1µF
Figure 5.
the currents are low due to series resistors to the current sense circuitry.
REGULATED AUXILIARY SUPPLY A secondary winding on the PFC boost inductor can be used to deliver a regulated auxiliary bias supply with few external components as shown in figure 5. Unlike more conventional and unregulated single diode or bridge rectifier techniques, this approach uses two diodes in a full wave configuration. This arrangement develops two separate voltages across capacitors C 1 and C2 each with 120 Hz components. However, when these two are summed at capacitor C3, the line variations are canceled, and a regulated auxiliary bias is obtained. The number of turns on the secondary winding will adjust the bias supply voltage. Additional windings on the boost inductor with similar rectification and filter circuitry can be used to deliver other semi-regulated isolated outputs.
UC 3854 POWER FACTOR CORRECTION EVALUATION KIT
LIST OF COMPONENTS
CAPACITORS (25 VDC) C1 = 0.47 µF/250 VAC
c2 = 4So µF/4So voe
C3 = 270 pF C4= 1 µF CS= NOT USED C6 = 47 nF C7 = 0.47 µF ca= NOT USED C9 = 100 mF
C10=10nF C11 =1 nF C12 = 0.1 µF C13 = 62 pF C14 =NOT USED C1S = 620 pF C16 = 1 µF
DIODES 01 =4 AMP/800VDC BRIDGE 02 = UHVP806 FAST RECOVERY D3 = 18 V ZENER 04 = 1NS821 SCHOTTKY 3A DS = 1N4148 06 = 1 AMP/100V BRIDGE D7 = 1NS817 Schottky 08 = 1NS817 Schottky
FUSE F1 - 6A/2SOVAC FUSE
INDUCTOR L1 = 1 milliHenry Inductor
TRANSISTORS 01 = SOOV/0.2S ohm NMOS FET 02 = 4SOV/O.SA NPN 03 = SOV/.SA NMOS FET
RESISTORS (1/2 WATT) R1 - 0.2S ohm/SWATT
R2 = 3.9 K R3 = 3.9 K R4 = 1.6 K
RS= 10 K
R6 = 24 K
R7 =240 K RS= 910 K (400V) R9 = 91 K R10 = 20 K R11=220 K R12=27K R13=75K R1S =ZERO ohm R20 = 3 K R21 = 24 K R22 = 30 K/3W R23 = 470 K R24 = USER SPECIFIED R2S = 910 K (400V) R26 = NOT USED (OPEN)
THERMISTOR TH1 =ohm NTC
INTEGRATED CIRCUIT U1 = UC38S1 PFC CONTROLLER
9-505
DN-39D
-m<n" ~c
!'"°O-l
~§g
-~-~~~m "5'l~"m~
;,;:§~
E~~
sgJ~
-~:~E~e
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I
~
~
0 Cl
250 WATT EXAMPLE VM·I0·270VAO
INRUSH DIOCE
FILTER
C1
+I · .
·I ·
1....AA..A..J
·
DI
I
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I
n~r!
I
~ <:: ~
.......T.P..".P............
.
a:
REGULATED BIAS SUPPLY
Y.ux AC IN
;
.i..
1N4148 VIA CLAMP
Q
T ..!..... ~...~ ....
TO
CURRENT AMP
YGUT
R7 240K
OFFSET BIAS
C.A..N.C.E..L.L.A.T.I.O.N.
~'°PIN 4 TO y_,
ce
Yeo ..J.11Y/10Y 5;
47nF
MULT OUT
:a?:
I
I
I IENA~.JJ....-'"
~ :l!::l
RI
24K
Cll 120pF
C1~. -~~~~ .~...
;±.. 7.-·Y...
4 I (SENS C/A
I
I I
I
.I 1·· Fe1
A M
I ~ I la '"c
A
r
A o
.Qw,
:>
....
I I ~ ~~~
ifiJ:i i'
c
ILMT
~...
Q
88
/\,
L _.!__ --- ~·--- --- ~
QND
TO
I ;~- 1.~. -1)~ J_
A21 NOT USED
y..,
C111ftF
SYNC~
R16 0 OHM
R14 llK
m c
c5"
:::J
z
0
i
I DQRTY
04 1N6820
I
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~
OC:
:Eo
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1O--~~J mcUDCoiX1l1>I
g. '~Tl II>
0 :::J
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S-l·. a.....
:0::J "(')' )> ';j'
-"C CD
"'2. 3
-· 111
I:(:':I!):>. n-·
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-UNITRODE Design Note
DN-40
THE EFFECTS OF OSCILLATOR DISCHARGE CURRENT VARIATIONS ON MAXIMUM DUTY CYCLE AND FREQUENCY IN UC3842 AND UC3842-"A" PWM ICs
by YEAM CHONG HOCK
Many designers try to program a precise maximum duty cycle and operating frequency by careful selection of the oscillator timing components, Rt and Ct. Because of the variations in oscillator discharge current, very accurate programming is not easily obtainable. However, it is possible with ICs which contain a "trimmed" discharge current which has specified limits. This Design Note will detail programming frequency and maximum duty cycle with both types of oscillators. Simplified equations will be used to develop obtainable ranges for these parameters over IC tolerances.
ON-TIME Maximum on-time directly corresponds to the maximum charging time of the timing capacitor. Charging time {Tc) is determined by the timing capacitor
IR
RT VREF
IC
ID
CT
Figure 2: Timing Waveforms and Design Equations
value (Ct), the charging current (IRt) and the voltage amplitude between the upper and lower oscillator thresholds.
OFF-TIME (DEADTIME)
The off-time occurs while the timing capacitor is discharged from the oscillator upper threshold to it lower threshold. The discharge current actuall sinks two currents to ground. One current is flowing from the discharging timing capacitor. Another current flows from the timing resistor (Rt) pulling to Vref. Therefore, the effective timing capacitor discharge current (ICt) is the ICs discharge current (Id) minus the timing resistor charging current (IRt). Maximum duty cycle and switching frequency can be controlled by accurately setting the ratio of
Figure 1: Basic UC3842 Oscillator Circuit
9-507
these currents and capacitor value. The related equations are listed below.
CHARGING:
/Ct- Cx ~~ICt =C * dV /Tc
/Ct-~ (approximation)
TC- ex dV /Rt
DISCHARGING :
/Ct- Id- /Rt
Td· ex dv (/Rt- Id)
Td- (Id- /Rt) Id
DUTY CYCLE:
D- Tc (Tc+Td)
D- (Id- Rt) Id
SWITCHING FREQUENCY: p __1__ 1
Tper ( Tc + Td)
F- ( ld-IRt) ( ldx Tc)
EXAMPLE 1:
This example will calculate the potential variations in maximum duty cycle and frequency using a standard UC3842 device. A ten milliamp internal discharge current (Id = 10mA) will be used for initial programming. The worst case limits of 6 and 14 milliamp discharge currents will be used to analyze the possible variations. A target of 1OOkHz at 60% duty cycle will be used.
Id - 10mA ( typicaJ Id( min )-6ma, Id( max)= 14ma F( typ) = 100kHz D-0.60 ( 60%)
DN-40
Based on the 1O mA discharging current and the equations previously mentioned;
/Rt - 4mA, and Tc - 6us
Using the same Rt and Ct values with a discharge current of 6 mA results in :
Dmax- 0.33 ( 30% )
F-55kHz
When the highest discharge current of 14 mA is used, the results are :
Omal(-0.71 ( 71%)
F-118kHz
Therefore, the total possible range due to discharge current variations in maximum duty cycle and frequency is :
Dmax - 33 71 percent
Frequency- 55188kHz
In most applications this range is far too wide to use in a high volume production environment. One technique to minimize the effects of the discharge current is to have the ICs sorted into different groups. Each group can have a tight distribution or tolerance and will use a specific timing resistor and capacitor to achieve the desired frequency and duty cycle. Each other group will also need a specific Rt and Ct fro that group. Keeping these groups separated can create problems in some production situations. One alternative is to have the ICs measured and "binned" at the factory. Another way is to use only ICs within one distribution
group, for example, 1O mA +/- 1 mA. Listed below
is a general procedure to follow with grouped parts.
1. Sort ICs by discharge current range
ex: 7mA +/- 1 mA (6 - 8 mA total)
2. Select Rt and Ct using previous equations and worst case conditions.
Table 1 shows the results of selecting ICs by discharge current. The oscillator was programmed not to exceed 100 kHz and 60% maximum duty cycle.
9-508
I Discharge Rt Ct (+/-1mA) (k) (nF)
7mA
1.56 11.3
Minimum Maximum Minimum Maximum Duty% Duty% Freq (kHz) Freq (kHz)
47
60
n.8
100
9mA
1.25 14.1 50
60
83.3
100
11mA
1.04 16.9 52
60
86.7
100
DN-40
TRIMMED DISCHARGE CURRENT
Very repeatable and predictable high volume prouduction can be rescued from these variations by using the right IC, one with a trimmed discharge current. The UC3842A, UC3843A, UC3844A and UC3845A devices have an internal factory trimmed discharge current with a tight distribution. This is set at 8.3 mA typically, and can only vary between a low of 7.5 mA and a high of 8.8 mA. Programming these ICs for a 50% maximum duty cycle and 100 kHz switching frequency will result in worst case variations of :
D(min)-56%
D(max)-62%
F( min)· 92.9kHz
F( max)-103.SkHz
This is a significant improvement over the non "A" version devices. The accuracy of these ICs will improve when these ICs are used at wider maximum
duty cycles, for example 65 to 85 percent. The
UC3844A and UC3845A are intended for 50% maximum duty cycle applications and contain a flip
flop to insure that 50% D(max) is never exceeded.
The UC3842A and UC3843A have maximum duty cycles near 100% and can be adjusted lower using
the appropriate Rt and Ct componen1s.
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9.509
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EXTEND CURRENT TRANSFORMER RANGE
DN-41
by PHILIP C. TODD
Transformers are used extensively for current sensing because they can monitor currents with very low power loss and they have wide bandwidth for good waveform fidelity. Current transformers perform well in applications with symmetrical AC currents such as push-pull or full bridge converter topologies. In single-ended applications, especially boost converters, problems can arise because of the need to accurately reproduce high duty factor, unipolar, waveforms. Unipolar pulses may saturate the current transformer and, if this happens, over current protection will be lost and, for current mode control, regulation will be lost and an over voltage condition will result.
The transformer core must be reset after each pulse so that the full range of the transformer will be available for the next pulse. Self reset of the current transformer is the most common techniques used but it has drawbacks. Self reset uses the energy stored in the current transformer core for reset and depends on the open circuit impedance of the current transformer to generate enough volt-seconds in a short period of time for reset. Current transformers operated above a 50% duty factor may not have enough stored energy to allow complete reset in the time available and this situation becomes worse as the duty factor approaches 100%.
The magnetizing inductance of the current transformer must be kept high because this determines the amount of droop the current waveform will exhibit over the pulse period. The higher the inductance the lower the droop will be. The waveform droop opposes slope compensation and should be kept to a minimum. High magnetizing inductance also means that the core stores very little energy which can be used to reset the core.
The current transformer turns ratio generally needs to be high to lower the power loss. The more turns put on the core, however, the greater the leakage inductance and the greater the parallel capaci-
tance. The leakage inductance by itself is generally not a problem but it will limit the current rise and fall times. The parallel capacitance also limits the bandwidth of the current transformer but it is a greater problem during transformer reset. For the transformer to reset properly, alt of the energy stored in the core must be removed. In self reset this energy must transfer from the magnetizing inductance to the parallel capacitance in a resonant manner. If the capacitance is too large, the resonant frequency will be too low and the magnetizing inductance will not be reset before the next pulse begins.
T
D
Vi
Rs
Figure 1: Conventional self-reset current transformer
Figure 1 shows a conventional current transformer circuit which uses self reset. The current I flowing in the primary, causes a current to flow through D and Rs to generate an output voltage proportional to Vc=IRs/N where N is the current transformer turns ratio. The problems discussed above occur during the reset interval when 1=0. The core of T may not have enough energy to fully reset itself in the time available given the secondary capacitance of T plus the capacitance of D.
The problems~with self reset of current transformers for unipolar pulse applications can be overcome with simple forced reset techniques derived from magnetic amplifiers. Duty factors above 90% are achievable with these techniques.
9-510
vcc
T
Rr
Vi
Rs
DN-41
the current pulse to be measured. This can be beneficial in some applications as it doubles the number of volt-seconds available from the transformer.
VCC
T
Rr
Rs
Figure 2: Current transformer with forced reset
Figure 2. shows the same circuit as Figure 1 configured for forced reset. The diode D has been moved from the high side of the transformer secondary winding to the ground side. This, of course, has no effect on the operation of the circuit and during the pulse this circuit behaves exactly as expected. During reset, however, Rr makes the circuit operation quite a bit different.
A current from Vee through Rr can be much greater than the self reset current available from the magnetizing current of the transformer. This forcing current rapidly charges the parasitic capacitances and reverses the voltage on the secondary of the transformer. The applied volt-seconds can quickly reset the core so that high duty-factor operation is possible.
The forced reset may be high enough to drive the
current transformer into saturation and this is an acceptable practice because the core will be saturated in the opposite direction (i.e. full reset) from
D
VI
Figure 3: Negative output current sense
In some applications it may be desirable to generate a negative voltage from the current transformer. This can be accomplished without a
negative voltage source to reset the transformer.
Figure 3 shows the .configuration. In this circuit there will be an error beca.use the reset current subtracts from the sense current in Rs during the pulse. Care must be taken to minimize this effect.
There are other circuit configurations which are possible to force reset of the current transformer.
Switches may be used to switch the reset current on and off. Additional windings or center tapped windings may be used also. Many circuits are po&sible and may provide a specific improvement at the expense of complexity. The circuits shown
here are the simplest available and illustrate the
basic concept.
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-UNITRDDE Design Notes
DN-42
DESIGN CONSIDERATIONS FOR TRANSITIONING FROM UC3842 TO THE NEW UCC3802 FAMILY John Gaumont
In arr attempt to stay abreast of trends in the power supply marketplace, the Power Supply Design Engineer is perpetually seeking methods of improving upon existing designs. Requirements such as lower power for battery operated equipment, higher switching frequencies for reduced magnetics size, higher levels of circuit integration for improved reliability and lower cost have become necessities for survival.
The UCC3802 offers numerous advantages which allow the Power Supply Design Engineer to meet these
challenging requirements. Features include:
·
· Bl-CMOS Process
· Low Starting Supply Current: typically 1OOµA
· Low Operating Supply Current: typically 500µA
Pin out Compatible with UC3842 and UC3842A
families
· 5 Volt Operation (UCC3803, UCC3805)
· Leading Edge Blanking of Current Sense Signal
· On-Chip Soft Start
,
· Internal Full Cycle Restart Delay
· 1% Voltage Reference
· Up to 1 MHz Oscillator
· Self-Biasing Output Low During UVLO
· Very Few External Components Required
· 70ns Response from Current Sense to Output
· Available in Surface Mount or DIP Package
The UCC3802 family of devices are pin out compatible with the UC3842 and UC3842A families however, they are NOT PLUG-IN COMPATIBLE. In general, the UCC3802 requires fewer external components and consumes less operating current. The following UCC3802 family attributes should be considered BEFORE inserting the device into a UC3842/42A family socket:
1. Maximum supply voltage 2. Turn-on and Turn-off thresholds 3. Oscillator Rt, Ct values 4. Schottky diodes may not be required on output
due to MOS body diode 5. No current sense filter required 6. No soft start circuitry required 7. Auxiliary power (bootstrap winding) may not be
required
PIN 1 COMP--The UCC3802 has a true low output impedance error amplifier which both sources and sinks current. The error amplifier associated with the UC3842 family is an open collector in parallel with a current source. The UCC3802 has power-up soft start and fault soft start bu.ilt on-chip with a fixed COMP rise time to 5V in 5ms. Therefore, NO EXTERNAL SOFT START CIRCUITRY IS REQUIRED saving 1 resistor, 1 capacitor, and 1 PNP transistor.
PIN 2 FB--The UCC3802 features a 2 MHz bandwidth error amplifier versus 1 MHz on the UC3842. Feedback techniques are identical to the UC3842 family. Stray capacitance on FB should be kept ·as small as possible, and the lead length as short as possible to achieve best stability.
PIN 3 CS--The UCC3802 current sense is significantly different from its predecessor. The UC3842 current sense input connects to only the PWM comparator. The UCC3802 Current Sense input connects to two comparator~; the PWM comparator and the over-current comparator. Internal leading edge blanking masks the first 1OOns of the current sense signal. This MAY ELIMINATE THE NEED FOR AN RC CURRENT SENSE FILTER AND PREVENT FALSE TRIGGERING due to leading edge noise. Connect CS directly to MOSFET source current sense resistor. The gain of the current sense amplifier on the UCC3802 family is typically 1.65 VN versus typically 3 VN with the UC3842 family.
Detailed Pin By Pin Description
PIN 4 RC--The UCC3802's oscillator allows for operation to 1 MHz versus 500KHz with the UC3842.
9-512
Design Notes
DN-42
Both devices make use of an external resistor to set
the charging current for the capacitor which
determines the oscillator frequency. For the
UCC3802 and UCC3804 F(Hz)
1
.5/R(OHMS)C(F). For the UCC3803 and UCC3805
F(Hz)=1.0/R(OHMS)C(F). The two equations are
different due to different reference voltages. The
recommended range of timing resistor values is
between 20K and 200K; the recommended range of
timing capacitor values is between 1OOpF and
1OOOpF. The peak to peak amplitude of the oscillator
waveform is 2.45 Volts versus 1.7 Volts. For best
performance, keep the timing capacitor lead to GND
as short as possible. Separate ground traces for the
timing capacitor and all other pins are
recommended. The maximum duty cycle for the
UCC3802/03 is approximately 99%; the maximum
duty cycle for the UCC3803/04 is approximately
49%. The duty cycle CANNOT be easily modified by
adjusting the RT and CT pins, unlike the UC3842A
family. The maximum duty cycle limit is set by the
ratio of the external oscillator charging resistor RT
and the internal oscillator discharge transistor
on-resistance, like the UC3842. However, maximum
duty cycle limits less than 90% for the UCC3802/03
and less than 45% for the UCC3804/05 can not reliably be set in this manner.
PIN 5 GND--Both devices same.
PIN 6 OUT--The output of the UCC3802 is a CMOS output versus a Bipolar output on the UC3842. Peak output current remains the same +/- 1 Amp. The CMOS output provides very smooth rising and falling waveforms, with virtually no overshoot or undershoot. Additionally, the CMOS output provides a low resistance to the supply in response to overshoot, and a low resistance to ground ·in response to undershoot. Because of this, SCHOTTKY DIODES MAY NOT BE NECESSARY on the output. Furthermore, the UCC3802 has a self-biasing, active low output during UVLO. This feature ELIMINATES THE GATE TO SOURCE 'BLEEDER' RESISTOR associated with the MOSFET gate drive. Finally, NO MOSFET GATE VOLTAGE CLAMP is necessary with the UCC3802 as the on-chip zener diode automatically clamps the output to VCC.
PIN 7VCC--The UCC3802 has a lower VCC (supply voltage) of 13.5 Volts typical versus 30 Volts on the
....:.:.:···1····1···:.::.... ·····.
'·
:j: :]; :~:
:·.-.·:
··········..:.···· ...................:'
Figure 1 Figure 1 illustrates a nonisolated off-line flyback. Dotted components may be eliminated using the UCC3802 family.
9-513
Design Notes
DN-42
UC3842. For applications which require a higher VCC voltage, a resistor must be placed in series with VCC to increase the source impedance. The maximum value of this resistor Rmax = (VIN(min)-VCC(max))/(ICC + (Qgate)(F)). Additionally, the UCC3802 has an on-chip zener diode to regulate VCC to 13.5 Volts. The turn-on and turn-off thresholds for the UCC3802 family are significantly different: 12.SV and 8V for the UCC3802 and UCC3804; 4.1 V and 3.6V for the UCC3803 and UCC3805. 5 Volt PWM operation is now possible. To ensure against noise related problems, filter VCC with an electrolytic and bypass with a ceramic capacitor to ground. Keep the capacitors close to the IC pins.
PIN 8 REF--The UCC3802 and UCC3804 have a 5 Volt reference. The UCC3803 and UCC3805 have
a 4 Volt reference; both +/- 1% versus+/- 2% on the UC3842 family. The output short circuit current is lower...5mA versus 30mA. REF should be bypassed to ground with a ceramic capacitor to prevent noise problems. REF can be used as a logic output; as when VCC is lower than the UVLO threshold, REF is held low.
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAl BLVD. · MERRIMACK, NH O'.X>54 TEL. (603) 424-2410 · FAX (603) 424-3460
9-514
Sales Offices
10-1
n n INTEGRATED
~CIRCUIT&
-UNITROOE
10-2
n n INTEGRATEC
~CIRCUITS
-UNITROOE
Effective Date: June, 1993
UNITRODE INTEGRATED CIRCUITS CORP.
Eastern Area Office 7 Continental Boulevard, Merrimack, NH 03054-0399, TEL: (603) 424-2410, FAX: (603) 424-3460
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Compass Marketing 11801 Tatum Blvd. Suite 101 Phoenix, AZ 85028 TEL: (602) 996-0635 FAX: (602) 996-0586
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DELAWARE
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DISTRICT OF COLUMBIA
See Maryland
10-3
FLORIDA
Photon Sales, Inc. 1600 Sarno Rd., Suite 21 Melbourne, FL 32935 TEL: (407) 259-8999 FAX: (407) 259-1323
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Victory Sales 1030 W. Higgins Rd. Suite 101 Hoffman Estates, IL 60195 TEL: (708) 490-0300 FAX: (708) 490-1499
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Scott Electronics Lima Valley Office Village 8109 Lima Rd. Fort Wayne, IN 46818-2162 TEL: (219) 489-5690 FAX: (219) 489-1842
DOMESTIC REPRESENTATIVES (Continued)
Scott Electronics 7321 Shadeland Station Suite256 Indianapolis, IN 46256-3920 TEL: (317) 841-0010 FAX: (317) 841-0107 IOWA See Minnesota
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MAINE
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MARYLAND Third Wave Solutions 8335-H Guilford Rd. Columbia, MD 21046 TEL: (410) 290-5990 FAX: (410) 381-5846
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Greiner Associates 15324 E. Jefferson Ave. Gross Pointe Park, Ml 48230 TEL: (313) 499-0188 FAX: (313) 499-0665
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NEW JERSEY - NORTHERN ERA, Inc. 354 Veterans Memorial Highway Commack, NY .11725 TEL: (516) 543-0510 FAX: (516) 543-0758 NJ#: (800) 645-5500
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ERA, Inc. 354 Veterans Memorial Highway Commack, NY 11725 TEL: (516) 543-0510 FAX: (516) 543-0758
NEW YORK- UPSTATE
Reagan Compar 3301 Country Club Road Suite 2211 Endwell, NY 13760 .TEL: (607) 754-2171 FAX: (607) 754-4270
NORTH CAROLINA
R.O. Whitesell & Assoc. 1920 Highway 54 Suite320 Durham, NC 27713 TEL: (919) 544-3380 FAX: (919) 544-3709
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See Minnesota
OHIO
R.O. Whitesell & Assoc. 4133 S. Dixie Avenue Dayton, OH 45439 TEL: (513) 298-9546 FAX: (513) 298-2586
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10-4
DOMESTIC REPRESENTATIVES (Continued)
OKLAHOMA Nova Marketing, Inc. 8125 D East 51st St. Suite 1339 Tulsa, OK 74145 TEL: (918) 660-5105 FAX: (918) 665-3815
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RHODE ISLAND
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SOUTH CAROLINA See North Carolina
SOUTH DAKOTA See Minnesota
TENNESSEE
R.O. Whitesell & Assoc. 9208 Kingston Pike Suite 358 Knoxville, TN 37922 TEL: (615) 694-9476 FAX: (615) 691-9693
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Nova Marketing, Inc. 831 O Capital of Texas Highway Suite 180 Austin, TX 78731 TEL: (512) 343-2321 FAX: (512) 343-2487
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Salt Lake - CSI, Inc. 411 West 7200 South Suite 301 Midvale, UT 84047 TEL: (801) 561-5099 FAX: (801) 561-6016
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10-5
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WISCONSIN - WEST
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CANADA Kaytronics, Ltd. 5800 Thimens Blvd. Ville St. Laurent Quebec H4S 1$5 TEL: (514) 745-5800 FAX: (514) 745-5858
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n n INTEGRATED
~CIRCUITS
-UNITRODE
Effective Date: June, 1993
DOMESTIC DISTRIBUTORS
Unijrode has over 200 distributor branches to serve its customers. For the location of the branch nearest you, please contact any of our franchised distributors.
HALL-MARK ELECTRONICS CORPORATION 11333 Pagemm ·Road Dallas, TX 75266 (214) 343-5000
HAMILTON/AVNET 10950 Washington Boulevard Culver City, CA 90232 (310) 558-2000
FUTURE ELECTRONICS 237 Hymus Boulevard Pointe Claire, Quebec, Canada H9R5C7 (514) 694-7710
NU HORIZONS ELECTRONICS CORPORATION 6000 New Horizons Boulevard Amityville, NY 11701 (516) 226-6000
ZEUS COMPONENTS, INC. 100 Midland Avenue Port Chester, NY 10573 (914) 937-7400
10-6
n n C_j
INTEGRATED CIRCUITS
-UNITROCE
Effective Date: June, 1993
UNITRODE INTERNATIONAL SALES OFFICES
Corporate International Sales Office 7 Continental Blvd., P.0. Box 399, Merrimack, NH 03054-0399 TEL: +1-603-424-2410, FAX: +1-603-424-3460
Unitrode Electronics GmbH Haupstrasse 68, 82008 Unterhaching, Germany TEL: +49 (0)89 6190 04/05/06, FAX: +49 (0)89 617984
Unitrode (UK) Limited 6 Cresswell Park, Blackheath, London SE3 9RD, England TEL: +44 (0)81 3181431, FAX: +44 (0)81 318 2549
Unitrode SRL Via Dei Carracci, 5, 20149 Milano, Italy TEL: +39 (0)2 480 07831, FAX: +39 (0)2 480 08014
Unitrode Ireland Ltd. Shannon Industrial Estate, Shannon, County Clare, Ireland TEL: +353 (0)61 472377, FAX: +353 (0)61 472529
Unitrode Electronics Asia Ltd. Suite 939, New World Office Bldg., 24 Salisbury Road, Kowloon, Hong Kong TEL: +852 722 1101, FAX: +852 369 7596
Unitrode Electronics (Singapore) PTE, Ltd. 55 Ayer Rajah Crescent, Unit #05-17/26 & 06-12/16, Singapore 0513 TEL: +65 779 2777, FAX: +65 779 4395
International Agents - Distributors
ARGENTINA
Reycom Electronica SRL Uruguay 362 Peso 8, Depto. F, 1015 Buenos Aires TEL: +54 (0)1111720 FAX: +54 (0)1111721
AUSTRALIA
Priority Electronics Pty. Ltd. Suite 1· 23-25 Melrose St. Sandringham, Victoria 3191 TEL: +61 (0)3 521 0266 FAX: +61 (0)3 521 0356
Priority Electronics Pty. Ltd. Suite 2, 25 Chard Road P.O. Box 560 Brookvale, NSW 2100 TEL: +61 (0)2 905 6024 FAX: +61 (0)2 939 6348
AUSTRIA
CODICO GmbH & Co. KG Muhlgasse 86 88 A-2380 Perchtoldsdorf TEL: 0222-862428 FAX: 0222-863257
BELGIUM
REPRESENTATIVE
lndel Postbox 1092 2340 BB Oegstgeest The Netherlands TEL: 31 (0) 71 170248 FAX: 31 (O) 71156599
DISTRIBUTORS
Koning en Hartman P.0.125 2600 AC Delft The Netherlands TEL: +31 (0)15 609906 TEL: +31 (0)15 619194
Sonetech NV Belgium Limburg Stirumlaan 243 1780 Wemmel TEL: +32 (0)2 460 0707 FAX: +32 (0)2 460 1200
BRAZIL
Hi Tech Commercial and Industrial Ltda. Av. Eng. Luiz Carlos Berrini, 801, Cj. 121 Cidade Moncors Sao Paulo 04 571 TEL: +55 (0)11 542 9833 FAX: +55 (0)11 240 2650
10-7
ETEK Electronics Corp. 6353 West Rogers Circle Suite3 Boca Raton, FL 33487, USA TEL: +1-407-997-6277 FAX: +1-407-997-5467
DENMARK
REPRESENTATIVE
Repretech Scandinavia AB Fagardal, 197 93 Bro Sweden TEL: +46 (0)8 582 431 25 FAX: +46 (0)8 582 433 58
DISTRIBUTOR
Techpartner A/S Sylbaekvej 33 DK-8230 Aabyhoj TEL: +45 (0)8 625 0055 FAX: +45 (0)8 625 2855
EASTERN EUROPE
Unitrode Electronics GmbH Hauptstrasse 68, 82008 Unterhaching, Germany TEL:+49 (0)89 619 004-006 FAX: +49 (0)89 617984
INTERNATIONAL AGENTS ·DISTRIBUTORS (Continued)
ATR Microsystems Gmbh Wickenburggasse 12 8010 Graz, Austria TEL: +43 (0)316 60920 FAX: +43 (0)316 609299
Plamen Fillev B.Sc.Eng. (Ase) P.O. Box 140 Sofia 1618, Bulgaria TEL/FAX: 359 (0)2 525 537
Macro Weil Spol s.r.o. Bechynova3 160-00 Praha 6, Czech Republic TEL: +42 (0) 2311 2182 FAX: +42 (0) 2 311 3454
Macro Zilina Vysokoskolakov 6 010-01 Zilina, Slovak TEL: +42 (0)8 934 181 FAX: +42 (0)8 934109
Macro Information and Service Office H-1016 Budapest, Hungary Szamado U.15 FSZ.3 TEL: +36 (0)1 186 8033 FAX: +36 (0)1 185-2318
Macropol Co. Ltd. 03-301 Warszawa UL Jagiellonska 80, Poland TEL/FAX: +48 (0)22 112 933
FINLAND
REPRESENTATIVE
Repretech Scandinavia AB Fagardal, 197 93Bro Sweden TEL: +46 (0)8 582 431 25 FAX: +46 (0)8 582 433 58
DISTRIBUTOR
Yleiselektroniikka OY PL63, 02201 Espoo TEL: +358 0 4526 21 FAX: +358 0 4526 2231
FRANCE
REPRESENTATIVE
Unirep Zone lndustrielle de la Bonde 1 bis, Rue Marcel Paul Batiment B 91300 Massy TEL: +33 1 69 20 03 64 FAX: +33 1 69 20 00 61
DISTRIBUTORS
Syscom Electronique Euro pare Pare Activities Technologiques 65, Rue Auguste Perret 94042 Creteil Cedex TEL: +33 (1) 43 77 84 88 FAX: +33 (1) 43 77 53 49 TELEX: 262566
Syscom Electronique Agence RHONE-ALPES 10-12, Rue Ste. Anne-de-Baraban 69006 Lyon TEL: +33 (16) 72 33 71 22 FAX: +33 (16) 78 53 66 06
C.C.I. Zone lndustrielle 5, Rue Marcel Berthelot 92160 Antony Cedex TEL: +33 (1) 46 74 47 00 FAX: +33 (1) 42 37 24 30 TELEX: 203881
C.C.I. 67, Rue Bataille 69008 Lyon TEL: +33 (16) 78 74 44 56 FAX: +33 (16) 78 76 08 91 TELEX: 375456
GERMANY
Unitrode Electronics GmbH Hauptstrasse 68 82008 Unterhaching TEL: +49 (0)89 6190 04/05/06 FAX: +49 (0)89 617984
REPRESENTATIVE
HY-LINE Power Components lnselkammerstrasse 1O Postfach 1222 82008 Unterhaching TEL: +49 (0)89 614 9010 FAX: +49 (0)89 614 0960
HY-LINE Power Components Oedenbergerstrasse 154 90491 Numberg TEL: +49 (0)911 593654 FAX: +49 (0)911 591256
10-8
DISTRIBUTORS
ProtecGmbH Laurinweg 1 85521 Ottobrunn TEL: +49 (0)89 609 7001 FAX: +49 (0)89 609 8170
Metronik GmbH Leonhardsweg 2 82008 Unterhaching TEL: +49 (0)89 611 080 FAX: +49 (0)89 611 6468
Metronik GmbH Siemensstrasse 4-6 68542 Heddesheim TEL: +49 (0)62 03 4701 FAX: +49 (0)62 04 45543
Metronik GmbH Lowenstrasse 37 70597 Stuttgart 70 TEL: +49 (0)711 764033 FAX: +49 (0)711 765 5181
Metronik GmbH Zurn Lonnenhohl 13 44319 Dortmund 13 TEL: +49 (0)231 217041 FAX: +49 (0)231 210799
Metronik GmbH Gottlieb-Daimler-Strasse 7 24568 Kaltenkirchen TEL: +49 (0)41 914206 FAX: +49 (0)41 914428
Metronik GmbH Liessauer Pfad 17 13503 Berlin (Heiligensee) TEL: +49 (0)30 4361219 FAX: +49 (0)30 431 5956
Metronik GmbH Grenzstrasse 26 06112 Halle TEL: +49 (0)345 823350 FAX: +49 (0)345 823346
Metronik GmbH Pilotystr. 27/2Jd 90408 Numberg TEL: +49 (0)911 363 536 FAX: +49 (0)911 353 986
GREECE
Ledar
Yani Suvermezoglu & Co.
9, L. Koromila St. GR117 45 N. Kosmos -Athens TEL:(1) 921940519242835/
9220429 FAX: (1) 9239698
INTERNATIONAL AGENTS - DISTRIBUTORS (Continued)
INDIA REPRESENTATIVE
Syratron Marketing PVT LTD 203, Copper Arch, 83, Infantry Road, Bangalore-560 001 TEL: +91 (0)80 591107
+91 (0)80 591031 FAX: +91 (0)80 569056 TLX: 0845-2997 NWLD IN.
IRELAND
REPRESENTATIVE
NETS (New England Technical Sales) The Diamond Malahide, County Dublin TEL: +353 (0)1 845 0635 FAX: +353 (0)18453625
NETS (New England Technical Sales) 5 Dalton Drive Salthill, Galway TEL: +353 (0)91 25899 FAX: +353 (0)91 24885
DISTRIBUTOR
Lyco Estuary House New Street Malahide, County Dublin TEL: +353 (0)1 845 2020 FAX: +353 (0)1 8451741
IS RAEL REPRESENTATIVE
STG International Ltd. 7, Derech Hashalom Tel-Aviv 67892 TEL: +972 (0)3 696 5231 FAX: +972 (0)3 696 5141
ITALV
Unitrode Sri Via Dei Carraci, 5 20149 Milano TEL: +39 (0)2 480 07831 FAX: +39 (0)2 480 08014
REPRESENTATIVE
Dimac Elettronica Sri Via Papa Giovanni XXlll, 25 20046 Biassono (Ml) TEL: +39 (0)39 491 445 FAX: +39 (0)39 491 773
DISTRIBUTORS
Eurelettronica Spa Via E. Fermi, 8 20090 Assago (Ml) TEL:+39 (0)2 457 841 FAX:+39 (0)2 488 34202
Fanton Bologna Sri
Via 0. Simoni, 5
40011 Anzola Dell' Emilia (BO) TEL:+39 (0)51 734 700 FAX:+39 (0)51 732 216 TELEX: 216613 FANTONB I
Fanton Firenze Sri Via Francesco Baracca, 183 50127 Firenze TEL: +39 (0)55 422 3897 FAX: +39 (0)55 4223898
Fanton Milano Sri Via Melegnano, 20 20019 Settimo Milanese (Ml) TEL: +39 (0)2 489 12963 FAX: +39 (0)2 489 13902 TELEX: 350853 FAN Ml
Fanton Electronic System Sri Via Savelli, 1 35129 Padova TEL: +39 (0)49 775 822 FAX: +39 (0)49 807 0521 TELEX: 430192 FANTON I
Fanton Torino Sri Via Cimabue, 5 10137 Torino TEL: +39 (0)11 309 7347 FAX: +39 (0)11 311 5069 TELEX: 224129 FANTON I
Fanton Roma Sri Via Rezzato, 118/122 00166 Roma TEL: +39 (0)6 309 7008 FAX: +39 (0)6 309 6736
JAPAN
lnternix Inc. Shinjuku Hamada Bldg. 7-4-7 Nishi-Shinjuku Shinjuku-Ku Tokyo 160 TEL: +81 (0)33 369 1105 FAX: +81 (0)33 366 8566
Jepico Corporation Shinjuku Dai-ichi/Seimei Bldg. Nishi-Shinjuku 2-7-1 Shinjuku-Ku Tokyo 163 TEL: +81 (0)33 348 0611 FAX: +81 (0)33 348 0623
10-9
Kanematsu Semiconductor Corp. Kyobashi Dai5 Nagaoka Bldg. 1-6-1, Shintomi 1-chome Chuo-ku Tokyo 104 TEL: +81 (0)33 551 7791 FAX: +81 (0)33 552 6096
KOREA R.O.K.
MS International Corp. CPO Box 6780 Room 1205 Haechun Bldg. 831 Yucksam-dong Kangnam-Ku, Seoul TEL: +82 (0)2 553 0901 FAX: +82 (0)2 553 0046
NETHERLANDS REPRESENTATIVE
lndel P.O. Box 1092 2340 BB Oegstegeest TEL: +31 (0) 71 170248 FAX: +31 (0) 71 156599
DISTRIBUTOR
Koning en Hartman P.O. Box 125 2600 AC Delft TEL: +31 (0)15 609906 FAX: +31 (0)15 619194
NEW ZEALAND
V.S.I. Electronics (NZ) Ltd. Private Bag Newmarket Auckland TEL: +64 (0)9 579 6603 FAX: +64 (0)9 525 0283
NORWAY REPRESENTAT/VE
Repretech Scandanavia AB Fagardal, 197 93 Bro Sweden TEL: +46 (0)8 582 431 25 FAX: +46 (0)8 582 433 58
DISTRIBUTOR
Hans H. Schive A/S Undelstadlia 27 P.O. Box 185 N-1371 Asker TEL: +47 (0)2 900900 FAX: +47 (0)2 904484
INTERNATIONAL AGENTS ·DISTRIBUTORS (Continued)
SINGAPORE
Unitrode Electronics (Singapore) PTE, Ltd. 55 Ayer Rajah Crescent Unit# 05-17/26 & 06-12/16 Singapore 0513 TEL: +65 779 2777 FAX: +65 779 4395
DISTRIBUTORS
Hamilton Electronics Pte. Ltd. No. 9 Howard Road Tat Hong Industrial Bldg. (5th Floor) Singapore 1336 TEL: +65 283 7828/7919 FAX: +65 283 7929 TELEX: RS34822 HAMIL
Desner Electronics (FE) Pte. Ltd. 42 Maetaggart Road #04-01 Maetaggart Bldg. Singapore 1336 TEL: +65 285 1566 FAX: +65 284 9466 TELEX: RS39191 DTD
SOUTH AFRICA
Electrolink (Pty) Ltd. P.O. Box 1020 Capetown 8000 TEL: +27 (0)21 215350 FAX: +27 (0)21 419 6256
SPAIN
Monolitic S.A. Avenida Hospital Militar 78-80 Entlo 08023 Barcelona TEL: +34 (0)3 2194154/016 FAX: +34 (0)3 2841193 TELEX: 08026
SWEDEN
REPRESENTATIVE
Repretech Scandinavia AB Fagardal, 197 93 Bro TEL: +46 (0)8 582 431 25 FAX: +46 (0)8 582 433 58
DISTRIBUTORS
NC Nordcomp Sweden AB P.O. Box4115 Hemvarnsgatan 13 TEL: +46 (0)8 764 6710 FAX: +46 (0)8 764 4730
SWITZERLAND ElkomAG Durisolstrasse 12 5612 Villmergen TEL: +4 t (0)57 211145 FAX: +41 (0)57 229658
TAIWAN Tai Full Technologies Corp. 4th Floor, No. 130 Nan King E. Road, Sec. 4 Taipei AOC TEL: +886 (0)2 731 0842 FAX: +886 (0)2 771 8664 DISTRIBUTOR Wanroc, Inc 8 Alley 40 Lane 629 Nei Hu Rd. Section 1 1/Floor Taipei TEL: +886 (0)2 627 9725 FAX: +886 (0)2 799 5948
THAILAND Choakchai Electronic Supplies Ltd., Part. No. 128/21-24 Thanon Atsadang Bangkok 10200 TEL: +66 (0)2 222 3921 FAX: +66 (0)2 224 7639
TURKEY Inter Inter Muhendislik Danismanlik ve Ticaret A.S. Hasircibasi Caddesi nr 55 81310 Kadikoy - Istanbul TEL: (1) 3499400 FAX: (1) 3499430/3499434
UNITED KINGDOM Unitrode (UK) Limited 6 Cresswell Park Blackheath, London SE3 9RD England TEL: +44 (0)81 318 1431 FAX: +44 (0)81 318 2549
10-10
REPRESENTATIVES
SOUTH/WEST
Albur Electronics 2 Keats Way Yateley, Camberley Surrey GU17 7YN England TEL: +44 (0)25 287 1882 FAX: +44 (0)25 2861015
MIDLANDS/NORTH
EC&E 22 Honeyborne Road Sutton Coldfield West Midlands B75 6BT England TEL: +44 (0)21 378 1128 FAX: +44 (0)21 3111426
EAST
Millfield Little Chesterford Saffron Walden Essex CB10 1UD England TEL: +44 (0)79 9530434 FAX: +44 (0)79 9531119
SCOTLAND
NETS (New England Technical Sales) 84 Hamilton Road Motherwell ML1 3BY Scotland TEL: +44 (0)69 826 5500 FAX: +44 (0)69 826 5511
DISTRIBUTORS
Bytech Components Ltd. 12A Cedarwood Chineham Business Park Basingstoke Hampshire RG24 OWD England TEL:+44(0)256707107 FAX: +44 (0) 256707162
Macro Marketing Burnham Lane Slough SL1 6LN England TEL:+44(0)628604383 FAX:+44(0)628666873
INTERNATIONAL AGENTS - DISTRIBUTORS (Continued)
Solid State Supplies Ltd. Unit 2 Eastlands Lane Paddock Wood Kent TN12 6BU TEL: +44 (0) 892 836 836 FAX: +44 (0) 892 837 837
DIE ONLY
Di-Tech Corbrook Road Chadderton Oldham OL99SD England TEL: +44 (0)61 626 3827 FAX: +44 (0)61 627 2341
UNITROOE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD.· MERRIMACK, NH 03054 TEL (603) 424-2410 ·FAX (603) 424-3460
10-11
n n INTEGRATED
~CIRCUITS
-UNITROOE
10-12
n n INTEGRATED
~CIRCUITS
-UNITRODE
Request for Additional Services
NAME COMPANY STREET ADDRESS CITY PHONE NUMBER (
TITLE/DEPT. MAIL STOP
STATE
ZIP
LITERATURE: Please send information on the following:
0 Power Supply Control Products
D Motor Control Products D Drivers, Switches, Interface Products D Additional Copy of this Data Book
0 Other _ _ _ _ _ _ _ _ _ __
OTHER D I would like to have an applications Engineer contact me concerning--------
Please mail to the Advertising Manager at the following address :
Unitrode Integrated Circuits Corp. 7 Continental Blvd. Merrimack, NH 03054-9917
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