User Manual. Prepared by: Jens Heim – TSPTC6. System Engineer GNSS. Date: C hecked by: Isaac Tejerina – TSPTC. System Engineer ASIC.
Ref: AGGA-ADSO-UM-1000485489 Issue: 01 Date: Nov 26, 2018
AGGA
AGGA-4 User Manual
Approval Information:
Name/Role:
Date:
BECKER, Thomas (OTN) / Product Assurance
May 02, 2019 03:01:07 PM GMT
LEMBKE, Erik [DE] / Project Manager
Apr 30, 2019 01:14:39 PM GMT
CADM office certifies that the above persons have signed this document by electronic validation process supported by Airbus Group tools. The current issue is the electronic copy available through Airbus Defence and Space PDM. All paper copies are for information only.
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AT7991 (AGGA-4) User Manual
Airbus DS GmbH Doc No: AGGA-ADSO-UM-1000485489 Issue: Issue 1 Updated: 26-Apr-2019 Page: 1 of 230
AT7991 (AGGA-4) User Manual
Prepared by:
Jens Heim TSPTC6 System Engineer GNSS
C hecked by:
Isaac Tejerina TSPTC System Engineer ASIC
Approved by:
Thomas Becker TOQSP1 Qualit y Assurance
Rel eased by:
Erik Lembke TSPAC3 Project Manager
Date: Date: Date: Date:
All Rights Reserved Copyright per DIN 34
AT7991 (AGGA-4) User Manual
Document Revision History
Airbus DS GmbH Doc No: AGGA-ADSO-UM-1000485489 Issue: Issue 1 Updated: 26-Apr-2019 Page: 2 of 230
Revision Issue 1
Date 26. Apr. 2019
Responsi bl e Jens Heim
Modi fi cati ons / Reasons for C hange
Initial Release (based on AGGA-4 Datasheet 1.1)
· Updat e of Section 1.1 Introduction · Added Not e about cache snooping issue to 4.9.2.3 · Added Cache Snooping Know Issue chapter 8.4.11 · SYS_CLK_DIV Clarification in chapter 6.3 · Removed min. timings from Table 6-2, covered by
ATMEL datasheet · Added new applicable document to section 1.5.1 · Added new reference document to section 1.5.2 · Added link to AGGA-4 Radiation test to 8.2 · Updat e of Section 8.4.7 · Corrected Table reference in 3.4.3.1 · Renamed space to taps in 3.4.4.4 to be consistent · Edit orial Correction in 7.4.5.17 · Corrected Code RAM description in 3.4.3.2 · Added ME/IE CarrObs/Phase to Fi gure 3-31 · Updat e of section 1.2
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Table of Contents
AT7991 (AGGA-4) User Manual
Airbus DS GmbH Doc No: AGGA-ADSO-UM-1000485489 Issue: Issue 1 Updated: 26-Apr-2019 Page: 3 of 230
1 INTRO DUC TION................................................................................................................... 12
1.1 PURPOSE.......................................................................................................................... 12 1.2 OPEN POINTS..................................................................................................................... 12 1.3 NOTATION........................................................................................................................ 12 1.4 ACRONYMS....................................................................................................................... 12 1.5 REFERENCES ..................................................................................................................... 14
1.5.1 Applicable Documents.................................................................................................................................... 14 1.5.2 Reference Documents...................................................................................................................................... 15
2 AGGA-4 OVERVIEW ............................................................................................................. 16
3 GNSS CORE.......................................................................................................................... 17
3.1 INPUT MODULE.................................................................................................................. 18 3.1.1 Input Format Converter (IFC) ....................................................................................................................... 21 3.1.2 Digital Down Converter (DDC) Module....................................................................................................... 22
3.1.2.1 T wo to Five Converter ....................................................................................................................................22 3.1.2.2 DDC I/Q Mixer Stage .....................................................................................................................................23 3.1.2.3 Decimating FIR Filter .....................................................................................................................................25 3.1.2.4 Re-Quantizer ..................................................................................................................................................26
3.1.3 Real to Complex Converter (R2C)................................................................................................................. 27
3.1.3.1 R2C I/Q Mixer Stage ......................................................................................................................................28 3.1.3.2 FIR Filter........................................................................................................................................................28 3.1.3.3 R2C Re-Quantizer...........................................................................................................................................30
3.1.4 D/A Converter................................................................................................................................................. 31 3.2 POWER LEVEL DETECTOR ..................................................................................................... 32
3.2.1 Power Level Detector 5I................................................................................................................................. 32 3.2.2 Power Level Detector IQ................................................................................................................................ 33
3.2.2.1 General Overview...........................................................................................................................................33 3.2.2.2 Insights to Pre-Accumulator and Re-Quantization............................................................................................34
3.3 DIGITAL BEAM FORMING (DBF) ............................................................................................. 37 3.4 CHANNEL MATRIX WITH CHANNELS ........................................................................................ 40
3.4.1 Input Selector................................................................................................................................................... 41 3.4.2 Final Down Converter (FDC)........................................................................................................................ 41
3.4.2.1 Carrier Generator............................................................................................................................................41 3.4.2.2 Carrier Mixer..................................................................................................................................................42
3.4.3 Code Generator Unit ...................................................................................................................................... 43
3.4.3.1 Very Flexible Co de Generator (VFCG) ............................................................................................................46 3.4.3.2 Primary Code Memory....................................................................................................................................49 3.4.3.3 Secondary Code Memory ................................................................................................................................50 3.4.3.4 BOC Processing..............................................................................................................................................51 3.4.3.5 Code Rate Generator.......................................................................................................................................52 3.4.3.6 Code Generator Unit Configuration Examples: ................................................................................................54
3.4.4 Code Delay Line Unit (CDLU) ...................................................................................................................... 58
3.4.4.1 Code Input Select............................................................................................................................................59 3.4.4.2 Code Swap .....................................................................................................................................................59 3.4.4.3 Delay Line Clock Select..................................................................................................................................59 3.4.4.4 Delay Line......................................................................................................................................................60 3.4.4.5 Code Output Select .........................................................................................................................................61
3.4.5 Correlator Unit ............................................................................................................................................... 61
3.4.5.1 Multiplier .......................................................................................................................................................62 3.4.5.2 Integration Counter .........................................................................................................................................64 3.4.5.3 Continuous Counter ........................................................................................................................................64 3.4.5.4 Long Epoch (LE) ............................................................................................................................................64 3.4.5.5 Integrator........................................................................................................................................................65 3.4.5.6 Data Collect....................................................................................................................................................65
3.4.6 Aiding Unit ...................................................................................................................................................... 66
3.4.6.1 Code Aiding Unit............................................................................................................................................66 3.4.6.2 Carrier Aiding Unit .........................................................................................................................................68
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3.4.6.3 Aiding Clock Generation.................................................................................................................................70 3.4.6.4 Behaviour Examples.......................................................................................................................................71
3.4.7 Observables..................................................................................................................................................... 72
3.4.7.1 Integration Epoch Observables ........................................................................................................................73 3.4.7.2 Measurement Epoch Observables ....................................................................................................................74 3.4.7.3 DMA T ransfer of GNSS Observables ..............................................................................................................74 3.4.7.4 T iming Notes about GNSS Observables...........................................................................................................75
3.4.8 Channel Slaving Concepts.............................................................................................................................. 76
3.4.8.1 Hardware/Software Slaving .............................................................................................................................76 3.4.8.2 Examples........................................................................................................................................................77
3.5 TIME BASE GENERATOR ....................................................................................................... 78 3.5.1 Epoch Clock (EC) ........................................................................................................................................... 78 3.5.2 Measurement Epoch (ME).............................................................................................................................. 78 3.5.3 Pulse Per Second (PPS).................................................................................................................................. 79 3.5.4 Synchronisation of ME and PPS.................................................................................................................... 79 3.5.5 Instrument Measurement Time (IMT)............................................................................................................ 79 3.5.6 External Clock (ExtClk) Interface.................................................................................................................. 80 3.5.7 Delay Line Clock Sync.................................................................................................................................... 80
3.6 ANTENNA SWITCH CONTROLLER (ASC) .................................................................................... 81 3.6.1 Antenna Switch Epoch (ASE) ......................................................................................................................... 81 3.6.2 Antenna Switch Sequencer.............................................................................................................................. 81 3.6.3 Antenna Switch Correlation Results.............................................................................................................. 82
3.7 AMBA HIGH PERFORMANCE BUS (AHB) INTERFACE ................................................................... 84
4 PROC ESSOR MODULE.......................................................................................................... 85
4.1 INTEGER UNIT ................................................................................................................... 85 4.1.1 Instruction Timing........................................................................................................................................... 85
4.2 FLOATING POINT UNIT (FPU)................................................................................................. 86 4.2.1 Floating-point number formats...................................................................................................................... 86 4.2.2 FP operations.................................................................................................................................................. 86 4.2.3 Exceptions........................................................................................................................................................ 88 4.2.4 Rounding.......................................................................................................................................................... 88 4.2.5 Denormalized numbers................................................................................................................................... 88 4.2.6 Non-standard Mode........................................................................................................................................ 88 4.2.7 NaNs.................................................................................................................................................................89 4.2.8 Timing ..............................................................................................................................................................89 4.2.9 GRFPC - GRFPU Control Unit..................................................................................................................... 89 4.2.10 Floating-Point register file............................................................................................................................. 89 4.2.11 Floating-Point State Register (FSR).............................................................................................................. 89 4.2.12 Floating-Point Exceptions and Floating-Point Deferred-Queue................................................................ 90
4.3 EXCEPTIONS...................................................................................................................... 90 4.4 WATCH-POINTS.................................................................................................................. 91 4.5 POWER DOWN REGIST ER ...................................................................................................... 91 4.6 LEON CONFIGURATION REGISTER............................................................................................ 92 4.7 FAULT TOLERANT FEATURES.................................................................................................. 92
4.7.1 Register file protection.................................................................................................................................... 92 4.7.2 External memory EDAC ................................................................................................................................. 92 4.7.3 Cache memory protection............................................................................................................................... 93 4.8 MULTIPLICATION/DIVISION INSTRUCTIONS ................................................................................ 93 4.9 CACHE SUB-SYSTEM ........................................................................................................... 93 4.9.1 Instruction Cache............................................................................................................................................ 95
4.9.1.1 Operation........................................................................................................................................................95 4.9.1.2 Instruction cache tag .......................................................................................................................................95
4.9.2 Data Cache...................................................................................................................................................... 96
4.9.2.1 Operation........................................................................................................................................................96 4.9.2.2 Write buffer ....................................................................................................................................................96 4.9.2.3 Data Cache Snooping......................................................................................................................................96 4.9.2.4 Data Cache T ag...............................................................................................................................................96
4.9.3 Cache Flushing ............................................................................................................................................... 97 4.9.4 Diagnostic Cache access................................................................................................................................ 97 4.9.5 Cache Freeze Alert.......................................................................................................................................... 97
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4.10 BYTE/HALF WORD ACCESSES ................................................................................................ 97 4.11 MEMORY CONTROLLER ........................................................................................................ 99
4.11.1 Attaching an external memory controller...................................................................................................... 99 4.11.2 8-bit PROM/EEPROM and SRAM access..................................................................................................... 99 4.11.3 8-bit IO access................................................................................................................................................. 99 4.12 INTERRUPT CONTROLLER.....................................................................................................100
4.12.1 Primary Interrupt Controller (PIC).............................................................................................................100
4.12.1.1 Pending Interrupt Cleared by T icc .............................................................................................................100
4.12.2 GNSS Interrupt Controller (GIC) ................................................................................................................101 4.12.3 Communication Interrupt Controller (CIC)................................................................................................102 4.13 TIMER UNIT .....................................................................................................................103 4.14 WRITE PROTECTION UNIT ....................................................................................................104
4.14.1 Overview........................................................................................................................................................104 4.14.2 Address/Mask Write Protection ...................................................................................................................104 4.14.3 Start/End Address Write Protection.............................................................................................................105 4.14.4 Generation of Write Protection....................................................................................................................105 4.15 AHB STATUS REGISTER ......................................................................................................105 4.16 HARDWARE DEBUG SUPPORT UNIT.........................................................................................106
4.16.1 Overview........................................................................................................................................................106 4.16.2 DSU Memory Map ........................................................................................................................................107 4.16.3 Trace Buffer...................................................................................................................................................107 4.16.4 DSU Control Register...................................................................................................................................109 4.16.5 DSU (Hardware) Breakpoints......................................................................................................................109 4.16.6 Instruction (Software) Breakpoints..............................................................................................................109 4.16.7 DSU Trap Register........................................................................................................................................109 4.16.8 Single Stepping..............................................................................................................................................109 4.16.9 Booting from DSU.........................................................................................................................................109
5 INTERFAC E MODULES........................................................................................................110
5.1 UART............................................................................................................................110 5.1.1 Transmitter Operation..................................................................................................................................110 5.1.2 Receiver Operation .......................................................................................................................................111 5.1.3 Baud Rate Generation...................................................................................................................................112 5.1.4 General UART Rules.....................................................................................................................................112 5.1.5 Error Handling..............................................................................................................................................112
5.1.5.1 Framing Error...............................................................................................................................................112 5.1.5.2 Parity Error...................................................................................................................................................112 5.1.5.3 Overrun in Receiver......................................................................................................................................113 5.1.5.4 Break Received.............................................................................................................................................113 5.1.5.5 T imeout........................................................................................................................................................113
5.1.6 Internal Loopback.........................................................................................................................................113 5.2 SPACEWIRE .....................................................................................................................114
5.2.1 SpaceWire Module........................................................................................................................................114 5.2.2 Data Transfer................................................................................................................................................114 5.2.3 SpW Interrupts...............................................................................................................................................115 5.3 MIL-BUS ........................................................................................................................116
5.3.1 General description.......................................................................................................................................116 5.3.2 Architectural description..............................................................................................................................116
5.3.2.1 1553B bus coupling module architecture........................................................................................................116 5.3.2.2 IP1553 internal architecture...........................................................................................................................117
5.3.3 IP1553 Initialization.....................................................................................................................................117
5.3.3.1 APB Interface...............................................................................................................................................118 5.3.3.2 Remote T erminal (RT ) mode definition .........................................................................................................119 5.3.3.3 IP1553 System interface................................................................................................................................132
5.4 DSU COMMUNICATION LINK ................................................................................................136 5.4.1 DSU UART Operation ..................................................................................................................................136 5.4.2 DSU UART Baud rate generation (not available in DSU SpaceWire operation) ....................................137 5.4.3 DSU SpaceWire Operation...........................................................................................................................137
5.5 SERIAL PERIPHERAL INTERFACE (SPI) .....................................................................................138 5.6 16-BIT I/OPORT ................................................................................................................139
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5.7 GPIO.............................................................................................................................139 5.8 SERIAL GENERAL PURPOSE OUTPUT (SGPO).............................................................................140
6 SYSTEM SUPPORT FUNC TIO NS ...........................................................................................141
6.1 FFT MODULE ...................................................................................................................141 6.1.1 FFT-AHB interface.......................................................................................................................................141 6.1.2 FFT Handling................................................................................................................................................141
6.2 CRC MODULE ..................................................................................................................142 6.3 EEPROM SUPPORT FUNCTION ..............................................................................................143 6.4 CLOCK DISTRIBUTION.........................................................................................................145
6.4.1 System Clock (SysClk) Divider.....................................................................................................................146 6.4.2 GNSS Core Clock (CoreClk) Generation....................................................................................................146 6.4.3 Mil-Bus Clock Generation............................................................................................................................146 6.4.4 System Clock (SysClk) Generation ..............................................................................................................146 6.4.5 SPI Clock (SPIClk) Generation....................................................................................................................147 6.4.6 SpWClock Generation..................................................................................................................................147 6.4.7 PLL Lock Status............................................................................................................................................147 6.5 RESET MECHANISMS ..........................................................................................................148 6.5.1 Power On Reset.............................................................................................................................................148 6.5.2 Watchdog Reset.............................................................................................................................................148 6.5.3 AGGA-4 Reset ...............................................................................................................................................149 6.5.4 GNSS Reset....................................................................................................................................................149 6.5.5 SW Reset ........................................................................................................................................................149 6.5.6 SpW Reset ......................................................................................................................................................149 6.5.7 Mil-Bus Reset.................................................................................................................................................150 6.5.8 UART Reset....................................................................................................................................................150 6.5.9 Mil-Bus triggered Reset................................................................................................................................150 6.5.10 Reset Status Register.....................................................................................................................................150 6.5.11 Processor reset..............................................................................................................................................150 6.6 AMBA BUS ....................................................................................................................151 6.6.1 AHB priorities...............................................................................................................................................151 6.6.2 AHB/APB bus access duration.....................................................................................................................151 6.7 TEST SUPPORT PINS............................................................................................................152 6.7.1 I/Q Data.........................................................................................................................................................152 6.7.2 IntEpoch and Code Out ................................................................................................................................152 6.7.3 IMT_12...........................................................................................................................................................152
7 PROGRAMMING .................................................................................................................153
7.1 OVERALL ADDRESS MAP .....................................................................................................153 7.2 APB ADDRESS MAP (PROCESSOR, INTERFACE AND SYSTEM SUPPORT)..............................................153
7.2.1 Overview........................................................................................................................................................153 7.2.2 LEON and Memory Interface Registers.......................................................................................................157
7.2.2.1 MCFG1 (Memory Configuration Register 1)..................................................................................................157 7.2.2.2 MCFG2 (Memory Configuration Register 2)..................................................................................................158 7.2.2.3 MCFG3 (Memory Configuration Register 3)..................................................................................................159 7.2.2.4 AHBFailin gAddress ......................................................................................................................................159 7.2.2.5 AHBStatus....................................................................................................................................................159 7.2.2.6 CacheCtrl .....................................................................................................................................................160 7.2.2.7 PowerDown ..................................................................................................................................................161 7.2.2.8 LeonConfig...................................................................................................................................................161
7.2.3 Timer Registers.............................................................................................................................................162
7.2.3.1 T imerN_Counter...........................................................................................................................................162 7.2.3.2 T imerN_Reload ............................................................................................................................................162 7.2.3.3 T imerN_Ctrl.................................................................................................................................................162 7.2.3.4 T imerPrescaleCounter...................................................................................................................................163 7.2.3.5 T imerPrescaleReload ....................................................................................................................................163
7.2.4 Primary Interrupt Controller Registers.......................................................................................................163
7.2.4.1 PrimIntMaskAndPrio....................................................................................................................................163 7.2.4.2 PrimIntPending.............................................................................................................................................164 7.2.4.3 PrimIntForce.................................................................................................................................................165 7.2.4.4 PrimIntClear .................................................................................................................................................166
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7.2.5 PIO Registers.................................................................................................................................................166
7.2.5.1 PIO_IO.........................................................................................................................................................166 7.2.5.2 PIODirection ................................................................................................................................................167 7.2.5.3 PIOIntConfig................................................................................................................................................168
7.2.6 Watchdog Registers.......................................................................................................................................169
7.2.6.1 WdogPrescale ...............................................................................................................................................169 7.2.6.2 WdogReload .................................................................................................................................................169 7.2.6.3 WdogSel.......................................................................................................................................................169 7.2.6.4 WdogWriteEnable.........................................................................................................................................169
7.2.7 Debug link (UART and SPW) Registers......................................................................................................170
7.2.7.1 DSU_UART _Status......................................................................................................................................170 7.2.7.2 DSU_UART _SpW_Ctrl................................................................................................................................170 7.2.7.3 DSU_UART _Scaler ......................................................................................................................................170
7.2.8 Write Protect Registers.................................................................................................................................171
7.2.8.1 WriteProtectN...............................................................................................................................................171 7.2.8.2 WriteProtectStartAddressN ...........................................................................................................................171 7.2.8.3 WriteProtectEndAddressN ............................................................................................................................171
7.2.9 GPIO Registers..............................................................................................................................................171
7.2.9.1 GPIO_Status.................................................................................................................................................171 7.2.9.2 GPIO_Output................................................................................................................................................172 7.2.9.3 GPIO_Direction............................................................................................................................................172
7.2.10 Reset and Miscellaneous Registers..............................................................................................................172
7.2.10.1 ResetStatus ...............................................................................................................................................172 7.2.10.2 SWRe setEnable ........................................................................................................................................173 7.2.10.3 SWRe setExecute.......................................................................................................................................173 7.2.10.4 MilBusRT Address ....................................................................................................................................173 7.2.10.5 AGGA4 Version ........................................................................................................................................173
7.2.11 Communication Interrupt Controller Registers..........................................................................................173
7.2.11.1 CIC_Mask ................................................................................................................................................173 7.2.11.2 CIC_Pending ............................................................................................................................................174 7.2.11.3 CIC_Clear ................................................................................................................................................174
7.2.12 SPI Registers.................................................................................................................................................175
7.2.12.1 SPI_StatusAndCtrl....................................................................................................................................175 7.2.12.2 SPI_ClkDivider ........................................................................................................................................176 7.2.12.3 SPI_Tx .....................................................................................................................................................176 7.2.12.4 SPI_Rx .....................................................................................................................................................176
7.2.13 CRC Unit Registers.......................................................................................................................................176
7.2.13.1 CRCLFSR ................................................................................................................................................176 7.2.13.2 CRCPolynom............................................................................................................................................176 7.2.13.3 CRCFinalXOR..........................................................................................................................................177 7.2.13.4 CRCCtrl ...................................................................................................................................................177 7.2.13.5 CRCStartAddress......................................................................................................................................177 7.2.13.6 CRCEndAddress.......................................................................................................................................177 7.2.13.7 CRCCurrentAddress .................................................................................................................................177
7.2.14 MILBUS Registers.........................................................................................................................................178
7.2.14.1 C53CF......................................................................................................................................................178 7.2.14.2 C53EMBA................................................................................................................................................178 7.2.14.3 C53CDST .................................................................................................................................................178 7.2.14.4 C53NIT ....................................................................................................................................................179 7.2.14.5 C53EIT.....................................................................................................................................................179 7.2.14.6 C53RIT ....................................................................................................................................................179 7.2.14.7 C53RT I ....................................................................................................................................................180 7.2.14.8 C53TTI.....................................................................................................................................................180
7.2.15 Serial General Purpose Output (SGPO) Registers.....................................................................................180
7.2.15.1 SGPO_T x.................................................................................................................................................180 7.2.15.2 SGPO_ Status............................................................................................................................................180 7.2.15.3 SGPO_Ctrl ...............................................................................................................................................180 7.2.15.4 SGPO_ Scaler ............................................................................................................................................181
7.2.16 UART Registers.............................................................................................................................................181
7.2.16.1 UART n_Tx_SAP......................................................................................................................................181 7.2.16.2 UART n_Tx_EAP......................................................................................................................................181 7.2.16.3 UART n_Tx_CAP .....................................................................................................................................181 7.2.16.4 UART n_Rx_SAP......................................................................................................................................181 7.2.16.5 UART n_Rx_EAP .....................................................................................................................................181
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7.2.16.6 7.2.16.7
UART n_Rx_CAP.....................................................................................................................................182 UART n_Status..........................................................................................................................................182
7.2.16.8 UART n_Ctrl.............................................................................................................................................182
7.2.16.9 UART n_Scaler .........................................................................................................................................183
7.2.16.10 UART _Reset ............................................................................................................................................183
7.2.17 Clock, PLL and EEPROM Control Registers.............................................................................................183
7.2.17.1 GNSSCoreClkCtrl.....................................................................................................................................183
7.2.17.2 7.2.17.3
MilBusClk Ctrl..........................................................................................................................................183 P LLSt at us................................................................................................................................................. 1 8 3
7.2.17.4 EEPROM_StatusAndCtrl..........................................................................................................................184
7.2.18 Spacewire Registers......................................................................................................................................184
7.2.18.1 SpWn_StatusAndCtrl................................................................................................................................184
7.2.18.2 SpWn_Tx_SAP ........................................................................................................................................184
7.2.18.3 SpW_T x_EAP..........................................................................................................................................185
7.2.18.4 7.2.18.5
Sp W n _ Tx _ CAP ........................................................................................................................................ 1 8 5 Sp W n _ Tx _ Rx _ Con fig............................................................................................................................... 1 8 5
7.2.18.6 SpWn_Rx_SAP ........................................................................................................................................185
7.2.18.7 SpWn_Rx_EAP........................................................................................................................................185
7.2.18.8 SpWn_Rx_CAP........................................................................................................................................186
7.2.18.9 SpW_Module Config .................................................................................................................................186
7.2.18.10 SpW_ModuleT imeCtrl..............................................................................................................................186
7.2.18.11 SpW_ModuleT imeCode ............................................................................................................................186
7.2.18.12 SpW_ModuleIntMask ...............................................................................................................................186
7.2.18.13 SpW_ModuleIntStatus ..............................................................................................................................187
7.2.18.14 SpW_ModuleIntClear ...............................................................................................................................188
7.3 DSU ADDRESS MAP ...........................................................................................................189
7.3.1 DSU Overview...............................................................................................................................................189
7.3.1.1 DSU_Ctrl .....................................................................................................................................................190
7.3.1.2 T raceBufferCtrl.............................................................................................................................................191 7.3.1.3 T imeT agCounter...........................................................................................................................................191
7.3.1.4 AHB_BreakAddressN ...................................................................................................................................192
7.3.1.5 AHB_MaskN................................................................................................................................................192
7.3.1.6 DSU_T rap ....................................................................................................................................................192
7.4 GNSS ADDRESS MAP .........................................................................................................192
7.4.1 GNSS Base Addresses...................................................................................................................................192
7.4.2 Input Module Registers.................................................................................................................................193
7.4.2.1 InputModuleCtrl ...........................................................................................................................................194
7.4.2.2 DDCMainPhaseInc .......................................................................................................................................194
7.4.2.3 DDCMainFIRQuantT hres.............................................................................................................................194
7.4.2.4 DDCAuxPhaseInc.........................................................................................................................................194
7.4.2.5 DDCAuxFIRQuantT hres...............................................................................................................................195
7.4.2.6 DACtrl .........................................................................................................................................................195
7.4.3 Power Level Detector Registers...................................................................................................................195
7.4.3.1 PLD5IInputSel..............................................................................................................................................196
7.4.3.2 PLD5ICtrl.....................................................................................................................................................196
7.4.3.3 PLDIQInputSel.............................................................................................................................................196
7.4.3.4 PLDIQPreAccCtrl.........................................................................................................................................196
7.4.3.5 PLDIQCtrl....................................................................................................................................................197
7.4.3.6 PLD Accumulation Registers.........................................................................................................................197
7.4.4 Channel Matrix Registers.............................................................................................................................197
7.4.4.1 ChActivation0...............................................................................................................................................198
7.4.4.2 ChActivation1...............................................................................................................................................198
7.4.4.3 DBFInputSel.................................................................................................................................................198
7.4.4.4 EpochClkDiv................................................................................................................................................198
7.4.4.5 MESettings...................................................................................................................................................199
7.4.4.6 PPSSettings ..................................................................................................................................................199
7.4.4.7 AntSwitchCtrl...............................................................................................................................................199
7.4.4.8 ExtClkSettings..............................................................................................................................................199
7.4.4.9 ExtClkCnt.....................................................................................................................................................200
7.4.4.10 ExtClkCntLatched.....................................................................................................................................200
7.4.4.11 IMT_LSW ................................................................................................................................................200
7.4.4.12 IMT_MSW ...............................................................................................................................................200
7.4.4.13 7.4.4.14
ME_IMT _LSW.........................................................................................................................................200 ME_IMT _MSW .......................................................................................................................................200
7.4.4.15 PPS_IMT _LSW........................................................................................................................................200
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7.4.4.16 PPS_IMT _MSW.......................................................................................................................................201 7.4.4.17 ASE_IMT _LSW .......................................................................................................................................201 7.4.4.18 ASE_IMT _MSW ......................................................................................................................................201 7.4.4.19 PLD_5I_IMT_LSW ..................................................................................................................................201 7.4.4.20 PLD_5I_IMT_MSW .................................................................................................................................201 7.4.4.21 PLD_IQ_IMT _LSW .................................................................................................................................201 7.4.4.22 PLD_IQ_IMT _MSW ................................................................................................................................201 7.4.4.23 AUT _IMT _LSW ......................................................................................................................................201 7.4.4.24 AUT _IMT _MSW .....................................................................................................................................202 7.4.4.25 T estSettings..............................................................................................................................................202
7.4.5 Channel Registers.........................................................................................................................................202
7.4.5.1 ChannelCtrl..................................................................................................................................................203 7.4.5.2 CarrSwFreq ..................................................................................................................................................204 7.4.5.3 CarrSwShift ..................................................................................................................................................204 7.4.5.4 Code SwFre q .................................................................................................................................................204 7.4.5.5 Code SwShift.................................................................................................................................................205 7.4.5.6 NCOSettings.................................................................................................................................................205 7.4.5.7 Code GenUnitCtrl..........................................................................................................................................205 7.4.5.8 PrimCodeRam1Ctrl.......................................................................................................................................206 7.4.5.9 PrimCodeRam2Ctrl.......................................................................................................................................206 7.4.5.10 Sec CodeRam1Ctrl.....................................................................................................................................207 7.4.5.11 Sec CodeRam2Ctrl.....................................................................................................................................207 7.4.5.12 VFCGExtTaps..........................................................................................................................................207 7.4.5.13 VFCGInit .................................................................................................................................................207 7.4.5.14 VFCGLength ............................................................................................................................................208 7.4.5.15 DelayLineCtrl...........................................................................................................................................208 7.4.5.16 CorrUnitCtrl.............................................................................................................................................208 7.4.5.17 IntCountCtrl .............................................................................................................................................209 7.4.5.18 ContCntOffset...........................................................................................................................................209 7.4.5.19 AidingUnitCtrl..........................................................................................................................................209 7.4.5.20 CarrAidFreq..............................................................................................................................................210 7.4.5.21 CarrAidAcc ..............................................................................................................................................210 7.4.5.22 CodeAidFreq ............................................................................................................................................210 7.4.5.23 CodeAidAcc .............................................................................................................................................210 7.4.5.24 LoopState .................................................................................................................................................210 7.4.5.25 IE_IMT_LSW...........................................................................................................................................211 7.4.5.26 IE_ValueEE_I...........................................................................................................................................211 7.4.5.27 IE_ValueEE_Q .........................................................................................................................................211 7.4.5.28 IE_ValueE_I .............................................................................................................................................211 7.4.5.29 IE_ValueE_Q ...........................................................................................................................................211 7.4.5.30 IE_ValueP_I .............................................................................................................................................211 7.4.5.31 IE_ValueP_Q............................................................................................................................................212 7.4.5.32 IE_ValueL_I .............................................................................................................................................212 7.4.5.33 IE_ValueL_Q ...........................................................................................................................................212 7.4.5.34 IE_ValueLL_I...........................................................................................................................................212 7.4.5.35 IE_ValueLL_Q .........................................................................................................................................212 7.4.5.36 DataCollect...............................................................................................................................................212 7.4.5.37 IE_CodeFreq ............................................................................................................................................213 7.4.5.38 IE_CarrFreq..............................................................................................................................................213 7.4.5.39 IE_CarrObsPhase......................................................................................................................................213 7.4.5.40 IE_ContCount...........................................................................................................................................213 7.4.5.41 IE_CodePhase...........................................................................................................................................213 7.4.5.42 ME_IMT _LSW.........................................................................................................................................213 7.4.5.43 ME_CarrObsPhase....................................................................................................................................213 7.4.5.44 ME_IntCount............................................................................................................................................214 7.4.5.45 ME_ContCount.........................................................................................................................................214 7.4.5.46 ME_CodePhase.........................................................................................................................................214 7.4.5.47 GNSS DMA Ctrl.......................................................................................................................................214 7.4.5.48 GNSS_ DMAStartAddr..............................................................................................................................215 7.4.5.49 GNSS_ DMAEndAddr ...............................................................................................................................215 7.4.5.50 GNSS_ DMACurAddr ...............................................................................................................................215
7.4.6 Channel RAM Address Map.........................................................................................................................215
7.4.6.1 PrimaryRAM1 ..............................................................................................................................................216 7.4.6.2 PrimaryRAM2 ..............................................................................................................................................216 7.4.6.3 SecondaryRAM1 ..........................................................................................................................................216 7.4.6.4 SecondaryRAM2 ..........................................................................................................................................217
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7.4.7 GNSS Interrupt Controller Registers...........................................................................................................217
7.4.7.1 GIC_Mask0 ..................................................................................................................................................218 7.4.7.2 GIC_Mask1 ..................................................................................................................................................218 7.4.7.3 GIC_Prio0 ....................................................................................................................................................219 7.4.7.4 GIC_Prio1 ....................................................................................................................................................219 7.4.7.5 GIC_Pend0 ...................................................................................................................................................219 7.4.7.6 GIC_Pend1 ...................................................................................................................................................219 7.4.7.7 GIC_ Clear0 ..................................................................................................................................................220 7.4.7.8 GIC_ Clear1 ..................................................................................................................................................220 7.4.7.9 GIC_QueueLo w............................................................................................................................................221 7.4.7.10 GIC_QueueHigh .......................................................................................................................................221 7.4.7.11 GIC_Queue Status .....................................................................................................................................221
7.5 FFT ADDRESS MAP............................................................................................................223
7.5.1 FFT RAM and Registers...............................................................................................................................223
7.5.1.1 FFT Ctrl........................................................................................................................................................223 7.5.1.2 FFT Value .....................................................................................................................................................223
8 MISC ELLANEO US ...............................................................................................................224
8.1 IMPLEMENTATION LOSSES....................................................................................................224 8.2 RADIATION MITIGATION......................................................................................................225
8.2.1 Flip Flops.......................................................................................................................................................225 8.2.2 RAM's............................................................................................................................................................225 8.2.3 TMR................................................................................................................................................................225
8.2.3.1 Watchdog T MR............................................................................................................................................225 8.2.3.2 AGGA-4 Re set T MR ....................................................................................................................................225 8.2.3.3 GNSS CoreClk Sel T MR................................................................................................................................225 8.2.3.4 Sec ure Lock T MR.........................................................................................................................................226
8.3 SYNCHRONIZATION OF MULTIPLE AGGA DEVICES.......................................................................226 8.4 KNOWN IMPLEMENT AT ION ISSUES AND SUGGEST ED WORK AROUNDS ..............................................227
8.4.1 GNSS Interrupt Queue Initialization ...........................................................................................................227 8.4.2 Cache Freeze Alert........................................................................................................................................227 8.4.3 Pending Interrupt Cleared by Ticc..............................................................................................................227 8.4.4 Reset and Clock Issue...................................................................................................................................227 8.4.5 Start of Code Generators..............................................................................................................................228 8.4.6 SpaceWire RX DMA loss of EOP and data when packets arrive very close.............................................228 8.4.7 Data Loss when utilizing both UART's in parallel.....................................................................................229 8.4.8 GNSS Code Shift error by changing mode..................................................................................................229 8.4.9 GNSS AHB Slave initilization.......................................................................................................................229 8.4.10 Access to non-exisiting GNSS code memories............................................................................................229 8.4.11 Cache Snooping Problem.............................................................................................................................230
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Contributions
This document cont ains cont ribut ions by · Deimos Port ugal · Gust avo López-Risueño (ESA) · Isaac Tejerina (Airbus DS) · Jens Heim (Airbus DS) · Josep Rosello (ESA) · Roland Weigand (ESA) · Paul Rast et t er (Airbus DS) · RUAG Aust ria · St ephan Fischer (Airbus DS)
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1 Introduction
1.1 Purpose
The purpose of this document is to describe how t he AGGA-4 works and how it s feat ures can be used by soft ware. Please be aware that this document complements the ATMEL AT7991 datasheet. Timings, Electrical and Mechanical specificat ions as well as pinout is given in t he ATMEL dat asheet . In case t here is overlap, t he ATMEL dat asheet shall prevail.
Note: Usually the description in t he following chapt ers only want s t o give a descript ion of how t he individual funct ional blocks work. It typically does not state every detail how e.g. a bit field can be programmed. This information is list ed in the programming section of the corresponding functional block. Therefore it is recommended in order to get t he full picture of a functional block to look at bot h informat ion sources, t he funct ional descript ion as well t he programming table. The user is also advised to read chapter 8.4 Known Implement at ion Issues and Suggest ed Work Arounds before act ually making use of t he AGGA-4.
The hist ory of t he development is det ailed in [RD-09].
1.2 Open Points
The following points are coming out of the AGGA-4 ASIC Validation. Before usage of these functions, Airbus shall be cont act ed.
1. Phase missaligment bet ween DDC main and DDC aux 2. Real t o Complex FIR Filt er 3. Dual UART operat ion
1.3 Notation
Normal Times New Roman font is used in t his document . When Italics and Capital and Small letters are used it refers to a register (e.g. DACtrl) or to a bitfield in a register or t o an int ernal clock domain (e.g. CoreClk, HalfSampleClk, SysClk). When Italics and only Capit al let t ers are used it refers t o a pin (e.g. EXT_SYS_CLK). Somet imes Bol d is used t o highlight somet hing
1.4 Acronyms
A/D ADC AGC AGGA AHB Alt BOC AMBA APB ASC ASE ASEI ASEO ASIC
Analogue t o Digit al A/D Convert er Aut omat ic Gain Cont rol Advanced GPS Galileo ASIC AMBA High Performance Bus Alt ernat ive BOC Advanced Microcont roller Bus Archit ect ure Advanced Peripheral Bus Ant enna Swit ch Cont rol Ant enna Swit ch Epoch Ant enna Swit ch Epoch Input Ant enna Swit ch Epoch Out put Applicat ion Specific Int egrat ed Circuit
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ATPG Aut omat ed Test Pat t ern Generat ion
AUT Aiding Unit Trigger
BIST Build In Self Test
BOC Binary Offset Carrier
CBOC Complement ary BOC
CDL Code Delay Line
CRC Cyclic Redundancy Check
D/A Digit al t o Analogue
DBF Digit al Beam Forming
DDC Digit al Down Conversion
DMA Direct Memory Access
EC
Epoch Clock
EDAC Error Det ect ion And Correct ion
FDC Final Down Convert er
FE
Front End
FFT Fast Fourier Transform
FIFO First In First Out
FIT
Failure in Time
FP
Float ing Point
FPU Float ing Point Unit
GNSS Global Navigat ion Sat ellit e Syst em
GPIO General Purpose Input / Out put
GRFPU (Cobham) Gaisler Research Float ing Point Unit
I /O Input / Out put
I/F
Int erface
IE
Int egrat ion Epoch
IF
Int ermediat e Frequency
IFC
Input Format Convert er
IM
Input Module
IMT Inst rument Measurement Time
IMU Inert ial Measurement Unit
IPN Int ernal Problem Not ice
JTAG Joint Test Act ion Group
LE
Long Epoch
LFSR Linear Feedback Shift Regist er
LSB Least Significant Bit
LUT Look Up Table
ME
Measurement Epoch
MEI Measurement Epoch Input
MEO Measurement Epoch Out put
MILBUS MIL-STD-1553B
MSB Most Significant Bit
MUX Mult iplexer
NCO Numerically Cont rolled Oscillat or
PIC
Primary Int errupt Cont roller
PLD Power Level Det ect or
PPS Pulse Per Second
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PPSI Pulse Per Second Input
PPSO Pulse Per Second Out put
PROM Programmable Read Only Memory
PVT Posit ion Velocit y Time
R2C Real t o Complex Convert er
RF
Radio Frequency
SCK Serial Clock
SCKM SCK Mast er
SCKS SCK Slave
SDRAM Synchronous dynamic random access memory
SEU Single Event Upset
SGPO Serial General Purpose Out put
SPI
Serial Peripheral Int erface
SRAM St at ic Random Access Memory
SV
Space Vehicle
TBG Time Based Generat or
TMBOC Time Mult iplexed BOC
UART Universal asynchronous receiver/t ransmit t er
VFCG Very Flexible Code Generat or
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1.5 References
1.5.1 Applicable Documents
Id [AD-01]
[AD-02] [AD-03]
Docu m e n t
The SPARC Architecture Manual ht tp://sparc.org/wp-content/uploads/2014/01/v8.pdf.gz
Cobham Gaisler Floating Point Unit (GRFPU) Manual ht tp://gaisler.com/doc/grfpu_product_sheet.pdf
AGGA-3 Technical Note, Implementation Loss Analysis, Issue 1.0, 04. Nov. 2004
[AD-04] ATMEL AT7991 Datasheet [AD-05] AGGA-4 Radiat ion Test Report
Re f e re n ce
AGGA3- AST D- T N- 0001 lat est APL/DOC/2018/0625 (latest)
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1.5.2 Reference Documents
Id
Docu m e n t
Re f e re n ce
[RD-01]
" Galileo Open Service Signal-In-Space Interface Control Document, Draft 0 (GAL OS SIS ICD/D.0)," Interface Control Document,
European Space Agency / Galileo Joint Undertaking, May 2006 ht tp://www.galileoju.com/page2.cfm
[RD-02] "Navstar GPS Space Segment / Navigation User Interfaces ICD-GPS200C, Rev C," Interface Control Document, January 2003, available at http://www.navcen.uscg.gov/gps/modernization/
[RD-03] [RD-04]
"Navstar GPS Space Segment / User Segment L5 Interfaces ICDGPS-705, Rev 2," Interface Control Document, September 2005, available at http://www.navcen.uscg.gov/gps/modernization/
"Navstar GPS Space Segment / User Segment L1C Interfaces Draft IS-GPS-800," Interface Specification, April 2006, available at ht tp://www.navcen.uscg.gov/gps/modernization/
[RD-05]
GNSS Receiver Design for Attitude Determination, Proceedings of Third ESA International Conference on Spacecraft Guidance, Navigat ion and Control Systems, ref. SP-381, pp. 275-285, February 1997, European Space Agency
[RD-06] AMBA Specification 2.0, 13.05.1999 ht tp://infocenter.arm.com/help/topic/com.arm.doc.ihi0011a/index.html
[RD-07] Mil Bus St andard with Notices
MI L- ST D-1553B
[RD-08] Mil Bus St andard Handbook
MIL-HDBK-1553A
[RD-09] AGGA-4 Final Report, ESA Contract 16831/03/NL/FF, 12.12.2014 AGGA4-ASTD-RP-0003
[RD-10] Anomaly in LEON2FT data cache snooper
ESA- T EC- TN-012539
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2 AGGA-4 Overview
The AGGA-4 (Advanced GPS/GALILEO ASIC) is a radiation tolerant GNSS baseband ASIC capable of processing the modernized GPS and Galileo Signals. Due to its flexibility it is also able to process not only GPS and Galileo but also ot her GNSS syst ems like Glonass, Compass, et c. While the predecessor AGGA-2 "only" incorporated the GNSS core inside the ASIC, AGGA-4 also incorporat es t he processor, the communication interfaces and other support functions (e.g. FFT, CRC) inside t he ASIC [RD-09]. This simplifies t he GNSS receiver board design, while at t he same t ime increasing t he capabilit ies. Figure 2-1 gives an overview t o t he funct ional blocks inside t heAGGA-4:
UART SpaceWire
SRAM PROM
IO
AGGA-4
Debug comm. link AHB
Trace buffer
Debug Support Unit
AHB
Gaisler FPU
LEON2FT IU
I-Cache D-Cache AHB
Status AHB
write protect
AHB
Arbiter/ Decoder
LEON config TIMERs Watchdog
CIC
PIC
A Mem H Ctrl B
AHB
AHB APB
APB
AHB | DMA SpaceWire
AHB | DMA
MIL-Bus 1553
AHB | DMA UARTs
AHB | DMA CRC
AHB FFT
AHB | DMA
GNSS Core & GIC
GPIO SPI
GPIO I/F SPI I/F
SpaceWire I/F MIL-Bus I/F UART I/F
Legend: GIC: GNSS Interrupt Controller CIC: Communication Interrupt Controller PIC: Primary Interrupt Controller
GNSS Signal I/F
Fi gure 2-1: AGGA-4 System O vervi ew
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3 GNSS Core
The AGGA-4 GNSS Core is depicted in Figure 3-1. It consists of 4 Input Modules (IM), one Power Level Det ect or (PLD) Module, two Beam Forming (DBF) Modules, a Time Base Generat or (TBG), an Ant enna Swit ch Cont roller (ASC) and 36 channels. Please note that the connections in Figure 3-1 just depict functional connections. They are not represent at ive concerning t heir widt h.
Front End Interface
Digital Beam Forming
Channel Matrix
Input A0/B0 Input A1/A1 Input A2/B2 Input A3/B3
D/A Out 0 D/A Out 1 D/A Out 2 D/A Out 3
Power Level Detector Module
Input Module 0
DBF 0
DBF 1
Carrier Generator
Unit
Code Generator
Unit
Aiding Unit
Delay Line Unit
Input Selector
X
Final Down Converter
Correlator Unit
PPS ME IMT AUT
ASE
Time Base Generator
Antenna
EC
Switch
Controller
ChaCnhnaenl 0nel 0
36
Half Sample Clk Core Clk Reset PPSI MEI PPSO MEO ExtClk AUT
ASEI ASEO ASC
Fi gure 3-1: AGGA-4 GNSS C ore
Up t o 4 RF Front End's can be connected to the AGGA-4. The data enters in AGGA-4 t hrough t he Input Module(s) where it can be further down converted, if necessary. From the Input Module(s) the data goes either through the Digit al Beam Forming (DBF) Network or directly into the channels. Each channel can select it s input signal out of several possibilities as further detailed in chapter 3.4.1. The GNSS Core of the AGGA-4 uses t wo clock domains, t he GNSS Core Clock (CoreClk) and the HalfSampleClock which has always to be 2.5 times the CoreClk frequency. Minimum periods for t hese clocks and t he way how t he int ernal clock domains are derived from t he ext ernal pins EXT_CORE_CLK and HALF_SAMPLE_CLK are shown in section 6.4. The GNSS Core has its own reset input. If it is used, all regist ers wit hin t he GNSS core are reset t o t heir default values.
Not e: The present chapter of the datasheet often refers to a CoreClk frequency of 40 MHz, because several parts of t he GNSS core like the Delay Line Settings, Aiding Unit Resolution, Integration Lengths, Accumulator Widt hs, et c have been opt imized for t his frequency.
Not e also that the SystemClock always has to be equal or greater than the GNSS CoreClk frequency. Otherwise a stable operat ion of t he AGGA-4 syst em is not guarant eed.
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3.1 Input Module
The AGGA-4 support s t he t ype of int erfaces support ed by t he AGGA-2. Addit ionally, it offers Digit al Down Conversion (DDC) modules for wide bandwidt h navigation signals and a D/A converters for AGC cont rol of t he RF Front Ends. In the DDC mode it is also possible to slave Input Modules together in order to separate several frequency bands. Figure 3-2 shows t he block diagram of the Input Modules. The AGGA-4 has four Input Modules referred to as 0, 1, 2 and 3 t o support up t o 4 ant ennas.
AGGA-4 Input Module 0
RF Front End
Input A0 (0:2) Input B0
(0:2)
Input Format Converter
D/A Out 0
D/A Converter
Input Module 1
RF Front End
Input A1 (0:2) Input B1
(0:2)
Input Format Converter
D/A Out 1
D/A Converter
Input Module 2
RF Front End
Input A2 (0:2) Input B2
(0:2)
Input Format Converter
D/A Out 2
D/A Converter
Input Module 3
RF Front End
Input A3 (0:2) Input B3
(0:2)
Input Format Converter
D/A Out 3
D/A Converter
2 to 5 Conversion
DDCMain
1
0 DDCMain
InSel0
I/Q Mixer
FIR Filter
FIR Filter
ReQuantiser
ReQuantiser
Real to Complex Converter
I (0:2)
Q (0:2) I (0:2) Q (0:2)
I/Q Mixer
FIR Filter
FIR Filter
ReQuantiser
I (0:2)
ReQuantiser
Q (0:2)
DDCAux
1
0 DDCAux InSel0
I/Q Mixer
FIR Filter
FIR Filter
ReQuantiser
I (0:2)
ReQuantiser
Q (0:2)
Mode0
2 to 5 Conversion
DDCMain
1
0 DDCMain
InSel1
I/Q Mixer
FIR Filter
FIR Filter
ReQuantiser
ReQuantiser
Real to Complex Converter
I (0:2)
Q (0:2) I (0:2) Q (0:2)
I/Q Mixer
FIR Filter
FIR Filter
ReQuantiser
I (0:2)
ReQuantiser
Q (0:2)
DDCAux
1
0 DDCAux InSel1
I/Q Mixer
FIR Filter
FIR Filter
ReQuantiser
I (0:2)
ReQuantiser
Q (0:2)
Mode1
2 to 5 Conversion
DDCMain
1
0 DDCMain
InSel2
I/Q Mixer
FIR Filter
FIR Filter
ReQuantiser
ReQuantiser
Real to Complex Converter
I (0:2)
Q (0:2) I (0:2) Q (0:2)
I/Q Mixer
FIR Filter
FIR Filter
ReQuantiser
I (0:2)
ReQuantiser
Q (0:2)
DDCAux
1
0 DDCAux InSel2
I/Q Mixer
FIR Filter
FIR Filter
ReQuantiser
I (0:2)
ReQuantiser
Q (0:2)
Mode2
2 to 5 Conversion
DDCMain
1
0 DDCMain
InSel3
I/Q Mixer
FIR Filter
FIR Filter
ReQuantiser
ReQuantiser
Real to Complex Converter
I (0:2)
Q (0:2) I (0:2) Q (0:2)
I/Q Mixer
FIR Filter
FIR Filter
ReQuantiser
I (0:2)
ReQuantiser
Q (0:2)
DDCAux
1
0 DDCAux InSel3
I/Q Mixer
FIR Filter
FIR Filter
ReQuantiser
I (0:2)
ReQuantiser
Q (0:2)
Mode3
IQ0
To DBF
Network
IQ0AUX To Input Selector
IQ1
To DBF
Network
To Input IQ1AUX Selector
IQ2
To DBF
Network
To Input IQ2AUX Selector
IQ3
To DBF
Network
To Input
IQ3AUX
Selector
Fi gure 3-2: AGGA-4 Input Modul es
Every input module contains an Input Format Convert er (IFC), t wo Digit al Down Convert er (DDCs), a Real t o Complex Converter (R2C) and a D/A Converter in order t o cont rol an AGC in t he RF Front End. The Front End Int erface is capable of processing wide-band signals and a variet y of RF Front End frequency plans.
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The AGGA-4 has four (0 to 3) separate 2 (A,B) x3-bit-wide inputs (A0 A3 and B0 B3), supporting ADC data from:
· Four chains of complex data (I and Q) on inputs An and Bn (three bits each for I and Q) in t he IFC mode for input signal sampled on t he rising edge of CoreClk.
· Four chains of real data on input An (three bits) to be furt her processed in t he R2C mode for input signal sampled on t he rising and falling edge of CoreClk.
· Four chains of real demultiplexed data on input An and Bn (each three bits) to be further processed in the DDC mode, supporting a high-speed sampling scheme: Input An is sampled on the rising edge and Input Bn on t he falling edge of t he HalfSampleClk.
This informat ion is summarized in t he following t able:
Mode Data Input on Pi ns
Input
CoreClk HalfSampleClk Sampling Required
Data Rate
On
Form at
IFC An (0) = I-Sample LSB 1 x
An (1) = I-Sample
CoreClk
An (2) = I-Sample MSB
Bn (0) = Q-Sample LSB
Bn (1) = Q-Sample
Bn (2) = Q-Sample MSB
R2C An (0) = I-Sample LSB 2 x
An (1) = I-Sample
CoreClk
An (2) = I-Sample MSB
CoreClk N/A CoreClk N/A
Rising edge
Sign/magnit ude,
Unsigned,
T wo's complement
Rising and falling edge
Sign/magnit ude,
Unsigned,
T wo's complement
DDC
An (0) = I-Sample-1 LSB An (1) = I-Sample-1 An (2) = I-Sample-1 MSB Bn (0) = I-Sample-2 LSB Bn (1) = I-Sample-2 Bn (2) = I-Sample-2 MSB
2.5 x CoreClk
CoreClk 2.5 x CoreClk
Input An on rising edge Input Bn on falling edge
Sign/magnit ude, Unsigned, T wo's complement
Tabl e 3-1: AGGA-4 Si gnal Input Schemes
The following figures give an example for each of the three modes. Note that for easier readability only two of the four input modules are depict ed.
Figure 3-3 gives an example for the IFC mode. This is the easiest input mode, since the data coming from the RF Front End is only formatted if needed and passed through to the Beam Forming Module. In t his mode t he Input Module requires complex (I/Q) Input data. The ADC for the Input Dat a as well as t he GNSS core is driven by t he CoreClk which can be up to 40 MHz (recommended). Figure 3-3 depicts an example with two RF Front End's (dual frequency receiver). The green path in the figure depicts the CoreClk domain. Note that the HalfSampleClk is not used in t he IFC mode.
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AGGA-4 Input Module 0
CoreClk
RF In
RF Down conversion
RF Front End
ADC I Q
AGC
SPI or D/A Out 0
Input A0 (0:2) Input B0
(0:2)
D/A Out 0
Input Format Converter
D/A Converter
CoreClk
Input Module 1
RF In
RF Down conversion
RF Front End
ADC I Q
AGC
SPI or D/A Out 0
Input A1 (0:2) Input B1
(0:2)
D/A Out 1
Input Format Converter
D/A Converter
1
2 to 5 Conversion
0
DDCInSel0
DDCMain
I/Q Mixer
FIR Filter
FIR Filter
ReQuantiser
I (0:2)
ReQuantiser
Q (0:2)
I (0:2) Q (0:2)
Real to Complex Converter
I/Q Mixer
FIR Filter
FIR Filter
ReQuantiser
I (0:2)
ReQuantiser
Q (0:2)
DDCAux
I/Q Mixer
FIR Filter
FIR Filter
ReQuantiser
I (0:2)
ReQuantiser
Q (0:2)
Mode0
IQ0
E.g. GPS L1
Gal E1
IQ0AUX Not used
1
2 to 5 Conversion
0
DDCInSel0
DDCMain
I/Q Mixer
FIR Filter
FIR Filter
ReQuantiser
I (0:2)
ReQuantiser
Q (0:2)
I (0:2) Q (0:2)
Real to Complex Converter
I/Q Mixer
FIR Filter
FIR Filter
ReQuantiser
I (0:2)
ReQuantiser
Q (0:2)
DDCAux
I/Q Mixer
FIR Filter
FIR Filter
ReQuantiser
I (0:2)
ReQuantiser
Q (0:2)
Mode0
IQ1
E.g. GPS L5
Gal E5a
IQ1AUX Not used
CoreClk HalfSampleClk
Fi gure 3-3: Input Format C onverter (IFC ) Mode Exampl e
Figure 3-4 gives an example for a dual frequency case using the R2C Mode. In this case t he ADC is sampling t wo IF chains (ch0 and ch1) and provides real samples with two times the CoreClk frequency on each path (ch0 and ch1). The
dat a is fed into the AGGA only via the An inputs. Inside the AGGA t he data is sampled wit h the rising and falling edge of t he CoreClk. The data can be re-formatted in the IFC if needed and is then mixed wit h one quarter of t he sampling frequency to near baseband and converted from a real to a complex I/Q signal. The ratio between the Sample frequency
and t he CoreClk frequency has to "2". In the drawn example the red color denotes the Sample Clock domain and t he green color t he CoreClk domain. Not e t hat t he HalfSampleClk is not used in t he R2C mode.
2*CoreClk
RF DownConv L1
ch0
ADC
RF In
RF DownConv L5
ch1
RF Front End
AGC
SPI or D/A Out
AGGA-4 Input Module 0
Input A0 (0:2) Input B0
(0:2)
Input Format Converter
D/A Out 0
D/A Converter
1
2 to 5 Conversion
0
DDCInSel0
DDCMain
I/Q Mixer
FIR Filter
FIR Filter
ReQuantiser
I (0:2)
ReQuantiser
Q (0:2)
Real to Complex Converter
I/Q Mixer
FIR Filter
FIR Filter
ReQuantiser
ReQuantiser
I (0:2) Q (0:2)
I (0:2) Q (0:2)
DDCAux
I/Q Mixer
FIR Filter
FIR Filter
ReQuantiser
I (0:2)
ReQuantiser
Q (0:2)
Mode0
IQ0
E.g. GPS L1
Gal E1
IQ0AUX Not used
Input Module 1
Input A1 (0:2) Input B1
(0:2)
Input Format Converter
D/A Out 1
D/A Converter
1
2 to 5 Conversion
0
DDCInSel0
DDCMain
I/Q Mixer
FIR Filter
FIR Filter
ReQuantiser
I (0:2)
ReQuantiser
Q (0:2)
Real to Complex Converter
I/Q Mixer
FIR Filter
FIR Filter
ReQuantiser
ReQuantiser
I (0:2) Q (0:2)
I (0:2) Q (0:2)
DDCAux
I/Q Mixer
FIR Filter
FIR Filter
ReQuantiser
I (0:2)
ReQuantiser
Q (0:2)
Mode0
IQ1
E.g. GPS L5
Gal E5a
IQ1AUX Not used
CoreClk HalfSampleClk
Fi gure 3-4: Real to C ompl ex (R2C ) Mode Exampl e
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Figure 3-5 gives an example for the DDC mode. In this mode a real signal is sampled with a sampling frequency up t o 200 MHz. The data is then fed in an interleaved mode on ports A and B to the AGGA wit h t he HalfSampling Clock and is t hen parallelized into five streams. Therefore after this parallelizing process (2to5 converter) the functional blocks are
running with CoreClk. In Figure 3-5 three DDC's have been slaved in order t o separat e t he different GNSS bands cont ained wit hin the ADC data. The ratio between the Half Sample Clock and the CoreClk has to be "2.5". In the drawn example t he red color denot es t he Half Sample Clock domain and t he green color t he CoreClk domain.
HalfSample Clk
AGGA-4 Input Module 0
RF In
RF Down conversion
RF Front End
ADC A B
AGC
SPI or D/A Out 0
Input A0 (0:2) Input B0
(0:2)
D/A Out 0
Input Format Converter
D/A Converter
Input Module 1
Input A1 (0:2) Input B1
(0:2)
Input Format Converter
D/A Out 1
D/A Converter
1
2 to 5 Conversion
0
DDCInSel0
DDCMain
I/Q Mixer
FIR Filter
FIR Filter
ReQuantiser
I (0:2)
ReQuantiser
Q (0:2)
Real to Complex Converter
I/Q Mixer
FIR Filter
FIR Filter
ReQuantiser
ReQuantiser
I (0:2) Q (0:2)
I (0:2) Q (0:2)
DDCAux
I/Q Mixer
FIR Filter
FIR Filter
ReQuantiser
I (0:2)
ReQuantiser
Q (0:2)
Mode0
IQ0
E.g. Glonass
L1
IQ0AUX E.g. Compass L1
1
2 to 5 Conversion
0
DDCInSel0
DDCMain
I/Q Mixer
FIR Filter
FIR Filter
ReQuantiser
I (0:2)
ReQuantiser
Q (0:2)
Real to Complex Converter
I/Q Mixer
FIR Filter
FIR Filter
ReQuantiser
ReQuantiser
I (0:2) Q (0:2)
I (0:2) Q (0:2)
DDCAux
I/Q Mixer
FIR Filter
FIR Filter
ReQuantiser
I (0:2)
ReQuantiser
Q (0:2)
Mode0
IQ0
E.g. GPS L1
Gal E1
IQ0AUX Not used
CoreClk HalfSampleClk
Fi gure 3-5: Di gi tal Down C onverter (DDC ) Mode Exampl e
3.1.1 Input Format Converter (IFC)
The input format converter samples the data from the Input An (3bit) and Bn (3bit) and translates it to the internally used 3 bit representation (unsigned). The unsigned representation is used wit hin the whole AGGA-4. It support s different input format s: sign/magnit ude, unsigned and t wo's complement as defined in Table 3-2.
Val ue -7 -5 -3 -1 +1 +3 +5 +7
Si gn/magni tude 011 010 001 000 100 101 110 111
Unsi gned 000 001 010 011 100 101 110 111
Two's compl ement 100 101 110 111 000 001 010 011
Tabl e 3-2: Supported i nput formats
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3.1.2 Digital Down Converter (DDC) Module
Each Input Module contains two identical DDC modules (main and auxiliary). Bot h are always processing t he same input . Each Input Module can support demodulat ion of different frequency bands wit hin one dat a st ream.
The main function of the Digital Down Converter module is t o down convert a GNSS signal band t o near baseband frequency. Moreover, each signal band is separated into its in-phase (I) and quadrature (Q) component s. If t wo DDCs are used (e.g. main(0) & auxiliary(0) or main(0) and main(1)) t hen t hey can separat e different frequency bands.
Only t he DDCmain is fed to the Digital Beam Forming Module. The DDCaux is directly fed t o t he Input Select or of each channel. Note that there is no clock cycle delay bet ween t he main and t he aux st ream, when arriving in t he channel.
DDCMainInSel and DDCAuxInSel in the InputModuleCtrl register determine whether a DDC Module shall process it s own input data or the input data of the predecessor Input Module (slaving mode). Note that the first Input Module (IM0) can only process it s own dat a.
In t he DDC mode the 3-bit samples are entering the AGGA-4 via the inputs An and Bn (e.g. A0/B0 for IM0) and are read wit h HalfSampleClk..
Not e that the ratio between HalfSampleClk and CoreClk shall exact ly be 2.5 (wit h const ant phase relat ionship).
3.1.2.1 Two to Five Converter The function of this module is the reduct ion of clock frequency by parallel dat a processing. In t he DDC mode a mult iplexed data stream on t he input s An and Bn is used, where n is an int eger from 0..3. Aft er t he t wo t o five conversion the sample clock frequency is reduced by a factor of 5 through processing of the divided dat a st ream in 5 st reams simult aneously. The funct ional block diagram is given in Figure 3-6.
AGGA-4
2 to 5 Conversion
DIV 2
HalfSampleClock
To I/Q mixer
Sample Clock
Analog Input
DIV 5
A/D Converter (external)
Conversion
1 to 2 stream conversion
Core Clk
An Bn
Stream 0 Stream 1 Stream 2 Stream 3 Stream 4
Fi gure 3-6: Functi onal bl ock di agram of the Two to Fi ve conversi on
As it is shown in Figure 3-6, the external A/D Converter divides the sampled data into t wo st reams. The t wo t o five channel conversion block uses the HalfSampleClk to input the data into a 16 stage buffer register and CoreClk to read it out in 5 parallel streams. In order to avoid a conflict between in and out pointer the data is written into the shift regist er wit h HalfSampleClk starting from position "0" after reset of t he AGGA-4 and is read wit h CoreClk st art ing from position "8" after reset of AGGA-4. From t here on t he t wo point ers are maint ained by t he t wo clock domains (HalfSampleClk and CoreClk) and it is guaranteed that the pointers will never int erfere t o each ot her as long as t he HalfSampleClk and CoreClk applied to the AGGA-4 show no phase drift ing against each ot her. This can eit her be guaranteed by chosing the AGGA-4 internal "2.5 HalfSampleClk to CoreClk" divider (see Fi gure 6-5) or by making sure t hat t he HalfSampleClk and CoreClk are derived from t he same frequency source.
As a consequence of this synchronization the data stream is delayed by 8 HalfSampleClk cycles by t he "Two t o Five Convert er".
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3.1.2.2 DDC I/Q Mixer Stage
The I/Q mixer separates the data stream int o t he inphase and quadrat ure component s and convert s t he sampled navigation signal from IF to near baseband. Both operations are carried out by the multiplicat ion of t he incoming IF signal data stream with a programmable mixing frequency. Figure 3-7 shows t he signals associated wit h the I/Q mixer.
I/Q Mixer
CoreClock
Stream 0 Stream 1 Stream 2 Stream 3 Stream 4
IStream 0 IStream 1 IStream 2 IStream 3 IStream 4 QStream 0 QStream 1 QStream 2 QStream 3 QStream 4
Fi gure 3-7: I/Q mi xer modul e
The programmable complex mixing frequency fLO is generated by a Numerically Cont rolled Oscillat or (NCO). The input signal frequency (fin) is transposed according to fin-fLo. The NCO frequency fLO is given by the following equation:
f LO
=
±
CoreClk 5 27
where is the signed phase register increment each CoreClk period. The accumulator is 7 bit wide. The frequency range is t herefore ± 5CoreClk/2 wit h a resolut ion of 5CoreClk/27 New phase increment values writ t en int o DDCMainPhaseInc or DDCAuxPhaseInc become effective with the next Measurement Epoch (ME). Besides this, also
t he phase of the NCO is reset to zero with the next ME. This allows phase alignment of mult iple DDC NCO's. The phase increment is a programmed value between -180 deg. and + 180 deg. As the data is paralleled into 5 bit st reams,
t he NCO produces a phase to each of the branches simultaneously. The NCO is increment ed by 5· and t he NCO
phase is distributed to the 5 branches where each branch performs an additional phase increment in order to achieve the appropriat ed LO phase (see Figure 3-8).
5
+
Z-1
LO Phase Generator
Set Phase Increment () 0-63
5 (real)
x
10
(complex)
R
2 3 4
NCO Phase Branch 0
+
Branch 1
+
Branch 2
+
Branch 3
+
Branch 4
Fi gure 3-8: DDC mi xer stage i ncl udi ng the NC O . The del ay of z-1 refers to the CoreClk
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The mixer stage converts the real input data stream, centered at IF between - SampleClk/2 and SampleClk/2 frequency, t o a complex signal near baseband. The incoming signal is therefore phase rotated into a complex signal. The real 3 bit input signal and the complex output signal use the internal representation, corresponding to the values [-7, -5, -3, -1, 1,
3, 5, 7]. The 8 possible representations for the real signal and t he result ing possible combinat ions for t he in-phase component and t he quadrat ure component are shown in Figure 3-9.
Q 7
5
3
1
-1
I
-3
-5
-7 -7 -5 -3 -1 1 3 5 7
Fi gure 3-9: 3 bit signal constellation for the real signal (blue squares) and for the complex signal (black poi nts). The bl ack circles show the rotation of the input frequency. The appropriated rotation is rounded to the nearest
compl ex state.
For t he down conversion the real 3 bit input values and the 7 bit phase register values are considered. With these input s t he resulting complex signal point can be read out of a Look-Up Table. In this table for each real input value and each possible phase shift the corresponding (minimum Euclidian Distance) complex value (I and Q component, each 3 bit) is saved.
In Figure 3-10 the 8 possible real 3 bit input samples are rotated with every possible phase shift (128; each phase shift has a size of 360°/128=2,8°) resulting in the small black dots. The light red circles represent t he possible complex samples after the phase rotation. Each rotated real input sample (black dot) is connect ed wit h t he nearest (minimum Euclidian Distance) possible complex sample by a blue line. The figure shows to which complex point the rot at ed real input samples are mapped.
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128 8
6
4
2
0
-2
-4
-6
-8
-8
-6
-4
-2
0
2
4
6
8
Fi gure 3-10: C ompl ex 3 bi t IQ si gnal constel l ati on
3.1.2.3 Decimating FIR Filter In t he DDC mode, the complex signal from the I/Q mixer is subsequent ly filt ered t o suppress undesired frequency components and frequency images. The FIR filter extracts the desired frequency components of the sampled navigation signal and decimates the sample rate by a factor of 5. As each FIR filter operates at 5 dat a st reams, only one out put sample of 5 input samples is generated. The output is synchronous with CoreClk and consist s of one st ream of dat a. Figure 3-11 shows t he Q filt er. The I filt er looks t he same.
Q Channel decimating FIR Filter
CoreClock
QStream 0 QStream 1 QStream 2 QFiltered QStream 3 QStream 4
Fi gure 3-11: Deci mati ng FIR fi l ter bl ock
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The input signals IStream0 IStream4 and QStream0 QStream4 are filtered in the FIR filter block. The output signals IFiltered and QFiltered, respectively, contain the filt ered and decimat ed dat a. Bot h, input and out put signals are synchronous wit h CoreClk.
Fixed FIR filter coefficients and a fixed decimation factor of 5 are used. The main characteristics of the FIR filter are to maintain a flat amplitude response within the pass band to minimize signal distort ion while suppressing out -of band signals and noise (see Figure 3-12). The hard coded (not programmable) FIR filter coefficients are [-1, -1, 0, 1, 3, 5, 6, 7, 6, 5, 3, 1, 0, -1, -1].
Fi gure 3-12: DDC /DDC FIR fi l ter. ADC sampl e rate = 1, output sampl e rate = 0.2. The architecture of the FIR filter in the DDC is shown in Figure 3-13, where the 15 tap transposed direct form FIR filter is given. The out put dat a rat e is decimat ed by a fact or of 5.
Fi gure 3-13: 15 tap transposed di rect form deci mati ng FIR fi l ter 3.1.2.4 Re-Quantizer The filtered data streams are fed to the re-quantiser and coding block. It performs rounding of the FIR filter samples t o 3 bit s for t he following st ages of GNSS dat a processing. The re-quant isat ion t hresholds are programmable. The re-quantiser block accepts the signal IFiltered and the Qfiltered and outputs the signal IOut and QOut. Alt hough the following figure depict s only t he Q re-quant iser, t he I re-quant iser looks t he same.
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Re-quantiser and coding Q
CoreClock
QOut
QFiltered
Re-quantiser Thresholds
Fi gure 3-14: Re-quanti ser and codi ng bl ock (fi gure wi th quadrature part onl y)
The three 10-bit threshold registers DDCMainFIRQuantThres and DDCAuxFIRQuantThres can be programmed. The t hresholds are going t o be int erpret ed as follows:
Data Fi l tered
Data O ut ( Form at t e d)
max - Threshold2 + 1 => +7
Threshold2 - Threshold1 + 1 => +5
Threshold1 - Threshold0 + 1 => +3
Threshold0 - 0
=> +1
-.1 - -Threshold0 => -1
-Threshold0 - 1
-Threshold1 => -3
-Threshold1 - 1 - -Threshold2 => -5
-Threshold2 - 1 - min
=> -7
Tabl e 3-3: Q uanti zati on Threshol ds
Not e that the max/min FIR out put value is +/- 287 and only 9-bit s of t he 10-bit t hreshold regist er are needed.
3.1.3 Real to Complex Converter (R2C)
The Real to Complex Converter (R2C) is the same as used in the AGGA-2. It can do a real to complex conversion. In comparison to the DDC module it has the limitation that the incoming IF has to be quarter of the sampling frequency or half of t he CoreClk frequency, while t he DDC can be used wit h a wide variet y of IF's. The real input signal is down converted in frequency and it is separated into the corresponding in-phase and quadrat ure component using a complex CoreClk/2 het erodyne as it is shown in Figure 3-15.
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Sampling Clock (2*CoreClock)
X(m)
m=2n
(-1)n x
x m=2n+1
(-1)n
FIR FIlter
Fi gure 3-15: C ompl ex CoreClk/2 heterodyne
I(n) Q(n)
It consists of a mixer stage and a low pass filter to suppress undesired frequency components and frequency images and t o time align the I and Q path. The FIR filter extracts the desired frequency component s of t he sampled navigat ion signal and decimat es t he sample rat e wit h a fact or of 2.
In t he R2C mode the 3-bit samples are entering the AGGA-4 only via the inputs Ax (e.g. A0 for IM0) and are read wit h t he rising and falling edge of t he CoreClk. The HalfSampleClk is not involved in t he R2C mode.
3.1.3.1 R2C I/Q Mixer Stage
The down conversion of the intermediate frequency signal and the division into the real and imaginary part requires a complex multiplication of the sampled signal with a local generated complex carrier. The sampling frequency is t o be selected so that the intermediate frequency is equal to CoreClk/2 which ensures the samples of the carrier wave taken at t he sampling rate are samples of sine and cosine functions with 4 samples per cycle i.e. the samples at the zero crossings wit h value 0, maxima with value 1 and minima with value -1. The heterodyning function becomes one of mult iplexing and selective inversion, as it is depicted in Figure 3-15. The complex het erodyne process corresponds t o a down conversion of the input signal by a fixed frequency equal to one quarter of the sampling frequency. The input signal frequency (fin) is t ransposed according t o fin-fLo.
3.1.3.2 FIR Filter
The complex baseband signal is subsequent ly low-pass filt ered t o remove undesired frequency images. As fIF = CoreClk/2 and alternate samples are zero, the filtering operation is implemented at a sampling rate of CoreClk /2. The low pass filt er charact erist ics are:
· Passband ripple peak-t o-peak: < 0.6 dB
· St oppband suppression:
30 dB
· The passband ends at ± 0.42 t imes CoreClk frequency
· The st opband st art s at ± 0.58 t imes CoreClk frequency
The incoming real signal frequency is centered around half CoreClk and should have a bandwidth not exceeding 0.84 t imes CoreClk frequency. A real input signal between 0.08*CoreClk and 0.92*CoreClk results in an int ernal complex signal bet ween -0.42*CoreClk and 0.42* CoreClk.
The FIR filter is symmetrical with the following hard-coded (not programmable) coefficient s relat ed t o t he input sampling rate:[2, 0,-3, 0, 5, 0, -9, 0, 30, 47, 30, 0, -9, 0, 5, 0, -3, 0, 2]. The overall filter response relat ed t o t he down convert ed signal is given in Figure 3-16.
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Fi gure 3-16: O veral l fi l ter response for the l ow pass fi l ter
The implementation of this filter is simplified by the fact that only the operations with non-zero coefficients are performed. The Q component is received with half CoreClk cycle delay respect the I component, being multiplied by the odd coefficients. In the same way, the I component is multiplied by even coefficients.
Defining the coefficient list as c1 - c19 and In and Qn the data of IMixed and Qmixed respectively, the resulting operations are: IFiltered = c1*I1 + c2*I2 + c3*I3 + c4*I4 + ... + c10*I10 + c11*I11 + ...
where C2n = 0, except c10; where I2n-1 = 0. IFiltered = c10*I10
QFiltered = c1*Q1 + c2*Q2 + c3*Q3 + c4*Q4 + ... + c10*Q10 + c11*Q11 + ... where C2n = 0, except c10; where Q2n = 0.
QFiltered = c1*Q1 + c3*Q3 + ... + c17*Q17 + c19*Q19 where cn = c20-n,
QFiltered = c1 (Q1 + Q19) + c3 (Q3 + Q17) + c5 (Q5 + Q15) + c7 (Q7 + Q13) + c9 (Q9 + Q11)
In order to realise this calculation it is required to have shift register to store the previous data (only even or odd data). The filtered I signal is not processed, because only one coefficient should be multiplied by the signal and in a next stage, the result will be requantised dividing by C10. Therefore, this multiplication and the corresponding requantisation can be optimized.
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In Fi gure 3-17 and Fi gure 3-18 it is detailed how these operations are implemented.
IMixed
IFiltered
QMixed CoreClock
CoreClock
Fi gure 3-17. I component filter calculation
QFiltered
C9
C7
C5
C3
C1
Fi gure 3-18. Q component filter calculation
3.1.3.3 R2C Re-Quantizer
The filtered data is fed to the re-quantiser and coding block. It performs rounding of the FIR filter samples to 3 bit s for t he following stages of GNSS dat a processing. Although the following figure depicts only the Q re-quantiser, t he I requant iser looks t he same.
R2C Re-Quantiser Q
CoreClock QFiltered
QOut
Re-Quantiser Thresholds
Fi gure 3-19: R2C Re-quanti ser (fi gure wi th quadrature part onl y)
The output is quantized into the internal 3 bit format by comparing t he filt er out put values t o const ant t hresholds.
The IFiltered and QFiltered component from the previous filter stage can have values ranged in between -343 t o +343. For a uniform distribution of this range, the thresholds are set t o const ant values according t o t he following t able:
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Q (Fi l tered)
Q (Formatted)
max - 283 => +7
282 - 189 => +5
188 - 95
=> +3
94 - 0
=> +1
-1 - -94 => -1
-95
-188 => -3
-189 - -282 => -5
-283 - Min => -7
Tabl e 3-4: Real -To-C ompl ex (Q part onl y) threshol ds
3.1.4 D/A Converter
In order to be able to adjust the input power level or offset level of the ADCs, sometimes a voltage is required to control at tenuators or automatic gain control (AGC) amplifiers prior to the ADCs. The D/A converter block produces a pulse widt h modulated digital bit stream, corresponding to the amplitude of the input word. Analogue low pass filt ering of t his bit st ream out side of t he AGGA-4 generat es t he cont rol volt age.
CoreClk
D/A Converter
DAControl
DA_OUT (pin)
Fi gure 3-20: D/A C onverter Bl ock
The 12 bit wide register DACt rl contains the input value to the D/A converter. It can be programmed via soft ware. Each input module contains one D/A Convert er. The out going signal is rout ed t o t he pins DA_OUT[0:3], where DA_OUT[0] corresponds to Input Module #0 and DA_OUT[3] to Input Module #3. The 12 bit input signal is used as an
increment input for a 12 bit wide incrementer. The carry-bit of this incrementer gives the output bit stream of t he D/A converter, making sure that t he average number of ones in t he out put bit -st ream is equal t o t he value which is programmed t o DACtrl. Furt hermore t he ones are evenly dist ribut ed.
The increment er and it s out put are synchronized t o t he GNSS CoreClk.
Example:
DACt rl = 0
=> All '0'
DACt rl = 1
=> 4095 '0' followed by one '1'
DACt rl = 1024 => 000100010001...
DACt rl = 2048 => 010101010101...
DACt rl = 4095 => one '0' followed by 4095 '1'
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3.2 Power Level Detector
AGGA-4 has t wo Power Level Detector (PLD) modules. One PLD 5I and one PLD I/Q (see also Figure 3-21). The PLD 5I can count five data streams in parallel. Therefore it shall be used for the DDC modules. The PLD I/Q is used t o count the sample occurrence either behind the Input Format Converter (IFC), before the Final Down Convert er (FDC) or aft er t he Final Down Convert er. Not e t hat t he PLD I/Q only works for frequencies up t o CoreClk.
PLD Module PLD I/Q
PLD 5I
IM (n-1)
Input Module
Input Format Converter
2 to 5 Conversion
DDC Main
R2C
Channel DBF
FDC
...
D/A Converter
DDC Aux
IM (n+1)
Fi gure 3-21: Power Level Detectors
3.2.1 Power Level Detector 5I
The PLD-5I detects the signal levels of the 5 input samples on the input data streams SampleStream 0 SampleStream 4 st emming from one of t he DDC's before it 's I/Q mixer.
Power LevelDetector5I
CoreClock
SampleStream 0 SampleStream 1 SampleStream 2 SampleStream 3 SampleStream 4
Acc5IPlusSeven Acc5IPlusFive Acc5IPlusThree Acc5IPlusOne Acc5IMinusOne Acc5IMinusThree Acc5IMinusFive Acc5IMinusSeven
Fi gure 3-22: Power Level Detector 5I bl ock
The numbers of occurrences of each signal level are accumulat ed in t he eight 24bit accumulat ors in parallel. The accumulation time is either determined by each Measurement Epoch (ME) or by a programmable 24bit count er. The count er can be programmed via the AccTime field in the PLD5ICtrl register. The 24bit counter is incremented with each sample. Since t he PLD is count ing always 5 dat a st reams, t he count er is always increment ed in st eps of 5.
Therefore note that a programmed AccTime of 0..4 causes the PLD to accumulate 5 samples, a programmed AccTime of 5..9 causes t he PLD t o accumulat e 10 samples, and so on.
The regist er PLD5IInputSel det ermines on which input module t he PLD shall count .
An int errupt (GNSS PLD-5I) is generated as soon as the level results are available. It can be masked/unmasked in t he GNSS Int errupt Cont roller (GIC).
When the PLD 5I latches its values, the corresponding time stamp is stored in t he regist ers PLD_5I_IMT_MSW and PLD_5I_IMT_LSW.
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Using t he maximum possible value of 224-1 for AccTimecan cause an overflow in one of t he accumulat ion regist ers under worst case conditions (all samples are equal over the measuring period). Therefore it is recommended not t o use t his value. Also note that the user has to take care that the accumulat ion regist ers have no overflow in case of ME lat ching.
3.2.2 Power Level Detector IQ
3.2.2.1 General Overview The second type of power level detector is called 'Power Level Detector I/Q'. This detect or consist s of t wo ident ical power level det ect ors for t he I and Q signal, which are processed in parallel.
Power Level Detector I/Q
CoreClock
SampleStream IFC IM0 SampleStream IFC IM1 SampleStream IFC IM2 SampleStream IFC IM3
SampleStream pre-FDC ch0 SampleStream pre-FDC ch35
SampleStream post-FDC ch0 SampleStream post-FDC ch35
AccIPlusSeven AccIPlusFive AccIPlusThree AccIPlusOne AccIMinusOne AccIMinusThree AccIMinusFive AccIMinusSeven
AccQPlusSeven AccQPlusFive AccQPlusThree AccQPlusOne AccQMinusOne AccQMinusThree AccQMinusFive AccQMinusSeven
Fi gure 3-23: Power Level Detector I/Q bl ock
In t he PLD I/Q the upper branch processes the I signal and the lower branch processes the Q signal in parallel (see also Figure 3-24). By programming of the the InputSel and SignalSel bit fields of t he PLDIQInputSel regist er a signal is
selected from the incoming signals. The incoming 3 bit I/Q signal can be pre-accumulated in a signed pre-accumulat or before the actual level detect ion. The pre-accumulat or act s as low-pass filt er wit h a 3dB cut -off frequency of:
f cutoff
=
0.44 2 2 ExpFactor
f CoreClk
The pre-accumulation can be useful to reduce the effect of out-of-band interference on the power level measurement s. It is possible to pre-accumulate over 22ExpFactor samples of t he incoming signal, where ExpFactor can be select ed bet ween 0 and 5. If the ExpFactor is set to zero, the pre-accumulat ion and subsequent re-quant izat ion is disabled.
The pre-accumulation window can be shift ed by 0..1023 samples by t he programming of t he Pause field in t he PLDIQPreAccCtrl regist er. The pause shift is applied once and immediat ely. The integration result is scaled eit her by 2ExpFactor or 22ExpFactor. This can be select ed by t he programming of t he ReQuantFactor bit in t he PLDIQPreAccCtrl regist er. The out put of t he re-quant izat ion st age is 3 bit wide.
The numbers of occurrences of each signal level are accumulated in the two times eight 24-bit accumulators in parallel for I and Q and for all signal levels separately. The accumulation time is either determined by each Measurement Epoch (ME) or by a programmable 24-bit counter. The counter can be programmed via the AccTime field in t he PLDIQCtrl regist er. The 24bit counter is incremented with each sample after pre-accumulation. Therefore, if a pre accumulation is enabled, t he effect ive accumulat ion t ime, measured in CoreClk cycles, will be AccTime * 2^(2*ExpFact or).
Not e t hat t he PLD I/Q can count t he occurrences according t o t he following t rut h t able:
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Sp y Point
Input Module Operating Mode
IFC Mode R2C Mode DDC Mode
after IFC
YES
NO
NO
before FDC
YES
YES
YES
after FDC
YES
YES
YES
Table 3-5: PLD IQ Possible Working Modes
An int errupt (GNSS PLD I/Q) is generated as soon as the level results are available. It can be masked/unmasked in t he GNSS Int errupt Controller. If masked, then it can also be used as status flag by polling the GNSS PLD IQ pending bit .
PLD I/Q
4
Inphase
36
Signals
36
Acc
Re-Quant
Level 8 Detect
Acc
8
InputSel / SignalSel
4
Quadrature
36
Signals 36
ExpFactor
Acc
Re -Quant
Level 8 Detect
Acc
8
Pause
Fi gure 3-24: Power Level Detector I/Q
The t ime inst ance when t he PLD I/Q lat ches it s values is st ored in t he regist ers PLD_IQ_IMT_MSW and PLD_IQ_IMT_LSW.
3.2.2.2 Insights to Pre-Accumulator and Re-Quantization
Before being accumulated in the pre-accumulator the samples are transformed t o 13-bit t wo's complement format numbers, in order to be able to handle negatives accumulations. This transformation is realised according to Table 3-6:
Sample
2's compl.
+7
+3
+5
+2
+3
+1
+1
0
-1
-1
-3
-2
-5
-3
-7
-4
Table 3-6: Sample Transformat ion
This transformation is asymmetric with respect to zero, inserting a negative offset of -0.5 with every sample, i.e. by an accumulation of 22N samples, an "unsymetry offset" of -(2(2N-1)) will be accumulated. In order to compensate this, at the beginning of the accumulation, the register is set with an initial value equal to 2(2N-1), setting to `1' the bit in the position 2N-1. Therefore aft er t he pre-accumulat ion t he offset is compensat ed.
Figure 3-25 depictes how t he re-quantization back t o 3bit s is done aft er t he pre-accumulat ion. In case of t he requant ization selection "ReQuant wit h ExpFactor 22ExpFactor", the re-quant izat ion is simply by shift ing t he result by
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22ExpFactor t o the right. In case of the re-quantization selection "ReQuant with ExpFactor 2ExpFactor" one has to know that if one of the saturation bits is different from the sign bit (bit13), t he Value[1:0] is also sat urat ed by t he hardware, no mat t er what t he act ual bit s of [1:0] have been.
Example: ExpFact or =2, t herefore 16 samples are pre-accumulat ed
Assumpt ion: 16x -7 is accumulat ed as 16x(-4) = -64, wit h offset pre condit ion +8 = -56
-56 is binary 1111111001000. According to Figure 3-25 the grey marked bits (bit12, bit3:2) would be t aken. However in t his case at least one of the saturation bits (bit 5:4) is different from the sign bit (bit12). Therefore the result will not be "110" but "100"
In t he end the two's complement values are back transformed to the 3bit unsigned represent at ion according t o Table 3-6.
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ExpFactor = 1
13
ReQuant with 2 2·ExpFactor
13
ReQuant with 2 ExpFactor Value[2]
ExpFactor = 2
13
ReQuant with 2 2·ExpFactor
13
ReQuant with 2 ExpFactor Value[2]
43210
Value[2:0]
43210
Value[1:0]
654 32 10
Value[2:0]
6543210
Value[1:0]
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Extracted bits
Saturation bits
ExpFactor = 3
13
ReQuant with 2 2·ExpFactor
13
ReQuant with 2 ExpFactor
Value[2]
87 6543
0
Value[2:0]
8765 43
0
Value[1:0]
ExpFactor = 4
13
10 9 8 7 6 5 4 3
0
ReQuant with
2 2·ExpFactor
Value[2:0]
13
10 9 8 7 6 5 4 3
0
ReQuant with
2 ExpFactor
Value[2]
Value[1:0]
ExpFactor = 5
13 12 11 10 9 8 7 6 5 4
0
ReQuant with
2 2·ExpFactor
Value[2:0]
13 12 11 10 9 8 7 6 5 4
0
ReQuant with
2 ExpFactor
Value[2]
Value[1:0]
Figure 3-25: Re-Quant isat ion of PLD I/Q Pre-Accumulat ion Result s
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3.3 Digital Beam Forming (DBF)
The Digital Beam Forming (DBF) module combines the signals of two antenna elements in the digital domain in order t o steer the antenna beam. In the AGGA-4, digital beam-forming is carried out before the correlation (pre-correlat ion beam forming). It performs phase shift ing and combinat ion of t wo ant enna signals aft er t he first coarse downconversion in the Input Modules prior to the correlators. The main advantage is that only the combined signals are fed t o t he final down-conversion st age and t he de-spreading correlat ors.
Two Digit al Beam Forming (DBF) modules for the processing of two antenna inputs each are implemented. Generally, t he first DBF module (DBF-0) processes the inputs from ant enna A0 and ant enna A1 and t he second DBF module (DBF-1) processes t he input s from ant enna A2 and A3 as it is shown in Figure 3-26.
A0
RF FE
IM0
e.g. L1
A1
DBF 0 9
RF FE
IM1
e.g. L1
A2
RF FE
IM2 e.g. L2
DBF 1 9
A3
RF FE
IM3 e.g. L2
Fi gure 3-26: Beam formi ng for si ngl e frequency operati on
However, for dual frequency operation the input from one antenna can be used for two Input Modules which process
different frequencies. Since a second antenna is needed for the beam forming, the input of ant enna A2 is send t o t he DBF-0 module and the input of antenna A0 is send to the DBF-1 module. By this architecture the antenna inputs of t he same frequency are combined in t he DBF modules. This is shown in Figure 3-27.
A0
RF FE
IM0
e.g. L1
A1
DBF 0 9
RF FE
IM1
e.g. L2 e.g. L1
A2
RF FE
IM2
DBF 1 9
A3
RF FE
IM3 e.g. L2
Fi gure 3-27: Beam formi ng for dual frequency operati on
A fixed set of beam-forming coefficients supporting the rotation angles of 0, +/- 45°, +/- 90° and +/- 135° is used in the AGGA-4. All 7 possible beams are generated simultaneously and these beams and t he direct ant enna signals can be rout ed t o any one of t he channels in t he GNSS core of t he AGGA-4.
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Beam Forming Coefficient Rotation Angle
j0
0°
j1
45°
j2
90°
j3
135°
Tabl e 3-7: Beam formi ng coeffi ci ents
Figure 3-28 shows t he architecture of the DBF modules. If the DBF-0 is used as shown in Figure 3-26 t hen t he input s IM 0 and IM 1 are used. If the DBF-0 is used as shown in Figure 3-27 then the inputs IM 0 and IM2 are processed. By t he programming of DBF0Sel and DBF1Sel in the DBFInputSel regist er, t he user can select for each DBF module which Input Module input (e.g. IM1 or IM2 for DBF0) shall be selected. The inputs are phase rotated and combined or fed direct ly t o t he channel mat rix.
From Input Modules
6
A
6
B
To Channel Matrix IM 0
IM 1/2
DBF0
IM 0
A
6
IM 1 0
6
B
IM 2 1
DBF0Sel
e jj1
+
Re-Quant 4bit -> 3bit
6
+
Re-Quant 4bit -> 3bit
6
+
Re-Quant 4bit -> 3bit
6
DBF1
IM 3
B
6
IM 2 0
6
A
IM 1 1
DBF1Sel
ejj2 ejj3 ejj1
+
Re-Quant 4bit -> 3bit
6
+
Re-Quant 4bit -> 3bit
6
+
Re-Quant 4bit -> 3bit
6
ejj2
+
Re-Quant 4bit -> 3bit
6
ejj3 Fi gure 3-28: Di gi tal Beam Formi ng Modul e
0° +45° +90° +135° -45° -90° -135°
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The carrier phase of the IM 1/2 signal is shifted in the mixer stage by j0 t hrough j3 (whereas j0 is not shown in t he figure below, since: j0 =0) and added to the IM 0 signal to obtain the desired beam forming, here referred t o as +45°, +90° and +135°. Further, shifting the IM 0 signal by j1 t hrough j3 and combining the shift ed signal wit h t he IM 1/2 signal causes t he beams referred t o as -45°, -90° and -135°.
It has to be noted that the +/- 90° rotation is lossless and needs no quantization, since every input point in t he AGGA-4 not ation (-7, -5, -3, -1, +1, +3, +5, +7) before the rotation can be directly be mapped to a rotated point in t he AGGA-4 not at ion.
If a rotation of +/-45° is selected then the points before the rotation (in AGGA-4 notation) are mapped t o t he nearest possible point in t he AGGA-4 not at ion aft er t he rot at ion.
Example: An input point of (-7/-3) rotated with 45° results in (-2.83/-7.07) which is t hen mapped t o (-3/-7). The mapping is done wit h a look up t able.
Figure 3-29 depicts the rotation diagrams for every possible rotation. The red circles represent t he possible point s in AGGA-4 not ation. The thicker black dots (not the black dots from the axes grid) are the points after rotation. The blue line shows t o which possible AGGA-4 point t he rot at ed point was mapped.
Example: Assuming an input point of (-7/-7). With a 45° rotation it moves to (0/-9.9). This point is t hen mapped t o (1/7).
Not e that rotations of 135° are done by doing first a 90° rotation followed by a 45° rotation. That's why the right hand diagram of Figure 3-29 is applicable for 45° and 135° rot at ions.
+/- 90° rot at ion
+/- 45° and +/- 135° rot at ion
Fi gure 3-29: DBF Rotati on operati on
Aft er the rotation, the signals from the two input modules are added. The input signals to the beam forming are 3-bit wide (I and Q). After the addition of two signals (e.g. IM0+ IM1) they have 4-bit. They are immediately re-quantized to 3-bit by t aking t he following LUT (Table 3-8):
Input to Requantization O utput of Requantization
-14 -12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12 14 -7 -7 -5 -5 -3 -3 -1 +1 +1 +3 +3 +5 +5 +7 +7
Tabl e 3-8: Requanti zati on Tabl e of Beamformi ng Addi ti on
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3.4 Channel Matrix with Channels
As ant icipated in Figure 3-1, the Channel Matrix can be underst ood as t he housing of all channels, t he Time Base Generat or (TBG) and the Antenna Swit ch Controller (ASC). The functionalit y of t hese modules is described in t he corresponding chapt ers.
Fi gure 3-30 gives an overview t o an AGGA-4 channel. The whole AGGA-4 inhabits 36 channels. By the programming of t he corresponding channel bit in the ChActivation0 and ChActivation1 registers, the clock t o each channel can be gat ed on or off. Note that a channel's registers are automatically reset to their default values defined in chapt er 7 if gat ed on/off. The PrimaryRAM1/2 and SecondaryRAM1/2 memories are not reset .
AGGA-4 channels can be slaved in a hardware manner (like it was the case in AGGA-2 and AGGA-3) or in a soft ware manner (which is new compared to AGGA-2 and AGGA-3). For further details about soft ware slaving funct ion see 3.4.8.
For t he hardware slaving each channel outputs a variety of signals (see also Figure 3-30) which can be used by the next channel as input signals. Note that wit h hardware slaving only subsequent channels can be slaved. Therefore if t he wording "previous channel" is used in the following chapters it always means channel-1. If the wording "next channel" is used it always means channel+1. There is one speciality which is the first and the last channel. The "next channel" seen from channel 36 is channel 0 (wrap around functionalit y). Also t he previous channel seen from channel 0 is channel 36.
Soft ware slaving has not been possible in the AGGA-2 and AGGA-3 since only t he MSBs of t he Carrier and Code NCOs have been visible to t he soft ware. Therefore it was not possible for t he soft ware t o make sure t hat t wo independent channels are running coherently not only in frequency, but also in phase. This is now possible since the full 32bit NCO states of Code and Carrier can be made visible to the software. The advantage of soft ware slaving is t hat every channel can be slaved with every channel (not only the next and previous one). The disadvantage is more effort for the software, since the control words for the channels have to be copied not only in the master channel, but also t o t he slave channels and that also in time (typically before t he next Int egrat ion Epoch). Figure 3-30 also shows t he int ernal connect ions t o t he Test Support Signals, see 6.7
From previous channel
IE from previous channel
LE from prev channel ASE In
Delay Clock In Code In 1 Code In 2 Primary Rate BOCRate (cos) In BOCRate (sin) In
Input Data from previous channel PPS In ME In Carrier In
From Time Base
ME PPS IMT
From DDCAux
From Beam Forming Network
Input Selector
Channel
D2
...
Code Generator
Code NCO
BOCRate (sin)
Code Generation
Carrier NCO
Code Delay Line Unit
EE
LL
Base
bandD 2
10
Final Down Converter
Integration Control
IE
LE
HDL Delay
EE
E
P
S
L
LL
+
Code Aiding
+
From S/W
Carrier Aiding
Aiding Clock Generation
AU Trigger
Aiding Unit
Data Collect 1 (LL-Q)
I/Q 10 Accumulations
Correlator Unit
IE_LoopState IE_IMT_LSW IE_ValueEE_I
... ME_CodePhase
Observables
To S/W
DD
D D D D D DD D
D
D = One CoreClk Delay
Test Points for debugging
ASE Out IntEpoch
Carrier Out SignalOutPostFDC
CodeOut Delay Clock Out
Code Out 1 Code Out 2 Primary Rate Out BOCRate (cos) Out BOCRate (sin) Out LE to next Ch. IE to next Ch.
Input Data to next channel
ME Out PPS Out SignalOutPreFDC
To next channel
Fi gure 3-30: C hannel O vervi ew
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3.4.1 Input Selector
The Input Select or select s an I/Q signal
· from t he previous channel
· direct ly from one of t he four Input Modules (DDCAux st reams)
· one beam out of t he beam forming net work.
Each I/Q signal provides a complex sample every CoreClk, consisting of the in-phase component and t he quadrat ure component. Each I and Q component is represented in the internal 3 bit format corresponding to the values [-7, -5, -3, 1, +1, +3, +5, +7]. In order t o select t he input signal, t he InputSel field of t he ChannelCtrl regist er has t o be programmed.
3.4.2 Final Down Converter (FDC)
The Final Down Converter consists of the Carrier Generator and the Carrier Mixer as shown in Figure 3-31. It removes t he residual carrier from the 2*3bit complex input signal selected from the Input Selector by subtracting the value of the Carrier Generator from the angle represented by the input signal. The residual frequency can include the Int ermediat e Frequency after the DDC, the R2C or after the IFC. Furthermore it can include the Doppler shift and the local oscillator offset .
Final Down Converter
CarrierNCOFreq from Aiding Unit
Carrier Generator
CarrNCOFreq
+
NCO Accu
CarrSwShiftMode
CarrSwShift
IE & ME
20bit Cycle Count
CarrObsSel
1
+0
IE CarrObs/Phase ME CarrObs/Phase
Carrier Signal from previous
channel
From Input Selector
1 0 CarrSel Carrier Signal (5 MSB's)
Carrier Mixer x
To Code Multiplier
Accesible by software
To next channel (for slaving)
Fi gure 3-31: Fi nal Down C onverter
3.4.2.1 Carrier Generator
The Carrier Generator provides the carrier replica to convert the navigat ion signal t o baseband and t o st rip off t he Doppler frequency. The frequency of the carrier NCO is determined by t he signed 32 bit CarrNCOFreq increment which comes from the Carrier Aiding Unit. The CarrNCOFreq increment gets accumulated with every CoreClk cycle in t he NCO accumulator. Additionally the phase can be adjusted by the signed 32bit CarrSwShift regist er. A writ t en value t o CarrSwShift is added once to the NCO accumulator either immediat e or wit h t he next int egrat ion epoch, depending on the programming of the CarrSwShiftMode bit in the NCOSettings register. Note that the current phase (32 bit NCO accumulat or value) is ret urned in t he CarrSwShift regist er if it is read. The valid range of CarrSwShift is from 231 to 231-1, corresponding to phase shifts of up to ±180 deg. with a resolut ion of approx. 84 ndeg.
As soon as the NCO accumulator wraps around the unsigned 20bit Cycle Counter is either incremented or decremented, depending whet her t he NCO generat es a posit ive or negat ive frequency.
At each Integration and Measurement Epoch the cycle count and the NCO accumulat or value are lat ched. They are t ransferred to the IE_CarrObsPhase and ME_CarrObsPhase registers. By programming t he IE_CarrObsSel and t he
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ME_CarrObsSel bit in the CorrUnitCtrl register, the user can select whether he want s t o have all 32bit of t he NCO accumulator latched in the observable or if he wants a mixture of cycle count and NCO accumulator value. If mixture is chosen, the 12MSBs of the NCO accumulator are written in the lower bits of the observable and the 20 bit cycle count is writ ten in the upper bits of the observable. Note that the observables are updated every IE and ME either in mixt ure OR pure phase mode.
By t he programming of the CarrSel bit in the ChannelCtrl register it can be selected whether t he Carrier Mixer shall t ake the local generated Carrier signal or the Carrier signal of the previous channel (hardware slaving). Not e t hat t he IE_CarrObsPhase and the ME_CarrObsPhaseobservables are always driven by the local NCO, no matter if the Carrier Mixer uses t he local or t he slaved Carrier signal.
The 5 MSBs of t he carrier NCO accumulat or are out put as Carrier signal, having 32 possible values.
The NCO out put frequency is calculat ed according t o t he following equat ion:
f out
=
CoreClk 2 27
11.25deg 360 deg
=
CoreClk 2 32
where fout is the output frequency and is the signed phase register increment (CarrNCOFreq). The frequency range is t herefore ±CoreClk/2 wit h a resolut ion of CoreClk/232.
3.4.2.2 Carrier Mixer
The complex input and output signals use the internal representation, corresponding to the values [-7, -5, -3, -1, 1, 3, 5, 7] for t he in-phase component and t he quadrat ure component .
Down conversion is performed in 3 steps. First the input sample given by the I and Q value is t ransformed int o polar coordinates with the help of a LUT. Then, the phase shift given by the Carrier signal is subtracted from the angle of the input signal. In the third step the shifted input value given by the magnit ude and t he new angle is ret ransformed t o Cart esian coordinates with the help of a LUT. The ent ries of t he LUT give for each possible magnit ude and each possible phase t he corresponding (minimum Euclidian Dist ance) IQ value of t he possible set of IQ values.
The LUTs only exist for the first quadrant of the signal constellation. Every signal which is not in t his area has t o be t ransformed to this section. For example, if the input signal is detected to be in the second quadrant it is rotated back for 90° by applying t he following equat ion:
Ir=Qi
Qr=-Ii, where t he subscript r ident ifies t he rot at ed signal and i t he input signal.
Figure 3-32 illustrates the down conversion. The red circles are t he possible values of t he signal space. The black squares are all possible samples after the rotation of the input samples. The blue lines show for each rotat ed sample t o which signal space point it is mapped.
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Fi gure 3-32: C ompl ex 3 bi t si gnal constel l ati on wi th 32 possi bl e NC O val ues
3.4.3 Code Generator Unit
The Code Generator Unit is capable of generat ing t wo independent codes. Each code can consist of primary and secondary code. Additionally these codes can be multiplied with a 2 bit Binary Offset Carrier (BOC) sin or cosine pat tern. Also time multiplexed codes (like GPS L2C) are possible. In this case the time mult iplexed code is rout ed t o Out put 1, while the enable/disable signal is routed to Output 2. Note that no AltBOC is support ed. TMBOC or CBOC signals can be tracked with minimal losses (e.g. the low frequency part of the BOC is tracked, while the high frequency part of t he BOC is not correlat ed).
The Code Generator Unit can be started either at the next Int egrat ion Epoch or Measurement Epoch. This can be select ed by t he configurat ion bit Trigger in t he CodeGenUnitCtrl regist er.
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Code NCO 180°
Divider Primary Rate
VFCG
x
x
x
Observables
Code Rate Generator
0 1 BOCCosEn
Divider
ResetSCM1
Divider
ResetSCM2 BOC Rate Reset with Primary Rate
Prim. Code Memory 1+2
Prim. Code Memory 1
Prim. Code Memory 2
Sec. Code Memory 1
Sec. Code Memory 2
BOC Register 2 bit
01
CodeRam Sel
01
1
x
x0
1 Output 1 0
GPSL2CEn
0 1
StartOfEpochSel 0
3
Start of Epoch
Fi gure 3-33: C ode Generator Uni t
The Very Flexible Code Generator (VFCG) consists of a 2x14 stages Linear Feedback Shift Register (LFSR) which can be coupled together to a 1x28 st age LFSR. Wit h t his configurat ion all t oday known shift regist er codes can be generat ed, except t he GPS P-code. Each primary code memory consists of 5120 bits. Each secondary code memory consists of 100 bit s. It is possible t o combine primary code memory 1 and primary code memory 2 to one primary code memory with 10240 bits. The output of t he combined memory is t hen eit her rout ed t o Out put 1 or t o Out put 2 (see Figure 3-33). Wit h this configuration all today known pilot/data code combinations can be processed wit hin one channel. Table 3-9 shall give an idea how the Code Generator Unit can be configured in order to generate the signals. The numbers below t he column VFCG refer to the LFSR st ages needed to generate the signal. The numbers below the column of t he code memories refer to the number of bits needed in order to generate the signal. Note that the examples on t his t able shall only give an idea how t he Code Generator can be configured. It is by far not complete, since there are almost unlimit ed combinat ions t o generat e t he different signals.
VFCG Prim. Code 1 Sec. Code 1 Prim. Code 2 Sec Code 2
BOC
GPS CA Code
2x10 ---
--1023
-----
-----
-----
-----
GPS L2C
1x27
---
---
10230
---
,,1",,0"or,,0",,1"
GPS L5 I+Q Galileo E1B+C
2x13 ---
--4092
20
10230
10
25
4092
0
--,,1" ,,0"
Galileo E5A I+Q 2x14
---
100
10230
20
---
Tabl e 3-9: Exampl e wi th possi bl e C ode Generator Uni t confi gurati on
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In general it can be said t hat t he Code Generat or Unit is able t o produce codes wit h t he following propert ies
Single Component Code (consist ing of eit her pilot or dat a) · Shift regist er codes wit h an lengt h up t o 228-1 bit · Memory codes (primary) wit h a lengt h up t o 10240 bit · Memory codes (secondary) wit h a lengt h up t o 100 bit · BOC code wit h a sequence lengt h up t o 2 bit
Double Component Code (consist ing of pilot and dat a) · One component 228-1 bit , t he ot her 10240 if one component can be generat ed wit h LFSR · Bot h component s of 5120 bit each, if bot h component s are memory based codes · Memory codes (secondary) wit h a lengt h up t o 100 bit · BOC code wit h a sequence lengt h up t o 2 bit
Reloading of secondary codes is not the preferred solution, but it is possible due to the low data rate of secondary codes. Therefore, any future signal (e.g. GPS L1C) wit h secondary codes longer than 100 bit s, but st ill fulfilling t he ot her crit eria's ment ioned above, can st ill be processed.
Having a look at the signals where the properties are already known, the Code Generator Unit will be able t o generat e t he following signals wit hin each of t he 36 channels:
Signal GPS L1 CA GPS L1 P-Code GPS L2 P-Code GPS L2CM GPS L2CL GPS L2C (M+L) GPS L5 I GPS L5 Q GPS L5 (I+Q)
Yes No x x x x x x x x x
Galileo E1 B
x
Galileo E1 C
x
Galileo E1 (B+C)
x
Galileo E5B I
x
Galileo E5B Q
x
Galileo E5B (I+Q) x
Galileo E5A I
x
Galileo E5A Q
x
Galileo E5A (I+Q) x
Galileo E5Q AltBOC
x
Beidou B1 I
x
Beidou B2 I
x
Beidou B3 I
x
Tabl e 3-10: December 2009 Si gnal Summary
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3.4.3.1 Very Flexible Code Generator (VFCG)
The Very Flexible Code Generator consists of a 2x14 stage LFSR, which can be coupled together to a 1x28 stage LFSR and a 2x14 bit counter, which can be coupled together to a 1x28 bit counter. With this configurat ion all t oday known shift regist er codes can be generat ed, except t he GPS P-code.
Start of Epoch
Primary Rate
Counter 14 Bit 14 Bit
28 Bit
LFSR 14 Bit 14 Bit
28 Bit
Primary Code Out
2x14 Bit LENGTH
2x14 Bit INIT 2x14 Bit POLYNOM
From uP I/F
VFCG
Fi gure 3-34: Very Fl exi bl e C ode Generator (Long Mode)
Primary Rate
Start of Epoch 1
Counter-1 14 Bit 14 Bit
28 Bit
LFSR-1 14 Bit 14 Bit
28 Bit
PN Seq. a
From uP I/F Start of Epoch 2
14 Bit LENGTH-1
GPS L5En
Counter-2 14 Bit 14 Bit
28 Bit
14 Bit INIT-1
14 Bit POLYNOM-1
X VFCG (1/2)
LFSR-2 14 Bit 14 Bit
28 Bit
PN Seq. b
Primary Code Out
14 Bit LENGTH-2
14 Bit INIT-2 14 Bit POLYNOM-2
From uP I/F
VFCG (2/2) VFCG
Fi gure 3-35 : Very Fl exi bl e C ode Generator (Normal Mode)
The StartOfEpoch Signal arises between the edge of the last and the first chip of a code epoch. It is used t o reload t he VFCG LFSR's wit h t he init patterns. Also it can be used to synchronize the Integration Epoch of t he correlat ors wit h
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t he code epoch. The VFCG length registers can be reloaded at any time to perform a quick L2CL adjustment once t he L2CM code has been acquired.
In principal t he VFCG can be operat ed in t wo modes: In t he "long mode" (VFCGLongEn = 1, Fi gure 3-34) t he VFCG appears t o have: · one 28 bit LFSR · one 28 bit lengt h count er · one 28 bit init regist er · one 28 bit polynom regist er In t he "normal mode" (VFCGLongEn = 0, Fi gure 3-35) t he VFCG appears t o have: · t wo 14 bit LFSR · t wo 14 bit lengt h count er · t wo 14 bit init regist er · t wo 14 bit polynom regist er
In "long mode" the LFSR is reloaded with the init value when either t he VFCG is st art ed or t he lengt h count er has elapsed. In "normal mode" t he reloading of t he sift regist ers is as following:
· LFSR 1 and 2 are reloaded when t heVFCG is st art ed · LFSR 1 is reloaded when t he lengt h count er 1 has elapsed · LFSR 2 is reloaded when t he lengt h count er 2 has elapsed · LFSR 1 is reloaded when the length count er 2 has elapsed (t his is only done when t he configurat ion bit
GPSL5En is set t o 1)
The architecture of the LFSR in normal mode is depicted in Figure 3-36. The architecture of the LFSR in long mode is depict ed in Figure 3-37. The init register is not shown in this figure as it simply preloads the LFSR register. The "+" in t he two figures are corresponding to XOR logic. The shift direction of the LFSR is left wise. The feedback t aps in t he figure have been arbitrarily chosen. They are determined by the programming of the VFCGExtTaps register. Wit h t his knowledge all existing PRN Codes can be concluded for the AGGA-4. Table 3-11 gives the initialization vectors for all Galileo and GPS shift register codes described in [RD-01] to [RD4]. The numbers are represented in 32bit hexadecimal format and can t herefore direct ly be past ed int o source code.
Polynom-1 Register
13
12
&
...
3
2
1
0
&
&
&
&
+
+
+ ... +
13
12
3
2
1
0
LFSR-1 Register
...
+
Code Out
Polynom-2 Register
13
12
&
3
2
1
0
&
&
&
&
+
+
+ ... +
13
12
3
2
1
0
LFSR-2 Register
Fi gure 3-36: LFSR archi tecture i n "normal mode"
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Polynom-1+2 Register
...
27
26
3
2
1
0
&
&
&
&
&
+
+
+ ... +
Code Out
27
26
3
2
1
0
LFSR-1+2 Register
Fi gure 3-37: LFSR archi tecture i n "l ong mode"
PRN
Galileo
GPS
E5A-I E5A-Q E5B-I E5B-Q
CA
L2CM L2CL
L5-I
L5-Q
1 0x0C8760C0 0x0A0CE0C0 0x03527C06 0x0166BC06 0x03C03800 0x02DF851E 0x05FD30A6 0x03293FEC 0x02F2BFEC
2 0x067E60C0 0x02A260C0 0x099DFC06 0x02817C06 0x01E03800 0x0B8181DE 0x04F08D8A 0x0E61BFEC 0x05283FEC
3 0x0B59A0C0 0x0A9E20C0 0x00217C06 0x0F967C06 0x00F03800 0x02673D00 0x07007824 0x01B6BFEC 0x0B0DBFEC
4 0x0880A0C0 0x0C47E0C0 0x06423C06 0x0D0CFC06 0x00783800 0x02BD69B0 0x0223044E 0x05DABFEC 0x07383FEC
5 0x097E60C0 0x0B47E0C0 0x07AEFC06 0x0060BC06 0x07F83800 0x09CE0606 0x0A763200 0x08F33FEC 0x06793FEC
6 0x0D68E0C0 0x0A87A0C0 0x01053C06 0x08F53C06 0x03FC3800 0x0DBACB0E 0x06B64350 0x07F23FEC 0x0C7E3FEC
7 0x06B160C0 0x0D4C60C0 0x00E43C06 0x04253C06 0x07F03800 0x01C094A8 0x07D45556 0x097EBFEC 0x0DAABFEC
8 0x0527A0C0 0x0B3420C0 0x0993FC06 0x035E7C06 0x03F83800 0x08F39BC6 0x0FF95184 0x03103FEC 0x01E33FEC
9 0x00DF60C0 0x03C0E0C0 0x00CF3C06 0x07787C06 0x01FC3800 0x089C3790 0x03F676C0 0x0AB73FEC 0x0B5ABFEC
10 0x0C9060C0 0x00F8E0C0 0x0A31FC06 0x0812BC06 0x02003800 0x0644C36E 0x07C2563A 0x04FABFEC 0x05AA3FEC
11 0x0B4320C0 0x0500A0C0 0x017A3C06 0x0A437C06 0x01003800 0x0A62974E 0x0AAE7320 0x07D0BFEC 0x0ED03FEC
12 0x038DE0C0 0x0DBAA0C0 0x095AFC06 0x0C53BC06 0x00403800 0x061FC4A0 0x014BFFC8 0x0C963FEC 0x0EFC3FEC
13 0x0FA460C0 0x074EA0C0 0x0F1BFC06 0x0123BC06 0x00203800 0x0C016A20 0x0B739586 0x0212BFEC 0x0EAC3FEC
14 0x07C5A0C0 0x072D20C0 0x0DE1FC06 0x0ACB7C06 0x00103800 0x0975AC64 0x0C77C300 0x0866BFEC 0x09083FEC
15 0x036CA0C0 0x0F4860C0 0x0386FC06 0x0E20FC06 0x00083800 0x00099A00 0x0AED9590 0x07893FEC 0x09AE3FEC
16 0x069060C0 0x0152A0C0 0x03093C06 0x03A97C06 0x00043800 0x062C4124 0x089C9676 0x0C293FEC 0x09573FEC
17 0x0AC7A0C0 0x0135A0C0 0x0E0DBC06 0x01E1FC06 0x07003800 0x0681681A 0x00920686 0x09AABFEC 0x0198BFEC
18 0x048260C0 0x036DA0C0 0x0513FC06 0x0A56BC06 0x03803800 0x0A3C5684 0x0E13F500 0x04DA3FEC 0x032B3FEC
19 0x0A95A0C0 0x0A6A60C0 0x00663C06 0x002FBC06 0x01C03800 0x026240B0 0x094E72AA 0x096ABFEC 0x0A3B3FEC
20 0x0063E0C0 0x050460C0 0x099A7C06 0x06737C06 0x00E03800 0x03D47028 0x0AFF55B4 0x0F35BFEC 0x0D393FEC
21 0x04BA20C0 0x021960C0 0x05F2FC06 0x0EB27C06 0x00703800 0x0DAE4090 0x0C387D80 0x01B43FEC 0x00CFBFEC
22 0x07E1A0C0 0x04C4E0C0 0x05C27C06 0x08C1FC06 0x00383800 0x0EB13CAE 0x0769E60A 0x09F23FEC 0x0410BFEC
23 0x0B3760C0 0x0007A0C0 0x0D4A3C06 0x0A1CFC06 0x06003800 0x0FEE3E90 0x0C4F3F1E 0x049E3FEC 0x0FEC3FEC
24 0x0C4DE0C0 0x033B20C0 0x0A16BC06 0x020B3C06 0x00C03800 0x00DC0A1E 0x06B9D6C6 0x03C23FEC 0x0BF03FEC
25 0x05F860C0 0x020660C0 0x0D89FC06 0x0CF1FC06 0x00603800 0x03A1E80E 0x008C4F3E 0x0F3D3FEC 0x0A12BFEC
26 0x061CE0C0 0x08BCA0C0 0x080E3C06 0x0C7A7C06 0x00303800 0x08D72840 0x03CF5C2E 0x057CBFEC 0x02733FEC
27 0x0EF360C0 0x04FC60C0 0x0ABAFC06 0x06CE7C06 0x00183800 0x0A4EC74E 0x0C44540E 0x04F43FEC 0x07F03FEC
28 0x09A3A0C0 0x09EAA0C0 0x0E027C06 0x06783C06 0x000C3800 0x04E15BEE 0x0CD77524 0x0556BFEC 0x06E3BFEC
29 0x0CD5E0C0 0x0CE520C0 0x01723C06 0x0958BC06 0x07C03800 0x038F4E4C 0x02357D68 0x0DF23FEC 0x0304BFEC
30 0x0B5020C0 0x0A8820C0 0x0F097C06 0x06FA7C06 0x03E03800 0x0E02A44E 0x0A52D99E 0x08A73FEC 0x0C8FBFEC
31 0x00DEA0C0 0x03D9E0C0 0x0923FC06 0x0FD0BC06 0x01F03800 0x0DA2652E 0x06C81908 0x04C33FEC 0x0E9C3FEC
32 0x067B60C0 0x0DDAA0C0 0x0B34FC06 0x04393C06 0x00F83800 0x0D12F050 0x073CCAD4 0x0CA2BFEC 0x0700BFEC
33 0x0C7260C0 0x02B1E0C0 0x0CA83C06 0x0BFE7C06 0x007C3800 0x0C3EAC0A 0x083C6FE2 0x0DA43FEC 0x035DBFEC
34 0x09DFA0C0 0x0B2560C0 0x0E8B7C06 0x0C94FC06 0x00FC3800 0x078FE2DE 0x043723CE 0x0C9E3FEC 0x035C3FEC
35 0x0D76A0C0 0x01E0E0C0 0x0E9BBC06 0x0C73FC06 0x07E03800 0x08F79DE8 0x0E118D24 0x022BBFEC 0x0BCB3FEC
36 0x0168A0C0 0x0113A0C0 0x04D97C06 0x06D6BC06 0x03F03800 0x0D4DEDDE 0x0E36523A 0x019CBFEC 0x09C33FEC
37 0x086460C0 0x0EF920C0 0x032B7C06 0x083ABC06 0x00FC3800 0x052316E2 0x0DC69C14 0x00C53FEC 0x0D4DBFEC
38 0x0E4CA0C0 0x029760C0 0x050C3C06 0x0482FC06
39 0x0E6C60C0 0x0F2DE0C0 0x0D01FC06 0x05E87C06
40 0x0A80A0C0 0x076360C0 0x01083C06 0x0FD3FC06
41 0x0651A0C0 0x0FB420C0 0x0202FC06 0x0FE67C06
42 0x0B7DA0C0 0x0348A0C0 0x0F7B3C06 0x0DFC7C06
43 0x0349A0C0 0x0B8FE0C0 0x07B7FC06 0x0334BC06
44 0x0C7420C0 0x07F1E0C0 0x0E69BC06 0x04813C06
45 0x0EC9E0C0 0x0E2160C0 0x0F53BC06 0x03113C06
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46 0x0A4E20C0 0x0FB120C0 0x0C41BC06 0x01D93C06 47 0x08A0E0C0 0x057EA0C0 0x0993BC06 0x06BE7C06 48 0x0C4960C0 0x0BBB20C0 0x0D3F3C06 0x08057C06 49 0x07FCA0C0 0x0834A0C0 0x03AC3C06 0x0E393C06 50 0x05D6E0C0 0x0A27A0C0 0x046CFC06 0x0A94FC06
Tabl e 3-11: LFSR Ini t Patterns for di fferent codes
3.4.3.2 Primary Code Memory
Each channel contains 2x5120 bit memory for primary codes. The memory has a widt h of 8 bit , which result s in t he smallest ASIC die area and therefore saving gate count compared t o a 32bit organized on chip memory. The t wo memories can be coupled together in order to have one large code memory wit h 10240 bit s. This can be done by configuring the Length field in the PrimCodeRAM1 register beyond 5120bits. The primary code memory is clocked wit h t he Primary Rate. Whenever the current pointer reaches the length pointer, the current pointer returns t o zero and t he St art of Epoch signal is generated. When the StartCM1 or StartCM2 bit of the CodeGenUnitCtrl register is set , t he current pointer is set equal to the offset pointer once and the current pointer starts moving with the next code generat or t rigger, which can be either the Integration Epoch or the Measurement Epoch depending on t he programming of t he Trigger bit in the CodeGenUnitCtrl register. In the time between setting the StartCM1 or StartCM2 bit and wait ing for t he trigger (IE or ME), the code memory is paused and is outputting the value of the chip corresponding to Offset. Not e t hat typically the user wants to align the Integration Epoch (IE) with the Code Epoch. This can be achieved by set t ing t he bit ResetAtStartofEpoch in the CorrUnitCtrl register to reset the accumulators and the counters for t he Int egrat ion Epoch at the time instance "Start of Epoch". Please take into account that two consecutives Integration Epoch (IE) can occur close together if synchronising to the Code Epoch. It is valid to set the two bits StartCM1/StartCM2 together with ResetAtStartofEpoch in order to minimize the setup t ime of t he code memory. However it is import ant t hat t he StartCM1 or StartCM2 bit is writ t en before t he ResetAtStartofEpoch bit .
Start of Epoch
Primary Rate
From uP I/F
Memory
O
L
F
E
F
N
S
G
E
T
T
H
Current Pointer
Primary Code Memory
Primary Code Out
Fi gure 3-38: Pri mary C ode Memory
The offset pointers as well as the length pointers are located in the PrimCodeRam1Ctrl respectively PrimCodeRam2Ctrl regist er and can be set by software. If the two RAM's are coupled together, the length and offset pointer are configured via PrimCodeRam1Ctrl. The settings in PrimCodeRam2Ctrl have no influence in this case. Note that the length as well as t he offset pointer can address not only byte wise, but also bit wise. Note also that the offset pointer always has t o be smaller or equal t han t he lengt h point er. Ot herwise t he out put of t he Code Generat or is invalid.
Figure 3-39 depicts how the code chips have to be written into the PrimaryRAM1/2 in order that they are output in t he correct order.
Data0 31
...
1 2 3 4 5 6 7 8 Chip Indexes 8 7 6 5 4 3 2 1 0 Bit Numbers
Data1 31
...
9 10 11 12 13 14 15 16 Chip Indexes 8 7 6 5 4 3 2 1 0 Bit Numbers
Fi gure 3-39: Data O rgani zati on of C ode RAM
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To ensure proper operation, the primary RAM should be configured as follow: first the length and offset point ers have t o be set and after this the start bit has to be set. From there on it takes 2 CoreClk cycles until one single code RAM or bot h RAM's coupled to one single RAM are ready to start. If both code RAM's are used separately it takes 4 CoreClk cycles unt il t hey are bot h ready t o st art .
It is guaranteed by the hardware that the trigger can not start the code memories until they are not ready. However if the t ime between setting the start bit and t he next t rigger is less t han 2 CoreClk cycles (one RAM single/coupled) respectively 4 CoreClk cycles (two single RAM's), the trigger is missed and the next trigger start s t he Code RAM(s).
Not e that for the code RAM, code lengths smaller than 16 chips are not possible due to timing constraints. That means if t he code length is programmed to values 0..15 the code RAM is disabled. In that case the output of the code RAM is a const ant one, no mat t er what is writ t en in t he code RAM.
Not e that a proper use of t he Code RAM's is only guarant eed if a channel is enabled in t he ChActivation0 and ChActivation1 regist ers.
3.4.3.3 Secondary Code Memory
Each channel contains 2x100 bit memory for secondary codes. The memory has a widt h of 8 bit , which result s in t he smallest ASIC die area and therefore saving gate count compared to a 32bit organized on chip memory. Each memory is clocked with the Secondary Rate. The Secondary Rate is generated by dividing the Primary Rate by a 14 bit int eger number. The divider can be programmed via the Divider field in the SecCodeRamCtrl register. Each secondary memory has it s own divider in order to have independent Secondary Rat es for t he t wo memories (see also Figure 3-33). Whenever the current pointer reaches the length pointer, the current pointer returns to zero. Addit ionally t he current pointer of each secondary code memory can be set to the offset pointer with the next StartOfEpoch signal. If an offset is writ t en (by writing the the Offset field in the SecCodeRam1Ctrl or SecCodeRam2Ctrl register), the next step is to set the ResetSCM1 or ResetSCM2 bit in the CodeGenUnitCtrl register. Then at t he next StartOfEpoch signal, t he current pointer will start reading the secondary code from the offset on. The offset value always is the offset from t he st art of t he secondary code RAM. If the offset pointer is read it returns the current point er posit ion. This is helpful for t he secondary code acquisition. Note that the offset pointer always has t o be smaller or equal t han t he lengt h point er. Ot herwise t he out put of t he Secondary Code is invalid.
Also t he lengt h point er can be set by t he programming of t he Length field in t he SecCodeRam1Ctrl or SecCodeRam2Ctrl register. Other than the offset pointer, the length pointer becomes effective immediat ely. It is also valid t o change the length pointer during runtime. A programmed length of "0" disables the secondary code RAM and a const ant "0" is coming out .
The data is organized the same way as it is done for the primary code. Therefore Figure 3-39 also applies for t he SecondaryRAM1/2 memory.
Not e that a proper use of the Secondary Code RAM's is only guaranteed if a channel is enabled in t he ChActivation0 and ChActivation1 regist ers.
Reset at Start of Epoch
Secondary Rate
From uP I/F
Memory
O
L
F
E
F
N
S
G
E
T
T
H
Current Pointer
Secondary Code Memory
Figure 3-40: Secondary Code Memory
Sec Code Out
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Start Condition: 1 Sec. Code Chip = 2 Prim. Code Chips Sec. Code Length = 4
Primary Code Epochs
Secondary Code Epochs 3 4 13 4 1 2 3 1
Write Conditions
Offset = 3
Length = 3
ResetSCM = 1
3.4.3.4 BOC Processing
The BOC register can hold up to 2 bit of a BOC sequence (e.g. "10"). Sin and cosine BOC pat t erns can be generat ed (more details see Figure 3-41). The BOC/Primary chip rat io can be programmed by t he 4 bit BOCDivider in t he CodeGenUnitCtrl regist er. That way a wide range of BOC(n,m) codes can be processed.
Values writ ten in the following registers fields: BocPattern, BOCDivider become effective either immediat ely or wit h t he next Integration Epoch, depending on theBOCEffectivebit. This allows swit ching mode without losing t rack, e.g. from single side band processing t o dual side band processing.
In case of even BOC division ratios (e.g. 2,4,6,...) the BOC sequence is synchronized with every primary chip, while for odd BOC division ratios (e.g. 1,3,5), the BOC sequence is synchronized only with every even primary chip (e.g. 0,2,4,...). Note that in this case the continuous synchronization works properly starting at the next StartOfEpoch event , since t he hardware uses t his t o dist inguish bet ween even and odd primary chips.
Primary Chips BOC(sin) bits BOC(cos) bits
Figure 3-41: BOC Sine and Cosine Logic
The BOCRat e(sin) is generated whenever the code NCO accumulator is full and has a wrap around at the 32bit border. The BOCRat e(cos) is generated whenever the code NCO accumulator MSB t oggles after it has wrapped around at t he 32bit border. Therefore BOCRate(sin) and BOCRate(cos) are shifted 180° against each ot her or 90° relat ive t o t he primary chip as depict ed in Figure 3-41.
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3.4.3.5 Code Rate Generator
Code Rate Generator
CodeNCOFreq from Aiding Unit
(CodeAidFreq+CodeSwFreq)
CodeNCOFreq
+
CodeSwShiftSteps
0
Next IE
1 Immediate
2 Repeated IE
CodeSwShiftMode
CodeSwShift
= not accessible by SW = Read access by SW = Read/Write access by SW
BOCRate(sin) BOCRate(cos)
from prev.
from prev.
channel
channel
IE ME
NCO Accu
IE_CodePhase ME_CodePhase
0
1
CodeSel
BOCRate(sin) BOCRate(cos)
Fi gure 3-42: C ode Rate Generator Archi tecture
The Code Rate Generator architecture is depicted in Figure 3-42. The code frequency increment (CodeNCOFreq) value is coming from the Code Aiding Unit. It is the summation of CodeAidFreq and CodeSwFreq. (further details see Code Aiding Unit chapter 3.4.6.1). Besides the code frequency also the code phase can be adjusted. Ot her t han AGGA-2/3, t he code phase shifts are not limited to 1/4 and 1/16 of a chip. The code phase shift can be programmed via the regist er CodeSwShift and can be any signed number within 32bit. However the user has t o t ake care t hat t he summat ion of CodeNCOFreq and CodeSwShift is not less than 0 and not more than 232. Otherwise the outcoming BOCRate is invalid. Also t he code phase is observable with all 32bits. Therefore AGGA-4 offers the possibility of soft ware slaving. That means that the code phase of two or multiple channels (which can, but don't have t o be adjacent ) can be exact ly synchronized. The 32bit code phase is latched at Integration and Measurement Epoch in t he corresponding regist ers (IE_CodePhaseand ME_CodePhase). Besides this the current code phase can be read at any t ime by reading t he CodeSwShift regist er.
For acquisition it is helpful to have the possibility to shift the code phase for several chips. This can be achieved wit h t he 22bit CodeSwShiftSteps field of the NCOSettings register. . If CodeSwShiftSteps is not zero, than t he CodeSwShift value is added CodeSwShiftSteps times to the Code NCO accumulator with every CoreClk. Therefore it might t ake CodeSwShiftSteps CoreClk cycles until the whole code phase shift is done. Also the user has t he possibilit y t o select when t he single or multiple code phase shift is applied. This can be select ed by t he CodeSwShiftMode field in t he NCOSettings register. There is the possibility to do the single/multiple code phase shift "once immediately" or "once at next integration epoch" or "repeated at integration epoch". If "repeated at integration epoch" is selected the user has t o t ake care that the single/multiple code phase shift lasts shorter than the integration epoch period. Ot herwise t he code phase shift operation can not work as int ended. The repeat ed mode can be st opped by programming eit her t he CodeSwShift or t he CodeSwShiftSteps regist er t o zero.
The CodeSwShift is a signed value and can therefore be applied in both directions (forward and backwards) wit h t he above ment ioned limit at ions (CodeSwShift + CodeNCOFreq bet ween 0 and 232).
Figure 3-43 is a timing example showing how t he different modes behave. Note that the example is not represent at ive concerning the distance between the adjacent IE's. In reality the distance would change due t o t he Code Phase Shift . Not e also t hat t he example assumes a programmed value of "2" for t he CodeSwShiftSteps regist er.
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CodeSwShiftMode
IE
IE
IE
Once
Immediate
12
CPU Write of CodeSwShift
IE Once at next IE
IE
IE
12
CPU Write of CodeSwShift
Repeat at IE
IE
IE
IE
12
12
CPU Write of CodeSwShift
Fi gure 3-43: C ode SW Shi ft O perati on Ti mi ng Exampl e
IE
IE
IE 12
Note : If the CodeNCOFreq is zero (which is the case after a channel reset or if the CodeNCOFreq was intentionally set t o zero), there is no more BOCRate coming out of the Code Rate Generator. Therefore also t he Int egrat ion Count er can't count BOCRate cycles and thus an Integration Epoch will never occur. If in this case CodeSwShiftMode would be
set to "0-new values become effective with next IE", then new values for the code NCO would never become effective, since no Integration Epoch would ever occur. Therefore in this particular case the CodeSwShiftModehas to be set to "1new values become effective immediately" until the CodeNCOFreq has the desired value. Then Integration Epochs will
occur and t he CodeSwShiftMode can be set back t o "0" if desired.
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3.4.3.6 Code Generator Unit Configuration Examples:
Please note that in the following example tables (Table 3-12 - Table 3-17) a "X" indicat es t hat t he set t ing does not necessarily have t o be "0" or "1", but can be chosen upon t he users desires (e.g. Delay Line Spacing, et c).
3.4.3.6.1 GPS C/A Code Generation
The GPS C/A Code is 1023 chips long and can be generated either wit h t he LFSRs of t he VFCG, t he primary code memory1 or the primary code memory2. If produced via LFSR the VFCG is configured to use two LFSR stages wit h a lengt h of 10 at a rat e of 1.023 MHz. The polynomials t o generat e GPS C/A code are t he following:
· G1= 1 + x3 + x10 · G2 = 1 + x2 + x3+ x6 + x8+ x9 + x10
The following settings depict an example of how to configure the Code Generator Unit in order t o generat e GPS C/A code PRN-1 via t he VFCG.
Register
MSB
Setting
CodeGenUnitCtrl (20bit)
0000 0000 0000 0000
PrimCodeRam1Ctrl (28bit)
0000 0000 0000 0000 0000 0000
PrimCodeRam2Ctrl (26bit)
00 0000 0000 0000 0000 0000
SecCodeRam1Ctrl (28bit)
0000 0000 0000 0000 0000 0000
SecCodeRam2Ctrl (28bit)
0000 0000 0000 0000 0000 0000
VFCGExtTaps (28bit)
0110 0101 1100 0000 1000 0001
VFCGInit (28bit)
0011 1100 0000 0011 1000 0000
VFCGLength (28bit)
0000 1111 1111 1000 0011 1111
DelayLineCtrl (26bit)
XX XXXX XXXX XXXX XXXX XX00
CorrUnitCtrl (17bit)
X XXXX XXXX XX00
Table 3-12: Example set t ings for GPS C/A code PRN-1 via VFCG
LSB 100X 0000 0000 0000 0000 0000 0000 1110 00XX 0001
Not e that in the previous example it was assumed that the user wanted to synchronize the int egrat ion count wit h t he code epoch. Therefore t he "ResetAtStartofEpoch" bit in CorrUnitCtrl regist er was set .
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3.4.3.6.2 GPS L2C Code Generation For t ime multiplexed codes, the BOC registers can be used. For GPS L2C for example the BOC Clock Divider will be programmed in a way that the BOC Rate is twice the Primary Rate. The VFCG is configured t o produce L2CL while Code Memory2 is configures to produce L2CM. Additionally the GPSL2CEn bit in the CodeGenUnitCtrl register has to be set . This causes t hat t he BOC regist er out put is not mult iplied ont o t he primary codes, but is forwarded as enable/disable control into Code Output2. Also it causes that the Outputs of the VFCG and t he Primary Code RAM are t ime mult iplexed and rout ed t o Code Out put 1. By programming the BOCPattern field in the CodeGenUnitCtrl register it can be det ermined which chip of t he t wo mult iplexed chips is enabled and which is disabled later on in the multiplier. A "1" in the BOCPattern field enables the chip lat er on in t he mult iplier, a "0" disables it .
The L2C signal cont ains t wo codes of different lengt h: · L2CM cont aining 10.230 chips wit h a code epoch lengt h of 20 msec · L2CL containing 767.250 chips with a code epoch length of 1.5 sec and synchronized to t he 1.5 sec Z-count
In principle bot h codes can be generat ed via t he VFCG wit h t he following polynomial: · 1 + x3 + x4+ x5 + x6+ x9 + x11+ x13 + x16+ x19 + x21+ x24 + x27
The following table depicts an example of how to configure the Code Generator Unit in order t o generat e GPS L2CM and L2CL code PRN-1. The pilot (L2CL) signal with the VFCG, t he dat a (L2CM) signal wit h t he coupled primary memory. Only the second half of the chip (L2CL) has been enabled. Therefore in the Correlat or Unit all correlat ors would correlate only on the L2CL part, and not on the L2CM part. The only exception is the LL-Q correlator shown in Figure 3-30, which in this example would correlate only on the L2CM part and therefore demodulate the dat a. Also in t his example the StartOfEpoch signal is generated from the code memory and therefore occurs every 20ms rat her t han every 1.5s as it would be t he case for t he L2CL signal.
Register
MSB
Setting
LSB
CodeGenUnitCtrl (20bit)
1000 0010 1101 0001 110X
PrimCodeRam1Ctrl (28bit)
0000 0000 0000 0010 0111 1111 0101
PrimCodeRam2Ctrl (26bit)
00 0000 0000 0000 0000 0000 0000
SecCodeRam1Ctrl (28bit)
0000 0000 0000 0000 0000 0000 0000
SecCodeRam2Ctrl (28bit)
0000 0000 0000 0000 0000 0000 0000
VFCGExtTaps (28bit)
0011 1100 1010 1001 0010 1001 0010
VFCGInit (28bit)
0101 1111 1101 0011 0000 1010 0110
VFCGLength (28bit)
0000 0000 1011 1011 0101 0001 0001
DelayLineCtrl (26bit)
XX XXXX XXXX XXXX XXXX XX00 00XX
CorrUnitCtrl (17bit)
X XXXX XXXX XX11 1001
Table 3-13: Example set t ings for GPS L2C PRN-1 via VFCG and coupled Primary Memory
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3.4.3.6.3 GPS L5 Code Generation The GPS L5 signal is composed of an in-phase data signal and a quadrature pilot signal. Both signals have a 10.23 MHz chip rat e. Bot h L5 codes can be generat ed wit h t wo 13 st age LFSRs wit h t he following polynomials:
· PXA = 1 + x9 + x10 + x12 + x13 · PXB = 1 + x + x3 + x4 + x6 + x7 + x8 + x12+ x13
The L5 in-phase and the L5 quadrature channel share the same generating polynomials. The codes only differ in t he selection of the initialization vector. Additionally the L5-Q signals carries a 20bit secondary code, while the L5-I signal carries a 10bit secondary code.
In order to generate the L5 signal with the VFCG, t he shift register1 generating PXA is shortened to 8190 chips using it s 14 bit count er. The shift regist er2 generat ing PXB is short ened t o 10230 chips using it s 14 bit count er. The reload signal of the second shift register is also used for the first shift regist er since t his generat or must also be reloaded at 10230 chips. This is done by set t ing t he GPSL5En bit of t he CodeGenUnitCtrl regist er. Not e that in the case of GPS L5 the StartOfEpoch signal should be derived from LFSR-2 or t he coupled primary memory (primary memory1) but not from LFSR-1, since the StartOfEpoch signal would then be generated every 8190 chips and not every 10230 chips as int ended.
The following example gives an overview of how to configure the Code Generator Unit in order to generate GPS L5 Q code PRN-1 wit h the VFCG and t he GPS L5 I code PRN-1 in the coupled primary memory. Also it is assumed that t he LL-Q correlator correlates the data signal, while all other correlators correlate on the pilot signal. It is assumed that t he StartOfEpoch signal is generated from the LFSR-2 of t he VFCG. However it would also work if t he StartOfEpoch signal is derived from the coupled primary memory. In that case the StartOfEpochSel bit would have t o be set t o "2" (primary code memory1), since t he coupled primary memory is always addressed by primary memory1.
Register
MSB
Setting
LSB
CodeGenUnitCtrl (20bit)
1000 0000 0010 1101 101X
PrimCodeRam1Ctrl (28bit)
0000 0000 0000 0010 0111 1111 0101
PrimCodeRam2Ctrl (26bit)
00 0000 0000 0000 0000 0000 0000
SecCodeRam1Ctrl (28bit)
1001 1111 1101 0100 0000 0001 0011
SecCodeRam2Ctrl (28bit)
1001 1111 1101 0100 0000 0000 1001
VFCGExtTaps (28bit)
1011 0111 0001 1000 0000 0011 0110
VFCGInit (28bit)
0010 1111 0010 1011 1111 1110 1100
VFCGLength (28bit)
1001 1111 1101 0101 1111 1111 1101
DelayLineCtrl (26bit)
XX XXXX XXXX XXXX XXXX XX00 00XX
CorrUnitCtrl (17bit)
X XXXX XXXX XX10 0001
Table 3-14: Example set t ings for GPS L5 PRN-1 via VFCG and Primary Memory 1
Besides t he above configuration the primary code RAM would have to be loaded wit h GPS L5 I PRN#1, the secondary RAM1 would have to be loaded with the 20bit Neuman Hoffman Code for the pilot and t he secondary RAM2 would have t o be loaded wit h t he 10bit Neuman Hoffman Code for t he dat a channel.
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3.4.3.6.4 Galileo E1 Code Generation
The Galileo E1-B and E1-C code are memory based codes. Therefore t he following example shows how t he Code Generat or Unit of a channel can be set up in order to generate E1-C wit h primary memory 1 and E1-B wit h primary memory 2.
Ot her than for shift register based codes, this example is valid for all PRNs of the Galileo E1-B/C family, since the PRN code number is only determined by the content of the memory, not by the content of the AGGA configuration regist er.
Register
MSB
Setting
LSB
CodeGenUnitCtrl (20bit)
0010 0011 0000 1111 010X
PrimCodeRam1Ctrl (28bit)
0000 0000 0000 0000 1111 1111 1011
PrimCodeRam2Ctrl (26bit)
0000 0000 0000 0000 1111 1111 1011
SecCodeRam1Ctrl (28bit)
0011 1111 1110 1100 0000 0001 1000
SecCodeRam2Ctrl (28bit)
0000 0000 0000 0000 0000 0000 0000
VFCGExtTaps (28bit)
0000 0000 0000 0000 0000 0000 0000
VFCGInit (28bit)
0000 0000 0000 0000 0000 0000 0000
VFCGLength (28bit)
0000 0000 0000 0000 0000 0000 0000
DelayLineCtrl (26bit)
XX XXXX XXXX XXXX XXXX XX00 00XX
CorrUnitCtrl (17bit)
X XXXX XXXX XX10 1001
Table 3-15: Example set t ings for Galileo E1 B+C via Primary Memory 1&2
3.4.3.6.5 Galileo E5 Code Generation
The E5A and E5B PRN codes are generated with two 14 stage LFSRs wit h the following polynomials (see also [RD01]):
E5AI and E5AQ share t he same polynomials: · PE5AI1/Q1 = 1 + x + x6 + x8 + x14 · P E5AI2/Q2 = 1 + x4 + x5 + x7 + x8 + x12+ x14
E5BI: · ·
PE5BI1 = 1 + x4 + x11 + x13 + x14 PE5BI2 = 1 + x2 + x5 + x8 + x9 + x12+ x14
E5BQ: · ·
PE5BQ1 = PE5BI1= 1 + x4 + x11 + x13 + x14 PE5BQ2 = 1 + x + x5 + x6 + x9 + x10+ x14
All codes have a 10.23 MHz chip rate. Each code is truncated at a length of 10230 chips resulting in a 1 ms code epoch.
Table 3-16 gives an example how t he Code Generator Unit can be configured in order to generat e Galileo E5A-I and Galileo E5A-Q in one channel. The example uses the VFCG for E5A-Q and the coupled memory code RAM for E5A-I. The example shows t he configurat ion for PRN-1.
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Register
MSB
Setting
LSB
CodeGenUnitCtrl (20bit)
1000 0000 0000 1101 100X
PrimCodeRam1Ctrl (28bit)
0000 0000 0000 0010 0111 1111 0101
PrimCodeRam2Ctrl (26bit)
00 0000 0000 0000 0000 0000 0000
SecCodeRam1Ctrl (28bit)
1001 1111 1101 0100 0000 0110 0011
SecCodeRam2Ctrl (28bit)
1001 1111 1101 0100 0000 0001 0011
VFCGExtTaps (28bit)
0001 1011 0001 0110 0001 0100 0001
VFCGInit (28bit)
1010 0000 1100 1110 0000 1100 0000
VFCGLength (28bit)
1001 1111 1101 0110 0111 1111 0101
DelayLineCtrl (26bit)
XX XXXX XXXX XXXX XXXX XX00 00XX
CorrUnitCtrl (17bit)
X XXXX XXXX XX10 0001
Table 3-16: Example set t ings for Galileo E5A (I+Q) PRN-1 code via VFCG and Primary Memory
Table 3-17 gives an example how t he Code Generator Unit can be configured in order t o generat e Galileo E5B-I and Galileo E5B-Q in one channel. The example uses the VFCG for E5B-Q and the coupled memory code RAM for E5B-I. The example shows t he configurat ion for PRN-1.
Register
MSB
Setting
LSB
CodeGenUnitCtrl (20bit)
1000 0000 0000 1101 100X
PrimCodeRam1Ctrl (28bit)
0000 0000 0000 0010 0111 1111 0101
PrimCodeRam2Ctrl (26bit)
00 0000 0000 0000 0000 0000 0000
SecCodeRam1Ctrl (28bit)
1001 1111 1101 0100 0000 0110 0011
SecCodeRam2Ctrl (28bit)
1001 1111 1101 0100 0000 0000 0011
VFCGExtTaps (28bit)
1000 1100 1100 0100 0100 0000 1011
VFCGInit (28bit)
0001 0110 0110 1011 1100 0000 0110
VFCGLength (28bit)
1001 1111 1101 0110 0111 1111 0101
DelayLineCtrl (26bit)
XX XXXX XXXX XXXX XXXX XX00 00XX
CorrUnitCtrl (17bit)
X XXXX XXXX XX10 0001
Table 3-17: Example set t ings for Galileo E5B (I+Q) PRN-1 code via VFCG and Primary Memory
3.4.4 Code Delay Line Unit (CDLU)
The Code Delay Line Unit in each channel as anticipated in Figure 3-30 and shown in more detail in Figure 3-44 selects and controls the delay to be applied to the code correlators. It generates the Early Early, Early, Punctual, Late and Lat e Lat e (i.e. EE, E, P, L, LL) version of t he select ed code sequence wit hin t he channel. Two Code Delay Lines are implemented within each CDLU allowing the processing of pilot and data signals within one channel and the processing of t ime mult iplexed signals (e.g. GPS L2C) wit hin one channel.
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CodeIn1 (from prev. Ch.)
CGU
DelayLine
CGU
Output-1
Core
ClkIn
Output-2
(from local Ch.) Clk (from prev.Ch.) (from local Ch.)
CodeIn2 (from prev. Ch.)
10
01
OR
CodeInSel GPSL2CEn
DelayLineClkSync (from Time Base)
CodeSwap ClkSel
Divider
0
1
0
1
1
0
CodeOutSel
Delay Line 1
DelayLine Clk
Delay Line 2
01
1
0
CodeOutSel
CodeOut1 (to next Ch.)
22222
EE E P L LL To Multiplier To LL-Q
CodeOut2 DelayLineClkOut (to next Ch.) (to next Ch.)
Fi gure 3-44: C ode Del ay Li ne Uni t (C DLU)
3.4.4.1 Code Input Select
In t he control register DelayLineCtrl there is a bit CodeInSel. If set, the code from the previous channel is t hroughput t hrough t he delay lines, ot herwise t he local generat ed code from t he Code Generat or Unit (CGU).
In t he case of processing GPS-L2C signal (GPSL2CEn = `1' in CodeGenUnitCtrl register), the Code Delay Line 2 will always t ake t he code generat ed in t he local Channel, regardless of CodeInSel.
3.4.4.2 Code Swap
In t he control register DelayLineCtrl there is a bit CodeSwap. If set, the input 1 is routed to Delay Line 2 and the input 2 is rout ed to Delay Line 1, otherwise input 1 is rout ed t o Delay Line 1 and t he input 2 is rout ed t o Delay Line 2.
3.4.4.3 Delay Line Clock Select
In t he control register DelayLineCtrl there is a bit ClkSel. If set, the DelayLineClk for the delay line is coming from t he previous channel, otherwise the DelayLineClk is coming from the local channel. If t he clock comes from t he local channel, t he DelayLineClk signal is comput ed as follow:
DelayLineClk = CoreClk DivRatio +1
where t he DivRatio is 2 bit wide and can be found in the DelayLineCtrl register. Possible values of DivRatio are [0, 1, 2, 3].
In order t o make sure t hat t he delay line clock divider count er st at e is phase coherent over all channels, a synchronizat ion signal DelayLineClkSync is generat ed every 12 CoreClk cycles in t he Time Base module.
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Not e that this synchronization signal only can make sure that the Delay Line clock divider state of different channels is synchronous among the different channels. It can not prohibit the under sampling effect. The under sampling effect is present if a Delay Line Divider other than zero is used. Then t he PRN code coming form t he Code Generat or is
sampled wit h a slowed down clock (which can be asynchronous to the chip edges) and this causes t hat t he PRN code edges can vary up to 3 CoreClk cycles behind the Delay Line compared to the true edge of the PRN code. This jit t er is dependant of the programmed Delay Line Divider. For the following Delay Line Divider values the following jitter has
t o be t aken int o account :
Del ay Line Divider (programmed value) 0
Jitter [C oreC lk cycles] 0
1
1
2
2
3
3
Table 3-18: Delay Line Divider caused Jit t er
3.4.4.4 Delay Line
Each Code Delay Line Unit consists of two identical Delay Lines. Each Delay Line is clocked by t he DelayLineClk signal and consists of five 22 stage shift registers each fed with the selected code sequence. The phase delay bet ween 2 adjacent shift register cells is referred to as one tap. The maximum length of 1 delay line is 110 taps. The delay between Early Early(EE), Early(E), Punctual(P), Late(L) and Late Late(LL) can be programmed individually in 22 steps i.e. 1, 2, 3, ... 21, 22 t aps. This can be done wit h t he Spacing bit field in t he DelayLineCtrl regist er.
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DelayLine Clk
CodeIn
1 2 3 4 5 6 7 .8.. 196 170 181 192 2103 2114 2125
1 2 3 4 5 6 7 .8.. 196 170 181 192 2103 2114 2125
1 2 3 4 5 6 7 .8.. 196 170 181 192 2103 2114 2125
1 2 3 4 5 6 7 .8.. 196 170 181 192 2103 2114 2125
1 2 3 4 5 6 7 .8.. 196 170 181 192 2103 2114 2125
ChipSpacing_EE EE
ChipSpacing_E E
ChipSpacing_P P
ChipSpacing_L L
ChipSpacing_LL LL
CodeOut
Figure 3-45: Delay Line
3.4.4.5 Code Output Select In t he control register DelayLineCtrl there is a bit called CodeOutSel. If set, the output from Delay Line 1 is routed to Code Out 1 of the Code Delay Line Unit and the output from Delay Line 2 is routed to Code Out 2 of the Code Delay Line Unit. If t he CodeOutSel bit is zero, there is a direct bypass from CodeIn1 (coming from the previous channel) to CodeOut1 and from CodeIn2 (coming from the previous channel) to CodeOut2. This is used for hardware slaving of channels.
3.4.5 Correlator Unit
The Correlator Unit anticipated in Figure 3-30 and shown in more detail in Figure 3-46 consists of the Mult iplier, t he 29bit wide Integrator, the 32bit wide Data Collector, the 21bit Integration Counter and the 32bit Cont inuous Count er. The DMA transfer of the integration results is described in chapter 3.4.7.3. The Ant enna Swit ch Cont roller (ASE) int eract ion wit h t he Correlat or Unit is described in more det ail in chapt er 3.6.3.
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Delay Line 1 From Delay Delay Line 2
Punctual
Line Block
Punctual
5x2bit
From
Final Down
2x3bit
Converter
Multiplier
10 x 4bit
EE E
P
L LL
Integrator
10 x 29bit
Data Collect
With DMA to external
RAM
Long Epoch (LE) Integration Epoch (IE)
tartOfEpoch BOC Rate
1/N
Integration Counter
Continuous Counter
Correlator Unit
AE (from Antenna witch Controller)
Figure 3-46: Correlat or Unit
3.4.5.1 Multiplier
In t he Multiplier the sequences coming from the Delay Line Block are multiplied with the signal from t he Final Down Converter. Ten multiplications are processed in parallel since t he I and Q part of t he signal from t he Final Down Converter are multiplied with each of the 5 (EE, E, P, L, LL) code sequences. The paths from the Delay Line Block t o t he Multiplier are 2bit wide. The MSB is always driven by the output of Delay Line 1. If GPSL2CEn = 0, t he LSB is always 0, hence multiplication is by 1 or -1. If GPSL2CEn = 1, the LSB is connected to the output of Delay Line 2 as an enable / disable signal, hence multiplication is by -1, 1 or 0. With this information (enable/disable) t he mult iplier can also output "0". Therefore the multiplier output is 4bit wide, since the output can not only have the values [-7, -5, -3, -1, +1, +3, +5, +7] but also "0".
Please note that the multiplication scheme is slight ly different for Ant enna Swit ch Epoch enabled (ASEEn = 1 in CorrUnitCtrl regist er). This is shown in Figure 3-47 and described in det ail in chapt er 3.6.3.
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Code Sequences from Delay Line Unit
aultiplier EE(0)
E(0)
EE(1)
E(1)
t(0) t(1)
L(0) L(1)
LL(0) LL(1)
'0'
'0'
'0'
'0'
'0'
1
0
1
0
1
0
1
0
1
0
DtSL2CEn
Inphase Signal
3
from FDC
Quadrature Signal 3
from FDC
2
2
2
0
1
2
2
1
0
2 x
x x x x
x x x x
ASEEn
4
EEI
4
EI
4
PI
4
LI
4
LLI
4
EEQ
4
EQ
4
PQ
4
LQ
aultiplier LLQ
CDLSel
x
4
LLQ
AND
LQSel
Direct Punctual Signal
from CDL 1
Figure 3-47: Mult iplier
Direct Punctual Signal
from CDL 2
There is one special multiplier (LL-Q) which can be used for various functions. The following table gives an overview t o t hese funct ions:
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Purpose LL-Q normal operation B/C operation I/Q operation L2C second half operation
IQSel CDLSel Multiplication of
0
0 incoming Q signal
1
2 incoming I signal
0
2 incoming Q signal
1
3 incoming I signal
with ... LL of DL 1 P of DL 2 P of DL 2 P of DL 1 AND inverse of DL2
Comment LL-Q is working like all other multipliers LL-Q is demodulating the data of e.g. E1B LL-Q is demodulating the data of e.g. E5A-I LL-Q is demodulating e.g. L2CM
Table 3-19: Possibilit ies of LL-Q
3.4.5.2 Integration Counter The Integration Counter shown in Figure 3-46 is 21bit wide and clocked with BOCRate. Once it elapses, the Integration Epoch occurs. The Integration Epoch can be phase aligned with the Code Epoch by resetting t he Int egrat ion Count er wit h t he Reset at St art of Epoch signal.
Not e also that the Integration Epoch is automatically phase aligned to the punctual correlat or wit h t he help of a half delay line.
3.4.5.3 Continuous Counter
The Continuous Counter is clocked with BOCRate and is 32 bit wide. A 32bit offset can be added t o t he Cont inuous Count er by writ ing t o t he ContCntOffset regist er. The offset is added wit h t he next Int egrat ion Epoch.
3.4.5.4 Long Epoch (LE)
If t he Long Epoch Divider (i.e. 1/N in Figure 3-46) is programmed to zero t hen t he Long Epoch is disabled and all correlators are working wit h Integration Epoch as usual. The accumulator values are lat ched at Int egrat ion Epoch, t ransferred via DMA and are reset back t o zero.
The Long Epoch Divider can be programmed by writ ing t he LongEpochDiv field in t he IntCountCtrl regist er.
If only the Long Epoch Divider is programmed to any other value than zero, then all accumulators are still latched wit h t he Integration Epoch, transferred via DMA but the accumulators are not reset back to zero. They are reset back to zero wit h t he next Long Epoch.
If t he bit LongEpochLLQ of CorrUnitCtrl register is set in addition to the Long Epoch Divider other than zero, then the LL-Q accumulator is reset back to zero with the Integrat ion Epoch, alt hough t he Long Epoch is act ive. All ot her accumulat ors are reset back whenever t he Long Epoch occurs.
This allows independent integration times for the pilot and the data component. Example: Taking t he Galileo E1B+C Signal, t he data part carries a message @ 250sps. The LL-Q multiplier would process the data part, all other multipliers would process the pilot part. Since a navigation message bit has 4ms width, the Integration Epoch has to be set to values equal or smaller than 4ms in order to catch all symbols correctly. However for the pilot part it might be of int erest t o have longer integration times than 4ms. Therefore the Long Epoch Divider could for example be set to ten. In t his case all accumulator values (besides LL-Q) are integrating over 40ms until the accumulator value get s reset back t o zero.
In order to know when a Long Epoch has occurred, t he firmware can read t he LongEpochReady st at us bit in t he CorrUnitCtrl register. If the bit is set the firmware can know that the IE which just occurred was also a LE. The bit is on for one IE, t hen swit ched off and swit ched on at t he next LE again and so on.
By set ting the bit IntSourceSel bit in the CorrUnitCtrl register to "1", the DMA and GIC are not invoked at every IE, but at every LE. This allows invoking the firmware at the lower LE rate, while collecting autonomously the Navigation Dat a Bits via the Data Collect function (see also 3.4.5.6). The mechanism of the Interrupt Source Selection is depict ed in Figure 3-48.
Channel IntSourceSel
IE
0
LE
1
GIC
1
Delay until DMA is ready
1
0
0
Interrupt registered as IE
DMA used
Fi gure 3-48: Inte rrupt Source (IE or LE) Se l e cti on
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3.4.5.5 Integrator
The Int egrat or (shown in Figure 3-46) has t en 29bit signed accumulat ion regist ers for all 10 correlat ors. An improvement compared to AGGA-2/3 is that the sign bit (bit 28 when counting is started with 0) is also copied t o bit 29-31 by the AGGA-4. Therefore the software does not have to do a sign extension at a high rat e aft er fet ching t he correlat ion values.
The accumulat ors can be lat ched and reset at t he following t ime inst ances: · Int egrat ion Epoch (IE) · Long Epoch (LE) · Ant enna Swit ch Epoch (ASE)
Table 3-20 gives a det ailed overview how t he accumulat ion regist ers are working under all condit ions.
Lat ched in this context means that a snapshot of the current accumulation values is taken at a certain time instance (IE; LE, ASE) and is written into the Integration Epoch Observables (i.e. IE_ValueEE_I, IE_ValueE_I, ..., IE_ValueLL_Q).
Reset in t his cont ext means t hat t he accumulat ors are reset back t o zero.
The charact er "+" in t his cont ext means a logical OR.
reset @
latch @
ASE_En LongEpochLLQ LongEpochDiv = 0 LongEpochDiv != 0
EE (I/Q) E (I/Q) P (I/Q) L (I/Q) LL (I) LL(Q) EE (I/Q) E (I/Q) P (I/Q) L (I/Q) LL (I) LL(Q)
0 0 true false IE
IE
IE
IE
IE IE IE
IE
IE
IE
IE IE
0 0 false true LE
LE
LE
LE LE LE IE
IE
IE
IE
IE IE
0 1 true false IE
IE
IE
IE
IE IE IE
IE
IE
IE
IE IE
0 1 false true LE
LE
LE
LE LE IE IE
IE
IE
IE
IE IE
1 0 true false IE
IE+ASE IE+ASE ASE IE IE IE
ASE IE
ASE IE IE
1 0 false true LE
LE+ASE LE+ASE ASE LE LE IE
ASE IE
ASE IE IE
1 1 true false IE
IE+ASE IE+ASE ASE IE IE IE
ASE IE
ASE IE IE
1 1 false true LE
LE+ASE LE+ASE ASE LE IE IE
ASE IE
ASE IE IE
Table 3-20: Act ion Table for Int egrat or
3.4.5.6 Data Collect
The sign of the LL-Q accumulator is entering a 32bit FIFO with every Integration Epoch. The FIFO is shifted left wise. The user can adjust a collecting length from 1..32 bits depending on the programming of the DataCollectLength field of t he CorrUnitCtrl register. Whenever the data collect length counter elapses, the 32 bit FIFO is copied t o t he regist er DataCollect. Due to the left shift, the latest bit is aligned on the right. The software gets informed about an update of the DataCollect register via t he flag DataCollectReady in t he CorrUnitCtrl regist er. Once t he soft ware reads t he DataCollect register, the DataCollectReady flag is cleared by t he hardware. The IMT value of t he corresponding Int egrat ion Epoch is also t he IMT t ime st amp for t he lat est bit .
By set ting the bit ResetDataCollect in the CorrUnitCtrl register, the current state of the data collect lengt h count er as well as t he 32bit FIFO is cleared wit h t he next Int egrat ion Epoch.
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3.4.6 Aiding Unit
The Aiding Unit can be used for various purposes. If the code and carrier NCOs are updated at a low rat e due t o long int egration epochs an autonomous update of the loop frequency setting according to expected carrier and code dynamics can be performed by t he aiding unit . The Aiding Unit can also be coupled t oget her wit h an ext ernal Inert ial Measurement Unit (IMU). Then the AGGA-4 pin AU_TRIGGER can be used as timing signal from the IMU system t o t he AGGA-4 Aiding Unit in order to coordinate the update of the Aiding Unit coefficients toget her wit h t he ext ernal IMU. In case the aiding unit is updated with the AU_TRIGGER pin, the time instance of AU Trigger is latched into t he regist ers AUT_IMT_MSW and AUT_IMT_LSW. As the signal dynamic influences the carrier frequency and t he code frequency t o a different ext ent , t wo aut onomous aiding modules are implement ed.
The aiding unit shown in Figure 3-49 consists of an autonomous carrier aiding module, an aut onomous code aiding module and a clock generat ion module.
Code Aiding Frequency
Aiding Unit
Code Aiding Module
Carrier Aiding Frequency
Carrier Aiding Module
AidClk
Aiding Clock Generation
Fi gure 3-49: Ai di ng Uni t
Input from Software
ME PPS AU Trigger
CoreClk
3.4.6.1 Code Aiding Unit
The code aiding unit st ruct ure is shown in Figure 3-50 wit h t he following regist ers:
· CodeNCOFreq is t he act ual code NCO frequency
· CodeSwFreq is the code frequency provided by the acquisition or tracking loop programmed in software (SW)
· CodeAidFreq is t he code aiding frequency
· CodeAidAcc is t he code aiding accelerat ion
Note: Please also see chapter 3.4.3.5 to get the relation between the Code Aiding Unit and the CodeSwShift funct ion.
In a first step (this is indicat ed wit h t he "1" next t o t he addit ion circle in Figure 3-50) wit h every AidClk, t he CodeAidAcc value is accumulated in the CodeAidFreq register according to Figure 3-50. As soon as t his is done, in a second step (this is indicated wit h the "2" next to the addition circle in Figure 3-50) the cont ent of CodeAidFreq and CodeSwFreq is added t oget her and writ t en t o t he regist er CodeNCOFreq as a second st ep.
By programming of the CodeAidEn bit in the AidingUnitCtrl register the Code Aiding Unit can be switched on and off, as shown in Figure 3-50. The swit ch command becomes effect ive wit h t he next Int egrat ion Epoch.
Not e: New parameters written into the registers CodeAidAcc and CodeAidFreq become effective eit her wit h t he next Measurement Epoch (ME), Pulse Per Second (PPS), or rising edge of t he AU_TRIGGER, depending on t he programming of the TriggerSel bit in the AidingUnitCtrl register. Note that the external AU_TRIGGER signal has to last at least 4 CoreClk cycles in order t o be correct ly det ect ed.
Also note that reading back the registers CodeAidAcc and CodeAidFreq give not back the value just written int o t hese regist ers but the actual effective value. That means if one writes a value into the register, the system waits for t he next applicable trigger event (either ME, PPS or AU_TRIGGER). Then the value becomes effective and then t he read-back value equals t he value writ t en before.
A new parameter written into the regist er CodeSwFreq becomes effect ive eit her immediat ely or wit h t he next Int egration Epoch, depending on t he programming of t he CodeSwFreqMode bit in t he NCOSettings regist er.
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If new parameters have been written to CodeAidFreq and/or to CodeAidAcc, then CodeAidFreq without the addition of CodeAidAcc is added to CodeNCOFreq with the next trigger event. From there on a combination of CodeAidAcc and CodeAidFreq (according t o Figure 3-50) is added t o CodeNCOFreq wit h every AidClk.
Note : It takes 2 CoreClk cycles aft er t he t rigger unt il t he new value (CodeSwFreq or CodeAidFreq) is added (applicable) in the NCO phase. Example: The SW changes the value CodeSwFreq from 10 to 20 and the trigger is set to IE. The NCO phase accumulat or would do ...10+10+10 IE 10+10+20+20+20+...
The following t able gives t he regist ers, which belong t o t he Code Aiding Unit :
Re gister Name CodeAidAcc CodeAidFreq CodeNCOFreq CodeSwFreq
Register Length Accessible Bits C omment
17 bit
17 bit (R/W)
31 bit
25 MSB (R/W) 6 LSB cleared at write access to the MSB
32 bit
32 bit (R)
32 bit
32 bit (R/W)
Tabl e 3-21: Regi sters of the C ode Ai di ng Uni t
Code Aiding Acceleration
Register Labels:
16
8
0
CodeAidAcc (signed)
Code Aiding Frequency
CodeAidEn
24
16
31
24
16
8
Code NCO Frequency 2
Code Software Frequency
31
24
16
8
1
8
0
0
0
CodeAidFreq (signed) CodeNCOFreq (unsigned) CodeSwFreq (unsigned)
8 Bit
Accessible by the Processor (R/W)
Accessible by the Processor (R)
Cleared at write access to the MSBs
Resolution:
CoreClk/2^45 [Hz] * AidClk [Hz] CoreClk/2^39 [Hz] CoreClk/2^32 [Hz]
Range:
± CoreClk/2^29 [Hz] * AidClk [Hz] ± CoreClk/2^15 [Hz] CoreClk [Hz]
Fi gure 3-50: C ode Ai di ng Uni t
The Code Aiding Unit as depicted in Figure 3-50 can cope with the following Doppler's and Accelerations:
Ranges of Code Aiding Unit @ 100Hz AidClk
Core Clock [MHz]
2,5
25
max Doppler [Hz]
+/-
76,29
762,94
max Acceleration [Hz/s]
+/-
0,47
4,66
Tabl e 3-22: C ode Ai di ng Uni t Ranges
The following formulas have been used to calculate the numbers in Table 3-22:
40 1220,70
7,45
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Max
Doppler
[Hz]
=
±
CoreClk 215
Max
Acceleration
Hz s
=
±
CoreClk 2 29
TAidClk
The resolution is chosen such that the maximum range error due to finite Code Aiding Unit resolution is the following:
Error of Code Aiding Unit @ 1kHz AidClk after 100ms due to finite resolution
Core Clock [MHz]
2,5 25 40
Range Error [mm] due to CodeAidFreq with 1MChip Code Range Error [mm] due to CodeAidFreq with 10MChip Code
+/- 0,13 1,33 2,13 +/- 0,01 0,13 0,21
Range Error [mm] due to CodeAidAcc with 1MChip Code
+/- 0,10 1,04 1,67
Range Error [mm] due to CodeAidAcc with 10MChip Code
+/- 0,01 0,10 0,17
Tabl e 3-23: C ode Ai di ng Uni t Errors due to fi ni te resol uti on
The following formulas have been used to calculate the numbers of Table 3-23:
CodePhaseError
[mm]
due
to
CodeAidFreq
=
CoreClk 239
tupdate
SpeedOfLight CodeFreq
1e3
CodePhaseError [mm] due to CodeAidAcc
= CoreClk 2 45 TAidClk
1 2
t
2 update
SpeedOfLight CodeFreq
1e3
Where tupdate is the update rate at which new aiding values are written by the software. The factor 1e3 is there to bring t he result from meter to millimeter.
3.4.6.2 Carrier Aiding Unit The carrier aiding unit st ruct ure is shown in Figure 3-51 wit h t he following regist ers:
· CarrNCOFreq is t he act ual carrier NCO frequency
· CarrSwFreq is the carrier frequency provided by the acquisition or tracking loop programmed in soft ware
· CarrAidFreq is t he carrier aiding frequency
· CarrAidAcc is t he carrier aiding accelerat ion Note : Please also see chapter 3.4.2 to get the relation between the Carrier Aiding Unit and t he CarrSwShift funct ion. In a first step (this is indicat ed wit h t he "1" next t o t he addit ion circle in Figure 3-51) wit h every AidClk, t he CarrAidAcc value is accumulated in the CarrAidFreq register according to Figure 3-51. As soon as t his is done, in a second step (this is indicated wit h the "2" next to the addition circle in Figure 3-51) the cont ent of CarrAidFreq and CarrSwFreq is added t oget her and writ t en t o t he regist er CarrNCOFreq as a second st ep. By programming of the CarrAidEn bit in the AidingUnitCtrl register the Carrier Aiding Unit can be switched on and off as shown in Figure 3-51. The swit ch command becomes effect ive wit h t he next Int egrat ion Epoch. Not e: New parameters written into the registers CarrAidAcc and CarrAidFreq become effect ive eit her wit h t he next Measurement Epoch (ME), Pulse Per Second (PPS), or rising edge of t he AU_TRIGGER pin, depending on t he programming of the TriggerSel bit in the AidingUnitCtrl register. Note that the external AU_TRIGGER signal has to last at least 4 CoreClk cycles in order t o be correct ly det ect ed. Also note that reading back the registers CarrAidAcc and CarrAidFreq does not give back the value just writ t en int o t hese registers, but the actual effective value. That means if one writes a value into the register, the system waits for the next applicable trigger event (either ME, PPS or AU_TRIGGER). Then the value becomes effective and then t he readback value equals t he value writ t en before.
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A new parameter written into t he regist er CarrSwFreq becomes effect ive eit her immediat ely or wit h t he next Int egration Epoch, depending on t he programming of t he CarrSwFreqMode bit in t he NCOSettings regist er. If new parameters have been written to CarrAidFreq and/or to CarrAidAcc, then CarrAidFreq wit hout the addit ion of CarrAidAcc is added t o CarrNCOFreq wit h t he next t rigger event . As shown in Figure 3-51 from t here on a combinat ion of CarrAidAcc and CarrAidFreq is added t o CarrNCOFreq wit h every AidClk. Note: It takes 2 CoreClk cycles after the trigger until the new value (CarrSwFreq or CarrAidFreq) is added (applicable) in t he NCO phase. Example: The SW changes the value CarrSwFreq from 10 to 20 and t he t rigger is set t o IE. The NCO phase accumulat or would do ...10+10+10 IE 10+10+20+20+20+...
The following t able gives t he regist ers, which belong t o t he Carrier Aiding Unit :
Register Name Register Length Accessible Bits C omment
CarrAidAcc
24 bit
24 bit (R/W)
CarrAidFreq 38 bit
32 MSB (R/W) 6 LSB cleared at write access to the MSB
CarrNCOFreq CarrSwFreq
32 bit 32 bit
32 bit (R) 32 bit (R/W)
Tabl e 3-24: Regi sters of the C arri er Ai di ng Uni t
23
Carrier Aiding Acceleration
Carrier Aiding Frequency Carrier NCO Frequency Carrier Software Frequency
CarrAidEn 31
24
31
24
2
31
24
16 16 16
16
8
1
8
0
8
0
8
0
8 Bit
Accessible by the Processor (R/W)
Accessible by the Processor (R)
Cleared at write access to the MSBs
Register Labels:
0
CarrAidAcc (signed)
CarrAidFreq (signed)
CarrNCOFreq (signed)
CarrSwFreq (signed) Resolution:
CoreClk/2^41 [Hz] * AidClk [Hz] CoreClk/2^35 [Hz] CoreClk/2^32 [Hz]
Range:
± CoreClk/2^18 [Hz] * AidClk [Hz] ± CoreClk/2^4 [Hz] ± CoreClk/2 [Hz]
Fi gure 3-51: C arri er Ai di ng Uni t The Carrier Aiding Unit as depicted in Figure 3-51 can cope with the following Doppler's and Accelerations:
Ranges of Carrier Aiding Unit @ 100Hz AidClk
Core Clock [MHz]
2,5
25
max Doppler [MHz] max Acceleration [Hz/s]
+/-
0,16
1,56
+/-
953,67
9536,74
Tabl e 3-25: C arri er Ai di ng Uni t Ranges
40 2,50 15258,79
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The following formulas have been used to calculate the numbers in Table 3-25:
Max
Doppler
[Hz]
=
±
CoreClk 24
Max
Acceleration
Hz s
=
±
CoreClk 2 18
TAidClk
The resolution is chosen such that the maximum range error due to finite Carrier Aiding Unit resolution is the following:
Error of Carrier Aiding Unit @ 1kHz AidClk after 100ms due to finite resolution
Core Clock [MHz]
2,5
25
40
Phase Error [um] due to CarrAidFreq @L1
+/- 1,38 13,85 22,15
Phase Error [um] due to CarrAidFreq @L5
+/- 1,85 18,54 29,67
Phase Error [um] due to CarrAidAcc @L1
+/- 1,08 10,82 17,31
Phase Error [um] due to CarrAidAcc @L5
+/- 1,45 14,49 23,18
Tabl e 3-26: C arri er Ai di ng Uni t Errors due to fi ni te resol uti on
The following formulas have been used to calculate the numbers Table 3-26:
CarrierPhaseError
[mm] due to
CarrAidAcc
=
CoreClk 241 TAidClk
1 2
tu2pdate
SpeedOfLight CarrierFreq
1e6
Not e: CarrierFreq in the two equations above are the physical carrier frequency (e.g. 1.57542 GHz for L1) and not the value of the register CarrAidFreq.
Where tupdate is the update rate at which new aiding values are written by the software. The factor 1e6 is there to bring t he result from meter to micrometer.
3.4.6.3 Aiding Clock Generation
The Aiding Unit clock (AidClk) is derived by dividing the CoreClk by a 19bit divider. It can be programmed via t he DivRatio field in the AidingUnitCtrl regist er. New writ t en set t ings become effect ive immediat ely. In order t o synchronize the AidClk wit h either the Measurement Epoch (ME), the Pulse Per second (PPS) or AU_TRIGGER, t he int ernal AidClk divider reset is armed whenever the software writes to one of t he following regist ers: CodeAidFreq, CodeAidAcc, CarrAidFreq, CarrAidAcc. Once the reset is armed it will reset at t he next t rigger event (ME, PPS or AU_TRIGGER). The timing event to which the AidClk shall be synchronized to, can be selected by the TriggerSel field in t he AidingUnitCtrl regist er.
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3.4.6.4 Behaviour Examples
The following two figures shall give some examples in order to fully understand the behaviour of the Aiding Unit. The figures use the Code Aiding Unit as an example. However the behaviour is exactly the same for the Carrier Aiding Unit.
Trigger Signal (ME, PPS or AU_TRIGGER)
Trigger Signal (ME, PPS or AU_TRIGGER)
t
Code Aiding Unit Output
AidClk
AidClk
CPU Write of CodeAidFreq(1) CodeAidAcc(1)
AidClk AidClk
AidClk
AidClk
t AidClk
CodeAidFreq(1)
CodeAidFreq(1) + 1*CodeAidAcc(1)
CodeAidFreq(1) + 2*CodeAidAcc(1)
CodeAidFreq(1) + 3*CodeAidAcc(1)
CodeAidFreq(0) + n*CodeAidAcc(0)
CodeAidFreq(0) + (n+1)*CodeAidAcc(0)
t
Fi gure 3-52: Ai di ng Uni t Behavi our Exampl e 1
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1 Aiding frequency generated at 1kHz
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t
2
CodeSwFreqMode (0=with next IE, 1=immediate)
1
0
t
3
CodeAidEn
1
0
t
4 Frequency settings written by tracking loop
t
IE CPU Write
IE CPU Write
IE
CPU Write
IE
CPU Write
IE CPU Write
IE
5 Frequency settings being effective in the channel
t
IE
IE
IE
IE
IE
IE
6 NCO frequency
t
Fi gure 3-53: Ai di ng Uni t Behavi our Exampl e 2
3.4.7 Observables
The channel observables consist of t he Int egrat ion Epoch (IE) observables and t he Measurement Epoch (ME) observables. The Integration Epoch observables mainly consist of the correlation values and the environmental sett ings which caused these correlation values (e.g. NCO settings) used for the acquisition and tracking loops. The Measurement Epoch observables are mainly used to get channel measurements (code/carrier phase) which are taken at the same t ime inst ance for all channels.
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3.4.7.1 Integration Epoch Observables
Regi ster Name U = Unsi gned S = Signed LoopSt at e (U)
Descri pti on
This register is writable and can therefore be used by the software to write data in it, which is t hen transferred (together with the other observables) via DMA into the external RAM. This allows keeping t he cont ext (e.g. loop set t ings) t oget her wit h t he correlat ion values.
IE_IMT_LSW (U) The lower 32bits of the Instrument Measurement Time (IMT) Counter at the time instance of Int egrat ion Epoch.
IE_ValueEE_I (S) The Early Early Inphase correlat ion value. See also Not e-1 below t his t able.
IE_ValueEE_Q (S) The Early Early Quadrat ure correlat ion value. See also Not e-1 below t his t able.
IE_ValueE_I (S)
The Early Inphase correlat ion value. See also Not e-1 and Not e-2 below t his t able.
IE_ValueE_Q (S)
The Early Quadrature correlat ion value. See also Not e-1 and Not e-2 below t his t able.
IE_ValueP_I (S)
The Punctual Inphase correlat ion value. See also Not e-1 and Not e-2 below t his t able.
IE_ValueP_Q (S)
The Punctual Quadrature correlation value. See also Not e-1 and Not e-2 below t his t able.
IE_ValueL_I (S)
The Late Inphase correlation value. Not e: See also Not e-1 and Not e-2 below t his t able.
IE_ValueL_Q (S)
The Lat e Quadrat ure correlat ion value. See also Not e-1 and Not e-2 below t his t able.
IE_ValueLL_I (S) The Lat e Lat e Inphase correlat ion value. See also Not e-1 below t his t able.
IE_ValueLL_Q (S) The Lat e Lat e Quadrat ure correlat ion value. See also Not e-1 below t his t able.
Dat aCollect (U)
This register contains t he dat a bit s which are collect ed wit h every Int egrat ion Epoch.
IE_CodeFreq (U)
If t he CodeFreqSel bit in the CorrUnitCtrl register is one, the observable will reflect only the Code NCO increment caused by the programming of CodeSwFreq (see chapter 3.4.6.1), not including t he aiding component caused by CodeAidFreq.
If t he CodeFreqSel bit in the CorrUnitCtrl register is zero, t he observable will reflect t he Code NCO increment caused by the summation of CodeSwFreq and the aiding component CodeAidFreq.
IE_CarrFreq (S)
If t he CarrFreqSel bit in the CorrUnitCtrl register is one, the observable will reflect only the Carrier NCO increment caused by the programming of CarrSwFreq (see chapter 3.4.6.2), not including t he aiding component caused by CarrAidFreq.
If t he CarrFreqSel bit in the CorrUnitCtrl register is zero, t he observable will reflect t he Carrier NCO increment caused by the summation of CarrSwFreq and the aiding component CarrAidFreq.
IE_CarrObsPhase (S) IE_Cont Count (U)
By default this register contains the 12MSB's of the carrier phase and the 20 bit cycle count (see chapter 3.4.2). If the bit IE_CarrObsSel in the CorrUnitCtrl register is set , t he regist er will contain the whole 32bit of the carrier phase. This allows software slaving of channels, since t he NCO's of t he channels can be phase aligned by soft ware.
This regist er cont ains t he 32bit Cont inuous Count lat ched at Int egrat ion Epoch.
IE_CodePhase (U) This regist er cont ains t he 32 bit code NCO phase lat ched at Int egrat ion Epoch.
Tabl e 3-27: Integrati on Epoch (IE) O bservabl es
Note-1: The sign bit of the correlation values is copied in the upper bits. Therefore the soft ware does not need do no furt her shift ing of t he correlat ion values in order t o correct ly reconst ruct t he t wo's complement values.
Note-2: If Ant enna Swit ch Mode is enabled, t his observable has a special funct ion (see chapt er 3.6.3).
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Regi ster Name U = Unsi gned S= Signed ME_IMT_LSW (U)
Descri pti on
The time stamp of the lower 32bits of the Instrument Measurement Time (IMT) count at t he time instance "Measurement Epoch". Note that this time stamp is t ypically ident ical wit h t he time stamp ME_IMT_LSW hosted in the Channel Matrix. However if channels are slaved, there is one CoreClk cycle delay between the channels for everyt hing. Then also t he ME_IMT_LSW time stamps in t he slaved channels will differ for t his delay.
ME_CarrObsPhase (S)
By default this register contains the 12MSB's of t he carrier phase and t he 20 bit cycle count (see chapter 3.4.2). If the bit ME_CarrObsSel in the CorrUnitCtrl register is set, t he regist er will contain the whole 32bit of the carrier phase. This allows soft ware slaving of channels, since t he NCO's of t he channels can be phase aligned by soft ware.
ME_Int Count (U)
This register contains t he value of t he 21bit Int egrat ion Count at t he t ime inst ance "Measurement Epoch".
ME_Cont Count (U)
This register contains t he value of t he 32bit Cont inuous Count at t he t ime inst ance "Measurement Epoch".
ME_CodePhase (U)
This register contains the 32bit code NCO phase at t he t ime inst ance "Measurement Epoch".
Tabl e 3-28: Measurement Epoch (ME) O bservabl es
3.4.7.3 DMA Transfer of GNSS Observables All channel observables can be transferred via DMA to any destination address. These observables are referred t o as "Raw Samples" in some applicat ions. The GNSS_DMACtrl regist er allows t o select which observable shall be t ransmitted via DMA and which not. Each bit represents one observable. The exact mat ching can be found in t he address t able in chapt er 7.4.5.47. In order t o set up a DMA operat ion, t he following order is recommended: · Clear GNSS_DMACtrl regist er in order t o be sure t hat t he DMA is not working · Configure t he GNSS_DMAStartAddr · Configure t he GNSS_DMACurAddr (t ypically set t o t he same value as GNSS_DMAStartAddr) · Configure t he GNSS_DMAEndAddr · Configure t he GNSS_DMACtrl regist er in order t o enable t he observables t ransfer
Not e that the GNSS DMA area must be seen as a circular buffer. Once the GNSS DMA t ransfer reaches the end address of t he buffer it wraps around and starts again from the start address. Therefore by setting the GNSS_DMAStartAddr and t he GNSS_DMAEndAddr only the borders of the circular buffer are defined. The address in the defined buffer where the DMA shall start to write its observables to is defined by writing to the GNSS_DMACurAddr. Note that typically a DMA current address pointer is read only. In this case (GNSS DMA) it is also writeable. Therefore the DMA transfer can be st art ed at any address which is wit hin t he buffer. The DMA t ransfer is always 32bit wide. By reading t he GNSS_DMACurAddr regist er it ret urns t he address of t he next free 32bit dat a element . If DMA is enabled, the Integration Epoch strobe is not directly routed from the GNSS core to the Interrupt Cont roller, but is delayed until the DMA transfer is finished to make sure that the DMA is ready if the soft ware get s invoked via int errupt. Note that only the notification to the software is delayed, not the Integration Epoch it self. The Int egrat ion Epoch observables cont ain of course t he dat a belonging t o t he t ime inst ance "Int egrat ion Epoch". Also note that the DMA is intended to transfer Integration Epoch Observables. Therefore the GNSS DMA is t riggered solely by the Integration Epoch. However since the Measurement Epoch Observables are just behind t he Int egrat ion Epoch Observables (from an address point of view) it is also possible to transfer the Measurement Epoch Observables by means of DMA at t he Int egrat ion Epoch t ime inst ance.
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The t iming of t he DMA process is as follow:
If any bit in the GNSS_DMACtrl register is switched on, it takes 11 CoreClk cycles to intit ialize t he DMA. Then t he hardware steps through the GNSS_DMACtrl register. It starts wit h Bit0 (IntLoopState) and it takes one CoreClk cycle to check whether a DMA transfer of this observable is requested or not. If it is request ed it t akes 5 CoreClk Cycles t o t ransfer each observable into the DMA FIFO of depth 32. If it is not requested it will step to the next bit (IE_MT_LSW) and decide once more (one CoreClk cycle) if t his observable has t o be t ransferred or not .
Once t here is a value in t he FIFO, t he AMBA bus is request ed and it t akes minimum 9 SysClk cycles unt il t he observable arrives at the destination (e.g. external RAM). Note that the AMBA bus can be blocked by inst ances wit h higher priority than the DMA. In this case the 9 SysClk cycles are exceeded. After t he DMA t ransfer of a part icular channel is finished it t akes 3 CoreClk cycles t o end t he DMA process.
The DMA t iming behaviour is depict ed in Figure 3-54.
Init DMA start
11 cycles
Check Transfer observable Check Transfer observable
Bit0
to DMA FIFO
Bit1
to DMA FIFO
if Bit0 is set
if Bit1 is set
1
5 cycles
1
5 cycles
1
Check Transfer observable
Bit22
to DMA FIFO
if Bit22 is set
1
5 cycles
end
3
CoreClk Cycles
Always executed
Once first observable
is in FIFO
Only executed if corresponding bit in register in GNSS_DMACtrl is set
repeated 23 times, once for each bit in GNSS_DMACtrl
min. 9 SysClk cycles
min. 9 SysClk cycles
Observable is transferred via AMBA bus. This process can be blocked at any time and
delayed indefinitely.
Figure 3-54: DMA Timing Behaviour
Example: In order to transfer all IE correlator values together wit h the time stamp via DMA in a syst em wit h 40 MHz CoreClk and SysClk at DMA rate of 1kHz, the GNSS_DMACtrl register would have to be configured t o 0x00000FFE. Then it would t ake:
11 CoreClk cycles t o init ialize t he DMA
23 x 1 CoreClk cycles t o st ep t hrough t he regist er GNSS_DMACtrl
11 x 5 CoreClkcycles t o t ransfer t he observables int o t he FIFO
11 x 9 SysClk cycles t o t ransfer t he observables out of t he FIFO t o t he dest inat ion (e.g. ext ernal RAM)
Not e: For timing calculations it has to be taken into account that the 11x5 transfer and t he 11x9 t ransfer are done in parallel, hence the spacing between two successive transfers of one channel is at least 5 CoreClk or 9 SysClk cycles (whichever is longer), possibly ext ended by wait st at es or ot her act ivit y on t he AHB bus.
In t he case of DMA transfers at the same time, these are going to be processed sequentially, st art ing from channel-0 and finishing wit h channel-35.
Not e: There is no risk that one processes the IE interrupt while t he DMA is st ill running, since t he IE int errupt is not ified t o t he GIC only if t he DMA for t hat channel is finished.
The dat a amount would be 11 x 32bit per millisecond, which is 352 kBit /s.
3.4.7.4 Timing Notes about GNSS Observables Whenever the Code NCO 32bit phase has a wrap around, the Int egrat ion Epoch count er is increased by one. If it reaches the programmed level, the Int egrat ion Epoch Count er will signal t he Integration Epoch (IE) and t he IE observables are latched. However from the point in time when the code NCO signals the wrap around until the latching of t he IE observables it t akes exact ly 3 CoreClk cycles.
The Measurement Epoch latching is artificially delayed by 3 CoreClk cycles so t hat bot h t ime lines ME and IE are consist ent .
Example: If in one channel t he IE would coincide wit h t he ME t han t he channel observables would be:
ME_IMT_LSW = IE_IMT_LSW and
ME_CodePhase = IE_CodePhase
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3.4.8 Channel Slaving Concepts
Up t o 36 channels can be slaved t oget her. There are t wo ways of slaving channels: · Hardware Slaving (known also from AGGA-2) · Soft ware Slaving (new)
Besides t his there are different applications where slaving is useful. Some of them will be treated in this section in order t o get familiar wit h t he slaving concept s. The cases which are t reat ed as examples are:
· At t it ude Det erminat ion · Fast Acquisit ion / Mult ipat h Det ect ion · Correlat ion Funct ion Probing
3.4.8.1 Hardware/Software Slaving
It has to be noted that Hardware and Software Slaving are not fully equivalent t o each ot her. Bot h met hods have advant ages and disadvant ages.
Hardware Slaving means that the signal (e.g. Carrier Frequency, Code Frequency, PRN Code, etc) is slaved to the next channel via hardware. The software configures the slaving once and then the information from t he mast er channel is spread to the slave channels without interaction from software. The restriction is that only subsequent channels can be slaved. That means it is for example possible to slave channels 1,2,3,4 but not 1,3,4,5, since the chain is int errupt ed at channel 2.
Soft ware slaving means that the software is copying the relevant information (Carrier NCO word, Code NCO word) t o t he slave channels. The advantage is that any channel can be slaved, also if the channels are not subsequent . Anot her advantage is that the software can apply modifications to the slaved values and by thus e.g. apply an offset to the copied NCO word. The disadvantage however is an increase in CPU load and that not everything can be slaved via soft ware.
If Hardware Slaving is used it has to be noted that there is one CoreClk delay in t he slaved signals. This can also be seen in Figure 3-30. This "one CoreClk delay" feature is necessary in order to make sure that the signals from t he first channel can be slaved up t o t he last channel wit hout problems in signal propagat ion t ime.
The following t able gives an overview of t he signals which can be slaved from channel t o channel:
Signal to slave Input Data ME PPS Carrier Delay Clock Code Out 1 Code Out 2 Primary Rate BOC Rate (cos) BOC Rate (sin) LE IE ASE
Hardware InputSel = 12 TimeBaseSel = 1 TimeBaseSel = 1 CarrSel = 1 CodeSel = 1 CodeSel = 1 CodeSel = 1 CodeSel = 1 CodeSel = 1 CodeSel = 1 IntEpochSel = 1 IntEpochSel = 1 TimeBaseSel = 1
Software N/A N/A N/A Yes (copy) Yes (config), but Restriction Yes (config) Yes (config) Yes (copy) Yes (copy) Yes (copy) Yes (config) Yes (config) N/A
Tabl e 3-29: Sl avi ng possi bi l i ti es
The table has to be read as follow: If Hardware slaving is chosen, the Input Dat a has t o be delayed by one CoreClk
cycle, since also the local signals (e.g. Carrier, Code) are delayed by one CoreClk cycle. This is also t rue for t iming signals like PPS, ME and ASE. However in case of software slaving this is not applicable, since there is no delay in t he signals (e.g. Carrier, Code) between the channels. Therefore also the input data and timing signals must not be delayed.
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The Carrier for example can be slaved via Hardware if t he bit CarrSel in t he ChannelCtrl regist er is set t o 1. Alt ernatively it can be slaved via software. Then the software has to adjust the carrier NCO phase once and from t here on just copy the carrier NCO word (frequency) from the master channel to the slave channel. The carrier phase of t wo channels can be synchronized with the help of the ME_CarrObsPhase register. It can be configured such that all 32bit s of t he Carrier NCO phase are accessible. From that observable the phase difference of t wo channels can be read out . This phase difference can t hen be adjust ed wit h t he help of t he CarrSwShift regist er.
The Delay Clock can be slaved via Hardware Slaving by setting t he CodeSel bit in t he ChannelCtrl regist er t o 1. Alt ernatively it can be slaved via software in that sense that the Delay Line is configured the same in the slave channel t han in the master channel. Note that it is not possible with software slaving to build up a correlator chain, meaning that one delay line is chained wit h a delay line from anot her channel.
The PRN code can be slaved via Hardware Slaving by set t ing t he CodeSel bit in t he ChannelCtrl regist er t o 1. Alt ernatively it can be slaved via software in that sense that the Code Generator is configured t he same in t he slave channel t han in t he mast er channel.
The PrimaryRate, the BOCRate(cos) and BOCRate(sin) are all derived from the Code NCO word. The Code NCO word for example can be slaved via Hardware if the bit CodeSel in the ChannelCtrl register is set to 1. Alternatively it can be slaved via software. Then the software has to adjust the code NCO phase once and from t here on just copy t he code NCO word (frequency) from t he mast er channel t o t he slave channel. The code phase of t wo channels can be synchronized wit h the help of the ME_CodePhase register. From that observable the phase difference of t wo channels can be read out . This phase difference can t hen be adjust ed wit h t he help of t he CodeSwShift regist er.
The Integration Epoch and Long Epoch can be slaved via Hardware Slaving by set t ing t he IntEpochSel bit in t he ChannelCtrl register to 1. Alternatively the Integration and Long Epoch can be configured via soft ware in t he slave channel such t hat t hey are equal or cont rollable delayed t o t he one in t he mast er channel.
3.4.8.2 Examples For Attitude Determination typically two or more channels are slaved together. The signal is t racked on t he mast er channel and all slave channels should behave the same like the master channel (Carrier NCO, Code NCO, Code). Then it is possible t o read out t he phase difference from t he I/Q correlat ion values of t he slave(d) channel(s). In case of Hardware Slaving t he following bit s would have t o be in t he ChannelCtrl regist er:
· CarrSel = 1 · CodeSel = 1 · IntEpochSel = 1 · TimeBaseSel = 1 · InputSel = 12 Addit ionally the Delay Line must be configured such that the correlators in the slave channel(s) see the same PRN code phase than the correlators in the master channel (see 3.4.4 Code Delay Line Unit (CDLU)). Also in the slave channels t he correlators can be configures special if Hybrid At t it ude Mode is used (see 3.6.3 Ant enna Swit ch Correlat ion Result s).
Since t here is always one CoreClk delay between the slaved signals (e.g. Carrier, Code), also the incoming dat a has t o be delayed by one CoreClk cycle (InputSel = 12) in order to maintain the phase relation bet ween local dat a and input dat a.
For Fast Acquisition and Multipath Detection it might be of interest to have many correlators slaved together. In t his case, the same configuration of the ChannelCtrl register should be used t han in t he At t it ude Det erminat ion Case. However the Delay Line would have to be configures such that the correlat ors are not working parallel (like in t he At t it ude Det erminat ion Case), but are chained (see see 3.4.4 Code Delay Line Unit (CDLU)).
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3.5 Time Base Generator
The Time Base Generator anticipated in Figure 3-1 produces the Epoch Clock (EC), the Measurement Epoch (ME), and t he Pulse-Per-Second (PPS). Also it provides the Instrument Measurement Time (IMT) as well as an ext ernal clock Int erface. The Time Base Generat or is depict ed in Figure 3-55.
Time Base Generator
PPSI (Pin)
Synchronizer
EXT_CORE_CLK (Pin)
EC Divider
Epoch Clock
MEI (Pin)
Synchronizer
ExtInputEn
PPS Divider
Reset
1 PPS
0 SyncEn
ME Divider
0 ME
1
ExtInputEn
IMT Counter /12 Divider
PPS IMT Latched
ME IMT Latched
AU Tr. IMT Latched
ASE IMT PLD 5I IMT PLD IQ IMT
Latched
Latched
Latched
LatchAtPPS
OutputEn 1 0
PPSO (Pin)
0 1 OutputEn
MEO (Pin)
EC PPS ME AU_TRIGGER (Pin) IMT
LatchAtME
DelayLine ClkSync
EXT_CLK (Pin)
1
ExtClk Counter
0
SignalSel
ExtClk Counter Latched
LatchAtExtClk
ASE
PLD 5I
PLD IQ
Fi gure 3-55: Ti me Base Generator Bl ock Di agram
3.5.1 Epoch Clock (EC)
The EC Divider is used to divide the CoreClk and to output the Epoch Clock. This is a divider with a 17 bit integer part and a 10 bit fractional part and can be programmed via the EpochClkDiv register. Note that the int eger part has t o be programmed with the desired value -1. New settings written to the Epoch Clock Divider become effective with the next Epoch Clock. The Epoch Clock is used for the generation of the ME, the PPS and t he Ant enna Swit ch Epoch (ASE) st robe. Example: Assuming a CoreClk of 30,456285 MHz and a desired Epoch Clock of 1 kHz, t he division rat io would be 30456,285. The value which would have to be programmed is 30456 1 = 30455 for the integer part and 0.285 * 1024 = 291.84 => 292 for t he fract ional part .
3.5.2 Measurement Epoch (ME)
The Measurement Epoch is used to sample the observables of all channels and t o synchronize t he measurement s of mult iple AGGA's if more t han one AGGA is used. T he ME Divider is used to divide the Epoch Clock and to output the Measurement Epoch. This is a programmable 14 bit divider. It is programmed via t he DivRatio field of t he MESettings regist er. Not e t hat t he divider has t o be programmed wit h t he desired value 1 and t hat new set t ings become effect ive wit h t he next ME event . The Measurement Epoch can be selected from an internally generated Measurement Epoch or an external input (MEI: Measurement Epoch Input). This can be selected by the ExtInputEn bit in the MESettings register. If the external input
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is used a synchronizer will synchronize the external MEI signal with the internal CoreClk. Internally t he ME signal is rout ed to the instances (e.g. channel), but it is also available as an output port (MEO: Measurement Epoch Output). The int ernal ME signal is asserted for one CoreClk cycle, while the external MEO signal is asserted for 128 CoreClk cycles. Ot her than in AGGA-2, the MEI has not t o be connect ed ext ernally t o t he MEO if only one AGGA-4 is used. In receivers with multiple AGGA-4s all MEI should be connect ed t o t he MEO from one AGGA-4, referred t o as t he mast er AGGA-4 in order t o ensure t hat all channels in t he receiver use t he same Measurement Epoch (ME).
The OutputEn field of the MESettings register controls whether the MEO signal is enabled or const ant ly de-assert ed. It is also possible t o generat e an int errupt for t he Measurement Epoch (see chapt er 4.12.2). The ME t ime inst ance is lat ched t o t he regist ers ME_IMT_MSW and ME_IMT_LSW. Not e: If MEI is used it takes 4 CoreClk cycles from the rising edge of the MEI input signal unt il t he lat ching of t he corresponding IMT value. Not e: If MEI is used t hen t he difference bet ween MEI and MEO is 3 t o 5 CoreClk cycles.
3.5.3 Pulse Per Second (PPS)
The PPS out put is int ended for synchronizing ext ernal equipment t o t he receiver t ime. The PPS Divider is used to divide the Epoch Clock and to output the Pulse Per Second. This is a programmable 14 bit divider. It is programmed via the DivRatio field of the PPSSettings register. Note that the divider has to be programmed wit h t he desired value 1 and t hat new set t ings become effect ive wit h t he next PPS event . The Pulse Per Second can be selected from an internally generated Pulse Per Second or an external input (PPSI: Pulse Per Second Input). This can be selected by the ExtInputEn bit in the PPSSettings register. If the external input is used a synchronizer will synchronize the external PPSI signal with the internal CoreClk. Internally the PPS signal is rout ed t o t he instances as PPS signal, but it is also available as an output port (PPSO: Pulse Per Second Output). The internal PPS signal is asserted for one CoreClk cycle, while the external PPSO signal is asserted for 128 CoreClk cycles. Other t han in AGGA-2, t he PPSI does not need to be connected externally to the PPSO if only one AGGA-4 is used. In receivers wit h multiple AGGA-4 all PPSI should be connected to the PPSO from one AGGA-4, referred to as the master AGGA4, t o ensure t hat all channels in t he receiver use t he same Pulse Per Second. The OutputEn field of the PPSSettings regist er cont rols whet her t he PPSO is enabled or const ant ly de-assert ed. It is also possible t o generat e an int errupt for t he Pulse Per Second (see chapt er 4.12.2). The PPS t ime inst ance is lat ched t o t he regist ers PPS_IMT_MSW and PPS_IMT_LSW. Not e: If PPSI is used t hen t he difference bet ween PPSI and PPSO is 4 t o 6 CoreClk cycles.
3.5.4 Synchronisation of ME and PPS
By set ting the bit SyncEn in the PPSSettings register, the Measurement Epoch (ME) is phase aligned with the PPS once. Aft er writing the SyncEn bit, the hardware detects and clears it immediately. In case that the PPS is generated inside the AGGA-4, only the ME Divider is reloaded to its nominal value. In case that the PPS is coming from ext ernal, t he ME Divider and the EC Divider (integer and fractional part) are reloaded wit h their nominal values. By this it can be assured t hat t he PPS st robe and t he ME st robe are phase aligned at t he t ime of alignment .
3.5.5 Instrument Measurement Time (IMT)
The 64 bit IMT Counter counts CoreClk cycles. It can be read via the IMT_MSW and IMT_LSW regist ers at any t ime and it will return the current IMT count. The IMT_MSW register contains the Most Significant Word (upper 32 bit s) of t he IMT Counter, while the IMT_LSW register cont ains t he Lowest Significant Word (lower 32bit s) of t he IMT Count er. By writing to these registers, the IMT Counter can be preset wit h any value. The writ t en value becomes effective with the next Measurement Epoch. Note that always both parts (IMT_MSW and IMT_LSW) have to be writt en (t he order does not matter), before the hardware executes the IMT preset. If this protect ion mechanism would not be t here it could happen that an ME occurs while only one part of the IMT counter (eit her IMT_MSW or IMT_LSW) has already been writ t en. Then t he ME Observables would indicat e an inconsist ent t ime st amp. When reading the current (unlatched) IMT count (not the IMT observables) t he user is advised t o first read t he t he IMT_MSW, second the IMT_LSW and third again the IMT_MSW. That way a wrap around in the IMT count er can be det ect ed and correct ed. At t he following GNSS events (PPS, ME, ASE, PLD 5I, PLD IQ, AU Trigger) the counter is latched and the values are st ored to the corresponding IMT latch registers (see also Figure 3-55). Therefore t hese event s can be precisely t ime t agged.
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The lower 32 bits of the IMT Count (= IMT_LSW) are distributed wit hin the GNSS core as time st amp. Each channel for example uses it t o precisely t ime t ag t he Int egrat ion Epoch. IMT_MSW and IMT_LSWare reset by the Power On or AGGA4 reset pins (PWR_ON_RESET_N, GNSS_RESET_N), but t hey are not cleared by an AGGA4 Reset (see sect ion 6.5.3).
3.5.6 External Clock (ExtClk) Interface
The External Clock Interface can be used for various purposes. The receiver can for example calculate clock corrections for its own oscillator even without a Position Velocity Time (PVT) if the External Clock input is connected t o a st able external reference. The External Clock Counter can either be clocked by the signal coming from the EXT_CLK input pin or with the signal coming from the EXT_CORE_CLK input pin. This can be programmed via t he SignalSel bit in t he ExtClkSettings regist er. The External Clock Counter is 32bit wide and has a natural wrap around. It is detecting the rising edge of t he count ing signal. The External Clock Counter can be read at any time by reading the register ExtClkCnt. It will return the current value. The Ext ernal Clock Count er can count frequencies up t o 50 MHz.
Addit ionally the counter can be latched at the following events (ME, PPS, ExtClk). The lat ched value can be read by reading the register ExtClkCntLatched. Depending on the switch bits, the latched counter shall do the following actions:
Swi tch Bits
Acti ons
extClkLatchAtExtClk extClkLatchAtME extClkLatchAtPPS
ExtClkCnt is
lat ched wit h ExtClkCnt is ExtClkCnt is
t rigger from lat ched wit h lat ched wit h
EXT_CLK ME
PPS
input
0 0 0
No
No
No
0 0 1
No
No
Yes
0 1 0
No
Yes
No
0 1 1
No
Yes
Yes
1 0 0
Yes
No
No
1 0 1
Yes
No
Yes
1 1 0
Yes
Yes
No
1 1 1
Yes
Yes
Yes
Tabl e 3-30: Acti on Tabl e for ExtClkCntLatched
Note : If the External Clock Counter is running with CoreClk all latch triggers are valid (ME, PPS, EXT_CLK input pin). If the External Clock Counter is running wit h the signal from the EXT_CLK input pin only the ME and PPS lat ch t riggers are valid.
3.5.7 Delay Line Clock Sync
In order t o make sure t hat t he delay line clock divider count er st at e is phase coherent over all channels, a synchronization signal DelayLineClkSync is generated every 12 CoreClk cycles in the Time Base module. This signal simultaneously clears all clock dividers, resulting in a phase-alignment of all delay line clocks regardless of t heir division rat io.
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3.6 Antenna Switch Controller (ASC)
This section describes the Antenna Swit ch Controller (ASC). As shown in Figure 3-56, it consist s of t he Ant enna Swit ch Epoch Output (ASEO) Divider, a Synchroniser for the Antenna Swit ch Epoch Input (ASEI) and t he Ant enna Swit ch Sequencer.
Antenna Switch Controller
EpochClk ASEI (Pin)
ASEO Divider
Synchroniser
1 0 OutputEn
Antenna Switch Sequencer
ASEO (Pin)
ASE ASC[0] (Pin) ASC[1] (Pin)
External connection on the board
Fi gure 3-56: Antenna Swi tch C ontrol l er (ASC )
The Antenna Swit ch Controller supports the Hybrid Parallel-Multiplex attitude determination scheme (see [RD-05]). The two lines Antenna Swit ch Control ASC outputs are intended for controlling external antenna switching of up to four ant ennas (see also Figure 3-57). Also the Antenna Swit ch Epoch ASE strobe is generated, which signals antenna swit ch events to the channels and which can be used to control the updating of the correlation values (see chapt er 3.6.3). An int errupt can be generated whenever ASE occurs (see chapter 4.12.2). Both t he ASE st robe and t he ASC out put s are generat ed from t he Ant enna Swit ch Epoch Input ASEI. In receivers with one AGGA-4 ASEI should be externally connected to its own ASEO output. In receivers with multiple AGGA-4 all ASEI inputs should be connected to the ASEO signal from one AGGA-4, referred to as the mast er AGGA4, t o ensure t hat all channels in t he receiver use t he same ASE.
3.6.1 Antenna Switch Epoch (ASE) The ASE st robe signals the end of each Antenna Swit ch Epoch. It is taken from the ASEI input after synchronization and det ect ion of t he rising edge. An int errupt can be generat ed whenever ASE occurs.
The ASEO signal can have frequencies from EpochClk to EpochClk/1024 depending on the programming of t he ASEO Divider. This divider can be programmed by the DivRatio field in the AntSwitchCtrl register. A typical value for ASEO would be 200 Hz. The OutputEn bit of the AntSwitchCtrl register controls whether the ASEO output is enabled or constantly de-assert ed. When it is disabled the ASEO Divider is also disabled. If enabled, the ASEO output is asserted for 128 CoreClk cycles once it occurs. The int ernal ASE signal is assert ed for one CoreClk cycle.
In order to reduce switching noise the integrators are inhibited at t he st art of each Ant enna Swit ch Epoch for 128 CoreClk cycles.
The time instance of t he Ant enna Swit ch Epoch is lat ched in t he regist ers ASE_IMT_MSW and ASE_IMT_LSW
3.6.2 Antenna Switch Sequencer
The Antenna Swit ch Sequencer outputs on the two pins ASC[0] and ASC[1] which ant enna is current ly assert ed t o cont rol the external antenna switching of up to four antennas to a common RF/IF section as depicted in Figure 3-57. To be clear; this antenna multiplexing scheme is only needed for the Hybrid Parallel-Mult iplex at t it ude det erminat ion
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scheme (see [RD-05]), not for a parallel attitude determination scheme, where each AGGA Input Module is connect ed t o one dedicat ed ant enna or for normal posit ioning applicat ions.
Antenna #0 Antenna #1 Antenna #2 Antenna #3
Antenna
Mux
TTL 0 - 1
RF Front-end
AGGA
ASC 0 - 1
Fi gure 3-57: AGGA-4 Antenna Mul ti pl exi ng
The mapping is as follow:
Antenna #0 #1 #2 #3
ASC[0] 0 0 1 1
ASC[1] 0 1 0 1
Tabl e 3-31: ASC O utput Mappi ng
The antennas can be switched in a sequence. The sequence can be programmed by t he SwitchSequencer field in t he AntSwitchCtrl register. At the start of each Antenna Swit ch Epoch t he Ant enna Swit ch Sequencer assert s t he next higher ASC output that has been enabled by the SwitchSequencer field. If no bit has been set in t he SwitchSequencer field t he ASC output is static. After PowerOn Reset t he ASC pins have t he assignment ASC[1:0] = 0, while aft er previous ASC st art/stop, the ASC[1:0] assignment must not necessarily be zero, but remains st at ic at it 's last st at e.
At t he end of each Antenna Swit ch Epoch (ASE) the number of the antenna that was asserted during t he last period is st ored in the read-only SwitchID field of the AntSwitchCtrl register. By reading this value the firmware can reconst ruct t o which ant enna t he correlat ion values correspond.
3.6.3 Antenna Switch Correlation Results
If t he ASEEn bit in the CorrUnitCtrl register is enabled, then t he correlat ors of a channel behave different ly. The following t able depict s t his (see also Table 3-20):
ASEEn = 0
ASEEn = 1
Multiplication
reset @ latch @ Multiplication
reset @
EE Incoming Signal x EE IE or LE IE
Incoming Signal x EE IE or LE
E Incoming Signal x E IE or LE IE
Incoming Signal x P (IE or LE) and ASE
P Incoming Signal x P IE or LE IE
Incoming Signal x P (IE or LE) and ASE
L Incoming Signal x L IE or LE IE
Incoming Signal x P ASE
LL Incoming Signal x LL IE or LE IE
Incoming Signal x LL IE or LE
latch @ IE ASE IE ASE IE
Tabl e 3-32: Acti on Tabl e for C orrel ators
The Early and Punctual correlator together result in the same functionality than AGGA-2/3 was giving. However if t he ASC mechanism is applied for signals where no inversion due to data is expected (e.g. pilot signals) then t he AGGA-4 offers an additional mode which simplifies the handling of the correlation values for the software. The late correlator is resetting and latching wit h ASE only. Therefore no reconst ruct ion of t he ASE correlat ion value is needed. It can direct ly be read out . Figure 3-58 shows graphically how t he Early, Late and Punctual correlator work t oget her wit h t he Ant enna Swit ch Cont roller.
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ASE
ANT1
ASE
ANT2
ASE
IE
IE
IE
IE
IE
IE
1
2
3
4
5
P
6
7
8
E
9
10
11
L
SUM ANT1 = 1 + 2 + 7 or SUM ANT2 = 3 + 4 + 8 or
SUM ANT1 = 10 SUM ANT2 = 11
ASE ... Antenna Switch Epoch IE ... Integration Epoch
Fi gure 3-58: ASC Behavi our on C orrel ators
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3.7 AMBA High Performance Bus (AHB) Interface
As ant icipated in Figure 2-1, the GNSS module is connected t o t he AMBA High Performance BUS (AHB) via t wo int erfaces: the AHB master and the AHB slave interface. The AHB master interface is required t o implement DMA capability to the GNSS module and the AHB slave interface is used to access all module int ernal regist ers (read and writ e).
GNSS Module GNSS Core
Input Module
DBF
4
Channel Matrix
Channel
ASC
36 Time Base
DMA Request Processing
DMA write processing
Ireg control
Synchroniser
DMA config regs
AHB
AHB / Master
AHB Slave
Fi gure 3-59: GNSS Modul e
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4 Processor Module
AGGA-4 uses t he LEON-2 Fault Tolerant Processor together with the Cobham Gaisler Floating Point Unit (GRFPU). An overview t o the Processor Module and its corresponding periphery can be seen in Figure 4-1 (t he solid blocks, which are not greyed out ).
UART SpaceWire
SRAM PROM
IO
AGGA-4
Debug comm. link AHB
Trace buffer
Debug Support Unit
AHB
Gaisler FPU
LEON2FT IU
I-Cache D-Cache AHB
Status AHB
write protect
AHB
Arbiter/ Decoder
LEON config TIMERs Watchdog
CIC
PIC
A Mem H Ctrl B
AHB
AHB
APB
APB
AHB | DMA SpaceWire
AHB | DMA
MIL-Bus 1553
AHB | DMA UARTs
AHB | DMA CRC
AHB FFT
AHB | DMA
GNSS Core & GIC
GPIO SPI
GPIO I/F SPI I/F
SpaceWire I/F MIL-Bus I/F UART I/F
Legend: GIC: GNSS Interrupt Controller CIC: Communication Interrupt Controller PIC: Primary Interrupt Controller
GNSS Signal I/F
Fi gure 4-1: O vervi ew of Processor Modul es
The LEON-2 processor implements the SPARC V8 st andard as defined in t he SPARC V8 archit ect ural manual (see [AD-01], [RD-06]). The LEON-2-FT version implement ed is 1.0.9.16.2.
The following chapt ers give an overview t o t he Leon-2 modules.
4.1 Integer Unit
4.1.1 Instruction Timing
Table 4-1 list s t he cycles per inst ruct ion (assuming cache hit and no load int erlock):
Instruction JMPL Double Load Single Store Double Store SMUL/UMUL SDIV/UDIV Taken Trap Atomic load/store All other intructions
Cycles 2 2 2 3 5 35 4 3 1
Tabl e 4-1 Instructi on ti mi ng
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4.2 Floating Point Unit (FPU)
The AGGA-4 uses the Cobham Gaisler Floating Point Unit (GRFPU). It is a high-performance FPU implement ing floating-point operations as defined in IEEE St andard for Binary Floating-Point Arithmetic (IEEE-754) and SPARC V8 st andard (IEEE-1754). Supported formats are single and double precision floating-point numbers. The advanced design combines two execution units, a fully pipelined unit for execution of t he most common FP operat ions and a nonblocking unit for execution of divide and square-root operations. The logical view of t he GRFPU is shown in Figure 4-2.
Pipelined execution unit
GRFPU
Iteration unit
Fi gure 4-2: C obham Gai sl er Fl oati ng Poi nt Uni t (GRFPU)
The following chapters describe the GRFPU from functional point of view. Chapt er "Funct ional descript ion" gives det ails about GRFPU's implementation of the IEEE-754 standard including FP formats, operations, opcodes, operat ion t iming, rounding and exceptions. "Signals and timing" describes the GRFPU interface and its signals. "GRFPU Control Unit " describes the software aspects of the GRFPU integration into a LEON processor t hrough t he GRFPU Cont rol Unit - GRFPC. For implementation details refer to the white paper, "GRFPU - High Performance IEEE-754 Float ingPoint Unit " (available at www.gaisler.com).
4.2.1 Floating-point number formats
GRFPU handles floating-point numbers in single or double precision format as defined in the IEEE-754 st andard wit h exception for denormalized numbers. See section Denormalized numbers for more informat ion on denormalized numbers.
4.2.2 FP operations
GRFPU supports four types of floating-point operations: arithmet ic, compare, convert and move. The operat ions implement all FP instructions specified by SPARC V8 instruction set, and most of the operations defined in IEEE-754. All operations are summarized in Table 4-2, with their opcodes, operands, results and except ion codes. Throughput s and lat encies and are shown in Table 4-3.
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Operation OpCode[8:0] Op1
Op2
Result
Exceptions Description
Arithmetic operations
FADDS
1000001 SP
FADDD
1000010 DP
FSUBS
1000101 SP
FSUBD
1000110 DP
FMULS
1001001 SP
FMULD
1001010 DP
FSMULD
1101001 SP
FDIVS
1001101 SP
FDIVD
1001110 DP
FSQRTS
101001 -
FSQRTD
101010 -
Conversion operations
FITOS
11000100 -
FITOD FSTOI
11001000 11010001 -
FDTOI FSTOI_RND
11010010 111010001 -
FDTOI_RND FSTOD
111010010 11001001 -
FDTOS
11000110
Comparison operations
FCMPS
1010001 SP
FCMPD FCMPES
1010010 DP 1010101 SP
FCMPED
1010110 DP
Negate, Absolute value and Move
FABSS
1001 -
FNEGS FMOVS
101 1
SP
SP
DP
DP
SP
SP
DP
DP
SP
SP
DP
DP
SP
DP
SP
SP
DP
DP
SP
SP
DP
DP
UNF, NV, OF, Addition UF, NX
UNF, NV, OF, Subtraction UF, NX
UNF, NV, OF, Multiplication,
UF, NX
FSMULD
gives exact
double-
UNF, NV, OF, precision
UF, NX
product of two
UNF, NV, OF, single-
UF
precision
UNF, NV, OF, Divisiond
UF, NX, DZ
UNF, NV, NX Square-root
INT
SP
NX
Integer to
DP
-
floating-point conversion
SP
INT
UNF, NV, NX Floating-point
to integer
conversion.
The result is
rounded in round-to-zero
DP
mode.
SP
INT
UNF, NV, NX Floating-point
to integer
conversion.
Rounding according to
DP
RND input.
SP
DP
UNF, NV
Conversion
between
DP
SP
UNF, NV, OF, floating-point
UF, NX
formats
SP
CC
NV
Floating-point
compare.
Invalid
exception is
generated if either operand
is a signaling
DP
NaN.
SP
CC
NV
Floating point
compare.
Invalid exception is
generated if
either operand
is a NaN (quiet
DP
or signaling).
SP
SP
-
SP
SP
-
SP
SP
-
Absolute value.
Negate.
Move. Copies operand to result output.
SP - single precision floating-point number DP - double precision floating-point number
INT - 32 bit integer
CC - condition codes, see table : Signal descriptions UNF, NV, OF, UF, NX - floating-point exceptions, see section Exceptions
Tabl e 4-2: GRFPU O perati ons
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Arit hmetic operations include addition, subtraction, multiplication, division and square-root. Each arithmetic operat ion can be performed in single or double precision formats. Arithmetic operations have one clock cycle t hroughput and a lat ency of four clock cycles, except for divide and square-root operations, which have a t hroughput of 16 - 25 clock cycles and latency of 16 - 25 clock cycles (see Table 4-3). Add, sub and multiply can be started on every clock cycle, providing high throughput for these common operations. Divide and square-root operations have lower throughput and higher latency due to complexity of the algorithms, but are executed in parallel with all other FP operat ions in a nonblocking iteration unit. Out-of-order execution of operations wit h different lat encies is easily handled t hrough t he GRFPU int erface by assigning an id to every operation which appears with the result on the output once the operation is complet ed (see sect ion4.2.8).
Operation
Throughput Latency
FADDS, FADDD, FSUBS, FSUBD, FMULS, FMULD, FSMULD
2
5
FITOS, FITOD, FSTOI, FSTOI_RND, FDTOI, FDTOI_RND, FSTOD, FDTOS
2
5
FCMPS, FCMPD, FCMPES, FCMPED
2
5
FDIVS
17
17
FDIVD
17.5 (16/19)* 17.5 (16/19)*
FSQRTS
25
25
FSQRTD
25.5 (24/27)* 25.5 (24/27)*
* Throughput and latency are data dependant with two possible cases with equal statistical possibility.
Tabl e 4-3: Throughput and Latency
Conversion operations execute in a pipelined execution unit and have throughput of one clock cycle and latency of four clock cycles. Conversion operations provide conversion between different floating-point numbers and between floatingpoint numbers and int egers. Comparison functions offering two different types of quiet Not-a-Numbers (QNaNs) handling are provided. Move, negat e and absolute value are also provided. These operations do not ever generate unfinished except ion (unfinished except ion is never signaled since compare, negat e, absolut e value and move handle denormalized numbers).
4.2.3 Exceptions
GRFPU det ects all exceptions defined by the IEEE-754 standard. This includes detection of Invalid Operat ion (NV), Overflow (OF), Underflow (UF), Division-by-Zero (DZ) and Inexact (NX) exception conditions. Generation of special result s such as NaNs and infinity is also implemented. Overflow (OF) and underflow (UF) are detected before rounding. If an operation underflows t he result is flushed to zero (GRFPU does not support denormalized numbers or gradual underflow). A special Unfinished exception (UNF) is signaled when one of t he operands is a denormalized number which is not handled by t he arit hmet ic and conversion operat ions.
4.2.4 Rounding
All four rounding modes defined in the IEEE-754 standard are supported: round-to-nearest, round-to-+inf, round-to--inf and round-t o-zero.
4.2.5 Denormalized numbers
Denormalized numbers are not handled by t he GRFPU arit hmet ic and conversion operat ions. A syst em (microprocessor) with the GRFPU could emulate rare cases of operations on denormals in soft ware using non-FPU operations. A special Unfinished exception (UNF) is used t o signal an arit hmet ic or conversion operat ion on t he denormalized numbers. Compare, move, negate and absolute value operations can handle denormalized numbers and do not raise the unfinished except ion. GRFPU does not generat e any denormalized numbers during arit hmet ic and conversion operations on normalized numbers. If the infinitely precise result of an operation is a tiny number (smaller t han minimum value representable in normal format) the result is flushed to zero (with underflow and inexact flags set).
4.2.6 Non-standard Mode
GRFPU can operate in a non-standard mode where all denormalized operands to arithmetic and conversion operat ions are t reated as (correctly signed) zeroes. Calculations are performed on zero operands inst ead of t he denormalized numbers obeying all rules of the floating-point arithmetics including rounding of the results and detect ing except ions.
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4.2.7 NaNs
GRFPU supports handling of Not-a-Numbers (NaNs) as defined in the IEEE-754 st andard. Operat ions on signaling NaNs (SNaNs) and invalid operations (e.g. inf/inf) generate the Invalid except ion and deliver QNaN_GEN as result . Operations on Quiet NaNs (QNaNs), except for FCMPES and FCMPED, do not raise any except ions and propagat e QNaNs t hrough t he FP operat ions by delivering NaN-result s according t o Table 4-4. QNaN_GEN is 0x7fffe00000000000 for double precision result s and 0x7fff0000 for single precision result s.
Operand 2
FP
QNaN2
SNaN2
none FP
QNaN2
QNaN_GEN
Operand 1 FP
FP
QNaN2
QNaN_GEN
QNaN1 QNaN1
QNaN2
QNaN_GEN
SNaN1 QNaN_GEN QNaN_GEN QNaN_GEN
Tabl e 4-4: O perati ons on NaNs
4.2.8 Timing
The FPU is fully pipelined and a new operation can be started every clock cycle. The only except ions are divide and square-root operations which require 16 to 26 clock cycles to complet e, and which are not pipelined. Division and square-root are implement ed t hrough it erat ive series expansion algorit hm. Since t he algorit hms basic st ep is mult iplication the floating-point multiplier is shared between multiplication, division and square-root . Division and square-root do not occupy the multiplier during the whole operation and allow mult iplicat ion t o be int erleaved and execut ed parallelly wit h division or square-root .
4.2.9 GRFPC - GRFPU Control Unit
The GRFPU Control Unit (GRFPC) is used to attach the GRFPU t o t he LEON int eger unit (IU). GRFPC performs scheduling, decoding and dispatching of the FP operations to the GRFPU as well as managing the floating-point register file, the floating-point state register (FSR) and the floating-point deferred-trap queue (FQ). Floating-point operations are execut ed in parallel with other integer instructions, the LEON integer pipeline is only st alled in case of operand or resource conflict s.
4.2.10 Floating-Point register file
The GRFPU floating-point register file contains 32 32-bit floating-point regist ers (%f0-%f31). The regist er file is accessed by floating-point load and store instructions (LDF, LDDF, STD, STDF) and floating-point operate instructions (FPop).
4.2.11 Floating-Point State Register (FSR)
The GRFPC manages the floating-point state register (FSR) containing FPU mode and status information. All fields of t he FSR register as defined in SPARC V8 specification are implemented and managed by t he GRFPU conforming t o t he SPARC V8 specification and the IEEE-754 standard. Implementation-specific parts of t he FSR managing are t he NS (non-st andard) bit and ftt field.
If t he NS (non-standard) bit of the FSR register is set, all floating-point operations will be performed in non-st andard mode as described in section 4.2.6. When the NS bit is cleared all operations are performed in standard IEEE-compliant mode.
Following float ing-point t rap t ypes never occur and are t herefore never set in t he ft t field:
· unimplement ed_FPop: all FPop operat ions are implement ed
· hardware_error: non-resumable hardware error
· invalid_fp_regist er: no check t hat double-precision regist er is 0 mod 2 is performed
GRFPU implements the qne bit of the FSR register which reads 0 if the floating-point deferred-queue (FQ) is empty and 1 ot herwise.
The FSR is accessed using LDFSR and STFSR inst ruct ions.
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4.2.12 Floating-Point Exceptions and Floating-Point Deferred-Queue
GRFPU implements the SPARC deferred trap model for floating-point exceptions (fp_except ion). A float ing-point exception is caused by a floating-point instruction performing an operation resulting in one of following condit ions:
· an operation raises IEEE floating-point exception (ftt = IEEE_754_exception) e.g. executing invalid operation such as 0/0 while t he NVM bit of t he TEM field id set (invalid except ion enabled).
· an operation on denormalized float ing-point numbers (in st andard IEEE-mode) raises unfinished_FPop float ing-point except ion
· sequence error: abnormal error condition in the FPU due to the erroneous use of the floating-point instructions in t he supervisor soft ware.
The trap is deferred to one of the floating-point instructions (FPop, FP load/st ore, FP branch) following t he t rapinducing instruction (note that this may not be next floating-point instruction in the program order due t o except iondet ecting mechanism and out-of-order instruction execution in the GRFPC). When the trap is taken the float ing-point deferred-queue (FQ) contains the trap-inducing instruction and up to seven FPop instructions t hat were dispat ched in t he GRFPC but did not complet e.
Aft er the trap is taken the qne bit of the FSR is set and remains set until the FQ is empt ied. The STDFQ inst ruct ion reads a double-word from the floating-point deferred queue, the first word is t he address of t he inst ruct ion and t he second word is the instruction code. All instructions in the FQ are FPop type instructions. The first access t o t he FQ gives a double-word with the t rap-inducing inst ruct ion, following double-words cont ain pending float ing-point inst ructions. Supervisor software should emulate FPops from the FQ in the same order as they were read from t he FQ.
Not e that instructions in the FQ may not appear in the same order as the program order since GRFPU executes floatingpoint instructions out-of-order. A floating-point trap is never deferred past an instruction specifying source regist ers, dest ination registers or condition codes that could be modified by the trap-inducing instruction. Execution or emulation of instructions in the FQ by the supervisor software gives therefore t he same FPU st at e as if t he inst ruct ions were execut ed in t he program order.
4.3 Exceptions
The LEON core inside AGGA-4 adheres to the general SPARC trap model. The table below shows t he implement ed t raps and t heir individual priorit y (TT=Trap Type, Pri=Priorit y).
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Trap
TT Pri Description
reset
0x00 1 Power-on reset
write error
0x2b 2 write buffer error (illegal/write protected address access)
instruction_access_exception 0x01 3 Error during instruction fetch
illegal_instruction
0x02 5 UNIMP or other un-implemented instruction
privileged_instruction
0x03 4 Execution of privileged instruction in user mode
fp_disabled
0x04 6 FP instruction while FPU disabled
cp_disabled
0x24 6 CP instruction while Co-processor disabled
watchpoint_detected
0x0B 7 Instruction or data watchpoint match
window_overflow
0x05 8 SAVE into invalid window
window_underflow
0x06 8 RESTORE into invalid window
mem_address_not_aligned
0x07 10 Memory access to un-aligned address
fp_exception
0x08 11 FPU exception
data_access_exception
0x09 13 Access error during load or store instruction (memory EDAC error)
tag_overflow
0x0A 14 Tagged arithmetic overflow
divide_exception
0x2A 15 Divide by zero
interrupt_level_1
0x11 31 Asynchronous interrupt 1 (AHB Error)
interrupt_level_2
0x12 30 Asynchronous interrupt 2 (Parallel I/O 0)
interrupt_level_3
0x13 29 Asynchronous interrupt 3 (Timer 1)
interrupt_level_4
0x14 28 Asynchronous interrupt 4 (FFT Done)
interrupt_level_5
0x15 27 Asynchronous interrupt 5 (GNSS low)
interrupt_level_6
0x16 26 Asynchronous interrupt 6 (Parallel I/O 1)
interrupt_level_7
0x17 25 Asynchronous interrupt 7 (Timer 2)
interrupt_level_8
0x18 24 Asynchronous interrupt 8 (Communication)
interrupt_level_9
0x19 23 Asynchronous interrupt 9 (Parallel I/O 2)
interrupt_level_10
0x1A 22 Asynchronous interrupt 10 (Timer 3)
interrupt_level_11
0x1B 21 Asynchronous interrupt 11 (GNSS high)
interrupt_level_12
0x1C 20 Asynchronous interrupt 12 (Parallel I/O 3)
interrupt_level_13
0x1D 19 Asynchronous interrupt 13 (Timer 4)
interrupt_level_14
0x1E 18 Asynchronous interrupt 14 (DSU Trace Buffer)
interrupt_level_15
0x1F 17 Asynchronous interrupt 15 (NMI)
trap_instruction
0x80 - 0xff 16 Software trap instruction (TA)
Tabl e 4-5 Trap al l ocati on and pri ori ty
4.4 Watch-points
The integer unit contains four hardware watch-points. Each wat ch-point consist s of a pair of applicat ion-specific regist ers (%asr24/25, %asr26/27, %asr28/29 and %asr30/31) registers; one with the break address and one with a mask:
Fi gure 4-3 Watch Poi nt Regi sters
Any binary aligned address range can be wat ched - the range is defined by the WADDR field, masked by the WMASK field (WMASK[x] = 1 enables comparison). On a watch-point hit, trap 0x0B is generated. By setting the IF, DL and DS bit s, a hit can be generated on instruction fetch, data load or data store. Clearing these three bits will effectively disable t he wat ch-point funct ion. Aft er reset all t hree bit s (IF, DL, DS) are zero.
4.5 Power Down Register
The processor can be powered-down by writing an arbitrary value to the PowerDown register. Power-down mode will be ent ered on the next load or store instruction. To enter power-down mode immediately, a st ore t o t he PowerDown
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regist er should be performed immediately followed by a `dummy' load. During power-down mode, the integer unit will effectively be halted. The power-down mode will be terminated (and the integer unit re-enabled) when an unmasked int errupt with higher level than the current processor interrupt level (PIL) becomes pending. All ot her funct ions and peripherals operat e as nominal during t he power-down mode. A suit able power-down rout ine could be:
struct pwd_reg_type { volatile int pwd; }; power_down() { struct pwd_reg_type *lreg = (struct pwd_reg_type *) 0x80000018; while (1) lreg->pwd = lreg->pwd; }
In assembly, a suit able sequence could be:
power_down: set 0x80000000, %l3 st %g0, [%l3 + 0x18] ba power_down ld [%l3 + 0x18], %g0
Note: The LEON2 error ,,Power-down causes lock-up of processor", documented in the AT697 errata sheet is corrected in t his LEON2 version.
4.6 Leon Configuration Register
Since LEON is synthesized from an extensively configurable VHDL model, the LeonConfig register (read-only) is used t o indicat e which opt ions were enabled during synt hesis.
4.7 Fault tolerant Features
4.7.1 Register file protection
To prevent erroneous operat ions from SEU errors, t he main regist er file is implement ed wit h hard flip flops.
4.7.2 External memory EDAC
The on-chip memory EDAC can correct one error and det ect t wo errors in a 32-bit word. For each word, a 7-bit checksum is generated according to the equations below. Correction is done on-the-fly and no t iming penalt y occurs during correction. If an un-correctable error (double-error) is detected, an error response is generated on t he AHB bus, which can lead to a memory exception in the processor, and interrupt 1 is generated. If a correct able error occurs, no error response is generated but the event is registered in t he AHB failing address and memory st at us regist er, and int errupt 1 is generated. This interrupt can be used to scrub the failing memory location. The EDAC can be used during access t o PROM or SRAM (0x4000_0000 - 0x5FFF_FFFF) areas by setting the corresponding EDAC enable bits in the MCFG3 regist er. The equat ions below show how t he EDAC check bit s are generat ed:
CB0 = D0 ^ D4 ^ D6 ^ D7 ^ D8 ^ D9 ^ D11 ^ D14 ^ D17 ^ D18 ^ D19 ^ D21 ^ D26 ^ D28 ^ D29 ^ D31 CB1 = D0 ^ D1 ^ D2 ^ D4 ^ D6 ^ D8 ^ D10 ^ D12 ^ D16 ^ D17 ^ D18 ^ D20 ^ D22 ^ D24 ^ D26 ^ D28 Not(CB2) = D0 ^ D3 ^ D4 ^ D7 ^ D9 ^ D10 ^ D13 ^ D15 ^ D16 ^ D19 ^ D20 ^ D23 ^ D25 ^ D26 ^ D29 ^ D31 Not(CB3) = D0 ^ D1 ^ D5 ^ D6 ^ D7 ^ D11 ^ D12 ^ D13 ^ D16 ^ D17 ^ D21 ^ D22 ^ D23 ^ D27 ^ D28 ^ D29 CB4 = D2 ^ D3 ^ D4 ^ D5 ^ D6 ^ D7 ^ D14 ^ D15 ^ D18 ^ D19 ^ D20 ^ D21 ^ D22 ^ D23 ^ D30 ^ D31 CB5 = D8 ^ D9 ^ D10 ^ D11 ^ D12 ^ D13 ^ D14 ^ D15 ^ D24 ^ D25 ^ D26 ^ D27 ^ D28 ^ D29 ^ D30 ^ D31 CB6 = D0 ^ D1 ^ D2 ^ D3 ^ D4 ^ D5 ^ D6 ^ D7 ^ D24 ^ D25 ^ D26 ^ D27 ^ D28 ^ D29 ^ D30 ^ D31
If t he memory is configured in 32-bit mode, the EDAC check bit bus (CB[6:0]) is used, the bits are stored in a separat e memory space, which is not seen by the user and which does not reduce t he available memory in t he 32-bit space.
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If t he memory is configured in 8-bit mode, the EDAC check bit bus (CB[6:0]) is not used but it is st ill possible t o use EDAC protection. Data is always accessed as words (4 bytes at a time) and the corresponding check bits are locat ed at t he address acquired by inverting the word address (ADDRESS[27:2]) and using it as a byte address. The same chipselect is kept active. A word written as four bytes to addresses 0, 1, 2, 3 will have its check bits at address 0x0FFFFFFF, addresses 4, 5, 6, 7 at 0x0FFFFFFE and so on. All the bits up to the maximum bank size will be inverted while the same chip-select is always asserted. This way all the bank size can be supported and no memory will be unused (except for a maximum of 4 Byte in the gap between the data and check bit area). The 8-bit mode applies to RAM and PROM. Only byt e-writes should be performed to ROM with EDAC enabled. In this case, only the corresponding byte will be written. The operation of the EDAC can be tested through the MCFG3 register. If the WB (write bypass) bit is set, t he value in t he TCB field will replace the normal check bits during memory write cycles. If the RB (read bypass) is set, the memory check bit s of t he loaded dat a will be st ored in t he TCB field during memory read cycles.
Note: when t he EDAC is enabled, t he ReadModifyWriteEn bit in MCFG2 regist er must be set .
Access t o 32-bit wide EDAC protected memory occurs with no performance degradation. Accesses to 8-bit wide EDAC prot ect ed memory needs 25% more t ime (The checksum has t o be writ t en sequent ially).
Note: when EDAC is enabled and 8bit PROM mode is used, t he EDAC is only support ed for read accesses. When writing into 8bit PROM the EDAC checksum has to be calculated and has to be written in the correct address by hand.
4.7.3 Cache memory protection
Error detection of cache tags and data is implemented using two parity bits per tag and per 4-byte dat a sub-block. The t ag parity is generated from the tag value and the valid bits. The data sub-block parit y is derived from t he sub-block dat a. The parity bits are written simultaneously with the associated tag or sub-block and checked on each access. The t wo parit y bit s correspond t o t he parit y of odd and even dat a (t ag) bit s. If a t ag parity error is detected during a cache access, a cache miss will be generat ed and t he t ag (and dat a) will be aut omatically updated. All valid bits except the one corresponding to the newly loaded dat a will be cleared. If a dat a sub-block parity error occurs, a miss will also be generated but only the failed sub-block will be updated with data from main memory.
4.8 Multiplication/Division Instructions
Full support for SPARC V8 divide instructions is provided (SDIV/UDIV/SDIVCC/UDIVCC). The divide inst ruct ions perform a 64-by-32 bit divide and produce a 32-bit result. Rounding and overflow detection is performed as defined in t he SPARC V8 st andard.
The LEON processor supports the SPARC integer multiply inst ruct ions UMUL, SMUL, UMULCC and SMULCC. These instructions perform a 32x32-bit integer mult iply, producing a 64-bit result . SMUL and SMULCC perform signed mult iply while UMUL and UMULCC perform unsigned mult iply. UMULCC and SMULCC also set t he condit ion codes t o reflect t he result .
4.9 Cache Sub-System
Separate instruction (32 KB) and data (16 KB) caches are provided. The instruction cache uses streaming during linerefill to minimize refill latency. The data cache uses write through policy and implements a double-word writ e-buffer. The dat a cache also performs bus-snooping on t he AHB bus.
C ache configuration
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Instructi on C ache Associat ivit y Cache Line Size Replacement Algorit hm Locking Data C ache Associat ivit y Cache Line Size Replacement Algorit hm Locking
Tabl e 4-6 C ache confi gurati on
32 Kbyt e 4 32 Byt e (8 dwords) Pseudo Random disabled 16 Kbyt e 2 16 Byt e (4 dwords) Pseudo Random disabled
The LEON core inside AGGA-4 implements Harvard architecture with separate instruction and data buses, connect ed t o two independent cache controllers. In addition to the address, a SPARC processor also generat es an 8-bit address space identifier (ASI), providing up to 256 separate, 32-bit address spaces. During normal operat ion, t he LEON core accesses inst ruct ions and dat a using ASI 0x8 - 0xB as defined in t he SPARC st andard. Using t he LDA/STA inst ructions, alternative address spaces can be accessed. The table shows the ASI usage for LEON. Only ASI[3:0] is used for t he mapping, ASI[7:4] has no influence on operat ion.
Fi gure 4-4 ASI usage
Access t o ASI 4 and 7 will force a cache miss, and update the cache if the data was previously cached. Access with ASI 0 - 3 will force a cache miss, update the cache if the data was previously cached, or allocated a new line if the dat a was not in the cache and the address refers to a cacheable location. The cacheable areas are by default t he prom and ram areas:
Address range
Mappi ng
0x0000_0000 - 0x1FFF_FFFF PROM
0x2000_0000 - 0x3FFF_FFFF IO
0x4000_0000 - 0x5FFF_FFFF SRAM
0x6000_0000 - 0x7FFF_FFFF RAMS_N[4] memory
0x8000_0000 - 0xFFFF_FFFF Int ernal (AHB)
Modul e cacheable Non-cacheable cacheable Non-cacheable Non-cacheable
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Tabl e 4-7 Defaul t cache tabl e
The memory behind chip select RAMS_N[4] is not cacheable. This offers the possibility to support shared memory or a dual-port memory t hat is connect ed t o t hat chip select . The operation of the instruction and data caches is controlled through a common Cache Control Register (CacheCtrl). Each cache can be in one of three modes: disabled, enabled and frozen. If disabled, no cache operation is performed and load and store requests are passed directly to the memory controller. If enabled, the cache operates as described above. In t he frozen state, the cache is accessed and kept in sync with the main memory as if it was enabled, but no new lines are allocat ed on read misses.
If t he Data Cache Freeze or the Instruction Cache Freeze bit is set, t he corresponding cache will be frozen when an asynchronous interrupt is taken. The device is affected by t he ESA Alert EA-2012-EEE-17-A. Before using cache freezing the Alert has to be read and understood. This can be beneficial in real-time system t o allow a more accurat e calculation of worst-case execution time for a code segment. The execution of the interrupt handler will not evict any cache lines and when control is returned to the interrupted task, the cache state is ident ical t o what it was before t he int errupt. If a cache has been frozen by an interrupt, it can only be enabled again by enabling it in t he Cache Cont rol Regist er. This is typically done at the end of the interrupt handler before control is ret urned t o t he int errupt ed t ask.
Not e: Always flush t he dat a/inst ruct ion cache before enabling.
4.9.1 Instruction Cache
4.9.1.1 Operation If instruction burst fetch is enabled in the cache control register (CacheCtrl) the cache line is filled from main memory st arting at the missed address and until the end of the line. At the same time, the instructions are forwarded t o t he IU (st reaming). If the IU cannot accept the streamed instructions due to internal dependencies or multi-cycle inst ruct ion, t he IU is halt ed unt il t he line fill is complet ed. If t he IU execut es a cont rol t ransfer inst ruct ion (branch/CALL/JMPL/RETT/TRAP) during the line fill, the line fill will be terminated on the next fetch. If inst ruct ion burst fetch is enabled, incremental AHB bursts will be used on consecutive instruction fetches, even when the cache is disabled. In this case, the fetched instructions are only forwarded to the IU, the cache is not updat ed and a st aggered burst will be observed.
If a memory access error occurs during a line fill with the IU halted, the corresponding valid bit in the cache tag will not be set . If the IU later fetches an instruction from the failed address, a cache miss will occur, triggering a new access t o t he failed address. If t he error remains, an inst ruct ion access error t rap (t t =0x1) will be generat ed.
4.9.1.2 Instruction cache tag A inst ruct ion cache t ag ent ry consist s of several fields as shown in Figure 4-5.
Fi gure 4-5: Intructi on C ache Tag
Field Definit ions: · [31:10]: Address Tag (ATAG) - Cont ains t he t ag address of t he cache line. · [9]: LRR - Used by LRR algorit hm t o st ore replacement hist ory. '0' as PRR is used. · [8]: LOCK - Locks a cache line when set . 0 as inst ruct ion cache locking is not enabled. · [7:0]: Valid (V) - When set, the corresponding sub-block of the cache line contains valid data. These bits is set when a sub-block is filled due to a successful cache miss; a cache fill which results in a memory error will leave the valid bit unset. A FLUSH instruction will clear all valid bits. V[0] corresponds to address 0 in the cache line, V[1] to address 1, V[2] to address 2 and so on.
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4.9.2 Data Cache
4.9.2.1 Operation Each line has a cache tag associated with it consisting of a tag field, valid field with one valid bit for each 4-byt e subblock and optional lock and LRR bits. On a data cache read-miss to a cachable location 4 bytes of data are loaded int o t he cache from main memory. The write policy for stores is write-through with no-allocate on write-miss. In a multi-set configuration a line to be replaced on read-miss is chosen according to the replacement policy. If a memory access error occurs during a data load, the corresponding valid bit in t he cache t ag will not be set and a dat a access error t rap (t t =0x9) will be generat ed
4.9.2.2 Write buffer The data cache contains a write buffer able to hold a single 8,16,32, or 64-bit write transaction. For half-word or byt e st ores, the stored data is replicated into proper byte alignment for writ ing t o a word-addressed device. The writ e is processed in the background so the processor pipeline can keep executing while the write is being processed. However, any following instruction that requires bus access (hence, NOT a load cache-hit ) will cause t he writ e buffer t o be empt ied prior fet ching new dat a t o avoid generat ion of any st ale dat a. Since t he processor executes parallel to the write buffer, a write error will not cause an except ion synchronous t o t he excecution of the store instruction. Depending on memory and cache act ivit y, t he writ e cycle may not occur unt il several clock cycles after the store instructions has completed. If a write error occurs, the currently executing instruction will t ake t rap 0x2b. Not e: the 0x2b trap handler should flush the data cache, since a write hit would updat e t he cache while t he memory would keep t he old value due t he writ e error.
Due t o the write buffer latency, depending on memory and cache activity, a write operation may not become effect ive unt il several cycles after the store instruction has completed in the processor. For APB register accesses where the exact t ime of writ ing is relevant , it may be advised t o force a flush of t he writ e buffer.
This can be done by adding a dummy memory access, e.g. a load or store (usually faster) to a dummy address in a noncacheable area. Since dummy instructions may have a performance impact and the next store will always flush out t he previous store, it is sufficient to do this at the end of a sequence of st ores (e.g. configuring a GNSS funct ion or an int erface).
Not e that in any case the correct order of st ore and load t ransact ions and t he coherency of dat a in t he cache is guarant eed by t he hardware.
4.9.2.3 Data Cache Snooping
The data cache controller will monitor write accesses to the AHB bus performed by other AHB masters (DMA). When a writ e access is performed to a cacheable memory location, the corresponding cacheline will be invalidated in the dat a cache if present .
Not e: See also Known Issues chapt er 8.4.11
4.9.2.4 Data Cache Tag A dat a cache t ag ent ry consist s of several fields as shown in Fi gure 4-6.
Field Definit ions:
Fi gure 4-6: Data C ache Tag
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· [31:10]: Address Tag (ATAG) - Cont ains t he address of t he dat a held in t he cache line. · [9]: LRR - Used by LRR algorit hm t o st ore replacement hist ory. `0' as PRR is used. · [8]: LOCK - Locks a cache line when set . `0' as inst ruct ion cache locking is not enabled. · [3:0]: Valid (V) - When set, the corresponding sub-block of the cache line contains valid data. These bits is set
when a sub-block is filled due to a successful cache miss; a cache fill which result s in a memory error will leave the valid bit unset. V[0] corresponds to address 0 in the cache line, V[1] to address 1, V[2] t o address 2 and V[3] t o address 3.
4.9.3 Cache Flushing
The instruction and data cache is flushed by executing the FLUSH instruction, setting the FI bit in t he cache cont rol regist er (CacheCtrl), or by writing to any location with ASI=0x5. The flushing will take one cycle per cache line and set during which the IU will not be halt ed, but during which t he inst ruct ion cache will be disabled. When t he flush operation is completed, the cache will resume the state (disabled, enabled or frozen) indicat ed in t he cache cont rol regist er. Select ive flushing of individual cache lines is not support ed.
4.9.4 Diagnostic Cache access
Tags and data in the instruction and data cache can be accessed through ASI address space 0xC, 0xD, 0xE and 0xF by execut ing LDA and STA instructions. Address bits making up t he cache offset will be used t o index t he t ag t o be accessed while the least significant bits of the bit s making up t he address t ag will be used t o index t he cache set .
Diagnostic read of tags is possible by executing an LDA inst ruct ion wit h ASI=0xC for inst ruct ion cache t ags and ASI=0xE for data cache tags. A cache line and set are indexed by the address bits making up the cache offset and t he least significant bits of the address bits making up t he address t ag. Similarly, t he dat a sub-blocks may be read by execut ing an LDA instruction with ASI=0xD for instruction cache data and ASI=0xF for data cache data. The sub-block t o be read in t he indexed cache line and set is select ed by A[4:2]. The tags can be directly written by executing a STA inst ruct ion wit h ASI=0xC for t he inst ruct ion cache t ags and ASI=0xE for the data cache tags. The cache line and set are indexed by the address bits making up the cache offset and t he least significant bits of the address bits making up the address tag. D[31:10] is writ ten int o t he ATAG field (see above) and the valid bits are written with the D[7:0] of the write data. Bit D[9] is written into the LRR bit (if enabled) and D[8] is written into the lock bit (if enabled). The dat a sub-blocks can be direct ly writ t en by execut ing a STA inst ruction wit h ASI=0xD for the instruction cache data and ASI=0xF for the data cache data. The sub-block to be read in t he indexed cache line and set is select ed by A[4:2].
Not e that diagnostic access to the cache is not possible during a FLUSH operat ion and will cause a dat a except ion (t rap=0x09) if at t empt ed.
4.9.5 Cache Freeze Alert
ESA Alert EA-2012-EEE-17-A details the anomaly in the Leon2FT ipcore that also is applicable for the AGGA-4. This alert also shows a workaround for t his anomaly.
Not e: ESA Alert s can be found at ht t ps://alert s.esa.int
4.10 Byte/Half Word Accesses
Single byt es and half words are written t o memory wit h AHB HSIZE = '000'/'001' indicat ing byt e/half word size t ransactions. Addresses for theses transactions can be byte or half word aligned. (Byte = 0x1, 0x2, 0x3, ... half word = 0x0, 0x2, 0x4, ...). Byt es/half words are duplicat ed during t he writ e process. Example:
stb 0x23, %address
The example above would generat e t he word 0x23232323 on t he AHB Bus.
sth 0x1234, %address
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The example above would generat e t he word 0x12341234 on t he AHB Bus.
If cacheable memory is read using a single byte/half word access, a whole word is transferred over t he AHB bus. Byt e accessing is done inside the processor module. Subsequent reads of bytes/half words in t he fet ched word are served from the cache.
Byt e ordering in memory is big endian. D(31:24) stores address[0x0]; D(23:16) st ores address[0x1] and so on (see Figure 4-7 Big Endian).
Fi gure 4-7 Bi g Endi an
Single byt e/half word accesses to an EDAC protected memory should not be used in applicat ions wit h high memory bandwidt h demands. Byte/half word writes to an un-initialized memory will return an EDAC error. Single byte writes to a 32 bit wide RAM interface needs 5 clock cycles (compared to 3 when writing a whole word). Single byte writes to an 8 bit wide RAM int erface need 25 clock cycles.
Single byt e/half word accesses are not allowed for APB Slaves. The APB Bridge does not take the HSIZE signal int o account . Therefore single byt e writ es like:
stb 0x12, 0x8000_000A0
The example above would store the value 0x12121212 into that register and therefore unexpectedly overwrite the other t hree byt es of t his regist er.
If single bytes/half words are read from an APB device the bridge reads a word from t he APB device but will only t ransfer the addressed byte to the AHB Master. Therefore information may be lost (i.e. if a read to clear mechanism or a FIFO is used). Not e that the memory accesses to the APB area are not cached. Subsequent reads of single bytes will therefore generate a series of accesses to the APB device. However, compilers may try to optimise accesses to hardware (APB) regist ers, merge them, change their order, or even remove accesses whose read values is never used by t he SW. This can have unwant ed side effects (e.g. removing a `clear-on-read'), and t herefore in C-code, every access t o t hese hardware regist ers should use variables / point ers declared as `volat ile'.
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4.11 Memory Controller
The external memory bus is controlled by a programmable memory controller. The cont roller act s as a slave on t he AHB bus. The function of the memory controller is programmed through memory configurat ion regist ers 1, 2 & 3 (MCFG1, MCFG2 & MCFG3) through the APB bus. The memory bus supports three different areas: PROM, SRAM and local I/O. The PROM area can be equipped with PROM/EEPROM or Flash ROM devices. The memory bus can also be configured in 8-bit mode for applicat ions wit h low memory and performance demands.
Not e about the RWE_N and WRITE_N pins. WRITE_N is assert ed 0 on all writ e t ransact ions in all areas (PROM, SRAM, IO) and all bus-widt h / data widt h combinations. RWE_N are complement ary byt e writ e signals, assert ed at same cycle, RWE_N[0] for DATA[31:24], RWE_N[1] for DATA[23:16], RWE_N[2] for DATA[15:8], RWE_N[3] for DATA[7:0]. They are assert ed as follows:
· Wit h 8-bit bus widt h (PROMWidth or RAMWidth = 00)., they are always "1110", indicating that DATA[31:24] holds t he valid dat a
· Wit h 32-bit SRAM (RAMWidth = "10") and ReadModifyWriteEn = 1, t hey are always "0000" · In all other situations (writes to 32-bit PROM, IO or write to 32-bit RAM with ReadModifyWriteEn = 0, t hey
are assert ed according t o t he st ore widt h t o select 1, 2 or 4 byt e lanes
4.11.1 Attaching an external memory controller
To attach an external memory controller, RAMS_N[4] should be used since it allows t he cycle time to vary through the use of BRDY_N. In t his way, delays can be insert ed as shown in [AD-04].
4.11.2 8-bit PROM/EEPROM and SRAM access
To support applications with low memory and performance requirements efficiently, it is not necessary to always have full 32-bit memory banks. The SRAM and PROM areas can be individually configured for 8-bit operat ion by programming the ROM and RAM size fields in the memory configuration registers. 32-bit accesses t o 8-bit memory will be t ransformed in a burst of four or five, with EDAC enabled, read cycles. During writes, only the necessary byt es will be writ t en.
Note: If EDAC is enabled, all byte writes will generate read-modify-write t ransact ions for a complet e word and it s EDAC bit s. So a single byte write on 8-bit EDAC protected memory will generate 10 memory transactions (5 byt es t o read, 5 byt es t o writ e).
Note : EEPROM/Flash based memories operating in 8 bit mode shall only be writ t en using single byt e assembler commands (stb), and parity bytes must be written explicitly by SW to the appropriate address (see section 4.7.2). Using half-word/word/d-word assembler commands (st h, st , st d) leads t o malfunct ion.
4.11.3 8-bit IO access
Similar to the PROM/RAM areas, the I/O area can also be configured to 8-bit s mode. However, t he I/O device will NOT be accessed by multiple 8 bits accesses as the memory areas, but only wit h one single access just as in 32-bit mode. To accesses an I/O device on an 8-bit bus, LDUB/STB should be used.
Note : It is not possible to access the IO space with the DSU or the SpaceWire modules if 8bit IO access is chosen. These mast ers are not capable of byt e/half word t ransact ions. They support 32-bit accesses only.
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4.12 Interrupt Controller 4.12.1 Primary Interrupt Controller (PIC)
NMI 15
DSU Trace Buffer
Timer 4
Parallel I/O (3)
15
GIC high
Timer 3 Parallel I/O (2) MilBus
CIC SpW
Timer 2 Parallel I/O (1)
GIC low
FFT Done Timer 1
Parallel I/O (0) AHB Error 1
IRQ Pending IRQ Force
IRQ Mask Priority Select
OR
AND
Priority Encoder
4 IRL[3:0]
Fi gure 4-8: Pri mary Interrupt C ontrol l er (PIC )
When an interrupt is generated, the corresponding bit is set in the PrimIntPending register. The pending bits are ANDed wit h t he interrupt mask which is contained in the PrimIntMaskAndPrio regist er and t hen forwarded t o t he priorit y selector. Each interrupt can be assigned to one of two levels as programmed in the PrimIntMaskAndPrio register. Level 1 has higher priority than level 0. The interrupts are prioritized wit hin each level, with interrupt 15 having t he highest priority and interrupt 1 the lowest. The highest interrupt from level 1 will be forwarded t o t he IU - if no unmasked pending int errupt exist s on level 1, t hen t he highest unmasked int errupt from level 0 will be forwarded.
The NMI can not be masked through the mask register; it also has always priority level 1. When t he IU acknowledges t he int errupt , t he corresponding pending bit will aut omat ically be cleared.
Int errupts can also be forced by setting a bit in the PrimIntForce register. In this case, t he IU acknowledgement will clear t he force bit rat her t han t he pending bit .
By set ting the corresponding clear bit in the PrimIntClear register the respective pending bit in the PIC will be cleared. The IU acknowledgement will not be able to clear the int errupt s t hat are not st ored inside t he primary int errupt cont roller (GIC high, CIC, GIC low). The interrupt handling routine has to make sure that the corresponding interrupt is cleared on its source. Also if a secondary interrupt controller interrupt shall be forced, it has to be forced at t he source.
The GIC low/high pending bits in the primary interrupt controller are directly connected to the interrupt vect or queues in t he GIC. That means if the GIC interrupt vector queue is not empty, the corresponding GIC low/high pending bit in t he PIC will be on. If the GIC interrupt vector queue is empty the corresponding GIC low/high pending bit in the PIC is not active.
The pending bits inside the CIC are OR'ed together and are direct ly connect ed t o t he CIC pending bit in t he PIC. Therefore if any pending bit inside t he CIC will be act ive, t he CIC pending bit in t he PIC will be on.
4.12.1.1 Pending Interrupt Cleared by Ticc AGGA4 is affect ed by t he following issue (ESA IPN #384):
An int errupt (tt = 0x11 0x1F), pending in the PrimIntPending or the PrimIntForce registers is systematically cleared by a software trap (Ticc) which shares the same lower 6 bit [5:0] in its trap type. As a side effect , if cache-freeze on int errupt is activated by setting CacheCtrl.DF and/or CacheCtrl.IF, the cache will be frozen erroneously. The anomaly only happens when the trap indicated in the pending or force irq register shares the lower 6bits with t he soft ware t rap number used in t he Ticc inst ruct ion.
The following t able summarises which soft ware t raps would clear which pending int errupt :
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Pending int err up t SW Trap t hat cl ears int errupt
(val ue of 't t')
(val ue of 't t')
0x11
0x91, 0xD1
0x12 0x13 0x14
0x92, 0xD2 0x93, 0xD3 0x94, 0xD4
0x15 0x16
0x95, 0xD5 0x96, 0xD6
0x17 0x18 0x19
0x97, 0xD7 0x98, 0xD8 0x99, 0xD9
0x1A 0x1B 0x1C
0x9A, 0xDA 0x9B, 0xDB 0x9C, 0xDC
0x1D 0x1E
0x9D, 0xDD 0x9E, 0xDE
0x1F
0x9F, 0x DF
Table 4-8: Pending cleared by Ticc
The following software workaround can be adopt ed: No Ticc inst ruct ion shall use t rap numbers which result in a t t value of 0x9- or 0xD
4.12.2 GNSS Interrupt Controller (GIC)
The first secondary interrupt controller called GNSS Interrupt Controller (GIC) is locat ed inside t he GNSS clock domain. Two int errupt signals (t ransport ing t he priorit y) are provided t o t he primary int errupt cont roller. The GNSS int errupt controller provides priorisation of the trigger events. The following events are served by t he GNSS int errupt cont roller:
Trigger Event
GNSS Channel Int egrat ion Epoch elapsed
36
GNSS Pulse Per Second Epoch elapsed
1
GNSS Ant enna Swit ch Epoch elapsed
1
GNSS Measurement Epoch elapsed
1
GNSS Power Level Det ect or I/Q elapsed
1
GNSS Power Level Det ect or 5I elapsed
1
GNSS DMA error occurred
1
Tabl e 4-9: GNSS Interrupts
Number
The implementation of the GNSS Int errupt Controller is similar to the secondary interrupt controller of t he LEON-IP. An int errupt priority register is added to provide the possibility to assign each GNSS int errupt to one of t wo int errupt levels. Also a queue mechanism is implemented, which can be used to store the interrupts in t he order of occurrence. The timestamp (IMT value) of an interrupt is st ored inside t he GNSS regist ers. The GNSS Int errupt Cont roller is depict ed in Figure 3-4.
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GNSS Interrupts
IRQ Pending
Priority Encoder
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GIC QUEUE HIGH
IRQ 11
6
Vector_high
GIC QUEUE LOW
IRQ 5
6
Vector_low
IRQ Mask
Priority Select
Fi gure 4-9: GNSS Interrupt C ontrol l er
If an interrupt is enabled trough the mask (GIC_Mask0/1), the interrupt is priorized via the GIC_Prio_0/1 registers and queued in eit her the GIC_QueueHigh or GIC_QueueLow queue according t o t heir priorit y. The 6bit queue ent ry ident ifies the interrupt source (e.g. channel, ME, PPS, etc). Also the queue maintains the timely order (first in first out). If an int errupt is regist ered in t he queue it is aut omat ically cleared by t he hardware in t he pending regist er (GIC_Pend0/1) and can not be cleared by the software. If the user reads the queue entry, also t he queue ent ry will be cleared automatically by the hardware and therefore must not be cleared by the software. The queue has a dept h of 64 ent ries. If a queue is empty a read on it will return the value 0x3F. If a queue is full, the corresponding pending bits will remain in the pending register (GIC_Pend0/1) until the queue has a free entry. Once there is a free entry, the pending bit is registered in the queue and automatically cleared in the pending register (GIC_Pend0/1). However in t his case (full queue) t he user has to take into account that the interrupts may not be entered in the correct time order once t he queue get s free again. If the PIC signals a GNSS low/high interrupt it is recommended to read the corresponding GIC queue in t he int errupt service rout ine unt il t he queue is empt y and t hus do a bat ch processing of int errupt event s.
If an interrupt is disabled through the mask (GIC_Mask0/1), the pending bit is not cleared automatically. The user has to clear it by set t ing t he corresponding bit in t he int errupt clear (GIC_Clear0/1) regist er.
This allows t reating some events by polling (by masking the interrupt and reading the pending bit), while ot her event s can be handled by an int errupt handler (by unmasking t he int errupt and reading t he queue).
By reading the register GIC_QueueStatus it is also possible to get the current fill st at us of t he GIC_QueueHigh and GIC_QueueLow as well as the informat ion whet her one of t he queues had an overflow somewhere in t he past .
Note: The internal Pending register in the AGGA-4 has 42bits. Since it is not possible for the software to read all 42bits at a time, a special mechanism has been implemented. If the software reads the GIC_Pend0 register it reads t he lower 32bit s of the 42bit Pending register. The upper 10bits of the 42bit Pending register are st ored by t he hardware int o a shadow register. If the software now reads the GIC_Pend1 register, it will read the content of t he shadow regist er and get s t he residual 10bits of the latched 42bit Pending register. Therefore in order to read the current stat us of t he upper 10bit s of t he 42bit Pending regist er, t he soft ware always has t o read first GIC_Pend0 and t hen GIC_Pend1.
Note: If a GNSS channel has enabled GNSS DMA, t he Integration Epoch (IE) is not directly signalled from the channel t o the GIC, but is delayed by the DMA machine until the DMA transfer of t hat channel is finished. That way it is ensured that the user can be sure, once he gets an IE interrupt, that the DMA is already done. If a GNSS channel has disabled GNSS DMA t he Integration Epoch (IE) is directly signalled to the GIC. Note that only the notificat ion t o t he user is delayed, not the IE mechanism itself. Therefore the IE observables do of course carry t he correct cont ent .
Note: After reset of the GNSS core the GIC queue low and the GIC queue high can have one arbitrary entry. Therefore if t he user wants to make use of these queues, it is recommended to read the GIC queues after a GNSS reset unt il 0x3F (queue empt y) is readback.
4.12.3 Communication Interrupt Controller (CIC)
The second secondary int errupt cont roller is t he Communicat ion Int errupt Cont roller (CIC).
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UART0
UART1 SPI CRC
IRQ Pending
CIC
S-GPO
SpW MilBus Nominal MilBus Reset MilBus Error
IRQ Mask
Fi gure 4-10: C ommuni cati on Interrupt C ontrol l er
The implementation of the Communication Interrupt Controller is similar to the secondary interrupt cont roller of t he LEON-IP. When a communication interrupt is generated, the corresponding bit is set in the CIC_Pending register. The pending bit s are ANDed wit h t he CIC_Mask regist er and t hen forwarded t o t he PIC. By set ting the corresponding clear bit in the CIC_Clear register the respective pending bit in t he CIC will be cleared. However the SpaceWire Module and the Mil-Bus IP Core do have t heir own int errupt cont rollers. Therefore t he int errupts of those modules are just mirrored in the CIC pending register, but they are not stored there. They are st ored in t heir own interrupt controller. Therefore the SpaceWire and Mil-Bus interrupts have to be cleared in t he SpaceWire respect ively Mil-Bus int errupt cont roller. The following event s are served by t he Communicat ion Int errupt Cont roller:
Trigger Event
Mil-Bus Nominal (C53It )
1
Mil-Bus Reset (C53Rst )
1
Mil-Bus Error (C53Err)
1
Spacewire
1
UART-1 (RxDone, TxDone, Error)
3
UART-0 (RxDone, TxDone, Error)
3
SPI
1
CRC Ready
1
SGPO Overrun
1
Tabl e 4-10: C IC Interrupts
Number
4.13 Timer Unit
The timer unit implements four 32-bit timers and one 10-bit shared prescaler (see Figure 4-11). The prescaler is clocked by t he Leon clock and decremented on each clock cycle. When t he prescaler underflows, it is reloaded from t he prescaler reload register (TimerPrescaleReload) and a timer tick is generated for the four timers. The effective division rat e is equal to prescaler reload register value + 1. The current value of the prescaler can always be accessed by reading t he TimerPrescaleCounter regist er.
The operation of the timers is controlled through the timer control register (TimerN_Ctrl). A timer is enabled by sett ing t he EN bit in the TimerN_Ctrl register. Note that the prescaler and t imer reload values must be set t o a legal value before enabling the timers. The timer value is then decremented each time the prescaler generates a timer tick. When a t imer underflows, it will automatically be reloaded wit h the value of the timer reload register (TimerN_Reload) if the RL
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bit in the TimerN_Ctrl is set, otherwise it will stop at 0xffffffff and reset the EN bit. The effective division rate is equal t o t imer reload regist er value + 1. An int errupt will be generat ed aft er each underflow.
The timer can be reloaded wit h the value in t he reload regist er at any t ime by writ ing a "1" t o t he LD bit in t he TimerN_Ctrl.
The current value of any of t he four t imers can be accessed by reading t he TimerN_Counter regist er.
To minimize complexity, the four timers share the same prescaler and decrement er as shown in Figure 4-11. The minimum allowed prescaler division factor is 8 (TimerPrescaleReload needs to be set to 7 at least before enabling any of t he timers). There is no rest rict ion t o t he value programmed in t he TimerN_Reload regist ers (0..0xFFFF).
Fi gure 4-11 Ti mer Uni t
4.14 Write Protection Unit
4.14.1 Overview
Write protection is provided to protect the RAM area against accident al over-writ ing. It is implement ed wit h t wo met hods: the address/mask method as implemented in the original LEON-2 model, and an ext ended version using st art/end addressing. Both methods can be used simultaneously. Therefore in total AGGA-4 has 4 Write Protect Unit s. Aft er reset writ e prot ect ion is disabled for all unit s. Note: The APB registers (0x8...) and the DSU area (0x9...) can not be protected with the Write Protection Unit . They are always accessible in user and superuser mode. The I/O area can be prot ect ed by set t ing t he IOEnable bit in t he MCFG1 regist er t o zero. The PROM area can be prot ect ed by set t ing t he PROMWriteEn bit in t he MCFG1 regist er t o zero.
4.14.2 Address/Mask Write Protection
The address/mask write protection is implemented with two block protect units capable of disabling or enabling writ e access t o a binary aligned memory block in the range of 32 Kbyte - 1 Gbyt e. Block prot ect unit 1 is cont rolled by WriteProtect1, block protect unit 2 is controlled by WriteProtect2. The units operate as follows: on each write access to
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RAM, address bits (29:15) are XORed with the TAG field in the control register, and ANDed with t he MASK field. A writ e protection hit is generated if the result is equal to zero, and the corresponding unit is enabled in block prot ect mode (BP = 1) or if t he result s is not zero and t he unit is enabled in segment mode (BP = 0).
Note: The ROM area can be writ e prot ect ed by clearing t he PROMWriteEn bit in t he MCFG1 regist er.
4.14.3 Start/End Address Write Protection
The start/end address write protect scheme contains two identical units that compare the AHB writ e address against a st art and an end address. They can be cont rolled via t he regist ers WriteProtectStartAddressN and WriteProtectEndAddressN, where N can be either 3 for Write Protect Unit 3 and 4 for Write Protect Unit 4. If operat ed in block protect mode (BP = 1) in the WriteProtectStartAddressN register and the AHB write address is equal or higher t han the start address and lower or equal to the end address, a write protect hit is generated. If operated in segment mode (BP = 0) in the WriteProtectStartAddressN register, a write protect hit is generated when the write address is lower than t he st art address, or higher t han t he end address.
The write protection can be enabled by setting the UM bit t o "1" in user mode or by set t ing t he SU bit t o "1" in superuser mode.
Note: All AHB Masters, except for the CPU and the Mil-Bus use the HPROT value "0011" meaning t hat t hey are "superuser". The Mil-Bus uses t he HPROT value "0000" meaning t hat it is "user". The CPU can be bot h.
4.14.4 Generation of Write Protection
The results from the t wo writ e prot ect ion schemes are combined t oget her according t o t he following scheme: · If all enabled units operate in block protect mode, then a write protect error will be generat ed if any of t he enabled unit s signal a writ e prot ect ion hit . · If at least one of the enabled units operates in segment mode, then a write protect error will be generat ed only if all unit s operat ing in segment mode signal a writ e prot ect ion hit .
A writ e protection error will result in that the AHB write cycle is ended with an AHB error response and the data is not writ t en to the memory. The ROM area can be write protected by clearing the PROMWriteEn bit in the MCFG1 register.
"Enabled" in t his cont ext means enabled eit her in user or in supervisor mode or bot h.
4.15 AHB Status Register
An access triggering an error response on the AHB bus will be regist ered in t wo regist ers; AHBFailingAddress and AHBStatus. The failing address register will store the address of the access while the status register will store the access and error types. The regist ers are updat ed when an error occurs. Once t he AHBFailingAddress regist er and t he AHBStatus register have been updated by the hardware, the NE (new error) bit in the AHBStatus regist er is set by t he hardware. The two registers are then locked, no new error will be recorded as long as NE is set, however the associat ed int errupts are still raised. After the software has read the AHBFailingAddress and the AHBStatus it must clear the NE bit t o re-arm t he regist ers.
The AHB status register is also triggered by correct able one-bit errors in t he ext ernal SRAM. So if t he memory cont roller identifies a correctable error in the attached memory, the CE (correctable) and NE (new error) bit s are set .
When t he NE bit is set , an int errupt is generat ed t o inform t he processor about t he error.
For un-correctable errors the NE bit and the corresponding interrupt in the primary interrupt controller has to be cleared.
For correctable errors the failed memory location has to be refreshed by a read-write cycle to the failed address, the NE and CE bit in the AHBStatus register has to be cleared, and finally the corresponding interrupt in the primary int errupt cont roller has t o be cleared.
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4.16 Hardware Debug Support Unit
4.16.1 Overview
The LEON processor includes hardware debug support to aid software debugging on target hardware. The support is provided through two modules: a debug support unit (DSU) and a debug communication link (DCL). The DSU can put t he processor in debug mode, allowing read/write access to all processor registers and cache memories. The DSU also cont ains a trace buffer which st ores execut ed inst ruct ions or dat a t ransfers on t he AMBA AHB bus. The debug communicat ions link (UART or SpaceWire) implement s a simple read/writ e prot ocol.
Fi gure 4-12 DSU O vervi ew
The debug support unit is used control the trace buffer and the processor debug mode. The DSU is attached to the AHB bus as slave, occupying a 2 Mbyte address space. Through this address space, any AHB master can access the processor regist ers and the contents of the trace buffer. The DSU control registers can be accessed at any time, while the processor regist ers and caches can only be accessed when the processor has entered debug mode. The trace buffer can be accessed only when tracing is disabled/completed. In debug mode, the processor pipeline is held and the processor is cont rolled by t he DSU. Ent ering t he debug mode can occur on t he following event s:
execut ing a breakpoint instruction (ta 1) int eger unit hardware breakpoint/watch point hit (trap 0xb) rising edge of the external break signal (DSU_BRE pin) set ting the break-now (BN) bit in the DSU_Ctrl register a t rap that would cause the processor to enter error mode occurrence of any, or a selection of traps as defined in the DSU control register aft er a single-step operation DSU breakpoint hit
The debug mode can only be entered when the debug support unit is enabled through an external pin (DSU_EN). When t he debug mode is ent ered, t he following act ions are t aken:
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PC and nPC are saved in temporary registers (accessible by the debug unit) an out put signal (DSU_ACT pin) is asserted to indicate the debug state t he timer unit is stopped to freeze the LEON timers
Not e: The wat chdog continues to run, if enabled.
The instruction that caused t he processor t o ent er debug mode is not execut ed, and t he processor st at e is kept unmodified. Execution is resumed by clearing the BN bit in the DSU_Ctrl regist er or by de-assert ing DSU_EN. The t imer unit will be re-enabled and execution will continue from the saved PC and nPC. Debug mode can also be ent ered aft er the processor has entered error mode, for instance when an application has terminated and halt ed t he processor. The error mode can be reset and t he processor rest art ed at any address.
4.16.2 DSU Memory Map
The DSU memory map can be seen in t he programming sect ion (chapt er 7.3) Note : The DSU memory addresses from 0x9000_0000 to 0x9FFF_FFFC can only be accessed if DSU is enabled via DSU_EN pin set to '1'. This is done to avoid accidental (in-flight) activation of the debug funct ionalit y (break point s et c.). Note: The trace buffer starts at 0x90010000 and ends at 0x90011FFC and is mirrored 8 t imes in t he memory range 0x90010000 0x90020000. If t racing is enabled, t he t race buffer cannot be accessed by soft ware.
The IU/FPU regist ers can be accessed at t he following addresses (window = psr.cwp): %on : 0x90020000 + (((window * 64) + 32 + 4*n) mod 512) %ln : 0x90020000 + (((window * 64) + 64 + 4*n) mod 512) %in : 0x90020000 + (((window * 64) + 96 + 4*n) mod 512) %gn : 0x90020200 + 4*n %fn : 0x90030000 + 4*n
4.16.3 Trace Buffer
The trace buffer consists of a circular buffer t hat st ores execut ed inst ruct ions or AHB dat a t ransfers. A 30-bit TimeTagCounter is also provided and stored in the trace as time tag. The trace buffer operation is controlled through the DSU_Ctrl register and the TraceBufferCtrl register. When the processor enters debug mode, tracing is suspended. The size of t he t race buffer is 512 lines (dept h) x 128bit (widt h) corresponding t o 8kbyt e.
The t race buffer is 128 bit s wide, t he informat ion st ored is indicat ed in Table 4-11 and Table 4-12 below:
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Bits Name 127 AHB breakpoint hit 126 -
125:96 TimeTagCounter 95:92 IRL 91:88 PIL 87:80 Trap type 79 Hwrite 78:77 Htrans 76:74 Hsize 73:71 Hburst 70:67 Hmaster 66 Hmastlock 65:64 Hresp 63:32 Load/Store data 31:0 Load/Store address
Definition Set to `1' if a DSU AHB breakpoint hit occurred Unused The value of the TimeTagCounter Processor interrupt request input Processor interrupt level (psr.pil) Processor trap type (psr.tt) AHB HWRITE AHB HTRANS AHB HSIZE AHB HBURST AHB HMASTER AHB HMASTLOCK AHB HRESP AHB HRDATA or HWDATA AHB HADDR
Tabl e 4-11 Trace Buffer Li ne Defi ni ti on (AHB Traci ng Mode)
Not e: See chapter 4.15 for AHB HMASTER and HSIZE explanation. The other AHB signals behave like stat ed in t he AHB Specificat ion (see [RD-06]).
Bits Name 127 Instruction breakpoint hit 126 Multi-cycle instruction
125:96 Time tag 95:64 Load/Store parameters 63:34 Program counter 33 Instruction trap 32 Processor error mode 31:0 Opcode
Definition Set to `1' if a DSU instruction breakpoint hit occurred. Set to `1' on the second and third instance of a multi-cycle instruction (LDD, ST or FPOP) The value of the time tag counter Instruction result, Store address or Store data Program counter (2 lsb bits removed since they are always zero) Set to `1' if traced instruction trapped Set to `1' if the traced instruction caused processor error mode Instruction opcode
Tabl e 4-12 Trace Buffer Li ne Defi ni ti on (Instructi on Traci ng Mode)
During instruction tracing, one instruction is stored per line in t he t race buffer wit h t he except ion of mult i-cycle inst ructions. Multi-cycle instructions are entered two or three times in t he t race buffer. For st ore inst ruct ions, bit s [63:32] correspond to the store address on the first entry and to the stored data on the second entry (and third in case of STD). Bit 126 is set on the second and third entry to indicate this. A double load (LDD) is ent ered t wice in t he t race buffer, with bits [63:32] containing the loaded data. Multiply and divide instructions are entered twice, but only the last ent ry contains the result. Bit 126 is set for the second entry. For FPU operation producing a double-precision result, t he first entry puts the MSB 32 bits of the results in bit [63:32] while the second entry put s t he LSB 32 bit s in t his field. When a t race is frozen, int errupt 14 (DSU Trace Buffer) is generat ed.
The DSU t ime tag counter is incremented each clock as long as the processor is running. The counter is st opped when t he processor ent ers debug mode, and rest art ed when execut ion is resumed.
The trace buffer can trace executed instructions, transfers on AHB or both (mixed-mode). The t race buffer cont rol regist er contains two counters that store the address of which location of the trace buffer will be written on next t race. Since t he buffer is circular, it actually points to the oldest entry in the buffer. The indexes are automatically incremented aft er each st ored t race ent ry.
When both instructions and AHB transfers are traced (`mixed mode t racing'), t he buffer is divided on t wo halves. Inst ructions are stored in the lower half (0x90010000) and AHB t ransfers in the upper half (0x90011000) of the buffer. The MSB bit of the AHB index counter is then automatically kept high, while the MSB of the instruction index counter is kept low. When the AF bit in the TraceBufferCtrl register is set, AHB tracing is st opped when t he processor is in debug mode. When AF is cleared, t racing cont inues unt il t he AHB t race enable bit s are cleared.
Addit ionally there is the possibility to apply trace buffer filtering. AHB trace buffer filt ering reduces t he amount of AHB t ransactions dumped into the trace buffer and helps debugging the access from specific mast ers or t o specific address areas on the AHB bus. Please note that master and slave filtering is subtractive, an access will be traced only if
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it passes both filters. With a setting of MFILT = 2 and SFILT = 1 for example, only accesses from AHB mast er #2 t o addresses st art ing wit h 0x8.... (APB regist ers) will be t raced. Programming a 0 in both fields disables the trace filtering, all AHB accesses are traced (LEON2 default functionalit y). Not e that regardless of the trace filter settings, AHB tracing also needs to be enabled with the usual configurat ion bit s (bit 0 of t he DSU_Ctrl regist er and bit 25 of t he TraceBufferCtrl regist er).
Note: The TraceBufferCtrl regist er is not cleared by any reset .
4.16.4 DSU Control Register
The DSU_Ctrl register gives many possibilities t o influence t he DSU behaviour. The det ails can be found in t he programming sect ion (chapt er 7.3.1.1)
4.16.5 DSU (Hardware) Breakpoints
The DSU contains two breakpoint registers for matching either AHB addresses or executed processor inst ruct ions. A breakpoint hit is typically used to freeze the trace buffer, but can also put the processor in debug mode. Freezing can be delayed by programming the delay counter DCNT field in the DSU_Ctrl register to a non-zero value. In t his case, t he DCNT value will be decremented (after breakpoint condition) for each additional trace until it reaches zero. Then t he t race buffer is frozen. If the BT bit in the DSU_Ctrl register is set, the DSU will force the processor int o debug mode when t he trace buffer is frozen. Note that due to pipeline delays, up to 4 additional instructions can be execut ed before t he processor is placed in debug mode.
A mask register is associated with each breakpoint, allowing breaking on a block of addresses. Only address bit s wit h t he corresponding mask bit set to `1' are compared during breakpoint detection. To break on executed instructions, t he EX bit in the AHB_BreakAddressN register should be set. To break on AHB load or store accesses, t he LD and/or ST bit s of t he AHB_MaskN regist er should be set .
4.16.6 Instruction (Software) Breakpoints
To insert instruction breakpoints, the breakpoint instruction (ta 1) should be used. This will leave the four IU hardware breakpoints free to be used as data watch points. Since cache snooping is only done on the data cache, t he inst ruct ion cache must be flushed after the insertion or removal of breakpoints. To minimize t he influence on execut ion, it is enough to clear the corresponding instruction cache tag (which is accessible t hrough t he DSU). The DSU hardware breakpoints should only be used to freeze the trace buffer, and not for software debugging since there is a 4-cycle delay from t he breakpoint hit before t he processor ent ers t he debug mode.
4.16.7 DSU Trap Register
The DSU_Trap register is a read-only register that indicates which SPARC trap type that caused the processor t o ent er debug mode. When debug mode is force by setting the BN bit in t he DSU_Ctrl regist er, t he t rap t ype will be 0xb (hardware wat ch point t rap).
4.16.8 Single Stepping
By writ ing the SS bit and resetting the BN bit in the DSU_Ctrl register, the processor will resume execut ion for one inst ruct ion and t hen aut omat ically ent er debug mode.
4.16.9 Booting from DSU
By asserting DSU_EN and DSU_BRE at reset time, the processor will directly enter debug mode without executing any inst ructions. The system can then be initialized via the DSU communication link, and applications can be downloaded and debugged.
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5 Interface Modules
5.1 UART
Two identical DMA capable UARTs are provided for serial communications. The UARTs support data frames wit h 8 dat a bits, one optional parity bit and one stop bit. To generate the bit-rate, each UART has a programmable 12-bit clock divider programmable via the UARTn_Scaler register. Hardware flow-control is support ed t hrough t he RTSN/CTSN hand-shake signals.
5.1.1 Transmitter Operation
The t ransmit t er is enabled t hrough t he TXEN bit in t he UARTn_Ctrl regist er.
Communication over UART is done by transferring data packets using DMA. To t ransmit dat a t he CPU writ es t he relevant data into the memory and sets the DMA Start Address Pointer UARTn_Tx_SAP to the start address of the dat a. The St art Address Pointer (SAP) will contain the address of the first memory cell t o be used. Then t he DMA End Address Pointer UARTn_Tx_EAP has to be set to the end address of t he dat a. The End Address Point er (EAP) will cont ain the address of the last memory cell to be used. Writing EAP starts the I/O activity and the DMA transfer of t he dat a is st art ed. Not e t hat t he St art Address Point er always has t o be 32bit aligned. Therefore bit 1:0 of t he UARTn_Tx_SAP are always zero. The End Address Point er can be byt e aligned. The Current Address Point er UARTn_Tx_CAP always points to the next 32bit address which will be transmit t ed. By reading t he Current Address Point er during t he t ransfer t he soft ware can det ermine t he progress of t he t ransmission if needed.
RAM
Tx Area
UART Transmitter Part
T5
T6
T7
T8
31
0
SAPTx CAPTx EAPTx
TxBuffer (8 Byte)
Tx Shifter
Tx
TXEN
(if HW handshake)
CTSN
Fi gure 5-1: UART Transm i t Path
The data in the RAM which has to be transmitted is then transferred into the TxBuffer. From there on it is converted t o a serial stream for the transmitter serial output pin (UARTn_TX). It automatically sends a start bit followed by eight data bit s, an opt ional parit y bit , and one st op bit (Figure 5-2).
Fi gure 5-2 UART data fram e s
Following the transmission of the stop bit, if no new character is available in the TxShifter, the transmit t er serial dat a out put remains high and the transmitter shift regist er empt y bit (TSE) will be set in t he UARTn_Status regist er. Transmission resumes and the TSE bit is cleared when a new character is loaded into the TxShifter. When the TxBuffer is empty the TE bit in the UARTn_Status register is set. If there is data in t he TxBuffer t he TE bit is cleared. If t he t ransmitter is disabled by setting the TXEN bit in the UARTn_Ctrl register to zero the transmitter will immediately st op
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any active transmission including the character current ly being shift ed out from t he t ransmit t er shift regist er. A t ransmission can be considered complet ed when t he TE and TSE bit s are bot h assert ed.
If flow control is enabled, the CTSN input must be low in order for the character to be transmitted. If it is de-asserted in t he middle of a transmission, the character in the shift register is transmit t ed and t he t ransmit t er serial out put t hen remains inactive until CTSN is asserted again. If the CTSN is connected to receivers RTSN, overrun can effect ively be prevent ed.
If all data of the defined transmit area has been transmitted an interrupt (UARTn_TxDone) is generated which is visible and cont rollable in t he Communicat ion Int errupt Cont roller (CIC).
5.1.2 Receiver Operation
The receiver is enabled for dat a recept ion t hrough t he receiver enable RXEN bit in t he UARTn_Ctrl regist er.
The receiver looks for a high to low t ransition of a start bit on t he receiver serial dat a input pin. If a t ransit ion is det ected, the state of the serial input is sampled half bit clocks later. If the serial input is sampled high t he st art bit is invalid and the search for a valid start bit continues. If the serial input is still low, a valid st art bit is assumed and t he receiver continues to sample the serial input at one bit time intervals (at the theoretical centre of the bit) until the proper number of data bits and the parity bit have been assembled and one stop bit has been detected. The serial input is shifted t hrough an 8-bit shift register where all bits have to have the same value before the new value is t aken int o account , effect ively forming a low-pass filt er wit h a cut -off frequency of 1/8 SysClk.
During reception, the least significant bit is received first. The dat a is t hen t ransferred from t he RxShift er t o t he RxBuffer and the data ready (DR) bit is set in the UARTn_Status register as soon as the RxBuffer contains at least one dat a frame. The parity, framing and overrun error bits are set at the received byte boundary, at the same time as t he DR bit is set. The data frame is not stored in the RxBuffer if an error is detected. Also, the new error st at us bit s are ORed wit h t he old values before they are stored into the UARTn_Status register. Thus, they are not cleared unt il writ t en t o wit h zeros from the APB bus. If both the RxBuffer and the RxShifter are full when a new st art bit is detected, t hen t he character held in the RxShifter will be lost and the overrun bit (OVR) will be set in the UARTn_Status regist er. If flow cont rol is enabled, then the RTSN will be negated (high) when a valid st art bit is det ect ed and t he RxBuffer is full. When t he RxBuffer is read, t he RTSN will aut omat ically be reassert ed again.
UART Receiver Part
RAM
Rx Area
Rx RTSN
Rx Shifter
RxBuffer (8 Byte)
(if HW handshake) Rx Buffer Full
SAPRx CAPRx EAPRx
Fi gure 5-3: UART Re ce i ve Path
R1 R2 R3 R4
31
0
To receive data the CPU has to configure the DMA St art Address Pointer UARTn_Rx_SAP to the st art address of t he reception RAM area. The Start Address Pointer (SAP) will contain the address of the first memory cell to be used. Then t he DMA End Address Pointer UARTn_Rx_EAP has to be set to the end address of the receive area. The End Address Pointer (EAP) will contain the address of the last memory cell to be used. Writing EAP starts the I/O act ivit y and t he cont ents of the RxBuffer are written via DMA to the memory. The Current Address Pointer (CAP) will be maint ained by t he ASIC. It will be set to SAP after EAP has been written. The Current Address Point er can be used t o read t he number of byt es which have been received so far (UARTn_Rx_CAP UARTn_Rx_SAP).
While the UARTn_Rx_CAP and UARTn_Rx_EAP Pointer can address byte wise, the UARTn_Rx_SAP has t o be 32bit aligned. Therefore bit 1:0 of t he writ t en UARTn_Rx_SAP are always zero.
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Note: The UART DMA always does 32bit writes into memory. Having a look to Figure 5-3 and assuming SAP would be set to 0x40000000 this would mean that the DMA would start writing the following data upon recept ion on t he following addresses:
· Aft er reception of t he first byt e: R1 00 00 00 on address 0x40000000 · Aft er recept ion of t he second byt e: R1 R2 00 00 on address 0x40000000 · Aft er reception of the thrird byt e: R1 R2 R3 00 on address 0x40000000 · Aft er reception of the fourth byt e: R1 R2 R3 R4 on address 0x40000000 · Aft er reception of t he fift h byt e: R5 00 00 00 on address 0x40000004 · ... Therefore, if the UARTn_Rx_EAP Pointer is not 32bit aligned, the user has to make sure that the residual 1..3 bytes after t he UARTn_Rx_EAP point er are not used by t he soft ware, since t hey cont ain invalid dat a.
If all dat a of t he defined receive area has been received (UARTn_Rx_CAP > UARTn_Rx_EAP) an int errupt (UARTn_RxDone) is generated which is visible and controllable in the Communicat ion Int errupt Cont roller (CIC).
5.1.3 Baud Rate Generation
Each UART contains a 12-bit down-counting scaler to generate the desired baud-rat e. The scaler is clocked by t he SysClk and generates a UART tick each time it underflows. It is reloaded wit h the value of the ReloadValue field in t he UARTn_Scaler register after each underflow. The resulting UART tick frequency should be 8 t imes t he desired baudrat e minus one. Therefore t he correct ReloadValue can be det ermined wit h t he following formula:
= 8 - 1
Note: If the baud rate is changed during operation up to 16 bytes can be corrupted until the new baud rat e set t ing will work.
5.1.4 General UART Rules
Here below some addit ional behaviour which applies for t he whole UART: · A "1" writ t en t o UART_Reset regist er will st op all I/O act ivit y on t he memory. · It will be sole responsibility of the user to specify meaningful addresses. The ASIC will not perform any plausibilit y checks. It is assumed, t hat SAP EAP always.
5.1.5 Error Handling
Each UART has five error conditions which can trigger the UARTn_Error interrupt in t he Communicat ion Int errupt Cont roller (CIC). The error int errupt can be masked/forced/cleared as a whole in t he CIC.
5.1.5.1 Framing Error If a framing error is detected, the FER bit in the UARTn_Status regist er of t he corresponding UART is set and t he UARTn_Error int errupt is generat ed (if not masked in t he CIC). The FER bit can be cleared by writ ing a "0" t o t hat bit .
5.1.5.2 Parity Error If a parity error is detected, the PER bit in t he UARTn_Status regist er of t he corresponding UART is set and t he UARTn_Error int errupt is generat ed (if not masked in t he CIC). The PER bit can be cleared by writ ing a "0" t o t hat bit .
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5.1.5.3 Overrun in Receiver If t he RxShifter and the RxBuffer are full and new dat a is incoming, an overrun is detected in t he UART receiver and t he OVR bit in the UARTn_Status register of the corresponding UART is set and a UARTn_Error interrupt is generat ed (if not masked in t he CIC). The OVR bit can be cleared by writ ing a "0" t o t hat bit .
5.1.5.4 Break Received If a Break Received is detected, the BR bit in the UARTn_Status register of t he corresponding UART is set and t he UARTn_Error int errupt is generat ed (if not masked in t he CIC). The BR bit can be cleared by writ ing a "0" t o t hat bit .
5.1.5.5 Timeout If dat a is available in the RxBuffer and is not read within a certain amount of time a timeout signal can be generat ed, which swit ches the RTO bit in the UARTn_Status register to "1" and which generates the UARTn_Error interrupt (if not masked in t he CIC). The RTO bit is cleared if the data in the RxBuffer is read, or if the timeout feature is disabled or if the UART receiver is disabled. The timeout feature can be switched on/off by the programming of the Timeout Enable (TOE) bit in t he UARTn_Ctrl regist er. The timeout period can be programmed by the TimeoutCnt field in the UARTn_Scaler register. The t imeout scaler is clocked with the BaudRate which can also be expressed as SysClk/(Scaler+1)/8. The TimeoutCnt field has therefore t o be programmed wit h t he desired amount of BaudTicks 1. If t he timeout feature is enabled, the timeout counter is reloaded wit h t he TimeoutCnt whenever t he RxBuffer was empty and now has data. The counter then starts running downwards towards zero and either stops if the RxBuffer get s empt y before t he count er elapses or t he count er reaches zero and generat es t he t imeout .
5.1.6 Internal Loopback
If t he LB bit in UARTn_Ctrl register is set , t he UART will be in t he int ernal loop back mode. In t his mode, t he t ransmitter output is internally connected to the receiver input and t he RTSN is connect ed t o t he CTSN. It is t hen possible to perform loop back tests to verify operation of receiver, transmitter and associated software routines. In t his mode, t he out put s remain in t he inact ive st at e, in order t o avoid sending out dat a.
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5.2 SpaceWire
5.2.1 SpaceWire Module
The AGGA-4 provides a SpaceWire module (see also Figure 5-4) wit h four ident ical SpaceWire int erfaces (or channels) for communicat ion purposes.
The four communication SpaceWire links share a common AHB interface and a common DMA controller. Data can be t ransferred via DMA from a SpaceWire link to the external memory and vice versa. The DMA function requires that the SpaceWire-AHB int erface has t he capabilit y t o become AHB mast er.
The SpaceWire module includes an interrupt controller (see also Figure 5-5). A common SpaceWire interrupt signal is generated t o signal a request of service t o t he processor via t he Communicat ion Int errupt Cont roller (CIC).
The operation of the SpaceWire interfaces is controlled by regist ers. The regist ers used t o cont rol t he SpaceWire int erface are split int o t wo groups. One group cont ains all regist ers commonly used by t he SpaceWire module (SpW_ModuleConfig, SpW_ModuleTimeCtrl, SpW_ModuleTimeCode, SpW_ModuleIntMask, SpW_ModuleIntStatus, SpW_ModuleIntClear). The ot her group cont ains all regist ers which are individual t o each SpaceWire channel (SpWn_StatusAndCtrl, SpWn_Tx_SAP, SpWn_Tx_EAP, SpWn_Tx_CAP, SpWn_Tx_Rx_Config, SpWn_Rx_SAP, SpWn_Rx_EAP, SpWn_Rx_CAP) and are available 4 t imes (n = 0..3). The SpaceWire module cont rol and st at us regist ers are accessible via t he SpaceWire-APB int erface.
AHB
APB
SpaceWire Module
SpW 10MHz Clk SpW MaxTx Clk
SpW-AHB-IF DMA processing
SpW- APB-IF to config
config
Tx
Rx
Channel 1
Channel 2
Channel 3
SpW
Fi gure 5-4: SpaceWi re Modul e
5.2.2 Data Transfer
Communication over SpaceWire is done by transferring data packets using DMA. To transmit data the CPU writ es t he relevant data into the memory and sets the registers in the SpaceWire interface (SpWn_Tx_SAP and SpWn_Tx_EAP) t hat points to this data. Further transfer activities are applied by the appropriated DMA without any CPU intervent ion. T o receive data the CPU sets the register in the SpaceWire interface (SpWn_Rx_SAP and SpWn_Rx_EAP) that points to t he receive area in the external memory. For each SpaceWire link 8 registers are provided. Four regist ers t o assign an
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area (transmit /receive) in t he ext ernal memory, t wo regist ers which carry t he current address value and t wo configurat ion regist ers. Transmit and receive registers of each of the four SPW links are programmable independently to use separate memory buffers, however all dat a st reams are sharing a common DMA and AHB int erface. When set t ing up a DMA channel, t he DMA point ers must be writ t en in t he order SpWn_R|Tx_SAP, t hen SpWn_R|Tx_EAP, because it is the write to the EAP register which will start the DMA transfer. Moreover, writ ing t o t he SAP or EAP register while a DMA transfer is in progress shall be avoided, as it will interrupt the ongoing t ransfer and most likely lead t o loss of dat a. By reading the current address register (SpWn_Tx_CAP, SpWn_Rx_CAP) the progress of data transfer can be observed.
The End Of Packet (EOP), or the occurrence of an error (Error EOP, EEP) on the SpaceWire link is indicat ed t hrough t he int errupt bit EOP_EEP (if enabled/unmasked). In addit ion, in case of EEP, EEP_Received will be set in SpWn_Tx_Rx_Config. The DMA transfer is stopped, and the number of received characters (bytes) will t hen be given by t he difference SpWn_Rx_CAP - SpWn_Rx_SAP.
When setting the NoStopOnEOP field in SpWn_Tx_Rx_Config, processing of EOP / EEP in t he RX dat ast ream is disabled. All incoming EOP and EEP are discarded, all received SPW packets are concat enat ed int o t he same DMA buffer until the buffer is full (CAP has reached EAP), which will be indicat ed by t he RxAreaFull int errupt bit . The maximum transmit (Tx) data rate is x MBit/s, where x is the used AGGA-4 SysClk in MHz. Lower Tx dat a rat es can be configured in the SpWn_StatusAndCtrl register. The Rx data rate is twice the SpWRxClk clock (see Tabl e 6-2).
5.2.3
SpW Interrupts
Various SPW events are notified by setting bits in t he SpW_ModuleIntStatus regist er. For each of t he event s, an int errupt to the processor can be raised if unmasked in the SpW_ModuleIntMask regist er. The int errupt bit s can be select ively cleared in t he SpW_ModuleIntClear regist er.
For each of t he four SPW links, t he following event s are report ed:
- SpaceWire link error (SPWn_LinkError) - SpaceWire link connected (SPWn_LinkConnected) - Packet transmission completed (SPWn_TxDone) - Receive DMA buffer (in external memory) full (SPWn_RxAreaFull) - Packet reception completed (EOP/EEP received) (SPWn)EOP_EEP)
Figure 5-5 shows t he SpaceWire int errupt cont roller.
Fi gure 5-5: SpW Interrupt C ontrol l er
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5.3 MIL-Bus
5.3.1 General description
The MIL-STD-1553B bus is a serial bus whose application is foreseen worldwide in many Space Applicat ions. It is a mult iplex data bus that operates asynchronously in a command/response mode. The transmission on the bus occurs in a half-duplex way. Every data transfer occurring on the bus is init ialized and managed by t he Bus Cont roller. More informat ion can be found in [RD-07]and [RD-08]. The data exchanges between the terminals connected to the bus involve 16 bits words. The data can be driven t hrough t he bus at a speed of 106 bit s/s. The IP1553 provides all facilit ies for efficient coupling bet ween t he Applicat ion and t he 1553B buses. The IP1553 has a dual bus capabilit y and operat es as a Remot e Terminal (RT). As a Remote Terminal, the IP1553 accepts all options and mode commands specified by the MIL-STD-1553B protocol. In addit ion, the transfer commands (including mode commands), may opt ionally be illegalized t hrough dedicat ed Charact erizat ion words. In t he Remote Terminal mode, the IP1553 offers a high level of aut onomy. 1553B t ransfers are cont rolled by t he IP1553 on a Sub Address based splitting scheme. The Application can allow multiple buffers which sizes are defined by Sub Address. The IP1553 provides a Control Word that ensures the completion and the validity of the message and an Informat ion Word giving dat ing and t he address where dat a were st ored.
The IP1553 is fully compatible with MIL-STD-1553B protocol. The next lines present the main feat ures provided by the IP1553:
· Full MIL-STD-1553B compliance · Remot e Terminal capabilit y · Dual redundant bus capabilit y · Fully compat ible wit h an AMBA bus int erface · Programmable non response t ime-out (14 µs or 31 µs) · Loop t est for t ransmission checking · Illegal commands management (in RT mode)
5.3.2 Architectural description
5.3.2.1 1553B bus coupling module architecture Figure 5-6 describes a typical IP1553 based on a 1553B bus coupling module. Very lit t le addit ional hardware is required t o ensure a full dual redundant 1553B bus coupling t o an Applicat ion.
1553B Bus
TRANSFORMER + TRANSCEIVER 0
IP1553
APPLICATION WITH
AHB & APB INTERFACES
01
TRANSFORMER + TRANSCEIVER 1
CLOCKS
Figure 5-6: IP1553 environment
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5.3.2.2 IP1553 internal architecture The internal architecture of IP1553 is shown on Figure 5-7. It is composed of t he five major following element s: Manchester Encoder/Decoder blocks, Internal regist ers, Commands management & Execut ing unit , Applicat ion Int erface block including an AMBA AHB int erface and an APB int erface.
5.3.2.2.1 Manchester Encoder/Decoder blocks The Encoder converts the parallel binary data to a serial Manchester encoded bit stream. The serial bit st ream is t hen driven t o t he act ive 1553B bus t ransmit t er. Two Encoders are included in t he IP1535 chip. The Decoder converts the 1553B serial Manchester data from one receiver t o parallel binary dat a. Thanks t o t wo independent Decoders t he IP1553 is able t o list en simult aneously on bot h buses.
5.3.2.2.2 Internal registers They cont ain necessary informat ion for IP1553 chip's configurat ion or operat ion.
5.3.2.2.3 Commands management & executing unit This block manages the 1553B protocol. Its function is defined by the Int ernal regist ers which cont rol t he way t he IP1553 init iat es responds t o commands in t he Remot e Terminal mode.
5.3.2.2.4 Application Interface block The Application Interface provides an APB interface for configuration and status registers. It provides also an AMBA AHB int erface for memory access.
DECODER 0 ENCODER 0
ENCODER 1 DECODER 1
INTERNAL REGISTERS
COMMANDS MANAGEMENT & EXECUTING UNIT
MEMORY BUS INTERFACE (AHB)
PROCESSOR BUS INTERFACE (APB)
Figure 5-7: IP1553 int ernal block diagram
5.3.3 IP1553 Initialization
The IP1553 act s as Remot e Terminal (RT). Aft er a AGGA4_RESET_N or PWR_ON_RESET_N activation, the IP1553 enters the init ializat ion sequence. Aft er a Rst 1553 bit act ivat ion, t he IP1553 ent ers t he reset sequence. In order to prevent any hazardous functioning of the chip, the following inputs or bits in registers must be stable out of t he "Reset state": Mode, TimeOut, DbcEn, BrCstEn, WdSize, LockEn, DW16En, ExtArea bit s. Any modificat ion on t hese bit s must be followed by t he act ivat ion of Rst1553 bit (C53CDST).
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Rst1553 = 1 RESET State
AGGA_RESET_N = 0 OR
POWER_ON_RESET_N = low
NO Rst1553 = 0 ? YES
Mode reading
INITIALIZATION State
AGGA_RESET_N = 1 ?
AND
NO
POWER_ON_RESET_N = high ?
YES
Mode = 00 or Mode = 11
REMOTE TERMINAL (RT) Mode
Figure 5-8: IP1553 init ializat ion and reset sequence
The Reset state corresponds to a reset of the IP1553 except its Bus Processor Interface in order to allow the Application t o writ e in it s Configurat ion regist er and it s Command regist er.
The Initialization state corresponds to a reset of the whole IP1553. Therefore, the IP1553 cannot be configured during Initialization state as its Bus Processor Interface is not active. The IP1553 leaves its Initializat ion st at e 5 µs after t he rising edge of t he AGGA4_RESET_N or PWR_ON_RESET_N input pin.
5.3.3.1 APB Interface
The det ailed regist er descript ion can be found in t he programming sect ion (chapt er 7.2.14)
The Applicat ion should configure t hese regist ers aft er t he Init ializat ion st at e ends.
When the Application set the Rst1553 bit to "0", the IP1553 leaves its reset stat e. The Applicat ion can t hen set t he GoStop bit t o "1". Upon AGGA4_RESET_N or PWR_ON_RESET_N input activation the IP1553 enters Initializat ion st at e and reset it s eight registers. Upon Rst1553 bit activation the IP1553 enters Reset state and reset the bits that are in read mode in t he C53CDST, C53RTI and t he C53TTI regist er.
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5.3.3.2 Remote Terminal (RT) mode definition
5.3.3.2.1 RT mode working scheme
The Remot e Terminal sequence is as shown on Figure 5-9. During "Initialization state" the IP1553 initializes its registers. During this period the IP1553 does not respond t o any request from the 1553B bus. The RstSt bit (C53CDST) is set to "1" by the IP1553 to indicate that it is in "Initializat ion st at e", ot herwise t his bit is set t o "0". The IP1553 enters its "St and-by state" after the end of the initialization. If GoStop bit (C53CDST) is set t o "1", t he IP1553 enters its "Active state". The BusyFlag bit (C53CDST) indicates when it is set t o "1" t hat t he IP1553 is in "Act ive st at e". Upon receipt of a valid command, the IP1553 performs an RT address parity cont rol. In case of mismat ch bet ween hard-wired parity and computed parit y, t he IP1553 does not process t he command and set t he ErrParAd bit in C53CDST and generat e C53Err int errupt t hrough act ivat ion of t he ErrRTAd bit in C53EIT. Upon receipt of "Reset remote terminal" Mode command, the IP1553 generates the C53Rst interrupt through activation of RstCom bit in C53RIT regist er and drives a 0 pulse on t he open-drain out put MIL_RESET_OUT_N.
REMOTE TERMINAL Mode
Initialization state Stand-by state
NO End of Reset ? YES
NO Gostop = 1 ?
YES
Active state
NO
Command
received ?
YES
RT address reading and Parity check
Parity OK? YES
Command management
NO Set C53Rst to "1"
"Reset remote terminal" Mode command received
Active state
ITs management
Figure 5-9: RT mode working scheme
5.3.3.2.2 RT mode internal registers definition
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In t he Remote Terminal mode, the following registers are used: the Status word register, the Last Command register and t he BIT regist er.
5.3.3.2.2.1 Status word register This regist er cont ains t he last St at us word sent in response t o Bus Cont roller int errogat ion. The St at us word regist er is as described hereaft er:
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
RTAD(4:0)
ME
NULL SREQ NULL NULL NULL BRX BUSY SSF
DBC
TF
Fi gure 5-10: Status word structure
RT AD(4:0)
Remot e Terminal address
ME Message Error
SREQ Service Request bit
BRX Broadcast Command received
BUSY
Busy bit
SSF
Subsyst em Flag bit
DBC
Dynamic Bus Cont rol accept ance
TF
Terminal Flag Bit = TTOFLG + MEMERR + BUSYAP
NULL Unused
During Transmit BIT word TF bit is forced t o "0". When TF bit is high, t he bit s B10 t o B1 are irrelevant .
The bit BUSY is always set to "0" as none busy case can occur in the IP1553. It is possible for t he Applicat ion t o updat e SSF and SREQ bit s of t he St at us word t hanks t o t he Charact erizat ion word cont ained in memory. The Application is also updated the DBC bit of the Status word t hanks t o t he DbcEn bit of t he Configurat ion regist er
(C53CF), see § 5.3.3.2.3.5 and § 5.3.3.2.4.2.
At init ializat ion, t he regist er is reset at 0000 (H) except Remot e Terminal address.
5.3.3.2.2.2 Command word register
This register contains the last valid received command word addressing the RT. At initialization, the register is reset at 0000 (H)
The Command word regist er is as described hereaft er:
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
RTAD(4:0)
T/R
SA(4:0)
WC(4:0)
RT AD( 4:0)
Figure 5-11: Command word st ruct ure Remot e Terminal address
T/R SA(4:0)
Transmit /Receive Sub-address/Mode
CWC(4:0)
Dat a word count /Mode code
5.3.3.2.2.3 Built-In-Test (BIT) word register This regist er informs t he Bus cont roller about possible 1553B t ransfer errors. The BIT word regist er is as described hereaft er:
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
NULL MEMERR TTO0 TTO1 TFINH NULL NULL NULL NULL HIWRD LOWRD UNDCMD T/R_ILL LP BUSYAP TTOFLG
Fi gure 5-12: BIT word structure MEMERR
Hresp input = Error
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T T O0
Transmission t ime-out act ivat ion on bus 0
T T O1
Transmission t ime-out act ivat ion on bus 1
T FI NH
Inhibit ion of Terminal Flag bit
HIWRDNumber of words received higher t han expect ed
LOWRD
Number of words received lower t han expect ed
UNDCMD
Undefined Command received
T /R_I LL
Bit T/R illegal in t he Mode command received
LP
Reserved
BUSYAP
Time-out access
T T OFLG
Transmission t ime-out act ivat ion on act ive bus
NULL Unused
At init ializat ion, t he regist er is reset at 0000 (H).
Not e:
- For t ransmission t ime-out descript ion refer t o § 5.3.3.2.7.2. - Undefined Command bit is always set to "0" as Undefined commands are treated as illegal commands (see
§ 5.3.3.2.4.1)
5.3.3.2.2.4 Internal registers management
The internal registers are updated for each valid command addressing the RT (except for some Mode commands) in the following way:
TYPE O F THE C O MMAND
C O MMAND Regi ster
Mode command: "Transmit Last Command"
Not modified
Mode command: "Transmit St at us word"
Updat ed
Mode command: "Transmit BIT word"
Updat ed
Ot her valid commands addressing t he RT
Updat ed
Invalid commands or commands addressing anot her RT
Not modified
STATUS Regi ster Not modified Not modified Updat ed Updat ed Not modified
BIT Re gi ste r Not modified Not modified Not modified
Updat ed Not modified
5.3.3.2.3 RT mode special functions
5.3.3.2.3.1 GoStop bit (C53CDST) The 1553 act ivit y can be cont rolled wit h t his bit : a low t o high t ransit ion or a high level allows t he 1553 t o st art/continue its Command processing, otherwise it stays/returns to "St and-by st at e" (aft er t he complet ion of t he current Command processing).
5.3.3.2.3.2 RstSt bit (C53CDST) This signal is set to "0" by the 1553 block when it is in "Initialization state", otherwise it is set t o " 1" during " Act ive st at e". So it follows t he act ivat ion of AGGA4_RESET_N input pin, 1553Rst bit or C53Rst int errupt .
5.3.3.2.3.3 BrCstEn bit (C53CF) It is possible t o cont rol t he aut horizat ion of Broadcast commands wit h BrCstEn bit . If BrCstEn = "1" then Broadcast commands is allowed, otherwise Broadcast commands is reject ed (is equivalent t o commands wit h a different RT address).
5.3.3.2.3.4 Memory access error
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When the IP1553 encounters a Memory access error, it sets MEMERR flag to "1" in t he BIT word if Hresp input = Error during the access, or set BUSYAP bit to "1" in t he BIT word if a Time-out has occurred during t he access.
If t he error occurs before transmission of the St atus word, the IP1553 sends its St atus word with ME bit set to "1" t hen st ops the Command processing. Otherwise, it completes the emission of t he current word t hen st ops t he Command processing. In all cases, t he IP1553 generat es t he C53Err int errupt .
5.3.3.2.3.5 SSF and SREQ bits
During t he Command processing, the IP1553 reads a Characterization word that contains informat ion about SSF and SREQ bit s. If these bits are set to "1" in the Characterization word, the IP1553 set s t hem t o "1" in t he St at us word, ot herwise t he IP1553 set s t hem t o "0".
5.3.3.2.3.6 RTAD(4:0) and RTParity The RTAD(4:0) define t he Remot e Terminal address according t o t he following t able:
Addre s s 0 1 ... 31
RTAD(4) 0 0
1
RTAD(3) 0 0
1
RTAD(2) 0 0
1
RTAD(1) 0 0
1
RTAD(0) 0 1
1
Not e: Address 31 is reserved for broadcast messages (refer t o AD1)
The RTParity allows t he detection of a possible address parity error. This input is wired in order to obtain an odd parit y on t he Remot e Terminal address as st at ed hereaft er:
RTPari ty = 1 RTAD(4) RTAD(3) RTAD(2) RTAD(1) RTAD(0) The RTParity input value is checked for each valid command received. If the value reflects a parity error, t he IP1553 does nottreat the command and sets ErrParAd bit to "1" in C53CDST and generate C53Err interrupt through activat ion of ErrRTAd bit in C53EIT.
5.3.3.2.4 Commands management
5.3.3.2.4.1 Commands legalization/illegalization
The IP1553 is able to legalize/illegalize any incoming command (including Mode commands, except " Transmit Last Command", "Transmit Status" and "Transmit BIT"), using Characterization words included into the Charact erizat ion area of the memory. One Characterization word is linked to each command (the format is as defined § 5.3.3.2.8.4). The IP1553 accesses to the Characterization memory at the beginning of each command processing to check the legality of t he command (except for "Transmit Last Command", "Transmit St atus" and "Transmit BIT" Mode commands which are always legal). To declare legal an incoming command t he following condit ion is fulfilled:
- LEG bit of the Characterization word is set to "1"
For any illegal command t he IP1553 sends back it s St at us word wit h ME bit set t o "1". All unused commands are illegalized in t he Charact erizat ion memory.
5.3.3.2.4.2 Mode commands management
The IP1553 behaviour is as described hereaft er for t he following Mode commands:
· Dynamic bus control: The IP1553 is able t o accept or not t he cont rol of t he 1553B bus. Applicat ion aut horizes it s accept ance by set t ing t o "1" a dedicat ed bit DbcEn (C53CF). Upon receipt of this command, if legalized and if DbcEn bit is high level, the IP1553 sends it s St at us word wit h DBC bit set t o "1" and generat e t he C53It int errupt t hrough t he act ivat ion of t he It Dbc bit (C53NIT).
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Ot herwise it sends only its Status word with DBC bit set to "0" and also ME bit set to "1" if the command is illegalized. The RT to BC mode switching will be effective only after modification of Mode bits (C53CF) and AGGA4_RESET_N, PWR_ON_RESET_N or Rst 1553 act ivat ion.
· Synchronize without data word:
Upon receipt of this command, if legalized, the IP1553 generates the interrupt C53It through the activation of the ItSync bit (C53NIT) and send it s St at us word. Ot herwise it sends only it s St at us word wit h ME bit set t o "1".
· Synchronize with data word: Upon receipt of this command, if legalized, the IP1553 stores the "Synchronization word" into the Buffer associated t o Receive Mode commands, generate the interrupt C53It through the activation of the ItSync bit (C53NIT) and send it s St at us word. Ot herwise it sends only it s St at us word wit h ME bit set t o "1".
· Transmit status word:
Upon receipt of t his command, if legalized, t he IP1553 sends t he cont ent of t he "St at us word" regist er.
· Initiate self test: Upon receipt of this command, if legalized, the IP1553 sends its Status word. Otherwise it sends only it s St at us word wit h ME bit set t o "1".
· Transmit BIT word: Upon receipt of this command, if legalized, the IP1553 sends its Status word followed by the content of the "BIT word" regist er. Ot herwise it sends only it s St at us word wit h ME bit set t o "1".
· Transmitter shutdown: Upon receipt of this command, if legalized, the IP1553 inhibits the opposite bus t ransceiver by forcing to high level t he corresponding pins (MIL_TX0, MIL_TX0B, MIL_TX0INH or MIL_TX1, MIL_TX1B, MIL_TX1INH). Otherwise it sends only it s St at us word wit h ME bit set t o "1".
· Override transmitter shutdown: Upon receipt of this command, if legalized, the IP1553 cancels the inhibition of the opposite bus transceiver. Otherwise it sends only it s St at us word wit h ME bit set t o "1".
· Inhibit terminal flag: Upon receipt of this command, if legalized, the IP1553 forces to "0" the TF bit of the St at us word and send it s St at us word. Ot herwise it sends only it s St at us word wit h ME bit set t o "1".
· Override inhibit terminal flag: Upon receipt of this command, if legalized, the IP1553 cancels the inhibition of the TF bit of t he St at us word send it s St at us word. Ot herwise it sends only it s St at us word wit h ME bit set t o "1".
· Reset remote terminal:
Upon receipt of this command, if legalized, t he IP1553 sends it s St at us word and generat e t he C53Rst int errupt (C53RIT) and drives a 0 pulse on the open-drain output MIL_RESET_OUT_N. Otherwise it sends only it s St at us word wit h ME bit set t o "1". The Reset state corresponds to a reset of the IP1553 except its Bus Processor Int erface (APB) in order t o allow t he Application to write in its Configuration register and its Command register. In this state, it resets the bits that are in read mode in t he C53CDST, C53RTI and C53TTI regist ers.
· Transmit vector word: Upon receipt of this command, if legalized, the IP1553 sends its Status word, read t he Vect or word from t he Buffer associated to Transmit Mode commands send it . Ot herwise it sends only it s St at us word wit h ME bit set t o " 1". · Transmit last command word: Upon receipt of this command, the IP1553 sends its Status word followed by the content of "Command word" regist er. · Selected transmitter shutdown:
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Upon receipt of this command, if legalized, the IP1553 stores the "data word" int o t he Buffer associat ed t o Receive Mode commands and send it s St at us word. Ot herwise it sends only it s St at us word wit h ME bit set t o "1".
· Override selected transmitter shutdown: Upon receipt of this command, if legalized, the IP1553 stores the "data word" int o t he Buffer associat ed t o Receive Mode commands and send it s St at us word. Ot herwise it sends only it s St at us word wit h ME bit set t o "1".
· Reserved Mode commands: These Mode commands should be illegalized into the Characterization words. Then upon receipt of t hese commands, t he IP1553 would only send it s St at us word wit h ME bit set t o "1". The mode codes available are t aken from t he following t able:
Transmit - Mode Funct ion receive bit code
Associat ed Broadcast dat a word command
allowed
Command im plem ent ed
1
00000 Dynamic Bus Cont rol
No
No
Yes
1
00001 Synchronize
No
Yes
Yes
1
00010 Transmit St at us Word
1
00011 Init iat e self-t est
No
No
No
Yes
Yes No(1)
1
00100 Transmit t er shut down
No
Yes
Yes
1
00101 Override t ransmit t er shut down
No
Yes
Yes
1
00110 Inhibit t erminal flag bit
No
Yes
Yes
1
00111 Override inhibit t erminal flag bit
No
Yes
Yes
1
01000 Reset remot e t erminal
No
Yes
Yes
1
01001 Reserved
No
No
No
1
01111 Reserved
No
No
No
1
10000 Transmit vect or word
Yes
No
Yes
0
10001 Synchronize
Yes
Yes
Yes
1
10010 Transmit last command
Yes
No
Yes
1
10011 Transmit bit word
Yes
No
Yes
0
10100 Select ed t ransmit t er shut down
Yes
Yes
Yes
0
10101 Override selected t ransmit t er shut down Yes
Yes
Yes
1 or 0 10110 Reserved
Yes
No
No
1 or 0 11111 Reserved
Yes
No
No
(1) The response for this command depends only on the legalization bit in the Characterization word. There is no special t reat ment associat ed wit h t his command.
5.3.3.2.5 No response time-out management
The IP1553 is able to handle programmable no response time-out. The time-out value is taken into account t o det ect a no-response from a Remote Terminal in a RT to RT transfer. The TimeOut bit (C53CF) determines the chosen value for no response time-out. The smallest value is 14 µs (TimeOut = "0"), and the highest value is 31 µs (TimeOut = " 1").
5.3.3.2.6 Redundancy management The IP1553 is fully compliant t o § 4.6 of document AD1.
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The IP1553 is able to detect any incoming command on either the nominal or the redundant bus and respond on the bus it has been act ivat ed by. The content of the internal registers (St atus word register, Last Command register and BIT register) always corresponds t o a t ransfer performed on t he act ive bus. If a t ransfer is interrupted on a 1553B bus by a valid command incoming on the other bus and addressing t he RT, t he IP1553 st ops t he processing of t he previous command and st art t he processing of t he new command.
5.3.3.2.7 Test support & Error report
5.3.3.2.7.1 Built-In-Test (BIT) word This 16 bit word provides error informat ion for each 1553B t ransfer. The BIT word corresponds t o t he bit descript ion given in § 5.3.3.2.2.3.
5.3.3.2.7.2 Transmission time-out The IP1553 contains a time-out to preclude a signal transmission of greater than 800 µs. If this time-out t riggers, t hen TTO0 or TTO1 and TTOFLG is set t o "1" in t he BIT word (see § 5.3.3.2.2.3). This funct ion does not preclude a correct t ransmission in response t o a command. Reset of this time-out function is performed by the reception of a valid command addressing t he RT on t he bus on which t he t ime-out has occurred.
5.3.3.2.7.3 "Loop Test" and "Self test" The 1553 funct ion in AGGA4 neit her implement s a "Self Test " nor a "Loop Test ".
5.3.3.2.8 Memory management The dat a management funct ion ensures t he following point s:
- The t ransfer of received dat a from t he 1553B bus t o t he memory,
- The availabilit y of t hese dat a for t he Applicat ion,
- The t ransfer of dat a t o t ransmit on t he 1553B bus from t he memory. The IP1553 realizes the memory management and communicate with the memory controller. It uses a shared area in memory. This area is defined by the Application thanks to MemArea bits (C53CF). MemArea defines an area for t he IP1553 of 128Kwords. This area can be placed in memory at each multiple of 128K word address in the whole memory, i.e. when MemArea is increased by 1 t he IP1553 area will be moved of 128 K word address. There are t hree different areas in t his shared memory:
- A command area which size is 4 Kwords including the received command words, cont rol words associat ed t o t hese commands, associated data to Mode commands, characterization words and two double indirect ion t ables of 32 addresses;
- A dat a received area which size is 32 Kwords including dat a words received on 1553B bus;
- A dat a t o t ransmit area which size is 32 Kwords including dat a words t o t ransmit on 1553B bus.
The 1553B and Identification words are stored in memory. The bits WdSize and DW16En (C53CF) det ermine if t he IP1553 st ores t he words in 32 bit words or 16 bit words. Wdsize= 1 is only possible if DW16En is set t o 1.
16 MSB 1st 1553B word
16 LSB unused
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16 MSB 1st Ident ificat ion word
16 LSB
2nd 1553B word
2nd ident ificat ion word
1553B and Ident ificat ion words mapping wit h 16 bit Word mode
16 MSB 1st 1553B word
16 LSB 1st Ident ificat ion word
2nd 1553B word
2nd Ident ificat ion word
1553B and Ident ificat ion words mapping wit h 32 bit Word mode
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5.3.3.2.8.1 Command area There are t he following part s in t he command area (Figure 5-16):
· A circular buffer, which contains the received command words on the 1553B bus. When a command is received and legalized, the IP1553 writes in this buffer at the end of the exchange the command word received, a cont rol word giving information about the exchange and a 32 bit word containing a 21 bit dat ing field and t he block number where t he dat a of t he command have been st ored.
This buffer is in write access mode by the IP1553 and in read access mode by the Application, the LastCmdAd bit s in t he C53CDST gives t he address in t he command area of t he last command t reat ed.
At t he end of t he buffer, t he access point er t akes t he beginning address of t he area.
· Two 32 word t ables including t he dat a associat ed t o each Mode Command.
The first table contains the data associated to receive Mode command. It is in write access mode by the IP1553 and in read access mode by t he Applicat ion. The Mode Code of t he command gives t he address in t he t able.
The second table contains the data associated to transmit Mode command. It is in read access mode by t he IP1553 and in write access mode by the Application. The Mode Code of t he command gives t he address in t he t able.
· A 32 word t able including characterisation words. Each word contains informat ion about t he legalizat ion of t he command (LEG bit), the enable of the ItTrok bit in the C53NIT (TROK bit) and the St atus response thanks t o SSFB and SREQ bit s. The Applicat ion init ializes t his t able in order t o allow t he IP1553 t o use it .
When the IP1553 receives a command, it accesses to this table to read the characterization word associat ed t o t he command word received. The Sub Address or t he Mode Code gives t he address in t he t able.
· A double 32 word table giving the beginning block number for receive dat a, t he maximum size of t he buffer in blocks and the next block to be used by the IP1553 in t he dat a area for each 32 Sub Address. The Applicat ion init ializes t his t able in order t o allow t he IP1553 t o use it .
The table word is as described Figure 5-13 (detailed description § 5.3.3.2.8.4):
B31 B30.............................B21 B20.............................B11 B10...............................................B0
ADUPD
Current block
Maximum buffer size
Beginning buffer reception block
Figure 5-13: Indirect ion t able word for recept ion
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When a Receive Command is received, the IP1553 reads the Indirection table word at the address given by t he Sub Address. Then the IP1553 writes the received data in the data area starting at the Beginning buffer recept ion block (BRBlk) + Current block value (CurBlk). The value of the CurBlk field is zero at the beginning. The size of a block is 16 (32 bit words) when 32 bit Word mode is activated, otherwise the size is 32 (32 bit words, but only MSB are used). Once this task is finished, t he IP1553 compares t he Maximum buffer size (MaxBS) wit h (CurBlk+1):
- If t he buffer is not full (CurBlk + 1 < MaxBS), the IP1553 updat es t he CurBlk if t he bit Address Updat e (ADUPD) is set to "1" by writing CurBlk+1. If the ADUPD bit is not set , t he CurBlk does not be updated and the next data received at this same Sub Address is written at the CurBlk + BRBlk. Meanwhile, t he BRBlk may have been modified by t he Applicat ion.
- If t he buffer is full (CurBlk + 1 = MaxBS), the IP1553 changes its internal table indicator for this Sub Address in order to point on the complementary table at the time of the next Receive command at this Sub Address. The IP1553 updates the CurBlk field with zero and generate the C53It interrupt through t he ItSwitch bit (C53NIT) act ivat ion.
The IP1553 maintains a table, which contains the table indicator for each Sub Address. This indicator is report ed in t he Cont rol Word associat ed t o t he received command.
At init ializat ion, t he IP1553 uses t he t able 0, which st art s at "MemArea+10F80H" and ends at " MemArea+10F9FH". When the buffer available will be full and if the ADUPD bit is set to "1", the IP1553 uses the t able 1 which starts at "MemArea+10FA0H" and ends at "MemArea+10FBFH" for the Sub Address considered. It warns t he Application thanks to C53It. When the buffer defined by the table 1 will have be full and if t he ADUPD bit is set t o "1", t he IP1553 uses t he t able 0 again, and so on...
· A double 32 word table giving the beginning block number for transmit data, the maximum size of t he buffer in blocks and the next block to be used by the IP1553 in t he dat a area for each 32 Sub Address. The Applicat ion init ializes t his t able in order t o allow t he IP1553 t o use it
The table word is as described in Figure 5-14 (detailed description § 5.3.3.2.8.4)
B31 B30.............................B21 B20.............................B11 B10...............................................B0
ADUPD
Current block
Maximum buffer size Beginning buffer transmission block
Figure 5-14: Indirect ion t able word for t ransmission
When a Transmit Command is received, the IP1553 reads the Indirection table word at the address given by the Sub Address. Then the IP1553 reads the data to transmit in the data area starting at the Beginning buffer t ransmission block (BTBlk) + Current block value (CurBlk). The value of the CurBlk field is zero at the beginning. The size of a block is 16 (32 bit words) when 32 bit Word mode is activated, otherwise the size is 32 (32 bit words, but only MSB are used). Once this task is finished, the IP1553 compares the Maximum buffer size (MaxBS) wit h (CurBlk+1):
- If t he buffer is not entirely read (CurBlk + 1 < MaxBS), the IP1553 updat es t he CurBlk if t he bit Address Updat e (ADUPD) is set to "1" by writ ing CurBlk+1. If t he ADUPD bit is not set , t he CurBlk is not updated and the next data to transmit from this same Sub Address is read at the CurBlk + BTBlk. Meanwhile, t he BTBlk may have been modified by t he Applicat ion.
- If t he buffer is entirely read (CurBlk +1 = MaxBS), the IP1553 changes its internal table indicator for t his Sub Address in order to point on the complementary t able at t he t ime of t he next Transmit
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command at this Sub Address. The IP1553 updates the CurBlk field with zero and generate the C53It int errupt t hrough t he ItSwitch bit (C53NIT) act ivat ion.
The IP1553 maintains a table, which contains the table indicator for each Sub Address. This indicator is report ed in t he Cont rol Word associat ed t o t he received command.
At init ializat ion, t he IP1553 uses t he t able 0, which st art s at "MemArea+10FC0H" and ends at "MemArea+10FDFH". When the buffer available has been entirely read and if t he ADUPD bit is set t o "1", t he IP1553 uses the table 1 which starts at "MemArea+10FE0H" and ends at "MemArea+10FFFH" for the Sub Address considered. It warns the Application thanks to C53It. When the buffer defined by the table 1 has been ent irely read and if t he ADUPD bit is set t o "1", t he IP1553 uses t he t able 0 again, and so on...
MemArea + 00000 BegAd SA1
EndAd SA1 BegAd SA2 EndAd SA2
Receive buffer area SA1 Receive buffer area SA2
Receive buffer area SA1 Receive buffer area SA2
BegAd SA30 EndAd SA30
Receive buffer area SA30
Receive buffer area SA30
Receive Command Data area
07FFF 08000 BegAd SA1 EndAd SA1 BegAd SA2
EndAd SA2
Transmit buffer area SA1 Transmit buffer area SA2
Transmit buffer area SA1 Transmit buffer area SA2
BegAd SA30 EndAd SA30
Transmit buffer area SA30
Transmit buffer area SA30
Transmit Command Data area
0FFFF
16 MSB bits
16 LSB bits
Figure 5-15: Dat a area mapping in RT mode
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Not e: The addresses in Figure 5-15 are address words.
MemArea + 10000 10001
First Command word
First Control word
First Information word
Last Command word
Last Control word
Last Information word
Command area
10F00
Receive Mode Command 0
10F1F 10F20
10F3F 10F40
Receive Mode Command 31 Characterisation: Mode Code 0
Characterisation: Mode Code or SA
Characterisation: Mode Code 31 Transmit Mode Command 0
10F5F Transmit Mode Command 31
Unused
10F80 10F81
10F9E 10F9F 10FA0 10FA1
10FBE 10FBF 10FC0 10FC1
10FDE 10FDF 10FE0 10FE1
10FFE 10FFF
1FFFF
Unused
Address Receive Table 0 SA1
Address Receive Table 0 SA30
Unused
Unused
Address Receive Table 1 SA1
Address Receive Table 1 SA30
Unused
Unused
Address Transmit Table 0 SA1
Address Transmit Table 0 SA30
Unused
Unused
Address Transmit Table 1 SA1
Address Transmit Table 1 SA30
Unused
Unused
Data associated to receive Mode Command area
Characterization area
Data associated to transmit Mode Command area
Address table for Receive Command
area 0
Address table for Receive Command
area 1
Address table for Transmit Command
area 0
Address table for Transmit Command
area 1
16 MSB bits
16 LSB bits
Figure 5-16: Command area mapping in RT mode Not e: The addresses in Figure 5-16 are address words.
5.3.3.2.8.2 Data reception area
The data reception area contains the data received on the 1553B bus. This area starts at "MemArea+00000H" and ends at "MemArea+08000H", that is to say 32 Kwords. It is virtually divided in 30 sub areas corresponding t o t he 30 Sub Address. Each sub area is identified by its BRBlk and MaxBS, writt en in t he Indirect ion t able word at t he address related to the Sub Address of the received command. Each sub area cont ains whet her one or several 16 word wide buffers if the 32 bit Word mode is activated, else one or several 32 word wide buffers to memorize t he received dat a. The Figure 5-17 & Figure 5-18 show how t he dat a are mapped:
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BRBlk+CurBlk & 0 BRBlk+CurBlk & 1
16 Most Significant Bits 1st 1553 Data received 3rd 1553 Data received
16 Least Significant Bits 2nd 1553 Data received 4th 1553 Data received
BRBlk+CurBlk & E BRBlk+CurBlk & F
29th 1553 Data received 31th 1553 Data received
30th 1553 Data received 32nd 1553 Data received
Figure 5-17: Dat a recept ion buffer mapping when 32 bit Word mode
BRBlk+CurBlk & 00 BRBlk+CurBlk & 01
BRBlk+CurBlk & 1E BRBlk+CurBlk & 1F
16 Most Significant Bits 1st 1553 Data received 2nd 1553 Data received
31th 1553 Data received 32nd 1553 Data received
16 Least Significant Bits Unused
Figure 5-18: Dat a recept ion buffer mapping when 16 bit Word mode
5.3.3.2.8.3 Data transmission area
The data transmission area contains the data to transmit on the 1553B bus. This area starts at "MemArea+08000H" and ends at "MemArea+0FFFFH", that is to say 32 Kwords. It is virtually divided in 30 sub areas corresponding t o t he 30 Sub Address. Each sub area is identified by its BTBlk and CurBlk, written in the Indirection table word at t he address related to the Sub Address of the received command. Each sub area cont ains whet her one or several 16 word wide buffers if the 32 bit Word mode is activated, else one or several 32 word wide buffers to memorize the data to transmit . The Figure 5-19 and Figure 5-20 show how t he dat a are mapped:
BTBlk+CurBlk & 0 BTBlk+CurBlk & 1
16 Most Significant Bits 1st 1553 Data to transmit 3rd 1553 Data to transmit
16 Least Significant Bits 2nd 1553 Data to transmit 4th 1553 Data to transmit
BTBlk+CurBlk & E 29th 1553 Data to transmit BTBlk+CurBlk & F 31th 1553 Data to transmit
30th 1553 Data to transmit 32nd 1553 Data to transmit
Figure 5-19: Dat a t ransmission buffer mapping when 32 bit Word mode
BTBlk+CurBlk & 00 BTBlk+CurBlk & 01
16 Most Significant Bits 1st 1553 Data to transmit 2nd 1553 Data to transmit
BTBlk+CurBlk & 1E 31th 1553 Data to transmit BTBlk+CurBlk & 1F 32nd 1553 Data to transmit
16 Least Significant Bits Unused
Figure 5-20: Dat a t ransmission buffer mapping when 16 bit Word mode
5.3.3.2.8.4 Memory words structure There are 6 different words used by the IP1553 in the memory. The data words, the command words, the Control Word, t he Charact erizat ion Word, t he Indirect ion Word and t he Informat ion Word are described hereaft er:
· Control Word:
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
DV
T
RT-RT BUSID NULL MEMERR TTO0 TTO1 TFINH HIWRD LOWRD UNDCMD T/R_ILL LP
DV T RT - RT BUSID MEMERR T T O0 T T O1
Fi gure 5-21: C ontrol Word structure Dat a Valid Indirect ion t able number used for t he command t reat ment RT-RT command received (when IP1553 is t he receiving RT) Command received on t he nominal ("0") or redundant ("1") bus HResp input = Error for memory access Transmission t ime-out act ivat ion on bus 0 Transmission t ime-out act ivat ion on bus 1
B1
B0
BUSYAP TTOFLG
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T FI NH
Inhibit ion of Terminal Flag bit
HIWRDNumber of words received higher t han expect ed
LOWRD
Number of words received lower t han expect ed
UNDCMD Undefined Command received
T /R_I LL
Bit T/R illegal in t he Mode command received
LP
Reserved
BUSYAP
Applicat ion Int erface is busy (Time-out error for memory access)
TTOFLGTransmission t ime-out act ivat ion on act ive bus
NULL
Unused ("0")
During a nominal exchange bits B11 to B0 is set t o "0". For "Transmit Last Command", "Transmit St at us" and "Transmit BIT", t he cont rol word writ t en represent s t he st at e of t he previous command.
· Characterization word:
Nominal Command Area
Mode Command Area
B31
B30
TROK LEG
B29
B28
B27
B26
SSF SREQ TROK LEG
B25
B24
B23
B22
SSF SREQ TROK LEG
B21
B20
B19
B18
SSF SREQ TROK LEG
B17
B16
SSF SREQ
Transmit
Receive
Transmit
Figure 5-22: Charact erizat ion word st ruct ure
Receive
T ROK
Enable of t he It Trok bit (C53NIT)
LEG
Legalizat ion bit : "0" Illegal / "1" Legal
SSF
Sub Syst em Flag bit
SREQ
Service Request bit
For t he Sub Address 31 and 32 ("00000b"), the bits B31 to B24 are irrelevant, as the command is a Mode command.
· Information words:
These words are written by the IP1553 after the command and control word in the command area for each valid and legal command t reat ed.
When 32 bi t Word mode, t he fields in t he indirect ion t able are defined hereaft er:
B31 B30.............................B21 B20.............................B11 B10...............................................B0
ADUPD
Current block
Maximum buffer size Beginning buffer transmission block
B31 B30.............................B21 B20.............................B11 B10...............................................B0
ADUPD
Current block
Maximum buffer size
Beginning buffer reception block
Figure 5-23: Indirect ion t able word for recept ion when 32 bit Word mode
Beginning buffer transmission or reception block field is 11 bits wide. We can access every block of 16 words of 32 bits (a full 1553 dat a buffer) in t he dat a recept ion or t ransmit area, which size is 32 Kwords.
Maximum buffer size field is 10 bit s wide. We cannot allocat e more t han 16 Kwords t o a single Sub Address.
(Maximum buffer size value + Beginning buffer block value) must be lower than 7FFH, which is the address of the last block in t he t ransmission or recept ion area.
B31.............................B21 B20...............................................B0
Data block number
Dating
Figure 5-24: Informat ion word st ruct ure when 32 bit Word mode
The Data block number field is 11 bits wide. Its value corresponds to the sum of Beginning buffer block and Current block. In case of Mode Command, Extended Memory mode or 1553 exchange error (Data Valid bit = "0") this field has no significance and corresponds to the value of the last valid and legal command, which is not a Mode command. The Dat a block number for t he first block of t he memory is zero.
The Dat ing field is always zero.
When 16 bi t Word mode, t he fields in t he indirect ion t able are defined hereaft er:
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B31 B30.............................B21 B20.............................B11 B10...............................................B0
ADUPD
Current block
Maximum buffer size Beginning buffer transmission block
B31 B30.............................B21 B20.............................B11 B10...............................................B0
ADUPD
Current block
Maximum buffer size
Beginning buffer reception block
Figure 5-25: Indirect ion t able word for recept ion when 16 bit Word mode
Beginning buffer transmission or reception block field is 11 bits wide. But only the 10 LSB is used by the IP1553. We can access every block of 32 words of 16 most significant bits of the 32 bit words (a full 1553 data buffer) in t he dat a recept ion or t ransmit area, which size is 32 Kwords.
Maximum buffer size field is 10 bit s wide. We can allocat e up t o 32 Kwords t o a single Sub Address.
(Maximum buffer size value + Beginning buffer block value) must be lower than 3FFH, which is the address of the last block in t he t ransmission or recept ion area.
B31 B30.........................B21 B20.........................................B0
0 Data block number
Dating
Figure 5-26: Informat ion word st ruct ure when 16 bit Word mode
The Data block number field is 10 bits wide. Its value corresponds to the sum of Beginning buffer block and Current block. In case of Mode Command, Extended Memory mode or 1553 exchange error (Data Valid bit = "0") this field has no significance and corresponds to the value of the last valid and legal command, which is not a Mode command. The Dat a block number for t he first block of t he memory is zero.
The Dat ing field is always zero.
5.3.3.2.8.5 Extended Area access to the memory
The IP1553 provides 5 bits (ExtSubAd bits in C53CF) which are written by the Application to define a Sub Address t o be used wit h t he Extended Area mode. This mode is activated thanks to the ExtArea bit (C53CF). If this bit is set to "0", t he Ext Subad is t reat ed as t he ot hers.
The Extended Area mode allows the IP1553 to access the whole memory in write or read mode. The beginning address of t hese accesses is provided by the Extended Memory Base Address register (C53EMBA). The IP1553 is t hen able t o access memory areas outside of the 128 Kwords normally provided thanks to MemArea bits (C53CF). In t his peculiar case, there is not an end area address: the C53EMBA is incremented for each double 1553 word read or writ e in t he memory, when the Sub Address defined is used and the Extended Area mode allowed. The words count associat ed t o each 1553 command for t his Sub Address is even.
The C53EMBA is programmable by t he 1553B bus t hanks t o a Receive command wit h only t wo words sent t o (Ext SubAd + 1). The 10 LSB of the first 1553 data is stored in the bits 25 to 16 of the C53EMBA(25 downt o 0). The second dat a word is st ored in t he 16 LSB bit s of t his regist er.
5.3.3.3 IP1553 System interface
5.3.3.3.1 Transceivers interface
The IP1553 is able t o support a redundant 1553B bus. Each connect ion t o a 1553B bus is done t hrough a Transceiver and a Transformer as shown in Figure 5-27. Each Transceiver IP1553 interface is composed of at least 5 signals: RX & RXB input signals for Receiver sect ion, TX & TXB & TXINH output signals for Transmitter section. The waveform of t hese signals is in accordance wit h Figure 5-28 & Figure 5-29.
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Bus 0 Transformer 0
Bus 1 Transformer 1
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Transceiver 0
Receive section
Filter
RX0 RX0B
Decoder 0
Transmit section
Inhibit
TX0 TX0B TX0INH
Transceiver 1
Receive section
Filter
RX1 RX1B
Encoder 0
IP1553
Decoder 1
Transmit section
Inhibit
TX1 TX1B TX1INH
Encoder 1
1553B Bus output
Encoder output:
TX
TXB
TXINH
Figure 5-27: Transceiver int erface Figure 5-28: Transmit t er signals waveform
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1553B Bus input
Decoder input:
RX
RXB
Figure 5-29: Receiver signals waveform
As shown on Figure 5-29, the expected idle level for RX and RXB signals is logic "1". This means that t he IP core is compat ible wit h t he Smit hs t ype t ransceiver.
5.3.3.3.2 IP1553 Interrupts support The IP1553 is able to inform the Application about special events, which are likely to happen. When these events occur, an out put interrupt is generated. There are 3 different interrupts: a nominal, a reset and an error int errupt , which t he causes are somet imes mult iple. They are described hereaft er: · C 53It: Nominal interrupt. It is generated thanks to the following bits activation: ItTrok, ItSync, ItDbc and ItSwitch.
To generate the interrupt, the IP1553 combines these sources wit h a logical OR. These bit s are in t he Nominal Int errupt regist er (C53NIT).
- ItTrok: Maskable bit (ItTrokMask in C53CF). In RT mode, this bit is set t o "1" at t he end of each valid exchange. It is reset t o "0" upon C53NIT read access.
- ItSync: Maskable bit (ItSyncMask in C53CF). In RT mode, this bit is set to "1" after " Synchronize" Mode command reception if this command is legalized. In BC mode, this bit is set t o " 1" aft er t he execut ion of an Instruction block with SYNC bit set in the first Instruction word. In BM mode, t his bit is set to "1" when the IP1553 toggles from one buffer to the other. It is reset to "0" upon C53NIT read access.
- ItDbc: Non maskable bit. In RT mode, this bit is set t o "1" aft er "Dynamic bus cont rol" Mode command reception if t his command is legalized. It is reset t o "0" upon C53NIT read access.
- ItSwitch: Non maskable bit. In RT mode, this bit is set to "1" after change of data address table for a sub-address. It is reset t o "0" upon C53NIT read access.
· C 53Rst: Reset interrupt. In RT mode, it is generated after "Reset remote terminal" Mode command reception if this command is legalized. The bit RstCom is reset t o "0" upon C53RIT read access.
· C 53Err: Error interrupt. It is generated thanks to the following bits activation: ErrMem, Err1553, ErrInst and CwError. To generate the interrupt, the IP1553 combines these sources with a logical OR. These bits are in the Error Int errupt register (C53EIT).
- ErrMem: Non maskable bit. In all modes, this bit is set to "1" in case of Memory access error: t imeout access or Hresp input = Error. It is reset t o "0" upon C53EIT read access.
- Err1553: Maskable bit (Err1553Mask in C53CF). In RT mode, this bit is set to "1" in case of 1553 error. In BC mode, this bit is set to "1" if EXCERR flag is set in the Control word wit hout additional ret ry allowed. It is reset t o "0" upon C53EIT read access.
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- CwError: Non maskable bit. In BC mode, this bit is set to "1" when t he bit CWERR is set in t he cont rol word writ t en in memory.
- ErrInst: Non maskable bit. In BC mode, this bit is set to "1" in case of Illegal Instruction detection by t he BC. It is reset t o "0" upon C53EIT read access.
- ErrRTAd: Non maskable bit. In all modes, this bit is set to "1" in case of RTAD parit y error. It is reset t o "0" upon C53EIT read access.
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5.4 DSU Communication Link
DSU communicat es eit her wit h SpaceWire or wit h an UART. Select ion is made by t he DSU_SPW_EN pin. · DSU_SPW_EN = low DSU via UART · DSU_SPW_EN = high DSU via SpaceWire
5.4.1 DSU UART Operation
The DSU communication link consists of a UART connected t o t he AHB bus as a mast er (Figure 5-30). A simple communication protocol is supported to transmit access parameters and data. A link command consist s of a cont rol byt e, followed by a 32-bit address, followed by optional write data. If the LR bit in the DSU cont rol regist er is set , a response byte will be sent after each AHB transfer. If the LR bit is not set, a write access does not return any response, while a read access only returns the read dat a. Dat a is sent on 8-bit basis as shown in Figure 5-32. Through t he communicat ion link, a read or writ e t ransfer can be generat ed t o any address on t he AHB bus.
Fi gure 5-30 DSU communi cati on l i nk bl ock di agram Fi gure 5-31 DSU UART Fram e
Fi gure 5-32 DSU C ommuni cati on l i nk commands Note: For DSU Writ e operat ion t he maximum word lengt h is 64!
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Note: Response Byt e is enabled t hrough DSU_Ctrl regist er
A response byte can optionally be sent when the processor goes from execution mode to debug mode. Block t ransfers can be performed be setting the length field t o n-1, where n denot es t he number of t ransferred words. For writ e accesses, the control byte and address is sent once, followed by the number of data words to be written. The address is aut omatically incremented after each data word. For read accesses, the control byt e and address is sent once and t he corresponding number of dat a words is ret urned. Det ails about t he DSU_UART_Status regist er can be found in sect ion 7.2.7.1.
5.4.2 DSU UART Baud rate generation (not available in DSU SpaceWire operation)
The UART contains a 14-bit down-counting scaler to generat e t he desired baud-rat e. The scaler is clocked by t he SysClk and generates a UART tick each time it underflows. It can be programmed via the register DSU_UART_Scaler. The scaler is reloaded with the value of the UART scaler reload register after each underflow. The resulting UART tick frequency should be 8 times the desired baud-rate. If not programmed by software, the baud rate will be aut omat ically discovered. This is done by searching for t he short est period bet ween t wo falling edges of t he received dat a (corresponding to two bit periods). When three identical two-bit periods have been found, t he corresponding scaler reload value is latched into the reload register, and the BL bit is set in t he UART cont rol regist er. If t he BL bit in DSU_UART_SpW_Ctrl register is reset by soft ware, t he baud rat e discovery process is rest art ed. The baud-rat e discovery is also restarted when a `break' is received by the receiver, allowing to change the baud rate from the external t ransmitter. For proper baud rate detection, the value 0x55 should be transmitted t o t he receiver aft er reset or aft er sending break. Please note that it is not recommended to change the scaler setting while the DSU UART link is connect ed. This will likely cause restart of the link, baud rate discovery leading again to the old baud rate. The DSU UART baud rate should be changed in t he ext ernal UART device before connect ing it t o AGGA-4.
The best scaler value for manually programming t he baud rat e can be calculat ed as follows:
Scaler = SysClk / (baudrat e * 8) - 1
5.4.3 DSU SpaceWire Operation
DSU SpaceWire does not support RMAP commands, it uses the same protocol as the DSU UART (see Figure 5-32). A command always starts with a MSB = 1 to indicate command (read/write and length). Prepended charact ers wit h MSB = 0 are ignored. The transmit speed can be adjusted via the DSU_UART_SpW_Ctrl register and can be set t o eit her 10 MBit /s or t o SysClk.
Note: In DSU SpaceWire operation the link is hardcoded to autostart mode and therefore automatically st art s t he link aft er NULL t oken have been received.
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5.5 Serial Peripheral Interface (SPI)
The SPI module works as SPI master, but it is prepared to operate either as Clock Master or as Clock Slave (see chapter 6.4.5 for furt her det ails).
In order to initiate a transfer, the transmitter has to be enabled first by setting the TxEn bit in t he SPI_StatusAndCtrl regist er. Then the data to be transferred has to be written to the SPI_Tx register and is loaded by the hardware int o t he TxShifter. If the data has been transferred from the SPI_Tx register into the TXShifter, the XmtEmpty flag signals t hat t he SPI_Tx register is now empty and that new dat a can be loaded into the SPI_Tx register if needed (e.g. consecut ive dat a t ranfers).
Transfer in the above sense means that the data from the SPI_Tx register is transmitted on the MOSI pin, while at t he same time data is received on the MISO pin. The received data is collected in the RxShift er and t ransferred int o t he SPI_Rx regist er aft er DataLength bit s have been received.
If a t ransfer of one register content has been completed the user gets notified via the SPI interrupt which is visible and cont rollable in t he Communicat ion Int errupt Cont roller (CIC).
Wit h the bitfield DataLength in the SPI_StatusAndCtrl register the number of bit s t o be t ransferred/received can be programmed. Note that the minimum number of bits to transfer/receive is 8bits, while the maximum is 16bits. Note also t hat t he DataLength field always applies for t ransmit and receive at t he same t ime.
MOSI MISO
Tx Shifter (16bit)
TxEn
Rx Shifter (16bit)
SPI Block SPI_Tx (16bit) SPI_Rx (16bit)
Fi gure 5-33: SPI Bl ock
The XmtDone flag of SPI_StatusAndCtrl register can be used as a status flag in order to see when a transfer is ongoing and when it is completed. The XmtDone flag is "0" as long as t he t ransfer is ongoing and "1" if t he t ransfer is complet ed. Not e t hat t he XmtDone flag is cleared if t he TxEn bit is set t o "0".
Aft er a SPI transmission, the content of the RxShifter is transferred to the SPI_Rx regist er. The RxAvailable flag in SPI_StatusAndCtrl register indicates that the received data is available in the SPI_Rx register. It is set back t o zero by reading it. Note: If the SPI_Rx register is not read, then the new receive process will overwrite the content of the SPI_Rx regist er.
Dat a transfer order: If MsbFirst=0 then the LSB of the data (or SPI_Tx) is t ransmit t ed first (meaning Bit 0 of t he SPI_Tx). If MsbFirst=1 then the MSB of the the data (not the SPI_Tx) is transmitted first (depending on what is set in t he DataLength field).
By set ting the Ss_n_afterTx bit in the SPI_StatusAndCtrl register to "1" it is possible to do consecutive data transfers in a way t hat the corresponding slave is not de-assert ed bet ween t he t ransfers. However in t his case t he following procedure has t o be applied:
· Set t he TxEn bit in t he SPI_StatusAndCtrl regist er · Writ e Data t o t he SPI_Tx regist er · Wait until the bit XmtEmpty in the SPI_StatusAndCtrl register is "1" and then writ e new dat a in t he SPI_Tx
regist er. Note that it can take a few SysClk cycles until the XmtEmpty flag is being raised after t he first writ e t ransfer has been initiated. This is due to the fact t hat t he SPI and syst em clock domain can be different (SPIClk is t ypically slower t han t he SysClk). · Met hod A (interrupt driven): In case the SPI interrupt occurs, read the XmtEmpty flag. If it is "1" writ e new dat a t o t he SPI_Tx regist er.
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· Met hod B (polling): Always poll t he XmtEmpty flag. If it is " 1" writ e new dat a t o t he SPI_Tx regist er.
The last bullet (either Method-A or Met hod-B) shall be repeat ed unt il t here is no more dat a t o t ransfer for t he consecutive data transfer. The user has to decide in his applicat ion which met hod is t he most effect ive for him.
Timing diagrams for SPI operat ion can be found in [AD-04].
5.6 16-bit I/O Port
To access the I/O ports the PIO_IO register has to be read/written. Note that there is only one regist er for input and out put . The PIODirection regist er defines t he direct ion of t he corresponding I/O port . Wit h t he PIOIntConfig regist er it is also possible t o feed up t o four ext ernal int errupt s int o t he AGGA-4. See programming sect ion for more det ails.
Note: After changing the PIOIntConfig register, the corresponding interrupt should be cleared in the Primary Int errupt Cont roller. A change of t he configurat ion may generat e a single int errupt .
To save pins, I/O pins are shared wit h ot her funct ions: · PIO(0) and PIO(1) define the PROM widt h at boot time (see also MCFG1 register), note that PIO(0) has to be t ied t o 0 during reset · PIO(2) defines t he EDAC usage for PROM at boot t ime (see also MCFG3 regist er) · PIO(8) is used as UART-1 CTSN signal if flow cont rol is enabled in t he UART1_Ctrl · PIO(9) is used as UART-1 RTSN signal if flow cont rol is enabled in t he UART1_Ctrl · PIO(11) is used as UART-1 TX signal (in addition to the dedicated UART1_TX pin) if the bit TxEn is enabled in t he UART1_Ctrl regist er and provided t hat PIO(11) is configured as out put . · PIO(12) is used as UART-0 CTSN signal if flow cont rol is enabled in t he UART0_Ctrl · PIO(13) is used as UART-0 RTSN signal if flow cont rol is enabled in t he UART0_Ctrl · PIO(15) is used as UART-0 TX signal (in addition to the dedicated UART0_TX pin) if the bit TxEn is enabled in t he UART0_Ctrl regist er and provided t hat PIO(15) is configured as out put .
Reading t he PIO_IO register always gives the actual value on the corresponding PIO pins. Writing the PIO_IO regist er always set s t he value t o be used when t he corresponding PIO pin is in out put mode.
Note: If flow control is used for the UART, then the PIO direction of t he RTSN signal has t o set as out put and t he CTSN signals has t o be set as input in t he PIODirection regist er.
5.7 GPIO
In addit ion to the 16 bit I/O port provided by the LEON on-chip peripherals further 16 general purpose input /out put ports are implemented. All 16 GPIOs are implemented as bi-directional ports. This gives t he user t he possibilit y t o configure t he number of input s or out put s according t o his needs.
The GPIO_Status register can be used to get the current level on the particular GPIO pin, no matter if it is configured as input or output. A "1" represents a high level on the GPIO pin, while a "0" represents a low level on t he GPIO input pin.
The GPIO_Direction regist er can be used t o configure a part icular GPIO pin as input or out put . A "1" in t he corresponding bit posit ion of t he GPIO_Direction regist er configures t he pin as an out put , while a "0" in t he corresponding bit posit ion of t he GPIO_Direction regist er configures t he pin as an input .
The GPIO_Output register can be used to assign a certain level to a particular GPIO pin. Note that the sett ings writ t en t o this register have only an effect if the GPIO pin is configured as output. Otherwise the programmed output value has no effect. A "1" written to the corresponding bit position of the GPIO_Output register assigns the corresponding GPIO pin t o Vcc, while a "0" in the corresponding bit position of the GPIO_Output register assigns the corresponding GPIO pin t o Ground. If the GPIO_Output register is read it returns the programmed values, not the current status of the GPIO pins.
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5.8 Serial General Purpose Output (SGPO)
Beyond the standard UART ports described in sect ion 5.1, a modified UART t ransmit t er wit h a 16 byt e FIFO is available, using t he AGGA-4 pin SGPO. When t he applicat ion soft ware writ es int o SGPO_Tx, t he hardware aut omatically splits the 32bit word into bytes and feeds 1, 2, 3 or 4 of them into the UART FIFO (least significant byt e first). The ByteSel field in the SGPO_Ctrl register determines how many bytes of the 32bit word are transferred into the FIFO. The application software has to take care that the FIFO has no overrun. The FIFO st at us can be read by reading t he SGPO_Status register. An interrupt SGPOOverrun is generated, indicating that dat a has been lost . The int errupt is visible and cont rollable in bit 0 of t he Communicat ion Int errupt Cont roller (CIC). It is also possible to disable the transmitter by set t ing t he TxEn bit in t he SGPO_Ctrl regist er t o zero. Wit h t he configurat ion bit s PS in t he SGPO_Ctrl regist er t he parit y can be swit ched bet ween even and odd. Wit h t he configurat ion bit s PE in t he SGPO_Ctrl regist er t he parit y can be enabled or disabled. The baud rate can be programmed by writing to the SGPO_Scaler register. This 12bit divider is used t o generat e t he baud rat e from t he LEON clock.
Scaler = LeonClk -1 BaudRate * 8
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6 System Support Functions
6.1 FFT Module
The FFT-Module performs the Fast Fourier Transformation using t he radix-2 algorit hm developed by Cooley and Tukey. The implement ed FFT uses 128 point s.
AHB
FFT -Amba I/F
FFT Module
Accesscontrol
FFT Engine
SRAM-I 128x
SRAM-Q 128x
Fi gure 6-1: FFT Modul e
6.1.1 FFT-AHB interface
In order to guarantee high data transfer rates to the FFT module it is integrated as an AMBA module. The data t ransfer is realized via t he AMBA bus. The FFT module is connect ed as a slave module t o t he AHB.
6.1.2 FFT Handling
The data written by the processor into the RAM is composed of real and imaginary data. The expected format is 32bit t wo's complement integer numbers. Since the FFT handles complex data, two RAMs are implemented. All data written at even address (0, 8, 10, ..), is written into the SRAM-I, which contains the real part of the value. Dat a writ t en at odd address (4, C, 14, ..), is written into the SRAM-Q, which contains the imaginary part of t he value. Not e t hat t he bit reversal of the sample indexes is done in hardware, so that the soft ware can writ e t he sequent ial input values ont o sequent ial FFT RAM addresses. This sample re-ordering process is executed automatically as the values are writ t en t o t he FFT RAM. This means that when a value is written to the address that should hold the n-th (sequent ially ordered) sample, the value is actually written to the address that corresponds to the index m, where m is the value of the reversed binary representation of n. In other words, when the SW wants to write the n-th (zero-based indexing) input sample of t he input it does so by issuing a write command to the FFT Module's base address (0xB0000000) plus an offset of 2n*4 byt es, for the real part, or (2n+1)*4, for the imaginary part. However, this value is instead (transparently) written to t he offset 2m*4, for the real part, or (2m+1)*4, for t he imaginary part , wit h m being t he value of t he bit -reversed n.
For example, the value written to the FFTValue_1_real position of the FFT RAM (n=1, '0000001' in binary) is actually writ t en by the hardware to the FFTValue_64_real position. (m=64, '1000000' in binary).
Aft er the write transfer is completed, the user should set the StartFFT bit in the FFTCtrl register. If t his bit is set , t he FFT engine starts and takes over the control of the access to the FFT RAMs. If the FFT has been started the FFT RAM must not be accessed by the processor or any other party then the FFT until the FFT is done. This is because t he FFT module is using t he FFT RAM also for int ermediat e calculat ion st eps.
If t he processor tries to access the FFT RAMs during the time t hey are under cont rol of t he FFT engine, an error response will be generat ed on t he AHB. Reading t he FFT cont rol regist er is always possible.
Aft er the FFT processing is finished, t he FFT module generat es an int errupt FFTdone in t he Primary Int errupt Cont roller and the processor can fetch the processed values which are located in t he same FFT RAM area where t he input data has be written to. If the Interrupt is masked it can be used as a status flag. FFTdone is also visible in FFTCt rl regist ers (cleared when writ ing t o FFTCt rl).
Not e that there is no need from the software side to scale the inputs, in order t o avoid an overflow wit hin t he FFT.
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The outputs of the FFT are IEEE 754 single precision Floating Point Numbers. However, it should be not ed t hat t he int ernal implementation is a 55-bit (39 + 16) fixed point format, stripping the lower 16 decimal bits aft er each radix-2 but t erfly. As a consequence, a data dependent rounding error is introduced which can lead t o significant (>> 100%) relative errors for individual samples when comparing wit h a float ing-point implement at ion. However, when normalising the relative error by the maximum absolute value, hence dividing by max [ abs (FFT(i) ], t he error is bounded t o a few percent, allowing the correct detection of t he peak value t o det ermine t he Doppler shift during acquisit ion.
A Fast Fourier Transformat ion is execut ed in 5126 SysClk cycles.
6.2 CRC Module
The architecture of the CRC block is depicted in Figure 6-2. The core consist s of a 32bit LFSR regist er and a 32bit polynomial regist er. Therefore up t o 32bit CRC's can be calculat ed.
CRC Polynom Xn-32
Xn-31
Xn-30
Xn-4
Xn-3
Xn-2
Xn-1
...
31
1320
29
&
&
&
3
2
1
0
&
&
&
&
+
+
+
+
+ ... +
+
Bitstream
3311
CRC LFSR
30
4
3
2
1
0
DMA Start Address DMA Current Address
DMA End Address
Fi gure 6-2: C RC Hardware Archi tecture
Byte 0 Byte 1 Byte 2
... Byte n
In order to set up the CRC, the polynomial must be programmed to the desired CRC t ype via the register CRCPolynom. Not e that the highest order term has to be discarded. Example: In order to program the Polynomial 1 + x5 + x12 + x16 int o the register, the taps for x0, x5 and x12 have to be set to ,,1", while x16 is discarded. The polynomial must be right aligned and in reversed format. That means for a 16 bit CRC t he bit 0 (right most bit ) of t he CRCPolynom regist er corresponds to x15 ,while for a 32 bit CRC t he bit 0 of the CRCPolynom register corresponds t o x31. Table 6-1 gives some examples of t he values which have t o be programmed in order t o get t he desired CRC funct ion.
The init value for the CRC calculation has to be written to the CRCLFSR register prior to every CRC st art . When t he CRC calculation has been done, the CRCLFSR register (containing the final CRC checksum) is XOR'ed with the value of t he CRCFinalXOR register. After this, the software gets notified via int errupt . Addit ionally t he readiness can be polled by masking the interrupt and polling the interrupt pending register.Note that the readiness can not be polled by observing t he current point er.
It has to be noted that not all CRC types require a final XOR multiplication. In that case the CRCFinalXOR register has t o be programmed to zero. Note that the final XOR value has to be written only once in order to configure t he t ype of CRC. It has not t o be programmed every t ime a CRC is t riggered.
By default, the CRC result in CRCLFSR is provided in normal format, i.e. bit 0 will contain the LSB of the CRC (= t he x0 t erm). For some CRC types it is required to reverse the CRC result after the final XOR multiplication (MSB<->LSB swap). This can be programmed by setting the bit ReverseResult in the CRCCtrl register to 1. In this case the content of t he CRCLFSR register is bit-reversed and automatically right aligned by the hardware. E.g. a CRC of lengt h 16 would be reversed and right shift ed by 16, bit 0 will cont ain t he x15 t erm.
In order to define the data which shall be processed the start and end address can be set wit h t he CRCStartAddress respectively CRCEndAddress register. The CRCStartAddress has to be word (32bit) aligned, while the CRCEndAddress can be byte aligned. After a write to CRCEndAddress register, the CRC calculation is started. Therefore t his regist er should be configured as t he last one.
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As soon as the CRCEndAddress register is written, the DMA machine will start and fetch the first byte and hand it over t o the CRC calculation. The byte is feed bitwise into the CRC. With the bit ReverseInData in t he CRCCtrl regist er it can be det ermined whether a byte is put from MSB to LSB or vice versa int o t he Bit st ream FIFO. By reading t he CRCCurAddress register it returns the address of the byte which is currently processed. Note that during CRC runt ime t he user shall not writ e any CRC regist er. Ot herwise t he CRC processing get s corrupt ed.
Example: In order t o calculat e t he CRC over 6 byt es which are placed st art ing at address 0x40000000, t he CRCStartAddress would have t o be programmed t o 0x40000000, t he CRCEndAddress t o 0x40000005.
CRC Type
Polynomial
Rev erse Rev erse CRCPolynom CRCLFSR (Init) CRCFinalXOR InData Result
CRC16-CCITT 1 + x5 + x12 + x16
0x00008408 0x0000FFFF
0x00000000
0
0
IBM-CRC-16 CRC-32 (IEEE 802.3)
1 + x2 + x15 + x16 1+ x1+ x2+ x4+ x5+ x7+ x8+ x10+ x11+ x12+ x16+ x22+ x23+ x26 x32
0x0000A001 0xEDB88320
0x00000000 0xFFFFFFFF
0x00000000 0xFFFFFFFF
1
1
1
1
Tabl e 6-1: C RC Exampl es CRC16-CCIT T refers to the implementation specified in the ITU-T Recommendation V.41 (1988) and in ECSS-E-7041A (2003) or ECSS-E-ST-70-41C (2016). AGGA4 correct ly meet s t he t est cases specified in t hese st andards.
Please note that other implmentations may exist, also labeled `CRC-CCITT', producing different result s, even t hough using t he same polynomial.
6.3 EEPROM Support Function
In space hardware it is required to switch-off the EEPROM devices when t hey are not in use, because of t he dat a ret ent ion issues. Therefore t he AGGA-4 offers an EEPROM swit ch funct ionalit y as depict ed in Figure 6-3.
APB Register
AGGA-4
EEPROM Power Switch Functionality
EEPROM_POWER EEPROM_RESET_N EEPROM_ENABLE
Figure 6-3: EEPROM Power Swit ch Funct ionalit y
By writ ing 0xAFFEDEAx (x= 0..F) in the EEPROM_Switch bitfield in the EEPROM_StatusAndCtrl register the switch on sequence is initiated. After switching on, the EEPROM_On bit indicates this as "1" and t he EEPROM is powered.
By writ ing 0xDEADAFFx (x= 0..F) in the EEPROM_Switch bitfield in the EEPROM_StatusAndCtrl register the switch off sequence is initiated. After switching off, the EEPROM_On bit indicates this as "0" and t he EEPROM is powered down aft er t 4.
By reading the 4 LSB's of the EEPROM_StatusAndCtrl register the current st at us of t he EEPROM cont rol signals (EEPROM_On, EEPROM_POWER, EEPROM_RESET_N and EEPROM_ENABLE) can be read.
Not e that all bits in EEPROM_StatusAndCtrl are 0 aft er reset , t he EEPROM is disabled. The EEPROM Support Funct ion can t herefore not be used for a boot EEPROM.
The swit ching of t he pins is performed in a part icular sequence as depict ed in Figure 6-4.
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EEPROM_Power
EEPROM_RESET_N
EEPROM_ENABLE
t1 t2
t3 t4
Figure 6-4: EEPROM Swit ching Sequence
The individual t imes ar as follow: · T1 = 1ms · T2 = 2ms · T3 = 100ms · T4 = 101ms
Not e that the above specified times T1 to T4 are only true if the pin configurable SYS_CLK_DIV divider is set such that t he out put of t he divider equals t o 10 MHz.
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6.4 Clock Distribution
HALF_SAMPLE_CLK EXT_CORE_CLK
GNSS Clk Block
/2.5 1
0
CoreClkSel
AGGA-4 HalfSampleClk CoreClk
To GNSS Core
EXT_MIL_CLK MIL_PLL_ICP[1:0] 2
MIL_PLL_LOCK MIL_CLK_OUT SYS_CLK_OUT
10 MHz
MilBus Clk Block
0
PLL x16
/10 1
MilBus
ClkSel
/4 /10
1553Clk SysClk
To Mil-Bus IP Core
SYS_PLL_LOCK
System Clk
SYS_PLL_FREQSEL[1:0]
2
PLL
Block
SYS_CLK_DIV[3:0] 4
DIV
x4
10
x8
MHz
L
SYS_CLK_ICP[1:0] 2
EXT_SYS_CLK
H
SYS_PLL_BYPASS
SPI_OUT_CLK SPI_IN_CLK
SPI Clk Block
0 DIV /8
1
0 1
ClkSel
SysClk
To Leon2-FT Core, System Periphery
SysClk
To SpaceWire
SpW 10MHz Clk
Module
SPIClk
To SPI Interface
Fi gure 6-5: AGGA-4 C l ock Di stri buti on
The clock generation and distribution is shown in Figure 6-5. The minimum periods for the clock domains shown at the right side of the figure as well as other clocking constraints and recommendations. These minimum periods have t o be respected from cycle-to-cycle, the jitter of the clock sources and t he int ernal PLL's has t o be considered, possibly leading to a reduced maximum frequency. Further details of the clock generation are provided in t he following subsect ions.
C l ock Domain C onstraint / Comment
CoreClk
Recommended frequency: 40 MHz
HalfSampleClk Frequency shall be exactly 2.5 x CoreClk only in DDC Mode
SysClk
Frequency shall be >= CoreClk Note: SpaceWire transmission clock is related to SysClk
1553Clk
Recommended 16 MHz, to be compliant wit h MIL standard
SpW10MHzClk Recommended 10 MHz, to be compliant wit h SpaceWire standard
SpWRxClk
Clock domain recovered from Data-St robe input signals in SpaceWire
SPIClk
Tabl e 6-2: C l ock domai ns
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6.4.1 System Clock (SysClk) Divider
It is possible to divide the clock signal applied to EXT_SYS_CLK by an integer value. The division is programmable via t he 4bit SYS_CLK_DIV external pin configuration. If all SYS_CLK_DIV pins are all logical low, the division factor is 1 (out put clk = input clk). If the pin SYS_CLK_DIV [0] is high and SYS_CLK_DIV [1:3] are low, t he division fact or would be 2 and so on. If any of the following functions is used, the divider should be programmed such that the output frequency is 10 MHz.
· Syst em PLL · MilBus PLL · EEPROM support funct ions · SpW int erface
6.4.2 GNSS Core Clock (CoreClk) Generation
The GNSS Core can be provided with two clock inputs. The HALF_SAMPLE_CLK and the EXT_CORE_CLK. While t he HALF_SAMPLE_CLK is directly fed into the GNSS core, the CoreClk can be derived from t wo sources. By t he CoreClkSel bit in the GNSSCoreClkCtrl register it can be selected whether the user wants to generate the CoreClk from a 2.5 division of the HALF_SAMPLE_CLK or if he wants to select the CoreClk direct ly from t he EXT_CORE_CLK input pin (default ). Not e: Besides of being radiation hardened, the CoreClkSel bit is also prot ect ed by t riple redundancy against SEU.
6.4.3 Mil-Bus Clock Generation
The MilBus IP Core is supplied wit h the two clocks: 1553Clk and SysClk. The 1553Clk has t o be 16MHz in order t o comply wit h the MIL-1553 data rate requirements. 1553Clk can be taken directly from the input pin EXT_MIL_CLK or it can be generated with an internal PLL. This can be selected by the MilBusClkSel bit in t he MilBusClkCtrl regist er. For monit oring purposes, 1553Clk divided by 4 is provided at t he out put pin MIL_CLK_OUT.
If t he PLL is selected, the PLL takes its input clock from the divided EXT_SYS_CLK pin. The PLL then mult iplies t he 10 MHz PLL input frequency by 16, thus generating 160 MHz. The 160 MHz is then divided by 10 in order t o arrive wit h 16MHz for t he 1553Clk.
f1553Clk = fEXT_SYS_CLK / (DivRat io +1) * 16 / 10
6.4.4 System Clock (SysClk) Generation
The Leon2-FT as well as the UARTs and the periphery are supplied with the SysClk. The SysClk can eit her be t aken directly from the EXT_SYS_CLK pin or it can be taken from the PLL. The selection is done by t he SYS_PLL_BYPASS pin. If t he SYS_PLL_BYPASS is assert ed logical high, t he PLL is bypassed and t he SysClk is t aken from t he EXT_SYS_CLK pin. If the SYS_PLL_BYPASS is asserted logical low, the PLL is enabled and the SysClk is driven by the PLL output. For monitoring purposes, SysClk divided by 10 is provided at t he out put pin SYS_CLK_OUT. Wit h SYS_PLL_FREQSEL = 0, the multiplication factor of the system clock PLL is 4, wit h SYS_PLL_FREQSEL = 1, t he mult iplicat ion fact or is 8.
Note: The overall processing performance does not increase linearly with SysClk. External fact ors (e.g. SRAM Wait St at es) are also relevant , and t herefore t he overall performance needs t o be analysed at syst em level.
Note: The SysClk frequency always has to be equal or greater than the GNSS CoreClk frequency. Ot herwise a st able operat ion of t he AGGA-4 syst em can not be guarant eed.
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6.4.5 SPI Clock (SPIClk) Generation
Alt hough the AGGA-4 is the SPI Master, it can also accept a clock input from a SPI slave. This is needed in order t o properly communicate with Saphyrion RF Front End chips which use a modified SPI int erface (clock is provided by SPI slave). Therefore the AGGA-4 has a bit ClkSel in t he SPI_StatusAndCtrl regist er by which select s bet ween int ernal and ext ernal SPIClk.
· Clk Sel = 1: SPIClk is taken directly from the pin SPI_IN_CLK. The incoming clock synchronized internally. A change of mode won't lead to glitches in the internal AGGA-4 logic, but the current transfer may be corrupted. Therefore it is recommended t o change t he clock direct ion only if no t ransfer is ongoing.
· ClkSel = 0: SPIClk is derived from SysClk as shown in Figure 6-5, pre-divided by 8 and further divided by the 8bit programmable DivRatio bitfield in the SPI_ClkDivider register. The divider ratio has t o be programmed according t o t he following formula:
DivRatio = SystemClk -1 8 SPIClk
6.4.6 SpW Clock Generation
The SpaceWire modules require two clock inputs. A SpW10MHzClk for start-up and the SysClk for fast t ransmission. The SpW10MHzClk is derived by t he divided EXT_SYS_CLK.
6.4.7 PLL Lock Status
The Lock St atus of the two PLLs (System and MilBus) can be monitored either via regist er or via t he ext ernal pins MIL_PLL_LOCK and SYS_PLL_LOCK. If read via register, the status of the Leon PLL can be read by reading the LeonPLLStatus bit in the PLLStatus regist er. The st at us of t he MilBus PLL can be read by reading t he MilBusPLLStatus bit in t he PLLStatus regist er. Not e t hat aft er power on it t akes 2400 EXT_SYS_CLK cycles unt il t he MilBusPLLStatus is set .
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6.5 Reset Mechanisms
The AGGA-4 has several reset possibilities which are depicted in Figure 6-6. Besides a global "Power On Reset" at pin PWR_ON_RESET_N, there are other reset possibilities which only reset parts of the AGGA-4. Each occurrence of such a partial reset is registered in the ResetStatus register. This allows t he software to determine the reset source after a reset has occurred. Moreover, the upper bits of the ResetStatus register can be used by t he soft ware t o st ore informat ion which is not cleared by any reset , except power on reset .
NMI_INT WDOG1_N WDOG2_N AGGA4_RESET_N
GNSS_RESET_N
PWR_ON_RESET_N
0
Watchdog WdogSel OR
1st
1
1
elapse
2
0
2nd elapse
SW Reset
3 4
OR
0xDEADAFFE
0xBEBECAFE
5
0xCAFEBEBE
6
OR
7
SpW Reset Mil-Bus Reset UART Reset
NMI
AGGA Reset: Reset whole AGGA-4, but not ResetStatusReg and not IMT counter
GNSS Reset: Reset GNSS Module
Reset SpW Module Reset Mil-Bus Module Reset UART Module Reset whole AGGA-4 Mil-Bus triggered Reset
AGGA-4
Reset Status Reg
NMI external
0
NMI Wdog
1
Wdog Reset 1 2
Wdog Reset 2 3
AGGA Reset HW 4
AGGA Reset SW 5
GNSS Reset SW 6
GNSS Reset HW 7 Mil-Bus trig.Reset 8
8
MIL_RESET_OUT_N
Fi gure 6-6: Reset Possi bi l i ti es wi thi n AGGA-4
Most of the registers in AGGA-4 use a synchronous reset. Therefore it is generally required that all clocks are act ive during reset (see also section 8.4.4). After assertion of any of the global AGGA-4-reset sources (PWR_ON_RESET_N, AGGA4_RESET_N, SW Reset, Watchdog, but not the GNSS_RESET_N), the internal reset is kept assert ed unt il t he SysClk PLL has asserted its lock signal (if that PLL is used at all), plus an addit ional 128 SysClk cycles. When t he SysClk PLL is disabled (bypassed), the delay is always 128 SysClk cycles. When the PLL loses lock (= de-assert s it s lock signal) during operation, no reset will be generated. The 1553Clk PLL lock is not taken into account during reset generat ion. The PrimaryRAM1/2 and SecondaryRAM1/2 memories are not reset .
6.5.1 Power On Reset
Assert ing PWR_ON_RESET_N to low level will restore the default values of all regist ers as specified in chapt er 7, including the ResetStatus and IMT counter (IMT_MSW, IMT_LSW) registers, provided that t he respect ive clocks are act ive. The registers which have no default value are marked as "undef" in the "Default" column in t he programming sect ion (chapter 7). The content of these registers is undefined after the Power On Reset. After deassert of the ext ernal power on reset, the AGGA-4 internal reset is de-asserted after 9 EXT_SYS_CLK cycles if SYS_PLL_BYPASS = 1 and 2209 EXT_SYS_CLK cycles if SYS_PLL_BYPASS = 0. Aft er t he syst em part is ready, t he GNSS Core t akes an addit ional 4 CoreClk cycles t o reset .
6.5.2 Watchdog Reset
The wat chdog consists of an 18 bit WdogPrescaler register and a 24 bit counter which is reloaded wit h the WdogReload value. The prescaler is clocked wit h the SysClk. With every time t ick t hat is generat ed from t he prescaler t he pre loadable wat chdog counter is decremented. The watchdog can be configured with a two-stage "bark and bite" function: If t he counter elapses (= reaches zero) for the first and for the second time, depending on t he set t ing of t he WdogSel regist er, t he following act ions t ake place:
Act ion WdogSel = 0 WdogSel = 1
1st elapse AGGA-4 Reset is executed (bite) NMI interrupt is generated (bark)
2nd elapse Not applicable AGGA-4 Reset is executed (bite)
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Regardless of the WdogSel register, the two elapse's (bark and bite) are signalled by driving the open-drain output pins WDOG1_N and WDOG2_N t o 0. Writing to the ReloadValue register returns the state of the wat chdog t o t he init ial st at e (before t he `1st elapse').
The wat chdog can be disabled by setting the ReloadValue in the WdogReload register to zero (default state after reset ). Not e that bit (15:0) of the WdogPrescaler register (t he PrescaleValue) are mapped t o bit s (17:2) of t he int ernal prescaler register which is used by the watchdog function, hence the prescaler division ratio is given as PrescaleValue *4 + 2. The default value of t he PrescaleValue fieldaft er reset is all "1". There is a dedicated write enable register (WdogWriteEnable) which inhibits an accident al writ e t o t he prescaler or reload value of the wat chdog. The user has to write the pattern "DEADAFFE" in the WdogWriteEnable register, before t he write access to either the reload or the prescaler value is granted for one time. The write enable register gives writ e access t o one regist er (reload/prescaler) for one t ime. The Wat chdog Elapse Time can be calculat ed wit h t he following formula:
Wat chdog Elapse Time = SysClkPeriod * ((PrescaleValue * 4) + 2) * (ReloadValue + 1)
6.5.3 AGGA-4 Reset
The AGGA-4 reset can be triggered by the Watchdog, the AGGA4_RESET_N input pin or by t he soft ware (Soft ware Reset registers). The AGGA-4 reset will restore the default values of all registers as specified in chapt er 7, except for t he ResetStatus and IMT counter registers. The ResetStatus register allows t he software to reconstruct the reset source. Wit h the IMT counter the soft ware can reconst ruct t he blackout t ime aft er a reset . This can be used for a fast reacquisit ion of t he GNSS signals aft er an AGGA-4 reset has occurred. The duration of the AGGA-4 Reset is 1 SysClk (internal) cycle + 5 EXT_SYS_CLK cycles. Aft er t he syst em part is ready, t he GNSS Core t akes addit ional 4 CoreClk cycles t o reset .
6.5.4 GNSS Reset
The GNSS reset can be triggered by the GNSS_RESET_N input pin or by t he soft ware (Soft ware Reset regist ers SwReset Enable and SwReset Execute). If one of these sources triggers the GNSS reset, only the GNSS module is reset (including t he IMT count er). Not e that during a GNSS reset the Leon shall not access any GNSS regist er. Otherwise the LEON will hang for the time of t he GNSS reset . The durat ion of t he GNSS reset is 1 SysClk (int ernal) cycle + 4 CoreClk cycles
6.5.5 SW Reset
It is possible to trigger an AGGA-4 reset or GNSS reset by software. Therefore two registers are foreseen. With the first one (SwResetEnable) the reset can be armed by writing the pattern "0xDEADAFFE" into this register. Any other value in t his register will inhibit a possible reset signal triggered by software. Note that t he " Enable" is only valid for one writ e access t o t he SwResetExecute regist er. The second register (SwResetExecute) executes the reset. It has t o be not ed t hat t he AGGA-4 Reset is t riggered by writ ing the pattern "0xBEBECAFE" into this register, while the GNSS Reset is triggered by writ ing "0xCAFEBEBE" int o t he regist er. Any existing content or writes to t he SwResetExecute regist er are ignored unless t he regist er has been armed by previously writ ing "0xDEADAFFE" int o t he SwResetEnable regist er.
6.5.6 SpW Reset
The SpaceWire module has a dedicated bit to reset the SpaceWire module. This can be done by writing "1" to the Reset bit in the SpW_ModuleConfig register. There is no dedicated HW pin to reset only t he Space Wire module, but t he SpaceWire module is also reset by t he above ment ioned global AGGA-4 reset s (except GNSS Reset ).
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6.5.7 Mil-Bus Reset
The Mil-Bus module has a dedicated bit to reset the Mil-Bus module. This can be done by writing "1" to the Rst1553 bit in t he C53CDST. There is no dedicated HW pin to reset only the Mil-Bus module, but the Mil-Bus module is also reset by t he above ment ioned global AGGA-4 reset s (except GNSS Reset ).
6.5.8 UART Reset
The UART module can be reset by writing "1" to the Reset bit in the UART_Reset. There is no dedicat ed HW pin t o reset only the UART module, but the UART module is also reset by t he above ment ioned global AGGA-4 reset s (except GNSS Reset )..
6.5.9 Mil-Bus triggered Reset
By sending the Mil-Bus mode command 8-"Reset Remote Terminal" to the AGGA-4, the AGGA-4 will drive the opendrain output pin MIL_RESET_OUT_N to level low for one 1553Clk cycle. By connecting the MIL_RESET_OUT_N pin t o one of the AGGA-4 reset input pins it is possible to force an AGGA-4 reset from the Mil-Bus bus controller to which t he AGGA-4 is connect ed t o.
6.5.10 Reset Status Register
The default value (after Power On Reset) of the ResetStatusRegister is all "1". If any `warm' reset (= except for t he Power On Reset) occurs, this register is not cleared, only the corresponding bit in the ResetStatusRegister is set to zero. This allows SW to distinguish after a reset cycle which reset was executed. The software should set back the all bit s t o "1" aft er a reading t his regist er.
6.5.11 Processor reset
The processor is reset by the PWR_ON_RESET_N or by any of the sources triggering the AGGA-4 reset . Aft er reset , t he processor will start fetching from address 0. In the Processor Status Register (PSR), t raps are disabled (ET = 0), supervisor mode is enabled (S = 1), all other fields are undefined or keep t heir previous value. As indicat ed in t he CacheCtrl register, caches / burst fet ch and snoop are also disabled. Caches need t o be flushed before enabling.
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6.6 AMBA BUS 6.6.1 AHB priorities
There are 7 bus mast ers on t he AGGA-4 AMBA AHB Bus wit h t he following priorit ies:
Priority highest
lowest
Participant 6 DSU 5 Milbus 1553 Module 4 GNSS Module 3 UART Module 2 SpW Module 1 CRC Module 0 Processor
Table 6-3: AMBA Priorit ies
Not e that an AHB burst transaction, once started, can not be interrupted by a higher priority master. This means t hat a even a low priority master can lock the bus for considerable time. Extreme case would be a CPU cache-line fetch (burst of 8), to be multiplied with the duration of a single access (see section 6.6.2 below) from 8-bit PROM wit h maximum (30) wait-states, EDAC on: The latency would be 8*5*(30+2) = 1280 cycles. Even longer lat encies are possible if accesses condit ioned BRDY_N are used.
The following t ransact ion t ypes and burst s are used by t he different mast ers:
· The processor uses 8x burst for cache line fet ches and 2x burst for load / st ore double inst ruct ions · The SpW RX DMA and SpW TX DMA uses 2x burst whenever possible (however, see the issue described in
sect ion 8.4.6). The SPW DMA performs one 32-bit AHB access per 4 SPW charact ers · The UART DMA uses single 32-bit accesses, no burst. Note that the UART-RX and UART-TX performs one
32-bit AHB access per received byt e . · The CRC Module uses single 32-bit accesses, no burst . · GNSS Module does not perform burst. The spacing between two t ransfers. See also descript ion in 3.4.7.4 · Mil1553 Module perform 32-bit accesses, no burst
6.6.2 AHB/APB bus access duration
The duration of an AHB access depends on the area of the address map (see section 7.1) which is accessed, width of the AHB access (8, 16 or 32 bit), on the width of the external memory (8 or 32 bit), the configuration (wait-st at es) and on t he ratio of SysClk / CoreClk frequencies. The duration in number of SysClk cycles can be calculat ed as follows:
· For accesses to PROM, RAM and memory-mapped IO, the duration of a single external access is two (2) plus t he wait states which are either configured in MCFG1 and MCFG2, or the input pin BRDY_N can be used t o impose wait states. However, as explained in the following bullets, depending on access widt h, memory bus widt h one single AHB access, depending on access widt h, memory width, and settings may result in several ext ernal accesses.
· For PROM, up to 30 wait states can be configured in MCFG1, hence a single acess takes up to 32 cycles. One 32-bit AHB read from an 8-bit wide PROM with EDAC enabled result s in 5 accesses (4 dat a and 1 parit y byt e), hence up t o 160 wait st at es can be generat ed.
· For memory mapped I/O area, up to 15 wait states can be configured in MCFG1. The IO area shall always be accessed wit h AHB accesses matching the IO bus widt h (hence using LDUB/STB instruction for 8-bit IO and LD/ST for 32-bit IO), and one AHB t ransact ion always result s in one single I/O access.
· For RAM, up to 4 wait states can be configured in MCFG2, hence a single access takes up to 6 cycles. One 32bit AHB access to 8-bit RAM with EDAC generates 5 memory accesses. Sub-word (8 / 16-bit) writes to RAM wit h EDAC are executed as Read-Modify-Write transactions, resulting in two accesses with 32-bit RAM, and 10 memory accesses wit h 8-bit RAM (read 4 byt es + 1 parit y, writ e 4 byt es + 1 parit y).
· For APB regist ers, t he durat ion is always 2 cycles.
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· Accesses to the registers located in t he GNSS module are crossing t he clock domain, and t heir durat ion depends on the SysClk / CoreClk frequency ratio and phase. The user can check t he t iming wit h t he Trace Buffer.
· Accesses to the FFT module t akes 2 cycles for t he dat a memory and 1 cycle for t he FFTCtrl regist er.
6.7 Test Support Pins
In order to support the application debugging, some internal signals can be accessed via t est pins. These point s are shown in Fi gure 3-30, highlight ed in red.
Not e: These signals are not for flight use. They are combinatorial outputs, and output delay on these signals may vary largely over temperature, supply, from t est point t o t est point , and from channel t o channel bet ween 7 27 ns (compared to EXT_CORE_CLK in PLL Bypass mode). Even at constant temperature / voltage, the skew bet ween t hese signals can be up to 5 ns. This can lead to a cycle slip which should be considered when interpret ing t he signal / code out put s.
6.7.1 I/Q Data
The 3bit I and 3bit Q data can be accessed just before and just after the Final Down Converter of a part icular channel. The I/Q dat a is visible on t he pins SIGNAL_OUT_I[2:0] and SIGNAL_OUT_Q[2:0].
The selection of the channel t o monit or is done by t he programming of t he SignalOutChanSel bit field in t he TestSettings regist er.
The select ion of monit oring before or aft er t he Final Down Convert er is done by t he programming of t he SignalOutPosSel bit field in t he TestSettings regist er.
Not e: If a certain channel shall be monitored the user has to make sure that the channel is activated in the ChActivation0 or ChActivation1 regist er.
6.7.2 IntEpoch and Code Out
It is possible to monitor the Integrat ion Epoch and t he punct ual delay line out put of t wo independent channels.
The Integration Epoch of the first selected channel is visible on the pin INT_EPOCH1, t he Int egrat ion Epoch of t he second selected channel is visible on the pin INT_EPOCH2. The selection of the Integration Epoch or Long Epoch is done by programming t he bit IntSourceSel of CorrUnitCtrl.
The punctual delay line output of the first selected channel is visible on the pins CODE_OUT1[1:0], the punctual delay line out put of t he second select ed channel is visible on t he pins CODE_OUT2[1:0].
The selection of the channel to monitor is done by the programming of the CodeOut1Sel bitfield and the CodeOut2Sel bit field in t he TestSettings regist er.
Not e: If a certain channel shall be monitored the user has to make sure that the channel is activated in the ChActivation0 or ChActivation1 regist er.
6.7.3 IMT_12
The IMT_12 pin connects to the bit 12 of the IMT count (defined from 0 to 63). The IMT count itself is clocked by t he CoreClk. Therefore this pin gives a mean to check if the AGGA sees t he CoreClk and if it the CoreClk has t he desired frequency. Example: A 40 MHz clock at the EXT_CORE_CLK will result frequency of 40 MHz / 213 =~ 4.88kHz on IMT_12.
Not e: If the IMT_12 is observed as a frequency t he divisor is 213 rat her t han 212 as one might t hink. This can be explained by the following example: Imagine the LSB would be observed. Then it changes its value with every CoreClk but it s frequency is CoreClk/2.
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7 Programming
This section lists the registers needed to program and control the AGGA-4. This sect ion uses t he following convent ions:
- `undef' means not affected by any of the resets and content is undefined at power-up. - R means Read-only , writing has not effect unless explicitly mentioned
- W means Write-only, the Read value has no meaning with no side effect unless explicitly mentioned - RW means Read-Write - `reserved' means writing has no effect, and reading value has no meaning
7.1 Overall Address Map
Address Range 0x00000000 - 0x1FFFFFFF 0x20000000 - 0x3FFFFFFF 0x40000000 - 0x7FFFFFFF 0x80000000 - 0x8FFFFFFF
0x90000000 - 0x9FFFFFFF 0xA0000000 - 0xAFFFFFFF 0xB0000000 - 0xBFFFFFFF 0xC0000000 - 0xFFFFFFFF
Size [Mbytes] 512 512 1024 256
256 256 256 1024
M apping
PROM I/O
SRAM Processor, Interface and System Support registers (see section 7.2) DSU (see section 7.3) GNSS (see section 7.4)
FFT (see section 7.5) Unused (see Note below )
M odule Memory Controller
AHB-APB bridge
DSU Module GNSS Module FFT Module
Tabl e 7-1: O veral l Address Map
Note: An access to an empty/unused AHB/APB address locat ion t riggers t he AHB default slave (see AHB st at us regist er, chapt er 4.15)
7.2 APB Address Map (Processor, Interface and System Support)
7.2.1 Overview
Addr e s s 0x80000000 0x80000004 0x80000008 0x8000000C 0x80000010 0x80000014 0x80000018 0x8000001C 0x80000020 0x80000024 0x80000028 0x8000002C 0x80000030 0x80000034
Size [bits] Nam e 31 MCFG1 19 MCFG2 32 MCFG3 28 AHBFailingAddress 10 AHBStatus 32 CacheCtrl 32 Pow erDow n 32 WriteProtect1 32 WriteProtect2 31 LeonConfig
N/A Reserved N/A Reserved N/A Reserved N/A Reserved
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Addr e s s 0x80000038 0x8000003C 0x80000040 0x80000044 0x80000048 0x8000004C 0x80000050 0x80000054 0x80000058 0x8000005C 0x80000060 0x80000064 0x80000068 0x8000006C 0x80000070 0x80000074 0x80000078 0x8000007C 0x80000080 0x80000084 0x80000088 0x8000008C 0x80000090 0x80000094 0x80000098 0x8000009C 0x800000A0 0x800000A4 0x800000A8 0x800000AC 0x800000B0 0x800000B4 0x800000B8 0x800000BC 0x800000C0 0x800000C4 0x800000C8 0x800000CC 0x800000D0 0x800000D4 0x800000D8 0x800000DC 0x800000E0 0x800000E4 0x800000E8 0x800000EC 0x800000F0 0x800000F4 0x800000F8 0x800000FC
Size [bits] Nam e N/A Reserved N/A Reserved 32 Timer1_Counter 32 Timer1_Reload 3 Timer1_Ctrl N/A reserved 32 Timer2_Counter 32 Timer2_Reload 3 Timer2_Ctrl N/A Reserved 10 TimerPrescaleCounter 10 TimerPrescaleReload N/A Reserved N/A Reserved 32 Timer3_Counter 32 Timer3_Reload 3 Timer3_Ctrl N/A Reserved 32 Timer4_Counter 32 Timer4_Reload 3 Timer4_Ctrl N/A Reserved 32 PrimIntMas kAndPrio 16 PrimIntPending 16 PrimIntForce 16 PrimIntClear 16 PIO_IO 16 PIODirection 32 PIOIntConfig N/A Reserved 18 WdogPrescale 24 WdogReload 1 WdogSel 32 WdogWriteEnable N/A Reserved 7 DSU_UART_Status 2 DSU_UART_SpW_Ctrl 14 DSU_UART_Scaler 30 WriteProtectStartAddress3 30 WriteProtectEndAddress3 30 WriteProtectStartAddress4 30 WriteProtectEndAddress4 16 GPIO_Status 16 GPIO_Output 16 GPIO_Direction 9 ResetStatus 32 Sw ResetEnable 32 Sw ResetExecute 6 MilBusRTAddress 12 AGGA4Version
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Addr e s s 0x80000100 0x80000104 0x80000108 0x8000010C 0x80000110 0x80000114 0x80000118 0x8000011C 0x80000120 0x80000124 0x80000128 0x8000012C 0x80000130 0x80000134 0x80000138 0x8000013C 0x80000140 0x80000144 0x80000148 0x8000014C 0x80000150 0x80000154 0x80000158 0x8000015C 0x80000160 0x80000164 0x80000168 0x8000016C 0x80000170 0x80000174 0x80000178 0x8000017C 0x80000180 0x80000184 0x80000188 0x8000018C 0x80000190 0x80000194 0x80000198 0x8000019C 0x800001A0 0x800001A4 0x800001A8 0x800001AC 0x800001B0 0x800001B4 0x800001B8 0x800001BC 0x800001C0 0x800001C4
Size [bits] Nam e 13 CIC_Mas k 13 CIC_Pending 9 CIC_Clear
N/A Reserved 19 SPI_StatusAndCtrl 8 SPI_ClkDivider 16 SPI_Tx 16 SPI_Rx 32 CRCLFSR 32 CRCPolynom 32 CRCFinalXOR 2 CRCCtrl 32 CRCStartAddress 32 CRCEndAddress 32 CRCCurAddress
N/A reserved 27 C53CF 26 C53EMBA 32 C53CDST 9 C53NIT 5 C53EIT 1 C53RIT
N/A reserved 32 C53RTI 32 C53TTI
N/A reserved N/A reserved N/A reserved
32 SGPO_Tx 6 SGPO_Status 5 SGPO_Ctrl
12 SGPO_Scaler 32 UART0_Tx_SAP 32 UART0_Tx_EA P 32 UART0_Tx_CA P 32 UART0_Rx_SA P 32 UART0_Rx_EA P 32 UART0_Rx_CA P
8 UART0_Status 10 UART0_Ctrl 29 UART0_Scaler 32 UART1_Tx_SAP 32 UART1_Tx_EA P 32 UART1_Tx_CA P 32 UART1_Rx_SA P 32 UART1_Rx_EA P 32 UART1_Rx_CA P
8 UART1_Status 10 UART1_Ctrl 29 UART1_Scaler
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Addr e s s 0x800001C8 0x800001CC 0x800001D0 0x800001D4 0x800001D8 0x800001DC 0x800001E0 0x800001E4 0x800001E8 0x800001EC 0x800001F0 0x800001F4 0x800001F8 0x800001FC 0x80000200 0x80000204 0x80000208 0x8000020C 0x80000210 0x80000214 0x80000218 0x8000021C 0x80000220 0x80000224 0x80000228 0x8000022C 0x80000230 0x80000234 0x80000238 0x8000023C 0x80000240 0x80000244 0x80000248 0x8000024C 0x80000250 0x80000254 0x80000258 0x8000025C 0x80000260 0x80000264 0x80000268 0x8000026C 0x80000270 0x80000274 0x80000278 0x8000027C 0x80000280 0x80000284 0x80000288 0x8000028C
Size [bits] Nam e 1 UART_Reset
N/A reserved N/A reserved N/A reserved N/A reserved N/A reserved
1 GNSSCoreClkCtrl N/A reserved
1 MilBusClkCtr l 2 PLLStatus N/A reserved N/A reserved 32 EEPROM_StatusAndCtrl N/A Reserved 13 SpW0_StatusAndCtrl N/A Reserved 32 SpW0_Tx_SAP 32 SpW0_Tx_EAP 32 SpW0_Tx_CAP 9 SpW0_Tx_Rx_Config 32 SpW0_Rx_SAP 32 SpW0_Rx_EAP 32 SpW0_Rx_CAP N/A Reserved N/A Reserved N/A Reserved N/A Reserved N/A Reserved N/A Reserved N/A Reserved 13 SpW1_StatusAndCtrl N/A Reserved 32 SpW1_Tx_SAP 32 SpW1_Tx_EAP 32 SpW1_Tx_CAP 9 SpW1_Tx_Rx_Config 32 SpW1_Rx_SAP 32 SpW1_Rx_EAP 32 SpW1_Rx_CAP N/A Reserved N/A Reserved N/A Reserved N/A Reserved N/A Reserved N/A Reserved N/A Reserved 13 SpW2_StatusAndCtrl N/A Reserved 32 SpW2_Tx_SAP 32 SpW2_Tx_EAP
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Addr e s s 0x80000290 0x80000294 0x80000298 0x8000029C 0x800002A0 0x800002A4 0x800002A8 0x800002AC 0x800002B0 0x800002B4 0x800002B8 0x800002BC 0x800002C0 0x800002C4 0x800002C8 0x800002CC 0x800002D0 0x800002D4 0x800002D8 0x800002DC 0x800002E0 0x800002E4 0x800002E8 0x800002EC 0x800002F0 0x800002F4 0x800002F8 0x800002FC 0x80000300 0x80000304 0x80000308 0x8000030C 0x80000310 0x80000314
Size [bits] Nam e 32 SpW2_Tx_CAP 9 SpW2_Tx_Rx_Config 32 SpW2_Rx_SAP 32 SpW2_Rx_EAP 32 SpW2_Rx_CAP
N/A Reserved N/A Reserved N/A Reserved N/A Reserved N/A Reserved N/A Reserved N/A Reserved
13 SpW3_StatusAndCtrl N/A Reserved
32 SpW3_Tx_SAP 32 SpW3_Tx_EAP 32 SpW3_Tx_CAP
9 SpW3_Tx_Rx_Config 32 SpW3_Rx_SAP 32 SpW3_Rx_EAP 32 SpW3_Rx_CAP N/A reserved N/A reserved N/A reserved N/A reserved N/A reserved N/A reserved N/A reserved
2 SpW_ModuleConfig 2 SpW_ModuleTimeCtrl 8 SpW_ModuleTimeCode 32 SpW_ModuleIntMask 32 SpW_ModuleIntStatus 32 SpW_ModuleIntClear
7.2.2 LEON and Memory Interface Registers
7.2.2.1 MCFG1 (Memory Configuration Register 1)
M CFG1
Bit
Fie ld
De fault
R/W Description
31 reserved
0 R
reserved
30 PBRDYN
0 R/W PROM area bus ready enable (PBRDYN). If set, a PROM access w ill be extended until BRDY_N is asserted
29 ABRDYN
0 R/W Asynchronous bus ready (ABRDYN). If set, the BRDY_N input can be asserted w ithout relation to the SysClk
28-27 IOBusWidth
undef R/W
Defines the data w ith of the I/O area 00 = 8 bit 10 = 32 bit 01, 11 = reserved (bit 27 shall alw ays be w ritten 0)
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M CFG1
Bit
Fie ld
26 BusReadyEn
25 BusErrorEn
24 reserved 23-20 IOWaitStates
19 IOEnable
18-12 reserved 11 PROMWr iteEn
10 reserved 9-8 PROMWidth
7-4 PROMWr iteWs 3-0 PROMReadWs
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De fault
R/W Description
0 R/W 0 R/W 0 R undef R/W
0 R/W 0 R 0 R/W 0 R PIO[1:0] R/W
15 R/W
15 R/W
1 = Bus ready (BRDY_N) enable for IO accesses 0 = Bus ready (BRDY_N) disable for IO accesses 1 = Bus error (BEXC_N) enable for IO accesses 0 = Bus error (BEXC_N) disable for IO accesses Reserved 0 = 0 w aitstates 1 = 1 w aitstate ... 15 = 15 w aitstates 0 = the access to the memory bus I/O area is disabled 1 = the access to the memory bus I/O area is enabled Reserved 0 = disables w rite access to the PROM area 1 = enables w rite access to the PROM area Reserved Defines the data w ith of the PROM area 00 = 8 bit w idth 10 = 32 bit w idth 01, 11 = reserved (bit 8 shall alw ays be w ritten 0) At reset PROMWidth ist set w ith the values on the PIO input pins. Bit 9 is set w ith the value on the PIO[1] pin. Bit 8 is set w ith the values on the PIO[0] pin. PIO[0] has to be tied to 0.
Defines the number of w ait states during PROM w rite cycles 0 = 0 w aitstates 1 = 2 w aitsates ... 15 = 30 w aitstates Defines the number of w ait states during PROM read cycles 0 = 0 w aitstates 1 = 2 w aitsates ... 15 = 30 w aitstates
7.2.2.2 MCFG2 (Memory Configuration Register 2)
M CFG2
Bit
Fie ld
Default R/W Description
31-13 reserved
0 R Reserved
12-9 RAMBankSize
undef R/W 0 = 2^0 x 8 kByte (8 kByte)
1 = 2^1 x 8 kByte (16 kByte)
2 = 2^2 x 8 kByte (32 kByte)
...
14 = 2^14 x 8 kbyte (128 Mbyte)
15 = 2^15 x 8 kbyte (256 Mbyte)
The 4 banks decoded by RAMS_N[0..3] are alw ays contiguous, hence their address range depends on this field Field not initialised at reset
8 reserved 7 BusReadyEn
0 R Reserved undef R/W 0 = disable BRDY_N for RAMS_N[4]
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M CFG2
Bit
Fie ld
6 ReadModifyWriteEn
Default R/W Description 1 = enable BRDY_N for RAMS_N[4] bitfield is not configured after reset
undef R/W Enable read-modify-w rite cycles on sub-w ord w rites to 32-bit areas w ith common w rite strobe (RWEN_N will always be "0000")
5-4 RAMWidth
3-2 RAMWriteWaitstates 1-0 RAMReadWaitstates
bitfield is not configured after reset undef R/W 00 = 8 bit w idth
10 = 32 bit w idth
01, 11 = reserved (bit 4 shall alw ays be w ritten 0) bitfield is not configured after reset undef R/W RAM Write Waitstates (0..3) undef R/W RAM Read Waitstates (0..3)
7.2.2.3 MCFG3 (Memory Configuration Register 3)
M CFG3
Bit
Fie ld
Default R/W Description
31-30 RFC
0 R
Register file check bits (RFC). Zero check bits are used, sibce register file is implemented w ith hard flip flops
29-28 reserved 27 ME
26-12 reserved 11 WB 10 RB 9 RE 8 PE
7-0 TCB
0 R Reserved 1 R 0 = memory EDAC is not present
1 = memory EDAC is present 0 R Reserved 0 R/W 0 = no w rite bypass for EDAC diagnostic
1 = w rite bypass for EDAC diagnostic 0 R/W 0 = no read bypass for EDAC diagnostic
1 = read bypass for EDAC diagnostic undef R/W 0 = disable EDAC checking of the RAM area
1 = enable EDAC checking of the RAM area PIO[2] R/W 0 = disable EDAC checking of the PROM area
1 = enable EDAC checking of the PROM area At reset this bit is initialized w ith the value of PIO[2] undef R/W Test Check Bits. This field replaces the normal check bits during store cycles w hen WB is set. TCB is also loaded w ith the memory check bits during load cycles w hen RB is set
7.2.2.4 AHBFailingAddress
AHBFailingAddr e s s
Bit
Fie ld
De fault
R/W
31-0 Address
undef R
De s cr iption AHB failing address
7.2.2.5 AHBStatus
AHBStatus
Bit
Fie ld
31-10 reserved
9 CE
Default R/W 0 R
undef R/W
De s cr iption Reserved
EDAC correctable error. This bit is set w hen a correctbale EDAC error is detected
All Rights Reserved Copyright per DIN 34
AHBStatus
Bit
Fie ld
8 NE
7 RW 6-3 HMASTER
2-0 HSIZE
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Default R/W 0 R/W
undef R undef R
undef R
De s cr iption This bit has to be cleared by the softw are New Error. This bit is set w hen a new error occurred. AHBStatus and AHBFailingAddress remain locked (no new error is recorded) until this bit is cleared by SW.
Read/Write. This bit is set if the failed access w as a read cycle, otherw ise it is zero
AHB master. This field contains the master that generated the failed access
0 = Processor 1 = CRC Module 2 = SpW Module 3 = UART_DMA 4 = GNSS Module 5 = Milbus 6 = DSU 7-15 = reserved This field contains the size of the failed transfer 0 = 1 Byte 1 = 2 Byte 2 = 4 Byte 3 = 8 Byte 4-7 = reserved
7.2.2.6 CacheCtrl
Cache Ctr l
Bit
Fie ld
31-30 DREPL
29-28 IREPL
27-26 25-24
23
ISETS DSETS DS
22 FD
21 FI
20-19 CPC 18-17 CPTE
16 IB
15 IP
14 DP
De fault
R/W
1 R
1 R
3 R 1 R 0 R/W
0 W
0 W
2 R undef R/W
0 R/W
0 R
0 R
De s cr iption Data cache replacement policy (DREPL) 1 = Pseudo Random Instruction cache replacement policy (IREPL) 1 = Pseudo Random 3 = 4-w ay associative 1 = 2-w ay associative 0 = disable data cache snooping 1 = enable data cache snooping 0 = data cache is not flushed 1 = data cache is flushed 0 = instruction cache is not flushed 1 = instruction cache is flushed 2 = 2 cache parity bits (CPC) are used to protect the caches Cache parity test bits. (CPTE). These bits are XOR'ed to the data and tag parity bits during diagnostic w rites.
0 = burst f ill during instruction f etch disabled 1 = burst f ill during instruction f etch enabled Instruction cache flush pending (IP). This bit is set w hen an instruction cache f lush operation is in progress
Data cache flush pending (DP). This bit is set w hen a data cache flush operation is in progress
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Cache Ctr l
Bit
Fie ld
13-12 ITE
11-10 IDE
9-8 DTE
7-6 DDE
5 DF 4 IF 3-2 DCS
1-0 ICS
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De fault
R/W
undef R/W
De s cr iption
Instruction cache tag error counter (ITE). This filed is incremented every time an instruction cache tag parity error is detected
undef R/W undef R/W undef R/W undef R/W
Instruction cache data error counter (IDE) - This field is incremented each time an instruction cache data sub-block parity error is detected
Data cache tag error counter (DTE) - This field is incremented every time a data cache tag parity error is detected. Does not overflow , stops at '11'. Can be cleared by w riting zeroes into the corresponding bits
Data cache data error counter (DDE) - This field is incremented each time an instruction cache data sub-block parity error is detected. Does not overflow , stops at '11'. Can be cleared by w riting zeroes into the corresponding bits
Data Cache Freeze on Interrupt (DF) - If set, the data cache w ill automatically be frozen w hen an asynchronous interrupt is taken
undef R/W 0 R/W
0 R/W
Instruction Cache Freeze on Interrupt (IF) - If set, the instruction cache w ill automatically be frozen w hen an asynchronous interrupt is taken
Data Cache state. Indicates the current data cache state Note: Alw ays flush the data cache before enabling 0 = disabled 1 = frozen 2 = disabled 3 = enabled Instruction Cache state. Indicates the current data cache state Note: Alw ays flush the instruction cache before enabling 0 = disabled 1 = frozen 2 = disabled 3 = enabled
7.2.2.7 PowerDown
Pow erDow n
Bit
Fie ld
De fault
31-0 value
R/W 0 R/W
De s cr iption w rite of arbitrary value causes pow er dow n of Integer Unit
7.2.2.8 LeonConfig
Le onConfig
Bit
Fie ld
31 reserved
30 DSUPresent
29 SDRAMPresent
28-26 NrOfWatchpoints
25 UMACPresent
24-20 NWINDOWS
Default R/W 0 R 1 R 0 R 4 R 0 R 7 R
De s cr iption Reserved DSU is present in AGGA-4 SDRAM Controller is not present in AGGA-4 Four Watchpoints are implemented in the AGGA-4 UMAC/SMA C instruction is not implemented in the AGGA-4 There are 8 SPARC register w indow s implemented in AGGA-4
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Le onConfig
Bit
Fie ld
19-17 ICSZ
16-15 ILSZ 14-12 DCSZ
11-10 9 8 7
DLSZ UDIVPresent UMULPres e nt LeonWdgPresent
6 MemStatReg 5-4 FPUType 3-2 PCICoreType 1-0 WriteProtectType
Default R/W 3 R
3 R 3 R
2 R 1 R 1 R 0 R
1 R 2 R 0 R 1 R
De s cr iption Instruction cache set size. The size (in Kbytes) of the instruction cache set. Cache set size = 2ICSZ = 23 = 8 kByte
AGGA4 has 4 instruction cache sets (CacheCtrlReg.ISETS), hence the total data cache size is 32 kByte Instruction cache line size (in 32-bit w ords) = 2ILSZ = 23 = 8 Data cache set size. The size (in Kbytes) of the data cache set. Cache set size = 2DCSZ = 23 = 8 kByte
AGGA4 has 2 data cache sets (CacheCtrlReg.DSETS), hence the total data cache size is 16 kByte Data cache line size (in 32-bit w ords) = 2DLSZ = 24 = 4
UDIV/SDIV instruction is implemented in AGGA-4 UMUL/SMUL instruction is implemented in AGGA-4 Leon standard w atchdog is not implemented in AGGA-4 AGGA-4 has an advanced w atchdog implemented Memory status and failing address register present Gaisler FPU is implemented in AGGA-4 There is no PCI interface in the AGGA-4 Standard Write protection type is implemented in AGGA-4
7.2.3 Timer Registers
7.2.3.1 TimerN_Counter
The register description is valid for the following registers: Timer1_Counter, Timer2_Counter, Timer3_Counter, and
Timer4_Counter.
Tim erN_Counter
Bit Field
De fault
R/W Description
31-0 CounterValue
undef R/W read: current counter value
w rite: counter value is modified once
7.2.3.2 TimerN_Reload
The register description is valid for the following regist ers: Timer1_Reload, Timer2_Reload, Timer3_Reload, and Timer4_Reload.
Tim erN_Reload
Bit Field
De fault
R/W Description
31-0 ReloadValue
undef R/W Timer division ratio = ReloadValue + 1
7.2.3.3 TimerN_Ctrl
The register description is valid for the following registers: Timer1_Ctrl, Timer2_Ctrl, Timer3_Ctrl, and Timer4_Ctrl.
Tim erN_Ctrl
Bit
Fie ld
Default R/W Description
31-3 reserved
0 R Reserved
2 LD
undef W 0 = do nothing
1 = load the reload value into the counter register
1 RL
undef R/W 0 = counter w ill not be reloaded automatically after underflow
1 = counter w ill be reloaded automatically after underflow
0 EN
0 R/W 0 = disable timer
All Rights Reserved Copyright per DIN 34
AT7991 (AGGA-4) User Manual
Tim erN_Ctrl
Bit
Fie ld
Default R/W Description 1 = enable timer
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7.2.3.4 TimerPrescaleCounter
Tim erPrescaleCounter
Bit
Fie ld
Default R/W
31-10 reserved
0 R
9-0 CounterValue
0 R/W
De s cr iption reserved read: current counter value w rite: counter value is modified once
7.2.3.5 TimerPrescaleReload
Tim erPrescaleReload
Bit
Fie ld
De fault
R/W
31-10 reserved
0 R
9-0 ReloadValue
0 R/W
De s cr iption
Reserved
Prescaler division ratio = ReloadValue + 1 Note that this value must be set to at least 7 before enabling the timers
7.2.4 Primary Interrupt Controller Registers
7.2.4.1 PrimIntMaskAndPrio
Prim IntMaskAndPrio Bit Field
31 reserved 30 DSUTraceBufPrio
Default R/W 1 R 0 R/W
29 Timer4Prio
0 R/W
28 PIO3Prio
0 R/W
27 GICHighPrio
0 R/W
26 Timer3Prio
0 R/W
25 PIO2Prio
0 R/W
24 CICPrio
0 R/W
23 Timer2Prio
0 R/W
22 PIO1Prio
0 R/W
21 GICLow Prio
0 R/W
20 FFTDonePrio
0 R/W
19 Timer1Prio
0 R/W
De s cr iption reserved (NMI is alw ays priority 1) 0 = Interrupt is low priority 1 = Interrupt is high priority 0 = Interrupt is low priority 1 = Interrupt is high priority 0 = Interrupt is low priority 1 = Interrupt is high priority 0 = Interrupt is low priority 1 = Interrupt is high priority 0 = Interrupt is low priority 1 = Interrupt is high priority 0 = Interrupt is low priority 1 = Interrupt is high priority 0 = Interrupt is low priority 1 = Interrupt is high priority 0 = Interrupt is low priority 1 = Interrupt is high priority 0 = Interrupt is low priority 1 = Interrupt is high priority 0 = Interrupt is low priority 1 = Interrupt is high priority 0 = Interrupt is low priority 1 = Interrupt is high priority 0 = Interrupt is low priority
All Rights Reserved Copyright per DIN 34
Prim IntMaskAndPrio Bit Field
18 PIO0Prio 17 AHBErrorPrio 16 reserved 15 reserved 14 DSUTraceBufMask 13 Timer4Mask 12 PIO3Mas k 11 GICHighMask 10 Timer3Mask
9 PIO2Mas k 8 CICMask 7 Timer2Mask 6 PIO1Mas k 5 GICLow Mask 4 FFTDoneMask 3 Timer1Mask 2 PIO0Mas k 1 AHBErrorMask 0 reserved
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Default R/W 0 R/W 0 R/W 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R
De s cr iption 1 = Interrupt is high priority 0 = Interrupt is low priority 1 = Interrupt is high priority 0 = Interrupt is low priority 1 = Interrupt is high priority Reserved reserved (NMI is not maskable) 0 = Interrupt disabled 1 = Interrupt enabled 0 = Interrupt disabled 1 = Interrupt enabled 0 = Interrupt disabled 1 = Interrupt enabled 0 = Interrupt disabled 1 = Interrupt enabled 0 = Interrupt disabled 1 = Interrupt enabled 0 = Interrupt disabled 1 = Interrupt enabled 0 = Interrupt disabled 1 = Interrupt enabled 0 = Interrupt disabled 1 = Interrupt enabled 0 = Interrupt disabled 1 = Interrupt enabled 0 = Interrupt disabled 1 = Interrupt enabled 0 = Interrupt disabled 1 = Interrupt enabled 0 = Interrupt disabled 1 = Interrupt enabled 0 = Interrupt disabled 1 = Interrupt enabled 0 = Interrupt disabled 1 = Interrupt enabled Reserved
7.2.4.2 PrimIntPending
Prim IntPending
Bit
Fie ld
31-16 reserved
15 NMI
14 DSUTraceBuf
13 Timer4
12 PIO3
Default R/W 0 R 0 R
0 R
0 R
0 R
De s cr iption Reserved 0 = Interrupt is not pending 1 = Interrupt is pending 0 = Interrupt is not pending 1 = Interrupt is pending 0 = Interrupt is not pending 1 = Interrupt is pending 0 = Interrupt is not pending 1 = Interrupt is pending
All Rights Reserved Copyright per DIN 34
Prim IntPending
Bit
Fie ld
11 GICHigh
10 Timer3
9 PIO2
8 CIC
7 Timer2
6 PIO1
5 GICLow
4 FFTDone
3 Timer1
2 PIO0
1 AHBError
0 reserved
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Default R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R
De s cr iption 0 = Interrupt is not pending 1 = Interrupt is pending 0 = Interrupt is not pending 1 = Interrupt is pending 0 = Interrupt is not pending 1 = Interrupt is pending 0 = Interrupt is not pending 1 = Interrupt is pending 0 = Interrupt is not pending 1 = Interrupt is pending 0 = Interrupt is not pending 1 = Interrupt is pending 0 = Interrupt is not pending 1 = Interrupt is pending 0 = Interrupt is not pending 1 = Interrupt is pending 0 = Interrupt is not pending 1 = Interrupt is pending 0 = Interrupt is not pending 1 = Interrupt is pending 0 = Interrupt is not pending 1 = Interrupt is pending Reserved
7.2.4.3 PrimIntForce
Prim IntForce
Bit
Fie ld
31-16 reserved
15 NMI
14 DSUTraceBuf
13 Timer4
12 PIO3
11 reserved 10 Timer3
9 PIO2
8 reserved 7 Timer2
6 PIO1
5 reserved 4 FFTDone
Default R/W 0 R 0 R/W
0 R/W
0 R/W
0 R/W
0 R 0 R/W
0 R/W
0 R 0 R/W
0 R/W
0 R 0 R/W
De s cr iption Reserved 0 = Interrupt is not forced 1 = Interrupt is forced 0 = Interrupt is not forced 1 = Interrupt is forced 0 = Interrupt is not forced 1 = Interrupt is forced 0 = Interrupt is not forced 1 = Interrupt is forced Reserved 0 = Interrupt is not forced 1 = Interrupt is forced 0 = Interrupt is not forced 1 = Interrupt is forced Reserved 0 = Interrupt is not forced 1 = Interrupt is forced 0 = Interrupt is not forced 1 = Interrupt is forced Reserved 0 = Interrupt is not forced 1 = Interrupt is forced
All Rights Reserved Copyright per DIN 34
Prim IntForce
Bit
Fie ld
3 Timer1
2 PIO0
1 AHBError
0 reserved
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Default R/W 0 R/W 0 R/W 0 R/W 0 R
De s cr iption 0 = Interrupt is not forced 1 = Interrupt is forced 0 = Interrupt is not forced 1 = Interrupt is forced 0 = Interrupt is not forced 1 = Interrupt is forced Reserved
7.2.4.4 PrimIntClear
Prim IntClear
Bit
Fie ld
31-16 reserved
15 NMI
14 DSUTraceBuf
13 Timer4
12 PIO3
11 reserved 10 Timer3
9 PIO2
8 reserved 7 Timer2
6 PIO1
5 reserved 4 FFTDone
3 Timer1
2 PIO0
1 AHBError
0 reserved
Default R/W 0 R 0 W
0 W 0 W
0 W 0 R 0 W 0 W
0 R 0 W
0 W 0 R 0 W
0 W 0 W
0 W 0 R
De s cr iption reserved 0 = Interrupt is not cleared 1 = Interrupt is cleared 0 = Interrupt is not cleared 1 = Interrupt is cleared 0 = Interrupt is not cleared 1 = Interrupt is cleared 0 = Interrupt is not cleared 1 = Interrupt is cleared reserved 0 = Interrupt is not cleared 1 = Interrupt is cleared 0 = Interrupt is not cleared 1 = Interrupt is cleared reserved 0 = Interrupt is not cleared 1 = Interrupt is cleared 0 = Interrupt is not cleared 1 = Interrupt is cleared Reserved 0 = Interrupt is not cleared 1 = Interrupt is cleared 0 = Interrupt is not cleared 1 = Interrupt is cleared 0 = Interrupt is not cleared 1 = Interrupt is cleared 0 = Interrupt is not cleared 1 = Interrupt is cleared Reserved
7.2.5 PIO Registers
7.2.5.1
PIO_IO Bit
31-16
PIO_IO
Fie ld reserved
Default R/W Description
0 R
Reserved
All Rights Reserved Copyright per DIN 34
PIO_IO Bit
15
Fie ld PIO15Dat a
14 PIO14Data
13 PIO13Data
12 PIO12Data
11 PIO11Data
10 PIO10Data
9 PIO9Data
8 PIO8Data
7 PIO7Data
6 PIO6Data
5 PIO5Data
4 PIO4Data
3 PIO3Data
2 PIO2Data
1 PIO1Data
0 PIO0Data
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Default R/W undef R/W undef R/W undef R/W undef R/W undef R/W undef R/W undef R/W undef R/W undef R/W undef R/W undef R/W undef R/W undef R/W undef R/W undef R/W undef R/W
De s cr iption read: current level of IO (regardless of PIODirection) w rite: value driven on PIO output (if PIODirection is set to output) read: current level of IO (regardless of PIODirection) w rite: value driven on PIO output (if PIODirection is set to output) read: current level of IO (regardless of PIODirection) w rite: value driven on PIO output (if PIODirection is set to output) read: current level of IO (regardless of PIODirection) w rite: value driven on PIO output (if PIODirection is set to output) read: current level of IO (regardless of PIODirection) w rite: value driven on PIO output (if PIODirection is set to output) read: current level of IO (regardless of PIODirection) w rite: value driven on PIO output (if PIODirection is set to output) read: current level of IO (regardless of PIODirection) w rite: value driven on PIO output (if PIODirection is set to output) read: current level of IO (regardless of PIODirection) w rite: value driven on PIO output (if PIODirection is set to output) read: current level of IO (regardless of PIODirection) w rite: value driven on PIO output (if PIODirection is set to output) read: current level of IO (regardless of PIODirection) w rite: value driven on PIO output (if PIODirection is set to output) read: current level of IO (regardless of PIODirection) w rite: value driven on PIO output (if PIODirection is set to output) read: current level of IO (regardless of PIODirection) w rite: value driven on PIO output (if PIODirection is set to output) read: current level of IO (regardless of PIODirection) w rite: value driven on PIO output (if PIODirection is set to output) read: current level of IO (regardless of PIODirection) w rite: value driven on PIO output (if PIODirection is set to output) read: current level of IO (regardless of PIODirection) w rite: value driven on PIO output (if PIODirection is set to output) read: current level of IO (regardless of PIODirection) w rite: value driven on PIO output (if PIODirection is set to output)
7.2.5.2 PIODirection
PIODir e ction
Bit
Fie ld
Default R/W
31-16 reserved 15 PIO15OutEn
0 R 0 R/W
14 PIO14OutEn
0 R/W
13 PIO13OutEn
0 R/W
12 PIO12OutEn
0 R/W
11 PIO11OutEn
0 R/W
10 PIO10OutEn
0 R/W
De s cr iption Reserved 0 = IO is input 1 = IO is output 0 = IO is input 1 = IO is output 0 = IO is input 1 = IO is output 0 = IO is input 1 = IO is output 0 = IO is input 1 = IO is output 0 = IO is input 1 = IO is output
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AT7991 (AGGA-4) User Manual
PIODir e ction
Bit
Fie ld
9 PIO9OutEn
8 PIO8OutEn
7 PIO7OutEn
6 PIO6OutEn
5 PIO5OutEn
4 PIO4OutEn
3 PIO3OutEn
2 PIO2OutEn
1 PIO1OutEn
0 PIO0OutEn
Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
De s cr iption 0 = IO is input 1 = IO is output 0 = IO is input 1 = IO is output 0 = IO is input 1 = IO is output 0 = IO is input 1 = IO is output 0 = IO is input 1 = IO is output 0 = IO is input 1 = IO is output 0 = IO is input 1 = IO is output 0 = IO is input 1 = IO is output 0 = IO is input 1 = IO is output 0 = IO is input 1 = IO is output
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7.2.5.3 PIOIntConfig
PIOIntConfig
Bit
Fie ld
Default R/W
31 EN3
0 R/W
30 LE3
undef R/W
29 PL3
undef R/W
28-24 ISEL3
undef R/W
23 EN2 22 LE2 21 PL2
0 R/W undef R/W undef R/W
20-16 ISEL2
undef R/W
15 EN1 14 LE1
0 R/W undef R/W
De s cr iption Enable. If set, the corresponding interrupt w ill be enabled, otherw ise it w ill be disabled
Level/edge triggered. If set, the interrupt w ill be edge-triggered, otherw ise level sensitive
Polarity. If set, the corresponding interrupt w ill be active high (or edgetriggered on positive edge). Otherw ise, it w ill be active low (or edgetriggered on negative edge)
I/O port select. The value of this field defines w hich I/O port (0 - 15) should generate parallel I/O port interrupt n. Note that I/O 16-31 are not valid.
Enable. If set, the corresponding interrupt w ill be enabled, otherw ise it w ill be disabled
Level/edge triggered. If set, the interrupt w ill be edge-triggered, otherw ise level sensitive
Polarity. If set, the corresponding interrupt w ill be active high (or edgetriggered on positive edge). Otherw ise, it w ill be active low (or edgetriggered on negative edge)
I/O port select. The value of this field defines w hich I/O port (0 - 15) should generate parallel I/O port interrupt n. Note that I/O 16-31 are not valid.
Enable. If set, the corresponding interrupt w ill be enabled, otherw ise it w ill be disabled
Level/edge triggered. If set, the interrupt w ill be edge-triggered, otherw ise level sensitive
All Rights Reserved Copyright per DIN 34
PIOIntConfig
Bit
Fie ld
13 PL1
12-8 ISEL1
7 EN0 6 LE0 5 PL0
4-0 ISEL0
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Default R/W undef R/W
undef R/W
0 R/W undef R/W undef R/W
undef R/W
De s cr iption Polarity. If set, the corresponding interrupt w ill be active high (or edgetriggered on positive edge). Otherw ise, it w ill be active low (or edgetriggered on negative edge)
I/O port select. The value of this field defines w hich I/O port (0 - 15) should generate parallel I/O port interrupt n. Note that I/O 16-31 are not valid.
Enable. If set, the corresponding interrupt w ill be enabled, otherw ise it w ill be disabled
Level/edge triggered. If set, the interrupt w ill be edge-triggered, otherw ise level sensitive
Polarity. If set, the corresponding interrupt w ill be active high (or edgetriggered on positive edge). Otherw ise, it w ill be active low (or edgetriggered on negative edge)
I/O port select. The value of this field defines w hich I/O port (0 - 15) should generate parallel I/O port interrupt n. Note that I/O 16-31 are not valid.
7.2.6 Watchdog Registers
7.2.6.1 WdogPrescale
WdogPr e s cale
Bit
Fie ld
31-16 reserved
15-0 PrescaleValue
Default R/W 0 R
65536 R/W
De s cr iption Reserved Prescaler = PrescaleValue * 4 + 2
7.2.6.2 WdogReload
WdogRe load
Bit
Fie ld
31-24 reserved
23-0 ReloadValue
De fault
R/W
0 R
0 R/W
De s cr iption Reserved
Division Ratio = ReloadValue + 1 (a ReloadValue of 0 disables the w atchdog)
7.2.6.3 WdogSel
WdogSe l
Bit
Fie ld
31-1 reserved
0 WdogSel
Default R/W 0 R 0 W
De s cr iption
Reserved
0 = AGGA reset is executed after 1st elapse of Wdog
1 = NMI interrupt is generated after 1st elapse of Wdog and AGGA reset is executed after 2nd elapse of Wdog Note: This bit is not readable. The application should cache the value in memory if needed.
7.2.6.4 WdogWriteEnable
WdogWr ite Enable
Bit
Field Default R/W
De s cr iption
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WdogWr ite Enable
Bit
Field Default R/W
31-0
0 W
De s cr iption
w rite of "0xDEADAFFE" enables a one time w rite access to either the WdogPrescale or the WdogReload register
7.2.7 Debug link (UART and SPW) Registers
7.2.7.1 DSU_UART_Status
Note: The fol l owi ng regi ster descri pti on i s onl y val i d i f the DSU i s operated vi a UART.
DSU_UART _Status (valid if DSU_SPW_EN pin = low )
Bit
Fie ld
De fault
R/W Description
31-7 reserved
0 R
Reserved
6 FE
0 R
Framing error (FE) -indicates that a framing error w as detected
5 reserved
0 R
Reserved
4 OV
0 R
(OV) - indicates that one or more character have been lost due to overrun
3 reserved 2 TH
0 R 1 R
Reserved
Transmitter hold register empty (TH) - indicates that the transmitter hold register is empty
1 TS
1 R
Transmitter shift register empty (TS) - indicates that the transmitter shift register is empty
0 DR
0 R
Data ready (DR) - indicates that new data is available in the receiver holding register
7.2.7.2 DSU_UART_SpW_Ctrl
DSU_UART _Sp W_Ctrl
Bit
Fie ld
Default R/W
31-3 reserved
0 R
2 LinkSpeed
0 R/W
1 BL
0 R/W
De s cr iption Reserved 0 = SpW link speed = 10MBits/s 1 = SpW link speed = SysClk Note: this bit is only valid if DSU SpW is enabled (pin DSU_SPW_EN = 1) Baud rate locked (BL) - is automatically set w hen the baud rate is locked
0 RE
Note: this bit is only valid if DSU UART is enabled (pin DSU_SPW_EN = 0) 0 R/W Receiver enable (RE) - if set, enables both the transmitter and receiver
Note: this bit is only valid if DSU UART is enabled (pin DSU_SPW_EN = 0)
7.2.7.3 DSU_UART_Scaler
Note: The fol l owi ng regi ster descri pti on i s onl y val i d i f the DSU i s operated vi a UART.
DSU_UART _Scaler (valid if DSU_SPW_EN pin = low )
Bit
Fie ld
De fault
R/W Description
31-14 reserved 13-0 ReloadValue
0 R 8191 R/W
Reserved
Baud Rate = SysClk / [ 8 * (ReloadValue + 1) ] or ReloadValue = SysClk / (BaudRate * 8) - 1
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7.2.8 Write Protect Registers
7.2.8.1 WriteProtectN The register description is valid for the WriteProtect1 and t he WriteProtect2 regist er (Address/Mask prot ect ion)
Wr ite Pr ote ctN
Bit
Fie ld
31 EN
30 BP
29-15 TAG 14-0 MASK
De fault
R/W
0 R/W
undef R/W
undef R/W undef R/W
De s cr iption 0 = disable w rite protect unit 1 = enable w rite protect unit 0 = segement protect mode 1 = block protect mode Address Tag. This field is compared against address(29:15) Address Mask. This field contains the address mask
7.2.8.2 WriteProtectStartAddressN
The register description is valid for the following registers: WriteProtectStartAddress3, WriteProtectStartAddress4
Wr ite Pr ote ctStar tAddr ess N
Bit
Fie ld
De fault
R/W Description
31-30 reserved
0 R
reserved
29-2 Start
undef R/W contains the first address in the protected block
1 BP
undef R/W Block Protect. If set, selects block protect mode
0 reserved
0 R
reserved
7.2.8.3 WriteProtectEndAddressN
The register description is valid for the following regist ers: WriteProtectEndAddress3, WriteProtectEndAddress4
Wr ite Pr ote ctEndAddr e s sN
Bit
Fie ld
Default R/W Description
31-30 reserved
0 R
reserved
29-2 End
undef R/W contains the last address in the protected block
1 UM
0 R/W User Mode. If set, w rite protection is enabled for user mode accesses
0 SU
0 R/W
Superuser Mode. If set, w rite protection is enabled for superuser mode accesses
7.2.9 GPIO Registers
7.2.9.1 GPIO_Status
GPIO_Status
Bit
Fie ld
31-16 reserved 15 GPIO_15
... 1 GPIO_1
0 GPIO_0
Default R/W 0 R
N/A R
De s cr iption reserved 0 = GPIO[15] is level low 1 = GPIO[15] is level high
N/A R N/A R
0 = GPIO[1] is level low 1 = GPIO[1] is level high 0 = GPIO[0] is level low 1 = GPIO[0] is level high
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7.2.9.2 GPIO_Output
GPIO_Output
Bit
Fie ld
Default R/W
31-16 reserved
0 R
15 GPIO_15
0 R/W
... 1 GPIO_1
0 R/W
0 GPIO_0
0 R/W
De s cr iption reserved 0 = GPIO[15] is assigned to level low 1 = GPIO[15] is assigned to level high
0 = GPIO[1] is assigned to level low 1 = GPIO[1] is assigned to level high 0 = GPIO[0] is assigned to level low 1 = GPIO[0] is assigned to level high
7.2.9.3 GPIO_Direction
GPIO_Dir e ction
Bit
Fie ld
31-16 reserved
15 GPIO_15
... 1 GPIO_1
0 GPIO_0
Default R/W 0 R 0 R/W
0 R/W 0 R/W
De s cr iption reserved 0 = GPIO[15] is an input 1 = GPIO[14] is an output
0 = GPIO[1] is an input 1 = GPIO[1] is an output 0 = GPIO[0] is an input 1 = GPIO[0] is an output
7.2.10 Reset and Miscellaneous Registers
7.2.10.1 ResetStatus
Re s e tStatus Bit Field 31-9 DataContainer
Default R/W all "1" R/W
De s cr iption
these bits can be used by the SW to store information over a reset (except pow er on reset). The bits are not changed by any reset, except pow er on reset. The bits are also not touched by any HW functionality.
8 MilBusTrigReset 7 GNSS_ResetHw 6 GNSS_ResetSw 5 AGGAResetSw 4 AGGAResetHw 3 WdogReset2 2 WdogReset1 1 NMI_WDOG
0 NMI_External
1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W
1 R/W
If a reset occurs, the bit is set to "0" by the hardw are.
If a reset occurs, the bit is set to "0" by the hardw are. If a reset occurs, the bit is set to "0" by the hardw are.
If a reset occurs, the bit is set to "0" by the hardw are. If a reset occurs, the bit is set to "0" by the hardw are.
If a reset occurs, the bit is set to "0" by the hardw are. If a reset occurs, the bit is set to "0" by the hardw are.
If the Watchdog triggered the NMI, the bit is set to "0" by the hardw are.
When NMI_INT pin is raised for >= 1 SysClk cycle, the bit is set to "0" by the hardw are. NMI (IRQ15) assertion requires BOTH edges (rise-fall or fall-rise) to occur w ith > 1 SysClk cycle distance.
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7.2.10.2 SWResetEnable
Sw ResetEnable
Bit
Fie ld
Default R/W Description
31-0
0 W
w rite of 0xDEADAFFE arms the softw are reset any other value w ill inhibit a softw are reset arming is granted for one w rite of Sw ResetExecute
7.2.10.3 SWResetExecute
Sw ResetExecute
Bit
Fie ld
31-0
Default R/W 0 W
De s cr iption w rite of 0xBEBECA FE executes an AGGA reset w rite of 0xCAFEBEBE executes a GNSS reset register has to be armed first by Sw ResetEnable register
7.2.10.4 MilBusRTAddress
M ilBus RTAddr e s s
Bit Field
Default R/W
31-6 reserved
0 R
5 Parity
0 R/W
4-0 RTAddress
0 R/W
De s cr iption reserved Parity for Mil Bus Remote Terminal Address Mil Bus Remote Terminal Address
7.2.10.5 AGGA4Version
AGGA4V e r s ion
Bit
Fie ld
De fault
31-0 Version
R/W 1 R
De s cr iption "1" for the AGGA4 ASIC
7.2.11 Communication Interrupt Controller Registers
7.2.11.1 CIC_Mask
CIC_M as k
Bit
Fie ld
31-13 reserved
12 MilBusNominal
(C53It)
11 MilBusReset
(C53Rst)
10 MilBusError
(C53Err)
9 SpaceWire
8 UART1_Error
7 UART1_TxDone
6 UART1_RxDone
5 UART0_Error
4 UART0_TxDone
Default R/W Description 0 R reserved 0 R/W 0 = Interrupt for Mil Bus Nominal is disabled 1 = Interrupt for Mil Bus Nominal is enabled 0 R/W 0 = Interrupt for Mil Bus Reset is disabled 1 = Interrupt for Mil Bus Reset is enabled 0 R/W 0 = Interrupt for Mil Bus Error is disabled 1 = Interrupt for Mil Bus Error is enabled 0 R/W 0 = Interrupt for SpaceWire is disabled 1 = Interrupt for SpaceWire is enabled 0 R/W 0 = Interrupt for UART1 Error is disabled 1 = Interrupt for UART1 Error is enabled 0 R/W 0 = Interrupt for UART1 Transmission Done is disabled 1 = Interrupt for UART1 Transmission Done is enabled 0 R/W 0 = Interrupt for UART1 Receive Done is disabled 1 = Interrupt for UART1 Receive Done is enabled 0 R/W 0 = Interrupt for UART0 Error is disabled 1 = Interrupt for UART0 Error is enabled 0 R/W 0 = Interrupt for UART0 Transmission Done is disabled
All Rights Reserved Copyright per DIN 34
CIC_M as k
Bit
Fie ld
3 UART0_RxDone
2 SPI
1 CRCReady
0 SGPOOverrun
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Default R/W Description 1 = Interrupt for UART0 Transmission Done is enabled
0 R/W 0 = Interrupt for UART0 Receive Done is disabled 1 = Interrupt for UART0 Receive Done is enabled
0 R/W 0 = Interrupt for SPI is disabled 1 = Interrupt for SPI is enabled
0 R/W 0 = Interrupt for CRC Ready is disabled 1 = Interrupt for CRC Ready is enabled
0 R/W 0 = Interrupt for Serial GPO Overrun is disabled 1 = Interrupt for Serial GPO Overrun is enabled
7.2.11.2 CIC_Pending
CIC_Pe nding
Bit
Fie ld
31-13 reserved
12 MILBusNominal (C53It)
11 MILBusReset (C53Rst)
10 MILBusError (C53Err)
9 SpaceWire
8 UART1_Error
7 UART1_TxDone
6 UART1_RxDone
5 UART0_Error
4 UART0_TxDone
3 UART0_RxDone
2 SPI
1 CRCReady
0 SGPOOverrun
Default R/W Description 0 R Reserved 0 R 0 = Interrupt for Mil Bus Nominal is not pending 1 = Interrupt for Mil Bus Nominal is pending 0 R 0 = Interrupt for Mil Bus Reset is not pending 1 = Interrupt for Mil Bus Reset is enabled 0 R 0 = Interrupt for Mil Bus Error is pending 1 = Interrupt for Mil Bus Error is enabled 0 R 0 = Interrupt for SpaceWire is not pending 1 = Interrupt for SpaceWire is pending 0 R 0 = Interrupt for UART1 Error is not pending 1 = Interrupt for UART1 Error is pending 0 R 0 = Interrupt for UART1 Transmission Done is not pending 1 = Interrupt for UART1 Transmission Done is pending 0 R 0 = Interrupt for UART1 Receive Done is not pending 1 = Interrupt for UART1 Receive Done is pending 0 R 0 = Interrupt for UART0 Error is not pending 1 = Interrupt for UART0 Error is pending 0 R 0 = Interrupt for UART0 Transmission Done is not pending 1 = Interrupt for UART0 Transmission Done is pending 0 R 0 = Interrupt for UART0 Receive Done is not pending 1 = Interrupt for UART0 Receive Done is pending 0 R 0 = Interrupt for SPI is not pending 1 = Interrupt for SPI is pending 0 R 0 = Interrupt for CRC Ready is not pending 1 = Interrupt for CRC Ready is pending 0 R 0 = Interrupt for Serial GPO Overrun is not pending 1 = Interrupt for Serial GPO Overrun is pending
7.2.11.3 CIC_Clear
CIC_Cle ar
Bit
Fie ld
31-13 reserved
12 reserved
11 reserved
10 reserved
9 reserved
8 UART1_Error
Default R/W Description 0 R Reserved 0 R reserved (MilBus Interrupt has to be cleared in MilBus Module) 0 R reserved (MilBus Interrupt has to be cleared in MilBus Module) 0 R reserved (MilBus Interrupt has to be cleared in MilBus Module) 0 R reserved (SpW Interrupt has to be cleared in SpW Module) 0 W 0 = Interrupt for UART1 Error is not cleared
All Rights Reserved Copyright per DIN 34
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CIC_Cle ar
Bit
Fie ld
7 UART1_TxDone
6 UART1_RxDone
5 UART0_Error
4 UART0_TxDone
3 UART0_RxDone
2 SPI
1 CRCReady
0 SGPOOverrun
Default R/W Description 1 = Interrupt for UART1 Error is cleared
0 W 0 = Interrupt for UART1 Transmission Done is not cleared 1 = Interrupt for UART1 Transmission Done is cleared
0 W 0 = Interrupt for UART1 Receive Done is not cleared 1 = Interrupt for UART1 Receive Done is cleared
0 W 0 = Interrupt for UART0 Error is not cleared 1 = Interrupt for UART0 Error is cleared
0 W 0 = Interrupt for UART0 Transmission Done is not cleared 1 = Interrupt for UART0 Transmission Done is cleared
0 W 0 = Interrupt for UART0 Receive Done is not cleared 1 = Interrupt for UART0 Receive Done is cleared
0 W 0 = Interrupt for SPI is not cleared 1 = Interrupt for SPI is cleared
0 W 0 = Interrupt for CRC Ready is not cleared 1 = Interrupt for CRC Ready is cleared
0 W 0 = Interrupt for Serial GPO Overrun is not cleared 1 = Interrupt for Serial GPO Overrun is cleared
7.2.12 SPI Registers
7.2.12.1 SPI_StatusAndCtrl
SPI_Status AndCtr l
Bit
Fie ld
Default R/W Description
31-20 reserved
0 R Reserved
19-16 DataLength
0 R/W Number of bits to be sent/received 1
The value must be betw een 8bits and 16bits
15-11 SlaveSelect
0 R/W Each bit enables the corresponding SELN line
Bit 11 corresponds to SELN0
Bit 15 corresponds to SELN4
0 = corresponding SELN line is high (deactivated)
1 = corresponding SELN line is low (activated)
10 XmtDone
1 R 0 = transmission ongoing
1 = transmission completed
9 XmtEmpty
1 R 0 = content of SPI_Tx is not transf ered to the Tx Shif ter yet
1 = content of SPI_Tx is already loaded into the TxShifter and therefore the SPI_Tx is empty and ready for new value
8 RxAvailable
0 R
0 = SPI_Rx is not ready for read
1 = SPI_Rx has received data and is ready for read. This bit is cleared by reading SPI_Rx register.
7 Ss_n_afterTx
0 R/W If set, the SPI_SEL_N signal is not deasserted betw een tw o consecutive transmissions to the same slave
6 reserved 5 TxEn 4 MsbFirst
3 ClkSel 2 ClkPhase
0 R Reserved 0 R/W 0 = SPI transmit disable
1 = SPI transmit enable 0 R/W Set order of the data transmission/reception
0 = LSB first 1 = MSB first 1 R/W 0 = Interface generates SPIClk on pin SPI_OUT_CLK 1 = Interface receives SPIClk on pin SPI_IN_CLK 0 R/W Clock phase of SPIClk in relationsihp to serial data.
All Rights Reserved Copyright per DIN 34
SPI_Status AndCtr l
Bit
Fie ld
1 ClkPol
0 RcvClkPol
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Default R/W Description 0 = data valid on the 1st SPIClk after slave select asserted 1 = data valid on the 2nd SPIClk after slave select asserted
0 R/W Master clock polarity w hen idle 0 = SPIClk is low w hen idle 1 = SPIClk is high w hen idle
0 R/W Received clock polarity. 0 = MISO data sampled on the falling edge of SPIClk 1 = MISO data sampled on the rising edge of SPIClk
7.2.12.2 SPI_ClkDivider
SPI_Clk Divide r
Bit
Fie ld
De fault
31-8 reserved
7-0 DivRatio
R/W 0 R 0 R/W
De s cr iption Reserved DivRatio = SysClk / (8 * SPIClk) - 1
7.2.12.3 SPI_Tx
SPI_Tx
Bit
Fie ld
31-16 reserved 15-0 Data
Default R/W 0 R 0 R/W
De s cr iption Reserved Data to be transmitted
7.2.12.4 SPI_Rx
SPI_Rx
Bit
Fie ld
31-16 reserved 15-0 Data
Default R/W 0 R 0 R
De s cr iption Reserved Data received
7.2.13 CRC Unit Registers
7.2.13.1 CRCLFSR
CRCLFSR
Bit
Fie ld
Default R/W
31-0
0 R/W
De s cr iption
before CRC start: w rite init value to this register af ter CRC completion: read f inal CRC value f rom this register
Note that the w ritten init value can not be read back. When reading the register it alw ays reflects the CRC result. Assuming a polynomial of order n, Bit_0 corresponds to the initial values that matches xn-1, Bit_1 corresponds to the initial values that matches xn-2, ... Unless n=32, Bits n to 31 shall be zero.
7.2.13.2 CRCPolynom
CRCPolynom
Bit Field
Default R/W
31-0
0 R/W
De s cr iption
defines the feedback taps. A set bit means feedback tap active Assuming a polynomial of order n,
All Rights Reserved Copyright per DIN 34
CRCPolynom Bit Field
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Default R/W Description Bit_0 corresponds to xn-1, Bit_1 corresponds to xn-2, ... Unless n=32, Bits n to 31 shall be zero.
7.2.13.3 CRCFinalXOR
CRCFinalXOR
Bit
Field Default
31-0
R/W 0 R/W
De s cr iption
at the end of the CRC processing, the result is XOR'd w ith CRCFina lX OR Assuming a polynomial of order n,
Bit_0 is xORed w ith Bit 0 of CRCLFSR, Bit_1 is xORed w ith bit 1 of CRCLFSR, etc. Unless n=32, Bits n to 31 shall be 0
7.2.13.4 CRCCtrl
CRCCtrl
Bit
Fie ld
31-2 reserved
1 ReverseResult
0 ReverseInData
Default R/W 0 R 0 R/W
0 R/W
De s cr iption Reserved 0 = CRC result is not reversed 1 = CRC result is reversed 0 = bytes are read from MSB to LSB (left to right) 1 = bytes are read from LSB to MSB (right to left)
7.2.13.5 CRCStartAddress
CRCStar tAddr e s s
Bit Field Default R/W
31-
0 R/W
0
De s cr iption start address of data to be processed
start address has to be 32bit aligned (bit 1:0 alw ays zero)
7.2.13.6 CRCEndAddress
CRCEndAddr e s s
Bit Field Default R/W
31-0
0 R/W
De s cr iption end address of data to be processed end address can be byte aligned DMA fetching and CRC processor w ill start w hen w riting to this register
7.2.13.7 CRCCurrentAddress
CRCCur Addr e s s
Bit
Field Default
R/W
31-0
0 R
De s cr iption current 8-bit address of data byte to be processed at the end of a CRC block: CRCCurAddress = CRCEndAddress
All Rights Reserved Copyright per DIN 34
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7.2.14 MILBUS Registers
7.2.14.1 C53CF
C53CF
Bit
Fie ld
31-28 reserved
27 DW16En
26-25 reserved 24-16 MemArea
15 Err1553Mask
Default R/W 0 R/W 0 R/W
0 R/W 0 R/W
De s cr iption Reserved
0 = 16-bit Word Size disabled 1 = 16-bit Word Size enabled Reserved
Memory area MSB: code the base address (19 LSB of Haddr at 0) of the 64Kw ords of data memory, follow ed by the 64Kw ords of BC instruction or RT command memory
0 R/W Err1553 Mask: must be at "0" to allow C53Err interrupt on 1553 error
14 ItSyncMask 13 ItTrokMask 12-8 ExtSubAd
7 WdSize 6 ExtArea 5 reserved 4 BrCstEn 3 DbcEn 2 TimeOut 1-0 Mode
0 R/W ItSync Mask: must be at "0" to allow C53It interrupt on reception of synchronise order
0 R/W ItTrok Mask: must be at "0" to allow C53It interrupt on end of a RT valid exchange
0 R/W 0 R/W
0 R/W 0 R/W 0 R/W 0 R/W
0 R/W 0 R/W
Sub-address number for Extended Memory Area mode 0 = 32bit Word Size 1 = 16bit Word Size (if DW16En is set to 1) 0 = extended memory area mode inhibited 1 = extended memory area mode activated Reserved 0 = broadcast mode disable 1 = broadcast mode enable 0 = dynamic bus control disable 1 = dynamic bus control enable 0 = 14us time out selection 1 = 31us time out selection 0 = Remote Terminal (RT) Mode 1 = reserved 2 = reserved 3 = Remote Terminal (RT) Mode
7.2.14.2 C53EMBA
C53EM BA
Bit
Fie ld
31-26 reserved
25-0 ExtMemAd
De fault
R/W
0 R
0 R
De s cr iption reserved
Base Address of the extended memory area (w ritten by 1553 link) (Word addressing)
7.2.14.3 C53CDST
C53CDST
Bit Field
Default R/W Description
31- LastCmdAd 0x10FFE R 15
Address in the 1553 memory area of the last command treated. Before any command, the value is irrelevant so the reset value is set to a value out of the command area. (Word addressing)
All Rights Reserved Copyright per DIN 34
14 ErrParAd 13-7 reserved
6 BusyFlag 5 RstSt 4-3 reserved 2 reserved 1 GoStop 0 Rst1553
7.2.14.4 C53NIT
C53NIT Bit Field
31-9 reserved 8-4 Sw itchSubAd 3 ItSw itch
2 ItDbc
1 ItSync
0 ItTrok
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0 R Set to "1" in case of RT address parity error 0 R Reserved 0 R 0 = stand by state
1 = active state 0 R 0 = reset state or initialization state
1 = active state given by BusyFlag 0 R Reserved 0 R/W Reserved 0 R/W 1553 Start Stop Command: set to "1" to activate the 1553 function
0 R/W 1553 function reset: set to "1" to reset the 1553 part
Default R/W 0 R 0 R 0 R 0 R
0 R
0 R
De s cr iption reserved Last Sub-address number w hich activated ItSw itch Not Maskable Interrupt: Set to "1" after change of data address table for a Sub-address; reset upon register read access
Not Maskable Interrupt: Dynamic bus control Command reception: set to "1" after Dynamic bus control Mode command reception in RT mode; reset upon register read access
Maskable Interrupt: Set to "1" after reception of synchronise order, if SYNC bit set in the first instruction w ord; reset upon register read access
Maskable Interrupt: Set to "1" at the end of a RT valid exchange; reset upon register read access
7.2.14.5 C53EIT
C53EIT
Bit
Fie ld
31-5 reserved
4 ErrRTAd
3 reserved 2 reserved 1 Err1553
0 ErrMem
De fault
R/W 0 R 0 R
0 R/W 0 R 0 R
0 R
De s cr iption reserved Not Maskable Interrupt : Set to 1 in case of RT address parity error; reset upon register read access
reserved reserved Maskable Interrupt: Set to "1" in case of 1553 error; reset upon register read access
Not Maskable Interrupt: Set to "1" in case of DRAM access error; reset upon register read access
7.2.14.6 C53RIT
C53RIT
Bit
Fie ld
31-1 reserved
De fault
R/W
0 R
De s cr iption reserved
All Rights Reserved Copyright per DIN 34
C53RIT
Bit
Fie ld
0 RstCom
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De fault
R/W
0 R
De s cr iption
Not maskable Interrupt: Set to "1" after reception of a valid "Reset Remote Terminal"; reset upon register read access
7.2.14.7 C53RTI
C53RTI
Bit
Fie ld
31-0 RTIndex
De fault
R/W
0 R
De s cr iption Reception Table Index Value
7.2.14.8 C53TTI
C53TTI
Bit
Fie ld
31-0 TTIndex
De fault
R/W
0 R
De s cr iption Transmission Table Index Value
7.2.15 Serial General Purpose Output (SGPO) Registers
7.2.15.1 SGPO_Tx
SGPO_Tx
Bit
Field Default
31-0
R/W 0 R/W
De s cr iption w rite: w ritten data is fed into the Tx FIFO read: w ritten data is read back
7.2.15.2 SGPO_Status
SGPO_Status
Bit Field
Default R/W
31-6 reserved
0 R
5-0 FIFOCnt
0 R
Description reserved Transmitter FIFO Count (0=empty, 16=full)
7.2.15.3 SGPO_Ctrl
SGPO_Ctrl Bit Field
Default R/W Description
31- reserved 5 4 TXEn
0 R Reserved
0 R/W 0 = transmitter disabled 1 = transmitter enabled
3 PS 2 PE
0 R/W 0 = even parity 1 = odd parity
R/W 0 = parity is disabled 1 = parity is enabled
1-0 ByteSel
0 R/W 0 = 1byte (Bit 7..0) of S-GPO-TX is transf ered to the FIFO 1 = 2bytes (Bit 15..0) of S-GPO-TX is transf ered to the FIFO 2 = 3bytes (Bit 23..0) of S-GPO-TX is transf ered to the FIFO 3 = 4bytes (Bit 31..0) of S-GPO-TX is transf ered to the FIFO
All Rights Reserved Copyright per DIN 34
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7.2.15.4 SGPO_Scaler
SGPO_Scale r
Bit
Fie ld
De fault
31-12 reserved
11-0 Scaler
R/W 0 R 0 R/W
De s cr iption reserved Scaler = SysClk / ( BaudRate * 8 ) - 1
7.2.16 UART Registers
7.2.16.1 UARTn_Tx_SAP
The regist er descript ion is valid for t he following regist ers: UART0_Tx_SAP and UART1_Tx_SAP.
UARTn_Tx_SAP
Bit
Field Default R/W Description
31-0
0 R/W start address for data transmission, 32-bit aligned
Bit 1:0 ignored at w rite, "00" at read
7.2.16.2 UARTn_Tx_EAP
The regist er descript ion is valid for t he following regist ers: UART0_Tx_EAP and UART1_Tx_EAP.
UARTn_Tx_EAP
Bit
Field Default
R/W Description
31-0
0 R/W end address for data transmission
end address is a byte address (8bit aligned)
After w rite access to this register the UART starts to read data from external memory
7.2.16.3 UARTn_Tx_CAP
The regist er descript ion is valid for t he following regist ers: UART0_Tx_CAP and UART1_Tx_CAP.
UARTn_Tx_CAP
Bit
Fie ld
De fault
R/W Description
31-0
0 R
current address for data transmission (bit 1:0 = alw ays "00")
Points to the first 32bit-w ord not yet read from memory
7.2.16.4 UARTn_Rx_SAP
The regist er descript ion is valid for t he following regist ers: UART0_Rx_SAP and UART1_Rx_SAP.
UARTn_Rx_SAP
Bit
Field Default R/W Description
31-0
0 R/W start address for data reception, 32-bit aligned (bit 1:0 ignored)
w riting to this register stops an ongoing DMA transfer
7.2.16.5 UARTn_Rx_EAP
The regist er descript ion is valid for t he following regist ers: UART0_Rx_EAP and UART1_Rx_EAP.
UARTn_Rx_ EAP
Bit Field Default
R/W Description
31-0
0 R/W end address for data reception
end address is a byte address (8bit aligned)
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UARTn_Rx_ EAP Bit Field Default
R/W Description
Note: If the EAP is not 32bit aligned, the user has to m ake sure that the residual 1..3 bytes after the EAP are not used by the softw are, since the DMA w rites zeros on these bytes.
7.2.16.6 UARTn_Rx_CAP
The regist er descript ion is valid for t he following regist ers: UART0_Rx_CAP and UART1_Rx_CAP.
UARTn_Rx_CAP
Bit
Field Default R/W Description
31-0
0 R current address for data reception
show s next free byte address for data reception
At the end of a transfer: CAP - SAP = nr. of received bytes
7.2.16.7 UARTn_Status
The regist er descript ion is valid for t he following regist ers: UART0_Status and UART1_Status.
UARTn_Status
Bit
Fie ld
Default R/W Description
31-8 reserved
0 R reserved
7 RTO
0 R Receiver time out (w hen TOE = '1')
RTO is cleared w hen RxBuffer is read or TOE=0 or RXEN=0
6 FER
0 R/W Framing Error (w rite '0' to clear)
5 PER
0 R/W Parity Error (w rite '0' to clear)
4 OVR
0 R/W Received overrrun (w rite '0' to clear)
3 BR
0 R/W Break Received (w rite '0' to clear)
2 TE
1 R Transmitter buffer empty
1 TSE
1 R Transmitter shift register empty
0 DR
0 R Data Ready. This bit is set w hen data is in the RxBuffer
7.2.16.8 UARTn_Ctrl
The regist er descript ion is valid for t he following regist ers: UART0_Ctrl and UART1_Ctrl.
UARTn_Ctrl
Bit
Fie ld
Default R/W Description
31-10 reserved
0 R reserved
9 LEND
0 R/W 0 = memory data in big endian order
1 = memory data in little endian order
8 TOE
0 R/W 0 = Timeout Function Disable
1 = Timeout Function Enable
7 LB
0 R/W 0 = internal loopback disabled
1 = internal loopback enabled
6 FL
0 R/W 0 = data flow controlled only w ith TX and RX signals
1 = data flow using CTS/RTS signals
5 PE
0 R/W 0 = parity is disabled
1 = parity is enabled
4 PS
0 R/W 0 = even parity
1 = odd parity
3 reserved
0 R reserved
All Rights Reserved Copyright per DIN 34
AT7991 (AGGA-4) User Manual
UARTn_Ctrl
Bit
Fie ld
2 reserved
1 TXEn
0 RXEn
Default R/W Description 0 R reserved 0 R/W 0 = Tx Disable 1 = Tx Enable 0 R/W 0 = Rx Disable 1 = Rx Enable
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7.2.16.9 UARTn_Scaler
The regist er descript ion is valid for t he following regist ers: UART0_Scaler and UART1_Scaler.
UARTn_Scale r
Bit
Fie ld
Default R/W Description
31-29 reserved
0 R Reserved
28-16 TimeoutCnt
8191 R/W Timeout Counter Reload Value. Counts in units of BaudTicks.
TiemoutCnt = DesiredBaudTicks 1
15-12 Reserved
0 R Reserved
11-0 ReloadValue
0 R/W Baud Rate = SysClk / [ 8 * (ReloadValue + 1) ] or ReloadValue = SysClk / (BaudRate * 8) - 1
7.2.16.10 UART_Reset
UART_Re s e t
Bit
Fie ld
Default R/W
31-1 reserved
0 R
0 Reset
0 W
De s cr iption Reserved If set, the UART Module (UART0 and UART1) is reset.
7.2.17 Clock, PLL and EEPROM Control Registers
7.2.17.1 GNSSCoreClkCtrl
GNSSCor e Clk Ctr l
Bit
Fie ld
Default R/W
31-1 reserved
0 R
0 CoreClkSel
0 R/W
De s cr iption Reserved 0 = CoreClk (internal) is taken from input pin EXT_CORE_CLK 1 = CoreClk (internal) is taken from pin HALF_SAMPLE_CLK / 2.5
7.2.17.2 MilBusClkCtrl
M ilBus Clk Ctr l
Bit
Fie ld
Default R/W Description
31-1 reserved
0 R Reserved
0 MilBusClkSel
0 R/W 0 = 1553Clk is taken from input pin EXT_MIL_CLK
1 = 1553Clk is taken from MilBus PLL output
7.2.17.3 PLLStatus
PLLStatus Bit Field 31-2 reserved
5-2 ClkDiv
Default R/W 0 R * R
De s cr iption Reserved Value set in SYS_CLK_DIV input pins
All Rights Reserved Copyright per DIN 34
PLLStatus Bit Field
1 MilBusPLLStatus
0 LeonPLLStatus
AT7991 (AGGA-4) User Manual
Default R/W 0 R
0 R
De s cr iption 0 = not locked 1 = locked 0 = not locked 1 = locked
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7.2.17.4 EEPROM_StatusAndCtrl
EEPROM _ Status AndCtr l
Bit Field
Default R/W
31-4 EEPROM_Sw itch
0 W
3 EEPROM_Enable 2 EEPROM_Reset 1 EEPROM_Pow er 0 EEPROM_On
0 R 0 R 0 R 0 R
De s cr iption 0xAFFEDEAx to sw itch EEPROM on (x = 0 .. F) 0xDEADAFFx to sw itch EEPROM off (x = 0 .. F) the status of the EEPROM_Enable signal the status of the EEPROM_Reset signal the status of the EEPROM_Pow er signal the status of the EEPROM_On signal
7.2.18 Spacewire Registers
7.2.18.1 SpWn_StatusAndCtrl
SpWn_Status AndCtr l
Bit
Fie ld
Default R/W Description
31-13 reserved
0 R Reserved
12 FCT_Err
0 R FCT Error status (reset after read)
11 ESC_Err
0 R ESC Error status (reset after read)
10 Parity_Err
0 R Parity Error status (reset after read)
9 Disconnect_Err
0 R Disconnect Error status (reset after read)
8 LinkOk
0 R Link OK status.
(this bit is reset if link error occurs or if bits 1-0 are set to "00")
7-5 reserved
0 R
4-3 TxBitRate
0 R/W Transmit bit rate selection (if bit 2 is set)
00: max. transmit bit rate, given by SysClk
01: max. transmit bit rate x 1/2
10: max. transmit bit rate x 1/4
11: max. transmit bit rate x 1/8
2 DefaultTxRate
0 R/W 0 = default transmit bit rate (10 Mbit/s, given by SpW10MHzClk)
1= transmit bit rate selected by "TxBitRate"
1 AutoStart
1 R/W 0 = no Auto Start
1 = Auto start link after a NULL token is received
0 StartStopLink
0 R/W 0 = Stop Link
1 = Start Link
7.2.18.2 SpWn_Tx_SAP
SpWn_Tx_SAP
Bit Field Default R/W Description
31-0
0 R/W start address for data transmission, 32-bit aligned
Bit 1:0 ignored at w rite, "00" at read
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7.2.18.3 SpW_Tx_EAP
SpWn_Tx_EAP
Bit
Field Default R/W
31-0
0 R/W
De s cr iption end address for data transmission After w rite access to this register SPWn starts to read data from external memory
7.2.18.4 SpWn_Tx_CAP
SpWn_Tx_CAP
Bit
Fie ld
Default R/W
31-0
0 R
De s cr iption current address for data transmission (in 32-bit steps) Points to the first 32bit w ord not yet read from memory
7.2.18.5 SpWn_Tx_Rx_Config
SpWn_Tx_Rx_Config
Bit
Fie ld
Default R/W Description
31-10 reserved
0 R reserved
9 TxLengthError 8 EEP_Received
0 R 0 R
Asserted w hen HeaderField mode is enabled (see below ) and the packet is shorter than the specified header length. (read-only, but cleared upon reading) It is set if a packet w as terminated w ith EEP (read-only, but cleared upon reading)
7-5 reserved 4 LittleEndianEnable
3 reserved 2 NoStopOnEOP
0 R 0 R/W 0 = big endian (byte 0 transported on D31-D24)
1 = little endian (byte 0 transported on D7-D0)
0 R
0 R/W if set, RX operation w ill not stop w hen an EOP or EEP is received, no EOP/EEP interrupt is generated, successive packets are concatenated.
1 HeaderField
0 R/W Header Field Control bit: If set, SpW TX interface uses the first byte of a packet as number of bytes w hich are transmitted as header bytes. The range f or the header f ield is f rom minimum 2 bytes (f irst byte + header itself) to a maximum 16 bytes. The size of header field can be 4, 8, 12 or 16 bytes. This means, that the data field starts at the next modulo 4 bytes. The rest of a 4-byte block w hich is not covered by the number of header bytes w ill not be transmitted.
0 reserved
0 R
7.2.18.6 SpWn_Rx_SAP
SpWn_Rx_SAP
Bit
Field Default R/W
31-0
0 R/W
De s cr iption start address for data reception, 32-bit aligned (bit 1:0 ignored) Writing to this register stops an ongoing DMA transfer
7.2.18.7 SpWn_Rx_EAP
SpWn_Rx_EAP
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Bit
Fie ld
31-0
Default R/W 3 R/W
De s cr iption end address for data reception bit 1:0 are alw ays "11"
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7.2.18.8 SpWn_Rx_CAP
SpWn_Rx_CAP
Bit
Field Default R/W
31-0
0 R
De s cr iption During transfer: current 32-bit address for data reception (bit 1:0 alw ays 0)
At the end of a transfer: CAP SAP = nr. of received bytes Bit 1:0 00 indicates a non 32-bit aligned packet w as received
7.2.18.9 SpW_ModuleConfig
SpW_ModuleConfig
Bit Field
Default
31-2 reserved 1 Reset 0 reserved
R/W 0 R 0 W 0 R
Description reserved If set, the Spw Module is reset.
7.2.18.10 SpW_ModuleTimeCtrl
SpW_ModuleTim eCtrl
Bit Field
Default R/W Description
31-2 reserved
0 R reserved
1 IRQ_En_All
0 R/W Enable TICK_IN interrupt for all time codes
0 IRQ_En_Valid
0 R/W Enable TICK_IN interrupt for valid time codes
7.2.18.11 SpW_ModuleTimeCode
SpW_ModuleTim eCode
Bit Field
Default R/W
31-8 reserved
0 R
7-6 Time CodeFlags
0 R/W
5-0 Time CodeValue
0 R/W
De s cr iption reserved time code flags (must be set to "00")
7.2.18.12 SpW_ModuleIntMask
SpW_M odule IntM as k
Bit
Fie ld
Default R/W
31 SPW_TickIn
0 R/W
30-29 reserved 28 SPW3_RxAreaFull
0 R 0 R/W
27 SPW3_EOP_EEP
0 R/W
26 SPW3_TxDone
0 R/W
25 SPW3_LinkConnected
0 R/W
De s cr iption 0 = Interrupt is masked 1 = Interrupt is enabled reserved 0 = Interrupt is masked 1 = Interrupt is enabled 0 = Interrupt is masked 1 = Interrupt is enabled 0 = Interrupt is masked 1 = Interrupt is enabled 0 = Interrupt is masked
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SpW_M odule IntM as k
Bit
Fie ld
24 SPW3_LinkError
23-21 reserved 20 SPW2_RxAreaFull
19 SPW2_EOP_EEP
18 SPW2_TxDone
17 SPW2_LinkConnected
16 SPW2_LinkError
15-13 reserved 12 SPW1_RxAreaFull
11 SPW1_EOP_EEP
10 SPW1_TxDone
9 SPW1_LinkConnected
8 SPW1_LinkError
7-5 reserved 4 SPW0_RxAreaFull
3 SPW0_EOP_EEP
2 SPW0_TxDone
1 SPW0_LinkConnected
0 SPW0_LinkError
Default R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
De s cr iption 1 = Interrupt is enabled 0 = Interrupt is masked 1 = Interrupt is enabled reserved 0 = Interrupt is masked 1 = Interrupt is enabled 0 = Interrupt is masked 1 = Interrupt is enabled 0 = Interrupt is masked 1 = Interrupt is enabled 0 = Interrupt is masked 1 = Interrupt is enabled 0 = Interrupt is masked 1 = Interrupt is enabled reserved 0 = Interrupt is masked 1 = Interrupt is enabled 0 = Interrupt is masked 1 = Interrupt is enabled 0 = Interrupt is masked 1 = Interrupt is enabled 0 = Interrupt is masked 1 = Interrupt is enabled 0 = Interrupt is masked 1 = Interrupt is enabled reserved 0 = Interrupt is masked 1 = Interrupt is enabled 0 = Interrupt is masked 1 = Interrupt is enabled 0 = Interrupt is masked 1 = Interrupt is enabled 0 = Interrupt is masked 1 = Interrupt is enabled 0 = Interrupt is masked 1 = Interrupt is enabled
7.2.18.13 SpW_ModuleIntStatus
SpW_M odule IntStatus
Bit
Fie ld
Default R/W
31 SPW_TickIn
0 R
30-29 reserved 28 SPW3_RxAreaFull
0 R 0 R
27 SPW3_EOP_EEP 26 SPW3_TxDone
0 R 0 R
25 SPW3_LinkConnected 24 SPW3_LinkError
0 R 0 R
23-21 reserved 20 SPW2_RxAreaFull
0 R 0 R
De s cr iption SpW Module TICK_IN
SPW3 Receive area full SPW3 EOP/EEP Received SPW3 packet is transmitted SPW3 Link is running SPW3 Link Error
SPW2 Receive area full
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SpW_M odule IntStatus
Bit
Fie ld
19 SPW2_EOP_EEP
18 SPW2_TxDone
17 SPW2_LinkConnected
16 SPW2_LinkError
15-13 reserved
12 SPW1_RxAreaFull
11 SPW1_EOP_EEP
10 SPW1_TxDone
9 SPW1_LinkConnected
8 SPW1_LinkError
7-5 reserved
4 SPW0_RxAreaFull
3 SPW0_EOP_EEP
2 SPW0_TxDone
1 SPW0_LinkConnected
0 SPW0_LinkError
Default R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R
De s cr iption SPW2 EOP/EEP Received SPW2 packet is transmitted SPW2 Link is running SPW2 Link Error
SPW1 Receive area full SPW1 EOP/EEP Received SPW1 packet is transmitted SPW1 Link is running SPW1 Link Error
SPW0 Receive area full SPW0 EOP/EEP Received SPW0 packet is transmitted SPW0 Link is running SPW0 Link Error
7.2.18.14 SpW_ModuleIntClear
SpW_M odule IntCle ar
Bit
Fie ld
Default R/W
31 SPW_TickIn
0 W
30-29 reserved 28 SPW3_RxAreaFull
0 R 0 W
27 SPW3_EOP_EEP
0 W
26 SPW3_TxDone
0 W
25 SPW3_LinkConnected
0 W
24 SPW3_LinkError
0 W
23-21 reserved 20 SPW2_RxAreaFull
0 R 0 W
19 SPW2_EOP_EEP
0 W
18 SPW2_TxDone
0 W
17 SPW2_LinkConnected
0 W
16 SPW2_LinkError
0 W
15-13 reserved 12 SPW1_RxAreaFull
0 R 0 W
11 SPW1_EOP_EEP
0 W
De s cr iption 0 = do nothing 1 = Interrupt is cleared reserved 0 = do nothing 1 = Interrupt is cleared 0 = do nothing 1 = Interrupt is cleared 0 = do nothing 1 = Interrupt is cleared 0 = do nothing 1 = Interrupt is cleared 0 = do nothing 1 = Interrupt is cleared Reserved 0 = do nothing 1 = Interrupt is cleared 0 = do nothing 1 = Interrupt is cleared 0 = do nothing 1 = Interrupt is cleared 0 = do nothing 1 = Interrupt is cleared 0 = do nothing 1 = Interrupt is cleared Reserved 0 = do nothing 1 = Interrupt is cleared 0 = do nothing 1 = Interrupt is cleared
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SpW_M odule IntCle ar
Bit
Fie ld
10 SPW1_TxDone
9 SPW1_LinkConnected
8 SPW1_LinkError
7-5 reserved 4 SPW0_RxAreaFull
3 SPW0_EOP_EEP
2 SPW0_TxDone
1 SPW0_LinkConnected
0 SPW0_LinkError
Default R/W 0 W 0 W 0 W 0 R 0 W 0 W 0 W 0 W 0 W
De s cr iption 0 = do nothing 1 = Interrupt is cleared 0 = do nothing 1 = Interrupt is cleared 0 = do nothing 1 = Interrupt is cleared Reserved 0 = do nothing 1 = Interrupt is cleared 0 = do nothing 1 = Interrupt is cleared 0 = do nothing 1 = Interrupt is cleared 0 = do nothing 1 = Interrupt is cleared 0 = do nothing 1 = Interrupt is cleared
7.3 DSU Address Map
7.3.1
DSU Overview
Address
0x90000000
0x90000004
0x90000008 0x90000010
0x90000014 0x90000018
0x9000001C 0x90010000 - 0x9001FFFC
...0 ...4
...8
...C 0x90020000 - 0x9003FFFC
0x90080000 - 0x900FFFFC 0x90080000
0x90080004 0x90080008
0x9008000C
0x90080010 0x90080014
0x90080018 0x9008001C
0x90080040 - 0x9008005C 0x90080060 - 0x9008007C
0x90100000 - 0x9013FFFC 0x90140000 - 0x9017FFFC
Register DSU_Ctrl TraceBufferCtrl TimeTagCounter AHB_BreakAddress1 AHB_Mask1 AHB_BreakAddress2 AHB_Mask2 Trace buffer Trace bits 127 - 96 Trace bits 95 - 64 Trace bits 63 - 32 Trace bits 31 - 0 IU/FPU register file IU special purpose registers Y register PSR register WIM register TBR register PC register NPC register FSR register DSU_Trap ASR16 - 23 (not implemented) ASR24 - 31 (watchpoints see 4.5) Instruction cache tags Instruction cache data
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0x90180000 - 0x901BFFFC Data cache tags 0x901C0000 - 0x901FFFFC Data cache data
7.3.1.1 DSU_Ctrl
DSU_Ctrl
Bit
Fie ld
De fault
31-29 reserved 0
28-20 DCNT
undef
19 RE
0
18 DR
0
R/W Description R reserved R/W Trace buffer delay counter (DCNT) W Reset error mode (RE) - if set, it w ill clear the error mode in the
processor
R/W Debug mode response (DR) - if set, the DSU communication link w ill send a response w ord w hen the processor enters debug mode
17 LR
16 SS
15 PE
14 EE 13 EB 12 DM
11 DE
0
0
0
DSUEN DSUBRE 0
0
R/W Link response (LR) - if set, the DSU communication link w ill send a response w ord after AHB transfer
R/W Single step (SS) - if set, the processor w ill execute one instruction and then return to debug mode
R Processor error mode (PE) - returns `1' on read w hen processor is in error mode, else `0'
R value of the external DSU_EN pin R value of the external DSU_BRE pin R 0 = processor is not in debug mode
1 = processor is in debug mode R/W Delay counter enable (DE) - if set, the trace buffer delay counter w ill
decrement for each stored trace. This bit is set automatically w hen a DSU breakpoint is hit and the delay counter is not equal to zero
10 BZ
9 BX 8 BD 7 BN 6 BS 5 BW 4 BE 3 FT
2 BT
DSUBRE
DSUBRE 0 DSUBRE 0 DSUBRE DSUBRE
R/W Break on error traps (BZ) - if set, it w ill force the processor into debug mode on all except the follow ing traps: priviledged_instruction, fpu_disabled, w indow _overflow, window_underflow , asynchronous_interrupt, ticc_trap
R/W Break on trap (BX) - if set, it w ill force the processor into debug mode w hen any trap occurs
R/W Break on DSU breakpoint (BD) - if set, it w ill force the processor to debug mode w hen a DSU breakpoint is hit
R/W Break now (BN) -If set, it w ill force processor into debug mode. If cleared, the processor w ill resume execution
R/W Break on S/W breakpoint (BS) - if set, debug mode w ill be forced w hen a breakpoint instruction (ta 1) is executed
R/W Break on IU w atch point - if set, debug mode w ill be forced on an IU w atch point (trap 0xb)
R/W Break on error (BE) - if set, it w ill force the processor to debug mode w hen the processor w ould have entered error condition (trap in trap)
0
R/W Freeze timers (FT) - if set, the scaler in the LEON timer unit w ill be
stopped during debug mode to preserve the time for the softw are
application
0
R/W Break on trace (BT) - if set, it w ill generate a DSU break condition on
trace freeze
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DSU_Ctrl
Bit
Fie ld
1 DM
0 TE
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De fault undef
0
R/W Description R/W Delay counter mode (DM). In mixed tracing mode, setting this bit w ill
cause the delay counter to decrement on AHB traces. If reset, the delay counter w ill decrement on instruction traces
R/W 0 = Trace Buffer disabled 1 = Trace Buffer enabled
7.3.1.2 TraceBufferCtrl
Trace Buffe rCtrl (!!Note that this re gis te r is not cle are d during re s et!!)
Bit
Fie ld
Default R/W Description
31-29 MFILT
undef
R/W trace only accesses from AHB masters w ith a particular master index
28-27 SFILT 26 AF
undef undef
0 = trace accesses from all masters 1 = trace only CRC module 2 = trace only SpW module 3 = trace only UART-DMA 4 = trace only GNSS DMA 5 = trace only Mil-Bus module 6 = trace only the DSU-UART 7 = trace only the CPU R/W trace only addresses w ith a certain prefix (bits 31:28) 0 = trace all slave addresses 1 = trace only APB (0x8) registers 2 = trace only GNNS (0xA) registers 3 = trace only FFT (0xB) registers R/W 0 = AHB trace buffer w ill not be frozen if processor enters debug mode
1 = AHB trace buffer w ill be frozen if processor enters debug mode
25 TA
24 TI
23-21 20-12
11-9 8-0
reserved AHBIndex reserved InstIndex
undef
undef
undef undef undef undef
R/W 0 = Trace AHB (TA) data transfer disabled
1 = Trace AHB (TA) data transfer enabled
R/W 0 = Trace Instruction (TI) disabled
1 = Trace Instruction (TI) enabled
R
reserved
R
AHB trace index counter
R
reserved
R
Instruction trace index counter
7.3.1.3 TimeTagCounter
Tim eTagCounter
Bit
Fie ld
31-30 reserved
29-0 TimeTagValue
De fault 0 n/a
R/W Description
R
reserved
R/W The DSU time tag counter is incremented each SysClk cycle as long as the processor is running. The counter is stopped w hen the processor enters debug mode, and restarted w hen execution is resumed.
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7.3.1.4 AHB_BreakAddressN
The regist er descript ion is valid for t he following regist ers: AHB_BreakAddress1, AHB_BreakAddress2
AHB_Br e ak Addr e s s N
Bit Field
Default R/W Description
31-2 BADDR
0
R/W break address
1 reserved 0
R reserved
0 EX
0
R/W 0 = no break on executed instructions
1 = break on executed instuctions
7.3.1.5 AHB_MaskN
The regist er descript ion is valid for t he following regist ers: AHB_Mask1, AHB_Mask2
AHB_M as k N
Bit Field
Default R/W Description
31-2 BMASK
0
R/W mask address for break
1 LD
0
R/W 0 = no break on load accesses
1 = break on load accesses
0 ST
0
R/W 0 = no break on store accesses
1 = break on store accesses
7.3.1.6 DSU_Trap
DSU_Trap
Bit
Fie ld
31-13 reserved
Default R/W Description
0
R
reserved
12 EM
0
R
Error mode (EM). Set if the trap w ould have cause the processor to
enter error mode
11-4 TrapType
0
R
8bit SPARC Trap Type
3-0 reserved
0
R
reserved
7.4 GNSS Address Map 7.4.1 GNSS Base Addresses
Since t he GNSS module is split into several channels and input modules, the address map is split int o base and offset addresses. The AHB base addresses for the respective channels, input modules, RAM blocks and ot her funct ions are
given in the following table. The address offsets provided in the other subsections of this chapter must be added t o t he base addresses.
Addr e s s
0xA0000000 0xA0010000 0xA0020000 0xA0030000 0xA0040000 0xA0050000 0xA0060000 0xA0070000 0xA0080000
M apping
Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Channel 8
Addr e s s
0xA1000000 0xA1010000 0xA1020000 0xA1030000 0xA1040000 0xA1050000 0xA1060000 0xA1070000 0xA1080000
M apping
RAM Channel 0 RAM Channel 1 RAM Channel 2 RAM Channel 3 RAM Channel 4 RAM Channel 5 RAM Channel 6 RAM Channel 7 RAM Channel 8
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Addr e s s
0xA0090000 0xA00A0000 0xA00B0000 0xA00C0000 0xA00D0000 0xA00E0000 0xA00F0000 0xA0100000 0xA0110000 0xA0120000 0xA0130000 0xA0140000 0xA0150000 0xA0160000 0xA0170000 0xA0180000 0xA0190000 0xA01A0000 0xA01B0000 0xA01C0000 0xA01D0000 0xA01E0000 0xA01F0000 0xA0200000 0xA0210000 0xA0220000 0xA0230000 0xA0240000
0xA0250000 0xA0260000 0xA0270000 0xA0280000 0xA0290000 0xA02A0000 0xA02B0000 0xA02C0000
M apping
Channel 9 Channel 10 Channel 11 Channel 12 Channel 13 Channel 14 Channel 15 Channel 16 Channel 17 Channel 18 Channel 19 Channel 20 Channel 21 Channel 22 Channel 23 Channel 24 Channel 25 Channel 26 Channel 27 Channel 28 Channel 29 Channel 30 Channel 31 Channel 32 Channel 33 Channel 34 Channel 35 ChannelMatrix
Input Module 0 Input Module 1 Input Module 2 Input Module 3 reserved reserved Pow er Level Detector Interrupt Registers
Addr e s s
0xA1090000 0xA10A0000 0xA10B0000 0xA10C0000 0xA10D0000 0xA10E0000 0xA10F0000 0xA1100000 0xA1110000 0xA1120000 0xA1130000 0xA1140000 0xA1150000 0xA1160000 0xA1170000 0xA1180000 0xA1190000 0xA11A0000 0xA11B0000 0xA11C0000 0xA11D0000 0xA11E0000 0xA11F0000 0xA1200000 0xA1210000 0xA1220000 0xA1230000 Other addr: 0xA1xxxxxx
M apping
RAM Channel 9 RAM Channel 10 RAM Channel 11 RAM Channel 12 RAM Channel 13 RAM Channel 14 RAM Channel 15 RAM Channel 16 RAM Channel 17 RAM Channel 18 RAM Channel 19 RAM Channel 20 RAM Channel 21 RAM Channel 22 RAM Channel 23 RAM Channel 24 RAM Channel 25 RAM Channel 26 RAM Channel 27 RAM Channel 28 RAM Channel 29 RAM Channel 30 RAM Channel 31 RAM Channel 32 RAM Channel 33 RAM Channel 34 RAM Channel 35 Reserved (access w ill lead to system lockup)
7.4.2
Input Module Registers
Address Offset + 0x00 + 0x04 + 0x08 + 0x0C + 0x10 + 0x14
Size
Name
[bits]
4 InputModuleCtrl
7 DDCMainPhaseInc
30 DDCMainFIRQuantThres
7 DDCAuxPhaseInc
30 DDCAuxFIRQuantThres
12 DACtrl
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7.4.2.1 InputModuleCtrl
InputM odule Ctr l
Bit
Fie ld
De fault
31-6 reserved
0
5 DDCAuxInSel
0
4 DDCMainInSel
0
3-2 IFCFormat
0
1-0 Mode
0
R/W R R/W R/W R/W
R/W
De s cr iption Reserved 0 = data from local Input Module is taken 1 = data from previous Input Module is taken 0 = data from local Input Module is taken 1 = data from previous Input Module is taken 0 = Sign/Magnitude 1 = Unsigned 2 = Tw o's Complement 3 = reserved 0 = Input Format Converter Mode (IFC) 1 = Real to complex Converter Mode (R2C) 2 = Digital Dow n Converter Simple Mode (DDC simple) 3 = reserved
7.4.2.2 DDCMainPhaseInc
DDCM ainPhas e Inc
Bit
Fie ld
Default R/W
31-7 reserved
0 R
6-0 Inc
0 R/W
De s cr iption
Reserved
Signed Increment for DDC I/Q Mixer NCO. New settings become effective w ith the next ME. The phase of the NCO is reset to zero w ith the next ME in order to be able to synchronize different DDC NCO's.
7.4.2.3 DDCMainFIRQuantThres
DDCM ainFIRQuantThr e s
Bit
Fie ld
Default R/W
31-30 reserved
0 R
29-20 Thres2
0 R/W
19-10 Thres1 9-0 Thres0
0 R/W 0 R/W
De s cr iption Reserved Output = +7 for Input > +Thres2 Output = -7 for Input < -Thres2 Output = +5 for "+Thres1 < Input <= +Thres2" Output = -5 for "-Thres2 <= Value < -Thres1" Output = +3 for "+Thres0 < Input <= +Thres1" Output = -3 for "-Thres1 <= Value < -Thres0" Output = +1 for "0 <= Value <= +Thres0" Output = -1 for "-Thres0 <= Input < 0"
7.4.2.4 DDCAuxPhaseInc
DDCAuxPhas e Inc
Bit
Fie ld
De fault
31-7 reserved 6-0 Inc
R/W 0 R 0 R/W
De s cr iption
Reserved
Signed Increment for DDC I/Q Mixer NCO. New settings become effective w ith the next ME. The phase of the NCO is reset to zero w ith the next ME in order to be able to synchronize different DDC NCO's.
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7.4.2.5 DDCAuxFIRQuantThres
DDCAuxFIRQu antThres
Bit
Fie ld
Default R/W
31-30 reserved
0 R
29-20 Thres2
0 R/W
19-10 Thres1 9-0 Thres0
0 R/W 0 R/W
De s cr iption Reserved Output = +7 for Input > +Thres2 Output = -7 for Input < -Thres2 Output = +5 for "+Thres1 < Input <= +Thres2" Output = -5 for "-Thres2 <= Value < -Thres1" Output = +3 for "+Thres0 < Input <= +Thres1" Output = -3 for "-Thres1 <= Value < -Thres0" Output = +1 for "0 <= Value <= +Thres0" Output = -1 for "-Thres0 <= Input < 0"
7.4.2.6 DACtrl
DACtrl
Bit
Fie ld
31-12 reserved
11-0 Value
Default R/W 0 R 0 R/W
De s cr iption Reserved Control Word for DA Converter
7.4.3 Power Level Detector Registers
Addr e s s Offs e t + 0x00 + 0x04 + 0x08 + 0x0C + 0x10 + 0x14 + 0x18 + 0x1C + 0x20 + 0x24 + 0x28 + 0x2C + 0x30 + 0x34 + 0x38 + 0x3C + 0x40 + 0x44 + 0x48 + 0x4C + 0x50 + 0x54 + 0x58 + 0x5C
Size [bits] Nam e
2 PLD5IInputSel 25 PLD5ICtrl
8 PLDIQInputSel 14 PLDIQPreAccCtr l 25 PLDIQCtrl 24 Acc5IPlusSeven 24 Acc5IPlusFive 24 Acc5IPlusThree 24 Acc5IPlusOne 24 Acc5IMinusOne 24 Acc5IMinusThree 24 Acc5IMinusFive 24 Acc5IMinusSeven 24 AccIPlusSeven 24 AccIPlusFive 24 AccIPlusThree 24 AccIPlusOne 24 AccIMinusOne 24 AccIMinusThree 24 AccIMinusFive 24 AccIMinusSeven 24 AccQPlusSeven 24 AccQPlusFive 24 AccQPlusThree
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Addr e s s Offs e t + 0x60 + 0x64
+ 0x68 + 0x6C
+ 0x70
Size [bits] Nam e
24 AccQPlusOne 24 AccQMinusOne 24 AccQMinusThree 24 AccQMinusFive 24 AccQMinusSeven
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7.4.3.1 PLD5IInputSel
PLD5IInputSe l
Bit Field
De fault
31-2 reserved
0
1-0 InputSel
0
R/W R R/W
De s cr iption Reserved 0 = Levels are measured from IM0 1 = Levels are measured from IM1 2 = Levels are measured from IM2 3 = Levels are measured from IM3 new values w ritten in in InputSel become effective w ith the next trigger (ME or acc. Samples)
7.4.3.2 PLD5ICtrl
PLD5ICtrl
Bit
Fie ld
31-25 reserved
24 SelectTrigger
23-0 AccTime
De fault 0 0
0
R/W R R/W
R/W
De s cr iption Reserved 0 = Accumulation Registers are latched after AccTime Samples 1 = Accumulation Registers are latched w ith MEO Accumulation Time in Samples
7.4.3.3 PLDIQInputSel
PLDIQInputSe l
Bit
Fie ld
De fault
31-8 reserved
0
7-6 InputSel
0
5-0 SignalSel
0
R/W R R/W
R/W
De s cr iption Reserved 0 = Input Modules after Input Format Converter 1 = Channels before Final Dow n Converter 2 = Channels after Final Dow n Converter 3 = reserved n = Input Module n or Channel n w ould be selected selections w hich do not make sense (e.g. Input Module 20) are reserved
new values w ritten in in InputSel and SignalSel become effective w ith the next trigger (ME or acc. Samples)
7.4.3.4 PLDIQPreAccCtrl
PLDIQPr e AccCtr l
Bit
Fie ld
Default R/W Description
31-14 reserved
0 R reserved
13-4 Pause
0 R/W number of cycles the preaccumulation w ill be paused
3 ReQuantFactor
0 R/W 0 = pre accumulator is requantised w ith 2^ExpFactor
All Rights Reserved Copyright per DIN 34
PLDIQPr e AccCtr l
Bit
Fie ld
2-0 ExpFactor
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De fault 0
R/W R/W
De s cr iption 1 = pre accumulator is requantised w ith 2^(2*ExpFactor) the valid range for ExpFactor is 0..5 an ExpFactor of 6..7 is reserved
7.4.3.5 PLDIQCtrl
PLDIQCtrl
Bit
Fie ld
31-25 reserved
24 SelectTrigger
23-0 AccTime
De fault 0 0
0
R/W R R/W
R/W
De s cr iption reserved 0 = Accumulation Registers are latched after AccTime Samples 1 = Accumulation Registers are latched w ith MEO Accumulation Time in Samples. If pre-accumulation is enabled, AccTime is given as the number of pre-accumulated samples.
7.4.3.6 PLD Accumulation Registers
The register description is valid for the following registers: Acc5IPlusSeven, Acc5IPlusFive, Acc5IPlusThree, Acc5IPlusOne, Acc5IMinusOne, Acc5IMinusThree, Acc5IMinusFive, Acc5IMinusSeven, AccIPlusSeven, AccIPlusFive, AccIPlusThree, AccIPlusOne, AccIMinusOne, AccIMinusThree, AccIMinusFive, AccIMinusSeven, AccQPlusSeven, AccQPlusFive, AccQPlusThree, AccQPlusOne, AccQMinusOne, AccQMinusThree, AccQMinusFive, AccQMinusSeven.
PLD Accum ulation Registers
Bit
Fie ld
Default R/W Description
31-24 reserved
0 R
reserved
23-0 Value
N/A R
Accumulated value over the measuring interval
7.4.4
Channel Matrix Registers
Address Offset + 0x00 + 0x04 + 0x08 + 0x0C + 0x10 + 0x14 + 0x18 + 0x1C + 0x20 + 0x24 + 0x28 + 0x2C + 0x30 + 0x34 + 0x38 + 0x3C + 0x40 + 0x44 + 0x48 + 0x4C
Size
Name
[bits]
32 ChActivation0
4 ChActivation1
2 DBFInputSel
27 EpochClkDiv
16 MESettings
17 PPSSettings
17 AntSwitchCtrl
4 ExtClkSettings
32 ExtClkCnt
32 ExtClkCntLatched
32 IMT_LSW
32 IMT_MSW
32 ME_IMT_LSW
32 ME_IMT_MSW
32 PPS_IMT_LSW
32 PPS_IMT_MSW
32 ASE_IMT_LSW
32 ASE_IMT_MSW
32 PLD_5I_IMT_LSW
32 PLD_5I_IMT_MSW
All Rights Reserved Copyright per DIN 34
+ 0x50 + 0x54 + 0x58 + 0x5C + 0x60
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32 PLD_IQ_IMT_LSW 32 PLD_IQ_IMT_MSW 32 AUT_IMT_LSW 32 AUT_IMT_MSW 19 TestSettings
7.4.4.1 ChActivation0
ChActivation0
Bit Field
Default R/W
31
0 R/W
...
0
0 R/W
De s cr iption 0 = Channel #31 is disabled 1 = Channel #31 is enabled ... 0 = Channel #0 is disabled 1 = Channel #0 is enabled
7.4.4.2 ChActivation1
ChActivation1
Bit
Fie ld
Default R/W
31-4 reserved
0 R
3
0 R/W
...
0
0 R/W
De s cr iption reserved 0 = Channel #35 is disabled 1 = Channel #35 is enabled ... 0 = Channel #32 is disabled 1 = Channel #32 is enabled
7.4.4.3 DBFInputSel
DBFInputSe l
Bit
Fie ld
31-2 reserved
1 DBF1Sel
Default R/W 0 R 0 R/W
0 DBF0Sel
0 R/W
De s cr iption reserved 0 = IM3 and IM2 are processed 1 = IM3 and IM1 are processed 0 = IM0 and IM1 are processed 1 = IM0 and IM2 are processed
7.4.4.4 EpochClkDiv
EpochClk Div
Bit
Fie ld
Default R/W Description
31-27 reserved 26-10 IntPart
0 R reserved 0 R/W Integer Part of Epoch Clock Divider
Epoch Clock = CoreClk / (DivRatio + 1) new settings become effective w ith the next Epoch Clock
9-0 FracPart
0 R/W fractional part of Epoch Clk Divider new settings become effective w ith the next Epoch Clock
All Rights Reserved Copyright per DIN 34
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7.4.4.5 MESettings
M ESe ttings
Bit
Fie ld
Default R/W
31-16 reserved
0 R
15 ExtInputEn
0 R/W
14 OutputEn
0 R/W
13-0 DivRatio
0 R/W
De s cr iption reserved 0 = ME is generated from local ME Divider 1 = ME is generated from MEI 0 = MEO generation is disabled 1 = MEO generation is enabled ME Clock = Epoch Clock / (DivRatio + 1) a new setting becomes effective w ith the next ME
7.4.4.6 PPSSettings
PPSSe ttings
Bit
Fie ld
Default R/W Description
31-17 reserved 16 SyncEn
0 R 0 W
reserved 0 = do nothing 1 = PPS strobe is synchronized to ME strobe once
15 ExtInputEn 14 OutputEn
0 R/W 0 = PPS is generated f rom local PPS Divider 1 = PPS is generated f rom PPSI
0 R/W 0 = PPSO generation is disabled 1 = PPSO generation is enabled
13-0 DivRatio
0 R/W PPS Clock = Epoch Clock / (DivRatio + 1) a new setting becomes effective w ith the next PPS
7.4.4.7 AntSwitchCtrl
AntSw itchCtrl
Bit
Fie ld
31-17 reserved
16-15 Sw itchID
14-11 Sw itchSequencer 10 OutputEn
9-0 DivRatio
Default R/W Description 0 R reserved 0 R ID of Ant. w hich w as active during the last AntEpoch 0 = Ant #1 1 = Ant #2 2 = Ant #3 3 = Ant #4 0 R/W each bit represents one antenna. Bit0 = Ant0, Bit1 = Ant1, ... 0 R/W 0 = ASEO generation is disabled 1 = ASEO generation is enabled 0 R/W Ant Sw itch Clock = Epoch Clock / (DivRatio + 1)
7.4.4.8 ExtClkSettings
ExtClk Se ttings
Bit
Fie ld
Default R/W Description
31-4 reserved
0 R reserved
3 LatchAtPPS
0 R/W 0 = Counter is not latched w ith PPS
1 = Counter is latched w ith PPS
2 LatchAtME
0 R/W 0 = Counter is not latched w ith ME
1 = Counter is latched w ith ME
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ExtClk Se ttings
Bit
Fie ld
1 LatchAtExtClk
0 SignalSel
Default R/W Description 0 R/W 0 = Counter is not latched w ith trigger from EXT_CLK pin 1 = Counter is latched w ith trigger from EXT_CORE_CLK pin 0 R/W 0 = Counter is running w ith EXT_CLK pin 1 = Counter is running w ith EXT_CORE_CLK pin
7.4.4.9 ExtClkCnt
ExtClk Cnt
Bit
Field Default
31-0
R/W 0 R
De s cr iption current value of External Clock Counter
7.4.4.10 ExtClkCntLatched
ExtClk CntLatche d
Bit
Field Default
R/W
31-0
0 R
De s cr iption latched value of External Clock Counter
7.4.4.11 IMT_LSW
IM T_LSW
Bit Field Default R/W Description
31-0
0 R/W Read: Current value of IMT low
Write: Preset value becoming effective w ith the next ME
7.4.4.12 IMT_MSW
IM T_M SW
Bit Field Default R/W Description
31-0
0 R/W Read: Current value of IMT high
Write: Preset value becoming effective w ith the next ME
7.4.4.13 ME_IMT_LSW
M E_IM T_LSW
Bit
Fie ld
De fault
31-0
R/W 0 R
De s cr iption value of IMT low at ME time instance
7.4.4.14 ME_IMT_MSW
M E_IM T_M SW
Bit
Field Default
31-0
R/W 0 R
De s cr iption value of IMT high at ME time instance
7.4.4.15 PPS_IMT_LSW
PPS_IM T_LSW
Bit
Field Default
R/W
31-0
0 R
De s cr iption value of IMT low at PPS time instance
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7.4.4.16 PPS_IMT_MSW
PPS_IM T_M SW
Bit
Field Default
R/W
31-0
0 R
De s cr iption value of IMT high at PPS time instance
7.4.4.17 ASE_IMT_LSW
ASE_IM T_LSW
Bit
Field Default
R/W
31-0
0 R
De s cr iption value of IMT low at ASE time instance
7.4.4.18 ASE_IMT_MSW
ASE_IM T_M SW
Bit
Field Default
R/W
31-0
0 R
De s cr iption value of IMT high at ASE time instance
7.4.4.19 PLD_5I_IMT_LSW
PLD_5I_IM T_LSW
Bit
Field Default
R/W
31-0
0 R
De s cr iption value of IMT low at PLD 5I time instance
7.4.4.20 PLD_5I_IMT_MSW
PLD_5I_IM T_M SW
Bit
Field Default
R/W
31-0
0 R
De s cr iption value of IMT high at PLD 5I time instance
7.4.4.21 PLD_IQ_IMT_LSW
PLD_IQ_IM T_LSW
Bit
Field Default
R/W
31-0
0 R
De s cr iption value of IMT low at PLD IQ time instance
7.4.4.22 PLD_IQ_IMT_MSW
PLD_IQ_IM T_M SW
Bit
Field Default
R/W
31-0
0 R
De s cr iption value of IMT high at PLD IQ time instance
7.4.4.23 AUT_IMT_LSW
AUT_IM T_LSW
Bit
Field Default R/W
31-0
0 R
De s cr iption value of IMT low at AUT (Aiding Unit Trigger) time instance
All Rights Reserved Copyright per DIN 34
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7.4.4.24 AUT_IMT_MSW
AUT_IM T_M SW
Bit
Field Default R/W
31-0
0 R
De s cr iption value of IMT high at AUT (Aiding Unit Trigger) time instance
7.4.4.25 TestSettings
Te s tSe ttings
Bit
Fie ld
31-19 reserved 18-13 CodeOut2Sel
12-7 CodeOut1Sel
6 SignalOutPosSel 5-0 SignalOutChanSel
Default R/W 0 R
63 R/W
63 R/W
1 R/W 63 R/W
De s cr iption reserved 0 = PRN Code and IntEpoch of channel 0 is output 1 = PRN Code and IntEpoch of channel 1 is output ... 35 = PRN Code and IntEpoch of channel 35 is output 36..63 sw itches CODE_OUT2[1:0] to ground (saves pow er, since pins are not toggling)
0 = PRN Code and IntEpoch of channel 0 is output 1 = PRN Code and IntEpoch of channel 1 is output ... 35 = PRN Code and IntEpoch of channel 35 is output 36..63 sw itches CODE_OUT1[1:0] to ground (saves pow er, since pins are not toggling)
0 = Signal before FDC is output 1 = Signal after FDC is output 0 = Input Data of channel 0 before/after FDC is output 1 = Input Data of channel 1 before/after FDC is output ... 35 = Input Data of channel 35 before/after FDC is output 36..63 sw itches SIGNAL_OUT_I[2:0] and SIGNAL_OUT_Q[2:0] to ground (saves pow er, since pins are not toggling)
7.4.5 Channel Registers
Addr e s s Offs e t + 0x000 + 0x004 + 0x008 + 0x00C + 0x010 + 0x014 + 0x018 + 0x01C + 0x020 + 0x024 + 0x028 + 0x02C + 0x030 + 0x034
Size [bits] Nam e
9 ChannelCtrl 32 CarrSw Freq 32 CarrSw Shift 32 CodeSw Freq 32 CodeSw Shift 27 NCOSettings 20 CodeGenUnitCtr l 28 PrimCodeRam1Ctr l 26 PrimCodeRam2Ctr l 28 SecCodeRam1Ctrl 28 SecCodeRam2Ctrl 28 VFCGExtTaps 28 VFCGInit 28 VFCGLength
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+ 0x038 + 0x03C + 0x040 + 0x044 + 0x048 + 0x04C + 0x050 + 0x054 + 0x058 + 0x05C + 0x060 + 0x064 + 0x068 + 0x06C + 0x070 + 0x074 + 0x078 + 0x07C + 0x080 + 0x084 + 0x088 + 0x08C + 0x090 + 0x094 + 0x098 + 0x09C + 0x0A0 + 0x0A4 + 0x0A8 + 0x0AC + 0x0B0 + 0x0B4 ... + 0x800 + 0x804 + 0x808 + 0x80C
31 DelayLineCtrl 19 CorrUnitCtrl 29 IntCountCtrl 32 ContCntOffset 22 AidingUnitCtrl 32 CarrAidFreq 24 CarrAidAcc 25 CodeAidFreq 17 CodeAidAcc 16 LoopState 32 IE_IMT_LSW 29 IE_ValueEE_I 29 IE_ValueEE_Q 29 IE_ValueE_I 29 IE_ValueE_Q 29 IE_ValueP_I 29 IE_ValueP_Q 29 IE_ValueL_I 29 IE_ValueL_Q 29 IE_ValueLL_I 29 IE_ValueLL_Q 32 DataCollect 32 IE_CodeFreq 32 IE_CarrFreq 32 IE_CarrObs Phase 32 IE_ContCount 32 IE_CodePhase 32 ME_IMT_LSW 32 ME_CarrObs Phase 21 ME_IntCount 32 ME_ContCount 32 ME_CodePhase
23 GNSS_DMACtr l 32 GNSS_DMAStartAddr 32 GNSS_DMA EndAddr 32 GNSS_DMACurAddr
7.4.5.1 ChannelCtrl
Channe lCtr l
Bit
Fie ld
Default R/W Description
31-9 reserved
0 R reserved
8 TimeBaseSel
0 R/W 0 = PPS, ME and ASE from local channel
1 = PPS, ME and ASE from previous channel (slaving)
7 IntEpochSel
0 R/W 0 = IE and LE f rom local channel
1 = IE and LE f rom previous channel (slaving)
6 CodeSel
0 R/W 0 = Code NCO signal f rom local channel
1 = Code NCO signal f rom previous channel (slaving)
5 CarrSel
0 R/W 0 = Carrier NCO signal from local channel
1 = Carrier NCO signal from previous channel (slaving)
All Rights Reserved Copyright per DIN 34
Channe lCtr l
Bit
Fie ld
4-0 InputSel
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Default R/W Description 0 R/W 0 = first bypass of DBF0 (IM 0) 1 = second bypass of DBF0 (IM 1/2) 2 = first bypass of DBF1 (IM 2/1) 3 = second bypass of DBF1 (IM 3) 4 = reserved 5 = reserved 6 = IM0 DDCaux 7 = IM1 DDCaux 8 = IM2 DDCaux 9 = IM3 DDCaux 10 = reserved 11 = reserved 12 = data from previous channel (slaving) 13 = data from DBF0 (-135°) 14 = data from DBF0 (-90°) 15 = data from DBF0 (-45°) 16 = data from DBF0 (-0°) 17 = data from DBF0 (+45°) 18 = data from DBF0 (+90°) 19 = data from DBF0 (+135°) 20 = data from DBF1 (-135°) 21 = data from DBF1 (-90°) 22 = data from DBF1 (-45°) 23 = data from DBF1 (-0°) 24 = data from DBF1 (+45°) 25 = data from DBF1 (+90°) 26 = data from DBF1 (+135°) 27 - 31 = reserved
7.4.5.2 CarrSwFreq
CarrSw Freq
Bit
Field Default
31-0
R/W 0 R/W
De s cr iption
Signed Carrier NCO Phase Increment (softw are part, not including the aiding part)
7.4.5.3 CarrSwShift
CarrSw Shift
Bit
Field Default
31-0
R/W 0 R/W
De s cr iption Write: Signed Carrier NCO Phase Increment w hich is added once to the Carrier NCO
Read: Current Carrier NCO Phase (signed value)
7.4.5.4 CodeSwFreq
CodeSw Freq
Bit
Field Default
31-0
R/W Description
0 R/W Unsigned Code NCO Phase Increment (softw are part, not including the aiding part)
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7.4.5.5 CodeSwShift
CodeSw Shift
Bit
Field Default
31-0
R/W Description
0 R/W Write: Signed Code NCO Phase Increment w hich is added to the Code NCO once or repeatedly (softw are part, not including the aiding part)
Read: Unsigned Current Code NCO Phase
7.4.5.6 NCOSettings
NCOSe ttings
Bit
Fie ld
31-27 reserved
26-5 CodeSw ShiftSteps
4-3 CodeSw ShiftMode
2 CodeSw FreqMode
1 CarrSw ShiftMode 0 CarrSw FreqMode
De fault 0 0 0
0
R/W R R/W R/W
R/W
De s cr iption reserved
number of shift steps 0 = new value becomes effective w ith next IE 1 = new value becomes ef f ective immediately 2 = new value becomes effective repeated w ith every IE 3 = reserved
0 = new value becomes effective w ith next IE 1 = new value becomes ef f ective immediately Note: In order to get the channel running from its reset state or if the Code NCO Frequency is set to zero during operation it is necessary to set this bit to immediate mode until the Code NCO is running.
Otherw ise there is a deadlock per definition. If the Code NCO frequency is zero there w ill never be an integration epoch and therefore also no new Code NCO values w ould become efefctive, since no integration epoch w ould occur.
0 R/W 0 = new value becomes effective w ith next IE 1 = new value becomes ef f ective immediately
0 R/W 0 = new value becomes effective w ith next IE 1 = new value becomes effective immediately
7.4.5.7 CodeGenUnitCtrl
Code Ge nUnitCtr l
Bit
Fie ld
De fault
31-20 reserved
0
19 CodeRamSel
0
18 BOCCosEn
0
17 BOCEffective
0
16-13 BOCDivider
0
12-11 BOCPattern
0
10 GPSL2CEn
0
R/W R R/W
R/W
R/W R/W R/W R/W
De s cr iption reserved 0 = CM1 is routed to output1, CM2 is routed to output2. If coupled output is routed to output 1
1 = CM1 is routed to output2, CM2 is routed to output1. If coupled output is routed to output 2
0 = BOC sine is selected 1 = BOC cosine is selected 0 = BOCDivider + BOCPattern becomes effective w ith next IE 1 = BOC Divider + BOCPattern becomes ef f ective immediately Primary Rate = NCO Rate / (BOCDivider + 1) BOC Pattern or L2C Enable/Disable Control 0 = do nothing
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Code Ge nUnitCtr l
Bit
Fie ld
9 GPSL5En
De fault 0
R/W R/W
De s cr iption 1 = BOC register output is routed to Output 2
0 = shift reg.1 is reloaded w hen length counter1 has elapsed, shift reg2 is reloaded w hen length counter2 has elapsed
1 = shift reg.1 is reloaded w hen length counter1 has elapsed, shift reg1 and reg2 are reloaded w hen length counter2 has elapsed
8 VFCGLongEn 7 ResetSCM2 6 ResetSCM1 5 StartCM2 4 StartCM1 3 StartVFCG 2-1 StartOfEpochSel
0 Trigger
0 R/W 0 = VFCG uses 2x14 bit shift registers 1 = VFCG uses 1x28 bit shift register
0 W 0 = do nothing (w rite only) 1 = SCM2 starts reading from offset w ith next StartOfEpoch
0 W 0 = do nothing (w rite only) 1 = SCM1 starts reading from offset w ith next StartOfEpoch
0 W 0 = do nothing (w rite only) 1 = start CM2 w ith next Trigger
0 W 0 = do nothing (w rite only) 1 = start CM1 w ith next Trigger
0 W 0 = do nothing (w rite only) 1 = start VFCG w ith next Trigger (executed only once)
0 R/W 0 = shift register 1 of VFCG 1 = shift register 2 of VFCG 2 = primary code memory 1 3 = primary code memory 2
0 R/W 0 = next Integration Epoch 1 = next Measurement Epoch
7.4.5.8 PrimCodeRam1Ctrl
Prim CodeRam 1Ctrl
Bit
Fie ld
Default R/W
31-28 reserved
0 R
27-14 Offset
0 R/W
De s cr iption reserved
at next Trigger, the primary RAM is read from Offset The Offset value is only applied once if the StartCM bit is set E.g. a programmed offset value of 1 causes the CG to start w ith Chip Nr.2. Note that the offset value alw ays has to be smaller or equal than the length value. Otherw ise the output of the Code Generator is invalid.
13-0 Length
0 R/W length of the primary code - 1
7.4.5.9 PrimCodeRam2Ctrl
PrimCodeRam2Ctrl
Bit Field Default R/W Description
31- reserved 26 25- Offset 13
0 R reserved 0 R/W at next Trigger, the primary RAM is read from Offset
The Offset value is only applied once if the StartCM bit is set
All Rights Reserved Copyright per DIN 34
12-0 Length
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E.g. a programmed offset value of 1 causes the CG to start with Chip Nr.2. Note that the offset value always has to be smaller or equal than the length value. Otherwise the output of the Code Generator is invalid.
0 R/W length of the primary code - 1
7.4.5.10 SecCodeRam1Ctrl
SecCodeRam 1Ctrl
Bit
Fie ld
Default R/W
31-28 reserved 27-14 Divider
0 R 0 R/W
13-7 Offset
0 R/W
De s cr iption
reserved secondary code rate = primary code rate / (Divider +1)
w rite: at next StartofEpoch the sec. RAM is read from Offset E.g. a programmed offset value of 1 causes the Secondary Code to start w ith Chip Nr.2. Note that the offset value alw ays has to be smaller or equal than the length value. Otherw ise the output of the Secondary Code is invalid.
6-0 Length
0 R/W
read: returns the current position of the secondary code pointer length of the secondary code - 1 A value of 0 deactivates the secondary code memory.
7.4.5.11 SecCodeRam2Ctrl
SecCodeRam 2Ctrl
Bit
Fie ld
Default R/W
31-28 reserved
0 R
27-14 Divider
0 R/W
13-7 Offset
0 R/W
De s cr iption reserved
secondary code rate = primary code rate / (Divider +1) w rite: at next StartOfEpoch the sec. RAM is read from Offset E.g. a programmed offset value of 1 causes the Secondary Code to start w ith Chip Nr.2. Note that the offset value alw ays has to be smaller or equal than the length value. Otherw ise the output of the Secondary Code is invalid.
6-0 Length
0 R/W
read: returns the current position of the secondary code pointer length of the secondary code - 1 A value of 0 deactivates the secondary code memory.
7.4.5.12 VFCGExtTaps
VFCGExtTaps
Bit
Fie ld
De fault
31-28 reserved
27-14 HighPart
13-0 Low Part
R/W 0 R 0 R/W 0 R/W
De s cr iption reserved upper 14 feedback taps (Polynom-2) low er 14 feedback taps (Polynom-1)
7.4.5.13 VFCGInit
VFCGInit
Bit
Fie ld
31-28 reserved
27-14 HighPart
De fault
R/W 0 R 0 R/W
De s cr iption reserved init of upper 14 taps (init LFSR-2)
All Rights Reserved Copyright per DIN 34
VFCGInit Bit
13-0
Fie ld Low Part
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De fault
R/W
0 R/W
De s cr iption init of low er 14 taps (init LFSR-1)
7.4.5.14 VFCGLength
V FCGLe ngth
Bit
Fie ld
Default R/W
31-28 reserved
0 R
27-14 HighPart
0 R/W
13-0 Low Part
0 R/W
De s cr iption reserved length of upper PRN sequence (LFSR-2 length) length of low er PRN sequence (LFSR-1 Length)
7.4.5.15 DelayLineCtrl
De layLine Ctr l
Bit
Fie ld
Default R/W Description
31 reserved
0 R
reserved
30-26 SpacingLL
0 R/W SpacingLL = Delay Line Spacing from L to LL in taps-1
SpacingLL 0 = 1 tap delay
SpacingLL 1 = 2 taps delay
...
SpacingLL 21 = 22 taps delay
SpacingLL 22..31 = reserved
The Spacing becomes effective w ith the next integration epoch
25-21 SpacingL
0 R/W SpacingL = Delay Line Spacing f rom P to L in taps-1
20-16 SpacingP
0 R/W SpacingP = Delay Line Spacing from E to P in taps-1
15-11 SpacingE
0 R/W SpacingE = Delay Line Spacing from EE to E in taps-1
10-6 SpacingEE
0 R/W SpacingEE = Delay Line Spacing f rom Code In to EE in taps-1
5 CodeSw ap
0 R/W 0 = Code1 goes through DL1, Code2 goes through DL2
1 = Code1 goes through DL2, Code2 goes through DL1
4 ClkSel
0 R/W 0 = local delay line clock is used
1 = delay line clock from previous channel is used
3 CodeOutSel
0 R/W 0 = CodeOut equals CodeIn (bypass mode)
1 = Code Out equals Output LL from local Delay Line
2 CodeInSel
0 R/W 0 = Code from local Code Generator Unit is used
1 = Code from previous channel is used
1-0 DivRatio
0 R/W Delay Line Clock = CoreClk / (DivRatio + 1)
new settings become effective w ith the next IE
7.4.5.16 CorrUnitCtrl
CorrUnitCtrl
Bit
Fie ld
31-19 reserved
18 IntSourceSel
17 LongEpochReady 16 DataCollectReady
Default R/W Description
0 R reserved
0 R/W 0 = DMA and GIC is triggered by IE
1 = DMA and GIC is triggered by LE
new settings become ef f ective immediately
0 R
if the bit is set new LE values are available. It is cleared w ith the next IE.
0 R
if the bit is set, new data is available in the DataCollect register the bit is cleared if the register DataCollect is read
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CorrUnitCtrl
Bit
Fie ld
15 IE_CarrObsSel
14 ME_CarrObsSel
13 CodeFreqSel
12 CarrFreqSel
11 ResetDataCollect
10-6 DataCollectLength 5-4 CDLSel
3 IQSel 2 ASEEn 1 LongEpochLLQ 0 ResetAtStartofEpoch
De fault 0 0 0 0 0 0 0
0 0 0 0
R/W R/W R/W R/W R/W W R/W R/W
R/W R/W R/W W
De s cr iption 0 = IE_CarrObs register contains phase MSB's and cycle cnt 1 = IE_CarrObs register contains only phase 0 = ME_CarrObs register contains phase MSB's and cycle cnt 1 = ME_CarrObs register contains only phase 0 = IE_CodeFreq Observable does include aiding component 1 = IE_CodeFreq Observable does not include aiding component 0 = IE_CarrFreq Observable does include aiding component 1 = IE_CarrFreq Observable does not include aiding component 0 = do nothing 1 = the Data Collect Register&Counter is cleared at next IE DataCollectLength = Bits to collect - 1 0 = LL-Q correlates w ith the LL replica of the Delay Line 1 1 = LL-Q correlates w ith the punctual replica of Delay Line 1 2 = LL-Q correlates w ith the punctual replica of Delay Line 2 3 = LL-Q correlates w ith P of DL1 and P-inverse of DL2 0 = LL-Q correlates w ith the incoming Q-path 1 = LL-Q correlates w ith the incoming I-path 0 = do nothing 1 = accumulators are w orking w ith ASE instead of IE 0 = all correlators are integrating over the same time period (IE) 1 = LL-Q integrates w ith IE, all other correlators w ith LongEpoch 0 = do nothing 1 = Reset IntCount and Accumulators w ith next Start of Epoch (executed only once)
7.4.5.17 IntCountCtrl
IntCountCtrl
Bit
Fie ld
31-29 reserved
28-21 LongEpochDiv
20-0 AccLength
Default R/W Description 0 R reserved
0 R/W Long Epoch = IntEpoch / (LongEpochDiv + 1) 0 R/W Accumulation length in BOC Rate cycles - 1. New w ritten value
becomes effective w ith the next IE
7.4.5.18 ContCntOffset
ContCntOffs e t
Bit Field Default R/W
31-0
0 R/W
De s cr iption offset is added once w ith the next integration epoch
7.4.5.19 AidingUnitCtrl
AidingUnitCtrl
Bit
Fie ld
De fault
31-23 reserved
0
22-21 TriggerSel
0
R/W R R/W
De s cr iption reserved
0 = Written parameters become effective w ith the next MEO 1 = Written parameters become effective w ith the next PPS 2 = Written parameters become effective w ith the next rising edge of the AU_TRIGGER pin
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AidingUnitCtrl
Bit
Fie ld
20 CodeAidEn
19 CarrAidEn
18-0 DivRatio
De fault 0 0 0
R/W R/W R/W R/W
De s cr iption 3 = reserved 0 = Code Aiding Unit disabled (becomes ef f ective at next IE) 1 = Code Aiding Unit enabled (becomes ef f ective at next IE) 0 = Carrier Aiding Unit disabled (becomes ef f ective at next IE) 1 = Carrier Aiding Unit enabled (becomes ef f ective at next IE) AidClk = CoreClk / (DivRatio + 1)
7.4.5.20 CarrAidFreq
Car r AidFr e q
Bit Field Default R/W
31-0
0 R/W
De s cr iption
Carrier Aiding Frequency (Doppler)
Note that the CarrAidFreq register has 38bit internally. Therefore the 6 LSB's are cleared if the upper 32bit are w ritten by the softw are. Read this register returns the 32-MSB of current value of the Frequency generated in the Aiding Unit.
7.4.5.21 CarrAidAcc
CarrAidAcc
Bit
Fie ld
31-24 reserved
23-0 Value
De fault
R/W 0 R 0 R/W
De s cr iption
reserved Carrier Aiding Acceleration (Doppler Rate) Read this register returns the current ef f ective value
7.4.5.22 CodeAidFreq
CodeAidFreq Bit Field
31-25 reserved
Default R/W Description 0 R reserved
24-0 Value
0 R/W
Code Aiding Frequency (Doppler)
Note that the CodeAidFreq register has 31bit internally. Therefore the 6 LSB's are cleared if the upper 25bit are written by the software Read this register returns the 25-MSB of current value of the Frequency generated in the Aiding Unit.
7.4.5.23 CodeAidAcc
CodeAidAcc
Bit
Field
31-17 reserved
Default R/W 0 R
16-0 Value
0 R/W
Description reserved
Code Aiding Acceleration (Doppler Rate) Read this register returns the current effective value
7.4.5.24 LoopState
LoopState
All Rights Reserved Copyright per DIN 34
Bit 31-16 15-0
Fie ld reserved Value
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De fault
R/W
0 R
0 R/W
De s cr iption reserved
This register has no influence on the hardw are and can be freely programmed
7.4.5.25 IE_IMT_LSW
IE_IM T_LSW
Bit
Field Default
R/W
31-0
N/A R
De s cr iption value of IMT low at Int Epoch time instance
7.4.5.26 IE_ValueEE_I
IE_ValueEE_I
Bit
Field
31-29 reserved
28-0
Default R/W N/A R N/A R
Description
Sign Extension Note that the sign bit (Bit28) is also copied to Bit 31-29. Therefore the software doesn't have to shift after reading.
7.4.5.27 IE_ValueEE_Q
IE_ValueEE_Q
Bit
Field
31-29 reserved
Default R/W N/A R
28-0
N/A R
Description Sign Extension
Note that the sign bit (Bit28) is also copied to Bit 31-29. Therefore the software doesn't have to shift after reading.
7.4.5.28 IE_ValueE_I
IE_ValueE_I
Bit
Field
31-29 reserved
28-0
Default R/W N/A R N/A R
Description
Sign Extension Note that the sign bit (Bit28) is also copied to Bit 31-29. Therefore the software doesn't have to shift after reading.
7.4.5.29 IE_ValueE_Q
IE_ValueE_Q
Bit
Field
31-29 reserved
Default R/W N/A R
28-0
N/A R
Description Sign Extension
Note that the sign bit (Bit28) is also copied to Bit 31-29. Therefore the software doesn't have to shift after reading.
7.4.5.30 IE_ValueP_I
IE_ValueP_I
Bit
Field
31-29 reserved
Default R/W N/A R
Description Sign Extension
All Rights Reserved Copyright per DIN 34
28-0
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N/A R
Note that the sign bit (Bit28) is also copied to Bit 31-29. Therefore the software doesn't have to shift after reading.
7.4.5.31 IE_ValueP_Q
IE_ValueP_Q
Bit
Field
Default R/W
31-29 reserved
N/A R
28-0
N/A R
Description Sign Extension
Note that the sign bit (Bit28) is also copied to Bit 31-29. Therefore the software doesn't have to shift after reading.
7.4.5.32 IE_ValueL_I
IE_ValueL_I
Bit
Field
Default R/W
31-29 reserved 28-0
N/A R N/A R
Description
Sign Extension Note that the sign bit (Bit28) is also copied to Bit 31-29. Therefore the software doesn't have to shift after reading.
7.4.5.33 IE_ValueL_Q
IE_ValueL_Q
Bit
Field
Default R/W
31-29 reserved
N/A R
28-0
N/A R
Description Sign Extension
Note that the sign bit (Bit28) is also copied to Bit 31-29. Therefore the software doesn't have to shift after reading.
7.4.5.34 IE_ValueLL_I
IE_ValueLL_I
Bit
Field
Default R/W
31-29 reserved 28-0
N/A R N/A R
Description
Sign Extension Note that the sign bit (Bit28) is also copied to Bit 31-29. Therefore the software doesn't have to shift after reading.
7.4.5.35 IE_ValueLL_Q
IE_ValueLL_Q
Bit
Field
Default R/W
31-29 reserved
N/A R
28-0
N/A R
Description Sign Extension
Note that the sign bit (Bit28) is also copied to Bit 31-29. Therefore the software doesn't have to shift after reading.
7.4.5.36 DataCollect
DataColle ct
Bit
Field Default
R/W
31-0
0 R (*)
De s cr iption
contains the raw symbols of the navigation message (*) w riting to this register only clears the DataCollectReady bit in the CorrUnitCtrl register
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7.4.5.37 IE_CodeFreq
IE_Code Fr e q
Bit
Field Default R/W
31-0
0 R
De s cr iption If CodeFreqSel=0 then IE_CodeFreq=CodeSw Freq+CodeAidFreq If CodeFreqSel=1 then IE_CodeFreq=CodeSw Freq
7.4.5.38 IE_CarrFreq
IE_Car r Fr e q
Bit
Field Default R/W
31-0
0 R
De s cr iption If CarrFreqSel=0 then IE_CarrFreq=CarrSw Freq+CarrAidFreq If CarrFreqSel=1 then IE_CarrFreq=CarrSw Freq
7.4.5.39 IE_CarrObsPhase
IE_Car r Obs Phas e
Bit
Fie ld
Default R/W Description
31-12 CycleCnt/Phase
0 R Carrier Cycle Count (if IE_CarrObsSel = 0)
20 MSB's of Carrier Phase (if IE_CarrObsSel = 1)
11-0 Phase
0 R 12 MSB's of Carrier Phase (if IE_CarrObsSel = 0)
12 LSB's of Carrier Phase (if IE_CarrObsSel = 1)
7.4.5.40 IE_ContCount
IE_ContCount
Bit
Field Default
R/W
31-0
0 R
De s cr iption 32bit continuous counter at Integration Epoch
7.4.5.41 IE_CodePhase
IE_Code Phas e
Bit
Fie ld
De fault
31-0
R/W 0 R
De s cr iption Code Phase at Integration Epoch
7.4.5.42 ME_IMT_LSW
M E_IM T_LSW
Bit
Fie ld
De fault
31-0
R/W 0 R
De s cr iption value of IMT low at ME time instance
7.4.5.43 ME_CarrObsPhase
M E_Car r Obs Phas e
Bit
Fie ld
Default R/W Description
31- CycleCnt/Phase 12
0 R
Carrier Cycle Count (if ME_CarrObs Sel = 0) 20 MSB's of Carrier Phase (if ME_CarrObs Sel = 1)
11-0 Phase
0 R 12 MSB's of Carrier Phase (if ME_CarrObs Sel = 0)
12 LSB's of Carrier Phase (if ME_CarrObsSel = 1)
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7.4.5.44 ME_IntCount
M E_IntCount
Bit
Fie ld
Default R/W
31-21 reserved
0 R
20-0 Value
0 R
De s cr iption reserved 21bit Integration Count at Measurement Epoch
7.4.5.45 ME_ContCount
M E_ContCount
Bit Field Default
R/W
31-0
0 R
De s cr iption 32bit Continuous Count at Measurement Epoch
7.4.5.46 ME_CodePhase
M E_Code Phas e
Bit
Field Default
R/W
31-0
0 R
De s cr iption 32bit Code Phase at Measurement Epoch
7.4.5.47 GNSS DMA Ctrl
GNSS_DM ACtr l
Bit
Fie ld
31-23 reserved
22 ME_CodePhase
21 ME_ContCount
20 ME_IntCount
19 ME_CarrObs/Phase
18 ME_IMT_LSW
17 IE_CodePhase
16 IE_ContCount
15 IE_CarrierObs/Phase
14 IE_CarrFreq
13 IE_CodeFreq
12 DataCollect
11 IE_ValueLL_Q
10 IE_ValueLL_I
9 IE_ValueL_Q
Default R/W 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
De s cr iption reserved 0 = transfer of this observable disabled 1 = transfer of this observable enabled 0 = transfer of this observable disabled 1 = transfer of this observable enabled 0 = transfer of this observable disabled 1 = transfer of this observable enabled 0 = transfer of this observable disabled 1 = transfer of this observable enabled 0 = transfer of this observable disabled 1 = transfer of this observable enabled 0 = transfer of this observable disabled 1 = transfer of this observable enabled 0 = transfer of this observable disabled 1 = transfer of this observable enabled 0 = transfer of this observable disabled 1 = transfer of this observable enabled 0 = transfer of this observable disabled 1 = transfer of this observable enabled 0 = transfer of this observable disabled 1 = transfer of this observable enabled 0 = transfer of this observable disabled 1 = transfer of this observable enabled 0 = transfer of this observable disabled 1 = transfer of this observable enabled 0 = transfer of this observable disabled 1 = transfer of this observable enabled 0 = transfer of this observable disabled 1 = transfer of this observable enabled
All Rights Reserved Copyright per DIN 34
GNSS_DM ACtr l
Bit
Fie ld
8 IE_ValueL_I
7 IE_ValueP_Q
6 IE_ValueP_I
5 IE_ValueE_Q
4 IE_ValueE_I
3 IE_ValueEE_Q
2 IE_ValueEE_I
1 IE_IMT_LSW
0 LoopState
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Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
De s cr iption 0 = transfer of this observable disabled 1 = transfer of this observable enabled 0 = transfer of this observable disabled 1 = transfer of this observable enabled 0 = transfer of this observable disabled 1 = transfer of this observable enabled 0 = transfer of this observable disabled 1 = transfer of this observable enabled 0 = transfer of this observable disabled 1 = transfer of this observable enabled 0 = transfer of this observable disabled 1 = transfer of this observable enabled 0 = transfer of this observable disabled 1 = transfer of this observable enabled 0 = transfer of this observable disabled 1 = transfer of this observable enabled 0 = transfer of this observable disabled 1 = transfer of this observable enabled
7.4.5.48 GNSS_DMAStartAddr
GNSS_DM AStar tAddr
Bit
Field Default
R/W
31-0
0 R/W
De s cr iption
start address of the destination buffer for that channel. Has to be 32bit aligned.
7.4.5.49 GNSS_DMAEndAddr
GNSS_DM AEndAddr
Bit
Field Default
R/W
31-0
0 R/W
De s cr iption
end address of the destination buffer for that channel. Has to be 32bit aligned.
7.4.5.50 GNSS_DMACurAddr
GNSS_DM ACur Addr
Bit
Field Default R/W Description
31-0
0 R/W current address of the DMA w rite pointer for that channel
Note that the current address pointer has to be set to a value w hich is equal or greater than the start address but sm aller than the end address before the DMA is started. Also not that the Current Address Pointer has to be 32bit alinge d.
7.4.6 Channel RAM Address Map
The PrimaryRAM1/2 and SecondaryRAM1/2 memories are not reset .
All Rights Reserved Copyright per DIN 34
Addr e s s Offs e t + 0x0000 + 0x0A00
+ 0x1400 + 0x1440
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Size [bits] Nam e
5120 5120
100 100
PrimaryRAM1 Primary RAM2 SecondaryRAM1 SecondaryRAM2
7.4.6.1 PrimaryRAM1
Prim aryRAM1
Addr e s s
Bit
Offs e t
+ 0x00
7-0
+ 0x04
... + 0x9FC
31-8 7-0
31-8 ... 7-0
31-8
Default Description
undef
undef undef undef undef undef
Data 0 Bit 7 = Chip 1 ... Bit 0 = Chip 8 reserved Data 1 reserved ... Data 639 reserved
7.4.6.2 PrimaryRAM2
Prim aryRAM2
Addr e s s
Bit
Offs e t
+ 0x00
7-0
+ 0x04
... + 0x9FC
31-8 7-0
31-8 ... 7-0
31-8
Default Description
undef
undef undef undef undef undef
Data 0 Bit 7 = Chip 1 ... Bit 0 = Chip 8 reserved Data 1 reserved ... Data 639 reserved
7.4.6.3 SecondaryRAM1
Se condar yRAM 1
Addr e s s
Bit
Offs e t
+ 0x00
7-0
+ 0x04 ...
31-8 7-0
31-8 ...
Default Description
undef
undef undef undef
Data 0 Bit 7 = Chip 1 ... Bit 0 = Chip 8 reserved Data 1 reserved ...
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Se condar yRAM 1
Addr e s s
Bit
Offs e t
+ 0x2C
7-0
31-8
+ 0x30
0-3 7-4 31-5
+ 0x34
31-0
+ 0x38
31-0
+ 0x3C
31-0
Default Description
undef undef
undef undef undef undef
undef undef
Data 11 reserved
reserved Data 12 reserved reserved
reserved reserved
7.4.6.4
SecondaryRAM2
Se condar yRAM 2
Addr e s s
Bit
Offs e t
+ 0x00
7-0
+ 0x04
... + 0x2C
+ 0x30
+ 0x34 + 0x38 + 0x3C
31-8 7-0
31-8 ... 7-0
31-8 0-3 7-4
31-5 31-0 31-0 31-0
Default Description
undef
undef undef undef
undef undef undef undef undef undef undef undef
Data 0 Bit 7 = Chip 1 ... Bit 0 = Chip 8 reserved Data 1 reserved ... Data 11 reserved reserved Data 12 reserved reserved reserved reserved
7.4.7
GNSS Interrupt Controller Registers
Addr e s s Offs e t
+ 0x00
Size [bits]
Nam e
32 GIC_Mask0
+ 0x04
10 GIC_Mask1
+ 0x08
32 GIC_Prio0
+ 0x0C
10 GIC_Prio1
+ 0x10
32 GIC_Pend0
+ 0x14
10 GIC_Pend1
+ 0x18
32 GIC_Clear0
+ 0x1C
10 GIC_Clear1
+ 0x20
6 GIC_QueueLow
+ 0x24
6 GIC_QueueHigh
+ 0x28
16 GIC_QueueStatus
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7.4.7.1 GIC_Mask0
GIC_M as k 0
Bit Field
De fault
31 Ch31
R/W 0 R/W
... 0 Ch0
0 R/W
De s cr iption 0 = Interrupt for channel #31 is stored in Pending Register, but does not cause PIC interrupt
1 = Interrupt for channel #31 is stored in Interrupt Queue and causes PIC interrupt
... 0 = Interrupt for channel #0 is stored in Pending Register, but does not cause PIC interrupt
1 = Interrupt for channel #0 is stored in Interrupt Queue and causes PIC interrupt
7.4.7.2 GIC_Mask1
GIC_M as k 1
Bit
Fie ld
De fault
R/W
31-10 reserved
0 R
9 DMAErr
0 R/W
8 PLD_IQ
0 R/W
7 PLD_5I
0 R/W
6 ME
0 R/W
5 ASE
0 R/W
4 PPS
0 R/W
3 Ch35
0 R/W
... 0 Ch32
0 R/W
De s cr iption reserved 0 = Interrupt for DMAErr is stored in Pending Register, but does not cause PIC interrupt
1 = Interrupt for DMAErr is stored in Interrupt Queue and causes PIC interrupt
0 = Interrupt for PLD_IQ is stored in Pending Register, but does not cause PIC interrupt
1 = Interrupt for PLD_IQ is stored in Interrupt Queue and causes PIC interrupt
0 = Interrupt for PLD_5I is stored in Pending Register, but does not cause PIC interrupt
1 = Interrupt for PLD_5I is stored in Interrupt Queue and causes PIC interrupt
0 = Interrupt for ME is stored in Pending Register, but does not cause PIC interrupt
1 = Interrupt for ME is stored in Interrupt Queue and causes PIC interrupt
0 = Interrupt for ASE is stored in Pending Register, but does not cause PIC interrupt
1 = Interrupt for ASE is stored in Interrupt Queue and causes PIC interrupt
0 = Interrupt for PPS is stored in Pending Register, but does not cause PIC interrupt
1 = Interrupt for PPS is stored in Interrupt Queue and causes PIC interrupt
0 = Interrupt for channel #35 is stored in Pending Register, but does not cause PIC interrupt
1 = Interrupt for channel #35 is stored in Interrupt Queue and causes PIC interrupt
... 0 = Interrupt for channel #32 is stored in Pending Register, but does not cause PIC interrupt
1 = Interrupt for channel #32 is stored in Interrupt Queue and causes PIC interrupt
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7.4.7.3 GIC_Prio0
GIC_Prio0
Bit Field Default R/W
31 Ch31
0 R/W
... 0 Ch0
0 R/W
De s cr iption 0 = Interrupt for channel #31 is assigned to level low 1 = Interrupt for channel #31 is assigned to level high ... 0 = Interrupt for channel #0 is assigned to level low 1 = Interrupt for channel #0 is assigned to level high
7.4.7.4 GIC_Prio1
GIC_Prio1
Bit
Fie ld
Default R/W Description
31-10 reserved 9 DMAErr
0 R reserved 0 R/W 0 = Interrupt for DMA error is assigned to level low
1 = Interrupt for DMA error is assigned to level high
8 PLD_IQ 7 PLD_5I
0 R/W 0 = Interrupt for pow er level detector IQ is assigned to level low 1 = Interrupt for pow er level detector IQ is assigned to level high
0 R/W 0 = Interrupt for pow er level detector 5I is assigned to level low 1 = Interrupt for pow er level detector 5I is assigned to level high
6 ME 5 ASE
0 R/W 0 = Interrupt for measurement epoch is assigned to level low 1 = Interrupt for measurement epoch is assigned to level high
0 R/W 0 = Interrupt for antenna sw itch epoch is assigned to level low 1 = Interrupt for antenna sw itch epoch is assigned to level high
4 PPS 3 Ch35
0 R/W 0 = Interrupt for pulse per second is assigned to level low 1 = Interrupt for pulse per second is assigned to level high
0 R/W 0 = Interrupt for channel #35 is assigned to level low
1 = Interrupt for channel #35 is assigned to level high
...
...
0 Ch32
0 R/W 0 = Interrupt for channel #32 is assigned to level low 1 = Interrupt for channel #32 is assigned to level high
7.4.7.5 GIC_Pend0
GIC_Pe nd0
Bit Field Default
R/W
31 Ch31
0 R
... 0 Ch0
0 R
De s cr iption 0 = Interrupt for channel #31 is not pending 1 = Interrupt for channel #31 is pending ... 0 = Interrupt for channel #0 is not pending 1 = Interrupt for channel #0 is pending
7.4.7.6 GIC_Pend1
GIC_Pe nd1
Bit
Fie ld
Default R/W
31-10 reserved
0 R
9 DMAErr
0 R
8 PLD_IQ
0 R
De s cr iption reserved 0 = Interrupt for DMA error is not pending 1 = Interrupt for DMA error is pending 0 = Interrupt for pow er level detector IQ is not pending 1 = Interrupt for pow er level detector IQ is pending
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GIC_Pe nd1
Bit
Fie ld
7 PLD_5I
6 ME
5 ASE
4 PPS
3 Ch35
... 0 Ch32
Default R/W 0 R 0 R 0 R 0 R 0 R
0 R
De s cr iption 0 = Interrupt for pow er level detector 5I is not pending 1 = Interrupt for pow er level detector 5I is pending 0 = Interrupt for measurement epoch is not pending 1 = Interrupt for measurement epoch is pending 0 = Interrupt for antenna sw itch epoch is not pending 1 = Interrupt for antenna sw itch epoch is pending 0 = Interrupt for pulse per second is not pending 1 = Interrupt for pulse per second is pending 0 = Interrupt for channel #35 is pending 1 = Interrupt for channel #35 is pending ... 0 = Interrupt for channel #32 is pending 1 = Interrupt for channel #32 is pending Note: In order to get the latest state of IntPend1, IntPend0 has to be read before
7.4.7.7 GIC_Clear0
GIC_Cle ar 0
Bit Field Default
R/W
31 Ch31
0 W
... 0 Ch0
0 W
De s cr iption 0 = Pending Bit for channel #31 is left unchanged 1 = Pending Bit for channel #31 is cleared ... 0 = Pending Bit for channel #0 is left unchanged 1 = Pending Bit for channel #0 is cleared
7.4.7.8 GIC_Clear1
GIC_Clear1 Bit Field 31-10 reserved
9 DMAErr
8 PLD_IQ
7 PLD_5I
6 ME
5 ASE
4 PPS
3 Ch35
... 0 Ch32
Default R/W Description 0 R reserved 0 W 0 = Pending Bit for DMA error is left unchanged 1 = Pending Bit for DMA error is cleared 0 W 0 = Pending Bit for power level detector IQ is left unchanged 1 = Pending Bit for power level detector IQ is cleared 0 W 0 = Pending Bit for power level detector 5I is left unchanged 1 = Pending Bit for power level detector 5I is cleared 0 W 0 = Pending Bit for measurement epoch is left unchanged 1 = Pending Bit for measurement epoch is cleared 0 W 0 = Pending Bit for antenna switch epoch is left unchanged 1 = Pending Bit for antenna switch epoch is cleared 0 W 0 = Pending Bit for pulse per second is left unchanged 1 = Pending Bit for pulse per second is cleared 0 W 0 = Interrupt for channel #35 is left unchanged 1 = Interrupt for channel #35 is cleared ... 0 W 0 = Interrupt for channel #32 is left unchanged 1 = Interrupt for channel #32 is cleared
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7.4.7.9 GIC_QueueLow
GIC_Que ue Low
Bit Field
Default R/W
31-6 reserved
0 R
5-0 Data
63 R
De s cr iption reserved 0 = channel #0 had interrupt 1 = channel #1 had interrupt ... 34 = channel #34 had interrupt 35 = channel #35 had interrupt 36 = PPS interrupt occured 37 = ASE interrupt occured 38 = ME interrupt occured 39 = PLD_5I interrupt occured 40 = PLD_IQ interrupt occured 41 = DMA error occured 42 = reserved ... 62 = reserved 63 = interrupt queue empty Note: After GNSS reset this register should be read until 0x3F (queue empty) is readback. See datasheet for more details.
7.4.7.10 GIC_QueueHigh
GIC_Que ue High
Bit Field
Default R/W
31-6 reserved
0 R
5-0 Data
63 R
De s cr iption reserved 0 = channel #0 had interrupt 1 = channel #0 had interrupt ... 34 = channel #34 had interrupt 35 = channel #35 had interrupt 36 = PPS interrupt occured 37 = ASE interrupt occured 38 = ME interrupt occured 39 = PLD_5I interrupt occured 40 = PLD_IQ interrupt occured 41 = DMA error occured 42 = reserved ... 62 = reserved 63 = interrupt queue empty Note: After GNSS reset this register should be read until 0x3F (queue empty) is readback. See datasheet for more details.
7.4.7.11 GIC_QueueStatus
GIC_Que ue Status
Bit Field
Default R/W Description
31- reserved 16
0 R reserved
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GIC_Que ue Status Bit Field
15 QueueLow Overflow
14 QueueHighOverflow
13-7 FifoLevelQueueLow 6-0 FifoLevelQueueHigh
De fault 0
R/W R/W
De s cr iption
If set, this bit indicates that the IntQueueLow w as full and another low queue enabled interrupt could not be registered in the low queue anymore. The bit can be set back to zero by w riting a "1" in this bit.
0 R/W If set, this bit indicates that the IntQueueHigh w as full and another high queue enabled interrupt could not be registered in the high queue anymore. The bit can be set back to zero by w riting a "1" in this bit.
N/A
R FIFO level of IntQueueLow . 0 = empty, 64 = full
N/A
R FIFO level of IntQueueHigh. 0 = empty, 64 = full
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7.5 FFT Address Map
7.5.1 FFT RAM and Registers
Addr e s s
Size [bits] Nam e
0xB0000000
32 FFTValue_0_real
0x B0000004
32 FFTValue_0_imag
0x B0000008
32 FFTValue_1_real
0x B000000C
32 FFTValue_1_imag
...
...
0x B00003F0
32 FFTValue_126_real
0x B00003F4
32 FFTValue_126_imag
0x B00003F8
32 FFTValue_127_real
0x B00003FC
32 FFTValue_127_imag
0x B0000400
1 FFTCtrl (see below )
7.5.1.1 FFTCtrl
FFTCtrl
Bit
Fie ld
31-2 reserved
1 FFTDone
0 startFFT
De fault 0 0
0
R/W Description
R Reserved
R Asserted w hen FFT done, cleared w hen w riting to FFTCtrl
R/W 0 = do nothing
1 = start FFT engine. Bit is cleared to 0 w hen FFT is done.
7.5.1.2 FFTValue
FFTValue
Bit
Fie ld
31-0 Value
De fault undef
R/W Description
R/W Write: Input data for FFT, in tw o's complement format Read : Output data of FFT calculation in IEEE 754 single precision Floating Point format
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8 Miscellaneous
8.1 Implementation Losses
For t he AGGA-4 t he following implement at ion losses have been found by analysis and simulat ion.
C ode
Input Modul e DDC Part - IQ Mixer - FIR Filt er - Aliasing (downsampling) - Quant izat ion R2C Part - FIR Filt er - Aliasing (downsampling) - Quant izat ion
Di gi tal Beam Formi ng - 2 Quant izat ions st eps
C hanne l - Final Down Convert er
Correlation Losses - Bandwidt h Limit ed Code - Jit t ering Code NCO
BPSK(1) [dB]
0,15 0,05 0,05 0,16
0,02 0,02 0,16
0,33
0,11
0,04 0,03
For furt her det ails see [AD-03].
BPSK(10) [dB]
Re m ark
0,15
0,05
0,05
0,16
wit h opt imal t hresholds
0,02 0,02 0,16
0,33
0,11
5 bit s rounded phase quant izat ion
0,44
0,29
for CoreClk frequency = 40 MHz
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8.2 Radiation Mitigation
8.2.1 Flip Flops
The AGGA-4 uses radiation hardened flip flops except for the following functions which are implemented wit h soft flip flops:
· Delay Lines of GNSS Core (t otal 36*20 = 7920 flip-flops). Bit errors in the code will be filt ered out by t he correlat ion process.
· Accumulators for EE,E,P,L,LL in the GNSS core (total 36*581 = 20916 flip-flops). Errors in t he correlat ion values, if on the MSB, can be large. However, the impact can be mitigated by plausibility checks (detection of out liers), appropriat e discriminat ors and filt ers in t he loop processing.
· Leon Memory interface data and check-bits buses (input and output) flip flops, total = 2* (32 + 7) = 78 flipflops. It is t herefore recommended t o always enable t he ext ernal memory EDAC.
8.2.2 RAM's
The following RAM's are used inside t he AGGA ASIC wit h t he following prot ect ion mechanisms: · GNSS primary code RAM, not prot ect ed · FFT RAM, not prot ect ed · DSU RAM (host ing t he DSU t race buffer), not prot ect ed · Cache Memory, parit y prot ect ed, see 4.7.3 for furt her det ails
In case of t he GNSS primary code RAM a bit flip would not dist urb t he GNSS receiver operat ion. Not e: If the primary code RAM is switched off, a radiation hard constant "1" comes out of the memories, so t hat t he residual code generat or is not dist urbed. The GNSS secondary code RAM and the Leon register file (typically also RAM) are implemented as hard flip flops and are t herefore not list ed in t he RAM sect ion. For ext ernal RAM t he AGGA offers a hardware EDAC prot ect ion. See 4.7.2 for furt her det ails.
8.2.3 TMR
The Triple Module Redundant implementation is used to protect critical register against SEU (Single Even Upset). Due t o the fact that the AGGA-4 design uses radiation hard technology, the use of TMR is limited to very critical regist ers.
8.2.3.1 Watchdog TMR The internal Watchdog is capable to force a reset in the whole ASIC. Therefore, the mechanism that directly generat es bot h watchdog level signals is protected with TMR. This protection consists of the t riplicat ion of t he int ernal st at e machine and generat ing via t riple vot ing of t heir result s t he wat chdog signals.
8.2.3.2 AGGA-4 Reset TMR The external AGGA-4 reset is used to control a count er t o release t he reset only when t he AGGA-4 clock PLL is locked. This allows keeping the design in reset during the stabilization of the PLL. A change in one of t he regist ers of t his counter can lead to a global reset. Therefore, this counter is implemented only once but if this counter reaches the 5 wait st at es, it set s t o high a TMR regist er.
8.2.3.3 GNSS CoreClkSel TMR CoreClkSel determines whether the CoreClk is the external EXT_CORE_CLK or the result of a division by 2.5 of t he HALF_SAMPLE_CLK pin. Due to the possibility that one of these clocks is connected to ground, a accident al change in t his register whould deactivate the whole GNSS circuit. Therefore, for this single bit regist er, an addit ional TMR prot ect ion is implement ed.
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8.2.3.4 Secure Lock TMR The internal lock signal shall indicate when the clock is stable and the syst em is ready t o operat e. This lock signal generated by a counter that keeps the system in reset unt il a given t ime is elapsed. An SEU in one of t his count er regist ers could force to a general reset in the system. Therefore, additional TMR prot ect ion is implement ed in t his count er.
Not e: A more det ailed analysis on t he radiat ion t est ing of AGGA-4 can be found in
8.3 Synchronization of multiple AGGA devices
In order to slave multiple AGGA-4's t oget her in order t o increase t he amount of GNSS channels, t he following arrangement for ME, PPS and IMT is recommended:
The int ended way t o have t he same PPS in all AGGA-4's is:
·
Provide t he same GNSS Core Clock t o all AGGA-4's
·
Define one AGGA-4 as PPS Mast er.
·
Connect t he PPSO from t he Mast er t o t he PPSI pins of all AGGA-4's
·
Configure all AGGA-4's t o use t he ext ernal PPS from t he PPSI pin (also t he mast er)
·
From now on all AGGA-4's should see t he same PPS event
The int ended way t o have t he same ME and IMT in all AGGA-4's is:
·
Provide t he same GNSS Core Clock t o all AGGA-4's
·
Define one AGGA-4 as Measurement Epoch (ME) Mast er.
·
Connect t he MEO from t he Mast er t o t he MEI pins of all AGGA-4's
·
Configure all AGGA-4's t o use t he ext ernal ME from t he MEI pin (also t he mast er)
·
At t ime of init ializat ion (aft er t he AGGA's have been configured t o use MEI), writ e "0" in t he
regist ers IMT_LSW and IMT_MSW
·
The "0" IMT value will become effect ive wit h t he next ME
·
From now on all AGGA-4's run fully synchronized (also t heir IMT count ers)
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8.4 Known Implementation Issues and Suggested Work Arounds
8.4.1 GNSS Interrupt Queue Initialization
Aft er reset of the GNSS core the GIC queue low and the GIC queue high can have one arbitrary entry. Therefore if t he user want s to make use of these queues, it is recommended to clean the queues by reading the registers GIC_QueueLow and GIC_QueueHigh aft er a GNSS reset unt il 0x3F (queue empt y) is readback.
8.4.2 Cache Freeze Alert
See sect ion 4.9.5
8.4.3 Pending Interrupt Cleared by Ticc
See sect ion 4.12.1.1
8.4.4 Reset and Clock Issue
If t he AGGA-4 is being reset (see chapter 6.5 for further det ails on t he reset logic) wit hout having t he t wo clock domains CoreClk and SysClk active at time of reset, uncontrolled GNSS DMA t ransfers to random addresses can occur. The receiver board design shall therefore make sure that both clock inputs EXT_SYS_CLK and EXT_CORE_CLK are available to the chip while POWER_ON_RESET_N is asserted. This is t rue for all possible AGGA-4 input modes.
If t he user wants to make use of the AGGA-4 DDC mode some additional remarks have to be taken into account. In this case t he GNSS operat ion needs t wo clock domains, t he CoreClk and t he HalfSampleClk. The user has t wo possibilit ies in t his case:
1. CoreClk and HalfSampleClk are generated outside the AGGA-4 and assigned t o t he pins EXT_CORE_CLK and HALF_SAMPLE_CLK. In this case no further considerations have to be taken into account, provided t hat all t hree ext ernal clocks are available during power-on reset .
2. HalfSampleClk is generated externally outside the AGGA-4 and is assigned to the pin HALF_SAMPLE_CLK. CoreClk is generated internally by setting the CoreClkSel bit in t he GNSSCoreClkCtrl regist er (see also chapter 6.4.2 for more details). In this case CoreClk is not present during power-on reset and t he following st artup sequence must be executed before act ually making use of t he GNSS core and it s DMA funct ion:
Acti on
C omment
Reset the AGGA-4 (e.g. power on or AGGA-4 reset )
EXT_SYS_CLK, EXT_CORE_CLK and HALF_SAMPLE_CLK must be available at time of reset . Note that in this particular case EXT_CORE_CLK
can be any frequency from 1MHz to the maximum, t here is no need to ensure a factor 2.5 between HalfSampleClk and CoreClk.
Program CoreClkSel = 1 in t he GNSSCoreClkCtrl Now CoreClk is generated int ernally by dividing t he
regist er
HALF_SAMPLE_CLK input .
Execut e a GNSS Reset by writ ing "0xDEADAFFE" Now t he GNSS core is properly initialized and ready to int o the SwResetEnable register, followed by a write of use. "0xCAFEBEBE" into t he SwResetExecute regist er.
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8.4.5 Start of Code Generators
Each Code Generator (VFCG, Primary Code Memory 1, Primary Code Memory 2) has the ability to (re-)start it s code generation (by setting the bits StartVFCG, StartCM1, StartCM2 in the CodeGenUnitCtrl register) wit h either t he IE or t he ME depending on t he Trigger bit in t he CodeGenUnitCtrl regist er. However the Code NCO phase is not reset at t he moment of t he configured t rigger aft er arming one of t he bit s StartVFCG, StartCM1, StartCM2. Therefore the user has to take into account that the edges of the code chips generated by t he (re-)st art ed code generat or can be phase shift ed relat ive t o t he IE or ME by a fract ion of one chip.
If t he user wants to implement a particular code phase relative to the ME he is advised to eit her t ake t his effect int o account or t o shift t he code phase wit h t he CodeSwShift regist er t o t he desired phase in relat ion.
Typically t he user want s t o have t he Code Epoch aligned wit h IE. In t his case t he user is advised t o set t he ResetAtStartOfEpoch bit in the CorrUnitCtrl register once the Code has started with the t rigger IE. Aft er set t ing t he ResetAtStartOfEpoch bit the IE is aligned to the Code Epoch and the sub-chip phase misalignment vanishes. Not e t hat in t his case one IE can occur wit h a very small delt a t ime t o it s predecessor (depending on t he sub-chip phase misalignement ).
8.4.6 SpaceWire RX DMA loss of EOP and data when packets arrive very close
When two SPW packets arrive close to each other on the same SPW link, EOP charact ers may be discarded. This happens if 8 or more characters of the next packet have been received at the time the DMA controller is transfering t he last character (and process the EOP) of the previous packet. In this case the EOP is not reported in the interrupt regist er SpW_ModuleIntStatus (bit SPWx_EOP_EEP), t he DMA is not stopped and the DMA continues wit h t he next packet inst ead. It is neither possible to give a minimum latency between the packets to trigger this condition, nor is it possible t o calculate the probability of the occurence of t his problem, because t he lat ency of t he DMA t ransfer is largely application dependent. The DMA transfer latencies depend on t he load of t he int ernal AHB bus which is a shared resource of t he CPU and all t he DMA unit s in t he AGGA-4.
In addit ion if this "loss-of-EOP" condition is triggered and the size of the old packet is NOT a multiple of 4 bytes (N*4, not including t he EOP), t hen t he first 4 byt es of t he new packet are discarded.
For example, t wo 9-charact er SPW packet s wit h dat a (in hex)...
· 00, 01, 02, 03, 04, 05, 06, 07, 08 · 10, 11, 12, 13, 14, 15, 16, 17, 18
... would be merged int o t he following 32-bit words found in t he DMA area:
· 0x 00 01 02 03 · 0x 04 05 06 07 · 0x 08 05 06 07 (last 3 bytes are dummy) · 0x 14 15 16 17 · 0x 18 15 16 17 (last 3 bytes are dummy)
The following measures are suggest ed as workaround:
Sol uti on A: The error will not occur if t he following condit ions are fulfilled: each SpW packet received by AGGA4 has a lengt h of modulo 8
AND { t he receive area, defined by the two registers SpWn_Rx_SAP and SpWn_Rx_EAP is large enough to receive a complet e SpW packet
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OR in t he case the receive area is NOT large enough to receive a complete SpW packet OR the length of the SpW packet is unknown, t hen t he lengt h of t he receive area has t o be modulo 8
} AND t he receive area is double word aligned, i.e. SpWn_Rx_SAP regist er bit s (2 t o 0) have t o be zero (0b000).
Sol ution B: The error will not occur if the defined DMA receive area is always exactly 4 bytes. As a consequence, t he DMA area has to be configured and re-started after each 4 bytes received. To avoid the overhead of frequent interrupt s, t his could be done by a background polling routine, copying the 4-byte word to a larger SW buffer and rest art ing t he DMA. Processing a packet could then still use the EOP int errupt , but ret rieving t he packet from t his SW buffer.
Sol ution C: The error will not occur if the next SpW packet is only received, after an EOP interrupt was generated from t he previous SpW packet - this means no SpW packet is in the "pipeline". This could t ypically be ensured by a high level flow control (e.g. the receiver acknowledges receipt with a ret urn packet , and only t hen t he sender(s) will be allowed t o send t he next packet ).
8.4.7 Data Loss when utilizing both UART's in parallel.
In certain scenarios of high congestion with both UARTs enabled for RX and TX, a loss of data on one of the receivers has been observed. The problem could never be fully analysed. The user is therefore currently advised to make not use of both UART's at the same t ime unt il t he issue is clarified.
8.4.8 GNSS Code Shift error by changing mode
The GNSS code generator described in chapter 3.4.3.5 allows to perform shifting of the code phase in different modes. However when writing the bitfield CodeSwShiftSteps in t he NCOSettings regist er t o zero, in very rare cases t he hardware will shift t he maximum number of 4194304 st eps rat her t han 0 st eps. Alt hough on first hand t his issue seems minor one has t o be aware t hat it not only can lead t o an unsucessfull acquisit ion of a particular channel, but also can have an influence on the length of the integration t ime (depending on t he value in the register CodeSwShift) and thus on the CPU load in order to process the channel. The user is t herefore advised t o never writ e "0" in t he bit field CodeSwShiftSteps. If t he user wants to stop the automatic slewing of the code generat or he is advised t o set t he value in t he regist er CodeSwShift t o zero and t he value of CodeSwShiftSteps t o "1".
8.4.9 GNSS AHB Slave initilization
Due t o an undeterministic initialization of the GNSS AHB Slave aft er power-on, it is possible t hat any access t o a GNSS core register can freeze the complete AMBA bus of the AGGA-4. Once this st at e has been reached, a syst em reset is required. The following opt ions are suggest ed as workaround:
· Program and enable the wat chdog as shown in chapter 6.5.2. In the case the wat chdog will generat e a reset if t his problem occurs. Aft er a t riggered wat chdog reset t he init ializat ion of t he GNSS AHB Slave is in a consist ent st at e.
· Aft er power up, just execute a software reset as shown in chapter 6.5.5. After this reset the initialization of t he GNSS AHB Slave is in save st at e.
· Writing to GNSS Code Memory (example: address 0xA100:0000) before the first access to any GNSS register. This dummy write generates the required ready signal t o resolve t he dead-lock in AHB slave int erface.
8.4.10 Access to non-exisiting GNSS code memories
The 36 GNSS code memories are implemented in the address range 0xA1000000 t o 0xA123FFFF. Accesses t o t he addresses from 0xA1240000 to 0xA13FFFFF will be int erpret ed by t he AGGA-4 as accesses t o code memories,
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alt hough they are not implemented. In such a case the AHB Slave interface of t he GNSS core will be frozen and t he AGGA-4 is no longer accessible. Only an AGGA-4 reset will break t his sit uat ion.
Any access t o address 0xA1240000 t o 0xA13FFFFF must t herefore be avoided.
8.4.11 Cache Snooping Problem
Probl em descri pti on An anomaly has been detected in the LEON2FT data cache controller, in a corner case in conjunct ion wit h part ially filled cache lines, i.e. lines allocated in the cache, of which not all valid bits are set. If the processor makes a read access t o a not yet cached word of such cache line (valid bit not set), causing a read miss, and t hat access closely coincides wit h a DMA write to that same cache line causing a snoop hit, the cache may become incoherent. The cache line should be cleared by the snooper, but the DMA write address may erroneously be set valid again, even though data in memory and dat a in cache are different .
Probl em i mpact The data cache may be incoherent, and as a consequence, data or commands coming in via DMA could be missed by t he processor, for example when the processor is polling a set of DMA locat ions, and DMA updat es one of t hem. The probability of occurrence seems to be generally very low, being conditioned by the coincidence of several event s: a) Exist ence of a part ially filled cache line b) CPU read t o a not yet cached locat ion of t his cache line c) DMA writ e t o an already cached locat ion of t he same cache line d) That CPU read and DMA writ e coincide in a narrow t ime window
C orrecti ve/Preventi ve acti ons to users Several count ermeasures may be considered: 1. Do not use t he cache for DMA dat a. This can be achieved by bypassing t he cache when reading DMA locat ions wit h ASI 0x4 or 0x7. Flushing t he cache before accessing any DMA locat ions would work as well, however will likely have a negat ive impact in performance. 2. Ensure cache coherency by an appropriat e soft ware prot ocol. For example, simult aneous read/writ e access is usually avoided by t he common double buffering scheme for DMA dat a, where one buffer is writ t en t o by DMA unt il full, t hen flip (swap) writ ing t o t he ot her buffer, while t he processor reads and processes only t he buffer which is not current ly at t ached t o DMA. 3. Since t he probabilit y of occurrence seems t o be very low, a use 'as-is' may be considered along wit h a suit able higher level fault det ect ion and recovery scheme. For example, for commands, a t imeout mechanism could be used, and dat a packet s be prot ect ed by parit y or CRC.
See also [RD-10] for furt her informat ion.
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