Open the PC chassis following the instructions provided with the PC. 4. The VCU128 board has a large cooling fan that requires two adjacent ...
Development Boards, Kits, Programmers | Evaluation Boards - Embedded - Complex Logic (FPGA, CPLD) | DigiKey
Xilinx Virtex UltraScale HBM | Renesas
VCU128 Evaluation Board
User Guide
UG1302 (v1.1) April 21, 2021
Table of Contents
Revision History...............................................................................................................4
Chapter 1: Introduction.............................................................................................. 5
Overview....................................................................................................................................... 5 Additional Resources.................................................................................................................. 5 Block Diagram..............................................................................................................................6 Board Features............................................................................................................................ 6 Board Specifications....................................................................................................................8
Chapter 2: Board Setup and Configuration......................................................9
Standard ESD Measures............................................................................................................. 9 Board Component Location.....................................................................................................10 Default Switch and Jumper Settings....................................................................................... 13 Installing the Board in a PC Chassis........................................................................................14 FPGA Configuration...................................................................................................................16
Chapter 3: Board Component Descriptions................................................... 18
Overview.....................................................................................................................................18 Component Descriptions......................................................................................................... 18
Appendix A: VITA 57.4 FMCP Connector Pinouts......................................... 93
Overview.....................................................................................................................................93
Appendix B: Xilinx Constraints File.................................................................... 94
Overview.....................................................................................................................................94
Appendix C: Regulatory and Compliance Information........................... 95
Overview.....................................................................................................................................95 CE Directives.............................................................................................................................. 95 CE Standards.............................................................................................................................. 95 Compliance Markings............................................................................................................... 96
Appendix D: Additional Resources and Legal Notices............................. 97
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Xilinx Resources.........................................................................................................................97 Documentation Navigator and Design Hubs.........................................................................97 References..................................................................................................................................98 Please Read: Important Legal Notices................................................................................. 100
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Revision History
Revision History
The following table shows the revision history for this document.
Section
Board Power System Initial release.
Revision Summary
04/21/2021 Version 1.1 Revised the Renesas smart power stage module part number in the power system block diagram.
12/21/2018 Version 1.0 N/A
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Chapter 1: Introduction
Chapter 1
Introduction
Overview
The VCU128 board incorporates the VU37P high bandwidth memory (HBM) FPGA, which uses stacked silicon interconnect (SSI) technology to add HBM die next to the FPGA die on the package substrate. The VCU128 evaluation board for the Xilinx® Virtex® UltraScale+TM FPGA provides a hardware environment for developing and evaluating designs targeting the UltraScale+ XCVU37P-2FSVH2892E device. The VCU128 evaluation board is equipped with many of the common board-level features needed for design development as listed here: · DDR4, RLD-3, and QDR-IV component memory · Ganged small form-factor pluggable (QSFP28) connectors · Sixteen-lane PCI Express® interface · Ethernet PHY · General purpose I/O · UART interface Additional features can be supported using modules compatible with the VITA-57.4 (FMCP HSPC) connector on the VCU128 board.
Additional Resources
See Appendix D: Additional Resources and Legal Notices for references to documents, files, and resources relevant to the VCU128 evaluation board.
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Chapter 1: Introduction
Block Diagram
A block diagram of the VCU128 evaluation board is shown in the following figure.
Figure 1: Evaluation Board Block Diagram
36-bit QDR-IV SDRAM (shown at banks 68, 69)
36-bit DQB-port
FMCP HSPC LA[00:33]
72-bit RLD-3 (2x32Mx36) MT44K32M36RB-107E
Not used Not used
PCIE_EP_TX/RX[0:3] PCIE_CLK2 PCIE_EP_TX/RX[4:7]
PCIE_EP_TX/RX[8:11] PCIE_CLK1 PCIE_EP_TX/RX[12:15]
INIT LED DONE LED PROG_B PB 1.5V BATT. QSPI 2Gb
235 not used
234 not used
233 not used
232 not used
231 not used
230 not used
229 not used
228 not used
227
226
225
224
70
71
72
75
74
73
0 XCVU37P-FSVH2892
0
HBM_43_PWR
HBM_43_PWR
NC
135
134 133 not used 132 131 130 not used 129 128 127 126
125
124
69
68
HBM_83
67
Not
used
64
HBM_43
65
66
Not
used
36-bit DQA-port + common 36-bit QDR-IV SDRAM 4Mx36 Dual-Port
CY7C4142KV13_106FCXC 36-bit DQB-port
Bank 70
GPIO 1.8V
ENET LED[0:7] PL_I2C0 BUS UART0, UART1 QSFP1, QSFP4 CTRL SMA_CLK OUT(P/N) SYSCTLR_UCA1 (TX/RX)
72-bit DDR4 Comp. Memory (4.5X512MX16)
MT40A512M16LY-075E
QSFP1 TX/RX[1:4] QSFP1_SI570_CLOCK QSFP2 TX/RX[1:4] QSFP2_SI570_CLOCK SI5328_CLOCK1 QSFP3 TX/RX[1:4] QSFP3_SI570_CLOCK SI5328_CLOCK2 QSFP4 TX/RX[1:4] QSFP4_SI570_CLOCK SMA_REFCLK_INPUT FMCP_HSPC_DP[20:23] FMCP_HSPC_GBTCLK5 FMCP_HSPC_DP[16:19] FMCP_HSPC_GBTCLK4 FMCP_HSPC_DP[12:15] FMCP_HSPC_GBTCLK3 FMCP_HSPC_DP[8:11] FMCP_HSPC_GBTCLK2 FMCP_HSPC_DP[4:7] FMCP_HSPC_GBTCLK1 FMCP_HSPC_DP[0:3] FMCP_HSPC_GBTCLK0
System Controller GPIO XC7Z010CLG225
X21647-112818
Board Features
The VCU128 evaluation board features are listed here. Detailed information for each feature is provided in Chapter 3: Board Component Descriptions.
· Virtex® UltraScale+TM XCVU37P-2FSVH2892E device · Zynq®-7000 SoC XC7Z010 based system controller · 4.5 GB DDR4 72-bit component memory interface (4.5 x [512 Mb x 16])
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Chapter 1: Introduction
· 144 Mb 36-bit dual-port QDR-IV component memory interface (1 x [4M x 36]) · 288 MB 72-bit RLD3 component memory interface (2 x [1.125 Gb x 36]) · 2 Gb Quad SPI flash configuration memory · QSFPF28 - Sixteen (16) GTY transceivers are allocated for a 1x4 QSFP cage · USB JTAG interface (FTDI FT4232HL with a micro-AB USB connector) · Clock sources:
SMA I/F clocks: - FPGA bank 67 SMA clock P/N
QSFP clocks: - Four Si570 I2C programmable clock oscillators (156.25 MHz default) - QSFP clock recovery Si5328 input to GTY132 and GTY134 - QSFP external SMA diff. clock input to GTY131
Memory I/F clocks: - Three SiT9120A fixed 100 MHz LVDS clock oscillators
PCIe® I/F clock: - Fixed 100 MHz HCSL clock from PCI Express® edge input to 1-to-2 clock buffer wired to GTY225 and GTY227
System controller clock: - SiT8008A 33.33 MHz single-ended clock oscillator
· 96 GTY transceivers (24 Quads) FMCP HSPC connector (twenty-four GTY transceivers) 4x28 Gb/s QSFP+ connectors (eight GTY transceivers) PCIe 16-lane edge connector (sixteen GTY transceivers) Not used (forty-eight GTY transceivers)
· PCI Express® Endpoint connectivity Gen1 (x1, x2, x4, x8, x16) Gen2 (x1, x2, x4, x8, x16) Gen3 (x1, x2, x4, x8, x16) Dual Gen4 (x1, x2, x4, x8)
· Ethernet PHY SGMII interface with RJ-45 connector · Dual USB-to-UART bridge with micro-B USB connector (shared FTDI FT4232HL)
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Chapter 1: Introduction
· I2C bus · Status LEDs · User I/O (1 x push-button switch, 8 x LED) · VITA 57.4 FMC+ HSPC connector (DP[0:23], LA[0:33]) · Power management with I2C voltage monitoring through Intersil power controllers and GUI · Configuration options:
Quad SPI flash memory USB JTAG I/F (FTDI FT4232HL) Platform cable USB II interface 2x7 2 mm keyed connector
Board Specifications
Dimensions
Height: 7.53 inch (19.14 cm) Length: 9.50 inch (24.13 cm) Thickness (±5%): 0.061 inch (0.1549 cm) Note: A 3D model of this board is not available.
IMPORTANT! The VCU128 board height exceeds the standard 4.376-inch (11.15 cm) height of a PCI Express® card.
Environmental
Temperature Operating: 0°C to +45°C, Storage: -25°C to +60°C
Humidity 10% to 90% non-condensing
Operating Voltage
+12 VDC
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Chapter 2: Board Setup and Configuration
Chapter 2
Board Setup and Configuration
Standard ESD Measures
CAUTION! ESD can damage electronic components when they are improperly handled, and can result in total or intermittent failures. Always follow ESD-prevention procedures when removing and replacing components.
To prevent ESD damage: · Attach a wrist strap to an unpainted metal surface of your hardware to prevent electrostatic
discharge from damaging your hardware. · When you are using a wrist strap, follow all electrical safety procedures. A wrist strap is for
static control. It does not increase or decrease your risk of receiving electric shock when you are using or working on electrical equipment. · If you do not have a wrist strap, before you remove the product from ESD packaging and installing or replacing hardware, touch an unpainted metal surface of the system for a minimum of five seconds. · Do not remove the device from the antistatic bag until you are ready to install the device in the system. · With the device still in its antistatic bag, touch it to the metal frame of the system. · Grasp cards and boards by the edges. Avoid touching the components and gold connectors on the adapter. · If you need to lay the device down while it is out of the antistatic bag, lay it on the antistatic bag. Before you pick it up again, touch the antistatic bag and the metal frame of the system at the same time. · Handle the devices carefully to prevent permanent damage.
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Chapter 2: Board Setup and Configuration
Board Component Location
The following figure shows the VCU128 board component locations. Each numbered component shown in the figure is keyed to the table in Board Component Descriptions.
IMPORTANT! The board component locations figure is for visual reference only and might not reflect the current revision of the board.
IMPORTANT! There could be multiple revisions of this board. The specific details concerning the differences between revisions are not captured in this document. This document is not intended to be a reference design guide and the information herein should not be used as such. Always refer to the schematic, layout, and XDC files of the specific VCU128 version of interest for such details.
Figure 2: Evaluation Board Component Locations
00
Round callout references a component on the front side of the board
00
Square callout references a component on the back side of the board
24 24
25 26
35
23
28
36
22
22
27 38
31
44
18
10
39
30 29 32
16
15 19
17 14 13
5
11 37
20 20
2 1 3
21 7 12
34 34
6
9
33
8
40
X22144-121718
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Chapter 2: Board Setup and Configuration
Board Component Descriptions
The following table identifies the components, references the respective schematic page numbers, and links to a detailed functional description of the components and board features in Chapter 3: Board Component Descriptions.
Table 1: Board Component Descriptions
Callout
Feature [U#] = Bottom
Notes
1
Virtex UltraScale+ XCVU37P-2FSVH2892E XCVU37P-2FSVH2892E
Device (with fan-sink on soldered FPGA) Cofan 30-4811
2
GTY transceivers, Right-side Quads (twelve Embedded within FPGA U1
quads)
3
GTY transceivers, Left-side Quads (twelve Embedded within FPGA U1
quads)
4
DDR4 Component Memory, 72-bit DDR4 5 x Micron MT40A256M16GE-075E
component memory I/F, (U17-U19), [U73,
U74]
5
RLD3 Component Memory, RLD3 72-bit
2 x Micron MT44K32M36RB-107E
component memory I/F (U37, U39)
6
QDR4 Component Memory (U40)
Cypress CY7C4142KV13-106FCXC
7
Quad SPI Flash Memory (U46)
Micron MT25QU02GCBB8E12-0SIT
8
System Controller, Zynq®-7000 SoC (U42) XC7Z010CLG225
9
System Controller Quad SPI Flash Memory Micron MT25QU02GCBB8E12-0SIT
[U89]
10
DDR4 Component Memory I/F clock, fixed SiTime SIT9120AI-2D3-33E100.0000
100 MHz LVDS [U76]
11
RLD3 Component Memory I/F clock, fixed SiTime SIT9120AI-2D3-33E100.0000
100 MHz LVDS (U45)
12
QDR4 Component Memory I/F clock, fixed SiTime SIT9120AI-2D3-33E100.0000
100 MHz LVDS [U96]
13
Programmable QSFP1 Clock I2C, LVDS
[U95]
Silicon Labs SI570BAB0000544DG (default 156.250 MHz)
14
Programmable QSFP2 Clock I2C, LVDS
[U90]
Silicon Labs SI570BAB0000544DG (default 156.250 MHz)
15
Programmable QSFP3 Clock I2C, LVDS
[U82]
Silicon Labs SI570BAB0000544DG (default 156.250 MHz)
16
Programmable QSFP4 Clock I2C, LVDS
[U80]
Silicon Labs SI570BAB0000544DG (default 156.250 MHz)
17
QSFP Jitter Attenuated Clock, [U87]
Silicon Labs SI5328B-C-GMR
18
User QSFP SMA Clock pair J24(P)/J26(N)
Rosenberger 32K10K-400L5
input to XCVU37P U1 GTY131
MGTREFCLK1P/N
19
Four 28 Gb/s zQSFP+ Module Connectors, 4 x TE 1551920-2 connectors with TE 2170745-2
QSFP1-4 (J42), (J39), (J35), (J32) + 1x4
cage with heatsink
ganged cage
Schematic Page
Number
14-15 16-17 24-26
29-30 27 3
48-50 49 32 32 32 40 40 40 40 40 12
38, 39
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Chapter 2: Board Setup and Configuration
Table 1: Board Component Descriptions (cont'd)
Callout
Feature [U#] = Bottom
Notes
20
PCI Express Endpoint Connectivity,
PCI Express® 16-lane connector (P1)
16-lane card edge connector
21
PCI Express Endpoint Connectivity 100
MHz REFCLK 1-to-2 clock buffer,
differential-to-LVDS [U94]
ICS ICS85411AMLF
22
10/100/1000 Mb/s Tri-speed Ethernet PHY TI DP83867ISRGZ with Wurth 7499111221A RJ45
with RJ45, SGMII mode only, [U62], (P2)
(with magnetics)
23
Ethernet PHY Status LEDs, LEDs are
integrated into P2 bezel
Wurth 7499111221A RJ45 integrated status LEDs
24
USB JTAG Interface, USB bridge (U8) with FTDI FT4232HL bridge
mini-B USB connector (J2) and 2x7 2 mm prog. cable connector (J4)
Hirose ZX62D-AB-5P8 connector Molex 87832-1420
25
I2C Bus, Topology, and Switches I2C0 bus TI PCA9544ARGYR
topology: I2C bus MUX [U55], 16-bit expansion port [U65]
TI TCA6416APWR
26
I2C Bus, Topology, and Switches I2C0 bus 2 x TI TCA9548APWR
topology: 2 x I2C bus MUX [U53, U54]
28
User GPIO LEDs (DS2-DS9), active-High
Lumex SML-LX0603GW-TR
29
User GPIO pushbutton, CPU reset (SW4), E-Switch TL3301EF100QG
active-High
30
Switches, program_B pushbutton, (SW2), E-Switch TL3301EF100QG
active-Low
31
FMCP Connector J18, (J18)
Samtec ASP_184329_01
32
Board Power System Power Input
Connector, (J16)
2x6 Molex-39-30-1060
33
Board Power System power input switch, C&K 1201M2S3AQE2
on/off slide switch (SW5)
34
Board Power System, power management Intersil power system
system (top and bottom)
35
Monitoring Voltage and Current, PMBus Amphenol 68021-406HLF
2x3 R.A. male pin header (J1)
36
Configuration Options, FPGA U1
configuration mode DIP switch, (SW1)
4-pole CTS 218-4LPSTRF
37
PCI Express Endpoint Connectivity, lane
2x4 0.1-inch male header Sullins PBC36DAAN
width select header, (J46)
38
Jumpers, FPGA POR_OVERRIDE select
header, (J14)
1x3 0.1-inch male header Sullins PBC36SAAN
39
Jumpers, FPGA VCCINT select header, (J25) 1x3 0.1-inch male header Sullins PBC36SAAN
40
Jumpers, SYS CTLR RE-PROG header, (J43) 1x2 0.1-inch male header Sullins PBC36SAAN
Schematic Page
Number
41 14
37 37 34
35
36 47 47 3 42-46 52 52 54-65 54 3 41 3 54 50
The VCU128 board schematics are available for download from the VCU128 Evaluation Kit website.
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Chapter 2: Board Setup and Configuration
Default Switch and Jumper Settings
Switches
Default switch settings are listed in the following table. The switch locations are shown in Figure 2. The following table also references the respective schematic page numbers.
Table 2: Default Switch Settings
Switch
Function
Default
Comments
Figure 2 Callout
SW5 On/Off SPST slide switch
OFF
Board shipped with power switch off
33
SW1
4-pole configuration1 SW1[1:4] = Position 1 = System Controller Enable
36
Default = SPI
0001 SW1[2:4] = FPGA U1 mode M[2:0] = 001
SW2
FPGA_PROG_B P.B.
NA
U1 XCVU37P PROG_B (active low)
30
SW3
SYSCTLR_POR_B P.B.
NA
U42 XC7Z010 POR_B (active low)
Near 29
SW4
CPU_RESET P.B.
NA
U1 XCVU37P USER P.B. (active high)
29
Notes: 1. DIP switch sections are active-High (connected net is pulled High when DIP switch is closed = 1).
Schematic Page
52 3
3 50
47
Jumpers
Default jumper settings are listed in the following table. Jumper header locations are shown in Figure 2. The following table also references the respective schematic page numbers.
Table 3: Default Jumper Settings
Jumper
Function
Default
Comments
J14
Power on reset (POR)
override
2-3
U1 POR_OVERRIDE pin
BG15 to GND
J25
VCCINT select
1-2
1-2: 0.85V; 2-3: 0.72V1
J46
PCIe® lane size select
7-8
16-lane configuration
J43
SYSCTLR RE-PROG
Off
U42 XCZU7010 MIO5 pin
A9
Notes: 1. VCCINT select header J25 should always have a jumper block installed.
Figure 2 Callout
38
39 37 40
Schematic Page
3
54 41 50
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Chapter 2: Board Setup and Configuration
Installing the Board in a PC Chassis
The VCU128 board 12V power input circuitry allows 12V to be applied through one of two connectors, J16 (typically used with the stand-alone VCU128 power adapter) or JP1, as shown in the following figure.
Figure 3: 12V Power Entry
X22058-121318
Installation of the VCU128 board inside a computer chassis is required when developing or testing PCI Express® functionality. When the VCU128 board is used inside a computer chassis (i.e., plugged in to a PCIe slot), power is provided by choosing one of two mutually exclusive ATX power supply cables as described in this section (use one cable or the other).
· The ATX power supply 4-pin (1x4) peripheral connector, which requires using the ATX adapter cable (see the following figure) to connect to J16 on the VCU128 board. The Xilinx part number for this cable is 2600304. See ATX Power Supply Adapter Cable.
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Chapter 2: Board Setup and Configuration
Figure 4: ATX Power Supply Adapter Cable
To ATX 4-Pin Peripheral Power Connector
To J16 on VCU128 Board
X21955-121918
· The ATX supply 8-pin (2x4) PCIe power connector, which plugs into JP1 on the VCU128 board.
Steps to Install Board
To install the board in a PC chassis:
1. On the VCU128 board, remove the five screws retaining the five rubber feet and standoffs, and the PCIe bracket. Reinstall the PCIe® bracket using two of the previously removed screws.
2. Power down the host computer and remove the power cord from the PC.
3. Open the PC chassis following the instructions provided with the PC.
4. The VCU128 board has a large cooling fan that requires two adjacent PCIe slots. Ensure the slot adjacent to the front of the board is free of obstructions.
5. Remove the PCIe expansion slot cover (at the back of the chassis) which aligns with the VCU128 PCIe bracket, by removing the screws on the top and bottom of the cover.
6. Plug the VCU128 board into the appropriate open slot.
7. Install the top mounting bracket screw into the PC expansion cover retainer bracket to secure the VCU128 board in its slot.
8. If using the ATX supply 4-pin (1x4) peripheral connector, connect power to the VCU128 board using the ATX power supply adapter cable as shown in the previous figure.
a. Plug the 6-pin 2 x 3 Molex connector end of the adapter cable into J16 on the VCU128 board.
b. Plug the 4-pin 1 x 4 peripheral power connector from the ATX power supply into the 4pin adapter connector end of the cable.
CAUTION! Do NOT plug a PC ATX power supply 6-pin connector into J16 on the VCU128 evaluation board. The ATX 6-pin connector has a different pinout than J16. Connecting an ATX 6pin connector into J16 damages the VCU128 evaluation board and voids the board warranty.
c. Slide the VCU128 board power switch SW5 to the ON position. The PC can now be powered on.
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Chapter 2: Board Setup and Configuration 9. If using the ATX supply 8-pin (2x4) PCIe power connector, plug the connector into VCU128
board JP1. The PC can now be powered on.
FPGA Configuration
The VCU128 board supports two of the five UltraScale+TM FPGA configuration modes:
· Quad SPI flash memory (2 Gb) · JTAG using:
USB JTAG configuration port (U8 FT4232HL + USB J2 micro-AB)
Xilinx Platform Cable USB II, 2 mm, keyed flat cable header (J4)
Each configuration interface corresponds to one or more configuration modes and bus widths, as listed in the following table. The mode switches M2, M1, and M0 are on SW1 positions 2, 3, and 4, respectively. The FPGA default mode setting M[2:0] = 001 selects the master SPI configuration mode.
Table 4: Configuration Modes
Configuration Mode
Master SPI JTAG
SW1 DIP Switch Settings M[2:0]
1
101
Bus Width
x1, x2, x4 x1
CCLK Direction
Output NA
For complete details on configuring the FPGA, see UltraScale Architecture Configuration User Guide (UG570). The following figure shows the configuration mode DIP switch SW1 JTAG switch positions.
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Chapter 2: Board Setup and Configuration
Figure 5: SW1 JTAG Mode Settings
ON Position = 1
SCE M2 M1 M0 SW1
OFF Position = 0
12 34
X21648-121918
JTAG
The Vivado®, Xilinx SDK, or third-party tools can establish a JTAG connection to the XCVU37P FPGA through the FTDI FT4232 USB-to-JTAG/USB UART device (U8) connected to the microUSB connector (J2). Alternatively, a JTAG cable can be connected to the keyed flat cable header (J4). JTAG initiated configuration takes priority over the configuration method selected through the FPGA mode pins M[2:0], wired to SW1 positions [2:4].
Quad SPI
To boot from the dual Quad SPI non-volatile configuration memory, follow these steps.
1. Store a valid XCVU37P FPGA boot image in the 2 Gbit Quad SPI flash device (U46) connected to the FPGA bank 0 Quad SPI interface. See the VCU128 Restoring Flash Tutorial (XTP533) for information on programming the QSPI.
2. Set the boot mode pins SW1 M[2:0] as indicated in the configuration modes table in FPGA Configuration for master SPI.
3. Power-cycle the VCU128 board. Mode SW1 is callout 36 in Figure 2.
See the VCU128 Software Install and Board Setup Tutorial (XTP535) for more information.
See System Controller for an overview of query and control of select programmable board features such as clocks, FMCP functionality, and power systems. See the VCU128 System Controller Tutorial (XTP534) for more information.
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Chapter 3: Board Component Descriptions
Chapter 3
Board Component Descriptions
Overview
This chapter provides a detailed functional description of the board's components and features. Table 1 identifies the components, references the respective schematic page numbers, and links to the corresponding detailed functional description in this chapter. Component locations are shown in Figure 2.
Component Descriptions
Virtex UltraScale+ XCVU37P-2FSVH2892E Device
[Figure 2, callout 1] The VCU128 board incorporates the VU37P high bandwidth memory (HBM) FPGA, which utilizes stacked silicon interconnect (SSI) technology to add HBM die next to the FPGA die on the package substrate. The VCU128 board is populated with the Virtex® UltraScale+TM XCVU37P-2FSVH2892E device. For more information on Virtex UltraScale+ FPGAs, see Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS923).
Encryption Key Battery Backup Circuit
The XCVU37P device U1 implements bitstream encryption key technology. The VCU128 board provides the encryption key backup battery circuit shown in the following figure.
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Chapter 3: Board Component Descriptions Figure 6: Encryption Key Backup Circuit
X21956-112918
The Seiko TS621E rechargeable 1.5V lithium button-type battery B1 is soldered to the board with the positive output connected to the XCVU37P device U1 VBATT pin BD13. The battery supply current IBATT specification is 150 nA maximum when the board power is off. B1 is charged from the VCC1V8_BUS 1.8V rail through a series diode with a typical forward voltage drop of 0.38V and 4.7 K current limit resistor. The nominal charging voltage is 1.42V.
I/O Voltage Rails
There are 12 I/O banks and 2 high-bandwidth memory (HBM) banks available on the XCVU37P device. The VCU128 board does not use the HBM banks. The voltages applied to the FPGA I/O banks on the VCU128 board are listed in the following table.
Table 5: I/O Bank Voltage Rails
FPGA (U1) Bank
Bank 0 HP bank 64 HP bank 65 HP bank 66 HP bank 67 HP bank 68 HP bank 69 HP bank 70 HP bank 71
Power Supply Rail Net Name
VCC1V8 DDR4_VDDQ_1V2 DDR4_VDDQ_1V2 DDR4_VDDQ_1V2
VCC1V8 QDR4_VDDQ_1V2 QDR4_VDDQ_1V2 QDR4_VDDQ_1V2
VADJ
Voltage
1.8V 1.2V 1.2V 1.2V 1.8V 1.2V 1.2V 1.2V 1.8V
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Chapter 3: Board Component Descriptions
Table 5: I/O Bank Voltage Rails (cont'd)
FPGA (U1) Bank
HP bank 72 HP bank 73 HP bank 74 HP bank 75 HBM_43 (not used) HBM_83 (not used)
Power Supply Rail Net Name
VADJ RLD3_VDDQ_1V2 RLD3_VDDQ_1V2 RLD3_VDDQ_1V2 VCCHBM/VCCAUX_HBM VCCHBM/VCCAUX_HBM
Voltage
1.8V 1.2V 1.2V 1.2V 1.2V/1.8V 1.2V/1.8V
DDR4 Component Memory
[Figure 2, callout 4]
The 4.5 GB DDR4 component memory system is comprised of five 512 Mb x 16 DDR4 SDRAM devices implemented in clam-shell fashion located at U17-U19 (top) and U73-U74 (bottom). Half of the U19 16-bits are used (4.5 x 16-bits = 72-bit wide interface).
· Manufacturer: Micron
· Part Number: MT40A512M16LY-075E
· Description: 8 Gb (512 Mb x 16)
1.2V 96-ball TFBGA
DDR4-2666
The VCU128 XCVU37P FPGA DDR4 interface performance is documented in the Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS923).
The 72-bit wide DDR4 memory system is connected to XCVU37P U1 HP banks 64, 65 and 66. The DDR4 0.6V VTT termination voltage (net DDR4_VTERM_0V6) is sourced from the TI TPS51200DR linear regulator U71. The DDR4 memory interface bank VREF pins are not connected, which, coupled with an XDC set_property INTERNAL VREF constraint, invoke the INTERNAL VREF mode. The connections between the 72-bit interface DDR4 component memories and XCVU37P banks 64, 65, and 66 are listed in the following table.
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Chapter 3: Board Component Descriptions
Table 6: DDR4 Memory 72-bit I/F to FPGA U1 Banks 64, 65, and 66
FPGA (U1) Pin
Schematic Net Name
I/O Standard
BM45 BP44 BP47 BN45 BM44 BN44 BN47 BP43 BN46 BP46 BN42 BL45 BK44 BL46 BK43 BL43 BJ44 BL42 BJ43 BK45 BK46 BL47 BK41 BG44 BG42 BH44 BH45 BG45 BG43 BJ41 BH46 BJ46 BH42 BE43 BF42 BC42 BF43 BD42
PL_DDR4_DQ0 PL_DDR4_DQ1 PL_DDR4_DQ2 PL_DDR4_DQ3 PL_DDR4_DQ4 PL_DDR4_DQ5 PL_DDR4_DQ6 PL_DDR4_DQ7 PL_DDR4_DQS0_T PL_DDR4_DQS0_C PL_DDR4_DM0_B PL_DDR4_DQ8 PL_DDR4_DQ9 PL_DDR4_DQ10 PL_DDR4_DQ11 PL_DDR4_DQ12 PL_DDR4_DQ13 PL_DDR4_DQ14 PL_DDR4_DQ15 PL_DDR4_DQS1_T PL_DDR4_DQS1_C PL_DDR4_DM1_B PL_DDR4_DQ16 PL_DDR4_DQ17 PL_DDR4_DQ18 PL_DDR4_DQ19 PL_DDR4_DQ20 PL_DDR4_DQ21 PL_DDR4_DQ22 PL_DDR4_DQ23 PL_DDR4_DQS2_T PL_DDR4_DQS2_C PL_DDR4_DM2_B PL_DDR4_DQ24 PL_DDR4_DQ25 PL_DDR4_DQ26 PL_DDR4_DQ27 PL_DDR4_DQ28
POD12_DCI POD12_DCI POD12_DCI POD12_DCI POD12_DCI POD12_DCI POD12_DCI POD12_DCI DIFF_POD12_DCI DIFF_POD12_DCI POD12_DCI POD12_DCI POD12_DCI POD12_DCI POD12_DCI POD12_DCI POD12_DCI POD12_DCI POD12_DCI DIFF_POD12_DCI DIFF_POD12_DCI POD12_DCI POD12_DCI POD12_DCI POD12_DCI POD12_DCI POD12_DCI POD12_DCI POD12_DCI POD12_DCI DIFF_POD12_DCI DIFF_POD12_DCI POD12_DCI POD12_DCI POD12_DCI POD12_DCI POD12_DCI POD12_DCI
Pin #
A3 B8 C3 C7 C2 C8 D3 D7 B7 A7 E2 G2 F7 H3 H7 H2 H8 J3 J7 G3 F3 E7 G2 F7 H3 H7 H2 H8 J3 J7 G3 F3 E7 G2 F7 H3 H7 H2
Component Memory
Pin Name
Ref. Des.
DQ8
U74
DQ9
U74
DQ10
U74
DQ11
U74
DQ12
U74
DQ13
U74
DQ14
U74
DQ15
U74
UDQS_T
U74
UDQS_C
U74
NF/UDM_B/UDBI_B
U74
DQ0
U17
DQ1
U17
DQ2
U17
DQ3
U17
DQ4
U17
DQ5
U17
DQ6
U17
DQ7
U17
LDQS_T
U17
LDQS_C
U17
NF/LDM_B/LDBI_B
U17
DQ0
U74
DQ1
U74
DQ2
U74
DQ3
U74
DQ4
U74
DQ5
U74
DQ6
U74
DQ7
U74
LDQS_T
U74
LDQS_C
U74
NF/LDM_B/LDBI_B
U74
DQ0
U18
DQ1
U18
DQ2
U18
DQ3
U18
DQ4
U18
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Chapter 3: Board Component Descriptions
Table 6: DDR4 Memory 72-bit I/F to FPGA U1 Banks 64, 65, and 66 (cont'd)
FPGA (U1) Pin
Schematic Net Name
I/O Standard
BF45 BE44 BF46 BE45 BE46 BD41 BP32 BP29 BP31 BP28 BN32 BM30 BN31 BL30 BN29 BN30 BM28 BL32 BP34 BN34 BK33 BL31 BL33 BM33 BK31 BL35 BM35 BM34 BJ34 BG35 BH34 BH35 BJ33 BF35 BG34 BF36 BK34 BK35
PL_DDR4_DQ29 PL_DDR4_DQ30 PL_DDR4_DQ31 PL_DDR4_DQS3_T PL_DDR4_DQS3_C PL_DDR4_DM3_B PL_DDR4_DQ32 PL_DDR4_DQ33 PL_DDR4_DQ34 PL_DDR4_DQ35 PL_DDR4_DQ36 PL_DDR4_DQ37 PL_DDR4_DQ38 PL_DDR4_DQ39 PL_DDR4_DQS4_T PL_DDR4_DQS4_C PL_DDR4_DM4_B PL_DDR4_DQ40 PL_DDR4_DQ41 PL_DDR4_DQ42 PL_DDR4_DQ43 PL_DDR4_DQ44 PL_DDR4_DQ45 PL_DDR4_DQ46 PL_DDR4_DQ47 PL_DDR4_DQS5_T PL_DDR4_DQS5_C PL_DDR4_DM5_B PL_DDR4_DQ48 PL_DDR4_DQ49 PL_DDR4_DQ50 PL_DDR4_DQ51 PL_DDR4_DQ52 PL_DDR4_DQ53 PL_DDR4_DQ54 PL_DDR4_DQ55 PL_DDR4_DQS6_T PL_DDR4_DQS6_C
POD12_DCI POD12_DCI POD12_DCI DIFF_POD12_DCI DIFF_POD12_DCI DIFF_POD12_DCI POD12_DCI POD12_DCI POD12_DCI POD12_DCI POD12_DCI POD12_DCI POD12_DCI POD12_DCI DIFF_POD12_DCI DIFF_POD12_DCI POD12_DCI POD12_DCI POD12_DCI POD12_DCI POD12_DCI POD12_DCI POD12_DCI POD12_DCI POD12_DCI DIFF_POD12_DCI DIFF_POD12_DCI POD12_DCI POD12_DCI POD12_DCI POD12_DCI POD12_DCI POD12_DCI POD12_DCI POD12_DCI POD12_DCI DIFF_POD12_DCI DIFF_POD12_DCI
Pin #
H8 J3 J7 G3 F3 E7 G2 F7 H3 H7 H2 H8 J3 J7 G3 F3 E7 G2 F7 H3 H7 H2 H8 J3 J7 G3 F3 E7 A3 B8 C3 C7 C2 C8 D3 D7 B7 A7
Component Memory
Pin Name
Ref. Des.
DQ5
U18
DQ6
U18
DQ7
U18
LDQS_T
U18
LDQS_C
U18
NF/LDM_B/LDBI_B
U18
DQ0
U73
DQ1
U73
DQ2
U73
DQ3
U73
DQ4
U73
DQ5
U73
DQ6
U73
DQ7
U73
LDQS_T
U73
LDQS_C
U73
NF/LDM_B/LDBI_B
U73
DQ0
U19
DQ1
U19
DQ2
U19
DQ3
U19
DQ4
U19
DQ5
U19
DQ6
U19
DQ7
U19
LDQS_T
U19
LDQS_C
U19
NF/LDM_B/LDBI_B
U19
DQ8
U18
DQ9
U18
DQ10
U18
DQ11
U18
DQ12
U18
DQ13
U18
DQ14
U18
DQ15
U18
UDQS_T
U18
UDQS_C
U18
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Chapter 3: Board Component Descriptions
Table 6: DDR4 Memory 72-bit I/F to FPGA U1 Banks 64, 65, and 66 (cont'd)
FPGA (U1) Pin
BH32 BF31 BH30 BJ31 BG32 BH31 BF32 BH29 BF33 BJ29 BK30 BG29 BN51 BM52 BN50 BL52 BM48 BL53 BN49 BL51 BM49 BM50 BP48
BF50 BD51 BG48 BE50 BE49 BE51 BF53 BG50 BF51 BG47 BF47 BG49 BF48 BF52
Schematic Net Name
PL_DDR4_DM6_B PL_DDR4_DQ56 PL_DDR4_DQ57 PL_DDR4_DQ58 PL_DDR4_DQ59 PL_DDR4_DQ60 PL_DDR4_DQ61 PL_DDR4_DQ62 PL_DDR4_DQ63 PL_DDR4_DQS7_T PL_DDR4_DQS7_C PL_DDR4_DM7_B PL_DDR4_DQ64 PL_DDR4_DQ65 PL_DDR4_DQ66 PL_DDR4_DQ67 PL_DDR4_DQ68 PL_DDR4_DQ69 PL_DDR4_DQ70 PL_DDR4_DQ71 PL_DDR4_DQS8_T PL_DDR4_DQS8_C PL_DDR4_DM8_B
PL_DDR4_A0 PL_DDR4_A1 PL_DDR4_A2 PL_DDR4_A3 PL_DDR4_A4 PL_DDR4_A5 PL_DDR4_A6 PL_DDR4_A7 PL_DDR4_A8 PL_DDR4_A9 PL_DDR4_A10 PL_DDR4_A11 PL_DDR4_A12 PL_DDR4_A13
I/O Standard
Pin #
POD12_DCI
E2
POD12_DCI
A3
POD12_DCI
B8
POD12_DCI
C3
POD12_DCI
C7
POD12_DCI
C2
POD12_DCI
C8
POD12_DCI
D3
POD12_DCI
D7
DIFF_POD12_DCI
B7
DIFF_POD12_DCI
A7
POD12_DCI
E2
POD12_DCI
A3
POD12_DCI
B8
POD12_DCI
C3
POD12_DCI
C7
POD12_DCI
C2
POD12_DCI
C8
POD12_DCI
D3
POD12_DCI
D7
DIFF_POD12_DCI
B7
DIFF_POD12_DCI
A7
POD12_DCI
E2
COMMON
SSTL12_DCI
P3
SSTL12_DCI
P7
SSTL12_DCI
R3
SSTL12_DCI
N7
SSTL12_DCI
N3
SSTL12_DCI
P8
SSTL12_DCI
P2
SSTL12_DCI
R8
SSTL12_DCI
R2
SSTL12_DCI
R7
SSTL12_DCI
M3
SSTL12_DCI
T2
SSTL12_DCI
M7
SSTL12_DCI
T8
Component Memory
Pin Name
Ref. Des.
NF/UDM_B/UDBI_B
U18
DQ8
U73
DQ9
U73
DQ10
U73
DQ11
U73
DQ12
U73
DQ13
U73
DQ14
U73
DQ15
U73
UDQS_T
U73
UDQS_C
U73
NF/UDM_B/UDBI_B
U73
DQ8
U17
DQ9
U17
DQ10
U17
DQ11
U17
DQ12
U17
DQ13
U17
DQ14
U17
DQ15
U17
UDQS_T
U17
UDQS_C
U17
NF/UDM_B/UDBI_B
U17
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC_B A13
U17-U19 U73-U74 U17-U19 U73-U74 U17-U19 U73-U74 U17-U19 U73-U74 U17-U19 U73-U74 U17-U19 U73-U74 U17-U19 U73-U74 U17-U19 U73-U74 U17-U19 U73-U74 U17-U19 U73-U74 U17-U19 U73-U74 U17-U19 U73-U74 U17-U19 U73-U74 U17-U19 U73-U74
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Chapter 3: Board Component Descriptions
Table 6: DDR4 Memory 72-bit I/F to FPGA U1 Banks 64, 65, and 66 (cont'd)
FPGA (U1) Pin
Schematic Net Name
I/O Standard
BE54 BE53 BG54 BG53 BJ54 BH54 BK53 BK54 BH52 BG52 BJ53 BJ52 BL48 BH50 BH49 BP49
PL_DDR4_BA0 PL_DDR4_BA1 PL_DDR4_BG0 PL_DDR4_WE_B PL_DDR4_RAS_B PL_DDR4_CAS_B PL_DDR4_CK_T PL_DDR4_CK_C PL_DDR4_CKE PL_DDR4_ACT_B PL_DDR4_TEN PL_DDR4_ALERT_B PL_DDR4_PARITY PL_DDR4_RESET_B PL_DDR4_ODT PL_DDR4_CS_B
SSTL12_DCI SSTL12_DCI SSTL12_DCI SSTL12_DCI SSTL12_DCI SSTL12_DCI DIFF_SSTL12_DCI DIFF_SSTL12_DCI SSTL12_DCI SSTL12_DCI SSTL12_DCI SSTL12_DCI SSTL12_DCI LVCMOS12 SSTL12_DCI SSTL12_DCI
Pin #
N2 N8 M2 L2 L8 M8 K7 K8 K2 L3 N9 P9 T3 P1 K3 L7
Component Memory
Pin Name
Ref. Des.
BA0
U17-U19 U73-U74
BA1
U17-U19 U73-U74
BG0
U17-U19 U73-U74
WE_B/A14
U17-U19 U73-U74
RAS_B/A16
U17-U19 U73-U74
CAS_B_A15
U17-U19 U73-U74
CK_T
U17-U19 U73-U74
CK_C
U17-U19 U73-U74
CKE
U17-U19 U73-U74
ACT_B
U17-U19 U73-U74
TEN
U17-U19 U73-U74
ALERT_B
U17-U19 U73-U74
PAR
U17-U19 U73-U74
RESET_B
U17-U19 U73-U74
ODT
U17-U19 U73-U74
CS_B
U17-U19 U73-U74
The VCU128 DDR4 memory component interfaces adhere to the constraints guidelines documented in the "DDR3/DDR4 Design Guidelines" section of the UltraScale Architecture-Based FPGAs Memory IP LogiCORE IP Product Guide (PG150). The VCU128 board DDR4 memory component interface is a 40 impedance implementation.
For more information on the internal VREF, see the "Supply Voltages for the SelectIO Pins VREF" and the "Internal VREF" sections in the UltraScale Architecture SelectIO Resources User Guide (UG571). For more details about the Micron DDR4 component memory, see the Micron MT40A512M16LY data sheet at the Micron Technology website.
RLD3 Component Memory
[Figure 2, callout 5]
The 288 MB RLD3 72-bit wide component memory system is comprised of two 36-bit 1.125 Gb RLDRAM3 devices located at U39 and U37.
· Manufacturer: Micron · Part Number: MT44K32M36RB-107E · Description:
1.125 Gb (32 Mb x 36)
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Chapter 3: Board Component Descriptions
1.2V 168-ball BGA
Up to RL3-1866
The VCU128 XCVU37P FPGA RLDRAM3 interface performance is documented in the Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS923).
This memory system is connected to the XCVU37P HP banks 73, 74, and 75. The RLD3 0.6V VTT termination voltage (net RLD3_VTERM_0V6) is sourced from TI TPS51200DR linear regulator U92. The RLD3 memory interface bank VREF pins are not connected, which, coupled with an XDC set_property INTERNAL_VREF constraint, invoke the INTERNAL VREF mode. The connections between the RLD3 component memories and XCVU37P banks 73, 74, and 75 are listed in the following table.
Table 7: RLD3 Memory 72-bit I/F to FPGA U1 Banks 73, 74, and 75
FPGA (U1) Pin
K29 J30 K32 J31 L29 L31 L30 J32 K31 G30 H30 F31 G28 H29 G31 G32 H32 F28 E33 F29 E29 C32 F33 D30 D32 D29
Schematic Net Name
RLD3_72B_DQ0 RLD3_72B_DQ1 RLD3_72B_DQ2 RLD3_72B_DQ3 RLD3_72B_DQ4 RLD3_72B_DQ5 RLD3_72B_DQ6 RLD3_72B_DQ7 RLD3_72B_DQ8 RLD3_72B_DQ9 RLD3_72B_DQ10 RLD3_72B_DQ11 RLD3_72B_DQ12 RLD3_72B_DQ13 RLD3_72B_DQ14 RLD3_72B_DQ15 RLD3_72B_DQ16 RLD3_72B_DQ17 RLD3_72B_DQ18 RLD3_72B_DQ19 RLD3_72B_DQ20 RLD3_72B_DQ21 RLD3_72B_DQ22 RLD3_72B_DQ23 RLD3_72B_DQ24 RLD3_72B_DQ25
I/O Standard
SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12
Pin #
D11 E10 C8 C10 C12 B9 B11 A8 A10 J10 K11 K13 L8 L10 L12 M9 M11 N8 D3 E4 C6 C4 C2 B5 B3 A6
Component Memory
Pin Name
Ref. Des.
DQ0
U39
DQ1
U39
DQ2
U39
DQ3
U39
DQ4
U39
DQ5
U39
DQ6
U39
DQ7
U39
DQ8
U39
DQ9
U39
DQ10
U39
DQ11
U39
DQ12
U39
DQ13
U39
DQ14
U39
DQ15
U39
DQ16
U39
DQ17
U39
DQ18
U39
DQ19
U39
DQ20
U39
DQ21
U39
DQ22
U39
DQ23
U39
DQ24
U39
DQ25
U39
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Chapter 3: Board Component Descriptions
Table 7: RLD3 Memory 72-bit I/F to FPGA U1 Banks 73, 74, and 75 (cont'd)
FPGA (U1) Pin
D31 A31 B32 A33 B30 A30 C28 C29 A29 B28 G42 G41 H42 G40 H43 J42 H40 J40 J41 D44 F45 F44 D46 F46 E44 E46 G45 H45 B46 A46 C43 B45 A45 C45 C44 D42 A43 D40
Schematic Net Name
RLD3_72B_DQ26 RLD3_72B_DQ27 RLD3_72B_DQ28 RLD3_72B_DQ29 RLD3_72B_DQ30 RLD3_72B_DQ31 RLD3_72B_DQ32 RLD3_72B_DQ33 RLD3_72B_DQ34 RLD3_72B_DQ35 RLD3_72B_DQ36 RLD3_72B_DQ37 RLD3_72B_DQ38 RLD3_72B_DQ39 RLD3_72B_DQ40 RLD3_72B_DQ41 RLD3_72B_DQ42 RLD3_72B_DQ43 RLD3_72B_DQ44 RLD3_72B_DQ45 RLD3_72B_DQ46 RLD3_72B_DQ47 RLD3_72B_DQ48 RLD3_72B_DQ49 RLD3_72B_DQ50 RLD3_72B_DQ51 RLD3_72B_DQ52 RLD3_72B_DQ53 RLD3_72B_DQ54 RLD3_72B_DQ55 RLD3_72B_DQ56 RLD3_72B_DQ57 RLD3_72B_DQ58 RLD3_72B_DQ59 RLD3_72B_DQ60 RLD3_72B_DQ61 RLD3_72B_DQ62 RLD3_72B_DQ63
I/O Standard
SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12
Pin #
A4 J4 K3 K1 L6 L4 L2 M5 M3 N6 D11 E10 C8 C10 C12 B9 B11 A8 A10 J10 K11 K13 L8 L10 L12 M9 M11 N8 D3 E4 C6 C4 C2 B5 B3 A6 A4 J4
Component Memory
Pin Name
Ref. Des.
DQ26
U39
DQ27
U39
DQ28
U39
DQ29
U39
DQ30
U39
DQ31
U39
DQ32
U39
DQ33
U39
DQ34
U39
DQ35
U39
DQ0
U37
DQ1
U37
DQ2
U37
DQ3
U37
DQ4
U37
DQ5
U37
DQ6
U37
DQ7
U37
DQ8
U37
DQ9
U37
DQ10
U37
DQ11
U37
DQ12
U37
DQ13
U37
DQ14
U37
DQ15
U37
DQ16
U37
DQ17
U37
DQ18
U37
DQ19
U37
DQ20
U37
DQ21
U37
DQ22
U37
DQ23
U37
DQ24
U37
DQ25
U37
DQ26
U37
DQ27
U37
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Chapter 3: Board Component Descriptions
Table 7: RLD3 Memory 72-bit I/F to FPGA U1 Banks 73, 74, and 75 (cont'd)
FPGA (U1) Pin
C40 A39 A41 B41 B40 D41 B42 E41 J29 A28 G43 A40 D39 A38 B38 J34 K34 K37 C38 E36 B35 L35 D34 E39 A35 C35 E37 E38 C37 B36 F34 J37 C39 C34 B37 A36 D36 D37
Schematic Net Name
RLD3_72B_DQ64 RLD3_72B_DQ65 RLD3_72B_DQ66 RLD3_72B_DQ67 RLD3_72B_DQ68 RLD3_72B_DQ69 RLD3_72B_DQ70 RLD3_72B_DQ71 RLD3_72B_DM0 RLD3_72B_DM1 RLD3_72B_DM2 RLD3_72B_DM3
RLD3_72B_A0 RLD3_72B_A1 RLD3_72B_A2 RLD3_72B_A3 RLD3_72B_A4 RLD3_72B_A5 RLD3_72B_A6 RLD3_72B_A7 RLD3_72B_A8 RLD3_72B_A9 RLD3_72B_A10 RLD3_72B_A11 RLD3_72B_A12 RLD3_72B_A13 RLD3_72B_A14 RLD3_72B_A15 RLD3_72B_A16 RLD3_72B_A17 RLD3_72B_A18 RLD3_72B_A19 RLD3_72B_A20 RLD3_72B_BA0 RLD3_72B_BA1 RLD3_72B_BA2 RLD3_72B_BA3 RLD3_72B_WE_B
I/O Standard
SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 SSTL12
Pin #
K3 K1 L6 L4 L2 M5 M3 N6 B7 M7 B7 M7 E2 F5 F4 F9 F10 F12 G3 F1 G11 F13 H13 D1 H11 D13 H3 G2 H4 H10 G12 H1 F2 G9 G5 H8 H6 F6
Component Memory
Pin Name
Ref. Des.
DQ28
U37
DQ29
U37
DQ30
U37
DQ31
U37
DQ32
U37
DQ33
U37
DQ34
U37
DQ35
U37
DM0
U39
DM1
U39
DM0
U37
DM1
U37
A0
U37, U39
A1
U37, U39
A2
U37, U39
A3
U37, U39
A4
U37, U39
A5
U37, U39
A6
U37, U39
A7
U37, U39
A8
U37, U39
A9
U37, U39
A10
U37, U39
A11
U37, U39
A12
U37, U39
A13
U37, U39
A14
U37, U39
A15
U37, U39
A16
U37, U39
A17
U37, U39
A18
U37, U39
A19
U37, U39
NF_A20
U37, U39
BA0
U37, U39
BA1
U37, U39
BA2
U37, U39
BA3
U37, U39
WE_B
U37, U39
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Chapter 3: Board Component Descriptions
Table 7: RLD3 Memory 72-bit I/F to FPGA U1 Banks 73, 74, and 75 (cont'd)
FPGA (U1) Pin
E34 G37 F38 D35 A34 H37 H38 H34 H35 G38 F39 G35 G36 L33 K33 H33 G33 E31 E32 C30 B31 K41 K42 J44 H44 E42 E43 F40 F41 F30 E28 D45 A44
Schematic Net Name
RLD3_72B_REF_B RLD3_72B_CK_P RLD3_72B_CK_N RLD3_72B_RESET_B RLD3_72B_CS_B RLD3_72B_DK0_P RLD3_72B_DK0_N RLD3_72B_DK1_P RLD3_72B_DK1_N RLD3_72B_DK2_P RLD3_72B_DK2_N RLD3_72B_DK3_P RLD3_72B_DK3_N RLD3_72B_QK0_P RLD3_72B_QK0_N RLD3_72B_QK1_P RLD3_72B_QK1_N RLD3_72B_QK2_P RLD3_72B_QK2_N RLD3_72B_QK3_P RLD3_72B_QK3_N RLD3_72B_QK4_P RLD3_72B_QK4_N RLD3_72B_QK5_P RLD3_72B_QK5_N RLD3_72B_QK6_P RLD3_72B_QK6_N RLD3_72B_QK7_P RLD3_72B_QK7_N RLD3_72B_QVLD0 RLD3_72B_QVLD1 RLD3_72B_QVLD2 RLD3_72B_QVLD3
I/O Standard
SSTL12 SSTL12 SSTL12 SSTL12 SSTL12 DIFF_SSTL12 DIFF_SSTL12 DIFF_SSTL12 DIFF_SSTL12 DIFF_SSTL12 DIFF_SSTL12 DIFF_SSTL12 DIFF_SSTL12 DIFF_SSTL12 DIFF_SSTL12 DIFF_SSTL12 DIFF_SSTL12 DIFF_SSTL12 DIFF_SSTL12 DIFF_SSTL12 DIFF_SSTL12 DIFF_SSTL12 DIFF_SSTL12 DIFF_SSTL12 DIFF_SSTL12 DIFF_SSTL12 DIFF_SSTL12 DIFF_SSTL12 DIFF_SSTL12 SSTL12 SSTL12 SSTL12 SSTL12
Pin #
F8 H7 G7 A13 E12 D7 C7 K7 L7 D7 C7 K7 L7 D9 E8 K9 J8 D5 E6 K5 J6 D9 E8 K9 J8 D5 E6 K5 J6 J12 J2 J12 J2
Component Memory
Pin Name
Ref. Des.
REF_B
U37, U39
CK
U37, U39
CK_B
U37, U39
RESET_B
U37, U39
CS_B
U37, U39
DK0
U39
DK0_B
U39
DK1
U39
DK1_B
U39
DK0
U37
DK0_B
U37
DK1
U37
DK1_B
U37
QK0
U39
QK0_B
U39
QK1
U39
QK1_B
U39
QK2
U39
QK2_B
U39
QK3
U39
QK3_B
U39
QK0
U37
QK0_B
U37
QK1
U37
QK1_B
U37
QK2
U37
QK2_B
U37
QK3
U37
QK3_B
U37
QVLD0
U39
QVLD1
U39
QVLD0
U37
QVLD1
U37
The VCU128 RLD3 72-bit memory component interface adheres to the constraints guidelines documented in the "RLD3 Design Guidelines" section of the UltraScale Architecture-Based FPGAs Memory IP LogiCORE IP Product Guide (PG150). The VCU128 RLD3 memory component interface is a 40 impedance implementation.
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Chapter 3: Board Component Descriptions
For more information on the internal VREF, see the "Supply Voltages for the SelectIO Pins", "VREF", and "Internal VREF" sections in the UltraScale Architecture SelectIO Resources User Guide (UG571). For more details about the Micron RLD3 component memory, see the Micron MT44K32M36RB Data Sheet at the Micron Technology website.
QDR4 Component Memory
[Figure 2, callout 6]
The 4.5 GB QDR4 component memory system is comprised of one 144-Mbit density (4M × 36) QDR4 SRAM device located at U40.
· Manufacturer: Cypress · Part Number: CY7C4142KV13_106FCXC · Description:
144-Mbit density (4M × 36) Dual independent 36-bit bidirectional double data rate (DDR) data ports Supports concurrent read/write transactions on both ports Single address port used to control both data ports 1.2V 361-ball FCBGA Maximum operating frequency of 1066 MHz
The VCU128 XCVU37P FPGA QDR IV interface performance is documented in the Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS923).
The 72-bit wide QDR4 memory is connected to XCVU37P U1 HP banks 68, 69, and 70. The QDR4 memory interface bank VREF pins are not connected, which, coupled with an XDC set_property INTERNAL VREF constraint, invoke the INTERNAL VREF mode. The connections between the 72-bit interface QDR4 component memories and XCVU37P banks 68, 69, and 70 are listed in the following table.
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Chapter 3: Board Component Descriptions
Table 8: QDR4 Memory 72-bit I/F to FPGA U1 Banks 68, 69, and 70
FPGA (U1) Pin
BM14 BM13 BN15 BN12 BM15 BP13 BP14 BM12 BL15 BM9 BK9 BL10 BK10 BL8 BN10 BM10 BN9
BJ9 BL12 BK14 BJ12 BK15 BL13 BH14 BH15 BJ14 BJ13 BE9 BE10 BG13 BE11 BF10 BG12 BG9 BG10 BF12
Schematic Net Name
QDR4_DQA0 QDR4_DQA1 QDR4_DQA2 QDR4_DQA3 QDR4_DQA4 QDR4_DQA5 QDR4_DQA6 QDR4_DQA7 QDR4_DQA8 QDR4_DQA9 QDR4_DQA10 QDR4_DQA11 QDR4_DQA12 QDR4_DQA13 QDR4_DQA14 QDR4_DQA15 QDR4_DQA16 QDR4_DQA17 QDR4_DQA18 QDR4_DQA19 QDR4_DQA20 QDR4_DQA21 QDR4_DQA22 QDR4_DQA23 QDR4_DQA24 QDR4_DQA25 QDR4_DQA26 QDR4_DQA27 QDR4_DQA28 QDR4_DQA29 QDR4_DQA30 QDR4_DQA31 QDR4_DQA32 QDR4_DQA33 QDR4_DQA34 QDR4_DQA35
I/O Standard
QDR4 A-side Data
Component Memory
Pin #
Pin Name
C8
DQA0
B7
DQA1
C6
DQA2
D5
DQA3
D7
DQA4
A4
DQA5
F5
DQA6
A6
DQA7
A8
DQA8
H3
DQA9
H5
DQA10
J2
DQA11
J4
DQA12
B2
DQA13
E2
DQA14
G2
DQA15
G4
DQA16
B5
DQA17
C12
DQA18
B13
DQA19
C14
DQA20
D15
DQA21
D13
DQA22
A16
DQA23
F15
DQA24
A14
DQA25
A12
DQA26
H17
DQA27
H15
DQA28
J18
DQA29
J16
DQA30
B18
DQA31
E18
DQA32
G18
DQA33
G16
DQA34
B15
DQA35
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Chapter 3: Board Component Descriptions
Table 8: QDR4 Memory 72-bit I/F to FPGA U1 Banks 68, 69, and 70 (cont'd)
FPGA (U1) Pin
BP12 BP11 BH10 BH9 BP9 BP8 BJ11 BK11 BM8 BK13 BM3 BM4 R522(GND)1 R519(GND)1
H15 J15 J12 J11 H14 G13 J14 H12 H13 G11 E12 F10 E11 D10 E9 F9 F11 D11 E14 A14 D15 B15
Schematic Net Name
QDR4_DKA0_P QDR4_DKA0_N QDR4_DKA1_P QDR4_DKA1_N QDR4_QKA0_P QDR4_QKA0_N QDR4_QKA1_P QDR4_QKA1_N QDR4_QVLDA0 QDR4_QVLDA1 QDR4_LDA_N QDR4_RWA_N QDR4_DINVA0 QDR4_DINVA1
QDR4_DQB0 QDR4_DQB1 QDR4_DQB2 QDR4_DQB3 QDR4_DQB4 QDR4_DQB5 QDR4_DQB6 QDR4_DQB7 QDR4_DQB8 QDR4_DQB9 QDR4_DQB10 QDR4_DQB11 QDR4_DQB12 QDR4_DQB13 QDR4_DQB14 QDR4_DQB15 QDR4_DQB16 QDR4_DQB17 QDR4_DQB18 QDR4_DQB19 QDR4_DQB20 QDR4_DQB21
I/O Standard
QDR4 A-side Control
QDR4 B-side Data
Component Memory
Pin #
Pin Name
F4
DKA0_P
F3
DKA0_N
F16
DKA1_P
F17
DKA1_N
C4
QKA0_P
D3
QKA0_N
C16
QKA1_P
D17
QKA1_N
C3
QVLDA0
C17
QVLDA1
H8
LDA_N
H10
RWA_N
D8
DINVA0
D12
DINVA1
U8
DQB0
V7
DQB1
U6
DQB2
T5
DQB3
T7
DQB4
W4
DQB5
P5
DQB6
W6
DQB7
W8
DQB8
M3
DQB9
M5
DQB10
L2
DQB11
L4
DQB12
V2
DQB13
R2
DQB14
N2
DQB15
N4
DQB16
V5
DQB17
U12
DQB18
V13
DQB19
U14
DQB20
T15
DQB21
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Chapter 3: Board Component Descriptions
Table 8: QDR4 Memory 72-bit I/F to FPGA U1 Banks 68, 69, and 70 (cont'd)
FPGA (U1) Pin
F13 C15 F15 A15 F14 C12 A11 B13 B12 A8 A9 B11 B10 A10
K14 K13 C10 C9 H10 G10 E13 D12 D9 D14 BL2 BL3 R606(GND)1 R602(GND)1
BF5 BF1 BE1 BE3 BE4 BE5 BE6 BF2
Schematic Net Name
QDR4_DQB22 QDR4_DQB23 QDR4_DQB24 QDR4_DQB25 QDR4_DQB26 QDR4_DQB27 QDR4_DQB28 QDR4_DQB29 QDR4_DQB30 QDR4_DQB31 QDR4_DQB32 QDR4_DQB33 QDR4_DQB34 QDR4_DQB35
QDR4_DKB0_P QDR4_DKB0_N QDR4_DKB1_P QDR4_DKB1_N QDR4_QKB0_P QDR4_QKB0_N QDR4_QKB1_P QDR4_QKB1_N QDR4_QVLDB0 QDR4_QVLDB1 QDR4_LDB_N QDR4_RWB_N QDR4_DINVB0 QDR4_DINVB1
QDR4_A0 QDR4_A1 QDR4_A2 QDR4_A3 QDR4_A4 QDR4_A5 QDR4_A6 QDR4_A7
I/O Standard
QDR4 B-side Control Common
Component Memory
Pin #
Pin Name
T13
DQB22
W16
DQB23
P15
DQB24
W14
DQB25
W12
DQB26
M17
DQB27
M15
DQB28
L18
DQB29
L16
DQB30
V18
DQB31
R18
DQB32
N18
DQB33
N16
DQB34
V15
DQB35
P4
DKB0_P
P3
DKB0_N
P16
DKB1_P
P17
DKB1_N
U4
QKB0_P
T3
QKB0_N
U16
QKB1_P
T17
QKB1_N
U3
QVLDB0
U17
QVLDB1
H12
LDB_N
L10
RWB_N
T8
DINVB0
T12
DINVB1
F10
A0
G10
A1
N10
A2
G7
A3
G13
A4
J7
A5
J13
A6
L7
A7
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Chapter 3: Board Component Descriptions
Table 8: QDR4 Memory 72-bit I/F to FPGA U1 Banks 68, 69, and 70 (cont'd)
FPGA (U1) Pin
Schematic Net Name
I/O Standard
Component Memory
Pin #
Pin Name
BF3
QDR4_A8
L13
A8
BG2
QDR4_A9
N7
A9
BG3
QDR4_A10
N13
A10
BG4
QDR4_A11
M8
A11
BG5
QDR4_A12
M12
A12
BF7
QDR4_A13
F8
A13
BF8
QDR4_A14
F12
A14
BG7
QDR4_A15
P8
A15
BG8
QDR4_A16
P12
A16
BJ7
QDR4_A17
L9
A17
BH7
QDR4_A18
L11
A18_36M
BK8
QDR4_A19
J9
A19_72M
BJ8
QDR4_A20
J11
A20_144M
BJ6
QDR4_A21
G9
A21_288M
BK5
QDR4_A22
G11
A22_576M
BH6
QDR4_A23
N9
A23_1152M
BK4
QDR4_A24
N11
A24_2304M
BK6
QDR4_AP
P10
AP
BJ1
QDR4_AINV
M10
AINV
BH5
QDR4_CK_P
J10
CK_P
BH4
QDR4_CK_N
K10
CK_N
BJ3
QDR4_LBK0_N
A10
LBK0_N
BH1
QDR4_LBK1_N
B10
LBK1_N
BH2
QDR4_CFG_N
D10
CFG_N
BJ2
QDR4_PE_N
V10
PE_N
BK1
QDR4_RST_N
K18
RST_N
QDR4 U40 ZQ_ZT pin W10 is wired to 220 R604 to GND
Notes: 1. Resistors to GND are 100.
The VCU128 QDR-IV dual independent 36-bit bidirectional data port memory component interfaces adhere to the constraints guidelines documented in the "QDR-IV Design Guidelines" section of the UltraScale Architecture-Based FPGAs Memory IP LogiCORE IP Product Guide (PG150). The VCU128 QDR-IV memory component interface is a 40 impedance implementation.
For more information on the internal VREF, see the "Supply Voltages for the SelectIO Pins", "VREF", and "Internal VREF" sections in the UltraScale Architecture SelectIO Resources User Guide (UG571). For more details about the Cypress QDR-IV component memory, see the Cypress CY7C4142KV13_106FCXC Data Sheet at the Cypress Semiconductor website.
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Chapter 3: Board Component Descriptions
Quad SPI Flash Memory
[Figure 2, callout 7] VCU128 boards host a Micron MT25QU02GCBB8E12-0SIT serial NOR flash Quad SPI flash memory capable of holding the boot image for the XCVU37P FPGA. This interface supports the QSPI32 boot mode as defined in the UltraScale Architecture Configuration User Guide (UG570). The Quad SPI flash memory U46 provides 2 Gb of non-volatile storage that can be used for configuration and data storage. · Part number: MT25QU02GCBB8E12-0SIT (Micron) · Supply voltage: 1.8V · Datapath width: 4 bits · Data rate: various depending on single/dual/quad mode The Quad SPI circuitry is shown in the following figure.
Figure 7: Quad SPI (2 Gbit) Flash Memory
X21957-121918
The connections between the Quad SPI flash memory and the XCVU37P FPGA are listed in the following table.
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Chapter 3: Board Component Descriptions
Table 9: Quad-SPI Component Connections to FPGA U1
XCVC37P (U1) Pin
AW15 AY15 AY14 AY13 BD14 BC15
Net Name
QSPI_DQ0 QSPI_DQ1 QSPI_DQ2 QSPI_DQ3 QSPI _CLK QSPI_CS_B
Pin #
D3 D2 C4 D4 B2 C2
U46 Quad SPI Pin Name
DQ0 DQ1 DQ2_W_B DQ3_RST_HLD_B
C S_B
The UltraScale Architecture Configuration User Guide (UG570) provides FPGA configuration details. For more Quad SPI component information, see the Micron MT25QU02GCBB8E12-0SIT data sheet at the Micron Technology website.
USB JTAG Interface
[Figure 2, callout 24]
JTAG configuration is provided through a dual-function FTDI FT4232HL USB-to-JTAG/UART bridge device (U8) where a host computer accesses the VCU128 board JTAG chain through a type-A (PC host side) to micro-AB (VCU128 board side J2) USB cable.
A 2 mm JTAG header (J4) is also provided in parallel for access by Xilinx® download cables, such as the Platform Cable USB II. JTAG initiated configuration takes priority over the configuration method selected through the FPGA mode pins M[2:0], wired to SW1 positions [2:4]. The JTAG chain of the VCU128 board is shown in the following figure.
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Chapter 3: Board Component Descriptions
FTDI USB JTAG (U8)
JTAG 2 mm Conn. (J4)
TCK TMS
TDI TDO
TDO TDI TMS TCK
Figure 8: JTAG Chain Block Diagram
U50 3.3V 1.8V
Level-shift
TCK TMS
U1 FPGA
TDI
TDO
SPST Bus Switch U72
N.C.
J18 FMC+ HSPC
Connector
TMS TCK TDO TDI
U75 1.8V 3.3V
Level-shift
X21649-110618
FMCP Connector JTAG Bypass
When an FMC is attached to the VCU128 board FMC+ HSPC connector J18, it is automatically added to the JTAG chain through the electronically controlled single-pole single-throw (SPST) switch U72. The SPST switch is in a normally closed state and transitions to an open state when the FMC is attached. Switch U72 adds an attached FMC to the FPGA JTAG chain as determined by the FMCP_HSPC_PRSNT_M2C_B signal.
IMPORTANT! The attached FMC must implement a TDI-to-TDO connection through a device or bypass jumper to ensure that the JTAG chain connects to the FPGA U1.
The JTAG connectivity on the VCU128 board allows a host computer to download bitstreams to the FPGA using the Xilinx tools. In addition, the JTAG connector allows debug tools such as the Vivado® serial I/O analyzer or a software debugger to access the FPGA. The Xilinx tools can also program the Quad SPI flash memory.
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Chapter 3: Board Component Descriptions
USB UART Interface
[Figure 2, callout 24] The FT4232HL U8 multi-function USB-UART on the VCU128 board provides three level-shifted UART connections through the single micro-AB USB connector J2. · Channel A is configured in JTAG mode to support the JTAG chain · Channel B implements 4-wire UART0 (level-shifted) FPGA U1 bank 67 connections · Channel C implements 4-wire UART1 (level-shifted) FPGA U1 bank 67 connections · Channel D implements 2-wire (level-shifted) SYSCTLR U42 bank 501 connections The USB UART interface circuit is shown in the following figure. The FTDI FT4232HL data sheet is available on the Future Technology Devices International Ltd. website.
Figure 9: FTDI USB JTAG/UART Circuit
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Chapter 3: Board Component Descriptions
Clock Generation
[Figure 2, callout 10-18] The VCU128 evaluation board clock sources to the FPGA are listed in the following table.
Table 10: Board Clock Sources
Clock Name
DDR4 clock 100 MHz QDR4 clock 100 MHz RLD3 clock 100 MHz
QSFP1 clock 156.250 MHz QSFP2 clock 156.250 MHz QSFP3 clock 156.250 MHz QSFP4 clock 156.250 MHz
QSFP GTY131 REFCLK1 SMA clock FPGA U1 bank 67 GPIO user SMA clock
QSFP1/2 jitter attenuated clock
Clock Ref. Des.
Description
Memory Interface Clocks
U76
SiTime SiT9120AI 3.3V fixed frequency
100.000 MHz (DDR4_CLK_100MHZ_P/N)
U96
SiTime SiT9120AI 3.3V fixed frequency
100.000 MHz (QDR4_CLK_100MHZ_P/N)
U45
SiTime SiT9120AI 3.3V fixed frequency
100.000 MHz (RLD3_CLK_100MHZ_P/N)
QSFP Interface Clocks
U95
Silicon Labs Si570 3.3V LVDS I2C
programmable oscillator, 156.250 MHz
default. (QSFP1_SI570_CLOCK_P/N)
U90
Silicon Labs Si570 3.3V LVDS I2C
programmable oscillator, 156.250 MHz
default. (QSFP2_SI570_CLOCK_P/N)
U82
Silicon Labs Si570 3.3V LVDS I2C
programmable oscillator, 156.250 MHz
default. (QSFP3_SI570_CLOCK_P/N)
U80
Silicon Labs Si570 3.3V LVDS I2C
programmable oscillator, 156.250 MHz
default. (QSFP4_SI570_CLOCK_P/N)
SMA GTY REFCLK and User Clock
SMA J24 (P)/SMA J26 (N)
Bank 131 series capacitor coupled SMA clock (SMA_REFCLK_INPUT_P/N)
SMA J12 (P)/SMA J13 (N)
Bank 67 QBC direct connect GPIO SMA (SMA_CLK_OUTPUT_P/N)
QSFP1/2 recovery clocks
U87
Silicon Labs Si5328B LVDS precision clock,
multiplier/jitter attenuator. See Jitter
Attenuated Clock (SI5328_CLOCK1/2_P/N)
The following table lists the VCU128 clock sources-to-FPGA U1 connections.
Table 11: Clock Sources to XCVU37P FPGA U1 Connections
Clock Source Device/ U#.Pin#
SIT9120AI/U76.4 SIT9120AI/U76.5 SIT9120AI/U96.4
Schematic Net Name
I/O Standard
Memory Interface Clocks
DDR4_CLK_100MHZ_P
LVDS
DDR4_CLK_100MHZ_N
LVDS
QDR4_CLK_100MHZ_P
LVDS
FPGA (U1) Pin
BH51 BJ51 BJ4
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Table 11: Clock Sources to XCVU37P FPGA U1 Connections (cont'd)
Clock Source Device/ U#.Pin#
Schematic Net Name
I/O Standard
SIT9120AI/U96.5
QDR4_CLK_100MHZ_N
LVDS
SIT9120AI/U45.4
RLD3_CLK_100MHZ_P
LVDS
SIT9120AI/U45.5
RLD3_CLK_100MHZ_N
LVDS
SI570/U95.4 SI570/U95.5 SI570/U90.4 SI570/U90.5 SI570/U82.4 SI570/U82.5 SI570/U80.4 SI570/U80.5
QSFP Interface Clocks
QSFP1_SI570_CLOCK_P
1
QSFP1_SI570_CLOCK_N
1
QSFP2_SI570_CLOCK_P
1
QSFP2_SI570_CLOCK_N
1
QSFP3_SI570_CLOCK_P
1
QSFP3_SI570_CLOCK_N
1
QSFP4_SI570_CLOCK_P
1
QSFP4_SI570_CLOCK_N
1
SMA J24.1 SMA J26.1 SMA J12.1 SMA J13.1
SMA GTY REFCLK and User Clock
SMA_REFCLK_INPUT_P
1
SMA_REFCLK_INPUT_N
1
SMA_CLK_OUTPUT_P
2
SMA_CLK_OUTPUT_N
2
SI5328B/U87.29 SI5328B/U87.28 SI5328B/U87.35 SI5328B/U87.34
QSFP1/2 Recovery Clocks
SI5328_CLOCK1_P
1
SI5328_CLOCK1_P
1
SI5328_CLOCK2_P
1
SI5328_CLOCK2_P
1
Notes: 1. Series capacitor coupled, MGT connections I/O standard is not applicable. 2. Signal amplitude not to exceed FPGA U1 bank 67 VCCO = VCC1V8 rail = 1.8V.
FPGA (U1) Pin
BK3 F35 F36
P42 P43 T42 T43 Y42 Y43 AB42 AB43
AA40 AA41 BK26 BL25
R40 R41 W40 W41
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DDR4 Interface Clock
[Figure 2, callout 10] The VCU128 evaluation board has a SiTime 100 MHz fixed frequency low-jitter 3.3V LVDS differential oscillator (U76) connected to FPGA U1 HP bank 66 DDR4 interface GC pins BH51 (P) and BJ51 (N) and is series capacitor coupled. · Fixed frequency oscillator: SiTime SIT9120AI-2D3-33E100.0000 (100 MHz) · 0.6 ps RMS phase jitter (random) over 12 kHz to 20 MHz bandwidth · 3.3V LVDS differential output The DDR4 interface fixed frequency clock circuit is shown in the following figure.
Figure 10: DDR4 Interface Clock
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Chapter 3: Board Component Descriptions
QDR4 Interface Clock
[Figure 2, callout 12] The VCU128 evaluation board has a SiTime 100 MHz fixed frequency low-jitter 3.3V LVDS differential oscillator (U96) connected to FPGA U1 HP bank 69 QDR4 interface GC pins BJ4 (P) and BK3 (N) and is series capacitor coupled. · Fixed frequency oscillator: SiTime SIT9120AI-2D3-33E100.0000 (100 MHz) · 0.6 ps RMS phase jitter (random) over 12 kHz to 20 MHz bandwidth · 3.3V LVDS differential output The QDR4 interface fixed frequency clock circuit is shown in the following figure.
Figure 11: QDR4 Interface Clock
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Chapter 3: Board Component Descriptions
RLD3 Interface Clock
[Figure 2, callout 11] The VCU128 evaluation board has a SiTime 100 MHz fixed frequency low-jitter 3.3V LVDS differential oscillator (U45) connected to FPGA U1 HP bank 74 RLD3 interface GC pins F35 (P) and F36 (N) and is series capacitor coupled. · Fixed frequency oscillator: SiTime SIT9120AI-2D3-33E100.0000 (100 MHz) · 0.6 ps RMS phase jitter (random) over 12 kHz to 20 MHz bandwidth · 3.3V LVDS differential output The RLD3 interface fixed frequency clock circuit is shown in the following figure. The SiTime SiT9120AI data sheet is available on the SiTime Corp. website.
Figure 12: RLD3 Interface Clock
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Chapter 3: Board Component Descriptions
Programmable QSFP1 Clock
[Figure 2, callout 13] The VCU128 evaluation board has a SI570 I2C programmable low-jitter 3.3V LVDS differential oscillator (U95) connected to FPGA U1 GTY bank 135 MGTREFCLK0 P/N pins P42 and P43 (series capacitor coupled), respectively. On power-up, the U95 SI570 user clock defaults to an output frequency of 156.250 MHz. The Zynq-7000 SoC system controller or FPGA implemented user IP can change the output frequency within the range of 10 MHz to 810 MHz through an I2C interface. Power cycling the VCU128 evaluation board resets the QSFP1 clock to the default frequency of 156.250 MHz. · Programmable oscillator: Silicon Labs Si570BAB0000544DG (10 MHz-810 MHz) · Frequency tolerance: 50 ppm · 3.3V LVDS differential output The programmable QSFP1 clock circuit is shown in the following figure.
Figure 13: QSFP1 Clock
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Chapter 3: Board Component Descriptions
Programmable QSFP2 Clock
[Figure 2, callout 14] The VCU128 evaluation board has a SI570 I2C programmable low-jitter 3.3V LVDS differential oscillator (U90) connected to FPGA U1 GTY bank 134 MGTREFCLK0 P/N pins T42 and T43 (series capacitor coupled), respectively. On power-up, the U90 SI570 user clock defaults to an output frequency of 156.250 MHz. The Zynq-7000 SoC system controller or FPGA implemented user IP can change the output frequency within the range of 10 MHz to 810 MHz through an I2C interface. Power cycling the VCU128 evaluation board resets the QSFP2 clock to the default frequency of 156.250 MHz. · Programmable oscillator: Silicon Labs Si570BAB0000544DG (10 MHz-810 MHz) · Frequency tolerance: 50 ppm · 3.3V LVDS differential output The programmable QSFP2 clock circuit is shown in the following figure.
Figure 14: QSFP2 Clock
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Chapter 3: Board Component Descriptions
Programmable QSFP3 Clock
[Figure 2, callout 15] The VCU128 evaluation board has a SI570 I2C programmable low-jitter 3.3V LVDS differential oscillator (U82) connected to FPGA U1 GTY bank 132 MGTREFCLK0 P/N pins Y42 and Y43 (series capacitor coupled), respectively. On power-up, the U82 SI570 user clock defaults to an output frequency of 156.250 MHz. The Zynq-7000 SoC system controller or FPGA implemented user IP can change the output frequency within the range of 10 MHz to 810 MHz through an I2C interface. Power cycling the VCU128 evaluation board resets the QSFP3 clock to the default frequency of 156.250 MHz. · Programmable oscillator: Silicon Labs Si570BAB0000544DG (10 MHz-810 MHz) · Frequency tolerance: 50 ppm · 3.3V LVDS differential output The programmable QSFP3 clock circuit is shown in the following figure.
Figure 15: QSFP3 Clock
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Chapter 3: Board Component Descriptions
Programmable QSFP4 Clock
[Figure 2, callout 16] The VCU128 evaluation board has a SI570 I2C programmable low-jitter 3.3V LVDS differential oscillator (U80) connected to FPGA U1 GTY bank 131 MGTREFCLK0 P/N pins AB42 and AB43 (series capacitor coupled), respectively. On power-up, the U80 SI570 user clock defaults to an output frequency of 156.250 MHz. The Zynq-7000 SoC system controller or FPGA implemented user IP can change the output frequency within the range of 10 MHz to 810 MHz through an I2C interface. Power cycling the VCU128 evaluation board resets the QSFP4 clock to the default frequency of 156.250 MHz · Programmable oscillator: Silicon Labs Si570BAB0000544DG (10 MHz-810 MHz) · Frequency tolerance: 50 ppm · 3.3V LVDS differential output The programmable QSFP4 clock circuit is shown in the following figure.
Figure 16: QSFP4 Clock
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Chapter 3: Board Component Descriptions
QSFP SMA Clock
[Figure 2, callout 18] The VCU128 board provides a pair of SMAs for differential user clock input into FPGA U1 GTY bank 131. The P-side SMA J24 signal SMA_REFCLK_INPUT_P is connected to FPGA U1 GTY bank 131 MGTREFCLK1P pin AA40, with the N-side SMA J26 signal SMA_REFCLK_INPUT_N connected to U1 GTY bank 131 MGTREFCLK1N pin AA41. The transceiver reference clock pin absolute input voltage range is 0.5V min. to 1.3V max. The user SMA MGT clock circuit is shown in the following figure.
Figure 17: QSFP SMA Clock
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Chapter 3: Board Component Descriptions
User SMA Clock
[Figure 2, callout 27] The VCU128 board provides a pair of SMAs for differential user clock I/O on FPGA U1 HP bank 67. The P-side SMA J12 net SMA_CLK_OUTPUT_P is connected to FPGA U1 HP bank 67 QBC pin BK26. The N-side SMA J13 net SMA_CLK_OUTPUT_N is connected to FPGA U1 HP bank 67 QBC pin BL25. Bank 67 VCC1V8 VCCO is nominally 1.8V. Any signal connected to the SMA_CLK_OUTPUT SMA connectors in input mode must be equal to or less than the VCCO for bank 67. This value must be confirmed prior to applying signals to the SMA_CLK_OUTPUT connectors.
Figure 18: User SMA Clock
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Chapter 3: Board Component Descriptions
Jitter Attenuated Clock
[Figure 2, callout 17]
The VCU128 board includes a Silicon Labs Si5328B jitter attenuator U87 on the back side of the board. FPGA U1 bank 67 implements two QSFP RX differential clocks (QSFP1_RECCLK_P, pin BH26 and QSFP1_RECCLK_N, pin BH25, and QSFP2_RECCLK_P, pin BJ26 and QSFP2_RECCLK_N, pin BK25) for jitter attenuation.
The jitter attenuated clock pair (SI5328_CLOCK1_C_P (U87 output pin 28), SI5328_CLOCK1_C_N (U87 output pin 29) is routed as a reference clock to FPGA U1 QSFP2 I/F GTY Quad 134 inputs MGTREFCLK1P (U1 pin R40) and MGTREFCLK1N (U1 pin R41).
The jitter attenuated clock pair (SI5328_CLOCK2_C_P (U87 output pin 35), SI5328_CLOCK2_C_N (U87 output pin 34) is routed as a reference clock to FPGA U1 QSFP3 I/F GTY Quad 132 inputs MGTREFCLK1P (U1 pin W40) and MGTREFCLK1N (U1 pin W41).
The primary purpose of this clock is to support synchronous protocols, such as common packet radio interface (CPRI) or open base station architecture initiative (OBSAI). These synchronous protocols perform clock recovery from user-supplied QSFP/QSFP+ modules, and use the jitter attenuated recovered clock to drive the reference clock inputs of a GTY transceiver.
The jitter attenuated clock circuit is shown in the following figure.
Figure 19: QSFP Recovery Clock
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Chapter 3: Board Component Descriptions
The SI5328B U87 I2C interface is connected to port 1 of the I2C0 bus TCA9548A U53 bus switch and can be configured by either the U42 system controller or U1 FPGA IP. The system controller configures SI5328B U87 in free-run mode or automatically switches over to one of two recovered clock inputs for synchronous operation. Enabling the jitter attenuation feature requires additional user programming through the I2C bus. The Silicon Labs Si570 and Si5328B data sheets are available on the Silicon Labs website.
GTY Transceivers
The GTY transceivers in the XCVU37P are grouped into four channels or quads. The XCVU37P has twelve GTY quads on the left side of the device and twelve GTY Quads on the right side of the device. The VCU128 board provides access to 14 of the 24 GTY Quads: · Four of the GTY Quads are wired to QSFP[1:4] Module Connectors (J42, J39, J35, J32) · Six of the GTY Quads are wired to FMC+ HSPC connector DP[0:23] (J18) · Four of the GTY Quads are wired to the PCIe 16-lane edge connector (P1) · Ten GTY Quads are not used (GTYs 130, 133, 228-235) The reference clock for a Quad can be sourced from the Quad above or the Quad below the GTY Quad of interest.
Right-side Quads
The ten connected GTY Quads on the right side of the XCVU37P FPGA are described in this section (MGTY133 and MGTY130 are not used). Quad 135 · MGTREFCLK0 QSFP1_SI570_CLOCK_P/N · MGTREFCLK1 NC · Four GTY transceivers allocated to QSFP1_TX/RX[1:4]_P/N Quad 134 · MGTREFCLK0 QSFP2_SI570_CLOCK_P/N · MGTREFCLK1 SI5328_CLOCK1_C_P/N · Four GTY transceivers allocated to QSFP2_TX/RX[1:4]_P/N Quad 132 · MGTREFCLK0 QSFP3_SI570_CLOCK_P/N
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Chapter 3: Board Component Descriptions
· MGTREFCLK1 SI5328_CLOCK2_C_P/N · Four GTY transceivers allocated to QSFP3_TX/RX[1:4]_P/N Quad 131 · MGTREFCLK0 QSFP4_SI570_CLOCK_P/N · MGTREFCLK1 SMA_REFCLK_INPUT_P/N · Four GTY transceivers allocated to QSFP4_TX/RX[1:4]_P/N Quad 129 · MGTREFCLK0 - FMCP_HSPC_GBTCLK5_M2C_P/N · NC · Four GTY transceivers allocated to FMCP_HSPC_DP[20:23] Quad 128 · MGTREFCLK0 - FMCP_HSPC_GBTCLK4_M2C_P/N · NC · Four GTY transceivers allocated to FMCP_HSPC_DP[16:19] Quad 127 · MGTREFCLK0 FMCP_HSPC_GBTCLK3_M2C_P/N · NC · Four GTY transceivers allocated to FMCP_HSPC_DP[12:15] Quad 126 · MGTREFCLK0 FMCP_HSPC_GBTCLK2_M2C_P/N · NC · Four GTY transceivers allocated to FMCP_HSPC_DP[8:11] Quad 125 · MGTREFCLK0 FMCP_HSPC_GBTCLK1_M2C_P/N · NC · Four GTY transceivers allocated to FMCP_HSPC_DP[4:7] Quad 124 · MGTREFCLK0 FMCP_HSPC_GBTCLK0_M2C_P/N · NC
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Chapter 3: Board Component Descriptions
· Four GTY transceivers allocated to FMCP_HSPC_DP[0:3]
The XCVU37P right-side GTY transceiver interface assignments are shown in the following figure.
Figure 20: XCVU37P Right-side GTY Transceiver Assignments
BANK 135 MGTY_135_0 QSFP1_TX1/RX1 MGTY_135_1 QSFP1_TX2/RX2 MGTY_135_2 QSFP1_TX3/RX3 MGTY_135_3 QSFP1_TX4/RX4
MGTY_135_REFCLK0 QSFP1_SI570_CLOCK MGTY_135_REFCLK1 NC
BANK 128 MGTY_128_0 FMCP_HSPC_DP16 MGTY_128_1 FMCP_HSPC_DP17 MGTY_128_2 FMCP_HSPC_DP18 MGTY_128_3 FMCP_HSPC_DP19
MGTY_128_REFCLK0 FMCP_HSPC_GBTCLK4_M2C MGTY_128_REFCLK1 NC
BANK 134 MGTY_134_0 QSFP2_TX1/RX1 MGTY_134_1 QSFP2_TX2/RX2 MGTY_134_2 QSFP2_TX3/RX3 MGTY_134_3 QSFP2_TX4/RX4
MGTY_134_REFCLK0 QSFP2_SI570_CLOCK MGTY_134_REFCLK1 SI5328_CLOCK1_C
BANK 132 MGTY_132_0 QSFP3_TX1/RX1 MGTY_132_1 QSFP3_TX2/RX2 MGTY_132_2 QSFP3_TX3/RX3 MGTY_132_3 QSFP3_TX4/RX4
MGTY_132_REFCLK0 QSFP3_SI570_CLOCK MGTY_132_REFCLK1 SI5328_CLOCK2_C
BANK 127 MGTY_127_0 FMCP_HSPC_DP12 MGTY_127_1 FMCP_HSPC_DP13 MGTY_127_2 FMCP_HSPC_DP14 MGTY_127_3 FMCP_HSPC_DP15
MGTY_127_REFCLK0 FMCP_HSPC_GBTCLK3_M2C MGTY_127_REFCLK1 NC
BANK 126 MGTY_126_0 FMCP_HSPC_DP8 MGTY_126_1 FMCP_HSPC_DP9 MGTY_126_2 FMCP_HSPC_DP10 MGTY_126_3 FMCP_HSPC_DP11
MGTY_126_REFCLK0 FMCP_HSPC_GBTCLK2_M2C MGTY_126_REFCLK1 NC
BANK 131 MGTY_131_0 QSFP4_TX1/RX1 MGTY_131_1 QSFP4_TX2/RX2 MGTY_131_2 QSFP4_TX3/RX3 MGTY_131_3 QSFP4_TX4/RX4
MGTY_131_REFCLK0 QSFP4_SI570_CLOCK MGTY_131_REFCLK1 SMA_REFCLK_INPUT
BANK 125 MGTY_125_0 FMCP_HSPC_DP4 MGTY_125_1 FMCP_HSPC_DP5 MGTY_125_2 FMCP_HSPC_DP6 MGTY_125_3 FMCP_HSPC_DP7
MGTY_125_REFCLK0 FMCP_HSPC_GBTCLK1_M2C MGTY_125_REFCLK1 NC
BANK 129 MGTY_129_0 FMCP_HSPC_DP20 MGTY_129_1 FMCP_HSPC_DP21 MGTY_129_2 FMCP_HSPC_DP22 MGTY_129_3 FMCP_HSPC_DP23
MGTY_129_REFCLK0 FMCP_HSPC_GBTCLK5_M2C MGTY_129_REFCLK1 NC
BANK 124 MGTY_124_0 FMCP_HSPC_DP0 MGTY_124_1 FMCP_HSPC_DP1 MGTY_124_2 FMCP_HSPC_DP2 MGTY_124_3 FMCP_HSPC_DP3
MGTY_124_REFCLK0 FMCP_HSPC_GBTCLK0_M2C MGTY_124_REFCLK1 NC
X21650-092618
Right-side GTY Transceiver Connectivity
The following tables list the connectivity of the ten XCVU37P FPGA U1 right-side GTY transceivers.
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Chapter 3: Board Component Descriptions
Table 12: XCVU37P U1 GTY Transceiver Bank 135 Connections
MGT FPGA Bank (U1) Pin
FPGA (U1) Pin Name
G48
MGTYTXP0_135
G49
MGTYTXN0_135
G53
MGTYRXP0_135
G54
MGTYRXN0_135
E48
MGTYTXP1_135
E49
MGTYTXN1_135
F51
MGTYRXP1_135
F52
MGTYRXN1_135
C48
MGTYTXP2_135
GTY bank
C49
135
E53
MGTYTXN2_135 MGTYRXP2_135
E54
MGTYRXN2_135
A49
MGTYTXP3_135
A50
MGTYTXN3_135
D51
MGTYRXP3_135
D52
MGTYRXN3_135
P42
MGTREFCLK0P_135
P43
MGTREFCLK0N_135
M42
MGTREFCLK1P_135
M43
MGTREFCLK1N_135
Notes: 1. Series 0.01 µF capacitor coupled.
Schematic Net Name
QSFP1_TX1_P QSFP1_TX1_N QSFP1_RX1_P QSFP1_RX1_N QSFP1_TX2_P QSFP1_TX2_N QSFP1_RX2_P QSFP1_RX2_N QSFP1_TX3_P QSFP1_TX3_N QSFP1_RX3_P QSFP1_RX3_N QSFP1_TX4_P QSFP1_TX4_N QSFP1_RX4_P QSFP1_RX4_N QSFP_SI570_CLOCK_P1 QSFP_SI570_CLOCK_N1
Connected Connected Connected
Pin
Pin Name Device
36
TX1P
37
TX1N
17
RX1P
18
RX1N
3
TX2P
2
TX2N
22
RX2P
21
RX2N
QSFP1 J42
33
TX3P
34
TX3N
14
RX3P
15
RX3N
6
TX4P
5
TX4N
25
RX4P
24
RX4N
4
OUT
U95 SI570 I2C
5
OUT_B
prog. osc.
NC
NC
NC
NC
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Table 13: XCVU37P U1 GTY Transceiver Bank 134 Connections
MGT FPGA Bank (U1) Pin
FPGA (U1) Pin Name
L48
MGTYTXP0_134
L49
MGTYTXN0_134
L53
MGTYRXP0_134
L54
MGTYRXN0_134
L44
MGTYTXP1_134
L45
MGTYTXN1_134
K51
MGTYRXP1_134
K52
MGTYRXN1_134
K46
MGTYTXP2_134
GTY bank
K47
134
J53
MGTYTXN2_134 MGTYRXP2_134
J54
MGTYRXN2_134
J48
MGTYTXP3_134
J49
MGTYTXN3_134
H51
MGTYRXP3_134
H52
MGTYRXN3_134
T42
MGTREFCLK0P_134
T43
MGTREFCLK0N_134
R40
MGTREFCLK1P_134
R41
MGTREFCLK1N_134
Notes: 1. Series 0.01 µF capacitor coupled.
Schematic Net Name
Connected Connected Connected
Pin
Pin Name Device
QSFP2_TX1_P
36
TX1P
QSFP2_TX1_N
37
TX1N
QSFP2_RX1_P
17
RX1P
QSFP2_RX1_N
18
RX1N
QSFP2_TX2_P
3
TX2P
QSFP2_TX2_N
2
TX2N
QSFP2_RX2_P
22
RX2P
QSFP2_RX2_N
21
RX2N
QSFP2_TX3_P
33
TX3P
QSFP2_TX3_N
34
TX3N
QSFP2_RX3_P
14
RX3P
QSFP2_RX3_N
15
RX3N
QSFP2_TX4_P
6
TX4P
QSFP2_TX4_N
5
TX4N
QSFP2_RX4_P
25
RX4P
QSFP2_RX4_N
24
QSFP2_SI570_CLOCK_P1
4
QSFP2_SI570_CLOCK_N1
5
SI5328_CLOCK1_C_P1
28
SI5328_CLOCK1_C_N1
29
RX4N OUT OUT_B CKOUT1_P CKOUT1_N
U90 SI570 I2C prog. osc.
U87 SI5328B jitter atten.
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Chapter 3: Board Component Descriptions
Table 14: XCVU37P U1 GTY Transceiver Bank 132 Connections
MGT FPGA Bank (U1) Pin
FPGA (U1) Pin Name
V46
MGTYTXP0_132
V47
MGTYTXN0_132
U53
MGTYRXP0_132
U54
MGTYRXN0_132
U44
MGTYTXP1_132
U45
MGTYTXN1_132
U49
MGTYRXP1_132
U50
MGTYRXN1_132
T46
MGTYTXP2_132
GTY bank
T47
132
T51
MGTYTXN2_132 MGTYRXP2_132
T52
MGTYRXN2_132
R44
MGTYTXP3_132
R45
MGTYTXN3_132
R53
MGTYRXP3_132
R54
MGTYRXN3_132
Y42
MGTREFCLK0P_132
Y43
MGTREFCLK0N_132
W40
MGTREFCLK1P_132
W41
MGTREFCLK1N_132
Notes: 1. Series 0.01 µF capacitor coupled.
Schematic Net Name
Connected Connected Connected
Pin
Pin Name Device
QSFP3_TX1_P
36
TX1P
QSFP3_TX1_N
37
TX1N
QSFP3_RX1_P
17
RX1P
QSFP3_RX1_N
18
RX1N
QSFP3_TX2_P
3
TX2P
QSFP3_TX2_N
2
TX2N
QSFP3_RX2_P
22
RX2P
QSFP3_RX2_N QSFP3_TX3_P
21
RX2N
QSFP2 J35
33
TX3P
QSFP3_TX3_N
34
TX3N
QSFP3_RX3_P
14
RX3P
QSFP3_RX3_N
15
RX3N
QSFP3_TX4_P
6
TX4P
QSFP3_TX4_N
5
TX4N
QSFP3_RX4_P
25
RX4P
QSFP3_RX4_N
24
QSFP3_SI570_CLOCK_P 1
4
QSFP3_SI570_CLOCK_N1
5
SI5328_CLOCK2_C_P1
35
SI5328_CLOCK2_C_N1
34
RX4N OUT OUT_B CKOUT2_P CKOUT2_N
U82 SI570 I2C prog. osc.
U87 SI5328B jitter atten.
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Table 15: XCVU37P U1 GTY Transceiver Bank 131 Connections
MGT FPGA Bank (U1) Pin
FPGA (U1) Pin Name
AA44
MGTYTXP0_131
AA45
MGTYTXN0_131
AA53
MGTYRXP0_131
AA54
MGTYRXN0_131
Y46
MGTYTXP1_131
Y47
MGTYTXN1_131
Y51
MGTYRXP1_131
Y52
MGTYRXN1_131
W48
MGTYTXP2_131
GTY bank 131
W49 W53
MGTYTXN2_131 MGTYRXP2_131
W54
MGTYRXN2_131
W44
MGTYTXP3_131
W45
MGTYTXN3_131
V51
MGTYRXP3_131
V52
MGTYRXN3_131
AB42
MGTREFCLK0P_131
AB43
MGTREFCLK0N_131
AA40
MGTREFCLK1P_131
AA41
MGTREFCLK1N_131
Notes: 1. Series 0.01 µF capacitor coupled.
Schematic Net Name
Connected Connected Connected
Pin
Pin Name Device
QSFP4_TX1_P
36
TX1P
QSFP4_TX1_N
37
TX1N
QSFP4_RX1_P
17
RX1P
QSFP4_RX1_N
18
RX1N
QSFP4_TX2_P
3
TX2P
QSFP4_TX2_N
2
TX2N
QSFP4_RX2_P
22
RX2P
QSFP4_RX2_N QSFP4_TX3_P
21
RX2N
QSFP2 J32
33
TX3P
QSFP4_TX3_N
34
TX3N
QSFP4_RX3_P
14
RX3P
QSFP4_RX3_N
15
RX3N
QSFP4_TX4_P
6
TX4P
QSFP4_TX4_N
5
TX4N
QSFP4_RX4_P
25
RX4P
QSFP4_RX4_N
24
QSFP4_SI570_CLOCK_P1
4
QSFP4_SI570_CLOCK_N1
5
SMA_REFCLK_INPUT_P1
1
SMA_REFCLK_INPUT_N1
1
RX4N OUT OUT_B SIG SIG
U80 SI570 I2C prog. osc.
SMA J24 (P) SMA J26 (N)
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Table 16: XCVU37P U1 GTY Transceiver Bank 129 Connections
MGT Bank
FPGA (U1) Pin
FPGA (U1) Pin Name
Schematic Net Name
Connected Connected Pin Connected
Pin
Name
Device
AG48 MGTYTXP0_129
FMCP_HSPC_DP20_C2M_P
Z8
DP20_C2M_P
AG49 MGTYTXN0_129
FMCP_HSPC_DP20_C2M_N
Z9
DP20_C2M_N
AG53 MGTYRXP0_129
FMCP_HSPC_DP20_M2C_P
M14
DP20_M2C_P
AG54 MGTYRXN0_129
FMCP_HSPC_DP20_M2C_N
M15
DP20_M2C_N
AG44 MGTYTXP1_129
FMCP_HSPC_DP21_C2M_P
Y6
DP21_C2M_P
AG45 MGTYTXN1_129
FMCP_HSPC_DP21_C2M_N
Y7
DP21_C2M_N
AF51 MGTYRXP1_129
FMCP_HSPC_DP21_M2C_P
M10
DP21_M2C_P
AF52 MGTYRXN1_129
FMCP_HSPC_DP21_M2C_N
M11
DP21_M2C_N
AF46 MGTYTXP2_129
FMCP_HSPC_DP22_C2M_P
Z4
DP22_C2M_P
FMCP HSPC
GTY AF47 MGTYTXN2_129
FMCP_HSPC_DP22_C2M_N
Z5
DP22_C2M_N
J18
bank
129 AE53 MGTYRXP2_129
FMCP_HSPC_DP22_M2C_P
M6
DP22_M2C_P
AE54 MGTYRXN2_129
FMCP_HSPC_DP22_M2C_N
M7
DP22_M2C_N
AE44 MGTYTXP3_129
FMCP_HSPC_DP23_C2M_P
Y2
DP23_C2M_P
AE45 MGTYTXN3_129
FMCP_HSPC_DP23_C2M_N
Y3
DP23_C2M_N
AE49 MGTYRXP3_129
FMCP_HSPC_DP23_M2C_P
M2
DP23_M2C_P
AE50 MGTYRXN3_129
FMCP_HSPC_DP23_M2C_N
M3
DP23_M2C_N
AG40 MGTREFCLK0P_129 FMCP_HSPC_GBTCLK5_M2C_P1
Z20
GBTCLK5_M2C_P
AG41 MGTREFCLK0N_129 FMCP_HSPC_GBTCLK5_M2C_N1
Z21
GBTCLK5_M2C_N
AF42 MGTREFCLK1P_129 NC
AF43 MGTREFCLK1N_129
NC
NC
NC
Notes: 1. Series 0.01 µF capacitor coupled.
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Table 17: XCVU37P U1 GTY Transceiver Bank 128 Connections
MGT Bank
FPGA (U1) Pin
FPGA (U1) Pin Name
Schematic Net Name
Connected Connected Pin Connected
Pin
Name
Device
AK46 MGTYTXP0_128
FMCP_HSPC_DP16_C2M_P
M26
DP16_C2M_P
AK47 MGTYTXN0_128
FMCP_HSPC_DP16_C2M_N
M27
DP16_C2M_N
AL49 MGTYRXP0_128
FMCP_HSPC_DP16_M2C_P
Z32
DP16_M2C_P
AL50 MGTYRXN0_128
FMCP_HSPC_DP16_M2C_N
Z33
DP16_M2C_N
AJ48 MGTYTXP1_128
FMCP_HSPC_DP17_C2M_P
M30
DP17_C2M_P
AJ49 MGTYTXN1_128
FMCP_HSPC_DP17_C2M_N
M31
DP17_C2M_N
AK51 MGTYRXP1_128
FMCP_HSPC_DP17_M2C_P
Y34
DP17_M2C_P
AK52 MGTYRXN1_128
FMCP_HSPC_DP17_M2C_N
Y35
DP17_M2C_N
GTY bank 128
AJ44 AJ45 AJ53 AJ54
MGTYTXP2_128 MGTYTXN2_128 MGTYRXP2_128 MGTYRXN2_128
FMCP_HSPC_DP18_C2M_P FMCP_HSPC_DP18_C2M_N FMCP_HSPC_DP18_M2C_P FMCP_HSPC_DP18_M2C_N
M34 M35 Z36 Z37
DP18_C2M_P DP18_C2M_N DP18_M2C_P DP18_M2C_N
FMCP HSPC J18
AH46 MGTYTXP3_128
FMCP_HSPC_DP19_C2M_P
M38
DP19_C2M_P
AH47 MGTYTXN3_128
FMCP_HSPC_DP19_C2M_N
M39
DP19_C2M_N
AH51 MGTYRXP3_128
FMCP_HSPC_DP19_M2C_P
Y38
DP19_M2C_P
AH52 MGTYRXN3_128
FMCP_HSPC_DP19_M2C_N
Y39
AJ40 MGTREFCLK0P_128 FMCP_HSPC_GBTCLK4_M2C_P1
L4
AJ41 MGTREFCLK0N_128 FMCP_HSPC_GBTCLK4_M2C_N 1
L5
DP19_M2C_N GBTCLK4_M2C_P GBTCLK4_M2C_N
AH42 MGTREFCLK1P_128 NC
AH43 MGTREFCLK1N_128
NC
NC
NC
Notes: 1. Series 0.01 µF capacitor coupled.
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Chapter 3: Board Component Descriptions
Table 18: XCVU37P U1 GTY Transceiver Bank 127 Connections
MGT Bank
FPGA (U1) Pin
FPGA (U1) Pin Name
Schematic Net Name
Connected Connected Pin Connected
Pin
Name
Device
AP46 MGTYTXP0_127
FMCP_HSPC_DP12_C2M_P
Z28
DP12_C2M_P
AP47 MGTYTXN0_127
FMCP_HSPC_DP12_C2M_N
Z29
DP12_C2M_N
AN53 MGTYRXP0_127
FMCP_HSPC_DP12_M2C_P
Y14
DP12_M2C_P
AN54 MGTYRXN0_127
FMCP_HSPC_DP12_M2C_N
Y15
DP12_M2C_N
AN44 MGTYTXP1_127
FMCP_HSPC_DP13_C2M_P
Y30
DP13_C2M_P
AN45 MGTYTXN1_127
FMCP_HSPC_DP13_C2M_N
Y31
DP13_C2M_N
AN49 MGTYRXP1_127
FMCP_HSPC_DP13_M2C_P
Z16
DP13_M2C_P
AN50 MGTYRXN1_127
FMCP_HSPC_DP13_M2C_N
Z17
DP13_M2C_N
GTY bank 127
AM46 AM47 AM51 AM52
MGTYTXP2_127 MGTYTXN2_127 MGTYRXP2_127 MGTYRXN2_127
FMCP_HSPC_DP14_C2M_P FMCP_HSPC_DP14_C2M_N FMCP_HSPC_DP14_M2C_P FMCP_HSPC_DP14_M2C_N
M18 M19 Y18 Y19
DP14_C2M_P DP14_C2M_N DP14_M2C_P DP14_M2C_N
FMCP HSPC J18
AL44 MGTYTXP3_127
FMCP_HSPC_DP15_C2M_P
M22
DP15_C2M_P
AL45 MGTYTXN3_127
FMCP_HSPC_DP15_C2M_N
M23
DP15_C2M_N
AL53 MGTYRXP3_127
FMCP_HSPC_DP15_M2C_P
Y22
DP15_M2C_P
AL54 MGTYRXN3_127
FMCP_HSPC_DP15_M2C_N
Y23
DP15_M2C_N
AL40 MGTREFCLK0P_127 FMCP_HSPC_GBTCLK3_M2C_P1
L8
GBTCLK3_M2C_P
AL41 MGTREFCLK0N_127 FMCP_HSPC_GBTCLK3_M2C_N1
L9
GBTCLK3_M2C_N
AK42 MGTREFCLK1P_127 NC
AK43 MGTREFCLK1N_127
NC
NC
NC
Notes: 1. Series 0.01 µF capacitor coupled.
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Chapter 3: Board Component Descriptions
Table 19: XCVU37P U1 GTY Transceiver Bank 126 Connections
MGT Bank
FPGA (U1) Pin
FPGA (U1) Pin Name
Schematic Net Name
Connected Connected Pin Connected
Pin
Name
Device
AU48 MGTYTXP0_126
FMCP_HSPC_DP8_C2M_P
B28
DP8_C2M_P
AU49 MGTYTXN0_126
FMCP_HSPC_DP8_C2M_N
B29
DP8_C2M_N
AU53 MGTYRXP0_126
FMCP_HSPC_DP8_M2C_P
B8
DP8_M2C_P
AU54 MGTYRXN0_126
FMCP_HSPC_DP8_M2C_N
B9
DP8_M2C_N
AT46 MGTYTXP1_126
FMCP_HSPC_DP9_C2M_P
B24
DP9_C2M_P
AT47 MGTYTXN1_126
FMCP_HSPC_DP9_C2M_N
B25
DP9_C2M_N
AT51 MGTYRXP1_126
FMCP_HSPC_DP9_M2C_P
B4
DP9_M2C_P
AT52 MGTYRXN1_126
FMCP_HSPC_DP9_M2C_N
B5
DP9_M2C_N
AR48 MGTYTXP2_126
FMCP_HSPC_DP10_C2M_P
Z24
DP10_C2M_P
FMCP HSPC
GTY AR49 MGTYTXN2_126
FMCP_HSPC_DP10_C2M_N
Z25
DP10_C2M_N
J18
bank
126 AR53 MGTYRXP2_126
FMCP_HSPC_DP10_M2C_P
Y10
DP10_M2C_P
AR54 MGTYRXN2_126
FMCP_HSPC_DP10_M2C_N
Y11
DP10_M2C_N
AR44 MGTYTXP3_126
FMCP_HSPC_DP11_C2M_P
Y26
DP11_C2M_P
AR45 MGTYTXN3_126
FMCP_HSPC_DP11_C2M_N
Y27
DP11_C2M_N
AP51 MGTYRXP3_126
FMCP_HSPC_DP11_M2C_P
Z12
DP11_M2C_P
AP52 MGTYRXN3_126
FMCP_HSPC_DP11_M2C_N
Z13
DP11_M2C_N
AN40 MGTREFCLK0P_126 FMCP_HSPC_GBTCLK2_M2C_P1
L12
GBTCLK2_M2C_P
AN41 MGTREFCLK0N_126 FMCP_HSPC_GBTCLK2_M2C_N1
L13
GBTCLK2_M2C_N
AM42 MGTREFCLK1P_126 NC
AM43 MGTREFCLK1N_126
NC
NC
NC
Notes: 1. Series 0.01 µF capacitor coupled.
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Table 20: XCVU37P U1 GTY Transceiver Bank 125 Connections
MGT Bank
FPGA (U1) Pin
FPGA (U1) Pin Name
Schematic Net Name
Connected Connected Pin Connected
Pin
Name
Device
AY46 MGTYTXP0_125
FMCP_HSPC_DP4_C2M_P
A34
DP4_C2M_P
AY47 MGTYTXN0_125
FMCP_HSPC_DP4_C2M_N
A35
DP4_C2M_N
AY51 MGTYRXP0_125
FMCP_HSPC_DP4_M2C_P
A14
DP4_M2C_P
AY52 MGTYRXN0_125
FMCP_HSPC_DP4_M2C_N
A15
DP4_M2C_N
AW44 MGTYTXP1_125
FMCP_HSPC_DP5_C2M_P
A38
DP5_C2M_P
AW45 MGTYTXN1_125
FMCP_HSPC_DP5_C2M_N
A39
DP5_C2M_N
AW53 MGTYRXP1_125
FMCP_HSPC_DP5_M2C_P
A18
DP5_M2C_P
AW54 MGTYRXN1_125
FMCP_HSPC_DP5_M2C_N
A19
DP5_M2C_N
AV46 MGTYTXP2_125
FMCP_HSPC_DP6_C2M_P
B36
DP6_C2M_P
FMCP HSPC
GTY AV47 MGTYTXN2_125
FMCP_HSPC_DP6_C2M_N
B37
DP6_C2M_N
J18
bank
125 AW49 MGTYRXP2_125
FMCP_HSPC_DP6_M2C_P
B16
DP6_M2C_P
AW50 MGTYRXN2_125
FMCP_HSPC_DP6_M2C_N
B17
DP6_M2C_N
AU44 MGTYTXP3_125
FMCP_HSPC_DP7_C2M_P
B32
DP7_C2M_P
AU45 MGTYTXN3_125
FMCP_HSPC_DP7_C2M_N
B33
DP7_C2M_N
AV51 MGTYRXP3_125
FMCP_HSPC_DP7_M2C_P
B12
DP7_M2C_P
AV52 MGTYRXN3_125
FMCP_HSPC_DP7_M2C_N
B13
DP7_M2C_N
AR40 MGTREFCLK0P_125 FMCP_HSPC_GBTCLK1_M2C_P1
B20
GBTCLK1_M2C_P
AR41 MGTREFCLK0N_125 FMCP_HSPC_GBTCLK1_M2C_N1
B21
GBTCLK1_M2C_N
AP42 MGTREFCLK1P_125 NC
AP43 MGTREFCLK1N_125
NC
NC
NC
Notes: 1. Series 0.01 µF capacitor coupled.
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Table 21: XCVU37P U1 GTY Transceiver Bank 124 Connections
MGT Bank
FPGA (U1) Pin
FPGA (U1) Pin Name
Schematic Net Name
Connected Connected Pin Connected
Pin
Name
Device
BC48 MGTYTXP0_124
FMCP_HSPC_DP0_C2M_P
C2
DP0_C2M_P
BC49 MGTYTXN0_124
FMCP_HSPC_DP0_C2M_N
C3
DP0_C2M_N
BC53 MGTYRXP0_124
FMCP_HSPC_DP0_M2C_P
C6
DP0_M2C_P
BC54 MGTYRXN0_124
FMCP_HSPC_DP0_M2C_N
C7
DP0_M2C_N
BC44 MGTYTXP1_124
FMCP_HSPC_DP1_C2M_P
A22
DP1_C2M_P
BC45 MGTYTXN1_124
FMCP_HSPC_DP1_C2M_N
A23
DP1_C2M_N
BB51 MGTYRXP1_124
FMCP_HSPC_DP1_M2C_P
A2
DP1_M2C_P
BB52 MGTYRXN1_124
FMCP_HSPC_DP1_M2C_N
A3
DP1_M2C_N
BB46 MGTYTXP2_124
FMCP_HSPC_DP2_C2M_P
A26
DP2_C2M_P
FMCP HSPC
GTY BB47 MGTYTXN2_124
FMCP_HSPC_DP2_C2M_N
A27
DP2_C2M_N
J18
Bank
124 BA53 MGTYRXP2_124
FMCP_HSPC_DP2_M2C_P
A6
DP2_M2C_P
BA54 MGTYRXN2_124
FMCP_HSPC_DP2_M2C_N
A7
DP2_M2C_N
BA44 MGTYTXP3_124
FMCP_HSPC_DP3_C2M_P
A30
DP3_C2M_P
BA45 MGTYTXN3_124
FMCP_HSPC_DP3_C2M_N
A31
DP3_C2M_N
BA49 MGTYRXP3_124
FMCP_HSPC_DP3_M2C_P
A10
DP3_M2C_P
BA50 MGTYRXN3_124
FMCP_HSPC_DP3_M2C_N
A11
DP3_M2C_N
AV42 MGTREFCLK0P_124 FMCP_HSPC_GBTCLK0_M2C_P1
D4
GBTCLK0_M2C_P
AV43 MGTREFCLK0N_124 FMCP_HSPC_GBTCLK0_M2C_N1
D5
GBTCLK0_M2C_N
AT42 MGTREFCLK1P_124 NC
AT43 MGTREFCLK1N_124
NC
NC
NC
Notes: 1. Series 0.01 µF capacitor coupled.
Left-side Quads
The four connected GTY Quads on the left side of the XCVU37P FPGA are described in this section (MGTY235- MGTY228 are not used).
· Quad 227 MGTREFCLK0 - PCIE_CLK2_P/N (U94) MGTREFCLK1 - not connected Four GTY transceivers allocated to PCIe lanes 3:0 PCIE_EP_TX/RX[3:0]
· Quad 226 MGTREFCLK0 - not connected MGTREFCLK1 - not connected
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Four GTY transceivers allocated to PCIe lanes 7:4 PCIE_EP_TX/RX[7:4] · Quad 225
MGTREFCLK0 - PCIE_CLK1_P/N (U94) MGTREFCLK1 - not connected Four GTY transceivers allocated to PCIe lanes 11:8 PCIE_EP_TX/RX[11:8] · Quad 224 MGTREFCLK0 - not connected MGTREFCLK1 - not connected Four GTY transceivers allocated to PCIe lanes 15:12 PCIE_EP_TX/RX[15:12]
The XCVU37P left-side GTY transceiver interface assignments are shown in the following figure.
Figure 21: XCVU37P Left-side GTY Transceiver Assignments
BANK 227 MGTY_227_0 PCIE_EP_TX/RX_3 MGTY_227_1 PCIE_EP_TX/RX_2 MGTY_227_2 PCIE_EP_TX/RX_1 MGTY_227_3 PCIE_EP_TX/RX_0
MGTY_227_REFCLK0 PCIE_CLK2 MGTY_227_REFCLK1 NC
BANK 225 MGTY_225_0 PCIE_EP_TX/RX_11 MGTY_225_1 PCIE_EP_TX/RX_10 MGTY_225_2 PCIE_EP_TX/RX_9 MGTY_225_3 PCIE_EP_TX/RX_8
MGTY_225_REFCLK0 PCIE_CLK1 MGTY_225_REFCLK1 NC
BANK 226 MGTY_226_0 PCIE_EP_TX/RX_7 MGTY_226_1 PCIE_EP_TX/RX_6 MGTY_226_2 PCIE_EP_TX/RX_5 MGTY_226_3 PCIE_EP_TX/RX_4
MGTY_226_REFCLK0 NC MGTY_226_REFCLK1 NC
BANK 224 MGTY_224_0 PCIE_EP_TX/RX_15 MGTY_224_1 PCIE_EP_TX/RX_14 MGTY_224_2 PCIE_EP_TX/RX_13 MGTY_224_3 PCIE_EP_TX/RX_12
MGTY_224_REFCLK0 NC MGTY_224_REFCLK1 NC
X21651-092618
Left-side GTY Transceiver Connectivity
The following tables list the XCVU37P FPGA U1 GTY transceiver banks 227, 226, 225, and 224 connections, respectively.
For additional information on GTY transceivers, see the UltraScale Architecture GTY Transceivers User Guide (UG578). Also see the UltraScale FPGAs Transceivers Wizard LogiCORE IP Product Guide (PG182). For additional information about the quad small form factor pluggable (28 Gb/s QSFP28) module, see the SFF-8663 and SFF-8679 specifications for the 28 Gb/s QSFP+ at the SNIA Technology Affiliates website.
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Table 22: XCVU37P U1 GTY Transceiver Bank 227 Connections
MGT FPGA Bank (U1) Pin
FPGA (U1) Pin Name
GTY bank 227
AP9 AP8 AN2 AN1 AN11 AN10 AN6 AN5 AM9 AM8 AM4 AM3 AL11 AL10 AL2 AL1 AL15 AL14
MGTYTXP0_227 MGTYTXN0_227 MGTYRXP0_227 MGTYRXN0_227 MGTYTXP1_227 MGTYTXN1_227 MGTYRXP1_227 MGTYRXN1_227 MGTYTXP2_227 MGTYTXN2_227 MGTYRXP2_227 MGTYRXN2_227 MGTYTXP3_227 MGTYTXN3_227 MGTYRXP3_227 MGTYRXN3_227 MGTREFCLK0P_227 MGTREFCLK0N_227
AK13
MGTREFCLK1P_227
AK12
MGTREFCLK1N_227
Notes: 1. Series 0.01 µF capacitor coupled.
Schematic Net Name TX1
PCIE_EP_TX3_P PCIE_EP_TX3_N PCIE_EP_RX3_P PCIE_EP_RX3_N PCIE_EP_TX2_P PCIE_EP_TX2_N PCIE_EP_RX2_P PCIE_EP_RX2_N PCIE_EP_TX1_P PCIE_EP_TX1_N PCIE_EP_RX1_P PCIE_EP_RX1_N PCIE_EP_TX0_P PCIE_EP_TX0_N PCIE_EP_RX0_P PCIE_EP_RX0_N PCIE_CLK2_P1 PCIE_CLK2_N1
NC
Connected Connected Connected
Pin
Pin Name Device
A29
PERP3
A30
PERN3
B27
PETP3
B28
PETN3
A25
PERP2
A26
PERN2
B23
PETP2
B24
PETN2
PCIE 16-lane
A21
PERP1
edge conn. P1
A22
PERN1
B19
PETP1
B20
PETN1
A16
PERP0
A17
PERN0
B14
PETP0
B15
PETN0
3
Q1
ICS85411A
4
NQ1
U94 clock buffer
NC
NC
NC
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Chapter 3: Board Component Descriptions
Table 23: XCVU37P U1 GTY Transceiver Bank 226 Connections
MGT FPGA Bank (U1) Pin
FPGA (U1) Pin Name
AU11
MGTYTXP0_226
AU10
MGTYTXN0_226
AU2
MGTYRXP0_226
AU1
MGTYRXN0_226
AT9
MGTYTXP1_226
AT8
MGTYTXN1_226
AT4
MGTYRXP1_226
AT3
MGTYRXN1_226
AR7
MGTYTXP2_226
GTY bank
AR6
226
AR2
MGTYTXN2_226 MGTYRXP2_226
AR1
MGTYRXN2_226
AR11
MGTYTXP3_226
AR10
MGTYTXN3_226
AP4
MGTYRXP3_226
AP3
MGTYRXN3_226
AN15
MGTREFCLK0P_226
AN14
MGTREFCLK0N_226
AM13
MGTREFCLK1P_226
AM12
MGTREFCLK1N_226
Notes: 1. Series 0.01 µF capacitor coupled.
Schematic Net Name TX1
PCIE_EP_TX7_P PCIE_EP_TX7_N PCIE_EP_RX7_P PCIE_EP_RX7_N PCIE_EP_TX6_P PCIE_EP_TX6_N PCIE_EP_RX6_P PCIE_EP_RX6_N PCIE_EP_TX5_P PCIE_EP_TX5_N PCIE_EP_RX5_P PCIE_EP_RX5_N PCIE_EP_TX4_P PCIE_EP_TX4_N PCIE_EP_RX4_P PCIE_EP_RX4_N
NC
Connected Connected Connected
Pin
Pin Name Device
A47
PERP7
A48
PERN7
B45
PETP7
B46
PETN7
A43
PERP6
A44
PERN6
B41
PETP6
B42
PETN6
PCIE 16-lane
A39
PERP5
edge conn. P1
A40
PERN5
B37
PETP5
B38
PETN5
A35
PERP4
A36
PERN4
B33
PETP4
B34
PETN4
NC
NC
NC
NC
NC
NC
NC
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Chapter 3: Board Component Descriptions
Table 24: XCVU37P U1 GTY Transceiver Bank 225 Connections
MGT FPGA Bank (U1) Pin
FPGA (U1) Pin Name
GTY bank 225
AY9 AY8 AY4 AY3 AW11 AW10 AW2 AW1 AV9 AV8 AW6 AW5 AU7 AU6 AV4 AV3 AR15 AR14
MGTYTXP0_225 MGTYTXN0_225 MGTYRXP0_225 MGTYRXN0_225 MGTYTXP1_225 MGTYTXN1_225 MGTYRXP1_225 MGTYRXN1_225 MGTYTXP2_225 MGTYTXN2_225 MGTYRXP2_225 MGTYRXN2_225 MGTYTXP3_225 MGTYTXN3_225 MGTYRXP3_225 MGTYRXN3_225 MGTREFCLK0P_225 MGTREFCLK0N_225
AP13
MGTREFCLK1P_225
AP12
MGTREFCLK1N_225
Notes: 1. Series 0.01 µF capacitor coupled.
Schematic Net Name TX
PCIE_EP_TX11_P PCIE_EP_TX11_N PCIE_EP_RX11_P PCIE_EP_RX11_N PCIE_EP_TX10_P PCIE_EP_TX10_N PCIE_EP_RX10_P PCIE_EP_RX10_N PCIE_EP_TX9_P PCIE_EP_TX9_N PCIE_EP_RX9_P PCIE_EP_RX9_N PCIE_EP_TX8_P PCIE_EP_TX8_N PCIE_EP_RX8_P PCIE_EP_RX8_N
PCIE_CLK1_P1 PCIE_CLK1_N1
NC
Connected Connected Connected
Pin
Pin Name Device
A64
PERP11
A65
PERN11
B62
PETP11
B63
PETN11
A60
PERP10
A61
PERN10
B58
PETP10
B59
PETN10
PCIE 16-lane
A56
PERP9
edge conn. P1
A57
PERN9
B54
PETP9
B55
PETN9
A52
PERP8
A53
PERN8
B50
PETP8
B51
PETN8
1
Q0
ICS85411A
2
NQ0
U94 clock buffer
NC
NC
NC
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Table 25: XCVU37P U1 GTY Transceiver Bank 224 Connections
MGT FPGA bank (U1) Pin
FPGA (U1) Pin Name
BC7
MGTYTXP0_224
BC6
MGTYTXN0_224
BC2
MGTYRXP0_224
BC1
MGTYRXN0_224
BC11
MGTYTXP1_224
BC10
MGTYTXN1_224
BB4
MGTYRXP1_224
BB3
MGTYRXN1_224
BB9
MGTYTXP2_224
GTY bank
BB8
224
BA2
MGTYTXN2_224 MGTYRXP2_224
BA1
MGTYRXN2_224
BA11
MGTYTXP3_224
BA10
MGTYTXN3_224
BA6
MGTYRXP3_224
BA5
MGTYRXN3_224
AV13
MGTREFCLK0P_224
AV12
MGTREFCLK0N_224
AT13
MGTREFCLK1P_224
AT12
MGTREFCLK1N_224
Notes: 1. Series 0.01 µF capacitor coupled.
Schematic Net Name TX
PCIE_TX15_P PCIE_TX15_N PCIE_RX15_P PCIE_RX15_N PCIE_TX14_P PCIE_TX14_N PCIE_RX14_P PCIE_RX14_N PCIE_TX13_P PCIE_TX13_N PCIE_RX13_P PCIE_RX13_N PCIE_TX12_P PCIE_TX12_N PCIE_RX12_P PCIE_RX12_N
NC
Connected Connected Connected
Pin
Pin Name device
A80
PERP15
A81
PERN15
B78
PETP15
B79
PETN15
A76
PERP14
A77
PERN14
B74
PETP14
B75
PETN14
PCIE 16-lane
A72
PERP13
edge conn. P1
A73
PERN13
B70
PETP13
B71
PETN13
A68
PERP12
A69
PERN12
B66
PETP12
B67
PETN12
NC
NC
NC
NC
NC
NC
NC
PCI Express Endpoint Connectivity
[Figure 2, callout 20]
The 16-lane PCI Express® edge connector P1 performs data transfers at the rate of 2.5 GT/s for Gen1 applications, 5.0 GT/s for Gen2 applications, 8.0 GT/s for Gen3 applications and 16.0 GT/s for Gen4 applications. The PCIe® transmit and receive signal data paths have a characteristic impedance of 85 ±10%. The PCIe clock is routed as a 100 differential pair.
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The XCVU37P-2FSVH2892E (-2 speed grade) is deployed on the VCU128 to support up to Gen4 x8. User selectable as PCIe Gen3 x16 or dual Gen4 x8. The PCIe reference clock is input from the P1 edge connector. The PCIe clock is routed from P1 pin A16 (P) and pin A17 (N) to a 1-to-2 ICS85411A clock buffer U94. The Q0 output of U94 is wired to the GTY225 MGTHREFCLK0 input (see Table 24). The Q1 output of U94 is wired to the GTY227 MGTHREFCLK0 input (see Table 22). PCIe lane width/size is selected by jumper J46. The default lane size selection is 16lane (J46 pins 7 and 8 jumpered). The 1-to-2 U94 PCIe clock buffer circuit and J46 lane size jumper are shown in the following figure.
Figure 22: PCI Express Lane Clock Circuit and Size Select Jumper J46
X21969-112818
The tables in Left-side GTY Transceiver Connectivity list the PCIe P1 edge connector wiring to the XCVU37P FPGA U1 MGTY transceiver banks 227-224. The two PCIe P1 edge connector control signals PCIE_EP_WAKE (P1 pin B11) and PCIE_EP_PERST (P1 pin A11) are level-shifted by SN74AVC2T245 U70 and connected to the XCVU39P U1 bank 65 pin BJ42 and pin BF41, respectively. For additional information about UltraScaleTM PCIe functionality, see the UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156). Additional information about the PCI Express standard is available on the PCI Express standard website.
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28 Gb/s zQSFP+ Module Connectors
[Figure 2, callout 19] The VCU128 board hosts four QSFP28 small form-factor pluggable (28 Gb/s QSFP+) connectors: QSFP1 J42, QSFP2 J39, QSFP3 J35, and QSFP4 J32, which accept 28 Gb/s QSFP+ optical modules. The four connectors are housed within a single 1x4 ganged 28 Gb/s QSFP+ cage assembly J37. The following figure shows a typical implementation of the 28 Gb/s QSFP28 module connector circuitry. Table 12 through Table 15 in Right-side GTY Transceiver Connectivity list the QSFP28 connections to the XCVU37P FPGA U1 MGTY transceiver banks 135 (QSFP1), 134 (QSFP2), 132 (QSFP3), and 131 (QSFP4).
Figure 23: 28 Gb/s QSFP28 Module Connector
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QSFP28 Connections to Transceiver Banks 67 and 69
The following table lists the QSFP28 module level-shifted control signal connections to XCVU37P FPGA U1 bank 67 (QSFP1, QSFP4) and bank 69 (QSFP2, QSFP3).
Table 26: XCVU37P U1 to QSFP28 Module Control and I2C Connections
FPGA (U1) Pin
BM24 BN25 BM25 BP24 BN24 U54.13 U54.14
BN5 BN6 BN7 BP6 BP7 U54.15 U54.16
BM5 BL6 BM7 BL7 BN4 U54.17 U54.18
BK23 BK24 BL22 BH21 BH21 U54.19
Schematic Net Name1,2
QSFP1_MODSKLL_LS QSFP1_RESETL_LS
QSFP1_MODPRSL_LS QSFP1_INTL_LS
QSFP1_LPMODE_LS QSFP1_I2C_SDA QSFP1_I2C_SCL
QSFP2_MODSKLL_LS QSFP2_RESETL_LS
QSFP2_MODPRSL_LS QSFP2_INTL_LS
QSFP2_LPMODE_LS QSFP2_I2C_SDA QSFP2_I2C_SCL
QSFP3_MODSKLL_LS QSFP3_RESETL_LS
QSFP3_MODPRSL_LS QSFP3_INTL_LS
QSFP3_LPMODE_LS QSFP3_I2C_SDA QSFP3_I2C_SCL
QSFP4_MODSKLL_LS QSFP4_RESETL_LS
QSFP4_MODPRSL_LS QSFP4_INTL_LS
QSFP4_LPMODE_LS QSFP4_I2C_SDA
FPGA (U1) Direction
QSFP1 J42 (U1 bank 67) Output Output Output Input Output BiDir Output
QSFP2 J39 (U1 bank 69) Output Output Output Input Output BiDir Output
QSFP3 J35 (U1 bank 69) Output Output Output Input Output BiDir Output
QSFP4 J32 (U1 bank 67) Output Output Output Input Output BiDir
Module Pin Num
8 9 27 28 31 12 11
8 9 27 28 31 12 11
8 9 27 28 31 12 11
8 9 27 28 31 12
Module Pin Name
MODSELL RESETL
MODPRSL INTL
LPMODE SDA SCL
MODSELL RESETL
MODPRSL INTL
LPMODE SDA SCL
MODSELL RESETL
MODPRSL INTL
LPMODE SDA SCL
MODSELL RESETL
MODPRSL INTL
LPMODE SDA
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Table 26: XCVU37P U1 to QSFP28 Module Control and I2C Connections (cont'd)
FPGA (U1) Pin
Schematic Net Name1,2
FPGA (U1) Direction
Module Pin Num Module Pin Name
U54.20
QSFP4_I2C_SCL
Output
11
SCL
Notes:
1. The QSFP28 connector control signals are level-shifted.
2. The four QSFP28 connector I2C SCL/SDA signals are connected via I2C switch U54 to the I2C1_SCL/SDA bus. See I2C Bus, Topology, and Switches section.
For additional information about the quad small form factor pluggable (28 Gb/s QSFP28) module, see the SFF-8663 and SFF-8679 specifications for the 28 Gb/s QSFP+ on the SNIA Technology Affiliates website.
10/100/1000 Mb/s Tri-speed Ethernet PHY
[Figure 2, callout 22]
The VCU128 evaluation board uses the TI PHY device DP83867ISRGZ (U62) for Ethernet communications at 10 Mb/s, 100 Mb/s, or 1000 Mb/s. The board supports SGMII mode only. The PHY connection to a user-provided Ethernet cable is through RJ-45 connector P2, a Wurth 7499111221A with built-in magnetics and status LEDs. On power-up, or on reset, the PHY is configured to operate in SGMII mode with PHY address[4:0] = 00011. The following table lists the FPGA U1 to U62 DP83867ISRGZ Ethernet PHY connections. This table also shows the net names for the connections from the FPGA to the Ethernet PHY. ENET_SGMII_IN correlates with the SGMII_TX ports in the FPGA design, and ENET_SGMII_OUT correlates with the SGMII_RX ports.
Table 27: XCVC37P U1 to Ethernet PHY U62 Connections
FPGA (U1) Pin
BG23 BN27 BF22 BH22 BG22 BJ21 BH21 BK22 BK23 U65.10 BP27 BJ23
Net Name
ENET_MDIO ENET_MDC ENET_PDWN_B_I_INT_B_O ENET_SGMII_IN_N ENET_SGMII_IN_P ENET_SGMII_OUT_N ENET_SGMII_OUT_P ENET_SGMII_CLK_N ENET_SGMII_CLK_P GEM3_ENET_RESET_B ENET_COL_GPIO ENET_CLKOUT
I/O Standard
LVCMOS18 LVCMOS18 LVCMOS18 LVCMOS18 LVCMOS18 LVCMOS18 LVCMOS18 LVCMOS18 LVCMOS18
NA LVCMOS18 LVCMOS18
DP83867ISRGZ U62
Pin
Name
17
MDIO
16
MDC
44
INT_PWDN
28
TX_D1_SGMII_SIP
27
TX_D0_SGMII_SIN
36
RX_D3_SGMII_SON
35
RX_D2_SGMII_SOP
34
RX_D1_SGMII_CON
33
RX_D0_SGMII_COP
43
RESET_B
39
GPIO_2
18
CLK_OUT
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Ethernet PHY Status LEDs
[Figure 2, callout 23] Two Ethernet PHY status LEDs are integrated into the metal frame of the P2 RJ-45 connector, installed on the top edge and towards the back of the VCU128 board. The two PHY status LEDs are visible within the frame of the RJ45 Ethernet jack as shown in the following figure. As viewed from the front opening, the left green LED is the link activity indicator and the right green LED is the 1000BASE-T link mode indicator.
Figure 24: Ethernet PHY Status LEDs
X21971-112818
A separate discrete LED on top of the board (DS19, near item 38 in Figure 2) indicates link established. Details about the tri-mode Ethernet MAC core are provided in the Tri-Mode Ethernet MAC LogiCORE IP Product Guide (PG051). The TI DP83867ISRGZ data sheet is on the TI website.
I2C Bus, Topology, and Switches
[Figure 2, callout 25, 26]
The VCU128 evaluation board I2C bus implementation consists of I2C bus I2C0. The FPGA U1 HP bank 67 (VCCO VCC1V8) and system controller U42 bank 501 are wired to I2C0 via levelshifters. I2C bus I2C0 is routed to a 1-to-4 channel TI PCA9544A bus switch U55 (address 0x75) and a dual 8-bit port TI TCA6416A IO expander U65 (address 0x20). I2C bus I2C0 is also routed to a pair of 1-to-8 channel TI TCA9548A bus switches U53 (address 0x74) and U54 (address 0x76). The bus switches can operate at speeds up to 400 kHz. The VCU128 evaluation board I2C0 I2C bus topology is shown in the following figures.
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IMPORTANT! The TCA9548 U53 and U54 RESET_B pin 3 control signal IIC_MUX_RESET_B is connected to the I2C0 bus TCA6416A U65 port expander (Addr 0x20) port P05 pin 9. The IIC_MUX_RESET_B signal must be driven hi-Z or High to enable I2C bus transactions with the target devices connected to U53 and U54.
U1 XCVU37P BANK 65 BE41/BP42
BANK 67 BL28/BM27
Figure 25: I2C0 Bus Topology
U49 L/S SYSMON_SDA/SCL
U60 L/S
I2C0_SDA/SCL
U65
TCA64 16A
MAX6643-OT_B
P00 MAX6643_FANFAIL_B
P01 VCCINT_VCCBRAM_HOT_N
SDA/
P02 PMIC_INTR
P03 SI5328_INT_ALM
P04 P05
ICC_MUX_RESET-B
P06 GEM3_EXP_RESET_B
P07 MAX6643_FULL_SPEED
SCL
FMC_HSPC_PRSNT_M2C_B
P10 P16 P17
MAIN_PMBUS_ALERT_B INA226_PMBUS_ALERT
0X20
U53
TCA9548A
SDA/ SCL
0X74
IIC-EEPROM-SDA/SCL
SD0/SC0 SI5328_SDA/SCL
SD1/SC1 SD2/SC2
NOT CONNECTED QSFP1_SI570_SDA/SCL
SD3/SC3 QSFP2_SI570_SDA/SCL
SD4/SC4 SD5/SC5
QSFP3_SI570_SDA/SCL
SD6/SC6 QSFP4_SI570_SDA/SCL
SD7/SC7
NOT CONNECTED
U42
XC7Z010 BANK 501
U58
D11/A15
L/S
U55
PCA9544A
INA226_PMBUS_ALERT
INT0_B INA226_PMBUS_SDA/SCL
SDA/
SD0/SC0 NC
SCL
INT1_B NC
SD1/SC1 INT2_B
SD2/SC2 INT3_B
MAIN_PMBUS_ALERT_B
MAIN_PMBUS_SDA/SCL NC
SYSMON_SDA/SCL
0X75
SD3/SC3
U54
TCA9548A
SDA/ SCL
0X76
SD0/SC0 SD1/SC1 SD2/SC2
FMCP_HSPC_IIC_SDA/SCL NOT CONNECTED
SYSMON_SDA/SCL
SD3/SC3 SD4/SC4 SD5/SC5 SD6/SC6
NOT CONNECTED QSFP1_I2C_SDA/SCL
QSFP2_I2C_SDA/SCL QSFP3_I2C_SDA/SCL QSFP4_I2C_SDA/SCL
SD7/SC7
X21652-112918
I2C Bus Addresses
User applications that communicate with any of the I2C bus I2C0 downstream devices must first set up a path to the desired target device through the appropriate bus switch: I2C0 U55 PCA9544A, address 0x75 (0b111101); U53 TCA9548A, address 0x74 (0b1110100), or U54 TCA9548A, address 0x76 (0b111110), respectively. The following table lists the address for each bus.
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Table 28: I2C Bus Addresses
I2C Devices
PCA9544A 4-channel bus switch PMBus INA226 power monitor1
Not used PMBus regulators1
I2C Switch Position
I2C Address
Binary Format
Hex Format
I2C0 Bus
N/A
0b1110101
0
0x75
0x40-0x42 0x46-0x48 0x4C-0x4D
1
N/A
N/A
2
0x60-0x65
0x68-0x6B
FPGA SYSMON
TCA9548 8-channel bus switch I2C EEPROM SI5328 clock Not used QSFP1 Si570 clock QSFP2 Si570 clock QSFP3 Si570 clock QSFP4 Si570 clock Not used
TCA9548 8-channel bus switch FMCP HSPC (FMC Plus) Not used FPGA SYSMON Not used QSFP1 module QSFP2 module QSFP3 module QSFP4 module Notes: 1. See Onboard Power System Devices.
3
0b0110010
I2C0 Bus
N/A
0b1110100
0
0b1010100
1
0b1101000
2
N/A
3
0b1011101
4
0b1011101
5
0b1011101
6
0b1011101
7
N/A
I2C0 Bus
N/A
0b1110101
0
0bXXXXXXX
1
N/A
2
0b0110010
3
N/A
4
0b1010000
5
0b1010000
6
0b1010000
7
0b1010000
0x32
0x74 0x54 0x68 N/A 0x5D 0x5D 0x5D 0x5D N/A
0x76 0x## N/A 0x32 N/A 0x50 0x50 0x50 0x50
Device
U55 PCA9544A INA226
U14,U16,U20,U21, U79,U84,U85,U86
N/A Various Intersil
regulators U3,U12,U15,U22,U24,U2 5,U29,U31,U36,U44,U67,
U68 U1 BANK 65
U53 TCA9548A U48 M24C08 U87 SI5328B
N/A U95 SI570 U90 SI570 U82 SI570 U80 SI570
N/A
U54 TCA9548A J18 FMCP HSPC
N/A U1 BANK 65
N/A J42 28 Gb/s QSFP+ J39 28 Gb/s QSFP+ J35 28 Gb/s QSFP+ J32 28 Gb/s QSFP+
Information about the PCA9544A, TCA9548, and TCA6416A is available on the TI Semiconductor website.
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Status and User LEDs
[Figure 2, callout 24] The following table defines VCU128 board status and user LEDs.
Table 29: Board Status and User LEDs
Reference Designator
Description (Green unless otherwise noted)
DS1 DS2 DS3 DS4 DS5 DS6 DS7 DS8 DS9 DS10 DS11 DS12 DS13 DS14 DS15 DS16 DS17 DS18 DS19 DS20 EPHY P2 RT EPHY P2 LFT
Combined power good (red/green) GPIO_LED_1 GPIO_LED_0 GPIO_LED_2 GPIO_LED_5 GPIO_LED_4 GPIO_LED_5 GPIO_LED_6 GPIO_LED_7 FPGA INIT (red/green) VCCINT 0.85V Mode VCCINT 0.72V Mode FPGA done VADJ_PG SYSTEM CTLR INIT (red/green) SYSTEM CTLR error (red) SYSTEM CTLR status SYSTEM CTLR done ENET PHY link 12V On ENET LINK1000 ENET link activity
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User GPIO
[Figure 2, callout 27, 28, 29] The VCU128 board provides the following user and general purpose I/O capabilities. · Eight user LEDs (callout 28)
GPIO_LED[7-0]: DS9, DS8, DS7, DS6, DS5, DS4, DS3, DS2 · CPU_RESET/GPIO pushbutton switch (callout 29)
CPU_RESET: SW4 The following figure shows the GPIO circuits.
Figure 26: User GPIO
GPIO Connections to FPGA U1
The following table lists the GPIO connections to FPGA U1.
X21972-112918
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Table 30: GPIO Connections to FPGA U1
FPGA (U1) Pin
Schematic Net Name
FPGA (U1) Direction
I/O Standard
BANK 67 BANK 67 BANK 67 BANK 67 BANK 67 BANK 67 BANK 67 BANK 67
BANK 64
BANK 67 BANK 67
GPIO LEDs (Active-High) GPIO_LED signals are wired to LED driver U56
BH24
GPIO_LED_0
Output
LVCMOS18
BG24
GPIO_LED_1
Output
LVCMOS18
BG25
GPIO_LED_2
Output
LVCMOS18
BF25
GPIO_LED_3
Output
LVCMOS18
BF26
GPIO_LED_4
Output
LVCMOS18
BF27
GPIO_LED_5
Output
LVCMOS18
BG27
GPIO_LED_6
Output
LVCMOS18
BG28
GPIO_LED_7
Output
LVCMOS18
CPU reset pushbutton (active-high)
BM29
CPU_RESET
Input
LVCMOS12
GPIO SMA pair (applied voltage should not exceed 1.8V)
BH27
SMA_CLK_OUTPUT_P
I/O
LVCMOS18
BJ27
SMA_CLK_OUTPUT_N
I/O
LVCMOS18
Device
DS2 DS3 DS4 DS5 DS6 DS7 DS8 DS9
SW4.3
J12.1 J13.1
Switches
[Figure 2, callouts 30, 33]
The VCU118 evaluation board includes a power on/off slide switch and a configuration pushbutton switch.
· FPGA Program_B SW4, active-Low (callout 30) · Power on/off slide switch SW5 (callout 33)
Power On/Off Slide Switch SW5
[Figure 2, callout 33]
The VCU118 board power switch is SW5. Sliding the switch actuator from the off to the on position applies 12VDC power from the 6-pin mini-fit power input connector J16, normally used in bench-top applications with the provided power adapter. The green LED DS20 illuminates when the VCU128 board power switch is on. See Board Power System for details on the onboard power system. The following figure shows the power connector J16, power switch SW5, and indicator LED DS20.
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Chapter 3: Board Component Descriptions Figure 27: Power On/Off Switch SW5
X21973-112818
When the VCU128 board is used inside a computer chassis (i.e., plugged in to a PCIe® slot), power is normally provided from the PC ATX supply 2x4 PCIe power connector. See Installing the Board in a PC Chassis.
Program_B Pushbutton Switch
[Figure 2, callout 30]
Switch SW2 grounds the XCVU37P FPGA U1 PROGRAM_B pin when pressed. This action clears the FPGA configuration. The FPGA_PROG_B signal is connected to XCVU37P FPGA U1 pin BB15. See the UltraScale Architecture Configuration User Guide (UG570) for further configuration details. The following figure shows SW2.
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Chapter 3: Board Component Descriptions Figure 28: Program_B Pushbutton Switch SW2
X21974-112918
FPGA Mezzanine Card Interface
[Figure 2, callout 31]
The VCU128 evaluation board supports the VITA 57.4 FPGA mezzanine card plus (FMC+ or FMCP) specification by providing a subset implementation of the high pin count connector at J18 (HSPC, high serial pin connector). The VITA 57.4 standard extends the VITA 57.1 FMC standard by specifying two new connectors that increase the number of multi-gigabit interfaces from 10 to 24. Also, there is an optional extension connector (the high serial pin connector extension, or HSPCe) to boost pin-count by 80 positions, arranged in a 4x20 array. The VCU128 board does not implement the high serial pin connector/HSPCe extension.
FMC+ connectors use a 14 x 40 form factor, populated with 560 pins. The connector is keyed so that a mezzanine card, when installed on the VCU128 evaluation board, faces away from the board.
J18 FMC+/FMCP Connectors
This section describes the J18 FMC+/FMCP connectors.
· Samtec SEAF series, 1.27 mm (0.050 in) pitch. Mates with SEAM series connector. More information about SEAF series connectors is available on the Samtec website.
· The 560-pin FMC+ connector defined by the FMC specification (see Appendix A: VITA 57.4 FMCP Connector Pinouts) provides connectivity for up to: 160 single-ended or 80 differential user-defined signals
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24 transceiver differential pairs 6 transceiver differential clocks 4 differential clocks 239 ground and 17 power connections
FMCP Connector J18
[Figure 2, callout 33] The HSPC connector at J18 implements a subset of the full FMCP connectivity: · 68 single-ended or 34 differential user-defined pairs (full LA-bus: LA[00:33]) · 24 transceiver differential pairs · 6 transceiver differential clocks · 2 differential clocks · 239 ground and 14 power connections
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J18 VITA 57.4 FMCP HSCP Connections
The FMCP J18 connections to FPGA U1 are listed in the following table. The net names shown in the table are connected to FMCP HSCP J18 pins.
Table 31: J18 VITA 57.4 FMCP HSCP Connections
J18 FMCP HSCP
Pin
A2 A3 A6 A7 A10 A11 A14 A15 A18 A19
A22
A23 A26 A27 A30 A31 A34 A35 A38 A39
Schematic Net Name
FMCP_HSPC_DP1_M2C_P FMCP_HSPC_DP1_M2C_N FMCP_HSPC_DP2_M2C_P FMCP_HSPC_DP2_M2C_N FMCP_HSPC_DP3_M2C_P FMCP_HSPC_DP3_M2C_N FMCP_HSPC_DP4_M2C_P FMCP_HSPC_DP4_M2C_N FMCP_HSPC_DP5_M2C_P FMCP_HSPC_DP5_M2C_N
FMCP_HSPC_DP1_C2M_P
FMCP_HSPC_DP1_C2M_N FMCP_HSPC_DP2_C2M_P FMCP_HSPC_DP2_C2M_N FMCP_HSPC_DP3_C2M_P FMCP_HSPC_DP3_C2M_N FMCP_HSPC_DP4_C2M_P FMCP_HSPC_DP4_C2M_N FMCP_HSPC_DP5_C2M_P FMCP_HSPC_DP5_C2M_N
I/O Standard
FPGA (U1) Pin
J18 FMCP HSCP
Pin
Schematic Net Name
I/O Standard
FPGA (U1) Pin
J18 Sections A/B Connections to FPGA U1
LVDS
BB51 B1
NC
LVDS
BB52 B4
FMCP_HSPC_DP9_M2C_P
LVDS
AT51
LVDS
BA53 B5
FMCP_HSPC_DP9_M2C_N
LVDS
AT52
LVDS
BA54 B8
FMCP_HSPC_DP8_M2C_P
LVDS
AU53
LVDS
BA49 B9
FMCP_HSPC_DP8_M2C_N
LVDS
AU54
LVDS
BA50 B12
FMCP_HSPC_DP7_M2C_P
LVDS
AV51
LVDS
AY51 B13
FMCP_HSPC_DP7_M2C_N
LVDS
AV52
LVDS
AY52 B16
FMCP_HSPC_DP6_M2C_P
LVDS
AW49
LVDS
AW53 B17
FMCP_HSPC_DP6_M2C_N
LVDS
AW50
LVDS
AW54 B20 FMCP_HSPC_GBTCLK1_M2C_ P
LVDS
AR40
LVDS
BC44
B21 FMCP_HSPC_GBTCLK1_M2C_ N
LVDS
AR41
LVDS
BC45 B24
FMCP_HSPC_DP9_C2M_P
LVDS
AT46
LVDS
BB46 B25
FMCP_HSPC_DP9_C2M_N
LVDS
AT47
LVDS
BB47 B28
FMCP_HSPC_DP8_C2M_P
LVDS
AU48
LVDS
BA44 B29
FMCP_HSPC_DP8_C2M_N
LVDS
AU49
LVDS
BA45 B32
FMCP_HSPC_DP7_C2M_P
LVDS
AU44
LVDS
AY46 B33
FMCP_HSPC_DP7_C2M_N
LVDS
AU45
LVDS
AY47 B36
FMCP_HSPC_DP6_C2M_P
LVDS
AV46
LVDS
AW44 B37
FMCP_HSPC_DP6_C2M_N
LVDS
AV47
LVDS
AW45 B40
NC
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Table 31: J18 VITA 57.4 FMCP HSCP Connections (cont'd)
J18 FMCP HSCP
Pin
C2 C3
C6
C7 C10 C11 C14 C15 C18 C19 C22 C23 C26 C27 C30 C31 C34 C35 C37 C39
Schematic Net Name
FMCP_HSPC_DP0_C2M_P FMCP_HSPC_DP0_C2M_N
FMCP_HSPC_DP0_M2C_P
FMCP_HSPC_DP0_M2C_N FMCP_HSPC_LA06_P FMCP_HSPC_LA06_N FMCP_HSPC_LA10_P FMCP_HSPC_LA10_N FMCP_HSPC_LA14_P FMCP_HSPC_LA14_N
FMCP_HSPC_LA18_CC_P FMCP_HSPC_LA18_CC_N
FMCP_HSPC_LA27_P FMCP_HSPC_LA27_N FMCP_HSPC_IIC_SCL FMCP_HSPC_IIC_SDA
GA0 = 0 = GND VCC12_SW VCC12_SW UTIL_3V3
I/O Standard
FPGA (U1) Pin
J18 FMCP HSCP
Pin
Schematic Net Name
I/O Standard
FPGA (U1) Pin
J18 Sections C/D Connections to FPGA U1
LVDS
BC53 D1
VADJ_PG
LVDS
BC54
D4 FMCP_HSPC_GBTCLK0_M2C_ P
LVDS
AV42
LVDS
BC48
D5 FMCP_HSPC_GBTCLK0_M2C_ N
LVDS
AV43
LVDS
BC49 D8
FMCP_HSPC_LA01_CC_P
LVDS
F26
LVDS
E22
D9
FMCP_HSPC_LA01_CC_N
LVDS
F25
LVDS
D22 D11
FMCP_HSPC_LA05_P
LVDS
H27
LVDS
B23 D12
FMCP_HSPC_LA05_N
LVDS
G27
LVDS
A23 D14
FMCP_HSPC_LA09_P
LVDS
E26
LVDS
C23 D15
FMCP_HSPC_LA09_N
LVDS
D26
LVDS
B22 D17
FMCP_HSPC_LA13_P
LVDS
A25
LVDS
E19
D18
FMCP_HSPC_LA13_N
LVDS
A24
LVDS
E18
D20
FMCP_HSPC_LA17_CC_P
LVDS
F18
LVDS
E21
D21
FMCP_HSPC_LA17_CC_N
LVDS
E17
LVDS
D21 D23
FMCP_HSPC_LA23_P
LVDS
B21
D24
FMCP_HSPC_LA23_N
LVDS
B20
D26
FMCP_HSPC_LA26_P
LVDS
D17
D27
FMCP_HSPC_LA26_N
LVDS
D16
D29
FMCP_HSPC_TCK_BUF
D30
FPGA_TDO_FMC_TDI_BUF
D31 FMCP_HSPC_TDO_HPC1_TDI
D32
UTIL_3V3
D33
FMCP_HSPC_TMS_BUF
D34
NC
D35
GA1 = 0 = GND
D36
UTIL_3V3
D38
UTIL_3V3
D40
UTIL_3V3
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Table 31: J18 VITA 57.4 FMCP HSCP Connections (cont'd)
J18 FMCP HSCP
Pin
G2 G3 G6 G7 G9 G10 G12 G13 G15 G16 G18 G19 G21 G22 G24 G25 G27 G28 G30 G31 G33 G34 G36 G37 G39
Schematic Net Name
FMCP_HSPC_CLK1_M2C_P FMCP_HSPC_CLK1_M2C_N
FMCP_HSPC_LA00_CC_P FMCP_HSPC_LA00_CC_N
FMCP_HSPC_LA03_P FMCP_HSPC_LA03_N FMCP_HSPC_LA08_P FMCP_HSPC_LA08_N FMCP_HSPC_LA12_P FMCP_HSPC_LA12_N FMCP_HSPC_LA16_P FMCP_HSPC_LA16_N FMCP_HSPC_LA20_P FMCP_HSPC_LA20_N FMCP_HSPC_LA22_P FMCP_HSPC_LA22_N FMCP_HSPC_LA25_P FMCP_HSPC_LA25_N FMCP_HSPC_LA29_P FMCP_HSPC_LA29_N FMCP_HSPC_LA31_P FMCP_HSPC_LA31_N FMCP_HSPC_LA33_P FMCP_HSPC_LA33_N
VADJ_1V8_FPGA
I/O Standard
FPGA (U1) Pin
J18 FMCP HSCP
Pin
Schematic Net Name
J18 Sections G/H Connections to FPGA U1
LVDS
G18
H1
FMCP_HSPC_VREF_A_M2C
LVDS
G17
H2 FMCP_HSPC_PRSNT_M2C_B
LVDS
E24
H4
FMCP_HSPC_CLK0_M2C_P
LVDS
E23
H5
FMCP_HSPC_CLK0_M2C_N
LVDS
B27
H7
FMCP_HSPC_LA02_P
LVDS
A26
H8
FMCP_HSPC_LA02_N
LVDS
E27
H10
FMCP_HSPC_LA04_P
LVDS
D27 H11
FMCP_HSPC_LA04_N
LVDS
J22
H13
FMCP_HSPC_LA07_P
LVDS
H22 H14
FMCP_HSPC_LA07_N
LVDS
K24
H16
FMCP_HSPC_LA11_P
LVDS
K23
H17
FMCP_HSPC_LA11_N
LVDS
A21 H19
FMCP_HSPC_LA15_P
LVDS
A20 H20
FMCP_HSPC_LA15_N
LVDS
B16 H22
FMCP_HSPC_LA19_P
LVDS
A16 H23
FMCP_HSPC_LA19_N
LVDS
D20 H25
FMCP_HSPC_LA21_P
LVDS
D19 H26
FMCP_HSPC_LA21_N
LVDS
H19 H28
FMCP_HSPC_LA24_P
LVDS
H18 H29
FMCP_HSPC_LA24_N
LVDS
H17 H31
FMCP_HSPC_LA28_P
LVDS
G16 H32
FMCP_HSPC_LA28_N
LVDS
K21
H34
FMCP_HSPC_LA30_P
LVDS
J21
H35
FMCP_HSPC_LA30_N
H37
FMCP_HSPC_LA32_P
H38
FMCP_HSPC_LA32_N
H40
VADJ
I/O Standard
FPGA (U1) Pin
LVDS
F24
LVDS
F23
LVDS
L23
LVDS
K22
LVDS
C25
LVDS
C24
LVDS
K27
LVDS
J27
LVDS
B26
LVDS
B25
LVDS
J26
LVDS
J25
LVDS
B18
LVDS
B17
LVDS
A19
LVDS
A18
LVDS
C18
LVDS
C17
LVDS
G21
LVDS
F21
LVDS
J20
LVDS
J19
LVDS
H20
LVDS
G20
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Table 31: J18 VITA 57.4 FMCP HSCP Connections (cont'd)
J18 FMCP HSCP
Pin
Schematic Net Name
I/O Standard
FPGA (U1) Pin
J18 FMCP HSCP
Pin
Schematic Net Name
J18 Sections L/M Connections to FPGA U1
L1
NC
M2
FMCP_HSPC_DP23_M2C_P
L4 FMCP_HSPC_GBTCLK4_M2C _P(5)
LVDS
AJ40
M3
FMCP_HSPC_DP23_M2C_N
L5 FMCP_HSPC_GBTCLK4_M2C _N(5)
LVDS
AJ41
M6
FMCP_HSPC_DP22_M2C_P
L8 FMCP_HSPC_GBTCLK3_M2C _P(5)
LVDS
AL40
M7
FMCP_HSPC_DP22_M2C_N
L9 FMCP_HSPC_GBTCLK3_M2C _N(5)
LVDS
AL41 M10 FMCP_HSPC_DP21_M2C_P
L12 FMCP_HSPC_GBTCLK2_M2C _P(5)
LVDS
AN40 M11 FMCP_HSPC_DP21_M2C_N
L13 FMCP_HSPC_GBTCLK2_M2C _N(5)
LVDS
AN41 M14 FMCP_HSPC_DP20_M2C_P
L16 FMCP_HSPC_SYNC_C2M_P
LVDS
D25 M15 FMCP_HSPC_DP20_M2C_N
L17 FMCP_HSPC_SYNC_C2M_N
LVDS
D24 M18 FMCP_HSPC_DP14_C2M_P
L20 FMCP_HSPC_REFCLK_C2M_ P
LVDS
H24 M19 FMCP_HSPC_DP14_C2M_N
L21 FMCP_HSPC_REFCLK_C2M_ N
LVDS
H23 M22 FMCP_HSPC_DP15_C2M_P
L24 FMCP_HSPC_REFCLK_M2C_ P
LVDS
G26 M23 FMCP_HSPC_DP15_C2M_N
L25 FMCP_HSPC_REFCLK_M2C_ N
LVDS
G25 M26 FMCP_HSPC_DP16_C2M_P
L28 FMCP_HSPC_SYNC_M2C_P
LVDS
G23 M27 FMCP_HSPC_DP16_C2M_N
L29 FMCP_HSPC_SYNC_M2C_N
LVDS
G22 M30 FMCP_HSPC_DP17_C2M_P
L32
NC
M31 FMCP_HSPC_DP17_C2M_N
L33
NC
M34 FMCP_HSPC_DP18_C2M_P
L36
VCC12_SW
M35 FMCP_HSPC_DP18_C2M_N
L37
VCC12_SW
M38 FMCP_HSPC_DP19_C2M_P
L40
VCC12_SW
M39 FMCP_HSPC_DP19_C2M_N
I/O Standard
FPGA (U1) Pin
LVDS LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS LVDS LVDS
LVDS
LVDS
LVDS
LVDS LVDS LVDS LVDS LVDS LVDS LVDS
AE49 AE50
AE53
AE54
AF51
AF52
AG53
AG54 AM46 AM47
AL44
AL45
AK46
AK47 AJ48 AJ49 AJ44 AJ45 AH46 AH47
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Table 31: J18 VITA 57.4 FMCP HSCP Connections (cont'd)
J18 FMCP HSCP
Pin
Y2 Y3 Y6 Y7 Y10 Y11 Y14 Y15 Y18 Y19
Y22
Y23 Y26 Y27 Y30 Y31 Y34 Y35 Y38 Y39
Schematic Net Name
FMCP_HSPC_DP23_C2M_P FMCP_HSPC_DP23_C2M_N FMCP_HSPC_DP21_C2M_P FMCP_HSPC_DP21_C2M_N FMCP_HSPC_DP10_M2C_P FMCP_HSPC_DP10_M2C_N FMCP_HSPC_DP12_M2C_P FMCP_HSPC_DP12_M2C_N FMCP_HSPC_DP14_M2C_P FMCP_HSPC_DP14_M2C_N
FMCP_HSPC_DP15_M2C_P
FMCP_HSPC_DP15_M2C_N FMCP_HSPC_DP11_C2M_P FMCP_HSPC_DP11_C2M_N FMCP_HSPC_DP13_C2M_P FMCP_HSPC_DP13_C2M_N FMCP_HSPC_DP17_M2C_P FMCP_HSPC_DP17_M2C_N FMCP_HSPC_DP19_M2C_P FMCP_HSPC_DP19_M2C_N
I/O Standard
FPGA (U1) Pin
J18 FMCP HSCP
Pin
Schematic Net Name
I/O Standard
FPGA (U1) Pin
J18 Sections Y/Z Connections to FPGA U1
LVDS
AE44
Z1
FMCP_HSPC_PRSNT_M2C_B
LVDS
AE45
Z4
FMCP_HSPC_DP22_C2M_P
LVDS
AF46
LVDS
AG44 Z5
FMCP_HSPC_DP22_C2M_N
LVDS
AF47
LVDS
AG45 Z8
FMCP_HSPC_DP20_C2M_P
LVDS
AG48
LVDS
AR53
Z9
FMCP_HSPC_DP20_C2M_N
LVDS
AG49
LVDS
AR54 Z12
FMCP_HSPC_DP11_M2C_P
LVDS
AP51
LVDS
AN53 Z13
FMCP_HSPC_DP11_M2C_N
LVDS
AP52
LVDS
AN54 Z16
FMCP_HSPC_DP13_M2C_P
LVDS
AN49
LVDS
AM51 Z17
FMCP_HSPC_DP13_M2C_N
LVDS
AN50
LVDS
AM52 Z20 FMCP_HSPC_GBTCLK5_M2C_ P
LVDS
AG40
LVDS
AL53
Z21 FMCP_HSPC_GBTCLK5_M2C_ N
LVDS
AG41
LVDS
AL54 Z24
FMCP_HSPC_DP10_C2M_P
LVDS
AR48
LVDS
AR44 Z25
FMCP_HSPC_DP10_C2M_N
LVDS
AR49
LVDS
AR45 Z28
FMCP_HSPC_DP12_C2M_P
LVDS
AP46
LVDS
AN44 Z29
FMCP_HSPC_DP12_C2M_N
LVDS
AP47
LVDS
AN45 Z32
FMCP_HSPC_DP16_M2C_P
LVDS
AL49
LVDS
AK51 Z33
FMCP_HSPC_DP16_M2C_N
LVDS
AL50
LVDS
AK52 Z36
FMCP_HSPC_DP18_M2C_P
LVDS
AJ53
LVDS
AH51 Z37
FMCP_HSPC_DP18_M2C_N
LVDS
AJ54
LVDS
AH52 Z40
UTIL_3V3
More information about the VITA 57.4 FMC+ specification is available on the VITA FMC Marketing Alliance website.
Board Power System
[Figure 2, callout 34]
The VCU128 board has an Intersil power system. The following figure shows the VCU128 board power system block diagram.
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Figure 29: Power System Block Diagram
12V Vin
252W (PCIe brick option)
*Wattage calculations based on XPE requirements plus 25% overhead for soft IP flexibility
UTIL_3V3 3.3V @ 20A ISL68301 + ISL99227B
DDR4_VTERM_0V6 0.6V @ 3A TPS51200
UTIL_5V0 5.0V @ 20A ISL68301 + ISL99227B
62W
RLD3_VTERM_0V6 0.6V @ 3A TPS51200
VCC1V8 1.8V @ 6A ISL91302B (A+B)
VADJ 1.8V @ 6A ISL91302B (C+D)
16W
Current Shunt
SYS_1V8 1.8V @ 1A ISL91211 (A)
MGTVCCAUX 1.8V @ 1A
ISL91211A (B)
MGTAVCC 0.9V @ 10A ISL91211A (C+D)
QDR4_VDDQ_1V2 1.2V @ 6A
ISL91302 (A+B)
UTIL_1V30 1.30V @ 6A ISL91302B (C+D)
11W Current Shunt Current Shunt
12W
VCCHBM 1.2V @ 25A ISL68301 + ISL99227B
MGTAVTT 1.2V @ 20A ISL68301 + ISL99227B
VCCINT 0.85V @ 125A
ISL68127 + ISL919227 (5)
VCCBRAM 0.85V @ 30A ISL68127 + ISL919227 (1)
22W 18W 103W
DDR4_VDDQ_1V2 1.2V @ 3A
ISL91302 (A+B+D)
RLD3_VDDQ_1V2 1.2V @ 10A ISL91302 (C)
UTIL_1V35 1.35V @ 10A ISL91302B (A+B+D)
SYS_1V0 1.0V @ 2A ISL91302B (C)
VCCAUX_HBM 2.5V @ 1.5A ISL80019
11W 10W 2W
Current Shunt Current Shunt
Current Shunt
Current Shunt Current Shunt
X21654-040821
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Chapter 3: Board Component Descriptions
Onboard Power System Devices
The VCU128 evaluation board uses programmable power regulators from Intersil Corporation to supply the core and auxiliary voltages listed in the following table.
Table 32: Onboard Power System Devices
Schematic Page
Rail Name
Regulator Type
U#
Vout (V)
Iout Range
(A)
I2C Address
Programmable Regulators and INA226 Map
Programmable Regulators
54
VCCINT (PWM[2:6])
ISL68127IRAZ-TR5823 U31 0.72 - 125 0.851
54
VCCBRAM (PWM[0])
ISL68127IRAZ-TR5823 U31 0.72 - 30
0.851
56
VCC1V8 (PH_A/B)
ISL91302BIKZ-TR5814 U15 1.8
4 - 6
56
VADJ (PH_C/D)
ISL91302BIKZ-TR5814 U15 0, 0.3 4.5 - 6 -1.8
57
VCCHBM
ISL68301IRAZ-TR5823 U36 1.2
25
57
MGTAVTT
ISL68301IRAZ-TR5823 U24 1.2
20
58
SYS_1V8 (PH_A)
ISL91211AIKZ-TR5818 U22 1.8 0.75 - 1
58
MGTVCCAUX (PH_B)
ISL91211AIKZ-TR5818 U22 1.8 0.75 - 1
58
MGTAVCC (PH_C/D)
ISL91211AIKZ-TR5818 U22 0.9 8 - 10
59
QDR4_VDDQ (PH_A/B) ISL91302BIKZ-TR5815 U44 1.2
5 - 6
59
UTIL_1V30 (PH_C/D)
ISL91302BIKZ-TR5815 U44 1.3 4.5 - 6
60
RLD3_VDDQ (PH_A/B/D) ISL91302BIKZ-TR5816 U67 1.2 7 - 10
60
DDR4_VDDQ (PH_C)
ISL91302BIKZ-TR5816 U67 1.2 2.5 - 3
61
UTIL_1V35 (PH_A/B/D) ISL91302BIKZ-TR5817 U68 1.35 6.5 - 10
61
SYS_1V0 (PH_C)
ISL91302BIKZ-TR5817 U68 1 1.75 - 2
62
UTIL_3V3
ISL68301IRAZ-TR5826 U3 3.3
30
62
UTIL_5V0
ISL68301IRAZ-TR5825 U12 5
20
Non-I2C Regulators
63
VCCAUX_HBM
SL80019FRZ-T7A
U29 2.5
1.5
65
VCC_3V3
ISL85415FRZ-T7A
U25 3.3
20
33
DDR4_VTERM_0V6
TPS51200DR
U71 0.6
3
33
RLD3_VTERM_0V6
TPS51200DR
U92 0.6
3
Notes: 1. Jumper selectable at 3-pin header J25: 1-2=0.85V (default); 2-3=0.72V.
0X65
0X65
0x63 0x63
0x68 0x69 0x60 0x60 0x60 0x62 0x62 0x64 0x64 0x61 0x61 0x6A 0x6B
NA NA NA NA
INA226
U#
I2C Address
U84
0x40
U86
0x41
U14
0X42
NA
NA
U85
0x4C
U21
0x47
NA
NA
U20
0x48
U16
0x46
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
U79 0x4D
NA
NA
NA
NA
NA
NA
Documentation describing the programming of the Intersil power controllers is available on the Intersil website (see References). The PCB layout and power system design meet the recommended criteria described in the UltraScale Architecture PCB Design User Guide (UG583).
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Chapter 3: Board Component Descriptions
FMCP HSPC Connector J18 VADJ Power Rail
The VCU128 evaluation board implements the ANSI/VITA 57.4 IPMI support functionality. The power control of the VADJ power rail is managed by the U42 system controller. This rail powers both the FMCP HSPC (J18) VADJ pins, as well as XCVU37P U1 HP banks 71 and 72 (see I/O Voltage Rails). The valid values of the VADJ rail are 1.2V, 1.5V, and 1.8V.
At power on, the system controller detects if an FMC module is connected to FMCP J18:
· If no FMC card is attached to the FMC port, the VADJ voltage is set to 0V
· When an FMC card is attached, its IIC EEPROM is read to find a VADJ voltage supported by both the VCU128 board and the FMC module, within the available choices of 1.2V, 1.5V, 1.8V, and 0.0V
· If no valid information is found in the IIC EEPROM, the VADJ rail is set to 0V
The system controller user interface allows the FMC IPMI routine to be overridden and an explicit value to be set for the VADJ rail.
Monitoring Voltage and Current
[Figure 2, callout 35]
Voltage and current monitoring and control for the Intersil power system is available through either the VCU128 system controller or the Intersil PowerNavigator software GUI. The VCU128 system controller is a simple and convenient way to monitor the voltage and current values for the power rails listed in the following table. The Intersil programmable power controllers listed in the table can also be accessed through the 2x3 male pin header J1. Using this connector requires the Intersil ZLUSBEVAL3Z USB to PMBus adapter. This adapter cable can be ordered from the Intersil website (see References). The associated Intersil PowerNavigator software GUI can be downloaded from the Intersil website. The Intersil programmable controller and INA226 power monitor I2C bus mapping is shown in the following table.
Table 33: Programmable Controller and INA226 Power Monitor I2C Bus Mapping
Schematic Page
54 54 56
Rail Name
Regulator Type
U#
Vout (V)
Iout Range
(A)
I2C Address
Programmable Regulators and INA226 Map
Programmable Regulators
VCCINT (PWM[2:6]) ISL68127IRAZ-TR5823 U31 0.72 - 125 0.851
VCCBRAM (PWM[0]) ISL68127IRAZ-TR5823 U31 0.72 - 30 0.851
VCC1V8 (PH_A/B)
ISL91302BIKZ-TR5814 U15 1.8
4 - 6
0X65 0X65 0x63
INA226
U#
I2C Address
U84
0x40
U86
0x41
U14
0X42
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Chapter 3: Board Component Descriptions
Table 33: Programmable Controller and INA226 Power Monitor I2C Bus Mapping (cont'd)
Schematic Page
Rail Name
Regulator Type
U#
Vout (V)
Iout Range
(A)
I2C Address
56
VADJ (PH_C/D)
ISL91302BIKZ-TR5814 U15 0, 0.3
-1.8
57
VCCHBM
ISL68301IRAZ-TR5823 U36 1.2
57
MGTAVTT
ISL68301IRAZ-TR5823 U24 1.2
58
SYS_1V8 (PH_A)
ISL91211AIKZ-TR5818 U22 1.8
58
MGTVCCAUX (PH_B) ISL91211AIKZ-TR5818 U22 1.8
58
MGTAVCC (PH_C/D) ISL91211AIKZ-TR5818 U22 0.9
59
QDR4_VDDQ (PH_A/B) ISL91302BIKZ-TR5815 U44 1.2
59
UTIL_1V30 (PH_C/D) ISL91302BIKZ-TR5815 U44 1.3
60
RLD3_VDDQ (PH_A/B/D) ISL91302BIKZ-TR5816 U67 1.2
60
DDR4_VDDQ (PH_C) ISL91302BIKZ-TR5816 U67 1.2
61
UTIL_1V35 (PH_A/B/D) ISL91302BIKZ-TR5817 U68 1.35
61
SYS_1V0 (PH_C)
ISL91302BIKZ-TR5817 U68 1
62
UTIL_3V3
ISL68301IRAZ-TR5826 U3 3.3
62
UTIL_5V0
ISL68301IRAZ-TR5825 U12 5
Non-I2C Regulators
63
VCCAUX_HBM
SL80019FRZ-T7A
U29 2.5
65
VCC_3V3
ISL85415FRZ-T7A
U25 3.3
33
DDR4_VTERM_0V6
TPS51200DR
U71 0.6
33
RLD3_VTERM_0V6
TPS51200DR
U92 0.6
Notes: 1. Jumper selectable at 3-pin header J25: 1-2 = 0.85V (default); 2-3 = 0.72V.
4.5 - 6
25 20 0.75 - 1 0.75 - 1 8 - 10 5 - 6 4.5 - 6 7 - 10 2.5 - 3 6.5 - 10 1.75 - 2 30 20
1.5 20 3 3
0x63
0x68 0x69 0x60 0x60 0x60 0x62 0x62 0x64 0x64 0x61 0x61 0x6A 0x6B
NA NA NA NA
INA226
U#
I2C Address
NA
NA
U85
0x4C
U21
0x47
NA
NA
U20
0x48
U16
0x46
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
U79 0x4D
NA
NA
NA
NA
NA
NA
Cooling Fan
The XCVU37P FPGA U1 cooling fan connector is shown in the following figure. The VCU128 fan circuit uses a Maxim MAX6643 fan controller that autonomously monitors the FPGA die temperature pins DXP and DXN. The fan circuit is set up to increase fan speed as the FPGA temperature increases.
Note: At initial power on, it is normal for the fan controller to energize at full speed for a few seconds.
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Chapter 3: Board Component Descriptions
Figure 30: Cooling Fan Circuit
X21975-112818
System Controller
[Figure 2, callout 8] The VCU128 board includes an onboard Zynq®-7000 SoC U42 as the system controller. A host PC resident graphical user interface for the system controller (SCUI) is provided on the VCU128 website. The SCUI can be used to query and control select programmable features such as clocks, FMC functionality, and power systems. The VCU128 evaluation kit website also includes a VCU128 System Controller Tutorial (XTP534) and the VCU128 Software Install and Board Setup Tutorial (XTP535). A summary of the steps is as follows. 1. Ensure the Silicon Labs VCP USB-UART drivers are installed on the host PC. See the Silicon
Labs CP210x USB-to-UART Installation Guide (UG1033). 2. Download the SCUI host PC application. 3. Connect the micro-B USB cable between the VCU128 board USB-UART connector (J2) and
the host PC. 4. Power-cycle the VCU128 board. 5. Launch the SCUI as shown in the following example.
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Chapter 3: Board Component Descriptions
X21976-112818
See the VCU128 System Controller Tutorial (XTP534) and the VCU128 Software Install and Board Setup Tutorial (XTP535) for more information on installing and using the System Controller utility.
Configuration Options
[Figure 2, callout 36]
The VCU128 board supports two of the seven UltraScaleTM FPGA configuration modes.
· Master SPI using the onboard 2 Gbit Quad SPI flash memory · JTAG using:
USB JTAG configuration port J2 (FTDI FT4232H bridge U8)
Xilinx® platform cable 2 mm, keyed flat cable header (J4)
Each configuration interface corresponds to one or more configuration modes and bus widths as listed in the following table. The mode switches M2, M1, and M0 are on 4-pole DIP SW1 positions 2, 3, and 4, respectively. The FPGA default mode setting M[2:0] = 001, selecting the master SPI configuration mode.
Table 34: Board FPGA Configuration Modes
Configuration Mode
Master SPI JTAG
SW16 DIP Switch Settings (M[2:0])
1
101
Bus Width
x1, x2, x4 x1
CCLK Direction
Output Not applicable
The following figure shows mode switch SW1.
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Chapter 3: Board Component Descriptions Figure 31: SW1 JTAG Settings
X21977-112818
The mode pins settings on SW1 determine if the Quad SPI flash is used for configuring the FPGA. DIP switch SW1 also includes a system controller enable switch in position 1. See the UltraScale Architecture Configuration User Guide (UG570) for further details on configuration modes.
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Appendix A: VITA 57.4 FMCP Connector Pinouts
Appendix A
VITA 57.4 FMCP Connector Pinouts
Overview
The following figure shows the pinout of the FPGA mezzanine card plus (FMCP) connector J18 defined by the VITA 57.4 FMC specification. For a description of how the VCU128 evaluation board implements the FMCP specification, see FPGA Mezzanine Card Interface.
Figure 32: FMCP Connector Pinouts
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Appendix B: Xilinx Constraints File
Appendix B
Xilinx Constraints File
Overview
The Xilinx® design constraints (XDC) file template for the VCU128 board provides for designs targeting the VCU128 evaluation board. Net names in the constraints listed correlate with net names on the latest VCU128 evaluation board schematic. Identify the appropriate pins and replace the net names with the net names in the user RTL. See the Vivado Design Suite User Guide: Using Constraints (UG903) for more information. The FMCP connector J18 (HSCP) is connected to 1.8V (nominal) VADJ banks 70 and 71. Because different FMC cards implement different circuitry, the FMC bank I/O standards must be uniquely defined by each customer.
IMPORTANT! See VCU128 board documentation for the XDC file.
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Appendix C: Regulatory and Compliance Information
Appendix C
Regulatory and Compliance Information
Overview
This product is designed and tested to conform to the European Union directives and standards described in this section. VCU128 Evaluation Kit - Master Answer Record 71849 For Technical Support, open a Support Service Request.
CE Directives
2006/95/EC, Low Voltage Directive (LVD) 2004/108/EC, Electromagnetic Compatibility (EMC) Directive
CE Standards
EN standards are maintained by the European Committee for Electrotechnical Standardization (CENELEC). IEC standards are maintained by the International Electrotechnical Commission (IEC).
Electromagnetic Compatibility
EN 55022:2010, Information Technology Equipment Radio Disturbance Characteristics Limits and Methods of Measurement EN 55024:2010, Information Technology Equipment Immunity Characteristics Limits and Methods of Measurement
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Appendix C: Regulatory and Compliance Information
This is a Class A product. In a domestic environment, this product can cause radio interference, in which case the user might be required to take adequate measures.
Safety
IEC 60950-1:2005, Information technology equipment Safety, Part 1: General requirements EN 60950-1:2006, Information technology equipment Safety, Part 1: General requirements
Compliance Markings
In August of 2005, the European Union (EU) implemented the EU Waste Electrical and Electronic Equipment (WEEE) Directive 2002/96/EC and later the WEEE Recast Directive 2012/19/EU. These directives require Producers of electronic and electrical equipment (EEE) to manage and finance the collection, reuse, recycling and to appropriately treat WEEE that the Producer places on the EU market after August 13, 2005. The goal of this directive is to minimize the volume of electrical and electronic waste disposal and to encourage re-use and recycling at the end of life. Xilinx has met its national obligations to the EU WEEE Directive by registering in those countries to which Xilinx is an importer. Xilinx has also elected to join WEEE Compliance Schemes in some countries to help manage customer returns at end-of-life. If you have purchased Xilinx-branded electrical or electronic products in the EU and are intending to discard these products at the end of their useful life, please do not dispose of them with your other household or municipal waste. Xilinx has labeled its branded electronic products with the WEEE Symbol to alert our customers that products bearing this label should not be disposed of in a landfill or with municipal or household waste in the EU.
This product complies with Directive 2002/95/EC on the restriction of hazardous substances (RoHS) in electrical and electronic equipment.
This product complies with CE Directives 2006/95/EC, Low Voltage Directive (LVD) and 2004/108/EC, Electromagnetic Compatibility (EMC) Directive.
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Appendix D: Additional Resources and Legal Notices
Appendix D
Additional Resources and Legal Notices
Xilinx Resources
For support resources such as Answers, Documentation, Downloads, and Forums, see Xilinx Support.
Documentation Navigator and Design Hubs
Xilinx® Documentation Navigator (DocNav) provides access to Xilinx documents, videos, and support resources, which you can filter and search to find information. To open DocNav: · From the Vivado® IDE, select HelpDocumentation and Tutorials. · On Windows, select StartAll ProgramsXilinx Design ToolsDocNav. · At the Linux command prompt, enter docnav. Xilinx Design Hubs provide links to documentation organized by design tasks and other topics, which you can use to learn key concepts and address frequently asked questions. To access the Design Hubs: · In DocNav, click the Design Hubs View tab. · On the Xilinx website, see the Design Hubs page. Note: For more information on DocNav, see the Documentation Navigator page on the Xilinx website.
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Appendix D: Additional Resources and Legal Notices
References
The most up to date information related to the VCU128 board and its documentation is available on the following websites.
VCU128 Evaluation Kit
VCU128 Evaluation Kit - Master Answer Record 71849
These documents provide supplemental material useful with this guide:
1. Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS923) 2. UltraScale Architecture Configuration User Guide (UG570) 3. UltraScale Architecture SelectIO Resources User Guide (UG571) 4. UltraScale Architecture-Based FPGAs Memory IP LogiCORE IP Product Guide (PG150) 5. UltraScale Architecture Clocking Resources User Guide (UG572) 6. UltraScale Architecture GTY Transceivers User Guide (UG578) 7. UltraScale FPGAs Transceivers Wizard LogiCORE IP Product Guide (PG182) 8. UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156) 9. Tri-Mode Ethernet MAC LogiCORE IP Product Guide (PG051) 10. AXI UART Lite LogiCORE IP Product Guide (PG142) 11. Vivado Design Suite User Guide: Using Constraints (UG903) 12. UltraScale Architecture PCB Design User Guide (UG583) 13. Silicon Labs CP210x USB-to-UART Installation Guide (UG1033) 14. VCU128 System Controller Tutorial (XTP534) 15. VCU128 Software Install and Board Setup Tutorial (XTP535) 16. VCU128 Restoring Flash Tutorial (XTP533) 17. For additional documents associated with Xilinx devices, design tools, intellectual property,
boards, and kits see the Xilinx documentation website. These websites provide supplemental material useful with this guide: 18. Xilinx, Inc.
(XCVU37P-2FSVH2892E) 19. Micron Technology
(MT40A512M16LY-075E, MT44K32M36RB-083E, MT25QU02GCBB8E12-0SIT) 20. http://www.cypress.com (CY7C4142KV13_106FCXC)
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Appendix D: Additional Resources and Legal Notices
21. Silicon Labs (Si570, Si5328B) 22. SiTime Corp. (SIT9120AI) 23. Future Technology Devices International Ltd. (FT232HL) 24. SNIA Technology Affiliates (SFF-8663, SFF-8679) 25. PCI Express® standard 26. Texas Instruments (TCA9548, PCA9544, DP83867ISRGZ) 27. Samtec, Inc. 28. VITA FMC Marketing Alliance
(FPGA Mezzanine Card (FMC) VITA 57.4 specification) This standard extends the VITA 57.1 FMC standard by specifying two new connectors that enable additional Gigabit Transceiver interfaces that run at up to 28 Gb/s. It also describes FMC+ I/O modules that support this enhanced version of the FMC electro-mechanical standard. This is between the front panel I/O, on the mezzanine module, and an FPGA processing device on the carrier card, which accepts the mezzanine module. Additional signals to support backplane reference clock and synchronization have been added. The VITA 57.4 specification is backwards compatible in that a VITA 57.4 carrier card can still support a VITA 57 FMC. 29. Intersil Corporation (a wholly owned subsidiary of Renesas Electronics Corporation) The Intersil PowerNavigator software is available at: https://www.intersil.com/en/ products/power-management/zilker-labs-digital-power/powernavigator.html The Intersil USB to PMBUS ZLUSBEVAL3Z Dongle is available at: https:// www.intersil.com/en/tools/reference-designs/zlusbeval3z.html
ATX Power Supply Adapter Cable
The Xilinx ATX cable part number 2600304 is manufactured by Sourcegate Technologies and is equivalent to the Sourcegate Technologies part number AZCBL-WH-11009.
Sourcegate only manufactures the latest revision, which is currently A4. To order, contact Aries Ang, aries.ang@sourcegate.net, +65 6483 2878 for price and availability. This is a custom cable and cannot be ordered from the Sourcegate website.
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Please Read: Important Legal Notices
The information disclosed to you hereunder (the "Materials") is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of Xilinx's limited warranty, please refer to Xilinx's Terms of Sale which can be viewed at https:// www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in such critical applications, please refer to Xilinx's Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos.
AUTOMOTIVE APPLICATIONS DISCLAIMER
AUTOMOTIVE PRODUCTS (IDENTIFIED AS "XA" IN THE PART NUMBER) ARE NOT WARRANTED FOR USE IN THE DEPLOYMENT OF AIRBAGS OR FOR USE IN APPLICATIONS THAT AFFECT CONTROL OF A VEHICLE ("SAFETY APPLICATION") UNLESS THERE IS A SAFETY CONCEPT OR REDUNDANCY FEATURE CONSISTENT WITH THE ISO 26262 AUTOMOTIVE SAFETY STANDARD ("SAFETY DESIGN"). CUSTOMER SHALL, PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE PRODUCTS, THOROUGHLY TEST SUCH SYSTEMS FOR SAFETY PURPOSES. USE OF PRODUCTS IN A SAFETY APPLICATION WITHOUT A SAFETY DESIGN IS FULLY AT THE RISK OF CUSTOMER, SUBJECT ONLY TO APPLICABLE LAWS AND REGULATIONS GOVERNING LIMITATIONS ON PRODUCT LIABILITY.
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© Copyright 2018-2021 Xilinx, Inc. Xilinx, the Xilinx logo, Alveo, Artix, Kintex, Spartan, Versal, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries.PCI, PCIe, and PCI Express are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
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