IS2083 Bluetooth Stereo Audio SoC Data Sheet

Data Sheet

Microchip Technology Inc.

IS2083 Bluetooth Stereo Audio SoC Data Sheet

IS2083 Bluetooth Stereo Audio SoC Data Sheet Introduction The IS2083 is a System-on-Chip (SoC) for dual mode Bluetooth stereo audio applications. It contains an on-board Bluetooth stack, audio profiles and supports 24-bit/96 kHz high-resolution (Hi-Res) audio formats to enable high-fidelity wireless audio.

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IS2083
IS2083 Bluetooth® Stereo Audio SoC Data Sheet

Introduction
The IS2083 is a System-on-Chip (SoC) for dual mode Bluetooth stereo audio applications. It contains an on-board Bluetooth stack, audio profiles and supports 24-bit/96 kHz high-resolution (Hi-Res) audio formats to enable highfidelity wireless audio. An integrated Digital Signal Processor (DSP) decodes (LDAC, Advanced Audio Codec (AAC), and Sub-band Codec (SBC) codecs) and executes advanced audio and voice processing (wideband speech, Acoustic Echo Cancellation (AEC), and Noise Reduction (NR)). This platform provides a Microcontroller (MCU) core for application implementation via Software Development Kit (SDK) with debug support and a GUI (Config Tool) tool for easy customization of peripheral settings and DSP functionality.
Note: Contact your local sales representative for more information about the Software Development Kit (SDK).
The IS2083 SoC is offered in a BGA package and contains in-package Flash, and is referred to as IS2083BM.
The IS2083BM supports Over-the-Air (OTA) firmware upgrade and controls the end-application via Bluetooth Low Energy using the Microchip Bluetooth Audio (MBA) mobile app.
Features
· Qualified for Bluetooth v5.0 specification Hands-free Profile (HFP) 1.7, Headset Profile (HSP) 1.2, Advanced Audio Distribution Profile (A2DP) 1.3, Serial Port Profile (SPP) 1.2, Audio/Video Remote Control Profile (AVRCP) 1.6, and Phone Book Access Profile (PBAP) 1.2 Bluetooth classic (BR/EDR) and Bluetooth Low Energy General Attribute Profile (GATT) and General Access Profile (GAP) Bluetooth Low Energy Data Length Extension (DLE) and secure connection
· Software Development Kit 8051 microcontroller debugging 24-bit program counter and Data Pointer modes
· Audio interfaces Stereo line input Two analog microphones One stereo digital microphone Stereo audio Digital-to-Analog Converter (DAC) I2S input/output I2S Master clock (MCLK)/reference clock
· USB, UART, and Over-the-Air (OTA) firmware upgrade · Built-in lithium-ion and lithium polymer battery charger (up to 350 mA) · Integrated 3V and 1.8V configurable switching regulator and Low-Dropout (LDO)
Radio Frequency (RF)/Analog · Bluetooth 5.0 dual mode RF radio · Receive sensitivity: 90 dBm (2 Mbps EDR) · Programmable transmit output power:

Datasheet

DS70005403B-page 1

IS2083
Up to +11 dBm (typical) for Basic Data Rate (BDR) Up to +9.5 dBm (typical) for Enhanced Data Rate (EDR) · Integrated Medium Power Amplifier (MPA) and Low Power Amplifier (LPA)
MCU Features · 8051 8-bit core · 8-bit data · 24-bit program counter (PC24) mode · 24-bit data pointer (DPTR24) mode · Operating speed: DC 48 MHz clock input 0.33-1 MIPS/MHz, depending on instruction
DSP Voice and Audio Processing · 16/32-bit DSP core with enhanced 32-bit precision, single cycle multiplier · Synchronous Connection-Oriented (SCO) channel operation · Modified Sub-Band Coding (mSBC) decoder for wideband speech · Built-in High-definition Clean Audio (HCA) algorithms for both narrowband and wideband speech processing · Built-in audio effect algorithms to enhance audio streaming · 64 Kbps A-Law, -Law Pulse Code Modulation (PCM), or Continuous Variable Slope Delta (CVSD) modulation for SCO channel operation · 8/16 kHz Noise Reduction (NR) · 8/16 kHz Acoustic Echo Cancellation (AEC) · Packet Loss Concealment (PLC) for SBC and mSBC codecs only
Audio Codec · Sub-band Codec (SBC), Advanced Audio Codec (AAC), and LDAC Decoding (IS2083BM-2L2 only) · 20-bit audio stereo DAC with SNR 95 dB · 16-bit audio stereo ADC with SNR 90 dB · 24-bit, I2S digital audio: 96 kHz output sampling frequency 48 kHz input sampling frequency
Peripherals · Successive Approximation Register Analog-to-Digital Converter (SAR ADC) with dedicated channels: Battery voltage detection and adapter voltage detection Charger thermal protection and ambient temperature detection · UART (with hardware flow control) · USB (full-speed USB 1.1 interface) · I2CTM Master · One Pulse Width Modulation (PWM) channel · Two LED drivers · Up to 19 General Purpose Inputs/Outputs (GPIOs)
8051 MCU Debug Features · 2-wire 8051 MCU Joint Test Action Group (JTAG) debug/program · CPU registers to write Flash for software downloading · Debug features supported Run/Stop control Single Step mode

Datasheet

DS70005403B-page 2

Software breakpoint Debug program Hardware breakpoint Program trace Access to ACC
Operating Condition · Operating voltage: 3.2V to 4.2V · Operating temperature: -40ºC to +85ºC
Applications · Portable speakers · Multiple speakers · Headphones · Bluetooth audio transmitter

IS2083

Datasheet

DS70005403B-page 3

IS2083
Table of Contents
Introduction.....................................................................................................................................................1
Features......................................................................................................................................................... 1
1. Quick References....................................................................................................................................6 1.1. Reference Documentation............................................................................................................6 1.2. Acronyms/Abbreviations...............................................................................................................6
2. Device Overview..................................................................................................................................... 9 2.1. IS2083BM Device Ball Diagram................................................................................................. 10 2.2. IS2083BM Device Ball Description.............................................................................................11
3. Audio Subsystem.................................................................................................................................. 17 3.1. Digital Signal Processor............................................................................................................. 18 3.2. Codec......................................................................................................................................... 19 3.3. Auxiliary Port.............................................................................................................................. 27 3.4. Microphone Inputs......................................................................................................................27 3.5. Analog Speaker Output.............................................................................................................. 28
4. Bluetooth Transceiver........................................................................................................................... 29 4.1. Transmitter................................................................................................................................. 29 4.2. Receiver..................................................................................................................................... 29 4.3. Synthesizer.................................................................................................................................30 4.4. Modulator-Demodulator..............................................................................................................30 4.5. Adaptive Frequency Hopping..................................................................................................... 30
5. Microcontroller.......................................................................................................................................31 5.1. Memory...................................................................................................................................... 32 5.2. Clock.......................................................................................................................................... 32
6. Power Management Unit.......................................................................................................................34 6.1. Device Operation........................................................................................................................34 6.2. Power Supply............................................................................................................................. 34 6.3. Adapter Input..............................................................................................................................34 6.4. Buck1 (BK1) Switching Regulator.............................................................................................. 35 6.5. Buck2 (BK2) Switching Regulator.............................................................................................. 35 6.6. Low-Droput Regulator................................................................................................................ 35 6.7. Battery Charging........................................................................................................................ 35 6.8. SAR ADC................................................................................................................................... 36 6.9. LED Driver..................................................................................................................................38
7. Application Information..........................................................................................................................39 7.1. Power On/Off Sequence............................................................................................................ 39 7.2. Reset.......................................................................................................................................... 40 7.3. Programming and Debugging.................................................................................................... 41 7.4. General Purpose I/O Pins.......................................................................................................... 45 7.5. I2S Mode Application..................................................................................................................45 7.6. Host MCU Interface....................................................................................................................46

Datasheet

DS70005403B-page 4

IS2083
8. Electrical Specifications........................................................................................................................ 48 8.1. Timing Specifications..................................................................................................................54
9. Package Information............................................................................................................................. 57 10. Ordering Information............................................................................................................................. 61 11. Document Revision History...................................................................................................................62 The Microchip Website.................................................................................................................................63 Product Change Notification Service............................................................................................................63 Customer Support........................................................................................................................................ 63 Microchip Devices Code Protection Feature................................................................................................ 63 Legal Notice................................................................................................................................................. 63 Trademarks.................................................................................................................................................. 64 Quality Management System....................................................................................................................... 64 Worldwide Sales and Service.......................................................................................................................65

Datasheet

DS70005403B-page 5

IS2083
Quick References

1. Quick References

1.1 Reference Documentation
For further study, refer to the following: · BM83 Bluetooth® Stereo Audio Module Data Sheet (DS70005402) · BM83 Bluetooth® Audio Development Board User's Guide (DS50002902) · IS2083 SDK User Guide (DS50002894) · BM83 Host MCU Firmware Development Guide (DS50002896) · IS2083 Bluetooth® Audio Application Design Guide (DS00003118) · IS2083 SDK Debugger User's Guide (DS50002892) · IS2083 Reference Design Application Note · Serial Quad Interface (SQI) Family Reference Manual (DS60001244)
Note: 1. For a complete list of development support tools and documents, visit: http://www.microchip.com/BM83 https://www.microchip.com/IS2083 2. Contact your local sales representative for more information about the Software Development Kit (SDK).

1.2

Acronyms/Abbreviations
Table 1-1.Acronyms/Abbreviations

Acronyms/Abbreviations A2DP AAC ADC AEC AFH ANCS API AVRCP AW BDR BER BLE BOM BPF BR CVSD DAC DFU DIS DLE

Description Advanced Audio Distribution Profile Advanced Audio Codec Analog-to-Digital Converter Acoustic Echo Cancellation Adaptive Frequency Hopping Apple Notification Center Service Application Programming Interfaces Audio/Video Remote Control Profile Audio Widening Basic Data Rate Bit Error Rate Bluetooth Low Energy Bill of Materials Band Pass Filter Basic Rate Continuous Variable Slope Delta Digital-to-Analog Converter Device Firmware Upgrade Device Information Service Data Length Extension

Datasheet

DS70005403B-page 6

...........continued Acronyms/Abbreviations DPSK DQPSK DR DSP DT EDR EMC EVB FET GAP GATT GFSK GPIO GUI HFP HPF HSP HW I2C I2S IC ICSP IDE IF IPE JTAG LDO LED LNA LPA LSB MAC MB DRC MCLK MCU MEMS MFB Modem MPA mSBC

Description Differential Phase Shift Keying Differential Quadrature Phase Shift Keying Receive Data Digital Signal Processor Transmit Data Enhanced Data Rate Electromagnetic Compatibility Evaluation Board Field Effect Transistor General Access Profile General Attribute Profile Gaussian Frequency Shift Keying General Purpose Input Output Graphical User Interface Hands-free Profile High Pass Filter Headset Profile Hardware Inter-Integrated Circuit Inter-IC Sound Integrated Circuit In-Circuit Serial Programming Integrated Development Environment Intermediate Frequency Integrated Programming Environment Joint Test Action Group Low-Dropout Light Emitting Diode Low-Noise Amplifier Linear Power Amplifier Least Significant Bit Medium Access Control Multiband Dynamic Range Compression Master Clock Microcontroller Micro-Electro-Mechanical Systems Multi-function Button Modulator-demodulator Medium Power Amplifier Modified Sub-band Coding

Datasheet

IS2083
Quick References
DS70005403B-page 7

...........continued Acronyms/Abbreviations MSPK NR OTA PBAP PCB PCM PDM PIM PLC PMU POR PWM RF RFS RoHS RSSI RX SAR SBC SCO SDK SIG SNR SoC SPP SW TX UART UI USB VB VCO WDT

Description Multi-speaker Noise Reduction Over-the-Air Phone Book Access Profile Printed Circuit Board Pulse Code Modulation Pulse Density Modulation Plug-in Module Packet Loss Concealment Power Management Unit Power-on Reset Pulse Width Modulation Radio Frequency Receive Frame Sync Restriction of Hazardous Substances Received Signal Strength Indicator Receiver Successive Approximation Register Sub-band Coding Synchronous Connection-oriented Software Development Kit Special Interest Group Signal-to-Noise Ratio System-on-Chip Serial Port Profile Software Transmitter Universal Asynchronous Receiver-Transmitter User Interface Universal Serial Bus Virtual Bass Enhancement Voltage-controlled Oscillator Watchdog Timer

IS2083
Quick References

Datasheet

DS70005403B-page 8

IS2083
Device Overview

2. Device Overview
The IS2083BM uses a single-cycle 8-bit 8051 MCU core connected to the system components via an MCU system bus. The MCU system bus provides interface memory map address decode for the Read Only Memory (ROM), Static Random Access Memory (SRAM), and peripherals.
IS2083BM contains the following major blocks:
· Bluetooth Link Controller (BTLC) Bluetooth clock, task scheduler, and Bluetooth hopping · Bluetooth modulator-demodulator (modem) TX/RX baseband, and RF · DSP audio subsystem DSP with audio codec · Program ROM Memory · Bluetooth DMA Common Memory Access · Power Management Unit (PMU) · Clock/Reset Low power logic
Figure 2-1.IS2083BM SoC Architecture

Debug Host

OCI Debug

Interrupt Controller
8-bit 8051 CPU Core

Patch MMU Logic

Program ROM
Patch RAM

CPU Subsystem

WDT

I2C

PWM GPIO

CPU Program/Data Bus

To Memories SQI

Hopping Sequence Controller
RF Controller

Bluetooth Clock Timer

Task Controller

Baseband
Bluetooth Baseband Core

CLDO RFLDO

Bluetooth 5.0 Dual Mode Radio

288 MHz PLL

XTAL

ULPC BG

TX path +
TX modem
RX path +
RX modem

CLKGEN

16 MHz 32 kHz 0-48 MHz 0-96 MHz

Common Memory

Controller Memory

Mailbox IO Bus
DSP Subsystem
DSP Core

DMA

SPORT0

Program RAM Coeff. RAM

Data RAM
Patch RAM

IO Bus

Audio Subsystem

Stereo Audio Codec

UART

USB

The IS2083BM device variants are: · IS2083BM variant supports analog output from the internal DAC · IS2083BM-2L2 variant supports LDAC and does not support analog output
The following table provides the features of IS2083BM SoC variants.

2 MB Flash
External Codec
MIC SPK RS-232 USB

Datasheet

DS70005403B-page 9

Table 2-1.IS2083BM Features

Features Application

IS2083BM
· Headset/Speaker · Bluetooth Audio Transmitter

Memory Stereo/Concert mode Package Pin/Ball count Dimensions Audio DAC output DAC (single-ended) SNR DAC (cap-less) SNR

Flash Yes BGA 82 5.5 mm x 5.5 mm 2 channel 95 dB 95 dB

ADC SNR at 1.8V I2S audio input I2S digital output

88 dB Yes Yes

MCLK output

Yes

Analog output

Yes

Analog Line-In

Yes

Analog microphone

2 channel

Digital microphone

2 channel

External audio amplifier interface

Yes

UART with hardware flow control

USB (Full-speed USB 1.1 interface and Yes battery charging)

I2C

PWM

1 channel

LED driver

Battery charger (350 mA maximum)

Yes

ADC for battery voltage and

Yes

temperature monitoring

GPIO

Up to 19

Multitone

Yes

Integrated MPA and LPA

Yes

IS2083
Device Overview
IS2083BM-2L2 Headset / Speaker
Flash Yes BGA 82 5.5 mm x 5.5 mm -- -- -- 88 dB Yes Yes Yes -- Yes 2 channel 2 channel Yes 1 Yes
1 1 channel 2 Yes Yes
Up to 19 Yes Yes

2.1 IS2083BM Device Ball Diagram
The following figure illustrates the ball diagram of the IS2083BM and IS2083BM-2L2.

Datasheet

DS70005403B-page 10

Figure 2-2. IS2083BM and IS2083BM-2L2 Ball Diagram

IS2083
Device Overview

A1 MIC_N2

A2 AOHPL

A3 AOHPM

A4 VDDA_CODEC

A5 AOHPR

A6 PA1OP

A7 GND

A10

RTX

VCC_BTPA

VCC_RF

B1 MIC_P2

B2 SCLK1

B3 RFS1

B4 VCOM

MIC_N1

DT1

C3 DR1

D1 MIC_P1

D2 MCLK1

D3 VDD_IO

E1 MICBIAS

E2 DMIC_CLK

E3 DMIC1_L

ADAP_IN

DMIC1_R

AIR

BAT_IN

P3_2

AIL

H1 SARVDD

H2 P0_6

H3 P2_6

J1 SYS_POWER

J2
P8_6/ UART_RXD

K1 BK1_VDDC

K2 BK1_LX1

J3 P8_5/ UART_TXD
K3 BK1_VOUT

J4 SK1
K4 MFB

B5
P1_3/ TCK_CPU/
SDA

B6 P1_2/ TDI_CPU/ SCL
C6 NC

B7 VCC_PA1

B8 P0_1
C8 VDD_IO
D8 RST_N

B9 P2_3

B10 XO_P

C9 P1_6/ PWM1
D9 P0_5

C10 XO_N
D10 ULPC_VSUS

E5 GND
F5 GND

E6 P0_7
F6 GND

H5 VDD_CORE

E8 P0_2

E9 P2_7

E10 VBG

F8
P0_0/ UART_TX_IND

F9 P0_3

G8
USB_1V2/ VDD_CORE

G9 P3_5

H8
AVDD_USB/ VDD_IO_10

H9
P3_7/ UART_CTS

F10 RFLDO_O
G10 PMIC_IN
H10 CLDO_O/ VDD_PLL

J5 SK2
K5 LDO31_VO

J6 VDD_CORE
K6 LDO31_VIN

J7 P3_4/ UART_RTS
K7 BK2_VOUT

J8 LED1
K8 BK2_LX

J9 LED2

J10 USB_DP

K9 BK2_VDD

K10 USB_DM

Note: The IS2083BM-2L2 does not support an analog output from the internal DAC. The AOHPR, AOHPM and AOHPL are affected pins.

2.2 IS2083BM Device Ball Description
Table 2-2.IS2083BM and IS2083BM-2L2 Ball Description

IS2083BM Ball IS2083BM-2L2 Ball Ball Name

Number

Ball Type

Description

MIC_N2
AOHPL(1) AOHPM(1)

MIC2 mono differential analog negative

input

Left channel, analog headphone output

Headphone common mode output/sense

input

Datasheet

DS70005403B-page 11

IS2083
Device Overview

...........continued

IS2083BM Ball IS2083BM-2L2 Ball Ball Name

Number

VDDA_CODEC

Ball Type
P

AOHPR(1)

PA1OP

I/O

GND

RTX

I/O

A10

VCC_BTPA

VCC_RF

MIC_P2

SCLK1

I/O

RFS1

I/O

VCOM

P1_3/

I/O

TCK_CPU/ SDA

P1_2/ TDI_CPU/ I/O SCL

VCC_PA1

P0_1

I/O

B10

P2_3

I/O

XO_P

MIC_N1

DT1

DR1

I/O

Description
· Analog audio codec power supply (1.8V)
· Connect to BK2_VOUT pin
Right channel, analog headphone output RF output pin for MPA Ground reference
· RF path (transmit/receive) · TX LPA output multiplexed with RX
LNA input
· Power supply for RF power amplifier · Connect to BK1_VOUT
· RF power input (1.28V) for both synthesizer and TX/RX block
· Connect to RFLDO_O
MIC2 mono differential analog positive input I2S interface for bit clock I2S interface for DAC digital left/right clock
· Internal biasing voltage for codec · Connect a 4.7 F capacitor to ground
· General purpose I/O port P1_3 · CPU 2-wire debug clock · I2C SDA
· General purpose I/O port P1_2 · CPU 2-wire debug data · I2C SCL
· Power supply for MPA · Connect to BK1_VOUT
· General purpose I/O port P0_1 · By default, this is configured as forward
button (user configurable button)
General purpose I/O port P2_3 16 MHz crystal positive input MIC1 mono differential analog negative input I2S interface: ADC digital left/right data I2S interface: DAC digital left/right data Not connected

Datasheet

DS70005403B-page 12

...........continued

IS2083BM Ball IS2083BM-2L2 Ball Ball Name

Number

VDD_IO

C10

P1_6/ PWM1
XO_N MIC_P1 MCLK1
VDD_IO

RST_N P0_5

D10

ULPC_VSUS

E10

MICBIAS DMIC_CLK DMIC1_L GND P0_7 P0_2
P2_7
VBG
ADAP_IN DMIC1_R AIR

IS2083
Device Overview

Ball Type P
I/O I I O P
I I/O
P
P O I P I/O I/O
I/O
P
P I I

Description
· I/O power supply input · Connect to ground through a 1 F
(X5R/X7R) capacitor
· General purpose I/O port P1_6 · PWM1 output
16 MHz crystal negative input
MIC1 mono differential analog positive input
Master clock output provided to an external I2S device/codec
· I/O power supply input · Connect to LDO31_VO and ground
through a 1 F (X5R/X7R) capacitor
System Reset pin (active-low)
· General purpose I/O port P0_5 · By default, this is configured as volume
down button (user configurable button)
· 1.2V ULPC output power · Maximum loading 1 mA · Connect to ground through a 1 F
capacitor
Electric microphone biasing voltage
Digital microphone clock
Digital microphone left channel
Ground reference
General purpose I/O port P0_7
· General purpose I/O port P0_2 · By default, this is configured as play/
pause button (user configurable button)
· General purpose I/O port P2_7 · By default, this is configured as volume
up button (user configurable button)
· Bandgap output reference for decoupling interference
· Connect to ground through a 1 F capacitor
5V power adapter input to charge the battery in the battery powered applications
Digital microphone right channel
Right channel, single-ended analog input

Datasheet

DS70005403B-page 13

IS2083
Device Overview

...........continued

IS2083BM Ball IS2083BM-2L2 Ball Ball Name

Number

GND
GND
P0_0/ UART_TX_IND

Ball Type
P P I/O

F10

G10

P0_3

I/O

RFLDO_O

BAT_IN

P3_2

I/O

AIL

USB_1V2/

VDD_CORE

P3_5

I/O

PMIC_IN

SARVDD

P0_6

I/0

P2_6

I/O

VDD_CORE

AVDD_USB/

VDD_IO_10

Description
Ground reference
Ground reference
· General purpose I/O port P0_0 · By default, this is configured as an
external codec reset (Embedded mode) · UART_TX_IND (active-high); used to wake-up host MCU (Host mode)
· General purpose I/O port P0_3 · By default, this is configured as reverse
button (user configurable button)
· 1.28V RF LDO output for internal use only
· Connect to ground through a 1 F capacitor
· Input power supply · Source can either be a battery or any
other power rail on the host board
· General purpose I/O port P3_2 · By default, this is configured as
AUX_IN DETECT
Left channel, single-ended analog input
· 1.2V core power input · Connect to ground through a 1 F
(X5R/X7R) capacitor
General purpose I/O port P3_5
· 1.8V power input for internal blocks · Connect to BK1_VOUT
· SAR ADC 1.8V input · Connect to BK2_O pin
General purpose I/O port P0_6
General purpose I/O port P2_6
· Core 1.2V power input · Connect to CLDO_O pin
· USB power input · Connect to LDO31_VO pin · Do not connect if USB functionality is
not required

Datasheet

DS70005403B-page 14

IS2083
Device Overview

...........continued

IS2083BM Ball IS2083BM-2L2 Ball Ball Name

Number

P3_7/ UART_CTS

H10

CLDO_O/ VDD_PLL

SYS_POWER

J10

P8_6/ UART_RXD P8_5/ UART_TXD SK1 SK2 VDD_CORE
P3_4/ UART_RTS
LED1 LED2 USB_DP BK1_VDDC
BK1_LX1 BK1_VOUT
MFB LDO31_VO
LDO31_VIN

Ball Type I/O
P
P
I/O I/O I I P
I/O
O O I/O P P P
I P P

Description
· General purpose I/O port P3_7 (this pin should not be pulled low during startup)
· UART CTS
· 1.2V core LDO output for internal use only
· Connect to ground through a 1 F capacitor
· System power output derived from the ADAP_IN or BAT_IN input
· Do not connect to any other devices · Only for internal use
· General purpose I/O port P8_6 · UART data input
· General purpose I/O port P8_5 · UART data output
ADC channel 1
ADC channel 2
· 1.2V core input power supply · Connect to ground through a 1 F
(X5R/X7R) capacitor
· General purpose I/O port P3_4 · System configuration pin (Application
mode or Test mode) · UART RTS
LED driver 1
LED driver 2
Differential data-plus USB
· 1.5V buck VDD power input · Connect to SYS_POWER pin
1.5V buck regulator feedback path
· 1.5V buck regulator output · Do not connect to other devices · Only for internal use
Multifunction push button and Power On key
· 3V LDO output for VDD_IO power · Do not calibrate
· LDO input · Connect to SYS_POWER

Datasheet

DS70005403B-page 15

IS2083
Device Overview

...........continued

IS2083BM Ball IS2083BM-2L2 Ball Ball Name

Number

BK2_VOUT

K10

BK2_LX BK2_VDD
USB_DM

Ball Type P
P P
I/O

Description
· 1.8V buck regulator output · Do not connect to other devices · Only for internal use 1.8V buck regulator feedback path · 1.8V buck VDD power input · Connect to SYS_POWER pin Differential data-minus USB

Note: 1. The AOHPR, AOHPM, and AOHPL pins are not available in the IS2083BM-2L2 variant as it does not support an analog output from the internal DAC. 2. The conventions used in the preceding table are indicated as follows: I = Input pin O = Output pin I/O = Input/Output pin P = Power pin

Datasheet

DS70005403B-page 16

IS2083
Audio Subsystem

3. Audio Subsystem
The input and output audio have different stages and each stage can be programmed to vary the gain response characteristics. For microphones, both single-ended inputs and differential inputs are supported. To maintain a highquality signal, a stable bias voltage source to the condenser microphone's FET is provided. The DC blocking capacitors can be used at both positive and negative sides of the input. Internally, this analog signal is converted to 16-bit, 8/16 kHz linear PCM data.
The following figure shows the audio subsystem.
Figure 3-1.Audio Subsystem

RSTGEN

reset

Analog Audio Codec

CLKGEN

clk

CPU

registers

DSP

DSP registers

DT0

DAC Controller

Audio DAC

AOHPL AOHPM AOHPR

ADC_SDATA ADC_LRO
DMIC_CLK DMIC1_L DMIC1_R

ADC Controller
digmic_mclk_out digmic1_l_data_in digmic1_r_data_in

Audio ADC
VREF

AIL AIR MICN1 MICP1 MICN2 MICP2
MICBIAS

Note: The AOHPL, AOHPM, AOHPR pins are not available in the IS2083BM-2L2 variant.

Datasheet

DS70005403B-page 17

IS2083
Audio Subsystem

3.1 Digital Signal Processor
A Digital Signal Processor (DSP) is used to perform speech and audio processing. The advanced speech features, such as AES and NR are inbuilt. To reduce nonlinear distortion and to help echo cancellation, an outgoing signal level to the speaker is monitored and adjusted to avoid saturation of speaker output or microphone input. In addition, adaptive filtering is applied to track the echo path impulse in response to provide echo free and full-duplex user experience.
The embedded noise reduction algorithm helps to extract clean speech signals from the noisy inputs captured by the microphones and improves mutual understanding in communication. The advanced audio features, such as multiband dynamic range control, parametric multiband equalizer, audio widening and virtual bass are inbuilt. The audio effect algorithms improve the user's audio listening experience in terms of better-quality audio after audio signal processing. Note: DSP parameters can be configured using the Config Tool.
The following figures illustrate the processing flow of speaker phone applications for speech and audio signal processing.
Figure 3-2.Speech Signal Processing

Antenna MCU

CVSD/A-Law/ -Law/MSBC
Decoders

IS2083BM

DSP
Far-end NR

Equaliser

HPF

SRC

CVSD/A-Law/ -Law/MSBC

Equaliser

Encoders

Additive Background Noise

Near-end NR/AES

AEC

HPF

Digital MIC Gain

SRC

DAC

Audio Amplifier Speaker

ADC Microphones

Figure 3-3.Audio Signal Processing

IS2083BM

Antenna

Line-In

MCU

SBC/AAC Decoders
LDAC Decoders

Audio Effect

Equaliser

I2S Output

DSP SRC

ADC
DAC (speaker
gain)

External Audio Source
Audio Amplifier
Speaker

Note: LDAC is supported only in the IS2083BM-2L2 device.
The DSP core consists of three computational units (ALU, MAC, and Barrel Shifter), two data address generators, PMD-DMD bus exchanger, program sequencer, bi-directional serial ports (SPORT), DMA controller, interrupt controller, programmable I/O, on-chip program, and on-chip data memory.
The DSP memory subsystem defines the address ranges for the following addressable memory regions:

Datasheet

DS70005403B-page 18

IS2083
Audio Subsystem
· Program space 96 KB of Program RAM 12 KB of Patch RAM 64 KB of Coefficient RAM
· Data space 96 KB of Data RAM
· I/O Space Memory-mapped registers
The DSP core implements a modified Harvard architecture in which data memory stores data and program memory stores both instructions and data (coefficients).

3.2
3.2.1

Codec
The built-in codec has a high signal-to-noise ratio (SNR) performance and it consists of an Analog-to-Digital Converter (ADC), a Digital-to-Analog Converter (DAC), and an additional analog circuitry.
· Interfaces Two mono differential or single-ended microphone inputs One stereo single-ended line input One stereo single-ended line output One stereo single-ended earphone output (capacitor-less connection)
· Built-in circuit Microphone bias (MICBIAS) Reference and biasing circuitry
· Optional digital High Pass Filter (HPF) on ADC path · Silence detection
Typically, used for Line-In inputs. For some applications, the Line-In input has high priority. After the Line-In input source is plugged in and before streaming out an audio, the Line-In noise cannot be ignored. So, the silence detection feature is used to mute this background noise.
· Anti-pop function to reduce audible glitches Pop reduction system Soft Mute mode Typically used when the codec analog gain is changed suddenly (for example, turning OFF the power or switching the volume dial very quickly), in which case the RCL circuits in the external audio amplifier would cause "pop" noise. The anti-pop function is used to lower or increase the gain in many small steps, 1- or 2dB change for each step, rather than a single large gain decrease or increase.
· ADC supports 8 kHz, 16 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, and 96 kHz sampling rates.

Audio Performance This section provides characteristics of the internal codec in the IS2083BM device.
Table 3-1.Test Conditions

Parameter (Condition) FS Analog gain setting for ADC Digital gain setting for ADC Analog gain setting for DAC

Value 48 kHz 0 dB 0 dB -3 dB

Digital gain setting for DAC

0 dB

Datasheet

DS70005403B-page 19

Figure 3-4.ADC Signal Quality THD

IS2083
Audio Subsystem

Note: Analog Gain = 0 dB, Digital Gain = 0 dB, Sweep Vin= -60 dbV to 5 dbV@1 kHz. Figure 3-5.ADC Signal Quality THD+N

Note: Analog Gain = 0 dB, Digital Gain = 0 dB, Sweep Vin= -60 dbV to 5 dbV@1 kHz.

Datasheet

DS70005403B-page 20

Figure 3-6.ADC Dynamic Range

IS2083
Audio Subsystem

Note: Analog Gain = 0 dB, Digital Gain = 0 dB, Sweep Vin= -100 dbV to 5 dbV@1 kHz. Figure 3-7.ADC Frequency Response

Note: Analog Gain = 0 dB, Digital Gain = 0 dB Sweep Fin= 20 Hz to 20 kHz @ -3 dbV.

Datasheet

DS70005403B-page 21

Figure 3-8.ADC Crosstalk Line-In

IS2083
Audio Subsystem

Note: Analog Gain = 0 dB, Digital Gain = 0 dB Sweep Fin= 20 Hz to 20 kHz @ -3 dbV. Figure 3-9.ADC Crosstalk Mic-in

Note: Analog Gain = 0 dB, Digital Gain = 0 dB Sweep Fin= 20 Hz to 20 kHz @ -3 dbV.

Datasheet

DS70005403B-page 22

Figure 3-10.DAC Signal Quality THD (Single-ended)

IS2083
Audio Subsystem

Note: Analog gain = -3 dB, digital gain = 0 dB, sweep Vin = -60 dBFS to 0 dBFS@ 1 kHz. Figure 3-11.DAC Signal Quality THD (Capless)
Note: Analog gain = -3 dB, digital gain = 0 dB, sweep Vin = -60 dBFS to 0 dBFS @1 kHz.

Datasheet

DS70005403B-page 23

Figure 3-12.DAC Signal Quality - THD+N (Single-ended)

IS2083
Audio Subsystem

Note: Analog gain = -3 dB, digital gain = 0 dB, sweep Vin = -60 dBFS to 0 dbFS @1 kHz. Figure 3-13.DAC Signal Quality - THD+N (Capless)

Note: Analog gain = -3 dB, digital gain = 0 dB, sweep Vin = -60 dBFS to 0 dBFS @1 kHz.

Datasheet

DS70005403B-page 24

Figure 3-14.DAC Dynamic Range (Single-ended)

IS2083
Audio Subsystem

Note: Analog gain = 3 dB, digital gain = 0 dB, sweep Vin = -100 dBFS to 0 dBFS @1 kHz. Figure 3-15.DAC Dynamic Range (Capless)

Note: Analog gain = 3 dB, digital gain = 0 dB, sweep Vin = -100 dBFS to 0 dBFS @1 kHz.

Datasheet

DS70005403B-page 25

Figure 3-16.DAC Frequency Response (Single-ended)

IS2083
Audio Subsystem

Note: Analog gain = -3 dB, sweep fin = 20 Hz to 20 kHz @ -3 dBFS. Figure 3-17.DAC Frequency Response (Capless)

Note: Analog gain = -3 dB, sweep fin = 20 Hz to 20 kHz @ -3 dBFS.

Datasheet

DS70005403B-page 26

Figure 3-18.DAC Crosstalk (Single-ended)

IS2083
Audio Subsystem

Note: Analog gain = -3 dB, sweep fin = 20 Hz to 20 kHz @ -3 dBFS. Figure 3-19.DAC Crosstalk (Capless)

Note: Analog gain = -3 dB, sweep fin = 20 Hz to 20 kHz @ -3 dBFS.
3.3 Auxiliary Port
The IS2083BM SoC supports one analog (Line-In, also called as Aux-In) signal from the external audio source. The analog (Line-In) signal can be processed by the DSP to generate different sound effects (multiband dynamic range compression and audio widening), which can be configured by using the Config Tool.
3.4 Microphone Inputs
The IS2083BM SoC supports: · One digital microphone with one (mono) or two channels (stereo L and R) · Two analog microphones (left and right)
Note: Do not use analog and digital microphones simultaneously.

Datasheet

DS70005403B-page 27

IS2083
Audio Subsystem
The DIGMIC interfaces should only be used for PDM digital microphones (typically, MEMS microphones) up to 4 MHz of clock frequency. I2S-based digital microphones should use the external I2S port.
3.5 Analog Speaker Output
The IS2083BM SoC supports the following speaker output modes: · Capless mode - Used for headphone applications in which capacitor less (capless) output connection helps to save the Bill of Material (BoM) cost by avoiding a large DC blocking capacitor. The following figure illustrates the Capless mode analog speaker output.
Figure 3-20.Capless Mode Analog Speaker Output
IS2083BM
AOHPR
AOHPM

AOHPL
16/32 Ohm Speaker
· Single-Ended mode - Used for driving an external audio amplifier where a DC blocking capacitor is required. The following figure illustrates the Single-Ended mode analog speaker output.
Figure 3-21.Single-ended Mode Analog Speaker Output

Audio Amplifier

IS2083BM
AOHPR AOHPL

Datasheet

DS70005403B-page 28

IS2083
Bluetooth Transceiver
4. Bluetooth Transceiver
The IS2083BM SoC is designed and optimized for Bluetooth 2.4 GHz systems. It contains a complete radio frequency transmitter (TX)/receiver (RX) section. An internal synthesizer generates a stable clock for synchronizing with another device.
4.1 Transmitter
The IS2083BM has Lower Power Amplifier (LPA) and Medium Power Amplifier (MPA). The MPA supports up to +11 dBm power level for Bluetooth Class1 configuration and LPA supports up to about +1 dBm power level for Bluetooth Class2 configuration. The MPA output is connected to the PA1OP pin of the SoC. The LPA output and LNA input are multiplexed and connected to the RTX pin of the device. The IS2083BM supports shared port configuration, in which the MPA and LPA pins are wired together as shown in the following figure. In shared port configuration, the external series capacitors on RTX, PA1OP pins and PI filter circuit implements a low BoM cost solution to combine the MPA and LPA/LNA signals. Typical value of these components are C1 = 2 pF, C2 = 3 pF, C3 = 1.3 pF/1.4 pF, L1 = 2.7 nH/2.8 nH, C4 = 3 pF (use the BM83 RF schematics as it is to achieve the desired RF performance). Note: For more details, refer to the IS2083 Reference Design Application Note. Figure 4-1.Shared Port Configuration

4.2 Receiver
The Low-Noise Amplifier (LNA) operates in a TR-combined mode for a single port application. It saves a pin on the package without having an external TX/RX switch.
The ADC is used to sample the analog input signal and convert it into a digital signal for demodulator analysis. A channel filter is integrated into the receiver channel before the ADC to reduce the external component count and increase the anti-interference capability.
The image rejection filter is used to reject the image frequency for the low-IF architecture, and it also intended to reduce the external Band Pass Filter (BPF) component for a super heterodyne architecture.
The Received Signal Strength Indicator (RSSI) signal feedback to the processor is used to control the RF output power to make a good trade-off for effective distance and current consumption.

Datasheet

DS70005403B-page 29

IS2083
Bluetooth Transceiver
4.3 Synthesizer
A synthesizer generates a clock for radio transceiver operation. There is a Voltage Controlled Oscillator (VCO) inside with a tunable internal LC tank that can reduce components variation. A crystal oscillator with an internal digital trimming circuit provides a stable clock for the synthesizer.
4.4 Modulator-Demodulator
For Bluetooth 1.2 specification and below, 1 Mbps is the standard data rate based on the Gaussian Frequency Shift Keying (GFSK) modulation scheme. This basic rate modulator-demodulator (Modem) meets Basic Data Rate (BDR) requirements of Bluetooth 2.0 with Enhanced Data Rate (EDR) specifications. For Bluetooth 2.0 and above specifications, EDR is introduced to provide the data rates of 1/2/3 Mbps. For baseband, both BDR and EDR utilize the same 1 MHz symbol rate and 1.6 kHz slot rate. For BDR, symbol 1 represents 1-bit. However, each symbol in the payload part of the EDR packet represents 2 or 3 bits. This is achieved by using two different modulations, /4 DQPSK and 8 DPSK.
4.5 Adaptive Frequency Hopping
The IS2083BM SoC has an Adaptive Frequency Hopping (AFH) function to avoid RF interference. It has an algorithm to check the nearby interference and to choose a clear channel for transceiver Bluetooth signal.

Datasheet

DS70005403B-page 30

IS2083
Microcontroller
5. Microcontroller
A 8051 microcontroller is built into the SoC to execute the Bluetooth protocols. It operates from 16 MHz to higher frequencies where the firmware can dynamically adjust the trade-off between the computing power and the power consumption. Figure 5-1.IS2083BM SoC Block Diagram
Antenna

External DSP

I2S (digital signal) and MCLK

Speaker 1 Speaker 2

ANAMIC1 ANAMIC2 DIGMIC1
AUX_In (Analog signal)

Audio Codec Digital Core 2-Channel
DAC
2-Channel ADC
Flash Memory 16 Mbit
USB 1.1 UART
I2C

32-bit DSP Core

Bluetooth Classic and Low Energy
Transceiver RF
RF Controller
MAC Modem

IS2083BM
MCU Core JTAG Debug 512 B Internal 832 KB Prog ROM 512 KB Prog/ Patch/Data RAM
PWM

PMU Battery Charger
Battery Monitor
Power Switch 1.5V
Buck Regulator 1.8V
Buck Regulator 3.1V LDO
LED Drivers
IO Ports

16 MHz Crystal Battery
LED

The MCU core contains Bluetooth stack and profiles, which are hard-coded into ROM to minimize power consumption for the firmware execution and to save the external Flash cost. This core is responsible for the following system functions:
· Boot-up · On-the-Air Device Firmware Upgrade (OTA DFU) · Executing the Bluetooth stack and Bluetooth profiles · Sending the packets to DSP core for audio processing · Loading audio codec registers with values read the Flash · Managing low-power modes · Executing UART commands

Datasheet

DS70005403B-page 31

IS2083
Microcontroller
· Device programming · GPIO button control · PWM control · LED control · Bluetooth role swap for multi-speakers · Adjusting the Bluetooth clock · External audio codec control/configuration, if needed · USB battery charge detection and configuration of the PMU battery charger · Configuration of PMU power regulation · Changing the audio subsystem clocks On-the-Fly (OTF) for different audio sampling rates
5.1 Memory
A synchronous single port RAM interface is used to fulfill the ROM and RAM requirements of the processor. The register bank, dedicated single port memory and Flash memory are connected to the processor bus. The processor coordinates with all link control procedures and the data movement happens using a set of pointer registers.
5.2 Clock
The IS2083BM SoC is composed of an integrated crystal oscillator that uses a 16 MHz ±10 ppm external crystal and two specified loading capacitors to provide a high-quality system reference timer source. This feature is typically used to remove the initial tolerance frequency errors, which are associated with the crystal and its equivalent loading capacitance in the mass production. Frequency trim is achieved by adjusting the crystal loading capacitance through the on-chip trim capacitors (Ctrim). The crystal trimming can be done using manufacturing tools provided by Microchip. The following figure illustrates the crystal oscillator connection of the IS2083BM SoC with two capacitors. Figure 5-2.Crystal Oscillator in the IS2083BM
IS2083BM

XO_N

XO_P

CL1

CL2

The clock module controls switching and synchronization of clock sources. Clock sources include: · System Phase-locked Loop (PLL) · Primary oscillator · External clock oscillator · Ultra Low-power internal RC oscillator (UPLC) with nominal frequency as 32 kHz.

Datasheet

DS70005403B-page 32

IS2083
Microcontroller
The clock module provides gated clock output for 8051 and its peripheral modules, gated clock output for Bluetooth modules as well as DSP audio subsystem. The system enters low power mode by switching OFF clocks driven from the PLL and external oscillator. Only ULPC is operated to maintain Bluetooth timing.

Datasheet

DS70005403B-page 33

IS2083
Power Management Unit

6. Power Management Unit
The IS2083BM SoC has an integrated Power Management Unit (PMU). The PMU includes buck switching regulator, LDO, battery charger, SAR ADC for voltage sensing, and LED drivers. The power switch is provided to switch between battery and adapter. It also provides current to the LED drivers.

6.1 Device Operation
The IS2083BM SoC is powered through the BAT_IN input pin. The external 5V power adapter can be connected to the ADAP_IN pin to charge the battery.
For normal operation, it is recommend to use the BAT_IN pin to power the IS2083BM SoC and ADAP_IN only for charging the battery. The following figure illustrates the connection from the BAT_IN pin to other voltage supply pins of the IS2083BM. The IS2083BM has two buck switching regulators:
· Buck1 DC/DC regulator provides 1.5V and is used to supply power to RF and baseband. · Buck2 DC/DC regulator provides 1.8V and is used to supply power to I/O pads and internal codec.
Figure 6-1.Power Tree Diagram

1.8V Buck
Switching BK_VDD Regulator
(Buck2)

BK_O BK_LX

(1.8V)

(3.2 to 4.2V) Li-Ion Battery
(4.5 to 5.5V)

BAT_IN ADAP_IN

Power Switch

SYS_PWR

5V Adapter

LDO31_VIN
3V LDO

VDDA/ VDDAO

(4.2 to 3.2V)

LDO31_VO (3.0 to 3.6V)

VDD_IO

BK_VDD

1.5V Buck Switching Regulator
(Buck1)

BK_O BK_LX

(1.5V)

PMIC_IN

(1.2V) CLDO_O

VDD_CORE

1.2V LDO
(1.28V) RFLDO_O

VCC_RF

SAR_VDD

6.2 Power Supply
Typically, the PWR (MFB) pin is connected to a mechanical button on the device. When pressed, it connects the BAT_IN pin to the power detection block of the PMU. The PMU keeps the VBAT_IN connected once the PWR pin is released.
6.3 Adapter Input
The adapter input (ADAP_IN) is used for charging the battery. If the total power consumed by IS2083BM SoC is less than 120 mA, ADAP_IN pin can also be used as power supply input. If the current to be driven is more than 120 mA, it is recommended to use the BAT_IN pin as the power supply input and the ADAP_IN pin can be left floating.

Datasheet

DS70005403B-page 34

IS2083
Power Management Unit

6.4 Buck1 (BK1) Switching Regulator
The IS2083BM includes a built-in programmable output voltage regulator which converts the battery voltage to 1.5V to supply the RF and baseband power supply. This converter has high conversion efficiency and fast transient response.
Note: Do not connect any other devices to buck1 regulator output pin (BK1_VOUT).

6.5 Buck2 (BK2) Switching Regulator
The IS2083BM includes a second build in programmable output voltage regulator which converts the battery voltage to 1.8V, to supply the PMU ADC and to optionally supply stereo audio codec and/or I/O's. This converter has a high conversion efficiency and a fast-transient response. Note: Do not connect any other devices to buck2 regulator output pin (BK2_VOUT).

6.6 Low-Droput Regulator
The built-in Low-Dropout (LDO) regulator is used to convert the battery or adapter power to 3.3V to supply the USB transceiver and to supply the I/O's.

6.7 Battery Charging
The IS2083BM SoC has built-in battery charger which is optimized for lithium-ion and lithium polymer batteries. The battery charger includes a current sensor for charging control, user programmable current regulator and high accuracy voltage regulator. The charging current parameters are configured by using the Config Tool. The maximum charging current is 350 mA. Whenever the adapter is plugged in, the charging circuit is activated.

Figure 6-2.Battery Charging Curve

Icharge VBatt

Stage Stage

I4 V4 1

Constant Current Mode

Stage 3

Stage 4

Constant Voltage Mode

Stop Charging
V5 = 0.1V drop

Recharge Mode

Stop Charging (back to re-charge if voltage drop > V5)

I3 V3 I5

I2 V2

Icomp

I1 V1

T1 T2

Time

6.7.1

Battery Charger Detection The IS2083BM USB transceiver includes built-in battery charger detection that is compatible with the following:
USB BC 1.2 Standard Downstream Port (SDP): This is the same port defined by the USB 2.0 spec and is the typical form found in desktop and laptop computers. The maximum load current is 2.5 mA when suspended, 100mA when connected and not suspended, and 500 mA (max) when connected and configured for higher power.
USB BC 1.2 Dedicated Charger Port (DCP): BC 1.2 describes power sources like wall warts and auto adapters that do not enumerate so that charging can occur with no digital communication at all. DCPs can supply up to 1.5A and are identified by a short between D+ to D-. This port does not support any data transfer, but is capable of supplying charge current beyond 1.5A.

Datasheet

DS70005403B-page 35

IS2083
Power Management Unit
Any device (such as the IS2083BM) that connects to any USB receptacle and uses that power to run itself or charge a battery, must know how much current is appropriate to draw. Attempting to draw 1A from a source capable of supplying only 500mA would not be good. An overloaded USB port will likely shut down or blow a fuse. Even with resettable protection, it will often not restart until the device is unplugged and reconnected. In ports with less rigorous protection, an overloaded port can cause the entire system to Reset. Once the USB transceiver determines the battery charger profile and port type (SDP, CDP, DCP), it interrupts the CPU, which then reads the battery charger profile and port type information out of the USB registers. It uses this information to program the PMU (via the 3-wire PMU interface) with the configuration corresponding to the battery charger profile and port type.
Figure 6-3.USB Battery Charger 1.2 DCP/SDP/CDP Signaling

6.8 SAR ADC
The IS2083BM SoC has a 10-bit Successive Approximation Register (SAR) ADC with ENOB (Effective Number of Bits) of 8-bits; used for battery voltage detection, adapter voltage detection, charger thermal protection, and ambient temperature detection. The input power of the SAR ADC is supplied by the 1.8V output of Buck2. The warning level can be programmed by using the Config Tool or the SDK.
The SK1 and SK2 are the ADC channel pins. The SK1 is used for charger thermal protection. The following figure illustrates the suggested circuit and thermistor, Murata NCP15WF104F. The charger thermal protection can avoid battery charge in a restricted temperature range. The upper and lower limits for temperature values can be configured by using the Config Tool.

Datasheet

DS70005403B-page 36

Figure 6-4.Ambient Detection Circuit

VDD_IO

SK1 C1
1 µF, 16V

R1 1M/1%
R2 86.6k/1%

IS2083
Power Management Unit

TR1 100k Thermistor: Murata NCP15WF104F
Note: The thermistor must be placed close to the battery in the user application for accurate temperature measurements and to enable the thermal shutdown feature. The following figures show SK1 and SK2 channel behavior. Figure 6-5.SK1 Channel

Datasheet

DS70005403B-page 37

Figure 6-6.SK2 Channel

IS2083
Power Management Unit

6.9 LED Driver
The IS2083BM has two LED drivers to control external LEDs. The LED drivers provide enough sink current (16-step control and 0.35 mA for each step) and the LED can be connected directly to the IS2083BM. The LED settings can be configured by using the Config Tool. The following figure illustrates the LED drivers in the IS2083BM. Figure 6-7.LED Driver
IS2083BM
SYS_PWR
LED1
LED2

Datasheet

DS70005403B-page 38

IS2083
Application Information

7. Application Information

7.1 Power On/Off Sequence
In Embedded mode, the BM83 module utilizes the MFB button to turn on and turn off the system. For Host mode, refer to 7.6 Host MCU Interface. The following figure illustrates the system behavior (Embedded mode) upon a MFB press event to turn on and turn off the system.
Figure 7-1.Timing Sequence of Power On/Off in Embedded Mode
BAT_IN

SYS_PWR

Turn On

Turn Off

MFB

VDD_IO RST_N

BK1 BK2 LDO31

The following figure illustrates the system behavior (Embedded mode) upon a MFB press event to turn on the system and then trigger a Reset event.
Figure 7-2.Timing Sequence of Power On and Reset Trigger in Embedded Mode

BAT_IN

SYS_PWR

Turn On

MFB

VDD_IO RST_N

Reset Trigger

BK1 BK2 LDO31

Datasheet

DS70005403B-page 39

IS2083
Application Information

7.2 Reset
The Reset logic generates proper sequence to the device during Reset events. The Reset sources include external Reset, power-up Reset, and Watchdog Timer (WDT). The IS2083 SoC provides a WDT to Reset the chip. In addition, it has an integrated Power-on Reset (POR) circuit that resets all circuits to a known Power On state. This action can also be driven by an external Reset signal, which is used to control the device externally by forcing it into a POR state. The following figure illustrates the system behavior upon a RST_N event. Note: The Reset (RST_N) is an active-low signal and can be utilized based on the application needs, otherwise, it can be left floating.
Figure 7-3.Timing Sequence of Reset Trigger
BAT_IN
SYS_PWR

MFB

VDD_IO

RST_N BK1

0 ms

200 ms

BK2

LDO31

Note: RST_N pin has an internal pull-up, thus, RST_N signal will transition to high again upon releasing the RST_N button. This is an expected behavior of RST_N signal.
Figure 7-4.Timing Sequence of Power Drop Protection

Power SYS_PWR

2.93V 2.7V

SYS_PWR

RST_N from Reset IC

IS2083 Reset

Reset IC
OUT VDD GND

MCU Reset
Timing sequence of power drop protection: · It is recommended to use the battery to provide the power supply at BAT_IN. · If an external power source or a power adapter is utilized to provide power to BAT_IN, it is recommended to use a voltage supervisor Integrated Circuit (IC). · The Reset IC output pin, RST_N, must be open drain type and threshold voltage as 2.93V. · The RST_N signal must be fully pulled low before SYS_PWR power drop to 2.7V.

Datasheet

DS70005403B-page 40

IS2083
Application Information

7.3 Programming and Debugging
The IS2083BM devices contain 2 MB of Flash memory which is interfaced using Serial Quad Interface (SQI). The below section defines the external SQI (Serial Quad Interface) Flash programming specification for the IS2083BM family of 8-bit microcontrollers to support external Flash programming. The following figure illustrates a typical programming setup which contains an external programmer tool and a target device (IS2083BM). The programmer tool is responsible for executing necessary programming steps and completing the operations.
Figure 7-5.Programming Setup

External Programmer

JTAG or
ICSPTM Interface

IS2083BM
SQI Interface
In-Package Serial Flash

7.3.1

Test Mode
The Test mode allows an external UART host to communicate with the device using Bluetooth vendor commands over the UART interface. The host can interface with the driver firmware on the device to perform TX/RX operations and to collect/report Bit Error Rate (BER) and other RF performance parameters. These values can then be used to accept/reject the device and/or calibrate the module.
Test mode is entered by pulling the PORT3_4 pin to low during start-up/Reset. The pin PORT3_4 can be used as GPIO pin, if the pin level is high during start-up/Reset. The boot code residing in the boot ROM is responsible for identifying this event, setting the CFGMODE [TEST_MODE] bit, and then performing a Reset of the device using the RST_N pin.
The following table provides the configurations required to set the Test mode or Application mode.
Table 7-1.Test Mode Configuration Settings

Pins

Status

Mode

P3_4

Low Floating

Test mode Application mode

To exit from Test mode (regardless of how it is entered), firmware can clear the Test mode bit, and perform a device Reset, either by asserting RST_N pin or by a Software Reset.

7.3.2 7.3.2.1

Flash Memory and SQI Controller
This section covers various aspects of SQI controller and Flash memory, which are essential for programming.
The SQI module is a synchronous serial interface that provides access to serial Flash memories and other serial devices. The SQI module supports Single Lane (identical to SPI), Dual Lane, and Quad Lane interface modes. Refer to the Serial Quad Interface (SQI) Documentation for more information: http://ww1.microchip.com/downloads/en/ DeviceDoc/60001244C.pdf.
SQI Controller 1. SQI controller is used to control the In-package serial Flash. It provides following functions: Command mode Memory mapped read

Datasheet

DS70005403B-page 41

IS2083
Application Information

7.3.3

Memory mapped write
The SQI controller provides both SPI and SQI mode. The device's initial state after a POR is SPI mode. A command instruction configures the device to SQI mode. The data flow in the SQI mode is similar to the SPI mode, except it uses four multiplexed I/O signals for command, address, and data sequence. Users are responsible to switch the mode. The SQI mode is overridden by next usage; users must set to the right mode before using it.
2-wire Interface The IS2083BM devices provide physical interface for connecting and programming the memory contents, see the following figure. For all programming interfaces, the target device must be powered, and all required signals must be connected. In addition, the interface must be enabled through a special initialization sequence.
Figure 7-6.2-wire ICSP Interface

Programmer/ Debugger

2-Wire ICSP TM

IS2IS8230B8M3BSMoC

The 2-wire ICSP port is used as interface to connect a Programmer/Debugger in IS2083BM device. The following table provides the required pin connections. This interface uses the following two communication lines to transfer data to and from the IS2083BM device being programmed:
· Serial Program Clock (TCK_CPU)
· Serial Program Data (TDI_CPU)
These signals are described in the following two sections. Refer to the specific device data sheet for the connection of the signals to the chip pins. The following table describes the 2-wire interface pins.
Table 7-2.2-wire Interface Pin Description

Pin Name RST_N VDD_IO, ADAP_IN, BAT_IN GND TCK_CPU TDI_CPU

Pin Type I P P I I/O

Description Reset pin Power supply pins Ground pin Primary programming pin pair: Serial Clock Primary programming pin pair: Serial Data

7.3.3.1 7.3.3.2

Note: For more details, refer to the IS2083 SDK Debugger User's Guide.
Serial Program Clock Serial Program Clock (TCK_CPU) is the clock that controls the updating of the TAP controller and the shifting of data through the Instruction or selected data registers. TCK_CPU is independent of the processor clock, with respect to both frequency and phase.
Serial Program Data Serial Program Data (TDI_CPU) is the data input/output to the instruction or selected data registers. In addition, it is the control signal for the TAP controller. This signal is sampled on the falling edge of TDI_CPU for some TAP controller states.

Datasheet

DS70005403B-page 42

IS2083
Application Information

7.3.4

Enabling Programming Interface On the IS2083BM, programming interfaces are enabled using the standard Microchip test patterns. Once RST_N is asserted (low), the user may provide an entry sequence on any TSTC2ENTRY and TSTD2ENTRY pin pair on the device. Once RST_N is de-asserted (high), the corresponding programming interface is enabled as per the entry sequence.
The TSTC2ENTRY/TSTD2ENTRY pin pairs are mapped on top of the CPU JTAG interface, so that 2-wire programming and debug interface may be enabled by controlling only 3 device pins (RST_N and 2 entry pins).
The programming/debugging mode is entry sequence for 2-wire mode is shown in the following table and the timing diagram is shown in the following figure.
Table 7-3.CPU Programming/Debugging Mode Entry

Debug Mode Entry Sequence

TSTC

TSTD

RST_N

Vdd

4D43 4851 "MCHQ"

Mode CPU/DSP 2-wire Debug mode

Figure 7-7.CPU Programming/Debug Mode Entry RST_N

TSTCnENTRY

32 clock pulses

TSTDnENTRY

.....

Device State

Reset

TMODn

tst_pat_tmod[3:0]

Reset value

TMODn

7.3.5
7.3.5.1 7.3.5.2

On-chip Instrumentation The OCI unit serves as an interface for On-chip Instrumentation. The OCI provides following functions for communication with On-chip Instrumentation.
· Run/Stop control · Single Step mode · Software breakpoint · Debug program · Hardware breakpoint · Program trace · Access to ACC
Enabling OCI Functionality Enabling the OCI is done by clearing the OCI_OFF bit in the OCI_DEBUG SFR register. By default, OCI is enabled after a device POR.
Entering Debug Mode Debug mode is entered by using the CPU 2-wire Test Mode Entry interface. On entry into Debug mode, the OCI holds the CPU and Watchdog Timer in the Reset state using JReset until the external debugger asserts DebugReq using the DebugReqOn JTAG instruction. This allows the debugger to configure the device before the CPU boots-up.

Datasheet

DS70005403B-page 43

IS2083
Application Information

7.3.5.3

Reading the Debug Status
There is no explicit status data register, rather, the status value is shifted out when a new JTAG Instruction Register (IR) value is shifted in.

7.3.5.4

Reading the Program Counter
The current value of the CPU program counter may be read using the Get PC JTAG instruction. In PC16 mode, only the least significant 16 bits (PC[15:0]) are valid.

7.3.5.5

Stopping Program Execution (Entering Debug Mode)
To enter Debug mode, the debugger issues the DebugReqOn JTAG instruction, which asserts the DebugReq input to the CPU core. Once the CPU enters Debug mode, the DebugAck signal is asserted, which can be determined by reading the Status. DebugAck or Result.DebugAckN register bits.

7.3.5.6

Starting Program Execution (Exiting Debug Mode)
To exit Debug mode, the debugger issues the DebugReqOff JTAG instruction, which negates the DebugReq input to the CPU core. Once the CPU exits Debug mode, the DebugAck signal is negated, which can be determined by reading the Status. DebugAck or Result.DebugAckN register bits.

7.3.5.7

User Single Step Mode
User Single Step mode, in which the CPU single steps through the code in Program Memory, is enabled when the debugger issues the DebugStepUser JTAG instruction. From Debug mode, the OCI executes one user instruction by pulsing DebugStep active for one clock (or until the first program fetch has completed). The core responds by fetching and executing one instruction, then returning to Debug mode. DebugAck is negated during the step.

7.3.5.8

OCI Single Step Mode
OCI Single Step mode, also known as Programming mode, is used to execute instructions from the debugger, typically for the purposes of programming the device. This mode is enabled when the debugger issues the DebugStepOCI JTAG instruction. Each instruction is fed into the CPU by writing it into the result register.
When device programming is being done over the OCI, the DebugPswrOn JTAG instruction may be issued to redirect External Data Writes to Program Memory. The DebugPswrOff JTAG instruction may be issued to disable this re-direction. On this device, which presents a unified Program/Data memory, this re-direction is not necessary, as the Program RAM can be written via the external data bus.

7.3.5.9

Setting Software Breakpoints
Software breakpoints may be set by replacing the instruction with a TRAP instruction (opcode 0xA5). Upon execution of the TRAP instruction, the core switches to Debug mode and asserts DebugAck. Through the JTAG port, the debugger system periodically polls Status.DebugAck (by issuing the DebugNOP JTAG instruction) and begins breakpoint processing when it becomes asserted. For breakpoints in read-only memories, Debug triggers may be used to set hardware breakpoints.

7.3.5.10

Simple and Complex Debug Triggers
The OCI provides a set of hardware breakpoint or trigger registers that monitor bus activity and perform various actions when specified bus events occur. Complex triggers allow a range of addresses to be matched for a trigger rather than a single address, as is the case for a simple trigger.

7.3.5.11

Reading and Writing Memory/SFR Registers
To read from or write to an internal resource, such as a memory or SFR registers, the OCI Single Step mode is used. In this mode, the external debugger can feed in an instruction sequence to perform the requested read/write operation. Read values are placed into the accumulator, which may then be read out of the result register using the DebugNOP JTAG instruction.

7.3.5.12 Trace Buffer The IS2083BM 8051 MCU implements a trace buffer to trace the messages from the OCI to the off-chip debugger.

7.3.5.13

Instruction Trace
The trace buffer memory stores the branches executed by the core. At every change of flow, the most recent PC from the old code sequence and the first PC from the new sequence are stored together as a trace record (frame). Change of flow events include branches, calls, returns, interrupts, and resets.

Datasheet

DS70005403B-page 44

IS2083
Application Information

7.4 General Purpose I/O Pins
The IS2083BM provides up to 19 GPIOs that can be configured by using the Config Tool. The MFB (PWR) pin must be configured as the power On/Off key, and the remaining pins can be configured for any one of the default functions as provided in the following table.
Table 7-4.GPIO Assigned Pins Function(1)

Pin Name P0_0 P0_1 P0_2 P0_3 P0_5 P0_6 P0_7 P1_2 P1_3 P1_6 P2_3 P2_6 P2_7 P3_2 P3_4 P3_5 P3_7 P8_5 P8_6

Function Assigned (in Embedded Mode) External codec reset Forward (FWD) button Play or pause (PLAY/PAUSE) button Reverse (REV) button Volume decrease (VOL_DN) button Available for user configuration Available for user configuration I2C SCL (muxed with 2-wire CPU debug data) I2C (muxed with 2-wire CPU debug clock) PWM Available for user configuration Available for user configuration Volume increase (VOL_UP) button Line-In detect SYS_CFG (muxed with UART_RTS)(2) Available for user configuration Available for user configuration UART_TXD(3)(4) UART_RXD(3)(4)

1. This table reflects the default IO assignment as per the Embedded mode. The GPIOs are user configurable by Config Tool.
2. GPIO P3_4 is used to enter Test mode during reset. If the user wants to use this pin to control external peripherals, care must be taken to ensure this pin is not pulled LOW and accidentally enters Test mode.
3. Microchip recommends to reserve UART port (P8_5 and P8_6) for Flash download in Test mode during production.
4. Currently, GPIOs ports P8_5 and P8_6 APIs (button detect driver) are not implemented.

7.5 I2S Mode Application
The IS2083BM SoC provides one I2S digital audio I/O interface to connect with an external codec or DSP. It provides 8, 16, 44.1, 48, 88.2 and 96 kHz sampling rates for 16- and 24-bit data formats. The I2S settings can be configured by the Config Tool. The I2S pins are as follows:
· SCLK1: Serial/Bit clock (IS2083BM input/output) · RFS1: Receive frame sync (IS2083BM input/output) · MCLK: Master clock (IS2083BM output)

Datasheet

DS70005403B-page 45

IS2083
Application Information

· DR1: Receive data (IS2083BM input) · DT1: Transmit data (IS2083BM output)
The MCLK is the master clock output provided to an external I2S device to use as its system clock. This signal is optional and is not required if the external I2S device provides its own system clock. This signal is not used with the internal audio codec.
The following figures illustrate the I2S signal connection between the IS2083BM and an external DSP. The Config Tool can be used to configure the IS2083BM as a master or slave.
Note: In this context, the terms "master" and "slave" refer to the I2S clocks and frame syncs, not to the audio data itself.
Figure 7-8.IS2083BM in I2S Master Mode

External DSP/ Codec
BCLK
DACLRC
MCLK
ADCDAT
DACDAT

IS2083BM
SCLK1 RFS1 MCLK DR1 DT1

Figure 7-9.IS2083BM in I2S Slave Mode
External DSP/ Codec
BCLK DACLRC

IS2083BM
SCLK1 RFS1

ADCDAT DACDAT

DR1 DT1

7.6 Host MCU Interface
The IS2083BM multi-speaker firmware supports following modes of operation: · Embedded mode In this mode, an external microcontroller (MCU) is not required. The multi-speaker (MSPK) firmware is integrated on the IS2083BM to perform application specific controls.
· Host mode: Requires an external MCU for application specific system control. The host MCU can control IS2083BM through UART command set.
The following figure illustrates the UART interface between the IS2083BM and an external MCU.

Datasheet

DS70005403B-page 46

Figure 7-10.Host MCU Interface Over UART
MCU
MCU_WAKE UP UART_RX UART_TX

IS2083
Application Information
IS2083BM
P0_0 UART_TXD UART_RXD

MFB GPIO

MFB RST_N

Note: For more details, refer to the IS2083 Bluetooth® Audio Application Design Guide Application Note.
All registers and flip-flops are synchronously Reset by an active-high internal Reset signal. External hardware Reset, or Watchdog Timer Reset can activate the Reset state. A high on RST_N pin or Watchdog Reset request for two clock cycles, while the oscillator is running, resets the device. The falling edge of clock is used for synchronization of the Reset signal. It ensures that all flip-flops are triggered by system clock and gated clocks are properly Reset.
Although a device POR (from the on-chip CLDO) does not explicitly drive the reset tree, but rather causes the assertion of the RST_N pin as follows:
1. POR causes the RST_N pad to drive '0' out. 2. Since the RST_N input buffer is always enabled, during a POR, the `0' propagates to the RST_N input buffer. 3. The RSTGEN modules see the RST_N pin asserted.

Datasheet

DS70005403B-page 47

IS2083
Electrical Specifications

8. Electrical Specifications
This section provides an overview of the IS2083BM device's electrical characteristics.
Table 8-1.Absolute Maximum Ratings

Parameter Ambient temperature under bias (TAMBIENT) Storage temperature (TSTORAGE) Digital core supply voltage (VDD_CORE) RF supply voltage (VCC_RF) SAR ADC supply voltage (SAR_VDD) Codec supply voltage (VDDA/VDDAO) I/O supply voltage (VDD_IO) Buck1 and Buck2 supply voltage (BK1_VDD and BK2_VDD) Supply voltage (LDO31_VIN) Battery input voltage (VBAT_IN) Adapter input voltage (VADAP_IN) Junction operating temperature (TJUNCTION)

Min. 40 65 0 0 0 0 0 0
0 0 0 40

Typ. -- -- -- -- -- -- -- --
-- -- -- --

Max.

Unit

+85

ºC

+150

ºC

1.35

2.1

3.3

3.6

4.3

7.0

+125

ºC

CAUTION

Stresses listed on the preceding table cause permanent damage to the device. This is a stress rating only. The functional operation of the device at those or any other conditions and those indicated in the operation listings of this specification are not implied. Exposure to maximum rating conditions for extended periods affects device reliability.

The following tables provide the recommended operating conditions and the electrical specifications of the IS2083BM SoC.
Table 8-2.Recommended Operating Condition

Parameter Digital core supply voltage (VDD_CORE) RF supply voltage (VCC_RF) SAR ADC supply voltage (SAR_VDD) Codec supply voltage (VDDA) I/O supply voltage (VDD_IO) Buck1 supply voltage (BK1_VDD) Buck2 supply voltage (BK2_VDD) Supply voltage (LDO31_VIN) Input voltage for battery (VBAT_IN) Input voltage for adapter (VADAP_IN(1)) Operation temperature (TOPERATION)

Min. 1.14 1.22 1.62 1.62 3.0 3.0 3.0 3.0 3.2 4.5 -40

Typ. 1.2 1.28 1.8 1.8 3.3 3.8 3.8 3.8 3.8 5 +25

Max.

Unit

1.26

1.34

1.98

3.6

4.25

4.2

5.5

+85

ºC

Datasheet

DS70005403B-page 48

IS2083
Electrical Specifications

1. ADAP_IN is recommended only for charging the battery in the battery-powered applications. Table 8-3.Buck1 (RF/Core/ULPC) Switching Regulator(1)

Parameter Input voltage Output voltage (Iload = 70 mA and VIN = 4V) Output voltage accuracy Output voltage adjustable step Output adjustment range Average load current (Iload) Conversion efficiency (VBAT_IN = 3.8V and Iload = 50 mA) Quiescent current (PFM) Output current (peak) Shutdown current

Min. 3.0 1.4 -- -- 0.1 120 -- -- 200 --

Typ. 3.8 1.5 ±5 50 -- -- 88 (2) -- -- --

Max. 4.25 1.75 -- -- +0.25 -- -- 40 -- <1

Unit V V % mV/Step V mA % A mA A

1. These parameters are characterized, but not tested on the production device. 2. Test condition: Temperature +25ºC and wired inductor 10 H.
Table 8-4.Buck2 (Audio Codec) Switching Regulator(1)

Parameter Input voltage Output voltage (Iload = 70 mA, VIN = 4V Output voltage accuracy Output voltage adjustable step Output adjustment range Average load current (Iload) Conversion efficiency (VBAT_IN = 3.8V, Iload= 50 mA)
Quiescent current (PFM) Output current (peak) Shutdown current

Min. 3.0 1.7 -- -- 0.1 120 --
-- 200 --

Typ. 3.8 1.8 ±5 50 -- -- 88(2)
-- -- --

Max. 4.25 2.05 -- -- +0.25 -- --
40 -- <1

Unit V V % mV/Step V mA %
µA mA µA

1. These parameters are characterized, but not tested on the production device. 2. Test condition: Temperature +25ºC and wired inductor 10 H.
Table 8-5.LDO Regulator(1)

Parameter

Input voltage

Output voltage

LDO31_VO

Output accuracy (VIN= 3.7V, Iload= 100 mA and +27ºC) Average output current

Min. 3.0 -- -- --

Typ. 3.8 3.3 ±5 --

Max.

Unit

4.25

100

Datasheet

DS70005403B-page 49

IS2083
Electrical Specifications

...........continued Parameter
Drop-out voltage (Iload = maximum output current) Quiescent current (excluding load and Iload < 1 mA) Shutdown current

Min. -- -- --

Typ. -- 45 --

Max.

Unit

300

µA

1. These parameters are characterized, but not tested on production device. 2. Test condition: Temperature +25ºC. The above measurements are done at +25ºC.
Table 8-6.Battery Charger (1)

Parameter

Min.

Adapter input voltage (VADAP_IN) Supply current (only charger)

4.6(2) --

Maximum battery fast charge current
Trickle charge voltage threshold

Headroom(3) > 0.7V

(VADAP_IN = 5V)

Headroom = 0.3V to 0.7V -- (VADAP_IN = 4.5V)

Battery charge termination current (% of fast charge

current)

Typ. 5.0 3 350
175(4)
3 10

Max. 5.5 4.5 --
--
-- --

Unit V mA mA
mA
V %

1. These parameters are characterized, but not tested on production device. 2. It needs more time to get battery fully charged when ADAP_IN = 4.5V. 3. Headroom = VADAP_IN VBAT_IN. 4. When VADAP_IN VBAT_IN > 2V, the maximum fast charge current is 175 mA for thermal protection.
Table 8-7.SAR ADC Operating Conditions

Parameter

Condition

Shutdown current (IOFF) Resolution

PDI_ADC = 1 --

Effective Number of Bits (ENOB) --

SAR core clock (FCLOCK) Conversion time per channel (TCONV) Offset error (EOFFSET) Gain error (EGAIN) ADC SAR core power-up (tPU)

-- 10 FCLOCK cycles
-- -- PDI_ADC transitions from 1 to 0

Min. -- -- 7 -- 10
-5 -- --

Typ. -- 10 8 0.5 20
-- -- --

Max. 1 -- -- 1 --
+5 +1 500

Unit A bits bits MHz s
% % ns

Datasheet

DS70005403B-page 50

IS2083
Electrical Specifications

...........continued Parameter
Input voltage range (VIN)

Condition

Min.

Typ.

Channel 8 (SK2 Pin) 0.25

Channel 9 (SK1 Pin) 0.25

Channel 10 (OTP)

0.25

Channel 11 (ADAP_IN 2.25

Pin)

Channel 12 (BAT_IN 1.0

Pin)

Table 8-8.LED Driver(1) Parameter Open-drain voltage Programmable current range Intensity control Current step Power-down open-drain current Shutdown current

Min. -- 0 -- -- -- --

Typ. -- -- 16 0.35 -- --

1. These parameters are characterized, but not tested on production device. Table 8-9.Audio Codec Digital-to-Analog Converter

Parameters DC Specifications Shutdown mode current Over-sampling rate Sample width resolution Output sample rate Digital gain Digital gain resolution Analog gain Analog gain resolution Turn ON/OFF click and pop level
Gain pop Allowed load
AC Specifications(1) SNR Capless mode SNR Cap mode

Single-ended Capless
Resistive Capacitive
AVDD = 1.8V AVDD = 1.8V

Min.
-- -- 16 8 54 2 28 -- -- -- -- 16 --
93 95

Typ.
-- 128 -- -- -- 6 -- 1 -- -- 1 -- --
-- --

Max. 1.4 1.4 1.4 12.6
5.6
Max. 3.6 5.25 -- -- 1 1
Max.
2 -- 20 48 4.85 0 3 -- 2 1 1 -- 500
-- --

Unit V V V V
V
Unit V mA step mA A A
Unit
A fs Bits kHz dB dB dB dB mV mV mV pF
dB dB

Datasheet

DS70005403B-page 51

IS2083
Electrical Specifications

...........continued Parameters
Output voltage full-scale swing

Total harmonic distortion Inter-channel isolation Dynamic range
Playback Mode Power Stereo mode current (16 or unload)
Mono mode current (16 or unload)
Maximum output power (AVDD = 1.8V)

AVDD = 1.8V
Capless and Singleended
Capless Single-ended Capless Single-ended Capless Single-ended

Min. 495 (1.4)

Typ.

Max.

742.5 (2.1) --

1.85

1.55

1.40

Unit mV rms (Vpp) dB dB dB
mA
mA
mW mW

1. fin = 1 kHz, bandwidth = 20 Hz to 20 kHz, A-weighted, THD+N < 0.01%, 0 dBFS signal, load = 100 k. Table 8-10.Audio Codec Analog-to-Digital Converter

Parameter (Condition) DC Specifications Shutdown mode Sample width resolution Input sample rate Digital gain Digital gain resolution Microphone boost gain Analog gain step Input full-scale at maximum gain (Differential) Input full-scale at minimum gain (Differential) 3 dB bandwidth Microphone mode input impedance (Resistance) Microphone mode input impedance (Capacitance) AC Specifications(1) SNR (AVDD = 1.8V) Total harmonic distortion (AVDD = 1.8V) Dynamic range (AVDD = 1.8V) THD+N (microphone input) at 30 mVrms input Record Mode Power

Min.
-- -- 8 54 2 -- -- -- -- -- -- --
88 -- -- --

Typ.
1 -- -- -- 6 20 1 4 800 20 6 --
-- 70 88 0.02

Max.
2 16 48 4.85 -- -- -- -- -- -- 10 20
-- -- -- --

Unit
µA Bits kHz dB dB dB dB mV rms mV rms kHz k pF
dB dB dB %

Datasheet

DS70005403B-page 52

IS2083
Electrical Specifications

...........continued Parameter (Condition) Stereo Record mode current Mono Record mode current

Min. -- --

Typ. 1.75 0.95

Max.

Unit

1. fin = 1 kHz, bandwidth= 20 Hz to 20 kHz, A-weighted, THD+N <1%, 150 mVPP input. Table 8-11.Transmitter Section Class1 (MPA Configuration) for BDR and EDR(1, 2)

Parameter(3, 4)

Bluetooth Specification Min.

Typ.

Max.

Transmit power BDR

0 to 20

10.5

11.5

Transmit power EDR 2M

0 to 20

9.5

Transmit power EDR 3M

0 to 20

9.5

Unit dBm dBm dBm

1. These parameters are characterized, but not tested on production device. 2. Test condition: VCC_RF = 1.28V, temperature +25ºC. 3. The RF transmit power is the average power measured for the mid-channel (Channel 39). 4. The RF transmit power is calibrated during production using the MP tool software and MT8852 Bluetooth test
equipment.
Table 8-12.Transmitter Section Class2 (LPA Configuration) for BDR and EDR(1, 2)

Parameter(3, 4)

Bluetooth Specification Min.

Typ.

Max.

Unit

Transmit power BDR

6 to 4

1.5

2.5

dBm

Transmit power EDR 2M

6 to 4

0.5

dBm

Transmit power EDR 3M

6 to 4

0.5

dBm

1. These parameters are characterized, but not tested on production device. 2. Test condition: VCC_RF = 1.28V, temperature +25ºC. 3. The RF transmit power is the average power measured for the mid-channel (Channel 39). 4. The RF transmit power is calibrated during production using the MP tool software and MT8852 Bluetooth test
equipment.
Table 8-13.Receiver Section for BDR, EDR, Bluetooth Low Energy(1, 2)

Parameter

Packet Type

Bluetooth

Min.

Typ.

Max.

Unit

Specification

Sensitivity at 0.1% GFSK BER

dBm

Sensitivity at 0.01% BER

/4 DQPSK 8 DPSK

70 70

dBm

Sensitivity at 0.1% Bluetooth Low

BER

Energy

dBm

1. These parameters are characterized, but not tested on production device. 2. Test condition: VCC_RF = 1.28V, temperature +25ºC.

Datasheet

DS70005403B-page 53

IS2083
Electrical Specifications

Table 8-14.IS2083BM System Current Consumption(1)

Modes

Condition

Role

Packet Type Current (Typ.) Unit

A2DP mode Internal codec, iOS Master Slave

2DH5/3DH5

12.0576

Internal codec, AndroidTM Slave

Master

3DH5

12.3218

Sniff mode(2) Internal codec, Bluetooth

Slave

DM1

547.232

µA

Low Energy disabled

Master

2DH1/3DH1

555.7494

µA

Internal codec, Bluetooth

Slave

DM1

832.109

µA

Low Energy enabled

Master

2DH1/3DH1

863.8432

µA

SCO/eSCO Mute at both far end and connection near end

Slave Master

2EV3 2EV3

14.1004

13.9436

Inquiry scan Bluetooth Low Energy

disabled

1.354

Bluetooth Low Energy

enabled

1.704

Standby mode

System off

Slave

Master

2.8162

µA

2.855

µA

RF modes(3) Continuous TX mode

Modulation OFF, PL0

Modulation 30

ON, PL0

Modulation 35.5

OFF, PL2

Modulation 22

ON, PL2

Continuous RX mode

Packet count disable

Packet count enable

38.5

1. Measurement conditions are: VBAT_IN = 3.8V; current measured across BAT_IN Standalone BM83 DVT3 module used for measurements; no LEDs, no speaker load. iPhone6 (iOS v12.2) and OnePlus6 (Android Oxygen version 9.0.3) used for measurements. Current measurements average over a period of 120 secs. Distance between DUT (BM83) and Bluetooth source (smartphone) is 30 cms. All measurements are taken inside a shield room.
2. Internal Codec mode enabled, UART disabled, Auto-Unsniff mode is disabled. 3. RF TX power is set to 10 dBm.

8.1 Timing Specifications
The following figures illustrate the timing diagram of the IS2083BM/BM83 in I2S and PCM modes.

Datasheet

DS70005403B-page 54

Figure 8-1.Timing Diagram for I2S Modes (Master/Slave) 1/fs
SCLK1

RFS1

Left channel

IS2083
Electrical Specifications
Right channel

DR1/DT1

Bn-1 Bn-2

B1 B0

Word length

Figure 8-2.Timing Diagram for PCM Modes (Master/Slave)

Bn-1 Bn-2

1/fs

SCLK1

RFS1

Left channel

Right channel

DR1/DT1

Bn-1 Bn-2

B1 Bn Bn-1 Bn-2

Word length

B1 Bn

The following figure illustrates the timing diagram of the audio interface. Figure 8-3.Audio Interface Timing Diagram

tSCLKCH

tSCLKCL

SCLK1

tSCLKCY

B1 Bn

RFS1

tRFSH

tRFSSU

DR1
tDH

The following table provides the timing specifications of the audio interface. Table 8-15.Audio Interface Timing Specifications (1)

Parameter SCLK1 duty ratio

Symbol dSCLK

Min. --

Typ. 50

Max. --

Unit %

Datasheet

DS70005403B-page 55

IS2083
Electrical Specifications

...........continued Parameter SCLK1 cycle time SCLK1 pulse width high SCLK1 pulse width low RFS1 setup time to SCLK1 rising edge RFS1 hold time from SCLK1 rising edge DR1 hold time from SCLK1 rising edge

Symbol tSCLKCY tSCLKCH tSCLKCL tRFSSU tRFSH tDH

Min. 50 20 20 10 10 10

Typ.

Max.

1. Test Conditions: Slave mode, fs = 48 kHz, 24-bit data, and SCLK1 period = 256 fs.

Unit ns ns ns ns ns ns

Datasheet

DS70005403B-page 56

IS2083
Package Information

9. Package Information
Note: For the most recent package drawings, see the Microchip Packaging Specification located at http:// www.microchip.com/packaging.
Figure 9-1.82-Ball Very Thin Fine Pitch Ball Grid Array (3MX) - 5.5x5.5 mm Body [VFBGA]

NOTE 1

(DATUM B) D
E

F
(DATUM A) G

0.10 C K

D
1 2 3 4 5 6 7 8 9 10

A B E

C SEATING A
PLANE

2X 0.10 C
(A2)
(A3)

TOP VIEW SIDE VIEW

A1 0.10 C
82X 0.08 C

D1
1 2 3 4 5 6 7 8 9 10

K
J
H
G F

e 2

NOTE 1

e
BOTTOM VIEW

Datasheet

DS70005403B-page 57

IS2083
Package Information
Figure 9-2.82-Ball Very Thin Fine Pitch Ball Grid Array (3MX) - 5.5x5.5 mm Body [VFBGA]

Units

Dimension Limits

Number of Terminals

Pitch

Overall Height

Standoff

Mold Thickness

Substrate Thickness

Overall Length

Overall Terminal Spacing

Overall Width

Overall Terminal Spacing

Terminal Diameter

MILLIMETERS

MIN

NOM

MAX

0.50 BSC

0.90

0.11

0.21

0.54 REF

0.125 REF

5.50 BSC

4.50 BSC

5.50 BSC

4.50 BSC

0.20

0.25

0.30

No te s :
1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated 3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only.

Datasheet

DS70005403B-page 58

Figure 9-3.IS2083BM Recommended Land Pattern
1 2 3 4 5 6 7 8 9 10
A B C D E F G H J K
ØX E
C1
RECOMMENDED LAND PATTERN

IS2083
Package Information
E C2
G
SILK SCREEN

Units

Dimension Limits

Contact Pitch

Overall Contact Pad Spacing

Contact Pad Width (X82)

Contact Pad to Contact Pad

MILLIMETERS

MIN

NOM

MAX

0.50 BSC

4.50

0.20

Notes:
1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process

Datasheet

DS70005403B-page 59

Figure 9-4.IS2083BM Package Marking Information

IS2083
Package Information

XXX: Chip serial number version and e1 Pb-free JEDEC designator for SAC305

YY: WW: NNN:

Year code (last 2 digits of calendar year) Week code (week of January 1 is week "01") Alphanumeric traceability code

Note: (1) SAC305 is the pre-solder version. Customer needs to take care solder paste before screen printing.

Datasheet

DS70005403B-page 60

IS2083
Ordering Information

10.

Ordering Information
Table 10-1.Ordering Information

Device

Description

Package Details

IS2083BM

Bluetooth Audio Dual mode Flash SoC, 2 5.5 mm X 5.5 mm X 0.9

microphones, 1 stereo digital

mm, 82 LD VFBGA

microphone, analog and I2S output

Bluetooth Audio Dual mode, Flash SoC, 2 microphones, 1 stereo digital microphone, LDAC support and I2S output

5.5 mm X 5.5 mm X 0.9 mm, 82 LD VFBGA

Part Number IS2083BM-232
IS2083BM-2L2

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Document Revision History

11.

Document Revision History

Revision B

Date 09/2019

Section Document 6.1 Device Operation 6.7 Battery Charging 6.8 SAR ADC

Description
Minor edits.
Updated Figure 6-1
Updated Figure 6-2
· Changed the section title to SAR ADC from Battery Voltage Monitoring and combined Ambient Temperature Detection Section.
· Updated contents.

7. Application Information

· Reorganized sections in this chapter. · Added 7.1 Power On/Off Sequence section. · Updated 7.2 Reset section. · Updated 7.4 General Purpose I/O Pins.

8. Electrical Specifications

Added Table 8-7

07/2019

Document

Initial Revision

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Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with

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your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated.
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© 2019, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
ISBN: 978-1-5224-5034-4
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Worldwide Sales and Service

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