ZC702 Evaluation Board for the Zynq-7000 XC7Z020 SoC User Guide
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ZC702 Evaluation Board for the Zynq-7000 XC7Z020 SoC User Guide
Describes the ZC702 evaluation board for the Zynq®-7000 XC7Z020-1CLG484C SoC.
UG850, Zynq-7000, XC7Z020, SoC, SoC, evaluation board, eval bd, v1.7
ZC702 Evaluation Board for the Zynq-7000 XC7Z020 SoC User ...
constraints file list is removed, and access instructions are added. Updated Appendix E, Regulatory an d Compliance Information . Corrected the v1.6.1 revision history date to 06/29/2018. Date Version Revision Send Feed…
ZC702 Evaluation Board for the Zynq-7000 XC7Z020 SoC User Guide UG850 (v1.7) March 27, 2019
Extracted Text
ZC702 Evaluation Board for the Zynq-7000 XC7Z020 SoC
User Guide
UG850 (v1.7) March 27, 2019
Please Read: Important Legal Notices
The information disclosed to you hereunder (the "Materials") is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of Xilinx's limited warranty, please refer to Xilinx's Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in such critical applications, please refer to Xilinx's Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos. AUTOMOTIVE APPLICATIONS DISCLAIMER AUTOMOTIVE PRODUCTS (IDENTIFIED AS "XA" IN THE PART NUMBER) ARE NOT WARRANTED FOR USE IN THE DEPLOYMENT OF AIRBAGS OR FOR USE IN APPLICATIONS THAT AFFECT CONTROL OF A VEHICLE ("SAFETY APPLICATION") UNLESS THERE IS A SAFETY CONCEPT OR REDUNDANCY FEATURE CONSISTENT WITH THE ISO 26262 AUTOMOTIVE SAFETY STANDARD ("SAFETY DESIGN"). CUSTOMER SHALL, PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE PRODUCTS, THOROUGHLY TEST SUCH SYSTEMS FOR SAFETY PURPOSES. USE OF PRODUCTS IN A SAFETY APPLICATION WITHOUT A SAFETY DESIGN IS FULLY AT THE RISK OF CUSTOMER, SUBJECT ONLY TO APPLICABLE LAWS AND REGULATIONS GOVERNING LIMITATIONS ON PRODUCT LIABILITY. � Copyright 2012�2019 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. Arm is a registered trademark of Arm in the EU and other countries. All other trademarks are the property of their respective owners.
Revision History
The following table shows the revision history for this document.
Date
05/24/2012 10/08/2012
Version
1.0 1.1
Revision
Initial Xilinx release. The board photo in Figure 1-2 was updated. Table 1-2, Switch SW16 Configuration Option Settings was added. The part number in Quad-SPI Flash Memory changed to N25Q128A13ESF40F. In Table 1-6, the J35 shunt controls OTG and Device mode. The frequency jitter in System Clock changed from 20 ppm to 50 ppm. The action description under Program_B Pushbutton changed. The 34 differential user-defined signals are defined as 34 LA pairs, LA00�LA33, in LPC Connectors J3 and J4. In the same section, 34 differential user-defined pairs changed to 68 single-ended or 34 differential user-defined signals. Appendix E, Regulatory and Compliance Information now includes a link to the Declaration of Conformity and markings for waste electrical and electronic equipment (WEEE), restriction of hazardous substances (RoHS), and CE compliance.
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Date
04/04/2013
06/04/2014 04/30/2015
Version
1.2
1.3 1.4
Revision
Chapter 1, ZC702 Evaluation Board Features: Marvell 88E1111 was changed to Marvell 88E1116R throughout the document. The bullet just before Block Diagram, page 10 changed from PL JTAG header to PS JTAG header. In Table 1-1, callout 3, PC28F00AG18FE StrataFlash memory changed to 128 Mb, N25Q128A11ESF40G. In callout 9, Marvell M88E1116R-BAB1C000 changed to 88E1116RA0-NNC1C000. Callout 30 for J59 and 31 for J60 were added. The Zynq-7000 XC7Z020 SoC, page 14 description for callout 1 changed. Callout 29 added a link to Table 1-2. Table 1-2 was removed because it is a duplicate of Table 1-10. Above Table 1-2, "configuration option" was changed to "JTAG configuration option." In Table 1-2, the PLL Used mode row was removed and the default setting changed. Section Encryption Key Backup Circuit, page 17 was added. In I/O Voltage Rails, "There are four I/O banks available on the XC7Z020 SoC" was changed to "There are four PL I/O banks available on the XC7Z020 SoC." A note about DDR3 memory was added after Table 1-4. In Quad-SPI Flash Memory and Figure 1-6, N25Q128A13ESF40F (Micron/Numonyx) changed to N25Q128A11ESF40G. In Quad-SPI Flash Memory, "The configuration section of UG585..." was changed to add "The configuration and QSPI section of UG585..." JTAG information in Figure 1-10 and Table 1-10 was updated. In Figure 1-10 pin numbers 5 and 6 are swapped and in U76, IN2 and IN1 switched places. In Table 1-10, SW10 became SW10[1:2] in the table column heading and the default setting was added. In Processing System Clock Source, frequency jitter changed from 20 ppm to 50 ppm. In I2C Bus, NXP semiconductor changed to TI. Figure 1-15 is updated. R249 was added to Figure 1-17. In Table 1-22, reference designator DS12 changed to DS14. U3 level shifter was changed to TXS0104E in Figure 1-19 and Table 1-21. The User I/O section was updated. Figure 1-21 added two LEDs. Table 1-23 added Net Name PS_LED1 and PS_MIO8_LED0 and removed pin info. Section User PS Switches was added. The Figure 1-26 title changed. A paragraph about design criteria was added to Power Management. A paragraph about the TI Fusion Digital Power graphical user interface precedes Table 1-30. Voltages were added to the description of U19 in Table 1-30. The TI link on page 62 was updated. Appendix A, Default Switch and Jumper Settings: In Table A-1, SW16 position 4 changed from right to left. Appendix C, Xilinx Design Constraints: A reminder was added to use the latest UCF listing. Minor changes were made to the list, and power and ground pin constraints were removed. Appendix D, Board Specifications: This appendix was added to the book. Appendix E, Regulatory and Compliance Information: A link to the ZC702 board master answer record was added.
Table 1-6 USB Jumper Settings was updated to highlight default shunt positions. GND changed to GA0 = 0 = GND in Table 1-28 and Table 1-29. The Appendix C Master UCF Listing was replaced with the Xilinx Design Constraints (XDC) file listing. The link in Declaration of Conformity was updated.
Description added to FMC Connector JTAG Bypass. Modifications to Table 1-12, Table 1-16, Table 1-17, Table 1-23, Table 1-25, Table 1-27, Table 1-28, and Table 1-29. Note added to Table 1-20. Revised the PMBus Controller�Aux address for U34 from 53 to 54 in Table 1-30. Annotations added to ZC702 Board Constraints File Listing. Added Figure Figure A-1 to identify jumper locations referenced in Table A-2.
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Date
09/04/2015
01/03/2018 06/29/2018 03/27/2019
Version
1.5
1.6 1.6.1 1.7
Revision
Added missing symbol font to fix improperly rendered text (kW, mF) to the correct units (k, F) in Table 1-6, rows 3 and 4. Removed base ambiguity from PMBUS address numbers 52, 53, and 54 by updating them according to context to 52 decimal, 53 decimal, and 54 decimal or to binary 0b0110100, 0b0110101 and 0b0110110 in Table 1-19, in Figure 1-29, in Table 1-30, in the first paragraph under Monitoring Voltage and Current, in Table 1-31, in Table 1-32, and in Table 1-33. Fixed typographical error in Figure 1-1. Updated User PMOD GPIO Headers. Editorial updates only. No technical content updates. Updated Electrostatic Discharge Caution information. Updated the DDR3 Component Memory and LPC Connectors J3 and J4 sections. Updated the function of callout 1 in Table A-2. Appendix C is renamed Xilinx Design Constraints, the constraints file list is removed, and access instructions are added. Updated Appendix E, Regulatory and Compliance Information. Corrected the v1.6.1 revision history date to 06/29/2018.
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Table of Contents
Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Chapter 1: ZC702 Evaluation Board Features
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
ZC702 Board Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Electrostatic Discharge Caution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Feature Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Zynq-7000 XC7Z020 SoC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Device Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Encryption Key Backup Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 I/O Voltage Rails . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
DDR3 Component Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Component Memory Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Quad-SPI Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 USB 2.0 ULPI Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 SD Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Programmable Logic JTAG Programming Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Programmable Logic JTAG Select Switch, JTAG Cable Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 FMC Connector JTAG Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 System Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Programmable User Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Processing System Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 10/100/1000 MHz Tri-Speed Ethernet PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Ethernet PHY Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 USB-to-UART Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 HDMI Video Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Real-Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 I/O Expansion Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 High Speed CAN Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Ethernet PHY User LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 User I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 User LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 User Pushbuttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 GPIO DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 User PS Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
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User PMOD GPIO Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Power On/Off Slide Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Program_B Pushbutton . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 PS Power-On and System Reset Pushbuttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 FPGA Mezzanine (FMC) Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 LPC Connectors J3 and J4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 VADJ Voltage Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Monitoring Voltage and Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Cooling Fan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 XADC Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Appendix A: Default Switch and Jumper Settings
Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Jumpers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Appendix B: VITA 57.1 FMC Connector Pinouts
Appendix C: Xilinx Design Constraints
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Appendix D: Board Specifications
Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Environmental . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 Humidity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 Operating Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Appendix E: Regulatory and Compliance Information
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 CE Directives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 CE Standards. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Electromagnetic Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
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Appendix F: Additional Resources
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Solution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
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Chapter 1
ZC702 Evaluation Board Features
Overview
The ZC702 evaluation board for the XC7Z020 SoC provides a hardware environment for developing atnd evaluating designs targeting the Zynq� XC7Z020-1CLG484C device. The ZC702 board provides features common to many embedded processing systems, including DDR3 component memory, a tri-mode Ethernet PHY, general purpose I/O, and two UART interfaces. Other features can be supported using VITA-57 FPGA mezzanine cards (FMC) attached to either of two low pin count (LPC) FMC connectors.
ZC702 Board Features
The ZC702 board features are listed in here. Detailed information for each feature is provided in Feature Descriptions. � Zynq XC7Z020-1CLG484C device � 1 GB DDR3 component memory (four 256 Mb x 8 devices) � 128 Mb Quad SPI flash memory � USB 2.0 ULPI (UTMI+ low pin interface) transceiver � Secure Digital (SD) connector � USB JTAG interface using a Digilent module � Clock sources:
� Fixed 200 MHz LVDS oscillator (differential) � I2C programmable LVDS oscillator (differential) � Fixed 33.33 MHz LVCMOS oscillator (single-ended) � Ethernet PHY RGMII interface with RJ-45 connector � USB-to-UART bridge � HDMI codec � I2C bus
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Overview
� I2C bus multiplexed to: � Si570 user clock � ADV7511 HDMI codec � M24C08 EEPROM (1 kB) � 1-To-16 TCA6416APWR port expander � RTC-8564JE real time clock � FMC1 LPC connector � FMC2 LPC connector � PMBUS data/clock
� Status LEDs: � Ethernet status � Power good � FPGA INIT � FPGA DONE
� User I/O: � Two programmable logic (PL) user pushbuttons � PL user DIP switch (2-pole) � Eight PL user LEDs � Two processing system (PS) pushbuttons shared with PS 2-pole DIP switch � Two PS user LEDs � Dual row Pmod GPIO header � Single row Pmod GPIO header
� SoC PS Reset Pushbuttons: � SRST_B PS reset button � POR_B PS reset button
� Two VITA 57.1 FMC LPC connectors � Power on/off slide switch � Power management with PMBus voltage and current monitoring via TI power
controllers � Dual 12-bit 1 MSPS XADC analog-to-digital front end � Configuration options:
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� Quad SPI flash memory � USB JTAG configuration port (Digilent module) � Platform cable header JTAG configuration port � 20-pin PL PJTAG header � 20-pin PS JTAG header
Block Diagram
The ZC702 board block diagram is shown in Figure 1-1.
X-Ref Target - Figure 1-1
Quad SPI Flash Memory
Page 20
JTAG Module and
Connector
Page 15
DDR3 Memory 4 x 256 Mb x 8
SDRAM
Pages 16-19
Clock and Reset/POR Pushbuttons
Page 14
JTAG Header Page 15
USB UART Page 36
Overview
CAN Bus
Page 21 SD Card Connector
Page 22 FMC1 LPC Connector
Page 23 FMC2 LPC Connector
Page 24
Processing System
U1 Zynq-7000 SoC XC7Z020-1CLG484C
Programmable Logic
ARM PJTAG Header
Page 35
Switches LEDs and Pushbuttons Page 34
I2C Real Time
Clock Page 33
I2C Multiplexer and
I2C EEPROM Page 32
Mechanicals Page 38
10/100/1,000 Ethernet PHY (RGMII only)
Page 26
USB 2.0 ULPI Transceiver
and Connector
Page 27
HDMI Codec and
Connector
Page 28, 29
Configurable Clocks
Page 30
Note: Page numbers reference the page number of schematic 0381449.
XADC Header
Page 31
Figure 1-1: ZC702 Board Block Diagram
UG850_c1_01_062918
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Electrostatic Discharge Caution
Board Layout
Figure 1-2 shows the ZC702 board. Each numbered feature that is referenced in Figure 1-2 is described in Table 1-1 with a link to detailed information provided under Feature Descriptions. Note that the image in Figure 1-2 is for reference only and might not reflect the current revision of the board.
Electrostatic Discharge Caution
CAUTION! ESD can damage electronic components when they are improperly handled, and can result in total or intermittent failures. Always follow ESD-prevention procedures when removing and replacing components.
To prevent ESD damage:
� Use an ESD wrist or ankle strap and ensure that it makes skin contact. Connect the equipment end of the strap to an unpainted metal surface on the chassis.
� Avoid touching the adapter against your clothing. The wrist strap protects components from ESD on the body only.
� Handle the adapter by its bracket or edges only. Avoid touching the printed circuit board or the connectors.
� Put the adapter down only on an antistatic surface such as the bag supplied in your kit. � If you are returning the adapter to Xilinx Product Support, place it back in its antistatic
bag immediately.
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Electrostatic Discharge Caution
X-Ref Target - Figure 1-2
00
Round callout references a component on the front side of the board
24
00
Square callout references a component on the back side of the board
24
27 26
29
3
17
5 18 19
18 30
31
23 20
8 1
7
25 25
14 13
15 2
22
9 10
21 12
6
11
4
28
16
Figure 1-2: ZC702 Board Component Locations
UG850_c1_02_032013
Table 1-1: ZC702 Board Component Descriptions
Callout
Reference Designator
Component Description
1
U1
Zynq-7000 XC7Z020 SoC
2
U66�U69
DDR3 Component Memory, 1 GB
3
U41
Quad-SPI Flash Memory, 128 Mb
4
U9, J1
USB 2.0 ULPI Transceiver, USB Mini-B connector
Notes
Xilinx part number: XC7Z020-1CLG484C 4 each 256Mb X 8 SDRAM Micron Technology Inc, MT41J256M8DA-107 Micron N25Q128A11ESF40G SMSC USB3320-EZK High-Speed USB transceiver
Schematic(1) 0381449 Page
Number
16�19
20 27
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Table 1-1: ZC702 Board Component Descriptions (Cont'd)
Callout
Reference Designator
Component Description
Notes
5
J64
SD Card Interface connector
Molex 67840-8001 SDIO Memory card connector
6
Programmable Logic JTAG
U23
Programming Options with integrated Digilent USB JTAG Module
Micro-B connector
7
U43
System Clock, 200 MHz, 2.5V LVDS oscillator
SiTime SIT9102-243N25E200.0000
8
U28, U65
Programmable User Clock and Processing System Clock Source
Silicon Labs SI570BAB0000544DG, default 156.250MHz, PS fixed 33 MHz clock
9
U35, P2
10/100/1000 MHz Tri-Speed Ethernet Marvell 88E1116RA0-NNC1C000, Halo
PHY, RJ45 w/magnetics
HFJ11-1G01ERL
10
X1
Ethernet PHY Clock Source, 25.000 MHz
Epson MA-506-25.000m-CO:ROHS
11
DS6�DS8
Ethernet PHY User LEDs
Ethernet PHY User LEDs, GREEN
12
U36, J17
USB-to-UART Bridge, USB Mini-B connector
Silicon Labs CP2103GM, Molex 54819-0589
13
U40, P1
HDMI Video Output
Analog Devices ADV7511KSTZ-P HDMI transmitter, Molex 500254-1927 HDMI receptacle
14
U44
I2C Bus
TI PCA9548ARGER
15
U16
Real-Time Clock
Epson RTC-8564JE:3:ROHS
16
J54
I/O Expansion Header driven from I2C Expander U80
2-row pin header
17
DS15�DS22
User LEDs
GPIO LEDs, GREEN 0603
18
SW5, SW7
User Pushbuttons SW5 = Left, SW7 = Right
E-Switch TL3301EP100QG
19
SW12
GPIO DIP Switch
2-pole C&K SDA02H1SBD
20
SW11
Power On/Off Slide Switch
C and K 1201M2S3AQE2
21
U14
High Speed CAN Transceiver
NXP TJA1040T/VM
22
SW4
Program_B Pushbutton
E-Switch TL3301EP100QG
23
SW10, J2
Programmable Logic JTAG Select Switch, JTAG Cable Connector
2-pole C and K SDA02H1SBD MOLEX 87832-1420
24
J3, J4
FPGA Mezzanine (FMC) Card Interface Samtec ASP_134486_01
25
U32, U33, U34
Power Management (bottom and top of board)
TI UCD9248PFC in conjunction with various regulators
26
J40
XADC Analog-to-Digital Converter
2X10 0.-inch male header
27
SW1, SW2
PS Power-On and System Reset Pushbuttons
Panasonic EVQ-11L07K 14
28
J62, J63
User PMOD GPIO Headers
J63 2 x 6 0.1 inch J63 1 x 6 0.1 inch male headers
29
SW16
5-pole SPDT MIO DIP switch
CTS 206-125. See Table 1-2 for switch settings.
30
J59
2x5 shrouded PMBus connector (bottom of board)
ASSMAN HW10G-0202
Schematic(1) 0381449 Page
Number 22
15
30
30
25�26
25 25 36
28�29
32 33 33 34 34 34 47 21 34 15 23, 24
39�47
31 35, 36
34, 35
14
47
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Table 1-1: ZC702 Board Component Descriptions (Cont'd)
Callout
Reference Designator
Component Description
Notes
31
J60
12V power input 2x6 connector
MOLEX 39-30-1060
Notes: 1. The ZC702 board schematics are available for download. See ZC702 Evaluation Kit. 2. Jumper locations are shown in Figure A-1.
Feature Descriptions
Schematic(1) 0381449 Page
Number 47
Feature Descriptions
Detailed information for each feature shown in Figure 1-2 and listed in Table 1-1 is provided in this section.
Zynq-7000 XC7Z020 SoC
[Figure 1-2, callout 1]
The ZC702 board is populated with the Zynq-7000 XC7Z020-1CLG484C SoC. The XC7Z020 SoC consists of an SoC-style integrated processing system (PS) and programmable logic (PL) on a single die.
The high-level block diagram is shown in Figure 1-3.
X-Ref Target - Figure 1-3
Processing System (PS)
Memory Interfaces
Programmable Logic (PL)
Input Output Peripherals
(IOP)
High-Bandwidth AMBA� AXI Interfaces
Application Processor Unit (APU)
Interconnect
Common Peripherals
Custom Peripherals
Common Accelerators Custom Accelerators
Figure 1-3: High-Level Block Diagram
UG850_c1_03_081612
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Feature Descriptions
The PS integrates two Arm� CortexTM-A9 MPCoreTM application processors, AMBA� interconnect, internal memories, external memory interfaces, and peripherals including USB, Ethernet, SPI, SD/SDIO, I2C, CAN, UART, and GPIO. The PS runs independently of the PL and boots at power-up or reset.
A system level block diagram is shown in Figure 1-4.
X-Ref Target - Figure 1-4
Zynq-7000 SoC
I/O Peripherals
USB
Processing System
Clock Generation
Reset
USB
GigE GigE SD SDIO SD SDIO GPIO UART UART CAN CAN I2C I2C SPI SPI
2x USB 2x GigE 2x SD IRQ
Central Interconnect
MIO
Memory Interfaces
SRAM/ NOR
ONFI 1.0 NAND
Q-SPI CTRL
SWDT
TTC
SystemLevel Control Regs
DMA 8 Channel
Application Processor Unit
FPU and NEON Engine
FPU and NEON Engine
MMU
ARM Cortex-A9 CPU
32 KB I-Cache
32 KB D-Cache
MMU
ARM Cortex-A9 CPU
32 KB I-Cache
32 KB D-Cache
GIC
Snoop Controller, AWDT, Timer
512 KB L2 Cache and Controller
OCM
256 K
Interconnect SRAM
CoreSight Components
Memory Interfaces
DDR2/3, LPDDR2 Controller
DAP DevC
Programmable Logic to Memory Interconnect
EMIO
XADC 12-Bit ADC
General-Purpose Ports
DMA IRQ Sync
Config AES/ SHA
High-Performance Ports
Programmable Logic
Notes: 1) Arrow direction shows control (master to slave) 2) Data flows in both directions: AXI 32-Bit/64-Bit, AXI 64-Bit, AXI 32-Bit, AHB 32-Bit, APB 32-Bit, Custom
ACP
SelectIO Resources
Figure 1-4: Zynq-7000 SoC Block Diagram
UG850_c1_04_062918
For additional information on Zynq-7000 SoC devices, see the Zynq-7000 SoC Data Sheet: Overview (DS190) [Ref 1], and the Zynq-7000 SoC Technical Reference Manual (UG585) [Ref 2] for more information about Zynq-7000 SoC configuration options.
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Feature Descriptions
Device Configuration
Zynq-7000 XC7Z020 SoC uses a multi-stage boot process that supports both a non-secure and a secure boot. The PS is the master of the boot and configuration process. For a secure boot, the PL must be powered on to enable the use of the security block located within the PL, which provides 256-bit AES and SHA decryption/authentication.
The ZC702 board supports these configuration options:
� PS Configuration: Quad SPI flash memory � PS Configuration: Processor System Boot from SD Card (J64) � PL Configuration: USB JTAG configuration port (Digilent module) � PL Configuration: Platform cable header J2 and flying lead header J58 JTAG
configuration ports
TIP: Designs using serial configuration based on Quad-SPI flash memory can take advantage of low-cost commodity SPI flash memory.
The JTAG configuration option is selected by setting SW16 as shown in Table 1-2 and SW10 as described in Programmable Logic JTAG Programming Options for PL configuration details. SW10 is callout 23 in Figure 1-2.
Table 1-2: Switch SW16 Configuration Option Settings
Boot Mode
JTAG mode(1) Independent JTAG mode Quad SPI mode SD mode MIO configuration pin
SW16.1
0 1 0 0 MIO2
SW16.2
0 0 0 0 MIO3
SW16.3
0 0 0 1 MIO4
SW16.4
0 0 1 1 MIO5
SW16.5
0 0 0 0 MIO6
Notes: 1. Default switch setting
Note: For more information about Zynq-7000 SoC configuration settings, see the Zynq-7000 SoC
Technical Reference Manual (UG585) [Ref 2].
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Feature Descriptions
Encryption Key Backup Circuit
The XC7Z020 SoC U1 implements bitstream encryption key technology. The ZC702 board provides the encryption key backup battery circuit shown in Figure 1-5.
X-Ref Target - Figure 1-5
NC
D8 40V 200 mW
1 3
VCCAUX
BAS40-04
To SoC
U1 Pin G9 (VCCBATT)
FPGA_VBATT B1
2 R2 4.70K 1% 1/16
1 +
Lithium Battery Seiko TS518SE_FL35E 1.5V 2
GND
UG850_c1_05_0632719
Figure 1-5: Encryption Key Backup Circuit
The Seiko TS518FE rechargeable 1.5V lithium button-type battery B1 is soldered to the board with the positive output connected to the XC7Z020 SoC U1 VCCBATT pin G9. The battery supply current IBATT specification is 150 nA maximum when board power is off. B1 is charged from the VCCAUX 1.8V rail through a series diode with a typical forward voltage drop of 0.38V and 4.7 K current limit resistor. The nominal charging voltage is 1.42V.
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Feature Descriptions
I/O Voltage Rails
There are four PL I/O banks available on the XC7Z020 SoC. The voltages applied to the XC7Z020 SoC I/O banks used by the ZC702 board are listed in Table 1-3.
Table 1-3: I/O Voltage Rails
XC7Z020 (U1) Bank
PL Bank 0 PL Bank 13 PL Bank 33 PL Bank 34 PL Bank 35 PS Bank 500 PS Bank 501 PS Bank 502
Net Name
VCC2V5_PL
VADJ(1)
VCCMIO_PS VCC1V5_PS
Voltage
2.5V
2.5V
1.8V 1.5V
Notes: 1. The ZC702 board is shipped with VADJ set to 2.5V.
Connected To
SoC Configuration Bank 0 FMC2, GPIO, PL_PJTAG, IIC_MAIN FMC2, HDMI Codec FMC1, HDMI Codec FMC1, HDMI Codec, XADC_GPIO, GPIO Quad-SPI flash memory, misc Ethernet PHY, USB ULPI Transceiver, SDIO, CAN PS_DDR3 MEM
DDR3 Component Memory
[Figure 1-2, callout 2]
The 1 GB, 32-bit wide DDR3 memory system is comprised of four SDRAMs at U66�U69. This memory system is connected to the XC7Z020 SoC processing system (PS) memory interface bank 502.
Component Memory Details
� Part number: MT41J256M8HX-15E (Micron Technology) � Configuration: 2Gb: 256 Mb x 8 � Supply voltage: 1.5V � Datapath width: 32 bits � Data rate: Up to 1,333 MT/s
The ZC702 XC7Z020 SoC PS DDR bank 502 interface performance is documented in the Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020): DC and AC Switching Characteristics (DS187) data sheet [Ref 3].
The DDR3 0.75V VTT termination voltage is sourced from linear regulator U22.
The connections between the DDR3 component memory and XC7Z045 SoC bank 502 are listed in Table 1-4.
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Feature Descriptions
Table 1-4: DDR3 Component Memory Connections to the XC7Z020 SoC
XC7Z020 (U1) Pin
Net Name
Component Memory
Pin Number
Pin Name
E3
PS_DDR3_DQ0
B3
C3
PS_DDR3_DQ1
C7
F2
PS_DDR3_DQ2
C2
D1
PS_DDR3_DQ3
C8
F1
PS_DDR3_DQ4
E3
E1
PS_DDR3_DQ5
E8
B2
PS_DDR3_DQ6
D2
D3
PS_DDR3_DQ7
E7
G2
PS_DDR3_DQ8
B3
L1
PS_DDR3_DQ9
C7
G1
PS_DDR3_DQ10
C2
K1
PS_DDR3_DQ11
C8
L3
PS_DDR3_DQ12
E3
L2
PS_DDR3_DQ13
E8
J1
PS_DDR3_DQ14
D2
K3
PS_DDR3_DQ15
E7
M1
PS_DDR3_DQ16
B3
T3
PS_DDR3_DQ17
C7
N3
PS_DDR3_DQ18
C2
T1
PS_DDR3_DQ19
C8
R3
PS_DDR3_DQ20
E3
T2
PS_DDR3_DQ21
E8
M2
PS_DDR3_DQ22
D2
R1
PS_DDR3_DQ23
E7
U1
PS_DDR3_DQ24
B3
AA1
PS_DDR3_DQ25
C7
U2
PS_DDR3_DQ26
C2
AA3
PS_DDR3_DQ27
C8
W1
PS_DDR3_DQ28
E3
Y3
PS_DDR3_DQ29
E8
W3
PS_DDR3_DQ30
D2
Y1
PS_DDR3_DQ31
E7
B1
PS_DDR3_DM0
B7
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM0
Reference Designator
U66 U66 U66 U66 U66 U66 U66 U66 U67 U67 U67 U67 U67 U67 U67 U67 U68 U68 U68 U68 U68 U68 U68 U68 U69 U69 U69 U69 U69 U69 U69 U69 U66
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Feature Descriptions
Table 1-4: DDR3 Component Memory Connections to the XC7Z020 SoC (Cont'd)
XC7Z020 (U1) Pin
Net Name
C2
PS_DDR3_DQS0_P
D2
PS_DDR3_DQS0_N
H3
PS_DDR3_DM1
H2
PS_DDR3_DQS1_P
J2
PS_DDR3_DQS1_N
P1
PS_DDR3_DM2
N2
PS_DDR3_DQS2_P
P2
PS_DDR3_DQS2_N
AA2
PS_DDR3_DM3
V2
PS_DDR3_DQS3_P
W2
PS_DDR3_DQS3_N
M4
PS_DDR3_A0
M5
PS_DDR3_A1
K4
PS_DDR3_A2
L4
PS_DDR3_A3
K6
PS_DDR3_A4
K5
PS_DDR3_A5
J7
PS_DDR3_A6
J6
PS_DDR3_A7
J5
PS_DDR3_A8
H5
PS_DDR3_A9
J3
PS_DDR3_A10
G5
PS_DDR3_A11
H4
PS_DDR3_A12
F4
PS_DDR3_A13
G4
PS_DDR3_A14
L7
PS_DDR3_BA0
L6
PS_DDR3_BA1
M6
PS_DDR3_BA2
N4
PS_DDR3_CLK_P
N5
PS_DDR3_CLK_N
V3
PS_DDR3_CKE
R4
PS_DDR3_WE_B
Pin Number
C3 D3 B7 C3 D3 B7 C3 D3 B7 C3 D3 K3 L7 L3 K2 L8 L2 M8 M2 N8 M3 H7 M7 K7 N3 N7 J2 K8 J3 F7 G7 G9 H3
Component Memory
Pin Name
Reference Designator
DQS0_P
U66
DQS0_N
U66
DM1
U67
DQS1_P
U67
DQS1_N
U67
DM2
U68
DQS2_P
U68
DQS2_N
U68
DM3
U69
DQS3_P
U69
DQS3_N
U69
A0
U66, U67, U68, U69
A1
U66, U67, U68, U69
A2
U66, U67, U68, U69
A3
U66, U67, U68, U69
A4
U66, U67, U68, U69
A5
U66, U67, U68, U69
A6
U66, U67, U68, U69
A7
U66, U67, U68, U69
A8
U66, U67, U68, U69
A9
U66, U67, U68, U69
A10
U66, U67, U68, U69
A11
U66, U67, U68, U69
A12
U66, U67, U68, U69
A13
U66, U67, U68, U69
A14
U66, U67, U68, U69
BA0
U66, U67, U68, U69
BA1
U66, U67, U68, U69
BA2
U66, U67, U68, U69
CK
U66, U67, U68, U69
CK_B
U66, U67, U68, U69
CKE
U66, U67, U68, U69
WE_B
U66, U67, U68, U69
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Feature Descriptions
Table 1-4: DDR3 Component Memory Connections to the XC7Z020 SoC (Cont'd)
XC7Z020 (U1) Pin
Net Name
P3
PS_DDR3_CAS_B
R5
PS_DDR3_RAS_B
F3
PS_DDR3_RESET_B
P6
PS_DDR3_CS_B
P5
PS_DDR3_ODT
M7
PS_VRN
N7
PS_VRP
H7
VTTVREF_PS
P7
VTTVREF_PS
Pin Number
G3 F3 N2 H2 G1
Component Memory
Pin Name
Reference Designator
CAS_B
U66, U67, U68, U69
RAS_B
U66, U67, U68, U69
RESET_B
U66, U67, U68, U69
CS_B
U66, U67, U68, U69
ODT
U66, U67, U68, U69
Note: The ZC702 DDR3 4x 8-bit component memory interface adheres to the constraints guidelines
documented in the DDR3 Design Guidelines section of the 7 Series FPGAs Memory Interface Solutions v1.8 User Guide (UG586) [Ref 4]. The ZC702 DDR3 memory interface is a 40 impedance implementation. Other memory interface details are available in UG586 and the 7 Series FPGAs Memory Resources User Guide (UG473) [Ref 5]. For more details, see the Micron MT41J256M8HX-15E data sheet at the Micron website [Ref 14].
Quad-SPI Flash Memory
[Figure 1-2, callout 3]
The Quad-SPI flash memory located at U41 provides 128 Mb of non-volatile storage that can be used for configuration and data storage.
� Part number: N25Q128A11ESF40G (Micron) � Supply voltage: 1.8V � Datapath width: 4 bits � Data rate: Various depending on Single/Dual/Quad mode
The connections between the SPI flash memory and the XC7Z020 SoC are listed in Table 1-5.
Table 1-5: Quad SPI Flash Memory Connections to the XC7Z020 SoC
XC7Z020 (U1)
Schematic Quad-SPI Flash Memory (U41) MIO Select
Pin Name
Bank Pin Number Net Name Pin Number Pin Name
Header
PS_MIO6
500
A4
QSPI_CLK
16
C
J26.2
PS_MIO5
500
A3
QSPI_IO3
1
DQ3_HOLD_B
J25.2
PS_MIO4
500
E4
QSPI_IO2
9
WP_B
J22.2
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Feature Descriptions
Table 1-5: Quad SPI Flash Memory Connections to the XC7Z020 SoC (Cont'd)
Pin Name
PS_MIO3 PS_MIO2 PS_MIO1
XC7Z020 (U1)
Bank
500
Pin Number
F6
500
A2
500
A1
Schematic Net Name
QSPI_IO1 QSPI_IO0 QSPI_CS_B
Quad-SPI Flash Memory (U41) MIO Select
Pin Number Pin Name
Header
8
DQ1
J20.2
15
DQ0
J21.2
7
S_B
NA
Notes: Each three-pin MIO select header has pin 1 wired to VCCMIO and pin 3 wired to GND.
The configuration and Quad SPI section of the Zynq-7000 SoC Technical Reference Manual (UG585) [Ref 2] provides details on using the Quad-SPI flash memory.
Figure 1-6 shows the connections of the linear Quad SPI flash memory on the ZC702 board. For more details, see the Micron N25Q128A11ESF40G data sheet at the Micron website [Ref 14].
X-Ref Target - Figure 1-6
VCCMIO
R324 330 5%
QSPI_IO3
C23 0.1F 25V
X5R
GND
QSPI_CS_B
QSPI_IO1
U41
N25Q128A11ESF40G
128 Mb Serial
Flash Memory
1 HOLD_B/DQ3
C 16
2 VCC
DQ0 15
3 NC0
NC7 14
4 NC1
NC6 13
5 NC2
NC5 12
6 NC3
NC4 11
7 SB
VSS 10
8 DQ1
WB/VPP/DQ2 9
QSPI_CLK QSPI_IO0
QSPI_IO2
GND
UG850_c1_06_032719
Figure 1-6: 128 Mb Quad-SPI Flash Memory (U41)
USB 2.0 ULPI Transceiver
[Figure 1-2, callout 4]
The ZC702 board uses a Standard Microsystems Corporation USB3320 USB 2.0 ULPI Transceiver at U9 to support a USB connection to the host computer. A USB cable is supplied in the ZC702 Evaluation Kit (Standard-A connector to host computer, Mini-B connector to ZC702 board connector J1). The USB3320 is a high-speed USB 2.0 PHY supporting the UTMI+ low pin interface (ULPI) interface standard. The ULPI standard defines the interface between the USB controller IP and the PHY device which drives the physical USB bus. Use of the ULPI standard reduces the interface pin count between the USB controller IP and the PHY device.
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Feature Descriptions
The USB3320 is clocked by a 24 MHz crystal. Consult the Standard Microsystems Corporation (SMSC) USB3320 data sheet for clocking mode details [Ref 15].
The interface to the USB3320 transceiver is implemented through the IP in the XC7Z020 SoC Processor System.
Table 1-6 describes the jumper settings for the USB 2.0 circuit. Bold text identifies the default shunt positions for USB 2.0 high speed on-the-go (OTG) mode.
Table 1-6: USB Jumper Settings
Header Function
J44
USB PHY reset
J7
VBUS 5V
supply
J33
RVBUS select
J35
CVBUS select
J34
Cable ID select
J36
USB Micro-B
Shunt Position
Notes
Shunt ON = USB PHY reset
Clean reset requires external
Shunt OFF = USB PHY normal operation debouncing
Shunt ON = Host or OTG mode Shunt OFF = Device mode
Position 1�2 = Device mode (10 k) Position 2�3 = OTG mode (1 k)
Overvoltage protection
Position 1-2 = OTG and Device mode (1 F) VBUS load capacitance Position 2-3 = Host mode (120 F)
Position 1-2 = A/B cable detect Position 2-3 = ID not used
Used in OTG mode.
Position 1-2 = Shield connected to GND Position 2-3 = Shield floating
The connections between the USB Mini-B connector at J1 and the PHY at U9 are listed in Table 1-7.
Table 1-7: USB Connector Pin Assignments and Signal Definitions Between J1 and U9
USB Connector J1
Pin Name
1
VBUS
Net Name
USB_VBUS_SEL
Description
+5V from host system
2
D_N
USB_D_N
Bidirectional differential serial data (N-side)
3
D_P
USB_D_P
Bidirectional differential serial data (P-side)
5
GND
GND
Signal ground
USB3320 (U9) Pin
22 19 18 33
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The connections between the USB 2.0 PHY at U9 and the XC7Z020 SoC are listed in Table 1-8.
Table 1-8: USB 2.0 ULPI Transceiver Connections to the XC7Z020 SoC
Pin Name
XC7Z020 (U1)
Bank
Pin Number
Schematic Net Name
PS_MIO36
501
A9
PS_MIO31
501
F9
PS_MIO32
501
C7
PS_MIO33
501
G13
PS_MIO34
501
B12
USB_CLKOUT USB_NXT
USB_DATA0 USB_DATA1 USB_DATA2
PS_MIO35
501
F14
USB_DATA3
PS_MIO28
501
A12
USB_DATA4
PS_MIO37
501
B14
USB_DATA5
PS_MIO38
501
F13
USB_DATA6
PS_MIO39
501
C13
USB_DATA7
PS_MIO30
501
A11
USB_STP
PS_MIO29
501
E8
USB_DIR
PS_MIO7
500
D5
USB_RESET_B_AND
USB3320 (U9) Pin
1 2 3 4 5 6 7 9 10 13 29 31 27 (through AND gate U62)
Figure 1-7 shows the USB 2.0 ULPI Transceiver circuitry. Note that the shield for the USB Mini-B connector (J1) can be tied to GND by a jumper on header J36 pins 1�2 (default). The USB shield can optionally be connected through a capacitor to GND by installing a capacitor (body size 0402) at location C202 and jumping pins 2-3 on header J36.
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X-Ref Target - Figure 1-7
8 USB_CLKOUT 8 USB_NXT 8 USB_DATA0 8 USB_DATA1 8 USB_DATA2 8 USB_DATA3 8 USB_DATA4
2 PLACES VCCMIO
C53
C54
C56 1 1 1
0.1F
25V 2
2
2
3 PLACES
GND USB3320_QFN32
1 CLKOUT_1 2 NXT_2 3 DATA0_3 4 DATA1_4 5 DATA2_5 6 DATA3_6 7 DATA4_7 8 REFSEL0_8
U9
VCCMIO
8 USB_DATA5 USB_DATA6
8 USB_DATA7
8
9 DATA5_9 10 DATA6_10 11 REFSEL1_11 NC 12 NC_12 13 DATA7_13 14 REFSEL2_14 NC 15 SPK_L_15 NC 16 SPK_R_16
VDDIO_32 32 DIR_31 31
VDD18_30 30 STP_29 29
VDD18_28 28 RESETB_27 27 REFCLK_26 26
XO_25 25
USB_DIR 8 USB_STP 8 USB_RESET_B 27
Feature Descriptions
1 R140 8.06K 1/10 2 1% 1 2 3
X2
C334 1
R295 1
18PF 50V
2
1.0M
NPO
1/10
5% 2
GND
12 24.000MHZ
1 C335
18PF
2
50V
NPO
GND
RBIAS_23 24 ID_23 23
VBUS_22 22 VBAT_21 21 VDD33_P 20
DM_19 19 DP_18 18 CPEN33_17 17
USB_ID 27
GND
USB_D_N USB_D_P
USB_VDD33 27
27 27 1
2
C137
2.2F 6.3V
33 CTR_GND_33
GND
VCC5V0
1 C413
0.1F
2
25V
GND
USB_VBUS_SEL
USB3320_QFN32 GND
R185 1
10.0K 1/10
2
1 R249
1.00K 2 1/16
USB_VBUS_SEL
L10
FERRITE-220
1
2
C270 1
1
5.6F
10V
2
2
1
2
FERRITE-220
L11
GND
J35 1 2 3
1 C414
1F
2
16V
X5R
CVBUS Select:
1-2: OTG Mode
GND
2-3: Host Mode
C303
1
120F
20V
2
TANT
GND
C5727
0.1F 27 25V
USB_D_N USB_D_P
SHLD1 6
SHLD2 7
SHLD3 8
SHLD4 9
ZX62D_AB_5P8 1
VBUS 2
D_N 3
D_P 4
ID 5
GND
J1
11 SHLD6
10 SHLD5
2
J34
1
2 USB_ID 27 GND 3 USB_VDD33 27
1
J36
1-2 = A/B CABLE DETECT 2-3 = ID NOT USED
VCC3V3
R280 1
261 1/10
2
DS5
2
1
LED-RED-SMT
J33
1-2 = DEVICE MODE 2-3 = HOST OR OTG MODE
J7
1
ON = HOST OR OTG MODE
2
OFF = DEVICE MODE
USB HOST POWER
MIC2025_SOP8
NC
1 2 3 4
EN FLG GND NC1
OUT2 IN
OUT1 NC2
8 7 6 5
NC
U13
GND
SOP127P500X600_8
VCC5V0
1 C58 1
0.1F
2
25V 2
C293
150F 10V
TANT
GND
GND
3
1
C202
2
DNP
GND
UG850_c1_07_032719
Figure 1-7: USB 2.0 ULPI Transceiver
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SD Card Interface
[Figure 1-2, callout 5]
The ZC702 board includes a secure digital input/output (SDIO) interface to provide user-logic access to general purpose nonvolatile SDIO memory cards and peripherals. Information for the SD I/O card specification can be found at the SanDisk Corporation [Ref 16] or SD Association [Ref 17] websites.
The SDIO signals are connected to XC7Z020 SoC PS bank 501 which has its VCCMIO set to 1.8V. A TXB02612 SDIO port expander with voltage-level translation (U61) is used between the XC7Z020 SoC and the SD card connector (J64).
Figure 1-8 shows the connections of the SD card interface on the ZC702 board.
X-Ref Target - Figure 1-8
VCCMIO_PS
VCC3V3
1 R381 1 R380
4.7K
4.7K
1/10 1/10 2 5% 2 5%
1 R321
4.7K 1/10 2 5%
1
C27
0.1F
2
25V
X5R
GND
22 SDIO_CD_DAT3 22 SDIO_CMD
22 SDIO_CLK
22 SDIO_DAT0
22 SDIO_DAT1
22
SDIO_DAT2
8
SDIO_SDDET
8
SDIO_SDWP
67840-8001
1 2 3 4 5 6 7 8 9
10 11 12
CD_DAT3
CMD
VSS1
VDD
CLK
VSS2
DAT0
DAT1
IOGND2
DAT2
IOGND1
GNDTAB4
DETECT
GNDTAB3
PROTECT
GNDTAB2
DETECT_PROTECT GNDTAB1
18 17 16 15 14 13
J64 GND
GND
UG850_c1_08_032719
Figure 1-8: SD Card Interface
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Table 1-9 lists the SD card interface connections to the XC7Z020 SoC.
Table 1-9: SDIO Connections to the XC7Z020 SoC
XC7Z020 (U1) Pin
Pin Name
PS_MIO15
Bank
500
Pin Number
E6
Schematic Net Name
SDIO_SDWP
PS_MIO0
500
G6
SDIO_SDDET
PS_MIO41
501
C8
SDIO_CMD_LS
PS_MIO40
501
PS_MIO42
501
PS_MIO45
501
PS_MIO44
501
PS_MIO43
501
E14
SDIO_CLK_LS
D8
SDIO_DAT2_LS
B9
SDIO_DAT1_LS
E13
SDIO_DAT0_LS
B11
SDIO_CD_DAT3_LS
Level Shifter (U61)
(A) Pin Number
N/A
(B) Pin Number
N/A
N/A
N/A
4
20
9
19
1
23
7
16
6
18
3
22
SDIO Connector (J64)
Pin Number
11
Pin Name
PROTECT
10
DETECT
2
CMD
5
CLK
9
DAT2
8
DAT1
7
DAT0
1
CD_DAT3
Programmable Logic JTAG Programming Options
[Figure 1-2, callout 6] The ZC702 board JTAG chain is shown in Figure 1-9.
X-Ref Target - Figure 1-9
J2
JTAG Header
TDO TDI
U23
JTAG Module
TDO TDI
J58
JTAG Header
TDO TDI
U75 U76 U77
3:1 Analog Switch
SPST Bus Switch U25
SPST Bus Switch U26
N.C. J3
FMC LPC Connector
TDI TDO
N.C. J4
FMC LPC Connector
TDI TDO
3.3V 2.5V
U39 SN74AVC1T45
Voltage Translator TDI TDO
U38 SN74AVC1T45
Voltage Translator
TDO TDI
Figure 1-9: JTAG Chain Block Diagram
U1 Zynq-7000 XC7Z020 SoC TDI TDO
UG850_c1_09_062918
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Feature Descriptions
Programmable Logic JTAG Select Switch, JTAG Cable Connector
[Figure 1-2, callout 23]
The JTAG chain can be programmed by three different methods made available through a 3-to-1 analog switch (U75, U76, and U77) controlled by a 2-position DIP switch at SW10.
Figure 1-10 shows the JTAG analog switches and DIP switch SW10.
X-Ref Target - Figure 1-10
VCC3V3
To J2 Parallel Cable or Platform Cable
(14 pins)
To U23 USB-to-JTAG Digilent bridge
To J58 Parallel Cable
(20 Pins)
14PIN_JTAG_TDI 14PIN_JTAG_TMS 14PIN_JTAG_TCK
DIGILENT_TDI DIGILENT_TMS DIGILENT_TCK
20PIN_JTAG_TDI 20PIN_JTAG_TMS 20PIN_JTAG_TCK
U75
TS5A3359 SP3T
ANALOG SWITCH
IN1
6
IN2
5
1 NO0
2 NO1
COM 7
3 NO2
4 GND
V+ 8
U76
TS5A3359 SP3T
ANALOG SWITCH
IN1
6
IN2
5
1 NO0
2 NO1
COM 7
3 NO2
4 GND
V+ 8
VCC3V3
43
SW10 SDA02H1SBD
JTAG_SEL_1 JTAG_SEL_2
R375 4.7k 0.1 5%
R376 4.7k 0.1 5%
12
GND
U77
TS5A3359
SP3T
ANALOG SWITCH
IN2
6
IN1
5
1 NO0
2 NO1 3 NO2
COM 7
4 GND
V+ 8
JTAG_TDI JTAG_TMS JTAG_TCK
Figure 1-10: PL JTAG Programming Source Analog Switch
UG850_c1_10_032719
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Feature Descriptions
DIP switch SW10[1:2] setting 10 selects the 14-pin header J2 for configuration using either a Parallel Cable IV (PC4) or Platform Cable USB II. DIP switch SW10 setting 01 selects the USB-to-JTAG Digilent bridge U23 for configuration over a Standard-A to Micro-B USB cable. DIP switch SW10 setting 11 selects the JTAG 20-pin header at J58. The four JTAG signals TDI, TDO, TCK, and TMS would be connected to J58 through flying leads from a JTAG cable. The 3-to-1 analog switch settings are shown in Table 1-10.
Table 1-10: Switch SW10 JTAG Configuration Option Settings
Configuration Source
None Digilent USB-to-JTAG interface U23 Cable connector J2(2) JTAG header J58
DIP Switch SW10[1:2]
Switch 1(1) JTAG_SEL_1
Switch 2(1) JTAG_SEL_2
0
0
0
1
1
0
1
1
Notes: 1. 0 = open, 1 = closed 2. Default switch setting
FMC Connector JTAG Bypass
When an FPGA mezzanine card (FMC) is attached to J3 or J4 it is automatically added to the JTAG chain through electronically controlled single-pole single-throw (SPST) switches U25 and U26. The SPST switches are normally closed and transition to an open state when an FMC is attached. Switch U25 adds an attached FMC to the JTAG chain as determined by the FMC1_HPC_PRSNT_M2C_B signal. Switch U26 adds an attached FMC to the JTAG chain as determined by the FMC2_LPC_PRSNT_M2C_B signal The attached FMC card must implement a TDI-to-TDO connection using a device or bypass jumper to ensure that the JTAG chain connects to the XC7Z020 SoC.
Clock Generation
The ZC702 board provides three clock sources for the XC7Z020 SoC. Table 1-11 lists the source devices for each clock.
Table 1-11: ZC702 Board Clock Sources
Clock Name
System Clock
Clock Source
U43
Description
SiT9102 2.5V LVDS 200 MHz fixed-frequency oscillator (SiTime). See System Clock.
User Clock PS Clock
U28
Si570 3.3V LVDS I2C programmable oscillator, 156.250 MHz default (Silicon Labs). See Programmable User Clock.
U65
SIT8103 1.8V single-ended CMOS 33.3333 MHz fixed frequency oscillator (SiTime). See Processing System Clock Source.
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Table 1-12 lists the pin-to-pin connections from each clock source to the XC7Z020 SoC.
Table 1-12: Clock Connections, Source to XC7Z020 SoC
Clock Reference Pin
5 U43
4
5 U28
4
U65
3
Net Name
SYSCLK_N SYSCLK_P USRCLK_N USRCLK_P
PS_CLK
I/O Standard
LVDS_25 LVDS_25 LVDS_25 LVDS_25
NA
XC7Z020 (U1) Pin
C19 D18 Y8 Y9 F7 (Bank 500)
System Clock
[Figure 1-2, callout 7]
The system clock source is an LVDS 200 MHz oscillator at U43. It is wired to a multi-region clock capable (MRCC) input on programmable logic (PL) bank 35. The signal pair is named SYSCLK_P and SYSCLK_N and each signal is connected to U1 pins D18 and C19 respectively on the XC7Z020 SoC.
� Oscillator: SiTime SiT9102AI-243N25E200.00000 (200 MHz) � Frequency Tolerance: 50 ppm � Differential Output
For more details, see the SiTime SiT9102 data sheet [Ref 18]. The system clock circuit is shown in Figure 1-11.
X-Ref Target - Figure 1-11
C71 0.1 F 10V X5R
VCC2V5
U43
SIT9102 200 MHz Oscillator
1 OE
VCC 6
2 NC OUT_B 5
3 GND OUT 4
R168 100 1%
SYSCLK_N SYSCLK_P
GND
Figure 1-11: System Clock Source
UG850_c1_11_030513
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Feature Descriptions
Programmable User Clock
[Figure 1-2, callout 8]
The ZC702 board has a programmable low-jitter 3.3V LVDS differential oscillator (U28) connected to the MRCC inputs of bank 13. This USRCLK_P and USRCLK_N clock signal pair is connected to XC7Z020 SoC U1 pins Y9 and Y8 respectively. On power-up the user clock defaults to an output frequency of 156.250 MHz. User applications can change the output frequency within the range of 10 MHz to 810 MHz through an I2C interface. Power cycling the ZC702 board reverts the user clock to the default frequency of 156.250 MHz.
� Programmable Oscillator: Silicon Labs Si570BAB0000544DG (10 MHz�810 MHz)
� LVDS Differential Output
The user clock circuit is shown in Figure 1-12.
X-Ref Target - Figure 1-12
VCC3V3
U28 R20
4.7K 5%
Si570
Programmable
Oscillator
1 NC 2 OE
VDD 6
USRCLK SDA USR CLK SCL
7 SDA
8 SCL
3 GND
CLK- 5 CLK+ 4
VCC3V3
C216 0.01 F 25V X7R
GND
R417 100 1%
USRCLK N USRCLK P
GND
UG850_c1_12_030513
Figure 1-12: User Clock Source
The Silicon Labs Si570 data sheet is available on the Silicon Labs website [Ref 19].
Processing System Clock Source
[Figure 1-2, callout 8]
The Processing System (PS) clock source is a 1.8V LVCMOS single-ended fixed 33.33333 MHz oscillator at U65. It is wired to PS bank 500, pin F7 (PS_CLK), on the XC7Z020 SoC.
� Oscillator: SiTime SiT8103AC-23-18E-33.33333 (33.3 MHz) � Frequency Tolerance: 50 ppm � Single-ended output
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Feature Descriptions
For more details, see the SiTime SiT8103 data sheet [Ref 18]. The system clock circuit is shown in Figure 1-13.
X-Ref Target - Figure 1-13
VCC1V8
R322 4.7K 5%
U65
SiT8103
MEMS Clock
Oscillator
33.33333 MHz
1 OE
VDD 4
2 GND OUT 3
VCC1V8
C449 0.01 F 25V X7R
GND
R403 24.9 1%
PS CLK
GND
UG850_c1_13_030513
Figure 1-13: Processing System Clock Source
10/100/1000 MHz Tri-Speed Ethernet PHY
[Figure 1-2, callout 9]
The ZC702 board uses the Marvell Alaska PHY device (88E1116R) at U35 for Ethernet communications at 10 Mb/s, 100 Mb/s, or 1000 Mb/s. The board supports RGMII mode only. The PHY connection to a user-provided Ethernet cable is through a Halo HFJ11-1G01E RJ-45 connector (P2) with built-in magnetics.
On power-up, or on reset, the PHY is configured to operate in RGMII mode with PHY address 0b00111 using the settings shown in Table 1-13. These settings can be overwritten using software commands passed over the MDIO interface.
Table 1-13: Board Connections for PHY Configuration Pins
U35 Pin
CONFIG0 CONFIG1
CONFIG2
Setting
VCCO_MIO1 EPHY_LED0
GND EPHY_LED0
Configuration
PHYAD[1]=1 PHYAD[0]=1
PHYAD[3]=0 PHYAD[2]=1
ENA_XC=0
PHYAD[4]=0
ENA_XC=0
PHYAD[4]=1
VCCO_MIO1
ENA_XC=1
PHYAD[4]=1
GND
RGMII_TX=0 RGMII_RX=0
CONFIG3
EPHY_LED0 EPHY_LED1
RGMII_TX=0 RGMII_TX=1
RGMII_RX=1 RGMII_RX=0
VCCO_MIO1 RGMII_TX=1 RGMII_RX=1
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Feature Descriptions
The Ethernet connections from the XC7Z020 SoC at U1 to the 88E1116R PHY device at U35 are listed in Table 1-14.
Table 1-14: Ethernet Connections, XC7Z020 SoC to the PHY Device
XC7Z020 (U1) Pin
Pin Name
Bank
Pin Number
Schematic Net Name
M88E1116R PHY U35
Pin
Name
PS_MIO53
501
C12
PHY_MDIO
45
MDIO
PS_MIO52
501
PS_MIO16
501
PS_MIO21
501
PS_MIO20
501
PS_MIO19
501
D10
PHY_MDC
48
D6
PHY_TX_CLK
60
F11
PHY_TX_CTRL
63
A8
PHY_TXD3
62
E10
PHY_TXD2
61
MDC TX_CLK TX_CTRL TXD3 TXD2
PS_MIO18
501
A7
PHY_TXD1
59
TXD1
PS_MIO17
501
E9
PHY_TXD0
58
TXD0
PS_MIO22
501
A14
PHY_RX_CLK
53
RX_CLK
PS_MIO27
501
D7
PHY_RX_CTRL
49
RX_CTRL
PS_MIO26
501
A13
PHY_RXD3
55
RXD3
PS_MIO25
501
F12
PHY_RXD2
54
RXD2
PS_MIO24
501
B7
PHY_RXD1
51
RXD1
PS_MIO23
501
E11
PHY_RXD0
50
RXD0
Ethernet PHY Clock Source
[Figure 1-2, callout 10]
A 25.00 MHz 50 ppm crystal at X1 is the clock source for the 88E1116R PHY at U35. Figure 1-14 shows the clock source.
X-Ref Target - Figure 1-14
C322 18pF 50V NPO
R246 DNP C333 18pF 50V NPO
X1 25.00 MHz
3
4
2
1
PHY XTAL OUT PHY XTAL IN
GND
UG850_c1_14_030513
Figure 1-14: Ethernet PHY Clock Source
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Feature Descriptions
The data sheet can be obtained under NDA with Marvell. The Marvell site includes contact information [Ref 20],
USB-to-UART Bridge
[Figure 1-2, callout 12]
The ZC702 board contains a Silicon Labs CP2103GM USB-to-UART bridge device (U36) which allows a connection to a host computer with a USB port. The USB cable is supplied in the ZC702 Evaluation Kit (Standard-A end to host computer, Type Mini-B end to ZC702 board connector J17). The CP2103GM is powered by the USB 5V provided by the host PC when the USB cable is plugged into the USB port on the ZC702 board.
The CP2013GM TX and RX pins are wired to the UART_1 IP block within the XC7Z020 SoC PS I/O Peripherals set. The XC7Z020 SoC supports the USB-to-UART bridge using two signal pins: Transmit (TX) and Receive (RX).
Silicon Labs provides royalty-free Virtual COM Port (VCP) drivers for the host computer. These drivers permit the CP2103GM USB-to-UART bridge to appear as a COM port to communications application software (for example, TeraTerm or HyperTerm) that runs on the host computer.
IMPORTANT: The VCP device drivers must be installed on the host PC prior to establishing communications with the ZC702 board.
The USB Connector pin assignments and signal definitions between J17 and U36 are listed in Table 1-15.
Table 1-15: USB Connector J17 Pin Assignments and Signal Definitions
USB Connector (J17)
Pin
Name
Net Name
Description
1 VBUS
USB_UART_VBUS +5V VBUS Powered
2 D_N 3 D_P
USB_UART_D_N USB_UART_D_P
Bidirectional differential serial data (N-side) Bidirectional differential serial data (P-side)
5 GND
USB_UART_GND
Signal ground
CP2103GM (U36)
Pin Name
7 REGIN 8 VBUS 4 D� 3 D+ 2 GND1 29 CNR_GND
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Table 1-16 lists the USB connections between the XC7Z020 SoC PS Bank 501 and the CP2103 UART bridge.
Table 1-16: XC7Z020 SoC to CP2103 Connections
XC7Z020 SoC (U1) Bank 500
Pin Name Pin Number Function Direction
PS_MIO48
D11
PS_MIO49
C14
TX
Data Out
RX
Data In
Net Name
USB_UART_RX USB_UART_TX
CP2103GM Device (U36)
Pin Function Direction
24
RXD
Data In
25
TXD
Data Out
Refer to the Silicon Labs website for technical information on the CP2103GM and the VCP drivers [Ref 19].
HDMI Video Output
[Figure 1-2, callout 13]
The ZC702 board provides a high-definition multimedia interface (HDMI�) video output using an Analog Devices ADV7511KSTZ-P HDMI transmitter at U40. The HDMI output is provided on a Molex 500254-1927 HDMI type-A receptacle at P1. The ADV7511 supports 1080P 60Hz, YCbCr 4:2:2 encoding via 16-bit input data mapping.
The ZC702 board supports the following HDMI device interfaces:
� 16 data lines � Independent VSYNC, HSYNC � Single-ended input CLK � Interrupt Out pin to XC7Z020 SoC � I2C � SPDIF
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Figure 1-15 shows the HDMI codec circuit.
X-Ref Target - Figure 1-15
VCC3V3
VADJ
R109 2.43K 1/10 1%
HDMI_INT
IIC_SCL_HDMI IIC_SDA_HDMI HDMI_VSYNC HDMI_HSYNC
HDMI_CLK
HDMI_HEAC_C_N
1 R105
2.43K 1/10 1%
To U1 SoC
HDMI_D15 HDMI_D14 HDMI_D13 HDMI_D12 HDMI_D11 HDMI_D10 HDMI_D9 HDMI_D8 HDMI_D7 HDMI_D6 HDMI_D5 HDMI_D4 HDMI_D3 HDMI_D2 HDMI_D1 HDMI_D0
HDMI_DE HDMI_SPDIF
R110
2.43K
1/102719 U40
1%
ADV7511
45 38 55 56
2 98
INT PD SCL SDA
VSYNC HSYNC
CEC_CLK SPDIF_OUT
50 46
HDMI_SPDIF_OUT
R402 24.9
79 CLK
30 HPD
HDMI_PLVDD HDMI_AVDD
57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 78 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96
D35 D34 D33 D32 D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
97 DE
10 SPDIF
PVDD1 PVDD2 PVDD3
21 24 25
AVDD1 AVDD2 AVDD3
29 34 41
DVDD1 DVDD2 DVDD3 DVDD4 DVDD5
76
77
49 19 1
DVDD_3V 47
BGVDD 26
TX0_P TX0_N TX1_P TX1_N TX2_P TX2_N TXC_P TXC_N
36 35 40 39 43 42 33 32
DDCSDA
54 53
DDCSCL
3 4 5 6 7 8 9
DSD0 DSD1 DSD2 DSD3 DSD4 DSD5 DSD_CLK
HEAC_P HEAC_N
52 51
CEC 48
11 MCLK
12 13 14 15 16 17
I2S0 I2S1 I2S2 I2S3 SCLK LRCLK
28 R_EXT
R107 887
GND1 GND2
99 100
GND3 GND4
18 20
GND5 GND6 GND7 GND8 GND9
22 23 27 31 37
GND10 GND11
44 75
HDMI_AVDD
HDMI_DVDD
HDMI_DVDD_3V HDMI_PLVDD
HDMI_D0_P HDMI_D0_N HDMI_D1_P HDMI_D1_N HDMI_D2_P HDMI_D2_N HDMI_CLK_P HDMI_CLK_N HDMI_DDCSDA HDMI_DDCSCL HDMI_HEAC_P HDMI_HEAC_N HDMI_CEC
GND
GND
Figure 1-15: HDMI Codec Circuit
VCC2V5
U31
SIT8102 12.00000 MHz
50PPM
4 VCC
OE 1
3 OUT
GND 2
C78
0.1F 25V X5R
1 2
GND
GND
To HDMI Connector
UG850_c1_15_032719
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Table 1-17 lists the connections between the codec and the XC7Z020 SoC.
Table 1-17: XC7Z020 SoC to HDMI Codec Connections (ADV7511)
XC7Z020 (U1) Pin
Net Name
AB21 AA21 AB22 AA22 V19 V18 V20 U20 W21 W20 W18 T19 U19 R19 T17 T16 T18 R15 L16 H15 R18 U14 H20
HDMI_D0 HDMI_D1 HDMI_D2 HDMI_D3 HDMI_D4 HDMI_D5 HDMI_D6 HDMI_D7 HDMI_D8 HDMI_D9 HDMI_D10 HDMI_D11 HDMI_D12 HDMI_D13 HDMI_D14 HDMI_D15 HDMI_DE HDMI_SPDIF HDMI_CLK HDMI_VSYNC HDMI_HSYNC HDMI_INT HDMI_SPDIF_OUT
I/O Standard
LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25
ADV7511 (U40)
Pin
Name
88
D8
87
D9
86
D10
85
D11
84
D12
83
D13
82
D14
81
D15
80
D16
78
D17
74
D18
73
D19
72
D20
71
D21
70
D22
69
D23
97
DE
10
SPDIF
79
CLK
2
VSYNC
98
HSYNC
45
INT
46
SPDIF_OUT
Table 1-18 lists the connections between the codec and the HDMI receptacle P1.
Table 1-18: ADV7511 to HDMI Receptacle Connections
ADV7511 (U40)
36 35 40 39 43
Net Name
HDMI_D0_P HDMI_D0_N HDMI_D1_P HDMI_D1_N HDMI_D2_P
HDMI Receptacle P1 Pin
7 9 4 6 1
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Table 1-18: ADV7511 to HDMI Receptacle Connections (Cont'd)
ADV7511 (U40)
42
Net Name
HDMI_D2_N
HDMI Receptacle P1 Pin
3
33
HDMI_CLK_P
10
32
HDMI_CLK_N
12
54
HDMI_DDCSDA
16
53
HDMI_DDCSCL
15
52
HDMI_HEAC_P
14
51
HDMI_HEAC_N
19
48
HDMI_CEC
13
Information about the ADV7511KSTZ-P is available on the Analog Devices website [Ref 21].
I2C Bus
[Figure 1-2, callout 14]
The ZC702 board implements a single I2C port on the XC7Z020 SoC (IIC_SDA_MAIN, IIC_SDA_SCL), which is routed through an TI Semiconductor PCA9548 1-to-8 channel I2C bus switch (U44). The bus switch can operate at speeds up to 400 kHz.
The bus switch I2C address is 0x74 (0b1110100) and must be addressed and configured to select the desired downstream device.
The ZC702 board I2C bus topology is shown in Figure 1-16.
X-Ref Target - Figure 1-16
U1 XC7Z020 SoC PL Bank 13 (2.5V)
U1 XC7Z020 SoC
PS Bank 501 (VCCMIO_PS 1.8V)
VADJ 2.5V U56
3.3 V
PCA9517 I2C
Level Shifter
IIC_SCL/SDA_MAIN A
B IIC_SDA/SCL_MAIN
VCCMIO_PS 1.8V U57
3.3 V
PCA9517 I2C
Level Shifter
PS_SDA/SCL_MAIN A
B
U44 PCA9548 12C 1-to-8 Bus Switch
CH0 - USER_CLK_SDL/SCL CH1 - IIC_SDA/SCL_HDMI CH2 - EEPROM_IIC_SDA/SCL CH3 - PORT_EXPANDER_SDA/SCL CH4 - IIC_RTC_SDA/SCL CH5 - FMC1_LPC_IIC_SDA/SCL CH6 - FMC2_LPC_IIC_SDA/SCL CH7 - PMBUS_DATA/CLK
UG850_C1_16_062918
Figure 1-16: I2C Bus Topology
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User applications that communicate with devices on one of the downstream I2C buses must first set up a path to the desired bus through the U44 bus switch at I2C address 0x74 (0b1110100). Table 1-19 lists the address for each bus.
Table 1-19: I2C Bus Addresses
I2C Device
PCA9548 8-channel bus switch Si570 clock ADV7511 HDMI I2C EEPROM I2C port expander I2C real time clock FMC LPC J3 FMC LPC J4 UCD9248 controller PMBUS
I2C Switch Position
NA 0 1 2 3 4 5 6 7
I2C Address
0b1110100 0b1011101 0b0111001 0b1010100 0b0100001 0b1010001 0bxxxxx00 0bxxxxx00 0b01101[ADDR](1)
Notes: 1. This I2C address is the binary equivalent of the TI Power Controller PMBus decimal address 52, 53,
or 54 which corresponds to b00, b01 and b10 in the lower 2 bits.
IMPORTANT: The PCA9548 I2C bus switch U44 pin 24 net IIC_MUX_RESET_B is level-shifted by U81 and is connected to the XCZ020 SoC U1 bank 500 pin A6. This is an active-Low signal and must be driven High to enable I2C bus transactions between the U1 and the other components on the I2C bus.
Information about the PCA9548 is available on the TI Semiconductor website at [Ref 25].
Real-Time Clock
[Figure 1-2, callout 15]
The Epson RTC-8564JE is an 12C bus interface real-time clock that has a built-in 32.768 KHz oscillator with these features
� Frequency output options: 32.768 KHz, 1024 Hz, 32 Hz or 1 Hz � Calendar output functions: Year, month, day, weekday, hour, minute and second � Clock counter, alarm and fixed-cycle timer interrupt functions
Programming information for the RTC-8564JE is available in the RTC-8564JE/NB Application Manual at the Epson Electronics America website [Ref 22].
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Figure 1-17 shows the real-time clock circuit.
X-Ref Target - Figure 1-17
Feature Descriptions
VADJ
VCC3V3
VCC2V5
IIC_RTC_SDA IIC_RTC_SCL IIC_RTC_IRQ_1_B
U16
R187 10.0K
RTC-8564JE
1
0.1
Real Time Clock
Module
7 SDA
6 SCL
10 INT
VCC 16 CLKOE 15 CLKOUT 14
GND 13
J39 YELLOW
D5 BAT54T1G 30V 400 mW
D6 BAT54T1G 30V 400 mW
D7 BAT54T1G 30V 400 mW
C217 2V 0.01F 25V X7R
R249 4.7K
B2 NBL-621/N9D
GND
GND
GND
UG850_c1_17_032719
Figure 1-17: Real Time Clock Circuit
Real-time clock connections to the XC7Z020 SoC and the PCA9548 8-Channel bus switch are listed in Table 1-20.
Table 1-20: Real Time Clock Connections
RTC-8564JE (U16) Pin Net Name
6
IIC_RTC_SCL
7
IIC_RTC_SDA
10
IIC_RTC_IRQ_1_B(1)
Connects To
U44.11 (PCA9548 SC4) U44.10 (PCA9548 SD4) U1.U7 (XC7Z020 SoC PL BANK 13)
Notes: 1. I/O standard = LVCMOS_25.
Information about the RTC-8564JE is available at the Epson Electronics America website [Ref 22].
I/O Expansion Header
[Figure 1-2, callout 16]
The 2 x 6 I/O expansion header J54 supports Digilent Pmod Peripheral Modules. 8 pins (IIC_PMOD[0:7]) are connected to the TI TCA6416APWR I2C expansion port device U80. See the Digilent website for information on Digilent Pmod Peripheral Modules [Ref 23].
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The expansion header circuit is shown in Figure 1-18.
X-Ref Target - Figure 1-18
To U44 PCA95498A 8-Channel I2C
Switch
VCC3V3 U80
C521 0.1F
10V X5R
C502 0.1F
10V X5R
GND
GND
VCC3V3
R363 0
0.1W
R408 4.7k 0.1W
R360 DNP
TCA641APWR 16-Bit I2C and SMBus
I/O Expander
24 VCCP
2 VCCI
P00 4 P01 5 P02 6
P03 7
3 RESET_B
21 ADDR
1 INT_B
P04 8 P05 9 P06 10 P07 11
GND
IIC_PORT_EXPANDER_SDA 23 SDA
IIC_PORT_EXPANDER_SCL 22 SCL 12 GND
P10 13 P11 14
P12 15 P13 16 P14 17
P15 18 P16 19 P17 20
IIC_PMOD_0 IIC_PMOD_1 IIC_PMOD_2 IIC_PMOD_3
GND
I/O Expansion Header
J54
1
2 IIC_PMOD_4
3
4 IIC_PMOD_5
5
5 IIC_PMOD_6
7
8 IIC_PMOD_7
9
10
11
12
VCC3V3
GND
GND
Figure 1-18: I/O Expansion Header Circuit
UG850_c1_18_030513
Information about the TCA641APWR is available at the Texas Instruments website [Ref 25].
High Speed CAN Transceiver
[Figure 1-2, callout 21]
The TJA1040 (U14) is an advanced high speed Controller Area Network (CAN) transceiver for use in automotive and general industrial applications. It supports the differential bus signal representation described in the international standard for in-vehicle high speed CAN applications (ISO 11898).
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Figure 1-19 shows the controller area network (CAN) bus interface.
X-Ref Target - Figure 1-19
VCC5V0 VCCMIO
C25 0.1F
25V X5R
GND
VCCMIO
C26
U3
0.1F 25V X5R
TXS0104E Bidirectional Voltage-Level
GND
1
Translator VCCA VCCB
14
CAN_TXD_LS
2 A1
B1 13
CAN_RXD_LS
3 A2
B2 12
CAN_STB_B_LS 4 A3
B3 11
5 A4
B4 10
6 NC1
NC2 9
7 GND
OE 8
CAN TXD CAN RXD CAN STB B
C24 0.1F 25V
X5R GND
C520 47 F 10V X5R
GND
CAN_CANH
U14
TJA1040
CAN
Transceiver
3 VCC
1 TXD
4 RXD
8 STB
CANH 7
CANL 6 SPLIT 5
GND 2
R282 60.4 5%
GND
C304 4700 pF 25V NPO
GND GND
GND
2
1
C330 J53 18 pF 50V NPO
R281 60.4 5%
GND
CAN Interface
Connector
J52
1
2
3
4
5
5
7
8
9
10
CAN_CANL
1
2
C331 J15 18 pF 50V NPO
GND
Figure 1-19: CAN Bus Interface
UG850_c1_19_031913
Information about the TXS0104E is available at the Texas Instruments website [Ref 25]. Data sheets and application notes for the TJA01040 CAN transceiver are available at the NXP Semiconductors website [Ref 24]. Table 1-21 shows the U14 CAN transceiver to U1 XC7Z020 interface connections through level shifter U3.
Table 1-21: CAN Transceiver SoC Connections
TJA1040 (U14)
TXS0104E Level Shifter (U3)
XC7Z020 SoC (U1)
Pin
Net Name
Net Name
Low Side Net
Bank
Pin
1
CAN_TXD
CAN_TXD_LS
PS_MIO47
501
B10
4
CAN_RXD
CAN_RXD_LS
PS_MIO46
501
D12
8
CAN_STB_B
CAN_STB_B_LS
PS_MIO9
500
C4
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Status LEDs
[Figure 1-2, callout 21] Table 1-22 defines the status LEDs. For user-controlled LEDs see User I/O.
Table 1-22: Status LEDs
Reference Designator
DS1
Net Name
POR
DS2
FPGA_INIT_B
DS3 DS4 DS5 DS6 DS7 DS8 DS14
DONE PWRCTL_VCC1B_FLKT_LINEAR_PG
U13_FLG PHY_LED2 PHY_LED1 PHY_LED0 VCC12_P_IN
DS13
PWRCTL_PWRGOOD
DS24
PWRCTL1_VCC4A_PG
LED Color
Description
Red
Green/Red
Green Green Red Green Green Green Green
Green
Green
Power on reset is active Green: FPGA initialization was successful Red: FPGA initialization is in progress FPGA bit file download is complete DDR3 VTT OK USB Power Error Ethernet PHY (U35) User LED2 Ethernet PHY (U35) User LED1 Ethernet PHY (U35) User LED0 12VDC Power ON UCD9248 Power Controllers U32, U33, U34 Power Good (board supply voltages > minimum operating voltage) FMC1, FMC2 Power Good
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Ethernet PHY User LEDs
[Figure 1-2, callout 11]
The three Ethernet PHY user LEDs shown in Figure 1-20 are located near the RJ45 Ethernet jack P2. The on/off state for each LED is software dependent and has no specific meaning at Ethernet PHY power on.
Refer to the Marvell 88E1116R Alaska Gigabit Ethernet transceiver data sheet for details concerning the use of the Ethernet PHY user LEDs. They are referred in the data sheet as LED0, LED1, and LED2. The data sheet and other product information for the Marvell 88E1116R Alaska Gigabit Ethernet Transceiver is available at the Marvell website [Ref 20].
X-Ref Target - Figure 1-20
VCC3V3
VCC3V3
VCC3V3
318 261 0.1
DS8
317 261 0.1
DS7
316 261 0.1
DS6
3
PHY LED 0 1 2
Q9 NDS331N 460 mW
PHY LED1
3 1
2
Q8 NDS331N 460 mW
3
PHY LED 2 1 2
Q7 NDS331N 460 mW
GND
GND
Figure 1-20: Ethernet PHY User LEDs
GND
UG850_c1_20_032719
User I/O
[Figure 1-2, callout 17�28]
The ZC702 board provides the following user and general purpose I/O capabilities:
� Ten user LEDs (callout 17) � PMOD0 0�PMOD0 3 and PMOD1 0�PMOD1 3: DS15�DS22 � PS_LED1: DS23 and PS_MIO8_LED0: DS12
� Two user pushbuttons and reset switch (callout 18) � GPIO_SW_N and GPIO_SW_S: SW5 and SW7
� 2-position user DIP switch (callout 24) � GPIO_DIP_SW1 and GPIO_DIP_SW0: SW12
� User PS switches (near callout 18)
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� Pushbutton SW13 wired in parallel to DIP switch SW15 switch 1 � Pushbutton SW14 wired in parallel to DIP switch SW15 switch 2 � PS Power-On and System Reset pushbuttons (Switches) � SW1 (PS_POR_B) � SW2 (PS_SRST_B) � Two user GPIO male pin headers (callout 28) � 2 x 6 0.1 inch pitch PMOD1 J63 � 1 x 6 0.1 inch pitch PMOD2 J62
User LEDs
[Figure 1-2, callout 17]
The ZC702 board supports eight user LEDs connected to XC7Z020 SoC Banks 13, 33, 34, and 35 through level-shifters. Note that the LEDs are wired in parallel with headers J63 (PMOD1) and J62 (PMOD2). These headers are described in User PMOD GPIO Headers.
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Feature Descriptions
Figure 1-21 shows the user LED circuits.
X-Ref Target - Figure 1-21
VCC3V3
VCC3V3
DS19
DS20
VCC3V3 DS21
VCC3V3 DS22
R409 261 0.1
3
PMOD1 0 1 2
Q20 NDS331N 460 mW
R410 261 0.1
3
PMOD1 1 1 2
Q17 NDS331N 460 mW
GND VCC3V3
GND VCC3V3
R411 261 0.1
3
PMOD1 2 1 2
Q18 NDS331N 460 mW
R412 261 0.1
3
PMOD1 3 1 2
Q19 NDS331N 460 mW
GND VCC3V3
GND VCC3V3
DS18
DS17
DS16
DS15
R407 261 0.1
3
PMOD2 0 1 2
Q16 NDS331N 460 mW
R406 261 0.1
3
PMOD2 1 1 2
Q15 NDS331N 460 mW
R405 261 0.1
3
PMOD2 2 1 2
Q14 NDS331N 460 mW
R404 261 0.1
3
PMOD2 3 1 2
Q12 NDS331N 460 mW
GND VCC3V3
GND
VCC3V3
GND
GND
DS23
R416 261 0.1
3
PS_LED1 1 2
Q21 NDS331N 460 mW
GND
DS12 VCCMIO (1.8V)
R85 20.5K 0.1W
PS_MIO8_LED0
R393 261 0.1
3 1
2
Q11 NDS331N 460 mW
GND
Figure 1-21: User LEDs
UG850_c1_21_032719
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Table 1-23 lists the user LED connections to XC7Z020 SoC U1.
Table 1-23: User LED Connections to XC7Z020 SoC U1
XC7Z020 (U1) Pin
E15 D15 W17 W5 V7 W10 P18 P17 Bank 501 G7 Bank 500 E5
Net Name
PMOD1_0 PMOD1_1 PMOD1_2 PMOD1_3 PMOD2_0 PMOD2_1 PMOD2_2 PMOD2_3 PS_LED1 PS_MIO8_LED0
I/O Standard
LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25
N/A N/A
LED Reference Designator
DS19 DS20 DS21 DS22 DS18 DS17 DS16 DS15 DS23 DS12
User Pushbuttons
[Figure 1-2, callout 18] Figure 1-22 shows the user pushbutton circuits.
X-Ref Target - Figure 1-22
GPIO SW N
SW5
4
3
VADJ
Left
1
2
GPIO SW S
VADJ
SW7 Right
4
1
3
2
R352 4.7k 0.1 5%
R354 4.7k 0.1 5%
GND
GND
UG850_c1_22_032719
Figure 1-22: User Pushbuttons
Table 1-24 lists the user pushbutton connections to XC7Z020 SoC U1.
Table 1-24: User Pushbutton Connections to XC7Z020 SoC U1
XC7Z020 SoC (U1) Pin
G19
Net Name I/O Standard Pushbutton and Pin Reference
GPIO_SW_N LVCMOS25
SW5.3 (Left switch)
F19
GPIO_SW_S LVCMOS25
SW7.3 (Right switch)
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GPIO DIP Switch
[Figure 1-2, callout 19] Figure 1-23 shows the GPIO DIP switch circuit.
X-Ref Target - Figure 1-23
GPIO_DIP_SW1 GPIO_DIP_SW0
SW12
1 2
VADJ
4 3
R51 4.7k 0.1 5%
R50 SDA02H1SBD
4.7k 0.1 5%
GND
UG850_c1_23_032719
Figure 1-23: GPIO DIP Switch
Table 1-25 lists the GPIO DIP switch connections to XC7Z020 SoC U1.
Table 1-25: GPIO DIP Switch Connections to XC7Z020 SoC at U1
XC7Z020 (U1) Pin
W6
Net Name
GPIO_DIP_SW0
I/O Standard
LVCMOS25
DIP Switch SW12 Pin
2
W7
GPIO_DIP_SW1
LVCMOS25
1
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User PS Switches
[Figure 1-2, near callout 18] Figure 1-25 shows the user PS pushbutton and DIP switch circuit.
X-Ref Target - Figure 1-24
PS_DIP_SW0 PS_DIP_SW1
VCCMIO_PS (1.8V)
SW13
4
1
3
2
R413 4.7 k 0.1 5%
GND
VCCMIO_PS (1.8V)
SW14
4
1
3
2
R414 4.7 k 0.1 5%2719
GND
VCCMIO_PS (1.8V)
SW15
1
4
2
3
SDA02H1SBD
UG850_c1_24_032719
Figure 1-24: User PS Pushbutton and DIP Switch Circuit Table 1-26 lists the user PS-side pushbutton and DIP switch connections to XC7Z020 SoC U1 Bank 500.
Table 1-26: User PS Switch Connections to XC7Z020 SoC U1
XC7Z020 SoC (U1) Pin
B6
Net Name
PS_DIP_SW0
Switch and Pin Reference
SW13.4 and SW15.1
C5
PS_DIP_SW1
SW14.4 and SW15.2
User PMOD GPIO Headers
[Figure 1-2, callout 28]
The ZC702 board supports two GPIO headers J62 and J63. The PMOD nets connected to these headers are dual-purpose, with the User LEDs wired in parallel to the header pins.
J63 has a second dual-purpose function. The even numbered pins are wired in parallel to the Arm PJTAG header J41 pins TDI, TIMS, TCK, and TDO. The J41 PJTAG signals are connected to SoC Bank 13 GPIO pins which simultaneously drive J41 and J63. When J41 is used for Arm PJTAG functionality, the J63 even numbered pin should not be used. When J63 even numbered pins are used as GPIO, connector J41 should not be used.
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PMOD connectors J62 and J63 are wired to the U1 XC7Z020 SoC via TXS0108E 3.3V-to-VADJ (typically 1.8V) level-shifters.
Figure 1-25 shows the user GPIO male pin header circuits.
X-Ref Target - Figure 1-25
VCC3V3
J62 1 2 3 4 5
6
PMOD2 0 PMOD2 1 PMOD2 2 PMOD2 3
VCC3V3
VCC3V3
PMOD1 0 PMOD1 1 PMOD1 2 PMOD1 3
J63
1
2
3
4
5
6
7
8
9
10
11
12
PL PJTAG TDI LS PL PJTAG TMS LS PL PJTAG TCK LS PL PJTAG TDO LS
GND
GND
GND
UG850_c1_25_030513
Figure 1-25: User GPIO Headers
When using the PMOD headers on the Zynq-7000 SoC ZC702 evaluation kit, the voltage level output might appear normal at steady state; however, the rise and fall times on the other side of the TXS0108E level shifters can be several microseconds. The paralleled LED driver NDS331N FET has a gate capacitance of ~200 pF. The 200 pF load affects maximum toggle rate, which is ~100 kHz. There are no speed requirements for PMOD or GPIOs. The recommendation for a specific high-speed access with GPIO is to use the FMC interface.
Table 1-27 lists the GPIO Header connections to XC7Z020 SoC U1.
Table 1-27: GPIO Header Connections to XC7Z020 SoC at U1
XC7Z020 (U1) Pin Net Name
I/O Standard GPIO Header and Pin
E15
PMOD1_0
LVCMOS25
J63.1
D15
PMOD1_1
LVCMOS25
J63.3
W17 W5 V7 W10 P18
PMOD1_2 PMOD1_3 PMOD2_0 PMOD2_1 PMOD2_2
LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25
J63.5 J63.7 J62.1 J62.2 J62.3
P17
PMOD2_3
LVCMOS25
J62.4
Refer to the Zynq-7000 SoC Technical Reference Manual (UG585) [Ref 2] for information about the PS PJTAG functionality.
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Switches
[Figure 1-2, callout 22�26] The ZC702 board includes a power and a configuration switch: � Power On/Off slide switch SW11 (callout 26) � SW4 (FPGA_PROG_B), active-Low pushbutton (callout 22)
Power On/Off Slide Switch
[Figure 1-2, callout 20] The ZC702 board power switch is SW11. Sliding the switch actuator from the Off to On position applies 12V power from J60, a 6-pin mini-fit connector. Green LED DS14 illuminates when the ZC702 board power is on. See Power Management for details on the onboard power system.
CAUTION! Do NOT plug a PC ATX power supply 6-pin connector into J60 on the ZC702 board. The ATX 6-pin connector has a different pinout than J60. Connecting an ATX 6-pin connector into J60 damages the ZC702 board and voids the board warranty.
Figure 1-26 shows the power connector J60, power switch SW11 and indicator LED DS14.
X-Ref Target - Figure 1-26
J60
12V 12V N/C N/C COM COM
1 4 2 5 3 6
VCC12_P_IN INPUT_GND
SW11 1
2 3
4 5
6
C512 1F 25V
U78 1
3
VCC12_P
8
C517
R387
330F
1k
25V
1%
7
6
DS14
5
INPUT_GND
GND
GND
UG850_c1_26_030513
Figure 1-26: Power On/Off Switch SW11
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Program_B Pushbutton
[Figure 1-2, callout 22]
Switch SW4 grounds the XC7Z020 SoC PROG_B pin when pressed. This action clears programmable logic configuration, which the PS software can then act on. The FPGA_PROG_B signal is connected to XC7Z020 SoC U1 pin T11.
See the 7 Series FPGAs Configuration User Guide (UG470) [Ref 8] for further details on configuring the 7 series FPGAs.
Figure 1-27 shows SW4.
X-Ref Target - Figure 1-27
VCC2V5
To XC7Z020 SoC PROGRAM_B_0
(U1.T11)
FPGA PROG B
R51 4.7k
0.1 5%
SW4
2
4
1
3
GND
UG850_c1_27_032719
Figure 1-27: PROG_B Pushbutton SW4
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PS Power-On and System Reset Pushbuttons
[Figure 1-2, callout 27] Figure 1-28 shows the reset circuitry for the processing system.
X-Ref Target - Figure 1-28
R179 10.0 K
0.1 1%
VCC3V3
R180 10.0 K
0.1 1%
R181 10.0 K
0.1 1%
R138 8.06 K
0.1 1%
SW1 2
PS_POR_B 1
SW2 2
PS_SRST_B 1
J6
R178 10.0 K
0.1 1%
VCCMIO
R139 8.06 K
0.1 1%
R182 10.0 K
0.1 1%
VCC3V3
VCCMIO VCCMIO
U2
MAX16025
Dual Voltage Monitor
and Sequencer
2 IN1
3 IN2
6 EN1
7 EN2
13 MR_B
4 TOL
9 TH0
8 TH1
VCC 1
RST_B 12 OUT1 11 OUT2 10 CDLY1 16 CDLY2 15
CRESET 14 EPAD 17 GND 5
R184
10.0 K
DS1
0.1
R183
1%
R92 249
0.1
10.0 K
0.1 1%
1%
PS_POR_B_SW
J28 1
2
3
PS_SRST_B_SW
1
J27
C4 0.1 �f
25V X5R
C5 0.1 �f
25V X5R
C3 0.1 �f
25V X5R
PS_POR_B PS_SRST_B
23 GND
GND
GND
Figure 1-28: PS Power On and System Reset Circuitry
UG850_c1_28_032719
Depressing and then releasing pushbutton SW1 causes PS_POR_B_SW to strobe Low.
PS_POR_B: This reset is used to hold the PS in reset until all PS power supplies are at the required voltage levels. It must be held Low through PS power-up. PS_POR_B should be generated by the power supply power-good signal.
Depressing and then releasing pushbutton SW2 causes PS_SRST_B_SW to strobe Low.
PS_SRST_B: This reset is used to force a system reset. It can be tied or pulled High, and can be High during the PS supply power ramps.
Refer to the Zynq-7000 SoC Technical Reference Manual (UG585) [Ref 2] for information concerning the resets.
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FPGA Mezzanine (FMC) Card Interface
[Figure 1-2, callout 24]
The ZC702 board supports the VITA 57.1 FPGA Mezzanine Card (FMC) specification [Ref 6] by providing subset implementations of low pin count (LPC) connectors at J3 and J4. Both connectors use a 10 x 40 form factor that is partially populated with 160 pins. The connectors are keyed so that a the mezzanine card faces away from the ZC702 board when connected.
Connector Type:
� Samtec SEAF series, 1.27 mm (0.050 in) pitch. Mates with SEAM series connector.
For more information about SEAF series connectors, go to the Samtec website [Ref 28].
LPC Connectors J3 and J4
[Figure 1-2, callout 24]
The 160-pin FMC LPC connector is shown in Figure B-1.
The LPC connections between FMC1 (J3) and XC7Z020 SoC U1 (Table 1-28) and between FMC2 (J4) and XC7Z020 SoC U1 (Table 1-29) both implement a subset of this connectivity (GTX is not supported):
� 68 single-ended or 34 differential user-defined signals (34 LA pairs, LA00�LA33) � 0 GTX transceivers � 0 GTX clocks � 2 differential clocks � 61 ground and 9 power connections Note: FMC1 (J3) and FMC2 (J4) GA0 = GA1 = 0 (GND).
Table 1-28 shows the LPC connections between J3 and XC7Z020 SoC U1.
Table 1-28: LPC Connections, FMC1 (J3) to XC7Z020 SoC U1
FMC1 J3 Pin
C2
Net Name
NC
I/O XC7Z020 FMC1 Standard (U1) Pin J3 Pin
D1
Net Name
PWRCTL2_VCC4A_PG
C3
NC
D4
NC
C6
NC
D5
NC
C7
NC
D8 FMC1_LPC_LA01_CC_P
C10
FMC1_LPC_LA06_P LVCMOS25 J18
D9 FMC1_LPC_LA01_CC_N
C11 FMC1_LPC_LA06_N LVCMOS25 K18 D11
FMC1_LPC_LA05_P
I/O XC7Z020 Standard (U1) Pin
LVCMOS25 N19 LVCMOS25 N20 LVCMOS25 N17
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Table 1-28: LPC Connections, FMC1 (J3) to XC7Z020 SoC U1 (Cont'd)
FMC1 J3 Pin
C14
Net Name
FMC1_LPC_LA10_P
I/O XC7Z020 FMC1 Standard (U1) Pin J3 Pin
LVCMOS25 L17 D12
Net Name
FMC1_LPC_LA05_N
I/O XC7Z020 Standard (U1) Pin
LVCMOS25 N18
C15 FMC1_LPC_LA10_N LVCMOS25 M17 D14
FMC1_LPC_LA09_P
LVCMOS25 M15
C18
FMC1_LPC_LA14_P LVCMOS25 J16 D15
FMC1_LPC_LA09_N LVCMOS25 M16
C19 FMC1_LPC_LA14_N LVCMOS25 J17 D17
FMC1_LPC_LA13_P
LVCMOS25 P16
C22 FMC1_LPC_LA18_CC_P LVCMOS25 D20 D18
FMC1_LPC_LA13_N LVCMOS25 R16
C23 FMC1_LPC_LA18_CC_N LVCMOS25 C20 D20 FMC1_LPC_LA17_CC_P LVCMOS25 B19
C26
FMC1_LPC_LA27_P LVCMOS25 C17 D21 FMC1_LPC_LA17_CC_N LVCMOS25 B20
C27 FMC1_LPC_LA27_N LVCMOS25 C18 D23
FMC1_LPC_LA23_P
LVCMOS25 G15
C30
FMC1_LPC_IIC_SCL
D24
FMC1_LPC_LA23_N LVCMOS25 G16
C31 FMC1_LPC_IIC_SDA
D26
FMC1_LPC_LA26_P
LVCMOS25 F18
C34
GA0 = 0 = GND
D27
FMC1_LPC_LA26_N LVCMOS25 E18
C35
VCC12_P
D29 FMC1_LPC_TCK_BUF
C37
VCC12_P
D30
FMC_TDI_BUF
C39
VCC3V3
D31
FMC1_LPC_TDO_FMC2_L PC_TDI
D32
VCC3V3
D33 FMC1_LPC_TMS_BUF
D34
NC
D35
GA0 = 0 = GND
D36
VCC3V3
D38
VCC3V3
D40
VCC3V3
G2
FMC1_LPC_CLK1_M2C_ P
LVCMOS25
M19
H1
NC
G3
FMC1_LPC_CLK1_M2C_ N
LVCMOS25
M20
H2
FMC1_LPC_PRSNT_M2C_ B
G6 FMC1_LPC_LA00_CC_P LVCMOS25 K19
H4 FMC1_LPC_CLK0_M2C_P LVCMOS25 L18
G7 FMC1_LPC_LA00_CC_N LVCMOS25 K20
H5 FMC1_LPC_CLK0_M2C_N LVCMOS25 L19
G9
FMC1_LPC_LA03_P LVCMOS25 J20
H7
FMC1_LPC_LA02_P
LVCMOS25 L21
G10
FMC1_LPC_LA03_N LVCMOS25 K21
H8
FMC1_LPC_LA02_N LVCMOS25 L22
G12
FMC1_LPC_LA08_P LVCMOS25 J21 H10
FMC1_LPC_LA04_P
LVCMOS25 M21
G13 FMC1_LPC_LA08_N LVCMOS25 J22 H11
FMC1_LPC_LA04_N LVCMOS25 M22
G15
FMC1_LPC_LA12_P LVCMOS25 N22 H13
FMC1_LPC_LA07_P
LVCMOS25 J15
G16 FMC1_LPC_LA12_N LVCMOS25 P22 H14
FMC1_LPC_LA07_N LVCMOS25 K15
G18
FMC1_LPC_LA16_P LVCMOS25 N15 H16
FMC1_LPC_LA11_P
LVCMOS25 R20
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Table 1-28: LPC Connections, FMC1 (J3) to XC7Z020 SoC U1 (Cont'd)
FMC1 J3 Pin
G19
Net Name
FMC1_LPC_LA16_N
I/O XC7Z020 FMC1 Standard (U1) Pin J3 Pin
LVCMOS25 P15 H17
Net Name
FMC1_LPC_LA11_N
G21
FMC1_LPC_LA20_P LVCMOS25 G20 H19
FMC1_LPC_LA15_P
G22 FMC1_LPC_LA20_N LVCMOS25 G21 H20
FMC1_LPC_LA15_N
G24
FMC1_LPC_LA22_P LVCMOS25 G17 H22
FMC1_LPC_LA19_P
G25 FMC1_LPC_LA22_N LVCMOS25 F17 H23
FMC1_LPC_LA19_N
G27
FMC1_LPC_LA25_P LVCMOS25 C15 H25
FMC1_LPC_LA21_P
G28 FMC1_LPC_LA25_N LVCMOS25 B15 H26
FMC1_LPC_LA21_N
G30
FMC1_LPC_LA29_P LVCMOS25 B16 H28
FMC1_LPC_LA24_P
G31 FMC1_LPC_LA29_N LVCMOS25 B17 H29
FMC1_LPC_LA24_N
G33
FMC1_LPC_LA31_P LVCMOS25 A16 H31
FMC1_LPC_LA28_P
G34 FMC1_LPC_LA31_N LVCMOS25 A17 H32
FMC1_LPC_LA28_N
G36
FMC1_LPC_LA33_P LVCMOS25 A18 H34
FMC1_LPC_LA30_P
G37 FMC1_LPC_LA33_N LVCMOS25 A19 H35
FMC1_LPC_LA30_N
G39
VADJ
H37
FMC1_LPC_LA32_P
H38
FMC1_LPC_LA32_N
H40
VADJ
I/O XC7Z020 Standard (U1) Pin
LVCMOS25 R21 LVCMOS25 P20 LVCMOS25 P21 LVCMOS25 E19 LVCMOS25 E20 LVCMOS25 F21 LVCMOS25 F22 LVCMOS25 A21 LVCMOS25 A22 LVCMOS25 D22 LVCMOS25 C22 LVCMOS25 E21 LVCMOS25 D21 LVCMOS25 B21 LVCMOS25 B22
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Table 1-29 shows the LPC connections between FMC2 (J4) and SoC U1.
Table 1-29: LPC Connections, FMC2 (J4) to SoC U1
FMC2 J4 Pin
C2 NC C3 NC C6 NC C7 NC
Net Name
C10 FMC2_LPC_LA06_P
C11 FMC2_LPC_LA06_N C14 FMC2_LPC_LA10_P C15 FMC2_LPC_LA10_N C18 FMC2_LPC_LA14_P C19 FMC2_LPC_LA14_N C22 FMC2_LPC_LA18_CC_P C23 FMC2_LPC_LA18_CC_N
C26 FMC2_LPC_LA27_P
C27 FMC2_LPC_LA27_N C30 FMC2_LPC_IIC_SCL C31 FMC2_LPC_IIC_SDA C34 GA0 = 0 = GND C35 VCC12_P C37 VCC12_P
C39 VCC3V3
G2 FMC2_LPC_CLK1_M2C_P
I/O Standard
LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25
LVCMOS25
XC7Z020 FMC2 (U1) Pin J4 Pin
Net Name
D1 PWRCTL2_VCC4A_PG
D4 NC
D5 NC
D8 FMC2_LPC_LA01_CC_ P
U17
D9 FMC2_LPC_LA01_CC_
N
V17
D11 FMC2_LPC_LA05_P
Y20
D12 FMC2_LPC_LA05_N
Y21
D14 FMC2_LPC_LA09_P
T22
D15 FMC2_LPC_LA09_N
U22
D17 FMC2_LPC_LA13_P
AA9
D18 FMC2_LPC_LA13_N
AA8
D20 FMC2_LPC_LA17_CC_
P
AB2
D21 FMC2_LPC_LA17_CC_
N
AB1
D23 FMC2_LPC_LA23_P
D24 FMC2_LPC_LA23_N
D26 FMC2_LPC_LA26_P
D27 FMC2_LPC_LA26_N
D29 FMC2_LPC_TCK_BUF
D30 FMC1_LPC_TDO_FMC 2_LPC_TDI
D31 FMC2_LPC_TDO_FPG A_TDI
D32 VCC3V3
D33 FMC2_LPC_TMS_BUF
D34 NC
D35 GA0 = 0 = GND
D36 VCC3V3
D38 VCC3V3
D40 VCC3V3
Y6
H1 NC
I/O XC7Z020 Standard (U1) Pin
LVCMOS25 W16
LVCMOS25 Y16
LVCMOS25 AB19 LVCMOS25 AB20 LVCMOS25 U15 LVCMOS25 U16 LVCMOS25 V22 LVCMOS25 W22 LVCMOS25 AA7
LVCMOS25 AA6
LVCMOS25 V12 LVCMOS25 W12 LVCMOS25 U12 LVCMOS25 U11
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Table 1-29: LPC Connections, FMC2 (J4) to SoC U1 (Cont'd)
FMC2 J4 Pin
Net Name
G3 FMC2_LPC_CLK1_M2C_N
G6 FMC2_LPC_LA00_CC_P
I/O XC7Z020 FMC2 Standard (U1) Pin J4 Pin
Net Name
LVCMOS25 Y5
H2 FMC2_LPC_PRSNT_M 2C_B
LVCMOS25 Y19
H4 FMC2_LPC_CLK0_M2 C_P
G7 FMC2_LPC_LA00_CC_N
LVCMOS25 AA19
H5
FMC2_LPC_CLK0_M2
C_N
G9 FMC2_LPC_LA03_P
LVCMOS25 AA16
H7
FMC2_LPC_LA02_P
G10 FMC2_LPC_LA03_N G12 FMC2_LPC_LA08_P G13 FMC2_LPC_LA08_N G15 FMC2_LPC_LA12_P G16 FMC2_LPC_LA12_N
LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25
AB16 AA17 AB17 W15 Y15
H8 FMC2_LPC_LA02_N H10 FMC2_LPC_LA04_P H11 FMC2_LPC_LA04_N H13 FMC2_LPC_LA07_P H14 FMC2_LPC_LA07_N
G18 FMC2_LPC_LA16_P
LVCMOS25 AB14
H16 FMC2_LPC_LA11_P
G19 FMC2_LPC_LA16_N
LVCMOS25 AB15
H17 FMC2_LPC_LA11_N
G21 FMC2_LPC_LA20_P
LVCMOS25 T4
H19 FMC2_LPC_LA15_P
G22 FMC2_LPC_LA20_N
LVCMOS25 U4
H20 FMC2_LPC_LA15_N
G24 FMC2_LPC_LA22_P
LVCMOS25 U10
H22 FMC2_LPC_LA19_P
G25 FMC2_LPC_LA22_N
LVCMOS25 U9
H23 FMC2_LPC_LA19_N
G27 FMC2_LPC_LA25_P
LVCMOS25 AA12
H25 FMC2_LPC_LA21_P
G28 FMC2_LPC_LA25_N
LVCMOS25 AB12
H26 FMC2_LPC_LA21_N
G30 FMC2_LPC_LA29_P G31 FMC2_LPC_LA29_N G33 FMC2_LPC_LA31_P G34 FMC2_LPC_LA31_N G36 FMC2_LPC_LA33_P
LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25
AA11 AB11 AB10 AB9 Y11
H28 FMC2_LPC_LA24_P H29 FMC2_LPC_LA24_N H31 FMC2_LPC_LA28_P H32 FMC2_LPC_LA28_N H34 FMC2_LPC_LA30_P
G37 FMC2_LPC_LA33_N
LVCMOS25 Y10
H35 FMC2_LPC_LA30_N
G39 VADJ
H37 FMC2_LPC_LA32_P
H38 FMC2_LPC_LA32_N
H40 VADJ
I/O XC7Z020 Standard (U1) Pin
LVCMOS25 Y18
LVCMOS25 AA18
LVCMOS25 V14 LVCMOS25 V15 LVCMOS25 V13 LVCMOS25 W13 LVCMOS25 T21 LVCMOS25 U21 LVCMOS25 Y14 LVCMOS25 AA14 LVCMOS25 Y13 LVCMOS25 AA13 LVCMOS25 R6 LVCMOS25 T6 LVCMOS25 V5 LVCMOS25 V4 LVCMOS25 U6 LVCMOS25 U5 LVCMOS25 AB5 LVCMOS25 AB4 LVCMOS25 AB7 LVCMOS25 AB6 LVCMOS25 Y4 LVCMOS25 AA4
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Power Management
[Figure 1-2, callout 25] TheZC702 PCB layout and power system design meets the recommended criteria described in the Zynq-7000 SoC PCB Design Guide (UG933) [Ref 13]. The ZC702 board power distribution diagram is shown in Figure 1-29.
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X-Ref Target - Figure 1-29
J60 12 V
Power Controller 1 (Core) U32 PMBus Addr 0b0110100
Switching Regulator 1.0V at 10A
Switching Regulator
1.0V at 10A
U17
Switching Regulator 1.8V at 10A
Switching Regulator
1.8V at 10A
U18
Power Controller 2 (Aux) U33 PMBus Addr 0b0110101
Switching Regulator 2.5V at 10A
Switching Regulator
1.5V at 10A
U19
Switching Regulator 1.8V at 10A
Switching Regulator
1.0V at 10A
U20
Power Controller 3 PMBus Addr 0b0110110
Switching Regulator 3.3V at 10A
Switching Regulator 2.5V at 10A
U34 U21
Linear Regulator
VREF 0.75V at 3A
U22
Figure 1-29: Onboard Power Regulators
Feature Descriptions
VCCINT VCCPINT VCCAUX VCCPAUX
VCCADJ VCC1V5 VCCMIO VCCBRAM
VCC3V3 VCC2V5
VTTDDR
UG850_c1_29_090215
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Feature Descriptions
The ZC702 board uses power regulators and a PMBus compliant system controller from Texas Instruments to supply core and auxiliary voltages as listed in Table 1-30. The Texas Instruments Fusion Digital Power graphical user interface is used to monitor the voltage and current levels of the board power modules.
Table 1-30: Onboard Power System Devices
Device Type
Reference Designator
Description
Core voltage controller and regulators
UCD9248PFC
U32
PMBus Controller�Core
Addr = 52 dec., 0b0110100)
PTD08D210W--VoutA
PTD08D210W--VoutB
Dual 10A 0.6V�3.6V Adj. Switching
Regulator U17
Dual 10A 0.6V�3.6V Adj. Switching
Regulator
PTD08D210W--VoutA PTD08D210W--VoutB
Dual 10A 0.6V�3.6V Adj. Switching
Regulator U18
Dual 10A 0.6V�3.6V Adj. Switching
Regulator
Auxiliary voltage controller and regulators
UCD9248PFC
U33
PMBus Controller�Aux
Addr = 53 dec., 0b0110101)
PTD08D210W--VoutA PTD08D210W--VoutB
Dual 10A 0.6V�3.6V Adj. Switching
Regulator
U19
(set to 1.8V, 2.5V or 3.3V)
Dual 10A 0.6V�3.6V Adj. Switching
Regulator
PTD08D210W--VoutA PTD08D210W--VoutB
Dual 10A 0.6V�3.6V Adj. Switching
Regulator U20
Dual 10A 0.6V�3.6V Adj. Switching
Regulator
Power Rail Net Name
Power Rail Voltage
Schematic Page
39
VCCINT
1.00V
40
VCCPINT
1.00V
40
VCCAUX
1.80V
41
VCCPAUX
1.80V
41
42
VADJ
2.50V
43
VCC1V5
1.50V
43
VCCMIO_PS
1.80V
44
VCCBRAM
1.00V
44
UCD9248PFC
U34
PMBus Controller�Aux
Addr = 54 dec., 0b0110110)
45
PTD08D210W--VoutA
Dual 10A 0.6V�3.6V Adj. Switching
Regulator
VCC3V3
3.30V
46
U21
PTD08D210W--VoutB
Dual 10A 0.6V�3.6V Adj. Switching
Regulator
VCC2V5/ VCC2V5_PL
2.50V
46
Linear regulator
TPS51200DR
U22
3A Tracking Regulator
VTTDDR_PS
0.75V
37
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Feature Descriptions
VADJ Voltage Control
The VADJ rail is set to 2.5V. When the ZC702 board is powered on, the state of the FMC_VADJ_ON_B signal wired to header J12 is sampled by the TI UCD9248 controller U33. If a jumper is installed on J12 signal FMC_VADJ_ON_B is held Low, and the TI controller U33 energizes the VADJ rail at power on.
Because the rail turn on decision is made at power on time based on the presence of the J12 jumper, removing the jumper at J12 after the board is powered up does not affect the 2.5V power delivered to the VADJ rail and it remains on.
A jumper installed at J12 is the default setting.
If a jumper is not installed on J12, signal FMC_VADJ_ON_B is High, and the ZC702 board does not energize the VADJ 2.5V at power on. In this mode you can control when to turn on VADJ and to what voltage level (1.8V, 2.5V or 3.3V only). With VADJ off, the XC7Z020 SoC still configures and has access to the TI controller PMBUS along with the FMC_VADJ_ON_B signal. The combination of these allows the user to develop code to command the VADJ rail to be set to something other than the default setting of 2.5V. After the new VADJ voltage level has been programmed into TI controller U33, the FMC_VADJ_ON_B signal can be driven Low by the user logic and the VADJ rail comes up at the new VADJ voltage level. Installing a jumper at J12 after a ZC702 board powers up in this mode turns on the VADJ rail.
The FMC_VADJ_ON_B signal is sourced by the TCA6416APWR I2C port expander U80 pin 13 (see Figure 1-18).
The I2C port expander IIC_PORT_EXPANDER SDA/SCL bus is wired to the PCA9548ARGER I2C bus switch (see I2C Bus).
Documentation describing PMBUS programming for the UCD9248 digital power controller is available at TI [Ref 25].
Monitoring Voltage and Current
Voltage and current monitoring and control are available for selected power rails through Texas Instruments' Fusion Digital Power graphical user interface. The three onboard TI power controllers (U32 at address 52 decimal, U33 at address 53 decimal, and U34 at address 54 decimal) are wired to the same PMBus. The PMBus connector, J59, is provided for use with the TI USB Interface Adapter PMBus pod (TI part number EVM USB-TO-GPIO, which can be ordered from the Texas Instruments website [Ref 26] and associated TI Fusion Digital Power Designer GUI [Ref 27]. This is the simplest and most convenient way to monitor the voltage and current values for the power rail listed in Table 1-31, Table 1-32, and Table 1-33.
In each of these the three tables (one per controller), the Power Good (PG) On Threshold is the setpoint at or above which the particular rail is deemed "good". The PG Off Threshold is the setpoint at or below which the particular rail is no longer deemed "good". The controller
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Feature Descriptions
internally OR's these PG conditions together and drives an output PG pin High only if all active rail PG states are "good". The On and Off Delay and rise and fall times are relative to when the board power on-off slide switch SW12 is turned on and off.
Table 1-31 defines the voltage and current values for each power rail controlled by the UCD9248 PMBus controller at address 52 decimal (U32).
Table 1-31: Power Rail Specifications for UCD9248 PMBus Controller at Address 52 Decimal
Shutdown Threshold(1)
Nominal VOUT (V) PG On Threshold (V) PG Off Threshold (V) On Delay (ms) Rise Time (ms) Off Delay (ms) Fall Time (ms) VOUT Over Fault (V) IOUT Over Fault (A) Temp Over Fault (�C)
Rail
Rail
Number Name
Rail Name
1
Rail #1
VCCINT
2
Rail #2
VCCPINT
3
Rail #3
VCCAUX
4
Rail #4
VCCPAUX
1
0.9
0.85
0
1
0.9
0.85
0
1.8
1.62
1.53
0
1.8
1.62
1.53
0
5
10
1
1.15
20
90
5
10
1
1.15
20
90
5
5
1
2.07 10.41
90
5
5
1
2.07 10.41
90
Notes: 1. The values defined in these columns are the voltage, current, and temperature thresholds that causes the regulator to shut
down if the value is exceeded.
Table 1-32 defines the voltage and current values for each power rail controlled by the UCD9248 PMBus controller at address 53 decimal (U33).
Table 1-32: Power Rail Specifications for UCD9248 PMBus Controller at Address 53 Decimal
Shutdown Threshold(1)
Nominal VOUT (V) PG On Threshold (V) PG Off Threshold (V) On Delay (ms) Rise Time (ms) Off Delay (ms) Fall Time (ms) VOUT Over Fault (V) IOUT Over Fault (A) Temp Over Fault (�C)
Rail
Rail
Number Name
Schematic Rail Name
1
Rail #1
VADJ
2
Rail #2
VCC1V5
3
Rail #3 VCCMIO_PS
4
Rail #4
VCCBRAM
2.5
2.25 2.125
0
1.5
1.35 1.275
0
1.8
1.62
1.53
0
1
0.9
0.85
0
5
1
1
2.875 10.41
90
5
0
1
1.725 10.41
90
5
5
1
2.07 10.41
90
5
10
1
1.15
20
90
Notes: 1. The values defined in these columns are the voltage, current, and temperature thresholds that causes the regulator to shut
down if the value is exceeded.
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Table 1-33 defines the voltage and current values for each power rail controlled by the UCD9248 PMBus controller at address 54 decimal (U34).
Table 1-33: Power Rail Specifications for UCD9248 PMBus Controller at Address 54 Decimal
Shutdown Threshold(1)
Nominal VOUT (V) PG On Threshold (V) PG Off Threshold (V) On Delay (ms) Rise Time (ms) Off Delay (ms) Fall Time (ms) VOUT Over Fault (V) IOUT Over Fault (A) Temp Over Fault (�C)
Rail
Rail
Number Name
Schematic Rail Name
1
Rail #1
VCC3V3
3.3
2.97 2.805
0
5
4
1
3.795 10.41
90
2
Rail #2
VCC2V5
2.5
2.25 2.125
0
5
1
1
2.875 10.41
90
Notes: 1. The values defined in these columns are the voltage, current, and temperature thresholds that causes the regulator to shut
down if the value is exceeded.
Cooling Fan
The XC7Z020 SoC cooling fan connector J61 is wired directly to 12VDC as shown in Figure 1-30.
X-Ref Target - Figure 1-30
J61 3
2
VCC12_P NC
1
GND
UG850_c1_30_030513
Figure 1-30: Cooling Fan Circuit
More information about the power system components used by the ZC702 board are available from the Texas Instruments digital power website [Ref 25].
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Feature Descriptions
XADC Analog-to-Digital Converter
[Figure 1-2, callout 26]
The XC7Z020 SoC provides an Analog Front End XADC block. The XADC block includes a dual 12-bit, 1 MSPS Analog-to-Digital Converter (ADC) and on-chip sensors. See the 7 Series FPGAs XADC Dual 12-Bit 1MSPS Analog-to-Digital Converter User Guide (UG480) [Ref 9] for details on the capabilities of the analog front end. Figure 1-31 shows the XADC block diagram.
X-Ref Target - Figure 1-31
U1
XC7Z020 SoC
VCCADC
GNDADC
VCCAUX Ferrite Bead
To J70.3 XADC_VCC
100 nF Close to Package Pins
XADC_AGND
1 J38
XADC_VCC Header J40
2
1.8V 150 mV max
U10
3
ADP123
Out
In
Gnd
10 F
10 F
VCC5V0 To Header J40 Ferrite Bead
J65
VCC5V0
XADC_AGND
XADC_AGND
Filter 5V Supply Locate Components on Board
To Header
J49
VREFP
Dual Use IO (Analog/Digital)
100
1 nF
100 100
1 nF
100
VREFN VAUX0P VP VAUX0N VN VAUX8P DXP VAUX8N DXN
To Header J40 VREF (1.25V) 1 J37
U29
REF3012
Out
In
Gnd
1 J70 2
VREFP 2
100 nF 3
Close to Package Pins
Internal Reference
XADC_AGND
10 F
3 XADC_VCC
Ferrite Bead J9
100 1 nF 100
XADC_AGND
To Header
J40
Star Grid Connection
J8
GND
UG850_c1_31_031819
Figure 1-31: XADC Block Diagram
The ZC702 board supports both the internal XC7Z020 SoC sensor measurements and the external measurement capabilities of the XADC. Internal measurements of the die temperature, VCCINT, VCCAUX, and VCCBRAM are available.
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Feature Descriptions
Jumper J37 can be used to select either an external voltage reference (VREF) or on-chip voltage reference for the analog-to-digital converter.
For external measurements an XADC header (J19) is provided. This header can be used to provide analog inputs to the XC7Z020 SoC dedicated VP/VN channel, and to the VAUXP[0]/VAUXN[0], VAUXP[8]/VAUXN[8] auxiliary analog input channels. Simultaneous sampling of Channel 0 and Channel 8 is supported.
A user-provided analog signal multiplexer card can be used to sample additional external analog inputs using the 4 GPIO pins available on the XADC header as multiplexer address lines. Figure 1-32 shows the XADC header connections.
X-Ref Target - Figure 1-32
XADC_VCC5V0 VADJ
XADC_VN XADC_VAUX0P
XADC_VAUX8N XADC_DXP XADC_VREF
XADC_GPIO_1 XADC_GPIO_3
J40
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
XADC_VP
XADC_VAUX0N XADC_VAUX8P
XADC_DXN XADC_VCC_HEADER
XADC_GPIO_0 XADC_GPIO_2
XADC_AGND
GND
XADC_AGND
UG850_c1_32_030513
Figure 1-32: XADC Header (J40) Table 1-34 describes the XADC header J40 pin functions.
Table 1-34: XADC Header J40 Pinout
Net Name
VN, VP
J19 Pin Number
1, 2
Description
Dedicated analog input channel for the XADC.
XADC_VAUX0P, N
XADC_VAUX8N, P
DXP, DXN XADC_AGND XADC_VREF XADC_VCC5V0
3, 6
7, 8
9, 12 4, 5, 10
11 13
Auxiliary analog input channel 0. Also supports use as I/O inputs when anti alias capacitor is not present. Auxiliary analog input channel 8. Also supports use as I/O inputs when anti alias capacitor is not present. Access to thermal diode. Analog ground reference. 1.25V reference from the board. Filtered 5V supply from board.
XADC_VCC_HEADER
14
Analog 1.8V supply for XADC.
VADJ
15
VCCO supply for bank which is the source of DIO pins.
GND
16
Digital Ground (board) Reference
Digital I/O. These pins should come from the same bank. These I/Os XADC_GPIO_3, 2, 1, 0 19, 20, 17, 18 should not be shared with other functions because they are required to
support 3-state operation.
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Appendix A
Default Switch and Jumper Settings
Switches
[Figure 1-2, callout 24] Default switch settings are listed in Table A-1.
Table A-1: Default Switch Settings Switch
SW10 (JTAG chain input select two-position DIP switch) SW12 (two-position DIP switch) SW15 (two-position DIP switch)
SW16 (five-position DIP switch)
Position
1 2 1 2 1 2 1 2 3 4 5
Setting
Off On Off Off Off Off Right Right Right Right Right
Figure 1-2 Callout
23 19 19
29
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Jumpers
Jumpers
[Figure 1-2, callout 24] Default jumper positions are listed in Table A-2. Jumper locations are shown in Figure A-1.
Table A-2: Default Jumper Settings
Callout
Jumper
1
J5
2
J6
3
J7
4
J8
5
J9
6
J10
7
J11
8
J12
9
J13
10
J14
11
J15
12
J43
13
J44
14
J53
15
J56
16
J65
17
J20
18
J21
19
J22
20
J25
21
J26
22
J27
23
J28
24
J30
Function
HDR_1 X 2 CFGBVS short to GND ZC702 configuration bank 0 is operated at 2.5V, therefore the CFGBVS pin is pulled high with a resistor. Jumper J5 should be never installed. POR Master Reset USB 2.0 USB_VBUS_SEL XADC GND L3 BYPASS XADC GND ARM HDR J41 PIN 2 TO VADJ UCD9248 U32 ADDR52 RESET_B FMC VADJ OFF UCD9248 U33 ADDR53 RESET_B UCD9248 U34 ADDR54 RESET_B CAN BUS COMMON-MODE CANH HDR ETHERNET PHY HDR USB 2.0 USB_RESET_B CAN BUS COMMON-MODE CANL HDR JTAG HDR J58 PIN 2 3.3V SEL XADC_VCC5V0 = VCC5V0
HDR_1 X 3 MIO3/QSPI_IO1 MIO2/QSPI_IO0 MIO4/QSPI_IO2 MIO5/QSPI_IO3 MIO6/QSPI_CLK PS_SRST_B PS_POR_B ETHERNET PHY HDR
Default Position
OFF
OFF 1-2 OFF ON OFF OFF ON OFF OFF 1-2 1-2 OFF 1-2 OFF ON
OFF OFF OFF OFF OFF 1-2 1-2 1-2
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Table A-2: Default Jumper Settings (Cont'd)
Callout
25
Jumper
J31
Function
ETHERNET PHY HDR
26
J32
ETHERNET PHY HDR
27
J33
USB 2.0 MODE
28
J34
USB 2.0 J1 ID SEL
29
J35
USB 2.0 J1 VBUS CAP SEL
30
J36
USB 2.0 J1 GND SEL
31
J37
XADC_VREP SEL
32
J38
XADC_VCC SEL
33
J70
XADC_VREF SOURCE SEL
Jumpers
Default Position
NONE NONE
2-3 1-2 1-2 1-2 1-2 2-3 2-3
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Figure A-1 shows jumper locations described in this table.
X-Ref Target - Figure A-1
Jumpers
2 22 23 18 17 19 20 21
54
16
31 32 33 15
1
6 11
14
25
24
26
12
13 28 30
3 27
29
Figure A-1: Jumper Locations
9
8 7
10 UG850_a1_01_011415
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Appendix B
VITA 57.1 FMC Connector Pinouts
Figure B-1 shows the pinout of the FPGA mezzanine card (FMC) low pin count (LPC) connector defined by the VITA 57.1 FMC specification. For a description of how the ZC702 board implements the FMC specification, see FPGA Mezzanine (FMC) Card Interface and LPC Connectors J3 and J4.
X-Ref Target - Figure B-1
K
1
NC
2
NC
3
NC
4
NC
5
NC
6
NC
7
NC
8
NC
9
NC
10
NC
11
NC
12
NC
13
NC
14
NC
15
NC
16
NC
17
NC
18
NC
19
NC
20
NC
21
NC
22
NC
23
NC
24
NC
25
NC
26
NC
27
NC
28
NC
29
NC
30
NC
31
NC
32
NC
33
NC
34
NC
35
NC
36
NC
37
NC
38
NC
39
NC
40
NC
J
H
G
F
NC
VREF_A_M2C
GND
NC
NC
PRSNT_M2C_L CLK1_M2C_P
NC
NC
GND
CLK1_M2C_N
NC
NC
CLK0_M2C_P
GND
NC
NC
CLK0_M2C_N
GND
NC
NC
GND
LA00_P_CC
NC
NC
LA02_P
LA00_N_CC
NC
NC
LA02_N
GND
NC
NC
GND
LA03_P
NC
NC
LA04_P
LA03_N
NC
NC
LA04_N
GND
NC
NC
GND
LA08_P
NC
NC
LA07_P
LA08_N
NC
NC
LA07_N
GND
NC
NC
GND
LA12_P
NC
NC
LA11_P
LA12_N
NC
NC
LA11_N
GND
NC
NC
GND
LA16_P
NC
NC
LA15_P
LA16_N
NC
NC
LA15_N
GND
NC
NC
GND
LA20_P
NC
NC
LA19_P
LA20_N
NC
NC
LA19_N
GND
NC
NC
GND
LA22_P
NC
NC
LA21_P
LA22_N
NC
NC
LA21_N
GND
NC
NC
GND
LA25_P
NC
NC
LA24_P
LA25_N
NC
NC
LA24_N
GND
NC
NC
GND
LA29_P
NC
NC
LA28_P
LA29_N
NC
NC
LA28_N
GND
NC
NC
GND
LA31_P
NC
NC
LA30_P
LA31_N
NC
NC
LA30_N
GND
NC
NC
GND
LA33_P
NC
NC
LA32_P
LA33_N
NC
NC
LA32_N
GND
NC
NC
GND
VADJ
NC
NC
VADJ
GND
NC
E
D
C
NC
PG_C2M
GND
NC
GND
DP0_C2M_P
NC
GND
DP0_C2M_N
NC
GBTCLK0_M2C_P
GND
NC
GBTCLK0_M2C_N
GND
NC
GND
DP0_M2C_P
NC
GND
DP0_M2C_N
NC
LA01_P_CC
GND
NC
LA01_N_CC
GND
NC
GND
LA06_P
NC
LA05_P
LA06_N
NC
LA05_N
GND
NC
GND
GND
NC
LA09_P
LA10_P
NC
LA09_N
LA10_N
NC
GND
GND
NC
LA13_P
GND
NC
LA13_N
LA14_P
NC
GND
LA14_N
NC
LA17_P_CC
GND
NC
LA17_N_CC
GND
NC
GND
LA18_P_CC
NC
LA23_P
LA18_N_CC
NC
LA23_N
GND
NC
GND
GND
NC
LA26_P
LA27_P
NC
LA26_N
LA27_N
NC
GND
GND
NC
TCK
GND
NC
TDI
SCL
NC
TDO
SDA
NC
3P3VAUX
GND
NC
TMS
GND
NC
TRST_L
GA0
NC
GA1
12P0V
NC
3P3V
GND
NC
GND
12P0V
NC
3P3V
GND
NC
GND
3P3V
NC
3P3V
GND
Figure B-1: FMC LPC Connector Pinout
B
A
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
UG850_aB_01_081612
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Appendix C
Xilinx Design Constraints
Overview
The ZC702 Xilinx� Design Constraints (XDC) template provides for designs targeting the ZC702 board. Net names in the constraints correlate with net names on the latest ZC702 board schematic. You must identify the appropriate pins and replace the net names below with net names in your RTL. See the Vivado Design Suite User Guide: Using Constraints (UG903) [Ref 12] for more information. The FMC LPC connectors J3 and J4 are connected to 2.5V VADJ banks. Because different FMC cards implement different circuitry, the FMC bank I/O standards must be uniquely defined by each customer. Note: The ZC702 ucf/xdc files are under the Documentation tab of the Zynq-7000 SoC ZC702
Evaluation Kit product page. Click the Board Files check box, find the XTP185 ZC702 Schematics entry, and expand the Associated File(s) list.
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Board Specifications
Dimensions
Width: 7.750 in. (19.685 cm) Length: 7.150 in. (18.161 cm)
Environmental
Temperature
Operating: 0�C to +45�C Storage: �25�C to +60�C
Humidity
10% to 90% non-condensing
Operating Voltage
+12 VDC
Appendix D
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Appendix E
Regulatory and Compliance Information
Overview
This product is designed and tested to conform to the European Union directives and standards described in this section. Refer to the ZC702 board master answer record concerning the CE requirements for the PC Test Environment: ZC702 Evaluation Kit � Master Answer Record 47864 The Zynq-7000 ZC702 Declaration of Conformity is online.
CE Directives
2006/95/EC, Low Voltage Directive (LVD) 2004/108/EC, Electromagnetic Compatibility (EMC) Directive
CE Standards
EN standards are maintained by the European Committee for Electrotechnical Standardization (CENELEC). IEC standards are maintained by the International Electrotechnical Commission (IEC).
Electromagnetic Compatibility
EN 55022:2010, Information Technology Equipment Radio Disturbance Characteristics � Limits and Methods of Measurement EN 55024:2010, Information Technology Equipment Immunity Characteristics � Limits and Methods of Measurement
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Markings
IMPORTANT: This is a Class A product. In a domestic environment, this product can cause radio interference, in which case the user might be required to take adequate measures.
Safety
IEC 60950-1:2005, Information technology equipment � Safety, Part 1: General requirements EN 60950-1:2006, Information technology equipment � Safety, Part 1: General requirements
Markings
In August of 2005, the European Union (EU) implemented the EU WEEE Directive 2002/96/EC and later the WEEE Recast Directive 2012/19/EU requiring Producers of electronic and electrical equipment (EEE) to manage and finance the collection, reuse, recycling and to appropriately treat WEEE that the Producer places on the EU market after August 13, 2005. The goal of this directive is to minimize the volume of electrical and electronic waste disposal and to encourage re-use and recycling at the end of life. Xilinx has met its national obligations to the EU WEEE Directive by registering in those countries to which Xilinx is an importer. Xilinx has also elected to join WEEE Compliance Schemes in some countries to help manage customer returns at end-of-life. If you have purchased Xilinx-branded electrical or electronic products in the EU and are intending to discard these products at the end of their useful life, please do not dispose of them with your other household or municipal waste. Xilinx has labeled its branded electronic products with the WEEE Symbol to alert our customers that products bearing this label should not be disposed of in a landfill or with municipal or household waste in the EU.
This product complies with Directive 2002/95/EC on the restriction of hazardous substances (RoHS) in electrical and electronic equipment.
This product complies with CE Directives 2006/95/EC, Low Voltage Directive (LVD) and 2004/108/EC, Electromagnetic Compatibility (EMC) Directive.
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Appendix F
Additional Resources
Xilinx Resources
For support resources such as Answers, Documentation, Downloads, and Forums, see the Xilinx Support website. For continual updates, add the Answer Record to your myAlerts.
Solution Centers
See the Xilinx Solution Centers for support on devices, software tools, and intellectual property at all stages of the design cycle. Topics include design assistance, advisories, and troubleshooting tips.
References
The most up to date information related to the ZC702 board and its documentation is available on the following websites.
ZC702 Evaluation Kit ZC702 Evaluation Kit � Master Answer Record 47864 These Xilinx documents provide supplemental material useful with this guide: 1. Zynq-7000 SoC Data Sheet: Overview (DS190) 2. Zynq-7000 SoC Technical Reference Manual (UG585) 3. Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020): DC and AC Switching Characteristics (DS187) 4. 7 Series FPGAs Memory Interface Solutions v1.8 User Guide (UG586) 5. 7 Series FPGAs Memory Resources User Guide (UG473)
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References
6. VITA FMC Marketing Alliance - VITA 57.1 base standard: www.vita.com/standards
7. Tri-Mode Ethernet MAC LogiCORE IP Product Guide (PG051)
8. 7 Series FPGAs Configuration User Guide (UG470)
9. 7 Series FPGAs XADC Dual 12-Bit 1MSPS Analog-to-Digital Converter User Guide (UG480)
10. Zynq-7000 SoC Packaging and Pinout Product Specification (UG865)
11. AMS101 Evaluation Card User Guide (UG886)
12. Vivado Design Suite User Guide: Using Constraints (UG903)
13. Zynq-7000 SoC PCB Design Guide (UG933)
The following websites provide supplemental material useful with this guide:
14. Micron Technology: www.micron.com (N25Q128A11ESF40G, MT41J256M8HX-15E)
15. Standard Microsystems Corporation: www.smsc.com/ (USB3320)
16. SanDisk Corporation: www.sandisk.com
17. SD Association: www.sdcard.org
18. SiTime: www.sitime.com (SiT8103, SiT9102)
19. Silicon Labs: www.silabs.com (Si570, Si5324C)
20. Marvell Semiconductor: www.marvell.com (88E1116R)
21. Analog Devices: www.analog.com/en/index.html (ADV7511KSTZ-P, ADP123)
22. Epson Electronics America: www.eea.epson.com and www.eea.epson.com/portal/pls/portal/docs/1/1413485.PDF (RTC-8564JE)
23. Digilent: www.digilentinc.com and www.digilentinc.com/Products/Catalog.cfm?NavPath=2,401&Cat=9 (Pmod Peripheral Modules)
24. NXP Semiconductors: ics.nxp.com (TJA01040)
25. Texas Instruments: www.ti.com, www.ti.com/fusiondocs, www.ti.com/ww/en/analog/digital-power/index.html and (UCD9248PFC, PTD08A010W, PTD08A020W, PTD08D210W, LMZ12002, TL1962ADC, TPS51200DR, PCA9548)
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References
26. Texas Instruments EVM USB-TO-GPIO: www.ti.com/xilinx_usb. 27. Texas Instruments TI Fusion Digital Power Designer GUI, downloadable from:
http://www.ti.com/fusion-gui 28. Samtec: www.samtec.com.
(SEAF series connectors) 29. Integrated Device Technology: www.idt.com
(ICS844021I)
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