Getting Started with Real-Time Counter (RTC)
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Getting Started with Real-Time Counter (RTC)
This Technical Brief describes how the RTC module works on tinyAVR 0-series, tinyAVR 1-series, and megaAVR 0-series microcontrollers.
DS-90003213C, DS90003213C, 90003213C, Microchip, AVR, Periodic Interrupt Timer, PIT, Real-Time Clock, RTC, ATmega4809 Xplained Pro
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Getting Started with Real-Time Counter (RTC) - Microchip Technology
TB3213 Getting Started with Real-Time Counter (RTC) Introduction Author: Victor Berzan, Microchip Technology Inc. This technical brief describes how the Real-Time Counter (RTC) module works on tinyAVR 0- and 1-series, m…
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TB3213
Getting Started with Real-Time Counter (RTC)
Introduction
Author: Victor Berzan, Microchip Technology Inc.
This technical brief describes how the Real-Time Counter (RTC) module works on tinyAVR� 0- and 1-series, megaAVR� 0-series and AVR� DA devices. It covers the following use cases:
� RTC Overflow Interrupt: Initialize the RTC, enable the overflow interrupt, and toggle an LED on each overflow.
� RTC Periodic Interrupt: Initialize the RTC PIT, enable the periodic interrupt, and toggle an LED on each periodic interrupt.
� RTC PIT Wake from Sleep: Initialize the RTC PIT, enable the periodic interrupt, configure device sleep mode, put CPU in Sleep, the PIT interrupt will wake the CPU.
Note: For each use case described in this document, there are two code examples: One bare metal developed on ATmega4809, and one generated with MPLAB� Code Configurator (MCC) developed on AVR128DA48.
View the ATmega4809 Code Examples on GitHub
Click to browse repository
View the AVR128DA48 Code Examples on GitHub
Click to browse repository
� 2021 Microchip Technology Inc.
Technical Brief
DS90003213C-page 1
TB3213
Table of Contents
Introduction.....................................................................................................................................................1 1. Relevant Devices.................................................................................................................................... 3
1.1. tinyAVR� 0-series.........................................................................................................................4 1.2. tinyAVR� 1-series.........................................................................................................................5 1.3. megaAVR� 0-series..................................................................................................................... 6 1.4. AVR� DA Family Overview.......................................................................................................... 6 2. Overview................................................................................................................................................. 7 3. RTC Overflow Interrupt........................................................................................................................... 8 4. RTC Periodic Interrupt...........................................................................................................................13 5. RTC PIT Wake from Sleep....................................................................................................................15 6. References............................................................................................................................................17 7. Appendix............................................................................................................................................... 18 8. Revision History.................................................................................................................................... 22 The Microchip Website.................................................................................................................................23 Product Change Notification Service............................................................................................................23 Customer Support........................................................................................................................................ 23 Microchip Devices Code Protection Feature................................................................................................ 23 Legal Notice................................................................................................................................................. 24 Trademarks.................................................................................................................................................. 24 Quality Management System....................................................................................................................... 25 Worldwide Sales and Service.......................................................................................................................26
� 2021 Microchip Technology Inc.
Technical Brief
DS90003213C-page 2
TB3213
Relevant Devices
1. Relevant Devices
This section lists the relevant devices for this document. The following figures show the different family devices, laying out pin count variants and memory sizes:
� Vertical migration upwards is possible without code modification, as these devices are pin-compatible and provide the same or more features. Downward migration on tinyAVR� 1-series devices may require code modification due to fewer available instances of some peripherals
� Horizontal migration to the left reduces the pin count and, therefore, the available features � Devices with different Flash memory sizes typically also have different SRAM and EEPROM
Figure 1-1.tinyAVR� 0-series Overview
Flash
16 KB
ATtiny1604
8 KB
ATtiny804
4 KB
ATtiny402
ATtiny404
2 KB
ATtiny202
ATtiny204
8
14
Figure 1-2.tinyAVR� 1-series Overview
ATtiny1606 ATtiny806 ATtiny406
20
ATtiny1607 ATtiny807
Pins 24
Flash 32 KB 16 KB
8 KB 4 KB 2 KB
ATtiny412 ATtiny212
8
ATtiny1614 ATtiny814 ATtiny414 ATtiny214
14
ATtiny3216 ATtiny1616 ATtiny816 ATtiny416
20
ATtiny3217 ATtiny1617 ATtiny817 ATtiny417
Pins 24
� 2021 Microchip Technology Inc.
Technical Brief
DS90003213C-page 3
Figure 1-3.megaAVR� 0-series Overview Flash
48 KB
ATmega4808
ATmega4808
32 KB
ATmega3208
ATmega3208
16 KB
ATmega1608
ATmega1608
8 KB
ATmega808
ATmega808
28
32
Figure 1-4.AVR� DA Family Overview Flash
128 KB
AVR128DA28
AVR128DA32
64 KB
AVR64DA28
AVR64DA32
32 KB
AVR32DA28 28
AVR32DA32 32
ATmega4809
40 AVR128DA48 AVR64DA48 AVR32DA48
48
TB3213
Relevant Devices
ATmega4809 ATmega3209 ATmega1609 ATmega809
Pins 48
AVR128DA64 AVR64DA64
Pins 64
1.1 tinyAVR� 0-series
The figure below shows the tinyAVR� 0-series devices, laying out pin count variants and memory sizes:
� Vertical migration upwards is possible without code modification, as these devices are pin-compatible and provide the same or more features
� Horizontal migration to the left reduces the pin count and, therefore, the available features
� 2021 Microchip Technology Inc.
Technical Brief
DS90003213C-page 4
Figure 1-5.tinyAVR� 0-series Overview Flash
TB3213
Relevant Devices
16 KB
ATtiny1604
ATtiny1606
ATtiny1607
8 KB
ATtiny804
ATtiny806
ATtiny807
4 KB
ATtiny402
ATtiny404
ATtiny406
2 KB
ATtiny202
ATtiny204
8
14
20
24
Devices with different Flash memory sizes typically also have different SRAM and EEPROM.
Pins
1.2 tinyAVR� 1-series
The following figure shows the tinyAVR 1-series devices, laying out pin count variants and memory sizes:
� Vertical migration upwards is possible without code modification, as these devices are pin-compatible and provide the same or more features. Downward migration may require code modification due to fewer available instances of some peripherals.
� Horizontal migration to the left reduces the pin count and, therefore, the available features
Figure 1-6.tinyAVR� 1-series Overview
Flash 32 KB
ATtiny3216
ATtiny3217
16 KB
ATtiny1614
ATtiny1616
ATtiny1617
8 KB
ATtiny814
ATtiny816
ATtiny817
4 KB
ATtiny412
ATtiny414
ATtiny416
ATtiny417
2 KB
ATtiny212
ATtiny214
8
14
20
24
Devices with different Flash memory sizes typically also have different SRAM and EEPROM.
Pins
� 2021 Microchip Technology Inc.
Technical Brief
DS90003213C-page 5
TB3213
Relevant Devices
1.3 megaAVR� 0-series
The figure below shows the megaAVR� 0-series devices, laying out pin count variants and memory sizes: � Vertical migration is possible without code modification, as these devices are fully pin and feature compatible � Horizontal migration to the left reduces the pin count and, therefore, the available features
Figure 1-7.megaAVR� 0-series Overview
Flash
48 KB
ATmega4808
ATmega4808
ATmega4809
ATmega4809
32 KB
ATmega3208
ATmega3208
ATmega3209
16 KB
ATmega1608
ATmega1608
ATmega1609
8 KB
ATmega808
ATmega808
ATmega809
Pins
28
32
40
48
Devices with different Flash memory sizes typically also have different SRAM and EEPROM.
1.4 AVR� DA Family Overview
The figure below shows the AVR� DA devices, laying out pin count variants and memory sizes:
� Vertical migration is possible without code modification, as these devices are fully pin and feature compatible � Horizontal migration to the left reduces the pin count, and therefore, the available features Figure 1-8.AVR� DA Family Overview
Flash
128 KB
AVR128DA28
AVR128DA32
AVR128DA48
AVR128DA64
64 KB
AVR64DA28
AVR64DA32
AVR64DA48
AVR64DA64
32 KB
AVR32DA28
AVR32DA32
AVR32DA48
28
32
48
Devices with different Flash memory sizes typically also have different SRAM.
Pins 64
� 2021 Microchip Technology Inc.
Technical Brief
DS90003213C-page 6
TB3213
Overview
2. Overview
The RTC peripheral offers two timing functions: A Real-Time Counter (RTC) and a Periodic Interrupt Timer (PIT). The PIT functionality can be enabled independently of the RTC functionality.
The RTC counts (prescaled) clock cycles in a Counter register and compares the content of the Counter register to a Period register and a Compare register. The RTC can generate both interrupts and events on compare match or overflow. It will generate a compare interrupt and/or event at the first count after the counter equals the Compare register value, and an overflow interrupt and/or event at the first count after the counter value equals the Period register value. The overflow will also reset the counter value to zero.
Using the same clock source as the RTC function, the PIT can request an interrupt or trigger an output event on every nth clock period (`n' can be selected from {4, 8, 16,.. 32768} for interrupts, and from {64, 128, 256,... 8192} for events).
Figure 2-1.Block Diagram
EXTCLK TOSC1 TOSC2
External Clock 32.768 kHz Crystal Osc
32.768 kHz Int. Osc
DIV32
RTC
CLKSEL
Correction counter
CLK_RTC 15-bit prescaler
PIT
PER =
CNT =
CMP
Overflow Compare
Period
The PIT and RTC functions are running off the same counter inside the prescaler. Writing the PRESCALER bit field in the RTC.CTRLA register configures the period of the clock signal that increments the CNT. The PERIOD bit field in RTC.PITCTRLA selects the bit from the 15-bit prescaler counter to be used as PIT period output.
� 2021 Microchip Technology Inc.
Technical Brief
DS90003213C-page 7
TB3213
RTC Overflow Interrupt
3. RTC Overflow Interrupt
This code example shows how to use the RTC with overflow interrupt enabled to toggle an LED. The overflow period is 500 ms. The on-board LED will be toggled each time the overflow interrupt occurs.
To operate the RTC, the source clock for the RTC counter must be configured before enabling the RTC peripheral and the desired actions (interrupt requests, output events). In this example, the 32.768 kHz external oscillator is used as the source clock.
To configure the oscillator, first, it must be disabled by clearing the ENABLE bit in the CLKCTRL.XOSC32KCTRLA register:
Figure 3-1.CLKCTRL.XOSC32KCTRLA � Clear the ENABLE Bit
The SEL and CSUT bits cannot be changed as long as the ENABLE bit is set or the XOSC32K Stable (XOSC32KS) bit in CLKCTRL.MCLKSTATUS is high. To change settings safely: Write a '0' to the ENABLE bit and wait until XOSC32KS is '0' before re-enabling the XOSC32K with new settings.
Bit
7
Access Reset
6
5
4
3
2
1
0
CSUT[1:0]
SEL
RUNSTDBY
ENABLE
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
Bit 0 � ENABLEEnable When this bit is written to '1', the configuration of the respective input pins is overridden to TOSC1 and TOSC2. Also, the Source Select (SEL) bit and Crystal Start-Up Time (CSUT) become read-only. This bit is I/O protected to prevent any unintentional enabling of the oscillator.
uint8_t temp; temp = CLKCTRL.XOSC32KCTRLA; temp &= ~CLKCTRL_ENABLE_bm; ccp_write_io((void*)&CLKCTRL.XOSC32KCTRLA, temp);
The user must then wait for the corresponding status bit to become `0': Figure 3-2.CLKCTRL.MCLKSTATUS � Read XOSC32KS
Bit
7
6
5
4
3
2
1
0
EXTS
XOSC32KS OSC32KS
OSC20MS
SOSC
Access
R
R
R
R
R
Reset
0
0
0
0
0
Bit 6 � XOSC32KS XOSC32K Status The Status bit will only be available if the source is requested as the main clock or by another module. If the oscillator
RUNSTDBY bit is set, but the oscillator is unused/not requested, this bit will be 0.
Value
Description
0
XOSC32K is not stable
1
XOSC32K is stable
while(CLKCTRL.MCLKSTATUS & CLKCTRL_XOSC32KS_bm) {
; }
Select the external oscillator by clearing the SEL bit in the CLKCTRL.XOSC32KCTRLA register:
� 2021 Microchip Technology Inc.
Technical Brief
DS90003213C-page 8
TB3213
RTC Overflow Interrupt
Figure 3-3.CLKCTRL.XOSC32KCTRLA � Clear the SEL Bit
Bit
7
Access Reset
6
5
4
3
2
1
0
CSUT[1:0]
SEL
RUNSTDBY
ENABLE
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
Bit 2 � SELSource Select
This bit selects the type of external source. It is write protected when the oscillator is enabled (ENABLE = 1).
Value
Description
0
External crystal
1
External clock on TOSC1 pin
temp = CLKCTRL.XOSC32KCTRLA; temp &= ~CLKCTRL_SEL_bm; ccp_write_io((void*)&CLKCTRL.XOSC32KCTRLA, temp);
Then, enable the oscillator by setting the ENABLE bit in the CLKCTRL.XOSC32KCTRLA register:
temp = CLKCTRL.XOSC32KCTRLA; temp |= CLKCTRL_ENABLE_bm; ccp_write_io((void*)&CLKCTRL.XOSC32KCTRLA, temp);
Afterward, the user must wait for all registers to be synchronized:
Figure 3-4.RTC.STATUS
Bit
7
6
5
4
3
CMPBUSY
Access
R
Reset
0
2 PERBUSY
R 0
1 CNTBUSY
R 0
0 CTRLABUSY
R 0
Bit 3 � CMPBUSY:Compare Synchronization Busy This bit is indicating whether the RTC is busy synchronizing the Compare register (RTC.CMP) in the RTC clock domain.
Bit 2 � PERBUSY:Period Synchronization Busy This bit is indicating whether the RTC is busy synchronizing the Period register (RTC.PER) in the RTC clock domain.
Bit 1 � CNTBUSY:Counter Synchronization Busy This bit is indicating whether the RTC is busy synchronizing the Count register (RTC.CNT) in the RTC clock domain.
Bit 0 � CTRLABUSY:Control A Synchronization Busy This bit is indicating whether the RTC is busy synchronizing the Control A register (RTC.CTRLA) in the RTC clock domain.
while (RTC.STATUS > 0) {
; }
The RTC period is set in the RTC.PER register:
� 2021 Microchip Technology Inc.
Technical Brief
DS90003213C-page 9
TB3213
RTC Overflow Interrupt
Figure 3-5.RTC.PER � Set Period
The RTC.PERL and RTC.PERH register pair represents the 16-bit value, PER. The low byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset +0x01. For more details on reading and writing 16-bit registers, refer to Accessing 16-bit Registers in the CPU section. Due to synchronization between the RTC clock and system clock domains, there is a latency of two RTC clock cycles from updating the register until this has an effect. The application software needs to check that the PERBUSY flag in RTC.STATUS is cleared before writing to this register.
Bit
15
14
13
12
11
10
9
8
PER[15:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
1
1
1
1
1
1
1
1
Bit
7
6
5
4
3
2
1
0
PER[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
1
1
1
1
1
1
1
1
Bits 15:8 � PER[15:8]Period High Byte These bits hold the MSB of the 16-bit Period register.
Bits 7:0 � PER[7:0]Period Low Byte These bits hold the LSB of the 16-bit Period register. The 32.768 kHz External Crystal Oscillator clock is selected in the RTC.CLKSEL register:
Figure 3-6.RTC.CLKSEL � Clock Selection
Bit
7
6
5
4
3
2
Access Reset
1
0
CLKSEL[1:0]
R/W
R/W
0
0
Bits 1:0 � CLKSEL[1:0]Clock Select bits
Writing these bits select the source for the RTC clock (CLK_RTC).
When configuring the RTC to use either XOSC32K or the external clock on TOSC1, XOSC32K needs to be enabled,
and the Source Select (SEL) bit and Run Standby (RUNSTDBY) bit in the XOSC32K Control A register of the Clock
Controller (CLKCTRL.XOSC32KCTRLA) must be configured accordingly.
Value
Name
Description
0x0
INT32K
32.768 kHz from OSCULP32K
0x1
INT1K
1.024 kHz from OSCULP32K
0x2
TOSC32K
32.768 kHz from XOSC32K or external clock from TOSC1
0x3
EXTCLK
External clock from the EXTCLK pin
RTC.CLKSEL = RTC_CLKSEL_TOSC32K_gc;
To enable the RTC to also run in Debug mode, the DBGRUN bit is set in the RTC.DBGCTRL register:
Figure 3-7.RTC.CLKSEL � Set the DBGRUN Bit
Bit
7
6
5
4
3
2
1
Access Reset
0 DBGRUN
R/W 0
Bit 0 � DBGRUN: Debug Run bit
Value 0 1
Description The peripheral is halted in Break Debug mode and ignores events The peripheral will continue to run in Break Debug mode when the CPU is halted
RTC.DBGCTRL |= RTC_DBGRUN_bm;
� 2021 Microchip Technology Inc.
Technical Brief
DS90003213C-page 10
TB3213
RTC Overflow Interrupt
The RTC prescaler is set in the RTC.CTRLA register. Set the RUNSTDBY bit in RTC.CTRLA to enable the RTC to also run in Standby mode. Set the RTCEN bit in RTC.CTRLA to enable the RTC.
Figure 3-8.RTC.CTRLA � Set the Prescaler, RUNSTDBY Bit, RTCEN Bit
Bit
7
6
RUNSTDBY
Access
R/W
R/W
Reset
0
0
5
4
PRESCALER[3:0]
R/W
R/W
0
0
3
2
1
CORREN
R/W
R/W
0
0
0 RTCEN
R/W 0
Bit 7 � RUNSTDBYRun in Standby
Value
Description
0
RTC disabled in Standby sleep mode
1
RTC enabled in Standby sleep mode
Bits 6:3 � PRESCALER[3:0]Prescaler bits
These bits define the prescaling of the CLK_RTC clock signal. Due to synchronization between the RTC clock and
system clock domains, there is a latency of two RTC clock cycles from updating the register until this has an effect.
The application software needs to check that the CTRLABUSY flag in RTC.STATUS is cleared before writing to this
register.
Value
Name
Description
0x0
DIV1
RTC clock/1 (no prescaling)
0x1
DIV2
RTC clock/2
0x2
DIV4
RTC clock/4
0x3
DIV8
RTC clock/8
0x4
DIV16
RTC clock/16
0x5
DIV32
RTC clock/32
0x6
DIV64
RTC clock/64
0x7
DIV128
RTC clock/128
0x8
DIV256
RTC clock/256
0x9
DIV512
RTC clock/512
0xA
DIV1024
RTC clock/1024
0xB
DIV2048
RTC clock/2048
0xC
DIV4096
RTC clock/4096
0xD
DIV8192
RTC clock/8192
0xE
DIV16384
RTC clock/16384
0xF
DIV32768
RTC clock/32768
Bit 0 � RTCENRTC Peripheral Enable
Value
Description
0
RTC peripheral disabled
1
RTC peripheral enabled
RTC.CTRLA = RTC_PRESCALER_DIV32_gc | RTC_RTCEN_bm | RTC_RUNSTDBY_bm;
Enable the overflow interrupt by setting the OVF bit in the RTC.INTCTRL register: Figure 3-9.RTC.INTCTRL � Set the OVF Bit
Bit
7
6
5
4
3
2
1
0
CMP
OVF
Access
R/W
R/W
Reset
0
0
Bit 0 � OVF Overflow Interrupt Enable Enable interrupt-on-counter overflow (i.e., when the Counter value (CNT) matches the Period value (PER) and wraps around to zero).
RTC.INTCTRL |= RTC_OVF_bm;
� 2021 Microchip Technology Inc.
Technical Brief
DS90003213C-page 11
TB3213
RTC Overflow Interrupt
For the interrupt to occur, the global interrupts must be enabled: sei();
The Interrupt Service Routine (ISR) for the RTC overflow will toggle an LED in the example below: ISR(RTC_CNT_vect) { RTC.INTFLAGS = RTC_OVF_bm; LED0_toggle(); }
Note: Clear the OVF bit from the RTC.INTFLAGS register by writing a `1' to it inside the ISR function.
Tip: The full code example is available in the Appendix section.
View the ATmega4809 Code Example on GitHub
Click to browse repository
An MCC generated code example for AVR128DA48, with the same functionality as the one described in this section, can be found here:
View the AVR128DA48 Code Example on GitHub
Click to browse repository
� 2021 Microchip Technology Inc.
Technical Brief
DS90003213C-page 12
TB3213
RTC Periodic Interrupt
4. RTC Periodic Interrupt
This code example shows how to use the PIT timing function of the RTC. The on-board LED will be toggled each second when the periodic interrupt occurs.
The source clock configuration for this particular example is the same as for the RTC overflow interrupt example. Enable the periodic interrupt by setting the PI bit in the RTC.PITINTCTRL register.
Figure 4-1.RTC.PITINTCTRL � Set the PI Bit
Bit
7
6
5
4
3
2
1
0
PI
Access
R/W
Reset
0
Bit 0 � PI: Periodic Interrupt bit
Value 0 1
Description The periodic interrupt is disabled The periodic interrupt is enabled
RTC.PITINTCTRL = RTC_PI_bm;
The PIT period is set in the RTC.PITCTRLA register. Enable the PIT by setting the PITEN bit in RTC.PITCTRLA.
Figure 4-2.RTC.PITCTRLA � Set the PITEN Bit
Bit
7
6
'
v
-
9
PERIOD[-:Y]
Access
RFW
RFW
RFW
RFW
Reset
Y
Y
Y
Y
8
Y
PITEN
RFW
Y
Bits 6:3 � PERIOD[3:0]: Period bits Writing this bit field selects the number of RTC clock cycles between each interrupt.
Value 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF
Name OFF CYCv CYC8 CYC86 CYC-9 CYC6v CYC898 CYC9'6 CYC'89 CYC8Y9v CYC9Yv8 CYCvY96 CYC8899 CYC86-8v CYC-9768 p
Description No interrupt v cycles 8 cycles 86 cycles -9 cycles 6v cycles 898 cycles 9'6 cycles '89 cycles 8Y9v cycles 9Yv8 cycles vY96 cycles 8899 cycles 86-8v cycles -9768 cycles Reserved
Bit 0 � PITEN: Periodic Interrupt Timer Enable bit Writing a `1' to this bit enables the Periodic Interrupt Timer.
RTC.PITCTRLA = RTC_PERIOD_CYC32768_gc | RTC_PITEN_bm;
� 2021 Microchip Technology Inc.
Technical Brief
DS90003213C-page 13
TB3213
RTC Periodic Interrupt
For the interrupt to occur, the global interrupts must be enabled: sei();
The Interrupt Service Routine (ISR) for the RTC PIT will toggle an LED in the example below: ISR(RTC_PIT_vect) { RTC.PITINTFLAGS = RTC_PI_bm; LED0_toggle(); }
Note: Clear the PI bit from the RTC.PITINTFLAGS register by writing a `1' to it inside the ISR function.
Tip: The full code example is available in the Appendix section.
View the ATmega4809 Code Example on GitHub
Click to browse repository
An MCC generated code example for AVR128DA48, with the same functionality as the one described in this section, can be found here:
View the AVR128DA48 Code Example on GitHub
Click to browse repository
� 2021 Microchip Technology Inc.
Technical Brief
DS90003213C-page 14
TB3213
RTC PIT Wake from Sleep
5. RTC PIT Wake from Sleep
This code example shows how to use the PIT timing function of the RTC to wake up the CPU from sleep. The on-board LED will be toggled each second when the periodic interrupt occurs, meaning it will be toggled when the CPU wakes up from sleep.
The sleep mode is configured in the SLPCTRL.CTRLA register. The sleep feature is enabled by setting the SEN bit in SLPCTRL.CTRLA.
Figure 5-1.SLPCTRL.CTRLA � Set the Sleep Mode, SEN Bit
Bit
7
6
5
4
3
2
1
0
SMODE[1:0]
SEN
Access
R
R
R
R
R
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bits 2:1 � SMODE[1:0] Sleep Mode
Writing these bits selects the sleep mode entered when the Sleep Enable (SEN) bit is written to '1', and the SLEEP instruction is executed.
Value
Name
Description
0x0
IDLE
Idle sleep mode enabled
0x1
STANDBY
Standby sleep mode enabled
0x2
PDOWN
Power-Down sleep mode enabled
other
-
Reserved
Bit 0 � SENSleep Enable This bit must be written to '1' before the SLEEP instruction is executed to make the MCU enter the selected sleep mode.
SLPCTRL.CTRLA |= SLPCTRL_SMODE_PDOWN_gc; SLPCTRL.CTRLA |= SLPCTRL_SEN_bm; The CPU can be put to sleep by calling the following function: sleep_cpu(); The PIT interrupt will wake the CPU from sleep. For the interrupt to occur, the global interrupts must be enabled: sei(); The Interrupt Service Routine (ISR) for the RTC PIT will toggle an LED in the example below: ISR(RTC_PIT_vect) {
RTC.PITINTFLAGS = RTC_PI_bm; LED0_toggle(); } Note: Clear the PI bit from the RTC.PITINTFLAGS register by writing a `1' to it inside the ISR function.
Tip: The full code example is available in the Appendix section.
View the ATmega4809 Code Example on GitHub
Click to browse repository
� 2021 Microchip Technology Inc.
Technical Brief
DS90003213C-page 15
TB3213
RTC PIT Wake from Sleep
An MCC generated code example for AVR128DA48, with the same functionality as the one described in this section, can be found here:
View the AVR128DA48 Code Example on GitHub
Click to browse repository
� 2021 Microchip Technology Inc.
Technical Brief
DS90003213C-page 16
TB3213
References
6. References
More information about the RTC and PIT operation modes can be found at the following links:
1. AVR128DA48 product page: www.microchip.com/wwwproducts/en/AVR128DA48 2. AVR128DA48 Curiosity Nano Evaluation Kit product page: https://www.microchip.com/Developmenttools/
ProductDetails/DM164151 3. AVR128DA28/32/48/64 Data Sheet 4. Getting Started with the AVR� DA Family 5. ATmega4809 product page: www.microchip.com/wwwproducts/en/ATMEGA4809 6. megaAVR� 0-series Family Data Sheet 7. ATmega809/1609/3209/4809 � 48-Pin Data Sheet megaAVR� 0-series 8. ATmega4809 Xplained Pro product page: https://www.microchip.com/developmenttools/ProductDetails/
atmega4809-xpro
� 2021 Microchip Technology Inc.
Technical Brief
DS90003213C-page 17
7. Appendix
Example 7-1.RTC Overflow Interrupt Code Example
/* RTC Period */ #define RTC_EXAMPLE_PERIOD
(511)
#include <avr/io.h> #include <avr/interrupt.h> #include <avr/cpufunc.h>
void RTC_init(void); void LED0_init(void); inline void LED0_toggle(void);
void RTC_init(void) {
uint8_t temp;
/* Initialize 32.768kHz Oscillator: */ /* Disable oscillator: */ temp = CLKCTRL.XOSC32KCTRLA; temp &= ~CLKCTRL_ENABLE_bm; /* Writing to protected register */ ccp_write_io((void*)&CLKCTRL.XOSC32KCTRLA, temp);
while(CLKCTRL.MCLKSTATUS & CLKCTRL_XOSC32KS_bm) {
; /* Wait until XOSC32KS becomes 0 */ }
/* SEL = 0 (Use External Crystal): */ temp = CLKCTRL.XOSC32KCTRLA; temp &= ~CLKCTRL_SEL_bm; /* Writing to protected register */ ccp_write_io((void*)&CLKCTRL.XOSC32KCTRLA, temp);
/* Enable oscillator: */ temp = CLKCTRL.XOSC32KCTRLA; temp |= CLKCTRL_ENABLE_bm; /* Writing to protected register */ ccp_write_io((void*)&CLKCTRL.XOSC32KCTRLA, temp);
/* Initialize RTC: */ while (RTC.STATUS > 0) {
; /* Wait for all register to be synchronized */ }
/* Set period */ RTC.PER = RTC_EXAMPLE_PERIOD;
/* 32.768kHz External Crystal Oscillator (XOSC32K) */ RTC.CLKSEL = RTC_CLKSEL_TOSC32K_gc;
/* Run in debug: enabled */ RTC.DBGCTRL |= RTC_DBGRUN_bm;
RTC.CTRLA = RTC_PRESCALER_DIV32_gc /* 32 */
| RTC_RTCEN_bm
/* Enable: enabled */
| RTC_RUNSTDBY_bm;
/* Run In Standby: enabled */
/* Enable Overflow Interrupt */ RTC.INTCTRL |= RTC_OVF_bm; }
void LED0_init(void) {
/* Make High (OFF) */ PORTB.OUT |= PIN5_bm; /* Make output */ PORTB.DIR |= PIN5_bm; }
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inline void LED0_toggle(void) {
PORTB.OUTTGL |= PIN5_bm; } ISR(RTC_CNT_vect) {
/* Clear flag by writing '1': */ RTC.INTFLAGS = RTC_OVF_bm; LED0_toggle(); } int main(void) { LED0_init(); RTC_init(); /* Enable Global Interrupts */ sei(); while (1) { } }
Example 7-2.RTC Periodic Interrupt Code Example #include <avr/io.h> #include <avr/interrupt.h> #include <avr/cpufunc.h> void RTC_init(void); void LED0_init(void); inline void LED0_toggle(void); void RTC_init(void) { uint8_t temp; /* Initialize 32.768kHz Oscillator: */ /* Disable oscillator: */ temp = CLKCTRL.XOSC32KCTRLA; temp &= ~CLKCTRL_ENABLE_bm; /* Writing to protected register */ ccp_write_io((void*)&CLKCTRL.XOSC32KCTRLA, temp); while(CLKCTRL.MCLKSTATUS & CLKCTRL_XOSC32KS_bm) { ; /* Wait until XOSC32KS becomes 0 */ } /* SEL = 0 (Use External Crystal): */ temp = CLKCTRL.XOSC32KCTRLA; temp &= ~CLKCTRL_SEL_bm; /* Writing to protected register */ ccp_write_io((void*)&CLKCTRL.XOSC32KCTRLA, temp); /* Enable oscillator: */ temp = CLKCTRL.XOSC32KCTRLA; temp |= CLKCTRL_ENABLE_bm; /* Writing to protected register */ ccp_write_io((void*)&CLKCTRL.XOSC32KCTRLA, temp); /* Initialize RTC: */ while (RTC.STATUS > 0) { ; /* Wait for all register to be synchronized */ } /* 32.768kHz External Crystal Oscillator (XOSC32K) */ RTC.CLKSEL = RTC_CLKSEL_TOSC32K_gc;
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/* Run in debug: enabled */ RTC.DBGCTRL = RTC_DBGRUN_bm; RTC.PITINTCTRL = RTC_PI_bm; /* Periodic Interrupt: enabled */ RTC.PITCTRLA = RTC_PERIOD_CYC32768_gc /* RTC Clock Cycles 32768 */
| RTC_PITEN_bm; /* Enable: enabled */ } void LED0_init(void) {
/* Make High (OFF) */ PORTB.OUT |= PIN5_bm; /* Make output */ PORTB.DIR |= PIN5_bm; } inline void LED0_toggle(void) { PORTB.OUTTGL |= PIN5_bm; } ISR(RTC_PIT_vect) { /* Clear flag by writing '1': */ RTC.PITINTFLAGS = RTC_PI_bm; LED0_toggle(); } int main(void) { LED0_init(); RTC_init(); /* Enable Global Interrupts */ sei(); while (1) { } }
Example 7-3.RTC PIT Wake from Sleep Code Example #include <avr/io.h> #include <avr/interrupt.h> #include <avr/sleep.h> #include <avr/cpufunc.h> void RTC_init(void); void LED0_init(void); inline void LED0_toggle(void); void SLPCTRL_init(void); void RTC_init(void) { uint8_t temp; /* Initialize 32.768kHz Oscillator: */ /* Disable oscillator: */ temp = CLKCTRL.XOSC32KCTRLA; temp &= ~CLKCTRL_ENABLE_bm; /* Writing to protected register */ ccp_write_io((void*)&CLKCTRL.XOSC32KCTRLA, temp); while(CLKCTRL.MCLKSTATUS & CLKCTRL_XOSC32KS_bm) { ; /* Wait until XOSC32KS becomes 0 */ } /* SEL = 0 (Use External Crystal): */
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temp = CLKCTRL.XOSC32KCTRLA; temp &= ~CLKCTRL_SEL_bm; /* Writing to protected register */ ccp_write_io((void*)&CLKCTRL.XOSC32KCTRLA, temp); /* Enable oscillator: */ temp = CLKCTRL.XOSC32KCTRLA; temp |= CLKCTRL_ENABLE_bm; /* Writing to protected register */ ccp_write_io((void*)&CLKCTRL.XOSC32KCTRLA, temp); /* Initialize RTC: */ while (RTC.STATUS > 0) {
; /* Wait for all register to be synchronized */ } /* 32.768kHz External Crystal Oscillator (XOSC32K) */ RTC.CLKSEL = RTC_CLKSEL_TOSC32K_gc; /* Run in debug: enabled */ RTC.DBGCTRL = RTC_DBGRUN_bm; RTC.PITINTCTRL = RTC_PI_bm; /* Periodic Interrupt: enabled */ RTC.PITCTRLA = RTC_PERIOD_CYC32768_gc /* RTC Clock Cycles 32768 */
| RTC_PITEN_bm; /* Enable: enabled */ } void LED0_init(void) {
/* Make High (OFF) */ PORTB.OUT |= PIN5_bm; /* Make output */ PORTB.DIR |= PIN5_bm; } inline void LED0_toggle(void) { PORTB.OUTTGL |= PIN5_bm; } ISR(RTC_PIT_vect) { /* Clear flag by writing '1': */ RTC.PITINTFLAGS = RTC_PI_bm; LED0_toggle(); } void SLPCTRL_init(void) { SLPCTRL.CTRLA |= SLPCTRL_SMODE_PDOWN_gc; SLPCTRL.CTRLA |= SLPCTRL_SEN_bm; } int main(void) { LED0_init(); RTC_init(); SLPCTRL_init(); /* Enable Global Interrupts */ sei(); while (1) {
/* Put the CPU in sleep */ sleep_cpu(); /* The PIT interrupt will wake the CPU */ } }
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8. Revision History
Document Revision Date
C
02/2021
B
12/2019
A
05/2019
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Revision History
Comments Updated the GitHub repository links, the References section, and the use cases sections. Added the AVR� DA Family Overview section. Added MCC versions for each use case, running on AVR128DA48. Other minor corrections. A write to the CCP registers is replaced by the ccp_write_io() function in the code. Initial document release.
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� 2021, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
ISBN: 978-1-5224-7542-2
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Quality Management System
For information regarding Microchip's Quality Management Systems, please visit www.microchip.com/quality.
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