ADSP-21565 Datasheet and Product Info | Analog Devices
Engineer-to-Engineer Note EE-418 Technical notes on using Analog Devices products and development tools Visit our Web resources http://www.analog.com/ee-notes and http://www.analog.com/processors or e-mail processor.support@analog.com or processor.tools.support@analog.com for technical support. ADSP-2156x Board Design Guidelines for Dynamic Memory Controller Contributed by Nishant Singh, Sachin-V Kumar Rev 2 September 10, 2020 Introduction This EE-note provides recommended board design practices for interfacing DDR memory and achieving expected performance from the controller. These guidelines should be used in addition to standard board-level design practices. Placement and General Routing Guidelines Use the following guidelines when designing PCB stack up, trace routing and component placement: Place the ADSP-2156x device and the memory as close as possible to each other while minimizing routing length. The ADSP-2156x DMC interface supports only point-to-point design and does not support fly-by topology. Plan the PCB stack-up such that all the DMC signals (address, command and control) have continuous reference planes (ground planes) on an immediately adjacent layer. Ensure that these signals do not travel across splits in the power/ground planes. It is better to increase the distance between the signal and its relevant planes than to implement the "cross split" routing. For better signal integrity, avoid power-planeto-signal-plane and power-plane-to-powerplane coupling. Strive to minimize this coupling. . The PCB trace characteristic impedance must be 50 for single-ended signals and 100 for differential signals, with a 5% tolerance. Route all DDR signals as a group in every layer to avoid a mismatch in trace impedance and propagation delay. Keep all grouped signals on the same layer. For example, the DMC_DQ00-07, DMC_LDQS, and DMC_LDQM signals should be routed as a group, in the same layer and having the same ground reference. Changing the ground reference plane can change the trace impedance. To avoid crosstalk, ensure that all DDR signals have center-to-center spacing of at least 3W between DDR signals and 4W to other signals, where W is the trace width. Maintain perpendicularity between DMC signals routing for different DMC signals routed in adjacent layers. This configuration reduces crosstalk, as signals on adjacent layers will not be parallel to each other. Avoid test points on the DDR signals, as they create stubs which can act as EMI sources. Instead, use vias for probing. It is also acceptable to use JEDEC-recommended methods that test vendors offer for diagnostics. To simplify routing, entire byte lanes can be swapped, but it should be ensured that all DQ , DQS, DM signals are substituted with each other (For example, DQ (7-0) DQ (15-8), DMC_LDQS DMC_UDQS, /DMC_LDQS Copyright 2020, Analog Devices, Inc. All rights reserved. Analog Devices assumes no responsibility for customer product design or the use or application of customers' products or for any infringements of patents or rights of others which may result from Analog Devices assistance. All trademarks and logos are property of their respective holders. Information furnished by Analog Devices applications and development tools engineers is believed to be accurate and reliable, however no responsibility is assumed by Analog Devices regarding technical accuracy and topicality of the content provided in Analog Devices Engineer-to-Engineer Notes /DMC_UDQS, DMC_UDM DMC_LDM). Within a byte lane, data bits can be swapped, with the exception of the lowest order bit (for example, DQ0 should be connected to DQ0 of the processor if lane swapping is not done). Swapping of address lines is not allowed. Trace Length-Matching Criteria The routing of all the DDR interface signals must be length-matched to avoid set-up and hold time violations due to propagation delay. The length-matching criteria are as follows: Match the trace length of all address (DMC_A [nn], DMC_BA[n]) and command (DMC_CKE, DMC_CS[n], DMC_ODT, DMC_RAS, DMC_RESET, DMC_WE) signals within +/- 40 mils relative to the DMC_CK signal. Match the trace length of all data (DMC_DQ [nn]) and data mask (DMC_UDM, DMC_LDM) signals within +/- 40 mils relative to their corresponding DQS signal. For example, match the trace length of the lower order data byte (DMC_DQ00 DMC_DQ07) and the corresponding data mask (DMC_LDM) signals with the lower order strobe (DMC_LDQS) signal. Match the trace length of differential signals such as clock (DMC_CK and /DMC_CK) and DQS pairs (DMC_LDQS and /DMC_LDQS, DMC_UDQS and /DMC_UDQS) within +/10 mils. For example, match the trace length of the DMC_CK and /DMC_CK signals within +/- 10 mils relative to each other. The maximum allowed trace length for DDR signals is 2 inches. for improved signal integrity. The DDR3/DDR3L data group signals do not require external termination because they have ODT. The termination guidelines are as follows: Install external series termination resistors on all address and control signals and place them as close as possible to the processor. The recommended value of the series termination resistors is 100 . This value can vary based on board routing. Select appropriate series termination resistor values, as well as ODT values, based on simulation results of the board. VTT Termination Use the following guidelines for VTT termination. These guidelines can differ from vendor to vendor. For DDR3/3L, VTT termination is recommended by JEDEC, as this mitigates signal reflection. The primary purpose of a VTT island is to prevent reflections at the memory device. Removing the VTT termination results in signal reflections. The removal can lead to higher than nominal voltages at the memory address or command input pins, which can damage or reduce the lifetime of the memory. Check with the appropriate memory vendor for devicespecific information. Implement VTT termination for the address and command lines as shown in Figure 1, Where RN1 is a resistor pack. Interface Termination All DDR interface signals without on-die termination (ODT) require external termination ADSP-2156x Board Design Guidelines for Dynamic Memory Controller (EE-418) Page 2 of 7 Perform a decoupling analysis of the VTT planes. Figure 1. VTT Termination for Address and Command Line The DMC_CK and /DMC_CK signals must be terminated using a differential termination scheme as shown in Figure 2. Figure 2. DMC clock differential termination VTT termination does not play a major role for the ADSP-2156x processor. It is mainly a requirement from the memory device. Any alternative that prevents reflections on the address or command bus is an acceptable substitute for VTT termination at the processor. Separate VTT and VREF islands by a minimum of 150 mils if placed on the same PCB layer. Placing the islands on different layers is preferred. Place VTT islands as close as possible to the memory device. VTT islands require at least two additional decoupling capacitors (4.7F) and two bulk capacitors (100F) at each end as shown in Figure 3. VTT island surface trace must have a minimum width of 150 mil minimum. A width of 250 mil is preferred. DMC Power (VDD_DMC) Decoupling Use the following guidelines for DMC power decoupling: The DMC interface should have enough decoupling on the VDD_DMC rail and the memory power rail to avoid data corruption. Refer to the DDR memory data sheet or consult the DDR memory vendor to identify the decoupling capacitor requirement for the DDR memory power rails. A critical parameter is Idd7, which defines the peak current during multi-bank operations and depends on the speed grade and ambient temperature of the DDR memory. Place all the decoupling capacitors very close to the VDD_DMC power rail and use solid power and ground planes. Ensure that the power and ground planes are adjacent to each other to provide the shortest return path and better power integrity. Isolate the DDR power planes from other supply planes. If this is not possible, separate them as much as possible and avoid overlapping them. Place individual power and ground vias from every power and ground pin of the ADSP2156x processor and the memory device to its associated plane. Place decoupling capacitors for the VDD_DMC power rail as close as possible to the actual power pins. This is very important because DDR signal slew rates are aggressive. Placing these capacitors close to the pin is mandatory. Provide dedicated power and ground vias for each decoupling capacitor pin, wherever possible. ADSP-2156x Board Design Guidelines for Dynamic Memory Controller (EE-418) Page 3 of 7 Ideally, the trace length from the power via to the processor pad should not exceed 30 mils. The maximum trace length from each power via to its decoupling capacitor is 60 mils. The maximum trace length from each power via to its power ball pad is 35 mils. Placement of the mid-bulk bypass capacitors (~10 F) is not critical. They can be placed to accommodate other circuitry with more constrained placement and routing requirements. Figure 3. VTT Supply and Decoupling Scheme DMC_VREF Voltage Supply DMC_VREF acts as a voltage reference for DDR3/DDR3L data signals and compares the difference between a steady reference voltage (DMC_VREF) and the signal received for identifying the logic. Hence, it is recommended to minimize noise on DMC_VREF. Route the DMC_VREF trace at least 40 mil away from high-speed signals and noisy power supply traces. Guard traces can be provided around the DMC_VREF trace, if required. Ensure that the guard traces have sufficient ground vias stitched to the main ground plane. Provide adequate decoupling near the DMC_VREF pins of the ADSP-2156x processor, as well as at the memory device. Keep the DMC_VREF trace as short as possible, with a width of at least 20 mils. Recommended ADSP-2156x DMC_VREF Filtering Scheme Figure 4 shows the RCR filtering scheme on DMC_VREF that is recommended for ADSP- ADSP-2156x Board Design Guidelines for Dynamic Memory Controller (EE-418) Page 4 of 7 2156x processors. As shown, DMC_VREF0 and DMC_VREF1 can be shorted together. PCB Placement and Routing Guidelines for the DMC_VREF Filter Network Use the following guidelines for the DMC_VREF filter network placement: Place the recommended RCR network between the DMC_VREF supply paths from the memory to the processor. Place the C (100 pF)-R (2 k) portion of the RCR network as close as possible to the ADSP-2156x DMC_VREF pin. Use a small package, preferably the 0402 size, for the 100pF capacitor to guarantee a high self-resonant frequency. Route the entire RCR network on one layer with no vias in the traces. Figure 4. DMC_VREF Filtering Network ADSP-2156x Board Design Guidelines for Dynamic Memory Controller (EE-418) Page 5 of 7 Figure 5. Recommended VREF Supply Circuit Memory-Side Recommendations for VREF Supply Use the following guidelines for DMC_VREF supply placement on the memory side. The requirements apply to both DDR3 and DDR3L. DDR3 memory has two VREF pins: VREFCA and VREFDQ. VREFCA serves as the reference for clock, address, command, and control signals. VREFDQ serves as the reference for strobe, data, and data mask signals VREFCA and VREFDQ can have a common supply source,but should be "STAR" routed and decoupled at the dedicated DRAM pins. Place two decoupling capacitors, 0.1 F and 0.01 F, for each VREF pin (VREFCA and VREFDQ). Place the 0.01 F capacitor closer to the DRAM pin, followed by the 0.1 F capacitor. Keep the length from the decoupling capacitor to the DRAM supply pin as short as possible. Maintain the trace width based on the peak current requirement of the DDR. Figure 5 shows the recommended VREF supply circuit for a DDR3 memory device. Routing Guidelines for Other High-Speed Interfaces Use the following recommendations for the highspeed peripherals (QSPI, Link Port, SPORT) signals routing. The recommendation for maximum trace length is 4 inches. The trace length should be matched within +/3 mils, between the clock and all other signals. This ensures that all the signals are fulfilling the required timings. The clock signal should be routed 3 times the trace width away from all other signals. This safeguard the clock signal from noise coupling. ADSP-2156x Board Design Guidelines for Dynamic Memory Controller (EE-418) Page 6 of 7 References [1] Interfacing DDR3/DDR2/LPDDR Memory to ADSP-SC5xx/215xx Processors (EE-387). Rev. 3, April 2018. Analog Devices, Inc. [2] ADZS-21569 EZ-Kit® Schematic, Rev B, Sep 2017. Analog Devices, Inc. Document History Revision Rev 2 September 10, 2020 by Sachin-V Kumar Rev 1 January 15, 2020 by Sachin-V Kumar Description Added new section "Routing Guidelines for Other High-Speed Interfaces" Minor changes in "VTT Termination" Added a new note in "Placement and General Routing Guidelines" Minor changes in "Figure 3" Initial Release ADSP-2156x Board Design Guidelines for Dynamic Memory Controller (EE-418) Page 7 of 7Analog Devices, Inc. Adobe PDF Library 15.0