File info: application/pdf · 749 pages · 23.10MB
1990 400023 FAST Advanced Schottky TTL Logic Databook
Index of /components/national/ dataBooks
Extracted Text
400023
~ ~ Semaictoinodunctaorl
A Corporate Dedication to Quality and Reliability
National Semiconductor is an industry leader in the manufacture of high quality, high reliability integrated circuits. We have been the leading proponent of driving down IC defects and extending product lifetimes. From raw material through product design, manufacturing and shipping, our quality and reliability is second to none. We are proud of our success ... it sets a standard for others to achieve. Yet, our quest for perfection is ongoing so that you, our customer, can continue to rely on National Semiconductor Corporation to produce high quality products for your design systems.
Charles E. Sporck President, Chief Executive Officer National Semiconductor Corporation
Wir fUhlen uns zu Qualitat und Zuverlassigkeit verpflichtet
National Semiconductor Corporation ist fOhrend bei der Herstellung von integrierten Schaltungen hoher Qualitat und hoher Zuverlassigkeit. National Semiconductor war schon immer Vorreiter, wenn es gait, die Zahl von IC Ausfallen zu verringern und die Lebensdauern von Produkten zu verbessern. Vom Rohmaterial Ober Entwurf und Herstellung bis zur Auslieferung, die Qualitat und die Zuverlassigkeit der Produkte von National Semiconductor sind unObertroffen. Wir sind stolz auf unseren Erfolg, der Standards setzt, die Hir andere erstrebenswert sind. Auch ihre AnsprOche steigen standig. Sie als unser Kunde konnen sich auch weiterhin auf National Semiconductor verlassen.
La Qualite et La Fiabilite:
Une Vocation Commune Chez National Semiconductor Corporation
National Semiconductor Corporation est un des leaders industriels qui fabrique des circuits integres d'une tres grande qualite et d'une fiabilite exceptionelle. National a ete le premier a vouloir faire chuter le nombre de circuits integres defectueux et a augmenter la duree de vie des produits. Depuis les matieres premieres, en passant par la conception du produit sa fabrication et son expedition, partout la qualite et la fiabilite chez National sont sans equivalents. Nous sommes tiers de notre succes et le standard ainsi defini devrait devenir l'objectif a atteindre par les autres societes. Et nous continuons a vouloir faire progresser notre recherche de la perfection; ii en resulte que VOUS, qui etes notre client, pouvez toujours faire confiance a National Semiconductor Corporation, en produisant des systemes d'une tres grande qualite standard.
Un lmpegno Societario di Qualita e Affidabilita
National Semiconductor Corporation e un'industria al vertice nella costruzione di circuiti integrati di alta qualita ed affidabilita. National e stata ii principale promotore per l'abbattimento della difettosita dei circuiti integrati e per l'allungamento della vita dei prodotti. Dal mat'3riale grezzo attraverso tutte le fasi di progettazione, costruzione e spedizione, la qualita e affidabilita National non e seconda a nessuno.
Noi siamo orgogliosi del nostro successo che fissa per gli altri un traguardo da raggiungere. II nostro desiderio di perfezione e d'altra parte illimitato e pertanto tu, nostro cliente, puoi continuare ad affidarti a National Semiconductor Corporation per la produzione dei tuoi sistemi con elevati livelli di qualita.
Charles E. Sporck President, Chief Executive Officer National Semiconductor Corporation
FAST DATABOOK
1990 Edition
Circuit Characteristics
II
Ratings, Specifications, and Waveforms
El
Design Considerations
El
Advanced Schottky TTL Datasheets
II
Ordering Information and
r.m
Physical Dimensions
E.m
iii
TRADEMARKS
Following is the most current list of National Semiconductor Corporation's trademarks and registered trademarks.
ABiCTM AbuseableTM AnadigTM ANS-R-TRANTM APPSTM ASPECTTM Auto-Chem DeflasherTM BCPTM Bl-FETTM Bl-FETllTM Bl-LINETM Bl PLANTM BLCTM BLXTM BMACTM Brite-LiteTM BSITM BTLTM CODTM CheckTrackTM CIMTM CIMBUSTM CLAS ICTM ClockvChekTM COMBO� COMBO ITM COMBO IITM COPSTM microcontrollers CRDTM DA4TM Datachecker� DENSPAKTM DIBTM Digitalker� DISCERNTM DISTILLTM DNR�
DPVMTM E2CMOSTM ELSTARTM
Embedded System ProcessorTM
E-Z-LINKTM FACTTM FACT Quiet SeriesTM FAIRCADTM FairtechTM FAST� 5-Star ServiceTM FlashTM GENIXTM GNXTM GTOTM HAMRTM HandiScanTM HEX3000TM HPCTM 13L�
ICMTM IN FOCH EXTM Integral ISETM lntelisplayTM ISETM ISE/06TM ISE/08TM ISE/16TM ISE32TM ISOPLANARTM ISOPLANAR-ZTM KeyScanTM LMCMOSTM M2CMOSTM MacrobusTM MacrocomponentTM MAXI-ROM� MeatvChekTM MenuMasterTM MicrobusTM data bus MICRO-DACTM �talkerTM
MicrotalkerTM MICROWIRETM MICROWIRE/PLUSTM MOLETM MPATM MSTTM Naked-8TM National� National Semiconductor� National Semiconductor
Corp.� NAX800TM Nitride PlusTM Nitride Plus OxideTM NMLTM NOB USTM NSC800TM NSCISETM NSX-16TM NS-XC-16TM NTERCOMTM NU RAMTM OXISSTM P2CMOSTM PC MasterTM Perfect WatchTM PharmavChekTM PLANTM PLANARTM PLAYERTM Plus-2TM PolycraftTM POSilinkTM POSitalkerTM
Power + ControlTM
POWERplanarTM QUAD3000TM QUIKLOOKTM RATTM RTX16TM
SABRTM ScriptvChekTM SCXTM SERIES/800TM Series 900TM Series 3000TM Series 32000� ShelfvChekTM Simple SwitcherTM SofChekTM SONICTM SPIRETM Staggered RefreshTM STARTM StarlinkTM STARPLEXTM Super-BlockTM SuperChipTM SuperScriptTM SYS32TM TapePak� TDSTM TeleGateTM The National Anthem� TimevChekTM TINATM TLCTM TrapezoidalTM TRI-CODETM TRI-POLYTM TRI-SAFETM TRI-STATE� TURBOTRANSCEIVERTM VIPTM VR32TM WATCHDOGTM XMOSTM XPUTM
ZSTARTM 883B/RETSTM 883S/RETSTM
Ethernet� is a registered trademark of Xerox Corporation.
LIFE SUPPORT POLICY
NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITIEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
NationalSemiconductorCorporation 2900 Semiconductor Drive, P.O. Box 58090, Santa Clara, California 95052-8090 (408) 721-5000 TWX (910) 339-9240
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied, and National reserves the right, at any time without notice, to change said circuitry or specifications.
iv
-I
ll>
Table of Contents
C"
-CD'
0 0
Fairchild Advanced Schottky TTL, FAST�, is a family of TTL circuits that exhibits a combination of performance and efficiency unapproached by any other TTL family. Made with the
:0:s
('I)
-::s -0
proven lsoplanar process, 54F/7 4F circuits offer the switch-
ing speed and output drive capability of Schottky TTL, with
superior noise margins and only one-fourth the power con-
sumption.
Product Index and Selection Guide
Lists 54F/74F circuits currently available, in design or planned. The Selection Guide groups the circuits by function.
Section 1 Circuit Characteristics ............... 1-1
Discusses FAST technology, circuit configurations and characteristics.
Section 2 Ratings, Specifications and Waveforms . ......................... 2-1
Contains common ratings and specifications for FAST devices, as well as AC test load and waveforms.
Section 3 Design Considerations .... ........... 3-1
Provides the designer with useful guidelines for dealing with transmission and other high speed design concerns.
Section 4 Data Sheets ......................... 4-1
Contains data sheets for currently available and pending new products.
Section 5
Ordering Information and Package Outlines, Field Sales Offices, Representatives and Distributor Locations . . . . . . . . . . . . 5-1
Explains simplified purchasing code which identifies device type, package type and temperature range. Contains detailed physical dimension drawings for each package.
v
(/)
c
~ ~National
:; U Semiconductor
c
(/)
:::s
-b3 -(.)
Product Status Definitions
:::s
"C
0
Ii.. Definition of Terms
Data Sheet Identification
Advance� Information
Product Status
Formative or In Design
Definition
This data sheet contains the design specifications for product development. Specifications may change in any manner without notice.
First Production
This data sheet contains preliminary data, and supplementary data will be published at a later date. National Semiconductor Corporation reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Full Production
This data sheet contains final specifications. National Semiconductor Corporation reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
National Semiconductor Corporation reserves the right to make changes without further notice to any products herein to improve reliability, function or design. National does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others.
vi
Alpha-Numeric Index
29F52 8-Bit Registered Transceiver ........................................................ 4-637 29F53 8-Bit Registered Transceiver ........................................................ 4-637 29F68 Dynamic RAM Controller ........................................................... 4-643 54F/74FOO Quad 2-lnput NANO Gate ........................................................ 4-6 54F/74F02 Quad 2-lnput NOR Gate ......................................................... 4-9 54F/74F04 Hex Inverter ................................................................... 4-12 54F/74F08 Quad 2-lnput AND Gate ........................................................ 4-15 54F/74F10 Triple 3-lnput NANO Gate ....................................................... 4-18 54F/74F11 Triple 3-lnput AND Gate ........................................................ 4-21 54F/74F13 Dual 4-lnput NANO Schmitt Trigger ............................................... 4-24 54F/74F14 Hex Inverter Schmitt Trigger ..................................................... 4-27 54F/74F20 Dual 4-lnput NANO Gate ........................................................ 4-30 54F/74F27 Triple 3-lnput NOR Gate ........................................................ 4-33 54F/74F30 8-lnput NANO Gate ............................................................ 4-36 54F/74F32 Quad 2-lnput OR Gate .......................................................... 4-39 54F/74F37 Quad 2-lnput NANO Buffer ...................................................... 4-42 54F/74F38 Quad 2-lnput NANO Buffer (Open Collector) ....................................... 4-45 54F/74F40 Dual 4-lnput NANO Buffer ....................................................... 4-48 54F/74F51 2-2-2-3 AND-OR-Invert Gate .................................................... 4-51 54F/74F64 4-2-3-2-lnput AND-OR-Invert Gate ............................................... 4-54 54F/74F74 Dual D-Type Positive Edge-Triggered Flip-Flop .................................... 4-57 54F/74F86 Quad 2-lnput Exclusive-OR Gate ................................................. 4-61
54F/74F109 Dual JK Positive Edge-Triggered Flip-Flop ....................................... 4-64
54F/74F112 Dual JK Negative Edge-Triggered Flip-Flop ...................................... 4-68 54F/74F113 Dual JK Negative Edge-Triggered Flip-Flop ...................................... 4-72 54F/74F114 Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears ......... 4-76 54F/74F125 Quad Buffer (TRI-STATE) ...................................................... 4-80 54F/74F132 Quad 2-lnput NANO SchmittTrigger ............................................. 4-83 54F/74F138 1-of-8 Decoder/Demultiplexer .................................................. 4-86 54F/74F139 Dual 1-of-4 Decoder/Demultiplexer ............................................. 4-90 54F/74F148 8-Line to 3-Line Priority Encoder ................................................ 4-94 54F/74F151A 8-lnput Multiplexer .................................... ~ ...................... 4-98 54F/74F153 Dual 4-lnput Multiplexer ...................................................... 4-102 54F/74F157A Quad 2-lnput Multiplexer .................................................... 4-106 54F/74F158A Quad 2-lnput Multiplexer (Inverted) ........................................... 4-110 54F/74F160A Synchronous Presettable BCD Decade Counter (Asynchronous Reset) ............ 4-114 54F/74F161A Synchronous Presettable Binary Counter (Asynchronous Reset) .................. 4-121 54F/74F162A Synchronous Presettable BCD Decade Counter (Synchronous Reset) ............. 4-114 54F/7 4F163A Synchronous Presettable Binary Counter (Synchronous Reset) ................... 4-121 54F/74F164A Serial-In, Parallel-Out Shift Register ........................................... 4-127 54F/74F168 4-Stage Synchronous Bidirectional Counter ..................................... 4-131 54F/74F169 4-Stage Synchronous Bidirectional Counter ..................................... 4-131 54F/74F174 Hex D Flip-Flop with Master Reset ............................................. 4-137 54F/74F175 Quad D Flip-Flop ............................................................ 4-141 54F/74F181 4-Bit Arithmetic Logic Unit .................................................... 4-145 54F/74F182 Carry Lookahead Generator .................................................. 4-151 54F/74F189 64-Bit Random Access Memory with TRI-STATE Outputs ......................... 4-156 54F/74F190 Up/Down Decade Counter with Preset and Ripple Clock .......................... 4-160 54F/74F191 Up/Down Binary Counter with Preset and Ripple Clock ........................... 4-165 54F/74F192 Up/Down Decade Counter with Separate Up/Down Clocks ....................... 4-170 54F/74F193 Up/Down Binary Counter with Separate Up/Down Clocks ......................... 4-175
vii
Alpha-Numeric lndex(conunued)
54F/74F194 4-Bit Bidirectional Universal Shift Register ...................................... 4-180 54F/74F219 64-Bit Random Access Memory with TRI-STATE Outputs ......................... 4-184 54F /7 4F240 Octal BufferI Line Driver with TRI-STATE Outputs (Inverting) ...................... 4-188 54F/74F241 Octal Buffer/Line Driver with TRI-STATE Outputs ................................ 4-188 54F /7 4F243 Quad Bus Transceiver with TRI-STATE Outputs ........................ �......... 4-192 54F/74F244 Octal Buffer/Line Driver with TRI-STATE Outputs ................................ 4-188 54F/74F245 Octal Bidirectional Transceiver with TRI-STATE Outputs .......................... 4-195 54F/74F251A 8-lnput Multiplexer with TRI-STATE Outputs ................................... 4-199 54F/74F253 Dual 4-Bit Multiplexer with TRI-STATE Outputs .................................. 4-203 54F /7 4F257A Quad 2-lnput Multiplexer with TRI-STATE Outputs .............................. 4-207 54F /74F258A Quad 2-lnput Multiplexer with TRI-STATE Outputs (Inverting) .................... 4-211 54F/74F269 8-Bit Bidirectional Binary Counter .............................................. 4-215 54F /7 4F273 Octal D Flip-Flop ............................................................ 4-219 54F/74F280 9-Bit Parity Generator/Checker ................................................ 4-223 54F/74F283 4-Bit Binary Full Adder with Fast Carry .......................................... 4-227 54F /74F299 Octal Universal Shift/Storage Register with Common Parallel 1/0 Pins .............. 4-232 54F/74F322 Octal Serial/Parallel Register with Sign Extend .................................. 4-237 54F/74F323 Octal Universal Shift/Storage Register with Synchronous Reset and Common 1/0
Pins ................................................................................. 4-242 54F/74F350 4-Bit Shifter with TRI-STATE Outputs ........................................... 4-247 54F/74F352 Dual 4-lnput Multiplexer ...................................................... 4-253 54F/74F353 Dual 4-lnput Multiplexer with TRI-STATE Outputs ................................ 4-257 54F/74F365 Hex Buffer/Driver with TRI-STATE Outputs .............................. , ...... 4-261 54F/74F366 Hex Inverter/Buffer with TRI-STATE Outputs .................................... 4-264 54F/74F368 Hex Inverter/Buffer with TRI-STATE Outputs .................................... 4-264 54F/7 4F373 Octal Transparent Latch with TRI-STATE Outputs ............................... 4-268 54F/74F374 Octal D-Type Flip-Flop with TRI-STATE Outputs ................................. 4-272 54F/74F377 Octal D-Type Flip-Flop with Clock Enable ....................................... 4-276 54F/74F378 Parallel D Register with Enable ................................................ 4-280 54F/74F379 Quad Parallel Register with Enable ............................................. 4-284 54F/74F381 4-Bit Arithmetic Logic Unit .................................................... 4-288 54F/74F382 4-Bit Arithmetic Logic Unit .................................................... 4-294 54F/74F384 8-Bit Serial/Parallel Twos' Complement Multiplier ................................ 4-300 54F/74F385 Quad Serial Adder/Subtracter ................................................. 4-306 54F/74F398 Quad 2-Port Register ......................................................... 4-311 54F/74F399 Quad 2-Port Register ......................................................... 4-311 54F/74F401 Cyclic Redundancy Check Generator/Checker .................................. 4-316 54F/74F402 Serial Data Polynomial Generator/Checker ..................................... 4-321 54F/74F403A 16 x 4 First-In First-Out Buffer Memory ........................................ 4-329 54F /74F407 Data Access Register ........................................................ 4-346 54F/74F410 Register Stack-16 x 4 RAM TRI-STATE Output Register ......................... 4-353 54F/74F412 Multi-Mode Buffered 8-Bit Latch with TRI-STATE Outputs ......................... 4-357 54F/74F413 64 x 4 First-In First-Out Buffer Memory with Parallel 1/0 ........................... 4-362 54F/74F420 Paralleled Check Bit/Syndrome Bit Generator ................................... 4-366 54F/74F432 Multi-Mode Buffered 8-Bit Latch with TRI-STATE Outputs ......................... 4-371 54F/74F433 64 x 4 First-In First-Out Buffer Memory ......................................... 4-377 54F/74F521 8-Bit Identity Comparator ..................................................... 4-391 54F/7 4F524 8-Bit Registered Comparator .................................................. 4-395 54F/74F525 16-Bit Programmable Counter ................................................. 4-402 54F/74F533 Octal Transparent Latch with TRI-STATE Outputs ............................... 4-409 54F /74F534 Octal D Flip-Flop with TRI-STATE Outputs ...................................... 4-413
viii
Alpha-Numeric lndex(continued)
54F/74F5371-of-10 Decoder with TRI-STATE Outputs ...................................... 4-417 54F/74F5381-of-8 Decoder with TRI-STATE Outputs ........................................ 4-421 54F/74F539 Dual 1-of-4 Decoder with TRI-STATE Outputs ................................... 4-425 54F/74F540 Octal Buffer/Line Driver with TRI-STATE Outputs (Inverting) ...................... 4-429 54F/74F541 Octal Buffer/Line Driver with TRI-STATE Outputs ................................ 4-429 54F/74F543 Octal Registered Transceiver ................................................. 4-433 54F/74F544 Octal Registered Transceiver (Inverting in Both Directions) ........................ 4-438 54F/74F545 Octal Bidirectional Transceiver with TRI-STATE Outputs .......................... 4-443 54F/74F547 Octal Decoder/Demultiplexer with Address Latches and Acknowledge ............. 4-446 54F/74F548 Octal Decoder/Demultiplexer with Acknowledge ................................. 4-451 54F/74F550 Octal Registered Transceiver with Status Flags .................................. 4-455 54F/74F551 Octal Registered Transceiver with Status Flags .................................. 4-455 54F/74F552 Octal Registered Transceiver with Parity and Flags ............................... 4-461 54F/74F563 Octal D-Type Latch with TRI-STATE Outputs .................................... 4-466 54F/74F564 Octal D-Type Flip-Flop with TRI-STATE Outputs ................................. 4-470 54F/74F568 4-Bit Bidirectional Decade Counter with TRI-STATE Outputs ...................... 4-474 54F/74F569 4-Bit Bidirectional Binary Counter with TRI-STATE Outputs ........................ 4-474 54F/74F573 Octal D-Type Latch with TRI-STATE Outputs .................................... 4-485 54F/74F574 Octal D-Type Flip-Flop with TRI-STATE Outputs ................................. 4-489 54F/74F579 8-Bit Bidirectional Binary Counter with TRI-STATE Outputs ........................ 4-493 54F/74F582 4-Bit BCD Arithmetic Logic Unit. ............................................... 4-494 54F/74F583 4-Bit BCD Adder ............................................................. 4-498 54F/74F588 Octal Bidirectional Transceiver with IEEE-488 Termination Resistors and
TRI-STATE Inputs/Outputs ............................................................. 4-502 54F/74F620 Inverting Octal Bus Transceiver with TRI-STATE Outputs ......................... 4-506 54F/74F623 Inverting Octal Bus Transceiver with TRI-STATE Outputs ......................... 4-506 54F/74F632 32-Bit Parallel Error Detection and Correction Circuit ............................. 4-51 O 54F/74F640 Octal Bus Transceiver with TRI-STATE Outputs ................................. 4-522 54F/74F643 Octal Bus Transceiver with TRI-STATE Outputs ................................. 4-522 54F/74F645 Octal Bus Transceiver with TRI-STATE Outputs ................................. 4-522 54F/74F646 Octal Transceiver/Register with TRI-STATE Outputs ............................. 4-527 54F/74F648 Octal Transceiver/Register with TRI-STATE Outputs ............................. 4-527 54F/74F651 Octal Transceiver/Register with TRI-STATE Outputs (Inverting) ................... 4-534 54F/74F652 Octal Transceiver/Register with TRI-STATE Outputs ............................. 4-534 54F/74F657 Octal Bidirectional Transceiver with 8-Bit Parity Generator/Checker and
TRI-STATE Outputs ................................................................... 4-540 54F/74F673A 16-Bit Serial-In, Serial/Parallel-Out Shift Register (Common Serial 110 Pin) ........ 4-545 54F/74F675A 16-Bit Serial-In, Serial/Parallel-Out Shift Register ............................... 4-550 54F/74F676 16-Bit Serial/Parallel-In, Serial-Out Shift Register ................................ 4-554 54F/74F779 8-Bit Bidirectional Binary Counter with TRI-STATE Outputs ........................ 4-558 54F/74F784 8-Bit Serial/Parallel Multiplier with Adder/Subtracter ............................. 4-559 54F/74F794 8-Bit Register with Readback .................................................. 4-565 54F/74F821 10-Bit 0-Type Flip-Flop ....................................................... 4-569 54F/74F823 9-Bit D-Type Flip-Flop ........................................................ 4-573 54F/74F825 8-Bit D-Type Flip-Flop ........................................................ 4-577 54F/74F82710-Bit Buffer/Line Driver ...................................................... 4-581 54F/74F828 10-Bit Buffer/Line Driver ...................................................... 4-581 54F/74F841 10-Bit Transparent Latch ..................................................... 4-586 54F/74F843 9-Bit Transparent Latch ...................................................... 4-590 54F/74F845 8-Bit Transparent Latch ...................................................... 4-594 54F/74F899 9-Bit Latchable Transceiver with Parity Generator/Checker ....................... 4-599
ix
Alpha-Numeric lndex(continued>
54F/74F9681 Megabit Dynamic RAM Controller ............................................ 4-609 54F/74F2241 Octal Buffer/Line Driver with 250 Series Resistors in the Outputs ................. 4-621 54F/74F2243 Quad Bus Transceiver with 250 Resistors in the Outputs ........................ 4-625 54F/74F2244 Octal Buffer/Line Driver with 250 Series Resistors in the Outputs .................. 4-621 54F/74F2620 Inverting Octal Bus Transceiver with 250 Resistors in the Outputs ................ 4-628 54F/74F2623 Inverting Octal Bus Transceiver with 250 Resistors in the Outputs ................ 4-628 54F/74F2640 Octal Bus Transceiver with 250 Resistors in the Outputs ........................ 4-632 54F/74F2643 Octal Bus Transceiver with 250 Resistors in the Outputs ........................ 4-632 54F/74F2645 Octal Bus Transceiver with 250 Resistors in the Outputs ........................ 4-632
x
~National Semiconductor FAST� Product Selection Guide
Gates
Function
NANO/NANO Buffer
Quad 2-lnput NANO Triple 3-lnput NANO Dual 4-lnput NANO Schmitt Trigger Dual 4-lnput NANO 8-lnput NANO Quad 2-lnput Positive NANO Buffer Quad 2-lnput NANO Buffer (OC) Dual 4-lnput Positive NANO Buffer Quad 2-lnput Positive NANO Schmitt Trigger AND
Quad 2-lnput AND Triple 3-lnput AND
OR/NOR/Exclusive-OR
Quad 2-lnput NOR Triple 3-lnput NOR Quad 2-lnput OR Quad 2-lnput Exclusive-OR
Invert/AND-OR-Invert Hex Inverter Hex Schmitt Trigger Inverter Dual AND-OR-Invert AND-OR-Invert
Device
54F/74FOO 54F/74F10 54F/74F13 54F/74F20 54F/74F30 54F/74F37 54F/74F38 54F/74F40 54F/74F132
54F/74F08 54F/74F11
54F/74F02 54F/74F27 54F/74F32 54F/74F86
54F/74F04 54F/74F14 54F/74F51 54F/74F64
Dual Edge Triggered Flip Flops
Function
Dual D Positive Dual JK Positive Dual JK Negative DualJK Dual JK Negative (Common Clocks & Clears)
Device
54F/74F74 54F/74F109 54F/74F112 54F/74F113 54F/74F114
Inputs/ Gate
2 3 4 4 8 2 2 4 2
2 3
2 3 2 2
3/3/2/2 4/2/3/2
No.of Gates
4 3 2 2
4 4 2 4
4 3
4 3 4 4
6 6
Clock Inputs
_/
_/
""""'-""""'-""""'--
Direct Set
Yes Yes Yes Yes Yes
Direct Clear Yes Yes Yes
Yes
.,,
)>
,,(/)
-I
.,
-a0nc.
(/) CD
-CnD"
s�
::s
C>
cc :
Leads
CD
14 14 14 14 14 14 14 14 14
14 14
14 14 14 14
14 14 14 14
Leads
14 16 16 14 14
xi
Q)
"C
~ Multiple Flip-Flops
c:
:;0::;
Function
(,)
Q)
-a;
en
(,)
Hex D Flip-Flop Quad D Flip-Flop Octal D Flip-Flop
:::s Octal D Flip-Flop
".0C..
Octal D Flip-Flop w/Clock Enable
c.. Parallel D Register w/Enable
1cn-
Parallel D Register w/Enable
<( Octal D Flip-Flop
LL
Octal D Flip-Flop
Octal D Flip-Flop
10-Bit D Flip-Flop
9-Bit D Flip-Flop
8-Bit D Flip-Flop
Device
54F/74F174 54F/74F175 54F/74F273 54F/74F374 54F/74F377 54F/74F378 54F/74F379 54F/74F534 54F/74F564 54F/74F574 54F/74F821 54F/74F823 54F/74F825
Clock Inputs
_r _r
_/ _/
_r
_/
_r
_/ _/ _/ _/ _/ _/
Master Reset
Yes Yes Yes
Yes Yes
Broadside Pinout
Yes Yes Yes Yes Yes
TRI-STATE� Outputs
Yes
Yes Yes Yes Yes Yes Yes
Leads
16 16 20 20 20 16 16 20 20 20 24 24 24
Registers
Function
Parallel D Register w/Enable Quad Parallel D Register w/Enable Quad 2-Port Register Quad 2-Port Register Serial Data Polynomial Generator/Checker Data Access Register Register Stack-16 x 4 RAM TRI-STATE Output Register 8-Bit Register with Readback
Device
54F/74F378 54F/74F379 54F/74F398 54F/74F399 54F/74F402 54F/74F407 54F/74F410 54F/74F794
Clock Inputs
_/ _/ _/ _/ _/ _/ _/ _/
Leads
16 16 20 16 16 24 18 20
Latches
Function
Octal Latch Multimode Buffered 8-Bit Latch Multimode Buffered 8-Bit Latch Octal D Latch Octal D Latch Octal D Latch 10-Bit D Latch 9-Bit D Latch 8-Bit D Latch
Device
54F/74F373 54F/74F412 54F/74F432 54F/74F533 54F/74F563 54F/74F573 54F/74F841 54F/74F843 54F/74F845
Enable Inputs 1(L) & 1(H)
1(L) & 1(H) 1(L) & 1(H) 1(L) & 1(H) 1(L) & 1(H) 1(L) & 1(H) 3(L) & 1(H)
Broadside Pin out
Yes Yes Yes Yes Yes
Inverting
Yes Yes Yes
TRI-STATE Outputs
Yes Yes Yes Yes Yes Yes Yes Yes Yes
Leads
20 24 24 20 20 20 24 24 24
xii
-n
)>
Counters
CJ)
-f
Function
Presettable 4-Bit BCD Decade Presettable 4-Bit Binary
Device
54F/74F160A 54F/74F161A
Parallel Entry
s s
Reset
A A
Up/ Down
TRI-STATE Outputs
Leads
16 16
.".t..J
-cc0 .
(") CJ)
Presettable 4-Bit BCD Decade Presettable 4-Bit Binary 4-Bit BCD Decade
54F/74F162A
s
54F/74F163A
s
54F/74F168
s
s s
Yes
16 16 16
C1>
-(ii'"
(")
a�
4-Bit Binary
54F/74F169
s
Yes
16
::::J
4-Bit BCD Decade w/Preset & Ripple Clock
54F/74F190
A
Yes
4-Bit Binary w/Preset & Ripple Clock
54F/74F191
A
16 16
acC>:
4-Bit BCD Decade w/Separate Up/Down Clocks 54F/74F192
A
A
Yes
16
C1>
4-Bit Binary w/Separate Up/Down Clocks
54F/74F193
A
A
Yes
16
8-Bit Binary
54F/74F269
s
Yes
24
16-Stage Programmable 4-Bit BCD Decade 4-Bit Binary 8-Bit Binary 8-Bit Binary
54F/74F525
A
28
54F/74F568
s
SIA
Yes
Yes
20
54F/74F569
s
SIA
Yes
Yes
20
54F/74F579
s
s
Yes
Yes
20
54F/74F779
s
Yes
Yes
16
S = Synchronous A = Asynchronous
Shift Registers
Function
Shift Right, Serial-In, Parallel-Out Bidirectional, Universal Universal Octal Shift/Storage w/Common 1/0 Pins Octal Serial/Parallel w/Sign Extend Universal Octal Shift/Storage w/Synch. Reset Serial-In, Serial/Parallel-Out (Common 1/0 Pin) Serial-In, Serial/Parallel-Out Serial/Parallel-In, Serial-Out
Device
54F/74F164A 54F/74F194 54F/74F299 54F/74F322 54F/74F323 54F/74F673A 54F/74F675A 54F/74F676
No.of Bits
8 4 8 8 8 16 16 16
Serial Inputs
2 2 2 2 2 1 1 1
Parallel Inputs
Yes Yes Yes Yes
Yes
TRI-STATE Outputs
Yes Yes Yes Yes
Leads
14 16 20 20 20 24 24 24
Buffers/Line Drivers
Function
Quad Buffer (TRI-STATE) Octal Buffer/Line Driver (TRI-STATE) Octal Buffer/Line Driver (TRI-STATE) Octal Buffer/Line Driver (TRI-STATE) Hex Buffer/Driver (TRI-STATE) Hex Inverter/Buffer (TRI-STATE) Hex Inverter/Buffer (TRI-STATE) Octal Buffer/Line Driver (TRI-STATE) Octal Buffer/Line Driver (TRI-STATE) 10-Bit Buffer/Line Driver 10-Bit Buffer/Line Driver Octal Buffer/Line Driver with 25!1 Resistor in the Output Pull-Down Octal Buffer/Line Driver with 25!1 Resistor in the Output Pull-Down
Device
54F/74F125 54F/74F240 54F/74F241 54F/74F244 54F/74F365 54F/74F366 54F/74F368 54F/74F540 54F/74F541 54F/74F827 54F/74F828 54F/74F2241
54F/74F2244
No. of Bits
4 8 8 8 6 6 6 8 8 10 10 8
8
Inverting
Yes
Yes Yes Yes
Yes
Noninverting Yes Yes Yes Yes
Yes Yes Yes Yes
Broadside Pinout
Yes Yes Yes Yes
Leads
14 20 20 20 16 16 16 20 20 24 24 20
20
xiii
G> "C
~ Tr~nsceivers/Registered Transceivers
c
; 0
Function
CJ
-aG;>
(/) CJ
Quad Bus Transceiver Octal Bidirectional Transceiver Octal Registered Transceiver
:::J Octal Registered Transceiver
"0.C..
Octal Bidirectional Transceiver
c. Octal Registered Transceiver
ti Octal Registered Transceiver
<uC..
Octal Registered Transceiver Octal Bidirectional Transceiver
Octal Bus Transceiver
Octal Bus Transceiver
Octal Bus Transceiver
Device
54F/74F243 54F/74F245 54F/74F543 54F/74F544 54F/74F545 54F/74F550 54F/74F551 54F/74F552 54F/74F588 54F/74F620 54F/74F623 54F/74F640
Registered
Yes Yes Yes Yes Yes
Octal Bus Transceiver
54F/74F643
Octal Bus Transceiver
54F/74F645
Octal Bus Transceiver
54F/74F646
Yes
Octal Bus Transceiver
54F/74F648
Yes
Octal Bus Transceiver
54F/74F651
Yes
Octal Bus Transceiver
54F/74F652
Yes
Octal Bidirectional Transceiver 54F/74F657
9-Bit Registered Transceiver
54F/74F899
Yes
Quad Bus Transceiver
54F /7 4F2243
Quad Bus Transceiver
54F /7 4F2620
Quad Bus Transceiver
54F / 7 4F2623
Quad Bus Transceiver
54F / 7 4F2640
Quad Bus Transceiver
54F /7 4F2643
Quad Bus Transceiver
54F /7 4F2645
Octal Registered Transceiver
29F52
Yes
Octal Registered Transceiver
29F53
Yes
Enable Inputs 1(L) & 1(H)
1 (L) 6(L) 6(L) 1(L) 4(L) 4(L) 2(L) 1 (L) 2(H) 2(H) 1(L)
1(L)
1(L)
1(L) & 1(H) 1(L) & 1(H) 1(L) & 1(H) 1(L) & 1(H) 1(L) & 1(H)
2(L) 1(L) & 1(H)
1(L) & 1(H)
1(L) & 1(H)
1 (L)
1(L)
1(L)
4(L) 4(L)
Features
TRI-STATE Inputs
Inverting in Both Directions TRI-STATE Inputs Status Flags Status Flags, Inverting Parity & Flag GPIB Compatible Inverting
25!1 Resistor in Output Pull-Down, Inverting 25!1 Resistor in Output Pull-Down, lnvert/Noninvert 25!1 Resistor in Output Pull-Down
Inverting Inverting Noninverting 8-Bit Parity Gen./Checker Parity Generate/Check 25!1 Resistor in Output Pull-Down 25!1 Resistor in Output Pull-Down, Inverting 25!1 Resistor in Output Pull-Down 25!1 Resistor in Output Pull-Down, Inverting 25!1 Resistor in Output Pull-Down, lnvert/Noninvert 25!1 Resistor in Output Pull-Down
Inverting
Leads
14 20 24 24 20 28 28 28 20 20 20 20
20
20
24 24 24 24 24 28 20
20
20
20
20
20
24 24
xiv
Multiplexers
Function
8-lnput Dual 4-lnput Quad 2-lnput Quad 2-lnput (Inverting) 8-lnput (TRI-STATE) Dual 4-lnput (TRI-STATE) Quad 2-lnput (TRI-STATE) Quad 2-lnput (TRI-STATE, Inverting) 4-lnput w/Shift (TRI-STATE) Dual 4-lnput Dual 4-lnput (TRI-STATE) Quad 2-Port Register Quad 2-Port Register
Device
54F/74F151A 54F/74F153 54F/74F157A 54F/74F158A 54F/74F251A 54F/74F253 54F/74F257A 54F/74F258A 54F/74F350 54F/74F352 54F/74F353 54F/74F398 54F/74F399
Enable Inputs
1(L) 2(L) 1(L) 1(L) 1(L) 2(L) 1(L) 1(L) 1(L) 2(L) 2(L)
True Output
Yes Yes Yes
Yes Yes Yes
Yes
Yes Yes
Complement Output Yes
Yes Yes
Yes
Yes Yes Yes
'Tl
Leads
16 16
.e.)-.,>n.t,
-c0nc .
16
16
16
16
16
16
16
16
16
20
16
Decoders/Demultiplexers
Function
1-of-8 Decoder/Demultiplexer Dual 1-of-4 Decoder/Demultiplexer 1-of-10 Decoder (TRI-STATE) 1-of-8 Decoder (TRI-STATE) Dual 1-of-4 Decoder (TRI-STATE) Octal Decoder/Demultiplexer w/Latches Octal Decoder/Demultiplexer w/Acknowledge
Device
54F/74F138 54F/74F139 54F/74F537 54F/74F538 54F/74539 54F/74F547 54F/74F548
Address Inputs
3 2&2
4 3 2&2 3 3
Enable
2(L) & 1(H) 1(L) & 1 (L) 1(L)& 1(H) 2(L) &2(H) 1(L)& 1(L) 1(L) &2(H) 2(L) & 2(H)
Output Enable
1(L) 2(L) 1(L) & 1(L)
Outputs
8(L) 4(L) & 4(L)
10(H) 8(H) 4(H) &4(H) 8(L) 8(L)
Leads
16 16 20 20 20 20 20
Adders/Subtracters
Function
Binary Full Adder w/Fast Carry Quad Serial Adder/Subtracter 4-Bit BCD Adder
Device
54F/74F283 54F/74F385 54F/74F583
Master Reset
Yes
Carry Lookahead
Yes
Yes
Leads
16 20 16
Multipliers
Function 8-Bit Serial/Parallel Multiplier 8-Bit Serial/Parallel Multiplier
Device
54F/74F384 54F/74F784
Expandable
Yes Yes
Adder/Subtracter Yes
Leads
16 20
xv
CD
�"sC Comparators
CJ
c
Function
0
:;:::;
(,)
8-Bit Identity Comparator
Device 54F/74F521
-aC;D
en
(,)
8-Bit Comparator Register /Counter /Comparator
54F/74F524 54F/74F701
::l
"C
0....
Divider
0..
1cn-
<(
Function
I
16-Stage Programmable Counter/Divider
I
u.
Device 54F/74F525
ALUs
Features Expandable Expandable, Registered Expandable
Features Crystal Oscillator
Leads
20 20 24
1 Leads
1
28
Function Arithmetic Logic Unit
Arithmetic Logic Unit
Arithmetic Logic Unit BCD Adder/Subtracter
Device 54F/74F181
54F/74F381
54F/74F382 54F/74F582
No.of Bits 4
4
4 4
Arithmetic Functions
16
3
3 2
Logic Functions
16
3
3
Features
Carry Generate/ Propagate Outputs
Carry Generate/ Propagate Outputs
Ripple Carry Expansion Lookahead & Ripple
Carry Expansion
Leads 24
20
20 24
ALU Support
Function Carry Lookahead Generator
4-Bit Shifter (Specialized Multiplexer) ALU/Function Generator
Device 54F/74F182
54F/74F350 54F/74F881
No.of Bits 4
4 4&4
Features
Carry Lookahead Generator for4 ALUs
Expandable Shifter
Leads 16
16 24
FIFOs
Function
16 x 4 FIFO Buffer Memory FIFO RAM Controller 64 x 4 FIFO Buffer Memory 64 x 4 FIFO Buffer Memory
Device
54F/7 4F403A 54F/74F411 54F/74F413 54F/74F433
Input Serial/Parallel
Parallel Serial/Parallel
Output Serial/ Parallel
Serial/Parallel Serial/Parallel
Leads
24 20 16 24
Memories
Function
16 x4 RAM 16x4 RAM 16 x 4 FIFO Buffer Memory 64 x 4 FIFO Buffer Memory 64 x 4 FIFO Buffer Memory
Device
54F/74F189 54F/74F219 54F/74F403 54F/74F413 54F/74F433
TRI-STATE Outputs Yes Yes Yes
Yes
Leads
16 16 24 16 24
xvi
Memory Support
Function
Data Access Register Register Stack-16 x 4 RAM FIFO RAM Controller Parallel Check Bit/Syndrome Bit Generator 32-Bit Error Detection & Correction 1 Megabit Dynamic RAM Controller Dynamic RAM Controller
Device
54F/74F407 54F/74F410 54F/74F411 54F/74F420 54F/74F632 54F/74F968 29F68
Cyclic Redundancy Checker-Generator
Function
Cyclic Redundancy Check Generator/Checker Serial Data Polynomial Generator/Checker
Device
54F/74F401 54F/74F402
Features TRI-STATE Outputs TRI-STATE Output Register
TRI-STATE Outputs Latched, TRI-STATE Outputs TRI-STATE Outputs TRI-STATE Outputs
Polynomial Length
16 64
Expandable Yes
"T1
e)>n
-f
Leads
"..t.J.
24 18 40
-0c.
c:
(")
en
48 52 52
-nCDr
(")
c;�
48
::::J
acG::>
CD
Leads
14 16
Parity Generator/Checker
Function
Parity Generator/Checker Parallel Check Bit/Syndrome Bit Generator Octal Bidirectional Transceiver 9-Bit Registered Transceiver
Device
54F/74F280 54F/74F420 54/74F657 54/74F899
Features Odd/Even Outputs, 9-Bits In
Parity Generate/Check Parity Generate/Check
Leads
14 48 24 28
Error Detection and Correction
Function 32-Bit Error Detection and Correction
Device 54F/74F632
Leads 52
Microprocessor Support
Function 8-Line to 3-Line Priority Encoder
Device 54F/74F148
TTL to ECL Translators
Function
Device
Complementary
Hex TTL-ECL Translator
F100124
Yes
Hex ECL-TIL Translator
F100125
Yes
Octal ECL-TIL Transceiver
F100128
For further information on TIL to EGL translators, refer to the F1 OOK databook.
Latched Yes
Leads 16
Features Enable Input
Common Mode Rejection = + 1V
ECL Output Cut-Off State
xvii
Section 1 Circuit Characteristics
a
Section 1 Contents
FAST Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FAST Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TRI-STATE Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FAST ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Switching Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Symbols & Terminology........................................................
1-3 1-4 1-6 1-8 1-9 1-9 1-14 1-14 1-15
1-2
0::;�
D~NaStemiicoonnduactlor
(')
c:
;:::+
.:0Q:,:)r
Circuit Characteristics
Q) (')
-.,(1)
u;�
-c:;�
en
FAST� Technology
FAST (Fairchild Advanced Schottky TTL) circuits are made with the advanced lsoplanar II process, which produces transistors with very high, well-controlled switching speeds, extremely small parasitic capacitances and fr in excess of 5 GHz. lsoplanar is an established National process, used for years in the manufacture of bipolar memories, CMOS, subnanosecond ECL and 13LTM (lsoplanar Integrated Injection Logic) LSI devices.
In the isoplanar process, components are isolated by a selectively grown thick oxide rather than the p + isolation region used in the planar process. Since this oxide needs no separation from the base-collector regions, component and chip sizes are substantially reduced. The base and emitter ends terminate in the oxide wall; masks can thus overlap the device area into the isolation oxide. This overlap feature eliminates the extremely close tolerances normally required for base and emitter masking, and the standard photolithograhic processes can be used.
Figure 1-1 shows the relative size of phase splitter transistors (02 in Figure 1-3) used in Schottky, Low Power Schottky and FAST circuits. The LS-TTL transistor is smaller than that of S-TTL because of process refinements, shal-
lower diffusions and smaller operating currents. The relative size of the FAST and FAST LSI transistors illustrate the reduction afforded by the lsoplanar process. This in turn reduces junction capacitances, while the use of oxide isolation reduces sidewall capacitance. The end result of these reductions is an increase in frequency response by a factor of three or more. Figure 1-2 shows the frequency response of two sizes of transistors made with the lsoplanar II process. Because they have modest, well-defined loads and thus can use smaller, faster transistors, internal gates of MSI devices are faster than SSI gates such as the 'FOO or 'F02. SSI gates, on the other hand, are designed to have high output drive capability and thus use larger transistors.
As is the case with other modern LSI processes, the shallower diffusions and thinner oxides make FAST devices more susceptible to damage from electrostatic discharge than are devices of earlier TTL families. Users should take the usual precautions when handling FAST devices: avoid placing them on non-conductive plastic surfaces or in plastic bags, make sure test equipment and jigs are grounded, individuals should be grounded before handling the devices, etc.
- t - - t - - Collector
c
Schottky Diode
SD
Silicon moxidee
II
Planar
Schottky
Washed Emitter
LS
lsoplanar
LSI
FIGURE 1�1. Relative Transistor Sizes in Various TTL Families
1-3
lsoplanar II
FAST
TL/F/9592-1
FAST Technology (Continued)
:cN:
-�.(s...)
...,<.:> 5.0
I
.g!5,. 4.0
et::
0
~ 3.0
::J
O"
..~....
I
2.0
~
1.0 .____.._ _.1..---1._...J...._--1._...J
1.0 2.0 5.0 10 20 50 100
le - Collector Current - mA
TL/F/9592-2
FIGURE 1-2. lsoplanar Transistor Frequency Response
FAST Circuitry
The 2-input NANO gate, shown in Figure 1-3, has three stages of gain (01, 02, 03) instead of two stages as in other TTL families. This raises the input threshold voltage and increases the output drive. The higher threshold makes it possible to use pn diodes for the input AND function (01 and 02) and still achieve an input threshold of 1.5V.
The capacitance of these diodes is comparatively low, which results in improved AC noise immunity. The effect of the threshold adjustment can be seen in the voltage transfer characteristics of Figures 1-4, 1-5 and 1-6. At 25�C (Figure 1-5) the FAST circuit threshold is nearly centered between the 0.8V and 2.0V limits specified for TTL circuits. This gives a better balance between the HIGH- and LOW-state noise
margins The + 125�C characteristics (Figure 1-6) show that
the FAST circuits threshold is comfortably above the 0.8V specification, more so than in S-TIL or LS-TIL circuits. At -55�C, the FAST circuit threshold is still well below the 2.0V specification, as shown in Figure 1-4.
FAST circuits contain several speed-up diodes to help discharge internal capacitances. Referring again to Figure 1-3, when a HIGH-to-LOW transition occurs at the 01 input, for example, Schottky diode 03 acts as a low-resistance path to discharge the several parasitic capacitances connected to the base of 02. This effect only comes into play, however, as the input signal falls below about 1.2V; 03 does not act as an entry path for negative spikes superimposed on a HIGH input level. When 02 turns ON and its collector voltage falls, 07 provides a discharge path for capacitance at the base of 06. Whereas 03, 04 and 07 enhance switching speed by helping to discharge internal nodes, 08 contributes to the ability of a FAST circuit to rapidly discharge load capacitance. Part of the charge stored in load capacitance passes through 08 and 02 to increase the base current of 03 and increase 03's current sinking capability during the HIGH-to-LOW output voltage transition .
....--------------------_.~Yee
4.1k
45.ll
07
02
DB
012
FIGURE 1�3. Basic FAST Gate Schematic
TL/F/9592-3
1-4
FAST Circuitry (Continued)
In addition to the 2K-04-3K squaring network, which is standard for Schottky-clamped TTL circuits, FAST circuits contain a network D9-D10-D11-07 whose purpose is to provide a momentary low impedance at the base of 03 during an output LOW-to-HIGH transition. The rising voltage at the emitter of 05 causes displacement current to flow through varactor diode D9 and momentarily turn ON 07, which in turn pulls down the base of 03 and absorbs the displacement current that flows through the collector-base capacitance (not shown) of 03 when the output voltage rises. Without the D9-07 network, the displacement current through the collector-base capacitance acts as base current, tending to prolong the turn-off of 03 and allow current to flow from 06 to ground through 03.
5.0
>
I
4.0
eCDn
~
0> 3.0
::ll
c.
::ll
2.0
0
I
1-::::>
>0 1.0
Yee= 5.ov TA =-55�c loH Applied
' 'R~ LS-TTL S-TTL FAST
0 0 0.5 1.0 1.5 2.0 2.5
V1N- Input Voltage - V
TL/F /9592-4
FIGURE 1-4. Transfer Functions at Low Temperature
The collector-base capacitance of 03, although small, is effectively multiplied by the voltage gain of 03. This phenomenon, first identified many years ago with vacuum tube triodes, is called the Miller effect. Thus the D9-07 network is familiarly called the 'Miller Killer' circuit and its use improves the output rise time and minimizes power consumption during repetitive switching at high frequencies. Diode 010 completes the discharge path for 09 through D7 when 02 turns on. D11 limits how tow 07 pulls down the base of 03 to a level adequate for the intended purpose, without sacrificing turn'.on speed when a circuit is cycled rapidly.
Also shown in Figure 1-3 is a clamp diode, D12, at the output. This diode limits negative voltage excursions due to parasitic coupling in signal lines or transmission tine effects.
The Schottky clamping diodes built into the transistors prevent saturation, thereby eliminating storage time as a factor in switching speed. Similarly, the speed-up diodes tend to minimize the impact of other variables on switching speed. The overall effect is to minimize variation in switching speed of FAST circuits with variations in supply voltage and ambient temperature (Figures 1-7 and 1-8). Propagation delay is specified not only under nominal supply voltage and temperature conditions, but also over the recommended operating range of Vee and TA for both military and commercial grade devices.
5.0
>
I
4.0
eCDn
~
0> 3.0
::ll
-5 2.0
0
I 1-::::>
>0 1.0
0 0
Yee= 5.ov TA=+25�c loH Applied
1 f
s-Ji' LS-TTL
FAST
1
\ Il
0.5 1.0 1.5 2.0 2.5
Y1N - Input Voltage - V
TL/F/9592-5
FIGURE 1-5. Transfer Functions at Room Temperature
The internal switching speed of a logic circuit is only one aspect of the circuit's suitability for high-speed operations at the system or subsystem level; the other aspect is the ability of the circuit to drive toad capacitance. FAST circuit outputs are structured to sink at least 20 mA in the LOW state, the same as S-TTL. This capability plus the effect of the aforementioned feedback through 08 assures that the circuit can rapidly discharge capacitance. During a LOW-to-HIGH transition, the pull-up current is limited by the 45!1 resistor, versus 55!1 for S-TTL. Therefore, FAST circuits are inherently more capable than S-TTL of charging load capacitance.
Figure 1-9 shows the effects of load capacitance on propagation delays of FAST, S-TTL and LS-TTL NANO gates. The curves show that FAST gates are not only faster than those of earlier families, but also are less affected by capacitance and exhibit less skew between the LOW-to-HIGH and HIGH-to-LOW delays. These improved characteristics offered by FAST circuits make it easier to predict system performance early in the design phase, before loading details are precisely known. The curves show that the skew between HIGH-to-LOW and LOW-to-HIGH delays for the FAST gate is only about 0.5 ns over a broad range of load capacitance, whereas the skew for the S-TIL gate is 1 ns or greater, depending on loading.
5.0 Yee= 5.ov
TA=+125�c
>
I
4.0 S-TTL
loH Applied
eCDn
al
~ >
3.0
Th
LS-TT~\ FAST
::ll
c.
::ll
20
0
I
1-::::>
>0 1.0
'
l.l.
0
0 0.5 1.0 1.5 2.0 2.5
V1N- Input Voltage - V
TL/F/9592-6
FIGURE 1-6. Transfer Functions at High Temperature
0:;� c;n::::;:
II
1-5
tn
(.)
~
tn
FAST Circuitry (Continued)
-"ii::
Q)
(.)
ca.t.l
-.cctl
0
�5
(.)
a..
.,
c I
l CL =50pF
o =+ 1 TA z5oc __,_,>--+--+---+---+--<
~
tPLH � - - � ~'-1--+--1---1---1--l
Cl
tPHL--
z
g 0
0
a0a::.:
I -' :aI.:
_
SCHOTIKY-+-
-----� -� -� -� 41--+--+----+---+--+~-+--+--+--l
---. - - - - ~rAsr
~ ---i-.
-~
21--+--+----+---+--+~-+--+--+--l
o.__...__..__.__.___..__.~..__...__.._~
4.5
5.0
5.5
Vee-SUPPLY VOLTAGE-V
TL/F/9592-7
FIGURE 1-7. Propagation Delay versus Vee
.,
c I
12...--...--.--.--.---.---.~...-~~~
~~;~~�~: 1---+---+----+---+--+--l-1
j
10 l---+---+----+---+--+--'-1 tPLH � - - �
w
Cl
z
0 i=
~
~ 1---+---+----+---+--+--l-1tPHL--
81-~:~---P'.=-S-'C-H-O:-T,IK.Y,.r:~ :::~j -i.~-, +--+' --+-~
.... __ ~
~-+-r--i-
0g:
6
~ SCHOTIKY --+-+-..11!-<~-,-..1
I -'
- -r--J--r
.J _3,,_
4 - -~-
-~F-A_ST�-~-I:..J.i..."-'
2,__..__.._..._..._._J....__..__.__..__.__.
-55
+25 +70
+125
TA-AMBIENT TEMPERATURE- 0c
TL/F/9592'-8
FIGURE 1-8. Propagation Delay versus Temperature
., 20
c
I
18
>-
ci 16
Cl
z
14
0 i=
12
<C(
<.:> a<C.(
10
~
8
a.
I
6
-'
.J 4
j 2
100
200
CL - LOAD CAPACITANCE- pf
FIGURE 1-9. Propagation Delay versus Load Capacitance
TL/F/9592-9
Output Characteristics
Figure 1-10 shows the current-voltage characteristics of a FAST gate with the pull-down transistor 03 turned� ON. These cuNes illustrate instantaneous conditions in discharging load capacitance during an output HIGH-to-LOW transmission. When the output voltage is at about 3.5V, for example, the circuit can absorb charge from the load capac-
itance at a 500 mA rate at + 25�C. From this level the rate
decreases steadily down to about 100 mA at 1.5V. In this region from 3.5V to 1.5V, part of the charge from the load capacitance is fed back through 08 (Figure 1-3) and 02 to provide extra base current for 03, boosting its current sinking capability and thus reducing the fall time. Below the 1.5V level, 03 continues to discharge the load capacitance, but without extra base current from 08. At about 0.5V, the integral Schottky clamp diode from base to collector of 03 starts conducting and prevents 03 from going into deep saturation.
4 l---+--f---r5-5--�.c-]1r/T-/#_-+J~1-2.5-�-c+---+---l
IA/
Yee= 5.ov
l
1
17
0'---'---1---'-.....J...---L..--1~'----'---1--~
0 200 400 600 800 1000 loL - OUTPUT LOW CURRENT- mA
TL/F/9592-10
FIGURE 1-10. Output LOW Characteristics- 'FOO
1.o .--.,..._-5.,..5-c-r--n--""T"+_2..,.5-oe-.--U"""J......---.
>
I
0
w <.:>
o~1--+-~+--lf+-+--r--ll-~vr-+--
~
> 0
0.6 J l--+--.__.,-H-+-+!Jt_-_-j1_-++1.2y5~�~c~
g3::
.....
:::>
_JL__ Yee= 5.ov
0.4 1--+--t--~-l~-+--tl"'-----+~~~_,
~
I N :::>
0
I o2
~- '
~~
o.__..._......__.__._---L..--1~'----'---1--~
0 20 40 60 80 100
loL - OUTPUT LOW CURRENT- mA
TL/F/9592-11
FIGURE 1-11. Output LOW Characteristics- 'FOO
1-6
Output Characteristics (Continued)
On a greatly expanded scale, the output LOW characteristics of a gate are shown in Figure 1-11. With no load, the output voltage is about 0.1 V, increasing with current on a slope of about 7.5!1. When the load current increases beyond the current-sinking capability of 03, the output voltage rises steeply. It can be seen that the worst-case specification of 0.5V max at 20 mA load is easily met. Similar characteristics for a buffer shown in Figure 1-12, over a broader current range. The curves are well below the output LOW voltage specification of 0.55V max at 48 mA over the military temperature range or 64 mA over the commercial temperature range.
>
I
w
(!)
~
0 >
g ~
/1)'L 0.8
-55oc
1---t-~1-1--t--t-#-l-1-t---t-+~
I o.s l---ll--+AV1_.L1_,,~'---""1"'--+--+-ve_,e_=..5...-ov-+-l
I=>~
0.412?'"
ri ::::>
0
I..... 0.2
-;;'
o.___..._....__..___.___..__.~.__..._...._~
0
100
200
300
loL - OUTPUT LOW CURRENT- mA
TL/F/9592-12
FIGURE 1-12. Output LOW Characteristics- 'F244
I
>
I
w
(!)
4
~ 100.n LOAD Vee =5.0V
~
0 >
: ~1--1+-+ 125PC
~
:I:
:c(!)
I-
:c::.:.>.
I-
::::> 0 I
:I:
> 0
11.
�~
11 ~
1~I t--55~�+C2~5oC
I
0
~
0 40 80 120 160 200
loH- OUTPUT HIGH CURRENT- mA
TL/F/9592-13
FIGURE 1-13. Output HIGH Characteristics- 'FOO
The output HIGH characteristics of a FAST gate are shown in Figure 1-13. At low values of output current the voltage is approximately 3.5V. This value is just the supply voltage minus the combined base-emitter voltages of the Darlington pull-up transistors 05 and 06 (Figure 1-3). For load currents above 16 mA or 18 mA, the voltage drop across the 45!1 Darlington collector resistor becomes appreciable and the Darlington saturates. For greater load currents the output voltage decreases with a slope of about 50!1, which is largely due to the 45!1 resistor. The value of current where a characteristic intersects the horizontal axis is the short-
:0;�
0
c:
circuit output current las. This is guaranteed to be at least
;::;:
60 mA for a FAST gate, compared to 40 mA for S-TTL. This
0
parameter is an important indicator of the ability of an output to charge load capacitance. Thus the FAST specifications insure that an output can charge load capacitance faster, or force a higher LOW-to-HIGH voltage step into the dynamic impedance of a long interconnection.
The output HIGH characteristics of a buffer are shown in Figure 1-14. These are similar in shape to Figure 1-13 but at
::::::r
.D..>..
D> 0
-.uc.t.>.;.� -c:;�
en
higher levels of current. The output HIGH voltage of a buffer
is guaranteed at two different levels of load current. With a
3 mA load, VoH is guaranteed to be at least 2.4V for both
military and commercial devices. VoH is also guaranteed to
be at least 2.0V with a 12 mA load for military or 15 mA load
for commercial devices. In addition, the short-circuit output
current of a buffer is guaranteed to be at least 100 mA.
When an output is driving a long interconnection, the initial LOW-to-HIGH transition is somewhat less than the final, quiescent HIGH level because of the loading effect of the line impedance. The full HIGH voltage level is only reached after the reflection from the far end of the line returns to the driver. The initial LOW-to-HIGH voltage step that an output can force into a line is determined by drawing a load line on the graph containing the output HIGH characteristic and noting the voltage value where the load line intersects the
characteristic. For example, if a FAST gate is driving a 1oon
line, a straight line from the lower left origin up to the point 5V, 50 mA intersects the - 55�C characteristic curve at about 2.8V. This indicates that the gate output voltage will rise to 2.8V initially, and the 2.8V signal, accompanied by 28 mA of current, will travel to the end of the line. If not terminated, the 28 mA is forced to return to the driver, whereupon it unloads the driver and the output voltage rises to the maximum value. Similarly, a 50!1 load line drawn on the buffer characteristic shows an intercept voltage of 2.5V. In both cases, the initial voltage step is great enough to pass through the switching region of any inputs that might be located near the driver end of the lline, and thus would not exhibit any exaggerated propagation delay due to the loading effect of the line impedance on the driver output. Thus the FAST output characteristics insure better system performance under adverse loading conditions.
>
I
l 1OO.n-;__,U.r-,-+---+-~;-+�~___,r--+---+----+---t
LOfD I
w
(!)
~
0 >
4 t+...1.25�C�~ /
~ /-.+- 50.n LOAD
:I: (!)
-5"~
Ve = 5.0V
:c
I-
v �~
~
: _l ~~+25�C
::::> 0
I
:I:
> 0
O.__..._....__..___.__.,__.~......._..._....__~
0
100
200
loH - OUTPUT HIGH CURRENT- mA
TL/F /9592-14
FIGURE 1-14. Output HIGH Characteristics- 'F244
II
1-7
rn
(J
:;::; rn
Input Characteristics
-"i::
C1' (J
The input of a FAST circuit represents a small capacitance, typically 4 pF to 5 pF, in parallel with an 1-V characteristic
....ta that exhibits different slopes over different ranges of input
-.tca
0
�s .(.J..
0
voltage. Figure 1-15 shows the input characteristic of a FAST gate at three temperatures. In the upper right, the flat horizontal portion is the V1H-l1H characteristic. In this region, all of the current from the 10 kn input resistor (Figure 1-3) is flowing into the base of 01 and the only current flowing in the iriput diode. is the leakage current l1H� When the input
voltage decreases to about 1.7V ( + 25�C), current starts to
flow out of the input diode and the curve shows a knee. At
this point some of the current from the 10 kn resistor is
diverted from the base of 01. When the input voltage de-
clines to about 1.4V the curve shows another knee; at this
point, substantially all of the current from the 1o kn resistor
flows out. of the input diode. The portion of the curve be-
tween 1.4V and 1.7V input voltage is the active region, es-
sentially corresponding to the FAST transfer function in Fig-
ure 1-5.
<
Or~-r-r-j~[-Ji--+---t-~-+-t
~::i. -200 t--++-1-+2-..5--�i-c1~-,_H.,J._~,_/,~#j-+-1'+--2--5--�.-c-5-5.--oc--+--+-1
~ -400 f"6'~F--+-P"-+--+--+--+----'-----'----1--l
(.)
Vee=S.OV
1::>-
-600 ~
H+-+--+--+---+--+---+-t--+--+--<
I
-800 H+-+--+--+---+--+---+-t--+---+--<
0
2
3
4
V1 - INPUT VOLTAGE - V
TL/F/9592-15
FIGURE 1-15. Input Characteristics- 'FOO
Below 1.4V input, the characteristic has the slope of the 1O kn input resistor. When the input voltage declines to about -0.3V, the Schottky clamping diode starts conducting and the current increases rapidly as the input voltage decreases further.
The input characteristics of a buffer, shown in Figure 1-16, differ from those of a gate in two respects. One is the location of the transition region along the horizontal axis. A buffer input has a hysteresis characteristic about 400 rnV wide, such that the transition region shifts left or right accordingly as the input voltage transition is HIGH-to-LOW or LOW-toHIGH, respectively. The curves in Figure 1-16 apply to the HIGH-to-LOW input voltage transition. The other difference between buffer and gate characteristics is the slope of the characteristic follows this value, rather than the 1O kn slope of a gate input.
0
r[J
< :I.
+
1 I
1
�I c
k
~~
Yee= 5.ov
I I-
~ aa:::: ::>
(.)
I-
p -400 +moq""'i
-800
~ T b..--55�C ~
::>
a..
~
-1200
~
I
-1600
0 1.0 2.0 3.0 4.0
Vi- INPUT VOLTAGE-V
TL/F/9592-16
FIGURE 1-16. Input Characteristics- 'F244
The characteristics of an input Schottky clamp diode are shown in Figure 1-17, for much larger values of current than those of Figures 1-15 and 1-16. The purpose of the clamp diode is to limit undershoot at the end of a line following a HIGH-to-LOW signal transition. For example, an output sig-
nal change from + 3.5V to + 0.5V into a 1oon line propa-
gates to the end of the line, accompanied by a 30 rnA current change. If the line is terminated in a high impedance the 3V signal change doubles, driving the terminal voltage down to - 2.5V. With the clamp diode, however, the negative excursion would be limited to about -0.7V. The same HIGH-to-LOW signal change on a 50n line would be clamped at about -1.0V. Figure 1-18 shows the typical breakdown characteristics for a FAST input.
< 10t--+--+--1-f1,1---1---rVc~c~=~s-.ov-ir~
E
,_I
i
,u _
~
~
I
40 l---t--t--!Hf-1---1---~-l-l--I
50 '--'--'--U'-'--L...-L......J--'--'---' -1.5-1.0-0.5 0 0.5 1.0 1.5
V1 - INPUT VOLTAGE- V TL/F/9592-17
FIGURE 1-17. Input Characteristics- 'FOO or 'F244
50
<( ~
40
,_I
~ 30
,u=_>
20
~
~
I
10
- s s0 e!___
!"" +25�C...::::j
fi
+125�C--i
Vcc=S.OV
0
0
10 15 20 25
V1- INPUT VOLTAGE-V TL/F/9592-18
FIGURE 1-18. Input Characteristics- 'FOO or 'F244
1-8
TRI-STATE� Outputs
A partial schematic of a circuit having a TRI-STATE output is shown in Figure 1-19. When the internal Output Enable (OE) signal is HIGH, the circuit operates in the normal fashion to provide HIGH or LOW output drive characteristics. When OE is LOW, however, the bases of 01, 02 and 05 are pulled down. In this condition the output is a high imped-
(')
:::;�
(")
c: ance. In this High Z condition, the output leakage is guaran- :;::;:
teed not to exceed 50 �A. In the case of a transceiver, each data pin is an input as well as an output and the leakage specification is increased to 70 �A. In the High Z state, output capacitance averages about 5 pF for a 20 mA output and about 12 pF for a 64 mA output.
FIGURE 1-19. Typical TRI-STATE Input Control
TL/F/9592-19
FAST ESD Protection
INTRODUCTION
The study of ESD failures began in earnest back when system designers, faced with very expensive assembly and post-assembly rework, began investigating system failures in great detail. In the course of their study, they checked all the records to determine which devices has passed earlier testing, but had failed once in the system. The data clearly indicated that something in the handling process resulted in higher attrition rates among the devices. Reliability physicists examined the failed devices in minute detail, in some cases subjecting them to examination under high powered scanning electron microscopes.
The problem was found to be one of electrical overstress, and further investigation determined that the cause of the overstress was a phenomenon called electrostatic discharge (or ESD).
EXPLANATION OF HOW ESD OCCURS
The concept of electrostatic discharge is easily understood. Electrostatic energy is static electricity, a stationary charge which can build up in either a nonconductive material or in an ungrounded conductive material. This charge can occur
in one of two ways, either through polarization, which occurs when a conductive material is exposed to a magnetic field, or triboelectric effects, which occur when two surfaces contact and then separate, leaving one positively charged and one negatively charged. Friction between two materials increases triboelectric charge by increasing the surface area that comes in contact. A good example of this phenomenon would be the charge one accumulates walking across a nylon carpet. The discharge occurs when one reaches for a doorknob or other conductive surface. The types of ESD with which we will be concerned fall into the category of triboelectric effects. Within this category, various materials have differing potentials for charge. Asbestos, nylon, human and animal hair and wool have a high positive triboelectric potential. Silicon has one of the highest negative triboelectric potentials, followed by such materials as polyurethane, polyester and rayon. Cotton, wood, steel and paper all tend � to be relatively neutral, which makes cotton clothing and steel table tops excellent ESD protective materials in environments where ESD problems can be anticipated.
II
1-9
ti)
(.)
:.;::
-�.t::i:):
Q)
(.)
-..cc.c.aa..
0
�:;
FAST ESD Protection (Continued)
The intensity of the charge is inversely proportional to the relative humidity. As humidity decreases, ESD problems increase. For example, walking across a carpet will generate a 1.5 kV charge at 90%RH, but will generate 35 kV at 10%RH. When an object storing a static charge comes in contact with another object, the charge will attempt to find a
(.....).
0
path to ground, discharging into the contacted object. Although the current level is extremely low (typically less than 0.1 nanoamp), the voltage can be as high as 35-50 kV.
The degree of damage caused by electrostatic discharge is a function of the size of the charge (which is determined by the capacitance of the charged object) and the rate at which it is discharged (determined by the resistance into which it is discharged). This relationship can be shown with a waveform (Figure 1-20) that utilizes what is termed a double exponential decay pulse. With such a pulse, 99% of the energy will be dissipated in five time constants, with each time constant established by the resistance and capacitance mentioned above. Where both are low, the discharge rate will be rapid enough to cause damage if the object into which discharge occurs is a semiconductor. As resistance and capacitance increase, both the discharge rate and the risk of damage decrease.
OR
v
t-
TL/F/9592-31
FIGURE 1-20. Ideal RC Waveform It is estimated that the value of devices lost to ESD could run as high as $1 billion per year. Most electrostatic damage is caused by the handling of devices by personnel who have not taken adequate precautions. One would expect this in light of the fact that the capacitance of the human body ranges from 50 to 200 pF. The ESD characteristics of work surfaces and of materials passing through the area should not be ignored, however, in an attempt to concentrate on the human effect. TYPES OF ESD DAMAGE The damage caused by ESD results from the charge's tendency to seek the shortest path to ground, overstressing any electrical interfaces in that path. There are several different types of damage that result, and each of these tends to be typical of specific component technologies and. elements.
Dielectric Breakdown
Dielectric breakdown occurs when the voltage across an oxide exceeds its dielectric breakdown strength. The single most important factor in this breakdown is the oxide thickness (Figure 1-21). Thinner oxide is more susceptible to electrostatic punch-through, which leaves a permanent lowresistance short through the oxide. Where there are pin holes or other weaknesses in the oxide, damage will be possible at lower charge levels. It should be noted that semiconductor manufacturers have reduced oxide thicknesses as they have reduced the overall size of the devices. ESD sensitivity has therefore increased dramatically.
OXIDE
/ /- METIA-L~.:;:-..._ OXIDE
l~�.: 1 \~,,7 ~I
TL/F/9592-32
FIGURE 1-21. Bipolar Transistor
Electrostatic charge which does not actually result in a breakdown can cause lattice damage in the oxide, lowering its ability to withstand subsequent ESD exposure. A weakened lattice will also have a lower breakdown threshold voltage, and this mechanism is voltage dependent.
Thermal Secondary Breakdown or Junction Burnout
Junction burnout is a significant failure mechanism for bipolar devices, and tends to be power dependent rather than voltage dependent. The interface (or junction) between a P-type diffusion and an N-type diffusion normally has a positive temperature coefficient at low temperatures (that is, increased temperature will result in increased resistance). When a reverse-biased pulse is applied, the junction dissipates heat in its very narrow depletion region, and the temperature increases rapidly. If enough energy is applied, the temperature of the junction will reach a point at which the temperature coefficient of the silicon will turn negative (that is, at which increased temperature will result in decreased resistance). Since the area of the junction is not uniform, hot spots occur. When the melting temperature of silicon (1415�C) is reached as a result of the ensuing thermal runaway condition, junction melting occurs in the localized area. If there is an additional energy available after the initiation of melt, the hot spot can grow into a filament short. The longer the pulse, the wider the resultant filament short.
After the occurrence of the transient, the silicon will resolidify. In a relatively short pulse, a hot spot may form, but not grow completely across the junction. As a result, the damage may not manifest itself immediately as a junction short but will appear at a later time as a result of electromigration. Shrinking geometries will decrease junction areas, and this should increase the susceptibility of these devices to ESD related junction problems.
1-10
FAST ESD Protection (Continued)
Metallization Melt
Semiconductor interconnect metallization typically has a small cross-sectional area and limited current carrying capability. As feature sizes continue to be reduced, metallization cross-section will be reduced as well. Reducing metallization line width by half and metallization thickness by half reduces the current carrying capability of that metallization stripe by 75%. Metallization melt, which is a power-dependent failure mechanism, is more likely to occur during short duration, high current pulses, since the only available heat sink (the bonding pad) is nearby and the heat dissipated in the metallization does not have time to flow into the surrounding areas. It can also occur as a side effect during junction melt.
Latent Failures
Immediate failure resulting from ESD exposure is easily determined: the device no longer works. A failed device may be removed from the lot or from the subassembly in which it is installed, and it represents no further reliability risk to the system. There are, however, devices which have been exposed to ESD but which have not immediately failed. Unfortunately, there has never been sufficient data dealing with the long-term reliability of devices which have survived ESD exposure, although some experts feel that two to five devices are degraded for every one that fails. It should be obvious from an examination of the failure mechanisms described above that there can be significant degradation without immediate failure. Damage can manifest itself in either a shortening of the device's lifetime (a possible cause for many of the infant mortality failures seen during burn-in) or in electrical performance shifts, many of which cause the device to fail electrical test limits.
ESD PROTECTIVE MEASURES
It should be obvious then that there are three principal considerations when dealing with ESD. The first is that the device should be designed in a manner that minimizes ESD sensitivity and incorporates some ESD protective features.
:0:;�
The second is that both manufacturers and users must un-
cn;::::;:
derstand the ESD susceptibility of the devices with which
:0:::r
they are dealing. Thirdly, both user and manufacturer must D>
understand the generation of and sources of ESD charges well enough to establish proper precautions throughout their plants.
-"""I
Dn >
CD
"""I
�:
Fast Dual-Rail ESD Protection
c:;�
The continuing development of faster and more complex en
IC's makes it unlikely that we will see a return to thicker
oxide layers and larger junctions. Early IC's used fairly sim-
ple clamping diodes on the inputs to protect them against
voltage transients in the system. Similar, but more compre-
hensive protective networks can be employed to provide
ESD protection. Figure 1-22 shows National's FAST propri-
etary dual-rail ESD protection circuitry. These structures are
included on most of the high volume FAST products and are
now standard on all new FAST designs and redesigns. (See
individual product specifications for identification of parts
with enhanced ESD protection.) By its design, this form of
ESD control limits product vulnerability to both positive and
negative ESD/EOS voltages by protecting inputs and out-
pus to Vcc as well as ground.
Protection to ground is provided through transistor .02 on the input and diode 02 on the output. On the input, the unique design and layout of the Schottky device insures a minimum turn-on voltage as well as maximum current carrying capability. For the output the standard Schottky clamp diode provides the protection. 01 and 03, through use of a BVCEO breakdown mechanism, protects the path to Vee. Diode D1 and D3 insure isolation of the input or output from Vee leakages. Again, these devices have been designed and laid-out to insure dependable turn-on characteristics as well as robustness.
Dual-rail ESD protection has provided FAST parts with protection levels exceeding 4000V. In fact, as measured through use of the MIL-STD-883 techniques described below, FAST ESD protection has averaged in excess of 8000V. Best of all, this protection has been achieved with no appreciable effect on speed or significant increase in input capacitance.
II
FIGURE 1-22. FAST ESD Circuitry 1-11
TL/F/9592-33
tn
;:C:J: tn
FAST ESD Protection (Continued)
-'ii:
Q)
CJ
E
Assessing ESD Tolerance Levels
As awareness of the importance� of addressing ESD concerns spread, many experts felt that ESD testing had to be
.Cc'CI 0
-�s
...CJ
uniform if results were to be shared. Method 3015 of MILSTD-883 was created for the purpose of allowing manufacturers to assess the ESD tolerance levels of the devices they offered and to allow users to determine the ESD sensi-
0
tivity of the parts with which they were assembling systems.
Method 3015 has established a test circuit (see
Figure 1-23) which approximates the resistance and capac-
itance found in the human body (which continues to provide
the major source of destructive ESD). The testing is per-
formed by charging the capacitor in the test circuit and then
discharging that capacitor into the unit under test. After test-
ing, a device will be classified as either Class 1, those devic-
es which exhibit ESD-induced failure or degradation at lev-
els between zero volts and 1,999V; or Class 2, those which
may exhibit ESD sensitivity at levels between 2,000V and
3,999V; or Class 3, those devices which may exhibit ESD
sensitivity at levels above 4,000V but have passed all test-
ing up to that level. This testing is performed on a sample
basis at initial device qualification and need not be repeated
unless the device is redesigned. The testing is considered
destructive, even for those devices which do not fail.
A device may be characterized as Class 1 in lieu of testing at a manufacturer's discretion. Some manufacturers, concerned with the possibility of latent damage due to inadequate protection of devices which test as Class 2, and conCf!rned that static charges resulting from handling can run as high as 50 kV, have elected to treat all of their devices as Class 1, thus ensuring that consistent implementation of common handling procedures will provide maximum protection for all devices.
Data generated by an RADC study of electrostatic discharge susceptibility (VZAP-1, Spring 1983) would seem to support that kind of a conservative approach. The data (see Figure 1-24) shows the point at which failure first occurred for a given device. It indicates that there are a number of devices which can be expected to fail between 2 kV and 5 kV, but few that will survive beyond 10 kV.
Those devices which are classified as Class 1 must be marked with one equilateral triangle, and those classified, as Class 2 must be marked with two equilateral triangles to identify them as static sensitive. (Class 3 devices will have no top mark designator.)
TABLE I. Device ESD Failure Threshold Classification
MIL Class ESD Tolerance Top Mark Designation
Class 1
OVto 1,999V
One triangle (i.e., ... )
Class2 2,000V to 3,995V Two triangles (i.e., ...... )
Class3 4,000V and above
No mark
800.ll MIN
1500.ll
WAVEFORM MEASUREMENT TERMINAL
FIGURE 1�23. ESD Test Circuit
TL/F/9592-34
1-12
:0::;�
FAST ESD Protection (Continued)
(')
c;::;:
0
...:m:J'
500 400
m
(')
-u.C.D;.�
-c:;�
fl)
300
200
100
2kV
4kV
6kV
8kV
10kV
12kV
14kV
16kV
FIGURE 1-24. Failure Rate at Ascending ESD Voltages
TL/F/9592-35
ESD Precautionary Measures
elimination of any unnecessary testing or test insertions.
ESD protective measures fall into two categories: those which shield the device from ESD and those which control the occurrence of ESD. ESD shielding can be accomplished by either grounding all of the device leads together, thus providing a more direct path to ground, or by surrounding the device with insulating material that would keep ESD from reaching the device. The first method is most practical during device assembly and environmental test, the second during shipment and storage. However, neither can be utilized during electrical testing.
Most of the handling of ICs, however, occurs during electrical testing. Testing cannot be performed if the device's leads are shorted together, nor can it take place if the device is within an insulated container. Control of ESD during testing is therefore extremely important. This is accomplished through the grounding of all potential sources of
Semiconductor manufacturers have decreased the number of test insertions for many devices by combining parametric, functional and switching tests onto a single insertion test program. Users have minimized handling by relying more heavily on the testing performed by their vendors and by eliminating incoming testing. Pick-and-place systems and other automated board assembly hardware have also helped to minimize device handling. Most systems manufacturers have also implemented procedures that minimize the handling of boards and subassemblies in order to ensure that devices receive no potentially damaging exposure to ESD after board assembly.
Effective control of ESD, however, cannot be accomplished unless the entire work area is designed around ESD concerns. This level of attention to detail is essential to the minimization of ESD problems.
ESD. Stainless steel work surfaces connected to ground
SUMMARY
through an appropriate resistive element provide a harmless bleed-off of any charge that occurs. Requiring that all personnel who handle devices wear ground straps can effec-
Electrostatic discharge will continue to be a major concern for those who use semiconductor devices. As device geo-
tively eliminate the human body and its clothing as sources
metries continue to shrink, the ESD sensitivity of devices
of ESD. It is also important to minimize the handling of devices. This can be partially accomplished through the use of
will increase. Only through proper handling and packaging, and through proper attention to ESD concerns will we be
automated test handlers, which allow the devices to be
able to ensure that long term reliability of key systems is not
loaded into the testers from ESD-protective rails and returned to those rails from the tester. Equally important is the
negatively affected by ESD problems.
I
1-13
"'(.)
;:;
-"'"i::
Q)
(c...a.).
Glossary
Currents-Positive current is defined as conventional current flow into a device. Negative current is defined as conventional current flow out of a device. All current limits are
-.cca:
0
�s
specifed as absolute values.
Ice Supply Current-The current flowing into the Vee supply terminal of a circuit with the specified input conditions
.(...). 0
and the outputs open. When not specified, input conditions are chosen to guarantee worst-case operation.
l1H Input HIGH Current-The current flowing into an input
when a specified HIGH voltage is applied.
l1L Input LOW Current-The current flowing out of an input when a specified LOW voltage is applied.
loH Output HIGH Current-The current flowing out of the output when it is in the HIGH state. For a turned-off opencollector output with a specified HIGH output voltage applied, the loH is the leakage current.
loL Output LOW Current-The current flowing into an output when it is in the LOW state.
los Output Short Circuit Current-The current flowing out of a HIGH-state output when that output is short circuited to ground (or other specified potential).
lozH Output OFF Current HIGH-The current flowing into a disabled TRI-STATE output with a specified HIGH output voltage applied.
lozL Output OFF Current LOW-The current flowing out of a disabled TRI-STATE output with a specified LOW output voltage applied.
Voltages-All voltages are referenced to the ground pin. Negative voltage limits are specified as absolute values (i.e., -1 O.OV is greater than -1.0V).
Vee Supply Voltage-The range of power supply voltage over which the device is guaranteed to operate within the specified limits.
Vco (Max) Input Clamp Diode Voltage-The most negative voltage at an input when a specified current is forced out of that input terminal. This parameter guarantees the integrity of the input diode, intended to clamp negative ringing at the input terminal.
V1H Input HIGH Voltage-The range of input voltages that represents a logic HIGH in the system.
V1H (Min) Minimum Input HIGH Voltage-The minimum allowed input HIGH in a logic system. This value represents the guaranteed input HIGH threshold for the device.
V1L Input LOW Voltage-The range of input voltages that represent a logic LOW in the system
V1L (Max) Maximum Input LOW Voltage-The maximum allowed input LOW in a system. This value represents the guaranteed input LOW threshold for the device.
VoH (Min) Output HIGH Voltage-The minimum voltage at an output terminal for the specified output current loH and at the minimum value of Vee.
Vol (Max) Output LOW Voltage-The maximum voltage at an output terminal sinking the maximum specified load current loL�
VT+ Positive-Going Threshold Voltage-The input voltage of a variable threshold device (i.e., Schmitt Trigger) that is interpreted as a V1H as the input transition rises from below VT - (Min).
VT- Negative-Going Threshold Voltage-The input voltage of a variable thr.eshold device (i.e., Schmitt Trigger) that is interpreted as a V1L as the input transition falls from above VT+ (Max).
AC Switching Parameters
ft Maximum Transistor Operating Frequency-The frequency at which the gain of the transistor has dropped by three decibels.
fmax Toggle Frequency/Operating Frequency-The maximum rate at which clock pulses may be applied to a sequential circuit. Above this frequency the device may cease to function.
tPLH Propagation Delay Time-The time between the specified reference points, normally 1.5V on the input and output voltage waveforms, with the output changing from the defined LOW level to the defined HIGH level.
tPHL Propagation Delay Time-The time between the specified reference points, normally 1.5V on the input and output voltage waveforms, with the output changing from the defined HIGH level to the defined LOW level.
tw Pulse Width-The time between 1.5V amplitude points on the leading and trailing edges of a pulse.
th Hold Time-The interval immediately following the active transition of the timing pulse (usually the clock pulse) of following the transition of the control input to its latching level, during which interval the data to be recognized must be maintained at the input to ensure its continued recognition. A negative hold time indicates that the correct logic level may be released prior to the active transition of the timing pulse and still be recognized.
t5 Setup Time-The interval immediately preceding the active transition of the timing pulse (usually the clock pulse) or preceding the transition of the control input to its latching level, during which interval the data to be recognized must be maintained at the input to ensure its recognition. A negative setup time indicates that the correct logic level may be initiated sometime after the active transition of the timing pulse and still be recognized.
tpHz Output Disable Time (of a TRI-STATE Output) from HIGH Level-The time between the 1.5V level on the input and a voltage 0.3V below the steady state output HIGH level with the TRI-STATE output changing from the defined HIGH level to a high impedance (OFF) state.
tpLz Output Disable Time (of a TRI-STATE Output) from LOW Level-The time between the 1.5V level on the input and a voltage 0.3V above the steady state output LOW level with the TRI-STATE output changing from the defined LOW level to a high impedance (OFF) state.
tpzH Output Enable Time (of a TRI-STATE Output) to a HIGH Level-The time between the 1.5V levels of the input and output voltage waveforms with the TRI-STATE output changing from a high impedance (OFF) state to a HIGH level.
tpzL Output Enable Time (of a TRI-STATE Output) to a LOW Level-The time between the 1.5V levels of the input and output voltage waveforms with the TRI-STATE output changing from a high impedance (OFF) state to a LOW level.
tree Recovery Time-The time between the 1.5V level on the trailing edge of an asynchronous input control pulse and the same level on a synchronous input (clock) pulse such that the device will respond to the synchronous input.
1-14
Logic Symbols and Terminology
The definitions of LOW and HIGH logic levels are: LOW- a voltage defined by V1L; HIGH- a voltage defined by V1H� A LOW condition represents logic 'O'; a HIGH condition, logic '1'.
The logic symbols used to represent the FAST devices follow MIL-STD-8068 for logic symbols. Elements are represented by rectangular blocks with appropriate external AND/OR gates when necessary. A small circle at an external input means that the specific input is active-LOW; (it produces the desired function, in conjunction with other inputs, if its voltage is the lower of the two logic levels in the system). A circle at the output indicates that. when the tune-
0::;�
(')
tion designated is true, the output is LOW. Generally, inputs
c;:::::;:
are at the top and left and outputs appear at the bottom and right of the logic symbol. An exception is the asynchronous Master Reset in some sequential circuits which is always at the left hand bottom corner.
Inputs and outputs are labeled with mnemonic letters as illustrated in Table 1-1. Note that an active LOW function labeled outside of the logic symbol is given a bar over the
0 ::::r .Q...).
Q) (')
-uC...D.;.� -c:;�
label, while the same function inside the symbol is labeled
en
without the bar. When several inputs or outputs use the
same letter, subscript numbers starting with zero are used in
an order natural for device operation.
TABLE 1-1
Label Ix
Meaning
General term for inputs to combinatorial circuits.
Example
So lo 11 12 13 14 15 's 17 S1
'F151 S2 E
J, K
Inputs to JK, SR and D
S,R
flip-flops and latches.
D
So J
'F112
CP
Co
TL/F/9592-20
So J
'F112
CP
0 Co
Ax,Sx
Address or Select inputs, used to select an input, output, data route, junction, or memory location.
LE
Enable, active LOW on all TTL/MSI. A latch
can receive new data when its Enable input
is in the active state.
TL/F/9592-21
Ao 'F259
A1 A2 MR Oo 01 02 03 04 05 05 07
TL/F/9592-22
Do D1 D2 D3 D4 D5 Ds D7
LE 'F373
OE
00 o1 02 03 04 05 Os 07
TL/F/9592-23
II
1-15
(/)
:;C:::J;
�.(:/:)
Q)
-..cCc.ca.aJ.
0
-�3
C...J.
Logic Symbols and Terminology (Continued)
TABLE 1�1 (Continued)
Label PE
Meaning
Parallel Enable, a control input used to synchronously load information in parallel into an otherwise autonomous circuit.
0 p
Parallel data inputs to shift registers and
counters.
PL
Parallel Load; similar to Parallel Enable
except that PL overrides the clock and
forces parallel loading asynchronously.
MR
Master Reset, synchronously resets all
outputs to zero, overriding all other inputs.
SR
Synchronous Reset, resets all outputs
to zero with active edge of clock.
CP
CE, CEP, CET
Clock Pulse, genrally a HIGH-to-LOW-to-HIGH transition. An active HIGH clock (no circle) means outputs change on LOW-to-HIGH clock transition Clock Enable inputs for counters.
Zx,Ox, Fx
General terms for outputs of combinatorial circuits
Example
- Po P1 P2 P3
'F1 GOA
TC
o0 o1 o2 o3
TL/F/9592-24
Po P1 P2 P3
0/D
CE
RC
'F190
CP
TC
PL
o0 o1 o2 o3
TL/F/9592-25
'R =MR on 'F160A/'F161A
SR on 'F162A/'F163A
PE Po P1 P2 P3
CEP
CET
'F16XA
TC
CP
�R o0 o1 o2 03
TL/F/9592-26
Po P1 P2 P3
'F16XA
TC
o0 o1 o2 o3
TL/F/9592-27
loe. 1111. lob l1b loc l1c lod l1d OE
'F258
s
TL/F/9592-28
1-16
Log~c Symbols and Terminology (Continued)
TABLE 1�1 (Continued)
Label Ox
Meaning
General term for latch and flip-flop outputs. If they pass through an enable gate before exiting the package, Q or Q changes to OorO.
TC
Terminal Count output (1111 for up binary
counters, 1001 for up decimal counters, or
0000 for down counters).
Output Enable, used to force TRI-STATE outputs into the high impedance state.
Example
PE Po P1 P2 P3
CEP
CET
'f'16X
TC
CP
�R 00 01 02 03
0:;�
(")
c :::+ 0
...:m::J"
m
(")
-.C.'D.
iii'
-.(;'
"'
TL/F/9592-29
CP 'F374
OE
This nomenclature is used throughout this book and may differ from nomenclature used on other data books, where outputs use alphabetic subscripts or use number sequences starting with one.
Handling Precautions for Semiconductor Components
The following standard handling precautions should be observed for oxide isolation, shallow junction processed parts, such as FAST or 1OOk ECL:
1. All National devices are shipped in conducting foam or antistatic tubes. When they are removed for inspection or assembly, proper precautions should be used.
TL/F/9592-30
2. National devices, after removal from their shipping material, should be placed leads down on a grounded surface. Under no circumstances should they be placed in polystyrene foam or non-conducting plastic trays used for shipment and handling of conventional ICs.
3. Individuals and tools should be grounded before coming in contact with these devices.
4. Do not insert or remove devices in sockets with power applied. Ensure that power supply transients, such as occur during power turn-on or off, do not exceed maximum ratings.
5. After assembly on PC boards, ensure that static discharge cannot occur during handling, storage or maintenance. Boards may be stored with their connectors surrounded with conductive foam.
II
1-17
Section 2 Ratings, Specifications, and Waveforms
Section 2 Contents
Unit Loads......................................................................... 2-3 AC Loading and Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 Family DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2-2
::c
~National
~s�
(Q
Q Semiconductor
Jn
en
"C
CD
(")
Ratings, Specifications and Waveforms
-:c:::;;;�
I�
c;�
For convenience in system design, the input loading and fan-out characteristics of each circuit are specified in terms of unit loads.
One unit load in the HIGH state is defined as 20 �A; thus both the input HIGH leakage current, l1H. and the output HIGH current-sourcing capability, loH. are normalized to 20 �A. The specified l1H for a typical FAST� single load input is 20 �A or 1.0 U.L. The loH rating for a FAST output depends upon whether the device has a standard or
the 54F/74F373 Transparent Latch and the 29F52 Regis-
e:nJ
tered Transceiver are reproduced below. In the second column from the right, the 54F/74F373 input
I�
:aJ .
HIGH/LOW load factors are 1.0/1.0 with the first number
=E
representing l1H and the second representing l1L� The 29F52 has input HIGH/LOW load factors of 1.0/1.0 for the typical FAST single load inputs and 3.5/ 1.083 for the register in-
-I<�
CD
0...
puts. For testing procurement purposes, these unit load
3
specifications can easily be translated into actual test limits
en
TRI-STATE� output or if the device is a buffer/line driver.
by multiplying the HIGH/LOW load factors by 20 �A and
The loH rating for a standard FAST device is 1.0 mA or 50
0.6 mA respectively. The current limits are listed as well.
U.L., while TRI-STATE is 3.0 mA or 150 U.L. and line driver/ buffers specify loH of 12.0 mA or 600 U.L.
Also in this column are the output HIGH/LOW output load factors, with the first number representing loH and the sec-
Similarly, one unit load in the LOW state is defined as
ond representing loL.These load factors can be translated
0.6 mA and both the input LOW current, l1L. and the output
to actual test limits by multiplying them by 20 �A and 0.6 mA
LOW current-sinking capability, loL� are normalized to
respectively. These are shown in the far right column. The
0.6 mA. The specified maximum l1L for a typical FAST single
54F/74F373 output HIGH/LOW drive factors are
load input is 0.6 mA or 1.0 U.L. However, the loL rating
150/40 (33.3) which translate into an loH of 3.0 mA and loL
differs among standard, TRI-STATE and buffer/line driver
of 24 mA for commercial grade and 20 mA for military
outputs. The loL rating for a standard output is 20 mA or
grade. The 29F52 A-Register outputs are TRI-STATE out-
33.3 U.L. FAST devices with TRI-STATE outputs specify loL
puts with HIGH/LOW drive factors of 150/40 (33.3) indicat-
at 24 mA or 40 U.L. for commercial temperature range and
ing an loH of 3 mA and loL of 24 mA for commercial and
20 mA or 33.3 U.L. for military temperature range. The loH
20. mA for military. The 8-Register outputs specify unit load
rating for a FAST buffer/line driver output is 64 mA or
factors of 600/106.6 (80) translating into an loH of 12 mA
106.6 U.L. for the commercial temperature range and 48 mA
and loL of 64 mA for commercial and 48 mA for military.
or 80 U.L. over the military temperature range.
On the data sheets the input and output load factors are listed in the Input Loading/Fan-Out table. The tables from
Unit Loading/Fan Out 29F52: See Section 2 for u.L. definitions
Pin Names
Ao-A7
80-87
OEA CPA CEA OEB CP8 CE8
Description
A-Register Inputs A-Register Outputs 8-Register Inputs 8-Register Outputs Output Enable A-Register A-Register Clock A-Register Clock Enable Output Enable 8-Register 8-Register Clock 8-Register Clock Enable
U.L. HIGH/LOW
3.5/1.083 150/40 (33.3)
3.5/1.083 600/ 106.6 (80)
1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0
54F/74F
Input l1Hll1L Output loH/loL
70 �A/0.65 mA -3 mA/24 mA (20 mA)
70 �A/0.65 mA -12 mA/64 mA (48 mA)
20 �A/-0.6 mA 20 �A/-0.6 mA 20 �A/-0.6 mA 20 �A/-0.6 mA 20 �Al - 0.6 mA 20 �A/-0.6 mA
2-3
0
-E
0
cC>ul>
3:
"ccCu
Unit Loading/Fan Out 54F/74F373: See Section 2 tor U.L. definitions
Pin Names
Description
Do-D7
Data Inputs
U.L. HIGH/LOW
1.011.0
29F
Input l1Hll1L Output loHllOL 20 �A/-0.6 mA
c 0
:;0::;
cu
LE OE Oo-07
Latch Enable Input (Active HIGH) Output Enable Input (Active LOW) TRI-STATE Latch Outputs
1.0/1.0 1.0/1.0 150/40 (33.3)
20 �A/-0.6 mA 20 �A/-0.6 mA -3 mA/24 mA (20 mA)
(,)
;�c::; AC Loading and Waveforms
Cl> 0..
Figure 2-1 shows the AC loading circuit used in characteriz-
CJ) ing and specifying propagation delays of all FAST devices,
en
ec n
unless otherwise specified in the data sheet of a specific device. The use of this load, which differs somewhat from
:;::;
cu a:
previous practice, provides more meaningful information
and minimizes problems of instrumentation and customer
correlation. In the past, + 25�C propagation delays for TTL
use in calculating minimum cycle times. Since the rising or falling waveform is RC-controlled, the first 0.3V of change is more linear than the first 05V and is less susceptible to external influences. More importantly, perhaps, from the system designer's point of view, a AV of 0.3V is adequate to ensure that a device output has turned OFF; measuring to a AV of 0.5V merely exaggerates the apparent Disable time
devices were specified with a load of 15 pF to ground; this
and thus penalizes system performance, since the designer
required great care in building test jigs to minimize stray
must use the Enable and Disable times to devise worst-case
capacitance, and implied the use of high impedance, high
timing signals to ensure that the output of one device is
frequency scope probes. FAST circuits changed to 50 pF of
disabled before that of another device is enabled.
capacitance allowing more leeway in stray capacitance and also loading the device during rising or falling output transitions. This more closely resembles the loading to be expected in average applications and thus gives the designer more useful delay figures. The net effect of the change in AC load is to increase the observed propagation delay by an average of about 1 ns.
Figure 2-2 describes the input signal voltages recommended for use when testing FAST circuits. The AC input signal levels follow industry convention of V1N switching 0 to 3 volts. DC low input levels are typically 0 to V1L. and high input levels are typically V1H to Vee- Input thresholds are guaranteed during Vol and VoH tests. High level noise immunity is the difference between VoH and V1H� Low level
The soon resistor to ground, in Figure 2-1, acts as a ballast,
noise immunity is the difference between V1L and Vol�
to slightly load the totem-pole pull-up and limit the quiescent
HIGH-state voltage to about + 3.5V. Otherwise, an output would rise quickly to about + 3.5V but then continue to rise very slowly to about + 4.4V. On the subsequent HIGH-to-
Noise-free V1H or V1L levels should not induce a switch on the appropriate output of the FAST device. When testing in
an automatic test environment, extreme caution should be
taken to ensure that input levels plus noise do not go into
LOW transition the observed tPHL would vary slightly with
the transition region.
duty cycle, depending on how long the output voltage was allowed to rise before switching to the LOW state. Perhaps more importantly, the 500n resistor to ground can be a high frequency passive probe for a sampling scope, which costs much less than the equivalent high impedance probe. Alternatively, the 500n load to ground can simply be a 450n resistor feeding into a son coaxial cable leading to a sampling scope input connector, with the internal 50n termination of the scope completing the path to ground. Note that with this scheme there should be a matching cable from the device input pin to the other input of the sampling scope; this also serves as a 50n termination for the pulse generator that supplies the input signal.
Good high frequency wiring practices should be used in constructing test jigs. Leads on the load capacitor should be as short as possible to minimize ripples on the output waveform transitions and to minimize undershoot. Generous ground metal (preferably a ground plane) should be used for the same reasons. A Vee bypass capacitor should be provided at the test socket, also with minimum lead lengths. Input signals should have rise and fall times of 2.5 ns and
signal swing of OV to + 3.0V. Rise and fall times ~ 1 ns
should be used for testing fmax or pulse width. A 1.0 MHz square wave is recommended for most propagation delay tests. The repetition rate must necessarily be increased for testing fmax� A 50% duty cycle should always be used when
Also shown in Figure 2-1 is a second 500n resistor from the
testing fmax� Two pulse generators are usually required for
device output to a switch. For most measurements this
testing such parameters as setup time, hold time, recovery
switch is open; it is closed for measuring a device with
time, etc.
open-collector outputs and for measuring one set of the En-
able/Disable parameters (LOW-to-OFF and OFF-to-LOW)
of a TRI-STATE output. With the switch closed, the pair of
500n resistors and the + 7.0V supply establish a quiescent HIGH level of +3.5V, which correlates with the HIGH level
discussed in the preceding paragraph.
Precautions should be taken to prevent damage to devices by electrostatic charge. Static charge tends to accumulate on insulated surfaces, such as synthetic fabrics or carpeting, plastic sheets, trays, foam, tubes or bags, and on ungrounded electrical tools or appliances. The problem is much worse in a dry atmosphere. In general, it is recom-
Figure 2-5 shows that the Disable times are measured at
mended that individuals take the precaution of touching a
the point where the output voltage has risen or fallen by
known ground before handling devices. To effectively avoid
0.3V from the quiescent level (i.e., LOW for tPLZ or HIGH for
electrostatic damage to FAST devices it may be necessary
tpHz), compared to a AV of 0.5V used in previous practice.
for individuals to wear a grounded wrist strap when handling
This change enhances the repeatability of measurements
devices.
and gives the system designer more realistic delay times to
2-4
OPEN
.J ALL OTHER
soo.n
soo.n
�includes jig and probe capacitance
FIGURE 2-1. Test Load
5.0Y
TL/F/9600-1
3.0Y 2.SY 2.0Y
O.BY 0.4Y
OY
AC Test
O.C. LOW O.C. HIGH
Input Levels Input Range Input Range
HIGH Level Noise
Immunity
LOW Level Noise
Immunity
Transl\lon Region
TL/F/9600-2
FIGURE 2-2. Test Input Signal Levels
DATA IN
DATA OUT
TL/F/9600-3
FIGURE 2-3. Propagation Delay Waveforms for Inverting and Non-Inverting Functions
CLOCK OR CONTROL
INPUT
Vm= 1.SV
Vm
DATA OUT
Vm
FIGURE 2-4. Propagation Delay, Pulse Width Waveforms
TL/F/9600-4
OUTPUT CONTROL
DATA OUT
- - - " " - - - - � I - - - - ' ' - - YoH 0.3V
DATA OUT
TLIF/9600-5
FIGURE 2-5. TRI-STATE Output HIGH and LOW Enable and Disable Times
Vm =I.SY DATA
IN Ym= I.SY
CLOCK OR CONTROL
INPUT
TL/F/9600-6
FIGURE 2-6. Setup Time, Hold Time and Recovery Time Waveforms
2-5
ti)
-.E..
0
Q)
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
>
CtS
please contact the National Semiconductor Sales
3: Office/Distributors for availability and specifications.
"cC
Storage Temperature
CtS Ambient Temperature under Bias
-65�C to + 150�C - 55�C to + 125�C
ti)
c
Junction Temperature under Bias
;:0::;
CtS
Ceramic Plastic
(.)
:;::: Vee Pin Potential to
- 55�C to + 175�C - 55�C to + 150�C
'(3
Ground Pin
-0.5Vto +7.0V
Q)
a. Input Voltage (Note 2)
-0.5Vto +7.0V
tn
ucc::rn
;:::;
Input Current (Note 2)
Voltage Applied to Output in HIGH State (with Vee = OV)
-30 mA to+ 5.0 mA
aCt:S
Standard Output TRI-STATE Output
-0.5VtoVcc -0.5Vto +5.5V
Current Applied to Output
in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under
these conditions is not implied.
�
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V +4.5Vto +5.5V
DC Electrical Characteristics
Symbol
Parameter
V1H
Input HIGH Voltage
V1L
Input LOW Voltage
Vco
Input Clamp Diode Voltage
54F/74F
Units Vee
Min
Typ
Max
Conditions
2.0
v
Recognized as a HIGH Signal
0.8
v
Recognized as a LOW Signal
-1.2
v Min l1N = -18 mA, Non 110 Pins
VoH
Output HIGH
Voltage
54F 10% Vee 2.5
54F 10% Vee 2.4
54F 10% Vee 2.0
74F 10% Vee 2.5
74F 10% Vee 2.4
74F 10% Vee 2.0
74F 5% Vee
2.7
74F 5% Vee
2.7
74F 5% Vee
2.0
loH = -1 mA, Standard or TRI-STATE Outputs loH = -3 mA, TRI-STATE or Buffer/Line Driver Outputs loH = -12 mA, Buffer/Line Driver Outputs loH = -1 mA, Standard or TRI-STATE Outputs
v Min loH = -3 mA, TRI-STATE or Buffer/Line Driver Outputs
loH = -12 mA, Buffer/Line Driver Outputs loH = -1 mA, Standard or TRI-STATE Outputs loH = -3 mA, TRI-STATE or Buffer/Line Driver Outputs loH = -15 mA, Buffer/Line Driver Outputs
Vol
Output LOW
Voltage
54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee 74F 10% Vee
0.5
loL = 20 mA, Standard or TRI-STATE Outputs
0.55
loL = 48 mA, Buffer/Line Driver Outputs
0.5
v Min loL = 20 mA, Standard Outputs
0.5
loL = 24 mA, TRI-STATE Outputs
0.55
loL'= 64 mA, Buffer/Line Driver Outputs
l1L
Input LOW Current
-0.6 mA Max V1N = 0.5V, 1.0 U.L. Input -1.2 mA Max V1N = 0.5V, 2.0 U.L. Input n(-0.6) mA Max V1N = 0.5V, n U.L. Input
l1H
Input HIGH
54F
Current
74F
20.0 �A Max V1N = 2.7V
5.0
lsv1
Input HIGH Current 54F
Breakdown Test 74F
100 �A Max V1N = 7.0V
7.0
lsv1T
Input HIGH Current 54F
Breakdown (i/o)
74F
1.0 mA Max V1N = 5.5 V
0.5
le Ex
Output HIGH
54F
Leakage Current 74F
250 �A Max VouT =Vee
50
V10
Input Leakage
74F
4.75
Test
v
110 = 1.9 �A 0.0
All Other Pins Grounded
loo
Output Leakage
74F
Circuit Current
V100 = 150mV
3.75
�A 0.0
All Other Pins Grounded
2-6
DC Electrical Characteristics (Continued)
-:D
D>
s�
Symbol
Parameter
lozH
Output Leakage Current
CQ
54F/74F
g>
Units Vee
Conditions
en
Min
Typ
Max
"C
CD
50
�A
Max Vour = 2.7V, TRI-STATE Outputs, Non 1/0
(")
::;;
lozL
l1H + lozH l1L + lozL
las
Output Leakage Current Output Leakage Current Output Leakage Current Output Short-Circuit Current
lzz loHe
leeH
Bus Drainage Test Open Collector, Output OFF Leakage Test Power Supply Current
-60 -100
-50 70
�.A �A
Max Vour = 0.5V, TRI-STATE Outputs, Non 1/0 Max V110 = 2.7V, 1/0 Pins
-(;'
D>
s�
:::s
-650 -150
�.A mA
Max Max
V110 = 0.5V, 110 Pins Vour = OV, Standard or TRI-STATE Outputs
"':cD::>s.
-225
mA
Max Vour = OV, Buffer/Line Driver Outputs
500
�A
o.ov Vour = 5.25V TRI-STATE Outputs
Vour = Vee. o.c. Outputs
250
�A
Min
-~
<
CD
0...
3
mA
Max Vour =HIGH
"'
lecL
Power Supply Current
mA
Max Vour =LOW
leez
Power Supply Current
mA
Max Vour = HIGHZ
2-7
Section 3 Design Considerations
El
Section 3 Contents
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Threshold and Noise Margins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test and Specification Improvements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmission Lines and Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-3 3-4 3-5 3-5 3-14 3-15
3-2
FAST� Design Considerations
FAST� is a high-speed logic family that achieves speeds typically 30% faster than the Schottky family with a corresponding power reduction of approximately 75%. It is fabricated with an advanced oxide isolation technique, lsoplanar II, which produces transistors with very high, well-controlled switching speeds, extremely small parasitic capacitances and fr in excess of 5 GHz. Since the family is designed to be pin-compatible with other TIL families such as Schottky, Low Power Schottky and standard TIL, existing designs can be easily upgraded. FAST logic offers significant improvement over the Schottky family in addition to improved speed and power specifications. Other key advantages are higher input threshold levels (improving noise margins), reduced input loading, and increased output drive. The FAST family contains a full complement of circuits for more efficient design capabilities: small scale integration, medium scale integration and large scale integration. Fairchild engineers had some specific design objectives in mind when they developed the FAST logic family. The primary objective was the improvement of the circuit speedpower performance versus earlier TIL families. Another important objective was increasing threshold levels to improve DC noise immunity. Other goals were maintaining or improving the output drive of Schottky for improved line driving capability, and reducing input loading for increasing the overall fanout out of the family. Output and input voltage levels, functions and pinouts were standardized to previous TTL families to maintain compatibility. The primary design consideration was to improve speed while reducing power. The speed of any device is limited by the charge storage of the transistors. The time required to remove this charge is proportional to the capacitance and current available. Thus, to improve the speed, either the internal resistor values must be lowered to increase the available current and therefore remove the charge faster, such as in the Schottky family, or the capacitance must be reduced. The speed-power curve shown in Figure 3-ta was used empirically to determine the optimum operating power level for the FAST family. Several internal gates programmed at a variety of power levels were produced on a wafer and the propagation delay of an internal gate for each power level was measured.
National Semiconductor
e~n
Application Note 661
-f
c
c<eeDn�
:::s
0
ce:0:n::s
a.
-<D
Dl c;�
4.5 ,...-,,........-...,......___,,--.....,....-.....-.......-~
e::n:s
4.0 1--<..+---l---<f---l---+----+--l
3.5 l-t-+---1---<--l---+----+--l
3.0 l--++--+--1---t---l-----1--1
Ill
c
2.5 l---H---+--l---t---l-----1--1
2.0 ~.75ns@ 4mW-1
1.5
l Il
1.0 '--......L.-...1.-__J'----L-..l....---L-....I
0
4
8 10 12 14
mW
TL/F/9607-1
b.
56 100k ECL
48
~
E
I
40
z
0
I<a=.
32
iii
VI
24
Ci
.e..t.:.:.
~
16
a0 .
8
m
2 4
10 12 14
GATE DELAY- ns
TL/F/9607-2
FIGURE 3-1. Speed-Power Product
As can be seen from the curves, power levels significantly below 4 mW per gate exhibit a dramatic degradation in performance. Power levels significantly above 4 mW, however, appear to have passed the point of diminishing returns with only minor improvements in propagation delay resulting from increased power. It was therefore concluded that the FAST family could be biased at 4 mW achieving a 1.75 ns propagation delay.
3-3
cen
;0.c:.a;.
C1>
Figure 3-tb compares the FAST logic family with previous TTL and ECL logic families. Each curve groups families with similar technologies. The first line, known as "gold doped,"
�"uC;
c
0
groups together the 7400 and the 74H families into one technology grouping. These saturating logic families can be seen to have a relatively poor speed-power curve.
0 c
�uc::;:n
The second curve notes the Schottky, Low Power Schottky and 1Ok ECL families. They use non-gold doped, soft saturated (Baker clamped) or current steering logic in order to
cC1>
achieve their speed-power performance; however, they still
t;
employ the planar technology. The last curve, which shows the FAST family with its ECL counterpart, the 100k ECL
u<i.:
family, employs the lsoplanar technology. With FAST lsoplanar technology, 3 ns propagation delays at only 4 mW
power dissipation are achieved with SSI devices.
THRESHOLD AND NOISE MARGINS
The noise margins most often cited for TTL obtained by subtracting the guaranteed maximum input HIGH level, V1H� of a driven input from the guaranteed minimum output HIGH level, VoH. of the driving source, and subtracting the guaranteed maximum output LOW level, VoL. of the driver from
the guaranteed minimum input LOW level, V1L. of a driven circuit. The guaranteed worst-case values of these parameters vary slightly among the various circuit families and are summarized in Table 111-1. Note that although the 9000 Series V1H and V1L specifications have different limits at different temperatures, they are grouped with the 54/74 family in the table as a matter of convenience. Note also that the VoL limit listed for 74LS is 0.5V, whereas these circuits are also specified at 04.V at a lower level of loL� Noise margins calculated in this manner are quite conservative, since it is assumed that both the driver output characteristics are worst-case and that Vee is on the low side for the driver and on the high side for the receiver.
Figure 3-2 shows how load capacitance affects the propagation delay of Low Power Schottky, Schottky and FAST gates, flip-flops, registers and decoders, etc. As would be expected, Low Power Schottky TTL shows greater sensitivity since LS output drive capability is not as great as either Schottky or FAST. Significantly, FAST is less affected than Schottky by load capacity. Figure 3-2 shows propagation delay versus load capacitance for buffers and line drivers since they are designed for greater output drive.
TABLE 111-1. Parameter Limits
TTL Families
Military (-55�C to+ 125�C
Commercial (O�C to + 70�C)
Units
V1l V1H Vol VoH V1L V1H Vol VoH
TTL
Standard TTL, 9000, 54/74
0.8 2.0
0.4
2.4
0.8 2.0
0.4
2.4
v
FAST
54F/74F
0.8 2.0 0.5
2.4
0.8 2.0
0.5
2.5
v
S-TTL
Schottky TTL, 54S/74S, 93S
0.8 2.0
0.5
2.5 0.8 2.0 0.5
2.7
v
LS-TTL Low Power Schottky TTL, 54LS/74LS 0.7 2.0
0.4
2.5
0.8 2.0
0.5
2.7
v
VoL and VoH are the voltages generated at the output. V1L and V1H are the voltages required at the input to generate the appropriate levels. The numbers given above are guaranteed worst-case values for standard outputs.
a. 'FOO
b. 'F240
.,
20..-~~....,..---,----..--.~...--....-..,..-~
c
I
18
~ 16
c z
14
0
~
121---+---+--+--+--.+---l~+--~-+-~ 101---+---+-_...,"-+---+---l--~.,_---~
a.
0
a0:.:
81---+--V--+--+-o~~---
I _,
61--:;t'f---+-.~"'74~--l___,....~~"-t-~
.J:
4i-..~-r----:h~....,."'--1~t-,---..,--~
-~
100
200
CL - LOAD CAPACITANCE- pF
TL/F/9607-3
1s~~....-~~~--,-~--.~~~~..,..-~__,...~~
c
I
161--~-+-~-+-__,--+~__,t--~+-__,-+-~--+~--l
~
:z: 0
~
141--~-t-~-+-__,-+~~t--~+-__,-+-~~.c+~~--j
121--~+-~+-~-t-~+-~-::i.-~_,,,,,.,:....-il--""'~~boo-"........,~ 101-----f~-+-~-+-~tp~LH~~c:::..._-+--::::;..-1"'[..........-=---+----1
.Y"" ~
~
j
-~ OL-~-'--~-"-~_,_~--'~~"'-~-'-~_._~__, 0 100 200 300 400 500 600 700 BOO
CL - LOAD CAPACITANCE- pF
TL/F/9607-4
FIGURE 3-2. Propagation Delay vs Load Capacitance
3-4
Notice also that for Schottky, the HIGH-to-LOW output transition is more affected than its LOW-to-HIGH transition, while for FAST both transitions are equally affected. This indicates a better balance in the design of the FAST output, and minimizes pulse stretching and compressing.
Designers are cautioned that curves of this type do not apply when the load capacitance is distributed along an interconnection.
TEST AND SPECIFICATION IMPROVEMENTS
Because the circuitry and technological improvements (feedback and speedup diodes and the Miller Killer circuitry) yield well-controlled AC parameters, the FAST family can be specified over extremes of external influences. FAST is the first TTL logic family which does not require derating estimates for worst-case design. This has been accomplished by specifying minimum and maximum propagation delays over the operating temperature and supply voltage ranges
with 50 pF loading.
In order to achieve easier correlation with our customers' needs, a change in the actual AC test load was needed. Previously, most TTL families were measured with three serial diodes in parallel with the load capacitor. For the FAST
logic family, a 50 pF capacitance in parallel with a soon
resistor is employed. This facilitates fabrication of low capacitance test jigs. It also provides better correlation with customers' measurements of propagation delay. Passive
soon scope probes, which are less expensive and easier to
use than the high impedance FET input scope probes, can be employed. This facilitates measurement of the AC performance on automatic test equipment and yields more conservative AC figures than are achieved with the previous AC load technique.
DESIGN CONSIDERATIONS
There are areas of concern which need to be addressed when designing with any high performance logic family. These topics include: transmission line concepts, printed circuit board layout, interfacing between technologies, open collector outputs, fanout, and unused inputs.
For additional information, please refer to National's FAST Applications Handbook.
TRANSMISSION LINES
Practical transmission lines, cables and strip lines used for TTL interconnections have a characteristic impedance be-
tween 30n and 1son. FAST is capable of driving a son line
under worst-case conditions.
"T1
These considerations, applicable only when the round trip
)>
CJ)
delay of the line is longer than the rise or fall time of the
-I
driving signal (2td > tr), do not affect most TTL interconnec-
c
tions. Short interconnections do not behave like a resistive transmission line, but more like a capacitive load. Since the
cCeenD�
rise time of different TTL outputs is known, the longest inter-
:::s
connection that can be tolerated without causing transmis-
0
0
sion line effects can easily be calculated and is listed in Table 111-11.
TABLE 111-11. PC Board Interconnections
TILFamily Rise Time Fall Time Max Interconnection Length
54174, 54/74LS 6-9 ns 4-6 ns 18 in. (45 cm)
ae:::ns:
-CD
""II
D>
5�
:e::ns
548/748
4-6 ns 2-3 ns 9 in. (22.5 cm)
FAST
1.8-2.8 ns 1.6-2.6 ns 7.5 in. (19 cm)
Assuming 1.7 ns/foot propagation speed, typical for epoxy fiberglass PC boards with fr = 4.7.
Slightly longer interconnections show minimal transmission line effects; the longer the interconnections, the greater the chance that system performance may be degraded due to reflections and ringing.
TRANSMISSION LINE EFFECTS
The fast rise and fall times of TTL outputs (2.0 ns to 6.0 ns) produce transmission line effects even with relatively short (<2 ft) interconnections. Consider one TTL device driving another and switching from the LOW to the HIGH state. If the propagation delay of the interconnection is long compared to the rise time of the signal, the arrangement behaves like a transmission line driven by a generator with a non-linear output impedance. Simple transmission line theory shows that the initial voltage step at the output just after the driver has switched is
Zo Vour= VE - - -
Zo +Ro
where Zo is the characteristic impedance of the line, Ro is the output impedance of the driver, and VE is the equivalent output voltage source in the driver, (i.e., Vee minus the forward drop of the pull-up transistors).
Figure 3-3 shows how the initial voltage step can be determined graphically by superimposing lines of constant impedance of the static input and output characteristics of TTL elements. The constant impedance lines are drawn from the intersection of the V1N and Vol characteristics which is the quiescent condition preceding a LOW-to-HIGH transition. After this transition the VoH characteristic applies, and the intersection of a particular impedance line with the VoH characteristic determines the initial voltage step. The VoH
characteristic shown in Figure 3-3 has an Ro of about son
and VE of approximately 4.0V, for calculation purposes.
3-S
1 mA
5.0 6.0
Volts
TL/F/9607-5
FIGURE 3-3. Initial Output Voltage of TTL Driving Transmission Line
This initial voltage step propagates down the line and reflects at the end, assuming the typical case where the line is open-ended or terminated in an impedance greater than its characteristic impedance Zo. Arriving back at the source, this reflected wave increases VouT� If the total round-trip delay is larger than the rise time of the driving signal, there is a staircase response at the driver output and anywhere along the line. If one of the loads (gate inputs) is connected to the line close to the driver, the initial output voltage VouT might not exceed V1H� This input is then undetermined until after the round trip of the system. Figure 3-4 shows the 'FOO driver output waveform for four different line impedances.
z For 0 of 25!1 and 50!1, the initial voltage step is in the
threshold region of a TTL input and the output voltage only
rises above the guaranteed 2.0V V1H level after a reflection returns from the end of the line. If VouT is increased to
> 2.0V, by either increasing Zo or decreasing Ro. additional delay does not occur. Ro is characteristic of the driver out-
put configuration, varying between the different TTL speed categories. Zo can be changed by varying the width of the conductor and its distance from ground. Table Ill-Ill lists the lowest transmission line impedance that can be driven by different TTL devices to insure an initial voltage step of 2.0V.
a.
c.
5.0
5.0
4.0
4.0
3.0
3.0
2.0 rn7777?-'fT77?7777/'7777/'7777/'7777:'7777:'77nm777 0.8 ~"-""'~�,t.:..L..L.L.L...1.:..L..L.L.L...1.:..L..L.LLl.:..L..L.L.LJ.:..L..L.LLl.:..L..L.LLl.:..L..L.LLI.~
2.0 rn7777?'7777/'77m--;'7777/'7777?'7777/'7777/'7777/m7T7 0.8 jLL.c..L.t.~,cL..LL.Lc..L.t.L.Lc..L.t.L.Lc..L.t.:L.LLL...l.:..L..L.LLl.:..L..L.LLl.:..L..L.LLl.:..LL.
50
100
b.
TL/F/9607-6
5.0
4.0
3.0 2.0 i.-,,.,~.,...,.,,..,.,,.~,.-n..,..,.,777..,..,.,777..,-,.777-rr-777-rr-777-?"T'7?-r77
0.8~"-""'~,_._,.:..L..L.L...LJ.:..L..L.L.LJ.:..L..L..L.L...:..L..L..L.L...:..L..L..L.L...:..L..L..L.L...~.L.L...~
TL/F/9607-8
d.
5.0 4.0 3.0 2.0 rn'7777/'7777/'7777.l'7777::'7777/'7777:'77'77:'1'7777:m777 0.8 JLLLL.t.~4f'-~"""f!'ZLLL.t.~LL.t.:L.L'LL~.L.L...~~~.L.L...<..LL.
50
100
150
50
100
150
TL/F/9607-7
TL/F/9607-9
FIGURE 3�4. TTL Driving Transmission Line
Note that the worst-case value, assuming a + 30% tolerance on the current limiting resistor and a -10% tolerance on Vee. is
80% higher than the value for nominal conditions.
3-6
TTLFamllyor Device
54/74 54S/74S 5440/7440 54S/74S40 54F/74FOO 54F/74F258 54F/74F240
Supply Voltage (Vee)
"T1
TABLE 111-111. Transmission Line Driving Capablllty
e)>n
Collector
Lowest Transmission Line Impedance n
-I
c
Resistor R!l
Worst Case
(R + 30%)
Nominal
Best Case (R - 30%)
cr<enD�
::s
130
241.4
204.8
136.8
84.6
75.8
0
55 100 25 45 25
110.0 185.7 50.0 66.2 36.76
92.2 157.5 41.9 57.7 32.0
61.1 105.2 27.7 40.9 22.7
37.5 65.1 17.0 27.6 15.3
33.4 58.3 15.2 25.0 13.9
r:0:ns ii
-<..D,
D>
a�
15
22.0
19.2
13.6
9.2
8.3
r::ns
4.50
4.75
5.00
5.25
5.50
A graphical method provides excellent insight into the effects of high-speed digital circuits driving interconnections acting as transmission lines. A load line is drawn for each input and output situation. Each load line starts at the previous quiescent point, determined where the previous load line intersects the appropriate characteristic. The magnitude of the slope of the load lines is identical and equal to the characteristics impedance of the line, but alternate load lines have opposite signs representing the change in direction of current flow. The points where the load lines intersect the input and output characteristics represent the voltage and current value at the input or output, respectively, for that reflection. The results, Figure 3-5, are shown with and without the input diode and illustrate how the input diode on TTL elements assists in eliminating spurious switching due to reflection.
TRANSMISSION LINE CONCEPTS
The interactions between wiring and circuitry in high-speed systems are more easily determined by treating the interconnections as transmissions lines. A brief review of basic concepts is presented and simplified methods of analysis
a. With Input Diode
Volts
are used to examine situations commonly encountered in digital systems. Since the principles and methods apply to any type of logic circuit, normalized pulse amplitudes are used in sample waveforms and calculations.
SIMPLIFYING ASSUMPTIONS For the great majority of interconnections in digital systems, the resistance of the conductors is much less than the input and output resistance of the circuits. Similarly, the insulating materials have very good dielectric properties. These circumstances allow such factors as attenuation, phase distortion and bandwidth limitations to be ignored. With these simplifications, interconnections can be dealt with in terms of characteristic impedance and propagation delay.
CHARACTERISTIC IMPEDANCE The two conductors that interconnect a pair of circuits have distributed series inductance and distributed capacitance between them, and thus constitute a transmission line. For any length in which these distributed parameters are constant, the pair of conductors have a characteristic imped-
b. Without Input Diode
Volts
- - - Theorellcal -Actual
- - - Theoretical -Actual
-1
-1
20 40 60 80 100 120 140 160 180 TL/F/9607-10
-2
-3
ns~-'---''----'-~....J...~..i.-~.1..----1~-1.~...i...~..1.-
20 40 60 80 100 120 140 160 180 TL/F/9607-11
FIGURE 3-5. Ringing Caused by Reflections
3-7
(/)
c:
...:0;
C'a
C1)
ance Za. Where quiescent conditions on the line are determined by the circuits and terminations, Zo is the ratio of transient voltage to transient current passing by a point on
"�uC; c:
0
the line when a signal change or other electrical disturbance occurs. The relationship between transient voltage, transient current, characteristic impedance, and the distributed
(.)
parameters is expressed as follows:
c: �uC;>
V/I = Zo = JLo/Co
where Lo = inductance per unit length, and Co = capaci-
cC1)
tance per unit length. Zo is in ohms, Lo in henries, and Co
ten-
in farads.
<( PROPAGATION VELOCITY
LL
Propagation velocity (v) and its reciprocal, delay per unit
length o, can also be expressed in terms of Lo and Co. A
consistent set of units is nanoseconds, microhenries and
picofarads, with a common unit of length.
o v = 1/Aoco
= AoCo
These equations provide a convenient means of determining the Lo and Co of a line when delay, length and imped-
o ance are known. For a length 1 and delay T, is the ratio
T/1. To determine Lo and Co. combine these equations.
Lo= oZo c0 = o!Zo
More formal treatments of transmission line effects are available from many sources.
TERMINATION AND REFLECTION
A transmission line with a terminating resistor is shown in Figure 3-6. As indicated, a positive step function voltage travels from left to right. To keep track of reflection polarities, it is convenient to consider the lower conductor as the voltage reference and to think in terms of current flow in the top conductor only. The generator is assumed to have zero internal impedance. The initial current 11 is determined by V1 and Zo.
_ ..
v1,1 1-
1,-
~T
v; T
+
v, rv
v, 11= fci
:, t :>~RT
- "i
LINE LENGTH = 1
FIGURE 3-6
TL/F/9607-12
DELAY= T = 1 o
If the terminating resistor matches the line impedance, the ratio of voltage to current traveling along the line is matched by the ratio of voltage to current which must, by Ohm's law, always prevail at Rr. From the viewpoint of the voltage step generator, no adjustment of output current is ever required; the situation is as though the transmission line never existed and Rr has been connected directly across the terminals of the generator.
From the Rr viewpoint, the only thing the line did was delay the arrival of the voltage step by the amount of time T.
When Rr is not equal to Zo, the initial current starting down the line is still determined by V1 and Zo but the final steady
state current, after all reflections have died out, is determined by V1 and Rr (ohmic resistance of the line is assumed to be negligible). The ratio of voltage to current in the initial wave is not equal to the ratio of voltage to current demanded by Rr. Therefore, at the instant the initial wave arrives at Rr. another voltage and current wave must be generated so that Ohm's law is satisfied at the line-load interface. This reflected wave, indicated by Vr and Ir in Figure 3-6, starts to return toward the generator. Applying Kirchoff's laws to the end of the line at the instant the initial wave arrives results in the following:
Ii + Ir = Ir = current into Rr
Since only one voltage can exist at the end of the line at this instant of time, the following is true:
V1 + Vr = Vr
thus,
also,
11 = V1/Zo and Ir= -Vr/Zo
with the minus sign indicating that Vr is moving toward the generator.
Combining the foregoing relationships algebraically and
solving for Vr yields a simplified expression in terms of V1, Zo and Rr.
V1 _ :!.!_ = V1 + Vr = V1 + Vr
Zo Zo
Rr
Rr Rr
V1 (...!... - ...!...) = Vr (...!... + ...!...)
Zo Rr
Rr Zo
Vr =
V1
(
Rr Rr
+-ZZoo )
=
PL V1
The term in parentheses is called the coefficient of reflection (pL). With Rr ranging between zero (shorted line) and infinity (open line), the coefficient ranges between -1 and
+ 1 respectively. The subscript L indicates that PL refers to
the coefficient at the load end of the line.
This last equation expresses the amount of voltage sent back down the line, and since
Vr = V1 + Vr
then
Vr = V1 (1 + pL)
Vr can also be determined from an expression which does not require the preliminary step of calculating PL� Manipulat-
ing (1 + pd results in
1 + PL= 1 + (Rr - Zo)/(Rr + Zo) = 2 (Rr/(Rr + Zo))
Substituting, this gives
Vr = 2 (Rr/(Rr + Zo)) V1
The foregoing has the same form as a simple voltage divider involving a generator V1 with internal impedance, Zo. driving a load Rr, except that the amplitude of Vr is doubled.
The arrow indicating the direction of Vr in Figure 3-6 correctly indicates the Vr direction of travel, but the direction of Ir flow depends on the Vr polarity. If Vr is positive, Ir flows toward the generator, opposing 11. This relationship between the polarity of Vr and the direction of Ir can be deduced by noting that if Vr is positive it is because Rr is greater than Zo. In turn, this means that the initial current Ir
3-8
is larger than the final quiescent current, dictated by V1 and RT. Hence Ir must oppose 11 to reduce the line current to the final quiescent value. Similar reasoning shows that if Vr is negative, Ir flows in the same direction as 11.
It is somewhat easier to determine the effect of Vr on line conditions by thinking of it as an independent voltage generator in series with RT. With this concept, the direction of Ir is immediately apparent; its magnitude, however, is the ratio of Vr to Zo. i.e., RT is already accounted for in the magnitude of Vr� The relationships between incident and reflected signals are represented in Figure 3-1 for both cases of mismatch between RT and Zo.
The incident wave is shown in Figure 3-1a, before it has reached the end of the line. In Figure 3-1b, a positive Vr is returning to the generator. To the left of Vr the current is still 11, flowing to the right, while to the right of Vr the net current in the line is the difference between 11 and Ir. In Figure 3-7c, the reflection coefficient is negative, producing a negative Vr. This, in turn, causes an increase in the amount of current flowing to the right behind the Vr wave.
"T1
SOURCE IMPEDANCE, MULTIPLE REFLECTIONS
)> CJ)
When a reflected voltage arrives back at the source (generator), the reflection coefficient at the source determines the response to Vr. The coefficient of reflection at the source is governed by Zo and the source resistance Rs.
-i
c
ceCenD�
::J
PS= (Rs - Zo)/(Rs + Zo)
0
If the source impedance matches the line impedance, a reflected voltage arriving at the source is not reflected back toward the load end. Voltage and current on the line are
0
c:e::nJ
stable with the following values. VT= Vi+ Vr
-CD
""'I
D>
5�
If neither source impedance nor terminating impedance matches Zo. multiple reflections occur; the voltage at each
:e:nJ
end of the line comes closer to the final steady state value
with each succeeding reflection. An example of a line mis-
matched on both ends is shown in Figure 3-8. The source is
a step function of Vee = 5.0V amplitude occurring at time
tO. The initial value of V1 starting down the line is 2.4V due to the voltage divider action of Zo and Rs. The time scale in
the photograph shows that the line delay is approximately
6 ns. Since neither end of the line is terminated in its char-
acteristic impedance, multiple reflections occur.
a. Incident Wave
vi v,,1,-
v,~t<T+
DISTANCE TL/F/9607-13
b. Reflected Wave for RT > Zo
Y1r--l------1.__lfc_------) Yr
T < t < 2T
I
TL/F/9607-14
c. Reflected Wave for RT > Zo
I FIGURE 3-7. Reflections for RT= Zo
TL/F/9607-15
3-9
"'c
;0:;
c...o..
Q)
�";C;
FAST OUTPUT
�----------------�I I I
z0 = 501l
c
0
0
v. Rr 3001l
�ec;n;
cQ)
e...n...
<(
TL/F/9607-16
FIGURE 3-8. Multiple Reflections Due to Mismatch at Load and Source
LL
Vo= Vee - 2�VsE = 3.6V
(25 - 50)!1
Ps = (25 + 50)!1 = -0.33
initially '
V1
=~�Vo=
Zo + Rs
~(3.6V)
(50 + 25)!1
=
2.4V
(300 - 50)!1
PL = (300 + 50)!1 = 0.71
V1 (1+p)~ ~.33
+2.4V t=to
4.10V
H = 20 ns/div. V = 1V/div.
TL/F /9607 -17
The amplitude and persistence of the ringing shown in Figure 3-8 become greater with increasing mismatch between the line impedance and source and load impedances. The difference in amplitude between the first two positive peaks observed at the open end is
Vr -V'r = (1 + pL)V1 - (1 + pL)V1 p2Lp2s = (1 + Pd V1 (1 - P2LP2s)
The factor (1 - p2s) is similar to the damping factor associated with lumped constant circuitry. It expresses the attenuation of successive positive or negative peaks of ringing.
LATTICE DIAGRAM
In the presence of multiple reflections, keeping track of the incremental waves on the line and the net voltage at the ends becomes a bookkeeping chore. A convenient and systematic method of indicating the conditions which combine magnitude, polarity and time utilizes a graphic construction called a lattice diagram. A lattice diagram for the line conditions of Figure 3-8 is shown in Figure 3-9.
3-10
The vertical lines symbolize discontinuity points, in this case the ends of the line. A time scale is marked off on each line in increments of 2T, starting at tO for V1 and T voltages traveling between the ends of the line; solid lines are used for positive voltages and dashed lines for transmission mul-
tipliers p and (1 + p) at each vertical line, and to tabulate
the incremental and net voltages in columns alongside the vertical lines. Both the lattice diagram and the waveform photograph show that V1 and Vr asymptomatically approach 3.4V, as they must with a 3.4V source driving a lightly loaded line.
SHORTED LINE
The open-ended line in Figure 3-8 has a reflection coefficient of 0.71 and the successive reflections tend toward the steady state conditions of zero line current and a line voltage equal to the source voltage. In contrast, a shorted line has a reflection coefficient of -1 and successive reflections must cause the line conditions to approach the steady state conditions of zero voltage and a line current determined by the source voltage and resistance.
Shorted line conditions are shown in Figure 3-10a with the reflection coefficient at the source end of the line also negative. A negative coefficient at both ends of the line means that any voltage approaching either end of the line is reflected in the opposite polarity. Figure 3-10b shows the response to an input step-function with a duration much longer than the line delay. The initial voltage starting down the line is about 2.4V, which is inverted at the shorted end and returned toward the source as - 2.4V. Arriving back at the
source end of the line, this voltage is multiplied by (1 + pg),
causing a -1.61V net change in V1. Concurrently, a reflect-
ed voltage of +o.aov (-2.4V times ps of -0.33) starts
back toward the shorted end of the line. The voltage at V1 is reduced by 50% with each successive round trip of reflections, thus leading to the final condition of zero volts on the line.
,,
When the duration of the input pulse is less than the delay
e:tn>
of the line, the reflections observed at the source end of the -t
line constitute a train of negative pulses, as shown in Figure
c
3-10c. The amplitude decreases by 50% with each successive occurrence as it did in Figure 3-1Ob.
cCeenD�
::I
SERIES TERMINATION
0
Driving an open-ended line through a source resistance equal to the line impedance is called series termination. It is particularly useful when transmitting signals which originate on a PC board and travel through the back-plane to another board, with the attendant discontinuities, since reflections
0
-:ae.C:.nD=I,
Ill
c;�
coming back to the source are absorbed and ringing thereby controlled. The amplitude of the initial signal sent down the
:e:nI
line is only half of the generator voltage, while the voltage at
the open end of the line is doubled to full amplitude
(1 + PL = 2). The reflected voltage arriving back at the
source raises V1 to the full amplitude of the generator signal. Since the reflection coefficient at the source is zero, no
further changes occur and the line voltage is equal to the
generator voltage. Because the initial signal on the line is
only half the normal signal swing, the loads must be con-
nected at or near the end of the line to avoid receiving a 2-
step input signal.
A TIL output driving a series-terminated line is severely limited in its fanout capabilities due to the JR drop associated with the collective l1L drops of the inputs being driven. For most TIL families other than FAST it should not be considered since either the input currents are so high (TIL, S, H) or the input threshold is very low (LS). In either case the noise margins are severely degraded to the point where the circuit becomes unusable. In FAST, however, the l1L of 0.6 mA, if sunk through a resistor of 25.fl used a series terminating resistor, will reduce the low level noise margin 15 mV for each standard FAST input driven.
3-11
tcn:
;.0c.a.
a. Reflection Coefficients for Shorted Line FAST OUTPUT
CD
"�uC;
c:
z0 =so.n
0
0
c:
Ry=D
�uC;')
Vy=O
cCD
I-
C/) <(
LL
PS= -0.33
PL= -1
TL/F/9607-19
b. Input Pulse Duration ~ Line Delay
c. Input Pulse Duration < Line Delay
V = 1V/div. H = 20 ns/div.
TL/F/9607-21
FIGURE 3-10. Reflections of Long and Short Pulses on a Shorted Line
TL/F/9607-20
TABLE Ill-IV. Relative Dielectric Constants of Various Materials
Material
Er
Air
1.0
Polyethylene Foam
1.6
Cellular Polyethylene
1.8
Teflon
2.1
Polyethylene
2.3
Polystyrene
2.5
Nylon
3.0
Silicon Rubber
3.1
Polyvinylchloride (PVC)
3.5
Epoxy Resin
3.6
Delrin
3.7
Epoxy Glass
4.7
Mylar
5.0
Polyurethane
7.0
All the above information on impedance and propagation delays are for the circuit interconnect only. The actual impedance and propagation delays will differ from this by the loading effects of gate input and output capacitances, and by any connectors that may be in line. The effective impedance and propagation delay can be determined from the following formula:
Zo
Zo' = ~1 + (~~) n
0 tpo = JLoCo :. tpo' = tpo~,...1-+~(-~..,L)~
where CL is the total of all additional loading.
The results of these formulas will frequently give effective impedances of less than half Zo, and interconnect propagation delays greater than the driving device propagation delays, thus becoming the predominant delay.
3-12
A
_[
l
FIGURE 3-11. Unterminated
TL/F/9607-22
The maximum length for an unterminated line can be determined by
lmax = Tr/2tpd
and for FAST, tr = 3 ns, so lmax = 10 inches for trace on
GIO epoxy glass PC.
The voltage wave propagated down the transmission line (V step) is the full output drive of the device into Zo'. Reflections will not be a problem if I ~ lmax� Lines longer than lmax will be subject to ringing and reflections and will drive the inputs and outputs below ground.
Zo
l
TL/F/9607-23
FIGURE 3-12. Series-Terminated
a. RT to Vee
RT= Zo'
'"T1
Series termination has limited use in TIL interconnect
)> CJ)
schemes due to the voltage drop across RTs in the LOW -i
state, reducing noise margins at the receiver. Series termi-
c
nation is the ideal termination for highly capacitive memory
(1) (/)
arrays whose DC loadings are minimal. RTs values of 1o.n <C"
to 50.0. are normally found in these applications.
::J
(")
Four possibilities for parallel termination exist:
0
A. Zo' to Vee. This will consume current from Vee when
output is LOW;
B. Zo' to GND. This will consume current from Vee when
output is HIGH;
::J
c:(/)
.a..(1)
5�
C. Thevenin equivalent termination. This will consume half
::J
the current of A and 8 from the output stage, but will
(/)
have reduced noise margins, and consume current from
Vee with outputs HIGH or LOW. If used on a
TRI-STATE� bus, this will set the quiescent line voltage
to half.
D. AC Termination. An RC termination to GND, C = 3tr/Zo.
This consumes no DC current with outputs in either state. If this is used on a TRI-STATE bus, then the quiescent voltage
on the line can be established at Vee or GND by a high
value pull up (down) resistor to the appropriate supply rail.
b. RTtoGND RT= Zo'
Zo'
Z0 '
TL/F/9607-24
c. Thevenin Termination RT= 2Zo'
TL/F/9607-25
d. AC Termination to GND
Rr + Xer = Zo'
A
Z0 '
z .
rlf
TL/F/9607-26
FIGURE 3-13. Parallel Terminated
TL/F/9607-27
3-13
Cl)
S DECOUPLING
;.c.;a.
CD
"�uC; c
0
0 c
�uC;'>
cCD
1cn-
a)so.n Vee
<(
Impedance
LL
Vee
~Board
b) 100.n Vee Impedance
~Board
c)6B.n Vee Impedance
~Board
d) 100.n Vee Impedance
.032" Epoxy Glass
e) 2.n Vee Impedance
FIGURE 3-14. Typical Dynamic Impedance of Unbypassed Vee Runs
TL/F/9607-28
This diagram shows several schemes for power and ground distribution on logic boards. Figure 3-14 is a cross-section,
with a, b, and c showing a 0.1 inch wide Vee bus and
ground on the opposite side. Figure 3-14d shows side-by-
side Vee and ground strips, each 0.04 inch wide. Figure
3-14e shows a four layer board with embedded power and ground planes.
In Figure 3-14a, the dynamic impedance of Vee with respect to ground is 50!1, even though the Vee trace width is gener-
ous and there is a complete ground plane. In Figure 3-14b,
the ground plane stops just below the edge of the Vee bus
and the dynamic impedance doubles to 100!1. In Figure
3-14c, the ground bus is also 0.1 inch wide and runs along
under the Vee bus and exhibits a dynamic impedance of
about 68!1. In Figure 3-14d, the trace widths and spacing are such that the traces can run under a DIP, between two
rows of pins. The impedance of the power and ground planes in Figure 3-14e is typically less than 2!1.
These typical dynamic impedances point out why a sudden
current demand due to an IC output switching can cause a
momentary reduction in Vee. unless a bypass capacitor is
located near the 1c:
��
Decoupling capacitors should be used on every PC card, at least one for every five to ten standard TTL packages, one for every five 'LS and 'S packages, one for every three
FAST packages, and one for every one-shot (monostable), line driver and line receiver package. They should be good
quality rt capacitors of 0.01 �F to 0.1 �F with short leads. It is particularly important to place good rt capacitors near se-
quential (bistable) devices. In addition, a larger capacitor (preferably a tantalum capacitor) of 2.0 �F to 20 �F should be included on each card.
Buffer Output Sees Net 500. Load. 500. Load Line on loH-VoH Characteristic Shows LOW-to-HIGH Step of Approx. 2.5V.
r2.7V
Vou1 ___}:
0.2V
; :
-+i : - '21113ns
_ J ~
: , ' ' ' SOmA
0
Worst-Case Octal Drain = 8 x 50 mA = 0.4 Amp.
FIGURE 3-15. lee Drain Due to Line Driving
TL/F/9607-29
3-14
This diagram illustrates the sudden demand for current from
Vee when a buffer output forces a LOW-to-HIGH transition
into the midpoint of a data bus. The sketch shows a wire-
over-ground transmission line, but it could also be a twisted
pair, flat cable or PC interconnect.
The buffer output effectively sees two 1OO!l lines in parallel
and thus a 50!1 load. For this value of load impedance, the
buffer output will force an initial LOW-to-HIGH transition
from 0.2V to 2.7V in about 3 ns. This net charge of 2.5V into
a 50 load causes an output-HIGH current change of 50 mA.
If all eight outputs of an octal buffer switch simultaneously,
in this application the current demand on Vee would be
0.4A. Clearly, a nearby Vee bypass capacitor is needed to
accommodate this demand.
Q =CV
Vee--J._. .--1.---c-J_t----if Zee
...J Vee Bus~
I= C/lV//lt c = llltnv
:.~ x 10-�
.,i~. "JJJ~
TL/F/9607-30
FIGURE 3-16. Vee Bypass Capacitor for Octal Driver
Specify Vee Droop = 0.1V max. c = 0.4 x 3 x 10 - 9 = 12 x 10-9 = 0.012 �F
0.1
Select c 8 ;;, 0.02 �F A Vee bus with bypass capacitors connected periodically along its length is shown above. Also shown is a current source representing the current demand of the buffer in the preceding application.
The equations illustrate an approximation method of estimating the size of a bypass capacitor based on the current demand, the drop in Vee that can be tolerated and the length of time that the capacitor must supply the charge. While the demand is known, the other two parameters must be chosen. A Vee droop of 0.1V will not cause any appreciable change in performance, while a time duration of 3 ns is long enough for other nearby bypass capacitors to help supply charge. If the current demand continues over a long period of time, charge must be supplied by a very large capacitor on the board. This is the reason for the recommendation that a large capacitor be located where Vee comes onto a board. If the buffers are also located near the connector end of the board, the large capacitor helps supply charge sooner.
DESIGN GUIDELINES
~
(/)
Ground
-i
A good ground system is essential for a PC card containing a large number of packages. The ground can either be a
c
ce�(e1n)
good ground bus, or better, a ground plane which, incorpo-
~
rated with the Vee supply, forms a transmission line power
(')
system. Power transmission systems, which can be at-
0
tached to a PC card to give an excellent power system without the cost of a multilayer PC card, are commercially avail-
ce~n:
able. Ground loops on or off PC cards are to be avoided unless they approximate a ground plane. With the advent of FAST, with considerably faster edge
-.(.1..)
ll>
5�
rates and switching times, proper grounding practice has
e~n
become of primary concern in printed circuit layout. Poor
circuit grounding layout techniques may result in crosstalk
and slowed switching rates. This reduces overall circuit per-
formance and may necessitate costly redesign. Also when
FAST chips are substituted for standard TIL-designed print-
ed circuit boards, faster edge rates can cause noise prob-
lems. The source of these problems can be sorted into
three categories:
1. Vee droop due to faster load capacitance charging;
2. Coupling via ground paths adjacent to both signal sources and loads; and
3. Crosstalk caused by parallel signal paths.
Vee droop can be remedied with better or more bypassing to ground. The rule here is to place 0.01 �F capacitors from Vee to ground for every three FAST circuits used, as near the IC as possible. The other two problems are not as easily corrected, because PC boards, may already be manufactured and utilized. In this case, simply replacing TIL circuits with FAST compatible circuits is not always as easy as it may seem, especially on two-sided boards. In this situation IC placement is critical at high speeds. Also when designing high density circuit layout, a ground-plane layer is imperative to provide both a sufficiently low inductance current return path and to provide electromagnetic and electrostatic shielding thus preventing noise problem 2 and reducing, by a large degree, noise problem 3.
Two-Sided PC Board Layout
When considering the two-sided PC board, more than one ground trace is often found in a parallel or non-parallel configuration. For this illustration parallel traces tied together at one end are shown. This arrangement is referred to as a ground comb. The ground comb is placed on one side of the PC board while the signal traces are on the other side, thus the two-sided circuit board.
GROUND COMB (BELOW)
FIGURE 3-17 3-15
TL/F/9607-31
cU:> ; 0
.m...
Q)
"�uC;
c:
0 0
c:
�uC;)
cQ)
1cn-
<( LL.
FIGURE3-1B
TL/F/9607-32
Figure 3-18 illustrates how noise is generated even though there is no apparent means of crosstalk between the circuits. If package A has an output which drives package D input and package B output drives package C input, there is no apparent path for crosstalk since mutual signal traces
are remotely located. What is significant, and must be emphasized here, is that circuit packages A and B accept their ground link from the same trace. Hence, circuit A may well couple noise to circuit B via the common or shared portion of the trace. This is especially true at high switching speeds.
Ground Strip---.:"\:----------....._
Inductance
_,
'
~
FIGURE 3-19. Ground Trace Coupling
'-----Strip #3
TL/F/9607-33
3-16
Ground trace noise coupling is illustrated by a model circuit in Figure 3-19. With the ground comb configuration, the ground strips may be shown to contain distributed inductance, as is indeed the case. Referring to Figure 3-19 we can see that if we switch gate A from HIGH to LOW, the current for the transition is drawn from ground strip number two. Current flows in the direction indicated by the arrow to the common tie point. It can be seen that gate B shares ground strip number two with gate A from the point where gate B is grounded back to the common tie point. This length is represented by L1. When A switches states there is a current transient which occurs on the ground strip in the positive direction. This current spike is caused by the ground strip inductance and it is "felt" by gate B. If gate B is in a LOW state (Vod the spike will appear on the output since gate B's Vol level is with reference to ground. Thus if gate B's ground reference rises momentarily Vol will also rise. Consequently, if gate B is output to another gate (C in the illustration) problems may arise.
Supply Voltage and Temperature
The normal supply voltage Vee for all TTL circuits is + 5.0V.
Commercial grade parts are guaranteed to perform with a
� 10% supply tolerance ( �500 mV) over an ambient tem-
perature range of 0�C. Military grade parts are guaranteed to
perform with � 10% supply tolerance ( �500 mV) over an ambient temperature range of - 55�C to + 125�C.
The actual junction temperature can be calculated by multiplying the power dissipation of the device with the thermal resistance of the package and adding it to the measured ambient temperature TA or package (case) temperature TC� For example, a device in ceramic DIP (OJA 100�C/W) dissi-
pates typically 145 mW. At + 55�C ambient temperature, the
junction temperature is
TJ = (0.145 X 100) + 55�C
Designers should note that localized temperatures can rise well above the general ambient in a system enclosure. On a large PC board mounted in a horizontal plane, for example, the local temperature surrounding an IC in the middle of the board can be quite high due to the heating effect of the
a.
"11
surrounding packages and the very poor natural convection.
)> CJ)
Low velocity forced air cooling is usually sufficient to allevi-
-f
ate such localized static air conditions.
c
Interfacing
ce�(e1n)
All TTL circuits are compatible, and any TTL output can
:::J
drive a certain number of TTL inputs. There are only subtle
0
differences in the worst-case noise immunity when low power, standard and Schottky TTL circuits are intermixed. Open-collector outputs, however, require a pull-up resistor to drive TTL inputs reliably.
While TTL is the dominating logic family, and many systems
0
a:e::nJ .c..:(1)
a�
use TTL exclusively, there are cases where different semiconductor technologies are used in one system, either to
e::n:J
improve the performance or to lower the cost, size and pow-
er dissipation. The following explains how TTL circuits can
interface with ECL, CMOS and discrete transistors.
Interfacing TTL and ECL-Mixing ECL and TTL logic families offers the design engineer a new level of freedom and opens the entire VHF frequency spectrum to the advantages of digital measurement, control and logic operation.
The main advantages gained with ECL are high speed, flexibility, design versatility and transmission line compatibility. But application and interfacing cost problems have traditionally discouraged the use of ECL in many areas, particularly in low cost, less sophisticated systems.
The most practical interfacing method for smaller systems
involves using a common supply of + 5.0V to + 5.2V. Care
must be exercised with both logic families when using this technique to assure proper bypassing of the power supply to prevent any coupling of noise between circuit families. When larger systems are operated on a common supply, separate power buses to each logic family help prevent problems. Otherwise, good high frequency bypassing techniques are usually sufficient.
ECL devices have high input impedance with input pulldown resistors(> 20 k.O.) to the negative supply. In the TTL to ECL interface circuits in Figure 3-20, it is assumed that the ECL devices have high input impedance.
b. + 5V
470n
TL/F/9607-34
1son
FIGURE 3-20. TTL-to-ECL Conversion
TL/F/9607-35
El
3-17
"c '
...:0c;:a;
G>
�"uC;
All circuits described operate with � 5% ECL and � 10%
TTL supply variations, except those with ECL and TTL on a
common supply. In those cases, the supply can be � 10% with ECL. All resistors are %W, � 5% composition type.
c
TTL to ECL conversion is easily accomplished with resis-
0
tors, which simultaneously attenuate the TTL signal swing,
0 c
�Cu;)
shift the signal levels, and provide low impedance for damping and immunity to stray noise pick-up. The resistors should be located as near as possible to the ECL circuit for
cG>
optimum effect. The circuits in Figure 3-20 assume an un-
etn-
loaded TTL gate as the standard TTL source. ECL input impedance is predominantly capacitive (approximately
<(
3 pF); the net RC time constant of this capacitance with the
LL
indicated resistors assures a net propagation delay gov-
erned primarily by the TTL signal.
a. Common Power Supply +5.2V 22.n
2k
1k
TL/F/9607-36
b. Separate Power Supplies +SV
When interfacing between high voltage swing TTL logic and low voltage swing ECL logic, the more difficult conversion is from ECL to TTL. This requires a voltage amplifier to build up the O.BV logic swing to a minimum of 2.5V. The circuits shown in Figure 3-21 may be used to interface from ECL to TTL.
The higher speed converters usually have the lowest fanout: only one or two TTL gates. This fanout can be increased simply by adding a TTL buffer gate to the output of the converter. Another option, where ultimate speed is required, is to use additional logic converters.
Interfacing FAST and CMOS-Due to their wide operating voltage range, CMOS devices will function outside of the
standard �5V � 10% supply levels. For our purposes, only
the case where both the FAST and CMOS devices are connected to the same voltage source will be considered.
FAST outputs can sink at least 20 mA in the LOW state. This is more than adequate to drive CMOS inputs to a valid LOW level. Due to their output designs, though, FAST outputs are unable to pull CMOS inputs to above approximately 4.0V. If the CMOS device does not have TTL-compatible input levels, the FAST output should be pulled with a resistor to Vee. The value of this resistor will vary according to the system. Factors that affect the selection of the value are: edge rate- the smaller the resistor, the faster the edge rate; fanout-the smaller the resistor, the greater the fanout; and noise margins-the smaller the resistor, the greater the output HIGH noise margin and the smaller the output LOW noise margin. FAST outputs can directly drive TTL-compatible CMOS inputs, such as the inputs on ACT or HCT devices, without pull up registers.
Most CMOS outputs are capable of directly driving FAST inputs. Be aware, though, that TTL inputs have higher loading specifications than CMOS inputs. Care must be taken to insure that the CMOS outputs are not overloaded by the FAST input loading.
TTL Driving Transistors-Although high voltage, high current ICs are available, it is sometimes necessary to control greater currents or voltages than integrated circuits are capable of handling. When this condition arises, a discrete transistor with sufficient capacity can be driven from a TTL output. Discrete transistors are also used to shift voltages from TTL levels to logic levels for which a standard interface driver is not available.
The two circuits of Figure 3-22 show how TTL can drive npn transistors. The first circuit is the most efficient but requires an open-collector TTL output. The other circuit limits the output current from the TTL totem pole output through a series resistor.
-5.2V
TL/F/9607-37
FIGURE 3�21. ECL-to-TTL Conversion
3-18
~
fJ)
-I
Yee
c
eCnl>
360.ll
(Q' ::J
C')
Open Collector TTL
lb> IOmA
0
TL/F/9607-38
.-..:ae:nJ:
Cl>
I�
c;�
FIGURE 3�22. TTL Driving npn Transistors
:e:nJ
-Vx
TL/F/9607-39
FIGURE 3�23. pnp Transistor Shifting TTL Output
Shifting a TTL Output to Negative Levels-The circuit of Figure 3-23 uses a pnp transistor to shift the TTL output to a negative level. When the TTL output is HIGH, the transistor is cut off and the output voltage is -Vx. When the TTL output is LOW, the transistor conducts and the output voltage is
VouT = -Vx + R1/R2 (Vee - 2.0V)
if the transistor is not saturated, or slightly positive if the transistor is allowed to saturate.
High Voltage Drivers-A TTL output can be used to drive high voltage, low current loads through the simple, non-inverting circuits shown in Figure 3-24. This can be useful for driving gas discharge displays or small relays, where the TTL output can handle the current but not the voltage. Load current should not exceed loL ( - 4 mA).
3-19
ctn
;0:;
a.
.c.u..
Q)
Vee
"�cC;;
c
0
0 c
1k
�cC;;)
cQ)
I-
C/) <( LL
To other Displays
b.
TL/F/9607-41
FIGURE 3�24. Non-Inverting High Voltage Drivers
Vee
10 k.n
10kfi 51.6k.n 5.6k.n
TL/F/9607-42
TTL
TL/F/9607-40
Transistors Driving TTL-It is sometimes difficult to drive the relatively low impedance and narrow voltage range of TTL inputs directly from external sources, particularly in a rough, electrically noisy environment. The circuits shown in Figure 3-25 can handle input signal swings in excess� of
� 1OOV without harming the circuits. The second circuit has
input RC filter that suppresses noise. Unambiguous TIL voltage levels are generated by the positive feedback (Schmitt trigger) connection.
OPEN COLLECTOR OUTPUTS
A number of available circuits have no pull-up circuit on the outputs. Open collector outputs are used for interfacing or for wired-OR (actually wired-AND) functions. The latter is achieved by connecting open collector outputs together and adding an external pull-up resistor.
The value of the pull-up resistor is determined by considering the fanout of the OR tie and the number of devices in the OR tie. The pull-up resistor value is chosen from a range between maximum value (established to maintain the required VoH with all the OR-tied outputs HIGH) and a minimum value (established so that the OR tie fanout is not exceeded when only one output is LOW).
TL/F/9607-43
FIGURE 3-25. Transistors Driving TTL
3-20
MINIMUM AND MAXIMUM PULL-UP RESISTOR VALUES
A
- ( Vee(MAX) - VoL )
X(MIN) - loL - N2(LOW) � 1.6 mA
A
-(
Vee(MIN) - VoH
)
X(MAX) - N1IOH + N2(HIGH) � 40 �A
where:
Rx = External pull-up resistor
N1 = Number of wired-OR outputs
N2 = Number of input unit loads being driven
loH = leex = Output HIGH leakage current
loL = LOW level fanout current of driving element
VoL = Output LOW voltage level (0.5V)
VoH = Output HIGH voltage level (2.5V)
Vee = Power Supply Voltage
Example: four 'F524 gate outputs driving four other gates or MSI inputs.
R
x (MIN) =
( 5.5V 8.0 mA -
0.5V
5.0V )
2.4 mA = 5.6 mA
= 8930
R
X (MAX) =
(
4.5V - 2.5V
2.0V )
4 � 250 �A + 2 � 40 �A = 1.08 mA
= 1852!1
where: N1 = 4
N2(HIGH) = 4 � 0.5 U.L. = 2 U.L. N2(LOW) = 4 � 0375 U.L. = 1.5 U.L.
loH = 250 �A loL = 8.0 mA VoL = 0.5V VoH = 2.5V Any values of pull-up resistor between 893!1 and 1852!1 can be used. The lower values yield the fastest speeds while the higher values yield the lowest power dissipation.
INCREASING FANOUT
~
Cf)
To increase fanout, inputs and outputs of gates on the same package may be paralleled to those in a single package to
-I
c
(1)
avoid large transient supply currents due to different switching times of the gates. This is not detrimental to the devices, but could cause logic problems if the gates are being used as clock drivers.
cUeJ �
::s 0 :0:s
UNUSED INPUTS
UcJ:
Theoretically, an unconnected input assumes the HIGH logic level, but practically speaking it is in an undefined logic
a(1)
state because it tends to act as an antenna for noise. Only a
c;�
few hundred millivolts of noise may cause the unconnected
::s
input to go to the logic LOW state. On devices with memory
UJ
(flip-flops, latches, registers, counters), it is particularly im-
portant to terminate unused inputs (MR, PE, PL, CP) proper-
ly since a noise spike on these inputs might change the
contents of the memory. It is a poor design practice to leave
unused inputs floating.
If the logic function calls for a LOW input, such as in NOR or OR gates, the input can be connected directly to ground. For a permanent HIGH signal, unused inputs can be tied directly to Vee- An unused input may also be tied to a used input having the same logic function, such as NANO and AND gates, provided that the driver can handle the added l1H� This practice is not recommended for diode-type inputs in a noisy environment, since each diode represents a small capacitor and two or more in parallel can act as an entry port for negative spikes superimposed on a HIGH level and cause momentary turn-off of 02.
3-21
Section 4 Advanced Schottky TTL Datasheets
Section 4 Contents
54F/74FOO Quad 2-lnput NANO Gate................................................. 54F/74F02 Quad 2-lnput NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54F/74F04 Hex Inverter............................................................. 54F/74F08Quad2-lnputANDGate .................................................. 54F/7 4F10 Triple 3-lnput NANO Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54F/74F11 Triple 3-lnput AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54F/74F13 Dual 4-lnput NANO Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54F/74F14 Hex Inverter Schmitt Trigger. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54F/74F20 Dual 4-lnput NANO Gate.................................................. 54F/74F27 Triple 3-lnput NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54F/74F30 8-lnput NANO Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54F/74F32 Quad 2-lnput OR Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54F/74F37 Quad 2-lnput NANO Buffer................................................ 54F/74F38 Quad 2-lnput NANO Buffer (Open Collector). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54F/74F40 Dual 4-lnput NANO Buffer................................................. 54F/74F51 2-2-2-3 AND-OR-Invert Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54F/74F64 4-2-3-2-lnput AND-OR-Invert Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54F/74F74 Dual D-Type Positive Edge-Triggered Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54F/74F86 Quad 2-lnput Exclusive-OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
54F/74F109 Dual JK Positive Edge-Triggered Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
54F/74F112 Dual JK Negative Edge-Triggered Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54F/74F113 Dual JK Negative Edge-Triggered Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54F/74F114 Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears . . . 54F/74F125 Quad Buffer (TRI-STATE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54F/74F132 Quad 2-lnput NANO Schmitt Trigger. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54F/74F1381-of-8 Decoder/Demultiplexer............................................ 54F/74F139 Dual 1-of-4 Decoder/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54F/74F148 8-Line to 3-Line Priority Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54F/74F151A 8-lnput Multiplexer..................................................... 54F/74F153 Dual 4-lnput Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54F/7 4F157A Quad 2-lnput Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54F/74F158A Quad 2-lnput Multiplexer (Inverted) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54F/74F160A Synchronous Presettable BCD Decade Counter (Asynchronous Reset) . . . . . . . 54F/74F162A Synchronous Presettable BCD Decade Counter (Synchronous Reset) . . . . . . . . 54F /74F161 A Synchronous Presettable Binary Counter (Asynchronous Reset). . . . . . . . . . . . . 54F/74F163A Synchronous Presettable Binary Counter (Synchronous Reset) . . . . . . . . . . . . . . 54F/74F164A Serial-In, Parallel-Out Shift Register...................................... 54F /7 4F168 4-Stage Synchronous Bidirectional Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54F/74F169 4-Stage Synchronous Bidirectional Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54F/74F174 Hex D Flip-Flop with Master Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54F/74F175 Quad D Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54F/74F181 4-Bit Arithmetic Logic Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54F/74F182 Carry Lookahead Generator.............................................. 54F/74F189 64-Bit Random Access Memory with TRI-STATE Outputs . . . . . . . . . . . . . . . . . . . . 54F/74F190 Up/Down Decade Counter with Preset and Ripple Clock. . . . . . . . . . . . . . . . . . . . . 54F/74F191 Up/Down Binary Counter with Preset and Ripple Clock . . . . . . . . . . . . . . . . . . . . . . 54F/74F192 Up/Down Decade Counter with Separate Up/Down Clocks . . . . . . . . . . . . . . . . . . 54F/74F193 Up/Down Binary Counter with Separate Up/Down Clocks. . . . . . . . . . . . . . . . . . . .
4-6 4-9 4-12 4-15 4-18 4-21 4-24 4-27 4-30 4-33 4-36 4-39 4-42 4-45 4-48 4-51 4-54 4-57 4-61 4-64 4-68 4-72 4-76 4-80 4-83 4-86 4-90 4-94 4-98 4-102 4-106 4-110 4-114 4-114 4-121 4-121 4-127 4-131 4-131 4-137 4-141 4-145 4-151 4-156 4-160 4-165 4-170 4-175
4-2
Section 4 Contents (Continued)
54F/74F194 4-Bit Bidirectional Universal Shift Register ................................ . 54F/74F219 64-Bit Random Access Memory with TRI-STATE Outputs ................... . 54F/74F240 Octal Buffer/Line Driver with TRI-STATE Outputs (Inverting) ................ . 54F/74F241 Octal Buffer/Line Driver with TRI-STATE Outputs .......................... . 54F/74F244 Octal Buffer/Line Driver with TRI-STATE Outputs .......................... . 54F/74F243 Quad Bus Transceiver with TRI-STATE Outputs ........................... . 54F/74F245 Octal Bidirectional Transceiver with TRI-STATE Outputs .................... . 54F/74F251A 8-lnput Multiplexer with TRI-STATE Outputs ............................. . 54F/74F253 Dual 4-Bit Multiplexer with TRI-STATE Outputs ............................ . 54F/74F257A Quad 2-lnput Multiplexer with TRI-STATE Outputs ........................ . 54F/74F258A Quad 2-lnput Multiplexer with TRI-STATE Outputs (Inverting) .............. . 54F/74F269 8-Bit Bidirectional Binary Counter ........................................ . 54F/74F273 Octal D Flip-Flop ...................................................... . 54F/74F280 9-Bit Parity Generator/Checker .......................................... . 54F/74F283 4-Bit Binary Full Adder with Fast Carry ................................... .. 54F/74F299 Octal Universal Shift/Storage Register with Common Parallel 1/0 Pins ........ . 54F/74F322 Octal Serial/Parallel Register with Sign Extend ............................ . 54F/74F323 Octal Universal Shift/Storage Register with Synchronous Reset and Common
1/0 Pins ........................................................................ . 54F/74F350 4-Bit Shifter with TRI-STATE Outputs ..................................... . 54F/74F352 Dual 4-lnput Multiplexer ................................................ . 54F/74F353 Dual 4-lnput Multiplexer with TRI-STATE Outputs .......................... . 54F/74F365 Hex Buffer/Driver with TRI-STATE Outputs ............................... . 54F/74F366 Hex Inverter/Buffer with TRI-STATE Outputs .............................. . 54F/74F368 Hex Inverter/Buffer with TRI-STATE Outputs .............................. . 54F/74F373 Octal Transparent Latch with TRI-STATE Outputs ......................... . 54F/74F374 Octal D-Type Flip-Flop with TRI-STATE Outputs ........................... . 54F/74F377 Octal D-Type Flip-Flop with Clock Enable ................................. . 54F/74F378 Parallel D Register with Enable .......................................... . 54F/74F379 Quad Parallel Register with Enable ....................................... . 54F/74F381 4-Bit Arithmetic Logic Unit .............................................. . 54F/74F382 4-Bit Arithmetic Logic Unit ............................................. .. 54F/74F384 8-Bit Serial/Parallel Twos' Complement Multiplier .......................... . 54F/74F385 Quad Serial Adder/Subtracter ........................................... . 54F/74F398 Quad 2-Port Register ................................................... . 54F/74F399 Quad 2-Port Register ................................................... . 54F/74F401 Cyclic Redundancy Check Generator/Checker ............................ . 54F/74F402 Serial Data Polynomial Generator/Checker ............................... . 54F/74F403A 16 x 4 First-In First-Out Buffer Memory .................................. . 54F/74F407 Data Access Register .................................................. . 54F/74F410 Register Stack-16 x 4 RAM TRI-STATE Output Register ................... . 54F/74F412 Multi-Mode Buffered 8-Bit Latch with TRI-STATE Outputs ................... . 54F/74F413 64 x 4 First-In First-Out Buffer Memory with Parallel 1/0 ..................... . 54F/74F420 Paralleled Check Bit/Syndrome Bit Generator ............................. . 54F/74F432 Multi-Mode Buffered 8-Bit Latch with TRI-STATE Outputs ................... . 54F/74F433 64 x 4 First-In First-Out Buffer Memory ................................... . 54F/74F521 8-Bit Identity Comparator ............................................... . 54F/74F524 8-Bit Registered Comparator ............................................ . 54F/74F525 16-Bit Programmable Counter ........................................... . 54F/74F533 Octal Transparent Latch with TRI-STATE Outputs ......................... . 54F/74F534 Octal D Flip-Flop with TRI-STATE Outputs ................................ . 54F/74F5371-of-10 Decoder with TRI-STATE Outputs ................................ .
4-180 4-184 4-188 4-188 4-188 4-192 4-195 4-199 4-203 4-207 4-211 4-215 4-219 4-223 4-227 4-232 4-237
4-242 4-247 4-253 4-257 4-261 4-264 4-264 4-268 4-272 4-276 4-280 4-284 4-288 4-294 4-300 4-306 4-311 4-311 4-316 4-321 4-329 4-346 4-353 4-357 4-362 4-366 4-371 4-377 4-391 4-395 4-402 4-409 4-413 4-417
4-3
m
Section 4 Contents (Continued)
54F/74F538 1-of-8 Decoder with TRI-STATE Outputs................................... 54F/74F539 Dual 1-of-4 Decoder with TRI-STATE Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54F/74F540 Octal Buffer/Line Driver with TRI-STATE Outputs (Inverting) . . . . . . . . . . . . . . . . . 54F/74F541 Octal Buffer/Line Driver with TRI-STATE Outputs........................... 54F/74F543 Octal Registered Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54F/74F544 Octal Registered Transceiver (Inverting in Both Directions)................... 54F/74F545 Octal Bidirectional Transceiver with TRI-STATE Outputs . . . . . . . . . . . . . . . . . . . . . 54F/74F547 Octal Decoder/Demultiplexer with Address Latches and Acknowledge . . . . . . . . 54F/74F548 Octal Decoder/Demultiplexer with Acknowledge............................ 54F/74F550 Octal Registered Transceiver with Status Flags . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 54F/74F551 Octal Registered Transceiver with Status Flags............................. 54F/74F552 Octal Registered Transceiver with Parity and Flags.......................... 54F /74F563 Octal D-Type Latch with TRI-STATE Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54F/74F564 Octal D-Type Flip-Flop with TRI-STATE Outputs............................ 54F/74F568 4-Bit Bidirectional Decade Counter with TRI-STATE Outputs . . . . . . . . . . . . . . . . . 54F/74F569 4-Bit Bidirectional Binary Counter with TRI-STATE Outputs . . . . . . . . . . . . . . . . . . . 54F/74F573 Octal D-Type Latch with TRI-STATE Outputs............................... 54F/74F574 Octal D-Type Flip-Flop with TRI-STATE Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54F/74F579 8-Bit Bidirectional Binary Counter with TRI-STATE Outputs................... 54F/74F582 4-Bit BCD Arithmetic Logic Unit........................................... 54F/74F583 4-Bit BCD Adder........................................................ 54F/74F588 Octal Bidirectional Transceiver with IEEE-488 Termination Resistors and
TRI-STATE Inputs/Outputs........................................................ 54F/74F620 Inverting Octal Bus Transceiver with TRI-STATE Outputs . . . . . . . . . . . . . . . . . . . . 54F/74F623 Inverting Octal Bus Transceiver with TRI-STATE Outputs . . . . . . . . . . . . . . . . . . . . 54F/74F632 32-Bit Parallel Error Detection and Correction Circuit . . . . . . . . . . . . . . . . . . . . . . . . 54F/74F640 Octal Bus Transceiver with TRI-STATE Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54F/74F643 Octal Bus Transceiver with TRI-STATE Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54F/74F645 Octal Bus Transceiver with TRI-STATE Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54F/74F646 Octal Transceiver/Register with TRI-STATE Outputs ................... ;.... 54F/74F648 Octal Transceiver/Register with TRI-STATE Outputs........................ 54F/74F651 Octal Transceiver/Register with TRI-STATE Outputs (Inverting) . . . . . . . . . . . . . . 54F/74F652 Octal Transceiver/Register with TRI-STATE Outputs........................ 54F/74F657 Octal Bidirectional Transceiver with 8-Bit Parity Generator/Checker and
TRI-STATE Outputs ......................................................... ; . . . . . 54F/74F673A 16-Bit Serial-In, Serial/Parallel-Out Shift Register (Common Serial 1/0 Pin) . . . 54F/74F675A 16-Bit Serial-In, Serial/Parallel-Out Shift Register.......................... 54F/74F676 16-Bit Serial/Parallel-In, Serial-Out Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 54F /74F779 8-Bit Bidirectional Binary Counter with TRI-STATE Outputs . . . . . . . . . . . . . . . . . . . 54F/74F784 8-Bit Serial/Parallel Multiplier with Adder/Subtracter . . . . . . . . . . . . . . . . . . . . . . . . 54F/74F794 8-Bit Register with Readback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54F/74F821 10-Bit D-Type Flip-Flop.................................................. 54F/74F823 9-Bit D-Type Flip-Flop................................................... 54F/74F825 8-Bit D-Type Flip-Flop .............................................. :.... 54F/74F827 10-Bit Buffer/Line Driver................................................. 54F/74F828 10-Bit Buffer/Line Driver................................................. 54F/74F841 10-Bit Transparent Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54F/74F843 9-Bit Transparent Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54F/74F845 8-Bit Transparent Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54F/74F899 9-Bit Latchable Transceiver with Parity Generator/Checker . . . . . . . . . . . . . . . . . . 54F/74F968 1 Megabit Dynamic RAM Controller . . .. .. . . . . . . .. . . . . . . . .. . .. . .. .. . .. . . . . . 54F/74F2241 Octal Buffer/Line Driver with 25!1 Series Resistors in the Outputs............
4-421 4-425 4-429 4-429 4-433 4-438 4-443 4-446 4-451 4-455 4-455 4-461 4-466 4-470 4-474 4-4 7 4 4-485 4-489 4-493 4-494 4-498
4-502 4-506 4-506 4-510 4-522 4-522 4-522 4-527 4-527 4-534 4-534
4-540 4-545 4-550 4-554 4-558 4-559 4-565 4-569 4-573 4-577 4-581 4-581 4-586 4-590 4-594 4-599 4-609 4-621
4-4
Section 4 Contents (Continued)
54F/74F2244 Octal Buffer/Line Driver with 25!1 Series Resistors in the Outputs............ 54F/74F2243 Quad Bus Transceiver with 250. Resistors in the Outputs . . . . . . . . . . . . . . . . . . . 54F/74F2620 Inverting Octal Bus Transceiver with 25!1 Resistors in the Outputs . . . . . . . . . . . 54F/74F2623 Inverting Octal Bus Transceiver with 25!1 Resistors in the Outputs . . . . . . . . . . . 54F/74F2640 Octal Bus Transceiver with 25!1 Resistors in the Outputs . . . . . . . . . . . . . . . . . . . 54F/74F2643 Octal Bus Transceiver with 25!1 Resistors in the Outputs . . . . . . . . . . . . . . . . . . . 54F/74F2645 Octal Bus Transceiver with 25!1 Resistors in the Outputs . . . . . . . . . . . . . . . . . . . 29F52 8-Bit Registered Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29F53 8-Bit Registered Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29F68 Dynamic RAM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-621 4-625 4-628 4-628 4-632 4-632 4-632 4-637 4-637 4-643
4.5
0 0
~DNaStemiicoonnduactlor
54F/74FOO
Quad 2-lnput NANO Gate
General Description
This device contains four independent gates, each of which performs the logic NANO function.
Features
� Guaranteed 4000V minimum ESD protection
Ordering Code: see section 5
Logic Symbol
Connection Diagrams
IEEE/IEC
Pin Assignment for DIP, SOIC and Flatpak
Pin Assignment for LCC
Ao
&
Oo
Ao
Bo
Bo A1
01
Oo
81
A1 A2
82
02
81
01 A3
03
GND
83
TL/F/9454-3
14 Vee
A2 82 02 A3 83 03
TL/F/9454-2
o8o1
NmC rAn1
NC
rn
m60
01 [[] GND [QI
NC [j]
03 li11
83 Ii]
[I] Bo
EilAo [JJNC
Im Vee
!IfilA2
IJ}]~[j]][j]][j]]
A3 NC 02 NC 82
TL/F/9454-1
Unit Loading/Fan Out: See Section 2 for U.L. definitions
Pin Names
An,Bn On
Description
Inputs Outputs
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loHlloL
1.0/1.0 50/33.3
20 �A/-0.6 mA -1 mA/20 mA
4-6
Absolute Maximum Ratings (Note 1)
If MiiitaryI Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
-55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to+ 7.0V
Input Voltage (Note 2)
-0.5V to+ 7.0V
Input Current (Note 2)
-30 mA to+ 5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5VtoVee - 0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
ESD Last Passing Voltage (Min)
4000V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
0 0
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
V1H
Input HIGH Voltage
V1L
Input LOW Voltage
Yeo
Input Clamp Diode Voltage
54F/74F Min Typ Max
Units Vee
Conditions
2.0
v
Recognized as a HIGH Signal
0.8
v
Recognized as a LOW Signal
-1.2
v
Min l1N = -18mA
VoH
Output HIGH
Voltage
54F 10% Vee 2.5
74F 10% Vee 2.5
74F 5% Vee
2.7
loH = -1 mA
v
Min loH = -1 mA
loH = -1 mA
Vol
Output LOW
Voltage
54F 10% Vee 74F 10% Vee
0.5
v
Min loL = 20 mA
0.5
IQL = 20mA
l1H
Input HIGH
54F
Current
74F
20.0
5.0
�A Max V1N = 2.7V
lsv1
Input HIGH Current 54F
Breakdown Test
74F
100
�A
Max V1N = 7.0V
7.0
leEX
Output HIGH
54F
Leakage Current
74F
250
50
�A
Max VouT =Vee
V10
Input Leakage
74F
Test
4.75
v
llD = 1.9 �A 0.0
All other pins grounded
loo
Output Leakage
74F
Circuit Current
3.75
�A
0.0
V100 = 150 mV All other pins grounded
l1L
Input LOW Current
los
Output Short-Circuit Current
-0.6
mA
Max V1N = 0.5V
-60
ov -150
mA
Max VouT =
leeH
Power Supply Current
1.9
2.8
mA Max Vo= HIGH
leeL
Power Supply Current
6.8
10.2
mA Max Vo= LOW
4-7
0 0
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
tPLH
Propagation Delay
tPHL
An, Bn to On
74F
TA= +25�C Vee= +5.0V
CL= 50pF
Min
Typ
Max
2.4
3.7
5.0
1.5
3.2
4.3
54F
TA, Vee= Mii CL= 50pF
Min
Max
2.0
7.0
1.5
6.5
74F
TA, Vee= Com CL= 50 pF
Min
Max
2.4
6.0
1.5
5.3
Units
Fig. No.
ns 2-3
4-8
0
I\)
~National
~Semiconductor
54F/74F02
Quad 2-lnput NOR Gate
General Description
This device contains four independent gates, each of which performs the logic NOR function.
Ordering Code: See Sections Logic Symbol
Connection Diagrams
IEEE/I EC
Ao
<?:1
Oo
Bo
A1 01
81
A2 02
82
A3 03
83
Pin Assignment for DIP, SOIC and Flatpak
14
60
Vee
13
Ao
62
Bo
82
01
A2
A1
03
81
83
GND
A3
TL/F/9455-3
TL/F/9455-2
Unit Loading/Fan Out: See Section 2 tor U.L. definitions
Pin Names
An, Bn On
Description
Inputs Outputs
54F/74F
U.L. HIGH/LOW
Input lrHllrL Output loHlloL
1.0/1.0 50/33.3
20 �A/-0.6 mA -1 mA/20 mA
Pin Assignment forLCC
A1 NC 01 NC 8a ml lII ~ [fil [!]
81 [fil GND [QJ
NC [j]
A3 !l11
8311]
[I) Ao
rn 60
O]NC
gQI Vee l!m 02
~[illjj]]l!Zlff�J
03 NC A2 NC 82
TL/F/9455-1
4-9
N 0
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5Vto +7.0V
Input Voltage (Note 2)
-0.5V to+ 7.0V
Input Current (Note 2)
-30 mA to+ 5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5VtoVee - 0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol V1H V1L Veo VoH
VoL l1H
lsv1
lcEx
V10
loo l1L los lecH lecL
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 74F 10% Vee 74F 5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage 74F
Test
Output Leakage 74F
Circuit Current
Input LOW Current
Output Short-Circuit Current
Power Supply Current
Power Supply Current
54F/74F Min Typ Max 2.0
0.8 -1.2 2.5 2.5 2.7 0.5 0.5 20.0 5.0 100 7.0 250
50
4.75
3.75
-0.6
-60
-150
3.7
5.6
8.7
13.0
Units
v v v v
v
�A
�A
�A
v
�A mA mA mA mA
Vee
Min Min
Min Max Max Max 0.0 0.0 Max Max Max Max
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal l1N = -18 mA loH = -1 mA loH = -1 mA loH = -1 mA loL = 20 mA loL = 20 mA
V1N = 2.7V
V1N = 7.0V
VouT =Vee
110 = 1.9 �A All other pins grounded V100 = 150 mV All other pins grounded V1N = 0.5V
VouT = ov
Vo= HIGH Vo= LOW
4-10
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
tPLH
Propagation Delay
tPHL
An, Bn to On
74F
TA= +25�C Vee= +5.0V
CL= 50 pF
Min
Typ
Max
2.5
4.4
5.5
1.5
3.2
4.3
54F
TA, Vee= Mil CL= 50 pF
Min
Max
2.5
7.5
1.5
6.5
74F
TA, Vee= Com CL= 50 pF
Min
Max
2.5
6.5
1.5
5.3
0 N
Units Fig. No.
ns
2-3
4-11
~National
~Semiconductor
54F/74F04
Hex Inverter
General Description
This device contains six independent gates, each of which performs the logic INVERT function.
Features
� Guaranteed 4000V minimum ESD protection
Ordering Code: see sections Logic Symbol
Connection Diagrams
IEEE/I EC
Pin Assignment for
Pin Assignment
DIP, SOIC and Flatpak
for LCC
Ao
Oo
At
Ot
Ao
14 Yee
Az NC Ot NC At
rn rn l!l rn rn
Az
Oz
Oo
13 A3
A3
03
3 A1
03
Oz[[)
moo
A4
04
Ot
As
Os
Az
TL/F/9456-3
Oz
A4
GND (j]]
NC [i]
04
Os li11
As
As fl]
rnA0 [I]NC
Im Yee
ff:IDA3
GND
05
TL/F/9456-2
~[j]]IJ]][ZI[�]
04 NC A4 NC 03
TL/F/9456-1
Unit Loading/Fan Out: see Section 2 tor U.L. definitions
Pin Names
An On
Description
Inputs Outputs
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loHlloL
1.0/1.0 50/33.3
20 �A/-0.6 mA -1 mA/20 mA
4-12
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for avallablllty and specifications.
Storage Temperature
- 65�C to + 15o�c
Ambient Temperature under Bias
- 55�c to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to + 7.0V
Input Voltage (Note 2)
-0.5V to + 7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5Vto Vee -0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated Im (mA)
ESD Last Passing Voltage (Min)
4000V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�c to + 125�c o�cto +70�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
V1H
Input HIGH Voltage
V1L
Input LOW Voltage
Veo
Input Clamp Diode Voltage
54F/74F Min Typ Max
Units Vee
Conditions
2.0
v
Recognized as a HIGH Signal
0.8
v
Recognized as a LOW Signal
-1.2
v
Min l1N = -18 mA
VoH
Output HIGH
Voltage
54F 10% Vee 2.5
74F 10% Vee 2.5
74F 5% Vee
2.7
loH = -1 mA
v
Min loH = -1 mA
loH = -1 mA
Vol
Output LOW
Voltage
54F 10% Vee 74F 10% Vee
0.5
v
Min loL = 2omA
0.5
loL = 20 mA
l1H
Input HIGH
54F
Current
74F
20.0
5.0
�A Max V1N = 2.7V
lsv1
Input HIGH Current 54F
Breakdown Test
74F
100 7.0
�A
Max V1N = 7.0V
leEx
Output HIGH
54F
Leakage Current
74F
250 50
�A
Max Vour =Vee
V10
Input Leakage
74F
4.75
Test
v
0.0 110 = 1.9 �A
All other pins grounded
loo
Output Leakage 74F
Circuit Current
3.75
�A
0.0
V100 = 150mV
All other pins grounded
l1L
Input LOW Current
-0.6
mA
Max V1N = 0.5V
los
Output Short-Circuit Current
-60
-150 mA Max Vour = ov
leeH
Power Supply Current
2.8
4.2
mA Max Vo= HIGH
leeL
Power Supply Current
10.2 15.3
mA Max Vo= LOW
4-13
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
lPLH
Propagation Delay
lPHL
An to On
74F
TA= +25�c Vee= +5.0V
CL= 50 pf
Min
Typ
Max
2.4
3.7
5.0
1.5
3.2
4.3
54F
TA, Vee= Mil CL= 50pF
Min
Max
2.0
7.0
1.5
6.5
74F
TA, Vee= Com CL= 50 pf
Min
Max
2.4
6.0
1.5
5.3
Fig. Units No.
ns 2-3
4-14
0
Q)
~National
U Semiconductor
54F/74F08
Quad 2-lnput AND Gate
General Description
This device contains four independent gates, each of which performs the logic AND function.
Features
� Guaranteed 4000V minimum ESD protection
Ordering Code: see section 5 Logic Symbol
Connection Diagrams
IEEE/I EC
Ao
&
Oo
Bo
A1 01
81
A2 02
82
A3 03
83
TL/F/9457-3
Pin Assignment for DIP, SOIC and Flatpak
TL/F/9457-2
Unit Loading/Fan Out: see Section 2 for U.L. definitions
Pin Names
An, Bn On
Description
Inputs Outputs
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loHlloL
1.0/1.0 50/33.3
20 �A/-0.6 mA -1 mA/20 mA
Pin Assignment for LCC
81 NC A1 NC Oo [ID [[] [fil [[] [I]
o, [2J
GND [j]] NC [j]
03 [j]] 83 [j]
rne0
[I)Ao [JJ NC
!ill Vee
[i]]A2
!j]][ill[�J[ZJ[j]] A5 NC 02 NC 82
TL/F /9457-1
4-15
co
0
Absolute Maximum Ratings (Note 1>
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5Vto +7.0V
Input Voltage (Note 2)
-0.5V to + 7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5VtoVee - 0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
ESD Last Passing Voltage (Min)
4000V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V +4.5V to +5.5V
DC Electrical Characteristics
Symbol �
Parameter
V1H V1L Veo VoH
VOL
l1H
lsv1
leEX
V10
loo
l1L los leeH leeL
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 74F 10% Vee 74F5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage 74F
Test
Output Leakage 74F
Circuit Current
Input LOW Current
Output Short-Circuit Current
Power Supply Current
Power Supply Current
54F/74F Min Typ Max 2.0
0.8 -1.2
2.5 2.5 2.7
0.5 0.5 20.0. 5.0 100 7.0 250 50
4.75
3.75
-0.6
-60
-150
5.5
8.3
8.6 12.9
Units
v
v v
v
v
�A
�A
�A
v
�A mA mA mA mA
Vee
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal Min l1N = -18 mA loH = -1 mA Min loH = -1 mA loH = -1 mA Min loL = 20 mA loL = 20 mA V1N = 2.7V Max
Max V1N = 7.0V
Max Vour =Vee
110 = 1.9 �A 0.0 All Other Pins Grounded 0.0 V100 = 150 mV
All Other Pins Grounded Max V1N = 0.5V
Max Vour = ov
Max Vo= HIGH Max Vo= LOW
4-16
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
tPLH tPHL
Propagation Delay An. Bn to On
74F
TA= +25�C Vee= +5.0V
CL= 50 pf
Min
Typ
Max
3.0
4.2
5.6
2.5
4.0
5.3
54F
TA, Vee= Mil CL= 50 pf
Min
Max
2.5
7.5
2.0
7.5
74F
TA, Vee= Com CL= 50 pf
Min
Max
3.0
6.6
2.5
6.3
0
Q)
Fig. Units No.
ns
2-3
4-17
0.....
D~NaStemiicoonnduactlor
54F/74F10
Triple 3-lnput NANO Gate
General Description
This device contains three independent gates, each of which performs the logic NANO function.
Ordering Code: see section 5
Logic Symbol
IEEE/I EC
Ao
&
Bo
60
Co
A1
81
61
C1
A2
82
02
C2
TL/F/9458-3
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
Ao ...1._ _ _.....,
Bo-=2:t-----.1r-......A1 3 81 4 C1 5 01 6 GND 7
TL/F/9458-2
Pin Assignment for LCC
C1 NC 81 NC A1
rn:i mrn rn m
01 [ID GND [QI
NC [j]
02 ll11
C2 Ii]
rnso rnAo
[]]NC
@!Vee
[j]]Co
Ii] [�] [j] [fl] [j])
B2 NC A2 NC 60
TL/F/9458-1
Unit Loading/Fan Out: See Section 2 for u.L. definitions
Pin Names
An, Bn, Cn On
Description
Inputs Outputs
54F/74F
U.L. HIGH/LOW
Input l1H/l1L Output loHlloL
1.0/1.0 50/33.3
20 �A/-0.6 mA -1 mA/20 mA
4-18
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 15o�c
Ambient Temperature under Bias
-55�C to+ 125�c
Junction Temperature under Bias
-55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5Vto +7.0V
Input Voltage (Note 2)
-0.5Vto +7.0V
Input Current (Note 2)
-30 mA to + 5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TAI-STATE� Output
-0.5VtoVec - 0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
.....
0
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C o�cto +70�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
54F/74F Min Typ Max
Units Vee
Conditions
V1H
Input HIGH Voltage
V1L
Input LOW Voltage
2.0
v
Recognized as a HIGH Signal
0.8
v
Recognized as a LOW Signal
Veo
Input Clamp Diode Voltage
-1.2
v
Min l1N = -18mA
VoH
Output HIGH
Voltage
54F 10% Vee 2.5
74F 10% Vee 2.5
74F 5% Vee
2.7
loH = -1 mA
v
Min loH = -1 mA
loH = -1 mA
VoL
Output LOW
Voltage
54F 10% Vee 74F 10% Vee
0.5
v
Min loL = 20 mA
0.5
loL = 20 mA
l1H
Input HIGH
54F
Current
74F
20.0
5.0
�A Max V1N = 2.7V
lsv1
Input HIGH Current 54F
Breakdown Test
74F
100
7.0
�A Max V1N = 7.0V
lcEX
Output HIGH
54F
Leakage Current
74F
250 50
�A
Max VouT =Vee
V10
Input Leakage
Test
74F
4.75
v
0.0 110 = 1.9 �A All other pins grounded
loo
Output Leakage
Circuit Current
74F
3.75
�A
0.0
V100 = 150mV All other pins grounded
l1L
Input LOW Current
-0.6
mA Max V1N = 0.5V
los
Output Short-Circuit Current
-60
-150 mA Max VouT = ov
leeH
Power Supply Current
1.4
2.1
mA Max Vo= HIGH
leeL
Power Supply Current
5.1
7.7
mA Max Vo= LOW
a
4-19
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
tPLH tPHL
Propagation Delay An. Bn, Cn to On
74F
TA= +25�C Vee= +5.0V
CL= 50pF
Min
Typ
Max
2.4
3.7
5.0
1.5
3.2
4.3
54F
TA, Vee= Mil CL= 50 pf
Min
Max
2.0
7.0
1.5
6.5
74F
TA, Vee= Coin CL= 50 pf
Min
Max
2.4
6.0
1.5
5.3
Fig. Units No.
ns
2-3
4-20
..........
~National
U Semiconductor
54F/74F11 Triple 3-lnput AND Gate
General Description
This device contains three independent gates, each of which performs the logic AND function.
Ordering Code: see section 5
Logic Symbol
IEEE/I EC
Ao
&
Bo
Co
A1 B1 C1
A2 B2 C2
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
Pin Assignment for LCC
Ao 2
Bo 3
A1
B1
C1
01 GND
Yee
Co Oo A2 B2 C2 02
TL/F/9459-2
rcn1
NC
rn
rBn1
NC
rn
mA1
011]]
GND !ill
NC [j]
02~ Cz [j]
[I] Bo
ill Ao
[j]NC
@Vee
[j]]Co
~ [j]J[j]]fi] [j]] B2 NC A2 NC 00
TL/F/9459-1
TL/F/9459-3
Unit Loading/Fan Out: See Section 2 for U.L. definitions
Pin Names
An, Bn, Cn On
Description
Inputs Outputs
54F/74F
U.L. HIGH/LOW
Input lrHllrL Output loHllOL
1.0/1.0 50/33.3
20 �A/-0.6 mA -1 mA/20 mA
4-21
,,........ Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�c
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to + 7.0V
Input Voltage (Note 2)
-0.5Vto +7.0V
Input Current (Note 2)
-30 mA to + 5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5VtoVee -0.5V to + 5.5V
Current Applied to Output
in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C o�cto +10�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
V1H V1L Veo VoH
VOL
l1H
lsv1
leEX
V10
loo
l1L los leeH leeL
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 74F 10% Vee 74F5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage 74F
Test
Output Leakage 74F
Circuit Current
Input LOW Current
Output Short-Circuit Current
Power Supply Current
Power Supply Current
54F/74F Min Typ Max 2.0
0.8 -1.2 2.5 2.5 2.7 0.5 0.5 20.0 5.0 100 7.0 250
50
4.75
3.75
-0.6
-60
-150
4.1
6.2
6.5
9.7
Units v v v
v
v
�A
�A
�A
v
�A mA mA mA mA
Vee
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal Min l1N = -18mA loH = -1 mA Min loH = -1 mA loH = -1 mA Min loL = 20 mA loL = 20 mA
Max V1N = 2.7V
Max V1N = 7.0V
Max Vour =Vee
0.0
110 = 1.9 �A
All other pins grounded
0.0 V100 = 150 mV All other pins grounded
Max V1N = 0.5V
Max Vour = ov
Max Vo= HIGH
Max Vo= LOW
4-22
AC Electrical Characteristics: See Section 2 tor Waveforms and Load Configurations
Symbol
Parameter
tPLH
Propagation Delay
tPHL
An, Bn, Cn to On
74F
TA= +25�C Vee= +5.0V
CL= 50 pF
Min
Typ
Max
3.0
4.2
5.6
2.5
4.1
5.5
54F
TA, Vee= Mil CL= 50 pF
Min
Max
2.5
7.5
2.0
7.5
74F
TA, Vee= Com CL= 50 pF
Min
Max
3.0
6.6
2.5
6.5
......
Fig. Units
No.
ns
2-3
4-23
~National
~Semiconductor
54F/74F13 Dual 4-lnput NANO Schmitt Trigger
General Description
The 'F13 contains two 4-input NANO gates which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. In addition, they have a greater noise margin than conventional NANO gates.
Each circuit contains a 4-input Schmitt trigger followed by level shifting circuitry and a standard FAST� output struc-
ture. The Schmitt trigger uses positive feedback to effectively speed-up slow input transitions, and provide different input threshold voltages for positive- and negative-going transitions. This hysteresis between the positive-going and negative-going input threshold (typically 800 mV) is determined by resistor ratios and is essentially insensitive to temperature and supply voltage variations.
Features
� Guaranteed 4000V minimum ESO protection
Ordering Code: See section 5 Logic Symbol
IEEE/I EC &.U
Ao Bo Co Do
A1
e,
c,
o,
TL/F/9460-3
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
Ao-+--. Bo--.---.1
NC
c0----.11
Do.-...--.111
Oo
GND
TL/F/9460-1
Pin Assignment for LCC
Do NC Co NC NC
!ID cz:rn:rn::i rn
Oo []]
GND Ii.QI
NC [j]
o, n1l
o, Ii]
me0
[I]Ao [i]NC
@JYcc [i]]A1
!i}][j]][�]lil][�] C1 NC NC NC 81
TL/F/9460-2
Unit Loading/Fan Out: See Section 2 for U.L. definitions
Pin Names
An. Bn, Cn. On On
Description
Inputs Outputs
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loHllOL
1.0/1.0 50/33.3
20 �A/-0.6 mA -1 mA/20mA
Function Table
Inputs
Output
A Bc D
0
L xxx H
xL xx H
xxL x H
x x x L
H
H H H H
L
H = HIGH Voltage Level
L = LOW Voltage Level X = Immaterial
4-24
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�c
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to + 7.0V
Input Voltage (Note 2)
-0.5V to + 7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5VtoVee - 0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
ESD Last Passing Voltage (Min)
4000V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
......
w
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�cto +70�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
Vr+ Vrll.Vr Veo
Positive-Going Threshold Negative-Going Threshold Hysteresis (Vr + -Vr -) Input Clamp Diode Voltage
54F/74F
Min Typ
Max
Units Vee
Conditions
1.5
2.0
v
5.0
0.7
1.1
v
5.0
0.4
-
v
5.0
-1.2
v
Min l1N = -18 mA
VoH
Output HIGH
Voltage
54F 10% Vee
2.5
74F 10% Vee
2.5
74F5% Vee
2.7
loH = -1 mA
v
Min loH = -1 mA
loH = -1 mA
VOL
Output LOW
Voltage
54F 10% Vee 74F 10% Vee
0.5
v
Min
loL = 20 mA
0.5
loL = 20 mA
l1H
Input HIGH
54F
Current
74F
20.0
V1N = 2.7V
5.0
�A
Max
lsv1
Input HIGH Current 54F
Breakdown Test
74F
100 7.0
�A
Max V1N = 7.0V
leEx
Output HIGH
54F
Leakage Current
74F
250
�A
Max Vour =Vee
50
V10
Input Leakage
74F
Test
4.75
v
0.0
110 = 1.9 �A All Other Pins Grounded
loo
Output Leakage 74F
Circuit Current
3.75
�A
0.0
V100 = 150 mV
All Other Pins Grounded
l1L
Input LOW Current
los
Output Short-Circuit Current
-0.6
mA
Max V1N = 0.5V
-60
-150
mA
Max Vour = ov
leeH
Power Supply Current
4.5
8.5
mA
Max Vo= HIGH
leeL
Power Supply Current
7.0
10.0
mA
Max Vo= LOW
4-25
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
tPLH
Propagation Delay
tPHL
An, Bn, Cn, Dn to On
74F
TA= +25�C Vee= +5.0V
CL= 50pF
Min
Typ
Max
5.0
10.5
9.5
17.5
54F
TA, Vee= Mil CL= 50pF
Min
Max
3.0
16.0
8.5
22.0
74F
TA, Vee= Com CL= 50 pf
Min
Max
4.5
12.0
9.5
18.5
Fig. Units No.
ns 2-3
4-26
~National
U Semiconductor
54F/74F14
Hex Inverter Schmitt Trigger
General Description
The 'F14 contains six logic inverters which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. In addition, they have a greater noise margin than conventional inverters.
Each circuit contains a Schmitt trigger followed by a Darlington level shifter and a phase splitter driving a TTL totempole output. The Schmitt trigger uses positive feed back to
effectively speed-up slow input transition, and provide different input threshold voltages for positive and negative-going transitions. This hysteresis between the positive-going and negative-going input thresholds (typically 800 mV) is determined internally by resistor ratios and is essentially insensitive to temperature and supply voltage variations.
Features
� Guaranteed 4000V minimum ESD protection
Ordering Code: see section 5
Logic Symbol
IEEE/IEC
lo .rr
Bo
11 .rr
B1
12 .rr
B2
13 .rr
B3
14 .rr
B4
15 .O"
B5 TL/F/9461-3
Connection Diagrams
Pin Assignment DIP, SOIC and Flatpak
lo Bo 11 B1 12 62 GND
TL/F/9461-1
Pin Assignment for LCC
12 NC B1 NC 11
rn:rn:rnH[WJ
B2 [fil
GND [j]] NC [j)
B3 !i1l
13 rm
LlJ6o
mlo
!I]NC
Im Yee
@115
!GI�] fill li1l [�] 04 NC 14 NC B5
TL/F/9461-2
Unit Loading/Fan Out: See Section 2 for u.L. definitions
Pin Names
In
On
Description
Input Output
54F/74F
U.L. HIGH/LOW
Input l1H/l1L Output loHlloL
1.0/1.0 50/33.3
20 �A/ - 0.6 mA -1 mA/20 mA
Function Table
Input
A
L H
H = HIGH Voltage Level
L = LOW Voltage Level
Output
0
H L
4-27
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
-65�C to+ 150�C
Ambient Temperature under Bias Junction Temperature under Bias
- 55�C to + 125�C
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
- 0.5V to + 7.0V
Input Voltage (Note 2)
-0.5V to + 7.0V
Input Current (Note 2)
-30 mA to + 5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5VtoVee - 0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
ESD Last Passing Voltage (Min)
4000V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�cto +70�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
Vr+ Vrt:i.Vr Veo VoH
VoL
l1H
lsv1
le EX
V10
loo
l1L los leeH leeL
Positive-Going Threshold
Negative-Going Threshold
Hysteresis (Vr + -Vr -)
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 74F 10% Vee 74F5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage
74F
Test
Output Leakage 74F
Circuit Current
Input LOW Current
Output Short-Circuit Current
Power Supply Current
Power Supply Current
54F/74F
Min
Typ
Max
1.5
1.7
2.0
0.7
0.9
1.1
0.4
0.8
-1.2
2.5 2.5 2.7
0.5 0.5
20.0 5.0
100 7.0
250 50
4.75
-60
3.75
-0.6 -150
25 25
Units
v v v v v
v
�A
�A
�A
v
�A mA mA mA mA
Vee
5.0V 5.0V 5.0V Min
Min
Min
Max
Max
Max
Max
0.0 Max Max Max Max
Conditions
l1N = -18 mA loH = -1 mA loH = -1 mA loH = -1 mA loL = 20 mA loL = 20 mA V1N = 2.7V
V1N = 7.0V
Vour =Vee
llD = 1.9 �A All Other Pins Grounded V100 = 150 mV All Other Pins Grounded V1N = 0.5V
Vour = ov
Vo= HIGH Vo= LOW
4-28
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
tPLH tPHL
Propagation Delay In-+ On
74F
TA= +2s0 c
Vee= +5.0V CL= 50 pF
Min
Max
4.0
10.5
3.5
8.5
54F
TA, Vee= Mil CL= 50 pF
Min
Max
4.0
14.0
3.5
10.0
74F
TA, Vee= Com CL= 50 pF
Min
Max
4.0
11.5
3.5
9.0
Units
Fig. No.
ns
2-3
4-29
~National
D Semiconductor
54F/74F20 Dual 4-lnput NANO Gate
General Description
This device contains two independent gates, each of which performs the logic NANO function.
Ordering Code: see section 5 Logic Symbol
IEEE/I EC &
Ao Bo
Oo Co Do
A1 Bt
01 C1 D1
TL/F/9462-3
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
1 Ao
2 Bo NC 3
4 Co Do 5
6 Oo GND 7
14 Vee 13 At 12B1 11 NC 10c1
9 Dt 8 0-1
TL/F/9462-2
Pin Assignment forLCC
Do NC Co NC NC
[[) rn [[) mrn
60 rn
GND [QI NC (j]
01 l!ll
D1 ti]
aJBo rnAo []]NC ~Vee !IfilA1
[11 Ii]] Ii] [j] [j]] c1 NC NC NC B1
TL/F/9462-1
Unit Loading/Fan Out: See Section 2 for u.L. definitions
Pin Names
An. Bn, Cn. Dn On
Description
Inputs Outputs
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loHlloL
1.011.0 50/33.3
20 �A/-0.6 mA -1 mA/20 mA
4-30
Absolute Maximum Ratings (Note 1>
If MilitaryI Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�c
Junction Temperature under Bias
- 55�c to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to + 7.0V
Input Voltage (Note 2)
-0.5V to + 7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5VtoVee
- 0.5V to +5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
N 0
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�c o�cto +70�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
54F/74F Min Typ Max
Units Vee
Conditions
V1H
Input HIGH Voltage
2.0
v
Recognized as a HIGH Signal
V1L
Input LOW Voltage
0.8
v
Recognized as a LOW Signal
Veo
input Clamp Diode Voltage
-1.2
v
Min l1N = -18 mA
VoH
Output HIGH
Voltage
54F 10% Vee 2.5
74F 10% Vee 2.5
74F5% Vee
2.7
loH = -1 mA
v
Min loH = -1 mA
loH = -1 mA
VOL
Output LOW
Voltage
54F 10% Vee 74F 10% Vee
0.5
v
Min loL = 20 mA
0.5
loL = 20 mA
l1H
Input HIGH
54F
Current
74F
20.0
�A Max V1N = 2.7V
5.0
lsv1
Input HIGH Current 54F
Breakdown Test
74F
100
7.0
�A Max V1N = 7.0V
leEX
Output HIGH
54F
Leakage Current
74F
250
50
�A
Max VouT =Vee
V10
Input Leakage
74F
4.75
Test
v
0.0 110 = 1.9 �A
All other pins grounded
loo
Output Leakage
Circuit Current
74F
3.75
�A
0.0 V100 = 150mV
All other pins grounded
l1L
Input LOW Current
-0.6
mA
Max V1N = 0.5V
los
Output Short-Circuit Current
-60
-150 mA Max VouT = ov
lecH
Power Supply Current
0.9
1.4
mA Max Vo= HIGH
lceL
Power Supply Current
3.4
5.1
mA Max Vo= LOW
4-31
0 N
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
74F
54F
74F
Symbol
Parameter
tPLH
Propagation Delay
tPHL
An. Bn, Cn, Dn to On
TA= +25�C Vee= +5.0V
CL= 50 pf
Min
Typ
Max
2.4
3.7
5.0
1.5
3.2
4.3
TA, Vee= Mil CL= 50pF
Min
Max
2.0
7.0
1.5
6.5
TA, Vee= Com CL= 50pF
Min
Max
2.4
6.0
1.5
5.3
Units
Fig. No.
ns 2-3
4-32
~National
U Semiconductor
54F/74F27
Triple 3-lnput NOR Gate
General Description
This device contains three independent gates, each of which performs the logic NOR function.
Ordering Code: see sections Logic Symbol
Connection Diagrams
IEEE/IEC
Pin Assignment for DIP, SOIC and Flatpak
A1 81
o,
82
c,
A2
c,
A2
81
82
02
C2
A1
o,
A3
GND
83
03
C3
TL/F/9539-3
TL/F/9539-2
Unit Loading/Fan Out: See Section 2 for u.L. Definitions
Pin Names
An, Bn, Cn On
Description
Data Inputs Data Outputs
54F/74F
U.L. HIGH/LOW
Input l1HlllL Output loHlloL
1.0/1.0 50/33.3
20 �A/-0.6 mA -1 mA/20mA
Pin Assignment forLCC
A1 NC
l!HIJ
81
III
NC
rn
C1
111
01 [[) GND [QI NC [i]
03 ffll
C31Lll - - - - - ' I I
alA2 !1JB2
OJ NC
@!Vee IJ]]C2
Ii] Ii] [j]] [j] Ii]) 83 NC A3 NC 02
TL/F/9539-1
Function Table
Inputs
Output
An
Bn
Cn
L
L
L
x
x
H
x
H
x
H
x
x
On
H = HIGH Voltage Level
H
L = LOW Voltage Level
L
X = Immaterial
L
L
4-33
Absolute Maximum Ratings (Note 1)
If MilitaryI Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vcc Pin Potential to Ground Pin
- 0.5V to + 7.0V
Input Voltage (Note 2)
-0.5Vto +7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5VtoVcc -0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
V1H
Input HIGH Voltage
V1L
Input LOW Voltage
Vco
Input Clamp Diode Voltage
54F/74F Min Typ Max
Units Vee
Conditions
2.0
v
Recognized as a HIGH Signal
0.8
v
Recognized as a LOW Signal
-1.2
v
Min l1N = -18 mA
VoH
Output HIGH
Voltage
54F 10% Yee 2.5
74F 10% Vee 2.5
74F 5% Vee
2.7
loH = -1 mA
v
Min loH = -1 mA
loH = -1 mA
Vol
Output LOW
Voltage
54F 10% Vee 74F 10% Vee
0.5
v
Min loL = 20 mA
0.5
loL = 20 mA
l1H
Input HIGH Current 54F
74F
20.0
�A
Max VrN = 2.7V
5.0
lsv1
Input HIGH Current 54F
Breakdown Test
74F
100
�A
Max Y1N = 7.0V
7.0
le EX
Output HIGH
54F
Leakage Current
74F
250 50
�A
Max Vour =Yee
V10
Input Leakage
Test
74F
4.75
v
0.0 110 = 1.9 �A
All Other Pins Grounded
loo
Output Leakage 74F
Circuit Current
3.75
�A
0.0 V100 = 150 mV
All Other Pins Grounded
lrL
Input LOW Current
los
Output Short-Circuit Current
-0.6
mA
Max V1N = 0.5V
-60
ov -150 mA Max Your=
leeH
Power Supply Current
4.0
5.5
mA Max Yo= HIGH
leeL
Power Supply Current
8.7
12.0
mA Max Yo= LOW
4-34
AC Electrical Characteristics: See Section 2 tor Waveforms and Load Configurations
Symbol
Parameter
tPLH
Propagation Delay
lPHL
74F
TA= +25�C Vee= +5.0V
CL= 50 pF
Min
Typ
Max
2.0
3.8
6.0
1.0
2.6
4.0
54F
TA, Vee= Mil CL= 50 pF
Min
Max
74F
TA, Vee= Com CL= 50 pF
Min
Max
1.5
6.5
1.0
4.5
Units
Fig. No. .
ns 2-3
4-35
D~NaStemiicoonnduactlor
54F/74F30
8-lnput NANO Gate
General Description
This device contains a single gate, which performs the logic NANO function.
Ordering Code: see Section 5 Logic Symbol
Connection Diagrams
IEEE/I EC
Pin Assignment for DIP, Flatpak and SOIC
TL/F/9560-4
TL/F/9560-1
Unit Loading/Fan Out: See Section 2 for U.L. Definitions .
Pin Names
Ao-A7
0
Description
Inputs Output
54F/74F
U.L. HIGH/LOW
Input l1HlllL Output loHlloL
1.0/1.0 50/33.3
20 �Al -0.6 mA -1 mA/20mA
Pin Assignment for LCC
A1 NC Ai NC A3
[[) mIII [[] rn
A0 m
GND [!QI
NC [j]
o[J]~<E==:_,
NC [j]
rnA4 (l]A5 [}]NC ~Vee [ID NC
[i]]~[�J[j][ID
NC NC A1 NC As
TL/F/9560-2
Function Table
Inputs
Output
AO A1 A2 A3 A4 AS A6 A7
0
Lxxxxxxx H
xLxxxxxx H
xxLxxxxx H
xxxLxxxx H
xxxxLxxx H
xxxxxLxx H
xxxxxxLx H
xxxxxxxL H
H H H H H H H H
L
H = HIGH Voltage Level L = LOW Voltage Level
X = Immaterial
4-36
Absolute Maximum Ratings (Note 1)
If Miiitary/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for avallablllty and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
-55�C to+ 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to+ 7.0V
Input Voltage (Note 2)
-0.5Vto +7.0V
Input Current (Note 2)
-30 mA to + 5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5VtoVee -0.5V to + 5.5V
Current Applied to Output
in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
w
0
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol V1H V1L Veo VoH
Vol lrH
lsvr
leEx Vro
loo l1L los leeH leeL
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 74F 10% Vee 74F5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage 74F
Test
Output Leakage 74F
Circuit Current
Input LOW Current
Output Short-Circuit Current
Power Supply Current
Power Supply Current
54F/74F Min Typ Max 2.0
0.8 -1.2 2.5 2.5 2.7 0.5 0.5 20.0 5.0 100 7.0 250 50
4.75
3.75
-0.6
-60
-150
0.5
1.5
4.5
Units v v v
v
v
�A
�A
�A
v
�A mA mA mA mA
Vee
Min Min
Min Max Max Max 0.0 0.0 Max Max Max Max
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal lrN = -18mA loH = -1 mA loH = -1 mA loH = -1 mA loL = 20 mA loL = 20 mA V1N = 2.7V
V1N = 7.0V
VouT =Vee
110 = 1.9 �A All Other Pins Grounded Vroo = 150 mv All Other Pins Grounded V1N = 0.5V
VouT = ov
Vo= HIGH Vo= LOW
4-37
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
tPLH
Propagation Delay
tpHL
AntoO
74F
TA= +25�c Vee= +5.0V
CL= 50 pf
Min
Typ
Max
1.0
3.7
5.0
1.5
2.8
5.0
54F
TA, Vee= Mil CL= 50pF
Min
Max
74F
TA, Vee= Com CL= 50 pf
Min
Max
1.0
5.5
1.5
5.5
Units
Fig. No.
ns
2-3
4-38
a~National Semiconductor
54F/74F32
Quad 2-lnput OR Gate
General Description
This device contains four independent gates, each of which performs the logic OR function.
Features
� Guaranteed 4000V minimum ESD protection
Ordering Code: see section 5 Logic Symbol
Connection Diagrams
IEEE/I EC
Pin Assignment for
Ao
~1
Bo
A1
B1
A2
B2
A3
B3
DIP, SOIC and Flatpak
Oo
Ao
Vee
o,
Bo
A2
Oo
B2
02
A1
02
B1
A3
03
o,
B3
GND
03
TL/F/9463-3
TL/F /9463-2
Unit Loading/Fan Out: See Section 2 for U.L. definitions
Pin Names
An, Bn On
Description
Inputs Outputs
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loHlloL
1.0/1.0 50/33.3
20 �A/-0.6 mA -1 mA/20 mA
Pin Assignment forLCC
B1 NC A1 NC Oo [[J[I]!IJ(fil[I]
o1rn
GND [QI NC [j]
03 ffll
B3 ll]I
ill Bo III A0
OJNC
~Vee
@JA2
~ li]]@l!ZJ[�) A3 NC 02 NC B2
TL/F/9463-1
4-39
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
-55�C to+ 175�C
Vee Pin Potential to Ground Pin
-0.5V to + 7.0V
Input Voltage (Note 2)
-0.5Vto +7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee= OV) Standard Output TRI-STATE� Output
-0.5Vto Vee -0.5Vto +5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
ESD Last Passing Voltage (Min)
4000V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�C to +70�C
Supply Voltage Military .
Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
�I
V1H
Input HIGH Voltage
V1L
Input LOW Voltage
Veo
Input Clamp Diode Voltage
VoH
Output HIGH
Voltage
54F 10% Vee 74F 10% Vee 74F5% Vee
VoL
Output LOW
Voltage
54F 10% Vee 74F 10% Vee
l1H
Input HIGH
54F
Current
74F
lsv1
Input HIGH Current 54F
Breakdown Test
74F
le Ex
Output HIGH
54F
Leakage Current
74F
V10
Input Leakage
74F
Test
loo
Output Leakage 74F
Circuit Current
l1L
Input LOW Current
los
Output Short-Circuit Current
lecH
Power Supply Current
leeL
Power Supply Current
54F/74F Min Typ Max 2.0
0.8 -1.2 2.5 2.5 2.7 0.5 0.5 20.0 5.0 100 7.0 250
50
4.75
3.75
-0.6
-60
-150
6.1
9.2
10.3 15.5
Units
v v v v
v
�A
�A
�A
v
�A mA mA mA mA
Vee
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal Min l1N = -18 mA loH = -1 mA Min . loH = -1 mA loH = -1 mA Min loL�= 20 mA loL = 20 mA Max V1N = 2.7V
Max V1N = 7.0V
Max Vour =Vee
0.0 110 = 1.9 �A All Other Pins Grounded
0.0 V100 = 150 mV All Other Pins Grounded
Max V1N = 0.5V
Max Vour = ov
Max Vo= HIGH Max Vo= LOW
4-40
AC Electrical Characteristics: See Section 2 tor Waveforms and Load Configurations
Symbol
Parameter
tPLH
Propagation Delay
tPHL
An, Bn to On
74F
TA= +25�C Vee= +5.0V
CL= 50 pf
Min
Typ
Max
3.0
4.2
5.6
3.0
4.0
5.3
54F
TA, Vee= Mii CL= 50pF
Min
Max
3.0
7.5
2.5
7.5
74F
TA, Vee= Com CL= 50 pf
Min
Max
3.0
6.6
3.0
6.3
w
I\)
Fig. Units No.
ns
2-3
4-41
D~NaStemiicoonnduactlor
54F/74F37
Quad Two-Input NANO Buffer
General Description
This device contains four independent gates, each of which performs the logic NANO function.
Ordering Code: see section 5 Logic Symbol
Connection Diagrams
IEEE/I EC
Ao
&I>
Oo
Bo
A1
o,
B1
A2 02
B2
A3 03
B3
Pin Assignment for DIP, SOIC and Flatpak
14
Ao
Vee
Bo
A2
Oo
B2
A1
02
B1
A3
01
B3
GND
TL/F/9464-3
TL/F/9464-1
Unit Loading/Fan Out: See Section 2 tor U.L. definitions
Pin Names
An. Bn On
Description
Inputs Outputs
U.L. HIGH/LOW
1.0/2.0 600/106.6 (80)
54F/74F
Input l1H/l1L Output loHlloL
20 �A/-1.2 mA -12 mA/64 mA (48 mA)
Pin Assignment for LCC
B1 NC A1 NC 50
[[JITJ[[)[fil[I]
o, [[]
GND [Q] NC [i]
031!11 B3 Ii]
LlJBo !IIA0 [j]NC
~Vee [ID A2
[1}[fil!rnil111J]] A3 NC 02 NC B2
TL/F/9464-2
Function Table
Inputs
A
B
L
L
L
H
H
L
H
H
Output
0
H H H L
H = HIGH Voltage Level L = LOW Voltage Level
4-42
Absolute Maximum Ratings (Note 1>
If MilitaryI Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 15o�c
Ambient Temperature under Bias
- 55�C to + 125�c
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to + 7.0V
Input Voltage (Note 2)
-0.5V to + 7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5V to Vee -0.5V to+ 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C o�cto +70�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
V1H
Input HIGH Voltage
54F/74F Min Typ Max 2.0
Units Vee
Conditions
v
Recognized as a HIGH Signal
V1L
Input LOW Voltage
Veo
Input Clamp Diode Voltage
0.8
v
Recognized as a LOW Signal
-1.2
v
Min l1N = -18mA
VoH
Output HIGH
Voltage
54F 10% Vee 2.4
54F 10% Vee 2.0
74F 10% Vee 2.4
74F 10% Vee 2.0
74F5% Vee
2.7
loH = -3mA
loH = -12mA
v
Min loH = -3 mA
loH = -15 mA
loH = -3 mA
Vm
Output LOW
Voltage
54F 10% Vee 74F 10% Vee
0.55
v
Min loL = 48 mA
0.55
loL = 64 mA
l1H
Input HIGH
54F
Current
74F
20.0 5.0
�A
Max V1N = 2.7V
lsv1
Input HIGH Current 54F
Breakdown Test
74F
100 7.0
�A
Max V1N = 7.0V
leEx
Output HIGH
54F
Leakage Current
74F
250
�A
Max Vour =Vee
50
V10
Input Leakage
74F
4.75
Test
v
0.0
110 = 1.9 �A All Other Pins Grounded
loo
Output Leakage 74F
Circuit Current
3.75
�A
0.0 V100 = 150 mV All Other Pins Grounded
l1L
Input LOW Current
-1.2 mA Max V1N = 0.5V
los
Output Short-Circuit Current
-100
-225 mA Max Vour =av
leeH
Power Supply Current
3.7
6.0
mA Max Vo= HIGH
leeL
Power Supply Current
28.0 33.0
mA Max Vo= LOW
4-43
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
tPLH
Propagation Delay
tPHL
An, Bn to On
74F
TA= +25�C Vee= +5.0V
CL= 50 pf
Min
Typ
Max
2.0
3.2
5.5
1.5
2.4
4.5
54F
TA, Vee= Mil CL= 50pF
Min
Max
74F
TA, Vee= Com CL= 50 pf
Min
Max
1.5
6.5
1.0
5.0
Fig. Units No.
ns 2-3
4-44
~National
D Semiconductor
54F/74F38 Quad Two-Input NANO Buffer ��
(Open Collector)
General Description
This device contains tour independent gates, each of which performs the logic NANO function. The open-collector outputs require external pull-up resistors for proper logical operation.
Ordering Code: see sections Logic Symbol
Connection Diagrams
IEEE/I EC
Pin Assignment
Ao
&: I>
for DIP, SOIC and Flatpak
{2
Oo
Bo
A1
e,
o,
Ao Bo
14 Vee
A2
A2
Oo
82
82
02
A1
02
A5 83
81
03
o,
A5 83
GND
03
TL/F /9465-3
TL/F/9465-1
Unit Loading/Fan Out: See Section 2 for U.L. definitions
Pin Names
Description
An,Bn On
Inputs Outputs
�oc = Open Collector
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loHllOL
1.0/2.0 OC*/106.6 (80)
20 �A/-1.2 mA OC* /64 mA (48 mA)
Function Table
Inputs
A
8
Output
0
L
L
H
L
H
H
H
L
H
H
H
L
H = HIGH Voltage Level L = LOW Voltage Level
Pin Assignment for LCC
rBn1:rNnC:rnA::1i
NC
rn
Oo
m
01rn
GND (@] NC [j]
03 li1.J
83 trn
ill Bo ill Ao
[!]NC
~Vee IJ]JA2
H] ~ lrn IIZl [�]
A5NC02NC~
TL/F/9465-2
4-45
Absolute Maximum Ratings (Note 1>
If Miiitary/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to + 7.0V
Input Voltage (Note 2) Input Current (Note 2)
-0.5Vto +7.0V
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5V to Vee -0.5V to +5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�c 0�cto +70�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
V1H
Input HIGH Voltage
V1L
Input LOW Voltage
Veo
Input Clamp Diode Voltage
54F/74F
Units Vee
Min Typ Max
Conditions
2.0
v
Recognized as a HIGH Signal
0.8
v
Recognized as a LOW Signal
-1.2
v
Min l1N = -18mA
VoL
Output LOW
Voltage
54F 10% Vee 74F 10% Vee
0.55
v
Min loL = 48 mA
0.55
loL = 64 mA
l1H
Input HIGH
54F
Current
74F
20.0
�A
Max V1N = 2.7V
5.0
lsv1
Input HIGH Current 54F
Breakdown Test
74F
100
�A
Max V1N = 7.0V
7.0
V10
Input Leakage
74F
4.75
Test
v
0.0 lio=1.9�A
All Other Pins Grounded
loo
Output Leakage
Circuit Current
74F
3.75
�A
0.0
V100 = 150 mV All Other Pins Grounded
l1L
Input LOW Current
-1.2 mA Max V1N = 0.5V
loHe
Open Collector, Output OFF Leakage Test
250
�A
Min VouT =Vee
leeH
Power Supply Current
2.1
7.0
mA Max Vo= HIGH
leeL
Power Supply Current
26.0 30.0
mA Max Vo= LOW
4-46
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
tPLH
Propagation Delay
tPHL
An. Bn to On
74F
TA= +25�C Vee= +5.0V
CL= 50 pf
Min
Typ
Max
6.5
9.7
12.5
1.0
2.1
5.0
54F
TA, Vee= Mii CL= 50pF
Min
Max
6.5
14.5
1.0
5.5
74F
TA, Vee= Com CL= 50 pf
Min
Max
6.5
13.0
1.0
5.5
Fig. Units No.
ns
2-3
4.47
D~NaStemiicoonnduactlor
54F/74F40 Dual 4~1nput NANO Buffer
General Description
This device contains two independent gates, each of which performs the logic NANO function.
Ordering Code: see section 5 Logic Symbol
Connection Diagrams
IEEE/I EC &: I>
Ao Bo Co Do
Pin Assignment for DIP, SOIC and Flatpak
A1
e, TL/F/9466-1
c, o,
TL/F/9466-3
Unit Loading/Fan Out: See Section 2 for U.L. definitions
Pin Names
An. Bn, Cn, Dn On
Description
Inputs Outputs
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loH/loL
1.0/2.0 600/106.6 (80)
20 �A/-1.2 mA -12 mA/64 mA (48 mA)
Function Table
Inputs
A
B
c
D
L
x
x
x
x
L
x
x
x
x
L
x
x
x
x
L
H
H
H
H
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
Output
0
H H H H L
Pin Assignment for LCC
Do NC Co NC NC
[[) mrn rn rn
Oo [[) GND IIQI NC lTIJ
o,~
o, ll]
rne0
[]]Ao O]NC ~Vee IIIDA1
liJ]li]][�]IIZJ[ID
c1 NC NC NC B1
TL/F/9466-2
4-48
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to+ 7.0V
Input Voltage (Note 2)
-0.5V to+ 7.0V
Input Current (Note 2)
-30 mA to + 5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5VtoVee - 0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
Input HIGH Voltage
Input LOW Voltage
Veo
Input Clamp Diode Voltage
54F/74F Min Typ Max
Units Vee
Conditions
2.0
v
Recognized as a HIGH Signal
0.8
v
Recognized as a LOW Signal
-1.2
v
Min l1N = -18 mA
Output HIGH Voltage
54F 10% Vee 2.4
54F 10% Vee 2.0
74F 10% Vee 2.4
74F 10% Vee 2.0
74F5% Vee
2.7
loH = -3mA
loH = -12mA
v
Min loH = -3mA
loH = -15mA
loH = -3mA
Output LOW Voltage
54F 10% Vee 74F 10% Vee
0.55 0.55
v
Im= 48 mA Min loL = 64 mA
Input HIGH
54F
Current
74F
20.0
�A
Max V1N = 2.7V
5.0
lsvr
Input HIGH Current 54F
Breakdown Test
74F
100 7.0
�A
Max V1N = 7.0V
leEx
Output High
54F
Leakage Current
74F
250
�A
Max VouT =Vee
50
V10
Input Leakage
74F
4.75
Test
v
0.0
110 = 1.9 �A
All Other Pins Grounded
loo
Output Leakage
74F
Circuit Current
3.75
�A
0.0 V100 = 150mV All Other Pins Grounded
Input LOW Current
los
Output Short-Circuit Current
-100
-1.2 mA Max V1N = 0.5V
-225 mA Max VouT = ov
leeH
Power Supply Current
1.6
4.0
mA Max Vo= HIGH
leeL
Power Supply Current
13.0 17.0
mA Max Vo= LOW
4-49
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
tPLH
Propagation Delay
tpHL
An, Bn, Cn, Dn to On
74F
TA= +25�c Vee= +5.0V
CL= 50pF
Min
Typ
Max
2.0
3.0
6.0
1.5
2.5
5.0
54F
TA, Vee= Mil CL= 50 pF
Min
Max
74F
TA, Vee= Com CL= 50 pF
Min
Max
1.5
7.0
1.0
5.5
Units Fig. No.
ns 2-3
4-50
~National
U Semiconductor
54F/74F51
2-2-2-3 AND-OR-Invert Gate
General Description
This device contains two independent logic units, one performing a 2-2 AND-OR-INVERT and the other performing a 3-3 AND-OR-INVERT function.
Ordering Code: see section 5 Logic Symbol
Connection Diagrams
IEEE/I EC
Ao
<!::: 1
&
Bo
Co
60
Do &
Eo
Fo
<!::: 1
A1
&
B1 61
C1
&
D1
TL/F/9468-4
Pin Assignment for DIP, SOIC and Flatpak
Ao A1 B1 C1 D1 01 GND
TL/F/9468-2
Pin Assignment for LCC
D1 NC C1 NC B1
rn rn rn rn rn
01 [[] GND [QI NC [j]
60 li1l
Do Ii]
LlJA1 [IJ Ao [I] NC
@Vee [j]]Co
I)]] [j]] li]J [j] Ii]]
to NC Fo NC Bo
TL/F/9468-1
Unit Loading/Fan Out: See Section 2 for u.L. definitions
Pin Names
An, Bn, Cn, Dn, En, Fn On
Description
Inputs Outputs
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loH/loL
1.0/1.0 50/33.3
20 �A/-0.6 mA -1 mA/20 mA
Function Table for 3-lnput Gates
Inputs
Output
Ao Bo Co Do Eo Fo
Bo
H H H xxx
L
xx x H HH
L
Ali other combinations
H
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
Function Table for 2-lnput Gates
Inputs
Output
A1
81
C1
D1
01
H
H
x
x
L
x
x
H
H
L
Ali other combinations
H
4-51
.,...
Lt)
Absolute Maximum Ratings (Note 1>
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 15o�c
Ambient Temperature under Bias
- 55�C to + 125�c
Junction Temperature under Bias
- 55�C to + 175�C
Vcc Pin Potential to Ground Pin
-0.5V to + 7.0V
Input Voltage (Note 2)
-0.5Vto +7.0V
Input Current (Note 2)
- 30 mA to + 5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5VtoVcc -0.5Vto +5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C
o�cto +1o�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
V1H V1L Vco VoH
Vol
l1H
lsv1
lcEx
V10
loo
l1L las lccH lccL
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 74F 10% Vee 74F5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage 74F
Test
Output Leakage 74F
Circuit Current
Input LOW Current
Output Short-Circuit Current
Power Supply Current
Power Supply Current
54F/74F Min Typ Max 2.0
0.8 -1.2 2.5 2.5 2.7 0.5 0.5 20.0 5.0 100 7.0 250
50
4.75
3.75
-0.6
-60
-150
1.9
3.0
5.3
8.5
Units v v v
v
v
�A
�A
�A
v
�A mA mA mA mA
Vee
Min Min
Min Max Max Max 0.0 0.0 Max Max Max Max
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal l1N = -18 mA loH = -1 mA loH = -1 mA loH = -1 mA loL = 20 mA loL = 20 mA
V1N = 2.7V
V1N = 7.0V
Vour =Vee
110 = 1.9 �A All other pins grounded V100 = 150 mV All other pins grounded V1N = 0.5V Vour = ov Vo= HIGH Vo= LOW
4-52
.U..1.. AC Electrical Characteristics: See Section 2 for waveforms and Load Configurations
Symbol
Parameter
tpLH
Propagation Delay
tPHL
An, Bn, Cn, Dn, En, Fn to On
74F
TA= +25�C Vee= +s.ov
CL= 50pF
Min
Typ
Max
2.0
3.7
6.0
1.0
2.6
4.0
54F
TA, Vee= Mii CL= 50pF
Min
Max
74F
TA, Vee= Comm CL= 50pF
Units
Fig. No.
Min
Max
1.5 1.0
6.5 4.5
ns 2-3
4-53
U~NaStemiicoonnduactlor
54F/74F64
4-2-3-2-lnput AND-OR-Invert Gate
General Description
This device contains gates configured to perform a 4-2-3-2 input AND-OR-INVERT function.
Ordering Code: see section 5 Logic Symbol
Connection Diagrams
I E E E / I EC
Pin Assignment for DIP, SOIC and Flatpak
Ao~t-----.
A2__....t--....., 8 2 - - - -.... A1 81 C1 GND
TL/F/9467-2
Pin Assignment for LCC
rBn1
mNC A1 [[!
NC
rn
82
rn
C1 [[] ----. ,,__. GND [QI
NC Ii]
o@
83 lill
[IJA2
[IJAo O]NC ~Vee [j] Bo
jg] [�]Ii]] IIZl Ml A3 NC Do NC Co
TL/F/9467-1
TL/F/9467-3
Unit Loading/Fan Out: See Section 2 for U.L. Definitions
Pin Names
An, Bn, Cn, Dn
0
Description
Inputs Output
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loHlloL
1.0/1.0 50/33.3
20 �A/-0.6 mA -1 mA/20 mA
4-54
Absolute Maximum Ratings (Note 1)
If Miiitary/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�c
Ambient Temperature under Bias
- 55�C to + 125�c
Junction Temperature under Bias
-55�C to+ 175�C
Vee Pin Potential to Ground Pin
-0.5V to + 7.0V
Input Voltage (Note 2)
-0.5V to+ 7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Yee = OV) Standard Output TAI-STATE� Output
-0.5VtoVee -0.5V to + 5.5V
Current Applied to Output
in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
-55�C to+ 125�c 0�cto +70�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol V1H V1L Yeo VoH
VoL
lrH
lsvr
leEX
Yro
loo
lrL los leeH leeL
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 74F 10% Yee 74F5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Yee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Output High
54F
Leakage Current
74F
Input Leakage 74F
Test
Output Leakage
Circuit Current
74F
Input LOW Current
Output Short-Circuit Current
Power Supply Current
Power Supply Current
54F/74F Min Typ Max 2.0
0.8 -1.2 2.5 2.5 2.7 0.5 0.5 20.0 5.0 100 7.0 250 50
4.75
3.75
-0.6
-60
-150
1.9
2.8
3.1
4.7
Units
v v v v
v
�A
�A
�A
v
�A mA mA mA mA
Vee
Min Min
Min Max Max Max 0.0 0.0 Max Max Max Max
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal l1N = -18 mA loH = -1 mA loH = -1 mA loH = -1 mA Im= 20 mA loL = 20 mA V1N = 2.7V
Y1N = 7.0V
Your= Vee
110 = 1.9 �A All Other Pins Grounded Yroo = 150 mV All Other Pins Grounded V1N = 0.5V
Your= ov
Vo= HIGH Vo= LOW
4-55
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
tpLH
Propagation Delay
tPHL
An, Bn, Cn, Dn to 0
74F
TA= +25�C Vee= +s.ov
CL= 50pf
Min
Typ
Max
2.5
4.6
6.5
1.5
3.2
4.5
54F
TA, Vee= Mii CL= 50pf
Min
Max
2.5
8.5
1.5
6.5
74F
TA, Vee= Com CL= 50pf
Min
Max
2.5
7.5
1.5
5.5
Fig. Units No.
ns 2-3
4-56
~National
U Semiconductor
54F/74F74 Dual D-Type Positive Edge-Triggered Flip-Flop
General Description
The 'F74 is a dual D-type flip-flop with Direct Clear and Set inputs and complementary (Q, 0) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input.
Asynchronous Inputs:
LOW input to So sets Q to HIGH level LOW input to Co sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on Co and So makes both Q and Q HIGH
Features
� Guaranteed 4000V minimum ESD protection
Ordering Code: See sections Logic Symbols
o, So1 o,
TL/F/9469-3
TL/F/9469-4
I E E E / I EC
So1
CP1 c, o,
Co1 So2 CP2 02 Co2
o,
a,
02 02
TL/F/9469-6
Connection Diagrams
Pin Assignment for DIP, SOIC, and Flatpak
Co1......,..___ __
o,
CP 1 So1
o,
a,
GNO
TL/F/9469-1
Pin Assignment for LCC
01 NC S01 NC CP1 [[l[ZJ[[l@JGJ
a, rn
GND [Q]
NCITI]
02 ll1l
02 [jl]
rno,
l1l Co1
[I] NC ~Vee [j]] Co2
~ [j] 11]) !Ill [j]]
So2 NC CP2 NC 02
TL/F/9469-2
4.57
Unit Loading/Fan Out: See Section 2 tor U.L. definitions
Pin Names
D1,D2 CP1, CP2 Co1. Co2 801. 802 01. 01. 02. 02
Description
Data Inputs Clock Pulse Inputs (Active Rising Edge) Direct Clear Inputs (Active LOW) Direct Set Inputs (Active LOW) Outputs
54F/74F
U.L.
Input l1Hll1L
HIGH/LOW Output loHllOL
1.0/1.0 1.0/1.0 1.0/3.0 1.0/3.0 50/33.3
20 �A/-0.6 mA 20 �A/-0.6 mA 20 �Al-1.8 mA 20 �A/-1.8 mA -1 mA/20 mA
Truth Table
Inputs
Outputs
So Co
CP
D
Q
Q
L
H
x
x
H
L
H
L
x
x
L
H
L
L
x
x
H
H
H
H
_/
h
H
L
H
H
_/
I
L
H
H
H
L
x Oo Oo
Logic Diagram
H (h) = HIGH Voltage Level L (I) = LOW Voltage Level
X = Immaterial
Oo = Previous Q (Q) before LOW-to-HIGH Clock Transition
Lower case letters indicate the state of the referenced input or output one setup time prior to the LOW-to-HIGH clock transition.
Q
D
CP
........... so~~~~~~
~~~~-t-~~~~~~~~~~
Co~~~~~~~~~~~~--~~~~~~~~~~~~~~~~~~-
TL/F/9469-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-58
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
-55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to + 7.0V
Input Voltage (Note 2)
-0.5V to + 7.0V
Input Current (Note 2)
-30 mA to + 5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5VtoVee -0.5V to+ 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
ESD Last Passing Voltage (Min)
4000V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol V1H V1L Veo VoH
VoL l1H lsv1 leEX V10 loo l1L los Ice
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 74F 10% Vee 74F5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage 74F
Test
Output Leakage 74F
Circuit Current
Input LOW Current
Output Short-Circuit Current Power Supply Current
54F/74F Min Typ Max 2.0
0.8 -1.2 2.5 2.5 2.7 0.5 0.5 20.0 5.0 100 7.0 250 50
4.75
-60
10.5
3.75
-0.6 -1.8 -150 16.0
Units
v v v v
v
�A
�A
�A
v
�A
mA mA mA
Vee
Min Min Min Max Max Max 0.0 0.0 Max Max Max
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal l1N = -18mA loH = -1 mA loH = -1 mA loH = -1 mA loL = 20 mA loL = 20 mA
V1N = 2.7V
V1N = 7.0V
VouT =Vee
110 = 1.9 �A All Other Pins Grounded V100 = 150 mV All Other Pins Grounded V1N = 0.5V V1N = 0.5V
VouT = ov
4-59
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
fmax
tPLH tPHL
tPLH tPHL
Maximum Clock Frequency
Propagation Delay CPn to On or On Propagation Delay Con or Son to On or On
74F
TA= +25�c Vee= +5.0V
CL= 50 pF
Min
Typ
Max
100
125
3.8
5.3
6.8
4.4
6.2
8.0
3.2
4.6
6.1
3.5
7.0
9.0
54F
TA, Vee= Mil CL= 50 pF
Min
Max
50
3.8
8.5
4.4
10.5
3.2
8.0
3.5
11.5
74F
TA, Vee= Com CL= 50 pF
Min
Max
100
3.8
7.8
4.4
9.2
3.2
7.1
3.5
10.5
Fig. Units No.
MHz 2-1 ns 2-3 ns 2-3
AC Operating Requirements: See Section 2 for Waveforms
Symbol
Parameter
t 5(H) t5 (L) th(H) th(L) tw(H) tw(L) tw(L)
tree
Setup Time, HIGH or LOW Dn to CPn
Hold Time, HIGH or LOW Dn toCPn
CPn Pulse Width HIGH or LOW
' Con or Son Pulse Width LOW
Recovery Time Con or Son to CP
74F
TA= +25�C Vee= +5.0V
Min
Max
2.0 3.0
1.0 1.0
4.0 5.0
4.0
2.0
54F
TA, Vee= Mil
Min
Max
3.0 4.0
2.0 2.0
4.0 6.0
4.0
3.0
74F
TA, Vee= Com
Min
Max
2.0 3.0
1.0 1.0
4.0 5.0
4.0
Units
Fig. No.
ns
2-6
2-4 ns
ns
2-4
2.0
ns
2-6
4-60
CIO O'>
~National
U Semiconductor
54F/74F86
2-lnput Exclusive-OR Gate
General Description
This device contains four independent gates, each of which performs the logic exclusive-OR function.
Ordering Code: see section 5 Logic Symbol
Connection Diagrams
I E E E / I EC
Pin Assignment for
Pin Assignment
DIP, SOIC and Flatpak
Ao
2::1
Oo
Bo
Ao
Vee
for LCC
B1 NC A1 NC 00 [ID[ZJl]J[[]GJ
Al
01
Bo
A2
Bl
Oo
B2
01 [[]
[IIB0
A2 B2 A3
02
Al
Bl
03
01
GND [�]
02
NC [j]
A3
03 li1J
B3
B3 I!]
ill Ao
[!]NC
gg Vee
[j]]A2
B3
GND
03
TL/F/9470-3
TL/F/9470-2
li]~IJ][il][j]J
A3 NC 02 NC B2
TL/F/9470-1
Unit Loading/Fan Out: See Section 2 tor U.L. definitions
Pin Names
An, Bn On
Description
Inputs Outputs
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loHlloL
1.0/1.0 50/33.3
20 �A/-0.6 mA -1 mA/20 mA
4-61
Absolute Maximum Ratings (Note 1)
If MilitaryI Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vcc Pin Potential to Ground Pin
-0.5Vto +7.0V
Input Voltage (Note 2)
-0.5Vto +7.0V
Input Current (Note 2)
- 30 mA to + 5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5V to Vee -0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C o�cto +10�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
V1H
Input HIGH Voltage
V1L
Input LOW Voltage
Vco
Input Clamp Diode Voltage
54F/74F Min Typ Max
Units Vee
Conditions
2.0
v
Recognized as a HIGH Signal
0.8
v
Recognized as a LOW Signal
-1.2
v
Min l1N= -18mA
VoH
Output HIGH
Voltage
54F 10% Vee 2.5
74F 10% Vee 2.5
74F 5% Vee
2.7
loH = -1 mA
v
Min loH = -1 mA
loH = -1 mA
VoL
Output LOW
Voltage
54F 10% Vee 74F 10% Vee
0.5 0.5
v
Min loL = 20mA
loL = 20 mA
l1H
Input HIGH
54F
Current
74F
20.0
5.0
�A Max V1N = 2.7V
lsv1
Input HIGH Current 54F
Breakdown Test
74F
100
7.0
�A Max V1N = 7.0V
lcEx
Output HIGH
54F
Leakage Current
74F
250 50
�A
Max VouT =Vee
V10
Input Leakage
74F
4.75
Test
v
0.0 110 = 1.9 �A
All other pins grounded
loo
Output Leakage
Circuit Current
74F
3.75
�A
0.0 V100 = 150mV
All other pins grounded
l1L
Input LOW Current
los
Output Short-Circuit Current
-0.6
mA Max V1N = 0.5V
-60
-150 mA Max VouT = ov
lccH
Power Supply Current
12
18
mA Max Vo= HIGH
lccL
Power Supply Current
18
28
mA Max Vo= LOW
4-62
AC Electrical Characteristics: See Section 2 for waveforms and Load Configurations
Symbol
Parameter
tpLH tPHL
tPLH tpHL
Propagation Delay An, Bn to On (Other Input LOW)
Propagation Delay An, Bn to On (Other Input HIGH)
74F
TA= +25�C Vee= +5.0V
CL= 50 pf
Min
Typ
Max
3.0
4.0
5.5
3.0
4.2
5.5
3.5
5.3
7.0
3.0
4.7
6.5
54F
TA, Vee= Mil CL= 50 pf
Min
Max
2.5
7.0
3.0
7.0
3.5
8.5
3.0
8.0
74F
TA, Vee= Com CL= 50 pf
Min
Max
3.0
6.5
3.0
6.5
3.5
8.0
3.0
7.5
(X)
a>
Fig. Units
No.
ns 2-3 ns 2-3
4-63
O>
0...... ~National
~Semiconductor
54F/74F109 Dual JK Positive Edge-Triggered Flip-Flop
General Description
The 'F109 consists of two high-speed, completely indepen-
dent transition clocked JK flip-flops. The clocking operation
is independent of rise and fall times of the clock waveform.
The JK design allows operation as a D flip-flop (refer to 'F74 data sheet) by connecting the J and K inputs.
Asynchronous Inputs:
LOW input to So sets Q to HIGH level LOW input to Co sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on Co and So makes both Q and Q
HIGH
Features
� Guaranteed 4000V minimum ESD protection.
Ordering Code: See sections Logic Symbols
So1
J1
01
eP1 K1
TL/F/9471-3
So2
J2
02
eP2 K2
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
Co1
J1
K1
K1
4 CP1
CP 1
5
So1
So1
o, o,
o,
GND
16 Vee 15 Co2 14 J2 K2 13 K2 CP2 12 CP2 11 -
So2 10 0 9 _2
02
TL/F /9471-1
Pin Assignment forLCC
01 So1 NC CP1 K1
!ID IIl [[) @] ill
011Il GND liQI
NC [i]
02 lrn
02 U]
l11J1
III Co1
[i]NC
WI Vee ~Co2
Ii] Ii]] liID liZl [ID SozCP2NC Kz .lz
TL/F/9471-2
, TL/F/9471-4
IEEE/IEC
501
JI
01
eP 1
K1
01
Co1
So2
J2
02
eP2
K2
02
Co2
TL/F/9471-6
4-64
.....
0
Unit Loading/Fan Out: See Section 2 for u.L. definitions
(0
Pin Names
J1.h R1. K2 CP1, CP2 Co1. Co2 801. So2 01, 02. 01, 02
Description
Data Inputs Clock Pulse Inputs (Active Rising Edge) Direct Clear Inputs (Active LOW) Direct Set Inputs (Active LOW) Outputs
54F/74F
U.L.
Input l1HlllL
HIGH/LOW Output loHlloL
1.0/1.0 1.0/1.0 1.0/3.0 1.0/3.0 50/33.3
20 �A/-0.6 mA 20 �Al - 0.6 mA 20 �A/-1.8 mA 20 �Al -1 .8 mA -1 mA/20mA
Truth Table
Inputs
Outputs
So Co
CP
J
K
Q
Q
L
H
x xx H
L
H
L
x xx L H
L
L
x xx H H
H
H
_/
I
I
L
H
H
H
_/
h
I
Toggle
H
H
_/
I
h Oo Oo
H
H
_/
h
h
H
L
H
H
L x x Oo Oo
H (h) = HIGH Voltage Level
L (I) = LOW Voltage Level .../" = LOW-to-HIGH Transition X = Immaterial
Oo (Oo) = Before LOW-to-HIGH Transition of Clock
Lower case letters indicate the state of the referenced output one setup time
prior to the LOW-to-HIGH clock transition.
Logic Diagram (One Half Shown)
Q
CP
so~~~~~~~~~~--~~~~~~-1-~~~~~~~~_,
.... Co~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~-
TL/F/9471-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-65
en
,0.... Absolute Maximum Ratings (Note 1>
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to + 7.0V
Input Voltage (Note 2)
-0.5Vto +7.0V
Input Current (Note 2)
-30 mA to+ 5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5VtoVec -0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
ESD Last Passing Voltage (Min)
4000V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol V1H V1L Vco VoH
VoL l1H lsv1 lcEx V10 loo l1L los Ice
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 74F 10% Vee 74F5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage 74F
Test
Output Leakage 74F
Circuit Current
Input LOW Current
Output Short-Circuit Current Power Supply Current
54F/74F Min Typ Max 2.0
0.8 -1.2 2.5 2.5 2.7 0.5 0.5 20.0 5.0 100 7.0 250
50
4.75
-60
11.7
3.75
-0.6 -1.8 -150 17.0
Units
v v v v
v
�A
�A
�A
v
�A mA mA mA mA
Vee
Min Min
Min Max Max Max 0.0 0.0 Max Max Max Max
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal l1N = -18 mA loH = -1 mA loH = -1 mA loH = -1 mA loL = 20 mA loL = 20mA V1N = 2.7V
V1N = 7.0V
Vour =Vee
110 = 1.9 �A All Other Pins Grounded V100 = 150 mV All Other Pins Grounded V1N = 0.5V <Jn. Kn) V1N = 0.5V (Con. Son)
Vour = ov
CP = OV
4-66
......
0
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
CD
Symbol
Parameter
fmax
tPLH tPHL
tPLH tPHL
Maximum Clock Frequency
Propagation Delay CPn to On or On
Propagation Delay Con or Son to On or On
74F
TA= +25�c Vee= +5.0V
CL= 50 pF
Min
Typ
Max
100
125
3.8
5.3
7.0
4.4
6.2
8.0
3.2
5.2
7.0
3.5
7.0
9.0
54F
TA, Vee= Mil CL= 50 pF
Min
Max
50
3.8
9.0
4.4
10.5
3.2
9.0
3.5
11.5
74F
TA, Vee= Com CL= 50 pF
Fig. Units
No.
Min
Max
90
MHz 2-1
3.8
8.0
ns 2-3
4.4
9.2
3.2
8.0
ns 2-3
3.5
10.5
AC Operating Requirements: see Section 2 for waveforms
Symbol
Parameter
t5 (H) t5 (L) th(H) th(L) tw(H) tw(L) tw(L)
tree
Setup Time, HIGH or LOW Jn or Kn to CPn
Hold Time, HIGH or LOW Jn or Kn to CPn
CPn Pulse Width HIGH or LOW
Con or Son Pulse Width, LOW
Recovery Time Con or Son to CP
74F
TA= +25�C Vee= +5.0V
Min
Max
3.0 3.0
1.0 1.0
4.0 5.0
4.0
2.0
54F
TA, Vee= Mil
Min
Max
3.0 5.0
1.0 1.0
4.0 5.0
4.0
2.0
74F
TA, Vee= Com
Min
Max
3.0 3.0
1.0 1.0
4.0 5.0
4.0
Units Fig. No.
ns
2-6
ns
2-4
ns
2-4
2.0
ns
2-6
4-67
.N....
~National
~Semiconductor
54F/74F112
Dual JK Negative Edge-Triggered Flip-Flop
General Description
The 'F112 contains two independent, high-speed JK flipflops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J and K inputs can change when the clock is in either state without affecting the flip-flop, provided that they are in the desired state dur- � ing the recommended setup and hold times relative to the
falling edge of the clock. A LOW signal on So or Co prevents clocking and forces Q or Q HIGH, respectively. Simul-
a taneous LOW signals on So and Co force both and 0
HIGH.
Asynchronous Inputs:
LOW input to So sets Q to HIGH level LOW input to Co sets Q to LOW level
Clear and Set are independent of clock
a Simultaneous LOW on Co and So makes both
and Q HIGH
Ordering Code: see section 5 Logic Symbols
So1
J1
01
CP 1
K1
01
Co1
TL/F/9472-3
I E E E / I EC
So1
JI
a,
CP1
c,
K1
Co1
So2
J2
Cfi2
K2
Co2
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
TL/F/9472-4
Cfi,-----.
K1 J,
So1
a,
o,
02
GND
Pin Assignment for LCC
01 ffil
m01 mNc
%rn11J111
TL/F/9472-1
TL/F/9472-6
02l1l
GND [Q] NC[j]
02 [gj So2 []]
!1JK1
l1J CP1
O]NC ~Vee [j] Co1
18J~[ffill]~
J2 K2 NC Cii2 ~
TL/F/9472-2
4-68
Unit Loading/Fan Out: See Section 2 tor U.L. definitions
Pin Names
J1, J2, K1, K2 CP1 1 CP2 Co1. Co2 801. 802 01. 02. 01, 02
Description
Data Inputs Clock Pulse Inputs (Active Falling Edge) Direct Clear Inputs (Active LOW) Direct Set Inputs (Active LOW) Outputs
54F/74F
U.L. HIGH/LOW
Input l1HlllL Output loHlloL
1.0/1.0 1.0/4.0 1.0/5.0 1.0/5.0 50/33.3
20 �A/ - 0.6 mA 20 �A/ - 2.4 mA 20 �Al -3.0 mA 20 �A/ - 3.0 mA -1 mA/20 mA
Truth Table
Inputs
Outputs
So Co
CP
J
K
Q
Q
L
H
H
L
L
L
x
xx H
L
x
x x
L
H
x
xx H
H
H
H """"'-- h h Oo Oo
H
H """"'-- I h
L
H
H
H """"'-- h I
H
L
H
H """"'-- I
I Oo Oo
Logic Diagram (One Halt Shown)
H(h) = HIGH Voltage Level
L(I) = LOW Voltage Level X = Immaterial
' - = HIGH-to-LOW Clock Transition Oo(Oo) = Before HIGH-to-LOW Transition of Clock
Lower case letters indicate the state of the referenced input or output one setup time prior to the HIGH-to-LOW clock transition.
Co~~~~~~~~.......~---1
. . . . J~~~~~~~~
~~---1
t--~.....~~~~~~~~~so
t--~~~~~~~~~~~K
TL/F/9472-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-69
,,N...... Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to + 7.0V
Input Voltage (Note 2)
-0.5V to + 7.0V
Input Current (Note 2)
-30 mA to + 5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5V to Vee -0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Veo VoH
Vol
lsv1 le EX
loo
los lceH leeL
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 74F 10% Vee 74F5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage 74F
Test
Output Leakage 74F
Circuit Current
Input LOW Current
Output Short-Circuit Current Power Supply Current Power Supply Current
54F/74F Min Typ Max 2.0
0.8 -1.2 2.5 2.5 2.7 0.5 0.5 20.0 5.0 100 7.0 250
50
4.75
3.75
-0.6 -2.4 -3.0
-60
-150
12
19
12
19
Units
v v v
v
v
�A �A �A
v
�A
mA
mA mA mA
Vee
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal Min l1N = -18 mA loH = -1 mA Min loH = -1 mA loH = -1 mA Min loL = 20 mA loL = 20 mA
Max V1N = 2.7V
Max V1N = 7.0V
Max VouT =Vee
0.0 llD = 1.9 �A
All other pins grounded 0.0 V100 = 150 mV
All other pins grounded V1N = 0.5V (Jn, Kn) Max V1N = 0.5V (CPn) V1N = 0.5V (Con. Son)
Max VouT = ov
Max Vo= HIGH Max Vo= LOW
4-70
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
fmax
Maximum Clock Frequency
tPLH
Propagation Delay
tPHL
CPn to On or On
tPLH
Propagation Delay
tPHL
Con. Son to On. On
74F
TA= +25�C Vee= +5.0V
CL= 50 pf
Min
Typ
Max
85
105
2.0
5.0
6.5
2.0
5.0
6.5
2.0
4.5
6.5
2.0
4.5
6.5
54F
TA, Vee= Mil CL= 50 pf
Min
Max
74F
TA, Vee= Com CL= 50 pf
Min
Max
80
2.0
7.5
2.0
7.5
2.0
7.5
2.0
7.5
Fig. Units
No.
MHz 2-1 ns 2-3 ns 2-3
AC Operating Requirements: See Section 2 for Waveforms
Symbol
Parameter
t5 (H) t5 (L) th(H) th(L) tw(H) tw(L) tw(L)
tree
Setup Time, HIGH or LOW Jn or Kn to CPn
Hold Time, HIGH or LOW Jn or Kn to CPn
CP Pulse Width HIGH or LOW
Pulse Width, LOW Con or Son Recovery Time Son. Con to CP
74F
c TA= +2s0
Vee= +5.0V
Min
Max
4.0 3.0
0 0
4.5 4.5
4.5
4.0
54F
TA, Vee= Mil
Min
Max
74F
TA, Vee= Com
Min
Max
5.0 3.5
0 0
5.0 5.0
5.0
5.0
Units Fig. No.
ns 2-6 ns 2-4 ns 2-4 ns 2-6
4-71
,,C...."..'..)
~National
~Semiconductor
54F/74F113
Dual JK Negative Edge..Triggered Flip-Flop
General Description
The 'F113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of the J and K inputs may be changed when the clock pulse is HIGH and the flip-flop will perform according to the Truth Table as long as minimum setup and hold times are observed. Input data is transferred to the outputs on the falling edge of the clock pulse.
Asynchronous input: LOW input to So sets 0 to HIGH level Set is independent of clock
Ordering Code: see section 5 Logic Symbols
Connection Diagrams
IEEE/I EC
501 J1 J1
ffi1 K1
So2 J2
ffi2 K2
01 01 02 02
TL/F/9473-6
Pin Assignment for . DIP, SOIC and Flatpak
Ki--.--+-. J1 501 01 01 GND
TL/F/9473-1
Pin Assignment for LCC
01 NC So1 NC J1
rn moo rn rn
01 (!] GND [Q]
NC !TI]
02 ll11 02 lrn ..,, r-~_ _J
[IIK1
!Ilffi1 [I]NC ~Vee !iIDffi2
li]~ll]][Z)ffID
SmNC ~NC K2
TL/F/9473-2
01
TL/F/9473-3
TL/F/9473-4
Unit Loading/Fan Out: see Section 2 for u.L. Definitions
Pin Names
J1, J2, K1, K2 CP1. CP2 801. So2 01. 02. 01. 02
Description
Data Inputs Clock Pulse Inputs (Acitve Falling Edge) Direct Set Inputs (Active LOW) Outputs
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loHlloL
1.0/1.0 1.0/4.0 1.0/5.0 50/33.3
20 �Al -0.6 mA 20 �Al - 2.4 mA 20 �Al -3.0 mA -1 mA/20 mA
4-72
Truth Table
Inputs
Outputs
So
CP
J
K
Q
a
L
x
x x
H
L
H
""""'--
h
h
Cio
Oo
H
""""'--
I
h
L
H
H
""""'--
h
I
H
L
H
""""'--
I
I
Oo Oo
Logic Diagram (One Halt Shown)
............
w
H(h) = HIGH Voltage Level L(I) = LOW Voltage level "'"'\._ = HIGH-to-LOW Clock Transition
X = Immaterial Oo (00) = Before HIGH-to-LOW Transition of
Clock Lower case letters indicate the state of the referenced input or output prior to the HIGH-to-LOW clock transition.
0
1-~-t1-~~~~~~~~~-so
t-~~~~~~~~~~~~-K
TL/F/9473-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-73
C,,....f..) Absolute Maximum Ratings (Note 1>
If MilitaryI Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction. Temperature under Bias
- 55�C to + 175�C
Vcc Pin Potential to Ground Pin
-0.5V to + 7.0V
Input Voltage (Note 2)
-0.5V to + 7.0V
Input Current (Note 2)
-30 mA to + 5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5Vto Vee -0.5Vto +5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C o�cto +70�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol V1H V1L Yeo VoH
Vol l1H lsv1 lcEX V10 loo l1L
lozH lozL los Ice
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 74F 10% Vee 74F5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage 74F
Test
Output Leakage 74F
Circuit Current
Input LOW Current
Output Leakage Current Output Leakage Current Output Short-Circuit Current Power Supply Current
54F/74F .Min Typ Max
2.0 0.8 -1.2
2.5 2.5 2.7
0.5 0.5 20.0 5.0 100 7.0 250 50
4.75
3.75
-0.6 -2.4 -3.0
50
-50
-60
-150
12
19
Units
v
v v v
v �A �A �A v �A
mA �A �A mA mA
Vee
Min Min
Min Max Max Max 0.0 0.0
Max Max Max Max Max
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal l1N = -18mA loH = -1 mA loH = -1 mA loH = -1 mA loL = 20 mA loL = 20 mA V1N = 2.7V
V1N = 7.0V
Vour =Vee
110 = 1.9 �A All Other Pins Grounded V100 = 150 mV All Other Pins Grounded V1N = 0.5V (Jn, Kn) V1N = 0.5V (CPn) V1N = 0.5V (Son) Vour = 2.7V Vour = 0.5V Vour = ov
4-74
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
74F
TA= +25�C Vee= +5.0V
CL= 50 pF
Min
Typ
Max
54F
TA, Vee= Mii CL= 50 pF
Min
Max
74F
TA, Vee= Com CL= 50 pF
Min
Max
fmax
Maximum Clock Frequency
85
105
tpLH tpHL
Propagation Delay CPn to On or On
2.0
4.0
6.0
2.0
4.0
6.0
tpLH tpHL
Propagation Delay Son to On or On
2.0
4.5
6.5
2.0
4.5
6.5
80
2.0
7.0
2.0
7.0
2.0
7.5
2.0
7.5
Units Fig. No.
MHz 2-1 ns 2-3 ns 2-3
AC Operating Requirements: See Section 2 for Waveforms
Symbol
Parameter
t 5 (H) t5 (L) th(H) th(L)
tw(H) tw(L)
tw(L)
Setup Time, HIGH or LOW Jn or Kn to CPn Hold Time, HIGH or LOW Jn or Kn to CPn
CPn Pulse Width HIGH or LOW
Son Pulse Width, LOW
74F
TA= +25�c Vee= +5.0V
Min
Max
4.0 3.0
0 0
4.5 4.5
4.5
54F
TA, Vee= Mil
Min
Max
tree
Son toCPn
4.0
Recovery Time
74F
TA, Vee= Com
Min
Max
5.0 3.5
0 0
5.0 5.0
5.0
5.0
Units
Fig. No.
ns
2-6
ns
2-4
ns
2-4
ns
2-6
a
4-75
",,..l..l:..f..'
~DNaStemiicoonnduactlor
54F/74F114
Dual JK Negative Edge-Triggered Flip...flop with Common Clocks and Clears
General Description
The 'F114 contains two high-speed JK flip-flops with common Clock and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J and K inputs can change when the clock is in either state without affecting the flip-flop, provided that they are in the desired state during the recommended setup and hold times relative to the falling edge of
the clock. A LOW signal on So or Co prevents clocking and
forces Q or Q HIGH, respectively. Simultaneous LOW sig-
nals on So and Co force both Q and Q HIGH.
Asynchronous Inputs:
LOW input to So sets Q to HIGH level LOW input to Co sets Q to LOW level
Clear and Set are independent of Clock
Simultaneous LOW on Co and So
makes both Q and Q HIGH
Ordering Code: see sections Logic Symbols
Connection Diagrams
TL/F/9474-3
IEEE/I EC
Co
CP
So1 01
J1 01
K1 So2
02 J7
02 K7
TL/F/9474-5
Pin Assignment for DIP, SOIC and Flatpak
TL/F/9474-1
Pin Assignment
for LCC
01 NC Soi NC J1
I]] II] !]] [[] ill
G~~mo~~ ~~~
NC [j]
02 lilJ
J
.9
oif..i- o.J'_~
OJ NC
~Vee
02 l@I
li1I CP
[]}]!Imlffil[Z]ij]J
SmNC Ji NC !<i
TL/F/9474-2
4-76
Unit Loading/Fan Out: See Section 2 for U.L. definitions
Pin Names
J1.h K1, K2
CP
Co So1.So2 01. 02. 01. 02
Description
Data Inputs Clock Pulse Input (Active Falling Edge) Direct Clear Input (Active LOW) Direct Set Inputs (Active LOW) Outputs
54F/74F
U.L
Input l1H/l1L
HIGH/LOW Output loH/loL
1.0/1.0 1.0/8.0 1.0/10.0 1.0/5.0 50/33.3
20 �A/ - 0.6 mA 20 �A/ -4.8 mA 20 �Al -6.0 mA 20 �A/-3.0 mA -1 mA/20mA
Truth Table
Inputs
Outputs
So
Co
CP
J
K
Q
Q
L
H
x
x x
H
L
H
L
x
x x
L
H
L
L
x
x x
H
H
H
H
"""\.__
h
h
Oo
Oo
H
H
"""\.__
I
h
L
H
H
H
"""\.__
h
I
H
L
H
H
"""\.__
I
I
Oo
Oo
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial "'�'\... = HIGH-to-LOW Clock Transition
a0 (00) = Before HIGH-to-LOW Transition of Clock
Lower case letters indicate the state of the referenced input or output one setup time prior to the HIGH-to-LOW clock transition.
Logic Diagram <one half shown)
TL/F/9474-4 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-77
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
-65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to+ 7.0V
Input Voltage (Note 2)
-0.5V to +7.0V
Input Current (Note 2)
-30 mA to + 5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5VtoVee - 0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol V1H V1L Veo VoH
VoL l1H lsv1 leEX V10 loo l1L
los leeH leeL
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 74F 10% Vee 74F 5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Output High
54F
Leakage Current
74F
Input Leakage
Test
74F
Output Leakage
74F
Circuit Current
Input LOW Current
Output Short-Circuit Current Power Supply Current Power Supply Current
54F/74F Min Typ Max 2.0
0.8 -1.2 2.5 2.5 2.7 0.5 0.5 20.0 5.0 100 7.0 250
50
4.75
3.75
-0.6 -3.0 -8.0 -10.0
-60
-150
12.0 19.0
12.0 19.0
Units
v v v v
v
�A �A �A
v
�A
mA
mA mA mA
Vee
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal Min l1N = -18 mA loH = -1 mA Min loH = -1 mA loH = -1 mA Min loL = 20 mA loL = 20mA V1N = 2.7V Max
Max V1N = 7.0V
Max Vour =Vee
0.0 110 = 1.9 �A All Other Pins Grounded
0.0 V100 = 150 mV All Other Pins Grounded V1N = 0.5V (Jn, Kn)
Max V1N = 0.5V (Son) V1N = 0.5V (CP) V1N = 0.5V (Con)
Max Vour = ov
Max Vo= HIGH Max Vo= LOW
4-78
..........
AC Electrical Characteristics: See Section 2 tor Waveforms and Load Configurations
~
Symbol
Parameter
fmax
tPLH tPHL
tPLH tPHL
Maximum Clock Frequency
Propagation Delay CPto On or On
Propagation Delay Con or Son to On or On
74F
TA= +25�C Vee= +5.0V
CL= 50 pf
Min
Typ
Max
75
95
3.0
5.0
6.5
3.0
5.5
7.5
3.0
4.5
6.5
3.0
4.5
6.5
54F
TA, Vee= Mil CL= 50 pf
Min
Max
74F
TA, Vee= Com Units Fig.
CL= 50 pf
No.
Min
Max
70
MHz 2-1
3.0
7.5
ns 2-3
3.0
8.5
3.0
7.5
ns 2-3
3.0
7.5
AC Operating Requirements: SeeSection2forWaveforms
Symbol
Parameter
t5 (H) t5 (L) th(H) th(L) tw(H) tw(L) tw(L)
tree
Setup Time, HIGH or LOW Jn or Kn to CP
Hold Time, HIGH or LOW Jn or Kn to CP
CP Pulse Width HIGH or LOW
Con or Son Pulse Width, LOW
Recovery Time Son. Con. to CP
74F
c TA= +2s0
Vee= +5.0V
Min
Max
4.0 3.0
0 0
4.5 4.5
4.5
4.0
54F
TA, Vee= Mil
Min
Max
74F
TA, Vee= Com
Min
Max
5.0 3.5
0 0
5.0 5.0
5.0
Units
Fig. No.
ns
2-6
ns
2-4
ns
2-4
5.0
ns
2-6
4-79
~~SNemaitcoinoduncatolr
54F/74F125
Quad Buffer (TRI-STATE�)
Features
� High impedance base inputs for reduced loading
Ordering Code: see section 5 Logic Symbol
Connection Diagrams
IEEE/I EC
Bo
Ao
EN
B1
A1
B2
A2
B3
A3
t> 1 v
Oo
v 01
v 02
v 03
TL/F/9475-4
Pin Assignment for DIP, SOIC and Flatpak
Ao
Vee
Bo
A2
Oo
B2
A1
02
B1
A3
01
B3
GND
03
TL/F/9475-1
unit. Loading/Fan Out: See Section 2 for U.L. Definitions
Pin Names
An, Bn On
Description
Inputs Outputs
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loHllOL
1.0/0.033 600/106.6 (80)
20 �A/-20 �A -12 mA/64 mA (48 mA)
Pin Assignment for LCC
B1
!ID
NC A1
mrn
NC
rn
Oo
rn
01 []] GND [QJ
NC (j]
03 il]
B3 Im
mB0 mA0 [IJNC
~Vee
Ii]] A2
~ ll]J[�I IIZl!IID A3 NC 0i NC 8i
TL/F/9475-2
Function Table
Inputs
An
Bn
L
L
L
H
H
x
Output
0
L H
z
H = High Voltage Level L = LOW Voltage Level Z = High Impedance X = Immaterial
4-80
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to + 7.0V
Input Voltage (Note 2)
-0.5Vto +7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
-0.5VtoVee - 0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
V1H VrL Vco VoH
VoL
l1H lsv1
lrL lozH lozL los leEx lzz leeH lecL leez
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee 74F 5% Vee 74F5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH Current
Input HIGH Current Breakdown Test
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Output HIGH Leakage Current
Buss Drainage Test
Power Supply Current
Power Supply Current
Power Supply Current
54F/74F
Min Typ Max
2.0
0.8
-1.2
2.4 2.0 2.4 2.0 2.7 2.0
0.55 0.55
20
100
-100
18.5 31.7 27.6
-20.0 50 -50
-225 250 500 24.0 40.0 35.0
Units
v v v
v
v
�A �A �A �A �A mA �A �A mA mA mA
Vee
Min
Min
Min Max
o.ov
Max Max Max Max Max
o.ov
Max Max Max
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal l1N = -18 mA loH = -3 mA loH = -12 mA loH = -3 mA loH = -12 mA loH = -3 mA loH = -15mA loL = 48 mA loL = 64 mA VrN = 2.7V VrN = 7.0V
VrN = 0.5V VouT = 2.7V VouT = 0.5V
VouT = ov
VouT =Vee VouT = 5.25V Vo= HIGH Vo= LOW Vo= HIGHZ
.......
I\)
U1
a
4-81
II)
,N... AC Electrical Characteristics: See Section 2 for Waveforms and Load configurations
Symbol
Parameter
tPLH tPHL
tpzH tpzL
tpHz tpLZ
Propagation Delay Output Enable Time Output Disable Time
74F
TA= +25�c Vee= +5.0V
CL= 50pF
Min
Typ
Max
2.0
4.0
6.0
3.0
4.6
7.5
3.5
4.7
7.5
3.5
5.3
8.0
1.5
3.9
5.5
1.5
4.0
6.0
54F
TA, Vee= Mii CL= 50pF
Min
Max
74F
TA, Vee= Com CL= 50 pF
Min
Max
2.0
6.5
3.0
8.0
3.0
8.5
3.5
9.0
1.5
6.0
1.5
6.5
Fig. Units No.
ns
2-3
ns
2-5
ns
2-5
4-82
~National
D Semiconductor
54F/74F132
Quad 2-lnput NANO Schmitt Trigger
General Description
The 'F132 contains four 2-input NANO gates which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. In addition, they have a greater noise margin than conventional NANO gates.
Each circuit contains a 2-input Schmitt trigger followed by level shifting circuitry and a standard FAST� output structure. The Schmitt trigger uses positive feedback to effectively speed-up slow input transitions, and provide different input threshold voltages for positive and negative-going transitions. This hysteresis between the positive-going and negative-going input threshold (typically 800 mV) is determined by resistor ratios and is essentially insensitive to temperature and supply voltage variations.
Guaranteed 4000V minimum ESO protection
Ordering Code: see sections Logic Symbol
Connection Diagrams
IEEE/I EC
Pin Assignment for
DIP, SOIC and Flatpak
Ao
&:.!J
60
Bo
Ao
Yee
A1
01
Bo
A2
B1
Oo
B2
A2
62
A1
02
B2
B1
A3
A3
03
01
B3
B3
GND
03
TL/F/9477-3
TL/F/9477-1
Unit Loading/Fan Out: See Section 2 for U.L. definitions
Pin Names
An, Bn On
Description
Inputs Outputs
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loHllOL
1.0/1.0 50/33.3
20 �A/-0.6 mA -1 mA/20mA
Function Table
Inputs
Outputs
A'
B
0
L
L
H
L
H
H
H
L
H
H
H
L
H = HIGH Voltage Level L = LOW Vcltage Level
Pin Assignment for LCC
rBn1
mNC A1 NC []]@J
m60
01 [I] GND [Q]
NC [jJ
03 [j]] B3 Ii]
[I] Bo [IJ Ao []]NC ~Vee [j]]A2
[1][j]J[j]][Z][j]J A3 NC 02 NC B2
TL/F/9477-2
4-83
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for avallablllty and specifications.
Storage Temperature Ambient Temperature under Bias
- 65�C to + 150�C
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to + 7~ov
Input Voltage (Note 2)
-0.5Vto +7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5VtoVee -0.5Vto +5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
ESD Last Passing Voltage (Min)
4000V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
VT+ VTfl.VT Veo VoH
Vol
l1H
lsv1
le EX
V10
loo
l1L los leeH leeL
Positive-going Threshold
Negative-going Threshold
Hysteresis (VT+ - VT-)
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 74F 10% Vee 74F 5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage
Test
74F
Output Leakage
74F
Circuit Current
Input LOW Current
Output Short-Circuit Current
Power Supply Current
Power Supply Current
54F/74F
Min Typ
Max
1.5
2.0
0.7
1.1
0.4
-1.2
2.5 2.5 2.7
0.5 0.5
20.0 5.0
100 7.0
250 50
4.75
-60
3.75
-0.6 -150 17.0 18.0
Units v v v v
v
v
�A
�A
�A
v
�A mA mA mA mA
Vee
5.0 5.0 5.0 Min
Min
Min
Max
Max
Max
0.0
0.0 Max Max Max Max
Conditions
l1N = -18 mA loH = -1 mA loH = -1 mA loH = -1 mA loL = 20 mA loL = 20 mA V1N = 2.7V
V1N = 7.0V
VouT =Vee 110 = 1.9 �A All Other Pins Grounded V100 = 150mV All Other Pins Grounded V1N = 0.5V VouT = ov Vo= HIGH Vo= LOW
4-84
AC Electrical Characteristics: See Section 2 for waveforms and Load Configurations
Symbol
Parameter
tPLH
Propagation Delay
tPHL
An, Bn to On
74F
TA= +2s0 c Vee= +s.ov
CL= 50pF
Min
Typ
Max
4.0
10.5
5.0
12.5
54F
TA, Vee= Mii CL= 50pF
Min
Max
2.0
13.0
4.5
16.0
74F
TA, Vee= Com CL= 50pF
Min
Max
3.5
12.0
5.0
13.0
Units Fig. No.
ns
2-3
a
4-85
.~National
U Semiconductor
54F/74F138 1-of-8 Decoder/Demultiplexer
General Description
The 'F138 is a high-speed 1-of-8 decoder/demultiplexer. This device is ideally suited for high-speed bipolar memory chip select address decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three 'F138 devices or a 1-of-32 decoder using four 'F138 devices and one inverter.
Features
� Demultiplexing capability � Multiple input enable for easy expansion � Active LOW mutually exclusive outputs � Guaranteed 4000V minimum ESD protection
Ordering Code: see section 5 Logic Symbols
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
E1 Ao A1 A2 E2 E3
TL/F/9478-3
IEEE/I EC
BIN/OCT
0
60
Ao
1
01
A1
2
02
A2
4
3
03
&: E3
E1
EN
E2
4
04
5
05
6
05
7
07
TL/F/9478-6
Ao
A1 2 A2 3 E1 4 E2 5
E3
07 7 GND 8
16 Vee 15 60 14 01 13 02 12 03 11 04 10 05 9 05
TL/F/9478-1
Unit Loading/Fan Out: See Section 2 for U.L. Definitions
Pin Names
Ao-A2 E1,E2 E3
Oo-01
Description
Address Inputs Enable Inputs (Active LOW) Enable Input (Active HIGH) Outputs (Active LOW)
54F/74F
U.L. HIGH/LOW
Input l1H/l1L Output loHlloL
1.0/1.0 1.0/1.0 1.0/1.0 50/33.3
20 �Al -0.6 mA 20 �Al -0.6 mA 20 �A/ -0.6 mA -1 mA/20 mA
Pin Assignment
for LCC
E3 I]]
mEi [N[C]
rEn1
rAn i
07 [[] GND !IQ]
NC [j]
05 Ii] 55 !rn
llJA1 rnAo
[i]NC
@]Vee
[l]]Oo
~G]!rnlIZJli]]
54 63 NC 62 51
TL/F/9478-2
4-86
Functional Description
The 'F138 high-speed 1-of-8 decoder/demultiplexer ac-
cepts three binary weighted inputs (Ao, A1, A2) and, when
enabled,. provides eight mutually exclusive active LOW out-
puts (Oo-07). The 'F138 features three Enable inputs, two
active will be
LHOIGWH(Eu1~lEes2s)
and one active E1 and E2 are
HIGH (E3). All outputs LOW and E3 is HIGH.
This multiple enable function allows easy parallel expansion
.....
w
Q)
of the device to a 1-of-32 (5 lines to 32 lines) decoder with just four 'F138 devices and one inverter (See Figure 1). The 'F138 can be used as an 8-output demultiplexer by using one of the active LOW Enable inputs as the data input and the other Enable inputs as strobes. The Enable inputs which are not used must be permanently tied to their appropriate active HIGH or active LOW state.
Truth Table
Inputs
Outputs
E1 E2 Ea Ao A1 A2 Oo 01 02 03 04 05 Os 07
H
x x x x x H
H
H
H
H
H
H
H
xH xx x x H
H
H
H
H
H
H
H
x x L
x x x H
H
H
H
H
H
H
H
L
L
H
L
L
L
L
H
H
H
H
H
H
H
L
L
H
H
L
L
H
L
H
H
H
H
H
H
L
L
H
L
H
L
H
H
L
H
H
H
H
H
L
L
H
H
H
L
H
H
H
L
H
H
H
H
L
L
H
L
L
H
H
H
H
H
L
H
H
H
L
L
H
H
L
H
H
H
H
H
H
L
H
H
L
L
H
L
H
H
H
H
H
H
H
H
L
H
L
L
H
H
H
H
H
H
H
H
H
H
H
L
H = HIGH Voltage Level L = LOW Voltage Level
X = Immaterial
Logic Diagram
TL/F/9478-4 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-87
CIC)
,(.'.f.) Absolute Maximum Ratings (Note 1)
If Miiitary/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for avallablllty and specifications.
Storage Temperature
-65�C to+ 150�C
Ambient Temperature under Bias Junction Temperature under Bias
- 55�C to + 125�c
-55�C to + 115�c
Vee Pin Potential to Ground Pin
-0.5Vto +7.0V
Input Voltage (Note 2)
-0.5Vto +7.0V
Input Current (Note 2)
-30 mA to + 5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TAI-STATE� Output
-0.5Vto Vee -0.5Vto +5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
ESD Last Passing Voltage (Min)
4000V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended �Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�c to + 125�c
o�c to +1o�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Veo
lsvr
leEX V10 loo l1L
las
leeH leeL
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 74F 10% Vee 74F 5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage 74F
Test
Output Leakage 74F
Circuit Current
Input LOW Current
Output Short-Circuit Current
Power Supply Current
Power Supply Current
54F/74F Min Typ Max 2.0
0.8 -1.2 2.5 2.5 2.7 0.5 0.5 20.0 5.0 100 7.0 250 50
4.75
3.75
. -60
-0.6 -150
13
20
13
20
Units
v v v v
v
�A
�A
v
�A mA mA mA mA
Vee
Min Min
Min Max Max Max 0.0 0.0 Max Max Max Max
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal l1N = -18 mA loH = -1 mA loH = -1 mA loH = -1 mA loL = 20mA loL = 20mA V1N = 2.7V
V1N = 7.0V
VouT =Vee
110 = 1.9 �A All Other Pins Grounded V100 = 150 mV All Other Pins Grounded v,N = 0.5V VouT = ov Vo= HIGH Vo= LOW
4-88
AC Electrical Characteristics: See section 2 for waveforms and Load Configurations
Symbol
Parameter
tPLH tPHL
tPLH tPHL
iPLH lPHL
Propagation Delay An to On
Propagation Delay E1 orE2toOn
Propagation Delay E3 to On
74F
TA= +25�c Vee= +5.0V
CL= 50 pF
Min
Typ
Max
3.5
5.6
7.5
4.0
6.1
8.0
3.5
5.4
7.0
3.0
5.3
7.0
4.0
6.2
8.0
3.5
5.6
7.5
54F
TA, Vee= Mii CL= 50 pF
Min
Max
3.5
12.0
4.0
9.5
3.5
11.0
3.0
8.0
4.0
12.5
3.5
8.5
74F
TA, Vee= Com CL= 50 pF
Min
Max
3.5
8.5
4.0
9.0
3.5
8.0
3.0
7.5
4.0
9.0
3.5
8.5
...... cw o
Units Fig. No.
ns
2-3
ns
2-4
ns
2-4
A1~+--+-~~~~~~~~J--+-~~~~~~~~+----~~~~~~~~+-~ A1~+---t--+-~~~~~~~J---t-..,_~~~~~~~+-4---~~~~~~~4--I--.
'F04
A3~~~~~-....~~~~~~~~~~--~~~~~~~~~--~~~~4--l--i-I
A.~~~~~--+.--~~~~~~~~~...+-~~~~~~~~~++-~~~~4--1--4-~~+.
oo�------------------------------------------------------------------------------------------�031
FIGURE 1. Expansion to 1-of-32 Decoding
TL/F/9478-5
4-89
~National
~Semiconductor
54F/74F139 Dual 1-of-4 Decoder/Demultiplexer
General Description
The 'F139 is a high-speed, dual 1-of-4 decoder/demultiplexer. The device has two independent decoders, each accepting two inputs and providing four mutually exclusive active LOW outputs. Each decoder has an active LOW Enable input which can be used as a data input for a 4-output demultiplexer. Each half of the 'F139 can be used as a function generator providing all four minterms of two variables.
Features
� Multifunction capability � Two completely independent 1-of-4 decoders � Active LOW mutually exclusive outputs � Guaranteed 4000V minimum ESD protection
Ordering Code: see sections Logic Symbols
Connection Diagrams
Pin Assignment DIP, SOIC and Flatpak
DECODER a
DECODER b
TL/F/9479-3
TL/F/9479-4
I E E E / I EC
X/Y
0
Ooa
Aoa
1
01a
A1a
Ea EN
2
Oza
3
03a
Oob
Aob
01b
A1b
Ozb
Eb 03b
TL/F/9479-7
Unit Loading/Fan Out: See Section 2 for u.L. Definitions
Pin Names
Ao,A1
E
Oo-03
Description
Address Inputs Enable Inputs (Active LOW) Outputs (Active LOW)
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loHlloL
1.0/1.0 1.0/1.0 50/33.3
20 �A/-0.6 mA 20 �A/-0.6 mA -1 mA/20mA
Ea
Aoa 2 A1a 3 0oa 4 01a 5
Oza 03a GND 8
16 Vee
� 15 Eb 14 Aob 13 A1b 12 Oob 11 01b 10 Ozb
03b
TL/F/9479-1
Pin Assignment for LCC
6r2n8 0r1n8
NC
[]]
00a A1a
rn rn
03a [[] GND Ii])
NC [i]
03b li1l
Ozb Ii]
[I]Aoa
rn Ea
[I]NC
@!Vee l!fil Eb
ll1I ~Ii] !ill [i]]
01b Oob NC A1b Aob
TL/F/9479-2
4-90
Functional Description
The 'F139 is a high-speed dual 1-of-4 decoder/demultiplexer. The device has two independent decoders, each of
which accepts two binary weighted inputs (Ao-A1) and provides four mutually exclusive active LOW Outputs (00 -03). Each decoder has an active LOW enable (E). When E is
HIGH all outputs are forced HIGH. The enable can be used
Truth Table
Inputs
Outputs
E Ao A1 Oo 01 02 03
H x x
H
H
H
H
L
L
L
L
H
H
H
L
H
L
H
L
H
H
L
L
H
H
H
L
H
L
H
H
H
H
H
L
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
Logic Diagram
as the data input for a 4-output demultiplexer application. Each half of the 'F139 generates all four minterms of two variables. These four minterms are useful in some applications, replacing multiple gate functions as shown in Figure 1, and thereby reducing the number of packages required in a logic network.
~3D-�o ~3D-�o
A1
A1
~3:LJ-�1 ~3D-�1
A1
A1
~~., ~3D--�2
A1
A1
~3:D-�, ~3:�>-�,
A1
A1
TL/F/9479-6
FIGURE 1. Gate Functions (each half)
TL/F/9479-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-91
II
O>
(.,"..). Absolute Maximum Ratings (Note 1)
If MilitaryI Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to+ 7.0V
Input Voltage (Note 2)
-0.5Vto +7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5VtoVcc -0.5V to + 5.5V
Current Applied to Output in LOW State (Max) � �
twice the rated loL (mA)
ESD Last Passing Voltage (Min)
4000V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V
+ 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
V1H
Input HIGH Voltage
V1L
Input LOW Voltage
Vco
Input Clamp Diode Voltage
54F/74F Min Typ Max
Units Vee
Conditions
2.0
v
Recognized as a HIGH Signal
0.8
v
Recognized as a LOW Signal
-1.2
v
Min l1N = -18 mA
VoH
Output HIGH
Voltage
54F 10% Vee 2.5
74F 10% Vee 2.5
74F5% Vee
2.7
loH = -1 mA
v
Min loH = -1 mA
loH = -1 mA
VoL
Output LOW
Voltage
54F 10% Vee 74F 10% Vee
0.5
v
Min loL = 20 mA
0.5
loL = 20 mA
l1H
Input HIGH
54F
Current
74F
20.0 5.0
�A
Max V1N = 2.7V
lsv1
Input HIGH Current 54F
Breakdown Test
74F
100
�A
Max V1N = 7.0V
7.0
lcEX
Output HIGH
54F
Leakage Current
74F
250
�A
Max VouT =Vee
50
V10
Input Leakage
74F
Test
. 4.75
v
110 = 1.9 �A 0.0 All Other Pins Grounded
loo
Output Leakage
74F
Circuit Current
3.75
�A
0.0 V100 = 150 mV All Other Pins Grounded
l1L
Input LOW Current
los
Output Short-Circuit Current
-0.6 mA Max V1N = 0.5V
-60
-150 mA Max VouT = ov
Ice
Power Supply Current
13
20
mA Max
4-92
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
lPLH tPHL
tPLH tPHL
Propagation Delay
AoorA1 to On
Propagation Delay
E1 to On
74F
TA= +25�C Vee= +5.0V
CL= 50pF
Min
Typ
Max
3.5
5.3
7.5
4.0
6.1
8.0
3.5
5.4
7.0
3.0
4.7
6.5
54F
TA, Vee= Mii CL= 50 pF
Min
Max
2.5
12.0
3.5
9.5
3.0
9.0
2.5
8.0
74F
TA, Vee= Com CL= 50 pF
Min
Max
3.0
8.5
4.0
9.0
3.5
8.0
3.0
7.5
Units
Fig. No.
ns
2-3
ns
2-3
a
4-93
co
.",'l.:f.' ~National
~Semiconductor
54F/74F148
8-Line to 3-Line Priority Encoder
General Description
The 'F148 provides three bits of binary coded output representing the position of the highest order active input, along with an output indicating the presence of any active input. It is easily expanded via input and output enables to provide priority encoding over many bits.
Features
� Encodes eight data lines in priority � Provides 3-bit binary priority code � Input enable capability � Signals when data is present on any input � Cascadable for priority encoding of n bits
Ordering Code: see section 5 Logic Symbols
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
El
TL/F/9480-3
IEEE/I EC
T4 T5 Ts 3
" T1
Ei 5
A2 6 Al GND
1S Vee
15 ro
14 GS
13 T3 12 T2 11 T1 10 To
9 Ao
To
0/210
Tl
1/Z11
T2
2/Z12
T3
3/Z13 10
T4
4/Z14 11
T5
5/215
12
13
Ts
S/Z1S
14
T1
7/Z17 15
fi
EN cr/V18 1S
17
TL/F/9480-6
TL/F/9480-1
Unit Loading/Fan Out: See Section 2 for U.L. definitions
54F/74F
Pin Names
Description
U.L.
Input l1Hll1L
HIGH/LOW Output loHllOL
io i1-i7 Ei
EO
GS
Ao-A2
Priority Input (Active LOW) Priority Inputs (Active LOW) Enable Input (Active LOW) Enable Output (Active LOW) Group Signal Output (Active LOW) Address Outputs (Active LOW)
1.0/1.0 1.0/2.0 1.0/1.0 50/33.3 50/33.3 50/33.3
20 �Al -0.6 mA 20 �A/-1.2 mA 20 �Al -0.6 mA -1 mA/20 mA -1 mA/20mA -1 mA/20mA
Pin Assignment for LCC
.,rnOrnT, A2Ei NCT7Ts [!) [l] [!I ~ lII
GND ffQ]
!IIT4
NC [j]
Aoli1l
T0 fill
[!]NC
~Vee
1!21ffi
IGl Ii]] [fil li1l [fil T1 T2 NC T3 GS
TL/F/9480-2
4-94
Functional Description
The 'F148 8-input priority encoder accepts data from eight
active LOW inputs (io-h) and provides a binary representa-
tion on the three active LOW outputs. A priority is assigned to each input so that when two or more inputs are simultaneously active, the input with the highest priority is represented on the output, with input line 7 having the highest priority. A HIGH on the Enable Input (Ei) will force all outputs to the inactive (HIGH) state and allow new data to settle without producing erroneous information at the outputs.
A Group Signal output (GS) and Enable Output (EO) are
provided along with the three priority data outputs (A2, A1,
Ao). GS is active LOW when any input is LOW: this indicates
when any input is active. EO is active LOW when all inputs are HIGH. Using the Enable Output along with the Enable Input allows cascading for priority encoding on any number of input signals. Both EO and GS are in the inactive HIGH state when the Enable Input is HIGH.
Truth Table
Inputs
Outputs
Ei io i1 i2 ia i4 is is '7 GS Ao A1 A2 EO
Hxxxxxxxx H H H H H
L HHHHHHHH H H H H L
L xxxxxxxL L L L L H L xxxxxxLH L H L L H L xxxxxL HH L L H L H
L xxxx L HHH L H H L H L xxxLHHHH L L L H H L xxLHHHHH L H L H H L xLHHHHHH L L H H H
L LHHHHHHH L H H H H
H = HIGH Voltage Level L = LOW Voltage Level
X = Immaterial
Logic Diagram
Ei T7
TL/F/9480-4 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-95
co
".'.1.:.1.' Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor � Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to+ 7.0V
Input Voltage (Note 2)
-0.5Vto +7.0V
Input Current (Note 2)
-30 mA to + 5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5V to Vee -0.5Vto +5.5V
Current Applied to Output in LOW State (Max)
twice the rated Im (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C o�cto +70�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
54F/74F Min Typ Max
Units Vee
Conditions
V1H
Input HIGH Voltage
2.0
v
Recognized as a HIGH Signal
V1L
Input LOW Voltage
0.8
v
Recognized as a LOW Signal
Veo
Input Clamp Diode Voltage
VoH
Output HIGH
Voltage
54F 10% Vee 2.5
74F 10% Vee 2.5
74F5%Vee
2.7
-1.2
v
Min l1N = -18 mA
loH = -1 mA
v
Min loH = -1 mA
loH = -1 mA
Vol
Output LOW
Voltage
54F 10% Vee 74F 10% Vee
0.5
loL =�20 mA
v
Min
0.5
loL = 20 mA
l1H
Input HIGH
54F
Current
74F
20.0
�A
Max V1N = 2.7V
5.0
lsv1
Input HIGH Current 54F
Breakdown Test
74F
100 7.0
�A
Max V1N = 7.0V
leEX
Output High
54F
Leakage Current
74F
250 50
�A
Max Vour =Vee
V10
Input Leakage
74F
4.75
Test
v
0.0 lio = 1.9 �A All Other Pins Grounded
loo
Output Leakage
74F
Circuit Current
3.75
�A
0.0 V100 = 150 mV All Other Pins Grounded
l1L
Input LOW
Current
-0.6 -1.2
mA mA
Max V1N = 0.5V (io. Ei)
V1N = 0.5V (i1-i7)
las
Output Short-Circuit Current
-60
-150 mA Max Vour = ov
leeH
Power Supply Current
35
mA Max Vo= HIGH
lceL
Power Supply Current
35
mA Max Vo= LOW
4-96
Application
LSB
16-lnput Priority Encoder
f.CSB
01234567EI 'f148
0 123 45 'f148
7 El
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
tPLH
Propagation Delay
tPHL
In to An
tPLH
Propagation Delay
tPHL
In to EO
tPLH
Propagation Delay
tPHL
In to GS
tPLH
Propagation Delay
tPHL
Ei to An
tPLH
Propagation Delay
tPHL
Ei to GS
tPLH
Propagation Delay
tPHL
Ei to EO
74F
TA= +25�C Vee= +5.0V
CL= 50pf
Min
Typ
Max
3.0
7.0
9.0
3.0
8.0
10.5
2.5
5.0
6.5
2.5
5.5
7.5
2.5
7.0
9.0
2.5
6.0
8.0
2.5
6.5
8.5
2.5
6.0
8.0
2.5
5.0
7.0
2.5
6.0
7.5
2.5
5.5
7.0
3.0
8.0
10.5
54F
TA, Vee= Mil CL= 50 pf
Min
Max
74F
TA, Vee= Com CL= 50pf
Min
Max
3.0
10.0
3.0
12.0
2.5
7.5
2.5
8.5
2.5
10.0
2.5
9.0
2.5
9.5
2.5
9.0
2.5
8.0
2.5
8.5
2.5
8.0
3.0
12.0
TL/F/9480-5
Fig. Units No.
ns 2-3
ns
2-3
ns 2-3
ns 2-3
ns 2-3
ns 2-3
4-97
<,..(.
,l.l.). ~National
U Semiconductor
54F/74F151A
8-lnput Multiplexer
General Description
The 'F151 A is a high-speed 8-input digital multiplexer. It provides in one package the ability to select one line of data from up to eight sources. The 'F151A can be used as a
universal function generator to generate any logic function of four variables. Both assertion and negation outputs are provided.
Ordering Code: see section 5
Logic Symbols
Connection Diagrams
TL/F/9481-3
I E E E / I EC MUX
EN
} So
S1 S2 lo 11 12 13 14 15 Is 17
TL/F/9481-5
Pin Assignment for DIP, SOIC and Flatpak
GND 8
16 Vee 15 14 14 15 13 Is 12 17 11 So
10 s1 9 s2
TL/F/9481-1
Pin Assignment for LCC
Z Z NC lo 11
[K][IJ [�:] @] [i]
GN~~o~:~
NC [j]
[j]NC
S2 li1!
~Vee
S1~
[j]Jl4
~[fillill [Z]fl]) So7NC~l5
TL/F/9481-2
Unit Loading/Fan Out: seeSection2forU.L.Definitions
Pin Names
lo-17 So-S2
E
z z
Description
Data Inputs Select Inputs Enable Input (Active LOW) Data Output Inverted Data Output
54F/74F
U.L. HIGH/LOW
Input l1H/l1L Output loHlloL
1.0/1.0 1.0/1.0 1.0/1.0 50/33.3 50/33.3
20 �Al - 0.6 mA 20 �A/ - 0.6 mA 20 �A/ - 0.6 mA -1 mA/20mA -1 mA/20 mA
4-98
.....
Functional Description
Truth Table
.U...1.
)>
The 'F151 A is a logic implementation of a single pole, 8-position switch with the switch position controlled by the state of three Select inputs, S0, S1, S2. Both assertion and negation outputs are provided. The Enable input (E) is active LOW. When it is not activated, the negation output is HIGH and the assertion output is LOW regardless of all other inputs. The logic function provided at the output is:
Z = E � Oo S2 S1 So + 11 S2 S1 So + 12 S2 S1 So +
Inputs
Outputs
E
S2
S1
.So
z
z
H
x
x
x
H
L
L
L
L
L
io
lo
L
L
L
H
i1
11
L
L
H
L
i2
12
13 S2 S1 So + 14 S2 S1 So + 15 S2 S1 So +
la S2 S1 So + 17 S2 S1 So)
The 'F151A provides the ability, in one package, to select from eight sources of data or control information. By proper manipulation of the inputs, the 'F151 A can provide any logic
L
L
H
H
h
13
L
H
L
L
l4
14
L
H
L
H
is
15
L
H
H
L
Ia
la
function of four variables and its negation.
L
H
H
H
l7
17
H = HIGH Voltage Level L = LOW Voltage Level
X = Immaterial
Logic Diagram
- 1- "><"'
-Vt
�- l ">("' ...... :JI
�- 1 ">("' ...... :JI
........ 1.1-
v
- I-
v
. . . . . . . loot-
I
-...........
-......I-
....... I-
j
.............
\..,...J
...............
\..,...J
.JJ ~
~
~~
~
z z
TL/F/9481-4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-99
,<.C.. ,L..t.) Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
-55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5Vto +7.0V
Input Voltage (Note 2)
-0.5V to+ 7.0V
Input Current (Note 2)
-30 mA to + 5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5V to Vee -0.5Vto +5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
V1H
Input HIGH Voltage
V1L
Input LOW Voltage
Veo
Input Clamp Diode Voltage
54F/74F Min Typ Max
Units Vee
Conditions
2.0
v
Recognized as a HIGH Signal
0.8
v
Recognized as a LOW Signal
-1.2
v
Min l1N = -18 mA
VoH
Output HIGH
Voltage
54F 10% Vee 2.5
74F 10% Vee 2.5
74F5% Vee
2.7
loH = -1 mA
v
Min loH = -1 mA
loH = -1 mA
VoL
Output LOW
Voltage
54F 10% Vee 74F 10% Vee
0.5
v
Min loL = 20 mA
0.5
loL = 20 mA
l1H
Input HIGH
54F
Current
74F
20.0 5.0
�A
Max V1N = 2.7V
lsv1
Input HIGH Current 54F
Breakdown Test
74F
100 7.0
�A
Max V1N = 7.0V
lcEx
Output HIGH
54F
Leakage Current
74F
250
�A
Max VouT =Vee
50
V10
Input Leakage
74F
4.75
Test
v
0.0
lio = 1.9 �A All Other Pins Grounded
loo
Output Leakage 74F
Circuit Current
3.75
�A
0.0
V100 = 150 mV All Other Pins Grounded
l1L
Input LOW Current
los
Output Short-Circuit Current
-0.6 mA Max V1N = 0.5V
-60
-150 mA Max VouT = ov
Ice
Power Supply Current
13.5 21.0
mA Max Vo= HIGH
4-100
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
tPLH tPHL
tPLH tPHL
tPLH tPHL
tPLH tPHL
tPLH tPHL
tPLH tPHL
Propagation Delay SntoZ
Propagation Delay SntoZ
Propagation Delay Etoz
Propagation Delay EtoZ
Propagation Delay lntoZ
Propagation Delay In toZ
74F
TA= +25�C Vee= +5.0V
CL= 50pF
Min
Typ
Max
4.0
6.2
9.0
3.2
5.2
7.5
4.5
7.5
10.5
4.0
6.2
9.0
3.0
4.7
6.1
3.0
4.4
6.0
5.0
7.0
9.5
3.5
5.3
7.0
3.0
4.8
6.5
1.5
2.5
4.0
3.0
4.8
6.5
3.7
5.5
7.0
54F
TA, Vee= Mil CL= 50 pf
Min
Max
3.5
11.5
3.0
8.0
4.5
13.5
4.0
9.5
3.0
7.5
2.5
6.5
4.0
12.0
3.0
8.0
2.5
7.5
1.5
6.0
2.5
8.5
3.5
9.0
74F
TA, Vee= Com CL= 50 pf
Min
Max
3.5
9.5
3.2
7.5
4.5
12.0
4.0
9.0
3.0
7.0
2.5
6.0
4.0
10.5
3.0
7.5
3.0
7.0
1.5
5.0
2.5
7.5
3.7
7.5
.... .C.J.1.
)> Fig. Units No.
ns
2-3
ns
2-3
ns
2-3
ns
2-3
ns
2-3
ns
2-3
4-101
~DNaStemiicoonnduactlor
54F/74F153 Dual 4-lnput Multiplexer
General Description
The 'F153 is a high-speed dual 4-input multiplexer with common select inputs and individual enable inputs for each section. It can select two lines of data from four sources. The
two buffered outputs present data in the true (non-inverted) form. In addition to multiplexer operation, the 'F153 can generate any two functions of three variables.
Ordering Code: see section 5
Logic Symbols
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
zb TL/F/9482-3
I E E E / I EC
Ea 1 s, 2
1311 3
1211
1111
l0a 6 Z11 7 GND 8
16 Vee 15 Eb 14 So 13 l3b 12 l2b 11 l1b 10 lob 9 zb
TL/F/9482-1
Pin Assignment for LCC
r'trlau
ml1a NC I]]
'r2na
r~n
G:~~o~t
NC [j]
[!]NC
zb li1J
~Vee
lob Ii]
Ii]] Eb
~IIID!ffi l!ZJ!l]] l1b '2b NC 13b So
TL/F/9482-2
TL/F/9482-5
Unit Loading/Fan Out: See Section 2 for U.L. definitions
Pin Names
Description
54F/74F
U.L.
Input l1Hll1L
HIGH/LOW Output loHlloL
loa-lsa lob-lsb So, S1 Ea Eb Za zb
Side A Data Inputs Side B Data Inputs Common Select Inputs Side A Enable Input (Active LOW) Side B Enable Input (Active LOW) Side A Output Side B Output
1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 50/33.3 50/33.3
20 �A/ -0.6 mA 20 �Al -0.6 mA 20 �A/-0.6 mA 20 �A/-0.6 mA 20 �Al -0.6 mA -1 mA/20 mA -1 mA/20 mA
4-102
Functional Description
The 'F153 is a dual 4-input multiplexer. It can select two bits of data from up to four sources under the control of the common Select inputs (S0, S1). The two 4-input multiplexer circuits have individual active LOW Enables (Ea, Eb) which can be used to strobe the outputs independently. When the Enables (Ea, Eb) are HIGH, the corresponding outputs (Za, Zb) are forced LOW. The 'F153 is the logic implementation of a 2-pole, 4-position switch, where the position of the switch is determined by the logic levels supplied to the two Select inputs. The logic equations for the outputs are as follows:
Truth Table
Select Inputs
So
S1
E
x
x
H
L
L
L
L
L
L
H
L
L
H
L
L
L
H
L
L
H
L
H
H
L
H
H
L
H = HIGH Voltage Level L =LOW X = Immaterial
Logic Diagram
Inputs (a orb)
lo
11
12
x
x
x
L
x
x
H
x
x
x
L
x
x
H
x
x
x
L
x
x
H
x
x
x
x
x
x
Za = Ea�(loa�S1�So + l1a�S1�So + l2a�S1 �So + l3a�S1 �So)
Zb = Eb�(lob�S1�So + l1b�S1�So + l2b�S1�So + l3b�S1�So)
The 'F153 can be used to move data from a group of registers to a common output bus. The particular register from which the data came would be determined by the state of the Select inputs. A less obvious application is as a function generator. The 'F153 can generate two functions of three variables. This is useful for implementing highly irregular random logic.
Output
13
z
x
L
x
L
x
H
x
L
x
H
x
L
x
H
L
L
H
H
TL/F/9482-4 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-103
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for avallablllty and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to+ 7.0V
Input Voltage (Note 2)
-0.5V to+ 7.0V
Input Current (Note 2)
-30 mA to + 5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5V to Vee -0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�c
o�c to +10�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
V1H
Input HIGH Voltage
V1L
Input LOW Voltage
Veo
Input Clamp Diode Voltage
VoH
Output HIGH
Voltage
54F 10% Vee 74F 10% Vee 74F5% Vee
54F/74F Min Typ Max 2.0
0.8 -1.2 2.5 2.5 2.7
Units Vee
Conditions
v
Recognized as a HIGH Signal
v
Recognized as a LOW Signal
v
Min l1N = -18 mA
loH = -1 mA
v
Min loH = -1 mA
loH = -1 mA
VoL
Output LOW
Voltage
54F 10% Vee 74F 10% Vee
0.5
v
Min loL = 20 mA
0.5
loL = 20mA
l1H
Input HIGH
54F
Current
74F
20.0
V1N = 2.7V
5.0
�A Max
lsv1
Input HIGH Current 54F
Breakdown Test
74F
100
�A
Max V1N = 7.0V
7.0
leEx
Output High
54F
Leakage Current
74F
250 50
�A
Max Vour =Vee
V10
Input Leakage
74F
4.75
Test
v
0.0 110 = 1.9 �A
All Other Pins Grounded
loo
Output Leakage 74F
Circuit Current
3.75
�A
0.0 V100 = 150mV
All Other Pins Grounded
l1L
Input LOW Current
los
Output Short-Circuit Current
-0.6
mA Max V1N = 0.5V
-60
ov -150 mA Max Vour =
leeL
Power Supply Current
12
20
mA Max Vo= LOW
4-104
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
tPLH
Propagation Delay
tPHL
Sn to Zn
tPLH
Propagation Delay
tPHL
En to Zn
tPLH
Propagation Delay
tPHL
In to Zn
74F
TA= +25�C Vee= +5.0V
CL= 50 pF
Min
Typ
Max
4.5
8.1
10.5
3.5
7.0
9.0
4.5
7.1
9.0
3.0
5.7
7.0
3.0
5.3
7.0
2.5
5.1
6.5
54F
TA, Vee= Mil CL= 50 pF
Min
Max
4.5
14.0
3.5
11.0
4.5
11.5
2.5
9.0
2.5
9.0
2.5
8.0
74F
TA, Vee= Com CL= 50 pF
Min
Max
4.5
12.0
3.5
10.5
4.5
10.5
2.5
8.0
3.0
8.0
2.5
7.5
.....
cw.n
Fig. Units
No.
ns
2-3
ns
2-3
ns
2-3
4-105
~UNaStemiicoonnduactlor
54F/74F157A
Quad 2..1nput Multiplexer
General Description
The 'F157A is a high-speed quad 2-input multiplexer. Four bits of data from two sources can be selected using the common Select and Enable inputs. The four outputs present the selected data in the true (non-inverted) form. The 'F157A can also be used to generate any four of the 16 different functions to two variables.
Features
� Guaranteed 4000V minimum ESD protection
Ordering Code: see section 5 Logic Symbols
Connection Diagrams
loa l1a lob l1b lac 110 lad l1d Za zb Zc zd
TL/F/9463-3
IEEE/I EC
Za
Pin Assignment for DIP, SOIC and Flatpak
s 1
1oa 2 l1a 3
Za
lob 11b 6 zb 7 GND 8
16 Vee 15 E
14 loc 13 11c 12 Zc 11 lod 10 l1d 9 zd
TL/F/9463-1
Pin Assignment
0for LCC l1b icJb NC la l1d []][Z]lfil[fillII
~zo b [~[] NC !TI) zd~ l1d[j]
!mIllsoa
[i]NC
~~cc
li2JE
li][ID[j]J[Z]ff�]
icJd le NC l1c be
TL/F/9483-2
TL/F/9463-5
Unit Loading/Fan Out: See Section 2 for U.L. Definitions
Pin Names
loa-lod l1a-l1d
E
s
Za-Zd
Description
Source 0 Data Inputs Source 1 Data Inputs Enable Input (Active LOW) Select Input Outputs
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loHllOL
1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 50/33.3
20 �A/-0.6 mA 20 �A/-0.6 mA 20 �A/-0.6 mA 20 �A/-0.6 mA -1 mA/20 mA
4-106
Functional Description
The 'F157A is a quad 2-input multiplexer. It selects four bits of data from two sources under the control of a common Select input (S). The Enable input (E) is active LOW. When Eis HIGH, all of the outputs (Z) are forced LOW regardless of all other inputs. The 'F157A is the logic implementation of a 4-pole, 2-position switch where the position of the switch is determined by the logic levels supplied to the Select input. The logic equations for the outputs are shown below:
Zn= E�(l1nS + lonS)
A common use of the 'F157A is the moving of data from two groups of registers to four common output busses. The particular register from which the data comes is determined by the state of the Select input. A less obvious use is as a function generator. The 'F157A can generate any four of the
Logic Diagram
...... (..J..1..
)> 16 different functions of two variables with one variable common. This is useful for implementing highly irregular logic.
Truth Table
Inputs
E
5
lo
H
x
x
L
H
x
L
H
x
L
L
L
L
L
H
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
Output
11
z
x
L
L
L
H
H
x
L
x
H
TL/F/9483-4 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-107
<,..C._
,L..t.) Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
-65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�c
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5Vto +7.0V
Input Voltage (Note 2)
-0.5Vto +7.0V
Input Current (Note 2)
-30 mA to + 5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5V to Vee -0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
ESD Last Passing Voltage (Min)
4000V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C o�cto +1o�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol V1H V1L Yeo VoH
Vol
l1H
lsv1
leEX
V10
loo
l1L los leeH leeL
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 74F 10% Vee 74F5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current
54F
Breakdown Test
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage 74F
Test
Output Leakage
Circuit Current
74F
Input LOW Current
Output Short-Circuit Current
Power Supply Current
Power Supply Current
54F/74F Min Typ Max 2.0
0.8 -1.2
2.5 2.5 2.7
0.5 0.5 20.0 5.0 100 7.0 250 50
4.75
3.75
-0.6
-60
-150
15
23
15
23
Units v v v
v
v
�A
�A
�A
v
�A mA mA mA mA
Vee
Min Min
Min Max Max Max 0.0 0.0 Max Max Max Max
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal l1N = -18 mA loH = -1 mA loH = -1 mA loH = -1 mA loL = 20mA loL = 20 mA V1N = 2.7V
V1N = 7.0V
Vour =Vee
110 = 1.9 �A All Other Pins Grounded V100 = 150 mV All Other Pins Grounded V1N = 0.5V Vour = ov Vo= HIGH Vo= LOW
4-108
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
tPLH tPHL
tpLH lPHL
lPLH lPHL
Propagation Delay StoZn
Propagation Delay EtoZn
Propagation Delay In to Zn
74F
TA= +25�C Vee= +s.ov
CL= 50pf
Min
Typ
Max
4.0
7.0
10.0
3.0
5.0
7.0
5.0
7.0
9.5
2.5
4.5
6.5
2.5
4.5
6.0
2.5
4.0
5.5
54F
TA, Vee= Mil CL= 50pf
Min
Max
4.0
12.0
3.0
9.0
5.0
13.0
2.5
7.5
2.5
7.5
1.5
7.5
74F
TA, Vee= Com CL= 50pf
Min
Max
4.0
11.0
3.0
8.0
5.0
11.0
2.5
7.0
2.5
6.5
2.0
7.0
Units
Fig. No.
ns
2-3
ns
2-3
ns
2-3
4-109
c<Co
L,..t>.. ~National
D Semiconductor
54F/74F158A
Quad 2-lnput Multiplexer
General Description
The 'F15BA is a high speed quad 2-input multiplexer. It selects four bits of data from two sources using the common Select and Enable inputs. The four outputs present the selected data in the inverted form. The 'F158A can also generate any four of the 16 different functions of two variables.
Features
� Guaranteed 4000V minimum ESD protection
Ordering Code: see section 5 Logic Symbols
IEEE/I EC
TL/F/9484-3
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
s 1
1oa 2 l1a 3 Za lob l1b 6 zb GND
16 Vee 15 E 14 loc 13 1tc 12 zc 11 1od 10 l1d 9 zd
TL/F /9484-1
Pin Assignment
for LCC
la l1b bb NC l1a
[[I II] [[J [�] !II
c!~:o~~a
NC [j)
zd 1i1J 11dllll
[I]NC
~Vee
[i]]E
~[filij]) !l][j]J
bd 2c NC l1c be
TL/F/9484-2
loa 1Y Za
l1a lob
2Y Zb l1b lod
3Yld l1d loc
4Y Zc l1c
TL/F/9484-5
Unit Loading/Fan Out: See Section 2 for U.L. Definitions
Pin Names
loa-lod l1a-l1d
E
s
Za-Zd
Description
Source O Data Inputs Source 1 Data Inputs Enable Input (Active LOW) Select Input Inverted Outputs
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loHlloL
1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 50/33.3
20 �A/-0.6 mA 20 �A/ - 0.6 mA 20 �A/-0.6 mA 20 �A/-0.6 mA
-1 mA/20mA
4-110
Functional Description
The 'F158A quad 2-input multiplexer selects four bits of data from two sources under the control of a common Select input (S) and presents the data in inverted form at the four outputs. The Enable input (E) is active LOW. When E is HIGH, all of the outputs (Z) are forced HIGH regardless of all other inputs. The 'F158A is the logic implementation of a 4-pole, 2-position switch where the position of the switch is determined by the logic levels supplied to the Select input.
A common use of the 'F158A is the moving of data from two groups of registers to four common output busses. The particular register from which the data comes is determined by the state of the Select input. A less obvious use is as a function generator. The 'F158A can generate four functions of two variables with one variable common. This is useful for implementing gating functions.
Logic Diagram
Truth Table
Inputs
E s lo 11
H x x x
L
L
L
x
L
L
H
x
L H x L
L H xH
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Zn = Ex (l1n S + Ion S)
Outputs
z
H H L H L
TL/F/9484-4 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-111
<co
,L..C..) Absolute Maximum Ratings (Note 1)
If MilitaryI Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 15o�c
Ambient Temperature under Bias
- 55�C to + 125�c
Junction Temperature under Bias
- 55�C to + 115�c
Vee Pin Potential to Ground Pin
- 0.5V to + 7.0V
Input Voltage (Note 2)
-0.5V to+ 7.0V
Input Current (Note 2)
-30 mA to + 5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5VtoVee - 0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
ESD Last Passing Voltage (Min)
4000V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�c o�cto +1o�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol V1H V1L Veo VoH
VoL l1H lsv1 lcEx V10 loo l1L las Ice
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 74F 10% Vee 74F5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage 74F
Test
Output Leakage 74F
Circuit Current
Input LOW Current
Output Short-Circuit Current
Power Supply Current
54F/74F Min Typ Max 2.0
0.8 -1.2 2.5 2.5 2.7 0.5 0.5 20.0 5.0 100 7.0 250
50
4.75
3.75
-0.6
-60
-150
10
15
Units v v v v
v �A �A �A v �A mA mA mA
Vee
Min Min
Min Max Max Max 0.0 0.0 Max Max Max
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal l1N = -18mA loH = -1 mA loH = -1 mA loH = -1 mA loL = 20 mA loL = 20 mA V1N = 2.7V
V1N = 7.0V
VouT =Vee
110 = 1.9 �A All Other Pins Grounded V100 = 150 mV All Other Pins Grounded V1N = 0.5V VouT = ov Vo= LOW
4-112
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
tPLH tPHL
tPLH tPHL
tPLH tPHL
Propagation Delay StoZn
Propagation Delay EtoZn
Propagation Delay Into Zn
74F
TA= +25�C Vee= +5.0V
CL= 50 pF
Min
Typ
Max
3.0
5.5
8.5
2.5
4.5
6.5
2.5
4.5
6.0
2.0
4.0
6.0
2.5
4.0
5.9
1.5
2.5
4.0
54F
TA, Vee= Mil CL= 50 pF
Min
Max
3.0
10.5
2.5
8.0
2.5
8.0
2.0
7.0
2.5
8.5
1.0
5.0
74F
TA, Vee= Com CL= 50 pF
Min
Max
3.0
9.5
2.5
7.0
2.5
7.0
2.0
6.5
2.5
7.0
1.5
4.5
.....
U1 O> )> Fig. Units No.
ns
2-3
ns
2-3
ns
2-3
4-113
<
N
<,.D..
< �
~National Q Semiconductor
0
<,.D..
54F/74F160A � 54F/74F162A
Synchronous Presettable BCD Decade Counter
General Description
The 'F160A and 'F162A are high-speed synchronous decade counters operating in the BCD (8421) sequence. They are synchronously presettable for applications in programmable dividers. There are two types of Count Enable inputs plus a Terminal Count output for versatility in forming synchronous multistage counters. The 'F160A has an asynchronous Master Reset input that overrides all other inputs and forces the outputs LOW. The 'F162A has a Synchronous Reset input that overrides counting and parallel load-
ing and allows all outputs to be simultaneously reset on the rising edge of the clock. The 'F160A and 'F162A are high speed versions of the 'F160 and 'F162.
Features
� Synchronous counting and loading � High-speed synchronous expansion � Typical count rate of 120 MHz � Guaranteed 4000V minimum ESD protection
Ordering Code: see section 5 Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
'F160A
MR 1 CP 2 Po 3 P1 4 P2 5 P3 6 CEP 7 GND 8
16 Yee
15 TC
14 Oo 13 01 12 02 11 03 10 CET
PE
TL/F/9485-1
Pin Assignment for LCC
'F160A P3 P2 NC P1 Po []] [I) [[] [[] [I]
CEP [[) GND [Q]
NC [j] PE~ CET I]}]
[I)CP
rn MR
[i]NC
~Yee li]]TC
li}]~filllIZJfi]] 03 02 NC 01 Oo
TL/F/9485-2
'F162A
SR
CP 2 Po 3 P1 4 P2 5 P3 CEP 7 GND 8
16 Yee
15 TC
14 Oo
13 o,
12 02 11 03 10 CET
PE
TL/F/9485-9
'F162A P3 P2 NC P1 Po []] [I) [[] [[) [I]
CEP [[) GND [Q]
NC [j] PE~ CET I]}]
[I)CP
rn SR
[i]NC
~Yee li]]TC
li}]~fil)lIZJfi]]
03 02 NC 01 Oo
TL/F/9485-10
4-114
Logic Symbols
'F160A
PE Po P1 P2 P3 CEP
CET
TC
CP
i;lR Oo 01 02 03
......
en
0
)>
IEEE/I EC
..�....
en
'F160A
N )>
CTRDIV10
i;lR
CT=O
PE
CET
CET
3CT::9
TC
CEP
CP
'F162A P1 P2 P3
TC
SR Oo 01 02 03
TL/F/9485-3 TL/F/9485-8
Po P1 P2 P3
'F162A
SR
PE
CET CET
Oo 01 02 03
TL/F/9485-6
TC
CP
Po
Oo
P1
01
P2
02
P3
03
TL/F/9485-7
Unit Loading/Fan Out: See Section 2 tor U.L. definitions
Pin Names
CEP CET CP MR ('F160A) SR ('F162A) Po-P3 PE Oo-03 TC
Description
Count Enable Parallel Input Count Enable Trickle Input Clock Pulse Input (Active Rising Edge) Asynchronous Master Reset Input (Active LOW) Synchronous Reset Input (Active LOW) Parallel Data Inputs Parallel Enable Input (Active LOW) Flip-Flop Outputs Terminal Count Output
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loHllOL
1.0/1.0 1.0/2.0 1.0/1.0 1.0/1.0 1.0/2.0 1.0/1.0 1.0/2.0 50/33.3 50/33.3
20 �A/-0.6 mA 20 �A/-1.2 mA 20 �A/-0.6 mA 20 �A/-0.6 mA 20 �A/-1.2 mA 20 �A/-0.6 mA 20 �A/-1.2 mA -1 mA/20 mA -1 mA/20 mA
4-115
<(
~N Functional Description
�
<(
The 'F160A and 'F162A count modulo-10 in the BCD (8421)
,c0.o..
sequence. From state 9 (HLLH) they increment to state O (LLLL). The clock inputs of all flip-flops are driven in parallel
through a clock buffer. Thus all changes of the Q outputs
(except due to Master Reset of the ('F160A) occur as a
result of, and synchronous with, the LOW-to-HIGH transition
of the CP input signal. The circuits have four fundamental
modes of operation, in order of precedence: asynchronous
reset ('F160A), synchronous reset ('F162A), parallel load,
count-up and hold. Five control inputs-Master Reset (MR,
'F160A), Synchronous Reset (SR, 'F162A), Parallel Enable
(PE), Count Enable Parallel (CEP) and Count Enable Trickle
(CET)-determine the mode of operation, as shown in the
Mode Select Table. A LOW signal on MR overrides all other
inputs and asynchronously forces all outputs LOW. A LOW
signal on SR overrides counting and parallel loading and
allows all outputs to go LOW on the next rising edge of CP.
A LOW signal on PE overrides counting and allows informa-
tion on the Parallel Data (Pn) inputs to be loaded into the
flip-flops on the next rising edge of CP. With PE and MR
('F160A) or SR ('F162A) HIGH, CEP and CET permit count-
ing when both are HIGH. Conversely, a LOW signal on ei-
ther CEP or CET inhibits counting.
The 'F160A and 'F162A use D-type edge-triggered flip-flops and changing the SR, PE, CEP and CET inputs when the CP is in either state does not cause errors, provided that the recommended setup and hold times, with respect to the rising edge of CP, are observed.
The Terminal Count (TC) output is HIGH when CET is HIGH and counter is in state 9. To implement synchronous multistage counters, the TC outputs can be used with the CEP and CET inputs in two different ways. Please refer to the 'F568 data sheet. The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops, counters or registers. In the 'F160A and 'F162A decade counters, the TC output is fully decoded and can only be HIGH in state 9. If a decade counter is preset to an illegal state, or assumes an illegal state when power is applied, it will return to the normal sequence within two counts, as shown in the State Diagram.
Logic Equations:
Count Enable = CEP x CET X PE TC = Oo x 01 x 02 x 03 x CET
*SR
PE
L
x
H
L
H
H
H
H
H
H
�For 'F162A only
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
Mode Select Table
CET
CEP
x
x
x
x
H
H
L
x
x
L
Action on the Rising Clock Edge (.../)
Reset (Clear) Load (Pn ~ On) Count (Increment) No Change (Hold) No Change (Hold)
State Diagram
TL/F/9485-4
4-116
PE
'160A
CEP CET
Po
P1
P2
r
c0ca;�
c
...ciiai"
m
P3
3
!
"""
CP
MR'160A SR'162A
DETAIL A
DETAIL A
DETAIL A
Oo
01
02
03
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
TUF/9485-5
m
\'~9 ~ � \'09 ~
<
N
<,..D..
Absolute Maximum Ratings (Note 1)
< �
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales
0
<,..D..
Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to + 7.0V
Input Voltage (Note 2)
-0.5Vto +7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5VtoVcc - 0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
ESD Last Passing Voltage (Min)
4000V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol V1H V1L Vco VoH
Vol l1H lsv1 le EX V10 loo l1L los Ice
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 74F 10% Vee 74F 5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage 74F
Test
Output Leakage
74F
Circuit Current
Input LOW Current
Output Short-Circuit Current
Power Supply Current
54F/74F Min Typ Max 2.0
0.8 -1.2 2.5 2.5 2.7 0.5 0.5 20.0 5.0 100 7.0 250
50
4.75
3.75
-0.6 -1.2
-60
-150
37
55
Units
v v v v
v
�A
�A
�A
v
�A mA mA mA mA
Vee
Min Min
Min Max Max Max 0.0 0.0 Max Max Max Max
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal l1N = -18mA loH = -1 mA loH = -1 mA loH = -1 mA loL = 20mA loL = 20mA V1N = 2.7V
V1N = 7.0V
VouT =Vee
110 = 1.9 �A Ail Other Pins Grounded V10D = 150 mV Ail Other Pins Grounded V1N = 0.5V (CP, CEP,Pn, MR ('F160A)) V1N = 0.5V (CET, SR ('F162A), PE)
VouT = ov
Vo= HIGH
4-118
......
en
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
0 )>
74F
54F
74F
..�....
en
TA= +25�C
I\.)
Symbol
Parameter
Vee= +5.0V
TA, Vee= Mil
TA, Vee= Com Units Fig. )>
CL= 50 pf
CL= 50 pf
No.
CL= 50 pf
Min
Typ
Max
Min
Max
Min
Max
fmax
Maximum Count Frequency
90
120
75
80
MHz 2-1
tPLH tPHL
Propagation Delay, Count CP to On (PE Input HIGH)
3.5 3.5
5.5
7.5
3.5
9.0
3.5
8.5
7.5
10.0
3.5
11.5
3.5
11.0
ns 2-3
tPLH tPHL
Propagation Delay, Load CP to On (PE Input LOW)
4.0 4.0
6.0
8.5
4.0
10.0
4.0
6.0
8.5
4.0
10.0
4.0
9.5 ns 2-3
9.5
tPLH tPHL
Propagation Delay CPtoTC
5.0
10.0
14.0
5.0
16.5
5.0
15.0
5.0
10.0
14.0
5.0
15.5
5.0
ns 2-3 15.0
tPLH tPHL
Propagation Delay CETtoTC
2.5
4.5
7.5
2.5
9.0
2.5
8.5
2.5
4.5
7.5
2.5
9.0
2.5
8.5
ns 2-3
tPHL
Propagation Delay MR to On ('F160A)
5.5
9.0
12.0
5.5
14.0
5.5
13.0
ns 2-3
tPHL
Propagation Delay MR to TC ('F160A)
4.5
8.0
10.5
4.5
12.5
4.5
11.5
ns 2-3
4-119
<C
N
,C..D. AC Operating Requirements: see Section 2 for waveforms
�
<C
0C,.D.. Symbol
Parameter
74F
TA= +2s0c Vee= +s.ov
54F
TA, Vee= Mil
Min
Max
Min
Max
t5 (H)
Setup Time, HIGH or LOW
4.0
5.5
t5 ( l )
Pn to CP ('F160A)
5.0
5.5
t5 (H)
Setup Time, HIGH or LOW
5.0
5.5
t5 ( l )
Pn to CP ('F162A)
5.0
5.5
th(H)
Hold Time, HIGH or LOW
2.0
2.5
th(l)
Pn to CP
2.0
2.5
t5 (H) t5 (L)
th(H) th(l)
Setup Time, HIGH or LOW
11.0
PE or SR toCP
8.5
Hold Time, HIGH or LOW
2.0
PE or SR to CP
0
13.5 10.5
2.0 0
t5 (H)
Setup Time, HIGH or LOW
11.0
13.0
t5 (l)
CEP or CET to CP
5.0
6.0
th(H)
Hold Time, HIGH or LOW
0
0
th(l)
CEP or CET to CP
0
0
tw(H)
Clock Pulse Width (load)
5.0
5.0
tw(l)
HIGH or LOW
5.0
5.0
tw(H)
Clock Pulse Width (Count)
4.0
5.0
tw(l)
HIGH or LOW
6.0
8.0
tw(l)
MR Pulse Width, LOW
5.0
5.0
('F160A)
tree
Recovery Time
6.0
6.0
MR to CP ('F160A)
74F
TA, Vee= Com
Min
Max
4.0 5.0
5.0 5.0
2.0 2.0
11.5 9.5
2.0 0
11.5 5.0
0 0
5.0 5.0
4.0 7.0
5.0
Fig. Units
No.
ns
2-6
ns
2-6
ns
2-6
ns
2-6
ns
2-4
ns
2-4
6.0
ns
2-6
4-120
......
~National
U Semiconductor
.O..'.>..
�)>
...... Ow'>
)>
54F/74F161A � 54F/74F163A
Synchronous Presettable Binary Counter
General Description
The 'F161A and 'F163A are high-speed synchronous modulo-16 binary counters. They are synchronously presettable for application in programmable dividers and have two types of Count Enable inputs plus a Terminal Count output for versatility in forming synchronous multi-stage counters. The 'F161 A has an asynchronous Master-Reset input that overrides all other inputs and forces the outputs LOW. The 'F163A has a Synchronous Reset input that overrides counting and parallel loading and allows the outputs to be simultaneously reset on the rising edge of the clock. The 'F161A and 'F163A are high-speed versions of the 'F161 and 'F163.
Features
� Synchronous counting and loading � High-speed synchronous expansion � Typical count frequency of 120 MHz � Guaranteed 4000V minimum ESD protection
Ordering Code: see section 5
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
'F161A
MR
CP Po P1 4 P2 P3 CEP GND 8
16 Vee 15 TC
14 Oo
13 o,
12 02 11 03 10 CET
9 PE
TL/F/9486-1
Pin Assignment for DIP, SOIC and Flatpak
'F163A
SR 1
CP
Po P1 4 P2 P3 CEP GND 8
16 Vee 15 TC
14 Oo 13 01 12 02 11 03 10 CET
PE
TL/F/9486-7
Pin Assignment for LCC 'F161A
mP3 mP2 mNC rPn1
Po
ill
~!~:o~~
NC [j]
ill NC
PE [j]
@I Vee
CET Ii]
llfil TC
~IJ]]!j]]ffZ]li]J
03 02 NC 01 0o
TL/F/9486-2
Pin Assignment for LCC 'F163A
mP3 mP2 mNC rPn1
Po
ill
~!~:o~~
NC [j]
[j]NC
PE [j]
@I Vee
CET Ii]
llfil TC
~Ii]] Ii]] ffZl [�]
03 02 NC 01 0o
TL/F/9486-8
4-121
<C
Cf)
�<...D..
<...C..
Logic Symbols
'F161A
.<..D..
PE Po P1 P2 P3
CEP
CET
TC
CP
MR Oo 01 02 03
IEEE/I EC 'F161A
CTRDIV16
TL/F/9486-3
TC CET
CEP
CP
'F163A
CEP
CET
TC
CP
SR Oo 01 02 03
IEEE/I EC 'F163A
CTRDIV16
TL/F/9486-9
TC CET
CEP
CP
TL/F/9466-6
Unit Loading/Fan Out: See Section 2 tor U.L. Definitions
Pin Names
CEP CET CP MR ('F161A) SR ('F163A) Po-P3 PE Oo-03 TC
Description
Count Enable Parallel Input Count Enable Trickle Input Clock Pulse Input (Active Rising Edge) Asynchronous Master Reset Input (Active LOW) Synchronous Reset Input (Active LOW) Parallel Data Inputs Parallel Enable Input (Active LOW) Flip-Flop Outputs Terminal Count Output
TL/F /9486-10
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loHlloL
1.0/1.0 1.0/2.0 1.0/1.0 1.0/1.0 1.0/2.0 1.0/1.0 1.0/2.0 50/33.3 50/33.3
20 �A/ -0.6 mA 20 �A/-1.2 mA 20 �A/-0.6 mA 20 �A/-0.6 mA 20 �A/-1.2 mA 20 �A/ - 0.6 mA 20 �A/-1.2 mA -1 mA/20 mA -1 mA/20 mA
4-122
Functional Description
The 'F161A and 'F163A count in modulo-16 binary sequence. From state 15 (HHHH) they increment to state 0 (LLLL). The clock inputs of all flip-flops are driven in parallel through a clock buffer. Thus all changes of the Q outputs (except due to Master Reset of the 'F161A) occur as a result of, and synchronous with, the LOW-to-HIGH transition of the CP input signal. The circuits have four fundamental modes of operation, in order of precedence: asynchronous reset ('F161 A), synchronous reset ('F163A), parallel load, count-up and hold. Five control inputs-Master Reset (MR, 'F161A), Synchronous Reset (SR, 'F163A), Parallel Enable (PE), Count Enable Parallel (CEP) and Count Enable Trickle (CET)-determine the mode of operation, as shown in the Mode Select Table. A LOW signal on MR overrides all other inputs and asynchronously forces all outputs LOW. A LOW signal on SR overrides counting and parallel loading and allows all outputs to go LOW on the next rising edge of CP. A LOW signal on PE overrides counting and allows information on the Parallel Data (Pn) inputs to be loaded into the
Mode Select Table
*SR PE CET
L xx
H
L
x
H
H
H
H
H
L
H H x
�For 'F163A only H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
CEP
x x
H
x
L
Action on the Rising Clock Edge (.../)
Reset (Clear) Load (Pn ~ On) Count (Increment) No Change (Hold) No Change (Hold)
......
.a..>...
flip-flops on the next rising edge of CP. With PE and MR
�l>
......
('F161 A) or SR ('F163A) HIGH, CEP and CET permit counting when both are HIGH. Conversely, a LOW signal on ei-
aw > l>
ther CEP or CET inhibits counting.
The 'F161A and 'F163A use D-type edge triggered flip-flops and changing the SR, PE, CEP and CET inputs when the CP is in either state does not cause errors, provided that the recommended setup and hold times, with respect to the rising edge of CP, are observed.
The Terminal Count (TC) output is HIGH when CET is HIGH and the counter is in state 15. To implement synchronous multi-stage counters, the TC outputs can be used with the CEP and CET inputs in two different ways. Please refer to the 'F568 data sheet. The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops, counters or registers.
Logic Equations: Count Enable = CEP � CET � PE
TC = Oo � 01 � 02 � 03 � GET
State Diagram
TL/F/9486-5
4-123
PE
I
IOI
'161A
'163A
L�
CEP
f l o j ____ I � ________
I I
err
'
I
I I
I '163A
1 ONLY ~
Po
' II
!
CP
N
~
MR ('161A) SR ('163A)
a;
I I
I '161A I
I ONLY.:
I I I
~-
Oo
Oo DETAIL A
P1
' II
DETAIL A 01
P2
' II
DETAIL A 02
161A�163A
m
0 n
~
P3
;c �
c.o,
D>
3
I
TC
DETAIL A
03 TL/F/9486-4
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5Vto +7.0V
Input Voltage (Note 2)
-0.5Vto +7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5VtoVcc - 0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
ESD Last Passing Voltage (Min)
4000V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
......
Recommended Operating Conditions
a...>...
�)>
......
Free Air Ambient Temperature
aw >
Military
- 55�C to + 125�C
)>
Commercial
0�Cto +70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
VrH VrL Veo.
Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage
54F/74F Min Typ Max 2.0
0.8 -1.2
Units
v
v v
Vee
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal Min lrN = -18 mA
VoH
Output HIGH
Voltage
54F 10% Vee 2.5
74F 10% Vee 2.5
74F 5% Vee
2.7
loH = -1 mA
v Min
Vol
Output LOW
Voltage
54F 10% Vee 74F 10% Vee
0.5 0.5
v
loL = 20 mA Min
lrH
Input HIGH
54F
Current
74F
20.0
VrN = 2.7V
5.0
�A Max
lsvr
Input HIGH Current 54F
Breakdown Test
74F
100
�A
Max VrN = 7.0V
7.0
leEX
Output HIGH
54F
Leakage Current
74F
250 50
�A
Max VouT =Vee
Vro
Input Leakage
74F
4.75
Test
v
0.0 lro = 1.9 �A
All Other Pins Grounded
loo
Output Leakage 74F
Circuit Current
3.75
�A
0.0 Vroo = 150 mV
All Other Pins Grounded
lrL
Input LOW Current
los
Output Short-Circuit Current
-0.6 mA Max VrN = 0.5V (CEP, CP, MR, Po-P3) -1.2 mA Max VrN = 0.5V (CET, PE, SR)
-60
-150 mA Max VouT = ov
Ice
Power Supply Current
37
55
mA Max
4-125
<C
C")
�.C.D-
<..C-
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
74F
54F
74F
.C.D-
Symbol
Parameter
TA= +25�C Vee= +5.0V
CL= 50pF
TA, Vee= Mii CL= 50 pF
TA, Vee= Com CL= 50pF
Units
Fig. No.
Min
Typ
Max
Min
Max
Min
Max
fmax
Maximum Count Frequency 100
120
75
90
MHz 2-1
tPLH
Propagation Delay
3.5
5.5
7.5
3.5
9.0
3.5
8.5
tPHL
CP to On (PE Input HIGH)
3.5
7.5
10.0
3.5
11.5
3.5
11.0
ns 2-3
tPLH
Propagation Delay
4.0
6.0
8.5
4.0
10.0
4.0
9.5
tPHL
CP to On (PE Input LOW)
4.0
6.0
8.5
4.0
10.0
4.0
9.5
tPLH tPHL
Propagation Delay CPtoTC
5.0
10.0
14.0
5.0
16.5
5.0
15.0
ns 2-3
5.0
10.0
14.0
5.0
15.5
5.0
15.0
tPLH tPHL
Propagation Delay CETtoTC
2.5
4.5
7.5
2.5
9.0
2.5
8.5
ns 2-3
2.5
4.5
7.5
2.5
9.0
2.5
8.5
tPHL
Propagation Delay MR to On ('F161A)
5.5
9.0
12.0
5.5
14.0
5.5
13.0
ns 2-3
tPHL
Propagation Delay MR to TC ('F161A)
4.5
8.0
10.5
4.5
12.5
4.5
11.5
ns 2-3
AC Operating Requirements: See Section 2 for Waveforms
Symbol
Parameter
ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) tw(H) tw(L) tw(H) tw(L) tw(L)
tree
Setup Time, HIGH or LOW Pn toCP
Hold Time, HIGH or LOW Pn to CP
Setup Time, HIGH or LOW PE or SR toCP
Hold Time, HIGH or LOW PE or SR to CP
Setup Time, HIGH or LOW CEP or CET to CP
Hold Time, HIGH or LOW CEP or CET to CP
Clock Pulse Width (Load) HIGH or LOW
Clock Pulse Width (Count) HIGH or LOW
MR Pulse Width, LOW ('F161A)
Recovery Time MR to CP ('F161A)
74F
TA= +25�C Vee= +5.0V
Min
Max
5.0 5.0
2.0 2.0
11.0 8.5
2.0 0
11.0 5.0
0 0
5.0 5.0
4.0 6.0
5.0
6.0
54F
TA, Vee= Mil
Min
5.5 5.5
2.5 2.5
13.5 10.5
3.6 0
13.0 6.0
0 0
5.0 5.0
5.0 8.0
Max
5.0
6.0
74F
TA, Vee= Com
Min
Max
5.0 5.0
2.0 2.0
11.5 9.5
2.0 0
11.5 5.0
0 0
5.0 5.0
4.0 7.0
5.0
Units
Fig. No.
ns
2-6
ns
2-6
ns
2-6
ns
2-4
ns
2-4
ns
2-4
6.0
ns
2-6
4-126
~National
~Semiconductor
54F/74F164A
Serial-In, Parallel-Out Shift Register
General Description
The 'F164A is a high-speed 8-bit serial-in/parallel-out shift register. Serial data is entered through a 2-input AND gate synchronous with the LOW-to-HIGH transition of the clock. The device features an asynchronous Master Reset which clears the register, setting all outputs LOW independent of the clock. The 'F164A is a faster version of the 'F164.
Features
� Typical shift frequency of 90 MHz � Asynchronous Master Reset � Gated serial data input � Fully synchronous data transfers � Guaranteed 4000V min ESD protection � 'F164A is a faster version of the 'F164
Ordering Code: see section 5 Logic Symbols
MR CP
TL/F/10613-1
IEEE/IEC
SRGB
MR
CP A
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
A 1 B
Oo 01 4 02 5 03 GND
14 Vee 13 07 12 05 11 05
10 o,.
9 i.iR
8 CP
TL/F/10613-2
Pin Assignment for LCC
r0n2
NmC r0n1
NC
rn
r0n0
G~~:o~:
NC (j]
[I]NC
CP li1J
gQj Vee
MR llll
l!fil01
~ ffID[j]J[Z]!iID o4 NC Os NC 05
TL/F/10613-3
TL/F/10613-4
Unit Loading/Fan Out: See Section 2 tor U.L. definitions
Pin Names
A,B CP MR
Oo-07
Description
Data Inputs Clock Pulse Input (Active Rising Edge) Master Reset Input (Active LOW) Outputs
54F/74F
U.L.
Input l1Hll1L
HIGH/LOW Output loHlloL
1.0/1.0 1.0/1.0 1.0/1.0 50/33.3
20 �A/-0.6 mA 20 �A/-0.6 mA 20 �A/-0.6 mA -1 mA/20mA
4-127
Functional Description
The 'F164A is an edge-triggered 8-bit shift register with serial data entry and an output from each of the eight stages. Data is entered serially through one of two inputs (A or B); either of these inputs can be used as an active HIGH Enable for data entry through the other input. An unused input must be tied HIGH. Each LOW-to-HIGH transition on the Clock (CP) input shifts data one place to the right and enters into Oo the logical AND of the two data inputs (A� B) that existed before the rising clock edge. A LOW level on the Master Reset (MR) input overrides all other inputs and clears the register asynchronously, forcing all Q outputs LOW.
Logic Diagram
Mode Select Table
Operating Mode
Reset (Clear)
Inputs MR A B
L xx
Outputs
Oo 01-07
L
L-L
Shift
H
I
I
L
qo-qs
H
I
h
L
qo-qs
H
h
I
L
qo-qs
H
h h
H
qo-qs
H(h) = HIGH Voltage Levels
L(I) = LOW Voltage Levels
X = Immaterial q0 = Lower case letters indicate the state of the referenced input or output one setup time prior to the LOW-to-HIGH clock transition.
~ TL/F/10613-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-128
Absolute Maximum Ratings (Note 1)
If MilitaryI Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for avallablllty and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
-55�C to+ 175�C
Vee Pin Potential to Ground Pin
-0.5V to + 7.0V
Input Voltage (Note 2)
-0.5Vto +7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5VtoVee -0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
ESD Last Passing Voltage (Min)
4000V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +10�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
54F/74F Min Typ Max
Units Vee
Conditions
V1H
Input HIGH Voltage
V1L
Input LOW Voltage
Veo
Input Clamp Diode Voltage
2.0
v
Recognized as a HIGH Signal
0.8
v
Recognized as a LOW Signal
-1.2
v
Min l1N = -18 mA
VoH
Output HIGH
Voltage
54F 10% Vee 2.5
74F 10% Vee 2.5
74F5% Vee
2.7
loH = -1 mA
v
Min loH = -1 mA
loH = -1 mA
Vol
Output LOW
Voltage
54F 10% Vee 74F 10% Vee
0.5
loL = 20 mA
0.5
v
Min IOL = 20 mA
l1H
Input HIGH
54F
Current
74F
20.0
5.0
�A Max V1N = 2.7V
lsv1
Input HIGH Current 54F
Breakdown Test
74F
100
�A Max V1N = 7.0V
7.0
leEx
Output HIGH
54F
Leakage Current
74F
250 50
�A Max Vour =Vee
V10
Input Leakage
74F
4.75
Test
110 = 1.9 �A
v
0.0
All other pins grounded
loo
Output Leakage
74F
Circuit Current
3.75
�A
0.0
V100 = 150 mV All other pins grounded
l1L
Input LOW Current
los
Output Short-Circuit Current
lee
Power Supply Current
-0.6
mA
Max V1N = 0.5V
-60
-150 mA Max Vour =av
CP =HIGH
35
55
mA
Max MR = GND, A, B = GND
4-129
<
~-.::I' AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
fmax tPLH tPHL tPHL
Maximum Clock Frequency
Propagation Delay CPtoOn
Propagation Delay MR to On
74F
TA= +25�C Vee= +5.0V
CL= 50 pF
Min
Typ
Max
80
120
3.0
4.8
7.5
3.5
5.0
8.0
5.0
7.0
10.0
54F
TA, Vee= Mil CL= 50pF
Min
Max
74F
TA, Vee= Com Units Fig.
CL= 50 pF
No.
Min
Max
80
MHz 2-1
3.0
7.5
ns 2-3
3.5
8.0
5.0
10.5
ns 2-3
AC Operating Requirements: See Section 2 tor waveforms
Symbol
Parameter
t5 (H) t5 (L) th(H) th(L)
lw(H) lw(L)
tw(L)
tree
Setup Time, HIGH or LOW AorB toCP
Hold Time, HIGH or LOW A or B to CP
CP Pulse Width HIGH or LOW
MR Pulse Width, LOW
Recovery Time MR to CP
74F
TA= +25�C Vee= +5.0V
Min
Max
4.5 4.0
1.0 1.0
4.0 7.0
4.0
5.0
54F
TA, Vee= Mil
Min
Max
74F
TA, Vee= Com
Min
Max
4.5 4.0
1.0 1.0
4.0 7.0
4.0
5.0
Units Fig. No.
ns
2-6
ns
2-4
ns
2-4
ns
2-6
4-130
.....
O'>
~~SNemaitcoinoduncatolr
Q)
..�...
cOo'>
54F/74F168 � 54F/74F169 4-Stage Synchronous Bidirectional Counters
General Description
The 'F168 and 'F169 are fully synchronous 4-stage up/ down counters. The 'F168 is a BCD decade counter; the 'F169 is a modulo-16 binary counter. Both feature a preset capability for programmable operation, carry lookahead for easy cascading and a U/D input to control the direction of counting. All state changes, whether in counting or parallel loading, are initiated by the LOW-to-HIGH transition of the clock.
Features
� Asynchronous counting and loading � Built-in lookahead carry capability � Presettable for programmable operation
Ordering Code: see section 5 Logic Symbols
PE Po P1 P2 P3
U/D
CEP
TC
CET
CP Oo 01 02 03
TL/F/9488-3
IEEE/IEC 'F168
PE
PE
U/fi
U/D
CET
3,5CT=9
TC
CET
CEP
4,5,CT=O
CEP
CP
2,3,5,6+ /C7
CP
Po
Oo
Po
P1
01
P1
P2
02
P2
P3
03
P3
TL/F/9488-8
'F169
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
U/D
CP 2 Po 3 P1 4 P2 5 P3 6 CEP 7 GND 8
16 Vee
15 TC
14 Oo 13 01 12 02 11 03 10 CET
PE
TL/F/9488-1
TC
Oo 01 02 03
TL/F/9488-9
Pin Assignment for LCC
P3 P2 NC P1 Po
[[] mmmm
CEP []]
GND ITQ] NC[]]
PE [J1J CET !Til
[I]CP
[l]U/D
[jJ NC ~Vee
[l]J TC
[j][filfil][j][j]] 03 02 NC 01 Oo
TL/F/9488-2
m
4-131
,cO..o>..
�,cc..oo..
Unit Loading/Fan Out: see Section 2 for U.L. definitions
54F/74F
Pin Names
Description
U.L.
Input l1Hll1L
HIGH/LOW Output loHlloL
CEP CET CP Po-P3 PE U/D Oo-03 TC
Count Enable Parallel Input (Active LOW) Count Enable Trickle Input (Active LOW) Clock Pulse Input (Active Rising Edge) Parallel Data Inputs Parallel Enable Input (Active LOW) Up-Down Count Control Input Flip-Flop Outputs Terminal Count Output (Active LOW)
1.0/1.0 1.0/2.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 50/33.3 50/33.3
20 �A/ - 0.6 mA 20 �A/ -1.2 mA 20 �A/-0.6 mA 20 �A/-0.6 mA 20 �A/-0.6 mA 20 �A/ - 0.6 mA -1 mA/20mA -1 mA/20mA
Functional Description
The 'F168 and 'F169 use edge-triggered J-K type flip-flops
the 'F169) in the Count Up mode. The TC output state is not
and have no constraints on changing the control or data
a function of the Count Enable Parallel (CEP) input level.
input signals in either state of the clock. The only require-
The TC output of the 'F168 decade counter can also be
ment is that the various inputs attain the desired state at
LOW in the illegal states 11, 13, and 15, which can occur
least a setup time before the rising edge of the clock and
when power is turned on or via parallel loading. If an illegal
remain valid for the recommended hold time thereafter. The
state occurs, the 'F168 will return to the legitimate se-
parallel load operation takes precedence over other opera-
quence within two counts. Since the TC signal is derived by
tions, as indicated in the Mode Select Table. When PE is
decoding the flip-flop states, there exists the possibility of
LOW, the data on the Po-P3 inputs enters the flip-flops on
decoding spikes on TC. For this reason the use of TC as a
the next rising edge of the clock. In order for counting to
clock signal is not recommended (see logic equations be-
occur, both CEP and CET must be LOW and PE must be
low).
HIGH; the U/D input then determines the direction of counting. The Terminal Count (TC) output is normally HIGH and goes LOW, provided that CET is LOW, when a counter reaches zero in the Count Down mode or reaches 9 (15 for
1) Count Enable = CEP � CET � PE 2) Up: ('F168): TC = Oo � 01 � 02 � 03 � (Up) � CET
('F169): TC = Oo � 01 � 02 � 03 �(Up)� CET
3) Down: TC = Oo � 01 � 02 � 03 � (Down) � CET
Logic Diagram
'F168
PE ............
Po
P1
P2
P3
_-v~
CEP
ffi
~ ~ ,,.
---
----
T ,.l;Q..
;-fib~
~
r~
r--
~
~ ~ I
~~ l
~
4-4-
~
LO T
I
~
BTl-t-
t--
..... ~
~ l i--B: "l
J
r;:t
~ -v
CP ..........
i=J
L.:b UPfj1-t-i
l
ON
t
a;
1 ~
;
I XI
l~ J CP :
�
F
>
B F I - -1 - - '
,trt= UP
ON DETAIL A EN
a; 0
t----
DETAIL A
1--
1---
tr
t---
1---
DETAIL A
----------t---'---Q-
~)'
~7
~7
~~
Oo
01
02
03
TL/F/9488-4
Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-132
......
en
Logic Diagram (Continued)
_bk PE _.....
m -y
Po
'F169
P1
P2
P3
QC)
..�....
ceon
~ m
-.....
--- ---- ------� I ~ 0 ~ T AT! 1f x!(ril I I
I I
!i!l'
~,....
CP .....
...... :
�v=1 UP~1-tJ
J
:~ r~
CP
I =o: :r
:ti
1
l~ :J CP
~
F,..'
.....
LO T BTt---'
ert-
UP
1----
t r ON DETAIL A ENr
a;
Q
1----
.....
1f;E
DETAIL A
.....
III
~
t--
t-
t---
tr
DETAIL A
t---
wa '"""'\_ l n J :J rr:I
0
--------- ~ -----Q-
~7
~7
~7
~7
Oo
o,
02
03
TL/F/9466-5
Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Mode Select Table
PE
CEP
CET
U/D
Action on Rising Clock Edge
L
x
x
x
Load (Pn --+ On)
H = HIGH Voltage Level
H
L
L
L = LOW Voltage Level
H
Count Up (Increment)
X = Immaterial
H
L
L
L
Count Down (Decrement)
H
H
x
x
No Change (Hold)
H
x
H
x
No Change (Hold)
State Diagrams
'F168
'F169
� - � Count Down -count Up
TL/F/9466-6
4-133
� - � Count Down -count Up
TL/F/9466-7
cO...o>..
�cc...oo..
Absolute Maximum Ratings (Note 1)
If MilitaryI Aerospace specified devices are required, please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Storage Temperature
-65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
-55�C to + 175�C
Vcc Pin Potential to Ground Pin
-0.5Vto +7.0V
Input Voltage (Note 2)
-0.5Vto +7.0V
Input Current (Note 2)
-30 mA to + 5.0 mA
Voltage Applied to Output
in HIGH State (with Vee = OV)
Standard Output TRI-STATE� Output
-0.5VtoVcc -0.5V to+ 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
V1H V1L Vco VoH
VoL l1H lsv1 lcEX V10 loo l1L
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 74F 10% Vee 74F 5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage 74F
Test
Output Leakage 74F
Circuit Current
Input LOW Current
los
Output Short-Circuit Current
lccL
Power Supply Current
54F/74F Min Typ Max 2.0
0.8 -1.2
2.5 2.5 2.7
0.5 0.5 20.0 5.0 100 7.0 250 50
4.75
3.75
-0.6 -1.2
-60
-150
35
52
Units
v v v v
v
�A
�A
�A
v
�A
mA mA mA
Vee
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal Min l1N = -18mA loH = -1 mA Min loH = -1 mA loH = -1 mA IQL = 20mA Min loL = 20mA Max V1N = 2.7V
Max V1N = 7.0V
Max VouT =Vee
0.0 110 = 1.9 �A All Other Pins Grounded
0.0 V100 = 150 mV All Other Pins Grounded V1N = 0.5V (except GET)
Max V1N = 0.5V (GET)
Max VouT = ov
Max Vo= LOW
4-134
'F168
�_...
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
O> CD
74F
54F
74F
Symbol
Parameter
TA= +25�C Vee= +5.0V
CL= 50 pF
TA, Vee= Mil CL= 50 pF
TA, Vee= Com CL= 50 pF
Fig. Units
No.
Min
Typ
Max
Min
Max
Min
Max
fmax
tPLH tPHL
tPLH tPHL
tPLH tPHL
tPLH tPHL
Maximum Count Frequency
100
115
6.0
90
Propagation Delay
3.0
CP to On (PE HIGH or LOW)
4.0
6.5
8.5
3.0
12.0
3.0
9.0
11.5
4.0
16.0
4.0
Propagation Delay CPtoTC
5.5
12.0
15.5
5.5
20.0
5.5
4.0
8.5
11.0
4.0
15.0
4.0
Propagation Delay CETtoTC
2.5
4.5
6.0
2.5
9.0
2.5
2.5
6.0
8.0
2.5
12.0
2.5
Propagation Delay U/DtoTC
3.5
8.5
11.0
3.5
16.0
3.5
4.0
12.5
16.0
4.0
14.0
4.0
MHz 2-1
9.5
ns 2-3
13.0
17.0
ns 2-3
12.5
7.0
ns 2-3
9.0
12.5 ns 2-3
18.0
AC Operating Requirements: See Section 2 for Waveforms
Symbol
Parameter
t 5 (H) t 5 (L)
th(H) th(L)
t 5 (H) t 5 (L)
th(H) th(L)
t 5 (H) t5 (L)
th(H) th(L)
t5 (H) t5 (L)
th(H) th(L)
tw(H) tw(L)
Setup Time, HIGH or LOW Pn to CP
Hold Time, HIGH or LOW Pn to CP
Setup Time, HIGH or LOW CEP or CET to CP
Hold Time, HIGH or LOW CEP or CET to CP
Setup Time, HIGH or LOW PEtoCP
Hold Time, HIGH or LOW PEtoCP
Setup Time, HIGH or LOW U/Dto CP
Hold Time, HIGH or LOW U/Dto CP
CP Pulse Width HIGH or LOW
74F
TA= +25�C Vee= +5.0V
Min
Max
4.0 4.0
3.0 3.0
5.0 5.0
0 0
8.0 8.0
0 0
11.0 16.5
0 0
5.0 5.0
54F
TA, Vee= Mil
Min
Max
4.5 4.5
3.5 3.5
8.0 8.0
0.0 1.0
10.0 10.0
1.0 0
14.0 12.0
0 0
6.0 9.0
74F
TA, Vee= Com
Min
Max
4.5 4.5
3.5 3.5
6.0 6.0
0 0
9.0 9.0
0 0
12.5 18.0
0 0
5.5 5.5
Fig. Units
No.
ns
2-6
ns
2-6
ns
2-6
ns
2-6
ns
2-4
4-135
O>
�C...D.. 'F169
co
.C..D.. AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
74F
54F
74F
Symbol
Parameter
TA= +25�c Vee= +5.0V
CL= 50pf
TA, Vee= Mil CL= 50 pf
TA, Vee= Com Units Fig.
CL= 50pf
No.
Min
Typ
Max
Min
Max
Min
Max
fmax
Maximum Count Frequency
90
60
70
MHz 2-1
tPLH
Propagation Delay
3.0
6.5
8.5
3.0
12.0
3.0
9.5
ns 2-3
tPHL
CP to On (PE HIGH or LOW) 4.0
9.0
11.5
4.0
16.0
4.0
13.0
tPLH
Propagation Delay
tPHL
CPtoTC
tPLH
Propagation Delay
tPHL
CETtoTC
tPLH
Propagation Delay
tPHL
U/D to TC
5.5
12.0
15.5
5.5
20.0
5.5
17.5
ns 2-3
4.0
8.5
12.5
4.0
15.0
4.0
13.0
2.5
4.5
6.5
2.5
9.0
2.5
7.0
ns 2-3
2.5
8.5
11.0
2.5
12.0
2.5
12.0
3.5
8.5
11.5
3.5
16.0
3.5
12.5
ns 2-3
4.0
8.0
12.0
4.0
14.0
4.0
13.0
AC Operating Requirements: See Section 2 for Waveforms
Symbol
Parameter
t8 (H) t5 (L)
th(H) th(L)
t8 (H) t5 (L)
th(H) th(L)
t8 (H) t5 (L)
th(H) th(L)
t8 (H) t5 (L)
th(H) th(L)
tw(H) tw(L)
Setup Time, HIGH or LOW Pn toCP
Hold Time, HIGH or LOW Pn to CP
Setup Time, HIGH or LOW CEP or CET to CP
Hold Time, HIGH or LOW CEP or CET to CP
Setup Time, HIGH or LOW PEtoCP
Hold Time, HIGH or LOW PE to CP
Setup Time, HIGH or LOW U/Dto CP
Hold Time, HIGH or LOW U/Dto CP
CP Pulse Width HIGH or LOW
74F
TA= +25�c Vee= +5.0V
Min
Max
4.0 4.0
3.0 3.0
7.0 5.0
0 0.5
8.0 8.0
1.0 0
11.0 7.0
0 0
4.0 7.0
54F
TA, Vee= Mil
Min
Max
4.5 4.5
3.5 3.5
8.0 8.0
0 1.0
10.0 10.0
1.0 0
14.0 12.0
0 0
6.0 9.0
74F
TA, Vee= Com
Min
Max
4.5 4.5
3.5 3.5
8.0 6.5
0 0.5
9.0 9.0
1.0 0
12.5 8.5
0 0
4.5 8.0
Units
Fig. No.
ns
2-6
ns
2-6
ns
2-6
ns
2-6
ns
2-4
4-136
~National
~Semiconductor
54F/74F174 Hex D Flip-Flop with Master Reset
General Description
The 'F174 is a high-speed hex D flip-flop. The device is used primarily as a 6-bit edge-triggered storage register. The information on the D inputs is transferred to storage during the LOW-to-HIGH clock transition. The device has a Master Reset to simultaneously clear all flip-flops.
Features
� Edge-triggered D-type inputs � Buffered positive edge-triggered clock � Asynchronous common reset � Guaranteed 4000V minimum ESD protection
Ordering Code: see sections
Logic Symbols
Connection Diagrams
CP MR
TL/F/9489-3
IEEE/IEC
MR
CP
Do
Oo
01
01
Dz
Oz
03
03
04
04
Ds
05
TL/F/9489-5
Pin Assignment for DIP, SOIC and Flatpak
Mii Oo Do 3
D, 4
01 5
02
02 GND 8
16 Vee 15 05 14 05 13 04 12 04
TL/F/9489-1
Pin Assignment forLCC
~ 01 NC D1 Do
rni::z::m1r:film
GNO D liQzJ [ [ I D [ I J O[1]oMR
NC [j]
[I]NC
CP Ill)
@Vee
03 ILll
l!filOs
[j}]li]jj]]lllJ(j]]
~ 04 NC D4 Os
TL/F/9489-2
Unit Loading/Fan Out: See Section 2 for u.L. Definitions
Pin Names
D0 - D s CP MR Oo-Os
Description
Data Inputs Clock Pulse Input (Active Rising Edge) Master Reset Input (Active LOW) Outputs
54F/74F
U.L.
Input lrHlllL
HIGH/LOW Output loHlloL
1.0/1.0 1.0/1.0 1.0/1.0 50/33.3
20 �A/ - 0.6 mA 20 �A/ -0.6 mA 20 �A/-0.6 mA -1 mA/20 mA
4-137
Functional Description
The 'F174 consists of six edge-triggered D flip-flops with individual D inputs and Q outputs. The Clock (CP) and Master Reset (MR) are common to all flip-flops. Each D input's state is transferred to the corresponding flip-flop's output following the LOW-to-HIGH Clock (CP) transition. A LOW input to the Master Reset (MR) will force all outputs LOW independent of Clock or Data inputs. The 'F174 is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements.
Logic Diagram
Truth Table
Inputs
MR
CP
Dn
L
x
x
H
_r
H
H
_r
L
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial ../" = LOW-to-HIGH Clock Transition
Outputs
On L H L
Do
CD
CD
CD
CD
CD
CD
Oo TL/F /9489-4 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-138
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�c
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5Vto +7.0V
Input Voltage (Note 2)
-0.5V to + 7.0V
Input Current (Note 2)
-30 mA to + 5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5VtoVee -0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
ESD Last Passing Voltage (Min)
4000V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
i-ree Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�cto +70�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
V1H
Input HIGH Voltage
V1L
Input LOW Voltage
Veo
Input Clamp Diode Voltage
54F/74F Min Typ Max
Units Vee
Conditions
2.0
v
Recognized as a HIGH Signal
0.8
v
Recognized as a LOW Signal
-1.2
v
Min l1N = -18mA
VoH
Output HIGH
Voltage
54F 10% Vee 2.5
74F 10% Vee 2.5
74F5% Vee
2.7
loH = -1 mA
v
Min loH = -1 mA
loH = -1 mA
Vol
Output LOW
Voltage
54F 10% Vee 74F 10% Vee
0.5 0.5
v
Min loL = 20 mA
loL = 20 mA
l1H
Input HIGH
54F
Current
74F
20.0
�A
Max V1N = 2.7V
5.0
lsv1
Input HIGH Current 54F
Breakdown Test
74F
100 7.0
�A
Max V1N = 7.0V
leEx
Output HIGH
54F
Leakage Current
74F
250
�A
Max Vour =Vee
50
V10
Input Leakage
74F
4.75
Test
v
0.0 110 = 1.9 �A
All Other Pins Grounded
loo
Output Leakage
74F
Circuit Current
3.75
�A
0.0 V100 = 150 mV All Other Pins Grounded
l1L
Input LOW Current
los
Output Short-Circuit Current
-0.6
mA
Max V1N = 0.5V
-60
ov -150 mA Max Vour =
leeH
Power Supply Current
30
45
mA
Max CP=..../
Dn =MR= HIGH
leeL
Power Supply Current
30
45
mA Max Vo= LOW
4-139
..'l..l..l.:..t..'
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
fmax
Maximum Clock Frequency
tPLH
Propagation Delay
tPHL
CPtoOn
tPHL
Propagation Delay
MR to On
74F
TA= +25�C Vee= +5.0V
CL= 50 pF
Min
Typ
Max
80
3.5
5.5
8.0
4.0
7.0
10.0
5.0
10.0
14.0
54F
TA, Vee= Mil CL= 50 pF
Min
Max
70
3.0
10.0
4.0
12.0
5.0
16.0
74F
TA, Vee== Com CL= 50pF
Fig. Units No.
Min
Max
80
MHz 2-1
3.5
9.0
ns 2-3
4.0
11.0
5.0
15.0
ns 2-3
AC Operating Requirements: See Section 2 for Waveforms
Symbol
Parameter
t5 (H) t5 (L) th(H) th(L)
tw(H) tw(L)
tw(L)
tree
Setup Time, HIGH or LOW Dn to CP Hold Time, HIGH or LOW Dn to CP CP Pulse Width HIGH or LOW
MR Pulse Width, LOW
Recovery Time, MR to CP
74F
TA= +25�C Vee= +5.0V
Min
Max
4.0 4.0
0 0
4.0 6.0
5.0
5.0
54F
TA, Vee= Mil
Min
Max
5.0 5.0
2.0 2.0
5.0 7.5
6.5
6.0
74F
TA, Vee= Com
Min
Max
4.0 4.0
0 0
4.0 6.0
5.0
5.0
Fig. Units
No.
ns
2-6
ns
2-4
ns
2-4
2-6
4-140
~National
~Semiconductor
54F/74F175 Quad D Flip-Flop
General Description
The 'F175 is a high-speed quad D flip-flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D inputs is stored during the LOW-to-HIGH clock transition. Both true and complemented outputs of each flip-flop are provided. A Master Reset input resets all flip-flops, independent of the Clock or D inputs, LOW.
Features
� Edge-triggered D-type inputs � Buffered positive edge-triggered clock � Asynchronous common reset � True and complement output
Ordering Code: see section 5
Logic Symbols
IEEE/I EC
MR
CP
Oo Do
Oo
o,
o,
o,
02 D2
02
03 03
03
TL/F/9490-5
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
MR
Oo Oo 3 Do
D1
o, 6
o, 7
GND 8
16 Vee 15 03 1-4 03 13 D3 12 Dz 11 02 10 02 9 CP
TL/F/9490-1
Pin Assignment for LCC
o01ocD:1z:NrnC:r0no:i0mo
G~:o~~
NC (j]
[i]NC
CPIJ1.]
~Vee
Oz Ii]
[2103
~~lifillillMI
Oz~NC~03
TL/F/9490-2
Do CP MR
TL/F/9490-3
Unit Loading/Fan Out: See Section 2 tor u.L Definitions
Pin Names
Do-D3 CP MR Oo-03 Oo-03
Description
Data Inputs Clock Pulse Input (Active Rising Edge) Master Reset Input (Active LOW) True Outputs Complement Outputs
54F/74F
U.L.
Input l1Hll1L
HIGH/LOW Output loHlloL
1.0/1.0 1.0/1.0 1.0/1.0 50/33.3 50/33.3
20 �A/ -0.6 mA 20 �A/ - 0.6 mA 20 �Al -0.6 mA -1 mA/20mA -1 mA/20 mA
4-141
Functional Description
The 'F175 consists of four edge-triggered D flip-flops with individual D inputs and Q and Q outputs. The Clock and Master Reset are common. The four flip-flops will store the state of their individual D inputs on the LOW-to-HIGH clock (CP) transition, causing individual Q and Q outputs to follow. A LOW input on the Master Reset (MR) will force all Q outputs LOW and Q outputs HIGH independent of Clock or Data inputs. The 'F175 is useful for general logic applications where a common Master Reset and Clock are acceptable.
Logic Diagram
MR CP
Truth Table
Inputs
MR
CP
Dn
L
x
x
H
_/
H
H
_/
L
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial ../ = LOW-to-HIGH Clock Transition
D,
Outputs
On
Qn
L
H
H
L
L
H
D
Q
--~DICP
Q
CD
D
Q
CP
Q
CD
D
Q
CP
Q
CD
D
Q
CP
Q
CD
Oo Oo
TL/F/9490-4 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-142
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 15o�c
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to + 7.0V
Input Voltage (Note 2)
-0.5V to + 7.0V
Input Current (Note 2)
-30 mA to + 5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5VtoVee -0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or currant limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C o�cto +70�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
V1H
Input HIGH Voltage
V1L
Input LOW Voltage
Veo
Input Clamp Diode Voltage
54F/74F Min Typ Max 2.0
0.8 -1.2
Units Vee
v
v
v
Min
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal l1N = -18mA
VoH
Output HIGH
Voltage
54F 10% Vee 2.5
74F 10% Vee 2.5
74F5% Vee
2.7
loH = -1 mA
v
Min loH = -1 mA
loH = -1 mA
VoL
Output LOW
Voltage
54F 10% Vee 74F 10% Vee
0.5
v
Min loL = 20 mA
0.5
loL = 20 mA
l1H
Input HIGH
54F
Current
74F
20.0
�A
Max V1N = 2.7V
5.0
lsv1
Input HIGH Current 54F
Breakdown Test
74F
100
�A
Max V1N = 7.0V
7.0
leEX
Output HIGH
54F
Leakage Current
74F
250
�A
Max Vour =Vee
50
V10
Input Leakage
74F
4.75
Test
v
0.0 110 = 1.9 �A
All Other Pins Grounded
loo
Output Leakage 74F
Circuit Current
3.75
�A
0.0 V100 = 150 mV
All Other Pins Grounded
l1L
Input LOW Current
-0.6
mA
Max V1N = 0.5V
los
Output Short-Circuit Current
-60
-150 mA Max Vour = ov
lee
Power Supply Current
22.5 34.0
CP=..../ mA Max
Dn =MR= HIGH
4-143
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
74F
54F
74F
Symbol
Parameter
TA= +25�C Vee= +5.0V
CL= 50pF
Min
Typ
Max
TA, Vee= Mii CL= 50pF
Min
Max
TA, Vee= Com CL= 50pF
Min
Max
fmax tPLH tPHL tPHL
Maximum Clock Frequency 100
Propagation Delay
4.0
CPto On or On
4.0
Propagation Delay 4.5
MR to On
140
80
5.0
6.5
3.5
6.5
8.5
4.0
9.0
11.5
4.5
100
8.5
4.0
7.5
10.5
4.0
9.5
15.0
4.5
13.0
tPLH
Propagation Delay
MR to On
4.0
6.5
8.0
4.0
11.0
4.0
9.0
Units
Fig. No.
MHz 2-1 ns 2-3 ns 2-3 ns 2-3
AC Operating Requirements: See Section 2 for Waveforms
Symbol
Parameter
t 5(H) t5(L) th(H) th(L)
tw(H) tw(L)
tw(L)
tree
Setup Time, HIGH or LOW Dn to CP
Hold Time, HIGH or LOW Dn toCP
CP Pulse Width HIGH or LOW
MR Pulse Width, LOW
Recovery Time, MR to CP
74F
TA= +25�C Vee= +5.0V
Min
Max
3.0 3.0
1.0 1.0
4.0 5.0
5.0
5.0
54F
TA, Vee= Mii
Min
Max
3.0 4.0
1.0 2.0
4.0 6.0
5.0
6.0
74F
TA, Vee= Com
Min
Max
3.0 3.0
1.0 1.0
4.0 5.0
5.0
5.0
Units
Fig. No.
ns
2-6
ns
2-4
ns
2-4
ns
2-6
4-144
.....
~National
.C..>..
U Semiconductor
54F/74F181 4-Bit Arithmetic Logic Unit
General Description
The 'F181 is a 4-bit Arithmetic logic Unit (ALU) which can perform all the possible 16 logic operations on two variables and a variety of arithmetic operations. It is 40% faster than the Schottky ALU and only consumes 30% as much power.
Features
� Full lookahead for high-speed arithmetic operation on long words
� Guaranteed 4000V minimum ESD protection
Ordering Code: see sections Logic Symbols
Connection Diagrams
Active-HIGH Operands
Active-LOW Operands
Pin Assignment for DIP, SOIC and Flatpak
en
M
So
A=B
s,
S2
S3
TL/F/9491-3
IEEE/I EC
TL/F/9491-4
Bo 1
Ao
S3 Sz S1 5 So 6
en 7 M 8
F'o 9 F1 10 F'2 11
GND 12
24 Vee 23 A1 22 B1 21 A2 20 B2 19 A3 18 B3 17 G
16 Cnu
15 p
14 A=B
13 F3
So S1 S2
}~ ALU (0 ... 15)CP (0 ... 15)CG
S3
6(P=O) Q
M
(0... 15)CO
en
Ao
(1)
Bo
A1
(2)
B1
Az
(4)
Bz
A3
(8)
B3
A=B Cnu
Fo F1 Fz F3
TL/F/9491-10
TL/F/9491-1
Pin Assignment for LCC
Fo M Cn NC So S1 S2
IIIl [QI rn [[] m!II rn
F1 li1I F2 Ii]
GND [11
NC~
F3 [j]]
A=BliZJ
p Ii]!
[I] S3
rn Ao rn iio
OJ NC
~Vee
Ill! A1 ~B1
[fil~~llll~~~
Cnu G B3 NC A3 B2 A2
TL/F/9491-2
4-145
T""
co
T"" Unit Loading/Fan Out: See Section 2 for U.L. definitions
Pin Names
Description
54F/74F
U.L.
Input l1Hll1L
HIGH/LOW Output loHllOL
Ao-A3 80-83 So-S3 M Cn Fo-F3 A=B
G p
Cn + 4
A Operand Inputs (Active LOW) B Operand Inputs (Active LOW) Function Select Inputs Mode Control Input Carry Input Function Outputs (Active LOW) Comparator Output Carry Generate Output (Active LOW) Carry Propagate Output (Active LOW) Carry Output
1.0/3.0 1.0/3.0 1.0/4.0 1.0/1.0 1.0/5.0 50/33.3 OC*/33.3 50/33.3 50/33.3 50/33.3
20 �A/-1.8 mA 20 �A/-1.8 mA 20 �A/ - 2.4 mA 20 �A/-0.6 mA 20 �A/-3.0 mA -1 mA/20mA
*/20 mA -1 mA/20 mA -1 mA/20 mA -1 mA/20mA
�oc-Open Collector
Functional Description
The 'F181 is a 4-bit high-speed parallel Arithmetic Logic Unit (ALU). Controlled by the four Function Select inputs (S0-S3) and the Mode Control input (M), it can perform all the 16 possible logic operations or 16 different arithmetic operations on Active HIGH or Active LOW operands. The Function Table lists these operations.
When the Mode Control input (M) is HIGH, all internal carries are inhibited and the device performs logic operations on the individual bits as listed. When the Mode Control input is LOW, the carries are enabled and the device performs arithmetic operations on the two 4-bit words. The device incorporates full internal carry lookahead and provides for either ripple carry between devices using the Cn + 4 output, or for carry lookahead between packages using the signals P (Carry Propagate) and G (Carry Generate). In the Add mode, P indicates that F is 15 or more, while G indicates
that Fis 16 or more. In the Subtract mode P indicates that F is zero or less, while G indicates that F is less than zero. P and G are not affected by carry in. When speed require-
ments are not stringent, the 'F181 can be used in a simple Ripple Carry mode by connecting the Carry output (Cn+4) signal to the Carry input (Cn) of the next unit. For high speed operation the device is used in conjunction with a carry lookahead circuit. One carry lookahead package is required for
each group of four 'F181 devices. Carry lookahead can be provided at various levels and offers high speed capability over extremely long word lengths.
The A= B output from the device goes HIGH when all four F outputs are HIGH and can be used to indicate logic equivalence over four bits when the unit is in the Subtract mode. The A= B output is open collector and can be wired AND with other A= B outputs to give a comparison for more than
four bits. The A= B signal can also be used with the Cn +4
signal to indicate A>B and A<B.
The Function Table lists the arithmetic operations that are performed without a carry in. An incoming carry adds a one to each operation. Thus, select code LHHL generates A minus B minus 1 (2s complement notation) without a carry in and generates A minus B when a carry is applied. Because subtraction is actually performed by complementary addition (1s complement), a carry out means borrow; thus a carry is generated when there is no underflow and no carry is generated when there is underflow. As indicated, this device can� be used with either active LOW inputs producing active LOW outputs or with active HIGH inputs producing active HIGH outputs. For either case the table lists the operations that are performed to the operands labeled inside the logic symbol.
4-146
Logic Diagram
...,
VI 0 VI
1.r ,J;'
1...:"'
lrD
1..C
0 llD
4-147
......
"I '
.C..X..>.
...CJ)
CJ)
~
I-
~
Q"i'
"O
c
0
~ ~ec.
CJ)
(ii
~
CJ)
.2
"O CJ) (/) ::l
CJ) .0
g
:"O;
~
"cO
"'(/)
g c
~
,..._...,
cCJ).
0
�~
..Q
0
~"c'
~
�
�
0
~
0
"O
,..._"'
CJ)
"�:O;;
e
c.
(/)
E
m
~
<II
'6
(/)
g �
* c
~
a~:
,,f'
,.... ,c..o.. Absolute Maximum Ratings (Note 1)
If MilitaryI Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�c
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5Vto +7.0V
Input Voltage (Note 2)
-0.5Vto +7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5VtoVee -0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
ESD Last Passing Voltage (Min)
4000V
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under
these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�cto +70�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
V1H
Input HIGH Voltage
V1L
Input LOW Voltage
Yeo
Input Clamp Diode Voltage
54F/74F Min Typ Max
Units Vee
Conditions
2.0
v
Recognized as a HIGH Signal
0.8
v
Recognized as a LOW Signal
-1.2
v
Min l1N = -18 mA
VoH
Output HIGH
Voltage
54F 10% Vee 2.5
74F 10% Vee 2.5
74F5% Vee
2.7
loH = -1 mA
v
Min loH = -1 mA
loH = -1 mA
Vol
Output LOW
Voltage
54F 10% Vee 74F 10% Vee
0.5
v
Min loL = 20 mA
0.5
loL = 20 mA
l1H
Input HIGH
54F
Current
74F
20.0 5.0
�A Max V1N = 2.7V
lsv1
Input HIGH Current 54F
Breakdown Test
74F
100 7.0
�A
Max V1N = 7.0V
lcEX
Output HIGH
54F
Leakage Current
74F
250
�A
Max VouT =Vee (Fn, G, P, Cn+4)
50
V10
Input Leakage Test
74F
4.75
v
lio = 1.9 �A 0.0
All Other Pins Grounded
loo
Output Leakage 74F
Circuit Current
3.75
�A
0.0 V100 = 150 mV
All Other Pins Grounded
l1L
Input LOW Current
-0.6
V1N = 0.5V (M)
-1.8 mA Max V1N = 0.5V (Ao, A1, A3, Bo, B1. B3)
-2.4
V1N = 0.5V (Sn, A2, B2)
-3.0
V1N = 0.5V (Cn)
los
Output Short-Circuit Current
-60
-150 mA Max VouT = OV (Fn. G, P, Cn+4)
loHC
Open Collector, Output OFF Leakage Test
250
�A
Min Vo= Vee(A = B)
lecH
Power Supply Current
43 65.0 mA Max Vo= HIGH
lccL
Power Supply Current
43 65.0 mA Max Vo= LOW
4-148
en
Ao Bo A1 B1 A2 82 A3 B3
en+4
So
A=B
'FIBI
S1
S2
S3
a. All Input Data Inverted
en
Ao Bo Al Bl A2 82 A3 83
en+4
I.I
So
A=8
'FIBI
S1
S2
S3 Fo
F1
F2
F3
b. All Input Data True
en
So
A=8
'F181
S1
S2
S3
c. A Input Data Inverted; B Input Data True
en
Ao Bo Al 81 A2 82 A3 B3
enu
So S1 S2 S3 Fa
'FIBI F1 F2
A=8 F3
d. A Input Data True; B Input Date Inverted
Table 5�2 'F181 Operation Tables
So
S1
S2
S3
Logic (M=H)
Arithmetic (M = L, Co= Inactive)
L
L
L
L
A
H
L
L
A�B
L
H
L
A+B
H
H
L
L
Logic "1"
L
L
H
L
A+B
H
L
H
L
8
L
H
H
L
A Gl B
H
H
H
L
A+B
L
L
L
H
A�B
H
L
L
H
L H
L
H
AGlB B
H
H
L
H
A+B
L
L
H
H
Logic "O"
H
L
H
H
A�B
L
H
H
H
A�B
H
H
H
H
A
A minus 1 A� B minus 1 A� B minus 1 minus 1 (2s comp.) Aplus(A + B) A � B plus (A + B) A minus B minus 1
A+B Aplus(A + B)
A plus B A � B plus (A + B)
A+B A plus A (2 x A)
A plus A� B A plus A� B
A
L
L
L
L
A
H
L
L
L
A+B
H
L
L
A�B
H
H
L
L
Logic "O"
L
L
H
L
A�B
H
L
H
L
8
L
H
H
L
AeB
H
H
H
L
A�B
L
L
L
H
A+B
H
L
L
H
AeB
L
H
L
H
B
H
H
L
H
A�B
L
L
H
H
Logic "1"
H
L
H
H
A+B
L
H
H
H
A+B
H
H
H
H
A
A A+B A+B minus 1 (2s comp.) A plus (A� B) A � B plus (A + B) A minus B minus 1 A� B minus 1 A plus A� B A plus B A � B plus (A + B) A� B minus 1 A plus A (2 x A) Aplus(A +B) Aplus(A + B) A minus 1
L
L
L
L
A
H
L
L
L
A+B
L
H
L
L
A�B
H
H
L
L
Logic "1"
L
L
H
L
A�B
H
L
H
L
B
L
H
H
L
Ae B
H
H
H
L
A+B
L
L
L
H
A+B
H
L
L
H
AeB
L
H
L
H
8
H
H
L
H
A+B
L
L
H
H
Logic "O"
H
L
H
H
A�B
L
H
H
H
A�B
H
H
H
H
A
A minus 1 A� B minus 1 A� B minus 1 minus 1 (2s comp.) A plus (A+ B) A � B plus (A + B)
A plus B A+B A plus (A+ B) A minus B minus 1 A � B plus (A + B) A+B AplusA(2 x A) A plus A� B A plus A� B
A
L
L
L
L
A
H
L
L
L
L
H
L
A�B
m
H
H
L
L
Logic "O"
L
L
H
L
A+B
H
L
H
L
B
L
H
H
L
m
H
H
H
L
A�B
L
L
L
H
A�B
H
L
L
H
AeB
L
H
L
H
8
H
H
L
H
A�B1
L
L
H
H
Logic .. .; ..
H
L
H
H
A+B
L
H
H
H
A+B
H
H
H
H
A
A A+B A+B minus 1 (2s comp.) A plus A� B A � B plus (A + B) A plus B A� B minus 1 A plus A� B A minus B minus 1 A � B plus (A + B) A� B minus 1 A plus A (2 x A) Aplus(A +B) Aplus(A + B) A minus 1
Arithmetic (M = L, Co= Active)
A A�B A�B Zero A plus (A + B) plus 1 A � B plus (A + B) plus 1 AminusB A+ Bplus 1 A plus (A + B plus 1 A plus B plus 1
A � Bplus (A + B) plus 1
A+ B plus 1 A plus A (2 x A) plus 1
A plus A � B plus 1 A plus A � B plus 1
A plus 1
A plus 1 A+ B plus 1 A+ Bplus 1
Zero A plus A � B plus 1 A � B plus (A + B) plus 1
A minus B A�B
A plus A � B plus 1 A plus B plus 1
A � B plus (A + B) plus 1 A�B
A plus A (2 x A) plus 1 A plus (A+ B) plus 1 A plus (A+ B) plus 1 A
A A�B A�B Zero A plus (A + B) plus 1
A � Bplus (A + B) plus 1
A plus B plus 1 A+ B plus 1 A plus (A + B) plus 1
A minusB A � B plus (A + B) plus 1
A+ Bplus 1 A plus A (2 x A) plus 1
A plus A � B plus 1 A plus A � B plus 1
A plus 1
A plus 1 A+ Bplus 1 A+ B plus 1
Zero A plus A � B plus 1
A � Bplus (A + B) plus 1
A plus B plus 1 A�B
A plus A � B plus 1 A minus B
A � Bplus (A + B) plus 1
A�B A plus A (2 x A) plus 1
A plus (A+ B) plus 1 A plus (A+ B) plus 1
A
..... c...o..
II
4-149
AC Electrical Characteristics: see Section 2 for waveforms and Load configurations
74F
54F
74F
Symbol
Parameter
Path
Mode
TA= +25�C Vee= +5.0V
CL= 50 pf
Min
Typ
Max
TA, Vee= Mil CL= 50 pf
Min
Max
TA, Vee= Com CL= 50pF
Min
Max
Propagation Delay
Cn to Cn + 4
3.0
6.4
8.5
3.0
10.0
3.0
9.5
3.0
6.1
8.0
3.0
9.5
3.0
9.0
Propagation Delay
5.0
10.0
13.0
5.0
15.5
5.0
14.0
A or B to Cn + 4
Sum
4.0
9.4
12.0
3.5
16.5
4.0
13.0
Propagation Delay
5.0
10.8
14.0
5.0
17.0
5.0
15.0
A or B to Cn + 4
Dif
5.0
10.0
13.0
4.0
15.0
5.0
14.0
Propagation Delay
3.0
6.7
8.5
2.5
16.0
3.0
9.5
Cn to F
Any
3.0
6.5
8.5
2.5
12.0
3.0
9.5
Propagation Delay
3.0
5.7
7.5
2.5
9.0
3.0
8.5
AorB orG
Sum
3.0
5.8
7.5
2.5
9.5
3.0
8.5
Propagation Delay
3.0
6.5
8.5
2.5
11.5
3.0
9.5
A orB to G
Dif
3.0
7.3
9.5
2.5
11.0
3.0
10.5
Propagation Delay
3.0
5.0
7.0
2.5
8.5
3.0
8.0
A or B to j5
Sum
3.0
5.5
7.5
3.0
9.5
3.0
8.5
Propagation Delay
3.0
5.8
7.5
2.5
11.0
3.0
8.5
A or B to j5
Dif
4.0
6.5
8.5
3.0
11.0
4.0
9.5
Propagation Delay
3.0
Ai or Bi to Fi
Sum 3.0
7.0
9.0
3.0
14.5
3.0
10.0
7.2
10.0
3.0
14.5
3.0
10.0
Propagation Delay
3.0
Ai or Bi to Fi
Dif 3.0
8.2
11.0
3.0
17.5
3.0
12.0
5.0
11.0
3.0
14.5
3.0
12.0
Propagation Delay
4.0
8.0
10.5
3.5
16.5
4.0
11.5
Any A or 8 to Any F Sum
4.0
7.8
10.0
4.0
13.5
4.0
11.0
Propagation Delay
4.5
Any A or B to Any F Dif
3.5
9.4
12.0
3.5
17.5
4.5
13.0
9.4
12.0
3.0
14.0
3.5
13.0
Propagation Delay
4.0
A or B to F
Logic
4.0
6.0
9.0
3.5
14.5
4.0
10.0
6.0
10.0
3.0
15.5
4.0
11.0
Propagation Delay
11.0
18.5
27.0
8.0
35.0
11.0
29.0
A or B to A = B
Dif
6.0
9.8
12.5
5.5
21.0
6.0
13.5
Units Fig. No.
ns 2-3 ns 2-3 ns 2-3 ns 2-3 ns 2-3 ns 2-3 ns 2-3 ns 2-3 ns 2-3 ns 2-3 ns 2-3 ns 2-3 ns 2-3 ns 2-3
4-150
U~NaStemiicoonnduactlor
54F/74F182
Carry Lookahead Generator
General Description
The 'F182 is a high-speed carry lookahead generator. It is generally used with the 'F181 or 'F381 4-bit arithmetic logic units to provide high-speed lookahead over word lengths of more than four bits.
Features
� Provides lookahead carries across a group of four ALUs
� Multi-level lookahead high-speed arithmetic operation over long word lengths
� Guaranteed 4000V minimum ESD protection
Ordering Code: see section 5 Logic Symbols
I E E E / I EC
ePG
en Z1
1, 2
en+x
1,2, 4
Po G2/Z10
3,4 5
en+y
Go Z3
1, 2,4, 6
P1 G4
3,4, 6 5, 6
en+z
G1 ZS
7
P2 G6
G2
Z7
P3 GB
G3 zg
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
G1 P1 Go 3 Po 4 G3 5
P3
p 7
GND 8
16 Vee 15 P2 14 G2 13 en 12 Cn+x 11 Cn+y 10 G
Cn+z
TL/F/9492-1
Pin Assignment for LCC
fi3 lfil
~ NC Po
mmrn
Go
m
pI]]
GND [QI NC[]]
Cn+z 1!11
GIi]
r[In]cP;1,
OJ NC
~Vee Ii]] P2
li][ill!rnlJ111i]] Cn+y Cn+x NC Cn G:z
TL/F/9492-2
en
TL/F/9492-3
Unit Loading/Fan Out: See Section 2 tor U.L. Definitions
Pin Names
Cn Go.G2 G1 G3 Po. P1 P2 P3 Cn+x-Cn+z G
p
Description
Carry Input Carry Generate Inputs (Active LOW) Carry Generate Input (Active LOW) Carry Generate Input (Active LOW) Carry Propagate Inputs (Active LOW) Carry Propagate Input (Active LOW) Carry Propagate Input (Active LOW) Carry Outputs Carry Generate Output (Active LOW) Carry Propagate Output (Active LOW)
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loHlloL
1.0/2.0 1.0/14.0 1.0/16.0 1.0/8.0 1.0/8.0 1.0/6.0 1.0/4.0 50/33.3 50/33.3 50/33.3
20 �A/-1.2 mA 20 �A/-8.4 mA 20 �A/-9.6 mA 20 �A/-4.8 mA 20 �Al -4.8 mA 20 �A/-3.6 mA 20 �Al - 2.4 mA -1 mA/20mA -1 mA/20 mA -1 mA/20 mA
4-151
,cC..o'\.I. Functional Descri,ption
The 'F182 carry lookahead generator accepts up to four pairs of Active LOW Carry Propagate (Po-P3) and Carry Generate (Go-G3) signals and an Active HIGH Carry input (Cn) and provides anticipated Active HIGH carries (Cn + X� Cn + Y� Cn + z} across four groups of binary adders. The 'F182 also has Active LOW Carry Propagate (P) and Carry Generate (G) outputs which may be used for further levels of lookahead. The logic equations provided at the outputs are:
Cn+x Cn+y Cn+z
= Go + PoCn = G1 + P1Go + P1P0Cn = G2 + P2G1 + P2P1Go + P2P1P0Cn
G
= G3 + P3G2 + P3P2G1 + P3P2P1Go
P
= P2P2P1Po
Also, the 'F182 can be used with binary ALUs in an active LOW or active HIGH input operand mode. The connections (Figure 1) to and from the ALU to the carry lookahead generator are identical in both cases. Carries are rippled between lookahead blocks. The critical speed path follows the circled numbers. There are several possible arrangements for the carry interconnects, but all achieve about the same speed. A 28-bit ALU is formed by dropping the last 'F181 or 'F381.
Truth Table
Inputs
Outputs
Cn Go Po G1 P1 G2 P2 Ga P3 Cn+x Cn+y Cn+z G p
x H H
L
L Hx
L
xL x
H
H xL
H
xxxH H
L
xH H H x
L
L HxH x
L
xxxL x
H
xL xxL
H
H xL xL
H
x xxxxH H
L
xxxH H H x xH H H xH x
L L
L H xHxHx
L
x x
x x
x x
x
L
x x
L
x
x
L
H H
xL xxL xL HxL xL xL
H H
x
xxxxH H
H
x
xxHHH x
H
x
H H H xH x
H
H
H xH xH x
H
x
xxxxL x
L
x
xxL xxL
L
x
L xxL xL
L
L
xL xL xL
L
H
x
x
x
x
H
x
x
H H
x
x
H
x
H
x
x
x
H
H
L
L
L
L
L
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
4-152
.....
(X)
Logic Diagram
N
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
TL/F/9492-4
A,B
CD
en
Cn+4
ALU� G
en ALU� G
en
enu ALU�
r�
FIGURE 1. 32-Blt ALU with Rippled Carry between 16-Bit Lookahead ALUs
�ALUs may be either 'F1B1 or 'F3B1
TL/F/9492-5
4-153
",c.o.'. Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Storage Temperature
-65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
-55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5Vto +7.0V
Input Voltage (Note 2) �
-0.5V to+ 7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5VtoVee -0.5Vto +5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
ESD Last Passing Voltage (Min)
4000V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +70�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
Input HIGH Voltage
Input LOW Voltage
Veo
Input Clamp Diode Voltage
54F/74F Min Typ Max
Units Vee
Conditions
2.0
v
Recognized as a HIGH Signal
0.8
v
Recognized as a LOW Signal
-1.2
v
Min l1N = -18 mA
VoH
Output HIGH
Voltage
54F 10% Vee 2.5
74F 10% Vee 2.5
74F5% Vee
2.7
loH = -1 mA
v
Min loH = -1 mA
loH = -1 mA
Output LOW Voltage
54F 10% Vee 74F 10% Vee
0.5
v
Min loL = 20 mA
0.5
loL = 20 mA
Input HIGH
54F
Current
74F
20.0
�A
Max V1N = 2.7V
5.0
lsv1
Input HIGH Current 54F
Breakdown Test
74F
100
�A
Max V1N = 7.0V
7.0
le Ex
Output HIGH
54F
Leakage Current
74F
250
�A
Max VouT =Vee
50
Input Leakage
74F
4.75
Test
v
0.0 110 = 1.9 �A
All Other Pins Grounded
loo
Output Leakage 74F
Circuit Current
3.75
�A
0.0
V100 = 150 mV All Other Pins Grounded
Input LOW Current
los
Output Short-Circuit Current
-1.2
V1N = 0.5V (Cn)
-2.4
V1N = 0.5V (P3)
-3.6 -4.8
mA
Max
V1N = 0.5V (P2) V1N = 0.5V (G3, Po, P1)
-8.4
V1N = 0.5V (Go, G2)
-9.6
V1N = 0.5V (G1)
-60
-150 mA Max VouT = ov
leeH
Power Supply Current
18.4 28.0
mA Max Vo= HIGH
leeL
Power Supply Current
23.5 36.0
mA Max Vo= LOW
4-154
.....
C>
AC Electrical Characteristics: see Section 2 for Waveforms and Load Configurations
N
Symbol
Parameter
tPLH tPHL tPLH tPHL
tPLH tPHL
tPLH tPHL tPLH tPHL tPLH tPHL
Propagation Delay Cn to Cn+x� Cn+.l,'. Cn+z
Propagation Delay Po, P1, or P2 to Cn+x� Cn+~ or Cn+z Propagation Delay Go. G1, or G2 to Cn+x� Cn+_y. orCn+z
Propagation Delay P1. P2. or P3 to G
Propagation Delay GntoG
Propagation Delay PntoP
74F
TA= +25�C Vee= +5.0V
CL= 50 pF
Min
Typ
Max
3.0
6.6
8.5
3.0
6.8
9.0
2.5
6.2
8.0
1.5
3.7
5.0
2.5
6.5
8.5
1.5
3.9
5.2
3.0
7.9
10.0
3.0
6.0
8.0
3.0
8.3
10.5
3.0
5.7
7.5
3.0
5.7
7.5
2.5
4.1
5.5
54F
TA, Vee= Mil CL= 50 pF
Min
Max
3.0
12.0
3.0
11.0
2.5
11.0
1.0
7.0
74F
TA, Vee= Com CL= 50 pF
Min
Max
3.0
9.5
3.0
10.0
2.5
9.0
1.5
6.0
Fig. Units No.
ns 2-3 ns 2-3
2.5
11.0
2.5
1.0
7.0
1.5
9.5 6.0
ns 2-3
3.0
12.0
3.0
11.0
ns 2-3
2.5
10.0
3.0
9.0
3.0 2.5
12.0 10.0
3.0 3.0
11.5 8.5
ns 2-3
2.5
10.0
3.0
8.5
ns 2-3
2.5
8.0
2.5
6.5
4-155
O,c.o.>.
~National
~Semiconductor
54F/74F189 64-Bit Random Access Memory with TRI-STATE� Outputs
General Description
The 'F189 is a high-speed 64-bit RAM organized as a 16word by 4-bit array. Address inputs are buffered to minimize loading and are fully decoded on-chip. The outputs are TRISTATE and are in the high impedance state whenever the Chip Select (CS) input is HIGH. The outputs are active only in the Read mode and the output data is the complement of the stored data.
Features
� TRI-STATE outputs for data bus applications � Buffered inputs minimize loading � Address decoding on-chip � Diode clamped inputs minimize ringing � Available in SOIC, (300 mil only)
Ordering Code: see section 5 Logic Symbols
Connection Diagrams
Ao Do D1 D2 D3
A1 A2 A3
cs
WE
IEEE/I EC
TL/F/9493-1
RAM16X4
Ao
A1
A2
A3
cs
WE
Pin Assignment for DIP, SOIC and Flatpak
Ao 1
cs 2
WE 3
Do 4 Oo 5
o, 6
o, 7
GND 8
16 Yee 15 A1 14 A2 13 A3 12 D3 11 03 10 Dz 9 Oz
TL/F/9493-2
Pin Assignment for LCC
[D[1] mo0 [N[C) [D[o] mWE
G~~~o~~
NC [.i]
[I) NC
02 (j1] D2 II]
gQJ Yee [fil A1
li3J Ii]] [j]f llll lrn
03 D3 NC A3 A-i_
TL/F/9493-3
Do
Oo
D,
o,
Dz
02
D3
03
TL/F/9493-4
Unit Loading/Fan Out: See Section 2 for U.L. Definitions
Pin Names
Ao-A3 cs WE Do-D3 Oo-03
Description
Address Inputs Chip Select Input (Active LOW) Write Enable Input (Active LOW) Data Inputs Inverted Data Outputs
U.L. HIGH/LOW
1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 150/40 (33.3)
54F/74F
Input l1Hll1L Output loH/loL
20 �Al -0.6 mA 20 �A/-1.2 mA 20 �A/-0.6 mA 20 �Al -0.6 mA -3.0 mA/24 mA (20 mA)
4-156
Function Table
Inputs Operation
cs WE
Condition of Outputs
L L
L H
H x
Write Read Inhibit
High Impedance Complement of Stored Data High Impedance
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
Block Diagram
DECODER DRIVERS
ADDRESS DECODER
.....
ccoo
WE
l " - -_ _ I O -. . .-+~~~~-cs
TL/F/9493-5
4-157
Absolute Maximum Ratings (Note 1)
If MilitaryI Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to + 7.0V
Input Voltage (Note 2)
-0.5V to + 7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
-0.5Vto Vee -0.5Vto +5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol V1H V1L Veo VoH
VoL l1H lsv1 leEx V10 loo l1L lozH lozL los lzz leez
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee 74F5% Vee 74F5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage 74F
Test
Output Leakage
74F
Circuit Current
Input LOW Current
Output Leakage Current Output Leakage Current Output Short-Circuit Current Bus Drainage Test Power Supply Current
54F/74F Min Typ Max
2.0
0.8 -1.2
2.5 2.4 2.5 2.4 2.7 2.7
0.5 0.5
20.0 5.0
100 7.0
250 50
4.75
3.75
-0.6 -1.2
50
-50
-60
-150
500
37
55
Units v v v
v
v �A �A �A v �A mA �A �A mA �A mA
Vee
Conditions
Recognized as a HIGH Signal
Recognized as a LOW Signal
Min l1N = -18 mA
loH = -1 mA loH = -3mA Min loH = -1 mA loH = -3mA loH = -1 mA loH = -3mA
loL = 20 mA Min
loL = 24 mA
Max V1N = 2.7V
Max V1N = 7.0V
Max Vour =Vee
0.0
0.0
Max Max Max Max o.ov Max
110 = 1.9 �A All Other Pins Grounded V100 = 150 mV All Other Pins Grounded V1N = 0.5V (except CS) V1N = 0.5V (CS)
Vour = 2.7V Vour = o.5V Vour = ov Vour = 5.25V Vo= HIGHZ
4-158
.....
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
cOo>
74F
54F
74F
Symbol
Parameter
tPLH tPHL
tpzH tpzL
tpHz tpLZ
tpzH tpzL
tpHz tpLZ
Access Time, HIGH or LOW An to On
Access Time, HIGH or LOW CS to On
Disable Time, HIGH or LOW CS to On
Write Recovery Time, HIGH or LOW WE to On
Disable Time, HIGH or LOW WE to On
TA= +25�C Vee= +5.0V
CL= 50 pf
Min
Typ
Max
10.0
18.5
26.0
8.0
13.5 19.0
3.5
6.0
8.5
5.0
9.0
13.0
2.0
4.0
6.0
3.0
5.5
8.0
6.5
15.0 28.0
6.5
11.0 15.5
4.0
7.0
10.0
5.0
9.0
13.0
*TA, Vee= Mil CL= 50pF
Min
Max
9.0
32.0
8.0
23.0
3.5
10.5
5.0
15.0
2.0
8.0
2.5
10.0
6.5
37.5
6.5
17.5
3.5
12.0
5.0
15.0
TA, Vee= Com CL= 50 pf
Fig. Units
No.
Min
Max
10.0
27.0
ns 2-3
8.0
20.0
3.5 5.0
9.5 14.0
ns 2-5
2.0
7.0
ns 2-5
3.0
9.0
6.5 6.5
29.0 16.5
ns 2-5
4.0 5.0
11.0 14.0
ns 2-5
AC Operating Requirements: see section 2 tor Waveforms
Symbol
Parameter
t5 (H) t5 (L)
th(H) th(L)
Setup Time, HIGH or LOW An to WE
Hold Time, HIGH or LOW An to WE
t5 (H) t5 (L)
th(H) th(L)
Setup Time, HIGH or LOW DntoWE
Hold Time, HIGH or LOW DntoWE
t 5 (L)
Setup Time, LOW
CS to WE
th(L)
Hold Time, LOW
CS to WE
tw(L)
WE Pulse Width, LOW
�rA = -40�c to+ 12s�c
74F
TA= +25�C Vee= +5.0V
Min
Max
0 0
2.0 2.0
10.0 10.0
0 0
0
6.0 6.0
54F
*TA, Vee= Mil
Min
Max
0 0
2.0 2.0
11.0 11.0
2.0 2.0
0
7.5 5.5
74F
TA, Vee= Com
Min
Max
0 0
2.0 2.0
10.0 10.0
0 0
0
6.0 6.0
Units Fig. No.
ns
2-6
ns
2-6
ns
2-6
ns
2-4
4-159
0
O...>.. ~National
D Semiconductor
54F/74F190
Up/Down Decade Counter with Preset and Ripple Clock
General Description
The 'F190 is a reversible BCD (8421) decade counter featuring synchronous counting and asynchronous presetting. The preset feature allows the 'F190 to be used in programmable dividers. The Count Enable input, the Terminal Count output and the Ripple Clock output make possible a variety of methods of implementing multistage �counters. In the counting modes, state changes are initiated by the rising edge of the clock.
Features
� High-speed-125 MHz typical count frequency � Synchronous counting � Asynchronous parallel load � Cascadable
Ordering Code: see section 5 Logic Symbols
PL Po P1 P2 P3
ii/D
RC
CE
TC
TL/F/9494-1
IEEE/I EC
cr
U/D
TC
CP
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
P1 1 01 2 Oo 3
cr 4
0/D 5
02 6 03 7 GND 8
16 Yee
15 Po 14 CP
13 RC
12 TC
11 PC
10 P2 9 P3
TL/F/9494-2
Pin Assignment forLCC
~ii/DNC Ci 0o III III IIl [[J III
G.~~:o~~;
NC[i)
[j]NC
P31i1l
~Vee
P21i]
Ii]] Po
~[�Iii]] li]ij]]
Pl TC NC RC CP
TL/F /9494-3
Oo
o,
02 03
TL/F/9494-4
Unit Loading/Fan Out: See Section 2 for U.L. Definitions
Pin Names
CE CP Po-P3 PL
DID
Oo-03 RC TC
Description
Count Enable Input (Active LOW) Clock Pulse Input (Active Rising Edge) Parallel Data Inputs Asynchronous Parallel Load Input (Active LOW) Up/Down Count Control Input Flip-Flop Outputs Ripple Clock Output (Active LOW) Terminal Count Output (Active HIGH)
54F/74F
U.L.
Input l1Hll1L
HIGH/LOW Output loHlloL
1.0/3.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 50/33.3 50/33.3 50/33.3
20 �.Al -1.8 mA 20 �.Al - 0.6 mA 20 �.Al - 0.6 mA 20 �.Al - 0.6 mA 20 �.Al - 0.6 mA -1 mA/20 mA -1 mA/20 mA -1 mA/20 mA
4-160
Functional Description
The 'F190 is a synchronous up/down BCD decade counter containing four edge-triggered flip-flops, with internal gating and steering logic to provide individual preset, count-up and count-down operations. It has an asynchronous parallel load capability permitting the counter to be preset to any desired number. When the Parallel Load (PL) input is LOW, information present on the Parallel Data inputs (Po-P3) is loaded into the counter and appears on the Q outputs. This operation overrides the counting functions, as indicated in the Mode Select Table. A HIGH signal on the CE input inhibits counting. When CE is LOW, internal state changes are initiated synchronously by the LOW-to-HIGH transition of the clock input. The direction of counting is determined by the U/D input signal, as indicated in the Mode Select Table, CE and U/D can be changed with the clock in either state, provided only that the recommended setup and hold times are observed.
RC Truth Table
Inputs
CE
TC*
CP
L
H
Lr
H
x
x
x
L
x
'TC is generated internally
H = HIGH Voltage Level
L = LOW Voltage Level X = Immaterial . . / = LOW-to-HIGH Clock Transition Lr = LOW Pulse
Output
RC
Lr H H
State Diagram
......
U> 0
Two types of outputs are provided as overflow/underflow indicators. The Terminal Count (TC) output is normally LOW and goes HIGH when a circuit reaches zero in the countdown mode or reaches 9 in the count-up mode. The TC output will then remain HIGH until a state change occurs, whether by counting or presetting or until U/D is changed. The TC output should not be used as a clock signal because it is subject to decoding spikes. The TC signal is also used internally to enable the Ripple Clock (RC) output. The RC output is normally HIGH. When CE is LOW and TC is HIGH, the RC output will go LOW when the clock next goes LOW and will stay LOW until the clock goes HIGH again. This feature simplifies the design of multistage counters. For a discussion and illustrations of the various methods of implementing multistage counters, please see the 'F191 data sheet.
Mode Select Table
Inputs
PL
CE
U/D
CP
Mode
H
L
H
L
L x
H
H
L
_/
Count Up
H
_/
Count Down
x
x
Preset (Asyn.)
x
x
No Change (Hold)
COUNT UP-COUNT DOWN- - �
TL/F/9494-5
4-161
0
.O..>.. Logic Diagram
TL/F/9494-6 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-162
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
-65�C to+ 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
-55�C to+ 175�C
Vee Pin Potential to Ground Pin
-0.5V to + 7.0V
Input Voltage (Note 2)
-0.5V to + 7.0V
Input Current (Note 2)
-30 mA to + 5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5VtoVee - 0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
......
CD
Recommended Operating
0
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
V1H
Input HIGH Voltage
V1L
Input LOW Voltage
Veo
Input Clamp Diode Voltage
54F/74F Min Typ Max
Units Vee
Conditions
2.0
v
Recognized as a HIGH Signal
0.8
v
Recognized as a LOW Signal
-1.2
v
Min l1N = -18 mA
VoH
Output HIGH
Voltage
54F 10% Vee 2.5
74F 10% Vee 2.5
74F5% Vee
2.7
loH = -1 mA
v
Min loH = -1 mA
loH = -1 mA
VoL
Output LOW
Voltage
54F 10% Vee 74F 10% Vee
0.5
v
Min loL = 20 rnA
0.5
loL = 20 rnA
l1H
Input HIGH
54F
Current
74F
20.0
�A
Max V1N = 2.7V
5.0
lsv1
Input HIGH Current 54F
Breakdown Test
74F
100
�A
Max V1N = 7.0V
7.0
lcEx
Output HIGH
54F
Leakage Current
74F
250
�A
Max VouT =Vee
50
V10
Input Leakage
74F
4.75
Test
v
0.0 110 = 1.9 �A
All Other Pins Grounded
loo
Output Leakage
74F
Circuit Current
3.75
�A
0.0 V100 = 150 mV All Other Pins Grounded
l1L
Input LOW Current
los
Output Short-Circuit Current
-0.6
mA
Max V1N = 0.5V, except CE
-1.8
V1N = 0.5V, CE
-60
ov -150 mA Max VouT =
lccL
Power Supply Current
38
55
mA Max Vo= LOW
4-163
0
.O..>.. AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
fmax
tPLH tPHL
tPLH tPHL
tPLH tPHL
tPLH tPHL
tPLH tPHL
tPLH tPHL
tPLH tPHL
tPLH tPHL
Maximum Clock Frequency
Propagation Delay CPtoOn
Propagation Delay CPtoTC
Propagation Delay CPto RC
Propagation Delay CE to RC
Propagation Delay U/Dto RC
Propagation Delay LJ/DtoTC
Propagation Delay Pn to On Propagation Delay PL to On
74F
TA= +25�C Vee= +5.0V
CL= 50pF
Min
Typ
Max
100
125
3.0
5.5
7.5
5.0
8.5
11.0
6.0
10.0
13.0
5.0
8.5
11.0
3.0
5.5
7.5
3.0
5.0
7.0
3.0
5.0
7.0
3.0
5.5
7.0
7.0
11.0
18.0
5.5
9.0
12.0
4.0
7.0
10.0
4.0
6.5
10.0
3.0
4.5
7.0
6.0
10.0
13.0
5.0
8.5
11.0
5.5
9.0
12.0
54F
TA, Vee= Mii CL= 50pF
Min
Max
75
3.0
9.5
5.0
13.5
6.0
16.5
5.0
13.5
3.0
9.5
3.0
9.0
3.0
9.0
3.0
9.0
7.0
22.0
5.5
14.0
4.0
13.5
4.0
12.5
3.0
9.0
6.0
16.0
5.0
13.0
5.5
14.5
74F
TA, Vee= Com CL= 50pF
Units
Fig. No.
Min
Max
90
MHz 2-1
3.0
8.5
5.0
12.0
ns 2-3
6.0
14.0
5.0
12.0
3.0
8.5
3.0
8.0
ns 2-3
3.0
8.0
3.0
8.0
7.0
20.0
5.5
13.0
ns 2-3
4.0
11.0
4.0
11.0
3.0
8.0
ns 2-3
6.0
14.0
5.0
12.0
ns 2-3
5.5
13.0
AC Operating Requirements: See Section 2 for Waveforms
74F
54F
Symbol
Parameter
t5(H) t5(L) th(H) th(L) t 5(L)
th(L)
Setup Time, HIGH or LOW Pn to PL
Hold Time, HIGH or LOW Pn to PL
Setup Time, LOW CE to GP
Hold Time, LOW CE to GP
TA= +25�C Vee= +5.0V
Min
Max
4.5 4.5
2.0 2.0
10.0
0
TA, Vee= Mil
Min
Max
6.0 6.0
2.0 2.0
10.5
0
t 5 (H) t 5 (L)
th(H) th(L)
Setup Time, HIGH or LOW U/DtoCP
Hold Time, HIGH or LOW LJ/DtoCP
12.0 12.0
0 0
12.0 12.0
0 0
tw(L)
PL Pulse Width, LOW
6.0
8.5
tw(L)
CP Pulse Width, LOW
5.0
7.0
tree
Recovery Time PL to CP
6.0
7.5
74F
TA, Vee= Com
Min
Max
5.0 5.0
2.0 2.0
10.0
0
12.0 12.0
0 0 6.0 5.0 6.0
Units
Fig. No.
ns
2-6
ns
2-6
ns
2-6
ns
2-4
ns
2-4
ns
2-6
4-164
.....
~National
.C..D..
U Semiconductor
54F/74F191
Up/Down Binary Counter with Preset and Ripple Clock
General Description
The 'F191 is a reversible modulo-16 binary counter featuring synchronous counting and asynchronous presetting. The preset feature allows the 'F191 to be used in programmable dividers. The Count Enable input, the Terminal Count output and Ripple Clock output make possible a variety of methods of implementing multistage counters. In the counting modes, state changes are initiated by the rising edge of the clock.
Features
� High-Speed-125 MHz typical count frequency � Synchronous counting � Asynchronous parallel load � Cascadable
Ordering Code: see section 5
Logic Symbols
Connection Diagrams
PL Po P1 P2 P3
U/D
RC
CE
TC
CP Oo 01 02 03
IEEE/IEC
TL/F /9495-1
Pin Assignment for DIP, SOIC and Flatpak
P1 1
o,
Oo
cr 4
0/D 5
02 03 GND 8
16 Vee 15 Po 14 CP
13 RC
12 TC
11 Pi:
10 P2 9 P3
TL/F/9495-2
Pin Assignment forLCC
020/DNC CE Oo
[]][ZJ[�][1JIIJ
G0 ND Ii3 ]] 0 0 D I I l 0 III P,1
NC[i]
[!]NC
P3 ll11
ggVcc
P2 [j]
Ii]] Po
IBJ[i]]li]JIIZJ[ID
PL TC NC RC CP
TL/F/9495-3
Oo
o,
02 03
TL/F /9495-4
Unit Loading/Fan Out: See Section 2 tor u.L. definitions
Pin Names
Description
54F/74F
U.L.
Input l1Hll1L
HIGH/LOW Output loHlloL
CE CP Po-P3 PL TIID Oo-03 RC TC
Count Enable Input (Active LOW) Clock Pulse Input (Active Rising Edge) Parallel Data Inputs Asynchronous Parallel Load Input (Active LOW) Up/Down Count Control Input Flip-Flop Outputs Ripple Clock Output (Active LOW) Terminal Count Output (Active HIGH)
1.0/3.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 50/33.3 50/33.3 50/33.3
20 �Al -1.8 mA 20 �Al -0.6 mA 20 �Al -0.6 mA 20 �A/ -0.6 mA 20 �Al -0.6 mA -1 mA/20 mA -1 mA/20 mA -1 mA/20 mA
4-165
,...
.-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
,O..>. Functional Description
The 'F191 is a synchronous up/down 4-bit binary counter. It contains four edge-triggered flip-flops, with internal gating and steering logic to provide individual preset, count-up and count-down operations.
Each circuit has an asynchronous parallel load capability permitting the counter to be preset to any desired number. When the Parallel Load (PL) input is LOW, information present on the Parallel Data inputs (Po-P3) is loaded into the counter and appears on the Q outputs. This operation overrides the counting functions, as indicated in the Mode Select Table.
A HIGH signal on the CE input inhibits counting. When CE is LOW, internal state changes are initiated synchronously by the LOW-to-HIGH transition of the clock input. The direction of counting is determined by the DID input signal, as indicated in the Mode Select Table. CE and LJ/D can be changed with the clock in either state, provided only that the recommended setup and hold times are observed.
A method of causing state changes to occur simultaneously in all stages is shown in Figure 2. All clock inputs are driven in parallel and the RC outputs propagate the carry/borrow signals in ripple fashion. In this configuration the LOW state duration of the clock must be long enough to allow the negative-going edge of the carry/borrow signal to ripple through to the last stage before the clock goes HIGH. There is no such restriction on the HIGH state duration of the clock, since the RC output of any device goes HIGH shortly after its CP input goes HIGH.
The configuration shown in Figure 3 avoids ripple delays and their associated restrictions. The CE input for a given stage is formed by combining the TC signals from all the preceding stages. Note that in order to inhibit counting an enable signal must be included in each carry gate. The simple inhibit scheme of Figures 1 and 2 doesn't apply, because the TC output of a given stage is not affected by its own CE.
Two types of outputs are provided as overflow/underflow indicators. The Terminal Count (TC) output is normally LOW and goes HIGH when a circuit reaches zero in the countdown mode or reaches 15 in the count-up mode. The TC output will then remain HIGH until a state change occurs, whether by counting or presetting or until TI/D is changed. The TC output should not be used as a clock signal because it is subject to decoding spikes.
The TC signal is also used internally to enable the Ripple Clock (RC) output. The RC output is normally HIGH. When CE is LOW and TC is HIGH, the RC output will go LOW when the clock next goes LOW and will stay LOW until the clock goes HIGH again. This feature simplifies the design of multistage counters, as indicated in Figures 1 and 2. In Figure 1, each RC output is used as the clock input for the next higher stage. This configuration is particularly advantageous when the clock source has a limited drive capability, since it drives only the first stage. To prevent counting in all stages it is only necessary to inhibit the first stage, since a HIGH signal on CE inhibits the RC output pulse, as indicated in the RC Truth Table. A disadvantage of this configuration, in some applications, is the timing skew between state changes in the first and last stages. This represents the cumulative delay of the clock as it ripples through the preceding stages.
Mode Select Table
Inputs
PL
CE
TI/D
CP
Mode
H
L
L
_r
Count Up
H
L
H
_r
Count Down
L x
x
x
Preset (Asyn.)
H
H
x
x
No Change (Hold)
RC Truth Table
Inputs
CE
TC*
CP
L
H
""1S
H
x
x
x
L
x
*TC is generated internally H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial .../ = LOW-to-HIGH Clock Transition Lf" =LOW Pulse
Output
RC
""1S H H
4-166
.....
Logic Diagram
.c..o..
TL/F/9495-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
FIGURE 1. n-Stage Counter Using Ripple Clock
TL/F/9495-6
li/D RC
U/D RC
CE
CE
CE
CP
CP
CP
CLOCK_.__ _ _ _ _ _+ - - - - - - - - + - - - - -
TL/F/9495- 7
FIGURE 2. Synchronous n-Stage Counter Using Ripple Carry/Borrow
DIRECTION CONTROL-------------------------tt------ENABLE - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
FIGURE 3. Synchronous n-Stage Counter with Gated Carry/Borrow 4-167
TL/F/9495-8
..... 0....). Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
-65�C to+ 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to+ 7.0V
Input Voltage (Note 2)
-0.5Vto +7.0V
Input Current (Note 2)
-30 mA to + 5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5V to Vee -0.5Vto +5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C o�cto +70�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
54F/74F Min Typ Max
Units Vee
Conditions
V1H
Input HIGH Voltage
2.0
v
Recognized as a HIGH Signal
V1L
Input LOW Voltage
0.8
v
Recognized as a LOW Signal
Vco
Input Clamp Diode Voltage
-1.2
v
Min l1N = -18 mA
VoH
Output HIGH
Voltage
54F 10% Vee 2.5
74F 10% Vee 2.5
74F 5% Vee
2.7
loH = -1 mA
v
Min loH = -1 mA
loH = -1 mA
Vol
Output LOW
Voltage
54F 10% Vee 74F 10% Vee
0.5
v
Min loL = 20mA
0.5
loL = 20 mA
l1H
Input HIGH
54F
Current
74F
20.0 5.0
�A
Max V1N = 2.7V
lsv1
Input HIGH Current 54F
Breakdown Test
74F
100
�A
Max V1N = 7.0V
7.0
lcEX
Output HIGH
54F
Leakage Current
74F
250 50
�A
Max Vour =Vee
V10
Input Leakage
74F
4.75
Test
v
0.0 110 = 1.9 �A,
All Other Pins Grounded
loo
Output Leakage
Circuit Current
74F
3.75
�A
0.0 V100 = 150 mV All Other Pins Grounded
l1L
Input LOW Current
-0.6 -1.8
mA
Max V1N = 0.5V (except CE) V1N = 0.5V (CE)
los
Output Short-Circuit Current
-60
-150 mA Max Vour = ov
Ice
Power Supply Current
38
55
mA Max
4-168
......
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
<...O...
Symbol
Parameter
fmax
tPLH tPHL
tPLH tPHL
tPLH tPHL
tPLH tPHL
iPLH tPHL
tPLH tPHL tpLH tPHL
tPLH tPHL
Maximum Count Frequency
Propagation Delay CPtoOn
Propagation Delay CPtoTC
Propagation Delay CPto RC
Propagation Delay CE to RC
Propagation Delay U/D to RC
Propagation Delay U/DtoTC
Propagation Delay Pn to On Propagation Delay PL to On
74F
TA= +25�C Vee= +5.0V
CL= 50pF
Min
Typ
Max
100
125
3.0
5.5
7.5
5.0
8.5
11.0
6.0
10.0
13.0
5.0
8.5
11.0
3.0
5.5
7.5
3.0
5.0
7.0
3.0
5.0
7.0
3.0
5.5
7.0
7.0
11.0
18.0
5.5
9.0
12.0
4.0
7.0
10.0
4.0
6.5
10.0
3.0
4.5
7.0
6.0
10.0 13.0
5.0
8.5
11.0
5.5
9.0
12.0
54F
TA, Vee= Mii CL= 50pF
Min
Max
75
3.0
9.5
5.0
13.5
6.0
16.5
5.0
13.5
3.0
9.5
3.0
9.0
3.0
9.0
3.0
9.0
7.0
22.0
5.5
14.0
4.0
13.5
4.0
12.5
3.0
9.0
6.0
16.0
5.0
13.0
5.5
14.5
74F
TA, Vee= Com Units Fig.
CL= 50pF
No.
Min
Max
90
MHz 2-1
3.0
8.5
5.0
12.0
ns 2-3
6.0
14.0
5.0
12.0
3.0
8.5
3.0
8.0
ns 2-3
3.0
8.0
3.0
8.0
7.0
20.0
5.5
13.0
ns 2-3
4.0
11.0
4.0
11.0
3.0
.8.0
ns 2-3
6.0
14.0
5.0
12.0
ns 2-3
5.5
13.0
AC Operating Requirements: See Section 2 for Waveforms
Symbol
Parameter
t5 (H) t5 (L) th(H) th(L) t 5 (L)
th(L)
t 5 (H) t 5 (L) th(H) th(L) tw(L) tw(L) tree
Setup Time, HIGH or LOW Pn to PL
Hold Time, HIGH or LOW Pn to PL
Setup Time LOW CE to GP
Hold Time LOW CE to CP
Setup Time, HIGH or LOW U/D to CP
Hold Time, HIGH or LOW U/D to CP
PL Pulse Width LOW
CP Pulse Width LOW
Recovery Time PL toCP
74F
TA= +25�C Vee= +5.0V
Min
Max
4.5 4.5
2.0 2.0
10.0
0
12.0 12.0
0 0 6.0 5.0
6.0
54F
TA, Vee= Mii
Min
Max
6.0 6.0
2.0 2.0
10.5
0
12.0 12.0
0 0 8.5 7.0
7.5
74F
TA, Vee= Com
Min
Max
5.0 5.0
2.0 2.0
10.0
0
12.0 12.0
0 0 6.0 5.0
6.0
Fig. Units
No.
ns
2-6
ns
2-6
ns 2-6
ns
2-4
ns
2-4
ns
2-6
4-169
~~SNemaitcoinoduncatolr
54F/74F192
Up/Down Decade Counter with Separate Up/Down Clocks
General Description
The 'F192 is an up/down BCD decade (8421) counter. Separate Count Up and Count Down Clocks are used, and in either counting mode the circuits operate synchronously. The outputs change state synchronously with the LOW-toHIGH transitions on the clock inputs.
Separate Terminal Count Up and Terminal Count Down outputs are used as the clocks for a subsequent stage without extra logic, thus simplifying multistage counter designs. Individual preset inputs allow the circuit to be used as a programmable counter. Both the Parallel Load (PL) and the Master Reset (MR) inputs asynchronously override the clocks.
Ordering Code: see section 5 Logic Symbols
TL/F/9496-3
IEEE/I EC
eTRDIV10 MR ePu
'iCu ep0
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
P1
01 Oo 3 CP0 4 CPu
Oz 03 7 GND 8
16 Vee
15 Po 14 MR 13 Teo
12 'fCu 11 Pi:
10 Pz 9 P3
TL/F/9496-1
Pin Assignment for LCC
o,ooorno, Oz CPu NC CPo Oo [!)IIJ[�]!IJ[1)
GND [QI
CIJP1
NC [i]
[J]NC
P31!ll
~Vee
Pz [j]
!IIDP0
Ii] lmlffi [i]li]]
PL lCu NC Teo MR
TL/F/9496-2
Oo
o,
Oz 03
TL/F/9496-6
Unit Loading/Fan Out: See Section 2 for u.L. Definitions
54F/74F
Pin Names
Description
U.L.
Input l1H/l1L
HIGH/LOW Output loHllOL
CPu CPo MR PL Po-P3 Oo-03 TCo TCu
Count Up Clock Input (Active Rising Edge) Count Down Clock Input (Active Rising Edge) Asynchronous Master Reset Input (Active HIGH) Asynchronous Parallel Load Input (Active LOW) Parallel Data Inputs Flip-Flop Outputs Terminal Count Down (Borrow) Output (Active LOW) Terminal Count Up (Carry) Output (Active LOW)
1.0/3.0 1.0/3.0 1.0/1.0 1.0/1.0 1.0/1.0 50/33.3 50/33.3 50/33.3
20 �A/-1.8 mA 20 �A/-1.8 mA 20 �A/ -0.6 mA 20 �A/ - 0.6 niA 20 �A/ -0.6 mA -1 mA/20 mA -1 mA/20 mA -1 mA/20mA
4-170
Functional Description
The 'F192 is an asynchronously presettable decade counter. It contains four edge-triggered flip-flops, with internal gating and steering logic to provide master reset, individual preset, count up and count down operations.
A LOW-to-HIGH transition on the CP input to each flip-flop causes the output to change state. Synchronous switching, as opposed to ripple counting, is achieved by driving the steering gates of all stages from a common Count Up line and a common Count Down line, thereby causing all state changes to be initiated simultaneously. A LOW-to-HIGH transition on the Count Up input will advance the count by one; a similar transition on the Count Down input will decrease the count by one. While counting with one clock input, the other should be held HIGH, as indicated in the Function Table. Otherwise, the circuit will either count by twos or not at all, depending on the state of the first flip-flop, which cannot toggle as long as either clock input is LOW.
The Terminal Count Up (TCu) and Terminal Count Down (TCo) outputs are normally HIGH. When the circuit has reached the maximum count state 9, the next HIGH-to-LOW transition of the Count Up Clock will cause TCu to go LOW. TCu will stay LOW until CPu goes HIGH again, thus effectively repeating the Count Up Clock, but delayed by two gate delays. Similarly, the TCo output will go LOW when the circuit is in the zero state and the Count Down Clock goes LOW. Since the TC outputs repeat the clock waveforms, they can be used as the clock input signals to the next higher order circuit in a multistage counter.
TCu = Oo � 03 � CPu
TCo = Do � 01 � 02 � 03 � CPo
The 'F192 has an asynchronous parallel load capability permitting the counter to be preset. When the Parallel Load (PL) and the Master Reset (MR) inputs are LOW, information present on the Parallel Data input (Po-P3) is loaded into the counter and appears on the outputs regardless of the conditions of the clock inputs. A HIGH signal on the Master Reset input will disable the preset gates, override both clock inputs, and latch each Q output in the LOW state. If one of the clock inputs is LOW during and after a reset or
.....
co
I\)
load operation, the next LOW-to-HIGH transition of that clock will be interpreted as a legitimate signal and will be counted.
Function Table
MR
PL
CPu
CPo
H x x
x
L
L
x
x
L
H
H
H
L
H
_/
H
L
H
H
_/
H = HIGH Voltage Level L = LOW Voltage Level
X = Immaterial
.../" = LOW-to-HIGH Clock Transition
Mode
Reset (Asyn.) Preset (Asyn.) No Change Count Up Count Down
State Diagram
-
COUNT UP
- - - - �COUNT DOWN
TL/F/9496-4
a
4-171
C\I
O...>.. Logic Diagrarr-
reu Teo
(CARRY) (BORROW)
~ T~~
.I
~ J_
ry ~ ~� ". r-CP
.-i
I
t-KCpSD
Qj
_J
Q-J
--.
l:
Qj
L
~ J._ t-J D QIt- CP 1-K Cp Q
~
>
J._
I- J D Q
CP
1-KCpQ
Qj
L
0
)
f
J_
J Co QI-'
~CP
K Co Q
Qj ~
~
c
CPu
CPo
MR
TL/F/9496-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-172
Absolute Maximum Ratings (Note 1)
If Miiitary/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for avallablllty and specifications.
Storage Temperature
- 65�C to + 15o�c
Ambient Temperature under Bias
- 55�C to + 125�c
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to+ 7.0V
Input Voltage (Note 2)
-0.5Vto +7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee= OV) Standard Output TRI-STATE� Output
-0.5VtoVee - 0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�c o�c to +10�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
54F/74F Min Typ Max
Units Vee
Conditions
V1H
Input HIGH Voltage
2.0
v
Recognized as a HIGH Signal
V1L
Input LOW Voltage
0.8
v
Recognized as a LOW Signal
Veo
Input Clamp Diode Voltage
-1.2
v
Min l1N = -18mA
VoH
Output HIGH
Voltage
54F 10% Vee 2.5
74F 10% Vee 2.5
74F5% Vee
2.7
loH = -1 mA
v
Min loH = -1 mA
loH = -1 mA
VoL
Output LOW
Voltage
54F 10% Vee 74F 10% Vee
0.5
v
Min loL = 20 mA
0.5
loL = 20 mA
l1H
Input HIGH
54F
Current
74F
20.0
�A
Max V1N = 2.7V
5.0
lsv1
Input HIGH Current 54F
Breakdown Test
74F
100 7.0
�A
Max V1N = 7.0V
leEx
Output HIGH
54F
Leakage Current
74F
250 50
�A
Max Vour =Vee
V10
Input Leakage
74F
4.75
Test
v
0.0 110 = 1.9 �A
All Other Pins Grounded
loo
Output Leakage
Circuit Current
74F
3.75
�A
0.0 V100 = 150 mV
All Other Pins Grounded
l1L
Input LOW Current
-0.6 -1.8
mA
Max V1N = 0.5V, Except CPu, CPo V1N = 0.5V, CPu, CPo
los
Output Short-Circuit Current
-60
-150 mA Max Vour = ov
leeL
Power Supply Current
38
55
mA Max Vo= LOW
4-173
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL
tPLH
tPHL
tPLH tPHL tPLH tPHL
Maximum Clock Frequency
Propagation Delay CPu or CPo to TCu or TCo
Propagation Delay CPu or CPo to On
Propagation Delay Pn to On
Propagation Delay PL to On
Propagation Delay MR to On
Propagation Delay MR toTCu
Propagation Delay MRtoTC0 Propagation Delay PL to TCu or TCo
Propagation Delay Pn to TCu or TCo
74F
TA= +25�C Vee= +5.0V
CL= 50pF
Min
Typ
Max
100
125
4.0
7.0
9.0
3.5
6.0
8.0
4.0
6.5
8.5
5.5
9.5
12.5
3.0
4.5
7.0
6.0
11.0
14.5
5.0
8.5
11.0
5.5
10.0
13.0
6.5
11.0
14.5
6.0
10.5
13.5
7.0
11.5
14.5
7.0
12.0
15.5
7.0
11.5
14.5
7.0
11.5
14.5
6.5
11.0
14.0
54F
TA, Vee= Mil CL= 50 pf
Min
Max
75
4.0
10.5
3.5
9.5
4.0
10.0
5.5
14.0
3.0
8.5
6.0
16.5
5.0
13.5
5.5
15.0
6.5
16.0
74F
TA, Vee= Com CL= 50pF
Min
Max
90
4.0
10.0
3.5
9.0
4.0
9.5
5.5
13.5
3.0
8.0
6.0
15.5
5.0
12.0
5.5
14.0
6.5
15.5
6.0
15.0
6.0
14.5
7.0
16.0
7.0
15.5
7.0
18.5
7.0
16.5
7.0
17.5
7.0
15.5
7.0
16.5
7.0
15.5
6.5
16.5
6.5
15.0
Units Fig. No.
MHz 2-1 ns 2-3 ns 2-3 ns 2-3 ns 2-3
ns 2-3
ns 2-3 ns 2-3
AC Operating Requirements: See Section 2 for Waveforms
Symbol
Parameter
t 5 (H) t 5 (L) th(H) th(L) tw(L) tw(L)
tw(L)
tw(H) tree
tree
Setup Time, HIGH or LOW Pn to PL
Hold Time, HIGH or LOW Pn to PL
PL Pulse Width, LOW
CPu orCPo Pulse Width, LOW
CPu orCPo Pulse Width, LOW (Change of Direction)
MR Pulse Width, HIGH
Recovery Time PL to CPu or CPo
Recovery Time MR to CPu or CPo
74F
TA= +25�C Vee= +5.0V
Min
Max
4.5 4.5
2.0 2.0
6.0
5.0
10.0 6.0 6.0 4.0
54F
TA, Vee= Mil
Min
Max
6.0 6.0
2.0 2.0
7.5
7.0
12.0 6.0 8.0 4.5
74F
TA, Vee= Com
Min
Max
5.0 5.0
2.0 2.0
6.0
5.0
Units
Fig. No.
ns
2-6
ns
2-4
ns
2-4
10.0 6.0 6.0 4.0
ns
2-4
ns
2-4
ns
2-6
ns
2-6
4-174
....
~National
cw o
D Semiconductor
54F/74F193 Up/Down Binary Counter with Separate Up/Down Clocks
General Description
The 'F193 is an up/down modulo-16 binary counter. Separate Count Up and Count Down Clocks are used, and in either counting mode the circuits operate synchronously. The outputs change state synchronously with the LOW-toHIGH transitions on the clock inputs. Separate Terminal Count Up and Terminal Count Down outputs are provided that are used as the clocks for subsequent stages without extra logic, thus simplifying multi-stage counter designs.
Individual preset inputs allow the circuit to be used as a programmable counter. Both the Parallel Load (PL) and the Master Reset (MR) inputs asynchronously override the clocks.
Features
� Guaranteed 4000V minimum ESD protection
Ordering Code: see section 5 Logic Symbols
PL Po P1 P2 P3
CPu
TCu
CPo
TCo
MR Oo 01 02 03
IEEE/I EC
CTRDIV16
TL/F /9497 -1
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
P1 1 01 2 Oo 3 CP0 4 CPu
02 03 7 GND 8
16 Yee 15 Po 14 MR 13 Teo 12 fCu 11 PI: 10 P2 9 P3
TL/F/9497-2
Pin Assignment for LCC
Oz CPu NC CPo Oo [[] IIll!JIIIGJ
G~~:o~~;
NC [j]
P3 li1J P2 lrn
[I]NC ~Vee l!IDPo
fi]~li]]ij]jj])
PL 'fCuNC'fCoMR
TL/F/9497-3
Unit Loading/Fan Out: See Section 2 for u.L. Definitions
Pin Names
Description
54F/74F
U.L.
Input l1Hll1L
HIGH/LOW Output loHlloL
CPu CPo MR PL Po-P3 Oo-03 TCo TCu
Count Up Clock Input (Active Rising Edge) Count Down Clock Input (Active Rising Edge) Asynchronous Master Reset Input (Active HIGH) Asynchronous Parallel Load Input (Active LOW) Parallel Data Inputs Flip-Flop Outputs Terminal Count Down (Borrow) Output (Active LOW) Terminal Count Up (Carry) Output (Active LOW)
1.0/3.0 1.0/3.0 1.0/1.0 1.0/1.0 1.0/1.0 50/33.3 50/33.3 50/33.3
20 �A/-1.8 mA 20 �A/-1.8 mA 20 �A/-0.6 mA 20 �A/-0.6 mA 20 �A/-0.6 mA -1 mA/20 mA -1 mA/20 mA -1 mA/20 mA
4-175
(")
O.,.>. Functional Description
The 'F193 is a 4-bit binary synchronous up/down (reversible) counter. It contains four edge-triggered flip-flops, with internal gating and steering logic to provide master reset, individual preset, count up and count down operations.
A LOW-to-HIGH transition on the CP input to each flip-flop causes the output to change state. Synchronous switching, as opposed to ripple counting, is achieved by driving the steering gates of all stages from a common Count Up line and a common Count Down line, thereby causing all state changes to be initiated simultaneously. A LOW-to-HIGH transition on the Count Up input will advance the count by one; a similar transition on the Count Down input will decrease the count by one. While counting with one clock input, the other should be held HIGH, as indicated in the Function Table.
The Terminal Count Up (TCu) and Terminal Count Down (TCo) outputs are normally HIGH. When the circuit has reached the maximum count state 15, the next HIGH-toLOW transition of the Count Up Clock will cause TCu to go LOW. TCu will stay LOW until CPu goes HIGH again, thus effectively repeating the Count Up Clock, but delayed by two gate delays. Similarly, the TCo output will go LOW when the circuit is in the zero state and the Count Down Clock goes LOW. Since the TC outputs repeat the clock waveforms, they can be used as the clock input signals to the next higher order circuit in a multistage counter.
TCu = Oo � 01 � 02 � 03 � CPu
TCo = Oo � 01 � 02 � 03 � CPo
The 'F193 has an asynchronous parallel load capability permitting the counter to be preset. When the Parallel Load (PL) and the Master Reset (MR) inputs are LOW, information present on the Parallel Data input (Po-P3) is loaded into the counter and appears on the outputs regardless of the conditions of the clock inputs. A HIGH signal on the Master Reset input will disable the preset gates, override
both clock inputs, and latch each 0 output in the LOW state.
If one of the clock inputs is LOW during and after a reset or load operation, the next LOW-to-HIGH transition of that clock will be interpreted as a legitimate signal and will be counted.
Function Table
MR
PL
CPu
CPo
H
x
x
x
L
L
x
x
L
H
H
H
L
H
..../
H
L
H
H
..../
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial _,r = LOW-to-HIGH Clock Transition
Mode
Reset (Asyn.) Preset (Asyn.) No Change Count Up Count Down
State Diagram
-
COUNT UP
� - - - �COUNT DOWN
TL/F/9497-5
4-176
......
Logic Diagram
cw o
TCu
{CARRY)
Teo
{BORROW)
l
t------+-t__~
l
~K~PSo1O1 t-' -1-l~-� ....,._-_--1-1-+-t-+t--++--------------_-_,-i..-------_-:_-_-:_------++--_-----
Co 0 D~-+--<ll
P3 ~H-t---+-:i:::t::t:t=++:+:-t-==....==r-~-~-+---+------1-----r-,
~
Oo
C)
CPu
CPo
MR
TL/F/9497-6
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-177
Absolute Maximum Ratings (Note 1)
If MilitaryI Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Yee Pin Potential to Ground Pin
-0.5Vto +7.0V
Input Voltage (Note 2)
-0.5Vto +7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5VtoVcc -0.5Vto +5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
ESD Last Passing Voltage (Min)
4000V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +70�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Yeo VoL lsv1 leEX loo los Ice
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 74F 10% Vee 74F5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage 74F
Test
Output Leakage
74F
Circuit Current
Input LOW Current
Output Short-Circuit Current Power Supply Current
54F/74F Min Typ Max 2.0
0.8 -1.2 2.5 2.5 2.7 0.5 0.5 20.0 5.0 100 7.0 250
50
4.75
3.75
-0.6 -1.8
-60
-150
38
55
Units
v
v v v
v
�A
�A �A
v
�A
mA mA mA
Vee
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal Min l1N = -18 mA loH = -1 mA Min loH = -1 mA loH = -1 mA Min loL = 20 mA loL = 20 mA Max V1N = 2.7V
Max V1N = 7.0V
Max Your= Vee
0.0 110 = 1.9 �A
All Other Pins Grounded 0.0 V100 = 150 mV
All Other Pins Grounded V1N = 0.5V (MR, PL, Pn) Max V1N = 0.5V (CPu, CPo) Max Your= OV Max
4-178
.....
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
cw o
Symbol
Parameter
fmax tPLH tpHL
tpLH tPHL tPLH tpHL tpLH tPHL tPHL
tPLH
tPHL
tpLH tPHL tPLH tPHL
Maximum Count Frequency
Propagation Delay CPu orCPo to TCuorTCo
Propagation Delay CPu or CPo to On
Propagation Delay Pn to On
Propagation Delay PL to On
Propagation Delay MR to On
Propagation Delay MR toTCu
Propagation Delay MRtoTCo
Propagation Delay PL to TCu or TCo
Propagation Delay Pn to TCu or TCo
74F
TA= +25�C Vee= +5.0V
CL= 50 pF
Min
Typ
Max
100
125
4.0
7.0
9.0
3.5
6.0
8.0
4.0
6.5
8.5
5.5
9.5
12.5
3.0
4.5
7.0
6.0
11.0
14.5
5.0
8.5
11.0
5.5
10.0
13.0
5.5
11.0
14.5
6.0
10.5
13.5
6.0
11.5
14.5
7.0
12.0
15.5
7.0
11.5
14.5
7.0
11.5
14.5
6.5
11.0
14.0
54F
TA, Vee= Mil CL= 50 pF
Min
Max
75
4.0
10.5
3.5
9.5
74F
TA, Vee= Com CL= 50 pF
Units
Fig. No.
Min
Max
90
MHz 2-1
4.0
10.0
3.5
9.0
ns 2-3
3.5 5.5
10.0 14.0
4.0 5.5
9.5 13.5
ns 2-3
3.0
8.5
3.0
8.0
ns 2-3
6.0
16.5
6.0
15.5
5.0
13.5
5.0
12.0
ns 2-3
5.5
15.0
5.5
14.0
5.0
16.0
5.5
15.5
5.0
15.0
6.0
14.5
ns 2-3
6.0
16.0
6.0
15.5
7.0 6.0
18.5 17.5
7.0 7.0
16.5 15.5
ns 2-3
6.0 5.0
16.5 16.5
7.0 6.5
15.5 15.0
ns 2-3
AC Operating Requirements: See Section 2 for Waveforms
Symbol
Parameter
t5 (H) t5 (L) th(H) th(L) tw(L) tw(L)
tw(L)
tw(H) tree
tree
Setup Time, HIGH or LOW Pn to PL Hold Time, HIGH or LOW Pn to PL
PL Pulse Width, LOW
CPu orCPo Pulse Width, LOW
CPu orCPo Pulse Width, LOW (Change of Direction)
MR Pulse Width, HIGH
Recovery Time PL to CPu or CPo
Recovery Time MR to CPu or CPo
74F
TA= +25�C Vee= +5.0V
Min
Max
4.5 4.5
2.0 2.0
6.0
5.0
10.0 6.0 6.0 4.0
54F
TA, Vee= Mil
Min
Max
6.0 6.0
2.0 2.0
7.5
7.0
12.0 6.0 8.0 4.5
74F
TA, Vee= Com
Min
Max
5.0 5.0
2.0 2.0
6.0
5.0
Units
Fig. No.
ns
2-6
ns
2-4
ns
2-4
10.0
ns
2-4
6.0
ns
2-4
6.0
ns
2-6
4.0
ns
2-6
4-179
~~SNemaitcoinoduncatolr
54F/74F194
4-Bit Bidirectional Universal Shift Register
General Description
The 'F194 is a high-speed 4-bit bidirectional universal shift register. As a high-speed, multifunctional, sequential building block, it is useful in a wide variety of applications. It may be used in serial-serial, shift left, shift right, serial-parallel, parallel-serial, and parallel-parallel data register transfers. The 'F194 is similar in operation to the 'F195 universal shift register, with added features of shift left without external connections and hold (do nothing) modes of operation.
Features
� Typical shift frequency of 150 MHz � Asynchronous master reset � Hold (do nothing) mode � Fully synchronous serial or parallel data transfers
Ordering Code: see section 5
Logic Symbols
IEEE/IEC
MR
So S1 CP
DsR Oo
Po
P1
01
P2
02
P3
0sL
03
TL/F /9498-5
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
MR
DsR Po 3 P1 4 P2 5 P3 6
Dsl 7
GND 8
16 Vee 15 Oo 14 01 13 02 12 03 11 CP 10 S1 9 So
TL/F/9498-1
Pin Assignment forLCC
P3 P2 NC P1 Po l!J[Z]IIJ[fil[!)
~morn~ GND [QI
IIJMR
NC !Iii
O]NC
s0 llll
~Vee
s1Ii]
li]]Oo
li1ll!filliElillliE
CP 03 NC 02 01
TL/F/9498-2
DsL Po P1 P2 P3
DsR
TL/F/9498-3
Unit Loading/Fan Out: See Section 2 for U.L. Definitions
Pin Names
So,S1 Po-P3 DsR DsL CP MR Oo-03
Description
Mode Control Inputs Parallel Data Inputs Serial Data Input (Shift Right) Serial Data Input (Shift Left) Clock Pulse Input (Active Rising Edge) Asynchronous Master Reset Input (Active LOW) Parallel Outputs
54F/74F
U.L.
Input l1Hll1L
HIGH/LOW Output loHlloL
1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 50/33.3
20 �A/ -0.6 mA 20 �A/ -0.6 mA 20 �A/ -0.6 mA 20 �A/ -0.6 mA 20 �A/ -0.6 mA 20 �A/-0.6 mA -1 mA/20 mA
4-180
Functional Description
The 'F194 contains four edge-triggered D flip-flops and the necessary interstage logic to synchronously perform shift right, shift left, parallel load and hold operations. Signals applied to the Select (S0, S1) inputs determine the type of operation, as shown in the Mode Select Table. Signals on the Sel~ct, Parallel data (P0-P3) and Serial data (DsR. Dsu
inputs can change when the clock is in either state, provided only that the recommended setup and hold times, with respect to the clock rising edge, are observed. A LOW signal on Master Reset (MR) overrides all other inputs and forces the outputs LOW.
Mode Select Table
Operating
Inputs
Outputs
Mode Reset
MR
S1
So
DsR
DsL
Pn
Oo
01
02
03
L
x x
x
x
x
L
L
L
L
Hold
H
I
I
x
x
x
Qo
Q1
Q2
q3
Shift Left
H
h
I
x
I
x
Q1
Q2
q3
L
H
h
I
x
h
x
Q1
Q2
q3
H
Shift Right
H
I
h
I
H
I
h
h
x
x
L
Qo
Q1
Q2
x
x
H
Qo
Q1
Q2
Parallel Load
H
h
h
x
x
Pn
Po
P1
P2
p3
H (h) = High Voltage Level
L (I) = Low Voltage Level
Pn (q0 ) = Lower case letters indicate the state of the referenced input (or output) one setup time prior to the LOW-to-HIGH clock transition.
X = Immaterial
Logic Diagram
Po
s,
CP
03 TL/F/9498-4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-181
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 15o�c
Ambient Temperature under Bias
- 55�c to + 125�c
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5Vto +7.0V
Input Voltage (Note 2)
-0.5V to+ 7.0V
Input Current (Note 2)
-30 mA to + 5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5VtoVee -0.5Vto +5.5V
Current Applied to Output in LOW State (Max)
twice the rated IQL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�c o�cto +10�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol V1H V1L Veo VoH
VoL l1H lsv1 lcEX V10 loo l1L los lee
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 74F 10% Vee 74F5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage
Test
74F
Output Leakage
Circuit Current
74F
Input LOW Current
Output Short-Circuit Current
Power Supply Current
54F/74F Min Typ Max 2.0
0.8 -1.2 2.5 2.5 2.7 0.5 0.5 20.0 5.0 100 7.0 250
50
4.75
3.75
-0.6
-60
-150
33
46
Units v v v v
v �A �A �A v �A mA mA mA
Vee
Min Min
Min Max Max Max 0.0 0.0 Max Max Max
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal l1N = -18 mA loH = -1 mA loH = -1 mA loH = -1 mA loL = 20 mA loL = 20 mA V1N = 2.7V
V1N = 7.0V
VouT =Vee
110 = 1.9 �A All Other Pins Grounded V100 = 150mV All Other Pins Grounded V1N = 0.5V VouT = ov
4-182
AC Electrical Characteristics: See Section 2 for waveforms and Load Configurations
Symbol
Parameter
fmax tPLH tPHL tPHL
Maximum Shift Frequency
Propagation Delay GP to On Propagation Delay MR to On
74F
TA= +25�C Vee= +5.0V
CL= 50 pF
Min
Typ
Max
105
150
3.5
5.2
7.0
3.5
5.5
7.0
4.5
8.6
12.0
54F
TA, Vee= Mil CL= 50pF
Min
Max
90
3.0
8.5
3.0
8.5
4.5
14.5
74F
TA, Vee= Com CL= 50 pF
Min
Max
90
3.5
8.0
3.5
8.0
4.5
14.0
Fig. Units No.
MHz 2-1 ns 2-3 ns 2-3
AC Operating Requirements: See Section 2 for Waveforms
Symbol
Parameter
t 5 (H) t 5 (L) th(H) th(L)
t 5 (H) t 5 (L) th(H) th(L)
tw(H)
tw(L)
tree
Setup Time, HIGH or LOW Pn or DsR or DsL to GP Hold Time, HIGH or LOW Pn or DsR or DsL to GP Setup Time, HIGH or LOW Sn to GP Hold Time, HIGH or LOW Sn toCP GP Pulse Width, HIGH
MR Pulse Width, LOW
Recovery Time MR to GP
74F
TA= +25�C Vee= +5.0V
Min
Max
4.0 4.0
1.0 0
10.0 8.0
0 0
5.0
5.0
9.0
54F
TA, Vee= Mil
Min
Max
6.0 4.0
1.5 1.0
10.5 8.0
0 0
5.5
5.0
9.0
74F
TA, Vee= Com
Min
Max
4.0 4.0
1.0 1.0
11.0 8.0
0 0
5.5
5.0
11.0
Fig. Units No.
ns
2-6
ns
2-6
ns
2-4
ns
2-4
ns
2-6
4-183
.O..>..
N D~NaStemiicoonnduactlor
54F/74F219 64-Bit Random Access Memory with TRI-STATE� Outputs
General Description
The 'F219 is a high-speed 64-bit RAM organized as a 16-word by 4-bit array. Address inputs are buffered to minimize loading and are fully decoded on-chip. The outputs are TRI-STATE and are in the high-impedance state whenever the Chip Select (CS) input is HIGH. The outputs are active only in the Read mode. This device is similar to the 'F189 but features non-inverting, rather than inverting,� data outputs.
Features
� TRI-STATE outputs for data bus applications � Buffered inputs minimize loading � Address decoding on-chip � Diode clamped inputs minimize ringing � Available in SOIC (300 mil only)
Ordering Code: See Sections Logic Symbol
Connection Diagrams
CS Do D1 D2 D3 Ao A1 A2 A3 WE Oo 01 02 03
TL/F/9500-1
Pin Assignment for DIP, SOIC and Flatpak
Ao 1
cs 2
WE 3
Do 4 Oo 5 D1 6 01 7 GND 8
16 Vee 15 A1 14 A2 13 A3 12 D3 11 03 10 D2 9 02
TL/F/9500-2
Pin Assignment for LCC
rn D1 o0 NC Do WE
!!HI! []] [[I
01 !ID
GND [QI
NC !DI
02~ D2 li]
!II cs
lllAo
[I]NC
@!Vee
liIDA1
~li]J[�]lilll!E
03~NCA3 ~
TL/F/9500-3
Unit Loading/Fan Out: See Section 2 for U.L. Definitions
Pin Names
Ao-A3
cs
WE Do-D3 Oo-03
Description
Address Inputs Chip Select Input (Active LOW) Write Enable Input (Active LOW) Data Inputs TRI-STATE Data Outputs
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loHlloL
1.0/1.0 1.0/2.0 1.0/1.0 1.0/1.0 150/40 (33.3)
20 �Al -0.6 mA 20 �A/ -1.2 mA 20 �A/-0.6 mA 20 �Al -0.6 mA -3 mA/24 mA (20 mA)
4-184
.N.....
Function Table
co
Inputs
cs WE
Operation
L
L
L
H
H x
Write Read Inhibit
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Condition of Outputs
High Impedance True Stored Data High Impedance
Block Diagram
WE
+ '--_JO-.... - - - - - cs
DECODER DRIVERS
ADDRESS DECODER
16-WORD x 4-BIT MEMORY CELL ARRAY
TL/F/9500-4
4-185
O...>.. C\I Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
-55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to+ 7.0V
Input Voltage (Note 2)
-0.5V to+ 7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
-0.5VtoVcc -0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
V1H V1L Vco VoH
VoL l1H lsv1 lcEx V10 loo l1L lozH lozL los lzz Ice
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee 74F 5% Vee 74F5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage 74F
Test
Output Leakage 74F
Circuit Current
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Bus Drainage Test
Power Supply Current
54F/74F Min Typ Max
2.0
0.8 -1.2
2.5 2.4 2.5 2.4 2.7 2.7
0.5 0.5 20.0 5.0 100 7.0
250 50
4.75
3.75
-0.6 -1.2
50
-50
-60
-150
500
37
55
Units
v v
v
v
v
�A �A �A
v
�A mA �A �A mA �A mA
Vee
Min
Min
Min Max Max Max 0.0 0.0 Max Max Max Max O.OV Max
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal l1N = -18 mA loH = -1 mA loH = -3mA loH = -1 mA loH = -3 mA loH = -1 mA loH = -3 mA loL = 20 mA loL = 24 mA V1N = 2.7V
V1N = 7.0V
Vour =Vee
110 = 1.9 �A All Other Pins Grounded V100 = 150 mV All Other Pins Grounded V1N = 0.5V (An, WE, Dn) V1N = 0.5V (CS) Vour = 2.7V Vour = 0.5V
Your= ov
Vour = 5.25V
4-186
.N....
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
co
Symbol
Parameter
tPLH tPHL
tpzH tpzL
tpHz tpLz
tpzH tpzL
tpHz tpLz
Access Time, HIGH or LOW An to On
Access Time, HIGH or LOW CS to On
Disable Time, HIGH or LOW CS to On
Write Recovery Time HIGH or LOW, WE to On
Disable Time, HIGH or LOW WE to On
74F
TA= +25�c Vee= +5.0V
CL= 50 pF
Min
Typ
Max
10.0
18.5
26.0
8.0
13.5
19.0
3.5
6.0
8.5
5.0
9.0
13.0
2.0
4.0
6.0
3.0
5.5
8.0
6.5
20.0
28.0
6.5
11.0
15.5
4.0
7.0
10.0
5.0
9.0
13.0
54F
TA, Vee= Mil CL= 50 pF
Min
Max
9.0
32.0
8.0
23.0
3.5
10.5
5.0
15.0
2.0
8.0
2.5
10.0
6.5
37.5
6.5
17.5
3.5
12.0
5.0
15.0
74F
TA, Vee= Com CL= 50 pF
Fig. Units
No.
Min
Max
10.0
27.0
8.0
20.0
ns 2-3
3.5
9.5
5.0
14.0
ns 2-5
2.0
7.0
3.0
9.0
6.5
29.0
6.5
16.5
ns 2-5
4.0
11.0
5.0
14.0
AC Operating Requirements: see Section 2 tor Waveforms
Symbol
Parameter
t5 (H) t5 (L) th(H) th(L) t5 (H) t5 (L) th(H) th(L) t5 (L)
th(L)
tw(L)
Setup Time, HIGH or LOW An to WE
Hold Time, HIGH or LOW An to WE
Setup Time, HIGH or LOW Dn to WE
Hold Time, HIGH or LOW DntoWE
Setup Time, LOW CS to WE
Hold Time, LOW CS to WE
WE Pulse Width, LOW
74F
c TA= +2s0
Vee= +5.0V
Min
Max
0 0
2.0 2.0
10.0 10.0
0 0
0
6.0 6.0
54F
TA, Vee= Mil
Min
Max
0 0
2.0 2.0
11.0 11.0
2.0 2.0
0
7.5 7.5
74F
TA, Vee= Com
Min
Max
0 0
2.0 2.0
10.0 10.0
0 0
0
6.0 6.0
Fig. Units
No.
ns
2-6
ns
2-6
ns
2-6
ns
2-4
4-187
~National
U Semiconductor
54F/74F240�54F/74F241�54F/74F244
Octal Buffers/Line Drivers with TRI-STATE� Outputs
General Description
The 'F240, 'F241 and 'F244 are octal buffers and line drivers designed to be employed as memory and address drivers, clock drivers and bus-oriented transmitters/receivers which provide improved PC and board density.
Features
� TRI-STATE outputs drive bus lines or buffer memory address registers
� Outputs sink 64 mA (48 mA mil) � 12 mA source current � Input clamp diodes limit high-speed termination effects � Guaranteed 4000V minimum ESD protection
Ordering Code: see section 5 Connection Diagrams
'F240
Logic Symbols
I E E E / I EC 'F240
OE1
lo
Oo
11
01
12
02
13
03
I E E E / I EC 'F241
OE1
lo
11 12 13
N
~
� 0
N
I E E E / I EC 'F244
.N~ .�...
~
~
OE1
lo
11 12 13
OE2
OE2
OE2
I"
o"
I"
I"
15
05
15
15
15
05
15
15
17
07
17
17
TL/F/9501-7
TL/F/9501-8
TL/F/9501-9
Unit Loading/Fan Out: See Section 2 for U.L. Definitions
Pin Names
Description
OE1, OE2 OE2 lo-17 lo-11 Oo-01, Oo-01
TRI-STATE Output Enable Input (Active LOW) TRI-STATE Output Enable Input (Active HIGH) Inputs ('F240) Inputs ('F241, 'F244) Outputs
�worst-case "F240 enabled; 'F241, 'F244 disabled
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loHlloL
1.0/1.667 1.0/1.667 1.0/1.667* 1.0/2.667* 600/106.6 (80)
20 �A/-1 rnA 20 �A/-1 rnA 20 �A/-1 rnA 20 �Al -1.6 mA -12 rnA/64 rnA (48 rnA)
Truth Tables
'F240
OE1
D1n
01n
OE2
D2n
02n
H
x
z
H
x
z
L
H
L
L
H
L
L
L
H
L
L
H
'F241
OE1
D1n
01n
OE2
D2n
02n
H
x
z
L
x
z
L
H
H
H
H
H
L
L
L
H
L
L
'F244
OE1
D1n
01n
OE2
D2n
02n
H
x
z
H
x
z
L
H
H
L
H
H
L
L
L
L
L
L
H = HIGH Voltage Level L = LOW Voltage Level
X = Immaterial
Z = High Impedance
4-189
Absolute Maximum Ratings (Note 1)
If MilitaryI Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 15o�c
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5Vto +7.0V
Input Voltage (Note 2)
-0.5V to+ 7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
-0.5VtoVee - 0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
ESD Last Passing Voltage (Min)
4000V
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under
these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C o�cto +10�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
V1H V1L Veo VoH
VoL l1H lsv1 leEX V10 loo l1L
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee 74F5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Output HIGH
54F
Leakage Current 74F
Input Leakage Test
74F
Output Leakage Circuit Current
74F
Input LOW Current
lozH lozL los lzz
Output Leakage Current Output Leakage Current Output Short-Circuit Current Bus Drainage Test
54F/74F
Min Typ Max
2.0
0.8
-1.2
2.4 2.0 2.4 2.0 2.7
0.55 0.55
20.0 5.0
100 7.0
250 50
Units v v v
v
v �A �A �A
4.75
v
-100
3.75 �A
-1.0 -1.6 mA
50
�A
-50 �A
-225 mA
500 �A
Vee
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal Min l1N = -18 mA loH = -3 mA loH = -12 mA Min loH = -3mA loH = -15 mA loH = -3 mA Min loL = 48 mA loL = 64 mA Max V1N = 2.7V
�A V1N = 7.0V
Max VouT =Vee
0.0
110 = 1.9 �A All Other Pins Grounded
0.0
V100 = 150mV All Other Pins Grounded
Max
V1N = 0.5V (OE1, OE2. OE2. Dn ('F240)) V1N = 0.5V (Dn ('F241, 'F244))
Max VouT = 2.7V
Max VouT = 0.5V
Max VouT = ov
o.ov VouT = 5.25V
4-190
DC Electrical Characteristics (Continued)
Symbol
lccH lccL lccz lccH
lccL
lccz
Parameter
Power Supply Current ('F240) Power Supply Current ('F240) Power Supply Current ('F240) Power Supply Current ('F241, 'F244) Power Supply Current ('F241, 'F244) Power Supply Current ('F241, 'F244)
54F/74F
Units
Vee
Min
Typ
Max
Conditions
19
29
mA
Max
Vo= HIGH
50
75
mA
Max
Vo= LOW
42
63
mA
Max
Vo= HIGHZ
40
60
mA
Max
Vo= HIGH
60
90
mA
Max
Vo= LOW
60
90
mA
Max
Vo= HIGHZ
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
tPLH tPHL
tpzH tpzL
tpHz tpLz
tPLH tPHL
tpzH tpzL
tpHz tpLz
Propagation Delay Data to Output ('F240) Output Enable Time ('F240)
Output Disable Time ('F240)
Propagation Delay Data to Output ('F241, 'F244) Output Enable Time ('F241, 'F244) Output Disable Time ('F241, 'F244)
74F
TA= +25�C Vee= +s.ov
CL= 50 pF
Min
Typ
Max
3.0
5.1
7.0
2.0
3.5
4.7
2.0
3.5
4.7
4.0
6.9
9.0
2.0
4.0
5.3
2.0
6.0
8.0
2.5
4.0
5.2
2.5
4.0
5.2
2.0
4.3
5.7
2.0
5.4
7.0
2.0
4.5
6.0
2.0
4.5
6.0
54F
TA, Vee= Mil CL= SOpF
Min
Max
3.0
9.0
2.0
6.0
2.0
6.5
4.0
10.5
2.0
6.5
2.0
12.5
2.0
6.5
2.0
7.0
2.0
7.0
2.0
8.5
2.0
7.0
2.0
7.5
74F
TA, Vee= Com
Fig. Units
CL= 50 pF
No.
Min
Max
3.0
8.0
ns 2-3
2.0
5.7
2.0
5.7
4.0
10.0
ns 2-5
2.0
6.3
2.0
9.5
2.5
6.2
ns 2-3
2.5
6.5
2.0
6.7
2.0
8.0
ns 2-5
2.0
7.0
2.0
7.0
II
4-191
D~NaStemiicoonnduactlor
54F/74F243
Quad Bus Transceiver with TRI-STATE� Outputs ,
General Description
The 'F243 is a quad bus transmitter/receiver designed for 4-line asynchronous 2-way data communications between data busses.
Features
� 2-Way asynchronous data bus communication � Input clamp diodes limit high-speed termination effects � Guaranteed 4000V minimum ESD protecti~n
Ordering Code: see section 5 Logic Symbol
Connection Diagrams
I E E E / I EC
Pin Assignment for DIP, SOIC and Flatpak
Pin Assignment forLCC
E2 E1
E1 _.1+-4ll>--. NC 2
o~oNmCAm1 rNnCAron
Ao
Bo
Ao 3
A3 [ID
!]]NC
A1 ..:!4:1...r+.-1>-'.::--,
GND [Q]
!lJE1
A1
B1
A2 ...:::S:t--++t>-;:=i""T
A3 ...s. ,.__I>-'~
NC [i]
B3 li1I .,.._L..f-+1f+f-.lf--.
O]NC ~Vee
A2
B2
GND 7
82 Ml
l!IDE2
AJ
83
TL/F/9502-1
liJl[i]J[fil[Z][iE
B1 NC Bo NC NC
TL/F/9502-3
TL/F /9502-2
Unit Loading/Fan Out: see Section 2 for U.L. definitions
54F/74F
Pin Names
Description
U.L. HIGH/LOW
Input l1Hll1L Output loHlloL
E1
E2 An, Bn
Enable Input (Active LOW) 1.0/1.67
20 �A/-1 mA
Enable Input (Active HIGH) 1.0/1.67
20 �A/-1 mA
Inputs
3.5/2.67
70 �Al -1.6 mA
Outputs
600/106.6(80) -12 mA/64 mA(48 mA)
Truth Table
Inputs
E1
E2
L
L
L
H
H
L
H
H
Inputs/Outputs
An
Input N/A
z
A=B
Bn
B=A N/A
z
Input
H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance NIA = Not Allowed
4-192
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for avallablllty and specifications.
Storage Temperature
- 65�C to + 1so�c
Ambient Temperature under Bias
- ss�c to + 125�c
Junction Temperature under Bias
- ss�c to + 17s�c
Vee Pin Potential to Ground Pin
-0.5Vto +7.0V
Input Voltage (Note 2)
-0.5V to+ 7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
-o.sv to Vee -0.5Vto +5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
ESD Last Passing Voltage (Min)
4000V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�c o�cto +70�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
V1H V1L Veo VoH
VoL
l1H
lsv1
lsv1r
leEX
V10
loo
l1L l1H + lozH l1L + lozL los leeH leeL leez
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee 74F5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Input HIGH Current 54F
Breakdown (1/0)
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage
Test
74F
Output Leakage Circuit Current
74F
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Power Supply Current
Power Supply Current
Power Supply Current
54F/74F
Min Typ Max
2.0
0.8
-1.2
2.4 2.0 2.4 2.0 2.7
0.55 0.55
20.0 5.0
100 7.0
1.0 0.5
250 50
4.75
3.75
-1.0
70
-1.6
-100
-225
64
80
64
90
71
90
Units v v v
v
v
�A
�A mA
�A v
�A mA �A mA mA mA mA mA
Vee
Min
Min
Min Max Max Max Max 0.0 0.0 Max Max Max Max Max Max Max
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal l1N= -18mA loH = - 3 mA (An, Bn) loH = -12 mA (An, Bn) loH = - 3 mA (An, Bn) loH = -15 mA (An, Bn) loH = -3 mA (An. Bn) loL = 48 mA (An. Bn) loL = 64 mA (An. Bn) V1N = 2.7V
V1N = 7.0V (E1, E2)
V1N = 5.5V (An, Bn)
Vour =Vee
110 = 1.9 �A All Other Pins Grounded V100 = 150mV All Other Pins Grounded V1N = 0.5V (E1, E2) Vour = 2.7V (An. Bn) Vour = 0.5V (An. Bn) Vour = OV (An, Bn) Vo= HIGH Vo= LOW Vo= HIGHZ
4-193
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
tPLH lPHL
tpzH tpzL
tpHz lpLz
Propagation Delay An to Bn. Bn to An
Output Enable Time
E1 to Bn, E2 to An
Output Disable Time
E1 to Bn. E2 to An
74F
TA= +25�C Vee= +5.0V
CL= 50pF
Min
Typ
Max
2.5
4.0
5.2
2.5
4.0
5.2
2.0
4.3
5.7
2.0
5.8
7.5
2.0
4.5
6.0
2.0
4.5
6.0
54F
TA, Vee= Mil CL= 50pF
Min
Max
2.0
6.5
2.0
8.5
2.0
8.0
2.0
10.5
1.5
7.5
2.0
8.5
74F
TA, Vee= Com CL= 50 pf
Min
Max
2.0
6.2
2.0
6.5
2.0
6.7
2.0
8.5
1.5
7.0
2.0
7.0
Units
Fig. No.
ns 2-3 ns 2-5
4-194
U~NaStemiicoonnduactlor
54F/74F245
Octal Bidirectional Transceiver with TRI-STATE� Outputs
General Description
The 'F245 contains eight non-inverting bidirectional buffers with TRI-STATE outputs and is intended for bus-oriented applications. Current sinking capability is 24 mA (20 mA Mil) at the A ports and 64 mA (48 mA Mil) at the B ports. The Transmit/Receive (T/A) input determines the direction of data flow through the bidirectional transceiver. Transmit (active HIGH) enables data from A ports to B ports; Receive (active LOW) enables data from B ports to A ports. The Output Enable input, when HIGH, disables both A and B ports by placing them in a High Z condition.
Features
� Non-inverting buffers � Bidirectional data path � A outputs sink 24 mA (20 mA Mil) � B outputs sink 64 mA (48 mA Mil) � Guaranteed 4000V minimum ESD protection
Ordering Code: see Section 5 Logic Symbols
Connection Diagrams
OE
T/R
TL/F/9503-3
IEEE/I EC OE T/R
Ao
Bo
A1
e,
Az
Bz
A3
83
A4
84
As
85
As
Bs
A1
87
TL/F/9503-4
Pin Assignment for DIP, SOIC and Flatpak
A1 -J'~==::::;t~'t.!�
A2....;.+~P---.'-'f"~-.. A3--+~f--.'-"""""'a-...-.. A4-.:.+.0:f-,L...-f'~;.;;. As....:.+.O:f-i'~-f'~;..;..
TL/F/9503-1
Pin Assignment for LCC
rnmmmm A6 As A4 A3 A2
A11fil GND !IQ]
ITI A,
m ;:m-1mimimrm~11; Ao
87 [!]
[j] T/R
e6 li1l �,1~mmmtv~lWl ~Vee
85 [j]
!Ifil OE
II!] fill [j] !ill [fil
84 83 82 81 Bo TL/F/9503-2
4-195
Unit Loading/Fan Out: See Section 2 for u.L definitions
Pin Names
OE T/R Ao-A7
Bo-B7
Description
Output Enable Input (Active LOW) Transmit/Receive Input Side A Inputs or TRI-STATE Outputs Side B Inputs or TRI-STATE Outputs
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loHlloL
1.0/2.0 1.0/2.0 3.5/1.083 150140(38.3) 3.5/1.083 600/106.6(80)
20 �A/ -1.2 mA 20 �A/ -1.2 mA 70 �A/ -0.65 mA -3 mA/24 mA (20 mA) 70 �A/ -0.65 mA -12 mA/64 mA (48 mA)
Truth Table
Inputs
OE
T/R
L
L
L
H
H
x
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
Output
Bus B Data to Bus A Bus A Data to Bus B High Z State
4-196
Absolute Maximum Ratings (Note 1>
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for avallablllty and specifications.
Storage Temperature
-65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5Vto +7.0V
Input Voltage (Note 2)
-0.5V to + 7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
-0.5VtoVec - 0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated Im (mA)
ESD Last Passing Voltage (Min)
4000V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol V1H V1L Veo VoH
Vol
l1H lsv1 lsv1r leEx V10 loo l1L l1H + lozH l1L + lozL
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee 74F5% Vee
Output LOW Voltage
54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F Breakdown Test 74F
Input HIGH Current 54F Breakdown (1/0) 74F
Output HIGH
54F
Leakage Current 74F
Input Leakage
Test
74F
Output Leakage
Circuit Current
74F
Input LOW Current
Output Leakage Current
Output Leakage Current
54F/74F Min Typ Max 2.0
0.8 -1.2 2.4 2.0 2.4 2.0 2.7 0.5 0.55 0.5 0.55 20.0
5.0 100 7.0 1.0 0.5 250 50
4.75
3.75
-1.2 70
-650
Units
v v v
v
v
�A �A mA �A
v
�A mA �A �A
Vee
Conditions
Recognized as a HIGH Signal
Recognized as a LOW Signal
Min l1N = -18 mA loH = -3 mA (An) loH = -12 mA (Bn)
loH = -3 mA (An)
Min IOH = -15 mA (Bn)
loH = -3 mA (An) loL = 20 mA (An) loL = 48 mA (Bn) Min loL = 24 mA (An) loL = 64 mA (Bn)
Max V1N = 2.7V
Max V1N = 7.0V (OE, T /A)
Max
Max
IJD = 1.9 �A 0.0
All Other Pins Grounded
0.0
V100 = 150 mV All Other Pins Grounded
Max V1N = 0.5V (T/A, OE)
Max Vour = 2.7V (An. Bn)
Max Vour = 0.5V (An. Bn)
4-197
DC Electrical Characteristics (Continued)
Symbol
Parameter
las
Output Short-Circuit Current
lzz lccH lccL lccz
Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current
Min
-60 -100
54F/74F Typ
70 95 85
Max -150 -225 500
90 120 110
Units
mA �A mA mA mA
Vee
Max
o.ov
Max Max Max
Conditions
Vour = ov (An)
Vour = OV (Bn) Vour = 5.25V(An. Bn) Vo= HIGH Vo= LOW Vo= HIGHZ
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
tPLH
Propagation Delay
tPHL
An to Bn or Bn to An
tpzH
Output Enable Time
tpzL
tpHz
Output Disable Time
tpLZ
74F
TA= +25�C Vee= +5.0V
CL= 50 pf
Min
Typ
Max
2.5
4.2
6.0
2.5
4.2
6.0
3.0
5.3
7.0
3.5
6.0
8.0
2.0
5.0
6.5
2.0
5.0
6.5
54F
TA, Vee= Mil CL= 50 pf
Min
Max
2.0
7.5
2.0
7.5
2.5
9.0
3.0
10.0
2.0
9.0
2.0
10.0
74F
TA, Vee= Com CL= 50 pf
Min
Max
2.0
7.0
2.0
7.0
2.5
8.0
3.0
9.0
2.0
7.5
2.0
7.5
Fig. Units No.
ns
2-3
ns
2-5
4-198
I\)
~National
.U...1.. l>
~Semiconductor
54F/74F251A 8-lnput Multiplexer with TRI-STATE� Outputs
General Description
The 'F251A is a high-speed 8-input digital multiplexer. It provides, in one package, the ability to select one bit of data from up to eight sources. It can be used as a universal function generator to generate any logic function of four variables. Both assertion and negation outputs are provided.
Features
� Multifunctional capability � On-chip select logic decoding � Inverting and non-inverting TRI-STATE outputs
Ordering Code: see section 5 Logic Symbols
Connection Diagrams
So lo 11 12 13 I" 15 Is 17
S1 Sz OE
IEEE/I EC
TL/F/9504-3
t.IUX
5E EN
} So
S1 Sz
lo
11
v
12
v
13
14
15
Is
17
TL/F/9504-5
Pin Assignment for DIP, SOIC and Flatpak
13
12 2
1, 3
lo 4
z 5
z 6
OE 7
GND 8
16 Vee 15 14 14 15 13 15 12 17 11 So
10 s,
9 Sz
TL/F/9504-1
Pin Assignment forLCC
Z
llil
ZmNllilCrnbrln1
OE[[)
GND [QI NC [i]
S2 !lll
S1 []
ITll2
[1]13 [I]NC
l?.Q)Vcc 112114
~!j]j[�J[Z]l!�J
So '7 NC Is Is
TL/F/9504-2
Unit Loading/Fan Out: See Section 2 for U.L. definitions
Pin Names
So-S2 OE lo-11
z z
Description
Select Inputs TRI-STATE Output Enable input (Active LOW) Multiplexer Inputs TRI-STATE Multiplexer Output Complementary TR I-STATE Multiplexer Output
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loHllOL
1.0/1.0 1.0/1.0 1.0/1.0 150/40 (33.3) 150/40 (33.3)
20 �A/-0.6 mA 20 �A/-0.6 mA 20 �A/-0.6 mA -3 mA/24 mA (20 mA) -3 mA/24 mA (20 mA)
4-199
<,..(. ~ Functional Description
This device is a logical implementation of a single-pole, 8position switch with the switch position controlled by the state of three Select inputs, So. S1, S2. Both assertion and negation outputs are provided. The Output Enable input (OE) is active LOW. When it is activated, the logic function provided at the output is:
Z = OE�(lo�So�S1 �S2 + l1�So�S1�S2 + l2�So�S1 �S2 + l3�So�S1 �S2 + l4�So�S1�S2 + l5�So�S1�S2 + l5�So�S1 �S2 + l7�So�S1 �S2)
When the Output Enable is HIGH, both outputs are in the high impedance (High Z) state. This feature allows multiplexer expansion by tying the outputs of up to 128 devices together. When the outputs of the TRI-STATE devices are tied together, all but one device must be in the high impedance state to avoid high currents that would exceed the
Logic Diagram
maximum ratings. The Output Enable signals should be designed to ensure there is no overlap in the active LOW portion of the enable voltages.
Truth Table
Inputs
Outputs
OE
52
51
So
z
z
H
x x xzz
L
L
L
L
To
lo
L
L
L
H
T1
11
L
L
H
L
T2
12
L
L
H
L
H
L
L
H
L
L
H
H
L
H
H
H = HIGH Voltage Level L ;,, LOW Voltage Level X = Immaterial Z = High Impedance
H
i3
13
L
i4
14
H
is
15
L H
Tr,s
Is 17
z z
TL/F/9504-4 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-200
Absolute Maximum Ratings (Note 1>
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 15o�c
Ambient Temperature under Bias
- 55�c to + 125�c
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to + 7.0V
Input Voltage (Note 2)
-0.5V to + 7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
-0.5VtoVee -0.5V to+ 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
I\)
Recommended Operating
.U...1.
l>
Conditions
Free Air Ambient Temperature Military Commercial
- 55�c to + 125�c
o�cto +1o�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol V1H V1L Veo VoH
Vol l1H lsv1
le Ex
V10 loo IJL lozH lozL los lzz leeL leez
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee 74F5% Vee 74F5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current
54F
Breakdown Test
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage Test
74F
Output Leakage
74F
Circuit Current
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Bus Drainage Test
Power Supply Current
Power Supply Current
54F/74F
Min Typ Max
2.0
0.8 -1.2
2.5 2.4 2.5 2.4 2.7 2.7
0.5 0.5
20.0 5.0 100 7.0
250 50
4.75
3.75
-0.6
50
-50
-60
-150
500
15
22
16
24
Units
v v v
v
v
�A
�A
�A
v
�A mA �A �A mA �A mA mA
Vee
Min
Min
Min Max Max Max 0.0 0.0 Max Max Max Max o.ov Max Max
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal l1N = -18 mA loH = -1 mA loH = -3 mA loH = -1 mA loH = -3mA loH = -1 mA loH = -3 mA loL = 20mA loL = 24mA V1N = 2.7V
V1N = 7.0V
Vour =Vee
110 = 1.9 �A All Other Pins Grounded V100 = 150 mV All Other Pins Grounded V1N = 0.5V Vour = 2.7V Vour = 0.5V Vour = ov Vour = 5.25V Vo= LOW Vo= HIGHZ
4-201
<
~'I""" AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
tpLH tpHL
tpLH tPHL
tPLH tPHL
tPLH tPHL
tpzH tpzL
tpHz tpLz
tpzH tpzL
tpHz tpLz
Propagation Delay SntoZ
Propagation Delay SntoZ
Propagation Delay lntoZ
Propagation Delay In to Z
Output Enable Time OEtoZ
Output Disable Time OEtoZ
Output Enable Time OEtoZ
Output Disable Time OEtoZ
74F
TA= +25�C Vee= +5.0V
CL= 50pF
Min
Typ
Max
3.5
6.0
9.0
3.2
5.0
7.5
4.5
7.5
10.5
4.0
6.0
8.5
3.0
5.0
6.5
1.5
2.5
4.0
3.5
5.0
7.0
3.5
5.5
7.0
2.5
4.3
6.0
2.5
4.3
6.0
2.5
4.0
5.5
1.5
3.0
4.5
3.5
5.0
7.0
3.5
5.5
7.5
2.0
3.8
5.5
1.5
3.0
4.5
54F
TA, Vee= Mil CL= 50 pF
Min
Max
3.5
11.5
3.2
8.0
3.5
14.0
3.0
10.5
2.5
8.0
1.5
6.0
2.5
9.0
3.5
9.0
2.0
7.0
2.5
7.5
2.5
6.0
1.5
5.0
3.0
8.5
3.5
9.0
2.0
5.5
1.5
5.5
74F
TA, Vee= Com CL= 50 pF
Min
Max
3.5
9.5
3.2
7.5
4.5
12.5
4.0
9.0
3.0
7.0
1.5
5.0
2.5
8.0
3.5
7.5
2.5
7.0
2.5
6.5
2.5
6.0
1.5
4.5
3.0
7.5
3.5
8.0
2.0
5.5
1.5
4.5
Units Fig. No.
ns 2-3 ns 2-3 ns 2-3 ns 2-3 ns 2-5
ns 2-5
4-202
I\)
~National
Uw 1
~Semiconductor
54F/74F253 Dual 4-lnput Multiplexer with TRI-STATE� Outputs
General Description
The 'F253 is a dual 4-input multiplexer with TRI-STATE� outputs. It can select two bits of data from four sources using common select inputs. The output may be individually switched to a high impedance state with a HIGH on the respective Output Enable (OE) inputs, allowing the outputs to interface directly with bus oriented systems.
Features
� Multifunction capability � Non-inverting TRI-STATE outputs � Guaranteed 4000V minimum ESD protection
Ordering Code: see section 5
Logic Symbols
Connection Diagrams
OEa 1oa 11a 12a 13a 1ob 11 b l2b l3b
Pin Assignment for DIP, SOIC and Flatpak
Pin Assignment for LCC
So
S1
OEb
Za
zb
IEEE/I EC
TL/F/9505-3
So S1
MUX
OEa EN
loa
0
l1a
l2a
2
13a
3
CiEb
lob
l1b
lzb
l3b
TL/F/9505-5
OE a
S1 2
13a l2a 4 l1a 5 loa 6 Za 7 GND
16 Vee
15 CiEb 14 So 13 l3b 12 lzb 11 l1b 10 lob
zb
TL/F/9505-1
Za [ID GND [Q]
NC [j]
zb ll1l
lob ff]
rns1
II!CiEa [I]NC ~Vee [J]] CiEb
Ii] l!m [�] [ZJ Ii]]
l1b lzb NC l3b So TL/F/9505-2
Unit Loading/Fan Out: See Section 2 for u.L. definitions
Pin Names
loa-13a lob-13b So-S1 OEa OEb Za,Zb
Description
Side A Data Inputs Side B Data Inputs Common Select Inputs Side A Output Enable Input (Active LOW) Side B Output Enable Input (Active LOW) TRI-STATE Outputs
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loHlloL
1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 150/40(33.3)
20 �A/-0.6 mA 20 �A/-0.6 mA 20 �A/-0.6 mA 20 �A/ -0.6 mA 20 �A/ -0.6 mA -3 mA/24 mA (20 mA)
4-203
Functional Description
This device contains two identical 4-input multiplexers with TRI-STATE outputs. They select two bits from four sources selected by common Select inputs (S0, S1). The 4-input multiplexers have individual Output Enable (OEa. OEb) inputs which, when HIGH, force the outputs to a high impedance (High Z) state. This device is the logic implementation of a 2-pole, 4-position switch, where the position of the switch is determined by the logic levels supplied to the two select inputs. The logic equations for the outputs are shown below:
Za = OEa � (loa � S1 �So + l1a � S1 �So + l2a � S1 � So + Isa � S1 � So)
zb = OEb �(lob� S1 �So + l1b � S1 �So + l2b � S1 � So + lsb � S1 � So)
If the outputs of TRI-STATE devices are tied together, all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. Designers should ensure that Output Enable signals to TRISTATE devices whose outputs are tied together are designed so that there is no overlap.
Truth Table
Select Inputs
Data Inputs
So
S1
lo
11
12
13
x xxxxx L L L xxx L L H xxx H L xL xx
H L xH xx L H xxL x L H xxH x H H xxxL H H xxxH
Address inputs So and S1 are common to both sections.
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
Z = High Impedance
Logic Diagram
Output Enable
OE
H L L L
L L L L L
Output
z
z L H L
H L H L H
TL/F/9505-4 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-204
Absolute Maximum Ratings (Note 1)
If MiiitaryI Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for avallablllty and specifications.
Storage Temperature
- 65�C to + 150�c
Ambient Temperature under Bias
- 55�C to + 125�c
Junction Temperature under Bias
-55�Cto +175�C
Vee Pin Potential to Ground Pin
-0.5Vto +7.0V
Input Voltage (Note 2)
-0.5Vto +7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TAI-STATE Output
-0.5V to Vee -0.5Vto +5.5V
N
(J1 (..)
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
ESD Last Passing Voltage (Min)
4000V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�c o�cto +70�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
V1H V1L Veo VoH
Vol l1H lsv1 leEx V10 loo l1L lozH lozL los
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee 74F5% Vee 74F5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage Test
74F
Output Leakage Circuit Current
74F
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
lzz leeH leeL leez
Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current
54F/74F
Min Typ Max
2.0
0.8 -1.2
2.5 2.4 2.5 2.4 2.7 2.7
0.5 0.5
20.0 5.0
100 7.0
250 50
4.75
3.75
-0.6
50
-50
-60 -100
-150 -225
500
11.5
16
16
23
16
23
Units v v v
v
v �A �A �A v �A mA �A �A mA �A mA mA mA
Vee
Min
Min
Min Max Max Max 0.0 0.0 Max Max Max Max o.ov Max Max Max
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal l1N = -18mA loH = -1 mA loH = -3 mA loH = -1 mA loH = -3 mA loH = -1 mA loH = -3 mA loL = 20 mA loL = 24 mA
V1N = 2.7V
V1N = 7.0V
Vour =Vee
110 = 1.9 �A All Other Pins Grounded V100 = 150 mV All Other Pins Grounded V1N = 0.5V Vour = 2.7V Vour = o.sv Vour = ov Vour = ov Vour =Vee Vo= HIGH Vo= LOW Vo= HIGHZ
4-205
AC Electrical Characteristics: See Section 2 tor Waveforms and Load Configurations
Symbol
Parameter
tPLH tPHL
tPLH tPHL
tpzH tpzL
tpHz tpLZ
Propagation Delay Sn to Zn Propagation Delay Into Zn Output Enable Time
Output Disable Time
74F
TA= +2s0 c Vee= +s.ov
CL= 50pF
Min
Typ
Max
4.5
8.5
11.5
3.0
6:5
9.0
3.0
5.5
7.0
2.5
4.5
6.0
3.0
6.0
8.0
3.0
6.0
8.0
2.0
3.7
5.0
2.0
4.4
6.0
54F
TA, Vee= Mii CL= 50pF
Min
Max
3.5
15.0
2.5
11.0
2.5
9.0
2.5
8.0
2.5
10.0
2.5
10.0
2.0
6.5
2.0
8.0
74F
TA, Vee= Com CL= 50pF
Min
Max
4.5
13.0
3.0
10.0
3.0
8.0
2.5
7.0
3.0
9.0
3.0
9.0
2.0
6.0
2.0
7.0
Fig. Units No.
ns 2-3 ns 2-3 ns 2-5
4-206
~National
U Semiconductor
54F/74F257A
Quad 2-lnput Multiplexer with TRI-STATE� Outputs
General Description
The 'F257A is a quad 2-input multiplexer with TRI-STATE outputs. Four bits of data from two sources can be selected using a Common Data Select input. The four outputs present the selected data in true (non-inverted) form. The outputs may be switched to a high impedance state with a HIGH on the common Output Enable (OE) input, allowing the outputs to interface directly with bus-oriented systems.
Features
� Multiplexer expansion by tying outputs together � Non-inverting TRI-STATE outputs � Input clamp diodes limit high-speed termination effects � Guaranteed 4000V minimum ESD protection
Ordering Code: see sections Logic Symbols
OE
IEEE/IEC
TL/F/9507-3
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
s 1
loa 2 l1a 3 Za
lob l1b 6 zb 7 GND 8
16 Vee
15 OE
14 loc 13 l1c 12 Zc 11 lad 10 l1d 9 zd
TL/F/9507-1
Pin Assignment forLCC
l1b I]]
mbl> !N]C]
rlan
rl1na
G:~:o~~a
� NC Ii]
DJ NC
Zd!ill
~Vee
l1d fill
l!m OE
[j] [j]] [�] !iZl I!�] bi le NC l1c loc
TL/F/9507-2
1011
11a
Za
lob zb
l1b
lod zd
l1d
loc Zc
l1c
TL/F/9507-5
Unit Loading/Fan Out: See Section 2 tor U.L. definitions
Pin Names
s OE loa-lod l1a-l1d Za-Zd
Description
Common Data Select Input TRI-STATE Output Enable Input (Active LOW) Data Inputs from Source 0 Data Inputs from Source 1 TRI-STATE Multiplexer Outputs
54F/74F
U.L. HIGH/LOW
Input l1HlllL Output loHlloL
1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 150/40 (33.3)
20 �Al -0.6 mA 20 �A/ -0.6 mA 20 �Al -0.6 mA 20 �Al -0.6 mA -3 mA/24 mA (20 mA)
4-207
Functional Description
The 'F257A is a quad 2-input multiplexer with TRI-STATE
outputs. It selects four bits of data from two sources under
control of a Common Data Select input. When the Select
input is LOW, the lox inputs are selected and when Select is
HIGH, the 11x inputs are selected. The data on the selected inputs appears at the outputs in true (non-inverted) form.
The device is the logic implementation qf a 4-pole, 2-posi-
tion switch where the position of the switch is determined by
the logic levels supplied to the Select input. The logic equa-
tion for the outputs is shown below:
�
Zn = OE � (In � S + Ion � S)
When the Output Enable input (OE) is HIGH, the outputs are forced to a high impedance OFF state. If the outputs are tied together, all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. Designers should ensure the Output Enable signals to TRI-STATE devices whose outputs are tied together are designed so there is no overlap.
Logic Diagram
1oa
l1a � '� 1ob
l1b
Truth Table
Output Enable
OE
H L L L L
Seiect Input
s x
H H L L
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance
Data Inputs
lo
11
x x x L x H L .x H x
Output
z z
L H L H
l1d
s
TL/F/9507-4 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-208
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 1so�c
Ambient Temperature under Bias
- ss�c to + 12s0 c
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to + 7.0V
Input Voltage (Note 2)
-0.5V to + 7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
-0.5VtoVee -0.5Vto +5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
ESD Last Passing Voltage (Min)
4000V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- ss�c to + 12s0 c o�cto +70�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
V1H V1L Veo VoH
Vol l1H
lsv1 leEX V10 loo l1L lozH lozL los lzz leeH leeL leez
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee 74F5% Vee 74F5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage Test
74F
Output Leakage Circuit Current
74F
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Bus Drainage Test
Power Supply Current
Power Supply Current
Power Supply Current
54F/74F
Min Typ Max
2.0
0.8
-1.2
2.5 2.4 2.5 2.4 2.7 2.7
0.5 0.5
20.0 5.0
100 7.0
250 50
4.75 }
3.75
-0.6
50
-50
-60
-150
500
9.0
15
14.5
22
15
23
Units v v v
v
v
�A �A
�A v
�A mA �A �A mA �A mA mA mA
Vee
Min
Min
Min Max Max Max 0.0 0.0 Max Max Max Max o.ov Max Max Max
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal l1N = -18mA loH = -1 mA loH = -3mA loH = -1 mA loH = -3mA loH = -1 mA loH=-3mA loL = 20 mA loL = 24 mA V1N = 2.7V
V1N = 7.0V
Vour =Vee
110 = 1.9 �A All Other Pins Grounded V100 = 150 mV All Other Pins Grounded V1N = 0.5V Vour = 2.7V Vour = 0.5V Vour = ov Vour = 5.25V Vo= HIGH Vo= LOW Vo= HIGHZ
4-209
..c...:,.(,.
C\I
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
74F
54F
74F
Symbol
Parameter
TA= +25�C Vee= +5.0V
CL= 50 pf
TA, Vee= Mil CL= 50 pf
TA, Vee= Com CL= 50 pf
Min
Typ
Max
Min
Max
Min
Max
tPLH
Propagation Delay
2.5
4.5
5.5
2.0
7.0
2.0
6.0
tPHL
In to Zn
2.0
4.2
5.5
1.5
7.0
2.0
6.0
tPLH
Propagation Delay
4.0
5.0
9.5
3.5
11.5
3.5
10.5
tPHL
StoZn
2.5
6.5
7.0
2.5
9.0
2.5
8.0
tpzH
Output Enable Time
2.0
5.9
6.0
2.0
8.0
2.0
7.0
tpzL
2.5
5.5
7.0
2.5
9.0
2.5
8.0
tpHz
Output Disable Time
2.0
4.3
6.0
2.0
7.0
2.0
7.0
tpLz
2.0
4.5
6.0
2.0
8.5
2.0
7.0
Fig. Units
No.
ns
2-3
ns
2-3
ns
2-5
4-210
N
U1
~National
ClO )>
~Semiconductor
54F/74F258A
Quad 2-lnput Multiplexer with TRI-STATE� Outputs
General Description
The 'F258A is a quad 2-input multiplexer with TRI-STATE outputs. Four bits of data from two sources can be selected using a common data select input. The four outputs present the selected data in the complement (inverted) form. The outputs may be switched to a high impedance state with a HIGH on the common Output Enable (OE) input, allowing the outputs to interface directly with bus-oriented systems.
Features
� Multiplexer expansion by tying outputs together � Inverting TRI-STATE outputs � Guaranteed 4000V minimum ESD protection
Ordering Code: see section 5 Logic Symbols
OE
TL/F/9508-3
IEEE/I EC OE EN
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
s
lea l1a Za 4 lob l1b zb GND
16 Vee 15 OE
14 Ice 13 l1e 12 Ze 11 led 10 l1d 9 zd
TL/F/9508-1
Pin Assignment for LCC
[l1]b] [~zb::NrnCmlaJ rl1na
zb rn
GND [QI NC [i]
zd li1I
l1d Ii]
l]]loa
ills
IJ] NC
Im Vee Ii]] OE
li}]~li][Z][�]
~ Ze NC l1e loc
TL/F/9508-2
MUX I>
1oa 1
l1a
" Za
lob zb
l1b
Ice ze
l1e
1od
zd
l1d
TL/ F/9508-5
Unit Loading/Fan Out: See Section 2 for u.L. Definitions
Pin Names
s OE loa-lod l1a-l1d Za-Zd
Description
Common Data Select Input TRI-STATE Output Enable Input (Active LOW) Data Inputs from Source 0 Data Inputs from Source 1 TRI-STATE Inverting Data Outputs
54F/74F
U.L. HIGH/LOW
Input l1HlltL Output loHlloL
1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 150/40 (33.3)
20 �A/-0.6 mA 20 �A/-0.6 mA 20 �A/-0.6 mA 20 �A/-0.6 mA -3 mA/24 mA (20 mA)
4-211
<c~o Functional Description
The 'F258A is a quad 2-input multiplexer with TRI-STATE outputs. It selects four bits of data from two sources under control of a common Select input (S). When the Select input is LOW, the lox inputs are selected and when Select is HIGH, the 11x inputs are selected. The data on the selected � inputs appears at the outputs in inverted form. The 'F258A is the logic implementation of a 4-pole, 2-position switch where the position of the switch is determined by the logic levels supplied to the Select input. The logic equation for the outputs is shown below:
Zn= OE�(l1n�S + lon�S)
When the Output Enable input (OE) is HIGH, the outputs are forced to a high impedance OFF state. If the outputs of the TRI-STATE devices are tied together, all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. Designers should ensure that Output Enable signals to TRI-STATE devices whose outputs are tied together are designed so there is no overlap.
Truth Table
Output Enable
OE
H L L L L
Select Input
s
x
H H L L
Data Inputs
lo
11
x
x
x
L
x
H
L
x
H
x
Output
z z
H L H L
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance
Logic Diagram
TL/F /9506-4 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-212
Absolute Maximum Ratings (Note 1)
If Miiitary/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for avallablllty and specifications.
Storage Temperature
- 65�C to + 15o�c
Ambient Temperature under Bias
- 55�C to + 12s0 c
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to + 7.0V
Input Voltage (Note 2)
-0.5V to + 7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
-0.5VtoVee -0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
ESD Last Passing Voltage (Min)
4000V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
I\)
U1
Recommended Operating
Q)
l>
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�cto +10�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
V1H V1L Veo VoH
VoL
l1H
lsv1
leEx V10
loo
l1L lozH lozL los lzz leeH leeL leez
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee 74F5% Vee 74F5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage Test
74F
Output Leakage Circuit Current
74F
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Bus Drainage Test
Power Supply Current
Power Supply Current
Power Supply Current
54F/74F
Min Typ Max
2.0
0.8 -1.2
2.5 2.4 2.5 2.4 2.7 2.7
0.5 0.5
20.0 5.0
100 7.0
250 50
4.75
-60
6.2 15.1 11.3
3.75
-0.6 50 -50
-150 500 9.5 23 17
Units v v v
v
v
�A �A
�A
v
�A mA �A �A mA �A mA mA mA
Vee
Min
Min
Min Max Max Max 0.0 0.0 Max Max Max Max o.ov Max Max Max
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal l1N = -18 mA loH = -1 mA loH = -3mA loH = -1 mA loH = -3 mA loH = -1 mA loH = -3mA loL = 20 mA loL = 24 mA V1N = 2.7V
V1N = 7.0V
Vour =Vee
110 = 1.9 �A All Other Pins Grounded V100 = 150mV All Other Pins Grounded V1N = 0.5V Vour = 2.7V Vour = 0.5V Vour = ov Vour =Vee Vo= HIGH Vo= LOW Vo= HIGHZ
4-213
<(
co
LI)
N
AC Electrical Characteristics: see Section 2 for Waveforms and Load Configurations
74F
54F
74F
Symbol
Parameter
TA= +25�c Vee= +5.0V
CL= 50pF
TA, Vee= Mil CL= 50pF
TA, Vee= Com CL= 50 pF
Min
Typ
Max
Min
Max
Min
Max
tPLH
Propagation Delay
2.5
tPHL
Into Zn
1.0
5.3
2.0
7.5
2.0
6.0
4.0
1.0
6.0
1.0
5.0
tPLH tPHL
tpzH tpzL
Propagation Delay
3.0
StoZn
2.5
Output Enable Time
2.0
2.5
7.5
3.0
9.5
3.0
8.5
7.0
2.5
9.0
2.5
8.0
6.0
2.0
8.0
2.0
7.0
7.0
2.5
9.0
2.5
8.0
tpHz tpLz
Output Disable Time
2.0
2.0
6.0
1.5
7.0
2.0
7.0
6.0
2.0
8.5
2.0
7.0
Fig. Units No.
ns
2-3
ns
2-3
ns
2-5
4-214
eN n
~National
CD
U Semiconductor
54F/74F269
8-Bit Bidirectional Binary Counter
General Description
The 'F269 is a fully synchronous 8-stage up/down counter featuring a preset capability for programmable operation, carry lookahead for easy cascading and a U/D input to control the direction of counting. All state changes, whether in counting or parallel loading, are initiated by the rising edge of the clock.
Features
� Synchronous counting and loading � Built-in lookahead carry capability � Count frequency 100 MHz � Supply current 113 mA typ � 300 mil slimline package
Ordering Code: see section 5
Logic Symbols
PE Po P1 P2 P3 p4 P5 p6 P7
U/D
CEP
TC
CET
CP Oo 01 02 03 04 05 06 07
TL/F/9510-1 I E E E / I EC
crr
CEP CP
Po
Oo
P1
01
Pz
Oz
P3
03
P4
04
P5
05
P5
05
P7
07
TC
TL/F/9510-4
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
U/ii
Oo 01 02 4 03 5 04 GND 05 8 Os 9 07 10 CP 11 CEP 12
24 Pf
23 Po . 22 P1
21 Pz 20 P3 19 Vee 18 P4 17 P5 16 P5 15 P7
14 TC
13 crr
Pin Assignment for LCC
02 01 Oo NCU/DPE Po
(j] Ii]] III !ID lil I]] [[I
03 llll
04 IJ]
GND IITJ
NC~
05 [j]] 05 [Z] 07 [ID
!IIP1 [l] P2
rn P3
ill NC
WI Yee
ill! P4
@P5
@J@~~gH.~~
CP CEPCIT NC TC P7 P5
TL/F/9510-3
TL/F/9510-2
Function Table
PE CEP CET U/D CP
Function
L
x
x
x _ / Parallel Load All
Flip-Flops
H H x x _/ Hold
H x
H
x _/ Hold (TC Held HIGH)
H L
L
H _/ Count Up
H L
L
L _/ Count Down
H = HIGH Vol1age Level L = LOW Voltage Level
X = Immaterial _,r = Transition LOW-to-HIGH
4-215
Unit Loading/Fan Out: See Section 2 for U.L. Definitions
Pin Names
Po-P7 PE U/D CEP CET CP TC Oo-07
Description
Parallel Data Inputs Parallel Enable Input (Active LOW) Up-Down Count Control Input Count Enable Parallel Input (Active LOW) Count Enable Trickle Input (Active LOW) Clock Input Terminal Count Output (Active LOW) Flip-Flop Outputs
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loHlloL
1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 5.0/33.3 50/33.3
20 �A/ - 0.6 mA 20 �Al - 0.6 mA 20 �A/-0.6 mA 20 �A/-0.6 mA 20 �Al - 0.6 mA 20 �A/ - 0.6 mA -1 mA/20 mA -1 mA/20mA
Logic Diagram
CP
U/D
Po
... 9
P1
... 9
P2
... 9
P3
... 9
P4
... 9
P5
... 9
Pa
... 9
P7
9 TC
...I
CLK
U D
o,
A1
CLK
U D
A2
02
CLK
U D
A3
03
CLK
UD
A4
o.
CLK
UD
As
05
CLK
UD
As
Os
CLK
U D
A1
07
4-216
TL/F/9510-6
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for avallablllty and specifications.
Storage Temperature
-65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 12s0 c
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to + 7.0V
Input Voltage (Note 2)
-0.5V to+ 7.0V
Input Current (Note 2)
- 30 mA to + 5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5V to Vee -0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
eN n
Recommended Operating
U)
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 12s0 c 0�Cto +70�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
V1H
Input HIGH Voltage
V1L
Input LOW Voltage
Veo
Input Clamp Diode Voltage
54F/74F Min Typ Max
Units Vee
Conditions
2.0
v
Recognized as a HIGH Signal
0.8
v
Recognized as a LOW Signal
-1.2
v
Min l1N = -18 mA
VoH
Output HIGH
Voltage
54F 10% Vee 2.5
74F 10% Vee 2.5
74F5% Vee
2.7
loH = -1 mA
v
Min loH = -1 mA
loH = -1 mA
VoL
Output LOW
Voltage
54F 10% Vee 74F 10% Vee
0.5 0.5
v
Min loL = 20 mA
loL = 20mA
l1H
Input HIGH Current 54F
74F
20.0
�A
Max V1N = 2.7V
5.0
lsv1
Input HIGH Current 54F
Breakdown Test
74F
100 7.0
�A
Max V1N = 7.0V
leEx
Output HIGH
54F
Leakage Current
74F
250 50
�A
Max Vour =Vee
V10
Input Leakage Test 74F
4.75
v
110 = 1.9 �A, 0.0
All Other Pins Grounded
loo
Output Leakage 74F
Circuit Current
3.75
�A
0.0
V100 = 150mV All Other Pins Grounded
l1L
Input LOW Current
las
Output Short-Circuit Current
-0.6 mA Max V1N = 0.5V
-60
-150 mA Max Vour = ov
leeH
Power Supply Current
104 125
mA Max Vo= HIGH
leeL
Power Supply Current
113 135
mA Max Vo= LOW
4-217
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
fmax
lPLH tPHL
tPLH tPHL
tPLH lPHL
lPLH lPHL
lPLH tPHL
lPLH tPHL
Maximum Clock Frequency
Propagation Delay CP to On (Count-Up)
Propagation Delay U/D to TC
Propagation Delay CETtoTC
Propagation Delay CPtoTC
Propagation Delay CP to an (Count-Down)
Propagation Delay CP to On (Load)
74F
TA= +25�C Vee= +5.0V
CL= 50 pf
Min
Typ
Max
100
3.5
8.0
4.5
10.5
3.5
9.5
4.5
9.5
3.5
9.0
3.0
10.5
4.5
10.0
5.0
10.0
3.5
10.5
4.5
10.5
3.5
9.0
4.0
9.0
54F
TA, Vee= Mil CL= 50 pf
Min
Max
74F
TA, Vee= Com CL= 50 pf
Min
Max
85
3.5
9.0
4.5
11.0
3.5
10.0
4.5
11.0
3.5
10.5
3.0
11.5
4.5
10.5
4.5
10.5
3.5
11.0
4.5
11.0
3.5
10.0
4.0
9.0
Fig. Units No.
MHz 2-1 ns 2-3 ns 2-3 ns 2-3 ns 2-3 ns 2-3 ns 2-3
AC Operating Requirements: See Section 2 for Waveforms
Symbol
Parameter
t5 (H) t5 (L)
th(H) th(L)
t5 (H) t5 (L)
th(H) th(L)
t5 (H) t5 (L)
th(H) th(L)
tw(H) tw(L)
t5 (H) t5 (L)
th(H) th(L)
Setup Time, HIGH or LOW Data toCP Hold Time, HIGH or LOW Data toCP Setup Time, HIGH or LOW PEtoCP Hold Time, HIGH or LOW PEtoCP Setup Time, HIGH or LOW CET or CEP to CP Hold Time, HIGH or LOW GET or CEP to CP Clock Pulse Width, HIGH or LOW
Setup Time, HIGH or LOW U/Dto CP Hold Time, HIGH or LOW U/D to CP
74F
TA= +25�c Vee= +s.ov
Min
Max
3.5 3.0
1.0 1.0
5.5 5.5
0 0
6.0 8.0
0 0
3.5 3.5
8.0 6.0
0.0 0.0
54F
TA, Vee= Mil
Min
Max
74F
TA, Vee= Com
Min
Max
4.0 3.0
2.0 1.0
6.5 6.5
0 0
6.5 9.0
0 0
3.5 4.0
9.5 7.0
0.0 0.0
Fig. Units No.
ns 2-6
ns 2-6
ns 2-6 ns 2-4 ns 2-6 ns 2-6
4-218
~National
~Semiconductor
54F/74F273 Octal D Flip-Flop
General Description
The 'F273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output.
All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements.
Features
� Ideal buffer for MOS microprocessor or memory � Eight edge-triggered D flip-flops � Buffered common clock � Buffered, asynchronous Master Reset � See 'F377 for clock enable version � See 'F373 for transparent latch version � See 'F374 for TRI-STATE� version � Guaranteed 4000V minimum ESD protection
Ordering Code: see section 5 Logic Symbols
Connection Diagrams
ep t.tR
TL/F/9511-3
IEEE/I EC
iiR
ep
Do
Oo
o,
o,
D2
02
D3
03
o,
04
05
05
Ds
Os
07
07
TL/F/9511-5
Pin Assignment for DIP, SOIC and Flatpak
MR 1 Oo 2 Do 3
o, 4
o, 5
02
02 03 8
03
GND 10
20 Vee 19 07 18 07 17 Ds 16 Os 15 05 14 D5 13 04 12 04 11 eP
TL/F/9511-1
Pin Assignment for LCC
[0[3)
mD:z m02 ron,
o,
m
03 []]
GND [QI CP Ii]
04 li1J
D4 Ii]]
moo II!Oo ITl iiR
@!Vee
11]]07
fG.I ~(j]J [l]li�]
Ds 05 Os Ds DJ
TL/f/9511-2
4-219
Unit Loading/Fan Out: See section 2 tor U.L. definitions
54F/74F
Pin Names
Description
U.L.
Input l1Hll1L
HIGH/LOW Output loHllOL
Do-D7 MR CP Oo-07
Data Inputs Master Reset (Active LOW) Clock Pulse Input (Active Rising Edge) Data Outputs
1.0/1.0 1.0/1.0 1.0/1.0 50/33.3
20 �A/-0.6 mA 20 �A/ -0.6 mA 20 �Al -0.6 mA -1 mA/20 mA
Mode Select-Function Table
Operating Mode
Reset (Clear) Load '1' Load 'O'
Inputs
MR
CP
Dn
L xx
H
_/
h
H
_/
I
Logic Diagram
Output On L H L
H = HIGH Voltage Level steady state h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock
transition
L = LOW Voltage Level steady state I = LOW Voltage Level one setup time prior to the LOW-to-HIGH clock
transition
X = Immaterial .../ = LOW-to-HIGH clock transition
CP
07 TL/F /9511-4 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-220
Absolute Maximum Ratings (Note 1)
If MiiitaryI Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
-55�C to+ 175�C
Vee Pin Potential to Ground Pin
-0.5V to + 7.0V
Input Voltage (Note 2)
-0.5V to+ 7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
-0.5VtoVee -0.5V to+ 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
ESD Last Passing Voltage (min)
4000V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol V1H V1L Veo VoH
VoL
l1H lsv1 leEX V10 loo l1L las leeH leeL
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
Mil 10% Vee 5% Vee
Output LOW Voltage
Mil 10% Vee 5%Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage 74F
Test
Output Leakage 74F
Circuit Current
Input LOW Current
Output Short-Circuit Current
Power Supply Current
54F/74F
Min Typ
Max
2.0
0.8
-1.2
2.5 2.5 2.7
0.5 0.5 0.5
20.0 5.0
100 7.0
250 50
4.75
-60
3.75
-0.6 -150
44 56
Units
v v v v
v
�A �A �A
v
�A mA mA mA
Vee
Min Min
Min Max Max Max 0.0 0.0 Max Max Max
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal l1N = -18 mA loH = -1 mA
loL = 20 mA
V1N = 2.7V
V1N = 7.0V
VouT =Vee
110 = 1.9 �A All other pins grounded V100 = 150 mV All other pins grounded V1N = 0.5V
VouT = ov
CP=_/ Dn =MR= HIGH
4-221
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
fmax
tPLH tpHL
tPLH tPHL
Maximum Clock Frequency
Propagation Delay Clock to Output
Propagation Delay MR to Output
74F
TA= +25�C Vee= +5.0V
CL= 50 pf
Min
Typ
Max
160.
3.0
7.0
4.0
9.00
4.5
9.5
54F
TA, Vee= Mii CL= 50pF
Min
Max
9.5
2.5
9.5
3.0
11.0
3.0
11.0
74F
TA, Vee= Com CL= 50 pf
Min
Max
130
2.5
7.5
3.5
9.0
4.0
10.0
Fig. Units No.
MHz 2-1 ns 2-4 ns 2-4
AC Operating Requirements: See Section 2 for Waveforms
Symbol
Parameter
t5(H) t5(L) th(H) th(L)
tw(L)
tw(H) tw(L)
tree
Setup Time, HIGH or LOW Data to CP
Hold Time, HIGH or LOW Data to GP
MR Pulse Width, LOW
CP Pulse Width HIGH or LOW
Recovery Time, MR to CP
74F
TA= +25�c Vee= +5.0V
Min
Max
3.0 3.5
0.5 1.0
6.0
6.0 6.0
3.0
54F
TA, Vee= Mii
Min
Max
3.5 4.0
1.0 1.0
4.0
5.0 5.0
4.5
74F
TA, Vee= Com
Min
Max
3.0 3.5
0.5 1.0
6.0
6.0 6.0
3.5
Units
Fig. No.
ns
2-6
ns
2-4
ns
2-4
ns
2-4
4-222
N
C>
~National
0
~Semiconductor
54F/74F280
9-Bit Parity Generator/Checker
General Description
The 'F280 is a high-speed parity generator/checker that accepts nine bits of input data and detects whether an even or an odd number of these inputs is HIGH. If an even number of inputs is HIGH, the Sum Even output is HIGH. If an odd number is HIGH, the Sum Even output is LOW. The Sum Odd output is the complement of the Sum Even output.
Features
� Guaranteed 4000V minimum ESD protection
Ordering Code: see section 5 Logic Symbols
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
TL/F/9512-3
15 17 2 NC 3 la 4 l:E 5 l:o 6 GND 7
I E E E / I EC
2k lo
11
12
13
l:E
14
15
l:o
15
17
la
TL/F/9512-5
14 Yee 13 15 12 14 11 13 10 12 9 1,
a 10
TL/F/9512.:.1
Unit Loading/Fan Out: see Section 2 for U.L. Definitions
Pin Names
lo-la lo le
Description
Data Inputs Odd Parity Output Even Parity Output
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loHlloL
1.0/1.0 50/33.3 50/33.3
20 �A/-0.6 mA -1 mA/20 mA -1 mA/20 mA
Pin Assignment for LCC
~NClaNCNC
[fil[I][]][[]!IJ
l:o []] GND [Q]
NC [i]
lo li1l
1, II]
illl7 [1)15 O]NC
@!Vee
!Im 15
[g]~li]ll1J[j]]
'2 NC 13 NC 14
TL/F/9512-2
a
4-223
c0 o
"' Truth Table Logic Diagram
Number of HIGH Inputs
lo-ls
0,2,4,6,8 1,3,5, 7,9
H = HIGH Voltage Level L = LOW Voltage Level
Outputs
~Even
~Odd
H
L
L
H
TL/F/9512-4
be Please note that this diagram is provided only for the understanding of logic operations and should not used to estimate propagation delays.
4-224
Absolute Maximum Ratings (Note 1)
If Miiitary/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
-65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
-55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5Vto +7.0V
Input Voltage (Note 2)
-0.5V to+ 7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5VtoVee - 0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
ESD Last Passing Voltage (Min)
4000V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
I\)
()0
Recommended Operating
c
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +70�C
Supply Voltage Military Commercial
+4.5V to + 5.5V +4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
V1H
Input HIGH Voltage
V1L
Input LOW Voltage
Veo
Input Clamp Diode Voltage
54F/74F Min Typ Max
Units Vee
Conditions
2.0
v
Recognized as a HIGH Signal
0.8
v
Recognized as a LOW Signal
-1.2
v
Min l1N = -18 mA
VoH
Output HIGH
Voltage
54F 10% Vee 2.5
74F 10% Vee 2.5
74F5% Vee
2.7
loH = -1 mA
v
Min loH = -1 mA
loH = -1 mA
VoL
Output LOW
Voltage
54F 10% Vee 74F 10% Vee
0.5
v
loL = 20mA Min
0.5
loL = 20mA
l1H
Input HIGH Current 54F
74F
20.0
�A
Max V1N = 2.7V
5.0
lsv1
Input HIGH Current 54F
Breakdown Test
74F
100
�A
Max V1N = 7.0V
7.0
leEX
Output HIGH
54F
Leakage Current
74F
250
�A
Max VouT =Vee
50
V10
Input Leakage Test 74F
4.75
v
llD = 1.9 �A 0.0 All Other Pins Grounded
loo
Output Leakage 74F
Circuit Current
3.75
�A
0.0
V100 = 150 mV All Other Pins Grounded
l1L
Input LOW Current
los
Output Short-Circuit Current
-0.6
mA
Max V1N = 0.5V
-60
ov -150 mA Max VouT =
leeH
Power Supply Current
25
38
mA Max Vo= HIGH
a
4-225
0co
N AC Electrical Characteristics: See Section 2 tor Waveforms and Load Configurations
Symbol
Parameter
lPLH tPHL
tPLH tPHL
Propagation Delay In to ~E
Propagation Delay In to ~o
74F
TA= +25�c Vee= +5.0V
CL= 50 pF
Min
Typ
Max
6.5
10.0
15.0
6.5
11.0
16.0
6.0
10.0
15.0
6.5
11.0
16.0
54F
TA, Vee= Mil CL= 50pF
Min
Max
6.5
20.0
6.5
21.0
6.0
20.0
6.5
21.0
74F
TA, Vee= Com CL= 50 pF
Min
Max
6.5
16.0
6.5
17.0
6.0
16.0
6.5
17.0
Units
Fig. No.
ns
2-3
� ns
2-3
4-226
~~SNemaitcoinoduncatolr
54F/74F283 4-Bit Binary Full Adder with Fast Carry
General Description
The 'F283 high-speed 4-bit binary full adder with internal
carry lookahead accepts two 4-bit binary words (A0-A3, 80-83) and a Carry input (Co). It generates the binary Sum outputs (S0-S3) and the Carry output (C4) from the most significant bit. The 'F283 will operate with either active HIGH or active LOW operands (positive or negative logic).
Features
� Guaranteed 4000V minimum ESD protection
Ordering Code: see section 5 Logic Symbols
TL/F/9513-1
IEEE/I EC
l:
Ao
A1 A2 A3
Bo B1 B2
J
}
{
So
s,
S2
S3
B3
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
s, B1 A1 3 So 4 Ao Bo Co GND
16 Vee 15 B2 14 A2 13 S2 12 A3 11 B3 10 S3 9 C4
TL/F/9513-2
Pin Assignment forLCC
Bo Ao NC So A1
[[] [[] [[] [Kl 111
~rnorn�, GND [QI
[I] s1
NC [i]
[I]NC
C4 !i11
!ill Vee
S3 ff]
[j]] B2
Ii] @] [�I Ii] [�]
B3 A3 NC 5i Ai
TL/F/9513-3
Co
Cl
co C4
TL/F/9513-4
Unit Loading/Fan Out: See Section 2 for U.L. Definitions
Pin Names
Ao-A3 80-83 Co So-S3 C4
Description
A Operand Inputs B Operand Inputs Carry Input Sum Outputs Carry Output
54F/74F
U.L. HIGH/LOW
Input l1H/l1L Output loHlloL
1.0/2.0 1.0/2.0 1.0/1.0 50/33.3 50/33.3
20 �A/-1.2 mA 20 �A/ -1.2 mA 20 �A/ - 0.6 mA -1 mA/20mA -1 mA/20 mA
4-227
Functional Description
The 'F283 adds two 4-bit binary words (A plus B) plus the incoming Carry (C0). The binary sum appears on the Sum (So-S3) and outgoing carry (C4) outputs. The binary weight of the various inputs and outputs is indicated by the subscript numbers, representing powers of two.
20(Ao +Bo+ Co)+ 21 (A1 + B1) + 22 (A2 + B2) + 23 (A3 + B3)
= So + 2S1 + 4S2 + 8S3 + 16C4
Where ( +) = plus
Interchanging inputs of equal weight does not affect the operation. Thus Co, Ao, Bo can be arbitrarily assigned to pins 5, 6 and 7 for DIPS, and 7, 8 and 9 for chip carrier packages. Due to the symmetry of the binary add function, the 'F283 can be used either with all inputs and outputs active HIGH (positive logic) or with all inputs and outputs active LOW (negative logic). See Figure 1. Note that if Co is not used it must be tied LOW for active HIGH logic or tied HIGH for active LOW logic.
Due to pin limitations, the intermediate carries of the 'F283 are not brought out for use as inputs or outputs. However,
other means can be used to effectively insert a carry into, or bring a carry out from, an intermediate stage. Figure 2
shows how to make a 3-bit adder. Tying the operand inputs of the fourth adder (A3, B3) LOW makes S3 dependent only on, and equal to, the carry from the third adder. Using somewhat the same principle, Figure 3 shows a way of dividing the 'F283 into a 2-bit and a 1-bit adder. The third stage
adder (A2, B2, S2) is used merely as a means of getting a carry (C10) signal into the fourth stage (via A2 and B2) and bringing out the carry from the second stage on S2. Note that as long as A2 and B2 are the same, whether HIGH or LOW, they do not influence S2. Similarly, when A2 and B2 are the same the carry into the third stage does not influence the carry out of the third stage. Figure 4 shows a method of implementing a 5-input encoder, where the inputs are
equally weighted. The outputs So, S1 and S2 present a binary number equal to the number of inputs 11-ls that are true. Figure 5 shows one method of implementing a 5-input majority gate. When three or more of the inputs I1-ls are true, the output Ms is true.
Co Ao A1 A2 A3 Bo 81 82 83 So 51 52 53 C4
Logic Levels L L H L H H L L H H H L L H
Active HIGH 0 0 1 0 1 1 0 0 1 1 1 0 0 1 Active LOW 1 1 0 1 0 0 1 1 0 0 0 1 1 0
Active HIGH: 0 + 10 + 9 = 3 + 16 Active LOW: 1 + 5 + 6 = 12 + 0 FIGURE 1. Active HIGH versus Active LOW Interpretation
Ao Bo A1 B1 A2 B2 A3 B3
Co
C4
So
S1
S2
S3
FIGURE 2. 3-Bit Adder
C3 TL/F/9513-5
Ao Bo A1 B1
C10 A10 B10
Co
Co
Ao Bo A1 B1
So
S1
I
'
'
'
A2 B2
'
'
' ' '
S2
'
' I
A3 B3 S3
C4
C11
So S1
C2 S10
TL/F/9513-6
FIGURE 3. 2�Bit and 1�Blt Adders
11 12
13 14 15
Ao Bo A1 B1 A2 B2 A3 B3
Co
C4
So
S1
S2
S3
20
21
22
FIGURE 4. 5-lnput Encoder
TL/F/9513-7
11 12
13 14 15
Ao Bo A1 B1 A2 B2 A3 B3
Co
C4
So
S1
S2
S3
TL/F/9513-8
FIGURE 5. 5-lnput Majority Gate
4-228
Logic Diagram
Ol
I
""O''l
U:
~
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-229
Absolute Maximum Ratings (Note 1>
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5Vto +7.0V
Input Voltage (Note 2)
-0.5V to+ 7.0V
Input Current (Note 2)
-30 mA to + 5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5VtoVee -0.5V to +5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
ESD Last Passing Voltage (Min)
4000V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol VrH VrL Veo VoH
Vol l1H lsvr ICEX Vro loo lrL los lceH lceL
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 74F 10% Vee 74F5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH Current 54F 74F
Input HIGH Current 54F
Breakdown Test
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage Test 74F
Output Leakage 74F
Circuit Current Input LOW Current
Output Short-Circuit Current Power Supply Current Power Supply Current
54F/74F Min Typ Max 2.0
0.8 -1.2 2.5 2.5 2.7 0.5 0.5 20.0 5.0 100 7.0 250
50
4.75
3.75
-0.6 -1.2
-60
-150
36
55
36
55
Units
v v v v
v
�A
�A
�A
v
�A
mA mA mA mA
Vee
Conditions
Min Min Min Max
Recognized as a HIGH Signal Recognized as a LOW Signal lrN = -18 mA loH = -1 mA loH = -1 mA loH = -1 mA loL = 20 mA loL = 20 mA VrN = 2.7V
Max VrN = 7.0V
Max VouT =Vee
lro = 1.9 �A
0.0
All Other Pins Grounded
Vroo = 150 mV
0.0
All Other Pins Grounded
VrN = 0.5V (Co) Max
VrN = 0.5V (An. Bn)
Max Vour = ov
Max Vo= HIGH
Max Vo= LOW
4-230
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
tPLH
Propagation Delay
tPHL
Co to Sn
tPLH
Propagation Delay
tPHL
An or Bn to Sn
tPLH
Propagation Delay
tPHL
Co to C4
tPLH
Propagation Delay
tPHL
An or Bn to C4
74F
TA= +25�C Vee= +5.0V
CL= 50 pF
Min
Typ
Max
3.5
7.0
9.5
3.0
7.0
9.5
3.0
7.0
9.5
3.0
7.0
9.5
3.0
5.7
7.5
3.0
5.4
7.0
3.0
5.7
7.5
2.5
5.3
7.0
54F
TA, Vee= Mil CL= 50 pF
Min
Max
3.5
14.0
3.0
14.0
3.0
17.0
3.0
14.0
3.0
10.5
2.5
10.0
3.0
10.5
2.5
10.0
74F
TA, Vee= Com CL= 50 pF
Min
Max
3.5
11.0
3.0
11.0
3.0
13.0
3.0
11.5
3.0
8.5
3.0
8.0
3.0
8.5
2.5
8.0
Units Fig. No.
ns 2-3
ns 2-3
ns 2-3
ns
2-3
4-231
O>
O>
N
'DWA
National
Semiconductor
54F/74F299 Octal Universal Shift/Storage Register with Common Parallel 1/0 Pins
General Description
The 'F299 is an 8-bit universal shift/storage register with TRI-STATE� outputs. Four modes of operation are possible: hold (store), shift left, shift right and load data. The parallel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins. Additional outputs, 0 0-07, are provided to allow easy serial cascading. A separate active LOW Master Reset is used to reset the register.
Features
� Common parallel 1/0 for reduced pin count � Additional serial inputs and outputs for expansion � Four operating modes: shift left, shift right, load and
store � TRI-STATE outputs for bus-oriented applications � Guaranteed 4000V minimum ESD protection
Ordering Code: see section 5 Logic Symbols
a,
MR Oo l/Oo 1/01 I/Oz 1/03 1/0' I/Os 1/06 1/07 TL/F/9515-1
IEEE/I EC SRGB 3EN13
Oo t> ZS t> ZS
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
So 1
or, 2
OE2 3 I/Os 4 1/04 5 1/02 6 l/Oo 7
Oo 8
MR
GND 10
20 Vee
19 s,
18 DS7 17 07 16 1/07 15 I/Os 14 1/03 13 1/01 12 CP 11 DS0
TL/F/9515-2
Pin Assignment for LCC
O[o]]1/m001r/n021rn/04r1n/06
MR[[]
GND Ii]] DSo [Ii] CP ff1]
1/01 llll
mrnoorr,2
DJ So
WlVee llfils,
IGI ~ Ii]) liZJ l@l
1/03 l/Osl/~ ~OS,
TL/F/9515-3
TL/F/9515-4
4-232
Unit Loading/Fan Out: See Section 2 for U.L. definitions
Pin Names
CP DSo DS7 So. S1 MR OE1. OE2 l/Oo-1/07
Oo,07
Description
Clock Pulse Input (Active Rising Edge) Serial Data Input for Right Shift Serial Data Input for Left Shift Mode Select Inputs Asynchronous Master Reset Input (Active LOW) TRI-STATE Output Enable Inputs (Active LOW) Parallel Data Inputs or TRI-STATE Parallel Outputs Serial Outputs
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loH/loL
1.0/1.0 1.0/1.0 1.0/1.0 1.0/2.0 1.0/1.0 1.0/1.0 3.5/1.083 150/40(33.3) 50/33.3
20 �A/-0.6 mA 20 �A/-0.6 mA 20 �A/-0.6 mA 20 �A/-1.2 mA 20 �A/-0.6 mA 20 �A/ - 0.6 mA 70 �Al - 0.65 mA -3 mA/24 mA (20 mA) -1 mA/20mA
Functional Description
The 'F299 contains eight edge-triggered D-type flip-flops and the interstage logic necessary to perform synchronous shift left, shift right, parallel load and hold operations. The type of operation is determined by So and S1, as shown in the Mode Select Table. All flip-flop outputs are brought out through TRI-STATE buffers to separate 1/0 pins that also serve as data inputs in the parallel load mode. 0 0 and 07 are also brought out on other pins for expansion in serial shifting of longer words.
A LOW signal on MR overrides the Select and CP inputs and resets the flip-flops. All other state changes are initiated by the rising edge of the clock. Inputs can change when the clock is in either state provided only that the recommended setup and hold times, relative to the rising edge of CP, are observed.
A HIGH signal on either OE1 or OE2 disables the TRISTATE buffers and puts the 1/0 pins in the high impedance state. In this condition the shift, hold, load and reset operations can still occur. The TRI-STATE outputs are also dis-
abled by HIGH signals on both So and S1 in preparation for a parallel load operation.
Mode Select Table
Inputs
Response
MR S1 So CP
L x x x Asynchronous Reset; 0 0-07 = LOW
H H H _ / Parallel Load; I/On ~ On
H L H _ / Shift Right; DSo ~ Oo. Oo ~ 01, etc.
H H L _ / Shift Left; DS7 ~ 07, 07 ~ 05, etc.
x H L L
Hold
H = HIGH Voltage Level
L = LOW Voltage Level X = Immaterial _r = LOW-to-HIGH Clock Transition
4-233
O> O>
"' Logic Diagram
TL/F/9515-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-234
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5Vto +7.0V
Input Voltage (Note 2)
-0.5V to + 7.0V
Input Current (Note 2)
-30 mA to + 5.0 mA
ESD Last Passing Voltage (Min)
4000V
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under
these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
N CD CD
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
Current Applied to Output in LOW State (Max)
-0.5V to Vee -0.5V to + 5.5V
twice the rated loL (mA)
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
V1H V1L Veo VoH
VoL
l1H lsv1 lsvir leEX V10 loo l1L l1H+ lozH l1L + lozL las lzz leeH leeL leez
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee 74F 5% Vee 74F 5% Vee
Output LOW Voltage
5410% Vee 7410% Vee 7410% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Input HIGH Current 54F Breakdown Test (1/0) 74F
Output HIGH
54F
Leakage Current
74F
Input Leakage Test
74F
Output Leakage Circuit Current
74F
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current
54F/74F
Min Typ Max
2.0
0.8
-1.2
2.5 2.4 2.5 2.4 2.7 2.7
0.5 0.5 0.5
20.0 5.0
100 7.0
1.0 0.5
250 50
4.75
3.75
-0.6 -1.2
70
-650
-60
-150
500
68 95
68 95
68 95
Units
v v v
v
v
�A �A mA �A
v
�A mA �A �A mA �A mA mA mA
Vee
Min
Min
Min Max Max Max Max 0.0 0.0 Max Max Max Max
o.ov
Max Max Max
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal l1N = -18 mA loH = -1 mA (Oo, 07, I/On) loH = -3 mA (I/On) loH = -1 mA (Oo. 07, I/On) loH = -3 mA (I/On) loH = -1 mA (Oo, 07, I/On) loH = -3 mA (I/On) IOL = 20 mA loL = 20 mA (Oo, 07) loL = 24 mA (I/On) V1N = 2.7V (CP, DSo, DS7, So. S1.
MR, OE1, OE2) V1N = 7.0V (CP, DSo. DS7, So. S1'
MR, OE1, OE2) V1N = 5.5V (I/On)
VouT =Vee
110 = 1.9 �A All Other Pins Grounded V100 = 150 mV All Other Pins Grounded V1N = 0.5V (CP, DSo, DS7, MR, OE1, OE2) V1N = 0.5V (So, S1) V110 = 2.7V (I/On)
V110 = 0.5V (I/On)
VouT = ov
VouT = 5.25V Vo= HIGH Vo= LOW Vo= HIGHZ
4-235
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
fmax lPLH tPHL lPLH lPHL lPHL
lPHL
tpzH tpzL tpHz tpLz tpzH tpzL tpHz tpLZ
Maximum Input Frequency
Propagation Delay CPtoOoorQ7 Propagation Delay CPto I/On
Propagation Delay MR to Oo orQ7
Propagation Delay MR to I/On
Output Enable Time OE to I/On
Output Disable Time OE to I/On
Output Enable Time Sn to I/On
Output Disable Time Sn to I/On
74F
TA= +25�C Vee= +5.0V
CL= 50 pF
Min
Typ
Max
70
100
4.0
7.0
8.0
4.5
6.5
8.0
3.5
7.0
9.0
4.0
8.5
9.0
5.5
7.5
9.5
5.5
11.0
10.0
3.5
6.0
8.0
4.0
7.0
10.0
2.0
4.5
6.0
1.0
4.0
5.5
3.5
9.0
4.0
10.0
2.5
6.0
1.5
5.5
54F
TA, Vee= Mil CL= 50pF
Min
Max
74F
TA, Vee= Com CL= 50 pF
Min
Max
70
4.0
8.5
4.5
8.5
3.5
10.0
4.0
10.0
5.5
10.5
5.5
10.5
3.5
9.0
4.0
11.0
2.0
7.0
1.0
6.5
3.5
10.0
4.0
11.0
2.5
7.0
1.5
6.5
Fig. Units No. MHz 2-1
ns 2-3
ns 2-3
ns 2-5 ns 2-5 ns 2-5
AC Operating Requirements: See Section 2 for Waveforms
Symbol
Parameter
t5 (H) t5 (L) th(H) th(L)
t5 (H) t5(L) th(H) th(L)
tw(H) tw(L)
tw(L)
tree
Setup Time, HIGH or LOW So orS1 toCP Hold Time, HIGH or LOW So or S1 to CP Setup Time, HIGH or LOW I/On, DSo or DS7 to CP
Hold Time, HIGH or LOW I/On. DSo or DS7 to CP
CP Pulse Width HIGH or LOW
MR Pulse Width, LOW
Recovery Time, MR to CP
74F
TA= +25�C Vee= +5.0V
Min
Max
8.5 8.5
0 0
5.0 5.0
2.0 2.0
5.0 5.0
5.0
7.0
54F
TA, Vee= Mil
Min
Max
74F
TA, Vee= Com
Min
Max
8.5 8.5
0 0
5.0 5.0
2.0 2.0
5.0 5.0
5.0
7.0
Fig. Units
No.
ns
2-6
ns
2-6
ns
2-4
ns
2-4
ns
2-6
4-236
~~SNemaitcoinoduncatolr
54F/74F322
Octal Serial/Parallel Register with Sign Extend
General Description
The 'F322 is an 8-bit shift register with provision for either serial or parallel loading and with TRI-STATE� parallel outputs plus a bi-state serial output. Parallel data inputs and parallel outputs are multiplexed to minimize pin count. State changes are initiated by the rising edge of ttie clock. Four synchronous modes of operation are possible: hold (store), shift right with serial entry, shift right with sign extend and parallel load. An asynchronous Master Reset (MR) input overrides clocked operation and clears the register.
Features
� Multiplexed parallel 1/0 ports � Separate serial input and output � Sign extend function � TRI-STATE outputs for bus applications
Ordering Code: see sections Logic Symbols
RE
S/P
SE CP OE
Mii 0� RE S/P
CP
TL/F/9516-3
IEEE/I EC
SRG8
t>
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
Rf 1
S/P
Do 1/07 4 1/05 5 1/03 1/01
i5E 8
i;iR 9 GND 10
20 Vee
19 s 18 SE
17 D1 16 1/06 15 1/04 14 I/Oz 13 l/Oo 12 Oo 11 CP
TL/F/9516-1
Pin Assignment
. morn~ for LCC vo 0�rn1/m011m/03rnm5 l/o,
GND [QI
ms/P
CP[i]
[I]RE
Oollll l/Oo I!]
lfilYcc II2JS
lj])@fil)li][fil
I/Oz 1/041/06 01SE
TL/F/9516-2
27
t>
ZS
t> Z14
Oo TL/F/9516-5
4-237
Unit Loading/Fan Out: See Section 2 for U.L. definitions
54F/74F
Pin Names
Description
U.L. HIGH/LOW
Input l1Hll1L Output loHllOL
RE SIP SE
s
Do,D1 CP MR OE
Oo l/Oo-1/07
Register Enable Input (Active LOW) Serial (HIGH) or Parallel (LOW) Mode Control Input Sign Extend Input (Active LOW) Serial Data Select Input Serial Data Inputs Clock Pulse Input (Active Rising Edge) Asynchronous Master Reset Input (Active LOW) TRI-STATE Output Enable Input (Active LOW) Bi-State Serial Output Multiplexed Parallel Data Inputs or TRI-STATE Parallel Data Outputs
1.0/1.0 1.0/1.0 1.0/3.0 1.0/2.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 50/33.3 3.5/1.083 150/40 (33.3)
20 �A/-0.6 mA 20 �A/-0.6 mA 20 �A/-1.8 mA 20 �A/-1.2 mA 20 �A/ -0.6 mA 20 �A/ -0.6 mA 20 �A/ -0.6 mA 20 �A/ - 0.6 mA -1 mA/-20 mA 70 �A/-0.65 mA - 3 mA/24 mA (20 mA)
Functional Description
The 'F322 contains eight D-type edge triggered flip-flops and the interstage gating required to perform right shift and the intrastage gating necessary for hold and synchronous parallel load operations. A LOW signal on RE enables shifting or parallel loading, while a HIGH signal enables the hold mode. A HIGH signal on S/P enables shift right, while a LOW signal disables the TRI-STATE output buffers and enables parallel loading. In the shift right mode a HIGH signal
on SE enables serial entry from either Do or D1, as determined by the S input. A LOW signal on SE enables shift right but 0 7 reloads its contents, thus performing the sign extend function required for the 'F384 Twos Complement Multiplier. A HIGH signal on OE disables the TRI-STATE output buffers, regardless of the other control inputs. In this condition the shifting and loading operations can still be performed.
Mode Select Table
Mode
Inputs
Outputs Oo
s MR RE S/P SE
OE* CP 1/07 1/05 I/Os 1/04 1/03 1102 1101 l/Oo
Clear
L x x xx L x L
L
L
L
L
L
L
L
L
L x x xx H x z z z z z z z z L
Parallel H
Load
L
L
x x x _/ 17
la
Is
14
13
12
11
lo
lo
Shift Right
H
L
H
H L
L
_/
Do
07
Oa
05
04
03
02
01 01
H
L
H
H H
L
_ / D1
07
Oa
05
04
03
02
01 01
Sign H
Extend
L
H
x L
L
_/ 07
07
Oa
05
04
03
02
01 01
Hold
H
H
x
x x L _/ NC NC
NC
NC NC NC NC NC NC
*When the OE input is HIGH all I/On terminals are at the high impedance state; sequential operation or clearing of the register is not affected.
Note 1: lrlo = The level of the steady-state input at the respective 1/0 terminal is loaded into the flip-flop while the flip.flop outputs (except Oo) are isolated from the 1/0 terminal.
Note 2: o0, 0 1 = The level of the steady-state inputs to the serial multiplexer input.
Note 3: OrOo = The level of the respective On flip-flop prior to the last Clock LOW-to-HIGH transition. H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance Output State ../ = LOW-to-HIGH Transition NC = No Change
4-238
Logic Diagram
RE S/P
CP MR OE
TL/F/9516-4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-239
Absolute Maximum Ratings (Note 1)
If Miiitary/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to + 7.0V
Input Voltage (Note 2)
-0.5V to+ 7.0V
Input Current (Note 2)
-30 mA to + 5.0 mA
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
Current Applied to Output in LOW State (Max)
-0.5VtoVcc -0.5V to + 5.5V
twice the rated loL (mA)
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol V1H V1L Vco VoH
VoL
l1H lsv1 lsv1r lcEX V10 loo l1L
l1H + lozH l1L + lozL los lzz Ice
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee 74F5% Vee 74F 5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Input HIGH Current 54F Breakdown Test (1/0) 74F
Output HIGH
54F
Leakage Current
74F
Input Leakage Test
74F
Output Leakage Circuit Current
74F
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current Bus Drainage Test Power Supply Current
54F/74F Min Typ Max
2.0
0.8
-1.2
2.5 2.4 2.5 2.4 2.7 2.7
0.5 0.5 0.5
20.0 5.0
100 7.0
1.0 0.5
250 50
4.75
3.75
-0.6 -1.2 -1.8
70
-650
-60 60
-150 500 90
Units
v v v
v
v
�A �A mA �A
v
�A mA mA mA �A �A mA �A mA
Vee
Min
Min
Min
Max Max Max Max 0.0 0.0 Max Max Max Max Max Max
o.ov
Max
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal l1N = -18 mA loH = -1 mA (Oo, I/On) loH = -3 mA (I/On) loH = :-1 mA (Oo, I/On) loH = -3 mA (I/On) loH = -1 mA (Oo. I/On) loH = -3 mA (I/On) loL = 20 mA (Oo, I/On) loL = 20 mA (Oo) loL = 24 mA (I/On) V1N = 2.7V
V1N = 7.0V (Non-1/0 Inputs)
V1N = 5.5V (I/On)
Vour =Vee
110 = 1.9 �A All Other Pins Grounded V100=�150 mV All Other Pins Grounded V1N = 0.5V (RE, S/P, Dn. CP, MR, OE) V1N = 0.5V (S) V1N = 0.5V (SE)
V110 = 2.7V (I/On)
V110 = 0.5V (I/On)
Vour = ov
Vour = 5.25V
4-240
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
fmax tPLH tPHL tPLH tPHL tPHL
tPHL
tpzH tpzL tpHz tpLz tpzH tpzL tpHz tpLz
Maximum Clock Frequency
Propagation Delay CPto I/On
Propagation Delay CPto00 Propagation Delay MR to I/On
Propagation Delay MRto00 Output Enable Time OE to I/On
Output Disable Time OE to I/On
Output Enable Time S/Pto I/On
Output Disable Time S/Pto I/On
74F
TA= +25�C Vee= +5.0V
CL= 50 pF
Min
Typ
Max
70
90
3.5
7.0
7.5
5.0
8.5
11.0
3.5
7.0
9.0
3.5
7.0
8.0
6.0
10.0
13.0
5.5
7.5
12.0
3.0
6.5
9.0
4.0
8.5
11.0
2.0
4.5
6.0
2.0
5.0
7.0
4.5
8.0
10.5
5.5
10.0
14.0
5.0
9.0
11.5
6.0
12.0
15.5
54F
TA, Vee= Mil CL= 50 pF
Min
Max
50
3.5
9.5
3.5
10.0
3.5
11.0
3.5
10.0
6.0
15.0
74F
TA, Vee= Com CL= 50 pF
Min
Max
70
3.5
8.5
5.0
12.0
3.5
10.0
3.5
9.0
6.0
14.0
5.5
14.0
5.5
13.0
3.0
12.5
3.0
10.0
4.0
14.5
4.0
12.0
2.0
8.0
2.0
7.0
2.0
10.0
2.0
8.0
4.5
13.5
4.5
11.5
5.5
17.0
5.5
15.0
5.0
16.5
5.0
12.5
6.0
19.5
6.0
16.5
Units Fig. No.
MHz 2-1 ns 2-3 ns 2-3 ns 2-3 ns 2-5
ns 2-5
AC Operating Requirements: See Section 2 for Waveforms
Symbol
Parameter
t5 (H) t5 (L)
th(H) th(L)
t5 (H) t5 (L)
th(H) th(L)
t5 (H) t5 (L)
th(H) th(L)
t5 (H) t5 (L) t5 (H) t5 (L)
th(H) th(L)
tw(H) tw(L)
tw(L)
tree
Setup Time, HIGH or LOW REtoCP
Hold Time, HIGH or LOW REtoCP Setup Time, HIGH or LOW Do, D1 or I/On to CP Hold Time, HIGH or LOW Do, D1 or I/On to CP Setup Time, HIGH or LOW SEtoCP Hold Time, HIGH or LOW SEtoCP Setup Time, HIGH or LOW S/Pto CP
Setup Time, HIGH or LOW StoCP Hold Time, HIGH or LOW SorS/Pto CP CP Pulse Width, HIGH or LOW
MR Pulse Width, LOW
Recovery Time MR to CP
74F
TA= +25�C Vee= +5.0V
Min
Max
6.0 14.0
0 0
6.5 6.5
2.0 2.0
7.0 2.5
2.0 0.0
11.0 13.5
6.5 9.0
0 0
7.0
5.5
8.0
54F
TA, Vee= Mil
Min
14.0 18.0
0 0
8.5 8.5
3.0 3.0
9.0 11.0
2.0 1.0
13.0 21.0
8.5 11.0
1.0 0
Max
8.0
7.5
12.0
4-241
74F
TA, Vee= Com
Min
Max
7.0 16.0
0 0
7.5 7.5
3.0 3.0
8.0 3.5
2.0 0.0
12.0 15.5
7.5 10.0
0 0
7.0
6.5
8.0
Units Fig. No.
ns
2-6
ns
2-6
ns 2-6
ns
2-6
ns 2-6
ns 2-6
ns 2-6
ns 2-6
ns 2-6
ns 2-4 2-4
ns 2-6
~National
~Semiconductor
54F/74F323 Octal Universal Shift/Storage Register with Synchronous Reset and Common 1/0 Pins
General Description
The 'F323 is an 8-bit universal shift/storage register with TRI-STATE� outputs. Its function is similar to the 'F299 with the exception of Synchronous Reset. Parallel load inputs and flip-flop outputs are multiplexed to minimize pin count. Separate serial inputs and outputs are provided for Oo and 0 7 to allow easy cascading. Four operation modes are possible: hold (store), shift left, shift right and parallel load.
Features
� Common parallel 1/0 for reduced pin count � Additional serial inputs and outputs for expansion � Four operating modes: shift left, shift right, load and
store � TRI-STATE outputs for bus-oriented applications � Guaranteed 4000V minimum ESD protection
Ordering Code: see sections Logic Symbols
TL/F/9517-1
IEEE/I EC
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
So 1 OE1 2 OE2 3 1/05 4 1/04 5 1/02 6 l/Oo 7
Oo
Sii
GND 10
20 Vee
19 s,
18 DS7 17 07 16 1/07 15 I/Os 14 1/03 13 1/01 12 CP 11 DS0
TL/F/9517-2
Pin Assignment for LCC
~ VOo ~ vo, VO.
[[JCTJ[!J[[llIJ
GSND [QiJi[[]DIT]OE[II zOE1
DSo [j]
OJ So
CPlilJ
~Vr;c
1/01 I]]
[fil s,
li]~[j]]li][j]]
"'�31/0sl/OJilJ DSr
TL/F /9517-3
DSo
Oo
l/Oo
1/01
1/02 1/03 1/04 1/05 1/06 1/07
DS7
07
TL/F/9517-5
4-242
Unit Loading/Fan Out: See Section 2 for U.L. definitions
Pin Names
CP DSo DS7 So,S1 SR OE1, OE2 l/Oo-1/07
Oo,07
Description
Clock Pulse Input (Active Rising Edge) Serial Data Input for Right Shift Serial Data Input for Left Shift Mode Select Inputs Synchronous Reset Input (Active LOW) TRI-STATE Output Enable Inputs (Active LOW) Multiplexed Parallel Data Inputs TRI-STATE Parallel Data Outputs Serial Outputs
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loHllOL
1.0/1.0 1.0/1.0 1.0/1.0 1.0/2.0 1.0/1.0 1.0/1.0 3.5/1.083 150/40 (33.3) 50/33.3
20 �Al -0.6 mA 20 �A/-0.6 mA 20 �A/ - 0.6 mA 20 �A/-1.2 mA 20 �A/-0.6 mA 20 �A/-0.6 mA 70 �A/ - 0.65 mA -3 mA/24 mA (20 mA) -1 mA/20 mA
Functional Description
The 'F323 contains eight edge-triggered D-type flip-flops and the interstage logic necessary to perform synchronous reset, shift left, shift right, parallel load and hold operations. The type of operation is determined by So and S1 as shown in the Mode Select Table. All flip-flop outputs are brought out through TRI-STATE buffers to separate 1/0 pins that also serve as data inputs in the parallel load mode. Oo and 07 are also brought out on other pins for expansion in serial shifting of longer words.
A LOW signal on SR overrides the Select inputs and allows the flip-flops to be reset by the next rising edge of CP. All
other state changes are also initiated by the LOW-to-HIGH CP transition. Inputs can change when the clock is in either state provided only that the recommended setup and hold times, relative to the rising edge of CP, are observed.
A HIGH signal on either OE1 or OE2 disables the TRISTATE buffers and puts the 1/0 pins in the high impedance state. In this condition the shift, load, hold and reset operations can still occur. The TRI-STATE buffers are also disabled by HIGH signals on both So and S1 in preparation for a parallel load operation.
Mode Select Table
Inputs
SR
S1
So
CP
L x x _r
H
H
H
_r
H
L
H
_r
H
H
L
_r
H
L
L
x
H = HIGH Voltage Level
L = LOW Voltage Level X = Immaterial .../" = LOW-to-HIGH transition
Response
Synchronous Reset; Oo-07 = LOW Parallel Load; I/On ~ On Shift Right; DS0 ~ Oo, Oo ~ 01, etc. Shift Left; DS7 ~ 07 07 ~ Os, etc.
1
Hold
I
4-243
Logic Diagram
TL/F/9517-4 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-244
Absolute Maximum Ratings (Note 1i
If Miiitary/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for avallablllty and specifications.
Storage Temperature
- 65�C to + 150�c
Ambient Temperature under Bias
-55�C to + 125�C
Junction Temperature under Bias
-55�C to+ 175�C
Vee Pin Potential to Ground Pin
-0.5V to + 7.0V
Input Voltage (Note 2)
-0.5V to + 7.0V
Input Current (Note 2)
-30 mA to + 5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
-0.5VtoVee -0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
ESD Last Passing Voltage (Min)
4000V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�c o�cto +70�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
V1H
Input HIGH Voltage
V1L
Input LOW Voltage
Veo
Input Clamp Diode Voltage
54F/74F
Units Vee
Min Typ Max
Conditions
2.0
v
Recognized as a HIGH Signal
0.8
v
Recognized as a LOW Signal
v -1.2
Min l1N = -18 mA
VoH
Output HIGH
Voltage
54F 10% Vee 2.5 54F 10% Vee 2.4 74F 10% Vee 2.5 74F 10% Vee 2.4 74F5% Vee� 2.7 74F5% Vee 2.7
loH = -1 mA (Oo,07)
loH = -3 mA (I/On)
v
loH = -1 mA (Oo,07) Min loH = -3 mA (I/On)
loH = -1 mA (Oo,07)
loH = -3 mA (I/On)
VoL
Output LOW
Voltage
54F 10% Vee 74F 10% Vee 74F 10% Vee
0.5
loL = 20mA (I/On, Oo, 07)
0.5
v Min loL = 20 mA (Oo,07)
0.5
loL = 24 mA (I/On)
l1H
Input HIGH
54F
Current
74F
20.0
V1N = 2.7V
�A Max
5.0
lsv1
Input HIGH Current 54F
Breakdown Test 74F
100
V1N = 7.0V (Non 1/0 Inputs)
�A Max
7.0
lsv1T
Input HIGH Current 54F Breakdown (1/0) 74F
1.0
V1N = 5.5V (1/0 Inputs)
0.5
mA Max
leEX
Output HIGH
54F
Leakage Current 74F
250
50
�A Max VouT =Vee
V10
Input Leakage
74F
4.75
Test
v 0.0 110 = 1.9 �A All Other Pins Grounded
loo
Output Leakage
74F
Circuit Current
3.75
�A
0.0
V100 = 150 mV All Other Pins Grounded
l1L
Input LOW Current
los
Output Short-Circuit Current
lzz
Bus Drainage Test
-0.6 mA Max V1N = 0.5V (CP, DSo, DS7, SR, OE1, OE2) -1.2 mA Max V1N = 0.5V (So,S1)
-60
-150 mA Max VouT = ov
500 �A o.ov VouT = 5.25V
leeH
Power Supply Current
68 95 mA Max Vo= HIGH
leeL
Power Supply Current
68 95 mA Max Vo= LOW
leez
Power Supply Current
68 95 mA Max Vo= HIGHZ
4-245
C") N
C") AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
fmax
tPLH tPHL
tPLH tPHL
tpzH tpzL
tpHz tpLz
tpzH tpzL
tpHz tpLz
Maximum Input Frequency Propagation Delay
CPto Oo or07
Propagation Delay CP to I/On Output Enable Time
Output Disable Time
Output Enable Time Sn to I/On Output Disable Time Sn to I/On
74F
TA= +25�C Vee= +5.0V
CL= 50pF
Min
Typ
Max
70
100
4.0
7.0
8.0
4.5
6.5
8.0
3.5
7.0
9.0
4.0
8.5
9.0
3.5
6.0
8.0
4.0
7.0
10.0
2.0
4.5
6.0
1.0
4.0
5.5
3.5
9.0
4.0
10.0
2.5
6.0
1.0
5.5
54F
TA, Vee= Mil CL= 50 pf
Min
Max
74F
TA, Vee= Com CL= 50pF
Min
Max
70
4.0
8.5
4.5
8.5
3.5
10.0
4.0
10.0
3.5
9.0
4.0
11.0
2.0
7.0
1.0
6.5
3.5
10.0
4.0
11.0
2.5
7.0
1.5
6.5
Fig. Units No. MHz 2-1
ns 2-3
ns 2-5 ns 2-5 ns 2-5
AC Operating Requirements: See Section 2 for Waveforms
Symbol
Parameter
t5(H) t5(L)
th(H) th(L)
t 5(H) t 5(L)
th(H) th(L)
t5(H) t5(L)
th(H) th(L)
tw(H) tw(L)
Setup Time, HIGH or LOW So or S1 to CP
Hold Time, HIGH or LOW So orS1 toCP Setup Time, HIGH or LOW I/On. DSo, DS7 to CP
Hold Time, HIGH or LOW I/On. DSo, DS7 to CP
Setup Time, HIGH or LOW SR toCP
Hold Time, HIGH or LOW SR to CP
CP Pulse Width HIGH or LOW
74F
TA= +25�C Vee= +5.0V
Min
Max
8.5 8.5
0 0
5.0 5.0
2.0 2.0
10.0 10.0
0 0
5.0 5.0
54F
TA, Vee= Mil
Min
Max
74F
TA, Vee= Com
Min
Max
8.5 8.5
0 0
5.0 5.0
2.0 2.0
10.0 10.0
0 0
5.0 5.0
Units
Fig. No.
ns
2-6
ns
2-6
ns
2-6
ns
2-4
4-246
CJ.)
U1
~National
0
D Semiconductor
54F/74F350 4-Bit Shifter with TRI-STATE� Outputs
General Description
The 'F350 is a specialized multiplexer that accepts a 4-bit word and shifts it 0, 1, 2 or 3 places, as determined by two Select (So, S1) inputs. For expansion to longer words, three linking inputs are provided for lower-order bits; thus two packages can shift an 8-bit word, four packages a 16-bit word, etc. Shifting by more than three places is accomplished by paralleling the TRI-STATE outputs of different packages and using the Output Enable (OE) inputs as a third Select level. With appropriate interconnections, the 'F350 can perform zero-backfill, sign-extend or end-around (barrel) shift functions.
Features
� Linking inputs for word expansion � TRI-STATE outputs for extending shift range
Ordering Code: see section 5 Logic Symbols
'-3 '-z '-1 lo 11 lz 13 So S1 OE
Oo 01 Oz 03
TL/F/9516-3
IEEE/I EC
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
1_3 l_z 2 1-1 3 lo 4
11 5 lz 13 7 GND
16 Yee 15 Oo 14 01
13 6E
12 Oz 11 03 10 So 9 S1
TL/F/9516-1
Pin Assignment forLCC
lz
[[]
u11:mNCrn~:i
mL1
13 [[] GND fj]J NC [i]
S1 fill So Ii]]
[I]Lz
IIJL3 [IJNC ~Vee llfilOo
fill [fil [�] [ZJ [j]]
03 02 NC OE 01
TL/F/9516-2
TL/F/9516-6
4-247
Unit Loading/Fan Out: See Section 2 for u.L. definitions
Pin Names
So,S1 l-3-13 OE Oo-03
Description
Select Inputs Data Inputs Output Enable Input (Active LOW) TRI-STATE Outputs
54F/74F
U.L. HIGH/LOW
Input l1H/l1L Output loH/loL
1.0/2.0 1.0/2.0 1.0/2.0 150/40 (33.3)
20 �A/-1.2 mA 20 �A/-1.2 mA 20 �A/ -1.2 mA -3 mA/24 mA (20 mA)
Functional Description
The 'F350 is operationally equivalent to a 4-input multiplexer with the inputs connected so that the select code causes successive one-bit shifts of the data word. This internal connection makes it possible to perform shifts of 0, 1, 2 or 3 places on words of any length.
A 4-bit data word is introduced at the In inputs and is shifted according to the code applied to the select inputs So, S1. Outputs 0 0 -03 are TRI-STATE, controlled by an active LOW output enable (OE). When OE is LOW, data outputs will follow selected data inputs; when HIGH, the data outputs will be forced to the high impedance state. This feature allows shifters to be cascaded on the same output lines or
Truth Table
Inputs
Outputs
OE
51
So
Oo
01
02
H
x x
z
z
z
L
L
L
lo
11
12
L
L
H
'-1
lo
11
L
H
L
'-2
'-1
lo
L
H
H
l-3
1-2
'-1
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance
Logic Diagram
to a common bus. The shift function can be logical, with zeros pulled in at eithe.r or both erids of the shifting field; arithmetic, where the sign. bit is repeated during a shift down; or end around, where the data word forms a continuous loop.
Logic Equations
Oo = SoS1lo + SoS1'-1 + SoS1'-2 + SoS1L3 01 = SoS1l1 + SoS1lo + SoS1l-1 + SoS1'-2 02 = SoS1l2 + SoS1l1 + SoS1lo + SoS1l-1 03 = SoS113 + SoS112 + SoS111 + SoS1 lo
03
z
13 12 11 lo
TL/F/9518-4 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-248
Applications
0 123
16-Blt Shift-Up oto 3 Places, Zero Backfill
4 5 6 7
8 9 10 11
w
U1 0 11 13 14 15
GND-~.....,
l.3 l.2 1., lo 1, 12 13 So
L3 L2 1., lo 11 12 13 So
l.3 L2 L1 lo 11 12 13 So
s,
OE
So...,.-+-ll---+--+---+-+--~-+---+---+1--+--+---+-+-+--t---+--+---tl----'
s,--~~--+---+---+--t------+----t---i~-+---+--------.,__-+-_..,--l~-..... ~---4~-+--+--+-+---+---+---+-+--+----+---tl--+--+---+----'
9 10 11
12 13 14 15 TL/F/9516-5
Function Table
S1
So
Shift Function
L
L
No Shift
L
H
Shift 1 Place
H
L
Shift 2 Places
H
H
Shift 3 Places
0 12 3
8-Blt End Around Shift oto 7 Places
4 5 6 7
L3 L2 L1 lo 1,
i-----so
r---s,
~OE
Yo Y1 Y2
12 13 Y3
I Ll .I J_
I I 1
L3 L2 L1 lo 1, 12 13 r---So
.--s,
r() OE
Yo Y1 Y2 Y3
I .I J_ I J. J.
I 11
1.3 1.2 1.1 10 1, 12 13
r-----so
r--1 s, ~OE
Yo Y1 Y2 Y3
1 i Il
l.3 l.2 '-1 'o 1, 12 13
r-----so
.---- s,
~OE
Yo Y1 Y2 Y3
TL/F/9516-6
4-249
0
U')
C") Applications (Continued)
Function Table
S2
S1
So
Shift Function
L
L
L
No Shift
L
L
H
Shift End Around 1
L
H
L
Shift End Around 2
L
H
H
Shift End Around 3
H
L
L
Shift End Around 4
H
L
H
Shift End Around 5
H
H
L
Shift End Around 6
H
H
H
Shift End Around 7
13�Bit Twos Complement Scaler
12 11 10 9
8 7 6 5
4 3 2 1
s
ll l
l_3 1-2 1-1 lo 11 12 13 ,...--- So
r--S1
If�' Yo Y1 Y2 Y3
11 l
1_3 1-2 1-1 lo 11 12 13 ,...--- So
r--! s,
It�' Yo Y1 Y2 Y3
..........
1II
. - 1_3 1-2 '-1 lo 11 '2 13 So
IJ40Er--S1 Yo Y1 Y2 Y3
12 11 10 9
7
5
Function Table
S1
So
Scale
L
L-;-8
%
L
H-;-4
%
H
L-;-2
%
H
H No Change
1
4 3 2
s
TL/F/9516-7
4-250
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�c
Ambient Temperature under Bias
- 55�C to + 125�c
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5Vto +7.0V
Input Voltage (Note 2)
-0.5V to + 7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
w
U1 0
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
Current Applied to Output in LOW State (Max)
-0.5VtoVee - 0.5V to + 5.5V
twice the rated loL (mA)
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C o�cto +70�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V +4.5V to +5.5V
DC Electrical Characteristics
Symbol V1H V1L Veo VoH
VoL
l1H
lsv1 leEX
V10 loo l1L lozH lozL los lzz leeH leeL leez
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee 74F 5% Vee 74F 10% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage
74F
Test
Output Leakage
Circuit Current
74F
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Bus Drainage Test
Power Supply Current
Power Supply Current
Power Supply Current
54F/74F
Min Typ Max
2.0
0.8 -1.2
2.5 2.4 2.5 2.4 2.7 2.7
0.5 0.5
20.0 5.0 100 7.0
250 50
4.75
-60
34 40 40
3.75
-1.2 50 -50
-150 500 42 57 57
Units
v v v
v
v
�A
�A
�A
v
�A mA �A �A mA �A mA mA mA
Vee
Min
Min
Min Max Max Max 0.0 0.0 Max Max Max Max O.OV Max Max Max
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal l1N = -18 mA loH = -1 mA loH = -3mA loH = -1 mA loH = -3mA loH = -1 mA loH = -3mA loL = 20 mA loL = 24 mA V1N = 2.7V
V1N = 7.0V
VouT =Vee
110 = 1.9 �A All Other Pins Grounded V100 = 150 mV All Other Pins Grounded V1N = 0.5V VouT = 2.7V VouT = 0.5V VouT = ov VouT = 5.25V Vo= HIGH Vo= LOW Vo= HIGHZ
4-251
0
Lt)
C") AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
tpLH tpHL
tPLH tPHL
tpzH tpzL
tpHz tpLZ
Propagation Delay In to On Propagation Delay Sn to On Output Enable Time
Output Disable Time
74F
TA= +25�C Vee= +5.0V
CL= 50 pf
Min
Typ
Max
3.0
4.5
6.0
2.5
4.0
5.5
4.0
7.8
10.0
3.0
6.5
8.5
2.5
5.0
7.0
4.0
7.0
9.0
2.0
3.9
5.5
2.0
4.0
5.5
54F
TA, Vee= Mil CL= 50pF
Min
Max
74F
TA, Vee= Com CL= 50 pf
Min
Max
3.0
7.0
2.5
6.5
4.0
13.5
3.0
9.5
2.5
8.0
4.0
10.0
2.0
6.5
2.0
7.5
Units Fig. No.
ns
2-3
ns
2-3
ns
2-5
4-252
U~NaStemiicoonnduactlor
54F/74F352 Dual 4-lnput Multiplexer
General Description
The 'F352 is a very high-speed dual 4-input multiplexer with common Select inputs and individual Enable inputs for each section. It can select two bits of data from four sources. The two buffered outputs present data in the inverted (complementary) form. The 'F352 is the functional equivalent of the 'F153 except with inverted outputs.
Features
� Inverted version of 'F153 � Separate enables for each multiplexer � Input clamp diode limits high speed termination effects
Ordering Code: see section 5 Logic Symbols
s 1oa '1 a '211 1311 'ob 11 b l2b l3b 0
S1
Ea
Eb
zb
I E E E / I EC
TL/F /9519-3
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
Ea 1 S1 2 13a 3 '2a 4 l1a 5 'oa 6 za GND
16 Vee 15 Eb 14 So 13 l3b 12 '2b 11 l1b
10 1ob 9 zb
TL/F/9519-1
Pin Assignment forLCC
1oa 11a NC l2a 13a
rnmmrnm
GNZ D liQal [ f i l O [ I ) S(1)1Ea
NC [i] Zb [lJ
[j]NC
~Vee
'ob [j]J
lJ]J Eb
~~[j]][i]li]) 11b l2b NC l3b So
TL/F/9519-2
TL/F/9519-5
Unit Loading/Fan Out: See Section 2 for U.L. definitions
54F/74F
Pin Names
Description
U.L.
Input l1Hll1L
HIGH/LOW Output loHlloL
loa-13a lob-13b So-S1 Ea Eb Za,Zb
Side A Data Inputs Side 8 Data Inputs Common Select Inputs Side A Enable Input (Active LOW) Side B Enable Input (Active LOW) Multiplexer Outputs (Inverted)
1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 50/33.3
20 �A/-0.6 mA 20 �A/-0.6 mA 20 �A/ - 0.6 mA 20 �A/ - 0.6 mA 20 �Al - 0.6 mA
-1 mA/20mA
4-253
Functional Description
The 'F352 is a dual 4-input multiplexer. It selects two bits of data from up to four sources under the control of the common Select inputs (So, S1). The two 4-input multiplexer circuits have individual active LOW Enables (Ea, Eb) which can be used to strobe the outputs independently. When the Enables (Ea. Eb) are HIGH, the corresponding outputs (Za. Zb) are forced HIGH.
The logic equations for the outputs are shown below:
Za =Ea� (loa � S1 �So+ l1a � S1 �So+
l2a � S1 � So + Isa � S1 � So) Zb =Eb� (lob� S1 �So+ l1b � S1 �So+
l2b � S1 � So + lsb � S1 � So)
The 'F352 can be used to move data from a group of registers to a common output bus. The particular register from which the data came would be determined by the state of the Select inputs. A less obvious application is as a function generator. The 'F352 can generate two functions of three variables. This is useful for implementing highly irregular random logic.
Truth Table
Select Inputs
Inputs (a orb)
Output
So
S1
E
lo
11
12
13
z
x xHxxxx
H
L
L
L L xxx
H
L
L
L H xxx
L
H
L
LxL xx
H
H
L
L xH xx
L
L
H
L xxL x
H
L
H
L xxH x
L
H
H
L xxxL
H
H
H
L xxxH
L
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
Logic Diagram
TL/F/9519-4 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-254
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for avallablllty and specifications.
~torage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
-55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5Vto +7.0V
Input Voltage (Note 2)
-0.5Vto +7.0V
Input Current (Note 2)
-30 mA to + 5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5V to Vee - 0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�C to +70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
V1H
Input HIGH Voltage
V1L
Input LOW Voltage
Veo
Input Clamp Diode Voltage
54F/74F Min Typ Max
Units Vee
Conditions
2.0
v
Recognized as a HIGH Signal
0.8
v
Recognized as a LOW Signal
-1.2
v
Min l1N = -18 mA
VoH
Output HIGH
Voltage
54F 10% Vee 2.5
74F 10% Vee 2.5
74F5% Vee
2.7
loH = -1 mA
v
Min loH = -1 mA
loH = -1 mA
VoL
Output LOW
Voltage
54F 10% Vee 74F 10% Vee
0.5
v
loL = 20 mA Min
0.5
loL = 20 mA
l1H
Input HIGH
54F
Current
74F
20.0
�A
Max V1N = 2.7V
5.0
lsv1
Input HIGH Current 54F
Breakdown Test
74F
100
�A
Max V1N = 7.0V
7.0
leEx
Output HIGH
54F
Leakage Current
74F
250 50
�A
Max Vour =Vee
V10
Input Leakage
74F
4.75
Test
v
110 = 1.9 �A 0.0 All Other Pins Grounded
loo
Output Leakage 74F
Circuit Current
3.75
�A
0.0 V100 = 150mV All Other Pins Grounded
l1L
Input LOW Current
los
Output Short-Circuit Current
-0.6
mA
Max V1N = 0.5V
-60
ov -150 mA Max Vour =
leeH
Power Supply Current
9.3
14
mA Max Vo= HIGH
leeL
Power Supply Current
13.3
20
mA Max Vo= LOW
4-255
N
II)
Cf) AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
74F
54F
74F
Symbol
Parameter
TA= +25�C Vee= +s.ov
CL= 50pf
Min
Typ
Max
TA, Vee= Mil CL= 50pf
Min
Max
TA, Vee= Com CL= 50pf
Min
Max
tPLH
Propagation Delay
4.0
8.0
11.0
3.5
14.0
3.5
12.5
tPHL
Sn to Zn
3.5
6.5
8.5
3.0
11.0
3.0
9.5
tPLH
Propagation Delay
3.0
4.5
6.0
2.5
8.0
2.5
7.0
tPHL
En to Zn
3.0
5.0
7.0
2.5
9.0
2.5
8.0
tPLH
Propagation Delay
2.0
5.2
7.0
2.0
9.0
2.0
8.0
tPHL
In to Zn
1.3
2.5
4.0
1.0
5.0
1.0
4.5
Fig. Units No.
ns 2-3 ns 2-3 ns 2-3
4-256
w
~National
Uw 1
~Semiconductor
54F/74F353 Dual 4-lnput Multiplexer with TRI-STATE� Outputs
General Description
The 'F353 is a dual 4-input multiplexer with TRI-STATE outputs. It can select two bits of data from four sources using common Select inputs. The outputs may be individually switched to a high impedance state with a HIGH on the respective Output Enable (OE) inputs, allowing the outputs to interface directly with bus-oriented systems.
Features
� Inverted version of 'F253 � Multifunction capability � Separate enables for each multiplexer
Ordering Code: see section 5 Logic Symbols
OEa lea 1111 1211 13a 'ob '1 b '2b l3b
OEb
So
s1
zb
IEEE/I EC
TL/F/9520-3
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
O'Ea S1 13a 3 l2a l1a 1011 6 Za 7
GND 8
16 Vee
15 O'Eb 1'4 So 13 l3b 12 l2b 11 l1b 10 lob
9 zb
TL/F/9520-1
Pin Assignment for LCC
oommrnm lo11 l1a NC 12111311
c!~~o~~-
NC [iJ
[j]NC
zb~
~Vee
1ob ~
Ii]] O'Eb
~~filll!1J[fil l1b l2b NC l3b So
TL/F/9520-2
TL/F/9520-5
Unit Loading/Fan Out: See Section 2 tor U.L. definitions
Pin Names
Description
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loHllOL
1oa-13a lob-13b So,S1 OEa OEb Za.Zb
Side A Data Inputs Side B Data Inputs Common Select Inputs Side A Output Enable Input (Active LOW) Side 8 Output Enable Input (Active LOW) TRI-STATE Outputs (Inverted)
1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 150/40 (33.3)
20 �Al - 0.6 mA 20 �Al - 0.6 mA 20 �A/ - 0.6 mA 20 �Al -0.6 mA 20 �A/-0.6 mA -3 mA/24 mA (20 mA)
4-257
Functional Description
The 'F353 contains two identical 4-input multiplexers with TRI-STATE outputs. They select two bits from four sources selected by common Select inputs (S0, S1). The 4-input multiplexers have individual Output Enable (OEa. OEb) inputs which, when HIGH, force the outputs to a high impedance (High Z) state. The logic equations for the outputs are shown below:
Za = OEa�(loa�S1�So + l1a�S1�So + l2a�S1 �So + l3a�S1 �So)
Zb = OEb�(lob�S1�So + l1b�S1�So + l2b�S1 �So + l3b�S1 �So)
If the outputs of TRI-STATE devices are tied together, all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings.. Designers should ensure that Outpu~ Enable signals to TRISTATE devices whose outputs are tied together are designed so that there is no overlap.
Truth Table
Select Inputs
So
S1
x x
L
L
L
L
H
L
Data Inputs
lo
11
12
13
x x x x L xxx H xxx x L x x
Output Enable
OE
H L L L
Output
z z
H L H
H L xHxx
L
L
L H xxL x
L
H
L H xxH x
L
L
H H xxxL
L
H
H H xxxH
L
L
Address inputs So and S1 are common to both sections.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial Z = High Impedance
Logic Diagram
TL/F/9520-4 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-258
Absolute Maximum Ratings (Note 1)
If Miiitary/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for avallabllity and specifications.
Storage Temperature
-65�C to+ 15o�c
Ambient Temperature under Bias
-55�C to+ 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5Vto +7.0V
Input Voltage (Note 2)
-0.5Vto +7.0V
Input Current (Note 2)
-30 mA to + 5.0 mA
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
-0.5VtoVee -0.5Vto +5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C o�c to +70�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol V1H V1L Veo VoH
Vol
l1H
lsv1 leEX V10
loo
l1L lozH lozL los lzz leeH leeL leez
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee 74F5% Vee 74F5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage 74F
Test
Output Leakage 74F
Circuit Current
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Bus Drainage Test
Power Supply Current
Power Supply Current
Power Supply Current
54F/74F
Min Typ Max
2.0
0.8 -1.2
2.5 2.4 2.5 2.4 2.7 2.7
0.5 0.5
20.0 5.0 100 7.0
250 50
4.75
3.75
-0.6
50
-50
-60
-150
500
9.3
14
13.3
20
15.0
23
Units v v v
v
v
�A �A
�A v
�A mA �A �A mA �A mA mA mA
Vee
Min
Min
Min Max Max Max 0.0 0.0 Max Max Max Max o.ov Max Max Max
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal l1N = -18 mA loH = -1 mA loH = -3mA loH = -1 mA loH = -3mA loH = -1 mA loH = -3mA loL = 20 mA loL = 24 mA V1N = 2.7V
V1N = 7.0V
Vour =Vee
110 = 1.9 �A All Other Pins Grounded V100 = 150 mV All Other Pins Grounded V1N = 0.5V Vour = 2.7V Vour = 0.5V Vour = ov Vour = 5.25V Vo= HIGH Vo= LOW Vo= HIGHZ
4-259
-�~
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
tPLH tPHL
tPLH tPHL
tpzH tpzL
tpHz tpLZ
Propagation Delay Sn to Zn Propagation Delay In to Zn Output Enable Time
Output Disable Time
74F
c TA= +2s0
Vee= +5.0V CL= 50pf
Min
Typ
Max
4.0
8.0
11.0
3.5
6.5
8.5
3.0
5.2
7.0
1.3
2.5
4.0
2.5
5.5
8.0
3.0
6.0
8.0
2.0
3.7
5.0
2.0
4.4
6.0
54F
TA, Vee= Mii CL= 50pf
Min
Max
3.5
14.0
3.0
11.0
3.0
9.0
1.0
5.0
2.0
10.5
2.5
10.5
2.0
7.0
2.0
8.0
74F
TA, Vee= Com CL= 50pf
Min
Max
3.5
12.5
3.0
9.5
3.0
8.0
1.0
4.5
2.0
9.0
2.5
9.0
2.0
6.0
2.0
7.0
Units
Fig. No.
ns 2-3 ns 2-3 ns 2-5
4-260
w
O>
~National
U1
D Semiconductor
54F/74F365
Hex Buffer/Driver with TRI-STATE� Outputs
General Description
The 'F365 is a hex buffer and line driver designed to be employed as a memory and address driver, clock driver and bus-oriented transmitter/receiver.
Features
� TRI-STATE buffer outputs � Outputs sink 64 mA � Bus-oriented
Ordering Code: see sections
Logic Symbol
Connection Diagrams
IEEE/I EC
lo
Oo
1,
o,
12
02
13
03
14
04
15
05
Pin Assignment for DIP, SOIC and Flatpak
OE1
Yee
lo
OE2
Oo
13
11
03
o,
14
12
04
02
15
GND
05
TL/F/9522-1
Pin Assignment forLCC
r'2n r0n1 oNCo r1n1 r0no
02 [[) GND [QI NC [j]
05 Ii]]
15~
rn10 CIIOE1
[I]NC
~Yee li]JOE2
li])[IDli]]IIlJ[ID 04 14 NC o3 13
TL/F /9522-2
TL/F/9522-4
Unit Loading/Fan Out: see Section 2 for U.L. definitions
Pin Names
DE1,0E2
In On
Description
Output Enable Input (Active LOW) Inputs Outputs
U.L HIGH/LOW
1.0/0.033
54F/74F
Input l1Hll1L Output loHllOL
20 �.A/20 �A
1.0/0.033
20 �.A/20 �A
600/106.6 (80) -12 mA/64 mA (48 mA)
Function Table
Inputs
OE1
OE2
I
L
L
L
L
L
H
x
H
x
H
x
x
Output 0 L H
z z
L = LOW Voltage Level
H = HIGH Voltage Level
X = Immaterial
Z = High Impedance
4-261
Absolute Maximum Ratings (Note 1)
If Miiitary/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vcc Pin Potential to Ground Pin
-0.5V to+ 7.0V
Input Voltage (Note 2)
-0.5V to + 7.0V
Input Current (Note 2)
- 30 mA to + 5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
-0.5V to Vee -0.5V to +5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�c to + 125�c o�c to +10�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
V1H V1L Veo VoH
VoL
l1H lsv1
l1L lozH lozL las leEx lzz lccH lccL lccz
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee 74F5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH Current
Input HIGH Current Breakdown Test
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Output HIGH Leakage Current
Bus Drainage Test
Power Supply Current
Power Supply Current
Power Supply Current
54F/74F
Min Typ Max
2.0
0.8 -1.2
2.4 2.0 2.4 2.0 2.7
0.55 0.55
20
100
-100
25 44 35
-20 50 -50 -225 250 500 35 62 48
Units
v v v
v
v
�A �A �A �A �A
mA
�A �A
mA mA mA
Vee
Min
Min
Min Max 0.0 Max Max Max Max Max
o.ov
Max Max Max
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal l1N = -18 mA loH = -3mA loH = -12 mA loH = -3mA loH = -15 mA loH = -3mA loL = 48mA loL = 64mA V1N = 2.7V V1N = 7.0V
V1N = 0.5V VouT = 2.7V VouT = 0.5V
VouT = ov
VouT =Vee VouT = 5.25V Vo= HIGH Vo= LOW Vo= HIGHZ
4-262
AC Electrical Characteristics: see Section 2 for waveforms and Load configurations
Symbol
Parameter
tPLH tPHL
tpzH tpzL
tpHz tpLZ
Propagation Delay lntOOn Enable Time
Disable Time
74F
TA= +25�C Vee= +5.0V
CL= 50 pf
Min
Typ
Max
2.5
4.6
6.5
2.5
4.9
7.0
2.5
5.1
9.5
2.5
5.7
9.0
2.0
3.6
6.5
2.0
4.4
6.5
54F
TA, Vee= Mii CL= 50 pf
Min
Max
2.0
7.0
2.0
7.0
2.0
8.5
2.0
8.5
1.5
6.5
1.5
9.0
74F
TA, Vee= Com CL= 50 pf
Min
Max
2.0
7.0
2.0
7.5
2.5
10.0
2.5
9.5
2.0
7.0
2.0
7.0
ew n
U1
Units Fig. No.
ns
2-3
ns
2-5
ns
2-5
4-263
i National CcoD
'WA Cf) ~ Semiconductor
54F/74F366�54F/74F368
Hex Inverter Buffer with TRI-STATE� Outputs
Features
� TRI-STATE buffer outputs sink 64 mA � High-speed � Bus-oriented � High impedance npn base inputs for reduced loading
Ordering Code: see sections
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
or,
lo Oo
1,
o,
12
02
GND
05
'F366
TL/F/9521-2
Pin Assignment forLCC
o12o
mo1 oNoC
11
111
orn0
02 [ID GND [Q] NC [j]
05 Hll
15 Ii]
!II lo
III or1
r+1t-+-1!:4--<:Jt:; Ill" [D NC (ig Vee Ii]] or2
o,~[�]!i]Jfj][j]J
1, NC 63 13
TUF/9521-1
Pin Assignment for DIP, SOIC and Flatpak
'F368
TL/F/9521-4
Pin Assignment for LCC
o12o
m61 oNoC
11
111
orn0
02 [ID GND [Q] NC [l]
05 Hll ...... ,.q, r''<h ,-Q-,
15 Ii]
!IIIlIloor1
[DNC
liQI Vee
ll]]or2
o,~[�]!i]Jfj][j]J 1, NC 03 13
TL/F/9521-3
4-264
Logic Symbols
I E E E / I EC 'F366
w
CJ)
�CJ)
w
CJ)
co
I E E E / I EC 'F368
EN1 EN2
lo
I> v Oo
lo
I> 1V Oo
11
01
11
01
12
02
12
02
13
03
1..
o..
13
03
I"
I> 2V o..
15
05
15
TL/F/9521-5
Unit Loading/Fan Out: See Section 2 for u.L. definitions
Pin Names
OE1,0E2
In On, On
Description
Output Enable Input (Active LOW) Input Outputs
54F/74F
U.L HIGH/LOW
Input l1Hll1L Output loHlloL
1.0/0.033 1.0/0.033 600/106.6 (80)
20 �A/-20 �A 20 �A/-20 �A -12 mA/64 mA (48 mA)
05
TL/F /9521-6
Function Tables
'F366
Inputs
Output
OE1 OE2
I
0
L
L
L
H
L
L
H
L
x
H x
z
H
x x
z
'F368
Inputs
OE
I
L
L
L
H
H
x
Output
0
H L
z
L = LOW Voltage Level H = HIGH Voltage Level X = Immaterial Z = High Impedance
4-265
ccoo
�C")
ccoo
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
C")
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias ',� Junction Temperature under Bias
- 55�C to + 125�C - 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to + 7.0V
Input Voltage (Note 2)
-0.5Vto +7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output .
-0.5VtoVee -0.5Vto +5.5V
Current Applied to Output in LOW State (Max)
tWice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
V1H V1L Veo VoH
VoL
l1H lsv1
l1L lozH lozL los lcEx lzz lceH lceL lcez
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 74F 10% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH Current
Input HIGH Current Breakdown Test
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Output HIGH Leakage Current
Bus Drainage Test
Power Supply Current
Power Supply Current
Power Supply Current
54F/74F Min Typ Max 2.0
0.8 -1.2 2.0 2.0 0.55 0.55 20
100
-20
50
-50
-100
-225
250
500
20
25
49
62
35
48
Units
v v v
v v
�A
�A
�A �A �A mA �A �A mA mA mA
Vee
Min
Min Min Max Max Max Max Max Max Max
o.ov
Max Max Max
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal l1N = -18 mA loH = -12 mA loH = -15 mA loL = 48 mA loL = 64 mA V1N = 2.7V V1N = 7.0V
V1N = 0.5V VouT = 2.7V VouT = 0.5V
VouT = ov
VouT =Vee VouT = 5.25V Vo= HIGH Vo= LOW Vo= HIGHZ
4-266
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
74F
54F
74F
Symbol
Parameter
tPLH tPHL
tpzH tpzL
tpzH tpzL
tpHz tpu
Propagation Delay Enable Time ('F366) Enable Time ('F368) Disable Time
TA= +25�C Vee= +5.0V
CL= 50pf
Min
Typ
Max
2.5
4.0
6.5
1.0
1.8
5.0
2.5
4.2
9.5
2.5
4.2
9.0
2.5
4.2
7.5
3.0
5.6
8.5
2.0
3.3
6.5
2.0
4.1
6.5
TA, Vee= Mil CL= 50 pf
Min
Max
TA, Vee= Com CL= 50pf
Min
Max
2.0
7.5
1.0
5.5
2.5
10.0
2.5
9.5
2.0
8.5
3.0
9.0
2.0
7.0
2.0
7.0
�eewnn
ecwno
Units Fig. No.
ns
2-3
ns
2-5
ns
2-5
ns
2-5
4-267
a~National Semiconductor
54F/74F373
Octal Transparent Latch with TRl..STATE� Outputs
General Description
The 'F373 consists of eight latches with TRI-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH the bus output is in the high impedance state.
Features
� Eight latches in a single package � TRI-STATE outputs for bus interfacing � Guaranteed 4000V minimum ESD protection
Ordering Code: see section 5 Logic Symbols
IEEE/IEC
OE
LE
Do
Oo
D1
o,
Dz
Oz
D3
03
D_.
o_.
D5
05
Ds
Os
~
07
TL/F/9523-4
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
OE 1
Oo 2 Do 3 D1 4
o, 5
Oz 6 Dz 7 D3 8 03 9 GND 10
20 Vee 19 07 18 ~ 17 Ds 16 Os 15 05 14 D5 13 D_.
12 o,.
11 LE
TL/F/9523-2
Pin Assignment for LCC
~~Oz
[[) IIl []]
ron1
D1
III
03 []] GND [QJ
LE [i]
o,.@
D4 fi]
CTlDo
IIJOo
ITl OE
~Vee
!iID07
IJ3Jfi�]!rnfiZl!!ID Ds 05 Os Ds ~
TL/F/9523-3
Do D1 Dz D3 D4 D5 Ds ~ LE
OE
o0 o1 Oz o3 o4 o5 Os o7
TL/F/9523-1
Unit Loading/Fan Out: See Section 2 for u.L. Definitions
Pin Names
Do-D1 LE OE Oo-01
Description
Data Inputs Latch Enable Input (Active HIGH) Output Enable Input (Active LOW) TRI-STATE Latch Outputs
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loHllOL
1.0/1.0 1.0/1.0 1.0/1.0 150/40 (33.3)
20 �Al -0.6 mA 20 �A/-0.6 mA 20 �A/-0.6 mA -3 mA/24 mA (20 mA)
4-268
Functional Description
The 'F373 contains eight D-type latches with TRI-STATE output buffers. When the Latch Enable (LE) input is HIGH, data on the 0 0 inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The TRI-STATE buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are in the
bi-state mode. When OE is HIGH the buffers are in the high
impedance mode but this does not interfere with entering new data into the latches.
Truth Table
Inputs
LE
OE
Dn
H
L
H
H
L
L
L
L
x
x
H
x
H ~ HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance State
Logic Diagram
Do
Output
On
H L On (no change)
z
LE
07
TL/F/9523-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-269
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
-65�C to + 15o�c
Ambient Temperature under Bias
-55�C to+ 125�c
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5Vto +7.0V
Input Voltage (Note 2)
-0.5V to + 7.0V
Input Current (Note 2)
-30 mA to + 5.0 mA
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
-0.5VtoVee - 0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
ESD Last Passing Voltage (Min)
4000V
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�c
o�cto +1o�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol V1H V1L Veo VoH
VoL l1H lsv1 le EX V10 loo l1L lozH lozL las lzz leez
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee 74F5% Vee 74F5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH Current 54F 74F
Input HIGH Current 54F
Breakdown Test
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage
Test
74F
Output Leakage
Circuit Current
74F
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Bus Drainage Test
Power Supply Current
54F/74F Min Typ Max
2.0 0.8 -1.2
2.5 2.4 2.5 2.4 2.7 2.7
0.5 0.5
20.0 5.0
100 7.0
250 50
4.75
3.75
-0.6
50
-50
-60
-150
500
38
55
Units v v v
v
v �A �A �A v �A mA �A �A mA �A mA
Vee
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal Min l1N = -18mA loH = -1 mA loH = -3mA loH = -1 mA Min loH = -3mA �loH = -1 mA loH = -3mA Min loL = 20mA loL = 24mA
Max V1N = 2.7V
Max V1N = 7.0V
Max Your= Vee
0.0
0.0
Max Max Max Max o.ov Max
110 = 1.9 �A All Other Pins Grounded V100 = 150mV All Other Pins Grounded V1N = 0.5V Your= 2.7V Your= o.5V Your= ov Your= 5.25V Vo= HIGHZ
4-270
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
tPLH tpHL
tPLH tpHL
tpzH tpzL
tpHz tpLZ
Propagation Delay Dn to On Propagation Delay LE to On Output Enable Time
Output Disable Time
74F
TA= +25�c Vee= +5.0V
CL= 50 pF
Min
Typ
Max
3.0
5.3
7.0
2.0
3.7
5.0
5.0
9.0
11.5
3.0
5.2
7.0
2.0
5.0
11.0
2.0
5.6
7.5
1.5
4.5
6.5
1.5
3.8
5.0
54F
TA, Vee= Mii CL= 50pF
Min
Max
3.0
8.5
2.0
7.0
5.0
15.0
3.0
8.5
2.0
13.5
2.0
10.0
1.5
10.0
1.5
7.0
74F
TA, Vee= Com CL= 50 pF
Min
Max
3.0
8.0
2.0
6.0
5.0
13.0
3.0
8.0
2.0
12.0
2.0
8.5
1.5
7.5
1.5
6.0
Fig. Units
No.
ns 2-3 ns 2-3 ns 2-5 ns 2-5
AC Operating Requirements: see section 2 tor Waveforms
Symbol
Parameter
t5 (H) t5 (L)
th(H) th(L)
tw(H)
Setup Time, HIGH or LOW Dn to LE
Hold Time, HIGH or LOW On to LE
LE Pulse Width, HIGH
74F
TA= +25�c Vee= +5.0V
Min
Max
2.0 2.0
3.0 3.0
6.0
54F
TA, Vee= Mil
Min
Max
2.0 2.0
3.0 4.0
6.0
74F
TA, Vee= Com
Min
Max
2.0 2.0
3.0 3.0
6.0
Units Fig. No.
ns
2-6
ns
2-4
4-271
D~NaStemiicoonndauclto.r
54F/74F374
Octal D-Type Flip-Flop with TRI-STATE� Outputs
General Description
The 'F374 is a high-speed, low-power octal D-type flip-flop featuring separate D-type inputs for each flip-flop and TRI-STATE outputs for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all flip-flops.
Features
� Edge-triggered D-type inputs � Buffered positive edge-triggered clock � TRI-STATE outputs for bus-oriented applications � Guaranteed 4000V minimum ESD protection
Ordering Code: see section 5 Logic Symbols
CP OE
TL/F/9524-1
IEEE/I EC
OE
CP
Do
Oo
D1
01
D2
02
D3
03
D4
04
Ds
05
D5
05
0,
07
TL/F/9524-4
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
OE 1
Oo 2 Do 3 D1
o, 5
02 6 D2 7 D3
03 GND 10
20 Vee 19 07
18 0,
17 D5 16 05 15 05 14 D5 13 D4 12 04 11 CP
Pin Assignment for LCC
o~oDmz m02 ron, rDn1
G~~:o~~:
CP [j]
[I] OE
04 [i]
~Vee
D4 [j]J
l!fil07
li]!rnll]JliZJ[rnJ
Ds Os 05 Os 0,
TL/F/9524-3
TL/F/9524-2
Unit Loading/Fan Out: See Section 2 for U.L. Definitions
Pin Names
Description
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loHllOL
Do-D1 CP OE Oo-01
Data Inputs Clock Pulse Input (Active Rising Edge) TRI-STATE Output Enable Input (Active LOW) TRI-STATE Outputs
1.0/1.0 1.0/1.0 1.0/1.0 150/40 (33.3)
20 �A/ -0.6 mA 20 �A/ -0.6 mA 20 �A/-0.6 mA -3 mA/24 mA (20 mA)
4-272
Functional Description
The 'F374 consists of eight edge-triggered flip-flops with individual D-type inputs and TRI-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flipflops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the
OE input does not affected the state of the flip-flops.
Logic Diagram
Truth Table
Inputs
Dn
CP
OE
H
..../
L
L
..../
L
x
x
H
Internal Register
H L
x
H = HIGH Voltage Level
L = LOW Voltage Level X = Immaterial Z = High Impedance
../" = LOW-to-HIGH Clock Transition
Output
On H L
z
CP
TL/F/9524-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-273
Absolute Maximum Ratings (Note 1>
If MilitaryI Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vcc Pin Potential to Ground Pin
-0.5V to+ 7.0V
Input Voltage (Note 2)
-0.5V to + 7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
-0.5Vto Vee - 0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
ESD Last Passing Voltage (Min)
4000V
Note 1: Absolute maximum ratings are valu.es beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit cir current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol V1H V1L Vco VoH
Vm l1H lsv1 lcEx V10 loo l1L lozH lozL los lzz lccz
�Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee 74F5% Vee 74F5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage
Test
74F
Output Leakage
Circuit Current
74F
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Bus Drainage Test
Power Supply Current
54F/74F
Min Typ Max
2.0
0.8 -1.2
2.5 2.4 2.5 2.4 2.7 2.7
0.5 0.5
20.0 5.0 100 7.0
250 50
4.75
3.75
-0.6
50
-50
-60
-150
500
55
86
Units
v v
v
v
v
�A
�A
�A
v
�A mA �A �A mA �A mA
Vee
Min
Min
Min Max Max Max 0.0 0.0 Max Max Max Max
o.ov
Max
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal l1N = -18 mA loH = -1 mA loH = -3 mA loH = -1 mA loH = -3mA loH = -1 mA loH = -3mA loL = 20mA Im= 24mA V1N = 2.7V
V1N = 7.0V
VouT =Vee
110 = 1.9 �A All Other Pins Grounded V100 = 150 mV All Other Pins Grounded V1N = 0.5V VouT = 2.7V VouT = 0.5V
VouT = ov
VouT = 5.25V Vo= HIGHZ
4-274
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
fmax
tPLH tPHL
tpzH tpzL
tpHz tpLz
Maximum Clock Frequency Propagation Delay CPtoOn Output Enable Time
Output Disable Time
74F
TA= +25�C Vee= +5.0V
CL= 50 pf
Min
Typ
Max
100
140
4.0
6.5
8.5
4.0
6.5
8.5
2.0
9.0
11.5
2.0
5.8
7.5
2.0
5.3
7.0
1.5
4.3
5.5
54F
TA, Vee= Mil CL= 50 pf
Min
Max
60
4.0
10.5
4.0
11.0
2.0
14.0
2.0
10.0
2.0
8.0
1.5
7.5
74F
TA, Vee= Com CL= 50pf
Min
Max
70
4.0
10.0
4.0
10.0
2.0
12.5
2.0
8.5
2.0
8.0
1.5
6.5
Fig. Units
No. MHz 2-1 ns 2-3
ns 2-5
AC Operating Requirements: See Section 2 for Waveforms
Symbol
Parameter
t5 (H) t 5 (L)
th(H) th(L)
tw(H) tw(L)
Setup Time, HIGH or LOW Dn to CP
Hold Time, HIGH or LOW DntoCP
CP Pulse Width HIGH or LOW
74F
TA= +25�C Vee= +s.ov
Min
Max
2.0 2.0
2.0 2.0
7.0 6.0
54F
TA, Vee= Mil
Min
Max
2.5 2.0
2.0 2.5
7.0 6.0
74F
TA, Vee= Com
Min
Max
2.0 2.0
2.0 2.0
7.0 6.0
Fig. Units
No.
ns
2-6
ns
2-4
4�275
D~NaStemiicoonnduactlor
54F/74F377
Octal D Flip-Flop with Clock Enable
General Description
The 'F377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW.
The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q out-
put. The CE input must be stable only one setup time prior
to the LOW-to-HIGH clock transition for predictable operation.
Features
� Ideal for addressable register applications � Clock enable for address and data synchronization
applications � Eight edge-triggered D flip-flops � Buffered common clock � See 'F273 for master reset version � See 'F373 for transparent latch version � See 'F374 for TRI-STATE� version � Guaranteed 4000V minimum ESD protection
Ordering Code: see sections Logic Symbols
Do D, Dz D3 D, D5 D5 ~ CP CE
o, Oo 01 02 03 05 05 07
TL/F/9525-1
I E E E / I EC
CE
CP
Do
Oo
o,
o,
02
02
03
03
o,
o,
05
05
05
05
~
07
TLIF /9525-4
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
CE
Oo 2 Do 3 D1 4 01 5 02 6 D2 7 03 8
03 GND 10
20 Vee 19 07 18 ~ 17 05 16 05 15 05 14 05
13 o,
12 o,
11 CP
TL/F/9525-2
Pin Assignment for LCC
% Dz 02 o, 01 l!HIJ III IID III
03 [[]
GNO [QJ CP (j]
o, Im o, Ii]
rno0
moo
OJCE
~Vee ~07
~Ml[�] ffZI [ID
Ds0505Dg~
TL/F/9525-3
4-276
Unit Loading/Fan Out: See Section 2 for U.L. definitions
Pin Names
Do-D7
CE
CP Oo-01
Description
Data Inputs Clock Enable (Active LOW) Clock Pulse Input Data Outputs
54F/74F
U.L
HIGH/LOW
Input l1Hll1L Output loHllOL
1.0/1.0 1.0/1.0 1.0/1.0 50/33.3
20 �Al -0.6 mA 20 �A/ -0.6 mA 20 �A/ - 0.6 mA -1 mA/20mA
Operating Mode
Load "1" Load "O" Hold (Do Nothing)
Mode Select-Function Table
Inputs
CP
CE
Dn
....r
I
h
....r
I
I
....r
h
x
x
H
x
Output
On H L No Change No Change
H = HIGH Voltage Level h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH Clock Transition L = LOW Voltage Level I = LOW Voltage Level one setup time prior to the LOW-to-HIGH Clock Transition X = Immaterial .../" = LOW-to-HIGH Clock Transition
Logic Diagram
CP
o,
Oz
07
TL/F/9525-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-277
Absolute Maximum Ratings (Note 1>
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 1so�c
Ambient Temperature under Bias
- 55�C to + 125�c
Junction Temperature under Bias
- 55�C to + 11s�c
Vee Pin Potential to Ground Pin
-0.5Vto +7.0V
Input Voltage (Note 2)
-0.5Vto +7.0V
Input Current (Note 2)
-30 mA to + 5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
-0.5VtoVee -0.5V to+ 5.5V
Current Applied to Output in LOW State (Max)
ESD Last Passing Voltage (Min)
twice the rated Im (mA) 4000V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free ;\ir Ambient Temperature Military Commercial
- 55�c to + 125�c
o�cto +1o�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
V1H V1L Veo VoH
Vol
l1H lsv1
l1L los leEX V10
loo
leeH leeL
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 74F 10% Vee 74F5% Vee
Output LOW Voltage
54F10% Vee 74F 10% Vee
Input HIGH Current
Input HIGH Current Breakdown Test
Input LOW Current
Output Short-Circuit Current
Output HIGH Leakage Current
Input Leakage Test
Output Leakage Circuit Current
Power Supply Current
54F/74F Min Typ Max 2.0
0.8 -1.2 2.5 2.5 2.7 0.5 0.5 5.0
7.0
-0.6
-60
-150
50
4.75
3.75
35
46
44
56
Units
v v v
v
v �A �A mA mA �A
v
�A
mA
Vee
Min Min
Min Max Max Max Max Max 0.0 0.0 Max
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal l1N = -18 mA loH = -1 mA loH = -1 mA loH = -1 mA loL = 20 mA loL = 20 mA V1N = 2.7V V1N = 7.0V
V1N = 0.5V VouT =av VouT =Vee 110 = 1.9 �A All Other Pins Grounded V100 = 150 mV All Other Pins Grounded CP=..../ Dn =MR= HIGH
4-278
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
fMax
Maximum Clock Frequency
tpLH
Propagation Delay
tPHL
CPtoOn
74F
TA= +25�C Vee= +5.0V
CL= 50 pF
Min
Typ
Max
130
3.0
7.0
4.0
9.0
54F
TA, Vee= Mil CL= 50 pF
Min
Max
85
2.0
8.5
3.0
10.5
74F
TA, Vee= Com CL= 50 pF
Min
Max
105
2.5
7.5
3.5
9.0
Fig. Units
No.
MHz 2-1 ns 2-4
AC Operating Requirements: See Section 2 for Waveforms
Symbol
Parameter
t 5 (H) t 5 (L)
th(H) th(L)
t 5 (H) t 5 (L)
th(H) th(L)
tw(H) tw(L)
Setup Time, HIGH or LOW Dn to CP
Hold Time, HIGH or LOW Dn toCP
Setup Time, HIGH or LOW CEtoCP
Hold Time, HIGH to LOW CEtoCP
Clock Pulse Width, HIGH or LOW
74F
TA= +25�C Vee= +s.ov
Min
Max
3.0 3.5
0.5 1.0
4.1 3.5
0.5 2.0
6.0 6.0
54F
TA, Vee= Mil
Min
Max
3.5 4.0
1.0 1.0
4.0 5.0
1.5 2.5
5.0 5.0
74F
TA, Vee= Com
Min
Max
3.0 3.5
0.5 1.0
4.1 4.0
0.5 2.0
6.0 6.0
Fig. Units
No.
ns
2-6
ns
2-6
ns
2-6
ns
2-6
ns
2-4
4-279
~National
~Semiconductor
54F/74F378
Parallel D Register with Enable
General Description
The 'F378 is a 6-bit register with a buffered common Enable. This device is similar to the 'F174, but with common Enable rather than common Master Reset.
Features
� 6-bit high-speed parallel register � Positive edge-triggered D-type inputs � Fully buffered common clock and enable inputs � Input clamp diodes limit high-speed termination effects � Full TTL and CMOS compatible
Ordering Code: see sections
Logic Symbols
CP TL/F/9526-1
IEEE/I EC
CP
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
1
Oo 2 Do 3 D, 4
o, 5
D2 6 02 7 GND 8
16 Vee 15 05 14 Ds 13 D4 12 04 11 D3 10 03 9 CP
TL/F/9526-2
Pin Assignment forLCC
~
rn:i
m01 oNoC
rDn1
rDno
02 [!] GND [QI NC [i]
CP !ill 03 lrn
rnoo
!IIE
[I]NC ~Vee
liID05
[j]J~li]]liZJ[ID
~ 04 NC D4 Os
TL/F/9526-3
Do
Oo
D,
o,
D2
02
D3
03
D4
04
Ds
05
TL/F /9526-4
Unit Loading/Fan Out: See Section 2 tor u.L. Definitions
54F/74F
Pin Names
Description
U.L.
Input l1Hll1L
HIGH/LOW Output loHllOL
E
Enable Input (Active LOW)
1.0/1.0 20 �A/ -0.6 mA
Do-Ds CP
Data Inputs
1.0/1.0 20 �Al -0.6 mA
Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 �Al -0.6 mA
Oo-Os
Outputs
50/33.3 -1 mA/20 mA
4-280
Functional Description
The 'F378 consists of six edge-triggered D-type flip-flops
a with individual D inputs and inputs. The Clock (CP) and
Enable (E) inputs are common to all flip-flops.
When the E input is LOW, new data is entered into the
register on the LOW-to-HIGH transition of the CP input.
When the E input is HIGH the register will retain the present
data independent of the CP input.
Logic Diagram
Truth Table
Inputs
E
CP
Dn
H
_r
x
L
_r
H
L
_r
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
_r = LOW-to-HIGH Clock Transition
Output
On No Change
H L
"- CP
~
Jl CP D
~E
0
_o_
CP D r-- E
0
_j:>_ CP D .---I E
0
_o_
CP D
~E
0
Jl CP D
r- E 0
Jl CP D
r- E 0
TL/F/9526-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-281
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
-65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5Vto +7.0V
Input Voltage (Note 2)
-0.5Vto +7.0V
Input Current (Note 2)
-30 mA to + 5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5V to Vee -0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
V1H
Input HIGH Voltage
V1L
Input LOW Voltage
Veo
Input Clamp Diode Voltage
54F/74F Min Typ Max
Units Vee
Conditions
2.0
v
Recognized as a HIGH Signal
0.8
v
Recognized as a LOW Signal
-1.2
v
Min l1N = -18 mA
VoH
Output HIGH
Voltage
54F 10% Vee 2.5
74F 10% Vee 2.5
74F 5%Vee
2.7
loH = -1 mA
v
Min loH = -1 mA
loH = -1 mA
VoL
Output LOW
Voltage
54F 10% Vee 74F 10% Vee
0.5
v
Min loL = 20 mA
0.5
loL = 20 mA
l1H
Input HIGH
54F
Current
74F
20.0
�A
Max V1N = 2.7V
5.0
lsv1
Input HIGH Current 54F
Breakdown Test
74F
100
V1N = 7.0V
7.0
�A Max
leEX
Output HIGH
54F
Leakage Current
74F
250 50
�A
Max VouT =Vee
V10
Input Leakage
74F
Test
4.75
v
0.0 110 = 1.9 �A
All Other Pins Grounded
loo
Output Leakage
74F
Circuit Current
3.75
�A
0.0 V100 = 150mV All Other Pins Grounded
l1L
Input LOW Current
las
Output Short-Circuit Current
-0.6 mA Max V1N = 0.5V
-60
ov -150 mA Max VouT =
leeL
Power Supply Current
30
45
mA Max Vo= LOW
4-282
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
fmax
tPLH tPHL
Maximum Input Frequency
Propagation Delay GP to On
74F
TA= +25�c Vee= +5.0V
CL= 50 pF
Min
Typ
Max
80
100
3.0
5.5
7.5
3.5
6.0
8.5
54F
TA, Vee= Mil CL= 50 pF
Min
Max
70
3.0
10.0
3.5
10.5
74F
TA, Vee= Com CL= 50 pF
Min
Max
80
3.0
8.5
3.5
9.5
Fig. Units No.
MHz 2-1 ns 2-3
AC Operating Requirements: See Section 2 for Waveforms
Symbol
Parameter
t 5 (H) t 5 (L)
th(H) th(L)
t 5 (H) t 5 (L)
th(H) th(L)
tw(H) tw(L)
Setup Time, HIGH or LOW DntoCP
Hold Time, HIGH or LOW Dn toCP
Setup Time, HIGH or LOW EtoCP
Hold Time, HIGH or LOW EtoCP
CP Pulse Width HIGH or LOW
74F
TA= +25�c Vee= +5.0V
Min
Max
4.0 4.0
0 0
6.0 10.0
0 0
4.0 6.0
54F
TA, Vee= Mil
Min
5.0 5.0
2.0 2.0
4.5 13.0
0 0
5.0 7.5
Max
74F
TA, Vee= Com
Min
Max
4.0 4.0
0 0
6.0 10.0
0 0
4.0 6.0
Fig. Units No.
ns
2-6
ns
2-6
ns
2-4
4-283
U~NaStemiicoonnduactlor
54F/74F379
Quad Parallel Register with Enable
General Description
The 'F379 is a 4-bit register with buffered common Enable. This device is similar to the 'F175 but features the common Enable rather than common Master Reset.
Features
� Edge triggered D-type inputs � Buffered positive edge-triggered clock � Buffered common enable input
� True and complement outputs � Guaranteed 4000V minimum ESD protection
Ordering Code: see section 5 Logic Symbols
I E E E / I EC
CP
Do
Oo
Oo
o,
D1 01
Oz Dz
Oz
03 D3
03
TL/F/9527-5
Connection Diagrams
Pin Assignment DIP, SOIC and Flatpak
Oo 2 Oo Do 4 D1 5 01 6
o, 7
GND 8
16 Vee
15 03 14 03 13 D3 12 Dz 11 Oz 10 Oz 9 CP
TL/F/9527-1
Pin Assignment forLCC
01 D1 NC Do 0o
[[][f]([J[fillJ]
01 [[] GND [QI
NC [j] CP l!1]
Oz !LlJ
rrnnoE0
O]NC
~Vee li]J03
Ii] Ii] [�] [Z] [ID
Oz~NCDJ03
TL/F/9527-2
Do D1 D2 D3 CP
TL/F/9527-3
Unit Loading/Fan Out: See Section 2 for U.L. Definitions
54F/74F
Pin Names
Description
U.L.
Input l1Hll1L
HIGH/LOW Output loHlloL
E
Do-D3 CP Oo-03 Oo-03
Enable Input (Active LOW) Data Inputs Clock Pulse Input (Active Rising Edge) Flip-Flop Outputs Complement Outputs
1.0/1.0 1.0/1.0 1.0/1.0 50/33.3 50/33.3
20 �A/-0.6 mA 20 �Al-0.6 mA 20 �Al -0.6 mA -1 mA/20 mA -1 mA/20 mA
4-284
Functional Description
The 'F379 consists of four edge-triggered D-Type flip-flops with individual D inputs and Q and Q outputs. The Clock
(CP) and Enable (E) inputs are common to all flip-flops.
When the Eis input HIGH, the register will retain the present data independent of the CP input. The Dn and E inputs can change when the clock is in either state, provided that the recommended setup and hold times are observed.
Truth Table
Inputs
E
CP
Dn
H
__r
x
L
__r
H
L
__r
L
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial J"' = LOW-to-HIGH Transition NC = No Change
Logic Diagram
Do
D1
Dz
CP
CP
CP
CP
D
Q
Q
Q
Q
0
Q
Outputs
On
On
NC
NC
H
L
L
H
D3
CP
Q
0
01
01
TL/F/9527-4 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-285
Absolute Maximum Ratings (Note 1)
If MilitaryI Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
-65�C to + 15o�c
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to + 7.0V
Input Voltage (Note 2)
-0.5Vto +7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5VtoVee -0.5Vto +5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
ESD Last Passing Voltge (Min)
4000V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�c o�cto +10�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
V1H
Input HIGH Voltage
V1L
Input LOW Voltage
Yeo
Input Clamp Diode Voltage
VoH
Output HIGH
Voltage
54F 10% Vee 74F 10% Vee 74F 5%Vee
VoL
Output LOW
Voltage
54F 10% Vee 74F 10% Vee
l1H
Input HIGH
54F
Current
74F
lsv1
Input HIGH Current 54F
Breakdown Test
74F
le EX
Output HIGH
54F
Leakage Current
74F
V10
Input Leakage
74F
Test
loo
Output Leakage
Circuit Current
74F
l1L
Input LOW Current
los
Output Short-Circuit Current
leeL
Power Supply Current
54F/74F Min Typ Max 2.0
0.8 -1.2 2.5 2.5 2.7 0.5 0.5 20.0 5.0 100 7.0 250
50
4.75
-60 28
3.75
-0.6 -150
40
Units v v v v
v
�A �A �A v �A mA mA mA
Vee
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal Min l1N = -18 mA loH = -1 mA Min loH = -1 mA loH = -1 mA Min loL = 20 mA loL = 20 mA Max V1N = 2.7V
Max V1N = 7.0V
Max VouT =Vee
0.0 110 = 1.9 �A All Other Pins Grounded
0.0 V100 = 150mV All Other Pins Grounded
Max V1N = 0.5V Max VouT = ov Max Vo= LOW
4-286
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
fmax
tPLH tPHL
Maximum Clock Frequency
Propagation Delay CPtoOn,On
74F
TA= +25�C Vee= +5.0V
CL= 50 pf
Min
Typ
Max
100
140
3.5
5.0
6.5
5.0
6.5
8.5
54F
TA, Vee= Mii CL= 50 pf
Min
Max
75
3.0
8.5
4.0
10.0
74F
TA, Vee= Com CL= 50pF
Min
Max
100
4.0
7.5
5.0
9.5
Units Fig. No.
MHz 2-1 ns 2-3
AC Operating Requirements: See Section 2 for Waveforms
Symbol
Parameter
t5 (H) t 5 (L)
th(H) th(L)
t5(H)
t 5 (L)
th(H) th(L)
tw(H) tw(L)
Setup Time, HIGH or LOW Dn toCP
Hold Time, HIGH or LOW DntoCP
Setup Time, HIGH or LOW EtoCP
Hold Time, HIGH or LOW EtoCP
CP Pulse Width HIGH or LOW
74F
TA= +25�C Vee= +5.0V
Min
Max
3.0 3.0
1.0 1.0
6.0 6.0
0 0
4.0 5.0
54F
TA, Vee= Mil
Min
Max
4.0 4.0
2.0 2.0
8.0 8.0
0 0
5.0 7.0
74F
TA, Vee= Com
Min
Max
3.0 3.0
1.0 1.0
6.0 6.0
0 0
4.0 5.0
Units Fig. No.
ns
2-6
ns
2-'6
ns
2-4
a
4-287
~National
~Semiconductor
54F/74F381
4-Bit Arithmetic Logic Unit
General Description
The 'F381 performs three arithmetic and three logic operations on two 4-bit words, A and B. Two additional select input codes force the function outputs LOW or HIGH. Carry propagate and generate outputs are provided for use with the 'F182 carry lookahead generator for high-speed expansion to longer word lengths. For ripple expansion, refer to the 'F382 ALU data sheet.
Features
� Low input loading minimizes drive requirements � Performs six arithmetic and logic functions � Selectable LOW (clear) and HIGH (preset) functions � Carry generate and propagate outputs for use with
carry lookahead generator
Ordering Code: See sections Logic Symbols
Cn Ao Bo A1 81 A2 82 A3 83
S2 S1 So ro r1 r2 F3
TL/F/9526-3
IEEE/I EC
So
s,
}~ ALU
52
(1/2/3)CP
(1/2)81 (1/2/3)CG
Ci
en
Ao
f'o Bo
A1
(2)
r1
81
A2
p (4)
B2
Q
r2
A3
p (8)
f'3
83
Q
TL/F/9526-6
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
A1 81 2
Ao 3
Bo 4 So 5 S1 6 S2 7 ro 8 r1 9 GND 10
20 Vee 19 A2 18 82 17 A3 16 83
15 en 14 p 13 G
12 r3 11 F2
TL/F /9526-1
Pin Assignment for LCC
rrno rSzi:mS1:rSnornBJo
r1m
GND [QI
r2 [l]
r3 irn
GH]
CTlAo illB 1
ITJA1 ~Vee
!IfilA2
IJ]J H]J [�] fj1J [ID P~B3A392
TL/F/9526-2
4-288
w
Unit Loading/Fan Out: See Section 2 for U.L. definitions
.C..D...
Pin Names
Description
54F/74F
U.L.
Input l1Hll1L
HIGH/LOW Output loHlloL
Ao-A3 Bo-83 So-S2 Cn
G p
Fo-Fs
A Operand Inputs B Operand Inputs Function Select Inputs Carry Input Carry Generate Output (Active LOW) Carry Propagate Output (Active LOW) Function Outputs
1.0/3.0 1.0/3.0 1.0/1.0 1.0/4.0 50/33.3 50/33.3 50/33.3
20 �A/-1.8 mA 20 �A/-1.8 mA 20 �A/ - 0.6 mA 20 �A/ - 2.4 mA -1 mA/20mA
-1 mA/20mA -1 mA/20mA
Functional Description
Signals applied to the Select inputs So-S2 determine the mode of operation, as indicated in the Function Select Table. An extensive listing of input and output levels is shown in the Truth Table. The circuit performs the arithmetic functions for either active HIGH or active LOW operands, with output levels in the same convention. In the Subtract operating modes, it is necessary to force a carry (HIGH for.active
HIGH operands, LOW for active LOW operands) into the Cn input of the least significant package.
The Carry Generate (G) and Carry Propagate (P) outputs supply input signals to the 'F182 carry lookahead generator for expansion to longer word length, as shown in Figure 1. Note that an 'F382 ALU is used for the most significant package. Typical delays for Figure 1 are given in Figure 2.
Function Select Table
Select
So
S1
S2
L
L
L
H
L
L
L
H
L
H
H
L
Operation
Clear B Minus A AMinusB A Plus B
L
L
H
L
L
H
H
H
H = HIGH Voltage Level
L = LOW Voltage Level
H
AEllB
H
A+B
H
AB
H
Preset
FIGURE 2. 16-Bit Delay Tabulation
Path Segment
Ai or'Bi to P Pi to Cn + j ('F182) CntoF Cn orCn + 4, OVR Total Delay
Toward F
7.2 ns 6.2 ns 8.1 ns
-
21.5 ns
Output Cn + 4,0VR
7.2 ns 6.2 ns
-
8.0 ns
21.4 ns
'f'182 Cl.A
FIGURE 1. 16-Blt Lookahead Carry ALU Expansion
Cour OVERFLOW
TL/F/9528-4
4-289
'I"'"
~ Logic Diagram
~~~~~~~~~~~~~~~~~~~~~~~~---.
Bo~~~. . . .~~~~=�'----'~'
D-r3 A3
IOrNnL�Y }TM'ONLY
c...
TL/F/9528-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-290
Truth Table
Inputs
Outputs
Function
So
51
52
Cn
An
Bn
Fo
F1
F2
Fa
G
p
CLEAR
L
L
L
x
x
x
L
L
L
L
L
L
L
L
L
H
H
H
H
H
L
L
L
H
L
H
H
H
L
L
L
H
L
L
L
L
L
H
H
L
H
H
H
H
H
H
H
L
B Minus A
H
L
L
H
L
L
L
L
L
L
H
L
H
L
H
H
H
H
H
L
L
H
H
L
H
L
L
L
H
H
H
H
H
L
L
L
L
H
L
L
L
L
H
H
H
H
H
L
L
L
H
L
L
L
L
H
H
L
H
L
L
H
H
H
L
L
A Minus B
L
H
L
L
H
H
H
H
H
H
H
L
H
L
L
L
L
L
L
H
L
H
L
H
H
L
L
L
H
H
H
H
L
H
H
H
H
L
L
H
H
H
L
L
L
L
H
L
A Plus B
L
L
L
L
L
L
L
H
H
L
L
H
H
H
H
H
H
L
L
H
L
H
H
H
H
H
L
H
H
L
L
H
H
L
H
H
H
L
L
H
L
L
H
L
L
L
H
H
H
L
H
L
L
L
L
H
L
H
H
L
L
L
L
L
H
L
H
H
H
H
H
H
H
L
L
A$ B
x
L
L
L
L
L
L
H
H
x
L
H
H
H
H
H
H
H
L
L
H
x
H
L
H
H
H
H
H
L
x
H
H
L
L
L
L
L
L
A+B
x
L
L
L
L
L
L
H
H
x
L
H
H
H
H
H
H
H
H
L
H
x
H
L
H
H
H
H
H
H
x
H
H
H
H
H
H
H
L
x
L
L
L
L
L
L
L
L
x
L
H
L
L
L
L
H
H
AB
L
H
H
x
H
L
L
L
L
L
L
L
x
H
H
H
H
H
H
H
L
PRESET
x
L
L
H
H
H
H
H
H
x
L
H
H
H
H
H
H
H
H
H
H
x
H
L
H
H
H
H
H
H
x
H
H
H
H
H
H
H
L
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
4-291
.,..
co
CW) Absolute Maximum Ratings (Note 1)
If Miiitary/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
-65�C to + 15o�c
Ambient Temperature under Bias
- 55�C to + 125�c
Junction Temperature under Bias
- 55�C to + 175�C
Yee Pin Potential to Ground Pin
-0.5V to + 7.0V
Input Voltage (Note 2)
-0.5Vto +7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee= OV) Standard Output TRI-STATE� Output
-0.5VtoVcc -0.5V to + 5.5V
Current Applied to Output
in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
c.. 55�C to + 125�C o�cto +70�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
V1H V1L Vco VoH
VoL l1H lsv1 lcEx V10 loo l1L
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 74F 10% Vee 74F5%Vcc
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage 74F
Test
Output Leakage 74F
Circuit Current
Input LOW Current
los
Output Short-Circuit Current
Ice
Power Supply Current
54F/74F Min Typ Max 2.0
0.8 -1.2 2.5 2.5 2.7 0.5 0.5 20.0 5.0 100 7.0 250
50
4.75
3.75
-0.6 -1.8 -2.4
-60
-150
59
89
Units
v v v
v
v
�A
�A
�A
v
�A mA mA mA mA mA
Vee
Min Min
Min Max Max Max 0.0 0.0 Max Max Max Max Max
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal l1N = -18mA loH = -1 mA loH = -1 mA loH = -1 mA loL = 20mA loL = 20 mA V1N = 2.7V
V1N = 7.0V
Your= Vee
110 = 1.9 �A All Other Pins Grounded V100 = 150mV All Other Pins Grounded V1N = 0.5V (Sn) V1N = 0.5V (An, Bn) V1N = 0.5V (Cn) Your= ov
4-292
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
tPLH
Propagation Delay
tPHL
Cn to Fi
tPLH
Propagation Delay
tPHL
Any A or B to Any F
tPLH
Propagation Delay
tPHL
SitOFi
tPLH
Propagation Delay
tPHL
Ai or Bi to G
tPLH
Propagation Delay
tPHL
Ai or BitO p
tPLH
Propagation Delay
lPHL
SitoGorP
74F
TA= +25"C Yee= +5.0Y
CL= 50pF
Min
Typ
Max
2.5
8.1
12.0
2.5
5.7
8.0
4.0
10.4
15.0
3.5
8.2
11.0
4.5
8.3
20.5
4.0
8.2
15.0
3.5
6.4
10.0
3.5
6.8
10.0
2.5
7.2
10.5
3.5
6.5
9.5
4.0
7.8
12.0
4.5
10.2
13.5
54F
TA, Yee= Mii CL= 50pF
Min
Max
74F
TA, Vee= Com CL= 50pF
Min
Max
2.5
13.0
2.5
9.0
4.0
16.0
3.5
12.0
4.5
21.5
4.0
16.0
3.5
11.0
3.0
11.0
2.5
11.5
3.5
10.5
4.0
13.0
4.5
14.5
Units
Fig. No.
ns 2-3 ns 2-3 ns 2-3 ns 2-3 ns 2-3 ns 2-3
4-293
~~SNemaitcoinoduncatolr
54F/74F382
4-Bit Arithmetic Logic Unit
General Description
The 'F382 performs three arithmetic and three logic operations on two 4-bit words, A and B. Two additional Select input codes force the Function outputs LOW or HIGH. An Overflow output is provided for convenience in twos complement arithmetic. A Carry output is provided for ripple expansion. For high-speed expansion using a Carry Lookahead Generator, refer to the 'F381 data sheet.
Features
� Performs six arithmetic and logic functions � Selectable LOW (clear) and HIGH (preset) functions � LOW input loading minimizes drive requirements � Carry output for ripple expansion � Overflow output for twos complement arithmetic
Ordering Code: See Section 5 Logic Symbols
I E E E / I EC
f3 TL/F/9529-6
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
A1 81
Ao 3
" Bo
So S1 S2 7 fo f1 GND 10
20 Vee 19 A2 18 82 17 A3 16 83 15 Cn 14 cn+-4 13 OVR 12 f3 11 f2
TL/F/9529-1
Pin Assignment for LCC
fo Si S1 So Bo IIDIIl!IDIIJ[i]
c:~:o~~
f2 [j] f31i11
[I]A1 ~Vee
OVR [j]
[j]] A2
ll1l [j]J li]J Ii] Ii]]
~4~ 83 A3 8i
TL/F/9529-2
Cn Ao Bo A1 81 A2 Bz A3 83
Cn+4 OVR
TL/F/9529-3
4-294
Unit Loading/Fan Out: See Section 2 for U.L. definitions
Pin Names
Ao-A3 Bo-83 So-S2 Cn Cn + 4 OVA Fo-F3
Description
A Operand Inputs B Operand Inputs Function Select Inputs Carry Input Carry Output Overflow Output Function Outputs
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loHlloL
1.0/4.0 1.0/4.0 1.0/1.0 1.0/5.0 50/33.3 50/33.3 50/33.3
20 �Al - 2.4 mA 20 �Al - 2.4 mA 20 �A/ -0.6 mA 20 �Al - 3.0 mA -1 mA/20mA -1 mA/20mA -1 mA/20 mA
Functional Description
Signals applied to the Select inputs So-S2 determine the mode of operation, as indicated in the Function Select Table. An extensive listing of input and output levels is shown in the Truth Table. The circuit performs the arithmetic functions for either active HIGH or active LOW operands, with output levels in the same convention. In the Subtract operating modes, it is necessary to force a carry (HIGH for active HIGH operands, LOW for active LOW operands) into the Cn input of the least significant package. Ripple expansion is illustrated in Figure 1. The overflow output OVA is the Exclusive-OR of Cn + 3 and Cn + 4; a HIGH signal on OVA indicates overflow in twos complement operation. Typical delays for Figure 1 are given in Figure 2.
Function Select Table
Select
So
S1
S2
L
L
L
H
L
L
L
H
L
H
H
L
L
L
H
H
L
H
L
H
H
H
H
H
H = HIGH Voltage Level L = LOW Voltage Level
Operation
Clear B Minus A AMinusB A Plus B A$ B A+B AB Preset
A
B
C1H - - - - I H Cn F382 Cn +4 t - - - l M
s
FIGURE 1. 16-Bit Ripply Carry ALU Expansion
Path Segment
Toward F
Ai or Bi to Cn + 4 C0 tOCn+4 Cn toCn + 4 C0 to F Cn to Cn + 4, OVA
6.5 ns 6.3 ns 6.3 ns 8.1 ns
-
Total Delay
27.2 ns
FIGURE 2. 16-Blt Delay Tabulation
Output Cn + 4,0VR
6.Sns 6.3 ns 6.3ns
-
8.0ns
27.1 ns
Cour
OVERFLOW
TL/F/9529-5
4-295
Truth Table
Inputs
Outputs
Function CLEAR
So
S1
S2
Cn
An
Bn
Fo
F1
F2
F3
OVR
Cn + 4
L
L
L
L H
x
x
x x
L L
L L
L L
L L
H H
H H
BMINUSA
H
L
L
L
L
L
H
H
H
H
L
L
L
L
H
L
H
H
H
L
H
L
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
L
L
H
L
L
L
L
L
L
L
H
H
L
H
H
H
H
H
L
H
H
H
L
H
L
L
L
L
L
H
H
H
L
L
L
L
L
H
AMINUSB
L
H
L
L
L
L
H
H
H
H
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
H
H
H
L
H
L
H
H
H
H
H
H
L
L
H
L
L
L
L
L
L
L
H
H
L
H
H
L
L
L
L
L
H
H
L
H
H
H
H
L
H
H
H
H
L
L
L
L
L
H
APLUSB
H
H
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
L
L
L
H
L
H
H
H
H
L
L
L
H
H
L
H
H
H
L
H
H
L
L
H
L
L
L
L
L
H
L
H
L
L
L
L
L
H
H
H
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
H
AeB
L
L
H
x
L
L
L
L
L
L
L
L
x
L
H
H
H
H
H
L
L
L
H
L
H
H
H
H
L
L
x
H
H
L
L
L
L
H
H
H
H
L
H
H
H
H
H
H
A+B
H
L
H
x
L
L
L
L
L
L
L
L
x
L
H
H
H
H
H
L
L
x
H
L
H
H
H
H
L
L
L
H
H
H
H
H
H
L
L
H
H
H
H
H
H
H
H
H
AB
L
H
H
x
L
L
L
L
L
L
H
H
x
L
H
L
L
L
L
L
L
x
H
L
L
L
L
L
H
H
L
H
H
H
H
H
H
L
L
H
H
H
H
H
H
H
H
H
PRESET
H
H
H
x
L
L
H
H
H
H
L
L
x
L
H
H
H
H
H
L
L
x
H
L
H
H
H
H
L
L
L
H
H
H
H
H
H
L
L
H
H
H
H
H
H
H
H
H
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
4-296
Logic Diagram
c.-----------------------...
Bo---------""1_....r_
'F381 ONLY
D-ovR l'F382 ONLY S1
TL/F/9529-4 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-297
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
-65�C to + 15o�c
Ambient Temperature under Bias
- 55�c to + 125�C
Junction Temperature under Bias
-55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5Vto +7.0V
Input Voltage (Note 2)
-0.5V to+ 7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5VtoVee -0.5Vto +5.5V
Current Applied to Output
in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�c
o�cto +1o�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics over Operating Temperature Range unless otherwise specified
Symbol V1H V1L Veo VoH
Vol l1H lsv1 lcEX V10 loo l1L
lozH lozL las Ice
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 74F 10% Vee 74F5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage 74F
Test
Output Leakage 74F
Circuit Current
Input LOW Current
Output Leakage Current Output Leakage Current Output Short-Circuit Current Power Supply Current
54F/74F Min Typ Max 2.0
0.8 -1.2 2.5 2.5 2.7 0.5 0.5 20.0 5.0 100 7.0 250
50
4.75
3.75
-0.6 -1.8 -2.4
50
-50
-60
-150
54
81
Units v v v v
v �A �A �A v �A
mA �A �A mA mA
Vee
Min Min
Min Max Max Max 0.0 0.0
Max Max Max Max Max
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal l1N = -18 mA loH = -1 mA loH = -1 mA loH = -1 mA loL = 20 mA loL = 20mA V1N =:= 2.7V
V1N = 7.0V
Vour =Vee
110 = 1.9 �A All Other Pins Grounded V100 = 150 mV All Other Pins Grounded V1N = 0.5V (So-S2)
V1N = 0.5V (Ao-A3, Bo-B3)
V1N = 0.5V (Cn, Cn+4)
Vour = 2.7V Vour = 0.5V Vour = ov
4-298
AC Electrical Characteristics: see section 2 tor u.L. definitions
Symbol
Parameter
tPLH tPHL
tPLH tPHL
tpLH tPHL
tPLH tPHL
tpLH tPHL
tPLH tPHL
tPLH tPHL
tPLH tPHL
Propagation Delay Cnto Fi
Propagation Delay Any A or B to Any F
Propagation Delay Sito Fi
Propagation Delay
Ai or Bi to Cn + 4
Propagation Delay
Si to OVR or Cn + 4
Propagation Delay
Cn to Cn + 4
Propagation Delay CntoOVR
Propagation Delay Ai or Bi to OVR
74F
TA= +25�C Vee= +5.0V
CL= 50 pf
Min
Typ
Max
3.0
8.1
12.0
2.5
5.7
8.0
4.0
10.4
15.0
3.0
8.2
11.0
6.5
11.0
20.5
4.0
8.2
15.0
3.5
6.0
8.5
3.5
6.5
9.0
7.0
12.5
16.5
5.0
9.0
12.0
2.5
5.6
8.0
3.5
6.3
9.0
3.5
8.0
11.0
2.5
7.1
10.0
7.0
11.5
15.5
3.0
8.0
10.5
54F
TA, Vee= Mil CL= 50 pf
Min
Max
74F
TA, Vee= Com CL= 50 pf
Min
Max
3.0
13.0
2.5
9.0
3.5
17.0
2.5
12.0
5.5
21.5
4.0
17.5
3.5
11.0
3.5
10.5
7.0
17.5
5.0
14.5
2.0
9.0
2.0
10.0
3.5
13.0
2.5
11.0
7.0
16.5
3.0
11.5
Fig. Units
No.
ns
2-4
ns
2-4
ns
2-4
ns
2-4
ns
2-4
ns
2-4
ns
2-4
ns
2-4
4-299
~~SNemaitcoinoduncatolr
54F/74F384
8-Bit Serial/Parallel Twos Complement Multiplier
General Description
The 'F384 is an 8-bit by 1-bit sequential logic element that multiplies two numbers represented in twos complement notation. The device implements Booth's algorithm internally to produce a twos complement product that needs no subsequent correction. Parallel inputs accept and store an 8-bit multiplicand (Xo-X7). The multiplier word is then applied to the Y input in a serial bit stream, least significant bit first. The product is clocked out at the SP output, least significant bit first.
The K input is used for expansion to longer X words, using two or more 'F384 devices by connecting the output (SP) of one device to the K input of the other device. The Mode Control (M) input is used to establish the most significant
device. An asynchronous Parallel Load (PL) input clears the internal flip-flops to the start condition and enables the X latches to accept new multiplicand data. The Parallel Load (PL) also clears the output (SP).
Features
� Twos complement multiplication � 8-bit by 1-bit sequential logic element � Parallel inputs accept and store an 8-bit multiplicand
(Xo-X7) � K input is used for expansion to longer X words � Functionally and pin compatible to the Am25LS14A
Ordering Code: See Sections Logic Symbol
Connection Diagrams
y PL X7 Xg X5 X4 X3 X2 X1 Xo M
CP
SP
TL/F/10217-1
Pin Assignment for DIP and SOIC
PC
X3 X2
x,
Xo SP CP 7 GND 8
16 Vee 15 y
14 X4 13 X5 12 Xg 11 X7 10 K
9 M
TL/F/10217-2
Pin Assignment
for LCC
SP
oo
Xo NC
m[�'.]
rXn1
X2
rn
G~~~o~~
NC !Ill
[j]NC
Mli1]
~Vee
K Im
[ID Y
!Bl Ii] [�! [Z] [�I X7 Xg NC Xs X4
TL/F/10217-3
Input Loading/Fan-Out: see section 2 For u.L. Definitions
Pin Names
CP K M PL Xo-X7 y
SP
Description
Clock Pulse Input (Active Rising Edge) Serial Expansion Input Mode Control Input Asynchronous Parallel Load Input (Active LOW) Multiplicand Data Inputs Serial Multiplier Input Serial X�Y Product Output
54F/74F (U.L.) High/Low
1.0/1.0 1.0/1.0 1.0/1.0 1.0/2.0 1.0/1.0 1.0/1.0 50/33.3
l1Hll1L loHllOL
20 �A/ -0.6 mA 20 �A/-0.6 mA 20 �A/-0.6 mA 20 �A/-1.2 mA 20 �A/ -0.6 mA 20 �A/ -0.6 mA
-1 mA/20mA
4-300
Functional Description
Referring to the Logic Diagram and Figure A, the multiplicand (Xo-X7) latches are enabled to receive new data when PL is LOW. Data that meet the setup/hold time requirements are stored when PL goes HIGH. The LOW signal on PL clears the output (SP) as well as the internal flip-flops.
New multiplicand data enter the X latches during bit time T0. It is assumed that PL goes LOW shortly after the CP rising edge that marks the beginning of To and goes HIGH again one recovery time before the beginning of T1. The LSB (Yo) of the multiplier is applied to the Y input during T0 and must be held one hold time after the beginning of T1. One propagation delay after the beginning of T1, the LSB (So) of the product appears at the output (SP). This multiplication process is continued by applying Y1- Y6 to the Y input causing S1 -Ss of the product to appear at the output (SP).
Logic Diagram
The MSB Y7 (the sign bit) of the multiplier is first applied to the Y input during T1 and must be held through T16 causing S7-S15 of the product to appear at the output (SP). This extension of the sign bit is a necessary adjunct to the implementation of Booth's algorithm. This is a built-in feature of the 'F322 Shift Register (See Figure 8 ).
Figure C shows the method of using two F384's to perform a 12 x n bit multiplication. Notice that the sign of X is effectively extended by connecting X11 to X4-X7 of the most significant package. Whereas the 8 x 8 multiplication re-
quired 17 clock periods (m + n to form the product terms
plus T0 to clear the multiplier), the arrangement of Figure C
requires 12 + n + 1 bits to form the product terms.
CLOCK (CP)
AODER/SUBTRACTOR AND REGISTERS
CP
SUM
SP
TL/F/10217-4 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Inputs
PL CP
K
M
X1
x
x
L
L
x
x x cs H x
L
x
x
x OP
H
x
x
x x
H
t
x x x
H
t
x xx
H
t
xx x
H
t
x x x
H = HIGH Voltage Level
L = LOW Voltage Level
t = LOW-to-HIGH Transition
CS = Connected to SP output of high order device OP = Xi latches open for new data (i = 0-7) AR = Output as required per Booth's algorithm X = Immaterial
Function Table
Internal
Output
y
Ya-1
SP
x
x
x
x x
x
x
L
L
x
x
x
L
L
AR
L
H
AR
H
L
AR
H
H
AR
Function
Most Significant Multiplier Device Devices Cascaded in Multiplier String Load New Multiplicand and Clear Internal Sum and Carry Registers Device Enabled Shift Sum Register Add Multiplicand to Sum Register and Shift Subtract Multiplicand from Sum Register and Shift Shift Sum Register
4-301
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�c
Ambient Temperature under Bias
-55�C to+ 125�c
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5Vto +7.0V
Input Voltage (Note 2)
-0.5V to + 7.0V
Input Current (Note 2)
-30 mA to + 5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5VtoVee - 0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit Is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�cto +7CJ'C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
V1H
Input HIGH Voltage
V1L
Input LOW Voltage
Yeo
Input Clamp Diode Voltage
54F/74F Min Typ Max 2.0
0.8 -1.2
Units Vee
Conditions
v
Recognized as a HIGH Signal
v
Recognized as a LOW Signal
v
Min l1N = -18 mA
VoH
Output HIGH
Voltage
54F 10% Vee 2.5
74F 10% Vee 2.5
74F5%Vee
2.7
loH = -1 mA
v
Min loH = -1 mA
loH = -1 mA
VoL
Output LOW
Voltage
54F 10% Vee 74F 10% Vee
0.5
v
Min loL = 20mA
0.5
loL = 20mA
l1H
Output HIGH
54F
Current
74F
20.0 5.0
�A Max V1N = 2.7V
lsv1
Input HIGH Current 54F
Breakdown Test
74F
100
7.0
�A Max V1N = 7.0V
le EX
Output HIGH
54F
Leakage Current
74F
250
50
�A Max Your= Vee
V10
Input Leakage
74F
4.75
Test
v
0.0 IJD = 1.9 �A
All Other Pins Grounded
loo
Output Leakage
Circuit Current
74F
3.75
�A
0.0 V100 = 150 mV
All Other Pins Grounded
l1L
Input LOW Current
los
Output Short-Circuit Current
-0.6 mA Max V1N = 0.5V (Except PL)
-1.2
mA
Max V1N = 0.5V (PL)
-60
-150 mA Max Your= ov
lee
Power Supply Current
60
90
mA Max Vo= HIGH
4-302
AC Electrical Characteristics : See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
fmax
Maximum Clock Frequency
tPLH
Propagation Delay
tPHL
CPtoSP
tPHL
Propagation Delay
PL to SP
54F/74F
TA= +25�C Vee= +5.0V
CL= 50pf
Min Typ Max
50
3.5
6.5
9.0
3.5
6.5
9.0
6.0 10.0 13.0
54F
TA, Vee= Mii
CL= 50 pf
Min Max
74F
TA, Vee= Com
CL= 50pf
Units
Fig. No.
Min Max
50
MHz 2-1
3.5 10.0 3.5 10.0
ns
2-3
6.0 14.0
ns
2-3
AC Operating Requirements : See Section 2 for waveforms
Symbol
Parameter
54F/74F
TA= c +2s0
Vee= +s.ov
54F
TA, Vee= Mii
74F
TA, Vee= Com
Units
Fig. No.
Min
Max
Min
Max
Min
Max
t8 (H) t8 (L)
th(H) th(L)
Setup Time, HIGH or LOW
9.0
KtoCP
9.0
Hold Time, HIGH or LOW
2.0
KtoCP
2.0
10.0
10.0
ns
2-6
2.0
2.0
t8 (H) t8 (L)
th(H) th(L)
Setup Time, HIGH or LOW
15.0
YtoCP
15.0
Hold Time, HIGH or LOW
2.0
YtoCP
2.0
15.0
15.0
ns
2-6
2.0
2.0
t8 (H) t8 (L)
th(H) th(L)
Setup Time, HIGH or LOW
3.0
Xn to PL
6.0
Hold Time, HIGH or LOW
2.0
Xn to PL
4.0
4.0
7.0
ns
2-6
2.0
4.0
tw(H)
CP Pulse Width
7.0
tw(L)
HIGH or LOW
7.0
7.0 7.0
ns
2-4
tw(L)
PL Pulse Width, LOW
6.5
7.0
ns
2-4
tree
Recovery Time
6.0
PL toCP
10.0
ns
2-6
4-303
CP
Y or K
FIGURE A. Timing Diagram
Serie.I/Pa rallel
Clock En able
6_'
RE i-. Do
S/P
H - D1
L-S Master Reset--0 MR Sign Extend--0 SE
�r322 8-Blt Shift Register
Oo 1--1--i
Clock- CP
Output Control--0 OE 1/07 1/05 1/05 1/0"4 1/03 1/02 1/01 l/Oo
TL/F/10217-5
Multiplier Input
Clock Clear
CP X7 X5 X5 x. X3 X2
~y
L- K L- M
�r3s4 Serial/Parallel
Multiplier
~PL
SP
x, Xo
FIGURE B. B�Blt by B�Blt Multiplier, Bus Organized, with B�Blt Truncated Product 4-304
TL/F/10217-7
y X7 X5 X5 x. X3 X2 X1 Xo
y X7 Xs X5 x. X3 X2 X1 Xo
K
SP--~--tK
l.t
'f'384
H l.t
'f'384
SP
PL
PL
CP
CP
OUTPUT
CL~R--....+------------~
CLOCK - - e - - - - - - - - - - - - - - '
FIGURE C. 12-Blt by n�Blt Twos Complement Multlpller
TL/F/10217-8
4-305
~National
~Semiconductor
54F/74F385
Quad Serial Adder/Subtracter
General Description
The 'F385 contains four serial adder/subtractors with common clock and clear inputs, but independent operand and mode select inputs. Each adder/subtractor contains a sum flip-flop and a carry-save flip-flop for synchronous operations. Each circuit performs either A plus 8 or A minus 8 in twos complement notation, but can also be used for magnitude-only or ones complement operation. The 'F385 is designed for use with the 'F384 and 'F784 serial multipliers in implementing digital filters or butterfly networks in fast Fourier transforms.
Features
� Four independent adder/subtractors � Twos complement arithmetic � Synchronous operation � Common clear and clock � Ones complement or magnitude-only capability
Ordering Code: see Section 5 Logic Symbols
~ ~ ~ ~ ~ ~ ~ ~ %~ ~ ~
CP MR
F1
F2
F3
F4
TL/F/9531-1
I E E E / I EC
MR CP
S1
F1
A1
B1
Sz
Fz
Az
82
S3
F3
A3
83
S4
r,
A4
84
TL/F/9531-5
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
CP
r, 2 s, 3
81 4 A1 5
A2 82 7 S2 8
F2 GND 10
20 Vee
19 r, 18 s,
17 8.i 16 A.i 15 A3 14 83 13 S3 12 F'3 11 ~
Pin Assignment forLCC
Si 8i A2 A1 81
rnJ II) [[] @] [!)
F2 rn
GND [Q] ~!III
F'3 H1J S3 !rn
rns, mr,
[I]CP
m1I Yee
~r,
rgJ ~Ii]] IIZI Ii])
83 A3 A.i 8.i S.i
TL/F/9531-3
TL/F/9531-2
4-306
Unit Loading/Fan Out: See Section 2 for U.L. definitions
Pin Names
A1-A4 81-84 S1-S4 CP MR F1-F4
Description
''
A Operand Inputs 8 Operand Inputs Function Select Inputs Clock Pulse Input (Active Rising Edge) Asynchronous Master Reset Input (Active LOW) Sum or Difference Outputs
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loHlloL
1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 50/33.3
20 �A/-0.6 mA 20 �A/-0.6 mA 20 �A/ - 0.6 mA 20 �A/ -0.6 mA 20 �Al - 0.6 mA -1 mA/20 mA
Functional Description
Each adder contains two edge-triggered flip-flops to store the sum and carry, as shown in the Logic Diagram. Flip-flop state changes occur on the rising edge of the Clock Pulse (CP) input signal. The Select (S) input should be LOW for the Add (A plus 8) mode and HIGH for the Subtract (A minus 8) mode. A LOW signal on the asynchronous Master Reset (MR) input clears the sum flip-flop and resets the carry flip-flop to zero in the Add mode or presets it to one in the Subtract mode.
Truth Table
In the Subtract mode, the 8 operand is internally complemented. Presetting the carry flip-flop to one completes the twos complement transformation by adding one to "A plus
B" during the first (LS8) operation after MR is released. For
ones complement subtraction, the carry flip-flop can be set to zero by making S LOW during the reset, then making S HIGH after the reset but before the next clock.
Inputs*
Internal Carry
MR
s
A
B
c
C1
L
L
x
x
L
L
L
H
x
x
H
H
H
L
L
L
L
L
H
L
L
L
H
L
H
L
L
H
L
L
H
L
L
H
H
H
H
L
H
L
L
L
H
L
H
L
H
H
H
L
H
H
L
H
H
L
H
H
H
H
H
H
L
L
L
L
H
H
L
L
H
H
H
H
L
H
L
L
H
H
L
H
H
L
H
H
H
L
L
H
H
H
H
L
H
H
H
H
H
H
L
L
H
H
H
H
H
H
H = HIGH Voltage Level L = LOW Voltage Level
X = Immaterial
� = Inputs before CP transition, output after C
C1 = Carry flip-flop state before (C) and after (C1) clock transition
Output*
F
L L
L H H L H L L H
H L L H L H H L
Function Clear Add
Subtract
4-307
Logic Diagram
CP
B1
S1 ADD/ SUBTRACT
TO 3 OTHER ADDER/SUBTRACTORS
---------l:Jll CP
SUM CLR
Q
MR
MASTER
><>---------+-----+}
RESET
TO 3 OTHER
ADDER/SUBTRACTORS
TL/F/9531-4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-308
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for avallablllty and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�c to + 125�c
Junction Temperature under Bias
- 55�c to + 115�C
Vcc Pin Potential to Ground Pin
-0.5V to+ 7.0V
Input Voltage (Note 2)
-0.5V to + 7.0V
Input Current (Note 2)
-30 mA to + 5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5V to Vee - 0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�c to + 125�c
o�cto +1o�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
V1H
Input HIGH Voltage
V1L
Input LOW Voltage
Vco
Input Clamp Diode Voltage
54F/74F Min Typ Max
Units Vee
Conditions
2.0
v
Recognized as a HIGH Signal
0.8
v
Recognized as a LOW Signal
-1.2
v
Min l1N = -18 mA
VoH
Output HIGH
Voltage
54F 10% Vee 2.5
74F 10% Vee 2.5
74F5% Vee
2.7
loH = -1 mA
v
Min loH = -1 mA
loH = -1 mA
Vol
Output LOW
Voltage
54F 10% Vee 74F 10% Vee
0.5
v
Min loL = 20mA
0.5
loL = 20mA
l1H
Input HIGH
54F
Current
74F
20.0 5.0
�.A
Max V1N = 2.7V
lsv1
Input HIGH Current 54F
Breakdown Test
74F
100
�.A
Max V1N = 7.0V
7.0
lcEx
Output HIGH
54F
Leakage Current
74F
250
�A
Max Your= Vee
50
V10
Input Leakage
74F
4.75
Test
v
0.0
110 = 1.9 �.A All Other Pins Grounded
loo
Output Leakage
74F
Circuit Current
3.75
�A
0.0
V100 = 150 mV All Other Pins Grounded
l1L
Input LOW Current
las
Output Short-Circuit Current
-0.6 mA Max V1N = 0.5V
-60
ov -150 mA Max Your=
lccH
Power Supply Current
68
92*
mA Max Vo= HIGH
lccL
Power Supply Current
�95 mA for 54F
68
92*
mA Max Vo= LOW
I
4-309
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
fmax
Maximum Clock Frequency
tPLH
Propagation Delay
tPHL
CP to Fn
IPHL
Propagation Delay
MR to Fn
74F
TA= +25�C Vee= +5.0V
CL= 50pF
Min
Typ
Max
70
100
3.5
6.0
8.0
4.0
7.0
9.0
5.5
9.0
12.0
54F
TA, Vee= Mil CL= 50pF
Min
Max
65
3.0
10.0
3.5
11.0
5.0
14.0
74F
TA, Vee= Com CL= 50pF
Min
Max
70
3.5
9.0
4.0
10.0
5.5
13.0
Fig. Units No.
MHz 2-1 ns 2-3 ns 2-3
AC Operating Requirements: SeeSection2torWaveforms
Symbol
Parameter
t5 (H) t5 (L) th(H) th(L)
15 (H) t5 (L) th(H) th(L)
tw(H) tw(L)
tw(L)
tree
Setup Time, HIGH or LOW An toCP
Hold Time, HIGH or LOW An toCP
Setup Time, HIGH or LOW Bn or Sn to CP Hold Time, HIGH or LOW Bn or Sn toCP
CP Pulse Width HIGH or LOW
MR Width, LOW
Recovery Time, MR to CP
74F
TA= +25�C Vee= +5.0V
Min
Max
15.0 15.0
0 0
15.0 15.0
0 0
6.0 6.0
6.0
8.5
54F
TA, Vee= Mil
Min
Max
17.5 17.5
0 0
17.5 17.5
0 0
7.0 7.0
6.5
10.0
74F
TA, Vee= Com
Min
Max
15.0 15.0
0 0
15.0 15.0
0 0
6.0 6.0
6.0
9.5
Units Fig. No.
ns
2-6
ns
2-6
ns
2-4
ns
2-4
ns
2-6
4-310
c(,o,)
U~NaStemiicoonnduactlor
�Q)
cc(,oo,)
54F/74F398 � 54F/74F399 Quad 2-Port Register
General Description
The 'F398 and 'F399 are the logical equivalents of a quad 2-input multiplexer feeding into four edge-triggered flipflops. A common Select input determines which of the two 4-bit words is accepted. The selected data enters the flipflops on the rising edge of the clock. The 'F399 is the 16-pin version of the 'F398, with only the Q outputs of the flip-flops available.
Features
� Select inputs from two data sources � Fully positive edge-triggered operation � Both true and complement outputs-'F398 � Guaranteed 4000V minimum ESD protection-'F399
Ordering Code: see section 5
Connection Diagrams
Pin Assignment for LCC
ob lob l1b l11l loll
rn:i mrn rn rn
'F398
ob[[) GND [QI
CP [i)
Oc ll1l
oc Ii]
moll
mmosll
@Vee IJ]]Od
ll3J[j]J[�][Z][j]) loc l1c l1d lod od
TL/F/9533-5
'F399
lob l1b NC l1ll IOll
rn:i mrn rn rn
ob[[) GND [QI
NC [i)
CP ll1J
Oc Ii]
mmosll
[I]NC
@Vee IJ]]Od
ll3J[j]J[�][Z][j]) loc l1c NC l1d loll
TL/F/9533-7
Pin Assignment for DIP, SOIC and Flatpak
Oil oil 3 loll 4 l11l 5 l1b 6 lob 7 Qb B ob 9 GND 10
20 Vee 19 Qd 18 od 17 lod 16 l1d 15 l1c 14 loc 13 oc 12 Oc 11 CP
TL/F/9533-6
s
Oil 2 loll 3 l11l 4 l1b 5 lob 6 ob 7 GND B
16 Vee 15 od 14 lod 13 l1d 12 l1c 11 loc 10 Oc 9 CP
TL/F/9533-8
II
4-311
O>
O>
�C") Logic Symbols
co
O>
C")
'F398
10a 11a lob l1b loc l1c lod l1d
s
CP
'F399
TL/F/9533-2
loa l1a lob l1b loc l1c IOd l1d
s
CP Oa ob Oc ad
TL/F/9533-4
IEEE/I EC 'F398
s
CP
loa l1a lob '1b lac l1c lod '1d
'F399
s
CP
'oa l1a lob l1b lac l1c lod l1d
Unit Loading/Fan Out: See Section 2 for U.L. Definitions
Pin Names
s
CP loa-lod l1a-l1d Oa-Od Oa-Od
Description
Common Select Input Clock Pulse Input (Active Rising Edge) Data Inputs from Source 0 Data Inputs from Source 1 Register True Outputs Register Complementary Outputs ('F398)
54F/74F
U.L HIGH/LOW
Input l1Hll1L Output loHllOL
1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 50/33.3 50/33.3
20 �A/-0.6 mA 20 �A/ -0.6 mA 20 �Al -0.6 mA 20 �Al -0.6 mA -1 mA/20mA -1 mA/20mA
Oa Oa ob ob Oc Oc ad Qd
TL/F/9533-1
Oa ob Oc ad
TL/F/9533-3
4-312
Functional Description
The 'F398 and 'F399 are high-speed quad 2-port registers. They select four bits of data from either of two sources (Ports) under control of a common Select input (S). The selected data is transferred to a 4-bit output register synchronous with the LOW-to-HIGH transition of the Clock input (CP). The 4-bit D-type output register is fully edge-trig~ gered. The Data inputs (lox. l1x) and Select input (S) must be stable only a setup time prior to and hold time after the LOW-to-HIGH transition of the Clock input for predictable operation. The 'F398 has both Q and Q outputs.
Logic Diagram
Function Table
Inputs
5
lo
11
Outputs
Q
a�
�wcmo
ccw.oo
I
I
x
L
H
I
h
x
H
L
h
x
I
L
H
h
x
h
H
L
H = HIGH Voltage Level L = LOW Voltage Level h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock transition I = LOW Voltage Level one setup time prior to the LOW-to-HIGH clock transition X = Immaterial �'F398 only
TL/F/9533-9 �'F398 Only Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-313
O>
O>
�C")
co
O>
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
C") please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5Vto +7.0V
Input Voltage (Note 2)
-0.5Vto +7.0V
Input Current (Note 2)
-30 mA to + 5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5VtoVee -0.5V to+ 5.5V
Current Applied to Output in LOW State (Max)
twice the rated ioL (mA)
ESD Last Passing Voltage (Min)-'F399
4000V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
�-55�C to+ 125�C o�cto +10�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
V1H
Input HIGH Voltage
V1L
Input LOW Voltage
Veo
Input Clamp Diode Voltage
54F/74F Min Typ Max
Units Vee
Conditions
2.0
v
Recognized as a HIGH Signal
0.8
v
Recognized as a LOW Signal
-1.2
v
Min l1N = -18 mA
VoH
Output HIGH
Voltage
54F 10% Vee 2.5
74F 10% Vee 2.5
74F5% Vee
2.7
loH = -1 mA
v
Min loH = -1 mA
loH = -1 mA
VoL
Output LOW
Voltage
54F 10% Vee 74F 10% Vee
0.5
v
Min ioL = 20 mA
0.5
loL = 20 mA
l1H
Input HIGH Current 54F
74F
lsv1
Input HIGH Current 54F
Breakdown Test
74F
20.0
�A
Max V1N = 2.7V
5.0
100.
7.0
�A
Max V1N = 7.0V
leEx
Output HIGH
54F
Leakage Current
74F
250 50
�A
Max VouT =Vee
V10
Input Leakage Test
74F
4.75
v
0.0 110 = 1.9 �A
All Other Pins Grounded
loo
Output Leakage
Circuit Current
74F
'3.75
�A
0.0 V100 = 150 mV ,
All Other Pins Grounded
l1L
input LOW Current
los
Output Short-Circuit Current
-0.6 mA Max V1N = 0.5V
-60
-150 mA Max VouT = ov
lccH
Power Supply Current ('F398)
25
38
mA Max Vo= HIGH
lccL
Power Supply Current ('F398)
25
38
mA Max Vo= LOW
lceH
Power Supply Current ('F399)
22
34
mA Max Vo= HIGH
lccL
Power Supply Current ('F399)
22
34
mA Max Vo= LOW
4-314
(,,)
co
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
�CC>
(,,)
74F
54F
74F
ccoo
Symbol
Parameter
TA= +25�C Vee= +5.0V
CL= 50 pf
TA, Vee= Mil CL= 50 pf
TA, Vee= Com CL= 50 pf
Fig. Units
No.
Min
Typ
Max
Min
Max
Min
Max
fmax
Input Clock Frequency
100
140
80
100
MHz 2-1
tPLH
Propagation Delay
tPHL
CPto Q orQ
�'F398 3.3 ns
3.0*
5.7
7.5
3.0
9.5
3.0
8.5
ns
2-3
3.0
6.8
9.0
3.0
11.5
3.0
10.0
AC Operating Requirements: See Section 2 for Waveforms
Symbol
Parameter
ts(H) ts(L)
th(H) th(L)
ts(H) t5(L) ts(H) t5(L) th(H) th(L)
tw(H) tw(L)
Setup Time, HIGH or LOW In to CP
Hold Time, HIGH or LOW lntoCP
Setup Time, HIGH or LOW S to CP ('F398)
Setup Time, HIGH or LOW S to CP ('F399)
Hold Time, HIGH or LOW StoCP
CP Pulse Width HIGH or LOW
74F
TA= +25�C Vee= +5.0V
Min
Max
3.0 3.0
1.0 1.0
7.5 7.5
7.5 7.5
0 0
4.0 5.0
54F
TA, Vee= Mil
Min
4.5 4.5
1.5 1.5
10.5 10.5
9.5 9.5
0 0
4.0 7.0
Max
74F
TA, Vee= Com
Min
Max
3.0 3.0
1.0 1.0
8.5 8.5
8.5 8.5
0 0
4.0 5.0
Units Fig. No.
ns
2-6
ns
2-6
ns
2-4
4-315
,...
0
"'=I' ~National
U Semiconductor
54F/74F401
CRC Generator/Checker
General Description
The 'F401 Cycle Redundancy Check (CRC) Generator/ Checker provides an advanced tool for implementing the most widely used error detection scheme in serial digital data handling systems. A 3-bit control input selects one-ofeight generator polynomials. The list of polynomials includes CRC-16 and CRC-CCITT as well as their reciprocals (reverse polynomials). Automatic right justification is incorporated for polynomials of degree less than 16. Separate clear and preset inputs are provided for floppy disk and other applications. The Error output indicates whether or not a transmission error has occurred. Another control input inhibits feedback during check word transmission. The 'F401 is fully compatible with all TTL families.
Features
� Eight selectable polynomials � Error indicator � Separate preset and clear controls � Automatic right justification � Fully compatible with all TTL logic families � 14-pin package � 9401 equivalent � Typical applications:
Floppy and other disk storage systems Digital cassette and cartridge systems Data communication systems
Ordering Code: see section 5
Logic Symbol
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
CP
14 Vee
p
13 ER
ER
So 3
12 Q
MR
�11 D
s,
10 CWE
Q
NC 6
9 NC
TL/F/9534-4
GND 7
8 Sz
TL/F/9534-1
Unit Loading/Fan Out: See Section 2 for U.L. definitions
Pin Assignment for LCC
s1 NC MR NC So
IIIITllillIJ[!] .
GN ND [QJC [ f i l o [ l ] P III CP
NC [i]
[j]NC
S2!rn NC(j]
!filVcc
~ER
!jj]~[j]]lilJIJ]]
CWENC D NC Q
TL/F/9534-2
Pin Names
Description
54F/74F
U.L.
Input l1Hll1L
HIGH/LOW Output loHlloL
So-S2 D CP CWE
p
MR Q ER
Polynomial Select Inputs Data Input Clock Input (Operates on HIGH-to-LOW Transition) Check Word Enable Input Preset (Active LOW) Input Master Reset (Active HIGH) Input Data Output Error Output
1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 50/33.3 50/33.3
20 �A/-0.6 mA 20 �A/-0.6 mA 20 �Al -0.6 mA 20 �A/ -0.6 mA 20 �A/ -0.6 mA 20 �A/ -0.6 mA -1 mA/20 mA -1 mA/20mA
4-316
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~---.
.i:i.
Functional Description
.0....
The 'F401 is a 16-bit programmable device which operates
Clock input (CP). This data is gated with the most significant
on serial data streams and provides a means of detecting
output (Q) of the register, and controls the Exclusive OR
transmission errors. Cyclic encoding and decoding schemes
gates (Figure 1). The Check Word Enable (CWE) must be
for error detection are based on polynomial manipulation in
held HIGH while the data is being entered. After the last
modulo arithmetic. For encoding, the data stream (message
data bit is entered, the CWE is brought LOW and the check
polynomial) is divided by a selected polynomial. This divi-
bits are shifted out of the register and appended to the data
sion results in a remainder which is appended to the mes-
bits using external gating (Figure 2).
sage as check bits. For error checking, the bit stream containing both data and check bits is divided by the same selected polynomial. If there are no detectable errors, this division results in a zero remainder. Although it is possible to choose many generating polynomials of a given degree, standards exist that specify a small number of useful polynomials. The 'F401 implements the polynomials listed in Table I by applying the appropriate logic levels to the select pins So, S1 and S2.
To check an incoming message for errors, both the data and check .bits are entered through the D input with the CWE input held HIGH. The 'F401 is not in the data path, but only monitors the message. The Error Output becomes valid after the last check bit has been entered into the 'F401 by a HIGH-to-LOW transition of GP. If no detectable errors have occurred during the data transmission, the resultant internal register bits are all LOW and the Error Output (ER) is LOW. If a detectable error has occurred, ER is HIGH.
The 'F401 consists of a 16-bit register, a Read Only Memory (ROM) and associated control circuitry as shown in the block diagram. The polynomial control code presented at
s inputs 0, S1 and S2 is decoded by the ROM, selecting the
desired polynomial by establishing shift mode operation on the register with Exclusive OR gates at appropriate inputs. To generate the check bits, the data stream is entered via
A HIGH on the Master Reset input (MR) asynchronously clears the register. A LOW on the Preset input (P) asynchronously sets the entire register if the control code inputs specify a 16-bit polynomial; in the case of 12- or 8-bit check polynomials only the most significant 12 or 8 register bits are set and the remaining bits are cleared.
the Data inputs (D), using the HIGH-to-LOW transition of the
Select Code
S2
S1
So
L
L
L
L
L
H
L
H
L
L
H
H
H
L
L
H
L
H
H
H
L
H
H
H
TABLE I
Polynomial
X16 + X15 + X2 + 1 X16 + X14 + X + 1 X16 + X15 + X13 + X7 + X4 + X2 + X1 + 1
x12 + x11 + X3 + x2 + x + 1 xa + x1 + xs + X4 + x + 1
xa + 1 X16 + x12 + xs + 1 X16 + X11 + X4 + 1
Remarks
CRC-16 CRC-16 REVERSE
CRC-12
LRC-8 CRC-CCITI CRC-CCITI REVERSE
Block Diagram
So
POLYNOt.llAL SELECT
s,
ROI.I
S2
CHECK WORD ENABLE PRESET
DATA CLOCK
t.IASTER RESET
.....
e0 :
z u 0
CWE
D
16-BIT REGISTER
Q
CP
t.IR
DATA OUTPUT
ERROR DETECTOR
ER
4-317
ERROR
TL/F/9534-5
....
0
Q
. MR
EP~---t-....--- - -.... ---+-----+--------------t-----CWE-----11------------+-----------------+---------,
FIGURE 1. Equivalent Circuit for X16 + X15 + X2 + 1
CHECK WORD --DA-TA-4..,_----------------f"'-....
(NOTE
1
ENABLE AND 3)
-
-
-
t
-
-
-
-
-
-
-
-
.
-
-
-.....--
-
i-.
.
,
NOTE 2
CLOCK -----a CP
MR
CWE F'-401 CRC GENERATOR/ CHECKER
NOTE 2
FIGURE 2. Check Word Generation
Note 1: Check word Enable is HIGH while data is being clocked, LOW while transmission of check bits. Note 2: 'F401 must be reset or preset before each computation. Note 3: CRC check bits are generated and appended to data bits.
TL/F/9534-6 DATA PLUS CHECK BITS
TL/F/ 9 5 3 4 - 7
4-318
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5Vto +7.0V
Input Voltage (Note 2)
- 0.5V to + 7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5VtoVee - 0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�C to +70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
V1H
Input HIGH Voltage
V1L
Input LOW Voltage
Veo
Input Clamp Diode Voltage
54F/74F Min Typ Max
Units Vee
Conditions
2.0
v
Recognized as a HIGH Signal
0.8
v
Recognized as a LOW Signal
-1.2
v
Min l1N = -18 mA
VoH
Output HIGH
Voltage
54F 10% Vee 2.5
74F 10% Vee 2.5
74F5% Vee
2.7
loH = -1 mA
v
Min loH = -1 mA
loH = -1 mA
Vol
Output LOW
Voltage
54F 10% Vee 74F 10% Vee
0.5
v
Min loL = 20mA
0.5
Im= 20 mA
l1H
Input HIGH Current 54F
74F
20.0 5.0
�A
Max V1N = 2.7V
lsv1
Input HIGH Current 54F
Breakdown Test
74F
100 7.0
�A
Max V1N = 7.0V
leEx
Output HIGH
54F
Leakage Current
74F
250 50
�A
Max Vour =Vee
V10
Input Leakage Test
74F
4.75
v
110 = 1.9 �A 0.0 All Other Pins Grounded
loo
Output Leakage
Circuit Current
74F
3.75
�A
0.0 V100 = 150mV All Other Pins Grounded
l1L
Input LOW Current
los
Output Short-Circuit Current
-0.6
mA
Max V1N = 0.5V
-60
-150 mA Max Vour = ov
leeH
Power Supply Current
70
105
mA Max Vo= HIGH
4-319
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
fmax
Maximum Clock Frequency
tPLH
Propagation Delay
tPHL
CPtoQ
Propagation Delay
tPHL
MRtoQ
Propagation Delay
tPLH
Ptoa
Propagation Delay
tPHL
MR to ER
Propagation Delay
tPLH
P to ER
tpLH
Propagation Delay
tPHL
CPto ER
74F
TA= +25�C Vee= +5.0V
CL= 50 pF
Min
Typ
Max
100
4.5
11.5
4.0
10.0
3.0
7.5
3.0
8.5
3.5
11.0
3.0
8.5
5.0
13.0
4.5
11.5
54F
TA, Vee= Mil CL= 50 pF
Min
Max
74F
TA, Vee= Com CL= 50 pF
Min
Max
85
4.5
13.5
4.0
11.0
3.0
8.0
3.0
9.5
3.5
12.0
3.0
10.0
5.0
14.5
4.5
12.5
Fig. Units
No.
MHz 2-1 ns 2-3 ns 2-3 ns 2-3 ns 2-3 ns 2-3 ns 2-3
AC Operating Requirements: See Section 2 for Waveforms
Symbol
Parameter
t5 (H) t5 (L) t5 (H) t5 (L) th(H) th(L) lw(L) tw(H) lw(L) lw(H)
tree
tree
Set-up Time, HIGH or LOW DtoCP
Set-up Time, HIGH or LOW CWEtoCP
Hold Time, HIGH or LOW D and CWE to CP
P Pulse Width, LOW
Clock Pulse Width, HIGH or LOW
MR Pulse Width, HIGH
Recovery Time MRtoCP
Recovery Time P to CP
74F
TA= +25�C Vee= +5.0V
Min
Max
5.0 5.0
4.0 4.0
2.0 2.0
7.0
5.0 5.0
5.0
4.0
2.0
54F
TA, Vee= Mil
Min
Max
74F
TA, Vee= Com
Min
Max
5.5 5.5
4.5 4.5
2.0 2.0
8.0
6.0 6.0
5.5
4.5
Fig. Units No.
ns 2-6
ns 2-4
ns 2-4
ns 2-4
ns
2-6
2.0
ns 2-6
4-320
~National
U Semiconductor
54F/74F402 Serial Data Polynomial Generator/Checker
General Description
The 'F402 expandable Serial Data Polynomial generator/ checker is an expandable version of the 'F401. It provides an advanced tool for the implementation of the most widely used error detection scheme in serial digital handling systems. A 4-bit control input selects one-of-six generator polynomials. The list of polynomials includes CRC-16, CRCCCITI and Ethernet�, as well as three other standard polynomials (56th order, 48th order, 32nd order). Individual clear and preset inputs are provided for floppy disk and other applications. The Error output indicates whether or not a transmission error has occurred. The CWG Control input inhibits feedback during check word transmission. The 'F402 is compatible with FAST� devices and with all TIL families.
Features
� Guaranteed 30 MHz data rate � Six selectable polynomials � Other polynomials available � Separate preset and clear controls � Expandable � Automatic right justification � Error output open collector � Typical applications:
Floppy and other disk storage systems Digital cassette and cartridge systems Data communication systems � Available in SOIC, (300 mil only)
Ordering Code: see sections Logic Symbol
Connection Diagrams
So S1 S2 S3 CWG
ER CP SEI RFB p
M D/CW RO
Pin Assignment for DIP, SOIC and Flatpak
CP
MR D 4
CWG 5 RFB SEI GND 8
16 Yee
15 So 14 S1 13 S2 12 S3 11 D/CW 10 RO
ER
TL/F/9535-1
Pin Assignment for LCC
RFB CWG NC D MR
[[] mmrn m
SEI []] GND [QI
NC [j] ER Ii] RO Ii]
rn P
[nCP
[I]NC ~Vee Ii]] So
Ii]] ii] lill lill [j]]
D/CW S3 NC S2 S1
TL/F/9535-2
TL/F/9535-4
4-321
Unit Loading/Fan Out: See Section 2 for u.L. definitions
Pin Names
So-S3 CWG D/CW D ER RO CP SEI RFB MR
p
�open Collector
Description
Polynomial Select Inputs Check Word Generate Input Serial Data/Check Word Data Input Error Output Register Output Clock Pulse Serial Expansion Input Register Feedback Master Reset Preset
U.L. HIGH/LOW
1.0/0.67 1.0/0.67 2 8 5 ( 1 0 0 ) / 1 3 . 3 ( 6 . 7) 1.0/0.67
*/26.7(13.3)
2 8 5 ( 1 0 0 ) / 1 3 . 3 ( 6 . 7) 1.0/0.67 1.0/0.67 1.0/0.67 1.0/0.67 1.0/0.67
54F/74F
Input l1Hll1L Output loHllOL
20 �A/-0.4 mA 20 �A/-0.4 mA -5.7 mA(-2 mA)/8 mA (4 mA) 20 �A/ - 0.4 mA */16 mA (8 mA) -5.7 mA(-2 mA)/8 mA (4 mA) 20 �A/-0.4 mA 20 �A/-0.4 mA 20 �A/-0.4 mA 20 �A/ -0.4 mA 20 �A/-0.4 mA
Functional Description
The 'F402 Serial Data Polynomial Generator/Checker is an expandable 16-bit programmable device which operates on serial data streams and provides a means of detecting transmission errors. Cyclic encoding and decoding schemes for error detection are based on polynomial manipulation in modulo arithmetic. For encoding, the data stream (message polynomial) is divided by a selected polynomial. This division results in a remainder (or residue) which is appended to the message as check bits. For error checking, the bit stream containing both data and check bits is divided by the same selected polynomial. If there are no detectable errors, this division results in a zero remainder. Although it is possible to choose many generating polynomials of a given degree, standards exist that specify a small number of useful polynomials. The 'F402 implements the polynomials listed in Table I by applying the appropriate logic levels to the select pins So, S1, S2 and S3.
The 'F402 consists of a 16-bit register, a Read Only Memory (ROM) and associated control circuitry as shown in the Block Diagram. The polynomial control code presented at
s inputs S0, 1, S2 and S3 is decoded by the ROM, selecting
the desired polynomial or part of a polynomial by establishing shift mode operation on the register with Exclusive OR (XOR) gates at appropriate inputs. To generate the check bits, the data stream is entered via the Data Inputs (D), using the LOW-to-HIGH transition of the Clock Input (CP). This data is gated with the most significant Register Output (RO) via the Register Feedback Input (RFB), and controls the
XOR gates. The Check Word Generate (CWG) must be held HIGH while the data is being entered. After the last data bit is entered, the CWG is brought LOW and the check bits are shifted out of the register(s) and appended to the data bits (no external gating is needed).
To check an incoming message for errors, both the data and check bits are entered through the D Input with the CWG Input held HIGH. The Error Output becomes valid after the last check bit has been entered into the 'F402 by a LOW-to-HIGH transition of CP, with the exception of the Ethernet polynomial (see Applications paragraph). If no detectable errors have occurred during the data transmission, the resultant internal register bits are all LOW and the Error Output (ER) is HIGH. If a detectable error has occurred, ER is LOW. ER remains valid until the next LOW-to-HIGH transition of CP or until the device has been preset or reset.
A HIGH on the Master Reset Input (MR) asynchronously clears the entire register. A LOW on the Preset Input (P) asynchronously sets the entire register with the exception of:
1 The Ethernet residue selection, in which the registers containing the non-zero residue are cleared;
2 The 56th order polynomial, in which the 8 least significant register bits of the least significant device are cleared; and,
3 Register S = O, in which all bits are cleared.
4-322
Select Code
Hex
S3
S2
S1
So
0
L
L
L
L
c
H
H
L
L
D
H
H
L
H
E
H
H
H
L
F
H
H
H
H
7
L
H
H
H
B
H
L
H
H
3
L
L
H
H
2
L
L
H
L
4
L
H
L
L
8
H
L
L
L
5
L
H
L
H
9
H
L
L
H
1
L
L
L
H
6
L
H
H
L
A
H
L
H
L
Block Diagram
TABLE I
Polynomial
0 X32+X26+ X23+ x22+ X16+ x12+x11 +x10+xa+x1+xs+x4+x2+x+1
x32+x31 +x21 +x2s+x2s+x19+x1s+
x1s+x13+x12+x11 +X9+X7+xs+xs+x4+x2+x+1 X1B+x1s+x2+1 X16+ x12+ xs+ 1 xss+xss+X49+X45+X41 + X39+X3B+X37 +X36+X31 + X22+X19+X17 +X16+X15+X14+X12+X11 +X9+ xs+x+ 1 X4B+ X36+ X35+ X23+X21 + x1s+ x13+ xa+ x2+ 1 X32+X23+X21 + X11+X2+1
Remarks
S=O
Ethernet Polynomial Ethernet Residue CRC-16 CRC-CCITI
56th Order
48th Order
32nd Order
4-323
TABLE II
Select Code
P3
P2
P1
Po
C2
C1
Co
Polynomial
0
0
0
0
0
1
0
0
S=O
c
1
1
1
1
1
0
1
Ethernet
D
1
1
1
1
1
0
1
Polynomial
E
0
0
0
0
0
0
0
Ethernet
F
0
0
0
0
0
1
0
Residue
7
1
1
1
1
1
0
0
CRC-15
B
1
1
1
1
1
0
0
CRC-CCITT
3
1
1
1
1
1
0
0
2
1
1
1
1
1
0
0
55th
4
1
1
1
1
1
0
0
Order
8
0
0
1
1
1
0
0
5
1
1
1
1
1
0
0
48th
9
1
1
1
1
1
0
0
Order
1
1
1
1
1
1
0
0
5
1
1
1
1
1
0
0
32nd
A
1
1
1
1
1
0
0
Order
Applications
In addition to polynomial selection there are four other capabilities provided for in the 'F402 ROM. The first is set or clear selectability. The sixteen internal registers have the
capability to be either set or cleared when P is brought
LOW. This set or clear capability is done in four groups of 4 (see Table II, P0-P3). The second ROM capability (Co) is in determining the polarity of the check word. As is the case with the Ethernet polynomial the check word can be inverted when it is appended to the data stream or as is the case with the other polynomials, the residue is appended with no inversion. Thirdly, the ROM contains a bit (C1) which is used to select the AFB input instead of the SEI input to be fed into the LSB. This is used when the polynomial selected is actually a residue (least significant) stored in the ROM which indicates whether the selected location is a polynomial or a residue. If the latter, then it inhibits the AFB input.
As mentioned previously, upon a successful data transmission, the CRC register has a zero residue. There is an exception to this, however, with respect to the Ethernet polynomial. This polynomial, upon a successful data transmission, has a non-zero residue in the CRC register (C7 04 DD 7B)15. In order to provide a no-error indication, two ROM locations have been preloaded with the residue so that by selecting these locations and clocking the device one additional time, after the last check bit has been entered, will result in zeroing the CRC register. In this manner a no-error indication is achieved.
With the present mix of polynomials, the largest is 55th order requiring four devices while the smallest is 15th order requiring just one device. In order to accommodate multiplexing between high order polynomials (X 15th order) and lower order polynomials, a location of all zeros is provided. This allows the user to choose a lower order polynomial even if the system is configured for a higher order one.
The 'F402 expandable CRC generator checker contains 5 popular CRC polynomials, 2-16th Order, 2-32nd Order, 149th Order and 1-55th Order. The application diagram shows the 'F402 connected for a 55th Order polynomial. Also shown are the input patterns for other polynomials. When the 'F402 is used with a gated clock, disabling the clock in a HIGH state will ensure no erroneous clocking occurs when the clock is re-enabled. Preset and Master Reset are asynchronous inputs presetting the register to S or clearing to 1s respectively (note Ethernet residue and 55th Order select code 8, LSB, are exceptions to this).
To generate a CRC, the pattern for the selected polynomial is applied to the S inputs, the register is preset or cleared as required, clock is enabled, CWG is set HIGH, data is applied to D input, output data is on D/CW. When the last data bit has been entered, CWG is set LOW and the register is clocked for n bits (where n is the order of the polynomial). The clock may now be stopped if desired (holding CWG LOW and clocking the register will output zeros from D/CW after the residue has been shifted out).
To check a CRC, the pattern for the selected polynomial is applied to the S inputs, the register is preset or cleared as required, clock is enabled, CWG is set HIGH, the data stream including the CRC is applied to D input. When the last bit of the CRC has been entered, the ER output is checked: HIGH =error free data, LOW= corrupt data. The clock may now be stopped if desired.
To implement polynomials of lower order than 55th, select the number of packages required for the order of polynomial and apply the pattern for the selected polynomial to the S inputs (0000 on S inputs disables the package from the feedback chain).
4-324
Applications (Continued)
Data/CRC Serial Data
Clock
.i:i. 0 N
Vee
56th Order
I l Eth~f~::net :. 4K7 I
Error Output
_ L I Serial Data Out
48th Order 32nd Order
Residue
CRC-16
n~nnlir ER DO RO
CWG
Sso1
s D 'F402 S2
CP
3
MR
.,_ pl--
r- CRC-CCITT 1 10 0 0 1 1 1 0 10 111 0 111110
0 0 0 1 10 1
SEI RFB
~
ER RO
So
CWG
s,
DCP
'F402
S2 S3
MR
p
SEI RFB
~
0 10 1 0 0 1 0 10 0 0 0 001 00 0 111 00
ER RO
So
CWG
s,
DCP
'F402
S2 S3
MR
p
SEI RFB
~
0 10 0 0 0 0 0000 0
1 0000 0 0 0000 0
ER
RO
So
CWG
s,
"'----- DCP
'F402
S2 S3
MR
p
SEI RFB
~ L__
0 000000 0 000000 0 000000 1 000000
Zero Register Initialize Register
TL/F/9535-6
4-325
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the Natlonal Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
-55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5Vto +7.0V
Input Voltage (Note 2)
-0.5V to+ 7.0V
Input Current (Note 2)
-30 mA to + 5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5V to Vee -0.5Vto +5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�c o�cto +10�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
Input HIGH Voltage
Input LOW Voltage
Vco
Input Clamp Diode Voltage
VoH
Output HIGH
Voltage
54F 10% Vee 74F 10% Vee 74F5% Vee
54F/74F Min Typ Max 2.0
0.8 -1.2 2.4 2.4 2.7
Units
v
v
v
v
Vee
Conditions
Recognized as a HIGH Signal
Recognized as a LOW Signal
Min l1N = -18 mA loH = -2 mA (RO, D/CW)
Min loH = -5.7 mA (RO, D/CW) loH = -5.7 mA (RO, D/CW)
VoL
Output LOW
Voltage
54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee
0.4
loL = 4 mA (D/CW, RO)
0.4
v
Min loL = 8 mA (ER)
0.5
IOL = 16 mA (ER)
0.5
loL = 8 mA (D/CW, RO)
Input HIGH Current 54F 74F
20.0
�A
Max V1N = 2.7V
5.0
lsv1
Input HIGH Current 54F
Breakdown Test
74F
100 7.0
�A
Max V1N = 7.0V
lcEX
Output HIGH
54F
Leakage Current
74F
250 50
�A
Max Vour =Vee
Input Leakage
74F
Test
4.75
v
0.0 110 = 1.9 �A
All Other Pins Grounded
loo
Output Leakage 74F
Circuit Current
3.75
�A
0.0 V100 = 150 mV
All Other Pins Grounded
los loHC
Input LOW Current Output Short-Circuit Current Open Collector, Output OFF Leakage Test
-0.4
mA
Max V1N = 0.5V
-20
ov -130 mA Max Vour = (D/CW, RO)
250
�A
Min Vour =Vee (ER)
Ice
Power Supply Current
110 165
mA Max
4-326
AC Electrical Characteristics: see section 2 for waveforms and Load configurations
Symbol
Parameter
fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH
tPLH
tPLH tPHL tPHL
lPLH
lPLH lPHL tPLH lPHL lPLH lPHL
Maximum Clock Frequency
Propagation Delay CPto D/CW
Propagation Delay CPto RO
Propagation Delay CPto ER
Propagation Delay Pto D/CW
Propagation Delay PtoRO
Propagation Delay Pto ER
Propagation Delay MR to D/CW
Propagation Delay MR to RO
Propagation Delay MR to ER
Propagation Delay DtoD/CW
Propagation Delay CWGtoD/CW
Propagation Delay SntoD/CW
74F
TA= +25�C Vee= +5.0V
CL= 50 pF
Min
Typ
Max
30
45
8.5
15.0
19.0
10.5
18.0
23.0
8.0
13.5
17.0
8.0
14.0
18.0
15.5
26.0
33.0
8.5
14.5
18.5
11.0
18.5
23.5
11.5
19.5
24.5
9.5
16.0
20.5
10.0
17.0
21.5
10.5
18.0
23.0
11.0
19.0
24.0
9.0
15.5
19.5
16.5
28.0
35.5
6.0
10.5
13.5
7.5
12.0
16.0
6.5
11.0
14.0
7.0
12.0
15.5
11.5
19.5
24.5
9.5
16.0
20.0
54F
TA, Vee= Mil CL= 50 pF
Min
Max
30
7.5
26.5
9.5
26.5
7.0
26.0
7.0
22.5
14.0
38.5
7.5
23.5
10.0
31.0
10.5
32.0
8.5
31.5
74F
TA, Vee= Com CL= 50 pf
Min
Max
30
7.5
21.0
9.5
25.0
7.0
19.0
7.0
20.0
14.0
35.0
7.5
20.5
10.0
25.5
10.5
26.5
8.5
22.5
9.0
26.0
9.0
23.5
9.5
29.0
9.5
25.5
10.0
28.5
10.0
26.0
8.0
23.5
8.0
21.5
14.5
39.0
14.5
37.5
5.0
19.5
5.0
15.0
6.5
20.0
6.5
18.0
5.5
21.5
5.5
15.5
6.0
21.5
6.0
17.5
9.0
29.0
10.5
26.5
8.5
25.0
8.5
22.0
Fig. Units No.
MHz 2-1 ns 2-3 ns 2-3 ns 2-3 ns 2-3 ns 2-3 ns 2-3 ns 2-3 ns 2-3 ns 2-3 ns 2-3 ns 2-3 ns 2-3
4-327
AC Operating Requirements: SeeSection2forWaveforms
Symbol
Parameter
74F
TA= +2s0 c Vee= +s.ov
Min
Max
54F
TA, Vee= Mil
Min
Max
t5(H) t5(L)
th(H) th(L)
t5(H) t5(L)
MH) th(L)
t5(H) t5(L)
th(H) th(L)
t5(H) t5(L)
th(H) th(L)
t5(H) t5(L)
th(H) ML)
tw(H) tw(L)
Setup Time, HIGH or LOW
4.5
SEI to CP
4.5
Hold Time, HIGH or LOW
0
SEI to CP
0
Setup Time, HIGH or LOW
11.0
RFBtoCP
11.0
Hold Time, HIGH or LOW
0
RFBtoCP
0
Setup Time, HIGH or LOW
13.5
S1 toCP
13.0
Hold Time, HIGH or LOW
0
S1 toCP
0
Setup Time, HIGH or LOW
9.0
DtoCP
9.0
Hold Time, HIGH or LOW
0
DtoCP
0
Setup Time, HIGH or LOW
7.0
CWGtoCP
5.5
Hold Time, HIGH or LOW
0
CWGtoCP
0
Clock Pulse Width
4.0
HIGH or LOW
4.0
6.0 6.0
1.0 1.0
14.0 14.0
0 0
16.0 15.5
0 0
11.5 11.5
0 0
9.0 8.0
0 0
7.0 5.0
tw(H)
MR Pulse Width, HIGH
4.0
7.0
tw(L)
P Pulse Width, LOW
4.0
5.0
tree
Recovery Time
3.0
4.0
MRtoCP
tree
Recovery Time
5.0
6.5
PtoCP
74F
TA, Vee= Com
Min
Max
5.0 5.0
0 0
12.5 12.5
0 0
15.0 14.5
0 0
10.0 10.0
0 0
8.0 6.5
0 0
4.5 4.5
4.5
4.5
3.5
6.0
Units
Fig.
No.
ns
2-6
ns
2-6
ns
2-6
ns
2-6
ns
2-6
ns
2-4
ns
2-4
ns
2-4
ns
2-6
4-328
~National
~Semiconductor
54F/74F403A First-In First-Out {FIFO) Buffer Memory
General Description
The 'F403A is an expandable fall-through type high-speed First-In First-Out (FIFO) Buffer Memory optimized for highspeed disk or tape controllers and communication buffer applications. It is organized as 16-words by 4-bits and may be expanded to any number of words or any number of bits in multiples of four. Data may be entered or extracted asynchronously in serial or parallel, allowing economical implementation of buffer memories.
The 'F403A has TRI-STATE� outputs which provide added versatility and is fully compatible with all TIL families.
Features
� Serial or parallel input � Serial or parallel output � Expandable without external logic � TRI-STATE outputs � Fully compatible with all TIL families � Slim 24-pin package � 9403A replacement � Guaranteed 4000V minimum ESD protection
Ordering Code: see section 5 Connection Diagrams
Pin Assignment for DIP and SOIC
iRF
PL 2 Do 3
o, 4
D2 5 D3 Ds 7 CPSI 8
iES
TTS 10 t.IR 11 GND 12
24 Yee 23 ORE 22 Os 21 Oo
20 o,
19 02 18 03
17 OE
16 CPSO 15 OES 14 TOS 13 TOP
TL/F/9536-2
Pin Assignment for PCC
IES CPSI Ds NC 03 Dz o, [i] [!ill [[] []] [I] []] [fil
TTS [j]] iiR 11]
GND IHJ
GND [fil TOP [j]]
TOS IIZJ
OES [fil
moo
[I] PL
[II IRF
QJ Yee ~Yee
~ORE ~Os
[fil~~~~~~
CPSO OE 03 NC 02 01 Oo
TL/F/9536-3
4-329
<C
(")
0 "'l:t'
Logic Symbol
PL
Ds D3 D2 D1 Do
- 0 TIS
--0 IES
IRF'
--0 CPSI
TOP
--0 TOS --0 OES --0 CPSO
OE
MR
03 02 01 Oo Os
ORE 0 -
Unit Loading/Fan Out: See Section 2 for U.L. definitions
Pin Names
Do-D3 Ds PL CPSI IES TTS OES TOS TOP MR OE CPSO Oo-03 Os IRF ORE
Description
Parallel Data Inputs Serial Data Input Parallel Load Input Serial Input Clock Serial Input Enable Transfer to Stack Input Serial Output Enable Transfer Out Serial Transfer Out Parallel Master Reset Output Enable Serial Output Clock Parallel Data Outputs Serial Data Output Input Register Full Output Register Empty
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loHllOL
1.0/0.667 1.0/0.667 1.0/0.667 1.0/0.667 1.0/0.667 1.0/0.667 1.0/0.667 1.0/0.667 1.0/0.667 1.0/0.667 1.0/0.667 1.0/0.667 285/26.7 285/26.7 20/13.3 20/13.3
20 �A/400 �A 20 �A/400 �A 20 �A/400 �A 20 �A/400 �A 20 �A/400 �A 20 �A/400 �A 20 �A/400 �A 20 �A/400 �A 20 �A/400 �A 20 �A/400 �A 20 �A/400 �A 20 �A/400 �A 5.7 mA/16 mA 5.7 mA/16 mA -400 �A/8 mA -400 �A/8 mA
TL/F/9536-1
4-330
.i:i.
Block Diagram
0 w
)>
PL INPUT DATA
CPSI
iEs
TTS
STACK CONTROL
14 X 4 STACK
OES TOP TOS
CPSO
OUTPUT REGISTER OUTPUT DATA
Functional Description
As shown in the block diagram the 'F403A consists of three sections:
1. An Input Register with parallel and serial data inputs as well as control inputs and outputs for input handshaking and expansion.
2. A 4-bit wide, 14-word deep fall-through stack with selfcontained control logic.
3. An Output Register with parallel and serial data outputs as well as control inputs and outputs for output handshaking and expansion.
Since these three sections operate asynchronously and almost independently, they will be described separately below.
INPUT REGISTER (DATA ENTRY)
The Input Register can receive data in either bit-serial or in 4-bit parallel form. It stores this data until it is sent to the fallthrough stack and generates the necessary status and control signals.
Figure 1 is a conceptual logic diagram of the input section. As described later, this 5-bit register is initialized by setting
TL/F/9536-4
the F3 flip-flop and resetting the other flip-flops. The Q output of the last flip-flop (FC) is brought out as the 'Input Register Full' output (IRF). After initialization this output is HIGH.
Parallel Entry-A HIGH on the PL input loads the Do-D3 inputs into the Fo-F3 flip-flops and sets the FC flip-flop. This forces the IRF output LOW indicating that the input register is full. During parallel entry, the CPSI input must be LOW. If parallel expansion is not being implemented, IES must be LOW to establish row mastership (see Expansion section).
Serial Entry-Data on the Ds input is serially entered into the F3, F2, F1, Fo, FC shift register on each HIGH-to-LOW transition of the CPSI clock input, provided IES and PL are LOW. After the fourth clock transition, the four data bits are located in the four flip-flops, F0-F3. The FC flip-flop is set, forcing the IRF output LOW and internally inhibiting CPSI clock pulses from affecting the register, Figure 2 illustrates the final positions in a 'F403A resulting from a 64-bit serial bit train. Bo is the first bit, 853 the last bit.
4-331
<C
Cf)
~ Functional Description (Continued)
. . . - - - - - - - - - - INPUT D A T A - - - - - - - - - -
D2
D1
Do I
I N I T I A L I Z E - - + - - - - - -.....
o---- Ds----i F3
CP R
0
re IRF
iES---+-or--..
CPSI
t--+-------+--------11--------'--'
INPUT R E G - S T A C K - - - - - - - - - - + - - - - - - - - + - - - - - - . . , __ _ _____, {PULSE DERIVED FROM ffi)
...___ _ _ _ _ _ _ DATA INPUTS TO S T A C K - - - - - - - - '
FIGURE 1. Conceptual Input Section
TL/F/9536-5
INPUT REGISTER
OUTPUT REGISTER
'r403A
TL/F/9536-6
FIGURE 2. Final Positions in a 'F403A Resulting from a 64-Bit Serial Train
Transfer to the Stack-The outputs of Flip-Flops F0 -F3 feed the stack. A LOW level on the TTS input initiates a 'fall-
through' action. If the top location of the stack is empty, data is loaded into the stack and the input register is re-initialized. Note that this initialization is postponed until PL is LOW again. Thus, automatic FIFO action is achieved by connecting the IRF output to the TTS input.
An RS Flip-Flop (the Request Initialization Flip-Flop shown in Figure 10) in the control section records the fact that data has been transferred to the stack. This prevents multiple entry of the same word into the stack despite the fact the IRF and TIS may still be LOW. The Request Initialization Flip-Flop is not cleared until PL goes LOW. Once in the stack, data falls through the stack automatically, pausing only when it is necessary to wait for an empty next location. In the 'F403A as in most modern FIFO designs, the MR input only initializes the stack control section and does not clear the data.
OUTPUT REGISTER (DATA EXTRACTION)
The Output Register receives 4-bit data words from the bottom stack location, stores it and outputs data on a TRISTATE 4-bit parallel data bus or on a TRI-STATE serial data bus. The output section generates and receives the necessary status and control signals. Figure 3 is a conceptual logic diagram of the output section.
4-332
Functional Description (Continued)
. . - - - - - - - - - - OUTPUT rROl.I S T A C K - - - - - - - - . . . . ,
~--~~~'\--+-----'-------+--------1-------+----'
TOP ----<lL-""
Oz
o,
Oo
L . - - - - - - - - - - OUTPUT D A T A - - - - - - - - - - '
FIGURE 3. Conceptual Output Section
TL/F/9536-7
Parallel Data Extraction-When the FIFO is empty after a LOW pulse is applied to MR, the Output Register Empty (ORE) output is LOW. After data has been entered into the FIFO and has fallen through to the bottom stack location, it is transferred into the Output Register provided the 'Transfer Out Parallel' (TOP) input is HIGH. As a result of the data transfer ORE goes HIGH, indicating valid data on the data outputs (provided the TRI-STATE buffer is enabled). TOP can now be used to clock out the next word. When TOP goes LOW, ORE will go LOW indicating that the output data has been extracted, but the data itself remains on the output bus until the next HIGH level at TOP permits the transfer of the next word (if available) into the Output Register. During parallel data extraction CPSO should be LOW. TOS should be grounded for single slice operation or connected to the appropriate ORE for expanded operation (see Expansion section).
TOP is not edge triggered. Therefore, if TOP goes HIGH before data is available from the stack, but data does become available before TOP goes LOW again, that data will be transferred into the Output Register. However, internal
control circuitry prevents the same data from being transferred twice. If TOP goes HIGH and returns to LOW before data is available from the stack, ORE remains LOW indicating that there is no valid data at the outputs.
Serial Data Extraction-When the FIFO is empty after a LOW pulse is applied to MR, the Output Register Empty (ORE) output is LOW. After data has been entered into the FIFO and has fallen through to the bottom stack location, it is transferred into the Output Register provided TOS is LOW and TOP is HIGH. As a result of the data transfer ORE goes HIGH indicating valid data in the register. The TRI-STATE Serial Data Output, Os, is automatically enabled and puts the first data bit on the output bus. Data is serially shifted out on the HIGH-to-LOW transition of CPSO. To prevent false shifting, CPSO should be LOW when the new word is being loaded into the Output Register. The fourth transition empties the shift register, forces ORE output LOW and disables the serial output, Os (refer to Figure 3). For serial operation the ORE output may be tied to the TOS input, requesting a new word from the stack as soon as the previous one has been shifted out.
4-333
<(
.-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
CW)
~ Functional Description (Continued)
EXPANSION
Vertical Expansion-The 'F403A may be vertically expanded to store more words without external parts. The interconnection is necessary to form a 46-word by 4-bit FIFO are shown in Figure 4. Using the same technique, and FIFO
of (15n + 1)-words by 4-bits can be constructed, where n is
the number of devices. Note that expansion does not sacrifice any of the 'F403A's flexibility for serial/parallel input and output.
MASTER RESET
PARALLEL DATA IN
PARALLEL I
I
LOAD D3 D2 D1 Do
SERIAL DATA IN SERIAL INPUT CLOCK
I l X+�" PL Ds D3 D2 Di Do TIS
~JES
IRF P-
; CPSI
""' OES
r-..0....
TOS TOP
-0 CPSO
'F403A
ORE P;
~OE
MR o3o2 o1o0o5
!i
T
NC
l
1
~ TIS PL Ds D3 D2D1 Do
;' JES
.~.....
CPSI OES
'F403A
r-..0....
TOS TOP
~ CPSO
IRF PORE p...
~OE
MR 03 o2 o1o0o5
j
T
NC _....
l
1
DUMP SERIAL OUTPUT CLOCK OUTPUT ENABLE
~ TIS PL Ds D3 D2 D1 Do
;' JES
...;.;;.;..
CPSI OES
'F403A
rO TOS
IRF p...
TOP
DATA VALID
~ CPSO
-d OE
ORE P-t--+
yMR o3o2 o1o0o5
l
s..~,.RIAL
DA TA
-=-
�~' ~'
OU TPUT
PARALLEL DATA OUT
FIGURE 4. A Vertical Expansion Scheme
TL/F/9536-8
4-334
Functional Description (Continued)
Horizontal and Vertical Expansion-The 'F403A can be expanded in both the horizontal and vertical directions without any external parts and without sacrificing any of its FIFO's flexibility for serial/parallel input and output. The interconnections necessary to form a 31-word by 16-bit FIFO are shown in Figure 6. Using the same technique, any FIFO
of (15m + 1)-words by (4n)-bits can be constructed, where
m is the number of devices in a column and n is the number of devices in a row. Figures 7 and 8 show the timing diagrams for serial data entry and extraction for the 31-word by 16-bit FIFO shown in Figure 6. The final position of data after serial insertion of 496 bits into the FIFO array of Figure 6 is shown in Figure 9.
Interlocking Circuitry-Most conventional FIFO designs provide status signals analogous to IRF and ORE. However, when these devices are operated in arrays, variations in unit to unit operating speed require external gating to assure all devices have completed an operation. The 'F403A incorporates simple but effective 'master/slave' interlocking circuitry to eliminate the need for external gating.
In the 'F403A array of Figure 6 devices 1 and 5 are defined as 'row masters' and the other devices are slaves to the master in their row. No slave in a given row will initialize its Input Register until it has received LOW on its IES input from a row master or a slave of higher priority.
In a similar fashion, the ORE outputs of slaves will not go HIGH until their OES inputs have gone HIGH. This interlock-
ing scheme ensures that new input data may be accepted by the array when the IRF output of the final slave in that row goes HIGH and that output data for the array may be extracted when the ORE of the final slave in the output row goes HIGH.
The row master is established by connecting its IES input to ground while a slave receives its IES input from the IRF output of the next higher priority device. When an array of 'F403A FIFOs is initialized with a LOW on the MR inputs of all devices, the IRF outputs of all devices will be HIGH. Thus, only the row master receives a LOW on the IES input during initialization. Figure 10 is a conceptual logic diagram of the internal circuitry which determines master/slave operation. Whenever MR and IES are LOW, the Master Latch is set. Whenever TTS goes LOW the Request Initialization Flip-Flop will be set. If the Master Latch is HIGH, the Input Register will be immediately initialized and the Request Initialization Flip-Flop reset. If the Master Latch is reset, the Input Register is not initialized until IES goes LOW. In array operation, activating the TTS initiates a ripple input register initialization from the row master to the last slave.
A similar operation takes place for the output register. Either a TOS or TOP input initiates a load-from-stack operation and sets the ORE Request Flip-Flop. If the Master Latch is set, the last Output Register Flip-Flop is set and ORE goes HIGH. If the Master Latch is reset, the ORE output will be LOW until an OES input is received.
. - - - - - - - - - PARALLEL DATA INPUT - - - - - - - - - - .
CPSI PL Ds
,.......
I
_il,
.....
ll, , , ...... ~~ ~
ullll
ri~ Ds D3 D2 D1 Do
~ IES
~ "" ,;.;...,.
CPSI OES
'F403A
IRF h.
~ TOS
..- TOP
~ p~~.q P-~ CPSO
ORE
~ OE
1' f;~Ds D3D2 D1 Do
LO'_;::: IES CPSI
IRF
i,.. I"
OES 'F403A
TOS
TOP
CPSO
ORE
OE
f;~Ds D3D2 D1 Do
IES
IRF p-,
CPSI
OES 'F403A TOS
TOP CPSO OE
ORE
~ ~
DATA READY
l.4R 03 02 01 Oo Os
o, l.4R0302 OoOs
l.4R03 02 010o0s
()
()
q
DUl.4P
CPSO
6E
SR _..._
, ~,
�~ I 03 02 01 Oo
� ��
07 Os 05 04
.,, ~,~
'-�- - - - - - - - PARALLEL DATA O U T P U T - - - - - - - - -
FIGURE 5. A Horizontal Expansion Scheme
TL/F/9536-9
4-335
<
C")
~ Functional Description (Continued)
SERIAL DATA INPUT PARALLEL LOAD INPUT CLOCK
. - - - - - - - - - - - PARALLEL DATA INPUT - - - - - - - - - - - - .
l?D5D5D4
D11D10 Dg Da
jjjj
'
J.
I
l
OUTPUT ENABLE OUTPUT CLOCK DUMP
SERIAL DATA OUTPUT
~ "'~
�
._0! _3_02_0_10_0_ _ _ _ _ _0_1_o&_o_so.PARALLEL DATA OUTPUTo_,,_0_10_0_9o_a_ _ _ _ _ _ _ _....
FIGURE 6. A 31x16 FIFO Array
TL/F/9536-10
4-336
Functional Description (Continued)
DEVICE 1
DEVICE 2 IRF
DEVICE 3
to-I::I -
...~~~~~~~~~~~~~~~~~~~--~--!~
I'
to-I-:I
'
~
I'
--------...-..-:I~:I -'to
_____,qI' -
DEVICE 4/TTS ALL DEVICES
_,' ;...-t
I I
0
I '
INPUTS O BITS
2
STORE IN DEVICE 1
I I I 7
a
9 10 11 12 13 14 1s
STORE IN DEVICE 2
STORE IN DEVICE 3
STORE IN DEVICE 4
FIGURE 7. Serial Data Entry for Array of Figure 6
TL/F/9536-11
to-I::I -
DEVICE 5
----~~------~~~~~~~~~~~~~~~...-.;~
DEVICE 6
______ I' to.-I.-,:I I..'iI......,
DEVICE 7 ORE
DEVICE 8, TOS ALL DEVICES ORE
SERIAL DATA OUTPUT
-:I :I -to I'
_,' ;...-t
I I
0
I '
DEVICE 5
DEVICE 6
DEVICE 7
DEVICE 8
FIGURE 8. Serial Data Extraction for Array of Figure 6
TL/F/9536-12
4.337
<(
C")
~ Functional Description (Continued)
SERIAL
03 D2 D1 Do
INPUT Ds
'f403A
'f403A
'f403A
'f403A
'f403A Os
'f403A Os
'f403A Os
'f403A
._B,.1s.....,B1,_4_B_,13..8...1, .,.2....,,..... SERIAL OUTPUT
Os
FIGURE 9. Final Position of a 496-Bit Serial Input
TL/F/9536-13
PL---~:>--f--------f.---+
iiR----01
t.lASTER LATCH
re t--f>o-� iRi'
(SEE FIGURE 1)
�-----------.....----1---_.. INITIALIZE (SEE FIGURE 1)
- - - - s INPUT REG- STACK
(DERIVED FROt.l ITS)
REQUEST
INTIALIZATION
FLIP-FLOP
R
FLIP-FLOP R
LOAD OUTPUT (DERIVED FROt.l TOP AND TOS) REGISTER
TOP-------------
ros -------------+-~
OES-------------+---------~
FX (SEE FIGURE 2)
FIGURE 10. Conceptual Diagram, Interlocking Circuitry
TL/F/9536-14
4-338
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
-55�C to+ 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to + 7.0V
Input Voltage (Note 2)
-0.5Vto +7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
-0.5VtoVee -0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
ESD Last Passing Voltage (Min)
4000V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
V1H
Input HIGH Voltage
V1L
Input LOW Voltage
Veo
Input Clamp Diode Voltage
54F/74F
Min Typ
Max
Units Vee
Conditions
2.0
v
Recognized as a HIGH Signal
0.8
v
Recognized as a LOW Signal
-1.5
v
Min l1N = -18 mA
VoH
Output HIGH
54F 10% Vee 2.4
Voltage
54F 10% Vee 2.4
74F 10% Vee 2.5
74F 10% Vee 2.5
74F5% Vee
2.7
74F5% Vee
2.7
loH = -400 �A (IRF, ORE)
loH = - 2.0 mA (On. Os)
v
loH = -400 �A (IRF, ORE) Min
loH = -5.7 mA (On, Os)
loH = -400 �A (IRF, ORE)
loH = - 5. 7 mA (On, Os)
Vm
Output LOW
54F 10% Vee
Voltage
54F 10% Vee
74F 10% Vee
74F 10% Vee
0.4
loL = 4 mA (IRF, ORE)
0.4
v
Min
loL = 8 mA (On, Os)
0.5
loL = 8 mA (IRF, ORE)
0.5
loL = 16 mA (On, Os)
l1H
Input HIGH Current
20
�A
Max V1N = 2.7V
lsv1
Input HIGH Current
Breakdown Test
100
�A
Max V1N = 7.0V
l1L
Input LOW Current
-0.4
mA
Max V1N = 0.5V
lozH
Output Leakage Current
50
�A
Max VouT = 2.7V
lozL
Output Leakage Current
los
Output Short-Circuit Current
-20
-50
�A
Max VouT = 0.5V
-130
mA
Max Vour = ov
leEx
Output HIGH Leakage Current
250
�A
Max Vour =Vee
leeL
Power Supply Current
170
mA
Max Vo= LOW
4-339
AC Electrical Characteristics
Symbol
Parameter
tPHL
tPLH
tPLH tPHL tPLH tPHL tPHL
tPHL
tPLH
tpLH
IPHL
tPLH
Propagation Delay, Negative-Going CPSI to IRF Output
Propagation Delay, Negative-Going TTSto IRF
Propagation Delay, Negative-Going CPSO to Os Output
Propagation Delay, Positive-Going TOP to Outputs Oo-03
Propagation Delay, Negative-Going CPSOtoORE
Propagation Delay, Negative-Going TOP to ORE
Propagation Delay, Positive-Going TOP to ORE
Propagation Delay, Negative-Going TOS to Positive Going ORE
Propagation Delay, Positive-Going PL to Negative-Going IRF
Propagation Delay, Negative-Going PL to Positive-Going IRF
74F
TA= +25�C Vee= +5.0V
CL= 50pF
Min
Max
7.5
14.0
11.0
8.5 8.0
10.0 8.5
20.5
17.0 14.5
18.0 15.5
9.5
17.5
8.0
15.0
12.5
22.0
12.5
22.0
7.0
13.0
9.5
17.0
54F
TA, Vee= Mil CL= 50 pf
Min
Max
74F
TA, Vee= Com CL= 50 pf
Units
Fig. No.
Min
Max
7.0
15.0
ns 403-a, b
10.0
22.5
7.5
18.5
7.0
15.5
ns 403-c, d
9.0
20.0
8.0
16.5
ns
403-e
9.0
19.0
ns
403-c, d
7.5
16.5
ns
403-e
11.5
25.0
11.0
25.0
ns 403-c, d
6.5
14.0
ns 403-g, h
8.5
19.5
4-340
AC Electrical Characteristics (Continued)
Symbol
Parameter
tPLH
tPLH
tPLH
tPHL
tpzH tpzL tpHz tpLz tpzH tpzL
tpHz tpLz
tpzH tpzL to FT tAP
tAs
Propagation Delay, Positive-Going OES to ORE
Propagation Delay, Positive-Going IES to Positive-Going IRF
Propagation Delay, MR to IRF
Propagation Delay, MR to ORE
Propagation Delay, OE to Oo. 01, 02, 03
Propagation Delay, OE to Oo, 01, 02, 03
Propagation Delay, Negative-Going OEStoOs
Propagation Delay, Negative-Going OEStoOs
Turn On Time T0Sto05 Fall Through Time
Parallel Appearance Time, OREtoOo-03 Serial Appearance Time, ORE to Os
74F
TA= +25�C Vee= +5.0V
CL= 50 pf
Min
Max
10.0
18.0
8.5
15.5
8.0
9.0
2.5 2.5 2.5 2.5 5.5 5.5
5.5 5.5
8.5 8.5 45.0
-10.0
-10.0
15.0
16.0
6.5 7.5 6.5 7.5 12.0 14.0
12.0 14.5
21.0 20.0 80.0
-1.0
2.0
54F
TA, Vee= Mil CL= 50 pf
Min
Max
74F
TA, Vee= Com
Units
Fig.
CL= 50 pf
No.
Min
Max
9.0
20.5
ns
7.5
17.5
ns
403-h
7.5
8.0
2.0 2.0 2.0 2.0 5.0 5.0
5.0 5.0
8.0 8.0 35.0
-10.0
-10.0
17.0
17.5
8.0 8.5 8.0 8.0 15.0 15.0
14.0 16.0
24.0 21.0 95.0
-1.0
2.0
ns ns ns
ns
ns
ns
403-f
ns
4-341
AC Operating Requirements
Symbol
Parameter
t 5(H) t5(L) th(H) th(L) t 5(L)
t 5(L)
t 5 (L)
t5 (L)
t5 (H) t5 (L) th(H) th(L) !w(H) lw(L) lw(H) lw(L)
tw(L) tw(H) tw(L) tw(H) tw(L) tree
Set-up Time HIGH or LOW
0 5 to Negative CPSI
Hold Time, HIGH or LOW
0 5 to CPSI
Set-up Time, LOW TTSto IRF Serial or Parallel Mode
Set-up Time, LOW Negative-Going ORE to Negative-Going TOS
Set-up Time, LOW Negative-Going IES to CPSI
Set-up Time, LOW Negative-Going TTS to CPSI
Set-up Time, HIGH or LOW Parallel Inputs to PL
Hold Time, HIGH or LOW Parallel Inputs to PL
CPSI Pulse Width HIGH or LOW
PL Pulse Width, HIGH
TTS Pulse Width, LOW Serial or Parallel Mode
MR Pulse Width, LOW
TOP Pulse Width HIGH or LOW
CPSO Pulse Width HIGH or LOW
Recovery Time MR to Any input
74F
TA= +2s0 c Vee= +s.ov
Min
Max
1.0 1.0
3.5 3.5
0
0
3.0
14.0
0 0 2.0 2.0 5.0 3.0 4.0
3.5
3.5 4.5 3.5 4.5 3.0
5.0
54F
TA, Vee= Mil
Min
Max
74F
TA, Vee= Com
Min
Max
1.0 1.0
3.5 3.5
0
Fig.
Units No.
ns
403-a, b
403-a, b, ns
g,h
0
ns
403-c, d
4.0
15.5
0 0 2.5 2.5 6.0 5.0 5.0
4.0
4.0 5.5 4.0 5.5 4.0
5.5
ns
403-b
ns
403-b
ns
ns
403-a, b
ns
403-g, h
403-a, b, ns
c, d
ns
403-f
ns
403-e
ns
403-c, d
ns
403-f
4-342
Timing Waveforms
Conditions: stack not full, ~. PL LOW
FIGURE 403-a. Serial Input, Unexpanded or Master Operation
TL/F/9536-15
Conditions: stack not full, ~ HIGH when initiated, PL LOW
FIGURE 403-b. Serial Input, Expanded Slave Operation
TL/F/9536-16
Conditions: data in stack, TOP HIGH, IES LOW when initiated, DES LOW FIGURE 403-c. Serial Output, Unexpanded or Master Operation
TL/F /9536-17
4-343
c:t
C")
~ Timing Waveforms (Continued)
Conditions: data in stack, TOP HIGH, ~ HIGH when initiated
FIGURE 403-d. Serial Output, Slave Operation
TOP
TL/F /9536-18
o-o tPLH tPHL
=1~
~--------------------------,-.5-V---~~N-EW---OU_T_P-UT----
03
Conditions: IES LOW when initiated, OE, CPSO LOW; data available in stack FIGURE 403-e. Parallel Output, 4-Blt Word or Master In Parallel Expansion
TL/F/9536-19
Conditions: TTS connected to IRF, TOS connected to ORE, IES, DES, OE, CPSO LOW, TOP HIGH FIGURE 403-f. Fall Through Time
TL/F/9536-20
4-344
Timing Waveforms (Continued)
tw
IL
PL
j
-I ts t-
'XY.'X
~
~
\
-I th t-
1.5V STABLE 1.5V
'Y'X'X'X
N
v
7 1.5V
- th t-
tPHL
TTS (note 2)
1.5V (note 3) t,=O
Conditions: stack not full, TES LOW when initialized FIGURE 403-g. Parallel Load Mode, 4-Bit Word (Unexpanded) or Master In Parallel Expansion
TL/F/9536-21
Conditions: stack not full, device initialized (Note 1) with IES HIGH
FIGURE 403-h. Parallel Load, Slave Mode
Note 1: Initialization requires a master reset to occur after power has been applied. Nole 2: TTS normally connected to IRF.
Nole 3: If stack is full, TRF will stay LOW.
TL/F/9536-22
4-345
~UNaStemiicoonnduactlor
54F/74F407
Data Access Register
General Description
The 'F407 Data Access Register (DAR) performs memory address arithmetic for RAM resident stack applications. It contains three 4-bit registers intended for Program Counter (Ro), Stack Pointer (R1), and Operand Address (R2). The 'F407 implements 16 instructions which allow either pre- or post-decrement/increment and register-to-register transfer in a single clock cycle. It is expandable in 4-bit increments and can operate at a 30 MHz microinstruction rate on a 16-bit word. The TRI-STATE� outputs are provided for busoriented applications. The 'F407 is fully compatible with all TTL families.
Features
� High-speed-greater than a 30 MHz microinstruction rate
� Three 4-bit registers � 16 instructions for register manipulation � Two separate output ports, one transparent � Relative addressing capability � TRI-STATE Outputs � Optional pre- or post- arithmetic � Expandable in multiples of four bits � 24-pin slim package � 9407 replacement
Ordering Code: see sections
Logic Symbol
Connection Diagrams
co
TL/F/9537-3
Pin Assignment for DIP, SOIC and Flatpak
EX 1 lo
12 13
rox 6 CP 7 Xo
x,
X2 10
X3 11 GND 12
24 Yee
23 a
22 roo 21 Do 20 Oo
19 o, 18 o,
17 ii2 16 02 15 03 14 03
13 co
TL/F/9537-1
Pin Assignment for LCC
X1 Xo CP NC EOx 13 12 [j] [QI []] I]] ILi [�] [[]
X2 fi1]
X3 lil!
GND iG]
NC fill
co [i]I
03 lill
D3 IJ]]
rn 11 imll 150
[i]NC
~Yee
lll!Ci
~E<io
li]J@l[i]~g]~~
62 ii2 61 NC ii1 60 ii0
TL/F/9537-2
Unit Loading/Fan Out: See Section 2 for u.L. definitions
54F/74F
Pin Names
Description
U.L. HIGH/LOW
Input l1Hll1L Output loHlloL
Do-53 lo-13
Ci
co
CP EX
EOx EOo Xo-X3 Oo-03
Data Inputs (Active LOW)
1.0/0.67
20 �A/-0.4 mA
Instruction Word Inputs
1.0/0.67
20 �A/-0.4 mA
Carry Input (Active LOW)
1.0/0.67
20 �A/-0.4 mA
Carry Output (Active LOW)
20/13.3 (0.67)
0.4 mA/8 mA (4 mA)
Clock Input (L-H Edge-Triggered)
1.0/0.67
20 �A/ - 0.4 mA
Execute Input (Active LOW)
1.0/0.67
20 �A/-0.4 mA
Address Output Enable Input (Active LOW)
1.0/0.67
20 �A/-0.4 mA
Data Output Enable Input (Active LOW)
1.0/0.67
20 �A/-0.4 mA
Address Outputs
284 (100)/26.7 (13.3) -5.7 mA (2 mA)/16 mA (8 mA)
Data Outputs (Active LOW)
284 (100)/26.7 (13.3) -5.7 mA (2 mA)/16 mA (8 mA)
4-346
Functional Description
The 'F407 contains a 4-bit slice of three Registers (R0 -R2), a 4-bit Adder, a TRI-STATE Address Output Buffer (Xo-X3) and a separate Output Register with TRI-STATE buffers (Oo-03), allowing output of the register contents on the data bus (refer to the Block Diagram). The DAR performs sixteen instructions, selected by 10 -13, as listed in the Function Table.
The 'F407 operates on a single clock. CP and EX are inputs to a 2-input, active LOW AND gate. For normal operation EX is brought LOW while CP is HIGH. A microcycle starts as the
clock goes HIGH. Data inputs 50-53 are applied to the
Adder as one of the operands. Three of the four instruction lines (l1-l2-l3) select which of the three registers, if any, is to be used as the other operand. The LOW-to-HIGH CP transition writes the result from the Adder into a register (Ro-R2) and into the output register provided EX is LOW. If
the lo instruction input is HIGH, the multiplexer routes the result from the Adder to the TRI-STATE Buffer controlling the address bus (Xo-X3), independent of EX and CP. The
er'F407 is organized as a 4-bit register slice. The active LOW
co and lines allow ripple-carry expansion over longer
word lengths.
In a typical application, the register utilization in the DAR may be as follows: Ro is the Program Counter (PC), R1 is the Stack Pointer (SP) for memory resident stacks and R2 contains the operand address. For an instruction Fetch, PC can be gated on the X-Bus while it is being incremented (i.e., D-Bus = 1). If the fetched instruction calls for an effective address for execution, which is displaced from the PC, the displacement can be added to the PC and loaded into R2 during the next microcycle.
Function Table
Instruction
Combinatorial Function
13
12
11
lo
Available on the X-Bus
Sequential Function Occurring on the Next Rising CP Edge
L
L
L
L
Ro
L
L
L
H
Ro Plus D Plus Cl
L
L
H
L
Ro
L
L
H
H
Ro Plus D Plus Cl
L
H
L
L
Ro
L
H
L
H
Ro Plus D Plus Cl
L
H
H
L
R1
L
H
H
H
R1 Plus D Plus Cl
H
L
L
L
R2
H
L
L
H
D Plus Cl
H
L
H
L
Ro
H
L
H
H
D Plus Cl
H
H
L
L
R2
H
H
L
H
R2 Plus D Plus Cl
H
H
H
L
R1
H
H
H
H
D Plus Cl
H = HIGH Voltage Level L = LOW Voltage Level
Ro Plus D Plus Cl ~ Ro and 0-Register Ro Plus D Plus Cl ~ R1 and 0-Register Ro Plus D Plus Cl ~ R2 and 0-Register R1 Plus D Plus Cl ~ R1 and 0-Register D Plus Cl ~ R2 and 0-Register D Plus Cl ~ Ro and 0-Register R2 Plus D Plus Cl ~ R2 and 0-Register D Plus Cl ~ R1 and0-Register
4-347
Block Diagram
a
_l
[" al e2 e, Bo A3 A2 A1 Ao
co
S3 S2 s, So MJ
1
J J
]
L
INSTRUCTION DECODER ENCODER
l
~ ilL
r---
So
s,
S2
Cl'
fX
_J
l l l 1
D3 D2 D1 Do
CP
4-BIT REG. (Ro)
03 02 01 Oo
QUAD 3-IHPUT
MUX
i�.l. l�111 ~~CP 4-BIT REG.
.__l (R,J
L.:=loA loe loc
loo
03 02 01 Oo
ZA I-<
Zat-1--'
Zct-1-H
Z o t -~
lu
D3 .1..1'jJlll
118 l1c 110
pl'Cl'
4-BIT REG. (R2)
03 02 01 Oo
12A l2e
'2c
120
""------"
llii
4�� �.. '] CP 4-BIT REG. (R3)
03 02 01 Oo
.C::::::2 :s~
1TI1ft o,
4"S'
"'
11 l "' "' .. "' ". 2-IHPUT MUX
. J
Zo
Zc
Ze
ZA
lf4~1+
TL/F/9537-4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-348
Timing Diagrams
EOx =LOW
1.5 v
EOo =LOW
FIGURE 407-a
EOx =LOW
71(_1.SV
_____. ~:;~~j------~ 1.5V
FIGURE 407-b
TL/F/9537-B
TL/F/9537-7
CLOCK (NOTE 1)
EOx = LOW, lo = HIGH
ttPHP L L H k
---------------- co
1.5 V
----------------- TL/F/9537-9
FIGURE 407-c
1.5V
EOx = LOW, lo = HIGH
1.5V
FIGURE 407-d
TL/F/9537-5
4-349
FIGURE 407-e
TL/F/9537-6
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to + 7.0V
Input Voltage (Note 2)
-0.5V to + 7.0V
Input Current (Note 2)
- 30 mA to + 5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
-0.5V to Vee -0.5V to +5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol V1H V1L Veo VoH
VoL
l1H lsv1 lcEx V10 loo l1L lozH lozL los Ice
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee 74F5% Vee 74F5% Vee
Output LOW Voltage
54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage
74F
Test
Output Leakage
74F
Circuit Current
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Power Supply Current
54F/74F
Min Typ Max
2.0
0.8
-1.5
2.4 2.4 2.4 2.4 2.4 2.7
0.5 0.5 0.5 0.5
20.0 5.0
100 7.0
250 50
4.75
3.75
-0.4
50
-50
-30
-100
90
145
Units
v v v
v
v
�A �A �A
v
�A mA �A �A mA mA
Vee
Conditions
Recognized as a HIGH Signal
Recognized as a LOW Signal
Min l1N = -18 mA
loH = -0.4 mA (CO) loH = -2 mA (Xo-X3, Oo-03) Min loH = -0.4 mA (CO) loH = -5.7 mA (Xo-X3, Oo-03) loH = -0.4 mA (CO) loH = -5.7 mA (Xo-X3, Oo-03)
loL = 4 mA (CO) Min loL = 8 mA (Xo-X3, Oo-03)
loL = 8 mA (CO) loL = 16 mA (Xo-X3, Oo-03)
Max V1N = 2.7V
Max V1N = 7.0V
Max Vour =Vee
0.0
110 = 1.9 �A All Other Pins Grounded
0.0
V100 = 150mV All Other Pins Grounded
Max V1N = 0.5V
Max Vour = 2.7V (Xo-X3, Oo-03)
Max Vour = 0.5V (Xo-X3, Oo-03)
Max Vour = ov
Max
4-350
AC Electrical Characteristics
74F
54F
74F
Symbol
Parameter
TA= +25�C Vee= +5.0V
CL= 50 pF
TA, Vee= Mil CL= 50 pF
TA, Vee= Com CL= 50 pF
Min
Typ
Max
Min
Max
Min
Max
tPLH tPHL
Propagation Delay CP to On (Note 1)
8.0
12.0
21.0
7.0
24.0
7.0
25.0
5.0
7.5
13.0
4.0
15.0
4.0
15.0
tPLH tPHL
tPLH tPHL
tPLH tPHL
tPLH tPHL
Propagation Delay, lo LOW
9.0
13.0
18.0
7.5
21.0
8.0
20.0
l1-l3t0Xo-X3
9.5
14.0
20.5
8.0
25.0
8.5
22.0
Propagation Delay, lo HIGH 16.5
23.5
33.0
8.5
50.0
14.5
36.0
l1-l3 to Xo-X3
11.0
17.0
25.0
6.5
35.0
10.0
27.0
Propagation Delay, lo LOW
9.0
13.5
21.0
7.0
24.0
8.0
22.5
CP to Xn
11.5
18.0
24.0
8.5
28.0
10.5
26.0
Propagation Delay, 10 HIGH 18.0
26.5
35.0
16.0
43.0
16.0
37.0
CP to Xn
12.5
20.0
28.5
11.5
36.5
11.5
31.0
tPLH tPHL
Propagation Delay Dn toXn
10.5
15.0
23.0
6.5
29.0
9.5
25.0
6.0
9.0
14.0
3.0
20.5
5.0
15.5
tPLH
Propagation Delay
tPHL
CltoXn
7.0
10.5
16.0
4.0
22.0
6.0
17.5
5.5
9.0
12.0
4.5
14.0
4.5
13.5
tPLH
Propagation Delay
tPHL
lotoXn
4.5
9.0
11.5
4.0
14.5
4.0
13.0
4.5
10.0
14.0
3.0
19.5
4.0
15.5
tPLH
Propagation Delay
tPHL
CPtoCO
11.0
19.0
24.0
9.0
33.0
11.0
26.0
11.5
18.5
27.0
6.5
38.0
11.5
29.0
tPLH tPHL
tPLH tPHL
tPLH tPHL
tpzH tpzL
Propagation Delay Cito CO
Propagation Delay Dn to CO
Propagation Delay l1-l3toCO
Enable Time EOo to On or EOx to Xn
3.5
5.5
8.5
3.0
11.0
3.0
9.5
4.5
7.0
12.0
3.0
10.0
4.0
13.0
3.5
5.5
9.0
3.0
10.0
3.0
9.5
4.0
6.5
11.0
3.5
10.0
3.5
12.0
10.0
15.0
22.0
8.0
23.0
9.0
23.5
11.0
16.0
23.0
6.0
32.5
10.0
25.0
7.0
10.0
14.5
4.5
26.0
5.5
17.0
6.0
9.0
15.0
3.5
16.0
5.5
16.5
tpHz
Disable Time
1.5
4.0
7.0
2.0
9.0
1.5
8.0
tpLz
EOo to On or EOx to Xn
5.0
10.0
14.0
5.0
18.0
4.0
15.5
Note 1: The internal clock is generated from GP and EX. The internal Clock is HIGH if EX or GP is HIGH, LOW if EX and GP are LOW.
Fig. Units
No.
ns 407-c ns 407-a ns 407-a ns 407-b ns 407-b ns 407-d ns 407-e ns 407-b ns 407-a ns 407-e ns 407-d ns 407-a ns ns
4-351
AC Electrical Characteristics
Symbol
Parameter
tcw t 5(H) t 5(L) th(H) th(L)
t5(H) t5(L) th(H) th(L)
t5(H) t5(L) th(H) th(L)
tw(H) tw(L)
Clock Period
Setup Time, HIGH or LOW I1-13 to Negative-Going CP
Hold Time, HIGH or LOW l1-l3 to Positive-Going CP
Setup Time, HIGH or LOW
Dn or C1 to Negative-Going CP
Hold Time, HIGH or LOW
Dn or Ci to
Negative-Going Clock
Setup Time, HIGH or LOW
Ci to Positive-Going CP
Hold Time, HIGH or LOW
Ci to Positive-Going CP
Clock Pulse Width HIGH or LOW
74F
TA= +25�C Vee= +5.0V
CL= 50 pF
Min
Typ
Max
32.0
26.0
4.0 4.0
0 0
16.5 16.5
0 0
13.0 13.0
0 0
7.5 7.5
54F
TA, Vee= Mil CL= 50 pF
Min
36.0
4.5 4.5
0 0
18.5 18.5
0 0
Max
74F
TA, Vee= Com Units Fig.
CL= 50 pF
No.
Min
36.0
4.5 4.5
0 0
18.5 18.5
0 0
Max
ns ns 407-c
ns 407-c
14.5 14.5
0 0
8.5 8.5
14.5 14.5
0 0
8.5 8.5
ns 407-c ns 407-c
4-352
~National
~Semiconductor
54F/74F410 Register Stack-16 x 4 RAM TRI-STATE� Output Register
General Description
The 'F410 is a register-oriented high-speed 64-bit Read/ Write Memory organized as 16-words by 4-bits. An edgetriggered 4-bit output register allows new input data to be written while previous data is held. TRI-STATE outputs are provided for maximum versatility. The 'F41 O is fully compatible with all TTL families.
Features
� Edge-triggered output register � Typical access time of 35 ns � TRI-STATE outputs � Optimized for register stack operation � 18-pin package � 941 O replacement
Ordering Code: see section 5 Logic Symbols
Connection Diagrams
Do D1 D2 03
Oo 01 02 03 TL/F/9538-3
Pin Assignment for DIP and Flatpak
cs 1
WE
Ao A1 4 A2 5 A5 6 CP 7
6E
GND
18 Vee 17 Do 16 Oo 15 D1 14 01 13 D2 12 02 11 D3 10 03
TL/F/9538-1
Pin Assignment for LCC
CP A3 NC A2 A1
[[] [[) [[] @J III
0
� GNO D [QE I [ i ] D I T J A [II~
03 (j]
mcs
D3 lJll
~Vee
02 ILll
II2!Do
[j}] fill [ill [j] !ill
Di 01 NC D1 Oo
TL/F/9538-2
Unit Loading/Fan Out: See Section 2 for U.L. Definitions
Pin Names
Ao-A3 Do-D3 cs OE WE CP
Oo-03
Description
Address Inputs Data Inputs Chip Select Input (Active LOW) Output Enable Input (Active LOW) Write Enable Input (Active LOW) Clock Input (Outputs Change on LOW-to-HIGH Transition) TRI-STATE Outputs
U.L. HIGH/LOW
1.0/1.0 1.0/1.0 1.0/2.0 1.0/1.0 1.0/1.0
54F/74F
Input l1Hll1L Output loHlloL
20 �A/-0.6 mA 20 �A/-0.6 mA 20 �A/-1.2 mA 20 �A/-0.6 mA 20 �A/-0.6 mA
1.0/2.0 150/40 (33.3)
20 �A/-1.2 mA -3 mA/24 mA (20 mA)
4-353
Functional Description
Write Operation-When the three control inputs, Write Enable (WE), Chip Select (CS), and Clock (CP), are LOW the information on the data inputs (00 -03) is written into the memory location selected by the address inputs (Ao-A3). If the input data changes while WE, CS, and CP are LOW, the contents of the selected memory location follow these changes, provided setup and hold time criteria are met.
Block Diagram
Read Operation-Whenever CS is LOW and CP goes from LOW-to-HIGH, the contents of the memory location selected by the address inputs (A0 -A3) are edge-triggered into the Output Register.
The (OE) input controls the output buffers. When OE is HIGH the four outputs (00-03) are in a high impedance or OFF state; when OE is LOW, the outputs are determined by the state of the Output Register.
Ao
A1
ADDRESS
16
DECODE
RAM
A2
A3
DATA INPUTS
REGISTER
01
02
1 - - - - - OE
TL/F/9538-4
4-354
Absolute Maximum Ratings (Note 1)
If MilitaryI Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vcc Pin Potential to Ground Pin
-0.5V to + 7.0V
Input Voltage (Note 2)
-0.5V to + 7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
-0.5VtoVcc -0.5Vto +5.5V
Current Applied to Output
in LOW State (Max)
twice the rated loL (m.A)
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
.~ .....
Recommended Operating
0
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�c o�cto +70�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol V1H V1L Vco VoH
VoL l1H lsv1 le EX V10 loo l1L lozH lozL los lzz
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee 74F5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage 74F
Test
Output Leakage 74F
Circuit Current
Input LOW Current
Output Leakage Current Output Leakage Current Output Short-Circuit Current Bus Drainage Test
54F/74F Min Typ Max 2.0
0.8 -1.2 2.5 2.4 2.5 2.4 2.7 0.5 0.5 20.0 5.0 100 7.0 250
50
4.75
3.75
-0.6 -1.2
50
-50
-60
-150
500
Units v v v
v
v �A �A �A v �A mA �A �A mA �A
Vee
Min
Min
Min Max Max Max 0.0 0.0 Max Max Max Max o.ov
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal l1N = -18 mA loH = -1 mA loH = -3mA loH = -1 mA loH = -3mA loH = -1 mA IQL = 20 mA loL = 24 mA
V1N = 2.7V
V1N = 7.0V
VouT =Vee
110 = 1.9 �A All Other Pins Grounded V100 = 150 mV All Other Pins Grounded V1N = 0.5V (An. Dn. OE, WE) V1N = 0.5V (CS, CP) VouT = 2.7V VouT = 0.5V VouT = ov VouT = 5.25V
4-355
0...... "'=f' DC Electrical Characteristics (Continued)
Symbol
Parameter
54F/74F
Units
Vee
Min
Typ
Max
Conditions
lccH
Power Supply Current
47
70
mA
Max
Vo= HIGH
lccL
Power Supply Current
lccz
Power Supply Current
47
70
mA
Max
Vo= LOW
47
70
mA
Max
Vo= HIGHZ
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
tPLH
Propagation Delay
tPHL
CPtoQ
tpzH
Enable Time
tpzL
OEtoQ
tpHz
Disable Time
tpLz
OEtoQ
74F
TA= +25�C Vee= +5.0V
CL= 50 pF
Min
Max
3.0
8.5
3.5
9.0
3.0
8.0
3.5
9.0
2.5
6.5
2.5
7.0
54F
TA, Vee= Mil CL= 50 pF
Min
Max
2.5
11.0
3.0
12.0
2.5
10.5
3.0
13.0
2.0
8.5
2.0
9.5
74F
TA, Vee= Com CL= 50pF
Min
Max
2.5
9.5
3.0
10.0
2.5
9.0
3.0
10.0
2.0
7.5
2.0
8.0
Fig. Units
No.
ns
2-3
ns
2-5
AC Operating Requirements: See Section 2 for Waveforms
Symbol
Parameter
READ MODE
t5 (H) t 5 (L)
th(H) th(L)
Setup Time, HIGH or LOW An to CP
Hold Time, HIGH or LOW An to CP
WRITE MODE
t5 (H) t5 (L)
th(H) th(L)
Setup Time, HIGH or LOW An to WE
Hold Time, HIGH or LOW An to WE
t5 (H) t 5 (L)
th(H) th(L)
Setup Time, HIGH or LOW Dn to WE
Hold Time, HIGH or LOW Dn to WE
WE Pulse Width
tw
Required to Write
CS Pulse Width
tw
Required to Write
CP Pulse Width
tw
Required to Write
74F
TA= +25�C Vee= +5.0V
Min
Max
15.0 15.0
0 0
0 0 0 0 5.0 5.0 0 0
7.5
7.5
7.5
54F
TA, Vee= Mil
Min
Max
23 23
0 0
0 0 0 0 8.5 8.5 2.5 2.5
9.5
9.5
9.5
74F
TA, Vee= Com
Min
Max
Fig. Units
No.
17.0
17.0
ns
2-6
0
0
0
0
ns
2-6
0
0
6.0
6.0
ns
2-6
0
0
8.5
ns
2-4
8.5
ns
2-4
8.5
ns
2-4
Note: Military temperature range for this device is -40�C to + 85�C.
1
4-356
~National
U Semiconductor
54F/74F412
Multi-Mode Buffered Latch with TRI-STATE� Outputs
General Description
The 'F412 is an 8-bit latch with TRI-STATE output buffers. Also included is a status flip-flop for providing device-busy or request-interrupt commands. Separate Mode and Select inputs allow data to be stored with the outputs enabled or disabled. The device can also operate in a fully transparent mode. The 'F412 is the functional equivalent of the Intel 8212.
Features
� TRI-STATE outputs � Status flip-flop for interrupt commands � Asynchronous or latched receiver modes � 300 mil 24-pin slim package
Ordering Code: see section 5 Logic Symbols
I E E E / I EC (1/0 PORT)
Do
Oo
D1
01
D2
02
D3
03
D4
04
D5
05
Ds
Os
0.,
07
TL/F/9540-4
-Q CLR
STB S1 S2
INT 0 -
00 01 o2 03 04 05 05 07
TL/F /9540-1
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
51 1 t.t
Do Oo 4
o, 5 o,
D2 02 8 D3 9 03 10 STB 11
GND 12
24 Vee 23 iNf
22 D7 21 07 20 Ds 19 Os 18 D5 17 05 16 D4 15 04
14 CCR
13 S2
TL/F/9540-2
Pin Assignment for LCC
D3 [jJ
02 [QI
rDn2
NC
[[]
m0 1
[D]]1
Oo
rn
03 [j]] STB [j]] GND [j] NC [ill S2 [j]] CLR [j1J 04 [j]]
[}]Do
[I] M
!1J 51
D]NC
~Vee ~iNT ~D7
[j]]~(I1]!nl~~~ D4 05 D5 NC 06 06 07
TL/F /9540-3
IJ
4-357
Unit Loading/Fan Out: See Section 2 for U.L. definitions
Pin Names
Oo-07 Do-D7 CLR STB INT M S1,S2
Description
Latch Outputs Data Inputs Clear Strobe Interrupt Mode Control Input Select Inputs
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loHlloL
150/40 (33.3) 1.0/1.0 1.0/1.0 1.0/1.0 50/33.3 1.0/1.0 1.0/1.0
-3 mA/24 mA (20 mA) 20 �Al -0.6 mA 20 �A/ - 0.6 mA 20 �A/-0.6 mA -1 mA/20 mA 20 �A/-0.6 mA 20 �A/ -0.6 mA
Functional Description
This high-performance eight-bit parallel expandable buffer register incorporates package and mode selection inputs and an edge-triggered status flip-flop designed specifically for implementing bus-organized input/output ports. The TRI-STATE data outputs can be connected to a common data bus and controlled from the appropriate select inputs to receive or transmit data. An integral status flip-flop provides busy or request interrupt commands.
The eight data latches are fully transparent when the internal gate enable, G, input is HIGH and the outputs are enabled. Latch transparency is selected by the mode control (M), select (S1 and S2), and the strobe (STB) inputs and during transparency each data output (On) follows its respective data input (Dn). This mode of operation can be terminated by clearing, de-selecting, or holding the data latches.
An input mode or an output mode is selectable from the M input. In the input mode, M = L, the eight data latch inputs are enabled when the strobe is HIGH regardless of device selection. If selected during an input mode, the outputs will follow the data inputs. When the strobe input is taken LOW, the latches will store the most-recently setup data.
In the output mode, M = H, the output buffers are enabled regardless of any other control input. During the output mode the content of the register is under control of the select (S1 and S2) inputs.
Data Latches Function Table
Function
CLR
M
51
52
STB
Data In
Data Out
Clear
L
H
H
x
x
x
L
L
L
L
H
L
x
L
De-Select
x
L
x
L
x
x
z
x
L
H
x
x
x
z
Hold
H
H
H
L
x
x
Oo
H
L
L
H
L
x
Oo
Data Bus
H
H
L
H
x
L
L
H
H
L
H
x
H
H
Data Bus
H
L
L
H
H
L
L
H
L
L
H
H
H
H
Status Flip-Flop Function Table
CLR
51
52
STB
INT
L
H
x
x
H
L
x
L
x
H
H
x
x
_r
L
H
L
H
x
L
H = HIGH Voltage Level L = LOW Voltage Level
X = Immaterial
Z = High Impedance .../' = LOW-to-HIGH Clock Transition
4-358
Logic Diagram
STB M
S1
S2
iNT
OE
Do Oo
D1 01
D2 02
D3 03
D-4 04
D5 05
D5 05
D7 07
CLR
TL/F/9540-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-359
"....'.
~ Absolute Maximum Ratings <Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
-55�C to+ 175�C
Vee Pin Potential to Ground Pin
-0.5Vto +7.0V
Input Voltage (Note 2)
-0.5V to + 7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
-0.5VtoVee -0.5V to + 5.5V
Current Applied to Output
in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
V1H V1L Veo VoH
VoL
l1H Isv1 le Ex V10 loo l1L lozH lozL las lzz lceH lceL Icez
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee 74F5% Vee 74F5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage Test
74F
Output Leakage Circuit Current
74F
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Bus Drainage Test
Power Supply Current
Power Supply Current
Power Supply Current
54F/74F
Min Typ Max
2.0
0.8
-1.2
2.5 2.4 2.5 2.4 2.7 2.7
0.5 0.5 0.5
20.0 5.0
100 7.0
250 50
4.75
3.75
-0.6
50
-50
-60
-150
500
33
50
40
60
40
60
Units
v v v
v
v
�A
�A
�A
v
�A mA �A �A mA �A mA mA mA
Vee
Min
Min
Min
Max Max Max 0.0 0.0 Max Max Max Max
o.ov
Max Max Max
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal l1N = -18 mA loH = -1 mA (INT) loH = -3 mA (On) loH = -1 mA (INT) loH = -3 mA (On) loH = -1 mA (INT) loH = -3 mA (On) IoL = 20 mA loL = 20 mA loL = 24 mA V1N = 2.7V
V1N = 7.0V
Vour =Vee
110 = 1.9 �A All Other Pins Grounded V100 = 150 mV All Other Pins Grounded V1N = 0.5V VouT = 2.7V VouT = 0.5V
Vour = ov
VouT = 5.25V Vo= HIGH Vo= LOW Vo= HIGHZ
4-360
AC Electrical Characteristics: See Section 2 for waveforms and Load Configurations
Symbol
Parameter
tPLH tPHL tPLH tPHL tPLH tPHL tPHL
tPHL
tpzH tpzL tpHz tpLz tpzH tpzL tpHz tpLz tpzH tpzL tpHz tpLz
Propagation Delay Dn to On
Propagation Delay
S1, S2 or STB to On
Propagation Delay
S1 or S2 to INT
Propagation Delay CLR to On
Propagation Delay STBtolNT
Access Time, HIGH or LOW
S1 to On
Disable Time, HIGH or LOW
S1 to On
Access Time, HIGH or LOW S2 to On
Disable Time, HIGH or LOW S2 to On
Access Time, HIGH or LOW Mto On
Disable Time, HIGH or LOW Mto On
74F
TA= +25�C Vee= +5.0V
CL= 50 pF
Min
Typ
Max
3.5
6.5
8.5
2.5
5.0
6.5
8.5
14.5
18.5
7.5
12.5
16.0
4.5
7.5
9.5
4.5
8.0
10.5
7.5
12.5
16.0
6.5
11.0
14.0
8.0
12.5
18.0
6.5
11.0
14.0
4.5
8.0
10.5
6.5
11.0
14.0
7.5
12.5
16.0
5.0
9.0
11.5
4.5
7.5
9.5
5.5
9.5
12.0
5.0
8.5
11.0
5.0
8.5
11.0
4.0
7.0
9.0
5.0
8.5
11.0
54F
TA, Vee= Mil CL= 50 pF
Min
Max
3.0
11.5
2.0
8.5
6.5
23.0
6.0
19.0
3.5
12.0
3.5
12.5
5.5
18.5
74F
TA, Vee= Com CL= 50 pF
Min
Max
3.0
9.5
2.0
7.5
7.5
20.5
6.5
17.5
4.0
10.5
4.0
11.5
6.5
17.5
5.5
17.5
5.5
15.0
6.5
20.0
7.0
19.0
5.5
18.0
5.5
15.0
4.0
14.5
4.0
11.5
5.5
17.0
5.5
15.0
6.5
18.5
6.5
17.5
4.0
15.5
4.5
12.5
3.5
12.5
4.0
10.5
4.5
14.5
4.5
13.0
4.5
16.0
4.5
12.0
4.0
15.0
4.5
12.0
3.5
11.5
3.5
10.0
4.5
14.0
4.5
12.0
Fig. Units
No. ns 2-3 ns 2-3 ns 2-3 ns 2-3 ns 2-3 ns 2-5
ns 2-5
ns 2-5
AC Operating Requirements: SeeSection2forWaveforms
Symbol
Parameter
t5 (H) t5 (L) th(H) th(L)
tw(H) tw(L)
tw(L)
Setup Time, HIGH or LOW
Dn to S1, S2 or STB
Hold Time
Dn to S1, S2 or STB S1, S2 or STB
Pulse Width, HIGH or LOW
CLR Pulse Width, LOW
74F
TA= +25�C Vee= +5.0V
Min
Max
0 0
8.0 8.0
8.0 8.0
8.0
54F
TA, Vee= Mil
Min
Max
2.0 2.0
10.0 10.0
11.0 11.0
11.5
74F
TA, Vee= Com
Min
Max
1.0 1.0
9.0 9.0
9.0 9.0
9.0
Fig. Units
No.
ns
2-6
ns
2-4
ns
2-4
4-361
U~NaStemiicoonnduactlor
54F/74F413
64 x 4 First-In First-Out Buffer Memory with Parallel 1/0
General Description
The 'F413 is an expandable fall-through type high-speed First-In First-Out (FIFO) buffer memory organized as 64 words by four bits. The 4-bit input and output registers record and transmit, respectively, asynchronous data in parallel form. Control pins on the input and output allow for handshaking and expansion. The 4-bit wide, 62-bit deep fallthrough stack has self-contained control logic.
Features
� Separate input and output clocks � Parallel input and output � Expandable without external logic � 15 MHz data rate � Supply current 160 mA max � Available in SOIC, (300 mil only)
Ordering Code: See Section 5 Logic Symbol
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
Do D1 D2 D3
SI
IR
so
OR
MR Oo 01 02 03
TL/F /9541-1
NC IR 2 SI 3 Do 4 D1 5 D2 D3 GND
16 Yee
15 So 14 OR 13 Oo 12 01 11 02 10 03
MR
TL/F/9541-2
Unit Loading/Fan Out: See Section 2 for u.L. Definitions
Pin Names
Do-D3 Oo-Os IR SI
so
OR MR
Description
Data Inputs Data Outputs Input Ready Shift In Shift Out Output Ready Master Reset
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loHlloL
1.0/0.667 50/13.3 1.0/0.667 1.0/0.667 1.0/0.667 1.0/0.667 1.0/0.667
20 �A/-0.4 mA -1 mA/8 mA
20 �A/-0.4 mA 20 �A/ - 0.4 mA 20 �A/-0.4 mA 20 �A/-0.4 mA 20 �A/-0.4 mA
Pin Assignment for LCC
D2 D1 NC Do SI
rn rn [�:] rn rn
D3 rn
GND [QI NC [ill
MR!i1J
03 [j]
Q]IR [l]NC [I]NC ~Vee IJ]]SO
IJ}] [j] Ii] IJ] Ii]] 02 01 NC 00 OR
TL/F /9541-3
4-362
Functional Description
Data Input-Data is entered into the FIFO on Do-D3 inputs. To enter data the Input Ready (IA) should be HIGH, indicating that the first location is ready to accept data. Data then present at the four data inputs is entered into the first location when the Shift In (SI) is brought HIGH. An SI HIGH signal causes the IA to go LOW. Data remains at the first location until SI is brought LOW. When SI is brought LOW and the FIFO is not full, IA will go HIGH, indicating that more room is available. Simultaneously, data will propagate to the second location and continue shifting until it reaches the output stage or a full location. If the memory is full, IA will remain LOW.
Data Transfer-Once data is entered into the second cell, the transfer of any full cell to the adjacent (downstream) empty cell is automatic, activated by an on-chip control. Thus data will stack up at the end of the device while empty locations will "bubble" to the front. The tpr parameter defines the time required for the first data to travel from input to the output of a previously empty device.
Block Diagram
Data Output-Data is read from the Oo-03 outputs. When data is shifted to the output stage, Output Ready (OR) goes HIGH, indicating the presence of valid data. When the OR is HIGH, data may be shifted out by bringing the Shift Out (SO) HIGH. A HIGH signal at SO causes the OR to go LOW. Valid data is maintained while the SO is HIGH. When SO is brought LOW, the upstream data, provided that stage has valid data, is shifted to the output stage. When new valid data is shifted to the output stage, OR goes HIGH. If the FIFO is emptied, OR stays LOW, and Oo-03 remains as before, i.e., data does not change if FIFO is empty.
Input Ready and Output Ready may also be used as status signals indicating that the FIFO is completely full (Input Ready stays LOW for at least tpr) or completely empty (Output Ready stays LOW for at least tpr).
SI
~. {
~
......
--,.
......
P"
INPUT REGISTER
~
......
62x4 FALL THROUGH
STACK
+
~
~so
. _
OUTPUT
P"
REGISTER
: }o,.,
.~ ...
~
IR....-
INPUT CONTROL
......
STACK
CONTROL
..... OUTPUT
P"
CONTROL
~
y
i
--,. O-R
MR TL/F/9541-4
4-363
Absolute Maximum Ratings (Note 1)
If MilitaryI Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to+ 7.0V
Input Voltage (Note 2)
-0.5V to + 7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5VtoVee -0.5Vto +5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�C to+ 70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol V1H V1L Veo VoH
Vol l1H lsv1 lcEX V10 loo l1L los lceH
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 74F 10% Vee 74F5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F Breakdown Test 74F
Output HIGH
54F
Leakage Current 74F
Input Leakage 74F
Test
Output Leakage 74F
Circuit Current
Input LOW Current
Output Short-Circuit Current
Power Supply Current
54F/74F Min Typ Max 2.0
0.8 -1.5 2.4 2.4 2.7 0.5 0.5 20.0 5.0 100 7.0 250
50
4.75
3.75
-0.4
-20
-130
115
160
Units
v v v v
v
�A
�A
�A
v
�A mA mA mA
Vee
Conditions
Recognized as a HIGH Signal
Recognized as a LOW Signal
Min l1N = -18 mA
loH = -1 mA Min loH = -1 mA
loH = -1 mA
Min
loL = 8 mA
loL = 8 mA
Max V1N = 2.7V
Max V1N = 7.0V
Max VouT =Vee
0.0
110 = 1.9 �A
All Other Pins Grounded
0.0
V100 = 150 mV
All Other Pins Grounded
Max V1N = 0.5V
Max VouT = ov
Max Vo= HIGH
4-364
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
fmax fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH
tPLH
Shift In Rate
Shift Out Rate
Propagation Delay Shift In to IR
Propagation Delay Shift Out to OR
Propagation Delay Output Data Delay
Propagation Delay Master Reset to IR
Propagation Delay Master Reset to OR
74F
TA= +25�C Vee= +5.0V
CL= 50 pF
Min
Typ
Max
10
10
1.5
44.0
1.5
31.0
1.5
52.0
1.5
31.0
1.5
46.0
1.5
34.0
1.5
27.0
1.5
30.0
54F
TA, Vee= Mil CL= 50 pF
Min
Max
8.0
8.0
1.5
50.0
1.5
37.0
1.5
57.0
1.5
37.0
1.5
52.0
1.5
39.0
1.5
33.0
1.5
34.0
74F
TA, Vee= Com CL= 50 pF
Min
Max
10
10
1.5
48.0
1.5
35.0
1.5
55.0
1.5
35.0
1.5
50.0
1.5
37.0
1.5
31.0
1.5
32.0
AC Operating Requirements: See Section 2 for Waveforms
Symbol
Parameter
t5 (H) t 5 (L) th(H) th(L) tw(H) tw(L) tw(H) tw(L) tw(H)
tw(L)
tw(L)
tree tpr
Setup Time, HIGH or LOW DntoSI
Hold Time, HIGH or LOW Dn to SI
Shift In Pulse Width HIGH or LOW
Shift Out Pulse Width HIGH or LOW
Input Ready Pulse Width, HIGH
Output Ready Pulse Width, LOW
Master Reset Pulse Width, LOW
Recovery Time, MR to SI
Data Throughput Time
74F
TA= +25�C Vee= +5.0V
Min
Max
1.0 1.0
10.0 10.0
5.0 10.0
7.5 10.0
7.5
5.0
10.0
32.0 0.9
54F
TA, Vee= Mil
Min
Max
1.0 1.0
10.0 10.0
5.0 10.0
8.5 10.0
8.5
5.0
10.0
35.0 1.0
74F
TA, Vee= Com
Min
Max
1.0 1.0
10.0 10.0
5.0 10.0
7.5 10.0
7.5
5.0
10.0
35.0 1.0
Fig. Units
No.
MHz 2-1 MHz 2-1
ns
2-3
ns
2-3
ns
2-3
ns
2-3
ns
2-3
Fig. Units
No.
ns
2-6
ns
2-4
ns
2-4
ns
2-4
ns
2-4
ns
2-6
�s
4-365
~~SNemaitcoinoduncatolr
54F/74F420
Parallel Check Bit/Syndrome Bit Generator
General Description
The 'F420 is a parallel check bit/syndrome bit generator. The 'F420 utilizes a modified hamming code to generate 7 check bits from a 32-bit dataword, in 15 ns, when operated in the check bit generate mode. When operated in the syndrome generate mode, the check bits and data bits
read from memory are utilized in a parity summer to generate syndrome bits upon error detection. The maximum error count detectable is 2. A single error detect can occur in 18 ns; a double error detect in 22 ns. The syndrome bit generation can be output in 15 ns (maximum).
Ordering Code: see section 5 Logic Diagram
Connection Diagrams
32
Do- D31
So
SEF
S1
DEF
CB Co C1 C2 C3 C4 Cs C5
TL/F/9542-1
Pin Assignment for LCC and PCC
Da 0., D5 Ds D,GNDNCVccD3 Dz D1 Do C5
gQ]li][j]ll1Jli]MJ/j]J~[i][i]IJ]J[!][[]
Dg 11Jl
D1o~ D11~ D12~
D13�1 Du~ NC Ill! D15~ D16~ D17 liQ]
D1aml 019~ Dzo~
rmnce5,
[i)C3 mc2
rmncc01
[!]NC
~So ~s1 ~SEF
~DEF
HID CB [!]NC
~~liID!mliID~~Hil~HJl[!j)H�]B!J Dz1DzzOz31J.i,OzsGNONCIJ.i&Oz7DzsDzg~~1
TL/F/9542-2
Pin Assignment for DIP and Flatpak
Co 1 C1 2 Cz 3 C3
c,
C5 C5 7 Do 8 D1 9 Dz 10 D3 11 Vee 12 GND 13 D, 1-4 Ds 15 05 16 0., 17 Dg 18 Dg 19 D10 20
D11 21 D1z 22 D13 23
D1, 24
48 So 47 S1 46 SEF 45 DEF 4-4 CB 43 NC 42 D31 41 D3o 40 Dzg 39 Dzg 38 Dz7 37 Dz5 36 GND 35 Dz5 34 Dz, 33 Dz3 32 0zz 31 Dz1
29 D19 28 D18 27 017 26 015 25 D1s
Unit Loading/Fan Out: See Section 2 for U.L. definitions
TL/F/9542-3
Pin Names
Description
Co-C6
Do-D31 CB DEF SEF So,S1
Check Bit/Syndrome Bus Inputs/ Outputs
Data Bit Bus Check Bit Control Double Error Flag Single Error Flag Mode Control
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loHlloL
3.5/1.083 150/40 (33.3)
1.0/1.0 1.0/1.0 50/33.3 50/33.3 1.0/1.0
70 �A/ - 0.65 mA -3 mA/24 mA (20 mA)
20 �A/-0.6 mA 20 �A/ - 0.6 mA -1 mA/20mA -1 mA/20mA 20 �A/-0.6 mA
4-366
Memory Cycle
Write Read Read Read Diagnostics
Diagnostics
Diagnostics
Function
Generate Check Bits Read & Flag Latch Check Bits Output Syndrome Bits Input Diagnostic Data Word Input Diagnostic Data Word Input Diagnostic Data Word
Block Diagram
Function Table
Control
51
So
Check Bit
L
L
Output Check
H
L
Input
H
H
Inputs
H
H
Output Syndrome Bits
H
H
Latched Check
Outputs High-Z
L
H
Output Latched
Check Bits
H
H
Output Syndrome
Bits
CB Control 1/0 L H H L H
L
L
Error Flags
SEF
DEF
H
H
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
PARITY TREE
.-----IQ
7 D ..-----_.,..~Co-Cs
INPUT LATCH
LE
COMPARE
OUTPUT BUFFER
OE
So
CONTROL
s,
CB
ERROR DETECT
----sEF
----DEF
TL/F/9542-4
4-367
0 N
"11:1" Absolute Maximum Ratings (Note 1)
If MilitaryI Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
-65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to + 7.0V
Input Voltage (Note 2)
-0.5V to + 7.0V
Input Current (Note 2)
-30 mA to+ 5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5VtoVee
- 0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life irnpaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�cto +70�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
V1H V1L Veo VoH
VoL
l1H lsv1 lcEx V10 loo lsv1T l1L l1H + lozH l1L + lozL los lzz lccH lecL lecz
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee 74F5% Vee 74F5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F Breakdown Test 74F
Output HIGH
54F
Leakage Current 74F
Input Leakage Test
74F
Output Leakage Circuit Current
74F
Input HIGH Current Breakdown Test (1/0)
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Bus Drainage Test
Power Supply Current
Power Supply Current
Power Supply Current
54F/74F
Min Typ Max
2.0
0.8
-1.2
2.5 2.4 2.5 2.4 2.7 2.7
0.5 0.5 0.5
20.0 5.0
100 7.0
250 50
4.75
3.75
1.0
-0.6
70
-650
-60
-150
500
130
130
130
Units
v v v
v
v
�A
�A
�A
v
�A
mA mA �A �A mA �A mA mA mA
Vee
Min
Min
Min
Max Max Max 0.0 0.0 Max Max Max Max Max
o.ov
Max Max Max
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal l1N = -18 mA, Dn, CB, So, S1 loH = -1 mA (All Outputs) loH = -3 mA (Co-C5) loH = -1 mA (All Outputs) loH = -3 mA (Co-C5) loH = -1 mA (All Outputs) loH = -3 mA (Co-C5) loL = 20 mA (All Outputs) loL = 20 mA (DEF, SEF) loL = 24 mA (Co-C5) V1N = 2.7V
V1N = 7.0V
VouT =Vee
110 = 1.9 �A All Other Pins Grounded V100 = 1.50 mV All Other Pins Grounded V1N = 5.5V (Co-C5)
V1N = 0.5V (On, CB, So, S1) VouT = 2.7V (Co-C5) VouT = 0.5V (Co-Ca)
VouT = ov
VouT = 5.25V Vo= HIGH Vo= LOW Vo= HIGHZ
4-368
AC Electrical Characteristics
Symbol
Parameter
tPLH tPHL
tPLH tPHL
tPLH tPHL
tPLH tPHL
tPLH tpHL
tpzH tpzL
tpHz tpLz
Propagation Delay Dn to Cn Propagation Delay Dn/Cn to SEF Propagation Delay Dn/Cn to DEF Propagation Delay S1 to Cn Propagation Delay S1 to SEF/DEF Output Enable Time
Output Disable Time
74F
TA= +25�C Vee= +5.0V
CL= 50 pF
Min
Typ
Max
5.0
20.0
5.0
17.0
5.0
20.0
4.0
16.0
6.0
24.0
5.0
21.0
4.0
18.0
3.0
13.0
4.0
14.0
3.0
9.0
2.0
12.0
2.0
11.0
1.0
7.5
1.0
7.5
54F
.TA, Vee= Mil CL= 50 pF
Min
Max
74F
TA, Vee= Com Units
Fig.
CL= 50 pF
No.
Min
Max
5.0
22.0
ns 420-a, b
5.0
19.0
5.0
22.0
ns
420-b
4.0
18.0
6.0
26.0
ns
420-b
5.0
22.0
4.0
19.0
ns 420-a, b
3.0
14.0
4.0
15.0
ns
420-b
3.0
10.0
2.0
13.0
2.0
12.0
ns
1.0
8.0
1.0
8.0
AC Operating Requirements: See section 2 for Waveforms
Symbol
Parameter
t5 (H) t5 (L)
th(H) th(L)
tw(L)
Setup Time, HIGH or LOW Cn to So
Hold Time, HIGH or LOW Cn to So Clock Pulse Width LOW
74F
TA= +25�C Vee= +5.0V
Min
Max
5.0 5.0
5.0 5.0
8.0
54F
TA, Vee= Mil
Min
Max
74F
TA, Vee= Com
Min
Max
5.0 5.0
5.0 5.0
8.0
Units
Fig. No.
ns
2-6
ns
2-6
ns
2-4
4-369
Timing Waveforms
So ----
SEF = H DEF= H
Do- D31 ---------<
~CHECKBIT~
---------------------------------- Co-Cs
-----------�GE-N-ER-A--.TE~
.----------------------------VALID CHECKWORD
--------------~
TL/F/9542-5
FIGURE 420-a.
CHECKING
J
LATCH CHECKBITS
OUTPUT SYNDROME BITS
.l
'
./i
~
1---Select to Syndrome Bit Output
~
~
SEF
Single~
Error 1
Detect
DEF
Multiple.l_
Error I
Detect
FIGURE 420-b.
TL/F/9542-6
4-370
U~NaStemiicoonnduactlor
54F/74F432
Multi-Mode Buffered Latch with TRI-STATE� Outputs
General Description
The 'F432 is an 8-bit latch with TRI-STATE output buffers and control and device selection logic. Also included is a status flip-flop for providing device-busy or request-interrupt commands. Separate Mode and Select inputs allow data to be stored with the outputs enabled or disabled. The device can also operate in a fully transparent mode.
The 'F432 is the functional equivalent of the Intel 8212, but with inverting outputs.
Features
� TRI-STATE inverting outputs � Status flip-flop for interrupt commands � Asynchronous or latched receiver modes � Data to output propagation delay typically 8.5 ns � Supply current 43 mA typ � 24-pin slim package
Ordering Code: see sections Logic Symbols
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
Pin Assignment for LCC
INT
TL/F/9543-1
I E E E / I EC
51 1 t.l
Do 60 D1 01 6 D2 7 62 D3 03 10 STB 11 GND 12
24 Yee
23 iNT
22 D7 21 07 20 D5 19 05 18 D5 17 65 16 D4 15 04 14 eLR 13 S2
TL/F/9543-2
D3 62 D2 NC 61 D1 Oo [j][QJ[[][[][I)[�J@]
03 [j] STB ff]
GND~
NC [fil
S2 [i]] CLR [j]
04 [j]J
moo
[Ilt.l
rn 51
[I] NC
~Yee
Ill] iNT
Im D7
[j]]@l~llll~i?.11~
D4 05 D5 NC Os Ds 07
TL/F/9543-3
Do
60
D1
61
D2
62
D3
03
D4
64
D5
05
D5
05
07
67
TL/F/9543-4
4-371
a
Unit Loading/Fan Out: see section 2 for u.L. definitions
Pin Names
Do-D7 Oo-07 S1.-S2. M STB INT CLR
Description
Data Inputs Latch Outputs Select Inputs Mode Control Input Strobe Interrupt Clear
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loHlloL
1.0/1.0 150/40 (33.3)
1.0/1.0 1.0/1.0 1.0/1.0 50/33.3 1.0/1.0
20 �A/ - 0.6 mA -3 mA/24 mA (20 mA)
20 �A/-0.6 mA 20 �A/-0.6 mA 20 �A/-0.6 mA -1 mA/20 mA 20 �A/-0.6 mA
Functional Description
This high-performance eight-bit parallel expandable buffer register incorporates package and mode selection inputs and an edge-triggered status flip-flop designed specifically for implementing bus-organized input/output ports. The TRI-STATE data outputs can be connected to a common data bus and controlled from the appropriate select inputs to receive or transmit data. An integral status flip-flop provides busy or request interrupt commands.
The eight data latches are fully transparent when the internal gate enable, G, input is HIGH and the outputs are enabled. Latch transparency is selected by the mode control (M), select (S1 and S2). and the strobe (STB) inputs and during transparency each data output (On) follows its respective data input (Dn). This mode of operation can be
terminated by clearing, de-selecting, or holding the data latches. See Data Latches Function Table.
An input mode or an output mode is selectable from this single input line. In the input mode, M = L, the eight data latch inputs are enabled when the strobe is HIGH regardless of device selection. If selected during an input mode, the outputs will follow the data inputs. When the strobe input is taken LOW the latches will store the most recently setup data.
In the output mode, M = H, the output buffers are enabled
regardless of any other control input. During the output mode the content of the register is under control of the select (S1 and S2) inputs. See Data Latches Function Table.
Function
CLR
Clear
L
L
De-select
x
x
Hold
H
H
Data Bus
H
H
Data Bus
H
H
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance
Data Latches Function Table
M
51
S2
STB
H
H
x
x
L
L
H
L
L
x
L
x
L
H
x
x
H
H
L
x
L
L
H
L
H
L
H
x
H
L
H
x
L
L
H
H
L
L
H
H
Data In
x x x x x x
L H
L H
Data Out
H H
z z
Oo
Do
H L
H L
Status Flip-Flop Function Table
CLR
81
S2
STB
INT
L
H
x
x
H
L
x
L
x
H
H
x
x
_r
L
H
L
H
x
L
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial ../" = LOW-to-HIGH Transition
4-372
Logic Diagram
STB~~~~~~~~~~"-4~
. . . . ~~~~~~
~~~~"-4~
OE
Q
G CLR
D Q
G CLR
D Q
G CLR
D Q
G CLR
D Q
G CLR
G CLR
G CLR
o-~-G CLR
TL/F/9543-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-373
Absolute Maximum Ratings (Note 1)
If MilitaryI Aerospace specified devices are required, please contact the National Semiconductor �Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to+ 7.0V
Input Voltage (Note 2)
-0.5Vto +7.0V
Input Current (Note 2)
-30 mA to + 5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
-0.5Vto Vee -0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�c
o�cto +1o�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol V1H V1L Yeo VoH
Vm l1H lsv1 lcEX V10 loo lsv1r l1L lozH lozL los
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee 74F 5% Vee 74F5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage
74F
Test
Output Leakage
74F
Circuit Current
Input HIGH Current Breakdown Test (1/0)
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
54F/74F Min Typ Max
2.0 0.8 -1.2
2.5 2.4 2.5 2.4 2.7 2.7
0.5 0.5
20.0 5.0
100 7.0
250 50
4.75
3.75
-60
1.0
-0.6 50 -50
-150
Units v v v
v
v �A �A �A v �A mA mA �A �A mA
Vee
Min
Min
Min Max Max Max 0.0 0.0 Max Max Max Max Max
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal l1N = -18 mA loH = -1 mA loH = -3mA loH = -1 mA loH = -3mA loH = -1 mA loH = -3mA loL = 20 mA Im= 24mA
V1N = 2.7V
V1N = 7.0V
Your= Vee
110 = 1.9 �A All Other Pins Grounded V100 = 150 mV All Other Pins Grounded V1N = 5.5V
V1N = 0.5V Your= 2.7V Your= o.5V Your= ov
4-374
DC Electrical Characteristics (Continued)
Symbol
lzz iccH lccL lccz
Parameter
Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current
54F/74F
Min
Typ
Max
500
50
65
50
65
50
65
Units
�A mA mA mA
Vee
O.OV Max Max Max
Conditions
Vour = 5.25V Vo= HIGH Vo= LOW Vo= HIGHZ
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
tPLH tPHL tPLH tPHL tPHL
tPHL
tPLH tPHL tPLH tPHL tPLH tPHL tpzH tpzL tpHz tpLz tpzH tpzL tpHz tpLz
Propagation Delay DntOOn
Propagation Delay
S1, S2 or STB to On
Propagation Delay CLRtoOn
Propagation Delay STB to INT
Propagation Delay
S1 to INT
Propagation Delay S2 to INT
Propagation Delay MtoOn
Enable Time MtoOn
Disable Time MtoOn
Enable Time
S1. S2toOn
Disable Time
S1, S2toOn
74F
TA= +25�C Vee= +5.0V
CL= 50 pf
Min
Typ
Max
3.5
8.5
10.5
2.5
5.5
7.0
8.5
16.0
21.0
6.5
12.5
16.0
7.0
15.0
18.5
6.0
11.5
14.5
4.0
7.5
9.5
5.5
7.5
12.0
4.0
7.5
9.5
4.5
7.5
9.5
9.0
15.0
19.0
6.5
11.0
14.0
6.0
8.5
14.0
6.0
8.5
13.0
4.5
6.5
9.5
5.5
9.5
12.0
4.5
13.0
18.0
5.0
11.0
15.0
4.0
8.0
11.0
5.0
11.0
15.5
54F
TA, Vee= Mil CL= 50 pf
Min
Max
74F
TA, Vee= Com CL= 50 pf
Min
Max
3.0
12.0
3.0
12.0
7.5
23.0
5.5
18.0
6.0
20.5
5.0
16.0
3.5
10.5
5.5
13.0
3.5
10.5
4.5
10.5
9.0
20.0
6.5
15.0
6.0
15.0
6.0
14.5
4.5
10.5
5.5
13.0
4.0
20.0
4.0
17.0
3.5
12.5
4.0
17.5
Fig. Units No.
ns
2-3
ns
2-3
ns
2-3
ns
2-3
ns
2-3
ns
2-3
ns
2-3
ns
2-5
ns
2-5
ns
2-5
4-375
AC Operating Requirements: see section 2 for waveforms
Symbol
Parameter
t5 (H) t5 (L) th(H) th(L)
t5 (H) t5 (L)
th(H) th(L)
t5 (H) t5 (L) th(H) th(L)
tw(H) tw(L)
tw(L)
tw(H) tw(L)
tw(H) tw(L)
Setup Time, HIGH or LOW
S1 to On
Hold Time, HIGH or LOW
S1 to On
Setup Time, HIGH or LOW S2 to Dn
Hold Time, HIGH or LOW S2 to Dn
Setup Time, HIGH or LOW STBto Dn
Hold Time, HIGH or LOW STB to Dn
STB Pulse Width HIGH or LOW
CLR Pulse Width, LOW
S1 Pulse Width
HIGH or LOW
S2 Pulse Width HIGH or LOW
74F
TA= +2s0 c Vee= +s.ov
Min
Max
0 0
11.0 8.5
0 0
9.0 7.0
0 0
13.0 10.0
5.0 5.0
10.0
9.0 7.0
7.0 9.0
54F
TA, Vee= Mil
Min
Max
74F
TA, Vee= Com
Min
Max
0 0
12.5 9.5
0 0
9.0 7.0
0 0
13.0 10.0
5.0 5.0
10.0
9.0 7.0
7.0 9.0
Fig.
Units No.
ns
2-6
ns
2-6
ns
2-6
ns
2-6
ns
2-6
ns
2-4
ns
2-4
ns
2-4
ns
2-4
4-376
~National
U Semiconductor
54F/74F433 First-In First-Out {FIFO) Buffer Memory
General Description
The 'F433 is an expandable fall-through type high-speed first-in first-out (FIFO) buffer memory that is optimized for high-speed disk or tape controller and communication buffer applications. It is organized as 64 words by 4 bits and may be expanded to any number of words or any number of bits in multiples of four. Data may be entered or extracted asynchronously in serial or parallel, allowing economical implementation of buffer memories.
The 'F433 has TRI-STATE� outputs that provide added versatility, and is fully compatible with all TTL families.
Features
� Serial or parallel input � Serial or parallel output � Expandable without additional logic � TRI-STATE outputs � Fully compatible with all TTL families � Slim 24-pin package � 9423 replacement
Ordering Code: see section 5 Logic Symbol
PL TTS IES CPSI TOP TOS OES CPSO OE t,jR
03 02
o, Oo Os
IRF 0 ORE 0 -
TL/F/9544-1
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
iiiF 1
PL
Do D1 Dz 5 DJ Ds CPSI
iES ffS 10 MR 11
GND 12
24 Vee 23 ORE
22 Os 21 Oo
20 o,
19 02 18 03
17 6E
16 CPSO
15 OES
14 TOS
13 TOP
Pin Assignment for LCC
iES CPSI Ds NC D3 D2 D1
rn rn [j] [j]J [�] [�:] [[]
TL/F/9544-2
4-377
TTS ij]
MR II]
GND Ii]
NC@
TOP [ill TOS [Z] OES [j]]
[�]Do
[I] PL
[I] fRF OJ NC
@I Yee
~ORE
~Os
[j]] ~ !ITI [~@] ~ ~ CPSO OE 03 NC 02 01 Oo
TL/F/9544-3
II
Unit Loading/Fan Out: See Section 2 for U.L. definitions
Pin Names
PL CPSI IES TTS MR OES TOP TOS CPSO OE Do-D3 Ds Oo-03 Os IRF ORE
Description
Parallel Load Input Serial Input Clock Serial Input Enable Transfer to Stack Input Master Reset Serial Output Enable Transfer Out Parallel Transfer Out Serial Serial Output Clock Output Enable Parallel Data Inputs Serial Data Input Parallel Data Outputs Serial Data Output Input Register Full Output Register Empty
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loH/loL
1.0/0.66 1.0/0.66 1.0/0.66 1.0/0.66 1.0/0.66 1.0/0.66 1.0/0.66 1.0/0.66 1.0/0.66 1.0/0.66 1.0/0.66 1.0/0.66 285/10 285/10
20/5 20/5
20 �A/400 �A 20 �A/400 �A 20 �A/400 �A 20 �A/400 �A 20 �A/400 �A 20 �A/400 �A 20 �A/400 �A 20 �A/400 �A 20 �A/400 �A 20 �A/400 �A 20 �A/400 �A 20 �A/400 �A 5.7 mA/16 mA 5.7 �A/16 mA 400 �A/8 mA 400 �A/8 mA
Functional Description
As shown in the block diagram, the 'F433 consists of three sections:
1. An Input Register with parallel and serial data inputs, as well as control inputs and outputs for input handshaking and expansion.
2. A 4-bit-wide, 62-word-deep fall-through stack with selfcontained control logic.
3. An Output Register with parallel and serial data outputs, as well as control inputs and outputs for output handshaking and expansion.
These three sections operate asynchronously and are virtually independent of one another.
Input Register (Data Entry)
The Input Register can receive data in either bit-serial or 4-bit parallel form. It stores this data until it is sent to the fallthrough stack, and also generates the necessary status and control signals.
This 5-bit register (see Figure 1 ) is initialized by setting flipflop F3 and resetting the other flip-flops. The Q-output of the last flip-flop (FC) is brought out as the Input Register Full (IRF) signal. After initialization, this output is HIGH.
Parallel Entry-A HIGH on the Parallel Load (PL) input loads the D0 -D3 inputs into the F0 -F3 flip-flops and sets the FC flip-flop. This forces the IRF output LOW, indicating that the input register is full. During parallel entry, the Serial Input Clock (CPSI) input must be LOW.
Serial Entry-Data on the Serial Data (Ds) input is serially entered into the shift register (F3, F2, F1, F0, FC) on each HIGH-to-LOW transition of the CPSI input when the Serial Input Enable (IES) signal is LOW. During serial entry, the PL input should be LOW.
After the fourth clock transition, the four data bits are located in flip-flops F0 -F3. The FC flip-flop is set, forcing the IRF output LOW and internally inhibiting CPSI pulses from affecting the register. Figure 2 illustrates the final positions in an 'F433 resulting from a 256-bit serial bit train (Bo is the first bit, 8255 the last).
Block Diagram
Ds-----------.
PL CPSI
iEs
TTS
STACK CONTROL
62 X 4 STACK
OES TOP TOS
CPSO
TL/F /9544-4
4-378
Functional Description (Continued)
o, . - - - - - - - - - - INPUT DATA - - - - - - - - - - - . D2
Ds--+---1 IRF
iE
CPSI
S
-
--
'
-
"
"""'r
-
't--t-------f------1------~1--1
FIGURE 1. Conceptual Input Section
TL/F/9544-5
INPUT REGISTER
OUTPUT REGISTER
'F433
TL/F/9544-6
FIGURE 2. Final Positions in an 'F433 Resulting from a 256-Bit Serial Train
Fall-Through Stack-The outputs of flip-flops F0 -F3 feed the stack. A LOW level on the Transfer to Stack (TTS) input initiates a fall-through action; if the top location of the stack is empty, data is loaded into the stack and the input register is reinitialized. (Note that this initialization is delayed until PL is LOW). Thus, automatic FIFO action is achieved by connecting the IRF output to the TTS input.
An RS-type flip-flop (the initialization flip-flop) in the control section records the fact that data has been transferred to the stack. This prevents multiple entry of the same word into the stack even though IRF and TTS may still be LOW; the initialization flip-flop is not cleared until PL goes LOW.
Once in the stack, data falls through automatically, pausing only when it is necessary to wait for an empty next location. In the 'F433, the master reset (MR) input only initializes the stack control section and does not clear the data.
Output Register
The Output Register (see Figure 3) receives 4-bit data words from the bottom stack location, stores them, and outputs data on a TRI-STATE, 4-bit parallel data bus or on a TRI-STATE serial data bus. The output section generates and receives the necessary status and control signals.
Parallel Extraction-When the FIFO is empty after a LOW
pulse is applied to the MR input, the Output Register Empty
(ORE) output is LOW. After data has been entered into the
FIFO and has fallen through to the bottom stack location, it
is transferred into the output register, if the Transfer Out
Parallel (TOP) input is HIGH. ORE goes HIGH, indicating
As a valid
result data
of on
the the
ddaattaatroauntspfuetr~
(provided that the TRI-STATE buffer is enabled). The TOP
input can then be used to clock out the next word.
When TOP goes LOW, ORE also goes LOW, indicating that the output data has been extracted; however, the data itself remains on the output bus until a HIGH level on TOP permits the transfer of the next word (if available) into the output register. During parallel data extraction, the serial output clock (CPSO) line should be LOW. The Transfer Out Serial (TOS) line should be grounded for single-slice operation or connected to the appropriate ORE line for expanded operation (refer to the 'Expansion' section).
The TOP signal is not edge-triggered. Therefore, if TOP goes HIGH before data is available from the stack but data becomes available before TOP again goes LOW, that data is transferred into the output register. However, internal
4-379
Functional Description (Continued)
control circuitry prevents the same data from being transferred twice. If TOP goes HIGH and returns to LOW before data is available from the stack, ORE remains LOW, indicating that there is no valid data at the outputs.
Serial Extraction-When the FIFO is empty after a LOW is applied to the MR input, the ORE output is LOW. After data has been entered into the FIFO and has fallen through to the bottom stack location, it is transferred into the output register, if the TOS input is LOW and TOP is HIGH. As a result of the data transfer, ORE goes HIGH, indicating that valid data is in the register.
The TRI-STATE Serial Data Output (Os) is automatically enabled and puts the first data bit on the output bus. Data is serially shifted out on the HIGH-to-LOW transition of CPSO. To prevent false shifting, CPSO should be LOW when the
new word is being loaded into the output register. The fourth
transition empties the shift register, forces ORE LOW, and
disables the serial output, Os. For serial operation, the ORE
output may be tied to the TOS input, requesting a new word
from the stack as soon as the previous one has been shift-
ed out.
�
Expansion
Vertical Expansion-The 'F433 may be vertically expanded, without external components, to store more words. The interconnections necessary to form a 190-word by 4-bit FIFO are shown in Figure 4. Using the same technique, any FIFO of (63n+ 1)-words by 4-bits can be configured, where n is the number of devices. Note that expansion does not sacrifice any of the 'F433 flexibility for serial/parallel input and output.
. . - - - - - - - - - - OUTPUT rROM S T A C K - - - - - - - - - - - .
Mii--- 1 or.......... 0---+----+--------+---------+------------'
TOP---OL_,,,,
01
Oo
.____ _ _ _ _ _ _ _ _ OUTPUT D A T A - - - - - - - - - - - '
FIGURE 3. Conceptual Output Section
TL/F/9544-7
4-380
Functional Description (Continued)
MASTER RESET
PARALLEL DATA IN
PARALLEL I
1
LOAD D3 D2 D1 Do
SERIAL DATA IN SERIAL INPUT CLOCK
~,._!_. hr
Le PL Ds D3 D2 D, Do
"'� TIS
-5 IES CPSI
IRF P..J
"'- OES
r-0 TOS .....- TOP
'F433
-0 CPSO
ORE P-
-0 OE
MR o302 0100 05
_9
T
NC
......
l
1
Lo TIS PL Ds D3 D2 Dt Do
~ IES
; g~~I
r-0 TOS .....- TOP
~ CPSO
~OE
MR
J
IRF P.J
'F433
ORE P-
o302 0100 05 T
NC
~
l
11
l-q TIS PL Ds D3 D2 Dt Do
~ IES
IRF P.J
~ CPSI
DUMP SERIAL OUTPUT CLOCK OUTPUT ENABLE
-.. OES
r<> TOS
'F433
TOP
DATA VALID
-0 CPSO
ORE P.....-+
.q OE
.,-gMR o3o2o1o0o5 1
s....~,. RIAL DA TA
-==
~ ~~�
OU TPUT
PARALLEL DATA OUT
FIGURE 4. A Vertical Expansion Scheme
TL/F/9544-8
4-381
Functional Description (Continued)
Horizontal Expansion-The 'F433 can be horizontally expanded, without external logic, to store long words (in multiples of 4-bits). The interconnections necessary to form a 64word by 12-bit FIFO are shown in Figure 5. Using the same technique, any FIFO of 64-words by 4n-bits can be constructed, where n is the number of devices.
The right-most (most significant) device is connected to the TTS inputs of all devices. Similarly, the ORE output of the most significant device is connected to the TOS inputs of all devices. As in the vertical expansion scheme, horizontal expansion does not sacrifice any of the 'F433 flexibility for serial/parallel input and output.
It should be noted that the horizontal expansion scheme shown in Figure 5 exacts a penalty in speed.
Horizontal and Vertical Expansion-The 'F433 can be expanded in both the horizontal and vertical directions without any external components and without sacrificing any of its FIFO flexibility for serial/parallel input and output. The interconnections necessary to form a 127-word by 16-bit FIFO are shown in Figure 6. Using the same technique, any FIFO
of (63m + 1)-words by 4n-bits can be configured, where m is
the number of devices in a column and n is the number of devices in a row. Figures 7 and 8 illustrate the timing diagrams for serial data entry and extraction for the FIFO shown in Figure 6. Figure 9 illustrates the final positions of bits in an expanded 'F433 FIFO resulting from a 2032-bit serial bit train.
Interlocking Circuitry-Most conventional FIFO designs provide status signal analogous to IRF and ORE. However, when these devices are operated in arrays, variations in unit-to-unit operating speed require external gating to ensure that all devices have completed an operation. The 'F433 incorporates simple but effective 'master/slave' interlocking circuitry to eliminate the need for external gating.
In the 'F433 array of Figure 6, devices 1 and 5 are the row masters; the other devices are slaves to the master in their rows. No slave in a given row initializes its input register until it has received a LOW on its IES input from a row master or a slave of higher priority.
Similarly, the ORE outputs of slaves do not go HIGH until their inputs have gone HIGH. This interlocking scheme ensures that new input data may be accepted by the array when the IRF output of the final slave in that row goes HIGH and that output data for the array may be extracted when the ORE output of the final slave in the output row goes HIGH.
The row master is established by connecting its IES input to ground, while a slave receives its IES input from the IRF output of the next-higher priority device. When an array of 'F433 FIFOs is initialized with a HIGH on the MR inputs of all devices, the IRF outputs of all devices are HIGH. Thus, only the row master receives a LOW on the IES input during initialization.
Figure 10 is a conceptual logic diagram of the internal circuitry that determines master/slave operation. When MR and IES are LOW, the master latch is set. When TTS goes LOW, the initialization flip-flop is set. If the master latch is HIGH, the input register is immediately initialized and the initialization flip-flop reset. If the master latch is reset, the input register is not initialized until IES goes LOW. In array operation, activating TTS initiates a ripple input register initialization from the row master to the last slave.
A similar operation takes place for the output register. Either a TOS or TOP input initiates a load-from-stack operation and sets the ORE request flip-flop. If the master latch is set, the last output register flip-flop is set and the ORE line goes HIGH. If the master latch is reset, the ORE output is LOW until a Serial Output Enable (OES) input is received.
- - - - - - - - PARALLEL DATA INPUT - - - - - - - - - - .
1111 CP~SI~-----+---1..L....i,-~--h-~------I1..-...--,--,-.-----+--1---1
DUMP--++-t~-+---+-+-+--+-+-+--t--H~l---+-+-t-t-+-+-+--+-' CPSO---i-+--1------+-+----+-+-+--+--+---i---+-+-1-o1--t--+--+-..._.
O"E--+-+-+-----i--+--+---+-i---+--+-__i--__.._......_..._ _ _._+-__,
SR--++-+----.-1--t-+-+---+--+---+-._,1-t-+--t--+--___,
......._
~i H
~ H
I 03 02 01 Oo
07 Os 05 04
'-�- - - - - - - - PARALLEL DATA OUTPUT--------_.
FIGURE 5. A Horizontal Expansion Scheme
4-382
TL/F/9544-9
Functional Description (Continued)
SERIAL DATA INPUT PARALLEL LOAD INPUT CLOCK
. - - - - - - - - - - - - PARALLEL DATA INPUT - - - - - - - - - - - - . C7DsD5D4
I
1
1 jjjj
I
I
1
1
l
l
I
1
J_
OUTPUT ENABLE OUTPUT CLOCK DUMP
SERIAL DATA OUTPUT
.,
,._0_3_02_0_10_0_ _ _ _ _ _01_0_6o_s04PARALLEL DATA OUTPUT0-11_0_10_0_9o_s_ _ _ _ _ _ _ __..
FIGURE 6. A 127 x 16 FIFO Array
TL/F/9544-10
CPSI
DEVICE 1
iRf
DEVICE 2
iRf
DEVICE J
iRf
DEVICE 4@ ALL DEVICES
iRf
I I I I INPUTS 0 BITS
12 3
4
''
--.: t+-to
LJJ
I I I I I 1 I I I I a 5 6 7
9 10 11 12 13 1� 15 1
STORED IN DEVICE 1
STORED IN DEVICE 2
STORED IN DEVICE 3
STORED IN DEVICE 4
FIGURE 7. Serial Data Entry for Array of Figure 6
TL/F/9544-11
4-383
('I)
~ Functional Description (Continued)
DEVICE 5 DEVICE 6 DEVICE 7
DEVICE 8, TOs ALL DEVICES
SERIAL DATA OUTPUT
I I
to_..: ;.--
'I '
I
I'
_______________t_,o:,I.~.I_':ri----
_______...:1:_--._::I rI:~-t-0-
I
-
.
'
:
':...-to
L_j-
DEVICE 5
DEVICE 6
DEVICE 7
DEVICE 8
FIGURE 8. Serial Data Extraction for Array of Figure 6
TL/F /9544-12
�r433
�r433
H33
H33
'r433
-----------
83 Bz 81 Bo Os
03 Oz 01 Oo
H33
-----------
87 85 85 84
03 Oz o, Oo Os
H33
-----------
811 810 Bg Bs Os
03 Oz 01 Oo
H33
-----------
B1s 814 813 812
SERIAL
OUTPUT
03 Oz 01 Oo Os
FIGURE 9. Final Position of a 2032-Bit Serial Input
TL/F/9544-13
LATCH
Mii----01
re
(SEE rlGURE 1)
~--------------+--� INmAUZE
(SEE rlGURE 1)
INPUT REG-STACK - - - - - 1 S
(DERIVED rROM TIS)
REQUEST
INTIALIZATION
rLIP-rLOP
R
ruP-rLOP R
LOAD OUTPUT (DERIVED rROM TOP AND TOS)
REGISTER Troosp--------------------+-.-. ' o~-----------+----------
rx
(SEE rlGURE 2)
FIGURE 10. Conceptual Diagram, Interlocking Circuitry 4-384
TL/F/9544-14
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
-55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to + 7.0V
Input Voltage (Note 2)
-0.5V to + 7.0V
Input Current (Note 2)
-30 mA to + 5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
-0.5VtoVcc -0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
54F/74F Min Typ Max
Units Vee
Conditions
V1H
Input HIGH Voltage
2.0
v
Recognized as a HIGH Signal
V1L
Input LOW Voltage
0.8
v
Recognized as a LOW Signal
Vco
Input Clamp Diode Voltage
-1.5
v
Min l1N = -18mA
VoH
Output HIGH
Voltage
54F 10% Vee 2.4
54F 10% Vee 2.4
74F 10% Vee 2.4
74F 10% Vee 2.4
74F5% Vee
2.7
74F 5% Vee
2.7
loH = 400 �A (ORE, IRF)
loH = 5.7 mA (On, Os)
loH = 400 �A (ORE, IRF)
v
Min
loH = 5.7 mA (On, Os)
loH = 400 �A (ORE, IRF)
loH = 5.7 mA (On, Os)
VoL
Output LOW
Voltage
54F 10% Vee 74F 10% Vee
0.50
loL = 8 mA (ORE, IRF)
0.50
v
Min loL = 16 mA (On, Os)
l1H
Input HIGH
54F
Current
74F
20.0
�A
Max V1N = 2.7V
5.0
lsv1
Input HIGH Current 54F
Breakdown Test
74F
100
�A
Max V1N = 7.0V
7.0
lcEx
Output HIGH
54F
Leakage Current
74F
250 50
�A
Max VouT =Vee
V10
Input Leakage
74F
4.75
Test
v
0.0
110 = 1.9�,A
All Other Pins Grounded
loo
Output Leakage
74F
Circuit Current
3.75
�A
0.0 V100 = 150 mV All Other Pins Grounded
l1L
Input LOW Current
-0.4
mA Max V1N = 0.5V
lozH
Output Leakage Current
50
�A
Max VouT = 2.7V (On, Os)
lozL
Output Leakage Current
los
Output Short-Circuit Current
-20
-50
�A
Max VouT = 0.5V (On. Os)
-130 mA Max VouT =av
Ice
Power Supply Current
150 215
mA Max
4-385
AC Electrical Characteristics
Symbol
Parameter
tPHL
tPLH
tPLH tPHL tPLH tPHL tPHL
tPHL
tPLH
tPLH
tPHL
tPLH
tPLH
tPLH
tPHL
tPLH
tpzH tpzL tpHz tpLz tpzH tpzL tpHz tpLz tpzH tpzL to FT tAP
tAs
Propagation Delay, Negative-Going CPSI to IRF Output
Propagation Delay, Negative-Going TTS to IRF
Propagation Delay, NegativeGoing CPSO to Os Output
Propagation Delay, PositiveGoing TOP to Oo-03 Outputs Propagation Delay, Negative-Going CPSO to ORE
Propagation Delay, Negative-Going TOP to ORE
Propagation Delay, Positive-Going TOP to ORE
Propagation Delay, Negative-Going TOS to Positive-Going ORE
Propagation Delay, PositiveGoing PL to Negative-Going IRF
Propagation Delay, NegativeGoing PL to Positive-Going IRF
Propagation Delay, Positive-Going OES to ORE
Propagation Delay Positive-IRF Going IES to Positive-Going
Propagation Delay MR to ORE
Propagation Delay MR to IRF
Enable Time OEtoOo-03
Disable Time OEtoOo-03
Enable Time Negative-Going OES to Os
Disable Time Negative-Going OES to Os
Enable Time TOStoOs
Fall-Through Time
Parallel Appearance Time OREtoOo-03
Serial Appearance Time ORE to Os
74F
TA= +25�C Vee= +5.0V
CL= 50 pf
Min
Max
2.0
17.0
9.0
34.0
4.0
25.0
5.0
20.0
8.0
35.0
7.0
30.0
7.0
25.0
6.0
26.0
13.0
48.0
13.0
45.0
4.0
22.0
7.0
31.0
9.0
38.0
5.0
25.0
7.0
28.0
5.0
27.0
1.0
16.0
1.0
14.0
1.0
10.0
1.0
23.0
1.0
10.0
1.0
14.0
1.0
10.0
1.0
14.0
1.0
35.0
1.0
35.0
0.2
0.9
-20.0 -2.0
-20.0 5.0
54F
TA, Vee= Mil CL= 50 pf
Min
Max
74F
TA, Vee= Com CL= 50 pf
Min
Max
2.0
18.0
8.0
38.0
3.0
27.0
5.0
21.0
7.0
38.0
7.0
32.0
6.0
28.0
6.0
28.0
12.0
51.0
12.0
50.0
4.0
23.0
6.0
35.0
8.0
44.0
5.0
27.0
7.0
31.0
5.0
1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 0.2
-20.0
30.0
18.0 16.0 12.0 30.0 12.0 15.0 12.0 16.0 42.0 39.0 1.0
-2.0
-20.0
5.0
Fig. Units No.
ns 433-a,b
ns 433-c,d ns 433-e ns 433-c,d ns 433-e
ns 433-c,d ns 433-g,h
ns ns 433-h ns ns ns
ns
ns
ns
433-f
ns
4-386
AC Operating Requirements
Symbol
Parameter
t5 (H) t5 (L) th(H) th(L) t 5 (L)
t5 (L)
t5 (L)
t 5 (L)
t5 (H) t5 (L) th(H) th(L) tw(H) tw(L) tw(H) tw(L)
tw(L) tw(H) tw(L) tw(H) tw(L) tree
Setup Time, HIGH or LOW Ds to Negative CPSI
Hold Time, HIGH or LOW Ds toCPSI
Setup Time, LOW TTS to IRF, Serial or Parallel Mode
Setup Time, LOW Negative-Going ORE to Negative-Going TOS
Setup Time, LOW NegativeGoing IES to CPSI
Setup Time, LOW NegativeGoing TTS to CPSI
Setup Time, HIGH or LOW Parallel Inputs to PL
Hold Time, HIGH or LOW Parallel Inputs to PL
CPSI Pulse Width HIGH or LOW
PL Pulse Width, HIGH
TTS Pulse Width, LOW Serial or Parallel Mode
MR Pulse Width, LOW
TOP Pulse Width HIGH or LOW
CPSO Pulse Width HIGH or LOW
Recovery Time MR to Any Input
74F
TA= +2s0 c Vee= +s.ov
Min
Max
7.0 7.0
2.0 2.0
0.0
0.0
8.0
30.0
0.0 0.0 4.0 4.0 10.0 5.0 7.0
7.0
7.0 14.0 7.0 14.0 7.0
8.0
54F
TA, Vee= Mil
Min
Max
74F
TA, Vee= Com Units
Min
Max
7.0 7.0
ns 2.0 2.0
Fig. No.
433-a,b
0.0
ns 433-a,b,g,h
0.0
ns
433-c,d
9.0
33.0
0.0 0.0 4.0 4.0 11.0 6.0 9.0
9.0
9.0 16.0 7.0 16.0 7.0
15.0
ns 433-b
ns
ns
ns
433-a,b
ns
433-g,h
ns 433-a,b,c,d
ns
433-f
ns
433-e
ns
433-c,d
ns
433-f
4-387
Timing Waveforms
Conditions: Stack not full, IES, PL LOW
FIGURE 433-a. Serial Input, Unexpanded or Master Operation
TL/F/9544-15
Conditions: Stack not full, IES HIGH when initiated, PL LOW
FIGURE 433-b. Serial Input, Expanded Slave Operation
TL/F/9544-16
1.5V
Conditions: Data in stack, TOP HIGH, IES LOW when initiated, OES LOW
FIGURE 433-c. Serial Output, Unexpanded or Master Operation
TL/F/9544-17
4-388
Timing Waveforms (Continued)
1.SV
CPSO tPLH tPHL
05
ORE
TOS
Conditions: Data in stack, TOP HIGH, IES HIGH when initiated
FIGURE 433-d. Serial Output, Slave Operation
TOP
1.SV
1.SV 1.SV
TL/F/9544-18
:;~~ =1~
Oo-03 - - - - - - - - - - - - - - 1 - . 5 - V......-.=J_N_EW_O_U_TP_U_T__
Conditions: IES LOW when initiated, OE, CPSO LOW; data available in stack
FIGURE 433-e. Parallel Output, 4-Bit Word or Master in Parallel Expansion
TL/ F/9544-19
Conditions: TTS connected to IRF, TOS connected to ORE, IES, OES, OE, CPSO LOW, TOP HIGH
FIGURE 433-f. Fall Through Time
TL/F/9544-20
4-389
Timing Waveforms (Continued)
PL
1.SV
1.SV STABLE 1.SV
TTS {note 2)
t9 =0
1.SV (note 3)
Conditions: Stack not full, JES LOW when initialized
FIGURE 433-g. Parallel Load Mode, 4�Bit Word (Unexpanded) or Master In Parallel Expansion
TLIF/9544-21
PL
1.SV STABLE 1.SV
__..,____
tPLH1.SV
1.SV
-t,
1.5V
Conditions: Stack not full, device initialized (Note 1) with IES HIGH
FIGURE 433-h. Parallel Load, Slave Mode
Note 1: Initialization requires a master reset to occur after power has been applied. Note 2: TTS normally connected to IRF. Note 3: If stack is full, IRF will stay LOW.
TL/F/9544-22
4-390
U1
~National
.N....
~Semiconductor
54F/74F521
a-ait Identity Comparator
General Description
The 'F521 is an expandable 8-bit comparator. It compares two words of up to eight bits each and provides a LOW output when the two words match bit for bit. The expansion
input iA = s also serves as an active LOW enable input.
Features
� Compares two 8-bit words in 6.5 ns typ � Expandable to any word length � 20-pin package
Ordering Code: see sections Logic Symbols
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
IEEE/I EC
TA=B
COMP
Gt
I>
Ao
0
A1
A2
A3
A4
As
As
A1
tP=O
Bo
0
B1
B2
B3 0
B4
Bs
Bs
B7 -7 -----
TL/F/9545-1
TA=B
Ao 2
Bo 3 A1 4 B1 5
A2 B2 7 A3 8
B3 GND 10
20 Yee 19 OA=B
18 B1 17 A1 16 Bs 15 As 14 Bs 13 As 12 B4 11 A4
TL/F/9545-2
TL/F/9545-4
Pin Assignment forLCC
A3 B2 A-z B1 A1
rn rz:rn:rn:rn::i
B3 [[] GND Ii]]
A4 [i]
B4 !l1] As~
[I]B0 11JAo
ITJTA=B ~Vee
lim OA=B
~ [j]Jli]] [Z]li]] BsAsBsA7~
TL/F/9545-3
4-391
Unit Loading/Fan Out: See Section 2 for U.L. definitions
Pin Names
Ao-A7 Bo-87 TA=B OA=B
Description
Word A Inputs Word B Inputs Expansion or Enable Input (Active LOW) Identity Output (Active LOW)
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loHlloL
1.0/1.0 1.0/1.0 1.0/1.0 50/33.3
20 �A/-0.6 mA 20 �A/-0.6 mA 20 �A/-0.6 mA -1 mA/20 mA
Truth Table
Inputs
IA= B
L L H H
A,B
A = B* A*B A = B* A*B
Output
OA= B
L H H H
H = HIGH Voltage Level
L = LOW Voltage Level �Ao = Bo. A1 = 81. A2 = 82. etc.
Logic Diag.ram
b Ao
80----{>o
b A1
81----{>o
b A2
82----{>o
b A3
83----{>o
b A4
84----{>o
OA=B
b As
85----{>o
b As
8s----{>o
b A7
87----{>o
TA=B
TL/F/9545-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-392
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 1so0 c
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to+ 7.0V
Input Voltage (Note 2)
-0.5V to + 7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5VtoVee - 0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
U1
N
Recommended Operating
..Ao
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�cto +70�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
V1H
Input HIGH Voltage
V1L
Input LOW Voltage
Veo
Input Clamp Diode Voltage
54F/74F Min Typ Max
Units Vee
Conditions
2.0
v
Recognized as a HIGH Signal
0.8
v
Recognized as a LOW Signal
-1.2
v
Min l1N = -18 mA
VoH
Output HIGH
Voltage
54F 10% Vee 2.5
74F 10% Vee 2.5
74F5% Vee
2.7
ioH = -1 mA
v
Min loH = -1 mA
loH = -1 mA
VoL
Output LOW
Voltage
54F 10% Vee 74F 10% Vee
0.5
v
Min loL = 20 mA
0.5
loL = 20 mA
l1H
Input HIGH
54F
Current
74F
20.0
5.0
�A
Max V1N = 2.7V
lsv1
Input HIGH Current 54F
Breakdown Test
74F
100
7.0
�A Max V1N = 7.0V
leEx
Output HIGH
54F
Leakage Current
74F
250
50
�A
Max VouT =Vee
V10
Input Leakage
Test
74F
4.75
v
110 = 1.9�A 0.0 All Other Pins Grounded
loo
Output Leakage
Circuit Current
74F
3.75
�A
0.0 V100 = 150 mV All Other Pins Grounded
l1L
Input LOW Current
los
Output Short-Circuit Current
-0.6
mA
Max V1N = 0.5V
-60
-150 mA Max VouT = ov
leeH
Power Supply Current
21
32
mA Max Vo= HIGH
4-393
,...
N
Lt> AC Electrical Characteristics: see Section 2 for waveforms and Load Configurations
Symbol
Parameter
tPLH
Propagation Delay
tPHL
An or Bn to OA=B
tPLH
Propagation Delay
tPHL
TA=stoOA=B
74F
TA= +25�C Vee= +5.0V
CL= 50 pF
Min
Typ
Max
3.0
7.0
10.0
4.5
7.0
10.0
3.0
5.0
6.5
3.5
6.5
9.0
54F
TA, Vee= Mil CL= 50 pF
Min
Max
3.0
14.0
4.0
15.0
3.0
8.5
3.5
13.5
74F
TA, Vee= Com CL= 50 pF
Min
Max
3.0
11.0
4.0
11.0
3.0
7.5
3.5
10.0
Applications
Ao Bo
Ripple Expansion
A1 B1
As Bs A15B15
A15B15 A23B23
Fig. Units
No.
ns
2-3
ns
2-3
ENABLE LOW
IA=B OA=B
IA=B OA=B
Ao Bo
Parallel Expansion
A1 B1
As Bs A15B15
IA=B OA=B
TL/F/9545-6
A1sB1s A23 B23
TL/F/9545-7
4-394
~~SNemaitcoinoduncatolr
54F/74F524
8-Bit Registered Comparator
General Description
The 'F524 is an 8-bit bidirectional register with parallel input and output plus serial input and output progressing from LSB to MSB. All data inputs, serial and parallel, are loaded by the rising edge of the input clock. The device functions are controlled by two control lines (S0, S1) to execute shift, load, hold and read out.
An 8-bit comparator examines the data stored in the registers and on the data bus. Three true-HIGH, open-collector outputs representing 'register equal to bus', 'register greater than bus' and 'register less than bus' are provided. These outputs can be disabled to the OFF state by the use of Status Enable (SE). A mode control has also been provided
to allow twos complement as well as magnitude compare. Linking inputs are provided for expansion to longer words.
Features
� 8-Bit bidirectional register with bus-oriented input-output � Independent serial input-output to register � Register bus comparator with 'equal to', 'greater than'
and 'less than' outputs � Cascadable in groups of eight bits � Open-collector comparator outputs for AND-wired
expansion
a Twos complement or magnitude compare
Ordering Code: See Section 5 Logic Symbols
LT GT EQ
TL/F/9546-1
IEEE/I EC
O o 1 } M3
~=HOLI =READ 2=SHIFT
3=LOAD
C4/2-+
MS MAGNITUDE M6 TWO'S
COMPLEMENT
C/SI
20
C/SO
SE
COMP
LT GT EQ
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
So 1 l/Oo 1/01 1/02 1/03 1/04 1/05 1/05 8 1/07 9 GND 10
20 Vee 19 S1 18 SE 17 C/SI 16 C/SO 15 EQ 1' GT 13 LT 12 M 11 CP
TL/F/9546-2
Pin Assignment forLCC
l/051/05l/041/03'J02 IIHIJlfil[[)[I)
lGN/D0 [2] 7 1 I J O r n vmo l/O,o
cP ITI!
ms0
Milli
~Vee
LT I!]
il]]S1
~~l!]][Z]l!ID
er EQ C/SO C/SI SE
TL/F/9546-3
TL/F/9546-4
4-395
Unit Loading/Fan Out: see section 2 for U.L. definitions
Pin Names
Description
So,S1 C/SI CP SE M l/Oo-1/07
C/SO LT EQ GT
Mode Select Inputs Status Priority or Serial Data Input Clock Pulse Input (Active Rising Edge) Status Enable Input (Active LOW) Compare Mode Select Input Parallel Data Inputs or TRI-STATE� Parallel Data Outputs Status Priority or Serial Data Output Register Less Than Bus Output Register Equal Bus Output Register Greater Than Bus Output
�oc = Open Collector
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loHlloL
1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 3.5/1.083 150/40 (33.3) 50/33.3 OC*/33.3 OC*/33.3 OC*/33.3
20 �A/-0.6 mA 20 �A/-0.6 mA 20 �A/-0.6 mA 20 �A/-0.6 mA 20 �A/-0.6 mA 70 �A/-0.65 mA -3 mA/24 mA (20 mA) -1 mA/20 mA
*/20 mA */20 mA */20 mA
Functional Description
The 'F524 contains eight D-type flip-flops connected as a shift register with provision for either parallel or serial loading. Parallel data may be read from or loaded into the registers via the data bus 1/00-1107. Serial data is entered from the C/SI input and may be shifted into the register and out through the C/SO output. Both parallel and serial data entry occur on the rising edge of the input clock (CP). The operation of the shift register is controlled by two signals So and S1 according to the Select Truth Table. The TRI-STATE parallel output buffers are enabled only in the Read mode.
One port of an 8-bit comparator is attached to the data bus while the other port is tied to the outputs of the internal register. Three active-OFF, open-collector outputs indicate whether the contents held in the shift register are 'greater than', (GT), 'less than' (LT), or 'equal to' (EQ) the data on the input bus. A HIGH signal on the Status Enable (SE) input disables these outputs to the OFF state. A mode control input (M) allows selection between a straightforward magnitude compare or a comparison between twos complement numbers.
For 'greater than' or 'less than' detection, the C/SI input must be held HIGH, as indicated in the Status Truth Table. The internal logic is arranged such that a LOW signal on the C/SI input disables the 'greater than' and 'less than' outputs. The C/SO output will be forced HIGH if the 'equal to' status condition exists, otherwise C/SO will be held LOW. These facilities enable the 'F524 to be cascaded for word length greater than eight bits.
Word length expansion (in groups of eight bits) can be achieved by connecting the C/SO output of the more significant byte to the C/SI input of the next less significant byte and also to its own SE input (see Figure 1 ). The C/SI input of the most significant device is held HIGH while the SE input of the least significant device is held LOW. The corresponding status outputs are AND-wired together. In the case of twos complement number compare, only the Mode input to the most significant device should be HIGH. The Mode inputs to all other cascaded devices are held LOW.
Suppose that an inequality condition is detected in the most significant device. Assuming that the byte stored in the register is greater than the byte on the data bus, the EQ and LT outputs will be pulled LOW and the GT output will float HIGH. Also the C/SO output of the most significant device will be forced LOW, disabling the subsequent devices but enabling its own status outputs. The correct status condition is thus indicated. The same applies if the registered byte is less than the data byte, only in this case the EQ and GT outputs go LOW and LT output floats HIGH.
If an equality condition is detected in the most significant device, its C/SO output is. forced HIGH. This enables the next less significant device and also disables its own status outputs. In this way, the status output priority is handed down to the next less significant device which now effectively becomes the most significant byte. The worst case propagation delay for a compare operation involving 'n' cascaded 'F524s will be when an equality condition is detected in all but the least significant byte. In this case, the status priority has to ripple all the way down the chain before the correct status output is established. Typically, this will take
35 + 6(n-2) ns.
Select Truth Table
So S1
Operation
L
L
Hold-Retains Data in Shift Register
L
H
Read-Read Contents in Register onto
Data Bus, Data Remains in
Register Unaffected by Clock
H
L
Shift-Allows Serial Shifting on Next
Rising Clock Edge
H
H
Load-Load Data on Bus
into Register
4-396
Functional Description (Continued)
Number Representation Select Table
M
Operation
L
Magnitude Compare
H
Twos Complement Compare
Status Truth Table (Hold Mode)
Inputs
Outputs
SE C/SI Data Comparison EQ GT LT C/SO
H H H L
x
HHH 1
x
HHH L
L L OA-OH > l/Oo-1/07 L H H L
L L OA-OH = l/Oo-1/07 H H H L
L L OA-OH < l/Oo-1/07 L H H L L H OA-OH > l/Oo-1/07 L H L L
L H OA-OH = l/Oo-1/07 H L L H
L H OA-OH < l/Oo-1/07 L L H L
1 = HIGH if data are equal, otherwise LOW
H = HIGH Voltage Level
L = LOW Votlage Level
X = Immaterial
H=TWO'S COMPLEMENT L=MAGNITUDE
H
GREATER THAN EQUAL TO LESS THAN
M GT EQ LT
SE
C/SI
C/SO
So S1
1/0
M GT EQ LT SE
C/SI
C/SO
1/0
Yee
M GT EQ LT
SE
1/0
RD
WR
8
8
8
MSB FIGURE 1. Cascading 'F524s for Comparing Longer Words
LSB
TL/F/9546-6
4-397
Block Diagram
C/SI
J,t
~
---~
~
---~ 1-;1_
"11-
~
A
B
c
D
E
r
G
H ~
(.)
8-BIT SHIFT REGISTER
g 0
-cC
0 -'
:0 c
t: ~
OA Oe Oc Oo OE OF Oc OH i---.
CP
2 TO 4 DECODE
LOAD HOLD SHIFT READ
t.4
Notes: 1. TRI-STATE Output 2. Open-Collector Output
Ao
A1
A2
A3
A4
A5
As
IX
r)D-1 ~
r--
A1
~
::E
0
(.)
Bo
e,
~ .,!,
82
83
84
85
85
RD-1 ~
87
LT EQ GT
1 .-LJ
~
~
~
A
B t.IUX
s
C/SO
TL/F/9546-5
4-398
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 15o�c
Ambient Temperature under Bias
- 55�C to + 125�c
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to + 7.0V
Input Voltage (Note 2)
-0.5V to + 7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
-0.5VtoVee -0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�c o�c to +10�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
54F/74F Min Typ Max
Units Vee
Conditions
V1H
Input HIGH Voltage
V1L
Input LOW Voltage
Veo
Input Clamp Diode Voltage
2.0
v
Recognized as a HIGH Signal
0.8
v
Recognized as a LOW Signal
-1.2
v
Min l1N = -18 mA
VoH
Output HIGH
54F 10% Vee 2.5
Voltage
54F 10% Vee 2.4
74F 10% Vee 2.5
74F 10% Vee 2.4
74F5% Vee 2.7
74F5% Vee 2.7
loH = -1 mA
loH = -3mA
loH = -1 mA
v
Min
loH = -3 mA
loH = -1 mA
loH = -3 mA
VoL
Output LOW
54F 10% Vee
Voltage
74F 10% Vee
74F 10% Vee
0.5
loL = 20 mA (I/On)
0.5
v
Min loL = 20 mA (I/On)
0.5
loL = 24 mA (LT, GT, EQ, C/SO)
l1H
Input HIGH
54F
Current
74F
20.0
5.0
�A Max V1N = 2.7V
lsv1
Input HIGH Current 54F
Breakdown Test
74F
100
�A Max V1N = 7.0V
7.0
leEX
Output HIGH
54F
Leakage Current
74F
250 50
�A Max Vour =Vee
V10
Input Leakage
Test
74F
4.75
v
0.0 110 = 1.9 �A
All Other Pins Grounded
loo
Output Leakage
Circuit Current
74F
3.75
�A
0.0
V100 = 150 mV All Other Pins Grounded
l1L
Input LOW Current
-0.6 mA Max V1N = 0.5V
l1H + lozH Output Leakage Current
70
�A Max V110 = 2.7V
l1L + lozL Output Leakage Current
-650 �A Max V110 = 0.5V
los
Output Short-Circuit Current
-60
-150 mA Max Vour = ov
4-399
DC Electrical Characteristics (Continued)
Symbol loHe
Parameter
Open Collector, Output OFF Leakage Test
54f/74f
Units
Vee
Min
Typ
Max
Conditions
250
�A
Min
Vour =Vee
lceH lceL lcez
Power Supply Current Power Supply Current Power Supply Current
128
180
mA
Max
Vo= HIGH
128
180
mA
Max
Vo= LOW
128
180
mA
Max
Vo= HIGHZ
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
fmax tPLH tPHL tPLH tPHL
tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH
tPLH tPHL
tPLH tPHL
tPLH tPHL
tPLH tPHL tPLH tPHL
tPLH tPHL
tPLH �tPHL
tPLH tPHL
Maximum Shift Frequency
Propagation Delay I/On to EQ
Propagation Delay I/On to GT
Propagation Delay I/On to LT
Propagation Delay I/On to C/SO
Propagation Delay CPto EQ
Propagation Delay CPtoGT
Propagation Delay CPto LT
Propagation Delay CP to CISO (Load)
. Propagation Delay CP to C/SO (Serial Shift)
Propagation Delay C/SI to GT
Propagation Delay C/SI to LT
Propagation Delay So, S1 to CISO Propagation Delay SE to EQ
Propagation Delay SE to GT
Propagation Delay SE to LT
Propagation Delay C/SI to CISO
74f
TA= +25�C Vee= +5.0V
CL= 50 pf
Min
Typ
Max
50
75
9.0
16.5
20.0
5.0
9.5
12.0
8.5
14.1
19.0
6.5
13.0
16.5
7.0
15.5
20.0
4.5
10.0
14.0
8.0
15.2
19.5
6.0
12.5
16.0
10.0
20.0
25.0
4.0
8.5
16.5
10.0
16.5
21.0
8.5
17.0
22.0
9.0
20.0
25.0
5.5
13.5
17.0
8.5
16.5
21.0
5.0
10.0
13.0
4.5
9.0
11.5
9.0
15.0
19.0
3.0
6.5
8.5
8.0
15.5
20.0
3.5
6.5
8.5
6.5
11.5
14.5
5.5
14.0
18.0
3.5
8.0
10.5
2.5
6.0
8.0
6.5
12.5
16.0
3.5
6.0
8.0
5.0
10.5
13.5
3.5
6.0
8.0
4.0
8.5
11.0
4.0
8.5
11.0
54F
TA, Vee= Mil CL= 50 pf
Min
Max
74f
TA, Vee= Com CL= 50 pf
Min
50
9.0 5.0
8.5 6.5
7.0 4.5
8.0 6.0
10.0 4.0
10.0 8.5
9.0 5.5
Max
21.0 13.0 20.0 17.5 21.0 15.0 20.5 17.0 26.0 17.5 22.0 23.0 26.0 18.0
8.5
22.0
5.0
14.0
4.5
12.5
9.0
20.0
3.0
9.5
8.0
21.0
3.5
9.5
6.5
15.5
5.5
19.0
3.5
11.5
2.5
9.0
6.5
17.0
3.5
. 9.0
5.0
14.5
3.5
9.0
4.0
12.0
4.0
12.0
Units
Fig. No.
MHz 2-1
ns 2-3
ns 2-3
ns 2-3
ns 2-3 ns 2-3 ns 2-3 ns 2-3 ns 2-3
4-400
AC Electrical Characteristics: See Section 2 tor Waveforms and Load Configurations
Symbol
Parameter
tPLH tPHL
tPLH tPHL
tPLH tPHL
tpLH tPHL
tPLH tPHL
tpzH tpzL
tpHz tpLz
Propagation Delay MtoGT
Propagation Delay M to LT
Propagation Delay So, S1 to EQ
Propagation Delay So, S1 to GT
Propagation Delay So. S1 to LT
Output Enable Time So, S1 to I/On
Output Disable Time So, S1 to I/On
74F
TA= +25�C Vee= +5.0V
CL= 50pf
Min
Typ
Max
8.0
15.0
19.5
6.0
12.0
15.5
8.0
17.0
22.0
4.5
9.5
12.0
15.0
25.0
33.0
9.0
15.0
19.0
10.5
18.0
23.0
10.5
18.0
23.0
13.0
22.0
28.0
12.0
19.0
24.0
4.5
10.0
13.0
5.5
11.0
15.0
3.5
8.0
12.0
4.5
9.6
12.5
54F
TA, Vee= Mil CL= 50 pf
Min
Max
74F
TA, Vee= Com CL= 50pf
Min
Max
8.0
20.5
6.0
16.5
8.0
23.0
4.5
13.0
15.0
35.0
9.0
20.0
10.5
24.0
10.5
24.0
13.0
30.0
12.0
25.0
4.5
14.0
5.5
16.0
3.5
13.0
4.5
13.5
AC Operating Requirements: see Section 2 tor Waveforms
Symbol
Parameter
t 5 (H) t5 (L)
th(H) th(L)
t5 (H) t5 (L)
th(H) th(L)
t 5 (H) t 5 (L)
th(H) th(L)
tw(H)
Setup Time, HIGH or LOW I/On to CP
Hold Time, HIGH or LOW I/On to CP
Setup Time, HIGH or LOW So or S1 to CP
Hold Time, HIGH or LOW So orS1 to CP
Setup Time, HIGH or LOW C/SI to CP
Hold Time, HIGH or LOW C/SI to CP
Clock Pulse Width, HIGH
74F
TA= +25�C Vee= +5.0V
Min
Max
6.0 6.0
0 0
10.0 10.0
0 0
7.0 7.0
0 0
5.0
54F
TA, Vee= Mil
Min
Max
74F
TA, Vee= Com
Min
Max
6.0 6.0
0 0
10.0 10.0
0 0
7.0 7.0
0 0
5.0
Units
Fig. No.
ns
2-3
ns
2-3
ns
2-5
Units
Fig. No.
ns
2-6
ns
2-6
ns
2-6
ns
2-4
4�401
a.n
aN.n ~National
U Semiconductor
54F/74F525
Programmable Counter
General Description
The 'F525 is a multi-function 28-pin device. It consists of a 16-bit count-down counter, logic to control the counter, logic to control the state of the outputs and a PLA to decode the particular function selected by the user. The list of highspeed timing applications include:
Features
� Baud rate generator � Digitally programmed monostable � Variable system frequency generator � Digital filter variable sampling rate � 16-bit data path � External trigger � Extremely accurate one shot w/pulse widths from
50 ns to 3.27 ms @CP = 40 MHz
Ordering Code: see Sections Logic Symbol
Connection Diagrams
Mo Do D1 D2 D3 D4 D5 D5 D1 Ds Dg D10 D11 D12 D13 D14 D15
M1
M2
XTR
WE
CP
MR
XTAL
0/2
TL/F/9547-1
Pin Assignment DIP, SOIC and Flatpak
0/2 1 o 2
XTR 3
Do D1 D2 6 D3 7 D4 8 Ds 9 D5 1D D1 11
WE 12
XTAL 13 GND 14
28 Yee
27 M2 26 M1 25 Mo 24 D15 23 D14 22 D13 21 D12 20 D11 19 D10 18 Dg 17 Ds
16 MR
15 CP
TL/F/9547-2
Pin Assignment for LCC and PCC
D1 D5 D5 D4 D3 D2 D1
[]] IIQl mIII [I] III @J
WE[]]
XTAL Ii] GND Ii]
CP Ii]]
MR Ii]] Ds IIZI
Dg li]J
[!]Do
[IJ XTR
rn Oo
moo/2 ~Vee
lllJ M2 Im M1
l!illlmliillllll~H~~ D10D11D12D13D14D15 Mo
TL/F/9547-3
4-402
(J1
I\)
Unit Loading/Fan Out: See Section 2 for U.L. definitions
(J1
Pin Names
0
012 Mo-M2 MR CP Do-D15 WE XTR XTAL
Description
Ouput (Primarily indicates when the counter has reached zero) Output (Divides 0 by 2) Status Inputs Master Reset Clock Pulse Data Inputs Write Enable Input External Trigger Input Crystal Output
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loHlloL
50/33.3
-1 mA/20 mA
50/33.3 1.0/1.0 1.0/1.0 1.0/2.0 1.0/1.0 1.0/1.0 1.0/3.0 1.0/1.0
-1 mA/20 mA 20 �A/-0.6 mA 20 �Al - 0.6 mA 20 �Al -1.2 mA 20 �A/-0.6 mA 20 �A/-0.6 mA 20 �A/-1.8 mA 20 �A/-0.6 mA
Functional Description
The multi-function aspect of the device consists of eight different modes of operation. An explanation of the operation of the device in each of the modes follows. However, there is one operation that is independent of the selected mode: the loading of data. Data is latched into a set of data latches when WE is brought from a LOW to a HIGH state. The latches are transparent when WE is held LOW.
Operation Notes:
1. Device should be reset before operation.
2. The XTR input acts as a select line for the clock.
3. With XTR low, the clock goes into the counter.
4. With XTR high, the clock loads the counter.
5. In mode 4 and 5, during counting, the counter cannot be reloaded. XTR high freezes the count.
6. Mode 7 is the only auto-reload mode, all other modes require and XTR pulse to begin.
7. Loading O into the latches idles the device.
MODE 0: Interval Timer with Level Output
While XTR is HIGH, the data in the data latches is loaded into the counter upon the next positive edge of CP. The negative edge of XTR enables the count-down to begin with the next positive edge of CP. When the count reaches zero, 0, normally LOW, is brought HIGH and 0/2 toggles state. Taking XTR HIGH at any time enables the data in the data latches to be loaded into the counter on the rising edge of CP and clears 0. See Figure 1.
MODE 1: Interval Timer with Inverted Level Output
The operation is exactly the same as in Mode 0 except that 0 is normally HIGH and goes LOW when the count reaches zero. 012 toggles on the negative-edge of 0. See Figure 1.
MODE 2: Interval Timer with Pulse Output
While XTR is HIGH, the data in the data latches is loaded into the counter upon the next positive edge of CP. The negative edge of XTR enables the count-down to begin with the next positive edge of CP. When the count reaches
zero, 0, normally LOW, is brought HIGH for a single period of CP. 0/2 toggles state on the positive edge of 0. Taking XTR HIGH at any time causes the data in the data latches to be loaded into the counter on the rising edge of CP and clears 0. See Figure 2.
MODE 3: Interval Timer with Inverted Pulse Output
The operation is exactly the same as in Mode 2 except that 0 is normally HIGH and goes LOW for a single period of CP. 012 toggles on the negative edge of 0. See Figure 2.
Function Table
M2
M1
Mo
Function
0
0
0
ModeO
0
0
1
Mode 1
0
1
0
Mode2
0
1
1
Mode3
1
0
0
Mode4
1
0
1
Mode5
1
1
0
Mode6
1
1
1
Mode?
MODE 4: Interval Timer, Pulse Output with Count Hold
While XTR is HIGH, the data in the data latches is loaded into the counter upon the next positive edge of CP. The negative edge of XTR enables the count-down to begin with the next positive edge of CP. When the count reaches zero, 0, normally low, is brought HIGH for a single period of CP. 012 toggles state on the positive edge of 0. Taking XTR HIGH before the counters reach zero, stops the count-down from the point where it was held. Data cannot be reloaded into the counter until a count of zero is reached. See Figure 3.
MODE 5: Interval Timer, Inverted Pulse Output with Count Hold
The operation is exactly the same as Mode 4 except that 0 is normally HIGH and goes LOW for a single period of CP. 012 toggles on the negative-edge of 0. See Figure 3.
4-403
Functional Description (Continued)
MODE 6: Retriggerable Synchronous One-Shot
When XTR is HIGH, the data in the data latches is loaded into the counter upon the positive edge of CP. The negative edge of XTR enables the count-down to begin with the next positive edge of CP, wehre Q, normally LOW, is then brought HIGH and the counter is decremented when the count reaches zero, Q is brought LOW, and Q/2 is toggled. Bringing XTR HIGH during the count-down will allow the data in the data latches to be loaded into the counter with the next positive edge of CP, but will not affect Q. See Figure 4. NOTE that the pulse width of Q will be N-1 clock cycles, where N is the number loaded into the counter.
N = 1 should not be used as this may cause unpredictable
results.
Block Diagram
MODE 7: Frequency Generator
When XTR is HIGH, the data in the data latches is loaded into the counter upon the positive edge of CP. The negative edge of XTR enables the count-down to begin with the next positive edge of CP. When the count reaches zero, Q, normally LOW, is brought HIGH for a single period of CP and Q/2 is toggled. The same clock edge that brings Q HIGH, also loads the data in the data latches into the counter. The counter will start to count on the next positive edge of CP. This mode will run continuously after an initial XTR until stopped by MR. Taking XTR HIGH at any time causes the data in the data latches to be loaded into the counter and Q output to be cleared with the next positive edge of CP. See Figures.
COUNTER CONTROL
LOGIC
COUNT-DOWN COUNTER
OUTPUT
a
STATE
CONTROL
LOGIC
0/2
TL/F/9547-4
4-404
U1
N
Timing Diagrams
U1
--~~~~~~~~--------r--~\~----------~-
CP
on:3:X)(XXXXXXXXXXXXXXXXX)()(XXXXX::::XXXXXXXXX
--------------- a
~~~~~-~
'---~~~-------~
�With XTR HIGH, the rising edge of CP loads data from the latches to the counter. @With XTR LOW, the rising edge of CP begins count-down cycle. �When the count reaches zero, 0 goes HIGH, and 012 toggles state. �The next occurrence of XTR clears 0.
FIGURE 1. MODE 0 and MODE 1 (Inverse Output of Mode 0)
Mn= ooo, 001
TL/F/9547-5
0n:3:X)(xxxxxxxxxxxxxxxxxxxxxxxx:::::xxxxxxxxxxxxxxxx
Q
~r---\.~----------------------~
~----~~~~~~-~,......~~~~~~~~~~~~~~~
0/2
~--------------
�With XTR HIGH, the rising edge of CP loads data from the latches to the counter.
@With XTR LOW, the rising edge of CP begins the count-down cycle. �When the count reaches zero, 0 goes HIGH for one period of CP, and 012 toggles state.
FIGURE 2. MODE 2 and MODE 3 (Inverse Output of Mode 2)
Mn= 010, 011
TL/F/9547-6
~
CLK
XTR
x Dn "4"
DON1 CARE
a (4) -----------------------------~r--\~----------------
a (5)
0/2~~~~~~~~~~~~~~~~~-''-~~~~~~~~~~~~
FIGURE 3. MODE 4 and MODE 5
Mn= 100, 101
�With XTR HIGH, the rising edge of CP loads data from the latches into the counter.
@With XTR LOW, the rising edge of CP begins the count-down.
TL/F/9547-7
�With XTR HIGH, during count-down, the rising edge of CP does nothing. �When the count reaches zero, 0 goes HIGH for one clock cycle and 012 toggles state. Note: Once the count reaches zero, the counter can be reloaded with XTR HIGH.
4-405
Timing Diagrams (Continued)
XTR
~'---------------------
~
CP
0n:!)(X){xxxxxxxxxxxxxxxxxxxxx)()(xxxxXX::XXXXXXXXXXX
0
l(2)
\ ~
~I
--------------~-~~~---~-~-~----
0/2
--------------------------------------------~
FIGURE 4. MODE 6
Mn= 110
TL/F/9547-8
�With XTR HIGH, the rising edge of CP loads data from the latches to the counter.
�With XTR LOW, the rising edge of CP begins the count, and Q goes HIGH.
@When the count reaches zero, Q goes LOW, and Q/2 toggles state. Bringing XTR HIGH before count reaches zero will reload the counter, but not affect Q.
Notes:
Loading N = 0 halts counter; loading N = 1 will result in undefined operation.
Pulse width = (2/CP) � (N-1)
XTR
CP
q; ~
~ ~
0
I\
I\
0/2
x ~
x ~
FIGURE 5. MODE 7
Mn= 111
�With XTR HIGH, the rising edge of CP, loads data from the latches to the counter. �On the falling edge of XTR, the rising edge of CP begins count-down. @When count reaches zero, Q goes HIGH for one period of CP, and Q/2 toggles on the Q rising edge. �On the rising edge of CP on which Q goes LOW, the counters are reloaded. �Count-down begins again.
TL/F/9547-9
4-406
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
-65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5Vto +7.0V
Input Voltage (Note 2)
-0.5V to + 7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5VtoVee -0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
C11
N
Recommended Operating
C11
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C o�cto +70�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
V1H
Input HIGH Voltage
V1L
Input LOW Voltage
Veo
Input Clamp Diode Voltage
54F/74F Min Typ Max
Units Vee
Conditions
2.0
v
Recognized as a HIGH Signal
0.8
v
Recognized as a LOW Signal
-1.2
v
Min l1N = -18mA
VoH
Output HIGH
Voltage
54F 10% Vee 2.5
74F 10% Vee 2.5
74F5% Vee
2.7
loH = -1 mA
v
Min loH = -1 mA
loH = -1 mA
VoL
Output LOW
Voltage
54F 10% Vee 74F 10% Vee
0.5 0.5
v
Min loL = 20 mA
loL = 20 mA
l1H
Input HIGH
54F
Current
74F
20.0
�A
Max V1N = 2.7V
5.0
lsv1
Input HIGH Current 54F
Breakdown Test
74F
100
V1N = 7.0V
�A Max
7.0
leEX
Output HIGH
54F
Leakage Current
74F
250
�A
Max VouT =Vee
50
V10
Input Leakage
74F
4.75
Test
v
0.0 110 = 1.9 �A
All Other Pins Grounded
loo
Output Leakage
74F
Circuit Current
3.75
�A
0.0 V100 = 150 mV All Other Pins Grounded
l1L
Input LOW Current
los
Output Short-Circuit Current
-0.6
mA
Max V1N = 0.5V
-60
-150 mA Max VouT = ov
leeH
Power Supply Current
106 160
mA Max Vo= HIGH
leeL
Power Supply Current
106 160
mA Max Vo= LOW
4-407
I.I)
C\I
I.I) AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
fmax
tpLH tpHL
tPLH tPHL
tPLH tpHL
tPLH tPHL
tPLH tPHL
tPLH tPHL
Maximum Clock Frequency
Propagation Delay CPtoQ
Propagation Delay CPto0/2
Propagation Delay XTR too
Propagation Delay MRtoO
Propagation Delay MRto0/2
Propagation Delay MntoQ
74F
TA= +25�C Vee= +5.0V
CL= 50 pF
Min
Typ
Max
50
60
9.0
16.0
20.5
8.0
12.0
15.5
9.0 10.0
15.5 15.5
20.0 20.0
8.5
12.0
15.5
6.0
10.5
13.5
11.5 9.0
16.5 12.5
21.0 16.0
8.0
14.0
17.5
7.0
10.5
13.5
10.0 10.5
15.0 17.0
19.0 21.5
54F
TA, Vee= Mil CL= 50 pF
Min
Max
74F
TA, Vee= Com CL= 50pF
Units
Fig. No.
Min
Max
40
MHz 2-1
8.0
22.5
ns 2-3
7.0
17.5
8.0
22.0
ns 2-3
9.0
22.0
7.5
17.5
ns 2-3
5.0
15.0
10.5
23.0
ns 2-3
8.0
18.0
7.0
19.5
ns 2-3
6.0
15.0
9.0
21.0
ns 2-3
9.5
23.5
AC Operating� Requirements: See Section 2 tor waveforms
Symbol
Parameter
t5(H) t5(L) th(H) th(L) t5 (H) t5(L) th(H) th(L) t 5 (H) t5 (L) th(H)
t5 (H)
t5 (L)
tw(H) tw(L) tw(L) tw(H) tw(L)
tree
tree
Setup Time, HIGH or LOW Dn to WE
Hold Time, HIGH or LOW Dn to WE
Setup Time, HIGH or LOW Dn to CP
Hold Time, HIGH or LOW Dn toCP
Setup Time, HIGH or LOW XTR toCP
Hold Time, HIGH or LOW XTR toCP
Setup Time, HIGH or LOW ModetoCP
XTR Pulse Width, HIGH
MR Pulse Width, LOW
WE Pulse Width, LOW
CP Pulse Width HIGH or LOW
Recovery Time MR toCP
Recovery Time Mode to CP
74F
TA= +25�C Vee= +5.0V
Min
Max
2.0 4.0
0 2.0
9.0 10.5
0 0
7.0 8.0
0
33.5 33.5 11.5 7.0 4.5 3.5 9.5
5.0
30.0
54F
TA, Vee= Mil
Min
Max
74F
TA, Vee= Com
Min
Max
2.5 4.5
0 2.5
10.0 12.0
0 0
8.0 9.0
0
35.5 35.5 13.0
8.0 5.0 4.0 10.5
6.0
Units
Fig. No.
ns
2-6
ns
2-6
ns
2-6
ns
2-6
ns
2-6
ns
2-6
ns
2-6
ns
2-4
ns
2':"'4
ns
2-4
ns
2-4
ns
2-6
32.0
ns
2-6
4-408
~National
wwU1
U Semiconductor
54F/74F533
Octal Transparent Latch with TRI-STATE� Outputs
General Description
The 'F533 consists of eight latches with TRI-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH the bus output is in the high impedance state. The 'F533 is the same as the 'F373, except that the outputs are inverted.
Features
� Eight latches in a single package � TRI-STATE outputs for bus interfacing � Inverted version of the 'F373 � Guaranteed 4000V minimum ESD protection
Ordering Code: see sections Logic Symbols
IEEE/I EC
TL/F/9548-4
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
OE
60 Do o, 4
o, 5
62 6 D2 D3 63 GND 10
20 Vee 19 67 18 D7 17 Ds Hi Os 15 65 14 D5 13 D4 12 64 11 LE
Pin Assignment for LCC
D3 ~ 02 01 D1 (fill2JIIJ[[)GJ
63 rn
GND [QI LE [j]
64 Im
D4 Ii]
moo
rn 60
IIl 6E
~Vee Ii]) 67
~Ii]) lrn [Z] @I
D5 05 Os Ds 0,
TL/F/9548-3
TL/F/9548-2
LE OE
TL/F/9548-1
4-409
C") C")
Lt) Unit Loading/Fan Out: See Section 2 for U.L. definitions
Pin Names
Do-D7 LE OE Oo-07
Description
Data Inputs Latch Enable Input (Active HIGH) Output Enable Input (Active LOW) Complementary TRI-STATE Outputs
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loHlloL
1.0/1.0 1.0/1.0 1.0/1.0 150/40 (33.3)
20 �A/-0.6 mA 20 �A/-0.6 mA 20 �A/-0.6 mA -3 mA/24 mA (20 mA)
Function Table
Inputs
LE
OE
D
H
L
H
H
L
L
L
L
x
x
H
x
H = HIGH Voltage Level L = LOW Voltage Level
X = Immaterial
Output
0
L H
Do
z
Functional Description
The 'F533 contains eight D-type latches with TRI-STATE output buffers. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D in-
Logic Diagram
puts a setup time preceding the HIGH-to-LOW transition of LE. The TRI-STATE buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are in the bi-state mode. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches.
LE
o,
07
TL/F/9548-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-410
Absolute Maximum Ratings (Note 1)
If MilitaryI Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5Vto +7.0V
Input Voltage (Note 2)
-0.5V to + 7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
-0.5VtoVee - 0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
ESD Last Passing Voltage (Min)
4000V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
V1H V1L Veo VoH
VoL l1H lsv1 lsv1r le EX V10 loo l1L lozH lozL los lzz leez
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee 74F 5% Vee 74F 5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Input HIGH Current 54F
Breakdown (1/0)
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage
74F
Test
Output Leakage
74F
Circuit Current
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Bus Drainage Test
Power Supply Current
54F/74F
Min Typ Max
2.0
0.8 -1.2
2.5 2.4 2.5 2.4 2.7 2.7
0.5 0.5
20.0 5.0
100 7.0
1.0 0.5
250 50
4.75
-60 41
3.75
-0.6 50 -50
-150 500 61
Units
v v v
v
v
�A
�A
mA
�A
v
�A mA �A �A mA �A mA
Vee
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal Min l1N=-18mA loH = -1 mA loH = -3 mA Min loH = -1 mA loH = -3mA loH = -1 mA loH = -3mA Min loL = 20 mA loL = 24 mA
Max V1N = 2.7V
Max V1N = 7.0V
Max V1N = 5.5V
Max_ Vour =Vee
0.0
0.0
Max Max Max Max
o.ov
Max
110 = 1.9 �A All Other Pins Grounded
V100 = 150 mV All Other Pins Grounded
V1N = 0.5V Vour = 2.?V Vour = 0.5V
Vour = ov
VouT = 5.25V Vo= HIGHZ
4-411
(") (")
It) AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
tPLH tPHL
tPLH tPHL
tpzH tpzL
tpHz tpLz
Propagation Delay Dn to On Propagation Delay LE to On Output Enable Time
Output Disable Time
74F
TA= +25�C Vee= +5.0V
CL= 50 pF
Min
Typ
Max
4.0
6.7
9.0
2.5
4.4
7.0
5.0
7.1
11.0
3.0
4.7
7.0
2.0
5.9
10.0
2.0
5.6
7.5
1.5
3.4
6.5
1.5
2.7
5.5
54F
TA, Vee= Mil CL= 50 pF
Min
Max
4.0
12.0
2.5
9.0
5.0
14.0
3.0
9.0
2.0
12.5
2.0
10.5
1.5
8.5
1.5
7.5
74F
TA, Vee= Com CL= 50pF
Min
Max
4.0
10.0
2.5
8.0
5.0
13.0
3.0
8.0
2.0
11.0
2.0
8.5
1.5
7.0
1.5
6.5
AC Operating Requirements: see section 2 for waveforms
Symbol
Parameter
t 5 (H) t5(L)
th(H) th(L)
tw(H)
Setup Time, HIGH or LOW Dn to LE
Hold Time, HIGH or LOW Dn to LE
LE Pulse Width, HIGH
74F
TA= +25�C Vee= +5.0V
Min
Max
2.0 2.0
3.0 3.0
6.0
54F
TA, Vee= Mil
Min
Max
2.0 2.0
3.0 3.0
6.0
74F
TA, Vee= Com
Min
Max
2.0 2.0
3.0 3.0
6.0
Units Fig. No.
ns
2-3
ns
2-3
ns
2-5
ns
2-5
Units Fig. No.
ns
2-6
ns
2-6
ns
2-4
4-412
~National
U Semiconductor
54F/74F534 Octal D-Type Flip-Flop with TRI-STATE� Outputs
General Description
The 'F534 is a high speed, low-power octal D-type flip-flop featuring separate D-type inputs for each flip-flop and TRI-STATE outputs for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all flip-flops. The 'F534 is the same as the 'F374 except that the outputs are inverted.
Features
� Edge-triggered D-type inputs � Buffered positive edge-triggered clock � TRI-STATE outputs for bus-oriented applications � Guaranteed 4000V minimum ESD protection
Ordering Code: see sections
Logic Symbols
Connection Diagrams
Do D1 D2 D3 D4 D5 D5 D7 CP
OE
IEEE/I EC
TL/F/9549-1
OE CP
Pin Assignment for DIP, SOIC and Flatpak
6E 60 2
Do D1 4 01 5
02 D2 7 D3 8 03 9 GND 10
20 Yee
19 07 18 D7 17 D5 16 05 15 05 14 D5 13 D4 12 04 11 CP
Pin Assignment for LCC
D3 Dz 02 01 D1
[]][Z]~(fil[i]
03 [[) GND [j]J
CP (j]
04 [j] D4 II]
moo
rn 60
UJCiE Im Yee
Ii]] 07
!Bl ~!ill !ill [j]] D5 05 05 D5 0,
TL/F/9549-3
Do
Oo
D1
01
D2
02
D3
03
D4
04
D5
05
D5
05
D7
07
TL/F/9549-5
TL/F/9549-2
Unit Loading/Fan Out: See Section 2 for u.L. Definitions
54F/74F
Pin Names
Description
U.L. HIGH/LOW
Input l1H/l1L Output loHlloL
Do-D7 CP OE
Oo-01
Data Inputs
1.0/1.0
20 �A/-0.6 mA
Clock Pulse Input (Active Rising Edge)
1.0/1.0
20 �A/-0.6 mA
TRI-STATE Output Enable Input (Active LOW) 1.0/1.0
20 �A/-0.6 mA
Complementary TRI-STATE Outputs
150/40(33.3) -3 mA/24 mA (20 mA)
4-413
Functional Description
The 'F534 consists of eight edge-triggered flip-flops with individual D-type inputs and TRI-STATE complementary outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold times requirements on the LOW-to-HIGH clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops.
Logic Diagram
Function Table
Inputs
CP
OE
D
_r
L
H
_r
L
L
L
L
x
x
H
x
H = HIGH Voltage Level
L = LOW Voltage Level X = Immaterial ~ = LOW-to-HIGH Clock Transition Z = High Impedance Oo = Value stored from previous clock cycle
Output
0
L H
Do z
CP
07
TL/F/9549-4 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-414
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5Vto +7.0V
Input Voltage (Note 2)
-0.5Vto +7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
-0.5VtoVee -0.5V to+ 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
ESD Last Passing Voltage (Min)
4000V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�cto +10�c
Supply Voltage Military Commercial
+4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol V1H V1L Veo VoH
Vol l1H lsv1 leEx V10 loo l1L lozH lozL los lzz leez
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee 74F5% Vee 74F 5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage 74F
Test
Output Leakage
74F
Circuit Current
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Bus Drainage Test
Power Supply Current
54F/74F
Min Typ Max
2.0
0.8 -1.2
2.5 2.4 2.5 2.4 2.7 2.7
0.5 0.5
20.0 5.0 100 7.0
250 50
4.75
3.75
-0.6
50
-50
-60
-150
500
55
86
Units
v v v
v
v
�A
�A
�A
v
�A mA �A �A mA �A mA
Vee
Min
Min
Min Max Max Max 0.0 0.0 Max Max Max Max
o.ov
Max
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal l1N = -18 mA loH = -1 mA loH = -3 mA loH = -1 mA loH = -3 mA loH = -1 mA loH = -3 mA loL = 20 mA loL = 24 mA
V1N = 2.7V
V1N = 7.0V
Vour =Vee
110 = 1.9 �A All Other Pins Grounded V100 = 1.50 �A All Other Pins Grounded V1N = 0.5V Vour = 2.7V
Vour = o.sv Vour = ov
Vour = 5.25V Vo= HIGHZ
4-415
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
fmax
tPLH tPHL
tpzH tpzL
tpHz tpLZ
Maximum Clock Frequency Propagation Delay CPtoOn Output Enable Time
Output Disable Time
74F
TA= +25�C Vee= +5.0V
CL= 50pf
Min
Typ
Max
100
4.0
6.5
8.5
4.0
6.5
8.5
2.0
9.0
11.5
2.0
5.8
7.5
1.5
5.3
7.0
1.5
4.3
5.5
54F
TA, Vee= Mil CL= 50 pf
Min
Max
60
4.0
10.5
4.0
11.0
2.0
14.0
2.0
10.0
1.5
8.0
1.5
7.5
74F
TA, Vee= Com CL= 50pf
Min
Max
70
4.0
10.0
4.0
10.0
2.0
12.5
2.0
8.5
1.5
8.0
1.5
6.5
Units
Fig. No.
MHz 2-1 ns 2-3
ns 2-5
AC Operating Requirements: See Section 2 for Waveforms
Symbol
Parameter
t 5 (H) t5 (L)
th(H) th(L)
tw(H) tw(L)
Setup Time, HIGH or LOW Dn toCP
Hold Time, HIGH or LOW Dn to CP
CP Pulse Width HIGH or LOW
74F
TA= +25�C Vee= +5.0V
Min
Max
2.0 2.0
2.0 2.0
7.0 6.0
54F
TA, Vee= Mil
Min
Max
2.0 2.5
2.0 2.5
7.0 6.0
74F
TA, Vee= Com
Min
Max
2.0 2.0
2.0 2.0
7.0 6.0
Fig. Units No.
ns 2-6 ns 2-4
4-416
~~SNemaitcoinoduncatolr
54F/74F537
1-of-10 Decoder with TRI-STATE� Outputs
General Description
The 'F537 is one-of-ten decoder/demultiplexer with four active HIGH BCD inputs and ten mutually exclusive outputs. A polarity control input determines whether the outputs are active LOW or active HIGH. The 'F537 has TRI-STATE outputs, and a HIGH signal on the Output Enable (OE) input forces all outputs to the high impedance state. Two input
enables, active HIGH E2 and active LOW E1, are available
for demultiplexing data to the selected output in either noninverted or inverted form. Input codes greater than BCD
nine cause all outputs to go to the inactive state (i.e., same
polarity as the P input).
Ordering Code: see section 5
Logic Symbols
TL/F/9550-3
IEEE/I EC
DMUX I>
0�
EN
0,10 v
Oo
1,10 v o,
}t Ao
A1 A2 A3
2,10 v
02
3,10 v
03
4,10 v
04
5, 10 v
05
6, 10 v
Os
clc
7,10 v
07
E2
8, 10 v
Os
E:,
9, 10 v
Og
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
02 1
Ooo,
p
6E
Ao
A1
Os 9 05 B
GND 10
20 Yee 19 03 18 04 17 A3 16 A2 15 E1 14 E2 13 Og 12 Os 11 07
Pin Assignment for LCC
05 A1 Ao OE p
l!JIIJ(�:]@J[I]
osrnornoo GND [QI
!IJ01
07 [j]
ITl02
Os~
~Yee
Og [j]J
[g!03
[j}l[fil[ID[Z][ID
E2 E1 Az. A3 04
TL/F/9550-2
TL/F/9550-1
TL/F/9550-5
Unit Loading/Fan Out: See Section 2 for U.L. Definitions
Pin Names
Ao-A3
E1
E2 OE p Oo-Og
Description
Address Inputs Enable Input (Active LOW) Enable Input (Active HIGH) Output Enable Input (Active LOW) Polarity Control Input TRI-STATE Outputs
54F/74F
U.L. HIGH/LOW
Input lrHllrL Output loHlloL
1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 150/40 (33.3)
20 �A/-0.6 mA 20 �A/-0.6 mA 20 �A/ -0.6 mA 20 �A/-0.6 mA 20 �A/-0.6 mA -3 mA/24 mA (20 mA)
4-417
Truth Table
Function
Inputs
Outputs
OE E1 E2 A3 A2 A1 Ao Oo 01 02 03 04 Os Os 07 Os Og
High Impedance H x x x x x x z z z z z z z z z z
Disable
L Hxxxxx L xLxxxx
Outputs Equal P Input
Active HIGH Output {P = L)
L LHL L L L H L L L L L L L L L L LHL L L H L H L L L L L L L L L LHL LHL L L H L L L L L L L L LHL L HH L L L H L L L L L L
L LHLH L L L L L L H L L L L L L LHL HL H L L L L L H L L L L L LHL HHL L L L L L L H L L L L LHL HHH L L L L L L L H L L
Active LOW Output {P = H)
L LHH L L L L L L L L L L L H L
L LHH L L H L L L L L L L L L H
x x L L H H
H
L L L L L L L L L L
x x L L H H H
L LL L L LLLLL
L LHL L L L L HHHHHHHHH L LHL L LHH L HHHHHHHH L LHL L HL HH L HHHHHHH L LHL L HHHHH L HHHHHH
L LHLH L L HHHH L HHHHH L LHLH LHHHHHH L HHHH L LHLHHL HHHHHH L HHH L LHLHHHHHHHHHH L HH
L LHH L L L H HH H H HHH L H
L LHH L L HHHHHHHHHH L
x x L L H H
H
H H H H H H H H H H
x x L L H H H
H HH H H HH HHH
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Logic Diagram
TL/F/9550-4 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-418
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 15o�c
Ambient Temperature under Bias
- 55�C to + 125�c
Junction Temperature under Bias
- 55�C to + 175�C
Vcc Pin Potential to Ground Pin
-0.5Vto +7.0V
Input Voltage (Note 2)
-0.5Vto +7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
-0.5VtoVcc - 0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�c
o�c to +1o�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol V1H V1L Vco VoH
VoL l1H lsv1 lcEX V10 loo l1L lozH lozL los lzz lccH lccz
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee 74F5% Vee 74F5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage 74F
Test
Output Leakage 74F
Circuit Current
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Bus Drainage Test
Power Supply Current
Power Supply Current
54F/74F Min Typ Max
2.0
0.8 -1.2
2.5 2.4 2.5 2.4 2.7 2.7
0.5 0.5
20.0 5.0 100 7.0
250 50
4.75
3.75
-0.6
50
-50
-60
-150
500
56
44
66
Units v v v
v
v �A �A �A v �A mA �A �A mA �A mA mA
Vee
Min
Min
Min Max Max Max 0.0 0.0 Max Max Max Max o.ov Max Max
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal l1N = -18 mA loH = -1 mA loH = -3 mA loH = -1 mA loH = -3mA loH = -1 mA loH = -3mA loL = 20mA loL = 24mA
V1N = 2.7V
V1N = 7.0V
Vour =Vee
110 = 1.9 �A All Other Pins Grounded V100 = 150 mV All Other Pins Grounded V1N = 0.5V Vour = 2.7V Vour = o.5V Vour = ov Vour = 5.25V Vo= HIGH Vo= HIGHZ
4-419
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
tPLH tPHL
tPLH tpHL
tPLH tPHL
tPLH tPHL
tpzH tpzL
tpHz tpLz
Propagation Delay An to On
Propagation Delay
E1 to On
Propagation Delay E2to On
Propagation Delay PtoOn
Output Enable Time OE to On
Output Disable Time OE to On
74F
TA= +25�C Vee= +5.0V
CL= 50 pf
Min
Typ
Max
6.0
11.0
16.0
4.0
7.5
11.0
5.0
8.5
14.5
4.0
6.5
9.0
6.0
11.0
16.0
5.0
10.0
14.0
6.0
11.5
18.0
6.0
11.0
16.0
3.0
5.5
10.5
5.0
9.0
13.0
2.0
4.0
6.0
3.0
5.0
7.0
54F
TA, Vee= Mil CL= 50pF
Min
Max
74F
TA, Vee= Com CL= 50 pf
Min
Max
6.0
17.0
4.0
12.0
5.0
15.5
4.0
10.0
6.0
17.0
5.0
15.0
6.0
20.0
6.0
17.0
3.0
11.5
5.0
14.0
2.0
7.0
3.0
8.0
Fig. Units No.
ns 2-3 ns 2-3 ns 2-5
4-420
~National
U Semiconductor
54F/74F538
1-of-8 Decoder with TRI-STATE� Outputs
General Description
The 'F538 decoder/demultiplexer accepts three Address (A0 -A2) input signals and decodes them to select one of eight mutually exclusive outputs. A polarity control input (P) determines whether the outputs are active LOW or active HIGH. A HIGH Signal on either of the active LOW Output Enable (OE) inputs forces all outputs to the high impedance state. Two active HIGH and two active LOW input enables are available for easy expansion to 1-of 32 decoding with
four packages, or for data demultiplexing to 1-of-8 or 1-of16 destinations.
Features
� Output polarity control � Data demultiplexing capability � Multiple enables for expansion � TRI-STATE outputs
Ordering Code: see sections
Logic Symbols
Connection Diagrams
IEEE/I EC
Dt.IUX I>
DE1
EN
DE2
} f Ao
A1 A2
a:
E4 E3 E2 E1
0, 10 v
Oo
1,10 v o,
2, 10 v
02
3, 10 v
03
4, 10 v
04
5, 10 v
05
6, 10 v
05
7, 10 v
07
TL/F/9551-5
Ao At A2
OE2 Oo 01 02 03 04 05 05 07 TL/F/9551-1
Unit Loading/Fan Out: See Section 2 for u.L. Definitions
Pin Names
Ao-A2 E1,E2 E3,E4 p CJE1. OE2 Oo-07
Description
Address Inputs Enable Inputs (Active LOW) Enable Inputs (Active HIGH) Polarity Control Input Output Enable Inputs (Active LOW) TRI-STATE Outputs
U.L.
HIGH/LOW
1.0/1.0 1.0/1.0
54F/74F
Input l1Hll1L Output loHllOL 20 �Al - 0.6 mA 20 �Al -0.6 mA
1.0/1.0
20 �Al -0.6 mA
1.0/1.0 1.0/1.0
20 �A/ -b.6 mA 20 �A/-0.6 mA
150/40 (33.3) -3 mA/24 mA (20 mA)
Pin Assignment for DIP, SOIC and Flatpak
02
o,
Oo 3
oc, 4
DE2 5 Ao 6 A1 7 05 8
05 GND 10
20 Vee
19 03 18 04 17 A2 16 E1 15 E2 14 E3 13 E4 12 p 11 07
TL/F/9551-2
Pin Assignment for LCC
05 A, Ao OE2 OE1
[fil[l)[]][il!IJ
G~~~o~~~
01 [j]
mo2
P !ill
~Vee
E4 IJ]
l!fil 03
fi3Jli1][j]]ffZ][i]]
E3 E2 E1 A-i, 04
TL/F/9551-3
4-421
co
Cf)
i.n Truth Table
Function
High Impedance Disable
Inputs
Outputs
OE1 OE2 E1 E2 E3 E4 A2 A1 Ao Oo 01 02 03 04 05 Os 07
H x xxxxxxxz z z z z z z z x H xxxxxxxz z z z z z z z
L L Hxxxxxx L L xHxxxxx L L xxL xxxx L L xxxL xxx
Outputs Equal P Input
Active HIGH L
Output
L
(P = L)
L
L
L
L
L
L
L
L LHH L L L H L L L L L L L
L
L LHH L L H L H L L L L L L
L
L LHH L H L L L H L L L L L
L
L LHH L HH L L L H L L L L
L L LHHH L L L L L L H L L L
L L LHHH L H L L L L L H L L
L
L LHHHH L L L L L L L H L
L
L LHHHHH L L L L L L L H
Active LOW Output (P = H)
L
L
L
L
L
L
L
L
L
L
L
L
L �L
L
L
L LHH L L L L H H H H H HH L LHH L L HH L H H H H HH L LHH L H L H H L H H H H H L LHH L HHH H H L H H HH L LHHH L L H H H H L H H H L LHHH L HH H H H H L H H L LHHHH L H H H H H H L H L LHHHHHH H H H H H H L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial Z = High Impedance
Logic Diagram
E1~~~~.....---:-::-~~--,~~~1ir-~--,Mt~~-;-r1~~'Ttj-~~tt1~~-,
E2------1::J1
E3 E2
TL/F/9551-4 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-422
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�c
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to + 7.0V
Input Voltage (Note 2)
-0.5V to + 7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
-0.5VtoVee -0.5Vto +5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�cto +70�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
V1H V1L Veo VoH
VoL
l1H
lsv1
le EX V10
loo l1L lozH lozL los lzz leeH leeL leez
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee 74F5% Vee 74F5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage Test
74F
Output Leakage Circuit Current
74F
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Bus Drainage Test
Power Supply Current
Power Supply Current
Power Supply Current
54F/74F
Min Typ Max
2.0
0.8
-1.2
2.5 2.4 2.5 2.4 2.7 2.7
0.5 0.5
20.0 5.0
100 7.0
250 50
4.75
3.75
-0.6
50
-50
-60
-150
500
31
45
37
56
37
56
Units
v v v
v
v
�A
�A
�A
v
�A mA �A �A mA �A mA mA mA
Vee
Min
Min
Min Max Max Max 0.0 0.0 Max Max Max Max
o.ov
Max Max Max
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal l1N = -18 mA loH = -1 mA loH = -3mA loH = -1 mA loH = -3mA loH = -1 mA loH = -3 mA loL = 20mA loL = 20mA
V1N = 2.7V
V1N = 7.0V
VouT =Vee
110 = 1.9�A All Other Pins Grounded V100 = 150 mV All Other Pins Grounded V1N = 0.5V VouT = 2.7V VouT = 0.5V
VouT = ov
VouT = 5.25V Vo= HIGH Vo= LOW Vo= HIGHZ
4-423
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
tPLH tPHL
tPLH tPHL
tPLH tPHL
tPLH tPHL
tpzH tpzL
tpHz tpLZ
Propagation Delay An to On
Propagation Delay E1 orE2toOn
Propagation Delay E3 or E4 to On
Propagation Delay PtoOn
Output Enable Time OE1 or OE2 to On
Output Disable Time OE1 or OE2 to On
74F
TA= +25�C Vee= +s.ov
CL= 50pF
Min
Typ
Max
6.0
11.0
16.0
4.0
7.5
11.0
5.0
8.5
15.0
4.0
6.5
9.0
6.0
11.0
16.0
5.0
10.0
14.0
6.0
11.5
18.0
6.0
11.0
16.0
3.0
5.5
10.0
5.0
9.0
13.0
2.0
4.0
6.0
3.0
5.0
8.0
54F
TA, Vee= Mil CL= 50pF
Min
Max
74F
TA, Vee= Com CL= 50 pF
Min
Max
6.0
17.0
4.0
12.0
5.0
16.0
4.0
10.0
6.0
17.0
5.0
15.0
6.0
20.0
6.0
17.0
3.0
11.0
5.0
14.0
2.0
7.0
3.0
9.0
Fig. Units
No. ns 2-3 ns 2-3 ns 2-5
4-424
(J1
w
~National
CD
~Semiconductor
54F/74F539
Dual 1-of-4 Decoder with TRI-STATE� Outputs
General Description
The 'F539 contains two independent decoders. Each accepts two Address (A0, A1) input signals and decodes them to select one of four mutually exclusive outputs. A polarity control input (P) determines whether the outputs are active
HIGH (P = L) or active LOW (P = H). An active LOW
input Enable (E) is available for data demultiplexing; data is routed to the selected output in non-inverted form in the active LOW mode or in inverted form in the active HIGH mode. A HIGH signal on the active LOW Output Enable (OE) input forces the TRI-STATE outputs to the high impedance state.
Ordering Code: see sections Logic Symbols
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
DECODER a OE Oo 01 02 03
IEEE/I EC
DMUX
Pb
NIO
OEb
EN
0, 10 v
Oob
Aob A1b
0} G01 3
1,10V
2,10 v
01b 02b
Eb
3, 10 v
03b
TL/F/9552-1
Pa
Ooa
BE a
Ota
Aoa
02a
A1a
03a
Ea TL/F/9552-4
02b 1 01b 2 Oob 3
Pb 4 filb 5 Aoa 6 A1a 7 03a 8
02a GND 10
20 Vee
19 03b 18 A1b 17 Aob 16 Eb
15 Ea 14 BEa
13 Pa 12 Ooa 11 Ota
TL/F/9552-2
Pin Assignment for LCC
m 03a A1a Aoa OEi, Pb
ffil III III [[)
02a I]] GND [Q]
01a [j] Ooa~
Pa [j]
rnoob
mo1b
OJ02b ~Vee li]]03b
Ii] ~Ii]] liZI II�)
OEa Ea E:i AobAtb
TL/F/9552-3
4-425
Unit Loading/Fan Out: See Section 2 for U.L. definitions
Pin Names
Aoa-A1a Aob-A1b Ea.Eb OEa, OEb Pa.Pb Ooa-03a Oob-03b
Description
Side A Address Inputs Side B Address Inputs Enable Inputs (Active LOW) Output Enable Inputs (Active LOW) Polarity Control Inputs Side A TRI-STATE Outputs Side B TRI-STATE Outputs
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loHlloL
1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 150/40 (33.3) 150/40 (33.3)
20 �A/-0.6 mA 20 �Al - 0.6 mA 20 �A/-0.6 mA 20 �A/-0.6 mA 20 �A/-0.6 mA -3 mA/24 mA (20 mA) -3 mA/24 mA (20 mA)
Truth Table (each half)
Function
Inputs
Outputs
OE
E
A1
Ao
Oo
01
02
03
High Impedance
H
x x
x
z
z
z
z
Disable
L
H
x
x
On= P
Active HIGH Output (P = L)
L
L
L
L
H
L
L
L
L
L
L
H
L
H
L
L
L
L
H
L
L
L
H
L
L
L
H
H
L
L
L
H
Active LOW Output (P = H)
L
L
L
L
L
H
H
H
L
L
L
H
H
L
H
H
L
L
H
L
H
H
L
H
L
L
H
H
H
H
H
L
Logic Diagram (one half shown>
H = HIGH Voltage Level L = LOW Voltage Level
X = Immaterial
Z = High Impedance
TL/F/9552-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-426
Absolute Maximum Ratings (Note 1)
If MilitaryI Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 15o�c
Ambient Temperature under Bias
- 55�C to + 125�c
Junction Temperature under Bias
-55�C to+ 175�C
Vee Pin Potential to Ground Pin
-0.5Vto +7.0V
Input Voltage (Note 2)
-0.5Vto +7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
-0.5VtoVee -0.5Vto +5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Uw 1
Recommended Operating
CD
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�c o�cto +70�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
V1H V1L Veo VoH
VoL
l1H
lsv1
le Ex
V10
loo
l1L lozH lozL los lzz leeH leeL leez
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee 74F5% Vee 74F5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage Test
74F
Output Leakage Circuit Current
74F
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Bus Drainage Test
Power Supply Current
Power Supply Current
Power Supply Current
54F/74F
Min Typ Max
2.0
0.8
-1.2
2.5 2.4 2.5 2.4 2.7 2.7
0.5 0.5
20.0 5.0
100 7.0
250 50
4.75
3.75
-0.6
50
-50
-60
-150
500
28
45
40
60
40
60
Units
v v v
v
v
�A
�A
�A
v
�A mA �A �A mA �A mA mA mA
Vee
Min
Min
Min Max Max Max 0.0 0.0 Max Max Max Max
o.ov
Max Max Max
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal l1N = -18 mA loH = -1 mA loH = -3mA loH = -1 mA loH = -3mA loH = -1 mA loH = -3mA loL = 20 mA IQL = 24 mA
V1N = 2.7V
V1N = 7.0V
Vour =Vee
110 = 1.9 �A All Other Pins Grounded V100 = 150 mV All Other Pins Grounded V1N = 0.5V Vour = 2.7V Vour = 0.5V
Vour = ov
VouT = 5.25V Vo= HIGH Vo= LOW Vo= HIGHZ
4-427
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
tPLH tPHL
tPLH tPHL
tPLH tPHL
tpzH tpzL
tpHz tpLz
Propagation Delay An to On
Propagation Delay EtoOn
Propagation Delay PtoOn
Output Enable Time OE to On
Output Disable Time OE to On
74F
TA= +25�C Vee= +5.0V
CL= 50 pF
Min
Typ
Max
4.0
14.5
18.5
4.0
9.5
12.0
5.0
12.0
16.0
4.0
7.5
9.5
7.5
14.5
21.5
5.0
11.0
16.5
4.5
8.0
10.5
5.5
10.0
13.0
2.0
4.5
6.5
3.0
6.5
8.5
54F
TA, Vee= Mil CL= 50 pF
Min
Max
74F
TA, Vee= Com CL= 50 pF
Min
Max
3.5
19.5
4.0
13.0
5.5
17.0
4.0
10.5
4.5
22.5
4.5
17.5
4.0
11.5
5.0
14.0
2.0
7.0
3.0
9.5
Fig. Units
No.
ns 2-3 ns 2-3 ns 2-3 ns 2-5
4-428
~~SNemaitcoinoduncatolr
54F/74F540 � 54F/74F541 Octal Buffer/Line Driver with TRI-STATE� Outputs
General Description
The 'F540 and 'F541 are similar in function to the 'F240 and 'F244 respectively, except that the inputs and outputs are on opposite sides of the package (see Connection Diagrams). This pinout arrangement makes these devices especially useful as output ports for microprocessors, allowing ease of layout and greater PC board density.
Features
� TRI-STATE outputs drive bus lines � Inputs and outputs opposite side of package, allowing
easier interface to microprocessors
Ordering Code: see section 5 Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
'F540
TL/F/9553-1
Pin Assignment for LCC
15
[]]
15
IIl
14
[[]
m13 I1I2I
G~~:-~:~
67[j]
[I] fil1
6s[j1]
~Vee
65[j]
Ii]] fil2
!j]][j]]!illl!l]I]]] 64 63 62 61 60
TL/F/9553-2
5E1-----. ........
lo
11
12 13 14 15
'F541
TL/F/9553-4
[I]s] r1n5 r1n4 r1n3 r1n2
GNlD[7 Q] [ [ ) - l i l ll1 1l lo
07[l]
mOE1
Os[j]
~Vee
05[j]
Ii]] fil2
!j]][ill!illl!l]li]] 04 03 02 01 Oo
TL/F/9553-5
Unit Loading/Fan Out: See Section 2 for U.L. Definitions
Pin Names
OE1, OE2 In On.On
Description
TRI-STATE Output Enable Input (Active LOW) Inputs Outputs
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loHlloL
1.0/1.0 1.0/1.0 600/106.6 (80)
20 �A/ - 0.6 mA 20 �A/-0.6 mA -12 mA/64 mA (48 mA)
4-429
Truth Table
Inputs
OE1
OE2
I
L
L
H
H
x x
x
H
x
L
L
L
H = HIGH Voltage Level
L = LOW Voltage Level X = Immaterial Z = High Impedance
Logic Diagrams
Outputs
'F540
'F541
L
H
z
z
z
z
H
L
I E E E / I EC 'F540
TL/F/9553-3
I E E E / I EC 'F541
OE1 OE2
lo 11 12 13 14 15 Is 17
Oo 01 02 03 04 05 Os 07
TL/F/9553-6
4-430
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
-55�C to + 175�C
Vcc Pin Potential to Ground Pin
-0.5V to+ 7.0V
Input Voltage (Note 2)
-0.5V to + 7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
-0.5VtoVce -0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
U1
A
Recommended Operating Conditions
Free Air Ambient Temperature
0
� .UA..1.
Military Commercial
- 55�C to + 125�c
o�cto +1o�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
V1H V1L Vco VoH
VoL l1H lsv1 leEx V10 loo l1L lozH lozL los lzz
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee 74F5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage 74F
Test
Output Leakage
74F
Circuit Current
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Bus Drainage Test
54F/74F
Min Typ Max 2.0
0.8 -1.2
2.4 2.0 2.4 2.0 2.7
0.55 0.55
20.0 5.0 100 7.0
250 50
4.75
-100
3.75
-0.6 50 -50
-225 500
Units
v v v
v
v
�A
�A
�A
v
�A mA �A �A mA �A
Vee
Min
Min
Min Max Max Max 0.0 0.0 Max Max Max Max
o.ov
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal l1N = -18 mA loH = -3 mA loH = -12mA loH = -3 mA loH = -15mA loH = -3 mA loL = 48mA loL = 64mA
V1N = 2.7V
V1N = 7.0V
VouT =Vee
110 = 1.9 �A All Other Pins Grounded V100 = 150 mV All Other Pins Grounded V1N = 0.5V VouT = 2.7V VouT = 0.5V
VouT = ov
VouT = 5.25V
4-431
,....
'11::1"
�Ln DC Electrical Characteristics (Continued)
0
'11::1"
Ln
Symbol
Parameter
54F/74F
Units
Vee
Min
Typ
Max
Conditions
lccH
Power Supply Current ('F540)
11
20
mA
Max
Vo= HIGH
lccL
Power Supply Current ('F540)
53
75
mA
Max
Vo= LOW
lccz
Power Supply Current ('F540)
31
45
mA
Max
Vo= HIGHZ
lccH
Power Supply Current ('F541)
26
35
mA
Max
Vo= HIGH
lccL
Power Supply Current ('F541)
55
75
mA
Max
Vo= LOW
lccz
Power Supply Current ('F541)
31
55
mA
Max
Vo= HIGHZ
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
tPLH tPHL
tpzH tpzL
tpHz tpLz
tPLH tPHL
tpzH tpzL
tpHz tpLz
Propagation Delay Data to Output ('F540) Output Enable Time ('F540)
Output Disable Time ('F540)
Propagation Delay Data to Output ('F541) Output Enable Time ('F541)
Output Disable Time ('F541)
74F
TA= +25�C Vee= +5.0V
CL= 50 pF
Min
Typ
Max
1.5
3.0
5.0
1.0
2.0
4.0
2.5
4.9
8.0
3.5
5.8
10.0
1.5
3.4
6.0
1.0
2.5
5.5
1.5
3.3
5.5
1.5
2.7
5.5
3.0
5.8
8.0
3.5
6.1
8.5
1.5
3.4
6.0
1.5
2.9
5.5
54F
74F
TA, Vee= Mil CL= SOpF
TA, Vee= Com CL= 50 pF
Min
Max. Min
Max
1.0
6.0
1.0
5.5
1.0
4.5
1.0
4.0
2.5
9.0
2.5
8.5
3.5
11.0
3.5
10.5
1.5
7.0
1.5
6.5
1.0
7.5
1.0
6.0
1.5
6.0
1.5
6.0
2.5
9.5
3.0
9.5
1.5
6.5
1.5
6.0
Units Fig. No.
ns 2-3 ns 2-5 ns 2-3 ns 2-5
4-432
U~NaStemiicoonnduactlor
54F/74F543
Octal Registered Transceiver
General Description
The 'F543 octal transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate Latch Enable and Output Enable inputs are provided for each register to permit independent control of inputting and outputting in either direction of data flow. The A outputs are guaranteed to sink 24 mA (20 mA Mil) while the B outputs are rated for 64 mA (48 mA Mil).
Features
� 8-bit octal transceiver � Back-to-back registers for storage � Separate controls for data flow in each direction � A outputs sink 24 mA (20 mA Mil) � B outputs sink 64 mA (48 mA Mil) � 300 mil slim package
Ordering Code: see sections Logic Symbols
Ao ��������� A7
OEAB OEBA CEAB CEBA LEAB LEBA
Bo ......... B7
TL/F/9554-1
I E E E / I EC
CEAB
2:1
LEAB
EN1
OEAB
CEBA
LEBA
OEBA
Ao+-+ V'1 A1+-+ A2+-+ A3+-+ A4+-+ A5+-+ As+-+ A1+-+
Bo B1 B2 B3 B4 Bs B5 B1 TL/F/9554-5
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
LEBA OEBA 2
Ao A1 4 Az 5 A3 A4 As 8 A5 A1 10 CEAB 11 GND 12
24 Vee
23 CEBA
22 Bo 21 B1 20 B2 19 B3 18 B4 17 Bs 16 B5 15 B1 14 LEAB
13 OEAB
Pin Assignment forLCC
A5 As A4 NC A3 A2 A1 [j][QJIIJ[fil[[J[I][[J
A1 [g] CEAB [j]] GND fl]
NC~
OEAB !ill LEAB IIZi
B1 [�]
0Ao [I] OEBA
1IJ LEBA
[I]NC
~Vee Ill] CEBA ~Bo
IJ]~~lll@I~~ 85 85 84 NC 83 82 B1
TL/F/9554-3
TL/F/9554-2
4-433
Unit Loading/Fan Out: See Section 2 for U.L. definitions
54F/74F
Pin Names
Description
U.L. HIGH/LOW
Input l1Hll1L Output loHlloL
OEAB OEBA CEAB CESA LEAB LESA Ao-A7
Bo-87
A-to-8 Output Enable Input (Active LOW) 8-to-A Output Enable Input (Active LOW) A-to-8 Enable Input (Active LOW) B-to-A Enable Input (Active LOW) A-to-8 Latch Enable Input (Active LOW) 8-to-A Latch Enable Input (Active LOW) A-to-B Data Inputs or 8-to-A TRI-STATE� Outputs 8-to-A Data Inputs or A-to-8 TRI-STATE Outputs
1.0/1.0 1.0/1.0 1.0/2.0 1.0/2.0 1.0/1.0 1.0/1.0 3.5/1.083 150/40 (33.8) 3.5/1.083 600/106.6 (80)
20 �A/-0.6 mA 20 �A/-0.6 mA 20 �A/ -1.2 mA 20 �A/-1.2 mA 20 �A/ - 0.6 mA 20 �A/ - 0.6 mA 70 �A/ - 650 �A -3 mA/24 mA (20 mA) 70 �A/ - 650 �A -12 mA/64 mA (48 mA)
Functional Description
The 'F543 contains two sets of eight D-type latches, with separate input and output controls for each set. For data flow from A to B, for example, the A-to-8 Enable (CEAB) input must be LOW in order to enter data from Ao-A7 or take data from 80 -87, as indicated in the Data 1/0 Control Table. With CEAB LOW, a LOW signal on the A-to-8 Latch Enable (LEAB) input makes the A-to-8 latches transparent; a subsequent LOW-to-HIGH transition of the LEAB signal puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB and OEAB both LOW, the TRI-STATE B output buffers are active and reflect the data present at the output of the A latches. Control of data flow from B to A is similar, but using the CESA, LESA and OEBA inputs.
Data 1/0 Control Table
CEAB
H
x
L
x
L
Inputs
LEAB
x
H
L
x x
OEAB
x x x
H L
Latch Status
Latched Latched Transparent
-
-
Output Buffers
HighZ
-
HighZ Driving
H = HIGH Voltage Level L = LOW Voltage Level
X = Immaterial
A-to-S data flow shown; S-to-A flow control is the same, except using CESA, LESA and OEBA
4-434
Logic Diagram
A1
81
A2
82
A3
83
A4
DETAIL Ax7
84
As
85
A5
85
A1
87
OEBA
OEAB
CEBA
CEAB
LEBA
LEAB
TL/F/9554-4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-435
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambiesnt Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5Vto +7.0V
Input Voltage (Note 2)
-0.5V to+ 7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
-0.5Vto Vee -0.5Vto +5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol V1H V1L Veo VoH
Vol
l1H lsv1 lsv1T
le Ex
V10 loo
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee 74F 10% Vee 74F5% Vee 74F5% Vee 74F5% Vee
Output LOW Voltage
54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Input HIGH Current 54F
Breakdown (1/0)
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage 74F
Test
Output Leakage 74F
Circuit Current
54F/74F Min Typ Max 2.0
0.8 -1.2 2.5 2.4 2.0 2.5 2.4 2.0 2.7 2.7 2.0 0.5 0.55 0.5 0.55 20.0 5.0 100 7.0
1.0 0.5 250 50
4.75
3.75
Units
v v v
v
v
�A �A mA �A
v
�A
Vee
Min
Min
Min Max Max Max Max 0.0 0.0
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal l1N = -18 mA loH = -1 mA (An) loH = - 3 mA (An (Bn) loH = -12 mA (Bn) loH = -1 mA (An) loH = -3 mA (An, Bn) loH = -12 mA (Bn) loH = -1 mA (An) loH = - 3 mA (An, Bn) loH = -15 mA (Bn) loL = 20 mA (An) loL = 48 mA (Bn) loL = 24 mA (An) loL = 64 mA (Bn)
V1N = 2.7V
V1N = 7.0V (OEAB, OEBA, LEAB, LEBA, CEAB, CEBA)
V1N = 5.5V (An, Bn)
VouT =Vee
110 = 1.9 �A All Other Pins Grounded V100 = 150 mV All Other Pins Grounded
4-436
DC Electrical Characteristics (Continued)
Symbol
Parameter
l1L
Input LOW Current
l1H + loZH l1L + lozL los
Output Leakage Current Output Leakage Current Output Short-Circuit Current
lzz lccH lccL lccz
Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current
54F/74F
Min Typ Max
-0.6 -1.2
70
-650
-60 -100
-150 -225
500
67. 100
83
125
83
125
Units
mA �A �A mA �A mA mA mA
Vee
Max Max Max Max
o.ov
Max Max Max
Conditions
V1N = 0.5V (OEAB, OEBA) V1N = 0.5V (CEAB, CEBA) Your = 2.7V (An, Bn) Your = 0.5V (An. Bn) Your = OV (An)
Your= av (Bn)
Your= 5.25V (An, Bn) Vo= HIGH Vo= LOW Vo= HIGHZ
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
tpLH tpHL
tpLH tpHL tPLH tpHL
IPZH tpzL
tpHz tpLz
Propagation Delay Transparent Mode An to Bn or Bn to An
Propagation Delay LESA to An
Propagation Delay LEAB to Bn
Output Enable Time OEBA or OEAB to An or Bn CESA or CEAB to An or Bn
Output Disable Time OEBA or OEAB to An or Bn CESA or CEAB to An or Bn
74F
TA= +25�C Vee= +5.0V
CL= 50pF
Min
Typ
Max
3.0
5.5
7.5
3.0
5.0
6.5
4.5
8.5
11.0
4.5
8.5
11.0
4.5
8.5
11.0
4.5
8.5
11.0
3.0
7.0
9.0
4.0
7.5
10.5
1.0
6.0
8.0
2.5
5.5
10.5
54F
TA, Vee= Mil CL= 50 pF
Min
Max
74F
TA, Vee= Com CL= 50 pF
Fig. Units
No.
Min
Max
3.0
8.5
ns 2-3
3.0
7.5
4.5
12.5
ns 2-3
4.5
12.5
4.5
12.5
ns 2-3
4.5
12.5
3.0
10.0
4.0
12.0
ns 2-5
1.0
9.0
2.5
11.5
AC Operating Requirements: See Section 2 for Waveforms
Symbol
Parameter
t5 (H) t5 (L)
th(H) th(L)
tw(L)
Setup Time, HIGH or LOW An or Bn to LEBA or LEAB
Hold Time, HIGH or LOW An or Bn to LESA or LEAB
Latch Enable, B to A Pulse Width, LOW
74F
TA= +25�C Vee= +5.0V
Min
Max
3.0 3.0
3.0 3.0
8.0
54F
TA, Vee= Mil
Min
Max
74F
TA, Vee= Com
Min
Max
3.5 3.5
3.5 3.5
9.0
Units Fig. No.
ns
2-6
ns
2-4
4-437
U~NaStemiicoonnduactlor
54F/74F544
Octal Registered Transceiver
General Description
The 'F544 octal transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate Latch Enable and Output Enable inputs are provided for each register to permit independent control of inputting and outputting in either direction of data flow. The A outputs are guaranteed to sink 24 mA (20 mA Mil) while the B outputs are rated for 64 mA (48 mA Mil). The 'F544 inverts data in both directions.
Features
� 8-bit octal transceiver � Back-to-back registers for storage � Separate controls for data flow in each direction � A outputs sink 24 mA (20 mA Mil), B outputs sink
64 mA (48 mA Mil)
� 300 mil slim PDIP
Ordering Code: see section 5 Logic Symbols
Connection Diagrams
Ao�������� .A7
OEAB OEBA CEAB CEBA LEAB LEBA
Bo ��������� B7
TL/F/9555-2
I E E E / I EC
CEAB LEAB OEAB CEBA LEBA OEBA
Ao
Bo
A1
ii,
A2
B2
A3
B3
A_.
ii_.
As
ii 5
As
Bs
A1
e.,
TL/F /9555-1
Pin Assignment for DIP, SOIC and Flatpak
LEBA OEBA
Ao A1 4 A2 A3
A" As 8 As 9 A1 10 CEAB 11 GND 12
24 Vee
23 CEBA
22 Bo 21 81 20 82 19 83 18 84 17 Eis 16 iis 15 81 14 LEAB
13 OEAB
Pin Assignment forLCC
As As A4 NC A3 A2 A1 (j][QJl]][fil[Z][�][fil
A1 Ii] CEAB Ii]! GND~
NC [ID OEAB [j]] LEAB Ii]
B1 [�]
[i]Ao
1IJ OEBA ill LEBA
[I] NC
@J Vee
IW CEBA
~Bo
IJ]J~12:11!lllgH~~ Bs Bs B4 NC B3 B2 B1
TL/F/9555-4
TL/F/9555-3
4-438
Unit Loading/Fan Out: See Section 2 for U.L. definitions
54F/74F
Pin Names
Description
U.L. HIGH/LOW
Input l1H/l1L Output loH/loL
OEAB OEBA CEAB CEBA LEAB LEBA
A0 -P.q
80-81
A-to-B Output Enable Input (Active LOW) 1.0/1.0
20 �A/-0.6 mA
B-to-A Output Enable Input (Active LOW) 1.0/1.0
20 �A/ - 0.6 mA
A-to-B Enable Input (Active LOW)
1.0/2.0
20 �A/-1.2 mA
8-to-A Enable Input (Active LOW)
1.0/2.0
20 �A/-1.2 mA
A-to-8 Latch Enable Input (Active LOW)
1.0/1.0
20 �Al - 0.6 mA
B-to-A Latch Enable Input (Active LOW)
1.011.0
20 �A/ - 0.6 mA
A-to-B Data Inputs or
3.5/1.083
70 �A/ - 650 �A
8-to-A TRI-STATE Outputs
150/40(33.3) - 3 mA/24 mA (20 mA)
B-to-A Data Inputs or
3.5/1.083
70 �A/ - 650 �A
A-to-8 TRI-STATE Outputs
600/ 106.6(80) -12 mA/64 mA (48 mA)
Functional Description
The 'F544 contains two sets of eight D-type latches, with separate input and output controls for each set. For data flow from A to B, for example, the A-to-B Enable (CEAB)
input must be LOW in order to enter data from A0-A7 or take data from 80-87, as indicated in the Data 1/0 Control
Table. With CEAB LOW, a LOW signal on the A-to-B Latch Enable (LEAB) input makes the A-to-B latches transparent; a subsequent LOW-to-HIGH transition of the LEAB signal puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB and OEAB both LOW, the TRI-STATE� B output buffers are active and reflect the data present at the output of the A latches. Control of data flow from B to A is similar, but using the CEBA, LEBA and OEBA inputs.
Data 1/0 Control Table
CEAB
H
x
L
x
L
Inputs
LEAB
x
H L
x x
OEAB
x x x
H L
Latch Status
Latched Latched Transparent
-
Output Buffers
HighZ
-
HighZ Driving
H = HIGH Voltage Level
L = LOW Voltage Level X = Immaterial
A-to-8 data flow shown; 8-to-A flow control is the same,
except using CESA, LESA and OEIDi
4-439
Logic Diagram
�': ---------------D-ET-A-IL-A---- Bo
I I I I
A1
B1
A2
B2
A3
B3
A4
DETAIL Ax7
B4
As
Bs
As
Bs
A1
B1
OEBA
OEAB
CEBA
CEAB LEBA
LEAB
TL/F/9555-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-440
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to + 7.0V
Input Voltage (Note 2)
-0.5Vto +7.0V
Input Current (Note 2)
-30 mA to + 5.0 mA
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
Current Applied to Output in LOW State (Max)
-0.5VtoVee - 0.5V to + 5.5V
twice the rated loL (mA)
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
V1H
Input HIGH Voltage
V1L
input LOW Voltage
54F/74F Min Typ Max 2.0
0.8
Units Vee
Conditions
v
Recognized as a HIGH Signal
v
Recognized as a LOW Signal
Veo
Input Clamp Diode Voltage
-1.2
v
Min l1N = -18mA,
(except An, Bn)
VoH
Output HIGH
54F 10% Vee 2.5
Voltage
54F 10% Vee 2.4
54F 10% Vee 2.0
74F 10% Vee 2.5
74F 10% Vee 2.4
74F 10% Vee 2.0
74F5% Vee
2.7
74F5% Vee
2.7
loH = -1 mA (An)
loH = -3 mA (An. Bn)
loH = -12 mA (Bn)
v
Min loH = -1 mA (An)
loH = - 3 mA (An. Bn)
loH = -15 mA (Bn)
loH = -1 mA (An)
loH = -3 mA (An, Bn)
Vm
Output LOW
54F 10% Vee
Voltage
54F 10% Vee
74F 10% Vee
74F 10% Vee
0.5
loL = 20 mA (An)
0.55
v
Min loL = 48 mA (Bn)
0.5
Im = 24 mA (An)
0.55
loL = 64 mA (Bn)
l1H
Input HIGH
54F
Current
74F
20.0
V1N = 2.7V (except An. Bn)
�A Max
5.0
lsv1
Input HIGH Current 54F
Breakdown Test
74F
100 7.0
�A
Max V1N = 7.0V (except An, Bn)
lsv1r
Input HIGH Current 54F
Breakdown (110)
74F
1.0
mA
Max V1N = 5.5V (An. Bn)
0.5
leEX
Output HIGH
54F
Leakage Current
74F
250 250
�A
Max Vour =Vee (An. Bn)
V10
Input Leakage 74F
4.75
Test
v
0.0 110 = 1.9 �A
All Other Pins Grounded
loo
Output Leakage
Circuit Current
74F
3.75
�A
0.0
V100 = 150 mV All Other Pins Grounded
l1L
Input LOW Current
-0.6
V1N = 0.5V (OEAB, OEBA)
-1.2
mA
Max V1N = 0.5V (CEAB, CEBA)
l1H + lozH
l1L + lozL
Output Leakage Current Output Leakage Current
70
�A Max Vour = 2.7V (An. Bn)
-650 �A Max Vour = 0.5V (An. Bn)
4-441
"1:1" 'Ol::t'
Lt) DC Electrical Characteristics (Continued)
Symbol
Parameter
los
Output Short-Circuit Current
lzz lccH lccL lccz
Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current
Min
-60 -100
54F/74F Typ
70 85 83
Max -150 -225 500 105 130 125
Units
mA �A mA mA mA
Vee
Max
o.ov
Max Max Max
Conditions
VouT = OV (An) VouT = OV (Bn) Vour = 5.25V (An. Bn)
Vo= HIGH Vo= LOW Vo= HIGHZ
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
tPLH
Propagation Delay
tpHL
Transparent Mode
An to Bn or Bn to An
tPLH
Propagation Delay
tPHL
LEBA to An
tPLH
Propagation Delay
tPHL
LEAB to Bn
tpzH
Output Enable Time
tpzL
OEBA or OEAB to An or Bn
CEBA or CEAB to An or Bn
tpHz
Output Disable Time
tpLZ
OEBA or OEAB to An or Bn
CEBA or CEAB to An or Bn
74F
TA= +2s0 c Vee= +s.ov
CL= 50pF
Min
Typ
Max
3.0
7.0
9.5
3.0
5.0
6.5
6.0
10.0
13.0
4.0
7.0
9.5
6.0
10.0
13.0
4.0
7.0
9.5
3.0
7.0
9.0
4.0
7.5
10.5
1.0
6.0
8.0
2.5
5.5
10.5
54F
TA, Vee= Mil CL= 50 pF
Min
Max
3.0
12.0
2.5
8.5
74F
TA, Vee= Com CL= 50pF
Min
Max
3.0
10.5
3.0
7.5
6.0
18.0
6.0
14.5
4.0
11.5
4.0
10.5
6.0
18.0
6.0
14.5
4.0
11.5
4.0
10.5
3.0
11.0
3.0
10.0
4.0
13.0
4.0
12.0
2.0
10.0
1.0
9.0
2.0
9.5
2.5
11.5
Fig Units No
ns 2-3 ns 2-3 ns 2-3
ns 2-5
AC Operating Requirements: See Section 2 tor Waveforms
Symbol
Parameter
t5 (H) t5 (L)
th(H) th(L)
tw(L)
Setup Time, HIGH or LOW
An or Bn to LEBA or LEAB
Hold Time, HIGH or LOW
An or Bn to LEBA or LEAB
Latch Enable, B to A Pulse Width, LOW
74F
TA= +2s0 c
Vee= +5.0V
Min
Max
3.0 3.0
3.0 3.0
6.0
54F
TA, Vee= Mil
Min
Max
3.0 3.0
3.0 3.0
9.0
74F
TA, Vee= Com
Min
Max
3.0 3.0
3.0 3.0
7.5
Fig Units No
ns
2-6
ns
2-4
4-442
~National
~Semiconductor
54F/74F545 Octal Bidirectional Transceiver with TRI-STATE� Outputs
General Description
The 'F545 is an 8-bit, TRI-STATE, high-speed transceiver. It provides bidirectional drive for bus-oriented microprocessor and digital communications systems. Straight through bidirectional transceivers are featured, with 24 mA (20 mA Mil) bus drive capability on the A ports and 64 mA (48 mA Mil) bus drive capability on the B ports.
One input, Transmit/Receive (T/R) determines the direction of logic signals through the bidirectional transceiver. Transmit enables data from A ports to B ports; Receive enables data from B ports to A ports. The Output Enable input disables both A and B ports by placing them in a TRI-STATE condition.
Features
� Higher drive than 8304 � 8-bit bidirectional data flow reduces system package
count
a TRI-STATE inputs/outputs for interfacing with bus-ori-
ented systems
� 24 mA (20 mA Mil) and 64 mA (48 mA Mil) bus drive capability on A and B ports, respectively
� Transmit/Receive and Output Enable simplify control logic
� Guaranteed 4000V minimum ESD protection
m Pin for Pin compatible with Intel 8286
Ordering Code: See section 5
Logic Symbols
Connection Diagrams
OE
T/R
IEEE/IEC
TL/F/9556-3
Pin Assignment for DIP, SOIC and Flatpak
Ao 1 Al 2 A2 3 A3 4 A4 As As 7 A1
5E
GNO 10
20 Vee 19 Bo 18 81 17 82 16 83 15 84 14 85 13 Bs 12 87
11 T/R
Pin Assignment forLCC
A1 [[J
rAns mAs
rAn4 rAn3
G~:o~~~
T/R ID]
DJ Ao
B7 l!ll
~Vee
Bs Ii]
[21Bo
18J!illi]]l!1Jl!m
85 84 83 82 81
TL/F/9556-2
Tl/F/9556-1
Truth Table
Inputs OE T/R
Outputs
L
L Bus B Data to Bus A
TL/F/9556-5
L
H Bus A Data to Bus B
H
x HighZ
Unit Loading/Fan Out: See Section 2 tor U.L. Definitions
H = HIGH Voltage Level
L = LOW Voltage Level X = Immaterial Z = High Impedance
Pin Names
Description
U.L. HIGH/LOW
54F/74F
Input l1Hll1L Output loHlloL
OE T/R Ao-A7
Bo-B7
Output Enable Input (Active LOW) Transmit/Receive Input Side A TRI-STATE Inputs or TRI-STATE Outputs Side B TRI-STATE Inputs or TRI-STATE Outputs
1.0/2.0 1.0/2.0 3.5/1.083 150/40 (33.3) 3.5/1.083 600/106.6 (80)
20 �A/-1.2 mA 20 �A/-1.2 mA 70 �A/ - 650 �A -3 mA/24 mA (20 mA) 70 �A/ - 650 �A -12 mA/64 mA (48 mA)
4-443
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�c
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to + 7.0V
Input Voltage (Note 2)
-0.5V to + 7.0V
Input Current (Note 2)
-30 mA to + 5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
-0.5VtoVee -0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
ESD Last Passing Voltage (Min)
4000V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +70�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
V1H V1L Veo VoH
Vol
l1H lsv1 lsv1T leEX V10 loo l1L l1H + lozH l1L + lozL los
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee 74F 10% Vee 74F5% Vee 74F5% Vee
Output LOW Voltage
54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Input HIGH Current 54F
Breakdown (1/0)
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage Test
74F
Output Leakage Circuit Current
74F
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
54F/74F
Min Typ Max
2.0
0.8
-1.2
2.5 2.4 2.0 2.5 2.4 2.0 2.7 2.7
0.5 0.55 0.5 0.55
20.0 5.0
100 7.0
1.0 0.5
250 50
4.75
-60 -100
4-444
3.75
-1.2 70
-650 -150 -225
Units
v v v
v
v
�A �A mA �A
v
�A mA �A �A mA
Vee
Min
Min
Min Max Max Max Max 0.0 0.0 Max Max Max Max
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal l1N = -18 mA (OE, T/R) loH = -1 mA (An) loH = -3 mA (An) loH = -12 mA (Bn) loH = -1 mA (An) loH = -3 mA (An) loH = -15 mA (Bn) loH = -1 mA (An) loH = -3 mA (An) loL = 20 mA (An) loL = 48 mA (Bn) Im = 24 mA (An) loL = 64 mA (Bn) V1N = 2.7V (OE, T/R)
V1N = 7.0V (OE, T/R)
V1N = 5.5V (An, Bn)
VouT =Vee
110 = 1.9 �A All Other Pins Grounded V100 = 150 mV All Other Pins Grounded V1N = 0.5V (OE, T/R) VouT = 2.7V (An. Bn) VouT = 0.5V (An, Bn) VouT = OV (An) VouT = OV (Bn)
U1
.i::a.
DC Electrical Characteristics (Continued)
U1
Symbol
lzz iccH lccL lccz
Parameter
Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current
54F/74F
Min
Typ
Max
5aa
7a
9a
95
12a
85
11a
Units
�A mA mA mA
Vee
a.av Max Max Max
Conditions
VouT = 5.25V Vo= HIGH Vo= LOW Vo= HIGHZ
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
tPLH tPHL
tpzH tpzL
tpHz tpLz
Propagation Delay An to Bn or Bn to An Output Enable Time
Output Disable Time
74F
TA= +25�C Vee= +5.0V
CL= 50 pf
Min
Typ
Max
2.5
4.2
6.a
2.5
4.6
6.a
3.a
5.3
7.a
3.5
6.a
8.a
3.a
5.a
6.5
2.a
5.a
6.5
54F
TA, Vee= Mil CL= 50 pf
Min
Max
2.a
7.5
2.a
7.5
2.5
9.a
3.a
1a.a
2.5
9.a
2.a
1a.a
74F
TA, Vee= Com CL= 50 pf
Min
Max
2.5
7.a
2.5
7.a
3.a
8.a
3.5
9.a
3.a
7.5
2.a
7.5
Logic Diagram
AO
A1
A2
A3
A4
AS
A6
Fig. Units
No. ns 2-3 ns 2-5
A7
BO
81
82
83
84
85
86
87
TL/F/9556-4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-445
~~SNemaitcoinoduncatolr
54F/74F547
Octal Decoder/Demultiplexer with Address Latches and Acknowledge
General Description
The 'F547 is a 3-to-8 line address decoder with latches for address storage. Designed primarily to simplify multiple chip selection in a microprocessor system, it contains one active LOW and two active HIGH Enables to conserve address space. Also included is an active LOW Acknowledge output that responds to either a Read or Write input signal when the Enables are active.
Features
� 3-to-8 line address decoder � Address storage latches � Multiple enables for address extension � Open collector acknowledge output
Ordering Code: see section 5 Logic Symbols
LE
Ao A1 A2
E1
E2 ACK
E3
RD
WR
I E E E / I EC
TL/F/9557-1
DMUX LE EN10
}OG~ Ao
A1
A2
LE
E1
&
ENS
E2
E3
0,8 Oo
1,8 o,
2,8 02 3,8 03 4,8 04 5,8 05 S,8 05 7,8 07
RD
8,9 ~
ACK
&
EN9
WR
TL/F/9557-4
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
02 1 01 2 ACK
WR 4 R5 5
Ao
A1
05
Os 9
GND 10
20 Yee
19 03 18 04 17 A2 16 LE
15 E1 14 E2 13 E3
12 Oo
11 07
Pin Assignment
for LCC
o5
!ID
mA1 rAno
RB
rn
WR
rn
Os[[]
GND [QI
07 [j]
60 li1I
E3 il]
[I]ACK
mo1
[I] 02
~Yee
[fil 03
!j]][j]]~[Z]~
E2 E1 LE ~ 04
TL/F/9557-3
TL/F/9557-2
4-446
Unit Loading/Fan Out: See Section 2 for u.L. definitions
Pin Names
Description
54F/74F
U.L.
Input l1Hll1L
HIGH/LOW Output loHlloL
Ao-A2
E1
E2,E3 LE RD WR ACK
Oo-07
Address Select Inputs Chip Enable Input (Active LOW) Chip Enable Inputs Latch Enable Input Read Acknowledge Input (Active LOW) Write Acknowledge Input (Active LOW) Open Collector Acknowledge Output (Active LOW) Decoded Outputs (Active LOW)
1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 *OC/33.3 50/33.3
20 �A/ - 0.6 mA 20 �A/ - 0.6 mA 20 �A/ - 0.6 mA 20 �A/ - 0.6 mA 20 �A/ - 0.6 mA 20 �A/ - 0.6 mA
*OC/20 mA -1 mA/20 mA
�oc = Open Collector
Functional Description
When enabled, the 'F547 accepts the A0 -A2 Address inputs and decodes them to select one of eight active LOW, mutually exclusive outputs, as shown in the Decoder Truth Table. With LE HIGH, the Address latches are transparent and the output selection changes each time the A0-A2 address changes. When LE is LOW, the latches store the last valid address preceding the HIGH-to-LOW transition of the LE input signal. For applications in which the separation of latch enable and chip enable functions is not required, LE
and E1 can be tied together, such that when HIGH the out-
puts are OFF and the latches are transparent, and when LOW the latches are storing and the selected output is enabled.
The open collector Acknowledge (ACK) output is normally
HIGH (i.e., OFF) and goes LOW when E1, E2 and E3 are all
active and either the Read (RD) or Write (WR) input is LOW, as indicated in the Acknowledge Truth Table.
Acknowledge Truth Table
Inputs
Output
E1
E2
E3
RD
WR
ACK
Hxx x x
H
x
L
x
x
x
H
xxL x x
H
L
H
H
H
H
H
L
H
H
L
x
L
L
H
H
x
L
L
H = HIGH Voltage Level L = LOW Voltage Level
X = Immaterial Latch Status Table
Input LE
H L
Latch Status
Transparent Storing
Output Status Table
Inputs
E1
E2
E3
L
H
H
H
x
x
x
L
x
x
x
L
Decoder Outputs
On= LOWt Oo-07 =HIGH Oo-07 =HIGH Oo-07 =HIGH
tSee Decoder Truth Table
Decoder Truth Table*
Inputs
Outputs
A2
A1
Ao
Oo
01
02
03
04
05
Os
07
L
L
L
L
H
H
H
H
H
H
H
L
L
H
H
L
H
H
H
H
H
H
L
H
L
H
H
L
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
L
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
*Assuming E1, LOW; E2 and E3, HIGH
4-447
" ~
U') Logic Diagram
LE
E1 E2 E3
Ao
E Q
A1
E
D
Q
Q
A2
E Q
TL/F/9557-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-448
Absolute Maximum Ratings (Note 1)
If MilitaryI Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�c
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vcc Pin Potential to Ground Pin
-0.5V to+ 7.0V
Input Voltage (Note 2)
-0.5V to + 7.0V
Input Current (Note 2)
-30 mA to + 5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5VtoVcc - 0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�cto +70�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
V1H
Input HIGH Voltage
V1L
Input LOW Voltage
Vco
Input Clamp Diode Voltage
54F/74F Min Typ Max
Units Vee
Conditions
2.0
v
Recognized as a HIGH Signal
0.8
v
Recognized as a LOW Signal
-1.2
v
Min l1N = -18mA
VoH
Output HIGH
Voltage
54F 10% Vee 2.5 74F 10% Vee 2.5 74F 5% Vee 2.7
loH = -1 mA (On)
v
Min loH = -1 mA (On)
loH = -1 mA (On)
VoL
Output LOW
Voltage
54F 10% Vee 74F 10% Vee
0.5
v
loL = 20 mA (ACK, On) Min
0.5
loL = 20 mA (ACK, On)
l1H
Input HIGH
54F
Current
74F
20.0
�A
Max V1N = 2.7V
5.0
lsv1
Input HIGH Current 54F
Breakdown Test
74F
100 7.0
�A
Max V1N = 7.0V
lcEX
Output HIGH
54F
Leakage Current
74F
250
�A
Max VouT =Vee (On)
50
V10
Input Leakage
74F
4.75
Test
v
0.0 110 = 1.9�A
All Other Pins Grounded
loo
Output Leakage 74F
Circuit Current
V100 = 150 mV
3.75
�A
0.0
All Other Pins Grounded
l1L
Input LOW Current
los
Output Short-Circuit Current
-0.6
mA
Max V1N = 0.5V
-60
-150 mA Max VouT =av (On)
loHC
Open Collector, Output OFF Leakage Test
250
�A
Min VouT =Vee (ACK)
Ice
Power Supply Current
17
30
mA Max
4-449
......
"11:1"
Lt) AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
tPLH
Propagation Delay
tPHL
An to On
tPLH
Propagation Delay
tPHL
E1 to On
tPLH
Propagation Delay
tPHL
LE to On
tPLH
Propagation Delay
tPHL
E2 or E3 to On
tPLH
Propagation Delay
tPHL
E1. RD or WR to ACK
tPLH
Propagation Delay
tPHL
E2 or E3 to ACK
74F
TA= +25�C Vee= +5.0V
CL= 50 pf
Min
Typ
Max
2.0
7.0
9.0
4.5
9.0
12.0
2.5
6.5
8.5
3.0
6.5
8.5
3.5
7.5
10.0
5.0
14.5
14.0
4.0
8.5
10.0
4.0
8.5
10.0
6.5
11.0
13.0
3.5
7.5
9.5
7.5
13.0
14.0
4.5
8.5
12.0
54F
TA, Vee= Mil CL= 50pF
Min
Max
3.0
10.5
5.0
13.5
3.0
10.0
3.5
10.0
4.0
11.5
5.0
20.0
4.5
12.5
4.5
12.5
6.5
16.0
3.5
11.0
8.0
18.5
5.0
12.5
74F
TA, Vee= Com CL= 50 pf
Min
Max
1.5
10.0
4.0
13.0
2.0
9.5
3.0
9.5
3.0
11.0
5.0
15.0
3.0
11.0
4.0
11.0
6.5
14.0
3.0
10.5
7.0
15.0
4.0
11.0
Units Fig. No.
ns
2-3
ns
2-3
ns
2-3
ns
2-3
ns
2-3
ns
2-3
AC Operating Requirements: See Section 2 for Waveforms
Symbol
Parameter
t 5(H) t 5(L)
th(H) th(L)
tw(H)
Setup Time, HIGH or LOW An to LE
Hold Time, HIGH or LOW An to LE
LE Pulse Width, HIGH
74F
TA= +25�C Vee= +5.0V
Min
Max
5.0 5.0
6.0 6.0
6.0
54F
TA, Vee= Mil
Min
Max
5.0 5.0
6.0 6.0
6.0
74F
TA, Vee= Com
Min
Max
5.0 5.0
6.0 6.0
6.0
Fig. Units No.
ns
2-6
ns
2-4
4-450
a~National Semiconductor
54F/74F548
Octal Decoder/Demultiplexer with Acknowledge
General Description
The 'F548 is a 3-to-8 line address decoder with four Enable inputs. Two of the Enables are Active LOW and two are Active HIGH for maximum addressing versatility. Also provided is an Active LOW Acknowledge output that responds to either a Read or Write input signal when the Enables are active.
Features
� 3-to-8 line address decoder � Multiple enables for address extension � Open collector acknowledge output � Active LOW decoder outputs
Ordering Code: see section 5 Logic Symbols
Connection Diagrams
ACK
I E E E / I EC
TL/F/9558-3
DMUX
60
Ao
01
A1
02
Az
03
04
E1
05
E2
05
ENS
E1
07
E4
Pin Assignment for DIP, SOIC and Flatpak
02 01 Aci< 3 Wii Rii
Ao 6 A1 7 05 8 05 9
GND 10
20 Yee
19 03 18 04 17 A2 16 E1
15
TL/F/9558-1
Pin Assignment for LCC
o5 A1 AoRiiWR
(]][f](]][fil0
G~0D [5�] [ f i l o [ I ] A cillK ~1
07 [j]
DJ 02
Ooli1.I
~Vee
E4 ij]
[fil 03
~li][j]li][j]
E1 ~ E1 "'1, 04
TL/F/9558-2
Rii
8,9 Q
ACiC
Wii
EN9
TL/F/9558-5
Unit Loading/Fan Out: See Section 2 for u.L. definitions
Pin Names
Description
54F/74F
U.L.
Input l1Hll1L
HIGH/LOW Output loHlloL
Ao-A2 E1,E2 E3,E4 RD WA ACK
Do-07
Output Select Address Inputs Chip Enable Inputs (Active LOW) Chip Enable Inputs Read Acknowledge Input (Active LOW) Write Acknowledge Input (Active LOW) Open Collector Acknowledge Output (Active LOW) Decoded Outputs (Active LOW)
1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 OC*/33.3 50/33.3
20 �A/ -0.6 mA 20 �Al -0.6 mA 20 �A/ -0.6 mA 20 �A/ -0.6 mA 20 �A/ -0.6 mA
*/20 mA -1 mA/20 mA
�oc = Open Collector
4-451
Functional Description
When enabled, the 'F548 accepts the A0-A2 Address inputs and decodes them to select one of eight active LOW, mutually exclusive outputs, as shown in the Decoder Truth Table. When one or more Enables is inactive, all decoder outputs are HIGH. Thus, the 'F548 can be used as a demultiplexer by applying data to one of the Enables.
The open collector Acknowledge (ACK) output is normally HIGH (i.e., OFF) and goes LOW when the Enables are all active and either the Read (RD) or Write (WR) input is LOW, as indicated in the Acknowledge Truth Table.
Acknowledge Truth Table Inputs
E1 E2 Ea E4 RD WR
Hxxx x x xHxx x x xxLx x x
xxxL x x
L
L
H
H
H
H
L
L
H
H
L
x
L
L
H
H
x
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Output
ACK
H H H
H H L L
Decoder Truth Table
Inputs
Outputs
E1
E2
Ea
E4
A2
A1
Ao
Oo
01
02
Oa
04
05
Os
07
H
x
x
x
x
x
x
H
H
H
H
H
H
H
H
x H
x
x
x
x
x
H
H
H
H
H
H
H
H
x x
L
x
x
x
x
H
H
H
H
H
H
H
H
x x
x
L
x
x
x
H
H
H
H
H
H
H
H
L
L
H
H
L
L
L
L
H
H
H
H
H
H
H
L
L
H
H
L
L
H
H
L
H
H
H
H
H
H
L
L
H
H
L
H
L
H
H
L
H
H
H
H
H
L
L
H
H
L
H
H
H
H
H
L
H
H
H
H
L
L
H
H
H
L
L
H
H
H
H
L
H
H
H
L
L
H
H
H
L
H
H
H
H
H
H
L
H
H
L
L
H
H
H
H
L
H
H
H
H
H
H
L
H
L
L
H
H
H
H
H
H
H
H
H
H
H
H
L
Logic Diagram
Ao
E1------. E2------~~
E3 E4
iffi WR
07
TL/F/9558-4 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-452
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�c
Ambient Temperature under Bias
-55�C to+ 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to + 7.0V
Input Voltage (Note 2)
-0.5Vto +7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5VtoVee -0.5Vto +5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C o�cto +70�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
54F/74F Min Typ Max
Units Vee
Conditions
V1H
Input HIGH Voltage
2.0
v
Recognized as a HIGH Signal
V1L
Input LOW Voltage
Vco
Input Clamp Diode Voltage
VoH
Output HIGH
Voltage
54F 10% Vee 2.5
74F 10% Vee 2.5
74F5% Vee
2.7
0.8
v
Recognized as a LOW Signal
-1.2
v
Min l1N = -18 mA
loH = -1 mA (Oo-07)
v
Min loH = -1 mA (Oo-07)
loH = -1 mA (Oo-07)
VoL
Output LOW
Voltage
54F 10% Vee 74F 10% Vee
0.5 0.5
v
Min loL = 20 mA
loL = 20 mA
l1H
Input HIGH
54F
Current
74F
20.0
V1N = 2.7V
5.0
�A Max
lsv1
Input HIGH Current 54F
Breakdown Test
74F
100
�A
Max V1N = 7.0V
7.0
leEx
Output HIGH
54F
Leakage Current
74F
250 50
�A
Max VouT =Vee
V10
Input Leakage
Test
74F
4.75
v
0.0 110 = 1.9 �A
All Other Pins Grounded
loo
Output Leakage 74F
Circuit Current
3.75
�A
0.0 V100 = 150 mV
All Other Pins Grounded
l1L
Input LOW Current
las
Output Short-Circuit Current
-0.6
mA
Max V1N = 0.5V
-60
-150 mA Max VouT = ov (Oo-07)
loHC
Open Collector, Output OFF Leakage Test
250
�A
Min VouT = Vee (ACK)
leeH
Power Supply Current
14
21
mA Max Vo= HIGH
4-453
AC Electrical Characteristics: see section 2 tor Waveforms and Load Configurations
Symbol
Parameter
tPLH
Propagation Delay
tPHL
An to On
tPLH
Propagation Delay
tPHL
E1 or E2 to On
tPLH
Propagation Delay
tpHL
E3 or E4 to On
tPLH
Propagation Delay
tPHL
E1 or E2 to ACK
tPLH
Propagation Delay
tPHL
E3 or E4 to ACK
tPLH
Propagation Delay
tPHL
RD or WR to ACK
74F
TA= +25�c Vee= +5.0V
CL= 50pF
Min
Typ
Max
2.0
5.5
8.0
4.0
8.0
9.5
2.5
6.5
8.5
3.5
6.5
8.5
4.0
8.5
9.5
4.0
8.5
9.5
6.5
11.0
12.5
3.0
7.5
9.5
8.0
13.0
14.0
4.0
8.5
10.0
5.5
10.0
12.0
2.5
5.0
8.0
54F
TA, Vee= Mil CL= 50pF
Min
Max
3.0
10.0
4.0
12.0
3.0
10.0
3.5
10.0
5.0
13.0
4.0
12.5
6.5
16.5
3.0
11.0
8.0
19.5
4.0
13.0
5.5
16.5
2.5
8.5
74F
TA, Vee= Com CL= 50pf
Min
Max
1.5
9.0
4.0
10.0
2.0
9.5
3.0
9.5
3.0
10.5
3.5
10.5
6.5
13.0
3.0
10.5
8.0
15.0
4.0
11.5
5.5
12.5
2.5
8.5
Fig. Units No.
ns 2-3 ns 2-3 ns 2-3 ns 2-3 ns 2-3 ns 2-3
4-454
U1
U1
~National
� 0
U1
U Semiconductor
U1 -"
54F/74F550 � 54F/74F551 Octal Registered Transceiver with Status Flags
General Description
The 'F550 and 'F551 octal transceivers each contain two 8bit registers for temporary storage of data flowing in either direction. Each register has its own clock pulse and clock enable inputs, as well as a flag flip-flop that is set automatically as the register is loaded. Each flag flip-flop is provided with a clear input, and each register has a separate output enable control for its TRI-STATE� buffers. The separate clocks, flags and enables provide considerable flexibility as 110 ports for demand-response data transfer. The 'F550 is non-inverting; the 'F551 inverts data in both directions.
Features
� 8-bit bidirectional 1/0 port with handshake � Back-to-back registers for storage � Register status flag flip-flops � Separate edge-detecting clears for flags � Inverting and non-inverting versions � B outputs sink 64 mA (48 mA Mil)
Ordering Code: see section 5
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
'F550
AJ 1 A4 2 As 3
� CFBA
FSA 5
B7 9 B5 10 FAB 11 CFAB 12 B5 13 B4 14
28 A2 A1 Ao
w
CPB
CEii
GND
CEA
CPA filjj
Bo 17 B1 16 B2 15 B3
TL/F/9559-1
'F551
A3 1
A� As CFBA 4 FBA 5 As 6 A7 Vee
ii1 9
iis 10 FAB 11 CFAB 12
iis 13 ii_. 14
28 A2
27 :A, 26 Ao
w 25
24 CPB
23 CEii
22 GND
21 CEA
20 CPA 19 filjj 18 iio
17 ii,
16 ii2 15 ii3
I E E E / I EC
TL/F/9559-B
Pin Assignment forLCC 'F550
I~ m0 m~~m.... ~
(j]l!Q][[][[][I][[]IIJ
CPA Im ill [j]
GND~
CEli I]]
CPB Ii]]
DEA llZJ
Ao Ii]]
III CFAB
[II FAB
[I]B5
III e7
~Yee ~A7 ~A5
[ID~~llll~~~ ...(<C(N.(l.(".,.t>~~
(.)
TL/F/9559-2
'F551
I"'~ 1m0 1cD1mN1~1~1~
(j]l!Q][[][[][Z][I]IIJ
CPA [j]
ill [j]
GND~
CEli I]]
CPB Ii]]
DEA 1i1J
Ao ff�l
[II CFAB
[II FAB
rIJiis
III ii7
~Yee ~ A7 ~As
[ID~~llll~~~ 1-<'1~1-ct...,,l<C.(...,<C(tn~ ~
TL/F/9559-9
E
4-455
.....
I.I)
�I.I) Connection Diagrams (Continued)
0
I.I) I.I)
'F550
CPA CEA CFAB OEA CPB CEB CFBA OEB
Ao
Bo
A1
81
A2
82
A3
83
A4
84
As
Bs
As
85
A1
87
TL/F/9559-10
Logic Symbols
'F550
'F551
CPA
CEA
CFAB
FAB
OEA
CPB
CEB
FBA
CFBA
OEB
Ao .----1......______~.....-�80
A1 .----1......_ _ _ _ _ _~.....-�81
A2 .----1....._______: .....- � 82
A3 .----1,.......__ _ _ __;--� 83
A4 .----1,.......__ _ _ __;--� 84
As
t - - - - - -.....-. - - - 8s
As .----1~
~1---+8s
A1
------~.....-�81
TL/F/9559-11
'F551
CFBA Ao A1 A2 A3 A4 As A5 A1
CFAB
CPA CPB
FAB
CEA
FBA
CEB
OEA
OEB Bo B1 82 83 84 Bs 85 87
CFBA Ao A1 A2 A3 A4 As As A1
CFAB
CPA CPB
FAB
CEA
FBA
CEB
OEA
OEB
TL/F/9559-3
Unit Loading/Fan Out: See Section 2 for U.L. definitions
Pin Names
Description
CPA CP8 CEA CE8 OEA OE8 CFA8 CF8A Ao-A7
Bo-81
FA8 F8A
A-to-8 Clock Pulse Input (Active Rising Edge) 8-to-A Clock Pulse Input (Active Rising Edge) A-to-8 Clock Enable Input (Active LOW) 8-to-A Clock Enable Input (Active LOW) A Output Enable Input (Active LOW) 8 Output Enable Input (Active LOW) A-to-8 Flag Clear Input (Active Rising Edge) 8-to-A Flag Clear Input (Active Rising Edge) A-to-8 Data Inputs or TRI-STATE 8-to-A Outputs 8-to-A Data Inputs or TRI-STATE A-to-8 Outputs A-to-8 Status Flag Output (Active HIGH) 8-to-A Status Flag Output (Active HIGH)
U.L. HIGH/LOW
1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 3.5/1.083 150/40 (33.3) 3.5/1.083 600/106.6 (80) 50/33.3 50/33.3
TL/F/9559-7
54F/74F
Input l1Hll1L Output loHllOL 20 �A/-0.6 mA 20 �A/ - 0.6 mA 20 �A/-0.6 mA 20 �A/-0.6 mA 20 �A/-0.6 mA 20 �A/-0.6 mA 20 �A/-0.6 mA 20 �A/ - 0.6 mA 70 �A/-0.65 mA -3 mA/24 mA (20 mA) 70 �A/ - 0.65 mA -12 mA/64 mA (48 mA) -1 mA/20 mA -1 mA/20mA
4-456
Functional Description
Data applied to the A inputs is entered and stored on the rising edge of the A Clock Pulse (CPA), provided that the A Clock Enable (CEA) is LOW; simultaneously, the status flipflop is set and the A-to-8 flag (FA8) output goes HIGH. Data thus entered from the A inputs is present at the inputs to the 8 output buffers, but only appears on the 8 1/0 pins when the 8 Output Enable (OE8) signal is made LOW. After the 8 output data is assimilated, the receiving system clears the A-to-8 flag flip-flop by applying a LOW-to-HIGH tran-
U1
U1
sition to the CFA8 input. Optionally, the OE8 and CFA8 pins can be tied together and operated by one function from
� 0
U1
.U...1..
the receiving system.
Data flow from 8-to-A proceeds in the same manner described for A-to-8 flow. Inputs CE8 and CP8 enter the 8 input data and set the 8-to-A flag (F8A) output HIGH. A LOW signal on OEA enables the A output buffers and a LOW-to-HIGH transition on CF8A clears the F8A flag.
Logic Diagrams
'F550
�-DE-TA-IL-A--------------------
A1
81
A2
82
AJ
83
A4
DETAIL Ax7
84
A5
85
A5
85
A1
87
OEA----1:�
1n----OE8
TL/F /9559-4 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-457
,....
i.n
�i.n Logic Diagrams (Continued)
0
i.n
i.n
'F551
�-DE-TA-IL-A--------------------
A0 ~+--tx: o----ta
At
ii,
A2
ii2
A3
ii3
A4
DETAIL Ax7
ii4
As
iis
As
iis
A1
ii1
OEA---4�
K.J----OEB
TL/F /9559-12 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-458
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
-65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to+ 7.0V
Input Voltage (Note 2)
-0.5V to+ 7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
-0.5V to Vee -0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
(J1
(J1
Recommended Operating Conditions
� 0
(J1
.(.J..1..
Free Air Ambient Temperature
Military
- 55�C to + 125�C
Commercial
0�Cto +70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
Parameter
V1H
Input HIGH Voltage
V1L
Input LOW Voltage
Veo
Input Clamp Diode Voltage
54F/74F Min Typ Max
Units Vee
Conditions
2.0
v
Recognized as a HIGH Signal
0.8
v
Recognized as a LOW Signal
-1.2
v
Min l1N = -18mA
VoH
Output HIGH
54F 10% Vee 2.5
Voltage
54F 10% Vee 2.4
54F 10% Vee 2.0
74F10% Vee 2.5
74F 10% Vee 2.4
74F 10% Vee 2.0
74F5% Vee
2.7
74F5% Vee
2.7
loH = -1 mA (Ao-A7)
loH = - 3 mA (Ao-A7)
loH = -12 mA (Bo-B7)
v
Min loH = -1 mA (Ao-A7)
loH = -3 mA (Ao-A7)
loH = -15 mA (Bo-B7)
loH = -1 mA (Ao-A7)
loH = -3 mA (Ao-A7)
VoL
Output Low
Voltage
54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee
0.5
loL = 20 mA (Ao-A7)
0.55
v
Min loL = 48 mA (Bo-B7)
0.5
loL = 24 mA (Ao-A7)
0.55
loL = 64 mA (Bo-B7)
l1H
Input HIGH
54F
Current
74F
20.0
V1N = 2.7V (Non 1/0 Inputs) �A Max
5.0
lsv1
Input HIGH Current 54F
Breakdown Test
74F
100
�A
Max V1N = 7.0V (Non 1/0 Inputs)
7.0
lsv1r
Input HIGH Current 54F
Breakdown (1/0)
74F
1.0
mA Max V1N = 5.5V (An, Bn)
0.5
leEx
Output HIGH
54F
Leakage Current
74F
250 50
�A
Max Vour =Vee
V10
Input Leakage
74F
4.75
Test
v
0.0
110 = 1.9 �A All Other Pins Grounded
loo
Output Leakage
74F
Circuit Current
3.75
�A
0.0
V100 = 150 mV All Other Pins Grounded
l1L
Input LOW Current
-0.6 mA Max V1N = 0.5V (Non 1/0 Inputs)
l1H + lozH Output Leakage Current
70
�A Max Vour = 2.7V (Ao-A7, Bo-B7)
l1L + lozL Output Leakage Current
-650 �A Max Vour = 0.5V (Ao-A7, Bo-B1)
4-459
,....
Ln
�Ln DC Electrical Characteristics (Continued)
0
Ln Ln Symbol
Parameter
54F/74F
Min
Typ
Max
Units Vee
Conditions
los
Output Short-Circuit Current
lzz
Bus Drainage Test
-60 -100
-150
mA
Max VouT = ov (Ao-A7)
-225
mA
Max VouT = ov (Bo-81)
500
�A
o.ov VouT = 5.25V
lccH
Power Supply Current
84
140
mA
Max Vo= HIGH
lccL
Power Supply Current
105
140
mA
Max Vo= LOW
lccz
Power Supply Current
102
140
mA
Max Vo= HIGHZ
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
tPLH tPHL tPLH
tPHL
tpzH tpzL tpHz tpLz
Propagation Delay CPA or CPB to Bn or An
Propagation Delay CPA or CPB to FBA or FAB
Propagation Delay CFAB or CFBA to FAB or FBA
Output Enable Time OEA or OEB to An or Bn
Output Disable Time OEA or OEB to An or Bn
74F
TA= +25�C Vee= +5.0V
CL= 50pf
Min
Typ
Max
3.0
5.5
7.5
4.0
7.0
9.0
3.5
6.0
8.0
5.0
9.0
11.5
2.5
5.5
7.5
3.5
7.0
9.5
3.0
6.5
9.0
2.5
5.5
7.5
54F
TA, Vee~ Mil CL= 50 pf
Min
Max
74F
TA, Vee= Com CL= 50 pf
Min
Max
2.5
8.5
3.5
10.0
3.0
9.0
4.5
13.0
2.0
8.5
3.0
10.5
2.5
10.0
2.0
8.5
Fig. Units
No.
ns 2-3 ns 2-3 ns 2-3 ns 2-5
AC Operating Requirements: See Section 2 for Waveforms
Symbol
Parameter
t5(H) t5(L) th(H) th(L) t5(H) t5(L) th(H) th(L) tw(H) tw(L) tw(H)
tree
Setup Time, HIGH or LOW An, Bn to CPA, CPB
Hold Time, HIGH or LOW An, Bn to CPA, CPB
Setup Time, HIGH or LOW CEA, CEB to CPA, CPB
Hold Time, HIGH or LOW CEA, CEB to CPA, CPB
Pulse Width, HIGH or LOW CPAorCPB
Pulse Width, HIGH CFABorCFBA
Recovery Time CFAB, CFBA to CPA, CPB
74F
TA= +25�C Vee= +5.0V
Min
Max
4.0 4.0
2.0 2.0
1.0 4.0
2.0 2.0
3.0 3.0
3.0
9.0
54F
TA, Vee= Mil
Min
Max
74F
TA, Vee= Com
Min
Max
4.5 4.5
2.5 2.5
1.5 4.5
2.5 2.5
3.5 3.5
3.5
Units Fig. No.
ns
2-6
ns
2-6
ns
2-4
ns
2-4
10.0
ns
2-6
4-460
U1
U1
~DNaStemiicoonnduactlor
N
54F/74F552 Octal Registered Transceiver with Parity and Flags
General Description
The 'F552 octal transceiver contains two 8-bit registers for temporary storage of data flowing in either direction. Each register has its own clock pulse and clock enable input as well as a flag flip-flop that is set automatically as the register is loaded. The flag output will be reset when the output enable returns to HIGH after reading the output port. Each register has a separate output enable control for its TRISTATE� buffer. The separate Clocks, Flags, and Enables provide considerable flexibility as 1/0 ports for demand-response data transfer. When data is transferred from the Apart to the 8-port, a parity bit is generated. On the
other hand, when data is transferred from the 8-port to the A-port, the parity of input data on 80-87 is checked.
Features
� 8-8it bidirectional 1/0 Port with handshake � Register status flag flip-flops � Separate clock enable and output enable � Parity generation and parity check � 8-outputs sink 64 mA � TRI-STATE outputs
Ordering Code: see sections
Logic Symbols
ERROR
rR
rs
TL/F/9561-1
I E E E / I EC
PARITY
ERROR
rs
FR
Ao
Bo
A1
B1
A2
B2
A3
B3
A4
B4
As
Bs
As
Bs
A1
B1
TL/F/9561-5
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
B4 Bs Bs 3 B1 4 OEBR
CPR
CTR 7
Vee ERROR
rs 10
A1 11 As 12 As 13 A4 14
28 B3 27 B2 26 B1 25 Bo 24 FR 23 PARITY 22 GND
21 ffi
20 CPS 19 DEAS
18 Ao
17 A1 16 A2 15 A3
Pin Assignment for LCC and PCC
DEAS Ao A1 A2 A3 A4 As [j][@][[][�]CIJIIJ!Il
CPS Ill! ffi Ill!
GND~
PARITY I� FR [fil
Bo [j] B1 Ii]]
Ill As
CI] A1
mrs
[I) ERROR
~Vee
[!)CTR Im CPR
!i]Jlfil~~lm~~ B2 83 84 Bs Bs B1 OEBR
TL/F/9561-3
TL/F/9561-2
4-461
Unit Loading/Fan Out: see Section 2 for U.L. definitions
Pin Names
Ao-A7
Bo-87
FR FS PARITY
ERROR CER CES CPR CPS OEBR
OEAS
Description
A-to-B Port Data Inputs or 8-to-A TRI-STATE B-to-A Transceiver Inputs or A-to-8 TRI-STATE Output B Port Flag Output A Port Flag Output Parity Bit Transceiver Input or Output
Parity Check Output (Active LOW) R Registers Clock Enable Input (Active LOW) S Registers Clock Enable Input (Active LOW) R Registers Clock Pulse Input (Active Rising Edge) S Registers Clock Pulse Input (Active Rising Edge) B Port and PARITY Output Enable (Active LOW) and Clear FR Input (Active Rising Edge) A Port Output Enable (Active LOW) and Clear FS Input (Active Rising Edge)
54F/74F
U.L. HIGH/LOW
Input l1H/l1L Output loHlloL
3.5/1.083 150/40 (33.3)
3.5/1.083 600/106.6 (80)
50/33.3 50/33.3 3.5/1.083 600/106.6 (50) 50/33.3 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/2.0
70 �A/-0.65 mA -3 mA/24 mA (20 mA)
70 �A/-0.65 mA -12 mA/64 mA (48 mA)
-1 mA/20 mA -1 mA/20 mA 70 �A/-0.65 mA -12 mA/64 mA (48 mA) -1 mA/20 mA 20 �A/ - 0.6 mA 20 �A/-0.6 mA 20 �A/-0.6 mA 20 �A/-0.6 mA 20 �A/ -1.2 mA
1.0/2.0
20 �A/ -1.2 mA
Functional Description
Data applied to the A-inputs are entered and stored in the R register on the rising edge of the CPR Clock Pulse, provided that the Clock Enable (CER) is LOW; simultaneously, the status flip-flop is set and the flag (FR) output goes HIGH. As the Clock Enable (CER) returns to HIGH, the data will be held in the R register. These data entered from the A-inputs will appear at the B-port 1/0 pins after the Output Enable (OEBR) has gone LOW. When OEBR is LOW, a parity bit appears at the PARITY pin, which will be set HIGH when there is an even number of 1s or all Os at the Q outputs of the R register. After the data is assimilated, the receiving system clears the flag FR by changing the signal at the OEBR pin from LOW to HIGH.
Data flow from 8-to-A proceeds in the same manner described for A-to-B flow. A LOW at the CES pin and a LOWto-HIGH transition at CPS pin enters the 8-input data and the parity-input data into the S registers and the parity register respectively and set the flag output FS to HIGH. A LOW signal at the OEAS pin enables the A-port 1/0 pins and a LOW-to-HIGH transition of the OEAS signal clears the FS flag. When OEAS is LOW, the parity check output ERROR will be HIGH if there is an odd number of 1s at the Q outputs of the S registers and the parity register. The flag FS can be cleared by a LOW-to-HIGH transition of the OEAS signal.
Register Function Table
(Applies to R or S Register)
Inputs
D
CP
CE
x
x
H
L ..r L
H ..r L
x
t
L
Internal
a
NC L H NC
Function Hold Data Load Data Keep Old Data
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial .../' =LOW-to-HIGH Transition t = Not LOW-to-HIGH Transition NC = No Change
Output Control
Internal
AorB
OE
a
Outputs
Function
H
x
z
Disable Output
L
L
L
Enable Output
L
H
H
Enable Output
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance
Flag Flip-Flop Function Table (Applies to R or S Flag Flip-Flop)
Inputs
CE
CP
OE
H
x
t
L
..r
t
x
x
__/
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial .../' = LOW-to-HIGH Transition t = Not LOW-to-HIGH Transition
NC = No Change
Flag Output
NC H L
Function
Hold Flag Set Flag Clear Flag
4-462
Functional Description
Parity Generation Function
OEBR
H L L
Number of HIGHs In the Q Outputs of the R Register
x
0,2,4,6,8 1, 3, 5, 7
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Parity Output
z
H L
Block Diagram
U1 U1 N
Parity Check Function
OEAS
H L L L L
Number of HIGHs in the Q Outputs of the S Register
x
0,2,4,6,8 1,3,5, 7
0,2,4,6,8 1,3,5, 7
Parity Input
x
L L H H
ERROR Output
H L H H L
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
rs
~ r---
OEAS
l
Wi
.-..
FLAG
r--
.--
FLAG
f-J
r-
r-t-1-t-'
c~ I---' "-
l
'l<
r-------------- .
CPR
-[><>-;
Ao
.....
'J
J
_i_]
REGISTER-R
R~~
RO _i_
:i]
[:i
H
l
I L
I I
IJ
JI
I
I
l I
:!]
L...!.
~
R_~so
I
REGISTER-S
I' L J,
~--------------�
A1
J J ]
REGISTER-R
R~7 5=
J
L
1
L J
J L
rr=t-_' ~ 57
REGISTER-S
l L [
-'
ERROR
' - + -I - + - "-t-1I - '
~ . _
PARITY CHECK
PARITY GENERATION
I - 'H-t-
t - -1-t-"
t-t-'
t--
4-463
FR OEBR
ffi
CPS Bo
87
PARITY TL/F/9561-4
Absolute Maximum Ratings (Note 1)
If MilitaryI Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
-65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
-55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to + 7.0V
Input Voltage (Note 2)
-0.5V to+ 7.0V
Input Current (Note 2)
-30 mA to + 5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
-0.5VtoVee -0.5V to + 5.5V
Current Applied to Output
in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol V1H V1L Veo VoH
Vol
l1H lsv1 lsv1r leEX V10 loo l1L
l1H + lozH l1L + lozL
los lzz leeH leeL leez
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee 74F 10% Vee 74F 5% Vee 74F 5% Vee
Output LOW Voltage
54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F Breakdown Test 74F
Input HIGH Current 54F Breakdown (1/0) 74F
Output HIGH
54F
Leakage Current 74F
Input Leakage Test
74F
Output Leakage Circuit Current
74F
Input LOW Current
Output Leakage Current Output Leakage Current Output ShortCircuit Current Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current
54F/74F
Min Typ Max
2.0
0.8
-1.2
2.5 2.4 2.0 2.5 2.4 2.0 2.7 2.7
0.5 0.55 0.5 0.5 0.55
20.0 5.0
100 7.0
1.0 0.5
250 50
4.75
3.75
-0.6 -1.2
70
-650
-60 -100
-150 -225
500
100 150
100 150
110 165
Units
v v v
v
v
�A �A mA �A
v
�A mA �A �A mA �A mA mA mA
Vee
Min
Min
Min
Max Max Max Max 0.0 0.0 Max Max Max Max
o.ov
Max Max Max
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal l1N = -18 mA (CEA, CES, CPR, CPS, OEBR, OEAS) loH = -1 mA (FR, FS, ERROR, An) loH = -3 mA (An. Bn. PARITY) loH = -12 mA (Bn, PARITY) loH = -1 mA (FR, FS, ERROR, An) loH = -3 mA (An. Bn PARITY) loH = -15 mA (Bn. PARITY) loH = -1 mA (FR, FS, ERROR, An) loH = -3 mA (An. Bn. PARITY) loL = 20 mA (FR, FS, ERROR, An) loL = 48 mA (Bn, PARITY) loL = 20 mA (FR, FS, ERROR) loL = 24 mA (An) loL = 64 mA (Bn, PARITY)
V1N = 2.7V (CEA, CES, CPR, CPS, OEBR, OEAS)
V1N = 7.0V (CEA, CES, CPR, CPS, OEBR, OEAS)
V1N = 5.5V (An, Bn. PARITY)
VouT = Vee (FR, FS, ERROR, An. Bn. PARITY)
llD = 1.9 �A All other pins grounded V100 = 150 mV All other pins grounded V1N = 0.5V (CEA, CES, CPR, CPS) V1N = 0.5V (OEBR, OEAS) VouT = 2.7V (An. Bn. PARITY) Vour = 0.5V (An, Bn, PARITY) Vour = OV (FR, FS, ERROR, An)
ov Vour = (Bn, PARITY)
VouT = 5.25V (An, Bn, PARITY) Vo= HIGH Vo= LOW Vo= HIGHZ
4-464
U1
U1
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
I\.)
Symbol
Parameter
tPLH tPHL tpLH
tpHL
tPLH tpHL tPLH tPHL tPLH tPHL tpzH tPZL tpHz tpLz tpzH tpzL tpHZ tpLZ
Propagation Delay CPS or CPR to An or Bn
Propagation Delay CPS or CPR to FS or FR
Propagation Delay OEASto FS
Propagation Delay CPR to Parity
Propagation Delay CPS to ERROR
Propagation Delay OEAS to ERROR
Enable Time OEAS or OEBR to Bn or An
Disable Time OEAS or OEBR to Bn or An
Enable Time OEBR to Parity
Disable Time OEBR to Parity
74f
TA= +25�C Vee= +5.0V
CL= 50 pf
Min
Typ
Max
3.5
6.0
8.0
4.0
7.0
9.5
3.0
5.5
7.5
3.5
6.0
8.0
8.0
14.0
18.0
8.5
14.5
18.5
8.0
13.5
17.5
7.5
13.0
16.5
3.5
6.0
8.0
3.0
5.0
7.0
3.0
5.5
7.5
3.5
7.0
9.5
3.0
6.5
8.5
3.0
5.5
7.5
3.0
4.5
7.5
3.5
6.0
9.5
3.0
5.5
8.5
3.0
6.5
7.5
54f
TA, Vee= Mil CL= 50 pF
Min
Max
74f
TA, Vee= Com CL= 50 pf
Min
Max
3.0
9.0
3.5
10.5
2.5
8.5
Fig. Units No.
ns 2-3 ns 2-3
3.0
9.0
ns 2-3
7.0
20.0
ns 2-3
7.5
20.5
7.0
19.5
ns 2-3
6.5
18.5
3.0
9.0
ns 2-3
2.5
8.0
2.5
8.5
3.0
10.5
ns 2-5
2.5
9.5
2.5
8.5
2.5
8.5
3.0
10.5
ns 2-5
2.5
9.5
2.5
8.5
AC Operating Requirements: See Section 2 for Waveforms
Symbol
Parameter
t5 (H) t5 (L)
th(H) th(L)
t 5 (H) t5 (L) th(H) th(L) tw(H) tw(L)
Setup Time, HIGH or LOW An or Bn or Parity to CPS or CPR
Hold Time, HIGH or LOW An or Bn or Parity to CPS or CPR
Setup, Time HIGH or LOW CES or CEA to CPS or CPR
Hold Time, HIGH or LOW CES or CEA to CPS or CPR
Pulse Width, HIGH or LOW CPS or CPR
74f
TA= +25�C Vee= +5.0V
Min
Max
7.5 4.5
0 0
6.0 10.0
0 0
4.0 6.0
54f
TA, Vee= Mil
Min
Max
74f
TA, Vee= Com
Min
Max
8.5 5.0
0 0
Fig. Units
No.
ns
2-6
7.0 11.5
0 0
4.5 7.0
ns
2-6
ns
2-4
4-465
U~NaStemiicoonnduactlor
54F/74F563
Octal D-Type Latch with TRI-STATE� Outputs
General Description
The 'F563 is a high-speed octal latch with buffered common Latch Enable (LE) and buffered common Output Enable (OE) inputs.
This device is functionally identical to the 'F573, but has inverted outputs.
Features
� Inputs and outputs on opposite sides of package allowing easy interface with microprocessors
� Useful as input or output port for microprocessors � Functionally identical to 'F573
Ordering Code: see Sections Logic Symbols
Connection Diagrams
Do D1 D2 03 04 05 Ds 0., LE
OE
TL/F/9562-3
IEEE/IEC
OE LE
Do
oo
D1
01
D2
02
D3
03
D4
04
D5
05
Ds
05
07
07
TL/F/9562-5
Pin Assignment for DIP, SOIC and Flatpak
OE
Do 2 D1 3 D2 4 03 5 04 6 05 7
Ds 07 9 GND 10
20 Vee 19 60 18 01 17 62 16 03 15 04 14 05 13 Os 12 07 11 LE
TL/F/9562-1
Pin Assignment for LCC
Ds 05 04 03 D2
rnJ ill [[] rnJ III
07 [[] GND [QI
LE [j]
07 li1J Os l!ll
[IJD1
rno0
OJ OE
~Vee [j]] Oo
lil!li][ffi[j]~
05 04 03 02 01
TL/F/9562-2
Unit Loading/Fan Out: See section 2 for U.L. definitions
Pin Names
Do-D7 LE OE
Oo-01
Description
Data Inputs Latch Enable Input (Active HIGH) TRI-STATE Output Enable Input (Active LOW) TRI-STATE Latch Outputs
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loHlloL
1.0/1.0 1.0/1.0 1.0/1.0 150/40 (33.3)
20 �A/ - 0.6 mA 20 �Al - 0.6 mA 20 �A/-0.6 mA -3 mA/24 mA (20 mA)
4-466
Functional Description
The 'F563 contains eight D-type latches with TRI-STATE output buffers. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The TRI-STATE buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are in the bi-state mode. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches.
e0wn1
Function Table
Inputs
OE LE D
H xx
H HL H HH
H Lx
L HL L HH
L Lx
Internal
Q
x
H L NC H L NC
Output
0
z z z z
H L NC
Function
High Z High Z High Z Latched Transparent Transparent Latched
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance NC = No Change
Logic Diagram
TL/F/9562-4 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-467
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 15o�c
Ambient Temperature under Bias
- 55�C to + 125�c
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to+ 7.0V
Input Voltage (Note 2)
-0.5Vto +7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
-0.5VtoVee -0.5Vto +5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�c
o�cto +1o�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol V1H V1L Yeo VoH
VoL l1H lsv1 le EX V10 loo l1L lozH lozL los lzz lceL leez
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee 74F5% Vee 74F5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage
74F
Test
Output Leakage
Circuit Current
74F
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Bus Drainage Test
Power Supply Current
Power Supply Current
54F/74F Min Typ Max
2.0
0.8 -1.2
2.5 2.4 2.5 2.4 2.7 2.7
0.5 0.5
20.0 5.0
100 7.0
250 50
4.75
3.75
-0.6
50
-50
-60
-150
500
40
61
40
61
Units v v v
v
v �A �A �A v �A mA �A �A mA �A mA mA
Vee
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal Min l1N = -18 mA loH = -1 mA loH = -3 mA Min loH = -1 mA loH = -3 mA loH = -1 mA loH = -3 mA Min loL = 20 mA loL = 24mA Max V1N = 2.7V
Max V1N = 7.0V
Max VouT =Vee
0.0
0.0
Max Max Max Max o.ov Max Max
110 = 1.9 �A All Other Pins Grounded V100 = 150mV All Other Pins Grounded V1N = 0.5V VouT = 2.7V VouT = 0.5V VouT = ov VouT = 5.25V Vo= LOW Vo= HIGHZ
4-468
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
tPLH tPHL
tPLH tPHL
tpzH tpzL
tpHz tpLz
Propagation Delay Dn to On Propagation Delay LE to On Output Enable Time
Output Disable Time
74F
TA= +25�C Vee= +5.0V
CL= 50 pF
Min
Typ
Max
3.5
8.5
2.5
6.5
4.5
9.5
3.0
7.0
2.0
7.5
3.0
8.5
1.5
5.5
1.5
5.5
54F
TA, Vee= Mil CL= 50 pF
Min
Max
3.0
10.5
2.0
7.5
4.0
11.0
2.5
7.5
2.0
9.5
2.5
10.0
1.5
7.0
1.5
5.5
74F
TA, Vee= Com CL= 50 pF
Min
Max
3.0
9.5
2.0
7.0
4.0
10.5
2.5
7.0
2.0
9.0
1.5
9.5
1.5
6.5
1.5
5.5
U1 a>
(,.)
Fig. Units
No.
ns
2-3
ns
2-3
ns
2-5
AC Operating Requirements: See Section 2 for Waveforms
Symbol
Parameter
t5 (H) t5 (L)
th(H) th(L)
tw(H)
Setup Time, HIGH or LOW Dn to LE
Hold Time, HIGH or LOW Dn to LE
LE Pulse Width, HIGH
74F
TA= +25�C Vee= +5.0V
Min
Max
2.0 2.0
3.0 3.0
4.0
54F
TA, Vee= Mil
Min
Max
2.0 2.0
3.0 3.0
4.0
74F
TA, Vee= Com
Min
Max
2.0 2.0
3.0 3.0
4.0
Fig. Units
No.
ns
2-6
ns
2-6
ns
2-4
4-469
~National
U Semiconductor
54F/74F564
Octal D-Type Flip-Flop with TRI-STATE� Outputs
General Description
The 'F564 is a high-speed, low power octal flip-flop with a buffered common Clock (CP) and a buffered common Output Enable (OE). The information presented to the D inputs is sorted in the flip-flops on the LOW-to-HIGH Clock (CP) transition.
This device is functionally identical to the 'F574, but has inverted outputs.
Features
� Inputs and outputs on opposite sides of package allow easy interface with microprocessors
� Useful as input or output port for microprocessors � Functionally identical to 'F574 � TRI-STATE outputs for bus-oriented applications
Ordering Code: see sections Logic Symbols
Connection Diagrams
Do D1 Dz D3 D4 D5 D5 D1 CP
OE
TL/F/9563-3
IEEE/I EC OE CP
Do
Oo
D1
01
Dz
Oz
D3
03
D4
04
D5
05
D5
05
D1
07
TL/F/9563-6
Pin Assignment for DIP, SOIC and Flatpak
OE 1 Do 2 D1 3 D2 4 D3 5 D4 Ds 7 D5 8 D7 GND 10
20 Vee
19 Oo 18 01 17 Oz 16 03 15 04 14 05 13 05 12 07 11 CP
TL/F/9563-1
Pin Assignment for LCC
D5
rn:i
0s
rn
[D[4]
rDn3
rDnz
D1 [[] GND [j])
CP [i]
07 [j] 05 Ii]
CTJD1
rnD0
OJ OE
~Vee
!!ID Oo
[j]] [fil IJ]] [ZJ [i]J 05 04 03 Oz 61
TL/F/9563-2
Unit Loading/Fan Out: see Section 2 for u.L. definitions
Pin Names
Do-D7 CP OE
Oo-01
Description
Data Inputs Clock Pulse Input (Active Rising Edge) TRI-STATE Output Enable Input (Active LOW) TRI-STATE Outputs
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loH/loL
1.0/1.0 1.0/1.0 1.0/1.0 150/40 (33.3)
20 �A/ - 0.6 mA 20 �A/ - 0.6 mA 20 �A/ - 0.6 mA -3 mA/24 mA (20 mA)
4-470
Functional Description
The 'F564 consists of eight edge-triggered flip-flops with individual 0-type inputs and TRI-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold times requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flipflops are available at the outputs. When OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops.
Logic Diagram
Function Table
Inputs
Internal
OE CP D Q
H H L NC
H H H NC
H _r L
H
H _r H
L
L _r L
H
L _r H
L
L H L NC
L H H NC
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance .../" = LOW-to-HIGH Transition NC = No Change
Outputs
0
z z z z
H L NC NC
Function
Hold Hold Load Load Data Available Data Available No Change in Data No Change in Data
TL/F/9563-4 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-471
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to + 7.0V
Input Voltage (Note 2)
-0.5V to+ 7.0V
Input Current (Note 2)
-30 mA to + 5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
-0.5VtoVee -0.5Vto +5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol V1H V1L Veo VoH
VoL l1H lsv1 leEx V10 loo l1L lozH lozL los lzz leez
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 54F 10% Vee 74F% 10% Vee 74F% 10% Vee 74F% 5% Vee 74F% 5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage 74F
Test
Output Leakage
74F
Circuit Current
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Bus Drainage Test
Power Supply Current
54F/74F Min Typ Max
2.0 0.8 -1.2
2.5 2.4 2.5 2.4 2.7 2.7
0.5 0.5
20.0 5.0
100 7.0
250 50
4.75
Units
v v v
v
v
�A �A �A
v
3.75
�A
-0.6 mA
50
�A
-50
�A
-60
-150 mA
500
�A
55
86
mA
Vee
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal Min l1N = -18 mA loH = -1 mA loH = -3 mA loH = -1 mA Min loH = -3 mA loH = -1 mA loH = -3 mA Min loL = 20 mA loL = 24 mA Max V1N = 2.7V
Max V1N = 7.0V
Max VouT =Vee
0.0
0.0
Max Max Max Max
o.ov
Max
110 = 1.9 �A All Other Pins Grounded
V100 = 150 mV All Other Pins Grounded
V1N = 0.5V
VouT = 2.7V VouT = 0.5V
VouT = ov
VouT = 5.25V Vo= HIGHZ
4-472
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
fmax
tPLH tPHL
tpzH tpzL
tpHz tpLz
Maximum Clock Frequency Propagation Delay CPtoOn Output Enable Time
Output Disable Time
74F
TA= +25�C Vee= +5.0V
CL= 50 pf
Min
Typ
Max
100
2.5
5.2
8.5
2.5
5.9
8.5
3.0
5.6
9.0
3.0
6.2
9.0
1.5
3.4
5.5
1.5
2.7
5.5
54F
TA, Vee= Mil CL= 50 pf
Min
Max
60
2.5
9.5
2.5
9.5
2.5
10.5
2.5
10.5
1.5
7.0
1.5
7.0
74F
TA, Vee= Com CL= 50 pf
Min
Max
70
2.5
8.5
2.5
8.5
2.5
10.0
2.5
10.0
1.5
6.5
1.5
6.5
Fig. Units No. MHz 2-1
ns 2-3
ns 2-5
AC Operating Requirements: See section 2 for waveforms
Symbol
Parameter
t5 (H) t5 (L)
th(H) th(L)
tw(H) tw(L)
Setup Time, HIGH or LOW Dn toCP
Hold Time, HIGH or LOW Dn to CP
CP Pulse Width HIGH or LOW
74F
TA= +25�C Vee= +5.0V
Min
Max
2.0 2.5
2.0 2.0
5.0 5.0
54F
TA, Vee= Mil
Min
Max
2.5 3.0
2.0 2.0
5.0 5.0
74F
TA, Vee= Com
Min
Max
2.0 2.5
2.0 2.0
5.0 5.0
Units Fig. No.
ns
2-6
ns
2-4
4-473
en
CD
�U')
co
~National
CD
U')
~Semiconductor
54F/74F568 � 54F/74F569
4-Bit Bidirectional Counters 'IJith TRI-STATE� Outputs
General Description
The 'F568 and 'F569 are fully synchronous, reversible counters with TRI-STATE outputs. The 'F568 is a BCD decade counter; the 'F569 is a binary counter. They feature preset capability for programmable operation, carry lookahead for easy cascading, and a U/D input to control the direction of counting. For maximum flexibility there are both synchronous and master asynchronous reset inputs as well as both Clocked Carry (CC) and Terminal Count (TC) outputs. All state changes except Master Reset are initiated by the rising edge of the clock. A HIGH signal on the Output Enable
(OE) input forces the output buffers into the high impedance state but does not prevent counting, resetting or parallel loading.
Features
� Synchronous counting and loading � Lookahead carry capability for easy cascading � Preset capability for programmable operation � TRI-STATE outputs for bus organized systems
Ordering Code: see Section 5
Logic Symbols
cc TC
IEEE/I EC 'F568
6,7,8,9
IEEE/I EC 'F569
Of
CTRDIV16
U/ii
CP
C5/1,4,7 ,8+ / 2 , 4 , 7 , 8 -
Z6
6,7,8,9
TL/F/9565-1
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
U/D
CP Po 3 P1 P2 P3 6
w 7
iiR 8 5R 9
GND 10
20 Vee 19 TC
18 cc
17 Of
16 Oo
15 01
14 02
13 03
12 CIT
11 PE
TL/F/9565-2
TL/F/9565-4
TL/F/9565-11
Pin Assignment for LCC
MR CEP P3 P2 P1
[[]!Il[]][[)IIJ
G~~o~~~-
PE 1IiJ
[j]U/D
CIT[@
@JVcc
03 1]]
~TC
[11fi]l[�)IIZll!fil
~ o1 Oo 6E cc
TL/F /9565-3
4-474
(J1
O')
Unit Loading/Fan Out: See Section 2 for U.L. definitions
�00
(J1
54F/74F
O')
CD
Pin Names
Description
U.L.
Input l1Hll1L
HIGH/LOW
Output loHlloL
Po-P3 CEP CET CP PE U/D OE MR SR
Oo-03 TC
cc
Parallel Data Inputs Count Enable Parallel Input (Active LOW) Count Enable Trickle Input (Active LOW) Clock Pulse Input (Active Rising Edge) Parallel Enable Input (Active LOW) Up/Down Count Control Input Output Enable Input (Active LOW) Master Reset Input (Active LOW) Synchronous Reset Input (Active LOW) TRI-STATE Parallel Data Outputs Terminal Count Output (Active LOW) Clocked Carry Output (Active LOW)
1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 150/40(33.3) 50/33.3 50/33.3
20 �A/-0.6 mA 20 �A/-0.6 mA 20 �A/-1.2 mA 20 �A/ - 0.6 mA 20 �A/-1.2 mA 20 �A/-0.6 mA 20 �A/-0.6 mA 20 �A/ - 0.6 mA 20 �A/-0.6 mA -3 mA/24 mA (20 mA) -1 mA/20mA -1 mA/20 mA
Functional Description
The 'F568 counts modulo-10 in the BCD (8421) sequence. From state 9 (HLLH) it will increment to 0 (LLLL) in the Up mode; in Down mode it will decrement from 0 to 9. The 'F569 counts in the modulo-16 binary sequence. From state 15 it will increment to state O in the Up mode; in the Down mode it will decrement from O to 15. The clock inputs of all flip-flops are driven in parallel through a clock buffer. All state changes (except due to Master Reset) occurs synchronously with the LOW-to-HIGH transition of the Clock Pulse (CP) input signal.
The circuits have five fundamental modes of operation, in order of precedence: asynchronous reset, synchronous reset, parallel load, count and hold. Five control inputs-Master Reset (MR), Synchronous Reset (SR), Parallel Enable (PE), Count Enable Parallel (CEP) and Count Enable Trickle CET)-plus the Up/Down (U/D) input, determine the mode of operation, as shown in the Mode Select Table. A LOW signal on MR overrides all other inputs and asynchronously forces the flip-flop Q outputs LOW. A LOW signal on SR overrides counting and parallel loading and allows the Q outputs to go LOW on the next rising edge of CP. A LOW signal on PE overrides counting and allows information on the Parallel Data (Pn) inputs to be loaded into the flip-flops on the next rising edge of CP. With MR, SR and PE HIGH, CEP and CET permit counting when both are LOW. Conversely, a HIGH signal on either CEP or CET inhibits counting.
The 'F568 and 'F569 use edge-triggered flip-flops and changing the SR, PE, CEP, CET or U/D inputs when the CP is in either state does not cause errors, provided that the recommended setup and hold times, with respect to the rising edge of CP, are observed.
Two types of outputs are provided as overflow/underflow indicators. The Terminal Count (TC) output is normally HIGH and goes LOW providing CET is LOW, when the
counter reaches zero in the Down mode, or reaches maximum (9 for the 'F568, 15 for the 'F569) in the Up mode. TC will then remain LOW until a state change occurs, whether by counting or presetting, or until U/D or CET is changed. To implement synchronous multistage counters, the connections between the TC output and the CEP and CET inputs can provide either slow or fast carry propagation.
Figure 1 shows the connections for simple ripple carry, in which the clock period must be longer than the CP to TC delay of the first stage, plus the cumulative CET to TC delays of the intermediate stages, plus the CET to CP setup time of the last stage. This total delay plus setup time sets the upper limit on clock frequency. For faster clock rates, the carry lookahead connections shown in Figure 2 are recommended. In this scheme the ripple delay through the intermediate stages commences with the same clock that causes the first stage to tick over from max to min in the Up mode, or min to max in the Down mode, to start its final cycle. Since this final cycle takes 10 ('F568) or 16 ('F569) clocks to complete, there is plenty of time for the ripple to progress through the intermediate stages. The critical timing that limits the clock period is the CP to TC delay of the first stage plus the CEP to CP setup time of the last stage. The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops, registers or counters. For such applications, the Clocked Carry (CC) output is provided. The CC output is normally HIGH. When CEP, CET, and TC are LOW, the CC output will go LOW when the clock next goes LOW and will stay LOW until the clock goes HIGH again, as shown in the CC Truth Table. When the Output Enable (OE) is LOW, the parallel data outputs Oo-03 are active and follow the flip-flop Q outputs. A HIGH signal on OE forces Oo-03 to the High Z state but does not prevent counting, loading or resetting.
4-475
O>
(0
�IJ')
QC) (0
Logic Equations
Count Enable = CEP � CET � PE
IJ')
Up ('F568): TC = Oo � 01 � 02 � 03 � (Up) � CET
('F569): TC = Oo � 01 � 02 � 03 � (Up) � CET
Down (Both): TC = Oo � 01 � 02 � 03 � (Down) � CET
CC Truth Table
Inputs
Output
SR PE CEP CET TC* CP
cc
Lx x x x x H xL x x x x H xx H x x x H xx x H x x H xx x x H x H
H H
L
L
L
l...J
l...J
'TC is generated internally
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
u = HIGH-to-LOW-to-HIGH Clock Transition
Mode Select Table
Inputs
Operating
MR SR PE CEP CET U/D
Mode
L xx x
x
x
Asynchronous Reset
H Lx x
x
x
Synchronous Reset
H
H
L
x
x
x
Parallel Load
H
H
H
H
x
x
Hold
H
H
H
x
H
x
Hold
H
H
H
L
L
H
Count Up
H
H
H
L
L
L
Count Down
H =HIGH Voltage Level L=LOW Voltage Level X =Immaterial
FIGURE 1: Multistage Counter with Ripple Carry
TL/F/9565-5
FIGURE 2: Multistage Counter with Lookahead Carry 4-476
TL/F/9565-6
State Diagrams
'F568
U1
CJ')
�C>
U1
CJ')
'F569
CD
� - - - � COUNT DOWN
-
COUNT UP
TL/F/9565-7
� - - - � COUNT DOWN
-
COUNT UP
TL/F/9565-8
4-477
568�569
'F568
r-
Po
Pf
'\. ~
P1
P2
P3
c0cc;�
~
co;�
CEP
_;;(_ ,,/
cc
l
CET
~
....--
,.....------'
ri ------1-1------,
T ~~~
19 IC
~
~ ~
""I
o.>
3en
J " r--
Do_l i~r-,_ L ~ re
"}":.".' ......
'@ ~
.....
1
_. llf1
) ....--r--
I l
cc
CD
LO T BT I-+-
I----'
U/ii
L UP.._LJ ~I ON
[[
I
UP
BF t-1r--
H----
ON DETAIL A
~
ENF t-
DETAIL A
r---
1--------i
trl
DETAIL A
a;
r~D t----0 5R
1--------i
CP
-
.J.
!
[~ ~ ~h .J.
~
Sil --�>-L()
i.iii
DETAIL A
0 Co
�-------~
- fil
6
~~
~7
6
o0
o1
o2
o3
Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
TL/F/9565-9
'F569
r-
Po
~m tr� il
P1
Pz
P3
I I 1 I [ I I I
cc0c;�
c
iii" cc
""I
D>
3
tn
�t.--------L~; ----T
0
0 ~
5�
r::
.Cet>,
~
i,.
cc
c--o.I
U/O
L!-~1---+--lH--ttt-:--T=i ~: DETAIL A BF
DETAIL A
p DETAIL A
Ci5 Ci5
c0 o SR
CP
..1.
__ I I SR~ I ~!~A!!___J~-h~ J
I
I I I
I I I
Mil
-
Of
~
fl
fl
fl
s:
Do
01
Oz
03
Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
II
TL/F/9565-10
69S�89S
O>
CD
�U')
co
CD
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
U') please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to+ 7.0V
Input Voltage (Note 2)
-0.5V to+ 7.0V
Input Current(Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
-0.5V to Vee -0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
V1H
Input HIGH Voltage
V1L
Input LOW Voltage
Veo
Input Clamp Diode Voltage
54F/74F
Units Vee
Min Typ Max
Conditions
2.0
v
Recognized as a HIGH Signal
0.8 v
Recognized as a LOW Signal
-1.2 v Min l1N = -18 mA
VoH
Output HIGH
Voltage
54F 10% Vee 2.5 54F 10% Vee 2.4 74F 10% Vee 2.5 74F 10% Vee 2.4 74F5% Vee 2.7 74F5% Vee 2.7
loH = -1 mA (TC, CC, On) loH = -3 mA (On)
v Min loH = -1 mA (TC, CC, On)
loH = -3 mA (On) loH = -1 mA (TC, CC, On) loH = -3 mA (On)
VoL
Output LOW
Voltage
54F 10% Vee 74F 10% Vee 74F 10% Vee
0.5
loL = 20 mA (TC, CC, On)
0.5
v Min loL = 20 mA (TC, CC)
0.5
loL = 24 mA (On)
l1H
Input HIGH
54F
Current
74F
20.0 5.0
�A Max V1N = 2.7V
lsv1
Input HIGH Current 54F
Breakdown Test 74F
100 �A Max V1N = 7.0V 7.0
lcEx
Output HIGH
54F
Leakage Current 74F
250 �A Max Vour =Vee (TC, CC, On) 50
V10
Input Leakage Test
74F
4.75
v
0.0
110 = 1.9 �A All Other Pins Grounded
loo
Output Leakage
Circuit Current
74F
3.75
�A
0.0
V100 = 150 mV All Other Pins Grounded
l1L
Input LOW Current
-0.6 mA Max V1N = 0.5V cPn. CEP, CP, U/D, OE, MR, SR) -1.2 mA Max V1N = 0.5V (PE, CET)
4-480
DC Electrical Characteristic (Continued)
Symbol
Parameter
54F/74F
U1
a>
�Q)
U1
Units Vee
Conditions
aco>
Min
Typ
Max
lozH lozL
Output Leakage Current Output Leakage Current
50
�A
Max VouT = 2.7V (On)
-50
�A
Max VouT = 0.5V (On)
las
Output Short-Circuit Current
-60
-150
mA
Max VouT = OV (TC, CC, On)
lzz
Bus Drainage Test
500
�A
O.OV VouT = 5.25V (On)
lccH
Power Supply Current
45
67
mA
Max Vo= HIGH
lccL
Power Supply Current
45
67
mA
Max Vo= LOW
lccz
Power Supply Current
45
67
mA
Max Vo= HIGHZ
'F568
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
fmax tPLH tpHL
tPLH tPHL tPLH tpHL tpLH tPHL tpLH tPHL tPLH tPHL tPHL
tpzH tpzL tpHz tpLz
Maximum Clock Frequency
Propagation Delay CP to On (PE HIGH or LOW)
Propagation Delay CPtoTC
Propagation Delay CETtoTC
Propagation Delay U/DtoTC
Propagation Delay CPtoCC
Propagation Delay CEP, CET to CC
Propagation Delay MR to On
Output Enable Time OE to On
Output Disable Time OE to On
74F
TA= +25�C Vee= +5.0V
CL= 50 pf
Min
Typ
Max
100
115
3.0
6.5
8.5
4.0
9.0
11.5
5.5
12.0
15.5
4.0
8.5
11.0
2.5
4.5
6.0
2.5
6.0
8.0
3.5
8.5
11.0
4.0
12.5
16.0
2.5
5.5
7.0
2.0
4.5
6.0
2.5
5.0
6.5
4.0
8.5
11.0
5.0
10.0
13.0
2.5
5.5
7.0
3.0
6.0
8.0
1.5
5.0
6.5
2.0
4.5
6.0
54F
TA, Vee= Mii CL= 50 pf
Min
Max
74F
TA, Vee= Com CL= 50 pf
Min
Max
90
3.0
9.5
4.0
13.0
5.5
17.5
4.0
12.5
2.5
7.0
2.5
9.0
3.5
12.5
4.0
18.0
2.5
8.0
2.0
7.0
2.5
7.5
4.0
12.5
5.0
14.5
2.5
8.0
3.0
9.0
1.5
7.5
2.0
7.0
Fig. Units
No.
MHz 2-1 ns 2-3 ns 2-3 ns 2-3 ns 2-3 ns 2-3
2-3 ns ns 2-3
ns 2-5
4-481
O>
U>
�Lt) 'F568
co
U>
Lt)
AC Operating Requirements: See Section 2 for Waveforms
Symbol
Parameter
t5(H) t 5(L) th(H) th(L)
t5(H) t5(L) th(H) th(L)
t 5(H) t5(L)
th(H) th(L)
t5(H) t5(L) th(H) th(L)
t5(H) t 5 (L) th(H) th(L)
tw(H) tw(L)
tw(L)
tree
Setup Time, HIGH or LOW Pn to CP
Hold Time, HIGH or LOW Pn to CP
Setup Time, HIGH or LOW CEP or CET to CP
Hold Time, HIGH or LOW CEP or CET to CP
Setup Time, HIGH or LOW PE to CP
Hold Time, HIGH or LOW PE to CP
Setup Time, HIGH or LOW U/DtoCP
Hold Time, HIGH or LOW U/DtoCP
Setup Time, HIGH or LOW SR to CP
Hold Time, HIGH or LOW SR toCP
CP Pulse Width, HIGH or LOW
MR Pulse Width, LOW
MR Recovery Time
74F
TA= +2s0 c Vee= +s.ov
Min
Max
4.0 4.0
3.0 3.0
5.0 5.0
0 0
8.0 8.0
0 0
11.0 16.0
0 0
9.5 8.5
0 0
4.0 6.0
4.5
6.0
54F
TA, Vee= Mil
Min
Max
74F
TA, Vee= Com
Min
Max
4.5 4.5
3.5 3.5
6.0 6.0
0 0
9.0 9.0
0 0
12.5 17.5
0 0
10.5 9.5
0 0
4.5 6.5
5.0
7.0
Units Fig. No.
ns
2-6
ns
2-6
ns
2-6
ns
2-6
ns
2-6
ns
2-6
ns
2-4
ns
2-4
ns
2-6
4-482
U1
O'>
'F569
�CIO
U1
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
cOo'>
Symbol
Parameter
fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tpLH tPHL tPHL
tpzH tpzL tpHz tpLZ
Maximum Clock Frequency
Propagation Delay CP to On (PE HIGH or LOW)
Propagation Delay CPtoTC
Propagation Delay CETtoTC
Propagation Delay U/DtoTC
Propagation Delay CPtoCC
Propagation Delay CEP, CET to CC
Propagation Delay MR to On
Output Enable Time OE to On
Output Disable Time OE to On
74F
TA= +25�C Vee= +5.0V
CL= 50 pf
Min
Typ
Max
90
3.0
6.5
8.5
4.0
9.0
11.5
5.5
12.0
15.5
4.0
8.5
12.5
2.5
4.5
6.5
2.5
6.0
11.0
3.5
8.5
11.5
4.0
8.0
12.0
2.5
5.5
7.0
2.0
4.5
6.0
2.5
5.0
6.5
4.0
8.5
11.0
5.0
10.0
13.0
2.5
5.5
8.0
3.0
6.0
9.0
1.5
5.0
7.0
2.0
4.5
6.0
54F
TA, Vee= Mil CL= 50pF
Min
Max
74F
TA, Vee= Com CL= 50 pF
Units
Fig. No.
Min
Max
70
MHz 2-1
3.0
9.5
ns 2-3
4.0
13.0
5.5
17.5
ns 2-3
4.0
13.0
2.5
7.0
ns 2-3
2.5
12.0
3.5
12.5
ns 2-3
4.0
13.0
2.0
8.0
ns 2-3
2.0
7.0
2.0
7.5
2-3 ns
4.0
12.5
5.0
14.5
ns 2-3
2.5
8.5
3.0
10.0
ns 2-5
1.5
8.0
2.0
7.0
4-483
O>
CD
�Lt) 'F569
ClO
CD
Lt)
AC Operating Requirements: See Section 2 for Waveforms
Symbol
Parameter
t 5 (H) t 5 (L) th(H) th(L)
t5 (H) t5 (L) th(H) th(L)
t 5 (H) t 5 (L) th(H) th(L)
t5 (H) t5 (L)
th(H) th(L)
t 5 (H) t 5 (L) th(H) th(L)
tw(H) tw(L)
tw(L)
tree
Setup Time, HIGH or LOW Pn to CP
Hold Time, HIGH or LOW Pn to CP
Setup Time, HIGH or LOW CEP or CET to CP
Hold Time, HIGH or LOW CEP or CET to CP
Setup Time, HIGH or LOW PEtoCP
Hold Time, HIGH or LOW PE to CP
Setup Time, HIGH or LOW U/DtoCP
Hold Time, HIGH or LOW U/Dto CP
Setup Time, HIGH or LOW SR toCP
Hold Time, HIGH or LOW SR toCP
CP Pulse Width, HIGH or LOW
MR Pulse Width, LOW
MR Recovery Time
74F
TA= +25�C Vee~ +s.ov
Min
Max
4.0 4.0
3.0 3.0
7.0 5.0
0 0.5
8.0 8.0
0.0 0
11.0 7.0
0 0
10.5 8.5
0 0
4.0 7.0
4.5
6.0
54F
TA, Vee= Mil
Min
Max
74F
TA, Vee= Com
Min
4.5 4.5
3.5 3.5
8.0 6.5
0 0.5
9.0 9.0
1.0 0
12.5 8.5
0 0
11.0 9.5
0 0
4.5 8.0
6.0
8.0
Max
Units Fig. No.
ns
2-6
ns
2-6
ns
2-6
ns
2-6
ns
2-6
ns
2-6
ns
2-4
ns
2-4
ns
2-6
4-484
~~SNemaitcoinoduncatolr
54F/74F573
Octal D-Type Latch with TRI-STATE� Outputs
General Description
The 'F573 is a high speed octal latch with buffered common Latch Enable (LE) and buffered common Output Enable (OE) inputs.
This device is functionally identical to the 'F373 but has different pinouts.
Features
� Inputs and outputs on opposite sides of package allowing easy interface with microprocessors
� Useful as input or output port for microprocessors � Functionally identical to 'F373 � TRI-STATE outputs for bus interfacing � Guaranteed 4000V minimum ESD protection
Ordering Code: see section 5 Logic Symbol
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
OE
Do 2 D1 3 D2 4 D3 5 D4 D5 D5 8 D1 GND 10
20 Yee
19 Oo
18 o,
17 02 16 03 15 04 14 05 13 05 12 07 11 LE
TL/F/9566-2
Pin Assignment for LCC
Ds 0s D-4 D3 Di rn:J III [�] [[] GJ
D1 []] GND r@I
LE [i) 07 !i11
05 Im
CIJD1
!1J Do ITIOE
@JYee
!IfilOo
!BJ ~ Ii]] Ii] [ID
05 04 03 02 o,
TL/F/9566-3
Unit Loading/Fan Out: See Section 2 for U.L. Definitions
Pin Names
Do-D1 LE OE
Oo-01
Description
Data Inputs Latch Enable Input (Active HIGH) TRI-STATE Output Enable Input (Active LOW) TRI-STATE Latch Outputs
54F/74F
U.L. HIGH/LOW
1.0/1.0 1.0/1.0
Input l1Hll1L Output loHlloL
20 �A/ - 0.6 mA 20 �A/-0.6 mA
1.0/1.0
20 �A/ - 0.6 mA
150/40(33.3) - 3 mA/24 mA (20 mA)
4-485
Functional Description
The 'F573 contains eight D-type latches with 3-state output buffers. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3state buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are in the bi-state mode. When OE is HIGH the buffers are in the high impedance mode but this does not interfer with entering new data into the latches.
Logic Diagram
Function Table
Inputs
OE
LE
D
L
H
H
L
H
L
L
L
x
H
x
x
H = HIGH Voltage Level
L = LOW Voltage Level X = Immaterial Oo = Value stored from previous clock cycle
Outputs
0
H L Oo
z
LE
07
TL/F/9566-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-486
Absolute Maximum Ratings (Note 1)
If MilitaryI Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to + 7.0V
Input Voltage (Note 2)
-0.5V to + 7.0V
Input Current (Note 2)
-30 mA to + 5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
-0.5VtoVee -0.5Vto +5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
ESD Last Passing Voltage (Min)
4000V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
V1H V1L Veo VoH
VoL l1H
lsv1 leEx V10 loo IJL lozH lozL los lzz leeL leez
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee 74F 5% Vee 74F5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage Test
74F
Output Leakage Circuit Current
74F
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Bus Drainage Test
Power Supply Current
Power Supply Current
54F/74F
Min Typ Max
2.0
0.8
-1.2
2.5 2.4 2.5 2.4 2.7 2.7
0.5 0.5
20.0 5.0
100 7.0
250 50
4.75
3.75
-0.6
50
-50
-60
-150
500
35
55
35
55
Units
v v v
v
v
�A
�A
�A
v
�A mA �A �A mA �A mA mA
Vee
Min
Min
Min Max Max Max 0.0 0.0 Max Max Max Max
o.ov
Max Max
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal l1N = -18 mA loH = -1 mA loH = -3 mA loH = -1 mA loH = -3 mA loH = -1 mA loH = -3 mA loL = 20mA loL = 24mA V1N = 2.7V
V1N = 7.0V
Vour =Vee
110 = 1.9 �A All Other Pins Grounded V100 = 150 mV All Other Pins Grounded V1N = 0.5V Vour = 2.7V Vour = 0.5V
Vour = ov
Vour = 5.25V Vo= LOW Vo= HIGHZ
4-487
AC Electrical Characteristics: see section 2 for waveforms and Load Configurations
Symbol
Parameter
tPLH
Propagation Delay
tPHL
Dn to On
tPLH
Propagation Delay
tPHL
LE to On
tpzH
Output Enable Time
tpzL
tpHz
Output Disable Time
tpLz
74F
TA= +25�C Vee= +5.0V
CL= 50 pf
Min
Typ
Max
3.0
5.3
7.0
2.0
3.7
6.0
5.0
9.0
11.0
3.0
5.2
7.0
2.0
5.0
8.0
2.0
5.6
8.5
1.5
4.5
5.5
1.5
3.8
5.5
54F
TA, Vee= Mil CL= 50 pf
Min
Max
3.0
9.0
2.0
7.0
5.0
13.5
3.0
7.5
2.0
10.0
2.0
10.0
1.5
7.0
1.5
5.5
74F
TA, Vee= Com CL= 50 pf
Min
Max
3.0
8.0
2.0
6.5
5.0
12.0
3.0
7.0
2.0
9.0
2.0
9.5
1.5
6.5
1.5
5.5
Fig. Units
No.
ns
2-3
ns
2-3
ns
2-5
AC Operating Requirements: See section 2 for Waveforms
Symbol
Parameter
t8 (H) t5 (L)
th(H) th(L)
tw(H)
Setup Time, HIGH or LOW Dn to LE
Hold Time, HIGH or LOW Dn to LE
LE Pulse Width, HIGH
74F
TA= +25�C Vee= +5.0V
Min
Max
2.0 2.0
3.0 3.5
4.0
54F
TA, Vee= Mil
Min
Max
2.0 2.0
3.0 4.0
4.0
74F
TA, Vee= Com
Min
Max
2.0 2.0
3.0 3.5
4.0
Fig. Units No.
ns
2-6
ns
2-4
4-488
U~NaStemiicoonnduactlor
54F/74F574 Octal D-Type Flip-Flop with TRI-STATE� Outputs
General Description
The 'F574 is a high-speed, low power octal flip-flop with a buffered common Clock (CP) and a buffered common Output Enable (OE). The information presented to the D inputs is stored in the flip-flops on the LOW-to-HIGH Clock (CP) transition.
This device is functionally identical to the 'F374 except for the pinouts.
Features
� Inputs and outputs on opposite sides of package allowing easy interface with microprocessors
� Useful as input or output port for microprocessors � Functionally identical to 'F374 � TRI-STATE outputs for bus-oriented applications
Ordering Code: See Section 5 Logic Symbols
Do D1 D2 D3 D4 D5 D5 D7 CP
OE
TL/F/9567-1
IEEE/I EC OE
CP
Do
Do
D1
01
D2
02
D3
03
D4
04
D5
05
D5
05
0,
07
TL/F/9567-4
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
OE 1
Do 2 o, 3 D2 4 03 5 D-4 6 D5 7 D5 8
0,
GND 10
20 Yee
19 Do 18 o, 17 02 16 03 15 04 14 05 13 05 12 07 11 CP
Pin Assignment for LCC
oDo5
mDs [D[4)
D3
ill
r0ni
0, [[]
GND [QI CP [j)
07 ff1l 05 !Lll
rno,
moo
OJOE
~Yee [j])Oo
li])~[j][j]ij]]
05 04 03 02 o,
TL/F/9567-3
TL/F/9567-2
Unit Loading/Fan Out: See Section 2 for U.L. definitions
Pin Names
Do-D1 CP OE Oo-01
Description
Data Inputs Clock Pulse Input (Active LOW) TRI-STATE Output Enable Input (Active LOW) TRI-STATE Outputs
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loHllOL
1.0/1.0 1.0/1.0 1.0/1.0 150/40 (33.3)
20 �A/ - 0.6 mA 20 �A/ -0.6 mA 20 �Al -0.6 mA -3 mA/24 mA (20 mA)
4-489
Functional Description
The 'F574 consists of eight edge-triggered flip-flops with individual D-type inputs and TRI-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold times requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flipflops are available at the outputs. When OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops.
Logic Diagram
Function Table
Inputs
OE CP D
H HL H HH
H ...r L H ...r H L ...r L L ...r H
L HL L HH
Internal
Q
NC NC L H L H NC NC
Outputs
0
z z
i.
z
L H NC NC
Function
Hold Hold Load Load Data Available Data Available No Change in Data No Change in Data
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance .../" = LOW-to-HIGH Transition NC = No Change
TL/F/9567 - 5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-490
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�c
Ambient Temperature under Bias Junction Temperature under Bias
- 55�C to + 125�C
-55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to + 7.0V
Input Voltage (Note 2)
-0.5V to+ 7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee= OV) Standard Output TRI-STATE Output
-0.5VtoVee -0.5Vto +5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�cto +70�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
V1H V1L Veo VoH
Vol l1H lsv1 leEX V10 loo l1L lozH lozL los lzz leez
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee 74F5% Vee 74F5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage 74F
Test
Output Leakage
Circuit Current
74F
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Bus Drainage Test
Power Supply Current
54F/74F Min Typ Max
2.0
0.8 -1.2
2.5 2.4 2.5 2.4 2.7 2.7
0.5 0.5
20.0 5.0 100 7.0
250 50
4.75
3.75
-0.6
50
-50
-60
-150
500
55
86
Units
v v v
v
v
�A
�A
�A
v
�A mA �A �A mA �A mA
Vee
Min
Min
Min Max Max Max 0.0 0.0 Max Max Max Max
o.ov
Max
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal l1N = -18 mA loH = -1 mA loH = -3mA loH = -1 mA loH = -3mA loH = -1 mA loH = -3mA loL = 20 mA loL = 24 mA V1N = 2.7V
V1N = 7.0V
Your= Vee
Im= 1.9 �A All Other Pins Grounded V100 = 150mV All Other Pins Grounded V1N = 0.5V Vour = 2.7V Vour = 0.5V
Your= ov
Your= 5.25V Vo= HIGHZ
4-491
AC Electrical Characteristics: see Section 2 for waveforms and Load Configurations
74F
54F
74F
Symbol
Parameter
fmax
1PLH 1PHL
tpzH tpzL
tpHz tpLZ
Maximum Clock Frequency Propagation Delay CPto On Output Enable Time
Output Disable Time
TA= +25�c Vee= +5.0V
CL= 50pF
Min
Typ
Max
100
2.5
5.3
8.5
2.5
5.3
8.5
3.0
5.5
9.0
3.0
6.0
9.0
1.5
3.3
5.5
1.5
2.8
5.5
TA, Vee= Mil CL= 50pF
Min
Max
60
2.5
9.5
2.5
9.5
2.5
10.5
2.5
10.5
1.5
7.0
1.5
7.0
TA, Vee= Com CL= 50pF
Min
Max
70
2.5
8.5
2.5
8.5
2.5
10.0
2.5
10.0
1.5
6.5
1.5
6.5
Units Fig. No.
MHz 2-1 ns 2-3
ns 2-5
AC Operating Requirements: See Section 2 for Waveforms
Symbol
Parameter
t8(H) t5 (L)
th(H) th(L)
tw(H) tw(L)
Set-up Time, HIGH or LOW Dn toCP
Hold Time, HIGH or LOW Dn toCP
CP Pulse Width HIGH or LOW
74F
TA= +25�c Vee= +5.0V
Min
Max
2.5 2.0
2.0 2.0
5.0 5.0
54F
TA, Vee= Mil
Min
Max
3.0 2.5
2.0 2.0
5.0 5.0
74F
TA, Vee= Com
Min
Max
2.5 2.0
2.0 2.0
5.0 5.0
Fig. Units No.
ns 2-6 ns 2-4
4-492
D~NaStemiicoonnduactlor
ADVANCE INFORMATION
54F/74F579
8-Bit Bidirectional Binary Counter with TRI-STATE� Outputs
General Description
The 'F579 is a fully synchronous 8-stage up/down counter with multiplexed TRI-STATE 1/0 ports for bus-oriented applications. It features a preset capability for programmable operation, carry lookahead for easy cascading and a U/D input to control the direction of counting. All state changes, whether in counting or parallel loading, are initiated by the rising edge of the clock.
Features
� Multiplexed TRI-STATE 1/0 ports � Built-in lookahead carry capability � Count frequency 100 MHz typ � Supply current 75 mA typ
Logic Symbols
Connection Diagrams
TC TL/F/9568-1
IEEE/I EC
SR
cs
M2(LOAO)
PE
i5E
ENl
U/5
ca w
CP
iiR
(1) ~'.;'.;'.!'v
(2) (4) (8) (16) (l2) (64) (128)
3,5,60 8CT=Z56 3,5,6,BCT=O
l/Oo 1/01 I/Oz 1/03 1/04 1/05 1/05 1/07 TC
TL/F/9568-4
Pin Assignment for DIP, SOIC and Flatpak
CP
l/Oo 1/01 l I/Oz 4 1/03 5 GNO 6
1/04 1/05 1/05 9 1/07 10
20 iiR
19 SR
18 w 17 ca
16 Vee 15 TC 14 U/5
1l PE
12 cs
11 i5E
TL/F/9568-2
Pin Assignment for LCC
mmmrnm I/Oz 1/01l/Oo CP ii�R
l~~~~o~;
1/04 [j]
l/051i1J 1/06 ff]
[I)CEi ~Ver, [fil TC
IBJ!Ifil[j])[ZJ[j])
I/~ Of cs PE U/5
TL/F/9568-3
4-493
Nco
i.n ~National
D Semiconductor
54F/74F582
4-Bit BCD Arithmetic Logic Unit
General Description
The 'F582 is a 24-pin expandable Arithmetic Logic Unit (ALU) that performs two arithmetic operations (A plus B, A minus B), compare (A equals B), and binary to BCD conversion. In addition to a ripple carry output, carry Propagate (P) and Generate (G) outputs are provided for use with the 'F182 carry lookahead generator for high-speed expansion to higher decades. It is functionally equivalent to the 82S82.
Features
� Performs four BCD functions � P and G outputs for high-speed expansion � Add/subtract delay 22 ns max � Lookahead delay 15.5 ns max � Supply current 80 mA max � 24-Lead 300 mil slim package
Ordering Code: see section 5
Logic Symbols
Connection Diagrams
Ao Bo A1 a, A2 82 A3 83
A/S
C/Bn+4
A=B
G C/Bn
Fo r, F2 F3
TL/F /9569-1
IEEE/IEC
ALU
(BCD)
A/S EN
CO/BO
c/iin+4
A=B
c/ii
G
Pin Assignment for DIP, SOIC and Flatpak
B2
A/S
B3 3 A3 c/ii
c/iin+4 8 NC 9
A=B 10 NC 11
GND 12
24 Vee 23 NC 22 Bl 21 A2 20 A1
19 Ao
18 Bo 17 Fo
16 r,
15 NC 14 F3 13 F2
TL/F/9569-2
A=B@ NCI!]
GNO[ii]
NCIJ]]
F3@
r,1!21
NC[!fil
Pin Assignment for LCC
mm mm NC C/Bn+4 P NC G C/Bn A3
[]] IIQl
0
IIJB3
[I] A/S me2
[I)Ne ~Vee [ll]Ne ~81
~~m:J[ll]~~~ F2 Fo Bo NC Ao A1 A2
TL/F/9569-3
Ao
Bo
Al
P1
Bl o,
A2
P2
B2
02
A3
P3
B3
03
Fo
r,
F2 F3 TL/F/9569-5
4-494
01
co
Unit Loading/Fan Out: See Section 2 for U.L. definitions
I\)
Pin Names
Description
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loHllOL
Ao-A3 Bo B1 B2 B3 Fo-F3 A=B
p G
C/B
C/Bn+4 A/S
A Operand Inputs B Operand Input B Operand Input B Operand Input B Operand Input Functional Outputs Comparator Output Carry Propagate Output Carry Generate Output Carry/Borrow Input Carry/Borrow Output Add/Subtract
1.0/2.0 1.0/1.0 1.0/5.0 1.0/3.0 1.0/2.0 50/33.3 OC*/33.3 50/33.3 50/33.3 1.0/1.0 50/33.3 1.0/3.0
20 �Al-1.2 mA 20 �A/-0.6 mA 20 �A/-3 mA 20 �A/-1.8 mA 20 �A/-1.2 mA -1 mA/20 mA
*/20 mA -1 mA/20 mA -1 mA/20 mA 20 �A/ - 0.6 mA -1 mA/20 mA 20 �A/-1.8 mA
'OC-Open Collector
Functional Description
The 'F582 Binary Coded Decimal (BCD) Arithmetic Logic Unit (ALU) is a 24-pin expandable unit that performs addition, subtraction, comparison of two numbers, and binary to BCD conversion.
The 'F582's input and output logic includes a Carry/Borrow which is generated internally in the lookahead mode, allowing BCD arithmetic to be computed directly. For more than one BCD decade, the Carry/Borrow term may ripple between 'F582s.
When A/S is LOW, BCD addition is performed (A + B +
C/B = F). If the sum is greater than 9, binary to BCD conversion results at the output.
When A/S is HIGH, subtraction is performed. If the C/B is LOW, then the subtraction is accomplished by internally
computing the 9s complement addition of two BCD numbers (A-B-1 = F). When C/B is HIGH, the difference of the two numbers is figured as A- B = F. For A greater than or equal to B, the BCD difference appears at the output F in its true form. If A is less than B and C/B is HIGH, the difference appears at the output as the 1Os complement of the true form. If A is less than B and C/B is LOW, the 9s complement of the true form appears at the output F. As long as A is less than B, and Active LOW borrow is also generated.
The 'F582 also performs binary to BCD conversion. For inputs between 10 and 15, binary to BCD conversion occurs by grounding the B inputs and applying the binary number to the other set of inputs. This will generate a carry term to the next decade.
Logic Diagram
Ao-----1---~
A/S
Bo---+-1---11.~
A=B
4-495
TL/F/9569-4
cN o
Lt) Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
-55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to + 7.0V
Input Voltage (Note 2)
-0.5Vto +7.0V
Input Current (Note 2)
- 30 mA to + 5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
- 0.5V to Vcc -0.5Vto +5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Vco VoH VoL
lsv1 lcEX
loo
los loHC Ice
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 74F 10% Vee 74F5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage
74F
Test
Output Leakage 74F
Circuit Current
Input LOW Current
Output Short-Circuit Current Open Collector, Output OFF Leakage Test Power Supply Current
54F/74F Min Typ Max 2.0
0.8 -1.2 2.5 2.5 2.7 0.5 0.5 20.0 5.0 100 7.0 250
50
4.75
Units
v
v
v
v
v
�A �A �A
v
3.75 �A
-0.6 -1.2
mA -1.8 -3.0
-60
-150 mA
250
�A
50
80
mA
Vee
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal Min l1N = -18 mA
loH = -1 mA (Fn. P, G, C/Bn +4) Min loH = -1 mA (Fn. P, G, C/Bn +4)
loH = -1 mA (Fn, P, G, C/Bn +4)
Min loL = 20 mA loL = 20 mA
Max V1N = 2.7V
Max V1N = 7.0V
Max VouT =Vee
0.0 110 = 1.9 �A
All Other Pins Grounded 0.0 V100 = 150 mV
All Other Pins Grounded V1N = 0.5V (Bo, C/B) Max V1N = 0.5V (An, B3) V1N = 0.5V (A/S, B2) V1N = 0.5V (B1)
Max VouT = OV (Fn. P, G, C/Bn + 4)
Min VouT = Vcc(A=B)
Max Vo= LOW
4-496
AC Operating Requirements: see section 2 for Waveforms
74F
54F
Symbol
Parameter
tPLH tPHL
tPLH tPHL
tPLH tPHL
tPLH tPHL
tPLH tPHL
tPLH tPHL
tPLH tPHL
Propagation Delay An or Bn to Fn
Propagation Delay An or Bn to C/Bn+4
Propagation Delay C/Bn to C/Bn + 4
Propagation Delay AnorBntoA = B
Propagation Delay
An or Bn to G or P
Propagation Delay A/Sto Fn
Propagation Delay C/B to Fn
TA= +25�C Vee= +5.0V
Min
Max
2.5
29.0
2.5
22.0
4.0
21.5
4.0
16.0
3.5
8.5
2.0
6.5
8.0
35.0
6.0
25.0
4.0
18.0
3.5
15.5
2.5
33.0
7.0
18.0
4.0
21.0
2.5
14.0
TA, Vee= Mil
Min
Max
74F
TA, Vee= Com
Min
Max
2.5
31.0
2.5
23.0
4.0
24.0
4.0
17.5
3.0
9.5
2.0
7.0
7.5
28.5
5.5
24.5
4.0
19.0
3.5
16.5
2.5
34.0
6.5
19.5
3.5
23.0
2.5
15.5
Uco1
N
Units
Fig. No.
ns
2-3
ns
2-3
ns
2-3
ns
2-3
ns
2-3
ns
2-3
ns
2-3
4-497
U~NaStemiicoonnduactlor
54F/74F583
4-Bit BCD Adder
General Description
The 'F583 high-speed 4-bit, BCD full adder with internal carry lookahead accepts two 4-bit decimal numbers (Ao-A3, Bo-83) and a Carry Input (Cn). It generates the decimal sum outputs (So-S3), and a Carry Output (Cn+ 4) if the sum is greater than 9. The 'F583 is the functional equivalent of the 82S83.
Features
� Adds two decimal numbers � Full internal lookahead � Fast ripple carry for economical expansion � Sum output delay time 16.5 ns max � Ripple carry delay time 8.5 ns max � Input to ripple delay time 14.0 ns max � Supply current 60 mA max � Available in SOIC, (300 mil only)
Ordering Code: see section 5
Logic Symbols
Connection Diagrams
Ao Bo A1 B1 A2 B2 A3 B3
en
Cn+4
So s, Sz S3
TL/F/9570-1
IEEE/I EC
}Ao
A1 A2 A3
Bo B1 Bz
}
B3
2:(BCD)
{
So S1 S3
S2
Pin Assignment for DIP, SOIC and Flatpak
B1 B2 B3 A3 en Cnu S2 GND
16 Yee 15 A2 14 A1 13 Ao 12 Bo 11 So 10 S1 9 S3
TL/F /9570-2
Pin Assignment for LCC
Cn+4 ~ NC A5 B3
[]] mmmm
S2 [[J GND [QJ
NC [j]
S3 ll1.l
S1 !!]
!IIB2 mB1 [JJNC ~Vee
li]]A2
~ [�)lffil lilll!ID So Bo NC Ao A1
TL/F/9570-3
en Cl
co en+4
TL/F/9570-4
Unit Loading/Fan Out: See Section 2 for u.L. Definitions
Pin Names
Ao-A3 Bo-83 Cn So-S3 Cn+4
Description
A Operand Inputs B Operand Inputs Carry Input Sum Outputs Carry Output
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loHllOL
1.0/2.0 1.0/2.0 1.0/1.0 50/33.3 50/33.3
20 �Al -1.2 mA 20 �A/-1.2 mA 20 �A/-0.6 mA -1 mA/20 mA -1 mA/20 mA
4-498
Functional Description
The 'F583 4-bit binary coded (BCD) full adder performs the addition of two decimal numbers (Ao-A3, Bo-B3). The lookahead generates the BCD carry terms internally, allowing the 'F583 to then do BCD addition correctly. For BCD num-
bers a� through 9 at A and B inputs, the BCD sum forms at
the output. In the addition of two BCD numbers totalling a number greater than 9, a valid BCD number and a carry will result.
Logic Diagram
For input values larger than 9, the number is converted from binary to BCD. Binary to BCD conversion occurs by grounding one set of inputs, An or Bn. and applying any 4-bit binary number to the other set of inputs. If the input is between O and 9, a BCD number occurs at the output. If the binary input falls between 10 and 15, a carry term is generated. Both the carry term and the sum are the BCD equivalent of the binary input. Converting binary numbers greater than 16 may be achieved through cascading 'F583s.
...-----------D-so
Ao~--+lL.)"1+---tt
S1
81---.il ~JO+---, T1ir==1f=t=;::T$$~0
A1---~
82----..,.=r'D..--~::t:t::=:al$$=a=J
Az-----.i1-t_.,,;
83---+--f
TL/F/9570-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-499
cCof)
Lt> Absolute Maximum Ratings (Note 1)
If MilitaryI Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
-65�C to+ 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vcc Pin Potential to Ground Pin
-0.5Vto +7.0V
Input Voltage (Note 2)
-0.5V to+ 7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5V to Vee -0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C
o�cto +1o�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
V1H
Input HIGH Voltage
V1L
Input LOW Voltage
Vco
Input Clamp Diode Voltage
54F/74F Min Typ Max
Units Vee
Conditions
2.0
v
Recognized as a HIGH Signal
0.8
v
Recognized as a LOW Signal
-1.2
v
Min l1N = -18 mA
VoH
Output HIGH
54F 10% Vee 2.5
Voltage
74F 10% Vee 2.5
74F 5% Vee
2.7
loH = -1 mA
v
Min loH = -1 mA
loH = -1 mA
VoL
Output LOW
54F 10% Vee
Voltage
74F 10% Vee
0.5
v
Min loL = 20 mA
0.5
loL = 20 mA
l1H
Input HIGH Current
20
�A
Max V1N = 2.7V
lsv1
Input HIGH Current
Breakdown Test
100
�A
Max V1N = 7.0V
l1L
Input LOW Current
las
Output Short-Circuit Current
-60
-0.6
V1N = 0.5V (Cn)
-1.2
mA
Max V1N = 0.5V (An, Bn)
-150
mA
Max Vour = ov
le EX
Output HIGH Leakage Current
250
�A
Max Vour =Vee
lccL
Power Supply Current
40
60
mA
Max Vo= LOW
4-500
AC Electrical Characteristics: See Section 2 tor Waveforms and Load Configurations
Symbol
Parameter
tPLH tPHL
tPLH tPHL
tpLH tPHL
Propagation Delay An or Bn to Sn
Propagation Delay Cn toCn+4 Propagation Delay An or Bn to Cn+4
74F
TA= +25�C Vee= +5.0V
CL= 50 pf
Min
Typ
Max
2.5
13.0
16.5
2.5
11.0
14.0
2.5
6.5
8.5
2.5
5.0
6.5
4.0
11.0
14.0
4.0
8.0
10.5
54F
TA, Vee= Mil CL= 50 pf
Min
Max
2.5
20.5
2.5
19.0
2.5
10.5
2.5
8.5
4.0
19.5
4.0
13.5
74F
TA, Vee= Com CL= 50 pf
Min
Max
2.5
17.5
2.5
15.0
2.5
9.5
2.5
7.5
4.0
15.0
4.0
11.5
U1
CwX>
Fig. Units No.
ns
2-3
ns
2-3
ns
2-3
I
4-501
co co
LC) ~National
U Semiconductor
54F/74F588 Octal Bidirectional Transceiver with TRI-STATE� Inputs/Outputs and IEEE-488 Termination Resistors
General Description
The 'F588 contains eight non-inverting bidirectional buffers with TRI-STATE outputs and is intended for bus-oriented applications. The B ports have termination resistors as specified in the IEEE-488 specifications. Current sinking capability is 24 mA (20 mA Mil) at the A ports and 64 mA (48 mA Mil) at the B ports. The Transmit/Receive (T/R) input determines the direction of data flow through the bidirectional transceiver. Transmit (active HIGH) enables data from A ports to B ports; Receive (active LOW) enables
data from B ports to A ports. The Output Enable input, when HIGH, disables both A and B ports by placing them in a high impedance condition.
Features
� Non-inverting buffers � Bidirectional data path � B outputs sink 64 mA (48 mA Mil), source 12 mA � Guaranteed 4000V minimum ESD protection
Ordering Code: see section 5 Logic Symbols
Ao A1 A2 A3 A4 As As A1 OE
T/R
Bo B1 B2 B3 B4 Bs Bs B1
TL/F/9571-2
IEEE/I EC
6E T/R
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
Ao A1 2 A2 3 A3 4 A4 5 As 6 As A1 8
OE
GND 10
20 Yee
19 Bo 18 B1 17 B2 16 B3 15 B4 14 Bs 13 Bs 12 B1
11 T/ii
TL/F/9571-3
Pin Assignment for LCC
A1 As As A4 A3 rn m[]] rn m
OE[[)
GND [QI
T/R [j]]
B1~
Bs lill
LlJA2
rnA1
DJ Ao
~Yee [i]]Bo
IJ][j]]IJ][ZJ[j]I
Bs B4 B3 8i B1
TL/F/9571-4
Ao
Bo
A1
B1
A2
B2
A2
B2
A3
B3
A4
84
As
8s
As
85
A1
87
TL/F/9571-1
4-502
U1
CX>
Unit Loading/Fan Out: See Section 2 tor U.L. definitions
CX>
Pin Names
Description
OE T/R Ao-A7
Bo-B7
Output Enable Input (Active LOW) Transmit/Receive Control Input A Port Inputs or TRI-STATE Outputs B Port Inputs or TRI-STATE Outputs
�r = Resistive Termination per IEEE-488 Standard
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loHlloL
1.0/2.0 1.0/2.0 3.5/1.083 150/40 (33.3) *T /5.33 600/106.6 (80)
20 �Al -1.2 mA 20 �Al-1.2 mA 70 �A/ - 0.65 mA - 3 mA/24 mA (20 mA)
*T/3.2 mA -12 mA/64 mA (48 mA)
Truth Table
Inputs
OE
T/R
L
L
L
H
H
x
Outputs
Bus B Data to Bus A Bus A Data to Bus B High Impedance
Logic Diagram
TL/F/9571-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
B Port Input Characteristic with T/R LOW
4-503
TL/F/9571-6
ccoo
i.n Absolute Maximum Ratings (Note 1)
If MilitaryI Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5Vto +7.0V
Input Voltage (Note 2)
-0.5Vto +7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
-0.5VtoVee -0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
ESD Last Passing Voltage (Min)
4000V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�c 0�Cto +70�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol V1H V1L Yeo VoH
VoL
l1H l1H + lozH
l1L +
lozL VNL lsv1 lsv1T
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee 74F 10% Vee 74F5% Vee 74F5% Vee
Output LOW Voltage
54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee
Input HIGH Current
l1H IEEE-488
l1L IEEE-488
No Load Voltage
Input HIGH Current Breakdown Test
Input HIGH Current Breakdown Test (1/0)
54F/74F
Min Typ Max
2.0
0.8
-1.2
2.5 2.4 2.0 2.5 2.4 2.0 2.7 2.7
0.5 0.55 0.5 0.55
20
700 2.5
-1.3
-3.2
2.5 3.7
100
1.0
Units Vee
v
v
v
Min
v
Min
v
Min
�A
Max
�A
4.75
mA
5.25
4.75 mA
5.25
v
4.75
5.25
�A
Max
mA
Max
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal l1N = -18 mA (OE, T/R) loH = -1 mA (An) loH = - 3 mA (An. Bn) loH = -12 mA (Bn) loH = -1 mA (An) loH = - 3 mA (An. Bn) loH = -15 mA (Bn) loH = -1 mA(An) loH = - 3 mA (An. Bn) loL = 20 mA (An) loL = 48 mA (Bn) loL = 24 mA (An) loL = 64 mA (Bn) V1N = 2.7V (OE, T/R) V1N = 5.0V (Bn) V1N = 5.5V (Bn) V1N = 0.4V (Bn) V1N = 0.4V (Bn) l1N = OV (Bn) l1N = OV (Bn) V1N = 7.0V (OE, T/R)
V1N = 5.5V (An)
4-504
(J1
ClO
DC Electrical Characteristics (Continued)
ClO
Symbol
Parameter
l1L l1H + lozH l1L + lozL los
Input LOW Current Output Leakage Current Output Leakage Current Output Short-Circuit Current
leEX lzz leeH leeL leez
Output HIGH Leakage Current Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current
54F/74F
Min Typ Max
-1.2
70
-650
-60 -100
-150 -225
250
500
67
100
90
135
83
125
Units
mA �A �A
mA
�A �A mA mA mA
Vee
Max Max Max
Max
Max
o.ov
Max Max Max
Conditions
V1N = 0.5V (OE, T/A) Vour = 2.7V (An) Vour = 0.5V (An) Vour = OV (An) Vour = OV (Bn) Vour =Vee (An) Vour = 5.25V (An. Bn) Vo= HIGH Vo= LOW Vo= HIGHZ
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
74F
54F
74F
Symbol
Parameter
tPLH tPHL
tpzH tpzL
tpHz tpLZ
Propagation Delay A to B orBtoA
Output Enable Time T/A or OE to A or B
Output Disable Time T/A or OE to A or B
TA= +25�C Vee= +5.0V
CL= 50pF
Min
Typ
Max
2.5
4.5
6.0
2.5
5.0
6.5
2.5
5.0
7.0
2.5
7.0
9.0
2.5
5.5
7.0
2.5
5.5
7.0
TA, Vee= Mil CL= 50 pF
Min
Max
TA, Vee= Com CL= 50 pF
Min
Max
2.5
7.0
2.5
7.5
2.5
8.0
2.5
10.0
2.5
8.0
2.5
8.0
Fig. Units
No.
ns
2-3
ns
2-5
4-505
(")
N
<D
�
~National
0 N <D
~Semiconductor
54F/74F620 � 54F/74F623
Inverting Octal Bus Transceiver with TRI-STATE� Outputs
General Description
These devices are octal bus transceivers designed for asynchronous two-way data flow between the A and B busses. Both busses are capable of sinking 64 mA and have TRISTATE outputs. Dual enable pins (GAB, GBA) allow data transmission from the A bus to the B bus or from the B bus to the A bus. The 'F620 is an inverting option of the 'F623.
Features
� Designed for asynchronous two-way data flow between busses
� Outputs sink 64 mA � Dual enable inputs control direction of data flow � Guaranteed 4000V minimum ESD protection � 'F620 is an inverting option of the 'F623
Ordering Code: see Sections Logic Symbol
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
GBA GAB
TL/F/9577-3
Unit Loading/Fan Out: See Section 2 for u.L. definitions
Pin Names
GBA,GAB Ao-A7 Bo-87
Description
Enable Inputs A Inputs or TRI-STATE Outputs B Inputs or TRI-STATE Outputs
54F/74F
U.L. HIGH/LOW
Input l1HlllL Output loHllOL
1.0/1.0 3.5/1.083 150/40 (33.3) 3.5/1.083 150/40 (33.3)
20 �A/-0.6 mA 70 �Al - 0.4 mA -3 mA/64 mA (48 mA) 70 �A/-0.4 mA -3 mA/64 mA (48 mA)
GAB
Ao
At
A2 A3 5 A4 6 As
A6 a
A1 GND 10
20 Vee 19 G8A 18 Bo 17 B1 16 B2 15 B3 14 84 13 85 12 B6 11 87
TL/F /9577-1
Pin Assignment for LCC
As
oo
mAs !AI4l
rAn3
mA2
A1 [[I GND [QI
B1 (j]
Bs 1!11
Bs Ii]
l1JA1
llJAo
[j]GAB
Im Vee l!ID GBA
~[�][�Jfill[i]!
B4 B3 B2 Bl Bo
TL/F/9577-2
4-506
Functional Description
The enable inputs GAB and GBA control whether data is transmitted from the A bus to the B bus or from the B bus to the A bus. If both GBA and GAB are disabled (GBA HIGH and GAB low), the outputs are in the high impedance state and data is stored at the A and B busses. When GBA is
a>
N
active (LOW), B data is sent to the A bus. When GAB is
0 �
a>
active (HIGH), data from the A bus is sent to the B bus. If
N w
both enable inputs are active (GBA LOW and GAB HIGH) B
data is sent to the A bus while A data is sent to the B bus.
Enable Inputs
GBA
GAB
L
L
H
H
H
L
L
H
H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance
Logic Diagram
Function Table
Operation
'F620
BData to A Bus
A Data to B Bus
z
BData to A Bus, A Data to B Bus
'F623
B Data to A Bus
A Data to B Bus
z
B Data to A Bus, A Data to B Bus
'F620
a,
Bz
GBA GAB
Az
A1
TL/F/9577-4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
'F623
TL/F/9577-7 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays:
4-507
Cf)
Nco
�
0
Absolute Maximum Ratings (Note 1>
If Military/Aerospace specified devices are required,
cN o
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
-55�C to+ 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to+ 7.0V
Input Voltage (Note 2)
-0.5V to + 7.0V
Input Current (Note 2)
-30 mA to + 5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
-0.5VtoVee - 0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
ESD Last Passing Voltage (Min)
4000V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Veo VoH
lsv1 lsv1T
le Ex
loo l1L l1H + lozH los lzz lceH lccL lcez lccH lceL lccz
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 74F 10% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Input HIGH Current 54F
Breakdown (110)
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage 74F
Test
Output Leakage 74F
Circuit Current
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Bus Drainage Test
Power Supply Current ('F620)
Power Supply Current ('F620)
Power Supply Current ('F620)
Power Supply Current ('F623)
Power Supply Current ('F623)
Power Supply Current ('F623)
54F/74F Min Typ Max 2.0
0.8 -1.2 2.0 2.0 0.55 0.55 20.0 5.0 100 7.0 1.0 0.5 250
50
4.75
-100
3.75
-0.6 70
-650 -225 500
82 82 95 65 82 85
Units
v v v v
v
�A
�A
mA
�A
v
�A
mA
�A �A
mA
�A
mA mA mA mA mA mA
Vee
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal Min l1N = -18 mA (Non 1/0 Pins) Min loH = -12 mA (An, Bn) loH = -15 mA (An. Bn) Min loL = 48 mA (An. Bn) loL = 64 mA (An. Bn)
Max V1N = 2.7V
Max ~IN = 7.0V (GBA, GAB)
Max
Max VouT =Vee
0.0
0.0
Max Max Max Max o.ov Max Max Max Max Max Max
110 = 1.9 �A
All Other Pins Grounded V100 = 150 mV All Other Pins Grounded V1N = 0.5V (Non 110 Pins) VouT = 2.7V (An, Bn) VouT = 0.5V (An. Bn) VouT =av VouT = 5.25V Vo = HIGH, V1N = 0.2V Vo= LOW
z Vo = HIGH
Vo= HIGH Vo = LOW, V1N = 0.2V
z Vo = HIGH
4-508
O'>
I\)
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
0
�
74F
54F
74F
O'>
I\)
w
Symbol
Parameter
TA= +25�C Vee= +5.0V
CL= 50 pF
TA, Vee= Mil CL= 50 pF
TA, Vee= Com Units Fig.
CL= 50 pF
No.
Min
Typ
Max
Min
Max
Min
Max
tPLH
Propagation Delay
2.5
7.5
tPHL
A Input to B Output ('F620)
2.0
7.0
2.0
8.0
ns 2-3
2.0
7.0
tPLH
Propagation Delay
2.5
7.5
tPHL
B Input to A Output ('F620)
2.0
7.0
2.0
8.0
ns 2-3
2.0
7.0
tPLH
Propagation Delay
1.5
6.5
tPHL
A Input to B Output ('F623)
2.0
7.0
1.5
7.5
2.0
7.5
ns 2-3
tPLH
Propagation Delay
1.5
6.5
tPHL
B Input to A Output ('F623)
2.0
7.0
1.5
7.5
ns 2-3
2.0
7.5
tpzH
Enable Time
2.0
7.0
tpzL
GBA Input to A Output
2.5
8.0
tpHz
Disable Time
1.5
6.5
tpLz
GBA Input to A Output
1.0
5.5
2.0
8.0
2.0
8.5
ns 2-5
1.5
7.5
1.0
5.5
tpzH
Enable Time
2.0
7.5
tpzL
GAB Input to B Output ('F620) 3.0
8.0
tpHz
Disable Time
2.5
8.0
tpLz
GAB Input to B Output ('F620) 2.0
7.5
2.0
8.5
2.0
8.5
ns 2-5
2.0
9.0
2.0
8.0
tpzH
Enable Time
2.0
7.5
tpzL
GAB Input to B Output ('F623) 2.5
8.0
tpHz
Disable Time
2.0
8.0
tpLz
GAB Input to B Output ('F623)
2.0
8.0
2.0
8.5
2.0
8.5
ns 2-5
2.0
9.0
2.0
8.0
4-509
~National
~Semiconductor
54F/74F632 32-Bit Parallel Error Detection and Correction Circuit
General Description
The 'F632 device is a 32-bit parallel error detection and correction circuit (EDAC) in a 52-pin or 68-pin package. The EDAC uses a modified Hamming code to generate a 7-bit check word from a 32-bit data word. This check word is stored along with the data word during the memory write cycle. During the memory read cycle, the 39-bit words from memory are processed by the EDAC to determine if errors have occurred in memory.
Single-bit errors in the 32-bit data word are flagged and corrected.
Single-bit errors in the 7-bit check word are flagged, and the CPU sends the EDAC through the correction cycle even though the 32-bit data word is not in error. The correction cycle will simply pass along the original 32-bit data word in this case and produce error syndrome bits to pinpoint the error-generating location.
Dual-bit errors are flagged but not corrected. These errors may occur in any two bits of the 39-bit word from memory (two errors in the 32-bit data word, two errors in the 7-bit check word, or one error in each word). The gross-error
condition of all LOWs or all HIGHs from memory will be detected. Otherwise, errors in three or more bits of the 39bit word are beyond the capabilities of these devices to detect.
Read-modify-write (byte-control) operations can be performed by using output latch enable, LEDBO, and the individual OEBo through OEB3 byte control pins.
Diagnostics are performed on the EDACs by controls and internal paths that allow the user to read the contents of the Data Bit and Check Bit input latches. These will determine if the failure occurred in memory or in the EDAC.
Features
� Detects and corrects single-bit errors � Detects and flags dual-bit errors � Built-in diagnostic capability � Fast write and read cycle processing times � Byte-write capability � Guaranteed 4000V minimum ESD protection
Ordering Code: see section 5
Logic Symbol
So S1 OECB LED BO OEBn
32 DB0-os31
CB0-CB6
MERR ERR
TL/F/9579-1
Unit Loading/Fan Out: See Section 2 for u.L. definitions
Pin Names
CB0-CB5
DB0-DB31
OEB0-0EB3 LED BO OECB So, S1 ERR MERR
Description
Check Word Bit, Input or TRI-STATE� Output Data Word Bit, Input or TR I-STATE Output Output Enable Data Bits Output Latch Enable Data Bit Output Enable Check Bit Select Pins Single Error Flag Multiple Error Flag
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loHlloL
3.5/1.083 150/40 (33.3)
3.5/1.083 150/40 (33.3)
1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 50/33.3 50/33.3
70 �A/ - 650 �A - 3 mA/24 mA (20 mA)
70 �A/ - 650 �A -3 mA/24 mA (20 mA)
20 �A/-0.6 mA 20 �A/ - 0.6 mA 20 �A/-0.6 mA 20 �A/-0.6 mA
-1 mA/20mA -1 mA/20mA
4-510
Connection Diagrams
Pin Assignment for Side Brazed DIP
LE080
MERR
ffi 3
080 4 081 5 D82 6 083 7
084 8
085 9 0Eii0 10 086 11 087 12 GNO 13 088 14
089 15 ill1 16 DB10 17 D811 18 DB12 19 DB13 20 DB14 21 DB15 22 C86 23 C85 24 CB4 25 OECB 26
52 Vee 51 S1 50 So 49 D831
.ca 0830
47 D829 46 OB2a 45 D8z7
� D825
43 0Eii3 42 0825 41 0824 40 GNO
39 D823 38 0822 37 0Eii2 36 0821 35 0820 34 D819 33 D81a 32 0817 31 0916 30 C8o 29 C81 28 C82 27 CB3
TL/F/9579-2
Pin Assignment for LCC and PCC
52-Pin
0013C812C811C81000i1OB9 OBa GNO 00, OBg OOio~ 084 ~li!Jll!lfillfill[fil[j]fill[j][j][QJ [fil(fil
D814mJ D815~
c06 � C85~ CB4 ~
OECB~
C83illJ
CB2irn
ce1[fi]
C8o~
D816rnJ
DB171llJ
DB1alnJ
[ZJOB3
III DB2
[]] 081
[IIOBo
[I)ffi (I] MERR
OJ LE080
[g]Vcc
lfilJS1 ~So ~0831 ~DB30 1�10829
IHI~ l1ID Ill.I !Thl~ HQl@l lill ~~fill~
00190Bzo0Bz100iz!Szzll8z3CH> llBz40BzsW30BzallBz10Bza
TL/F/9579-3
Pin Assignment for LCC and PCC
68-Pin
~ ~ ~ ~ ~ I~ ~ ~ ~ ~ ~ ~ I~ ~ ~ ~ ~
~~~~~~~~~~~[fil~~~~~
NC Ill) NC~
NC llfil
0815 ~
NC II!J
CB6 jg] CBS~ C84 ~ OECB ~ CB3 ~ CB2 [llJ
CBI~ C80 ~
0916 HQ! 0917 [!j]
NC lilJ
NC~
11] NC
[[)NC
lil 082
[[) 091
moeo G]ffi [I] MERR
IIJ LEOBO ITl Vee
~Vee [0 S1
flll so
~0831
IHI 0030
~ 0929 [gj NC
[!j] NC
~~~~@~~~~~~~~~~~~
~ ~ � ~ I~ ~ ~ ~ ~ ~ ~ I~ � ~ � ~ ~
NC-No internal connection
TL/F/9579-8
4-511
Functional Description
MEMORY WRITE CYCLE DETAILS
During a memory write cycle, the check bits (CBo through CBa) are generated internally in the EDAC by seven 16-input parity generators using the 32-bit data word as defined in Table II. These seven check bits are stored in memory along with the original 32-bit data word. This 32-bit word will later be used in the memory read cycle for error detection and correction.
ERROR DETECTION AND CORRECTION DETAILS
During a memory read cycle, the 7-bit check word is retrieved along with the actual data. In order to be able to determine whether the data from memory is acceptable to use as presented to the bus, the error flags must be tested to determine if they are at the HIGH level.
The first case in Table Ill represents the normal, no-error conditions. The EDAC presents HIGHs on both flags. The next two cases of single-bit errors give a HIGH on MERR and a LOW on ERR, which is the signal for a correctable error, and the EDAC should be sent through the correction cycle. The last three cases of double-bit errors will cause the EDAC to signal LOWs on both ERR and MERR, which is the interrupt indication for the CPU.
Error detection is accomplished as the 7-bit check word and the 32-bit data word from memory are applied to internal parity generators/checkers. If the parity of all seven groupings of data and check bits is correct, it is assumed that no error has occurred and both error flags will be HIGH.
Memory Cycle
EDAC Function
Control
S1
So
Write
Generate
L
L
Check Word
'See Table II for details of check bit generation.
TABLE I. Write Control Function
Data 1/0 Input
DB Control OEBn
H
DB Output Latch LED BO
x
Check 1/0
Output Check Bit*
CB Control OECB
L
Error Flags ERR MERR
H
H
TABLE II. Parity Algorithm
Check Word
32-Bit Data Word
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CBo x x x x
x xxx
x
x xxxx x
x
CB1
x x x x x xxx
x x x x x xxx
CB2 x x
xx x
x x
xx x
x x x xx x
CB3
x x x
x x x
x x
x x x
x x x
x x
CB4
x x
x x x x x x
C85 x x x x x x x x
x x
x x x )( x x
x x x x x x xx
CBa x x x x x x x x
xx x x x x x x
The seven check bits are parity bits derived from the matrix of data bits as indicated by X for each bit.
TABLE Ill. Error Function
Total Number of Errors
Error Flags
32-Bit Data Word
7-Bit Check Word
ERR
MERR
0 1 0 1 2 0
H = HIGH Voltage Level L = LOW Voltage Level
0
H
H
0
L
H
1
L
H
1
L
L
0
L
L
2
L
L
Data Correction
Not Applicable Correction Correction Interrupt Interrupt Interrupt
4-512
Functional Description (Continued)
If the parity of one or more of the check groups is incorrect, an error has occurred and the proper error flag or flags will be set LOW. Any single error in the 32-bit data word will change the state of either three or five bits of the 7-bit check word. Any single error in the 7-bit check word changes the state of only that one bit. In either case, the single error flag (ERR) will be set LOW while the dual error flag (MERR) will remain HIGH.
Any 2-bit error will change the state of an even number of check bits. The 2-bit error is not correctable since the parity tree can only identify single-bit errors. Both error flags are set LOW when any 2-bit error is detected.
Three or more simultaneous bit errors can cause the EDAC to believe that no error, a correctable error, or an uncorrectable error has occurred and will produce erroneous results in all three cases. It should be noted that the gross-error conditions of all LOWs and all HIGHs will be detected.
As the corrected word is made available on the data 1/0 port (DBo through DB31 ), the check word 1/0 port (CB0 through CB6) presents a 7-bit syndrome error code. This syndrome error code can be used to locate the bad memory chip. See Table V for syndrome decoding.
READ-MODIFY-WRITE (BYTE CONTROL) OPERATIONS
The 'F632 device is capable of byte-write operations. The 39-bit word from memory must first be latched into the Data Bit and Check Bit input latches. This is easily accomplished by switching from the read and flag mode (S1 = H, So = L)
to the latch input mode (S1 = H, So = H). The EDAC will
then make any corrections, if necessary, to the data word and place it at the input of the output data latch. This data word must then be latched into the output data latch by taking LEDBO from a LOW to a HIGH.
wen
N
Byte control can now be employed on the data word through the OEBo through OEB3 controls. OEBo controls DB0-DB7 (byte 0), OEB1 controls DBa-DB1s (byte 1), OEB2 controls DB15-DB23 (byte 2), and OEB3 controls DB24 -DB31 (byte 3). Placing a HIGH on the byte control will disable the output and the user can modify the byte. If a LOW is placed on the byte control, then the original byte is allowed to pass onto the data bus unchanged. If the original data word is altered through byte control, a new check word must be generated before it is written back into memory. This is easily accomplished by taking controls S1 and So LOW. Table VI lists the read-modify-write functions.
DIAGNOSTIC OPERATIONS
The 'F632 is capable of diagnostics that allow the user to determine whether the EDAC or the memory is failing. The diagnostic function tables will help the user to see the possibilities for diagnostic control. In the diagnostic mode (S1 = L, So = H), the check word is latched into the input latch while the data input latch remains transparent. This lets the user apply various data words against a fixed known check word. If the user applies a diagnostic data word with an error in any bit location, the ERR flag should be LOW. If a diagnostic data word with two errors in any bit location is applied, the MERR flag should be LOW. After the check word is latched into the input latch, it can be verified by taking OECB LOW. This outputs the latched check word. The diagnostic data word can be latched into the output data latch and verified. By changing from the diagnostic mode (S1 = L, So = H) to the correction mode (S1 = H, So = H), the user can verify that the EDAC will correct the diagnostic data word. Also, the syndrome bits can be produced to verify that the EDAC pinpoints the error location. Table VII lists the diagnostic functions.
TABLE IV. Read, Flag and Correct Function
Memory Cycle
EDAC Function
Control S1 So
Read
Read & Flag
H
L
Read
Latch Input Data&Check Bits
H
H
Read
Output
Corrected Data
H
H
& Syndrome Bits
Note 1: See Table Ill for error description. Note 2: See Table V for error location.
Data 1/0
Input Latched Input Data Output Corrected Data Word
DB Control OEBn H H
L
DB Output Latch LED BO
x
L
x
Check 1/0
Input Latched Input Check Word Output Syndrome Bits (Note 2)
CB Control OECB
H
H
L
Error Flags ERR MERR Enabled (Note 1) Enabled (Note 1)
Enabled (Note 1)
4-513
Functional Description (Continued)
Syndrome Bits
6 5 4 3 2 1
L L L L L L L L L L L L L. L L L L H L L L L LH
L L L L HL L L L L HL L L L L HH L L L L HH
L L L HL L L L L HL L L L LHLH L LLHLH
L L L HH L
L L LHHL L L L HHH L L L HHH
L LHL L L L LHL L L L LHL LH L LHL LH
L LHLHL L LHLHL L L H L HH L LH LHH
L LHH L L L L HH L L L LHHLH L LHH LH
L LHHHL L LHHHL L LHHHH L L HHHH
TABLE V. Syndrome Decoding
Error 0
L
unc
H
2-8it
L
2-8it
H
unc
L
2-8it
H
unc
L
unc
H 2-Bit (Note 2)
L
2-8it
H
unc
L
0831
H
2-Bit
L
unc
H
2-Bit
L
2-8it
H
0830
L
2-8it
H
unc
L
0829
H
2-8it
L
082a
H
2-8it
L
2-8it
H
0827
L
0825
H
2-8it
L
2-8it
H
0825
L
2-8it
H
0824
L
unc
H
2-8it
Syndrome Bits
Error
6
5
4
3
2
1
0
L
H
L
L
L
L
L 2-8it
L
H
L
L
L
L
H unc
L
H
L
L
L
H
L 087
L
H
L
L
L
H
H 2-8it
L
H
L
L
H
L
L 085
L
H L
L
H
L
H 2-8it
L
H
L
L
H
H
L 2-8it
L
H
L
L
H H
H 085
L
H
L
H
L
L
L 084
L
H
L
H
L
L
H 2-8it
L
H
L
H
L
H
L 2-8it
L
H
L
H
L
H
H 083
L
H
L
H
H
L
L 2-8it
L
H
L
H
H
L
H 082
L
H
L
H
H
H
L
unc
L
H
L
H
H
H
H 2-8it
L
H
H
L
L
L
L 080
L
H
H
L
L
L
H 2-8it
L
H H
L
L
H
L 2-8it
L
H
H
L
L
H
H
unc
L
H
H
L
H
L
L 2-8it
L
H
H
L
H
L
H 081
L
H H
L
H
H
L unc
L
H
H
L
H
H
H 2-8it
L
H
H
H
L
L
L 2-8it
L
H H
H
L
L
H
unc
L
H
H
H
L
H
L unc
L
H
H
H
L
H
H 2-8it
L
H
H
H
H
L
L
unc
L
H H
H
H
L
H 2-bit
L
H
H
H
H
H
L 2-bit
L
H
H
H
H
H
H C85
CBx = Error in check bit X DBy = Error in data bit Y 2-Bit = Double-bit error unc = Uncorrectable multi-bit error
Note: 2-bit and unc condition will cause both ERR and MERA to be LOW Note 1: Syndrome bits for all LOWs. MERA and ERR LOW for all LOWs, only ERR LOW for 0830 error. Note 2: Syndrome bits for all HIGHs.
4-514
Functional Description (Continued)
TABLE V. Syndrome Decoding (Continued)
Syndrome Bits
Error
6
5
4
3
2
1
0
H
L
L
L
L
L
L 2-8it
H
L
L
L
L
L
H
unc
H
L
L
L
L
H
L
unc
H
L
L
L
L
H H 2-8it
H
L
L
L
H L
L
unc
H
L
L
L
H
L
H 2-8it
H
L
L
L
H H
L 2-8it
H
L
L
L
H H H unc
H
L
L
H
L
L
L
unc
H
L
L
H
L
L
H 2-8it
H
L
L
H
L
H
L 2-8it
H
L
L
H
L
H H 0815
H
L
L
H H
L
L 2-8it
H
L
L
H
H
L
H
unc
H
L
L
H H
H
L 0814
H
L
L
H
H
H
H 2-8it
H L
H L
L
L
L
unc
H
L
H
L
L
L
H 2-8it
H
L
H
L
L
H
L 2-8it
H
L
H
L
L
H H 0813
H
L
H
L
H
L
L 2-8it
H
L
H
L
H
L
H 0812
H
L
H
L
H
H
L 0811
H L H L H H H 2-8it
H
L
H H
L
L
L 2-8it
H
L
H H
L
L
H 0810
H
L
H
H
L
H
L 089
H L H H L H H 2-8it
H L
H H H L
L
08a
H
L
H H H
L
H 2-8it
H L H H H H L 2-8it
H L H H H H H C85
Syndrome Bits 6 5 4 3 2 10
Error
HHL L L L L HHL L L L H HH L L L HL HH L L L HH
unc 2-8it 2-8it 0823
HHL L HL L HHL L HL H HHL L HHL HH L L HHH
2-8it
0822 0821 2-8it
HHL H L L L HHL H L L H HHL H L HL HH L H L HH
2-8it
0820 0819 2-8it
HHL HH L L HH L H H L H HH L HHHL HH L H HHH
0819 2-8it 2-8it C84
HHH L L L L HHH L L L H HHH L L HL HHH L L HH
2-8it
0815 unc 2-8it
HHH L H L L HHH L HL H HHH L HHL HHH L HHH
0817 2-8it 2-8it
C83
H H H H L L L unc (Note 1)
HHHH L L H
2-8it
HHH H L HL
2-8it
HHH H L HH
C82
HHHHH L L HHHHH L H HHH H HHL HHH H HHH
2-8it
C81 C8o None
CBx = Error in check bit X
DBy = Error in data bit Y 2-Bit = Double-bit error
unc = Uncorrectable multi-bit error
Note: 2-bit and unc condition will cause both ERR and MffiR to be LOW
Note 1: Syndrome bits for all LOWs. MERA and ERR LOW for all LOWs, only ERR LOW for 0830 error. Note 2: Syndrome bits for all HIGHs.
4-515
Functional Description (Continued)
TABLE VI. Read-Modify-Write Function
Memory Cycle
EDAC Function
Read
Read & Flag
Control
S1
So
H
L
BYTEn* Input
OEBn* H
DB Output Latch LED BO
x
Check 1/0 Input
CB Control OECB
H
Error Flags ERR MERR
Enabled
Read
Latch Input Data& Check Bits
Latched
H
H Input
H
Data
Read
Latch Corrected
Latched
Data Word into Output Latch
H
H Output Data
H
Word
Latched
L
Input
H
Enabled
Check Word
HighZ
H
H
Output
Syndrome
Bits
Enabled L
Modify/ Modify
Write
Appropriate
Byte or Bytes
& Generate New
L
Check Word
Input
Modified
H
BYTEo L
Output
Unchanged
L
BYTEo
H
Output
L
Check Word
H
H
*0E8o controls D80-D87 (8YTEo); OE81 controls D8a-D81s (8YTE1); OE82 controls 0816-0823 (8YTE2); OE83 controls 0824-0831 (8YTE3).
TABLE VII. Diagnostic Function
EDAC Function
Read & Flag
Control
S1
So
H
L
Data 1/0
Input Correct Data Word
DB Byte Control
OEBn
H
DB Output Latch LED BO
x
Check 1/0
Input Correct Check Bits
CB Control OECB
H
Error Flags ERR MERR
H
Latch Input Check
Word while Data
Input
Input Latch
L
H Diagnostic
H
Remains
Data Word*
Transparent
Latched
L
Input
H
Check Bits
Enabled
Latch Diagnostic
Data Word into
Input
Output Latch
L
H Diagnostic
H
Data Word*
Latch Diagnostic
Latched
Data Word into Input Latch
H
H
Input
Diagnostic
H
Data Word
Output
Latched
L
H
Check Bits
HighZ
H
Output
Syndrome
L
H
Bits
HighZ
H
Enabled Enabled
Output Diagnostic
Data Word&
Output
Syndrome Bits
H
H Diagnostic
L
Data Word
Output
Syndrome
L
H
Bits
High Z
H
Enabled
Output Corrected
Output
Diagnostic Data Word & Output
H
H
Corrected
Diagnostic
L
Syndrome Bits
Data Word
Output
Syndrome
L
L
Bits
HighZ
H
Enabled
*Diagnostic data is a data word with an error in one bit location except when testing the MERA error flag. In this case.the diagnostic data word will contain errors in two bit locations.
4-516
Block Diagram
s,
GSEYNNEDRRAOTMOER
=1
DB - DB _ _ _ _...,._ ___,,..__ _--! 07
DBs - DB15 - - - - + + - - - - - ; . . . - - - - - I LATCHES
DDBB1264--DDBB3213
----4--++-----;...-----1
_ _ _ _ _ _ ____,,..__ _--t
DEETRERCOTROR EN
32
_____3..2,.'---t co~~~~~oR
=1
Timing Waveforms
Read, Flag and Correct Mode
-+!4--------CORRECT--------i
TL/F /9579-4
tpd=1
ERR-s-s-s~s~s-s-s-s-s-s-ssx--------va-lid-E-RR-F-,a-g-------xsss
MERR \\\\\\\\1\-\t\p\d\\:\:x::,l_______Va-lid..M..E..R..R...-Fla-g-----xsss
TL/F/9579-5
4-517
Timing Waveforms (Continued)
Read, Correct and Modify Mode
f-- REAO--e-i--------CORRECT--------e.i----WRITE-
S1
Input Data Word Input Data Word
Output Corrected Data Word
Input New Byte
Output Corrected Data Word
s,
DB0 thru DB31
Input Check Word
Output Syndrome Code
rn\\\\\S\\S\\SX_ _ _ _ _~_nd_E_RR_fla_g_____x\\\\\\\\\\\\
\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ x ' -_ _ _ MERR
va_nd_M_ERR_f_.lag..__----lx\\\\\\\\\\\\
Diagnostic Mode
TL/F/9579-6
t,--i
......----------------------~
Input Valid Data Word
Input Diagnostic Data Word
Output Diagnostic Data Word
t,+t.
j-lpd
Output Syndrome Code
--------- ..----------------------------------------� ...... \ Verify Proper Operation of ERR flag
I
Verify Proper Operation of ERR flag, flag Should Be Low
'.. ___ so(E!a.a ~~u.l,d_B!_ f!!g_!!)_ ____ ..'
With a Diagnostic Data Word With a Single Error
. - - - - !~~ \
1.--tpd----+j - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - �
Verify Proper Operation of MERR flag I
Verify Proper Operation of MERR flag, flag Should Be Low
\. ___ _(~a.2_ ~h2._U!!! !e_H!g~ ____ ./
With a Diagnostic Data Word With a Double Error
TL/F/9579-7
4-518
Absolute Maximum Ratings (Note 1)
If MilitaryI Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5Vto +7.0V
Input Voltage (Note 2)
-0.5V to + 7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
-0.5VtoVcc -0.5Vto +5.5V
Current Applied to Output in LOW State (Max)
twice the rated Im (mA)
ESD Last Passing Voltage (Min)
4000V
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
-55�C to + 125�C 0�Cto +70�C
Supply Voltage Military Commercial
+4.5V to +5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
V1H
Input HIGH Voltage
V1L
Input LOW Voltage
Vco
Input Clamp Diode Voltage
54F/74F
Units Vee
Min Typ Max
Conditions
2.0
v
Recognized as a HIGH Signal
0.8 v
Recognized as a LOW Signal
v -1.2
Min l1N = -18 mA
VoH
Output HIGH
54F 10% Vee . 2.5
Voltage
54F 10% Vee 2.4
74F 10% Vee 2.5
74F 10% Vee 2.4
74F5% Vee 2.7
74F 5% Vee 2.7
loH = -1 mA (ERR, MERR, DBn. CBn)
loH = -3 mA (DBn, CBn)
v
Min
loH = -1 mA (ERR, MERR, DBn, CBn)
loH = - 3 mA (DBn, CBn)
loH = -1 mA (ERR, MERA'. DBn, CBn)
loH = - 3 mA (DBn, CBn)
VoL
Output LOW
54F 10% Vee
Voltage
74F 10% Vee
74F 10% Vee
0.5
Im = 20 mA (ERR, MERR, DBn, CBn)
0.5
v Min loL = 20 mA (ERR, MERR)
0.5
loL = 24 mA (DBn, CBn)
l1H
Input HIGH
54F
Current
74F
20.0 5.0
�A
Max V1N = 2.7V (So, S1, OEBn, OECB, LEDBO)
lsv1
Input HIGH Current 54F
Breakdown Test 74F
100 7.0
�A Max V1N = 7.0V (So, S1. OEBn, OECB, LEDBO)
lsvlT
Input HIGH Current 54F Breakdown (1/0) 74F
1.0
mA Max V1N = 5.5V (CBn. DBn)
0.5
leEX
Output HIGH
54F
Leakage Current 74F
250 50
�A Max VouT =Vee
V10
Input Leakage
Test
74F
4.75
v
0.0
110 = 1.9 �A
All Other Pins Grounded
loo
Output Leakage
Circuit Current
74F
3.75
�A
0.0
V100 = 150 mV
All Other Pins Grounded
l1L
Input LOW Current
-0.6 mA Max V1N = 0.5V (So, S1, OEBn, OECB, LEDBO)
l1H + lozH Output Leakage Current
70 �A Max V110 = 2.7V (CBn, DBn)
l1L + lozL Output Leakage Current
-650 �A Max V110 = 0.5V (CBn. DBn)
lozH
Output Leakage Current
70
�A Max V110 = 2.7V (CBn. DBn)
lozL los
Output Leakage Current Output Short-Circuit Current
-650 �A Max V110 = 0.5V (CBn, DBn)
-60
-150 mA Max VouT = ov
lzz
Bus Drainage Test
500 �A O.OV VouT = 5.25V (CBn, DBn)
Ice
Power Supply Current
340 mA Max TA = 0�C-25�C
Ice
Power Supply Current
325 mA Max TA = 25�C- 70�C
4-519
N
(")
<D AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
tpLH tPHL
tPLH tPHL
tPLH tpHL
tPLH tPHL tpLH tPHL
tPLH tPHL
tPLH
tPLH tPHL
tPLH tPHL tpzH tpzL
tpHz tpLz
tpzH tpzL
tpHz tpLz
Propagation Delay DB or CB to ERR
Propa~n Delay DB to ERR
Propagation Delay DB or CB to MERA
Propagation Delay DB to MERA
Propagation Delay So and S1, LOW, to DB Propagation Delay S1 to CB
Propagation Delay _ _ So or S1 to ERR or MERA
Propagation Delay DB to CB
Propagation Delay LEDBOto DB
Output Enable Time OEBn to DB
Output Disable Time OEBnto DB
Output Enable Time OECBtoCB
Output Disable Time OECBtoCB
74F
TA= +25�C Vee= +5.0V
CL= 50 pF
Min
Typ
Max
4.0
14.0
27.0
4.0
10.5
18.0
4.0
21.0
27.0
4.0
14.0
18.0
5.0
17.0
27.0
5.0
16.0
27.0
5.0
23.0
27.0
5.0
19.0
27.0
4.0
12.0
16.0
4.0
12.0
16.0
4.0
10.5
14.0
4.0
9.0
14.0
2.0
11.5
13.0
4.0
16.0
23.0
4.0
18.0
23.0
2.0
11.0
13.0
2.0
11.0
13.0
1.0
6.0
10.0
1.0
6.0
10.0
10
5.0
10.0
1.0
4.0
10.0
1.0
6.0
10.0
1.0
6.0
10.0
1.0
5.0
10.0
1.0
4.0
10.0
54F
TA, Vee= Mil CL= 50 pF
Min
Max
74F
TA, Vee= Com CL= 50 pF
Min
Max
4.0
31.0
4.0
20.0
4.0
31.0
4.0
20.0
5.0
31.0
5.0
31.0
5.0
31.0
5.0
31.0
4.0
20.0
4.0
20.0
4.0
15.0
. 4.0
15.0
2.0
14.0
4.0
25.0
4.0
25.0
2.0
14.0
2.0
14.0
1.0
10.0
1.0
10.0
1.0
10.0
1.0
10.0
1.0
10.0
1.0
10.0
1.0
10.0
1.0
10.0
Units
Fig. No.
ns 2-3 ns 2-3 ns 2-3 ns 2-3 ns 2-3 ns 2-3 ns 2-3 ns 2-3 ns 2-3 ns 2-5 ns 2-5 ns 2-5 ns 2-5
4-520
AC Operating Requirements: see section 2 for Waveforms
Symbol
Parameter
ts ts(H) ts(H) ts(H) ts ts
ts
th(L) th
Setup Time, HIGH or LOW DB/CB before So HIGH (S1 HIGH) Setup Time, HIGH So HIGH before LEDBO HIGH
Setup Time, HIGH LEDBO HIGH before So or S1 LOW Setup Time, HIGH LEDBO HIGH before S1 HIGH Setup Time, HIGH or LOW Diagnostic DB before S1 HIGH
Setup Time, HIGH or LOW Diagnostic CB before S1 LOW or So HIGH Setup Time, HIGH or LOW Diagnostic DB before LEDBO HIGH (S1 LOW, So HIGH)
Hold Time, LOW So LOW after S1 HIGH
Hold Time, HIGH or LOW DB and CB Hold after So HIGH
74F
TA= +25�c Vee= +5.0V
Min
Max
3.0
12.0
0
0
0
3.0
8.0 8.0 8.0
54F
TA, Vee= Mil
Min
Max
th
Hold Time, HIGH or LOW
DB Hold after S1 HIGH
8.0
th
Hold Time, HIGH or LOW CB Hold after S1 LOW or So HIGH
5.0
th
Hold Time, HIGH or LOW
Diagnostic DB after
0
LEDBO HIGH (S1 LOW, So HIGH)
tw(L)*
LEDBO Pulse Width
8.0
tcorr *
Correction Time
25.0
�Note: These parameters are guaranteed by characterization or other tests performed.
74F
TA, Vee= Com
Min
Max
3.0
Units
Fig. No.
ns 2-6
14.0
ns 2-6
0
ns 2-6
0
ns 2-6
0
ns 2-6
3.0
ns 2-6
8.0
ns 2-6
8.0
ns 2-6
8.0
ns 2-6
8.0
ns 2-6
5.0
ns 2-6
0
ns 2-6
8.0
ns 2-4
28.0
ns
4-521
~~SNemaitcoinoduncatolr
54F/74F640 � 54F/74F643 � 54F/74F645 Octal Bus Transceiver with TRI-STATE� Outputs
General Description
These devices are octal bus transceivers designed for asynchronous two-way data flow between the A and B busses. Both busses are capable of sinking 64 mA, have TRISTATE outputs, and a common output enable pin. The direction of data flow is determined by the transmit/receive (T/R) input. The 'F645 is a high speed/low power version of the 'F245. The 'F640 is an inverting option of the 'F645. The 'F643 has a noninverting A bus and an inverting B bus.
Features
� Designed for asynchronous two-way data flow between busses
� Outputs sink 64 mA � Transmit/receive (T/R) input controls the direction of
data flow � Guaranteed 4000V minimum ESD protection � 'F645 is a lower power, faster version of the 'F245 � 'F640 is an inverting option of the 'F645 � 'F643 has noninverting A bus and inverting B bus
Ordering Code: see section 5 Logic Symbol
Connection Diagrams
Of T/R
TL/F/10267-3
Unit Loading/Fan Out: see Section 2 for u.L. definitions
Pin Names
Description
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loHlloL
OE
T/R Ao-A1
Bo-87
Output Enable Input (Active LOW) Transmit/Receive Input Side A Inputs or TRI-STATE Outputs Side B Inputs or TRI-STATE Outputs
1.0/1.0
1.0/1.0 3.5/0.667 600/106.6 (80) 3.5/0.667 600/106.6 (80)
20 �A/ - 0.6 mA
20 �A/ -0.6 mA 70 �A/ - 0.4 mA -12 mA/64 mA (48 mA) 70 �A/ -0.4 mA -12 mA/64 mA (48 mA)
Pin Assignment for DIP, SOIC and Flatpak
T/R
Ao A1 A2 4 A3 5 A4 As As A1 GND 10
20 Vee 19 Of
18 Bo 17 81 16 82 15 83 14 84 13 85 12 85 11 87
TL/F/10267-1
Pin Assignment for LCC
As As
[film
A4
rn
A3
rn
rAn-i_
A1 I]] GND l!Q]
87 [j]
Bs lrn
85 Ii]
[I] A1
[I]Ao
[IJT/R WI Vee ll])Of
[illi]Jli]]IIlJ@I
84 83 ~ 81 Bo
TL/F/10267-2
4-522
Functional Description
The output enable (OE) is active LOW. If the device is disabled (OE HIGH), the outputs are in the high impedance state. The transmit/receive input (T/A) controls whether data is transmitted from the A bus to the B bus or from the B
bus to the A bus. When T/A is LOW, B data is sent to the A
bus. If TIA is HIGH, A data is sent to the B bus.
Function Table
Inputs
Outputs
OE T/R
'F640
'F643
'F645
L L Bus 8 data to Bus A Bus B data to Bus A Bus B data to Bus A
L H Bus A data to Bus B Bus A data to Bus B Bus A data to Bus B
H xz
z
z
H = High voltage level
L = Low voltage level
X = Don't care
Z = High-impedance state
Logic Diagrams
'F640
'F643 'F645
4-523
O'> .i:i. 0
�
O'>
.wi:i.
�
O'> .i:i. U1
TL/F/10267-4 TL/F/10267-5 TL/F/10267-6
..,,
-.:!'
�CD
C")
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
-.:!' CD
please contact the National Semiconductor Sales
�
Office/Distributors for availability and specifications.
0 -.:!'
Storage Temperature
- 65�C to + 150�C
CD
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vcc Pin Potential to Ground Pin
-0.5V to+ 7.0V
Input Voltage (Note 2)
-0.5V to + 7.0V
Input Current (Note 2)
-30 mA to + 5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
-0.5VtoVcc - 0.5V to + 5.5V
DC Electrical Characteristics
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
ESD Last Passing Voltage (Min)
4000V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
Supply Voltage Military Commercial
- 55�C to + 125�C 0�Cto +70�C
+ 4.5V to + 5.5V + 4.5V to + 5.5V
Symbol
V1H V1L Vco VoH
Vol
l1H
lsv1
lsv1r
lcEx
V10
loo
IJL l1H + lozH l1L + lozL los lzz lccH lccL lccz lccH lccL lccz lccH lccL lccz
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 74F 10% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Input HIGH Current 54F
Breakdown (1/0)
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage
Test
74F
Output Leakage
Circuit Current
74F
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Bus Drainage Test
Power Supply Current ('F640)
Power Supply Current ('F640)
Power Supply Current ('F640)
Power Supply Current ('F643)
Power Supply Current ('F643)
Power Supply Current ('F643)
Power Supply Current ('F645)
Power Supply Current ('F645)
Power Supply Current ('F645)
54F/74F Min Typ Max 2.0
0.8 -1.2 2.0 2.0 0.55 0.55 20.0 5.0 100 7.0 1.0 0.5 250
50
4.75
-100
3.75
-0.6 70
-650 -225 500
80 80 96 75 85 95 65 80 90
Units
v v v
v v
�A
�A
mA
�A
v
�A mA �A �A mA �A mA mA mA mA mA mA mA mA mA
Vee
Min
Min Min
Max
Max
Max
Max
0.0
0.0 Max Max Max Max
o.ov
Max Max Max Max Max Max Max Max Max
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal l1N = -18 mA (Non 1/0 Pins) loH = -12 mA (An. Bn) loH = -15 mA (An. Bn) loL = 48 mA (An. Bn) loL = 64 mA (An, Bn) V1N = 2.7V (Non 1/0 Pins)
V1N = 7.0V (Non 1/0 Pins)
V1N = 5.5V (An. Bn)
Vour =Vee
110 = 1.9 �A All Other Pins Grounded V100 = 150 mV All Other Pins Grounded V1N = 0.5V (Non 1/0 Pins) VouT = 2.7V (An, Bn) Vour = 0.5V (An, Bn)
Vour = ov
Vour = 5.25 Vo = HIGH, V1N = 0.2V Vo= LOW Vo= HIGHZ Vo = HIGH, V1N = 0.2V (An) Vo = LOW, V1N = 0.2V (Bn) Vo= HIGHZ Vo= HIGH Vo = LOW, V1N = 0.2V Vo= HIGHZ
4-524
O'>
.a::a.
'F640 AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
0
�
74F
54F
74F
O'>
w.a::a.
Symbol
Parameter
TA= +25�C Vee= +5.0V
TA, Vee= Mil CL= 50 pF
TA, Vee= Com CL= 50 pF
Fig. Units No.
�
CL= 50 pF
Min
Typ
Max
Min
Max
Min
Max
tPLH
Propagation Delay
2.5
7.5
tPHL
A Input to 8 Output
2.0
7.0
2.0
8.0
ns
2-3
2.0
7.0
tPLH
Propagation Delay
2.5
7.5
tPHL
B Input to A Output
2.0
7.0
2.0
8.0
ns
2-3
2.0
7.0
tpzH
Enable Time
2.5
7.5
tpzL
OE Input to A Output
2.5
8.0
tpHz
Disable Time
1.5
7.0
tpLz
OE Input to A Output
1.5
6.0
2.0
9.0
2.0
8.5
ns
2-5
1.0
7.5
1.5
6.0
tpzH
Enable Time
2.5
7.5
tpzL
OE Input to B Output
2.5
8.0
tpHz
Disable Time
1.5
7.0
tpLz
OE Input to B Output
1.5
6.0
2.0
9.0
2.0
8.5
ns
2-5
1.0
7.5
1.5
6.0
'F643 AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
tpLH tPHL
tPLH tPHL
tpzH tpzL
tpHz tpLz
tpzH tpzL
tpHz tpLz
Propagation Delay A Input to B Output
Propagation Delay 8 Input to A Output
Enable Time OE Input to A Output
Disable Time OE Input to A Output
Enable Time OE Input to B Output
Disable Time OE Input to 8 Output
74F
TA= +25�c Vee= +5.0V
CL= 50 pF
Min
Typ
Max
2.5
7.5
2.0
7.0
1.5
6.0
2.0
7.0
2.5
8.0
2.5
8.5
1.5
7.0
1.0
5.5
2.5
7.5
2.5
8.0
1.5
6.5
1.5
6.0
54F
TA, Vee= Mil CL= 50 pF
Min
Max
74F
TA, Vee= Com CL= 50 pF
Min
Max
2.0
8.0
2.0
7.0
1.5
7.0
2.0
7.5
2.0
9.0
2.0
8.5
1.0
8.0
1.0
5.5
2.0
9.0
2.0
8.5
1.0
7.5
1.5
6.0
Fig. Units
No.
ns
2-3
ns
2-3
ns
2-5
ns
2-5
4-525
Lt)
"'l:t'
�CD
'F645 AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
C")
"'l:t'
74F
54F
74F
�CD
0 "'l:t'
Symbol
CD
Parameter
TA= +25�C Vee= +5.0V
CL= 50 pF
TA, Vee= Mil CL= 50pF
TA, Vee= Com CL= 50pF
Fig. Units No.
Min
Typ
Max
Min
Max
Min
Max
tpLH
Propagation Delay
1.5
6.0
tPHL
A Input to B Output
2.0
7.0
1.5
7.0
ns 2-3
2.0
7.5
tPLH
Propagation Delay
1.5
6.0
tPHL
B Input to A Output
2.0
7.0
1.5
7.0
ns 2-3
2.0
7.5
tpzH
Enable Time
2.5
8.0
tpzL
OE Input to A Output
2.5
8.5
tpHz
Disable Time
1.5
7.0
tpu
OE Input to A Output
1.0
5.5
2.0
9.0
2.0
8.5
ns 2-5
1.0
8.0
1.0
5.5
tpzH
Enable Time
2.5
7.5
tpzL
OE Input to B Output
2.5
8.5
tpHz
Disable Time
1.5
6.5
tpLz
OE Input to B Output
1.0
5.5
2.0
9.5
2.5
9.0
ns 2-5
1.0
7.5
1.0
5.5
4-526
~National
�
~Semiconductor
54F/74F646 � 54F/74F648 Octal Transceiver/Register with TRI-STATE� Outputs
General Description
These devices consist of bus transceiver circuits with TRISTATE, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes
to a high logic level. Control G and direction pins are provid-
ed to control the transceiver function. In the transceiver mode, data present at the high impedance port may be stored in either the A or the B register or in both. The select controls can multiplex stored and real-time (transparent mode) data. The direction control determines which bus will
receive data when the enable control G is Active LOW. In the isolation mode (control G HIGH), A data may be stored
in the B register and/or B data may be stored in the A register.
Features
� Independent registers for A and B buses � Multiplexed real-time and stored data � Choice of true and inverting ('F648) data paths � TRI-STATE outputs � 300 mil slim DIP � Guaranteed 4000V minimum ESD protection
Ordering Code: see Section 5
Logic Symbols
F646
F648
G e0 81 e2 83 84 85 86 e7
I E E E / I EC
F646
DIR CPBA
SBA CPAB
SAB
Ao
A1 A2 A5 A4 As As A1
TL/F/9580-1
Bo
e,
B2 B3 84 Bs Bs 87
TL/F/9580-4
4-527
DIR CPBA SBA
IEEE/I EC
F648
DIR CPBA SBA CPAB SAB
Ao
A, A2 A5 A4 As As A1
TL/F/9580-7
ii1
TL/F/9580-9
co
"'11:1�
�(0 Connection Diagrams
(0
"'11:1�
Pin Assignment
(0
for DIP, SOIC and Flatpak
F646
CPAB SAB DIR 3 Ao 4 A1 5 Az 6 A3 7 A4 8 As 9 As 10 A1 11 GND 12
24 Vee
23 CPBA
22 SBA
21 G
20 Bo 19 B1 18 Bz 17 B3 16 B4 15 Bs 14 Bs 13 B1
TL/F/9580-2
Pin Assignment for LCC F646
As A4 A3 NC Az A1 Ao
[l] [QI [[] ([] l:IJ[�J rfil
As fill
A11Lll GND~
NC li]J
B1 Ii]]
Bs lill
Bs Ii]]
[i] DIR [II SAB [I) CPAB [j] NC ~Vee gz] CPBA ~SBA
!!ID @ [i] llll 1?.H3l ~ B4 B3 Bz NC B1 Bo G
TL/F/9580-3
Pin Assignment for DIP, SOIC and Flatpak
F648
CPAB 1 SAS 2 DIR 3 Ao 4 A1 5 A2 6 A3 7 A4 8 As 9 As 10 A1 11 GND 12
24 Vee
23 CPBA
22 SBA
21 G
20 ii0 19 81 18 82 17 83 16 84 15 iis 14 iis 13 , 81
TL/F /9580-8
Pin Assignment for LCC F648
As [j]
A4 [QI
rAn3
NC
rn
mA2 rAn1rAn0
As fill
A11Lll GND~
NC li]J
B7 IJ]] Bs lill
iis Ii]]
[i] DIR [II SAS [I]CPAB [j] NC ~Vee gz] CPBA
~SBA
[!ID@[j]lll]~~~
84 83 ii2 NC 81 80 G
TL/F/9580-10
4-528
en
Unit Loading/Fan Out: See Section 2 for U.L. definitions
54F/74F
e.i:ni.
e�n
.ci:oi.
Pin Names
Description
U.L.
Input l1HlllL
HIGH/LOW
Output loHlloL
Ao-A1
Data Register A Inputs/
TRI-STATE Outputs
Bo-87
Data Register B Inputs/
TRI-STATE Outputs
CPAB, CPBA Clock Pulse Inputs
SAB, SBA Select Inputs
G
Output Enable Input
DIR
Direction Control Input
3.5/1.083 600/106.6 (80)
3.5/1.083 600/106.6 (80)
1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0
70 �Al - 650 �A -12 mA/64 mA (48 mA)
70 �Al - 650 �A -12 mA/64 mA (48 mA)
20 �Al - 0.6 mA 20 �A/-0.6 mA 20 �Al - 0.6 mA 20 �A/ - 0.6 mA
Function Table
Inputs
Data 1/0*
G
DIR
CPAB
CPBA
SAB
SBA
Ao-A1
Bo-81
Function
H
x
Hor L Hor L
x
H x ....r
x
x
H x
x
....r x
x
Isolation
x
Input
Input
Clock An Data into A Register
x
Clock Bn Data into B Register
L
H
x
x
L
H
....r
x
L
H
Hor L
x
L
H
....r
x
L
x
An to Bn-Real Time (Transparent Mode)
L
x
Clock An Data into A Register
H
x
Input
Output
A Register to Bn (Stored Mode)
H
x
Clock An Data into A Register and Output to Bn
L
L
L
L
L
L
L
L
x
x
x
x
....r
x
x
Hor L
x
x
....r
x
L
Bn to An-Real Time (Transparent Mode)
L
Clock Bn Data into B Register
Output
Input
H
B Register to An (Stored Mode)
H
Clock Bn Data into B Register and Output to An
�rhe data output functions may be enabled or disabled by various signals at the G and DIR Inputs. Data input functions are always enabled; i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the clock inputs.
H = HIGH Voltage Level L = LOW Voltage Level X = Irrelevant _r = LOW-to-HIGH Transition
4-529
Logic Diagrams (Continued)
'F646
DIR-----
CBA----------li--------------11 SBA----------li-------11 CAB----1 SAB--------t--+----t
�- - -----1-or-8-C-H-AN-N-EL-S --- - - ---------------- - -�
Co�>-----
A o , . _ -..... , _ + -....- e e--+---t--<llCo
Bo . , .....- + - - i i e - -....
�- - ---------------- - - ---------------- - -�
TO 7 OTHER CHANNELS
TL/F/9580-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-530
Logic Diagrams (Continued)
'F648
DIR--....- - t
CBA----------11------~------1 SBA----~-----1-------11
CAB----1
SAB--------t---+-~--1
1 or 8 CHANNELS
_ _.._.___ "~Co
�- ---------------- - -
- ---------------- - -4
TO 7 OTHER CHANNELS
TL/F/9580-6 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-531
co
"'l::t'
�<D
<D
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
"'l::t' <D
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to + 7.0V
Input Voltage (Note 2)
-0.5V to + 7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
-0.5VtoVee -0.5Vto +5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
ESD Last Passing Voltage (Min)
4000V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
V1H V1L Yeo VoH
Vol
l1H
lsv1
lsv1T
lcEx
V10
loo
l1L l1H + lozH l1L + lozL los lzz lceH lceL lccz
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 74F 10% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Input HIGH Current 54F
Breakdown (1/0)
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage
Test
74F
Output Leakage
Circuit Current
74F
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Bus Drainage Test
Power Supply Current
Power Supply Current
Power Supply Current
54F/74F Min Typ Max 2.0
0.8 -1.2 2.0 2.0 0.55 0.55 20.0 5.0 100 7.0 1.0 0.5 250
50
4.75
Units
v v v v v
�A
�A
mA
�A
v
-100
3.75
�A
-0.6 mA
70
�A
-650 �A
-225 mA
500
�A
135
mA
150
mA
150
mA
Vee
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal Min l1N = -18 mA (Non 1/0 Pins) Min loH = -12 mA (An, Bn) loH = -15 mA (An, Bn) Min loL = 48 mA (An, Bn) loL = 64 mA (An, Bn) Max V1N = 2.7V (Non 1/0 Pins)
V1N = 7.0V (Non 1/0 Pins) Max
Max V1N = 5.5V (An. Bn)
Max VouT =Vee
0.0
0.0
Max Max Max Max
o.ov
Max Max Max
IJD = 1.9 �A All Other Pins Grounded
V100 = 150 mV All Other Pins Grounded V1N = 0.5V (Non 1/0 Pins)
VouT = 2.7V (An. Bn) VouT = 0.5V (An. Bn)
VouT = ov
VouT = 5.25V Vo= HIGH Vo= LOW Vo= HIGH Z
4-532
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
fmax
tPLH tPHL
tPLH tPHL
tPLH tPHL
tPLH tPHL
tpzH tpzL
tpHz tpLz
tpzH tpzL
tpHz tpLz
Maximum Clock Frequency
Propagation Delay Clock to Bus
Propagation Delay Bus to Bus ('F646)
Propagation Delay Bus to Bus ('F648)
Propagation Delay SBA or SAB to A or B
Enable Time OE to A or B
Disable Time OE to A or B
Enable Time DIRtoAorB
Disable Time DIR to A or B
74F
TA= +25�C Vee= +5.0V
CL= 50 pF
Min
Max
90
2.0
7.0
2.0
8.0
1.0
7.0
1.0
6.5
2.0
8.5
1.0
7.5
2.0
8.5
2.0
8.0
2.0
8.5
2.0
12.0
1.0
7.5
2.0
9.0
2.0
14.0
2.0
13.0
1.0
9.0
2.0
11.0
54F
TA, Vee= Mil CL= 50 pF
Min
Max
75
2.0
8.5
2.0
9.5
1.0
8.0
1.0
8.0
1.0
10.0
1.0
9.0
2.0
11.0
2.0
10.0
2.0
10.0
2.0
13.5
1.0
9.0
2.0
11.0
2.0
16.0
2.0
15.0
1.0
10.0
2.0
12.0
74F
TA, Vee= Com CL= 50 pF
Min
Max
90
2.0
8.0
2.0
9.0
1.0
7.5
1.0
7.0
2.0
9.0
1.0
8.0
2.0
9.5
2.0
9.0
2.0
9.0
2.0
12.5
1.0
8.5
2.0
9.5
2.0
15.0
2.0
14.0
1.0
9.5
2.0
11.5
AC Operating Requirements: See Section 2 for Waveforms
Symbol
Parameter
t5 (H) t5 (L)
th(H) th(L)
tw(H) tw(L)
Setup Time, HIGH or LOW Busto Clock
Hold Time, HIGH or LOW Busto Clock
Clock Pulse Width HIGH or LOW
74F
TA= +25�C Vee= +5.0V
Min
Max
5.0 5.0
2.0 2.0
5.0 5.0
54F
TA, Vee= Mil
Min
Max
5.0 5.0
2.5 2.5
5.0 5.0
74F
TA, Vee= Com
Min
Max
5.0 5.0
2.0 2.0
5.0 5.0
Fig. Units
No.
MHz 2-1
ns
2-3
ns
2-3
ns
2-3
ns
2-3
ns
ns
2-5
ns
ns
2-5
Fig. Units
No.
ns
2-6
ns
2-6
ns
2-4
4-533
N
Lt)
C,�.D.. ~National
Lt)
CD
~Semiconductor
54F/74F651 � 54F/74F652 Transceivers/Registers
General Description
These devices consist of bus transceiver circuits with D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to HIGH logic level. Output Enable pins (OEAB, OEBA) are provided to control the transceiver function.
Features
� Independent registers for A and B buses � Multiplexed real-time and stored data � Choice of non-inverting and inverting data paths
- 'F651 inverting - 'F652 non-inverting � Guaranteed 4000V minimum ESD protection
Ordering Code: see section 5 Logic Symbols
I E E E / I EC 'F651
OEBA OEAB SBA CPBA CPAB
SAB
Ao
OEBA OEAB CPBA SBA CPAB SAB
Bo
Ao
A1
B1
A1
A2
B2
A2
A5
B5
A5
A4
B4
A4
As
Bs
As
As
Bs
As
A1
B1
A1
TL/F/9581-1
'F651
I E E E / I EC 'F652
Bo
'F652
B1 B2 B5 B4 Bs Bs B1
TL/F/9581-10
Ao A, A2 A5 A4 As As A1
CPAB SAB
OEAB
CPBA
OEBA
SBA
Bo B1 B2 B3 B4 B5 B6 B7
TL/F/9581-2
TL/F/9581-11
Connection Diagrams
Pin Assignment DIP, SOIC and Flatpak
CPAB
SAB OEAB 3
Ao 4
A1 5 A2 6 A5
A4 As 9 As 10 A1 11 GND 12
24 Vee 23 CPBA 22 SBA 21 OEBA 20 Bo 19 B1 18 82 17 83 16 B4 15 Bs 14 Bs 13 B1
TL/F/9581-3
Pin Assignment
� forLCC
As [j]
A4 l@l
rAn3
NC
l!l
mA2 IAI1I
Ao
rn
A5@ A1fill GND [i]] NC[fil
87 [j]) B5 [j]
Bs l!ID
[!J OEA8
C1J SA8
lIJCPA8 [I]NC ~Vee ~CPBA ~SBA
li]J~lii!~~~~
84 83 B2 NC B1 Bo OEiiA
TL/F/9581-4
4-534
a>
Unit Loading/Fan Out: See Section 2 tor u.L. Definitions
C_J.1.
�a>
54F/74F
CJ1
~
Pin Names
Description
U.L.
Input l1H/l1L
HIGH/LOW
Output loH/loL
Ao-A7, 80-87
CPAB,CPBA SAS, SBA OEAB,OEBA
A and B Inputs/ TRI-STATE� Outputs Clock Inputs Select Inputs Output Enable Inputs
1.0/1.0 600/106.6 (80)
1.0/1.0 1.0/1.0 1.0/1.0
20 �A/ - 0.6 mA -12 mA/64 mA (48 mA)
20 �A/ - 0.6 mA 20 �A/-0.6 mA 20 �A/-0.6 mA
Logic Diagrams
'F652
OEAB-----1 CPBA------+-----------1 SBA-------l,__--1 CPAB
SAB-----+---l~
TO 7 OTHER CHANNELS
TL/F/9581-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-535
Logic Diagrams (Continued)
'F651
OEAB-----11
CPBA-------+---------~---1 SBA-~~~---+-~
CPAB SAB------1~.......
TO 7 OTHER CHANNELS
TL/F/9581-12
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Functional Description
In the transceiver mode, data present at the HIGH impedance port may be stored in either the A or B register or both.
The select (SAB, SBA) controls can multiplex stored and real-time.
The examples in Figure 1 demonstrate the four fundamental bus-management functions that can be performed with the Octal bus transceivers and receivers.
Data on the A or B data bus, or both can be stored in the internal D flip-flop by LOW to HIGH transitions at the appro-
priate Clock Inputs (CPAB, CPBA) regardless of the Select or Output Enable Inputs. When SAB and SBA are in the real time transfer mode, it is also possible to store data without using the internal D flip-flops by simultaneously enabling OEAB and OEBA. In this configuration each Output reinforces its Input. Thus when all other data sources to the two sets of bus lines are in a HIGH impedance state, each set of bus lines will remain at its last state.
4-536
a>
1----!T---1 r Note A: Real-Time
Transfer Bus B to Bus A
~<~A
]Note B: Real-Time Transfer Bus A to Bus B
������I������
I
Ill
I
I
Ill
I
I
Ill
I
I
II I
I
Note C: Storage
'f'l ;----~;----~ ..,
. .--~--~'!'.'/>.
I
II I
I
I II
VI
I
Ill
:
I
I I
"V'I
Note D: Transfer Storage Data to A or B
�.U..1..
a> U1 N
~"'f~-.--.~.-.--.~~~
I
II I
I J\ m
~~~.--.~.-.--.~y/I~
::>
"'
I I
Ill Ill
I
::>
I
:
:~
I
I
Ill
I
I
111
I
I
111
I
� �I ----�111�----�I
m 1llI
I
111
I
I
111
t
� I
111
I
�I ----�111�----�I
ITII III
:�----�~�I�----�I Jill 1111
TII 11
TL/F/9561-6 OEAB ornA CPAB CPBA SAB SBA
X L
II II I
TL/F/9581-7 OEAB otilA CPAB CPBA SAB SBA
L X
TTITTT
TL/F/9561-8
OEAB otilA CPAB CPBA SAB SBA
X
H .../ X X X
x .../ x x
L
H .../ .../ X X
11 II
TL/F/9581-9 OEAB otilA CPAB CPBA SAB SBA
L HorL HorL H X
FIGURE 1
Inputs
Inputs/Outputs (Note 1)
Operating Mode
OEAB
CPAB CPBA SAB SBA
Ao thru A1
Bo thru B1
L
H
Hor L Hor L
x
x
Input
L
H
x x
Input
Isolation Store A and B Data
x
H
H orl
x
x
Input
Not Specified Store A, Hold B
H
H
x
x
Input
Output
Store A in Both Registers
L
x
Hor L
x
x
Not Specified Input
Hold A, Store B
L
L
x
x
Output
Input
Store B in Both Registers
L
L
x
x
x
L
Output
L
L
x
Hor L
x
H
Input
Real-Time B Data to A Bus Store B Data to A Bus
H
H
x
x
L
x
Input
H
H
Horl
x
H
x
Output
Real-Time A Data to B Bus Stored A Data to B Bus
H
L
Hor L Hor L
H
H
Output
Output
Stored A Data to B Bus and Stored B Data to A Bus
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
_r = LOW to HIGH Clock Transition
Note 1: The data output functions may be enabled or disabled by various signals at OEAB or OEBA inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every LOW to HIGH transition on the clock inputs.
4-537
C\I
LC)
�<,.D.. Absolute Maximum Ratings (Note 1)
LC) If Military/Aerospace specified devices are required, <D please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 15o�c
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-;'0.5V to+ 7.0V
Input Voltage (Note 2)
-0.5V to+ 7.0V
Input Current (Note 2)
-30 mA to+ 5.0 mA
Note 1: Absolute maximum ratings are values beyond which the.device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
Current Applied to Output in LOW State (Max)
ESD Last Passing Voltage (Min)
-0.5V to Vee - 0.5V to + 5.5V
twice the rated loL (mA) 4000V
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C o�cto +70�c
Supply Voltage Military Commercial
+4.5Vto +5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
VrH VrL Yeo VoH
Vm
lrH
lsvr
lsvrr
lcEx
V10
loo
l1L lrH + lozH lrL + lozL las lzz lceH lceL lcez
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 74F 10% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Input HIGH Current 54F
Breakdown (1/0)
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage 74F
Test
Output Leakage 74F
Circuit Current
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Bus Drainage Test
Power Supply Current
Power Supply Current
Power Supply Current
54F/74F Min Typ Max 2.0
0.8 -1.2 2.0 2.0 0.55 0.55 20.0 5.0 100 7.0 1.0 0.5 250
50
4.75
3.75
-0.6
70
-650
-100
-225
500
105 135
118 150
115 150
Units
v v v v
v
�A
�A
mA
�A
v
�A mA �A �A mA �A mA mA mA
Vee
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal Min lrN = -18 mA (Non 1/0 Pins) loH = -12 mA (An. Bn) Min loH = -15 mA (An. Bn) Min loL = 48 mA (An. Bn) loL = 64 mA (An, Bn) VrN = 2.7V Max (Non 1/0 Pins) Max VrN = 7.0V
Max VrN = 5.5V (An. Bn)
Max VouT =Vee
0.0
0.0
Max Max Max Max o.ov Max Max Max
110 = 1.9 �A All Other Pins Grounded Vlroo = 150 mV All Other Pins Grounded VrN = 0.5V (Non 1/0 Pins) VouT = 2.7V (An, Bn) VouT = 0.5V (An, Bn) VouT = ov VouT = 5.25V Vo= HIGH Vo= LOW Vo= HIGHZ
4-538
AC Electrical Characteristics: See section 2 for Waveforms and Load Configurations
Symbol
Parameter
fmax
tpLH tPHL
tpLH tPHL
tPLH tpHL
tpLH tpHL
Max. Clock Frequency
Propagation Delay Clock to Bus
Propagation Delay Bus to Bus ('F651)
Propagation Delay Bus to Bus ('F652)
Propagation Delay SBA or SAB to A or B
74F
TA= +25�C Vee= +5.0V
CL= 50 pF
Min
Max
90
2.0
7.0
2.0
8.0
2.0
8.5
1.0
7.5
1.0
7.0
1.0
6.5
2.0
8.5
2.0
8.0
54F
TA, Vee= Mil CL= 50 pf
Min
Max
75
2.0
8.5
2.0
9.5
1.0
9.0
1.0
8.0
1.0
8.0
1.0
8.0
2.0
11.0
2.0
10.0
74F
TA, Vee= Com CL= 50 pF
Min
Max
90
2.0
8.0
2.0
9.0
2.0
9.0
1.0
8.0
1.0
7.5
1.0
7.0
2.0
9.5
2.0
9.0
AC Operating Requirements: See Section 2 for Waveforms
Symbol
Parameter
tpzH tpzL
tpHZ tpLz
tpzH tpzL
tpHz tpLZ t5 (H) t 5 (L) th(H) th(L)
tw(H) tw(L)
Enable Time *OEBA to A
Disable Time *OEBAtoA
Enable Time OEABto B
Disable Time OEAB to B
Setup Time, HIGH or LOW, Bus to Clock
Hold Time, HIGH or LOW, Bus to Clock
Clock Pulse Width HIGH or LOW
74F
TA= +25�C Vee= +5.0V
Min
Max
2.0
9.5
2.0
12.0
1.0
7.5
2.0
8.5
2.0
9.5
3.0
13.0
2.0
9.0
2.0
10.5
5.0 5.0
2.0 2.0
5.0 5.0
54F
TA, Vee= Mil
Min
Max
2.0
10.0
2.0
10.0
1.0
9.0
1.0
9.0
2.0
10.0
2.0
12.0
1.0
9.0
1.0
12.0
5.0 5.0
2.5 2.5
5.0 5.0
74F
TA, Vee= Com
Min
Max
2.0
10.0
2.0
12.5
1.0
8.0
2.0
9.0
2.0
10.0
3.0
14.0
2.0
10.0
2.0
11.0
5.0 5.0
2.0 2.0
5.0 5.0
en
.eU.�.n.1.
U1 N
Fig. Units
No.
MHz
2-1
ns
2-3
ns
2-3
ns
2-3
ns
2-3
Fig. Units
No.
ns
2-5
ns
2-5
ns
2-6
ns
2-6
ns
2-4
4-539
~~SNemaitcoinoduncatolr
54F/74F657 Octal Bidirectional Transceiver with 8-Bit Parity Generator/Checker and TRI-STATE� Outputs
General Description
The 'F657 contains eight non-inverting buffers with TRI-STATE� outputs and an 8-bit parity generator/checker. It is intended for bus-oriented applications. The buffers have a guaranteed current sinking capability of 24 mA (20 mA mil) at the A port and 64 mA (48 mA mil) at the B port.
Features
� 300 Mil 24-pin slimline DIP � Combines 'F245 and 'F280A functions in one package � TRI-STATE outputs � 8 Outputs sink 64 mA (48 mA mil) � 12 mA source current, B side � Input diodes for termination effects
Ordering Code: see sections Logic Symbols
Connection Diagrams
T/R OE
ODD/ EVEN
Ao
A1 A2 A3 A4 As A5 A1
I E E E / I EC
PARITY ERROR Bo B1 B2 B3 B4 Bs B5 B1 TL/F/9584-5
Pin Assignment for DIP, SOIC and Flatpak
T/R Ao
A1 3 A2 A3 A4 6
Yee 7
As 8 A5 9 A1 10 ODD/EVEN 11 ERROR 12
24 OE
23 Bo 22 B1 21 B2 20 B3 19 GND
18 GND
17 B4 16 Bs 15 B5 14 B1 13 PARITY
TL/F/9584-2
Pin Assignment for LCC
85 85 87 NC PAR ERR ODD/EVEN
[j] l!QI rn rn rn [�:] rn
B4 Ii]] GND ILl] GND Ii]
NC fj]]
B5 fill
B2 Ii] B1 [�]
1IJ A1
[lJ A5
illA5 [I] NC
~Yee
lllJ A4
~A3
II2l~~~l~H~~
Bo OE T/R NC Ao A1 A2
TL/F/9584-3
TL/F/9584-1
4-540
Unit Loading/Fan Out: See Section 2 for U.L. definitions
Pin Names
Description
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loH/loL
Ao-A7
Data Inputs/
TRI-STATE Outputs
Bo-B7
Data Inputs/
TRI-STATE Outputs
T/R
Transmit/Receive Input
OE
Enable Input
PARITY
Parity Input/
TRI-STATE Output
ODD/EVEN ODD/EVEN Parity Input
ERROR
Error Output
4.5/0.15 150/40 (33.3)
3.5/0.117 600/106.6 (80)
2.0/0.067 2.0/0.067 3.5/0.117 600/106.6 (80) 1.0/0.033 600/106.6 (80)
90 �A/- 90 �A -3 mA/24 mA (20 mA)
70 �A/-70 �A -12 mA/64 mA (48 mA)
40 �A/-40 �A 40 �A/-40 �A 70 �A/-70�A -12 mA/64 mA (48 mA) 20 �A/-20 �A -12 mA/64 mA (48 mA)
Functional Description
The Transmit/Receive (T/R) input determines the direction of the data flow through the bidirectional transceivers. Transmit (active HIGH) enables data from the A port to the B port; Receive (active LOW) enables data from the B port to the A port.
The Output Enable (OE) input disables the parity and ERROR outputs and both the A and B ports by placing them in a HIGH-Z condition when the Output Enable input is HIGH.
When transmitting (T/R HIGH), the parity generator detects whether an even or odd number of bits on the A port are HIGH and compares these with the condition of the pari-
ty select (ODD/EVEN). If the Parity Select is HIGH and an even number of A inputs are HIGH, the Parity output is HIGH.
In receiving mode (T/R LOW), the parity select and number of HIGH inputs on port B are compared to the condition of the Parity input. If an even number of bits on the B port are HIGH, the parity select is HIGH, and the PARITY input is HIGH, then ERROR will be HIGH to indicate no error. If an odd number of bits on the B port are HIGH, the parity select is HIGH, and the PARITY input is HIGH, the ERROR will be LOW indicating an error.
Function Table
Number of Inputs That
Inputs
Input/ Output
Outputs
Are High
OE
T/R
ODD/EVEN
Parity
ERROR
Outputs Mode
0,2,4,6,8
L
H
H
L
H
L
H
z
Transmit
L
z
Transmit
L
L
H
H
H
Receive
L
L
H
L
L
Receive
L
L
L
H
L
Receive
L
L
L
L
H
Receive
1, 3, 5, 7
L
H
H
L
H
L
L
z
Transmit
H
z
Transmit
L
L
H
H
L
Receive
L
L
H
L
H
Receive
L
L
L
H
H
Receive
L
L
L
L
L
Receive
Immaterial
H
x
x
z
z
z
H = HIGH Voltage Level
L = LOW Voltage Level X = Immaterial Z = High Impedance
Function Table
Inputs
OE
T/R
Outputs
L
L
Bus B Data to Bus A
L
H
Bus A Data to Bus B
H
x
High-Z State
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
4-541
Functional Block Diagram
T/R
6E
Ao Bo
A1 81
A2 82
A3 83
A-4 B-4
A5 85
As Bs
A1 87
2 GROUND PINS 1 Yee PIN
4-542
TL/F/9584-4
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
-65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to + 7.0V
Input Voltage (Note 2)
-0.5V to+ 7.0V
Input Current (Note 2)
-30 mA to + 5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
-0.5VtoVee -0.5V to +5.5V
DC Electrical Characteristics
CJ)
.c....n..
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
Symbol V1H V1L Veo VoH
Vol
l1H lsv1 lsv1r l1L lozH lozL l1H + lozH l1L + lozL los leEX
lzz leeH leeL leez
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10%Vee 54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee 74F 10% Vee 74F5% Vee 74F5% Vee
Output LOW Voltage
54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee
Input HIGH Current
Input HIGH Current Breakdown Test
Input HIGH Current Breakdown Test (1/0)
Input LOW Current
Output Leakage Current Output Leakage Current Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Output HIGH Leakage Current
Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current
54F/74F
Min Typ Max
2.0
0.8
-1.2
2.5 2.4 2.0 2.5 2.4 2.0 2.7 2.7
0.5 0.55 0.5 0.55
20 40
100
1.0 2.0
-20 -40
50
-50
70 90
-70 -90
-60 -100
-150 -225
250 1.0 2.0
500
101 125
112 150
109 145
Units
v v v
v
v
�A �A mA �A �A �A �A �A mA �A mA mA �A mA mA mA
Vee
Conditions
Recognized as a HIGH Signal
Recognized as a LOW Signal
Min l1N = -18mA
loH = -1 mA (An)
loH = -3 mA (An, Bn. Parity, ERROR)
loH = -12 mA (Bn. Parity, ERROR)
Min
loH = -1 mA (An) loH = -3 mA (An Bn, Parity, ERROR)
loH = -15 mA (Bn. Parity, ERROR)
loH = -1 mA (An)
loH = ..,..3 iTIA (An. Bn, Parity, ERROR)
loL = 20 mA (An)
Min
loL = 48 mA (Bn. Parity, ERROR) loL = 24 mA (An)
loL = 64 mA (Bn Parity, ERROR)
Max
V1N = 2.7V (ODD/EVEN) V1N 2.7V (T/R, OE)
o Vee= V1N = 7.0V (T/R, OE, ODD/EVEN)
Max
Max
Max Max
Max
Max
Max
Max Max Max
o.ov
Max Max Max
V1N = 5.5V (Parity, Bn) V1N = 5.5V (An)
V1N = 0.5V (ODD/EVEN) V1N = 0.5V (T/R, OE)
Vour = 2.7V (ERROR)
Vour = 0.5V (ERROR)
V110 = 2.7V (Bn, Parity) V110 = 2. 7V (An)
V110 = 0.5V (Bn, Parity) V110 = 0.5V (An)
Vour = OV (An) Vour = OV (Bn. Parity, ERROR)
Vour = Vee (ERROR) Vour = Vee (Bn. Parity) Vour = Vee (An) Vour = 5.25V (An, Bn, Parity, ERROR)
Vo= HIGH
Vo= LOW
Vo= HIGHZ
4-543
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
74F
54F
74F
Symbol
Parameter
TA= +25�C Vee= +5.0V
CL= 50 pF
TA, Vee= Mil CL= 50 pF
TA, Vee= Com CL= 50 pF
Units
Fig. No.
Min
Typ
Max
Min
Max
Min
Max
tPLH tPHL
Propagation Delay An to Bn, Bn to An
2.5
4.5
8.0
2.5
9.5
2.5
9.0
ns
2-3
3.0
4 .. 9
7.5
3.0
8.5
3.0
8.0
tPLH tpHL
Propagation Delay An to Parity
6.5
10.1
14.0
5.5
18.0
6.0
16.0
ns
2-3
7.0
10.9
15.0
5.5
20.5
6.0
16.5
tpLH
Propagation Delay
4.5
7.8
11.0
4.0
14.0
4.0
13.0
ns
2-3
tPHL
ODD/EVEN to PARITY
4.5
8.8
12.0
4.5
16.5
4.5
13.5
tPLH tpHL
Propagation Delay
4.5
ODD/EVEN to ERROR
4.5
7.5 8.2
11.0 12.0
4.0 4.5
14.0 16.5
4.0 4.5
13.0 13.5
ns
2-3
tpLH tPHL
Propagation Delay Bn to ERROR
8.0
14.0
20.5
7.5
27.0
7.5
23.0
8.0
15.0
21.5
7.5
28.5
7.5
23.5
ns
2-3
tPLH
Propagation Delay
tPHL
PARITY to ERROR
7.0
10.8
15.5
6.0
20.0
6.0
17.0
ns
2-3
7.5
11.8
16.5
6.5
22.0
7.5
18.5
tpzH tpzL
Output Enable Time OE toAn/Bn
3.0
5.0
8.0
2.5
11.0
2.5
9.5
ns
2-5
4.0
6.5
10.0
3.5
13.5
3.5
11.0
tpHz tpLZ
Output Disable Time OE to An/Bn
1.0
4.5
8.0
1.0
9.5
1.0
9.0
1.0
4.9
7.5
1.0
8.5
1.0
ns
2-5
8.0
tpzH
Output Enable Time
3.0
5.0
8.0
2.5
11.0
2.5
9.5
ns
2-5
tpzL
OE to ERROR (Note 1)
4.0
7.7
10.0
3.5
13.5
3.5
11.0
tpHz tpLz
Output Disable Time OE to ERROR
1.0
4.5
8.0
1.0
9.5
1.0
9.0
1.0
4.9
7.5
1.0
8.5
ns
2-5
1.0
8.0
tpzH tpzL
Output Enable Time OE to PARITY
3.0
5.0
8.0
2.5
11.0
2.5
9.5
4.0
7.7
10.0
3.5
13.5
3.5
ns
2-5
11.0
tpHz tpLz
Output Disable Time OE to PARITY
1.0
4.6
8.0
1.0
9.5
1.0
9.0
ns
2-5
1.0
5.1
7.5
1.0
8.5
1.0
8.0
Note 1: These delay times reflect the TRI-STATE recovery time only and not the signal time through the buffers or the parity check circuity. To assure VALID
information at the ERROR pin, time must be allowed for the signal to propagate through the drivers (B to A), through the parity check circuitry (same as A to
PARITY), and to the ERROR output after the ERROR pin has been enabled (Output Enable times). VALID data at the ERROR pin~ (A to PARITY) + (Output
Enable Time).
4-544
~~SNemaitcoinoduncatolr
54F/74F673A
16-Bit Serial-In, Serial/Parallel-Out Shift Register
General Description
The 'F673A contains a 16-bit serial-in, serial-out shift register and a 16-bit parallel-out storage register. A single pin serves either as an input for serial entry or as a TRISTATE� serial output. In the Serial-out mode, the data recirculates in the shift register. By means of a separate clock, the contents of the shift register are transferred to the storage register for parallel outputting. The contents of the storage register can also be parallel loaded back into the shift register. A HIGH signal on the Chip Select input prevents both shifting and parallel transfer. The storage register may be cleared via STMR.
Features
� Serial-to-parallel converter � 16-bit serial 1/0 shift register � 16-bit parallel-out storage register � Recirculating serial shifting � Recirculating parallel transfer � Common serial data 1/0 pin � Slim 24 lead package
Ordering Code: See section 5 Logic Symbols
Sl/O
I E E E / I EC SRG16
TLIF/9585-1
4-545
TL/F/9585-4
<t
C")
"(0 Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
Cs
SHCP
R/W 3
STMR 4 STCP 5
Sl/O Oo 7 01 8 02 03 10 04 11
GND 12
24 Yee
23 015 22 014 21 013 20 012 . 19 011 18 010 17 Og
16 Os 15 07 14 05 13 05
TL/F/9585-2
Pin Assignment for LCC
02 01 Oo NC Sl/O STCP STMR
[TI [IQ] []] []] [ZJ []] ill
03 [i1] 04 [Ll] GND IG]
NC !Im
05 [�] 05 [Q] 07 11]]
l�l R/W
[]] SHCP
[I] cs
[I] NC ~Vee Ill] 015
Im 014
[j]]~~llll~~~ 08 Og 010 NC 011 012 013
TL/F/9585-3
Unit Loading/Fan Out: See Section 2 for U.L. Definitions
54F/74F
Pin Names
Description
U.L. HIGH/LOW
Input l1Hll1L Output loH/loL
cs
SHCP STMR STCP R/W Sl/O
Oo-015
Chip Select Input (Active LOW) Shift Clock Pulse Input (Active Falling Edge) Store Master Reset Input (Active LOW) Store Clock Pulse Input Read/Write Input Serial Data Input or TRI-STATE Serial Output Parallel Data Outputs
1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 3.5/1.0 150/40 (33.3) 50/33.3
20 �A/-0.6 mA 20 �Al - 0.6 mA 20 �A/-0.6 mA 20 �A/-0.6 mA 20 �A/-0.6 mA 70 �Al - 0.6 mA -3 mA/24 mA (20 mA) -1 mA/20 mA
Functional Description
The 16-bit shift register operates in one of four modes, as indicated in the Shift Register Operations Table. A HIGH signal on the Chip Select (CS) input prevents clocking and forces the Serial Input/Output (Sl/0) TRI-STATE buffer into the high impedance state. During serial shift-out operations, the Sl/O buffer is active (i.e., enabled) and the output data is also recirculated back into the shift register. When parallel loading the shift register from the storage register, serial shifting is inhibited.
The storage register has an asynchronous master reset
(STMR) input that overrides all other inputs and forces the Oo-01s outputs LOW. The storage register is in the Hold mode when either CS or the Read/Write (R/W) input is HIGH. With CS and R/W both LOW, the storage register is parallel loaded from the shift register.
4-546
.----~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~---,
Shift Register Operations Table
O'>
w.......
)>
Control Inputs
cs
R/W
SHCP
STCP
Sl/O Status
Operating Mode
H
x
x
L
L
L
H
"--
x
HighZ
Hold
x
Data In
Serial Load
H = HIGH Voltage Level L = LOW Voltage Level
X = Immaterial
Serial Output
L
Data Out
"'""-- = HIGH-to-LOW Transition
with Recirculation
L
H
"--
H
Active
Parallel Load; No Shifting
STMR
L H H H
Storage Register Operations Table
Control Inputs
cs
R/W
x x
H
x
x
H
L
L
STCP
x x x
_r
Operating Mode
Reset; Outputs LOW Hold Hold Parallel Load
Block Diagram
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial .../" = LOW-to-HIGH Transition
SHCP RfW
STCP STt.lR
PE
Po-P15
Do
015
Sl/O
SHIFT REGISTER
CP
Oo-015
16
Do-D15
STORAGE REGISTER
CP t.lR
Oo-015
16 Oo-015
16 TL/F/9585-5
4-547
Absolute Maximum Ratings (Note 1)
If MilitaryI Aerospace specified devices are required, please contact the Natlonal Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 15o�c
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to+ 7.0V
Input Voltage (Note 2)
-0.5Vto +7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
-0.5Vto Vee - 0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C
o�cto +10�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
V1H V1L Veo VoH
VoL
l1H lsv1
lsv1r
l1L l1H + lozH l1L + lozL los leEX lzz leeH leeL
,,
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee 74F5% Vee 74F 5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee 74F 10% Vee
Input HIGH Current
Input HIGH Current Breakdown Test
Input HIGH Current Breakdown Test (1/0)
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current Output HIGH Leakage Current Bus Drainage Test Power Supply Current Power Supply Current
54F/74F Min Typ Max 2.0
0.8 -1.2 2.5 2.4 2.5 2.4 2.7 2.7 0.5 0.5 0.5
20
100
1.0
Units v v v
v
v �A �A mA
-0.6
mA
70
�A
-650
�A
-60
-150
mA
250
�A
500
�A
114
172
mA
114
172
mA
Vee
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal
Min l1N = -18 mA (Non 1/0 pins) loH = -1 mA (On, Sl/O) loH = -3 mA (Sl/O) loH = -1 mA (On, Sl/0)
Min loH = -3 mA (Sl/0) loH = -1 mA (On, Sl/O) loH = -3 mA (Sl/0) loL = 20 mA (All outputs)
Min loL = 20 mA (On) loL = 24 mA (Sl/O)
Max V1N = 2.7V (Non 1/0 pins) Max V1N = 7.0V (Non 1/0 pins)
Max V1N = 5.5V (Sl/O)
Max V1N = 0.5V Max Vour = 2.7V (Sl/O)
Max
Max Max o.ov Max Max
Vour = 0.5V (Sl/O)
Vour = ov Vour =Vee Vour = 5.25V Vo= HIGH Vo= LOW
4-548
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
74F
54F
74F
Symbol
Parameter
fmax tPLH tPHL tPHL
tPLH tPHL tpzH tpzL tpHz tpLz tpzH tpzL tpHz tpLz
Maximum Clock Frequency
Propagation Delay STCPto On
Propagation Delay STMR to On
Propagation Delay SHCPto Sl/O
Output Enable Time CS to Sl/0
Output Disable Time CS to Sl/O
Output Enable Time R/WtoSl/O
Output Disable Time R/Wto Sl/O
TA= +25�C Vee= +5.0V
CL= 50 pf
Min
Typ
Max
100
130
3.0
8.0
10.5
3.0
10.5
13.5
6.0
16.5
20.5
4.0
6.5
8.5
4.5
8.0
10.5
5.0
8.5
11.0
5.5
9.0
11.5
3.5
5.5
7.5
3.0
4.5
6.5
4.5
7.5
9.5
4.5
8.0
10.0
3.0
5.5
7.0
2.5
4.0
5.5
TA, Vee= Mil CL= 50 pf
Min
Max
TA, Vee= Com CL= 50 pF
Min
Max
85
2.5
12.0
2.5
15.0
5.5
22.5
3.5
9.5
4.0
12.0
4.0
12.5
4.5
13.0
3.0
8.5
2.5
7.5
4.0
10.5
4.0
11.5
2.5
8.0
2.0
6.5
Fig. Units No. MHz 2-1
ns 2-3 ns 2-3 ns 2-3 ns 2-5
ns 2-5
AC Operating Requirements: See Section 2 for Waveforms
Symbol
Parameter
t5 (H) t5 (L)
th(H) th(L)
t 5 (H) t 5 (L)
th(H) th(L)
Setup Time, HIGH or LOW CS or R/W to STCP
Hold Time, HIGH or LOW CS or R/W to STCP
Setup Time, HIGH or LOW SI/Oto SHCP
Hold Time, HIGH or LOW Sl/OtoSHCP
54F/74F
TA= +25�C Vee= +5.0V
Min
Max
3.5 6.0
0 0
3.0 3.0
3.0 3.0
54F
TA, Vee= Mil
Min
Max
74F
TA, Vee= Com
Min
Max
4.0 7.0
0 0
3.5 3.5
3.5 3.5
Fig. Units No.
ns
2-6
ns
2-6
4-549
~National
~Semiconductor
54F/74F675A
16-Bit Serial-In, Serial/ParallelaOut Shift Register
General Description
The 'F675A contains a 16-bit serial in/serial out shift register and a 16-bit parallel out storage register. Separate serial input and output pins are provided for expansion to longer words. By means of a separate clock, the contents of the shift register are transferred to the .storage register. The contents of the storage register can also be loaded back into the shift register. A HIGH signal on the Chip Select input prevents both shifting and parallel loading.
Features
� Serial-to-parallel converter � 16-Bit serial 1/0 shift register � 16-Bit parallel out storage register � Recirculating parallel transfer � Expandable for longer words � Slim 24 lead package � 'F675A version prevents false clocking through CS or
R/W inputs
Ordering Code: see section 5 Logic Symbols
cs
SI
SHCP
R/W
STCPoo o, 02 03 04 05 Os 07 Oa 09010011012013014015SO
TL/F /9587 -1
IEEE/I EC
STCP
SRG16
~O 07}(M0~/1)CS
1
HOLD 1 SHIFT RIGHT 2 SHIFT RIGHT
J
R/W
&
3 PARALLEL LOAD
ENS
so
SI 8D
8D
26 3 4D
26 8D
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
cs 1
SHCP 2 R/W 3
SI 4 STCP
so 6
Oo 7 01 02 9 03 10 04 11 GND 12
24 Vee
23 015 22 014 21 013 20 012 19 011 18 010 17 Og 16 Os 15 07 14 05 13 05
TL/F/9587-2
Pin Assignment forLCC
02 01 Oo NC SO STCP SI
[j) [QJ m[[] m[[] rn
03 li11
04 Ii]) GND~ NC!]]
05 !ill
Os [j] 07 II�i
[i]R/W
III SHCP
rn cs
ill NC
~Vee ~015
im014
[fil~~llll~~~ Os Og 010 NC 011012013
TL/F/9587-3
4-550
CJ)
.......
Unit Loading/Fan Out: See Section 2 for U.L. definitions
CTI
)>
Pin Names
Description
54F/74F
U.L.
Input l1Hll1L
HIGH/LOW Output loHlloL
SI
cs
SHCP
STCP
R/W
so
Oo-015
Serial Data Input Chip Select Input (Active LOW) Shift Clock Pulse Input (Active Falling Edge) Store Clock Pulse Input (Active Rising Edge) Read/Write Input Serial Data Output Parallel Data Outputs
1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 50/33.3 50/33.3
20 �A/-0.6 mA 20 �A/-0.6 mA 20 �A/-0.6 mA 20 �A/-0.6 mA 20 �A/-0.6 mA -1 mA/20 mA -1 mA/20mA
Functional Description
The 16-Bit shift register operates in one of four modes, as determined by the signals applied to the Chip Select (CS), Read/Write (R/W) and Store Clock Pulse (STCP) input. State changes are indicated by the falling edge of the Shift Clock Pulse (SHCP). In the Shift Right mode, data enters Do from the Serial Input (SI) pin and exits from 0 15 via the Serial Data Output (SO) pin. In the Parallel Load mode, data from the storage register outputs enter the shift register and serial shifting is inhibited.
The storage register is in the Hold mode when either CS or R/W is HIGH. With CS and R/W both LOW, the storage register is parallel loaded from the shift register on the rising edge of STCP.
To prevent false clocking of the shift register, SHCP should be in the LOW state during a LOW-to-HIGH transition of CS. To prevent false clocking of the storage register, STCP should be LOW during a HIGH-to-LOW transition of CS if R/W is LOW, and should also be LOW during a HIGH-toLOW transition of R/W if CS is LOW.
Shift Register Operations Table
Control Inputs
Operating
cs R/W SHCP STCP
Mode
H
x
x
L
L
"""--
L
H
"""--
x
Hold
x
Shift Right
L
Shift Right
L
H
"""--
H
Parallel Load,
No Shifting
Storage Register Operations Table
Inputs
Operating
cs
R/W
STCP
Mode
H
x
x
Hold
L
H
x
Hold
L
L
_r
Parallel Load
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
.../" = LOW-to-HIGH Transition
'-.... = HIGH-to-LOW Transition
Logic Diagram
PE Do
CP
Po-P15
015
so
Oo-015
R/W
16
Do- D15
STCP
CP
Oo-015
Oo-015
I]
TL/F/9587-4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-551
<( Ln
"CD Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required,
please contact the National Semiconductor� Sales
Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to + 7.0V
Input Voltage (Note 2)
-0.5Vto +7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5VtoVee -0.5Vto +5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
V1H
Input HIGH Voltage
V1L
Input LOW Voltage
Veo
Input Clamp Diode Voltage
54F/74F Min Typ Max
Units Vee
Conditions
2.0
v
Recognized as a HIGH Signal
0.8
v
Recognized as a LOW Signal
-1.2
v
Min l1N = -18 mA
VoH
Output HIGH
Voltage
54F 10% Vee 2.5
74F 10% Vee 2.5
74F5% Vee
2.7
loH = -1 mA
v
Min loH = -1 mA
loH = -1 mA
VoL
Output LOW
Voltage
54F 10% Vee 74F 10% Vee
0.5
v
Min loL = 20 mA
0.5
loL = 20 mA
l1H
Input HIGH
54F
Current
74F
20.0 5.0
�A
Max V1N = 2.7V
lsv1
Input HIGH Current 54F
Breakdown Test
74F
100
�A
Max V1N = 7.0V
7.0
lcEX
Output HIGH
54F
Leakage Current
74F
250 50
�A
Max VouT =Vee
V10
Input Leakage
Test
74F
4.75
v
0.0 110 = 1.9 �A
All Other Pins Grounded
loo
Output Leakage 74F
Circuit Current
3.75
�A
0.0 V100 = 150 mV
All Other Pins Grounded
l1L
Input LOW Current
las
Output Short-Circuit Current
-0.6
mA
Max V1N = 0.5V
-60
-150 mA Max VouT = ov
lecH
Power Supply Current
106 160
mA Max Vo= HIGH
lecL
Power Supply Current
106 160
mA Max Vo= LOW
4-552
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
fmax
tpLH tPHL
tPLH tPHL
Maximum Clock Frequency
Propagation Delay STCPtoOn
Propagation Delay SHCPtoSO
74F
TA= +25�C Vee= +5.0V
CL= 50 pF
Min
Typ
Max
100
130
3.0
8.0
10.5
3.0
10.5
13.5
4.0
7.0
9.5
4.5
8.0
10.5
54F
TA, Vee= Mil CL= 50 pF
Min
Max
74F
TA, Vee= Com CL= 50 pF
Min
Max
85
2.5
12.0
2.5
15.0
3.5
10.5
4.0
12.0
Units Fig. No.
MHz 2-1 ns 2-3 ns 2-3
AC Operating Requirements: See Section 2 for Waveforms
Symbol
Parameter
t 5 (H) t 5 (L) th(H) th(L)
t5 (H) t5 (L)
th(H) th(L)
t5 (H) t5 (L)
th(H) th(L)
t5 (H) t5 (L)
th(H) th(L)
t5 (H) t5 (L)
th(H) th(L)
tw(H) tw(L)
tw(H) tw(L)
t5 (L)
th(H)
Setup Time, HIGH or LOW CS or R/W to STCP
Hold Time, HIGH or LOW CS or R/W to STCP
Setup Time, HIGH or LOW SI toSHCP
Hold Time, HIGH or LOW SI toSHCP
Setup Time, HIGH or LOW R/WtoSHCP
Hold Time, HIGH or LOW R/WtoSHCP
Setup Time, HIGH or LOW STCPtoSHCP
Hold Time, HIGH or LOW STCPto SHCP
Setup Time, HIGH or LOW CStoSHCP
Hold Time, HIGH or LOW CStoSHCP
SHCP Pulse Width HIGH or LOW
STCP Pulse Width HIGH or LOW
SHCPtoSTCP
SHCPtoSTCP
74F
TA= +25�C Vee= +5.0V
Min
Max
3.5 5.5
0 0
3.0 3.0
3.0 3.0
6.5 9.0
0 0
7.0 7.0
0 0
3.0 3.0
3.0 3.0
5.0 5.0
6.0 5.0
8.0
0.0
54F
TA, Vee= Mil
Min
Max
74F
TA, Vee= Com
Min
Max
4.0 6.5
0 0
3.5 3.5
3.5 3.5
7.5 10.0
0 0
8.0 8.0
0 0
3.5 3.5
3.5 3.5
6.0 6.0
7.0 6.0
9.0
0.0
Fig. Units No.
ns
2-6
ns
2-6
ns
2-6
ns
2-6
ns
2-6
ns
2-4
ns
2-6
ns
2-6
4-553
~National
~Semiconductor
54F/74F676
16-Bit Serial/Parallel-In, Serial-Out Shift Register
General Description
The 'F676 contains 16 flip-flops with provision for synchronous parallel or serial entry and serial output. When the Mode (M) input is HIGH, information present on the parallel data (P0 -P15) inputs is entered on the falling edge of the Clock Pulse (CP) input signal. When Mis LOW, data is shifted out of the most significant bit position while information present on the Serial (SI) input shifts into the least significant bit position. A HIGH signal on the Chip Select (CS) input prevents both parallel and serial operations.
Features
� 16-bit parallel-to-serial conversion � 16-bit serial-in, serial-out � Chip select control � Slim 24 lead 300 mil package
Ordering Code: see section 5 Logic Symbols
M
so
I E E E / I EC
M
cs
Cii
Po P1 P2 P3 P4
P5 P5 P7 Ps Pg P10 P11 P12 P13 P14 P15 SI
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
TL/F/9588-1
cs 1
C'P
NC SI 4 M 5
so 6
Po 7 P1 8 P2 9 P3 10 P4 11 GND 12
24 Vee 23 P15 22 P14 21 P13 20 P12 19 P11 18 P10 17 P9 16 Ps 15 P7 14 P5 13 P5
TL/F/9588-2
so
TL/F/9588-4
Pin Assignment for LCC
Pz P1 Po NC so M SI
[l] [Q] III [[) IIl [[) [[]
P3 Ii]
P4 [j] GND IJ}]
NC Ii]]
P5 IIID P5 li1J
P7 [j]]
[i] NC
QJC'P
rn cs
[!]NC
B�l Vee Ill! P15
g�] P14
[j]]~~~~~~ Pa P9 Pio NC P11 P12 P13
TL/F/9588-3
4-554
Unit Loading/Fan Out: See Section 2 tor U.L. definitions
ee...nn...
Pin Names
Po-P15
cs
CP M SI
so
Description
Parallel Data Inputs Chip Select Input (Active LOW) Clock Pulse Input (Active LOW) Mode Select Input Serial Data Input Serial Output
54F/74F
U.L.
Input l1Hll1L
HIGH/LOW Output loH/loL
1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 50/33.3
20 �A/-0.6 mA 20 �A/-0.6 mA 20 �A/ - 0.6 mA 20 �A/-0.6 mA 20 �A/-0.6 mA -1 mA/20 mA
Functional Description
The 16-bit shift register operates in one of three modes, as indicated in the Shift Register Operations Table.
HOLD-a HIGH signal on the Chip Select (CS) input prevents clocking, and data is stored in the sixteen registers.
Shift/Serial Load-data present on the SI pin shifts into the register on the falling edge of CP. Data enters the Oo position and shifts toward 01 s on successive clocks, finally appearing on the SO pin.
Parallel Load-data present on Po-P15 are entered into the register on the falling edge of CP. The SO output represents the 0 1s register output. To prevent false clocking, CP must be LOW during a LOWto-HIGH transition of CS.
Block Diagram
Shift Register Operations Table
Control Input
cs
M
CP
H
x
x
L
L
"""--
L
H
"""--
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial "-- = HIGH-to-LOW Transition
Operating Mode
Hold Shift/Serial Load Parallel Load
cs
PE CP
Sl~Do
TL/F/9588-5
4-555
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to+ 7.0V
Input Voltage (Note 2)
-0.5V to + 7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5Vto Vee -0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol V1H V1L Vco VoH
VoL l1H lsv1 lcEX VID loo l1L los Ice
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 74F 10% Vee 74F5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage
74F
Test
Output Leakage
74F
Circuit Current
Input LOW Current
Output Short-Circuit Current
Power Supply Current
54F/74F Min Typ Max 2.0
0.8 -1.2 2.5 2.5 2.7 0.5 0.5 20.0 5.0 100 7.0 250
50
4.75
3.75
-0.6
-60
-150
72
Units
v v v v
v
�A
�A
�A
v
�A mA mA mA
Vee
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal Min l1N = -18 mA loH = -1 mA Min loH = -1 mA loH = -1 mA Min loL = 20mA loL = 20 mA Max V1N = 2.7V
V1N = 7.0V Max
Max VouT =Vee
0.0 110 = 1.9 �A, All Other Pins Grounded
0.0
V100 = 150 mV, All Other Pins Grounded
Max V1N = 0.5V
Max VouT = ov
Max
4-556
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
.ee...nn...
Symbol
Param~ter
fmax
tPLH tPHL
Maximum Clock Frequency
Propagation Delay CPtoSO
74F
TA= +25�C Vee= +5.0V
CL= 50 pF
Min
Typ
Max
100
110
4.5
9.0
11.0
5.0
9.0
12.5
54F
TA, Vee= Mil CL= 50 pF
Min
Max
45
4.5
17.0
5.0
14.5
74F
TA, Vee= Com CL= 50 pF
Fig. Units
No.
Min
Max
90
MHz 2-1
4.5 5.0
12.0 13.5
ns 2-3
AC Operating Requirements: See Section 2 for Waveforms
Symbol
Parameter
t5 (H) t5 (L) th(H) th(L) t5 (H) t5 (L) th(H) th(L) t 5 (H) t5 (L) th(H) th(L) t 5 (L)
th(H)
tw(H) tw(L)
Setup Time, HIGH or LOW SltoCP
Hold Time, HIGH or LOW SltoCP
Setup Time, HIGH or LOW Pn to CP
Hold Time, HIGH or LOW Pn toCP
Setup Time, HIGH or LOW MtoCP
Hold Time, HIGH or LOW MtoCP
Setup Time, LOW CS to CP
Hold Time, HIGH CStoCP
CP Pulse Width HIGH or LOW
74F
TA= +25�C Vee= +5.0V
Min
Max
4.0 4.0
4.0 4.0
3.0 3.0
4.0 4.0
8.0 8.0
2.0 2.0
10.0
10.0
4.0 6.0
54F
TA, Vee= Mil
Min
Max
4.0 4.0
4.0 4.0
3.0 3.0
4.0 4.0
8.0 8.0
2.0 2.0
12.0
10.0
5.0 9.0
74F
TA, Vee= Com
Min
Max
4.0 4.0
4.0 4.0
3.0 3.0
4.0 4.0
8.0 8.0
2.0 2.0
10.0
10.0
4.0 6.0
Fig. Units
No.
ns
2-6
ns
2-6
ns
2-6
ns
2-6
ns
2-4
4-557
U~NaStemiicoonnduactlor
ADVANCE INFORMATION
54F/74F779
8a8it Bidirectional Binary Counter with TRI-STATE� Outputs
General Description
The 'F779 is a fully synchronous 8-stage up/down counter with multiplexed TRI-STATE 1/0 ports for bus-oriented applications. All control functions (hold, count up, count down, synchronous load) are controlled by two mode pins (So. S1). The device also features carry lookahead for easy cascading. All state changes are initiated by the rising edge of the clock.
Features
� Multiplexed TRI-STATE 1/0 ports � Built-in lookahead carry capability � Count frequency 100 MHz typ � Supply current 80 mA typ
Logic Symbols
CET
CP
TC
OE
TL/F/9593-1
IEEE/IEC
CTR DIV 25S
:}'U' ""J Sso,
M- DUOPWHNELO
3 HOLD
CB
EN4
CP
2+/C5
1-
OE
ENS
(1) (2) (4) (8) (16) (32) (64) (128)
4, 5, 6, CT= 256 4,5,6,CT=O
l/Oo 1/01 1/02 1/03 1/04 I/Os I/Os 1/07
TC
TL/F/9593-5
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
1/01 1 1/02 2 1/03 3 GND 4
1/04 I/Os I/Os 7 1/07 8
16 l/Oo 15 CP 14 CET 13 Vee
12 re
11 So 10 S1
9 OE
TL/F/9593-2
Pin Assignment for LCC and PCC
[[] m m 1/03 1/02 NC 1/011/0o C�J [[]
GND (]]
1/04 [j]] NC [TI]
I/Os IJ]] I/Os [j}]
[I]CP
mcrr
[j] NC ~Vee
lI2J fC
~ [j]] !!]] IJll [@]
1/0, OE NC s 1 So
TL/F/9593-3
4-558
~National
~Semiconductor
54F/74F784
8-Bit Serial/Parallel Multiplier with Adder/Subtracter
General Description
The 'F784 is an 8-bit by 1-bit sequential logic element that multiplies two numbers represented in twos complement notation. The device implements Booth's algorithm internally to produce a twos complement product that needs no subsequent correction. In addition to the serial product out-
put (SP), an S � B output is obtained with an internal adder/
subtracter stage which adds a B bit to the SP product. Parallel inputs accept and store an 8-bit multiplicand (Xo-X7). The add/subtract (A/S), Bn and Bn-1 inputs control the internal adder/subtractor stage. The multiplier word is then applied to the Y input in a serial bit stream, least significant bit first. The product is clocked out at the SP output and the
product � B at the S � B output delayed by one clock cycle.
Both appear least significant bit first.
The K input is used for expansion to longer X words, using two or more 'F784 devices by connecting the output (SP) of
one device to the K input of the other device. The Mode Control (M) input is used to establish the most significant device. An asynchronous Parallel Load (PL) input clears the internal flip-flops to the start condition and enables the X latches to accept new multiplicand data. The Parallel Load (PL) also clears the outputs (SP and S � 8).
Features
� Twos complement multiplication � 8-bit by 1-bit sequential logic element � Includes product output (SP) and product � B output
(S�B) � Parallel inputs accept and store an 8-bit multiplicand
(Xo-X7)
a K input is used for expansion to longer X words
� Combines the 'F384 and 'F385 in one chip
Ordering Code: see section 5
Logic Symbol
Connection Diagrams
CP
A/S
SP
StB
TL/F/10230-1
Pin Assignment for DIP and SOIC
20 Yee 19 y
18 x,
17 X5 16 X5 15 X7 14 00
13 A/S
12 K 11 ...
TL/F/10230-2
Pin Assignment for LCC
s�B SP Xo X1 X2
[[][I][�][[]8]
G~~~o~~
t.l(j]
K [j]
A/S Ii]
illBn-1
!ill Vee [IDY
IBJ~[�)[Z]l!]J Bn X7 X6 X5 X4
TL/F/10230-3
Input Loading/Fan-Out: see section 2
Pin Names
CP K M PL Xo-X7 y
A/S Bn Bn-1 S�B SP
Description
Clock Pulse Input (Active Rising Edge) Serial Expansion Input Mode Control Input Asynchronous Parallel Load Input (Active LOW) Multiplicand Data Inputs Serial Multiplier Input Add/Subtract Serial B Input Delayed Serial B Input
Serial X � Y � B Output
Serial X � Y Product Output
54F/74F (U.L.) High/Low
1.0/1.0 1.0/1.0 1.0/1.0 1.0/2.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 50/33.3 50/33.3
l1HlllL loHlloL
20 �A/-0.6 mA 20 �A/-0.6 mA 20 �A/-0.6 mA 20 �A/-1.2 mA 20 �Al - 0.6 mA 20 �A/-0.6 mA 20 �A/-0.6 mA 20 �A/-0.6 mA 20 �A/-0.6 mA -1 mA/20 mA
-1 mA/20 mA
4-559
Functional Description
The 'F784 is a serial-parallel 8-bit multiplier. Also included is an adder/subtractor stage. The X word (multiplicand) is loaded into a register while simultaneously clearing the arithmetic cell flip-flops in preparation for a multiplication. The Y word (multiplier) is clocked in serially. (See Figure A).
Expansion capability is provided via the M and K inputs. The K (cascade) input is connected to the So output of the more significant chip. The M (mode) input is used to determine whether the multiplicand is to be treated as a two's complement or unsigned number.
The 'F784 has logic to enable complex arithmetic to be performed. A serial adder/subtractor enables constants to be added to the product. Typically this feature would be used in FFT butterfly networks to reduce package count and power.
Two outputs are provided: the product XY and the product XY � B. Because of the internal adder/subtractor, a speed advantage is gained when using the 'F784 over using a separate adder and multiplier chip. (Refer to Figure 8).
During a multiplication operation, the first clock cycle is used to load both the X word (multiplicand) and the first bit
of the Y word (operand) into the input registers. At this time there is no valid data at the SP output so that B bits added will not give the correct sum output. In order to load the first B bit on the same clock as X and Y, a Bn-1 input is provided which delays the B data by one clock cycle. Thus, a valid output results.
Inputs
A/S Bn Bn-1
L
H
Cn
Function
Add Cn to product (Cn loaded at the same time as Yn)
L Cn
H
Add Cn to product (Cn must be
delayed one clock cycle)
H
H
Cn Subtract Cn from product (Cn
loaded at the same time as Yn)
H Cn
H
Subtract Cn from product (Cn
must be delayed one clock cycle)
L = LOW Voltage Level H = HIGH Voltage Level Cn = Constant
Inputs
PL
CP
K
M
x,
y
x
x
L
L
x x
x x cs H x x
L
x
x x OP x
H x xxxx
H
i
x x x L
H
i
x x x L
H
i
x xxH
H
i
x x x H
H = HIGH Voltage Level L = LOW Voltage Level j = LOW-to-HIGH Transition
CS = Connected to SP output of high order device
Function Table
Internal
Ya-1
x x
Outputs
SP
S�B
x x
x x
Function
Most Significant Multiplier Device Devices Cascaded in Multiplier String
L
L
L
Load New Multiplicand and Clear
Internal Sum and Carry Registers
x
x
x
Device Enabled
L
p
P�B
Shift Sum Register
H
p
P�B
Add Multiplicand to Sum
Register and Shift
L
p
P�B
Subtract Multiplicand from Sum
Register and Shift
H
p
P�B
Shift Sum Register
OP = Xi latches open for new data {i = 0-7) P = Output as required per Booth's algorithm P�B = Product � a constant {delayed one clock cycle) X = Immaterial
4-560
Logic Diagram
a.00<
(CP)
Pl
SP
s. s..,
A/S ADO SUSlRACT
e ~ ! "7
X7
x,
"' CP
X5 M AOOER A,
SUBTI!ACTOR AND
R�GIST[R$
X4
A4
X3 Al
SUM
~
Xz
x,
At
Ao
Xo
Cii
CP D
'-~~~~~~~~~~~-dlCLR
SUM
a
SU TL/F/ 10230-4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
FIGURE A
4-561
Timing Waveforms
CP
PL
lJ14 tw(I)
:
I
I
Xn
Y or K
SP
A/S
I
Bn-1 Bn
S:l:B
x
I
I
x
-(S�B)o x
FIGURE B
TL/F/10230-5
4-562
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
-55�C to+ 175�C
Vee Pin Potential to Ground Pin
-0.5V to + 7.0V
Input Voltage (Note 2)
-0.5V to + 7.0V
Input Current (Note 2)
-30 mA to + 5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5VtoVcc - 0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
54F/74F Min Typ Max
Units Vee
Conditions
V1H
Input HIGH Voltage
2.0
v
Recognized as a HIGH Signal
V1L
Input LOW Voltage
0.8
v
Recognized as a LOW Signal
Vco
Input Clamp Diode Voltage
-1.2
v
Min l1N = -18 mA
VoH
Output HIGH
Voltage
54F 10% Vee 2.5
74F 10% Vee 2.5
74F 5% Vee
2.7
loH = -1 mA
v
Min loH = -1 mA
loH = -1 mA
VoL
Output LOW
Voltage
54F 10% Vee 74F 10% Vee
0.5
v
Min loL = 20mA
0.5
loL = 20mA
l1H
Input HIGH
54F
Current
74F
20.0
�A Max V1N = 2.7V
5.0
lsv1
Input HIGH Current 54F
Breakdown Test
74F
100 7.0
�A Max V1N = 7.0V
lcEX
Output HIGH
54F
Leakage Current
74F
250
50
�A
Max VouT =Vee
V10
Input Leakage
74F
4.75
Test
v
0.0 110 = 1.9 �A
All Other Pins Grounded
loo
Output Leakage 74F
Circuit Current
3.75
�A
0.0 V100 = 150 mV
All Other Pins Grounded
l1L
Input LOW Current
-0.6
mA Max V1N = 0.5V (Except PL)
-1.2
mA
Max V1N = 0.5V (PL)
los
Output Short-Circuit Current
-60
-150 mA Max VouT =av
Ice
Power Supply Current
70
100
mA Max Vo= HIGH
4-563
AC Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
fmax tPHL
tPHL
tPLH tPHL tPLH tPHL
Maximum Clock Frequency
Propagation Delay PL to SP
Propagation Delay PLto S �8
Propagation Delay CPtoSP
Propagation Delay CPtoS�B
54F/74F
TA= +25�c Vee= +5.0V
CL= 50pF
Min Typ Max
50
65
6.0
10.0 13.0
5.5
9.5
12.0
4.0
6.5
9.0
4.5
8.0
10.5
4.0
7.0
9.0
4.0
7.0
9.0
54F
TA, Vee= Mil
CL= 50 pf
Min
Max
74F
TA, Vee= Com
CL= 50 pf
Min
Max
50
5.0
14.5
4.5
13.5
3.5
10.0
4.0
12.0
3.5
10.0
3.5
10.0
Fig. Units
No.
MHz
2-1
ns
2-3
ns
2-3
ns
2-3
ns
2-3
AC Operating Requirements: see Section 2 for Waveforms
Symbol
t5(H) t 5(L) th(H) th(L) t5(H) t 5 (L) th(H) th(L)
t 5 (H) t 5 (L) th(H) th(L)
t 5 (H) t5 (L) th(H) th(L)
t 5 (H) t5 (L) th(H) th(L)
t5 (H) t 5 (L) th(H) th(L)
tw(L)
tw(H) tw(L)
tree
Parameter
Setup Time, HIGH or LOW KtoCP Hold Time, HIGH or LOW KtoCP Setup Time, HIGH or LOW YtoCP
Hold Time, HIGH or LOW YtoCP Setup Time, HIGH or LOW XtoPL Hold Time, HIGH or LOW Xto PL
Setup Time, HIGH or LOW Bn to CP Hold Time, HIGH or LOW Bn to CP Setup Time, HIGH or LOW A/StoCP
Hold Time, HIGH or LOW A/StoCP
Setup Time, HIGH or LOW Bn-1 to CP Hold Time, HIGH or LOW Bn-1 to CP PL Pulse Width, LOW CP Pulse Width HIGH or LOW
Recovery Time PL to CP
54F/74F
TA= +25�c Vee= +5.0V
Min
Typ
Max
9.0 9.0
2.0 2.0
15.0 15.0
2.0 2.0
3.0 6.0
2.0 4.0
7.0 7.0
0 0
12.0 12.0
0 0
5.0 5.0
1.0 1.0
6.5
7.0 7.0
6.0
54F
TA, Vee= Mil
Min
Max
74F
TA, Vee= Com
Min
Max
10.0 10.0
2.0 2.0
15.0 15.0
2.0 2.0
4.0 7.0
2.0 4.0
8.0 8.0
0 0
13.0 13.0
0 0
5.0 5.0
2.0 2.0
7.0
7.0 7.0
10.0
Units
Fig. No.
ns
2-6
ns
2-6
ns
2-6
ns
2-6
ns
2-6
ns
2-6
ns
2-4
ns
2-4
ns
2-6
4-564
~National Q Semiconductor
54F/74F794
8-Bit Register with Readback
General Description
The 'F794 is an 8-bit register with readback capability designed to store data as well as read the register information back onto the data bus. The 1/0 bus (D bus) has TRISTATE� outputs. Current sinking capability is 64 mA on both the D and Q busses.
Data is loaded into the registers on the low-to-high transition of the clock (CP). The output enable (OE) is used to enable data on Do-07. When OE is low, the output of the registers is enabled on Do-D7, enabling D as an output bus. When
OE is high, 0 0 -07 are inputs to the registers configuring D as an input bus.
Features
� TRI-STATE outputs on the 1/0 port � D and Q output sink capability of 64 mA � Guaranteed 4000V minimum ESD protection � Functionally and pin equivalent to the 'LS794
Ordering Code: See Section 5
Logic Symbol
Connection Diagram
OE CP
Input Loading/Fan-Out
Pin Names
Description
OE CP Do-07
Oo-07
Output Enable Input Clock Pulse Inputs D Bus Inputs/ TRI-STATE Outputs Q Bus Outputs
TL/F/10652-1
DIP, SOIC and Flatpak
OE 1 Do 2
o, 3
D2 4 03 D4 D5 7 Ds D7 GND 10
20 Yee
19 Oo 18 01 17 02 16 03 15 04 14 05 13 Os 12 07 11 CP
TL/F/10652-2
74F High/Low
(U.L.)
Current
1.0/1.0 1.0/1.0 3.5/1.083 750/106.6 750/106.6
20 �A/-0.6 mA 20 �A/-0.6 mA 70 �Al - 650 �A -15 mA/64 mA -15 mA/64 mA
4-565
""e"n"" Truth Table
Inputs
Outputs
CP
OE
Q
D
Lor Hor J,
Lor Hor J..
t t
L
On
Output, 0
H
On
Input
L
On
Output, O*
H
D
Input
*In this case the output of the register is clocked to the inputs and the overall Q output is unchanged at On.
Logic Diagram
to---- .___ _C.
CP
4-566
TL/F/10652-3
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
-65�C to+ 150�C
Ambient Temperature under Bias
-55� to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5Vto +7.0V
Input Voltage (Note 2)
-0.5V to+ 7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
ESD Last Passing Voltage (Min)
4000V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Voltage Applied to Output In HIGH State (with Vee = OV) Standard Output TRI-STATE Output
-0.5V to Vee -0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
Twice the Rated loL (mA)
ESD Last Passing Voltage (Min)
4000V
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto 70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Characteristics over Operating Temperature Range unless otherwise specified
Symbol
Parameter
54F/74F
Units Vee
Min
Typ
Max
Conditions
V1H
Input HIGH
Voltage
2.0
v
Recognized as
a HIGH Signal
V1L
Input LOW
Voltage
0.8
v
Recognized as a LOW Signal
Vco
Input Clamp
Diode Voltage
-1.2
v
Min
l1N = -18 mA
VoH
Output HIGH
Voltage
2.4
2.8
2.0
2.44
v
Min
loH = -3 mA
loH = -15 mA
VoL
Output LOW
Voltage
0.45
0.55
v
loL = 64 mA Min
l1H
Input HIGH
54F
Current
74F
20.0
V1N = 2.7V
5.0
�A
Max
lsv1
Input HIGH Current
54F
Breakdown Test
74F
100
V1N = 7.0V (OE, CP)
�A
Max
7.0
lsv1r
Input HIGH Current
54F
Breakdown (1/0)
74F
1.0
mA
Max
V1N = 5.5V (00 )
0.5
leEx
Output HIGH
54F
Leakage Current
74F
250 50
�A
Max
Vour =Vee
V10
Input Leakage
74F
4.75
Test
v
0.0
110 = 1.9 �A
All Other Pins Grounded
loo
Output Leakage
74F
Circuit Current
3.75
�A
0.0
V100 = 150 mV
All Other Pins Grounded
l1L
Input LOW
Current
-0.6
mA
V1N = 0.5V
Max
(OE,CP)
4-567
DC Characteristics over Operating Temperature Range unless other specified (Continued)
Symbol
Parameter
54F/74F
Min
Typ
Max
Units
Vee
los
Output Short-
Circuit Current
-100
-225
mA
Max
l1H +
lozH
l1L +
lozL
Output Leakage Current
Output Leakage Current
70
�A
Max
-650
�A
Max
V10
Input Leakage 74F
Test
4.75
v
0.0
loo
Output Circuit 74F
Leakage Current
3.75
�A
0.0
lzz
lccH lccL lccz
Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current
100
�A
0.0
65
mA
Max
80
mA
Max
80
mA
Max
Conditions
VouT = ov
VouT = 2.7V (On) VouT = 0.5V (On) 110 = 1.9 �A All Other Pins Grounded V100 = 150 mV All Other Pins Grounded VouT = 5.25V
Vo= HIGH Vo= LOW Vo= HIGHZ
AC Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
fMAX tPLH tPHL tPZH tpzL tpHz tpLz t 5 (H) t5(L) th(H) th(L) tw(H
Parameter
Max. Clock Frequency Propagation Delay CPtoQn Output Enable Time
Output Disable Time
Setup Time, HIGH or LOW Bus to Clock Hold Time, HIGH or LOW Bus to Clock Clock Pulse Width HIGH or LOW
74F
TA= +25�C Vee= +5.0V
CL= 50 pf
Min Typ Max
90
2.5
7.0
2.5
8.0
2.3
8.5
2.0
10.0
1.0
7.0
1.0
7.0
4.0 4.0
1.5 1.5
5.8 5.8
54F
TA. Vee= Mil
Min
Max
74F
TA, Vee= Comm
CL= 50 pf
Min Max
90
2.5
8.0
2.5
9.0
2.0
9.0
2.0 10.5
1.0
8.0
1.0
8.0
4.0 4.0
1.5 1.5
5.8 5.8
Units
MHz ns ns ns ns ns ns
Fig. No.
2-1 2-3 2-5 2-5 2-6 2-6 2-14
4-568
~National
U Semiconductor
54F/74F821 10-Bit D-Type Flip-Flop
General Description
The 'F821 is a 10-bit D-type flip-flop with TRI-STATE� true outputs arranged in a broadside pinout. The 'F821 is tunetionally and pin compatible with the AMD's Am29821.
Features
� TRI-STATE Outputs � Direct replacement for AMD's Am29821
Ordering Code: see Section 5
Logic Symbols
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
Do D1 D2 03 D4 05 05 Di Da Dg
OE
ep
Oo 01 02 03 04 05 05 07 Os Og
TL/F/9595-1
IEEE/I EC
OE
CP
Do
Oo
o,
01
D2
02
03
03
04
04
D5
05
Ds
05
DJ
07
Da
Oa
Dg
Og
TL/F/9595-5
OE 1
Do 2
o, 3
D2 4 D3 5
04
D5 Ds 8
DJ 9
Ds 10 Dg 11 GND 12
24 Yee
23 Oo 22 01 21 02 20 03 19 04 18 05 17 Os 16 07 15 Os 14 Og 13 CP
TL/F/9595-2
Unit Loading/Fan Out: See Section 2 tor u.L. Definitions
Pin Names
Do-Dg OE
CP Oo-Og
Description
Data Inputs Output Enable TRI-STATE Input Clock Input TRI-STATE Outputs
U.L. HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0 150/40 (33.3)
54F/74F Input l1Hll1L
Output loHllOL 20 �A/-0.6 mA
20 �A/-0.6 mA
20 �A/-0.6 mA -3.0 mA/24 mA (20 mA)
Pin Assignment forLCC
DJ Ds o5 NC 04 D3 D2
[j] [Q] []] []] [[] [I] [[]
Os li11
Dg Ii]
GND 11iJ
NC Ii]] CP [j] Og Ii]
05 Ii]]
mo,
[}]Do
[I] OE
[II NC
Im Yee lllJ Oo
~o,
li]]~~~l~H~�I 07 Os 05 NC 04 03 02
TL/F/9595-3
4-569
Functional Description
The 'F821 consists of ten D-type edge-triggered flip-flops. This device has TRI-STATE true outputs for bus systems organized in a broadside pinning. The buffered Clock (CP) and buffered Output Enable (OE) are common to all flipflops. The flip-flops will store the state of their individual D inputs that meet the setup and hold times requirements on the LOW-to-HIGH CP transition. With the OE LOW the content of the flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops.
Logic Diagram
Function Table
Inputs
Internal
OE CP D
Q
H H x NC H L x NC
H ..../ L
H
H ..../ H
L
L ..../ L
H
L ..../ H
L
L H x NC
L L x NC
L = LOW Voltage Level
H = HIGH Voltage Level
X = Immaterial Z = High Impedance .../" = LOW-to-HIGH Transition NC = No Change
Output
0
z z z z
L
H
NC
NC
Function
Hold Hold Load Load Data Available Data Available No Change in Data No Change in Data
Dg
CP
o,
Og
TL/F /9595-4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-570
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vcc Pin Potential to Ground Pin
-0.5V to + 7.0V
Input Voltage (Note 2)
-0.5Vto +7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
-0.5VtoVec
-0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
....CX>
I\)
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
Input HIGH Voltage
Input LOW Voltage
Vco
Input Clamp Diode Voltage
54F/74F Min Typ Max 2.0
0.8 -1.2
Units Vee
v
v
v
Min
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal l1N = -18mA
VoH
Output HIGH
Voltage
54F 10% Vee 2.5
54F 10% Vee 2.4
74F 10% Vee 2.5
74F 10% Vee 2.4
74F5% Vee
2.7
74F5% Vee
2.7
loH = -1 mA
loH = -3 mA
v
loH = -1 mA Min
loH = -3 mA
loH = -1 mA
loH = -3 mA
Output LOW Voltage
54F 10% Vee 74F 10% Vee
0.5
v
Min loL = 20 mA
0.5
loL = 24 mA
Input HIGH Current 54F 74F
20.0
�A
Max V1N = 2.7V
5.0
lsv1
Input HIGH Current 54F
Breakdown Test
74F
100 7.0
�A
Max V1N = 7.0V
le Ex
Output HIGH
54F
Leakage Current
74F
250
�A
Max Vour =Yee
50
Input Leakage Test
74F
4.75
v
110 = 1.9 �A,
0.0
All Other Pins Grounded
loo
Output Leakage 74F
Circuit Current
3.75
�A
V100 = 150 mV
0.0
All Other Pins Grounded
Input LOW Current
-0.6
mA
Max Y1N = 0.5V
lozH lozL las lcez
Output Leakage Current Output Leakage Current Output Short-Circuit Current Power Supply Current
50
�A
Max Vour = 2.7V
-50
�A
Max Your= 0.5V
-60
ov -150
mA
Max Vour =
78
100
mA
z Max Vo = HIGH
4-571
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
fmax
tPLH tPHL
tpzH tpzL
tpHZ tpLZ
Maximum Clock Frequency
Propagation Delay CPto On
Output Enable Time OE to On
Output Disable Time OE to On
74F
TA= +25�C Vee= +5.0V
CL= 50pF
Min
Typ
Max
100
150
2.0
6.4
9.5
2.0
6.2
9.5
2.0
5.8
10.5
2.0
6.3
10.5
1.5
3.4
7.0
1.5
3.5
7.0
54F
TA, Vee= Mil CL= 50pF
Min
Max
60
2.0
10.5
2.0
10.5
2.0
13.0
2.0
13.0
1.0
7.5
1.0
7.5
74F
TA, Vee= Com CL= 50 pF
Min
Max
70
2.0
10.5
2.0
10.5
2.0
11.5
2.0
11.5
1.5
7.5
1.5
7.5
Units
Fig. No.
MHz 2-1 ns 2-3
ns 2-5
AC Operating Requirements: See Section 2 for Waveforms
Symbol
Parameter
t5(H) t 5(L)
th(H) th(L)
tw(H) tw(L)
Setup Time, HIGH or LOW DntoCP
Hold Time, HIGH or LOW DntoCP
CP Pulse Width HIGH or LOW
74F
TA= +25�C Vee= +s.ov
Min
Max
2.5 2.5
2.5 2.5
5.0 5.0
54F
TA, Vee= Mil
Min
Max
4.0 4.0
2.5 2.5
6.0 6.0
74F
TA, Vee= Com
Min
Max
3.0 3.0
2.5 2.5
6.0 6.0
Units Fig. No.
ns
2-6
ns
2-4
4-572
D~NaStemiicoonnduactlor
54F/74F823
9-Bit D-Type Flip-Flop
General Description
The 'F823 is a 9-bit buffered register. It features Clock Enable and Clear which are ideal for parity bus interfacing in high performance microprogramming systems.
The 'F823 is functionally and pin compatible with AMD's Am29823.
Features
� TRI-STATE� outputs � Clock Enable and Clear � Direct replacement for AMD's Am29823
Ordering Code: see Section 5
Logic Symbols
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
TL/F/9596-2
IEEE/IEC
6E CLii EN
CP
Do
Oo
o,
o,
D2
02
D3
03
04
04
D5
05
Ds
Os
07
07
Ds
Os
TL/F/9596-1
OE
Do
o, 3
D2 4 D3 5� D4 6 D5 7 Ds 8
Di 9
Ds 10
CLii 11
CND 12
24 Vee 23 Oo
22 o,
18 05 17 Os 16 07 15 Os
14 EN
13 CP
TL/F/9596-3
Unit Loading/Fan Out: See section 2 for u.L definitions
Pin Names
Do-Da OE CLR CP EN Oo-Oa
Description
Data Inputs Output Enable Input Clear Clock Input Clock Enable TRI-STATE Outputs
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loH/loL
1.0/1.0 1.0/1.0 1.0/1.0 1.0/2.0 1.0/1.0 150/40 (33.3)
20 �Al - 0.6 mA 20 �A/ - 0.6 mA 20 �Al - 0.6 mA 20 �A/-1.2 mA 20 �A/-0.6 mA -3 mA/24 mA (20 mA)
Pin Assignment for LCC
0., Ds c5 NC D4 03 D2
(j][Q][[](fil[Z][[)~
Ds lill ill ff]
CND~
NC�
CPI]]
EN lill Os lilll
mo,
[I] Do
III OE
[j] NC
~Vee Ill] Oo ~o,
[j]~~~~~� 07 Os 05 NC 04 03 02
TL/F/9596-4
4-573
(") C\I
co Functional Description
The 'F823 device consists of nine D-type edge-triggered flip-flops. It has TRI-STATE true outputs and is organized in broadside pinning. The buffered Clock (GP) and buffered Output Enable (OE) are common to all flip-flops. The flipflops will store the state of their individual D inputs that meet the setup and hold times requirements on the LOW-to-HIGH GP transition. With the OE LOW the contents of the flipflops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. In addi-
tion to the Clock and Output Enable pins, the 'F823 has Clear (CLR) and Clock Enable (EN) pins.
When the CLR is LOW and the OE is LOW, the outputs are LOW. When CLR is HIGH, data can be entered into the flipflops. When EN is LOW, data on the inputs is transferred to the outputs on the LOW to HIGH clock transition. When the EN is HIGH, the outputs do not change state regardless of the data or clock inputs transitions. This device is ideal for parity bus interfacing in high performance systems.
Inputs
OE CLR EN CP
H
H
L
H
H
H
L
L
H
H
H
x
L
H
H x
H L xx
L L xx
H
H
L _r
H
H
L _r
L
H
L _r
L
H
L _r
L
H
L
H
L
H
L
L
L = LOW Voltage Level
H = HIGH Voltage Level X = Immaterial Z = High Impedance _,r = LOW-to-HIGH Transition NC = No Change
Function Table
Internal Output
D
Q
0
x
NC
z
x
NC
z
x
NC
z
x
NC
NC
x
H
z
x
H
L
H
H
z
H
L
z
L
H
L
H
L
H
x
NC
NC
x
NC
NC
-
Function
Hold Hold Hold Hold Clear Clear Load Load Data Available Data Available No Change in Data No Change in Data
Logic Diagram
Os TL/F/9596-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-574
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to + 7.0V
Input Voltage (Note 2)
-0.5Vto +7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
-0.5VtoVee -0.5Vto +5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol V1H V1L Veo VoH
VoL l1H lsv1 leEx V10 loo l1L lozH lozL los lzz leez
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee 74F5% Vee 74F5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage 74F
Test
Output Leakage
74F
Circuit Current
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Buss Drainage Test
Power Supply Current
54F/74F Min Typ Max
2.0
0.8 -1.2
2.5 2.4 2.5 2.4 2.7 2.7
0.5 0.5
20.0 5.0
100 7.0
250 50
4.75
3.75
-0.6 -1.2
50 -50
-60
-150
500
75
100
Units
v v v
v
v
�A
�A
�A
v
�A mA mA �A �A mA �A mA
Vee
Min
Min
Min Max Max Max 0.0 0.0 Max Max Max Max Max
o.ov
Max
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal l1N = -18 mA loH = -1 mA loH= -3mA loH = -1 mA loH = -3mA loH = -1 mA loH = -3mA loL = 20 mA loL = 24mA V1N = 2.7V
V1N = 7.0V
VouT =Vee
110 = 1.9 �A All Other Pins Grounded V100 = 150 mV All Other Pins Grounded V1N = 0.5V (OE, CLR, EN) V1N = 0.5V (CP) VouT = 2.7V VouT = 0.5V
VouT = ov
VouT = 5.25V Vo= HIGHZ
4-575
a
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
fmax tPLH tPHL tPHL
tpzH tpzL tpHz tpLZ
Maximum Clock Frequency
Propagation Delay CPto On
Propagation Delay CLR to On
Output Enable Time OE to On
Output Disable Time OE to On
74F
TA= +25�C Vee= +5.0V
CL= 50 pF
Min
Typ
Max
100
160
2.0
5.6
9.5
2.0
5.2
9.5
4.0
7.1
12.0
2.0
5.8
10.5
2.0
5.5
10.5
1.5
2.9
7.0
1.5
2.7
7.0
54F
TA, Vee= Mil CL= 50 pF
Min
Max
60
2.0
10.5
2.0
10.5
4.0
13.0
2.0
13.0
2.0
13.0
1.0
7.5
1.0
7.5
74F
TA, Vee= Com CL= 50pF
Min
Max
70
2.0
10.5
2.0
10.5
4.0
13.0
2.0
11.5
2.0
11.5
1.5
7.5
1.5
7.5
Units
Fig. No.
MHz 2-1 ns 2-3 ns 2-3
ns 2-5
AC Operating Requirements: See Section 2 for Waveforms
Symbol
Parameter
t 5 (H) t5 (L) th(H) th(L)
t 5 (H) t5 (L) th(H) th(L)
tw(H) tw(L)
tw(L)
tree
Setup Time, HIGH or LOW DntoCP
Hold Time, HIGH or LOW Dn toCP Setup Time, HIGH or LOW EN toCP
Hold Time, HIGH or LOW ENtoCP
CP Pulse Width HIGH or LOW
CLR Pulse Width, LOW
CLR Recovery Time
74F
TA= +25�C Vee= +5.0V
Min
Max
2.5 2.5
2.5 2.5
4.5 2.5
2.0 0
5.0 5.0
5.0
5.0
54F
TA, Vee= Mil
Min
Max
4.0 4.0
2.5 2.5
5.0 3.0
3.0 1.0
6.0 6.0
5.0
5.0
74F
TA, Vee= Com
Min
Max
3.0 3.0
2.5 2.5
5.0 3.0
2.0 0
6.0 6.0
5.0
5.0
Fig. Units No.
ns
2-6
ns
2-6
ns
2-4
ns
2-4
ns
2-6
4-576
Q)
N
~National
CJ1
~Semiconductor
54F/74F825 8-Bit D-Type Flip-Flop
General Description
The 'F825 is an 8-bit buffered register. It has Clock Enable and Clear features which are ideal for parity bus interfacing in high performance microprogramming systems. Also included in the 'F825 are multiple enables that allow multiuser control of the interface.
The 'F825 is functionally and pin compatible with AMD's Am29825.
Features
� TRI-STATE� output � Clock enable and clear � Multiple output enables � Direct replacement for AMD's Am24825
Ordering Code: see section 5 Logic Symbols
Connection Diagrams
OE1 Do D1 D2 D3 D4 Ds Ds I?
OE2 OE3 eLR ep
EN Oo 01 02 03 04 05 05 07
TL/f/9597-1
IEEE/I EC
OE1
OE2
EN
OE3
CIR
EN ep
Pin Assignment for DIP, SOIC and Flatpak
OE1 6E2
Do 3 D1 D2 5 D3 6 D4 D5 D5 9 D1 10 CLR 11 GND 12
24 Vee
23 OE3 22 Oo 21 01 20 02 19 03 18 04 17 05 16 Os 15 07
1"' EN
13 CP
TL/F/9597-2
Pin Assignment for LCC
Ds D5 D4 NC D3 D2 D1 [j] [@] [[] []] [I] []] [fil
I? li1I
CLR Ii]
GND 181 NC !ill
CP [�]
ENlill
07 Ii]]
l:IIDo
Ill 6E2 III 6E1 ill NC
~Vee
lllJ OE3 !lli Oo
lffil~ITII~~~~ Os 05 04 NC 03 02 0 1
TL/f/9597-3
Do
Oo
D1
01
D2
02
03
03
D4
04
D5
05
06
06
I?
07
TL/F /9597 - 4
Unit Loading/Fan Out: See Section 2 for u.L. Definitions
54F/74F
Pin Names
Description
U.L. HIGH/LOW
Input l1Hll1L Output loHlloL
Do-D7
Data Inputs
1.0/1.0
20 �A/-0.6 mA
Oo-01
TRI-STATE Data Outputs 150/40 (33.3) -3 mA/24 mA (20 mA)
OE1, OE2, OE3 Output Enable Input
1.0/1.0
20 �A/-0.6 mA
EN
Clock Enable
1.0/1.0
20 �A/-0.6 mA
CLR
Clear
1.011.0
20 �A/-0.6 mA
CP
Clock Input
1.0/2.0
20 �A/-1.2 mA
4-577
ll)
cCo\I Functional Description
The 'F825 consists of eight D-type edge-triggered flip-flops. This device has TRI-STATE true outputs and is organized in broadside pinning. In addition to the clock and output enable pins, the buffered clock (CP) and buffered Output Enable (OE) are common to all flip-flops. The flip-flops will store the state of their individual D inputs that meet the setup and hold times requirements on the LOW-to-HIGH CP transition. With the OE LOW the contents of the flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE
input does not affect the state of the flip-flops. The 'F825 has Clear (CLR) and Clock Enable (EN) pins.
When the CLR is LOW and the OE is LOW the outputs are LOW. When CLR is HIGH, data can be entered into the flipflops. When EN is LOW, data on the inputs is transferred to the outputs on the LOW-to-HIGH clock transition. When the EN is HIGH the outputs do not change state, regardless of the data or clock input transitions.
Function Table
Inputs
Internal
OE
CLR
EN
CP
D
Q
H
H
L
H
x
NC
H
H
L
L
x
NC
H
H
H
x x
NC
L
H
H
x x
NC
H
L
x xx
H
L
L
x xx
H
H
H
L
__r
L
H
H
H
L
__r
H
L
L
H
L
__r
L
H
L
H
L
__r
H
L
L
H
L
H
x
NC
L
H
L
L
x
NC
L = LOW Voltage Level
H = HIGH Voltage Level X = Immaterial
Z = High Impedance
.../" = LOW-to-HIGH Transition
NC = No Change
Output
0
z z z
NC
z
L
z z
L H NC NC
Function
Hold Hold Hold Hold Clear Clear Load Load Data Available Data Available No Change in Data No Change in Data
Logic Diagram
TL/F/9597-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-578
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
-55�C to+ 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to + 7.0V
Input Voltage (Note 2)
-0.5V to + 7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
-0.5VtoVee -0.5Vto +5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol V1H V1L Veo VoH
VoL l1H lsv1 leEx V10 loo l1L lozH lozL los lzz leez
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee 74F5% Vee 74F5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage 74F
Test
Output Leakage
Circuit Current
74F
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Buss Drainage Test
Power Supply Current
54F/74F
Min Typ Max
2.0
0.8 -1.2
2.5 2.4 2.5 2.4 2.7 2.7
0.5 0.5
20.0 5.0 100 7.0
250 50
4.75
3.75
-0.6
50
-50
-60
-150
500
75
90
Units
v v v
v
v
�A
�A
�A
v
�A mA �A �A mA �A mA
Vee
Min
Min
Min Max Max Max 0.0 0.0 Max Max Max Max
o.ov
Max
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal l1N = -18 mA loH = -1 mA loH = -3mA loH = -1 mA loH = -3 mA loH = -1 mA loH = -3mA loL = 20 mA loL = 24mA V1N = 2.7V
V1N = 7.0V
Vour =Vee
110 = 1.9 �A All Other Pins Grounded V100 = 150 mV All Other Pins Grounded V1N = 0.5V Vour = 2.7V Vour = 0.5V
Vour = ov
Vour = 5.25V Vo= HIGHZ
4-579
Lt>
Cco\I AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
fmax tPLH tPHL tPHL
tpzH tpzL tpHz tpu
Maximum Clock Frequency
Propagation Delay CPto00 Propagation Delay CLR to00 Output Enable Time OE to 0 0 Output Disable Time OE to On
74F
TA= +25�C Vee= +5.0V
CL= 50pF
Min
Typ
Max
100
160
2.0
6.5
9.5
2.0
6.6
9.5
4.0
7.4
12.0
2.0
6.5
10.5
2.0
6.6
10.5
1.5
3.5
7.0
1.5
3.3
7.0
54F
TA, Vee= Mil CL= 50pF
Min
Max
60
2.0
10.5
2.0
10.5
4.0
13.0
2.0
13.0
2.0
13.0
1.0
7.5
1.0
7.5
74F
TA, Vee= Com CL= 50pF
Fig. Units
No.
Min
Max
70
MHz 2-1
2.0
10.5
ns 2-3
2.0
10.5
4.0
13.0
ns 2-3
2.0
11.5
2.0
11.5
ns 2-5
1.5
7.5
1.5
7.5
AC Operating Requirements: See Section 2 for Waveforms
Symbol
Parameter
t 5 (H) t 5 (L) th(H) th(L)
t 5 (H) t 5 (L) th(H) th(L)
tw(H) tw(L)
tw(L)
tree
Setup Time, HIGH or LOW Dn to CP
Hold Time, HIGH or LOW Dn toCP
Setup Time, HIGH or LOW ENtoCP
Hold Time, HIGH or LOW EN to CP
CP Pulse Width HIGH or LOW
CLR Pulse Width, LOW
CLR Recovery Time
74F
TA= +25�C Vee= +5.0V
Min
Max
2.5 2.5
2.5 2.5
4.5 2.5
2.0 0
5.0 5.0
5.0
5.0
54F
TA, Vee= Mil
Min
Max
4.0 4.0
2.5 2.5
5.0 3.0
3.0 2.0
6.0 6.0
5.0
5.0
74F
TA, Vee= Com
Min
Max
3.0 3.0
2.5 2.5
5.0 3.0
1.0 0
6.0 6.0
5.0
5.0
Fig. Units
No.
ns
2-6
ns
2-6
ns
2-4
ns
2-4
ns
2-6
4-580
U~NaStemiicoonnduactlor
54F/74F827 � 54F/74F828 10-Bit Buffers/Line Drivers
General Description
The 'F827 and 'F828 10-bit bus buffers provide high performance bus interface buffering for wide data/address paths or buses carrying parity. The 10-bit buffers have NOR output enables for maximum control flexibility.
The 'F827 and 'F828 are functionally- and pin-compatible to AMD's Am29827 and Am29828. The 'F828 is an inverting version of the 'F827.
Features
� TRI-STATE� output � 'F828 is inverting � Direct replacement for AMD's Am29827 and Am29828
Ordering Code: see section 5
Connection Diagrams
Pin Assignment for DIP, Flatpak and SOIC
'F827
fil1 Do D1 3 D2 4 D3 5 D4 D5 D5 8 D1 9 D5 10 D9 11 GND 12
24 Vee
23 Oo 22 01 21 02 20 03 19 04 18 05 17 05 16 07 15 05 14 09 13 OE2
TL/F/9598-1
Pin Assignment for LCC 'F827
m m D7 D6 05 NC D4 D3 D2
!ITI [QI [�] [IJ ffil
D5 ij] D9 Ii]
GND 1BJ
NC [ill
OE2 Ii]] 09 [j] 05 Ii]]
0D1
rn Do
[IJOE1 [I] NC
~Vee
Ill] Oo
g�J 01
[j]]@l[Ij]~~~~ 07 06 05 NC 04 03 02
TL/F/9598-2
'F828
fil1 1 Do 2 D1 3 D2 D3 D4 D5 D5 8 D1 9 Ds 10 D9 11 GND 12
24 Vee 23 Bo
22 01 21 02 20 03 19 04 18 05 17 05 16 07 15 05 14 09 13 OE2
TL/F/9598-8
'F828
m m D1 D6 o5 NC 04 D3 D2
!ITI [QI [�] [IJ ffil
D5 ij] D9 Ii]
GND 1BJ
NC [ill
DE2 !Ifil
09 [j]
05 Ii]]
0D1 Q] Do
mBE1
[I] NC
~Vee
llll 60
g�J 01
[j]]@l[Ij]~~~~ 07 05 05 NC 04 03 02
TL/F/9598-9
D
4-581
co
cN o
�.......
Logic Symbols
cN o
IEEE/I EC
'F827
IEEE/I EC 'F828
'F827
TL/F/9598-6
TL/F/9598-3
'F828
TL/F/9598-7
TL/F/9598-10
4-582
ClO
Unit Loading/Fan Out: See Section 2 tor U.L. definitions
N......
�
54F/74F
ClO N
ClO
Pin Names
Description
U.L.
Input l1Hll1L
HIGH/LOW
Output loH/loL
OE1, OE2 Do-D7 Oo-07
Output Enable Input
1.0/1.0
20 �A/ -0.6 mA
Data Inputs
1.0/1.0
20 �A/ - 0.6 mA
Data Outputs, TRI-STATE 600/106.6 (80) -12 mA/64 mA (48 mA)
Functional Description
The 'F827 and 'F828 are line drivers designed to be employed as memory address drivers, clock drivers and busoriented transmitters/receivers which provide improved PC board density. The devices have TRI-STATE outputs controlled by the Output Enable (OE) pins. The outputs can sink 64 mA (48 mA mil) and source 15 mA. Input clamp diodes limit high-speed termination effects.
Logic Diagrams
Function Table
Inputs
Outputs
OE
Dn
On
'F827
'F828
L
H
H
L
L
L
L
H
H
x
z
z
H = HIGH Voltage level L = LOW Voltage Level
Z = High Impedance
X = Immaterial
Function
Transparent Transparent HighZ
'F827
Dg
D4
Do
Og
07
01
TL/F/9598-4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
'F828
TL/F /9598-11 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-583
co
cCo'\I
..�....
Absolute Maximum Ratings (Note 1)
If MilitaryI Aerospace specified devices are required,
cCo'\I
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
-55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to+ 7.0V
Input Voltage (Note 2) �
-0.5V to + 7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
-0.5VtoVee -0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
V1H V1L Vco VoH
Vol l1H lsv1 leEX V10 loo l1L lozH lozL los
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee 74F5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage 74F
Test
Output Leakage 74F
Circuit Current
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
54F/74F Min Typ Max 2.0
0.8 -1.2
2.4 2.0 2.4 2.0 2.7
0.55 0.55
20.0 5.0
100 7.0
250 50
4.75
-100
3.75
-0.6 50 -50
-225
Units
v v v
v
v
�A
�A
�A
v
�A mA �A �A mA
Vee
Min
Min
Min Max Max Max 0.0 0.0 Max Max Max Max
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal l1N = -18mA loH = -3 mA loH = -12mA loH = -3 mA loH = -15 mA loH = -3mA loL = 48 mA loL = 64 mA V1N = 2.7V
V1N = 7.0V
Vour =Vee
110 = 1.9 �A All Other Pins Grounded V100 = 150 mV All Other Pins Grounded V1N = 0.5V VouT = 2.7V Vour = 0.5V
Vour = ov
4-584
DC Electrical Characteristics (Continued)
Symbol
Parameter
54F/74F
Units
Vee
Min
Typ
Max
co
.N....
c�o
Conditions
cN o
lzz
Bus Drainage Test
5aa
�A
a.av
VouT = 5.25V
lccH
Power Supply Current ('F827)
3a
45
mA
Max
Vo= HIGH
lccL
Power Supply Current ('F827)
6a
9a
mA
Max
Vo= LOW
Jeez
Power Supply Current ('F827)
4a
6a
mA
Max
Vo= HIGHZ
lccH
Power Supply Current ('F828)
14
2a
mA
Max
Vo= HIGH
lccL
Power Supply Current ('F828)
56
85
mA
Max
Vo= LOW
lccz
Power Supply Current ('F828)
35
5a
mA
Max
Vo= HIGHZ
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
tPLH tpHL
tPLH tPHL
tpzH tpzL
tpHz tpLz
Propagation Delay Data to Output ('F827)
Propagation Delay Data to Output ('F828)
Output Enable Time OE to On
Output Disable Time OE to On
74F
TA= +25�C Vee= +5.0V
CL= 50pF
Min
Typ
Max
1.a
3.a
5.5
1.5
3.3
5.5
1.0
3.a
5.a
1.0
2.0
4.a
3.a
5.7
9.a
3.5
6.8
11.5
1.5
3.3
8.0
1.0
3.5
8.a
54F
TA, Vee= Mil CL= 50 pF
Min
Max
1.0
7.5
1.5
7.0
1.0
6.5
1.0
5.0
2.5
10.0
3.0
12.5
1.5
9.0
1.a
9.0
74F
TA, Vee= Com CL= 50 pF
Min
Max
1.0
6.5
1.5
6.0
1.0
5.5
1.0
4.0
2.5
9.5
3.0
12.0
1.5
8.5
1.0
8.5
Fig. Units
No.
ns 2-3 ns 2-3 ns 2-5 ns 2-5
4-585
~National
~Semiconductor
PRELIMINARY
54F/74F841
10-Bit Transparent Latch
General Description
The 'F841 bus interface latch is designed to eliminate the extra packages required to buffer existing latches and provide extra data width for wider address/data paths or buses carrying parity. The 'F841 is a 10-bit transparent latch, a 1Obit version of the 'F373.
The 'F841 is functionally and pin compatible to AMD's Am29841.
Features
� TRI-STATE� output � Direct replacement for AMD's Am29841
Ordering Code: see section 5
Logic Symbols
Connection Diagrams
Do D1 Dz D3 D4 D5 D5 D1 De Dg OE LE
Og Os 07 05 05 04 03 Oz 01 Oo
TL/F/9599-1
I E E E / I EC
5E
LE
Do
Oo
D1
01
Dz
Oz
D3
03
D4
04
D5
05
D5
05
~
07
De
Os
Dg
Og
TL/F/9599-5
Pin Assignment for DIP, SOIC and Flatpak
CiE 1
Do 2 D1 3 Dz 4 D3 5 D4 6 D5 7 Ds 8 ~ 9 Ds 10 Dg 11 GND 12
24 Yee 23 Do
22 o,
21 Oz 20 03 19 04 18 05 17 Os 16 07 15 Os 14 Og 13 LE
Pin Assignment for LCC
D7
lTil
D6 ffQJ
rDn5
NC
l!I
D4 D3
ml!I
Dz
rn
Ds@ Dg Ii}]
GND 1GJ
NC~
LE[�] Og Ii] Os[�]
IIJD1
rn Do
[IJOE OJ NC
~Yee
lllJ Oo
~01
ff2l@l~llll~~rm 07 06 05 NC 04 03 Oz
TL/F/9599-3
TL/F/9599-2
Unit Loading/Fan Out: See Section 2 for U.L. Definitions
Pin Names
Do-Dg Oo-Og OE LE
Description
Data Inputs TRI-STATE Outputs Output Enable Input Latch Enable
54F/74F
U.L. HIGH/LOW
Input l1H/l1L Output loHllOL
1.0/1.0 150/40 (33.3)
1.0/1.0 1.0/1.0
20 �A/ -0.6 mA -3 mA/24 mA (20 mA)
20 �A/-0.6 mA 20 �A/-0.6 mA
4-586
Functional Description
The 'F841 device consists of ten D-type latches with TRI-STATE outputs. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. This allows asynchronous operation, as the output transition follows the data in transition.
Inputs
OE
LE
x x
H
H
H
H
H
L
L
H
L
H
L
L
L
x
L
x
L
x
H
L
H
L
Function Table
Internal
Output
D
a
0
x
x
z
L
L
z
H
H
z
x
NC
z
L
L
L
H
H
H
x
NC
NC
x
H
H
x
L
L
x
H
H
x
L
z
x
H
z
On the LE HIGH-to-LOW transition, the data that meets the setup and hold time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH the bus output is in the high impedance state.
Function
HighZ HighZ HighZ Latched Transparent Transparent Latched Preset Clear Preset Latched Latched
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
Z = HIGH Impedance
NC = No Change
Logic Diagram
Dg
LE
OE Og
TL/F/9599-4 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-587
..... c""=o" Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to + 7.0V
Input Voltage (Note 2)
-0.5V to+ 7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
-0.5Vto Vee -0.5Vto +5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol V1H V1L Vco VoH
VoL l1H lsv1 leEx V10 loo l1L lozH lozL los lzz leez
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee 74F5% Vee 74F5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current
54F
Breakdown Test
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage 74F
Test
Output Leakage 74F
Circuit Current
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Bus Drainage Test
Power Supply Current
54F/74F Min Typ Max
2.0 0.8 -1.2
2.5 2.4 2.5 2.4 2.7 2.7
0.5 0.5
20.0 5.0
100 7.0
250 50
4.75
3.75
-0.6
50
-50
-60
-150
500
69
92
Units
v
v
v
v
v
�A
�A
�A
v
�A mA �A �A mA �A mA
Vee
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal Min l1N = -18 mA loH = -1 mA loH = -3 mA Min loH = -1 mA loH = -3 mA loH = -1 mA loH = -3 mA Min loL = 20 mA loL = 24mA Max V1N = 2.7V
Max V1N = 7.0V
Max Vour =Vee
0.0 110 = 1.9 �A All Other Pins Grounded
0.0 V100 = 150 mV All Other Pins Grounded
Max V1N = 0.5V Max Vour = 2.7V Max Vour = 0.5V
Max Vour = ov o.ov Vour = 5.25V
Max Vo= HIGHZ
4-588
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
tPLH tPHL
tPLH tPHL
tpzH tpzL
tpHz tpu
Propagation Delay Dn to On
Propagation Delay LE to On
Output Enable Time OE to On
Output Disable Time OE to On
74F
TA= +25�C Vee= +5.0V
CL= 50 pF
Min
Typ
Max
2.5
8.0
1.5
6.5
5.0
12.0
2.0
7.5
2.5
8.5
2.5
9.0
1.0
6.5
1.0
6.5
54F
TA, Vee= Mil CL= 50 pF
Min
Max
74F
TA, Vee= Com CL= 50 pF
Min
Max
2.0
9.0
1.5
7.0
4.5
13.5
2.0
8.0
2.0
9.5
2.0
10.0
1.0
7.5
1.0
7.5
AC Operating Requirements: See Section 2 for Waveforms
Symbol
Parameter
t5 (H) t5 (L)
th(H) th(L)
tw(H)
Setup Time, HIGH or LOW Dn to LE
Hold Time, HIGH or LOW Dn to LE
LE Pulse Width, HIGH
74F
TA= +25�C Vee= +5.0V
Min
Max
2.0 2.0
2.5 3.0
4.0
54F
TA, Vee= Mil
Min
Max
74F
TA, Vee= Com
Min
Max
2.5 2.5
3.0 3.5
4.0
Fig. Units
No. ns 2-3 ns 2-3 ns 2-5
Fig. Units
No.
ns
2-6
ns
2-4
4-589
~National
~Semiconductor
54F/74F843
9-Bit Transparent Latch
General Description
The 'F843 bus interface latch is designed to eliminate the extra packages required to buffer existing latches and provide extra data width for wider address/data paths or buses carrying parity.
The 'F843 is functionally and pin compatible with AMD's Am29843.
Features
� TRI-STATE� output � Direct replacement for AMD's Am29843
Ordering Code: see section 5 Logic Symbols
IEEE Symbol
TL/F/9453-6
Connection Diagram
Pin Assignment for DIP and SOIC
Of
Do D1 3 D2 D3 D4 6 D5 D5
0., 9
Ds 10 CLR 11 GND 12
24 Vee 23 Oo 22 01 21 02 20 03 19 04 18 05 17 05 16 07 15 Os 14 PRE
13 LE
TL/F/9453-2
OE Do D1 D2 D3 D4 D5 D5 D7 Ds eLR LE PRE Oo 01 02 03 04 05 05 07 Os
TL/F/9453-1
Unit Loading/Fan Out: See Section 2 for U.L. Definitions
Pin Names
De&cription
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loHlloL
Do-Da OE LE CLR PRE Oo-Oa
Data Inputs Output Enable Input Latch Enable Clear Preset TRI-STATE Data Outputs
1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 150/40 (33.3)
20 �A/-0.6 mA 20 �A/-0.6 mA 20 �Al - 0.6 mA 20 �Al -0.6 mA 20 �A/-0.6 mA -3 mA/24 mA (20 mA)
4-590
Functional Description
The 'F843 consists of nine D-type latches with TRI-STATE outputs. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. This allows asynchronous operation, as the output transition follows the data in transition. On the LE HIGH-to-LOW transition, the data that meets the setup times is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus
Function Table
Inputs
Internal Output Function
CLR PRE OE LE D Q
0
H H x xx x
H H H HL L
H H H HH H
x H H H L
NC
z
HighZ
z
HighZ
z
High Z
z
Latched
H H L HL L
L Transparent
H H L HH H
x H H L L
NC
H L L xx H
L H L xx L
L L L xx H
L H H Lx L
H L H Lx H
H Transparent
NC
Latched
H
Preset
L
Clear
H
Preset
z
Latched
z
Latched
Logic Diagram
output is in the high impedance state. In addition to the LE and OE pins, the 'F843 has a Clear (CLR) pin and a Preset (PRE). These pins are ideal for parity bus interfacing in high performance systems. When CLR is LOW, the outputs are LOW if OE is LOW. When CLR is HIGH, data can be entered into the latch. When PRE is LOW, the Outputs are HIGH if OE is LOW. Preset overrides CLR.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial Z = High Impedance NC = No Change
LE
Oa TL/F/9453-4 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-591
Absolute Maximum Ratings (Note 1>
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
-55�C to + 125�c
Junction Temperature under Bias
-55�Cto +175�C
Vee Pin Potential to Ground Pin
-0.5V to+ 7.0V
Input Voltage (Note 2)
-0.5Vto +7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with Vee = OV)
Standard Output TRI-STATE Output
-0.5VtoVcc -0.5Vto +5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�c o�cto +70�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
V1H V1L Vco VoH
Vol l1H lsv1 lcEx V10 loo l1L lozH lozL los lzz Ice
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee 74F 5% Vee 74F 5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage 74F
Test
Output Leakage 74F
Circuit Current
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Bus Drainage Test
Power Supply Current
54F/74F Min Typ Max
2.0 0.8 -1.2
2.5 2.4 2.5 2.4 2.7 2.7
0.5 0.5
20.0 5.0 100 7.0
250 50
4.75
3.75
-0.6
50
-50
-60
-150
500
65
90
Units v v v
v
v �A �A �A v �A mA �A �A mA �A mA
Vee
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal Min l1N = -18 mA loH = -1 mA loH = -3 mA Min loH = -1 mA loH = -3 mA loH = -1 mA loH = -3mA Min loL = 20 mA loL = 24 mA
Max V1N = 2.7V
Max V1N = 7.0V
Max VouT =Vee
0.0
0.0
Max Max Max Max o.ov Max
110 = 1.9 �A All other pins grounded V100 = 150 mV All other pins grounded V1N = 0.5V VouT = 2.7V VouT = 0.5V VouT = ov VouT = 5.25V
4-592
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
tPLH tPHL tPLH tpHL tPLH
tpHL
tpzH tpzL tpHz tpLz
Propagation Delay Dn to On
Propagation Delay LE to On
Propagation Delay PRE to On
Propagation Delay CLR to On
Output Enable Time OE to On
Output Disable Time OE to On
74F
TA= +25�c Vee= +5.0V
CL= 50 pF
Min
Typ
Max
2.5
5.4
8.0
1.5
4.2
6.5
5.0
8.5
12.0
2.0
4.7
7.5
3.0
7.3
10.0
3.0
6.9
10.0
2.5
5.0
8.5
2.5
6.1
9.0
1.0
3.6
6.5
1.0
3.4
6.5
54F
TA, Vee= Mii CL= 50 pF
Min
Max
74F
TA, Vee= Com CL= 50 pF
Min
Max
2.0
9.0
1.5
7.0
4.5
13.5
2.0
8.0
2.5
11.0
2.5
11.0
2.0
9.5
2.0
10.0
1.0
7.5
1.0
7.5
AC Operating Requirements: See section 2 for Waveforms
Symbol
Parameter
ts (H) ts (L) th (H) th (L) tw (H) tw(L) tw (L)
tree tree
Setup Time, HIGH or LOW Dn to LE Hold Time, HIGH or LOW Dn to LE LE Pulse Width, HIGH PRE Pulse Width, LOW CLR Pulse Width, LOW PRE Recovery Time CLR Recovery Time
74F
TA= +25�C Vee= +5.0V
Min
Max
2.0 2.0
2.5 3.0
4.0
5.0
5.0
10.0
12.0
54F
TA, Vee= Mii
Min
Max
74F
TA, Vee= Com
Min
Max
2.5 2.5
3.0 3.5
4.0
5.0
5.0
10.0
13.0
Fig. Units No.
ns
2-3
ns
2-3
ns
2-3
ns
2-3
ns
2-3
ns
2-5
Fig. Units
No.
ns
2-6
ns
2-4
ns
2-4
ns
2-4
ns
2-6
ns
2-6
4-593
~National
~Semiconductor
54F/74F845
8-Bit Transparent Latch
General Description
The 'F845 bus interface latch is designed to eliminate the extra packages required to buffer existing latches and provide extra data width for wider address/data paths or buses carrying parity.
The 'F845 is functionally- and pin-compatible with AMD's Am29845.
Features
� TRI-STATE� outputs
a Direct replacement for AMD's Am29845
Ordering Code: see section 5
Logic Symbols
Connection Diagrams
TL/F/9601-3
IEEE/I EC
DE1 CiE2 DE3
m
CLii
LE
Pin Assignment for DIP, SOIC and Flatpak
OE1 1 6[2 �2
Do 3 D1 4 D2 5 D3 6 D4 7
Ds
D5 D1 10
ru 11
GND 12
24 Vee
23 OE3 22 Oo 21 01 20 02 19 03 18 04 17 05 16 05 15 07
14 PRE
13 LE
TL/F /9601-1
Pin Assignment for LCC
D6 D5 D4 NC D3 D2 D1 [j][Q]IIJ[�]IIJ[�JIIJ
D1 li11
ru !ill
GND IB]
NC~ LE~
PRE IIZl
07 II�]
[II Do
[I] 0E2
rn 6E1
Q] NC
~Vee
llll oc3
@] Oo
@l~ll:il~~~~ 05 05 04 NC 03 02 01
TL/F/9601-2
Do
Do
D1
01
D2
02
03
03
04
04
05
05
05
05
~
o,
TL/F/9601-5
Unit Loading/Fan Out: See Section 2 for U.L. Definitions
Pin Names
Do-D7 Oo-07 OE1-0E3 LE CLR PRE
Description
Data Inputs Data Outputs Output Enables Latch Enable Clear Preset
U.L. HIGH/LOW
1.0/1.0 150/40 (33.3) 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0
54F/74F
Input l1Hll1L Output loH/loL
20 �A/-0.6 mA -3.0 �A/24 mA (20 mA) 20 �A/-0.6 mA 20 �A/ -0.6 mA 20 �A/-0.6 mA 20 �A/-0.6 mA
4-594
Functional Description
The 'FB45 consists of eight D-type latches with TRI-STATE outputs. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. This allows asynchronous operation as the output transition follows the data in transition.
Logic Diagram
On the LE HIGH-to-LOW transition, the data that meets the setup times is latched. Data appears on the bus when the output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedance state.
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
TL/F/9601-4
Function Table
Inputs
Internal Output Function
CLR PRE OE LE D Q
0
H H H xx x
H H H HL L
H H H HH H
x H H H L
NC
z HighZ z HighZ z HighZ z Latched
H H L HL L
L Transparent
H H L HH H
x H H L L
NC
H L L xx H
L H L xx L
L L L xx H
L H H Lx L
H L H Lx H
H Transparent NC Latched H Preset L Clear
H Preset
z Latched z Latched
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance NC = No Change
4-595
U") ~
co Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5Vto +7.0V
Input Voltage (Note 2)
-0.5Vto +7.0V
Input Current (Note 2)
-30 mA to + 5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
-0.5VtoVee - 0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�cto +70�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Vco VoH
VoL
lsv1 leEX
loo
lozH lozL los lzz lecz
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee 74F 5% Vee 74F 5% Vee
Output LOW Voltage
54F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage 74F
Test
Output Leakage 74F
Circuit Current
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Bus Drainage Test
Power Supply Current
54F/74F Min Typ Max
2.0
0.8 -1.2
2.5 2.4 2.5 2.4 2.7 2.7
0.5 0.5 20.0 5.0
100 7.0
250 50
4.75
3.75
-0.6
50
-50
-60
-150
500
63
85
Units
v
v
v
v
v
�A �A �A
v
�A
mA
�A �A
mA
�A
mA
Vee
Min
Min
Min Max Max Max 0.0 0.0 Max Max Max Max
o.ov
Max
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal l1N = -18 mA loH = -1 mA loH = -3mA loH = -1 mA loH = -3mA loH = -1 mA loH = -3mA loL = 20 mA loL = 24 mA V1N = 2.7V
V1N = 7.0V
VouT =Vee
110 = 1.9 �A
All Other Pins Grounded V100 = 150 mV All Other Pins Grounded V1N = 0.5V VouT = 2.7V VouT = 0.5V
VouT = ov
VouT = 5.25V Vo = HIGH Z
4-596
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
74F
54F
74F
Symbol
Parameter
tPLH tPHL tpLH tPHL tPLH
tpHL
tpzH tpzL tpHz tpLz
Propagation Delay Dn to On
Propagation Delay LE to On
Propagation Delay PRE to On
Propagation Delay CLR to On
Output Enable Time OE to On
Output Disable Time OE to On
TA= +25�C Vee= +5.0V
CL= 50 pF
Min
Typ
Max
2.5
4.8
8.0
1.5
3.6
6.5
5.0
8.1
12.0
2.0
4.4
7.5
3.0
5.9
10.0
3.0
6.5
10.0
2.5
5.8
9.5
2.5
7.6
12.0
1.0
3.1
7.5
1.0
2.8
6.5
TA, Vee= Mil CL= 50 pF
Min
Max
TA, Vee= Com CL= 50 pF
Min
Max
2.0
9.0
1.5
7.0
4.5
13.5
2.0
8.0
2.5
11.0
2.5
11.0
2.0
10.5
2.0
13.0
1.0
8.5
1.0
7.5
Fig. Units No.
ns
2-3
ns
2-3
ns
2-3
ns
2-3
ns
2-5
ns
2-5
4-597
AC Operating Requirements: See Section 2 for Waveforms
Symbol
Parameter
t5 (H) t5 (L) th(H) th(L) tw(H) tw(L) tw(L)
tree tree
Setup Time, HIGH or LOW Dn to LE Hold Time, HIGH or LOW Dn to LE LE Pulse Width, HIGH PRE Pulse Width, LOW CLR Pulse Width, LOW PRE Recovery Time CLR Recovery Time
74F
TA= +25�C Vee= +s.ov
Min
Max
2.0 2.0
2.5 3.0
4.0
5.0
5.0
10.0
12.0
54F
TA, Vee= Mil
Min
Max
74F
TA, Vee= Com
Min
Max
2.5 2.5
3.0 3.5
4.0
5.0
5.0
10.0
13.0
Units
Fig. No.
ns
2-6
ns
2-6
ns
2-4
ns
2-4
ns
2-4
ns
2-6
ns
2-6
4-598
CX>
<O
a~National Semiconductor
<O
54F/74F899 9-Bit Latchable Transceiver with Parity Generator/Checker
General Description
The 'F899 is a 9-bit to 9-bit parity transceiver with transparent latches. The device can operate as a feed-through transceiver or it can generate/check parity from the 8-bit data busses in either direction. It has a guaranteed current sinking capability of 24 mA at the A-bus and 64 mA at the B-bus.
The 'F899 features independent latch enables for the A-to-B direction and the B-to-A direction, a select pin for ODD/EVEN parity, and separate error signal output pins for checking parity.
Features
� Latchable transceiver with output sink of 24 mA at the A-bus and 64 mA at the B-bus
� Option to select generate parity and check or "feedthrough" data/parity in directions A-to-B or B-to-A
� Independent latch enables for A-to-B and B-to-A directions
� Select pin for ODD/EVEN parity � ERRA and ERRB output pins for parity checking
� Ability to simultaneously generate and check parity � May be used in systems applications in place of the
'F543 and 'F280
� May be used in system applications in place of the
'F657 and 'F373 (no need to change T/R to check par-
ity)
� Guaranteed 4000V min ESD protection
Ordering Code: see section 5
Logic Symbol
Bo B1 B2 B3 B" B5 Bs B7 BPAR ODD/EVEN
LEB
Connection Diagram
Pin Assignment for PCC
A7 As A5 A-4 A3 A2 A1 [j][QJ []][[]CZ] [[I[[)
APAR IJ] GBA [j] GND~
ERRB Ml SIT !ill LEB Ii]
BPAR [fil
[II Ao [l] LEA [l] ERRA [JJ ODD/EVEN
@l Vee Ill] GAB
~Bo
TL/F/10195-16
Input Loading/Fan-Out: see section 2
l!:2ltm~llll~~� B7 B6 B5 B4 B3 B2 B1
Pin Names
Ao-A7
Bo-B7
APAR
BPAR
ODD/EVEN GBA,GAB SEL LEA, LEB ERRA, ERRB
Description
Data Inputs/ Data Outputs Data Inputs/ Data Outputs A Bus Parity Input/Output B Bus Parity Input/Output Parity Select Input Output Enable Inputs Mode Select Input Latch Enable Inputs Error Signal Outputs
54F/74F HIGH/LOW
U.L. HIGH/LOW
Input l1Hll1L Output loH/loL
1.0/1.0 150/40 1.011.0 600/106.6 1.0/1.0 150/40 1.0/1.0 600/106.6 1.011.0 1.0/1.0 1.0/1.0 1.0/1.0 50/33.3
20 �Al-'- 0.6 mA -3 mA/24 mA 20 �A/ - 0.6 mA -12 mA/64 mA 20 �A/ - 0.6 mA -3 mA/24 mA 20 �A/-0.6 mA -12 mA/64 mA 20 �A/-0.6 mA 20 �Al - 0.6 mA 20 �Al -0.6 mA 20 �A/-0.6 mA -1 mA/20 mA
TL/F/10195-1
4-599
O>
cOo>
Pin Names
Description
Ao-A7 Bo-87 APAR, BPAR ODD/EVEN
GBA, GAB
SEL
LEA, LEB
ERRA, ERRB
A Bus Data Inputs/Data Outputs B Bus Data Inputs/Data Outputs A and B Bus Parity Inputs ODD/EVEN Parity Select, Active LOW for EVEN Parity Output Enables for A or B Bus, Active LOW Select Pin for Feed-Through or Generate Mode, LOW for Generate Mode Latch Enables for A and B Latches, HIGH for Transparent Mode Error Signals for Checking Generated Parity with Parity In, LOW if Error Occurs
Functional Description
The 'F899 has three principal modes of operation which are outlined below. These modes apply to both the A-to-8 and 8-to-A directions.
- Bus A (8) communicates to Bus B (A), parity is generated and passed on to the B (A).Bus as BPAR (APAR). If LEB (LEA) is HIGH and the Mode Select (SEL) is LOW, the parity generated from 8[0:7) (A[O:?]) can be checked and monitored by ERRB (ERRA).
- Bus A (8) communicates to Bus B (A) in a feed-through mode if SEL is HIGH. Parity is still generated and checked as ERRA and ERRB in the feed-through mode (can be used as an interrupt to signal a data/parity bit error to the CPU).
...,..... Independent Latch Enables (LEA and LEB) allow other permutations of generating/checking (see Function Table below).
Function Table
Inputs
GAB GBA SEL LEA LEB
Operation
H
H
x x x Susses A and Bare TRI-STATE�.
H L L L H Generates parity from B[0:7) based on O/E (Note 1). Generated parity --+ APAR. Generated parity checked against BPAR and output as ERRB.
H
L
L H H Generates parity from 8[0:7) based on 0/E. Generated parity --+
APAR. Generated parity checked against SPAR and output as ERRB.
Generated parity also fed back through the A latch for generate/check
as ERRA.
H
L
L
x
L Generates parity from B latch data based on O/E. Generated parity
--+ APAR. Generated parity checked against latched BPAR and
output as ERRB.
H
L
x H
H BPAR/8[0:7) --+ APAR/ AO:?] Feed-through mode. Generated parity
checked against BPAR and output as ERRB.
H
L
H H H BPAR/8[0:7) --+ APAR/A[O:?]
Feed-through mode. Generated parity checked against BPAR and
output as ERRB. Generated parity also fed back through the A latch for
generate/check as ERRA.
L
H
L H
L Generates parity for A[O:?] based on 0/E. Generated parity --+
SPAR. Generated parity checked against APAR and output as ERRA.
L
H
L H H Generates parity from A[O:?] based on O/E. Generated parity --+
BPAR. Generated parity checked against APAR and output as ERRA.
Generated parity also fed back through the B latch for generate/check
as ERRB.
L
H
L
L
x Generates parity from A latch data based on 0/E. Generated parity
--+ SPAR. Generated parity checked against latched APAR and
output as ERRA.
L
H HH
L APAR/A[O:?] --+ BPAR/8[0:7)
Feed-through mode. Generated parity checked against APAR and
output as ERRA.
L
H
H H H APAR/A[O:?] --+ BPAR/8[0:7)
Feed-through mode. Generated parity checked against APAR and
output as ERRA. Generated parity also fed back through the B latch for
generate/check as ERRB.
H = HIGH Voltage Level L = LOW Voltage Level
X = Immaterial
Note 1: O/E = ODD/EVEN
4-600
Functional Block Diagram
.....-------
9-bll TRANSPARENT
....--- LATCH
r,-....
-LEA _..,.
LE
- t-f-< - t-+-+-<
I
.rT:r1I
]]l
PARITY GENERATOR
1Ji!?
I
]
~
9-blt Output Buffer
1-t--+-
1--+-+-
t -t-t-t-
-
t-
H-
H -+ -
t-t-H -
ODD/EVEN LEB
,---
i...+-I - - -
' -.+_-
9-blt Output Buffer
...�1....__
I
"'T"T
Y-Tl
lSJrTI; IJ]
PARITY
l
GENERATOR
,.-,
t1---
t---
9-bit I----TRANSPARENT
LATCH
.- LE
TL/F/10195-2
AC Path
An, APAR (Bn, BPAR)
Bn, BPAR (An, APAR)
An, APAR -+ Bn. BPAR (Bn, BPAR -+ An. APAR)
/
FIGURE 1
"'---- INPUT
OUTPUT
TL/F/10195-3
4-601
eenn
a:> AC Path (Continued)
SEL
0 O/E
LEA (LEB)
A[0:71 (8[0:71)
ODD PARITY
BPAR (APAR)
An - SPAR (Sn - APAR)
O/E
APAR 0 (BPAR)
LEA (LEB)
AC0:7J (BC0:71)
ODD PARITY
ERRA (ERRB)
An - ERRA (Bn - ERRS)
APAR (BPAR)
=>< A[Q:7J
(8[0:71)
O/E
ERRA (ERRB)
O/E - ERRA O/E - ERRS
TPLH
EVEN PARITY TPHL
FIGURE 2
EVEN PARITY TPLH
FIGURE3 EVEN PARITY
TPHL FIGURE4
ODD PARITY
INPUT
TPLH
OUTPUT TL/F/10195-4
ODD PARITY TPHL
INPUT OUTPUT
TL/F/10195-5
INPUT INPUT OUTPUT
TL/F/10195-6
4-602
AC Path (Continued)
0 SEL APAR 0 (8PAR)
=>< AC0:7J
(8[0:71)
O/E
EVEN PARITY
cCXo> co
INPUT INPUT
8PAR (APAR)
O/E - SPAR (0/E - APAR)
TPLH
TPHL
FIGURE 5
0
O/E - - - - - - - - - - - - - - - - - - - - - - - - -
A!0:7J~
(8C0:71) ____/"-_ _ _ _ _ _ _ _ _EV_E_N_P_AR-ITY-----------
OUTPUT TL/F/10195-7
INPUT
APAR (8PAR)
INPUT
OUTPUT
APAR - ERRA (SPAR - ERRS)
TPLH
TPHL FIGURES
TL/F/10195-8
0/E-1----------------------------------
APAR
(8PAR)o------------------------------
A[0:7] (8[0:7])
EVEN
x
ODD
x
EVEN
LEA (LEB)
\
ERR8 (ERRA)
L3 \
LJ
INPUT OUTPUT
FIGURE7
TL/F/10195-18
SEL 1
INPUT
ZH,HZ
8PAR, 8[0:71 (APAR, AC0:71)
TPHZ
0.3V
FIGURES 4-603
TPZH
OUTPUT TL/F/10195-9
O>
cOo>
AC Path (Continued)
SEL 1
GAB {GBA)
ZL, lZ
BPAR, BC0:7J {APAR, AC0:7J)
TPLZ
O/E
APAR (BPAR)
AC0:7J (BC0:7J)
1 0
=><
SEL
BPAR (APAR)
TPLH
SEE - BPAR (S�IT - APAR)
SEL
O/E
AC0:71, APAR (BC0:7J, BPAR)
LEA {LEB)
BC0:7J, BPAR {AC0:7J, APAR)
LEA - BPAR, 8[0:7] (LEB - APAR, A[0:7])
/
TPLH
0.3V FIGURE9 EVEN PARITY
TPHL FIGURE 10
'
FIGURE 11
INPUT
OUTPUT
TPZL
TL/F/10195-10
INPUT INPUT OUTPUT
TL/F/10195-11
/
TPHL
INPUT INPUT OUTPUT
TL/F/10195-12
4-604
AC Path (Continued)
LEA {LEB)
APAR, Al0:71 {8PAR, 8(0:71)
TS(H), TH(H) LEA --. APAR, A[0:7] (LE8 __. 8PAR, 8(0:7])
LEA {LEB)
APAR, Al0:71 {8PAR, 810:71)
TS(L), TH(L) LEA --. APAR, A[0:7] (LE8 __. 8PAR, 8(0:7])
LEA (LEB)
APAR, AW:71 (8PAR, 8(0:71)
8PAR, A[Q:71 (APAR, 810:71)
TW
TS{H) FIGURE 12
TS{L) FIGURE 13
FIGURE 14
C)
<O <O
INPUT
TH{H)
INPUT TL/F/10195-13
TH{L)
INPUT INPUT
TL/F/10195-14
INPUT INPUT OUTPUT
TL/F/10195-17
4-605
O>
cOo> Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
-55�C to+ 175�C
Vee Pin Potential to Ground Pin
-0.5Vto +7.0V
Input Voltage (Note 2)
-0.5V to+ 7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Voltage Applied to Output in HIGH State (with Vee= OV) Standard Output TRI-STATE Output
-0.5VtoVee -0.5Vto +5.5V
Current Applied to Output
in LOW State (Max)
Twice the Rated loL (mA)
ESD Last Passing Voltage (Min)
4000V
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
Vee f--54-F/- 74- F -~ Units Min Typ Max
Conditions
Input HIGH Voltage
2.0
v Recognized as a
HIGH Signal
Input LOW Voltage
Veo
Input Clamp Diode Voltage
Min
0.8
v Recognized as a
LOW Signal
-1.2 v l1N = -18 mA
VoH
Output HIGH
Voltage
54F 10% Vee Min 2.5
54F 10% Vee Min 2.4
54F 10% Vee Min 2.0
74F 10% Vee
2.5
74F 10% Vee
2.4
74F 10% Vee
2.0
74F 5% Vee
2.7
74F 5% Vee
2.7
loH = -1 mA loH = -3 mA loH = -12 mA (Bn, SPAR) loH = -1 mA
v loH = -3 mA
loH = -15 mA (Bn, SPAR) loH = -1 mA loH = -3 mA
Output LOW Voltage
54F 10% Vee Min
54F 10% Vee Min 74F 10% Vee
74F5% Vee
74F 10% Vee Input Threshold Voltage
0.5
0.55 0.5
0.5
0.55 1.45
loL = 20 mA (An, APAR, ERRA, ERRS) loL = 48 mA (Bn, SPAR)
v loL = 20 mA
(An. APAR, ERRA, ERRS) loL = 24 mA (An, APAR, ERRA, ERRS) loL = 64 mA (Bn, SPAR)
v �0.1V, Sweep Edge Rate must be> 1V/50 ns
Vmv
Negative Ground Bounce Voltage
1.0
v Observed on "quiet" output during
simultaneous switching of remaining outputs
VoLP
Positive Ground Bounce Voltage
1.0
v Observed on "quiet" output during
simultaneous switching of remaining outputs
Input Low Current
Max
- 0.6 mA V1N = 0.5V
Input HIGH
54F
Current
74F
20.0 �A
5.0
Max V1N = 2.7V
lsv1
Input HIGH Current 54F
Breakdown Test 74F
100 �A
7.0
Max V1N = 7.0V (ODD/EVEN, GBA, GAB, SEL, LEA, LEB)
lsv1r
Input HIGH Current 54F Breakdown (110) 74F
1.0
V1N = 5.5V
mA Max
0.5
(An, Bn. ApAR� SPAR)
4-606
DC Electrical Characteristics (Continued)
Symbol
Parameter
leEX
V10
loo
l1L
l1H +
lozH
l1L +
lozL los
Output HIGH
54F
Leakage Current 74F
Input Leakage 74F
Test
Output Leakage 74F
Circuit Current
Input Low Current
Output Leakage Current Current
Output Leakage Current
Output Short-Circuit Current
54F/74F Vee
Min
Typ
Max
250 �A
50
4.75
v
3.75
�A
Max
-0.6
Max
70
Max
Max
-60
-650 -150
lzz leeH leeL
Bus Drainage Test Power Supply Current Power Supply Current
Max -100
o.ov
-225 500
Max
132
155
Max
178
210
leez
Power Supply Current
Max
160
190
Units
Max 0.0 0.0 mA �A �A
mA �A mA mA mA
Conditions
Vour =Vee
110 = 1.9 �A All Other Pins Grounded V100 = 150 mV All Other Pins Grounded V1N = 0.5V V110 = 2.7V (An. Bn. APAR, BPAR) V110 = 0.5V (An, Bn, APAR, BPAR)
Vour = ov
(An, APAR, ERRA, ERRB)
ov Vour = (Bn. BPAR)
Vour = 5.25V Vo= HIGH Vo = LOW, GAB = LOW, GBA = HIGH, V1L = LOW Vo= HIGHZ
AC Electrical Characteristics
Symbol
tPLH tPHL tpLH tPHL tPLH tPHL tpLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL
Parameter
Propagation Delay An, APAR to Bn. BPAR Propagation Delay An, Bn to BPAR, APAR Propagation Delay An, Bn to ERRA, ERRB Propagation Delay ODD/EVEN to ERRA, ERRB Propagation Delay ODD/EVEN to APAR, BPAR Propagation Delay APAR, BPAR to ERRA, ERRB LEA/LEB to ERRA/ERRB
54F/74F
TA= +25�C Vee= +5.0V
CL= 50 pF
Min Typ Max
4.0
7.5
13.0
4.0
8.5
13.0
7.5
12.0 17.0
7.5
12.5 17.0
7.5
12.0 17.0
7.5
12.5 17.0
4.5
7.5
11.0
4.5
8.0
11.0
4.5
7.5
11.5
4.5
8.5
11.5
5.5
9.0
13.0
5.5
9.5
13.0
9.5
13.0 17.5
9.7
17.5
54F
TA, Vee= Mil
CL= 50 pF
Min Max
74F
TA, Vee= Com
CL= 50 pF
Min Max
4.0 14.0 4.0 14.0
7.5
18.0
7.5
18.0
7.5 18.0 7.5 18.0
4.5
12.0
4.5 12.0
4.5 12.5
4.5
12.5
5.5
14.0
5.5
14.0
7.5
18.0
7.5
18.0
Units
ns ns ns ns ns ns ns
Fig. No.
899-1 899-2 899-3 899-4 899-5 899-6 899-7
4-607
O> O>
co AC Electrical Characteristics (Continued)
Symbol
tPLH tPHL tPLH tPHL tPLH tPHL tpzH tpzL
tpHz tpLz
t5(H) t5(L) th(H) th(L) tw
Parameter
Propagation Delay SEL to APAR, SPAR Propagation Delay LEB to An, APAR Propagation Delay LEA to Bn, SPAR Output Enable Time GBA or GAB to An, APAR or Bn, SPAR Output Disable Time GBA or GAB to An. APAR or Bn, SPAR Setup Time, HIGH or LOW An, Bn to LEA, LEB Hold Time, HIGH or LOW An, Bn to LEA, LEB Pulse Width for LEA, LEB
54F/74F
TA= +25�C Vee= +5.0V
CL= 50 pf
Min Typ Max
3.0
6.0
10.0
3.0
7.0
10.0
3.5
7.0
10.0
3.5
8.0
10.0
3.5
6.5
10.0
3.5
7.5
10.0
1.0
4.5
10.0
1.0
6.5
10.0
1.0
4.0
7.0
1.0
4.0
7.0
5.0
1.6
5.0
1.8
0
-1.7
0
-1.5
6.0
2.0
54F
TA, Vee= Mil
CL =50 pf
Min Max
74F
TA, Vee= Com
CL= 50 pf
Min Max
3.0 11.0 3.0 11.0
3.5 11.0 3.5 11.0
3.5 11.0 3.5 11.0
1.0 11.0 1.0 11.0
1.0
8.0
1.0
8.0
5.0 5.0
0 0
6.0
Units
ns ns ns ns
ns ns ns ns
Fig. No.
899-10 899-11 899-11 899-8, 9
899-8, 9 899-12, 13 899-12, 13
899-14
4-608
co
a>
~National
CC)
~Semiconductor
54F/74F968
1 Mbit Dynamic RAM Controller
General Description
The 'F968 is a high performance memory controller, replacing many SSI and MSI devices by grouping several unique functions. It provides two 10-bit address latches and two 1Obit counters for row and column address generation during refresh. A 2-bit bank select latch for row and column address generation during refresh and a 2-bit bank select latch for the two high order address bits are provided to select one of the four RAS and CAS outputs.
Features
� Provides control for 16k, 64k, 256k or 1 Mbit DRAM systems
� Outputs directly drive up to 88 DRAMs � Chip select for easy expansion � Provides memory refresh with error correction mode � 52-pin plastic leaded chip carrier
Ordering Code: see section 5 Logic Symbol
cs
MSEL
LE
SELo SEL1 MC0 MC1 RASI CASI OE
"'lN-O"'lN-O
V(-.<)I Vu<I Vu<I Vu<I Va<:I: Va<:I: aV<:I: Va<:I:
TL/F/9604-1
4-609
CIC)
CD
O> Connection Diagram
Pin Assignment for PCC
cs ACz ARz AC1 AR1 ACo ARoMSEl. CASI RASoCASoW1CAS1
~ [j] [j]J [!] [ID ~ (j] [j] [fil [jJ [j]] II.I (fil
AR3 ~ AC3 ~ AR4 ~ AC4 ~
GND(ECL)~
LE~
AR5[ll)
AC5 ~ AR6 ~
AC5~
AR7 ill] AC7 ~ AR8 [TI]
moo
1Ila1
@]Oz
[I]03
m a. . .
[IJ GND (TTL)
OJ6E
igj Vcc (TTL) . [fill Vcc(ECL) ~05
~06 ~07
!�Joa
~~~rm~~~@l~~~~~ ACa ARg AC9SELoSEL1 MC1 MCo RASI CAS3RAS3CASzRASz09
TL/F/9604-3
4-610
<enD
Unit Loading/Fan Out: See section 2 for u.L. definitions
Q)
Pin Names
ACo-ACg ARo-ARg MCo, MC1
cs
MSEL LE SELo, SEL1 RASI CASI OE RAS0-RAS3 CAS0-CAS3 Oo-Og
Description
Column Address Inputs Row Address Inputs Mode Control Inputs Chip Select Input Multiplexer Select Input Latch Enable Input Bank Select Inputs Row Address Strobe In Column Address Strobe In Output Enable Row Address Strobe Outputs Column Address Strobe Outputs Address Outputs
54F/74F
U.L.
Input l1Hll1L
HIGH/LOW Output loHllOL
1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 150/1.667 150/1.667 150/1.667
20 �A/ - 0.6 mA 20 �A/-0.6 mA 20 �A/-0.6 mA 20 �A/-0.6 mA 20 �A/ - 0.6 mA 20 �A/ - 0.6 mA 20 �A/-0.6 mA 20 �A/ - 0.6 mA 20 �A/ - 0.6 mA 20 �A/ -0.6 mA -3mA/1.0mA -3 mA/1.0 mA -3mA/1.0mA
Pin Descr~tion
Name
1/0
Description
ARo-ARg ACo-ACg
I Address Inputs. AR0-ARg are latched in as the 10-bit Row Address for the RAM. These inputs drive Oo-Og when the 'F968 is in the Read/Write mode and MSEL is LOW. AC0-AC9 are latched in as the Column Address, and will drive Oo-09 when MSEL is HIGH and the 'F968 is in the Read/Write mode. The addresses are latched with the Latch Enable (LE) signal.
SELo-SEL1
I Bank Select. These two inputs are normally the two higher order address bits, and are used in the Read/Write mode to select which bank of memory will be receiving the RASn and CASn signals after RASI and CASI go HIGH.
LE
I Latch Enable. This active-HIGH input causes the Row, Column and Bank Select latches to become
transparent, allowing the latches to accept new input data. A LOW input on LE latches the input data,
assuming it meets the setup and hold time requirements.
MSEL
cs
I Multiplexer Select. This input determines whether the Row or Column Address will be sent to the memory address inputs. When MSEL is HIGH the Column Address is selected, while the Row Address is selected when MSEL is LOW. The address may come from either the address latch or refresh address counter depending on MCo, MC1.
I Chip Select. This active-LOW input is used to enable the 'F968. When CS is active, the 'F968 operates normally in all four modes. When CS goes HIGH, the device will not enter the Read/Write mode. This allows other devices to access the same memory that the 'F968 is controlling (e.g., OMA controller).
OE
I Output Enable. This active-LOW input enables/disables the output signals. When OE is HIGH, the outputs
of the 'F968 enter the high impedance state. The OE signal allows more than one 'F968 to control the
same memory, thus providing an easy method to expand the memory size.
MCo, MC1
I Mode Control. These inputs are used to specify which of the four operating modes the 'F968 should be using. The description of the four operating modes is given in the Mode Control Function Table.
Oo-Og
0 Address Outputs. These address outputs will feed the DRAM address inputs and provide drive for
memory systems up to 500 pF in capacitance.
RASI
I Row Address Strobe Input. During normal memory cycles, the decoded RASn output (RASo, RAS1, RAS2 or RAS3) is forced LOW after receipt of RASI. In either refresh mode, all four RASn outputs will go LOW following RASI going HIGH.
RAS0-RAS3 0 Row Address Strobe. Each one of the Row Address Strobe outputs provides a RASn signal to one of the
four banks of dynamic memory. Each will go LOW only when selected by SELo and SEL1 and only after RASI goes HIGH. All four go LOW in response to RASI in either of the Refresh modes.
CASI
I Column Address Strobe Input. This input going active will cause the selected CASn output to be forced LOW.
CAS0-CAS3 0 Column Address Strobe. During normal Read/Write cycles the two select bits (SEL.o, SEL1) determine
which CASn output will go active following CASI going HIGH. When memory error correction is performed,
only the CASn signal selected by CNTRo and CNTR1 will be active. For non-error correction cycles, all four CASn outputs remain HIGH.
4-611
co
CD
O> Functional Description
The 74F968 is a 1 Mbit DRAM controller which is functionally equivalent to AMD's Am29368. The 74F968 provides row/column address multiplexing, refresh address generation and bank selection for up to four banks of RAMs.
Twenty-two (22) address bits (AR0-AR9 , ACo-ACg and bank select addresses SELo and SEL1) are presented to the controller. These addresses are latched by a 22-bit latch. A 22-bit counter generates the refresh address.
A 10-bit multiplexer selects the output address between the input row address, column address, refresh counter row address, column address, or zero (clear). Four RAS and four CAS outputs select the appropriate bank of RAMs and strobe in the row and column addresses.
It should be noted that the counters are cleared (MC0, MC1 = 1, 1) on the next RASI transition, but the Q outputs are asynchronously cleared through the multiplexer.
Mode Control Function Table
MC1
MCo
L
L
L
H
H
L
H
H
H = HIGH Voltage Level L = LOW Voltage Level
Operating Mode
Refresh without Error Correction- Refresh cycles are performed with only the Row Counter being used to generate addresses. In this mode, all four RASn outputs are active while the four CASn signals are kept HIGH.
Refresh with Error Correction/Initialize- During this mode, refresh cycles are done with both the Row and Column counters generating the addresses. MSEL is used to select between the Row and Column counter. All four RASn outputs go active in response to RASI, while only one CASn output goes LOW in response to CASI. The Bank Counter keeps track of which CASn output will go active. This mode of operation is possible when supported by an error detection/correction circuit such as the 'F632.
Read/Write- This mode is used to perform Read/Write cycles. Both the Row and Column addresses are latched and multiplexed to the address output lines using MSEL; SELo and SEL1 are decoded to determine which RASn and CASn will be active.
Clear Refresh Counter-This mode will clear.the three refresh counters (Row, Column and Bank) on the HIGH-to-LOW transition of RASI, putting them at the start of the refresh sequence. In this mode, all four RASn outputs are driven LOW upon receipt of RASI so that DRAM wake-up cycles are performed. This mode also asynchronously clears the On outputs.
cs
MC1
L
L L
H
H
L
L H
H
H H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
MCo L H
L
H L H
L H
Address Output Function Table
MSEL
x
Mode Refresh without Error Correction
H
Refresh with Error Correction
L
H
Read/Write
L
x
Clear Refresh Counter
x
Refresh without Error Correction
H
Refresh with Error Correction
L
x
Read/Write
x
Clear Refresh Counter
MUX Output Row Counter Address Column Counter Address Row Counter Address Column Address Latch Row Address Latch Zero Row Counter Address Column Counter Address Row Counter Address Zero Zero
4-612
<D
O')
RAS Output Function Table
Q)
RASI cs MC1 MCo SEL1 SELo
Mode
RASo RAS1 RAS2 RAS3
L xx x
x
x
Non-Refresh
H
H
H
H
L
L
x
x
Refresh without Error Correction
L
L
L
L
L
H
x
x
Refresh with Error Correction
L
L
L
L
L
L
Read/Write
L
H
H
H
L
H
L
L
H
H
H
L
H
L
H
H
H
H
L
H
H
H
H
H
H
L
H
H
x
x
Clear Refresh Counter
L
L
L
L
L
L
x
x
Refresh without Error Correction
L
L
L
L
H
L
H
H
L
Refresh with Error Correction Read/Write
L
L
L
L
H
H
H
H
H
H
Clear Refresh Counter
L
L
L
L
Inputs
CASI
cs
MC1
MCo
L
L
L
H
L
H
L
H
H
H
L
L
L
H
H
H
L
H
H
L xx x
CAS Output Function Table
Internal Counter
Inputs
CNTR1
x
L L H H
x
x x
L L H H
CNTRo
x
L H L H
x
x x
L H L H
SEL1
x
SELo
x
x x
L
L
L
H
H
L
H
H
x x
x x
x x
x
x
x x
x
x
x x
CASo
H L H H H L H H H H H L H H H
H
H
Outputs
CAS1
H
CAS2
H
H
H
L
H
H
L
H
H
H
H
L
H
H
L
H
H
H
H
H
H
H
H
L
H
H
L
H
H
H
H
H
H
CAS3
H H H H L H H H L H H H H H L
H
H
4-613
co
CD
O> Block Diagram
RASI
CASI
cs
MC 1 MC0 MSEL
LE
6E
CLR CONTROL
LOGIC
SELo SEL1
BANK LATCH
CLR
BANK COUNTER
CNTR0 CNTR 1 2
RAS
RAS0-RAS3
4
CAS
CAS0-CAS3
4
ARo-ARg
ROW LATCH
CLR
AC0 -ACg
COLUMN LATCH
CLR
Memory Cycle Timing
The relationship between the 'F968 specifications and system timing requirements is shown in Figures 1-6. T1, T2 and T3 represent the minimum timing requirements at the 'F968 inputs to guarantee that the RAM timing requirements are met and that maximum system performance is achieved.
COLUMN COUNTER
ROW COUNTER
10 10 10 10
CLR
00 -0g
TL/F/9604-4
The minimum requirement for T1, T2 and T3 are as follows:
T1 Min = tASR + tskew T2 Min = tRAH + tskew T3 Min = T2 + tskew + tASC�
See RAM data sheet for applicable values for tRAH� tAsC and tASR�
4-614
<O
Memory Cycle Timing (Continued)
a>
CX>
xxxxxxxxx:x x:=:: Qn ------------"'XXXX*.._..,,.,., ROW ADDRESS VALID
COLUMN AOORESS VALD
- - - - RASI
\\\\\
I
LE
MSEL
CASI
CASn
\\
SELn
----------------------RAM-SElM/-COAR-SYI-CPYU-CLLS-EET-WIMIDI-NTGH-S ---------------------
RASl/CASI
FIGURE 1. Dynamic Memory Controller Timing
TL/F/9604-5
MSEL
CASI
CASn
Note A: Guaranteed maximum difference between fastest RASI to RASn delay and the slowest An to On delay on any single device. Note B: Guaranteed maximum difference between fastest MSEL to On delay and the slowest RASI to RASn delay on any single device. Note C: Guaranteed maximum difference between fastest CASI to CASn delay and the slowest MSEL to On delay on any single device.
FIGURE 2. Specifications Applicable to Memory Cycle Timing (MCn = 1,0)
4-615
TL/F/9604-6
Memory Cycle Timing (Continued)
RASn MSEL CASI CASn
Refresh Cycle Timing
FIGURE 3. Desired System Timing
TL/F /9604-7
MSEL
CASI
CASn
Note B: Guaranteed maximum difference between fastest MSEL to On delay and the slowest RASI to RASn delay on any single device. Note C: Guaranteed maximum difference between fastest CASI to CASn delay and the slowest MSEL to On delay on any single device. Note D: Guaranteed maximum difference between fastest RASI to RASn delay and the slowest MCn to On delay on any single device.
FIGURE 4. Specifications Applicable to Refresh Cycle Timing (MCn = 00,01)
TL/F/9604-B
4-616
<O
Refresh Cycle Timing (Continued)
cOo>
RASI
MSEL CASI CASn
FIGURE 5. Designed Timing-Refresh with Error Correction
TL/F/9604-9
o"-------~-------
RASI -------1-
RASn
L,.,.i \_S..\.\.._\_3_ _ __
FIGURE 6. Desired Timing-Refresh without Error Correction
TL/F/9604-10
4-617
Q)
eCnD Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
-65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to+ 7.0V
Input Voltage (Note 2)
-0.5V to + 7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output 3-State Output
-0.5Vto Vee - 0.5V to + 5.5V
Current Applied to Output
in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Veo
lsv1 leEx
loo lozH lozL los lzz leeH leeL leez
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee 74F5% Vee 74F5% Vee
Output LOW Voltage
54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage 74F
Test
Output Leakage
Circuit Current
74F
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Buss Drainage Test
Power Supply Current
Power Supply Current
Power Supply Current
54F/74F Min Typ Max
2.0
0.8
-1.2
2.5 2.4 2.5 2.4 2.7 2.7
0.5 0.8 0.5 0.8
20.0 5.0
100 7.0
250 50
4.75
-60
3.75
-0.6 50 -50
-150 500 300 300 300
Units
v
v v
v
v
�A �A �A
v
�A
mA
�A �A
mA
�A
mA mA mA
Vee
Min
Min
Min
Max Max Max 0.0 0.0 Max Max Max Max
o.ov
Max Max Max
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal
l1N = -18 mA
loH = -1 mA loH = -3 mA loH = -1 mA loH = -3mA loH = -1 mA loH = -3mA loL = 1.0 mA loL = 12 mA loL = 1.0mA loL=12mA V1N = 2.7V
V1N = 7.0V
VouT =Vee
110 = 1.9 �A
All Other Pins Grounded V100 = 150 mV All Other Pins Grounded V1N = 0.5V VouT = 2.7V VouT = 0.5V
VouT = ov
VouT = 5.25V Vo= HIGH Vo= LOW
Vo = HIGH z
4-618
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
74F
Symbol
Parameter
TA= +25�C Vee= +5.0V
CL= 50 pF
TA, Vee= Com CL= 50 pF
TA, Vee= Com CL= 500 pF*
Min
Typ
Max
Min
Max
Min
Typ
Max
tPLH tPHL
Propagation Delay 3.0
AR to On
3.0
7.0
11.0
2.5
12.0
7.0
11.0
2.5
12.0
19.0 22.0
tPLH tPHL
Propagation Delay 3.0
AC to On
3.0
7.0
11.0
2.5
12.0
7.0
11.0
2.5
12.0
19.0 22.0
tPLH
Propagation Delay 3.5
8.0
12.0
3.0
13.0
23.0
tPHL
RASI to RASn
3.5
7.0
12.0
3.0
13.0
20.0
tPLH
Propagation Delay 1.0
6.0
8.0
1.0
8.5
tPHL
CASI to CASn
1.0
4.0
8.0
1.0
8.5
19.0 17.0
tPLH tPHL
Propagation Delay 3.0
MSEL to On
3.0
9.0
13.0
2.5
14.0
8.0
13.0
2.5
14.0
24.0 21.0
tPLH
Propagation Delay 4.0
10.0
15.0
3.5
16.0
tPHL
MCn to On
4.0
9.0
15.0
3.5
16.0
25.0 22.0
tPLH
Propagation Delay 3.5
11.0
17.5
3.0
18.5
tPHL
MCn to RASn
3.5
8.0
17.5
3.0
18.5
24.0 22.0
tPLH tPHL
Propagation Delay 4.0
MCn to CASn
4.0
8.0
12.5
3.5
13.5
9.0
12.5
3.5
13.5
23.0 21.0
tPLH tPHL
Propagation Delay 4.0
10.0
15.0
3.5
16.0
LE to RASn
4.0
9.0
15.0
3.5
16.0
25.0 24.0
tPLH tPHL
Propagation Delay 5.0
LE to CASn
5.0
9.0
13.5
4.5
14.5
9.0
13.5
4.5
14.5
24.0 24.0
tPLH tPHL
Propagation Delay 3.5
LE to On
3.5
8.0
12.0
3.0
13.0
7.0
12.0
3.0
13.0
23.0 22.0
tPLH
Propagation Delay 3.0
10.0
14.5
3.0
15.5
tPHL
CS to On
3.0
8.0
14.5
3.0
15.5
25.0 23.0
tPLH tPHL
Propagation Delay 3.5
CS to RASn
3.5
8.0
13.0
3.0
14.0
8.0
13.0
3.0
14.0
23.0 23.0
tPLH tPHL
Propagation Delay 4.0
CS to CASn
4.0
8.0
11.5
3.5
12.5
8.0
11.5
3.5
12.5
23.0 23.0
tPLH tPHL
Propagation Delay 4.0
SELn to RASn
4.0
9.0
15.5
3.5
16.0
8.0
15.5
3.5
16.0
24.0 23.0
tPLH tPHL
Propagation Delay 4.5
SELn toCASn
4.5
9.0
14.5
4.0
15.5
9.0
14.5
4.0
15.5
�These values are given for typical derivative with a 500 pF load; these are not guaranteed specifications.
24.0 24.0
eCnD
Q)
Units Fig. No.
ns 2-3 ns 2-3 ns 2-3 ns 2-3 ns 2-3 ns 2-3 ns 2-3 ns 2-3 ns 2-3 ns 2-3 ns 2-3 ns 2-3 ns 2-3 ns 2-3 ns 2-3 ns 2-3
4-619
co
CD
O> AC Electrical Characteristics (Continued): See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
tpHz tpLz
tpzH tpzL
tpHz tpLz
tpzH tpzL
tpHz tpLz
tpzH tpzL
Output Disable Time OE to On
Output Enable Time OE to On
Output Disable Time OE to RASn
Output Enable Time OE to RASn
Output Disable Time OE to CASn
Output Enable Time OEtoCASn
74F
TA= +25�C Vee= +5.0V
CL= 50pF
Min
Typ
Max
1.0
5.0
9.5
1.0
4.0
9.5
1.0
5.0
9.5
1.0
6.0
9.5
1.0
5.0
9.5
1.0
4.0
9.5
1.0
5.0
9.5
1.0
6.0
9.5
1.0
5.0
9.5
1.0
4.0
9.5
1.0
5.0
9.5
1.0
6.0
9.5
TA, Vee= Com CL= 50pF
Min
Max
1.0
10.0
1.0
10.0
1.0
10.0
1.0
10.0
1.0
10.0
1.0
10.0
1.0
10.0
1.0
10.0
1.0
10.0
1.0
10.0
1.0
10.0
1.0
10.0
Fig.
Units
No.
ns
2-5
ns
2-5
ns
2-5
ns
2-5
ns
2-5
ns
2-5
AC Operating Requirements: See Section 2 for Waveforms
Symbol
Parameter
t8 (H) t5 (L) th(H) th(L)
t8 (H) t8(L) th(H) th(L)
tw(H) tw(L)
tskew
Setup Time, HIGH or LOW An to LE
Hold Time, HIGH or LOW An to LE
Setup Time, HIGH or LOW SEL to LE
Hold Time, HIGH or LOW SEL to LE
Pulse Width, HIGH or LOW CASn, RASn
On to CASn, RASn
TA= +25�C Vee= +5.0V
Min
Max
5.0 5.0
5.0 5.0
5.0 5.0
5.0 5.0
15.0 15.0
10.0
74F
TA, Vee= Com
Min
Max
5.0 5.0
5.0 5.0
5.0 5.0
5.0 5.0
15.0 15.0
10.0
Fig. Units
No.
ns
2-6
ns
2-6
ns
2-6
ns
2-6
ns
2-4
ns
4-620
~National
U Semiconductor
54F/74F2241�54F/74F2244 Octal Buffers/Line Drivers with 250 Series Resistors in Outputs
General Description
The 'F2241 and 'F2244 are octal buffers and line drivers designed to drive the capacitive inputs of MOS memory drivers, address drivers, clock drivers and bus-oriented transmitters/receivers.
The 25n series resistors in the outputs reduce ringing and eliminate the need for external resistors.
Features
� TRI-STATE� outputs drive bus lines or buffer memory address registers
� 12 mA source current � 25n series resistors in outputs eliminate the need for
external resistors. � Designed to drive the capacitive inputs of MOS devices � Guaranteed 4000V minimum ESD protection
Ordering Code: see sections
Connection Diagrams
Pin Assignment for LCC
l[a]3]
mOb2 la2 C�J
Ornbt
rlnat
'F2241
ob3 rn
GND[QJ lb3 [j]
Oe,31!11 1b2 [j]
[I)Obo
IIJlao
OJOEt
Im Vee
[j]]OE2
[j]~[j]]IJ][j]]
Oa2 'bt Oe.1 Ibo Oao
TL/F/9499-1
le[.]3]Omb2 lCa�2J Ornbt r1ant
'F2244
ob3 rn
GND[QJ lb3 [j]
Oa31i11 lb2 [j]
[I)Obo IIJlao
OJO"Et
Im Vee
!l]]CiE2
[j]~[j]]IJ][j]]
Oa2 'bt Oe.1 lboOao
TL/F/9499-3
Pin Assignment for DIP, SOIC and Flatpak
20
CiEt
Vee
19
'e.o
18 OE2
Obo
Oe.o 17
'e.t
Ibo 16
Obt
Oe.t 15
'e.2
lbt 14
ob2
13 0a2
'e.3
lb2 12
ob3
oe.3 11
GND
lb3
TL/F/9499-2
20
CiEt
Vee
19
'e.o
OE2 18
Obo
Oe.o 17
1at
Ibo 16
ob1
Oat 15
1a2
14 'bt
ob2
13 0a2
'e.3
lb2 12
ob3
oe.3
11
GND
lb3
TL/F/9499-4
m
4-621
"Ill:!"
"Ill:!"
N
� N
T-
"Ill:!"
Logic Symbols
IEEE/I EC
N
'F2241
N
oc,
lao la1 1a2 1a3
OE2
Ibo lb1 lb2 lb3
TL/F/9499-5
IEEE/I EC 'F2244
oc,
lao la1 1a2 1a3
OE2
1bo lb1 lb2 lb3
TL/F/9499-6
Unit Loading/Fan Out: See Section 2 for U.L. definitions
Pin Names
Description
OE1. OE2 OE2 Ian� lbn Oan.Obn
TRI-STATE Output Enable Input (Active LOW) TRI-STATE Output Enable Input (Active HIGH) Inputs Outputs
�worst-case 'F2241, 'F2244 disabled
54F/74F
U.L. HIGH/LOW
Input l1HlllL Output loHlloL
1.0/1.667 1.0/1.667 1.0/2.667*
750/20
20 �A/-1 mA 20 �A/-1 mA 20 �A/-1.6 mA -15 mA/12 mA
Truth Tables
'F2241
'F2244
OE1
Ian
Oan
OE2
lbn
Obn
H
x
z
L
x z
L
H
H
H
H
H
L
L
L
H
L
L
OE1
Ian
Oan
OE2
lbn
Obn
H
x z
H
x z
L
H
H
L
H
H
L
L
L
L
L
L
H = HIGH Voltage Level L = LOW Voltage Level
X = Immaterial
Z = High Impedance
4-622
Absolute Maximum Ratings (Note 1>
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
-55�C to+ 175�C
Vee Pin Potential to Ground Pin
- 0.5V to + 7.0V
Input Voltage (Note 2)
-0.5V to + 7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
-0.5VtoVee - 0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
ESD Last Passing Voltage (Min)
4000V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C o�cto +70�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
54F/74F Min Typ Max
Units Vee
Conditions
V1H
Input HIGH Voltage
2.0
v
Recognized as a HIGH Signal
V1L
Input LOW Voltage
0.8
v
Recognized as a LOW Signal
Veo
Input Clamp Diode Voltage
-1.2
v
Min l1N = -18 mA
VoH
Output HIGH
Voltage
54F 10% Vee 2.4
54F 10% Vee 2.0
74F 10% Vee 2.4
74F 10% Vee 2.0
74F 5% Vee
2.7
loH = -3 mA
loH = -12 mA
v
Min
loH = -3 mA loH = -15mA
loH = -3 mA
Vol
Output LOW
Voltage
0.50
IQL = 1 mA
0.75
v
Min loL = 12 mA
l1H
Input HIGH
54F
Current
74F
20.0
5.0
�A Max V1N = 2.7V
lsv1
Input HIGH Current 54F
Breakdown Test
74F
100 7.0
�A Max V1N = 7.0V
leEX
Output HIGH
54F
Leakage Current
74F
250 50
�A Max Vour =Vee
V10
Input Leakage
74F
4.75
Test
v
0.0
110 = 1.9 �A All other pins grounded
loo
Output Leakage Circuit Current
74F
3.75
�A
0.0
V100 = 150 mV All other pins grounded
l1L
Input LOW Current
-1.0 -1.6
mA
Max
V1N = 0.5V (OE1, OE2, OE2) V1N = 0.5V (In)
lozH lozL los
Output Leakage Current Output Leakage Current Output Short-Circuit Current
-100
50
�A Max Vour = 2.7V
-50
�A Max Vour = 0.5V
-225 mA Max Vour = ov
leeH
Power Supply Current
40
60
mA Max Vo= HIGH
leeL
Power Supply Current
60
90
mA Max Vo= LOW
lccz
Power Supply Current
60
90
mA Max Vo= HIGH Z
4-623
v v
N
N,�....
AC Electrical. Characteristics: See Section 2 for Waveforms and Load Configurations
v
74F
54F
74F
N
N
TA= +25�C
Symbol
Parameter
Vee= +5.0V
TA, Vee= Mil CL= 50 pf
TA, Vee= Com CL= 50pf
CL= 50pf
Min
Typ
Max
Min
Max
Min
Max
tPLH
Propagation Delay
1.5
tPHL
Data to Output
2.5
7.0
2.0
6.5
1.5
7.0
8.0
2.0
7.0
2.0
8.0
tpzH tpzL
Output Enable Time
1.5
2.5
9.0
2.0
7.0
1.0
9.5
11.5
2.0
8.5
2.5
12.0
tpHz tpLz
Output Disable Time
1.5
1.5
9.0
2.0
7.0
1.0
9.5
8.5
2.0
7.5
1.5
9.5
Fig. Units No.
ns 2-3 ns 2-5
4-624
~National
D Semiconductor
54F/74F2243 Quad Bus Transceiver with 250 Series Resistors in the Outputs
General Description
The 'F2243 is a quad bus transmitter/receiver which can be used for 4-line asynchronous 2-way data communications between data busses. It is designed to drive the capacitive inputs of MOS memory drivers, address drivers, clock drivers, and bus-oriented transmitters/receivers.
The 25n series resistors in the outputs reduce ringing and eliminate the need for external resistors.
Features
� 25n series resistors in outputs eliminate the need for external resistors
� 2-Way asynchronous data bus communication � TRI-STATE� outputs � 12 mA source current � Designed to drive the capacitive inputs of MOS devices � Guaranteed 4000V minimum ESD protection
Ordering Code: See section 5 Logic Symbol
I E E E / I EC
Connection Diagram
Pin Assignment for DIP
TL/F/9530-1
Unit Loading/Fan Out: See section 2 for U.L. definitions
Pin Names
E1
E2 An, Bn
Description
Enable Input (Active LOW) Enable Input (Active HIGH) Inputs Outputs
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loHllOL
1.0/1.67 1.0/1.67 3.5/2.67 750/20
20 �A/-1 mA 20 �A/-1 mA 70 �A/-1.6 mA -15 mA/12 mA
Truth Table
Inputs
E1
E2
L
L
L
H
H
L
H
H
Inputs/Outputs
An
Input N/A
z
A=B
Bn
B=A N/A
z
Input
H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance N/A = Not Allowed
4-625
TL/F/9530-2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5Vto +7.0V
Input Voltage (Note 2)
-0.5Vto +7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
-0.5VtoVee -0.5Vto +5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
ESD Last Passing Voltage (Min)
4000V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
Veo
lsv1 lsv1T
l1H + lozH l1L + lozL las leEX leeH leeL leez
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee 74F 5% Vee
Output LOW Voltage
Input HIGH Current
Input HIGH Current Breakdown Test
Input HIGH Current Breakdown Test (1/0)
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Output HIGH Leakage Current
Power Supply Current
Power Supply Current
Power Supply Current
54F/74F Min Typ Max 2.0
0.8 -1.2
2.4 2.0 2.4 2.0 2.7
0.50 0.75 20
100
Units Vee
Conditions
v
Recognized as a HIGH Signal
v
Recognized as a LOW Signal
v
Min l1N = -18 mA
loH = -3 mA (An, Bn)
loH = -12 mA (An, Bn)
v
Min loH = - 3 mA (An, Bn)
loH = -15 mA (An. Bn)
loH = -3 mA (An, Bn)
v
loL = 1 mA (An. Bn) Min
loL = 12 mA (An. Bn)
�A Max
�A Max
1.0
mA Max
-1.0
mA
Max
70
�A
Max VouT = 2.7V (An, Bn)
-1.6
mA
Max VouT = 0.5V (An. Bn)
-100
-225 mA Max VouT = OV (An. Bn)
250
�A
Max VouT = Vee
64
80
mA Max Vo= HIGH
64
90
mA Max Vo= LOW
71
90
mA
z Max Vo = HIGH
4-626
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
tPLH tPHL
tpzH tpzL
tpHz tpLZ
Propagation Delay An to Bn, Bn to An
Output Enable Time E1 to Bn. E2 to An
Output Disable Time E1 to Bn, E2 to An
74F
TA= +25�C Vee= +5.0V
CL= 50pF
Min
Typ
Max
1.5
7.0
2.5
8.0
1.5
9.0
2.5
11.5
1.5
9.0
1.5
8.5
54F
TA, Vee= Mil CL= 50 pF
Min
Max
1.5
7.0
2.0
8.0
1.0
9.5
2.5
12.0
1.0
9.5
1.5
9.5
74F
TA, Vee= Com CL= 50 pF
Min
Max
1.5
7.0
2.0
8.0
1.0
9.5
2.5
12.0
1.0
9.5
1.5
9.5
Units
Fig. No.
ns 2-3 ns 2-5
II
4-627
CW)
C'\I
U CD
C'\I
�
~National
0 C'\I
Semiconductor
CD
C'\I
54F/74F2620 � 54F/74F2623
Inverting Octal Bus Transceiver
with 250 Series Resistors in the Outputs
General Description
These devices are octal bus transceivers designed for asynchronous two-way data flow between the A and B busses. These devices are functionally equivalent to the 'F620 and 'F623. The 25n series resistors in the outputs reduce ringing and eliminate the need for external resistors. Both busses are capable of sinking 12 mA, sourcing 15 mA, and have TRI-STATE outputs. Dual enable pins (GAB, GBA) allow data transmission from the A bus to the B bus or from the B bus to the A bus. The 'F2620 is an inverting option of the 'F2623.
Features
� 25n series resistors in the outputs eliminate the need for external resistors.
� Designed for asynchronous two-way data flow between busses
� Outputs sink 12 mA and source 15 mA � Dual enable inputs control direction of data flow � Guaranteed 4000V minimum ESD protection � 'F2620 is an inverting option of the 'F2623
Ordering Code: see section 5 Logic Symbol
GBA GAB
TL/F/10628-1
Unit Loading/Fan Out: see section 2 tor U.L. definitions
Pin Names
GBA,GAB Ao-A7 Bo-B7
Description
Enable Inputs A Inputs or TRI-STATE Outputs B Inputs or TRI-STATE Outputs
54F/74F
U.L. HIGH/LOW
Input l1H/l1L Output loH/loL
1.0/1.0 3.5/0.667
750/20 3.5/0.667
750/20
20 �A/-0.6 mA 70 �A/ - 0.4 mA -15mA/12mA 70 �A/-0.4 mA -15 mA/12 mA
Connection Diagrams
Pin Assignment for DIP, SOIC and Flatpak
GAB 1
Ao
A1 A2 A3 A1, 6 A5 7 As A1 GND 10
20 Yee
19 G8A 18 Bo 17 81 16 82 15 83 14 84 13 85 12 85 11 87
TL/F/10628-2
Pin Assignment for LCC
As As A1, A5 Az [[)[Z]IIJ11J0
G~ri:o~~
87 fill
[j]GA8
851!11
@Vee
85 Ii}]
[ID G8A
~[�)[fil[Z][fil
84 83 ~ 81 Bo
TL/F/10628-3
4-628
Functional Description
The enable inputs GAB and GBA control whether data is transmitted from the A bus to the B bus or from the B bus to the A bus. If both GBA and GAB are disabled (GBA HIGH and GAB low), the outputs are in the high impedance state and data is stored at the A and B busses. When GBA is active (LOW), B data is sent to the A bus. When GAB is active (HIGH), data from the A bus is sent to the B bus. If both enable inputs are active (GBA LOW and GAB HIGH) B data is sent to the A bus while A data is sent to the B bus.
eN n
N
Function Table
0 �
Enable Inputs
Operation
eN n Ncu
GBA GAB
'F2620
'F2623
L
L
B Data to A Bus B Data to A Bus
H
H
A Data to B Bus A Data to B Bus
H
L
z
z
L
H
8 Data to A Bus, B Data to A Bus,
A Data to B Bus A Data to B Bus
H = HIGH Voltage Level L = LOW Voltage Level
Z = High Impedance
Logic Diagram
'F2620
TL/F/10628-4 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
'F2623
TL/F/10628-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-629
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
-55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to + 7.0V
Input Voltage (Note 2)
-0.5Vto +7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
-0.5Vto Vee -0.5V to + 5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
ESD Last Passing Voltage (Min)
4000V
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�cto +70�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
V1H V1L Veo VoH
Vol
l1H
lsv1
lsv1T
leEx
V10
loo
l1L l1H + lozH l1L + lozL los lzz leeH lecL leez leeH leeL leez
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 74F 10% Vee
Output LOW Voltage
Input HIGH
54F
Current
74F
Input HIGH Current
54F
Breakdown Test
74F
Input HIGH Current
54F
Breakdown Test (1/0) 74F
Output HIGH
54F
Leakage Current
74F
Input Leakage 74F
Test
Output Leakage 74F
Circuit Current
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Bus Drainage Test
Power Supply Current ('F2620)
Power Supply Current ('F2620)
Power Supply Current ('F2620)
Power Supply Current ('F2623)
Power Supply Current ('F2623)
Power Supply Current ('F2623)
54F/74F Min Typ Max 2.0
0.8 -1.2 2.0 2.0 0.5 0.75 20.0 5.0 100 7.0 1.0 0.5 250
50
4.75
-100
3.75
-0.6 70
-650 -225 500
82 82 95 82 82 95
Units
v v v
v v
�A
�A
mA
�A
v
�A mA �A �A mA �A mA mA mA mA mA mA
Vee
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal Min l1N = -18 mA (Non 110 Pins) loH = -12 mA (An, Bn) Min loH = -15 mA (An, Bn) Min loL = 1.0 mA (An. Bn) loL = 12 mA (An, Bn)
Max V1N = 2.7V (Non 1/0 Pins)
Max V1N = 7.0V (Non 1/0 Pins)
Max V1N = 5.5V (An, Bn)
Max VouT =Vee
0.0
0.0
Max Max Max Max
o.ov
Max Max Max Max Max Max
110 = 1.9 �A All Other Pins Grounded V100 = 150 mV All Other Pins Grounded V1N = 0.5V (Non 1/0 Pins) VouT = 2.7V (An, Bn) VouT = 0.5V (An. Bn)
VouT = ov
VouT = 5.25V Vo = HIGH, V1N = 0.2V Vo= LOW Vo= HIGHZ Vo= HIGH Vo = LOW, V1N = 0.2V Vo= HIGHZ
4-630
I\)
a>
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
I\)
0
74F
54F
74F
�
I\)
a>
Symbol
Parameter
TA= +25�C Vee= +5.0V
TA, Vee= Mil CL= 50 pF
I\)
TA, Vee= Com
Fig. Units
CJ,)
CL= 50 pF
No.
CL= 50 pF
Min
Typ
Max
Min
Max
Min
Max
tPLH
Propagation Delay
2.5
7.5
tPHL
A Input to B Output ('F2620)
3.0
8.0
2.0
8.0
ns 2-3
3.0
8.0
tPLH
Propagation Delay
2.5
7.5
tPHL
B Input to A Output ('F2620)
3.0
8.0
2.0
8.0
ns 2-3
3.0
8.0
tPLH
Propagation Delay
1.5
6.5
tPHL
A Input to B Output ('F2623)
2.5
7.5
1.5
7.5
ns 2-3
2.5
8.0
tPLH
Propagation Delay
1.5
6.5
tPHL
B Input to A Output ('F2623)
2.5
7.5
1.5
7.5
ns 2-3
2.5
8.0
tpzH
Enable Time
2.0
7.0
tpzL
GBA Input to A Output
2.5
8.0
tpHz
Disable Time
1.5
6.5
tpLz
GBA Input to A Output
1.0
5.5
2.0
8.0
2.0
8.5
ns 2-5
1.5
7.5
1.0
5.5
tpzH
Enable Time
2.0
7.5
tpzL
GAB Input to B Output ('F2620) 3.0
8.0
tpHz
Disable Time
2.5
8.0
tpLz
GAB Input to B Output ('F2620) 2.0
7.5
2.0
8.5
2.0
8.5
ns 2-5
2.0
9.0
2.0
8.0
tpzH
Enable Time
2.0
7.5
tpzL
GAB Input to B Output ('F2623) 2.5
8.0
tpHz
Disable Time
2.0
8.0
tpLz
GAB Input to B Output ('F2623) 2.0
8.0
2.0
8.5
2.0
8.5 ns 2-5
2.0
9.0
2.0
8.0
Basic FAST Circuit Showing Series Resistor Placement
Yee
> ~
~
;>
.? ~
~ ~
~
, LOGIC _.... ..........
1 ~ "'Ill
~01
]'.as
06
cY
OE
......
~
"'Ill
1 ~
f{:o2 "'Ill
=~~~
~: ~~
~>Rs
] ' .03
~
~
~
~ ~
>~:
~
>
~,. ~,
~� 4~ ~7
~
~
Rs= 250
-=- -
TL/F/10628-6
4-631
~National
~Semiconductor
54F/74F2640 � 54F/74F2643 � 54F/74F2645 Octal Bus Transceiver with 25!! Series Resistors in the Outputs
General Description
These devices are octal bus transceivers designed for asynchronous two-way data flow between the A and B busses. These devices are functionally equivalent to the 'F640, 'F643, and 'F645. The 25!1 series resistors in the outputs reduce ringing and eliminate the need for external resistors. Both busses are capable of sinking 12 mA, sourcing 15 mA, have TRI-STATE outputs, and a common output enable pin. The direction of data flow is determined by the transmit/receive (T/R) input. The 'F2640 is an inverting version of the 'F2645. The 'F2643 has a noninverting A bus and an inverting B bus. The 'F2645 is a low power version of the 'F245 with 25!1 series resistors in the outputs.
Features
� 25!1 series resistors in the outputs eliminates the need for external resistors
� Designed for asynchronous two-way data flow between busses
� Outputs sink 12 mA and source 15 mA � Transmit/receive (T/R) input controls the direction of
data flow � Guaranteed 4000V minimum ESD protection � 'F2645 is a low power version of the 'F245 with 25!1
series resistors in the outputs � 'F2640 is an inverting option of the 'F2645 � 'F2643 has noninverting A bus and inverting B bus
Ordering Code: see section 5 Logic Symbol
Connection Diagrams
0E T/R
TL/F/10629-1
Unit Loading/Fan Out: See Section 2 tor u.L. definitions
Pin Names
OE T/R Ao-A7 80-87
Description
Output Enable Input (Active LOW) Transmit/Receive Input Side A Inputs or TRI-STATE Outputs Side B Inputs or TRI-STATE Outputs
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loH/loL
1.0/1.0
1.0/1.0 3.5/0.667
750/20 3.5/0.667
750/20
20 �A/-0.6 mA
20 �A/-0.6 mA 70 �Al - 0.4 mA -15 mA/12 mA 70 �A/-0.4 mA -15 mA/12 mA
Pin Assignment for DIP, SOIC and Flatpak
T/R
Ao Al A2 4 A3 5 A4 As As A7 GND 10
20 Vee
19 6E
18 Bo 17 Bl 16 B2 15 B3 14 B4 13 Bs 12 Bs 11 B7
TL/F/ 10629-2
Pin Assignment for LCC and PCC
Ar, As A4 A3 A1
lli][l][[)[[][I]
A1 [[I GND [QI
B7 !TII
Bs U1]
Bs lill
[I]A1
[I]Ao
III T/R
~Vee [j]]Q[
li]ii]][j]J[Z]ff�J
B4 B3 82 Bl Bo
TL/F/10629-3
4-632
Functional Description
The output enable (OE) is active LOW. If the device is disabled (OE HIGH), the outputs are in the high impedance state. The transmit/receive input (T/R) controls whether data is transmitted from the A bus to the B bus or from the B
bus to the A bus. When T /R is LOW, B data is sent to the A bus. If T /R is HIGH, A data is sent to the B bus.
Function Table
Inputs
Outputs
OE T/R
'F2640
'F2643
'F2645
L
L Bus B data to Bus A Bus B data to Bus A Bus B data to Bus A
L H Bus A data to Bus B Bus A data to Bus B Bus A data to Bus B
H xz
z
z
H = High voltage level
L = Low voltage level
X = Don't care Z = High-impedance state
Logic Diagrams
'F2640
'F2643 'F2645
4-633
m N
.i:a. 0
�
m N
�.wi:a.
m N
~
U1
TL/F/10629-4 TL/F/10629-5 TL/F/10629-6
Absolute Maximum Ratings (Note 1>
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�c
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5V to+ 7.0V
Input Voltage (Note 2)
-0.5V to + 7.0V
Input Current (Note 2)
-30 mA to + 5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
-0.5VtoVee -0.5Vto +5.5V
Current Applied to Output in LOW State (Max)
twice the rated loL (mA)
ESD Last Passing Voltage (Min)
4000V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful .life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�c o�cto +70�c
Supply Voltage Military Commercial
+ 4.5V to + 5.5V
+4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Parameter
V1H VrL Yeo VoH
VoL
l1H
lsvr
lsvrT
leEx
Vro
loo
lrL lrH + lozH
lrL + lozL
los lzz lecH lecL lccz lecH lccL lccz lccH lecL iecz
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 74F 10% Vee
Output LOW Voltage
74F10% Vee 74F 10% Vee
Input HIGH
54F
Current
74F
Input HIGH Current 54F
Breakdown Test
74F
Input HIGH Current 54F
Breakdown (1/0)
74F
Output HIGH
54F
Leakage Current
74F
Input Leakage Test
74F
Output Leakage Circuit Current
74F
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Bus Drainage Test
Power Supply Current ('F2640)
Power Supply Current ('F2640)
Power Supply Current ('F2640)
Power Supply Current ('F2643)
Power Supply Current ('F2643)
Power Supply Current ('F2643)
Power Supply Current ('F2645)
Power Supply Current ('F2645)
Power Supply Current ('F2645)
54F/74F Min Typ Max 2.0
0.8 -1.2
2.0 2.0
0.50 0.75
20.0 5.0 100 7.0
1.0 0.5 250 50
4.75
-100
3.75
-0.6 70 -650 -225 500 82 82 95 82 82 95 82 82 95
Units
v v v v
v
�A
�A
mA
�A
v
�A
mA �A �A mA �A mA mA mA mA mA mA mA mA mA
Vee
Min Min
Min
Max
Max
Max
Max
0.0
0.0 Max Max Max Max
o.ov
Max Max Max Max Max Max Max Max Max
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal l1N = -18 mA (Non 1/0 Pins) loH = -12 mA (An, Bn) loH = -15 mA (An, Bn) loL �= 1 mA (An, Bn) loL = 12 mA (An, Bn) V1N = 2.7V (Non 1/0 Pins)
VrN = 7.0V (Non 1/0 Pins)
VrN = 5.5V (An, Bn)
VouT =Vee
lro = 1.9 �A All Other Pins Grounded Vroo = 150mV All Other Pins Grounded V1N = 0.5V (Non 1/0 Pins) VouT = 2.7V (An, Bn) VouT = 0.5V (An, Bn)
VouT = ov
VouT = 5.25 Vo = HIGH, V1N = 0.2V Vo= LOW Vo= HIGHZ Vo = HIGH, V1N = 0.2V (An) Vo = LOW, VrN = 0.2V (Bn) Vo= HIGHZ Vo= HiGH Vo = LOW, VrN = 0.2V Vo= HIGHZ
4-634
N
O>
'F2640 AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
.i:i. C>
74F
54F
74F
�
N
O>
Symbol
Parameter
TA= +25�C Vee= +5.0V
TA, Vee= Mil CL= 50 pF
TA, Vee= Com CL= 50 pF
Units
Fig. No.
�w.i:i.
CL= 50 pF
N
O>
Min
Typ
Max
Min
Max
Min
Max
.i:i. (J'1
1PLH
Propagation Delay
2.5
7.5
1PHL
A Input to B Output
2.5
7.5
2.0
8.0
2.5
7.5
ns
2-3
tPLH
Propagation Delay
2.5
7.5
tPHL
B Input to A Output
2.5
7.5
2.0
8.0
ns
2-3
2.5
7.5
tpzH
Enable Time
2.5
7.5
tpzL
OE Input to A Output
2.5
8.0
tpHz
Disable Time
1.5
7.0
tpLz
OE Input to A Output
1.5
6.0
2.0
9.0
2.0
8.5
ns
2-5
1.0
7.5
1.5
6.0
tpzH
Enable Time
2.5
7.5
tpzL
OE Input to B Output
2.5
8.0
tpHz
Disable Time
1.5
6.5
tpLz
OE Input to B Output
1.5
6.0
2.0
9.0
2.0
8.5
ns
2-5
1.0
7.5
1.5
6.0
'F2643 AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
tPLH tPHL
tPLH tPHL
tpzH tpzL
tpHz tpLz
tpzH tpzL
tpHz tpLZ
Propagation Delay A Input to B Output
Propagation Delay B Input to A Output
Enable Time OE Input to A Output
Disable Time OE Input to A Output
Enable Time OE Input to B Output
Disable Time OE Input to B Output
74F
TA= +25�C Vee= +5.0V
CL= 50 pF
Min
Typ
Max
2.5
7.5
2.5
7.5
2.5
7.0
2.5
7.5
2.5
8.0
2.5
8.5
1.5
7.0
1.0
5.5
2.5
7.5
2.5
8.0
1.5
6.5
1.5
6.0
54F
TA, Vee= Mil CL= 50 pF
Min
Max
74F
TA, Vee= Com CL= 50pF
Min
Max
2.0
8.0
2.5
7.5
2.5
8.0
2.5
8.0
2.0
9.0
2.0
8.5
1.0
8.0
1.0
5.5
2.0
9.0
2.0
8.5
1.0
7.5
1.5
6.0
Fig. Units
No.
ns
2-3
ns
2-3
ns
2-5
ns
2-5
4-635
'F2645 AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
tPLH
Propagation Delay
tPHL
A Input to 8 Output
tPLH
Propagation Delay
tPHL
8 Input to A Output
tpzH
Enable Time
tpzL
OE Input to A Output
tpHz
Disable Time
tpLz
OE Input to A Output
tpzH
Enable Time
tpzL
OE Input to B Output
tpHz
Disable Time
tpLZ
OE Input to B Output
74F
TA= +25�C Vee= +5.0V
CL= 50 pf
Min
Typ
Max
1.5
6.0
2.5
7.5
1.5
6.0
2.5
7.5
2.5
8.0
2.5
8.5
1.5
7.0
1.0
5.5
2.5
7.5
2.5
8.5
1.5
6.5
1.0
6.5
54F
TA, Vee= Mii CL= 50 pf
Min
Max
74F
TA, Vee= Com CL= 50pF
Min
Max
1.5
7.0
2.5
8.0
1.5
7.0
2.5
8.0
2.0
9.0
2.0
8.5
1.0
8.0
1.0
5.5
2.0
9.5
2.5
9.0
1.0
7.5
1.0
6.5
Fig. Units
No. ns 2-3 ns 2-3 ns 2-5
ns 2-5
Basic FAST Circuit Showing Serles Resistor Placement
4-636
TL/F/10629-7
I\)
co
~~SNemaitcoinoduncatolr
"cT.n1
�I\)
I\)
co
cw"T.n1
29F52�29F53
8-Bit Registered Transceiver
General Description
The 29F52 and 29F53 are 8-bit registered transceivers. Two 8-bit back to back registers store data flowing in both directions between two bidirectional buses. Separate clock, clock enable and TRI-STATE� output enable signals are provided for each register. The A0-A7 output pins are guaranteed to sink 24 mA (20 mA mil.) while the B0-B7 output pins are designed for 64 mA.
The 29F53 is an inverting option of the 29F52. Both transceivers are AMO Am2952/2953 functional equivalents.
Features
� 8-bit registered transceivers � Separate clock, clock enable and TRI-STATE output
enable provided for each register � AMO Am2952/2953 functional equivalents � Both inverting and non-inverting options available � 24-Pin slimline package
Ordering Code: see sections
Logic Symbols
29F52
29F53
Ao A1 A2 A5 A4 As As A1 OEB OEA CPA CPB CEB CEA
I E E E / I EC 29F52
TL/F/9606-1
I E E E / I EC 29F53
TL/F/9606-7
Ao
Bo
Ao
iio
A1
81
A1
ii,
A2
82
A2
ii2
A3
83
A3
83
A4
84
A4
84
As
Bs
As
iis
As
Bs
As
iis
A7
87 A1
TL/F/9606-4
87
TL/F/9606-5
II
4-637
(")
LI)
LenL Connection Diagrams (Continued)
�C\I
C\I
Pin Assignment
LI)
for DIP, SOIC and Flatpak
LenL
29F52
C\I
B1 1 Bs 2 Bs 3 B4 4 B3 B2 B1 Bo OEB CPA 10 CEA 11 GND 12
24 Vee 23 A1 22 As 21 As 20 A4 19 A3 18 A2 17 A1 16 Ao 15 OEA 14 CPB 13 CEB
TL/F/9606-2
Pin Assignment for LCC and PCC
29F52
OEB [j]
Bo l!QI
rBn1
NC [[I
B2 B3
m rn
B4
m
CPA IIl]
CEA~
GND Ii]
NC [ill
CEB Im
CPB [Z] OEA [�]
III Bs
ITlBs [II 87 [i]NC ~Vee
ill! A1
rm As
fffil~~~l?]~!m
Ao A1 A2 NC A3 A4 As
TL/F/9606-3
Pin Assignment for DIP, SOIC and Flatpak
29F53
81 iis 2 Eis 3 84 4 83 5 82 81 Bo 8 OEB 9 CPA 10 CEA 11 GND 12
24 Vee 23 A1 22 As 21 As 20 A4 19 A3 18 A2 17 A1 16 Ao 15 OEA 14 CPB 13 CEB
TL/F/9606-8
Pin Assignment for LCC and PCC
29F53
OEB [j]
ii0 l!QI
rini1[N[CI
B2 B3
m rn
B4
m
CPA iil]
CEA~
GND Ii]
NC [ill
CEB Im
CPB [Z] OEA [�]
III 85
mes
rn ii1
[i]NC
~Vee
Ill! A1
rm As
fffil~~~l?]~!m Ao A.1 A.2 NC A3 A4 As
TL/F/9606-9
Unit Loading/Fan Out: See Section 2 for U.L. definitions
Pin Names
Ao-A7
80-87
OEA CPA CEA OE8 CPB CEB
Description
A-Register Inputs/ 8-Register TRI-STATE Outputs 8 Register Inputs/ A-Register TRI-STATE Outputs Output Enable A-Register A-Register Clock A-Register Clock Enable Output Enable 8-Register B-Register Clock B-Register Clock Enable
54F/74F
U.L. HIGH/LOW
Input l1Hll1L Output loH/loL
3.5/1.083 150/40 (33.3)
3.5/1.083 600/106.6 (80)
1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0
70 �A/0.65 mA -3 mA/24 mA (20 mA)
70 �A/0.65 mA -12 mA/64 mA (48 mA)
20 �A/-0.6 mA 20 �Al - 0.6 mA 20 �A/-0.6 mA 20 �A/-0.6 mA 20 �Al - 0.6 mA 20 �A/-0.6 mA
4-638
Block Diagrams
CPA
ill
29F52
~
~ CE
Do
CP Oo
D1 +--*
g D2
02
D3
03
Register A
D4
04
D5
05
D5 05H
D1
07K
Oo
Do
L--(
01
D1
~
02
D2
03
D3
Register B
04
D_.
05
D5
05
D5
07
D7
-
CE CP
""Q'
.,,N
(0 UI
.,,�N
N (0
Uw I
Cilli
Bo 81 82 B3 84 85 85 87
CPB
cre
TL/F/9606-6
4-639
CW)
Lt)
LL
O>
Block Diagrams (Continued)
�C\I
C\I
Lt)
LL
CPA
O> C\I
ill
29F53
l
CE Do
~Oo
-
./L..
o,
CP o,
~
ii,
02
02
-
D5
H 05
-
Register A
04
04
-
05
05
'-,....
Os
Os
-
07
07
'-
Output Control
Internal
Y-Output
OE
Q
29F52 29F53
H
x
z z
L
L
L
H
L
H
H
L
H = HIGH Voltage Level
L = LOW Voltage Level X = Immaterial Z = HIGH Impedance
.../ = LOW-to-HIGH Transition
NC = No Change
Oo
Do
o,
o,
-
02
D2
--
05
D5
Register B
-
04
D4
-
05
D5
-
Os
Ds
-
07
D7
llCE CP
CPB
CEii
TL/F/9606-10
Function
Disable Outputs Enable Outputs
Register Function Table (Applies to A or B Register)
Inputs
D
CP
CE
x x
H
L
_r
L
H
_r
L
Internal Q
NC L H
Function
Hold Data Load Data
4-640
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
-55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5Vto +7.0V
Input Voltage (Note 2)
-0.5Vto +7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE Output
-0.5VtoVee -0.5Vto +5.5V
Current Applied to Output
in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
cN o
Recommended Operating
"'T1 U1
Conditions
Free Air Ambient Temperature
� N
Nco
Military Commercial
- 55�C to + 125�C 0�Cto +70�C
"'T1
wU1
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol V1H V1L Veo VoH
VoL
ltH lsv1 lsv1T l1L l1H + lozH l1L + lozL los leEx lzz leeH leeL leez
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee 74F 10% Vee 74F5% Vee 74F 5% Vee
Output LOW Voltage
54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee
Input HIGH Current
Input HIGH Current Breakdown Test
Input HIGH Current Breakdown Test (1/0)
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Output HIGH Leakage Current Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current
54F/74F
Min Typ Max
2.0
0.8
-1.2
2.5 2.4 2.0 2.5 2.4 2.0 2.7 2.7
0.5 0.55 0.5 0.55
20
100
1.0
-0.6
70
-650
-60 -100
-150 -225
250
500
130
190
190
190
Units
v v v
v
v
�A �A mA mA �A �A mA �A �A mA mA mA
Vee
Conditions
Recognized as a HIGH Signal
Recognized as a LOW Signal
Min l1N = -18 mA (Non 1/0 Pins)
loH = -1 mA (An)
loH = -3 mA (An, Bn)
loH = -12 mA (Bn)
Min
loH = -1 mA (An) loH = - 3 mA (An, Bn)
loH = -15 mA (Bn)
loH = -1 mA (An)
loH = - 3 mA (An. Bn)
loL = 20 mA (An) Min loL = 48 mA (Bn)
loL = 24 mA (An) loL = 64 mA (Bn)
Max V1N = 2.7V (Non-1/0 Pins)
Max V1N = 7.0V (Non-1/0 Pins)
Max V1N = 5.5V (An. Bn)
Max Max Max
Max�
Max
o.ov
Max Max Max
V1N = 0.5V (Non-1/0 Pins) VouT = 2.7V (An. Bn) VouT = 0.5V (An, Bn) VouT = OV (An) VouT = OV (Bn) VouT =Vee (An, Bn) VouT = 5.25V (An. Bn) Vo= HIGH Vo= LOW Vo= HIGHZ
4-641
C")
Lt)
~ AC Electrical Characteristics: See Section 2 for waveforms and Load Configurations
"'"�'uLt.)
O>
"' Symbol
Parameter
74F
TA= +25�C .Vee= +5.0V
CL= 50 pf
54F
TA, Vee= Mil CL= 50pF
74F
TA, Vee= Com CL= 50pF
Fig. Units
No.
Min
Typ
Max
Min
Max
Min
Max
tPLH
Propagation Delay
3.0
5.5
7.5
tPHL
CPA or CPB to An or Bn
4.0
7.0
9.0
2.5 3.5
8.5 10.0
ns 2-3
tpzH
Output Enable Time
2.5
5.5
7.5
tpzL
OEA or OEB to An or Bn 3.5
7.0
9.5
2.0
8.5
ns 2-5
3.0
10.5
tpHz
Output Disable Time
2.5
6.5
9.0
tpLz
OEA or OEB to An or Bn
2.5
5.5
7.5
2.0 2.0
10.0 8.5
ns 2-5
AC Operating Requirements: See Section 2 for Waveforms
Symbol
Parameter
t5 (H) t 5 (L)
th(H) th(L)
t 5 (H) t 5 (L)
th(H) th(L)
tw(H) tw(L)
Setup Time, HIGH or LOW An or Bn to CPA or CPB
Hold Time, HIGH or LOW An or Bn to CPA or CPB
Setup Time, HIGH or LOW CEA or CEB to CPA or CPB
Hold Time, HIGH or LOW CEA or CEB to CPA or CPB
Pulse Width, HIGH or LOW CPAorCPB
74F
TA= +25�C Vee= +5.0V
Min
Max
4.0 4.0
2.0 2.0
1.0 4.0
2.0 2.0
3.0 3.0
54F
TA, Vee= Mil
Min
Max
74F
TA, Vee= Com
Min
Max
4.5 4.5
2.5 2.5
1.5 4.5
2.5 2.5
3.5 3.5
Fig. Units
No.
ns 2-6 ns 2-6 ns 2-6 ns 2-6 ns 2-4
4-642
.,,N
CD
~National
m
CX>
~Semiconductor
29F68 Dynamic RAM Controller
General Description
The 29F68 is a high-performance memory controller, replacing many SS! and MSI devices by grouping several unique functions. It provides two 9-bit address latches and two 9-bit counters for row and column address generation during refresh. A 2-bit bank select latch for row and column address generation during refresh, and a 2-bit bank select latch for the two high order address bits are provided to select one of the four RAS and CAS outputs.
The 29F68 is functionally equivalent to AMD's Am2968 and Motorola's MC74F2968.
Features
� High-performance memory controller � Replaces many SSI and MS! devices by grouping
several unique functions � Functionally equivalent to AMD's Am2968 and
Motorola's MC74F2968 � Provides control for 16K, 64K, or 256K dynamic RAM
systems � Outputs directly drive up to 88 DRAMs � Highest order two address bits select one of four banks
of RAMs � Chip Select for easy expansion � Provides memory refresh with error correction mode
Ordering Code: see sections
Logic Symbol
cs
MSEL LE SEL1 SELo MC1 MC0 RASI CASI OE
Connection Diagram
Pin Assignment for LCC and PCC AR1ACsARs ACsARs LE GND AC4AR4AC3AR3ACiAR2
liQ!lifilli]][Z]ll!J~IHllLlllll![i][QJ[[][[)
TL/F/9608-1
AC7 g:i]
ARs illl
AC8 � SELo~ SEL 1 ~ MC 1 ~ MC0 [Z]
RASI~
CAS3 ~ RAS3 ~ CAS2 mJ
NC (g]
RAS2 [nJ
III NC
[�] AC1 [[] AR1
III AC0
[I] AR0 (1]MSEL
[I]Cs
~CASI
Ifill RASo
~ CASo ~ RASo ~ CAS1
Im Oo
~~~!m~@l~!iil~~IBJ~~
o, Os 07 Os Os Vee Vee OE GND 04 03 02 NC
TL/F/9608-2
4-643
ClO
CD
LL O>
Pin Description
N
Name
1/0
ARo-ARa
I
ACo-ACa
SEL0-SEL1
I
LE
I
MSEL
I
cs
I
OE
I
MCo, MC1
I
Oo-Oa
0
RASI
I
.RAS0-RAS3
0
CASI
I
CAS0-CAS3
0
Description
Address Inputs. AR0-AR8 are latched in as the 9-bit Row Address for the RAM. These inputs drive Oo-Oa when the 29F68 is in the Read/ Write mode and MSEL is LOW. ACo-AC8 are latched in as the Column Address, and will drive Oo-Oa when MSEL is HIGH and the 29F68 is in the Read/Write mode. Tho addresses are latched with the Latch Enable (LE) signal.
Bank Select. These two inputs are normally the two higher order address bits, and are used in the Read/Write mode to select which bank of memory will be receiving the RASn and CASn signals after RASI and CASI go HIGH:
Latch Enable. This active-HIGH input causes the Row, Column and Bank Select latches to become transparent, allowing the latches to accept new input data. A LOW input on LE latches the input data, assuming it meets the setup and hold time requirements.
Multiplexer Select. This input determines whether the Row or Column Address will be sent to the memory address inputs. When MSEL is HIGH the Column Address is selected, while the Row Address is selected when MSEL is LOW. The address may come from either the address latch or refresh address counter depending on MCo, MC1.
Chip Select. This active-LOW input is used to enable the 29F68. When CS is active, the 29F68 operates normally in all four modes. When CS goes HIGH, the device will not enter the Read/Write mode. This allows other devices to access the same memory that the 29F68 is controlling (e.g., OMA controller).
Output Enable. This active-LOW input enables/disables the output signals. When OE is HIGH, the outputs of the 29F68 enter the high impedance state. The OE signal allows more than one 29F68 to control the same memory, thus providing an easy method to expand the memory size.'
Mode Control. These inputs are used to specify which of the four operating modes the 29F68 should be using. The description of the four operating modes is given in the Mode Control Function Table.
Address Outputs. These address outputs will feed the DRAM address inputs and provide drive for memory systems up to 500 pF in capacitance.
Row Address Strobe Input. During normal memory cycles, the decoded RASn output (RASci, RAS1, RAS2 or RAS3) is forced LOW after receipt of RASI. In either refresh mode, all four RASn outputs will go LOW following RASI going HIGH.
Row Address Strobe. Each one of the Row Address Strobe outputs provides a RASn signal to one of the four banks of dynamic memory. Each will go LOW only when selected by SELo and SEL1 and only after RASI goes HIGH. All four go LOW in response to RASI in either of the Refresh modes.
Column Address Strobe Input. This input going active will cause the selected CASn output to be forced LOW.
Column Address Strobe. During normal Read/Write cycles the two select bits (SELo, SEL1) determine which CASn output will go active following CASI going HIGH. When memory error correction is performed, only the CASn signal selected by CNTRo and CNTR1 will be active. For non-error correction cycles, all four CASn outputs remain HIGH.
4-644
Functional Description
The 29F68 is designed to be used with 16k, 64k, or 256k dynamic RAMs and is functionally equivalent to AMD's AM2968. The 29F68 provides row/column address multiplexing, refresh address generation and bank selection for up to four banks of RAMs.
Twenty (20) address bits (ARo-AR8, AC0 -AC8, and bank select addresses SELo and SEL1) are presented to the controller. These addresses are latched by a 20-bit latch. A 20bit counter generates the refresh address.
N
CD
e"Tn1
A 9-bit multiplexer selects the output address between the
CIC)
input row address, column address, refresh counter row ad-
dress, column address, or zero (clear). Four RAS and four
CAS outputs select the appropriate bank of RAMs and
strobe in the row and column addresses.
It should be noted that the counters are cleared (MC0, MC1 = 1,1) on the next RASI transition, but the Q outputs are asynchronously cleared through the multiplexer.
Mode Control Function Table
MCo
Operating Mode
0
0
Refresh without Error Correction. Refresh cycles are performed with
only the Row Counter being used to generate addresses. In this mode,
all four RASn outputs are active while the four CASn signals are kept
HIGH.
0
Refresh with Error Correction/Initialize-During this mode, refresh
cycles are done with both the Row and Column counters generating
the addresses. MSEL is used to select between the Row and Column
counter. All four RASn outputs go active in response to RASI, while
only one CASn output goes LOW in response to CASI. The Bank
Counter keeps track of which CASn output will go active. This mode is
also used on system power-up so that the memory can be written with
a known data pattern.
0
Read/Write- This mode is used to perform Read/Write cycles. Both
the Row and Column addresses are latched and multiplexed to the
address output lines using MSEL; SEL0 and SEL1 are decoded to determine which RASn and CASn will be active.
Clear Refresh Counter-This mode will clear the three refresh counters (Row, Column, and Bank) on the HIGH-to-LOW transition of RASI, putting them at the start of the refresh sequence..In this mode, all four RASn are driven LOW upon receipt of RASI so that DRAM wake-up cycles may be performed. This mode also asynchronously clears the On outputs.
Address Output Function Table
MC1
MCo
MSEL
Mode
MUX Output
L
L
L
x
Refresh without Error Correction
Row Counter Address
L
H
H
Refresh with Error Correction
Column Counter Address
L
Row Counter Address
H
L
H
Read/Write
Column Address Latch
H
H
H
L
L
L
Row Address Latch
x
Clear Refresh Counter
Zero
x
Refresh without Error Correction
Row Counter Address
L
H
H
Refresh with Error Correction
Column Counter Address
H
L
H
H
L
x
Read/Write
x
Clear Refresh Counter
Row Counter Address Zero Zero
4-645
ccoo
lL
RAS Output Function Table
O>
N
RASI cs MC1 MCo SEL1 SELo
Mode
L xx x
x
x
Non-refresh
H
L
L
L
x
x
Refresh without Scrubbing
L
H
x
x
Refresh with Scrubbing
RASo H L L
RAS1 H L L
RAS2 H L L
RAS3 H L L
H
L
L
L
Read/Write
L
H
H
H
L
H
H
L
H
H
H
L
H
H
L
H
H
H
H
H
H
L
H
H
x
x
Clear Refresh Counter
L
L
L
L
H
L
L
x
x
Refresh without Error Correction
L
L
L
L
L
H
Refresh with Error Correction
L
L
L
L
H
L
Read/Write
H
H
H
H
H
H
Clear Refresh Counter
L
L
L
L
CAS Output Function Table
Inputs
Internal Counter
CASI
cs
MC1
MCo
CNTR1
H
L
L
L
x
CNTRo
x
L
H
L
L
Inputs
SEL1 SELo
x x x x
CA So H L
Outputs
CAS1 CAS2
H
H
H
H
CAS3 H H
L
H
H
L
H
H
H
L
H
H
L
H
H
H
L
x
H
H
H
H
L
x
L
L
L
H
H
H
L
H
H
L
H
H
H
L
H
H
L
H
H
H
H
x
L
L
x
L
H
L
H
H
H
H
H
L
x
x
x
H.
H
H
H
x
x x
H
H
H
H
L
x
x
L
H
H
H
L
H
H
L
H
H
H
L
H
H
L
H
H
H
L
x
H
H
H
H
L
x
x
x
H
H
H
H
H
H
L xx x
x
x
x
x
H
H
H
H
4-646
Unit Loading/Fan Out: See Section 2 tor U.L. definitions
Pin Names
Description
54F/74F
U.L.
Input �1H/l1L
HIGH/LOW Output loHlloL
ACo-ACa ARo-ARa Oo-Oa MCo, MC1
cs
MSEL LE SELo, SEL1 RASI CASI RAS0-RAS3 CAS0-CAS3 OE
Column Address Row Address Address Outputs Memory Cycle Chip Select Input Multiplexer Select Input Latch Enable Input Select Inputs Row Address Strobe In Column Address Strobe In Row Address Stobe Outputs Column Address Strobe Outputs Output Enable
1.0/1.0 1.0/1.0 50/33.3 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.011.0 50/33.3 50/33.3 1.0/1.0
20 �A/ - 0.6 mA 20 �A/-0.6 mA -1 mA/20 mA 20 �A/ - 0.6 mA 20 �A/-0.6 mA 20 �A/ - 0.6 mA 20 �A/-0.6 mA 20 �A/ - 0.6 mA 20 �A/ - 0.6 mA 20 �A/ - 0.6 mA -1 mA/20 mA -1 mA/20mA 20 �A/-0.6 mA
Block Diagram
LE
SELo
ADDRESS ACo-ACa
ADDRESS ARo-ARa
cN o e'"nTl
Q)
MSEL CS
~ {BANK)
LATCH
Ci 2
j
~ (MSB)
LATCH
a
l
_'j LATCH
r--+I (LSB)
Ci
l
rt-'"
~
I
CL
'\J
BANK COUNTER
Ci
1f
tCNTRo,1
0
c
f
I
CL COLUMN COUNTER
Ci
1
I
RAS CODE
r-
CAS CODE
J 1I ~
MC1MCo
'"7..
I
)
()
~
-
CASI
_r'"7_ I 4)
~
~
l
CL
\
ROW COUNTER
a
l
MUX CONTROL
1~~' _'j
~~.._
So-S3
~
MUX
l
~
n ~ On OE
4-647
TL/F/9608-3
CIO
CD
LL O>
Timing Waveforms
N
X. .X. XX* *>0000000<>< Qn _____________ ~ ~ow ADDRESS VALID
COLUMN ADDRESS VAi.DC::
RASI
RASn
I
LE
MSEL
CASI
CASn
____ SELn
,,
\\
----------------------RAM-SElM/-COAR-SYI-CPYU-CLLSE-ET-WIMIDI-NTGH-S ---------------------
RAS I/CASI
FIGURE 1. Dynamic Memory Controller Timing
TL/F/9608-4
ARn,Acn:::::)E_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~
MSEL
CASI
CASn
Note A: Guaranteed maximum difference between fastest RASI to RASn delay and the slowest An to On delay on any single device. Note B: Guaranteed maximum difference between fastest MSEL to On delay and the slowest RASI to RASn delay on any single device. Note C: Guaranteed maximum difference between fastest CASI to CASn delay and the slowest MSEL to On delay on any single device.
FIGURE 2. Specifications Applicable to Memory Cycle Timing (MCn = 1,0)
4-648
TL/F/9608-5
Timing Waveforms (Continued)
- ARn,ACn --1I (
On
XX'XJv - ROW RErRESH ADDRESS r-~j
l-T1-
RASI
:I
~
1----tRAH-
~
MSEL
T2
_}
T3
i
CASI
I-
~
CASn
COLUMN REFRESH ADDRESS tASC
Refresh Cycle Timing
FIGURE 3. Desired System Timing
TL/F/9608-6
Mcn:::::){-----------------------------------------------------------------
MSEL
CASI
CASn
FIGURE 4. Specifications Applicable to Refresh Cycle Timing (MC0 = 00,01)
Note B: Guaranteed maximum difference between fastest MSEL to On delay and the slowest RASI to RASn delay on any single device. Note C: Guaranteed maximum difference between fastest CASI to CASn delay and the slowest MSEL to On delay on any single device. Note D: Guaranteed maximum difference between fastest RASI to RASn delay and the slowest MCn to On delay on any single device.
TL/F/9608-7
4�649
uccoo.
O>
Refresh Cycle Timing (Continued)
N
MCn~-------M_c_n_=_o_1________________________________________________
RASI
t.4SEL
CASI
CASn FIGURE 5. Designed Timing-Refresh with Error Correction
TL/F /9608-8
Mcn _____....1){~__-M_c_n_=_o_o _______________________________________________
On
RASI -----------~-/-
RASn FIGURE 6. Desired Timing-Refresh without Error Correction
TL/F/9608-9
4-650
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National. Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
- 65�C to + 150�C
Ambient Temperature under Bias
- 55�C to + 125�C
Junction Temperature under Bias
- 55�C to + 175�C
Vee Pin Potential to Ground Pin
-0.5Vto +7.0V
Input Voltage (Note 2)
-0.5Vto +7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Output in HIGH State (with Vee = OV) Standard Output TRI-STATE� Output
-0.5VtoVee -0.5Vto +5.5V
Current Applied to� Output in LOW State (Max)
twice the rated loL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
.,,N
CD
Recommended Operating
C')
Conditions
OC)
Free Air Ambient Temperature Military Commercial
- 55�C to + 125�C 0�Cto +70�C
Supply Voltage Military Commercial
+ 4.5V to + 5.5V + 4.5V to + 5.5V
DC Electrical Characteristics
Symbol
Veo
VoL
lsv1
lozH lozL los leEx lzz leeH leeL leez
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee 74F5% Vee 74F5% Vee
Output LOW Voltage
54F 10% Vee 54F 10% Vee 74F 10% Vee 74F 10% Vee
Input HIGH Current
Input HIGH Current Breakdown Test
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Output HIGH Leakage Current
Bus Drainage Test
Power Supply Current
Power Supply Current
Power Supply Current
54F/74F
Min Typ Max
2.0
0.8
-1.2
2.5 2.4 2.5 2.4 2.7 2.7
0.5 0.8 0.5 0.8
20
100
-60
-0.6 50 -50
-150 250 500 300 300 300
Units
v v v
v
v
�A �A
mA
�A �A
mA
�A �A
mA mA mA
Vee
Min
Min
Min
Max Max Max Max Max Max Max
o.ov
Max Max Max
Conditions
Recognized as a HIGH Signal Recognized as a LOW Signal
loH = -1 mA loH = -3mA loH = -1 mA loH = -3mA loH = -1 mA loH = -3 mA
loL = 1.0 mA
loL = 12.0 mA loL = 1.0 mA loL = 12.0 mA V1N = 2.7V V1N = 7.0V
V1N = 0.5V VouT = 2.7V VouT = 0.5V
VouT = ov
VouT =Vee VouT = 5.25V Vo= HIGH Vo= LOW Vo= HIGHZ
4-651
uccenoo.
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
"'
Military
Commercial
29F
29F
29F
Symbol
Parameter
TA= +25�C Vee= +s.ov
CL= SO pf
TA, Vee= Mil TA, Vee= Com
CL= SO pf
CL= SO pf
TA, Vee= Com CL= 500pF
Units Fig. No.
Min Max Min Max Min Max Min Typ Max
tPLH tPHL
Propagation Delay 3.0
AR to On
3.0
11.0 11.0
2.5
12.0
2.5
12.0
19.0 22.0
ns 2-3
tPLH tPHL
Propagation Delay 3.0
AC to On
3.0
11.0 11.0
2.5
12.0
2.5
12.0
19.0 22.0
ns 2-3
lPLH tPHL
Propagation Delay 3.5
RASlto RASi
3.5
12.0 12.0
3.0
13.0
23.0
3.0
13.0
20.0
ns 2-3
tPLH
Propagation Delay 1.0
8.0
tPHL
CASltoCASi
1.0
8.0
1.0
8.5
1.0
8.5
19.0 17.0
ns 2-3
tPLH tPHL
Propagation Delay 3.0
MSEL to On
3.0
13.0 13.0
2.5
14.0
24.0
2.5
14.0
21.0
ns 2-3
tPLH tPHL
Propagation Delay 4.0
MCntOOn
4.0
15.0 15.0
3.5
16.0
3.5
16.0
25.0 22.0
ns 2-3
tpLH tPHL
Propagation Delay 3.5
MCn to RASn
3.5
17.5 17.5
3.0
18.5
3.0
18.5
24.0 22.0
ns 2-3
tPLH tPHL
Propagation Delay 4.0
MCntoCASn
4.0
12.5 12.5
3.5
13.5
3.5
13.5
23.0 21.0
ns 2-3
tPLH tPHL
Propagation Delay 4.0
LE to RASn
4.0
15.0 15.0
3.5
16.0
3.5
16.0
25.0 24.0
ns 2-3
lPLH tPHL
Propagation Delay 5.0
LEtoCASn
5.0
13.5 13.5
4.5
14.5
4.5
14.5
24.0 24.0
ns 2-3
tPLH
Propagation Delay 3.5
12.0
tPHL
LE to On
3.5
12.0
3.0
13.0
3.0
13.0
23.0 22.0
ns 2-3
4-652
AC Electrical Characteristics: See Section 2 for Waveforms and Load Configurations
Symbol
Parameter
tpzH tpzL
tpzH tpzL
tpHz tpLZ
tpzH tpzL
tpHz tpLz
tpzH tpzL tw(H) tw(L)
tskew
Output Disable Time OE to On
Output Disable Time OE to On Output Disable Time OE to RASn
Output Disable Time OE to RASn
Output Disable Time OE to CASn
Output Enable Time OEtoCASn
Pulse Width, HIGH or LOW CASn, RASn
On to CASn, RASn
29F
TA= +25�C Vee= +5.0V
CL= 50 pF
Min
Max
1.0
9.5
1.0
9.5
1.0
9.5
1.0
9.5
1.0
9.5
1.0
9.5
1.0
9.5
1.0
9.5
1.0
9.5
1.0
9.5
1.0
9.5
1.0
9.5
15.0 15.0
10.0
Military 29F
TA, Vee= Mil CL= 50 pF
Min
Max
Commercial 29F
TA, Vee= Com CL= 50 pF
Min
1.0 1.0
1.0 1.0
1.0 1.0
1.0 1.0
1.0 1.0
1.0 1.0
15.0 15.0
Max 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0
10.0
.,,I\)
<O
a> O>
Fig. Units
No.
ns
2-5
ns
2-5
ns
2-5
ns
2-5
ns
2-5
ns
2-5
ns
2-4
ns
AC Operating Requirements: See Section 2 for Waveforms
Symbol
Parameter
t5 (H) t5 (L)
th(H) th(L)
t5 (H) t5 (L)
th(H) th(L)
Setup Time, HIGH or LOW An to LE
Hold Time, HIGH or LOW An to LE
Setup Time, HIGH or LOW SEL to LE
Hold Time, HIGH or LOW SEL to LE
29F
TA= +25�C Vee= +5.0V
Min
Max
5.0 5.0
5.0 5.0
5.0 5.0
5.0 5.0
Military 29F
TA, Vee= Mil
Min
Max
Commercial 29F
TA, Vee= Com
Min
Max
5.0 5.0
5.0 5.0
5.0 5.0
5.0 5.0
Fig. Units
No.
ns
2-6
ns
2-6
ns
2-6
ns
2-6
4-653
Section 5 Ordering Information and Physical Dimensions
Section 5 Contents
Ordering Information and Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 Bookshelf Distributors
5-2
0
""I
~National
~Semiconductor
0.. CD
s�""I
-cc
5"
0
FAST� Ordering Information
-3
I�
(5"
::I
The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows:
74F ~ P
Temperature Range F a m i l y - - - - -...T ... 74F = Commercial 54F = Military 29F = Commercial or Military
Device Type _ _ _ _ _ _ _ _ _ _ _ ____,
Package Code-------------~ P = Plastic DIP
SP = Slim Plastic DIP D =Ceramic DIP
SD = Slim Ceramic DIP F = Flatpak L = Leadless Chip Carrier (LCC) Q = Plastic Chip Carrier (PCC) S = Small Outline (SOIC)
C QR
l _ Special Variations
X = Devices shipped in 13" reels QR = Commercial grade device
with burn-in QB = Military grade device with
environmental and burn-in processing
.____ _ Temperature Range
C = Commercial-JEDEC
( - 40�C to +85�C)
J = Commercial-EIAJ
(0�C to +70�C) SOIC Only
M =Military
(- 55�C to + 125�C)
For most current packaging information, contact Product Marketing.
Dim
A JEDEC
B
A EIAJ
B
Units: Inch (mm)
JEDEC-EIAJ Small Outline Package Comparison
14-Pin
16-Pin
20-Pin
Min
Max
Min
Max
Min
Max
0.228 (5.80)
0.245 (6.20)
0.228 (5.80)
0.245 (6.20)
0.393 (10.0)
0.420 (10.65)
0.149 (3.80)
0.158 (4.00)
0.149 (3.80)
0.158 (4.00)
0.291 (7.40)
0.300 (7.60)
0.300 (7.62)
0.198 (5.02)
0.350 (8.89)
0.245 (6.22)
0.300 (7.62)
0.198 (5.02)
0.350 (8.89)
0.245 (6.22)
0.300 (7.62)
0.198 (5.02)
0.350 (8.89)
0.245 (6.22)
DOI f A ! TL/F/9790-2
24-Pin
Min
Max
0.393 (10.0)
0.420 (10.65)
0.291 (7.40)
0.300 (7.60)
0.300 (7.62)
0.350 (8.89)
0.198 (5.02)
0.245 (6.22)
5-3
ctn
�0u;
c
Cl)
c E
D~NaStemiicoonnduactlor
All dimensions are in incnes (millimeters)
m
�(u); .>c-
52 Lead Side-Brazed Dual In-Line Package (D) NS Package Number D52A
i.-~~~~~~~~~~~~~~-,::;:,~~~~~~~~~~~~~~~-+-1
D.
MAX
~ ~ ~ d d ~ d U 84 Q ~ ~ 40 H H V H ~ ~ H H ~ ~ H H n
I 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 28
~(130..54072)~
0.125~
I
MAX
I
i " MIN '(21 .714-5.080)iio.r . u-�.m�~~
I : I I -""""'~ ~
~j t~
0.035-0.055
.
(2.540:0.254)
(0.889-1.397)
SEATINGl'LANE
TYP
TYP
0.015-0.023
(O.Hl-0.584)
TYP
15"MAX AUOWABLE
20 Terminal Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
I --i8.0i.93500��o0.T00o83i--
D I
Top View
Side View
_/"< -1 0.015
0.200�0.005 ~
TYJP
~45'x (:~;:!::;:,
~~Na~~~
~ ~~ f _,,~...............V--.!
:=:::::,
R TYP
,::T:Y:L=:,:::~~~,~r=�::-:.:.,.-. ......1..,...IG-----,t_,:::~=:::~,
TYP
TYP
45'x~ (1.016�0.254) 3PLCS
Bottom View
0.003
~
(0076)--i
_r-(0.381)
+ MINTYP~MAXTYP
(0.0022 .559)! y-T~
MAXTYP
(0.152)
MINTYP
Detail A
5-4
28 Terminal Ceramic Leadless Chip Carrier {L) NS Package Number E28A
r- 0.065-0.076 (1.651-1.930)
TOP VIEW
BOTTOM VIEW
SIDE VIEW
E28A(AEVC)
14 Lead Ceramic Dual In-Line Package {D) NS Package Number J14A
0.025
(0.635)
RAD
0.785 (19.9391-----1
MAX
t 0.220-0.310 (5.588-7.874)
............_~-.-.--.-.-,~_J
0.060 �0.005
0.200 (5.080)
- - - - � � - - - - - - - - - - M - + - A X 0.020-0.060 (0.508-1.524)
0.008-0.012 (0.203-0.305)
0.098 (2.489) MAX BOTH ENDS
--11- 0.018 �0.003
0.125-0.200
L(0.457 �0.076) 0.100 �0.010 (2.540 �0.254)
(3.175-5.080) 0.150 (3.81)
MIN
J14A(REVG)
5-5
cen
0
"iii
16 Lead Ceramic Dual In-Line Package (D)
ccu NS Package Number J1GA
E
i5
(ij
(.)
-~
0.025
a.c..
(0.635) RAO
J16A (REV K)
18 Lead Ceramic Dual In-Line Package (D) NS Package Number J18A
0.020 (0.5081 RAD MAX
0.915 ------(23.24) MAX
�1_
~~~~~t
0.310 (7.874) MAX
-,..........,.....,._..,..,._,...,,..,.......~-LJ
J!:!!!!!.MIN-(0.127)
0.037 � 0.005 '(0.940�0.127)
L LjJyp 0.100�0.010 (2.540 � 0.254) 0.018� 0.003 TYP (0.457 �0.076)
0.098
(2.489) MAX
BOTH ENDS
0.150 (3.810)
MIN
J18A(REVL)
5-6
20 Lead Ceramic Dual In-Line Package (D) NS Package Number J20A
0.985
-------(25.019) ------.i
MAX
0.180
(4.572) MAX
GLASS SEALANT
0.008-0.012 (0.203-0.305)
0.055�0.005 (1.397�0.127)
0.100�0.010 (2.540�0.254)
0.018�0.ooa ~IL 10.457�0.016)11
0.200 (5.080) MAX
0.125-0.200 (3.175- 5.080)
t
J20A(REVM)
24 Lead Ceramic Dual In-Line Package (D) NS Package Number J24A
1.290
~------- (32.766)--------1
0.600
MAX
i~t::)
0.025
(0.635)
RAD
,,,. .rJ6) 0.514-0.526
0.030-0.055
(0.762-1.397) RAD TVP
I- I 0.100 t0.010
--l (2.540 I 0.254)
I I' - 0.018 �0.003 86'
1-- - - 1 (0.457 �0.076) 94
TYP
0.125-0.200 (3.175-5.080)
MIN
0.150
(3.810) MIN
J24A(REVHI
5-7
24 Lead Slim (0.300" Wide) Ceramic Dual In-Line Package {SD) NS Package Number J24F
0.025 (D.635) RAD
1
-
-
-
-
-
-
-
- 1.290 132.77)
MAX
0.295 (7.493)MAX
0.060 �0.005 (1.524 �0.127) TYP
J24F(REVG)
28 Lead Ceramic Dual In-Line Package {D) NS Package Number J28A
....... _1~10~~2~~) 1.490
t - - - - - - - - - ( 3 7 . 8 4 6 ) MAX
_..
� . . . _. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAX GLASS
0.025
(0.635) RAD
0.514-0.526
0.030-0.055
(0.762-1.397) RAD TYP 0.180
,,
0.060-0.100 (1.524-2.540)
~ 11 0.100 �0.010 (2.540 '0.254)
0.225
(5.715)
~~�020-0.010
~0.501-1.7111
~h 0.018 � 0.002 (0.457 ;0.508)
0.125
(3.175) MIN
J28A tREVEt
5-8
14 Lead Small Outline Integrated Circuit (S) NS Package Number M14A
/-(~~~~=~:~;:)-,
14 13 12 11 10 9 8
-J . . , _ . I- . . . - . . . . . . . . - - - .
0.228-0.244
(5.791-6.198)
('�'\
~3y 0� p
LEAD
N0.1 IOENT
,,,..-JJ!~....u -...--.,. -,. ~~1 2
.
-.
.,.-.-...--.
.,---.
,-..----,.,---.
,.-.,..-1-1 c::__yl _
1------i-
~ f_
~MAX (0.254)
~ r ~45 (0.254-0.508) x
0.150-0.157 (3.810-3.988) -
80 MAX TYP
l__JJ r---.:) i1i ALL rDS
- rI _jJ l t 0.008-C:-.
(0.203-0.254)
0.016-0.050
TYP ALL LEADS
0.004
j0:102j'
(0.406-1.270) TYP ALL LEADS
ALL LEAD TIPS
0.053-0.069 (1.346 -1. 753)
SEATING PLANE
t
t f0.014
(0.356)
TM
JL. - .
~J I
(1.270)
-
0.004-0.010
. t (0.102-0.254)
_j l:J-0.020 TYP (0.356-0.508)
TYP
~TYP
(0.203)
M14AjREV H)
14 Lead Small Outline Package - EIAJ (SJ) NS Package Number M14D
.� o�-��
t-J L0018-0031 (0.406- 0.787) DETAILF
~,~:.::=:o~:,~
I ~,,,, ,,~
0.295-0.319
""[}o
0.205-0.213
CT
1
SEEDETAILF
0.071
0.067 - 0.083
(1.803) REF
(1.702-2.108)
~ L~ _J ~(~:~~)J L t I~(1.I204.054)9REF
+
SEATINGPLANE 0.000-0.010
0.014-0.020
(0.000- 0.254)
(0.356 - 0.508)
M140(REVA)
5-9
ctn -~ 16 Lead Small Outline Integrated Circuit (S)
5j NS Package Number M16A
c E
(ij
�(u,;) .a>c.-
r ~ 45~ 'r~:!~~=~:!!~,
(0.254 -0.508) x
8� MAX TYP
L . cJf
ALL LEADS
)\1i +
o.oo8C ~J L~o.050
(0.203-0.254)
I
-
(0.406-1.270)
TYP AU LEADS
0.004
TYP ALL LEADS
(0.102)
ALL LEAD TIPS
LEAD N0.1 IDENT
0.053-0.069 (1.346-1.753)
+ t
t oL (0.356)
0.004 -0.010
(0.102-0.254)
ha� �t=tAF1FiJ_J SEATING
J L J L o.o5oJL
o.01L.::P
(1.270)
(0.356-0.508)
TYP
~TYP
(0.203)
Ml6A (REV HI
f,,,, ,.... 16 Lead (0.300" Wide) Small Outline Integrated Circuit (S)
NS Package Number M16B
~I ,:.'::=:��~.-1
0.394-0.419
. . y:.::.:---K)~~~~9?99~~~~~
a---i~MAX (0.254)
0.093-0.104
~
t
t~�~� SEATING
(~:~:, I I ~ JLJL PLANE
0.004-0.012 0.014-0.020 TYP
-
- (1.270)
(0.356-0.508)
TYP
0.008 TYP
(0.203)
M166(REV El
5-10
16 Lead Small Outline Package - EIAJ (SJ) NS Package Number M16D
tJ-Lk,.._.., (0.406- 0.787) DETAILF
SEE DETAILF
~REF
0.067 - 0.083
(1.803)
L
(1.702 - 2.108)
t
r~ JL _J l-(~:~~,
t SEATINGPLANE
0.000-0.010
0.014-0.020
(0.000-0.254l
(0.356 - 0.508)
M16D(AEVA)
20 Lead Small Outline Integrated Circuit (S)
NS Package Number M20B
0.496-0.512
r1 l� ~ 112.598-13.005) 19 18 17 16 15 14 13 12 11
0.394-0.419
110.DD8-10.ti43J
'"",::.;-C------------~
t (~:~::=~:::,J D.01D-D.D29
(D.254-0.737)
x
45 �
:�:.8� MAXTYP
.J:~lll2'..2::=,=~:~=o:=.=/=:::::;:=~~I
(0.229-0.330) TYP ALL LEADS
All LEAD TIPS
-
,._(0.4D6-1.27D)
TYP ALL LEADS
1 2 3
9 10-r .!:!!!!MAX (0.254)
0.093-0.104
(2.362 -2.642)
� Ej~rnc~ ::::=__J L
t _I JL _J J_ (~h 1-~
0.004-0.012 (0.102-0.305)
SEATING
o.D1!-o.:NTEYP
.
(1.270)
(D.356 -0.508)
TYP
J!J!!!!TYP
(D.2D3J
M20B(AEVF)
5-11
cU)
�u0; 20 Lead Small Outline Package - EIAJ (SJ)
c
Cl)
NS Package Number M20D
c E
ca
�u(.;)
.>c-
t-IE Q. J L.. _.~,
10.40& - o.1sn
DETAILF
SEEDETAILF
0.071 REF
0.067 -0.083
L(1.803)
(1.702-2.108)
i
~ J _J l-(~:~~~)
L~t SEATINGPLANE
(0.000 - 0.254)
0.014-0.020
(0.356- 0.508)
M200(REVA)
24 Lead Small Outline Integrated Circuit (S)
NS Package Number M24B
-----11 ------- (01.55.9164--015.6.5142) 22 21 20 19 18 17 16 15 14 13
5 6 7 8 9 10 11 12
~ 0.291-0.299 -~
0.037-0.044
0.009-0.013 (0.229-0.330)
0.011-1 (0.432) x45�
t(0.940-1.118)
TYP ALL LEADS
0' -8� TYP ALL LEADS
.L J -_t-t=~=~=~\:::::!Q:~+,
0.093-0.104 (2.362-2.642)
t
t J
(0.102) ALL LEAD TIPS
TYP ALL LEADS
L~ (1.270)
5-12
0.004-0.012 ~0.305)
Jl_o.oLo.019 (0.356-0.483) TYP
28 Lead Small Outline Integrated Circuit (S) *NS Package Number M28B
INDEX AREA
10.65 (0.420) 10.00 (0.393)
l
I
18.10 (0.713)
17.70 (0.696)
0.75 (0.030) x450 0.25 (0.009)
(0.01~3~ -i~tr r;-::::;::===:;::== 0.32
_[_ 0.23 (0.009)
l
~
2.65 (0.105) 2.35 (0.092)
1.27 (0.050) BSC
0.49 (0.020) 0.35 (0.013)
'J~~:
1.27 (0.050) 0.40 (0.015)
-c--- 0.30 (0.012) 0.10 (0.003) M28B
*For most current package information contact product marketing.
14 Lead Plastic Dual In-Line Package (P) NS Package Number N14A
~ 0.250�0.010 (6.350 �0.254)
~~;::;:::;::::~~~~~
~DIA ~MAX (2.337) (0. 762) DEPTH
OPTION 1
0.135�0.005 (3.429�0.127)
,~:~~~)+
-11 MIN 0.125-I0.150
(3.175-3.810)
0.014-0.023 TYP- (0.356-0.584)
~T I __1
'�4' TYP 0.075 �0.015
---(1.905�0.381)
-
I
1.
0.100�0.010 _ (2.540 �0.254)
TYP
-,~:~~~=~:~~~) TYP
5-13
OPTION 02
0.300-0.320
~I
liE3I= IJ;:!s� -ii~ 0L-D.Dl6 TYP (0.203-0.406) L0.280 (7.112)_. MIN
0.325~~::
(8.255
+1.016) -0.381
N14A.(REVFI
c 0
�~ 16 Lead Plastic Dual In-Line Package (P)
~ NS Package Number N16E
E
i:S
ca
�uu;
AREA
�.�.....������:..
.>ca
D.
I N D E X. �. � �.:�. �. �.�: l��.:� 1�: �.�.�::15.�.::.�: �:� � � :� ��:� � � :� �� �.:� �:�:��:. ��:.:��.
PIN NO. 1 IDENT
PIN N0.1 IDENT
-�-�-���1 2
0.130t0.005 (3.302t 0.127)
0.145 - 0.200
(3.683- 5.080)
i= o.o1o MIJ
0 508 <� >
o.t25-o.15~L
(3.175-3.810)
OPTION 01
I- 0.030t0.015
' (0.762t0.381)
OPTION 02
0.065
I 0.300-0.320 ~ (1.620-8.128) I
t(1.651)
---r
1.~.1 I- 0.280 -l
0.008-0.016 TYP (0.203- 0.406)
0.014- 0.023
(0.356- 0.584) TYP
I 0.100t0.010 14- (2.540t0.254)
TYP
(0.325 ~8:8tg
(8.255+-01..308lS1 )
N16E (REV F)
18 Lead Plastic Dual In-Line Package (P)
NS Package Number N 1BA
~x~
(2.336) (0.762) NOM MAX DEEP (2 PLCS)
-:-:j 0.843-0.870
(21.41-22.10)
15 14 13 12 11 D
f
0.2SO �0.005
~ I (70.1.122)80j MIN
300-0.320 . 620-8.12~
(6.3SO �0.127)
t;;T=i:;;;:::;:;;:;::::;;;:;;::::::;:;:;:::::;::;;;::;:;;;::;:;;;=:;:;;:I _ i
0.040
!1 ?\
I� �I 0.32S ~:~~~
f~ uss
+1.016) -D.381
11-- J 1i.:-1-' 0.025 �0.015
(0.63S �0.381)
0.018 �0.003
j-- (0.457 �0.076)
0.100 �D.-010
(2.540 �0.2S4) TYP
0.14S-0.200
iJ.6i3:s:OeOi
N18A(REVE)
5-14
:":'trJ
20 Lead Plastic Dual In-Line Package (P) NS Package Number N20B
'ce<n;� e!.
3c �
0.092 x 0.030
(2.337 x 0.762) MAX DP
-,
C'D
0 . 0 3 2 � 0 . 0 0 S V1O 9 (0.813�0.127)
se:nJ�
RAD 0.240-0.260
e:nJ
(6.096-6.604)
PIN NO. 1 IDENT~
~::;:::r::;:;:;::;=:::;::r;:;::;=:=;:~~~~__j_
OPTION 2
N20B(REVA)
24 Lead Plastic Dual In-Line Package (P)
NS Package Number N24A
-------.11 - - - - - -(311.2.4537--13.222760)
�
13
0.062 (1.575)
RAD
PIN NO. 1 IDENT
95��5�
0.625 ~:~~~
f--- )---J (15.875 -+-00..358315
0.009-0.015 ~
(0.229-0.381)
0.075 �0.015 (1.905 �0.381)
1--
5-15
N2U(AEVE)
cfl)
�c0;; 24 Lead Slim (0.300" Wide) Plastic Dual In-Line Package (SP)
c
Q)
NS Package Number N24C
c E
n;
0.092 (2.337)
1.243-1.270
(31.57-32.26) MAX
�c(.;);
(2 PLS)
.a>c . -
PIN N0.1 IDENT
f
D.260�0.005 (6.604�0.127)
~
0.300-0.320
I,,~~~"" I
OPTION 2
0.062
(1.575) RAD
0.325 ~~:~~~
1~8.
255
+1.016) -0.381
95��5�
0.280 (7.112)
MIN
-r-J0.065
(1.651)
0.015 �0.015 (1.905�0.381)
If-
0.040 (1.016)
TYP
0.130�0.005 (3.302�0.127)
t (0O�M0~2~08l
0.145-0.200 (3.683-5.080)
... ___-+- 0.125-0.145
. (3.175-3.556) MIN
N24CiAEV Fi
28 Lead Plastic Dual In-Line Package (P) NS Package Number N28B
""ftrc~-. 0.03iiMAX
0.600-0.620 _ _ ,
I
r
0.510�0.005
(12.95� rm .J,!; r;: : :;: : ; ; ; : ;:=;: ;: r;: :;:;:; ;:;: ;: :; : ; =;: :;: ;: :;: ~:;:;:; :r=;: : ;: : ;: :rl
1
PIN NO. 1 IDENT
1i......------,!5~:=!&~~~)------~
�~TYP
(1.270)
(0.15840 .73)MIN~
0.625 -+00..001255
(15.88 ~~:~~)
0.125-0.145 (3.175 -3.683)
N28B(AEVE)
5-16
20 Lead Plastic Chip Carrier {Q) NS Package Number V20A
I 18
0.080 (2.032)
'--.,..__.........,.J...-+--'- Po~~E~~:L
b..___... ___._ .....
4 SPACES AT 0.050
.113
iLl7oi
.;1 0.226 (5.740) NOM SOU ARE
0.310-0.330
(7.874-8.382) (CONTACT DIMENSION)
(T0.i4.3i0 4 5 i r
x45'
=P 15' VIEW A�A
____ ...._ 0.385-0.395
(9.779-10.03) SQUARE
28 Lead Plastic Chip Carrier {Q) NS Package Number V28A
V20A1AEVJ)
0.326
22 (8.280) NOM SQUARE
(C0~::~~~1~0N) ~
(0.813-1.016)
0.020
(o:5U8
MIN
i~Ert=~l--t -I f (0.127-0.381)
1=-1
[
I ~
0.013-0 018 (0.330-0.457)
TYP
~ 0.165-0.180
5
'
ft
t ~ ~
C jl0.450
(0.660n:�a13)
(2.642-2.997)
iiUii
REF SQ
0.485-0.495
(12.32-12.57) SQUARE
5-17
_J!iVIEWA�A
(1.143) x45�
V28A(REVGI
cU)
0 'Ci)
52 Lead Plastic Chip Carrier (Q)
c
G>
NS Package Number V52A
E
i5
m
(,)
'Ci)
12SPACES AT
I ~-1 r--0.050=0.600 '
0.026-0.032 ~
.>c-
33
21
TYP
Q.
0.165-0.180
~
68 Lead Plastic Chip Carrier (Q) NS Package Number V68A
r
0.826
(20.98) NOM
L 43 I�
-101
Q (8.382) DIA NOM PEDESTAL
0.050=0.800 (1.270 = 20.32) 16 SPACES AT
�~(1.270) REF
_j_
-26
0.826
..27,
(20.98)
NOM
0.950
i24.13i
REF SQ
0.985-0.995
(25.02-25.27) SQUARE
V68AIREVG)
5-18
14 Lead Ceramic Flatpak (F) NS Package Number W148
0.026-0.035 (0.660-0.889)
TYP
0.055-0.080 ( 1.397-2.032)
~
0 370-0 385 (9:398-9:779)
-
0.050 t 0.005 (1.270 t0.127)
l
11-~MIN TYP
TYP
1
0.250-0.370
j
,,or,..) ..1.4...1.3.1..j1..2....1..1.1.0...9......8... ,��
J L 0.004-0.006
(0.102-0.152) TYP
I.GL.A_s_s-1~-�r--- .,.1...,~�.�77) <10..218102>
MAX
D
......2.....,3..,4,.....5....,.6
0.245-0.255
SEE;~).
DETAIL A
PIIDNEN#T1
J L .0.015-0.019 ""
(0.381-0.483) TYP
l0.250-0.370
(6.350-9.398)
~ ~(~:~!~)MAX TYP
1 0.008-0012 ( 0.203-0.305) DETAIL A
W1'8 (REV H)
16 Lead Ceramic Flatpak (F) NS Package Number W1 SA
I I 0.050-0.080 ~ ~
(1.210-2.oa21
II 0.004-0.006 TYP-fj
10.102-0.1521
0.007-0.018 (0.178-0.457)
TYP
1-~ '~I I-
0.050�0.005 (1.270�0.127)
TYP
71.._o.ooo MIN TYP
0.026-0.040 TYP (0.660-1.016)
0.25010.370
(6.350-9.398)
I
+ "1""6"'1..5..1..4'""1"3".1..2...1..1...1..0.....9...~~'r
0.300 (7.620)
~
0.245~0.275
(6.223-6.985)
MAX GLASS
I
r _i --, 2 3 4 5 6 7 8
'
DETAILA--.1~1Jj
PIN NO. 1 IDENT
0.250-0.370
(6.350-9.398)
-..JII -* ~ 0.015-0.019 (0.381 - 0.482)
TYP
W16A !REV HI
1-
0.008-0.012 ~1 .-(0.203-0.305)
DETAIL A
5-19
"c '
�c0;; 20 Lead Ceramic Flatpak (F)
c
Q)
NS Package Number W20A
E
i5
cu
�c(,;); .>c-
0.060-0 090
0 540
(1.524-2:286) I - - (13.72) MAX-
0.030-0.040 TYP (0.162-1.016)
I I
-(01..025100:Jt~0�.102015)
1 1 T ~
1-{OQ.010257) MIN TYP
D.
0.250-0.320
(6.350-8.128)
-t ~ ,
0 285
L (7.�239)
,. 1918 17161514 13 12 11
D
(06.266004--06.287508)
l'j~ -t. .(g:::~:;)j MAX
2 3 4 S 6 7 8 9 10
D~~~LS#EE~//Jf/1'
IDENT
- l l j L j 0.004-0.006 TYP
0.015-0.019 TYP
(0.102-0.152)
{0.381-0.483)
0 250-0.320
l(6:350-8.128)
i - 0.045 MAX TYP (1.143)
DETAIL A
W20A (REV D)
24 Lead Ceramic Flatpak (F)
NS Package Number W24C
r-l (02..008302--02.~029:0:~�0.005 I... I 1~14.09.599-01-50..68285)
0.030-0.040 (0.762-1.016)
rr
(1.270�0.127)
-1~0005 MIN TYP
(0.127)
r
0.250-0.320
.....,~��"" .............................................................................
~ 24 23 22 21 20 19 18 17 16 15 14 13
t
o.4oo
I
l(10.16)
MAX GLASS 0.011-0.025
t"\
j.1
0.365-0.380
_ l(9.271-9.652)
(0.2791-0.635)
;:_ 2 3 4 s 6 1 8 9 10 11 12
J;(~ t 0'11DNAL/; PIN # 1 IDENT (REFER DEOTPATIILON"A#"1)
.J::~:)
(6.3501-
j
(~:~~~=~:~~:) - II._
- -, (~:~!~=~:~!~) TYP
~(~:~:~)MAX
(' "Fr 0.011-0.025
~ __ 1
0.008-0.015 (0.203-0.381)
DETAIL "A" PIN # 1 IDENT OPTION 2
- (~:~~~=~:~!~)
Wl4CtREV DI
5-20
NOTES
~National
~Semiconductor
Bookshelf of Technical Support Information
National Semiconductor Corporation recognizes the need to keep you informed about the availability of current technical literature. This bookshelf is a compilation of books that are currently available. The listing that follows shows the publication year and section contents for each book. Please contact your local National sales office for possible complimentary copies. A listing of sales offices follows this bookshelf. We are interested in your comments on our technical literature and your suggestions for improvement. Please send them to:
Technical Communications Dept. M/S 16-300 2900 Semiconductor Drive P.O. Box 58090 Santa Clara, CA 95052-8090
ALS/AS LOGIC DATABOOK-1990
Introduction to Advanced Bipolar Logic � Advanced Low Power Schottky �Advanced Schottky
ASIC DESIGN MANUAL/GATE ARRAYS & STANDARD CELLS-1987
SSl/MSI Functions� Peripheral Functions� LSI/VLSI Functions� Design Guidelines� Packaging
CMOS LOGIC DATABOOK-1988
CMOS AC Switching Test Circuits and Timing Waveforms� CMOS Application Notes� MM54HC/MM74HC MM54HCT/MM74HCT � CD4XXX � MM54CXXX/MM74CXXX �Surface Mount
DATA ACQUISITION LINEAR DEVICES-1989
Active Filters � Analog Switches/Multiplexers � Analog-to-Digital Converters � Digital-to-Analog Converters Sample and Hold� Temperature Sensors� Voltage Regulators� Surface Mount
DATA COMMUNICATION/LAN/UART DATABOOK-1990
LAN IEEE 802.3 � High Speed Serial/IBM Data Communications� ISDN Components� UARTs Modems� Transmission Line Drivers/Receivers
DISCRETE SEMICONDUCTOR PRODUCTS DATABOOK-1989
Selection Guide and Cross Reference Guides � Diodes � Bipolar NPN Transistors Bipolar PNP Transistors � JFET Transistors� Surface Mount Products � Pro-Electron Series Consumer Series � Power Components � Transistor Datasheets � Process Characteristics
DRAM MANAGEMENT HANDBOOK-1989
Dynamic Memory Control � Error Detection and Correction � Microprocessor Applications for the DP8408A/09A/17/18/19/28/29 �Microprocessor Applications for the DP8420A/21A/22A Microprocessor Applications for the NS32CG821
EMBEDDED SYSTEM PROCESSOR DATABOOK-1989
Embedded System Processor Overview � Central Processing Units � Slave Processors� Peripherals Development Systems and Software Tools
F100K ECL LOGIC DATABOOK & DESIGN GUIDE-1990
Family Overview� 300 Series (Low-Power) Datasheets � 100 Series Datasheets � 11 C Datasheets ECL BiCMOS SAAM, ECL PAL, and ECL ASIC Datasheets � Design Guide� Circuit Basics� Logic Design Transmission Line Concepts � System Considerations � Power Distribution and Thermal Considerations Testing Techniques� Quality Assurance and Reliability� Application Notes
FACTTM ADVANCED CMOS LOGIC DATABOOK-1990
Description and Family Characteristics � Ratings, Specifications and Waveforms Design Considerations� 54AC/74ACXXX � 54ACT/74ACTXXX �Quiet Series: 54ACQ/74ACQXXX Quiet Series: 54ACTQ/74ACTQXXX � 54FCT/74FCTXXX � FCTA: 54FCTXXXA/74FCTXXXA
FAST� ADVANCED SCHOTTKY TTL LOGIC DATABOOK-1990
Circuit Characteristics� Ratings, Specifications and Waveforms� Design Considerations� 54F/74FXXX
FAST� APPLICATIONS HANDBOOK-1990
Reprint of 1987 Fairchild FAST Applications Handbook Contains application information on the FAST family: Introduction� Multiplexers� Decoders� Encoders Operators� FIFOs �Counters� TIL Small Scale Integration� Line Driving and System Design FAST Characteristics and Testing� Packaging Characteristics
GENERAL PURPOSE LINEAR DEVICES DATABOOK-1989
Continuous Voltage Regulators � Switching Voltage Regulators � Operational Amplifiers � Buffers � Voltage Comparators Instrumentation Amplifiers � Surface Mount
GRAPHICS HANDBOOK-1989
Advanced Graphics Chipset � DP8500 Development Tools� Application Notes
INTERFACE DATABOOK-1990
Transmission Line Drivers/Receivers � Bus Transceivers � Peripheral Power Drivers � Display Drivers Memory Support � Microprocessor Support � Level Translators and Buffers � Frequency Synthesis � Hi-Rel Interface
LINEAR APPLICATIONS HANDBOOK-1986
The purpose of this handbook is to provide a fully indexed and cross-referenced collection of linear integrated circuit applications using both monolithic and hybrid circuits from National Semiconductor. Individual application notes are normally written to explain the operation and use of one particular device or to detail various methods of accomplishing a given function. The organization of this handbook takes advantage of this innate coherence by keeping each application note intact, arranging them in numerical order, and providing a detailed Subject Index.
LS/S/TTL DATABOOK-1989
Contains former Fairchild Products Introduction to Bipolar Logic� Low Power Schottky� Schottky� TIL � TIL-Low Power
MASS STORAGE HANDBOOK-1989
Rigid Disk Pulse Detectors� Rigid Disk Data Separators/Synchronizers and ENDECs Rigid Disk Data Controller� SCSI Bus Interface Circuits� Floppy Disk Controllers� Disk Drive Interface Circuits Rigid Disk Preamplifiers and Servo Control Circuits� Rigid Disk Microcontroller Circuits� Disk Interface Design Guide
MEMORY DATABOOK-1990
PROMs, EPROMs, EEPROMs � TIL 110 SRAMs � ECL 1/0 SRAMs
MICROCONTROLLER DATABOOK-1989
COP400 Family� COP800 Family� COPS Applications� HPC Family� HPC Applications MICROWIRE and MICROWIRE/PLUS Peripherals� Microcontroller Development Tools
MICROPROCESSOR DATABOOK-1989
Series 32000 Overview � Central Processing Units � Slave Processors � Peripherals Development Systems and Software Tools� Application Notes� NSC800 Family
PROGRAMMABLE LOGIC DATABOOK & DESIGN MANUAL-1990
Product Line Overview� Datasheets � Designing with PLDs � PLO Design Methodology� PLO Design Development Tools Fabrication of Programmable Logic � Application Examples
REAL TIME CLOCK HANDBOOK-1989
Real Time Clocks and Timer Clock Peripherals � Application Notes
RELIABILITY HANDBOOK-1986
Reliability and the Die� Internal Construction� Finished Package� MIL-STD-883 � MIL-M-38510 The Specification Development Process� Reliability and the Hybrid Device� VLSl/VHSIC Devices Radiation Environment � Electrostatic Discharge � Discrete Device � Standardization Quality Assurance and Reliability Engineering � Reliability and Documentation � Commercial Grade Device European Reliability Programs � Reliability and the Cost of Semiconductor Ownership Reliability Testing at National Semiconductor� The Total Military/Aerospace Standardization Program 8838/RETSTM Products� MILS/RETSTM Products� 883/RETSTM Hybrids� MIL-M-38510 Class B Products Radiation Hardened Technology� Wafer Fabrication� Semiconductor Assembly and Packaging Semiconductor Packages� Glossary of Terms� Key Government Agencies� AN/ Numbers and Acronyms Bibliography� MIL-M-38510 and DESC Drawing Cross Listing
SPECIAL PURPOSE LINEAR DEVICES DATABOOK-1989
Audio Circuits� Radio Circuits � Video Circuits � Motion Control Circuits � Special Function Circuits Surface Mount
TELECOMMUNICATIONS-1990
Line Card Components� Integrated Services Digital Network Components� Analog Telephone Components Application Notes
NATIONAL SEMICONDUCTOR CORPORATION DISTRIBUTORS
ALABAMA Huntsville Arrow Electronics (205) 837-6955 Bell Industries (205) 837-1074 Hamilton/Avnet (205) 837-7210 Pioneer Technology (205) 837-9300 Time Electronics (205) 721-1133
ARIZONA Chandler Hamilton/Avnet (602) 231-5100 Phoenix Arrow Electronics (602) 437-0750 Tempe Anthem Electronics (602) 966-6600 Bell Industries (602) 966-7800 Time Electronics (602) 967-2000
CALIFORNIA Agora Hills Bell Industries (818) 706-2608 Zeus Components (818) 889-3838 Anaheim Time Electronics (714) 934-0911 Chatsworth Anthem Electronics (818) 700-1000 Arrow Electronics (818) 701-7500 Hamilton Electro Sales (818) 700-6500 Time Electronics (818) 998-7200 Costa Mesa Avnet Electronics (714) 754-6050 Hamilton Electro Sales (714) 641-4159 Cypress Bell Industries (714) 895-7801 Gardena Bell Industries (213) 515-1800 Hamilton/ Avnet (213) 217-6751 Irvine Anthem Electronics (714) 768-4444 Ontario Hamilton/Avnet (714) 989-4602 Rocklin Anthem Electronics (916) 624-9744 Bell Industries (916) 652-0414 Sacramento Hamilton/Avnet (916) 925-2216 San Diego Anthem Electronics (619) 453-9005 Arrow Electronics (619) 565-4800 Hamilton/Avnet (619) 571-7510 Time Electronics (619) 586-1331
San Jose Anthem Electronics (408) 453-1200 Pioneer Technology (408) 954-9100 Zeus Components (408) 629-4789
Sunnyvale Arrow Electronics (408) 745-6600 Bell Industries (408) 734-8570 Hamilton/ Avnet (408) 743-3355 Time Electronics (408) 734-9888
Thousand Oaks Bell Industries (805) 499-6821
Torrance Time Electronics (213) 320-0880
Tustin Arrow Electronics (714) 838-5422
Yorba Linda Zeus Components (714) 921-9000
COLORADO Englewood Anthem Electronics (303) 790-4500 Arrow Electronics (303) 790-4444 Hamilton/Avnet (303) 799-7800
CONNECTICUT Cheshire Time Electronics (203) 271-3200 Danbury Hamilton/Avnet (203) 797-2800 Norwalk Pioneer Standard (203) 853-1515 Wallingford Arrow Electronics (203) 265-7741 Waterbury Anthem Electronics (203) 575-1575
FLORIDA Altamonte Springs Bell Industries (407) 339-0078 Pioneer Technology (407) 834-9090 Clearwater Pioneer Technology (813) 536-0445 Deerfield Beach Arrow Electronics (305) 429-8200 Bell Industries (305) 421-1997 Pioneer Technology (305) 428-8877 Fort Lauderdale Hamilton/Avnet (305) 971-2900 Time Electronics (305) 484-7778 Lake Mary Arrow Electronics (407) 333-9300 Largo Bell Industries (813) 541-4434
Orlando Time Electronics (407) 841-6565
Oviedo Zeus Components (407) 365-3000
St. Petersburg Hamilton/Avnet (813) 576-3930
Winter Park Hamilton/Avnet (407) 628-3888
GEORGIA Duluth Arrow Electronics (404) 497-1300 Norcross Bell Industries (404) 662-0923 Hamilton/Avnet (404) 447-7500 Pioneer Technology (404) 448-1711 Time Electronics (404) 448-4448
ILLINOIS Addison Pioneer Electronics (708) 437-9680 Bensenville Hamilton/Avnet (708) 860-7780 Elk Grove Village Anthem Electronics (708) 640-6066 Bell Industries (708) 640-1910 Itasca Arrow Electronics (708) 250-0500 Urbana Bell Industries (217) 328-1077 Wood Dale Time Electronics (708) 350-0610
INDIANA Carmel Hamilton/Avnet (317) 844-9333 Fort Wayne Bell Industries (219) 423-3422 Indianapolis Advent Electronics Inc. (317) 872-4910 Arrow Electronics (317) 243-9353 Bell Industries (317) 634-8200 Pioneer Standard (317) 573-0880
IOWA Cedar Rapids Advent Electronics (319) 363-0221 Arrow Electronics (319) 395-7230 Bell Industries (319) 395-0730 Hamilton/Avnet (319) 362-4757
KANSAS Lenexa Arrow Electronics (913) 541-9542 Hamilton/Avnet (913) 888-8900
MARYLAND Columbia Anthem Electronics (301) 995-6640 Arrow Electronics (301) 995-0003 Hamilton/Avnet (301) 995-3500 Time Electronics (301) 964-3090 Zeus Components (301)997-1118 Gaithersburg Pioneer Technology (301) 921-0660
MASSACHUSETTS Andover Bell Industries (508) 474-8880 Lexington Pioneer Standard (617) 861-9200 Zeus Components (617) 863-8800 Norwood Gerber Electronics (617) 769-6000 Peabody Hamilton/Avnet (508) 531-7430 Time Electronics (508) 532-6200 Wilmington Anthem Electronics (508) 657-5170 Arrow Electronics (508) 658-0900
MICHIGAN Ann Arbor Bell Industries (313)971-9093 Grand Rapids Arrow Electronics (616)243-0912 Hamilton/Avnet (616) 243-8805 Pioneer Standard (616) 698-1800 Livonia Arrow Electronics (313) 665-4100 Pioneer Standard (313) 525-1800 Novi Hamilton/Avnet (313) 347-4720 Southfield R. M. Electronics, Inc. (313) 262-1582 Wyoming R. M. Electronics, Inc. (616) 531-9300
MINNESOTA Eden Prairie Anthem Electronics (612) 944-5454 Pioneer Standard (612) 944.3355 Edina Arrow Electronics (612) 830-1800 Time Electronics (612) 835-1250 Minnetonka Hamilton/ Avnet (612) 932-0600
NATIONAL SEMICONDUCTOR CORPORATION DISTRIBUTORS (Continued)
MISSOURI Chesterfield Hamilton/ Avnet (314) 537-1600 St. Louis Arrow Electronics (314) 567-6888 Pioneer Standard (314) 432-4350 Time Electronics (314) 391-6444
NEW HAMPSHIRE Hudson Bell Industries (603) 882-1133 Manchester Arrow Electronics (603) 668-6968 Hamilton/Avnet (603) 624-9400
NEW JERSEY Cherry Hill Hamilton/Avnet (609) 424-0100 Fairfield Anthem Electronics (201) 227-7960 Hamilton/Avnet (201) 575-3390 Marlton Arrow Electronics (609) 596-8000 Parsippany Arrow Electronics (201) 538-0900 Pine Brook Pioneer Standard (201) 575-3510 Time Electronics (201) 882-4611
NEW MEXICO Albuquerque Alliance Electronics Inc. (505) 292-3360 Arrow Electronics (505) 243-4566 Bell Industries (505) 292-2700 Hamilton/Avnet (505) 345-0001
NEW YORK Binghamton Pioneer (607) 722-9300 Buffalo Summit Electronics . (716) 887-2800 Commack Anthem Electronics (516) 864-6600 Fairport Pioneer Standard (716) 381-7070 Time Electronics (716) 383-8853 Hauppauge Arrow Electronics (516) 231-1000 Hamilton/Avnet (516) 434-7413 Time Electronics (516) 273-0100 Port Chester Zeus Components (914) 937-7400 .
Rochester Arrow Electronics (716) 427-0300 Hamilton/ Avnet (716) 475-9130 Summit Electronics (716) 334-8110
Ronkonkoma Zeus Components (516) 737-4500
Syracuse Hamilton/ Avnet (315) 437-2641 Time Electronics (315) 432-0355
Westbury Hamilton/Avnet Export Div. (516) 997-6868
Woodbury Pioneer Electronics (516) 921-8700
NORTH CAROLINA Charlotte Pioneer Technology (704) 527-8188 Time Electronics (704) 522-7600 Durham Pioneer Technology (919) 544-5400 Raleigh Arrow Electronics (919) 876-3132 Hamilton/Avnet (919) 878-0810 Winston-Salem Arrow Electronics (919) 725-8711
OHIO Centerville Arrow Electronics (513) 435-5563 Bell Industries (513) 435-8660 Bell Industries-Military (513) 434-8231 Cleveland Pioneer (216) 587-3600 Dayton Hamilton/Avnet (513) 439-6700 Pioneer Standard (513) 236-9900 Zeus Components (914) 937-7400 Dublin Time Electronics (614) 761-1100 Solon Arrow Electronics (216) 248-3990 Hamilton/Avnet (216) 831-3500 Westerville Hamilton/ Avnet (614) 882-7004
OKLAHOMA Tulsa Arrow Electronics (918) 252-7537 Hamilton/ Avnet (918) 252-7297 Pioneer Standard (918) 492-0546 Radio Inc. (918) 587-9123
OREGON Beaverton Almac-Stroum Electronics (503) 629-8090 Anthem Electronics (503) 643-1114. Arrow Electronics (503) 645-6456 Hamilton/Avnet (503) 627-0201 Lake Oswego Bell Industries (503) 635-6500 Portland Time Electronics (503) 684-3780
PENNSYLVANIA Horsham Anthem Electronics (215) 443-5150 Pioneer Technology (215) 674-4000 King of Prussia Time Electronics (215) 337-0900 Monroeville Arrow Electronics (412) 856-7000 Pittsburgh Hamilton/Avnet (412)281-4150 Pioneer (412) 782-2300
TEXAS Austin Arrow Electronics (512) 835-4180 Hamilton/Avnet (512) 837-8911 Pioneer Standard (512) 835-4000 Time Electronics (512) 399-3051 Carrollton Arrow Electronics (214) 380-6464 Time Electronics (214) 241-7441 Dallas Hamilton/ Avnet (214) 404-9906 Pioneer Standard (214) 386-7300 Houston Arrow Electronics (713) 530-4700 Pioneer Standard (713) 988-5555 Richardson Anthem Electronics (214) 238-7100 Zeus Components (214) 783-7010 Stafford Hamilton/ Avnet (713) 240-7733
UTAH Midvale Bell Industries (801) 255-9611 Salt Lake City Anthem Electronics (801) 973-8555 Arrow Electronics (801) 973-6913 Hamilton/Avnet (801) 972-4300 West Valley Time Electronics (801) 973-8181
WASHINGTON Bellevue Almac-Stroum Electronics (206) 643-9992 Bothell Anthem Electronics (206) 483-1700 Kent Arrow Electronics (206) 575-4420 Redmond Bell Industries (206) 885-9963 Hamilton/Avnet (206) 881-6697 Time Electronics (206) 882-1600
WISCONSIN Brookfield Arrow Electronics (414) 792-0150 Mequon Taylor Electric (414) 241-4321 Waukesha Bell Industries (414) 547-8879 Hamilton/ Avnet (414) 784-4516
CANADA WESTERN PROVINCES
Burnaby Hamilton/Avnet (604) 437-6667 Semad Electronics (604) 420-9889
Calgary Hamilton/ Avnet (403) 250-9380 Semad Electronics (403) 252-5664 Zentronics (403) 272-1021
Edmonton Zentronics (403) 468-9306
Richmond Zentronics (604) 273-5575
Saskatoon Zentronics (306) 955-2207
Winnipeg Zentronics (204) 694-1957
EASTERN PROVINCES Mississauga Hamilton/Avnet (416) 677-7432 Time Electronics (416) 672-5300 Zentronics (416) 564-9600 Nepean Hamilton/Avnet (613) 226-1700 Zentronics (613) 226-8840 Ottawa Semad Electronics (613) 727-8325 Pointe Claire Semad Electronics (514) 694-0860 St. Laurent Hamilton/Avnet (514) 335-1000 Zentronics (514) 737-9700 Willowdale ElectroSonic Inc. (416) 494-1666
SALES OFFICES
ALABAMA Huntsville (205) 721-9367
ARIZONA Tempe (602) 966-4563
CALIFORNIA El Segundo (213) 643-7099 Rocklin (916) 632-2750 San Diego (619) 587-0666 Santa Clara (408) 562-5900 Tustin (714) 259-8880 Woodland Hills (818) 888-2602
COLORADO Boulder (303) 440-3400 Colorado Springs (719) 578-3319 Englewood (303) 790-8090
FLORIDA Boca Raton (407) 997-9891 Orlando (407) 629-1720 St. Petersburg (813) 577-5017
GEORGIA Norcross (404) 441-2740
ILLINOIS Schaumburg (708) 397-8777
INDIANA Carmel (317) 843-7160 Fort Wayne (219) 484-0722
IOWA Cedar Rapids (319) 395-0090
KANSAS Overland Park (913) 451-4402
MARYLAND Hanover (301) 796-8900
MASSACHUSETTS Burlington (617) 221-4500
MICHIGAN Grand Rapids (616) 940-0588 W. Bloomfield (313) 855-0166
MINNESOTA Bloomington (612) 854-8200
MISSOURI St. Louis (314) 569-9830
NEW JERSEY Paramus (201) 599-0955
NEW MEXICO Albuquerque (505) 884-5601
NEW YORK Fairport (716) 223-7700 Melville (516) 351-1000 Wappinger Falls (914) 298-0680
NORIH CAROLINA Raleigh (919) 832-0661
OHIO Dayton (513) 435-6886 Independence (216) 524-5577
ONTARIO Mississauga (416) 678-2920 Nepean (613) 596-0411
OREGON Portland (503) 639-5442
PENNSYLVANIA Horsham (215), 672-6767
PUERTO RICO Rio Piedras (809) 758-9211
QUEBEC Pointe Claire (514) 426-2992
TEXAS Austin (512) 346-3990 Houston (713) 771-3547 Richardson (214) 234-3811
UTAH Salt Lake City (801) 322-4747
WASHINGTON Kirkland (206) 822-4004
WISCONSIN Brookfield (414) 782-1818
~ National
~ Semiconductor
National Semiconductor Corporation 2900 Semiconductor Drive P 0 Box 58090 Santa Clara. CA 95052-8090 Tel (408) 721-5000 TWX (910) 339-9240
SALES OFFICES (Continued)
INTERNATIONAL OFFICES
Electronica NSC de Mexico SA Juvent1no Rosas No 118-2 Col Guadalupe 'nn Mexico_ 01020 D F Mexico Tt,I 52-5-524-9402
National Semicondutores Do Bras il Ltda . Av Brig Faria Lima 1383 6 0 Ardor-Ccn1 62 0145 1 Sao Paulo SP Bras1i Tel (55,11)212-5066 Fax (55-11)211-1181 NSBRBR
National Semiconductor GmbH lnclustr1estrasse 10 D-8080 Furstenfeldbruck. West German~ Tel (0-81.4 ~I 103-0 Telex 527-649 Fa;w; I 0814 ~ l 103554
National Semiconductor (UK) Ltd . The Maple Kembrey Park Swindon W11tsh1re SN2 6UT United k 1ngdom Tel (07-93J61-41-41 Telex 444-674 Fax (07-93) 69- 75-22
National Semiconductor Benelux V�Jrstlaan 100 8-1 170 Brussels Belgium Te! I 021 6-61 -06-80 Te1e._ 61007 ~ax 1021 6-60-23-9:'.
National Semiconductor (UK) Lid. R1ngager 4A 3 Ok.-2605 Brcndt:y Denman< Tel 102J43�32-11 TeleK 15.179 F-aK (02),13-31-11
National Semiconductor S.A. Centre d'AHa1res�La Bours1d1ere 8<3.t1mcn1 Champagne. 8 P 90 Route Na!1onale 186 F-923':'-7 Le P1ess1s Robinson France Tel (1l 40-94-88-88 Telex 631065 Fax ( 1) 40-94-88-11
National Semiconductor (UK) Lid. un.t 2A Clonskeagr, Square Clonskeagh Road Dublin 14 Tel (01)69-55-89 Tele._ 91047 Fax W)) 69-55-89
Natioflal Semiconductor S.p.A. Strada 7 Palazzo R 1.20089 Razzano Milanof�or1 Ital/ Tel 102102.12045, 7- 9,19 TwK 352647 Fa .. 102) 8254758
National Semiconductor S.p.A. \/1a del Cararaqg10 107 0014 7 Rome Ital\. Te1 !061 5-13-48-80 FaK 10615-13-79-41
National Semiconductor (UK) Lid. Stasionsvn 18 Postboks 15 N- t 361 Billlngstadsletla Norway TCl .! 7-2-849362 Fax 4 7-2-848 ~ 04
National Semiconductor AB P 0 BOK 1009 Grosshandlarvaegen 7 S-12 ~ 23 Johannesr.ov Sweden Tel 46-8-7228050 Fax 46-8-722909': Telex 10731 NSC S
National Semiconductor GmbH Calle Agustin de Fox a. 27 (9 0) 28036 Madrid Spain Tel (01) 733-2958 Telex 46133 Fax (01l 733-8018
National Semiconductor Switzerland Alte W1nterthurerstrasse 53 Poslfach 567 Ch-8304 Wall1sellen-Zur1ch Switzerland Tel (01 l 830�2727 Tele� 828-444 Fax (01)830-1900
National Semiconductor Kauppakartanonka!u 7 A22 SF-0093C Hels1nk1 Finland Tel (9C) 33-80-33 Telex 126116 Fax (90) 33-81-30
National Semiconductor Postbus 90 1380 AB Weesp The Netheriands Tel !0-29-401 3-04-48 Telex 10-956 Fax (0�29-401 3-04-30
National Semiconductor Japan Ltd. Sanseido Bldg SF 4-15 N1sh1Sh1n1uku Sh1n1uku-ku To~yo 160 Japan Tel 3-299-7001 Fax 3�299-7000
National Semiconductor Hong Kong Ltd . Suite 513. 5th Floor Ch1nacnem Golden Plaza 77 Mody Road. Ts1mshatsu1 East Kowloor. Hong Kong Tel 3�7231290 Tele� 52996 NSSEA HX Fax 3-3112536
National Semiconductor (Australia) PTY. Ltd . 1st Floor. 441 St Kilda Rd Melbourne 3004 VJC'loria. Australia Tel (03J 267�5000 Fax 61-3-~677458
National Semiconductor (PTE}, Ltd. 200 Cantonment Road 13-01 Southpo1nt Singapore 0208 Tel 2252226 Telex RS 33877
National Semiconductor (Far East) Ltd. Taiwan Branch P 0 Box 68-332 Ta1pe1 7th Floor. Nan Shan Lile Bldg 302 Min Chuan East Road Ta1pe1 Ta1wan R 0 C Tel (86) 02-501-7227 TeleK 22837 NSTW Cable NSTW TAIPEI
National S'emiconductor (Far East) Ltd. Korea Branch 13th Floor. Dai Han Lile insurance 63 Building 60 Yo1do�dong. Youngdeungpo�ku Seoul. Korea 150- 763 Tel 102) 784-8051 3. 785-0696.1 8 Telex 24942 NSPKLO Fax (02) 784-8054
400023
NATIONAL 74FXX SERIES OATABOOK
$11.95