Bwave Technology TETHYS Tethys User Manual

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Under Development
Confidential
ASD-B-16-0247
RTK00V2XRC7746SFS
User’s Manual: Hardware
― Preliminary ―
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corp. without notice. Please review the latest information published by
Renesas Electronics Corp.
Rev.1.00
Nov. 2016
RTK00V2XRC7746SFS
Hardware Design Specification
CONTENTS
OVERVIEW.............................................................................................................................................................. 9
1.1
FEATURES .......................................................................................................................................................... 10
1.1.1
Features of the Tethys Board..................................................................................................................... 10
1.1.2
Functions of the Tethys Board ................................................................................................................... 11
1.2
USAGE NOTES ................................................................................................................................................... 12
1.2.1
1.3
Specifications of the Tethys Board ............................................................................................................ 12
BOARD CONFIGURATION ................................................................................................................................... 13
1.3.1
OPERATING CONDITION AND ANTENNA CHARACTERISTIC ............................................................... 14
2.1
Block Diagram of the Tethys Board .......................................................................................................... 13
OPERATING CONDITION...................................................................................................................................... 14
SPECIFICATIONS OF INTERFACE MODULES ON THE TETHYS BOARD............................................. 15
3.1
MODE SETTING.................................................................................................................................................. 15
3.1.1
Specifications ............................................................................................................................................ 15
3.1.2
MD0 Pin -Selection of Free-Running Mode or Step-Up Mode ................................................................. 15
3.1.3
MD [3:1] Pins-Selection of Boot Device .................................................................................................. 15
3.1.4
MD4 Pin-Selection of CS0 Space Size ...................................................................................................... 15
3.1.5
MD5 Pin-Reserved .................................................................................................................................... 15
3.1.6
MD[7:6] Pins-Selection of Master Boot Processor .................................................................................. 15
3.1.7
MD8 Pin-Selection of Area 0 Space Data Bus Width................................................................................ 16
3.1.8
MD9 Pin-Selection of Crystal Resonator or Crystal Oscillator ............................................................... 16
3.1.9
MD21, MD20, MD11, MD10, and MDT[1:0] Pins-Switching of JTAG, SDHI1, and SDHI2 .................. 16
3.1.10
MD[14:13] Pins-Frequency Mode Setting ............................................................................................... 17
3.1.11
Initial Values of Mode Setting Pins on Tethys Board ................................................................................ 17
3.2
DDR3-SDRAM INTERFACE (DBSC) ................................................................................................................ 18
3.2.1
Specifications ............................................................................................................................................ 18
3.2.2
Signal Connections between R-Car W2H and DDR3-SDRAMs ............................................................... 18
3.2.3
Block Diagram .......................................................................................................................................... 19
3.3
SPI-FLASH INTERFACE (QSPI) .......................................................................................................................... 20
3.3.1
Specifications ............................................................................................................................................ 20
3.3.2
Block Diagram .......................................................................................................................................... 20
3.4
AUDIO CODEC INTERFACES (SSI0, SSI1)........................................................................................................... 21
3.4.1
Specifications ............................................................................................................................................ 21
3.4.2
Block Diagram .......................................................................................................................................... 21
3.5
3.5.1
EMMC MEMORY INTERFACE (EMMC) .............................................................................................................. 22
Specifications ............................................................................................................................................ 22
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3.5.2
3.6
Block Diagram .......................................................................................................................................... 22
SD CARD HOST INTERFACE (SDHI2) ................................................................................................................ 23
3.6.1
Specifications ............................................................................................................................................ 23
3.6.2
Block Diagram .......................................................................................................................................... 23
3.7
MINI PCI EXPRESS INTERFACE .......................................................................................................................... 24
3.7.1
Specifications ............................................................................................................................................ 24
3.7.2
The Mini PCIE connector signal configuration are shown as below: ...................................................... 24
3.7.3
Block Diagram .......................................................................................................................................... 28
3.8
USB TO UART .................................................................................................................................................. 29
3.8.1
Specifications ............................................................................................................................................ 29
3.8.2
Block Diagram .......................................................................................................................................... 29
3.9
USB2.0 INTERFACE ........................................................................................................................................... 30
3.9.1
Specifications ............................................................................................................................................ 30
3.9.2
Block Diagram .......................................................................................................................................... 31
3.10
DEBUG INTERFACE ............................................................................................................................................ 32
3.10.1
CPU debug................................................................................................................................................ 32
3.10.2
CPU JTAG2 debug.................................................................................................................................... 33
3.10.3
MCU debug ............................................................................................................................................... 34
3.11
GYRO/G-SENSOR .......................................................................................................................................... 35
3.11.1
Specifications ............................................................................................................................................ 35
3.11.2
Block Diagram .......................................................................................................................................... 35
3.12
I2C INTERFACES ................................................................................................................................................ 36
3.12.1
Specifications ............................................................................................................................................ 36
3.12.2
List of Slave Addresses .............................................................................................................................. 37
3.12.3
Block Diagram .......................................................................................................................................... 37
3.13
GPS MODULE .................................................................................................................................................... 38
3.13.1
Specifications ............................................................................................................................................ 38
3.13.2
Block Diagram .......................................................................................................................................... 38
3.14
CAN AND FLEXRAY INTERFACE......................................................................................................................... 39
3.14.1
Specifications ............................................................................................................................................ 39
3.14.2
Block Diagram .......................................................................................................................................... 39
3.15
LEDS AND SWITCHES ........................................................................................................................................ 41
3.15.1
3.16
Specifications ............................................................................................................................................ 41
CONNECTION BETWEEN CPU AND MCU ........................................................................................................... 44
3.16.1
Specifications ............................................................................................................................................ 44
3.16.2
Block Diagram .......................................................................................................................................... 44
3.17
CLOCK SYSTEM.................................................................................................................................................. 45
3.17.1
Clock Signals Supplied to the R-Car W2H ............................................................................................... 45
3.17.2
Differential Clock Signals Supplied to the R-Car W2H ............................................................................ 45
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3.17.3
Clock Signals Supplied to Devices Other than R-Car W2H ..................................................................... 45
3.17.4
Block Diagram .......................................................................................................................................... 46
3.18
3.18.1
Specifications ............................................................................................................................................ 46
3.18.2
Block Diagram .......................................................................................................................................... 47
3.19
RESET SYSTEM .................................................................................................................................................. 47
3.19.1
Specifications ............................................................................................................................................ 47
3.19.2
Block Diagram .......................................................................................................................................... 48
3.19.3
Reset Sequence .......................................................................................................................................... 48
3.20
EXTERNAL INTERRUPTS ..................................................................................................................................... 46
POWER SYSTEM ................................................................................................................................................. 50
3.20.1
Specifications ............................................................................................................................................ 50
3.20.2
Block Diagram .......................................................................................................................................... 51
3.20.3
Power Sequence ........................................................................................................................................ 52
MEMORY MAP ..................................................................................................................................................... 53
4.1
SPECIFICATIONS ................................................................................................................................................. 53
4.2
FUNCTION .......................................................................................................................................................... 57
4.2.1
Control the power of the Tethys Custom Board. ....................................................................................... 57
4.2.2
Realize the UART with the baud rate of 115200 ....................................................................................... 58
4.2.3
Realize an asynchronous serial with baud rate of 1M between RH850 and CPU. ................................... 59
4.2.4
Make CAN0 and CAN1 working with baud rate of 1M............................................................................. 59
OUTLINE DIAGRAMS OF THE TETHYS BOARD......................................................................................... 60
5.1
TETHYS BOARD DIMENSION .............................................................................................................................. 60
5.2
THE WEIGHT OF THE TETHYS BOARD ................................................................................................................. 60
5.3
TETHYS ID DIMENSION ...................................................................................................................................... 61
5.4
TETHYS ASSEMBLY ............................................................................................................................................ 63
BOARD CONNECTORS ....................................................................................................................................... 67
6.1
TOP SIDE CONNECTORS ..................................................................................................................................... 67
6.2
BOTTOM SIDE CONNECTORS .............................................................................................................................. 68
6.3
THE DETAILS OF CONNECTORS ........................................................................................................................... 69
APPENDIX ............................................................................................................................................................. 71
7.1
USB DEBUG CABLE ........................................................................................................................................... 71
7.2
AC ADAPTER ..................................................................................................................................................... 72
7.2.1
Specifications ............................................................................................................................................ 72
7.2.2
Mechanic Size and Picture ........................................................................................................................ 73
7.3
7.3.1
GPS ANTENNA ................................................................................................................................................... 75
Specification ............................................................................................................................................. 75
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Hardware Design Specification
7.4
7.4.1
7.5
7.5.1
7.6
7.6.1
7.7
Specification ............................................................................................................................................. 77
V2X ANTENNA (ROD TYPE) .............................................................................................................................. 84
Specification ............................................................................................................................................. 84
RF CABLE.......................................................................................................................................................... 91
Specification ............................................................................................................................................. 91
JTAG DEBUG BOARD WITH FPC CABLE ........................................................................................................... 92
7.7.1
Specifications ............................................................................................................................................ 92
7.7.2
Block Structure.......................................................................................................................................... 92
7.7.3
Block Diagram .......................................................................................................................................... 93
7.8
V2X CONNECTION BOARD................................................................................................................................. 94
7.8.1
Board Structure ......................................................................................................................................... 94
7.8.2
Block Diagram .......................................................................................................................................... 95
7.8.3
Block dimension ....................................................................................................................................... 95
7.9
V2X ANTENNA1 WITH 2M CABLE ...................................................................................................................... 77
SUB BOARD TORTUGA WIRELESS MODULE BOARD DIMENSION........................................................................... 96
7.9.1
RF characteristic ...................................................................................................................................... 96
7.9.2
Board Dimension ...................................................................................................................................... 98
7.10
SIDE COVER OPTION OF CASE ........................................................................................................................... 100
7.11
ACRONYMS AND ABBREVIATIONS .................................................................................................................... 101
REGULATORY WARNING STATEMENTS .................................................................................................... 102
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Tables
Table 1 Features of the Tethys Board .......................................................................................................... 10
Table 2 List of Tethys Board Functions ....................................................................................................... 11
Table 3 Operating Condition...................................................................................................................... 14
Table 4 DDR3-SDRAM Interface Specifications ......................................................................................... 18
Table 5 Signal Connections between R-Car W2H and DDR3-SDRAMs ........................................................ 18
Table 6 SPI-Flash Interface Specifications .................................................................................................. 20
Table 7 SSI Codec Specifications............................................................................................................... 21
Table 8 eMMC Memory Interface (eMMC) Specifications........................................................................... 22
Table 9 Specifications of SD Card Host Interface (SDHI2) .......................................................................... 23
Table 10 USB to UART Specifications ....................................................................................................... 29
Table 11 USB2.0 Interface ........................................................................................................................ 30
Table 12
CPU debug Specifications ........................................................................................................... 32
Table 13
CPU JTAG2 debug ..................................................................................................................... 33
Table 14
MCU debug Specification............................................................................................................ 34
Table 15 GYRO/G-SENSOR Specifications ............................................................................................... 35
Table 16
List of I2C Devices ..................................................................................................................... 36
Table 17
List of I2C Slave Addresses ......................................................................................................... 37
Table 18
CAN and Flexray Interface Specifications ..................................................................................... 39
Table 19 DIP Switches default setting is as below table ............................................................................... 41
Table 20 Slide Switches default setting is as below table: ............................................................................. 43
Table 21
List of Clock Signals and Crystals for the R-Car W2H ................................................................... 45
Table 22
List of Differential Clock Signals Supplied to the R-Car W2H ........................................................ 45
Table 23
List of Clocks and Crystals other than for R-Car W2H ................................................................... 45
Table 24
External Interrupts Specifications ................................................................................................. 46
Table 25
Reset System Specifications......................................................................................................... 47
Table 26
List of the Switching Controllers and Regulators on the Tethys Board ............................................. 50
Table 27 Antenna Specification for GPS module ......................................................................................... 75
Table 28 Antenna Specification for V2X (2m cable) .................................................................................... 77
Table 29 Antenna Specification for V2X (Rod Type) ................................................................................... 84
Table 30
RF Cable Specification for GPS module & RF Board..................................................................... 91
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Figures
Figure 1
Block Diagram of the Tethys Board .............................................................................................. 13
Figure 2
Block Diagram of the DDR3-SDRAM Interface ............................................................................ 19
Figure 3
Block Diagram of the SPI-Flash Interface ..................................................................................... 20
Figure 4
Block Diagram of the Audio Codec Interface ................................................................................. 21
Figure 5
Block Diagram of the eMMC Memory Interface ............................................................................ 22
Figure 6
Block Diagram of the SDHI2 Interface ......................................................................................... 23
Figure 7
Block Diagram of Mini PCI Express Interface ............................................................................... 28
Figure 8
Block Diagram of the USB to UART ............................................................................................ 29
Figure 9
Block Diagram of the USB2.0 Interface ........................................................................................ 31
Figure 10
Block Diagram of the CPU debug ............................................................................................... 32
Figure 11
Block Diagram of the CPU JTAG2 (SH-4AL) debug .................................................................... 33
Figure 12
Block Diagram of the MCU debug .............................................................................................. 34
Figure 13
Block Diagram of the GYRO/G-SENSOR ................................................................................... 35
Figure 14
Block Diagram of the I2C Interfaces ........................................................................................... 37
Figure 15
Block Diagram of the GPS module ............................................................................................. 38
Figure 16
Block Diagram of the CAN and Flexray Interface ........................................................................ 39
Figure 17
Block Diagram of the Connection between CPU and MCU ........................................................... 44
Figure 18
Block Diagram of the Clock system ............................................................................................ 46
Figure 19
Block Diagram of the External Interrupts .................................................................................... 47
Figure 20
Block Diagram of the Reset System ............................................................................................ 48
Figure 21
The Reset Sequence ................................................................................................................... 49
Figure 22
Block Diagram of the Power System ........................................................................................... 51
Figure 23
The Power Sequence.................................................................................................................. 52
Figure 24
The Tethys board dimension ....................................................................................................... 60
Figure 25
TOP Side Connectors ................................................................................................................. 67
Figure 26
Bottom side connectors .............................................................................................................. 68
Figure 27
Image of USB debug cable ......................................................................................................... 71
Figure 28
Power Adapter ID LOG specification .......................................................................................... 74
Figure 29
Image of Power Adapter............................................................................................................. 74
Figure 30
Image of GPS Antenna from Bottom view ................................................................................... 76
Figure 31
Image of GPS Antenna from Top view ........................................................................................ 76
Figure 32 V2X Antenna Test Chamber description ...................................................................................... 78
Figure 33 V2X Antennal test axis definition description .............................................................................. 79
Figure 34 V2X Antennal VSWR test character ............................................................................................ 80
Figure 35 V2X Antennal 2D radiation pattern ............................................................................................. 81
Figure 36 V2X Antennal 3D radiation pattern ............................................................................................. 82
Figure 37
Image of V2X Antenna1 from Bottom view ................................................................................. 83
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Figure 38
Image of V2X Antenna1 from Top view ...................................................................................... 83
Figure 39 V2X Antenna2 Test Chamber description .................................................................................... 85
Figure 40 V2X Antenna2 test axis definition description .............................................................................. 86
Figure 41 V2X Antenna2 VSWR test character ........................................................................................... 87
Figure 42 V2X Antenna2 2D radiation pattern ............................................................................................ 88
Figure 43 V2X Antenna2 3D radiation pattern ............................................................................................ 89
Figure 44
Image of V2X Antenna2 (SMA rotate 90 degree) ......................................................................... 90
Figure 45
Image of V2X Antenna2 (SMA rotate 0 degree) ........................................................................... 90
Figure 46
RF Cable .................................................................................................................................. 91
Figure 47
JTAG Debug Board with FPC Cable for W2H & RH850 MCU ..................................................... 92
Figure 48
JTAG Debug Board block structure ............................................................................................. 92
Figure 49
Block Diagram of the JTAG Debug Board ................................................................................... 93
Figure 50
Top side view of V2X Connection board ..................................................................................... 94
Figure 51
Bottom side view of V2X Connection board ................................................................................ 94
Figure 52
Block structure of V2X Connection board ................................................................................... 94
Figure 53
Block Diagram of the V2X Connection board .............................................................................. 95
Figure 54
Side cover option of case.......................................................................................................... 100
Appendix
Appendix 1 Acronyms and Abbreviations ................................................................................................. 101
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Hardware Design Specification
1 Overview
The Tethys board is R-Car W2H-specific evaluation board that can be used to evaluate systems using the R-Car
W2H and to develop operating systems, device drivers, and applications. Using the Tethys board allows developers to
efficiently conduct required tasks such as evaluating the performance of R-Car W2H-based systems, thus greatly
reducing turn-around times in product development.
Micro USB : CN16、CN10、CN5
D12 (GPS_LED)、D4、D6、D8、D10
Audio jack
CN9、CN8、CN12、CN11
J1
HSM CN14
DEBUG CN4
USB CN1
POWER Switch
CAN&Flexray
SW18
CN6
POWER IN JACK
Ethernet CN3
CN17 and CN18
ETNB CN13
SW1、SW2
D9、D7、D5、D3、D11 (GPS_LED)
SW11、SW10、SW9、SW8
SW16、SW15、SW14、SW13、SW4 (MCU reset)
SW5、SW6、SW7
SD Card CN2
GPS Antenna CN7
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1.1 Features
1.1.1
Features of the Tethys Board
Table 1
Features of the Tethys Board
Item
CPU
Description
·U1:R-Car W2H
( Operating clock: ARM 1.0GHz(Max), SH-4AL 260MHz)
MCU
·U32:RH850F1H/F1L
( Operating clock: RH850F1H 120MHz, RH850F1L 60MHz)
Audio Interfaces
·J1:
(1) L/R Audio output for SSI0
(2) Microphone input for SSI1
Connectors
·CN6:CAN & Flexray Connector( Flexray not support)
·CN7:GPS ANT Connector
·CN14:HSM Connector( not support)
·CN13:ETNB Connector ( not support)
PCIE Connectors
·CN9:Mini PCIE Connector for V2X Sub Board
·CN8:Mini PCIE Connector for EtherAVB Sub Board( not support)
·CN12:Mini PCIE Connector for V2X Sub Board
·CN11:Standard Mini PCIE
Debugger Interfaces
·CN4:26 pin FPC connector for CPU and MCU.
·CN10:UART-USB for Debug
·CN5:UART-USB for CPU Debug
·CN16:UART-USB for MCU Debug
Network Interfaces
·CN3:10M/100M Ethernet connector for Ethernet MAC
Storage Interfaces
·CN1:USB2.0 type A receptacle x 2
·CN2:SD card slots for SDHI2
·eMMC memory for MMC
Power Supply
·CN17 or CN18: DC 12V input
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1.1.2
Functions of the Tethys Board
Table 2
List of Tethys Board Functions
Tethys
Board Function
RAM
DDR3 I/F : DDR3-SDRAM 1066MHz 1 GB x2
USB 2.0
USB2.0 CH0 : USB2.0 type A
USB2.0 CH1 : USB2.0 type A
SDHI
SDHI0 : Mini PCIE Connector for V2X Sub Board
SDHI2 : SD card slots , Mini PCIE Connector for V2X Sub Board
SCIF
SCIF0_D/HSCIF0_B : (1) Mini PCIE Connector for V2X Sub Board ,
(2) UART-USB
SCIF3_B/HSCIF2 : Mini PCIE Connector for V2X Sub Board
SCIF2_B(Debug serial) : UART-USB for CPU Debug
SCIF5_C : GPS Module
ROM(QSPI)
QSPI0 : SPI Flash 64MB
QSPI1 : SPI Flash 4MB
Ether MAC / Ether AVB
Ether MAC : RJ45 Connector
Ether AVB : Mini PCIE Connector for Ether AVB Sub Board (Ether AVB not support)
HSCIF
HSCIF1_A : Mini PCIE Connector for Ether AVB Sub Board (Ether AVB not support)
SCIF0_D/HSCIF0_B : (1) Mini PCIE Connector for V2X Sub Board ,
(2) UART-USB
SCIF3_B/HSCIF2 : Mini PCIE Connector for V2X Sub Board
I2C
I2C1_A/SPI : HSM Connector ( not support)
I2C1_A : G-Sensor , Gyro , MCU
SSI
SSI0,1,2,9 : Audio CODEC
MSIOF
MSIOF1_B : MCU [Flexray (not support)、Ethernet AVB not support]
MMC
MMC : eMMC(8GB)
PCI Express
Mini PCIE Connector
CAN
W2H CAN channel support, RH850 CAN0/1 support ,Flexray not support
Debug I/F
DBG : TO Sub Connector
VCC
Power Block
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1.2 Usage Notes
1.2.1
Specifications of the Tethys Board
When the AC adapter is connected to the outlet, the 12V DC power is supplied to the Tethys board and some of the circuitry start
operating. Setting the ACC switch (SW18) to the ON side after that leads to the generation of various power supply levels including
5V DC and 3.3V DC from the 12V DC power.

Take particular care to ensure the correct configurations of the jumpers and switches mounted on the Tethys board. Incorrect
configurations may damage on-board devices.

For power supply to the Tethys, be sure to use the power supply that comes with it. Applying a voltage greater than 12 V may
damage devices on the Tethys board.

There are sequences for turning on and off the power supply to the Tethys board. Be sure to obey the notes below when using
the Tethys board.
(1) When turning on the power
Be sure to confirm that the ACC switch (SW18) is off before plugging the AC adapter into the power source.
It is prohibited to plug the AC adapter into a power source while the ACC switch (SW18) is on.
(2) When turning off the power
Be sure to turn off the ACC switch (SW18) before unplugging the AC adapter from the power source.
It is prohibited to unplug the AC adapter from the power source while the ACC switch (SW18) is on.

The AC adapter that comes with the Tethys board can supply current up to 3A at 12V. If you intend sub board to PCIe connect
on Tethys board, ensure that this does not lead to supply current exceeding 3A.
If the system configuration is such that the current supply does exceed 3A, prepare a separate stabilized DC power supply that
can supply more current at 12V.

Regarding the dedicated socket for the R-Car W2H, neither disconnect it from nor connect it to the Tethys board; also,
regarding the R-Car W2H, neither remove it from nor insert it in the dedicated socket. Both actions lead to malfunctions of
R-Car W2H operation on the board due to loosening of contacts between the socket and the board and between the socket and
the R-Car W2H.
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1.3 Board Configuration
The Tethys board is composed of a single board whose size is 185 mm ×110 mm
1.3.1
Block Diagram of the Tethys Board
Figure 1 shows a block diagram of the Tethys board
SPI Flash(4MB)
S25FL132K0XMFI011
Spansion
DDR3 4Gbit
2 devices
DDR3
4G*32 bit
MT41K256M16HA-125
Micron
2 devices
DDR3 I/F
SPI Flash(64MB)
S25FL512SAGMFIG11
Spansion
QSPI
USB 2.0-H
Type-A CN 2 in1
1775468-1
Samtec
GPIO
USB2.0 CH1-2
USB 2.0 CH0
HSCIF1_A
USB 2.0 CH1-2,3,4
USB CH1 -1
USB HUB
GL852GT-MNGXX
GENESYS
USB 2.0 CH1
EtherMAC/
EtherAVB
SDHI0
MMC
Mini PCI
Express CN
1759546-1
TE
RJ45 CN
HY911105AE
Hanrun
RMII PHY
KSZ8041RNLI
Micrel
USB 2.0 CH1-4
1PPS
Mini PCI
Express CN
1759546-1
TE
Emmc(8GB)
SDIN8DE1-8G-XA
Sandisk
GPIO
G-Sensor
AIS328DQ
ST
SCIF0_D/HSCIF0_B
I2C1_A
Gyro
A3G4250D
ST
USB to UART
CP2102
Silicon
USB micro-B CN
47346-0001
Molex
CAN0_C
SD Card Slot CN
503182-1852
Molex
SDHI2
GPIO
USB 2.0 CH1-3
Mini PCI
Express CN
1759546-1
TE
SCIF3_B/HSCIF2
CPU
R-CarW2H
Renesas
CAN CN
TSW-104-08-F-D
Samtec
CAN transceiver
TJA1050
NXP
1PPS
SCIF5_C
GPIO
GPS Module
NEO-7M
U-blox
GPS ANT
U.FL-R-SMT
Murata
1PPS
USB to UART
CP2102
Silicon
Mini PCI
Express CN
1759546-1
TE
USB micro-B CN
47346-0001
Molex
PCI Express
MSIOF1_B
USB to UART
CP2102
Silicon
USB micro-B CN
47346-0001
Molex
SCIF2_B
(debug serial)
HSCIF2
I2C1_A
Audio DAC/ADC
AK4642
AKM
Mini Jack Line OUT
MCU
RH850F1H
Renesas
RESET
SSI0,1,2,9
FlexrayDriver
FlexrayCN
CAN
transceiver
TJA1050
NXP
CAN CN
TSW-104-08-F-D
Samtec
CAN
transceiver
TJA1050
NXP
CAN CN
TSW-104-08-F-D
Samtec
GPIO
HSM CN
EtherAVB CN
I2C1_A/SPI
CPU JTAG CN
HTST-110-01-S-DV
Samtec
DBG
Tact SW 4bit
SKRKAEE010
ALPS
GPIO
LED 4bit
SML-D13FW
ROHM
GPIO
VCC
Power Block
To sub Connector
FH12-20S-0.5SV
Irios
FPC
Connector
FH12-20S-0.5SV
Irios
CPU SH4A JTAG CN
1-1634688-4
Samtec
BU12V
MCU JTAG CN
1-1634688-4
Samtec
Debug Board
Tethy Board
Figure 1
Block Diagram of the Tethys Board
Notice:

White text means not support the function
(HSM CN, Flexray_CN, EtherAVB CN)
ASD-B-16-0247 Rev1.0
Nov 29, 2016
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Hardware Design Specification
2 Operating condition and antenna characteristic
2.1 Operating condition
Table 3 shows the operating condition. To use the Tethys board system, please keep the condition.
Table 3
Operating Condition
Item
Min
Typ
Max
Units
Input Voltage
12
25
Consumption Current
200
450
3000(*1)
mA
Operating Temperature
-25
25
+85
Degree C
V2X antenna Frequency range
5860
5920
MHz
V2X antenna VSWR
2.0
V2X antenna Gain
dBi
2M Cable Type:
(1)3.0(without cable loss)
(2) -1.0(with cable loss)
Rod Type:
(1)5.0
V2X antenna Cable Loss
4.0 (L=2m)
dB
GPS antenna Center Frequency
1575 ± 3
MHz
GPS antenna VSWR
GPS antenna Bandwidth
2.0
20
GPS antenna Gain
MHz
30
dB
Storage Temperature
-25
85
Degree C
Operating Humidity
25
85(*2)
Notice:

(*1): 3000mA is the maximum current of AC adapter. If user need more current for Tethys board, user need
prepare stable big current AC adapter.

(*2):Humidity: No condensation.
ASD-B-16-0247 Rev1.0
Nov 29, 2016
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RTK00V2XRC7746SFS
Hardware Design Specification
3 Specifications of Interface Modules on the Tethys Board
This section describes the main function of the Tethys board, which includes the following sections:
3.1 Mode Setting
3.1.1
Specifications
The operating mode of the R-CarW2H is set by a power-on reset. For details on the operating mode, see the documents related
to the R-CarW2H operating mode specifications.
3.1.2
MD0 Pin -Selection of Free-Running Mode or Step-Up Mode
Do not change the initial setting at shipment (MD0=0).
3.1.3
MD [3:1] Pins-Selection of Boot Device
These pins select the boot device.
MD3
MD2
MD1
Selection of Boot Device
External ROM boot (area 0)
eMMC boot via SDHI1
Serial flash ROM boot via QSPI; 16Kbytes transferred at 48.75 MHz
Reserved
Serial flash ROM boot via QSPI; 16Kbytes transferred at 39 MHz
Reserved
Serial flash ROM boot via QSPI; 4 Kbytes transferred at 39 MHz
Reserved
3.1.4
MD4 Pin-Selection of CS0 Space Size
This pin selects whether the area 0 space (CS0) is used as a normal space (64 Mbytes) or an expanded space (128 Mbytes).
MD4
Area Division
Area 0: 64 Mbytes
Area 0: 128 Mbytes
3.1.5
MD5 Pin-Reserved
Do not change the initial setting at shipment (MD5=1).
3.1.6
MD[7:6] Pins-Selection of Master Boot Processor
These pins select the master boot processor.
ASD-B-16-0247 Rev1.0
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RTK00V2XRC7746SFS
Hardware Design Specification
MD7
MD6
Selection of Master Boot Processor
Setting prohibited
Booted through CPU0 in CA7.
Booted through SH-4AL in 32-bit mode
Setting prohibited
3.1.7
MD8 Pin-Selection of Area 0 Space Data Bus Width
This pin sets the data bus width of the area 0 space (CS0) to 8 bits or 16 bits. Select the data bus width of the boot device
connected to the LBSC.
MD8
EXBUS Area 0 Data Bus Width
8-bit bus
16-bit bus
3.1.8
MD9 Pin-Selection of Crystal Resonator or Crystal Oscillator
This pin selects either a crystal resonator or a crystal oscillator to be connected to the EXTAL/XTAL pins. A crystal oscillator
(Y2: 20 MHz) is mounted on the Tethys board by default.
MD9
EXTAL/XTAL Pin Setting
An external clock is input to the EXTAL pin.
A crystal resonator is connected to the EXTAL and XTAL pins.
3.1.9
MD21, MD20, MD11, MD10, and MDT[1:0] Pins-Switching of JTAG, SDHI1, and SDHI2
These pins select the debugging function through the JTAG connector (CN4) or the SD card slot for the SDHI1. The debugging
through the SDHI1 or SDHI2 is possible by the combination of MD pin settings in the R-CarW2H specifications.
MD10
MD[21:20]
MD11
MDT[1:0]
00
--
Boundary scan
Normal function
Normal function
01
--
Reserved
Reserved
Reserved
10
--
Coresight (*1)
Normal function
Normal function
10
00
Coresight (*1)
Reserved
Reserved
10
01
Coresight (*1)
SH-4AL
Normal function
10
10
Coresight (*1)
Reserved
Reserved
10
11
Coresight (*1)
Normal function
SH-4AL
11
--
SH-4AL
Normal function
Normal function
11
00
SH-4AL
Coresight (*1)
Normal function
00
--
Reserved
Reserved
Reserved
01
--
Reserved
Reserved
Reserved
01
01
Reserved
Reserved
Reserved
10
--
Reserved
Reserved
Reserved
11
--
Reserved
Reserved
Reserved
ASD-B-16-0247 Rev1.0
Nov 29, 2016
JTAG
MMC
SDHI2
Page 16 of 102
RTK00V2XRC7746SFS
Hardware Design Specification
(*1) “Coresight” is an abbreviation of “Coresight debug port”.
3.1.10 MD[14:13] Pins-Frequency Mode Setting
These pins select the frequency mode. A crystal oscillator (Y2: 20 MHz) is mounted on the Tethys board. Do not change the
initial setting at shipment (MD14 = 0, MD13 = 0).
MD14
MD13
EXTAL
EXTAL
PLL0 Multiplication
PLL1 Multiplication
Frequency
Divider
Ratio
Ratio
20 MHz
×1
×80
×78
×50
VCO = 1600 MHz
VCO = 1560 MHz
VCO = 1000 MHz
×60
×60
×56
VCO = 1560 MHz
VCO = 1560 MHz
VCO = 1456 MHz
×52
×52
×50
VCO = 1560 MHz
VCO = 1560 MHz
VCO = 1500 MHz
26 MHz
×1
PLL3 Multiplication Ratio
Prohibited
setting
30 MHz
×1
3.1.11 Initial Values of Mode Setting Pins on Tethys Board
The following table shows the Initial Values of Mode Setting Pins on the Board, and how the individual mode pins are set:
MD Pins
Initial
Initial Function
Setting Method
Value
MD0
Set by a dip switch
MD[3:1]
010
Boot from the QSPI(48.75 MHz/16-Kbyte
Set by a dip switch
transfer)
MD4
CS0 space size (64 Mbytes)
Set by a dip switch
MD5
Set by a dip switch
MD[7:6]
01
Cortex-A7 boot
Set by a dip switch
MD8
CS0 space data bus width (16 bits)
Set by a dip switch
MD9
Crystal resonator is used.
Set by a dip switch
MD10, MD[21:20], MD11,
0,10,0,00
JTAG = Coresight
Set by a dip switch
MDT[1:0]
MD[14:13]
ASD-B-16-0247 Rev1.0
Nov 29, 2016
SDHI1 and SDHI2 = Normal function
00
Input frequency = 20 MHz
Set by a dip switch
Page 17 of 102
RTK00V2XRC7746SFS
Hardware Design Specification
3.2 DDR3-SDRAM Interface (DBSC)
3.2.1
Specifications
The Tethys board incorporates two 4-Gbit DDR3-SDRAMs (16-bit bus width) and operates at a maximum speed of
DDR3-1000. The Tethys board can support memory size up to 2GB (8-Gbit memory x 2) and the data bus width is 32 bits x1. The
DDR3-SDRAMs are allocated to the address space from H'01_0000 0000 to H'01_FFFF FFFF in the R-CarW2H. The address ranges
from H'00_40000000 to H'00_BFFF FFFF can be accessed by default as a mirror area of H'01_0000 0000 to H'01_7FFF FFFF.
Table 4
DDR3-SDRAM Interface Specifications
Controller
On-chip external bus controller for DDR3-SDRAM (DBSC) in the R-Car W2H
Product name
MT41K256M16HA-125 AAT:E from Micron
DDR3-1600 (x 16 bits, 4 Gbits) x 2 pcs
Power supply voltage
1.50 V
Capacity
H'01_0000 0000 to H'01_FFFF FFFF
Bus width
32-bit data bus
Memory bus frequency(R-Car W2H Spec.)
DDR3-1000
3.2.2
Signal Connections between R-Car W2H and DDR3-SDRAMs
Table 5
R-Car W2H
Signal Connections between R-Car W2H and DDR3-SDRAMs
DDR3-SDRAM (U3)
DDR3-SDRAM (U4)
D[31:16]
D[15:0]
M0DQ[31:16]
DQ[15:0]
--
M0DQ[15:0]
--
DQ[15:0]
M0A[15:0]
A[15:0]
←
M0BA[2:0]
BA[2:0]
←
M0CK1、M0CK1#
CK、CK#
--
M0CK0、M0CK0#
--
CK、CK#
MCKE1
CKE
--
MCKE0
--
CKE
M0CS1#
CS#
--
M0CS0#
--
CS#
M0WE#
WE#
←
M0RAS#
RAS#A
←
M0CAS#
CAS#
←
M0DQS3、M0DQS3#
UDQS、UDQS#
--
M0DQS2、M0DQS2#
LDQS、LDQS#
--
M0DQS1、M0DQS1#
--
UDQS、UDQS#
ASD-B-16-0247 Rev1.0
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RTK00V2XRC7746SFS
Hardware Design Specification
M0DQS0、M0DQS0#
--
LDQS、LDQS#
M0DM3、M0DM2
UDM、LDM
--
M0DM1、M0DM0
--
UDM、LDM
M0ODT1
ODT
--
M0ODT0
--
ODT
M0RESET#
RESET#
←
3.2.3
Block Diagram
M0DQ[31:0]
22
M0A[15:0]
22
M0BA[2:0]
A[15:0]
BA[2:0]
22
22
M0RAS#
M0CAS#
DQU[7:0]
CAS#
22
VREFCA
VREFDQ
CS#
22
M0ODT0
ODT
M0CK0
M0CK0#
CK
CK#
M0DQS[1:0]
M0DQS[1:0]#
DQS
DQS#
M0DM[1:0]
DM
20K
CKE
0.1uF
M0CKE0
RESET#
20K
22
M0CS0#
0.1uF
100
D1.5V
MT41K256M16H
A-125 AAT:E
WE#
M0WE#
M0RESET#
DQL[7:0]
RAS#
51
0.1uF
DQL[7:0]
22
M0CS1#
M0DQS[3:2]
M0DQS[3:2]#
M0DM[3:2]
R-CarW2H
DQU[7:0]
CS#
DQS
DQS#
DM
DDR3
22
22
M0CKE1
M0ODT1
M0CK1
M0CK1#
CKE
ODT
CK
CK#
M0ZQ
240
51
0.1uF
M0BKPRST
M0BKPRST#
D1.5V
20K
0.1uF
20K
0.1uF
0.1uF
20K
0.1uF
0.1uF
20K
0.1uF
M0VREFDQ1
M0VREFDQ0
M0VREFCA
D1.5V
M0ZQ
120
Figure 2
ASD-B-16-0247 Rev1.0
Nov 29, 2016
Block Diagram of the DDR3-SDRAM Interface
Page 19 of 102
RTK00V2XRC7746SFS
Hardware Design Specification
3.3 SPI-Flash Interface (QSPI)
3.3.1
Specifications
The Tethys board incorporates 512-Mbit and 32-Mbit SPI flash memory devices manufactured by Spansion. These flash memory
devices are connected to the QSPI of the R-CarW2H’s pin of (GP1_21/QSPI0_SSL/WE1#). And the connection is controlled by
SW9 When the 512-Mbit SPI flash memory is to be assessed, set SW9 pin 3 and 6 short, and when the 32-Mbit SPI flash memory is
to be accessed, set SW9 pin 4 and 8 short. Do not short them at the same time.
Table 6
SPI-Flash Interface Specifications
Flash memory interfaces
QSPI0 and QSPI1 in the R-Car W2H
QSPI0 devices
U5:S25FL512SAGMFIG11 (512 Mbits, 8-/16-bit data width) from Spansion ×1 pcs
U6:S25FL132K0XMFI011(32Mbits, 8-/16-bit data width) from Spansion ×1 pcs
Operating voltage
D3.3 V_FLASH = 3.3V
Capacity
512-Mbit and 32-Mbit
Mapping area (512-Mbit)
0x0000000~0x3ffffff
Mapping area (32-Mbit)
0x0000000~0x3fffff
3.3.2
Block Diagram
GP1_20/QSPI0_IO3/RD#
GP1_19/QSPI0_IO2/CS0#
SPI FLASH
S25FL132K0XMFI011
32Mbit
U6
QSPI_IO3
D3.3V_FLASH
HOLD#/IO3
QSPI_IO2
W#/ACC/IO2
QSPI_SO/IO1
GP1_18/QSPI0_MISO/QSPI0_IO1/RD/WR#
SI/IO1
QSPI_SI/IO0
GP1_17/QSPI0_MOSI/QSPI0_IO0/BS#
SI/IO0
QSPI_CLK
GP1_16/QSPI0_SPCLK/WE0#
GP1_21/QSPI0_SSL/WE1#
QSPI
CLK
CS#
SW9
R-Car W2H
SPI FLASH
S25FL512SAGMFIG11
512Mbit
U5
D3.3V_FLASH
DQ3
DQ2
DQ1
DQ0
CLK
CS#
Figure 3
ASD-B-16-0247 Rev1.0
Nov 29, 2016
Block Diagram of the SPI-Flash Interface
Page 20 of 102
RTK00V2XRC7746SFS
Hardware Design Specification
3.4 Audio Codec Interfaces (SSI0, SSI1)
3.4.1
Specifications
The Tethys board incorporates an audio codec (AK4642EN, U29) which is connected to SSI0 and SSI1 of the R-Car W2H. For
details on the SSI, see the R-CarW2H Hardware Manual. For details on the AK4642EN, see the datasheet published by Asahi Kasei
Micro devices.
Table 7
Controller
SSI Codec Specifications
On-chip SSI0and SSI1 in the R-CarW2H
AK4642EN (U29) from AKM
Audio codec
I2C bus : Interface 1
I2C slave address: 0x25 for read, 0x24 for write (CAD0= 0)
Master/slave mode
AK4642EN: Master/slave selectable(slave mode by default)
Audio connector
MIC IN (J1)
LINE-OUT( J1)
3.4.2
Block Diagram
LOUT
J1
Line Out
LRCK
GP5_9/SSI_SCK0129_A
ROUT
BICK
GP5_10/SSI_WS0129_A
GP5_11/SSI_SDATA0_A
SDTI
RIN1/IN1+
GP5_21/SSI_SDATA1_A
2K 1%
J1
MIC In
MPWR
SDTO
LIN1/IN1-
22
GP5_28/AUDIO_CLKA_A
MCKO
CSN/CAD0
U1
R-Car W2H
U29
AUDIO
AK4642EN
I2C Buffer
LTC4313IMS81#PBF
MCK
Figure 4
ASD-B-16-0247 Rev1.0
Nov 29, 2016
X3
12.288MHz
Block Diagram of the Audio Codec Interface
Page 21 of 102
RTK00V2XRC7746SFS
Hardware Design Specification
3.5
3.5.1
eMMC Memory Interface (eMMC)
Specifications
The Tethys board incorporates an eMMC memory SDIN8DE1-8G-XA manufactured by SanDisk that is connected to the on-chip
MMC interface of the R-CarW2H.For details on the MMC, see the R-CarW2H Hardware Manual.
Table 8
eMMC Memory Interface (eMMC) Specifications
MMC controller
On-chip MMC in the R-Car W2H
Interface voltage control
D3.3V_eMMC=3.3V
eMMC memory
SDIN8DE1-8G-XA(U7) from SanDisk
Capacity:8GB
3.5.2
Block Diagram
D3.3V_eMMC
10K
D3.3V_eMMC
MMC_CLK
R-Car W2H
CLK
VCC
MMC_CMD
CMD
VCCQ
MMC_D[7:0]
DATA[7:0]
eMMC
Figure 5
ASD-B-16-0247 Rev1.0
Nov 29, 2016
D3.3V
VCCQ_MMC
Block Diagram of the eMMC Memory Interface
Page 22 of 102
RTK00V2XRC7746SFS
Hardware Design Specification
3.6
SD Card Host Interface (SDHI2)
3.6.1
Specifications
The Tethys board incorporates a SD card slot (CN2) and a mini-PCI Express CN (CN12) for the on-chip SD card host interface
(SDHI2) of the R-CarW2H. For details on the SDHI2, please refer to the R-CarW2H hardware manual. CN12 and CN2 can not be
used at the same time.
Table 9
Specifications of SD Card Host Interface (SDHI2)
SD Host Interface
On-chip SDHI2 in the R-Car W2H
Voltage control for VDD
VCCQ_SD2 =3.3V/1.8V it can be switched by software , D3.3V=3.3V
SD Card Slot
503182-1852(CN2) from Molex
3.6.2
Block Diagram
D3.3V
VCCQ_SD2
47K
22
SD2_CLK
CLK
D3.3V
33
DATA[3:0]
SD2_DATA[3:0]
33
R-Car W2H
SDHI2
SD2_WP
WP
SD Slot
CN2
33
SD2_CD
CD
33
SD2_CMD
Figure 6
ASD-B-16-0247 Rev1.0
Nov 29, 2016
CMD
Block Diagram of the SDHI2 Interface
Page 23 of 102
RTK00V2XRC7746SFS
Hardware Design Specification
3.7
Mini PCI Express Interface
3.7.1
Specifications
The Tethys board incorporates four mini PCIE interface manufactured by TE. One Mini-PCI Express CN(CN9) is connected to
SDHI0, GPIO, SCIF0 and the HSCIF0 of the R-CarW2H, another Mini-PCI Express CN(CN12) is connected to SDHI2, GPIO,
SCIF3 and the HSCIF2 of the R-CarW2H, and the third Mini-PCI Express CN(CN8) is connected to the Ether MAC/EtherAVB,
GPIO and the HSCIF1 of the R-CarW2H, The fourth Mini-PCI Express CN(CN11) acts as a standard Mini-PCI Express signal
connector and transmits the standard Mini-PCI Express signals. There are also USB 2.0 signals and 1pps signal connected to the mini
PCIE connectors.
3.7.2
3.7.2.1
The Mini PCIE connector signal configuration are shown as below:
CN9 of figure 7 signal assignments are shown as below:
Pin NO.
Signal
I/O
Remark
Pin NO.
Signal
I/O
Remark
C2X0_DCMODE
GPIO
D3.3V
PO
Power
N.C.
GND
Power
PCIE_5.0V
PO
Power
PCIE_5.0V
PO
Power
C2X0_RESETB
GPIO
GPS_1PPS/
I/O
GPS 1PPS input
C2X0_GPIO_B3
or GPIO
GND
Power
10
C2X0_GPIO_B2
I/O
GPIO
11
RX0_D/
UART from CPU
12
C2X0_GPIO_B1
I/O
GPIO
14
C2X0_GPIO_B0
I/O
GPIO
16
C2X0_STATE
C2X state
C2X_RXD
13
TX0_D/
or USB2UART
C2X_TXD
UART from CPU
or USB2UART
15
GND
17
N.C.
18
GND
Power
19
N.C.
20
C2X0_GPIO_A6
I/O
GPIO
21
GND
Power
22
C2X0_GPIO_A5
I/O
GPIO
23
HRX0_B
UART from CPU
24
PCIE_5.0V
PO
Power
25
HTX0_B
UART from CPU
26
GND
Power
27
GND
Power
28
PCIE_5.0V
PO
Power
29
GND
Power
30
C2X0_GPIO_A4
I/O
GPIO
31
MD10/HCTS0#
I/O
UART from CPU
32
C2X0_GPIO_A3
I/O
GPIO
33
MD11/HRTS0#
I/O
UART from CPU
34
GND
Power
35
GND
Power
36
N.C
37
SD0_CLK
SD0 clock
38
N.C
39
SD0_WP
SD0 write protect
40
GND
Power
41
SD0_CD
SD0 card detect
42
C2X0_GPIO_A2
I/O
GPIO
ASD-B-16-0247 Rev1.0
Nov 29, 2016
Power
Page 24 of 102
RTK00V2XRC7746SFS
Hardware Design Specification
43
SD0_DATA3
I/O
SD0 data3
44
C2X0_GPIO_A1
I/O
GPIO
45
SD0_DATA2
I/O
SD0 data2
46
C2X0_GPIO_A0
I/O
GPIO
47
SD0_DATA1
I/O
SD0 data1
48
PCIE_5.0V
PO
Power
49
SD0_DATA0
I/O
SD0 data0
50
GND
Power
51
SD0_CMD
I/O
SD0 command
52
D3.3V
PO
Power
3.7.2.2
Pin NO.
CN12 of figure 7 signal assignments are shown as below:
Signal
I/O
Remark
Pin
Signal
I/O
Remark
D3.3V
PO
Power
GND
Power
NO.
C2X1_DCMODE
GPIO
N.C.
PCIE_5.0V
PO
Power
PCIE_5.0V
PO
Power
C2X1_RESETB
GPIO
GPS_1PPS/
I/O
GPS 1PPS input
C2X1_GPIO_B3
or GPIO
GND
Power
10
C2X1_GPIO_B2
I/O
GPIO
11
RX3_B
UART from CPU
12
C2X1_GPIO_B1
I/O
GPIO
13
TX3_B
UART from CPU
14
C2X1_GPIO_B0
I/O
GPIO
15
GND
Power
16
C2X1_STATE
C2X state
17
N.C.
18
GND
Power
19
N.C.
20
C2X1_GPIO_A6
I/O
GPIO
21
GND
Power
22
C2X1_GPIO_A5
I/O
GPIO
23
HRX2
UART from CPU
24
PCIE_5.0V
PO
Power
25
HTX2
UART from CPU
26
GND
Power
27
GND
Power
28
PCIE_5.0V
PO
Power
29
GND
Power
30
C2X1_GPIO_A4
I/O
GPIO
31
HCTS2#
I/O
UART from CPU
32
C2X1_GPIO_A3
I/O
GPIO
33
HRTS2#
I/O
UART from CPU
34
GND
Power
35
GND
Power
36
USB1_DM3
I/O
USB data
negative
37
SD2_CLK
SD0 clock
38
USB1_DP3
I/O
USB data
positive
39
SD2_WP
SD0 write protect
40
GND
Power
41
SD2_CD
SD0 card detect
42
C2X1_GPIO_A2
I/O
GPIO
43
SD2_DATA3
I/O
SD0 data3
44
C2X1_GPIO_A1
I/O
GPIO
45
SD2_DATA2
I/O
SD0 data2
46
C2X1_GPIO_A0
I/O
GPIO
47
SD2_DATA1
I/O
SD0 data1
48
PCIE_5.0V
PO
Power
49
SD2_DATA0
I/O
SD0 data0
50
GND
Power
51
SD2_CMD
I/O
SD0 command
52
D3.3V
PO
Power
ASD-B-16-0247 Rev1.0
Nov 29, 2016
Page 25 of 102
RTK00V2XRC7746SFS
Hardware Design Specification
3.7.2.3
CN8 of Figure 7 signal assignments are shown as below:
Pin NO.
Signal
I/O
Remark
Pin NO.
Signal
I/O
Remark
AVB_TX_ER
Transmit error signal
D3.3V
PO
Power
AVB_MDIO
I/O
Management information
GND
Power
transmit/receive data
PCIE_5.0V
PO
Power
PCIE_5.0V
PO
Power
AVB_GPIO6
I/O
GPIO
ETH_CRS_DV/
Receive data
(AVB_CRS)
GND
AVB_RX_DV
Power
10
ETH_RX_ER/
enable signal
AVB_RXD3
11
AVB_PHY_INT
PHY interrupt signal
12
ETH_TXD0/
signal
AVB_RX_ER
13
AVB_MDC
Management information
14
transfer clock signal
15
GND
Power
ETH_RXD1/
ETH_MDIO/
Reception error
signal
AVB_RXD1
16
Receive data
Receive data
signal
AVB_RXD2
Receive data
signal
17
AVB_TX_CLK
Transmit clock signal
18
GND
Power
19
C2X1_RESETB/
GMII transmit clock signal
20
ETH_REF_CLK/
Receive clock
AVB_GTX_CLK
AVB_RX_CLK
21
GND
23
HRX1_A
25
HTX1_A
27
C2X1_GPIO_A1/
Power
signal
22
AVB_RESETn
GPIO
High speed uart
24
PCIE_5.0V
PO
Power
High speed uart
26
GND
Power
Transmit data signal
28
PCIE_5.0V
PO
Power
Transmit data signal
30
GTXREFCLK
GMII reference
AVB_TXD7
29
C2X1_GPIO_B0/
AVB_TXD6
31
HCTS1#_A
clock signal
I/O
High speed uart
32
ETH_RXD0/
AVB_RXD0
Receive data
signal
33
HRTS1#_A
I/O
High speed uart
34
GND
Power
35
C2X1_GPIO_B1/
Receive data signal
36
USB1_DM2
I/O
USB data
AVB_TXD5
37
AVB_TXD3
negative
Transmit data signal
38
USB1_DP2
I/O
USB data
positive
39
AVB_TXD0
Transmit data signal
40
GND
Power
41
AVB_TXD1
Transmit data signal
42
AVB_GPIO5
I/O
GPIO
I/O
GPIO
(AVB_RXD7)
43
AVB_TXD2
Transmit data signal
44
ETH_TX_EN/
AVB_GPIO3
ASD-B-16-0247 Rev1.0
Nov 29, 2016
Page 26 of 102
RTK00V2XRC7746SFS
Hardware Design Specification
(AVB_RXD6)
45
C2X1_GPIO_B2/
Transmit data signal
46
AVB_TXD4
47
ETH_LINK/
AVB_GPIO4
I/O
GPIO
(AVB_COL)
I/O
GPIO
48
PCIE_5.0V
PO
Power
I/O
GPIO
50
GND
Power
GPIO
52
D3.3V
PO
Power
AVB_GPIO1
(AVB_RXD4)
49
ETH_TXD1/
AVB_GPIO2
(AVB_RXD5)
51
3.7.2.4
AVB_TX_EN
CN11 of figure 7 signal assignments are shown as below:
Pin NO.
Signal
I/O
N.C
Pin NO.
Signal
I/O
Remark
D3.3V
PO
Power
N.C
GND
Power
N.C
D1.5V
PO
Power
N.C
N.C
GND
Power
10
N.C
11
PCIe_CLKN
PCIe clock minus
12
N.C
13
PCIe_CLKP
PCIe clock plus
14
N.C
15
GND
Power
16
N.C
17
N.C
18
GND
19
N.C
20
N.C
21
GND
Power
22
N.C
23
PCIe_RXN
PCIe receive data minus
24
D3.3V
PO
Power
25
PCIe_RXP
PCIe receive data plus
26
GND
Power
27
GND
Power
28
D1.5V
PO
Power
29
GND
Power
30
I2C1-SCL
I/O
I2C clock
31
PCIe_TXN
PCIe transmit data minus
32
I2C1-SDA
I/O
I2C data
33
PCIe_TXP
PCIe transmit data plus
34
GND
Power
35
GND
Power
36
USB1_DM4
I/O
USB data negative
37
N.C
38
USB1_DP4
I/O
USB data positive
39
N.C
40
GND
Power
41
N.C
42
N.C
43
N.C
44
N.C
45
N.C
46
N.C
47
N.C
48
D1.5V
PO
Power
49
N.C
50
GND
Power
ASD-B-16-0247 Rev1.0
Nov 29, 2016
Remark
Power
Page 27 of 102
RTK00V2XRC7746SFS
Hardware Design Specification
51
3.7.3
N.C
52
D3.3V
PO
Power
Block Diagram
SDHI0
Mini PCI
Express CN
TE
CN9
GPIO
SCIF0/HSCIF0
1PPS
USB 2.0
SDHI2
R-car W2H
Mini PCI
Express CN
TE
CN12
GPIO
SCIF3/HSCIF2
1PPS
USB 2.0
EtherAVB
Mini PCI
Express CN
TE
CN8
GPIO
HSCIF1
USB 2.0
Mini PCI
Express CN
TE
CN11
PCIe
I2C
Figure 7
ASD-B-16-0247 Rev1.0
Nov 29, 2016
Block Diagram of Mini PCI Express Interface
Page 28 of 102
RTK00V2XRC7746SFS
Hardware Design Specification
3.8
3.8.1
USB to UART
Specifications
The Tethys board incorporates three USB to UART bridges: One is connected to a mini PCIE connector, one is connected to
the R-CarW2H and another is connected to the MCU. Users can control and debug the Tethys board through the USB port.
Table 10
USB controller
USB to UART Specifications
On-chip SCIF2(debug) function controller in the R-Car W2H, MCU，
and Mini PCI express CN
USB to UART IC
CP2102-GM from Silicon
USB function connector
47346-0001 from Molex x
Common mode filter with ESD protection diode
3.8.2
PRTR5V0U2X from NXP
3pcs
3pcs
Block Diagram
ESD protection
PRTR5V0U2X
D22
Mini PCI
Express CN
TE
USB to UART
CP2102
Silicon
USB micro-B CN
CN10
ESD protection
PRTR5V0U2X
D24
R-car W2H
USB to UART
CP2102
Silicon
SCIF2
(debug)
USB micro-B CN
CN5
ESD protection
PRTR5V0U2X
D23
USB to UART
CP2102
Silicon
MCU
Figure 8
ASD-B-16-0247 Rev1.0
Nov 29, 2016
USB micro-B CN
CN16
Block Diagram of the USB to UART
Page 29 of 102
RTK00V2XRC7746SFS
Hardware Design Specification
3.9 USB2.0 Interface
3.9.1
Specifications
The Tethys board incorporates two A Type USB Connectors for the USB2.0 host interface. The USB0 of the R-CarW2H is
connected to a USB 2.0 type A port directly. The USB1 of the R-CarW2H is connected to the GL852GT which manufactured by
Genesys to expand 4 USB 2.0. The expand 1 port of the GL852GT is connected to a USB 2.0 type A port. There is a switch IC for
the two USB ports’ power supply. The other 3 USB port of the GL650USB are connected to the three of four mini PCIE connectors
separately.
Table 11
USB2.0 Interface
USB controller
On-chip
USB2.0 function controller in the R-Car W2H
USB Power Switch
BD2066FJ-LBE2 from ROHM
USB host connector x 2
On-chip USB2.0 interface1 in the R-Car W2H
1759546-1 from TE x 2
USB
Hub
Common mode filter with ESD protection diode
ASD-B-16-0247 Rev1.0
Nov 29, 2016
GL852GT-MNGXX from Genesys
PRTR5V0U2X from NXP
Page 30 of 102
RTK00V2XRC7746SFS
Hardware Design Specification
3.9.2
Block Diagram
D3.3V
D3.3V
1K
1K
10K
CTRLA
FLAGA
OVCUR1
PWRENB1
CTRLB
FLAGB
D3.3V
BD2066FJ
-LBE2
10K
ESD Protection
PRTR5V0U2X
D1
10K
GND
D+
DVBUS
USB 2.0-H
type-A CN 2
in1
1775468-1
TE
GND CN1
D+
DVBUS
USB0_DP
USB0_DM
USB0_PWEN
USB0_OVC
USB 2.0
USB1_DP
USB1_DM
USB1_PWEN
USB1_OVC
DP0
DM0
DP1
DM1
OVCUR1# OVCUR1
PWRENB1# PWRENB1
D3.3V
10K
ESD Protection
PRTR5V0U2X
D2
R-car W2H
DP2
DM2
OVCUR1#
PWRENB1#
Mini PCI
Express CN
TE CN8
GL852GT
12M
SYS_RESETn_33
Figure 9
ASD-B-16-0247 Rev1.0
Nov 29, 2016
DP3
DM3
OVCUR1#
PWRENB1#
Mini PCI
Express CN
TE CN12
DP4
DM4
OVCUR1#
PWRENB1#
Mini PCI
Express CN
TE CN11
RESET
Block Diagram of the USB2.0 Interface
Page 31 of 102
RTK00V2XRC7746SFS
Hardware Design Specification
3.10
Debug Interface
The JTAG connector can be found in the debug sub board including CPU Debug connector,JTAG debug connector and MCU
JTAG connector through 26 pin FPC (CN4) connector.
3.10.1 CPU debug
3.10.1.1 Specifications
The R-CarW2H incorporates three debugger interfaces: one is a 26-pin connector (DBG) incorporates ARM core and Real-time
processing core for connection to the JTAG emulator, one USB-B connector and the third EtherMAC for connection to the host PC.
The SW3 and SW12 switch 2-3 short is for normal operation and 2-1 short for CPU JTAG Debug.
On the Tethys board, the SCIF2 of the R-CarW2H are used as debug serial interfaces by connecting the USB-B connector to
the host PC through a USB cable. The SCIF2 of the R-CarW2H is connected to the USB-B connector via the USB to UART Bridge
CP2102. The R-CarW2H incorporates the EtherMAC that supports 100Base-T or 10Base-T compliant with IEEE 802.3u. On the
Tethys board, the EtherMAC signals are connected to the RMII PHY interface (KSZ8041RNLI) manufactured by Micrel.
Table 12
Control
Interface
CPU debug Specifications
CPU JTAG Debug.
Debug Interface
CN4: IMSA-9632S-26Y801 from IRISO
operating conditions
SW3 and SW12 switch 2-1 short
3.10.1.2 Block Diagram
D1.8V
D1.8V
4.7K
SW3,SW12
TCK, TDI, TMS
4.7K
1K
TCK
TRST_N
TMS
TDI
TDO
ASEBRK
DUI
TRST
JTAG CN
CN4
D3.3V
PRESETn
ETH_LINK
4.7K
GP5_8/SSI_SDATA7_A/IRQ8/
AUDIO_CLKA_D/CAN_CLK_D
INTRP
LED0
LED1
TX+
R-Car W2H
RMII
RJ45
CN3
TX-
EtherMAC
RX+
RXKSZ8041RNLI
D3.3V
49.9
100nF
10K
CP2102
TX2_B
TXD
VBUS
RXD
DP
DM
SCIF2
RX2_B
Figure 10
ASD-B-16-0247 Rev1.0
Nov 29, 2016
USB micro-B CN
CN5
Block Diagram of the CPU debug
Page 32 of 102
RTK00V2XRC7746SFS
Hardware Design Specification
3.10.2 CPU JTAG2 debug
3.10.2.1 Specification
On the Tethys board, the R-CarW2H has the CPU JTAG2 debug interface. The SW12 switch 2-3 short is for normal operation
and 2-1 short for CPU JTAG2 debug
Table 13
Control
Interface
CPU JTAG2 debug
CPU JTAG2
Debug Interface
CN4: IMSA-9632S-26Y801 from IRISO
operating conditions
The SW12 switch 2-1 short
The SW1 switch 9-8 short, switch 10-7 short
The SW2 switch 8-1 short, switch 7-2 short, switch 6-3 short, switch 5-4 short
3.10.2.2 Block Diagram
D1.8V
D1.8V
10K
10K
JTAG CN
CN4
10K
SW1
R-Car W2H
U1
SW12
GP0_14/MMC0_CMD
GP0_13/MMC0_CLK
10
MMC0_CLK_TDO
GP0_18/MMC0_D3
MMC0_D3_ASEBRK#/ACK
GP0_17/MMC0_D2
MMC0_D2_TDI
GP0_16/MMC0_D1
MMC0_D1_TMS
GP0_15/MMC0_D0
MMC0_D0_TCK
Figure 11
ASD-B-16-0247 Rev1.0
Nov 29, 2016
MMC0_CMD_TRST
SW2
Block Diagram of the CPU JTAG2 (SH-4AL) debug
Page 33 of 102
RTK00V2XRC7746SFS
Hardware Design Specification
3.10.3 MCU debug
3.10.3.1 Specifications
On the Tethys board, the RH850 F1H / F1L has the JTAG interface and provides the serial programming function. The serial
programming function is used to test the connection between the devices mounted on the printed-circuit board. The SW17 switch 2-3
short is for normal operation and 2-1 short for MCU Debug.
Table 14
Control
Interface
MCU debug Specification
MCU Debug
Debug Interface
CN4: IMSA-9632S-26Y801 from IRISO
operating conditions
The SW17 switch 2-1 short for MCU Debug
3.10.3.2 Block Diagram
BU3.3V
BU3.3V
4.7K
SW17
4.7K
1K
DCUTRST
DCUTCK
RH850F1H/F1L
DCUTMS
DCUTDI
JTAG CN
CN4
DCUTDO
Figure 12
ASD-B-16-0247 Rev1.0
Nov 29, 2016
Block Diagram of the MCU debug
Page 34 of 102
RTK00V2XRC7746SFS
Hardware Design Specification
3.11 GYRO/G-SENSOR
3.11.1 Specifications
The A3G4250D manufactured by ST is a low-power 3-axis angular rate sensor able to provide unprecedented stability at zero
rate level and sensitivity over temperature and time. The AIS328DQ is an ultra low-power high performance 3-axis linear
accelerometer. The CPU communicates with the A3G4250D and AIS328DQ through its I2C1 and GPIOs.
Table 15
GYRO/G-SENSOR Specifications
Controller
R-car W2H
Control
The A3G4250D and AIS328DQ from ST
Interface
Supply voltage
D3.3V=3.3V
3.11.2 Block Diagram
D3.3V
10K
SDO/SA0
CS
SCL1
SCL
SDA1
SDA
GYRO
A3G4250D
GP4_22
DRDY/INT2
GP4_23
INT1
R-car W2H
SDO/SA0
CS
SCL
SDA
Figure 13
ASD-B-16-0247 Rev1.0
Nov 29, 2016
GP4_24
INT1
GP4_25
INT2
G-SENSOR
AIS328DQ
Block Diagram of the GYRO/G-SENSOR
Page 35 of 102
RTK00V2XRC7746SFS
Hardware Design Specification
3.12 I2C Interfaces
3.12.1 Specifications
The R-Car W2H incorporates five I2C interfaces (3.3 V). Since the R-Car W2H uses LVTTL-type I/O buffers on I2C interfaces, it
cannot directly drive an I2C bus with a relatively high load capacitance (e.g. 100 pF).
While the above restriction applies to interfaces of the R-Car W2H, the design of the Tethys board calls for multiple I2C devices
being connected to I2C interfaces 1. In order to compensate for the driving ability of the R-Car W2H, the Tethys board incorporates
an LTC4313IMS8-1#PBF I2C buffer manufactured by Linear Technology, through which each I2C device is connected to the I2C
interface for the device.
The following devices are connected to each I2C interface on the Tethys board.
Table 16
I2C
Controller
I2C devices through I2C interface 1
List of I2C Devices
On-chip I2C controllers in the R-CarW2H
Through LTC4313IMS8-1#PBF (U2) from Linear Technology
U17: 24LC64EST from Microchip
ASD-B-16-0247 Rev1.0
Nov 29, 2016
U28:
A3G4250D from ST
U29:
AK4642EN from AKM
U30:
AIS328DQ from ST
U32:
RH850F1H/F1L from Renesas
CN11:
1759546-1 from TE for PCIE Express
CN14:
HTST-103-04-S-D-RA from Samtec for HSM
Page 36 of 102
RTK00V2XRC7746SFS
Hardware Design Specification
3.12.2 List of Slave Addresses
The table below lists the slave addresses of the I2C devices on the Tethys board
Table 17
List of I2C Slave Addresses
Slave Addresses
I2C
Ux/CNx
Device
Binary
Note
Hexadecimal
Interfaces
SA7
SA6
SA5
SA4
SA3
SA2
SA1
R/W#
RD
WR
0xA1
0xA0
*1
I2C EEPROM for
U17
24LC64EST
MAC address
U28
A3G4250D
GYRO
0xD7
0xD6
*2
U29
AK4642EN
AUDIO
0x25
0x24
*3
U30
AIS328DQ
G-SENSOR
0x33
0x32
*4
U32
RH850F1H/F1L
MCU
--
--
--
--
--
--
--
--
--
--
*5
CN11
Mini PCIE
Connector
--
--
--
--
--
--
--
--
--
--
CN14
HSM CN
Connector
--
--
--
--
--
--
--
--
--
--
Note:
*1 Pins 3 to 1 (A [2:0]) = GND
*2 Pin 8 to 12 (RESERVED [5:1]) = GND
*3 Pin 8 (CSN/CAD0) = GND
*4 Pin 25(EP) and Pin 4 (RESERVED1) = GND
*5 I2C no use
3.12.3 Block Diagram
D3.3V
U1
R-Car W2H
2K
1%
U29
AK4642EN
D3.3V
2K
1%
2K
1%
2K
1%
U17
24LC64EST
SCL
SCL1_A
SDA1_A
U28
A3G4250D
SDA
SCL
SDA
SCL
SDA
CN11
Mini PCIE
U30
AIS328DQ
SCL
SDA
U32
RH850F1H/F1L
SCL
SDA
CN14
HSM CN
SCL
SDA
SCL
33
U2
LTC4313IMS8-1#PBF
Figure 14
ASD-B-16-0247 Rev1.0
Nov 29, 2016
Block Diagram of the I2C Interfaces
Page 37 of 102
SDA
33
RTK00V2XRC7746SFS
Hardware Design Specification
3.13 GPS Module
3.13.1 Specifications
The NEO-7P /7M/M8L manufactured by UBLOX is a high performance GPS module. It has high performance active antenna.
It communicates with the CPU through the SCIF5 interface.
3.13.2 Block Diagram
GPS
Antenna
CN7
U.FL-R-SMT
Hirose
Figure 15
ASD-B-16-0247 Rev1.0
Nov 29, 2016
GPS Receiver Module
NEO-7P/7M/M8L
TXD
RXD
SCIF5
R-Car W2H
Block Diagram of the GPS module
Page 38 of 102
RTK00V2XRC7746SFS
Hardware Design Specification
3.14 CAN and Flexray Interface
3.14.1 Specifications
On the Tethys board, there are three CAN bus, one is connected to the R-CarW2H, and another two are connected to the MCU.
The high speed CAN driver TJA1050 manufactured by NXP is used for the two CAN bus.
On the Tethys board, there are one Flexray bus connected to the MCU. The high speed Flexray driver TJA1082 manufactured
by NXP is used for the Flexray bus.
Table 18
CAN and Flexray Interface Specifications
Controller
R-Car W2H and RH850F1H/F1L， if mounting RH850F1L, not Flexray function
Control
CN6: HTST-105-04-S-D-RA from Samtec
Interface
CAN Transceiver Interface
TJA1050 from NXP
Flexray Transceiver Interface
TJA1082 from NXP
3.14.2 Block Diagram
R-car W2H
CPU
U1
CAN transceiver
TJA1050
NXP
U19
CAN transceiver
TJA1050
NXP
U21
RH850F1H/F1L
MCU
U32
CN6
10 pin 2.54 pitch
connector
HTST-105-04-S-D-RA
CAN transceiver
TJA1050
NXP
U23
Flexray transceiver
TJA1082
NXP
U47
Figure 16
ASD-B-16-0247 Rev1.0
Nov 29, 2016
Block Diagram of the CAN and Flexray Interface
Page 39 of 102
RTK00V2XRC7746SFS
Hardware Design Specification
The 10 pin connector (CN6) pin assignment is shown as below:
CN6 PIN Number
Signal
Remark
CPU_CAN0_H
HIGH-level CAN bus line
CPU_CAN0_L
LOW-level CAN bus line
MCU_CAN0_H
HIGH-level CAN bus line
MCU_CAN0_L
LOW-level CAN bus line
MCU_CAN1_H
HIGH-level CAN bus line
MCU_CAN1_L
LOW-level CAN bus line
BP
Flexray bus line plus
BM
Flexray bus line minus
GND
Ground
10
GND
Ground
ASD-B-16-0247 Rev1.0
Nov 29, 2016
Page 40 of 102
RTK00V2XRC7746SFS
Hardware Design Specification
3.15 LEDs and Switches
3.15.1 Specifications
The Tethys board incorporates four bits of tactile switches, and four bits of LEDs (eight LEDS for 4 GPIO place both top and
bottom side of the PCB) for debugging and status indication. They are connected to the GPIO pins of the R-CarW2H. Besides, there
are two LEDS control by the GPS 1PPS signal to indicate the GPS work status. The LED controlled by R-CarW2H port and GPS
1PPS signal correspondingly is shown as the table below,
LED
R-CarW2H PORT
Color
D3&D4
GP5_4
Green
D5&D6
GP5_5
Green
D7&D8
GP5_6
Green
D9&D10
GP5_7
Green
LED
Signal
Color
D11&D12
GPS_1PPS
Green
The tactile switch controlled by R-CarW2H or MCU port correspondingly is shown as the table below,
Tact SW
R-CarW2H or MCU PORT
SW13
GP5_0
SW14
GP5_1
SW15
GP5_2
SW16
GP5_3
SW4
MCU reset
There are other Switches are listed as below:
Table 19
DIP Switch
Description
DIP Switches default setting is as below table
Default setting
Function
ON(Short)
SW1
OFF(Open)
eMMC interface
eMMC
and RL JTAG
SW1:
1-16 short
SW1:
1-16 open
○
Select switch
SW1:
2-15 short
SW1:
2-15 open
○
SW1:
3-14 short
SW1:
3-14 open
○
SW1:
4-13 short
SW1:
4-13 open
○
SW1:
5-12 short
SW1:
5-12 open
○
SW1:
6-11 short
SW1:
6-11 open
○
SW1:
7-10 open
SW1:
7-10 short
○
SW1:
8-9 open
SW1:
8-9 short
○
ASD-B-16-0247 Rev1.0
Nov 29, 2016
JTAG
Page 41 of 102
RTK00V2XRC7746SFS
Hardware Design Specification
SW2
SW5
SW6
SW7
SW8
SW9
MMC interface and
JTAG
eMMC
RL JTAG Select
SW2:
1-8 short
SW2:
1-8 open
○
switch
SW2:
2-7 short
SW2:
2-7 open
○
SW2:
3-6 short
SW2:
3-6 open
○
SW2:
4-5 short
SW2:
4-5 open
○
Mode select switch
Mode=0
Mode=1
MD0
SW5:
1-16 short
SW5:
1-16 open
○
MD1
SW5:
2-15 short
SW5:
2-15 open
○
MD2
SW5:
3-14 short
SW5:
3-14 open
MD3
SW5:
4-13 short
SW5:
4-13 open
○
MD4
SW5:
5-12 short
SW5:
5-12 open
○
MD5
SW5:
6-11 short
SW5:
6-11 open
○
MD6
SW5:
7-10 short
SW5:
7-10 open
○
MD7
SW5:
8-9 short
SW5:
8-9 open
Mode select switch
○
○
Mode=0
Mode=1
MD8
SW6:
1-16 short
SW6:
1-16 open
○
MD9
SW6:
2-15 short
SW6:
2-15 open
○
MD10
SW6:
3-14 short
SW6:
3-14 open
○
MD11
SW6:
4-13 short
SW6:
4-13 open
○
MD13
SW6:
5-12 short
SW6:
5-12 open
○
MD14
SW6:
6-11 short
SW6:
6-11 open
○
MD20
SW6:
7-10 short
SW6:
7-10 open
○
MD21
SW6:
8-9
SW6:
8-9 open
Mode select switch
short
○
Mode=0
Mode=1
MDT0
SW7:
1-4 short
SW7:
1-4 open
○
MDT1
SW7:
2-3 short
SW7:
2-3 open
○
EtherMAC and
EtherMAC
Ether/EtherAVB:
EtherAVB Selected
SW8:
1-8 short
SW8:
1-8 open
○
switch
SW8:
2-7 short
SW8:
2-7 open
○
SW8:
3-6 short
SW8:
3-6 open
○
SW8:
4-5 short
SW8:
4-5 open
○
1.EtherMAC and
EtherMAC
Ether/EtherAVB
EtherAVB
SW9:
1-8 short
SW9:
1-8 open
○
Selected switch
SW9:
2-7 short
SW9:
2-7 open
○
2.512Mbit or
SW9:
3-6 short
SW9:
3-6 open
○
32Mbit SPI
SW9:
4-5 short
SW9:
4-5 open
FLASH Selected
QSPI0(512Mbit) Default
ASD-B-16-0247 Rev1.0
Nov 29, 2016
○
QSPI1 (32Mbit)
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Hardware Design Specification
switch
SW10
SW11
SW9 :
3-6 short
SW9 : 3-6 open
SW9 :
4-5 open
SW9 : 4-5 short
○
EtherMAC and
Ether/EtherAVB
EtherMAC
EtherAVB Selected
SW10:
1-8 open
SW10:
1-8 short
○
switch
SW10:
2-7 open
SW10:
2-7 short
○
SW10:
3-6 open
SW10:
3-6 short
○
SW10:
4-5 open
SW10:
4-5 short
○
EtherMAC and
Ether/EtherAVB
EtherMAC
EtherAVB Selected
SW11:
1-4 open
SW11:
1-4 short
switch
SW11:
2-3 not use
SW11:
2-3 not use
Table 20
Slide Switch
○
○
○
Slide Switches default setting is as below table:
Description
Default setting
Function
ON(Short)
SW3
SW12
SW17
SW18
JTAG Debug/Normal
JTAG Debug
Normal operation
Operation select switch
SW3:
1-2 short
SW3:
1-2 open
SW3:
2-3 open
SW3:
2-3 short
JTAG Debug/Normal
JTAG2 Debug
Normal operation
Operation select switch
SW12:
1-2 short
SW12:
1-2 open
SW12:
2-3 open
SW12:
2-3 short
JTAG Debug/Normal
MCU JTAG Debug
Normal operation
Operation select switch
SW17:
1-2 short
SW17:
1-2 open
SW17:
2-3 open
SW17:
2-3 short
Power switch
○
○
○
○
○
○
System power
ON
ASD-B-16-0247 Rev1.0
Nov 29, 2016
OFF(Open)
OFF
SW18:
2-3 short
SW18:
2-3 open
SW18:
1-2 open
SW18:
1-2 short
○
○
Page 43 of 102
RTK00V2XRC7746SFS
Hardware Design Specification
3.16 Connection between CPU and MCU
3.16.1 Specifications
The Tethys board have a MCU to control the Power sequence and Reset sequence. The power sequence and reset sequence are shown
as Figure 23 and Figure 21 respectively in the next chapter.
The Tethys and MCU connection include MSIOF0 and I2C1 and RESET signal. The corresponding signals are shown as below:
HSCIF2 connection:
Rcar-W2H Signal
MCU signal
MSIOF0_RXD_A
P11_9/CSIG1SO/RLIN35RX/INTP15/PWGA49O/TAUB1I13/TAUB1O13/MEMC0CS1
MSIOF0_SCK_A
P11_10/CSIG1SC/PWGA50O/TAUB1I15/TAUB1O15/MEMC0CS2/ETNB0COL
MSIOF0_TXD_A
P11_11/CSIG1SI/RLIN25TX/PWGA51O/TAUB1I0/TAUB1O0/MEMC0CS3/ETNB0RXDV
I2C connection:
Rcar-W2H Signal
MCU signal
I2C1-SDA
P0_11/RIIC0SDA/DPIN12/CSIH1CSS2/TAUB0I8/TAUB0O8/RLIN26RX/PWGA34O
I2C1-SCL
P0_12/RIIC0SCL/DPIN13/PWGA45O/TAUB0I10/TAUB0O10/CSIG0SI/RLIN26TX
The CPU reset signal is controlled by MCU GPIO. That is P1_0/RLIN33RX/INTP13.
3.16.2 Block Diagram
MSIOF1_B
MSIOF
Rcar-W2H
I2C1
I2C1
RESET
RESET
Figure 17
ASD-B-16-0247 Rev1.0
Nov 29, 2016
RLIN
MCU
RH850F1H/F1L
RIIC0
RESET
Block Diagram of the Connection between CPU and MCU
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3.17 Clock system
The Tethys board uses the crystal oscillators and resonators shown below.
3.17.1 Clock Signals Supplied to the R-Car W2H
Table 21
NO.
Xn
Supply voltage
List of Clock Signals and Crystals for the R-Car W2H
R-car W2H pin name
GP1_22/EX_WAIT0/CAN_
X1
Frequency
Description
14.7456MHz
SCIF clock
SG-8003CE14.7456
Manufacturer
Type
Epson
Oscillator
Epson
Oscillator
Epson
Crystal
Epson
Crystal
3.3V
CLK_B/SCIF_CLK_A
GP3_11/RX0_B/SCL0_C/A
Part number
X2
3.3V
00MHzPCL
125.00MHz
VB_GTXREFCLK/ETH_M
AVB_GTXREF
SG-8003CE125.000
CLK
000MHzPCL
USB clock
FA-238A48.000MH
DC
USB_XTAL ,
48MHz
Y1
USB_EXTAL
z10
CPU main clock
Y2
XTAL , EXTAL
FA-238A20.000000
20.00MHz
MHz10
3.17.2 Differential Clock Signals Supplied to the R-Car W2H
Table 22
NO.
List of Differential Clock Signals Supplied to the R-Car W2H
R-car W2H pin name
R-Car W2H Pin Assignment
Clock Driver Pin Name
AC12
CLKP
REFCLK-
AB12
CLKN
REFCLK+
Signal Type
Differential signal
3.17.3 Clock Signals Supplied to Devices Other than R-Car W2H
Table 23
NO.
Xn
X3
Device
List of Clocks and Crystals other than for R-Car W2H
Device pin name
Frequency
MCKI
12.288MHz
Description
Audio Clock
Part number
SG-8003CE12.2880
Manufacturer
Type
Epson
Oscillator
Epson
Crystal
Epson
Crystal
Epson
Crystal
Epson
Crystal
AK4642EN
00MHzPCL
X1 , X2
Y3
12MHz
USB Hub Clock
FA-238A12.000000
GL852GT(USB Hub)
MHz10
XI , XO
Y4
25MHz
Ethernet clock
FA-238A25.0000M
KSZ8041RNLI
Hz18
X1 , X2
Y5
12MHz
MCU main clock
FA-238A12.000000
RH850F1H/F1L
MHz10
32.768kHz
Y6
RH850F1H/F1L
XT1 , XT2
FC-13A32.768000k
MCU sub clock
Hz12.5
ASD-B-16-0247 Rev1.0
Nov 29, 2016
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Hardware Design Specification
3.17.4 Block Diagram
U1
R-Car W2H
N.M.
X1
OSC
14.7456MHz
X2
OSC
125MHz
N.M.
22
33
Mini PCIE Connector for
EtherAVB Sub Board
CN8
PCIE CON
CN11
X3
OSC
12.288MHz
Y1
Crystal
48MHz
U29
AK4642EN
U3、U4
DDR3 x 2psc
Y2
Crystal
20MHz
Y6
Crystal
32.768KHz
Y5
Crystal
12MHz
Y3
Crystal
12MHz
Y4
Crystal
25MHz
U32
RH850F1H/F1L
Figure 18
U14
GL852GT-MNGXX
U16
KSZ8041RNLI
Block Diagram of the Clock system
3.18 External Interrupts
3.18.1 Specifications
The R-Car W2H has external interrupt input pins which are NMI, GP4_22, GP4_23, GP4_24, GP4_25, and GP5_8. For details on the
external interrupts, please refer to the R-Car W2H Hardware Manual.
The Tethys board uses NMI as external interrupt input pin, GP4_22, GP4_23, GP4_24, GP4_25, and GP5_8 as GPIO interrupts.
These pins should be used as active-low signals in programs.
The devices and connectors of the interrupt request sources on the Tethys board are shown below table 24.
Table 24
ASD-B-16-0247 Rev1.0
Nov 29, 2016
External Interrupts Specifications
Page 46 of 102
RTK00V2XRC7746SFS
Hardware Design Specification
Interrupt Pin
NMI
Other pin function
Devices that Output Interrupt Request
Connectors
——
Test point
——
TP5
GP4_22
GP4_23
RX3_A/SCL1_C/MSIOF1_RXD_B
GYRO
——
/AUDIO_CLKA_C/SSI_SDATA4_B
U28 A3G4250D from ST
TX3_A/SDA1_C/MSIOF1_TXD_B
/AUDIO_CLKB_C/SSI_WS4_B
GP4_24
GP4_25
SCL2_A/MSIOF1_SCK_B
G-SENSOR
——
/AUDIO_CLKC_C/SSI_SCK4_B
U30 AIS328DQ from ST
SDA2_A/MSIOF1_SYNC_B
/AUDIO_CLKOUT_C
GP5_8/IRQS#
SSI_SDATA7_A/
ETHERNET
——
AUDIO_CLKA_D/CAN_CLK_D
KSZ8041RNLI from Micrel
3.18.2 Block Diagram
D3.3V
TP5
Test point
U1
R-Car W2H
10K
NMI
U28
GYRO
A3G4250D
U30
G-SENSOR
AIS328DQ
U16
ETHERNET
KSZ8041RNLI
GP4_22
GP4_23
GP4_24
GP4_25
D3.3V_ETH
GP5_8/IRQ8#
Figure 19
Block Diagram of the External Interrupts
3.19 Reset System
3.19.1 Specifications
On the Tethys board, the MCU power-on reset signal is cleared by the reset IC TPS3808G01DBVT, 389ms after the D3.3V
power supply has settled. Also a power-on reset signal can be generated by pushing the push switch (SW4). The reset signal is
level-shifted from 3.3 V to 1.8 V by the HD74LV1G08ACME and is input to the PRESET# pin of the R-CarW2H.
Table 25
ASD-B-16-0247 Rev1.0
Nov 29, 2016
Reset System Specifications
Page 47 of 102
RTK00V2XRC7746SFS
Hardware Design Specification
TPS3808G01DBVT from TI
Reset IC

Threshold voltage: 1.7415V

Reset delay time : 389ms (Reset delay time=CT ( nF )/175+0.0005 (s ) )
3.19.2 Block Diagram
BU3.3V
CN4
MCU JTAG
IMSA-9632S-26Y801
VDD
U8
Reset IC
TPS3808G01DBVT
BU3.3V
SW4
RESET#
MCU_RESETn
U32
MCU
RH850F1H/F1L
SOC_RST
U36
DCDC
R2A11301FT
10K
U29
AUDIO CODEC
AK4642EN
MR#
U14
USB HUB
GL852GT-MNGXX
D3.3V
10K
SYS_RESETn_33
RESET
U5
SPI FLASH
S25FL512SAGMFIG11
RST_n
U7
EMMC
SDIN8DE1-8G-XA
D1.8V
VCC
IN_A
U9
HD74LV1G08ACME
IN_B
OUT_Y
CN4
CPU JTAG
IMSA-9632S-26Y801
SYS_RESETn_18
U16
ETHERNET
KSZ8041RNLI
RST#
DDR3*2( U3、U4)
M0RESET# MT41K256M16HA-125
AAT:E
PRESET#
Figure 20
3.19.3
U1
R-CarW2H
ResetB
CN9
Mini PCIE CN
1759546-1
ResetB
CN8
Mini PCIE CN
1759546-1
ResetB
CN12
Mini PCIE CN
1759546-1
Block Diagram of the Reset System
Reset Sequence
The Reset sequence is shown below:
ASD-B-16-0247 Rev1.0
Nov 29, 2016
Page 48 of 102
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Reset sequence
BU5.0V
BU3.3V
MCU_RESETn
VSYS
Reset time
MCU boot
1ms min
3ms
P5.0V
2ms
P3.3V
2ms
SOC_PWRON(MCU)
D1.8V
1us min
SOC_D18PWGD
D1.0V
D1.5V
VREF/VTT
SOC_D10PWGD
D3.3V
D5.0V
SOC_RST(MCU)
Figure 21
ASD-B-16-0247 Rev1.0
Nov 29, 2016
The Reset Sequence
Page 49 of 102
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Hardware Design Specification
3.20 Power system
3.20.1 Specifications
The Tethys board operates on a single BU12V power supply. The power supplies used for the Tethys board are generated by the
switching regulators and low-dropout regulators. Because the maximum output current of the AC adapter attached for Tethys board
is 3A at 12v input status, please make sure not to exceed 3A for all sub-board inserted in extending interface connector such as mini
PCIE etc. If end user need more current AC adapter, please prepare over 6A/12V stable AC adapter by end user.
Table 26
List of the Switching Controllers and Regulators on the Tethys Board
Switching Controller/Regulator
Vin
Power MOSFET
ACC Switch Control
_________
Not supported
Renesas
supported
HAT2210R
supported
(U35 and U37)
supported
Vout
Power Supply BU12V
_________
BU12.0V
Through CN17 or CN18 (1*)
VSYS
Renesas
BU5.0V
R2A11301FT (U36)
BU12.0V
P3.3V
Texas Instruments
supported
PCIE_5.0V
TPS54531DDA(U26)
Vishay Siliconix
VSYS
supported
P5.0V
Si3433CDV-T1-E3(U34)
RICOH
BU5.0V
supported
BU3.3V
RP111N331D-TR-AE(U33)
Vishay Siliconix
supported
D3.3V
SI3433CDV-T1-E3(U40)
Texas Instruments
P3.3V
supported
D1.5V
TPS3808G01DBVT(U45)
RICOH
supported
D2.5V
RP111N251D-TR-AE(U46)
Texas Instruments
supported
D1.2V
TPS54531DDA(U44)
SEMTECH
P5.0V
supported
D1.8V
SC183CULTRT(U38)
Vishay Siliconix
supported
D5.0V
Si3433CDV-T1-E3(U43)
RICOH
supported
VCCQ_SD2
RP111N181D-TR-AE(U12)
D3.3V
VCCQ_SD0
ASD-B-16-0247 Rev1.0
Nov 29, 2016
Vishay Siliconix
Supported
Page 50 of 102
RTK00V2XRC7746SFS
Hardware Design Specification
SI3433CDV-T1-E3(U13)
BU3.3V
(1*)
BU3.3V_MCU
supported
CN17 and CN18 are 12V power connectors , use can choose one connector according to the demand
3.20.2 Block Diagram
MCU CAN (max:75mA)
MCU CAN (max:75mA)
Flexray transceiver (max:350mA)
MCU
FB
CN18
HEC0470-01630(MJ-179P)
BU5.0V
BU3.3V
RP111N331D-TR-AE
Flexray transceiver(max:350mA)
MCU reset (max:0.005mA)
BU12V
CPU and MCU JTAG
CPU CAN transceiver(max:75mA)
MOSFET(Power Switch)
Si3433CDV-T1-E3
BU12V
R2A11301FT
Gate Ctrl
MOS FET
HAT2210R
VSYS
D5.0V
To USB Host Type A Receptacle(max:500mA)
FB
To USB HUB: GL852GT-MNGXX(max:100mA)
EN1/EN2
HSM CN
D1.8V
ACC_CONT_EXT
ACC_CONT_EXT
SC183CULTRT
CN17
34793-9040
To USB Host Type A Receptacle(max:500mA)
MOSFET(Power Switch)
Si3433CDV-T1-E3
Main CPU(max:120mA)
Micro SD slot(max:100mA)
P5.0V
D1.2V
TPS54531DDA
Main CPU(max:3525mA)
Main CPU(max:450mA)
DDR3(max:360mA)
D1.5V
LM3102MH
DDR3(max:360mA)
PCIE CN(max:375mA)
Gate Ctrl
BU12V
MOS FET
HAT2210R
BU12V
FB
P3.3V
D2.5V
RP111N251D-TR-AE
SW18
Main CPU(max:400mA)
[LED (max:10mA)]X10
Main CPU(max:324mA)
SPI Flash(max:100mA)
SPI Flash(max:100mA)
GPS Receive(Max:63mA)
SW18：2-3 short: ON
1-2 short: OFF
P3.3V
MOSFET(Power Switch)
Si3433CDV-T1-E3
D3.3V
RMII PHY(min:53mA)
EMMC(max:300mA)
GYRO(max:7mA)
G-SENSOR(max:450uA)
AUDIO Codec(max:167mA)
Micro SD slot(max:100mA)
PCIE CN(max:1000mA)
TPS54531DDA
Figure 22
ASD-B-16-0247 Rev1.0
Nov 29, 2016
PCIE_5.0V
[PCIE CN(max:1500mA)]X3
Block Diagram of the Power System
Page 51 of 102
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Hardware Design Specification
3.20.3 Power Sequence
There are no restrictions on the power-on sequence. Ensure that all other power supplies rise from the ground (VSS**)
within 300 ms of any single power supply rising from the ground (VSS**) . We do power up sequence as the Tethys power up
sequence. The diagram of the sequence for turning on the power to the Tethys board is shown as below
Power on sequence
BU5.0V
BU3.3V
VSYS
P5.0V
P3.3V
SOC_PWRON(MCU)
D1.8V
SOC_D18PWGD
D1.0V
D1.5V
1um min
VREF/VTT
2ms
SOC_D10PWGD
2ms
D3.3V
3ms
D5.0V
1ms min
SOC_RST(MCU)
300ms max
Figure 23
The Power Sequence
There are no restrictions on the power-off sequence. Ensure that all other power supplies fall to the ground (VSS**)
level within 300 ms of any single power supply being turned off. We do the power off sequence as the Tethys power off sequence ,
turn off the power supplies in reverse order of the power-on sequence.
ASD-B-16-0247 Rev1.0
Nov 29, 2016
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4 Memory map
4.1 Specifications
Memory map for R-CarW2H boot loader is shown below. The maximum size of U-Boot is the value that
subtracted Initialization stack from 240Kbytes. The maximum size of initialization stack is 256Kbytes.
ASD-B-16-0247 Rev1.0
Nov 29, 2016
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RTK00V2XRC7746SFS
Hardware Design Specification
Memory map for RH850F1H/F1L is shown in the above figure. The user area of the code flash memory of
the RH850F1H/F1L is 2MB. A single block of 32-Kbyte extended user area is also incorporated.
RH8500F1H/F1L includes three types of the local RAM: Primary local RAM, Secondary local RAM, Retention
RAM. RH850’s data memory uses Primary local RAM which is RAM area that can be accessed with speed.
ASD-B-16-0247 Rev1.0
Nov 29, 2016
Page 54 of 102
RTK00V2XRC7746SFS
Hardware Design Specification
Memory map for 32MB SPI flash is shown below:
ASD-B-16-0247 Rev1.0
Nov 29, 2016
Page 55 of 102
RTK00V2XRC7746SFS
Hardware Design Specification
Memory map for 512MB SPI flash is shown below:
ASD-B-16-0247 Rev1.0
Nov 29, 2016
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RTK00V2XRC7746SFS
Hardware Design Specification
4.2 Function
These codes of RH850 have realized four functions as follows.
4.2.1
Control the power of the Tethys Custom Board.
The flow chart is as follows:
START
Pull down the SOC_RST
and SOC_PWRON
Pull up
SOC_PWRO
SOC_PWRON has
NO
been pulled up
YES
Delay 300ms (max)
Pull up SOC_RST
END
ASD-B-16-0247 Rev1.0
Nov 29, 2016
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RTK00V2XRC7746SFS
Hardware Design Specification
4.2.2
Realize the UART with the baud rate of 115200
This UART uses RLIN31 of RH850’s LIN/UART interface.
RLIN3nTX
LIN communication
clock source
LINn baud rate
generator
Protocol
controller
RLIN3nRX
INTRLIN3nUR0
INTRLIN3nUR1
LINn interrupt
controller circuit
INTRLIN3nUR2
INTRLIN3n
RLIN3n
LINn registers
Edge detection circuit
INTP1n
Figure shows LIN/UART interface (in UART mode) transmission operations as follows
（1）（2）（3）
（4）
（5）
（6）
（7）
RLIN3nTX
Idle
Idle
Start bit
7 , 8, or 9 data bits
0 or 1
parity bit
1 or 2
stop bits
UART frame
Figure shows the LIN/UART interface (in UART mode) reception operation as follows.
（1）
（2）
（4）
（3）
（5） （6）
（7）
RLIN3nTX
Idle
Idle
7 , 8, or 9 data bits
0 or 1
parity bit
1 or 2
stop bits
UART frame
(about [NSPB],[IBS]’s definition, please refer to [r01uh0445ej0100_rh850f1h.pdf] page 937,859’s description).
This UART’s operations are as follows:
1.
15 : The NSPB bits select the number of sampling in one Tbit (reciprocal of the bit rate).
2.
Noise filter ON: The noise filter is enabled when receiving data
3.
Non-parity, 8bit, 1stop.
4.
No space: The IBS bits set the width of the space between the UART frame in UART buffer transmit
ASD-B-16-0247 Rev1.0
Nov 29, 2016
Page 58 of 102
RTK00V2XRC7746SFS
Hardware Design Specification
4.2.3
Realize an asynchronous serial with baud rate of 1M between RH850 and CPU.
This UART uses RLIN30 of RH850’s LIN/UART interface. The operations are same as above.
4.2.4
Make CAN0 and CAN1 working with baud rate of 1M
1.
CAN0 sends 4-byte data only once.
2.
CAN1 receives the data coming from CAN0.
3.
Once CAN1 receives, the wave form can not be monitored.
The flow chart is as follows
START
Initialize can0
and can1
Can0 sends
4-byte data
Can1 has received
NO
the data
YES
END
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5 Outline Diagrams of the Tethys Board
5.1 Tethys Board dimension
The Tethys board dimension is shown as below (Unit: mm):
Board : 1.6 mm
Board : 8 Layers
Figure 24
The Tethys board dimension
5.2 The weight of the Tethys Board
Condition
Weight (Unit : g)
Screw (total)
Spacer (two piece)
Shell
Heat dissipation silica gel
165
Board
143
RF Cable (15cm, four piece)
16
RF Cable (20cm, one piece)
Tethys assembly(total)
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5.3 Tethys ID dimension
The ID of Tethys board dimension is shown as below (Unit: mm):
Base Panel size
Cover Panel size:
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Side Cover size (Option)
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5.4 Tethys assembly
The assembly pictures of Tethys board are shown as below
Top side view:
Bottom side view:
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Top Side View：
Bottom Side View：
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Left Side View
Right View Side
Front Side View
Back Side View
ASD-B-16-0247 Rev1.0
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V2X RF Cable/GPS RF Cable connection image internal AL case
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6 Board connectors
6.1 TOP side connectors
Switch
The top side connector is shown as the picture in the following.
LED
DIP Switch
SD Card CN
GPS CN
SW5、SW6、SW7
D9、D7、D5、D3、D11 (GPS_LED)
SD Card CN2
SW16、SW15、SW14、SW13、(SW4) MCU reset
Figure 25
ASD-B-16-0247 Rev1.0
Nov 29, 2016
TOP Side Connectors
GPS CN7
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6.2 Bottom side connectors
The bottom side connectors are shown as the picture in the following.
Micro USB CN
LED
DEBUG CN
Audio jack
HSM CN
DIP SW
DIP SW
USB CN
MINI PCIE CN
CAN&Fle
xray CN
POWER Switch
Ethernet CN
DIP SW
DIP SW
ETNB CN
POWER IN JACK
Micro USB
CN16、CN10、CN5
D12 (GPS_LED)、D4、D6、D8、D10
SW12
Audio jack
DEBUG CN14
J1
HSM CN14
SW17、SW3
USB CN1
CAN&Flexr
CN9、CN8、CN12、CN11
ay CN6
POWER Switch
Ethernet
SW18
CN3
POWER IN JACK
CN17 and CN18
SW1、SW2
Figure 26
Bottom side connectors
ETNB CN13
SW11、SW10、SW9、SW8
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6.3 The details of connectors
CN1A:USB0
2 4 6 8 10
1 3 5 7 9
CN1B: USB1
(1) There are two USB connectors, the CN1B is corresponding to Tethys from HUB and CN1A is
corresponding to Tethys from W2H respectively as the picture shown above.
(2) The CAN pin assignments are shown as below:
CN6 PIN Number
Signal
Remark
CPU_CAN0_H
HIGH-level CAN bus line
CPU_CAN0_L
LOW-level CAN bus line
MCU_CAN0_H
HIGH-level CAN bus line
MCU_CAN0_L
LOW-level CAN bus line
MCU_CAN1_H
HIGH-level CAN bus line
MCU_CAN1_L
LOW-level CAN bus line
BP
Flexray bus line plus
BM
Flexray bus line minus
GND
Ground
10
GND
Ground
MCU Debug
CPU Debug
Sub Board V2X
Debug
As the picture shown above, there are there USB2UART connectors From the left to right as the figure
shown, they are for MCU debug, sub board V2X debug and CPU debug respectively.
CH2 & CH3
GPS:
to V2X SUB(CN12)
to Tethys CN7
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CH0 & CH1
to V2X SUB (CN9)
As the picture shown above, there are five RF connectors to the antenna. In the inner connection, the CH2 and
CH3 are for the V2X sub-board which is inserted in Tethys MINI PCIE connector CN12, the CH0 and CH1 are
for the V2X sub-board which is inserted in the Tethys MINI PCIE connector CN9. The GPS is for Tethys GPS
module antenna connector CN7 at the top side.
One possible connection is shown as the picture in the following picture:
CN8
CN9
Connect to
Connect to
CH0
CH1
ASD-B-16-0247 Rev1.0
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CN12
Connect to
CH2
CN11
Connect to
CH3
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7 Appendix
7.1 USB debug Cable
USB debug Cable Length：1.5m, This USB cable is used for Micro USB type B connector CN5, CN10, CN16 for debug
on V2X main board. This cable can be inserted to miniUSB1/miniUSB2/miniUSB3 connector .
Figure 27
ASD-B-16-0247 Rev1.0
Nov 29, 2016
Image of USB debug cable
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7.2 AC Adapter
This 12V AC adapter is used for power supply to the Tethys .
7.2.1
Specifications
Item
Specification
Part Number
GPE048A-120300-W
Manufacturer
GOLDEN PROFIT ELECTRONICS LTD
Input voltage range
90-264V AC
Input frequency range
63/47 Hz
AC input current
1A Max .@100V AC
AC input power saving
0.075W Max .@230V AC at no load
Inrush Current
60 A Max .@100VAC (Cold start）
90 A Max .@230VAC (Cold start）
Leakage current
0.25mA Max
Output voltage
12V
Max. load current
3A
Min. load current
0A
Output voltage
12 V± 5%
Output ripple & noise
12 V± 5%
Total output power
36 W
Operating Temp
0~40℃
Storage Temp
–25℃ to 85℃
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7.2.2
Mechanic Size and Picture
Mechanic Size：
Cable Spec：
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LOG Image：
Figure 28
Power Adapter ID LOG specification
Figure 29
ASD-B-16-0247 Rev1.0
Nov 29, 2016
Image of Power Adapter
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7.3 GPS antenna
7.3.1
Specification
About GPS antenna specification, please refer to the following data:
Table 27
Antenna Specification for GPS module
Specification
Item
Part Number
DAM1575 A4D1
Manufacturer
Taiwan ACC
Cable Length
5m
Center Frequency
1575MHz ± 3MHz
VSWR
Maximum 2.0
Bandwidth
Minimum 20MHz
IF Resister
50ohm
Peak Gain
4 dBic(base on 70mm x 70mm ground plane)
Gain coverage
≥-4dBic at -90°<θ<+90°（over 75% volume）
Polarity
RHCP
Power consumption
1 watt
Gain
30dB(typical)
Noise parameter
1.5dB(typical)
Material
Copper
Plating treatment
Gold plating
Male/Female
Male
Filter
-24dB(±100mHz)
DC voltage
3-5.0V ±0.25V
DC current
Maximum 16mA
Weight
≤110 g
Size
50x50x17 mm3
Cable type
rg174, 5m
IF Type
SMA
Color
Black
Work temperature
-40℃~ +85℃
Save temperature
-40℃~ +85℃
Vibration
sine wave, 1g(0-p) 10-150-10Hz for each axis
Humidity
95%~100%, no condensation
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This GPS antenna connect the SMA connector labeled GPS in the case. Cable Length： 5m
Figure 30
Figure 31
ASD-B-16-0247 Rev1.0
Nov 29, 2016
Image of GPS Antenna from Bottom view
Image of GPS Antenna from Top view
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7.4 V2X Antenna1 with 2m cable
7.4.1
Specification
About V2X antenna specification, please refer to the following data:
Table 28
Antenna Specification for V2X (2m cable)
Item
Specification
Part Number
6073F00005
Manufacturer
Signal Plus
Frequency Range
5860~ 5920MHz
Polarization
Horizontal
Impedance
50 Ohm
VSWR
2.0 Max
Gain
3.0dBi(without cable loss)
-1.0dBi(with cable loss)
Cable Loss
4.0dB(L=2m)
Radiation
Omni Directional
Cable length
2m
Antenna Cap
ABS
Color
Black
Connector
SMA Plug Standard
Material
Copper
Plating treatment
Gold plating
Male/Female
Male
Operating Temp
-.20℃ ~ +65℃
Storage Temp
-.30℃ ~ +75℃
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This Antenna’s radiation pattern is described as below figures.
Figure 32
ASD-B-16-0247 Rev1.0
Nov 29, 2016
V2X Antenna Test Chamber description
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Figure 33
ASD-B-16-0247 Rev1.0
Nov 29, 2016
V2X Antennal test axis definition description
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Hardware Design Specification
Figure 34
ASD-B-16-0247 Rev1.0
Nov 29, 2016
V2X Antennal VSWR test character
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Figure 35
ASD-B-16-0247 Rev1.0
Nov 29, 2016
V2X Antennal 2D radiation pattern
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Hardware Design Specification
Figure 36
ASD-B-16-0247 Rev1.0
Nov 29, 2016
V2X Antennal 3D radiation pattern
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Hardware Design Specification
This V2X antenna connects with the SMA connector labeled CH0, CH1 in the case by default while delivery.
Cable Length: 2m
Figure 37
Figure 38
ASD-B-16-0247 Rev1.0
Nov 29, 2016
Image of V2X Antenna1 from Bottom view
Image of V2X Antenna1 from Top view
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7.5 V2X Antenna (Rod Type)
7.5.1
Specification
About 5.9GHz V2X antenna specification, please refer to the following data:
Table 29
Antenna Specification for V2X (Rod Type)
Item
Specification
Part Number
6073F00006
Manufacturer
Signal Plus
Frequency Range
5860~ 5920MHz
Polarization
Vertical
Impedance
50 Ohm
VSWR
2.0 Max
Gain
5.0dBi
Cable Loss
0.5dB (with SMA)
Radiation
Omni Directional
Color
Black
Connector
SMA Plug Standard
Material
nickel
Plating treatment
nickel plating
Male/Female
Male
Operating Temp
-.20℃ ~ +65℃
Storage Temp
-.30℃ ~ +75℃
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Hardware Design Specification
This Antenna’s radiation pattern is described as below figures.
Figure 39
ASD-B-16-0247 Rev1.0
Nov 29, 2016
V2X Antenna2 Test Chamber description
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Figure 40
ASD-B-16-0247 Rev1.0
Nov 29, 2016
V2X Antenna2 test axis definition description
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Hardware Design Specification
Figure 41
ASD-B-16-0247 Rev1.0
Nov 29, 2016
V2X Antenna2 VSWR test character
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Hardware Design Specification
Figure 42
ASD-B-16-0247 Rev1.0
Nov 29, 2016
V2X Antenna2 2D radiation pattern
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Hardware Design Specification
Figure 43
ASD-B-16-0247 Rev1.0
Nov 29, 2016
V2X Antenna2 3D radiation pattern
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ASD-B-16-0247 Rev1.0
Nov 29, 2016
Figure 44
Image of V2X Antenna2 (SMA rotate 90 degree)
Figure 45
Image of V2X Antenna2 (SMA rotate 0 degree)
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7.6 RF Cable
7.6.1
Specification
About RF Cable specification, please refer to the following data:
Table 30
RF Cable Specification for GPS module & RF Board
Item
Specification
Frequency Range
0~ 6GHz
Impedance
50 Ohm
VSWR
1.4 Max
Cable Loss
1.3dB Max
Cable length
(1)13~15cm for V2X
(2)20cm for GPS
Cable Type
U.FL-LP-088
Connector
SMA
Material
Copper
Plating treatment
Gold plating
Male/Female
Female
Operating Temp
-.40℃ ~ +90℃
Storage Temp
-.40℃ ~ +70℃
Figure 46
ASD-B-16-0247 Rev1.0
Nov 29, 2016
RF Cable
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Hardware Design Specification
7.7 JTAG Debug Board with FPC Cable
7.7.1
Specifications
Connecter
Function
Manufacturer
CN1
CPU JTAG
ARM JTAG ICE Debugger
ARM JTAG ICE Vendor
CN4
CPU JTAG2(SH-4A)
E10A
Renesas (Japan)
CN3
MCU JTAG
E1
Renesas (Japan)
Figure 47
7.7.2
Debugger
JTAG Debug Board with FPC Cable for W2H & RH850 MCU
Block Structure
CPU JTAG ( 02 )
CONN(2)
CPU JTAG2 ( SH-4AL )
( 02 )
MCU JTAG ( 02 )
Figure 48
ASD-B-16-0247 Rev1.0
Nov 29, 2016
JTAG Debug Board block structure
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Hardware Design Specification
7.7.3
Block Diagram
IMSA-9632S-26Y801
CN2
25
TDI
TDI
24
23
TMS
TCK
TMS
TCK
VDD0
22
TDO
TDO
VDD1
20
ASEBRKn
NC1
26
CPU
JTAG
D1.8V
HTST-110-01-S-DV
CN1
TRSTn
21
SYS_RESETn_18
TRST
SRSTZ
D1.8V
BU3.3V
D1.8V
SYS_RESETn_18
MMC0_CMD_TRST
MMC0_D2_TDI
MMC0_D1_TMS
11
MMC0_D0_TCK
MMC0_CLK_TDO
MMC0_D3_ASEBRK#/ACK
CPU
JTAG2
(SH-4AL)
DCUTDI
16
DCUTMS
DCUTCK
15
13
17
Figure 49
ASD-B-16-0247 Rev1.0
Nov 29, 2016
4.7K
DCUTRST
19
1-1634688-4
CN4
18
MCU
JTAG
13
14
DCUTDO
MCU_RESETn
13
DCURDY
11
12
FLMD0
BU3.3V
1-1634688-4
CN4
Block Diagram of the JTAG Debug Board
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Hardware Design Specification
7.8 V2X Connection board
This sub board can be connected to CN9 or CN12 to extend SD socket IF.
Top side view:
Figure 50
Top side view of V2X Connection board
Bottom side view:
Figure 51
7.8.1
Bottom side view of V2X Connection board
Board Structure
CONN ( 02 )
GOLD finger ( 2 )
Micro SD SLOT ( 02 )
Figure 52
ASD-B-16-0247 Rev1.0
Nov 29, 2016
Block structure of V2X Connection board
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7.8.2
Block Diagram
Mini PCIE
PLUG
Gold finger
CN1
33
SDIO_DAT3
RESERVED7
33
SDIO_DAT2
RESERVED8
RESERVED9
33
33
SDIO_DAT1
SDIO_DAT0
RESERVED10
33
SDIO_CMD
RESERVED3
SDIO_CLK
RESERVED6
D3.3V
Connect to C2X
HTST-108-01-F-D
CN2
15
13
11
D3.3V
D3.3V
SDIO_DAT3
3.3V
SDIO_DAT2
SDIO_DAT1
SDIO_DAT0
SDIO_CLK
RESERVED4
Figure 53
7.8.3
SD_CD
DAT2
DAT1
Micro SD slot
503182-1852
CN3
DAT0
CMD
CLK
PAD
VDD
PAD
100nF/25V
SDIO_CMD
CD/DAT3
Block Diagram of the V2X Connection board
Block dimension
ASD-B-16-0247 Rev1.0
Nov 29, 2016
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7.9 Sub board Tortuga wireless module board dimension
The Tethys board can connect to Tortuga wireless module through MINI PCIE interface transfer board, and the transfer
sub board dimension is shown as below(Unit: mm): Please connect this board to CN9, CN12.
7.9.1
RF characteristic
*1 typical operating condition (Just informative, not guaranteed.):
*1 HW = Tortuga7, Ta = 25°C, VDD3V3 =3.3V, VDD1V2 =1.2V, VDD5V0=5.0V
*1 Measurement point is circled in red in the figure below
(1) Receive characteristic
Min
Frequency range
Input VSWR
Minimum Sensitivity
(Diversity off)
Typ
Max
5850
5925
2.0
-94
-93
-87
-77
Minimum Sensitivity
(Diversity on)
-94
-94
-87
-80
Maximum
Input Level
(Diversity off)
Maximum
Input Level
(Diversity on)
Adjacent channel rejection
(Diversity off)
[dBm]
[dBm]
5890MHz
Data rate = 3Mbps
Data rate = 6Mbps
Data rate = 12Mbps
[dBm]
Data rate = 27Mbps
[dBm]
Data rate = 3Mbps
Data rate = 6Mbps
[dBm]
Data rate = 12Mbps
[dBm]
Data rate = 27Mbps
[dBm]
Data rate = 27Mbps
-20
[dBm]
Data rate = 27Mbps
30
[dB]
Data rate = 3Mbps
[dB]
Data rate = 12Mbps
[dB]
Data rate = 3Mbps
[dB]
Data rate = 12Mbps
-20
29
18
44
41
36
27
ASD-B-16-0247 Rev1.0
Nov 29, 2016
[MHz]
[dBm]
Condition
[dBm]
28
Nonadjacent Adjacent channel
rejection
(Diversity off)
Unit
[dB]
Data rate = 6Mbps
[dB]
Data rate = 27Mbps
[dB]
Data rate = 6Mbps
[dB]
Data rate = 27Mbps
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(2) Transmit characteristic
Ta = 25°C, VDD3V3 =3.3V, VDD1V2 =1.2V, VDD5V0=5.0V
Min
Frequency range
Output VSWR
Maximum out put
Power(ANT_B)
Maximum out put
Power(ANT_A)
Minimum out put Power(ANT_B)
Minimum out put Power(ANT_A)
Output Power control range
Power control step
Relative constellation error
Spectrum Mask
(in band)
Typ
Max
5850
5925
Condition
[MHz]
2.0
24
[dBm]
5890MHz
5890MHz
-8
[dBm]
5890MHz
-7
-35
30
0.5
-28
-28
-28
-28
-31
[dBm]
[dBm]
[dB]
[dB]
[dB]
5890MHz
5890MHz
5890MHz
-33
-36
-54
ASD-B-16-0247 Rev1.0
Nov 29, 2016
Unit
[dBr/100
KHz]
@5890
MHz
Data rate = 3Mbps
Data rate = 6Mbps
Data rate = 12Mbps
Data rate = 27Mbps
4.5MHz
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