Compaq Ecqd2Kcte Users Manual

2015-02-03

• Table of Contents
  • 1 Introduction
  • 2 Basic Architecture
  • 3 Instruction Formats
  • 4 Instruction Descriptions
  • 5 System Architecture and Programming Implications
  • 6 Common PALcode Architecture
  • 7 Console Subsystem Overview
  • 8 Input/Output Overview
  • 9 OpenVMS Alpha
  • 10 Digital UNIX
  • 11 Windows NT Alpha
  • A Software Considerations
  • B IEEE Floating-Point Conformance
  • C Instruction Summary
  • D Registered System and Processor Identifiers
  • E Waivers and Implementation-Dependent Functionality
• Figures
• Tables
• Preface
• Introduction
  • 1.1 The Alpha Approach to RISC Architecture
  • 1.2 Data Format Overview
  • 1.3 Instruction Format Overview
  • 1.4 Instruction Overview
  • 1.5 Instruction Set Characteristics
  • 1.6 Terminology and Conventions
    • 1.6.1 Numbering
    • 1.6.2 Security Holes
    • 1.6.3 UNPREDICTABLE and UNDEFINED
    • 1.6.4 Ranges and Extents
    • 1.6.5 ALIGNED and UNALIGNED
    • 1.6.6 Must Be Zero (MBZ)
    • 1.6.7 Read As Zero (RAZ)
    • 1.6.8 Should Be Zero (SBZ)
    • 1.6.9 Ignore (IGN)
    • 1.6.10 Implementation Dependent (IMP)
    • 1.6.11 Illustration Conventions
    • 1.6.12 Macro Code Example Conventions
• Basic Architecture
  • 2.1 Addressing
  • 2.2 Data Types
    • 2.2.1 Byte
    • 2.2.2 Word
    • 2.2.3 Longword
    • 2.2.4 Quadword
    • 2.2.5 VAX Floating-Point Formats
      • 2.2.5.1 F_floating
      • 2.2.5.2 G_floating
      • 2.2.5.3 D_floating
    • 2.2.6 IEEE Floating-Point Formats
      • 2.2.6.1 S_Floating
      • 2.2.6.2 T_floating
      • 2.2.6.3 X_Floating
    • 2.2.7 Longword Integer Format in Floating-Point Unit
    • 2.2.8 Quadword Integer Format in Floating-Point Unit
    • 2.2.9 Data Types with No Hardware Support
  • 2.3 Big-Endian Addressing Support
• Instruction Formats
  • 3.1 Alpha Registers
    • 3.1.1 Program Counter
    • 3.1.2 Integer Registers
    • 3.1.3 Floating-Point Registers
    • 3.1.4 Lock Registers
    • 3.1.5 Processor Cycle Counter (PCC) Register
    • 3.1.6 Optional Registers
      • 3.1.6.1 Memory Prefetch Registers
      • 3.1.6.2 VAX Compatibility Register
  • 3.2 Notation
    • 3.2.1 Operand Notation
    • 3.2.2 Instruction Operand Notation
      • 3.2.2.1 Operand Name Notation
      • 3.2.2.2 Operand Access Type Notation
      • 3.2.2.3 Operand Data Type Notation
    • 3.2.3 Operators
    • 3.2.4 Notation Conventions
  • 3.3 Instruction Formats
    • 3.3.1 Memory Instruction Format
      • 3.3.1.1 Memory Format Instructions with a Function Code
      • 3.3.1.2 Memory Format Jump Instructions
    • 3.3.2 Branch Instruction Format
    • 3.3.3 Operate Instruction Format
    • 3.3.4 Floating-Point Operate Instruction Format
      • 3.3.4.1 Floating-Point Convert Instructions
      • 3.3.4.2 Floating-Point/Integer Register Moves
    • 3.3.5 PALcode Instruction Format
• Instruction Descriptions
  • 4.1 Instruction Set Overview
    • 4.1.1 Subsetting Rules
    • 4.1.2 Floating-Point Subsets
    • 4.1.3 Software Emulation Rules
    • 4.1.4 Opcode Qualifiers
  • 4.2 Memory Integer Load/Store Instructions
    • 4.2.1 Load Address
    • 4.2.2 Load Memory Data into Integer Register
    • 4.2.3 Load Unaligned Memory Data into Integer Register
    • 4.2.4 Load Memory Data into Integer Register Locked
    • 4.2.5 Store Integer Register Data into Memory Conditional
    • 4.2.6 Store Integer Register Data into Memory
    • 4.2.7 Store Unaligned Integer Register Data into Memory
  • 4.3 Control Instructions
    • 4.3.1 Conditional Branch
    • 4.3.2 Unconditional Branch
    • 4.3.3 Jumps
  • 4.4 Integer Arithmetic Instructions
    • 4.4.1 Longword Add
    • 4.4.2 Scaled Longword Add
    • 4.4.3 Quadword Add
    • 4.4.4 Scaled Quadword Add
    • 4.4.5 Integer Signed Compare
    • 4.4.6 Integer Unsigned Compare
    • 4.4.7 Count Leading Zero
    • 4.4.8 Count Population
    • 4.4.9 Count Trailing Zero
    • 4.4.10 Longword Multiply
    • 4.4.11 Quadword Multiply
    • 4.4.12 Unsigned Quadword Multiply High
    • 4.4.13 Longword Subtract
    • 4.4.14 Scaled Longword Subtract
    • 4.4.15 Quadword Subtract
    • 4.4.16 Scaled Quadword Subtract
  • 4.5 Logical and Shift Instructions
    • 4.5.1 Logical Functions
    • 4.5.2 Conditional Move Integer
    • 4.5.3 Shift Logical
    • 4.5.4 Shift Arithmetic
  • 4.6 Byte Manipulation Instructions
    • 4.6.1 Compare Byte
    • 4.6.2 Extract Byte
    • 4.6.3 Byte Insert
    • 4.6.4 Byte Mask
    • 4.6.5 Sign Extend
    • 4.6.6 Zero Bytes
  • 4.7 Floating-Point Instructions
    • 4.7.1 Single-Precision Operations
    • 4.7.2 Subsets and Faults
    • 4.7.3 Definitions
    • 4.7.4 Encodings
    • 4.7.5 Rounding Modes
    • 4.7.6 Computational Models
      • 4.7.6.1 VAX-Format Arithmetic with Precise Exceptions
      • 4.7.6.2 High-Performance VAX-Format Arithmetic
      • 4.7.6.3 IEEE-Compliant Arithmetic
      • 4.7.6.4 IEEE-Compliant Arithmetic Without Inexact Exception
      • 4.7.6.5 High-Performance IEEE-Format Arithmetic
    • 4.7.7 Trapping Modes
      • 4.7.7.1 VAX Trapping Modes
      • 4.7.7.2 IEEE Trapping Modes
      • 4.7.7.3 Arithmetic Trap Completion
        • 4.7.7.3.1 Trap Shadow Rules
        • 4.7.7.3.2 Trap Shadow Length Rules
      • 4.7.7.4 Invalid Operation (INV) Arithmetic Trap
      • 4.7.7.5 Division by Zero (DZE) Arithmetic Trap
      • 4.7.7.6 Overflow (OVF) Arithmetic Trap
      • 4.7.7.7 Underflow (UNF) Arithmetic Trap
      • 4.7.7.8 Inexact Result (INE) Arithmetic Trap
      • 4.7.7.9 Integer Overflow (IOV) Arithmetic Trap
      • 4.7.7.10 IEEE Floating-Point Trap Disable Bits
      • 4.7.7.11 IEEE Denormal Control Bits
    • 4.7.8 Floating-Point Control Register (FPCR)
      • 4.7.8.1 Accessing the FPCR
      • 4.7.8.2 Default Values of the FPCR
      • 4.7.8.3 Saving and Restoring the FPCR
    • 4.7.9 Floating-Point Instruction Function Field Format
    • 4.7.10 IEEE Standard
      • 4.7.10.1 Conversion of NaN and Infinity Values
      • 4.7.10.2 Copying NaN Values
      • 4.7.10.3 Generating NaN Values
      • 4.7.10.4 Propagating NaN Values
  • 4.8 Memory Format Floating-Point Instructions
    • 4.8.1 Load F_floating
    • 4.8.2 Load G_floating
    • 4.8.3 Load S_floating
    • 4.8.4 Load T_floating
    • 4.8.5 Store F_floating
    • 4.8.6 Store G_floating
    • 4.8.7 Store S_floating
    • 4.8.8 Store T_floating
  • 4.9 Branch Format Floating-Point Instructions
    • 4.9.1 Conditional Branch
  • 4.10 Floating-Point Operate Format Instructions
    • 4.10.1 Copy Sign
    • 4.10.2 Convert Integer to Integer
    • 4.10.3 Floating-Point Conditional Move
    • 4.10.4 Move from/to Floating-Point Control Register
    • 4.10.5 VAX Floating Add
    • 4.10.6 IEEE Floating Add
    • 4.10.7 VAX Floating Compare
    • 4.10.8 IEEE Floating Compare
    • 4.10.9 Convert VAX Floating to Integer
    • 4.10.10 Convert Integer to VAX Floating
    • 4.10.11 Convert VAX Floating to VAX Floating
    • 4.10.12 Convert IEEE Floating to Integer
    • 4.10.13 Convert Integer to IEEE Floating
    • 4.10.14 Convert IEEE S_Floating to IEEE T_Floating
    • 4.10.15 Convert IEEE T_Floating to IEEE S_Floating
    • 4.10.16 VAX Floating Divide
    • 4.10.17 IEEE Floating Divide
    • 4.10.18 Floating-Point Register to Integer Register Move
    • 4.10.19 Integer Register to Floating-Point Register Move
    • 4.10.20 VAX Floating Multiply
    • 4.10.21 IEEE Floating Multiply
    • 4.10.22 VAX Floating Square Root
    • 4.10.23 IEEE Floating Square Root
    • 4.10.24 VAX Floating Subtract
    • 4.10.25 IEEE Floating Subtract
  • 4.11 Miscellaneous Instructions
    • 4.11.1 Architecture Mask
    • 4.11.2 Call Privileged Architecture Library
    • 4.11.3 Evict Data Cache Block
    • 4.11.4 Exception Barrier
    • 4.11.5 Prefetch Data
    • 4.11.6 Implementation Version
    • 4.11.7 Memory Barrier
    • 4.11.8 Read Processor Cycle Counter
    • 4.11.9 Trap Barrier
    • 4.11.10 Write Hint
    • 4.11.11 Write Memory Barrier
  • 4.12 VAX Compatibility Instructions
    • 4.12.1 VAX Compatibility Instructions
  • 4.13 Multimedia (Graphics and Video) Support
    • 4.13.1 Byte and Word Minimum and Maximum
    • 4.13.2 Pixel Error
    • 4.13.3 Pack Bytes
    • 4.13.4 Unpack Bytes
• System Architecture and Programming Implications
  • 5.1 Introduction
  • 5.2 Physical Address Space Characteristics
    • 5.2.1 Coherency of Memory Access
    • 5.2.2 Granularity of Memory Access
    • 5.2.3 Width of Memory Access
    • 5.2.4 Memory-Like and Non-Memory-Like Behavior
  • 5.3 Translation Buffers and Virtual Caches
  • 5.4 Caches and Write Buffers
  • 5.5 Data Sharing
    • 5.5.1 Atomic Change of a Single Datum
    • 5.5.2 Atomic Update of a Single Datum
    • 5.5.3 Atomic Update of Data Structures
    • 5.5.4 Ordering Considerations for Shared Data Structures
  • 5.6 Read/Write Ordering
    • 5.6.1 Alpha Shared Memory Model
      • 5.6.1.1 Architectural Definition of Processor Issue Sequence
      • 5.6.1.2 Definition of Before and After
      • 5.6.1.3 Definition of Processor Issue Constraints
      • 5.6.1.4 Definition of Location Access Constraints
      • 5.6.1.5 Definition of Visibility
      • 5.6.1.6 Definition of Storage
      • 5.6.1.7 Definition of Dependence Constraint
      • 5.6.1.8 Definition of Load-Locked and Store-Conditional
      • 5.6.1.9 Timeliness
    • 5.6.2 Litmus Tests
      • 5.6.2.1 Litmus Test 1 (Impossible Sequence)
      • 5.6.2.2 Litmus Test 2 (Impossible Sequence)
      • 5.6.2.3 Litmus Test 3 (Impossible Sequence)
      • 5.6.2.4 Litmus Test 4 (Sequence Okay)
      • 5.6.2.5 Litmus Test 5 (Sequence Okay)
      • 5.6.2.6 Litmus Test 6 (Sequence Okay)
      • 5.6.2.7 Litmus Test 7 (Impossible Sequence)
      • 5.6.2.8 Litmus Test 8 (Impossible Sequence)
      • 5.6.2.9 Litmus Test 9 (Impossible Sequence)
      • 5.6.2.10 Litmus Test 10 (Sequence Okay)
      • 5.6.2.11 Litmus Test 11 (Impossible Sequence)
    • 5.6.3 Implied Barriers
    • 5.6.4 Implications for Software
      • 5.6.4.1 Single Processor Data Stream
      • 5.6.4.2 Single Processor Instruction Stream
      • 5.6.4.3 Multiprocessor Data Stream (Including Single Processor with DMA I/O)
      • 5.6.4.4 Multiprocessor Instruction Stream (Including Single Processor with DMA I/O)
      • 5.6.4.5 Multiprocessor Context Switch
      • 5.6.4.6 Multiprocessor Send/Receive Interrupt
      • 5.6.4.7 Implications for Memory Mapped I/O
      • 5.6.4.8 Multiple Processors Writing to a Single I/O Device
    • 5.6.5 Implications for Hardware
  • 5.7 Arithmetic Traps
• Common PALcode Architecture
  • 6.1 PALcode
  • 6.2 PALcode Instructions and Functions
  • 6.3 PALcode Environment
  • 6.4 Special Functions Required for PALcode
  • 6.5 PALcode Effects on System Code
  • 6.6 PALcode Replacement
  • 6.7 Required PALcode Instructions
    • 6.7.1 Drain Aborts
    • 6.7.2 Halt
    • 6.7.3 Instruction Memory Barrier
• Console Subsystem Overview
• Input/Output Overview
• OpenVMS Alpha
  • 9.1 Unprivileged OpenVMS Alpha PALcode
  • 9.2 Privileged OpenVMS Alpha Palcode
• Digital UNIX
  • 10.1 Unprivileged Digital UNIX PALcode
  • 10.2 Privileged Digital UNIX PALcode
• Windows NT Alpha
  • 11.1 Unprivileged Windows NT Alpha PALcode
  • 11.2 Privileged Windows NT Alpha PALcode
• Software Considerations
  • A.1 Hardware-Software Compact
  • A.2 Instruction-Stream Considerations
    • A.2.1 Instruction Alignment
    • A.2.2 Branch Prediction and Minimizing Branch-Taken — Factor of 3
    • A.2.3 Improving I-Stream Density — Factor of 3
    • A.2.4 Instruction Scheduling — Factor of 3
  • A.3 Data-Stream Considerations
    • A.3.1 Data Alignment — Factor of 10
    • A.3.2 Shared Data in Multiple Processors — Factor of 3
    • A.3.3 Avoiding Cache/TB Conflicts — Factor of 1
    • A.3.4 Sequential Read/Write — Factor of 1
    • A.3.5 Prefetching — Factor of 3
  • A.4 Code Sequences
    • A.4.1 Aligned Byte/Word (Within Register) Memory Accesses
    • A.4.2 Division
    • A.4.3 Byte Swap
    • A.4.4 Stylized Code Forms
      • A.4.4.1 NOP
      • A.4.4.2 Clear a Register
      • A.4.4.3 Load Literal
      • A.4.4.4 Register-to-Register Move
      • A.4.4.5 Negate
      • A.4.4.6 NOT
      • A.4.4.7 Booleans
    • A.4.5 Exceptions and Trap Barriers
    • A.4.6 Pseudo-Operations (Stylized Code Forms)
  • A.5 Timing Considerations: Atomic Sequences
• IEEE Floating-Point Conformance
  • B.1 Alpha Choices for IEEE Options
  • B.2 Alpha Support for OS Completion Handlers
    • B.2.1 IEEE Floating-Point Control (FP_C) Quadword
  • B.3 Mapping to IEEE Standard
• Instruction Summary
  • C.1 Common Architecture Instruction Summary
  • C.2 IEEE Floating-Point Instructions
  • C.3 VAX Floating-Point Instructions
  • C.4 Independent Floating-Point Instructions
  • C.5 Opcode Summary
  • C.6 Common Architecture Opcodes in Numerical Order
  • C.7 OpenVMS Alpha PALcode Instruction Summary
  • C.8 DIGITAL UNIX PALcode Instruction Summary
  • C.9 Windows NT Alpha Instruction Summary
  • C.10 PALcode Opcodes in Numerical Order
  • C.11 Required PALcode Opcodes
  • C.12 Opcodes Reserved to PALcode
  • C.13 Opcodes Reserved to Compaq
  • C.14 Unused Function Code Behavior
  • C.15 ASCII Character Set
• Registered System and Processor Identifiers
  • D.1 Processor Type Assignments
  • D.2 PALcode Variation Assignments
  • D.3 Architecture Mask and Implementation Values
• Waivers and Implementation-Dependent Functionality
  • E.1 Waivers
    • E.1.1 DECchip 21064, DECchip 21066, and DECchip 21068 IEEE Divide Instruction Violation
    • E.1.2 DECchip 21064, DECchip 21066, and DECchip 21068 Write Buffer Violation
    • E.1.3 DECchip 21264 LDx_L/STx_C with WH64 Violation
  • E.2 Implementation-Specific Functionality
    • E.2.1 DECchip 21064/21066/21068 Performance Monitoring
      • E.2.1.1 DECchip 21064/21066/21068 Performance Monitor Interrupt Mechanism
      • E.2.1.2 Functions and Arguments for the DECchip 21064/21066/21068
    • E.2.2 DECchip 21164/21164PC Performance Monitoring
      • E.2.2.1 Performance Monitor Interrupt Mechanism
      • E.2.2.2 Windows NT Alpha Functions and Argument
      • E.2.2.3 OpenVMS Alpha and DIGITAL UNIX Functions and Arguments
    • E.2.3 21264 Performance Monitoring
      • E.2.3.1 Performance Monitor Interrupt Mechanism
      • E.2.3.2 Windows NT Alpha Functions and Argument
      • E.2.3.3 OpenVMS Alpha and DIGITAL UNIX Functions and Arguments
• Index
  • A
  • B
  • C
  • D
  • E
  • F
  • G
  • H
  • I
  • J
  • L
  • M
  • N
  • O
  • P
  • Q
  • R
  • S
  • T
  • U
  • V
  • W
  • X
  • Y
  • Z