Cypress Semiconductor 2011 Bluetooth Module User Manual II

Cypress Semiconductor Bluetooth Module II

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User Manual II

CYBLE-212019-00Document Number: 002-09764 Rev. ** Page 2 of 31ContentsOverview............................................................................ 3Module Description...................................................... 3Pad Connection Interface ................................................ 5Recommended Host PCB Layout ................................... 6Power Supply Connections and Recommended External Components...................................................................... 9Connection Options..................................................... 9External Component Recommendation ...................... 9Critical Components List ........................................... 11Antenna Design......................................................... 11Electrical Specification .................................................. 12GPIO ......................................................................... 14XRES......................................................................... 15Digital Peripherals ..................................................... 18Serial Communication ............................................... 20Memory ..................................................................... 21System Resources .................................................... 21Environmental Specifications ....................................... 24Environmental Compliance ....................................... 24RF Certification.......................................................... 24Environmental Conditions ......................................... 24ESD and EMI Protection ........................................... 24Regulatory Information.................................................. 25FCC........................................................................... 25Industry Canada (IC) Certification............................. 26European R&TTE Declaration of Conformity ............ 26MIC Japan................................................................. 27KC Korea................................................................... 27Ordering Information...................................................... 28Part Numbering Convention...................................... 28Document Conventions............................................. 29Document History Page................................................. 30Sales, Solutions, and Legal Information ...................... 31Worldwide Sales and Design Support....................... 31Products .................................................................... 31PSoC® Solutions ...................................................... 31Cypress Developer Community................................. 31Technical Support ..................................................... 31

CYBLE-212019-00Document Number: 002-09764 Rev. ** Page 3 of 31OverviewModule DescriptionThe CYBLE-212019-00 module is a complete module designed to be soldered to the applications main board. Module Dimensions and DrawingCypress reserves the right to select components (including the appropriate BLE device) from various vendors to achieve the BLE module functionality. Such selections will still guarantee that all height restrictions of the component area are maintained. Designs should be held within the physical dimensions shown in the mechanical drawings in Figure 1. All dimensions are in millimeters (mm).Table 1. Module Design DimensionsSee Figure 1 on page 4 for the mechanical reference drawing for CYBLE-212019-00.Dimension Item SpecificationModule dimensions Length (X) 14.52 ± 0.15 mmWidth (Y) 19.20 ± 0.15 mmAntenna location dimensions Length (X) 11.00 ± 0.15 mmWidth (Y) 5.00 ± 0.15 mmPCB thickness Height (H) 0.80 ± 0.10 mmShield height Height (H) 1.20 ± 0.10 mmMaximum component height Height (H) 1.20 mm typical (shield) Total module thickness (bottom of module to highest component) Height (H) 2.00 mm typical

CYBLE-212019-00Document Number: 002-09764 Rev. ** Page 4 of 31Figure 1. Module Mechanical DrawingTop ViewSide ViewBottom ViewNote1. No metal should be located beneath or above the antenna area. Only bare PCB material should be located beneath the antenna area. For more information on recommended host PCB layout, see Figure 3 and Figure 4 on page 6.

CYBLE-212019-00Document Number: 002-09764 Rev. ** Page 5 of 31Pad Connection InterfaceAs shown in the bottom view of Figure 1 on page 4, the CYBLE-212019-00 connects to the host board via solder pads on the backside of the module. Tab le 2 and Figure 2 detail the solder pad length, width, and pitch dimensions of the CYBLE-212019-00 module. Figure 2. Solder Pad Dimensions Table 2. Solder Pad Connection DescriptionName Connections Connection Type Pad Length Dimension Pad Width Dimension Pad PitchSP 31 Solder Pads 1.02 mm 0.71 mm 1.27 mm

CYBLE-212019-00Document Number: 002-09764 Rev. ** Page 6 of 31Recommended Host PCB LayoutFigure 3 details the recommended PCB layout pattern for the host PCB.Figure 3. Recommended PCB Layout Pattern for CYBLE-212019-00 ModuleTo maximize RF performance, the host layout should follow these recommendations:1. The ideal placement of the Cypress BLE module is in a corner of the host board with the trace antenna located at the far corner. This placement minimizes the additional recommended keep out area stated in item 2. 2. It is recommended that the area around the Cypress BLE module trace antenna should contain an additional keep out area, where no grounding or signal trace are contained. The keep out area applies to all layers of the host board. The recommended dimensions of the host PCB keep out area are shown in Figure 4 (dimensions are in mm). Figure 4. Recommended Host PCB Keep Out Area Around the CYBLE-212019-00 AntennaTop View (On Host PCB)Host PCB Keep Out Area Around Trace Antenna

CYBLE-212019-00Document Number: 002-09764 Rev. ** Page 7 of 31Table 3 details the solder pad pitch (center-to-center) for each of the neighboring connections. Table 3. Module Solder Pad Connection DimensionsPad X Pad Y Pad Pitch (Pad X - Pad Y) CommentsBottom Right Corner 1 4.88 mm Distance from Bottom Right Corner to Pad 1 center1 2 1.27 mm Distance from Pad 1 center to Pad 2 center2 3 1.27 mm Distance from Pad 2 center to Pad 3 center3 4 1.27 mm Distance from Pad 3 center to Pad 4 center4 5 1.27 mm Distance from Pad 4 center to Pad 5 center5 6 1.27 mm Distance from Pad 5 center to Pad 6 center6 7 1.27 mm Distance from Pad 6 center to Pad 7 center7 8 1.27 mm Distance from Pad 7 center to Pad 8 center8 9 1.27 mm Distance from Pad 8 center to Pad 9 center9 10 1.27 mm Distance from Pad 9 center to Pad 10 center10 11 1.27 mm Distance from Pad 10 center to Pad 11 centerTop Right Corner 12 2.04 mm Distance from Top Right Corner to Pad 12 center12 13 1.27 mm Distance from Pad 12 center to Pad 13 center13 14 1.27 mm Distance from Pad 13 center to Pad 14 center14 15 1.27 mm Distance from Pad 14 center to Pad 15 center15 16 1.27 mm Distance from Pad 15 center to Pad 16 center16 17 1.27 mm Distance from Pad 16 center to Pad 17 center17 18 1.27 mm Distance from Pad 17 center to Pad 18 center18 19 1.27 mm Distance from Pad 18 center to Pad 19 center19 20 1.27 mm Distance from Pad 19 center to Pad 20 center20 21 1.27 mm Distance from Pad 20 center to Pad 21 centerTop Left Corner 22 2.90 mm Distance from Top Left Corner to Pad 22 center22 23 1.27 mm Distance from Pad 22 center to Pad 23 center23 24 1.27 mm Distance from Pad 23 center to Pad 24 center24 25 1.27 mm Distance from Pad 24 center to Pad 25 center25 26 1.27 mm Distance from Pad 25 center to Pad 26 center26 27 1.27 mm Distance from Pad 26 center to Pad 27 center27 28 1.27 mm Distance from Pad 27 center to Pad 28 center28 29 1.27 mm Distance from Pad 28 center to Pad 29 center29 30 1.27 mm Distance from Pad 29 center to Pad 30 center30 31 1.27 mm Distance from Pad 30 center to Pad 31 center31 Bottom Left Corner 4.88 mm Distance from Pad 31 center to Bottom Left Corner

CYBLE-212019-00Document Number: 002-09764 Rev. ** Page 8 of 31Table 4 details the solder pad connection definitions and available functions for each connection pad. Table 4 lists the solder pads on CYBLE-212019-00, the BLE device port-pin, and denotes whether the function shown is available for each solder pad. Each connection is configurable for a single option shown with a 3.Table 4. Solder Pad Connection DefinitionsSolder Pad NumberDevice Port Pin UART SPI I2CTCPWM[2] CapSense WCO Out ECO_OUT LCD SWD GPIO1 XRES External Reset Hardware Connection Input2P4.0[3] 3(RTS) 3(MOSI) 33(CMOD)333P3.73(CTS) 33(Sensor) 33 34P3.63(RTS) 33(Sensor) 335P3.53(TX) 3(SCL) 33(Sensor) 336P3.43(RX) 3(SDA) 33(Sensor) 337P3.33(CTS) 33(Sensor) 338P3.23(RTS) 33(Sensor) 339P2.6 3(Sensor) 3310 VREF Reference Voltage Input (Optional)11 P2.4 3(Sensor) 3312 P2.3 3(Sensor) 33 313 P2.2 3(SS) 3(Sensor) 3314 P2.0 3(SS) 3(Sensor) 3315 VDD Digital Power Supply Input (1.8 to 5.5V)16 P1.7 3(CTS) 3(SCLK) 33(Sensor) 3317 P1.6 3(RTS) 3(SS) 33(Sensor) 3318 P1.5 3(TX) 3(MISO) 3(SCL) 33(Sensor) 3319 P1.4 3(RX) 3(MOSI) 3(SDA) 33(Sensor) 3320 P1.0 33(Sensor) 3321 P0.4 3(RX) 3(MOSI) 3(SDA) 33(Sensor) 33 322 P0.5 3(TX) 3(MISO) 3(SCL) 33(Sensor) 3323 P0.7 3(CTS) 3(SCLK) 33(Sensor) 33(SWDCLK) 324 P0.6 3(RTS) 3(SS) 33(Sensor) 33(SWDIO) 325 GND[4] Ground Connection26 GND Ground Connection27 GND Ground Connection28 GND Ground Connection29 VDDR Radio Power Supply (1.9V to 5.5V)30 P5.03(RX) 3(SS) 3(SDA) 33(Sensor) 3331 P5.1 3(TX) 3(SCLK) 3(SCL) 33(Sensor) 33 3Notes2. TCPWM: Timer, Counter, and Pulse Width Modulator. If supported, the pad can be configured to any of these peripheral functions.3. When using the capacitive sensing functionality, Pad 2 (P4.0) must be connected to a CMOD capacitor (located off of Cypress BLE Module). The value of this capacitor is 2.2 nF and should be placed as close to the module as possible. 4. The main board needs to connect all GND connections (Pad 25/26/27/28) on the module to the common ground of the system. 5. If the I2S feature is used in the design, the I2S pins shall be dynamically routed to the appropriate available GPIO by PSoC Creator

CYBLE-212019-00Document Number: 002-09764 Rev. ** Page 9 of 31Power Supply Connections and Recommended External ComponentsPower ConnectionsThe CYBLE-212019-00 contains two power supply connections, VDD and VDDR. The VDD connection supplies power for both digital and analog device operation. The VDDR connection supplies power for the device radio. VDD accepts a supply range of 1.8 V to 5.5 V. VDDR accepts a supply range of 1.9 V to 5.5 V. These specifications can be found in Table 9. The maximum power supply ripple for both power connections on the module is 100 mV, as shown in Table 7. The power supply ramp rate of VDD must be equal to or greater than that of VDDR. Connection OptionsTwo connection options are available for any application: 1. Single supply: Connect VDD and VDDR to the same supply. 2. Independent supply: Power VDD and VDDR separately. External Component RecommendationIn either connection scenario, it is recommended to place an external ferrite bead between the supply and the module connection. The ferrite bead should be positioned as close as possible to the module pin connection. Figure 5 details the recommended host schematic options for a single supply scenario. The use of one or two ferrite beads will depend on the specific application and configuration of the CYBLE-212019-00.Figure 6 details the recommended host schematic for an independent supply scenario. The recommended ferrite bead value is 330 Ω, 100 MHz. (Murata BLM21PG331SN1D).Figure 5. Recommended Host Schematic Options for a Single Supply OptionFigure 6. Recommended Host Schematic for an Independent Supply OptionTwo Ferrite Bead OptionSingle Ferrite Bead Option1.9V~5.5V Input 1.9V~5.5V Input1.9V~5.5V Input1.8V~5.5V Input

CYBLE-212019-00Document Number: 002-09764 Rev. ** Page 10 of 31The CYBLE-212019-00 schematic is shown in Figure 7.Figure 7. CYBLE-212019-00 Schematic Diagram

CYBLE-212019-00Document Number: 002-09764 Rev. ** Page 11 of 31Critical Components ListTable 5 details the critical components used in the CYBLE-212019-00 module.Table 5. Critical Component ListAntenna DesignTable 6 details trace antenna used in the CYBLE-212019-00 module. For more information, see Table 8.Table 6. Trace Antenna SpecificationsComponent Reference Designator DescriptionSilicon U1 56-pin QFN 256KB flash Programmable Radio-on-Chip (PRoC) with BLE Crystal Y1 24.000 MHz, 10PFCrystal Y2 32.768 kHz, 12.5PFItem DescriptionFrequency Range 2400 – 2500 MHzPeak Gain 0.5 dBi typicalAverage Gain -0.5 dBi typicalReturn Loss 10 dB minimum

CYBLE-212019-00Document Number: 002-09764 Rev. ** Page 12 of 31Electrical SpecificationTable 7 details the absolute maximum electrical characteristics for the Cypress BLE module.Table 7. CYBLE-212019-00 Absolute Maximum RatingsTable 8 details the RF characteristics for the Cypress BLE module.Table 8. CYBLE-212019-00 RF Performance CharacteristicsTable 9 through Table 48 list the module level electrical characteristics for the CYBLE-212019-00. All specifications are valid for –40 °C ≤ TA ≤ 85 °C and TJ ≤ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted.Parameter Description Min Typ Max Units Details/ConditionsVDDD_ABS Analog, digital, or radio supply relative to VSS (VSSD = VSSA)–0.5 – 6 V Absolute maximumVCCD_ABS Direct digital core voltage input relative to VSSD –0.5 – 1.95 V Absolute maximumVDD_RIPPLE Maximum power supply ripple for VDD and VDDR input voltage – – 100 mV3.0V supplyRipple frequency of 100 kHz to 750 kHzVGPIO_ABS GPIO voltage –0.5 – VDD +0.5 V Absolute maximumIGPIO_ABS Maximum current per GPIO –25 – 25 mA Absolute maximumIGPIO_injection GPIO injection current: Maximum for VIH > VDD and minimum for VIL < VSS –0.5 – 0.5 mA Absolute maximum current injected per pinLU Pin current for latch up –200 200 mA –Parameter Description Min Typ Max Units Details/ConditionsRFO RF output power on ANT –18 0 3 dBm Configurable via register settingsRXSRF receive sensitivity on ANT – –91 – dBm Guaranteed by design simulation; High Gain ModeFRModule frequency range 2400 – 2480 MHz –GPPeak gain – 0.5 – dBi –GAvg Average gain – –0.5 – dBi –RL Return loss – –10.5 – dB –Table 9. CYBLE-212019-00 DC SpecificationsParameter Description Min Typ Max Units Details/ConditionsVDD1 Power supply input voltage 1.8 – 5.5 V With regulator enabledVDD2 Power supply input voltage unregulated 1.71 1.8 1.89 V Internally unregulated supplyVDDR1 Radio supply voltage (radio on) 1.9 – 5.5 V –VDDR2 Radio supply voltage (radio off) 1.71 – 5.5 V –Active Mode, VDD = 1.71 V to 5.5 VIDD3 Execute from flash; CPU at 3 MHz – 1.7 – mA T = 25 °C, VDD = 3.3 VIDD4 Execute from flash; CPU at 3 MHz – – – mA T = –40 °C to 85 °CIDD5 Execute from flash; CPU at 6 MHz – 2.5 – mA T = 25 °C, VDD = 3.3 VIDD6 Execute from flash; CPU at 6 MHz – – – mA T = –40 °C to 85 °CIDD7 Execute from flash; CPU at 12 MHz – 4 – mA T = 25 °C, VDD = 3.3 V

CYBLE-212019-00Document Number: 002-09764 Rev. ** Page 13 of 31IDD8 Execute from flash; CPU at 12 MHz – – – mA T = –40 °C to 85 °CIDD9 Execute from flash; CPU at 24 MHz – 7.1 – mA T = 25 °C, VDD = 3.3 VIDD10 Execute from flash; CPU at 24 MHz – – – mA T = –40 °C to 85 °CIDD11 Execute from flash; CPU at 48 MHz – 13.4 – mA T = 25 °C, VDD = 3.3 VIDD12 Execute from flash; CPU at 48 MHz – – – mA T = –40 °C to 85 °CSleep Mode, VDD = 1.8 to 5.5 VIDD13 IMO on – – – mA T = 25 °C, VDD = 3.3 V, SYSCLK = 3 MHzSleep Mode, VDD and VDDR = 1.9 to 5.5 VIDD14 ECO on – – – mA T = 25 °C, VDD = 3.3 V, SYSCLK = 3 MHzDeep-Sleep Mode, VDD = 1.8 to 3.6 VIDD15 WDT with WCO on – 1.5 – µA T = 25 °C,VDD = 3.3 VIDD16 WDT with WCO on – – – µA T = –40 °C to 85 °CIDD17 WDT with WCO on – – – µA T = 25 °C, VDD = 5 VIDD18 WDT with WCO on – – – µA T = –40 °C to 85 °CDeep-Sleep Mode, VDD = 1.71 to 1.89 V (Regulator Bypassed)IDD19 WDT with WCO on – – – µA T = 25 °CIDD20 WDT with WCO on – – – µA T = –40 °C to 85 °CHibernate Mode, VDD = 1.8 to 3.6 VIDD27 GPIO and reset active – 150 – nA T = 25 °C, VDD = 3.3 VIDD28 GPIO and reset active – – – nA T = –40 °C to 85 °CHibernate Mode, VDD = 3.6 to 5.5 VIDD29 GPIO and reset active – – – nA T = 25 °C, VDD = 5 VIDD30 GPIO and reset active – – – nA T = –40 °C to 85 °CStop Mode, VDD = 1.8 to 3.6 VIDD33 Stop-mode current (VDD)–20–nAT = 25 °C, VDD = 3.3 VIDD34 Stop-mode current (VDDR)–40–- nAT = 25 °C, VDDR = 3.3 VIDD35 Stop-mode current (VDD) – – – nA T = –40 °C to 85 °CIDD36 Stop-mode current (VDDR)–––nAT = –40 °C to 85 °C, VDDR = 1.9 V to 3.6 VStop Mode, VDD = 3.6 to 5.5 VIDD37 Stop-mode current (VDD)–––nAT = 25 °C, VDD = 5 VIDD38 Stop-mode current (VDDR)–––nAT = 25 °C, VDDR = 5 VIDD39 Stop-mode current (VDD) – – – nA T = –40 °C to 85 °CIDD40 Stop-mode current (VDDR) – – – nA T = –40 °C to 85 °CTable 9. CYBLE-212019-00 DC Specifications (continued)Parameter Description Min Typ Max Units Details/Conditions

CYBLE-212019-00Document Number: 002-09764 Rev. ** Page 14 of 31Table 10. AC SpecificationsGPIOParameter Description Min Typ Max Units Details/ConditionsFCPU CPU frequency DC – 48 MHz 1.71 V ≤ VDD ≤ 5.5 VTSLEEP Wakeup from Sleep mode – 0 – µs Guaranteed by characterizationTDEEPSLEEP Wakeup from Deep-Sleep mode – – 25 µs 24-MHz IMO. Guaranteed by characterizationTHIBERNATE Wakeup from Hibernate mode – – 2 ms Guaranteed by characterizationTSTOP Wakeup from Stop mode – – 2 ms XRES wakeupTable 11. GPIO DC SpecificationsParameter Description Min Typ Max Units Details/ConditionsVIH[6]Input voltage HIGH threshold 0.7 × VDD – – V CMOS inputLVTTL input, VDD < 2.7 V 0.7 × VDD – – V –LVTTL input, VDD >= 2.7 V 2.0 – – V –VILInput voltage LOW threshold – – 0.3 × VDD VCMOS inputLVTTL input, VDD < 2.7 V – – 0.3× VDD V–LVTTL input, VDD >= 2.7 V – – 0.8 V –VOHOutput voltage HIGH level VDD –0.6 – – V IOH = 4 mA at 3.3-V VDD Output voltage HIGH level VDD –0.5 – – V IOH = 1 mA at 1.8-V VDDVOLOutput voltage LOW level – – 0.6 V IOL = 8 mA at 3.3-V VDDOutput voltage LOW level – – 0.6 V IOL = 4 mA at 1.8-V VDDOutput voltage LOW level – – 0.4 V IOL = 3 mA at 3.3-V VDDRPULLUP Pull-up resistor 3.5 5.6 8.5 kΩ–RPULLDOWN Pull-down resistor 3.5 5.6 8.5 kΩ–IIL Input leakage current (absolute value) – – 2 nA 25 °C, VDD = 3.3 VIIL_CTBM Input leakage on CTBm input pins – – 4 nA –CIN Input capacitance – – 7 pF –VHYSTTL Input hysteresis LVTTL 25 40 – mV VDD > 2.7 VVHYSCMOS Input hysteresis CMOS 0.05 × VDD – – 1 –IDIODE Current through protection diode to VDD/VSS – – 100 µA –ITOT_GPIO Maximum total source or sink chip current – – 200 mA –Note6. VIH must not exceed VDD + 0.2 V.

CYBLE-212019-00Document Number: 002-09764 Rev. ** Page 15 of 31Table 12. GPIO AC SpecificationsXRESParameter Description Min Typ Max Units Details/ConditionsTRISEF Rise time in Fast-Strong mode 2 – 12 ns 3.3-V VDDD, CLOAD = 25 pFTFALLF Fall time in Fast-Strong mode 2 – 12 ns 3.3-V VDDD, CLOAD = 25 pFTRISES Rise time in Slow-Strong mode 10 – 60 ns 3.3-V VDDD, CLOAD = 25 pFTFALLS Fall time in Slow-Strong mode 10 – 60 ns 3.3-V VDDD, CLOAD = 25 pFFGPIOUT1 GPIO Fout; 3.3 V ≤ VDD ≤ 5.5 V Fast-Strong mode ––33MHz90/10%, 25 pF load, 60/40 duty cycleFGPIOUT2 GPIO Fout; 1.7 V≤ VDD ≤ 3.3 V Fast-Strong mode – – 16.7 MHz 90/10%, 25 pF load, 60/40 duty cycleFGPIOUT3 GPIO Fout; 3.3 V ≤ VDD ≤ 5.5 V Slow-Strong mode –– 7 MHz90/10%, 25 pF load, 60/40 duty cycleFGPIOUT4 GPIO Fout; 1.7 V ≤ VDD ≤ 3.3 V Slow-Strong mode ––3.5MHz90/10%, 25 pF load, 60/40 duty cycleFGPIOIN GPIO input operating frequency1.71 V ≤ VDD ≤ 5.5 V – – 48 MHz 90/10% VIOTable 13. OVT GPIO DC Specifications (P5_0 and P5_1 Only)Parameter Description Min Typ Max Units Details/ConditionsIIL Input leakage (absolute value).VIH > VDD – – 10 µA 25°C, VDD = 0 V, VIH = 3.0 VVOL Output voltage LOW level – – 0.4 V IOL = 20 mA, VDD > 2.9 V Table 14. OVT GPIO AC Specifications (P5_0 and P5_1 Only)Parameter Description Min Typ Max Units Details/ConditionsTRISE_OVFS Output rise time in Fast-Strong mode 1.5 – 12 ns 25-pF load, 10%–90%, VDD=3.3 VTFALL_OVFS Output fall time in Fast-Strong mode 1.5 – 12 ns 25-pF load, 10%–90%, VDD=3.3 VTRISESS Output rise time in Slow-Strong mode 10 – 60 ns 25 pF load, 10%-90%, VDD = 3.3 VTFALLSS Output fall time in Slow-Strong mode 10 – 60 ns 25 pF load, 10%-90%, VDD = 3.3 VFGPIOUT1 GPIO FOUT; 3.3 V ≤ VDD ≤ 5.5 VFast-Strong mode ––24MHz90/10%, 25 pF load, 60/40 duty cycleFGPIOUT2 GPIO FOUT; 1.71 V ≤ VDD ≤ 3.3 VFast-Strong mode ––16MHz90/10%, 25 pF load, 60/40 duty cycleTable 15. XRES DC SpecificationsParameter Description Min Typ Max Units Details/ConditionsVIH Input voltage HIGH threshold 0.7 × VDDD – – V CMOS inputVIL Input voltage LOW threshold – – 0.3 × VDDD V CMOS inputRPULLUP Pull-up resistor 3.5 5.6 8.5 kΩ–CIN Input capacitance – 3 – pF –VHYSXRES Input voltage hysteresis – 100 – mV –IDIODE Current through protection diode to VDD/VSS – – 100 µA –

CYBLE-212019-00Document Number: 002-09764 Rev. ** Page 16 of 31Temperature SensorSAR ADCTable 16. XRES AC SpecificationsParameter Description Min Typ Max Units Details/ConditionsTRESETWIDTH Reset pulse width 1 – – µs –Table 17. Temperature Sensor Specifications Parameter Description Min Typ Max Units Details/ConditionsTSENSACC Temperature-sensor accuracy –5 ±1 5 °C –40 to +85 °CTable 18. SAR ADC DC SpecificationsParameter Description Min Typ Max Units Details/ConditionsA_RES Resolution – – 12 bitsA_CHNIS_S Number of channels - single-ended – – 8 8 full-speedA-CHNKS_D Number of channels - differential – – 4 Diff inputs use neighboring I/OA-MONO Monotonicity – – – YesA_GAINERR Gain error – – ±0.1 % With external reference A_OFFSET Input offset voltage – – 2 mV Measured with 1-V VREFA_ISAR Current consumption – – 1 mAA_VINS Input voltage range - single-ended VSS –VDDA VA_VIND Input voltage range - differential VSS – VDDA VA_INRES Input resistance – – 2.2 kΩA_INCAP Input capacitance – – 10 pFVREFSAR Trimmed internal reference to SAR –1 – 1 % Percentage of Vbg (1.024 V)Table 19. SAR ADC AC SpecificationsParameter Description Min Typ Max Units Details/ConditionsA_PSRR Power-supply rejection ratio 70 – – dB Measured at 1-V referenceA_CMRR Common-mode rejection ratio 66 – – dBA_SAMP Sample rate – – 1 Msps 806 Ksps for CYBLE-212019-00 devicesFsarintref SAR operating speed without external ref. bypass– – 100 Ksps 12-bit resolutionA_SNR Signal-to-noise ratio (SNR) 65 – – dB FIN = 10 kHzA_BW Input bandwidth without aliasing – – A_SAMP/2 kHzA_INL Integral nonlinearity. VDD = 1.71 V to 5.5 V, 1 Msps–1.7 – 2 LSB VREF = 1 V to VDDA_INL Integral nonlinearity. VDDD = 1.71 V to 3.6 V, 1 Msps–1.5 – 1.7 LSB VREF = 1.71 V to VDDA_INL Integral nonlinearity. VDD = 1.71 V to 5.5 V, 500 Ksps–1.5 – 1.7 LSB VREF = 1 V to VDD

CYBLE-212019-00Document Number: 002-09764 Rev. ** Page 17 of 31CSDA_dnl Differential nonlinearity. VDD = 1.71 V to 5.5 V, 1 Msps–1 – 2.2 LSB VREF = 1 V to VDDA_DNL Differential nonlinearity. VDD = 1.71 V to 3.6 V, 1 Msps–1 – 2 LSB VREF = 1.71 V to VDDA_DNL Differential nonlinearity. VDD = 1.71 V to 5.5 V, 500 Ksps–1 – 2.2 LSB VREF = 1 V to VDDA_THD Total harmonic distortion – – –65 dB FIN = 10 kHzTable 19. SAR ADC AC Specifications (continued)Parameter Description Min Typ Max Units Details/ConditionsCSD Block SpecificationsParameter Description Min Typ Max Units Details/ConditionsVCSD Voltage range of operation 1.71 – 5.5 VIDAC1 DNL for 8-bit resolution –1 – 1 LSBIDAC1 INL for 8-bit resolution –3 – 3 LSBIDAC2 DNL for 7-bit resolution –1 – 1 LSBIDAC2 INL for 7-bit resolution –3 – 3 LSBSNR Ratio of counts of finger to noise 5 – – Ratio Capacitance range of 9 pF to 35 pF, 0.1-pF sensitivity. Radio is not operating during the scanIDAC1_CRT1 Output current of IDAC1 (8 bits) in High range–612 – µAIDAC1_CRT2 Output current of IDAC1 (8 bits) in Low range–306 – µAIDAC2_CRT1 Output current of IDAC2 (7 bits) in High range–305 – µAIDAC2_CRT2 Output current of IDAC2 (7 bits) in Low range–153 – µA

CYBLE-212019-00Document Number: 002-09764 Rev. ** Page 18 of 31Digital PeripheralsTimer Counter Table 20. Timer DC SpecificationsParameter Description Min Typ Max Units Details/ConditionsITIM1 Block current consumption at 3 MHz – – 42 µA 16-bit timerITIM2 Block current consumption at 12 MHz – – 130 µA 16-bit timerITIM3 Block current consumption at 48 MHz – – 535 µA 16-bit timerTable 21. Timer AC SpecificationsParameter Description Min Typ Max Units Details/ConditionsTTIMFREQ Operating frequency FCLK –48MHzTCAPWINT Capture pulse width (internal) 2 × TCLK ––nsTCAPWEXT Capture pulse width (external) 2 × TCLK ––nsTTIMRES Timer resolution TCLK ––nsTTENWIDINT Enable pulse width (internal) 2 × TCLK ––nsTTENWIDEXT Enable pulse width (external) 2 × TCLK ––nsTTIMRESWINT Reset pulse width (internal) 2 × TCLK ––nsTTIMRESEXT Reset pulse width (external) 2 × TCLK ––nsTable 22. Counter DC SpecificationsParameter Description Min Typ Max Units Details/ConditionsICTR1 Block current consumption at 3 MHz – – 42 µA 16-bit counterICTR2 Block current consumption at 12 MHz – – 130 µA 16-bit counterICTR3 Block current consumption at 48 MHz – – 535 µA 16-bit counterTable 23. Counter AC SpecificationsParameter Description Min Typ Max Units Details/ConditionsTCTRFREQ Operating frequency FCLK –48MHzTCTRPWINT Capture pulse width (internal) 2 × TCLK ––nsTCTRPWEXT Capture pulse width (external) 2 × TCLK ––nsTCTRES Counter Resolution TCLK ––nsTCENWIDINT Enable pulse width (internal) 2 × TCLK ––nsTCENWIDEXT Enable pulse width (external) 2 × TCLK ––nsTCTRRESWINT Reset pulse width (internal) 2 × TCLK ––nsTCTRRESWEXT Reset pulse width (external) 2 × TCLK –– ns

CYBLE-212019-00Document Number: 002-09764 Rev. ** Page 19 of 31Pulse Width Modulation (PWM) LCD Direct Drive Table 24. PWM DC SpecificationsParameter Description Min Typ Max Units Details/ConditionsIPWM1 Block current consumption at 3 MHz – – 42 µA 16-bit PWMIPWM2 Block current consumption at 12 MHz – – 130 µA 16-bit PWMIPWM3 Block current consumption at 48 MHz – – 535 µA 16-bit PWMTable 25. PWM AC SpecificationsParameter Description Min Typ Max Units Details/ConditionsTPWMFREQ Operating frequency FCLK –48MHzTPWMPWINT Pulse width (internal) 2 × TCLK ––nsTPWMEXT Pulse width (external) 2 × TCLK ––nsTPWMKILLINT Kill pulse width (internal) 2 × TCLK ––nsTPWMKILLEXT Kill pulse width (external) 2 × TCLK ––nsTPWMEINT Enable pulse width (internal) 2 × TCLK ––nsTPWMENEXT Enable pulse width (external) 2 × TCLK ––nsTPWMRESWINT Reset pulse width (internal) 2 × TCLK ––nsTPWMRESWEXT Reset pulse width (external) 2 × TCLK ––nsTable 26. LCD Direct Drive DC SpecificationsParameter Description Min Typ Max Units Details/ConditionsILCDLOW Operating current in low-power mode – 17.5 – µA 16 × 4 small segment display at 50 HzCLCDCAP LCD capacitance per segment/common driver– 500 5000 pFLCDOFFSET Long-term segment offset – 20 – mVILCDOP1 LCD system operating currentVBIAS = 5 V – 2 – mA 32 × 4 segments. 50 Hz at 25 °CILCDOP2 LCD system operating currentVBIAS = 3.3 V– 2 – mA 32 × 4 segments50 Hz at 25 °CTable 27. LCD Direct Drive AC SpecificationsParameter Description Min Typ Max Units Details/ConditionsFLCD LCD frame rate 10 50 150 Hz

CYBLE-212019-00Document Number: 002-09764 Rev. ** Page 20 of 31Serial CommunicationTable 28. Fixed I2C DC SpecificationsTable 30. Fixed UART DC SpecificationsTable 31. Fixed UART AC SpecificationsParameter Description Min Typ Max Units Details/ConditionsII2C1 Block current consumption at 100 kHz – – 50 µA –II2C2 Block current consumption at 400 kHz – – 155 µA –II2C3 Block current consumption at 1 Mbps – – 390 µA –II2C4 I2C enabled in Deep-Sleep mode – – 1.4 µA –Table 29. Fixed I2C AC SpecificationsParameter Description Min Typ Max Units Details/ConditionsFI2C1 Bit rate – – 400 kHzParameter Description Min Typ Max Units Details/ConditionsIUART1 Block current consumption at 100 kbps – – 55 µA –IUART2 Block current consumption at 1000 kbps – – 312 µA –Parameter Description Min Typ Max Units Details/ConditionsFUART Bit rate – – 1 Mbps –Table 32. Fixed SPI DC SpecificationsParameter Description Min Typ Max Units Details/ConditionsISPI1 Block current consumption at 1 Mbps – – 360 µA –ISPI2 Block current consumption at 4 Mbps – – 560 µA –ISPI3 Block current consumption at 8 Mbps – – 600 µA –Table 33. Fixed SPI AC SpecificationsParameter Description Min Typ Max Units Details/ConditionsFSPI SPI operating frequency (master; 6x over sampling) – – 8 MHz –Table 34. Fixed SPI Master Mode AC SpecificationsParameter Description Min Typ Max Units Details/ConditionsTDMO MOSI valid after SCLK driving edge – – 18 ns –TDSI MISO valid before SCLK capturing edge Full clock, late MISO sampling used 20 – – ns Full clock, late MISO samplingTHMO Previous MOSI data hold time 0 – – ns Referred to Slave capturing edgeTable 35. Fixed SPI Slave Mode AC SpecificationsParameter Description Min Typ Max UnitsTDMI MOSI valid before SCLK capturing edge 40 – – nsTDSO MISO valid after SCLK driving edge – – 42 + 3 × TCPU nsTDSO_ext MISO Valid after SCLK driving edge in external clock mode. VDD < 3.0 V – – 50 nsTHSO Previous MISO data hold time 0 – – nsTSSELSCK SSEL valid to first SCK valid edge 100 – – ns

CYBLE-212019-00Document Number: 002-09764 Rev. ** Page 21 of 31MemorySystem ResourcesPower-on-Reset (POR) Table 36. Flash DC SpecificationsParameter Description Min Typ Max Units Details/ConditionsVPE Erase and program voltage 1.71 – 5.5 V –TWS48 Number of Wait states at 32–48 MHz 2 – – CPU execution from flashTWS32 Number of Wait states at 16–32 MHz 1 – – CPU execution from flashTWS16 Number of Wait states for 0–16 MHz 0 – – CPU execution from flashTable 37. Flash AC SpecificationsParameter Description Min Typ Max Units Details/ConditionsTROWWRITE[7] Row (block) write time (erase and program) – – 20 ms Row (block) = 256 bytesTROWERASE[7] Row erase time – – 13 ms –TROWPROGRAM[7] Row program time after erase – – 7 ms –TBULKERASE[7] Bulk erase time (256 KB) – – 35 ms –TDEVPROG[7] Total device program time – – 25 seconds –FEND Flash endurance 100 K – – cycles –FRET Flash retention. TA ≤ 55 °C, 100 K P/E cycles 20 – – years –FRET2 Flash retention. TA ≤ 85 °C, 10 K P/E cycles 10 – – years –Note7. It can take as much as 20 ms to write to flash. During this time, the device should not be reset, or flash operations will be interrupted and cannot be relied on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs. Make certain that these are not inadvertently activated.Table 38. POR DC SpecificationsParameter Description Min Typ Max Units Details/ConditionsVRISEIPOR Rising trip voltage 0.80 – 1.45 V –VFALLIPOR Falling trip voltage 0.75 – 1.40 V –VIPORHYST Hysteresis 15 – 200 mV –Table 39. POR AC SpecificationsParameter Description Min Typ Max Units Details/ConditionsTPPOR_TR Precision power-on reset (PPOR) response time in Active and Sleep modes ––1µs –Table 40. Brown-Out DetectParameter Description Min Typ Max Units Details/ConditionsVFALLPPOR BOD trip voltage in Active and Sleep modes 1.64 – – V –VFALLDPSLP BOD trip voltage in Deep Sleep 1.4 – – V –Table 41. Hibernate ResetParameter Description Min Typ Max Units Details/ConditionsVHBRTRIP BOD trip voltage in Hibernate 1.1 – – V –

CYBLE-212019-00Document Number: 002-09764 Rev. ** Page 22 of 31Voltage Monitors (LVD) SWD Interface Table 42. Voltage Monitor DC SpecificationsParameter Description Min Typ Max Units Details/ConditionsVLVI1 LVI_A/D_SEL[3:0] = 0000b 1.71 1.75 1.79 V –VLVI2 LVI_A/D_SEL[3:0] = 0001b 1.76 1.80 1.85 V –VLVI3 LVI_A/D_SEL[3:0] = 0010b 1.85 1.90 1.95 V –VLVI4 LVI_A/D_SEL[3:0] = 0011b 1.95 2.00 2.05 V –VLVI5 LVI_A/D_SEL[3:0] = 0100b 2.05 2.10 2.15 V –VLVI6 LVI_A/D_SEL[3:0] = 0101b 2.15 2.20 2.26 V –VLVI7 LVI_A/D_SEL[3:0] = 0110b 2.24 2.30 2.36 V –VLVI8 LVI_A/D_SEL[3:0] = 0111b 2.34 2.40 2.46 V –VLVI9 LVI_A/D_SEL[3:0] = 1000b 2.44 2.50 2.56 V –VLVI10 LVI_A/D_SEL[3:0] = 1001b 2.54 2.60 2.67 V –VLVI11 LVI_A/D_SEL[3:0] = 1010b 2.63 2.70 2.77 V –VLVI12 LVI_A/D_SEL[3:0] = 1011b 2.73 2.80 2.87 V –VLVI13 LVI_A/D_SEL[3:0] = 1100b 2.83 2.90 2.97 V –VLVI14 LVI_A/D_SEL[3:0] = 1101b 2.93 3.00 3.08 V –VLVI15 LVI_A/D_SEL[3:0] = 1110b 3.12 3.20 3.28 V –VLVI16 LVI_A/D_SEL[3:0] = 1111b 4.39 4.50 4.61 V –LVI_IDD Block current – – 100 µA –Table 43. Voltage Monitor AC SpecificationsParameter Description Min Typ Max Units Details/ConditionsTMONTRIP Voltage monitor trip time – – 1 µs –Table 44. SWD Interface SpecificationsParameter Description Min Typ Max Units Details/ConditionsF_SWDCLK1 3.3 V ≤ VDD ≤ 5.5 V – – 14 MHz SWDCLK ≤ 1/3 CPU clock frequencyF_SWDCLK2 1.71 V ≤ VDD ≤ 3.3 V – – 7 MHz SWDCLK ≤ 1/3 CPU clock frequencyT_SWDI_SETUP T = 1/f SWDCLK 0.25 × T – – ns –T_SWDI_HOLD T = 1/f SWDCLK 0.25 × T – – ns –T_SWDO_VALID T = 1/f SWDCLK – – 0.5 × T ns –T_SWDO_HOLD T = 1/f SWDCLK 1 – – ns –

CYBLE-212019-00Document Number: 002-09764 Rev. ** Page 23 of 31Internal Main OscillatorInternal Low-Speed Oscillator Table 49. ECO Trim Value SpecificationTable 45. IMO DC SpecificationsParameter Description Min Typ Max Units Details/ConditionsIIMO1 IMO operating current at 48 MHz – – 1000 µA –IIMO2 IMO operating current at 24 MHz – – 325 µA –IIMO3 IMO operating current at 12 MHz – – 225 µA –IIMO4 IMO operating current at 6 MHz – – 180 µA –IIMO5 IMO operating current at 3 MHz – – 150 µA –Table 46. IMO AC SpecificationsParameter Description Min Typ Max Units Details/ConditionsFIMOTOL3 Frequency variation from 3 to 48 MHz – – ±2 % With API-called calibrationFIMOTOL3 IMO startup time – 12 – µs –Table 47. ILO DC SpecificationsParameter Description Min Typ Max Units Details/ConditionsIILO2 ILO operating current at 32 kHz – 0.3 1.05 µA –Table 48. ILO AC SpecificationsParameter Description Min Typ Max Units Details/ConditionsTSTARTILO1 ILO startup time – – 2 ms –FILOTRIM1 32-kHz trimmed frequency 15 32 50 kHz –Parameter Description Value Details/ConditionsECOTRIM 24-MHz trim value (firmware configuration) 0x00003FFA Optimum trim value that needs to be loaded to register CY_SYS_XTAL_BLERD_BB_XO_CAPTRIM_REG

CYBLE-212019-00Document Number: 002-09764 Rev. ** Page 24 of 31Environmental SpecificationsEnvironmental ComplianceThis Cypress BLE module is built in compliance with the Restriction of Hazardous Substances (RoHS) and Halogen Free (HF) directives. The Cypress module and components used to produce this module are RoHS and HF compliant.RF CertificationThe CYBLE-212019-00 module will be certified under the following RF certification standards at production release.nFCC: WAP2011nCEnIC: 7922A-2011nMIC: TBDnKC: MSIP-CRM-Cyp-2011Environmental ConditionsTable 50 describes the operating and storage conditions for the Cypress BLE module.Table 50. Environmental Conditions for CYBLE-212019-00ESD and EMI ProtectionExposed components require special attention to ESD and electromagnetic interference (EMI).A grounded conductive layer inside the device enclosure is suggested for EMI and ESD performance. Any openings in the enclosure near the module should be surrounded by a grounded conductive layer to provide ESD protection and a low-impedance path to ground. Device Handling: Proper ESD protocol must be followed in manufacturing to ensure component reliability.Description Minimum Specification Maximum SpecificationOperating temperature -40 °C 85 °COperating humidity (relative, non-condensation) 5% 85%Thermal ramp rate – 3 °C/minuteStorage temperature –40 °C 85 °CStorage temperature and humidity – 85 ° C at 85%ESD: Module integrated into system Components[8] –15 kV Air2.2 kV ContactNote8. This does not apply to the RF pins (ANT, XTALI, and XTALO). RF pins (ANT, XTALI, and XTALO) are tested for 500-V HBM.

CYBLE-212019-00Document Number: 002-09764 Rev. ** Page 25 of 31Regulatory InformationFCCFCC NOTICE:The device CYBLE-212019-00 complies with Part 15 of the FCC Rules. The device meets the requirements for modular transmitter approval as detailed in FCC public Notice DA00-1407.transmitter Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause undesired operation.CAUTION:The FCC requires the user to be notified that any changes or modifications made to this device that are not expressly approved by Cypress Semiconductor may void the user's authority to operate the equipment.This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions,ê may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures:nReorient or relocate the receiving antenna. nIncrease the separation between the equipment and receiver. nConnect the equipment into an outlet on a circuit different from that to which the receiver is connected. nConsult the dealer or an experienced radio/TV technician for help LABELING REQUIREMENTS:The Original Equipment Manufacturer (OEM) must ensure that FCC labelling requirements are met. This includes a clearly visible label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor FCC identifier for this product as well as the FCC Notice above. The FCC identifier is FCC ID: WAP2011.In any case the end product must be labeled exterior with "Contains FCC ID: WAP2011"ANTENNA WARNING: This device is tested with a standard SMA connector and with the antennas listed below. When integrated in the OEMs product, these fixed antennas require installation preventing end-users from replacing them with non-approved antennas. Any antenna not in the following table must be tested to comply with FCC Section 15.203 for unique antenna connectors and Section 15.247 for emissions.RF EXPOSURE: To comply with FCC RF Exposure requirements, the Original Equipment Manufacturer (OEM) must ensure to install the approved antenna in the previous.The preceding statement must be included as a CAUTION statement in manuals, for products operating with the approved antennas in Table 6 on page 11, to alert users on FCC RF Exposure compliance. Any notification to the end user of installation or removal instructions about the integrated radio module is not allowed.The radiated output power of CYBLE-212019-00 with the trace antenna is far below the FCC radio frequency exposure limits. Nevertheless, use CYBLE-212019-00 in such a manner that minimizes the potential for human contact during normal operation. End users may not be provided with the module installation instructions. OEM integrators and end users must be provided with transmitter operating conditions for satisfying RF exposure compliance.

CYBLE-212019-00Document Number: 002-09764 Rev. ** Page 26 of 31Industry Canada (IC) CertificationCYBLE-212019-00 is licensed to meet the regulatory requirements of Industry Canada (IC), License: IC: 7922A-2011Manufacturers of mobile, fixed or portable devices incorporating this module are advised to clarify any regulatory questions and ensure compliance for SAR and/or RF exposure limits. Users can obtain Canadian information on RF exposure and compliance from www.ic.gc.ca.This device has been designed to operate with the antennas listed in Table 6 on page 11, having a maximum gain of 0.5 dBi. Antennas not included in this list or having a gain greater than 0.5 dBi are strictly prohibited for use with this device. The required antenna impedance is 50 ohms. The antenna used for this transmitter must not be co-located or operating in conjunction with any other antenna or transmitter.IC NOTICE:The device CYBLE-212019-00 including the built-in trace antenna complies with Canada RSS-GEN Rules. The device meets the requirements for modular transmitter approval as detailed in RSS-GEN. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause undesired operation.IC RADIATION EXPOSURE STATEMENT FOR CANADAThis device complies with Industry Canada licence-exempt RSS standard(s). Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation of the device.Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation est autorisée aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.LABELING REQUIREMENTS:The Original Equipment Manufacturer (OEM) must ensure that IC labelling requirements are met. This includes a clearly visible label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor IC identifier for this product as well as the IC Notice above. The IC identifier is 7922A-2011. In any case, the end product must be labeled in its exterior with "Contains IC: 7922A-2011"European R&TTE Declaration of ConformityHereby, Cypress Semiconductor declares that the Bluetooth module CYBLE-212019-00 complies with the essential requirements and other relevant provisions of Directive 1999/5/EC. As a result of the conformity assessment procedure described in Annex III of the Directive 1999/5/EC, the end-customer equipment should be labeled as follows: All versions of the CYBLE-212019-00 in the specified reference design can be used in the following countries: Austria, Belgium, Cyprus, Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Ireland, Italy, Latvia, Lithuania, Luxem-bourg, Malta, Poland, Portugal, Slovakia, Slovenia, Spain, Sweden, The Netherlands, the United Kingdom, Switzerland, and Norway.

CYBLE-212019-00Document Number: 002-09764 Rev. ** Page 27 of 31MIC JapanCYBLE-212019-00 is certified as a module with type certification number TBD. End products that integrate CYBLE-212019-00 do not need additional MIC Japan certification for the end product.End product can display the certification label of the embedded module.KC KoreaCYBLE-212019-00 is certified for use in Korea with certificate number MSIP-CRM-Cyp-2011.

CYBLE-212019-00Document Number: 002-09764 Rev. ** Page 28 of 31Ordering InformationThe CYBLE-212019-00 is avialable in certified and uncertified options. The avialable part numbers and features are listed in the belowtable. Part Numbering ConventionThe part numbers are of the form CYBLE-ABCDEF-GH where the fields are defined as follows.For additional information and a complete list of Cypress Semiconductor BLE products, contact your local Cypress sales representative. To locate the nearest Cypress office, visit our website.Part NumberCPU Speed (MHz)Flash Size (KB)CapSense SCB TCPWM12-Bit SAR ADCI2SLCD Package Packing ShieldCYBLE-212019-00 48 256 Yes 2 4 1 Msps Yes Yes 31-SMT Tape and Reel YesU.S. Cypress Headquarters Address 198 Champion Court, San Jose, CA 95134U.S. Cypress Headquarter Contact Info (408) 943-2600Cypress website address http://www.cypress.com

CYBLE-212019-00Document Number: 002-09764 Rev. ** Page 29 of 31AcronymsDocument ConventionsUnits of MeasureAcronym DescriptionBLE Bluetooth Low EnergyBluetooth SIG Bluetooth Special Interest GroupCE European ConformityCSA Canadian Standards AssociationEMI electromagnetic interferenceESD electrostatic dischargeFCC Federal Communications CommissionGPIO general-purpose input/outputIC Industry CanadaIDE integrated design environmentKC Korea CertificationMIC Ministry of Internal Affairs and Communications (Japan)PCB printed circuit boardRX receiveQDID qualification design IDSMT surface-mount technology; a method for producing electronic circuitry in which the components are placed directly onto the surface of PCBsTCPWM timer, counter, pulse width modulator (PWM)TUV Germany: Technischer Überwachungs-Verein (Technical Inspection Association)TX transmitSymbol Unit of Measure°C degree CelsiuskV kilovoltmA milliamperesmm millimetersmV millivoltµA microamperesµm micrometersMHz megahertzGHz gigahertzVvolt

CYBLE-212019-00Document Number: 002-09764 Rev. ** Page 30 of 31Document History Page Document Title: CYBLE-212019-00 Bluetooth® Low Energy (BLE) ModuleDocument Number: 002-09764Revision ECN Orig. of ChangeSubmission Date Description of Change** MINS 11/1/2015 Preliminary datasheet for CYBLE-212019-00 module.

Document Number: 002-09764 Rev. ** Revised November 4, 2015 Page 31 of 31All products and company names mentioned in this document may be the trademarks of their respective holders.CYBLE-212019-00© Cypress Semiconductor Corporation, 2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of anycircuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as criticalcomponents in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systemsapplication implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypressintegrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited withoutthe express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIESOF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does notassume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems wherea malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturerassumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Sales, Solutions, and Legal InformationWorldwide Sales and Design SupportCypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.ProductsAutomotive cypress.com/go/automotiveClocks & Buffers cypress.com/go/clocksInterface cypress.com/go/interfaceLighting & Power Control cypress.com/go/powerpsocMemory cypress.com/go/memoryPSoC cypress.com/go/psocTouch Sensing cypress.com/go/touchUSB Controllers cypress.com/go/USBWireless/RF cypress.com/go/wirelessPSoC® Solutionspsoc.cypress.com/solutionsPSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LPCypress Developer CommunityCommunity | Forums | Blogs | Video | Training Technical Supportcypress.com/go/support

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