Cypress Semiconductor 4008 Bluetooth Module User Manual II

Cypress Semiconductor Bluetooth Module II

Contents

User Manual II

PRELIMINARY CYBLE-214009-00EZ-BLETM PSoC® ModuleCypress Semiconductor Corporation 198 Champion Court San Jose,CA 95134-1709 408-943-2600Document Number: 002-09714 Rev. ** Revised October 29, 2015General DescriptionThe Cypress CYBLE-214009-00 is a fully certified and qualifiedmodule supporting Bluetooth Low Energy (BLE) wirelesscommunication. The CYBLE-214009-00 is a turnkey solutionand includes onboard crystal oscillators, trace antenna, passivecomponents, and the Cypress PSoC® 4 BLE. Refer to thePSoC® 4 BLE datasheet for additional details on the capabilitiesof the PSoC® 4 BLE device used on this module.The EZ-BLETM PSoC® module is a scalable and reconfigurableplatform architecture. It combines programmable andreconfigurable analog and digital blocks with flexible automaticrouting. The CYBLE-214009-00 also includes digitalprogrammable logic, high-performance analog-to-digitalconversion (ADC), opamps with comparator mode, and standardcommunication and timing peripherals. The CYBLE-214009-00 includes a royalty-free BLE stackcompatible with Bluetooth 4.1 and provides up to 25 GPIOs in asmall 11 × 11 × 1.80 mm package. The CYBLE-214009-00 is a complete solution and an ideal fit forapplications seeking a highly integrated BLE wireless solution.CYBLE-214009-00 is drop-in compatible CYBLE-014008-00.Module DescriptionnModule size: 11.0 mm × 11.0 mm × 1.80 mm (with shield)nBluetooth 4.1 single-mode modulenIndustrial temperature range: –40 °C to +85 °Cn32-bit processor (0.9 DMIPS/MHz) with single-cycle 32-bit multiply, operating at up to 48 MHzn256-KB flash memory, 32-KB SRAM memorynWatchdog timer with dedicated internal low-speed oscillator (ILO)nTwo-pin SWD for programmingnUp to 25 GPIOs configurable as open drain high/low, pull-up/pull-down, HI-Z analog, HI-Z digial, or strong outputnCertified to FCC, CE, MIC, KC, and IC regulationsnBluetooth SIG 4.1 qualifiedPower ConsumptionnTX output power: –18 dbm to +3 dbmnReceived signal strength indicator (RSSI) with 1-dB resolutionnTX current consumption of 15.6 mA (radio only, 0 dbm)nRX current consumption of 16.4 mA (radio only)nLow power mode supportpDeep Sleep: 1.3 µA with watch crystal oscillator (WCO) onpHibernate: 150 nA with SRAM retentionpStop: 60 nA with XRES wakeupProgrammable AnalognFour opamps with reconfigurable high-drive external and high-bandwidth internal drive, comparator modes, and ADC input buffering capability; can operate in Deep-Sleep mode.n12-bit, 1-Msps SAR ADC with differential and single-ended modes; channel sequencer with signal averagingnTwo current DACs (IDACs) for general-purpose or capacitive sensing applications on any pinnOne low-power comparator that operate in Deep-Sleep modeProgrammable DigitalnFour programmable logic blocks called universal digital blocks, (UDBs), each with eight macrocells and datapathnCypress-provided peripheral Component library, user-defined state machines, and Verilog inputCapacitive Sensing nCypress CapSense Sigma-Delta (CSD) provides best-in-class SNR (> 5:1) and liquid tolerancenCypress-supplied software component makes capacitive-sensing design easynAutomatic hardware-tuning algorithm (SmartSense™)Segment LCD DrivenLCD drive supported on all GPIOs (common or segment)nOperates in Deep-Sleep mode with four bits per pin memorySerial CommunicationnTwo independent runtime reconfigurable serial communication blocks (SCBs) with I2C, SPI, or UART functionalityTiming and Pulse-Width ModulationnFour 16-bit timer, counter, pulse-width modulator (TCPWM) blocksnCenter-aligned, Edge, and Pseudo-random modesnComparator-based triggering of Kill signals for motor drive and other high-reliability digital logic applicationsUp to 25 Programmable GPIOs nAny GPIO pin can be CapSense, LCD, analog, or digitalnTwo overvoltage-tolerant (OVT) pins; drive modes, strengths, and slew rates are programmable
PRELIMINARY CYBLE-214009-00Document Number: 002-09714 Rev. ** Page 2 of 40ContentsOverview............................................................................ 3Module Description...................................................... 3Pad Connection Interface ................................................ 5Recommended Host PCB Layout ................................... 6Power Supply Connections and Recommended External Components.................................................................... 10Connection Options................................................... 10External Component Recommendation .................... 10Critical Components List ........................................... 13Antenna Design......................................................... 13Electrical Specification .................................................. 14GPIO ......................................................................... 16XRES......................................................................... 17Analog Peripherals .................................................... 17Digital Peripherals ..................................................... 21Serial Communication ............................................... 23Memory ..................................................................... 24System Resources .................................................... 24Environmental Specifications ....................................... 30Environmental Compliance ....................................... 30RF Certification.......................................................... 30Environmental Conditions ......................................... 30ESD and EMI Protection ........................................... 30Regulatory Information .................................................. 31FCC........................................................................... 31Industry Canada (IC) Certification............................. 32European R&TTE Declaration of Conformity ............ 32MIC Japan................................................................. 33KC Korea................................................................... 33Ordering Information...................................................... 34Part Numbering Convention...................................... 34Acronyms........................................................................ 35Document Conventions ................................................. 37Units of Measure ....................................................... 37Errata ............................................................................... 38Document History Page................................................. 39Sales, Solutions, and Legal Information ...................... 40Worldwide Sales and Design Support....................... 40Products .................................................................... 40PSoC® Solutions ...................................................... 40Cypress Developer Community................................. 40Technical Support ..................................................... 40
PRELIMINARY CYBLE-214009-00Document Number: 002-09714 Rev. ** Page 3 of 40OverviewModule DescriptionThe CYBLE-214009-00 module is a complete module designed to be soldered to the main host board. Module Dimensions and DrawingCypress reserves the right to select components (including the appropriate BLE device) from various vendors to achieve the BLE module functionality. Such selections will guarantee that all height restrictions of the component area are maintained. Designs should be completed with the physical dimensions shown in the mechanical drawings in Figure 1. All dimensions are in millimeters (mm).Table 1. Module Design DimensionsSee Figure 1 on page 4 for the mechanical reference drawing for CYBLE-214009-00.Dimension Item SpecificationModule dimensions Length (X) 11.00 ± 0.15 mmWidth (Y) 11.00 ± 0.15 mmAntenna location dimensions Length (X) 11.00 ± 0.15 mmWidth (Y) 4.62 ± 0.15 mmPCB thickness Height (H) 0.80 ± 0.10 mmShield height Height (H) 1.00 ± 0.10 mmMaximum component height Height (H) 1.00 mm typical (shield)Total module thickness (bottom of module to highest component) Height (H) 1.80 mm typical
PRELIMINARY CYBLE-214009-00Document Number: 002-09714 Rev. ** Page 4 of 40Figure 1. Module Mechanical DrawingTop ViewSide ViewBottom ViewNote1. No metal should be located beneath or above the antenna area. Only bare PCB material should be located beneath the antenna area. For more information on recommended host PCB layout, see Figure 3 and Figure 4 on page 6.
PRELIMINARY CYBLE-214009-00Document Number: 002-09714 Rev. ** Page 5 of 40Pad Connection InterfaceAs shown in the bottom view of Figure 1 on page 4, the CYBLE-214009-00 connects to the host board via solder pads on the back of the module. Table 2 and Figure 2 detail the solder pad length, width, and pitch dimensions of the CYBLE-214009-00 module. Figure 2. Solder Pad Dimensions Table 2. Solder Pad Connection DescriptionName Connections Connection Type Pad Length Dimension Pad Width Dimension Pad PitchSP 32 Solder Pads Pad9/Pad24: 0.74 mmAll Others: 0.79 mm 0.41 mm 0.66 mm
PRELIMINARY CYBLE-214009-00Document Number: 002-09714 Rev. ** Page 6 of 40Recommended Host PCB LayoutFigure 3 details the recommended PCB layout pattern for the host PCB. Dimensions are in mm. Figure 3. Recommended PCB Layout Pattern for CYBLE-214009-00To maximize RF performance, the host layout should follow these recommendations:1. The ideal placement of the Cypress BLE module is in a corner of the host board with the antenna located on the edge of the host board. This placement minimizes the additional recommended keep-out area stated in item 2. 2. It is recommended that the area around the Cypress BLE module trace antenna should contain an additional keep-out area, where no grounding or signal traces are contained. The keep-out area applies to all layers of the host board. The recommended dimensions of the host PCB keep-out area are shown in Figure 4 (dimensions are in mm). Figure 4. Recommended Host PCB Keep-Out Area Around the CYBLE-214009-00 Trace AntennaTop View (On Host PCB)Host PCB Keep-Out Area Around Trace Antenna
PRELIMINARY CYBLE-214009-00Document Number: 002-09714 Rev. ** Page 7 of 40Table 3 details the solder pad pitch (center-to-center) for each of the neighboring connections. Table 3. Module Solder Pad Connection DimensionsPad X Pad Y Pad Pitch (Pad X - Pad Y) CommentsBottom Right Corner 1 4.83 mm Distance from bottom right corner to Pad 1 center1 2 0.66 mm Distance from Pad 1 center to Pad 2 center2 3 0.66 mm Distance from Pad 2 center to Pad 3 center3 4 0.66 mm Distance from Pad 3 center to Pad 4 center4 5 0.66 mm Distance from Pad 4 center to Pad 5 center5 6 0.66 mm Distance from Pad 5 center to Pad 6 center6 7 0.66 mm Distance from Pad 6 center to Pad 7 center7 8 0.66 mm Distance from Pad 7 center to Pad 8 center8 9 0.66 mm Distance from Pad 8 center to Pad 9 centerTop Right Corner 10 1.21 mm Distance from Pad 9 center to Pad 10 center10 11 0.66 mm Distance from Pad 10 center to Pad 11 center11 12 0.66 mm Distance from Pad 11 center to Pad 12 center12 13 0.66 mm Distance from Pad 12 center to Pad 13 center13 14 0.66 mm Distance from Pad 13 center to Pad 14 center14 15 0.66 mm Distance from Pad 14 center to Pad 15 center15 16 0.66 mm Distance from Pad 15 center to Pad 16 center16 17 0.66 mm Distance from Pad 16 center to Pad 17 center17 18 0.66 mm Distance from Pad 17 center to Pad 18 center18 19 0.66 mm Distance from Pad 18 center to Pad 19 center19 20 0.66 mm Distance from Pad 19 center to Pad 20 center20 21 0.66 mm Distance from Pad 20 center to Pad 21 center21 22 0.66 mm Distance from Pad 21 center to Pad 22 center22 23 0.66 mm Distance from Pad 22 center to Pad 23 centerTop Left Corner 24 0.89 mm Distance from Top Left Corner to Pad 24 center24 25 0.66 mm Distance from Pad 24 center to Pad 25 center25 26 0.66 mm Distance from Pad 25 center to Pad 26 center26 27 0.66 mm Distance from Pad 26 center to Pad 27 center27 28 0.66 mm Distance from Pad 27 center to Pad 28 center28 29 0.66 mm Distance from Pad 28 center to Pad 29 center29 30 0.66 mm Distance from Pad 29 center to Pad 30 center30 31 0.66 mm Distance from Pad 30 center to Pad 31 center31 32 0.66 mm Distance from Pad 31 center to Pad 32 center32 Bottom Left Corner 4.83 mm Distance from Pad 32 center to Bottom Left Corner
PRELIMINARY CYBLE-214009-00Document Number: 002-09714 Rev. ** Page 8 of 40Table 4 and Ta ble 5 detail the solder pad connection definitions and available functions for each connection pad. Table 4 lists the solder pads on CYBLE-214009-00, the BLE device port-pin, and denotes whether the digital function shown is available for each solder pad. Table 5 denotes whether the analog function shown is available for each solder pad. Each connection is configurable for a single option shown with a 3.Table 4. Digital Peripheral CapabilitiesPad NumberDevice Port Pin UART SPI I2CTCPWM[2] Cap- SenseWCO OutECO OUT LCD SWD GPIO1GND[3] Ground Connection2P1.1 3(SCB1_SS1) 3(TCPWM0) 3333P1.0 3(TCPWM0) 3334P1.53(SCB0_TX) 3(SCB0_MISO) 3(SCB0_SCL) 3(TCPWM2) 3335P0.13(SCB1_TX) 3(SCB1_MISO) 3(SCB1_SCL) 3(TCPWM0) 3336P0.73(SCB0_CTS) 3(SCB0_SCLK) 3(TCPWM2) 333(SWDCLK)37 VDD Digital Power Supply Input (1.71 to 5.5V)8P1.43(SCB0_RX) 3(SCB0_MOSI) 3(SCB0_SDA) 3(TCPWM2) 3339P0.43(SCB0_RX) 3(SCB0_MOSI) 3(SCB0_SDA) 3(TCPWM1) 333 310 P0.5 3(SCB0_TX) 3(SCB0_MISO) 3(SCB0_SCL) 3(TCPWM1) 33311 P0.6 3(SCB0_RTS) 3(SCB0_SS0) 3(TCPWM2) 333(SWDIO)312 P1.2 3(SCB1_SS2) 3(TCPWM1) 33313 VDDR Radio Power Supply (1.9V to 5.5V)14 P2.6 33315 P1.3 3(SCB1_SS3) 3(TCPWM1) 33316 P3.0 3(SCB0_RX) 3(SCB0_SDA) 3(TCPWM0) 33317 P2.1 3(SCB0_SS2) 33318 P2.2 3(SCB0_SS3) 33319 P2.3 33 3 320 VDDA Analog Power Supply Input (1.71 to 5.5V)21 P3.4 3(SCB1_RX) 3(SCB1_SDA) 3(TCPWM2) 33322 P3.1 3(SCB0_TX) 3(SCB0_SCL) 3(TCPWM0) 33323 P3.7 3(SCB1_CTS) 3(TCPWM3) 33 3 324 P3.5 3(SCB1_TX) 3(SCB1_SCL) 3(TCPWM2) 33325 P3.3 3(SCB0_CTS) 3(TCPWM1) 33326 VREF Reference Voltage Input27 P3.2 3(SCB0_RTS) 3(TCPWM1) 33328 P3.6 3(SCB1_RTS) 3(TCPWM3) 33329 XRES External Reset Hardware Connection Input30 P2.4 33331 P2.5 33332 GND Ground ConnectionNotes2. TCPWM stands for timer, counter, and PWM. If supported, the pad can be configured to any of these peripheral functions.3. The main board needs to connect both GND connections (Pad 1 and Pad 32) on the module to the common ground of the system.
PRELIMINARY CYBLE-214009-00Document Number: 002-09714 Rev. ** Page 9 of 40.Table 5. Analog Peripheral CapabilitiesPad Number Device Port Pin SARMUX OPAMP LPCOMP1GND[3] Ground Connection2P1.1 3(CTBm1_OA0_INN)3P1.0 3(CTBm1_OA0_INP)4P1.5 3(CTBm1_OA1_INP)5P0.1 3(COMP0_INN)6P0.77 VDD Digital Power Supply Input (1.71 to 5.5V)8P1.4 3(CTBm1_OA1_INN)9P0.4 3(COMP1_INP)10 P0.5 3(COMP1_INN)11 P0.612 P1.2 3(CTBm1_OA0_OUT)13 VDDR Radio Power Supply (1.9V to 5.5V)14 P2.6 3(CTBm1_OA0_INP)15 P1.3 3(CTBm1_OA1_OUT)16 P3.0 317 P2.1 3(CTBm1_OA0_INN)18 P2.2 3(CTBm1_OA0_OUT)19 P2.3 3(CTBm1_OA1_OUT)20 VDDA Analog Power Supply Input (1.71 to 5.5V)21 P3.4 322 P3.1 323 P3.7 324 P3.5 325 P3.3 326 VREF Reference Voltage Input (Optional)27 P3.2 328 P3.6 329 XRES External Reset Hardware Connection Input30 P2.4 3(CTBm1_OA1_INN)31 P2.5 3(CTBm1_OA1_INP)32 GND Ground Connection
PRELIMINARY CYBLE-214009-00Document Number: 002-09714 Rev. ** Page 10 of 40Power Supply Connections and Recommended External ComponentsPower ConnectionsThe CYBLE-214009-00 contains three power supply connec-tions, VDD, VDDA, and VDDR. The VDD and VDDA connections supply power for the digital and analog device operation respec-tively. VDDR supplies power for the device radio. VDD and VDDA accept a supply range of 1.71 V to 5.5 V. VDDR accepts a supply range of 1.9 V to 5.5 V. These specifications can be found in Ta ble 10. The maximum power supply ripple for both power connections on the module is 100 mV, as shown in Table 8. The power supply ramp rate of VDD and VDDA must be equal to or greater than that of VDDR when the radio is used. Connection OptionsTwo connection options are available for any application: 1. Single supply: Connect VDD, VDDA, and VDDR to the same supply. 2. Independent supply: Power VDD, VDDA, and VDDR separately. External Component RecommendationIn either connection scenario, it is recommended to place an external ferrite bead between the supply and the module connection. The ferrite bead should be positioned as close as possible to the module pin connection. Figure 5 details the recommended host schematic options for a single supply scenario. The use of one or two ferrite beads will depend on the specific application and configuration of the CYBLE-214009-00.Figure 6 details the recommended host schematic for an independent supply scenario. The recommended ferrite bead value is 330 Ω, 100 MHz. (Murata BLM21PG331SN1D).Figure 5. Recommended Host Schematic Options for a Single Supply OptionThree Ferrite Bead Option Single Ferrite Bead Option
PRELIMINARY CYBLE-214009-00Document Number: 002-09714 Rev. ** Page 11 of 40Figure 6. Recommended Host Schematic for an Independent Supply Option
PRELIMINARY CYBLE-214009-00Document Number: 002-09714 Rev. ** Page 12 of 40The CYBLE-214009-00 schematic is shown in Figure 7. Figure 7. CYBLE-214009-00 Schematic Diagram
PRELIMINARY CYBLE-214009-00Document Number: 002-09714 Rev. ** Page 13 of 40Critical Components ListTable 6 details the critical components used in the CYBLE-214009-00 module.Table 6. Critical Component ListAntenna DesignTable 7 details antenna used on the CYBLE-214009-00 module. The Cypress module performance improves many of these charac-teristics. For more information, see Table 9.Table 7. Trace Antenna SpecificationsComponent Reference Designator DescriptionSilicon U1 76-pin WLCSP Programmable System-on-Chip (PSoC) with BLECrystal Y1 24.000 MHz, 10PFCrystal Y2 32.768 kHz, 12.5PFItem DescriptionFrequency Range 2400 – 2500 MHzPeak Gain 0.5 dBi typicalAverage Gain -0.5 dBi typicalReturn Loss 10 dB minimum
PRELIMINARY CYBLE-214009-00Document Number: 002-09714 Rev. ** Page 14 of 40Electrical SpecificationTable 8 details the absolute maximum electrical characteristics for the Cypress BLE module.Table 8. CYBLE-214009-00 Absolute Maximum RatingsTable 9 details the RF characteristics for the Cypress BLE module.Table 9. CYBLE-214009-00 RF Performance CharacteristicsTable 10 through Table 50 list the module level electrical characteristics for the CYBLE-214009-00. All specifications are valid for –40 °C ≤ TA ≤ 85 °C and TJ ≤ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted.Parameter Description Min Typ Max Units Details/ConditionsVDDD_ABS VDD, VDDA or VDDR supply relative to VSS (VSSD = VSSA)–0.5 – 6 V Absolute maximumVCCD_ABS Direct digital core voltage input relative to VSSD –0.5 – 1.95 V Absolute maximumVDDD_RIPPLE Maximum power supply ripple for VDD, VDDA and VDDR input voltage – – 100 mV3.0V supplyRipple frequency of 100 kHz to 750 kHzVGPIO_ABS GPIO voltage –0.5 – VDD +0.5 V Absolute maximumIGPIO_ABS Maximum current per GPIO –25 – 25 mA Absolute maximumIGPIO_injection GPIO injection current: Maximum for VIH > VDD and minimum for VIL < VSS –0.5 – 0.5 mA Absolute maximum current injected per pinLU Pin current for latch up –200 200 mA –Parameter Description Min Typ Max Units Details/ConditionsRFO RF output power on ANT –18 0 3 dBm Configurable via register settingsRXSRF receive sensitivity on ANT – –91 – dBm Guaranteed by design simulation; High Gain ModeFRModule frequency range 2400 – 2480 MHz –GPPeak gain – 0.5 – dBi –GAvg Average gain – –0.5 – dBi –RL Return loss – –10 – dB –Table 10. CYBLE-214009-00 DC SpecificationsParameter Description Min Typ Max Units Details/ConditionsVDD1 Power supply input voltage (VDD = VDDA = VDDR) 1.71 – 5.5 V With regulator enabledVDD2 Power supply input voltage unregulated (VDD = VDDA = VDDR)1.71 1.8 1.89 V Internally unregulated supplyVDDR1 Radio supply voltage (radio on) 1.9 – 5.5 V –VDDR2 Radio supply voltage (radio off) 1.71 – 5.5 V –Active Mode, VDD = 1.71 V to 5.5 VIDD3 Execute from flash; CPU at 3 MHz – 1.7 – mA T = 25 °C, VDD = 3.3 VIDD4 Execute from flash; CPU at 3 MHz – – – mA T = –40 °C to 85 °CIDD5 Execute from flash; CPU at 6 MHz – 2.5 – mA T = 25 °C, VDD = 3.3 VIDD6 Execute from flash; CPU at 6 MHz – – – mA T = –40 °C to 85 °CIDD7 Execute from flash; CPU at 12 MHz – 4 – mA T = 25 °C, VDD = 3.3 V
PRELIMINARY CYBLE-214009-00Document Number: 002-09714 Rev. ** Page 15 of 40IDD8 Execute from flash; CPU at 12 MHz – – – mA T = –40 °C to 85 °CIDD9 Execute from flash; CPU at 24 MHz – 7.1 – mA T = 25 °C, VDD = 3.3 VIDD10 Execute from flash; CPU at 24 MHz – – – mA T = –40 °C to 85 °CIDD11 Execute from flash; CPU at 48 MHz – 13.4 – mA T = 25 °C, VDD = 3.3 VIDD12 Execute from flash; CPU at 48 MHz – – – mA T = –40 °C to 85 °CSleep Mode, VDD = 1.71 to 5.5 VIDD13 IMO on – – – mA T = 25 °C, VDD = 3.3 V, SYSCLK = 3 MHzSleep Mode, VDD and VDDR = 1.9 to 5.5 VIDD14 ECO on – – – mA T = 25 °C, VDD = 3.3 V, SYSCLK = 3 MHzDeep-Sleep Mode, VDD = 1.71 to 3.6 VIDD15 WDT with WCO on – 1.3 – µA T = 25 °C,VDD = 3.3 VIDD16 WDT with WCO on – – – µA T = –40 °C to 85 °CIDD17 WDT with WCO on – – – µA T = 25 °C, VDD = 5 VIDD18 WDT with WCO on – – – µA T = –40 °C to 85 °CDeep-Sleep Mode, VDD = 1.71 to 1.89 V (Regulator Bypassed)IDD19 WDT with WCO on – – – µA T = 25 °CIDD20 WDT with WCO on – – – µA T = –40 °C to 85 °CHibernate Mode, VDD = 1.71 to 3.6 VIDD27 GPIO and reset active – 150 – nA T = 25 °C, VDD = 3.3 VIDD28 GPIO and reset active – – – nA T = –40 °C to 85 °CHibernate Mode, VDD = 3.6 to 5.5 VIDD29 GPIO and reset active – – – nA T = 25 °C, VDD = 5 VIDD30 GPIO and reset active – – – nA T = –40 °C to 85 °CStop Mode, VDD = 1.71 to 3.6 VIDD33 Stop-mode current (VDD)–20–nAT = 25 °C, VDD = 3.3 VIDD34 Stop-mode current (VDDR)–40–- nAT = 25 °C, VDDR = 3.3 VIDD35 Stop-mode current (VDD) – – – nA T = –40 °C to 85 °CIDD36 Stop-mode current (VDDR)–––nAT = –40 °C to 85 °C, VDDR = 1.9 V to 3.6 VStop Mode, VDD = 3.6 to 5.5 VIDD37 Stop-mode current (VDD)–––nAT = 25 °C, VDD = 5 VIDD38 Stop-mode current (VDDR)–––nAT = 25 °C, VDDR = 5 VIDD39 Stop-mode current (VDD) – – – nA T = –40 °C to 85 °CIDD40 Stop-mode current (VDDR) – – – nA T = –40 °C to 85 °CTable 10. CYBLE-214009-00 DC Specifications (continued)Parameter Description Min Typ Max Units Details/Conditions
PRELIMINARY CYBLE-214009-00Document Number: 002-09714 Rev. ** Page 16 of 40Table 11. AC SpecificationsGPIOParameter Description Min Typ Max Units Details/ConditionsFCPU CPU frequency DC – 48 MHz 1.71 V ≤ VDD ≤ 5.5 VTSLEEP Wakeup from Sleep mode – 0 – µs Guaranteed by characterizationTDEEPSLEEP Wakeup from Deep-Sleep mode – – 25 µs 24-MHz IMO. Guaranteed by characterizationTHIBERNATE Wakeup from Hibernate mode – – 800 µs Guaranteed by characterizationTSTOP Wakeup from Stop mode – – 2 ms XRES wakeupTable 12. GPIO DC SpecificationsParameter Description Min Typ Max Units Details/ConditionsVIH[4]Input voltage HIGH threshold 0.7 × VDD – – V CMOS inputLVTTL input, VDD < 2.7 V 0.7 × VDD – – V –LVTTL input, VDD ≥ 2.7 V 2.0 – – V –VILInput voltage LOW threshold – – 0.3 × VDD VCMOS inputLVTTL input, VDD < 2.7 V – – 0.3× VDD V–LVTTL input, VDD ≥ 2.7 V – – 0.8 V –VOHOutput voltage HIGH level VDD –0.6 – – V IOH = 4 mA at 3.3-V VDD Output voltage HIGH level VDD –0.5 – – V IOH = 1 mA at 1.8-V VDDVOLOutput voltage LOW level – – 0.6 V IOL = 8 mA at 3.3-V VDDOutput voltage LOW level – – 0.6 V IOL = 4 mA at 1.8-V VDDOutput voltage LOW level – – 0.4 V IOL = 3 mA at 3.3-V VDDRPULLUP Pull-up resistor 3.5 5.6 8.5 kΩ–RPULLDOWN Pull-down resistor 3.5 5.6 8.5 kΩ–IIL Input leakage current (absolute value) – – 2 nA 25 °C, VDD = 3.3 VIIL_CTBM Input leakage on CTBm input pins – – 4 nA –CIN Input capacitance – – 7 pF –VHYSTTL Input hysteresis LVTTL 25 40 – mV VDD > 2.7 VVHYSCMOS Input hysteresis CMOS 0.05 × VDD – – 1 –IDIODE Current through protection diode to VDD/VSS – – 100 µA –ITOT_GPIO Maximum total source or sink chip current – – 200 mA –Note4. VIH must not exceed VDD + 0.2 V.
PRELIMINARY CYBLE-214009-00Document Number: 002-09714 Rev. ** Page 17 of 40Table 13. GPIO AC SpecificationsXRESAnalog PeripheralsOpampParameter Description Min Typ Max Units Details/ConditionsTRISEF Rise time in Fast-Strong mode 2 – 12 ns 3.3-V VDDD, CLOAD = 25 pFTFALLF Fall time in Fast-Strong mode 2 – 12 ns 3.3-V VDDD, CLOAD = 25 pFTRISES Rise time in Slow-Strong mode 10 – 60 ns 3.3-V VDDD, CLOAD = 25 pFTFALLS Fall time in Slow-Strong mode 10 – 60 ns 3.3-V VDDD, CLOAD = 25 pFFGPIOUT1 GPIO Fout; 3.3 V ≤ VDD ≤ 5.5 V Fast-Strong mode ––33MHz90/10%, 25 pF load, 60/40 duty cycleFGPIOUT2 GPIO Fout; 1.7 V≤ VDD ≤ 3.3 V Fast-Strong mode – – 16.7 MHz 90/10%, 25 pF load, 60/40 duty cycleFGPIOUT3 GPIO Fout; 3.3 V ≤ VDD ≤ 5.5 V Slow-Strong mode –– 7 MHz90/10%, 25 pF load, 60/40 duty cycleFGPIOUT4 GPIO Fout; 1.7 V ≤ VDD ≤ 3.3 V Slow-Strong mode ––3.5MHz90/10%, 25 pF load, 60/40 duty cycleFGPIOIN GPIO input operating frequency1.71 V ≤ VDD ≤ 5.5 V – – 48 MHz 90/10% VIOTable 14. XRES DC SpecificationsParameter Description Min Typ Max Units Details/ConditionsVIH Input voltage HIGH threshold 0.7 × VDDD – – V CMOS inputVIL Input voltage LOW threshold – – 0.3 × VDDD V CMOS inputRPULLUP Pull-up resistor 3.5 5.6 8.5 kΩ–CIN Input capacitance – 3 – pF –VHYSXRES Input voltage hysteresis – 100 – mV –IDIODE Current through protection diode to VDD/VSS – – 100 µA –Table 15. XRES AC SpecificationsParameter Description Min Typ Max Units Details/ConditionsTRESETWIDTH Reset pulse width 1 – – µs –Table 16. Opamp SpecificationsParameter Description Min Typ Max Units Details/ConditionsIDD (Opamp Block Current. VDD = 1.8 V. No Load)IDD_HI Power = high – 1000 1300 µAIDD_MED Power = medium – 500 – µAIDD_LOW Power = low – 250 350 µAGBW (Load = 20 pF, 0.1 mA. VDDA = 2.7 V)GBW_HI Power = high 6 – – MHzGBW_MED Power = medium 4 – – MHzGBW_LO Power = low – 1 – MHzIOUT_MAX (VDDA ≥ 2.7 V, 500 mV from Rail)
PRELIMINARY CYBLE-214009-00Document Number: 002-09714 Rev. ** Page 18 of 40IOUT_MAX_HI Power = high 10 – – mAIOUT_MAX_MID Power = medium 10 – – mAIOUT_MAX_LO Power = low – 5 – mAIOUT (VDDA = 1.71 V, 500 mV from Rail)IOUT_MAX_HI Power = high 4 – – mAIOUT_MAX_MID Power = medium 4 – – mAIOUT_MAX_LO Power = low – 2 – mAVIN Charge pump on, VDDA ≥ 2.7 V –0.05 – VDDA – 0.2 VVCM Charge pump on, VDDA ≥ 2.7 V –0.05 – VDDA – 0.2 VVOUT (VDDA ≥ 2.7 V)VOUT_1 Power = high, ILOAD=10 mA 0.5 – VDDA – 0.5 VVOUT_2 Power = high, ILOAD=1 mA 0.2 – VDDA – 0.2 VVOUT_3 Power = medium, ILOAD=1 mA 0.2 – VDDA – 0.2 VVOUT_4 Power = low, ILOAD=0.1 mA 0.2 – VDDA – 0.2 VVOS_TR Offset voltage, trimmed 1 ±0.5 1 mV High modeVOS_TR Offset voltage, trimmed – ±1 – mV Medium modeVOS_TR Offset voltage, trimmed – ±2 – mV Low modeVOS_DR_TR Offset voltage drift, trimmed –10 ±3 10 µV/C High modeVOS_DR_TR Offset voltage drift, trimmed – ±10 – µV/C Medium modeVOS_DR_TR Offset voltage drift, trimmed – ±10 – µV/C Low modeCMRR DC 65 70 – dB VDDD = 3.6 V, High-power modePSRR At 1 kHz, 100-mV ripple 70 85 – dB VDDD = 3.6 VNoiseVN1 Input referred, 1 Hz–1 GHz, power = high – 94 – µVrmsVN2 Input referred, 1 kHz, power = high – 72 – nV/rtHzVN3 Input referred, 10 kHz, power = high – 28 – nV/rtHzVN4 Input referred, 100 kHz, power = high – 15 – nV/rtHzCLOAD Stable up to maximum load. Performance specs at 50 pF––125 pFSlew_rate Cload = 50 pF, Power = High, VDDA ≥ 2.7 V6 – – V/µsecT_op_wake From disable to enable, no external RC dominating– 300 – µsecComp_mode (Comparator Mode; 50-mV Drive, TRISE = TFALL (Approx.)TPD1 Response time; power = high – 150 – nsecTPD2 Response time; power = medium – 400 – nsecTPD3 Response time; power = low – 2000 – nsecVhyst_op Hysteresis – 10 – mVDeep-Sleep Mode (Deep-Sleep mode operation is only guaranteed for VDDA > 2.5 V)GBW_DS Gain bandwidth product – 50 – kHzIDD_DS Current – 15 – µAVos_DS Offset voltage – 5 – mVTable 16. Opamp Specifications (continued)Parameter Description Min Typ Max Units Details/Conditions
PRELIMINARY CYBLE-214009-00Document Number: 002-09714 Rev. ** Page 19 of 40Temperature SensorSAR ADCVos_dr_DS Offset voltage drift – 20 – µV/°CVout_DS Output voltage 0.2 – VDD–0.2 VVcm_DS Common mode voltage 0.2 – VDD–1.8 VTable 16. Opamp Specifications (continued)Parameter Description Min Typ Max Units Details/ConditionsTable 17. Comparator DC Specifications Parameter Description Min Typ Max Units Details/ConditionsVOFFSET1 Input offset voltage, Factory trim – – ±10 mVVOFFSET2 Input offset voltage, Custom trim – – ±6 mVVOFFSET3 Input offset voltage, ultra-low-power mode – ±12 – mVVHYST Hysteresis when enabled – 10 35 mVVICM1 Input common mode voltage in normal mode 0 – VDDD –0.1 V Modes 1 and 2VICM2 Input common mode voltage in low-power mode0– VDDD VVICM3 Input common mode voltage in ultra low-power mode0–VDDD –1.15VCMRR Common mode rejection ratio 50 – – dB VDDD ≥ 2.7 VCMRR Common mode rejection ratio 42 – – dB VDDD ≤ 2.7 VICMP1 Block current, normal mode – – 400 µAICMP2 Block current, low-power mode – – 100 µAICMP3 Block current in ultra-low-power mode – 6 – µAZCMP DC input impedance of comparator 35 – – MΩTable 18. Comparator AC Specifications Parameter Description Min Typ Max Units Details/ConditionsTRESP1 Response time, normal mode, 50-mV overdrive–38– ns50-mV overdriveTRESP2 Response time, low-power mode, 50-mV overdrive–70– ns50-mV overdriveTRESP3 Response time, ultra-low-power mode, 50-mV overdrive– 2.3 – µs 200-mV overdriveTable 19. Temperature Sensor Specifications Parameter Description Min Typ Max Units Details/ConditionsTSENSACC Temperature-sensor accuracy –5 ±1 5 °C –40 to +85 °CTable 20. SAR ADC DC SpecificationsParameter Description Min Typ Max Units Details/ConditionsA_RES Resolution – – 12 bits
PRELIMINARY CYBLE-214009-00Document Number: 002-09714 Rev. ** Page 20 of 40CSDA_CHNIS_S Number of channels - single-ended – – 8 8 full-speedA-CHNKS_D Number of channels - differential – – 4 Diff inputs use neighboring I/OA-MONO Monotonicity – – – YesA_GAINERR Gain error – – ±0.1 % With external reference A_OFFSET Input offset voltage – – 2 mV Measured with 1-V VREFA_ISAR Current consumption – – 1 mAA_VINS Input voltage range - single-ended VSS –VDDA VA_VIND Input voltage range - differential VSS – VDDA VA_INRES Input resistance – – 2.2 kΩA_INCAP Input capacitance – – 10 pFVREFSAR Trimmed internal reference to SAR –1 – 1 % Percentage of Vbg (1.024 V)Table 20. SAR ADC DC SpecificationsTable 21. SAR ADC AC SpecificationsParameter Description Min Typ Max Units Details/ConditionsA_PSRR Power-supply rejection ratio 70 – – dB Measured at 1-V referenceA_CMRR Common-mode rejection ratio 66 – – dBA_SAMP Sample rate – – 1 Msps 806 Ksps for More Part Numbers devicesFsarintref SAR operating speed without external ref. bypass– – 100 Ksps 12-bit resolutionA_SNR Signal-to-noise ratio (SNR) 65 – – dB FIN = 10 kHzA_BW Input bandwidth without aliasing – – A_SAMP/2 kHzA_INL Integral nonlinearity. VDD = 1.71 V to 5.5 V, 1 Msps–1.7 – 2 LSB VREF = 1 V to VDDA_INL Integral nonlinearity. VDDD = 1.71 V to 3.6 V, 1 Msps–1.5 – 1.7 LSB VREF = 1.71 V to VDDA_INL Integral nonlinearity. VDD = 1.71 V to 5.5 V, 500 Ksps–1.5 – 1.7 LSB VREF = 1 V to VDDA_dnl Differential nonlinearity. VDD = 1.71 V to 5.5 V, 1 Msps–1 – 2.2 LSB VREF = 1 V to VDDA_DNL Differential nonlinearity. VDD = 1.71 V to 3.6 V, 1 Msps–1 – 2 LSB VREF = 1.71 V to VDDA_DNL Differential nonlinearity. VDD = 1.71 V to 5.5 V, 500 Ksps–1 – 2.2 LSB VREF = 1 V to VDDA_THD Total harmonic distortion – – –65 dB FIN = 10 kHzCSD Block SpecificationsParameter Description Min Typ Max Units Details/ConditionsVCSD Voltage range of operation 1.71 – 5.5 V
PRELIMINARY CYBLE-214009-00Document Number: 002-09714 Rev. ** Page 21 of 40Digital PeripheralsTimer Counter IDAC1 DNL for 8-bit resolution –1 – 1 LSBIDAC1 INL for 8-bit resolution –3 – 3 LSBIDAC2 DNL for 7-bit resolution –1 – 1 LSBIDAC2 INL for 7-bit resolution –3 – 3 LSBSNR Ratio of counts of finger to noise 5 – – Ratio Capacitance range of 9 pF to 35 pF, 0.1-pF sensitivity. Radio is not operating during the scanIDAC1_CRT1 Output current of IDAC1 (8 bits) in High range–612 – µAIDAC1_CRT2 Output current of IDAC1 (8 bits) in Low range–306 – µAIDAC2_CRT1 Output current of IDAC2 (7 bits) in High range–305 – µAIDAC2_CRT2 Output current of IDAC2 (7 bits) in Low range–153 – µACSD Block Specifications (continued)Parameter Description Min Typ Max Units Details/ConditionsTable 22. Timer DC SpecificationsParameter Description Min Typ Max Units Details/ConditionsITIM1 Block current consumption at 3 MHz – – 42 µA 16-bit timerITIM2 Block current consumption at 12 MHz – – 130 µA 16-bit timerITIM3 Block current consumption at 48 MHz – – 535 µA 16-bit timerTable 23. Timer AC SpecificationsParameter Description Min Typ Max Units Details/ConditionsTTIMFREQ Operating frequency FCLK –48MHzTCAPWINT Capture pulse width (internal) 2 × TCLK ––nsTCAPWEXT Capture pulse width (external) 2 × TCLK ––nsTTIMRES Timer resolution TCLK ––nsTTENWIDINT Enable pulse width (internal) 2 × TCLK ––nsTTENWIDEXT Enable pulse width (external) 2 × TCLK ––nsTTIMRESWINT Reset pulse width (internal) 2 × TCLK ––nsTTIMRESEXT Reset pulse width (external) 2 × TCLK ––nsTable 24. Counter DC SpecificationsParameter Description Min Typ Max Units Details/ConditionsICTR1 Block current consumption at 3 MHz – – 42 µA 16-bit counterICTR2 Block current consumption at 12 MHz – – 130 µA 16-bit counterICTR3 Block current consumption at 48 MHz – – 535 µA 16-bit counter
PRELIMINARY CYBLE-214009-00Document Number: 002-09714 Rev. ** Page 22 of 40Pulse Width Modulation (PWM) LCD Direct Drive Table 25. Counter AC SpecificationsParameter Description Min Typ Max Units Details/ConditionsTCTRFREQ Operating frequency FCLK –48MHzTCTRPWINT Capture pulse width (internal) 2 × TCLK ––nsTCTRPWEXT Capture pulse width (external) 2 × TCLK ––nsTCTRES Counter Resolution TCLK ––nsTCENWIDINT Enable pulse width (internal) 2 × TCLK ––nsTCENWIDEXT Enable pulse width (external) 2 × TCLK ––nsTCTRRESWINT Reset pulse width (internal) 2 × TCLK ––nsTCTRRESWEXT Reset pulse width (external) 2 × TCLK –– nsTable 26. PWM DC SpecificationsParameter Description Min Typ Max Units Details/ConditionsIPWM1 Block current consumption at 3 MHz – – 42 µA 16-bit PWMIPWM2 Block current consumption at 12 MHz – – 130 µA 16-bit PWMIPWM3 Block current consumption at 48 MHz – – 535 µA 16-bit PWMTable 27. PWM AC SpecificationsParameter Description Min Typ Max Units Details/ConditionsTPWMFREQ Operating frequency FCLK –48MHzTPWMPWINT Pulse width (internal) 2 × TCLK ––nsTPWMEXT Pulse width (external) 2 × TCLK ––nsTPWMKILLINT Kill pulse width (internal) 2 × TCLK ––nsTPWMKILLEXT Kill pulse width (external) 2 × TCLK ––nsTPWMEINT Enable pulse width (internal) 2 × TCLK ––nsTPWMENEXT Enable pulse width (external) 2 × TCLK ––nsTPWMRESWINT Reset pulse width (internal) 2 × TCLK ––nsTPWMRESWEXT Reset pulse width (external) 2 × TCLK ––nsTable 28. LCD Direct Drive DC SpecificationsSpec ID Parameter Description Min Typ Max Units Details/ConditionsSID228 ILCDLOW Operating current in low-power mode – 17.5 – µA 16 × 4 small segment display at 50 HzSID229 CLCDCAP LCD capacitance per segment/common driver– 500 5000 pFSID230 LCDOFFSET Long-term segment offset – 20 – mVSID231 ILCDOP1 LCD system operating currentVBIAS = 5 V – 2 – mA 32 × 4 segments. 50 Hz at 25 °CSID232 ILCDOP2 LCD system operating currentVBIAS = 3.3 V– 2 – mA 32 × 4 segments50 Hz at 25 °CTable 29. LCD Direct Drive AC SpecificationsSpec ID Parameter Description Min Typ Max Units Details/ConditionsSID233 FLCD LCD frame rate 10 50 150 Hz
PRELIMINARY CYBLE-214009-00Document Number: 002-09714 Rev. ** Page 23 of 40Serial CommunicationTable 30. Fixed I2C DC SpecificationsTable 32. Fixed UART DC SpecificationsTable 33. Fixed UART AC SpecificationsParameter Description Min Typ Max Units Details/ConditionsII2C1 Block current consumption at 100 kHz – – 50 µA –II2C2 Block current consumption at 400 kHz – – 155 µA –II2C3 Block current consumption at 1 Mbps – – 390 µA –II2C4 I2C enabled in Deep-Sleep mode – – 1.4 µA –Table 31. Fixed I2C AC SpecificationsParameter Description Min Typ Max Units Details/ConditionsFI2C1 Bit rate – – 400 kHzParameter Description Min Typ Max Units Details/ConditionsIUART1 Block current consumption at 100 kbps – – 55 µA –IUART2 Block current consumption at 1000 kbps – – 312 µA –Parameter Description Min Typ Max Units Details/ConditionsFUART Bit rate – – 1 Mbps –Table 34. Fixed SPI DC SpecificationsParameter Description Min Typ Max Units Details/ConditionsISPI1 Block current consumption at 1 Mbps – – 360 µA –ISPI2 Block current consumption at 4 Mbps – – 560 µA –ISPI3 Block current consumption at 8 Mbps – – 600 µA –Table 35. Fixed SPI AC SpecificationsParameter Description Min Typ Max Units Details/ConditionsFSPI SPI operating frequency (master; 6x over sampling) – – 8 MHz –Table 36. Fixed SPI Master Mode AC SpecificationsParameter Description Min Typ Max Units Details/ConditionsTDMO MOSI valid after SCLK driving edge – – 18 ns –TDSI MISO valid before SCLK capturing edge Full clock, late MISO sampling used 20 – – ns Full clock, late MISO samplingTHMO Previous MOSI data hold time 0 – – ns Referred to Slave capturing edgeTable 37. Fixed SPI Slave Mode AC SpecificationsParameter Description Min Typ Max UnitsTDMI MOSI valid before SCLK capturing edge 40 – – nsTDSO MISO valid after SCLK driving edge – – 42 + 3 × TCPU nsTDSO_ext MISO Valid after SCLK driving edge in external clock mode. VDD < 3.0 V – – 50 nsTHSO Previous MISO data hold time 0 – – nsTSSELSCK SSEL valid to first SCK valid edge 100 – – ns
PRELIMINARY CYBLE-214009-00Document Number: 002-09714 Rev. ** Page 24 of 40MemorySystem ResourcesPower-on-Reset (POR) Note5. It can take as much as 20 ms to write to flash. During this time, the device should not be reset, or flash operations will be interrupted and cannot be relied on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs. Make certain that these are not inadvertently activated.Table 38. Flash DC SpecificationsParameter Description Min Typ Max Units Details/ConditionsVPE Erase and program voltage 1.71 – 5.5 V –TWS48 Number of Wait states at 32–48 MHz 2 – – CPU execution from flashTWS32 Number of Wait states at 16–32 MHz 1 – – CPU execution from flashTWS16 Number of Wait states for 0–16 MHz 0 – – CPU execution from flashTable 39. Flash AC SpecificationsParameter Description Min Typ Max Units Details/ConditionsTROWWRITE[5] Row (block) write time (erase and program) – – 20 ms Row (block) = 256 bytesTROWERASE[5] Row erase time – – 13 ms –TROWPROGRAM[5] Row program time after erase – – 7 ms –TBULKERASE[5] Bulk erase time (256 KB) – – 35 ms –TDEVPROG[5] Total device program time – – 25 seconds –FEND Flash endurance 100 K – – cycles –FRET Flash retention. TA ≤ 55 °C, 100 K P/E cycles 20 – – years –FRET2 Flash retention. TA ≤ 85 °C, 10 K P/E cycles 10 – – years –Table 40. POR DC SpecificationsParameter Description Min Typ Max Units Details/ConditionsVRISEIPOR Rising trip voltage 0.80 – 1.45 V –VFALLIPOR Falling trip voltage 0.75 – 1.40 V –VIPORHYST Hysteresis 15 – 200 mV –Table 41. POR AC SpecificationsParameter Description Min Typ Max Units Details/ConditionsTPPOR_TR Precision power-on reset (PPOR) response time in Active and Sleep modes ––1µs –Table 42. Brown-Out DetectParameter Description Min Typ Max Units Details/ConditionsVFALLPPOR BOD trip voltage in Active and Sleep modes 1.64 – – V –VFALLDPSLP BOD trip voltage in Deep Sleep 1.4 – – V –Table 43. Hibernate ResetParameter Description Min Typ Max Units Details/ConditionsVHBRTRIP BOD trip voltage in Hibernate 1.1 – – V –
PRELIMINARY CYBLE-214009-00Document Number: 002-09714 Rev. ** Page 25 of 40Voltage Monitors (LVD) SWD Interface Table 44. Voltage Monitor DC SpecificationsParameter Description Min Typ Max Units Details/ConditionsVLVI1 LVI_A/D_SEL[3:0] = 0000b 1.71 1.75 1.79 V –VLVI2 LVI_A/D_SEL[3:0] = 0001b 1.76 1.80 1.85 V –VLVI3 LVI_A/D_SEL[3:0] = 0010b 1.85 1.90 1.95 V –VLVI4 LVI_A/D_SEL[3:0] = 0011b 1.95 2.00 2.05 V –VLVI5 LVI_A/D_SEL[3:0] = 0100b 2.05 2.10 2.15 V –VLVI6 LVI_A/D_SEL[3:0] = 0101b 2.15 2.20 2.26 V –VLVI7 LVI_A/D_SEL[3:0] = 0110b 2.24 2.30 2.36 V –VLVI8 LVI_A/D_SEL[3:0] = 0111b 2.34 2.40 2.46 V –VLVI9 LVI_A/D_SEL[3:0] = 1000b 2.44 2.50 2.56 V –VLVI10 LVI_A/D_SEL[3:0] = 1001b 2.54 2.60 2.67 V –VLVI11 LVI_A/D_SEL[3:0] = 1010b 2.63 2.70 2.77 V –VLVI12 LVI_A/D_SEL[3:0] = 1011b 2.73 2.80 2.87 V –VLVI13 LVI_A/D_SEL[3:0] = 1100b 2.83 2.90 2.97 V –VLVI14 LVI_A/D_SEL[3:0] = 1101b 2.93 3.00 3.08 V –VLVI15 LVI_A/D_SEL[3:0] = 1110b 3.12 3.20 3.28 V –VLVI16 LVI_A/D_SEL[3:0] = 1111b 4.39 4.50 4.61 V –LVI_IDD Block current – – 100 µA –Table 45. Voltage Monitor AC SpecificationsParameter Description Min Typ Max Units Details/ConditionsTMONTRIP Voltage monitor trip time – – 1 µs –Table 46. SWD Interface SpecificationsParameter Description Min Typ Max Units Details/ConditionsF_SWDCLK1 3.3 V ≤ VDD ≤ 5.5 V – – 14 MHz SWDCLK ≤ 1/3 CPU clock frequencyF_SWDCLK2 1.71 V ≤ VDD ≤ 3.3 V – – 7 MHz SWDCLK ≤ 1/3 CPU clock frequencyT_SWDI_SETUP T = 1/f SWDCLK 0.25 × T – – ns –T_SWDI_HOLD T = 1/f SWDCLK 0.25 × T – – ns –T_SWDO_VALID T = 1/f SWDCLK – – 0.5 × T ns –T_SWDO_HOLD T = 1/f SWDCLK 1 – – ns –
PRELIMINARY CYBLE-214009-00Document Number: 002-09714 Rev. ** Page 26 of 40Internal Main OscillatorInternal Low-Speed Oscillator Table 51. ECO Trim Value SpecificationTable 47. IMO DC SpecificationsParameter Description Min Typ Max Units Details/ConditionsIIMO1 IMO operating current at 48 MHz – – 1000 µA –IIMO2 IMO operating current at 24 MHz – – 325 µA –IIMO3 IMO operating current at 12 MHz – – 225 µA –IIMO4 IMO operating current at 6 MHz – – 180 µA –IIMO5 IMO operating current at 3 MHz – – 150 µA –Table 48. IMO AC SpecificationsParameter Description Min Typ Max Units Details/ConditionsFIMOTOL3 Frequency variation from 3 to 48 MHz – – ±2 % With API-called calibrationFIMOTOL3 IMO startup time – 12 – µs –Table 49. ILO DC SpecificationsParameter Description Min Typ Max Units Details/ConditionsIILO2 ILO operating current at 32 kHz – 0.3 1.05 µA –Table 50. ILO AC SpecificationsParameter Description Min Typ Max Units Details/ConditionsTSTARTILO1 ILO startup time – – 2 ms –FILOTRIM1 32-kHz trimmed frequency 15 32 50 kHz –Parameter Description Value Details/ConditionsECOTRIM 24-MHz trim value (firmware configuration) 0x00003FFA Optimum trim value that needs to be loaded to register CY_SYS_XTAL_BLERD_BB_XO_CAPTRIM_REG Table 52. UDB AC SpecificationsParameter Description Min Typ Max Units Details/ConditionsData Path performanceFMAX-TIMER Max frequency of 16-bit timer in a UDB pair––48MHzFMAX-ADDER Max frequency of 16-bit adder in a UDB pair––48MHzFMAX_CRC Max frequency of 16-bit CRC/PRS in a UDB pair––48MHzPLD Performance in UDBFMAX_PLD Max frequency of 2-pass PLD function in a UDB pair––48MHzClock to Output PerformanceTCLK_OUT_UDB1 Prop. delay for clock in to data out at 25 °C, Typical–15 – nsTCLK_OUT_UDB2 Prop. delay for clock in to data out, Worst case–25 – ns
PRELIMINARY CYBLE-214009-00Document Number: 002-09714 Rev. ** Page 27 of 40Table 53. BLE SubsystemParameter Description Min Typ Max Units Details/ConditionsRF Receiver SpecificationRXS, IDLE RX sensitivity with idle transmitter – –89 – dBmRX sensitivity with idle transmitter excluding Balun loss– –91 – dBm Guaranteed by design simulationRXS, DIRTY RX sensitivity with dirty transmitter – –87 –70 dBm RF-PHY Specification (RCV-LE/CA/01/C)RXS, HIGHGAIN RX sensitivity in high-gain mode with idle transmitter– –91 – dBmPRXMAX Maximum input power –10 –1 – dBm RF-PHY Specification (RCV-LE/CA/06/C)CI1 Cochannel interference, Wanted signal at –67 dBm and Interferer at FRX– 9 21 dB RF-PHY Specification (RCV-LE/CA/03/C)CI2 Adjacent channel interferenceWanted signal at –67 dBm and Interferer at FRX ±1 MHz – 3 15 dB RF-PHY Specification (RCV-LE/CA/03/C)CI3 Adjacent channel interferenceWanted signal at –67 dBm and Interferer at FRX ±2 MHz – –29 – dB RF-PHY Specification (RCV-LE/CA/03/C)CI4 Adjacent channel interferenceWanted signal at –67 dBm and Interferer at ≥FRX ±3 MHz – –39 – dB RF-PHY Specification (RCV-LE/CA/03/C)CI5 Adjacent channel interferenceWanted Signal at –67 dBm and Interferer at Image frequency (FIMAGE)– –20 – dB RF-PHY Specification (RCV-LE/CA/03/C)CI3 Adjacent channel interferenceWanted signal at –67 dBm and Interferer at Image frequency (FIMAGE ± 1 MHz) – –30 – dB RF-PHY Specification (RCV-LE/CA/03/C)OBB1 Out-of-band blocking,Wanted signal at –67 dBm and Interferer at F = 30–2000 MHz–30 –27 – dBm RF-PHY Specification (RCV-LE/CA/04/C)OBB2 Out-of-band blocking,Wanted signal at –67 dBm and Interferer at F = 2003–2399 MHz–35 –27 – dBm RF-PHY Specification (RCV-LE/CA/04/C)OBB3 Out-of-band blocking,Wanted signal at –67 dBm and Interferer at F = 2484–2997 MHz–35 –27 – dBm RF-PHY Specification (RCV-LE/CA/04/C)OBB4 Out-of-band blocking,Wanted signal a –67 dBm and Interferer at F = 3000–12750 MHz–30 –27 – dBm RF-PHY Specification (RCV-LE/CA/04/C)IMD Intermodulation performanceWanted signal at –64 dBm and 1-Mbps BLE, third, fourth, and fifth offset channel–50 – – dBm RF-PHY Specification (RCV-LE/CA/05/C)RXSE1 Receiver spurious emission30 MHz to 1.0 GHz– – –57 dBm 100-kHz measurement bandwidthETSI EN300 328 V1.8.1
PRELIMINARY CYBLE-214009-00Document Number: 002-09714 Rev. ** Page 28 of 40RXSE2 Receiver spurious emission1.0 GHz to 12.75 GHz– – –47 dBm 1-MHz measurement bandwidthETSI EN300 328 V1.8.1RF Transmitter SpecificationsTXP, ACC RF power accuracy – ±1 – dBTXP, RANGE RF power control range – 20 – dBTXP, 0dBm Output power, 0-dB Gain setting (PA7) – 0 – dBmTXP, MAX Output power, maximum power setting (PA10)–3 – dBmTXP, MIN Output power, minimum power setting (PA1)– –18 – dBmF2AVG Average frequency deviation for 10101010 pattern185 – – kHz RF-PHY Specification (TRM-LE/CA/05/C)F1AVG Average frequency deviation for 11110000 pattern225 250 275 kHz RF-PHY Specification (TRM-LE/CA/05/C)EO Eye opening = ΔF2AVG/ΔF1AVG 0.8 – – RF-PHY Specification (TRM-LE/CA/05/C)FTX, ACC Frequency accuracy –150 – 150 kHz RF-PHY Specification (TRM-LE/CA/06/C)FTX, MAXDR Maximum frequency drift –50 – 50 kHz RF-PHY Specification (TRM-LE/CA/06/C)FTX, INITDR Initial frequency drift –20 – 20 kHz RF-PHY Specification (TRM-LE/CA/06/C)FTX, DR Maximum drift rate –20 – 20 kHz/50 µsRF-PHY Specification (TRM-LE/CA/06/C)IBSE1 In-band spurious emission at 2-MHz offset– – –20 dBm RF-PHY Specification (TRM-LE/CA/03/C)IBSE2 In-band spurious emission at ≥3-MHz offset– – -30 dBm RF-PHY Specification (TRM-LE/CA/03/C)TXSE1 Transmitter spurious emissions (average), <1.0 GHz– – -55.5 dBm FCC-15.247TXSE2 Transmitter spurious emissions (average), >1.0 GHz– – -41.5 dBm FCC-15.247RF Current SpecificationsIRX Receive current in normal mode – 18.7 – mAIRX_RF Radio receive current in normal mode – 16.4 – mA Measured at VDDRIRX, HIGHGAIN Receive current in high-gain mode – 21.5 – mAITX, 3dBm TX current at 3-dBm setting (PA10) – 20 – mAITX, 0dBm TX current at 0-dBm setting (PA7) – 16.5 – mAITX_RF, 0dBm Radio TX current at 0 dBm setting (PA7) – 15.6 – mA Measured at VDDRITX_RF, 0dBm Radio TX current at 0 dBm excluding Balun loss– 14.2 – mA Guaranteed by design simulationITX,-3dBm TX current at –3-dBm setting (PA4) – 15.5 – mAITX,-6dBm TX current at –6-dBm setting (PA3) – 14.5 – mATable 53. BLE Subsystem (continued)Parameter Description Min Typ Max Units Details/Conditions
PRELIMINARY CYBLE-214009-00Document Number: 002-09714 Rev. ** Page 29 of 40ITX,-12dBm TX current at –12-dBm setting (PA2) – 13.2 – mAITX,-18dBm TX current at –18-dBm setting (PA1) – 12.5 – mAIavg_1sec, 0dBm Average current at 1-second BLE connection interval– 17.1 – µA TXP: 0 dBm; ±20-ppm master and slave clock accuracy.For empty PDU exchangeIavg_4sec, 0dBm Average current at 4-second BLE connection interval – 6.1 – µA TXP: 0 dBm; ±20-ppm master and slave clock accuracy.For empty PDU exchangeGeneral RF SpecificationsFREQ RF operating frequency 2400 – 2482 MHzCHBW Channel spacing – 2 – MHzDR On-air data rate – 1000 – kbpsIDLE2TX BLE.IDLE to BLE. TX transition time – 120 140 µsIDLE2RX BLE.IDLE to BLE. RX transition time – 75 120 µsRSSI SpecificationsRSSI, ACC RSSI accuracy – ±5 – dBRSSI, RES RSSI resolution – 1 – dBRSSI, PER RSSI sample period – 6 – µsTable 53. BLE Subsystem (continued)Parameter Description Min Typ Max Units Details/Conditions
PRELIMINARY CYBLE-214009-00Document Number: 002-09714 Rev. ** Page 30 of 40Environmental SpecificationsEnvironmental ComplianceThis Cypress BLE module is built in compliance with the Restriction of Hazardous Substances (RoHS) and Halogen Free (HF) directives. The Cypress module and components used to produce this module are RoHS and HF compliant.RF CertificationThe CYBLE-214009-00 module is certified under the following RF certification standards:nFCC ID: WAP4008nCE nIC: 7922A-4008nMIC (Japan)nKC: MSIP-CRM-Cyp-4008Environmental ConditionsTable 54 describes the operating and storage conditions for the Cypress BLE module.Table 54. Environmental Conditions for CYBLE-214009-00 ESD and EMI ProtectionExposed components require special attention to ESD and electromagnetic interference (EMI).A grounded conductive layer inside the device enclosure is suggested for EMI and ESD performance. Any openings in the enclosure near the module should be surrounded by a grounded conductive layer to provide ESD protection and a low-impedance path to ground. Device Handling: Proper ESD protocol must be followed in manufacturing to ensure component reliability.Description Minimum Specification Maximum SpecificationOperating temperature -40 °C 85 °COperating humidity (relative, non-condensation) 5% 85%Thermal ramp rate – 3 °C/minuteStorage temperature –40 °C 85 °CStorage temperature and humidity – 85 ° C at 85%ESD: Module integrated into system Components[6] –15 kV Air2.2 kV ContactNote6. This does not apply to the RF pins (ANT, XTALI, and XTALO). RF pins (ANT, XTALI, and XTALO) are tested for 500-V HBM.
PRELIMINARY CYBLE-214009-00Document Number: 002-09714 Rev. ** Page 31 of 40Regulatory InformationFCCFCC NOTICE:The device CYBLE-214009-00 complies with Part 15 of the FCC Rules. The device meets the requirements for modular transmitter approval as detailed in FCC public Notice DA00-1407. Transmitter Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause undesired operation.CAUTION:The FCC requires the user to be notified that any changes or modifications made to this device that are not expressly approved by Cypress Semiconductor may void the user's authority to operate the equipment.This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates and can radiate radio frequency energy and, if not installed and used in accordance with the instructions,ê may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures:nReorient or relocate the receiving antenna. nIncrease the separation between the equipment and receiver. nConnect the equipment into an outlet on a circuit different from that to which the receiver is connected. nConsult the dealer or an experienced radio/TV technician for help LABELING REQUIREMENTS:The Original Equipment Manufacturer (OEM) must ensure that FCC labelling requirements are met. This includes a clearly visible label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor FCC identifier for this product as well as the FCC Notice above. The FCC identifier is FCC ID: WAP4008.In any case the end product must be labeled exterior with "Contains FCC ID: WAP4008"ANTENNA WARNING: This device is tested with a standard SMA connector and with the antennas listed in Table 7 on page 13. When integrated in the OEMs product, these fixed antennas require installation preventing end-users from replacing them with non-approved antennas. Any antenna not in the following table must be tested to comply with FCC Section 15.203 for unique antenna connectors and Section 15.247 for emissions.RF EXPOSURE: To comply with FCC RF Exposure requirements, the Original Equipment Manufacturer (OEM) must ensure to install the approved antenna in the previous.The preceding statement must be included as a CAUTION statement in manuals, for products operating with the approved antennas in Table 7 on page 13, to alert users on FCC RF Exposure compliance. Any notification to the end user of installation or removal instructions about the integrated radio module is not allowed.The radiated output power of CYBLE-214009-00 is far below the FCC radio frequency exposure limits. Nevertheless, use CYBLE-214009-00 in such a manner that minimizes the potential for human contact during normal operation. End users may not be provided with the module installation instructions. OEM integrators and end users must be provided with transmitter operating conditions for satisfying RF exposure compliance.
PRELIMINARY CYBLE-214009-00Document Number: 002-09714 Rev. ** Page 32 of 40Industry Canada (IC) CertificationCYBLE-214009-00 is licensed to meet the regulatory requirements of Industry Canada (IC), License: IC: 7922A-4008Manufacturers of mobile, fixed or portable devices incorporating this module are advised to clarify any regulatory questions and ensure compliance for SAR and/or RF exposure limits. Users can obtain Canadian information on RF exposure and compliance from www.ic.gc.ca.This device has been designed to operate with the antennas listed in Table 7 on page 13, having a maximum gain of 0.5 dBi. Antennas not included in this list or having a gain greater than 0.5 dBi are strictly prohibited for use with this device. The required antenna impedance is 50 ohms. The antenna used for this transmitter must not be co-located or operating in conjunction with any other antenna or transmitter.IC NOTICE:The device CYBLE-214009-00 complies with Canada RSS-GEN Rules. The device meets the requirements for modular transmitter approval as detailed in RSS-GEN. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause undesired operation.IC RADIATION EXPOSURE STATEMENT FOR CANADAThis device complies with Industry Canada licence-exempt RSS standard(s). Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation of the device.Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation est autorisée aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.LABELING REQUIREMENTS:The Original Equipment Manufacturer (OEM) must ensure that IC labelling requirements are met. This includes a clearly visible label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor IC identifier for this product as well as the IC Notice above. The IC identifier is 7922A-4008. In any case, the end product must be labeled in its exterior with "Contains IC: 7922A-4008".European R&TTE Declaration of ConformityHereby, Cypress Semiconductor declares that the Bluetooth module CYBLE-214009-00 complies with the essential requirements and other relevant provisions of Directive 1999/5/EC. As a result of the conformity assessment procedure described in Annex III of the Directive 1999/5/EC, the end-customer equipment should be labeled as follows: All versions of the CYBLE-214009-00 in the specified reference design can be used in the following countries: Austria, Belgium, Cyprus, Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Ireland, Italy, Latvia, Lithuania, Luxem-bourg, Malta, Poland, Portugal, Slovakia, Slovenia, Spain, Sweden, The Netherlands, the United Kingdom, Switzerland, and Norway.
PRELIMINARY CYBLE-214009-00Document Number: 002-09714 Rev. ** Page 33 of 40MIC JapanCYBLE-214009-00 is certified as a module with type certification number TBD. End products that integrate CYBLE-214009-00 do not need additional MIC Japan certification for the end product.End product can display the certification label of the embedded module.KC KoreaCYBLE-214009-00 is certified for use in Korea with certificate number MSIP-CRM-Cyp-4008
PRELIMINARY CYBLE-214009-00Document Number: 002-09714 Rev. ** Page 34 of 40Ordering InformationThe CYBLE-214009-00 part number and features are listed in the following table. Part Numbering ConventionThe part numbers are of the form CYBLE-ABCDEF-GH where the fields are defined as follows.For additional information and a complete list of Cypress Semiconductor BLE products, contact your local Cypress sales representative. To locate the nearest Cypress office, visit our website.MPNFeaturesPackageMax CPU Speed (MHz)Flash (KB)SRAM (KB)UDBOpamp (CTBm)CapSenseDirect LCD Drive12-bit SAR ADCLP ComparatorsTCPWM BlocksSCB BlocksPWMs (using UDBs)I2S (using UDB)GPIOCYBLE-214009-00 48 256 32 4 4 3 3 1 Msps 1 4 2 4 325 32-SMTU.S. Cypress Headquarters Address 198 Champion Court, San Jose, CA 95134U.S. Cypress Headquarter Contact Info (408) 943-2600Cypress website address http://www.cypress.com
PRELIMINARY CYBLE-214009-00Document Number: 002-09714 Rev. ** Page 35 of 40AcronymsTable 55. Acronyms Used in this Document Acronym DescriptionABUS analog local busADC analog-to-digital converterAG analog globalAHB AMBA (advanced microcontroller bus archi-tecture) high-performance bus, an ARM data transfer busALU arithmetic logic unitAMUXBUS analog multiplexer busAPI application programming interfaceAPSR application program status registerARM®advanced RISC machine, a CPU architectureATM automatic thump modeBLE Bluetooth Low EnergyBluetooth SIGBluetooth Special Interest GroupBW bandwidthCAN Controller Area Network, a communications protocolCE European ConformityCSA Canadian Standards AssociationCMRR common-mode rejection ratioCPU central processing unitCRC cyclic redundancy check, an error-checking protocolDAC digital-to-analog converter, see also IDAC, VDACDFB digital filter blockDIO digital input/output, GPIO with only digital capabilities, no analog. See GPIO.DMIPS Dhrystone million instructions per secondDMA direct memory access, see also TDDNL differential nonlinearity, see also INLDNU do not useDR port write data registersDSI digital system interconnectDWT data watchpoint and traceECC error correcting codeECO external crystal oscillatorEEPROM electrically erasable programmable read-only memoryEMI electromagnetic interferenceEMIF external memory interfaceEOC end of conversionEOF end of frameEPSR execution program status register ESD electrostatic dischargeETM embedded trace macrocellFCC Federal Communications CommissionFET field-effect transistorFIR finite impulse response, see also IIRFPB flash patch and breakpointFS full-speedGPIO general-purpose input/output, applies to a PSoC pinHCI host controller interfaceHVI high-voltage interrupt, see also LVI, LVDIC integrated circuitIDAC current DAC, see also DAC, VDACIDE integrated development environmentI2C, or IIC Inter-Integrated Circuit, a communications protocolIC Industry CanadaIIR infinite impulse response, see also FIRILO internal low-speed oscillator, see also IMOIMO internal main oscillator, see also ILOINL integral nonlinearity, see also DNLI/O input/output, see also GPIO, DIO, SIO, USBIOIPOR initial power-on reset IPSR interrupt program status registerIRQ interrupt requestITM instrumentation trace macrocellKC Korea CertificationLCD liquid crystal displayLIN Local Interconnect Network, a communications protocol.LR link registerLUT lookup tableLVD low-voltage detect, see also LVILVI low-voltage interrupt, see also HVILVTTL low-voltage transistor-transistor logicTable 55. Acronyms Used in this Document (continued)Acronym Description
PRELIMINARY CYBLE-214009-00Document Number: 002-09714 Rev. ** Page 36 of 40MAC multiply-accumulateMCU microcontroller unitMIC Ministry of Internal Affairs and Communications (Japan)MISO master-in slave-outNC no connectNMI nonmaskable interruptNRZ non-return-to-zeroNVIC nested vectored interrupt controllerNVL nonvolatile latch, see also WOLOpamp operational amplifierPAL programmable array logic, see also PLDPC program counterPCB printed circuit boardPGA programmable gain amplifierPHUB peripheral hubPHY physical layerPICU port interrupt control unitPLA programmable logic arrayPLD programmable logic device, see also PALPLL phase-locked loopPMDD package material declaration data sheetPOR power-on resetPRES precise power-on resetPRS pseudo random sequencePS port read data registerPSoC®Programmable System-on-Chip™PSRR power supply rejection ratioPWM pulse-width modulatorQDID qualification design IDRAM random-access memoryRISC reduced-instruction-set computingRMS root-mean-squareRTC real-time clockRTL register transfer languageRTR remote transmission requestRX receiveSAR successive approximation registerSC/CT switched capacitor/continuous timeSCL I2C serial clockTable 55. Acronyms Used in this Document (continued)Acronym DescriptionSDA I2C serial dataS/H sample and holdSINAD signal to noise and distortion ratioSIO special input/output, GPIO with advanced features. See GPIO.SMT surface-mount technology; a method for producing electronic circuitry in which the compo-nents are placed directly onto the surface of PCBsSOC start of conversionSOF start of frameSPI Serial Peripheral Interface, a communications protocolSR slew rateSRAM static random access memorySRES software resetSTN super twisted nematicSWD serial wire debug, a test protocolSWV single-wire viewerTD transaction descriptor, see also DMATHD total harmonic distortionTIA transimpedance amplifierTN twisted nematicTRM technical reference manualTTL transistor-transistor logicTUV Germany: Technischer Überwachungs-Verein (Technical Inspection Association)TX transmitUART Universal Asynchronous Transmitter Receiver, a communications protocolUDB universal digital blockUSB Universal Serial BusUSBIO USB input/output, PSoC pins used to connect to a USB portVDAC voltage DAC, see also DAC, IDACWDT watchdog timerWOL write once latch, see also NVLWRES watchdog timer resetXRES external reset I/O pinXTAL crystalTable 55. Acronyms Used in this Document (continued)Acronym Description
PRELIMINARY CYBLE-214009-00Document Number: 002-09714 Rev. ** Page 37 of 40Document ConventionsUnits of MeasureTable 56. Units of MeasureSymbol Unit of Measure°C degrees CelsiusdB decibeldBm decibel-milliwattsfF femtofaradsHz hertzKB 1024 byteskbps kilobits per secondKhr kilohourkHz kilohertzkΩkilo ohmksps kilosamples per secondLSB least significant bitMbps megabits per secondMHz megahertzMΩmega-ohmMsps megasamples per secondµA microampereµF microfaradµH microhenryµs microsecondµV microvoltµW microwattmA milliamperems millisecondmV millivoltnA nanoamperens nanosecondnV nanovoltΩohmpF picofaradppm parts per millionps picoseconds secondsps samples per secondsqrtHz square root of hertzVvolt
PRELIMINARY CYBLE-214009-00Document Number: 002-09714 Rev. ** Page 38 of 40ErrataThis section describes the errata for the CYBLE-214009-00 module. Details include errata trigger conditions, scope of impact, andavailable workarounds. Contact your local Cypress Sales Representative if you have questions. Errata Summary1. CapSense is not enabled in PSoC Creator.n PROBLEM DEFINITION CapSense Support for CYBLE-214009-00 is not enabled in PSoC Creator 3.3. n PARAMETERS AFFECTED Nonen TRIGGER CONDITIONS Applicatoins that need CapSense functionality will not be able to enable it with PSoC Creator 3.3.n SCOPE OF IMPACT Nonen WORKAROUND No work aruond with PSoC Creator 3.3. n FIX STATUS This issue will be fixed in November, 2015 on a future PSoC Creator release. n CHANGES None
PRELIMINARY CYBLE-214009-00Document Number: 002-09714 Rev. ** Page 39 of 40Document History Page Document Title: CYBLE-214009-00 EZ-BLETM PSoC® ModuleDocument Number: 002-09714Revision ECN Orig. of ChangeSubmission Date Description of Change** DSO 10/29/2015 Preliminary datasheet for CYBLE-214009-00 module.
Document Number: 002-09714 Rev. ** Revised October 29, 2015 Page 40 of 40All products and company names mentioned in this document may be the trademarks of their respective holders.PRELIMINARY CYBLE-214009-00© Cypress Semiconductor Corporation, 2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of anycircuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as criticalcomponents in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systemsapplication implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypressintegrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited withoutthe express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIESOF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does notassume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems wherea malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturerassumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Sales, Solutions, and Legal InformationWorldwide Sales and Design SupportCypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.ProductsAutomotive cypress.com/go/automotiveClocks & Buffers cypress.com/go/clocksInterface cypress.com/go/interfaceLighting & Power Control cypress.com/go/powerpsocMemory cypress.com/go/memoryPSoC cypress.com/go/psocTouch Sensing cypress.com/go/touchUSB Controllers cypress.com/go/USBWireless/RF cypress.com/go/wirelessPSoC® Solutionspsoc.cypress.com/solutionsPSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LPCypress Developer CommunityCommunity | Forums | Blogs | Video | Training Technical Supportcypress.com/go/support

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