Cypress Semiconductor 4008 Bluetooth Module User Manual

Cypress Semiconductor Bluetooth Module

Contents

User Manual

PRELIMINARY CYBLE-014008-00
EZ-BLETM PSoC® Module
Cypress Semiconductor Corporation 198 Champion Court San Jose,CA 95134-1709 408-943-2600
Document Number: 002-00023 Rev. *C Revised October 29, 2015
General Description
The Cypress CYBLE-014008-00 is a fully certified and qualified
module supporting Bluetooth Low Energy (BLE) wireless
communication. The CYBLE-014008-00 is a turnkey solution
and includes onboard crystal oscillators, trace antenna, passive
components, and the Cypress PSoC® 4 BLE. Refer to the
PSoC® 4 BLE datasheet for additional details on the capabilities
of the PSoC® 4 BLE device used on this module.
The EZ-BLETM PSoC® module is a scalable and reconfigurable
platform architecture. It combines programmable and
reconfigurable analog and digital blocks with flexible automatic
routing. The CYBLE-014008-00 also includes digital
programmable logic, high-performance analog-to-digital
conversion (ADC), opamps with comparator mode, and standard
communication and timing peripherals.
The CYBLE-014008-00 includes a royalty-free BLE stack
compatible with Bluetooth 4.1 and provides up to 25 GPIOs in a
small 11 × 11 × 1.80 mm package.
The CYBLE-014008-00 is a complete solution and an ideal fit for
applications seeking a highly integrated BLE wireless solution.
Module Description
nModule size: 11.0 mm × 11.0 mm × 1.80 mm (with shield)
nBluetooth 4.1 single-mode module
nIndustrial temperature range: –40 °C to +85 °C
n32-bit processor (0.9 DMIPS/MHz) with single-cycle 32-bit
multiply, operating at up to 48 MHz
n128-KB flash memory
n16-KB SRAM memory
nWatchdog timer with dedicated internal low-speed oscillator
(ILO)
nTwo-pin SWD for programming
nUp to 25 GPIOs configurable as open drain high/low,
pull-up/pull-down, HI-Z analog, HI-Z digial, or strong output
nCertified to FCC, CE, MIC, KC, and IC regulations
nBluetooth SIG 4.1 qualified
Power Consumption
nTX output power: –18 dbm to +3 dbm
nReceived signal strength indicator (RSSI) with 1-dB resolution
nTX current consumption of 15.6 mA (radio only, 0 dbm)
nRX current consumption of 16.4 mA (radio only)
nLow power mode support
pDeep Sleep: 1.3 µA with watch crystal oscillator (WCO) on
pHibernate: 150 nA with SRAM retention
pStop: 60 nA with XRES wakeup
Programmable Analog
nFour opamps with reconfigurable high-drive external and
high-bandwidth internal drive, comparator modes, and ADC
input buffering capability; can operate in Deep-Sleep mode.
n12-bit, 1-Msps SAR ADC with differential and single-ended
modes; channel sequencer with signal averaging
nTwo current DACs (IDACs) for general-purpose or capacitive
sensing applications on any pin
nOne low-power comparator that operate in Deep-Sleep mode
Programmable Digital
nFour programmable logic blocks called universal digital blocks,
(UDBs), each with eight macrocells and datapath
nCypress-provided peripheral Component library, user-defined
state machines, and Verilog input
Capacitive Sensing
nCypress CapSense Sigma-Delta (CSD) provides best-in-class
SNR (> 5:1) and liquid tolerance
nCypress-supplied software component makes
capacitive-sensing design easy
nAutomatic hardware-tuning algorithm (SmartSense™)
Segment LCD Drive
nLCD drive supported on all GPIOs (common or segment)
nOperates in Deep-Sleep mode with four bits per pin memory
Serial Communication
nTwo independent runtime reconfigurable serial communication
blocks (SCBs) with I2C, SPI, or UART functionality
Timing and Pulse-Width Modulation
nFour 16-bit timer, counter, pulse-width modulator (TCPWM)
blocks
nCenter-aligned, Edge, and Pseudo-random modes
nComparator-based triggering of Kill signals for motor drive and
other high-reliability digital logic applications
Up to 25 Programmable GPIOs
nAny GPIO pin can be CapSense, LCD, analog, or digital
nTwo overvoltage-tolerant (OVT) pins; drive modes, strengths,
and slew rates are programmable
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Contents
Overview............................................................................ 3
Module Description...................................................... 3
Pad Connection Interface ................................................ 5
Recommended Host PCB Layout ................................... 6
Power Supply Connections and Recommended External
Components.................................................................... 10
Connection Options................................................... 10
External Component Recommendation .................... 10
Critical Components List ........................................... 13
Antenna Design......................................................... 13
Electrical Specification .................................................. 14
GPIO ......................................................................... 16
XRES......................................................................... 17
Analog Peripherals .................................................... 17
Digital Peripherals ..................................................... 21
Serial Communication ............................................... 23
Memory ..................................................................... 24
System Resources .................................................... 24
Environmental Specifications ....................................... 30
Environmental Compliance ....................................... 30
RF Certification.......................................................... 30
Environmental Conditions ......................................... 30
ESD and EMI Protection ........................................... 30
Regulatory Information .................................................. 31
FCC........................................................................... 31
Industry Canada (IC) Certification............................. 32
European R&TTE Declaration of Conformity ............ 32
MIC Japan................................................................. 33
KC Korea................................................................... 33
Ordering Information...................................................... 34
Part Numbering Convention...................................... 34
Acronyms........................................................................ 35
Document Conventions ................................................. 37
Units of Measure ....................................................... 37
Errata ............................................................................... 38
Document History Page................................................. 39
Sales, Solutions, and Legal Information ...................... 40
Worldwide Sales and Design Support....................... 40
Products .................................................................... 40
PSoC® Solutions ...................................................... 40
Cypress Developer Community................................. 40
Technical Support ..................................................... 40
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Overview
Module Description
The CYBLE-014008-00 module is a complete module designed to be soldered to the main host board.
Module Dimensions and Drawing
Cypress reserves the right to select components (including the appropriate BLE device) from various vendors to achieve the BLE
module functionality. Such selections will guarantee that all height restrictions of the component area are maintained. Designs should
be completed with the physical dimensions shown in the mechanical drawings in Figure 1. All dimensions are in millimeters (mm).
Table 1. Module Design Dimensions
See Figure 1 on page 4 for the mechanical reference drawing for CYBLE-014008-00.
Dimension Item Specification
Module dimensions Length (X) 11.00 ± 0.15 mm
Width (Y) 11.00 ± 0.15 mm
Antenna location dimensions Length (X) 11.00 ± 0.15 mm
Width (Y) 4.62 ± 0.15 mm
PCB thickness Height (H) 0.80 ± 0.10 mm
Shield height Height (H) 1.00 ± 0.10 mm
Maximum component height Height (H) 1.00 mm typical (shield)
Total module thickness (bottom of module to highest component) Height (H) 1.80 mm typical
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Figure 1. Module Mechanical Drawing
Top View
Side View
Bottom View
Note
1. No metal should be located beneath or above the antenna area. Only bare PCB material should be located beneath the antenna area. For more information on
recommended host PCB layout, see Figure 3 and Figure 4 on page 6.
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Pad Connection Interface
As shown in the bottom view of Figure 1 on page 4, the CYBLE-014008-00 connects to the host board via solder pads on the back
of the module. Table 2 and Figure 2 detail the solder pad length, width, and pitch dimensions of the CYBLE-014008-00 module.
Figure 2. Solder Pad Dimensions
Table 2. Solder Pad Connection Description
Name Connections Connection Type Pad Length Dimension Pad Width Dimension Pad Pitch
SP 32 Solder Pads Pad9/Pad24: 0.74 mm
All Others: 0.79 mm 0.41 mm 0.66 mm
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Recommended Host PCB Layout
Figure 3 details the recommended PCB layout pattern for the host PCB. Dimensions are in mm.
Figure 3. Recommended PCB Layout Pattern for CYBLE-014008-00
To maximize RF performance, the host layout should follow these recommendations:
1. The ideal placement of the Cypress BLE module is in a corner of the host board with the antenna located on the edge of the host
board. This placement minimizes the additional recommended keep-out area stated in item 2.
2. It is recommended that the area around the Cypress BLE module trace antenna should contain an additional keep-out area, where
no grounding or signal traces are contained. The keep-out area applies to all layers of the host board. The recommended
dimensions of the host PCB keep-out area are shown in Figure 4 (dimensions are in mm).
Figure 4. Recommended Host PCB Keep-Out Area Around the CYBLE-014008-00 Trace Antenna
Top View (On Host PCB)
Host PCB Keep-Out Area Around Trace Antenna
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Table 3 details the solder pad pitch (center-to-center) for each of the neighboring connections.
Table 3. Module Solder Pad Connection Dimensions
Pad X Pad Y Pad Pitch (Pad X - Pad Y) Comments
Bottom Right Corner 1 4.83 mm Distance from bottom right corner to Pad 1 center
1 2 0.66 mm Distance from Pad 1 center to Pad 2 center
2 3 0.66 mm Distance from Pad 2 center to Pad 3 center
3 4 0.66 mm Distance from Pad 3 center to Pad 4 center
4 5 0.66 mm Distance from Pad 4 center to Pad 5 center
5 6 0.66 mm Distance from Pad 5 center to Pad 6 center
6 7 0.66 mm Distance from Pad 6 center to Pad 7 center
7 8 0.66 mm Distance from Pad 7 center to Pad 8 center
8 9 0.66 mm Distance from Pad 8 center to Pad 9 center
Top Right Corner 10 1.21 mm Distance from Pad 9 center to Pad 10 center
10 11 0.66 mm Distance from Pad 10 center to Pad 11 center
11 12 0.66 mm Distance from Pad 11 center to Pad 12 center
12 13 0.66 mm Distance from Pad 12 center to Pad 13 center
13 14 0.66 mm Distance from Pad 13 center to Pad 14 center
14 15 0.66 mm Distance from Pad 14 center to Pad 15 center
15 16 0.66 mm Distance from Pad 15 center to Pad 16 center
16 17 0.66 mm Distance from Pad 16 center to Pad 17 center
17 18 0.66 mm Distance from Pad 17 center to Pad 18 center
18 19 0.66 mm Distance from Pad 18 center to Pad 19 center
19 20 0.66 mm Distance from Pad 19 center to Pad 20 center
20 21 0.66 mm Distance from Pad 20 center to Pad 21 center
21 22 0.66 mm Distance from Pad 21 center to Pad 22 center
22 23 0.66 mm Distance from Pad 22 center to Pad 23 center
Top Left Corner 24 0.89 mm Distance from Top Left Corner to Pad 24 center
24 25 0.66 mm Distance from Pad 24 center to Pad 25 center
25 26 0.66 mm Distance from Pad 25 center to Pad 26 center
26 27 0.66 mm Distance from Pad 26 center to Pad 27 center
27 28 0.66 mm Distance from Pad 27 center to Pad 28 center
28 29 0.66 mm Distance from Pad 28 center to Pad 29 center
29 30 0.66 mm Distance from Pad 29 center to Pad 30 center
30 31 0.66 mm Distance from Pad 30 center to Pad 31 center
31 32 0.66 mm Distance from Pad 31 center to Pad 32 center
32 Bottom Left Corner 4.83 mm Distance from Pad 32 center to Bottom Left Corner
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Table 4 and Ta ble 5 detail the solder pad connection definitions and available functions for each connection pad. Table 4 lists the
solder pads on CYBLE-014008-00, the BLE device port-pin, and denotes whether the digital function shown is available for each
solder pad. Table 5 denotes whether the analog function shown is available for each solder pad. Each connection is configurable for
a single option shown with a 3.
Table 4. Digital Peripheral Capabilities
Pad
Number
Device
Port Pin UART SPI I2CTCPWM[2] Cap-
Sense
WCO
Out
ECO
OUT LCD SWD GPIO
1GND
[3] Ground Connection
2P1.1 3(SCB1_SS1) 3(TCPWM0) 333
3P1.0 3(TCPWM0) 333
4P1.53(SCB0_TX) 3(SCB0_MISO) 3(SCB0_SCL) 3(TCPWM2) 333
5P0.13(SCB1_TX) 3(SCB1_MISO) 3(SCB1_SCL) 3(TCPWM0) 333
6P0.73(SCB0_CTS) 3(SCB0_SCLK) 3(TCPWM2) 33
3
(SWDCLK)
3
7 VDD Digital Power Supply Input (1.71 to 5.5V)
8P1.4
3(SCB0_RX) 3(SCB0_MOSI) 3(SCB0_SDA) 3(TCPWM2) 333
9P0.43(SCB0_RX) 3(SCB0_MOSI) 3(SCB0_SDA) 3(TCPWM1) 333 3
10 P0.5 3(SCB0_TX) 3(SCB0_MISO) 3(SCB0_SCL) 3(TCPWM1) 333
11 P0.6 3(SCB0_RTS) 3(SCB0_SS0) 3(TCPWM2) 333
(SWDIO)
3
12 P1.2 3(SCB1_SS2) 3(TCPWM1) 333
13 VDDR Radio Power Supply (1.9V to 5.5V)
14 P2.6 333
15 P1.3 3(SCB1_SS3) 3(TCPWM1) 333
16 P3.0 3(SCB0_RX) 3(SCB0_SDA) 3(TCPWM0) 333
17 P2.1 3(SCB0_SS2) 333
18 P2.2 3(SCB0_SS3) 333
19 P2.3 33 3 3
20 VDDA Analog Power Supply Input (1.71 to 5.5V)
21 P3.4 3(SCB1_RX) 3(SCB1_SDA) 3(TCPWM2) 333
22 P3.1 3(SCB0_TX) 3(SCB0_SCL) 3(TCPWM0) 333
23 P3.7 3(SCB1_CTS) 3(TCPWM3) 33 3 3
24 P3.5 3(SCB1_TX) 3(SCB1_SCL) 3(TCPWM2) 333
25 P3.3 3(SCB0_CTS) 3(TCPWM1) 333
26 VREF Reference Voltage Input
27 P3.2 3(SCB0_RTS) 3(TCPWM1) 333
28 P3.6 3(SCB1_RTS) 3(TCPWM3) 333
29 XRES External Reset Hardware Connection Input
30 P2.4 333
31 P2.5 333
32 GND Ground Connection
Notes
2. TCPWM stands for timer, counter, and PWM. If supported, the pad can be configured to any of these peripheral functions.
3. The main board needs to connect both GND connections (Pad 1 and Pad 32) on the module to the common ground of the system.
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.
Table 5. Analog Peripheral Capabilities
Pad Number Device Port Pin SARMUX OPAMP LPCOMP
1GND
[3] Ground Connection
2P1.1 3(CTBm1_OA0_INN)
3P1.0 3(CTBm1_OA0_INP)
4P1.5 3(CTBm1_OA1_INP)
5P0.1 3(COMP0_INN)
6P0.7
7 VDD Digital Power Supply Input (1.71 to 5.5V)
8P1.4 3(CTBm1_OA1_INN)
9P0.4 3(COMP1_INP)
10 P0.5 3(COMP1_INN)
11 P0.6
12 P1.2 3(CTBm1_OA0_OUT)
13 VDDR Radio Power Supply (1.9V to 5.5V)
14 P2.6 3(CTBm1_OA0_INP)
15 P1.3 3(CTBm1_OA1_OUT)
16 P3.0 3
17 P2.1 3(CTBm1_OA0_INN)
18 P2.2 3(CTBm1_OA0_OUT)
19 P2.3 3(CTBm1_OA1_OUT)
20 VDDA Analog Power Supply Input (1.71 to 5.5V)
21 P3.4 3
22 P3.1 3
23 P3.7 3
24 P3.5 3
25 P3.3 3
26 VREF Reference Voltage Input (Optional)
27 P3.2 3
28 P3.6 3
29 XRES External Reset Hardware Connection Input
30 P2.4 3(CTBm1_OA1_INN)
31 P2.5 3(CTBm1_OA1_INP)
32 GND Ground Connection
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Power Supply Connections and Recommended External Components
Power Connections
The CYBLE-014008-00 contains three power supply connec-
tions, VDD, VDDA, and VDDR. The VDD and VDDA connections
supply power for the digital and analog device operation respec-
tively. VDDR supplies power for the device radio.
VDD and VDDA accept a supply range of 1.71 V to 5.5 V. VDDR
accepts a supply range of 1.9 V to 5.5 V. These specifications
can be found in Ta ble 10. The maximum power supply ripple for
both power connections on the module is 100 mV, as shown in
Table 8.
The power supply ramp rate of VDD and VDDA must be equal
to or greater than that of VDDR when the radio is used.
Connection Options
Two connection options are available for any application:
1. Single supply: Connect VDD, VDDA, and VDDR to the same
supply.
2. Independent supply: Power VDD, VDDA, and VDDR
separately.
External Component Recommendation
In either connection scenario, it is recommended to place an
external ferrite bead between the supply and the module
connection. The ferrite bead should be positioned as close as
possible to the module pin connection.
Figure 5 details the recommended host schematic options for a
single supply scenario. The use of one or two ferrite beads will
depend on the specific application and configuration of the
CYBLE-014008-00.
Figure 6 details the recommended host schematic for an
independent supply scenario.
The recommended ferrite bead value is 330 Ω, 100 MHz. (Murata
BLM21PG331SN1D).
Figure 5. Recommended Host Schematic Options for a Single Supply Option
Three Ferrite Bead Option Single Ferrite Bead Option
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Figure 6. Recommended Host Schematic for an Independent Supply Option
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The CYBLE-014008-00 schematic is shown in Figure 7.
Figure 7. CYBLE-014008-00 Schematic Diagram
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Critical Components List
Table 6 details the critical components used in the CYBLE-014008-00 module.
Table 6. Critical Component List
Antenna Design
Table 7 details antenna used on the CYBLE-014008-00 module. The Cypress module performance improves many of these charac-
teristics. For more information, see Table 9.
Table 7. Trace Antenna Specifications
Component Reference Designator Description
Silicon U1 68-pin WLCSP Programmable System-on-Chip (PSoC) with BLE
Crystal Y1 24.000 MHz, 10PF
Crystal Y2 32.768 kHz, 12.5PF
Item Description
Frequency Range 2400 – 2500 MHz
Peak Gain 0.5 dBi typical
Average Gain -0.5 dBi typical
Return Loss 10 dB minimum
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Electrical Specification
Table 8 details the absolute maximum electrical characteristics for the Cypress BLE module.
Table 8. CYBLE-014008-00 Absolute Maximum Ratings
Table 9 details the RF characteristics for the Cypress BLE module.
Table 9. CYBLE-014008-00 RF Performance Characteristics
Table 10 through Table 50 list the module level electrical characteristics for the CYBLE-014008-00. All specifications are valid for –40
°C ≤ TA ≤ 85 °C and TJ ≤ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted.
Parameter Description Min Typ Max Units Details/Conditions
VDDD_ABS VDD, VDDA or VDDR supply relative to VSS (VSSD
= VSSA)–0.5 – 6 V Absolute maximum
VCCD_ABS Direct digital core voltage input relative to VSSD –0.5 – 1.95 V Absolute maximum
VDDD_RIPPLE Maximum power supply ripple for VDD, VDDA and
VDDR input voltage – – 100 mV
3.0V supply
Ripple frequency of 100 kHz
to 750 kHz
VGPIO_ABS GPIO voltage –0.5 – VDD +0.5 V Absolute maximum
IGPIO_ABS Maximum current per GPIO –25 – 25 mA Absolute maximum
IGPIO_injection GPIO injection current: Maximum for VIH > VDD
and minimum for VIL < VSS –0.5 – 0.5 mA Absolute maximum current
injected per pin
LU Pin current for latch up –200 200 mA –
Parameter Description Min Typ Max Units Details/Conditions
RFO RF output power on ANT –18 0 3 dBm Configurable via register
settings
RXSRF receive sensitivity on ANT – –91 – dBm Guaranteed by design
simulation; High Gain Mode
FRModule frequency range 2400 – 2480 MHz –
GPPeak gain – 0.5 – dBi –
GAvg Average gain – –0.5 – dBi –
RL Return loss – –10 – dB –
Table 10. CYBLE-014008-00 DC Specifications
Parameter Description Min Typ Max Units Details/Conditions
VDD1 Power supply input voltage (VDD = VDDA = VDDR) 1.71 – 5.5 V With regulator enabled
VDD2 Power supply input voltage unregulated (VDD =
VDDA = VDDR)1.71 1.8 1.89 V Internally unregulated
supply
VDDR1 Radio supply voltage (radio on) 1.9 – 5.5 V –
VDDR2 Radio supply voltage (radio off) 1.71 – 5.5 V –
Active Mode, VDD = 1.71 V to 5.5 V
IDD3 Execute from flash; CPU at 3 MHz – 1.7 – mA T = 25 °C,
VDD = 3.3 V
IDD4 Execute from flash; CPU at 3 MHz – – – mA T = –40 °C to 85 °C
IDD5 Execute from flash; CPU at 6 MHz – 2.5 – mA T = 25 °C,
VDD = 3.3 V
IDD6 Execute from flash; CPU at 6 MHz – – – mA T = –40 °C to 85 °C
IDD7 Execute from flash; CPU at 12 MHz – 4 – mA T = 25 °C,
VDD = 3.3 V
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IDD8 Execute from flash; CPU at 12 MHz – – – mA T = –40 °C to 85 °C
IDD9 Execute from flash; CPU at 24 MHz – 7.1 – mA T = 25 °C,
VDD = 3.3 V
IDD10 Execute from flash; CPU at 24 MHz – – – mA T = –40 °C to 85 °C
IDD11 Execute from flash; CPU at 48 MHz – 13.4 – mA T = 25 °C,
VDD = 3.3 V
IDD12 Execute from flash; CPU at 48 MHz – – – mA T = –40 °C to 85 °C
Sleep Mode, VDD = 1.71 to 5.5 V
IDD13 IMO on – – – mA T = 25 °C, VDD = 3.3 V,
SYSCLK = 3 MHz
Sleep Mode, VDD and VDDR = 1.9 to 5.5 V
IDD14 ECO on – – – mA T = 25 °C, VDD = 3.3 V,
SYSCLK = 3 MHz
Deep-Sleep Mode, VDD = 1.71 to 3.6 V
IDD15 WDT with WCO on – 1.3 – µA T = 25 °C,
VDD = 3.3 V
IDD16 WDT with WCO on – – – µA T = –40 °C to 85 °C
IDD17 WDT with WCO on – – – µA T = 25 °C,
VDD = 5 V
IDD18 WDT with WCO on – – – µA T = –40 °C to 85 °C
Deep-Sleep Mode, VDD = 1.71 to 1.89 V (Regulator Bypassed)
IDD19 WDT with WCO on – – – µA T = 25 °C
IDD20 WDT with WCO on – – – µA T = –40 °C to 85 °C
Hibernate Mode, VDD = 1.71 to 3.6 V
IDD27 GPIO and reset active – 150 – nA T = 25 °C,
VDD = 3.3 V
IDD28 GPIO and reset active – – – nA T = –40 °C to 85 °C
Hibernate Mode, VDD = 3.6 to 5.5 V
IDD29 GPIO and reset active – – – nA T = 25 °C,
VDD = 5 V
IDD30 GPIO and reset active – – – nA T = –40 °C to 85 °C
Stop Mode, VDD = 1.71 to 3.6 V
IDD33 Stop-mode current (VDD)–20–nA
T = 25 °C,
VDD = 3.3 V
IDD34 Stop-mode current (VDDR)–40–- nA
T = 25 °C,
VDDR = 3.3 V
IDD35 Stop-mode current (VDD) – – – nA T = –40 °C to 85 °C
IDD36 Stop-mode current (VDDR)–––nA
T = –40 °C to 85 °C,
VDDR = 1.9 V to 3.6 V
Stop Mode, VDD = 3.6 to 5.5 V
IDD37 Stop-mode current (VDD)–––nA
T = 25 °C,
VDD = 5 V
IDD38 Stop-mode current (VDDR)–––nA
T = 25 °C,
VDDR = 5 V
IDD39 Stop-mode current (VDD) – – – nA T = –40 °C to 85 °C
IDD40 Stop-mode current (VDDR) – – – nA T = –40 °C to 85 °C
Table 10. CYBLE-014008-00 DC Specifications (continued)
Parameter Description Min Typ Max Units Details/Conditions
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Table 11. AC Specifications
GPIO
Parameter Description Min Typ Max Units Details/Conditions
FCPU CPU frequency DC – 48 MHz 1.71 V ≤ VDD ≤ 5.5 V
TSLEEP Wakeup from Sleep mode – 0 – µs Guaranteed by characterization
TDEEPSLEEP Wakeup from Deep-Sleep mode – – 25 µs 24-MHz IMO. Guaranteed by
characterization
THIBERNATE Wakeup from Hibernate mode – – 800 µs Guaranteed by characterization
TSTOP Wakeup from Stop mode – – 2 ms XRES wakeup
Table 12. GPIO DC Specifications
Parameter Description Min Typ Max Units Details/Conditions
VIH[4]
Input voltage HIGH threshold 0.7 × VDD – – V CMOS input
LVTTL input, VDD < 2.7 V 0.7 × VDD – – V –
LVTTL input, VDD ≥ 2.7 V 2.0 – – V –
VIL
Input voltage LOW threshold – – 0.3 × VDD VCMOS input
LVTTL input, VDD < 2.7 V – – 0.3× VDD V–
LVTTL input, VDD ≥ 2.7 V – – 0.8 V –
VOH
Output voltage HIGH level VDD –0.6 – – V IOH = 4 mA at 3.3-V VDD
Output voltage HIGH level VDD –0.5 – – V IOH = 1 mA at 1.8-V VDD
VOL
Output voltage LOW level – – 0.6 V IOL = 8 mA at 3.3-V VDD
Output voltage LOW level – – 0.6 V IOL = 4 mA at 1.8-V VDD
Output voltage LOW level – – 0.4 V IOL = 3 mA at 3.3-V VDD
RPULLUP Pull-up resistor 3.5 5.6 8.5 kΩ–
RPULLDOWN Pull-down resistor 3.5 5.6 8.5 kΩ–
IIL Input leakage current (absolute value) – – 2 nA 25 °C, VDD = 3.3 V
IIL_CTBM Input leakage on CTBm input pins – – 4 nA –
CIN Input capacitance – – 7 pF –
VHYSTTL Input hysteresis LVTTL 25 40 – mV VDD > 2.7 V
VHYSCMOS Input hysteresis CMOS 0.05 × VDD – – 1 –
IDIODE Current through protection diode to
VDD/VSS – – 100 µA –
ITOT_GPIO Maximum total source or sink chip
current – – 200 mA –
Note
4. VIH must not exceed VDD + 0.2 V.
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Table 13. GPIO AC Specifications
XRES
Analog Peripherals
Opamp
Parameter Description Min Typ Max Units Details/Conditions
TRISEF Rise time in Fast-Strong mode 2 – 12 ns 3.3-V VDDD, CLOAD = 25 pF
TFALLF Fall time in Fast-Strong mode 2 – 12 ns 3.3-V VDDD, CLOAD = 25 pF
TRISES Rise time in Slow-Strong mode 10 – 60 ns 3.3-V VDDD, CLOAD = 25 pF
TFALLS Fall time in Slow-Strong mode 10 – 60 ns 3.3-V VDDD, CLOAD = 25 pF
FGPIOUT1 GPIO Fout; 3.3 V ≤ VDD ≤ 5.5 V
Fast-Strong mode ––33MHz
90/10%, 25 pF load, 60/40 duty
cycle
FGPIOUT2 GPIO Fout; 1.7 V≤ VDD ≤ 3.3 V
Fast-Strong mode – – 16.7 MHz 90/10%, 25 pF load, 60/40 duty
cycle
FGPIOUT3 GPIO Fout; 3.3 V ≤ VDD ≤ 5.5 V
Slow-Strong mode –– 7 MHz
90/10%, 25 pF load, 60/40 duty
cycle
FGPIOUT4 GPIO Fout; 1.7 V ≤ VDD ≤ 3.3 V
Slow-Strong mode ––3.5MHz
90/10%, 25 pF load, 60/40 duty
cycle
FGPIOIN GPIO input operating frequency
1.71 V ≤ VDD ≤ 5.5 V – – 48 MHz 90/10% VIO
Table 14. XRES DC Specifications
Parameter Description Min Typ Max Units Details/Conditions
VIH Input voltage HIGH threshold 0.7 × VDDD – – V CMOS input
VIL Input voltage LOW threshold – – 0.3 × VDDD V CMOS input
RPULLUP Pull-up resistor 3.5 5.6 8.5 kΩ–
CIN Input capacitance – 3 – pF –
VHYSXRES Input voltage hysteresis – 100 – mV –
IDIODE Current through protection diode to
VDD/VSS – – 100 µA –
Table 15. XRES AC Specifications
Parameter Description Min Typ Max Units Details/Conditions
TRESETWIDTH Reset pulse width 1 – – µs –
Table 16. Opamp Specifications
Parameter Description Min Typ Max Units Details/
Conditions
IDD (Opamp Block Current. VDD = 1.8 V. No Load)
IDD_HI Power = high – 1000 1300 µA
IDD_MED Power = medium – 500 – µA
IDD_LOW Power = low – 250 350 µA
GBW (Load = 20 pF, 0.1 mA. VDDA = 2.7 V)
GBW_HI Power = high 6 – – MHz
GBW_MED Power = medium 4 – – MHz
GBW_LO Power = low – 1 – MHz
IOUT_MAX (VDDA ≥ 2.7 V, 500 mV from Rail)
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IOUT_MAX_HI Power = high 10 – – mA
IOUT_MAX_MID Power = medium 10 – – mA
IOUT_MAX_LO Power = low – 5 – mA
IOUT (VDDA = 1.71 V, 500 mV from Rail)
IOUT_MAX_HI Power = high 4 – – mA
IOUT_MAX_MID Power = medium 4 – – mA
IOUT_MAX_LO Power = low – 2 – mA
VIN Charge pump on, VDDA ≥ 2.7 V –0.05 – VDDA – 0.2 V
VCM Charge pump on, VDDA ≥ 2.7 V –0.05 – VDDA – 0.2 V
VOUT (VDDA ≥ 2.7 V)
VOUT_1 Power = high, ILOAD=10 mA 0.5 – VDDA – 0.5 V
VOUT_2 Power = high, ILOAD=1 mA 0.2 – VDDA – 0.2 V
VOUT_3 Power = medium, ILOAD=1 mA 0.2 – VDDA – 0.2 V
VOUT_4 Power = low, ILOAD=0.1 mA 0.2 – VDDA – 0.2 V
VOS_TR Offset voltage, trimmed 1 ±0.5 1 mV High mode
VOS_TR Offset voltage, trimmed – ±1 – mV Medium mode
VOS_TR Offset voltage, trimmed – ±2 – mV Low mode
VOS_DR_TR Offset voltage drift, trimmed –10 ±3 10 µV/C High mode
VOS_DR_TR Offset voltage drift, trimmed – ±10 – µV/C Medium mode
VOS_DR_TR Offset voltage drift, trimmed – ±10 – µV/C Low mode
CMRR DC 65 70 – dB VDDD = 3.6 V,
High-power mode
PSRR At 1 kHz, 100-mV ripple 70 85 – dB VDDD = 3.6 V
Noise
VN1 Input referred, 1 Hz–1 GHz, power = high – 94 – µVrms
VN2 Input referred, 1 kHz, power = high – 72 – nV/rtHz
VN3 Input referred, 10 kHz, power = high – 28 – nV/rtHz
VN4 Input referred, 100 kHz, power = high – 15 – nV/rtHz
CLOAD Stable up to maximum load. Performance
specs at 50 pF
––125 pF
Slew_rate Cload = 50 pF, Power = High,
VDDA ≥ 2.7 V
6 – – V/µsec
T_op_wake From disable to enable, no external RC
dominating
– 300 – µsec
Comp_mode (Comparator Mode; 50-mV Drive, TRISE = TFALL (Approx.)
TPD1 Response time; power = high – 150 – nsec
TPD2 Response time; power = medium – 400 – nsec
TPD3 Response time; power = low – 2000 – nsec
Vhyst_op Hysteresis – 10 – mV
Deep-Sleep Mode (Deep-Sleep mode operation is only guaranteed for VDDA > 2.5 V)
GBW_DS Gain bandwidth product – 50 – kHz
IDD_DS Current – 15 – µA
Vos_DS Offset voltage – 5 – mV
Table 16. Opamp Specifications (continued)
Parameter Description Min Typ Max Units Details/
Conditions
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Temperature Sensor
SAR ADC
Vos_dr_DS Offset voltage drift – 20 – µV/°C
Vout_DS Output voltage 0.2 – VDD–0.2 V
Vcm_DS Common mode voltage 0.2 – VDD–1.8 V
Table 16. Opamp Specifications (continued)
Parameter Description Min Typ Max Units Details/
Conditions
Table 17. Comparator DC Specifications
Parameter Description Min Typ Max Units Details/
Conditions
VOFFSET1 Input offset voltage, Factory trim – – ±10 mV
VOFFSET2 Input offset voltage, Custom trim – – ±6 mV
VOFFSET3 Input offset voltage, ultra-low-power mode – ±12 – mV
VHYST Hysteresis when enabled – 10 35 mV
VICM1 Input common mode voltage in normal mode 0 – VDDD –0.1 V Modes 1 and 2
VICM2 Input common mode voltage in low-power
mode
0– V
DDD V
VICM3 Input common mode voltage in ultra
low-power mode
0–V
DDD
–1.15
V
CMRR Common mode rejection ratio 50 – – dB VDDD ≥ 2.7 V
CMRR Common mode rejection ratio 42 – – dB VDDD ≤ 2.7 V
ICMP1 Block current, normal mode – – 400 µA
ICMP2 Block current, low-power mode – – 100 µA
ICMP3 Block current in ultra-low-power mode – 6 – µA
ZCMP DC input impedance of comparator 35 – – MΩ
Table 18. Comparator AC Specifications
Parameter Description Min Typ Max Units Details/
Conditions
TRESP1 Response time, normal mode, 50-mV
overdrive
–38– ns50-mV overdrive
TRESP2 Response time, low-power mode, 50-mV
overdrive
–70– ns50-mV overdrive
TRESP3 Response time, ultra-low-power mode,
50-mV overdrive
– 2.3 – µs 200-mV overdrive
Table 19. Temperature Sensor Specifications
Parameter Description Min Typ Max Units Details/Conditions
TSENSACC Temperature-sensor accuracy –5 ±1 5 °C –40 to +85 °C
Table 20. SAR ADC DC Specifications
Parameter Description Min Typ Max Units Details/Conditions
A_RES Resolution – – 12 bits
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CSD
A_CHNIS_S Number of channels - single-ended – – 8 8 full-speed
A-CHNKS_D Number of channels - differential – – 4 Diff inputs use
neighboring I/O
A-MONO Monotonicity – – – Yes
A_GAINERR Gain error – – ±0.1 % With external
reference
A_OFFSET Input offset voltage – – 2 mV Measured with 1-V
VREF
A_ISAR Current consumption – – 1 mA
A_VINS Input voltage range - single-ended VSS –V
DDA V
A_VIND Input voltage range - differential VSS – VDDA V
A_INRES Input resistance – – 2.2 kΩ
A_INCAP Input capacitance – – 10 pF
VREFSAR Trimmed internal reference to SAR –1 – 1 % Percentage of Vbg
(1.024 V)
Table 20. SAR ADC DC Specifications
Table 21. SAR ADC AC Specifications
Parameter Description Min Typ Max Units Details/
Conditions
A_PSRR Power-supply rejection ratio 70 – – dB Measured at 1-V
reference
A_CMRR Common-mode rejection ratio 66 – – dB
A_SAMP Sample rate – – 1 Msps 806 Ksps for More Part
Numbers devices
Fsarintref SAR operating speed without external ref.
bypass
– – 100 Ksps 12-bit resolution
A_SNR Signal-to-noise ratio (SNR) 65 – – dB FIN = 10 kHz
A_BW Input bandwidth without aliasing – – A_SAMP/2 kHz
A_INL Integral nonlinearity. VDD = 1.71 V to 5.5 V,
1 Msps
–1.7 – 2 LSB VREF = 1 V to VDD
A_INL Integral nonlinearity. VDDD = 1.71 V to 3.6 V,
1 Msps
–1.5 – 1.7 LSB VREF = 1.71 V to VDD
A_INL Integral nonlinearity. VDD = 1.71 V to 5.5 V,
500 Ksps
–1.5 – 1.7 LSB VREF = 1 V to VDD
A_dnl Differential nonlinearity. VDD = 1.71 V to
5.5 V, 1 Msps
–1 – 2.2 LSB VREF = 1 V to VDD
A_DNL Differential nonlinearity. VDD = 1.71 V to
3.6 V, 1 Msps
–1 – 2 LSB VREF = 1.71 V to VDD
A_DNL Differential nonlinearity. VDD = 1.71 V to
5.5 V, 500 Ksps
–1 – 2.2 LSB VREF = 1 V to VDD
A_THD Total harmonic distortion – – –65 dB FIN = 10 kHz
CSD Block Specifications
Parameter Description Min Typ Max Units Details/
Conditions
VCSD Voltage range of operation 1.71 – 5.5 V
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Digital Peripherals
Timer
Counter
IDAC1 DNL for 8-bit resolution –1 – 1 LSB
IDAC1 INL for 8-bit resolution –3 – 3 LSB
IDAC2 DNL for 7-bit resolution –1 – 1 LSB
IDAC2 INL for 7-bit resolution –3 – 3 LSB
SNR Ratio of counts of finger to noise 5 – – Ratio Capacitance range of
9 pF to 35 pF, 0.1-pF
sensitivity. Radio is not
operating during the
scan
IDAC1_CRT1 Output current of IDAC1 (8 bits) in High
range
–612 – µA
IDAC1_CRT2 Output current of IDAC1 (8 bits) in Low
range
–306 – µA
IDAC2_CRT1 Output current of IDAC2 (7 bits) in High
range
–305 – µA
IDAC2_CRT2 Output current of IDAC2 (7 bits) in Low
range
–153 – µA
CSD Block Specifications (continued)
Parameter Description Min Typ Max Units Details/
Conditions
Table 22. Timer DC Specifications
Parameter Description Min Typ Max Units Details/Conditions
ITIM1 Block current consumption at 3 MHz – – 42 µA 16-bit timer
ITIM2 Block current consumption at 12 MHz – – 130 µA 16-bit timer
ITIM3 Block current consumption at 48 MHz – – 535 µA 16-bit timer
Table 23. Timer AC Specifications
Parameter Description Min Typ Max Units Details/Conditions
TTIMFREQ Operating frequency FCLK –48MHz
TCAPWINT Capture pulse width (internal) 2 × TCLK ––ns
TCAPWEXT Capture pulse width (external) 2 × TCLK ––ns
TTIMRES Timer resolution TCLK ––ns
TTENWIDINT Enable pulse width (internal) 2 × TCLK ––ns
TTENWIDEXT Enable pulse width (external) 2 × TCLK ––ns
TTIMRESWINT Reset pulse width (internal) 2 × TCLK ––ns
TTIMRESEXT Reset pulse width (external) 2 × TCLK ––ns
Table 24. Counter DC Specifications
Parameter Description Min Typ Max Units Details/Conditions
ICTR1 Block current consumption at 3 MHz – – 42 µA 16-bit counter
ICTR2 Block current consumption at 12 MHz – – 130 µA 16-bit counter
ICTR3 Block current consumption at 48 MHz – – 535 µA 16-bit counter
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Pulse Width Modulation (PWM)
LCD Direct Drive
Table 25. Counter AC Specifications
Parameter Description Min Typ Max Units Details/Conditions
TCTRFREQ Operating frequency FCLK –48MHz
TCTRPWINT Capture pulse width (internal) 2 × TCLK ––ns
TCTRPWEXT Capture pulse width (external) 2 × TCLK ––ns
TCTRES Counter Resolution TCLK ––ns
TCENWIDINT Enable pulse width (internal) 2 × TCLK ––ns
TCENWIDEXT Enable pulse width (external) 2 × TCLK ––ns
TCTRRESWINT Reset pulse width (internal) 2 × TCLK ––ns
TCTRRESWEXT Reset pulse width (external) 2 × TCLK –– ns
Table 26. PWM DC Specifications
Parameter Description Min Typ Max Units Details/Conditions
IPWM1 Block current consumption at 3 MHz – – 42 µA 16-bit PWM
IPWM2 Block current consumption at 12 MHz – – 130 µA 16-bit PWM
IPWM3 Block current consumption at 48 MHz – – 535 µA 16-bit PWM
Table 27. PWM AC Specifications
Parameter Description Min Typ Max Units Details/Conditions
TPWMFREQ Operating frequency FCLK –48MHz
TPWMPWINT Pulse width (internal) 2 × TCLK ––ns
TPWMEXT Pulse width (external) 2 × TCLK ––ns
TPWMKILLINT Kill pulse width (internal) 2 × TCLK ––ns
TPWMKILLEXT Kill pulse width (external) 2 × TCLK ––ns
TPWMEINT Enable pulse width (internal) 2 × TCLK ––ns
TPWMENEXT Enable pulse width (external) 2 × TCLK ––ns
TPWMRESWINT Reset pulse width (internal) 2 × TCLK ––ns
TPWMRESWEXT Reset pulse width (external) 2 × TCLK ––ns
Table 28. LCD Direct Drive DC Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID228 ILCDLOW Operating current in low-power mode – 17.5 – µA 16 × 4 small segment
display at 50 Hz
SID229 CLCDCAP LCD capacitance per segment/common
driver
– 500 5000 pF
SID230 LCDOFFSET Long-term segment offset – 20 – mV
SID231 ILCDOP1 LCD system operating current
VBIAS = 5 V
– 2 – mA 32 × 4 segments.
50 Hz at 25 °C
SID232 ILCDOP2 LCD system operating current
VBIAS = 3.3 V
– 2 – mA 32 × 4 segments
50 Hz at 25 °C
Table 29. LCD Direct Drive AC Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID233 FLCD LCD frame rate 10 50 150 Hz
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Serial Communication
Table 30. Fixed I2C DC Specifications
Table 32. Fixed UART DC Specifications
Table 33. Fixed UART AC Specifications
Parameter Description Min Typ Max Units Details/Conditions
II2C1 Block current consumption at 100 kHz – – 50 µA –
II2C2 Block current consumption at 400 kHz – – 155 µA –
II2C3 Block current consumption at 1 Mbps – – 390 µA –
II2C4 I2C enabled in Deep-Sleep mode – – 1.4 µA –
Table 31. Fixed I2C AC Specifications
Parameter Description Min Typ Max Units Details/Conditions
FI2C1 Bit rate – – 400 kHz
Parameter Description Min Typ Max Units Details/Conditions
IUART1 Block current consumption at 100 kbps – – 55 µA –
IUART2 Block current consumption at 1000 kbps – – 312 µA –
Parameter Description Min Typ Max Units Details/Conditions
FUART Bit rate – – 1 Mbps –
Table 34. Fixed SPI DC Specifications
Parameter Description Min Typ Max Units Details/Conditions
ISPI1 Block current consumption at 1 Mbps – – 360 µA –
ISPI2 Block current consumption at 4 Mbps – – 560 µA –
ISPI3 Block current consumption at 8 Mbps – – 600 µA –
Table 35. Fixed SPI AC Specifications
Parameter Description Min Typ Max Units Details/Conditions
FSPI SPI operating frequency (master; 6x over sampling) – – 8 MHz –
Table 36. Fixed SPI Master Mode AC Specifications
Parameter Description Min Typ Max Units Details/Conditions
TDMO MOSI valid after SCLK driving edge – – 18 ns –
TDSI MISO valid before SCLK capturing edge
Full clock, late MISO sampling used 20 – – ns Full clock, late MISO sampling
THMO Previous MOSI data hold time 0 – – ns Referred to Slave capturing edge
Table 37. Fixed SPI Slave Mode AC Specifications
Parameter Description Min Typ Max Units
TDMI MOSI valid before SCLK capturing edge 40 – – ns
TDSO MISO valid after SCLK driving edge – – 42 + 3 × TCPU ns
TDSO_ext MISO Valid after SCLK driving edge in
external clock mode. VDD < 3.0 V – – 50 ns
THSO Previous MISO data hold time 0 – – ns
TSSELSCK SSEL valid to first SCK valid edge 100 – – ns
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Memory
System Resources
Power-on-Reset (POR)
Note
5. It can take as much as 20 ms to write to flash. During this time, the device should not be reset, or flash operations will be interrupted and cannot be relied on to have
completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs. Make
certain that these are not inadvertently activated.
Table 38. Flash DC Specifications
Parameter Description Min Typ Max Units Details/Conditions
VPE Erase and program voltage 1.71 – 5.5 V –
TWS48 Number of Wait states at 32–48 MHz 2 – – CPU execution from flash
TWS32 Number of Wait states at 16–32 MHz 1 – – CPU execution from flash
TWS16 Number of Wait states for 0–16 MHz 0 – – CPU execution from flash
Table 39. Flash AC Specifications
Parameter Description Min Typ Max Units Details/Conditions
TROWWRITE[5] Row (block) write time (erase and program) – – 20 ms Row (block) = 128 bytes
TROWERASE[5] Row erase time – – 13 ms –
TROWPROGRAM[5] Row program time after erase – – 7 ms –
TBULKERASE[5] Bulk erase time (128 KB) – – 35 ms –
TDEVPROG[5] Total device program time – – 25 seconds –
FEND Flash endurance 100 K – – cycles –
FRET Flash retention. TA ≤ 55 °C, 100 K P/E cycles 20 – – years –
FRET2 Flash retention. TA ≤ 85 °C, 10 K P/E cycles 10 – – years –
Table 40. POR DC Specifications
Parameter Description Min Typ Max Units Details/Conditions
VRISEIPOR Rising trip voltage 0.80 – 1.45 V –
VFALLIPOR Falling trip voltage 0.75 – 1.40 V –
VIPORHYST Hysteresis 15 – 200 mV –
Table 41. POR AC Specifications
Parameter Description Min Typ Max Units Details/Conditions
TPPOR_TR Precision power-on reset (PPOR) response
time in Active and Sleep modes ––1µs –
Table 42. Brown-Out Detect
Parameter Description Min Typ Max Units Details/Conditions
VFALLPPOR BOD trip voltage in Active and Sleep modes 1.64 – – V –
VFALLDPSLP BOD trip voltage in Deep Sleep 1.4 – – V –
Table 43. Hibernate Reset
Parameter Description Min Typ Max Units Details/Conditions
VHBRTRIP BOD trip voltage in Hibernate 1.1 – – V –
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Voltage Monitors (LVD)
SWD Interface
Table 44. Voltage Monitor DC Specifications
Parameter Description Min Typ Max Units Details/Conditions
VLVI1 LVI_A/D_SEL[3:0] = 0000b 1.71 1.75 1.79 V –
VLVI2 LVI_A/D_SEL[3:0] = 0001b 1.76 1.80 1.85 V –
VLVI3 LVI_A/D_SEL[3:0] = 0010b 1.85 1.90 1.95 V –
VLVI4 LVI_A/D_SEL[3:0] = 0011b 1.95 2.00 2.05 V –
VLVI5 LVI_A/D_SEL[3:0] = 0100b 2.05 2.10 2.15 V –
VLVI6 LVI_A/D_SEL[3:0] = 0101b 2.15 2.20 2.26 V –
VLVI7 LVI_A/D_SEL[3:0] = 0110b 2.24 2.30 2.36 V –
VLVI8 LVI_A/D_SEL[3:0] = 0111b 2.34 2.40 2.46 V –
VLVI9 LVI_A/D_SEL[3:0] = 1000b 2.44 2.50 2.56 V –
VLVI10 LVI_A/D_SEL[3:0] = 1001b 2.54 2.60 2.67 V –
VLVI11 LVI_A/D_SEL[3:0] = 1010b 2.63 2.70 2.77 V –
VLVI12 LVI_A/D_SEL[3:0] = 1011b 2.73 2.80 2.87 V –
VLVI13 LVI_A/D_SEL[3:0] = 1100b 2.83 2.90 2.97 V –
VLVI14 LVI_A/D_SEL[3:0] = 1101b 2.93 3.00 3.08 V –
VLVI15 LVI_A/D_SEL[3:0] = 1110b 3.12 3.20 3.28 V –
VLVI16 LVI_A/D_SEL[3:0] = 1111b 4.39 4.50 4.61 V –
LVI_IDD Block current – – 100 µA –
Table 45. Voltage Monitor AC Specifications
Parameter Description Min Typ Max Units Details/Conditions
TMONTRIP Voltage monitor trip time – – 1 µs –
Table 46. SWD Interface Specifications
Parameter Description Min Typ Max Units Details/Conditions
F_SWDCLK1 3.3 V ≤ VDD ≤ 5.5 V – – 14 MHz SWDCLK ≤ 1/3 CPU clock frequency
F_SWDCLK2 1.71 V ≤ VDD ≤ 3.3 V – – 7 MHz SWDCLK ≤ 1/3 CPU clock frequency
T_SWDI_SETUP T = 1/f SWDCLK 0.25 × T – – ns –
T_SWDI_HOLD T = 1/f SWDCLK 0.25 × T – – ns –
T_SWDO_VALID T = 1/f SWDCLK – – 0.5 × T ns –
T_SWDO_HOLD T = 1/f SWDCLK 1 – – ns –
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Internal Main Oscillator
Internal Low-Speed Oscillator
Table 51. ECO Trim Value Specification
Table 47. IMO DC Specifications
Parameter Description Min Typ Max Units Details/Conditions
IIMO1 IMO operating current at 48 MHz – – 1000 µA –
IIMO2 IMO operating current at 24 MHz – – 325 µA –
IIMO3 IMO operating current at 12 MHz – – 225 µA –
IIMO4 IMO operating current at 6 MHz – – 180 µA –
IIMO5 IMO operating current at 3 MHz – – 150 µA –
Table 48. IMO AC Specifications
Parameter Description Min Typ Max Units Details/Conditions
FIMOTOL3 Frequency variation from 3 to 48 MHz – – ±2 % With API-called calibration
FIMOTOL3 IMO startup time – 12 – µs –
Table 49. ILO DC Specifications
Parameter Description Min Typ Max Units Details/Conditions
IILO2 ILO operating current at 32 kHz – 0.3 1.05 µA –
Table 50. ILO AC Specifications
Parameter Description Min Typ Max Units Details/Conditions
TSTARTILO1 ILO startup time – – 2 ms –
FILOTRIM1 32-kHz trimmed frequency 15 32 50 kHz –
Parameter Description Value Details/Conditions
ECOTRIM 24-MHz trim value
(firmware configuration) 0x00003FFA Optimum trim value that needs to be loaded to register
CY_SYS_XTAL_BLERD_BB_XO_CAPTRIM_REG
Table 52. UDB AC Specifications
Parameter Description Min Typ Max Units Details/Conditions
Data Path performance
FMAX-TIMER Max frequency of 16-bit timer in a UDB
pair
––48MHz
FMAX-ADDER Max frequency of 16-bit adder in a UDB
pair
––48MHz
FMAX_CRC Max frequency of 16-bit CRC/PRS in a
UDB pair
––48MHz
PLD Performance in UDB
FMAX_PLD Max frequency of 2-pass PLD function
in a UDB pair
––48MHz
Clock to Output Performance
TCLK_OUT_UDB1 Prop. delay for clock in to data out at
25 °C, Typical
–15 – ns
TCLK_OUT_UDB2 Prop. delay for clock in to data out,
Worst case
–25 – ns
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Table 53. BLE Subsystem
Parameter Description Min Typ Max Units Details/
Conditions
RF Receiver Specification
RXS, IDLE RX sensitivity with idle transmitter – –89 – dBm
RX sensitivity with idle transmitter
excluding Balun loss
– –91 – dBm Guaranteed by design
simulation
RXS, DIRTY RX sensitivity with dirty transmitter – –87 –70 dBm RF-PHY Specification
(RCV-LE/CA/01/C)
RXS, HIGHGAIN RX sensitivity in high-gain mode with idle
transmitter
– –91 – dBm
PRXMAX Maximum input power –10 –1 – dBm RF-PHY Specification
(RCV-LE/CA/06/C)
CI1 Cochannel interference,
Wanted signal at –67 dBm and Interferer
at FRX
– 9 21 dB RF-PHY Specification
(RCV-LE/CA/03/C)
CI2 Adjacent channel interference
Wanted signal at –67 dBm and Interferer
at FRX ±1 MHz
– 3 15 dB RF-PHY Specification
(RCV-LE/CA/03/C)
CI3 Adjacent channel interference
Wanted signal at –67 dBm and Interferer
at FRX ±2 MHz
– –29 – dB RF-PHY Specification
(RCV-LE/CA/03/C)
CI4 Adjacent channel interference
Wanted signal at –67 dBm and Interferer
at ≥FRX ±3 MHz
– –39 – dB RF-PHY Specification
(RCV-LE/CA/03/C)
CI5 Adjacent channel interference
Wanted Signal at –67 dBm and Interferer
at Image frequency (FIMAGE)
– –20 – dB RF-PHY Specification
(RCV-LE/CA/03/C)
CI3 Adjacent channel interference
Wanted signal at –67 dBm and Interferer
at Image frequency (FIMAGE ± 1 MHz)
– –30 – dB RF-PHY Specification
(RCV-LE/CA/03/C)
OBB1 Out-of-band blocking,
Wanted signal at –67 dBm and Interferer
at F = 30–2000 MHz
–30 –27 – dBm RF-PHY Specification
(RCV-LE/CA/04/C)
OBB2 Out-of-band blocking,
Wanted signal at –67 dBm and Interferer
at F = 2003–2399 MHz
–35 –27 – dBm RF-PHY Specification
(RCV-LE/CA/04/C)
OBB3 Out-of-band blocking,
Wanted signal at –67 dBm and Interferer
at F = 2484–2997 MHz
–35 –27 – dBm RF-PHY Specification
(RCV-LE/CA/04/C)
OBB4 Out-of-band blocking,
Wanted signal a –67 dBm and Interferer
at F = 3000–12750 MHz
–30 –27 – dBm RF-PHY Specification
(RCV-LE/CA/04/C)
IMD Intermodulation performance
Wanted signal at –64 dBm and 1-Mbps
BLE, third, fourth, and fifth offset channel
–50 – – dBm RF-PHY Specification
(RCV-LE/CA/05/C)
RXSE1 Receiver spurious emission
30 MHz to 1.0 GHz
– – –57 dBm 100-kHz measurement
bandwidth
ETSI EN300 328 V1.8.1
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RXSE2 Receiver spurious emission
1.0 GHz to 12.75 GHz
– – –47 dBm 1-MHz measurement
bandwidth
ETSI EN300 328 V1.8.1
RF Transmitter Specifications
TXP, ACC RF power accuracy – ±1 – dB
TXP, RANGE RF power control range – 20 – dB
TXP, 0dBm Output power, 0-dB Gain setting (PA7) – 0 – dBm
TXP, MAX Output power, maximum power setting
(PA10)
–3 – dBm
TXP, MIN Output power, minimum power setting
(PA1)
– –18 – dBm
F2AVG Average frequency deviation for
10101010 pattern
185 – – kHz RF-PHY Specification
(TRM-LE/CA/05/C)
F1AVG Average frequency deviation for
11110000 pattern
225 250 275 kHz RF-PHY Specification
(TRM-LE/CA/05/C)
EO Eye opening = ΔF2AVG/ΔF1AVG 0.8 – – RF-PHY Specification
(TRM-LE/CA/05/C)
FTX, ACC Frequency accuracy –150 – 150 kHz RF-PHY Specification
(TRM-LE/CA/06/C)
FTX, MAXDR Maximum frequency drift –50 – 50 kHz RF-PHY Specification
(TRM-LE/CA/06/C)
FTX, INITDR Initial frequency drift –20 – 20 kHz RF-PHY Specification
(TRM-LE/CA/06/C)
FTX, DR Maximum drift rate –20 – 20 kHz/
50 µs
RF-PHY Specification
(TRM-LE/CA/06/C)
IBSE1 In-band spurious emission at 2-MHz
offset
– – –20 dBm RF-PHY Specification
(TRM-LE/CA/03/C)
IBSE2 In-band spurious emission at ≥3-MHz
offset
– – -30 dBm RF-PHY Specification
(TRM-LE/CA/03/C)
TXSE1 Transmitter spurious emissions
(average), <1.0 GHz
– – -55.5 dBm FCC-15.247
TXSE2 Transmitter spurious emissions
(average), >1.0 GHz
– – -41.5 dBm FCC-15.247
RF Current Specifications
IRX Receive current in normal mode – 18.7 – mA
IRX_RF Radio receive current in normal mode – 16.4 – mA Measured at VDDR
IRX, HIGHGAIN Receive current in high-gain mode – 21.5 – mA
ITX, 3dBm TX current at 3-dBm setting (PA10) – 20 – mA
ITX, 0dBm TX current at 0-dBm setting (PA7) – 16.5 – mA
ITX_RF, 0dBm Radio TX current at 0 dBm setting (PA7) – 15.6 – mA Measured at VDDR
ITX_RF, 0dBm Radio TX current at 0 dBm excluding
Balun loss
– 14.2 – mA Guaranteed by design
simulation
ITX,-3dBm TX current at –3-dBm setting (PA4) – 15.5 – mA
ITX,-6dBm TX current at –6-dBm setting (PA3) – 14.5 – mA
Table 53. BLE Subsystem (continued)
Parameter Description Min Typ Max Units Details/
Conditions
PRELIMINARY CYBLE-014008-00
Document Number: 002-00023 Rev. *C Page 29 of 40
ITX,-12dBm TX current at –12-dBm setting (PA2) – 13.2 – mA
ITX,-18dBm TX current at –18-dBm setting (PA1) – 12.5 – mA
Iavg_1sec, 0dBm Average current at 1-second BLE
connection interval
– 17.1 – µA TXP: 0 dBm; ±20-ppm
master and slave clock
accuracy.
For empty PDU exchange
Iavg_4sec, 0dBm Average current at 4-second BLE
connection interval
– 6.1 – µA TXP: 0 dBm; ±20-ppm
master and slave clock
accuracy.
For empty PDU exchange
General RF Specifications
FREQ RF operating frequency 2400 – 2482 MHz
CHBW Channel spacing – 2 – MHz
DR On-air data rate – 1000 – kbps
IDLE2TX BLE.IDLE to BLE. TX transition time – 120 140 µs
IDLE2RX BLE.IDLE to BLE. RX transition time – 75 120 µs
RSSI Specifications
RSSI, ACC RSSI accuracy – ±5 – dB
RSSI, RES RSSI resolution – 1 – dB
RSSI, PER RSSI sample period – 6 – µs
Table 53. BLE Subsystem (continued)
Parameter Description Min Typ Max Units Details/
Conditions
PRELIMINARY CYBLE-014008-00
Document Number: 002-00023 Rev. *C Page 30 of 40
Environmental Specifications
Environmental Compliance
This Cypress BLE module is built in compliance with the Restriction of Hazardous Substances (RoHS) and Halogen Free (HF)
directives. The Cypress module and components used to produce this module are RoHS and HF compliant.
RF Certification
The CYBLE-014008-00 module is certified under the following RF certification standards:
nFCC ID: WAP4008
nCE
nIC: 7922A-4008
nMIC (Japan)
nKC: MSIP-CRM-Cyp-4008
Environmental Conditions
Table 54 describes the operating and storage conditions for the Cypress BLE module.
Table 54. Environmental Conditions for CYBLE-014008-00
ESD and EMI Protection
Exposed components require special attention to ESD and electromagnetic interference (EMI).
A grounded conductive layer inside the device enclosure is suggested for EMI and ESD performance. Any openings in the enclosure
near the module should be surrounded by a grounded conductive layer to provide ESD protection and a low-impedance path to ground.
Device Handling: Proper ESD protocol must be followed in manufacturing to ensure component reliability.
Description Minimum Specification Maximum Specification
Operating temperature -40 °C 85 °C
Operating humidity (relative, non-condensation) 5% 85%
Thermal ramp rate – 3 °C/minute
Storage temperature –40 °C 85 °C
Storage temperature and humidity – 85 ° C at 85%
ESD: Module integrated into system
Components[6] –15 kV Air
2.2 kV Contact
Note
6. This does not apply to the RF pins (ANT, XTALI, and XTALO). RF pins (ANT, XTALI, and XTALO) are tested for 500-V HBM.
PRELIMINARY CYBLE-014008-00
Document Number: 002-00023 Rev. *C Page 31 of 40
Regulatory Information
FCC
FCC NOTICE:
The device CYBLE-014008-00 complies with Part 15 of the FCC Rules. The device meets the requirements for modular transmitter
approval as detailed in FCC public Notice DA00-1407. Transmitter Operation is subject to the following two conditions: (1) This device
may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause
undesired operation.
CAUTION:
The FCC requires the user to be notified that any changes or modifications made to this device that are not expressly approved by
Cypress Semiconductor may void the user's authority to operate the equipment.
This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules.
These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment
generates and can radiate radio frequency energy and, if not installed and used in accordance with the instructions,ê may cause
harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation.
If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment
off and on, the user is encouraged to try to correct the interference by one or more of the following measures:
nReorient or relocate the receiving antenna.
nIncrease the separation between the equipment and receiver.
nConnect the equipment into an outlet on a circuit different from that to which the receiver is connected.
nConsult the dealer or an experienced radio/TV technician for help
LABELING REQUIREMENTS:
The Original Equipment Manufacturer (OEM) must ensure that FCC labelling requirements are met. This includes a clearly visible
label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor FCC identifier for this product as well
as the FCC Notice above. The FCC identifier is FCC ID: WAP4008.
In any case the end product must be labeled exterior with "Contains FCC ID: WAP4008"
ANTENNA WARNING:
This device is tested with a standard SMA connector and with the antennas listed in Table 7 on page 13. When integrated in the OEMs
product, these fixed antennas require installation preventing end-users from replacing them with non-approved antennas. Any antenna
not in the following table must be tested to comply with FCC Section 15.203 for unique antenna connectors and Section 15.247 for
emissions.
RF EXPOSURE:
To comply with FCC RF Exposure requirements, the Original Equipment Manufacturer (OEM) must ensure to install the approved
antenna in the previous.
The preceding statement must be included as a CAUTION statement in manuals, for products operating with the approved antennas
in Table 7 on page 13, to alert users on FCC RF Exposure compliance. Any notification to the end user of installation or removal
instructions about the integrated radio module is not allowed.
The radiated output power of CYBLE-014008-00 is far below the FCC radio frequency exposure limits. Nevertheless, use
CYBLE-014008-00 in such a manner that minimizes the potential for human contact during normal operation.
End users may not be provided with the module installation instructions. OEM integrators and end users must be provided with
transmitter operating conditions for satisfying RF exposure compliance.
PRELIMINARY CYBLE-014008-00
Document Number: 002-00023 Rev. *C Page 32 of 40
Industry Canada (IC) Certification
CYBLE-014008-00 is licensed to meet the regulatory requirements of Industry Canada (IC),
License: IC: 7922A-4008
Manufacturers of mobile, fixed or portable devices incorporating this module are advised to clarify any regulatory questions and ensure
compliance for SAR and/or RF exposure limits. Users can obtain Canadian information on RF exposure and compliance from
www.ic.gc.ca.
This device has been designed to operate with the antennas listed in Table 7 on page 13, having a maximum gain of 0.5 dBi. Antennas
not included in this list or having a gain greater than 0.5 dBi are strictly prohibited for use with this device. The required antenna
impedance is 50 ohms. The antenna used for this transmitter must not be co-located or operating in conjunction with any other antenna
or transmitter.
IC NOTICE:
The device CYBLE-014008-00 complies with Canada RSS-GEN Rules. The device meets the requirements for modular transmitter
approval as detailed in RSS-GEN. Operation is subject to the following two conditions: (1) This device may not cause harmful
interference, and (2) This device must accept any interference received, including interference that may cause undesired operation.
IC RADIATION EXPOSURE STATEMENT FOR CANADA
This device complies with Industry Canada licence-exempt RSS standard(s). Operation is subject to the following two conditions: (1)
this device may not cause interference, and (2) this device must accept any interference, including interference that may cause
undesired operation of the device.
Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation est
autorisée aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter
tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.
LABELING REQUIREMENTS:
The Original Equipment Manufacturer (OEM) must ensure that IC labelling requirements are met. This includes a clearly visible label
on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor IC identifier for this product as well as the IC
Notice above. The IC identifier is 7922A-4008. In any case, the end product must be labeled in its exterior with "Contains IC:
7922A-4008".
European R&TTE Declaration of Conformity
Hereby, Cypress Semiconductor declares that the Bluetooth module CYBLE-014008-00 complies with the essential requirements and
other relevant provisions of Directive 1999/5/EC. As a result of the conformity assessment procedure described in Annex III of the
Directive 1999/5/EC, the end-customer equipment should be labeled as follows:
All versions of the CYBLE-014008-00 in the specified reference design can be used in the following countries: Austria, Belgium,
Cyprus, Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Ireland, Italy, Latvia, Lithuania, Luxem-
bourg, Malta, Poland, Portugal, Slovakia, Slovenia, Spain, Sweden, The Netherlands, the United Kingdom, Switzerland, and Norway.
PRELIMINARY CYBLE-014008-00
Document Number: 002-00023 Rev. *C Page 33 of 40
MIC Japan
CYBLE-014008-00 is certified as a module with type certification number TBD. End products that integrate CYBLE-014008-00 do not
need additional MIC Japan certification for the end product.
End product can display the certification label of the embedded module.
KC Korea
CYBLE-014008-00 is certified for use in Korea with certificate number MSIP-CRM-Cyp-4008.
PRELIMINARY CYBLE-014008-00
Document Number: 002-00023 Rev. *C Page 34 of 40
Ordering Information
The CYBLE-014008-00 part number and features are listed in the following table.
Part Numbering Convention
The part numbers are of the form CYBLE-ABCDEF-GH where the fields are defined as follows.
For additional information and a complete list of Cypress Semiconductor BLE products, contact your local Cypress sales
representative. To locate the nearest Cypress office, visit our website.
MPN
Features
Package
Max CPU Speed (MHz)
Flash (KB)
SRAM (KB)
UDB
Opamp (CTBm)
CapSense
Direct LCD Drive
12-bit SAR ADC
LP Comparators
TCPWM Blocks
SCB Blocks
PWMs (using UDBs)
I2S (using UDB)
GPIO
CYBLE-014008-00 48 128 16 4 4 3 3 1 Msps 1 4 2 4 325 32-SMT
U.S. Cypress Headquarters Address 198 Champion Court, San Jose, CA 95134
U.S. Cypress Headquarter Contact Info (408) 943-2600
Cypress website address http://www.cypress.com
PRELIMINARY CYBLE-014008-00
Document Number: 002-00023 Rev. *C Page 35 of 40
Acronyms
Table 55. Acronyms Used in this Document
Acronym Description
ABUS analog local bus
ADC analog-to-digital converter
AG analog global
AHB AMBA (advanced microcontroller bus archi-
tecture) high-performance bus, an ARM data
transfer bus
ALU arithmetic logic unit
AMUXBUS analog multiplexer bus
API application programming interface
APSR application program status register
ARM®advanced RISC machine, a CPU architecture
ATM automatic thump mode
BLE Bluetooth Low Energy
Bluetooth
SIG
Bluetooth Special Interest Group
BW bandwidth
CAN Controller Area Network, a communications
protocol
CE European Conformity
CSA Canadian Standards Association
CMRR common-mode rejection ratio
CPU central processing unit
CRC cyclic redundancy check, an error-checking
protocol
DAC digital-to-analog converter, see also IDAC, VDAC
DFB digital filter block
DIO digital input/output, GPIO with only digital
capabilities, no analog. See GPIO.
DMIPS Dhrystone million instructions per second
DMA direct memory access, see also TD
DNL differential nonlinearity, see also INL
DNU do not use
DR port write data registers
DSI digital system interconnect
DWT data watchpoint and trace
ECC error correcting code
ECO external crystal oscillator
EEPROM electrically erasable programmable read-only
memory
EMI electromagnetic interference
EMIF external memory interface
EOC end of conversion
EOF end of frame
EPSR execution program status register
ESD electrostatic discharge
ETM embedded trace macrocell
FCC Federal Communications Commission
FET field-effect transistor
FIR finite impulse response, see also IIR
FPB flash patch and breakpoint
FS full-speed
GPIO general-purpose input/output, applies to a PSoC
pin
HCI host controller interface
HVI high-voltage interrupt, see also LVI, LVD
IC integrated circuit
IDAC current DAC, see also DAC, VDAC
IDE integrated development environment
I2C, or IIC Inter-Integrated Circuit, a communications
protocol
IC Industry Canada
IIR infinite impulse response, see also FIR
ILO internal low-speed oscillator, see also IMO
IMO internal main oscillator, see also ILO
INL integral nonlinearity, see also DNL
I/O input/output, see also GPIO, DIO, SIO, USBIO
IPOR initial power-on reset
IPSR interrupt program status register
IRQ interrupt request
ITM instrumentation trace macrocell
KC Korea Certification
LCD liquid crystal display
LIN Local Interconnect Network, a communications
protocol.
LR link register
LUT lookup table
LVD low-voltage detect, see also LVI
LVI low-voltage interrupt, see also HVI
LVTTL low-voltage transistor-transistor logic
Table 55. Acronyms Used in this Document (continued)
Acronym Description
PRELIMINARY CYBLE-014008-00
Document Number: 002-00023 Rev. *C Page 36 of 40
MAC multiply-accumulate
MCU microcontroller unit
MIC Ministry of Internal Affairs and Communications
(Japan)
MISO master-in slave-out
NC no connect
NMI nonmaskable interrupt
NRZ non-return-to-zero
NVIC nested vectored interrupt controller
NVL nonvolatile latch, see also WOL
Opamp operational amplifier
PAL programmable array logic, see also PLD
PC program counter
PCB printed circuit board
PGA programmable gain amplifier
PHUB peripheral hub
PHY physical layer
PICU port interrupt control unit
PLA programmable logic array
PLD programmable logic device, see also PAL
PLL phase-locked loop
PMDD package material declaration data sheet
POR power-on reset
PRES precise power-on reset
PRS pseudo random sequence
PS port read data register
PSoC®Programmable System-on-Chip™
PSRR power supply rejection ratio
PWM pulse-width modulator
QDID qualification design ID
RAM random-access memory
RISC reduced-instruction-set computing
RMS root-mean-square
RTC real-time clock
RTL register transfer language
RTR remote transmission request
RX receive
SAR successive approximation register
SC/CT switched capacitor/continuous time
SCL I2C serial clock
Table 55. Acronyms Used in this Document (continued)
Acronym Description
SDA I2C serial data
S/H sample and hold
SINAD signal to noise and distortion ratio
SIO special input/output, GPIO with advanced
features. See GPIO.
SMT surface-mount technology; a method for
producing electronic circuitry in which the compo-
nents are placed directly onto the surface of
PCBs
SOC start of conversion
SOF start of frame
SPI Serial Peripheral Interface, a communications
protocol
SR slew rate
SRAM static random access memory
SRES software reset
STN super twisted nematic
SWD serial wire debug, a test protocol
SWV single-wire viewer
TD transaction descriptor, see also DMA
THD total harmonic distortion
TIA transimpedance amplifier
TN twisted nematic
TRM technical reference manual
TTL transistor-transistor logic
TUV Germany: Technischer Überwachungs-Verein
(Technical Inspection Association)
TX transmit
UART Universal Asynchronous Transmitter Receiver, a
communications protocol
UDB universal digital block
USB Universal Serial Bus
USBIO USB input/output, PSoC pins used to connect to
a USB port
VDAC voltage DAC, see also DAC, IDAC
WDT watchdog timer
WOL write once latch, see also NVL
WRES watchdog timer reset
XRES external reset I/O pin
XTAL crystal
Table 55. Acronyms Used in this Document (continued)
Acronym Description
PRELIMINARY CYBLE-014008-00
Document Number: 002-00023 Rev. *C Page 37 of 40
Document Conventions
Units of Measure
Table 56. Units of Measure
Symbol Unit of Measure
°C degrees Celsius
dB decibel
dBm decibel-milliwatts
fF femtofarads
Hz hertz
KB 1024 bytes
kbps kilobits per second
Khr kilohour
kHz kilohertz
kΩkilo ohm
ksps kilosamples per second
LSB least significant bit
Mbps megabits per second
MHz megahertz
MΩmega-ohm
Msps megasamples per second
µA microampere
µF microfarad
µH microhenry
µs microsecond
µV microvolt
µW microwatt
mA milliampere
ms millisecond
mV millivolt
nA nanoampere
ns nanosecond
nV nanovolt
Ωohm
pF picofarad
ppm parts per million
ps picosecond
s second
sps samples per second
sqrtHz square root of hertz
Vvolt
PRELIMINARY CYBLE-014008-00
Document Number: 002-00023 Rev. *C Page 38 of 40
Errata
This section describes the errata for the CYBLE-014008-00 module. Details include errata trigger conditions, scope of impact, and
available workarounds. Contact your local Cypress Sales Representative if you have questions.
Errata Summary
1. CapSense is not enabled in PSoC Creator.
n PROBLEM DEFINITION
CapSense Support for CYBLE-014008-00 is not enabled in PSoC Creator 3.3.
n PARAMETERS AFFECTED
None
n TRIGGER CONDITIONS
Applicatoins that need CapSense functionality will not be able to enable it with PSoC Creator 3.3.
n SCOPE OF IMPACT
None
n WORKAROUND
No work aruond with PSoC Creator 3.3.
n FIX STATUS
This issue will be fixed in November, 2015 on a future PSoC Creator release.
n CHANGES
None
PRELIMINARY CYBLE-014008-00
Document Number: 002-00023 Rev. *C Page 39 of 40
Document History Page
Document Title: CYBLE-014008-00 EZ-BLETM PSoC® Module
Document Number: 002-00023
Revision ECN Orig. of
Change
Submission
Date Description of Change
** 4895738 DSO 8/26/2015 Preliminary datasheet for CYBLE-014008-00 module.
*A 4910660 DSO 9/07/2015 Modify reference of VDD/VDDA minimum voltage from 1.8V to 1.71V.
Update Table 2 on page 5 Connections number from 21 to 32.
Remove Footnotes 4, 5, and 6 on Page 8.
Update Table 5 on page 9 to remove LPCOMP capabilities from Pads 2, 3, 4, 14,
30, and 31.
Update Table 5 on page 9 to specify Vref (Pad 26) as Optional.
Update Figure 5 on page 10 to swap diagram descriptions.
Update Table 11 on page 16 THibernate from 2 ms to 800 µs.
Update Table 53 on page 27 - changed power consumption Iavg_1sec from 18.5
mA to 17.1 mA.
Update Table 53 on page 27 - changed power consumption Iavg_4sec from 6.25
mA to 6.1 mA.
*B 4944131 DSO 09/25/2015 Update Table 3 on page 7 to correct a typo in seventh row - changed “Distance
from top right corner to Pad 6 center” to ““Distance from Pad 5 center to Pad 6
center”.
Corrected Footnotes 3 to specify ground connection as Pad 1 and Pad 32.
Added VDDA to VDDD_RIPPLE specification description Table 8 on page 14.
Update Table 10 on page 14, parameters VDD1 and VDD2 to specify that VDD =
VDDA = VDDR
Removed Table 14 (OVT GPIO DC Specifications) and Table 15 (OVT GPIO AC
Specifications).
Added regulatory certification country in RF Certification on page 30
Added Errata section on page 38.
*C DSO 10/29/2015 Update General Description to add reference link to PSoC® 4 BLE datasheet.
Update Regulatory Information section to include final FCC, IC, and KC certifi-
cation identification numbers.
Update Industry Canada (IC) Certification on page 32 to add IC Radiation
Exposure Statement for Canada (English and French language) per Industry
Canada Requirements.
Document Number: 002-00023 Rev. *C Revised October 29, 2015 Page 40 of 40
All products and company names mentioned in this document may be the trademarks of their respective holders.
PRELIMINARY CYBLE-014008-00
© Cypress Semiconductor Corporation, 2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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