Cypress Cy62137Fv30 Users Manual MoBL® 2 Mbit (128K X 16) Static RAM
CY62137FV30 to the manual 05d9b701-655a-4290-afed-f12fec96d4eb
2015-02-05
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Page Count: 12
- Features
- Functional Description
- Logic Block Diagram
- Product Portfolio
- Pin Configuration
- Maximum Ratings
- Operating Range
- Electrical Characteristics
- Capacitance
- Thermal Resistance
- AC Test Loads and Waveforms
- Data Retention Characteristics
- Data Retention Waveform
- Switching Characteristics
- Switching Waveforms
- Truth Table
- Ordering Information
- Package Diagram
- Document History Page
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Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-07141 Rev. *F Revised January 2, 2008
CY62137FV30 MoBL®
2-Mbit (128K x 16) Static RAM
Features
■Very high speed: 45 ns
■Temperature ranges
❐Industrial: –40°C to +85°C
❐Automotive-A: –40°C to +85°C
❐Automotive-E: –40°C to +125°C
■Wide voltage range: 2.20V–3.60V
■Pin compatible with CY62137CV/CV25/CV30/CV33,
CY62137V, and CY62137EV30
■Ultra low standby power
❐Typical standby current: 1 μA
❐Maximum standby current: 5 μA (Industrial)
■Ultra low active power
❐Typical active current: 1.6 mA at f = 1 MHz (45 ns speed)
■Easy memory expansion with CE and OE features
■Automatic power down when deselected
■CMOS for optimum speed and power
■Byte power down feature
■Available in Pb free 48-Ball VFBGA and 44-pin TSOP II
package
Functional Description
The CY62137FV30 is a high performance CMOS static RAM
organized as 128K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL®) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption by 90% when addresses are not toggling. Placing
the device into standby mode reduces power consumption by
more than 99% when deselected (CE HIGH or both BLE and
BHE are HIGH). The input and output pins (IO0 through IO15) are
placed in a high impedance state in the following conditions:
■Deselected (CE HIGH)
■Outputs are disabled (OE HIGH
■Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH)
■Write operation is active (CE LOW and WE LOW)
Write to the device by taking Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from IO pins (IO0 through IO7) is written into the location
specified on the address pins (A0 through A16). If Byte High
Enable (BHE) is LOW, then data from IO pins (IO8 through IO15)
is written into the location specified on the address pins (A0
through A16).
Read from the device by taking Chip Enable (CE) and Output
Enable (OE) LOW, while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appear on IO0 to IO7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on IO8 to IO15. See the “Truth Table” on page 9 for a
complete description of read and write modes.
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
128K x 16
RAM Array IO0–IO7
ROW DECODER
A8
A7
A6
A5
A2
COLUMN DECODER
A11
A12
A13
A14
A15
SENSE AMPS
DATA IN DRIVERS
OE
A4
A3IO8–IO15
CE
WE
BHE
A16
A0
A1
A9
A10
BLE
BHE
BLE
CE
POWER DOWN
CIRCUIT
Logic Block Diagram
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CY62137FV30 MoBL®
Document Number: 001-07141 Rev. *F Page 2 of 12
Product Portfolio
Product Range VCC Range (V) Speed
(ns)
Power Dissipation
Operating ICC (mA) Standby ISB2
(μA)
f = 1MHz f = fmax
Min Typ [1] Max Typ [1] Max Typ [1] Max Typ [1] Max
CY62137FV30LL Ind’l/Auto-A 2.2V 3.0V 3.6V 45 1.6 2.5 13 18 1 5
Auto-E 2.2V 3.0V 3.6V 55 2 3 15 25 1 20
Pin Configuration
Figure 1. 48-Ball VFBGA Pinout [2, 3] Figure 2. 44-Pin TSOP II [2]
WE
A11
A10
A6
A0
A3CE
IO10
IO8
IO9
A4
A5
IO11
IO13
IO12
IO14
IO15
VSS
A9
A8
OE
A7
IO0
BHE
NC
NC
A2
A1
BLE
IO2
IO1
IO3
IO4
IO5IO6
IO7
A15
A14
A13
A12
NC
NC NC
326
5
41
D
E
B
A
C
F
G
H
A16
NC
VCC
VCC VSS
1
2
3
4
5
6
7
8
9
11
14 31
32
36
35
34
33
37
40
39
38
12
13
41
44
43
42
16
15 29
30
A
5
18
17
20
19 27
28
25
26
22
21 23
24
A
6
A
7
A
4
A
3
A
2
A
1
A
0
A
14
A
15
A
8
A
9
A
10
A
11
A
12
A
13
NC
OE
BHE
BLE
CE
WE
IO
0
IO
1
IO
2
IO
3
IO
4
IO
5
IO
6
IO
7
IO
8
IO
9
IO
10
IO
11
IO
12
IO
13
IO
14
IO
15
V
CC
V
CC
V
SS
V
SS
NC
10
A
16
Notes
1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C.
2. NC pins are not connected on the die.
3. Pins D3, H1, G2, and H6 in the VFBGA package are address expansion pins for 4 Mb, 8 Mb, 16 Mb, and 32 Mb, respectively.
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CY62137FV30 MoBL®
Document Number: 001-07141 Rev. *F Page 3 of 12
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................ –65°C to + 150°C
Ambient Temperature with
Power Applied .......................................... –55°C to + 125°C
Supply Voltage to Ground
Potential ...........................................................-0.3V to 3.9V
DC Voltage Applied to Outputs
in High Z state [4, 5]............................................-0.3V to 3.9V
DC Input Voltage [4, 5].......................................–0.3V to 3.9V
Output Current into Outputs (LOW) ............................ 20 mA
Static Discharge Voltage ......................................... > 2001V
(MIL–STD–883, Method 3015)
Latch up Current .................................................... > 200 mA
Operating Range
Device Range Ambient
Temperature VCC [6]
CY62137FV30LL Ind’l/Auto-A –40°C to +85°C 2.2V to 3.6V
Auto-E –40°C to +125°C
Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions 45 ns (Ind’l/Auto-A) 55 ns (Auto-E) Unit
Min Typ[1] Max Min Typ[1] Max
VOH Output HIGH Voltage 2.2 < VCC < 2.7 IOH = –0.1 mA 2.0 2.0 V
2.7 < VCC < 3.6 IOH = –1.0 mA 2.4 2.4 V
VOL Output LOW Voltage 2.2 < VCC < 2.7 IOL = 0.1 mA 0.4 0.4 V
2.7 < VCC < 3.6 IOL = 2.1mA 0.4 0.4 V
VIH Input HIGH Voltage 2.2 < VCC < 2.7 1.8 VCC + 0.3 1.8 VCC + 0.3 V
2.7 < VCC < 3.6 2.2 VCC + 0.3 2.2 VCC + 0.3 V
VIL Input LOW Voltage 2.2 < VCC < 2.7 –0.3 0.6 –0.3 0.6 V
2.7 < VCC < 3.6 –0.3 0.8 –0.3 0.8 V
IIX Input Leakage Current GND < VI < VCC –1 +1 –4 +4 μA
IOZ Output Leakage
Current GND < VO < VCC, Output disabled –1 +1 –4 +4 μA
ICC VCC Operating Supply
Current f = fmax = 1/tRC VCC = VCC(max)
IOUT = 0 mA
CMOS levels
13 18 15 25 mA
f = 1 MHz 1.6 2.5 2 3
ISB1 Automatic CE Power
Down Current – CMOS
Inputs
CE > VCC – 0.2V,
VIN > VCC – 0.2V, VIN < 0.2V
f = fmax (address and data only),
f = 0 (OE, WE, BHE, and BLE), VCC = 3.60V
15 120μA
ISB2 [7] Automatic CE Power
Down Current – CMOS
Inputs
CE > VCC – 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V,
f = 0, VCC = 3.60V
15 120μA
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter Description Test Conditions Max Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VCC = VCC(typ)
10 pF
COUT Output Capacitance 10 pF
Notes
4. VIL(min) = –2.0V for pulse durations less than 20 ns.
5. VIH(max)=VCC+0.75V for pulse durations less than 20 ns.
6. Full device AC operation assumes a minimum of 100 μs ramp time from 0 to VCC(min) and 200 μs wait time after VCC stabilization.
7. Only chip enable (CE) and byte enables (BHE and BLE) are tied to CMOS levels to meet the ISB2 / ICCDR specification. Other inputs can be left floating.
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CY62137FV30 MoBL®
Document Number: 001-07141 Rev. *F Page 4 of 12
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
Parameter Description Test Conditions VFBGA TSOP II Unit
ΘJA Thermal Resistance
(Junction to Ambient) Still air, soldered on a 3 × 4.5 inch,
two layer printed circuit board 75 77 °C/W
ΘJC Thermal Resistance
(Junction to Case) 10 13 °C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveform
Parameters 2.5V (2.2V to 2.7V) 3.0V (2.7V to 3.6V) Unit
R1 16667 1103 Ω
R2 15385 1554 Ω
RTH 8000 645 Ω
VTH 1.20 1.75 V
Data Retention Characteristics
Over the Operating Range
Parameter Description Conditions Min Typ [1] Max Unit
VDR VCC for Data Retention 1.5 V
ICCDR [7] Data Retention Current VCC = 1.5V, CE > VCC - 0.2V,
VIN > VCC - 0.2V or VIN < 0.2V
Ind’l/Auto-A 4 μA
Auto-E 12
tCDR [8] Chip Deselect to Data Retention Time 0 ns
tR [9] Operation Recovery Time tRC ns
Data Retention Waveform Figure 4. Data Retention Waveform [10]
VCC
VCC
OUTPUT
R2
30 pF GND
90%
10% 90%
10%
Rise Time = 1 V/ns Fall Time = 1 V/ns
OUTPUT
Equivalent to: THÉVENIN EQUIVALENT
ALL INPUT PULSES
RTH
R1
V
INCLUDING
JIG AND
SCOPE
VCC(min)
VCC(min)
tCDR
VDR >1.5V
DATA RETENTION MODE
tR
VCC
CE or
BHE.BLE
Notes
8. Tested initially and after any design or process changes that may affect these parameters.
9. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 μs or stable at VCC(min) > 100 μs.
10. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE.
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CY62137FV30 MoBL®
Document Number: 001-07141 Rev. *F Page 5 of 12
Switching Characteristics
Over the Operating Range [11, 12]
Parameter Description 45 ns (Ind’l/Auto-A) 55 ns (Auto-E) Unit
Min Max Min Max
Read Cycle
tRC Read Cycle Time 45 55 ns
tAA Address to Data Valid 45 55 ns
tOHA Data Hold From Address Change 10 10 ns
tACE CE LOW to Data Valid 45 55 ns
tDOE OE LOW to Data Valid 22 25 ns
tLZOE OE LOW to Low Z [13] 55ns
tHZOE OE HIGH to High Z [13, 14] 18 20 ns
tLZCE CE LOW to Low Z [13] 10 10 ns
tHZCE CE HIGH to High Z [13, 14] 18 20 ns
tPU CE LOW to Power Up 00ns
tPD CE HIGH to Power Down 45 55 ns
tDBE BLE/BHE LOW to Data Valid 45 55 ns
tLZBE BLE/BHE LOW to Low Z [13, 15] 510ns
tHZBE BLE/BHE HIGH to High Z [13, 14] 18 20 ns
Write Cycle [16]
tWC Write Cycle Time 45 55 ns
tSCE CE LOW to Write End 35 40 ns
tAW Address Setup to Write End 35 40 ns
tHA Address Hold from Write End 0 0 ns
tSA Address Setup to Write Start 0 0 ns
tPWE WE Pulse Width 35 40 ns
tBW BLE/BHE LOW to Write End 35 40 ns
tSD Data Setup to Write End 25 25 ns
tHD Data Hold From Write End 0 0 ns
tHZWE WE LOW to High Z [13, 14] 18 20 ns
tLZWE WE HIGH to Low Z [13] 10 10 ns
Notes
11. Test conditions for all parameters, other than tri-state parameters, assume signal transition time of 3 ns (1V/ns) or less, timing reference levels of VCC(typ)/2, input pulse
levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in “AC Test Loads and Waveforms” on page 4.
12. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. Please see application note AN13842 for further clarification.
13. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
14. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.
15. If both byte enables are toggled together, this value is 10 ns.
16. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals are ACTIVE to initiate a write and any of these
signals terminate a write by going INACTIVE. The data input setup and hold timing are referenced to the edge of the signal that terminates the write.
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CY62137FV30 MoBL®
Document Number: 001-07141 Rev. *F Page 6 of 12
Switching Waveforms
Figure 5. Read Cycle 1: Address Transition Controlled [17, 18]
Figure 6. Read Cycle 2: OE Controlled [18, 19]
PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
ADDRESS
DATA OUT
50%
50%
DATA VALID
t
RC
t
ACE
t
LZBE
t
LZCE
t
PU
HIGH IMPEDANCE
I
CC
t
HZOE
t
HZCE
t
PD
t
HZBE
t
LZOE
t
DBE
t
DOE
IMPEDANCE
HIGH
I
SB
DATA OUT
OE
CE
V
CC
SUPPLY
CURRENT
BHE/BLE
ADDRESS
Notes
17. The device is continuously selected. OE, CE = VIL, BHE and/or BLE = VIL.
18. WE is HIGH for read cycle.
19. Address valid before or similar to CE and BHE, BLE transition LOW.
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CY62137FV30 MoBL®
Document Number: 001-07141 Rev. *F Page 7 of 12
Figure 7. Write Cycle 1: WE Controlled [16, 20, 21]
Figure 8. Write Cycle 2: CE Controlled [16, 20, 21]
Switching Waveforms (continued)
tHD
tSD
tPWE
tSA
tHA
tAW
tWC
tHZOE
DATAIN
NOTE 22
tBW
tSCE
DATA IO
ADDRESS
CE
WE
OE
BHE/BLE
tHD
tSD
tPWE
tHA
tAW
tSCE
tWC
tHZOE
DATAIN
tBW
tSA
CE
ADDRESS
WE
DATA IO
OE
BHE/BLE
NOTE 22
Notes
20. Data IO is high impedance if OE = VIH.
21. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
22. During this period, the IOs are in output state. Do not apply input signals.
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CY62137FV30 MoBL®
Document Number: 001-07141 Rev. *F Page 8 of 12
Figure 9. Write Cycle 3: WE Controlled, OE LOW [21]
Figure 10. Write Cycle 4: BHE/BLE Controlled, OE LOW [21]
Switching Waveforms (continued)
DATAIN
tHD
tSD
tLZWE
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZWE
tBW
NOTE 22
CE
ADDRESS
WE
DATA IO
BHE/BLE
t
HD
t
SD
t
SA
t
HA
t
AW
tWC
DATA
IN
t
BW
tSCE
t
PWE
tHZWE
tLZWE
NOTE 22
DATA IO
ADDRESS
CE
WE
BHE/BLE
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CY62137FV30 MoBL®
Document Number: 001-07141 Rev. *F Page 9 of 12
Truth Table
CE WE OE BHE BLE Inputs or Outputs Mode Power
HXXXXHigh Z Deselect or Power Down Standby (I
SB)
X X X H H High Z Deselect or Power Down Standby (ISB)
L H L L L Data Out (IO0–IO15)Read Active (I
CC)
LHLHLData Out (IO
0–IO7);
IO8–IO15 in High Z Read Active (ICC)
L H L L H Data Out (IO8–IO15);
IO0–IO7 in High Z Read Active (ICC)
L H H L L High Z Output Disabled Active (ICC)
L H H H L High Z Output Disabled Active (ICC)
L H H L H High Z Output Disabled Active (ICC)
L L X L L Data In (IO0–IO15) Write Active (ICC)
L L X H L Data In (IO0–IO7);
IO8–IO15 in High Z Write Active (ICC)
L L X L H Data In (IO8–IO15);
IO0–IO7 in High Z Write Active (ICC)
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CY62137FV30 MoBL®
Document Number: 001-07141 Rev. *F Page 10 of 12
Ordering Information
Speed
(ns) Ordering Code Package
Diagram Package Type Operating
Range
45 CY62137FV30LL-45BVI 51-85150 48-Ball VFBGA Industrial
CY62137FV30LL-45BVXI 48-Ball VFBGA (Pb-free)
CY62137FV30LL-45ZSXI 51-85087 44-Pin TSOP II (Pb-free)
45 CY62137FV30LL-45ZSXA 51-85087 44-Pin TSOP II (Pb-free) Automotive-A
55 CY62137FV30LL-55ZSXE 51-85087 44-Pin TSOP II (Pb-free) Automotive-E
Contact your local Cypress sales representative for availability of these parts.
Package Diagram
Figure 11. 48-Ball VFBGA (6 x 8 x 1 mm)
A
1
A1 CORNER
0.75
0.75
Ø0.30±0.05(48X)
Ø0.25 M C A B
Ø0.05 M C
B
A
0.15(4X)
0.21±0.05
1.00 MAX
C
SEATING PLANE
0.55 MAX.
0.25 C
0.10 C
A1 CORNER
TOP VIEW BOTTOM VIEW
234
3.75
5.25
B
C
D
E
F
G
H
65
465231
D
H
F
G
E
C
B
A
6.00±0.10
8.00±0.10
A
8.00±0.10
6.00±0.10
B
1.875
2.625
0.26 MAX.
51-85150-*D
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CY62137FV30 MoBL®
© Cypress Semiconductor Corporation, 2006-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-07141 Rev. *F Revised January 2, 2008 Page 12 of 12
MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.
Document History Page
Document Title: CY62137FV30 MoBL® 2-Mbit (128K x 16) Static RAM
Document Number: 001-07141
REV. ECN NO. Issue
Date Orig. of
Change Description of Change
** 449438 See ECN NXR New datasheet
*A 464509 See ECN NXR Changed the ISB2(typ) value from 1.0 μA to 0.5 μA
Changed the ISB2(max) value from 4 μA to 2.5 μA
Changed the ICC(typ) value from 2 mA to 1.6 mA and ICC(max) value from
2.5 mA to 2.25 mA for f=1 MHz test condition
Changed the ICC(typ) value from 15 mA to 13 mA and ICC(max) value from
20 mA to 18 mA for f=1 MHz test condition
Changed the ICCDR(typ) value from 0.7 μA to 0.5 μA and ICCDR(max) value from 3 μA to
2.5 μA
*B 566724 See ECN NXR Converted from preliminary to final
Changed the ICC(max) value from 2.25 mA to 2.5 mA for test condition f=1 MHz
Changed the ISB2(typ) value from 0.5 μA to 1 μA
Changed the ISB2(max) value from 2.5 μA to 5 μA
Changed the ICCDR(typ) value from 0.5 μA to 1 μA and ICCDR(max) value from 2.5 μA to
4 μA
*C 869500 See ECN VKN Added Automotive-A and Automotive-E information
Updated Ordering Information Table
Added footnote 13 related to tACE
*D 901800 See ECN VKN Added footnote 9 related to ISB2 and ICCDR
Made footnote 14 applicable to AC parameters from tACE
*E 1371124 See ECN VKN/AESA Converted Automotive information from preliminary to final
Changed IIX min spec from –1 μA to –4 μA and IIX max spec from +1 μA to +4 μA
Changed IOZ min spec from –1 μA to –4 μA and IOZ max spec from +1 μA to +4 μA
*F 1875374 See ECN VKN/AESA Added -45BVI part in the Ordering Information table
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