EZ USB® FX3™ Technical Reference Manual 001 76074 USB FX3
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- EZ-USB® FX3™ Technical Reference Manual
- Contents
- 1. Introduction to EZ-USB FX3
- 2. FX3 CPU Subsystem
- 3. Memory and System Interconnect
- 4. Global Controller (GCTL)
- 5. FX3 DMA Subsystem
- 5.1 DMA Introduction
- 5.2 DMA Features
- 5.3 DMA Block Diagram
- 5.4 DMA Overview
- 5.5 DMA Subsystem Components
- 5.6 Programming Sequence
- 5.7 CPU Intervention In Between Ingress and Egress
- 5.8 Concept of DMA Channels
- 6. Universal Serial Bus (USB)
- 6.1 Introduction
- 6.2 Features
- 6.3 Block Diagram
- 6.4 Overview
- 6.5 UIB Top-Level Register Interface
- 6.6 USB Function Controllers
- 6.7 USB 2.0 Function
- 6.8 USB 3.0 and USB 2.0 Function Coordination
- 6.9 USB Function Programming Model
- 6.10 USB OTG Controller
- 6.11 USB Charger Detect Controller
- 7. General Programmable Interface II (GPIF II)
- 7.1 Features
- 7.2 Block Diagram
- 7.3 Typical GPIF II interface
- 7.4 Functional Overview
- 7.4.1 Actions
- 7.4.1.1 Action - IN_DATA
- 7.4.1.2 Action - IN_ADDR
- 7.4.1.3 Action - DR_DATA
- 7.4.1.4 Action - DR_ADDR
- 7.4.1.5 Action - COMMIT
- 7.4.1.6 Action - DR_GPIO
- 7.4.1.7 Action - LD_ADDR_COUNT
- 7.4.1.8 Action - LD_DATA_COUNT
- 7.4.1.9 Action - LD_CTRL_COUNT
- 7.4.1.10 Action - COUNT_ADDR
- 7.4.1.11 Action - COUNT_DATA
- 7.4.1.12 Action - COUNT_CTRL
- 7.4.1.13 Action - CMP_ADDR
- 7.4.1.14 Action - CMP_DATA
- 7.4.1.15 Action - CMP_CTRL
- 7.4.1.16 Action - INTR_CPU
- 7.4.1.17 Action - INTR_HOST
- 7.4.1.18 Action - DR_DRQ
- 7.4.2 Triggers
- 7.4.3 Transition Conditions
- 7.4.4 GPIF II Designer Tool
- 7.4.5 GPIF II Hardware Resources
- 7.4.6 Threads and Sockets
- 7.4.7 Addressing
- 7.4.8 Async/Sync
- 7.4.9 Configuration of Flags
- 7.4.10 Developing the GPIF II State Machine
- 7.4.1 Actions
- 7.5 Designing a GPIF II Interface
- 7.6 GPIF II State Machine Implementation
- 7.7 GPIF II Constraints
- 7.8 Initialization and Configuration of GPIF II Block
- 7.9 Performing Read and Write Operations Using GPIF II
- 7.10 DMA Channel Creation in FX3 Firmware to Perform GPIF II to USB Data Transfers
- 7.11 GPIF II State Machine to Read Data into a Socket
- 7.12 DMA Channel Creation in FX3 Firmware to Perform USB to GPIF II Data Transfers
- 7.13 GPIF II State Machine to Drive Data from Socket as Data Source
- 7.14 GPIF II Read and Write over Registers
- 7.15 Implementing Synchronous Slave FIFO Interface
- 7.16 Synchronous Slave FIFO Access Sequence and Interface Timing
- 8. Low Performance Peripherals (LPP)
- 8.1 I2C Interface
- 8.2 FX3 I2C Operations Overview
- 8.3 Serial Peripheral Interface
- 8.4 Programming Model
- 8.5 Examples
- 8.6 Universal Asynchronous Receiver Transmitter
- 8.7 FX3 UART Operations Overview
- 8.8 Integrated Interchip Sound Interface
- 8.8.1 I2S Block Features
- 8.8.2 I2S Overview
- 8.8.3 FX3 I2S Operations Overview
- 8.8.4 Programming Model
- 8.8.4.1 Start Transmission
- 8.8.4.2 Mute Condition
- 8.8.4.3 Pause Condition
- 8.8.4.4 Buffer Underflow
- 8.8.4.5 Stop Event
- 8.8.4.6 Fixed Clock Mode
- 8.8.4.7 Data Shift Mode
- 8.8.4.8 Padding
- 8.8.4.9 Error Conditions
- 8.8.4.10 Examples
- 8.8.4.11 Initialize I2S Block
- 8.8.4.12 Configure I2S Interface
- 8.8.4.13 Transferring Data from USB Interface to I2S Interface Using DMA Transfers
- 8.9 GPIO
- 9. Storage Ports
- 9.1 Storage Interface Block Features
- 9.2 Block Diagram
- 9.3 Storage Interface (S-Port)
- 9.4 SD/ MMC/ SDIO Interface
- 9.5 FX3S S-Port Operations Overview
- 9.5.1 S-port Initialization and Configuration
- 9.5.2 Reads and Writes to SD/ MMC Using DMA Transfers
- 9.5.3 Working with SDIO Cards
- 9.5.3.1 Configuration and Initialization
- 9.5.3.2 Reads and Writes from SDIO Card Registers
- 9.5.3.3 IO_RW_DIRECT Command (CMD52)
- 9.5.3.4 Setting Function Block Size
- 9.5.3.5 Initialization and Operation of SDIO Functions
- 9.5.3.6 SDIO Interrupts
- 9.5.3.7 Enabling and Disabling SDIO Interrupts
- 9.5.3.8 Handling SDIO Interrupts
- 9.6 FX3S-Specific Features
- 10. Registers
- 10.1 Introduction
- 10.2 Register Conventions
- 10.3 Vectored Interrupt Controller (VIC) Registers
- 10.4 Global Controller Registers
- 10.4.1 GCTL_IOMATRIX
- 10.4.2 GCTL_GPIO_SIMPLE
- 10.4.3 GCTL_GPIO_COMPLEX
- 10.4.4 GCTL_DS
- 10.4.5 GCTL_WPU_CFG
- 10.4.6 GCTL_WPD_CFG
- 10.4.7 GCTL_IOPOWER
- 10.4.8 GCTL_IOPOWER_INTR
- 10.4.9 GCTL_IOPOWER_INTR_MASK
- 10.4.10 GCTL_SW_INT
- 10.4.11 GCTL_PLL_CFG
- 10.4.12 GCTL_CPU_CLK_CFG
- 10.4.13 GCTL_UIB_CORE_CLK
- 10.4.14 GCTL_PIB_CORE_CLK
- 10.4.15 GCTL_GPIO_FAST_CLK
- 10.4.16 GCTL_GPIO_SLOW_CLK
- 10.4.17 GCTL_I2C_CORE_CLK
- 10.4.18 GCTL_UART_CORE_CLK
- 10.4.19 GCTL_SPI_CORE_CLK
- 10.4.20 GCTL_I2S_CORE_CLK
- 10.5 Global Controller Always On Registers
- 10.6 PIB Registers
- 10.7 GPIF Registers
- 10.7.1 GPIF_CONFIG
- 10.7.2 GPIF_BUS_CONFIG
- 10.7.3 GPIF_BUS_CONFIG2
- 10.7.4 GPIF_AD_CONFIG
- 10.7.5 GPIF_STATUS
- 10.7.6 GPIF_INTR
- 10.7.7 GPIF_INTR_MASK
- 10.7.8 GPIF_CTRL_BUS_DIRECTION
- 10.7.9 GPIF_CTRL_BUS_DEFAULT
- 10.7.10 GPIF_CTRL_BUS_POLARITY
- 10.7.11 GPIF_CTRL_BUS_TOGGLE
- 10.7.12 GPIF_CTRL_BUS_SELECT
- 10.7.13 GPIF_CTRL_COUNT_CONFIG
- 10.7.14 GPIF_CTRL_COUNT_RESET
- 10.7.15 GPIF_CTRL_COUNT_LIMIT
- 10.7.16 GPIF_ADDR_COUNT_CONFIG
- 10.7.17 GPIF_ADDR_COUNT_RESET
- 10.7.18 GPIF_ADDR_COUNT_LIMIT
- 10.7.19 GPIF_STATE_COUNT_CONFIG
- 10.7.20 GPIF_STATE_COUNT_LIMIT
- 10.7.21 GPIF_DATA_COUNT_CONFIG
- 10.7.22 GPIF_DATA_COUNT_RESET
- 10.7.23 GPIF_DATA_COUNT_LIMIT
- 10.7.24 GPIF_CTRL_COMP_VALUE
- 10.7.25 GPIF_CTRL_COMP_MASK
- 10.7.26 GPIF_DATA_COMP_VALUE
- 10.7.27 GPIF_DATA_COMP_MASK
- 10.7.28 GPIF_ADDR_COMP_VALUE
- 10.7.29 GPIF_ADDR_COMP_MASK
- 10.7.30 GPIF_DATA_CTRL
- 10.7.31 GPIF_INGRESS_DATA
- 10.7.32 GPIF_EGRESS_DATA
- 10.7.33 GPIF_INGRESS_ADDRESS
- 10.7.34 GPIF_EGRESS_ADDRESS
- 10.7.35 GPIF_THREAD_CONFIG
- 10.7.36 GPIF_LAMBDA_STAT
- 10.7.37 GPIF_ALPHA_STAT
- 10.7.38 GPIF_BETA_STAT
- 10.7.39 GPIF_WAVEFORM_CTRL_STAT
- 10.7.40 GPIF_WAVEFORM_SWITCH
- 10.7.41 GPIF_WAVEFORM_SWITCH_TIMEOUT
- 10.7.42 GPIF_CRC_CONFIG
- 10.7.43 GPIF_CRC_DATA
- 10.7.44 GPIF_BETA_DEASSERT
- 10.7.45 GPIF_FUNCTION
- 10.7.46 GPIF_LEFT_WAVEFORM
- 10.7.47 GPIF_RIGHT_WAVEFORM
- 10.8 P-Port Registers
- 10.8.1 PP_ID
- 10.8.2 PP_INIT
- 10.8.3 PP_CONFIG
- 10.8.4 PP_INTR_MASK
- 10.8.5 PP_DRQR5_MASK
- 10.8.6 PP_SOCK_MASK
- 10.8.7 PP_ERROR
- 10.8.8 PP_DMA_XFER
- 10.8.9 PP_DMA_SIZE
- 10.8.10 PP_WR_MAILBOX
- 10.8.11 PP_MMIO_ADDR
- 10.8.12 PP_MMIO_DATA
- 10.8.13 PP_MMIO
- 10.8.14 PP_EVENT
- 10.8.15 PP_RD_MAILBOX
- 10.8.16 PP_SOCK_STAT
- 10.8.17 PP_BUF_SIZE_CNT
- 10.9 USB Port Registers
- 10.10 USB2 HS/FS/LS PHY Registers
- 10.11 USB2 Device Controller Registers
- 10.12 USB Controller Miscellaneous Registers
- 10.13 USB End Point Manager Registers
- 10.14 USB2 Host Controller Registers
- 10.14.1 HOST_CS
- 10.14.2 HOST_EP_INTR
- 10.14.3 HOST_EP_INTR_MASK
- 10.14.4 HOST_TOGGLE
- 10.14.5 HOST_SHDL_CS
- 10.14.6 HOST_SHDL_SLEEP
- 10.14.7 HOST_RESP_BASE
- 10.14.8 HOST_RESP_CS
- 10.14.9 HOST_ACTIVE_EP
- 10.14.10 OHCI_REVISION
- 10.14.11 OHCI_CONTROL
- 10.14.12 OHCI_COMMAND_STATUS
- 10.14.13 OHCI_INTERRUPT_STATUS
- 10.14.14 OHCI_INTERRUPT_ENABLE
- 10.14.15 OHCI_INTERRUPT_DISABLE
- 10.14.16 OHCI_FM_INTERVAL
- 10.14.17 OHCI_FM_REMAINING
- 10.14.18 OHCI_FM_NUMBER
- 10.14.19 OHCI_PERIODIC_START
- 10.14.20 OHCI_LS_THRESHOLD
- 10.14.21 OHCI_RH_PORT_STATUS
- 10.14.22 OHCI_EOF
- 10.14.23 EHCI_HCCPARAMS
- 10.14.24 EHCI_USBCMD
- 10.14.25 EHCI_USBSTS
- 10.14.26 EHCI_USBINTR
- 10.14.27 EHCI_FRINDEX
- 10.14.28 EHCI_CONFIGFLAG
- 10.14.29 EHCI_PORTSC
- 10.14.30 EHCI_EOF
- 10.14.31 SHDL_CHNG_TYPE
- 10.14.32 SHDL_STATE_MACHINE
- 10.14.33 SHDL_INTERNAL_STATUS
- 10.14.34 SHDL_OHCI
- 10.14.35 SHDL_EHCI
- 10.15 USB3 Link Controller Registers
- 10.15.1 LNK_CONF
- 10.15.2 LNK_INTR
- 10.15.3 LNK_INTR_MASK
- 10.15.4 LNK_ERROR_CONF
- 10.15.5 LNK_ERROR_STATUS
- 10.15.6 LNK_ERROR_COUNT
- 10.15.7 LNK_ERROR_COUNT_THRESHOLD
- 10.15.8 LNK_PHY_CONF
- 10.15.9 LNK_PHY_MPLL_STATUS
- 10.15.10 LNK_PHY_TX_TRIM
- 10.15.11 LNK_PHY_ERROR_CONF
- 10.15.12 LNK_PHY_ERROR_STATUS
- 10.15.13 LNK_DEVICE_POWER_CONTROL
- 10.15.14 LNK_LTSSM_STATE
- 10.15.15 LNK_LFPS_OBSERVE
- 10.15.16 LNK_COMPLIANCE_PATTERN_0
- 10.15.17 LNK_COMPLIANCE_PATTERN_1
- 10.15.18 LNK_COMPLIANCE_PATTERN_2
- 10.15.19 LNK_COMPLIANCE_PATTERN_3
- 10.15.20 LNK_COMPLIANCE_PATTERN_4
- 10.15.21 LNK_COMPLIANCE_PATTERN_5
- 10.15.22 LNK_COMPLIANCE_PATTERN_6
- 10.15.23 LNK_COMPLIANCE_PATTERN_7
- 10.15.24 LNK_COMPLIANCE_PATTERN_8
- 10.16 USB3 Protocol Layer Registers
- 10.16.1 PROT_CS
- 10.16.2 PROT_INTR
- 10.16.3 PROT_INTR_MASK
- 10.16.4 PROT_FRAMECNT
- 10.16.5 PROT_ITP_TIME
- 10.16.6 PROT_ITP_TIMESTAMP
- 10.16.7 PROT_SETUP_DAT
- 10.16.8 PROT_SEQ_NUM
- 10.16.9 PROT_EP_INTR
- 10.16.10 PROT_EP_INTR_MASK
- 10.16.11 PROT_EPI_CS1
- 10.16.12 PROT_EPI_CS2
- 10.16.13 PROT_EPI_UNMAPPED_STREAM
- 10.16.14 PROT_EPI_MAPPED_STREAM
- 10.16.15 PROT_EPO_CS1
- 10.16.16 PROT_EPO_CS2
- 10.16.17 PROT_EPO_UNMAPPED_STREAM
- 10.16.18 PROT_EPO_MAPPED_STREAM
- 10.17 USB Port - SuperSpeed Ingress Socket Registers
- 10.18 I2S Registers
- 10.19 I2C Registers
- 10.19.1 I2C_CONFIG
- 10.19.2 I2C_STATUS
- 10.19.3 I2C_INTR
- 10.19.4 I2C_INTR_MASK
- 10.19.5 I2C_TIMEOUT
- 10.19.6 I2C_DMA_TIMEOUT
- 10.19.7 I2C_PREAMBLE_CTRL
- 10.19.8 I2C_PREAMBLE_DATA
- 10.19.9 I2C_PREAMBLE_RPT
- 10.19.10 I2C_COMMAND
- 10.19.11 I2C_EGRESS_DATA
- 10.19.12 I2C_INGRESS_DATA
- 10.19.13 I2C_CLOCK_LOW_COUNT
- 10.19.14 I2C_BYTE_COUNT
- 10.19.15 I2C_BYTES_TRANSFERRED
- 10.19.16 I2C_SOCKET
- 10.19.17 I2C_ID
- 10.19.18 I2C_POWER
- 10.20 UART Registers
- 10.21 SPI Registers
- 10.22 General Purpose IO Block Registers
- 10.23 General Purpose IO Registers (one pin)
- 10.24 Low Performance Peripherals Registers
- 10.25 DMA Socket and Descriptor Registers
- 10.26 DMA Adapter Global Registers
- 10.26.1 SCK_INTR
- 10.26.2 ADAPTER_STATUS
- 10.26.3 SIB_ID
- 10.26.4 SIB_POWER
- 10.26.5 SDMMC_CMD_IDX
- 10.26.6 SDMMC_CMD_ARG0
- 10.26.7 SDMMC_CMD_ARG1
- 10.26.8 SDMMC_RESP_IDX
- 10.26.9 SDMMC_RESP_REG0
- 10.26.10 SDMMC_RESP_REG1
- 10.26.11 SDMMC_RESP_REG2
- 10.26.12 SDMMC_RESP_REG3
- 10.26.13 SDMMC_RESP_REG4
- 10.26.14 SDMMC_CMD_RESP_FMT
- 10.26.15 SDMMC_BLOCK_COUNT
- 10.26.16 SDMMC_BLOCK_LEN
- 10.26.17 SDMMC_MODE_CFG
- 10.26.18 SDMMC_DATA_CFG
- 10.26.19 SDMMC_CS
- 10.26.20 SDMMC_STATUS
- 10.26.21 SDMMC_INTR
- 10.26.22 SDMMC_INTR_MASK
- 10.26.23 SDMMC_NCR
- 10.26.24 SDMMC_NCC_NWR
- 10.26.25 SDMMC_NAC
- 10.26.26 SDMMC_HW_CTRL
- 10.26.27 SDMMC_DLL_CTRL
- Revision History