0120 0054 10 K205 Logic Analyzer Service Manual Nov84
0120-0054-10_K205_Logic_Analyzer_Service_Manual_Nov84 0120-0054-10_K205_Logic_Analyzer_Service_Manual_Nov84
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Publ ication Number 0120-0054-10
November 1984
K205 LOGIC ANALYZER
SERVICE MANUAL
Gould Inc., Design & Test Systems Division
4650 Old Ironsides Drive
Santa Clara, CA 95054-1279
Telephone: (408) 988-6800
TWX/TELEX # 910-338-0509
11/84
Copyright© 1984. No part
of this publ ication may be
reproduced without written
permission from Gould Inc.,
Design and Test Systems
Division. Printed in U.S.A.
I
K205 Logic Analyzer
iii
WARNING
This equipment has not been tested to show compl iance with new FCC Rules (47 CFR Part 15) designed
to limit interference to radio and TV reception.
Operation of this equipment in a residential area
is I ikely to cause unacceptable interference to
radio communication requiring the operator to take
whatever steps are necessary to correct the interference.
The fol lowing procedures may help to alleviate the
Radio or Television Interference Problems:
1.
Reorient the antenna of the receiver receiving
the interference.
2.
Relocate the equipment causing the interference with respect to the receiver (move or
change relative pos'ition).
3.
Reconnect the equipment causing the interference into a different outlet so the receiver
and the equipment are connected to different
branch circuits.
4.
Remove the equipment from the power source.
NOTE:
The user may find the fol lowing booklet prepared by
the FCC helpful: "How to Identify and Resolve
Radio-TV Interference Problems". This booklet is
avai lable from the U.S. Printing Office,
Washington, D.C. 20402. Stock No. 004-000-00345-4.
v
PREFACE
This manual contains information for servIcing and maintaining the Gould K205
Logic Analyzer. Procedures are provided for making adjustments and calibrating the control circuits for various functions. These procedures include the
use of diagnostic tests to troubleshoot and isolate a malfunction to a circuit component. Theory of operation is presented for the printed circuit
board functions. Service aids in the form of schematic diagrams, wiring
diagrams, assembly drawings, cable connection diagrams and parts lists are
included for user reference.
The material in this manual reflects the Control Firmware level val id on
October 1, 1984, and is up-to-date at the time of publication, but is subject
to change without notice.
Copies of this publication and other Gould Inc., Design and Test Systems
Division Publ ications may be obtained from the Gould Inc., Design and Test
Systems Division sales office or distributor serving your locality.
RELATED PUBLICATIONS
The fol lowing support documentation may be used in conjunction with this
manual:
K205 User's Manual, Publ ication Number 0120-0014-10 which
describes the capabi lities, functions, and operation of
the K205 Logic Analyzer.
ASSISTANCE
If you require assistance on this product, please cal I Gould Inc., Design and
Test Systems Division Customer Service on the tol I-free, hot-line number
listed below.
Nationwide (800) 538-9320/9321
Cal ifornia (800) 662-9231
vii
WARRANTY
The Gould Inc., Design and Test Systems Division K205 is warranted against defects in materials and workmanship for a period of one year from date of shipment. Any floppy disk or hard disk drives attached to or contained within
this equipment are warranted for 90 days from date of shipment. Gould Inc.,
Design and Test Systems Division wi I I repair or replace products that prove to
be defective during the warranty period.
Warranty service must be performed at a Gould Inc., Design and Test Systems
Division authorized service faci lity. The customer must call Gould's Customer
Service department at the tol I-free numbers listed in the front of this manual
and obtain a Return Authorization number prior to returning the unit for
service. If a unit fai Is within 30 days of shipment date, Gould Inc. wil I pay
al I shipping charges relating to the repair of the unit. Units under warranty, but beyond the 30-day period, should be sent to Gould Inc. prepaid, and
Gould Inc. wi I I return the unit prepaid. The customer must pay al I shipping
charges for units out of warranty.
Misuse of, abuse of, or tampering with this unit will, at the discretion of
Gould Incorporated, cause this warranty to be nul I and void.
ix
CONTENTS
Chapter
Page
GENERAL DESCRIPTION
I NTRODUCT I ON •••••••••••••••••••••••••••••••••••••• 1-1
Overview of K205 Features •••••••••••••••••••• 1-1
Overview of Manual Contents •••••••••••••••••• 1-3
SERVICING PHILOSOPY ••••••••••••••••••••••••••••••• 1-4
Power Up Diagnostic Routines ••••••••••••••••• 1-4
DOS Diagnostic Routines •••••••••••••••••••••• 1-5
MAINTENANCE FEATURES •••••••••••••••••••••••••••••• 1-5
Probe Test ••••••••••••••••••••••••••••••••••• 1-6
Display Cal ibration Pattern •••••••••••••••••• 1-6
SPECIFICATIONS •••••••••••••••••••••••••••••••••••• 1-6
K205 Unit Configurations ••••••••••••••••••••• 1-6
Power Requirements ••••••••••••••••••••••••••• 1-7
Physical Dimensions and Weight ••••••••••••••• 1-7
Environmental Limits ••••••••••••••••••••••••• 1-7
Probes ••••••••••••••••••••••••••••••••••••••• 1-7
Data Inputs •••••••••••••••••••••••••••••••••• 1-8
Clocks ••••••••••••••••••••••••••••••••••••••. 1-8
External Clock Specifications •••••••••••••••• 1-9
Data Set Up and Hold Time •••••••••••••••••••• 1-9
DVM Inputs ••••••••••••••••••••••••••••••••••• 1-9
Signal Outputs ••••••••••••••••••••••••••••••• 1-10
Memor y ••••••••••••••••••••••••••••••••••••••• 1-1 0
Trace Control •••••••••••••••••••••••••••••••• 1-10
Interface •••.•••••.•••••••••••••••••••••••••• 1-10
Audible Tone Signal •••••••••••••••••••••••••• 1-10
2
SYSTEM COMPONENTS AND INTERCONNECTIONS
I NTRODUCT I ON •••••••••••••••••••••••••••••••••••••• 2-1
BOARDS AND COMPONENTS ••••••••••••••••••••••••••••• 2-1
BOARD AND COMPONENT INTERCONNECTIONS •••••••••••••• 2-4
Boards ............•...............•.•.....•.• 2-4
Components •••..•.•••••••••.•••.•.••••••.••••• 2-4
CARD CAGE ARRANGEMENT ••••••••••••••••••••••••••••• 2-6
Data Board Configurations •••••••••••••••••••• 2-6
Board Calibration Controls ••••••••••••••••••• 2-7
SUGGESTED TEST EQUIPMENT •••••••••••••••••••••••••• 2-7
3
CALIBRATION AND POWER UP DIAGNOSTICS
GENERAL ••••••••••••••••••••••••••••••••••••• .••••• • 3-1
POWER UP DIAGNOSTICS •••••••••••••••••••••••••••••• 3-1
Diagnostic Operation ••••••••••••••••••••••••• 3-1
User Interaction ••••••••••••••••••••••••••••• 3-2
Microprocessor RAM Test Description •••••••••• 3-2
Microprocessor ROM Checksum Test Description.3-3
Keyboard Stuck Key Test Description •••••••••• 3-3
Voltage Test Description ••••••••••••••••••••• 3-4
Display Board CMOS RAM Test Description •••••• 3-4
xi
Chapter
3
Page
CALIBRATION AND POWER UP DIAGNOSTICS (Cont'd.)
PROBE TES T ••••••••••••••••••••••••••••••••••••••••• 3-5
Probe Test Pattern Generator •••••••••••••••••• 3-5
Probe Connections •••••.••••••••••••••••••••••• 3-5
Default Setup ••••••••••••••••••••••••••••••••• 3-5
Fixed ECL Threshold Setup ••••••••••••••••••••. 3-6
Record/Review Test Results •••••••••••••••••••• 3-6
oISPLA Y CAL IBRA T ION •••••••••••••••••••••••••••••••• 3-8
Cal ibration Requirements •••••••••••••••••••••• 3-8
Display Adjustment Points ••••••••••••••••••••• 3-8
POWER SUPPLY VOLTAGE MEASUREMENTS •••••••••••••••••• 3-11
REFERENCE/THRESHOLD VOLTAGE AND DVM CALIBRATION •••• 3-13
10V Reference Voltage Adjustment •••••••••••••• 3-13
TTL Threshold Adjustment •••••••••••••••••••••• 3-14
ECL Threshold Adjustment •••••••••••••••••••••• 3-16
Variable A Threshold Adjustment ••••••••••••••• 3-17
Variable B Threshold Adjustment ••••••••••••••• 3-18
DVM Adjustment •••••••••••••••••••••••••••••••• 3-19
INTERNAL CLOCK ADJUSTMENT •••••••••••••••••••••••••• 3-20
4
THEORY OF OPERATION
GENERAL ••••••••••••••••••••••••••••••••••••••••••••• 4-1
OVERVIEW OF K205 UNIT OPERATION ••••••••••••••••••••• 4-1
MPU Board Interaction ••••••••••••••••••••••••• 4-1
Data Board Interaction •••••••••••••••••••••••• 4-3
Clock Board Interaction ••••••••••••••••••••••• 4-3
Control Board Interaction ••••••••••••••••••••• 4-3
Threshold/GPIB/RS-232 Board Intreaction ••••••• 4-3
Data Display Board Interaction •••••••••••••••• 4-4
DATA DISPLAY BOARD OPERATIONS ••••••••••••••••••••••• 4-5
Overview •••••••••••••••••••••••••••••••••••••• 4-5
CRT Control ler •••••••••••••••••••••••••••••••• 4-5
Interrupt Processor ••••••••••••••••••••••••••• 4-8
Keyboard and Front Panel Interface Circuit •••• 4-8
CMOS RAM Save Circuit ••••••••••••••••••••••••• 4-8
Real Time Clock ••••••••••••••••••••••••••••••• 4-9
Audio Error Alarm Circuit ••••••••••••••••••••• 4-9
DOS Interface Circuit ••••••••••••••.•••••••••• 4-9
MPU BOARD OPERATIONS •••••••••••••••••••••••••••••••• 4-10
Overv jew •••••••••••••••••••••••••••••••••••••• 4-10
Microprocessor •••••••••••••••••••••••••••••••• 4-10
Address Registers and Data Transceivers ••••••• 4-12
Memory •••••••••••••••••••••••••••••••••••••••• 4-12
Memory Control ler ••••••••••••••••••••••••••••• 4-12
I/O Decoding •••••••••••••••••••••••••••••••••• 4-13
THRESHOLD/GPIB/RS-232 BOARD OPERATIONS •••••••••••••• 4-14
Overview •••••••••••••••••••••••••••••••••••••• 4-14
Threshold Circuit •••••••••••••••••.••• ~ •••••.• 4-14
DVM Circuit ••••••••••••••••••••••••••••••••••• 4-16
GPIB Interface Circuit ........................ 4-16
RS-232 Interface Circuit •••••••••••••••••••••• 4-16
~~PU
Inter face •••.•.•.•••.••..••.••..•.•.••.•.• 4-16
xi i
Chapter
4
Page
THEORY OF OPERATION (Cont'd.)
CLOCK BOARD OPERATIONS •••••••••••••••••••••••••••• 4-18
Overview ••••••••••••••••••••••••••••••••••••• 4-18
Internal Clocks •••••••••••••••••••••••••••••• 4-18
External Clocks •••••••••••••••••••••••••••••• 4-20
AND Master Clocks •••••••••••••••••••••••••••• 4-20
OR Clock Selection ••••••••••••••••••••••••••• 4-21
Level Memory Circuit ••••••••••••••••••••••••• 4-21
MPU Interface .••••••••••••••••••••••.•••••••• 4-21
DATA BOARD OPERATIONS ••••••••••••••••••••••••••••• 4-23
Ov.erv i ew ••••••••••••••••••••••••••••••••••••• 4-23
Data Input Control ••••••••••••••••••••••••••• 4-23
Operating Modes •••••••••••••••••••••••••••••• 4-25
Sampling Circuit ••••••••••••••••••••••••••••• 4-25
Data Pipeline Control •••••••••••••••••••••••• 4-25
Memory Control ................................ 4-26
MPU Interface •••••••••.••••••••.••••••••••••• 4-26
CONTROL BOARD OPERATIONS •••••••••••••••••••••••••• 4-26
Overview •••••.•••••.••••••••••••••••••••••••• 4-27
Word Recognition Clrcuits •••••••••••••••••••• 4-27
Word Selection Cfrcuits •••••••••••••••••••••• 4-29
Level Switching Circuits ••••••••••••••••••••• 4-30
Delay Counter ••.••••••••••••••••••••••••••••• 4-30
Recording Control Circuits ••••••••••••••••••• 4-30
MPU. Interface •••••••••••••••••••••••••••••••• 4-32
5
DISK DIAGNOSTICS
INTRODUCTION •••••••••••••••••••••••••••••••••••••• 5-1
STARTING UP THE K205 DIAGNOSTICS •••••••••••••••••• 5-3
DIAG MENUS AND DISPLAYS~ •••••••••••••••••••••••••• 5-3
Main Menus ••••••••••••••••••••••••••••••••••• 5-3
System Testing (AI I Active Boards} ••••••••••• 5-4
Single Board Testing ••••••••••••••••• ~ ••••••• 5-5
Conducting al I Subtests or Individual Tests •• 5-5
DIAGNOSTIC PARAMETERS (EDIT KEY} •••••••••••••••••• 5-5
General •••••••••••••••••••••••••••••••••••••• 5-5
Halt on Error ••••••••••••••••••••••••.••••••• 5-6
Loop on Error ••••••••••• ,••••••••••••••••••••• 5-6
Display Error Messages ••••••••••••••••••••••• 5-7
Number of Times to Repeat Test(s} •••••••••••• 5-7
Test Drive A, Test Drive B••••••••••••••••••• 5-8
Test Side 0, Test Side 1 ••••••••••••••••••••• 5-8
Run Operator Action Tests •••••••••••••••••••• 5-8
PASS/ERROR TABULATION (DATA KEY} •••••••••••••••••• 5-9
DIAGNOSTIC RE-INITIALIZATION AND EXIT TO SYSTEM ••• 5-10
General •••••••••••••••••••••••••••••••••••••• 5-10
Exiting the Diagnostic ••••••••••••
5-10
SUMMARY OF DIAGNOSTIC OPERATING SYSTEM KEYS ••••••• 5-11
KEYBOARD/DISPLAY BOARD DIAGNOSTIC TEST •••••••••••• 5-12
DATA BOARD DIAGNOSTIC TEST •••••••••••••••••••••••• 5-23
CONTROL BOARD DIAGNOSTIC TEST ••••••••••••••••••••• 5-51
CLOCK BOARD DIAGNOSTIC TEST ••••••••••••••••••••••• 5-74
THRESHOLD/GPIB/RS-232 BOARD DIAGNOSTIC TEST •••••• ~5-115
STORAGE CONTROLLER BOARD DIAGNOSTIC TEST •••••••••• 5-136
r ••••••••••
xiii
Chapter
6
Page
SCHEMATICS AND DRAWINGS
GENERAL ••••••••••••••••••••••••••••••••••••••••••• 6-1
liST OF DRAWINGS •••••••••••••••••••••••••••••••••• 6-1
Figure
Page
1-1
2-1
2-2
2-3
2-4
3-1
3-2
3-3
·3-4
3-5
3-6
3-7
3-8
4-1
4-2
4-3
4-4
4-5
4-6
4-7
5-1
K205 logic Analyzer, General Arrangement •••••••••••••••• 1-2
K205 Front Panel Arrangement •••••••••••••••••••••••••••• 2-3
K205 Rear Panel Arrangement ••••••••••••••••••••••••••••• 2-3
K205 System Interface of Components to Mother Board ••••• 2-5
K205 Card Cage Arrangement •••••••••••••••••••••••••••••• 2-6
Typical Probe Test Recording Using ECl Threshold •••••••• 3-7
CRT Centering Rlngs ••••••••••••••••••••••••••••••••••••• 3-9
Data Display Board Adjustment Points •••••••••••••••••••• 3-10
CRT Grid Pattern •••••••••••••••••••••••••••••••••••••••• 3-10
Power Supply Voltage Measurements ••••••••••••••••••••••• 3-12
Threshold/GPIB/RS-232 Board Adjustments ••••••••••••••••• 3-14
Test Connections for Threshold Voltage Adjustment ••••••• 3-15
Clock Board, Internal Clock Adjustment •••••••••••••••••• 3-21
K205 System Data Flow and Control Block Diagram ••••••••• 4-2
Data Display Board, Block Dlagram •••••••••••••••••••••• 4-6
MPU Board, Block Diagram •••••••••••••••••••••••••••••••• 4-11
Threshold/GPIB/RS-232 Board, Block Dlagram •••••••••••••• 4-15
Clock Board Block Diagram ••••••••••••••••••••••••••••••• 4-19
Data Board, Block Diagram ••••••••••••••••••••••••••••••• 4-24
Control Board, Block Diagram •••••••••••••••••••••••••••• 4-28
Organization of K205 Diagnostic Software •••••••••••••••• 5-2
xiv
Chapter 1
GENERAL DESCRIPTION
INTRODUCTION
Overview of K205 Features
The Gould Model K205 Logic Analyzer (Figure 1-1) is a precIsIon test instrument that monitors and records logic signals generated by the user's high
speed digital logic based equipment. The K205 accepts 32 standard (or 48
extended) data inputs and 8 standard (or 12 extended) external clock inputs
supplied via probe interface circuits.
The K205 internal control logic performs measurements on the input signals to
accomplish comparison analysis, capture of data samples, correlation of data
characteristics, and recording the results in memory. The measurement operations are menu-driven by resident firm~are which is control led by manipulating
various function keys located on the front panel. The menu displays al low the
user to set up test conditions, capture the analysis results for binary logic
states associated with data-domain analysis, and collect pulse-train waveforms
associated with time-domain analysis.
The menu-driven displays provide fast, convenient access to al I logic analyzer
capabil ities and al low the user to define parameters for threshold logic
levels and timing relationships of sample inputs. Major features of the K205
operation are summarized in the fol lowing list:
•
The K205 equipment functions are menu-driven under the control
of a 16-bit, 8086 microprocessor.
•
The operating system accommodates up to 256K bytes of RAM and
128K bytes of ROM.
•
Three input sections, A, B, and optional C, accept user inputs
via probe circuits. Each section is subdivided into two input
groups. Each input group accepts 8 data and 2 clock signals
to provide a total of 48 data inputs and 12 external clocks.
•
Data inputs are capable of being sampled internally at frequency rates up to 100 MHz. Data may be displayed in 40column Binary format or in Hexadecimal, Octal, ASCI I, EBCDIC,
or user defined format.
•
Three different input modes, Sample, GI itch, and Latch/Demultiplex can be selected in groups of 8 or 16 channels.
•
Independent threshold-level selection is provided for each' logic
probe and associated group of clocks.
•
Up to 16 different state levels for trace control are selected
by using the display menus and front panel keys.
1-1
/
r
DISK OPERAnNG SYSTEM
(DOS OPTION) •
CRT
POWER SWITCH
SECTIONS A AND B PROBE INPUTS
32 DATA INPUTS, 8 CLOCKS
(STANDARD)
SECnON C PROBE INPUTS
ADDITIONAL 16 DATA INPUTS, 4 CLOCKS
(EXTENDED)
Figure 1-1
K205-D Logic Analyzer, General Arrangement
1-2
Overview of K205 Features (cont'd.)
•
The K205 can correctly track a 50MHz state machine, simultaneously
comparing the machine state to four search patterns per level every
20 nanoseconds.
•
The trace is recorded in a 48-bit wide x 515-word length memory.
•
A 24-hour Real-Time clock with battery backup feature al lows the
K205 to log the current time of day and date of each recording.
•
The battery backup feature also drives the CMOS memory which
preserves the current set up for recording parameters if power is
interrupted.
•
A bui It-in Digital Voltmeter (DVM) with input jacks on the
front panel provides a 4-digit readout for user convenience.
•
A self-contained frequency counter provides automatic measurement
of external clock frequency and status.
•
The K205 may be operated as a stand-alone unit or interfaced
with the user's external CPU system or peripherals via an
RS-232-C or IEEE-488 communications link.
•
An optional Disk Operating System (DOS) provides a capability
for storing set up information and data on a floppy disk for
later restoration. The DOS option also provides a capabil ity
for loading and executing disk-based diagnostic routines.
Overview of Manual Contents
The organization and scope of this manual describes the K205 circuit characteristics and component functions as appl icable for servicing and cal ibrating
the unit to maintain its accuracy and availabil ity for use. Seriice aids in
the form of schematic/wiring diagrams, assembly drawings, cable connection
diagrams, and parts I ists are included for reference purposes. The manual
content is arranged as fol lows:
Chapter 1. GENERAL INFORMATION - This chapter presents an overview of the
K205 operating features, organization of manual contents, servIcing philosophy, maintenance features, and equipment specifications.
Chapter 2. SYSTEM COMPONENTS AND INTERCONNECTION - This chapter describes the
interconnection of printed circuit boards, power distribution, external I/O
interface, and special tools and test equipment.
Chapter 3. CALIBRATION AND POWER UP DIAGNOSTICS - This chapter describes the
power up Boot PROM check, Probe Test, cal ibration of the Data Display Board,
Clock Board, and Threshold/GPIB/RS-232 Board, and measurement of the power
supply voltages.
Chapter 4. THEORY OF OPERATION - This chapter presents theory of operation
for each printed circuit board and associated circuitry.
1-3
Overview of Manual Contents (cont'd.)
Chapter 5. DOS DIAGNOSTICS - This chapter presents a description of each
diagnostic module and its associated subtests. Procedures are included for
loading the diagnostic program from the disk, selecting the diagnostic test,
setup of test parameters, executing the test routines, and interpreting the
results.
Chapter 6. SCHEMATIC DIAGRAMS AND PARTS LISTS - This chapter provides reference material such as schematic diagrams, assembly drawings, and parts lists.
SERVICING PHILOSOPHY
Maintenance strategy for the K205 involves the use of diagnostic routines to
isolate a defective circuit function for repair or replacement of boards at
the user's site. The K205 contains firmware diagnostic routines that perform
an operational check of major circuit functions whenever the unit is reset or
powered up from a cold start. Malfunctions detected by the firmware diagnostics may be tested further by using the Disk Operating System (DOS) diagnostic
routines to Isolate the cause of failure. The resident firmware also generates special displays which permit the user to conduct input Probe Tests and
perform CRT al ignment.
The use of any diagnostic for troubleshooting does not eliminate the need for
user interaction to visually inspect cable connections, ensure printed circuit
boards are seated properly, and ensure cal ibration adjustments are made within
prescribed limits. The diagnostic should be rerun after a repair is completed
to verify the problem is resolved before the unit is placed Into operation.
Power Up Diagnostic Routines
The Power Up Diagnostic routines provide a general indication of the system
operational status. Appropriate messages are displayed on the CRT to identify
the type of error condition and the failed function. Since several interacting components may be associated with the resulting malfunction, basic boardswapping techniques and rerunning the diagnostic may be employed to accomplish
the repair. To avoid possible damage to equipment, do not remove or instal I a
printed circuit board while AC or DC power is applied to the unit. The
fol lowing circuit functions are tested by the Power Up Diagnostic routines:
•
MPU Board RAM test
•
MPU Board ROM test
•
Keyboard Matrix test for stuck keys
•
System voltage tolerance test
•
Display Board CMOS RAM Test
•
Threshold/GPIB/RS-232 Board Check
1-4
Power UP Diagnostic Routines
(cont'd)
•
DOS Recognition Check
•
Data Board Recognition Check
•
Clock Board Recognition Check
•
Control Board Recognition Check
DOS Diagnostic Routines
The K205 Disk Operating System (DOS) option provides a capability for loading
diagnostic routines from the disk to further isolate the cause of failure to a
specific circuit or component. The DOS loader firmware, however, must be
functional to effect loading of the diagnostic software from the disk. The
DOS diagnostic provides flexibility for the user to set up test parameters
that halt on error, loop on error, perform repetitive tests for a specified
pass count, etc. The DOS diagnostic is fully described in Chapter 5.
A separate diagnostic routine is provided for each component. The diagnostic
does not assume any part of the system is functional until it has passed its
associated subtests. If a failure is detected, the diagnostic monitor generates an error message identifying the cause of failure. A Self Test menu is
displayed when the DOS diagnostic is invoked. The fol lowing software is
contained on the diagnostic disk:
•
Diagnostic Operating System (K205)
•
Keyboard/Display Diagnostic Module (KDDIAG)
•
Threshold/GPIB/RS-232 Diagnostic Module (THDIAG)
•
Control Board Diagnostic Module (CBDIAG)
•
Clock Board Diagnostic Module (CKDIAG)
•
Data Board Diagnostic Module (DBDIAG)
•
Storage System Controller Diagnostic Module (SCDIAG)
When the user selects a test for execution, the diagnostic test monitor generates detailed sub-menus that direct the user in running the test procedure.
MAINTENANCE FEATURES
In addition to the power up diagnostics firmware, the K205 contains additional
bui It-in features that aid in maintaining the equipment. These features, also
driven by resident firmware, al low the user to test the sample and clock inputs at each probe and to align the CRT display characteristics. An overview
of these features is presented in paragraphs that fol low.
1~
Probe Test
Two Probe Test connectors, located on the front panel, allow the user to
verify that two clock inputs and eight data Inputs supplied from each probe,
operate within acceptable limits. A test pattern generated by the K205
firmware is supplied to the probe under test. Procedures for conducting
the Probe Test are described in Chapter 3.
Display Calibration Pattern
Procedures for calibrating the CRT are described in Chapter 3. The Display
Calibration Pattern, is accessed by depressing and holding the SHIFT key while
powering up the unit. This pattern al lows the user to make adjustments on the
Display printed circuit board for cal ibratlng the fol lowing display characterIstics:
•
Vertical Height
•
Vertical Hold
•
Horizontal Width
•
Horizontal Linearity
•
Vertical Linearity
•
Focus
•
Brightness
SPECIFICATIONS
The fol lowing is a summary of the physical, environmental, and operating characteristics of the K205.
K205 Unit Configurations
Standard
Unit:
Provides inputs for 32 data signals and 8 clocks via
input Sections A and B.
Extended
Unit:
Provides inputs for 48 data signals and 12 clocks via
Input Sections A, B, and C.
Section C Option:
Provides probe Inputs for 16 add-on data signals and 4
additional clocks via input Section C.
DOS Option:
Disk Operating System provides two 5 1/4" floppy disk
drives mounted in an add-on assembly unit which provides
312K bytes of storage per disk.
1-6
Power Requirements
Input Frequency:
Input Voltage:
I nput Power:
50 or 60 Hz
90 to 135 VAC or 180 to 270 VAC
500 Watts without DOS option or 550 Watts with DOS option
Fuses for Rated Voltage:
Voltage Range
Fuse
90 VAC to 135 VAC
3AG, 8 Amp
180 VAC to 270 VAC
3AG, 4 Amp
Physical Dimensions and Weight
Height:
Width:
Depth:
8.6 inches (21.8 Cm) without DOS, 12 inches (30.1 Cm) with DOS
17.5 inches (44.5 Cm)
24.7 inches (62.7 Cm) including handle
Weight:
45 Ibs. (20 Kg) without probes or DOS
55 Ibs. (25 Kg) without probes
Environmental Limits
Ambient Temperatures:
39 to 115 Deg.F (4 to 46 Deg.C) OPERATING
-8 to 117 Deg.F (-20 to 50 Deg.C) STORAGE
Relative Humidity:
20% to 80% OPERATING
1% to 95% STORAGE
Max Wet Bulb:
78 Deg.F (25 Deg.C) OPERATING
No condensation STORAGE
Probes
Loading Characteristics:
Signal Inputs
Input resistance:
Input capacitance:
NOTE:
1 megohm referenced to threshold
< = 6pF « = 15 pF with flying leads)
Input resistance may approach 500K ohms at voltages
exceeding +/- 15 volts from threshold.
Maximum input without damage:
Common mode range:
Ground Input:
+/- 50 volts peak
+/- 0.5 volt maximum between probe and unit probed
Input resistance is 91K ohms referenced to chassis
1-7
Probe Transfer Characteristics:
Bandwidth to 90% volts out:
Minimum swing for output:
Threshold variance:
= >100
MHz
Threshold +/- 0.20 V maximum
+/- 15 Mv maximum, between input signals;
+/- 30 Mv maximum, any two probes
Input compensation:
Thresholds:
Even to 20% overcompensated
Thresholds are independently selectable for each probe and
thec locks as fo I lows:
TTL, +1.4 volts
ECl, -1.3 volts
VAR A and VAR B
NOTE:
Variable thresholds may be set from -9.99 volts to +9.99 volts in
0.01 volt increments. Accuracy of al I threshold voltages is
30Mv.·
Polarity:
+ or - is selectable for each signal
Data Inputs
32 standard (or 48 extended) data inputs configured in two (or three) input
sections, A, Band C. Each section contains two Input groups that accept 16
signals (one group for lower Bits 7-0, the other group for upper Bits F-8).
Input Modes:
Sample Mode
latch and Demu It i P Iex
G I itch Mode
Input Frequency:
t~ode
DC to 100 MHz (data)
DC to 50 MHz (clocks)
Clocks
The 32-standard input configuration provides 6 Sample (edge-sensitive) clocks
and 2 latch Enable (level-sensitive) clocks for a total of 8 external clocks.
The 48-extended input configuration provides 6 Sample (edge-sensitive) clocks
and 6 latch Enable (level-sensitive) clocks for a total of 12 external clocks.
Internal:
Internal clock is selectable from 20 ns (50 MHz) to 100 ms
(10Hz) in decades of time which is divided by units of 1 to 10
(i.e., 100ns, 1 us, 10 us and 1 us, 2 us, 3 us, ••• 10 us). One
internal clock may be programmed per recording.
A 10 ns (100 MHz) clock is available to the Sample/Store sections
in addition to the internal or external clock.
1-8
External:
Twelve external clock inputs which may be combined to form three
Sample clocks, three Latch Enable clocks, and one Master (M) clock.
Sample clock:
One sample clock may be specified for each input section
(A, B, or C) to hold data for the master clock, or move
trace data into memory (effective for internal, external,
and 100 MHz clocks). This clock Is edge sensitive.
Latch clock:
A special case of Sample Mode which is used to temporarily
hold (by latch) the first byte of multiplexed data. When
the latch clock goes false, data is held in the input ~atched
(until the latch clock returns to true). The master clock or
sample/store clock then moves the latched sample (or the present
data, if latch is true) into the pipel ine (effective for
external clocks only). This clock is level sensitive.
M-CLock:
The master clock is used to shift samples into memory and the
trace control logic (effective for internal or external clocks).
This clock is edge sensitive.
External Clock Specification:
Frequency:
DC to 50 MHz
Pulse Width:
8 ns Minimum
Clock Skew:
7 ns Maximum between any two clock combinations
Latch Clocks Setup:
13 ns Minimum before Sample Clocks
Clock Frequency Measurement:
The K205 automatically measures the external
clock frequency from 100 Hz to 50 MHz with
0.1% accuracy
Data Set Up and Hold Time
Data must be present 12 ns maximum before, and stable until, the clock active
edge. Typical setup time is 8 ns.
Data may change zero ns after the clock active edge
Minimum detectable pulse width is one clock period +5 ns
DVM Input
Range:
+/- 20 VDC Maximum
Resolution:
20 mv
Input Impedance:
20k ohms
Accuracy:
+/- 0.5%
1-9
Signal Outputs
VIDEO, BNC connector:
1 Vp-p into 75 ohms composite video output is
compatible with RS-170
CLOCK, BNC connector:
ECl active low corresponds to the internal clock
GET, BNC connector:
Group execute trigger pulse output for the IEEE-488
Command - TTL
TRACE BNC connector:
TTL high output when trace is enabled
Two lEMO power output connectors:
+5V and -5.2V @ 300 mA
Memory
The K205 contains main memory M, storage memory A, and reference memory B.
Memory M is organized as 515 by 36 or 52 bits. Four bits of each word are
used to store the level at which data was recorded. The CPU reads data from M
into A or from A into B. Both A and B are a part of the CPU memory.
The operating system accommodates up to 256k bytes of RAM and 128k bytes of
ROM under the control of the 16-bit, 8086 CPU.
Trace Control
Trace control employs 16 trace levels that are defined by user inputs via the
display menu and keyboard. Four commands are decoded for each of the sixteen
levels. The four commands are TRACE, STOP, JUMP, and ADVANCE. Control begins
at level zero and automatically stops on advance from level F.
A delay counter may be programmed from 1 to 65,535 clocks or events to begin
tracing after the specified condition occurs. The rear panel BNC output for
TRACE is at a TTL level that goes high while the K205 is tracing.
Interface
One RS-232-C Serial I/O Port configured as Data Terminal Equipment (DTE) sixwire system
One Auxi I iary Serial I/O Port for RS-232-C (reserved for K205 options)
One IEEE-488 Bus Interface, Paral lei Port with Talker/listener configuration
selectable by the user via software control
Timer:
A 24-hour, time-of-day clock is backed up by a 2.9 V battery
Back Up Memory:
A 2k x 16 CMOS memory with battery backup saves the setup
of recording parameters if power is interrupted or when the
unit is turned off.
Audible Tone Signal
An audible tone signal (beeper) which indicates keystroke errors can be
enabled or disabled by the user via a menu display.
1-10
Chapter 2
SYSTEM COMPONENTS AND INTERCONNECTIONS
INTRODUCTION
This chapter describes individual printed circuit boards and components that
comprise the K205 Logic Analyzer. Further descriptions are included for the
interconnection of these boards and components along with the equipment that
is necessary for making repairs. Front and rear views of the K205 chassis
are shown in Figures 2-1 and 2-2.
BOARDS AND COMPONENTS
The fol lowing boards and components are used for K205 hardware configurations:
• Keyboard--The keyboard, configured as a scanned matrix, consists of 48
keys, many of which can be shifted to perform a second
function. Because of the shift capabil ity, 20 keys can
perform as a ful I alpha-numeric keyboard •
• Front Connector Panel--The front connector panel contains the fol lowing
components:
-
Six DB-25 female connectors for external data/clock input
Two jacks for DVM (POS and NEG) input
Two card-edge female connectors for PROBE TEST output
Power LED indicator
AC power switch
- The data/clock input connectors that are avai lable for
the standard (32) or extended (48) input configuration
is establ ished by the number of Data Boards instal led.
The unit may be configured with two or three Data Boards
which accommodate 32 or 48 inputs respectively. The
Configuration Display screen indicates the number of
active connectors present for a given instrument.
- I I lumination of the Power LED indicator also indicates
the presence of -5 VDC when AC power is appl ied •
• Display Assembly--The display assembly consists of an 8-inch, P39 CRT
and a CRT deflection yoke with cable harness. The mounting
bracket for the assembly is an integral part of the CRT
glass envelope •
• Rear Connector Panel--The rear connector panel provides external
interface for signal I/O and power via the fol lowing
circuit components:
- Signal output is provided for VIDEO, CLOCK, TRACE,
and GET via four BNC connectors.
2-1
• Rear Connector Panel (Cont'd)
The + 5V and - 5V output is provided by each of two LEMO
connectors
Signal I/O is provided by one IEEE-488 connector
and two RS-232 connectors (one of which is labeled
AUX and is intended for future options).
- Power Interface is provided by the 120/240 VAC line
voltage input socket, the I ine voltage select switch
(for 120/240 VAC), and the power fuse rated at 8 Amp,
3AG for 120 VAC or 4 Amp, 3AG for 240 VAC power input.
• Power Supply--The power supply is a switching type supply which
provides the fol lowing outputs:
+ 5VDC at 11 Amps
- 5.2VDC at 36 Amps
+15VDC at 3.0 Amps
-15VDC at 0.2 Amp
-2VDC at 17 Amps
• Data Board--The Data Board Assembly interfaces the ECL devices of
the probes to the TTL devices of the board. The Data
Board processes 16 inputs. Either two or three Data
Boards wi I I be instal led in a given system configuration
as determined by the 32 or 48 input capabi I ity.
- The Data Board main memory is 515 bits deep by 48 bits
wide and gathers data at 100MHz.
• MPU Board--The
and
The
MPU
MPU Board Assembly contains the 8086 microprocessor
operates as the controller for K205 operations.
operating firmware resides in ROM located on the
Board.
• Control Board--The Control Board Assembly provides the user with
a menu driven display that al lows 16 trace levels to be
programmed by the user. A selection of qual ifiers enables
the user to pick and choose the information that wi I I
be recorded. The Control Board also provides an output
signal to the rear panel TRACE BNC connector.
• Threshold/GPIB/RS-232 Board--The Threshold/GPIB/RS-232 Board Assembly
provides fixed and variable threshold voltages for the
probe pods. In addition, this board provides two RS-232
ports(one of which is intended for future options) and
one IEEE-488 Talker/Listener port. This board also contains
control circuits for DVM input and provides an output
signal to the rear panel GET BNC connector.
2-2
"'IVIOUI
D
'O....T
[J
CLOCKI
,D
U 11I"CI
,. CONTIIOL
...
D
110.'
D
DE'AULT
+
MEM B
DATA
A-,B
z
, "
~D
DD
DLJ
T
I
TIMING
HdCH
GRAPH
COlllfldl
o
B
D
K205 Logic Analyzer
0
-
@
....11.•
@
DVII INPUT
'110" TEIT
Figure 2-1.
TMCE
CLOCK
@) @) @
0\
NIG
0-7 K,J
OFF
AC PO'""
U
:0.
..
GOULD
ON
@
no
MEM A
GET
VIlIO
0\
11"'-'
~,K.7-0
"CTION C
)0
)0
0\
/0
/0
11 •••'-1
J,K,7-0
J,K.7-0
]0
0\
INPUT.
0\
11,1.'-'
0\
IICTION • NIUT'
]0
SECTION A INPUTS
K205 Front Panel Arrangement
HVOC
@@ ©©
@@ @
FUll
0
@
@
@
EJ
LINE
OUTPUTI
VOLTAGE SELECT
@
@
@-@
@
Figure 2-2. K205 Rear Panel Arrangement
2-3
@
• Data Display Board--The Data Display Board Assembly contains the
keyboard scanning circuitry and the horizontal and vertical
and high-voltage circuitry for the CRT. In addition this
board contains the interface for two 5 1/4 -inch floppy
.disk drives and the Keyboard Assembly. This board provides
an output signal to the rear panel VIDEO BNC connector •
• Clock Board--The Clock Board Assembly processes the external clocks
from the probes and provides a range of internal clocks
for the system. This board also provides an output signal
to the rear panel CLOCK BNC connector and test pattern
signal to the two front panel PROBE TEST sockets.
BOARD AND COMPONENT INTERCONNECTIONS
Boards
The K205 printed circuit boards are contained in an eight-slot card cage,
and are interconnected via a mother board. Interconnection of the printed
circuit boards to the front and rear connector panels is provided by flat
cables that mate to connectors located along the upper edges of the board.
The interface of printed circuit boards to the mother board bus and the
probe inputs, as wei I as interaction of boards to each other and the I/O
interface is shown in the block diagram of Figure 2-3.
Components
Because the K205 is a compact unit, the discrete cable harnesses necessary
to connect the power supply to the mother board, and the display assembly
to the Data Display Board are kept quite short. The mother board is connected
to the keyboard by a short flat cable.
The optional Disk Operating System (DOS) Assembly contains the two disk drives
and the associated disk controller interface board. The DOS I/O signal
interface is provided by a flat cable that mates to a connector (P4) located
on the Data Display Board. The power supply harness interfaces to a harness
connector located on the base of the chassis. All interface cables required
for the DOS installation are included with the DOS kit.
2-4
rDATI\-~ARD~ECTIoNcIN~--------------------------l
SECTION A
PROBE
16 DATA/4 CLOCK r---'
A
PROBE INPUTS: • '-----,I
AF - A8, R,S
A7 - AO, J,K
SECTION B l
16 OATA/4 CLOCK
c:::::
I
r--------------------------_________
~----------,I
I DATA BOARD (SECIlON B INPUTS)
II
:I
32(48) DATA INPUTS I
I
Ir--------------------------------------------~-,
DATA BOARD (SECTlON A INPUTS)
I
II
r
I
II
. .~.1
IN~
MEMORY
:
~~~~1~~~,F~~~~~I~I~
L_I I I
CONDmONING
I
'1
M
(MAIN)
I
L-L___ ~_____ --- --------------- - - --- --JrMPU-~-----------,
.1
I+-
ql
PROBE
I
I
r---------CONTROL BOARD -----------,
I-
I
I
I
I
I
BO, J,K
(OPTIONAL)
SECTION C
16 DATA/4 CLOSC..K
PROBE INPUT
CF - C8, R,S
C7 - CO, J,K
SAMPLE
I
PROBE
B
PROBE INPUTS:
BF - BB, R,S
B7 -
:
I
I
I
,_
I
C
~
L _____ .J
~::::;:==='i
"
I
TRACE
CONTROL
I
I
I
I
THRESHOLD
,
N
U1
..
{
REAR
PANEL"
1/0 PORTS
! ·1
IEEE 4B6
:
I
..- - - - - . . ,
_I
1
RS-232
I
r-----..,
L.- - - - -....
- - --1-1
AUX RS-232
GETBNC~
BUS
OUTPUT ~L.._..:;M:;:G:::M;:.T_......
--+-11
1I
I
I
I
...
--•
8 (12)
I
FRONT
PANEL
DVM
INPUT
I'-::~==:'I.I
I
DVM
L.._ _ _ _......
TIMER/CTR
IL _________________ ~
CLOCK
'NI
R&S J&K
(STORAGEI
I
I
REAR!ANEL
TRACE BNC
OUTPUT
~=~===:'I.I
~
A
:
1
GENERATEISELECT ~:=~I;:::=::!:=!==!~
MEMORY
"I
rTHRESHo"LDiGPiaiRs.232---1
BOARD
11'
I
8l1li
aou
I
IL _______ _
________
INTR
.JI
rDAl'A DiSPlAy
--------.,
11IOAIIDr-__......._--,
DELAY
COUNTERI
CONTROL
I
v;::=!=~
~
1\
WORD A, B, C r
.lI DETECT/sELECT
'I
LOGIC
L _______________________ .J
DISPlAY
CRT CTRUIIAIVER
I--i-I~
MOTHER BOARD ADORESS/DATA BUS
rc~K-BOARD----------------
- - - ----1
I
~~~~--~------~~~~~~~--~I SAM~~
PROBES A, BAND C
I
I
CLOCK SELECT
1
ENABLE
1
I
'--~~~-------------------~
REAR PANEL FRONT PANEL
CLOCK BNC PROBE TEST
OUTPUT
OUTPUT
DOS
INTERFACE
!
n
1
1L ________ II
I
__v-_ . .
I--------~
__
...... ,
DISK J
, ----",
/
/
\
"
Fl.OPPV '
......
Figure 2-3. K205 System Interface of Components to Mother Board
REAR PANEL
VIDEO BNC
OUTPUT
CARD CAGE ARRANGEMENT
The K205 card cage arrangement is shown in Figure 2-4. The board ejector
tabs on each printed circuit board are numbered to correspond to the
assigned slot location in the card cage. For the most part, the assigned
board is dedicated to reside in its assigned slot, except where noted below
for the three Data Boards:
Data Board Configurations
Three Data Boards reside in slot locations A2, A3, and A4. The ejector tabs
are not numbered on these boards, because each board is identical and is
interchangeable for these slots. Each slot location, however, is associated
with a specific SECTION INPUT as shown in Figure 2-4.
The K205 instrument configured for standard 32 data inputs (Sections A and B)
uses two Data Boards instal led in slot locations A4 and A3 respectively.
Instruments configured for extended 48 data inputs (Section C) use an
additional Data Board instal led in slot location A2 •
. . . - - - - - - - CLOCK BOARD
~----
THRESHOLD/GPIB/RS·232 BOARD
SECTION C DATA
'----SECTION B DATA
'------SECTION A DATA
Figure 2-4. K205 Card Cage Arrangement
2-6
I
REAR
3 DATA BOARDS
(TYPICAL)
C>
Board Calibration Controls
Three of the printed circuit boards, Data Display, Threshold/GPIB/RS-232,
and Clock contain controls for calibrating various circuit functions.
The location of these controls for a respective board is shown in Figure 2-4.
The procedure for performing the cal ibration adjustments is described in
Chapter 3. The fol lowing circuit functions are adjusted by these controls:
A8
CIRCUIT FUNCTION
ADJUSTMENT
BOARD
NAME
CARD CAGE
LOCATION
Data Display
A6
Threshold/GPIB/RS-232
A5
Clock
R20,
R21,
R29,
R32,
R47,
R56,
L1,
L2,
CRT Vertical Height
CRT Vertical Hold
CRT Focus
CRT Brightness
CRT Vertical Linearity
Audio Alarm Volume
CRT Horizontal Width
CRT Horizontal Linearity
R1, R2, Variable B Threshold
R3, R5, DVM Voltage
R6, R9, Variable A Threshold
R7, ECL Threshold
R8, TTL Threshold
R44, Reference Voltage (+ 10V)
R19, C8, Internal Clock Frequency
SUGGESTED TEST EQUIPMENT
The fol lowing is a list of the suggested test equipment for servicing and
troubleshooting the K205 Logic Analyzer:
ITEM
DESCRIPTION
Extender Board
Gould Part Number 0117-0195-01
Digital Multi-meter
4 1/2 Digits, DC Accuracy of +/- (0.03%
of reading + 2 digits)
Frequency Counter
Capable of 0.01% accuracy on ECL at 100MHz
Osci I loscope
350 MHz band width, Horizontal Resolution
to 1 ns/DIV
Logic Analyzer
Any current production model, Gould
Logic Analyzer
20-Pin, 0.3" IC Clip
Standard
3 Mini Clips/Grabbers
Standard
4.7K-Ohm, 1/4 W, 5% Resister
Standard
2-7
Chapter 3
CALIBRATION AND POWER UP DIAGNOSTICS
GENERAL
This chapter describes the K205 Power Up diagnostic test routines and procedures for cal ibrating system components. This information is organized as
fol lows:
•
•
•
•
•
•
•
Power Up Diagnostics
Probe Test
Display Calibration
Power Supply Voltage Measurements
Threshold Voltage Cal ibration
DVM Circuit Calibration
Internal Clock Adjustment
POWER UP DIAGNOSTICS
The Power Up Diagnostic test is executed by the K205 to verify the operational
readiness of hardware components whenever the instrument Is powered up from a
cold start or restarted. The power up ~iagnostic is implemented by a resident
program in the EPROM firmware located on the MPU printed circuit board.
Diagnostic Operation
As soon as the AC POWER switch is turned ON, the K205 wil I beep and begin executing the diagnostic test routines. As each test is completed, the next test
is automatically run. When al I tests are successfully completed, the Configuration screen displays the current hardware configuration and the instrument
can accept user inputs.
The power up diagnostic is also initiated when the SHIFT and DEFAULT keys are
depressed to reset system operations. The power up diagnostic runs for
approximately ten seconds to check for the presence of certain components and
perform a series of tests. The fol lowing tests and checks are performed by
the power up diagnostics:
Microprocessor RAM Test
Microprocessor ROM Checksum Test
Keyboard Stuck Key Test
Voltage-Test
Display Board CMOS RAM Test
Threshold/GPIB/RS-232 Board Check
DOS Recognition Check
Data Board Recognition Check
Clock Board Recognition Check
Control Board Recognition Check
3-1
User Interaction
If an error is detected in any of the tests, the name of the failed test is
displayed and further testing is halted. To run the remaining power up tests,
or to attempt operation of the instrument despite the error condition, depress
the NEXT key to resume testing, or depress the PREVIOUS key to repeat the test.
After the last test is executed, the Configuration screen is displayed. At
this point, since an error has been detected, the appropriate disk-based
diagnostic test may be executed to further isolate the cause of the error.
As each power up diagnostic test is executed, the name of the test is displayed on the CRT. If the test is run successfully, the word PASSED is
printed after the test name. The first failure encountered in a test is
indicated by the word FAILED, which is printed after the test name. A testresults header is then printed on the next I ine and the results of the test
are printed on subsequent I ines. Any additional failures associated with the
specified test name causes the results to be printed on successive lines.
A detailed description of the various diagnostic tests is given in subsequent
paragraphs.
Microprocessor RAM Test Description
The Microprocessor RAM Test is executed by writing and reading bits in a test
pattern as fol lows:
1.
Write 0000 to address locations OOOO-FFFF.
2.
Read 0000 from address locations FFFF-OOOO
and write FFFF at each location.
3.
Read FFFF from address locations OOOO-FFFF
and write 0000 at each location.
4.
Read 0000 from address locations OOOO-FFFF
and write FFFF at each location.
5.
Read FFFF from address location FFFF-OOOO
and write 0000 at each location.
The above test is repeated, changing the segment registers so that RAM
address locations 0:0000 to 3000:FFFF are al I tested. If al I test patterns are
read back successfully, the fol lowing information is displayed:
MICROPROCESSOR RAM TEST -
PASSED
If any bits fail, the fol lowing information is displayed in graphic form:
3-2
t~ ICROP RaCE SSOR
RAM TE ST -
FAILED
MPU MEMORY FAILURE
MAP OF RAMS ON MPU BOARD (G
COL-->
ROW
I
A
B
C
'"
0
E
F
G
H
3
4
5
6
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
X
G
G
G
X
G
G
G
= GOOD, X = BAD)
Please press NEXT to continue.
Where:
PREV to repeat.
COL and ROW positions correspond to
respective RAM socket locations on
MPU board.
Microprocessor ROM Checksum Test Description
The ROM Checksum Test computes 16-bit checksums for each of the ROMs which are
numbered from 1 to 16. The computed checksum values are then compared with
the expected values which are stored in the top of ROMs 15 and 16.
If the values match, the test is successful and the system proceeds to the
next test.
If the values do not match, the error display indicates the ROM number, the expected checksum value, and the actual checksum value as shown below. Note
that a missing ROM generates the fol lowing display:
ROM CHECKSUM TEST
FAILED
ROM
NUMBER
EXPECTED
CHECKSUM
ACTUAL
CHECKSUM
2
463B
ALL "FF"
Keyboard Stuck Key Test Description
This test performs a check of the keyboard matrix for stuck keys (i.e., where
the key contacts do not make and break properly).
If one or more keys are stuck, the affected key(s) is displayed below the test
failed message in a matrix that is continuously updated.
If al I keys were stuck, the fol lowing information is displayed on the CRT
screen:
3-3
KEYBOARD STUCK KEY TEST NE 1\
PR <
FO MA
CL DA
TR TI
AM GR
When al I keys are unstuck,
to the next test.
FA ILED
> CN SH I0 ED AR
v RF HL SP IN ST
MB
AB
SE
CM
C
8
4
0
D E
A
5 6
1 2
9
F F1
B F2
7 F3
3 F4
the test is successful and the system proceeds
Voltage Test Description
The fol lowing voltages are checked by the power up diagnostic:
+15.00 VDC
-15.00 VDC
-10.00 VDC
+ 5.04 VDC
- 5.28 VDC
- 2.08 VDC
V BATT
Tolerance tor +15V test has been arbitrarily set to +0.5 VDC. The tolerances
for remaining voltages have been set to +/- 10%. The testing sequence
is conducted as fol lows:
1.
The +15V test is repeated up to 100 times. If the
voltage returned is not within the tolerance I imit on or before
test 100 occurs, the test has fai led.
2.
If the +15V test is successful, remaining voltages are
tested. A failed condition occurs if any of the voltages are
not within acceptable limits.
3.
For each voltage that fai Is, the fol lowing information is displayed on the CRT: name of voltage being tested, the minimum
voltage limit, the maximum voltage I imit, and measured voltage
value(average and peak-to-peak) which was read.
Display Board CMOS RAM Test Description
The CMOS RAM is backed up by batteries to store setup parameters for recording
information. This test routine causes the stored data to be compared with a
checksum value which is also stored in the CMOS RAM. A fai lure causes an
error message, as fol lows, to be displayed:
CMOS RAM TEST
FAILED
An error condition generally indicates the instrument wi I I not properly restore the recording setup parameters which were previously stored, nor correctly save new parameters.
3-4
The presence of an error condition, however, does not always indicate a component has fai led. The source of failure could be an intermittent, soft
error. Depressing the NEXT key resumes execution of the diagnostic. If the
original error was not caused by a component failure, the CMOS RAM TEST
ERROR should not appear on the next power up and the CMOS memory should
operate correctly.
PROBE TEST
Two front panel connectors, labeled PROBE TEST, are used to quickly check the
probe circuitry to verify it is operational. The test is performed on eight
sample data input signals of each probe.
NOTE:
The clocks are not checked by this test.
Probe Test Pattern Generator
The Probe Test Pattern Generator is always enabled. The pattern generator
circuits generate an output signal to the PROBE TEST sockets consisting of a
known ring-counter loop and clocking sequence. The pattern generator outputs two clock signals and eight data signals for each PROBE TEST socket.
These signals are suppl ied as input to the probe tip.
The clock and data signals output from the PROBE TEST sockets have a voltage
swing from 0 to -5 volts.
Probe Connections
The arrangement of two PROBE TEST sockets al lows the low order (bits 7-0)
probe and high order (bits F-8) probe of each input section to be tested
concurrently. In order to avoid the possibility of extraneous noise pulses at
the other input sections, it is recommended that the probe cables also be
connected to these input sections whi Ie conducting the probe test. Use the
fol lowing procedure to connect the probe cables:
1.
Connect the low order bit probe cable to lower front panel
socket labeled SECTION A INPUTS (J, K, 7-0).
2.
Connect the high order bit probe cable to upper front panel
socket labeled SECTION A INPUTS (R, S, F-8).
3.
Repeat Steps 1 and 2 to connect probe cables to front panel
sockets at Section Inputs Band C.
4.
Plug the lower order bit probe tip of SECTION A INPUT cable into
the lower PROBE TEST socket. Ensure label faces upward.
5.
Plug the high order bit probe tip of SECTION A INPUT cable into
the upper PROBE TEST socket. Ensure label faces upward.
Default Setup
The K205 contains CMOS memory which is backed up by battery to retain the previous set-up parameters. Whenever the unit is powered up from a cold start,
the previous set-up parameters are restored. It is, therefore, necessary to
initialize al I set-up parameters to their default value as fol lows:
3-5
1.
Depress the SHIFT and ARM MODE/DEFAULT keys to select the Configuration Screen.
2.
Depress Function key, Fl, to select the Default Setup
Parameters.
3.
Observe the fol lowing message is displayed at the top of the
screen:
Default Setup M and Display values locked in
Fixed ECl Threshold Setup
1.
Depress the FORMAT key; observe the Format Display indicates
Data Inputs for AF through AO and Threshold at TTL level.
2.
Change the threshold for inputs AF through AO to ECl by moving
the bl inking cursor to the AF-A8 I ine of the Data Inputs display
and change TTL to ECl as fol lows:
a)
Depress Function key, Fl, to select top of threshold.
b)
Depress FIELD down-arrow key four times to move cursor downward
to AF-A8 line.
c)
Depress alphanumeric key, 1, two times to change entries
to ECl level at lines AF-A8 and A7-AO.
Record/Review Test Results
1.
Depress the ARM key to initiate a recording.
2.
Observe the machine status message which is located in the lower
right area of the screen. This status indicates a recording has
occurred with,the fol lowing condition:
READY
BUSY
EOR
- Ready for an ARM signal
- Setup internally for a recording
- End of recording activity
NOTE: The actual recording occurs quickly; if necessary, depress the
ARM key again to view the display. Depress the Fl key to scrol I through
the input displays until the desired input signals are displayed on the
screen.
3.
Depress the TIMING key and observe the display pattern. A
staircase pattern of pulses (shown in Figure 3-1) should appear
on the screen. This pattern may begin at any point on the
screen as determined by the Default Setup. Memory is fil led
with samples starting at location 0 in the data stream.
3-6
4.
Use the Control and Reference cursors to measure the characteristic total trace time of 10 microseconds and pulse width of
0.9 microsecond. The presence of these conditions indicates the
probes under test are functioning properly to accept inputs for
recording.
Verify a pulse is present for each channel. If a channel does not
contain a pulse, reverse the upper and lower probes and repeat the
test. A malfunction of the generator can be isolated by swapping the
probes. A malfunction of the probe can be isolated by swapping the
probe at the input connector. If the fai lure is sti I I present, the
problem is associated with internal cabl ing or the Data Boards.
5.
Repeat the Probe Test for Section Band C Inputs, and verify these
probes are functioning properly to accept inputs for recording.
T I t-11 NG
(A
::0
10/05/84
10:45:36
PAGE
Figure 3-1.
=
Typical Probe Test Recording Using ECl Threshold
3-7
8
DISPLAY CALIBRATION
The Display Board contains circuitry for generating signals that are used for
driving the CRT, reading front panel Keyboard, control I ing priorities for
interrupt levels, control I ing the Real Time Clock and driving the Audio Error
Alarm.
*** ******* **** * * ** * ***
*
*
*
*
*
WARNING
*
*
*
*
*
*
** * ** ** ********** * ****
Hazardous voltages dangerous to life
are present on the Data Display board
and CRT. Avoid body contact in these
areas which could result in injury.
Calibration Requirements
A display cal ibration pattern is provided by the K205 firmware.
This pattern
is a.ccessed by depress i ng and ho I ding the SH IFT key wh i Ie power i ng up the
unit. Raster adjustments are made with the Data Display board fully Instal led
in the chassis. The technician is cautioned that the cal ibration controls are
located near an area where high-voltages are generated for operation of the
CRT.
Body contact with the printed ciruit board and flyback transformer
should be avoided.
The technician is further cautioned to use nonmetal I ic
tools when making raster adjustments.
Display Adjustment Points
Prior to attempting any height, width or I inearity adjustments, the technician
must first ensure the cal ibration pattern is centered.
Centering is
accompl ishyed using the intersection point of the "X" traces as a reference
point and locating the point to the center of the screen by moving and
centering rings on the CRT yoke (See Figure 3-2).
Because al I raster adjustments are interacting, recentering the cal ibration
pattern might be required as height, width and I inearity adjustments are made.
Refer to Figure 3-3 for the location of adjustment controls for VOLUME (R56),
VERTICAL (R20, R21 and R47), HORIZONTAL (ll and l2), FOCUS (R29), and
BRIGHTNESS (R32).
Adjustment of the Display board is to be accomplished as fol lows:
1.
Turn power on and verify unit passes the power-up diagnostic test by
displaying the Configuration Screen.
2.
During power-up test, adjust VOLUME (R56) for good sound. Depressing an
i I legal Key with the Error Beep on causes a brief tone to be generated.
The Error Beep is turned on and off by accessing the Date screen and
depressing the FIELD right arrow and NEXT keys to select the Beep
parameter.
3-8
3.
Adjust VERTICAL HOLD (R21) unti I picture locks in on screen.
NOTE: In further screen adjustments, keep 0.25 inch
margins on al I four borders.
4.
Adjust VERTICAL HEIGHT (R20) observing that change occurs in the height.
Set for the best picture.
5.
Adjust VERTICAL LINEARITY (R47) observing that change occurs in vertical
I inearity. Set for the be~t picture.
6.
Adjust FOCUS (R29) observing that change occurs in focus. Set for
best picture.
7.
Adjust BRIGHTNESS (R32) observing that change occurs in brightness.
Set for good picture brightness.
8.
Adjust HORIZONTAL WIDTH (Ll) observing change occurs in width.
Set for good picture.
9.
Adjust HORIZONTAL LINEARITY (L2) observing change occurs in
horizontal linearity. Set for good picture. Turn power off.
10.
Hold the SHIFT key down and turn power on. A grid pattern
will appear on the CRT as shown In Figure 3-4.
o~============~=~==============~
,/
,/
,/
/
/
o
o
REAR YEW
Figure 3-2. CRT Centering Rings
3-9
VERTICAL VER11::AL HORIZONTAL
HEIOHT
HOLD
WIDTH
9-
R58
~
R20
Lc::J
c::::>
o
Figure 3-3. Data Display Board Adjustment Points
'\
,
/
;
I
i\.
'\
/
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!
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j /'
F
roo..
7
'\
/
"\
:'\
,,
:
:
V'
/ K
t~,
//
V
./
/
~
r'...
/i
/
V'
'"
:
:
Press NEXT to con1:inue
Figure 3-4. CRT Grid Pattern
3-10
~
'\
~
11.
Verify good linearity and picture size is indicated by the grid
pattern. Repeat adjustments if necessary to obtain a uniform
presentation in the dis~lay.
12.
Verify the VIDEO output signal at rear panel BNC connector
is present as tol lows:
a.
Connect a 50-ohm coaxial cable from the Composite
Video Out BNC connector of K205 to one input of scope.
b.
Use 1-Megohm input scope termination.
c.
Set scope for 1 volt/division and trace centerllne(ground).
d.
Verify approximately 1.6V pp pulse occurs every 64 usec.
POWER SUPPLY VOLTAGE MEASUREMENTS
The K205 Power Supply does not contain adjustments accessible to the user.
A voltage measurement check is conducted to determine if the power supply
is functioning properly. If the measured voltages are not within the specified
limits, the power supply must be replaced.
NOTE: The power supply must be al lowed to warm up
for at least 10 minutes prior to checking the
supply voltages.
Voltages are measured at the power supply terminal board locations shown In
Figure 3-5. The measurement is taken between the specified voltage signal
and its respective return. The measured voltages must be within the fol lowing
ranges:
RANGE
NOMINAL VOLTAGE
MAXIMUM
MINIMUM
+15V
+14.4
to
+15.6V
+ 5V
+ 4.8
to
+ 5.2V
- 2V
- 2.2
to
- 2.0V
- 5.3V
- 5.5
to
- 5.1V
-15V
-15.6
to
-14.4V
3-11
RESET
+5
2
+5 RTN
3
+15 RTN
4
+15
5
-15
6
-15 RTN
7
-2
8
-2
9
-2 RTN
10
-2RTN
11
-5.2
12
-5.2
13
-5.2
14
-5.2 RTN
15
-5.2 RTN
16
-5.2 RTN
17
POWER
SUPPLY
REAR
0'
Figure 3-5. Power Supply Voltage Measurements
3-12
THRESHOLD VOLTAGE AND DVM CALIBRATION
The fol lowing adjustments are made on the Threshold/GPIB/RS-232 Board:
• 10V Reference Voltage Adjustment
• TTL Threshold Adjustment
• ECl Threshold Adjustment
• Variable A Threshold Adjustment
• Variable B Threshold Adjustment
• DVM Adjustment
The location of potentiometers to accomplish the various adjustments are shown
in Figure 3-6. The following tools and test equipment are required to make
these adjustments:
• Extender Board:
Gould Part Number 0117-0195-01
• Digital Multimeter:
4 1/2 Digits, DC accuracy of +/- (0.03% of
Reading plus 2 Digits)
.4.7K-Ohm, 1/4 W, 5% Resistor:
Standard
• External voltage source of +/- 20.000 VDC +/- 3Mv
Use the fol lowing procedures to make the adjustments:
NOTE: To ensure that proper values are set for Threshold adjustments,
the user should turn the power off, then on to obtain the Configuration
screen. Depressing the Fl key moves the cursor to the top Threshold location
on the screen.
10V Reference Voltage Adjustment
1.
Turn power off, remove the Threshold/GPIB/RS-232 Board from card cage
and install on an extender board.
2.
Turn power on and verify unit passes power-up diagnostic test by
displaying the configuration screen.
3.
Connect external DVM reference (-) to the board A GND test point, and
connect the DVM (+) input to the right side of resistor R38. (These
connection points are shown in Figure 3-6.)
4.
Adjust R44 for a DVM reading of +10.00 +/- O.OlV.
3-13
REFERENCE VOLTAGE
MEASUREMENT POINT
REFERENCE VOLTAGE
GROUND POINT
THRESHOLDI GP1 BI RS-232 BOARD
D
o o
D D
o
R38
VAR A OFFSET ADJ
TILADJ
ECLADJ
VAR A GAIN ADJ
DVM GAINADJ
DVM OFFSET ADJ
VAR B OFFSET ADJ
VAR B GAIN ADJ
10V REF ADJ
Figure 3-6.
Threshold/GPIB/RS-232 Board Adjustments
TIL Threshol d Adjustmen,t
Remove al I input cables from the unit. This procedure employs a 4.7K-Ohm
resistor which serves as a load for adjustment of threshold voltages. All
voltages wil I be measured accross the resistor. The TTL adjustment procedure
also verifies that no shorts are present between High and Low inputs, and
between Data and Clock inputs. The TTL adjustment is performed on each front
panel input connector as fol lows:
1.
Configure the K205 unit with three Data Boards to provide 16 inputs
at each SECTION Input (A, B, and C).
2.
Install the 4.7K-Ohm resistor between sockets 2 (ground) and 14 (Clock
Threshold input) at SECTION A (bits 7-0). Connect the DVM positive
(+) lead to socket 2 and DVM negative (-) lead to socket 14 so that
the voltage measurement is taken across the resistor as shown in
Figure 3-7.
3-14
+
.') 0
o
DVM
SECTION INPUT CONNECTOR
Figure 3-7.
Test Connections tor Threshold Voltage Adjustment
3.
Depress the FORMAT Key verity that al I Thresholds are set to TTL.
4.
Depress the ARM key on keyboard
5.
Adjust TTL THRESHOLD (R8) for a DVM reading of +1.400 +/- 5Mv.
6.
Relocate the resistor to SECTION A Inputs (bits F-8) connector
and verify the TTL Threshold of +1.400 +/- 25Mv is present.
7.
Check the TTL level of other inputs by moving the load resistor
to input connectors at SECTIONs Band C. Verify the TTL Threshold
of +1.400 +/- 25Mv is present at sockets 2 and 14 of each low-byte
(bits 7-0) and high-byte (bits F-B) connector.
B.
Instal I the 4.7K-Ohm resistor between sockets 2 (ground) and 15 (Data
Threshold), a~d repeat steps 3 through 7.
9.
Ensure no shorts are present between low and High inputs, as weI I as
between Data and Clock Inputs by performing the fol lowing test:
a.
Depress FORMAT key to select Format M screen, then depress
F1 key to move cursor to top Threshold location. Depress
quick key 1, to change TTL level to ECl.
b.
Move cursor down by depressing FIELD down-arrow key one time,
and depress quick key 1 to change TTL level to ECl.
c.
Repeat substep b, and depress ARM key.
d.
Install the 4.7K-Ohm
14 (Clock Threshold)
Connect externa I DV~~
(-) I ead to pin 15.
+/- 25Mv is present.
resistor between sockets
of SECTION C upper INPUT
positive (+) lead to pin
Verify the ECl Threshold
3-15
2 (ground) and
Connector.
2 and negative
of -1.300V
e.
Instal I the 4.7K-Ohm resistor between pin 2 and 14 of the
same connector~ Connect DVM leads and verify the TTL
Threshold of +1.400V +/- 25Mv is present. If the DVM reads
ECL Threshold instead of TTL Threshold, this indicates a short
is present between Data Input and Clock Input lines.
f.
I nsta II the res i stor between pin 2 (ground) and 15 (Data
Threshold) of SECTION C lower Input connector. Connect
DVM leads and verify TTL Threshold of +1.400V +/- 25Mv is
present. If the DVM reads ECL Threshold instead of TTL
Threshold, this indicates a short is present between High
and Low Data Input lines.
g.
Repeat substep e for this connector.
h. Repeat substeps d through f for SECTION B and SECTION A inputs.
EeL Threshold Adjustment
The ECL Threshold adjustment is performed for each front panel Input connector
as follows:
1.
Instal I the 4.7K-Ohm resistor at sockets 2 and 14 of SECTION A input
connector(bits 7-0). Connect the DVM positive(+) lead to socket 2
and the DVM negative(-) lead to socket 14 so that the measurement is
taken across the resistor.
2.
Make the fol lowing keyboard entries to change al I thresholds from
TTL to ECL:
a.
Depress FORMAT key to access the Format screen.
b.
Depress the FUNCTION key, F1, to move cursor to the Top
Threshold location.
c.
Depress and hold quick Key 1 untl I ECL is selected for al I
threshold voltages.
d.
Depress the ARM key to change DVM reading to ECL level.
ECL levels should now be selected for al I inputs.
3.
Adjust ECL THRESHOLD (R7) for DVM reading of +1.300 +/- 5Mv.
4.
Relocate the resistor to SECTION A (bits F-8) input connector and
verify the ECL Threshold of +1.300 +/- 25Mv is present.
5.
Check the ECL level
to input connectors
Threshold of +1.300
low byte (bits 7-0)
of other inputs by moving the load resistor
at SECTION B and SECTION C. Verify the ECL
+/- 25Mv is present at sockets 2 and 14 of each
and high byte (bits F-8) input connector.
3-16
Variable A Threshold Adjustment
The Variable A Threshold adjustment is performed for each front panel input
connector as fol lows:
1.
Instal I the 4.7K-Ohm resistor at sockets 2 and 14 of the SECTION
A Input connector (bits 7-0). Connect the DVM positive (+) lead
to socket 2 and connect the DVM negative (-) lead to socket 14 so
that the measurement is taken across the resistor as shown in
Figure 3-7.
2.
Make the fol lowing keyboard entries:
a.
Depress FORMAT key to access the Format screen.
b.
Depress the FUNCTION key, F1, to move cursor to top
threshold location.
c.
Depress and hold quick Key 2 unti I VARA is selected for al I
threshold voltages.
d.
Depress the ARM key to change DVM reading to VARA level.
All inputs should now indicate VARA = 9.99V.
3.
Adjust VARA GAIN (R6) for DVM reading of 9.990 +/- 5Mv.
4.
Make the fol lowing keyboard entries:
a.
Depress FIELD right-arrow key to move cursor right to
position 9.99.
b.
Depress and hold Quick Key 0 until 9.99 inputs are set
at 0.00
c.
Depress the ARM key.
VARA = O.OOV.
All inputs should now indicate
5.
Adjust VARA OFFSET (R9) for DVM reading of 0.000 +/- 5Mv.
6.
Make the fol lowing keyboard entries:
a.
Depress and hold Quick Key 9 until 0.00 inputs are set
at 9.99.
b.
Depress ARM key.
7.
Adjust VARA GAIN (R6) for DVM reading of +9.990 +/- 5Mv.
8.
Make the fol lowing keyboard entries:
a.
Depress FIELD left-arrow key to move cursor left to the
+ position.
b.
Depress the NEXT key to change positive (+) to negative (-)
value.
c.
Depress the ARM key.
3-17
9.
10.
Note the value of DVM reading and adjust VARA GAIN
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1
0
0
'TmG"'
I
I
OPTIONAL DOSI
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0
0
al
KEYBOARD
INTERFACE
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BUS
READ/WRITE
CONTROL
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0274-+-1
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AD DR COUNTER
,.,:.,:.,.
VIDEO CONTROL
I
DATA BUS
INTERFACE
74LS245
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ERROR
ALARM
J
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0
60
en
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0
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0
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MPU ADDRESS/DATA BUS
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Figure 4-2.
CMOS
ADDRESS
GENERATION
0
PRESET
ADDR
COUNTER
--
l!---
r--
CMOS BUS
INTERFACE
74LS245
BDO-15
ENABLE
I
K205 Data Display Board Block Diagram
6
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en
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al
en
en
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II:
0
0
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al
Horizontal Deflection and High Voltage: The horizontal drive signal from the
CRT controller synchronizes the horizontal scanning with the retrace blanking by
control ling the horizontal drive transistor, Q5 (sheet 1 of schematic diagrams).
The horizontal drive transistor (Q5) performs two functions; it provides energy
to the flyback transformer and it draws current from the horizontal deflection
coi I to generate the scan from left to right. The Flyback Transformer, T2
provides the energy for rapid retrace from right to left and it serves as an AC
to DC converter for generating the operating voltages for the CRT. The
fol lowing voltages are supplied to the CRT:
+10KV
+200V
+30V
-40V
CRT Anode
Focus
Cathode
CRT Grid
The horizontal deflection and high voltage circuit al lows adjustment of the
Focus (R29) and Brightness (R32) which are located near the top of the board.
The Horizontal Width adjustment (ll) and linearity adjustment (l2) are also
present.
Vertical Deflection: The vertical processor (sheet 2 of schematic diagrams)
generates and synchronizes the vertical scanning. The vertical processor drives
the vertical deflection coil directly, and senses current through the coil via a
sense resistor. The TDA 1270 processor (11B) contains an osci I lator that is
synchronized to the vertical sync pulse, an adjustable constant current source
ramp generator, an emitter fol lower, and a power amp I ifier to drive the coi I.
The vertical processor circuitry al lows adjustment of Vertical Hold (R21)
Vertical Height (R20) and Vertical Linearity (R47).
Video: The CRT brightness is control led by combining the digital data with the
horizontal and vertical blanking signals and switching the cathode voltage
between zero volts (white) and +30V (black). The video is modulated by an 8MHz
clock signal to provide a sharper display presentation. A composite video
signal is also generated at the rear panel BNC connector for use with another
video monitor.
Video Operation: Transistor Q3 operates as the video amp I ifier and appl ies the
video signal to the cathode of the CRT. R28 is the load resistor connecting Q3
to the 30 VDC supply. The 30 VDC supply is composed of CR6 and C38, and the -40
VDC grid bias supply for the CRT consists of CR3 and C35. CR4 and C37 comprise
the 200 VDC focus electrode supply.
The source voltage for these supplies is the high-voltage transformer, T2. Note
also that T2 supplies the 10 KV for the second-anode of the CRT. The rectifier
for the high-voltage is an integral part of the second-anode lead, and the
filter capacitor for the high-voltage is the 600pF capacitance of the CRT
aquedag coatings.
Transformer T1 and transistors Q4 and Q5 drive transformer T2: When Q5 is
conducting, energy is stored in the primary of T2. When Q5 is switched off, the
energy stored in the T2 primary is transferred to the secondary.
4-7
When Q5 switches off, the voltage at i~s col lector rises to approximately 120
VDC and is impressed upon the horizontal deflection coi I via L1 and L2. This
voltage causes a current to flow in the deflection coi I which In turn causes the
electron to deflect to the left side of the CRT. The positive current flow
decays in a I inear manner, being zero at center screen. Because of the resonant
circuit, C53 and the deflection coi I, the current increases in the negative
direction for the right side of the screen. At center screen Q5 again switches
on and remains on unti I the beam is deflected to the right side of the screen.
At this time, Q5 again switches off, and the process begins again.
Vertical deflection is accomplished using a TDA1270 integrated circuit, U11B.
This IC contains an osci I lator, a preamp and a power amp. The osci I lator
frequency is controlled by R21, R22 and C49. The waveform is shaped by R20,
R37, R42, R44, R47, C45 and C46. The waveform is ampl ified by the preamp and
power ampl ifier and impressed upon the vertical deflection coi I via C51. The
current is sensed across R45 and returned to the preamp via feedback resistor
R46.
Interrupt Processor
The Interrupt Processor circuit (sheet 4 of schematic diagrams) accommodates up
to eight levels of interrupts (INTO - INT7) using a 8259A Interrupt Processor
chip (2E). Seven levels of interrupts are used for K205 appl ication with the
fol lowing assignments:
INTERRUPT LEVEL
ASSIGNMENT
INT7
Floppy Disk Controller
INT6
1 Second (Time of Day Clock)
INT5
(Not used)
INT4
Timer #0
INT3
Auxiliary, RS-232 (USART#2) (RXRDY+TXRDY)
INT2
RS-232 (USART #1) (RXRDY+TXRDY)
INTl
GPIB
INTO
50Hz (CRT Interrupt)
Keyboard and Front Panel Interface Circuit
The Keyboard and Front Panel Interface .
I
MPU TIMING AND
RAM CONTROL
8086 CPU
(c::::::
CONTROL SIGNALS
FROM DATA DISPLAY
BOARD
MPU
CONTROL
SIGNAL
INTERFACE
<==::
DATA BUS
INTERFACE
I---
f-;n
-'
«
z
CAD-15
I .
ADDRESS
BUS
INTERFACE
~
RAM ADDRESS
INTERFACE
CRT SERIAL
DATA
RAM
MEMORY
256K
DATA BUS
INTERFACE
~
TO MOTHERBOARD
ADDRESS/DATA BUS
CRT ADDRESS
GENERATION
AD-15
CJ
~
iii
ADDRESS
BUS
INTERFACE
ROM
MEMORY
128K
-'
ea:
«
l«
0
iii
ffLn
I-
z
e l.-----o
0
:=I
ROM CONTROL
AND TIMING
11.
::;:
a:~
06
00
«~
DATA OUT BUS
:=IU)
11.:=1
::;:m
Figure 4-3. MPU Board Block Diagram
-
8
TO DATA
DISPLAY
BOARD
Address Registers and Data Transceivers
The 80B6 microprocessor uses a multiplexed bus for address and data transfers
(sheet 1 of schematic diagrams). The MPU Board demultiplexes the BOB6 bus into
two buses. One bus controls al I information to the ROM and the RAM which is
contained on locations lA to lH, 2A to 2H, 4A to 4H and 6A to 6H. The other bus
interfaces with other boards in the K205. Locations 9K, 10K and 11K are buffers
for 20 memory address lines (AO to A19) and BHE. Locations 9M, 10M and llL are
buffers for 20 address lines and BHE to boards other than the MPU. The
transceivers for the data I ines are located at locations 7M and BM. Locations
7K, 7L, BK and BL are wired for PROM's and buffers for temporary test only. The
B086 loads addresses into the address registers by using the Address Latch
Enable signal (ALE) and then transmits (WR) the data to, or receives (RD) the
data from, the address in the register.
Memory
The BOB6 memory space is organized into 16 segments of 64K bytes of external
memory space (sheets 2 and 5 of schematic diagrams). Segment E and F (Hex) are
the 12BK bytes of ROM which contains the operating software. Segment 0 - 3
(Hex) contain the 256K bytes of dynamic RAM.
The ROM segment (schematic sheet 5), locations lA to
sixteen BK X B memories arranged into eight sections
Locations 3J and 3K (schematic sheet 4) are ROM chip
output is read from ROM through a buffer at location
and at location 3M for low byte data.
lH and 2A to 2H, uses
of BK words each.
select decoders. Data
3L for high-byte data
The RAM segment (schematic sheet 2), locations 3A to 3H, 4A to 4H, 5A to 5H and
6A to 6H, is made up of thirty-two 64K X 1 dynamic memories providing 128K words
(256K bytes). Data is input into the RAM, through the buffer at location 4J for
high-byte data and at location 6J for low-byte data via RAM WRITE DATA EN. Data
output is read from RAM through the latch buffer at location 4K for high-byte
data and at location 6K for low-byte data via MPU LATCH ENABLE and EN RAM READ.
CRT Data is read out into buffer registers at locatiohs 6L and 4L and then
shifted out at an 8 MHz clock rate to the Data Display Board by shift registers
at locations 6M and 4M~
Memory Controller
The memory timing and the clock for the 80B6 microprocessor (sheet 3 of
schematic diagrams) are derived from a 24 MHz osci I lator (location Yl).
Locations lOA, 10C, 100, 10E, l1C, 110, l1E and llF are used to divide to an
8 MHz clock to the CRT and a 4 MHz clock to the BOB6 clock pin. Locations lOA,
100, 110, 12D and 12E divide the 24 MHz clock into timing signals used to
generate Row Address Strobe (RAS) at locations lOB and 8B. Additionally, column
Address Strobe (CASO and CAS1) are also generated at locations BA, 9A and 12C.
Write Enable signals for high-byte and low-byte of both RAM segments are
generated at locations 7A, 8A, 8B, lOA and lOCo Row Select, Column Select and
Latch Enable for both the MPU and CRT are generated at locations 9A and 9B.
The CRT port of the memory requests a word from memory every 2 us (500 KHz).
The CRT page select addresses are generated at locations 7C, 70, BC and BD
(sheet 4 of the schematics) by the 500 KHz clock rate from location 7B. If the
8086 requests a memory cycle during the CRT cycle, the memory controller uses
the READY I ine on the 80B6 microprocessor to generate wait states until the CRT
cycle is finished and the memory can complete the requested 8086 memory cycle.
4-12
The CRT Read cycle of one word every 2 usec also provides sequential opera+ion
required for the RAM refreshing.
I/O Decoding
The MPU Board addresses other boards in the system as I/O. The PROM (schematic
sheet 4) at location 10F is used to decode addresses All to A19. When I/O is
addressed, M/IO goes LOW, causing the PROM's outputs to be HIGH. The conditions
in which S.A EN is normally HIGH and DEN (Data Enable) becomes active and causes
the EN OFFBOARD DATA signal at location 9C to go LOW, placing data on the bus.
Read commands for RAM, ROM and S.A are generated by RD, RAM ADRS, ROM ADRS and
S.A at locations 90 and 9E. Control signals RD, WR, DEN, DT/R and M/IO are also
buffered out to other boards via buffers at location 9F.
4-13
THRESHOLD/GPIB/RS-232 BOARD OPERATIONS
Overview
This section describes theory of operation for the K205 Threshold/GPIB/RS-232
Board assembly, Part Number 0114-0170~30. The circuits on this board generate
threshold voltage levels, convert analog voltages to digital equivalents,
control the GPIB Talker/listener interface, control the RS-232 Interface and
process digital readout of external voltage input.
The Threshold/GPIB/RS-232 Board block diagram is shown in Figure 4-4. The board
assembly drawing, schematic diagrams and I ist-of-materials are provided in
Chapter 6. Reference is made to the schematic diagrams throughout the
descriptions for the fol lowing circuit functions:
• Threshold Circuit (Schematic Sheet 1)
• OVM Circuit (Schematic Sheet 2)
• GPIB Interface Circuit (Schematic Sheet 3)
• RS-232 Interface Circuit (Schematic Sheet 4)
• MPU Interface (Schematic Sheet 5)
Threshold Circuit
The Threshold Circuit (sheet 1 of schematic diagram) generates four voltage
sources, as fol lows, that may be selected for each probe: VAR A, VAR B,
TTL and ECl.
The VAR A and VAR B thresholds are defined by the four 74lS273 FI ip-Flop holding
registers, locations 9B and 12B for VAR A, and locations 4B and 60 for VAR B.
The holding registers buffer the MPU data bus to the two A07533lN Oigital-toAnalog Converters WAC) at" location 9A for VAR A and location 4A for VAR B.
Separate cal ibration adjustments are provided for VAR A and VAR B Voltage
levels. The VAR A Gain is adjusted by R6; Offset is adjusted by R9. The VAR B
Gain is adjusted by Rl; Offset is adjusted by R2. Both OACs have a resolution
of lOb i ts.
The TTL and ECl thresholds are generated by using a voltage divider network and
+/- 10V reference voltage level. The cal ibration adjustment for TTL is RB, ECl
is adjusted by R7. The +/- 10V reference adjustment is control led by R44.
The threshold voltages are suppl ied as input to eight analog multiplexers (sheet
2 of schematic diagrams). The selection of a particular threshold voltage (VAR
A, VAR B, TTL or ECl) used by each probe is accompl ished by a set of eight
analog multiplexers and eight buffer amp I ifiers. Six of the multiplexers, at
locations lA, 10, lB, lC, 2A and 20 are tied to high and low data bytes at input
sections A, Band C. Two of the multiplexers are tied to R & S latch clocks
(location 2B) and J & K sample clocks (location 2C). This al lows the software to
select one of the four voltages as the threshold. The outputs of the analog
multiplexers are buffered by the operational ampl ifiers (locations lE and 2E)
which provide a gain of two that increases the range of the OAC output.
4-14
INTERRUPT SIGNAL
r;:=====;;:;:==========::;;;;:===:::) TO DATA DISPLAY BOARD
BAUD RATE SET
.1
~J,.!-,II IlJ
I
FROM MPU
CLOCK
BOARD
C==>l GENERATION 1=====>1
(8 MHz ClK)
2 MHz
1
'I
,----
FROM
FRONT PANEL
DVM INPUT
± 10V
DVM INPUT
BUFFER
1=]
~E~~~
TIMER!
COUNTER
I
RS-232
USART NO.1
1r
I-- r l
I
I I
~
.j:lo.
I
\J1
FROM
, r---'I
POWER SUPPLY ~
~ Dof--
E
TO FRONT PANEL
INPffA':0.5
GEN
...--.
VAR "A"
GEN
L-.. VAR "B"
'----,.
GEN
THRESHOLD
SELECTION
I--
IrI'r-
I
n
II
IEEE 488
GPIB BUS
DATA BUS OUT 1-::==lI:===:::j DATA OUT REG.
CONNECTOR
IPARALLEL POLL ~=;~~=t~(O~N~REA:R~P:A~N~E~L)~
..-------. RESPONSE REG,!,
GPIB
DATA IN
AUXILIARY
INTERFACE
[
AND
CONNECTOR
GPIB SIGNALS
(REAR PANEL)
INTERRUPT
DATA BUS IN (DO ,15)
REGISTER
RESETll
11
F
.P~~~~
CONTROL
SIGNAL
CONVERTER
L~=m:~
~
11 1
THRESHOLD
SELECTION
DATA LATCH
DATA BUS OUT
I----
DATA BUS
BUS
MANAGEMENT
)
~ ~ TO DATA
I
1
OUT
r----K:===I~~==:;D;At;'A~B;'U;S~I;N~(D;0~'1;5;)::=~
CONTROL SIGNAL BUS
n
STATE
CONTROL
rtmm~mi. CONTROL
GPIB
M
I L.lDVM DATA BUS!---.
I
LATCH
r-- I.--_---J
I
GPIB
DATA OUT
CONTROL SIGNAL BUS
ICOM~~ATOR
I-r--
RS·232
INTERFACE
AND
CONNECTOR
ON REAR PNL
DVM INPUT
SELECTION
GATES
RS-232
USART NO.2
bmmi~1immmm~PiDmAtmAEB~UiS~lmNm(DmOI~m5m)~
~,.
1i
REF
~TC
~U-----'-'-,
DATA
I BUS OUT I
i-----o
r----.
SOURCE ~
HANDSHAKE j---.
i
-t
DATA BUS I,ADDRESS BUSI
INTERFACE
INTERFACE
00·15
AO·11
TO
REAR t-'-PANEL I.--GET BNC
GPIB HANDSHAKE BUS
MPU ADDRESS/DATA BUS
Figure 4-4. K205 Threshold/GPIB/RS-232 Board Block Diagram
f--I ~:5':~~Y
of the functions contained on the Threshold/GPIB/RS-232 Board Is a software
control led Dlgltal-ta-Analog Converter and a comparator that performs Analog-toDigital Conversions that Is used by the software to check the power supply and
reference voltages during power up. Three multiplexers (sheet 2 of schematic
diagrams) at locations 5F, 6F and 7F are used to select anyone of the power
supply voltages used In the K205. The selected voltage Is then scanned by the
software using the 12-blt DAC at location 8A. When the DAC value exceeds the
voltage being tested, the comparator (location 7A) becomes switched. The MPU
compares the resulting value with a table of voltages and their tolerances to
determine the pass/fall condition of the test result.
On~
DVM Circuit
The front panel DVM input signal (sheet 2 of schematic diagrams) is buffered
onto the Threshold/GPIB/RS-232 Board by the operational ampl ifier at location 7A
and is supplied to the multiplexer at 6F. The multiplexer selects the input
voltage range that is suppl ied to the 12-bit DAC at location 8A and
the comparator. The comparator (location 7A) generates the digital value that
is used by the software to specify the DVM readout.
GPIB Interface Circuit
The GPIB Interface Circuit (sheet 3 of schematic diagram) is partitioned so that
the handshake required to transmit individual bytes of information (for data or
control) is performed by the hardware. All message generation or interpretation
is done In the software. The GPIB address and mode for Talk Only, Talk/Listen
and Listen Only, are determined by the Interactive display for I/O setup. Once
the Mode is determined, the GPIB control register Is loaded with the specified
mode information and the interrupt is enabled. AI I I/O data transfers occur
under control of the interrupt line. With Listen mode selected, the receipt of
a data byte or a command at the K205 wll I generate the Interrupt. With Talker
mode selected, the interrupt Is generated when the byte has been accepted by the
listener I/O device.
RS-232 Interface Circuit
The RS-232 Interface Circuit (sheet 4 of schematic diagram) causes Information
to be entered onto the "Threshold/GPIB/RS-232 Board via two 8251A Universal
Synchronous/Asynchronous Receiver/Transmitter (USART) at locations 120 and 12E.
USART #1 interfaces with the K205 back panel RS-232 port. USART #2 interfaces
with the AUX port. The transmit/receive bit rates (Baud) is set by the 8253B
programmable interval timer/counter at location 8E. The internal timer uses a 2
MHz clock input derived from the CPU oscillator to measure the external master
clock period. The bit rate clock output supplied to the USARTS is set at 16
times the actual rate at which data is being transmitted. Plus and minus
15-volt I ine drivers are used to send the signals to external devices.
WU Interface
The MPU Interface circuit (sheet 5 of schematic diagram) buffers MPU data and
address I ines sent to the Threshold/GPIB/RS-232 Board via the motherboard
interface.
4-16
The MPU data bus (BDO-BD15) is buffered onto the board by two 74LS245 bus
transceivers, locations 14F and 12F which control the two-way direction of data
transfers to and from the MPU Address/Data Bus. The buffered data bytes, 00-07
and D8-DF are transferred to, and received from on board circuits for Threshold
Selection Data Latch (schematic sheet 1), DVM Data Bus Latch (schematic sheet
2), Bus Management and GET BNC output connector (schematic sheet 3),
Programmable Interval Timer and RS-232 USARTs (schematic sheet 4), and GPIB
Parallel Poll Register and Interrupt Register (schematic sheet 3).
The MPU address bus (BA1-BAll) is buffered onto the board by the 74LS244
Buffer/Line Drivers at locations 10F and llF (schematic sheet 5)~ The jumper
connector for M/IO input signal supplied to line receiver at llF must be
connected across E13 and E14 to disable the memory mapped I/O and enable the I/O
mapped I/O function. The 74LS244 buffers generate three state outputs that are
suppl ied to five 74LS138, 1 of 8 decoders, locations 90, lOB, 100, llB and 110.
These decoders accept three binary inputs and output one active-low control
signal (from eight possibilities) for Write Hi Byte, Write Lo Byte, Read High
Byte, Read Lo Byte. The control signals are suppl ied to on-board circuits that
control the Threshold Selection Data Latch, DVM Data Bus Latch, Bus Management
circuits and rear panel GET BNC output connector, Programmable Interval Timer
and RS-232 USARTS and GPIB Parallel Poll Register.
4-17
CLOCK BOARD OPERATIONS
Overview
This section describes theory of operafion for the K205 Clock Board assembly,
Part Number 0114-0160-10/20. The circuits on this board provide al I internal
clock periods and programmable logic functions. These logic functions decode
external clock inputs in accordance with the Master Clock, Sample Clock and
Enable Boolean Expressions selected by the instrument operator. Also, circuits
for the Level Memory, which store the level at which each sample was recorded,
is located on the clock board.
The Clock Board block diagram is shown in Figure 4-5.
The board assembly
drawing, schematic diagrams and list-of-material are provided in Chapter 6.
Reference is made to the schematic diagrams throughout the descriptions for the
following circuit functions:
• Internal Clocks and Probe Test (Schematic Sheets 1 and 3)
• External Clocks (Schematic Sheets 2 and 3)
• AND Master Clocks (Schematic Sheet 3)
• OR Clock Selection (Schematic Sheet 3)
• Level Memory Circuit (Schematic Sheet 4)
• MPU Interface (Schematic Sheet 5)
Internal Clocks
All Internal Clocks (sheet 1 of schematic diagram) are derived from the 100 MHz
oscillator circuit containing crystal Yl. The potentiometer, R19 al lows
adjustment of the average value of the 100 MHz signal on the emitter of Q2 so
that symmetry of the clock output at location 12C, pin 12 can be set.
The
variable capacitor, C8 al lows adjustment of oscillator frequency.
The two 10137 BCD counters, locations 9E and 10E are connected as decade
dividers to provide the 10 MHz and 1 MHz decades.
The 1 .MHz output of 10E goes
to Ql which shifts the level, making it compatible with the input requirements
of the counter at location 9C~
The two 14518 CMOS Dual BCD Counters at locations 9C and 90 operate between -5V
and ground for compatibility with the ECL level.
The outputs of al I six decade
dividers, are supplied to inputs of the eight-to-one, 10164 multiplexer at
location 10C.
The MPU can select any decade as the output of 10C.
For clock
frequencies greater than 10 MHz, the select I ines to 10C, and the 10109 OR gate
at location 100, is set to all zeros by the MPU.
This enables the 100102 OR
gates at location 12C to output the 100 MHz (10nsec) clock. The selected decade
feeds the input to the 10016 Programmable Binary Counter at location l1B.
4-18
TO FRONT
PANEL
100 MHz
OSCILLATOR
FROM FRONT PANEL
INPUT BOARD
DIAGNOSTIC LATCH CLOCK
>0:
§
~
:::;
li!
DECADE
COUNTER
FROM FRONT PANEL _ . _
INPUT BOARD
SEL().2
'"T1
CLOCK SELECTION CONTROL LINES
"K"CLOCK
SELECT
(Q
,c:
MULT.
(I)
.:0.
I
VI
().3
MULTIPUER
SELECTOR
"K"CLOCK
FORCE
DISQUALIFY
FROM
INPUT BOARD
INTERNAL CLOCK
~
.:0.
I
\0
N
0
VI
(")
-0
0
7'
TO REAR
PANEL
CLOCKBNC
"J"CLOCK
SELECT
OJ
,0
QI
0-
LATCH (ENABLE) CLOCKS
A,BANDC
CONTROL CLOCK
(.f)
0
100101
':r
(I)
3
QI
-+
0
SAMPLE CLOCKS
A,BANDC
100101
CONTROL CLOCK
(fO DATA & CONTROL BOARDS)
LEVEL MEMORY DATA (MLO·3)
CLOCK FREQ. SELECTION
MPU ADDRESSIDATA BUS
CLOCK SELECT & LEVEL MEMORY
CONTROL LINES
The combination of the decade dividers combined with the programmable counter
al lows the selection of clock periods from 20 ns to 160 Ms in a 1 through 16
sequence. The software, however,1 imits the user capabi I ity to clock periods
from 20 ns to 100 Ms in a 1 through 10 sequence. The BCD outputs of the 100
KHz decade counter also drives the select I ines of the 4028 CMOS Demultiplexer
at location 9B. The outputs of 9B provide a 1 of 8 pulse pattern to the front
panel PROBE TEST connector as test data.
The 1 MHz clock and the least significant bit of BCD counter at location 9C are
also suppl ied to the front panel PROBE TEST connector as test clocks.
When an
internal clock mode is selected, al I external clocks are de-selected by the MPU
(schematic sheet 3), and the gate at location 3H, pin 21 is pul led low, thereby
enabl ing Internal clocks to pass through to the OR gate at location 4J, pin 9.
External Clocks
The External Clocks (sheets 2 and 3 of schematic diagram) consist of seven clock
circuits as fol lows:
• Three Latch Enable Clocks (schematic sheet 2)
• Three Sample Clocks (schematic sheet 3)
• 1 Control (Master) Clock (schematic sheet 3)
Basically, al I seven clock circuits are the same.
Only the Control Clock
selection, which is the most complex is described in subsequent paragraphs. The
Control Clock selection gates have 13 inputs as fol lows:
One Internal Clock
Three AND Clocks (AJ, BJ and CJ)
Three AND Clocks (AJ, BJ and CJ)
Three OR Clocks ( AK, BK and CK)
'- Clocks (AK, BK and CK)
Three OR
The major difference between Control Clock selection and the Latch Enable
selection is the absence of Internal clocks for Latch Enable and the existence
of Internal MPU Diagnostic Latch Enable.
AND Master Clocks Selection
The AND (Master) Clocks (sheet 3 of schematic diagram) are selected by the eight
100102 gates at locations 3H and 5H. Each of these gates has three inputs. Pin
19 is common to al I gates and is driven by the output of the OR Clock selection
gate at 40.
One pin of each of the 3H and 5H gates is driven by one of the J
Clock inputs or their complements.
The MPU controls the third input by placing
a Iowan those gates whose J Clock input goes high when the selected clock is
true.
Only when al I selected AND Clocks, or the OR Clock is true, wil I all of
the outputs of 3H and 5H be low, thereby al lowing the control clock at location
4J, pin 9 to go high. Synchronous start-up of the control clock is provided by
the 10231 dual fl ip flops at location 5J.
This prevents "sl iver" clocks from
being passed at the beginning of a record cycle.
4-20
OR Clock Selection
The OR
gates at
low on
selected
Clocks (sheet 3 of schematic diagram) are selected by the five 100102
location 50 and parts of the two gates at 4A and 40.
The MPU places a
one input of each gate whose other input wil I be low when one of the
OR Clocks is true. The OR clocks are the K Clock inputs.
Jumper selection for external clocks (schematic sheet 2, section A8) shows
the jumper configuration table. With al I jumpers positioned on the left two
pins, the board is configured for al I twelve clocks. With jumpers positioned
on the right two pins, the C K Clock comes from the B S probe and the C J
Clock from the B R probe.
NOTE:
The software cannot read these jumpers, but instead, counts the
number of Data Boards present in the system.
level Memory Circuit
The level Memory circuit (sheet 4 of schematic diagram) records which level of
trace control is used for each word recorded on the Data Boards. level data
enters the clock board via the 20-pin header, Jl.
The two 10176 registers at locations l1E and 11F and single 10173 register at
location 11J operate as a pipeline which holds the level data temporarily while
the decision is made to either record or not record the data. This decision is
made on the Control Board which generates the Armed and Traced signals along with
the level data that is sent to the pipel ine. When the Traced signal is high,
its complement is clocked into register 11F along with the level data. This
action al lows the OR gate, 12E to produce a write enable pulse on the next
control clock transition. If the Traced signal is false, OR gate 12E is
disabled and the level data in register 11F is written over at the next sample
without being recorded. If the Armed signal goes false, the level memory
becomes locked up.
The two 10016 address counters at locations 11G and 12H are used for the 10422
memories at locations 12F and 12G. The level memory is multiplexed in two ways:
(1) Via the 10231 latc~, pins 13 and 14 at location 110 which select the memory
phase that is written to on each sample. (2) Via the 110 latch at pin 3 which
provides uniform 10nsec pulses when recording is in process regardless of the
sample rate.
In read mode, the OR gate at location 120, pin 3 is disabled thereby causing the
output of latch 110, pin 3 to become 1/2 the frequency of the input. When the
Armed signal goes false, the pin 0 input goes true thereby stopping the pulse.
t-PU Interface
The MPU Interface circuit (sheet 5 of schematic diagram) interfaces the Clock
Board circuits to the motherboard via edge connector P2. The 74lS85 comparator
at 12J decodes four address inputs A4 through A7 from the MPU to provide the
My Address signal when the Clock Board is addressed. The My Address signal
enables the five 10124 TTl-to-ECl level translators at locations 6J, 7J, 8J, 9K
and 10K which buffer the MPU data bus content onto the Clock Board.
4-21
The 10161 de-multiplexer at location 9J decodes address lines Al, A2 and A3
along with the MPU BWR control signal to create load pulses for the 20 10176
holding registers at locations 7A through 7H, 8A through 8H, 9G and 9H, 10J and
10H.
The 10173 multiplexer latch at location lOG multiplexes 8 bits of read data into
two 4-bit nibbles which are translated from ECL to TTL levels by the 10125
translator at location 10F. The 74368 tri-state buffer at location 9F is
enabled by the BRD signal sent from the MPU and the My Address signal generated
by the comparator at location l2J.
The clock Board is configured with eight jumpers located at the lower left
corner of the board. These jumpers select clock signals for 32-input or
48-input capabil ity as determined by the number of Data Boards instal led in
the unit. When the C Option Data Board is added to an existing 32-input unit
to provide 48 inputs, it is necessary to rearrange the jumper connections
to enable the SECTION C clock inputs and route the B R, B S clocks into the
user specified Latch Clock equation. The jumpers must be relocated from the
eight center/lower-row pins to the center/upper-row pins.
NOTE: The K205 software wil I not recognize the SECTION C clock inputs
unless these jumper connections are completed.
4-22
DATA BOARD OPERATIONS
Overview
This section describes theory of operation for the K205 Data Board assembly,
part number 0114-0110-10. Each data board provides 16 inputs and either two or
three identical boards may be instal led in the K205 unit to provide the 32
standard or 48 extended data input configuration. The circuits on this board
buffer input data signals supplied from the user's equipment, select operating
modes, generate the pipeline processing functions, record traced Information in
main memory, decode th~ MPU address/data bus, and present status to the CPU.
The Data Board block diagram is shown in Figure 4-6. The board assembly
drawing, schematic diagrams, and list of material are provided in Chapter 6.
Reference is made to the schematic diagrams throughout the descriptions for the
following circuit functions:
• Data Input Control (Schematic Sheets 3 and 7)
• Operating Modes (Schematic Sheet 3)
• Sampling Circuit Operation (Schematic Sheet 3)
• Data Pipeline Control (Schematic Sheets 2 and 3)
• Memory Control (Schematic Sheet 2)
• MPU Interface (Schematic Sheet 7)
Data Input Control
In the circuit descriptions which follow, al I references are made to data input
signals for AF, BF and CF which are used as an example. Circuits for the 15
remaining signals at each Input Section are identical except as noted.
The differential input signal from the probe (schematic sheet 3) is buffered
onto the Data Board by the 10216 Line Receiver Buffer at location 2B (upper left
corner of schematic). Output of the buffer is presented to the 10121 gates at
location 20.
Control signals from the MPU Holding Registers (schematic sheet 7) select which
of the four data sources, Memory, Probe, Multiplex, or Diagnostic, wil I be
passed through to the sampling circuitry. A description of each data source
type fol lows:
Memory Data: This data source is a recirculation of the channel memory output
which is used only for self-diagnostic purposes (Memory Select).
Probe Data:
This data source is used in normal input mode (Normal Select).
Multiplex Data: This data source obtained from the low order channels is also
routed to the high order channels (F-8). In this case, channel F is paired with
channel 7, al lowing single probing when demultiplex is selected (Demux Select).
Diagnostic Data:
purposes.
This data source is supplied by the MPU for self-diagnostic
4-23
r--------------------------------,
I
I
I
MEMORY DATA I
I
f
MEMORY DATA
DATA
MUX
PIPELINE DATA BUS
FROM FRONT
PANEL INPUT
CH8-F
INPUT
BUFFER
~
173 SELECT
i!:
..
I!i
0
~
:0
ill
~
0
Z
~
0.
I
:0
I
I
I
I
I
I
I
~
ill0
:0
MEMORY DATA I
DATA
~
MUX
PIPELINE DATA BUS
i!:
~
I
N
~
FROM FRONT
PANEL INPUT
CHO:/
INPUT
BUFFER
'0106
INPUT
SELECTION
RAM ADDRESS BUS
L LATCH
_______________________________
.A•
AND GLITCH CAPTURE
INPUT MODE SELECT
DATA OUT BUS
MPUJPOWER-UP DIAGNOSTIC INPUT
NOTE: CLOCK BUS SIGNALS
ARE AS FOUOWS:
1. PIPE LINE CLOCKS
2.~'AND2
3. LATCH CLOCKS
4.231 CLOCKS
5.176 CLOCKS
MUX ADDRESS 0,1· MUX ENABLE
MPIJ ADDRESS/DATA BUS
Figure 4-6. K205 Data Board, Block Diagram
Operating Modes
The output of the 10121 gate at location 2D (schematic sheet 3) is presented to
the mode selection circuit consisting of two 10106 gates at location 2E, the
two 10130 latches at location 2H and 10231 latches at location 2J. This circuit
has three different modes of operation, Sample Mode, Latch Mode, and GI itch Mode
which are described in subsequent paragraphs.
Sample Mode: Pins 6 and 12 of the 10106 gates, location 2E are held high by the
MPU, causing these gates to become disabled in sample mode. Pins 6 and 9 at the
10130 latch, location 2H are held low by the MPU which causes the latch output
to fol low the input asynchronously. The 10231 latch at location 2J is the
sample register. The input data is transferred to the output and held at the
rising edge of the sample clock on pin 9.
Latch Mode: The gate, 2E is disabled as described in Sample Mode. Pin 6 of the
10130 latch at location 2H is held low al lowing the Latch Enable Clock at 2H,
pin 9 to control the latch. When the latch clock is low, 2H is transparent as
in sample mode. When the latch clock goes high, the data that was true at the
clock transition is held at the output. The 10231 sample register at location
2J functions the same as sample mode conditions.
GI itch Mode: The MPU signal GI itch Disable, is low in this mode al lowing
outputs of the 10106, location 2E to be control led by the input data and the
data in the sample register. The MPU signal, Glitch Enable, is high in this
mode, thereby disabl ing the D input pin of the 10130 latch at location 2E. The
state of the 2H latch output is then control led by the outputs of 2E via the
asynchronous set and reset pins.
Sampling Circuit Operation
The sampl ing circuit (sheet 3 of schematic diagram) operates as fol lows: Assume
that pin 2 of the 10130 and 10231 latches, at locations 2H and 2J respectively,
are high at the start of operation. The input pin 5 of gate 2E is high thereby
disabl ing the upper gate that goes to pin 5 of latch 2H. The input at pin 13 of
gate 2E is low which al lows any low input signal to reset 2H, pin 2 by placing a
high on the direct reset, pin 4. Pin 2 of latch 2H remains in this new state
regardless of any activity on the input signal. At the next sample clock, the
output of pin 15 at latch 2J goes low which enables the upper gate of 2E to
respond to a high input signal only. If the input signal goes high at anytime,
the signal at pin 3 of gate 2D goes low causing pin 3 of gate 2E to go high
which sets the output of latch 2H to a high condition for the next sample clock.
In addition to going to the GI itch Feedback Comparison Gates, outputs of the
register are also supplied to: (1) the 10174 multiplexer at location 2L for MPU
diagnostic access, (2) the pipel ine register 10176, location 2K, and (3)
inverted data from pin 14 of latch 10231 goes to the Control Board word
recognition circuits.
Data Pipeline Control
The Data Pipeline (sheet 3 of schematic diagram) consists of two stages of D
registers contained in the 10176 latch at location 2K. The source of the
pipel ine clock depends on either of two clock modes selected as fol lows: In
most modes, the pipe clock is the same as the Master (Control) Clock. In
store mode, the pipe clock is the same as the sample clock.
Note that the data in both stages of the pipel ine is also present at the 10174
multiplexers, locations 1L and 2L for diagnostic access.
4-25
Pipel ine data is also presented to the inputs of both 10176 registers at
locations 6D and 6E which begin" two-way memory multiplexing. The registers at
locations 6D and 6E act as pre-memories and are clocked by the rising edge of
signals WEOl and WE02 respectively, which are output from the OR gates, location
6J or schematic sheet 2. The WEOl and WE02 signals are 180 degrees out of
phase, which causes samples to be stored alternately in the two 10422, 256x4
RAMs at locations 5B and 5C. The 10173 demultiplexer at location 5D
demultiplexes the memory. The data out of 5D goes back to the 10121 input
selectors at location 2D for diagnostic recirculation and to the multiplexers at
location lL and 2l for MPU access.
Memory Control
The Memory Control logic (sheet 2 of schematic diagram) is implemented by the
100155 Mux Latch at location 6H which keeps track of control signals from the
MPU and Control Board. This Mux Latch also controls which phase of memory wil I
be written to, or read from, next via the 01 and 02 signals which alternately
enable the two 100101 gates at location 5J.
When Internal Clock is used, the OLD TRACED signal, output from pin 2 of 6H
combines with the ASYNCH~ signal from the MPU to form the MEMORY ALIVE
signal which enables pins 5 and 9 of the 100101 gates at location 5J.
When External Sample Clocks are selected, the MEMORY ALIVE signal is derived
from the SYNC MODE MPU control signal and the TRACED signal from the Control
Board. The outputs of pins 5 and 9 at location 5J are the WE pulses for the
record memories.
The HALTED output signal from Mux Latch at location 6H disables the OR gates at
location 5K. These gates pass the sample clock and select the source of the
pipe clock. The OR gates at location 6J distribute al I clocks and the WE
signals. Note that the width of 173 clocks at gate 6J, pin 13 is set by a
difference in propogation delay when the same signal feeds both inputs via two
different paths~
MPU Interface
The MPU Interface circuits (sheet 7 of schematic diagram) decode the MPU Address
Bus via the 10124 TTL to ECL Translator at location 8K, the 74S85 four-bit
comparator at location 9M and the associated circuits. The 10124 translators at
locations 6M, 7L, 10L and 9K are also used as TTL to ECL level translators for
the data bus. These translators feed the inputs of the 10176 Hex D latches
which hold control information from the MPU.
The 10173 Multiplexers at locations 12M and 13M multiplex the lower 8 bits of
Read data to the MPU. The 10125 TTL to ECl level translators at locations 1M,
2M, 3M and 11M translate TTL logic levels received from the bus to ECl logic
level for data board interface.
4-26
CONTROL BOARD OPERATIONS
Overview
This section describes theory of operation for the K205 Control Board assembly,
part number 0114-0120-10. The Control Board contains al I decision making logic
for control I ing the recording process. This includes word recognition circuits,
delay counters, and the logic to combine delay conditions with detected words.
These circuit functions cause the K205 unit to stop recording, jump or advance
to another level with different record parameters and selectively enable or
disable the recording operation.
The Control Board block diagram is shown in Figure 4-7. The board assembly
drawing, schematic diagrams, and list of material are provided in Chapter 6.
Reference is made to the schematic diagrams throughout the descriptions for the
fol lowing circuit functions:
• Word Recognition Circuits (Schematic Sheets 1, 2, and 3)
• Word Selection Circuits (Schematic Sheets 4 and 5)
• Level Switching Circuit (Schematic Sheet 6)
• Delay Counter (Schematic Sheet 8)
• Recording Control Circuits (Schematic Sheet 7)
• MPU Interface (Schematic Sheet 9)
Word Recognition Circuits
The Word Recognition Circuits are contained on sheets 1,2 and 3 of schematic
diagrams. Word recognition is accomplished separately for each Input Section,
A, B, and C with the separate words being combined in the word selection
circuits described in subsequent paragraphs. In the circuit descriptions which
fol low, al I references are made to the Section C Input (schematic sheet 3) which
is used as an example. Sections A and B operate identically to Section C.
The DATA signal supplied from the Q output of the sample registers on the C Data
Board enters the Control Board via the motherboard and is synchronized with the
control clock in the 10176 registers at locations 1H, 2H, and 3H. The data
output from these registers Is presented to four of the eight address inputs,
and to each of the four 10422, 256x4 Static RAMs at locations 1G, 1F, 3G and 3F.
The other four address I ines of the RAMs are driven by the LEVEL X signal, where
X is the 4-bit number representing the level of trace control.
The four data
outputs of the 10422 RAMs correspond to the four combinational functions of the
K205 for STOP, JUMP, ADVANCE and TRACE signals generated by the 100101 OR gates
at locations 1D and 3~.
The MPU initializes the RAMs to contain zeros only at those address locations
and bit positions that correspond to the combinations selected by the user for
STOP, JUMP, ADVANCE and TRACE at each level.
4-27
FROM
DATA
BOARD "B"
FROM
DATA
BOARD "A"
LEVEL SELECTION BUS
r
1
/--
-
CLO~
r--I
~
DATA BUS OUT
r
1
JUMP
SELECTION
ADVANCE
SELECTION
ex>
I
G
WORD DETECTION DATA BUS
=
DATA BUS IN
DATA "C"
WORD
DETECTION
DATA BUS OUT
[
~
I
N
I
MPU DATA BUS IN
~
FORCE
CONDITION
GENERATION
11
DATA "B"
WORD
DETECTION
DATA "A"
WORD
DETECTION
•
FROM
DATA
BOARD"C"
1
STOP
SELECTION
TRACE
SELECTION
fL ~ DC bD
AJST DATA BUS
~
TO CLOCK
BOARD LEVEL
MEMORIES
c= ==
LEVEL SELECTION BUS
LEVEL SELECTION BUS
I--
11
J
LEVEL
SELECTION
TO REAR
L-....,
PANEL TRACE
BNC
CONTROL
CIRCUITS
T=D
T>D
TD in these circuits.
For purpose of this discussion, only the ADVANCE
select circuit wi I I be considered.
The STOP, JUMP and TRACE circuits generally
operate in the same manner as the ADVANCE circuit.
The signals for ADVANCE A, B, and C, and their complements along with the delay
condition signals f<5, T=D, and T>D are presented to the inputs of the 100102
gates at locations 5C and 50.
Each of these gates is also suppl ied with one of
the outputs of the 10145A High Speed, 4x16 RAMs at location 4B, 5B and 6B. The
outputs of gates 5C and 50 are NORed together in the 100101 gate at location 5F
whose input must be low for the ADVANCE signal to go high.
The ADVANCE signal
wi I I be low if any of the gates at location 5C or 50 have lows on al I three
inputs. Pin 19 of gates at locations 5C and 50 is common to al I gates and is
low at al I times except during Diagnostic Tests or when the Arm Initial ization
condition is present and the MPU can pul I it high for the FORCE ADVANCE
condition, as presented in the fol lowing example operation.
1.
Assume the user has selected conditions for:
Advance if Data=A and T=D
2.
For this selection, the MPU would initial ize the 10145A High Speed RAMs
to place a low state at pins 1 and 17 of gate 5C. Signals at the
appropriate level would be applied to pins 17 and 24 of gate 50.
3.
4.
The control I in9 input signals to these gates become: ADVANCE B, TO, ADVANCE C, and ADVANCE A.
If anyone of these signals is low, indicating the selected equation is
false, the output of the gate it controls wil I be high, causing ADVANCE
to be true and ADVANCE to be false.
The address inputs to the 10145A High Speed RAMs is the 4-bit LEVEL number
(e.g., LEVEL 3C, LEVEL 2C, LEVEL lC and LEVEL OC). It is therefore possible to
select a different Advance equation for each of the 16 levels of trace.
The inputs to the 100101 OR Gate at location 70 paral lei the inputs suppl ied to
OR Gate at location 5F which are control led by the Word Recognition Logic,
disregarding the delay conditions. The outputs of 70 are cal led EVENT and EVENT
which are used to control the delay counter in Events Delay Mode.
The 10176 Registers at locations 6A and 7A are used to hold MPU control signals
which can force the signals for STOP, STOP, JUMP, JUMP, ADVANCE, ADVANcE, TRACE,
TRACE, EVENT, and EVENT to a desired logical state by overriding the normal
input conditions. These signals are used during the Diagnostic Checks and the
Arm Initialization Sequence.
4-29
The register at 6A also enables the 10231 Latch at location 5A to FORCE ADVANCE
for one clock period. This is used for manual advance and to begin the armed
cycle when the unit advances from Level F into Level 0 on the first control
clock.
Level Switching Circuit
The Level Switching Circuit is contained on sheet 6 of the schematic diagrams.
The 100155 IC at location 5G is a Quad Multiplex Latch. The two sets of inputs
to the latch come from the two 10145A RAMs at locations 5H and 5J. The address
input to 5H and 5J is the 4-bit number level. The 5H and 5J RAMs are
initial ized by the MPU so that for any given level address, 5H contains the
number of the user selected Jump To Level.
The 100155 has two Enable inputs, both of which must be in a low state for the
selected input to be transferred to the output as the next level. One of the
Enables is driven with the JUMP OR ADVANCE control signal, al lowing the level to
change only when a JUMP or ADVANCE condition is detected. The other Enable is a
3nsec pulse derived from the control (master) clock. The new level then becomes
the new address for the Level RAMs 5H and 5J. The propagation delays around the
loops are that much greater than the 3nsec Latch Enable pulse that al lows
glitch-free operation to occur. The JUMP condition present at pins 16 and 17 of
5G selects which set of inputs wi I I become latched. Therefore, the decision to
jump or advance gives priority to jumping even when the advance condition is
true at the same time.
Delay Counter
The Delay Counter circuit is shown
10016 at location 13C and 13E form
The 10145 RAMs at location 14C and
is initial ized by the MPU with the
for the corresponding Level.
on sheet 8 of the schematic diagrams. The
a 'simple Programmable Synchronous Counter.
14F are addressed by the Level. Each address
two's complement plus 1 of the delay number
Recording Control Circuits
The Recording Control circuits are shown on sheet 7 of schematic diagrams. The
ICs at location 12A, 12B and14B store the status of the Control Board that was
present prior to the most recent transition of the control clock. Note that al I
output signal names are expressed in past tense. The Input conditions that
caused the outputs to become true may not always remain true after being
latched. These remembered state signals are decoded by gate circuits located
at 110, 11C, 11B, 11A, 11F and 9B along with the DELAY TOP COUNT (TC) signal
(suppl ied from location 110 on sheet 8 of schematic). The TC signal controls
the delay status bits, T=D, TD to stop recording at the correct time
and to control the process of selective trace recording.
The 100155 Mux Latch at location 12B has three inputs, EVEN~ ADVANCE and JUMP.
Two of these inputs ADVANCE and JUMP are connected to both the A and B Mux
inputs and are clocked to the output regardless of the state of the Mux
Selection Control on pins 16 and 17 of 12B. The two output signals ADVANCED and
JUMPED are ORed together at location 11C, to form the DELAY PE signal, which
al lows the delay counter to become loaded on the next clock transition and
Advanced or Jumped which is used to control the states of the delay condition
signals.
4-30
The Mux Select control signal for 12B is the EVENT MODE signal which is output
of the 10145A RAM at location 13A. This bit Is high at those levels in which
the user has selected Events Delay Mode. If EVENT MODE is low, the A Mux inputs
of 12B are selected causing output pin 9 of 12B to become latched low only when
EVENT is low.
The output signal at pin 9 of 12B is called EVENTED and is combined with the 0[0
TO signal (which is at a low state if T was less than 0 prior to the last clock)
to form the DELAY CE signal. Therefore, operation In Events Delay Mode only
al lows the Delay Counter to increment once for each sample on which the selected
event combination was true.
.
The 10055 Mux Latch at location 14B also has three inputs, ADVANCE, STOP and
TRACE. The STOP and TRACE inputs are connected to both the A and B Mux inputs.
The STOP input signal becomes STOPPED after being clocked through 14B and causes
the ARMED signal to become false there~YACnding the recording process. The
TRACE input signal becomes TRACED and TR ED after being clocked. The TRACED
signal is combined with ARMED and is fed to a BNC connector on the rear of the
K205 chassis as the TRACE signal. The TRACED signal is routed to the Data
Boards where it is combined with the ARMED signal to al low the sample that
caused the trace condition to be recorded.
The third input to Mux Latch at location 14B is the ADVANCE signal which is
connected only to the B Mux input at pin 15. The Mux control input which
determines whether ADVANCE will be latched in 14B is the END LEVEL signal which
is one of the outputs supplied from the 10145A RAMs at location 13A. The END
LEVEL signal will be high only at Level F.
The output signal at pin 9 of 14B is cal led ADVANCED and ENDED. As the name
impl ies, the signal will be true only if Advance and End Level are both true
when 14B Is clocked. The Advanced and Ended condition causes the ARMED signal
to go false thereby ending the recording process.
The 10176 Mux Latch at location 12A has six Inputs: 0=1 IF JUMP, 0=1 IF ADVANCE,
CYCLE RESET, Tn. The CYCLE RESET signal is used only by the MPU
during the Arm Initialization cycle or during Self Diagnosis. The other five
inputs to 12A coordinate the switching of the delay status bits. The signals
for 0-1 IF JUMP and 0=1 IF ADVANCE are supplied from the 10145A RAM at location
13A. These signals provide a look ahead function to provide delays of one which
the 10016 Delay Counter cannot provide. The signals for 0=1 IF JUMP and 0=1 IF
ADVANCE wil I be low only if the next level (either the JUMP-TO or ADVANCE-TO
level, or both) has a delay of one selected.
The outputs of 12A for 0=1 IF JUMPED and 0=1 IF ADVANCED are combined with the
JUMPED and ADVANCED signals respectively at location llC and 110 to cause the
T=D signal to become true immediately upon entering a level with a delay of one
selected.
The signals for TO. These three signals also must be present at l1B, l1C, and 110
to ensure proper cycl ing of the delay condition bits. The 10164 Multiplexers at
locations 12C and 12F provide access for the MPU to determine record control
status for self-diagnostics.
4-31
MPU Interface
The MPU Interface is shown on sheet 9 of the schematic diagram. The 74lS85
Comparator at location 13H decodes the address bus to enable the interface only
when the Control Board is addressed. The 10124 Translators at locations 11H,
8J, 7J, 3J and 10H provide TTL to ECl level translation for the 16 line
address/data bus. The read data from the Control Board is multiplexed down to
only four lines. These lines are translated from ECl to TTL levels by the
74368A Three-State Inverter Buffer at location 12H. The 10161 Demultiplexer at
location 13G decodes Address lines Al, A2 and A3 along with the WR signal from
the MPU to provide lOAD signals for the MPU programmable holding registers, word
detection RAMs and control RAMs.
4-32
Chapter 5
DISK DIAGNOSTICS
INTRODUCTION
This chapter provides the technician with descriptions of, and instructions
for executing diagnostic test routines contained on the K205 Master Diagnostic
Disk, Gould part number 0120-0167-10. Separate test routines are provided for
each printed circuit board and associated circuits, excepting the MPU Board.
The MPU Board is tested by the K205 Power-Up diagnostic firmware which
verifies the operational status of the MPU Board whenever the K205 unit is
initial ized. The t1PU Board must therefore be functional to load and execute
the K205 Disk Diagnostic Routines.
The K205 Diagnostic Operating System (DIAG) software is organized as shown in
Figure 5-1. The operating system is a monitor control program designed to
checkout hardware/software functions for K205 printed circuit boards and
components. The K205 DIAG is driven by the 8086 CPU on the MPU Board. the
diagnostic routines are executed by using keys on the keyboard to select and
set up a specific test module and control the testing operating.
Major features of DAIG are as fol lows:
• DIAG provides a menu for the operator to enter options and parameters.
The individual Diagnostic modules use these options to determine program
flow and operation.
These options specify which boards in the system are to be tested,
the number of times to repeat each test, halt diagnostic execution upon
error, loop diagnostic execution upon error, test floppy disk Drive A or
B, test Drive Side 0 or Side 1, display or suppress error messages and
al low operator interaction whi Ie running the Diagnostics. These options
and parameters ar~ explained in a later section •
•
DIAG loads Diagnostic modules from Disk and executes them.
The Diagnostic modules consist of six programs on the K205-D disk and
are loaded in one at a time, and executed. Due to the size of the modules,
(up to 40k in length), and the I irnited RAM space available, (64k), it
would be impossible for al I of the code required to test the K205 to be
resident in memory at once.
So when DIAG is testing a particular board, the appropriate Diagnostic
module is then loaded in from the Disk as an overlay and executed.
These Diagnostic modules are discussed in a later section •
•
DIAG provides Pass/Fail History information.
DIAG keeps a tabulation of each time a test is executed, and whether it
Passed or Fai led. This information is accumulative, so if the Diagnostic
is run for a long period of time, the Pass/Error information is a total
representation of al I Passes and Errors.
5-1
K205
MASTER DIAGNOSTIC DISK
PART NUMBER 0120-0167-10
MEMORY RESIDENT
MONilOR CONTROl PROGRAM
1<205 DIAGNOSTIC
OPERATING SYSTEM
(1<2050)
DISK RESIDENT
DIAGNOSTIC MODULE ROUTINES
(KDOIAG) KEYBOARD/DISPLAY BOARD
(DBOIAG) DATA BOARD
(CBDIAG) CONTROL BOARD
(CKOIAG) CLOCK BOARD
(THDIAG) THRESHOLD/GPIBlRS-232 BOARD
(SCOIAG) SlORAGE CONTROUER BOARD
DISK RESIDENT
UTILITY FILES
PASSlFAlL STATUS FOR SPECIFIC TEST
ACCUMULATED ERROR COUNT FOR BOARD
ACCUMULATED PASS COUNT FOR SPECIFIC TEST
ERROR MESSAGES
INFORMATION MESSAGES
Figure 5-1. Organization of K205 Diagnostic Software
5-2
NOTE:
The maximum number of Passes and Errors DIAG can log is 65,535.
If the error count reaches this limit, it wil I not wrap around to 0, rather
DIAG wi I I stop incrementing this count.
STARTING UP THE K205 DIAGNOSTICS
* * * * * * * *
*
*
*
*
*
*
*
*
*
*
*
* *
* *CAUTION* * * * * * * * * * * * *
Prior to using the K205 Master Diagnostic
Disk, it is recommended that the user format
and copy the master disk as described in the
K205 Disk Storage System User's Manual Addendum.
Store the master disk and use the duplicate as
a backup to avoid possible damage to the original.
Ensure the duplicate disk is write protected to
prevent inadvertent writing that could destroy
data.
*
*
*
*
*
*
*
*
*
*
************************** ***
When The K205 Logic Analyzer is powered on, it wi I I perform it's power on
self test Diagnostics. Assuming these have Passed, the Logic Analyzers's
default menu wi I I be displayed.
To boot up the Disk Operating System,
insert the mini Floppy Diskette into Disk Drive A with the Write protect
tab nearest to the activity light, and close the door on the Drive.
Press the "I/O" key, then press "1". This wil I "boot up" the Disk
Operating System and the screen display should change to show the directory
contents of the Diskette. The following files should be In the display:
K205D -01 .EXE
KDDIAG-OO.EXE
DBDIAG-OO.EXE
CBDIAG-OO.EXE
CKDIAG-OO.EXE
THDI AG-OO.EXE
SCDIAG-OO.EXE
(K205 Diagnostic Operating System)
(Keyboard/Display Diagnostic Module)
(Data Board Diagnostic Module)
(Control Board Diagnostic Module)
(Clock Board Diagnostic Module)
(Threshold/GPIB Board Diagnostic Module)
(Storage Controller Diagnostic Module)
Other files may be listed, but they are irrelevant to the Diagnostics.
The diagnostic modules for KDDIAG, DBDIAG, CBDIAG, CKDIAG, THDIAG and SCDIAG
are not executable as stand alone programs. They are loaded In and executed
by K205 D-O 1 • EXE • I f a "RECALL" is done on one of these mod u Ies, the K205 wi I I
lock up, and the power wil I have to be turned off, and restored to reset
system operations.
To load the K205 Diagnostic, press the NEXT key until the DOS "RECALL"
selection appears. Press the right arrow key to enter the filename field.
Press the down arrow key until K205D-Ol.EXE is highlighted. Press the F4 key.
This loads DIAG from the Disk and executes it. The K205 Diagnostic Main Menu
is then displayed.
DIAG MENUS AND DISPLAYS
Main Menu
The "main" menu Is displayed upon booting up DIAG. This main menu has three
main fields as fol lows:
5-3
The top of the screen has a list at the keys, and a description of
the function for each key. Throughout the Diagnostic execution,the top of the
screen wi I I have a list of keys. The keys listed and the functions of these
keys wi I I vary, depending on the particular state or menu the Diagnostic is in.
The lower-right side of the screen has a list of the "Active" boards
in the system. When DIAG began executing, it determined which boards were
instal led in the K205 chassis. The boards that it found are designated as
"Active", and these are the boards that are tested.
The lower-left side of the screen has a I ist of the "Inactive" boards,
or the boards that are not present in the system. Some boards are optional,
and since DIAG was written to test al I possible components of a K205 system,
boards that are not present are displayed as "Inactive", indicating that these
boards wi I I not be tested.
NOTE: The "Active" and "Inactive" status can be forced or overridden. If,
for example, a board is actually present in the system, but you do not wish
it to be tested, you can force it to become Inactive by positioning the cursor
with the up or down arrow keys, next to the name of the board, and press the
left arrow key. This action wi I I place the board into Inactive status. This
can be done for any or al I boards.
Boards that are flagged as "Inactive" can be forced to become "Active"
by positioning the cursor using the up or down arrow key, next to the name of
the board and' pressing the right arror key. This would be useful if a board
is actually in the system but is faulty, and caused it to appear in the
"Inactive" status when DIAGstarted up. The board- can be forced "Active" and
tested.
Of course if a board is not in the system, and it is forced to be
"Active" and the Diagnostic is run, it wi II Fai I and give you non relevant
information.
System Testing (All Actiye Boards)
When DIAG is started and the Main Menu is displayed, the Active/Inactive/Test
»> cursor wi I I be pointing to "AI I Active Boards". If the NEXT Key is
pressed, al I of the tests for al I of the boards In the "Active" list wi I I be
automatically tested sequentially.
..-
Before each test is executed it wi I I be loaded in by DIAG and the message
"Loading Diagnostic Fi Ie" wi I I be displayed. The name of the current
Diagnostic module wi I I be displayed at the top and the test names and test
steps wi I I be updated.
During this automatic testing DIAG wi I I display the number of Passes
and Errors at the bottom of the screen. If there are any Errors, an Error
message wi I I be displayed at the center of the screen, and the Error count
at the bottom of the screen wi I 1 be incremented. The Pass counter at the
bottom of the screen wi I I not be incremented unti I al I tests for al I Active
boards are performed.
5-4
If at any time you wish to abort the Diagnostic execution, pressing the
STOP key wi I I abort the current test and return to the Main Menu.
System Testing is normally performed if an overal I picture of the
unit's integrity is desired. Since al I Subtests for al I Active boards wi II
be performed, this testing wi I I take quite a whi Ie.
Single Board Testing
If a single board is to be tested, the Test »> cursor should be
positioned next to the name of the board and the NEXT key pressed. This method
is different from testing "AI I Active Boards" in several ways as follows:
First,the testing is performed only on the chosen board.
Second, the testing is not started automatically. The Subtest Menu list
for that particular Board wi I I be displayed, and either all Subtests can be
executed, or a single Subtest can be executed.
Third, the Pass and Error count is not displayed at the bottom of the screen.
Single Board testing is done when the integrity of a single board or
boards is unknown, and a direct test on the board in question is performed.
This method provides information at a quicker rate than if al I the previous
boards in the Active list are tested.
If at any time you wish to abort the Diagnostic execution, pressing the
STOP key wi I I abort the current Subtest and return to the Subtest Menu.
Conducting All Subtests or Individual Subtests
When a single board is selected for testing, the Subtest Menu is
displayed. A single Subtest can be performed by positioning the highlighting
cursor, using the up or down arrow keys, over the desired test and pressing
the NEXT key. The single. Subtest wi I I run, and then return to the Subtest
Menu. If the parameter selection for NUMBER TO REPEAT TESTS is greater than 1,
the particular Subtest wi I I be repeated that number of times.
Selecting "ALL SUBTESTS" executes al I of the tests in the Menu sequentially,
and returns to the Subtest Menu when complete.
If at any time you wish to abort the Diagnostic execution, pressing the
STOP key wil I abort the current Subtest and return to the Subtest Menu.
Pressing the PREVIOUS key restores the Main Menu.
DIAGNOSTIC PARAMETERS (EDIT KEY)
General
There are a number of options or parameters avai lable for execution of
the Diagnostic modules. These parameters control the program flow of execution.
The parameters can be displayed and/or changed at any time by pressing the
EDIT key. This wi II display the list of parameters, and the current selections.
5-5
Once the parameter options are selected, p~essing the PREVIOUS key wi I I return
you to the previous Menu Display or program execution.
The parameters are changed by positioning the highlighting cursor next
to the desired parameter and pressing the NEXT key. This wi II select the
opposite of the currently displayed option, i.e. YES changes to NO. This
method is valid for al I parameters except the Times to Repeat Test, which
is explained later.
The parameters are as fol lows:
Parameter
Options
-----------------------------------------------------------
1 • Halt on Error
2. Loop on Error
3. Display Error Messages
4. Times to Repeat Test(s)
5. Test Floppy Disk Drive A
6. Test Floppy Disk Drive B
7. Test Side 0 of Drive(s)
8. Test Side 1 of Drive(s)
9. Run Operator Action Tests
No, Yes
No, Yes
Yes, No
1 - 65535
No, Yes
Yes, No
Yes, No
Yes, No
No, Yes
(default
(default
(default
(default
(default
(default
(default
(default
(default
s
s
s
s
s
s
s
s
s
No)
No)
Yes)
1>
No)
Yes)
Yes)
Yes)
No)
Halt on Error
The first parameter, Halt on Error, specifies that if an Error occurs during
execution of the Diagnostic, the Diagnostic wi II temporarily halt and the
Error message remains on the screen. A "HALTED ON ERROR" blinks on the screen
to verify that the Diagnostic is halted. Diagnostic execution can be resumed
by depressing the NEXT key. If another error occurs, DIAG again halts until
the NEXT key is depressed.
Normally when there is an Error, and the Halt on Error parameter is
not selected, the Error message is displayed on the screen for about a second.
This doesn't al low adequate time to read al I of the information displayed,
so Halt on Error is useful for "single stepping" through the Errors that occur.
The disadvantage of Halt on Error is that when an Error occurs, al I
testing is suspended, and the NEXT key must be entered to resume. In the case
where you want a unit to run the Diagnostics for a period of time without the
need of operator actions, and then later check on the number of Passes and
Errors, Halt on Error should be disabled by setting the option to "NO".
Loop on Error
Loop on Error specifies that if during the execution of the Diagnostic
an Error occurs, the Diagnostic wil I loop on the test step that found an Error.
This test step wil I be repeated continuously even if it occasionally Passes.
The Loop on Error option is useful for debugging a board. If for
example, a board is intermittently failing, the continuous looping al lows the
operator to trigger on a Write pulse, a Read pulse or a Clock.
The looping continues until either the CONTROL key is pressed, or the Loop
on Error option is disabled by pressing the EDIT key, and changing the
selection to "NO".
NOTE 1: The CONTROL key is used during the process of Looping on Error.
Pressing the CONTROL key "skips" out of the current Test Step and proceeds to
the next Test Step. It provides a means to quickly abort a Test Step without
changing the Loop on Error Parameter.
NOTE 2: The Loop on Error option has one characteristic that could be
confusing. If for example, the option is enabled and an Error occurs, the
Error message wi I I be displayed as usual, and the test wi I I be repeated. But,
the Error message is only displayed for about a second, so if the test starts
Passing, the Diagnostic may appear to hang since no messages are being
displayed and the Test Step number is remaining constant. The Diagnostic is
not hung up, it is in fact repeating the same Test Step without Error.
Pressing the CONTROL key, or disabling the Loop on Error Parameter wi I I al low
the Diagnostic execution to proceed.
Display Error Messages
This parameter controls whether or not the Error messages are displayed
Errors occur.
when
Normally when an Error occurs, and this option is set to YES, a message
describing the Error is displayed for about a second, then the message is
cleared. For most testing situations this is the desired response.
If a test
test, and
Each time
increases
this wi I I
is running that is rather lengthy, such as a RAM addressing
there are many Errors, the screen wi I I display many Error messages.
a message is displayed the Diagnostic is paused, and this actually
the Total Test Time. If the'Display Error Messages is set to NO,
decrease the Total Test Time.
If the unit is to be run unattended (i.e. it is not necessary to view
every Error message and the maximum number of test cycles desired), this
parameter should be set to NO. The total number of Errors can be displayed at
a later time by pressing the DATA key.
NOTE:
When the Display Error Messages is set to NO, the Diagnostic module
that is currently executing sti I I cal Is the Error tabulation routine, so every
Error is counted and tabulated.
Number of Times to Repeat Test(s)
This parameter controls the number of times a test is performed. The
default is 1. This means when the test or tests are started by pressing the
NEXT key, testing is executed one time and the Diagnostic wi I I pause.
If several test repeats or continuous testing is desired, any number
from 1 to 65,535 can be selected. Enter this parameter by positioning the
cursor, pressing the NEXT key, entering a number with 1 to 5 digits, and again
pressing the NEXT key. (If 5 digits are entered, the terminating NEXT key
need not be pressed.)
For example if the count desired is 158, press NEXT, 1, 5, 8, NEXT.
If a number larger than 65,535 is entered, the program wi I I request you to reenter the number.
5-7
NOTE: If the repeat count is more than one, DIAG wi I I cycle through al I
Subtests of al I Active boards and then repeat the cycle unti I the repeat count
has been reached.
At any time during this execution, the DATA key may be pressed to view
the Pass/Error history then the PREVIOUS key wi I I resume execution. The EDIT
key may also be pressed to change any of the parameters. The PREVIOUS key wi I I
then resume execution.
Test Drive A, Test Drive B
This parameter refers to the Floppy Disk Drive tests for Disk Drives
A and B. If a Drive is selected, a Disk Write/Read test wi I I be performed on
that Drive, and a "scratch" Disk must be used since al I data on that Disk
wi I I be destroyed.
The default selections are Drive A = NO, Drive B = YES. The Diagnostic
Disk is residing in Disk Drive A~ and a "scratch" Disk should be residing in
Disk Drive B. With the default selections, no operator actions are required.
Drive B is tested, and Drive A is not tested.
If both Disk Drives are to be tested, the parameter options must be
changed to Drive A = YES, and Drive B = YES. Each time DIAG is ready to test
Disk Drive A, the Diagnostic Disk must be removed, and a "scratch" Disk
placed in the Drive. When the test is complete, the sratch Disk wi I I have to
be removed from Drive A, and the Diagnostic Disk re-inserted.
This procedure requires actions to be performed by the operator, and the
RUN OPERATOR ACTIONS parameter must be enabled. This wi I I be explained later.
NOTE: A "scratch" Disk is defined as a new or fairly new Floppy Diskette,
that has been "formatted" using the K205 Disk Operating System Format command.
The Write Protect slot must not be covered. The Disk used should not contain
any important data or programs, since the process of Formatting and the Disk
Drive testing destroys al I data on the Diskette.
Test Side 0, Test Side
This parameter also refers to the Floppy Disk Drives testing. Each
Disk Drive has two sides, Side 0 and Side 1. Normally parameters 7 and 8 wi I I
be YES, and both sides wi I I be tested during the Floppy Disk testing.
If for example, Disk Drive B is having Errors on Side 1, and no Errors
on Side 0, setting the TEST SIDE 0 option to NO wi II al low for more frequent
testing of Side 1 of the Disk Drive, and give more Pass/Fai I information at a
quicker rate.
Run Operator Action Tests
Some of the tests in the Diagnostic modules require the operator to
perform certain actions. One example is the testing of Disk Drive A requires
the operator to remove the Diagnostic Disk and insert a "scratch" Disk, al low
the test to run, then re-insert the Diagnostic Disk.
Other actions might be the installation of RS-232 wrap-back connectors, the
testing of the Keys on the K205 Keyboard, GPIB Testing, etc.
5-8
If a unit is to run the Diagnostics unattended, this parameter should
be set to NO, and the specific tests that require operator actions wi I I not
be performed.
PASS/ERROR TABLUATION (DATA KEY)
At anytime during the Diagnostic Execution the number of Passes and
Errors can be displayed by pressing the DATA key. Pressing the PREVIOUS key
wi I I return to the previous Menu or executions. A list of the boards in the
system wi I I be displayed, as wei I as the total number of Errors as fol lows:
Number of Errors
Cycle Through AI I Tests
Keybd/Display
Data Board A
Data Board B
Data Board C
Control Board
Clock Board
Threshold Board
Storage Controller Board
0
0
0
0
0
0
0
0
There are two fields that are highlighted by the cursor, they are
"Errors" and "Cycle Through AI I Tests". If the cursor is over Errors, pressing
the NEXT key wi I I change the display to the number of Passes, (changing Errors
to Passes). Pressing the NEXT key again wi II change back to the Error display.
This Errors/Passes display shows the total accumulative Errors and
Passes for each board in the K205 System. If a board is not in the system, or
it was forced Inactive, the Pass and Error count wi I I be 0 for that board.
Otherwise, the number of times DIAG tested the board wi I I be displayed for the
Passes, and the total number, (if any), of Errors wi I I be displayed.
If the down arrow key is entered this wi I I move the cursor into the
"Cycle Through AI I Tests" field, and pressing the NEXT key wi I I display the
total Errors/Passes for each Subtest of the Keyboard/Display Board. Pressing
the NEXT key wi I I then display the total Errors/Passes for each Subtest of
Data Board A.
Consecutively pressing of the NEXT key wi I I display the Data Board B,
Data Board C, Control Board, Clock Board, Threshold Board, Storage Controller
Board, and then finally back to the Board Level Error/Pass Display.
If for example, you wish to view
do the fo Ilow i ng steps:
information about Data Board A,
1. Press the DATA key to display the Board list and total Error count.
2. Press the NEXT key to display the Board list and total Pass count.
3. Press the down arrow key and press the NEXT key twice to display the Data
Board
A Subtest Pass count.
5-9
4. Press the up arrow key and then the NEXT key to display the Data Board
A Subtest Error count.
5. Press the PREVIOUS key to return to the previous Menu.
DIAGNOSTIC RE-INITIALIZATION AND DIAGNOSTIC EXIT TO SYSTEM
General
When the Diagnostic Modules are executed, the Pass/Fai I information
is accumulated; pressing the DATA key wi I I display this information.
If a "fresh" start of the Diagnostic is desired, with the Pass/Error
information set to 0, this can be achieved by entering the Main Menu by
pressing the PREVIOUS key, and then pressing the PREVIOUS key again. This wi I I
set up the default Parameters, and set al I Pass/Error information to O.
NOTE: Be careful using the PREVIOUS key whi Ie in Main Menu, as it would
be easy to re-initialize the Diagnostic by accident, and lose al I the
Pass/Error information that was accumulated.
Exiting the Diagnostic
When the K205 Logic Analyzer is powered on, it goes through its power
on Diagnostics and comes up in the Default Menu. Whi fe in this menu, if you
press the "F2" key, the power on diagnostics are repeated.
Whi Ie the K205 Diagnostic Operating System is under Execution, it is
possible to exit back to the Default Menu of the Logic Analyzer. This is done
by pressing the "F2" key three consecutive times. This wi I I cause any
Diagnostic execution to be aborted, and the K205 wi I I go through the power on
diagnostics and come up in the Default Menu.
Pressing the "F2" key three consecutive times has the same effect as
powering off the K205, and then powering it back on, without the need to remove
the Floppy Diskettes.
NOTE: The "F2" key must be pressed three consecutive times to avoid an
accidental exit from the Diagnostic Operating System. Any other keys pressed
between the three "F2" keys voids out the exit.
5-10
SUMMARY OF K205 DIAGNOSTIC OPERATING SYSTEM KEYS
The K205 Diagnostic wi II recognize the fol lowing keys:
Key
Menu or Execution
Function
NEXT
Main Menu
Subtest Menu
HALTED ON ERROR
Parameter Menu
Pass/Error Display
Execute Diagnostic.
Execute Diagnostic.
Resume Diagnostic execution.
Change selected option.
Change Error display to Pass display,
Cycle through Subtest lists.
PREVIOUS
Main Menu
Subtest Menu
Parameter Menu
Pass/Error Display
Re-initial ize Diagnostic.
Return to Main Menu.
Return to previous Menu or execution.
Return to previous Menu or execution.
EDIT
Any Menu or execution
Display the Parameter options.
DATA
Any Menu or execution
Display the Pass/Error information.
STOP
Any execution
HALTED ON ERROR
Abort current test.
Abort current test.
FIELD (arrows)
Main Menu
Subtest Menu
Parameter Menu
Pass/Error Display
Activate/Inactivate a Board, or
Select a Board for testing.
Select a Single Test or all Tests.
Select a parameter.
Change fields for Errors/Passes,
or cycle through al I Subtest lists.
CONTROL
Looping on Error
Skip out of current Subtest and
proceed to the next Subtest.
F2
Any Menu or execution
Three consecutive key-strokes causes
an EXIT from the Diagnostics and cold
starts the K205 Logic Analyzer.
5-11
K205 KEYBOARD/DISPLAY BOARD DIAGNOSTIC
DIAGNOSTIC OVERVIEW
This section describes subtests that are executed on the K205 keyboard/
display board, how error reporting is done, and the concept behind each
subtest program.
There are eight subtests written for the keyboard/ display board. Each of
the subtests are described individually on the pages which fol low. Loop on
error, error count, and pass count update are incorporated into each subtest.
Detai Is for selecting the various test options and parameters for control ling
the diagnostic monitor are described in the Introduction for Chapter 5.
AI I Error Messages are preceded by a
">" prefix.
"*"
whi Ie Information Messages use the
Early exit of each subtest Is accompl ished by pressing the "STOP" key.
ASSUMPTIONS
This series of tests assumes that the fol lowing boards are Installed and
are operational:
1. MPU
2. Threshold/GPIB/RS-232
3. Clock
4. Control
SUBTEST CATEGORIES
1-
2.
3.
4.
5.
6.
7.
8.
Keyboard Test
Interrupt Controller (8259) Test
Clock/Calendar (5832) Test
Video RAM Data Test
Video RAM Address Test
6116 RAM Data Test
6116 RAM Address Test
Beeper Exercise
ERROR COUNT CATEGORIES
1-
2.
3.
4.
5.
6.
7.
8.
Subtest
Subtest
Subtest
Subtest
Subtest
Subtest
Subtest
Subtest
1
2
3
4
5
6
7
8
Error
Error
Error
Error
Error
Error
Error
Error
Count
Count
Count
Count
Count
Count
Count
Count
5-12
Keyboard/Display Diagnostic Subtest 1
TITLE:
KEYBOARD TEST
TARGET LOGIC:
8E, 14E, 13E, 10E and keyboard interface matrix
PURPOSE: The keyboard logic is functionally tested by pressing a specified
key on the front panel, reading the corresponding I/O port from buffer (10E),
and then verifying the key data to the expected data.
TEST DESCRIPTION: There are 48 keys on the front panel; the corresponding
I/O Port, lxh are arranged as fol lows:
a.
b.
c.
d.
e.
f.
h.
i•
x=O
x=2
x=4
x=6
x=8
x=a
x=c
x=e
if
if
if
if
if
if
if
if
key
key
key
key
key
key
key
key
is
is
is
is
is
is
is
is
at
at
at
at
at
at
at
at
located
located
located
located
located
located
located
located
col umn
column
col umn
col umn
column
col umn
col umn
co I umn
1
2
3
4
in
in
in
in
5 in
6 in
7 in
8 in
the
the
the
the
the
the
the
the
front
front
front
front
front
front
front
front
panel
panel
panel
panel
panel
panel
panel
pane I.
There are 6 key data read from the buffer (10e),theyare arranged as fo II ows:
a.
b.
c.
d.
e.
f.
the
the
the
the
the
the
key
key
key
key
key
key
data
data
data
data
data
data
read=feh
read=fdh
read=fbh
read=f7h
read=efh
read=dfh
f
f
f
f
f
f
the
the
the
the
the
the
key
key
key
key
key
key
s
s
s
s
s
s
located
located
located
located
located
located
at
at
at
at
at
at
row
row
row
row
row
row
1 in the front panel
2 in the front panel
3 in the
4 in the
5 in the
6 in the
front
front
front
front
panel
panel
panel
panel
The fol lowing information message is displayed before each key is tested:
>Press key labeled: ?????????????
Where ?????????1??? could be 1 character, for example, "0" through "9",
"a" through "f", or up to 13 characters, for example, "TRACE CONTROL" in
the domain of 48 defined keys.
TEST STEP INFORMATION:
Test Step
1
2
3
4
5
6
7
8
9
10
11
Key Tested
NEXT
PREVIOUS
FORMAT
CLOCKS
TRACE CONTROL
ARM MODE
UP ARROW
LEFT ARROW
MEM A
DATA
TIMING
5-13
Test Step
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Key Tested (cont'd)
GRAPH
RIGHT ARROW
DOWN ARROW
MEM B
A->B
SEARCH
COMPARE
CONTROL
REF
C
8
4
0
SHIFT
HELP
0
9
5
1
I/O
"X"
E
A
6
2
EDIT
INS
F
B
7
3
ARM
STOP
F1
F2
F3
F4
ERROR MESSAGE:
If a key data error occurs, the fol lowing message is displayed:
*Test FAILED--Test Step
ss
Keyboard Error
Expected Keycode
= eeh
= ddh
Keycode Found
Key Data Code Read = "?????????????"
where ss should be 1 through 48
ee should be 1 through 48
dd should be be 1 through 48
5-14
Keyboard/Display Diagnostic Subtest 2
INTERRUPT CONTROLLER TEST
TITLE:
PURPOSE:
The interrupt logic is functionally tested by selecting each
interrupt on the 8259 controller and causing each interrupt to occur.
As each interrupt is generated, the 8259 receives the interrupt then
outputs a vector for the 8086 processor. At these vectors are routines
which set diagnostic flags. These flags are examined to determine if the
interrupt actually took place. The source of the interrupts are then turned
off, and the flags are cleared. After a smal I amount of time the flags are
re-examined to determine if the source of the interrupt has actually been
disabled. If a flag is found to be set then an error message is displayed.
TARGET LOGIC:
4E, 2E, 8E, 10E, 90, and 100
TEST DESCRIPTION: The fol lowing table indicates the
line for the diagnostic test step:
interrupt source and
TEST STEP INFORMATION:
Test Step
Interrupt from
On Board
GPIB
Threshold
RS-232
Threshold
AUX
Threshold
Total trace
Clock
time clock
(timer NO)
(Simulated from software)
Time of day
Display
Disk
Storage
Control Ier
1
2
3
4
5
6
7
Interrupt Line
intr
intr
intr
intr
1
2
3
4
not currently assigned
intr 6
intr 7
ERROR MESSAGE:
If an error occurs, the fol lowing messages are displayed:
*Test FAILED--Test Step
Intr Oz Not Generated.
where z
=
z
1 - 7
*Test FAILED--Test Step
z
Unexpected Interrupt Oz Generated.
where z
=1
- 7
5-15
Keyboard/Display Diagnostic Subtest 3
TI TLE:
CLOCK/CALENDAR TEST
PURPOSE: This subtest verifies operation of the 5832 clock/calendar by
saving the current time, then exercising the component by setting the time.
The time Is then read back and verified. If test Is successful, It Indicates
the 5832 Is operating properly.
The time is set so the next second time Interval causes a rollover.
An example of a rol lover is If the minutes counter was set to 59. When
minutes are advanced then the minutes counter becomes zero and the hours
count is incremented by one. This rol lover process continues untl I the years
counter rol Is over to 00 (from 99).
TARGET LOGIC:
2D, 2E, 3D, 4D, 5D and 7D
TEST DESCRIPTION:
Operations are exercised on the clock calendar
components according to the fol lowing table:
TEST STEP INFORMATION:
Test Step
Operation
1---------------Read current time, save for last step
2 ------------- Set clock to: Jan. 1, 1900 @OO:OO:OO
Using test feature on 5832 simulate
60 seconds.
Read time:
Compare to:
Jan. 1, 1900 @00:Ol:00
3 ------------- Set clock to: Jan. 1, 1900 @00:59:00
Using test feature on 5832 simulate
60 seconds.
Read time:
Compare to:
Jan. 1, 1900 @01:00:00
4 ------------- Set clock to: Jan. 1, 1900 @23:59:00
Using test feature on 5832 srmulate
60 seconds.
Read time:
Compare to:
5-16
Jan. 2, 1900 @OO:OO:OO
Test Step
Operation (cont'd)
5 ------------- Set clock to: Jan. 31, 1900 @23:59:00
Using test feature on 5832 simulate
60 seconds.
Read time:
Compare to:
Feb. 1, 1900 @OO:OO:OO
6 ------------- Set clock to: Dec. 31, 1900 @23:59:00
Using test feature on 5832 simulate
60 seconds.
Read time:
Compare to:
Jan. 1, 1901 @OO:OO:OO
7 ------------- Set clock to: Dec. 31, 1999 @23:59:00
Using test feature on 5832 simulate
60 seconds.
Read time:
Compare to:
Jan. 1, 1900 @OO:OO:OO
NOTE: Exiting this test via the STOP key restores the time saved in
step 1. If power is removed during steps 2 - 7, the time is lost.
ERROR MESSAGE:
If the time read does not match the time expected, the fol lowing error
message is displayed:
*Test FAILED--Test Step
Clock/Calendar Error
year month day hour
Expected: aaa bbb
cce ddd
Read: ggg hhh
iii j j j
where aaa, 999
bbb, hhh
eee, iii
ddd, j j j
eee, kkk
fff, III
=
=
=
=
=
=
x
minute
eee
kkk
000 - 999
001
012
001
031
000
023
000 - 059
000
059
5-17
second
fff
III
Keyboard/Display Diagnostic Subtest 4
VIDEO RAM DATA TEST
TITLE:
PURPOSE: This subtest verifies that the Keyboard/Display Board does not
prevent normal operation of the MPU RAM dedicated to video display.
7A, 7B, 7C, 8A, 8B, 8C, 9A, 9B, 9C, 10A and lOB
dedicated RAM on MPU Board used for video
TARGET LOGIC:
TEST DESCRIPTION: Although the RAM under test is on the MPU Board, the
Display Board uses this memory to create an image sent to the screen. Various
data patterns are written to the MPU memory and read back.
The data written
is compared to the data read and if a miscompare is detected an error message
is displayed. This continues unti I al I the data patterns listed below have
been tried.
TEST STEP INFORMATION:
Test Step
Value Written
OOH
AAH
1
2
3
55H
4
CCH
5
33H
6
7
8
9
01H
02H
04H
08H
10H
20H
40H
BOH
10
11
12
13
NOTE:
This memory physically starts at location 0100h
ERROR MESSAGE:
If an error occurs during this subtest the fol lowing message is displayed:
* Test FAILED--Test step
RAM Data Error
Value Written = aaH
Value Read
= bbH
Address Count = ccccH
where
aa
bb
cccc
= 00 = 00 = 0000
xx
FF
FF
- 3FFF
5-18
Keyboard/Display Diagnostic Subtest 5
VIDEO RAM ADDRESS TEST
TITLE:
PURPOSE:
This subtest verifies that the Keyboard/Display Board does not
prevent normal operation of the MPU RAM dedicated to video display.
TARGET LOGIC:
7A, 7B, 7C, 8A, 8B, 8C,9A, 9B, 9C, t OA and t OB
RAM located on MPU Board used for video,
TEST DESCRIPTION:
AI I of the RAM in this test is preset to zero then the
indicated.address is written with the value Oaah. AI I of the RAM is then read
to verify that the indicated address is the only data element that was set to
Oaah.
TEST STEP INFORMATION:
Test Step
OOOOH
0001H
0002H
0004H
000811
OOtOH
0020H
0040H
0080H
0100H
0200H
0400H
1
2
3
4
5
6
7
8
9
10
11
12
NOTE:
Indicated Address
This memory physically starts at location OtOOh
ERROR MESSAGE:
If an error occurs during this subtest, the following message is displayed:
* Test FAILED--Test Step
RAM Data Error
Value Written = aah
Value Read
= bbh
Address Count = cccch
where
xx
= 00
- ff
- ff
cccc = 0000 - 3fff
aa
bb
= 00
5-19
Keyboard/Display Diagnostic Subtest 6
TITLE:
6116 RAM DATA TEST
PURPOSE:
Thissubtest verifies operation and integrity of the 6116 RAMs
on the keyboard/display board by writing to the memory several different
data patterns; This memory is then read back and compared to the value
written. If a miscompare occurs then an error message is displayed.
This process is repeated for al I of the 6116 memory until al I the patterns
listed below have been tried.
TARGET LOGIC:
18, 38, 3C, 4C, 58, 68, 5E, 6E, 5C and 6D
TEST DESCRIPTION:
The fol lowing is a summary of the data written to the
RAM during each test step:
TEST STEP INFORMATION:
Test Step
Value Written
1
OOH
2
AAH
355H
4
CCH
5
. 33H
6
01H
7
02H
8
04H
9
08H
10
10H
11
20H
12
40H
13
80H
NOTE:
This memory physically starts at location 040000h
ERROR MESSAGE:
If an error occurs during this subtest, the fol lowing message is displayed:
* Test FAILED--Test Step
RAM Data Error
Value Written = aaH
Value Read
= bbH
Address Count = ccccH
where
aa
bb
cccc
xx
00 - FF
00 - FF
= 0000 - 3FFF
=
=
5-20
Keyboard/Display Diagnostic Subtest 7
TITLE:
6116 RAM ADDRESS TEST
PURPOSE: This subtest verfies the operation and integrity of the 6116 RAMs
on the keyboard/display board. AI I of the RAM in this test is preset to zero
then the indicated address is written with the value Oaah. AI I of RAM is then
read to verify that the indicated address is the only data element that was
set to Oaah.
TARGET LOGIC:
18, 38, 3C, 4C, 58, 68, 5E, 6E, 5C and 60
TEST DESCRIPTION: AI I RAM is preset to zero, then the indicated address
is written with the value Oaah. All of RAM is then read to verify the written
data.
TEST STEP INFORMATION:
Indicated Address
Test Step
OOOOH
0001H
0002H
0004H
0008H
0010H
0020H
0040H
0080H
0100H
0200H
0400H
1
2
3
4
5
6
7
8
9
10
11
12
NOTE:
This memory physically starts at location 040000h
ERROR MESSAGE:
If an error occurs during this subtest, the following message is displayed:
* Test FAILED--Test step
RAM Data Error
Value Written = aaH
Value Read
= bbH
Address Count = ccccH
where
aa
bb
cccc
= 00
xx
- FF
FF
- 3FFF
= 00 = 0000
5-21
Keyboard/Display Diagnostic Subtest 8
TITLE:
BEEPER EXERCISE TEST
PURPOSE: This subtest exercises the beeper circuitry. there are no error
messages generated by this routine as there is no way to verfy operation
except via audio monitoring.
TARGET LOGIC:
15E, 16E, 17E and 18E
TEST DESCRIPTION: The beeper is activated by loading pO-p3 on IC with the
duration value, then the line labeled cp is pulsed. The beeper is set
various durations as given in the fol lowing table:
to
TEST STEP INFORMATION:
Test Step
1
25
Duration
.1 sec
1.5 sec
ERROR MESSAGE:
There are no error messages for this subtest •. Also note that since no errors
are possible, "loop on error" and "haolt on error" do not function.
5-22
K205 DATA BOARD DIAGNOSTIC
DIAGNOSTIC OVERVIEW
This section describes subtests that are performed by the K205 Data Board
Diagnostic. The target hardware is presented, as wei I as a general description
of each subtest, a list of information for each test step, and a description
of Error Messages that may be printed for the subtest results.
The K205 Data Board Diagnostic is a board level test of the board operations
that run under the K205 Diagnostic Operating System. The diagnostic can
test from 1 to 3 Data Boards in the system. These correspond to Data Boards
A, Band C. In order for the Diagnostic to run properly, the board under test
must be instal led on the Mother Board, (not on an extender card). The internal
probe input cables must be connected to Jl and J2, and the external probes
instal led. AI I of the channels of al I probes must be free from connection to
anything (i.e. they must be al lowed to float). Also, al I of the other boards
must be instal led in the K205 system.
NOTE: The internal probe input cables are too short for the board to
be instal led on an extender card. If extension cables are used, then an
extender card may be used.
Several of the subtests use a sequence of 24 Data patterns to write,
read and verify an I/O port or Memory Address. These Data patterns verify
that al I 16 Data Bits are functional and completely independent of each other.
These 24 Data patterns are as fol lows:
OOOOH, 5555H, AAAAH, CCCCH, 3333H, 6666H, 9999H, FFFFH,
000lH, 0002H, 0004H, 0008H, 0010H, 0020H, 0040H, 0080H,
0100H, 0200H, 0400H, 0800H, 1000H, 2000H, 4000H, 8000H.
When writing these Data patterns to an I/O port such as the Sample Register
or the Pipeline Registers, the Data value can be randomly accessed. The ECl
RAM Memory on the other hand is essentially a 512 byte FIFO. AI I 512
locations a~e accessed at the same I/O address, (i.e. OC6H for writes, and
OCOH for reads). The RAM's addressing is accomplished by sequential reads from,
or writes to the RAM. Address counters on the board are incremented each time
a RAM access (i.e. a Sample Clock) occurs.
The RAM actually requires 515 Sample clocks to get 512 words of data to the
RAM. The three extra clocks are required to get the Data through the pipeline.
After the 512th clock, the 512th Data value resides in the Sample Register.
One more clock shifts it to the New Pipe Register. An additional clock shifts
it to the Old Pipe Register, and the last clock writes it to RAM.
NOTE: When an I/O address is specified for explanation, the addresses for
Data Board A are used. These addresses would only apply if Data Board A was
being tested. Data Board B addresses are ODxH, and Data Board Care OExH.
5-23
SUBTEST CATAGORIES
There are thirteen Subtests that are performed by the Data Board Diagnostic.
These are categorized as fol lows:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
Force Conditions Test
Data Path Test
Clocking Disable Test
Latch Bits 0-7 Test
Latch Bits 8-F Test
Glitch Bits 0-7 Test
Glitch Bits 8-F Test
Multiplex Select Test
Pipeline Shift Test
RAM Data Integrity
RAM Addr Integrity
Trace Conditions Test
Recirculate RAM Test
ERROR COUNT CATEGORIES
The Error Count Display information is a one for one match with the Subtest
list above. The K205 Diagnostic Operating System wi II display the "Subtest n"
instead of the actual test name.
Subtest
Subtest
Subtest
Subtest
Subtest
Subtest
Subtest
Subtest
Subtest
Subtest
Subtest
Subtest
Subtest
1
2
3
4
5
6
7
8
9
10
11
12
13
(Force Conditions Test)
,
of the Clock Board.
The majority of the subsequent subtests use this Data Path to exercise various
features and functions of the Data Board. So if there are any errors in this
test, there are bound to be many failures that fol low.
TEST STEP INFORMATION:
Step
Data
Data Written to
1
OOOOH
5555H
AAAAH
CCCCH
3333H
6666H
9999H
FFFFH
0001H
0002H
0004H
0008H
0010H
0020H
0040H
0080H
0100H
0200H
0400H
0800H
tOOOH
2000H
4000H
8000H
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
Data Verified at
---------------------------------------------------------------------
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
2t
22
23
24
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
D agnostic
o agnostic
D agnostic
D agnostic
o agnostic
D agnostic
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
5-27
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
Samp e
Samp e
Samp e
Samp e
Samp e
Samp e
Samp e
Samp e
Samp e
Samp e
Samp e
Samp e
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Reg i ster
Regi ster
Register
Register
Regi ster
Register
Reg ster
Reg ster
Reg ster
Reg ster
Reg ster
Reg ster
Reg ster
Reg ster
Register
Register
Reg ster
Reg ster
Reg ster
Reg ster
Reg ster
Reg ster
Reg ster
Reg ster
ERROR MESSAGES:
If an error occurs, the fol lowing message is displayed:
* Test FAILED--Test step ssss
Data Path Diag to Sample Reg Error
I/O Address
= aaaaH
Data Read
= rrrrH
Data Expected
= eeeeH
Error Bit Map
= OOOOOOOOOOOOOOOOB
Board Status X8 = iiiiH
Where:
ssss is the test step number in the range of 1 to 24.
aaaa
15 the I/O address of the Data Board:
OC6H for Data Board A Sample Register,
OD6H for Data Board B Sample Register,
OE6H for Data Board C Sample Register.
rrrr
is the Data Word read from the Data Board.
eeee
is the Data Word Expected from the Data Board.
iii i
is the Status information from the current Data Board under test.
NOTE: The Error Bit Map is a map of the Data Bus, DO -015, and is an
exclusive OR of the Data Read and the Data Expected. Any bits that are
different show up as a "1". Bits that show up as a "0" passed the compare.
5-28
Data Board Diagnostic Subtest 3
TITLE:
CLOCK DISABLE TEST
TARGET LOGIC:
5K 8J 6J 5L
6H 5A 6A 8A 9A
AI I Logic listed in Subtest 2
TEST DESCRIPTION:
This subtest checks the different ways of clocking the Data Board, and the
different ways of disabling the clocking.
In Single Phase Mode the Sample Clock, Pl-42 is used for al I clocking
on the Data Board. If the Multiphase Mode is selected, the Sample Clock, Pl-42
is used for the Sample Register, and the Control Clock, Pl-46 is used for the
RAM, Pipelines and Address Counters.
A Condition called "Force Clocks" wi II cause all Sample Clocks and all
Control Clocks to be ignored. Also a condition cal led "Halted" wi I I disable
these clocks.
This test also checks the Address Reset--Memory Ful I function. The address
counters are reset by toggling W4B12. The Memory is "fil led" by clocking the
address counters 512 times.
TEST STEP INFORMATION:
Step
Mode of Phase
Force Clocks
Data Expected
1
2
Single Phase
Multi Phase
Single Phase
Multi Phase
inactive
inactive
active
active
5555H
AAAAH
OOOOH
OOOOH
"HALTED/"
MEMORYFULL
Status
high
low
low
high
000lH
0004H
Step
Mode of Phase
Force Clocks
Halt When Full
Data Expected
7
Single Phase
i nact i ve
active
OOOOH
3
4
Step
5
6
5-29
ERROR MESSAGES:
If an error occurs, the fol lowing message is displayed:
* Test
FAILED--Test step
ssss
hmsg
I/O Address
= aaaaH
Data Read
= rrrrH
Data Expected
= eeeeH
Error Bit Map
= OOOOOOOOOOOOOOOOB
Board Status X8 = iiilH
. Where:
ssss Is the test step number In the range of 1 to 7.
hmsg
Is the Error heading message:
Force Clocks Enable Data move Error,
Force Clocks Disable Data move Error,
155 En2 Memory Not Ful I Status Error,
155 En2 Mem-Fu II /Ha It Status Error,
Halt Freeze Sample Register Error.
aaaa
is the I/O address of the Data Board:
OC6H for Data Board
OC8H for Data Board
OD6H for Data Board
OD8H for Data Board
OE6H for Data Board
OE8H for Data Board
A Sample
A Status
B Sample
B Status
C Sample
C Status
Register,
Register,
Register,
Register,
Register,
Register.
rrrr
Is the Data Word read from the Data Board.
eeee
is the Data Word Expected from the Data Board.
illl
Is the Status Information from the current Data Board under test.
NOTE: The Error Bit Map is a map of the Data Bus, DO - 015, and Is an
exclusive OR of the Data Read and the Data Expected. Any bits that are
different show up as a "1". Bits that show up as-a "0" passed the compare.
5-30
Data Board Diagnostic Subtest 4
TITLE:
LATCH DATA BITS 0-7 TEST
TARGET LOGIC:
5F
5L
2H lH 4H 3H llH 10H 13H 12H
Diagnostic Latch Clock
Pl-44 (From Clock Board)
All hardware used in Data Path Test •
. TEST DESCR IPT ION:
This tests. the latch mode of 10130 latches of the lower a bits,
with the upper eight bits in transparent mode. The Latch Clock 0-7 feeds
the common Enable input to the 10130's. This input is held high, and
pulsed low to latch the current data from the "D" to the "Q". The Glitch
is disabled so the other Enable input is held low. The upper bits 8-F are not
latched, the Data slips through the "0" to the "Q~.
If there are any errors in this test, but the Data Path Test passed,
the failure is probably in the Latch Clock or the 10130's.
TEST STEP INFORMATION:
Step
Data
Data Written to
1
2
3
4
5
6
7
a
9
10
11
12
13
14
15
16
OOOOH
5555H
AAAAH
CCCCH
3333H
6666H
9999H
FFFFH
0001H
0002H
0004H
OOOaH
0010H
0020H
0040H
OOaOH
0100H
0200H
0400H
OaOOH
1000H
2000H
4000H
8000H
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
Data Verified at
---------------------------------------------------------------------
17
18
19
20
21
22
23
24
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
Samp e
Samp e
Samp e
Samp e
Samp e
Samp e
Samp e
Samp e
Samp e
Samp e
Samp e
Samp e
Samp e
Samp e
Samp e
Samp e
Samp e
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Reg ster
Reg ster
Reg ster
Reg ster
Reg ster
Reg ster
Reg ster
Reg ster
ERROR MESSAGES:
If an error occurs, the fol lowing message is displayed:
* Test FAILED--Test Step ssss
Latch Data bits 0-7 Error
I/O Address
= aaaaH
Data Read
= rrrrH
Data Expected
= eeeeH
Error Bit Map
= OOOOOOOOOOOOOOOOB
Board Status X8 = iiiiH
Where:
ssss is the test step number in the range of 1 to 24.
aaaa
is the I/O address of the Data Board:
OC6H for Data Board A Sample Register,
OD6H for Data Board B Sample Register,
OE6H for Data Board C Sample Register.
rrrr
is the Data Word read from the Data Board.
eeee
is the Data Word Expected from the Data Board.
iii I
is the Status information from the current Data Board under test.
NOTE: The Error Bit Map is a map of the Data Bus, DO - D15, and is an
exclusive OR of the Data Read and the Data Expected. Any bits that are
different show up as a "1". Bits that show up as a "0" passed the compare.
5-32
Data Board Diagnostic Subtest 5
TITLE:
LATCH DATA BITS 8-F TEST
TARGET LOGIC:
5F
5L
2H 1H 4H 3H 11H 10H 13H 12H
Diagnostic Latch Clock
Pl-44 (From Clock Board)
AI I hardware used in Data Path Test.
TEST DESCRIPTION:
This subtest is identical to the previous test except that the upper
Data bits 8-F are tested instead of the lower bits 0-7.
The test verifies the latch mode of 10130 latches the upper 8 bits,
with the lower eight bits in transparent mode. The Latch Clock 8-F feeds
the common Enable input to the 10130's. This input is held high, and
pulsed low to latch the current data from the "D" to the "Q". The Glitch
Is disabled so the other Enable input is held low. The lower bits 0-7 are not
latched, the Data sl ips through the "D" to the "Q".
If there are any errors in this test, but the Data Path Test passed,
the fai lure is probably in the Latch Clock or the 10130's.
TEST STEP INFORMATION:
Step
Data
Data Written to
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
OOOOH
5555H
AAAAH
CCCCH
3333H
6666H
9999H
FFFFH
0001H
0002H
0004H
0008H
0010H
0020H
0040H
0080H
0100H
0200H
0400H
0800H
1000H
2000H
4000H
8000H
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
D agnostic
D agnostic
D agnostic
D agnostic
D agnostic
D agnostic
D agnostic
D agnostic
D agnostic
D agnostic
D agnostic
D agnostic
D agnostic
D agnostic
D agnostic
DIagnostic
Diagnostic
Diagnostic
Diagnost c
Diagnost c
Dlagnost c
Diagnost c
Diagnost c
Diagnost c
Data Verified at
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
5-33
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Samp e
Samp e
Samp e
Samp e
Samp e
Samp e
Samp e
Samp e
Samp e
Samp e
Samp e
Samp e
Samp e
Samp e
Samp e
Samp e
Samp e
Register
Register
Register
Register
Register
Register
Reg ster
Reg ster
Reg ster
Reg ster
Reg ster
Reg ster
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
ERROR MESSAGES:
If an error occurs, the fol lowing message is displayed:
* Test FA ILEO--Test Step ssss·
Latch Data bits 8-F Error
I/O Address
= aaaaH
Data Read
= rrrrH
Data Expected = eeeeH
Error Bit Map
= OOOOOOOOOOOOOOOOB
Board Status X8 = iii i H
Where:
ssss is the test step number in the range of 1 to 24.
aaaa
is the .1/0 address of the Data Board:
OC6H for Data Board A Sample Register,
OD6H for Data Board B Sample Register,
OE6H for Data Board C Sample Register.
rrrr
is the Data Word read from the Data Board.
eeee
is the Data Word Expected from the Data Board.
illi
is the Status information from the current Data Board under test.
NOTE: The Error Bit Map is a map of the Data Bus, DO - 015, and is an
exclusive OR of the Data Read and the Data Expected. Any bits that are
different show up as a "1". Bits that show up as a "0" passed the compare.
5-34
Data Board Diagnostic Subtest 6
TITLE:
GLI TCH DATA BI TS 0-7 TEST
TARGET LOGIC:
2E 1E 2F 1F
4E 3F 4F 3E
11 E 1OE 11 F 1OF
13E 12F 13F 12E
2H lH 4H 3H
l1H 10H 13H 12H
All hardware in the Data Path Test.
TEST DESCRIPTION:
This subtest tests the Glitch capture feature of the Data boards by enabling
the Glitch circuitry which uses the "Set" and "Reset" pins on the 10130's,
instead of the "0" inputs to send the Data from th~ 10121 Multiplexers to the
"Q" output. The individual Enable pins on the 10130's are held high so that
any "clocking" from the Diagnostic Latch Clock is disabled. (No effect).
Each output instruction to the Diagnostic bits port OC6H, latches the
Data in the Glitch latches. A Sample Clock is required to send the Data through
to the Sample Register. A maximum cf two Data values may be output to the
Diagnostic bits port before data overrun occurs.
The way that this circuitry is tested, is two consecutive Output
instructions are performed with different Data. The first Data is checked at
the Sample register after Issuing a single Sample Clock. Another Sample Clock
wi I I present the Second Data to the Sample Register.
In this test, only Data bits 0-7 are in the Glitch Mode. The upper bits
8-F slip through the 10130's because both of the enable pins are low,
so "Q" fo I lows "0".
TEST STEP INFORMATION:
step
1st Data
2nd Data
Step
1st Data
2nd Data (cont'd)
12
0004H
0008H
0010H
0020H
0040H
0080H
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
13
14
15
16
17
18
19
20
21
22
23
24
25
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
ERROR MESSAGES:
If an error occurs, the fol lowing message is displayed:
* Test FAILED-~Test Step ssss
Glitch Data Bits 0-7 Error
I/O Address
= aaaaH
Data Read
= rrrrH
Data Expected
= eeeeH
Error Bit Map
= OOOOOOOOOOOOOOOOB
Board Status X8 = iiliH
Where:
ssss is the test step number in the range of 1 to 25.
aaaa
is the I/O address of the Data Board:
OC6H for Data Board A Sample Register,
OD6H for Data Board B Sample Register,
OE6H for Data Board C Sample Register.
rrrr
is the Data Word read from the Data Board.
eeee
is the Data Word Expected from the Data Board.
iiii
is the Status Information from the current Data Board under test.
NOTE: The Error Bit Map is a map of the Data Bus, DO - D15, and is an
exclusive OR of the Data Read and the Data Expected. Any bits that are
different show up as a "1". Bits that show up as a "0" passed the compare.
5-36
Data Board Diagnostic Subtest 7
TITLE:
GLITCH DATA BITS
TARGET LOGIC:
8-F TEST
2E lE 2F IF
4E 3F 4F 3E
11 E 1OE 11 F 1OF
13E 12F 13F 12E
2H lH 4H 3H
11 H 1OH 13H 12H
All hardware in the Data Path Test.
TEST DESCRIPTION:
This subtest is simi lar to the Glitch Data Bits 0-7 except the upper bits are
being tested.
This subtest checks the Glitch capture feature of the Data boards by enabling
the Glitch circuitry which uses the "Set" and "Reset" pins on the 10130's,
instead of the "0" inputs to send the Data from the 10121 Multiplexers to the
"Q" output. The individual Enable pins on the 10130's are held high so that
any "clocking" from the Diagnostic Latch Clock is disabled. (No effect).
Each output instruction to the Diagnostic bits port OC6H, latches the Data in
the Glitch latches. A Sample Clock is required to send the Data through
to the Sample Register. A maximum of two Data values may be output to the
Diagnostic bits port before data overrun occurs.
The way that this circuitry is tested, is two consecutive Output instructions
are performed with different Data. The first Data is checked at the Sample
register after issuing a single Sample Clock. Another Sample Clock presents
the Second Data to the Sample Register.
In this test, only Data bits 8-F are in the Glitch Mode. The lower bits
0-7 slip through the 10130's because both of the enable pins are low,
so "Q" fo I lows "0".
TEST STEP INFORMATION:
Step
1
2
3
4
5
6
7
8
9
1st Data
2nd Data
OOOOH
OOOOH
5500H
AAOOH
CCOOH
3300H
6600H
9900H
FFOOH
-----OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
5-37
Step
1st Data
2nd Data (Cont'd)
10
11
12
13
14
15
16
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
0100H
0200H
0400H
0800H
1000H
2000H
4000H
8000H
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
---------------------------------
17
18
19
20
21
22
23
24
25
ERROR MESSAGES:
If an error occurs, the fol lowing message is displayed:
* Test FAILED--Test Step ssss
Glitch Data Bits 8-F Error
I/O Address
= aaaaH
Data Read
= rrrrH
Data Expected
= eeeeH
Error Bit Map
= OOOOOOOOOOOOOOOOB
Board Status X8 = iiiiH
Where:
ssss is the test step number in the range of 1 to 25.
aaaa
is the I/O address of the Data Board:
OC6H for Data Board A Sample Register,
OD6H for Data Board B Sample Register,
OE6H for Data Board C Sample Register.
rrrr
is the Data Word read from the Data Board.
eeee
is the Data Word Expected from the Data Board.
iiii
is the Status information from the current Data Board under test.
NOTE: The Error Bit Map is a map of the Data Bus, DO - D15, and is an
exclusive OR of the Data Read and the Data Expected. Any bits that are
different show up as a "1". Bits that show up as a "0" passed the compare.
5-38
Data Board Diagnostic Subtest 8
TITLE:
PROBES/MULTIPLEX TEST
TARGET LOGIC:
8F
2B lB 4B 3B llB lOB 13B 12B
20 10 2C lC 40 3C 4C 3D
110 100 llC 10C 130 12C 13C 120
Jl, J2, Internal Probe Cables, External Probe Cables
AI I of the hardware in the Data Path Test.
TEST DESCRIPTION:
This subtest checks the five Multiplexing Select Modes of the Data Board.
The five modes are:
1. "NORMAL" mode. This samples the logic state at the inputs of Jl
and J2. This logic state is set high or low by the external probes.
2. "DEMUX" mode. This is simi lar to the Normal Mode except the lower
eight bits are mirrored into the upper eight bits.
3. "DIAGNOSTIC" select. This reads the Diagnostic bits Register.
4. "MEMORY" select. This reads the data that is currently residing
in the ECL Memory, (Manual Recirculate>.
5. NOTHING SELECTED. With al I four select lines disabled, the Data
lines should be pul led up to read OFFFFH.
This subtest requires the use of a known good Threshold Board and the
installation of the external probes. The Normal Mode and the Demux Mode use the
Threshold board to set different thresholds at the hybrid circuit in the probes.
TEST STEP INFORMATION:
Step
1
2
3
4
5
6
7
8
9
Data Expected
Multiplex
Lower Threshold
Upper Threshold
FFFFH
OOOOH
OOFFH
FFFFH
OOOOH
FFFFH
F069H
5AC3H
FFFFH
Normal
Normal
Normal
Demux
Demux
Demux
Diagnostic
Memory
Floating
ECL
VARIABLE A
ECL
ECL
VARIABLE A
ECL
ECL
VARIABLE
VARIABLE
ECL
VARIABLE
VARIABLE
------------
-----------------------
5-39
A
A
A
A
-------------------------------------
ERROR MESSAGES:
If an error occurs, the following message is displayed:
*
Test FAILED--Test Step
ssss
hmsg
I/O Address
= aaaaH
Data Read
= rrrrH
Data Expected = eeeeH
Error Bit Map = OOOOOOOOOOOOOOOOB
Board Status X8 = iiiiH
Where:
ssss is the test step number in the range of 1 to 9.
hmsg
is the Error heading message:
Normal ECL Threshold Mux Error,
Normal VARA F Threshold Mux Error,
Normal ECLVARA Threshold Mux Error,
Demux ECL Threshold Mux Error,
Demux VARA F Threshold Mux Error,
Demux ECLVARA Threshold Mux Error,
Diagnostic Select Mux Error,
Memory Select Mux Error,
Multiplexer Disable-Float Error.
aaaa
is the I/O address of the Data Board:
OC6H for Data Board A Sample Register,
OD6H for Data Board B Sample Register,
OE6H for Data Board C Sample, Register.
rrrr
is the Data Word read from the Data Board.
eeee
is the Data Word Expected from the Data Board.
iiii
is the Status information from the current Data Board under test.
NOTE: The Error Bit Map is a map of the Data Bus, DO - 015, and is an
exclusive OR of the Data Read and the Data Expected. Any bIts that are
di f,ferent show up as a "1". Bits that show up as a "0" passed the compare.
5-40
Data Board Diagnostic Subtest 9
TITLE:
PIPELINES SHIFT TEST
TARGET LOGIC:
2K 1K 3K 11K 12K 13K
2L 1L 3L 4L 10K 11L 12L 13L
5K
Sample Clock Pl-42,
Control Clock Pl-46, (from Clock Board).
AI I hardware in Data Path Test.
TEST DESCRIPTION:
This test checks the Data Board Pipeline. The Pipeline consists of a
three step FILO, (first in last out), with "0" latches at each step that can
be read. The steps are cal led the "Sample Register", the "New Pipe Register",
and the "Old Pipe Register" respectively.
With each Pipel ine Clock transition, the Old Pipeline Register Data is lost
and receives its new data from the New Pipeline Register. The New Pipeline
Register receives its new data from the Sample Register. The Sample Register
receives its data from the 10130 Glitch Latches.
The Pipeline can receive it's clocking from either the Sample Clock
if "Single Phase Mode" is selected, or from the Control Clock if "Multi Phase
Mode" is selected. Test Steps 1 - 24 wi I I use the Sample Clock, and Test Steps
25 - 48 wi I I use the Control Clock.
TEST STEP INFORMATION:
Step
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Sample Data
New Pipe Data
Old Pipe Data
Mode of Phase
OOOOH
5555H
AAAAH
CCCCH
3333H
6666H
9999H
FFFFH
0001H
0002H
0OO4H
0008H
0010H
0020H
0040H
OOaOH
OOOOH
OOOOH
5555H
AAAAH
CCCCH
3333H
6666H
9999H·
FFFFH
000lH
0002H
0004H
0008H
0010H
0020H
0040H
OOOOH
OOOOH
OOOOH
5555H
AAAAH
CCCCH
3333H
6666H
9999H
FFFFH
0001H
0OO2H
0OO4H
0OO8H
0010H
0020H
S ngle
S ngle
S ngle
S ngle
S ngle
S ngle
S ngle
Single
Single
S ngle
S ngle
S ngle
S ngle
S ngle
S ngle
S ngle
5-41
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Step
Sample Data
New Pipe Data
Old Pipe Data
Mode of Phase(Cont'd)
17
18
19
20
21
22
23
24
0100H
0200H
0400H
0800H
1000H
2000H
4000H
8000H
0080H
0100H
0200H
0400H
0800H
1000H
2000H
4000H
0040H
0080H
0100H
0200H
0400H
0800H
1000H
2000H
S
S
S
S
S
ngle
ngle
ngle
ngle
ngle
S ngle
S ngle
S ngle
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
OOOOH
5555H
AAAAH
CCCCH
3333H
66.66H
9999H .
FFFFH
0001H
0002H
0004H
0008H
0010H
0020H
0040H
0080H
0100H
0200H
0400H
0800H
1000H
2000H
4000H
8000H
OOOOH
OOOOH
5555H
AAAAH
CCCCH
3333H
6666H
9999H
FFFFH
0001H
0002H
0004H
0008H
0010H
0020H
0040H
0080H
0100H
0200H
0400H
0800H
1000H
2000H
4000H
OOOOH
OOOOH
OOOOH
5555H
AAAAH
CCCCH
3333H
6666H
9999H
FFFFH
0001H
0002H
0004H
0008H
0010H
0020H
0040H
0080H
0100H
0200H
0400H
0800H
1000H
2000H
Mult
Mult
Mu t
Mu t
Mu t
Mu t
Mu t
Mu t
Mu t
Mu t
Mu ti
Mu tl
Mu tl
Mu ti
Mu ti
Mu ti
Mu ti
Mu ti
Mu ti
Mu ti
Mu ti
Mu ti
Mu ti
Mu ti
-----------------------------------------------------------------------------
ERROR MESSAGES:
If an error occurs, the fol lowing message is displayed:
* Test
FAILED--Test Step
ssss
hmsg
I/O Address
= aaaaH
Data Read
= rrrrH
Data Expected
= eeeeH
Error Bit Map
= OOOOOOOOOOOOOOOOB
Board Status X8 = iiiiH
Where:
ssss is the test step number in the range of 1 to 48.
hmsg
is the Error heading message:
Sample Clock: Old Pipe Register Error
Sample Clock: New Pipe Register Error
5-42
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
ERROR MESSAGES: (Cont'd.)
Sample Clock: Sample Register Error
Control Clock: Old Pipe Register Error
Control Clock: New Pipe Register Error
Control Clock: Sample Register Error
aaaa
is the I/O address of the Data Board:
OC2H for Data Board
OC4H for Data Board
OC6H for Data Board
OD2H for Data Board
OD4H for Data Board
OD6H for Data Board
OE2H for Data Board
OE4H for Data Board
OE6H for Data Board
A Old Pipe Register,
A New Pipe Register,
A Sample Register,
B Old Pipe Register,
B New Pipe Register,
B Sample Register,
C Old Pipe Register,
C New Pipe Register,
C Sample Register.
rrrr
is the Data Word read from the Data Board.
eeee
is the Data Word Expected from the Data Board.
iiii
is the Status information from the current Qata Board under test.
NOTE: The Error Bit Map is a map of the Data Bus, DO - 015, and is an
exclusive OR of the Data Read and the Data Expected. Any bits that are
different show up as a "1". Bits that show up as a "0" passed the compare.
5-43
Data 80ard Diagnostic Subtest 10
TITLE:
RAM DATA INTEGRITY TEST
TARGET LOGIC:
6E 60 7E 7D 8E 80
58 5C 686C 88 8C 98 9C
5D 5E 9E 90
5A 6A 8A 9A
6J 5J 5L 8J 4K
6H
AI I hardware in Data Path Test.
TEST DESCRIPTION:
This test performs a static test of the RAM on the Data boards.
This is done using the 24 Data patterns. All 512 Memory locations are written
to with the same data to the same I/O port OC6H. Since The address counters
should be advancing on each Sample Clock, al I locations should be written to.
This test does not check the addressing uniqueness of each location.
It does verify that al I Data bits are functional and totally independant of
each other.
Prior to this test, the Data path up to the Old Pipe Register has been
checked. There are two 10176 "0" latches between the Old Pipe Register and the
RAM chip. These latches receive their clock from either WE01/ or WE02/,
depending on the current Phase of the clock. The signals WE01/ and WE02 also
are the write enables to the RAM chips. So The RAM chips are 'alternately
written to on each Sample Clock.
TEST STEP INFORMATION:
Step
Data
Data Written to
1
2
3
4
OOOOH
5555H
AAAAH
CCCCH
3333H
6666H
9999H
FFFFH
0001H
0002H
0004H
0008H
0010H
0020H
0040H
0080H
0100H
0200H
0400H
0800H
1000H
2000H
4000H
8000H
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
Data Verified at
------------------------------------------------------------------------------
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
OC6H~
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
Diagnostic
Diagnostic
Diagnostic
Diaghostlc
Diagnostic
Diagnostic
oi agnost i c
Diagnostic
o agnostic
o agnostic
o agnostic
o agnostic
o agnostic
o agnostic
o agnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
5-44
OCOH,
OCOH,
OCOH,
OCOH,
OCOH,
OCOH,
OCOH,
OCOH,
OCOH,
OCOH,
OCOH,
OCOH,
OCOH,
OCOH,
OCOH,
OCOH,
OCOH,
OCOH,
OCOH,
OCOH,
OCOH,
OCOH,
OCOH,
OCOH,
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
Locations
Locations
Locations
Locations
Locations
Locations
Locations
Locations
Locations
Locations
Locations
Locations
Locations
Locations
Locations
Locations
Locations
Locations
Locations
Locations
Locations
Locations
Locations
Locations
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
-
lFFH
lFFH
lFFH
lFFH
lFFH
lFFH
lFFH
lFFH
lFFH
lFFH
lFFH
lFFH
lFFH
lFFH
lFFH
lFFH
1FFH
lFFH
lFFH
1FFH
lFFH
1FFH
lFFH
lFFH
ERROR MESSAGES:
If an error occurs, the following message is displayed:
* Test FAILED--Test Step ssss
RAM Data Integrity Verify Error
Byte Count
= aaaaH
Data Read
= rrrrH
Data Expected
= eeeeH
Error Bit Map
= OOOOOOOOOOOOOOOOB
Board Status X8 = iliiH
Where:
ssss is the test step number in the range of 1 to 24.
o to
1FFH.
aaaa
Is the Address offset for the RAM, in the range of
rrrr
is the Data Word read from the Data Board.
eeee
is the Data Word Expected from the Data Board.
iii i
is the Status information from the current Data Board under test.
NOTE:
The Error Bit Map is a map of the Data Bus, DO - 015, and is an
exclusive OR of the Data Read and the Data Expected. Any bits that are
different show up as a "1". Bits that show up as a "0" passed the compare.
5-45
Data Board Diagnostic Subtest 11
TITLE:
RAM ADDRESS ING INTEGR ITY TEST
TARGET LOGIC:
6E
5B
5D
5A
6J
6H
6D
5C
5E
6A
5J
7E
6B
9E
8A
5L
7D 8E 8D
6C 8B 8C 9B 9C
9D
9A
8J 4K
AI I hardware in Data Path Test.
TEST DESCRIPTION:
This test writes a unique Data value to each of the 512 Memory
locations. Each memory location should contain unique Data from each other
location. The Memory is read back and each location is verified to see if
each address is uniquely addressable.
The Data that is written is an incrementing pattern. The first
test step starts with a value of OOOtH for the first location, and the
sequential locations are written to with a 0002H, 0003H, etc.
The second Test step is simi lar to the first, except the starting
Data value is a 0002H. Subsequent test steps shift this Data value left,
so that the starting Data values for the 16 test steps are:
TEST STEP INFORMATION:
Step
Start Data
Data Written to
Data Verified at
--------------~--------------------------------------- ------------------------
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
0001H
0002H
0004H
0008H
0010H
0020H
0040H
0080H
0100H
0200H
0400H
0800H
1000H
2000H
4000H
8000H
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
D agnostic
D agnostic
D agnostic
D agnostic
D agnost c
D agnost c
D agnost c
D agnost c
D agnost c
D agnost c
D agnost c
D agnost c
D agnost c
D agnost c
D agnost c
D agnost c
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
5-46
OCOH,
OCOH,
OCOH,
OCOH,
OCOH,
OCOH,
OCOH,
OCOH,
OCOH,
OCOH,
OCOH,
OCOH,
OeOH,
OCOH,
OCOH,
OCOH,
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
Locations
Locations
Locations
Locations
Locations
Locations
Locations
Locations
Locations
Locations
Locations
Locations
Locations
RM~ . Locat ions
RAM Locations
RAM Locations
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
-
lFFH
1FFH
1FFH
lFFH
lFFH
lFFH
lFFH
lFFH
lFFH
lFFH
lFFH
lFFH
lFFH
1FFH
lFFH
1FFH
ERROR MESSAGES:
If an error occurs, the following message is displayed:
* Test FAILED--Test Step ssss
RAM Address Unique Error
Byte Count
= aaaaH
Data Read
= rrrrH
Data Expected = eeeeH
Error Bit Map
= OOOOOOOOOOOOOOOOB
Board Status X8 = iiiiH
. Where:
ssss is the test step number in the range of 1 to 16.
aaaa
is the Address offset for the RAM, in the range of 0 to lFFH.
rrrr
is the Data Word read from the Data Board.
eeee
is the Data Word Expected from the Data Board.
iiii
is the Status information from the current Data Board under test.
NOTE:
The Error Bit Map is a map of the Data Bus, DO - 015, and is an
exclusive OR of the Data Read and the Data Expected. Any bits that are
different show up as a "1". Bits t!1at show up as a "0" passed the compare.
5-47
Data Board Diagnostic Subtest 12
TITLE:
TRACE CONDITIONS TEST
TARGET LOGIC:
8J 8H
6H 6L 9H
12M 13M 3M 11M 10M
TRACED/ Signal P2-56 from Control Board
ARMED
Signal P2-58 from Control Board
TEST DESCRIPTION:
This test uses the Control Board to provide Trace Conditions that exist on
the Data Board. These are mainly "ARMED" and "TRACED/". This test is simi lar
to the Force Conditions Test.
TEST STEP INFORMATION:
Step
Status Expected
1
2
3
45H
C5H
4
71H
72H
ERROR MESSAGES:
If an error occurs, the following message is displayed:
* Test FAILED--Test Step ssss
Trace Conditions Error
I/O Address
= aaaaH
Status Read
= rrrrH
Status Expected = eeeeH
Error Bit Map
= OOOOOOOOOOOOOOOOB
Board Status X8 = iiliH
Where:
ssss is the test step number in the range of
to 4.
aaaa
is the I/O address of the Data Board:
OC8H for Data Board A Status Register,
OD8H for Data Board B Status Register,
OE8H for Data Board C Status Register.
rrrr
is the Data Word read from the Data Board.
eeee
is the Data Word Expected from the Data Board.
iii i
is the Status information from the current Data Board under test.
NOTE:
The Error Bit Map is a map of the Data Bus, DO - D15, and is an
exclusive OR of the Data Read and the Data Expected. Any bits that are
different show up as a "1". Bits that show up as a "0" passed the compare.
5-48
Data Board Diagnostic Subtest 13
TITLE:
RECIRCULATE RAM TEST
TARGET LOGIC:
The main hardware being tested Is the feed back loop of the 10173 Multiplexers
50, 5E, 9E and 90, to the 10121 Multiplexers with Memory Select Enabled.
The entire Data Path and most of the Control Logic must be fuctional for this
test to pass.
TEST DESCRIPTION:
The. contents of the ECL RAM is recirculated out of the RAM through the
Multiplexers, through the Glitch Latches, through the Sample Register, through
the New Pipe Register, through the Old Pipe Register, through the RAM latch and
back into the ECL RAM. AI I of the clocking is done by the Clock board and the
Control Board.
There is a time-out counter on the recirculation, and after the recirculation
is completed, the Data in the ECL RAM should be the same as before.
TEST STEP INFORMATION:
Step
Status Expected
Clock Time Out
1
8000H
8000H
8000H
10 usec
20 usec
30 usec
---------------------------------------------3
5
Step
2
4
6
Data Expected
OOOOH - 01FFH (incrementing pattern)
OOOOH - 01FFH (incrementing pattern)
OOOOH - 01FFH (incrementing pattern)
ERROR MESSAGES:
If an error occurs, the fol lowing message is displayed:
* Test
FAILED--Test Step
ssss
hmsg
I/O Address
= aaaaH
Data Read
= rrrrH
Data Expected
= eeeeH
Error Bit Map
= OOOOOOOOOOOOOOOOB
Board Status X8 = iiiiH
5-49
ERROR MESSAGES: (Cont'd)
Where:
ssss is the test step number in the range of 1 to 6.
hmsg
is the Error heading message:
Recirculation
Recirculation
Recirculation
Recirculation
Recirculation
Recirculation
Time out-10us clock,
Error-10us clock,
Time out-20us clock,
Error-20us clock,
Time out-30us clock,
Error-30us clock.
aaaa
is the I/O address of the D~ta Board:
OCOH for Data Board A RAM,
ODOH for Data Board B RAM,
OEOH for Data Board CRAM,
OFOH for Control Board Status.
rrrr
is the Data Word read from the Data Board.
eeee
is the Data Word Expected from the Data
iiii
is the Status information from the current Data Board under test.
Boa~d.
NOTE:
The Error Bit Map is a map of the Data Bus, DO - 015, and is an
exclusive OR of the Data Read and the Data Expected. Any bits that are
different show up as a "1". Bits that show up as a "0" passed the compare.
5-50
K205 CONTROL BOARD DIAGNOSTIC
DIAGNOSTIC OVERVIEW
This section describes the subtests that are performed by the K205 Control
Board Diagnostic. The target hardware is presented, as well as a general
description of each subtest, a list of information for each test step, and
a dsecription of Error Messages that may be printed for the subtest results.
The Control Board Diagnostic is divided into 12 subtests, each of which is
described Individually on the following pages.
Subtest 1 is a Force Conditions test, subtest 2 is an Advance RAM Forward
and Jump RAM backward test, subtest 3 and 4 are Detection RAMs Data and
Address integrity test, subtest 5 and 6 are Delay Control RAM Data and
Address integrity test, subtest 7 and 8 are Delay RAMs Data and Address
integrity test, subtest 9 is Delay Counter test, subtest 10 is Relation
Logic test, subtest 11 and 12 are Selection RAMs data and Address integrity
test.
Subtests 1, 2, and 3 require Data Boards A, B, and C installed in the system.
The external signals through mother board to the Data Boards are checked by
subtest 1, the external signals through connector J1 to the Clock Board are
checked by subtest 2.
NOTE:
The 'TARGET LOGIC' listed in each subtest description does not
necessarily include all of the logic which could affect the operation of
the subtest.
SUBTEST CATEGORY
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
Force Condition Test
Advance and Jump RAM Test
Detection RAMs Data Integrity Test
Detection RAMs Address Integrity Test
Delay Control RAM Data Integrity Test
Delay Control Ram Address Integrity Test
Delay RAMs Data Integrity Test
Delay RAMs Address Integrity Test
Delay Counter Test
Relation Logic Test
Selection RAMss Data Integrity Test
Selection RAMs Address Integrity Test
5-51
ERROR COUNT CATEGORY
1- Subtest 1 Error Count
2. Subtest 2 Error Count
3. Subtest 3 Error Count
4. Subtest 4 Error Count
5. Subtest 5 Error Count
6. Subtest 6 Error Count
7. Subtest 7 Error Count
8. Subtest 8 Error Count
9. Subtest 9 Error Count
10. Subtest 10 Error Count
11- Subtest 11 Error Count
12. Subtest 12 Error Count
5-52
Control Board Diagnostic Subtest 1
TITLE:
FORCE CONDITION TEST
TARGET LOGIC:
6A, 7A, 5A, 4A, llA, 5F, 70, 5C, 50, 7C, 40, 80,
lC, 3C, BC, 9C, 5G, llG, 4J, 12C, 14B, 12A, 12F,
and 5K, 8J, 8H, 6H of DATA BOARD A, B, and C
TEST DESCRIPTION:
The force condition is functionally tested by forcing the desired condition
true; the condition is then verified by reading back the corresponding status
bit.
There are seven force condition tests included. Condition 0 is force level O.
Condition 1 is force jump and jump not. Condition 2 is force trace and trace
not. Condition 3 is force stop and stop not. Condition 4 is force event and
advance. Condition 5 Is force stopped and armed. Condition 6 is force manual
manual advance.
Conditon 2 also verifies the 'TRACED' signal can propagate through the mother
board to data boards A, B, and C. Condition 5 also verifies the 'MEM. ARMED'
signal can propagate through the mother board to data boards A, B, and C.
TEST STEP INFORMATION:
Test Step
1
2
3
4.
5.
6.
7.
Condition Tested
force
force
force
force
force
force
force
Signals in schematics
level 0
jump and jump not
trace and trace not
stop and stop not
event and advance
stopped and armed
manual advance
'FORCE LEVEL=O'
'FORCE JUMP', 'FORCE JUMP/'
'FORCE TRACE', 'FORCE TRACE/'
'FORCE STOP', 'FORCE STOP/'
'FORCE EVENT AND ADVANCE'
'CYCLE RESET'
'ENABLE MANUAL ADVANCE'
ERROR MESSAGES:
1. If error condition 0 occurs, the fol lowing message is displayed:
*TEST FAILED -- TEST STEP zz
CONDITION : Force Level 0
Level Expected = eeH
Level Read
= rrH
Where zz should be 01
ee should be 00 through OF
rr should be 00 through OF
5-53
ERROR MESSAGES (Cont'd)
2. If error condition 1 occurs, the fol lowing message is displayed:
*TEST FAILED -- TEST STEP zz
CONDITION .: Force JUMP & JUMP NOT
Jump Expected = e
Jump Read
=r
Where zz should be 02
e should be 0 or
r should be 0 or
3. If errqr condition 2 occurs, the fol lowing message is displayed:
*TEST FAILED -- TEST STEP zz
CONDITION: Force TRACE & TRACE NOT
Trace Expected
=e
Trace Read
=r
Old Traced A Expected = a
.01 d Traced A Read
=t
Old Traced B Expected = b
Old Traced BRead
=u
Old Traced C Expected = c
Old Traced C Read
=v
Where zz should be 03
e, r, a, t, b, u, c, v should be 0 or 1
4. If error condition 3 occurs, the fol lowing message Is displayed:
*TEST FAILED -- TEST STEP zz
CONDITION: Force STOP & STOP NOT
Stop Expected = e
Stop Read
=r
Where zz should be 04
e should be 0 or
r should be 0 or
5. If error condition 4 occurs, the fol lowing message is displayed:
*TEST FAILED -- TEST STEP zz
CONDITION: Force EVENT & ADVANCE
Event Expected
=e
Event Read
=r
Advance Expected = p
=d
Advance Read
5-54
ERROR MESSAGES (Cont'd)
Where zz should be 05
e, r, p, d should be 0 or 1
6. If error condition 5 occurs, the fol lowing message is displayed:
*TEST FAILED -- TEST STEP zz
CONDITION: Force STOPPED & ARMED
Stopped Expected
= e
Stopped/ Read
= r
Armed Expected
= p
Armed/ Read
= d
Mem. Armed A Expected = a
Mem. Armed A Read
= t
Mem. Armed B Expected = b
Mem. Armed BRead
=u
Mem. Armed C Expected = c
Mem. Armed C Read
=v
Where zz should be 06
e, r, p, d, a, t, b, u, c, v should be 0 or
7. If
error condition 6 occurs, the fol lowing message is displayed:
*TEST FAILED -- TEST STEP zz
CONDITION: Force MANUAL ADVANCE
Advance Expected
= e
AdvancE Read
=r
Manual Advance Expected = p
Man. Advance Read
=d
Where zz should be 07
e, r, p, d should be 0 or1
5-55
Control Board Diagnostic Subtest 2
TITLE:
ADVANCE AND JUMP RAM TEST
TARGET LOGIC:
5H, 5J, 5G, llG, 12F, llF,
and level memory logic in the clock board,
connector J1 included.
TEST DESCRIPTION:
The advance and jump RAMs are functionally tested by advancing the Advance
RAM to the next level and restoring the jump RAM backward to a previous level.
The RAM data is then verified by reading back the level and comparing the
result to the expected level.
TEST STEP INFORMATION:
Test Step
RAM Tested
Level Tested
Expected Level
OOH through OFH
OOH through OFH
Level tested + 1
Level tested - 1
----------------------------------------------------------------1 through 16
17 through 32
advance
jump
ERROR MESSAGE:
1. If an error of Advance RAM occurs, the fol lowing message is displayed:
*TEST FAILED -- TEST STEP zz
Adv. RAM Advancing Test
Adv. RAM Level at
= IIH
Adv. RAM Data Expected = eeH
Adv. RAM Data Read
= rrH
Error Bit Map
= xxxxxxxxB
= ppH
Ext. Level Expected
Ext. Level Read
= qqH
= yyyyyyyyB
Error Bit Map
Where zz should be 01 through 16
II should be 00 through OF
ee should be 00 through OF
rr should be 00 through OF
pp should be 00 through OF
qq should be 00 through OF
xxxxxxxx should be 00000000 through 00001111
yyyyyyyy should be 00000000 through 00001111
5-56
ERROR MESSAGE (Cont'd)
2. If an error of Jump RAM occurs, the fol lowing message is displayed:
*TEST FAILED -- TEST STEP zz
Jump RAM Advancing Test
Jump RAM Level at = IIH
Jump RAM Data Expected = eeH
Jump RAM Data Read = rrH
Where zz should be 17 through 32
II should be 00 through OF
ee should be 00 through OF
rr should be 00 through OF
5-57
Control 60ard Diagnostic Subtest 3
TITLE:
DETECTION RAM DATA INTEGRITY TEST
TARGET LOGIC:
8G, 8F" 9G, 9F,
4G, 4F, 7G, 7F,
lG, lF, 3G, 3F,
2J, 66, 56, 46,
50, 5C, 7C, 40,
12C, 12G, 12H
80,
3D,
10,
7B,
5F,
90
4D, 70
3D
86, 16, 2B, 36, 8A, 9A
3C, lC, 8C, 9C, 9B
TEST DESCRIPTION:
The detection RAMs data integrity is functionally tested by writing a four
bits nibble into each RAM, the RAM data is then verified by reading the
(ADVANCE,JUMP,STOP,TRACE) nibble and comparing the result to the expected
nibble.
The nibble patterns tested are:
10106, 01016, 1100B, 00116, 00016, 00106, 01006, 1000B.
The detection RAMs tested are:
8G, 8F, 9G, 9F, 4G, 4F, 7G, 7F, lG, lF, 3G, 3F.
TEST STEP INFORMATION:
Test Step
01
09
17
25
33
41
49
57
65
73
81
89
through 08
through 16
through 24
through· 32
through 40
through 48
through 56
through 64
through 72
through 80
through 88
through 96
RAM Chip Location
8G D)*(Cadvanced + jumped) /)
(T < D) = NOT (P1 + P2 + P3 + P4 + P5)
(T = D) = P1 + P2 + P3 + P4
(T > D) = P5 + P6
Path 0 logic means T < 0 true.
TEST STEP INFORMATION
Test Step
1
2
3
4
Logic Path
Relation True
0,
2
3
T < 0 then T = 0
T
T
=0
4, 5, 6
T
=
=0
0 then T > 0
ERROR MESSAGES:
If an error occurs, the fol lowing message is displayed:
*TEST FAILED -- TEST STEP zz
Relation Logic Path p Fal led
"T < 0" Expected = a
"T < 0" Read
= b
"T = 0" Expected = c
"T = 0" Read
= d
"T > D" Expected = e
"T > 0" Read
=f
Where zz should be
through 4.
a, b, c, d, e, f should be 0 or 1.
5-68
Control Board Diagnostic Subtest 11
SELECTION RAM DATA INTEGRITY TEST
TITLE:
TARGET LOGIC:
68, 58, 48, 78, 88, 18, 28, 38, 8A, 9A,
5C, 50, 7C, 4D, 8D, 5F, 7D, lC, 3C, 8C,
9C, 3D, 98
TEST DESCRIPTION:
The Selection RAMs data integrity is functionally tested by separating al RAMs
into 4 subgroups (ADVANCE, JUMP, STOP, TRACE), writing the specified data into
into the RAMS of each subgroup, and verifying the data integrity by reading
the (ADVANCE, JUMP, STOP, TRACE) bits and comparing the result to the nibble
expected.
There are 4 subgroups as follows, being tested:
selection bit
Subgroup A : b t 0
btl
selection bit
selection bit
b t 2
b t 3
selection bit
b t 4
selection bit
b t 5 -- selection bit
b t 6 -- selection bit
b t 7
selection bit
for
for
for
for
for
for
for
for
ADVANCE A
ADVANCE B
ADVANCE C
(ADVANCE C.8.A)/
ADVANCE if T > D
ADVANCE if T = D
ADVANCE if T < 0
ADVANCE if 'x'
Subgroup J
b t 0
btl
b t 2
b t 3
b t 4
b t 5
b t 6
selection
selection
selection
selection
selection
selection
selection
bit
bit
bit
bit
bit
bit
bit
for
for
for
for
for
for
for
JUMP A
JUMP 8
JUMP C
(JUMP C.8.A)/
JUMP if T > D
JUMP if T = D
JUMP if T < 0
Subgroup S
bit
bit
bit
bit
bit
bit
bit
bit
0
1
2
3
4
5
6
7
selection
selection
selection
selection
selection
selection
selection
selection
bit
bit
bit
bit
bit
bit
bit
bit
for
for
for
for
for
for
for
for
STOP A
STOP 8
STOP C
(STOP C.8.A)/
STOP if T > D
STOP if T = D
STOP if T < D
STOP if 'x'
bit
bit
bit
bit
bit
bit
bit
bit
selection bit for TRACE A
1
selection bit for TRACE 8
2 -- selection b t for TRACE C
3
selection b t for D
5
selection b t for TRACE if T = D
6
selection b t for TRACE if T < D
7
selection b t for TRACE if 'x'
Subgroup T
-----
0
Each bit has logic
o and logic 1 to be tested.
5-69
TEST STEP INFORMATION:
Test Step
Subgroup
Bit
1
Advance
Advance
Advance
Advance
Advance
Advance
Advance
Advance
Advance
Advance
Advance
Advance
Advance
Advance
Advance
Advance
Jump
Jump
Jump
Jump
Jump
Jump
Jump
Jump
Jump
Jump
Jump
Jump
Jump
Jump
Jump
Jump
Stop
Stop
stop
Stop
Stop
Stop
stop
Stop
Stop
Stop
Stop
Stop
Stop
Stop
Stop
Stop
Trace
Trace
Trace
Trace
0
0
Mnemonic
Logic State
Related Chip
----------------------------------------------------------------------------2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
1
1
2
2
3
3
4
4
5
5
6
6
7
7
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
0
0
1
1
ADVANCE A
ADVANCE A
ADVANCE B
ADVANCE B
ADVANCE C
ADVANCE C
(ADVANCE C.B.A)/
(ADVANCE C.B.A)/
ADVANCE if T > D
ADVANCE if T > D
ADVANCE if T = D
ADVANCE if T = D
ADVANCE if T < D
ADVANCE if T < D
ADVANCE if I x,
ADVANCE if I X I
Jump A
Jump A
Jump B
Jump B
Jump C
Jump C
(Jump C.B.A)/
(Jump C.B.A)/
Jump 'if T > D
Jump if T > D
Jump if T = D
Jump if T = D
Jump if T < D
Jump if T < D
None
None
Stop A
Stop A
Stop 8
Stop B
Stop C
Stop C
(Stop C.B.A)/
(Stop C.B.A)/
Stop f T > D
Stop f T > D
Stop f T = D
Stop f T = D
Stop f T < D
stop f T < D
Stop f I x I
Stop f 'x I
Trace A
Trace A
Trace B
Trace B
5-70
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
x
x
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
4B-D3
4B-D3
58-D2
5B-D2
5B-D3
5B-D3
5B-Dl
5B-Dl
6B-D2
6B-D2
6B-DO
6B-DO
6B-D3
6B-D3
6B-D1
6B-D1
8B-D2
8B-D2
8B-D3
8B-D3
4B-DO
4B-DO
4B-D2
4B-D2
7B-D3
7B-D3
7B-Dl
7B-D1
7B-D2
7B-D2
None
None
3B-D2
3B-D2
2B-DO
2B-DO
2B-D2
2B-D2
18-D1
1B-Dl
lB-DO
lB-DO
18-D3
lB-D3
lB-D2
1B-D2
2B-D3
2B-D3
9A-DO
9A-DO
8A-D2
8A-D2
53
54
55
56
57
58
59
60
61
62
63
64
Trace
Trace
Trace
Trace
Trace
Trace
Trace
Trace
Trace
Trace
Trace
Trace
2
2
3
3
4
4
5
5
6
6
7
7
Trace C
Trace C
(Trace C.B.A)/
D
Trace if T > 0
Trace t f T = 0
Trace if T = 0
Trace if T < D
Trace if T < D
Trace if' x'
Trace t f' x'
ERROR MESSAGES:
If an error occurs, the following message is displayed:
*TEST FAILED -- TEST STEP zz
Selection RAMs Data Integrity
Subgroup g Bit b Testing
RAM Address
= aaH
AJST/ Nibble Expected = nnH
AJST/ Nibble Read
= rrH
Error Bit Map
= xxxxxxxxB
Where zz should be 1 through 64
g should be A, J, S, T.
b should be 0 or 1.
aa should be 00 through OF.
nn should be 08, 04, 02, 01, 0
rr should be 00 through OF
xxx xxx xx should be 00000000 through 00001111
5-71
0
1
0
1
0
1
0
1
0
1
0
1
8A-DO
8A-DO
8A-D1
8A-Dl
9A-D2
9A-D2
9A-D3
9A-D3
3B-DO
3B-00
3B-Dl
38-D1
Control Board Diagnostic Subtest 12
TITLE:
SELECTION RAM ADDRESS INTEGRITY TEST
TARGET LOGIC:
68, 5B, 48, 78, 88, 18, 28, 3B, 8A, 9A,
5C, 5D, 7C, 4D, 8D, 5F, 7D, 1C, 3C, 8C,
9C, 3D, 98
TEST DESCRIPTION:
The Selection RAMs address integrity is functionally tested by separating al I
RAMs into 4 subgroups (ADVANCE, JUMP, STOP, TRACE), clearing al I locations
of selection RAMs, going to the asserted level address, and writing bit a
into the RAMS of each subgroup. The address integrity is then verified by
reading the (ADVANCE, JUMP, STOP, TRACE) bits from al I locations.
There are 4 subgroups as follows, being tested:
Subgroup
Subgroup
Subgroup
Subgroup
A
J
S
T
bit
bit
bit
bit
a
a
a
a
selection
selection
selection
selection
bit
bit
bit
bit
for
for
for
for
ADVANCE A
JUMP A
STOP A
TRACE A
Each bit only test logic a.
TEST STEP INFORMATION:
Test Step
Subgroup
Bit
1
Advance
Advance
Advance
Advance
Jump
Jump
Jump
Jump
Stop
Stop
Stop
Stop
TRACE
TRACE
TRACE
TRACE
a
a
a
a
a
a
a
0
0
0
0
0
0
0
0
a
Mnemonic
Logic State
Level Address
-----------------------------------------------------------------------------2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
ADVANCE A
ADVANCE A
ADVANCE A
ADVANCE A
JUMP A
JUMP A
JUMP A
JUMP A
STOP A
STOP A
STOP A
STOP A
TRACE A
TRACE A
TRACE A
TRACE A
5-72
a
a
a
a
a
a
0
0
0
0
0
a
0
0
0
0
a1H
a2H
a4H
a8H
a1H
a2H
a4H
08H
01H
02H
a4H
08H
a1H
02H
a4H
a8H
ERROR MESSAGES:
If an error occurs, the fol lowing message is displayed:
*TEST FAILED -- TEST STEP zz
Selection RAMs Address Integrity
Subgroup g Testing
Address' Expected
= eeH
Address Found
= ffH
AJST/ Nibble Expected = nnH
AJST/ Nibble Read
= rrH
Where zz should be 1 through 16
g should be A, J, S, T.
ee should be 01, 02, 04, 08
ff should be 00 through OF
nn should be 08, 04, 02, 01
rr should be 00 through OF
5-73
K205 CLOCK BOARD DIAGNOSTIC
DIAGNOSTIC OVERVIEW
This section describes subtests that are performed by the K205 Clock Board
Diagnostic. The target hardware is presented, as wei I as a general
description of each Subtest, a list of information for each Test Step, and
Error Messages that may be printed.
The K205 Clock Board Diagnostic is a board level Diagnostic which runs under
the K205 Diagnostic Operating System. The Diagnostic verifies al I functions
of the Clock Board except for "J2", which presents clocks to the front panel.
The hardware that is not tested is a 4028 Multiplexer/Driver at 9B, two
drivers at lOB, and the cable going to the front panel.
The Diagnostic Tests that are performed can be divided into five basic
sections as described below.
The first is the Force Conditions Test. This test is a series of simple I/O
operations that are performed on the Clock Board.
The second is the Sample and Control Clock testing. These clocks move data on
the Data Boards. Specifically, the Sample Clock clocks the Data Board's
Sample Registers, and the Control Clock clocks the Data Board's Pipeline.
The third is the Latch Clock testing. The Latch Clocks also clock data on the
Data Boards, but in a special "latch mode" where data is latched before it
reaches the Data Board's Sample Registers.
The fourth is the Frequency testing. AI I seven decades from the 100Mhz Clock,
down to the 100 Hz Clock are tested. The Clock Board Multiplier is tested to
see if it can actually perform a divide by function, thus slowing down the
clock rate.
The fifth and final is the testing of the Level RAM. The RAM is tested
Data integrity, Addressing integrity, and control logic functionality.
for
The Diagnostic uses Data Boards A, Band C extensively to check out the
clocking features. The Diagnostic also requires the use of the Control Board
and the Threshold Board. AI I of these boards must be functional for any
realistic pinpointing of possible fai lures. AI I six of the external probes
must be instal led, with floating inputs (no connection).
If Data Board C is not instal led, (i.e. unit contains 32 input channels),
the C section clocks of the Clock Board wi I I not be tested, and the fol lowing
message is displayed:
>Testing sections A & B, cannot test section C.
This message informs the operator that the A and B sections are being tested,
but there is insufficient hardware in the system to diagnose section C.
AI I six probes must sti II be instal led to properly test sections A and B.
5-74
The type of tests that are performed on the Clock Board are static type tests.
The tests verify the functionality and individuality of multiplexers and gates
but do not perform "real time" testing on the board. Therefore, If racing
conditions exist, or If problems occur with propagation delays, the Diagnostic
wll I probably not detect them.
Also, the frequency test that Is performed on the Clock Decades Is a
"ballpark" test, and does not verify that the 100 Mhz source clock is exactly
100.00 Mhz. This must be adjusted/verified with a scope or frequency counter.
The Clock Board provides very little status information to monitor the Modes
or selections. Of the 133 Command Output Bits, the Clock board only provides
4 Status Input Bits.
If multiple failures exist on a board under test, the problem might originate
in the I/O port decoding and data latching. This portion of the board is
Inltlal.ly assumed to be functional. If it is not funtional, very few If any
tests wi II pass.
DESCRIPTION OF DATA BOARD REGISTERS USED TO TEST CLOCK BOARD
The Sample Clocks, Latch Clocks and Control Clocks are tested using the K205
Data Boards. The Data Boards are also used for the Frequency tests.
A simple outline of the registers on the Data Boards is as fo I lows:
1- Data Boards Diagnostic Latch Register.
Data Board A - Write Port OCOH. (cannot read this port back)
Data Board B - Wr ite Port ODOH. (cannot read this port back)
Data Board C - Write Port OEOH. (cannot read this port back)
This Latch is the "Front End" to the Data Board's Data Path. Data is
placed in this register by simply performing an OUTWORD Instruction.
2. Data Boards Sample Registers.
Data Board A - Read Port OC6H. (cannot write directly to this port)
Data Board B - Read Port OD6H. (cannot write directly to this port)
Data Board C - Read Port OD6H. (cannot write directly to this port)
Data is transfered from the Data Board's Diagnostic Latch Registers
to the Data Board's Sample Register when a Sample Clock is Issued.
Sample Register A requires Sample Clock A, Sample Register B requires
Sample Clock B, and Sample Register C requires Sample Clock C.
This transfer wi I I take place assuming the Data Board is not in
"Latch" mode.
3. Data Boards New Pipe Registers.
Data Board A - Read Port OC4H. (cannot write directly to this port)
Data Board B - Read Port OD4H. (cannot write directly to this port)
Data Board C - Read Port OD4H. (cannot write directly to this port)
5-75
Data Is transferred from the Data Boards Sample Registers to the
Data Boards New Pipe Registers when a Control Clock is issued.
Data Boards A, Band C all use a single Control Clock for transfer.
4. "Latch" Mode on the Data Boards.
When the Data Boards are in Latch Mode, an extra Data latch is present
between the Diagnostic Latch Registers and the Sample Registers.
A Latch Clock is required to transfer Data.
In Latch Mode, the fol lowing sequence is required to place Data Into
the Data Board's Sample Registers.
Output the desired Data to the Diagnostic Latch Registers. This wll I
present the Data to the Input of the "Latch" mode Registers. Issuing
a Latch Clock presents this Data to the input of the Sample Registers.
Issuing a Sample Clock latches this Data In the Sample Registers.
Data Board A requires Latch Clock A, Data Board B requires Latch Clock
B, and Data Board C requires Latch Clock C.
SUBTEST CATEGORIES
There are fourteen subtests that are performed by the Clock Board Diagnostic.
These tests are as fol lows:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
Force Conditions Test
Sample and Control Clocks, Diagnostic Internal Clock Test
Sample and Control Clocks, OR-only Enables Test
Sample Clocks, 10ns Clock Test
Sample and Control Clocks, AJ, BJ and CJ Clocks Test
Sample and Control Clocks, AK, BK and CK Clocks Test
Latch Clocks, Diagnostic Internal Clock Test
Latch Clocks, Diagnostic OR-only Enables Test
Latch Clocks, AR, BR and CR Clocks Test
Latch Clocks, AS, BSand CS Clocks Test
Decade Frequency and Multiplier Divide by Test
Level RAMs Data Integrity Test
Level RAMs Address Integrity Test
Level RAMs Control Test
ERROR COUNT CATEGORIES
The Error Count Display Information is a one for one match with the subtest
above. The K205 Diagnostic Operating System wi I I display the message "Subtest
n" instead of the actual test name (where "n" = Subtest Number).
Subtest 1
Subtest 2
Subtest 3
Subtest 4
Subtest 5
Subtest 6
(Force Conditions)
(Sample and Control Clocks, Diagnostic Internal)
(Sample and Control Clocks, OR-only Enables)
(Sample Clocks, 10ns Clock Test
(Sample and Control Clocks, AJ, BJ and CJ)
(Sample and Control Clocks, AK, BK and CK)
5-76
Subtest 7
Subtest 8
Subtest 9
Subtest 10
Subtest 11
Subtest 12
Subtest 13
Subtest 14
(Latch Clocks, Diagnostic Internal)
(Latch Clocks, Diagnostic OR-only Enables)
(Latch Clocks, AR, BR and CR)
(Latch Clocks, AS, BS and CS)
(Decade Frequency and Multiplier)
(Level RAMs Data Integrity)
(Level RAMs Address Integrity)
(Level RAMs Control)
5-77
Clock Board Diagnostic Subtest 1
TITLE:
FORCE CONDITIONS TEST
TARGET LOGIC:
7J, 6J, 8J, 10K,
11K, 12J, 6K, 9K, 9J, l1H
10H
lOG, 10F, 9F, 11K,
5J
TEST DESCRIPTION:
This test issues commands to the Clock Board and expects to see certain status
conditions existing. Commands are issued by writing to port OBEH, and the
Status is read back from port OB2H.
Since the Clock Board only provides 4 status bits for al I of the 113 command
bits, only a fraction of the I/O read/write/co~trol logic is actually tested.
If there are errors in this test, the I/O decode logic and/or data latches may
be faulty, and the succeeding tests wi I I probably have multiple errors.
TEST STEP INFORMATION:
Step
1
2
3
4
5
Expected Status
AOOOH
2000H
OOOOH
6000H, 7000H
7000H
ERROR MESSAGES:
If an error occurs, the fol lowing message is displayed:
* Test FAILED--Test Step ssss
Force Conditions/Status Error
No Clocking used
I/O Address
= aaaaH
Status Read
= rrrrH
Status Expected = eeeeH
5-78
Where:
ssss is the Test Step in the range of 1 to 5.
aaaa
is the address of the Clock Board Status Register, OOB2H.
rrrr
is the Data Word read from the Status Register.
eeee
is the Data Word expected from the Status Register.
NOTE: With the limited amount of status bits on the Clock Board, it is
difficult to pin point the cause of an error. Whether the fault lies with
an address decoder, a Data Bit Driver or Latch, the fault can be determined
objectively by using a Logic Analyzer or Scope, and setting the Loop On Error
Option.
5-79
Clock Board Diagnostic Subtest 2
TITLE:
SAMPLE AND CONTROL CLOCKS, DIAGNOSTIC INTERNAL CLOCK TEST
TARGET LOGIC:
7A,
7D,
7F,
11H,
10C
11 B
3E,
8A,
8D,
8F,
10D,
10H,
10J,
7G,
12C,
7B, 8B, 9G
7E, 8E, 9H
8G, 7H, 8H
11 C
3F,
3G,
3H, 4H, 4J, 4C, 4D
TEST DESCRIPTION:
The Diagnostic Internal Sample Clocks A, Band C, and the Diagnostic
Internal Control Clock wil I be tested for functionality and uniqueness, as
wei I as the abi lity to disable these Clocks using the Threshold Disable, and
the Force Disqualify Disable.
The Sample Clocks are tested by placing Data at the Front End of the Data
Board, issuing a Diagnostic Internal Sample Clock, and checking the
Sample Registers to see if a Data transfer took place.
The Control Clocks are similarly tested by clocking data into the Sample
Registers, issuing a Diagnostic Internal Control Clock, and checking
the New Pipe Registers to see If a Data transfer took place.
NOTE: The Diagnostic Internal Clock is "kicked" by outputing a "1" to bit
DO of Write Registers OB8H of the Clock Board. This produces a clock pulse the
width of the 8086's Write pulse. Consecutive "kicks" can be achieved by
consecutive outputs to this port. It Is never necessary to set this bit low.
TEST STEP INFORMATION:
Step
Data
Clock Tested
1
2
.3
4
5
6
7
8
9
10
11
12
13
14
15
16
OOOOH
5555H
AAAAH
CCCCH
3333H
6666H
9999H
FFFFH
OOOOH
5555H
AAAAH
CCCCH
3333H
6666H
9999H
FFFFH
Sample A,
Sample A,
Sample A,
Sample A,
Sample A,
Sample A,
Sample A,
Sample A,
Control
Control
Control
Control
Control
Control
Control
Control
B,
B,
B,
B,
B,
B,
B,
B,
Data Verified at
C
C
C
C
C
C
C
C
Sample Registers A, B, C
Sample Registers A, B, C
Sample Registers A, B, C
Sample Registers A, B, C
Sample Registers A, B, C
Sample Registers A, B, C
Sample Registers A, B, C
Sample Registers A, B, C
New Pipe Registers A, B, C
New Pipe Registers A, B, C
New Pipe Registers A, B, C
New Pipe Registers A, B, C
New Pipe Registers A, B, C
New Pipe Registers A, B, C
New Pipe Registers A, B, C
New Pipe Registers A, B, C
5-80
Uniqueness Test:
Step
A Data B Data
C Data Clock Tested
Data Verified at
17
AAAAH
OOOOH
OOOOH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
OOOOH
OOOOH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
Sample Registers A, B, C
Sample Registers A, B, C
Sample Registers A, B, C
Sample Registers A, B, C
Sample Registers A, B, C
Sample Registers A, B, C
New Pipe Registers A, B, C
New Pipe Registers A, B, C
New Pipe Registers A, B, C
------------------------------------------------------------------------18
19
20
21
22
23
24
25
OOOOH
BBBBH
OOOOH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
Sample A
Sample B
Sample C
Control
Control
Control
Control
Control
Control
. NOTE: Test Steps 20 - 22 verify the Control Clock does not change the
contents of the Sample Registers.
Test Steps 23 - 25 verify the Control Clock can latch Data into the New Pipe
Pipe Reg.isters with al I Sample Clocks disabled.
Disable Test
Step
A Data
B Data C Data
Clock Tested
Data Verified at
---------------------------------~-------------------- -------------
26
27
28
29
30
31
AAAAH
BBBBH
CCCCH
OOOOH
OOOOH
OOOOH
Sample A
Sample B
Sample C
Control
Control
Control
Sample Register A
Sample Register B
Sample Register C
New Pipe Register A
New Pipe Register B
New Pipe Register C
Force Disqualify Test:
Step
A Data
32
33
34
35
36
37
AAAAH
B Data C Data Clock Tested
BBBBH
CCCCH
OOOOH
aoaOH
OOOOH
Sample A
Sample B
Sample C
Control
Control
Control
Data Verified at
Sample Register A
Sample Register B
Sample Register C
New Pipe Register A
New Pipe Register B
New Pipe Register C
ERROR MESSAGES:
If an error occurs, the fol lowing message is displayed:
* Test
FAILED--Test Step
cccc Clock tttt Error
Diagnostic Internal Clock
I/O Address
= aaaaH
Status Read
= rrrrH
Status Expected = eeeeH
ssss
5-81
Where:
ssss is the Test Step in the range: 1 to 37.
cccc is. the tested Clock: Sample.A,
Sample B,
Sample C,
Control.
tttt is the test type:
Functional,
Uniqueness,
Disable,
Force Disqualify
aaaa is the address of a Data Board Sample Register:
OC6H for Data Board A,
OD6H for Data Board B,
OE6H for Data Board C.
or a Data Board New Pipe Register:
OC4H for Data Board A,
OD4H for Data Board B,
OE4H for Data Board C.
rrrr is the Data Word read from the Status Register.
eeee is the Data Word expected from the Sample Register which should be:
OOOOH,
5555H,
AAAAH,
CCCCH,
3333H,
6666H,
9999H,
FFFFH.
NOTE: OOOOH is the expected Data Word for Data Boards during Uniqueness
Testing.
5-82
Clock Board Diagnostic Subtest 3
TITLE:
SAMPLE AND CONTROL CLOCKS OR-ONLY ENABLES TEST
TARGET LOGIC:
5E, 5F, 5G, 5H, 4H, 4J, 4C, 40
Setup Latches in Subtest 2
TEST DESCRIPTION:
The Sample Clocks A, Band C, and Control Clock's OR-Only Enable bits are
tested for functionality and uniqueness, as wei I as the abi lity to disable
these Clocks using the Force Disqualify Disable test.
The Sample Clocks are tested by placing Data at the Front End of the
Data Board, issuing a Sample Clock by toggling the OR-Only Enable bit, and
checking the Sample Registers to see if a Data transfer took place.
The Control Clocks are similarly tested by clocking data into the Sample
Registers, issuing a Control Clock by toggling the OR-Only Enable bit,
and checking the New'Pipe Registers to see if a Data transfer took place.
TEST STEP INFORMATION:
Functionality Test:
Step
Data
Clock Tested
Data Verified at
1
AAAAH
BBBBH
CCCCH
AAAAH
BBBBH
CCCCH
Sample A
Sample B
Sample C
Control
Control
Control
Sample Register A
Sample Register B
Sample Register C
New Pipe Register A
New Pipe Register B
New Pipe Register C
2
3
4
5
6
Uniqueness Test:
Step
A Data
B Data C Data Clock Tested
Data Verified at
7
AAAAH
OOOOH
OOOOH
AAAAH
AAAAH
OOOOH
BBBBH
OOOOH
BBBBH
BBBSH
Sample Registers A,
Sample Registers A,
Sample Registers A,
New Pipe Registers
New Pipe Registers
8
9
10
11
OOOOH
OOOOH
CCCCH
CCCCH
CCCCH
Sample A
Sample B
Sample C
Control
Control
5-83
B,
B,
B,
A,
A,
C
C
C
B, C
B, C
Force Disqualify Test:
Step
A Data
12
13
14
15
16
AAAAH
B Data
C Data Clock Tested
BBBBH
CCCCH
OOOOH
OOOOH
OOOOH
17
Sample A
Sample B
Sample C
Control
Control
Control
Data Verified at
Sample Register A
Sample Register B
Sample Register C
New Pipe Register A
New Pipe Register B
New Pipe Register C
ERROR MESSAGES:
If an error occurs, the fol lowing message is displayed:
*
Test FAILED--Test Step
cccc Clock tttt Error
OR Only Enables
I/O Address
= aaaaH
Status Read
= rrrrH
Status Expected = eeeeH
ssss
Where:
ssss is the Test Step in the range: 1 to 17.
cccc is the tested Clock: Sample A,
Sample B,
Sample C,
Control.
tttt is the test type:
Functional,
Uniqueness,
Force Disqualify.
aaaa is the address of a Data Board Sample Register:
OC6H for Data Board A,
OD6H for Data Board B,
OE6H for Data Board C.
or a Data Board New Pipe Register:
OC4H for Data Board A,
OD4H for Data Board B,
OE4H for Data Board C.
rrrr is the Data Word read from the Status Register.
eeee is the Data Word expected from the Sample Register which should be:
AAAAH for Data Board A, (OC6H, OC4H).
BBBBH for Data Board B, (OD6H, OD4H).
CCCCH for Data Board C, (OE6H, OE4H).
NOTE: OOOOH is the expected data word for al I Data Boards during
Uniqueness Testing.
5-84
Clock Board Diagnostic Subtest 4
TITLE:
SAMPLE CLOCKS, 10ns CLOCK TEST
TARGET LOGIC:
5E, 5F, 5G, 4H, 4J, 4C, 40
Setup Latches in Subtest 2
TEST DESCRIPTION:
The Sample Clocks A, B, C, and 10ns Clock Enable bit wi I I be tested for
functionality and uniqueness, as wei I as the abi lity to disable these Clocks
using the Force Disqualify Disable.
The Sample Clocks are tested by placing Data at the Front End of the
Data Board, toggling the 10ns Enable bit, and then checking the Sample
Registers to see if a Data transfer took place.
NOTE: The 10ns Enable bit is toggled active then inactive with two
consecutive output instructions by the 8086 CPU. Since the 100Mhz Clock is
so fast compared to the execution speed of the 8086, many Sample Clocks wi I I
occur during the short period that the 10ns Enable is active. This wi I I not
cause a problem, since the Sample Register cannot overflow.
TEST STEP INFORMATION:
Functionality Test:
Step
Data
Clock Tested
Data Verified at
1
AAAAH
BBBBH
CCCCH
Sample A
Sample B
Sample C
Sample Register A
Sample Register B
Sample Register C
2
3
Uniqueness Test:
Step
A Data
B Data
C Data
Clock Tested
Data Verified at
4
5
AAAAH
OOOOH
OOOOH
OOOOH
BBBBH
OOOOH
OOOOH
OOOOH
CCCCH
Sample A
Sample B
Sample C
Sample Registers A, B, C
Sample Registers A, B, C
Sample Registers A, B, C
6
5-85
Force Disqualify Test:
Step
A Data B' Data C Data Clock Tested
Data Verified at
AAAAH
Sample-Register A
Sample Register B
Sample Register C
---------------------------------------------------------------7
~
9
BBBBH
CCCCH
Sample A
Sample B
Sample C
ERROR MESSAGES:
If an error occurs, the fol lowing message Is displayed:
* Test
FAILED--Test Step
cccc Clock tttt Error
10ns Clock
I/O' Address
= aaaaH
Status Read
= rrrrH
Status Expected = eeeeH
ssss
Where:
ssss Is the Test Step In the range: 1 to 9.
cccc is the tested Clock: Sample A,
Samp Ie 'B,
Sample C.
tttt Is the test type:
Functional,'
Uniqueness,
Force Disqualify.
aaaa is the address of a Data Board ~ample Register:
OC6H for Data Board A,
OD6H for Data Board B,
OE6H for Data Board C.
rrrr is the Data Word read from the Status Register.
eeee Is the Data Word expected from the Sample Register which should be:
AAAAH for Data Board A.
BBBBH for Data Board B.
CCCCH for Data Board C.
NOTE: OOOOH is the expected Data Word for al I Data Boards during
Testing.
5-86
Clock Board Diagnostic Subtest 5
TITLE:
SAMPLE AND CONTROL CLOCKS AJ, 8J, and CJ CLOCKS TEST
TARGET LOGIC:
3E, 5E, 3F, 5F, 3G, 5G, 3H, 5H
4H, 4J, 4C, 40
4E
Setup latches in Subtest 2
TEST DESCRIPTION:
The AJ, AJ/, 8J, 8J/, CJ and CJ/ clock enables for the Sample Clocks
A, 8, C and the Control Clock wi I I be tested for functionality and uniqueness
as wei I as the abi lity to disable these Clocks using the Threshold Disable,
and the Force Disqualify Disable.
The Sample Clocks are tested by placing Data at the Front End of the Data
80ard, issuing a Sample Clock by toggling one of the AJ, 8J, CJ Enables, and
checking the Sample Registers to see if a Data transfer took place.
The Control Clocks are similarly tested by clocking data into the Sample
Registers, issuing a Control Clock by toggling one of the AJ, 8J, CJ Enables,
and checking the New Pipe Registers to see if a Data transfer took place.
NOTE: The logic states of AJ, AJ/, 8J, 8J/, CJ and CJ/ are determined by
the current threshold at the probes. An ECl Threshold, and a VARAIA8lE A
Threshold wi I I be used to provide the High and low logic states. This test
wi II require the use of the Threshold Board and the probes.
TEST STEP INFORMATION:
Functionality Test:
Step
Data
Clock Tested
1
2
AAAAH
BBBBH
CCCCH
AAAAH
BBB8H
CCCCH
AAAAH
8B88H
CCCCH
AAAAH
BBB8H
CCCCH
Sample A Sample B Sample C Control Control Control Sample A Sample 8 Sample C Control Control Control -
Data Verified at
-------------------------------------------------------------3
4
5
6
7
8
9
10.
11
12
AJ/,
AJ/,
AJ/,
AJ/,
AJ/,
AJ/,
AJ,
AJ,
AJ,
AJ,
AJ,
AJ,
8J/ ,
8J/,
8J/,
BJ/,
8J/,
BJ/,
8J,
8J,
BJ,
BJ,
8J,
BJ,
CJ/
CJ/
CJ/
CJ/
CJ/
CJ/
CJ
CJ
CJ
CJ
CJ
CJ
5-87
Sample Register A
Sample Register B
Sample Register C
New Pipe Register A
New Pipe Register 8
New Pipe Register C
Sample Register A
Sample Register 8
Sample Register C
New Pipe Register A
New Pipe Register 8
New Pipe Register C
Uniqueness Test:
Step
A Data B Data C Data Clock Tested
Data Verified at
13
14
15
16
AAAAH
AAAAH
AAAAH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
AAAAH
AAAAH
AAAAH
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
New Pipe Registers
New Pipe Registers
New Pipe Registers
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
New Pipe Registers
New Pipe Registers
New Pipe Registers
----------------------------------------------------------------------
17
18
19
20
21
22
23
24
25
.26
27
28
29
30
31
32
33
34
35
36
OOOOH
OOOOH
OOOOH
BBBBH
BBBBH
BBBBH
OOOOH
OOOOH
OOOOH
BBBBH
BBBBH
BBBBH
OOOOH
OOOOH
OOOOH
BBBBH
BBBBH
BBBBH
OOOOH
OOOOH
OOOOH
BBBBH
BBBBH
BBBBH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
Sample A Sample A Sample A Sample B Sample B Sample B Sample C Sample C Sample C Control Control Control ..
Sample A Sample A Sample A Sample B Sample B Sample B Sample C Sample C Sample C Control Control Control -
AJ/
BJ/
CJ/
AJ/
BJ/
CJ/
AJ/
BJ/
CJ/
AJ/
BJ/
CJ/
AJ
BJ
CJ
AJ
BJ
CJ
AJ
BJ
CJ
AJ
BJ
CJ
B,
B,
B,
B,
B,
B,
B,
B,
B,
A,
A,
A,
B,
B,
B,
B,
B,
B,
B,
B,
B,
A,
A,
A,
C
C
C
C
C
C
C
C
C
B,
B,
B,
C
C
C
C
C
C
C
C
C
B,
B,
B,
C
C
C
C
C
C
Threshold Disable Test:
Step
A Data B Data C Data Clock Tested
Data Verified at
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
OOOOH
OOOOH
OOOOH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
OOOOH
OOOOH
OOOOH
Sample Registers A, B, C
Sample Registers A, B, C
Sample Registers A, B, C
Sample Registers A, B, C
Sample Registers A, B, C
Sample Registers A, B, C
Sample Registers A, B, C
Sample Registers A, B, C
Sample Registers A, B, C
New Pipe Registers A, B, C
New Pipe Registers A, B, C
New Pipe Registers A, B, C
Sample Registers A, B, C
Sample Registers A, B, C
Sample Reg sters A, B, C
Sample Reg sters A, B, C
Sample Reg sters A, B, C
Sample Reg sters A, B, C
Sample Reg sters A, B, C
Sample Reg sters A, B, C
Sample Reg sters A, B, C
New Pipe Registers A, B, C
New Pipe Registers A, B, C
New Pipe Registers A,B,C
---------------------------------------------------------------BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
OOOOH
OOOOH
OOOOH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
OOOOH
OOOOH
OOOOH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
OOOOH
OOOOH
OOOOH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
OOOOH
OOOOH
OOOOH
Sample A - AJ/
Sample A - BJ/
Sample A - CJ/
Sample B - AJ/
Sample B - BJ/
Sample B - CJ/
Sample C - AJ/
Sample C - BJ/
Sample C - CJ/
Control - AJ/
Control - BJ/
Control - CJ/
Sample A - AJ
Sample A - BJ
Sample A - CJ
Sample B .. AJ
Sample B - BJ
Sample B - CJ
Sample C - AJ
Sample C - BJ
Sample C - CJ
Control - AJ
Control - BJ
Control - CJ
5-88
Force Disqualify Test:
Step
A Data
B Data C Data Clock Tested
Data Verified at
61
62
63
64
65
66
67
68
69
70
71
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
OOOOH
OOOOH
OOOOH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
OOOOH
OOOOH
OOOOH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
OOOOH
OOOOH
OOOOH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
OOOOH
OOOOH
OOOOH
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
New Pipe Registers
New Pipe Registers
New Pipe Registers
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
New Pipe Registers
New Pipe Registers
New Pipe Registers
72
73
74
75
76
77
78
79
80
81
82
83
84
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
OOOOH
OOOOH
OOOOH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
OOOOH
OOOOH
OOOOH
Sample A Sample A Sample A Sample B Sample B Sample B Sample C Sample C Sample C Control Control Control Sample A Sample A Sample A Sample B Sample B Sample B Sample C Sample C Sample C Control Control Control -
AJ/
BJ/
CJ/
AJ/
BJ/
CJ/
AJ/
BJ/
CJ/
AJ/
BJ/
CJ/
AJ
BJ
CJ
AJ
BJ
CJ
AJ
BJ
CJ
AJ
BJ
CJ
ERROR MESSAGES:
If an error occurs, the fo I low i ng message is displayed:
*
Test FAILED--Test Step
ecce Clock tttt Error
qqqq Clock Enables
= aaaaH
I/O Address
= rrrrH
Status Read
Status Expected = eeeeH
ssss
Where:
ssss is the Test Step in the range: 1 to 84.
ecce is the tested Clock: Sample A,
Sample B,
Sample C,
Control.
tttt is the test type:
Functional,
Uniqueness,
Disable,
Force Disqualify.
5-89
B,
B,
B,
B,
B,
B,
B,
B,
B,
A,
A,
A,
B,
B,
B,
B,
B,
B,
B,
B,
B,
A,
A,
A,
C
C
C
C
C
C
C
C
C
B,
B,
B,
C
C
C
C
C
C
C
C
C
B,
B,
B,
C
C
C
C
C
C
qqqq Is the tested Clock Enable: AJ/ BJ/ CJ/,
AJ BJ CJ,
AJ/,
BJ/,
CJ/,
AJ,
BJ,
CJ.
aaaa is the address of a Data Board Sample Register:
OC6H for Data Board A,
OD6H for Data Board B,
OE6H for Data Board C.
or a Data Board New Pipe Register:
OC4H for Data Board A,
OD4H for Data Board B,
OE4H for Data Board C.
rrrr is the Data Word read from the Status Register.
eeee is the Data Word expected from the Sample Register which should be:
AAAAH for Data Board AI (OC6H, OC4H).
BBBBH for Data Board B, (OD6H, OD4H).
CCCCH for Data Board C, (OE6H, OE4H).
NOTE: OOOOH is the expected Data Word for al I Data Boards during
Uniqueness Testing.
5-90
Clock Board Diagnostic Subtest 6
TITLE:
SAMPLE AND CONTROL CLOCKS
TARGET LOGIC:
AK, BK AND CK CLOCKS TEST
5A, 4A, 5B, 5C, 5D, 4C, 4D,
5E, 5F, 5G, 5H, 4H, 4J,
6A
Setup latches in Subtest 2
TEST DESCRIPTION:
The AK,
and the
as wei I
and the
AK/, BK, BK/, CK and CK/ clock enables for the Sample Clocks A, B, C,
Control Clock wi I I be tested for functionality and uniqueness, as well
as the ability to disable these Clocks using the Threshold Disable,
Force Disqualify Disa~le.
The Sample Clocks are tested by placing Data at the Front End of the Data
Board, issuing a Sample Clock by toggling one of the AK, BK, CK Enables,
and checking the Sample Registers to see if a bata transfer took place.
The Control Clocks are similarly tested by clocking data into the Sample
Registers, issuing a Control Clock by toggling one of the AK, BK, CK Enables,
and checking the New Pipe Registers to see if a Data transfer took place.
NOTE: The logic states of AK, AK/, BK, BK/, CK and CK/ are determined by
the current threshold at the probes. An ECl Threshold, and a VARAIABlE A
Threshold wi I I be used to provide the High and low logic states.
This test wi II require the use of the Threshold Board, and the probes.
TEST STEP INFORMATION:
Functionality Test:
Step
Data
Clock Tested
Data Verified at
-----------------------------------------------~-------------1
AAAAH Sample A - AK/, BK/, CK/
Sample Register A
Sample Register B
BBBBH Sample B - AK/, BK/, CK/
2
3
4
5
6
7
8
9
10
11
12
CCCCH
AAAAH
BBBBH
CCCCH
AAAAH
BBBBH
CCCCH
AAAAH
BBBBH
CCCCH
Sample C Control Control Control Sample A Sample B Sample C Control Control Control -
AK/,
AK/,
AK/,
AK/,
AK,
AK,
AK,
AK,
AK,
AK,
BK/ ,
BK/,
BK/ ,
BK/,
BK,
BK,
BK,
BK,
BK,
BK,
CK/
CK/
CK/
CK/
CK
CK
CK
CK
CK
CK
5-91
Sample Register C
New Pipe Register A
New Pipe Register B
New Pipe Register C
Sample Register A
Sample Register B
Sample Register C
New Pipe Register A
New Pipe Register B
New Pipe Register C
Uniqueness Test:
Step
A Data B Data C Data Clock Tested
Data Verified at
13
14
15
16
AAAAH
AAAAH
AAAAH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
AAAAH
AAAAH
AAAAH
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Regist~rsA,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
New Pipe Registers
New Pipe Registers
New Pipe Registers
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
New Pipe Registers
New Pipe Registers
New Pipe Registers
----------------------------------------------------------------------
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
OOOOH
OOOOH
OOOOH
BBBBH
BBBBH
BBBBH
OOOOH
OOOOH
OOOOH
BBBBH
BBBBH
BBBBH
OOOOH
OOOOH
OOOOH
BBBBH
BBBBH
BBBBH
OOOOH
OOOOH
OOOOH
BBBBH
BBBBH
BBBBH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
Sample A Sample A Sample A Sample B Sample B Sample B Sample C Sample C Sample C Control Control Control Sample A Sample A Sample A Sample B Sample B Sample B Sample C Sample C Sample C Control Control Control -
AKI
BKI
CKI
AKI
BKI
CKI
AKI
BKI
CKI
AKI
BKI
CKI
AK
BK
CK
AK
BK
CK
AK
BK
CK
AK
BK
CK
B,
B,
B,
B,
B,
B,
B,
B,
B,
A,
A,
A,
B,
B,
B,
B,
B,
B,
B,
B,
B,
A,
A,
A,
C
C
C
C
C
C
C
C
C
B,
B,
B,
C
C
C
C
C
C
C
C
C
B,
B,
B,
B,
B,
B,
B,
B,
B,
B,
B,
B,
A,
A,
A,
B,
B,
B,
B,
B,
B,
B,
B,
B,
A,
A,
A,
C
C
C
C
C
C
C
C
C
B, C
B, C
B, C
C
C
C
C
C
C
C
C
C
B, C
B, C
B,' C
C
C
C
C
C
C
Threshold Disable Test:
Step
A Data B Data C Data Clock Tested
Data Verified at
37 .
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
OOOOH
OOOOH
OOOOH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
OOOOH
OOOOH
OOOOH
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
New Pipe Registers
New Pipe Registers
New Pipe Registers
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
New Pipe Registers
New Pipe Registers
New Pipe Registers
---------------------------------------------------------------BBBBH CCCCH
BBBBH CCCCH
BBBBH CCCCH
BBBBH CCCCH
BBBBH CCCCH
BBBBH CCCCH
BBBBH CCCCH
BBBBH CCCCH
BBBBH CCCCH
OOOOH OOOOH
OOOOH OOOOH
OOOOH OOOOH
BBBBH CCCCH
BBBBH CCCCH
BBBBH CCCCH
BBBBH CCCCH
BBBBH CCCCH
BBBBH CCCCH
BBBBH . CCCCH
BBBBH CCCCH
BBBBH CCCCH
OOOOH OOOOH
OOOOH OOOOH
OOOOH OOOOH
Sample A Samp Ie A Samp Ie A Sample B Sample B Sample B Samp Ie C Sample C Samp Ie C Control Control Control Sample A Sample A Sample A Sample B Sample B Sample B Sample C Sample C Sample C Control Control Control 5-92
AKI
BK I
CKI
AKI
BKI
CKI
AK I
BKI
CKI
AKI
BKI
CKI
AK
BK
CK
AK
BK
CK
AK
BK
CK
AK
BK
CK
Force Disqualify Test
Step
A Data B Data
C Data
Clock Tested
Data Verified at
61
62
63
64
65
66
67
68
69
70
71
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
OOOOH
OOOOH
OOOOH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
OOOOH
OOOOH
OOOOH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
OOOOH
OOOOH
OOOOH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
OOOOH
OOOOH
OOOOH
Sample A Sample A Sample A Sample B Sample B Sample B Sample C Sample C Sample C Control Control Control Sample A Sample A Sample A Sample B Sample B Sample B Sample C Sample C Sample C Control Control Control -
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Reg sters A,
Sample Reg sters A,
Sample Reg sters A,
Sample Reg sters A,
Sample Reg sters A,
Sample Reg sters A,
New Pipe Registers
New Pipe Registers
New Pipe Registers
Sample Registers A,
Sample Registers A,
Samp1e Reg sters A,
Sample Reg sters A,
Sample Reg sters A,
Sample Reg sters A,
Sample Reg sters A,
Sample Reg sters A,
Sample Registers A,
New Pipe Registers
New Pipe Registers
New Pipe Registers
72
73
74
75
76
77
78
79
80
81
82
83
84
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
OOOOH
OOOOH
OOOOH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
OOOOH
OOOOH
OOOOH
AK/
BK/
CK/
AK/
BK/
CK/
AK/
BK/
CK/
AK/
BK/
CK/
AK
BK
CK
AK
BK
CK
AK
BK
CK
AK
BK
CK
ERROR MESSAGES:
If an error occurs, the fol lowing message is displayed:
*
Test FAILED--Test Step
cccc Clock tttt Error
qqqq Clock Enables
I/O Address
= aaaaH
Status Read
= rrrrH
Status Expected = eeeeH
ssss
Where:
ssss is the Test Step in the range: 1 to 84.
cccc is the tested Clock: Sample A,
Sample B,
Sample C,
Control
tttt is the test type:
Functional,
Uniqueness,
Disable,
Force Disqualify
5-93
B,
B,
B,
B,
B,
B,
B,
B,
B,
A,
A,
A,
B,
B,
B,
B,
B,
B,
B,
B,
B,
A,
A,
A,
C
C
C
C
C
C
C
C
C
B,
B,
B,
C
C
C
C
C
C
C
C
C
B,
B,
B,
C
C
C
C
C
C
qqqq Is the tested Clock Enable: AK/ BKI CK/,
AK BK CK,
AK/,
BK/,
CK/,
AK,
BK,
CK
aaaa is the address of a Data Board Sample Register:
OC6H for Data Board A,
OD6H for Data Board B,
OE6H for Data Board C.
or a Data Board New Pipe Register:
OC4H tor Data Board A,
OD4H for Data Board B,
OE4H for Data Board C.
rrrr Is the Data Word read from the Status Register.
eeee Is the Data Word expected trom the Sample Register which should be:
AAAAH tor Data Board A, (OC6H, OC4H).
BBBBH for Data Board B, (OD6H, OD4H).
CCCCH for Data Board C, (OE6H, OE4H).
NOTE:
OOOOH is the expected Data Word for al I Data Boards during
Uniqueness Testing.
5-94
Clock Board Diagnostic Subtest 7
TITLE:
LATCH CLOCKS, DIAGNOSTIC INTERNAL CLOCK TEST
TARGET LOGIC:
llH, IF, lG, 1H, 2H
lD, 2B, 2A, 2C, 2D
6A
Setup Latches in Subtest 2
TEST DESCRIPTION:
The Diagnostic Internal Latch Clocks A, Band C are tested for functionality
as wei I as the ability to disable these Clocks using the Normal Disable and
the Latch Disqualify Disable.
The Latch Clocks are tested by placing Data at the Front End of the Data
Board, issuing a Diagnostic Latch Clock, issui~g a Diagnostic Sample Clock,
and checking the Sample Registers to see if a Data transfer took place.
NOTE:
The Diagnostic Latch Clock is "kicked" by outputing a "1" to bit Dl
of Write Register OB8H of the Clock Board. This produces a clock pulse the
width of the 8086's Write pulse. Consecutive "kicks" can be achieved by
consecutive outputs to this port. It is never necessary to set this bit low.
TEST STEP INFORMATION:
Functionality Test:
Step
Data
Clock Tested
1
OOOOH
5555H
AAAAH
CCCCH
3333H
6666H
9999H
FFFFH
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
2
3
4
5
6
7
8
A,
A,
A,
A,
A,
A,
A,
A,
B,
B,
B,
B,
B,
B,
B,
B,
C
C
C
C
C
C
C
C
Data Verified at
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Threshold Disable Test:
Step
Data
Clock Tested
Data Verified at
----------------------------~-------------------
9
10
11
AAAAH
BBBBH
CCCCH
La.tch A
Latch B
Latch C
Sample Register A
Sample Register B
Sample Register C
5-95
A,
A,
A,
A,
A,
A,
A,
A,
B,
B,
B,
B,
B,
B,
C
C
C
C
C
C
S, C
B, C
Latch Disqualify Disable Test:
Step
Data
Clock Tested
Data Verified at
12
AAAAH
BBBBH
CCCCH
Latch A
Latch B
Latch C
Sample Register A
Sample Register B
Sample Register C
13
14
ERROR MESSAGES:
If an error occurs, the fol lowing message is displayed:
*
Test FAILED--Test Step
cccc Clock tttt Error
Diagnostic Latch Clock
I/O Address
= aaaaH
Status Read
= rrrrH
Status Expected = eeeeH
ssss
Where:
ssss is the Test Step in the range: 1 to 14.
cccc is the tested Clock: Latch A,
Latch B,
Latch C.
tttt is the test type:
Functional,
Threshold Disable,
Disqualify Disable.
aaaa is the address of a Data Board Sample Register:
OC6H for Data Board A,
OD6H for Data Board B,
OE6H for Data Board C.
rrrr is the Data Word read from the Status Register.
eeee is the Data Word expected from the Sample Register which should be:
Data for Functional Testing:
OOOOH,
5555H,
AAAAH,
CCCCH,
3333H,
6666H,
9999H,
FFFFH.
Data for Threshold Disable and
AAAAH for Data
BBBBH for Data
CCCCH for Data
Disqualify Disable Testing:
Board A.
Board B.
Board C.
5-96
Clock Board Diagnostic Subtest 8
TITLE:
LATCH CLOCKS, OR-ONLY ENABLES TEST
TARGET LOGIC:
2E, 2F, 2G, 2H
10, 2B, 2A, 2C, 20
Setup Latches in Subtest 2
TEST DESCRIPTION:
The Latch Clocks A, Band C OR-Only Enables are tested for functionality,
and the abi lity to disable these Clocks using the
the Latch Disqualify Disable.
The Latch Clocks are tested by placing Data at the Front End of the Data
Board, issuing a Diagnostic Latch Clock, issuing a Diagnostic Sample
Clock, and checking the Sample Registers to see if a Data transfer took place.
TEST STEP INFORMATION:
Functionality Test:
Step
Data
Clock Tested
Data Verified at
1
AAAAH
BBBBH
CCCCH
Latch A
Latch B
Latch C
Sample Register A
Sample Register B
Sample Register C
2
3
Uniqueness Test:
Step
4
5
6
A Data B Data C Data Clock Tested
Data Verified at
AAAAH
OOOOH
OOOOH
Latch A
Latch B
Latch C
Sample Registers A, B, C
Sample Registers A, B, C
Sample Registers A, B, C
OOOOH
BBBBH
OOOOH
OOOOH
OOOOH
CCCCH
Latch Disqualify Disable Test:
Step
A Data
B Data
C Data
Clock Tested
Data Verified at
7
8
9
AAAAH
AAAAH
AAAAH
BBBBH
BBBBH
BBBBH
CCCCH
CCCCH
CCCCH
Latch A
Latch B
Latch C
Sample Registers A, B, C
Sample Registers A, B, C
Sample Registers A, B, C
5-97
ERROR MESSAGES:
If an error occurs, the following message is displayed:
*
Test FAILED--Test Step
cccc Clock tttt Error
OR Only Enables
I/O Address
= aaaaH
Status Read
= rrrrH
Status Expected = eeeeH
Where:
ssss Is the Test Step in the range:
ssss
to 9.
cccc Is the tested Clock: Latch A,
Latch B,
Latch C.
tttt Is the test type:
Functional,
Uniqueness,
Latch Di squa I i fy DIsab.I e.
aaaa is the address of a Data Board Sample Register:
OC6H for Data Board A,
OD6H for Data Board B,
OE6H for Data Board C.
rrrr Is the Data Word read from the Status Register.
eeee Is the Data Word expected from the Sample Register which should be:
AAAAH for Data Board A.
BBBBH for D~ta Board B.
CCCCH for Data Board C.
NOTE:_ OOOOH is the expected data word for al I Data Boards during
Uniqueness Testing.
5-98
Clock Board Diagnostic Subtest 9
TITLE:
LATCH CLOCKS, AR, BR AND CR CLOCKS TEST
TARGET LOGIC:
lF,
10,
lE
2E,
2B,
1G,
2A,
2F,
2C,
1H,
20
2G,
2H
Setup Latches in Subtest 2
TEST DESCRIPTION:
The AR,.. AR/, BR, BR/, CR and CRI Clock Enables for Latch Clocks A, B, and C
are tested for functionality and uniqueness, as wei I as the ability to disable
these Clocks using the Threshold Disable, and the Latch Disqualify Disable.
The Latch Clocks are tested by placing Data at the Front End of the Data
Board, Issuing a Latch Clock by toggling one of the AR, BR, CR Enables,
and issuing a Diagnostic Internal Sample Clock' and checking the Sample
Registers to see if a Data transfer took place.
NOTE: The Logic states of AR, AR/, BR, BR/, CR and CRI are determined by
the current threshold at the probes. AnECL Threshold, and a VARIABLE A
Threshold wil I be used to provide the High and Low logic states.
This test requires the use of the Threshold Board, and the probes.
TEST STEP INFORMATION:
Functionality Test:
Step
Data
Clock Tested
1
2
3
MAAH
BBBBH
CCCCH
AAAAH
BBBBH
CCCCH
Latch
Latch
Latch
Latch
Latch
Latch
4
5
6"
Data Verified at
A - AR/, BR/, CRI
B - AR/, BR/, CRI
C - AR/, BR/, CRI
A - AR, BR, CR
B - AR, BR, CR
C - AR, BR, CR
Sample
Sample
Sample
Sample
Sample
Sample
Register
Register
Register
Register
Register
Register
A
B
C
A
B
C
Uniqueness Test:
Step
7
8
9
10
11
12
13
A Data B Data C Data Clock Tested
Data Verified at
AAAAH
AAAAH
AAAAH
OOOOH
OOOOH
OOOOH
OOOOH
Sample
Sample
Sample
Sample
Sample
Sample
Sample
OOOOH
OOOOH
OOOOH
BBBBH
BBBBH
BBBBH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
CCCCH
Latch
Latch
Latch
Latch
Latch
Latch
Latch
AAABBBC-
5-99
ARI
BRI
CRI
ARI
BRI
CRI
ARI
Registers
Registers
Registers
Registers
Registers
Registers
Registers
A,
A,
A,
A,
A,
A,
A,
B,
B,
B,
B,
B,
B,
B,
C
C
C
C
C
C
C
14
15
16
17
18
19
20
21
22
23
24
OOOOH
OOOOH
AAAAH
AAAAH
AAAAH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
BBBBH
BBBBH
BBBBH
OOOOH
OOOOH
OOOOH
CCCCH
CCCCH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
CCCCH
CCCCH
CCCCH
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
CCAAABBBCCC-
BR/
CR/
AR
BR
CR
AR
BR
CR
AR
BR
CR
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
A,
A,
A,
A,
A,
A,
A,
A,
A,
A,
A,
B,
B,
B,
B,
B,
B,
B,
B,
B,
B,
B,
C
C
C
C
C
C
C
C
C
C
C
A,
A,
A,
A,
A,
A,
A,
A,
A,
A,
A,
A,
A,
A,
A,
A,
A,
A,
B,
B,
B,
B,
B,
B,
B,
B,
B,
B,
B,
B,
B,
B,
B,
B,
B,
B,
C
C
C
C
C
C
C
C
C
C
C
C
C
Threshold Disable Test:
Step
A Data B Data C Data Clock Tested
Data Verified at
25
.26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42 .
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
---------------------------------------------------------------BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
AAABBBCCCAAABBBCCC-
AR/
BR/
CR/
AR/
BR/
CR/
AR/
BR/
CR/
AR
BR
CR
AR
BR
CR
AR
BR
CR
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
e
C
C
C
C
Latch Disqualify Disable Test:
Step
A Data B Data C Data Clock Tested
Data Verified at
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
---------------------------------------------------------------------BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
CCCCH Latch A - AR/
CCCCH Latch A - BR/
CCCCH Latch A - CR/
CCCCH Latch B - AR/
CCCCH Latch B - BR/
CCCCH Latch B - CR/
CCCCH . Latch C - AR/
CCCCH Latch C - BR/
CCCCH Latch C - CR/
CCCCH Latch A - AR
CCCCH Latch A - BR
CCCCH Latch A - CR
CCCCH Latch B - AR
CCCCH Latch B - BR
CCCCH Latch B - CR
CCCCH Latch C - AR
CCCCH Latch C - BR
CCCCH Latch C - CR
5-100
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
A,
A,
A,
A,
A,
A,
A,
A,
A,
A,
A,
A,
A,
A,
A,
A,
A,
A,
B,
B,
B,
B,
B,
B,
B,
B,
B,
B,
B,
B,
B,
B,
B,
B,
B,
B,
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
ERROR MESSAGES:
If an error occurs, the fol lowing message is displayed:
* Test FAILED--Test Step
cccc Clock tttt Error
qqqq Clock Enable
I/O Address
= aaaaH
Status Read
= rrrrH
Status Expected = eeeeH
ssss
Where:
ssss is the Test Step in the range: 1 to 60.
cccc is the tested Clock: Latch A,
Latch B,
Latch C.
tttt is the test type:
Functional,
Uniqueness,
Threshold Disable,
Latch Disqualify Disable.
qqqq is the tested Clock Enable: AR/ BR/ CRt,
AR BR CR,
AR/,
BR/,
CRt,
AR,
BR,
CR.
aaaa Is the address of a Data Board Sample Register:
OC6H for Data Board A,
OD6H for Data Board B,
OE6H for Data Board C.
rrrr Is the Data Word read from the Status Register.
eeee is the Data Word expected from the Sample Register which should be:
AAAAH for Data Board A.
BBBBH for Data Board B.
CCCCH for Data Board C.
NOTE:
OOOOH is the expected data word for all Data Boards during
Uniqueness Testing.
5-101
Clock Board Diagnostic Subtest 10
TITLE:
LATCH CLOCKS AS, BS AND CS CLOCKS TEST
TARGET LOGIC:
2B, 2A, 2C, 20, 10, 2E, 2F, 2G, 2H
3A
Setup Latches in Subtest 2
TEST DESCRIPTION:
The AS, AS/, BS, BS/, CS and CS/ Clock Enables for Latch Clocks A, Band C
are tested for functionality and uniqueness, as wei I as the abi Ilty to disable
these Clocks using the Threshold Disable.
The Latch Clocks
Board, asserting
Latch Clock, and
Sample Registers
are tested by placing Data at the Front End of the Data
the appropriate AS, BS, CS Enables, issuing a Diagnostic
issuing a Diagnostic Internal Sample Clock and checking the
to see if a Data transfer took place.
NOTE 1: This test Is different than the rest due to the transparent
mode of the 10130 Latches on the Data Boards. When the Latch Clock Is held In
a low state, the 10130 Latches on the Data Board are transparent, I.e., the "Q"
output fol lows the "0" Input. When the Latch Clock goes high, this latches the
Data Into the 10130's and the "0" Input then becomes a don't care.
In this test, Instead of toggling the enable to the AS, BS or CS, It
Is held active and a Diagnostic Int Clock Issued. This causes the Data Board
to be In Latch Mode, Instead of being transparent.
NOTE 2: The Logic states of AR, AR/, BR, BR/, CR and CR/ are determined by
the current threshold at the probes. An ECL Threshold, and a VARIABLE A
Threshold are used to provide the High and Low logic states.
This test requires the use of the Threshold Board, and the probes.
TEST STEP INFORMATION:
Functionality Test:
Step·
Data
Clock Tested
1
2
3
AAAAH
BBBBH
CCCCH
AAAAH
BBBBH
CCCCH
Latch
Latch
Latch
Latch
Latch
Latch
4
5
6
ABCABC-
AS/,
AS/,
AS/,
AS,
AS,
AS,
Data Verified at
BS/,
BS/,
BS/,
BS,
BS,
BS,
CS/
CS/
CS/
CS
CS
CS
5-102
Sample
Sample
Sample
Sample
Sample
Sample
Register
Register
Register
Register
Register
Register
A
B
C
A
B
C
Uniqueness Test:
Step
A Data
B Data C Data Clock Tested
Data Verified at
OOOOH
OOOOH
OOOOH
BBBBH
BBBBH
BBBBH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
BBBBH
BBBBH
BBBBH
OOOOH
OOOOH
OOOOH
Samp e
Samp e
Samp e
Samp e
Samp e
Samp e
Samp e
Samp e
Samp e
Samp e
Samp e
Samp e
Samp e
Samp e
Samp e
Sample
Sample
Sample
---------------------------------------------------------------------7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
AAAAH
AAAAH
AAAAH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
AAAAH
AAAAH
AAAAH
.OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
CCCCH
CCCCH
CCCCH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
CCCCH
CCCCH
CCCCH
Latch A Latch A Latch A LatchB Latch B Latch B Latch C Latch C Latch C Latch A Latch A Latch A Latch B Latch B Latch B Latch C Latch C Latch C -
AS/
BS/
cst
AS/
BS/
cst
AS/
BS/
cst
AS
BS
CS
AS
BS
CS
AS
BS
CS
Registers A,
Registers A,
Registers A,
Reg sters A,
Reg sters A,
Reg sters A,
Reg stersA,
Reg sters A,
Reg sters A,
Reg sters A,
Reg sters A,
Reg sters A,
Registers A,
Registers A,
Registers A,
Registers A,
Registers A,
Registers A,
B,
B,
B,
B,
B,
B,
B,
B,
B,
B,
B,
B,
B,
B,
B,
B,
B,
B,
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
B,
B,
B,
B,
B,
B,
B,
B,
B,
B,
B,
B,
B,
B,
B,
B,
B,
B,
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
Threshold Disable Test:
Step
A Data
B Data C Data
Clock Tested
Data Verified at
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
Latch
Latch
Latch
Latch
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
---------------------------------------------------------------CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
Latc~
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
AAABBBCCCAAABBBCCC-
AS/
BS/
cst
AS/
BS/
cst
AS/
BS/
cst
AS
BS
CS
AS
BS
CS
AS
BS
CS
ERROR MESSAGES:
If an error occurs, the fol lowing message is displayed:
* Test
FAILED--Test Step
cccc Clock tttt Error
qjqq Clock Enable
= aaaaH
I 0 Address
ssss
5-103
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Reg sters
Reg sters
Reg sters
Reg sters
Reg sters
Reg sters
Registers
Registers
Registers
Registers
A,
A,
A,
A,
A,
A,
A,
A,
A,
A,
A,
A,
A,
A,
A,
A,
A,
A,
Status Read
= rrrrH
Status Expected = eeeeH
Where:
ssss is the Test Step In the range: 1 to 42.
cccc is the tested Clock: Latch A,
Latch B,
Latch C.
tttt Is the test type:
Functional,
Uniqueness,
Threshold Disable.
qqqq Is the tested Clock Enable: AS/ BS/ CS/,
AS BS CS,
AS/,
BS/,
CS/,
AS,
BS,
CS.
aaaa Is the address of a Data Board Sample Register:
OC6H for Data Board A,
OD6H for Data Board B,
OE6H for Data Board C.
rrrr is the Data Word read from the Status Register.
eeee is the Data Word expected from the Sample Register which should be:
AAAAH for Data Board A.
BBBBH for Data Board B.
CCCCH for Data Board C.
NOTE: OOOOH Is the expected data word for al I Data Boards during
Uniqueness Testing.
5-104
Clock Board Diagnostic Subtest 11
TITLE:
DECADE FREQUENCY AND MULTIPLIER DIVIDE BY TEST
TARGET LOGIC:
100, 12C, llC
10C
11 B
9E, 10E, 9C, 90
Setup Latches in Subtest 2
100Mhz Oscilator Descrete Componets (Grid 8B-6B)
TEST DESCRIPTION:
This test wi I I check the Clock Decade multiplexer, (Decade), and the divide
by counter, (Multiplier).
The 100Mhz, 10Mhz, lMhz, 100Khz, 10Khz, 1Khz and 100hz Clocks wi I I be tested
with various Multipliers. The Clock frequencies wi I I be verified within a
ballpark range, but this wi II only verify that the multiplexer is selecting
different Decades.
A frequency counter is required to adjust/verify the Time
Period of the 100Mhz Clock.
When the faster Clock frequencies are being tested, the testing time is very
quick, and the fol lowing message wi I I be displayed:
>Counting Clock Pulses •••
During the 1Khz test, (this one takes a whi Ie), the fol lowing message
wi II be displayed:
>Counting Clock Pulses ••• 4 seconds
During the 100hz test, (this one takes a long time), the fol lowing
message wi I I be displayed:
>Counting Clock Pulses ••• 20 seconds
During the testing of the Multiplier Divide by counter, the fol lowing
message wi I I be displayed:
>Checking the Multipl ier Divide by •••
5-105
TEST STEP INFORMATION:
Decade Frequency Test:
Step
Decade Muit
Clks Expected
Clks Minimum
Clks Maximum
0
1
2
3
4
5
6
256
256
256
256
256
256
256
128
128
128
128
128
128
128
384
384
384
384
384
384
384
Clks Minimum
Clks Maximum
-------------------------------------------------------------------1
2
3
4
5
6
7
8
8
8
8
8
8
8
Multiplier Divide by Test:
Step
Dec'ade Mult
Clks Expected
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
11189
11195
11197
111111
111122
111134
111148
"'167
·191
111224
111270
111336
"'450
256
256
-------------------------------------------------------------------11183
8
*
*
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Step
Step
Step
Step
Step
Step
Step
Step
Step
Step
Step
Step
Step,
0
8 Clock Count
9 Clock C9unt
10 Clock Count
11 Clock Count
12 Clock Count
13 Clock Count
14 Clock Count
15 Clock Count
16 Clock Count
17 Clock Count
18 Clock Count
19 Clock Count
20 Clock Count
0
0
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
NOTE 1: The values above preceeded by 111 are aproximate values. They were
selected by running the test a single time on a single K205. This value
wll I vary from System to System due to minor differences in the CPU's Clock
frequency, and other hardware propagation times. The precise values are not
important as long as Clock count increments whl Ie the Multiplier incrementes.
NOTE 2: Test Steps 22 and 23 are different from the rest. When the
Multiplier goes 'from 13 to 14, and from 14 to 15, the Clock count no longer
fol lows the slow-linear increase that It fol lowed with the Multiplier range
of 0 to 12. The Clock count aproximately doubles, so a bal Iparklng method
of 25~ clocks Inside the 0 to 512 range is used.
5-106
ERROR MESSAGES:
If an error occurs, the fol lowing message Is displayed:
* Test
FAILED--Test Step
hmsg Error
Decade x: ffff Clock
= mmmmD
Mu Iti p I I er
Clocks counted = ccccD
MI n Clock count = 11110
Max Clock count = hhhhD
ssss
Where:
ssss Is the Test Step In the range: 1 to 23.
hmsg Is."Clock Frequency Counting",
"Mu Itip I I er Clock 0 Iv I de by".
x
is the selected Decade: 0, 1, 2, 3, 4, 5, 6.
ttff Is the Clock frequency:
100
10
1
100
10
1
100
Mhz,
Mhz,
Mhz,
Khz,
Khz,
Khz,
hz.
mmmm Is the current Multiplier value, range Is 0 to 15.
cccc Is the Number of clocks counted, range is 0 to 512.
I I II is the Minimum number of clocks that could be counted for frequency.
hhhh is the Maximum number of clocks that could be counted for frequency.
5-107
Clock Board Diagnostic Subtest 12
LEVEL RAMs DATA INTEGRITY TEST
TITLE:
TARGET LOGIC:
llE, llF
11 J
12F, 12G
12D,10D,12E
Setup Latches in Subtest 2
TEST DESCRIPTION:
. The Level RAMs on the Clock Board are organized as 512 x 4. They are written
to by the Control Board, and read Into the highest nibble of the word from
port BOH of the Clock Board.
The Level RAM's Data Integrity is checked by writing al I 16 possible values
to the RAM, and reading it back to verify that each Data Bit is functional
and unique.
TEST STEP INFORMATION:
Data Integrity Test:
Step
1.
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Data
OOOOH
0001H
0002H
0003H
0004H
0005H
0006H
0007H
0008H
0009H
OOOAH
OOOBH
OOOCH
OOODH
OOOEH
OOOFH
Address Locations
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
-
511
511
511
511
511
511
511
511
511
511
511
511
511
511
511
511
5-108
ERROR MESSAGES:
If an error occurs, the fol lowing message is displayed:
* Test FAILED--Test Step ssss
Level RAM Data Integrity Error
Diagnostic Internal Clock
Byte Count
= ccccD
= rrrrH
Data Read
Data Expected = eeeeH
Where:
ssss is the Test Step In the range: 1 to 16.
cccc is RAM byte count, (address) in the range of 0 to 511.
rrrr is the Data Word read from the Level RAMS.
eeee is the Data Word expected from the Level RAMS which should be:
OOOOH,
0001H,
0002H,
0003H,
0004H,
0005H,
0006H,
0007H,
0008H,
0009H,
OOOAH,
OOOBH,
OOOCH,
OOODH,
OOOEH,
OOOFH.
5-109
Clock Board Diagnostic Subtest 13
TITLE:
LEVEL RAMs ADDRESS INTEGRITY TEST
TARGET LOGIC:
110
1t G, 12H
l1E,,11F
11 J
12F, 12G
120, 100, 12E
Setup Latches in Subtest 2
TEST DESCRIPTION:
The Level RAMs address Is provided by dual counters which provide eight
address lines which can address 256 locations. An additions tllp tlop toggles
back and torth between the two 10422 RAM Chips. on each Write/Read, to allow
the access ot 512 RAM locations.
The Level RAMs are tested tor addressing uniqueness. This wi II verity that
each ot 512 locations can be written to independently ot all other locations.
TEST STEP INFORMATION:
Step 1.
An incrementing Data pattern trom OOH to OFHis written to RAM,
which repeats atter each 1~ locations. This verities address lines
AO, Al, A2 and A3.
Step 2.
A Block Incrementing Data pattern trom OOH to OFH is written to RAM,
which repeats atter each 256 locations. This verities address lines
A4, A5, A6 and A7.
Step 3.
A Block Data pattern ot 05H and OAH Is written to RAM, which covers
all 512 locations. This verities that both ot the 10422 RAM chips are
written to.
ERROR MESSAGES:
It an error occurs, the tol lowing message is displayed:
* Test FAILED--Test Step ssss
Level RAM Address Uniqueness Error
Diagnostic Internal Clock
Byte Count
= ccccD
Data Read
= rrrrH
Data Expected = eeeeH
5-110
Where:
ssss Is the Test Step in the range: 1 to 3.
cccc is RAM byte count, (address) In the range of 0 to 511.
rrrr Is the Data Word read from the Level RAMS.
eeee Is the Data Word expected from the Level RAMS which should be:
OOOOH,
000lH,
0002H,
0003H,
0004H,
0005H,
0006H,
0007H,
OOOSH,
0009H,
OOOAH,
OOOBH,
OOOCH,
OOODH,
OOOEH,
OOOFH.
5-111
Clock Board Diagnostic Subtest 14
TITLE:
LEVEL RAMs CONTROL TEST
TARGET LOGIC:
110
11 G,
l1E,
11 J
12F,
120,
12H
l1F
12G
100, 12E
Setup Latches in Subtest 2
TEST DESCRIPTION:
This Subtest verifies the functionality of the Control Logic associated
with the Level RAM.
The First Test Step checks the odd/even toggling of the level ram. Each
Consecutive write operation to the RAM should toggle back and forth between the
"Even 10422" RAM chip, and the "ODD 10422" RAM chip. A "0" latch is acting as a
flip flop, and providing a write enable signal to only one RAM chip. An OAH
wi II be written to al I Even addresses and a 05H to al I Odd.
The Second Test Step checks the Level RAM Write Enable/Disable function.
The Level RAM is Write enabled when the signals 'ARMED' and 'TRACED' from
the Control Board are both active.
Thl.s test does 7 writes with the fol lowl ng conditions:
LEVEL
0
1
2
3
4
5
5
ARMED
1
1
1
1
1
1
0
TRACED
1
1
0
0
1
1
1
RESULT
0
1
not recorded
not recorded
4
5
not recorded
The Third Test Step checks the Recirculation feature of the Level RAM.
The Data Is read out of the 10422 RAM chips, looped back, and written back in.
This is checked by writing an Incrementing pattern into the RAM, and then
reading It back, verifying the Data Integrity.
The Data is then read back a second time and verified. On the second read,
the Data wi II be shifted by one Address location from the Recirculation.
5-112
The Fourth Test Step checks the Level RAM reset persistence by first fi I ling
the RAM with a value of OOH, then holding the reset line to the RAM address
counters active, and hammering address location 0 by performing 512
consecutive write operations. This should modify the Data Value at location 0,
but the other 511 locations should be unchanged. AI I 512 locations are read
back and verified.
TEST STEP INFORMATION:
Step
Data Even Locations
Data Odd Locations
OOOAH
0005H
Step
Data
Address
2
OOOOH
0001H
0004H
0005H
000
001
002
003
Step
Data
Address
4
0005H
OOOOH
OOOOH
000
001
002
OOOOH
OOOOH
510
511
(0005H in Location 000 Only)
ERROR MESSAGES:
If an error occurs, the fol lowing message is displayed:
*
Test FAILED--Test Step
hmsg Error
Diagnostic Internal Clock
Byte Count
= ccccD
Data Read
= rrrrH
Data Expected = eeeeH
ssss
Where:
ssss is the Test Step in the range: 1 to 4.
hmsg is Level
Level
Level
Level
RAM
RAM
RAM
RAM
odd/even Toggle,
Write enable/disable,
Recirculation,
Hammer/Addr Reset.
cccc is RAM byte count, (address) in the range of 0 to 511.
rrrr is the Data Word read from the Level RAMS.
5-113
eeee is the Data Word expected from the Level RAMS which should be:
Odd/Even Test:
0005H,
OOOAH.
Write Disable/Enable Test:
OOOOH,
0001H,
0004H,
0005H.
Recirculation Test:
OOOOH,
0001H,
0002H,
0003H,
0004H,
0005H,
0006H,
0007H,
OOOSH,
0009H,
OOOAH,
OOOBH,
OOOCH,
OOODH,
OOOEH,
OOOFH.
Hammer/Address Reset Test:
0005H,
OOOOH.
5-114
K205 LOGIC ANALYZER THRESHOLO/GPIB/RS-232 BOARD DIAGNOSTIC
DIAGNOSTIC OVERVIEW
This section describes the subtests executed on the K205 Threshold/
GPIB/RS-232 Board, how Error Reporting is accomplished, and the concept
behind each subtest program.
The Threshold/GPIB/RS-232 board diagnostics is divided into nine subtests,
each of which is described individually on the fol lowing pages.
Subtest 1 is a DAC 7541 linearity test; subtest 2 is a DAC 7533 linearity
test; subtest 3 is a Multiplexer/threshold test, subtest 4 is a serial I/O
#1 test; subtest 5 is a serial I/O #2 test, subtest 6 is a 8253 counter mode
test; subtest 7 through subtest 9 are GPIB internal logic tests (the GPIB
cable and operator intervene flag should not be set); subtest 7 is GPIB
control status test; subtest 8 is GPIB MPU interrupt logic test; subtest 9
is GPIB data out register and parallel pol I response register test.
Subtests 4 and 5· require a RS-232 wrap back connector instal led to perform the
test.
Only a part of the GPIB logic is checked in the GPIB internal test (i.e.
subtests 7 through 9 check internal logic only); external handshake logic
is not tested.
NOTE:
The 'TARGET LOGIC' listed in each subtest description
does not necessari Iy include al I of the logic which could affect
the operation of the subtest.
SUBTEST CATEGORY
1.
2.
3.
4.
5.
6.
7.
8.
9.
DAC 7541 LINEARITY TEST
DAC 7533 LINEARITY TEST
MUX/THRESHOLD LOGIC TEST
SERIAL I/O #1 TEST
SERIAL I/O #2 TEST
TIMER 8253 COUNTER 0 TEST
GPIB INTERNAL CONTROL LINE TEST
GPIB INTERNAL MPU INTERRUPT LOGIC TEST
GPIB INTERNAL DATA REGISTER TEST
ERROR COUNT CATEGORY
1.
2.
3.
4.
5.
6.
7.
8.
9.
SUBTEST
SUBTEST
SUBTEST
SUBTEST
SUBTEST
SUBTEST
SUBTEST
SUBTEST
SUBTEST
1 ERROR COUNT.
2
3
4
5
6
7
8
9
ERROR
ERROR
ERROR
ERROR
ERROR
ERROR
ERROR
ERROR
COUNT.
COUNT.
COUNT.
COUNT.
COUNT.
COUNT.
COUNT.
COUNT.
5-115
Threshold Diagnostic Subtest
TITLE:
DAC 7541 liNEARITY TEST
TARGET lOGIC:
5E, 6E, 88, 7F, 8F, 8A
7A, 7E, Q2
and power supply +5.0V, -5.2V, -2.0V, AGND, -10.0V, +10.0V,
V88(+3.0V), +15V(divided as +7.5V), -15V(dlvided as -7.5V)
TEST DESCRIPTION:
The DAC 7541 linearity is functionally tested by using the +10.0V, -10.0V,
AGND, -2.0V, -5.2V, +5.0V, +3.0V, +7.5V, -7.5V, +O.OOV, +1.30V and -1.40V
as reference voltage, multiplexed through 7F as noninverting input, and
wrlting data into 8A as inverting input until Q2 toggles Its state. The
ADC status Is then verified by reading port 04H bit o.
When the reference voltage is +10.0V, the DAC 7541 is initially programmed
to -10.0V, so Q2 is turned on. The ADC status bit is equal to 0 which
increments the DAC 7541 output voltage until the ADC status bit toggles its
state.
When the reference voltages are -10.0V, AGND, -2.0V, -5.2V, +5.0V, +3.0V,
+7.50V, -7.50V, DVM Input, +1.30V, and -1.40V, the DAC 7541 Is initially
programmed to +10.0V, so Q2 Is turned off. The ADC status bit is equal to 1,
decrementing the DAC 7541 output voltage unti I the ADC status bit toggles
its state.
TEST STEP INFORMATION:
Step
Reference Voltage
Initial 7541 Data Voltage
Initial ADC Status
-------------------------------------------------------------------------1
2
3
4
5
6
7
8
9
10
11
12
+10.0V
-10.0V
AGND
-2.0V
-5.2V
+5.0V
V88(+3.0V)
+15V/2
-15V/2
DVM
-ECl
+TTL
OFFFH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
(-10.0V)
(+10.0V)
(+10.0V)
(+10.0V)
(+10.0V)
(+10.0V)
(+10.0V)
(+10.0V)
(+10.0V)
(+10.0V)
(+10.0V)
(+10.0V)
5-116
o
1
1
1
1
1
1
1
1
1
1
1
ERROR MESSAGE:
If an error occurs, the fol lowing message is displayed:
* Test FAILED--Test Step zz
DAC 7541 Linearity Test
Voltage Expected
= see.eee
Voltage Lower Limit = suu.uuu
Voltage Upper Limit = sll.1 II
Actual Voltage Read = saa.aaa
ADC Status Expected = x
ADC Status Expected = y
Where zz should be in the range of 1 through 12
s should be + or ee.eee should be in the range of 00.000 through 10.000
uu.uuu should be 9.940, 10.235, 0.300, 2.350, 5.625, 4.820
2.700, 7.380, 7.980, 0.300, 1.000, 1.700
I I • I I I shou Id be 10.240, 9.935, 0.300, 1.750, 5.025, 5.420
3.300, 7.980, 7.380, 0.300, 1.600, 1.100
aa.aaa should be in the range of 00.000 through 10.000
x,y should be 0 or 1
5-117
Threshold Diagnostic Subtest 2
TITLE:
DAC 7533 LINEARITY TEST
TARGET LOGIC:
60, 48, 128, 98, 9A, 4A, 5A, lOA,
6F, 7A, SA, Q2, SF, 5E, 6E, S8
TEST DESCRIPTION:
The DAC 7533 linearity is functionally tested by using the DAC 7541 as
reference voltage. VAR A and VAR 8 are multiplexed through 6F as the
. noninverting input of 7A, and continues incrementing or decrementing the
VAR A or VAR 8 voltage by writing to port OSH or OAH untl I the ADC output bit
toggles its state.
When the DAC 7541 reference voltage is +10.0V, the DAC 7533 is initially
programmed to -10.0V, so Q2 is turned off and the ADC status bit is equal
to 1. When the DAC 7541 reference voltages are -9.9S0V, -5.0V, O.OOV, and
+5.0V, DAC 7533 is Initialized to +10.0V, so Q2 i~ turned on, and the ADC
Is equal to O.
When VAR A and VAR 8 are being teste~, each DAC 7533 contains five voltage
levels, -9.9S0V, -5.0V, O.OOV, +5.00V, and +10.00V.
TEST STEP INFORMATION:
Step
1
2
3
4
5
6
7
S
9
10
Reference Voltage
-9.9S0V
-5.0V
-O.OOOV
+5.0V
+10.00V
-9.9S0V
-5.0V
-O.OOOV
+5.0V
+10.00V
(7541 )
<7541 )
(7541 )
(7541 )
(7541 )
<7541 )
(7541 )
<7541 )
(7541 )
(7541 )
Initial 7533 Data Voltage
Initial ADC Status
(VAR
(VAR
(VAR
(VAR
(VAR
(VAR
(VAR
(VAR
(VAR
(VAR
o
o
OOOOH
OOOOH
OOOOH
OOOOH
OFFFH
OOOOH
OOOOH
OOOOH
OOOOH
OFFFH
A +10.0V)
A +10.0V)
A +10.0V)
A +1 O.OV)
A -10.0V)
8 +10.0V)
8 +10.0V)
8 +10.0V)
8 +10.0V)
8 -10.0V)
ERROR MESSAGE:
If an error occurs, the fol lowing message is displayed:
* Test FAILED--Test Step zz
DAC 7533 Li near i ty Test
Voltage Expected
= see.eee
Voltage Lower Limit = suu.uuu
Voltage Upper Limit = sl 1.1 I I
Actual Voltage Read = saa.aaa
ADC Status Expected = x
ADC Status Expected = y
5-11S
o
o
1
o
o
o
o
1
Where zz should be In the range of 1 through 10
s should be + or ee.eee should be in the range of 00.000 through 10.000
uu.uuu should be 10.220, 5.620, 0.500, 4.620, 9.740
I I • I I I should be
9.740, 4.620, 0.500, 5.620, 10.240
aa.aaa should be in the range of 00.000 through 10.000
x,y should be 0 or 1
5-119
Threshold Diagnostic Subtest 3
TITLE:
THRESHOLD/MUX. LOGIC TEST
TARGET LOGIC:
40, 58, lA, 10, 18, lC, 2A, 20
5F, 7A, 7E, 5E, 6E, 88, 8A, 8F
and Q2.
TEST DESCRIPTION:
The Threshold/mux's logic Is functionally tested by using the THO through TH5
as reference voltages. These voltages are multiplexed through 5F and supplied
as the nonlnvertlng Input to 7A. The OAC 7541 Is Initially programmed to
+10.0V and decrements the output voltages unti I the AOC output status bit
toggles Its state.
Reference voltages for -ECl, -TTL, -VAR A, and -VAR 8 are present for each
threshold channel. The -ECl is +1.300V, -TTL Is -1.400V, -VAR A Is +5.0V, and
-VAR 8 is -5.0V.
Testing occurs for threshold channels THO through TH5. The original ADC
status bit should be 1 when the DAC 7541 is Initialized to +10.0V.
TEST STEP INFORMATI ON:
Step
logic TH Channel
Initialized 7541 Voltage
Initial ADC Status
---------------------------------------------------------------------------1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
24
24
-ECl
-Eel
-Eel
-Eel
-Eel
-Eel
-VAR
-VAR
-VAR
-VAR
-VAR
-VAR
-TTL
-TTL
-TTL
-TTL
-TTL
-TTL
-VAR
-VAR
-VAR
-VAR
-VAR
-VAR
A
A
A
A
A
A
8
8
8
8
8
8
0
1
2
3
4
5
0
1
2
3
4
5
0
1
2
3
4
5
0
1
2
3
4
5
+10.0V
+10.0V
+10.0V
+10.0V
+10.0V
+10.0V
+10.0V
+10.0V
+10.0V
+10.0V
+10.0V
+10.0V
+10.0V
+10.0V
+10.0V
+10.0V
+10.0V
+10.0V
+10.0V
+10.0V
+10.0V
+10.0V
+10.0V
+10.0V
5-120
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ERROR MESSAGE:
If an error occurs, the fol lowing message is displayed:
* Test FAILED--Test Step zz
Threshold/Mux. Logic Test
?????? Threshold Testing
TH Channel n Testing
Voltage Expected
= see.eee
Voltage Lower Limit = suu.uuu
Voltage Upper Limit = sll.1 I I
Actual Voltage Read = saa.aaa
ADC Status Expected = x
ADC Status Expected = y
Where
z~
should be in the range of 1 through 24
?????? should be -ECL, -VAR A, -TTL, -VAR B
n should be in the range of 0 through 5
s should be + or ee.eee should be 1.300, 5.000, 1.400, 5.000
uu.uuu should be 0.980, 4.800, 1.720, 5.440
I I • I I I should be 1.620, 5.400, 1 .080, 4.800
aa.aaa should be in the range of 00.000 through 10.000
x,y should be
o or
1
5-121
Threshold Diagnostic Subtest 4
TITLE:
SERIAL I/O PORT #1 TEST
TARGET LOGIC:
120, 14A, 13A, BE
TEST DESCRIPTION:
Serial I/O port #1 is functionally tested by using USART #1 as a transmitter/
receiver to transmit an B bit data pattern and receive the transmitted bytes
through the wrap back, RS-232 connector within a specified time window
(95% through 105%).
The RS-232-. wrap back connector is conf i gured as fo II ows:
Pin 2, CTS (clear to send); short to Pin 3, RTS (request to send),
Pin 4, DSR (data set ready); short to Pln5, DTR (data terminal ready),
Pin 6, RxD (received data); short to Pin 20, TxD (transmitted data).
The fol lowing patterns are transmitted:
OAAH, 055H, OCCH, 033H, 01H, 02H, 04H, OBH, 10H, 20H, 40H, BOH.
The fol lowing baud rates are tested:
110, 150, 300, 600, 1200, lBOO, 2400, 4BOO, 9600
TEST STEP INFORMATION:
Test Step
1
13
25
37
49
61
-73
through
through
through
through
through
through
through
B5 through
97 through
Baud Rate
12
24
36
4B
60
72
B4
96
lOB
110
150
300
600
1200
lBOO
2400
4BOO
9600
Data Pattern
OAAH,55H,OCCH,33H,01H,02H,04H,OBH,10H,20H,40H,BOH
OAAH,55H,OCCH,33H,01H,02H,04H,08H,10H,20H,40H,BOH
OAAH,55H,OCCH,33H,01H,02H,04H,08H,10H,20H,40H,BOH
OAAH,55H,OCCH,33H,01H,02H,04H,OBH,10H,20H,40H,BOH
OAAH,55H,OCCH,33H,OlH,02H,04H,08H,10H,20H,40H,BOH
OAAH,55H,OCCH,33H,01H,02H,04H,08H,10H,20H,40H,BOH
OAAH,55H,OCCH,33H,01H,02H,04H,08H,10H,20H,40H,BOH
OAAH,55H,OCCH,33H,01H,02H,04H,OBH,10H,20H,40H,BOH
OAAH,55H,OCCH,33H,01H,02H,04H,08H,10H,20H,40H,BOH
5-122
ERROR MESSAGE:
1. If an error for transmitter buffer not empty occurs,
the fol lowing message is displayed:
* Test FAILED--Test Step zz
Serial I/O Port 1 Test
Transmitter Buffer Not Empty
Testing Baud Rate
= bbbb
Status Byte Read
= rrH
where zz should be in the range of 1 through 108
bbbb should be 110, 150, 300, 600, 1200, 1800, 2400, 4800, 9600
rr should be in the range of 00 through FF
2. If an error for no character received occurs, .
the fol lowing message is displayed:
* Test FAILED--Test Step zz
Serial I/O Port 1 Test
No Character Received
Tesing Baud Rate
= bbbb
Status Byte Read
= rrH
where zz should be In the range of 1 through 108
bbbb should be 110, 150, 300, 600, 1200, 1800, 2400, 4800, 9600
rr should be in the range of 00 through FF
3. If an error for charac}er received early occurs,
the fol lowing message is displayed:
* Test FAILED--Test Step zz
Serial I/O Port 1 Test
Character Received Early
= bbbb
Tesing Baud Rate
Minimum Expected Count =eeeee
Actual Software Count
= ccccc
Received Data
= rrH
= ttH
Transmitted Data
where zz should be in the range of 1 through 108
bbbb should be 110, 150, 300, 600, 1200, 1800, 2400, 4800, 9600
eeeee should be 1777, 1296, 641, 320, 156, 118, 79, 40, 20
5-123
ccccc should be In the range of 00000 through 65535
rr should be In the range of 00 through FF
tt should be AA, 55, CC, 33, 01, 02, 04, 08, 10, 20, 40, 80
4. If an error for character received late occurs,
the fol lowing message Is displayed:
* Test FAILED--Test Step zz
Serial I/O Port 1 Test
Character Received Late
Teslng Baud Rate
= bbbb
Maximum Expected Count = eeeee
Actual Software Count
= ccccc
Received Data
= rrH
Transmitted Data
= ttH
where zz should be In the range of 1 through 108
bbbb should be 110, 150, 300, 600, 1200, 1800, 2400, 4800, 9600
eeeee should be 2303, 1701, 859, 417, 204, 155, 99, 53, 28
ccccc should be In the range of 00000 through 65535
rr should be in the range of 00 through FF
tt should be AA, 55, CC, 33, 01, 02, 04, 08, 10, 20, 40, 80
5. If an error for bad character occurs,
the fo Ilowl ng message is dl sp Iayed:
* Test FAILED--Test Step zz
Serial I/O Port 1 Test
Bad character Received
Testing Baud Rate
Received Data
Transmitted Data
= bbbb
= rrH
= ttH
where zz should be in the range of 1 through 108
bbbb should be 110, 150, 300, 600, 1200, 1800, 2400, 4800, 9600
rr should be In the range of 00 through FF
tt should be AA, 55, CC, 33, 01,02, 04, 08, 10, 20, 40, 80
5-124
Threshold Diagnostic Subtest 5
TITLE:
SERIAL I/O PORT #2 TEST
TARGET LOGIC:
12E, 15B, 13B, 8E, 80
TEST DESCRIPTION:
Serial I/O port #2 Is functionally tested by using USART #2 as a transmitter/
receiver to transmit an 8-blt data pattern and receive the transmitted bytes
through the wrap back RS-232 connector within a specified time window (95%
through 105%)
The RS-232 wrap back connector is configured as fol lows:
Pin 2, CTS (clear to send); short to Pin 3, RTS (request to send),
Pin 4, DSR (data set ready); short to Pin 5, DTR (data terminal ready),
Pin 6, RxD (received data); short to Pin 20, TxD (transmitted data).
The following patterns are transmitted:
OAAH, 055H, OCCH, 033H, 01H, 02H, 04H, 08H, 10H, 20H, 40H, 80H.
The following baud rates are tested:
110, 150, 300, 600, 1200, 1800, 2400, 4800, 9600
TEST STEP INFORMATION:
Test Step
1
13
25
37
49
61
73
85
97
through
through
through
through
through
through
through
through
through
Baud Rate
12
24
36
48
60
72
84
96
108
110
150
300
600
1200
1800
2400
4800
9600
Data Pattern
OAAH,55H,OCCH,33H,OlH,02H,04H,08H,10H,20H,40H,80H
OAAH,55H,OCCH,33H,OlH,02H,04H,08H,10H,20H,40H,80H
OAAH,55H,OCCH,33H,OlH,02H,04H,08H,10H,20H,40H,80H
OAAH,55H,OCCH,33H,OlH,02H,04H,08H,10H,20H,40H,80H
OAAH,55H,OCCH,33H,OlH,02H,04H,08H,10H,20H,40H,80H
OAAH,55H,OCCH,33H,OlH,02H,04H,08H,10H,20H,40H,80H
OAAH,55H,OCCH,33H,OlH,02H,04H,08H,10H,20H,40H,80H
OAAH,55H,OCCH,33H,OlH,02H,04H,08H,10H,20H,40H,80H
OAAH,55H,OCCH,33H,OlH,02H,04H,08H,10H,20H,40H,80H
5-125
ERROR MESSAGE:
1. If an error for transmitter buffer not empty occurs,
the fol lowing message is displayed:
* Test FAILED--Test Step zz
Serial I/O Port 2 Test
Transmitter Buffer Not Empty
Testing Baud Rate
= bbbb
Status Byte Read
= rrH
where zz should be in the range of 1 through 108
bbbb should be 110, 150, 300, 600, 1200, 1800, 2400, 4800, 9600
rr should be in the range of 00 through FF
2. If an error for no character received occurs, .
the fol lowing message is displayed:
* Test FAILED--Test Step zz
Serial I/O Port 2 Test
No Character Received
Tesing Baud Rate
= bbbb
Status Byte Read
= rrH
where zz should be in the range of 1 through 108
bbbb should be 110, 150, 300, 600, 1200, 1800, 2400, 4800, 9600
rr should be in the range of 00 through FF
3. If an error for character received early occurs,
the fol lowing message is displayed:
* Test FAILED--Test Step zz
Serial I/O Port 2 Test
Character Received Early
= bbbb
Tesing Baud Rate
Minimum Expected Count = eeeee
Actual Software Count = ccccc
Received Data
= rrH
= ttH
Transmitted Data
where zz should be in the range of 1 through 108
bbbb should be 110, 150, 300, 600, 1200, 1800, 2400, 4800, 9600
eeeee should be 1777, 1296, 641, 320, 156, 118, 79, 40, 20
5-126
ccccc should be in the range of 00000 through 65535
rr should be in the range of 00 through FF
tt should be AA, 55, CC, 33, 01, 02, 04, 08, 10, 20, 40, 80
4. If an error for character received late occurs,
the fol lowing message is displayed:
* Test FAILED--Test Step zz
Serial I/O Port 2 Test
Character Received Late
= bbbb
Tesing Baud Rate
Maximum Expected Count = eeeee
= ccccc
Actual Software Count
Received Data
= rrH
Transmitted Data
= ttH
where zz should be in the range of 1 through 108
bbbb should be 110, 150, 300, 600, 1200, 1800, 2400, 4800, 9600
eeeee should be 2303, 1701,859, 417, 204, 155,99, 53, 28
ccccc should be in the range of 00000 through 65535
rr should be in the range of 00 through FF
tt should be AA, 55, CC, 33, 01, 02, 04, 08, 10, 20, 40, 80
5. If an error for bad character occurs,
the fol lowing message is displayed:
* Test FAILED--Test Step zz
Serial I/O Port 2 Test
Bad character Received
= bbbb
Testing Baud Rate
Received Data
= rrH
= ttH
Transmitted Data
where zz should be in the range of 1 through 108
bbbb should be 110, 150, 300, 600, 1200, 1800, 2400, 4800, 9600
rr should be in the range of 00 through FF
tt should be AA, 55, CC, 33, 01, 02, 04, 08, 10, 20, 40, 80
5-127
Threshold Diagnostic Subtest 6
o TEST
TITLE:
TIMER 8253 COUNTER
TARGET LOGIC:
13F, 80, 8E and GATE/ logic from control board
TEST DESCRIPTION:
The timer 8253 counter 0 Is functionally tested by programming counter 0 to
to mode 1 (programmable one shot mode), and triggering GATEO from control board
GATE/ logic. The counter 0 is then verified by reading the latched count after
GATEO been triggered.
The terminal count patterns tested are:
8000H, 4000H, 2000H, 1000H, 0800H, 0400H, 0200H, 0100H,
0080H, 0040H, 0020H, 0010H, 0008H, 0004H, 0002H, 0001H.
There are two methods for testing counter 0 in mode 1:
1. After loading terminal count, trigger GATEO from low to high.
2. After loading terminal count, trigger GATEO from low to high two
times. The second trigger should cause the counter to reset to
the terminal count value.
TEST STEP INFORMATION:
Test Step
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Terminal Count Programmed
Rising Edge Trigger Pulses
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
8000H
4000H
2000H
1000H
0800H
0400H
0200H
0100H
0080H
0040H
0020H
0010H
0008H
0004H
0002H
0001H
8000H
4000H
2000H
1000H
0800H
0400H
5-128
0200H
0100H
0080H
0040H
0020H
OOlOH
0008H
0004H
0002H
OOOlH
23
24
25
26
27
28
29
30
31
32
2
2
2
2
2
2
2
2
2
2
ERROR MESSAGE:
If an error occurs, the fol lowing message is displayed:
* Test FAILED--Test Step zz
Timer 8253 Counter 0 Test
Programmable One Shot Mode
Testing Terminal count = ccccH
= eeeeH
Expected High Count
Expected Low Count
= I I I IH
Actually Read Count
= rrrrH
where zz should be in the range of 1 through 32
cccc should be 8000, 4000, 2000, 1000, 0800, 0400, 0200, 0100,
0080, 0040, 0020, 0010, 0008, 0004, 0002, 0001.
eeee should be 7EC8, 3EC8, lEC8, OEC8, 06C8, 02C8, 00C8, FFC8,
FF48, FF08, FEE8, FED8, FEDO, FECC, FECA, FEC9.
or 7FDD, 3FDD, lFOO, OFOO, 0700, 0300, 0100, 0000,
0050, 0010, FFFO, FFEO, FFE5, FFE1, FFOF, FFOE.
II I I should be 7EB8, 3EB8, lEB8, OEB8, 06B8, 02B8, 00B8, FFB8,
FF38, FEF8, FE08, FEC8, FECO, FEBC, FEBA, FEB9.
or 7FCO, 3FCO, lFCO, OFCO, 07CO, 03CO, OlCO, OOCO,
0040, 0000, FFED, FFDO, FF05, FF01, FFCF, FFCE.
rrrr should be in the range of 0000 through FFFF
5-129
Threshold Diagnostic Subtest 7
TITLE:
GPIB INTERNAL CONTROL LINES TEST
TARGET LOGIC:
15F, 17F, 16F, 160
TEST DESCRIPTION:
The GPIB internal control lines are functionally tested by writing the local
control bit true. The control bit is then verified by reading back the control
status bit.
There are ··5 contro I lines be i ng tested as fo I lows:
'catn', 'cifc', 'cren', 'srq', 'end'.
NOTE: If the 'cacs' line is not true, the lines for 'catn', 'cifc', 'cren'
and 'srq' are also not true.
TEST STEP INFORMATION:
Test Step
Control Bit
'catn'
'cifc'
'cren'
'srq'
'end'
1
2
3
4
5
ERROR MESSAGE:
If an error occurs, the following message is displayed:
* Test FAILED -- Test Step zz
GPIB Internal Control Lines
Status Port Address 01H
Bit 7 through Bit 3 is :
atn srq ifc ren eoi
"I???" and "cacs" Logic Test
"I???" Status Expected = ssssssssB
"I???" Status Read
= rrrrrrrrB
Falling Time Constant = ttttt
"????" Status Expected = eeeeeeeeB
"????" Status Read
= vvvvvvvvB
Rising Time Constant = ccccc
5-130
where:
zz should be in the range of 1 to 5
1111 should be catn, cifc, cren, srq, end.
ssssssss should be 10000000, 00100000, 00010000, 01000000, 00001000.
rrrrrrrr should be 00000000 through 11111111.
ttttt should be In the range of 00000 through 65535.
eeeeeeee should be 00000000.
vvvvvvvv should be 00000000 through 11111111.
ccccc should be In the range of 00000 through 65535.
NOTE:
Fa·1 ling and rising time constants are for diagnostic reference only.
5-131
Threshold Diagnostic Subtest 8
TITLE:
GPIB INTERNAL MPU INTERRUPT TEST
TARGET LOGIC:
15F, 17F, 16F, 150, 170, 210, 17B,
18B, 19B, 20A, 20B, 21 A, 19A, 20A, 16B, 21 F
TEST DESCRIPTION:
The GPIB internal MPU interrupt is functionally tested by writing local
control bit true and local command bits true. The interrupt status bit is
then verified by reading the interrupt status.
There are four MPU interrupt logic conditions being tested: 'tint', 'srint',
'nrlnt' and 'cint'. (The 'lint' logic condition is associated with the GPIB
external handshake function which is not tested.)
The 'INTR1/' test Is associated with the 'tint',' srlnt', 'nrint' and 'cint'
Interrupt logic conditions.
TEST STEP INFORMATION:
Test Step
MPU Interrupt Logic
'tint' and 'INTR1/'
'srint' and 'INTR1/'
'nrint' and' INTR1/'
'cint' and 'INTR1/ t
1
2
3
4
ERROR MESSAGE:
1. If an INTR1/ error occurs, the fol lowing message Is dIsplayed:
* Test FAILED -- Test Step zz
GPIB Internal Interrupt Line
gint/ lint tint cint nrlnt srlnt get/ nins/
"11111" Interrupt Line Test
GPIB INTR1/ Not Generated
where zz should be In the range of 1 through 4
11111 should be tint, srint, nrint, cint.
5-132
2. If an interrupt status error occurs, the following message is displayed:
* Test FAILED -- Test Step zz
GPIB Internal Interrupt Line
gint/ lint tint cint nrint srint get/ nins/
"11111" Interrupt Line Test
Status 1 Expected
= aaaaaaaaB
Status 1 Read
= bbbbbbbbB
Status 2 Expected
= ccccccccB
Status 2 Read
= ddddddddB
Status 3 Expected
= eeeeeeeeB
Status 3 Read
= ffffffffB
Status 4 Expected
= ggggggggB
Status 4 Read
= hhhhhhhhB
where zz should be 1 through 4
11111 should be tint, sri nt, nrint, cint
aaaaaaaa should be 10000010.
cccccccc should be 11111111, 10000010.
eeeeeeee should be 00100010, 00000110, 00001010, 00010010.
gggggggg should be 10000010.
bbbbbbbb should be in the range of 00000000 through 11111111
dddddddd should be in the range of 00000000 through 11111111
ffffffff should be in the range of 00000000 through 11111111
hhhhhhhh should be in the range of 00000000 through 11111111
5-133
Threshold Diagnostic Subtest 9
TITLE:
GPIB INTERNAL DATA REGISTER TEST
T.A.RGET LOGIC:
18E, 19E, 180, 190, 20E, 21E, 20F
TEST DESCRIPTION:
The GPIB internal data register is functionally tested by writing a data byte
pattern to the data register or paral lei pol I response register. The data
is then verified by reading the data from the input register.
There are 12 data patterns tb be tested:
OAAH, 55H, OCCH, 33H, 01H, 02H, 04H, 08H, 10H, 20H, 40H, 80H.
There are two output registers to be tested :
1. Data output register (18E)
2. paral lei poll response register (19E).
TEST STEP INFORMATION:
Test Step
Register Under Test
Data Pattern
---------------------------------------------------2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
data
data
data
data
data
data
data
data
data
data
data
data
para
para
para
para
para
para
para
para
para
para
para
para
output register
output register
output register
output register
output register
output register
output register
output register
output register
output register
output register
output register
e pol I response
e pol I response
e poll response
e poll response
e pol I response
e pol I response
e poll response
e poll response
e poll response
e pol I response
e poll response
e pol I response
OAAH
55H
OCCH
33H
01H
02H
04H
08H
10H
20H
40H
80H
OAAH
55H
OCCH
33H
01H
02H
04H
08H
10H
20H
40H
80H
5-134
ERROR MESSAGE:
1. If an error occurs in the data output register, the fol lowing message is
displayed:
* Test FAILED -- Test Step zz
GPIB Data Register Test
Data Out Register Testing
Data Register Expected = eeH
Data Register Read
= rrH
where zz should be in the range of 1 through 24
ee should be AA, 55, ee, 33, 01, 02, 04, 08, 10, 20, 40, 80
rr should be 00 through FF
2. If an error occurs in the
displayed:
parallel poll
respo~se
register, the following
* Test FAILED -- Test Step zz
GPIB Data Register Test
.
Para I Ie I Po I I Response
Data Register Expected = eeH
Data Register Read
= rrH
where zz should be in the range of 1 through 24
ee should be AA, 55,
ee,
33, 01, 02, 04, 08, 10, 20, 40, 80
rr should be 00 through FF
5-135
K205 STORAGE CONTROLLER BOARD DIAGNOSTIC
DIAGNOSTIC OVERVIEW
This section describes subtests executed on the K205 Storage Controller Board,
how error reporting is done, and the concept behind each subtest program.
It should be noted that the K205 Storage Controller-Board contains future
provisions for Installing a UART. This Diagnostic does not test any of the
UART components.
There are six subtests written for the Storage Controller Board. Each of
these subtests Is described Individually on the fol lowing pages. Parameters
for Loop on Error, Error Count, and Pass Count Update are incorporated Into
each subtest.
AI I error messages are preceded by a
">" prefix.
"*".
The Information messages use the
Early exit of each subtest is accomplished by pressing the "STOP" key.
ASSUMPTIONS
This series of tests assumes that two other boards are instal led In the K205
and are functional, an operational MPU Board as well as the Keyboard/Display
Board must be present.
SUBTEST CATEGORIES
1.
6116 Data Integrity Test
2.
6116 Address Integrity Test
3.
FDC Seek Test
4.
Fixed FDC Write/Read Test
5.
Random FDC Write/Read Test
6.
FDC/DMA Address Logic Test
5-136
ERROR COUNT CATEGORIES
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.
Subtest 1
Subtest 2
Subtest 3
Subtest 4
Subtest 5
Subtest 6
Seek Command Error Count
Recallbrate Command Error Count
Write Command Error Count
Read Command Error Count
Drive A Error Count
Drive B Error Count
Side 0 Error Count
Side 1 Error Count
Soft Error Count
Hard Error Count
Not Ready Error Count
Head Address Error Count
Ready Changed State Error Count
Missing Address Mark Error Count
Write Protected Error Count
Sector Not Found Error Count
FDC Overrun Error Count
FDC Int Tlmout Error Count
Access beyond End of Track Error Count
Missing Data Address Mark Error Count
Bad Track Error Count
Wrong Cylinder Error Count
Data Error CRC Error Count
Control Mark : Deleted Data Encountered Error Count
Unformatted Diskette Error Count
Diagnostic Program Error Count
5-137
Storage System Controller Subtest 1
TITLE:
6116 DATA INTEGRITY TEST
PURPOSE:
This subtest confirms the abi lity of the DMA hardware to sucessfully write
data into the 4K area of 6116 RAM. The integrity of the RAM is checked
by running several patterns through the Memory.
The RAM is not directly addressable; al I access is through the DMA controller.
TARGET HARDWARE:
50, 5E, 5F, 5H, 6E, 6F, 7E
TEST PESCRIPTION:
It is not possible to Write directly to the 6116 RAMs. All access is through
the DMA controller. Data is written to the DMA controller and the controller
passes it on to the RAM. Reading is accomplished through the same type of
cycle. Various Data patterns are wr.itten to the RAM then Read back. If a
miscompare occurs, an Error message is printed.
The following is a summary of the Data written to the RAM during each test
step:
TEST STEP INFORMATION:
Value Written
Test Step
------------------------------------------1
2
3
4
5
6
7
8
9
10
11
12
13
o
AAH
55H
CCH
33H
01H
02H
04H
08H
10H
20H
40H
80H
5... 138
ERROR MESSAGE:
If any errors are detected, this subtest displays the fol lowing message:
* Test FAILED--Test Step
RAM Data Error
Value Written = aaH
Va Iue Read
= bbH
Address Count = ccccH
DMA Status
= ddH
where
xx
aa
bb
cccc
dd
= test
= 00 = 00 = 6000
= 00 -
xx
step number
FF
FF
- OFFF
FF
5-139
Storage System Controller Subtest 2
TITLE:
6116 ADDRESS INTEGRITY TEST
PURPOSE:
The purpose of this test is to selectivly write 1 byte of Data into the 4K of
RAM on the storage controller board which has been preset to zero.
Verification is then made to confirm the only place the RAM is written to
is the indicated Address.
TARGET HARDWARE:
5D, 5E, 5F, 5H, 6E, 6F, 7E
TEST DESCRIPTION:
It is not possible to Write directly to the 6116 RAMs. AI I access is through
the DMA controller. Data is written to the DMA controller and the control fer
passes it on to the RAM. Reading Is accomplished through the same type of
cycle. Various Data patterns are written to the RAM then Read back. If a
miscompare occurs, an error message Is printed.
All of the RAM in this test is preset to zero then the indicated Address is
written with the value Oaah. All of RAM is then Read to verify the written
Data. If a miscompare is detected then an error message is displayed.
TEST STEP INFORMATION:
Test Step
1
2
3
4
5
6
7
8
9
10
11
12
Indicated Address
OOOOH
0001H
0002H
0004H
0008H
0010H
0020H
0040H
0080H
0100H
0200H
0400H
5-140
ERROR MESSAGES:
If any errors are detected, this subtest displays the following message:
* Test FAILED--Test Step
xx
All Storage Controller RAM Set to Zero.
Wrote aaH to Address bbbbH
Read ccH at Address ddddH
where
xx = test step number
aa = 00 - FF
bbbb = 0000 - OFFF
cc = 00 - FF
dddd = 0000 - OFFF
5-141
Storage System Controller Subtest 3
TITLE:
FDCSEEK TEST
PURPOSE:
The purpose of this subtest is to verify operation of the seek process
on one or both Disk Drives.
,
TARGET HARDWARE:
2H, 3D, 3E, 3F, 3H, 4C, 40, 4E, 4F, 70, 7F
TEST DESCR.IPTI.ON:
The FDC is commanded to perform seeks to the given Track as outlined
below. Tracks are accessed from Track 0 to 39, and 39 to o.
Finally, an alternating pattern of seeks spiraling from outermost to
innermost Tracks is performed.
As these operations are sent to the ·FDC controller, the status of the
controller is monitored. If an error is detected, an error message
is displayed.
This operation is repeated for all selected Drive and Side options selected.
TEST STEP INFORMATION:
Test Step Number
Drive/Side
Disk Action
A
/
0
A
A
A
A
A
/
/
/
/
/
0
0
1
1
1
B
/
/
0
0
/
/
/
/
0
1
1
1
seek 0-39
seek 39-0
sp I ra I Inward
seek 0-39
seek 39-0
sp i ra I inward
seek 0-39
seek 39-0
sp i ra I inward
seek 0-39
seek 39-0
spiral inward
----------------------------------------------------------1 - 40
41- 80
81- 120
121-160
161-200
201-240
241-280
281-320
321-360
361-400
401-440
441-480
B
B
B
B
B
ERROR MESSAGES:
If any errors are detected, this subtest wi I I display the error
messages found in Appendix 1.
5-142
Storage System Controller Subtest 4
TITLE:
FDCWRITE/READ TEST
PURPOSE:
The purpose of this subtest is to verify the Storage Controller Board's
capabi lity to Write and Read back information on al I Tracks of the Disk Drive.
TARGET HARDWARE:
2H, 3D, 3E, 3F, 3H, 4C, 4D, 4E, 4F, 7D, 7F
2A, 2B, 2C, 3A, 3B
TEST DESCRIPTION:
The FDC is Commanded to Write Data to al I Tracks pn a given Disk surface on a
sector by sector basis. If the Track written to is either Track 0 or Track 39
then al I sectors are written to. On other Tracks, only sector 1 is actually
tested. The Data is then Read back.and compared to the pattern written. If
a miscompare occurs, an error message Is displayed.
As these operations are sent to the FDC controller, the status of the
controller is monitored and if an error is detected an error message is
displayed. This operation is repeated for al I selected Drive and Side
options selected.
TEST STEP INFORMATION:
Test Step Number
1 - 40
41 - 80
81 - 120
121 - 160
Drive/Side
Disk Action
a/O
a/l
b/O
b/l
Write/Read/compare
Write/Read/compare
Write/Read/compare
Write/Read/compare
ERROR MESSAGES:
If any errors are detected, this subtest wi II display the fol lowing message:
xxx
* Test FAILED--Test step
Sector Compare Error
= Oaa
Track Number
Sector Number
= OOb
Address Within Sector = Occch
Wrote ddh
Read eeh
5-143
where
xxx
aa
bb
ccc
dd
ee
NOTE:
= test
step number
= 0 - 39
=0 - 8
= 000 - FFF
= 00 - FF
= 00
- FF
Also see Appendix 1.
5-144
Storage System Controller Subtest 5
TITLE:
RANDOM FDCWRITE/READ
PURPOSE:
The purpose of this subtest is to verify the Storage Controller Board's
capability to Write and Read back information on 63 random locations of the
Disk Drive.
TARGET HARDWARE:
2H, 3D, 3E, 3F, 3H, 4C, 40, 4E, 4F, 70, 7F
2A, 2B, 2C, 3A, 3B
TEST DESCRIPTION:
This subtest generates random Data and performs 63 random Read/Write cycles.
As Data is written it is then Read back and compared. If a miscompare of data
occurs, it is reported via an error message.
As these operations are sent to the FDC controller, the status of the
controller is monitored and if an error is detected an error message
is displayed.
This operation Is repeated for al I selected Drive and Side options selected.
TEST STEP INFORMATION:
Test Step Number
Drive/Side
Disk Action
165127191-
a/O
a/l
b/O
b/l
Write/Read/compare
Write/Read/compare
Write/Read/compare
Write/Read/compare
64
126
190
254
ERROR MESSAGES:
If any errors are detected, this subtest will display the fol lowing message:
*
Test FAILED--Test Step
xx
Sector Compare Error
Track Number
= Oaa
Sector Number
= OOb
Address Within Sector = cccH
Wrote ddH
Read eeH
5-145
where
xx
aa
bb
ccc
dd
ee
NOTE:
= test step
= 0 - 39
=0 - 8
= 000 - FFF
= 00 - FF
= 00 - FF
number
Also see Appendix 1.
5-146
Storage System Controller Subtest 6
TITLE:
FDC/DMA ADDRESS LOGIC
PURPOSE:
The purpose of this subtest is to verify integrity of the Address Counters
logic between the DMA controller and the floppy Disk controller.
TARGET HARDWARE:
2H, 3D, 3E, 3F, 3H, 4C, 4D, 4E, 4F, 7D, 7F
2A, 2B, 2C, 3A, 3B
TEST DESCRIPTION:
The Data pattern, Oaah, is written to the indicated Addresses on the Storage
Controller Board. The entire RAM contents are wrJtten to Track 22 on the
first available Drive. The RAM is zeroed out then a Read sector Command
is issued. The RAM is then analyzed to determine if the DMA controller has
placed Data in the original locations.
As these operations are sent to the FDC controller, the status of the
controller is monitored and if an error is detected an error message
is displayed.
This operation is repeated for al I selected Drive and Side options selected.
TEST STEP INFORMATION:
Test step
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Address Range
OOOOH
0001H
0002H
0004H
0008H
0010H
0020H
0040H
0080H
0100H
0200H
0400H
0800H
1000H
-
01FFH
0200H
0201H
0203H
0207H
020FH
021FH
023FH
027FH
02FFH
03FFH
05FFH
09FFH
11FFH
5-147
ERROR MESSAGES:
If any errors are detected this subtest wi I I display the fol lowing message:
* Test FAILED--Test Step
xx
AI I storage Controller RAM set to Zero.
Unique Testing Address Range = I I I IH to hhhhH
Data in Address Range = ddH
Checking Data at Address = aaaaH
Data Expected
= eeH
Data Read
= rrH
where
xx
I I II
hhhh
dd
aaaa
ee
rr
NOTE:
= test step number
= 0000 - OFFF
= 0000 - OFFF
= AAH
= 0000 - OFFF
= 00
= 00
- FF
- FF
Also see Appendix 1.
5-148
Storage System.Controller Diagnostic Appendix
Error Messages Common to all Disk Activity:
Subtests 3-6 all use a common routine for Disk operations which can generate
the following error message:
* Test FAILED--Test Step
Retrying Disk Command
Retry Count = b
Disk Command: c
Drive = d
Head
=e
Track = Off
Sector = g
msg
aa
where aa
test step number
b = number of times Disk Command has been attempted
c = seek Command,
Read id Command,
recalibrate Command,
Write Track Command,
Write sector Command,
Read Track Command,
Read sector Command.
d = a or b
e=Oor1
ff = 0 to 39
9 = 1 to 8
msg = Disk Drive Not Ready.
Head Address Error.
During Command, Ready Changed State.
Missing Address Mark.
Write Protected.
Sector Not Found.
FDC Over-run Error.
Data Error (CRC).
FDC Interrupt Timeout Error.
Access Beyond End of Track.
Missing Data Address Mark.
Bad Track.
Wrong Cy II nder.
Data Error (crc).
Control Mark: Deleted Data Encountered.
Not a Formatted Disk.
5-149
Chapter 6
SCHEMATICS AND DRAWINGS
GENERAL
This chapter contains Schematic Diagrams, Assembly Drawings, Parts Lists and
Wire Lists for the K205 Logic Analyzer. The drawings are arranged sequentially
by drawing number.
LIST OF DRAWINGS
The fo I low i ng draw i ngs are proy i ded in th is chapter:
DRAWING NUMBER
0112-0204-10
0114-0110-10
011 4-0111
0114-0120-10
0114-0121
0114-0160-10/20
0114-0161
0114-0170-30
0114-0171
0114-0185-80
0114-0186
0114-0468-20
0114-0475-10
0114-0476
0114-2010-40
0114-2011
0114-2024-10
0117-0021-10
0117-0040-20
0117-0099-10
011 7-0117 -1 0
0117-0123-10
0117-0133-10
0117-0294-30
0117-0294-50
0120-0004
0120-0025-01
0120-0026
0120-0031-10
0120-0042-01
0120-0043-01
0120-0044-01
0120-0057-10
0120-0080-10
0120-0081
0120-0145-01
DESCRIPTION
Keyboard Cable Assembly
Data Board Assembly
Data Board Schematic
Control ~oard Assembly
Control Board Schematic
Clock Board Assembly
Clock Board Schematic
Threshold/GPIB/RS-232 Board Assembly
Threshold/GPIB/RS-232 Board Schematic
MPU Board Assembly
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Display Board Assembly
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CRT Assembly
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I DATE
DESCRIPTION
OWN
I
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ENGINEER
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LIST OF MATERIAL
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biomation
QUALITY ASSURANCE
DASH
NO.
NUMBER
QTY
NEXT ASSEMBLY
1
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CODE
I
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2
OF
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RE~R
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UNIT
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ITEM
•
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20
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CKD
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B 10\ILt-2010
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biomation
DATA
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NUMBER
I
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106
t
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NO.
!
I 5 ~ 91'2 15 20 ~ ~P'2.
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1500· 0018
1800-010S
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PI.AN HOLD CORPORATION
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DRAWN' M.
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NUMBER
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81
82
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PLAN HOlO CORPORATION
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CKD
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LIST OF MATERIAL
DATA DISPLAY
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DASH
NO.
NUMBER
QTY
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I MODELJ(IDI/K$tJO
biomation
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B 101lY--20(0 !.~
CODE
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PLAN HOLD CQRPORATKlN
TOTAL
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COMMENTS
UNIT
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ITEM
1
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2
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109
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I
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113
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117
119
I
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120
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125
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I
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LIST OF MATERIAL
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NUMBER
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127
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130
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124
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Source Exif Data:
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