0121 0005 10 K450 Logic Analyzer Service Manual Apr86

0121-0005-10_K450_Logic_Analyzer_Service_Manual_Apr86 0121-0005-10_K450_Logic_Analyzer_Service_Manual_Apr86

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Publication Number 0121-0005-10
Rev. 50
April, 1986

S!RVICE, MANUAL

4/86

Copyrlght© 1986. No part of
this'Rublication may be
rept"gQuced without written
-piii_r~~~;i(;ri from Gould, Inc.,
Desigu-·'uHd Test Systems
DivisIon. Printed in U.S.A.

II

-_.

*-~

~_t

. _. i<>_,
,_,

K450 Logic Analyzer
iii

<11_~

WARNING

This equipment has not been tested to show compliance with new
FCC Rules (47 CFR Part 15) designed to limit interference to
radio and TV reception. Operation of this equipment in a
residential area is likely to cause unacceptable interference
to radio communication requiring the operator to take whatever
steps are necessary to correct the interference.
The following procedures may help to alleviate the
Television Interference Problems:

Radio

or

1.

Reorient the antenna of the receiver receiving the
interference.

2.

Relocate the equipment c.ausing the
respect
to the receiver (move or
position).

3.

Reconnect the equipment causing the interference into a
different outlet so the receiver and the equipment are
connected to different branch circuits.

4.

Remove the equipment from the power source.

interference with
change
relative

Note: The user may find the following booklet prepared by the
FCC
helpful:
"Row
to Identify and
Resolve
Radio-TV
Interference Problems".
This booklet is available from the
U.S. Printing Office, Washington, D.C. 20402. Stock No. 004- 000-00345-4.

iv

PREFACE

This manual contains information for servicing and maintaining the Gould K450
Logic
Analyzer.
Procedures are provided for> making adjustments
and
calibrating the control circui ts for various func,tions.
These procedures
include the use of diagnostic tests to troubleshoot and isolate a malfunction
to a circuit component.
Theory of operation is presented for the printed
circuit board functions.
Service aids in the form· of schematic diagrams,
wiring diagrams, assembly drawings, cable connec.tion diagrams and parts lists
are included for user reference.
The material in this manual reflects the G.ontrol~ Firmware level valid on March
17, 1986 and is up-to-date at the time of publication. but is subject to
change without notice.
Copies of this publication and other Gould Inc., Design and Test Systems
Division Publications may be obtained from the Gould Inc., Design and Test
Systems Division sales office or distributor serving your locality.

RELATED PUBLICATIONS

The following support documentation may be used with this manual:
o

K450 User's Manual, Publication Number 0121-0004-10, Describes the
capabilities, functions, and operation of the K450 Logic Analyzer.

o

K450 Disk Storage System User's Manual Add~ndum, Publication Number
0121-0084-10, Describes the capabi..1ities, function and operation of
the K450 DSS option.

ASSISTANCE

If you require assistance on this product, please call Gould Inc., Design and
Test Systems Division Customer Service on the toll-free, hot-line numbers
listed below.

Nationwide (800) 538-9320/9321
California (800) 662-9231

v

WARRANTY

The Gould Inc., Design and Test Systems Division K450 is warranted against
defects in materials and workmanship for a period of one year from date of
shipment. Any floppy disk or hard disk drives attached to or contained within
this equipment are warranted for 90 days from date of shipment.
Gould Inc.,
Design and Test Systems Division will repair or replace products that prove to
be defective during the warranty period.
Warranty service must be performed at a Gould Inc., Design and Test Systems
Division authorized service facility. The customer must call Gould's Customer
Service department at the toll-free numbers listed in the front of thil manual
and obtain a Return Authorization number prior to returning the unit for
service. If a unit fails within 30 days of shipment date, Gould Inc. will pay
all shipping charges relating to the repair of the unit.
Units under
warranty, but beyond the 30-day period, should be sent to Gould Inc. prepaid,
and Gould Inc. will return the unit prepaid.
The customer must pay all
shipping charges for units out of warranty.
Misuse of. abuse of. or tampering with this unit will. at the discretion of
Gould Incorporated. cause this warranty to be null and void.

vi

CONTENTS

Chapter
1

Page
GENERAL DESCRIPTION
INTRODUCTION •••••••••••••••••••••••••••••••••••••• l-l
Overview of K450 Features •••••••••••••••••••• l-l
Overview of Manual Contents •••••••••••••••••• 1-3
SERVICING PLAN •••••••••••••••••••••••••••••••••••• 1-3
Power Up Diagnostic Routines ••••••••••••••••• 1-3
DOS Diagnostic Routines •••••••••••••••••••••• 1-4
MAINTENANCE FEATURES •••• ~ ••••••••••••••••••••••••• 1-5
Probe Test ••••••••
1-5
Display Calibration Pattern.~ •••••••••••••••• 1-5
SPECIFICATIONS •••• ~~ •••••••••••••••••••••••••••••• 1-6
K450 Unit Configurations ••••••••••• ~ ••••••••• 1-6
Power Requirements ••••••••••••••••••••••••••• 1-6
Physical Dimensions and Weight ••••••••••••••• 1-6
Environmental Limits ••••••••••••••••••••••••• 1-7
Probes ••••••••••••••••••••• ~ ••••••••••••••••• 1-7
Data Inputs •••••••• ~ •••• ~ •••••••• : ••••••••••• 1-8
Clocks ••••••••••••••••••••••••••••••••••••••• 1-8
External Clock SpecificatioRs •••••••••••••••• 1-9
Data Set Up and Hold Time •••••••••••••••••••• 1-9
DVM Inputs ••••••••••••••••••••••••••••••••••• 1-9
Signal Outputs ••••••••••••••••••••••••••••••• 1-9
Memory ••••••••••••••••••••••••••••••••••••••• l-lO
Trace Control •••••••••••••••••••••••••••••••• l-lO
Interface •••••••••••••••••••••••••••••••••••• l-lO
Keystroke Tone Signal •••••••••••••••••••••••• l-lO
G ••••••••••••••••••••••••••

2

SYSTEM COMPONENTS AND INTERCONNECTIONS
INTRODUCTION •••••••••••••••••••••••••••••••J • • • • • • 2-1
BOARDS AND COMPONENTS ••••••••••••••••••••••••••••• 2-2
BOARD AND COMPONENT INTERCONNECTIONS •••••••••••••• 2-4
Boards ••••••••••••••••••••••••••••••••••••••• 2-4
Components ••••••••••••••••••••••••••••••••••• 2-4
CARD CAGE ARRANGEMENT ••••••••••••••••••••••••••••• 2-6
Data Board Configurations •••••••••••••••••••• 2-6
Board Calibration Controls ••••••••••••••••••• 2-7
SUGGESTED TEST EQUIPMENT •••••••••••••••••••••••••• 2-7

3

CALIBRATION AND POWER UP DIAGNOSTICS
GENERAL ••••••••••••••••••••••••••••••••••••••••••• 3-1
POWER UP DIAGNOSTICS •••••••••••••••••••••••••••••• 3-1
Diagnostic Operation ••••••••••••••••••••••••• 3-1
User Interaction ••••••••••••••••••••••••••••• 3-2
Microprocessor RAM Test Description •••••••••• 3-2
Microprocessor ROM Checksum Test Description.3-3
Keyboard Stuck Key Test Description •••••••••• 3-3
Voltage Test Description ••••••••••••••••••••• 3-4
Display Board CMOS RAM Test Description •••••• 3-4
vii

PROBE TEST •••••••••••••••••••••••••••••••••••••••• 3-S
Probe Test Pattern Generator ••••••••••••••••• 3-S
Trace Control Setup •••••••••••••••••••••••••• 3-S
Record/Review Test Results ••••••••••••••••••• 3-S
Probe Connections •••••••••••••••••••••••••••• 3-6
Default Setup •••••••••••••••••••••••••••••••• 3-7
Fixed ECL Threshold Setup •••••••••••••••••••• 3-8
DISPLAY CALIBRATION ••••••••••••••••••••••••••••••• 3-8
Calibration Requirements ••••••••••••••••••••• 3-8
Display Adjustment Points •••••••••••••••••••• 3-8
POWER SUPPLY VOLTAGE HEASUREHENTS ••••••••••••••••• 3-12
REFERENCE/THRESHOLD VOLTAGE AND DVM CALIBRATION ••• 3-13
lOV Reference Voltage Adjustment ••••••••••••• 3-13
TTL Threshold Adjustment ••••••••••••••••••••• 3-14
ECL Threshold Adjustment ••••••••••••••••••••• 3-16
Variable A Threshold Adjustment •••••••••••••• 3-17
Variable B Threshold Adjustment •••••••••••••• 3-18
DVM Adjustment ••••••••••••••••••••••••••••••• 3-19
INTERNAL CLOCK ADJUSTMENT ••••••••••••••••••••••••• 3-20
4

THEORY OF OPERATION
GENERAL •••••••••••••••••••••••••••••••••••••••••••• 4-1

OVERVIEW OF K4S0 UNIT OPERATION •••••••••••••••••••• 4-1
MPU Board Interaction •••••••••••••••••••••••• 4-1
Data Board Interaction ••••••••••••••••••••••• 4-3
Clock Board Interaction •••••••••••••••••••••• 4-3
Control Board Interaction •••••••••••••••••••• 4-3
Threshold/GPIB/RS-232 Board Interaction •••••• 4-3
Data Display Board Interaction ••••••••••••••• 4-4
DATA DISPLAY BOARD OPERATIONS ••••••••••••••••••••• 4-4
Overview ••••••••••••••••••••••••••••••••••••• 4-4
CRT Controller ••••••••••••••••••••••••••••••• 4-6
Interrupt Processor •••••••••••••••••••••••••• 4-7
Keyboard and Front Panel Interface Circuit ••• 4-8
CMOS RAM Save Circuit •••••••••••••••••••••••• 4-8
Real Time Clock •••••••••••••••••••••••••••••• 4-8
Audio Error Alarm Circuit •••••••••••••••••••• 4-8
DOS Interface Circuit •••••••••••••••••••••••• 4-9
MPU BOARD OPERATIONS ••••••••••••••••••••••••••••••• 4-9
Overview ••••••••••••••••••••••••••••••••••••• 4-9
Microprocessor ••••••••••••••••••••••••••••••• 4-9
Address Registers and Data Transceivers •••••• 4-12
Memory ••••••••••••••••••••••••••••••••••••••• 4-12
Memory Controller •••••••••••••••••••••••••••• 4-12
I/O Decoding ••••••••••••••••••••••••••••••••• 4-13
THRESHOLD/GPIB/RS-232 BOARD OPERATIONS ••••••••••••• 4-13
Overview ••••••• o • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 4-13
Threshold Circuit •••••••••••••••••••••••••••• 4-13
DVM Circuit •••••••••••••••••••••••••••••••••• 4-16
GPIB Interface Circuit ••••••••••••••••••••••• 4-16
RS-232 Interface Circuit ••••••••••••••••••••• 4-16
MPU Interface •••••••••••••••••••••••••••••••• 4-16
CLOCK BOARD OPERATIONS •••••••••••••••••• e • • • • • • • • • 4-17
Overview~ •••••• ~o • • • • • • • • • • • • • • • • • • • • • • • • • • • • 4-17
Internal Clocks •• o • • • • • • • • • • • • • • • • • • • • • • • • • • • 4-17
External Clocks •••••••••••••••••••••••••••••• 4-20
viii

AND t1aster Clocks •••••••••••••••••••••••••••• 4-20
OR Clock Selection ••••••••••••••••••••••••••• 4-21
Level Memory Circuit ••••••••••••••••••••••••• 4-21
MPU Interface •••••••••••••••••••••••••••••••• 4-21
DATA BOARD OPERATIONS •••••••••••••••••••••••••••••• 4-22
Overview •••••••••••••• e • • • • • • • • • • • • • • • • • • • • • • 4-22
Data Input Control ••••••••••••••••••••••••••• 4-22
Operating Modes •••••••••••••••••••••••••••••• 4-25
Sampling Circuit Operation ••••••••••••••••••• 4-25
5 ns Sampling (200 MHz Operation) •••••••••••• 4-26
Data Pipeline Control •••••••••••••••••••••••• 4-26
Memory Control ••••••••••••••••••••••••••••••• 4-26
MPU Interface •••••••••••••••••••••••••••••••• 4-27
CONTROL BOARD OPERATIONS •••••••••••••••••••••••••• 4-27
Overview ••••••••••••••••••••••••••••••••••••• 4-27
Word Recognition Circuits •••••••••••••••••••• 4-27
Word Selection Circuits •••••••••••••••••••••• 4-29
Level Switching Circuits ••••••••••••••••••••• 4-30
Delay Counter •••••••••••••••••••••••••••••••• 4-30
Recording Control Circuits ••••••••••••••••••• 4-30
MPU Interface •••••••••••••••••••••••••••••••• 4-32
5

DISK DIAGNOSTICS
INTRODUCTION •••••••••••••••••••••••••••••••••••••• 5-1
STARTING UP THE K450 DIAGNOSTICS •••••••••••••••••• 5-3
DIAG MENUS AND DISPLAYS ••••••••••••••••••••••••••• 5-4
Main Menus ••••••••••••••••••••••••• eo • • • • • • • • 5-4
System Testing (All Active Boards) ••••••••••• 5-4
Single Board Testing ••••••••••••• c • • • • • • • • • • • 5-5
Conducting all Subtests or Individual Tests •• 5-5
DIAGNOSTIC PARAMETERS (EDIT KEY) •••••••••••••••••• 5-5
General •••••••••••••••••••••••••••••••••••••• 5-5
Halt on Error •••••••••••••••••••••••••••••••• 5-6
Loop on Error •••••••••••••••••••••••••••••••• 5-6
Display Error Messages ••••••••••••••••••••••• 5-7
Number of Times to Repeat Test(s) •••• .-. •••••• 5-7
Test Drive A, Test Drive B••••••••••••••••••• 5-8
Test Side 0, Test Side 1 ••••••••••••••••••••• 5-8
Run Operator Action Tests •••••••••••••••••••• 5-8
PASS/ERROR TABULATION (DATA KEY) •••••••••••••••••• 5-8
DIAGNOSTIC RE-INITIALIZATION AND EXIT TO SYSTEM ••• 5-10
General •••••••••••••••••••••••••••••••••••••• 5-10
Exiting the Diagnostic ••••••••• c • • • • • • • • • • • • • 5-10
SUMMARY OF DIAGNOSTIC OPERATING SYSTEM KEYS ••••••• 5-10
KEYBOARD/DISPLAY BOAF~ DIAGNOSTIC TEST •••••••••••• 5-12
DATA BOARD DIAGNOSTIC TEST.~ •••••••••••••••••••••• 5-23
CONTROL BOARD DIAGNOSTIC TEST ••••••••••••••••••••• 5-51
CLOCK BOARD DIAGNOSTIC TEST ••••••••• ~ ••••••••••••• 5-74
THRESHOLD/GPIB/RS-232 BOARD DIAGNOSTIC TEST ••••••• 5-117
STORAGE CONTROLLER BOARD DIAGNOSTIC TEST •••••••••• 5-138

6

OPTIONS INSTALLATION
GENERA.L •••

0

••••••••••••••••••••••••••••••••••••••••

6-1

Card Cage Arrangement •••••••••••••••••••••••• 6-1
Data Board Input Configuration ••••••••••••••• 6-1
INSTALLATION OF K450 INPUT EXPANSION OPTION •••••••• 6-2
ix

Unpacking And Inspection ••••••••••••••••••••• 6-2
Installation Procedure ••••••••••••••••••••••• 6-2
Removal of DSS Option Assembly ••••••••••••••• 6-5
INSTALLATION OF DSS OPTION ••••••••••••••••••••••••• 6-6
Unpacking And Inspection ••••••••••••••••••••• 6-6
Installation Procedure ••••••••••••••••••••••• 6-7
7

SCHEMATICS AND DRAWINGS
GENERAL ••••••••••••••••••••••••••••••••••••••••••• • 7-1

LIST OF DRAWINGS ••••••••••••••••••••••••••••••••••• 7-1
Figure

Page

1-1
2-1
2-2
2-3
2-4
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
4-1
4-2
4-3
4-4
4-5
4-6
4-7
5-1
6-1
6-2
6-3
6-4
6-5

K450 Logic Analyzer, General Arrangement •••••••••••••••• l-l
K450 Front Panel Arrangement •••••••••••••••••••••••••••• 2-1
K450 Rear Panel Arrangement ••••••••••••••••••••••••••••• 2-2
K450 System Interface of Components to Mother Board ••••• 2-5
K450 Card Cage Arrangement •••••••••••••••••••••••••••••• 2-6
Typical Probe Test Recording Using An Internal Clock •••• 3-6
Typical Probe Test Recording Using An External Clock •••• 3-7
CRT Centering Rings ••••••••••••••••••••••••••••••••••••• 3-9
Data Display Board Adjustment Points •••••••••••••••••••• 3-10
CRT Grid Pattern •••••••••••••••••••••••••••••••••••••••• 3-11
Power Supply Voltage Measurements ••••••••••••••••••••••• 3-12
Threshold/GPIB/RS-232 Board Adjustments ••••••••••••••••• 3-14
Test Connections for Threshold Voltage Adjustment ••••••• 3-15
Clock Board, Internal Clock Adjustment •••••••••••••••••• 3-21
K450 System Data Flow and Control Block Diagram ••••••••• 4-2
Data Display Board, Block Diagram •••••••••••••••••••••• 4-5
MPU Board, Block Diagram •••••••••••••••••••••••••••••••• 4-11
Threshold/GPIB/RS-232 Board, Block Diagram •••••••••••••• 4-15
Clock Board Block Diagram ••••••••••••••••••••••••••••••• 4-19
Data Board, Block Diagram ••••••••••••••••••••••••••••••• 4-24
Control Board, Block Diagram •••••••••••••••••••••••••••• 4-28
Organization of K450 Diagnostic Software •••••••••••••••• 5-2
K450 Card Cage Arrangement, Top View •••••••••••• -. •••••• 6-4
K450 Ribbon Cable Connections At Card Cage •••••••••••••• 6-5
DSS Power Supply Harness Connection, Top View ••••••••••• 6-7
K450 DSS Assembly, Top View With Cover Removed •••••••••• 6-8
Disk Drive I/O Ribbon Cable Connection •••••••••••••••••• 6-9

x

Chapter 1

GENERAL DESCRIPTION
INTRODUCTION
Overview of K450 Features
The Gould/Biomation K4S0 Logic Analyzer (Figure 1-1) is a test and development
instrument, that monitors and records signals from the user's target system.

KEYBOARD
PANEL

DISK STORAGE SYSTEM~

- ...--......•

..

.

-t~,~"'~'
INPUTS

Figure 1-1.

VOLTMETER
INPUTS

POWER INDICATOR

K450-D Logic Analyzer, General Arrangement

The K450 may be configured to accept the following data inputs:
o

16, 32, or 48 Inputs @ 100 MHz Sections A, Band C.

o

8, 16, or 24 Inputs @ 200 mlz Sections A, Band C.

The K450 also accepts the following external clock inputs:
o

2 Sample and 2 Latch clocks, Section A only.

o

6 Sample and 2 Latch clocks, Section A and B.

o

6 Sample and 6 Latch clocks, Sections A, Band C.

The K4S0 control logic measures input signals to correlate data and timing
characteristics.
The K4S0 captures and compares data samples.
The results
are then recorded in memory.
The features are menu-driven by resident
firmware which is controlled by the Keyboard Panel.
The menus allow the user
to set up test conditions, capture the results of binary logic states through
trace control for data-domain analysis.
The pulse train waveforms are
displayed for time domain analysis.
The display screen presents the results
of analysis for examination and/or modification by the user.
Major features of the K4S0 operation are:
o

The K4S0 equipment functions are menu-driven under the control of a
16-bit, 8086 microprocessor.

o

The operating
bytes of ROH.

o

Three input sections, A, Band C, accept user inputs through probe
circuits.
Each section is subdivided into two input groups.
Each
input group accepts 8 data and 2 clock signals to provide 48 data
inputs and 12 external clocks.

o

Data inputs are capable of being sampled internally at frequency
rates up to 200 MHz. Data may be displayed in 40-column Binary,
Hexadecimal, Octal, ASCII, EBCDIC, or user defined formats.

o

Sample, Glitch, and Latch/Demultiplex
groups of 8 or 16 channels.

o

Independent threshold-level selection
probe and group of clocks.

o

Up to 16 different state levels for trace control are
using the display menus and front panel keys.

o

The K4S0 tracks a SOMHz state machine, while comparing the machine
state to four search patterns per level, every 20 ns.

o

The

o

A 24-hour Real-Time clock with battery backup feature allows the
K4S0 to log the current time of day and date of each recording.

o

The battery backup feature also drives the CMOS memory which
preserves the current set up for recording parameters if power is
interrupted.

o

A built-in Digital Voltmeter (DVM) with input jacks on
panel provides a 4-digit readout for user convenience.

o

A self-contained frequency counter provides automatic measurement of
external clock frequency and status.

o

The K4S0 may be operated as a stand-alone unit or linked
user's system through a RS-232-C or IEEE-488 interface.

trace

is

system accommodates up to S12K bytes of RM1 and

256K

input modes are selected in
is provided for

each

logic

selected

by

recorded in a 48-bit wide x 20S1-word length memory.

1-2

the

front

with the

o

An optional Disk Storage System (DSS) stores set up information and
data on a floppy disk for later analysis. The DSS option also loads
and executes disk-based diagnostic routines.

Overview of Manual Contents
The manual is arranged as follows:
Chapter 1. GENERAL INFO~~TION - Presents an overview of the K450 operating
features, organization of manual contents, service plan, maintenance features,
and equipment specifications.
Chapter
2.
SYSTEM
COMPONENTS
AND INTERCONNECTIONS
- Describes
interconnection of printed circuit boards, power distribution, external
interface, and special tools and test equipment.

the
I/O

Chapter 3. CALIBRATION AND POWER UP DIAGNOSTICS - Describes the power up
Boot PROM check, Probe Test, calibration of the Data Display Board, Clock
Board, and Threshold/GPIB/RS-232 Board, and measurement of the power supply
voltages.
Chapter 4. THEORY OF OPERATION - Presents theory of operation for each printed
circuit board and associated circuitry.
Chapter 5. DSS DIAGNOSTICS
associated subtests.

- Describes

each

diagnostic

Chapter 6. OPTIONS INSTALLATION
Provides procedures for
Expansion Option for the Band C section inputs and the Disk
(DSS) Option equipment.

module

and

its

installing the
Storage System

Chapter 7. SCHEMATIC DIAGRAMS AND PARTS LISTS - Provides reference
such as schematic diagrams, assembly drawings, and parts lists.

material

SERVICE PLAN
The service plan for the K450 involves the use of diagnostic routines to
isolate a defective circuit function.
The K450 has diagnostic routines that
perform a check of major circuit functions whenever the unit is reset or
powered up from a cold start. Malfunctions detected by the diagnostics may be
tested further by using the DSS routines to isolate the cause of failure.
The resident firmware also generates special displays which permit the ~ser to
conduct input Probe Tests and perform CRT alignmento The diagnostic should be
rerun after a repair is completed to verify the problem is resolved before the
unit is placed into operation.
Power Up Diagnostic Routine.
The Power Up Diagnostic routines indicate system operational status. Messages
are displayed on the screen to identify the type of error condition and the
failed function.
Since several components may be associated with the
malfunction,
boardswapping and rerunning the diagnostic may fix the problem.
To avoid possible damage to equipment, do not remove or install a printed
circuit board while ac or dc power is applied to the unit.

The following circuits are tested by the Power Up Diagnostic routines:
o

MPU Board RAM Test

o

HPU Board ROM Test

o

Keyboard Matrix Test For Stuck Keys

o

System Voltage Tolerance Test

o

Display Board CMOS

o

Threshold/GPIB/RS-232 Board Check

o

DSS Recognition Check

o

Data Board Recognition Check

o

Clock Board Recognition Check

o

Control Board Recognition Check

~~

Test

DSS Diagnostic Routines
The K450 Disk Storage System (DSS) option loads diagnostic routines from the
disk to further isolate the cause of failure to a specific circuit or
component.
The DSS diagnostic provides flexibility for the user to set up
test parameters that halt on error, loop on error and perform repetitive tests
for a specified pass count. The DSS diagnostic is described in Chapter 5.
A separate diagnostic routine is provided for each component.
The diagnostic
does not assume any part of the system is functional until it has passed its
associated subtests.
If a failure is detected, the diagnostic generates an
error message identifying the cause of failure. A Self Test menu is displayed
when the DSS diagnostic is invoked.
The following software is contained on the diagnostic disk:
0

Diagnostic Storage System (K450)

0

Keyboard/Display Diagnostic Module (KDDIAG)

0

Threshold/GPIB/RS-232 Diagnostic Module (THDIAG)

0

Control Board Diagnostic Module (CBDIAG)

0

Clock Board Diagnostic Hodule (CKDIAG)

0

Data Board Diagnostic Module (DBDIAG)

0

Storage System Controller Diagnostic Hodule (SCDIAG)

When the user selects a test for execution, the diagnostic test monitor
generates detailed sub-menus that direct the user in running the test
procedure.

1-4

MAINTENANCE FEATURES

The K450 contains additional built-in features that aid in maintaining the
equipment. These features allow the user to test the sample and clock in-puts
at each probe and to align the CRT display characteristics.

Probe Test
Two Probe Test connectors allow the user to verify that two clock inputs and
eight data inputs supplied from each probe, operate within acceptable limits.
A test pattern generated by the K450 firmware is supplied to the probe under
test. Procedures for conducting the Probe Test are described in Chapter 3.

Display Calibration Pattern
Procedures for calibrating the CRT are described in Chapter 3.
The Display
Calibration Pattern, is used by holding the SHIFT key while powering up the
unit. This pattern allows the user to make adjustments on the Display printed
circuit board for calibrating the following display items:
0

Vertical Height

0

Vertical Hold

0

Horizontal Width

0

Horizontal Linearity

0

Vertical Linearity

0

Focus

0

Brightness

SPECIFICATIONS
The following is a summary of the
characteristics of the K450.

physical,

environmental,

and

operating

K450 Unit Configurations
016

Unit:

Provides inputs for 16 data signals @ 100
signals @ 200 MHz) and 4 clocks via input

032

Unit:

Provides inputs for 32 data signals @ 100 }ffiz (16
data signals @ 200 MHz) and 8 clocks via input
Sections A and B.

048

Unit:

Provides inputs for 48 data signals @ 100 MHz (24
data signals at 200 MHz) and 12 clocks via Input
Sections A, B, and C.

Expansion

DSS

Option:

Option:

(8 data
Section A.

}ffiz

Each data board provides probe inputs for 16 add-on
data signals at 100 MHz (8 data signals @ 200 MHz)
and 4 additional clocks through input Section B or C.
Disk Storage System provides two 5 1/4" floppy disk
drives mounted in an add-on assembly unit which
provides 312K bytes of storage per disk.

Power Requirement.
Input Frequency:

50 or 60 Hz

Input Voltage:

90 to 135 Vac or 180 to 270 Vac

Input

500 Watts
option

Power:

Fuses For Rated
Voltage:

without DSS option or 550 Watts with

Voltage Range

Fuse

90 Vac to 135 Vac

3AG, 8 Amp

180 Vac to 270 Vac

3AG, 4 Amp

DSS

Physical Dimensions and Weight
Height:

8.6 inches (21.8 CM) without DSS, 12 inches (30.1 em)
with DSS

Width:

17.5 inches (44.5 CM)

Depth:

24.7 inches (62.7 CM) including handle

Weight:

45 lbs. (20 kg) without probes or DSS
55 lbs. (25 kg) without probes

1-6

Environmental Limits
Ambient Temp:

39 to 115 Deg.F (4 to 46 Deg.C)

OPERATING

-8 to 117 Deg.F (-20 to 50 Deg.C) STORAGE
Relative Humidity:

20% to 80% OPERATING
1% to 95% STORAGE

Max Wet Bulb:

78 Deg.F (25 Deg.C) OPERATING
No condensation

STORAGE

Probes
Loading Characteristics:
Signal Inputs
Input Resistance:

1 megohm referenced to threshold

Input Capacitance:

<=

6pF

«=

NOTE:

Input resistance may
+15 volts from threshold.

15 pF with flying leads)
approach 500K ohms at voltages exceeding

Maximum Input
Without Damage:

+50 volts, peak

Common Mode Range:

+0.5 volt max between probe and unit probed

Ground Input:

Input resistance is 91K ohms referenced to chassis

Probe Transfer
Characteristics:

Bandwidth to 90% volts out: = )100 MHz

Minimum Swing For
Output:

Threshold +0.20 V maximum

Threshold Variance: +15 mV maximum, between input signals;
+30 mV maximum, any two probes
Input Compensation: Even to 20% overcompensated
Thresholds:

Thresholds
probe:

are

independently selectable

TTL, +1.4 volts
ECL, -1.3 volts
VAR A and VAR B

1-7

for

each

NOTE: Variable thresholds may be set from -9.99 to +9.99 volts in 0.01
volt increments. Accuracy of all threshold voltages i8 3OmV.
Polarity:

+ or - is selectable for each signal

Data Inputs
16, 32, or 48 (@100 MHz); or 8, 16, 24 (@ 200 tffiz) data inputs configured in
one two or three input sections, A, Band C. Each section contains two input
groups that accept 16 signals.
One group for lower Bits 7-0 at 100 or 200
tlliz, the other group for upper Bits F-8 at 100 MHz.
Input Modes:

Sample Uode
Latch and Demultiplex Mode
Glitch Mode

Input Frequency:

dc to 100 UHz (data)
dc to

50 HHz (clocks)

Clocks
The 16-input configuration provides 2 Sample (edge-sensitive) clocks and
Latch Enable (level sensitive) clocks for a total of 4 external clocks.

2

The 32-input configuration provides 6 Sample (edge-sensitive) clocks and
Latch Enable (level-sensitive) clocks for a total of 8 external clocks.

2

The 48-input configuration provides 6 Sample (edge-sensitive) clocks and
Latch Enable (level-sensitive) clocks for a total of 12 external clocks.

6

Internal:

Internal clock is selectable from 20 ns (50 tn~) to
100 ms (10 Hz) in decades of time which is divided by
units of 1 to 10 (100 ns, 1 us, 10 us and 1 us, 2 us,
3 us, ••• 10 us). One internal clock may be programmed
per recording.
This clock is edge sensitive.
A 10
ns (100 tffiz) or 5 ns (200 MHz) clock is available to
the sample/store sections in addition to the external
clock. This clock is edge sensitive.

External:

Six external clock inputs which may be combined to
form three Sample clocks, three Latch Enable clocks,
and one Master (M) clock.

Sample

One sample clock may be specified for each input
section (A B, or C) to hold data for the master
clock, or move trace data into memory (effective for
internal, external, 200 tffiz, and 100 tffiz clocks).
This clock is edge sensitive.

Latch

Clock:

Clock:

A special

case of Sample Mode which is used to
temporarily
hold (by latch) the first byte of
multiplexed data.
When the latch clock goes false,
data are held in the input latched until the latch
clock returns true.
1-8

The master clock then moves the sample into the
pipeline (effective for external clocks only).
This
clock is edge sensitive.
M-Clock:

The master clock is used to shift samples into memory
and the trace control logic (effective for internal
or external clocks).
This clock is edge sensitive.

External Clock Specification
Frequency:

dc to 50 MHz

Pulse Width:

8 ns Minimum

Clock Skew:

7 ns Maximum between any two clock combinations

Latch Clocks Setup: 13 ns Minimum before Sample Clocks
Clock

Frequency:

The K450 automatically measures the external clock
frequency from 100 Hz to 50 MHz with 0.1% accuracy.

Data Setup and Hold Time
Data must be present 12 ns (maximum) before,
active edge. Typical setup time is 8 ns.

and stable

until,

the

clock

Data may change zero ns after the clock active edge "0 Hold Time."
Minimum detectable pulse width is one clock period +5 ns.

DVM Input
Range:

+20 Vdc Maximum

Resolution:

20 mv

Input Impedance:

20k ohms

Accuracy:

+0.5%

Signal Outputs
VIDEO, BNC
Connector:
CLOCK, BNC
Connector:
GET, BNC
Connector:
TRACE BNC
Connector:

1 Vp-p into 75 ohms
compatible with RS-170

composite

video

output

is

ECL active low corresponds to the internal clock
Group execute trigger pulse output for the IEEE-488
Command - TTL
TTL high output when trace is enabled

1-9

Two LEMO
Connectors:

+5V and -5.2V @ 300 rnA

Memory
The K450 contains main memory M, storage memory A, and reference memory B.
Four bits of each word
Memory M is organized as 2,048 by 20, 36 or 52 bits.
are used to store the level at which data were recorded.
The CPU reads data
from M into A or from A into B. Both A and B are a part of the CPU memory.
The operating system accommodates up to 512K bytes of RAM and 256K
ROM under the control of the 16-bit, 8086 CPU.

bytes

of

Trace Control
Trace control employs 16 trace levels defined by user inputs through the
display screen and keyboard.
Four commands are decoded for each of the
sixteen levels.
The four commands are TRACE, STOP, JUMP, and ADVANCE.
Control begins at level zero.

A delay counter may be programmed from 1 to 65,535 clocks or events to begin
tracing after a specified condition occurs. The rear panel BNC output for
TRACE is at a TTL level that goes high while the K450 is tracing.
Interface
One RS-232-C Serial I/O Port configured as Data Terminal Equipment (DTE)
wire system.

six

One Auxiliary Serial I/O Port for RS-232-C (reserved for K450 options).
One IEEE-488 Bus Interface, Parallel Port with Talker/Listener
selectable by the user through software control.

configuration

Timer:

A 24-hour, time and date clock is backed up by a 2.9
V battery

Backup Memory:

A 2k

x 16 CMOS memory with battery backup saves the
last setup of recording parameters if power is
interrupted or when the unit is turned off.

Keystroke Tone Signal

A beeper indicates keystroke errors and is enabled by the user through a
display.

1-10

menu

Chapter 2

SYSTEM COMPONENTS AND INTERCONNECTIONS
INTRODUCTION
This chapter describes individual printed circuit boards and components that
comprise the K450 Logic Analyzer.
Information is also included for the
interconnection of these boards and recommended equipment. Front and rear
views of the K450 chassis are shown in Figures 2-1 and 2-2.

CO"TR~

..,,,,.

fOrT

110

G O D D:D
&
.IT

CAHCIL

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0

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8

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8088
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8888
y

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0
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P')WER

GOULD

K450 Logic Analyzer

ON

B

0-7 1t,J

AC 'OWEII

'"011! TUT

OI .~~~
Figure 2-2.

~I

@
@

@

(illflJ @

®

AC
INPUT

f'.';;;'.~r.t! ®
. • ~,

=~

@
@~
----------------------------~

K450 Rear Panel Arrangement

BOARDS AND COMPONENTS

The following boards and components are used for K450 hardware configurations:
o

Keyboard:
The keyboard has 48 keys, several can be shifted to perform a second
function. Because of the shift capability, 20 keys can perform as a
full alpha-numeric keyboard.

o

Front Connector Panel:
The front connector panel has the following components:
- Six DB-25 female connectors for external data/clock input
- Two jacks for DVM (POS and NEG) input
- Two card-edge female connectors for PROBE TEST output
- Power LED indicator
- ac power switch

2-2

- The data/clock input connectors available for 16, 32 or 48 input
configuration are established by the number of Data Boards
installed. The unit may be configured with one, two or three Data
Boards.
These Data Boards have 16, 32 or 48 inputs.
The
Configuration Display screen indicates the number of active
connectors present for a given instrument.
- Illumination of the Power LED indicator
presence of +5 Vdc when ac power is applied.
o

also

indicates

the

Display Assembly:
The display assembly has a 8-inch, P39 CRT and a CRT deflection
yoke with cable harness.
The mounting bracket for the assembly is
an integral part of the CRT glass envelope.

o

Rear Connector Panel:
The rear connector panel provides external interface for signal I/O
and power through the following circuit components:
- Signal output is provided for VIDEO, CLOCK, TRACE, and GET through
four BNC connectors.
- The + 5V
connectors

and

- 5V

output is provided

by

each

of

two

LEMO

- Signal I/O is provided by one IEEE-488 connector and two RS-232
connectors. One RS-232 connector is labeled AUX and is intended
for future options.
- Power Interface is provided by the 120/240Vac line voltage input
socket and the line voltage select switch (for 120/240 Vac).
The
power fuse is rated at 8 Amp, 3AG for 120 Vac or 4 Amp, 3AG for
240 Vac power input.
o

Power Supply:
The power supply provides the following outputs:
+ 5Vdc at 11 Amps
- 5.2Vdc at 36 Amps
+15Vdc at 3.0 Amps
-15Vdc at 0.2 Amp
-2Vdc at 17 Amps

o

Data Board:
The Data Board Assembly interfaces the ECL devices of the probes to
the TTL devices of the board.
The Data Board processes 16 inputs.
Either one, two or three Data Boards will be installed in a given
system configuration as determined by the 16, 32 or 48 input
capability.

- The Data Board main memory (M) is 2,048 bits deep by 48 bits
and gathers data at 200 MHz in store mode input.
o

wide

HPU Board:
The MPU Board Assembly contains the 8086 microprocessor and operates
as the controller for K450 operations.
The firmware resides in ROM
located on the MPU Board.

o

Control Board:
The Control Board Assembly provides the user with a menu driven
display that allows 16 trace levels to be programmed by the user. A
selection of qualifiers enables the user to pick and choose the
information that will be recorded.
The Control Board also provides
an output signal to the rear panel TRACE BNC connector.

o

Threshold/GPIB/RS-232 Board:
The Threshold/GPIB/RS-232 Board Assembly provides fixed and variable
threshold voltages for the probe pods.
This board provides two RS232 ports and one IEEE-488 Talker/Listener port.
This board also
has
control circuits for DVM input and provides an
output
signal to the rear panel GET BNC connector.

o

Data Display Board:
The Data Display Board Assembly contains the keyboard scanning
circuitry and the horizontal and vertical and high-voltage circuitry
for the CRT.
In addition this board contains the interface for two
5 1/4 -inch floppy disk drives and the Keyboard Assembly.
This
board provides a video composite signal (8 tffiz dot clock frequency)
to the rear panel VIDEO BNC connector.

o

Clock Board:
The Clock Board Assembly processes the external
probes and provides a range of internal clocks for
board also provides an output signal to the rear
connector and test pattern signal to the two front
sockets.

clocks from the
the system. This
panel CLOCK BNC
panel PROBE TEST

BOARD AND COMPONENT INTERCONNECTIONS
Boards
The K450 printed circuit boards are contained in an eight-slot card cage, and
are interconnected through a mother board.
Interconnection of the printed
circuit boards to the front and rear connector panels is provided by flat
cables that mate to connectors located along the upper edges of the board.
See Figure 2-3 for the system interface.
Components
Because the K450 is a compact unit, the cable harnesses to the mother board,
and to the Data Display Board are short. The mother board is connected to the
keyboard by a short, flat cable.
2-4

:~----------------------------------------------,
DATA BOARD (SECTION C INPUTS)
I
:
iDATA-BOARD(SECT~NBIN~TSi-------------------------i
II

32(48) DATA INPUTS I
I
UJ. F~

SECTION A
16 DATAl. CLOC
PROBE INPUT

PROBE
A

S:K~

AF -

A8. R. S

A7 -

AO. J.K

SECTION B
16 DATAl. CLOC
S:K
PROBE INPUT
BF B7 -

88. R.S
80. J.K

SECTION C
16 DATAl. CLOC
PROBE INPUTS:
CF - ca. R.S
C7 - CO. J.K

I
I

K~I

PROBE
C

r--------------------------------------------4-,

I DATA BOARD (SECTION A INPUTS)
I
I

.•

I

I

._-'-1
t

n

~

r-I
I
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CONTAOlj:;
SIGNAl

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--,

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THRESHOLD
GENERATEISELECT

:

-

I

I
I
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i

I
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IL _________

REAR PANEL
'JIRACE BNC
OUTPUT

,

~

i DATA DISPLAY
I

'll

:

t

:

'II

I

•

•

:

I
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.---~~
o;JT=~~
F"10NT
PANEL
DVM
INPUT

I

R5-232

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,
I
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BUS
MGMT

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DVM

TlMERlCTR
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.....

I

DISPLAY
CRT CTRUDRIVER

I

r;

REAR PANEL
VIDEO BNC
OUTPUT

I
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CD

0..

I

I
I

I
I

r-------------------------- - - ------,

I
I

I
I

I

I
I

I CLOCK BOARD,

PROBES A. BAND C

J&K

I

MUlT

II

PROBE

I

CLOCK SELECT
SAMPlEiMASTERI
ENABLE

CMOS
RAM

A

I

I

I

REAL TIME
CLOCK

I
I

I
I
I
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KEYBOARD
INTERFACE

,

~

CLOCK
INPUTS

r;
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MOTHER BOARD ADDRESS/DATA BUS

8(12)

I

I
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I
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t---------J
-------.,

I

IEEE 488

AUX RS-232

INTR

BOARD

1

L

rtEAR
PANEL
J PORTS

~

8086
CPU

.I

"--

,

MEMORY
A
(STORAGE)

A

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1::1

:

I

f

DELAY
COUNTERI
CONTROL

TRACE
CONTROL

I

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B
(REFERENCE)

I
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IMAINI
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INPUT
CONDITIONING

L_:

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riH"R ESHOLDIGPl8IRS-232

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PROBE
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c:::::::j

II
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DOS
INTERFACE

!,

I

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:

I I

I
I

: I

:

L-------- t I ______ --~

__ V_ . . .

/

REAR PANEL FRONT PANEL
CLOCK BNC PROBE TEST
OUTPUT
OUTPUT

f1'

r

I"
\

FLOPPY
DISK

""- _ _ -""'"

"

I

/

OPTIONAL)

Pigure 2-3. K4S0 Sy.tea Interface of Coaponent. to Mother Board

"-

\
/1

KEYBOARD
INPUT

I

CARD CAGE ARRANGEMENT

The K450 card cage arrangement is shown in Figure 2-4. The board ejector tabs
on each printed circuit board are numbered to correspond to the assigned slot
location in the card cage.
The assigned board is dedicated to reside in its
slott except where noted below for the three Data Boards.

Data Board Configurations
Three Data Boards reside in slot locations A2t A3 t and A4. The ejector tabs
are not numbered on these boards t because each board is identical and is
interchangeable for these slots.
Each slot location has a specific SECTION
INPUT, as shown in Figure 2-4.

. , . - - - - - - - - CLOCK BOARD
~----THRESHOLD/GPIB/RS·232

~--

L - - ._ _

SECTION C DATA
SECTION B DATA

' - - - - - - SECTION A DATA

Figure 2-4.

BOARD

MPU BOARD

I

REAR

(>

3 DATA BOARDS
(TYPICAL)

K450 Card Cage Arrangement

The K450 configured for 16 inputs (Section A) uses one data board installed in
slot A.
An instrument configured for 32 data inputs (Sections A and B) uses
two Data Boards installed in slot locations A4 and A3. Instruments configured
for extended 48 data inputs (Sections At B and C) use an additional Data Board
installed in slot location A2.
1'\

£.

Board Calibration Control.
The Data Display, Threshold/GPIB/RS-232 and Clock boards have controls for
calibrating circuit functions.
The location of these controls is shown in
Figure 2-4.
The procedure for performing the calibration adjustments is
described in Chapter 3. The following circuit functions are adjusted by these
controls:
CARD CAGE
LOCATION

NAME

A8

Data Display

R20, CRT Vertical Height
R21, CRT Vertical Hold
R29, CRT Focus
R32, CRT Brightness
R47, CRT Vertical Linearity
R56, Audio Alarm Volume
Ll, CRT Horizontal Width
L2, CRT Horizontal Linearity

A6

Threshold/GPIB/RS-232

Rl, R2, Variable B Threshold
R3, R5, DVti Voltage
R6, R9, Variable A Threshold
R7, ECL Threshold
R8, TTL Threshold
R44, Reference Voltage (+ 10V)

A5

Clock

R19, C8 100 MHz Clock
(Oscillator Circuit)

BOARD

CIRCUIT FUNCTION
ADJUSTMENT

SUGGESTED TEST EQUIPMENT
The following is a list of the suggested test equipment for servicing the K450
Logic Analyzer:
ITEM

DESCRIPTION

Extender Board

Gould Part Number 0117-0195-01

Digital Multi-meter

4 1/2 Digits, de Accuracy of +/(0.03% of reading + 2 digits)

Frequency Counter

Capable of 0.01% accuracy on ECL
at 100MHz

Oscilloscope

350 MHz band width, Horizontal
Resolution to 1 nS/DIV

Logic Analyzer

Any current Gould production model

20-Pin, 0.3" IC Clip

Standard

3 Mini Clips/Grabbers

Standard

4.7K-Ohm, 1/4 W, 5% Resister

Standard

2-7

Chapter 3

CALIBRATION AND POWER UP DIAGNOSTICS
GENERAL
This chapter describes the K450 Power Up
procedures for calibrating system components.
as follows:
o

Power Up Diagnostics

o

Probe Test

o

Display Calibration

o

Power Supply Voltage Measurements

o

Threshold Voltage Calibration

o

DVM Circuit Calibration

o

Internal Clock Adjustment

diagnostic test routines and
This information is organized

POWER UP DIAGNOSTICS
The Power Up Diagnostic test verifies the readiness of hardware components
whenever the K450 is powered up from a cold start or restarted.
The power up
diagnostic is implemented by software in the EPRO~1 firmware located on the MPU
printed circuit board.
Diagnostic Operation
As soon as the AC POWER switch is turned ON, the K450 beeps and executes the
diagnostic test routines.
As each test is completed, the next test is run.
When all tests are successfully completed, the Configuration screen displays
the current hardware configuration. The K450 is ready to accept user inputs.
The power up diagnostic is also initiated when the SHIFT and DEFAULT
pressed to reset system operations.
The power up diagnostic
approximately ten seconds to check certain components and perform a
tests.
The following tests and checks are performed by the
diagnostics:
0

Microprocessor RAM Test

0

Microprocessor ROM Checksum Test

0

Keyboard Stuck Key Test

0

System Voltage Test

0

Display Board CMOS RAM Test

0

Threshold/GPIB/RS-232 Board Check
~

,

keys are
runs for
series of
power up

o

DOS Recognition Check

o

Data Board Recognition Check

o

Clock Board Recognition Check

o

Control Board Recognition Check

User Interaction
If an error is detected in any of the tests, the name of the failed test is
displayed and testing is stopped. To run the remaining power up tests, or to
attempt operation of the instrument despite the error condition, press the
NEXT key to resume testing. Press the PREVIOUS key to repeat the test. After
the last test is executed, the Configuration screen is displayed.
Since an
error was detected, the disk-based diagnostic test is used to further isolate
the cause of the error.
As each power up diagnostic test is executed, the name of the test is
displayed on the CRT.
If the test is run successfullY, PASSED is printed
after the test name.
The first failure in a test is indicated by FAILED,
which is printed after the test name.
A test-results header is then printed
on the next line and the results of the test are printed on subsequent lines.
Any more failures causes the results to be printed on successive lines.
A
description of the diagnostic tests is given in in this chapter.
Microprocessor RAM Test Description
The Microprocessor RM1 Test is executed by writing and reading bits in a test
pattern as follows:
1.

Write 0000 to address locations OOOO-FFFF.

2.

Read 0000 from address locations FFFF-OOOO
and write FFFF at each location.

3.

Read FFFF from address locations OOOO-FFFF
and write 0000 at each location.

4.

Read 0000 from address locations OOOO-FFFF
and write FFFF at each location.

S.

Read FFFF from address location FFFF-OOOO
and write 0000 at each location.

This test is repeated, changing the segment registers so that RAM address
locations 0:0000 to 7000:FFFF are all tested.
If all test patterns are read
back successfully, the following is displayed:
MICROPROCESSOR RAH TEST -

PASSED

If any bits fail, the following is displayed:
MICROPROCESSOR RN1 TEST MPU MEMORY FAILURE

3-2

FAILED

MAP OF RAHS ON HPU BOARD (G
COL--)
ROW

{

A

B
C
D
E
F
G
H

4

6

G
G
G
G
G
G
G
G

G
G
G
X
G
G
G

= GOOD,

X

= BAD)

X

Please press NEXT to continue.

PREV to repeat.

Where: COL and ROW positions correspond to the
socket locations on HPU board.

RAM

Microprocessor ROM Checksum Test Description
The ROM Checksum Test computes 16-bit checksums for each of the RO~ls which are
numbered from 1 to 10.
The computed checksum values are then compared with
the expected values which are stored in the top of ROMs 1 and 2.
If the
values match, the test is successful and the system proceeds to the next test.
If the values do not match, the error display indicates the ROM number, the
expected checksum value, and the actual checksum value.
Note that a missing
ROM generates the following:
ROM CHECKSUM TEST

FAILED

ROM
NUMBER

EXPECTED
CHECKSUM

ACTUAL
CHECKSUM

2

463B

ALL "FF"

Keyboard Stuck Key Test Description
This test performs a check of the keyboard matrix for stuck keys.
If one or more keys are stuck, the affected key(s) is displayed below the test
failed message, in a matrix that is continuously updated.
If all keys were stuck, the following is displayed on the CRT screen:
KEYBOARD STUCK KEY TEST NE

CN SH 10 ED AR
HL SP IN ST

PR


HORIZ ~ X48

TRACES

00::0: 15: 15

i212 ...... 1 :3 ...... ·::'0

P~GE

=

8

r_._

1

HFM~----------------------------------~--------~~C
n
11'__ _ _ _~II'-------'~ i'I

r

n

HE_
e:.:ClI

II

'='C f

n
n

AAI

A'::'I-----1I

n

.::.::::I----I\
1 •••• ' ••••

n

n

!

nL-_ _ _ _ _~n

flL..____

1 •••• 1 •••• 1 •••••••••••••• , •••• 1 •••• , . . . . . . .

. 0

A41

A

~

:31

7l

n

,,'--_______~!

n

~
~

n

0
0

~

n

0
42

~~------F~fl'-------_~~n'-

n

fl-12'I

• ••••••• ·., ••••••••• 1 •••• 1

21

A7t
A6L
A5'

n

n
n
n
II~_ _ _ _ _ _ _~~________~r

n

AEI

n

II

'
!
1I~_ _ _ _ _ _~n

!

___--_~,;
fl-~
0

II

II

II

12'1

nL--_____. . .!I'_______ I l'__ _ _ _ _ _ r l'__ _ _ _ _ 12'I
ri''---------:fl~n'_::::::::;::fl~IIL..-------fl-Jn
'-_____ :
---i

---i

A0f1'--________~n~______~n'________~n'___________rL-0
C

TOTAL TRACE TIME = 1. 92mS
rONTROL~0000
REF s 2050
CL=l (R-C)=+2050
r;ii=PAGE UP,
!iiIiI=PAGE DOWN,
_-HOR I Z E~~~P,
Es'·.lERT E~-


c=JO 0
E3

rn

~ §?D~
0

R2.

' .. c::)

H

CJ~;(

9l

~

I

0'080
o

o

•

VERT
LINEARITY

Figure 3-4.

= [jJ

0

Data Display Board Adjustment Points

Adjust the Display board as follows:
1.

Turn the power on and verify unit passes the
test by displaying the Configuration Screen.

power-up

diagnostic

2.

During power-up test, adjust VOLUME (RS6) for good sound. Pressing
an illegal Key with the Error Beep on sounds a brief tone.
The
Error Beep is turned on and off by accessing the Date screen and
pressing the FIELD right arrow and NEXT keys to select the Beep
parameter.

3.

Adjust the VERTICAL HOLD (R21) until the picture locks in on screen.
In further screen adjustments, keep 0.25 inch margins on all
four borders.

NOTE:
4.

Adjust the VERTICAL HEIGHT (R20),
height. Set for the best picture.

5.

Adjust the VERTICAL LINEARITY (R47), verify that change occurs
vertical linearity. Set for the best picture.

3-10

verify that change occurs in the
in

Adjust the FOCUS (R29),
for the best picture.

7.

Adjust the BRIGHTNESS (R32), verify that change occurs in brightness.
Set for the best picture brightness.

8.

Adjust the HORIZONTAL WIDTH (L1), verify that change occurs in width.
Set for the best picture.

9.

Adjust the HORIZONTAL
horizontal linearity.

10.

verify that change occurs in focus.

Set

6.

LINEARITY (L2), verify that change occurs in
Set for the best picture. Turn the power off.
A grid appears

Hold down the SHIFT key and turn the power on.
the screen, as shown in Figure 3-5.

\

~

7

.~

/

V

~

~

~

~

~

~
I

, ,I' V

/

/

/

/1
V

/

/

-

\

:

~

V

V

/'

~

~

~

:

'K ,
~

:

~

Figure 3-5. CRT Grid Pattern
3-11

on

11.

Good linearity and picture is shown by the grid pattern.
adjustments to get a uniform picture in the display.

Repeat the

12.

Verify if the VIDEO output signal at the rear panel BNC connector is
present as follows:
a.

Connect a 50-ohm coaxial cable from the Composite Video Out BNC
connector of K4s0 to one input of scope.

b.

Use a I-Megohm input scope termination.

c.

Set the scope for 1 volt/division and ground.

d.

Verify that a 1.6V pp pulse occurs every 64 usec.

POWER SUPPLY VOLTAGE MEASUREMENTS
The user cannot adjust the K4s0 Power Supply.
A voltage measurement check
determines if the power supply is functioning properly.
If the measured
voltages are not within the specified limits, the power supply must be
replaced. Voltages are measured at the power supply terminal board locations,
as shown in Figure 3-6.
The measurement is taken between the specified
voltage signal and its respective return.

NOTB: The power supply should warm up for at least 10 minutes before checking
the supply voltages.

RESET
+5

2

+5 RTN

3

+15 RTN

4

+15

5

-15

6

-15 RTN

7

-2

8

-2

9

-2 RTN

10

-2RTN

11

-5.2

12

-5.2

13

-5.2

14

-5.2 RTN

15

-5.2 RTN

16

-5.2 RTN

17

POWER
SUPPLY

REAR

Figure 3-6.

Power Supply Voltage Measurements
3-12

The measured voltages must be within the following ranges:
RANGE
MINIMUM
MAXIMUM

NOMINAL VOLTAGE
+15V

+14.4

to

+15.6V

+ 5V

+ 4.8

to

+ 5.2V

- 2V

- 2.2

to

- 2.0V

- 5.3V

- 5.5

to

- 5.1V

-15V

-15.6

to

-14.4V

THRESHOLD VOLTAGE AND DVM CALIBRATION
The following adjustments are made on the Threshold/GPIB/RS-232 Board:
0

10V Reference Voltage Adjustment

0

TTL Threshold Adjustment

0

ECL Threshold Adjustment

0

Variable A Threshold Adjustment

0

Variable B Threshold Adjustment

0

DVU Adjustment

The location of potentiometers is shown in Figure 3-7.
and test equipment is required:

The following

tools

o

Extender Board:

Gould Part Number 0117-0195-01

o

Digital Multimeter:

4 1/2 Digits, DC accuracy of +/- (0.03% of
Reading plus 2 Digits)

o

4 • 7K-0 hm , 1 /4 W,
5% Resistor:

o

Standard

External voltage source of +/- 20.000 Vdc +/- 3mV

Use the following procedures to make the adjustments:
NOTE: To set for Threshold adjustments, turn the power off. Turn the power
on to get the Configuration screen.
Pressing the FI key moves the cursor to
the top Threshold location on the screen.

IOV Reference Voltage Adjustment
1.

Turn the power off, remove the Threshold/GPIB/RS-232 Board from the
card cage and install on an extender board.

2.

Turn the power on and verify unit passes power-up diagnostic test by
displaying the configuration screen.
'1_1'1

3.

Connect the external DVM reference (-) to the board A GNU test
point. Connect the Dm1 (+) input to the right side of resistor R38.
See Figure 3-6.

4.

Adjust R44 for a DVM reading of +10.00 +/- O.OlV.

REFERENCE VOLTAGE
GROUND POINT

REFERENCE VOLTAGE
MEASUREMENT POINT

THRESHOLD/GP1 Bf RS-232 BOARD

D

o

D o D

o

D

VAR A OFFSET ADJ

VAR B OFFSET ADJ

Figure 3-7.

Threshold/GPIB/RS-232 Board Adjustments

TTL Threshold Adjustment
Remove all input cables from the unit.
This procedure uses a 4.7K-Ohm
resistor which serves as a load for adjustment of threshold voltages.
All
voltages are measured accross the resistor. The TTL adjustment procedure also
verifies that no shorts are present between High and Low inputs, and between
Data and Clock inputs.
The TTL adjustment is performed on each front panel
input connector as follows:
1.

Configure the K450 unit with three Data Boards to provide 16 inputs
at each SECTION Input (A, B, and C).

2.

Install the 4.7K-Ohm resistor between sockets 2 (ground) and 14
(Clock Threshold input) at SECTION A (bits 7-0).
Connect the DVM
positive (+) lead to socket 2 and the DVM negative (-) lead to
socket 14 so that the voltage measurement is taken across the
resistor. See Figure 3-8.
3-14

+

.2

o

0

o
15

DVM

SECTION INPUT CONNECTOR

Figure 3-8.
the

Test Connections for Threshold Voltage Adjustment

3.

Press

FORHAT

Key

verify that all Thresholds are set to TTL.

4.

Press the ARM key on keyboard

5.

Adjust the TTL

6.

Relocate the resistor to SECTION A Inputs (bits F-B) connector
and verify the TTL Threshold of +1.400 +/- smV is present.

7.

Check the TTL level of other inputs by moving the load resistor
to input connectors at SECTIONs Band C.
Verify the TTL Threshold
of +1.400 +/- smV is present at sockets 2 and 14 of each low-byte
(bits 7-0) and high-byte (bits F-B) connector.

B.

Install the 4.7K Ohm resistor between sockets
Threshold). Repeat steps 3 through 7.

9.

Ensure no shorts are present between Low and High inputs, as well as
between Data and Clock inputs by performing the following test:

THRESHOLD (RB) for a DVM reading of +1.400 +/- 2smV.

2

and

15

a.

Press the FORMAT key to select the Format M screen.
the
Fl key to move cursor to top Threshold location.
quick key 1, to change TTL level to ECL.

b.

Move the cursor down by pressing the FIELD down-arrow key
and press quick key 1 to change TTL level to ECL.

c.

Press the ARM key.

d.

Install the 4.7K-Ohm
15 (Data Threshold)

3-15

(Data

Press
Press
once

resistor between sockets 2 (ground) and
of SECTION C upper INPUT Connector.

Connect external DVM positive (+) lead to pin 2 and negative
(-) lead to pin 15.
Verify that the ECL Threshold of -1.300V
+/- 25mV is present.
e.

Install the 4.7K-Ohm resistor between pin 2 and 14 of the
same connector.
Connect the DVM leads and verify that the TTL
Threshold of +1.400V +/- 25mV is present. If the D~1 reads ECL
Threshold instead of TTL Threshold, this indicates a short is
present between Data Input and Clock Input lines.

f.

Install the resistor between pin 2 (ground) and 15 (Data
Threshold) of SECTION C~~er input connector.
Connect the
DVM leads and verify '8!t Threshold off I .40.9'V,,1 +/- 25mV is
present. If the DVM reads ECL instead of TTt~is indicates a
short is present between High and Low Data Input lines.

g.

Repeat substep e for this connector.

h.

Repeat substeps d through f for SECTION B and SECTION A.

EeL Threshold Adjustment
The ECL Threshold adjustment is performed for each front panel input connector
as follows:

1.

Install the 4.7K-Ohm resistor at sockets 2 and 14 of SECTION A input
connector (bits 7-0). Connect the DVM positive (+) lead to socket 2
and the DVM negative(-) lead to socket 14 so that the measurement is
taken across the resistor.

2.

Make the following keyboard entries to change all thresholds
TTL to ECL:
a.

Press the FORMAT key to access the Format screen.

b.

Press the Fl FUNCTION
Threshold location.

c.

Press and hold quick Key 1
threshold voltages.

d.

Press the ARM key to change DVM reading to ECL level.
ECL levels for all inputs.

key,

to move the cursor to
until ECL is

selected

from

the

Top

for

all

Select

3.

Adjust the ECL THRESHOLD (R7) for DVM reading of +1.300 +/- 25mV.

4.

Relocate the resistor to SECTION A (bits F-8) input connector
verify the ECL Threshold of +1.300 +/- 5mV is present.

5.

Check the ECL level of other inputs by moving the load resistor
to input connectors at SECTION B and SECTION C.
Verify the ECL
Threshold of +1.300 +/- 5mV is present at sockets 2 and 14 of each
low byte (bits 7-0) and high byte (bits F-8) input connector.

3-16

and

Variable A Threshold Adjultmant
The Variable A Threshold adjustment is performed for each front
connector as follows:
1.

2.

panel

Install the 4.7K-Ohm resistor at sockets 2 and 14 of the SECTION
A Input connector (bits 7-0).
Connect the DVM positive (+) lead to
socket 2.
Connect the DVM negative (-) lead to socket 14 so the
measurement is taken across the resistor. See Figure 3-8.
Make the following keyboard entries:
a.

Press the FORMAT key to access the Format screen.

b.

Press the FUNCTION key, Fl, to move cursor to the top threshold
location.

c.

Press and hold quick
threshold voltages.

d.

Press the ARM key to change DVM reading to VARA
inputs should read VARA = 9.99V.

Key 2 until VARA is selected

D~1

3.

Adjust the VARA GAIN (R6) for

4.

Make the following keyboard entries:

for

all

level.

All

reading of 9.990 +/- SmV.

a.

Press the FIELD right-arrow key to move the cursor to 9.99.

b.

Press and hold Quick Key 0 until 9.99 inputs are set at 0.00

c.

Press the ARM key.

All inputs should read VARA

= O.OOV.

5.

Adjust the VARA OFFSET (R9) for DVM reading of 0.000 +/- 5mV.

6.

Make the following keyboard entries:
a.

Press and hold Quick Key 9 until 0.00 inputs are set at 9.99.

b.

Press the ARM key.

7.

Adjust the VARA GAIN (R6) for DVM reading of +9.990 +/- SmV.

8.

Make the following keyboard entries:

9.

input

a.

Press the FIELD left-arrow key to move cursor to the + position.

b.

Press the NEXT key to change positive (+) to negative (-) value.

c.

Press the ARM key.

Read the DVM and adjust the VARA GAIN (R6) for -9.990V + 1/2 the
difference of actual reading and -9.990V.
(For example, if the
actual DVM reading is -9.98V, subtract this value from -9.990V. The
difference of -O.OlV is divided by 2 to obtain -0.005V and R6 would
be adjusted for -9.995V.)

3-17

10.

Repeat steps 6 through 9 until the offset is the same
positive and negative voltages +/- 3OmV.

for

both

Variable B Threshold Adjustment
The Variable B Threshold adjustment is performed for each front panel input
connector. The procedures are the same as steps 1 through 10 for the Variable
A adjustment, except as follows:
1.

Install the 4.7K-Ohm resistor at SECTION A input connector
described in Variable A Threshold adjustment procedure.

2.

Make the following keyboard entries:

as

a.

Press the FORMAT key to access the Format screen.

b.

Press the
threshold.

c.

Press and hold quick Key 3
threshold voltages.

d.

Press the ARM key to change the DVM reading to the VARB level.
All inputs should read VARB = 9.99.

Fl

FUNCTION key,

to

move the cursor

to

until VARB is selected

top
for

3.

Adjust the VARB GAIN (R1) for a DVM reading of 9.990 +/- SmV.

4.

Make the following keyboard entries:
a.

Press the FIELD right-arrow key twice to move the
position 9.99.

b.

Press

c.

Press the ARM key.

and

hold quick Key

a

All inputs should read VARB
D~1

Adjust the VARB OFFSET (R2) for a

6.

Make the following keyboard entries:
Press

and

b.

Press the ARM key.

all

to

until 9.99 inputs are set at 0.00.

S.

a.

cursor

of

= +o.OOV.

reading of 0.000 +/- SmV.

hold Quick Key 9 until 0.00 inputs are set at 9.99.

7.

Adjust the VARB GAIN (Rl) for a DVM reading of +9.990 +/- SmV.

8.

Make the following keyboard entries:
a.

Press the FIELD left-arrow key to move the cursor left to the
(+) position.

b.

Press the NEXT key to change from a positive (+) to a
(-) value.

c.

Press the AIDi key.

3-18

negative

9.

Note the value of the DVM reading and adjust the VARB GAIN (Rl) for
- 9.990V + 1/2 the difference of actual reading and -9.990V.

10.

Repeat
steps 6 through 9 until the offset is the same
positive and negative voltages, +/- 30mV.

for

both

DVM Circuit Adjustment
The user must provide an external voltage source of +20.000 +/- 3mV dc that is
used to calibrate the K450 Digital Voltmeter (DVM) circuit.
The adjustment
controls for D~1 GAIN (R5) and DVM OFFSET (R3) are located on
the
Threshold/GPIB/RS-232 Board shown in Figure 3-7.
The Configuration screen provides a DVM readout for making the adjustments.
Note that any display screen reads the DVM voltage except those displays for
Memory A or B.
Use the following procedure to calibrate the
on

circuit:

D~1

1.

Turn the power
diagnostic test.

and verify if the

unit

passes

the

power-up

2.

Connect
output.
output.

3.

Set the external dc voltage source for a DVM reading of +20.000 +/3mV.

4.

Connect
the positive lead of an external voltage source to the POS
DVM INPUT jack located on the K450 front panel.
Connect the
negative lead of an external voltage source to the NEG DVM INPUT
jack on K450 front panel.

5.

Check the voltage indication at the external-voltage source to
verify if the adjusted value of +20.000 +/- 3mV is still present.
Readjust the voltage if necessary.

6.

Watch the DVM value on the screen.
DVM value of +20.00V.

7.

Set the external DC voltage source to indicate 0.000
watch the DVM value on the screen.

8.

Adjust the DVM OFFSET (R3) for a DVM value of O.OOV.

9.

Set the external dc voltage source to -20.00V +/- 3mV.
DVM value on the screen.

the DVM POS (+) lead to external dc voltage source positive
Connect the DVM NEG (-) lead to an external dc negative

Adjust the DVM GAIN (R5) for a

10.

Verify if the DVM value is -20.00V.
this reading.

11.

Repeat steps 3 through 10 until the DVM values of
O.OOV are +/- 3mV.

1-1Q

+/- 3mV

and

Watch the

Adjust the DVM GAIN (R5) to get
+/- 20.00V

and

INTERNAL CLOCK ADJUSTMENT
This adjustment is performed on the Clock Board.
and external clocks, and enable circuits.
The following
adjustments:

tools

and

test

This board selects internal

equipment are required

to

make

the

clock

o

Frequency Counter: Capable of 0.01% accuracy on ECL at 100 }ffiz

o

Oscilloscope: 350

o

Extender Board: Gould Part Number 0117-0195-01

MHz Band Width, Horizontal Resolution to 1 ns/Div

Adjustment is as follows:
1.

Turn the power off and remove the Clock Board from the card
Install on the Extender Board.

2.

Connect six cables and probes to front panel connectors at
A, B, and C.

3.

Turn the power on and verify the power up diagnostic test by seeing
the Configuration screen.

4.

Set the oscilloscope to .05V/div.
Use a Tektronix P6106 XI0, 1
megohm probe.
Set the time base to 2 ns/div.
Set the trace base
line at +1.30 V above the center line so that the ECL threshold
(- 1.30V) is at the center line of the screen.

5.

Connect the oscilloscope probe tip input to pin 12 (output) on the
100102 IC device at board location 12C.
Connect the probe ground
lead to the ground lug at board location 11B.
See Figure 3-9 for
clock board component locations.

6.

Adjust pot R19 for approximately 50% duty cycle,
the ECL threshold.

7.

While probing IC 12C, pin
peak-to-peak amplitude.

8.

Re-adjust symmetry pot R19 for a 50% +/- 2% duty cycle about the ECL
threshold.
Monitor IC 12C pin 12 or 13 with an oscilloscope.
Verify that the rising and falling edges are sharp, not fuzzy.

9.

Connect a frequency counter (use non-metalic adjustment tool) with a
1 megaohm input to IC 12C, pin 12 or 13. Verify for a frequency of
100 MHz +/- .1% (99.9 MHz to 100.1 MHz).

10.

Turn off the unit.

11.

Turn on the unit and should see a frequency of 100 tfllz on the scope.
If the frequency is not stable, repeat steps 1 through 11.

12.

off the unit and remove the clock board from the
Turn
Install the clock board inside the K450 chassis.
board.
the unit.

12,

SECTION

symmetrical

adjust trimmer cap C8 for

cage.

about
maximum

extender
Turn on

13.

Check for the proper frequency and duty cycle (symmetry) at IC 12C,
pin 13.
Re-adjust if necessary.
Use the scope probe tip with
insulated ground.
Use the same ground lug location with short
ground lead attached.

14.

Turn the unit on and off.

Re-check the frequency.

GROUND LUG

FREQUENCY ADJUST
(C8)

CLOCK BOARD

GNDI

}L.-_~

B

?

DEVICE AT BOARD
LOCATION 12 C

Figure 3-9.

Clock Board Internal Clock Adjustment

1.-?1

Chapter 4
THEORY OF OPERATION
GENERAL
This chapter describes the theory of operation for the K450 Logic Analyzer.
An overview of the operation is presented to show the relationship of the
various circuit functions.
The overview is followed by a description of
internal circuit functions for each printed circuit board. These descriptions
are referenced to specific board components and circuit functions found in
chapter 7. A block diagram is provided to support these descriptions. Theory
of operation is provided for the following printed circuit boards:
0

Data Display Board

0

MPU Board

0

Threshold/GPIB/RS-232 Board

0

Clock Board

0

Data Board

0

Control Board

OVERVIEW OF K450 UNIT OPERATION
The block diagram of Figure 4-1 presents the overall K450 system data flow and
control operations.
This diagram also shows the K450 system architecture and
interaction of board circuit functions.
MPU Board Interaction
The K450 Logic Analyzer employs a 16-bit, 8086 microprocessor for controlling
system operations. The 8086 CPU is located on the Master Processor Unit (MPU)
board. The MPU Board addresses all other boards in the system as I/O devices.
The MPU Board communicates with the circuit boards through the multiplexed
address/data bus interface on the motherboard.
The operating system uses up
to 256K bytes of ROM and 512K bytes of RAM on the MPU board.
The K450 operating system and power-up diagnostic routines are firmware stored
in the ten EPROM chips located on the MPU board. This firmware executes the
K450 operations that perform digital circuit analysis and processing of
external data and clock signals supplied by the user's equipment.

DATA BOARDS (2 OR 3)

r-------------

____________________________ ,

1
AFASI

01

DETECT

,
DATA
LATCH

1
1
1

L~~~~~

FRONT

I

I
BUS
I'I..---.".INTERFACE
I

1

1
I
I1
I

:.:.:.:.:.:.:.:.:.-:.=J
ARMED

RAM

11.K

L _______________________ J

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--~--ll--~ TO REAR PNL

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SERIAL OATA

TRACE. BNC

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1
1

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_
~M~E~~

L! _____ --------------TO PROBE PODS

iMPUOOMW---------------------l

I: I
I 'I

1 1 1
1 1 1
1 I
1 1 1
1 I 1
1 1 1
11 11 1I

GLITCH
FRONT PANEL
DATA INPUTS
FROM
ACTIVE PROBES

I,

SYNCH

-------------,
I
I

1

I

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1

1L ____________________ _

IL __

I I

_____ -1

CMOS RAM

TO DATA BOARDS
TO CON~ECTORS
ON REAR PANEL

I
I
I
I
1

FRONT PANEL! R & S CLOCKS
CLOCK INPUTS
FROM
ACTIVE PROBES

J & K CLOCKS

VIDEO

-----,

I

(~~=======:::..-===:=r--...J

I
I
I
I

H SYNCH

CRT DRIVER

V SYNCH

I
I

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IL ___ _

I

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FROM KEYBOARD

I
I

TO REAR PANEL
VIDEO BNG

__ -1
TO REAR PANEL
CLOCK BNC

MOTHERBOARD ADDRESS/DATA BUS

(OPTIONAl)

Information collected and analyzed by the system is recorded in main memory.
The results are selectively accessed by the user and displayed on demand. The
MPU Board provides the control functions for display, display setups, memory
transfer, memory control, memory compares and keyboard input.
Data Board Interaction
The external data and clock input signals collected by the probes are supplied
to the input panel.
The data input signals (7-0 and F-8) are directed to the
Data Board.
The clock input signals (J & K and R & S) are sent to the Clock
Board.
The Data Board functions have circuits that buffer the input data
signals, select high/low bytes and detect glitches.
These functions define
the sample content through pipeline control circuits to main memory and word
detection RAJ! on the Control Board.
Control signals from MPU holding
registers select the data source that is passed through the sampling
circuitry. Input signals from the Control Board initiate the ARMED and TRACED
condition so that the sample is recorded in Memory.
Clock Board Interaction
The
and
in
on
the

Clock Board combines and selects clock signals to generate Latch, Sample
Master clocks. The J & K clock inputs and R & S latch inputs are combined
user defined AND/OR Boolean expressions.
The internal clock is generated
this board.
It is always available at the CLOCK output BNC connector on
rear panel.

The 100MHz internal clock is also generated on this board. The user selected
clocks and combined clocks are routed to the Data Boards and the trace Control
Board. The PROBE TEST output signal at the front panel connector is generated
by the pattern generator on the Clock Board.
Control Board Interaction
The Control Board contains decision making logic for control of the trace and
recording process.
This includes word recognition circuIts that detect the
sample data supplied from the Data Boards. Delay counter logic combines delay
conditions with detected words to set up sequencing for Stop Recording, Jump
or advance to another recording level with different parameters.
Delay
counter logic also enables or disables input sample data recordings~
The
trace control logic resolves these conditions to initiate the ARMED and TRACE
signals.
These signals are sent to the Data Board to enable recording of the
traced information.
The Control Board also generates the TRACE output signal
supplied to the BNC connector on the back panel.
Threahold/GPIB/RS-232 Board Interaction
The Thresho1d/GPIB/RS-232 Board generates two variable,
and two fixed
threshold voltage sources that are supplied to the probes.
The variable
voltages are VAR A and VAR B.
The fixed voltages are TTL and ECL. Threshold
control circuits enable each probe to select one of these voltage sources. The
VAR A and VAR B threshold levels are driven by software-controlled, digita1to-analog converter (Dac) circuits. A comparator circuit performs the ana10gto -digital conversion (ADC) that is used by the power-up diagnostic to
measure power supply voltage levels.

The TTL and ECL Threshold sources use a voltage divider network and +/- lOV
reference voltage for generating the fixed levels. Both the RS-232 and AUX
serial communication links are driven by a Universal Synchronous/Asynchronous
Receiver/Transmit (USART) chip.
The GPIB (IEEE-488) parallel interface for
Talker/Listen modes transfer data under control of an Interrupt line.
The
GPIB control circuits generate the interrupt signal supplied to the Data
Display Board.
The GPIB control circuits generate the GET (Group Execute
Trigger) output signal supplied to the BNC connector on the rear panel.
The
DVM input supplied from the front panel is buffered to the Threshold/GPIB/RS232 Board where the analog-to-digital conversion takes place.

Data Display Board Interaction
The Data Display Board presents a display pattern that is derived by the MPU
processing and stored in the RAM as a complete dot map.
Each dot location of
the CRT is represented by a bit in the RAM (where 1 = white, 0 = black). Each
dot is supplied to video control circuits on the Data Display Board.
The
video control circuits accept CRT address clocking information and serial
input data supplied by the MPU.
The circuits generates the video control
signals that drive the horizontal, vertical, and synchronization for the CRT.
The CRT controller circuits continuously interact with processor circuits to
generate direct memory access cycles from the RAM. This data is translated to
the CRT.
A 16-bit word is read from the RAM every 2 us and converted into a
string of 16 dots on the CRT.
The Data Display Board also accepts interrupt
signals generated by other board circuits.
The interrupt signals are used by
the Data Display Board interrupt processor to send an interrupt to the }1PU.
The Data Display Board provides the Keyboard interface and DOS interface. The
Real Time Clock and CMOS Memory Save circuits are backed up by battery power.
These batteries drive the circuits when facility power is interrupted or
removed from the K450 unit.
The Audio Error Alarm circuit is also contained
on the Data Display Board.

DATA DISPLAY BOARD OPERATIONS
Overview
This section describes Theory of Operation for the K450 Data Display Board
assembly, Part Number 0114-2010-60 or 0114-3010-60.
The board assembly
drawing, schematic diagrams and list of material are provided in Chapter 7.
Reference is made to the schematic diagrams throughout the descriptions of
circuit functions. The Data Display Board block diagram is shown in Figure 42. The following board circuit functions are described:
o

CRT Controller (Schematic sheets 1, 2 and 3)

o

Interrupt Processor (Schematic Sheet 4)

o

Keyboard and Front Panel Interface Circuit (Schematic Sheet 4)

o

CMOS RAM Save Circuit (Schematic Sheet 5)

o

Audio Error Alarm Circuit (Schematic Sheet 4)

o

Real Time Clock (Schematic Sheet 6)

o

DOS Interface Circuit (Schematic Sheet 6)
4-4

FROM
THRESHOLD/GPIB/RS·232
BOARD

I

CMOS POWER
BATTERY
BACK·UP

FROM MPU BOARD

D

..
~

REAL TIME
CLOCK
MSMS832

TO MPU BOARD

CRT
ADDRESS
GENERATION

~

CMOS
MEMORIES
6116

j'-\,-

CMOS
ADDRESS
GENERATION

1'1
tD
~

u

N

I

~

I

•

I

VERTICAL
PROM

~

Vt

0

n

I

o

~

:--

INTERRUPT
INTERFACE
74LS240

N

~l--lO_~~
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l

HORIZ
PROM

~E=-N_A_B_L::..:E=4

ADDR COUNTER

INTERRUPT
CONTROL
8259A

~

~

C»

"

RAM ADDRESS
INTERFACE

"ZK
A0-15

ADDRESS
BUS
INTERFACE

CJ
(ii

~

ADDRESS
BUS
INTERFACE

ROM
MEMORY
256K

-.J

0

0::

....
z

«
....
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0
en

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AND TIMING

DATA OUT BUS

:::>(/)
0..:::>
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L-...., ROM CONTROL

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00

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CRT SERIAL
DATA
RAM
MEMORY

DATA BUS
INTERFACE

~

•...

CA0-15

TO DATA

~ DISPLAY
BOARD

Address Registers and Data Transceiver.
The 8086 microprocessor uses a multiplexed bus for address and data transfers
(sheet 2 of schematic diagrams).
The MPU Board demultiplexes the 8086 bus
into two buses. One bus controls all information to the ROM and the RAM which
is contained on locations 1A to IE, 2A to 2E, 4A to 411 and 6A to 6H.
The
other bus interfaces with other boards in the K450. Locations 9H, 10H and l1J
are buffers for 20 memory address lines (AO to A19) and BHE.
Locations 9K,
10K and 11K are buffers for 20 address lines and BHE to boards other than the
~lPU.
The transceivers for the data lines are located at locations 7K and 8K.
Locations 7J, 7H, 8J and 8H are wired for PROM's and buffers for temporary
test only.
The 8086 loads addresses into the address registers by using the
Address Latch Enable signal (ALE) and then transmits (WR) the data to, or
receives (RD) the data from, the address in the register.

Memory
The 8086 memory space is organized into 16 segments of 64K bytes of external
memory space (sheets 2 and 5 of schematic diagrams).
Segments C, D, E and F
(Hex) are the 256K bytes of ROM which contains the operating software.
Segment 0 - 7 (Hex) contain the 512K bytes of dynamic RAM.
The ROt1 segment (schematic sheet 7), locations lA to IE and 2A to 2E, uses
sixteen 16K X 8 memories arranged into eight sections of 16K words each.
Locations 3L and 3M (schematic sheet 6) are ROM chip select decoders.
Data
output is read from ROM through a buffer at location 3J for high-byte data and
at location 3K for low byte data.
The RAM segment (schematic sheets 3 and 4 ), locations, 4A to 4H and 6A to 6H,
is made up of sixteen 256K X 1 dynamic memories providing 256K words (512K
bytes).
Data is input into the RAM, through the buffer at location 4J for
high-byte data and at location 6J for low-byte data through RAM WRITE DATA EN.
Data output is read from RAM through the latch buffer at location 4K for highbyte data and at location 6K for low-byte data through MPU LATCH ENABLE and EN
RAM READ.
CRT Data is read out into buffer registers at locations 6L and 4L
and then shifted out at an 811Hz clock rate to the Data Display Board by shift
registers at locations 6M and 4M.

Memory Controller
The memory timing and the clock for the 8086 microprocessor (sheet 5 of
schematic diagrams) are derived from a 24 MHz oscillator (location Y1).
Locations 10E, 10D, 12J, 12C, llC, lID, lIE and l2B are used to divide to an 8
MHz clock to the CRT and a 4 MHz clock to the 8086 clock pin.
Locations lIE,
l2E and l2F divide the 24 ffilz clock into timing signals used to generate Row
Address Strobe (RAS) at locations 10C and 8B.
Additionally, column Address
Strobe (CASO and CASl) are also generated at locations 8A, 9A and l2D. Write
Enable signals for high-byte and low-byte of both RAM segments are generated
at locations 7A, 8A, 8B, lOA and lOB.
Row Select, Column Select and Latch
Enable for both the MPU and CRT are generated at locations 9A and 9B.
The CRT port of the memory requests a word from memory every 2 us (500 KHz).
The CRT page select addresses are generated at locations 7C, 7D, 8C and 8E
(sheet 6 of the schematics) by the 500 KHz clock rate from location 7B.

If the 8086 requests a memory cycle during the CRT cycle, the memory
controller uses the READY line on the 8086 microprocessor to generate wait
states until the CRT cycle is finished.
The memory then completes the
requested 8086 memory cycle. The CRT Read cycle of one word every 2 usec also
provides sequential operation required for the RAM refreshing.
I/O Decoding
The MPU Board addresses other boards in the system as I/O.
The PROM
(schematic sheet 4) at location 10F is used to decode addresses All to A19.
When I/O is addressed, M/IO goes LOW, causing the PROM's outputs to be IIIGH.
The conditions in which S.A EN is normally HIGH and DEN (Data Enable) becomes
active and causes the EN OFFBOARD DATA signal at location 9C to go LOW,
placing data on the bus.
Read commands for RAM, ROM and S.A are generated by
RD, RAM ADRS, ROM ADRS and S.A at locations 9D and 9E.
Control signals RD,
WR, DEN, DT/R and M/IO are also buffered out to other boards through buffers
at location 9G.

THlESHOLD/GPIB/RS-232 BOARD OPERATIONS
Overview
This section describes the theory of operation for the Threshold/GPIB/RS-232
Board assembly, Part Number 0114-0170-30. The circuits on this board generate
threshold voltage levels, convert analog voltages to digital equivalents,
control the GPIB Talker/Listener interface, control the RS-232 Interface and
process digital readout of external voltage input.
The Threshold/GPIB/RS-232 Board block diagram is shown in Figure 4-4.
The
board assembly drawing, schematic diagrams and list-of-materials are provided
in Chapter 7.
Reference is made to the schematic diagrams throughout the
descriptions for the following circuit functions:
o

Threshold Circuit (Schematic Sheet 1)

o

DVM Circuit (Schematic Sheet 2)

o

GPIB Interface Circuit (Schematic Sheet 3)

o

RS-232 Interface Circuit (Schematic Sheet 4)

o

MPU Interface (Schematic Sheet 5)

Threshold Circuit
The Threshold Circuit (sheet 1 of schematic diagram) generates voltage
sources, (VAR A, VAR B, TTL and ECL) that may be selected for each probe.
The VAR A and VAR B thresholds are defined by the four 74LS273 Flip-Flop
holding registers.
Locations 9B and 12B for VAR A, and locations 4B and 6D
for VAR B.
The holding registers buffer the MPU data bus to the two AD7533LN
Digital-to-Analog Converters (Dac) at location 9A for VAR A and location 4A
for VAR B.
Separate calibration adjustments are provided for VAR A and VAR B
Voltage levels.
The VAR A Gain is adjusted by R6; Offset is adjusted by R9.
The Offset is adjusted by R2.
Both Dacs
The VAR B Gain is adjusted by Rl.
have a resolution of 10 bits.

The TTL and ECL thresholds are generated by using a voltage divider network
and +/- lOV reference voltage level. The calibration adjustment for TTL is R8 t
ECL is adjusted by R7. The +/- lOV reference adjustment is controlled by R44.
The threshold voltages are supplied as input to eight analog multiplexers
(sheet 2 of schematic diagrams).
The selection of a particular threshold
voltage (VAR A, VAR B, TTL or ECL) used by each probe is accomplished by a set
of eight analog multiplexers and eight buffer amplifiers.
Six of the
multiplexers, at locations lA, lD, lB, lC, 2A and 2D are tied to high and low
data bytes at input sections A, Band C. Two of the multiplexers are tied to
R & S latch clocks (location 2B) and J & K sample clocks (location 2C). This
allows the software to select one of the four voltages as the threshold.
The
outputs of the analog multiplexers are buffered by the operational amplifiers
(locations IE and 2E) which provide a gain of two that increases the range of
the Dac output.

4-14

..

iNTERRUPT SIGNAL
J TO DATA DISPLAY BOARD

(INT CONTROU.ER)

~



CD

S

..

o

~1'1

~

co

,

.&:-

0\

•

~

MEMORY DATA

.&:-

~------~---

DATA

V1
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tv
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PIPELINE DATA BUS

0

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~

0

FROM FRONT
PANEL INPUT
CH 0-7

Q)

1'1

Po-

~
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0

L LATCH
_______________________________
oJ,
AND GUTCH CAPTURE

~
t::1
....

S»

OQ
1'1

;

INPUT MODE SELECT

MPU/POWER.lJP DIAGNOSTIC INPUT

NOTE

CLOCK BUS SIGNALS
ARE AS FOLLOWS
I. PIPE LINE CLOCKS

2 WRITE ENABLE I AND 2
3. LATCH CLOCKS
4 231 CLOCKS
5.176 CLOCKS

MUX AODR~SS 0.1 MUX ENAHll

---

MPU ADDRESS/DATA BUS

c:==_

----~----

--

-

~

-"-

Operating Modes
The output of the 10121 gate at location 2D (schematic sheet 3) is presented
to the mode selection circuit consisting of two 10HI06 gates at location 2E,
the two IOR130 latches at location 2H and IOR131 latches at location 2J. This
circuit has three different modes of operation, Sample Mode, Latch Mode, and
Glitch Mode which are described in subsequent paragraphs.
Sample Mode: Pins 6 and 12 of the 10Rl06 gates, location 2E are held high by
the ~1PU, causing these gates to become disabled in sample mode. Pins 6 and 9
at the IOH130 latch, location 2R are held low by the MPU which causes the
latch output to follow the input asynchronously. The 101l13l latch at location
2J is the sample register.
The input data is transferred to the output and
held at the rising edge of the sample clock on pin 9.
Latch Mode: The gate, 2E is disabled as described in Sample Mode.
Pin 6 of
the IOR130 latch at location 2R is held low allowing the Latch Enable Clock at
2R, pin 9 to control the latch.
When the latch clock is low, 2R is
transparent as in sample mode.
When the latch clock goes high, the data that
was true at the clock transition is held at the output.
The 10R131 sample
register at location 2J functions the same as sample mode conditions.
Glitch Mode:
The MPU signal Glitch Disable, is low in this mode allowing
outputs of the 10HI06, location 2E to be controlled by the input data and the
data in the sample register.
The MPU signal, Glitch Enable, is high in this
mode, thereby disabling the D input pin of the 10R130 latch at location 2E.
The state of the 2R latch output is then controlled by the outputs of 2E
through the asynchronous set and reset pins.
Sampling Circuit Operation
The sampling circuit (sheet 3 of schematic diagram) operates as follows:
Assume that pins 2 and 15 of the 10R130 and 10H13l latches, at locations 2R
and 2J respectively, are high at the start of operation. - The input pin 5 of
gate 2E is high thereby disabling the upper gate that goes to pin 5 of latch
2H.
The input at pin 13 of gate 2E is low which allows any low input signal
to reset 2R, pin 2 by placing a high on the direct reset, pin 4.
Pin 2 of
latch 2R remains in this new state regardless of any activity on the input
signal.
At the next sample clock, the output of pin 15 at latch 2J goes low which
enables the upper gate of 2E to respond to a high input signal only.
If the
input signal goes high at anytime, the signal at pin 3 of gate 2D goes low
causing pin 3 of gate 2E to go high which sets the output of latch 2R to a
high condition for the next sample clock.
In addition to going to the Glitch Feedback Comparison Gates,
register are also supplied to:

outputs of

the

1.

The 10174 multiplexer at location 2L for MPU diagnostic access.

2.

The pipeline register 10176, location 2K.

3.

Inverted data from pin 14 of latch 10R13l goes to the Control Board
word recognition circuits.

5 ns Sampling (200 MHz Operation)
The DEMUX SELECT signal is active low at 2D, pin 9 and 2C pin 12. This allows
data from the same channel (channel 7 in this example) to be sampled by Ie's
1H and 2H. A rising edge of the LATCH CLK 0-7 signal, latches the data at 1H,
pin 7. Then 5 ns later a rising edge of the LATCH CLK 8-F signal, latches the
data at 2H, pin 7.
Since the data going to these two pins are from the same
channel, data is sampled every 5 ns.
The outputs of 1H and 2H are then
sampled by 1J and 2J every 10 ns.

Data Pipeline Control
The Data Pipeline (sheet 3 of schematic diagram) consists of two stages of D
registers contained in the 10176 latch at location 2K.
The source of the
pipeline clock depends on either of two clock modes selected.
In most modes,
the pipe clock is the same as the Master (Control) Clock.
In Store mode, the
pipe clock is the same as the sample clock. Note that the data in both stages
of the pipeline is also present at the 10174 multiplexers, locations 1L and 2L
for diagnostic access.
Pipeline data is also presented to the inputs of both 10176 registers at
locations 6D and 6E which begin two-way memory multiplexing. The registers at
locations 6D and 6E act as pre-memories and are clocked by the rising edge of
signals WE01 and WE02.
They are outputed from the OR gates, location 6J or
schematic sheet 2.
The WE01 and WE02 signals are 180 degrees out of phase,
which causes samples to be stored alternately in the two 10474 (2051), 512x4
RAMs at locations 5B and 5C.
The 10173 demultiplexer at location 5D
demultiplexes the memory.
The data out of 5D goes back to the 10121 input
selectors at location 2D for diagnostic recirculation and to the multiplexers
at location 1L and 2L for MPU access.

Memory Control
The Memory Control logic (sheet 2 of schematic diagram) is implemented by the
100155 Mux Latch at location 6H which keeps track of control signals from the
MPU and Control Board.
This Mux Latch also controls which phase of memory
will be written to, or read from, next through the 01 and 02 signals which
alternately enable the two 100101 gates at location 5J.
When Internal Clock is used, the OLD TRACED signal, output from pin 2 of 6H
combines with the ASYNCH MODE signal from the MPU to form the MEMORY ALIVE
signal which enables pins 5 and 9 of the 100101 gates at location 5J.
When External Sample Clocks are selected, the MEMORY ALIVE signal is derived
from the SYNC MODE MPU control signal and the TRACED signal from the Control
Board.
The outputs of pins 5 and 9 at location 5J are the WE pulses for the
record memories.
The HALTED output signal from Mux Latch at location 6H disables the OR gates
at location 5K.
These gates pass the sample clock and select the source of
the pipe clock.
The OR gates at location 6J distribute all clocks and the WE
signals.
Note that the width of 173 clocks at gate 6J, pin 13 is set by a
difference in propogation delay when the same signal feeds both inputs through
two different paths.

4-2n

MPU Interface
The MPU Interface circuits (sheet 7 of schematic diagram) decode the tlPU
Address Bus through the 10124 TTL to ECL Translator at location 8K. the 74S85
four-bit comparator at location 9M and the associated circuits.
The 10124
translators at locations 6M. 7L. 10L and 9K are also used as TTL to ECL level
translators for the data bus.
These translators feed the inputs of the 10176
Hex D Latches which hold control information from the MPU.
The 10173 Multiplexers at locations 12M and 13M multiplex the lower 8 bits of
Read data to the MPU. The 10125 TTL to ECL level translators at locations 1M.
2M, ~1 and 11M translate TTL logic levels received from the bus to ECL logic
level for data board interface.
CONTROL BOARD OPERATIONS
Overview
This section describes theory of operation for the K450 Control Board
assembly, part number 0114-0120-10.
The Control Board contains all decision
making logic for controlling the recording process.
This includes word recognition circuits. delay counters. and the logic to
combine delay conditions with detected words.
These circuit functions cause
the K450 to stop recording, jump or advance to another level with different
record parameters and selectively enable or disable the recording operation.
The Control Board block diagram is shown in Figure 4-7.
The board assembly
drawing. schematic diagrams. and list of material are provided in Chapter 7.
Reference is made to the schematic diagrams throughout the descriptions for
the following circuit functions:
o

Word Recognition Circuits (Schematic Sheets 1. 2. and 3)

o

Word Selection Circuits (Schematic Sheets 4 and 5)

o

Level Switching Circuit (Schematic Sheet 6)

o

Delay Counter (Schematic Sheet 8)

o

Recording Control Circuits (Schematic Sheet 7)

o

MPU Interface (Schematic Sheet 9)

Word Recognition Circuits
The Word Recognition Circuits are contained on sheets 1. 2 and 3 of schematic
diagrams. Word recognition is accomplished separately for each Input Section.
A. B, and C with the separate words being combined in the word selection
circuits described in subsequent paragraphs.
In the circuit descriptions all
references are made to the Section C Input (schematic sheet 3) which is used
as an example. Sections A and B operate identically to Section C.
The DATA signal supplied from the Q output of the sample registers on the C
Data Board enters the Control Board through the motherboard.
It is
synchronized with the control clock in the 10176 registers at locations 1H,
2H. and 3H.

The data output from these registers is presented to four of the eight address
inputs, and to each of the four 10474 (2051), 256x4 Static RAMs at locations
1G, IF, 3G and 3F. The other four address lines of the RAMs are driven by the
LEVEL X signal, where X is the 4-bit number representing the level of trace
control.
The four data outputs of the 10474 RAMs correspond to the four
combinational functions of the K450 for STOP, JUMP, ADVANCE and TRACE signals
generated by the 100101 OR gates at locations 1D and 3D.
The MPU initializes the RAl1s to contain zeros only at those address locations
and bit positions that correspond to the combinations selected by the user for
STOP, JUMP, ADVANCE and TRACE at each level.

FROM

FROM
DATA
BOARO "A"
LEVEl SEUCTlON BUS

~1
DATA "A"
WORD
DETECllON

(1)>-111

I

I

'>--

I~

FORCE
CONDIT1OH

tl

--

I

GENEAAllOH

I
!"--

'>--

WORD
DETECTIOH

J

10 CLOCK

IOA.RD LEVEl

1--

11

11

11

ADVANCE

JUMP

STOP

SELECT10H

SB.ECT1OH

SELECT10H

PANS. TRACE

-

CONTROl SIGHALI

r---

GENERATlOH

- --f

SELECT10H

-

I
LEVEL SEUCl10H IUS

u

J

DElAY COMllICl

CONTROl
CIACUITS

INC

CLOCK

I

TOAEAR

11»71
--'I

-

1
TRACE

Ie
U

LEVEl
SEI..ECTlOH
-

u

JL UL ~ d

LEVEl SEUCTlON IUS

f--

-

DETiCllON

l[IHt

ADlDoGa_

~tEMORtES

l~

DATA "S"

WORD D£TECT1OH DATA IUS

!"--

CLOCK

DATA

BOAAO"C"'

r-

a

IoIPU DATA IUS III ClM-7I

-::II

FROM

DATA
BOARD"S"

I

T.D

~

DO

IXUf

T cursor is pointing to All Active Boards. If the NEXT Key is pressed,
all of the tests for all of the boards in the Active list are automatically
tested sequentially.
Before each test is executed it is loaded in by DIAG and the message Loading
Diagnostic File, is displayed.
The name of the current Diagnostic module is
displayed at the top and the test names and test steps are updated.
During this automatic testing DIAG displays the number of Passes and Errors at
the bottom of the screen.
If there are any Errors, an Error message
is
displayed at the center of the screen, and the Error count at the bottom of
the screen is incremented. The Pass counter at the bottom of the screen is not
incremented until all tests for all Active boards are performed. Pressing the
STOP key aborts the current test and returns to the Main Menu.

5-4

System Testing is normally performed if an overall picture of the unit's
integrity is desired.
Since all Subtests for all Active boards is performed,
this test is long.

Single Board Testing
If a single board is to be tested, the Test »> cursor is positioned next to
the name of the board and the NEXT key pressed. This method is different from
testing All Active Boards in several ways.
First, the testing is performed only on the chosen board.
Second, the testing is not started automatically.
The Subtest Menu list for
that particular Board is displayed, and either all Subtests are executed, or a
single Subtest can be executed.
Third,

the Pass and Error count is not displayed at the bottom of the screen.

Single Board testing is done when the integrity of a single board or boards is
unknown, and a direct test on the board in question is performed. This method
provides information at a quicker rate than if all the previous boards in the
Active list are tested.
Pressing
Menu.

the

STOP key aborts the current Subtest and returns to the

Subtest

Conducting All Subtests or Individual Subtests
When a single board is selected for testing, the Subtest Menu is displayed. A
single Subtest is performed by positioning the highlighting cursor, using the
UP or DOWN ARROW keys, over the desired test and pressing the NEXT key. The
single Subtest runs, and then returns to the Subtest Menu. If the parameter
selection for NUMBER TO REPEAT TESTS is greater than 1, the particular Subtest
is repeated that number of times.
Selecting ALL SUBTESTS executes all of the tests in the Menu sequentially, and
returns to the Subtest Menu when complete.
Pressing the STOP key aborts the current subtest and returns to
menu. Pressing the PREVIOUS key restores the Main Menu.

the

Subtest

DIAGNOSTIC PARAMETERS (EDIT KEY)
General
There are a number of options or parameters available for execution of the
Diagnostic modules. These parameters control the program flow of execution.
The parameters are displayed and/or changed at any time by pressing the EDIT
key.
This displays the list of parameters, and the current selections. Once
the parameter options are selected, pressing the PREVIOUS key return to the
previous ~1enu Display or program execution.
The parameters are changed by
positioning the highlighting cursor next to the desired parameter and pressing
the NEXT key.
This selects the opposite of the currently displayed option,
(YES changes to NO). This method is valid for all parameters except the Times
to Repeat Test.

5-5

The parameters are as follows:
Parameter

Options

1•

Halt on Error

No, Yes

(default is No)

2.

Loop on Error

No, Yes

(default is No)

3.

Display Error Messages

Yes, No

(default is Yes)

4.

Times to Repeat Test(s)

1 - 65535

(default is 1)

5.

Test Floppy Disk Drive A

No, Yes

(default is No)

6.

Test Floppy Disk Drive

Yes, No

(default is Yes)

7.

Test Side 0 of Drive(s)

Yes, No

(default is Yes)

8.

Test Side 1 of Drive(s)

Yes, No

(default is Yes)

9.

Run Operator Action Tests

No, Yes

(default is No)

B

Halt on Error
The first parameter, Halt on Error, specifies that if an Error
execution of the Diagnostic, the Diagnostic temporarily halts
message remains on the screen. A HALTED ON ERROR message blinks
to verify that the Diagnostic is halted.
Diagnostic execution
pressing the NEXT key. If another error occurs, DIAG halts
key is pressed.

occurs during
and the Error
on the screen
is resumed by
until the NEXT

Normally when there is an Error, and the Halt on Error parameter is not
selected, the Error message is displayed on the screen for about a second.
This does not allow adequate time to read all of the information displayed, so
Halt on Error is useful for single stepping through the Errors that occur.
The disadvantage of Halt on Error is that when an Error occurs, all testing is
suspended, and the NEXT key must be entered to resume. In the case where you
want a unit to run the Diagnostics for a period of time without the need of
operator actions, and then later check on the number of Passes and Errors,
Halt on Error should be disabled by setting the option to NO.
Loop on Error
Loop on Error specifies that if during the execution of the Diagnostic an
Error occurs, the Diagnostic loops on the test step that found an Error. This
test step is repeated continuously even if it occasionally Passes.
The Loop on Error option is useful for debugging a board.
For example, a
board is intermittently failing, the continuous looping allows the operator to
trigger on a Write pulse, a Read pulse or a Clock.
The looping continues until either the CONTROL key is pressed, or the Loop on
Error option is disabled by pressing the EDIT key, and changing the selection
to NO.

5-6

NOTE: The CONTROL key is
used during the process of Looping on Error.
Pressing the CONTROL key skips out of the current Test Step and proceed. to
the next Test Step. It provides a means to quickly abort a Test Step without
changing the Loop on Error Parameter.
NOTE: The Loop on Error option has one characteristic that is confusing. For
example, the option is enabled and an Error occurs, the Error message is
displayed as usual, and the test is repeated. But, the Error message is only
displayed for about a second, so if the test starts Passing, the Diagnostic
may appear to hang since no messages are displayed and the Test Step number
remains constant. The Diagnostic is not hung up, it is in fact repeating the
same Test Step without Error. Pressing the CONTROL key, or disabling the Loop
on Error Parameter allows the Diagnostic execution to proceed.
Display Error Messages
This parameter controls whether or not the Error messages are displayed
Errors occur.

when

Normally when an Error occurs, and this option is set to YES, a message
describing the Error is displayed for about a second, then the message is
cleared. For most testing situations this is the desired response.
If a test is running that is rather lengthy, such as a RAM addressing test,
and there are many Errors, the screen displays many Error messages. Each time
a message is displayed the Diagnostic is paused, and this increases the Total
Test Time.
If the Display Error Messages is set to NO, this decreases the
Total Test Time.
If the unit is to be run unattended (it is not necessary to view every Error
message and the maximum number of test cycles desired), this parameter should
be set to NO. The total number of Errors can be displayed at a later time by
pressing the DATA key.
NOT!: When the Display Error Messages is set to NO, the Diagnostic module that
is currently executing still calls the Error tabulation routine, 10 every
Error is counted and tabulated.
Number of Times to Repeat Teat(a)
This parameter controls the number of times a test is performed. The default
is 1. This means when the test or tests are started by pressing the NEXT key,
testing is executed one time and the Diagnostic will pause.
If several test repeats or continuous testing is desired, any number from 1 to
65,535 is selected.
Enter this parameter by positioning the cursor, pressing
the NEXT key, entering a number with 1 to 5 digits, and again pressing the
NEXT key. (If 5 digits are entered, the terminating NEXT key need not be
pressed.) For example, if the count desired is 158, press NEXT, 1, 5, 8,
NEXT. If a number larger than 65,535 is entered, the program will requests to
re-enter the number.
NOTE: If the repeat count is more than one, DIAG cycles through all Subtests
of all Active boards and then repeat the cycle until the repeat count i.
reached.

5-7

At any time during this execution, the DATA key is pressed to view the
Pass/Error history then the PREVIOUS key resumes execution.
The EDIT key may
also be pressed to change any of the parameters. The PREVIOUS key resumes
execution.

Teat Drive A, Test Drive B
This parameter refers to the Floppy Disk Drive tests for Disk Drives A and B.
If a Drive is selected, a Disk Write/Read test is performed on that Drive, and
a scratch Disk must be used since all data on that Disk is destroyed.
The default selections are Drive A = NO, Drive B = YES. The Diagnostic Disk is
residing in Disk Drive A, and a scratch Disk should be residing in Disk Drive
B. With the default selections, no operator actions are required. Drive B is
tested, and Drive A is not tested.
If both
Drive A
A, the
Drive.
and the

Disk Drives are to be tested, the parameter options must be changed to
and Drive B = YES. Each time DIAG is ready to test Disk Drive
Diagnostic Disk must be removed, and a scratch Disk placed in the
When the test is complete, the scratch Disk is removed from Drive A,
Diagnostic Disk re-inserted.

= YES,

This procedure requires actions to be performed by the operator,
OPERATOR ACTIONS parameter must be enabled.

and the

RUN

NOTE: A scratch Disk is defined as a new or fairly new Floppy Diskette, that
is formatted using the K450 Disk Operating System Format command.
The Write
Protect slot must not be covered.
The Disk used should not contain any
important data or programs,
since the process of Formatting and the Disk
Drive testing destroys all data on the Diskette.
Test Side 0, Test Side 1
This parameter also refers to the Floppy Disk Drives testing. Each Disk Drive
has two sides, Side 0 and Side 1.
Normally parameters 7" and 8 are YES, and
both sides are tested during the Floppy Disk testing.
For example, Disk Drive B is having Errors on Side 1, and no Errors on Side 0,
setting the TEST SIDE 0 option to NO allows for more frequent testing of Side
1 of the Disk Drive, and give more Pass/Fail information at a quicker rate.

Run Operator Action Tests
Some of the tests in the Diagnostic modules require the operator to perform
certain actions.
One example is the testing of Disk Drive A requires the
operator to remove the Diagnostic Disk and insert a scratch Disk, allows the
test to run, then re-inserts the Diagnostic Disk.
Other actions might be the installation of RS-232 wrap-back connectors, the
testing of the Keys on the K450 Keyboard, GPIB Testing, etc. If a unit is to
run the Diagnostics unattended, this parameter should be set to NO, and the
specific tests that require operator actions are not performed.

PASS/ERROR TABLUATION (DATA KEY)
At anytime during the Diagnostic Execution the number of Passes and Errors can
be displayed by pressing the DATA key.

Pressing the PREVIOUS key returns to the previous i1enu or executions. A list
of the boards in the system is displayed, as well as the total number of
Errors as follows:
Number of Errors
Cycle Through All Tests
Keybd/Display

0

Data Board A

0

Data Board B

0

Data Board C

0

Control Board

0

Clock Board

0

Threshold Board

0

Storage Controller Board

0

There are two fields that are highlighted by the cursor, they are Errors and
Cycle Through All Tests. If the cursor is over Errors, pressing the NEXT key
changes the display to the number of Passes, (changing Errors to Passes).
Pressing the NEXT key again changes back to the Error display.
This Errors/Passes display shows the total accumulative Errors and Passes
each board in the K450 System. If a board is not in the system, or it
forced Inactive, the Pass and Error count is 0 for that board. Otherwise,
number of times DIAG tested the board is displayed for the Passes, and
total number, (if any), of Errors is displayed.

for
was
the
the

If the DOWN ARROW key is entered, this moves the cursor into the Cycle Through
All Tests field.
Pressing the NEXT key displays the total Errors/Passes for
each Subtest of the Keyboard/Display Board. Pressing the NEXT key displays the
total Errors/Passes for each Subtest of Data Board A.
Pressing the NEXT key displays the Data Board B, Data Board C, Control Board,
Clock Board, Threshold Board, Storage Controller Board, and then finally back
to the Board Level Error/Pass Display.
To view information about Data Board A, do the following steps:
1.

Press

the DATA key to display the Board list and total Error count.

2.

Press

the

3.

Press the DOWN ARROW key. Press
Data Board A Subtest Pass count.

4.

Press the UP ARROW key and then the NEXT key to display
Board A Subtest Error count.

5.

Press the PREVIOUS key to return to the previous Menu.

NEXT key to display the Board list and total Pass count.

c:

n

the

NEXT key twice to display the
the

Data

DIAGNOSTIC RE-INITIALIZATION AND DIAGNOSTIC EXIT TO SYSTEM
General
When the Diagnostic Modules are executed, the Pass/Fail information
accumulated. Pressing the DATA key displays this information.

is

If a fresh start of the Diagnostic is desired, with the Pass/Error information
set to 0, press the PREVIOUS key twice. This sets up the default Parameters,
and sets all Pass/Error information to O.
NOTE: Be careful using the PREVIOUS key while in Main Menu, it iseasy to reinitialize the Diagnostic by accident, and lose all the Pass/Error information
that was accumulated.
Exiting the Diagnostic
When the K450 Logic Analyzer is powered on,
Diagnostics and comes up in the Default Menu.
F2 key, the power on diagnostics are repeated.

it goes through its
While in this menu,

power on
press the

While the K450 Diagnostic Operating System is under Execution, it is possible
to exit back to the Default Menu of the Logic Analyzer.
This is done by
pressing the F2 key three times. This causes any Diagnostic execution to be
aborted, and the K450 goes through the power on diagnostics and come up in the
Default Menu.
Pressing the F2 key three times has the same effect as powering off the K450,
and then powering it back on, without the need to remove the Floppy Diskettes.

NOTII The '2 key must be pressed three times to avoid an accidental exit from
the Diagnostic Operating System.
keys voids out the exit.

Any other keys pressed between the three

'2

SUMMARY OF K450 DIAGNOSTIC OPERATING SYSTEM KEYS
The K450 Diagnostic recognizes the following keys:
Key

Menu or Execution

Function

NEXT

Main Menu
Subtest Menu
HALTED ON ERROR
Parameter Menu
Pass/Error Display

Execute Diagnostic.
Execute Diagnostic.
Resume Diagnostic execution.
Change selected option.
Change Error display to Pass
display, Cycle through Subtest
lists.

PREVIOUS

Uain Menu
Subtest Menu
Parameter Menu
Pass/Error Display

Re-initialize Diagnostic.
Return to Main Menu.
Return to previous Menu/execution.
Return to previous Menu/execution.

EDIT

Any Menu or execution

Display the Parameter options.

DATA
STOP

Any Menu or execution
Any execution

Display the Pass/Error data.
Abort current test.

5-10

ARROWS

HALTED ON ERROR

Abort current test.

Main Menu

Activate/Inactivate a Board, or
Select a Board for testing.
Select a Single Test or all Tests.
Select a parameter.
Change fields for Errors/Passes,
or cycle through Subtest lists.

Subtest Menu
Parameter Henu
Pass/Error Display
CONTROL

Looping on Error

Skip out of current Subtest and
proceed to the next Subtest.

F2

Any Uenu or execution

Three consecutive key-strokes
causes an EXIT from the
Diagnostics and cold starts the
K450 Logic Analyzer.

K450 KEYBOARD/DISPLAY BOARD DIAGNOSTIC
DIAGNOSTIC OVERVIEW
This section describes subtests that are executed on the K450 keyboard/
display board, how error reporting is done, and the concept behind each
subtest program.
There are eight subtests written for the keyboard/ display board. Each of the
subtests are described individually on the pages which follow. Loop on error,
error count, and pass count update are incorporated into each subtest. Details
for selecting the various test options and parameters for controlling the
diagnostic monitor are described in the Introduction for Chapter 5.
All

">"

Error Messages are preceded by a
prefix.

"*".

All Information Messages use

the

Early exit of each subtest is accomplished by pressing the "STOP" key.
ASSUMPTIONS
This series of tests assumes that the following boards are installed and
operational:
1. HPU

2. Threshold/GPIB/RS-232
3. Clock
4. Control
SUBTEST CATEGORIES
1.

2.
3.

4.
5.
6.

7.
8.

Keyboard Test
Interrupt Controller (8259) Test
Clock/Calendar (5832) Test
Video RAM Data Test
Video RAM Address Test
6116 RAM Data Test
6116 RAM Address Test
Beeper Exercise
ERROR COUNT CATEGORIES

1.

2.
3.

4.
5.
6.
7.
8.

Subtest
Subtest
Subtest
Subtest
Subtest
Subtest
Subtest
Subtest

1 Error Count
2 Error Count
3 Error Count
4 Error Count
5 Error Count
6 Error Count
7 Error Count
8 Error Count

5-12

are

Keyboard/Display Diagnostic Subtest 1
KEYBOARD TEST

TITLE:

TARGET LOGIC:

8E, 14E, 13E, 10E and keyboard interface matrix

PURPOSE: The keyboard logic is functionally tested by pressing a specified
key on the front panel, reading the corresponding I/O port from buffer (lOE),
and then verifying the key data to the expected data.
TEST DESCRIPTION: There are 48 keys on the front panel; the corresponding
I/O Port, lxh are arranged as follows:
a.
b.
c.
d.
e.
f.
h.
i.
There

if
if
if
if
if
if
if
if

key
key
key
key
key
key
key
key

is
is
is
is
is
is
is
is

located
located
located
located
located
located
located
located

at
at
at
at
at
at
at
at

column
column
column
column
column
column
column
column

1
2
3
4
5

6
7
8

in
in
in
in
in
in
in
in

the
the
the
the
the
the
the
the

front
front
front
front
front
front
front
front

panel
panel
panel
panel
panel
panel
panel
panel.

are 6 key data read from the buffer (10e) ,they are arranged as follows:

a.
b.
c.
d.
e.
f.
The

x=O
x=2
x=4
x=6
x=8
x=a
x=c
x=e

the
the
the
the
the
the

key
key
key
key
key
key

following

data
data
data
data
data
data

read=feh
read=fdh
read=fbh
read=f7h
read=efh
read=dfh

information

if
if
if
if
if
if

the
the
the
the
the
the

key
key
key
key
key
key

message

is
is
is
is
is
is

is

located
located
located
located
located
located

at
at
at
at
at
at

row
row
row
row
row
row

in
in
in
in
5 in
6 in
1
2
3
4

the
the
the
the
the
the

front
front
front
front
front
front

panel
panel
panel
panel
panel
panel

displayed before each key is tested:

)Press key labeled: ?????????????
Where ????????????? could be 1 character, for example, "0" through "9",
a" through "f", or up to 13 characters, for example, "TRACE CONTROL"
in the domain of 48 defined keys.
TEST STEP INFORMATION:
Test Step
1
2
3
4

Key Tested

6
7
8

NEXT
PREVIOUS
FORMAT
CLOCKS
TRACE CONTROL
ARM MODE
UP ARROW
LEFT ARROW

9

MEM A

10

DATA
TIMING

5

11

1: __ 1 'l

Test Step

12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48

Key Tested (cont'd)
GRAPH
RIGHT ARROW
DOWN ARROW
MEU B
A-)B
SEARCH
COMPARE
CONTROL
REF
C
8
4
0
SHIFT
HELP
D

9
5
1
I/O

"X"
E
A

6
2
EDIT
INS
F

B

7
3
ARl1

STOP
F1
F2
F3
F4

ERROR MESSAGE:
If a key data error occurs, the following message is displayec:
*Test FAILED--Test Step
ss
Keyboard Error
Expected Keycode
= eeh
Keycode Found
ddh
Key Data Code Read = "?????????????"
where ss should be 1 through 48
ee should be 1 through 48
dd should be be 1 through 48
')-14

Keyboard/Display Diagnostic Subtest 2
INTERRUPT CONTROLLER TEST

TITLE:

PURPOSE:
The interrupt logic is functionally tested by selecting each
interrupt on the 8259 controller and causing each interrupt to occur. As each
interrupt is generated, the 8259 receives the interrupt then outputs a vector
for the 8086 processor.
At these vectors are routines which set diagnostic
flags.
These flags are examined to determine if the interrupt actually took
place.
The source of the interrupts are then turned off, and the flags are
cleared.
After a small amount of time the flags are re-examined to determine
if the source of the interrupt has actually been disabled. If a flag is found
to be set then an error message is displayed.
TARGET LOGIC:

4E, 2E, 8E, 10E, 90, and 100

TEST DESCRIPTION: The

following table indicates the interrupt source and line
for the diagnostic test step:

TEST STEP INFORMATION:
Test Step
1
2
3
4

5
6
7

Interrupt from

On Board

Threshold
GPIB
Threshold
RS-232
Threshold
AUX
Clock
Total trace
time clock
(timer "0)
(Simulated from software)
Display
Time of day
Storage
Disk
Controller

Interrupt Line
intr
intr
intr
intr

1

2
3
4

not currently assigned
intr 6
intr 7

ERROR MESSAGE:

If an error occurs, the following messages are displayed:
*Test FAILED--Test Step
Intr Oz Not Generated.
where z

z

=1- 7

*Test FAILED--Test Step
z
Unexpected Interrupt Oz Generated.
where z = 1 - 7

5-15

Keyboard/Display Diagnostic Subtest 3
CLOCK/CALENDAR TEST

TITLE:

PURPOSE: This subtest verifies operation of the 5832 clock/calendar by saving
the current time, then exercising the component by setting the time. The time
is then read back and verified. If test is successful, it indicates the 5832
is operating properly.
The time is set so the next second time interval causes a rollover.
An
example of a rollover is if the minutes counter was set to 59.
When minutes
are advanced then the minutes counter becomes zero and the hours count is
incremented by one.
This rollover process continues until the years counter
rolls over to 00 (from 99).
TARGET LOGIC:

2D, 2E, 3D, 4D, 5D and 7D

TEST DESCRIPTION:
Operations are exercised on the clock calendar components
according to the following table:
TEST STEP INFORMATION:
Test Step

Operation

l---------------Read current time, save for last step
2 ------------- Set clock to: Jan. 1, 1900 @OO:OO:OO
Using test feature on 5832 simulate
60 seconds.
Read time:
Compare to:

Jan. 1, 1900 @00:01:00

3 ------------- Set clock to: Jan. 1, 1900 @00:59:00
Using test feature on 5832 simulate
60 seconds.
Read time:
Compare to:

Jan. 1, 1900 @01:00:00

4 ------------- Set clock to: Jan. 1, 1900 @23:59:00
Using test feature on 5832 simulate
60 seconds.
Read time:
Compare to:

5-16

Jan. 2, 1900 @OO:OO:OO

Test Step

Operation (cont'd)

5 ------------- Set clock to: Jan. 31, 1900 @23:59:00
Using test feature on 5832 simulate
60 seconds.
Read time:
Compare to:

Feb. 1, 1900 @OO:OO:OO

6 ------------- Set clock to: Dec. 31, 1900 @23:59:00
Using test feature on 5832 simulate
60 seconds.
Read time:
Compare to:

Jan. 1, 1901 @OO:OO:OO

7 ------------- Set clock to: Dec. 31, 1999 @23:59:00
Using test feature on 5832 simulate
60 seconds.
Read time:
Compare to:

Jan. 1, 1900 @OO:OO:OO

NOTE: Exiting this test via the STOP key restores the time saved in step
If power is removed during steps 2 - 7, the time is lost.

1.

ERROR MESSAGE:

If the time read does not match the time expected, the following error message
is displayed:
*Test FAILED--Test Step
Clock/Calendar Error
year month day hour
Expected: aaa bbb
ccc ddd
Read: ggg hhh
iii j j j
where aaa,
bbb,
ccc,
ddd,
eee,
fff,

ggg - 000 hhh = 001 iii = 001 j j j = 000 kkk = 000 111 = 000 -

x
minute
eee
kkk

999
012
031
023
059
059

5-17

second
fff
III

X.yboard/Dlsplay DIagnostic Subtest 4
VIDEO RAM DATA TEST

TITLE:

PURPOSE: This subtest verifies that the Keyboard/Display Board
prevent normal operation of the MPU RAH dedicated to video display.
TARGET LOGIC:

does

not

7A t 7B t 7C t 8A t 8B, 8C, 9A, 9B., 9C, lOA and lOB
dedicated RAl'1 on UPU Board used for video

TEST DESCRIPTION:
Although the RM1 under test is on the MPU Board, the
Display Board uses this memory to create an image sent to the screen. Various
data patterns are written to the MPU memory and read back.
The data written
is compared to the data read and if a miscompare is detected an error message
is displayed. This continues until all the data patterns listed below have
been tried.
TEST STEP INFORMATION:
Test Step

Value Written
OOH

1
2
3

AAH

55H
CCH
33H
01H
02H
04H
08H
10H
20H
40H
80H

4

5
6

7
8
9

10
11
12
13
NOTE:

This memory physically starts at location 0100h

ERROR MESSAGE:
If

an

error

occurs

during this subtest the following message is displayed:

* Test FAILED--Test step
RAH Data Error
Value Written = aaH
= bbH
Value Read
ccccH
Address Count
where

xx

aa - 00 - FF
bb - 00 - FF
cccc - 0000 - 3FFF

5-18

Keyboard/Display Diagnostic Suhtest 5
VIDEO RAM ADDRESS TEST

TITLE:

PURPOSE:
. This subtest verifies that the Keyboard/Display Board
prevent normal operation of the MPU RAM dedicated to video display.
TARGET LOGIC:

does

not

7A., 7B., 7C., 8A., 8B., 8C., 9A, 9B., 9C., lOA and lOB
RAM located on MPU Board used for video,

TEST DESCRIPTION: All of the RAM in this test is preset to zero then the
indicated address is written with the value Oaah. All of the RAM is then read
to verify that the indicated address is the only data element that was set to
Oaah.

TEST STEP INFORMATION:
Test Step

OOOOH
0001H
0002H
0004H
0008H
0010H
0020H
0040H
0080H
0100H
0200H
0400H

1
2
3
4
5
6
7
8
9

10
11

12
NOTE:

Indicated Address

This memory physically starts at location 0100h

ERROR MESSAGE:

If

an

error

occurs during this subtest, the following message is displayed:

* Test

FAILED--Test Step

xx

RAM Data Error

Value Written = aah
Value Read
= bbh
Address Count - cccch
where

aa
00 - ff
bb
00 - ff
cccc = 0000 - 3fff
::II

5-19

Keyboard/Display Diagnostic Subtest 6
6116 RAM DATA TEST

TITLE:

PURPOSE: This subtest verifies operation and integrity of the 6116 RAMs on the
keyboard/display board by writing to the memory several different data
patterns.
This memory is then read back and compared to the value written.
If a miscompare occurs then an error message is displayed. This process is
repeated for all of the 6116 memory until all the patterns listed below have
been tried.
TARGET LOGIC:

1B, 3B, 3C, 4C, 5B, 6B, 5E, 6E, 5C and 6D

TEST DESCRIPTION: The following is a summary of the data written to RN1 during
each test step:
TEST STEP INFORMATION:
Test Step

Value Written

1

OOH

2
3

AAH

55H
CCH
33H
01R
02H
04H
08H
10H
20H
40H
80H

4
5
6

7
8
9
10
11
12
13
NOTE:

This memory physically starts at location 040000h

ERROR MESSAGE:
If

an

error

occurs during this subtest, the following message is displayed:

* Test

FAILED--Test Step

xx

RAM Data Error

Value Written = aaH
Value Read
= bbH
Address Count = ccccH
where

aa = 00 - FF
bb = 00 - FF
cccc = 0000 - 3FFF

5-20

Keyboard/Display Diagnostic Subtest 7
6116 RAM ADDRESS TEST

TITLE:

PURPOSE: This subtest verfies the operation and integrity of the 6116 RAMs on
the keyboard/display board. All of the RAM in this test is preset to zero then
the indicated address is written with the value Oaah. All of RAM is then read
to verify that the indicated address is the only data element that was set to
Oaah.
TARGET LOGIC:

1B, 3B, 3C, 4C, 5B, 6B, 5E, 6E, 5C and 6D

TEST DESCRIPTION: All RAM is preset to zero, then the indicated address is
written with the value Oaah. All of RAM is read to verify the written data.
TEST STEP INFORMATION:
Test Step

Indicated Address

1
2
3
4
5
6

OOOOH
000lH
0002H
0004H
0008H
0010H
0020H
0040H

7

B
9

OOBOH

10
11
12

0100H
0200H
0400H

NOTE:

This memory physically starts at location 040000h

ERROR MESSAGE:
If

an

error

*

occurs during this subtest, the following message is displayed:

Test FAILED--Test step

xx

RAM Data Error

Value Written - aaH
= bbH
Value Read
Address Count = ccccH
where

aa
bb
cccc

= 00
= 00

- FF
- FF
0000 - 3FFF

5-21

Keyboard/Display Diagnostic Subtest 8

TITLE:

BEEPER EXERCISE TEST

PURPOSE: This subtest exercises the beeper circuitry. There are
messages generated by this routine as there is no way to verify
except via audio monitoring.
TARGET LOGIC:

no error
operation

15E, 16E, 17E and 18E

TEST

DESCRIPTION: The beeper is activated by loading pO-p3 on IC with the
duration value, then the line labeled cp is pulsed. The beeper is set to
various durations as given in the following table:

TEST STEP INFORMATION:
Test Step

Duration

1

.1 sec

25

1.5 sec

ERROR MESSAGE:
There are no error messages for this subtest.
Also note that since no errors
are possible, "loop on error" and "halt on error" do not function.

5-22

K450 DATA BOARD DIAGNOSTIC

DIAGNOSTIC OVERVIEW
This section describes subtests that are performed
Diagnostic. The target hardware is presented, as well
of each subtest, a list of information for each test
of Error Messages that may be printed for the subtest

by the K450 Data Board
as a general description
step, and a description
results.

The K450 Data Board Diagnostic is a board level test of the board operations
that run under the K450 Diagnostic Operating System. The diagnostic can test
from 1 to 3 Data Boards in the system. These correspond to Data Boards A, B
and C. In order for the Diagnostic to run properly, the board under test must
be installed on the Mother Board, (not on an extender card). The internal
probe input cables must be connected to Jl and J2, and the external probes
installed. All of the channels of all probes must be free from connection to
anything (they must be allowed to float). Also, all of the other boards must
be installed in the K450 system.
NOTE: The internal probe input cables are too short for the board to be
installed on an extender card. If extension cables are used, then an extender
card may be used.
Several of the subtests use a sequence of 24 Data patterns to write, read and
verify an I/O port or Memory Address. These Data patterns verify that all 16
Data Bits are functional and completely independent of each other. These 24
Data patterns are as follows:
OOOOH, 5555H, AAAAH, CCCCH, 3333H, 6666H, 9999H, FFFFH,
OOOlH, 0002H, 0004H, 0008R, OOlOR, 0020R, 0040R, 0080R,
OlOOH, 0200H, 0400H, 0800R, 1000R, 2000R, 4000R, 8000R.
When writing these Data patterns to an I/O port such as the Sample Register or
the Pipeline Registers, the Data value can be randomly accessed. The ECL RAM
Memory is a 2048 byte FIFO. All 2048 locations are accessed at the same I/O
address, (OC6H for writes, and OCOH for reads). The RAM's addressing is
accomplished by sequential reads from, or writes to the RAM. Address counters
on the board are incremented each time a RAM access (a Sample Clock) occurs.
The

RAM actually requires 2051 Sample clocks to get 2048 words of data to the

RAM. The three extra clocks are required to get the Data through the pipeline.
After the 2048th clock, the 2048th Data value resides in the Sample Register.
One more clock shifts it to the New Pipe Register. An additional clock shifts
it to the Old Pipe Register, and the last clock writes it to RAM.
NOTE: When an I/O address is specified for explanation, the addresses for Data
Board A are used. These addresses would only apply if Data Board A was beinl
tested. Data Board B addresses are ODxH, and Data Board Care OExH.

5-23

SUBTEST CATAGORIES
There are thirteen Subtests that are performed by the Data Board
These are categorized as follows:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.

Diagnostic.

Force Conditions Test
Data Path Test
Clocking Disable Test
Latch Bits 0-7 Test
Latch Bits 8-F Test
Glitch Bits 0-7 Test
Glitch Bits 8-F Test
Multiplex Select Test
Pipeline Shift Test
RAM Data Integrity
RAM Addr Integrity
Trace Conditions Test
Recirculate RAM Test

ERROR COUNT CATEGORIES
The Error Count Display information is a one for one match with the Subtest
list above. The K450 Diagnostic Operating System will display the "Subtest n"
instead of the actual test name.
Subtest
Subtest
Subtest
Subtest
Subtest
Subtest
Subtest
Subtest
Subtest
Subtest
Subtest
Subtest
Subtest

1
2
3
4
5

6
7
8
9
10
11
12
13

(Force Conditions Test)
(Data Path Test)
(Clocking Disable Test)
(Latch Bits 0-7 Test)
(Latch Bits 8-F Test)
(Glitch Bits 0-7 Test)
(Glitch Bits 8-F Test)
(Multiplex Select Test)
(Pipeline Shift Test)
(RAM Data Integrity)
(RAM Addr Integrity)
(Trace Conditions Test)
(Recirculate RAM Test)

5-24

Data Board Diagnostic Subtest 1
FORCE CONDITIONS TEST

TITLE:
TARGET LOGIC:

6H
6rt 7L 10L

8K 7K
1M 2M
7K 9M

9K 7F SF 8F 9H 6L
9M 8L 12M 13M
3M 11M 8K
8L 8M 10M

TEST DESCRIPTION:
This subtest writes various commands to the Data Board and expects certain
status values to exist. The commands are written to ports OC2H and OC4H. The
status is read back from port OC8H.
This test does not require any boards other than the MPU to be installed
the system. Specifically, it requires no clocking from the Clock Board.

TEST STEP INFORMATION:
Step
1
2
3
4

Status Expected
45H
65H
75H
F5H

ERROR MESSAGES:
If an error occurs, the following message is displayed:

* Test FAILED--Test Step ssss
hmsg
I/O Address
= aaaaH
= rrrrH
Data Read
Data Expected
= eeeeH
= OOOOOOOOOOOOOOOOB
Error Bit Map
Board Status X8 = iiiiH
Where:
ssss is the test step number in the range of 1 to 4.
hmsg

is the Error heading message:
Not Halt, Mem full, ExpWrlow 02 Error
Multiphase Mode Clear Error
Async Mode Clear Error
Freeze Memory Clear Error

aaaa

is the I/O address of the Data Board:
OC8H for Data Board A Status Register,
OD8H for Data Board B Status Register,
OE8n for Data Board C Status Register.
5-25

in

rrrr

is the Data Word read from the Data Board.

eeee

is the Data Word Expected from the Data Board.

iiii

is the Status information from the current Data Board under test.

NOTE: The Error Bit Map is a map of the Data Bus, DO - DIS, and i8 an
exclusive Or of the Data Read and the Data Expected. Any bits that are
different show up as a "1". Bits that show up as a "0" passed the compare.

5-26

Data Board Diagnostic Subtest 2

TITLE:

DATA PATH TEST

TARGET LOGIC:

6M 7L 10L 9K 6F 5H 9F
2D 1D 2C 1C 4D 3C 4C 3D
lID 10D 11C 10C 13D 12C
2H 1H 4H 3H 11H 10H 13H
2J 1J 4J 3J 11J 10J 13J
8K 7K 9H 8L 5K 6J
10K IlL 12L 13L
13M 12M 1M 2M 3M 11M 8M

13C 12D
12H
12J
10M

TEST DESCRIPTION:
This subtest checks the Data Bus path of the Data Board for functionality and
Data Bit uniqueness.
Data is transferred by sending output to the Diagnostic
Latch at I/O address OC6H, issuing a Sample Clock, receiving input from the
Sample Register at I/O address OC6H, and comparing Data. Since the Glitch Mode
and Latch Mode are both disabled, the Data will slip through to the Sample
Registers without the need for a Latch Clock.
The Clock Board is required to run this test. The "Sample Clock", PI-42 is
used to clock the data to the Sample Register. This is achieved by doing a
"KICK$CLOCK" , which writes a "1" to Data bit DO of Write Register 8, (OB8H),
of the Clock Board.
The majority of the subsequent subtests use this Data
Path to exercise various features and functions of the Data Board. So if there
are any errors in this test, there are bound to be many failures that follow.

TEST STEP INFORMATION:
Step

Data

Data Written to

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

OOOOH
5555H

OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6R,
OC6H,
OC6R,
OC6H,
OC6H,
OC6H,
OC6H,
OC6R,

AAAAH

CCCCH
3333H
6666H
9999H
FFFFH
0001H
0002H
0004H
0008H
0010H
0020H
0040H
0080H
0100R
0200R
0400R
0800H
1000R
2000R
4000H
BOOOH

Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic

Data Verified at
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch

5-27

OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6R,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6R,
OC6R,
OC6H,
OC6H,
OC6H,
OC6R,
OC6H,
OC6H,
OC6R,
OC6H,
OC6H,

Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample

Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register

ElUlOR. MESSAGES:

If an error occurs, the following message is displayed:

* Test FAILED--Test Step ssss
Data Path Diag to Sample Reg Error
I/O Address
= aaaaH
Data Read
rrrrH
Data Expected
= eeeeH
Error Bit Map
= OOOOOOOOOOOOOOOOB
Board Status X8
iiiiH
Where:
ssss

is the test step number in the range of 1 to 24.

aaaa

is the I/O address of the Data Board:
OC6H for Data Board A Sample Register,
OD6H for Data Board B Sample Register,
OE6H for Data Board C Sample Register.

rrrr

is the Data Word read from the Data Board.

eeee

is the Data Word Expected from the Data Board.

iiii

is the Status information from the current Data Board under test.

NOTE: The Error Bit Map is a map of the Data Bus, DO - DIS, and is an
exclusive OR of the Data Read and the Data Expected. Any bits that are
different show up as a "1". Bits that show up as a "0" passed the compare.

5-28

Data Board Diagnostic Subtest 3
CLOCK DISABLE TEST

TITLE:

TARGET LOGIC:

5K 8J 6J 5L
6H SA 6A 8A 9A
All Logic listed in Subtest 2

TEST DESCRIPTION:
This subtest checks the different ways of clocking the Data Board,
different ways of disabling the clocking.

and

the

In Single Phase Mode the Sample Clock, Pl-42 is used for all clocking on the
Data Board. If the Multiphase Mode is selected, the Sample Clock, Pl-42 is
used for the Sample Register, and the Control Clock, Pl-46 is used for the
RA}1, Pipelines and Address Counters.
A Condition called Force Clocks causes all Sample Clocks and all Control
Clocks to be ignored. Also a condition called Halted disables these clocks.
This test also checks the Address Reset-Memory Full function. The address
counters are reset by toggling W4B12. The Memory is filled by clocking the
address counters 2048 times.

TEST STEP INFORMATION:
Step

Mode of Phase

Force Clocks

Single Phase
Multi Phase
Single Phase
Multi Phase

inactive
inactive
active
active

"HALTED/"

MEMORYFULL

Status

high
low

low
high

OOOlH
0004H

Step

Mode of Phase

Force Clocks

Halt When Full

Data Expected

7

Single Phase

inactive

active

OOOOH

1

2
3

4
Step
5
6

Data Expected
5555H
AAAAH

OOOOH
OOOOH

5-29

ERROR MESSAGES:
If an error occurs, the following message is displayed:

* Test FAILED--Test Step ssss
hmsg
aaaaH
I/O Address
rrrrH
Data Read
Data Expected
eeeeH
Error Bit Map
OOOOOOOOOOOOOOOOB
Board Status X8
iiiiH
Where:
ssss

is the test step number in the range of 1 to 7.

hmsg

is the Error heading message:
Force Clocks Enable Data move Error,
Force Clocks Disable Data move Error,
155 En2 Memory Not Full Status Error,
155 En2 Mem-Full/Halt Status Error,
Halt Freeze Sample Register Error.

aaaa

is the I/O address of the Data Board:
OC6H
OC8H
OD6H
OD8H
OE6H
OE8H

for
for
for
for
for
for

Data
Data
Data
Data
Data
Data

Board
Board
Board
Board
Board
Board

A
A
B
B
C
C

Sample
Status
Sample
Status
Sample
Status

Register,
Register,
Register,
Register,
Register,
Register.

rrrr

is the Data Word read from the Data Board.

eeee

is the Data Word Expected from the Data Board.

iiii

is the Status information from the current Data Board under test.

NOTE: The Error Bit Map is a map of the Data Bus, DO - D15, and is an
exclusive OR of the Data Read and the Data Expected. Any bits that are
different show up as a "1". Bits that show up as a "0" passed the compare.

5-30

Data Board Diagnostic Subtest 4

TITLE:

LATCH DATA BITS 0-7 TEST

TARGET LOGIC:

SF
5L
2H IH 4H 3H IIH 10H 13H 12H
Diagnostic Latch Clock

PI-44 (From Clock Board)

All hardware used in Data Path Test.

TEST DESCRIPTION:
This tests the latch mode of 10130 latches of the lower 8 bits, with the upper
eight bits in transparent mode. The Latch Clock 0-7 feeds the common Enable
input to the 10130's. This input is held high, and pulsed low to latch the
current data from the "D" to the "Q". The Glitch is disabled so the other
Enable input is held low. The upper bits 8-F are not latched, the Data slips
through the "D" to the "Q".
If there are any errors in this test, but the Data Path
failure is probably in the Latch Clock or the 10130's.

Test

passed,

TEST STEP INFORMATION:
Step

Data

Data Written to

Data Verified at

---------------------------------------------------------------------

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

OOOOH
5555H

AAAAH

CCCCH
3333H
6666H
9999H
FFFFH
0001H
0002H
0004H
0008H
OOlOH
0020H
0040H
0080H
0100H
0200H
0400H
0800H
1000H
2000H
4000H
8000H

OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,

Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic

Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch

5-31

OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,

Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample

Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register

the

ERROR MESSAGES:
If an error occurs, the following message is displayed:

* Test FAILED--Test Step ssss
Latch Data bits 0-7 Error
I/O Address
aaaaH
Data Read
rrrrH
eeeeH
Data Expected
Error Bit Map
= OOOOOOOOOOOOOOOOB
Board Status X8 = iiiiH
Where:
ssss

is the test step number in the range of 1 to 24.

aaaa

is the I/O address of the Data Board:
OC6H for Data Board A Sample Register,
OD6H for Data Board B Sample Register,
OE6H for Data Board C Sample Register.

rrrr

is the Data Word read from the Data Board.

eeee

is the Data Word Expected from the Data Board.

iiil

is the Status information from the current Data Board under test.

NOTE:

The Error Bit Map is a map of the Data Bus, DO - 015, and is an
exclusive OR of the Data Read and the Data Expected. Any bits that are
different show up as a "1". Bits that show up as a "0" passed the compare.

5-32

Data Board Diagnostic Subtest 5
LATCH DATA BITS 8-F TEST

TITLE:
TARGET LOGIC:

5F
5L
2H IH 4H 3H IIH 10H 13H 12H
Diagnostic Latch Clock

PI-44 (From Clock Board)

All hardware used in Data Path Test.

TEST DESCRIPTION:
This subtest is identical to the previous test except that the upper Data bits
8-F are tested instead of the lower bits 0-7.
The test verifies the latch mode of 10130 latches the upper 8 bits, with the
lower eight bits in transparent mode. The Latch Clock 8-F feeds the common
Enable input to the 10130's. This input is held high, and pulsed low to latch
the current data from the "D" to the "Q". The Glitch is disabled so the other
Enable input is held low. The lower bits 0-7 are not latched, the Data slips
through the "D" to the "Q".
If there are any errors in this test, but the Data Path
failure is probably in the Latch Clock or the 10130's.

Test

passed,

TEST STEP INFORMATION:
Step

Data

Data Written to

Data Verified at

--------------------------------------------------------------------

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

OOOOH
5555H

AAAAH

CCCCH
3333H
6666H
9999H
FFFFH
0001H
0002H
0004H
0008H
0010H
0020H
0040H
0080H
0100H
0200H
0400H
0800H
1000H
2000H
4000H
8000H

OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,

Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic

Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch

5-33

OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,

Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample

Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register

the

ERROR MESSAGES:
If an error occurs, the following message is displayed:

* Test FAILED--Test Step ssss
Latch Data bits 8-F Error
I/O Address
aaaaH
Data Read
rrrrH
eeeeH
Data Expected
Error Bit Map
OOOOOOOOOOOOOOOOB
iiiiH
Board Status X8
Where:
ssss

is the test step number in the range of 1 to 24.

aaaa

is the I/O address of the Data Board:
OC6H for Data Board A Sample Register,
OD6H for Data Board B Sample Register,
OE6H for Data Board C Sample Register.

rrrr

is the Data Word read from the Data Board.

eeee

is the Data Word Expected from the Data Board.

iiii

is the Status information from the current Data Board under test.

NOTE: The Error Bit Map is a map of the Data Bus, DO - DIS, and is an
exclusive OR of the Data Read and the Data Expected. Any bits that are
different show up as a "1". Bits that show up as a "0" passed the compare.

5-34

Data Board Diagnostic Subtest 6

TITLE:

GLITCH DATA BITS 0-7 TEST

TARGET LOGIC:

2E IE 2F IF
4E 3F 4F 3E
lIE 10E 11F 10F
13E 12F 13F 12E
2H 1H 4H 3H
11H 10H 13H 12H
All hardware in the Data Path Test.

TEST DESCRIPTION:
This subtest tests the Glitch capture feature of the Data boards by enabling
the Glitch circuitry which uses the Set and Reset pins on the 10130's, instead
of the D inputs to send the Data from the 10121 Multiplexers to the Q output.
The individual Enable pins on the 10130's are held high so that any cloCking
from the Diagnostic Latch Clock is disabled.
Each output instruction to the Diagnostic bits port OC6H, latches the Data in
the Glitch latches. A Sample Clock is required to send the Data through to the
Sample Register. A maximum of two Data values may be output to the Diagnostic
bits port before data overrun occurs.
The way that this circuitry is tested, is two consecutive Output instructions
are performed with different Data. The first Data is checked at the Sample
register after issuing a single Sample Clock. Another Sample Clock presents
the Second Data to the Sample Register.
In this test, only Data bits 0-7 are in the Glitch Mode.- The upper bits 8-F
slip through the 10130's because both of the enable pins are low, so Q follows
D.

TEST STEP INFORMATION:
Step
1
2
3
4

5
6
7
8
9
10
11

1st Data

2nd Data

OOOOH
OOOOH
0055H
OOAAH
OOCCH
0033H
0066H
0099H
OOFFH
0001H
0002H

-----OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
5-35

Step

1st Data

2nd Data (cont'd)

12
13
14
15
16
17
18

0004H
0008H
0010H
0020H
0040H
0080H
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH

OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH

19

20
21
22
23
24
25

ERROR MESSAGES:
If an error occurs, the following message is displayed:

* Test FAILED--Test Step ssss
Glitch Data Bits 0-7 Error
I/O Address
= aaaaH
Data Read
= rrrrH
Data Expected
= eeeeH
Error Bit Map
= OOOOOOOOOOOOOOOOB
Board Status X8 = iiiiH
Where:
ssss

is the test step number in the range of 1 to 25.

aaaa

is the I/O address of the Data Board:
OC6H for Data Board A Sample Register,
OD6H for Data Board B Sample Register,
OE6H for Data Board C Sample Register.

rrrr

is the Data Word read from the Data Board.

eeee

is the Data Word Expected from the Data Board.

iiii

is the Status information from the current Data Board under test.

NOTE: The Error Bit Map is a map of the Data Bus, DO - 015, and is an
exclusive OR of the Data Read and the Data Expected. Any bits that are
different show up as a 1. Bits that show up as a "0" passed the compare.

5-36

Data Board Diagnostic Subtest 7
GLITCH DATA BITS

TITLE:
TARGET LOGIC:

8-F TEST

2E IE 2F IF
4E 3F 4F 3E
lIE 10E IlF 10F
13E 12F 13F 12E
2H IH 4H 3H
IlH 10H 13H 12H
All hardware in the Data Path Test.

TEST DESCRIPTION:
This subtest is similar to the Glitch Data Bits 0-7 except the upper bits are
being tested.
This
subtest checks the Glitch capture feature of the Data
boards by enabling the Glitch circuitry which uses the "Set" and "Reset" pins
on the 10130's, instead of the "D" inputs to send the Data from the 10121
Multiplexers to the "Q" output. The individual Enable pins on the 10130's are
held high so that any "clocking" from the Diagnostic Latch Clock is disabled.
Each output instruction to the Diagnostic bits port OC6H, latches the Data in
the Glitch latches. A Sample Clock is required to send the Data through to the
Sample Register. A maximum of two Data values may be output to the Diagnostic
bits port before data overrun occurs.
The way that this circuitry is tested, is two consecutive Output instructions
are performed with different Data. The first Data is checked at the Sample
register after issuing a single Sample Clock. Another Sample Clock presents
the Second Data to the Sample Register.
In this test, only Data bits 8-F are in the Glitch Mode.- The lower bits 0-7
slip through the 10130's because both of the enable pins are low, so Q follows
D.

TEST STEP INFOBMATION:
Step
1
2
3
4
5
6
7
8
9

1st Data

2nd Data

OOOOH
OOOOH
5500H
AAOOH
CCOOH
3300H
6600H
9900H
FFOOH

-----OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH

5-37

Step

1st Data

2nd Data (Cont'd)

10
11
12
13
14
15
16

OOOOR
OOOOR
OOOOR
OOOOR
OOOOR
OOOOR
OOOOR
OOOOR
OlOOR
0200R
0400R
0800R
1000R
2000R
4000R
8000R

OOOOR
OOOOR
OOOOR
OOOOR
OOOOR
OOOOR
OOOOR
OOOOR
OOOOR
OOOOR
OOOOR
OOOOR
OOOOR
OOOOR
OOOOR
OOOOR

17

18
19

20
21
22
23
24
25

ERROR MES SAGES:

If an error occurs, the following message is displayed:

* Test FAILED--Test Step ssss
Glitch Data Bits 8-F Error
I/O Address
= aaaaR
= rrrrR
Data Read
Data Expected
= eeeeH
Error Bit Map
= OOOOOOOOOOOOOOOOB
Board Status X8 = iiiiH
Where:
ssss

is the test step number in the range of 1 to 25.

aaaa

is the I/O address of the Data Board:
OC6H for Data Board A Sample Register,
OD6R for Data Board B Sample Register,
OE6R for Data Board C Sample Register.

rrrr

is the Data Word read from the Data Board.

eeee

is the Data Word Expected from the Data Board.

iiii

is the Status information from the current Data Board under test.

NOTI: The Error Bit Map is a .ap of the Data Bus, DO - DIS,

and is an
exclusive OR of the Data Read and the Data Expected. Any bits that are
different show up as a "1". Bits that show up as a "0" passed the compare.

5-38

Data Board Diagnostic Subtest 8

TITLE:

PROBES/MULTIPLEX TEST

TARGET LOGIC:

8F

2B 1B 4B 3B lIB lOB 13B 12B
2D 1D 2C 1C 4D 3C 4C 3D
lID 10D 11C 10C 13D 12C 13C 12D
J1, J2, Internal Probe Cables, External Probe Cables
All of the hardware in the Data Path Test.

TEST DESCRIPTION:
This subtest checks the five Multiplexing Select Modes of the Data Board.
five modes are:
1.

NORMAL mode. This samples the logic state at the inputs of J1 and
J2. This logic state is set high or low by the external probes.

2.

DEMUX mode. This is similar to the Normal Mode except the lower
eight bits are mirrored into the upper eight bits.

3.

DIAGNOSTIC select. This reads the Diagnostic bits Register.

4.

MEMORY select. This reads the data that is currently residing in the
ECL Memory, (Manual Recirculate).

5.

NOTHING
SELECTED. With all four select lines disabled,
lines should be pulled up to read OFFFFH.

the

This subtest requires the use of a known good Threshold Board and
installation of the external probes. The Normal Mode and the Demux Mode
the Threshold board to set different thresholds at the hybrid circuit in
probes.

TEST STEP INFOIMATION:
Step
1

2
3
4
5
6
7
8

9

The

Data Expected

Multiplex

Lower Threshold

Upper Threshold

FFFFH
OOOOH
OOFFH
FFFFH
OOOOH
FFFFH
F069H
5AC3H
FFFFH

Normal
Normal
Normal
Demux
Demux
Demux
Diagnostic
Memory
Floating

ECL
VARIABLE A
ECL
ECL
VARIABLE A
ECL

ECL
VARIABLE
VARIABLE
ECL
VARIABLE
VARIABLE

------------

-----------------------

5-39

A
A
A
A

-------------------------------------

Data
the
use
the

ERROR MESSAGES:
If an error occurs, the following message is displayed:

* Test FAILED--Test Step ssss
hmsg
I/O Address
aaaaH
Data Read
= rrrrH
Data Expected
eeeeH
OOOOOOOOOOOOOOOOB
Error Bit Map
Board Status X8
iiiiH
Where:
ssss

is the test step number in the range of 1 to 9.

hmsg

is the Error heading message:
Normal ECL Threshold Mux Error,
Normal VARA F Threshold Mux Error,
Normal ECLVARA Threshold Mux Error,
Demux ECL Threshold Mux Error,
Demux VARA F Threshold Mux Error,
Demux ECLVARA Threshold Mux Error,
Diagnostic Select Mux Error,
Memory Select Mux Error,
Multiplexer Disable-Float Error.

aaaa

is the I/O address of the Data Board:
OC6H for Data Board A Sample Register,
OD6H for Data Board B Sample Register,
OE6H for Data Board C Sample Register.

-

rrrr

is the Data Word read from the Data Board.

eeee

is the Data Word Expected from the Data Board.

iiii

is the Status information from the current Data Board under test.

NOTB: The Brror Bit Map is a map of the Data Bus, DO - D15, and is an
exclusive OR of the Data Read and the Data Expected.
Any bits that are
different abOlf up as a "1". Bits that show up as a "0" passed the compare.

5-40

nata Board Diagnostic Subtest 9
PIPELINES SHIFT TEST

TITLE:
TARGET LOGIC:

2K lK 3K 11K 12K 13K
2L lL 3L 4L 10K IlL 12L 13L
5K
Sample Clock PI-42,
Control Clock Pl-46, (from Clock Board).
All hardware in Data Path Test.

TEST DESCRIPTION:
This test checks the Data Board Pipeline. The Pipeline consists of a three
step FILa, (first in last out), with D latches at each step that can be read.
The steps are called the Sample Register, the New Pipe Register, and the Old
Pipe Register.
With each Pipeline Clock transition, the Old Pipeline Register Data is lost
and receives its new data from the New Pipeline Register. The New Pipeline
Register receives its new data from the Sample Register. The Sample Register
receives its data from the 10130 Glitch Latches.
The Pipeline can receive it's clocking from either the Sample Clock if Single
Phase Mode is selected, or from the Control Clock if Multi Phase Mode is
selected. Test Steps 1 - 24 will use the Sample Clock, and Test Steps 25 - 4B
will use the Control Clock.

TEST STEP INFORMATION:
Step

Sample Data

New Pipe Data

Old Pipe Data

Mode of Phase

--------------------------------------------------------------------1
OOOOH
OOOOH
OOOOH
Single Phase
2
3
4
5
6
7

B
9
10
11
12
13
14
15
16

5555H
AMAH

CCCCH
3333H
6666H
9999H
FFFFH
0001H
0002H
0004H
OOOBH
0010H
0020H
0040H
OOBOH

OOOOH
OOOOH
5555H

OOOOH
5555H
AMAH

CCCCH
3333H
6666H
9999H
FFFFH
0001H
0002H
0004H

AMAH

CCCCH
3333H
6666H
9999H
FFFFH
0001H
0002H
0004H

OOOBH

OOOBH

0010H
0020H
0040H

0010H
0020H
5-41

Single
Single
Single
Single
Single
Single
Single
Single
Single
Single
Single
Single
Single
Single
Single

Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase

Step

Sample Data

New Pipe Data

Old Pipe Data

Mode of Phase(Cont'd)

-----------------------------------------------------------------------------

17
18
19
20
21
22
23
24

OlOOH
0200H
0400H
0800R
1000R
2000H
4000R
8000R

0080H
OlOOH
0200H
0400H
0800R
lOOOR
2000R
4000H

0040H
0080H
OlOOH
0200R
0400R
0800R
1000R
2000R

Single
Single
Single
Single
Single
Single
Single
Single

25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48

OOOOR
5555H

OOOOH
OOOOR
5555H
AAAAH

OOOOR
OOOOR
OOOOR
5555R

CCCCR
3333H
6666R
9999R
FFFFH
OOOIH
0002H
0OO4H
0OO8R
OOIOH
0020H
0040R
0080H
OIOOR
0200H
0400H
0800H
lOOOH
2000H
4000H

CCCCR
3333H
6666R
9999H
FFFFH
OOOlH
0OO2R
0OO4R
0OO8R
OOIOR
0020R
0040R
0080H
OIOOH
0200H
0400H
0800H
IOOOH
2000H

Multi
Multi
Multi
Multi
Multi
Multi
Multi
Multi
Multi
Multi
Multi
Multi
Multi
Multi
Multi
Multi
Multi
Multi
Multi
Multi
Multi
Multi
Multi
Multi

AAAAH

CCCCR
3333H
6666H
9999H
FFFFH
OOOlH
0002H
0OO4H
0OO8R
OOlOH
0020R
0040R
0080R
OIOOR
0200H
0400R
0800H
lOOOH
2000R
4000H
8000R

AAAAH

ERROR MES SAGES:
If an error occurs, the following message is displayed:

* Test FAILED--Test Step ssss
hmsg
I/O Address
- aaaaH
Data Read
= rrrrH
Data Expected
- eeeeH
Error Bit Map
= OOOOOOOOOOOOOOOOB
Board Status X8 = iiiiR
Where:
ssss

is the test step number in the range of 1 to 48.

5-42

Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase

Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase

hmsg

is the Error heading message:
Sample Clock: Old Pipe Register Error
Sample Clock: New Pipe Register Error
Sample Clock: Sample Register Error
Control Clock: Old Pipe Register Error
Control Clock: New Pipe Register Error
Control Clock: Sample Register Error

aaaa

is the I/O address of the Data Board:
OC2H
OC4H
OC6H
OD2H
OD4H
OD6H
OE2H
OE4H
OE6H

for
for
for
for
for
for
for
for
for

Data
Data
Data
Data
Data
Data
Data
Data
Data

Board
Board
Board
Board
Board
Board
Board
Board
Board

A Old Pipe Register,
A New Pipe Register,
A Sample Register,
B Old Pipe Register,
B New Pipe Register,
B Sample Register,
C Old Pipe Register,
C New Pipe Register,
C Sample Register.

rrrr

is the Data Word read from the Data Board.

eeee

is the Data Word Expected from the Data Board.

iiii

is the Status information from the current Data Board under test.

NOTE: The Error Bit Map is a map of the Data Bus, DO - DIS, and is an
exclusive OR of the Data Read and the Data Expected.
Any bits that are
different show up as a 1. Bits that show up as a 0 passed the compare.

5-43

Data Board Diagnostic Subtest 10

RAM DATA INTEGRITY TEST

TITLE:

TARGET LOGIC:

6E 6D 7E 7D 8E 8D
5B 5C 6B 6C 8B 8C 9B 9C
5D 5E 9E 9D
SA 6A 8A 9A
6J 5J 5L 8J 4K
6H
All hardware in Data Path Test.

TEST DESCRIPTION:
This test performs a static test of the RAM on the Data boards.
This is done
using the 24 Data patterns. All 2048 Memory locations are written to with the
same data to the same I/O port OC6H. Since The address counters should be
advancing on each Sample Clock. all locations should be written to. This test
does not check the addressing uniqueness of each location. It does verify that
all Data bits are functional and totally independent of each other.
Prior to this test. the Data path up to the Old Pipe Register has been
checked. There are two 10176 tiD" latches between the Old Pipe Register and the
RAM chip. These latches receive their clock from either WEOl/ or WE02/.
depending on the current Phase of the clock. The signals WE01/ and WE02 also
are the write enables to the RAM chips. So The RAM chips are alternately
written to on each Sample Clock.

TEST STEP INFORMATION:
Step

Data

Data Written to

Data Verified at

-----------------------------------------------------------------------------1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

OOOOH
5555R

AAAAH

CCCCR
3333R
6666R
9999H
FFFFR
OOOlR
0002R
0004R
0008R
OOIOR
0020H
0040R
0080R
OlOOR
0200R
0400H
0800R
1000R
2000R
4000H
8000R

OC6R.
OC6R.
OC6R,
OC6R,
OC6R,
OC6R,
OC6R,
OC6R,
OC6R,
OC6R,
OC6R,
OC6R,
OC6R,
OC6R,
OC6R,
OC6R,
OC6R,
OC6R,
OC6R.
OC6R,
OC6R.
OC6R,
OC6H.
OC6R.

Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic

Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch

5-44

OCOR.
OCOR.
OCOR.
OCOR.
OCOR,
OCOR,
OCOR,
OCOR,
OCOR,
OCOR,
OCOR,
OCOR,
OCOR,
OCOR,
OCOR,
OCOR,
OCOR.
OCOR,
OCOR.
OCOR,
OCOR.
OCOR.
OCOR.
OCOR.

RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM

Locations
Locations
Locations
!.ocations
Locations
Locations
Locations
Locations
Locations
Locations
Locations
Locations
Locations
Locations
Locations
Locations
Locations
Locations
Locations
Locations
Locations
Locations
Locations
Locations

000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000

-

IFFH
IFFR
IFFR
IFFR
IFFR
1FFR
IFFR
1FFR
IFFR
IFFR
IFFR
IFFR
1FFR
IFFR
1FFR
lFFR
IFFR
IFFR
IFFR
IFFH
IFFR
IFFH
IFFR
IFFR

ERROR MESSAGES:

If an error occurs, the following message is displayed:

* Test FAILED--Test Step ssss
RAM Data Integrity Verify Error
Byte Count
= aaaaH
Data Read
= rrrrH
Data Expected
eeeeH
Error Bit Map
OOOOOOOOOOOOOOOOB
Board Status X8 = iiiiH
Where:
ssss

is the test step number in the range of 1 to 24.

aaaa

is the Address offset for the RAM, in the range of

rrrr

is the Data Word read from the Data Board.

eeee

is the Data Word Expected from the Data Board.

iiii

is the Status information from the current Data Board under test.

o to

IFFH.

NOTE: The Error Bit Map is a map of the Data Bus, DO - DIS, and is a exclusive
01 of the Data Read and the Data Expected. Any bits that are different show up
as a 1. Bits that show up as a 0 passed the compare.

5-45

Data Board Diagnostic Subtest 11
TITLE:

RAM ADDRESSING INTEGRITY TEST

TARGET LOGIC:

6E
5B
5D
5A
6J
6R

6D
5C
5E
6A
5J

7E
6B
9E
8A
5L

7D 8E 8D
6C 8B 8C 9B 9C
9D
9A
8J 4K

All hardware in Data Path Test.

TEST DESCRIPTION:
This test writes a unique Data value to each of the 2048 Memory locations.
Each memory location should contain unique Data from each other location. The
Memory is read back and each location is verified to see if each address is
uniquely addressable.
The Data that is written is an incrementing pattern. The first
starts with a value of 0001R for the first location, and the
locations are written to with a 0002H, 0003H, etc.

test step
sequential

The second Test step is similar to the first, except the starting Data value
is a 0002H. Subsequent test steps shift this Data value left, so that the
starting Data values for the 16 test steps are:

TEST STEP INFORMATION:
Step
1
2
3
4
5

6
7
8
9
10
11
12
13
14
15
16

Start Data
0001R
0002H
0004R
0008H
0010H
0020H
0040H
0080H
0100H
0200H
0400H
0800H
1000H
2000H
4000R
8000H

Data Written to
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,
OC6H,

Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic

Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch

5-46

Data Verified at
OCOH, RAM
OCOH, RAM
OCOH, RAM
OCOH, RAM
OCOH, RAM
OCOH, RAM
OCOH, RAM
OCOH, RAM
OCOH, RAM
OCOH, RAM
OCOH, RAM
OCOH, RAM
OCOH, RAM
OCOH, RAM
OCOH, 'RAM
OCOH, RAM

Locations
Locations
Locations
Locations
Locations
Locations
Locations
Locations
Locations
Locations
Locations
Locations
Locations
Locations
Locations
Locations

000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000

-

1FFH
1FFH
1FFH
1FFH
1FFH
1FFH
1FFH
1FFH
1FFH
1FFH
1FFH
1FFH
IFFH
1FFH
IFFH
IFFH

ERROR MESSAGES:
If an error occurs, the following message is displayed:

* Test FAILED--Test Step ssss
RAM Address Unique Error
Byte Count
= aaaaH
Data Read
= rrrrH
Data Expected
eeeeH
Error Bit Map
OOOOOOOOOOOOOOOOB
Board Status X8
iiiiH
Where:
ssss

is the test step number in the range of 1 to 16.

aaaa

is the Address offset for the RAM, in the range of

rrrr

is the Data Word read from the Data Board.

eeee

is the Data Word Expected from the Data Board.

iiii

is the Status information from the current Data Board under test.

o to

1FFH.

NOTE: The Error Bit Map is a map of the Data Bus, DO - DIS. and i. an
exclusive OR of the Data Read and the Data Expected. Any bits that are
different show up as a 1. Bits that show up as a 0 passed the compare.

5-47

Data Board Diagnostic Subtest 12
TITLE:

TRACE CONDITIONS TEST

TARGET LOGIC:

8J 8H
6H 6L 9H
12M 13M 3M 11M 10M

TRACED/ Signal P2-S6 from Control Board
ARMED
Signal P2-S8 from Control Board

TEST DESCRIPTION:
This test uses the Control Board to provide Trace Conditions that exist on the
Data Board. These are mainly ARMED and TRACED/. This test is similar to the
Force Conditions Test.

TEST STEP INFORMATION:
Step
1

2
3
4

Status Expected
4SH
CSH
72H
71H

EOOR MESSAGES:

If an error occurs, the following message is displayed:

* Test FAILED--Test Step ssss
Trace Conditions Error
I/O Address
= aaaaH
Status Read
= rrrrH
Status Expected = eeeeH
Error Bit Map
= OOOOOOOOOOOOOOOOB
Board Status X8 = iiiiH
Where:
ssss

is the test step number in the range of 1 to 4.

aaaa

is the I/O address of the Data Board:
OC8H for Data Board A Status Register,
OD8H for Data Board B Status Register,
OE8H for Data Board C Status Register.

rrrr

is the Data Word read from the Data Board.

eeee

is the Data Word Expected from the Data Board.

iiii

is the Status information from the current Data Board under test.

NOTE: The Error Bit Map is a map of the Data Bus, DO - DlS, and is an
exclusive OR of the Data Read and the Data Expected. Any bits that are
different show up as a 1. Bits that show up as a 0 passed the compare.
5-48

Data Board Diagnostic Subtest 13
RECIRCULATE RAM TEST

TITLE:

TARGET LOGIC:
The main hardware being tested is the feed back loop of the 10173 Multiplexers
5D, 5E, 9E and 9D, to the 10121 Multiplexers with Memory Select Enabled.
The entire Data Path and most of the Control Logic must be fuctional for this
test to pass.

TEST DESCRIPTION:
The contents of the ECL RAM is recirculated out of the RAM through the
Multiplexers, through the Glitch Latches, through the Sample Register, through
the New Pipe Register, through the Old Pipe Register, through the RAM latch
and back into the ECL RAM. All of the clocking is done by the Clock board and
the Control Board.
There is a time-out counter on the recirculation, and after the recirculation
is completed, the Data in the ECL RAM should be the same as before.

TEST STEP INFORMATION:
Step

Status Expected

Clock Time Out

1

BOOOH
BOOOH
BOOOH

10 usec
20 usec
30 usec

3

5

Step
2
4
6

Data Expected
OOOOH - 01FFH (incrementing pattern)
OOOOH - 01FFH (incrementing pattern)
OOOOH - OlFFH (incrementing pattern)

ERROR MESSAGES:
If an error occurs, the following message is displayed:

* Test FAILED--Test Step ssss
hmsg
I/O Address
= aaaaH
Data Read
= rrrrH
Data Expected
= eeeeH
Error Bit Map
= OOOOOOOOOOOOOOOOB
Board Status XB = iiiiH

5-49

ERROR MESSAGES: (Cont'd)
Where:
ssss

is the test step number in the range of 1 to 6.

hmsg

is the Error heading message:
Recirculation
Recirculation
Recirculation
Recirculation
Recirculation
Recirculation

aaaa

Time out-lOus clock,
Error-lOus clock,
Time out-20us clock,
Error-20us clock,
Time out-30us clock,
Error-30us clock.

is the I/O address of the Data Board:
OCOR
ODOR
OEOR
OFOR

for
for
for
for

Data Board A RAM,
Data Board B RAM,
Data Board C RAM,
Control Board Status.

rrrr

is the Data Word read from the Data Board.

eeee

is the Data Word Expected from the Data Board.

iiii

is the Status information from the current Data Board under test.

NOTI: The Error Bit Map is a map of the Data Bus, DO - D1S, and is an
exclusive OR of the Data Read and the Data Expected. Any bits that are
different show up as a 1. Bits that show up as a 0 passed the compare.

5-50

1450 CONTROL BOARD DIAGNOSTIC
DIAGNOSTIC OVERVIEW
This section describes the subtests that are performed by the K450 Control
Board Diagnostic. The target hardware is presented, as well as a general
description of each subtest, a list of information for each test step, and a
description of Error Messages that may be printed for the subtest results.
The Control Board Diagnostic is divided into 12 subtests, each of which is
described individually on the following pages.
Subtest 1 is a Force Conditions test, subtest 2 is an Advance RAM Forward and
Jump RAM backward test, subtest 3 and 4 are Detection RAMs Data and Address
integrity test, subtest 5
and 6 are Delay Control RNI Data and Address
integrity test, subtest 7 and 8 are Delay RAMs Data and Address integrity
test, subtest 9 is Delay Counter test, subtest 10 is Relation Logic test,
subtest 11 and 12 are Selection RAMs data and Address integrity test.
Subtests 1, 2, and 3 require Data Boards A, E, and C installed in the system.
The external signals through mother board to the Data Boards are checked by
subtest 1, the external signals through connector J1 to the Clock Board are
checked by subtest 2.

NOTE: The TARGET LOGIC listed in each subtest description does not necessarily
include all of the logic which could affect the operation of the subt •• t.
SUITEST CATEGORY
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.

Force Condition Test
Advance and Jump RAM Test
Detection RAMs Data Integrity Test
Detection RAMs Address Integrity Test Delay Control RAM Data Integrity Test
Delay Control Ram Address Integrity Test
Delay RAMs Data Integrity Test
Delay RAMs Address Integrity Test
Delay Counter Test
Relation Logic Test
Selection RAMss Data Integrity Test
Selection RAMs Address Integrity Test

5-51

ERROR COUNT CATEGORY
1•
2.
3.
4.

5.
6.
7•

8.
9.
10.
11 •
12.

Subtest
Subtest
Subtest
Subtest
Subtest
Subtest
Subtest
Subtest
Subtest
Subtest
Subtest
Subtest

Error Count
Error Count
Error Count
Error Count
5 Error Count
6 Error Count
7 Error Count
8 Error Count
9 Error Count
10 Error Count
11 Error Count
12 Error Count
1
2
3
4

5-52

Control Board Diagnostic Subtest 1
FORCE CONDITION TEST

TITLE:
TARGET LOGIC:

6A, 7A, SA, 4A, IIA, SF, 7D, 5C, 5D, 7C, 4D, 8D,
IC, 3C, 8C, 9C, 5G, 11G, 4J, 12C, 14B, 12A, 12F,
and 5K, 8J, 8R, 6R of DATA BOARD A, B, and C

TEST DESCRIPTION:
The force condition is functionally tested by forcing the desired condition
true. The condition is then verified by reading back the corresponding status
bit.
There are seven force condition tests included. Condition 0 is force level O.
Condition 1 is force jump and jump not.
Condition 2 is force trace and trace
not. Condition 3 is force stop and stop not. Condition 4 is force event and
advance. Condition 5 is force stopped and armed. Condition 6 is force manual
advance.
Condition 2 also verifies the TRACED signal can propagate through the mother
board to data boards A, B, and C. Condition 5 also verifies the MEM. ARMED
signal can propagate through the mother board to data boards A, B, and C.
TEST STEP INFORMATION:
Test Step
1
2
3
4.
5.
6.
7.

Condition Tested

Signals in schematics

force
force
force
force
force
force
force

'FORCE LEVEL=O'
'FORCE JUMP' ,'FORCE JUMP/'
'FORCE TRACE' ,'FORCE TRACE/'
'FORCE STOP' ,'FORCE STOP/'
'FORCE EVENT AND ADVANCE'
'CYCLE RESET'
'ENABLE MANUAL ADVANCE'

level 0
jump and jump not
trace and trace not
stop and stop not
event and advance
stopped and armed
manual advance

ERROR MESSAGES:
1.

If error condition 0 occurs, the following message is displayed:
*TEST FAILED -- TEST STEP zz
CONDITION : Force Level 0
Level Expected - eeH
Level Read
= rrH
Where zz should be 01
ee should be 00 through OF
rr should be 00 through OF

5-53

ERROR MESSAGES (Cont'd)
2.

If error condition 1 occurs, the following message is displayed:
*TEST FAILED -- TEST STEP zz
CONDITION : Force JUMP & JUMP NOT
Jump Expected = e
Jump Read
= r
Where zz should be 02
e should be 0 or 1
r should be 0 or 1

3.

If error condition 2 occurs, the following message is displayed:
*TEST FAILED -- TEST STEP zz
CONDITION : Force TRACE & TRACE NOT
Trace Expected
e
Trace Read
r
a
Old Traced A Expected
Old Traced A Read
t
Old Traced B Expected = b
Old Traced B Read
u
Old Traced C Expected = c
Old Traced C Read
=v
Where zz should be 03
e, r, a, t, b, u, c, v should be 0 or 1

4.

If error condition 3 occurs, the following message is displayed:
*TEST FAILED -- TEST STEP zz
CONDITION : Force STOP & STOP NOT
Stop Expected
e
Stop Read
=r
Where zz should be 04
e should be 0 or 1
r should be 0 or 1

5.

If error condition 4 occurs, the following message is displayed:
*TEST FAILED -- TEST STEP zz
CONDITION : Force EVENT & ADVANCE
Event Expected
e
Event Read
= r
Advance Expected = p
= d
Advance Read

5-54

ERROR MESSAGES (Cont'd)
Where zz should be 05
e, r, p, d should be 0 or 1
6.

If error condition 5 occurs, the following message is displayed:
*TEST FAILED -- TEST STEP zz
CONDITION : Force STOPPED & ARl1ED
Stopped Expected
=e
Stopped/ Read
=r
Armed Expected
= p
Armed/ Read
d
Mem. Armed A Expected = a
t
Hem. Armed A Read
b
Mem. Armed B Expected
u
Mem. Armed B Read
Mem. Armed C Expected = c
Mem. Armed C Read
= v
Where zz should be 06
e, r, p, d, a, t, b, u, c, v should be 0 or 1

7.

If

error condition 6 occurs, the following message is displayed:

*TEST FAILED -- TEST STEP zz
CONDITION : Force MANUAL ADVANCE
Advance Expected
= e
= r
AdvancE Read
Manual Advance Expected = p
= d
Man. Advance Read
Where zz should be 07
e, r, p, d should be 0 or 1

5-55

Control Board Diagnostic Subtest 2

TITLE:

ADVANCE AND JUMP RAM TEST

TARGET LOGIC:

SH, SJ, SG, 11 G, 12F, 11 F ,
and level memory logic in the clock board,
connector Jl included.

TEST DESCRIPTION:
The advance and jump RAJ~ are functionally tested by advancing the Advance RAM
to the next level and restoring the jump RAJi backward to a previous level. The
RAM data is then verified by reading back the level and comparing the result
to the expected level.

TEST STEP INFORMATION:
Test Step
1 through 16
17 through 32

RAM Tested
advance
jump

Level Tested

Expected Level

OOH through OFH
OOH through OFH

Level tested + 1
Level tested - 1

ERROR MESSAGE:
1.

If
an error
displayed:

of Advance RAM

occurs,

the

*TEST FAILED -- TEST STEP zz
Adv. RAM Advancing Test
Adv. RAM Level at
= 11H
Adv. RAM Data Expected = eeH
Adv. RAM Data Read
rrH
Error Bit Map
= xxxxxxxxB
Ext. Level Expected
= ppH
= qqH
Ext. Level Read
Error Bit Map
yyyyyyyyB
Where zz should be 01 through 16
11 should be 00 through OF
ee should be 00 through OF
rr should be 00 through OF
pp should be 00 through OF
qq should be 00 through OF
xxxxxxxx should be 00000000 through 00001111
yyyyyyyy should be 00000000 through 00001111
5-56

following

message

is

ERROR MESSAGE (Cont'd)
2.

If an error of Jump RAM occurs, the following message is displayed:
*TEST FAILED -- TEST STEP zz
Jump RAM Advancing Test
Jump RAM Level at = llH
Jump RAM Data Expected = eeH
Jump RAM Data Read = rrH
Where zz should be 17 through 32
11 should be 00 through OF

ee should be 00 through OF
rr should be 00 through OF

5-57

Control Board Diagnostic Subtest 3
DETECTION RAM DATA INTEGRITY TEST

TITLE:

TARGET LOGIC:

8G, 8F, 9G, 9F,
4G, 4F, 7G, 7F,
1G, 1F, 3G, 3F,
2J, 6B, 5B, 4B,
5D, 5C, 7C, 4D,
12C, 12G, 12H

8D,
3D,
1D,
7B,
SF,

9D
4D, 7D
3D
8B, 1B, 2B, 3B, 8A, 9A
3C, 1C, 8C, 9C, 9B

TEST DESCRIPTION:
The detection RAMs data integrity is functionally tested by writing a four
bits nibble into each RAM, the RAM data is then verified by reading the
(ADVANCE, JUMP , STOP ,TRACE) nibble and comparing the result to the expected
nibble.
The nibble patterns tested are:
1010B, 0101B, 1100B, 0011B, 0001B, 0010B, 0100B, 1000B.
The detection RAMs tested are:
8G, 8F, 9G, 9F, 4G, 4F, 7G, 7F, 1G, IF, 3G, 3F.
TEST STEP INFORMATION:
Test Step
01
09
17
25
33
41
49
57
65
73
81
89

through
through
through
through
through
through
through
through
through
through
through
through

RAM Chip Location
08
16
24
32
40
48
56
64
72
80
88
96

8G(00)
8F( 01)
9G(02)
9F(03)
4G(04)
4F(05)
7G(06)
7F(07)
1G(08)
1F(09)
3G(10)
3F(11)

Nibble Patterns
1010,0101,1100,0011,0001,0010,0100,1000
1010,0101,1100,0011,0001,0010,0100,1000
1010,0101,1100,0011,0001,0010,0100,1000
1010,0101,1100,0011,0001,0010,0100,1000
1010,0101,1100,0011,0001,0010,0100,1000
1010,0101,1100,0011,0001,0010,0100,1000
1010,0101,1100,0011,0001,0010,0100,1000
1010,0101,1100,0011,0001,0010,0100,1000
1010,0101,1100,0011,0001,0010,0100,1000
1010,0101,1100,0011,0001,0010,0100,1000
1010,0101,1100,0011,0001,0010,0100,1000
1010,0101,1100,0011,0001,0010,0100,1000

5-58

ERllOR MES SAGE:

If an error occurs, the following message is displayed:
*TEST FAILED -- TEST STEP zz
Detection RAMs Data Integrity Test
RAM chip location
= cc
Detect Address
ddR
AJST/ Nibble Expected = nnR
AJST/ Nibble Read
= rrR
Error Bit Map
= xxxxxxxxB
Where cc should be 00 through 11
dd should be 00 through FF
nn should be OA,05,OC,03,01,02,04,08
rr should be 00 through FF
xxxxxxxx should be 00000000 through 00001111
ROTE: AJST is the abbreviation of ADVANCE, JUMP, STOP, TlACE nibble.

5-59

Control Board Diagnostic Subtest 4

TITLE:

DETECTION RAU ADDRESS INTEGRITY TEST

TARGET LOGIC:

1H,
8G,
4G,
1G,

2H,
8F,
4F,
1F,

3H,
9G,
7G,
3G,

4H, 6H, 7H, 8H, 9H,
9F,
7F,
3F,

TEST DESCRIPTION:
The detection RAMs address integrity is functionally tested by clearing all
locations of each RAM, then writing a 4 bits nibble (1010B) into the asserted
address. The RAM address is then verified by reading the (ADVANCE, JUMP, STOP,
TRACE) nibble from all locations and comparing the result to the nibble OAH.
The detection

~~s

tested are:

8G, 8F, 9G, 9F, 4G, 4F, 7G, 7F, 1G, 1F, 3G and 3F.
There are 8 address bits for each detection RAM, consisting of low nibble from
levels and high nibble from sample registers of Data Boards.

TEST STEP INFORMArION:
Test Step
1 through 8
9 through 16
17 through 24
25 through 32
33 through 40
41 through 48
49 through 56
57 through 64
65 through 72
73 through 80
81 through 88
89 through 96

RAU Chip Location
8G(00)
8F(01)
9G(02)
9F(03)
4G(04)
4F(05)
7G(06)
7F(07)
1G(08)
1F(09)
3G( 10)
3F(11)

Asserted Address Bit
01H,02H,04H,08H,10H,20H,40H,80H
01H,02H,04H,08H,10H,20H,40H,80H
01H,02H,04H,08H,10H,20H,40H,80H
01H,02H,04H,08H,10H,20H,40H,80H
01H,02H,04H,08H,10H,20H,40H,80H
01H,02H,04H,08H,10H,20H,40H,80H
01H,02H,04H,08H,10H,20H,40H,80H
01H,02H,04H,08H,10H,20H,40H,80H
01H,02H,04H,08H,10H,20H,40H,80H
01H,02H,04H,08H,10H,20H,40H,80H
01H,02H,04H,08H,10H,20H,40H,80H
01H,02H,04H,08H,10H,20H,40H,80H

5-60

ERROR MES SAGE:
If an error occurs, the following message is displayed:
*TEST FAILED -- TEST STEP zz
Detection RAMs Address Integrity Test
RAM Chip Location
= cc
High Nibble Related to Data Board B
Address Expected
= ddH
Address Found
= ffH
AJST/ Nibble Expected = nnH
AJST/ Nibble Read
= rrH
Where cc should be 00 through 11
b should be A,B,C
dd should be 00 through FF
ff should be 00 through FF
nn should be OA,05,OC,03,01,02,04,08
rr should be 00 through FF

NOT!: AJST is the abbreviation of ADVANCE. JUMP, STOP, TRACE nibble.

5-61

Control Board Diagnostic Subtest 5

TITLE:

DELAY CONTROL RAM DATA INTEGRITY TEST

TARGET LOGIC:

13A, 12C, 12G, 12H

TEST DESCRIPTION:
The Delay Control RN1 data integrity is functionally tested by writing a four
bits nibble into the delay control RAM, the RAM data is then verified by
reading the (EVENT MODE, END LEVEL, (D=l IF JUMP)/, (D=l IF ADVANCE)/) nibble
from bit 14 of port OFEH, OFCH, OFAR, OF8H and compare the result to the
nibble written.
There are 8 nibble patterns as follows:
1010B, 0101B, 1100B, 0011B, 0001B, 0010B, 0100B, 1000B

TEST STEP INFORMATION:
Test Step
1
2
3
4
5
6
7

8

Nibble Pattern

Levels

1010B
0101B
1100B
0011B
0001B
0010B
0100B
1000B

0
0
0
0
0
0
0
0

through
through
through
through
through
through
through
through

OFH
OFH
OFH
OFH
OFH
OFH
OFH
OFH

ERROR MES SAGES:
If an error occurs, the following message is displayed:

* Test FAILED -- Test Step zz
Delay control RAM Data Integrity Test
RAM Address
= aaH
Nibble Expected
eeH
Nibble Read
= rrH
Error Bit Map
= xxxxxxxxB
Where aa should be 00 through OF
ee should be OA,05,OC,03,01,02,04,08
rr should be 00 through OF
xxxxxxxx should be 00000000 through 00001111

5-62

Control Board Diagnostic Subtest 6

TITLE:

DELAY CONTROL RAM ADDRESS INTEGRITY TEST

TARGET LOGIC:

13A, 12C, 12G, 12H

TEST DESCRIPTION:
The Delay Control ~~ address integrity is functionally tested by writing a
four bits nibble (lOlOB) into the asserted address. The address is then
verified by reading nibble data from all 16 locations,and comparing the result
to the nibble expected (1010B).

TEST STEP INFORMATION:
Test Step

Nibble Pattern

Asserted Address

1010B
1010B
1010B
1010B

0001B
0010B
0100B
1000B

1

2
3
4

BRROR MES SAGBS :
If an error occurs, the following message is displayed:
*TEST FAILED -- TEST STEP zz
Delay control RAM Address Integrity test
Address Expected = eeH
Address Found
= ffH
Nibble Expected = nnH
Nibble Read
= rrH
Where zz should be 1 through 4
ee should be 01,02,04,08
ff should be 00 through FF

nn should be OA.
rr should be 00 through OF

5-63

Control Board Diagnostic Subtest 7
TITLE:

DELAY RAMS DATA INTEGRITY TEST

TARGET LOGIC:

l4C, l4D, l4E, l4F, l3C, l3D, l3E, l3F
llC, llB, l2D, l2E, l2G, l2H

TEST DESCRIPTION:
The Delay RAMS data integrity is functionally tested by writing a word pattern
into the delay RAMs. The word data of RAMs is then loaded into the delay
counter. The data integrity is then verified by reading the word data and
comparing the result to the word expected.
There are 8 delay word patterns tested as follows:

AAAAH, 5555H, CCCCH, 3333H, llllH, 2222H, 4444H, 8888H.
TEST STEP INFORMATION:
Test Step

Word Pattern Tested

1

AAAAH

2
3
4
5

5555H
CCCCH
3333H
llllH
2222H
4444H
8888H

6
7
8

InOll MESSAGES:
If an error occurs, the following message is displayed:
*TEST FAILED -- TEST STEP zz
Delay RAM Data Integrity Test
RAM Address
- aaH
Word Expected - eeeeH
Word Read
- rrrrH
Error Bit Map - xxxxxxxxxxxxxxxxB
Where zz should be 1 through 8.
aa should be 00 through OF
eeee should be AAAA,5555,CCCC,3333,1111,2222,4444,8888
rrrr should be 0000 through FFFF
xxxxxxxxxxxxxxxx should be 0000000000000000 through 1111111111111111

5-64

Control Board Diagnostic Subtest 8
DELAY RMIS ADDRESS INTEGRITY TEST

TITLE:
TARGET LOGIC:

14C, 14D, 14E, l4F, l3C, 13D, l3E, l3F
IlC, lIB, l2D, l2E, l2G, l2H

TEST DESCRIPTION:
The Delay RM1s address integrity is functionally tested by writing a word
(OAAAAH) into the asserted level address. The delay RAM is then loaded into
the delay counter, and the address integrity is verified by reading the delay
count from all level addresses and comparing the result to the word OAAAAH.
There are 4 address bits tested are:
OOOIB, OOIOB, OlOOB, 1000B
TEST STEP INFORMATION:
Test Step

Word Pattern Tested

1

MAAH

2
3
4

AAAAH
AAAAH

Asserted Level Address
0001B
OOIOB
OIOOB
1000B

AAAAH

ERROR MES SAGES:

If an error occurs, the following message is displayed:
*TEST FAILED -- TEST STEP zz
Delay RAM Address Integrity Test
Address Expected = aaH
Address Found
= ffH
Word Expected
= eeeeH
Word Read
= rrrrH
Where zz should be 1 through 4.
aa should be 01,02,04,08
ff should be 00 through OF
eeee should be AAAA.
rrrr should be 0000 through FFFF

5-65

Control Board Diagnostic Subtest 9

TITLE:

DELAY COUNTER TEST

TARGET LOGIC:

14C, 14D, 14E, 14F, 13C, 13D, 13E, 13F
11 C, 11 B, 12D, 12E, 12G, 12R

TEST DESCRIPTION:
The Delay Counter is functionally tested by writing a delay word into the
delay RAMs and loading it into the delay counter. The counting operation is
then verified by kicking clocks, reading the delay count and comparing the
result to the word expected.
The counting operation is verified by the following two methods:
1.

Kick clocks until delay count is equal to O.

2.

Kick a clock to increment only one count.

The delay count word patterns being tested are as follows:

SOOOR, 4000H, 2000R, 1000R, OSOOR, 0400R, 0200R, OIOOR,
OOSOR, 0040R, 0020R, OOIOR, 0008R, 0004R, 0002R, OOOIR.

TEST STEP INFORMATION:
Test Step

I
2
3

4
5
6
7
S
9
10
11
12
13
14
15
16
17
18
19
02
21
22
23
24

Word Pattern Tested

SOOOR
SOOOR
4000R
4000R
2000R
2000R
1000R
1000R
0800R
0800R
0400R
0400R
0200R
0200R
0100R
0100R
0080R
0080R
0040R
0040R
0020R
0020R
0010R
OOIOR

Clocks to Kick

SOOOR
I
COOOR
I
EOOOR
1
FOOOR
1
FSOOR
1
FCOOR
1
FEOOR
1
FFOOR
1
FF80R
1
FFCOR
1
FFEOR
1
FFFOR
1
5-66

Expected Count

0
SOOIR
0
400lH
0
200lR
0
100lR
0
0801R
0
0401R
0
0201R
0
0101R
0
OOSlR
0
0041R
0
0021R
0
OOllH

Test Step
(Cont'd)

Word Pattern Tested

FFF8H
1
FFFCH
1
FFFEH
1
FFFFH
1

0008H
0008H
0004H
0004H
0002H
0002H
0001H
0001H

25
26
27
28
29
30
31
32

Clocks to Kick

Expected

Count

0
0009H
0
OOOSH
0
0003H
0
0002H

ERROR MESSAGES:

If an error occurs, the following message is displayed:
*TEST
Delay
Count
Count
Count
Error

FAILED -- TEST STEP zz
Counting Operation Test
Pattern = ccccH
Expected = eeeeH
= rrrrH
Read
Bit Map = xxxxxxxxxxxxxxxxB

Where zz should be 1 through 32
cccc should be 8000, 4000, 2000, 1000, 0800, 0400
0200, 0100, 0080, 0040, 0020, 0010
0008, 0004, 0002, 0001
eeee should be 8000, 4000, 2000, 1000, 0800, 0400, 0200, 0100
0080, 0040, 0020, 0010, 0008, 0004, 0002, 0001, 0
rrrr should be 0000 through FFFF
xxxxxxxxxxxxxxxx should be 0000000000000000 through 1111111111111111

5-67

Control Board Diagnostic Subtest 10
TITLE:

RELATION LOGIC TEST

TAIQET LOGIC:

12B, 14B, 12A, 13A, 11A, 11F, 11C, 11B, 11D, 9B, 12F

TEST DESCRIPTION:
The Relation Logic is functionally tested by making one of the logic paths
true. The relation is then verified by reading the desired relation bit and
comparing the result to the expected logic state.
The Boolean function of each logic path is:
Path 1
P1
(old T < D)*(advanced + jumped)*(evented)*(TC)
Path 2
P2
(jumped)*(D = 1 If Jumped)
Path 3
P3
(advanced)*(D = 1 If advanced)*(jumped /)
Path 4
P4
(old T = D)*(evented /)*«advanced + jumped) /)
Path 5
P5 = (old T = D)*(evented)*«advanced + jumped) /)
Path 6
P6
(old T > D)*«advanced + jumped) /)
(T < D)
NOT (Pl + P2 + P3 + P4 + P5)
(T = D) = Pl + P2 + P3 + P4
(T > D) = P5 + P6
Path
logic means T < D true.

°

TEST STEP INFORMATION
Test Step
1
2

3
4

Logic Path

Relation True
T <
T =
T
T =

0, 1
2
3
4, 5, 6

D then T = D
D
D
D then T > IJ

ERROR MESSAGES:
If an error occurs, the following message is displayed:
*TEST FAILED -- TEST STEP zz
Relation Logic Path p Failed
tiT < DtI Expected := a
tiT < DtI Read
b
tiT = DtI Expected = c
tiT
D" Read
=d
itT > DIf Expected = e
1fT > D" Read
f
Where zz should be 1 through 4.
a, b, c, d, e, f should be

° or 1.
5-68

Control Board Diagnostic Subtest 11

TITLE:

SELECTION RAM DATA INTEGRITY TEST

TARGET LOGIC:

6B, SB, 4B, 7B, 8B, IB, 2B, 3B, 8A, 9A,
5C, 5D, 7C, 4D, 8D, SF, 7D, 1C, 3C, 8C,
9C, 3D, 9B

TEST DESCRIPTION:
The Selection RAMs data integrity is functionally tested by separating all
RAMs into 4 subgroups (ADVANCE, JUMP, STOP, TRACE), writing the specified data
into the RAMS of each subgroup, and verifying the data integrity by reading
the (ADVANCE, JUMP, STOP, TRACE) bits and comparing the result to the nibble
expected.
There are 4 subgroups as follows, being tested:
Subgroup A : bit
bit
bit
bit
bit
bit
bit
bit
Subgroup J

Subgroup S

Subgroup T

bit
bit
bit
bit
bit
bit
bit

0
1
2

3

4
5
6

7
0

1
2

3
4
5
6

bit
bit
bit
bit
bit
bit
bit
bit

0
1

bit
bit
bit
bit
bit
bit
bit
bit

0
1

2
3

4
5
6

7

2
3
4
5
6
7

selection
selection
selection
selection
selection
selection
selection
selection

bit
bit
bit
bit
bit
bit
bit
bit

for
for
for
for
for
for
for
for

ADVANCE A
ADVANCE B
ADVANCE C
(ADVANCE C.B.A)/
ADVANCE if T ) D
ADVANCE if T = 0
ADVANCE if T < D
ADVANCE· if 'x'

selection
selection
selection
selection
selection
selection
selection

bit
bit
bit
bit
bit
bit
bit

for
for
for
for
for
for
for

JUMP A
JUMPB
JUMP C
(JUMP C.B.A)/
JUMP if T > D
JUMP if T = DJUMP if T < D

selection
selection
selection
selection
selection
selection
selection
-- selection

bit
bit
bit
bit
bit
bit
bit
bit

for
for
for
for
for
for
for
for

STOP A
STOP B
STOP C
(STOP C.B.A)/
STOP if T ) D
STOP if T = D
STOP if T < D
STOP if 'x'

selection
selection
selection
selection
selection
selection
selection
selection

bit
bit
bit
bit
bit
bit
bit
bit

for
for
for
for
for
for
for
for

TRACE A
TRACE B
TRACE C
(TRACE C.B.A)/
TRACE if T ) D
TRACE if T = D
TRACE if T < D
TRACE if 'x'

Each bit has logic 0 and logic 1 to be tested.
5-69

TEST STEP INFORMATION:
Test Step

Subgroup

Bit

Mnemonic

Logic State

Related Chip

----------------------------------------------------------------------------1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52

Advance
Advance
Advance
Advance
Advance
Advance
Advance
Advance
Advance
Advance
Advance
Advance
Advance
Advance
Advance
Advance
Jump
Jump
Jump
Jump
Jump
Jump
Jump
Jump
Jump
Jump
Jump
Jump
Jump
Jump
Jump
Jump
Stop
Stop
Stop
Stop
Stop
Stop
Stop
Stop
Stop
Stop
Stop
Stop
Stop
Stop
Stop
Stop
Trace
Trace
Trace
Trace

0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
0
0
1
1

ADVANCE A
ADVANCE A
ADVANCE B
ADVANCE B
ADVANCE C
ADVANCE C
(ADVANCE C.B.A)/
(ADVANCE C.B.A)/
ADVANCE if T > D
ADVANCE if T > D
ADVANCE if T = D
ADVANCE if T = D
ADVANCE if T < D
ADVANCE if T < D
ADVANCE if 'x',
ADVANCE if 'x
Jump A
Jump A
Jump B
Jump B
Jump C
Jump C
(Jump C.B.A)/
(Jump C.B .A) /
Jump if T > D
Jump if T > D
Jump if T = D
Jump if T = D
Jump if T < D
Jump if T < D
None
None
Stop A
Stop A
Stop B
Stop B
Stop C
Stop C
(Stop C.B.A)/
(Stop C.B.A)/
Stop if T > D
Stop if T > D
Stop if T = D
Stop if T = D
Stop if T < D
Stop if T < D
Stop if 'x'
Stop if 'x'
Trace A
Trace A
Trace B
Trace B
5-70

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
x
x

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

0
1

-

4B-D3
4B-D3
5B-D2
5B-D2
5B-D3
5B-D3
5B-Dl
5B-Dl
6B-D2
6B-D2
6B-DO
6B-DO
6B-D3
6B-D3
6B-D1
6B-D1
8B-D2
8B-D2
8B-D3
8B-D3
4B-DO
4B-DO
4B-D2
4B-D2
7B-D3
7B-D3
7B-D1
7B-D1
7B-D2
7B-D2
None
None
3B-D2
3B-D2
2B-DO
2B-DO
2B-D2
2B-D2
1B-D1
1B-D1
1B-DO
1B-DO
1B-D3
1B-D3
1B-D2
1B-D2
2B-D3
2B-D3
9A-DO
9A-DO
8A-D2
8A-D2

53
54
55
56
57
58
59
60
61
62
63
64

Trace
Trace
Trace
Trace
Trace
Trace
Trace
Trace
Trace
Trace
Trace
Trace

2
2
3
3
4
4
5
5
6
6
7
7

Trace C
Trace C
(Trace C.B.A)/
(Trace C.B.A)/
Trace if T > D
Trace if T > D
Trace if T D
Trace if T D
Trace if T < D
Trace if T < D
Trace if'x',
Trace if'x

ERROR MESSAGES:

If an error occurs, the following message is displayed:
*TEST FAILED -- TEST STEP zz
Selection RAMs Data Integrity
Subgroup g Bit b Testing
RAt! Address = aaH
AJST/ Nibble Expected = nnH
AJST/ Nibble Read = rrH
Error Bit Map = xxxxxxxxB
Where zz should be 1 through 64
g should be A, J, S, T.
b should be

o or

1.

aa should be 00 through OF.
nn should be 08, 04, 02, 01, 0
rr should be 00 through OF
xxxxxxxx should be 00000000 through 00001111

5-71

0
1
0

1
0

1
0

1
0

1
0

1

8A-DO
8A-DO
8A-Dl
8A-Dl
9A-D2
9A-D2
9A-D3
9A-D3
3B-DO
3B-DO
3B-D1
3B-Dl

Control Board Diagnostic Subtest 12
SELECTION RAM ADDRESS INTEGRITY TEST

TITLE:

6B, 5B, 4B, 7B, 8B, 1B , 2B , 3B, 8A , 9 A,
5C, 5D, 7C, 4D, 8D, SF, 7D, lC, 3C, 8C,
9C, 3D, 9B

TARGET LOGIC:

TEST DESCRIPTION:
The Selection RAMS address integrity is functionally tested by separating all
RAMs into 4 subgroups (ADVANCE, JUMP, STOP, TRACE), clearing all locations of
selection RAMs, going to the asserted level address, and writing bit 0 into
the R&~S of each subgroup.
The address integrity is then verified by reading
the (ADVANCE, JUMP, STOP, TRACE) bits from all locations.
There are 4 subgroups as follows, being tested:
Subgroup
Subgroup
Subgroup
Subgroup

A
J
S
T

bit
bit
bit
bit

0
0
0
0 --

selection
selection
selection
selection

bit
bit
bit
bit

for
for
for
for

ADVANCE A
JUMP A
STOP A
TRACE A

Each bit only test logic O.
TEST STEP INFORMATION:
Test Step
1

2
3
4
5
6
7
8
9

10
11
12
13
14
15
16

Subgroup

Bit

Mnemonic

Advance
Advance
Advance
Advance
Jump
Jump
Jump
Jump
Stop
Stop
Stop
Stop
TRACE
TRACE
TRACE
TRACE

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

ADVANCE
ADVANCE
ADVANCE
ADVANCE
JUMP A
JUMP A
JUMP A
JUMP A
STOP A
STOP A
STOP A
STOP A
TRACE A
TRACE A
TRACE A
TRACE A

5-72

Logic State
A
A
A
A

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

Level Address
01R
02R
04R
08R
OlR
02R
04H
08H
OlH
02H
04H
08H
01H
02H
04H
08H

ERROR MES SAGES:

If an error occurs, the following message is displayed:
*TEST FAILED -- TEST STEP zz
Selection RAMs Address Integrity
Subgroup g Testing
Address Expected
eeR
Address Found
ffR
AJST/ Nibble Expected
nnR
AJST/ Nibble Read
= rrR
Where zz should be 1 through 16
g should be A, J, S, T.
ee should be 01, 02, 04, 08
ff should be 00 through OF
nn should be 08, 04, 02, 01
rr should be 00 through OF

5-73

K450 CLOCK BOARD DIAGNOSTIC
DIAGNOSTIC OVERVIEW
This section describes subtests that are performed by the K450 Clock Board
Diagnostic.
The target hardware is presented, as well as a general
description of each Subtest, a list of information for each Test Step, and
Error Hessages that may be printed.
The K450 Clock Board Diagnostic is a
the K450 Diagnostic Operating System.
the Clock Board except for J2, which
hardware that is not tested is a 4028
lOB, and the cable going to the front

board level Diagnostic which runs under
The Diagnostic verifies all functions of
presents clocks to the front panel. The
Multiplexer/Driver at 9B, two drivers at
panel.

The Diagnostic Tests that are performed can be divided into five sections
described below.

as

The first is the Force Conditions Test. This test is a series of simple
operations that are performed on the Clock Board.

I/O

The second is the Sample and Control Clock testing. These clocks move data on
the Data Boards.
Specifically, the Sample Clock clocks the Data Board's
Sample Registers, and the Control Clock clocks the Data Board's Pipeline.
The third is the Latch Clock testing. The Latch Clocks also clock data on the
Data Boards, but in a special latch mode where data is latched before it
reaches the Data Board's Sample Registers.
The fourth is the Frequency testing. All seven decades from the lOOMhz Clock,
down to the 100 Hz Clock are tested. The Clock Board Multiplier is tested to
see if it can actually perform a divide by function, thus slowing down the
clock rate.
The fifth and final is the testing of the Level RAM.
The RAM is tested
Data integrity, Addressing integrity, and control logic functionality.

for

The Diagnostic uses Data Boards A, Band C extensively to check out the
clocking features.
The Diagnostic also requires the use of the Control Board
and the Threshold Board.
All of these boards must be functional for any
realistic pinpointing of possible failures. All six of the external probes
must be installed, with floating inputs (no connection).
If Data Board C is not installed, (unit contains 32 input channels), the C
section clocks of the Clock Board is not tested, and the following message is
displayed:
)Testing sections A & B, cannot test section C.
This message informs the operator that the A and B sections are being tested,
but there is insufficient hardware in the system to diagnose section C. All
six probes must still be installed to properly test sections A and B.
The type of tests that are performed on the Clock Board are static type tests.

5-74

The tests verify the functionality and individuality of mUltiplexers and gates
but do not perform real time testing on the board.
Therefore, if racing
conditions exist, or if problems occur with propagation delays, the Diagnostic
will probably not detect them.
Also, the frequency test that is performed on the Clock Decades is a ballpark
test, and does not verify that the 100 ~fuz source clock is exactly 100.00 Mhz.
This must be adjusted/verified with a acope or frequency counter.
The Clock Board provides very little status information to monitor the Modes
or selections. Of the 133 Command Output Bits, the Clock board only provides 4
Status Input Bits.
If multiple failures exist on a board under test, the problem might originate
in the I/O port decoding and data latching.
This portion of the board is
initially assumed to be functional.
If it is not funtional, very few if any
tests will pass.
DESCRIPTION OF DATA BOARD REGISTERS USED TO TEST CLOCK BOARD

The Sample Clocks, Latch Clocks and Control Clocks are tested using the K450
Data Boards. The Data Boards are also used for the Frequency tests.
A simple outline of the registers on the Data Boards is as follows:

1.

Data Boards Diagnostic Latch Register.
Data Board A - Write Port OCOR. (cannot read this port back)
Data Board B - Write Port ODOR. (cannot read this port back)
Data Board C - Write Port OEOR. (cannot read this port back)
This Latch is the "Front End" to the Data Board's Data Path. Data is
placed in this register by simply performing an OUTWORD instruction.

2.

Data Boards Sample Registers.
Data Board A - Read Port OC6H.
Data Board B - Read Port OD6R.
Data Board C - Read Port OE6R.

(cannot write directly to this port)
(cannot write directly to this port)
(cannot write directly to this port)

Data is transfered from the Data Board's Diagnostic Latch Registers
to the Data Board's Sample Register when a Sample Clock is issued.
Sample Register A requires Sample Clock A, Sample Register B requires
Sample Clock B, and Sample Register C requires Sample Clock C. This
transfer takes place assuming the Data Board is not in Latch mode.
3.

Data Boards New Pipe Registers.
Data Board A - Read Port OC4H.
Data Board B - Read Port OD4R.
Data Board C - Read Port OD4H.

(cannot write directly to this port)
(cannot write directly to this port)
(cannot write directly to this port)

Data is transferred from the Data Boards Sample Registers to
Data Boards New Pipe Registers when a Control Clock is issued.
5-75

the

Data
4.

Boards A, Band C all use a single Control Clock for transfer.

Latch Mode on the Data Boards.
When the Data Boards are in Latch Hade, an extra Data latch is
present between the Diagnostic Latch Registers and the Sample
Registers. A Latch Clock is required to transfer Data.
In Latch Mode, the following sequence is required to place Data into
the Data Board's Sample Registers.
Output the desired Data to the Diagnostic Latch Registers.
This
presents the Data to the input of the "Latch" mode Registers.
Issuing a Latch Clock presents this Data to the input of the Sample
Registers.
Issuing a Sample Clock latches this Data in the Sample
Registers.
Data Board A requires Latch Clock A, Data Board B
requires Latch Clock B, and Data Board C requires Latch Clock C.

SUBTEST CATEGORIES
There are fourteen subtests performed by the Clock Board
tests are as follows:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.

Diagnostic.

These

Force Conditions Test
Sample and Control Clocks, Diagnostic Internal Clock Test
Sample and Control Clocks, OR-only Enables Test
Sample Clocks, IOns Clock Test
Sample and Control Clocks, AJ, BJ and CJ Clocks Test
Sample and Control Clocks, AK, BK and CK Clocks Test
Latch Clocks, Diagnostic Internal Clock Test
Latch Clocks, Diagnostic OR-only Enables Test
Latch Clocks, AR, BR and CR Clocks Test
Latch Clocks, AS, BS and CS Clocks Test
Decade Frequency and Multiplier Divide oy Test
Level RAMs Data Integrity Test
Level RAMs Address Integrity Test
Level RAMs Control Test

ERROR COUNT CATEGORIES
The Error Count Display information is a one for one match with the subtest
above.
The K450 Diagnostic Operating System displays the message Subtest n
instead of the actual test name (where n = Subtest Number).
Subtest
Subtest
Subtest
Subtest
Subtest
Subtest
Subtest
Subtest
Subtest

1
2
3
4
5
6
7
8
9

(Force Conditions)
(Sample and Control Clocks, Diagnostic Internal)
(Sample and Control Clocks, OR-only Enables)
(Sample Clocks, IOns Clock Test
(Sample and Control Clocks, AJ, BJ and CJ)
(Sample and Control Clocks, AK, BK and CK)
(Latch Clocks, Diagnostic Internal)
(Latch Clocks, Diagnostic OR-only Enables)
(Latch Clocks, AR, BR and CR)
5-76

Subtest
Subtest
Subtest
Subtest
Subtest

10
11
12
13
14

(Latch Clocks, AS, BS and CS)
(Decade Frequency and Multiplier)
(Level RAMs Data Integrity)
(Level RA~s Address Integrity)
(Level RAHs Control)

5-77

Clock Board Diagnostic Subtest 1

TITLE:

FORCE CONDITIONS TEST

TARGET LOGIC:

7 J, 6J, 8J, 10K,
11K, 12J, 6K, 9K, 9J, llH
lOR
lOG, 10F, 9F, 11K,
5J

TEST DESCRIPTION:
This test issues commands to the Clock Board and expects to see certain status
conditions existing.
Commands are issued by writing to port OBEH, and the
Status is read back from port OB2R.
Since the Clock Board only provides 4 status bits for all of the 113 command
bits, only a fraction of the I/O read/write/control logic is actually tested.
If there are errors in this test, the I/O decode logic and/or data latches may
be faulty, and the succeeding tests probably has multiple errors.

TEST STEP INFORMATION:
Step
1
2
3
4
5

Expected Status
AOOOH
2000H

OOOOH
6000B, 7000H
7000H

ERROR MESSAGES:
If an error occurs, the following message is displayed:

* Test FAILED--Test Step ssss
Force Conditions/Status Error
No Clocking used
I/O Address
~ aaaaH
Status Read
~ rrrrH
Status Expected = eeeeR

5-78

Where:
ssss

is the Test Step in the range of 1 to 5.

aaaa

is the address of the Clock Board Status Register, OOB2H.

rrrr

is the Data Word read from the Status Register.

eeee

is the Data Word expected from the Status Register.

NOT!:
With the limited amount of status bits on the Clock Board, it is
difficult to pin point the cause of an error.
Whether the fault lie8 with an
address decoder, a Data Bit Driver or Latch, the fault can be determined by
using a Logic Analyzer or Scope, and setting the Loop On Error Option.

5-79

Clock Board Diagnostic Subtest 2
SAMPLE AND CONTROL CLOCKS, DIAGNOSTIC INTERNAL CLOCK TEST

TITLE:

7A,
7D,
7F,
IIR,
laC
lIB
3E,

TARGET LOGIC:

8A,
8D,
8F,
laD,

lOR,
IOJ,
7G,
12C,

7B, 8B, 9G
7E, 8E, 9R
8G, 7R, 8R
IIC

3F,

3G,

3R, 4R, 4J, 4C, 4D

TEST DESCRIPTION:
The Diagnostic Internal Sample Clocks A, Band C, and the Diagnostic Internal
Control Clock tests for functionality and uniqueness, as well as the ability
to disable these Clocks using the Threshold Disable, and the Force Disqualify
Disable.
The Sample Clocks are tested by placing Data at the Front End of the Data
Board, issuing a Diagnostic Internal Sample Clock, and checking the Sample
Registers to see if a Data transfer took place.
The Control Clocks are similarly tested by clocking data into the Sample
Registers, issuing a Diagnostic Internal Control Clock, and checking the New
Pipe Registers to see if a Data transfer took place.
NOTE: The Diagnostic Internal Clock is kicked by outputing a 1 to bit DO of
Write Registers OBSH of the Clock Board. This produces a clock pulse the width
of the 8086's Write pulse. Consecutive kicks are achieved by consecutive
outputs to this port. It is never necessary to set this bit low.
TEST STEP INFORMATION:
Step

Data

Clock Tested

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

OOOOR
5555H

Sample A,
Sample A,
Sample A,
Sample A,
Sample A,
Sample A,
Sample A,
Sample A,
Control
Control
Control
Control
Control
Control
Control
Control

AMAH

CCCCH
3333H
6666H
9999H
FFFFH
OOOOH
5555H
AMAR
CCCCH
3333R
6666H
9999H

FFFFH

B,
B,
B,
B,
B,
B,
B,
B,

Data Verified at
C
C
C
C
C
C
C
C

Sample Registers A, B, C
Sample Registers A, B, C
Sample Registers A, B, C
Sample Registers A, B, C
Sample Registers A, B, C
Sample Registers A, B, C
Sample Registers A, B, C
Sample Registers A, B, C
New Pipe Registers A, B,
New Pipe Registers A, B,
New Pipe Registers A, B,
New Pipe Registers A, B,
New Pipe Registers A, B,
New Pipe Registers A, B,
New Pipe Registers A, B,
New Pipe Registers A, B,

5-80

C
C
C
C
C
C
C
C

Uniqueness Test:
Step

A Data

B Data

C Data

Clock Tested

Data Verified at

------------------------------------------------------------------------17
OOOOR
OOOOR
Sample A
AAAAH
Sample Registers
C
18
19
20
21
22
23
24
25

OOOOR
OOOOR
AAAAH.
AAAAH.
AAAAH.
AAAAH
AAAAH
AAAAH.

BBBBR
OOOOR
BBBBR
BBBBR
BBBBR
BBBBR
BBBBR
BBBBR

OOOOR
CCCCR
CCCCR
CCCCH
CCCCR
CCCCR
CCCCR
CCCCR

Sample B
Sample C
Control
Control
Control
Control
Control
Control

A, B,
Sample Registers A, B, C
Sample Registers A, B, C
Sample Registers A, B, C
Sample Registers A, B, C
Sample Registers A, B, C
New Pipe Registers A, B, C
New Pipe Registers A, B, C
New Pipe Registers A, B, C

NOTE: Test Steps 20 - 22 verify the Control Clock does not change the contentl
of the Sample Registers.
Test Steps 23 - 25 verify the Control Clock can latch Data into the New
Pipe Registers with all Sample Clocks disabled.
Disable Test
Step

A

26
27
28
29
30
31

AAAAH.

Data

B Data

C Data

Clock Tested

Data Verified at

OOOOR

Sample A
Sample B
Sample C
Control
Control
Control

Sample Register A
Sample Register B
Sample Register C
New Pipe Register A
New Pipe Register B
New Pipe Register C

C Data

Clock Tested

Data Verified at

Sample A
Sample B
Sample C
Control
Control
Control

Sample Register A
Sample Register B
Sample Register C
New Pipe Register A
New Pipe Register B
New Pipe Register C

BBBBR
CCCCR
OOOOR
OOOOR

Porce Disqualify Test:
Step

A Data

32
33
34
35
36
37

AAAAH.

B Data
BBBBH

CCCCH
OOOOH
OOOOR
OOOOH

ERROR MESSAGES:
If an error occurs, the following message is displayed:

* Test

FAILED--Test Step
cccc Clock tttt Error
Diagnostic Internal Clock
I/O Address
= aaaaH
Status Read
= rrrrH
Status Expected = eeeeR

ssss

5-81

Pipe

Where:
ssss is the Test Step in the range: 1 to 37.
cccc is the tested Clock: Sample A,
Sample B,
Sample C,
Control.
tttt is the test type:

Functional,
Uniqueness,
Disable,
Force Disqualify

aaaa is the address of a Data Board Sample Register:
OC6H for Data Board A,
OD6H for Data Board B,
OE6H for Data Board C.
or a Data Board New Pipe Register:
OC4H for Data Board A,
OD4H for Data Board B,
OE4H for Data Board C.
rrrr is the Data Word read from the Status Register.
eeee is the Data Word expected from the Sample Register which should be:
OOOOH,
5555H,
AAAAH,

CGGGH,
3333H,
6666H,

9999H,
FFFFH.

NOTE: OOOOH
Testing.

is

the

expected Data Word for Data

5-82

Boards

during

Uniqueness

Clock Board Diagnostic Subtest 3
SAMPLE AND CONTROL CLOCKS OR-ONLY ENABLES TEST

TITLE:

sE, SF, sG, 5H, 4H, 4J, 4C, 4D

TARGET LOGIC:

Setup Latches in Subtest 2
TEST DESCRIPTION:
The Sample Clocks A, Band C, and Control Clock's OR-Only Enable bits are
tested for functionality and uniqueness, as well as the ability to disable
these Clocks using the Force Disqualify Disable test.
The Sample Clocks are tested by placing Data at the Front End of the Data
Board, issuing a Sample Clock by toggling the OR-Only Enable bit, and checking
the Sample Registers to see if a Data transfer took place.
The Control Clocks are similarly tested by clocking data into the Sample
Registers, issuing a Control Clock by toggling the OR-only Enable bit, and
checking the New Pipe Registers to see if a Data transfer took place.
TEST STEP INFORMATION:
Functionality Test:
Step
1
2
3

Data

Clock Tested

Data Verified at

AAAAH

Sample A
Sample B
Sample C
Control
Control
Control

Sample Register A
Sample Register B
Sample Register C
New Pipe Register A
New Pipe Register B
New Pipe Register C

BBBBH
CCCCH

4

AAAAH

5

BBBBH
CCCCH

6

Uniqueness Test:
Step

A Data

B Data

C Data

Clock Tested

Data Verified at

7

AAAAH

OOOOH

8

OOOOH
OOOOH

BBBBH

OOOOH
OOOOH

AAAAH
AAAAH

BBBBH
BBBBH

Sample A
Sample B
Sample C
Control
Control

Sample Registers A,
Sample Registers A,
Sample Registers A,
New Pipe Registers
New Pipe Registers

9
10
11

OOOOH

CCCCH
CCCCH
CCCCH

5-83

B,
B,
B,
A,
A,

C
C
C
B, C
B, C

Porce Disqualify Test:
Step

A Data

12
13
14
15
16
17

AMAH

B Data

C Data

BBBBH
CCCCH
OOOOH
OOOOH
OOOOH

Clock Tested

Data Verified at

Sample A
Sample B
Sample C
Control
Control
Control

Sample Register A
Sample Register B
Sample Register C
New Pipe Register A
New Pipe Register B
New Pipe Register C

BR.R.OR MESSAGES:
If an error occurs, the following message is displayed:

* Test FAILED--Test Step
cccc Clock tttt Error
OR Only Enables
I/O Address
aaaaH
Status Read
= rrrrH
Status Expected = eeeeH

ssss

Where:
ssss is the Test Step in the range: 1 to 17.
cccc is the tested Clock: Sample A,
Sample B,
Sample C,
Control.
tttt is the test type:

Functional,
Uniqueness,
Force Disqualify.

aaaa is the address of a Data Board Sample Register:
OC6H for Data Board A,
OD6H for Data Board B,
OE6H for Data Board C.
or a Data Board New Pipe Register:
OC4H for Data Board A,
OD4H for Data Board B,
OE4H for Data Board C.
rrrr is the Data Word read from the Status Register.
eeee is the Data Word expected from the Sample Register which should
be:

A, (OC6H, OC4H) •
BBBBH for Data Board B, (OD6H, OD4H) •
CCCCH for Data Board C, (OE6H, OE4H) •

AMAH for Data Board

5-84

NOT!:

OOOOH is the expected data word for all Data Boards during Uniqueness

Testing.

5-85

Clock Board Diagnostic Subtest 4
SAMPLE CLOCKS t 10ns CLOCK TEST

TITLE:
TARGET LOGIC:

SEt SF, SG, 4H, 4J, 4C, 40

Setup Latches in Subtest 2
TEST DESCRIPTION:
The Sample Clocks A, B, C, and 10ns Clock Enable bit are tested for
functionality and uniqueness, as well as the ability to disable these Clocks
using the Force Disqualify Disable.
The Sample Clocks are tested by placing Data at the Front End of the Data
Board, toggling the IOns Enable bit, and then checking the Sample Registers to
see if a Data transfer took place.
NOTE: The IOns Enable bit is toggled active then inactive with two consecutive
output instructions by the 8086 CPU.
Since the 100Mhz Clock is so fast
compared to the execution speed of the 8086, many Sample Clocks occur during
the short period that the IOns Enable is active. This does not cau.. a
problem, since the Sample Register cannot overflow.
TEST STEP INFORMATION:
Functionality Test:
Step
1

2
3

Data

Clock Tested

Data Verified at

AAAAH
BBBBH

Sample A
Sample B
Sample C

Sample Register A
Sample Register B
Sample Register C

B Data

C Data

Clock Tested

Data Verified at

Sample A
Sample B
Sample C

Sample Registers A, B, C
Sample Registers A, B, C
Sample Registers A, B, C

CCCCH

Uniqueness Test:
Step

A Data

4
5
6

AAAAH

OOOOH

OOOOH
OOOOH

BBBBH

OOOOH
OOOOH

OOOOH

CCCCH

5-86

Foree Disqualify Test:
Step

A Data

7
8
9

AAAAH

B Data

C Data

Clock Tested

Data Verified at

CCCCH

Sample A
Sample B
Sample C

Sample Register A
Sample Register B
Sample Register C

BBBBH

ERROR MESSAGES:

If an error occurs, the following message is displayed:

* Test

FAILED--Test Step
cccc Clock tttt Error
10 ns Clock
I/O Address
= aaaaH
Status Read
= rrrrH
Status Expected = eeeeH

ssss

Where:
ssss is the Test Step in the range: 1 to 9.
eccc is the tested Clock: Sample A,
Sample B,
Sample C.
tttt is the test type:

Functional,
Uniqueness,
Force Disqualify.

aaaa is the address of a Data Board Sample Register:
OC6H for Data Board A,
OD6H for Data Board B,
OE6H for Data Board C.
rrrr is the Data Word read from the Status Register.
eeee is the Data Word expected from the Sample Register which should be:
AAAAH for Data Board A.

BBBBH for Data Board B.
CCCCH for Data Board C.

NOTE: OOOOH 1s the expected Data Word for all Data Boards during Testing.

5-87

Clock Board Diagnostic Subtest 5

TITLE:

SAMPLE AND CONTROL CLOCKS AJ, BJ, and CJ CLOCKS TEST

TARGET LOGIC:

3E, SE, 3F, SF, 3G, SG, 3H, SH
4H, 4J, 4C, 4D
4E

Setup Latches in Subtest 2

TEST DESCRIPTION:
The AJ, AJ/, BJ, BJ/, CJ and CJ/ clock enables for the Sample Clocks A, B, C
and the Control Clock are tested for functionality and uniqueness as well as
the ability to disable these Clocks using the Threshold Disable, and the Force
Disqualify Disable.
The Sample Clocks are tested by placing Data at the Front End of the Data
Board, issuing a Sample Clock by toggling one of the AJ, BJ, CJ Enables, and
checking the Sample Registers to see if a Data transfer took place.
The Control Clocks are similarly tested by clocking data into the Sample
Registers, issuing a Control Clock by toggling one of the AJ, BJ, CJ Enables,
and checking the New Pipe Registers to see if a Data transfer took place.
The Logic states of AJ. AJ/. BJ. BJI. CJ and CJI are determined by the
current threshold at the probes.
An ECL Threshold. and a VARAIABLE A
Threshold are used to provide the High and Low logic states.
This test
requires the use of the Threshold Board and the probes.

NOTE:

TEST STEP INFORMATION:
Functionality T•• tl
Step
1
2

Data

Clock Tested

AAAAH

Sample A
Sample B
Sample C
Control
Control
Control
Sample A
Sample B
Sample C
Control
Control
Control

3

BBBBH
CCCCH

4
5
6

BBBBH
CCCCH

7
8
9
10
11
12

AAAAH

AAAAH

BBBBH
CCCCH
AAAAH

BBBBH
CCCCH

- AJ/ , BJ/,
- AJ/, BJ/,
- AJ/, BJ/,
- AJ/, BJ/,
- AJ/, BJ/,
- AJ/, BJ/,
- AJ, BJ,
- AJ, BJ,
- AJ, BJ,
- AJ, BJ,
- AJ, BJ,
- AJ, BJ,

Data Verified at
CJ/
CJ/
CJ/
CJ/
CJI
CJI

CJ
CJ
CJ
CJ
CJ
CJ

5-88

Sample Register A
Sample Register B
Sample Register C
New Pipe Register
New Pipe Register
New Pipe Register
Sample Register A
Sample Register B
Sample Register C
New Pipe Register
New Pipe Register
New Pipe Register

A
B
C

A
B
C

Uniqueness Telts
Step

A Data

B Data

C Data

Clock Tested

Data Verified at

----------------------------------------------------------------------

13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36

AAAAH
AAAAH
AAAAH

OOOOR
OOOOH
OOOOR
OOOOR
OOOOH
OOOOR
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH

OOOOR
OOOOR
OOOOR
OOOOH
OOOOR
OOOOR
AAAAH
AAAAH
AAAAH

OOOOH
OOOOH
OOOOR
BBBBR
BBBBR
BBBBR
OOOOR
OOOOR
OOOOR
BBBBR
BBBBR
BBBBH
OOOOR
OOOOH
OOOOH
BBBBH
BBBBR
BBBBR
OOOOR
OOOOH
OOOOH
BBBBH
BBBBH
BBBBH

OOOOR
OOOOH
OOOOR
OOOOR
OOOOR
OOOOH
CCCCR
CCCCR
CCCCR
CCCCH
CCCCR
CCCCH
OOOOH
OOOOH
OOOOR
OOOOR
OOOOR
OOOOR
CCCCH
CCCCH
CCCCR
CCCCH
CCCCR
CCCCH

Sample A - AJ/
Sample A - BJ/
Sample A - CJ/
Sample B - AJ/
Sample B - BJ/
Sample B - CJ/
Sample C - AJ/
Sample C - BJ/
Sample C - CJ/
Control - AJ/
Control - BJ/
Control - CJ/
Sample A - AJ
Sample A - BJ
Sample A - CJ
Sample B -AJ
Sample B - BJ
Sample B - CJ
Sample C -AJ
Sample C - BJ
Sample C - CJ
Control -AJ
Control - BJ
Control - CJ

Sample Registers At
Sample Registers At
Sample Registers At
Sample Registers At
Sample Registers At
Sample Registers At
Sample Registers A,
Sample Registers A,
Sample Registers At
New Pipe Registers
New Pipe Registers
New Pipe Registers
Sample Registers At
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
New Pipe Registers
New Pipe Registers
New Pipe Registers

Bt
at
Bt
Bt
Bt
B,
B,
B,
B,
A,
At
A,
B,
Bt
B,
B,
B,
B,
B,
B,
B,
A,
A,
A,

C
C
C
C
C
C
C
C
C
B,
Bt
Bt
C
C
C
C
C
C
C
C
C
B,
B,
B,

C
C
C

C
C
C

Threshold Disable Test:
Step

A Data

B Data

C Data

Clock Tested

Data Verified at

AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH

BBBBR
BBBBR
BBBBR
BBBBH
BBBBR
BBBBR
BBBBH
BBBBR
BBBBR
OOOOH
OOOOH
OOOOH
BBBBH
BBBBH
BBBBR
BBBBH
BBBBR
BBBBH
BBBBH
BBBBR
BBBBH
OOOOH
OOOOR
OOOOH

CCCCR
CCCCH
CCCCH
CCCCH
CCCCR
CCCCH
CCCCH
CCCCH
CCCCH
OOOOH
OOOOR
OOOOH
CCCCR
CCCCH
CCCCR
CCCCH
CCCCR
CCCCH
CCCCR
CCCCH
CCCCR
OOOOR
OOOOR
OOOOR

Sample A - AJ/
Sample A - BJ/
Sample A - CJ/
Sample B - AJ/
Sample B - BJ/
Sample B - CJ/
Sample C - AJ/
Sample C - BJ/
Sample C - CJ/
Control - AJ/
Control - BJ/
Control - CJ/
Sample A - AJ
Sample A - BJ
Sample A - CJ
Sample B - AJ
Sample B - BJ
Sample B - CJ
Sample C - AJ
Sample C - BJ
Sample C - CJ
Control -AJ
Control - BJ
Control - CJ

Sample Registers A, B, C
Sample Registers A, B, C
Sample Registers A, B, C
Sample Registers A, B, C
Sample Registers A, B, C
Sample Registers A, B, C
Sample Registers A, B, C
Sample Registers A, B, C
Sample Registers A, B, C
New Pipe Registers A, B,
New Pipe Registers A, B,
New Pipe Registers A, B,
Sample Registers A, B, C
Sample Registers A, B, C
Sample Registers A, B, C
Sample Registers A, B, C
Sample Registers A, B, C
Sample Registers A, B, C
Sample Registers A, B, C
Sample Registers A, B, C
Sample Registers A, B, C
New Pipe Registers A, B,
New Pipe Registers A, B,
New Pipe Registers A,B,C

----------------------------------------------------------------

37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60

OOOOH
OOOOH
OOOOH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH

OOOOR
OOOOR
OOOOH

5-89

C
C
C

C
C

Force Disqualify Test:
Step

A Data

B Data

C Data

Clock Tested

Data Verified at

61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84

AAAAH
AAAAH
AAAAH
AAAAH

BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
OOOOH
OOOOH
OOOOH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
OOOOH
OOOOH
OOOOH

CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
OOOOH
OOOOH
OOOOH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
OOOOH
OOOOH
OOOOH

Sample A - AJI
Sample A - BJI
Sample A - CJI
Sample B - AJI
Sample B - BJI
Sample B - CJI
Sample C - AJI
Sample C - BJI
Sample C - CJI
Control - AJI
Control - BJI
Control - CJI
Sample A - AJ
Sample A - BJ
Sample A - CJ
Sample B - AJ
Sample B - BJ
Sample B - CJ
Sample C -AJ
Sample C - BJ
Sample C - CJ
Control -AJ
Control - BJ
Control - CJ

Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
New Pipe Registers
New Pipe Registers
New Pipe Registers
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
New Pipe Registers
New Pipe Registers
New Pipe Registers

AAAAH
AAAAH
AAAAH
AAAAH

AAAAH
OOOOH
OOOOH
OOOOH
AAAAH
AAAAH
AAAAH
AMAH

AMAH
AAAAH

AMAH
AAAAH
AAAAH

OOOOH
OOOOH
OOOOH

ERROR MESSAGES:
If an error occurs, the following message is displayed:

*

Test FAILED--Test Step
cccc Clock tttt Error
qqqq Clock Enables
1/0 Address
= aaaaH
Status Read
= rrrrH
Status Expected = eeeeH

ssss

Where:
ssss is the Test Step in the range: 1 to 84.
cccc is the tested Clock: Sample A,
Sample B,
Sample C,
Control.
tttt is the test type:

Functional,
Uniqueness,
Disable,
Force Disqualify.

5-90

B,
B,
B,
B,
B,
B,
B,
B,
B,
A,
A,
A,
B,
B,
B,
B,
B,
B,
B,
B,
B,
A,
A,
A,

C
C
C
C
C
C
C
C
C
B,
B,
B,
C
C
C
C
C
C
C
C
C
B,
B,
B,

C
C
C

C
C
C

qqqq is the tested Clock Enable: AJ/ BJ/ CJ/ t
AJ BJ CJ t

AJ/ t
BJ/,
CJ/,
AJ,
BJ,
CJ.
aaaa is the address of a Data Board Sample Register:
OC6H
OD6H
OE6H
or a
OC4H
OD4H
OE4H

for Data Board
for Data Board
for Data Board
Data Board New
for Data Board
for Data Board
for Data Board

At
B,
C.
Pipe Register:
A,
B,
C.

rrrr is the Data Word read from the Status Register.
eeee is the Data Word expected from the Sample Register which should be:
AAAAH for Data Board A, (OC6H, OC4H).
BBBBH for Data Board B, (OD6H, OD4H).
CCCCH for Data Board C, (OE6H, OE4H).

NOTE: OOOOH
Testing.

is the expected Data Word for all Data Boards during

5-91

Uniquenes8

Clock Board Diagnostic Subtest 6
SAMPLE AND CONTROL CLOCKS

TITLE:

AK, BK AND CK CLOCKS TEST

SA, 4A, sB, sC, sD, 4C, 4D,
sE, SF, sG, sR, 4H, 4J,

TARGET LOGIC:

6A

Setup Latches in Subtest 2
TEST DESCRIPTION:
The AK, AK/, BK, BK/, CK and CK/ clock enables for the Sample Clocks A, B, C,
and the Control Clock is tested for functionality and uniqueness, as well as
well as the ability to disable these Clocks using the Threshold Disable, and
the Force Disqualify Disable.
The Sample Clocks are tested by placing Data at the Front End of the Data
Board, issuing a Sample Clock by toggling one of the AK, BK, CK Enables, and
checking the Sample Registers to see if a Data transfer took place.
The Control Clocks are similarly tested by clocking data into the Sample
Registers, issuing a Control Clock by toggling one of the AK, BK, CK Enables,
and checking the New Pipe Registers to see if a Data transfer took place.
NOTE: The Logic states of AK. AK/. BK. BK/. CK and CKI are determined by the
current threshold at the probes. An ECL Threshold. and a VARAIABLE A Threshold
il uled to provide the High and Low logic states.
This test requires the use of the Threshold Board, and the probes.
TEST STEP INFORMATION:
Functionality Test:
Step

Data

Clock Tested

1
2
3
4

AAAAH

5
6
7

BBBBH
CCCCH

Sample A
Sample B
Sample C
Control
Control
Control
Sample A
Sample B
Sample C
Control
Control
Control

8

9
10
11

12

BBBBH
CCCCH
AAAAH

AAAAH

BBBBH
CCCCH
AAAAH

BBBBH
CCCCH

Data Verified at

- AK/, BK/, CK/

- AK/, BK/ , CK/
- AK/, BK/ , CK/
- AK/, BK/, CK/
- AK/, BK/,
- AK/, BK/,
- AK, BK,
- AK, BK,
- AK, BK,
- AK, BK,
- AK, BK,
- AK, BK,

CK/
CK/
CK
CK
CK
CK
CK
CK

5-92

Sample Register A
Sample Register B
Sample Register C
New Pipe Register
New Pipe Register
New Pipe Register
Sample Register A
Sample Register B
Sample Register C
New Pipe Register
New Pipe Register
New Pipe Register

A

B
C

A

B
C

Uniqueness Test:
Step

A Data

B Data

C Data

Clock Tested

Data Verified at

----------------------------------------------------------------------

13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
-33
34
35
36

AAAAR

AAAAH
AAAAH

OOOOR
OOOOR
OOOOR
OOOOR
OOOOR
OOOOR
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH

OOOOR
OOOOR
OOOOR
OOOOR
OOOOR
OOOOR
AAAAH
AAAAH
AAAAH

OOOOR
OOOOR
OOOOR
BBBBR
BBBBR
BBBBR
OOOOR
OOOOR
OOOOR
BBBBR
BBBBR
BBBBR
OOOOR
OOOOR
OOOOR
BBBBR
BBBBR
BBBBR
OOOOR
OOOOR
OOOOR
BBBBR
BBBBR
BBBBR

OOOOR
OOOOR
OOOOR
OOOOR
OOOOR
OOOOR
CCCCR
CCCCR
CCCCR
CCCCR
CCCCR
CCCCR
OOOOR
OOOOR
OOOOR
OOOOR
OOOOR
OOOOR
CCCCR
CCCCR
CCCCR
CCCCR
CCCCR
CCCCR

Sample A - AK/
Sample A - BK/
Sample A - CK/
Sample B - AK/
Sample B - BK/
Sample B - CK/
Sample C - AK/
Sample C - BK/
Sample C - CK/
Control - AK/
Control - BK/
Control - CK/
Sample A - AK
Sample A - BK
Sample A - CK
Sample B -AI{
Sample B - BK
Sample B - CK
Sample C -AK
Sample C - BK
Sample C - CK
Control -AK
Control - BK
Control - CK

Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
New Pipe Registers
New Pipe Registers
New Pipe Registers
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
New Pipe Registers
New Pipe Registers
New Pipe Registers

C Data

Clock Tested

Data Verified at

B,
B,
B,
B,
B,
B,
B,
B,
B,
A,
A,
A,
B,
B,
B,
B,
B,
B,
B,
B,
B,
A,
A,
A,

C
C
C
C
C
C
C
C
C
B,
B,
B,
C
C
C
C
C
C
C
C
C
B,
B,
B,

B,
B,
B,
B,
B,
B,
B,
B,
B,
A,
A,

C
C
C
C
C
C
C
C
C
B,
B,
B,
C
C
C
C
C
C
C
C
C
B,
B,
B,

C
C
C

C
C
C

Threshold Disable Test:
Step

A Data

B Data

----------------------------------------------------------------

37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60

AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH

OOOOH
OOOOH
OOOOH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH

OOOOH
OOOOH
OOOOR

BBBBR
BBBBR
BBBBR
BBBBR
BBBBR
BBBBR
BBBBR
BBBBR
BBBBR
OOOOH
OOOOH
OOOOH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBR
OOOOR
OOOOR
OOOOR

CCCCR
CCCCH
CCCCR
CCCCR
CCCCR
CCCCR
CCCCR
CCCCR
CCCCR
OOOOR
OOOOH
OOOOR
CCCCR
CCCCH
CCCCR
CCCCH
CCCCH
CCCCH
CCCCR
CCCCH
CCCCR
OOOOH
OOOOR
OOOOH

Sample A - AK/
Sample A - BK/
Sample A - CK/
Sample B - AK/
Sample B - BK/
Sample B - CK/
Sample C - AK/
Sample C - BK/
Sample C - CK/
Control - AK/
Control - BK/
Control - CK/
Sample A -AK
Sample A - BK
Sample A - CK
Sample B - AI{
Sample B - BK
Sample B - CK
Sample C - AK
Sample C - BK
Sample C - CK
Control -AK
Control - BK
Control - CK
5-93

Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
New Pipe Registers
New Pipe Registers
New Pipe Registers
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
New Pipe Registers
New Pipe Registers
New Pipe Registers

A,

B,
B,
B,
B,
B,
B,
B,
B,
B,
A,
A,
A,

C
C
C

C
C
C

Force Disqualify Test
Step

A Data

B Data

C Data

Clock Tested

Data Verified at

---------------------------------------------------------------------CCCCH
Sample A - AK/ Sample Registers
61
BBBBH
AAAAH
B
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84

AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH

OOOOH
OOOOH
OOOOH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH
AAAAH

OOOOH
OOOOH
OOOOH

BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
OOOOH
OOOOH
OOOOH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
OOOOH
OOOOH
OOOOH

CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
OOOOH
OOOOH
OOOOH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
OOOOH
OOOOH
OOOOH

Sample A - BK/
Sample A - CK/
Sample B - AK/
Sample B - BK/
Sample B - CK/
Sample C - AK/
Sample C - BK/
Sample C - CK/
Control - AK/
Control - BK/
Control - CK/
Sample A - AK
Sample A - BK
Sample A - CK
Sample B -AK
Sample B - BK
Sample B - CK
Sample C -AK
Sample C - BK
Sample C -CK
Control -AI{
Control - BK
Control - CK

At
Sample Registers A,
Sample Registers At
Sample Registers A,
Sample Registers At
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
New Pipe Registers
New Pipe Registers
New Pipe Registers
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
Sample Registers A,
New Pipe Registers
New Pipe Registers
New Pipe Registers

ERROR MESSAGES:
If an error occurs, the following message is displayed:

* Test FAILED--Test Step
cccc Clock tttt Error
qqqq Clock Enables
I/O Address
= aaaaH
Status Read
= rrrrH
Status Expected = eeeeH

ssss

Where:
ssss is the Test Step in the range: 1 to 84.
cccc 1s the tested Clock: Sample A,
Sample B,
Sample C,
Control
tttt is the test type:

Functional,
Uniqueness,
Disable,
Force Disqualify

5-94

t
B,
B,
B,
B,
B,
B,
B,
B,
A,
A,
A,
B,
B,
B,
B,
B,
B,
B,
B,
B,
A,
A,
A,

C
C
C
C
C
C
C
C
C
B,
B,
B,
C
C
C
C
C
C
C
C
C
B,
B,
B,

C
C
C

C
C
C

qqqq is the tested Clock Enable: AK/ BK/ CK/,
AK BK CK,
AK/ ,

BK/ ,
CK/,
AK.,
BK,
CK
aaaa is the address of a Data Board Sample Register:
OC6H for Data Board A,
OD6H for Data Board B,
OE6H for Data Board C.
or a
OC4H
OD4H
OE4H

Data Board New
for Data Board
for Data Board
for Data Board

Pipe Register:
A,
B,
C.

rrrr is the Data Word read from the Status Register.
eeee is the Data Word expected from the Sample Register which should be:
AAAAH for Data Board A, (OC6H, OC4H).
BBBBH for Data Board B, (OD6H, OD4H).
CCCCH for Data Board C, (OE6H, OE4H).

NOTE: OOOOR
Testing.

is the expected Data Word for all Data Boards during Un1qu.n•••

5-95

Clock Board Diagnostic Subtest 7
LATCH CLOCKS, DIAGNOSTIC INTERNAL CLOCK TEST

TITLE:

IIH, IF, IG, IH, 2H
ID, 2B, 2A, 2C, 2D
6A

TARGBT LOGIC:

Setup Latches in Subtest 2
TEST DESCRIPTION:
The Diagnostic Internal Latch Clocks A, Band C are tested for functionality
as well as the ability to disable these Clocks using the Normal Disable and
the Latch Disqualify Disable.
The Latch Clocks are tested by placing Data at the Front End of the Data
Board, issuing a Diagnostic Latch Clock, issuing a Diagnostic Sample Clock,
and checking the Sample Registers to see if a Data transfer took place.

NOTE: The Diagnostic Latch Clock is kicked by outputing a 1 to bit Dl of Writ.
Register OBSH of the Clock Board. This produces a clock pulse the width of the
8086's Write pulse. Consecutive kicks is achieved by consecutive outputs to
this port. It is never necessary to set this bit low.
TEST STEP INFORMATION I
Functionality Test:
Step

Data

Clock Tested

1
2

DOOOH
5555H

3

AAAAH

4

CCCCR
3333H
6666H
9999H
FFFFR

Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch

5
6
7

8

A,
A,
A,
A,
A,
A,
A,
A,

B,
B,
B,
B,
B,
B,
B,
B,

Data Verified at
C
C
C
C
C
C
C
C

Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample

Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers

Threshold Disable Test:
Step

Data

Clock Tested

Data Verified at

-----------------------------------------------Sample Register A
Latch A
9
AAAAH
10
11

BBBBH
CCCCH

Latch B
Latch C

Sample Register B
Sample Register C

5-96

A,
A,
A,
A,
A,
A,
A,
A,

B,
B,
B,
B,
B,
B,
B,
B,

C
C
C
C
C
C
C
C

Latch Disqualify Disable T•• t:
Step

Data

Clock Tested

Data Verified at

12

AAAAH

13

BBBBH
CCCCH

Latch A
Latch B
Latch C

Sample Register A
Sample Register B
Sample Register C

14

ERROR MESSAGES:
If an error occurs, the following message is displayed:

* Test FAILED--Test Step
cccc Clock tttt Error
Diagnostic Latch Clock
I/O Address
aaaaH
Status Read
= rrrrH
Status Expected = eeeeH

ssss

Where:
ssss is the Test Step in the range: 1 to 14.
cccc is the tested Clock: Latch A,
Latch B,
Latch C.
tttt is the test type:

Functional,
Threshold Disable,
Disqualify Disable.

aaaa is the address of a Data Board Sample Register:
OC6H for Data Board A,
OD6H for Data Board B,
OE6H for Data Board C.
rrrr is the Data Word read from the Status Register.
eeee is the Data Word expected from the Sample Register which should be:
Data for Functional Testing:
OOOOH,
5555H,
AAAAH,

CCCCH,
3333H,
6666H,
9999H,
FFFFH.

5-97

Data for Threshold Disable and Disqualify Disable Testing:
AAAAH for Data Board A.
BBBBH for Data Board B.
CCCCH for Data Board C.

5-98

Clock Board Diagnostic Subtest 8

TITLE:

LATCH CLOCKS, OR-ONLY ENABLES TEST

TARGET LOGIC:

2E, 2F, 2G, 2H
1D, 2B, 2A, 2C, 2D
Setup Latches in Subtest 2

TEST DESCRIPTION:
The Latch Clocks A, Band C OR-Only Enables are tested for functionality, and
the ability to disable these Clocks using the the Latch Disqualify Disable.
The Latch Clocks are tested by placing Data at the Front End of the Data
Board, issuing a Diagnostic Latch Clock, issuing a Diagnostic Sample Clock,
and checking the Sample Registers to see if a Data transfer took place.

TEST STEP

INFO~ION:

Functionality Test:
Step
1
2
3

Data

Clock Tested

Data Verified at

AAAAH

Latch A
Latch B
Latch C

Sample Register A
Sample Register B
Sample Register C

BBBBH
CCCCH

Uniqueness Test:
Step

A Data

B Data

C Data

Clock Tested

Data Verified at

4

AAAAH

5

OOOOH

6

00000

OOOOH
BBBBH
OOOOH

OOOOH
OOOOH
CCCCH

Latch A
Latch B
Latch C

Sample Registers A, B, C
Sample Registers A, B, C
Sample Registers A, B, C

Clock Tested

Data Verified at

Latch Disqualify Disable Test:
Step

A Data

B Data

C Data

---------------------------------------------------------------7
CCCCH
Latch A
Sample Registers
AMAH
BBBBH
8

9

AAAAH
AAAAH

BBBBH
BBBBH

CCCCH
CCCCH

Latch B
Latch C

5-99

A, B, C
Sample Registers A, B, C
Sample Registers A, B, C

ERROR MESSAGES:

If an error occurs, the following message is displayed:

* Test FAILED--Test Step
cccc Clock tttt Error
OR Only Enables
I/O Address
aaaaH
Status Read
rrrrH
Status Expected
eeeeH

ssss

Where:
ssss is the Test Step in the range: 1 to 9.
cccc is the tested Clock: Latch A,
Latch B,
Latch C.
tttt is the test type:

Functional,
Uniqueness,
Latch Disqualify Disable.

aaaa is the address of a Data Board Sample Register:
OC6H for Data Board A,
OD6H for Data Board B,
OE6H for Data Board C.
rrrr is the Data Word read from the Status Register.
eeee is the Data Word expected from the Sample Register which should be:
AAAAH for Data Board A.
BBBBH for Data Board B.
CCCCH for Data Board C.

NOTE: OOOOH
Testing.

is the expected data word for all Data Boards during Uniqueness

5-100

Clock Board Diagnostic Subtest 9
LATCH CLOCKS, AR, BR AND CR CLOCKS TEST

TITLB:
TARGET LOGIC:

IF,
ID,
IE

2E,
2B,

IG,
2A,

2F,
2C,

IH,
2D

2G,

2H

Setup Latches in Subtest 2
TEST DESCRIPTION:
The AR, AR/, BR, BR/, CR and CR/ Clock Enables for Latch Clocks A, B, and C
are tested for functionality and uniqueness, as well as the ability to disable
these Clocks using the Threshold Disable, and the Latch Disqualify Disable.
The Latch Clocks are tested by placing Data at the Front End of the Data
Board, issuing a Latch Clock by toggling one of the AR, BR, CR Enables, and
issuing a Diagnostic Internal Sample Clock and checking the Sample Registers
to see if a Data transfer took place.
NOTE: The Logic states of AR, ARI, BR, BR/. CR and CRI are determined by the
current threshold at the probes. An ECL Threshold. and a VARIABLE A Threshold
1. u.ed to provide the High and Low logic states.
This test requires the use of the Threshold Board, and the probes.
TEST STBP INFORMATION:
Functionality Testa
Step

Data

Clock Tested

1

AAAAH

2

Latch
Latch
Latch
Latch
Latch
Latch

3

BBBBH
CCCCH

4

AAAAH

5

BBBBH
CCCCH

6

A
B
C
A
B
C

Data Verified at
Sample
Sample
Sample
Sample
Sample
Sample

- AR/, BR/, CR/
- AR/, BR/, CR/
- AR/, BR/, CR/
- AR, BR, CR
- AR, BR, CR
- AR, BR, CR

Register
Register
Register
Register
Register
Register

A
B
C
A
B
C

Uniqueness Test:
Step

A Data

B Data

C Data

Clock Tested

Data Verified at

---------------------------------------------------------------------OOOOH
7
Sample Registers A, B,
AAAAH
OOOOH
Latch A - AR/
8
9

AAAAH
AAAAH

10
11
12
13

OOOOH
OOOOH
OOOOH
OOOOH

OOOOH
OOOOH
BBBBH
BBBBH
BBBBH
OOOOH

OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
CCCCH

Latch
Latch
Latch
Latch
Latch
Latch

A
A
B
B
B
C

-

5-101

BR/
CR/
AR/
BR/
CR/
AR/

Sample
Sample
Sample
Sample
Sample
Sample

Registers
Registers
Registers
Registers
Registers
Registers

A,
A,
A,
A,
A,
A,

B,
B,
B,
B,
B,
B,

C
C
C
C
C
C
C

14
15
16
17
18
19
20
21
22
23
24

OOOOR
OOOOR
AAAAII
AMAH
AMAH

OOOOR
OOOOR
OOOOR
OOOOR
OOOOR
OOOOR

OOOOR
OOOOR
OOOOR
OOOOR
OOOOR
BBBBR
BBBBR
BBBBR
OOOOR
OOOOR
OOOOR

CCCCR
CCCCH
OOOOR
OOOOR
OOOOR
OOOOR
OOOOR
OOOOR
CCCCR
CCCCR
CCCCR

Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch

C Data

Clock Tested

C
C
A
A
A
B
B
B
C
C
C

- BR/
- CR/
- AR
- BR
- CR
-AR
- BR
- CR
-AR
- BR
- CR

Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample

Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers

A,
A,
A,
A,
At
A,
A,
A,
A,
A,
A,

'8,

C
C
C
C
C
C
C
C
C
C
C

B,
B,
B,
B,
B,
B,
B,
B,
B,
B,
B,
B,
B,
B,
B,
B,
B,
B,

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

'8,

B,
B,
B,
B,

R,
B,
B,
B,
B,

Threshold Disable Teat:
Step

A Data

B Data

Data Verified at

----------------------------------------------------------------

25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42

AMAH

AMAH

AMAH
AMAH
AMAH
AMAH
AMAH
AMAH
AMAH
AAAAH
AMAH
AMAH
AMAH
AMAH
AMAH
AMAH
AMAH
AMAH

BBBBR
BBBBR
BBBBR
BBBBR
BBBBR
BBBBR
BBBBR
BBBBR
BBBBR
BBBBH
BBBBR
BBBBR
BBBBR
BBBBR
BBBBR
BBBBR
BBBBR
BBBBR

CCCCR
CCCCR
CCCCR
CCCCR
CCCCR
CCCCR
CCCCR
CCCCR
CCCCR
CCCCR
CCCCR
CCCCR
CCCCR
CCCCR
CCCCR
CCCCH
CCCCR
CCCCR

Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch

A - AR/
A - BR/
A - CR/
B - AR/
B - BR/
B - CR/
C - AR/
C - BR/
C - CR/
A - AR
A - BR
A - CR
B -AR
B - BR
B - CR
C -AR
C - BR
C - CR

Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample

Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers

A,
A,
A,
A,
A,
A,
A,
A,
A,
A,
A,
A,
A,
A,
A,
A,
A,
A,

Latch Disqualify Disable Test:
Step

A Data

B Data

C Data

Clock Tested

Data Verified at

----------------------------------------------------------------------

43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60

AMAH
AMAH
AMAH
AMAH
AMAH
AMAH
AMAH
AMAH
AMAH
AMAH
AMAH
AMAH
AMAH
AMAH
AMAH
AMAH
AMAH
AMAH

BBBBR
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBR
BBBBH
BBBBR
BBBBR
BBBBR
BBBBR
BBBBH
BBBBH

CCCCR
CCCCR
CCCCR
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCR
CCCCR
CCCCR
CCCCH
CCCCR
CCCCR

Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch

A - AR/
A - BR/
A - CR/
B - AR/
B - BR/
B - CR/
C - AR/
C - BR/
C - CR/
A - AR
A - BR
A - CR
B -AR
B - BR
B - CR
C -AR
C - BR
C - CR

5-102

Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample

Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers

A,
A,
At
A,
A,
A,
A,
A,
A,
A,
A,
A,
A,
A,
A,
A,
A,
A,

B,
B,
B,
B,
B,
B,
B,
B,
B,
B,
B,
B,
B,
B,
B,
B,
B,
B,

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

ERROR MESSAGES:

If an error occurs, the following message is displayed:

* Test

FAILED--Test Step
cccc Clock tttt Error
qqqq Clock Enable
I/O Address
= aaaaH
Status Read
= rrrrH
Status Expected
eeeeH

ssss

Where:
ssss is the Test Step in the range: 1 to 60.
cccc is the tested Clock: Latch A,
Latch B,
Latch C•.
tttt is the test type:

Functional,
Uniqueness,
Threshold Disable,
Latch Disqualify Disable.

qqqq is the tested Clock Enable: ARI BRI CR/,
AR BR CR,

ARI,
BR/,

CRI,
AR,
BR,

CR.
aaaa is the address of a Data Board Sample Register:
OC6H for Data Board A,
OD6H for Data Board B,
OE6H for Data Board C.
rrrr is the Data Word read from the Status Register.
eeee is the Data Word expected from the Sample Register which should be:
AAAAH for Data Board A.
BBBBH for Data Board B.
CCCCH for Data Board C.

NOTE: OOOOH
Testing.

i8 the expected data word for all Data Boards during

5-103

Uniqueness

Clock Board Diagnostic Subtest 10

TITL!:

LATCH CLOCKS AS, BS AND CS CLOCKS TEST

TARGET LOGIC:

2B, 2A, 2C, 2D,
3A

1D,

2E, 2F, 2G,

2H

Setup Latches in Subtest 2

TEST DESCRIPTION:
The AS, AS/, BS, BS/, CS and CS/ Clock Enables for Latch Clocks A, Band Care
tested for functionality and uniqueness, as well as the ability to disable
these Clocks using the Threshold Disable.
The Latch Clocks are tested by placing Data at the Front End of the Data
Board, asserting the appropriate AS, BS, CS Enables, issuing a Diagnostic
Latch Clock, and issuing a Diagnostic Internal Sample Clock and checking the
Sample Registers to see if a Data transfer took place.
This test is different than the rest due to the transparent mode of the 10130
Latches on the Data Boards.
When the Latch Clock is held in a low state, the
10130 Latches on the Data Board are transparent, the Q output follows the D
input. When the Latch Clock goes high, this latches the Data into the 10130's
and the D input then becomes a don't care.
In this test, instead of toggling the enable to the AS, BS or CS, it is held
active and a Diagnostic Int Clock issued. This causes the Data Board to be in
Latch Mode, instead of being transparent.
The Logic states of AR, AR/, BR, BR/, CR and CR/ are determined by the current
threshold at the probes. An ECL Threshold, and a VARIABLE A Threshold are used
to provide the High and Low logic states.
This test requires the use of the Threshold Board, and the probes.

TEST STEP INFORMATION:
Punetlonallty Test:
Step

Data

Clock Tested

Data Verified at

-----------------------------------------------------------1

AMAH

2

BBBBH
CCCCH

3
4
5
6

AMAH

BBBBH
CCCCH

Latch
Latch
Latch
Latch
Latch
Latch

A
B
C
A
B
C

-

AS/,
AS/,
AS/,
AS,
AS,
AS,

BS/,
BS/,
BS/,
BS,
BS,
BS,

CS/
CS/
CS/
CS
CS
CS

5-104

Sample
Sample
Sample
Sample
Sample
Sample

Register
Register
Register
Register
Register
Register

A
B
C
A
B
C

Uniqueness Test:
Step

A Data

B Data

C Data

Clock Tested

Data Verified at

7
8
9

AMAH
AMAH
AMAH

OOOOH
OOOOH
OOOOH

10
11
12

OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH

BBBBH
BBBBH
BBBBH

OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH

Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample

13
14

15
16

17
18
19
20

21
22
23
24

AMAH
AMAH
AMAH

OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH

BBBBH
BBBBH
BBBBH

OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH

OOOOH
OOOOH
OOOOH

CCCCH
CCCCH
CCCCH

Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch

OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH

CCCCH
CCCCH
CCCCH

AAAB B B C CCAAAB B B CC C-

AS/
BS/
CS/
AS/
BS/
CS/
AS/
BS/
CS/
AS
BS
CS
AS
BS
CS
AS
BS
CS

Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers

At
At
At
At
At
At
At
At
At
At
At
At
At
At
At
At
At
A,

Bt C
~t C
Bt C
Bt C
Bt C
Bt C
Bt C
Bt C
Bt C
Bt C
Bt C
Bt C
Bt C
Bt C
Bt C
B, C
B, C
B, C

At
A,
A,
A,
A,
A,
At
A,
A,
A,
A,
A,
At
A,
A,
A,
A,
A,

B,
B,
Bt
B,
Bt
B,
B,
B,
B,
B,
B,
B,
Bt
B,
Bt
B,
Bt
B,

Threshold Disable Test:
Step

A Data

B Data

C Data

Clock Tested

Data Verified at

25
26
27

AMAH
AMAH
AMAH
AMAH
AMAH
AMAH
AMAH
AMAH
AMAH
AMAH
AMAH
AMAH
AMAH
AMAH
AMAH
AMAH
AMAH
AMAH

BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH
BBBBH

CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH
CCCCH

Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch

Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample

28
29
30
31

32
33
34

35
36
37

38
39

40
41
42

A
A
A
B
B
B
C
C
C
A
A
A
B
B
B
C
C
C

-

AS/
BS/
CS/
AS/
BS/
CS/
AS/
BS/
CS/
AS
BS
CS
AS
BS
CS
AS
BS
CS

ElUtOR MESSAGES:

If an error occurs, the following message is displayed:

* Test

FAILED--Test Step
cccc Clock tttt Error
qqqq Clock Enable
I/O Address
= aaaaH
Status Read
= rrrrH
Status Expected = eeeeH

ssss

5-105

Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

Where:
ssss is the Test Step in the range: 1 to 42.
cccc is the tested Clock: Latch A,
Latch B,
Latch C.
tttt is the test type:

Functional,
Uniqueness,
Threshold Disable.

qqqq is the tested Clock Enable: AS/ BS/ CS/,
AS BS CS,
AS/,
BS/,
CS/,
AS,
BS,
CS.
aaaa is the address of a Data Board Sample Register:
OC6H for Data Board A,
OD6H for Data Board B,
OE6H for Data Board C.
rrrr is the Data Word read from the Status Register.
eeee is the Data Word expected from the Sample Register which should be:
AMAH for Data Board A.
BBBBH for Data Board B.
CCCCH for Data Board C.

NOTE: OOOOH
Testing.

i8 the expected data word for all Data Boards during

5-106

Uniqueness

Clock Board Diagnostic Subt •• t 11
TITLE:

DECADE FREQUENCY AND MULTIPLIER DIVIDE BY TEST

TARGET LOGIC:

10D , 12 C, 11 C
10C
lIB
9E, 10E, 9C, 9D
Setup Latches in Subtest 2
100Mhz Oscilator Descrete Componets (Grid 8B-6B)

TEST DESCRIPTION:
This test checks the Clock Decade multiplexer,
counter, (Multiplier).

(Decade),

and the divide

by

The 100Mhz, 10Mhz, 1Mhz, 100Khz, 10Khz, 1Khz and 100hz Clocks are tested with
various Multipliers.
The Clock frequencies are verified within a ballpark
range, but this verifies that the multiplexer is selecting different Decades.
A frequency counter is required to adjust/verify the Time Period of the 100Mhz
Clock.
When the faster Clock frequencies are being tested,
quick, and the following message is displayed:

the testing time is very

)Counting Clock Pulses •••
During the 1Khz test, the following message is displayed:
)Counting Clock Pulses ••• 4 seconds
During the 100hz test, the following message is displayed:
)Counting Clock Pulses ••• 20 seconds
During the testing of the Multiplier Divide by counter,
is displayed:
)Checkina the Multiplier Divide by •••

5-107

the following message

TEST STEP INFORMATION:
Decade Frequency Test:
Step
1
2
3
4
5
6
7

Decade

Mult

Clks Expected

Clks Minimum

Clks Maximum

0
1
2
3
4
5
6

8
8
8
8
8
8
8

256
256
256
256
256
256
256

128
128
128
128
128
128
128

384
384
384
384
384
384
384

Clks Minimum

Clks Maximum

Multiplier Divide by Test:
Step

Decade

Hult

Clks Expected

--------------------------------------------------------------------83
o
8
3
o
2048
9

10
11
12
13
14
15
16
17
18
19
20
21
22
23

*
*

3
3
3
3
3
3
3
3
3
3
3
3
3
3
3

1
2
3
4
5
6
7
8
9

10
11
12
13
14
15

-89
-95
-97
-111
-122
-134
-148
-167
-191
-224
-270
-336
-450
256
256

Step
Step
Step
Step
Step
Step
Step
Step
Step
Step
Step
Step
Step

8 Clock Count
9 Clock Count
10 Clock Count
11 Clock Count
12 Clock Count
13 Clock Count
14 Clock Count
15 Clock Count
16 Clock Count
17 Clock Count
18 Clock Count
19 Clock Count
20 Clock Count

o
o

2048
2048
2048
2048
2048
2048
2048
2048
2048
2048
2048
2048
2048
2048
2048

The values above preceeded by - are approximate values. They were selected by
running the test a single time on a single K450.
This value varies from
System to System due to minor differences in the CPU's Clock frequency, and
other hardware propagation times. The precise values are not important as long
as Clock count increments while the Multiplier increments.
Test Steps 22 and 23 are different from the rest. When the Multiplier goes
from 13 to 14, and from 14 to 15, the Clock count no longer follow~ the slowlinear increase that it followed with the Multiplier range of 0 to 12.
The
Clock count approximately doubles, so a ballparking method of 256 clocks
inside the 0 to 2048 range is used.

5-108

BOOtt MESSAGBS:

If an error occurs, the following message is displayed:

* Test FAILED--Test Step
hmsg Error
Decade x: ffff Clock
Multiplier
= mmmmD
Clocks counted = ccccD
Min Clock count = llllD
Max Clock count = hhhhD

ssss

Where:
ssss is the Test Step in the range: 1 to 23.
hmsg is "Clock Frequency Counting",
"Multiplier Clock Divide by".
x is the selected Decade: 0, 1, 2, 3, 4, 5, 6.
ffff is the Clock frequency:

100 Mhz,
10 Mhz,
1 Mhz,
100 Khz,
10 Khz,
1 Khz,
100 hz.

mmmm is the current Multiplier value, range is 0 to 15.
cccc is the Number of clocks counted, range is 0 to 2048.
1111 is the Minimum number of clocks that could be counted for frequency.

hhhh is the Maximum number of clocks that could be counted for frequency.

5-109

Clock Board Diagnostic Subtest 12
LEVEL RAMs DATA INTEGRITY TEST

TITLE:
TARGET LOGIC:

lIE. IlF

11J
12F. 12G
120. 100. 12E
Setup Latches in Subtest 2
TEST DESCRIPTION:
The Level RAMs on the Clock Board are organized as 2048 x 4. They are written
to by the Control Board. and read into the highest nibble of the word from
port BOH of the Clock Board.
The Level RAM's Data Integrity is checked by
writing all 16 possible values to the RAM. and reading it back to verify that
each Data Bit is functional and unique.
TEST STEP INFORMATION:
Data Integrity Test:
Step

Data

Address Locations

----------------------------------1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

OOOOH
0001H
0002H
0003H
0004H
0005H
0006H
0007H
0008H
0009H
OOOAH
OOOBH
OOOCH
OOODH
OOOEH
OOOFH

000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000

-

2047
2047
2047
2047
2047
2047
2047
2047
2047
2047
2047
2047
2047
2047
2047
2047

5-110

Inoa MESSAGES:

If an error occurs, the following message is displayed:

* Test FAILED--Test Step ssss
Level RAM Data Integrity Error
Diagnostic Internal Clock
Byte Count
= ccccD
Data Read
= rrrrH
Data Expected = eeeeH
Where:
ssss is the Test Step in the range: 1 to 16.
cccc is RAM byte count, (address) in the range of 0 to 2047.
rrrr is the Data Word read from the Level RAMS.
eeee is the Data Word expected from the Level RAMS which should be:

OOOOH,
0001H,
0002H,
0003H,

0004H,
0005H,
0006H,
0007H,

OOOBH,
0009H,

OOOAH,
OOOBH,
OOOCH,
OOODH,
OOOEH,
OOOFH.

Clock Board Diagnostic Subteat 13

TITLE:

LEVEL RAMs ADDRESS INTEGRITY TEST

TARGET LOGIC:

IlD
IlG,
llE,
IlJ
12F,
12D,

12H
IlF
12G
10D, 12E

Setup Latches in Subtest 2

TEST DESCRIPTION:
The Level RAMs address is provided by thru counters which provide ten address
lines which can address 1024 locations. An additional flip flop toggles back
and forth between the two 10474 RAM Chips on each Write/Read, to allow the
access of 2048 RAM locations.
The Level RAMs are tested for addressing uniqueness. This verifies that each
of 2048 locations can be written to independently of all other locations.

TEST STEP INFORMATION:
Step 1.

An incrementing Data pattern from OOH to OFH is written to RAM,
which repeats after each 16 locations.
This verifies address
lines AO, AI, A2 and A3.

Step 2.

A Block Incrementing Data pattern from OQH to OFH is written to
RAM, which repeats after each 1024 locations.
This verifies
address lines A4, AS, A8 and A9.

Step 3.

A Block Data pattern of OsH and OAR is written to RAM, which
covers all 2048 locations. This verifies that both of the 10474
RAM chips are written to.

ERROR MESSAGES:
If an error occurs, the following message is displayed:

* Test FAILED--Test Step ssss
Level RAM Address Uniqueness Error
Diagnostic Internal Clock
Byte Count
= ccccD
Data Read
= rrrrH
Data Expected = eeeeH

5-112

Where:
ssss is the Test Step in the range: 1 to 3.
cccc is RAM byte count, (address) in the range of 0 to 2047.
rrrr is the Data Word read from the Level RAMS.
eeee is the Data Word expected from the Level RAMS which should be:

OOOOH,
0001H,
0002H,
0003H,
0004H,
0005H,
0006H,
0007H,
0008H,
0009H,

OOOAH,
OOOBH,
OOOCH,
OOODH,
OOOER,
OOOFH.

5-113

Clock Board Diagnostic Subteet 14

TITLE:

LEVEL RAMs CONTROL TEST

TARGET LOGIC:

lID
IlG,
lIE,
11J
12F,
12D,

12H
11F
12G
10D, 12E

Setup Latches in Subtest 2

TEST DESCRIPTION:
This Subtest verifies the functionality of the Control Logic associated with
the Level RAM.
The First Test Step checks the odd/even toggling of the level
ram. Each Consecutive write operation to the RAM should toggle back and forth
between the Even 10422 RAM chip, and the ODD 10422 RAM chip. A D latch is
acting as a flip flop, and providing a write enable signal to only one RAM
chip. An OAH is written to all Even addresses and a 05H to all Odd.
The Second Test Step checks the Level RAM Write Enable/Disable function.
The
Level RAM is Write enabled when the signals ARMED and TRACED from the Control
Board are both active.
This test does seven writes with the following conditions:
LEVEL

ARMED

TRACED

RESULT

0

1

1

0

1

1

1

1

2

1

0

not recorded

3

1

0

not recorded

4

1

1

4

5

1

1

5

5

0

1

not recorded

The Third Test Step checks the Recirculation feature of the Level RAM.
The
Data is read out of the 10422 RAM chips, looped back, and written back in.
This is checked by writing an incrementing pattern into the RAM, and then
reading it back, verifying the Data Integrity.
The Data is then read back a
second time and verified. On the second read, the Data is shifted by one
Address location from the Recirculation.

5-114

The Fourth Test Step checks the Level RAM reset persistence by first filling
the RAM with a value of OOH, then holding the reset line to the RAM address
counters active,
and hammering address location 0 by performing 2048
consecutive write operations.
This should modify the Data Value at location
0, but the other 2047 locations should be unchanged.
All 2048 locations are
read back and verified.

TEST STEP INFORMATION:
Step
1
Step

Data Even Locations

Data Odd Locations

OOOAH

0005H

Data

Address

2

OOOOH
0001H
0004H
0005H

000
001
002
003

Step

Data

Address

0005H
OOOOH

000
001
002

OOOOH
OOOOH

2046
2047

4

OOOOR

(0005H in Location 000 Only)

ERROR MESSAGES:
If an error occurs, the following message is

* Test FAILED--Test Step
hmsg Error
Diagnostic Internal Clock
Byte Count
= ccccD
Data Read
= rrrrH
Data Expected = eeeeH

displayed~

ssss

Where:
ssss is the Test Step in the range: 1 to 4.
hmsg is Level
Level
Level
Level

RAM
RAM
RAM
RAM

odd/even Toggle,
Write enable/disable,
Recirculation,
Hammer/Addr Reset.

cccc is RAM byte count, (address) in the range of 0 to 2047.
rrrr is the Data Word read from the Level RAMS.

5-115

eeee is the Data Word expected from the Level RAMS which should be:
Odd/Even Test:

OOOSH,
OOOAR.
Write Disable/Enable Test:

OOOOH,
OOOlH,
0004H,

OOOSH.
Recirculation Test:

OOOOH,
OOOlH,
0002H,
0003H,
0004H,

OOOSH,
0006H,
0007H,
0008H,
0009H,

OOOAR,
OOOBH,
OOOCR,
OOODH,
OOOER,
OOOFR.
Hammer/Address Reset Test:

OOOSH,
OOOOH.

S-1l6

K450 LOGIC ANALYZER THRESROLD/GPIB/RS-232 BOARD DIAGNOSTIC

DIAGNOSTIC OVERVIEW
This
section
describes
the
subtests
executed
on
the
K450
Threshold/GPIB/RS-232 Board, how Error Reporting is accomplished, and the
concept behind each subtest program.
The Threshold/GPIB/RS-232 board diagnostics is divided into nine
each of which is described individually on the following pages.

subtests,

Subtest 1 is a DAC 7541 linearity test;
subtest 2 is a DAC 7533 linearity
test;
subtest 3 is a Multiplexer/threshold test, subtest 4 is a serial I/O
#1 test; subtest 5 is a serial I/O #2 test, subtest 6 is a 8253 counter mode 1
test; subtest 7 through subtest 9 are GPIB internal logic tests (the GPIB
cable and operator intervene flag should not be set);
subtest 7 is GPIB
control status test; subtest 8 is GPIB }WU interrupt logic test; subtest 9
is GPIB data out register and parallel poll response register test.
Subtests 4 and 5 require a RS-232 wrap back connector installed to perform the
test.
Only a part of the GPIB logic is checked in the GPIB internal test (subtests 7
through 9 check internal logic only).
The external handshake logic is not
tested.
NOTE: The TARGET LOGIC listed in each subtest description does not necessarily
include all of the logic which could affect the operation of the subteat.
SUBTEST CATEGORY
1.
2.
3.
4.
5.
6.
7•
8.
9.

DAC 7541 LINEARITY TEST
DAC 7533 LINEARITY TEST
MUX/THRESHOLD LOGIC TEST
SERIAL I/O #1 TEST
SERIAL I/O #2 TEST
TIMER 8253 COUNTER 0 TEST
GPIB INTERNAL CONTROL LINE TEST
GPIB INTERNAL MPU INTERRUPT LOGIC TEST
GPIB INTERNAL DATA REGISTER TEST
ERROR COUNT CATEGORY

1. SUBTEST 1
2. SUBTEST 2
3. SUBTEST 3
4. SUBTEST 4
5. SUBTEST 5
6. SUBTEST 6
7. SUBTEST 7
8. SUBTEST 8
9. SUBTEST 9

ERROR
ERROR
ERROR
ERROR
ERROR
ERROR
ERROR
ERROR
ERROR

COUNT.
COUNT.
COUNT.
COUNT.
COUNT.
COUNT.
COUNT.
COUNT.
COUNT.

5-117

Threshold Diagnostic Subtest 1
DAC 7541 LINEARITY TEST

TITLE:

TARGET LOGIC:

5E, 6E, 8B, 7F, 8F, 8A
7A, 7E, Q2
and power supply +5.0V, -5.2V,-2.0V, AGND, -10.0V, +10.0V,
VBB(+3.0V), +15V(divided as +7.5V), -15V(divided as -7.5V)

TEST DESCRIPTION:
The DAC 7541 linearity is tested by using the +10.0V, -lO.OV, AGND, -2.0V, 5.2V, +5.0V, +3.0V, +7.5V, -7.5V, +o.OOV, +1.30V and -1.40V as reference
voltage, multiplexed through 7F as noninverting input, and writing data into
8A
as inverting input until Q2 toggles its state.
The ADC status is then
verified by reading port 04H bit O.
When the reference voltage is +10.0V, the DAC 7541 is initially programmed to
-10.0V, so Q2 is turned on. The ADC status bit is equal to 0 which increments
the DAC 7541 output voltage until the ADC status bit toggles its state.
When the reference voltages are -10.0V, AGND, -2.0V, -5.2V, +5.0V, +3.0V,
+7.50V, -7.50V, DVM input, +1.30V, and -1.40V, the DAC 7541 is initially
programmed to +10.0V, so Q2 is turned off. The ADC status bit is equal to 1,
decrementing the DAC 7541 output voltage until the ADC status bit toggles its
state.

TEST STEP INFORMATION:
Step
1
2
3
4
5
6
7
8
9

10
11
12

Reference Voltage
+10.0V
-10.0V
AGND
-2.0V
-5.2V
+5.0V
VBB(+3.0V)
+15V /2
-15V/2
DVM
-ECL
+TTL

Initial 7541 Data Voltage
OFFFH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH

(-10.0V)
(+10.0V)
(+10.0V)
(+10.0V)
(+lO.OV)
(+10.0V)
(+10.0V)
(+10.0V)
(+10.0V)
(+10.0V)
(+10.0V)
(+10.0V)

5-118

Initial ADC Status
0
1
1
1
1
1
1
1
1
1
1
1

ERROR MESSAGE:

If an error occurs, the following message is displayed:

* Test FAILED--Test Step zz
DAC 7541 Linearity Test
Voltage Expected
see.eee
Voltage Lower Limit
suu.uuu
Voltage Upper Limit
sll.lll
Actual Voltage Read = saa.aaa
ADC Status Expected = x
ADC Status Expected = y
Where zz should be in the range of 1 through 12
s should be + or ee.eee should be in the range of 00.000 through 10.000
uu.uuu should be 9.940, 10.235, 0.300, 2.350, 5.625, 4.820
2.700, 7.380, 7.980, 0.300, 1.000, 1.700
11.111 should be 10.240, 9.935, 0.300, 1.750, 5.025, 5.420

3.300, 7.980, 7.380, 0.300, 1.600, 1.100
aa.aaa should be in the range of 00.000 through 10.000
x,y should be 0 or 1

5-119

Threshold Diagnostic Subtest 2
TITLE:

DAC 7533 LINEARITY TEST

TARGET LOGIC:

6D, 4B, 12B, 9B, 9A, 4A, SA, lOA,
6F, 7A, 8A, Q2, 8F, 5E, 6E, 8B

TEST DESCRIPTION:
The DAC 7533 linearity is tested by using the DAC 7541 as reference voltage.
VAR A and VAR B are multiplexed through 6F as the noninverting input of
7A,
and
continues incrementing or decrementing the VAR A or VAR B voltage by
writing to port 08R or OAR until the ADC output bit toggles its state.
When the DAC 7541 reference voltage is +10.0V, the DAC 7533 is initially
programmed to -10.0V, so Q2 is turned off and the ADC status bit is equal to
1. When the DAC 7541 reference voltages are -9.980V, -5.0V, O.OOV, and +5.0V,
DAC 7533 is initialized to +10.0V, so Q2 is turned on, and the ADC is equal to
O.
When VAR A and VAR B are tested, each DAC 7533 contains five voltage levels, 9.980V, -5.0V, O.OOV, +5.00V, and +10.00V.
TEST STEP INFORMATION:
Step
1
2
3
4
5
6
7
8
9
10

Reference Voltage
-9.980V
-5.0V
-O.OOOV
+S.OV
+10.00V
-9.980V
-S.OV
-O.OOOV
+5.0V
+10.00V

(7541 )
(7541)
(7541)
(7541 )
(7541)
(7541)
(7541)
(7541 )
(7541)
(7541)

Initial 7533 Data Voltage
OOOOR
OOOOR
OOOOR
OOOOR
OFFFR
OOOOR
OOOOR
OOOOR
OOOOR
OFFFH

(VAR
(VAR
(VAR
(VAR
(VAR
(VAR
(VAR
(VAR
(VAR
(VAR

A
A
A
A
A
B
B
B
B
B

+10.0V)
+10.0V)
+10.0V)
+10.0V)
-10.0V)
+10.0V)
+10.0V)
+10.0V)
+10.0V)
-10.0V)

ERROR MESSAGE:
If an error occurs, the following message is displayed:

* Test FAILED--Test Step zz
DAC 7533 Linearity Test
Voltage Expected
see.eee
Voltage Lower Limit
suu.uuu
Voltage Upper Limit
sll.lll
Actual Voltage Read = saa.aaa
ADC Status Expected = x
ADC Status Expected = y
5-120

Initial ADC Status
0
0
0
0
1
0
0
0
0
1

Where zz should be in the range of 1 through 10
s should be + or ee.eee should be in the range of 00.000 through 10.000
uu.uuu should be 10.220, 5.620, 0.500, 4.620, 9.740
11.111 should be

9.740, 4.620, 0.500, 5.620, 10.240

aa.aaa should be in the range of 00.000 through 10.000
x,Y should be

o

or 1

5-121

Threshold Diagnostic Subteat 3

TITLE:

THRESHOLD/MUX. LOGIC TEST

TARGET LOGIC:

4D, sB, lA, ID, IB, lC, 2A, 2D
SF, 7A, 7E, sE, 6E, 8B, 8A, 8F
and Q2.

TEST DESCRIPTION:
The Threshold/mux's logic is tested by using the THO through THs as reference
voltages.
These voltages are multiplexed through SF and supplied as the
noninverting input to 7A.
The DAC 7541 is initially programmed to +lO.OV and
decrements the output voltages until the ADC output status bit toggles its
state.
Reference voltages for -ECL, -TTL, -VAR A, and -VAR B are present for each
threshold channel. The -ECL is +1.300V, -TTL is -1.400V, -VAR A is +s.OV, and
-VAR B is -s.OV.
Testing occurs for threshold channels THO through THs.
The original
status bit should be 1 when the DAC 7541 is initialized to +10.0V.

ADC

TEST STEP INFORMATION:
Step

Logic

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
24
24

-ECL
-ECL
-ECL
-ECL
-ECL
-ECL
-VAR
-VAR
-VAR
-VAR
-VAR
-VAR

TH Channel

A
A
A
A
A
A

-TTL
-TTL
-TTL

-TTL
-TTL
-TTL
-VAR
-VAR
-VAR
-VAR
-VAR
-VAR

B
B
B
B
B
B

0
1
2
3
4
5
0
1
2
3
4
5
0
1
2
3
4
5
0
1
2
3
4
5

Initialized 7541 Voltage
+10.OV
+10.0V
+10.0V
+10.0V
+10.0V
+10.0V
+10.0V
+10.0V
+10.0V
+10.0V
+10.0V
+10.0V
+10.0V
+10.0V
+10.0V
+10.0V
+10.0V
+10.0V
+10.0V
+10.0V
+10.0V
+10.0V
+10.0V
+10.0V

5-122

Initial ADC Status
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

ERROR MESSAGE:

If an error occurs, the following message is displayed:

* Test FAILED--Test Step zz
Threshold/Mux. Logic Test
111111 Threshold Testing
TH Channel n Testing
Voltage Expected
= see.eee
Voltage Lower Limit = suu.uuu
Voltage Upper Limit
sll.lll
Actual Voltage Read
saa.aaa
ADC Status Expected = x
ADC Status Expected
y
Where zz should be in the range of 1 through 24
111111 should be -ECL, -VAR A, -TTL, -VAR B
n should be in the range of 0 through 5
s should be + or ee.eee should be 1.300, 5.000, 1.400, 5.000
uu.uuu should be 0.9S0, 4.S00, 1.720, 5.440
11.111 should be 1.620, 5.400, 1.0S0, 4.S00

aa.aaa should be in the range of 00.000 through 10.000
x,y should be

a or 1

5-123

Threshold Diagnostic Subtest 4
TITLE:

SERIAL I/O PORT #1 TEST

TARGET LOGIC:

12D, 14A, 13A, 8E

TEST DESCRIPTION:
Serial I/O port #1 is tested by using USART #1 as a transmitter/receiver to
transmit an 8 bit data pattern and receive the transmitted bytes through the
wrap back, RS-232 connector within a specified time window (95% through 105%).
The RS-232 wrap back connector is configured as follows:
Pin 2, CTS (clear to send); short to Pin 3, RTS (request to send),
Pin 4, DSR (data set ready); short to PinS, DTR (data terminal ready),
Pin 6, RxD (received data); short to Pin 20, TxD (transmitted data).
The following patterns are transmitted:
OAAH, 055H, OCCH, 033H, 01H, 02H, 04H, 08H, 10H, 20H, 40H, 80H.
The following baud rates are tested:
110, 150, 300, 600, 1200, 1800, 2400, 4800, 9600

TEST STEP INFORMATION:
Test Step
1
13
25
37
49
61
73
85
97

through
through
through
through
through
through
through
through
through

Baud Rate
12
24
36
48
60
72
84
96
108

110
150
300
600
1200
1800
2400
4800
9600

Data Pattern
OAAH,55H,OCCH,33H,OlH,02H,04H,08H,10H,20H,40H,80H
OAAH,55H,OCCH,33H,OlH,02H,04H,08H,10H,20H,40H,80H
OAAH,55H,OCCH,33H,01H,02H,04H,08H,10H,20H,40H,80H
OAAH,55H,OCCH,33H,01H,02H,04H,08H,10H,20H,40H,80H
OAAH,55H,OCCH,33H,01H,02H,04H,08H,10H,20H,40H,80H
OAAH,55H,OCCH,33H,01H,02H,04H,08H,10H,20H,40H,80H
OAAH,55H,OCCH,33H,01H,02H,04H,08H,1011,20H,40H,80H
OAAH,55H,OCCH,33H,01H,02H,04H,08H,10H,20H,40H,80H
OAAH,55H,OCCH,33H,01H,02H,04H,08H,10H,20H,40H,80H

5-124

ERROR MESSAGE:
1.

If an error for transmitter buffer not empty occurs,
message is displayed:

the following

*

Test FAILED--Test Step zz
Serial I/O Port 1 Test
Transmitter Buffer Not Empty
Testing Baud Rate
bbbb
Status Byte Read
= rrH
where zz should be in the range of 1 through 108
bbbb should be 110, 150, 300, 600, 1200, 1800, 2400, 4800, 9600
rr should be in the range of 00 through FF

2.

If an error for no character received occurs, the following message
is displayed:

* Test FAILED--Test Step zz
Serial I/O Port 1 Test
No Character Received
Testing Baud Rate
= bbbb
Status Byte Read
rrH
where zz should be in the range of 1 through 108
bbbb should be 110, 150, 300, 600, 1200, 1800, 2400, 4800, 9600
rr should be in the range of 00 through FF
3.

If an error for character received
message is displayed:

early

occurs,the

following

* Test FAILED--Test Step zz
Serial I/O Port 1 Test
Character Received Early
bbbb
Testing Baud Rate
Minimum Expected Count = eeeee
= ccccc
Actual Software Count
Received Data
= rrH
Transmitted Data
= ttH
where zz should be in the range of 1 through 108
bbbb should be 110, 150, 300, 600, 1200, 1800, 2400, 4800, 9600
eeeee should be 1777, 1296, 641, 320, 156, 118, 79, 40, 20
ccccc should be in the range of 00000 through 65535

5-125

rr should be in the range of 00 through FF
tt should be AA, 55, CC, 33, 01, 02, 04, 08, 10, 20, 40, 80
4.

If an error for character received
message is displayed:

late

occurs,

the

following

* Test FAILED--Test Step zz
Serial I/O Port 1 Test
Character Received Late
Testing Baud Rate
bbbb
Maximum Expected Count = eeeee
Actual Software Count
ccccc
Received Data
rrH
Transmitted Data
ttH
where zz should be in the range of 1 through 108
bbbb should be 110, 150, 300, 600, 1200, 1800, 2400, 4800, 9600
eeeee should be 2303, 1701, 859, 417, 204, 155, 99, 53, 28
ccccc should be in the range of 00000 through 65535
rr should be in the range of 00 through FF
tt should be AA, 55, CC, 33, 01, 02, 04, 08, 10, 20, 40, 80

5.

If an error for
displayed:

bad character occurs,

the following

message

* Test FAILED--Test Step zz
Serial I/O Port 1 Test
Bad character Received
Testing Baud Rate
= bbbb
Received Data
rrH
Transmitted Data
= ttH
where zz should be in the range of 1 through 108
bbbb should be 110, 150, 300, 600, 1200, 1800, 2400, 4800, 9600
rr should be in the range of 00 through FF
tt should be AA, 55, CC, 33, 01, 02, 04, 08, 10, 20, 40, 80

5-126

is

Threshold Diagnostic Subt •• t 5
TITLE:

SERIAL I/O PORT #2 TEST

TARGET LOGIC:

12E, 15B, 13B, 8E, 8D

TEST DESCRIPTION:
Serial I/O port #2 is tested by using USART #2 as a transmitter/receiver to
transmit an 8-bit data pattern and receive the transmitted bytes through the
wrap back RS-232 connector within a specified time window (95% through 105%)
The RS-232 wrap back connector is configured as follows:
Pin 2, CTS (clear to send); short to Pin 3, RTS (request to send),
Pin 4, DSR (data set ready); short to Pin 5, DTR (data terminal ready),
Pin 6, RxD (received data); short to Pin 20, TxD (transmitted data).

The following patterns are transmitted:
OAAH, 055H, OCCH, 033H, 01H, 02H, 04H, 08H, 10H, 20H, 40H, 80H.
The following baud rates are tested:
110, 150, 300, 600, 1200, 1800, 2400, 4800, 9600

TEST STEP INFORMATION:
Test Step
1
13
25
37
49
61
73
85
97

through
through
through
through
through
through
through
through
through

Baud Rate
12
24
36
48
60
72
84
96
108

110
150
300
600
1200
1800
2400
4800
9600

Data Pattern
OAAH,55H,OCCH,33H,01H,02H,04H,08H,10H,20H,40H,80H
OAAH,55H,OCCH,33H,01H,02H,04H,08H,10H,20H,40H,80H
OAAH,55H,OCCH,33H,01H,02H,04H,08H,10H,20H,40H,80H
OAAH,55H,OCCH,33H,01H,02H,04H,08H,10H,20H,40H,80H
OAAH,55H,OCCH,33H,01H,02H,04H,08H,10H,20H,40H,80H
OAAH,55H,OCCH,33H,01H,02H,04H,08H,10H,20H,40H,80H
OAAH,55H,OCCH,33H,01H,02H,04H,08H,10H,20H,40H,80H
OAAH,55H,OCCH,33H,01H,02H,04H,08H,10H,20H,40H,80H
OAAH,55H,OCCH,33H,01H,02H,04H,08H,10H,20H,40H,80H

5-127

ERROR MESSAGE:
1.

If an error for transmitter buffer not empty occurs,
message is displayed:

the following

* Test FAILED--Test Step zz
Serial I/O Port 2 Test
Transmitter Buffer Not Empty
Testing Baud Rate
bbbb
Status Byte Read
rrH
where zz should be in the range of 1 through 108
bbbb should be 110, 150, 300, 600, 1200, 1800, 2400, 4800, 9600
rr should be in the range of 00 through FF

2.

If an error for no character received occurs, the following message
is displayed:

*

Test FAILED--Test Step zz
Serial I/O Port 2 Test
No Character Received
Tesing Baud Rate
bbbb
Status Byte Read
= rrH
where zz should be in the range of 1 through 108
bbbb should be 110, 150, 300, 600, 1200, 1800, 2400, 4800, 9600
rr should be in the range of 00 through FF

3.

If an error for character received early
message is displayed:

occurs,

the

following

* Test FAILED--Test Step zz
Serial I/O Port 2 Test
Character Received Early
Tesing Baud Rate
= bbbb
Minimum Expected Count = eeeee
= ccccc
Actual Software Count
= rrH
Received Data
= ttH
Transmitted Data
where zz should be in the range of 1 through 108
bbbb should be 110, 150, 300, 600, 1200, 1800, 2400, 4800, 9600
eeeee should be 1777, 1296, 641, 320, 156, 118, 79, 40, 20
5-128

ccccc should be in the range of 00000 through 65535
rr should be in the range of 00 through FF

4.

If an error for character received
message is displayed:

late

occurs,

the

following

* Test FAILED--Test Step zz
Serial I/O Port 2 Test
Character Received Late
Tesing Baud Rate
= bbbb
Maximum Expected Count
eeeee
Actual Software Count
ccccc
Received Data
= rrH
Transmitted Data
ttH
where zz should be in the range of 1 through 108
bbbb should be 110, 150, 300, 600, 1200, 1800, 2400, 4800, 9600
eeeee should be 2303, 1701, 859, 417, 204, 155, 99, 53, 28
ccccc should be in the range of 00000 through 65535
rr should be in the range of 00 through FF
tt should be AA, 55, CC, 33, 01, 02, 04, 08, 10, 20, 40, 80

5.

If an error
displayed:

for bad character occurs,

the following

message

* Test FAILED--Test Step zz
Serial I/O Port 2 Test
Bad character Received
Testing Baud Rate
= bbbb
Received Data
= rrH
Transmitted Data
= ttH
where zz should be in the range of 1 through 108
bbbb should be 110, 150, 300, 600, 1200, 1800, 2400, 4800, 9600
rr should be in the range of 00 through FF
tt should be AA, 55, CC, 33, 01, 02, 04, 08, 10, 20, 40, 80

5-129

is

Threshold Diagnostic Subteat 6

TITLE:

TIMER 8253 COUNTER 0 TEST

TARGET LOGIC:

13F, 8D, 8E and GATE/ logic from control board

TEST DESCRIPTION:
The timer 8253 counter 0 is tested by programming counter 0 to to mode 1
(programmable one shot mode), and triggering GATEO from control board GATE/
logic. The counter 0 is then verified by reading the latched count after GATEO
been triggered.
The terminal count patterns tested are :
8000R, 4000R, 2000R, 1000R, 0800R, 0400R, 0200R, 0100R,
0080R, 0040R, 0020R, 0010R, 0008R, 0004R, 0002R, 000lR.
There are two methods for testing counter 0 in mode 1:
1.

After loading terminal count, trigger GATEO from low to high.

2.

After loading terminal count, trigger GATEO from low to high two
times. The second trigger should cause the counter to reset to the
terminal count value.

TEST STEP INFORMATION:
Test Step
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

Terminal Count Programmed

Rising Edge Trigger Pulses

8000R
4000R
2000R
1000R
0800R
0400R
0200R
0100R
0080R
0040H
0020H
0010H
0008H
0004H
0002H
0001H
8000H
4000H
2000R
1000H
0800H
0400H

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
5-130

0200H
0100H
0080H
0040H
0020H
0010H
0008H
0004H
0002H
0001H

23
24
25
26
27
28
29
30
31
32

2

2
2
2
2
2
2
2
2
2

ERROR MESSAGE:

If an error occurs, the following message is displayed:

* Test FAILED--Test Step zz
Timer 8253 Counter 0 Test
Programmable One Shot Mode
Testing Terminal count = ccccH
Expected High Count
= eeeeH
Expected Low Count
llllH
Actually Read Count
= rrrrH
where zz should be in the range of 1 through 32
cccc should be 8000, 4000, 2000, 1000, 0800, 0400, 0200, 0100,
0080, 0040, 0020, 0010, 0008, 0004, 0002, 0001.
eeee should be 7EC8, 3EC8, 1EC8, OEC8, 06C8, 02C8, 00C8, FFC8,
FF48, FF08, FEE8, FED8, FEDO, FECC, FECA, FEC9.
or 7FDD, 3FDD, IFDD, OFDD, 07DD, 03DD, OlDD, OODD,
005D, 001D, FFFD, FFED, FFE5, FFE1, FEDF, FFDE.
1111 should be 7EB8, 3EB8, 1EB8, OEB8, 06B8, 02B8, 00B8, FFB8,

FF38, FEF8, FED8, FEC8, FECO, FEBC, FEBA, FEB9.
or 7FCD, 3FCD, 1FCD, OFCD, 07CD, 03CD, 01CD, OOCD,
004D, OOOD, FFED, FFDD, FFD5, FFD1, FFCF, FFCE.
rrrr should be in the range of 0000 through FFFF

5-131

Threshold Diagnostic Subtest 7
TITLE:

GPIB INTERNAL CONTROL LINES TEST

TARGET LOGIC:

15F, 17F, 16F, 16D

TEST DESCRIPTION:
The GPIB internal control lines are tested by writing the local control bit
true.
The control bit is then verified by reading back the control status
bit.
There are 5 control lines being tested as follows:
'catn', 'cifc', 'cren', 'srq', 'end'.
NOTE: If the 'cacs' line is not true, the lines for 'catn', 'cifc', 'cren' and
'srq' are also not true.
TEST STEP INFORMATION:
Test Step

Control Bit
'catn'
'cifc'
'cren'
'srq'
'end'

1

2
3
4
5

ElUtOR MESSAGE:
If an error occurs, the following message is displayed:

*

Test FAILED -- Test Step zz
GPIB Internal Control Lines
Status Port Address OlR
Bit 7 through Bit 3 is :
atn srq ifc ren eoi
U????" and "cacs" Logic Test
"????" Status Expected
ssssssssB
"????U Status Read
= rrrrrrrrB
Falling Time Constant = ttttt
"????" Status Expected
eeeeeeeeB
"????" Status Read
= vvvvvvvvB
Rising Time Constant
= ccccc

5-132

where:

zz should be in the range of 1 to 5

???? should be catn, cifc, cren, srq, end.
ssssssss should be 10000000, 00100000, 00010000, 01000000, 00001000.
rrrrrrrr should be 00000000 through 11111111.
ttttt should be in the range of 00000 through 65535.
eeeeeeee should be 00000000.
vvvvvvvv should be 00000000 through 11111111.
ccccc should be in the range of 00000 through 65535.

NOTE: Falling and rising time constants are for diagnostic reference only.

5-133

Threshold Diagnostic Subtest 8
TITLE:

GPIB INTERNAL MPU INTERRUPT TEST

TARGET LOGIC:

15F, 17F, 16F, lSD, 17D, 21D, 17B,
18B, 19B, 20A, 20B, 21A, 19A, 20A, 16B, 21F

TEST DESCRIPTION:
The GPIB internal MPU interrupt is tested by writing local control bit true
and local command bits true.
The interrupt status bit is then verified by
reading the interrupt status.
There are four MPU interrupt logic conditions being tested: 'tint', 'srint',
'nrint' and 'cint'.
The 'lint' logic condition is associated with the GPIB
external handshake function which is not tested.
The 'INTR1/' test is associated with the 'tint' "
interrupt logic conditions.

srint',

'nrint' and

TEST STEP INFORMATION:
Test Step

MPU Interrupt Logic
'tint' and 'INTRI/'
'srint' and 'INTRI/'
'nrint' and 'INTRI/'
'cint' and 'INTRI/'

1

2
3
4

ERROR MESSAGE:
1.

If an INTR1/ error occurs, the following message is displayed:

* Test FAILED -- Test Step zz
GPIB Internal Interrupt Line
gint/ lint tint cint nrint srint get/ nins/
"?????" Interrupt Line Test
GPIB INTRI/ Not Generated
where zz should be in the range of 1 through 4

????? should be tint, srint, nrint, cint.

5-134

'cint'

2.

If an interrupt
displayed:

status

error occurs,

the following

message

*

Test FAILED -- Test Step zz
GPIB Internal Interrupt Line
gint/ lint tint cint nrint srint get/ nins/
"?????" Interrupt Line Test
aaaaaaaaB
Status 1 Expected
bbbbbbbbB
Status 1 Read
Status 2 Expected
ccccccccB
Status 2 Read
= ddddddddB
Status 3 Expected
= eeeeeeeeB
Status 3 Read
= ffffffffB
Status 4 Expected
ggggggggB
Status 4 Read
hhhhhhhhB
where zz should be 1 through 4

????? should be tint, srint, nrint, cint
aaaaaaaa should be 10000010.
cccccccc should be 11111111, 10000010.
eeeeeeee should be 00100010, 00000110, 00001010, 00010010.
gggggggg should be 10000010.
bbbbbbbb should be in the range of 00000000 through 11111111
dddddddd should be in the range of 00000000 through 11111111
ffffffff should be in the range of 00000000 through 11111111
hhhhhhhh should be in the range of 00000000 thrOllgh 11111111

5-135

is

Threshold Diagnostic Subtest 9

TITLE:

GPIB INTERNAL DATA REGISTER TEST

TARGET LOGIC:

l8E, 19E, 18D, 19D, 20E, 21E, 20F

TEST DESCRIPTION:
The GPIB internal data register is functionally tested by writing a data byte
pattern to the data register or parallel poll response register.
The data is
then verified by reading the data from the input register.
There are 12 data patterns tb be tested :
OAAH, 55H, OCCH, 33H, OlH, 02H, 04H, 08H, 10H, 20H, 40H, 80H.
There are two output registers to be tested :
1.

Data output register (18E)

2.

Parallel poll response register (19E).

TEST STEP INFORMATION:
Test Step
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

Register Under Test

Data Pattern

data output register
data output register
data output register
data output register
data output register
data output register
data output register
data output register
data output register
data output register
data output register
data output register
parallel poll response
parallel poll response
parallel poll response
parallel poll response
parallel poll response
parallel poll response
parallel poll response
parallel poll response
parallel poll response
parallel poll response
parallel poll response
parallel poll response

OAAH
55H
OCCH
33H
01H
02H
04H
08H
10H
20H
40H
SOH
OAAH
55H
OCCH
33H
01H
02H
04H
OSH
10H
20H
40H
SOH

5-136

ERROR MESSAGE:
1.

If an error occurs in the data
message is displayed:

output

register,

the

following

* Test FAILED -- Test Step zz
GPIB Data Register Test
Data Out Register Testing
Data Register Expected
eeH
Data Register Read
= rrH
where zz should be in the range of 1 through 24
ee should be AA, 55, CC, 33, 01, 02, 04, 08, 10, 20, 40, 80
rr should be 00 through FF

2.

If an error occurs in the
following displayed:

parallel poll response

register,

* Test FAILED -- Test Step zz
GPIB Data Register Test
Parallel Poll Response
Data Register Expected = eeH
Data Register Read
rrH
where zz should be in the range of 1 through 24
ee should be AA, 55, CC, 33, 01, 02, 04, 08, 10, 20, 40, 80
rr should be 00 through FF

5-137

the

K450 STORAGE CONTROLLER BOARD DIAGNOSTIC
DIAGNOSTIC OVERVIEW
This section describes subtests executed on the K450 Storage Controller Board,
how error reporting is done, and the concept behind each subtest program.
The K450 Storage Controller Board has future provisions for installing a UART.
This Diagnostic does not test any of the UART components.
There are six subtests written for the Storage Controller Board.
Each of
these subtests is described individually on the following pages.
Parameters
for Loop on Error, Error Count, and Pass Count Update are incorporated into
each subtest.
All

">"

error messages are preceded by a
prefix.

"*"

.

The information messages use

the

Early exit of each subtest is accomplished by pressing the STOP key.

ASSUMPTIONS
This series of tests assumes that two other boards are installed in the K450
and are functional, an operational MPU Board as well as the Keyboard/Display
Board must be present.

SUBTEST CATEGORIES
1.
2.
3.
4.
5.
6.

6116 Data Integrity Test
6116 Address Integrity Test
FDC Seek Test
Fixed FDC Write/Read Test
Random FDC Write/Read Test
FDC/DMA Address Logic Test

5-138

ERROR COUNT CATEGORIES

1.

2.
3.
4.
5.
6.
7.

B.
9.
10.
11.
12.
13.
14.
15.
16.
17.

lB.
19.
20.
21.
22.
23.
24.
25.
26.
27.

2B.
29.
30.
31.
32.

Subtest 1
Subtest 2
Subtest 3
Subtest 4
Subtest 5
Subtest 6
Seek Command Error Count
Recalibrate Command Error Count
Write Command Error Count
Read Command Error Count
Drive A Error Count
Drive B Error Count
Side 0 Error Count
Side 1 Error Count
Soft Error Count
Hard Error Count
Not Ready Error Count
Head Address Error Count
Ready Changed State Error Count
Missing Address Mark Error Count
Write Protected Error Count
Sector Not Found Error Count
FDC Overrun Error Count
FDC Int Timout Error Count
Access beyond End of Track Error Count
Missing Data Address Mark Error Count
Bad Track Error Count
Wrong Cylinder Error Count
Data Error CRC Error Count
Control Mark : Deleted Data Encountered Error Count
Unformatted Diskette Error Count
Diagnostic Program Error Count

5-139

Storage System Controller Subtest 1

TITLE:

6116 DATA INTEGRITY TEST

PURPOSE:
This subtest confirms the ability of the D}lA hardware to sucessfully write
data into the 4K area of 6116 RAM.
The integrity of the RAM is checked by
running several patterns through the Memory.
The RAM is not directly addressable, all access is through the DMA controller.

TARGET HARDWARE:

SD, SE, SF, SH, 6E, 6F, 7E

TEST DESCRIPTION:
It is not possible to Write directly to the 6116 RAMs.
All access is through
the DMA controller.
Data is written to the DMA controller and the controller
passes it on to the RAM.
Reading is accomplished through the same type of
cycle.
Various Data patterns are written to the RAM then Read back.
If a
miscompare occurs, an Error message is printed.

TEST STEP INFOBMATION:
Test Step

Value Written
1
2
3
4
S
6
7

8
9

10
11
12
13

0
AAH
SSH
CCH
33H
01H
02H
04H
08H
10H
20H
40H
80H

S-140

ERROR MESSAGE:
If any errors are detected, this subtest displays the following message:

* Test FAILED--Test Step
RAM Data Error
Value Written = aaH
Value Read
bbH
ccccH
Address Count
ddH
DMA Status
where

xx =
aa
bb
cccc
dd =

xx

test step number
00 - FF
00 - FF
= 0000 - OFFF
00 - FF

5-141

Storage System Controller Subtest 2

TITLE:

6116 ADDRESS INTEGRITY TEST

PURPOSE:
The purpose of this test is to selectivly write 1 byte of Data into the 4K of
RAM on the storage controller board which has been preset to
zero.
Verification is then made to confirm the only place the RAM is written to is
the indicated Address.

TARGET HARDWARE:

sD, sE, SF, sH, 6E, 6F, 7E

TEST DESCRIPTION:
It is not possible to Write directly to the 6116 RAMS.
All access is through
the DMA controller.
Data is written to the DMA controller and the controller
passes it on to the RAM.
Reading is accomplished through the same type of
cycle.
Various Data patterns are written to the RAM then Read back.
If a
miscompare occurs, an error message is printed.
All of the RAM in this test is preset to zero then the indicated Address is
written with the value Oaah.
All of RAM is then Read to verify the written
Data. If a miscompare is detected then an error message is displayed.

TEST STEP INFORMATION:
Test Step
1

2
3
4

5
6
7
8
9

10
11
12

Indicated Address
OOOOH
0001H
0002H
0004H
0008H
0010H
0020H
0040H
0080H
0100H
0200H
0400H

5-142

ERROR MESSAGES:

If any errors are detected, this subtest displays the following message:

* Test FAILED--Test Step xx
All Storage Controller RM1 Set to Zero.
Wrote aaH to Address bbbbH
Read ccH at Address ddddH
where

xx = test step number
aa = 00 - FF
bbbb = 0000 - OFFF
cc = 00 - FF
dddd = 0000 - OFFF

5-143

Storage System Controller Subtest 3

TITLE:

FDC SEEK TEST

PURPOSE:
The purpose of this subtest is to verify operation of the seek process on one
or both Disk Drives.
2R, 3D, 3E, 3F, 3R, 4C, 4D, 4E, 4F, 7D, 7F

TARGET HARDWARE:

TEST DESCRIPTION:
The FDC is commanded to perform seeks to the given Track as outlined below.
Tracks are accessed from Track 0 to 39, and 39 to O. Finally, an alternating
pattern of seeks spiraling from outermost to innermost Tracks is performed.
As these operations are
controller is monitored.
displayed.
This

operation

sent to the FDC controller, the status of the
If an error is detected, an error message is

is repeated for all selected Drive and Side options selected.

TEST STEP INFORMATION:
Test Step Number
1 - 40
41- 80
81- 120
121-160
161-200
201-240
241-280
281-320
321-360
361-400
401-440
441-480

Drive/Side

Disk Action

A
A
A
A
A
A

seek 0-39 seek 39-0
spiral inward
seek 0-39
seek 39-0
spiral inward
seek 0-39
seek 39-0
spiral inward
seek 0-39
seek 39-0
spiral inward

B
B

B
B

B
B

/
/
/
/
/
/
/
/
/
/
/
/

0
0
0
1
1
1
0
0
0
1
1
1

ERROR MESSAGES:
If any errors are detected,
Appendix 1.

this subtest displays the error messages found in

5-144

Storage System Controller Subtest 4
TITLE:

FDC WRITE/READ TEST

PURPOSE:
The purpose of this subtest is to verify the Storage Controller Board's
capability to Write and Read back information on all Tracks of the Disk Drive.

TARGET HARDWARE:

2H, 3D, 3E, 3F, 3R, 4C, 4D, 4E, 4F, 7D, 7F
2A, 2B, 2C, 3A, 3B

TEST DESCRIPTION:
The FDC is Commanded to Write Data to all Tracks on a given Disk surface on a
sector by sector basis. If the Track written to is either Track 0 or Track 39
then all sectors
are written to. On other Tracks, only sector 1 is actually
tested. The Data
is then Read back and compared to the pattern written. If
a miscompare occurs, an error message is displayed.
As these operations are sent to the FDC controller, the status of the
controller is monitored and if an error is detected an error message is
displayed. This operation is repeated for all selected Drive and Side options
selected.

TEST STEP INFORMATION:
Test Step Number

Drive/Side

1 - 40

a/O

41 - 80
81 - 120
121 - 160

a/I
b/O
b/1

Disk Action
Write/Read/compare
Write/Read/compare
Write/Read/compare
Write/Read/compare

ERROR MESSAGES:
If

any

errors are detected, this subtest will display the following message:

*

xxx
Test FAILED--Test Step
Sector Compare Error
= Oaa
Track Number
Sector Number
OOb
Occch
Address Within Sector =
Wrote ddh
Read eeh

5-145

where

xxx
aa

= test step number
= a - 39

bb = a
- 8
ccc = 000 - FFF
dd = 00 - FF
ee = 00 - FF

NOTE: Also see Appendix 1.

5-146

Storage System Controller Subtest 5
RANDOM FDC WRITE/READ

TITLE:
PURPOSE:

The purpose of this subtest is to verify the Storage Controller
capability to Write and Read back information on 63 random locations
Disk Drive.

TARGET HARDWARE:

Board's
of the

2R, 3D, 3E, 3F, 3R, 4C, 4D, 4E, 4F, 7D, 7F
2A, 2B, 2C, 3A, 3B

TEST DESCRIPTION:
This subtest generates random Data and performs 63 random Read/Write cycles.
As Data is written it is then Read back and compared. If a miscompare of data
occurs, it is reported via an error message. As these operations are sent to
the FDC controller, the status of the controller is monitored and if an error
is detected an error message is displayed. This operation is repeated for all
selected Drive and Side options selected.

TEST STEP INFORMATION:
Test Step Number

Drive/Side

Disk Action

1- 64
65- 126
127- 190
191- 254

a/O
a/I
b/O
b/1

Write/Read/compare
Write/Read/compare
Write/Read/compare
Write/Read/compare

Dl.OR MESSAGES:

If

any

errors are detected, this subtest will display the following message:

* Test FAILED--Test Step xx
Sector Compare Error
Track Number
= Oaa
Sector Number
= OOb
Address Within Sector = cccR
Wrote ddH
Read eeH
where

xx
aa
bb

= test
=a =a-

step number
39
8

ccc = 000 - FFF
dd = 00 - FF
ee = 00 - FF

NOTE: Also see Appendix 1.
5-147

Storage System Controller Subteat 6

TITLE:

FDC/DMA ADDRESS LOGIC

PURPOSE:
The purpose of this subtest is to verify integrity of the Address
logic between the DMA controller and the floppy Disk controller.

TARGET HARDWARE:

Counters

2H, 3D, 3E, 3F, 3R, 4C, 4D, 4E, 4F, 7D, 7F
2A, 2B, 2C, 3A, 3B

TEST DESCRIPTION:
The Data pattern, Oaah, is written to the indicated Addresses on the Storage
Controller Board.
The entire RAM contents are written to Track 22 on the
first available Drive.
The RAM is zeroed out then a Read sector Command is
issued.
The RAM is then analyzed to determine if the DMA controller has
placed Data in the original locations.
As these operations are sent to the FDC controller, the status of the
controller is monitored and if an error is detected an error message is
displayed.
This

operation

is repeated for all selected Drive and Side options selected.

TEST STEP INFORMATION:
Test Step
1

2
3
4
5
6
7
8
9

10
11

12
13
14

Address Range
OOOOH
0001H
0002H
0004H
0008H
0010R
0020H
0040R
0080R
0100R
0200H
0400H
0800H
1000H

-

01FFH
0200H
0201H
0203H
0207H
020FH
021FH
023FH
027FH
02FFH
03FFH
05FFH
09FFH
IlFFH

5-148

ERROR MESSAGES:
If any errors are detected this subtest will display the following message:

* Test FAILED--Test Step xx
All storage Controller RAM set to Zero.
Unique Testing Address Range = llllH to hhhhH
Data in Address Range = ddH
Checking Data at Address = aaaaH
Data Expected
eeH
Data Read
rrH
where

xx =
1111
hhhh
dd =
aaaa
ee
rr =

test step number
- OFFF
= 0000 - OFFF

= 0000

AAH
= 0000 - OFFF
00 - FF
00 - FF

NOTE: Also see Appendix 1.

5-149

Storage System Controller Diagnostic Appendix 1
Error Messages Common to all Disk Activity:
Subtests 3-6 all use a common routine for Disk operations which generate
following error message:

* Test FAILED--Test Step
Retrying Disk Command
Retry Count = b
Disk Command: c
Drive
d
Head
= e
Track
Off
g
Sector
msg
where

aa

aa = test step number
b = number of times Disk Command has been attempted
c = seek Command,
Read id Command,
recalibrate Command,
Write Track Command,
Write sector Command,
Read Track Command,
Read sector Command.
d = a or b
e = 0 or 1
ff = 0 to 39
g = 1 to 8
msg = Disk Drive Not Ready.
Head Address Error.
During Command, Ready Changed State.
Missing Address Mark.
Write Protected.
Sector Not Found.
FDC Over-run Error.
Data Error (CRC).
FDC Interrupt Timeout Error.
Access Beyond End of Track.
Missing Data Address Mark.
Bad Track.
Wrong Cylinder.
Data Error (ere).
Control Mark: Deleted Data Encountered.
Not a Formatted Disk.

5-150

the

Chapter 6

OPTIONS INSTALLATION
GENERAL
This chapter describes procedures for installing the K450 Input
Expansion
Option and K450 Disk Storage System (DSS) Option equipment at the user's site.
This optional equipment is provided in kit form for users who desire to expand
the operating capabilities of their existing equipment. Once installed, the
K450 automatically recognizes the new hardware configuration when powered up.
The Configuration Screen indicates which optional features are available for
the user.
The the system responds when the new features are accessed.
The
following kits are available:
o

K450 Input Expansion Option Kit, Part Number 0121-0030-10

o

K450 Disk Storage System Option Kit, Part Number 0114-0468-20

Each kit contains installation instructions for the equipment option. The
internal wiring harness assemblies that interface with optional printed
circuit board edge connectors are installed in the K450 chassis by the factory
to facilitate the addition of options by the user.
These harness assemblies
are located at the upper right-hand side of the card cage. Individual cables
contained within the harness are labeled for identification.
The entire
bundle of cables is exposed when the top cover is removed from
the K450
chassis.
The K450 Input Expansion Option kit contains a Data printed circuit board
assembly and a set of input cables, probes and grabbers which provide 16
additional inputs to the K450. A separate kit is required for Input Sections B
and C.
The DSS Option Kit contains the dual disk drive assembly and mounting hardware
which includes a power cable assembly and signal cable assembly that must be
installed by the user.
The associated diagrams and wiring details are
described in the installation procedure. The DSS functional description and
operation
are
described in a separate K450 User's Manual
Addendum,
Publication Number 0121-0084-10, which is included in the kit.
Card Cage Arrangement
The board ejector tabs on each printed circuit board are numbered to
correspond to the assigned slot location in the card cage. For the most part,
the assigned board is dedicated to reside in its assigned slot location except
where specified below for the three Data Boards. The installed boards are
secured in the card cage by a slotted retainer bar, which is fastened to the
top of the card cage by two screws.
Data Board Input Configurations
Three Data Boards reside in slot locations A2, A3 and A4. The ejector tabs
are not numbered because each board is identical and interchangeable for these
slots.
Each slot location has a particular Input Section as described in the
installation procedure.
6-1

The
K450 unit
configured for 16 Inputs (Section A) uses one Data Board
installed in slot location A4. Units configured for 32 inputs (Sections A and
B) use two Data Boards installed in slot locations A4 and A3.
Units configured for 48 inputs (Sections A, B, C) use another Data Board
installed in slot location A2. The expansion for Input Section C requires
jumper connections on the Clock Board to be repositioned to convert the BR and
BS Sample Clocks into Latch Clocks as described in the installation procedure.
INSTALLATION OF K450 INPUT EXPANSION OPTION
Unpacking and Inspection
The Data Board and probes supplied for the
Expansion Option provide 16
additional channels for Input Sections B or C.
A separate kit is required to
install the option at each Input Section.
All hardware items required to
install and operate this option at the user's site are contained in the kit.
The components provided for each kit are described in Table 6-1.
Table 6-1.
QUANTITY

Expansion Option Component a
PART NUMBER

DESCRIPTION

1

0121-0015-10

Data Board, Printed Circuit
Board Assembly

2

0117-0294-30/-50

Input Cable Set

22

7100-0116-10

Grabbers

2

0117-0099-10

Probe Subassembly

1

0121-0031-10

Instruction Sheet

1

0117-0740-10

Label, Active Probe Pod

1

0117-0208-01

Label, Output Cable

All equipment was thoroughly inspected and checked out at the factory prior to
packaging for shipment.
After removing the equipment from its shipping
container, inspect for damage that might have occurred during shipping. Refer
to the shipping papers to verify all items were received.
If equipment received from the carrier is incomplete or damaged, do not
install the equipment.
File a claim with the shipping firm immediately, and
notify Gould Inc.,
Design and Test Systems Division Customer Service
department at once.
Gould Inc., DTD will arrange for replacement of the
equipment without waiting for settlement of the claim against the carrier.
Installation Procedure
Prior to beginning the option installation, position the carrying handle of
the K450 to the front of the machine so that the unit rests flat on the work
surface.

6-2

********************

*
*
*
*
*
*
*
*
*
*

WARNING
Disconnect the 115/240 Vac source
to the K450 prior to installing
any options. Otherwise, a shock
hazard exists. Also, high voltage
is present on the CRT and Display
Board.

*
*
**
*
*
*
*
*
*

********************
The following steps outline the procedure necessary to install the Data Board
for Input Section B or C on K450 units that do not contain the DSS option. If
the DSS Option is present in lieu of the top chassis cover, refer to the DSS
Option Removal Procedure at the end of this section.
1.

Remove the six Phillips-head screws securing the top cover to
chassis, and carefully lift cover from the unit.

the

2.

Remove the two screws that secure the card retainer bar to the top
of the card cage and lift it from the chassis.
The card cage
arrangement is shown in Figure 6-1.

3.

Carefully disconnect the cable harnesses from board sockets at
card cage locations A3, A4 and AS, noting which sockets are
associated with each cable.

4.

Position the
Expansion Option "Data Board with the solder side
toward the power supply of the unit.
Carefully insert the Data
Board into the designated card slot, A2 for Section C Inputs or A3
for Section B Inputs (refer to Figure 6-1).
Ensure the Data Board
is seated firmly in the motherboard sockets.

5.

If the Input Section C Data Board is being installed, remove the
Clock Board from the card cage to change the jumper conne~tions.
Rearranging the jumper connections enables the Input Section C clock
inputs and
routes the BR and BS clocks into the user specified
Latch Clock equation.
The K450 software will not recognize clock
inputs at Section C unless these jumper connections are completed.

6-3

T " " ' " " - " - - - - - C l O C K BOARD
1 ClOCK BOARD

r - - - - - THRESHOlDIGPIBJR5-232 BOARD

HARNESS CONNECTOR J2

~----------T--~~~~~------~~~
:3 OATA BOARD HARNESS
CONNECTORS. J2

Figure 6-1.

SECTION C DATA
' - - - - SECTION B DATA
' - - - - - SECTION A DATA

I

REARQ

3 DATA BOARDS
(TYPICAL)

K450 Card Cage Arrangement, Top View

The eight jumpers are contained at board location column 3, row K.
These jumpers are to be relocated to pins from the common/lower row
to pins at the common/upper row, to provide the following connection
points:
TI-T2, T4-T5, T7-T8, TIO-TII
T13-T14, TI6-T17, T19-T20, T22-T23
6.

Replace

the

card cage retainer bar and secure with the two screws.

7.

Locate the unattached ribbon cables BF and BR (for Section B Data
Board) or CF and CR (for Section C Data Board).
See Figure 6-2.
Install the ribbon cable connector on JI near the front of the
machine.
The dark-brown wire braid on the connector should be
located to the front of the machine.

NOTE: If J1 is installed backwards, the equipment is not damaged.
Reversing the connector
The data at DO is displayed on channel D7.
corrects this condition.
Install the ribbon cable connector on J2 near the rear end of
machine. See Figure 6-2.
6-4

the

CONNECTOR P3
RESERVED FOR FUTURE
COMMUNICATIONS 1/0 UNK

1 1 - - - - - DATA BOARD B

U - - - - - - DATA BOARD A
~-------CLOCK

'JJ-ooI_--------

BOARD

THRESI:IOLD/GPIBI
RS-232 BOARD

Figure 6-2. K450 Ribbon Cable Connections at Card Cage
Ensure

each

8.

Replace the harness connectors removed in Step 3.
harness is connected to its socket. See Figure 6-2.

9.

Ensure the harness cables are properly positioned and do not
interfere with reinstallation of the top cover.
Reinstall the top
cover.

10.

Reinstall the six retaining screws.

11.

Reconnect the 115/240 Vac source to the K450. Operation of the K450
with 32 or 48 expanded inputs is described in the K450 User's Manual.

Removal of DSS Option Assembley
The DSS assembly must be removed from the K450 chassis to gain access to the
card cage or other components.
Use the following procedure to accomplish
removal:
1.

Remove the four Phillips-Head screws securing the top cover to the
DSS assembly, and carefully lift the top cover from the DOS housing.

2.

Remove the two screws that secure the DSS base and ground connection
lug to the top of the K450 chassis.

3.

Remove the four screws (2 on each side) that secure the DSS assembly
to the K450 chassis.

NOTE: Disconnect the power harness and I/O ribbon cable at the DSS
assembly to remove it from the K450 chassis.
6-5

4.

Lift the DSS assembly from the K450 chassis. Hold the DSS assembly
suspended and disconnect the power harness plug.
Disconnect the
I/O ribbon cable from the interface connector, J3, on the Controller
Board in the DSS assembly.
Pull the I/O cable through the access
slot under the printed circuit board so that the DSS assembly is
separated from the K450 chassis.

5.

Position the DSS assembly on its side to the left of the K450
chassis.
The front of the DSS assembly should be located at the
front of the K450 chassis.

6.

Reinstall the DSS assembly by reversing the removal procedure.
Ensure that the I/O signal cable is routed through the access slot
under the printed circuit board.
Ensure it is properly folded at
the Controller Board connector (J3).
Ensure it does not bind, nor
interfere with other internal components, when the DSS assembly is
positioned on top of the K450 chassis.

INSTALLATION OF DSS OPTION
Unpacking and Inspection
The Disk Storage System Option allows the user to store K450 set up
parameters, trace information and data for later retrieval, and to load and
execute the disk-based diagnostic routines.
All hardware items required to
install and operate the Disk Storage System (DSS) option at the user's site
are shipped in packaged units.
External interface cables are included for
connecting all components in the system. Components supplied for the DSS
Option are described in Table 6-2.

Table 6-2.

DSS Option Components

PART NUMBER

DESCRIPTION

1

0114-0468-20

DSS Option

1

0121-0084-10

K450 Disk Operating System User'S
Manual Addendum

1

0121-0065-10

K450 Storage Operating System
Diskettes (Set of 2)

1

0121-0094-20

K450 DSS Option Instruction Sheet

QUANTITY

Assembl~

All equipment was thoroughly inspected and checked out at the factory prior to
packaging for shipment.
After removing the equipment from its shipping
container, inspect for scratches, dents or other damage that might have
occurred during shipping. Refer to the shipping papers to verify that all
items were received.
If equipment received from the carrier is incomplete or damaged, do not
install the equipment. File a claim with the shipping firm immediately, and
notify Gould Inc.,
Design and Test Systems Division Customer Service
department at once.
Gould Inc., DTD will arrange for repair or replacement
of the equipment without waiting for a settlement of the claim against the
carrier.

6-6

Installation Procedure
Prior to beginning the option installation, position the carrying handle of
the K450 to the front of the machine so that the unit rests flat on the work
surface.

********************

*
WARNING
*
** Disconnect the 115/240 Vac source
* to the K450 prior to installing
* any options. Otherwise, a shock
* hazard exists. Also, high voltage
* is present on the CRT and Display
* Board.
*

*
*
**
*
*
*
*
*
*

********************
The following steps outline the procedure necessary to install the DSS
on the K450 chassis:

option

1.

Remove the six Phillips-head screws securing the top cover to
K450 chassis, and carefully lift the cover from the unit.

2.

Remove the four Phillips-head screws securing the top cover to the
DSS assembly, and carefully remove the top cover.
Note the
position of the ribbon cable connectors to the disk drives (see
Figures 6-3 and 6-4). Disconnect the I/O ribbon cable connectors
from the Disk Controller Board and remove the cable from the DSS
assembly. (This helps to position and fold the I/O cable after the
DSS assembly is placed on the K450 chassis.)

~

1~--"1I~

Figure 6-3.

DOS POWER HARNE•• CONNECTOR
INTERFACE PLUG

DSS Power Supply Harness Connection, Top View
6-7

the

BASE MOUNTING HOLE
(2 PLACES)

STORAGE SYSTEM
CONTRO L BOARD

-----------..,.

""

"

------- ---,---~
I

I

I

I

I

1/0 RIBBON CABLE
RO UTED UNDER
CONTRO L BOARD

DRIVE INTERFACE
VO RIBBON CABLE

DRIVE B POWER HARNESS

DRIVE A
POWER HARNESS

----_/

/

DRIVE A

DRIVE B

GROUND LUG

VO R1380N CABLE
CONNECTOR
(TO DISPLAY BOARD)
P4 CONNECTO R

DO S TOP COVER
MOUNTING HOLE
(4 PLACES)

FRONT

Q
Figure 6-4.

K450 DSS Assembly, Top View With Cover Removed

3.

Connect the single ribbon connector to the Data Display Board
connector P4, located near the center of the unit. See Figure 6-S.
Remove the card cage retainer bar and raise the Data Display Board
approximately 2 inches in the card cage to gain access to the P4
connector. Pin 1 is at the top of connector P4.

4.

Position the DSS assembly on the K4S0 chassis and route the
ribbon cable through the access slot in the base of the
assembly. Do not connect the I/O ribbon cable at this time.

S.

Locate the DSS power harness connector cable near the power supply
which is installed by the manufacturer for interfacing the
DSS
option (See Figure 6-3).
Connect the power harness connector plug
from the DSS unit to the power supply harness connector through the
rear access slot.

6.

Fold the I/O ribbon cable under the Disk Controller Board so that
it is routed to the left Controller Board connector, J3. See Figure
6-4. Pin 1 is at the front of connector J3. Connect the I/O ribbon
cable to the Controller Board connector.
Ensure that no cables
interfere with the final positioning of the DSS assembly, and seat
the assembly on the top of the K4S0 chassis.
6-8

I/O
DSS

DISPLAY BOARD

Firure 6-5.

Disk Drive I/O Ribbon Cable Connection

7.

Install the six retaining screws, the two screws that secure the DSS
Base and ground lug to the top of the K450 chassis.
Install the
four screws that secure the sides of DSS unit to the K450 chassis.

8.

Reinstall the DSS top cover with the four

9.

Reconnect the 115/240 Vac source to the K450 unit.

6-9

retain~ng

screws.

Chapter 7
SCHEMATICS AND DRAWINGS
GENERAL

This chapter contains Schematic Diagrams, Assembly Drawings, Parts Lists and
Wire Lists for the K450 Logic Analyzer. The drawings are arranged sequentially
by drawing number.
LIST OF DRAWINGS
The following drawings are provided in this chapter:
DRAWING NUMBER
0112-0204-10
0114-0120-10
0114-0121
0114-0170-30
0114-0171
0114-0468-20
0114-0475-10
0114-0476
0114-2010-60
0114-2011
0114-2024-10
0114-3010-60
0117-0021-10
0117-0040-30
0117-0099-10
0117-0117-10
0117-0123-10
0117-0133-10
0117-0294-30, -50
0117-0540-10
0117-0541
0120-0025-01
0120-0026
0120-0042-01
0120-0043-01
0120-0044-01
0120-0080-10
0120-0081
0120-0145-10
0121-0006-10
0121-0010-10
0121-0011
0121-0015-10
0121-0016

DESCRIPTION
Keyboard Cable Assembly
Control Board Assembly
Control Board Schematic
Threshold/GPIB/RS-232 Board Assembly
Threshold/GPIB/RS-232 Board Schematic
DOS Option Assembly
DOS Controller Board Assembly
DOS Controller Board Schematic
Display Board Assembly
Display Board Schematic
Mother Board/Power Supply Cable Assembly
Display Board Assembly
Crt Cable Assembly
Keyboard P.C.B. Assembly
Probe Subassembly
Power Switch Cable Assembly
CRT Assembly
Chassis Ground Cable Assembly
Input Cable Set
MPU Board Assembly
MPU Board Schematic
Input Board Assembly
Input Board Schematic
Input Board Cable Assembly
Probe Test Cable Assembly
Data Input Cable Assembly
Mother Board Assembly
Mother Board Schematic
DOS Power Harness Assembly
Chassis Top Assembly
Clock Board Assembly
Clock Board Schematic
Data Board Assembly
Data Board Schematic

7-1

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GOULD INC., DESIGN AND TEST DIVISION

PAGE

BILL OF MATERIAL

----------------

AS OF

02/12/86

0114-0120--10
1'10DEL:

K205

ITEM
PART NUMBER

ff

DESCRIPTION

QTY PER
REFERENCE
ASSEMBLY UM DESIGNATOR

1 (I

P0114-0120
00114-0121
0114-0122-10
3700-0057-10
1800-0105-10
1800-0254-10
1 e.OO-0349-1 0
6000-0307-10
7000-0120-10
1850-0103-10
1850-0097-10
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GOULD INC., DESIGN AND TEST DIVISION

PAGE

2

BILL OF MATERIAL
================
AS OF 02/12/86
0114-0120-10
MODEL : ~(2 OS

ASSY,PCB,CONTROL,Kl01

I1EM
PART NUMBER

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DESCRIPTION

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BILL OF MATERIAL

----------------

AS OF
0114-0170-30
MODEL:

02/12/86

ASSY,PCB,THRESHOLD,GPIB,RS232

I TEt1

PART NUMBER

ti

DE.SCRIPTION

QTY PER
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ASSEMBLY UM DESIGNATOR

0 D0114-0170
0 D0114-0171
1 0114-0172-10
3 7000-0120-10
5 1700-0086-10

DWG,ASSY,THRESHOLD/GPIB/RS232
DWG,SCHEM THRESHOLD/GPIB/RS232
FAB)PCB,THRESHOLD/GPIB,RS232
CARD EJECTOR NYLON 6/6
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IC

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8 1820-0077-10
9 1820-0076-10

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IC
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REF-01EJ VOLT REF
MP7S3'3CO MULT DAC
MP75080IJN ANA MULT

1 0 1820-0075-10
1 1 1800-0343-10
12 1800-0344-10
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1 4 1700-0102-10
15 1800-0200-10
1 6 t800-0125-10
1 7 1800-0231-10

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P8253-S PROG INTER
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74LS161N 20CNTR, SYN, BIN
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EA 80
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98,40,60
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1

PAGE

(; a UL 0 INC. IDE S I GNAN 0 T EST D I V I S ION

2

BILL OF MATERIAL

---------------AS OF

0114-0170-30

02/12/86

ASSY,PCB / THRESHOLD,GPIB,RS232

MODEL:
II EM
1t

PART NUMBER

343000-"2201-10
3S 3000-1001-10
36 JOOO-2200-10
37 3000-1004-10
38 3000-2006-10
39 3000-5106-10
40 3000-2701-10
41 3000-2002-10
45 3100-1003-10
46 3100-4990-10
47 3000-]]02-10
48 3300-0070-10
49 3300-0060-10
50 3300-0012-10
51 3700-0048-10

DESCRIPTION

RES/2.2K S/.,1/4W,C
RES, 1K,5%, 1/4W,C
RES,220,s%/1/4W,C
RES,lM,5%,l/4W,C
RES,20 / S%,l/4W,C
RES,S1,5%,l/4U,C
RES,2.7K,s%,l/4W,C
RES,2K,S%,1/4W,C
RES,100K,1%,1/8U,MF
RES,499 1Y.,l/8U,MF
RES,33K,S%,l/4W,C
POT,10K,0.SU,107. 20T,PC,RTANG
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REFERENCE
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6
4

3
2
1
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3
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2
3
4

2
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EA
EA
EA
EA
EA
EA
EA
EA
EA
EA
EA
EA
EA
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R3S-3S
R16,22,32
R40,41
R31
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2
2
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58 1000-0003-10
59 1300-0028-10
60 1400-0019-10
61 3000-2001-10
62 ]000-3001-10
63 4010-0103-10

6S 4010-0470-10

66

4010-0471-10

67 4010-0104-10

68
69
71
72

4400-0045-10
4400-0043-10
6000-0417-10
6000-0388-20

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9

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TRAN 2N3906
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EA 5
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EA RP7 / 8
EA Rl0,12
EA CR 1 12
EA Q2
EA Q3
EA R27
EA R29
EA 14-32
34-37
39-41
43-51
75,78,79
9,11,60,61
Cl,2,6,7
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53-57,59
C3-5,8,10
EA C77
EA 58
C63-72,S2
EA C73,74
EA C76
EA P4
EA P3

GOULD INC.) DESIGN AND TEST DIVISION

PAGE

3

BILL OF MATERIAL
================
AS OF 02/12/86
0114-0170-30
f'10DEL:

ITEM

DESCRIPTION

PART NUMBER

#

74
75
76
77
78
86

6100-0119-10
6100-0120-10
6100-0156-10
6100-0122-10

6100-0151-10
9000-0054-10

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16 PIN DIP LO-PROFIL
18 PIN
SKT
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GOULD INC.,

DESIGN AND TEST DIVISION

PAGE

BILL OF MATERIAL
================
AS OF
02/12/86
0114-2010-60
MODEL:
K450
ITEM
PART NUMBER

~

0 n0114-2010
0 00114-2011
1 0114-2012-10
-:;.
..... 3000-2000-10
3 3000-3307-10
4 3050-4700-10
S 3000-8206-10
6 3000-4700-10
7 3000-2201-10

8

3000-1002-10

DESCRIPTION

DWG,ASSY,DATA DISPLAY
DWG,SCHEM,DATA DISPLAY
FAB,PCB,DATA DISPLAY
RES,200,S%,1/4W,C
RES,3.3,5/.,1/4W,C
RES,470,S%,1/2W/C
RES, 82,5iC 1 14W, C
RES,470,S%,1/4W,C
RES,2.2K,S/.,1/4W,C

RES,10K,5%}1/4W,C

9 3000-5601-10
1 0 3000-8201-10
1 1 3000-4702-10
1 2 3000-1203-10
1 3 3000-2203-10
14 ]000-2703-10
15 3000-5103-10
1 7 3000-1004-10
1 8 3050-2200-10
1 9 3050-1007-10
20 30S0-3906-10
21 3050-1000-10
23 3000-2202-10
24 3200··0008-10
25 3070-1501-10
26 3100-7506-10
27 3100-6040-10
28 3100-8250-10
29 3100-9090-10
30 3300-0084-10
31 3300-008S-10
32 ]300-0088-10
33 4100-0024-10
34 4100-0002-10
35 4000-0009-10

RES,S.6K,SY.,1/4W,C
RES,8.2K,S/.,1/4W,C
RES,47K,5Y.,1/4W,C
R£S,120K,S%,1/4W
RES,220K,5Y.,1/4W,C
RES,270K,S%,1/4W,C
RES,S10K,S/.,1/4W,C
RES,lM,5%,1/4W,C
RES,220,5%,1/2W,C
RES,l,5X,1/2W,C
RES,39,s%,1/2W,C
RES,100,SY.,1/2W,C
RES,22K,S%,1/4W,C
RES,l,3%,lW,WW
RES,l.5K,S%,lW,C
RES,75,l%,l/8W,MF
RES}604)1%}1/8W)MF
RES,82S,l/.,1/8U,MF
RES,909 i 1%,1/8W,MF
POT,SOK,O.5W,20Y. IT,PC,STR
POT,100K,O.SW,20y' IT,PC,STR
POT,lM,O.25W,30X 1T,PC,STR
CAP,68PF,500V,SY.,MICA
CAP,470PF,SOOV,SY.,MICA
CAP,O.lUF,100V,10%,CER

36 4400-0043-10

CAP,47UF,20Y.,10V,ELCTLT

37 4000-0042-10
39 4000-0043-10
40 4010-0103-10

CAP,O.lSUF,100V,5Y.,POLYTEST
CAP,O.01UF,SOOV,10/.,CER
CAP,0.01UF,sOV,10Y.,CER

QTY PER
REFERENCE
ASSEMBLY UM DESIGNATOR

2
12

EA
EA
EA
EA
EA
EA
EA
EA
EA

4

EA

0
0
1
3
1

2

2
2

1
2
1
1
2

1
1

2
1
2
1

1
3

EA
EA
EA
EA
EA
EA
EA
EA
EA
EA
EA
EA
EA
EA
EA
EA
EA
EA
EA

EA

1
1
8

EA
EA
EA
EA
EA

5

EA

2

EA
EA
EA

3
26

REF
REF
R35,36,64
R38
R8,9
R12
R5,34
3,4,60,62
53-55,S8
65
R19,l,2
R17,18,52
R63
R46
R39,40
R43,44
R22
R37,41
R42
R31
R30,49
R24
R45
R25,s7
R33
R67,68
R48
R28
R13
R14
R15
R16
R47
R20,21,32
R29
C43
C39
44-46,CS,6
C33,35,42
Cl,4,24,27
C19
C36,49
C32,34,37
18,20,56
21-23,25

GOULO INC.,

DESIGN AND TEST DIVISION

PAGE

2

BILL OF MATERIAL

---------------AS OF

02/12/86

0114-2010-60

MODEL:

1<450

11EM
PART NUMBER

#

DESCRIPTION

40 4010-0103-10

QTY PER
REFERENCE
ASSEMBLY UN DESIGNATOR

26

EA 26 / 28}29
48 , 7 , 12 , 17
57 / 58,59
8

41 4010-0100-10
42 4400-0036-10
43 4400-0037-10
44 4400-0047-10
45 4200-0036-10
46 4400-0038-10
47 7000-0451-10
48 1200-0033-10
49 1200-0031-10
50 4300-0041-10
Sl 1000-3900-10
52 6100-0151-10

CAP,10PF,SO/100V,S4,CER
CAP,1000UF~16V~10/'~ELCTLT

1
1

CAP,470UF,2SV,10Y.,ELCTLT

2

CAP)220UF,40V,-lO~

EA C50

+50~/ELCTLT

CAP,6MF,200V,10/.,POLYCARB
CAP/100UF/100V~-10r.+l00/./ELCTL

BATTERY, N.I.C.D. 2.4V
RECT 3SF4 3 AMP
RECT lN4937 1 AMP
CAP,O.056UF,400V,10/.,TNTLM
RES,390,S/.,1/4W,C
SKT
28 PIN DIP LO PROFIL

9,13,14,16
C40,41,2,3
EA C 11
EA C51
EA C47,54

1
1

3
1
1

3

EA C52
EA C38
EA B1
EA CR5
EA CR3,4,6
EA C53
EA R66
EA X2E,X1B
X3B

54
55
56
57
58
59
60
62

4600-0010-10
1300-0028-10
1400-0019-10
1300-0049-10
lS00-0048-10
6100-0120-10
3000-6800-10
3700-0083-10

CAP,7-40PF,100V,CER
TRAN 2N3904
TRAN 2N3906
TRAN BU407
TRAN 2N4921
SKT
16 PIN DIP LO-PROFIL
RES,680,S/'~1/4W,C

RPAK,2.2K,O.18W,2Y.,10/9

EA
EA
EA
EA
EA
EA
EA
EA

Cl0
Q2,6
Ql

1

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X8B,X10S
R51
12,15,20
14
RP1,S/6,9
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RP3,7,8,ll
EA 4, 1 3
RP10,16-19
EA Q3
EA 7C
EA 6C
EA 90 / 50
EA 80
EA 7B,17E
EA SE,6E
EA 9C
EA 14E
EA lSE,16E
7A-l0A
EA 9B

3

EA

10D~4E,6P.

2
1
1
1
2
1
8

63 3700-0085-10

5

64 3700-0049-10

7

65 1500-0018-10
66 1800-0105-10
67 1800-0123-10
68 1800-0110-10
69 1800-0111-10
701800-0115-10
71 1800-0254-10
72 1800-0404-10
73 1800-0301-10
74 1800-0125-10

TRAN
IC
IC
IC
IC
IC
IC
IC
Ie
IC

VN10KM
74LSOON
74LS14N
74LS10N
74LS20N

7S 1800-0121-10
76 1800-0267-10

Ie
IC

74LS17SN QUAD 0 F/F
74LS240N OCTAL LINE

2-IN NAND LOU
HEX SCHMITT
TRIPLE NAND
DUAL 4-IN
74LS74N , 14, FF, 0, X2
74LS85N 4-BIT MAG
74LS136N 14 XOR X4
74LS156N 16
74LS161N 20CNTR , SYN, BIN

1
2
1

2
2
1
1
6

QS

GOULD INC.

I

DESIGN AND TEST DIVISION

PAGE

3

BILL OF MATERIAL

---------------AS OF

0114-2010-60
MODEL:
K450
r'l EM
:.

77 1800-0240-10

80 1800-0193-10
81 1800-0097-10
82 1800-0038-10
84 1.'320-0080-10
85 1800-0319-10
87 1700-0082-10
88 1800-0341-10
891800-0311-10
91 9000-0049-10
920113-0011-10
93

~,1

00-0018-1 0

94 0113-0014-10
9S

ASSY,PCB,DATA DISPLAY,K4S0

9000-0082-10

96 7000-0365-10
97 7000-0366-10
98 7000-0221-10
99 -(200-0017-10
101 6000-0359-06
102 6000-0359-08
103 6000-0359-10
104 7000-0120-10
105 9000-0054-10
I 0 6 -( 2 0 0 - 0 0 32- 1 0
108 3000-1001-10
109 3000-2200-10
1103000-3300-10
111 3300-0096-10
112 7400-0002-10
113 1700-0071-10
114 4400-0045-10
115 0112-0228-08
1161800-0351-10
117 1800-0352-10
118 JOOO-5106-10
1191000-0002-10
120 8300-0027-10
121 4000-0011-10
122 6000-0389-10
123 6100-0146-10
125 3000-2700-10
126 3000-3301-10
127 0114-0432-10
128 7011-1440-10

QTY PER
REFERENCE
ASSEMBLY UM DESIGNATOR

DESCRIPTION

PAR T N U MB E R

7,13 1800-0268-10
79 1800-0231-10

02/12/86

74LS244N,20,BUFF/TRI-ST
IC
IC
74LS24SN BUS TRANS
IC
74LS27JN 20 FF, 0, X8
IC
74LS13BN 16 DCDR} 3T08
IC
7406N HEX INV BUF/DR
IC
74S20N 14 NAND X2
IC HM6116LP-3 2KX8 ST RAM CMOS
IC
D8259A PROG INTR eNT
IC
TDA1170/S TV VERT DEF
IC
MSMSS32 MICRO-PROC
IC
7438N QUAD 2-INPUT
WIDTH COIL
ASSY}HORIZONTAL COIL
XTAL 32.768KHZ,
ASSY}XFMR/HORIZ DRIVE
ASSY,FLYBACK TRANSFORMER, FINIS
HTSK TO-202
HTSK
WSHR SHLDR INS R
INSULATOR TO 220
CONN 6 PIN HDR
CONN SPIN HDR
CONN 10 PIN HDR
CARD EJECTOR NYLON 6/6
BUSS WIRE, FORMED
MOUSETAIL} 411 LONG
RES/1K,S%/1/4W/C

RES,220,S/.,1/4W}C
RES,330,SY.,1/4W/C

POT,lK}0.5W,20Y. IT}PC,STR
BUZZER/ALARM
IC LF3S6AN MONO OP AMP

3

3
3
1

2
2

1

2
2
1
1
1

1

1

o
1
1
1

RES,270,S%,l/4W,C

RES}3.3K,S/.,1/4W,C
LABEL,

CAUTION tlNICD ONLY"

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1

1

12E,3D 4D
BE
10C/18E
8C
18,3B
2E
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CARD EJECTOR-HOT STAMPED (AS)
IC
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IC
74LS22N 4-IN NAND OPE
TAPE,FOAM,lX1Xl/S"
CAP,2.2UF,50V,20Y.}0.2LS,CER
CONN 34 PIN ST HDR
SKT 18 PIN TERM CARRIER

13E,SB 1D
10E,3C,4C

EA 20
EA 7D

CAP/33UF/25V,ELCTLT

RES,Sl,S%/1/4W,C
OIO/1N41S2

EA
EA
EA
EA
EA
EA
EA
EA

1
2

EA
EA
EA
EA
EA
EA
EA
EA
EA
EA
EA
EA
EA
EA
EA
EA
EA
EA
EA
EA
EA
EA
EA
EA
EA
EA
EA
FT
EA
EA
EA
EA
EA
EA
EA

L1
L2
Y1

T1
T2

@ QS
@ 11 B

@ QS
@ QS
Pl
P2
P3

GND
Rl0/69
R26

R27
RS6
11 C

C5S

SC
60
R61

CR7
S5 OF 3A
C61

P4
20
R7

RSO

GOULD INC., DESIGN AND TEST DIVISION

PAGE

4

BILL OF MATERIAL

----------------

AS OF

02/12/86

0114-2010-60
MODEL:
K450
ITEM
Va

PART NUMBER

129 0117-0149-10
130 0117-0150-10
}32 0117-0139-10
133 7085-1004-00
134 7080-1004-00
136 7150-0018-09

DESCRIPTION

ASSY / PROM,VERT,Kl0S
ASSY,PROM,HORIZ,Kl0S
SHIELD , DEFLECTION}Kl0S
WSHR,INT TOOTH LOCK,#4,STZN
WSHR,FLAT,#4,SP / STZN
WIRE,PVC,18 AWG,WHT

GTY PER
REFERENCE
ASSEMBLY UM DESIGNATOR

1
1
1
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2
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EA 8B
EA 1 OB
EA
EA
EA
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PAGE

BILL OF MATERIAL
================
AS OF
02/12/86
0120-0042-01

MODEL:

ASSY,CBL,INPUT BO TO MB,K20S

K205

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I 1 EM
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PART NUMBER

0 1::0120-0042
1 6000-0391-20

2 6000-0352-20
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DESCRIPTION

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DESIGN AND TEST DIVISION

BILL OF MATERIAL
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MODEL:
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02/12/86

ASY CBL PROBE TEST TO CLK / K20S

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PART NUMBER

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6000-0273-10
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GOULD INC.} DESIGN AND TEST DIVISION

PAGE

BILL OF MATERIAL

---------------AS OF

0121-0006-10
MODEL:
K450

02/12/86

ASSY,CHASSIS,K450

11 EM
~

PART NUMBER

0 0114-0039-60
0 D0120-0004
4 7000-0334-10
S 0121-0007-10
6 0120-0023-10
1 1 0114-0005-20
12 0120-0022-10
1 3 9000-0138-10
21 0120-0042-01
22 0111-0016-10
24 0285-0117-30
25 8200-0032-10
26 0120-0043-01
27 0120-0044-01
28 0120-0145-10
29 0950-0099-10
30 0117-0123-10
31 7000-0376-10
32 7000-0328-10
33 7011-1832-60
34 7011-1632-16
36 7071-1008-00
37 7021-2612-12
38 7094-0001-10
39 7085-1006-00
40 7011-1632-12
41 7011-1632-24
42 7000-0320-10
43 7071-1632-00
52 0112-0308-10
53 7011-1832-12
57 7085-1008-00

DESCRIPTION

COVER,BOTTOM,45S0
DWG,ASSY,CHASSIS,K205
HDWR "U" SPEED NUr FSTNR
ASSY,FRT BEZEL,K450
BEZEL FRT,PUNCHED,K205
ASBY,REAR,CASTING
ASSY,CARD CAGE,K20,:)
SPEC. PUR SPLY Kl0l/02/05
ASSY,CBl,INPUT SO TO MB,K205
ASSY,HANDlE
SIDE RAIL,WHT,4500
ADHESIVE, THREAD LOCK 262
ASY CSl PROBE TEST TO ClK,K205
ASY CBl INPUT TO DATA BD,K205
ASSY,HARNESS,DOS-PWR,K205
REAR FOOT,KSOO
ASSY,CRT,Kl0S
SCR,HD,CAP)3/4 X 1/4-20
SCR,PHH,8-32 X 5/S
SCR,X,PH,8-32 X 1-7/S,STZN
SCR,X,PH,6-32 X 1/2,5TZN
NUT,KEP,#8,STD,STZN
SCR,X,FH 100,6-32 X 3/8,S5
WSHR,SPRG,1/4
WSHR,INT TOOTH lOCK,#6,STZN
SCR,X,PH,6-32 X 3/S,STZN
SCR,X,PH,6-32 X 3/4,STZN
SPCR,l/8 BJRND
NUT,S-lOCK,6-32,STO,STZN
INSULATOR, KEYBOARD
SCR,X,PH,S-32 X 3/S,STZN
LOCK WASHER INT. #8

QTY PER
REFERENCE
ASSEMBLY UM DESIGNATOR

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GOULD INC.

I

DESIGN AND TEST DIVISION

PAGE

BILL OF MATERIAL
================

AS OF

02/12/86

0121-0010-10
MODEL:
1<450
ITEM

PARr NUMBER

~

DESCRIPTION

0 00121-0010
0 00121-0011
1 0121-0012-10
3 1400-0019-10
4 3000-1200-10
5 1300-0038-10
7 1800-0105-10
8 1800-0254-10
9 1800-0349-10
1 0 1800-0280-10
1 1 1820-0028-10
1 2 1820-0065-10
1 :5 1820-0063-10
1 5 1850-0077-10

DWG,ASSY,CLOCK BD. K450
DWG,SCHEM,CLOCK BD. K450
FAB,PWB,CLOCK BD. K450
TRAN 2N3906
RES)120)5%, t/4W,C
TRAN BFR-91
74LSOON 2-IN NAND LOW
IC
IC
74LS8SN 4-BIT MAG
74368AN HEX BUS DR
IC
74S37N BUFFER/CLK DR.
IC
IC
4028 1 OF 1 0 DEC
IC
F4069B HEX INVERTER
MCt4St8B DUAL UP CNT
IC
IC
Fl00101DC TPL SOR/NOR

1 7 6 1 0 0 -- 0 1 1 9 - 1 0

SKT

1 4 PIN DIP LO-PROFIL
F1001020C 2IN OR/NOR

19

1850-0078-10

Ie

21
c~

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1850-0147-10
1850-0125-10

IC 10474
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MC10Hl16P TPL LINE RCVR

23

1850-0097-10

IC
IC

MC10231L DUAL 0 F/F
MC10176L HEX 0 F/F

IC
IC
IC
IC
IC
IC

MC10173L
MC10164L
MC10161L
MC10137l
MC10125L
MC10124L

24 1850-0098-10

26 1850-0105-10

27 1850-0099-10
28 1850-0100-10
''"\0:)
c. " 1850-0101-10
30 1850-010]-10
31 1850-0104-10
32 1850-0108-10
33 1850-0113-10

34 1850-0114-10
35 6100-0137-10
36 2100-0014-10
37 2100-0012-10
38 2100-0036-10
40 2950-5106-10
41 3000-1000-10

QUAD 2-IN
8-INPUT MULT
1 OF 8 DEC
DECADE CNTR
QUAD ECl-TT
QUAD TTL

Fl0109DC DUAL 4-5 INP
MC10101L QUAD OR/GAT
Fl0016DC 4-BIT BIN
IC
SKT 24 PIN DIP LOW PRO
IND 1025-94 MOLDED CHOKE
IND 1025-12 FERRITE CORE
INO 2743002121 SHLD BEAD
RES,S1,S%,l/8W,C
IC

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RES,100J5/'~1/4W,C

QTY PER
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ASSEMBLY UM DESIGNATOR

0
0
1

2
5
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1

1
1

2
7

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EA
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EA
EA
EA
EA
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25

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2
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R35,36
I

GOULD INC.

I

DESIGN AND TEST DIVISION

PAGE

2

BILL OF MATERIAL
================
AS OF

02/12/86

0121-0010-10
K450

MODEL:

QTY PER

I rEM

PART NUMBER

#

42
43
44
45
46
48
49

3000-8200-10
3000-1006-10
3000-1501-10
3000-1600-10
3000-1800-10
3000-2001-10
3000-2200-10

51
52
53
S4

3000-3006-10
3000-4700-10
3000-5100-10
.3000-5600-10
S5 3000-3001-10
56 3000-6800-10
57 3000-6806-10

DESCRIPTION

RES,820,S%,l/4W)C
RES,10,5%,l/4W,C
RES, 1 .5~C5t.) 1/4W,C
RES,160,S/.,1/4W,C
RES,180,5t.,1/4W,C
RES,2K,5Y.,1J4W,C
RES,220,SY.,1/4W,C
RES, 30 5%,1 14W . C
RES,470,Sk,t/4W,C
RES,510,5t.,1/4W,C
RES,560,SY.,1/4W,C
RES,3K,5Y.,l/4W,C
RES,680,SY.,1/4W,C
RES, G8, st., 1/4\.L C

1

EA R21

1
1
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1
3
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RES,2.2K,SF.,l/4W,C
POT,200 1 0.SW , 10r. 20T,PC,RTANG
RPAK,10K,O.2W,2F.,8/4
RPAK / 3K/6.2K,lJSW / SY.,10/16
RPAK,2.2K,O.18W,2Y.,B/7

4
4

63 3700-0039-10

RPAK,56,O.18W,2Y.,10/9

4

64 3700-0091-10

RPAK,6S,O.2W,2F.,S/7

6

66 3700-0092-10

RPAK,68,O.2W,27.,10/9

68
69
70
71
73
76

100MHZ .39UH
XTAL
RPAK,100,O.2W,2Y.,S/7
CAP,33PF,SO/100V,SY.,CER
CAP
6SPF 1 SO/100V 110% . 1
CAP,S.6PF,100V,SY.,CER
CAP,O.OlUF)50V)10F.,CER

58
59
60
61
62

3000-2201-10
3300-0067-10
3700-0051-10
3700-0049-10
3700-0057-10

5100-0004-10
3700-0096-10
4010-0330-10
4010-0680-10
4010-S606-10
4010-0103-10

REFERENCE

ASSEMBLY UM DESIGNATOR

3
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EA RP14
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EA 54
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EA 24
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EA 37,46,56
RP1S,27,28
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38-45
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EA RPSS
EA C70,71
EA C1
EA C7
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58-63,65
69
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79 4400-0043-10

CAP,47UF,20/.,10V,ELCTLT

80 4600-0009-10
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CAP
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Tl0-Tl1

GOULD INC.

I

DESIGN AND TEST DIVISION

PAGE

3

BILL OF MATERIAL

---------------AS OF

02/12/86

0121-0010-10
MODEL:
K450
I'1 EM

PART NUMBER

#

81

6000-0571-10

83 6000-0384-10

84 6000-0293-08
87 0112-0228-05
88 7000-0120-10
90 9000-0054-10
91 1850-0131-10
92 1850-0124-10

93 6000-0293-02

DESCRIPTION

CONN SHORrING PLUG

CONN
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20 POS RT ANGLE HDR
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GOULD INC., DESIGN AND TEST DIVISION

PAGE

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GOULD INC., DESIGN AND TEST DIVISION

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