MIPS32 Instruction Set Quick Reference 01 Instructions
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MIPS32® Instruction Set
Quick Reference
LOGICAL AND BIT-FIELD OPERATIONS
AND
ANDI
RD
RS, RT
RA
PC
ACC
LO, HI
±
∅
::
R2
DOTTED
DESTINATION REGISTER
SOURCE OPERAND REGISTERS
RETURN ADDRESS REGISTER (R31)
PROGRAM COUNTER
64-BIT ACCUMULATOR
ACCUMULATOR LOW (ACC31:0) AND HIGH (ACC 63:32) PARTS
SIGNED OPERAND OR SIGN EXTENSION
UNSIGNED OPERAND OR ZERO EXTENSION
CONCATENATION OF BIT FIELDS
MIPS32 RELEASE 2 INSTRUCTION
ASSEMBLER PSEUDO-INSTRUCTION
PLEASE REFER TO “MIPS32 ARCHITECTURE FOR PROGRAMMERS VOLUME II:
THE MIPS32 INSTRUCTION SET” FOR COMPLETE INSTRUCTION SET INFORMATION.
ADD
RD, RS, RT
RD = RS + RT
(OVERFLOW TRAP)
ADDI
RD, RS, CONST16
RD = RS + CONST16 ±
(OVERFLOW TRAP)
ADDIU
RD, RS, CONST16
RD = RS + CONST16 ±
ADDU
RD, RS, RT
RD = RS + RT
CLO
RD, RS
RD = COUNTLEADINGONES(RS)
CLZ
RD, RS
RD = COUNTLEADINGZEROS(RS)
LA
RD, LABEL
RD = ADDRESS(LABEL)
LI
RD, IMM32
RD = IMM32
LUI
RD, CONST16
RD = CONST16 << 16
MOVE
RD, RS
RD = RS
NEGU
RD, RS
RD = –RS
SEB
RD = R
SEHR2
RD, RS
RD = RS 15:0±
SUB
RD, RS, RT
RD = RS – RT
SUBU
RD, RS, RT
RD = RS – RT
RD = RS & CONST16
∅
∅
SP+S-1:P
(OVERFLOW TRAP)
JUMPS AND BRANCHES (NOTE: ONE DELAY SLOT)
B
OFF18
PC += OFF18±
BAL
OFF18
RA = PC + 8, PC += OFF18±
RD, RS, P, S
RS = R
BEQ
RS, RT, OFF18
IF
RS = RT, PC += OFF18±
INSR2
RD, RS, P, S
RDP+S-1:P = RSS-1:0
BEQZ
RS, OFF18
IF
RS = 0, PC += OFF18 ±
NO-OP
BGEZ
RS, OFF18
IF
RS ≥ 0, PC += OFF18±
BGEZAL RS, OFF18
RA = PC + 8; IF RS ≥ 0, PC += OFF18±
BGTZ
RS, OFF18
IF
RS > 0, PC += OFF18±
BLEZ
RS, OFF18
IF
RS ≤ 0, PC += OFF18±
BLTZ
RS, OFF18
IF
RS < 0, PC += OFF18±
NOP
NOR
RD, RS, RT
RD = ~(RS | RT)
NOT
RD, RS
RD = ~RS
OR
RD, RS, RT
RD = RS | RT
ORI
RD, RS, CONST16
RD = RS | CONST16 ∅
WSBHR2 RD, RS
RD = RS 23:16 :: RS31:24 :: RS7:0 :: RS15:8
XOR
RD = RS ⊕ RT
RD, RS, RT
RD, RS, CONST16
RD = RS ⊕ CONST16
∅
CONDITION TESTING AND CONDITIONAL MOVE OPERATIONS
MOVN
RD, RS, RT
IF
RT ≠ 0, RD = RS
MOVZ
RD, RS, RT
IF
RT = 0, RD = RS
SLT
RD, RS, RT
RD = (RS± < RT±) ? 1 : 0
SLTI
RD, RS, CONST16
RD = (RS± < CONST16±) ? 1 : 0
SLTIU
RD, RS, CONST16
RD = (RS∅ < CONST16∅) ? 1 : 0
SLTU
RD, RS, RT
RD = (RS∅ < RT∅) ? 1 : 0
MULTIPLY AND DIVIDE OPERATIONS
±
S 7:0
RD, RS
R2
RD, RS, CONST16
RD = RS & RT
EXT
R2
XORI
ARITHMETIC OPERATIONS
RD, RS, RT
DIV
RS, RT
LO = RS± / RT±; ΗΙ = RS± MOD RT±
DIVU
RS, RT
LO = RS∅ / RT∅; ΗΙ = RS∅ MOD RT∅
MADD
RS, RT
ACC += RS± × RT±
MADDU RS, RT
ACC += RS∅ × RT∅
MSUB
ACC −= RS± × RT±
RS, RT
BLTZAL RS, OFF18
RA = PC + 8; IF RS < 0, PC += OFF18 ±
BNE
RS, RT, OFF18
IF
RS ≠ RT, PC += OFF18±
BNEZ
RS, OFF18
IF
RS ≠ 0, PC += OFF18±
J
ADDR28
PC = PC31:28 :: ADDR28∅
JAL
ADDR28
RA = PC + 8; PC = PC31:28 :: ADDR28∅
JALR
RD, RS
RD = PC + 8; PC = RS
JR
RS
PC = RS
LOAD AND STORE OPERATIONS
LB
RD, OFF16(RS)
RD = MEM8(RS + OFF16 ±)±
LBU
RD, OFF16(RS)
RD = MEM8(RS + OFF16 ±)∅
LH
RD, OFF16(RS)
RD = MEM16(RS + OFF16 ±)±
LHU
RD, OFF16(RS)
RD = MEM16(RS + OFF16 ±)∅
LW
RD, OFF16(RS)
RD = MEM32(RS + OFF16 ±)
LWL
RD, OFF16(RS)
RD = LOADWORDLEFT(RS + OFF16 ±)
LWR
RD, OFF16(RS)
RD = LOADWORDRIGHT(RS + OFF16 ±)
SB
RS, OFF16(RT)
MEM8(RT
SH
RS, OFF16(RT)
MEM16(RT
+ OFF16±) = RS15:0
SW
RS, OFF16(RT)
MEM32(RT
+ OFF16±) = RS
SWL
RS, OFF16(RT)
STOREWORDLEFT(RT + OFF16±, RS)
SWR
RS, OFF16(RT)
STOREWORDRIGHT(RT + OFF16 ±, RS)
ULW
RD, OFF16(RS)
RD = UNALIGNED_MEM32(RS + OFF16 ±)
USW
RS, OFF16(RT)
UNALIGNED_MEM32(RT
+ OFF16±) = RS7:0
MSUBU RS, RT
ACC −= RS∅ × RT∅
MUL
RD, RS, RT
RD = RS ± × RT±
RD = RSBITS5–1:0 :: RS31:BITS5
MULT
RS, RT
ACC = RS± × RT±
ROTRVR2 RD, RS, RT
RD = RSRT4:0–1:0 :: RS31:RT4:0
MULTU RS, RT
SLL
RD, RS, SHIFT5
RD = RS << SHIFT5
SLLV
RD, RS, RT
RD = RS << RT4:0
SRA
RD, RS, SHIFT5
RD = RS± >> SHIFT5
MFHI
RD
RD = HI
SRAV
RD, RS, RT
RD = RS± >> RT4:0
MFLO
RD
RD = LO
SRL
RD, RS, SHIFT5
RD = RS∅ >> SHIFT5
MTHI
RS
HI = RS
LL
RD, OFF16(RS)
RD = MEM32(RS + OFF16 ±); LINK
SRLV
RD, RS, RT
RD = RS∅ >> RT4:0
MTLO
RS
LO = RS
SC
RD, OFF16(RS)
IF
SHIFT AND ROTATE OPERATIONS
ROTRR2
RD, RS, BITS5
Copyright © 2008 MIPS Technologies, Inc. All rights reserved.
ACC = RS∅ × RT∅
ACCUMULATOR ACCESS OPERATIONS
+ OFF16±) = RS
ATOMIC READ-MODIFY-WRITE OPERATIONS
ATOMIC, MEM32(RS + OFF16 ±) = RD;
RD = ATOMIC ? 1 : 0
MD00565 Revision 01.01
REGISTERS
0
zero
1
at
READING THE CYCLE COUNT REGISTER FROM C
Always equal to zero
Assembler temporary; used by the assembler
2-3
v0-v1 Return value from a function call
4-7
a0-a3
First four parameters for a function call
8-15
t0-t7
Temporary variables; need not be preserved
16-23
s0-s7
Function variables; must be preserved
24-25
t8-t9
Two more temporary variables
26-27
k0-k1 Kernel use registers; may change unexpectedly
28
gp
Global pointer
29
sp
Stack pointer
30
fp/s8
31
ra
unsigned mips_cycle_counter_read()
{
unsigned cc;
asm volatile("mfc0 %0, $9" : "=r" (cc));
return (cc << 1);
}
ATOMIC READ-MODIFY-WRITE EXAMPLE
atomic_inc:
ll
addiu
sc
beqz
nop
ASSEMBLY-LANGUAGE FUNCTION EXAMPLE
Stack frame pointer or subroutine variable
Return address of the last subroutine call
DEFAULT C CALLING CONVENTION (O32)
Stack Management
• The stack grows down.
• Subtract from $sp to allocate local storage space.
• Restore $sp by adding the same amount at function exit.
• The stack must be 8-byte aligned.
• Modify $sp only in multiples of eight.
Function Parameters
• Every parameter smaller than 32 bits is promoted to 32 bits.
• First four parameters are passed in registers $a0−$a3.
• 64-bit parameters are passed in register pairs:
• Little-endian mode: $a1:$a0 or $a3:$a2.
• Big-endian mode: $a0:$a1 or $a2:$a3.
• Every subsequent parameter is passed through the stack.
• First 16 bytes on the stack are not used.
• Assuming $sp was not modified at function entry:
• The 1st stack parameter is located at 16($sp).
• The 2nd stack parameter is located at 20($sp), etc.
• 64-bit parameters are 8-byte aligned.
Return Values
• 32-bit and smaller values are returned in register $v0.
• 64-bit values are returned in registers $v0 and $v1:
• Little-endian mode: $v1:$v0.
• Big-endian mode: $v0:$v1.
NOTE:
# int asm_max(int a, int b)
# {
#
int r = (a < b) ? b : a;
#
return r;
# }
.text
.set
.set
nomacro
noreorder
.global
.ent
asm_max
asm_max
asm_max:
move
slt
jr
movn
.end
$v0, $a0
$t0, $a0, $a1
$ra
$v0, $a1, $t0
$t0,
$t1,
$t1,
$t1,
0($a0)
$t0, 1
0($a0)
atomic_inc
#
#
#
#
load linked
increment
store cond'l
loop if failed
ACCESSING UNALIGNED DATA
ULW AND USW AUTOMATICALLY GENERATE APPROPRIATE CODE
LITTLE-ENDIAN MODE
BIG-ENDIAN MODE
LWR
LWL
RD, OFF16(RS)
RD, OFF16+3(RS)
LWL
LWR
RD, OFF16(RS)
RD, OFF16+3(RS)
SWR
SWL
RD, OFF16(RS)
RD, OFF16+3(RS)
SWL
SWR
RD, OFF16(RS)
RD, OFF16+3(RS)
ACCESSING UNALIGNED DATA FROM C
#
#
#
#
r = a
a < b ?
return
if yes, r = b
asm_max
typedef struct
{
int u;
} __attribute__((packed)) unaligned;
int unaligned_load(void *ptr)
{
unaligned *uptr = (unaligned *)ptr;
return uptr->u;
}
C / ASSEMBLY-LANGUAGE FUNCTION INTERFACE
MIPS SDE-GCC COMPILER DEFINES
#include
int asm_max(int a, int b);
int main()
{
int x = asm_max(10, 100);
int y = asm_max(200, 20);
printf("%d %d\n", x, y);
}
__mips
MIPS ISA (= 32 for MIPS32)
__mips_isa_rev
MIPS ISA Revision (= 2 for MIPS32 R2)
__mips_dsp
DSP ASE extensions enabled
_MIPSEB
Big-endian target CPU
_MIPSEL
Little-endian target CPU
_MIPS_ARCH_CPU
Target CPU specified by -march=CPU
_MIPS_TUNE_CPU
Pipeline tuning selected by -mtune=CPU
INVOKING MULT AND MADD INSTRUCTIONS FROM C
MIPS32 VIRTUAL ADDRESS SPACE
kseg3
0xE000.0000
0xFFFF.FFFF
Mapped
Cached
ksseg
0xC000.0000
0xDFFF.FFFF
Mapped
Cached
kseg1
0xA000.0000
0xBFFF.FFFF
Unmapped
Uncached
kseg0
0x8000.0000
0x9FFF.FFFF
Unmapped
Cached
useg
0x0000.0000
0x7FFF.FFFF
Mapped
Cached
Copyright © 2008 MIPS Technologies, Inc. All rights reserved.
int dp(int a[], int b[], int n)
{
int i;
long long acc = (long long) a[0] * b[0];
for (i = 1; i < n; i++)
acc += (long long) a[i] * b[i];
return (acc >> 31);
}
NOTES
• Many assembler pseudo-instructions and some rarely used
machine instructions are omitted.
• The C calling convention is simplified. Additional rules apply
when passing complex data structures as function parameters.
• The examples illustrate syntax used by GCC compilers.
• Most MIPS processors increment the cycle counter every other
cycle. Please check your processor documentation.
MD00565 Revision 01.01
Source Exif Data:
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