02770 9001_2770A_2771A_Disc_Memory_Service_Sep69 9001 2770A 2771A Disc Memory Service Sep69

User Manual: 02770-9001_2770A_2771A_Disc_Memory_Service_Sep69

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~------~--------HEWLETT?PPACKARD------------------~

OPERATING AND SERVICE MANUAL

2770A
2770A-01

2771A
2771A-01

DISC MEMORY

' __ J

02770-9001

HEWLETT-PACKARD COMPANY
11000 WOLFE ROAD, CUPeRTINO, CALIFORNIA, U.s.A.

Printed: SEPT 1969

FOREWORD

This manual provides operating and maintenance instructions for the magnetic
Memory System Model 7301 (Part No. 13870) and Model 7302 (Part No. 13770).
manufactured by Digital Development Corporation, San Diego, California.
Hewlett·Packard assigned model numbers and options are as follows, and this manual
provides information on all versions:

Model/Option

Storage Capability and Input Freq.

2770A
2770A·01

3 Megabits, 60 Hz (expandable to 6 megabits)
6 Megabits, 60 Hz (non-expandable)

2771A
2771A-01

6 Megabits, 60 Hz (expandable to 12 megabits)
12 Megabits, 60 Hz (non-expandable)

The Disc Memories described in this manual are manufactured for general data storage
and are designed to interface with the Hewlett-Packard 2115 and 2116 Computers.
The Disc Memories are modular, high-capacity, rapid access digital data memory
systems containing the necessary electronics for address decoding, generation of timing
and control signals, and recording and recovering data. They employ a proven
non-contact head-per-track design for fast access and continued reliable operation.
When requesting further information or assistance in the effective utilization of the
Disc Memory, please refer to specific model, part, and serial number of individual
units.

This manual was printed by permission of the Digital Development Corporation.

MAGNETIC
MEMORY
SYSTEM

is.CltO ... •

TABLE OF CONTENTS
Section

1

Page
GENERAL DESCRIPTION
1.1
1.2

II

....................

0

............................

..

1-1
1-1
1-1
1-1
1-1
1-6
1-6
1-6

1-11

If,[ST ALLATION AND OPERATION . . . • . . • . . . • . • . . . • • . . . .

2-1

Introduction ....
Receiving Data . . . . . . • . • . • • . . . . . . . . . . • . . . • . • • .
2.2.1
Handling and Unpacking the Equipment. . . • • • • ..
2.2.2
Inspection............................................
Equipment Di mensions
Instalmtion .......................
Tools Required
2.4.1
Installation Procedures . . . . • . . • • . . . . . . • . •
2.4.2
Cable lnte rconnecti ons . • . . . • . . . . . • . • . . . . . • . . . . .
Operation ........
Controls and Indicators . . • • • • . . . . . • . . . . • .
2.6. 1
Energizing the Unit . . . •

2-1
2-1
2-1
2-1

2. 1
2.2

2.3

2.4

2.5
2.6

2.7
3

....

I)escription ..........................
1.2. 1
Men10ry Unit . • . . . . . . . . . . . . . . . . . . . . . . . .
1. :2.2
Disc Memory Assembly . . . . . . . . . . . . . • . . . .
Disc Housing . • . . . . . . . . . . . . . . . . . : • . . . . .
1. 2.3
Rotating Assembly . . . . . . • . . . . . . . • . . . . • . .
1. 2. 4
AC Drive Motor . . . . . . . . • . . . . . . . . . . . • . • .
1. 2.5
Discs .•• ~ • • • • • • . • • • • • • • • • • • • • • • • • • • •
1. 2. 6
Recording Heads . • . . . . • . • . . . . • . . . . . . • • .
1. 2.7
Data Headplate Assembly • . . . . . • . . • . . . • • • • .
1. 2.8
Timing Head Assembly . . . . . • . . . . . . . • . . . . •
1. 2.9
1. 2.10 Baseplate Assembly . . . . . . . • . . . , . . . . . . . • .
1.2.11 Front Panel Assembly . . . . . . . . . . . . . . . . . • •
1.2.12 Eiectl'onics Assembly . . . . . . • • . • • . . . • • . • • .
Specifications. . . . • . . . . . . . . . . . . . . . • . . . . • • . . .•

1.3

2

i11tl--oduction

1-1

e-

G

........

3. 1

......

0

0

.........

PRINCIPLES OF OPERATION

3.2

"

..

(I

................................

...................

.............

a

0

(I

.........

.................

..

.

..

2-2
2-2

2-2
2-3
2-3
2-7
2-7

...................................

0

••••••••••••••••••••••

2-8

..

..

3-1

..

•

..

..

..

•

it

..

..

..

..

..

..

..

•

..

..

•

•

•

Int roduction . . . .
Electromechanical Description • . • . . • . . • . . . . • . . • . .
3.2. 1
Environmental Gas System • . . . . • . • • . . . . . . .
3.2.2
Head Actuation Pressure System . . . . • . • . • • . •
3.2,3
ElectrIcal Control System •• ' - T o • • • • • • • • • , • •
II

1-9
1-9
1-9

0

..

.

1-7
1-7
1-7

•••••••••••••••••••••••••••

3-1
3-1
3-1
3-4
3-6

MAGNETIC
MEMORY
SYSTEM

mm
B

TABLE OF CONTENTS (Cont)

Section
3
(Cont)

System Electronics Description .•••••••..
3.3. 1
Phase Modulation Recording • . . • • • • • • . . . • .
3.3.2
Clock and Timing Signals•..•••••••••••••••
3.3.3
Write Logic . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.4
Write Amplifier Operation .•••••••••••..•.•
Addressing and Headplate Organization . • . • . . .
3.3.5
Read Logic . . . . .
3.3.6
3.3.7
Strobe Selection ••.••••••••..•
3.3. 8
Combination of Data A + Data B ••••.•.•..•.•
System/Controller Interface ••••••••.••..•.••••.•
3.4.1
Functional Block Diagram •••••••..••.••..•
3. 4. 2
Principles of Operation •••••.••••.•.••.•••

Page
3-11
3-11
3-12
3-14
3-16
3-22
3-31
3-37
3-37
3-40
3-40
3-43

CIRCUIT BOARD SPECIFICATIONS ••.• ; •••.•••.•••••.••

4-1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write Amplifier 11306. . . • • • • • • . • • . • . . • • • •
Delay Circuit 11640 ...••
Decode Driver 11661 ..•••.•••••••.••••
Clock Generator and Speed Detector 11791/11874..
Read Amplifier 11803 •••.
Linear Data Preamplifier 11807 ..••.•••
Linear Timi~g Preamplifier 11811 • • • • • • • • • ••
Line Terminator 11815 • . • • • . • • • • • • . • • • • •.
''X'' Amplifier 11818 •••..•.•••.•••.•

4-1
4-2
4-6
4- 8
4-10
4-13
4-15
4-16
4-17
4-19

3.3

0

•••••••

0

0

3.4

4

0

4.1

•

•

•

•

•

•

0

•

•

0

•

0

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

0

••••••••

•

•

•

•

•

•

•

•

•

•

•

•

•

•

MAINTENANCE . . . . . . . . . .

5.1
5.2

5.3
5.4

I)

••••••••••••••••

I)

•

3

•

•

•

•

•

•

0

•

•

•

0

••••

0

5

•

•

••

••

•••••

Introduction . . . . . . . . . .
Preventive Maintenance . . • • • . • . • . • • • . • • . . . • • . • .
5.2.1
Helium Bottle Replacement •••••••...••••.
5; 2.2
System Purging . • . • • • . • • . • • . • • • • • • . . . .
Correcti ve Maintenance ••••••...•..••.••.••••.•
Pressure Switch Assembly Adjustments ..•••••.
5.3.1
Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4. 1
Leak Detection
••....•.•.•
5.4.2
Troubleshooting the Environmental Gas
Supply System ..••••••..•.••.••••••..
5.4.3
Troubleshooting the Head Actuation
Pressure System
OJ

•

•

•

•

•

I)

•

•

I)

0

•

•

•

•

•

•

0

•••••••••••

I)

•

•

I)

•

5-1
5-1
5-1
5-1
5-2
5-3
5-3
5-6
5-6
5-6
5-6

mm
T ABLE OF CONTENTS (Cont)
Section
5
(Cont)

Troubleshooting the Electronic System
5.4.4
Replacement Procedures . . • . • . . . . . • . . . . • . . . . . • .
5. 5. 1
Cover Removal . . . . . . • • • • . . . . . • . • • • • • .
5.5.2
Data Headplate Assembly Replacement
.....•.
5.5.3
Headplate Diodes . . . . • . . . . . . • . .
5. 5. 4
Dump Valve Replacement . . . . • • . . . . •
5.5.5
Pressure Relief Valve Replacement . . . . • . . . . •
5.5.6
Head Actuation Pressure Pump Replacement . . . .
5.5.7
Pump Capacitor Replacement . . .
5.5. 8
Pressure Pump Check Valve Replacement •..•.•
5.5.9
Timing Head Assembly Replacement . . . . . . . • . •
5.5.10 Swagelok Fitting Installation . • . . . . • . . • . • . . .

5-8
5-17
5-17
5-17
5-17
5-17
5-18
5-18
5-19
5-19
5-19
5-19

ENGINEERING DRAWINGS AND PARTS LISTS . . . . . . . . . • • . • .

6-1

G. 1

Int roduction • . . . . . . . . . . . • . . . • . • . . . . . . . . • . . . •

6-1

G.2

Index . . . . . . . . . . ,. . . . .

5.5

0

••••••••

0

0

6



S YS TEM

<

>
i ..

;;;;;;;;;;\\};':.:,.;;<;;;';'<}}}<

BEARING CAP
AND COVER
MAGNETIC DRUM
SPEED PICK-UP
HEAD
DR UM HOUSING
OVER TEMPERATURE
THERMOSTAT

.HEADPLATE
HEAD PLATE
DIODE BOARD
PRESSURE
SWITCH

INDICATOR
PANEL
CIRCUIT -~-~-f--­
CARDS

FRONT VIEW

SHIPPING
BRACKETS
(Remove for Installation)

Figure 1-1. Major Components, Magnetic Memory System (Sheet 1 of 2)

mm
ACCUMULATOR

PREAMPLIFIER (4)

''X'' AMPLIFIER

TIMING CAPSULE

ATTACHING
SCREW
CHECK
VALVE
INPUT/
OUTPUT
SIGNAL
CONNECTOR

ISOLATION
TRANSFORMER

SHIPPING---r
BRACKETS
(Remove for
Installation)
SUPPLY
BOTTLE
REAR VIEW

Figure 1-1.

I-BEAM
MOUNT FOR
MOTOR START
CAPACITORS

Major Components, Magnetic Memory System (Sheet 2 of 2) ,

SPARE /NORMAL
TIMING SWITCH

MOTOR
CAPACITOR

1
RELAY
MOUNTING
BOARD

L

LOW PRESSURE '~
GAUGE - - - - 1 - - - - - - ,

SUPPLY

HIGH---~-I­

!V BOTTLE

PRESSURE
GAUGE

SHUTOFF
VALVE----o*
ISQLATION
TRANSFORMER

Figure 1-2. Major Components Locatec(

Jer Baseplate Assembly

mm
UPPER BEARING

TOP END PLATE

* DISCS

.AiU---HUB

ROTOR OF
MOTOR

* NOTE.,:

(MATES WITH
BEARING HOUSING -_..r-o=~
IN DRUM HOUSING)

Figure 1-3.

NUMBER OF DISCS IS
DEPENDENT ON CUSTOMER
ORDEP.

Typical Rotating Assembly

contains the motor stator winding and also serves as a mount for
the lower bearing housing. The top end plate, with upper bearing
housing, fits on top of the disc housing. Headplateopenings ate
spaced at intervals around the housing for mounting data and
timing head assemblies. Two eccentric locating pins, which
align the data he ad plate with the disc surface, are installed in
the housing at each headplate opening. Each data head plate
assembly is pressure-actuated through a chamber drilled in the
drum housing.

No field adjustments are required for recording
heads. If adjustments are attempted, serious
damage may result to the equipment.

MAGNETIC

mm

MEMORY
SYS,TEM

B
The helium· gas· inlet fitting from the envirorunentalg~ supply', .
is located on the base of tll~,drum housing. This gas~itpply
system is not to be coJlf~~dWith the head actuation pressure
system. 'l'he envir()f)~Atal gas supply is -received f:r:()ltl~,\:i>~t;
sustainingga@'~uPll~!~~tt1e external to the sealed cove~:.,',',
provides the ~tt.:""."""">.".",.,,.,.
SYSTEM
TABLE 1-1. SPECIFicATIONS (Cont)
INTERFACE
REQUffiEMENTS (Cont)

Interface signal
connectors:

All interface signal lines
between the controller and the
memory system are connected
via one Winchester type
MRAC-50-S (50 pin) connector.
A mating connector is also
provided.

AC Power:

The AC power required by the
disc motor is supplied via a
Bendix PTO 2A-12-3P connector.
A mating connector is also
provided.

DC Power:

The DC power required by the
disc electronics is supplied
via a Bendix PTO 2A-14-12P
connector. A mating connector
is also provided.

MAGNETIC
MEMORY
S YS TEM ·.···.i!;)eCl10n
INSTALLATION AND OPERATION
2.1 INTRODUCTION

This section provides installation information consisting of
receiving data, equipment dimensions, cabling data, installing,
and operating procedures.

2.2 RECEIVING DATA
2.2.1 HANDLING
AND UNPACKING THE
EQUIPMENT

A powered fork lift of 300 pounds capacity is recommended for
handling the memory unit.

2.2.2 INSPECTION

2.2.2.1 VISUAL CHECKS. The following checks should be
made and the Factory notified irnmediately if the unit shows
any evidence of damage:

DO NOT drop the memory unit while handling
it. Serious damage could result from dropping the unit. If the unit is dropped, DO NOT
apply power. Notify the Factory immediately
to prevent voiding the warranty.

a.

Check for dents or abrasions on cover.

b.

Check control panel for broken indicators or damaged
switch.

c.

Check rear connector bracket for damaged connectors.

d.

Check underside of baseplate for dented relays and
broken cables.

e.

Check electronic card rack for loose, missing or
damaged circuit cards. Check that cards are properly
installed.

f.

Check part number of Clock Generator and Speed
Detector card in electronic card rack. Part number
11874 is used only in installations having a 50 Hz
primary input line frequency. Part number 11791 is
used only in installations having a 60 Hz primary input line frequency. Ensure proper card is installed
for the intended installation.

2.2.2.2 ENVIRONMENTAL GAS SYSTEM CHECKS. Perform
the following visual examination of the environmental gas supply
system:
a.

Check that the helium gas supply bottle is securely clamped
in place.

b.

Ensure that the helium gas supply bottle valve is open
(completely counterclockwise).

MAGNETIC
MEMORY
SYSTEM
c.

Check that the 0-4000 psi gauge indicates greater than
1000 psi. If not, excessive leakage has occured. Replace or recharge the bottle before pressure is allowed
to drop below 300 psi. (Refer to Section 5 .. )

d.

Check that the 0-3 psi gauge indicates 1/4 to 3/8 psi.
If it does not, adjust the regulator according to procedures

outlined in Section 5 .

2.3 EQUIPMENT
DIMENSIONS
AND WEIGHTS

The equipment dimensions and weights are contained in Table 2-1.
Tf.BLE 2-1.

EQUIPMENT DIMENSIONS AND WEIGHTS

Physical Description

Model 7301

Model 7302

Depth:

20.0 in.

20.0 in.

Width: Slides (max.)
Baseplate

17.625 in.
17.550 in.

17.625 in.
17.550 in.

Height:

17.75 in.

19.25 in.

Equipment Weight

140 lbs.

160 lbs.

Equipment Dimensions

2.4 INSTALLATION
2.4.1 TOOLS
REQUIRED

A recommended list of tools and equipment required to install the
memory unit is contained in Table 2-2.
TABLE 2-2. LIST OF TOOLS AND ACCESSORIES
REQUIRED FOR INSTALLATION
Quantity
1
1
1
1 set
1
1
1
1
4
1
1

Tool
Power Fork Lift
Winch with "A" Frame
Open end wrench
Allen wrenche s
Open end wrench
Open end wrench
Open end wrench
Open end wrench
Eyebolts
YOM
Oscilloscope

Description
300-pound capacity
300-pound capacity
Adjustable
1/2-inch
9/16-inch
5/8-inch
3/4-inch
10-24
10, 000 ohm/volt
(or better)
2-channel

2.4.2 INSTALLATION
PROCEDURESi . .

To install the mem8ry unit, proceed as follows:
1. Remove the four 10-24 bolts in each of the four
corners on top of the baseplate. Replace them with forged or
welded 10-24 eyebolts.

NOTE
Because of the equipment's weight
and awkwardness in handling, the
use of eyebolts will facilitate handling of the unit with a winch and "A"
frame hoist.
2. Attach the removeable outside section of the slides
to the cabinet. Remove the shipping brackets and install the
unit so the two sections of the slides on the memory unit and on
the cabinet mate properly.

CAUTION

DO NOT EXTEND the baseplate to
the end of its slides before the
cabinet is securely installed. The
weight of the extended memory unit
could cause the cabinet to tip over.
3. Install interconnecting cabling.
connections before applying power.

2.5 CABLE
INTERCONNECTIONS

·Check all inter-

Figure 2-1 is a cable diagram illustrating how the interconnecting
cables should be connected to place the equipment into operation.
All interconnections should be checked before applying power.
Table 2-3 lists the function of all cables. Table 2-4 lists all
connectors and their part numbers.

CAUTION

Before applying power to the equipment, check for correct voltages at
the pins of the input connectors to
prevent possible damage to the
electrical and electronic systems.

RELAY BOARD

CARD RACK

.i!:!...
PI
-

r-

I

J2
P2

'-- ,-

d

I

P3
L-. r-

PWR/SIG SOURCE

0

J4
P4

CJ
IoQ

'-- -

~

>

CJ
IoQ

~

~

r:.J).

f-j

M
~
>-I

J2A

P2A~

Z

IoQ
C
f-j

J4A P4A

g)
Q

Z

>

t:-'
r:.J).

~------~~--~--~~--------~~------------------~Jl0 Pl0~--------~

--L
PI2

-......,

--

--

P8

P6

P5

-JI2 -J8

-

J6

LNECTOR MTG BRKT

-

I

J5

INDICATOR PANEL
BASE PLATE

Figure 2-1.

Interconnecting Cable Diagram

MAG
M ENET
M 0 RI C
Y .• .• • • //F)cig
. .:. . . .ij)2t5
. . . . . :. >•..••••.•••.i..•••...•••.i•••...

SYSTEM
TABLE 2-3.
Cable

CABLE FUNCTIONS

Function

From

To

PI-Jl

Motor & Pressure
Control Signals

Ind. Panel

Relay Board

P2A-J2A

DC Power Input &
Disc Ready Contac s

Pwr/Sig
Source

Conn. Mtg. Brkt.

P2-J2

DC Power Input &
Disc Ready Contacts

Conn. Mtg.
BrIet.

Relay Board

P3-J3

Drum Speed Signals

Card Rack

Relay Board

P4A-J4A

AC Power Input

Pwr/Sig
Source

Conn. Mtg. Brkt.

P4-J4

AC Power Input

Conn. Mtg.
Brkt.

Relay Board

P5-J5

Motor & Dump
Valve Power

Relay Board

Baseplates

P6-J6

X & Y Lines-Under
Pressure Contacts

Card Rack

Baseplates

P8-J8

Timing Signals

Card Rack

Baseplates

PIO-JIO

Disc Input Signals

Card Rack

System
Interface

P12-J12

Drum Speed
Pickup Signals

Relay Board

Baseplate

mID
TABLE 2-4. CABLE CONNECTOR PART NUMBERS
~

Connector

Part Number

PI

Bendix Connector Plug

PT06A-12-10P (SR)

P2

Bendix

PTQ6A-14-12S (SR)

P3

Bendix

PT06A-14-12P (SR)

P4

Bendix

PT06A-12-3S (SR)

P5

Bendix

PT06A-18-11S (SR)

P6

Bendix

PT06A-22-55S (SR)

P8

Bendix

PT06A-16-26S (SR)

P10

Winchester

MRAC 50 PJTDH9

P12

Bendix

PT06A-12-lOS (SR)

J1

Bendix

PT06A-12-10S

J2

Bendix

PT02A-14-12P

-J3

Bendix

PT02A-14-12S

J4

Bendix

PT02A-12-3P

J5

Bendix Receptacle

PT07H-18-11P (101)

J6

Bendix Receptacle

PT07H..,22-55P (101)

J8

Bendix Receptacle

PT07H-16-26P (101)

J10

Winchester

MRAC 50-SJ6

(Contacts PJTDH9)

(Contacts 100-1022P)

MAGNETIC
MEMORY
SYSTEM
2.6 OPERATION

The disc file is completely interlocked and fail-safe. The
functional operation of the unit can be monitored by observing
the front panel indications.

2. 6. 1 CONTROLS
AND
INDICATORS

The front panel, Figure 2-2, contains four indicator lamps
and a motor reset switch.
MOTOR POWER ON INDICATOR. The MOTOR
2.6.1.1
POWER ON indicator lamp lights when primary AC power is
applied to the unit.
2.6.1. 2
DRUM SPEED LOW INDICATOR. When power is
applied, the DRUM SPEED LOW indicator lamp glows until the
unit reaches a speed of 3300 rpm nominal (2750 rpm @ 50 Hz).
The DRUM SPEED LOW indicator will remain unlighted during
operation unless the speed of the unit drops below 3100 rpm
nominal (2580 rpm @ 50 Hz). When the disc drops below its
normal safe operating speed, the head actuation pressure drops
to zero and the data and timing heads retract.
2.6.1. 3
ACTUATION PRESSURE LOW INDICATOR. The
ACTUATION PRESSURE LOW indicator lamp lights when the
head actuation pressure is below the nominal level of 1. 5 psi
and indicates that the pressure pump is operating. The
ACTUATION PRESSURE LOW indicator does NOT indicate a
loss of helium in the environmental control system. After
the disc attains operating speed, the pressure pump operates for
approximately two to four seconds and the ACTUATION PRESSURE
LOW lamp lights. When pressure has built up to the operating
level of 1. 5 psi, the ACTUATION PRESSURE LOW indicator
extinguishes. Normally, the pump will cycle two or three times
after initial start, during which time the indicator lamp will
illuminate. During these periods the pump will operate for
approximately one second. After the initial starting phase, the
pump should cycle for about one second at a minimum of 10minute intervals. During the short period while the pump is
cycling, the ACTUATION PRESSURE LOW indicator will flash.
2.6.1.4
DRUM TEMPERATURE HIGH INDICATOR. The
DRUM TEMP HIGH indicator lamp lights when the temperature of
either the drum housing rises above a safe limit of 150°F or the
motor winding rises above 270°F. Whenever either the drum
housing thermostat or the motor thermal switch is thus activated,
an overload relay actuates and removes AC power from the motor
winding.

1
~~~ ~f'dQ~.2~8
SYSTEM

M~

····.SeCUOrl2
........

ACTUI!TIO..
PRESSURE
1.0
'

,.......

••
DRUM
SP!EIJ
L'OW

DRUM
TEMP
HIG

Figure 2-2.

Front Panel

2.6.1. 5
MOTOR RESET SWITCH. If the temperature inside
the sealed cover rises to an unsafe condition, one of the two
thermostats activates and causes AC power to the motor to be
removed. After the unit has cooled to a safe operation temperature, the MOTOR RESET switch must be actuated before power
can be applied to the motor.

2.7 ENERGIZING THE UNIT··

The magnetic memory system is energized when AC power is
applied. Operation can be monitored by observing the indicators
on the front panel. DC power can be applied in any sequence.
The system is interlocked to inhibit writing when any of the DC
voltages are too low. There are no provisions for an overvoltage
condition. The DRUM SPEED LOW indicator will not extinguish
unless DC power has been supplied to the disc memory unit. The
drum speed detector circuit requires DC power to operate the
drum speed relay. Prolonged operation of four-disc units on
only AC power should be avoided to prevent overheating the motor.

mm
SECTION 3
PRINCIPLES OF OPERATION
3.1 INTRODUCTION

This section is divided into an electromechanical description
and a system electronics description of the Magnetic Memory
System. An overall functional block diagram of the Magnetic
Memory System is provided in Figure 3-1.

3.2 ELECTROMECHANICAL
DESCRIPTION

The following paragraphs provide a functional description of
the environmental gas system, the head actuation system, and
the electrical control system.

3.2.1 ENVIRONMENTAL
GAS SYSTEM

The environmental gas system, Figure 3-2, is a helium gas
supply that provides the unit with the clean, controlled, environment required for reliable operation of the flying heads. This
inert environment also inhibits oxidation of the bearing lubricant,
and considerably extends the bearing life. In addition, less heat
is generated from windage friction because of the low density of
helium.
The environmental gas system consists of a sustaining helium
supply bottle, a two- stage regulator with inlet and outlet gauges,
an inlet fitting and a pressure relief valve. The helium supply
bottle is a standard type-B medical cylinder with a eGA cutoff
valve which, when full, contains approximately six cubic feet of
gas. This is a sufficient supply to fill the volume of space under
the cover a minimum of six times.
The helium gas inlet fitting from the environmental gas supply
is located on the base of the drum housing. This gas supply
system is not to be confused with the head actuation pressure
system, which is a completely self-contained system within
the sealed cover. The environmental gas supply is received
from the gas supply bottle, external to the sealed cover, and
provides the controlled atmosphere for the unit. Helium gas
enters the base of the drum housing and bleeds out of the housing
into the remainder of the sealed chamber surrounding the memory device, maintaining a positive pressure of approximately
1/4 to 2 psi within the sealed enclosure.
An Airco Regulator (Stock No. 806-8418) is used to reduce the
bottle pressure in two stages. The first stage reduces the
pressure from 2000 psi to approximately 300psi. The second
stage reduces it to approximately 25 psi. The regulator has a
0-4000 psi gauge that monitors bottle pressure,. a 0-.3 psi gauge
that monitors output pressure, and a T-handle with a locking
nut used for adjusting regulator output pressure. The pressurized
gas is fed to the baseplate through a cutoff valve, a length of
plastic tubing, and fittings on both sides of the baseplate.

DRIVE
MOTOR
I

__ AC POWER

.

•
.

OVER
TEMP
SIGS

•

...

DISC/:MEMORY

••

•

~

...

-..

DISC
SPEED
SIG

ELECTRICAL
CONTROL
SYSTEM

FROM
COMPUTER

I

I
I

INDICATOR
SIGS ~
INDICATORS
AND CONTROLS

...

DISC
READY
SIG ...

READ
DATA ,r

I

TIMING SIGS
ELECTRONIC
SYSTEM

WRITE DATA

ADDRESS SIGS

~

...

50/60 Hz POWE R

MOTOR
RESET
SIG

•

RECORDING
HEADS
WRITE
DATA
TIMING Be CONT SIGS

t

--

I

ENVmON:MENTAL
GAS SYSTEM
~---

115 VAC t 10

TO COMPUTER

...

READ DATA

ELEC RELATION
DC POWER---.6

- - - - - - - - MECH RELATION
Figure 3-1. System Block Diagram

11m

11m
PRESSURE
RELIEF VALVE

CLAMP
GAS SUPPLY

HIGH
PRESSURE
GAUGE
TWO STAGE
REGULATOR
LOW
PRESSURE
GAUGE
DISCONNECT
TUBE AT EITHER

BOTTLE

MEMORY UNIT

ENCLOSURE
INLET FITTING
(EPOXIED TO BASE)

Figure 3-2. Environmental Gas Supply System

PURGING
SUPPLY
BOTTLE

MAGNETIC
MEMORY
SYSTEM
It is then fed into the drum housing through another length of

plastic tubing and distributed throughout the drum housing
and hub assembly. From there, as previously explained, the
helium gas passes around the headplates and timing capsules
to fill the space inside the cover at a pressure of approximately
1/4 psi at room ambient temperature.
3.2.2 HEAD
ACTUATION
PRESSURE
SYSTEM

Operating completely closed loop within the environmental atmosphere is the head actuation pressure system, Figure 3-3.
The sole function of this system is to supply pressure to
diaphragm assemblies, located behind each timing and data
recording head, to actuate the heads to flying distance of the
recording surface. At this position, the recording heads "fly"
on the gas bearing generated by the rotating discs. The head
actuation pressure system can be divided into an upper and
lower section. The upper section distributes the pressure to
the heads via a distribution manifold, while the lower section
develops and controls the pressure. The lower section contains
the pressure pump, check valve, accumulator, dump valve,
pressure switch, and synchronous switch.
The head actuation, pressure-distribution manifold is made of
copper tubing and mounted under the drum housing. Outlet
tubes from the manifold mate with inlet holes in the drum
housing to distribute the actuation pressure to the data headplates. Four other outlet tubes are used to directly pressurize
the timing head assemblies. Two of these tubes are connected
to the two timing head assemblies by a section of plastic tubing.
The remaining two, intended for spare timing heads not installed,
are sealed off with a swagelok fitting or with sealed plastic
tubing. The distribution manifold inlet tube is connected with a
detachable fitting to the lower pneumatic actuation system on
the baseplate assembly.
3.2.2.1
PRESSURE PUMP. The pressure pump is a diaphragn.
type pump with a maximum rated operating pressure of 5 psi. The
diaphragm is driven by an AC solenoid operating from 115 VAC ,
single phase, 50/60 Hz source. The rated life of the pump is five
years under continuous operation. This rating is conservative,
as the pump operates at only 1-5/8 psI with a duty cycle of-I to 2
seconds approximately every 20 minutes.
3.2.2.2
CHECK VALVE. The check valve., located between the
pressure pump and accumulator, is a unidirectional valve that
permits gas flow only from the pump to the accumulator. A
pressure differential of 3/4 psi across the valve is required to
operate the valve properly and prevent backflow from the accumulator to the pump. A small orifice is provided on the inlet
side of the check valve to vent the pressure trapped in the line
between the pump and the valve and prevent backflow.

~

ORIFICE

..---.....
CHECK VALVE
~------~

ACCUMULATOR

IIEI

PUMP

) (ORIFICE

SOL

MANIFOLD
SHUT
OFF
VALVE

"--..,.-~

DUMP
VALVE

SOL

I

I

~
N. C.
TO PWR CONT

N. C.
TO PWR CONT ...---011.......

-0----------..

A

H
PUMP
ACTUATION

HIGH PRESSURE
DUMP
LOW/PRESSURE

~------~~~

Figure 3-3. Head Actuation Pressure System

NORMAL

mm

MAGN ETI C • • • • • ~.~.~rl~8
M EM 0 RY {~~~;~ipn

SYSTEM . . . . . . . . .

» .••••••

3.2.2.3
ACCUMULATOR. The accumulator, which has a
capacity of approximately 58 cubic inches, is a plenum chamber
which eliminates wide pressure variations within the system by
storing a supply of gas used by the pressure actuation system.
3.2.2.4
DUMP VALVE. Operating from 115 VAC, 50/60 Hz
power, this solenoid-operated valve consumes approximately
7 watts. It remains closed during normal operation, but opens
in the event of AC power failure or system shutdown and allows
a controlled discharge of the pressure system.
3.2.2.5
PRESSURE SWITCH ASSEMBLY. The pressure switch
assembly controls the pressure within the actuation system. An
expanding bellows comes in contact with three microswitch contacts. The three microswitches are set as follows: The "L"
(or low) switch controls a logic level signal to the controller when
the actuation pressure is at 1. 5 psi. The "A" (or actuate) switch
shuts off the pressure pump when a pressure of 1-5/8 psi is
attained. The "H" (or high) switch deenergizes the dump valve
to release the pressure if 1-3/4 psi is reached.
3.2.2.6
SYNCHRONOUS SWITOH. The synchronous switch
circuit shown in Figure 3-4, eliminates large switching transients caused by a sudden application or removal of power from
inductive loads on the AC line. Two circuits are used, one in
. series with the pressure pump and the other in series with the
dump valve. Basically, they are full wave bridge rectifiers
using an SCR as a switching element. The gating circuit of the
SCR is controlled so that voltage will only be applied to the pump
when the instantaneous line voltage is less than 20 volts, thus
preventing high voltage turn-on transients. When the pump is
commanded to turn off, current flow continues until it falls below
the holding current of the SCR. Energy stored in the inductor is
then at a minimum level and turn-off transients are avoided.
3.2.3 ELECTRICAL
CONTROL

The electrical control system, Figure 3-5, is energized when
115 VAC, 50/60 Hz, is applied to connector pins J4-A and J4-C.
The AC power is conducted thru an isolation transformer, the
normally closed contacts of de energized relays K2 and K3,
motor-start capacitor C1, and then to the main power and
auxiliary-start windings of the drive motor. The drive motor
is energized and the parallel MOTOR POWER ON lamp 11 is
illuminated as long as AC power is made available. The power
to the drive motor and the lamp 11 is interrupted whenever
thermal overload relay K2 becomes energized, as described in
subsequent paragraphs. Initially, AC power from J4-A and
J4-C is also conducted to the normally-closed contacts of relay
K1, controlling power to the DRUM SPEED LOW lamp 12. The
lamp 12 goes on and remains on as long as drum speed relay K1
remains deenergized,.

L-2

SCR 1

II
&111

FULL
WAVE
RECTIFIER

SCR 2
D4

D1

D8

R1

D2

D3

R3

R4

R5

'-S1----- - - - - - - - - - - ,
I
S2
~S2-2
L!;, ..,
I

D9

L

-

(H) HIGH (1-3/4 PSI) PRESSURE ACT. SW.

(A)

AVERAG~1-5/8PSI~RESSURE

ACT.

-

TB24 -

I

S~ ~
P

I

L ____

1------,
I
PUMP
I

SCR 3
SWITCH
D13

I

I

I

I

I
TS2-2

I

L _ _ _ _ ---l
D10

D12

Figure 3-4. Schematic-Synchronous Switch

-I
I

V1
DUMP

VALVE
~. O. --.J

Page
3-8
Section
3

JIO

>

>

CO>N
_01)-

++'
J 3 I I J I K L·I

AC FAILURE
WARNING
POWER SUPPLY
SENSE LINES

+18 VDC

+ 5 VDC
-12 VDC
LOGIC GND

\J~:23 0 C POWER

1

EM

A

H ....

B

I

\UT CABLE ASSY
P2

~

J
K t__-~---------------I K
L
L
M I - - - < . - - - - - - - - - - - - - - _ _ 1M

+18 V J
+5 v'R'

t__-_---------------I

~

VJ12

'-------l~_:::L
~-

r-

-12 vrt
I~
LOGI C 'M~--------------~~T~S1~-3~'----~------~~~
r.=
GND

~

!

1

53 "L"
PRES5URE
ACTUATED
SWITCH

r------+--+-----+-----+-----,.~S"'PA"""RE..-t~I-------t}

POWER SlPPLY{
SENSE L.INE
E
RETURNS
G
J4
A1 _ - - - ,

P4

:

J 4

I

~~------------~~~~r-~~--~r-~

A

TSI-4;..........

P

Il:> S5NORM

. r-o

~

,.&..

I

-

~

HEAD S ELECT LEADS
TlMI NG HEADS

"'-

--~+-'RED

~J5

,.&.--O--+-+------------i'E"
_

TS2-3

.---~~TI-+_-~--.--~'--+__+----__1~
K2 .,~+THERMAL)l'"'
OVERLOAD
RELAY

P,/.J 12

MA~NETIC
~

N
:I:

---------..

01)

8

Cl

BLUE

t=-n
b

'--·~---'-,--+-+--""""HK WHT ~

y:-O~ _

i

rJ

,

0

B

J
K

,~,/.>--j(-<~:!HT

I,
I

K3)

DRUM
SPEED
RELAY

lSHRO 0
IMOTOR
THERMAL SW
SI

T~1 2

,,-

M

~

13834 A C POWER
INPUT CABLE ASSY

C

PRE5SURE
ACTUATED

5

1

SWITCH

T52-4

~

IIV1

~

J3

TS2-2

~~~lE

N.O.

r__----~~~~_-------------~
t-

0 C F G '\

C3~

P~~P~

SPEED
DETEC TOR

!

L 11
Al
A2~~
'I P R
ESSURE
%-1 ,·SS-2
52 ACTUATED
"HM SWITCH
8
I
82
PjL2+-

S

>

CI---....... \

_I

SYNCHRONOUS
SWITCH

W':

....

~'fn~M

c(

---q

Q'

------frc~
r-tU\

CAPACITOR
CUTOUT
PRESSURE

u

T1W,2

C2*

I

: Kl

0


J~ I

\l~F D C POWE~

TJIKILI

~Q

a:~

-

11

TEIMI

B

A

Qa:
H \..

I

\UT CABLE ASSY

#

P2
~~~------------------------~~

~~~------------------------~K

~--~------------------------~L

t-t-----------------------------tM

-

vfR'
V~

-12
L OGI C
GND

I

MA:~
SENSOR

,l:

o

K

~
u

cc
>

~
~

~
~ .......

'

CZ

f=
F

CI

r

K~~
CAPACITOR
CUTOUT
PRESSURE
SYSTEM
RELAY

- 3.34 A C POWER
rNPUT CABLE ASS(

SYNCHRONO US
SWitCH
L 1!

\mo.Sl ~r'S!.-l I1 SS-2A2~.S2 PRESSURE
ACTUATED
"fI(
I
..
PRESSURE
ACTUATED
SWITCH

81

:
P L2

82

~ SWITCH

+-

~II

~~@
~

"':"

T~2

Vl
DUMP
VALVE
N.O.

~

D C FI~

I-'-'

':,

P-l
PUMP

rc""
LE AS'$(

THERMAL D
SW

f.=.

SPEE-D
DETECTOR

C~------I\

-

T~2
---. ---.

4>-<~:L
I !sHoo
~
~
(HI-<

:!!
J~

} HEAD SELECT LEADS
TIM I NG HEADS

r::"

•
I
I

~
,

I

S~·L·

PRESSURE
ACTUATED
SWITCH

o/J5

•
•I
•

rJDRUM
SPEED
RELAY

~n

S 5t1)Rt,t

•

I Kl

,

(J:::>

,. '"

K2 •
THERMAL>[
OVERLOAD
RELAY

ID

f.;.

-~~
.E

I

i~
1Y-J12

B

ret--

c;= -.",

r;
fO

N

I

f-

J!

J4

A

115 VAC
50-60H

~~
rI

+18 V~
+5

P~

-.-4+...-.......
- - - - -- - "'l

1Y'~2

M

to
""
P/JlIAI

IGI

12
DRUM
SPEED
LOW

101

•

I. CIRCUIT SHOWN WITH NO POWER APPUED.
ONLY.

C

I

NOTE:

.y C2 USED ON 4 DISC UNITS
<::II NOT USED ON 51 N I.

F

E

S4
MOTOR
RESET
N.C.

14
DRUM
TEMP.
HIGH

13

11

•

•

PRESSURE
LOW

MOTOR
POWER
ON

FIGURE 3-5. SYSTEM CONTROL Will.ING

Model 7302, Serial No. 14 and above
Model 7301, Serial No. 10 and above
--'----':.:.r~__i SYSTEM CONTROL

~!:!"'...,..-

WI RING

~ ~: ':::. '" .. "

.......

Drum speed relay Kl is controlled by the speed detector which,
in turn, responds to pulses from the disc speed magnetic sensor.
As the drive motor causes the disc speed to increase, the rate of
the magnetic sensor pulses to the speed detector increases proportionately, and when the disc speed reaches 3300 rpm, the
speed detector energizes relay Kl. The disc speed relay remains
energized as long as the disc speed is maintained above 3100 rpm.
When relay Kl energizes, the DRUM 8PEED LOW lamp 12 goes off
and the AC power at relay K1 contacts is switched to relay K3.
The energized capacitor cutout/pressure system relay K3 removes
AC power from the motor-start capacitor C 1, permitting the motor
to operate on the AC power applied from the normally-closed contacts of thermal overload relay K2 to the main power winding. The
MOTOR POWER ON lamp 12 remains on. The energized contacts
of relay K3 route the AC power to the synchronous switch to control the pump motor PI and dump valve VI operation.
On receipt of AC power at pins Ll and L2, the synchronous switch
88-1 section starts pump PI, and the 88-2 section energizes the
dump valve VI solenoid. The synchronous switch 88-1 and 88-2
sections contain 8CR switch circuits used for eliminating voltage
transients inherent in any circuits that require switching combined with inductive loads. The AC output of 88-1 to pump PI is
controlled by the "A" pressure-actuated 81, and the 88-2 AC
output to the dump valve is controlled by the "H" pressure-actuated
switch 82, as explained in the following paragraphs. Initially, the
synchronous switch applies AC power to pump PI and parallel
PRE88URE LOW lamp 13. Pump PI starts supplying pressure to
the head actuating system and lamp 13 lights and remains on. At
the same time, energized dump valve VI closes and allows the
head pneumatic system pressure to build up to operating level.
The dump valve, closed when energized, opens to allow a controlled discharge of pressure whenever system shutdown occurs
or AC power is inadvertently removed.
When the pump brings the actuating system up to the required
average pressure of 1-5/8 psi, the "A" pressure-actuated switch
81 opens, causing the synchronous switch to interrupt AC power
to pump PI. The pump then stops and PRE88URE LOW lamp 13
goes off.
If the system pressure exceeds 1-3/4 psi at any time, the "H"
pressure-actuated switch 82 opens, causing the synchronous
switch to remove power from dump valve VI. The deenergized
dump valve releases the gas until pressure returns to normal.

MAGNETIC
MEMORY
SYSTEM

Page

3-10

3

If the pressure drops below 1-5/8 psi, the pump will be turned

on by action of the "A" switch S1 and pressure will be restored.
When this occurs, the PRESSURE LOW lamp will come on for a
few seconds, but the operation of the unit will not be interrupted.
When the head actuation pressure is above 1. 5 pSi, indicating the
heads are actuated properly, the ilL" (low) pressure-actuated
switch S3 closes to provide a status signal from pin J3-E to pin
J3-H. When switch S3 is closed to the normal state, the signal
indicates to the control logic that the drum is at operating speed,
the head pressure system is activated, and the system is ready
for operation. If the ilL" switch is opened by a reduction in
pressure below 1. 5 psi, an abnormal state status indication is
switched to pin J3-H and sent to the controller.
The drive motor is protected from thermal overload by parallel
thermostats T1 and T2. If the shroud temperature reaches 150°F
or if the motor housing temperature reaches 270°F, the respective
thermostat, Tl or T2 closes, applying AC power from P4-A
through the completed thermostat switch patch to thermal overload
relay K2 and the DRUM TEMP HIGH lamp 14. Relay K2 energizes
and lamp 14 remains on as long as the overload condition exists.
When relay K2 is energized, AC power is removed from the driv,
motor, the synchronous switch, the dump valve, and the pump.
Opening of the AC power circuit deenergizes the solenoid dump
valve, causing the head actuation pressure to reduce to zero, and
automatically retracting the read and write heads. Drum speed
relay Kl is deenergized when the disc speed slows below 3100
rpm, because of the deenergized drive motor. When relay K1
deenergizes, the SPEED LOW lamp 12 goes on again.
When the actuated thermostat, T1 or T2, cools, its contacts will
automatically reopen, removing the AC power applied from the
thermostats to thermal overload relay K2. However, relay K2
remains energized because of the holding AC voltage applied from
the normally-open contacts of K2 through MOTOR RESET switch
S4. To restart operation, MOTOR RESET switch S4 must be
pressed to remove the holding voltage from relay K2, permitting
the relay to become deenergized and the DRUM TEMPHIGH lamp
to go off. The AC voltage will then be reapplied to the drive
motor, dump valve, and pump.

MAGNETIC
MEMORY
SYSTEM

3.3 SYSTEM
ELECTRONICS
DESCRIPTION

The memory system electronics contains the components
and circuits necessary for address decoding, the generation
of timing and control signals, and the recording and
recovering of data. The logical organization of the electronics is dictated by the interface requirements of the
Hewlett Packard 2115A/2116A Digital Computer. These
requirements specify a memory organization of 90 data
sectors per address. Each sector contains 1088 data
bits and must have the capability of being written in or
read from, singly or in sequence, at a nominal data rate
of 3 MHz. Furthermore, the access time to any sector
must be no greater than 35 msec.
To satisfy these requirements, the Digital Development
Corporation Magnetic Memory System is organized such
that each address sent by the controller actually addresses
4 data tracks. Since the memory discs rotate at a nominal
3450 rpm (17.4 msec/revolution), two tracks are accessed
in parallel during one revolution and two different parallel
tracks are accessed during the second revolution. Thus,
to one address the controller can send 97, 920 (90 times
1088) data bits at a rate of 3 MHz within a 35-ms period.
However, the interface logic separates this 3 MHz data
stream into two 1. 5-MHz parallel data streams (channels
A and B) and writes 24,480 data bits on each of two tracks
during the first of two 17.4 ms disc revolutions. During
the second revolution, two other tracks automatically receive
24,480 data bits each. Thus within 35 ms, the disc can
store 97,920 (3 MHz) data bits, at one address (controller
sent), but four physical tracks are actually used.

3.3.1 PHASE
MODULATION
RECORDING

In the Magnetic Memory System, phase modulation is used
to record the data and the timing signals. Phase modulation,
Figure 3-6, is defined as having one phase of the write
current for "l"s and the opposite phase for "O"s. Consequently, the use of phase modulation recording always
requires a write current change to occur at the center of
the bit time.

MAGNETIC
MEMORY
SYSTEM
I I I

1

J1JLJL
CURRENTJ/!
CHANGE

I !
1 BIT TIME

1.-1
BIT

Figure 3-6.

o

0

-*

I
I

1

Section

3

1

o

11 :
I

I

1-~1
BIT

o

Page 3-12

BIT

I
I

1-.j. 1 ~ 1.j. 1-+1

BIT

BIT

BIT

BIT

Phase Modulation Recording Method

If the current is going positive at center bit time, then a "1"
is being recorded; if the current is going negative at center

bit time J then a "o,t is being recorded. Details of the
phase modulation recording process will be discussed in the
section which describes writing,
3. :3.2 C LOCK AND
TI:\UNG
SIGNALS

The Read/Write clock signal is derived from a clock track
recorded on the periphery of one disc. This signal is effectivelya phase modulated signal of 25,325 "1 "s, each of which
defines one bit time or clock period for all operations. A
spare clock track is recorded in phase with the master and
may be used to recover data recorded with the master clock.
A switch on the relay mounting board allows selection of
ei the r clock track.
The timing signals, Track Origin (TOP) and Sector Clock
(SC a , SCb) ~ are derived from a timing track and also recorded
on the periphery of a disc. The data on the timing track is a
particular sequence of phase modulated "1 "s and "0 tIs which
are logically decoded to provide the two timing signals. A
spare timing track is provided and selected with the same
switch which selects the spare clock track.
The low level (10 - 20 mv) clock and timing readback signals
are amplified by linear preamplifiers which have a voltage gain
of approximately 50. The clock and timing preamplifiers are
located on the top endplate of the disc housing assembly,
placing them in close proximity to the read heads, thus
maintaining noise pick-up at a minimum. The amplified
linear signals are routed through the baseplate to the input
of read amplifiers located in the electronic card rack. The
read amplifiers transform the amplified signals into logiclevel outputs, Conversion of the phase-modulated timing

MAGNETICIIII
MEMORY
SYSTEM

BID

signals into NRZ signals is accomplished by a read flip-flop
which is clocked with a clock pulse derived from the clock track.
3.3.2.1
READ/WRITE CLOCK GENERATION. From the
clock read amplifier, the clock is coupled to the input of two
idenreal clock generator circuits which shape the symmetrical
clock into pulses of predetermined width. The clock generator one-sltot multivibrator will trigger on either the positive
or negative-going edge of the clock depending on which input
is used. (See Figure 3-7.)

INPUT TO CG

n.......~n__...n'-_...n~_. .rL
--11__~n__. .n~~n~__

OUTPUT A CG
OUTPUTB CG
WRITE/READ
CLOCK

25325 BITS/REV
25325 BITS!REV
50050 BITS!REV

Figure 3-7. Clock Generation Timing
Clock generator circuit A, Figure 3-8, is wired to trigger
on the positive-going edge of the clock. Thus two clocks,
designated C 1 and C2 , are formed which are respectively
180 0 out of phase.

3

+5 __~~3____~~~l4
2

________-J

WRITE/READ
CLOCK

R/W CLOCK ALLOW

Figure 3-8. Clock Generator Circuits A and B

mm

MAGNETIC
MEMORY
SYSTEM

Page 3-14
Section 3

II
The outputs of the clock generators are inverted, ORed and
gated by a read/write clock allow signal in a 3-input NAND
gate. Clock generators C 1 and C 2 thus form the 3 lVIHz R/W
clock of 50, 650 bits/disc revolution.
3.3.2.2
ORIGIN PULSE (TOP) AND SECTOR CLOCKS (SC)
GENERATION. The origin pulse and sector clocks are
recorded on the same timing track and share a common timing
preamplifier. The timing is written in a logical code of "1' sit
and "O's" and is decoded into NRZ timing with a decode flipflop located in the electronic card rack. The NRZ multiplexed
timing signal is then separated in an origin pulse and sector
clocks by shift registers and logic gating circuits.
The TOP pulse is six-clock periods wide, with respect to the
read/write clock, and is logically true every other disc
revolution.
There are 45 sectors per disc revolution, plus one guard
band. Each sector is 1124 clock (3 MHz) bits in length. There
are two sector clocks per sector, each sector clock being
logically true for one-clock period. The first sector clock
(SCa) is logically true 68 bits before the second sector clock
(SCb) I except for sector one. SCa is true 62 bits prior to
SCb for sector one. The guard band is 70-clock periods in
duration and follows the leading edge of the index pulse (an
internal memory signal) every disc revolution.
Digital Development Corporation Drawing Number 13779, which
is included in Section 6, shows the above timing relationship
in detail.
3.3.3 WRITE
LOGIC

Data to be written into the disc memory is presented to the
disc file as a 3 MHz NRZ signal. The disc system is designed
to write this data at a 1. 5 MHz rate. It is therefore necessary
to divide the incoming data into two parts. Data is gated
with the read/write clock allow (RWA) and sent to two flipflops as shown in Figure 3-9. One flip-flop is clocked with
C1 and the other is clocked with C2. One flip-flop output
will consist of the odd-numbered bits, the other output will
consist of the even-numbered bits. Data is to be clocked
into the write amplifiers at clock C1 time, Figure 3-10,

MAGNETIC rqll'<~""l
MEMORY Sec,'IOft
SYSTEM
so it is necessary to resync the odd-numbered bits again with
sample flip-flop. This circuit is clocked with clock
C2.
The timing relationships are shown in greater detail on
Digital Development Corporation Drawing Number 13779,
provided in Section 6.
~other

R/W CLOCK .
ALLOW

r-....

~--~

DATA TO WRITE AMP A
DATA TO WRITE AMP A

Cl

NRZ DATA
FROM
CONTROLLER

L-_'-I D

C2--~C

Q

~-t~

Q~""".

DATA TO WRITE AMP B

DATA TO WRITE AMP

Figure 3-9. Separation of NRZ Data from Controller into
Two Data Lines

B

Page 3-16
Section

3

Cl

C2

R/W CLOCK
NRZ DATA

ODD SAMPLE
FLIP FLOP
OUT

DATA TO WA

,..;----+---1

EVEN SAMPLE
FLIP FLOP
OUT
ODD
FLIPFLOP
NO.2 OUT

0

DATA TOWA

0

A

Figure 3-10.
3.3.4 WRITE
AMPLIFIER
OPERATION

0

B

Timing For Data Separation

Ti~e function of the write amplifier is to convert the NRZ data
into phase modulated data, and to control a pair of write current
drivers. Conversion of NRZ data into phase modulated data is
accomplished by a special flip-flop located on the write amplifier card. Data and data are applied to the write flip-flop
through dc control gates which resynchronize data and data
with clock Cl. The output of these gates are conducted to the
bases of the write flip-flop switching transistors. If data and
clock C 1 are TRUE, the write flip-flop will set. If data and
clock Cl are TRUE, the write flip-flop will be reset. In addition
to the dc control gate outputs which set or reset the write flipflop, another gate is added. This gate is common I2....both bases
of the write flip-flop switching transistors. Clock C2 is connected
to this gate. Remember that clock C2 is 180 displaced from
clock Cl. Consider now that the flip-flop is setting and resetting
depending on the condition of (data and C 1) and (Oara and C 1). The
flip-flop will be set or reset with the positive-going edge of C 1.
If C2 is input to the bases of -the write flip-flop switching transistors, then at each C2 time the flip-flop will toggle to the opposite state.
0

The phase modulated data and data are coupled to a pair of write
enable gates, Gl and G 2 , Figure 3-11, which allow passage only
if the write enable signal is present. This signal must be high
(true) to enable the write amplifier. If the write enable signal is
low, then write enable gates Gl and G2 will be inhibited.

t lOO~O~

TI

DATA

DATA

ENABLE

ENABLE
WRITE
DISABLE

+v

Figure 3-11. Write Enable/Disable Gates

11m

MAGNETIC
MEMORY
SYSTEM

3

Current drivers D1 and D2, Figure 3-1.2, are NPN transistors
with emitters at ground potential and collectors connected to
current-determining resistors R1 and R2. The R1 and R2 values
are set to allow 125-ma of write current to flow through each half
of write transformer Tl. Because phase modulated data and data
are 1800 out of phase with each other only one current driver is
"on" at anyone time. Collector potential V cc is supplied to the
center tap of transformer T1 via disabling gate G3. Disabling
gate. G3 is a PNP transistor switch with emitter connected to
+V and collector connected directly to the center tap of transformer Tl. The base of this transistor must be grounded to
enable this switch. If the input to this switch goes to +18V at
anytime, write current will cease to flow.
Write amplifiers A and B deliver write current to all read/
write heads in the memory system. Only one head can be
written into at one time by each write amplifier. Current
distribution is accomplished by forming a matrix of ''X'' and
''Y'' lines. This matrix will be discussed in detail in another
section. F or now, consider that the memory consists of one
read/write head. The ''X'' lines will be connected through the
''X'' amplifier; the ''Y'' line will be returned to ground through
one t'Y" amplifier.
The write amplifier, Figure 3-13, has been enabled and is
delivering phase modulated current to the write transformer
in push-pull fashion. Diodes D1 and D2 are turned off until
the ''X'' amplifier receives an enable signal at the bases ofQl
and Q2. Current will not flow until Q3, in the ''Y'' amplifier, is
turned on to supply a ground return at the center-tapped read/
write head. The ''X'' amplifier and ''Y'' amplifier are enabled
at the same time by the decoding of the track address lines.
At the write transformer, consider point "A" positive with
respect to point ''B''. Current will flow through D1 and D3,
the emitter collector junction of biased-on transistor Q3,
through D5 and D7, through the left half of the read/write head,
completing its path through transistor Q3 to ground. A similar
current path through the right half of the head is used for the
opposite polarity signal out of the write amplifier. Waveforms
of normal and abnormal write current are provided in Figure
3-14.

"WRITE CURRENT OUT

DISABLE
G3

tJ:JTl

PHASE MOD
DATA FROM
"WRITE

-~

PHASE MOD
WRITE
FLIP FLOP

-v

"WRITE ENABLE

Figure 3-12. Write Head Current Drivers

MAGNETIC
MEMORY
SYSTEM

Page 3-20
Section 3

WRITE
AMP
"'-I-~--- B

A

1------I

-I
Dl

D2

XAMP
D4

+V

I

I

I

!

, - - - - - - +V

I
I

___ J
D6

D5

YAMP

I
I
I

Q2

L ________ _

I

I

Ql

ISEL~CT
I
I

l

I

READ /WRITE HEAD

I
I

.--t--'"

I Y SELECT
I

I
L ____ ---=J
Figure 3-13. Write Amplifier Push-Pull Operation

I

IIID
B
+125 MA
""'~--f"'7 STRAY CAPACITANCE

BEING CHARGED

o
-125 MA

NORMAL WRITE CURRENT

1 BIT

1 BIT

PERIOD
+125 MA

+125 MA.

o

o

-125 MA

-125 MA

maH RESISTANCE
SHORT IN HEAD

DmECT SHORT
IN HEAD

LABNORMAL WRITE CURRENTS

Figure 3-14. Write Current Waveforms

J

MAGNETIC
MEMORY
SYSTEM
3.3.5 ADDRESSING
AND HEADPLATE ORGANIZATION

There are up to four rotating discs located within the disc
housing. Each of the flat sides on the discs is used for data
storage. Each flat side has a capacity of 64 recording tracks,
and is serviced by one headplate assembly containing the 64
read/write heads. This section describes the electrical
organization of the headplates and their associated addressing
circuitry.
3.3.5.1
HEADPLATE AND MATRIX ORGANIZATION.
Electrically, the 64 read/write heads of each headplate, Figure
3-15 and 3-16, are separated into 4 "X" lines, each containing
16 read/write heads. Each ''X'' line is serviced by one ''X''
amplifier. Each of the 16 read/write heads is a center-tapped
coil. The center tap of each head in the ''X'' line is made common with one head in each of the remaining three ''X'' lines.
A functional schematic diagram of the headplate organization,
Digital Development Corporation Drawing Number 14011, is
provided as Figure 3-17.
Matched pairs of isolation diodes are in series with each of the
read/write heads. These diodes reduce noise as well as prevent
cross-coupling into an unselected head. All electrical connection
and input points are made on a terminal board mounted on the bacL
of each headplate. This terminal board also contains the isolation
diodes. Total matrix size of each headplate is 4 ''X'' and 16 "Y"
lines. (See Figure 3-17.) As there is a total of 8 headplates, the
second 4 headplates use the same 16 ''X'' amplifiers that service
the first 4 headplates. Separation is accomplished with 16 different "Y" lines. Total matrix size is 16 ''X'' lines (selected
two at a time) and 32 'ry" lines. The ''X'' amplifiers are located
on the back of the lower 4 headplates with jumper wires routed
to the upper 4 headplates. The 32 'ry" lines are routed through
a connector on the baseplate from the outputs of 32 "Y" amplifiers
located on the "Y" decode matrix board. The ''X'' select lines
to the ''X'' amplifiers are routed through a connector on the baseplate from the 16 decode drivers outputs. Track selection is accomplished by enabling a particular ''X'' amplifier and "Y" amplifier.
3.2.5.2
ADDRESSING. As previ'ously discussed, data from
the controller is divided into two sections, A arid B. This data
is transmitted to separate write amplifiers and written simultaneously on different recording tracks. Because one addressable track, with respect to the controller, is two disc revolutions
in duration, it is necessary to switch to two new tracks at the end
of the first revolution of the disc. Switching is accomplished
within the disc system by switching track address flip-flop TA at
index time. Therefore, the address sent by the controller remail
the same during both revolutions of the disc.

mm
Bl
ISOLATION DIODES

"Y" AMPS
:It

YO

"X"

SELECT

AMP

Y2
"X" SELECT

SELECT

Y4

SELECT

Y6

SELECT

Y8

SELECT

YlO

SELECT

Y12
~-

SELECT

Y14

SELECT
L.....-"'-

Y15 SELECT

Xl
Figure 3-15.

16 R/W Heads with Common X Amp (1/4 Headplate)

WRITE
AMP

XO

Xl
SELECT

SELECT

X2
SELECT ~---r

~---r

X3
SELECT

11m

~-----,

~--~--------'---~--~--------+---"---+--------~---4~~~

MORE

MORE

13
MORE

HEADS

HEADS

HEADS

HEADS

13 MORE
fly"~

Figure 3-16. Block Diagram

of Typical

Headplate

YI

LINES

(J)

..._.
G

n

0
:::J
c,.,

"'0

0

c



I

~

,j:..

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BOl>.RD

(4 PLAcE-'S)

(

"""'I\\\.~AL..

",{t.D+'U.""\"I:. .....

I

15O"Rl) (4

!'L(.S···U4J l4/lP->,L3)

Page 3-25
Section 3

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FIGURE 3-17. HEADPLATE ORGANIZATION'
I-IEADPL/io,IiO:

0 .•. t'& .. ' D I • • L. . . . . . ...

ORC:,o.Nrz.,b., \O~

~.•~~•• A.t.! L""

.'

''--

',.

",

','

'"

3.3.5. 3 ADDRESS DECODl~G.:
3-18·, is .accomplished bySelecttnlapartiQhlar
.and a particular "Y" amplifiet.The''XffampliUers recellve"
their selection command from
"'X" decode driver ........•.....•.. ' ......' "/'
''Y'' amplifier receives its enabling' commandfrotnoneoftw;9:-<'
''Y'' decode drivers. Table 3-1 lists the relationship between
the octal address, the "X" line, and the headplate.Recall
that it is a ''Y'' line that changes with TA; the ''X'' linedoesnQt
change with TA. Table 3-2 lists the relationship between the .
octal address, the''Y'' line, and the headplate.

an

'i

Y

DECODE
DRIVER

iii'

i'

Selected when Addresses
08 -:778 are TRUE

FROM

MEMORY'
SYSTEM
FROM

Selected when Addresses
8 -177S are TRUE

---.10°

CONTROLLE

Figure 3-18. Address Decoding

E~h "Y" decode driver accepts afotir"'bifbin~rYCode,~d,
depending upon the code composition,'selectsapa:rticulaT'uyu
amplifier that, in turn,supplies a gro4nwerfrom.theelectronic
card rack. Outputs from the data and timing preamplifiel"sare
processed to the. electronic card rack through a connector. The
data preamplifiers receive their' inputs directly from the
read/write heads through read' diodes loca~d.()n· tile ''Xu
amplifiers.. (Recall that the ''X'' amplifiersiatelocated()n
the back of the four lower headplates.)
The function of the ''X''alll~ifiet~ln.thereadmodeiSto,proVide
a forward biasing curreAttQi:~~~~ddiodesAAd thei~tion

P-d.ge 3-32
Section 3
B8,B16

B7,B15

B5, B13

B6,B14

B3, Bll

B4,B12

Bl,B9

B2,BIO

X .A

o

20
11

8

~

8

22

32

8

23

8

8

26

8

.:. ::'"

17

27

8

ADDRESSES START
AT YO (AI, CI)
AND END AT Y15
(AI6, CI6).
ALL HEADPLATE
ADDRESS START
AND END IN THIS
MANNER.

Y2

A4, C4

Y3

A5, C5

Y4

A6, C6

Y5

FIRST HALF
ADDRESS = TA

A7, C7

Y6

SECOND HALF
ADDRESS = TA

AS, 08 .

Y7

A9. C 9 Y 8

Al 0, ClO

Y9

All, Cli

YlO .

A12, C12

. Yll

A13. C13

Y12

A14, C14

. Y13

A15, C15

Y14

A16, C16

Y15

.

.~, :..(

",'

(Bl & B2);

C3

8

34
·8

·.06•

Yl

NOTE: ADDRESSES START
AT Xo (B7 & B8)
AND END AT X 4

8

8

12 .

8

A2, C2
A3~

23

06

.YO

8

·31

12

AI, Cl

HEADPLA TE Ll
Figure 3-19. Headplate Versus Address Location Diagram

o
.. TO READ
AMP A

WRITE
AMP
A

DATA
PREAMP

P

..

j\

A \

TO READ
AMPB

r--+
DATA"
PREAMP/

j\
B

II

WRITE
AMP
B

\

11 iii

7 OTHER X AMPS

...

......
'"
SELECT

X~_~

.
X
AMP

........
-....._

...._ _......~

....

P"1~l)"

~

;-

..::.. ....

~,

,r

, ., ..... - ..

"'(0'~

A~ ~ y ,.....---1---...- - - - t.... 8 MORE
~ SELECT'
,
HEADS

. . . . . . . . . ---....----1----_---<:
,

8
MORE

X

~

"--

T- -

OTHER
AMPS

AMPS

.,.--....
~~ .... t- T~",\I"'" ~~

'"
SELECT

~T07

T07
.....
OTHER

HEADS

....._ ......
o} X

X
AMP

X

7 OTHER
X AMPS

15 MORE HEADS

15 MORE HEADS
~<_.~a <:l_?O

Read/Write/Select Block Diagram

11m

MAGNETIC
MEMORY
SYSTEM

Page 3-34

Sect jon 3

m
diodes in series with each read/write head. The function of
the "Y" amplifiers in the read mode is to provide a return
path for the bias current. Head selection in the read mode
is the same as in the write mode.
3.3.6. I
READING WITH A TYPICAL READ/WRITE HEAD.
(Refer to Figure 3-21.) Assume that tlX" amplifier Xo and tly"
amplifier YO are selected. DC current flows from V through
resistor RI, diode DI3, the emitter-collector of transistor Q2,
diodes D2 and D4, half of the read/write head, and through QI
to ground. DC current also flows from V through resistor R2,
diode DU, transistor QI, diodes DI and D3, half of the read/
write head, and through QI to ground.
Read buss diodes Dl2 and D14 are forward biased by current
flowing from V through resistors R2 and RI, transistors QI
and Q2, read buss diodes D12 and D14, and through Q2 and QI
to -4V DC. The low-level AC readback signals are coupled to
the input of the data preamplifiers. The linear data preamplifier
outputs are coupled to the read amplifiers where they are further
amplified into logic levels. The read amplifiers are saturable
comparators that provide a positive voltage or ground level output, depending on the relative polarity of the input signal. DC
feedback is used to ensure signal symmetry.
The readback signals are then decoded into NRZ data with D
flip-flops that are gated with the data strobe clock. (See
Figure 3-23.) The data strobe clock is delayed so that it will
examine the second half of each bit. The flip-flop will set if
the data is high at strobe time and reset if the data is low at
strobe time.

- - + - - -.....- -...

+V

R2
FROM
WRITE
A:MP

>-~-+---------~

AMP~IFIER
Xo

Dll

1\

I~--------I

D12

~~AD II

~~)
.."..---+-.

D13

I
I

XOSELECT

DA T A PREAMPLIFIER

~

- - - . --

I

Q2

---~

r-=--I+V

L -

YO
SELECT

I
IL

Ql

I

15 MORE
HEADS

-

_ _ _-_Y AMPLIFIER Y_O

1- --- - - - - ~ - -

I

_-.J

Figure 3-21.

II

Read/Write/Select Schematic

_J

AIvIP

iii

Figure 3-22. Not Used

3.3.7 STROBE
SELECTION

Because of variations in head inductance and disc plating
characteristics, data to be recovered does not always occur
at the sarr~e time with respect to a fixed clock. Some data
will be earlier, some later. The electronic system looks at
the data for one bit time at the beginning of each sector. If
the data is early then an early strobe will be selected and
processed to the data decode flip-flop. If the data is late,
then a late strobe will be processed to the data decode flip-flop.
The sample window, Figure 3-23, becomes true for one bit
time at the beginning of each sector. Sample gates A and B
become true and allow the sample clock to be applied to their
respective sample flip-flops. Data from each data read
amplifier is applied to the input of the sample flip-flops
where it will be compared to the sample clock. If data and
sample clock are both true, then the sample flip-flops will set.
If the data and the sample clock are not true, then the sample
flip-flop will be reset. Each sample flip-flop operates independent of the other. The data at sample window time is
always a logical "1" and is written that way by the memory
system. If the sample flip-flop sets, then an early strobe is
processed to the data decode flip-flop to strobe the data during
that particular sector. If the sample flip-flop is reset, then
late strobe is processed to the data decode flip-flop for that
sector. The sample clocks, early and late strobe, are derived
from an adjustable delay line. Input to the delay line is clock C2 .
(Recall that data is written at clock C1 time. Clock C2 occurs at
center bit time and must be delayed to strobe the second half of
the data bit.) The delay line is capable of 250 nanosecond delay in
12. 5 nanosecon.d steps. Delay settings are determined by the
manufacturer during test operations.

3.3.8 COMBINATION OF
DATAA+
DATAB

When data is sent from the controller it is sent at a 3. 0 MHz rate.
The data is divided into two data streams, A and B, and is written
into different tracks. Before data can be sent back to the controller,
it must be reassembled into 3.0 MHz data. Data from decode
flip-flop A is resynced to clock Cl by a NAND gate and processed
through a data latch-circuit. Data from decode flip-flop B is
resynced to clock(ST)by a NAND gate and processed through a
data latch circuit. Data latch A and data latch B are reset by

DECODE
FLIP-FLOP A

~--

__----------------------------~D

NRZ
DATA A

Q

C

SAMPLE FLIP-FLOP A

SAMPLE
CLOCK A

SAMPLE
GATE
A

LATE STROBE
SAMPLE

WINnow
SAMPLE
GATE
B

AND/OR FUNCTION
M
C
Q I - - - -......r......
'---_.::..I

~...-.t

SAMPLE
CLOCK B

LATE STROBE

DATAB

DECODE
FLIP-FLOP B

-------------+""""D

>--....

C

Figure 3-23. Strobe Select Circuitry

Q

NRZ
DATAB

mm

MAGNETIC
MEMORY
SYSTEM

P·age····a...39

Section 3

clock C2 and Cl respectively. The outputs of the data latches
become true with their respective clocks and the two outputs are
combined through an OR gate. The OR gate output is inverted
and processed to the controller. The OR gate in inhibited from
operation during the write mode by an inhibit signal.

3.4 SYSTEM /
CONTROLLER
INTERFACE
3.4.1
DIAGRAM

A functional block diagram of the system is provided in
Figure 3-24, consisting of two sheets. Data control logic
is shown on sheet 1. Address decoding logic is shown on
sheet 2. Sheet 1 of the drawing depicts elements of the eight
circuit cards (A1, A10, All, A13, A15, A16, A17, A18).
Card A1 contains the four read amplifiers; one each for clock,
timing code, channel A data, and channel B data. Card A10
has the write amplifiers (for both data channels A and B), and
also several inverters. Card All is the delay line card. Card
A13 is the terminator card that has line termination resistors
and voltage monitoring diodes. The function of card A15 is to
generate the three clocks (Cl, C2, and ST) and to supply a
current sink for the disc-speed relay.
Card A16 is the Interface No. 1 card. As shown on the block
diagram, the lower portion of card A16 has flip-flop shift registers and gates used for generating the sector and index timing
signals from the coded information recorded on the timing
track. The upper portion contains channel A and Bread flipflops and the gates required to serialize the two data streams
of 1. 5 MHz data into a single 3 MHz stream.
Card A17 is the Interface No. 2 card. The upper portion
generates the signals (TOP and T A) required to simulate an
l800-rpm disc speed and also generates the delayed ready
signal (RY). The three flip-flops shown in the center of the
A17 logic, separate alternate data bits in the 3 MHz data write
into two parallel 1. 5 MHz data streams. The read inhibit logic
and the logic that causes the flow of read/write clocks to begin
at the correct times is below these flip-flops. At the very
bottom, there is the write enable logic that causes writing to
continue for a short time after the write command is removed.
Card A18 contains the circuitry necessary for selecting the
correct data strobe for each of the two data channels.
Sheet 2 of the functional block diagram shows the "Y" and "X"
decode logic that generates the "X" and "yn select signals that
control the matrix of read/write heads. The inputs consist of
the address lines (TO through T6) from the controller and a
signal (T A) generated in the memory that selects different halves
of the memory during alternate disc revolutions.

Page 3-41
Section 3

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3.4.2 PRINCIPLES
OF
OPERATION

The disc speed signal on pin P3-C is a twice per revolution
(17 ms) signal. The disc speed detector contains three oneshot multivibrators and uses the disc speed signal to determine
when the disc reaches approximately 3300 rpm. When the disc
has reached this rotational speed, the speed detector draws
current through the disc speed relay coil. Closure of the disc
speed relay causes removal of the starting capacitor from the
drive motor circuitry, and energizes the pneumatic pump
which supplies the pressure for head actuation.
When the heads actuate, the memory ready signal on pin P3-H
goes high and the interface logic is activated. As soon as the
heads have actuated, the preamplifiers will cease oscillation
and a 1. 5 MHz square-wave clock will appear at pin 30 of
Card A 1. There will be 25,325 clocks per disc revolution.
The positive and negative transitions of the clock alternately
fire two 170-ns one-shot multivibrators that provide the two
timing signals C1 and C2. A third one-shot multivibrator
operates in parallel with the C2 one-shot multivibrator and
provides the SO-ns ST (strobe) timing signal.
The track index (IX) and the sector clock (SC) are timing signals
that define the beginning of each revolution and each sector
respectively. They are generated from a coded pattern recorded
on the timing track. The timing code (TC) is present at pin 31
of Card A1 and is strobed into and shifted through the register
stages A, B, C, and D with ST. Six "1 "s in the timing code
define the revolution index or origin point; two "1 flS occur at
each sector clock time. A single "1" is used to begin the flow
of clocks to the controller during writing and reading and to
generate the strobe select window.
As the six bits shift through the register, the outputs A, B, C,
and D are combined to form the index (IX) signal that is three
bits (1. 5 MHz) in: length and occurs once per revolution (17 ms).
b:s the two-bit code passes through the shift register, the condition
BCD is detected, generating the first sector clock (SC a ) signal
that is one-half bit (1. 5 MHz) in length. Two of these sector
clocks occur for each sector of data and are spaced 32 bits
(1. 5 MHz) apart. The second sector clock (8Cb) of each pair
defines the beginning of each sector. As the sil~l~bit pattern
passes through the shift register, the condition BCD is detected
and is used as a "window" in the strobe selection circuitry and
is also to initiate the secondary shift register EFGH. The shift
register output F is used to begin the gating of read write clocks
to the computer during a write operation. The shift register output H is used to begin the gating of read write clocks to the computer
during a read operation.

MAGNETICfl'III\11
MSYSTEM??
EM0 RY;j!I;5M~I'I~~~~~• • • • ~• i• • • • •

The disc controller requires a track origin pulse (TOP) once every
other disc revolution (34 ms); it is generated by gating through
every other IX. Before reading or writing can commence, the
controller must receive a ready status from pin J10-FF. This
occurs after a memory ready (P3-H) goes high and is delayed
at least two revolutions time by being clocked by TOP through
two D-type flip-flops. The sending circuit for the ready signal
is an open-collector transistor that allows the controller to
pull the ready line high to the not-ready condition, when DC
power is lost in the memory system. The signal TA, which
appears at pin 13 of Card 17, is used in the 'ry" decode to select
different halves of the memory during alternate disc revolutions.
The source of TA is the flip-flop that is used for generating
TOP by gating through alternate index signals. Signal TA is
high during the revolution following TOP and low during the
revolution preceding TOP.
The Read Inhibit (RI) signal at J10-H goes low whenever a head
change signal or write command is detected. It will remain low
beyond one sector clock B following the removal oUoth the head
change and write command signals. Read inhibit (RI) is generated·
by two cross-coupled gate latches. The first latch is set and Iff
goes to ground when either head change or write command occurs'!
After both head change and write command have been removed,
their absence and timing signal F cause the second latch to set.
As soon as the second latch reaches the set state, the first
resets, causing RI to go high (FALSE).
The following is a description of the write/read command
operation in the disc memory. Digital Development Corporation
Drawing Number 13779 is provided in Section 6 and consists of
a timing diagram for the memory and interface signals. Sheet
4 of that drawing shows the events that occur dllring the beginning
and the ending of a command; sheet 3 shows the events occuring
during the data. transfer portion of the sector. The write command
(W) at J10-S comes true (0 volts) at the leadingeqge of the second
of the sector clock pair (SCb). The occuranceofW immediately
sets the write enable latch, thereby permitting writing to begin
because of the falling of the enable sign_al at pin 29 of Ca.rd A17.
At this time, data from the controller is not being written;
instead, five "1' l s are written. These .are to be used as a pre~
amble during reading.
Four bit times (1. 5 MHz) after the appearance of the write command, F gate causes the setting of a latch that allows the read
write allow (RWA) atA17-17 to come true. RWAgates 3 MHz
clocks to the controller, which in turn, begins the sending of

mm

MAGNETIC
MEMORY
SYSTEM

m
data to the memory. Data from the controller (data write)
at J10-M is inverted at A18-41. This same inverter causes
the writing of preamble "l"s when the RWA signal is low.
The inverted data (3 MHz) is converted to two parallel streams
of 1. 5 MHz data by three D-type flip-flops at pins 10, 11 and
12 of Card A17.
The controller bits being conducted to the channel A data stream
are subjected to a one-bit delay in order that the data bits on
both channels can be written and read simultaneously. When
the controller detects the 1088th negative shift in the read write
clock it removes the write command. This causes RWA to fall
and prevents clocks from being sent to the controller. Also,
because A18-40 is now at ground, all "l"s are now written in
the memory. Writing continues until the next sector clock
(SCb - the second of the pair) is detected. The enable latch is
reset causing A17-29 to go high. It should be noted that the
first sector clock (SCa) of a pair occurs during that portion of
a sector in which data is written, but that particular sector
clock will not reset the enable latch even though it switches one
of the gates in the latch. The other gate in the enable latch is
kept from switching by the presence of the write command.
Thus, the writing of "1 "s begins at sector clock B. The writing
of data occurs shortly thereafter and continues beyond the distant
but approaching sector clockA, then, the writing of "l"s resumes
and continues until sector clock B.
The read command can become active only at sector clock B time.
Coincidence of the read command and H gate sets a latch that
causes RWA to come true which, in turn, allows read write clocks
to be sent to the controller. Parallel channel data from the two
read amplifiers is present at pins 40 and 42 of Card A16. The
two parallel data streams are strobed into D-type flip-flops and
alternately gated out of these flip-flops into two latches; the outputs of which for~ the data read (3 MHz) interface signal. The
OR gate that combines the two data streams is disabled when the
read inhibit signal is active (0 volts). The data read at interface
output J-10-P is re-inverted at A18-44 to compensate for the
inversion at the interface input (A18-41) .. Thus, if the controller
sends "l"s to the memory to be written, "Otis are written, but
"l"s are ultimately returned to the controller during a subsequent
read command.
The data read signal will have gating spikes between the data bits
because of the way the outputs of the latches are used to form the
data read signal. The channel A data enters its read latch at Cl
leading edge and the latch is reset at C2 leading edge .. The channel

&1

MAGNETIC
MEMORY
SYSTEM

m
B data enters its latch with the leading edge of ST (which is
coincident with the leading edge of C2), and the latch is reset
with 'Cl leading edge. The output of these two read latches
are "ORed" to form the data read. ST, instead of C2, is used
to gate the channel B data into its read latch because the data
in the channel B read flip-flop may change during the last
part of C2 (depending upon the timing of STB),. and,ST
is shorter than C2. Therefore, the setting of the read latch
will be complete before the read flip-flop changes.
Variation in the physical parameters of heads and discs causes
the read signals from different tracks (heads) to be delayed by
slightly different amounts relative to the clock. Strobe selection
is a means whereby the better of two timing signals is selected
to clock (strobe) the amplified signal from the read/write heads
into the read flip-flop. Although each channel has separate
strobe selection logic, only channel A will be described, since
channels A and B are similar.
.
A preamble of several "l"s is recorded immediately preceding
each sector of data. During a read operation, a middle bit of the
preamble is sampled by a timing pulse that is known to be
coincident with signals from "early" heads. If the sample
"catches" the selected preamble bit, it sets a flip-flop that
continuously selects early strobes during the subsequent reading
of sector data. If the sample fails to "catch" the selected preamble bit, the flip-flop is reset and a late strobe is selected.
The five signals used in strobe selection are: Read Data - from
the read amplifier; Window - which defines the time period of a
middle preamble bit; Sample - an "early" pulse that is gated
through by the window to sample the preamble and set the
selection flip-flop; Early Strobe (EST) - a pulse that has an
action edge slightly later than that of sample (the leading edge
of sample is used, but the trailing edge of the selected strobe
is the action edge); Late Strobe (LST) - a pulse that is significantly
later (50 to 150 ns) than EST.
The window (BCD) is present at pin 22 of Card A16. It is at ground
long enough to gate one sample A through the NOR gate at A18-28.
The leading edge of the gated sample will set the D:"type flip-flop
at A18-M2, if the prea:\llble "1" on the data line is present at
A18-25. This will select EST at A18-2 and A18-l3. If the "1"
. is late and misses being sampled, the flip-flop will reset and
LST will be selected at A18-5 and A18-6. The selected strobe is
present atA18-7 and is used (trailing edge) at A16-44 to clock the
data into the read flip-flop at A16-M3. Since the selection flipflop can be set or reset only once per sector (at window time),
the strobe selected will continue to be used throughout the full
sector of data.

mm
SECTION 4
CIRCUIT BOARD SPECIFICATIONS
4.1 INTRODUCTION

Descriptions and specifications of the individual circuit boards
installed in the Magnetic Memory System are included in this
section as an aid to maintenance. The functional description
of the circuit boards containing the integrated circuit logic modules
(DIP) is contained in Section 3, Paragraph 3.4. The circuit board
descriptions are arranged in numerical order. The respective
schematics,assembly drawings, and parts lists for the circuit
boards are provided in Section 5. The following list of circuit
boards and respective part numbers is provided for reference
purposes:
PART NUMBER

CIRCUIT BOARD

11306

Write Amplifier

11640

Delay Circuit

11661

Decode Driver

11791/11874

Clock Generator and Speed Detector

11803

Read Amplifier

11807

Linear Data Preamplifier

11811

Linear Timing Preamplifier

11815

Line Terminator

11818

''X'' Amplifier

MAGNETIC
MEMORY
SYS'TEM

mm
WRITE AMPLIFIER
11306

This module contains two write amplifiers, one buffer amplifier,
and three inverter circuits. The write amplifier consists of three
separate circuit functions: (1) Set/reset diode-gated flip-flop designed to form phase-modulated write data from NRZ computer
data, its complement, and a two-phase clock; (2) a push-pull
current switch, controlled by the flip-flop and used to drive write
currents through magnetic read/write heads; (3) a high-current
transistor switch designed to remove the source voltage from the
write driver to inhibit writing when commanded. The buffer
amplifier may be used to drive the disable input in the highcurrent transistor switch or for other functions that require a
non-inverting amplifier. If write protect switches are used as
part of the design and a protected track-is selected, the write
voltage is removed from the write driver. The three inverter
circuits have no special function and are used wherever inverter
or buffer amplifiers are required.

SPECIFICATIONS

WRITE AMPLIFIER SECTION:
Maximum Operating Frequency: 2.0 MHz
Input Signals:
Data:

TRUE ::.:: +3V min.
FALSE::.:: +lV max.
Input current::.:: -lOrna @ OV
Open circuit voltage::.:: + 3V nom.

C1 Input:

TRUE ::.:: +3V min.
FALSE::.:: +lV max.
Input current::.:: -lOrna @ OV, for
each of two inputs required
Open circuit voltage == +3V nom.

C2' Toggle Input:

Triggers on falling edge of pulse
Minimum Pulse Width == 50 ns
Minimum Amplitude == BV

Enable In put:

TRUE == +6V min.
FALSE == +lV max.
Open circuit voltage: 7V nom.
Input current: -14ma @ OV

MAGNETIC
MEMORY
SYSTEM
11306 (Cont)

Disable Input:

SPECIFICATIONS
(Cont)

TRUE == +18V or open
FALSE = +lV max.
Input current = -lOma @ OV

Output Signals:

Push-pull
Output to head

Rise/Fall Time:

100 ns min.
head load

Propagation Delay:

75 ns

t

=

l50ma max.

into 10 p.H nominal

max.

INVERTER SECTION:
Input Signals:

TRUE = +3V min.
FALSE = +lV max.

Output Signals:

TRUE == 7. 5V ±O. 5V @ 8ma
FALSE == O. 5V max. @ -65ma

Input Current:

-lOma @OV

Rise!F all Time:

15 ns typical

Propagation Delay:

25 ns nominal

BUFFER SECTION:
Input Signals:

TRUE == +3V min.
FALSE == +lV max.

Output Signals:

OFF = + l8V, no load
ON = +lV @ 100ma

Input Current:

-lOma @ OV

Rise!F all Time:

25 ns typical, dependent on load

Propagation Delay:

50 ns

WRITE AMPLIFIER
11306 (Cont)
SPECIFICATIONS
(Cont)

MODULE POWER REQUIREMENTS: + 18V @ 500ma
-12V @ 25ma
CONNECTIONS:
Circuit Ref.
Point
1
2
3
4
5
6
7
8
9
10
11
12
13
14

Circuit Pin Numbers
A
C
1L
4
3
10
23
13
12
15
14
11
5
9
19
16
17

29
30
35
49
39
38
41
40
36
31
34

45
42

ill'III:1111

MAG
NET Ie • • • • • ~
MEMORY
SYSTEM

11m
WRITE AMPLIFIER
11306 (Cont)

DATA

1o---r-.. . .
C1

S

11--[-........

2 ~~"'L.--",

3

C2'
0--+----1
T

R
5

o-oE_N_A;,;;M;I~E;;;;....

O~-r-.......

_ _ _ _..
+18V

so-D.I.SA
..
B.L.E______________OL__/

B

10

11
C

12

""::10--(")

14

13

NOTE: Ref. 13 (pin 16) provides access directly to base of
second inverter for special control applications.

WRITE AMPLIFIER FUNCTIONAL SCHEMATIC

MAG NET IC ::lliill~~}i?
MEMORY
SYSTEM

mID
DELAY CIRCUIT
11640

This module contains one delay line driver circuit, one delay
line, eight tap amplifier circuits, and one inverter Circuit.
The delay circuit is used to derive the read strobe clock from
one phase of the two-phase write clock. The delay line has a
total delay of 250 ns and is tapped every 12.5 ns. Each tap
amplifier may be connected to any tap of the delay line. The
inverter has no special function and is used wherever an
inverter or buffer is required.

SPECIFICA TIONS

DELAY LINE DRIVER CmCUIT:
Maximum Operating Frequency:

5 MHz

Input Signals:

TRUE :;;: +3V min.
FALSE == +lV max.

Input. Current:

-Sma max. @ OV

Minimum Pulse Width:

50 ns

Output Drive Capacity:

Delay line with tap amplifiers

TAP AMPLIFIER:
Maximum Operating Frequency:

5 MHz

Input Signals:

Delay line tap output

Output Signals:

4. 3V ±O. 5V @ Sma
+0.5V max. @ -65ma

Rise/Fall Time:

15 ns max.

Driver / Amplifier Propagation Delay: Delay line setting
+50 ns nominal
INVERTER CmCUIT:
Input Signals:

TRUE
FALSE

Output Signals:

4. 3V ±.O. 5V @ Sma
+0.5V max. @ -65ma

<;:

+3V min.
max.

= +lV

DELAY CIRCUIT
11640 (Cont)

Input Current:

-8ma max. @ OV

SPECIFICATIONS
(Cont)

Rise/Fall Time:

15 ns typical

Propagation Delay:

25 ns

MODULE POWER REQUIREMENTS:

1

+ 18V @ 120ma
-12V @ 12ma

Delay == 250 ns @ 12.5 ns per tap
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

~

...L.{)o-L
~

~
~
~

~.

~
TAP

AMPLIFIERS

INVERTER

MAGNETIC
MEMORY
SY5 TEM\~~I~

tilr.1I\il,1

DECODE DRIVER
11661

This circuit consists of a binary to decimal decoder with a tran~
sistor driver at each of the sixteen outputs. The transistor output is designed to drive the center-tap llyn line ()f a head matrix.
The inputs accept a 4-bit "word" from which the 16 outputs are
decoded so that one is selected at a time. Additional input signals,
usually higher-order bits in a computer "word", are used to select
one of several cards. In this module, some of the necessary connections .are left to connector wirihg to permit variations for
different applications.

SPECIFICA TIONS

DECODE DRIVER:
Input Signals:

(or "I" voltage): 2.5V min. ,
5Vmax.
FALSE (or HO" voltage): OV min. ,
O.5V max.
TRUE

Input loading depends on connection
of input gates. If necessary, input
gates can be wired to present a
maximum of 2 TTL gate loads per
input signal for matrix sizes up to
64 by 64 heads (eight modules).
Output Signals;

Selected: +lV max. @ 250ma max.
Non-selected: +18V

Power Supply:

+18V, pin 24
Logic ground: Pins 1 and 51, 7, 19,
33, and 45

MAG N ETIC 11'1.1 f.··. II• • • • ••
MEMORY
SYSTEM

mm
DECODE DRIVER
11661 (Cont)

A

B
(E)

r-:b

>2__ . .____

I
~_ ~12:....__ _ __Cl....---"

-- -- ,
(A 13 CD)'
- --,

I

(A BCD)

15~

__

A-I

(A BCD)

(A B.Q Q),

....

t-~ /~u -----iii.!

(A~

(A BCD)'

..J __4_ _ _ _--qL./

-

C

(F)
I
I

I
I

I

L_.-________

I 23

CQ):

(A BCD)

6

(A BCD)'
(A 13 CD)'
(A 13 CD)'
(A B ~ D)'
(A BCD)'
{A~ CD)'
(A BCD)'
(A BCD)'
(A BCD)'

~__"

DECODE DRIVER FUNCTIONAL SCHEMATIC

NOTE: Dotted lines show typical connector wiring. Expander
or card select terms E and F must· be grounded if not
used.

MAGNETIC
MEMORY
SYSTEM

mID
II
CLOCK GENERATOR
AND SPEED
DETECTOR
11791 AND 11874

The following general description and specificatiop.s apply tonoth
Clock Generator and Speed Detector Part Numbers 11791 and
11874. Characteristics of the two modules are identical, except
the Part Number 11791 is designed for use in. installations having
a 60 Hz primary input line frequency and the Part Number 11874
is designed for use with a 50 Hz primary input line frequency.
Either module contains three clock shaping circuits, a discspeed detecting circuit, transistor inverter, and two 2-input
NAND gates.
CLOCK GENERATOR. The clock generator section includes
three integrated circuit one-shot multivibrators. Two of these
are set for the correct pulse width for system clocks C1 and C2.
Clock C 1 is generated by one edge of the square wave disc clock;
C2 by the other edge 180 out of phase with Cl. The third oneshot produces a pulse coincident withC2 but not necessarily of
the same width. This pulse is normally used to drive the delay
circuit on another card for optimum strobing of data rea.9.1rom
the disc. Buffer-drivers are used for the output of C1, C1, C2
and C2 to provide adequate drive for distributing these clocks
throughout a system.
0

DISC SPEED DETECTOR. The circuit compares the pulse
spacing from a magnetic pickup with a reference interval from
a one-shot multivibrator. Another one-shot multivibrator is
used to eliminate extra trigger pulses due to aringmg effect of
'the pickup. A third one-shot multivibrator provides consistent
output conditions. The first one-shot multivibrator sets on an
input signal. When it resets, it triggers the second one-shot
multivibrator .. If the disc is at operating speed, the second one,...
shot multivibrator will still be in a set condition when the next
input pulse occurs. The pulse is then gated to trigger the third
one-shot multivibrator. Each of the one-shot multivibrators is
retriggerable at any time, whether or not it is reset. When the
disc is at speed, ef"c1ch input pulse will retrigger the third oneshot multivibrator. Since it has a period longer than the time
between input pulses, the third one-shot multivibrator stays in
a set conditions as long as the pulses are gated to it, or as long
as the disc is at speed. A transistor relay driver stage is at
the output of the detector.
AUXILIARY CIRCUITS. Two TTL 2-input NAND gates are
available on the card for general use as required. In addition,
a discrete component inverter is provided for a speciai application requiring an open-collector output.

MAGN ETIC .· .·. .·.........·.
MEMORY
SYSTEM . . . . ~ . . . .~.

····>·.i

OtlCT1,on>LL

CLOCK GENERATOR
AND SPEED
DETECTOR
11791 AND 11874
(Cont)
SPE CIFICATIONS

CLOCK GENERATOR:
Input (square wave clock):

"0" level = O. 8V max. @ -6.4ma
Ill" level = 2. OV min. @ O.25ma

Driver Outputs:

"0" level = 0.4V max. @ 48ma max.
Ill" level = 2.4V min. J no load

Non-driver Outputs:

"0" level
"1" level

= 0.45V
=

max. @ 8ma max.
2. 4V min. J no load

SPEED DETECTOR:
Input Impedance:

1000 ohms t approximate

Signal Required:

10V p-p, or -5V peak

Output:

Load: 12V, 2500 ohm relay
DSR at speed: 6V nominal
DSR below speed: 18V
Test point at speed: O.5V max.
Test point below speed: 18V

Power Supply Inputs:

+5V, pin 26
+18V, pin 24
Logic ground, pins 1 and 51

AUXILIARY INVERTER:
Input Voltage:

"0" level: 0.8V max. @ lOrna
"1" level: 2V min.

Output:

"0" level: 0.4V max. @ 20ma
"1" level: Open collector , 12V
max. pull-up voltage

AUXILIARY GATES:
Input Voltage:

"0" level: O. 8V max. @ 1.6ma
"1" level: 2V min.

Output:

"a" level:

0.4V max. @ 16ma
"1" level: 2.4V min., no load

MAGNETIC
MEMORY
SYSTEM
CLOCK GENERATOR
AND SPEED
DETECTOR
11791 AND 11874

2

(Cant)

STROBE
C1

CLOCK

C1 DRIVER
C1 DRIVER

CLOCK
GEN

8

C2 DRIVER
C2 DRIVER
C2

CLOCK GENERATOR

24
MAGNETIC
PICKUP

35

~--51

SPEED
DETECTOR

23

- --)

12 VOLT
2500 OHM
RELAY

---

---

TEST POINT

DISC SPEED DETECTOR

_~6_[>o1--_9_-

__:~:Dio-3_2_
DI-

22
_ _1-.9

2_ O
__

AUXILIARY CIRCUITS

M-AGNETIC
MEMORY Section
SYSTEM
READ AMP LIFIER
11803

The read amplifier transforms a lineal'" signal into a switched
logic level signal. The module contains a clock amplifier,
timing amplifier, and two data amplifiers.
DATA AMPLIFIER
The circuit consists of a differential comparator followed by
three inverters in series. Filtered feedback from the first
and second inverters to the non-inverting and inverting inputs,
respectively, compensates for variations in comparator
characteristics to maintain symmetry of the output waveform.
Output from the circuit is through the third inverter which acts
as a buffer to prevent load variations from affecting the feedback signal.
TIMING AMPLIFIER
This amplifier is identical to the data amplifier, except that
a high frequency roll-off capacitor is added across the input
to the comparator to provide additional noise immunity.
CLOCK AMPLIFIER
The comparator in this circuit is followed by a transistor
differential switch, with feedback from each side to the
appropriate comparator input. Each of the complementary
outputs is available through a buffer inverter.

SPECIFICA TIONS

INPUT SIGNAL REQUIREMENTS (ALL THREE TYPES):
Differential Signal:

200mv p-p min.
2.0V p-p max.

F reguency Range:

1 MHz to 2 MHz, phase-modulated

OUTPUT CHARACTERISTICS (TTL INVERTER):
"0" level: 0 to +0. 5V @ 16ma maximum
"1" level: +2.4V minimum
POWER REQUIREMENTS:
+18V, pin 24, 70ma nominal
+5V, pin 26, 200ma nominal
-12V, pin 28, 70ma nominal

mm
READ AMPLIFIER

11803 (Cont)
CLOCK
CLOCK
SHIELD
CLOCK

44
46
48

C>::

TIMING
TIMING
SHIELD
TIMING·

34
36
38

[>31

DATA
DATA
SHIELD
DATA

14
16
18

[>22

DATA

4
DATA
SHIELD
DATA

6
8

[>23

READ AMPLIFIER SYMBOLS

MAGNETIC
MEMORY
5 Y 5 TEM
LINEAR DATA
PREAMPLIFIER
11807



The line terminator card contains appropriate resistors for
terminating twisted pair transmission lines to minimize
reflections. In addition, the card has voltage monitoring circuits which provide a change in output if the voltage falls below
normal on the +18 volt, +5 volt, or -12 volt power supply buss.
The line terminator section has 13 termination resistors with
one end connected to +2.3 volts. The +2.3 volts is derived
from Zener diodes on the card and resistors which are connected to the 5-volt power supply. Other resistors provide
a logic voltage source and terminator for a ready signal
which comes from a switch contact.
POWER CONNECTIONS:
+18 volts: pin 24
+5 volts: pins 32, 46, 48
D. C. O~: pins 1, 51, 3. 4, 15, 16, 25, 39
-12 volts: pins 23, 30. 34, 38
+2.3 volts: pins 2, 6,10. 50 (connected together); pins 14,
18, 42, 45 (connected together)
VOLTAGE MONITOR:
-12 volts: pins 35 and 36
CIRCUIT PIN NUMBERS:
n

~

5, 7, 8, 9, 11, 12, 13, 17, 19, 20, 21, 43, and 44

LINE TERMINATOR
11815 (Cont)
+5V

+2.3V

~>

l

39

40

49

n

'"-,,_ _ _ _ _...... .,.-_ _ _ _--.JI

V

READY SIGNAL SOURCE
AND TERMINATOR

+18V MONITOR
+5V MONITOR
-12V MONITOR

LINE
TERMINATOR

27

31
33

---::.,.

/+2.3V '\

I

\

\
\
LINE
DRIVER

I

"

-TYPICAL LINE TERMINATOR APPLICATION

--

I
/

''X'' AMPLIFIER
MODULE
11818

SPECIFICA TIONS

The module is a small, 1 by 5 inch, circuit board, with discrete
components and solder type connection pOints. It is designed for
mounting directly to the back of a data headplate. Each module
contains four dual-gate, high-current, transistor circuits. Each
dual gate is used for channeling write current and read bias
currents to one ''X'' line pair serving the heads in one row of a
matrix. A common input pair from the write amplifier supplies
write current to anyone of the four gates that is enabled. In the
absence of write current, a pair of resistors in the module supplies
read bias current to anyone of the gates that is enabled. Each of
the gate pairs is controlled by an enable line, normally driven by
one output of a decode driver circuit.
MAX. OUTPUT FREQUENCY:
2 MHz
CONTROL INPUT SIGNAL REQUIRED:
ON: +2V max. -40ma max.
OFF: +18V or open
WRITE CURRENT:
150ma maximum
SWITCHING TIME:
1 ms nominal
MODULE POWER REQUIREMENTS:
+18V @ 20ma. Pin B
Logic ground: Pin A
WRITE

{:

15

16

mID
SECTION 5
MAINTENANCE
5.1 INTRODUCTION

This section includes preventive maintenance instructions,
corrective maintenance, troubleshooting, and component
replacement procedures.
CAUTION

DO NOT run the disc system with the cover removed. Serious damage may result by allowing
unit to operate in a contaminated environment.

5.2 PREVENTIVE
MAINTENANCE
5.2.1 HELIUM
BOTTLE
REPLACEMENT

Preventive maintenance for the Magnetic Memory System
consists of checking the environmental gas system pressure
gauges at regular intervals and replacing the sustaining
helium gas bottle as required.
Under ordinary conditions, the helium bottle which supplies the
sealed enclosure should last approximately six months. The
helium bottle should be replaced before reaching a level of
300 psi, while a small amount of pressure remains in the system. New bottle pressure is approximately 2100 to 2200 psi.
Use highest-grade, oil-free helium with a purity of at least
99.995% (Liquid Carbonic Specification L-U4 Atomic Grade,
or equivalent). It is not necessary to purge the system when
replacing the helium bottle unless the cover has been opened.
To replace the helium bottle while system is in operation, proceed as follows:
CAUTION

In the following steps, take care not to disturb
the setting of the two stage regulator (Figure 3-2)
except as indicated.
1.

Shut off main valve on helium bottle (turn fully

clockwise) .
2. Disconnect either end of tube between low pressure
gauge and enclosure inlet fitting (Figure 3-2).
3. Unfasten enCircling clamp that supports helium
bottle and pull bottle away from unit.
4. Disconnect depleted bottle from regulator and
connect full bottie.
5.

Clamp helium bottle into place and reconnect tube.

6. Open main valve on helium bottle (turn fully
counterclockwise) .

MAG NET I C . . . . .
MEMORY

5 Y 5 TEM

mID

..,AlfA

< •.•.·.•Pal1a •.·
MEMORY
SYSTEM
5.3.1.3

·.V7U····• ·• ·••

AVERAGE PRESSURE SWITCH SETTING

1. Disassemble synchronous switch assembly and place
an ohmmeter between terminals marked A-1 and B-l.
2. Increase pressure from regulator to 1-5/8 psi; contact
opening should occur at 1-5/8 psi pressure. The switch may close
at approximately 1-1/2 psi and cause a short to exist between
terminals A-1 and B-1. Adjust slotted screw marked lIA" clockwise or counterclockwise until a switch setting with closure at
1-5/8 psi is obtained.
5.3.1.4

HIGH PRESSURE SWITCH SETTING

1. Place ohmmeter between terminals A-2and B-2 on
the synchronous switch circuit board.
2.

Increase pressure from regulator to 1-3/4 psi.

3. At pressures less than 1-3/4 psi, a short should
exist between A-2 and B-2. At 1-3/4 psi, an open condition
should exist between A-2 and B-2 of the switch. Adjust slotted
screw marked "H" clockwise or cowlterclockwise until the switch
opens at 1-3/4 psi with increasing pressure.
5.3.1.5

FINAL CHECKS AND PROCEDURES

1. Shut off regulator and release pressure from pressure
system by removing stop plug from the dump valve.
2. Reinstall stop plug and slowly increase pressure from
1-3/4 psi. The microswitches will audibly open and close at
the proper settings indicated on the Marshaltown pressure gauge.

o to

3.

Readjust switches if necessary.

4. Shut off regulator and release pressure from system by
removing stop plug from dump valve.
5. Close valve located on manifold block and remove gauge
from manifold block. Remove all pieces of teflon tape from the
threads of the manifold block.
6; Reconnect all pressure lines taking care to seat them
properly. Do not bend or apply stress to the manifold inlet. Use
a back-up wrench whenever reconnecting at this location.

7.

Replace cover and purge system as previously described.

5.4 TROUBLESHOOTING
5.4 .. 1 LEAK
DETECTION

A Bacharach Model SA63 Electronic Gas Leak Detector, or
equivalent, is recommended for leak detection in the head
actuation pressure system or environmental gas supply system.

5.4.2 TROUBLESHOOTING THE
ENVIRONMENTAL GAS
SUPPLY
SYSTEM

A leak in this system is evidenced by the sustaining gas bottle
being depleted at an excessive rate. The sustaining gas bottle
will last a minimum of 6 months under normal usage. To
troubleshoot the system, proceed as follows:
1. Check the regulator output pressure by observing
the 0 to 3 psi gauge. If the pressure is less than 2.0 psi, the
relief valve may be leaking. If the leak detector confirms this,
shut down system, and allow system temperature to stabilize
to room temperature (3 hours). Manually release pressure
from cover and reset regulator to 1/4 psi flow. If the pressure
is less than 2.0 psi, remove power and proceed to next step
(allow system to stabilize to room temperature).

2. U sing the leak detector, check the baseplate inlet
fitting. The fitting may not be tightened sufficiently, or the
epoxy seal between the fitting and the baseplate may be damaged;
the seal may be damaged when the inlet fitting is tightened improperly. To avoid an inlet fitting leak, wrap one turn of teflon
plumbers tape (one-mil thick) around the male end of the inlet
fitting. Screw in the mating fitting until finger tight, then tighten
with a wrench, taking care not to break the epoxy seal between
the fitting and the baseplate.
3. Check for leaks around the cover using the leak
detector. If any leakage is observed, remove the cover and wipe
the seal and mating surfaces carefully. Reinstall cover as previously described.
5.4.3 TROUBLESHOOTING
THE HEAD
ACTUATION
PRESSURE
SYSTEM

The presence of a leak in the head actuation pressure system is
evidenced by excessive cycling of the pressure pump. Normally,
the pump operates for a few seconds at not less than 10 minute
intervals and has no effect on the environmental system or bottle
depletion. Frequent cycling of the pump may indicate a leak in the
system. Determine if the leak is in the lower pressure system
(components mounted on the baseplate) or in the upper system
(components mounted on or in the drum housing). Once the system
area is isolated, locate and repair the actual leak as follows:
LOWER PRESSURE SYSTEM LEAK ISOLATION. To
5.4.3.1
isolate a leak in the lower pressure system, remove the cover and
apply electrical power only to the lower pressure system so tests
can be performed without the motor running. Perform step-bystep isolation procedure as follows:

1. Disconnect pressure outlet line from upper system
manifold at manifold block. Close the opening in the manifold
block with a dead-end cap. Connect a pressure gauge to manifold block and open valve.

2. Connect a two-lead power jumper cable with spade
lugs to terminals 1 and 3 of terminal board TS2.
3. Connect power jumper cable to a source of 115 VAC
50/60 Hz power. The pump will start and cycle 2 or 3 times.
4. If leak is in lower system, the pump will continue to
cycle with same frequency as it did before cover was removed.
If leak is not in lower system, the pump will not run more than a
few seconds during the normal 10-minute intervals. If the leak
does not appear to be in lower system, remove jumper cable,
reinstall pressure outlet line to upper system, and proceed to
upper pressure system leak isolation. If leak is in lower system,
proceed to step 5.
5. Hold finger over dump valve port. If leak is at dump
valve port, pump will stop when system operating pressure is
attained. Replace dump valve if it is leaking. Retest.
6. To test check valve located between pump and accumulator, pressurize system and disconnect fitting at pump side of
check valve. A drop in pressure may indicate a faulty check
valve. Replace if necessary and retest.
7. If system appears to be leak-free and pump cannot
provide sufficient pressure for operation, replace pump.
8. After leak has been detected and corrected, reconnect
upper pressure system tubing. Ensure that pressure accumulated
during test is dumped from system and any electrical test connections
are removed. Replace cover and purge system.
UPPER PRESSURE SYSTEM L~AK DETECTION. If a:
5.4.3.2
pressure leak cannot be traced to the lower system, pressurize the
upper system as follows:
1. Disconnect pressure line from the manifold block to
the manifold and insert a piece of tubing with a T-connection on
the exposed end of the copper manifold. On one T-end, attach a
Marshaltown 0-3 psi pressure gauge. On the other T-end, connect a purgirig line to a regulator and helium bottle. It is recommended that a shut-off valve be installed between the regulator
and the T-junction to prevent a loss of pressure through the
regulator.

BID
CAUTION

DO NOT allow more than 1· psi in the upper
pressure system.
2. Pressurize upper pressure system to 1 psi, shut off
regulator, and close shut-off valve. The uppe·r pressure system
is now pressurized.
3. Insert .and tighten nylon screws clockwise into back
of valve receptacles to prevent pressure from entering the headplate assembly; this permits a check of diaphram leakage.
Monitor pressure gauge to see if it is holding pressure. If
pressure leak has stopped, the leak is in one of the head plate
assemblies. Do not attempt replacement. Only a Factoryauthorized service man can replace a head plate assembly ..
4. If the system is still leaking, use leak detector to
probe the following areas:
a.

Timing capsules and associated tubing. If the
plastic tubing is cracked, replace the tubing
and epoxy the connection. If the leak is in the
diaphram of the timing capsule, do not attempt
removal. Contact the Factory as soon as possible.

b.

Manifold connections. Epoxy the suspected
location if a leak is detected.

c.

Headplate area.

d.

Unused head plate and timing locations.

5. Remove all nylon screws from valve receptacle and reassemble pressure system. Remove glass cover on the top end
plate and slowly rotate disc assembly to ensure disc moves freely
without binding or scraping. Reinstall glass cover on top end plate
6.. Install cover and purge system. Refer to purging
instructions.
5. 4.4 TROUBLESHOOTING
THE
ELECTRONIC
SYSTEM

Troubleshooting the electronics system is accomplished by
isolating any malfunction to one oI'more of the following
functional areas: Timing, addressing, writing, or reading.
Before troubleshooting the electronics system, verify appropriate
dc power levels are present and status indicator lamps on the
front panel are operating. All timing signals require the disc to
be at proper speed and actuation pressure to be at the proper level
for system operation and troubleshooting . The TOP, sector clock,

MAGNETICi111iflii
MEMORY
SYSTEM
and read/write clock must be furnished to the controller before
it can function properly. The two timing clocks, TOP and sector
clock, are originally multiplexed onto one timing track and share
a common timing preamplifier. They are separated in the electronic card rack by logic circuits and the master clock. The
read/write clock is derived from clocks C1 + Cw, which are
derived from the master clock. The read/write clock is processed
to the controller if the RWA (Read/Write Allow) signal is present.
Table 5-1 lists the troubleshooting procedures for the electronics
system.

MAG NET IC I'~~II<~~~,~i;
MEMORYs
SYSTEM

TABLE 5-1. ELECTRONICS SYSTEM TROUBLESHOOTING PROCEDURE
Timing
Malfunction

Troubleshooting Procedure

NO TOP OR
1.
SECTOR CLOCK

Check timing read amplifier output. If no output is present,
switch to spare timing set. If there is still no input to the read
amplifier, remove the cover and check the timing preamplifiers
for the following:
a.

dc power connections from electronic card rack.

b.

faulty solder connections.
CAUTION

Under no circumstance check continuity of
the timing heads with an ohmmeter. DC
current can erase timing recordings. If
soldering an improper timing head connection, remove 115 V AC plug on soldering
iron from the power outlet prior to soldering.
c.

output continuity to electronic card rack.

2.

If the timing read amplifier output is normal, check the output
of the clock read amplifier following the procedure in sfep 1.

3.

If timing and clock read amplifier outputs are normal, check

the following circuits for correct function as_indicated by the
Functional Block Diagram provided in Section 6:
a.

b.

InterfaceBoard No.1, card location A16:
(1)

Decode flip-flop and shift registers Ml and M4

(2)

NAND gates M7, M8, and M11

Clock Generator, card location A15:
(1)

Clock generators M3, M6, and M9

(2)

NAND gates M5 and M8

TABLE 5-1.

ELECTRONICS SYSTEM TROUBLESHOOTING PROCEDURE (Cont)

Timing
Malfunction

Troubleshooting Procedure
c.

NO TOPOR
SECTOR CLOCK
(Cont)

NO READ/
WRITE CLOCK

1.

(1)

NAND gates M8 and M10

(2)

Flip-flop M5

Check the following circuits:
a.

b.

ADDRESSING

Interface Board No.2, card location A17:

Clock Generator, card location A15:
(1)

Clock generators M6 and M9

(2)

NAND gate M8

Interface Board No.1, card location A16:
(1)

NAND gate M10

(2)

Check the Read Write Allow (RWA) signal. It must
be positive to allow gate M10. If this signal is not
present, check the following~
(a)

Read or write command from the controller

(b)

The following gates on Interface Board No.2,
card location A17: NAND gates M3, M6, M7,
M9, M4, M10

To process information to or from a particular read/write he adin the matrix of all the read/write heads, it is necessary to select
its unique "X" or 'ry" address. Addressing difficulties usually
are easily detected by running a diagnostic test on all tracks. If
parity errors encountered show a common 'ry" line or ''X'' line,
the problem may exist in the addressing section (including the
wiring to the read/write heads). If random, unrelated tracks
indicate parity errors, it is safe to assume that ''X'' selection is
being correctly accomplished. However, shorts can occur in the
heads themselves, causing a multitude of parity errors that show
little relationship to each other. Before troubleshooting, ensure
that all address commands to the decode drivers are present.

MAGNETIC
MEMORY
SYSTEM

TABLE 5-1. ELECTRONICS SYSTEM TROUBLESHOOTING PROCEDURE (Cont)
Timing
Malfunction

Troubleshooting Procedure

ADDRESSING
(Cont)
Parity errors
on tracks
sharing a
common "Y"
line

Parity errors
on successive
tracks sharing
a common ''X''
amplifier

1.

1.

Check the following:
a.

"Y" decode driver input to fry" amplifier

b.

'ry" amplifier driving the particular 'ry" line in question

c.

open wire from 'ry" amplifier to head plate

d.

fry" line short to ground

e.

fry" line to "Y" line short

Check the follOWing:
a. . decode driver output to ''Xt! amplifiers
b.

''X'' amplifier operation

c.

'ry" line to fly" line short

d.

open wire from ''X'' amplifier to headplate

e.

open isolation diodes in headplate (matched pair must be
replaced even if only one is bad)

WRITING

Observation of write current is a valuable tool in determining whether
the write section is functioning correctly.

Write current
malfunction

1.

Examine the write current for the following characteristics:
a.

Amplitude: Should be 125 ±.10 ma through each half of
the write/read head

b.

Symmetry: Relationship in time between the first half and
the second half of oile bit should equal
bit ~ime ±.3%

MAGNETIC
MEMORY
SYSTEM

mm
II

TABLE 5-1. ELECTRONICS SYSTEM TROUBLESHOOTING PROCEDURE (Cont)
Timing
Malfunction

Troubleshooting Procedure
c.

Write current
malfunction
(Cont)

Current
observation

1.

1.

The waveform should start with an expotential rise
which is the charging of the distributed capacitance
encountered between the write buss and ground.
After the distributed capacitance is charged, the
current dips toward zero and then starts a second
exponential rise which is the charging of the inductance. The current increases exponentially until
it reaches a magnitude of 125 ±10 ma, remains at
this level for a short period, and then decreases to
zero. Current then passes through zero in the opposite direction and charges the distributed capacitance on the opposite write buss. After the distributed
capacitance is charged, the current dips toward zero,
starts rising exponentially to 125 ±10 ma, remains
for a short period, then decreases to zero.

Modify an extender board to observe current as follows:
a.

No write
current

Shape:

Remove wires from the following pins:
(1)

pins 11 and 15

C'A"

(2)

pins 36 and 41

("B" write amp)

write amp)

b.

Add an extended length of Wires so that current probe can
encircle either pair, pins 11 and 15 or pins 36 and 41.

c.

Install write amplifier card in extender board socket and
energize system.

d.

Place controller in WRITE mode and select desired track,
using a pattern of all "zeros" or flonest!. Sync oscilloscope
on origin pulse. Check write current for proper characteristics

Check the following pins on card A10: .
a.

pin 3 should have clock Cl

b.

pin 10 should have clock C2

c.

pin 30 should have clock Cl

MAGNETIC
MEMORY
SYSTEM

mm

m

TABLE 5-1.

ELECTRONICS SYSTEM TROUBLESHOOTING PROCEDURE (Cont)

Timing
Malfunction

Troubleshooting Procedure

No write
current (Cont)

2.

d.

pin 35 should have clock C2

e.

pin 13 should be positive

f.

pin 39 should be positive

g.

pin 12 should be ground

h.

pin 38 should be ground

Ensure that ''X'' and 'ty" amplifiers are functioning properly.

-

Write current
1.
not symmetrical

Check that relationship of C 1 to C2 at write amplifier (pins
3 and 10) is 180 0 ±3%

No write current 1.
on tracks rising
from same "Y" 2.
line

Check tty" amplifier in question for operation

No write current 1.
on tracks sharing
2.
a common 'X"
amplifier
3.

Check ''X'' amplifier for operation

Reduced write
current on
tracks indicating a pattern
of ny" lines
(0,2,20,22,40
42, etc.)

1.

Check for fly" line to fly" line shorts

2.

Check for two 'ty" amplifiers being selected at the same time.

1.

Check positive voltage

2.

Check current determining resistors in write amplifier

3.

Check current drivers in write amplifier.

Reduced write
current on
all tracks

Check continuity of

wi~'ing

from 'ty" amplifier to headplate.

Check for open isolation diodes in headplate
Check wiring to head plate .

IIill1rl1

MAGNETIC
MEMORYi
SYSTEM

mm

TABLE 5-1. ELECTRONICS SYSTEM TROUBLESHOOTING PROCEDURE (Cont)
Timing
Malfunction

Troubleshooting Procedure

ADDRESSING
(Cont)
Incorrect data
pattern

READING

. No data

1.

Check data inputs to write amplifier

2.

Check write flip-flop operation (should change state at every
C2 time and change phase with respect to NRZ data).

Data recovered from the read/write heads is low level and must be
amplified intq logic levels before being decoded into NRZ data. Before checking read data, ascertain that the write current is sufficient.
1.

Check the following:

~tput

a.

Write current

b.

Addressing

c.

Output of data preamplifiers (linear)

d.

Output of read amplifiers (logic level)

e.

Input to decode flip-flops (A16, M3):
(1)

phase modulated data

(2)

strobe (C2 delayed)

f.

Output of decode flip-flops

g.

Output of data latches (A16, M9)

h.

Output of data NAND gate (A16, M10)
(1). insure that RI (read inhibit) is not positive during reading

i.

Output of NAND gate (A18, M4)

mm

MAGNETIC
MEMORY
SYSTEM

II
TABLE 5-1. ELECTRONICS SYSTEM TROUBLESHOOTING PROCEDURE (Cont)
~

Timing
Malfunction

Troubleshooting Procedure

READING
(Cont)

''X'' amplifier

No data output
from tracks
sharing a
common ''XI!
amplifier

1.

Check for open read diodes on selected

Intermittant
bits being
picked up or
dropped

1.

Check relationship of inputs to data decode flip...:flops
(A16, M3). The data strobe should be well away from
changes in each bit and not during data changes.

5.5 REPLACEMENT
PROCEDURES
5.5.1 COVER
REMOVAL

To remove cover, proceed as follows:
1. Allow system to cool 3 hours prior to cover removal. Thermal shock may cause damage to the rotating
assembly.
2. Loosen 12 socket-head cap screws in succession until
screws are free of restraint from expanding cover seal, then
remove screws.
3. Before removing cover, ensure cover is free and will
not pull the baseplate seal out of its recess.
4. Slowly lift up cover; do not tilt cover, as timing capsules and harnesses may be damaged.
5. When reinstalling cover, align arrow on cover with the
matching arrow on the baseplate assembly. The cover must be
reinstalled in the same manner as it was removed. Ensure the
cover seal is free of obstructions (wire, solder splashes, etc.),
as a helium leak may result if a proper seal is not obtained between the cover and baseplate seal.

5.5.2 DATA HEADPLATE
ASSEMBLY
REPLACEMENT

Replacement of the data headplate assembly may be performed
only by a Factory-authorized field representative.
CAUTION

No adjustments can be performed on the
data headplate assembly. DO NOT attempt
to adjust or replace this assembly or serious
damage to the equipment will result.
5.5.3 HEADPLATE
DIODES

Replacement of a defective headplate diode on the diode board
may be performed only by a Factory-authorized field representative.

5.5.4 DUMP VALVE
REPLACEMENT

The dump valve may be replaced as follows:
1.

Disconnect pump from accumulator.

2. Disconnect pressure line between accumulator and
manifold block at manifold end.

MAGNETICII1
MEMORY
11
SYSTEM

ElID

3. Disconnect pressure line between accumulator ,and
dump valve at accumulator junction.
4.

Remove two screws holding accumulator to baseplate.

5.

Remove accumulator.

6. Remove wires to dump valve from terminal strip TS2,
terminals 3 and 4.
7.

Remove two holding screws to dump valve.

8.

Replace dump valve.
CAUTION

Do not move T-fitting that is epoxied
to the accumulator.
9. When reconnecting pressure lines, tighten lines finger
tight plus 1/4 turn. Take care in connecting pump to the accumulator to prevent damage to the tubing. Tighten tubing
finger tight plus 1/8 of a turn.
The pressure relief valve located in the baseplate is removed
through the lower surface of the baseplate using a socket wrench
and extender. When installing new valve, wrap two turns of
teflon plumbers tape (one-mil thick) around threads to ensure a
proper seal. Tighten securely during installation.

5.5.5

5.5.6 HEAD

ACTUATION
PRESSURE
PUMP
REPLACEMENT

To replace pressure pump, proceed as follows:
1.

Remove two screws attaching pump to the baseplate.

2. The unit has a check valve following the pump. Disconnect
tubing from check valve. DO NOT break the epoxy seal around
accumulator inlet fitting. Remove the spring installed in the pump
outlet line.
3. Disconnect two white pump electrical leads at terminal.
board TS2, terminals 1 and 2 .
4.

Remove the pump.

5. . Install replacement in reverse sequence of this procedure.

MAGN ETIC ··sactlnn 6

mm
6.2 INDEX

The following reference drawings and parts lists are provided
in this section in the order listed.
Drawing No.

Title

13834

Drum Wiring and X-Y Harness List (9 sheets)

13775

Card Rack Wire List (27 sheets)

13770/13870

Memory System Installation Assembly
(3 sheets)

13777/13882

Functional Block Diagram (2 sheets)

13779

Timing Diagram (4 sheets)

13774

Card Location Diagram

14011

Headplate Organization

13833/13884

Relay Mounting Board Assembly (2 sheets)

11795

Parts List, Interface No. 1

11796/11797

Interface No. It Pictorial/Schematic

11799

Parts List, Interface No. 2

11800/11801

Interface No.2, Pictorial/Schematic

11791

Parts List, Clock Generator (60 Hz)

11874

Parts List, Clock Generator (50 Hz)

11792/11793

Clock Generator, Pictorial/Schematic

11803

Parts List, Read Amplifier

11804/11805

Read Amplifier, Pictorial/Schematic

11306

Parts List, Write Amplifier (2 sheets)

11326/11336

Write Amplifier, Pictorial/Schematic

11661

Parts List, Decode Driver (2 sheets)

11662/11663

Decode Driver, Pictorial/Schematic

MAGNETIC

MEMORY
SYSTEM

Drawing No. (Cont)

Title (Cont)

11640

Parts List, Delay Circuit

11645

Schematic, Delay Circuit

11650

Pictorial, Delay Circuit

11815

Parts List, Line Terminator

11816/11817

Line Terminator, Pictorial/Schematic

11680

Parts List, Head Substitution Terminal
Board

11674/11679
11695

Head Substitution Terminal Board, Pictorial/
Schematic
Parts List, Synchronous Switch

11697/11698

Synchronous Switch, Pictorial/Schematic

11811

Parts List, Linear Timing Preamplifier
(2 sheets)

11812/11813

Linear Timing Preamplifier, Pictorial/Schematic

11807

Parts List, Linear Preamplifier (2 sheets)

11726/11727

Linear Preamplifier, Pictorial/Schematic

11818

Parts List, 'XH Amplifier

11819/11820

'fJ{Y!

-

Amplifier, Pictorial/Schematic

Terminal

From

To

Function

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17

T1- (R)
J8-R
T 1- (W)
T1-(B)
J12-G
J12-F
T3-(W)
T3- (B)
J8-S
T3- (R)

T1-Shield
PA2-2

Logic Ground
+18 volts DC
Preamp Input A
Preamp Input A
Head Select Input A
Head Select Input B
Preamp Input B
Preamp Input B
12 volts DC
Logic Ground
Logic Ground
Logic Ground
Logic Ground
Logic Ground
Clock Output
Shield Termination
Return for Clock Output

PA2-5
PA2-6
PA2-9
T3-Shield

J8-A (W)
J8-C (S)
J8-B (B)

NOTE:

**

For balance of drum wiring, refer
to drawing 14011.

**Shielded pair

Preamp #1
() I (0 I ,.

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C

0

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I ..

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1

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13834-

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Fl."om

TZ (R)
PAl-2
T2 (W)

1
2
3
4

T2 (B)

5

PA1-S
PA1-6

6
1

To

T2 (Shield)
PA3-2

T4-(W)
T4-(B)

8
9.

PAl-9
T4-(R)

10

PA3-5
T4-Shield

11
12
13
14

15
16
17

J8-D (W)
Ja-F (5)
J8-E (B)

J

1\11'"

Logic Ground
t18 volts DC
Preamp Input A
I
IPreamp Input .A I
:Head Select Input A
Head Select Input B
Preamp Input B
Preamp Input B
12 Volts D. C,
Logic Ground
Logic Ground
Logic Ground
Logic Ground
Logic Ground
Timing Ou tpu t
Shield Termination
Return for Timing Output

Preamp #2
DICOIl""L
r~

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P MEN T

DRUM WIRE LIST

~

1

owa

;;834 . JY_

COII"ORATION

Page

2

,

Terminal

From

1
2

Preamp 2-2

To
XAL1-A**
PA4-2
XAL1-2(W)
XAL1-1 (B)
PA4-5
XAL2-A**

Logic Ground
+18 volts DC
Read Bus (A)
*** Read Bus (A)
-12 volts DC
Logic Ground
Data Preamp Out
JS-G(W)U
J8-J(S)
*
Shield Termination
J8-H(b)
Return for Data (A)

-- 0

3

4
P.A. 2-9

5

Function

6

7

8
9

,

,

i

,
1

!

,

!

i
,
!

,

*Twisted Pair, Shielded
**22 ga Blk.
***Blk. & wht. twisted pair
Pre3.n1,p Ii 3
DIG 1 ... A L

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J

13834

3

Logic Ground
+18 volts DC
Read Bus (B)
XAU1-2
*** Read Bus (B)
XAU1-1 (B)
-12 volts DC
Logic Ground
XAU2-A **
Data (B) Preamp Out
J8-K (W
Shield Termination
J8-M (S) *
Return for Data (B)
J8-L (b)
XAU1-A

1
2
3
4
5
6
7
8

Function

To

From

Terminal

Preamp 3-2

**

(WD

Preamp 3-5

U

9

*Twisted Pair, Shielded
**22 ga. Blk.
'k**Blk. & wht. twisted pair

I

Preamp #4
DIGITAL

~.

OEVEL..OPM'EN"r
CORPOAATION

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DRUM WIRE LIST

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13834
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Page

4

Mi\.l~l'

the follov.. i:lg connections as required for the head
bstalled. D;;isy-chain by the shortest route.

platC'~~that

are

REFERENCE ONLY
Wi:dng is included in "X II amp and pre-amp wiring.

X Amplifier
Read PellS Connections

Preamp - Data. (A)
PA 3-3 - PA 3-4 -

- XALl-2 - - - - XAL2-2 (W)].
- XA L 1 - 1 - - - - XA L 2 - 1 (B)

*

Preamp - Data (B)
PA4-3 PA4-4 -

--

1

- XAU 1-2 - - - - XAU2-2 (W)
- XAU1-1 - - - - XAU2 .. 1 ~B) ..,j

....

:;C

):: Blk and Wht. Twisted Pair

DIGITAL.

Tc

Dr::V£LOPMEN'f
CORPORATIOp.!

X Amplifier Read En:"'.n.1

DRUM ,\VIRE LIST

1

13834
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5

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I·
I

To

I

IA

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F
G
H
I

J
K
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Preamp
Preamp
Preamp
Preamp
Preamp
Preamp
Preamp
Preamp
Preamp
Preamp
Preamp
Preamp

(WO
(WJ
(W]
(W]

1-15
1-17(B)
1-16(S)
2-15
2-17(B)
2-16(S)
3-7
3-9 (B)
3-8 (S)
4-7
4-9 (B)
4-8 (S)

(

Function

*
(Shield-black wire)
*
(Shield-black wire)
*
(Shield-black wire)
*
(Shield-balck wire)

I

Clock Preamp Out
Return for Clock
Shield Termination
Timing Preamp Out
Return for ~iming
Shield Termination
Data (A) Preamp Out
Return for Data (A)
Shield Termination
Data (B) Preamp Out
Return for Data (B)
Shield termination

i

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.I

P
R

S
T
U
V
tv
X

:y
Z

a
b

Preamp 1-2
Preamp 1-9
Logic Ground
Logic Ground
Logic Ground
Logic Ground
Logic Ground
Logic Ground
Logic Ground
Logic Ground
Logic Ground
Logic Ground

+18 volts DC
-12 volts DC
(B)]
(B)
(B)
**Group 1
eB)
(B)
(B)]
(B)
**Group 2
(B)
(B)
(B)

*Twisted Pair, shielded
**22 ga black stranded wire. Crimp and solder each group
into a ring terminal and tie to ground lug on motor housing.
Route below all other disc wiring. Wire length to be
10-1:2 inches.

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I

_L ___ ,

JS P5
MOTOR COM MOW ~

MAIN WIND1NG

,S\-\

D, 0

C

**
AU"!.. WINO\t-..lG

:DUMP VALVE.

~

E

F

TS~'Z. }

iSt-'Z.

C

{

~

•

RUN

:: ?=

•

S'rA$2T

r-

E

-f- -~

IS VAC

1

T

wo ' C •!'lei

:

I

i ~: ....
L ___

J

I

K3

CAPACiTOR
CUTOUT

RELAY ~F

NOTES:
1)
2)
3}

*

See MDL for Capacitor Values,
Use 16 Ga. white Teflon, Strandecl wire.
** Omit this Capacitor on 1 & 2 Disc Units.

r------- -

-------1

CONNECTION OF
MOTOR CAPACITORS
: C i ....;i~l_

DRUM WIRING

13834Page

9

Pa••
1.
Z
3

Rev

Pa.e

B

ZI

I"J

22

~.

.

Rev

5

6
7

D

8

I:

23
24·
25
_26_
27

/1,

t3

12
F'

!l
10
.11
12
13
14
15
16
17
18
19

.I:i
it
Ii
~

~
~
~

F

10

.....

ALTERATION

By

j¥t

Revisions m.ade to Page 1,7,8, 13, 15, 17, 18 and 24.

A

~f+.

B

Updated logic changes and corrected errors

C

Page 27. Pin DD added connection from. J2-H. AC Failure
Warning
Per ECR #766

D

Pin 23 Function should be T6 input is (T6)'
PER ECR *800
Chg'd. .heets 15, 18,20 It 27 per ECR 819

<' ..... ~

ctf:;'

······a; /
-~,'I>.

~vj

I3c k

.'
I Y?~9
I (-d (,,')

;;,

1/t'f~.5'

X'Z//o..9
.ti~ 5>

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11)1/6)

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'

Of

,

-'';.''';''0

OrVIL

' , . ... ~ ...

T

C

...

.•.. ..-

•

····1..

.... ...

(t

1.

...

..

'l

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Pa•• lof 27

Ittt

l

~CI'e

Je.::\(c:,,.·. 2,·4 9

D,c.,' ...

RACK WIRE LIST

-/ Ie,

{Ii

(page 8)

-*-C

:0....
>-·l-~;.i~

, /(,;/~, .. <'.
....t'~ 1IL*"J,.... ."'!
•• f i /opr/'l
....
~::/~ .\ { l

III" /01
11../9/1;t:('
I ~ If-'. J L,

~VJ

PER ECR 740

F

II/rift:, ("

~V)
~iL

Deleted wire P8-N to A5-24

E

Date

,

•

... ,

l-' -..
c.

IH

REV

~/J'

G

Changed sheets 3, 17 and 18 per ECR 1409

H

Page 15 changed function column on lines 18, 30, 25 and 12
Per ECR 1311
5·
(..9
Incorporated ECN 719

DATE

CHECKED

PC

"c..

r;-,"_~_j)

REVISION SHEET

DATE

BY

ALTERATION

'2.., -

I~VJ

:sl?J/~~

C-ac/.e ('/1/('9

nvJ

DIGITAL.

~ I"!:>/

,q

~

DEVEL.OPM~NT

CORPORATION
APPROVED

APPROVED

Page la

'0''''

No. 026

NOTES:

1.

See DDC 13775 Sheet 1, pages 24 through 27, for
Connector Wiring.

2.

Socket to socket wiring to be No. 24 gao Kynar solid wire.

3.

Install DDC #12888-13 Power Bus between Pins 24 and 28 of
Connectors Al thru Al3.

4.

Install DDC #14023-4 Power Bu. on Pin 26 of Connectors A1S
thru A18.

DIGITAL ~
CEV!l:LOPMENT
COJt .. OJtATION

TIT~.

IIMT _

RACK WIRING

I

Dwe. flO.

It.y

13775
Page 2

/I

Terminal
I
Z
3
4

From

P8_H'(Bl

_5
P8-G

fW)

Read Data "A

"'\

PR_.T {S\

6
7
8
9
10

Function
DC Common

To

>

*

'

Input

~"Ml..1

.'

~

Read Data "A" Inout

'\

Read Data "B" Input

II
12

13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
3Z

P8_ l i B '

)

P8 .. MIS)

*

I

~hl .. l~

PS .. K (W\ )

**
**

Read Data "B" Input

A16-40
A16-42

Data "B" Output
Data "A' Output
+IS VDC

***
***

Slf11!fII!VA
A 1~_~2

+5 VDC

A15-8
Alb-30

***

Clock Data Output
ClocY-Uata Uutput
Tlmmg Data Output

'.

Tlmmg Read Input

-12

Sleeve

***

~3

I

34
35
jb
37
38
39
40

'DR

n

'DR _ li'

,rW\

>*

I~\

P8-E (B\

vue

~'h~ .. lA

Tlmm~eaaTnput

)

41
41.

43
44

Clock Read Input

PR_A IW\ '\

4_~

4b
47

P8-C (S1

4~

P8~B(B)

) *

Shield

I

Clock Read Input

)

49
50
51

* Shielded twisted pair 24 gao
** INSULATE ENTIRE PIN TO BUS BAR

DC Common
':":":'Route outside pin area

WITH SHRINK TU BING

*** B

& W Twisted Pair, Black to DC Common

DIGITAL
~
DEVIELO .. MIINT
CO"~O"ATION

T'TLR

WIRE LIST - CARD RACK

Location: Al
Card Type:
Read Amp}.
IaMT _ Dwe 100.
13775
1

!tRY

~

Page 3
.,0 • • Nt)

r ••

Terminal

Fron1

To

Function

1
2
3
4

5

6
7
8
9
10

11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35

.,-

jb

37
38
39
40
41

4l
43
44
45
46
47
. 4b

49
50
51

DIGITAL.
~
DEVELOPMENT
CO",.Ol'tATION

Location: A2
Card Type:
No Card Required

"T,-.
WIRE LIST -

.HT._

CARD RACK

1

ow •.

NO.

,.. v

13775

Page

4

Terminal
1

From

To

Function

2

3
4

5

6
_7__,~"

8

9-~"'~'

10
II
12
13

14
15

16
17

18
19
20
21

22
23
24
25
26
27
28
29
JO
31
32

i

-

;

--

~"j

7

I

33"
~

I

35
Jb
37
38
39
40

~

.

41

.

42

43
44

--,

45
46

,-

4"'(4(:$

49

""' ... _;.=

5()

51
I

Ih'GITAL "*

DEVELOPMENT
CO".-O"ATIOI'4

Location: A3
Card Type:
No Card Required
TITLE

WIRE LIST -

[aHT,_

-1

owe,

HO,

~
IIKV

13775
Page 5

.

-------.-----.------_. -1
.-~.

.-...

...

-.--.-----.

- -'-¥'-.• ".-.__._.- - - - - - "---_._.

__

~'-,---

...

--~

I

.. - . - - - - -.. '!'

~----,,'- .. -~----~.---".--.....-.- -~---------.---'.'--:.

__
.__ ._--_ _---------T
._____._ . _._... __ ._,_._._,____________._____._____J

-_.- _._- _.-

..

.

j

..

t

- -___ i

!

---'-'!,
.,

--

I

.' ..-'-'- -.. __...___ ._____ -____,______.___ .__.____ ._.________________J

.---_ ...

~

, J

_. __ _ -_._-_ _-_._--_._-_._---------_._----_.----------------..

.•.

..

)

----- ------- - ..------ -------.,.. _., •.......•..

__.----_._---

I

--------- -1
i

',!

,
,______ J

--.-----.-------"~

, • ~ _ _ _ _ _ _ _ _ _ _ _ o_......4

'.

~-

<.~.-----------.-

i

;}

··-1,
._----_.--1

~

------'i1,

',"""'--- ---"-'-'."---..

'!

, 11

-

-.,.",,,.,,~, ~-"' •. " .. ~. T.d ']':'P·:'·
_N~t
JTA1' Address Input
Y17 Outnut

13

14
15
16
17
18
19
20
21
22
23 0
24
25
26
27 ~I
28
29
30
31
32
33
34
35
:>6
37

A6-17
P6-d

t
P6-h
P6-r

P8-R

38

*
**

Y28 Output

*

+18 VDC

Y24 Output
Y 16 Ou~ut

.,P8-S

4.

-lZ V v(';

*

tTZ)
T 1 Address
tl 1)

Ab-30
~

.1:-'0-1

0
.l:"'b-a
.l:"'b-e
.l:"'b-n

4,

39 •
40
41
42
43
44
45
46
47

Y20 Output

(Tal' Address Input

*
*
*
*

Input

U

Y l.5 Uutput
Y.51 Uutput
Y U uutput
x J,'1 uutput
ll. lo} .
(TZ)

'1'2 Address Input

Ao-4U

('11)

4
.l:"'b-J

••

.l:"'b-b
.l:"'b-l
.l:"'b-P

41:S

49
50

••

51

*

*
*
*
*

Y2Z Uutput
uutput
x lob uutput
X HS uutput

Y jU

DC Common

,

24 Ga White Stranded Wire

DIGITAL
~
DEVELOPMENT
CO""Ol'tATION

Location: A5
Card Type:
Decode Driver

.HT_

TITLR

WIRE LIST -

CARD RACK

1

0
,,,y

DW •. MO.

13775
Page 7

D

1

Terminal
1
.~
2
3
14
'0

From

Function

To

••

~

6
7
8
9
10

DC ComTnnn
AI3-11

T A Annl"IF'RR T... n"t

•

4~

11
12

P6-CC

*

P6-u
P6-v
A5-10
P6-GG

*
>I<

*

0

13
0
14
15
16
17 4~
18
19
U
20
21
22
23 ..
24
25
26
27 .~
28
29

4'

~O

A13-12
P6-DD
A5-17
P6-v
P6-z
P6-HH

j

••

A13-17

A5-30
P6-AA

4.
P6-s
P6-w
P6-EE

Jb

*
*
*
*

••

lTO}'
TO Address Innllt
Y4 Outout
(TO)'
Yl20utout.
Y8outout
YO Outout

-12 VDC
(T2)'
T 1 Address Inout
(T 1)'
Y7 Outout
Y 15 OutJ;)ut
YllOutout
Y3 Output
(T2r'
(T2)'
T2 Address Innut
(T 1)'

~t

AI3-1'}

YI:3 Outnut
Y9 Outout
(TA)'
YI Outnut

T6 Address Innllt
+18 VDC

A5-3

31 0
32
33
34
35

37
38
39
40
41 ••

*
*
*
*

lTA\'
YS Olltnnt

A5-40

4~

43

,.,

44

4-5
40
4"
. 4CS

49
50
51

,

P6-BB

*

Y6 Output

P6-t
P6-x
P6-FF

*
*
*

Y14 Outout
YI00utout
YZ Output

•

4

*
DIGITAL

DC Common

Location: A6
Card Type:
Decode Driver

24 Ga White Stranded Wire

~

DEVELOPMENT
CO .... O .. ATION

TIT!.!!

aNT._

WIRE LIST -

CARD RACK

1

DW •. MO.

"IV

13775
Page

-

8

E

_ _ ... _

"_, •. _ _ ., • •

---~-~r.

i

~_,

___

~h-.

_ _\<-

- -... -~--~:--:;~~

, , t ~":' •. : 1

. - - - ' .. ' __ """''''-k _ _ '''_'''·

r'u:-~~'~~' ~,-.,.."...

---- --,---

.

------- ---"--- ----------.---"------- .. ------.-

i

,~~o-~-'-l

··---·---1

-.---.-----..".--.-----------....--.-.. ----- .-_.. -- ----. -l

I

--------------"--.---"-.-.

---------------------_._--_~tL.

---- --------. ----i
-~'-'I

---_. ---_......

-------------.----- ------~l,

__ ._.___ .________________ ._____

._---------._---_._--

)

.\
I
1

c

~~~~----~~-~.~~-~-----:-----=~---~---.=~-------.~~--.---'-~---------~-~~----~~~~~~~~~~~~~~~=~~=--~=~------------~.!

-,-,

"'"."----,,,.~,,-.~---

.~

.--'.-

-------------_.._--_.

1 :.

I

l-z;---------------~---.-.----

1 .-,
"

I

1 J'~

--:Y--

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-fe)-

.--------~,

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---_._._------,,-----.---_.
__ ._------------------------~I
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----_._---------._---',
.----------- ---------------------~(
2J
-)

,,<,;;...

l-. ;f

...

i.

~)

_--_._-_._------------,..------------

----------'.1
rI

--------------------,1

_ _ _ _ _ _ _ _ _ _ _ __

---_._----

2... ~/

----------------------------------------------------------------------1t

2~)

------------------,I
--------,.1
________

!

-::r:,.;-------···...------------.. -,-... --,...

------.----~,-

------------------------------------~.I

. --.--.

-:7"";:;----.---- .... -~-..--- --.•.. ' . - - - - - . - - - - - - - - - - - - - - - - - -

-

~_=_.-=--,:::_-_=_-._~=.-_--_:_:_=_-.~-.-----.-.-=-~::~::.-=--.---.----~-------------

..) i __..

fl

--.-.-r-.. ._--......"---.--------.
_.-,"'",..-', _ _ _ ' _ , _ " .

,~

.

_ _ ~._, _ _ _ _ _ _ _ _ _ _ .....~ __

"·~·~,··

_ _ _ _ _ _ _ _ _ _ _4_ __

',: 4.-~

--------~,-,---,----"---,--------

"~

3

---.---..~-.- •.-----.-----~-.---..
--" "--'''-----'--'

--~-- ...

j

~

-.---.-.------'------".,-

---------- ----------".,,--_._----

'

-

---.
J

----._-----_.•,,---.. .._._,,------_._---------------_._-------------...,
. --------------.-.-----.--.-.-----------,---..--·-----·-------------------------1
.1
__

---..()~ ..
1
)

------~-

:, (:

~i1------------------.----------------------.----------------I

Terminal

From

To

Function

1
2
3
4
5
6
7
8
9
10
11

i2
13
14
15

16
17
18

19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
jb

37
38
39
40

41
4~

43
44
45
4b
41
4ts

,

49
50
51

Location: AS
Card Type:
No card required
DIGITAL ~
DEVELOPMENT
CO""O"ATION

. TITL.

WIRE LIST -

.HT._

CARD RACK

1

DW •. MO.

"a"

13775
Page 10

Terminal

From

Function

To

It.}

n r.

2 C)
3
4 C)

s
6
7
8
9
10

A13-20

r.n1"n1"nnn

T3 In'Ont '
~

~

t~

P6-U
~

\

11
17. ~~
13 ~~

.

lie

XliA 011t'011t
X5R C'XIB Out'Out
In'Out (T.3\'
X fA Out'011t

P6-K

lie

P6-P

lie

P6.V

lie

P6-V

lie

P6·L

lie

P6-R

'Ph. 7.

lie
lie

P6-F

lie

n

14
15
16
17
U
18
19 ~
20
21
22
23 ~
24
25
26
27 It
28
29 I~
30
31
41
32
33 tl
34
35

A13-21

•

P6-C

lie

T4 Innllt
X4A Outtmt
Inout tT4:)'
X4B Outout
XO'R

("l..fo ........ fo

ynA n"t-a......"t

.L 1 A

vnr.

.12. vnc

-,
..III

. A13.43

Tn ......"t Tr:;

36

37
38
0
39
40 0
41
n
4Z
43
44
45 t)
46
47

'Ph_~

lie

'Ph.J.:!'

lie

Y7'R nnt......"t

P6-M

Ph-W

**

Y~'R

Ph-T

lie

XhA 011tn11t

Pb-J
Pb":N
P6-X

**

X6B Outnut
XZB Outout
XZA Outout

Y7 A n" t ......" t

'.

Y~A

n"t ......"t
n11t'Ont

•

. 4tj

49
50
51 4.

lie

DC Common

* 24 Ga White Stranded Wire
DIGITAL
~
DEVELOPMENT
CO.-rPOI'tATION

Location:
A9
Card Type:
Decode Driver

"'T\.I

WIRE LIST -

,

_NT.NO

CARD RACK

1

DW. . . .O.

13775
Page

11

4
..."

&

Terminal
1
?
....

From

Function
DC Common

To

0

0

3

Cl
"A" Data Input
(Write Enable)' Input

A17-6
A17-Z9

4

--.5

b
7

8
9 D

0

J0
11

P6-A

17.

13

)lC

(W 1)

0

Write Enable
(CZl'
Write Amp1 "A" Outout
W rite Inhibit

~)

14

0

l~

*

16
17
16
19
20
21
22
23
24
25
26
27
28
29

P3-A

* (W 3)

P6-B
(B1)
A13-Z7

Write Amp1 "A" Outout
+V Monitor
Write Inhibit

A13- 33

- V .Monitor

A17-5
P3-J(Red 16 !la.)

"A" Data)' Inout
+18 VDC
,'-

~O

P3-L(Wht. 16 !la.)
A17-8

-12 VDC
"B" Data Input
Cl

A15-36

C2

f)

31
32
33
34
35

0

(r.? \ I
(r.? \'

Q

P6-D

5b

37
38
39 C)
40 0

)

P3-B

P6-E

* (B2)

Write Amo1 "B" Outout
r.l
tr.1\1

A15-38

4b

Write Amp1 "B" Outout
Write Inhibit

0

43
44
45

(W2)

* (B3)

41
-:q:z

)lC

47
4/j

49
50
51

4'~

A17-7

"B" (Data)' Inout

P3-MtB1k 16 !laJ

DC Common

* Twisted pair

#24 gao
Pair by Number

"i%

DIGITAL.
DEVEL.OPMENT

CO"~O"ATION

B&W

TITLI

WIRE LIST - CARD RACK

Location: AlO
Card Type:
Write Amo1.
jaHTNO

1

DW •. NO.

..IV

13775
Page

12

13

--

"

"

.. -

t.

~.

'.-----"-

.---~

~

-'

...

'l

,~

-......, ...

~'

.-.----..

~-~.---"-.-"--

~------",~-----.--

..

---.....,---.,....

-.-----------~

.. ,._.-

,

...

____,_______________________,____ D _C;,Common_ -----:L-------~l
_-. ~ _'" _-______.Nor E
_______________1'. ~It Ampli Ii ~ r .In pu t ----\----------l

-- ....1 --- --_._--

___}
_--'-_{:-_-='-,_-_-_. --A18_~·3_4-.-~==_-~-._-_-_---~-=--=--=--=--=--=--=--=--=--=--=--=--=-__~ S~~ pIe" A ~,~:~~~-~==~=--.-----------~

i

___ .___ .AlS.Z9 ____.. _____. S a t n p l e ' 'IIB"_' .. __ .______._____ !
-.J-:_--""_""_"'_--""_.....__NOTE_
_ _____ .Tap.Axnplifie r Input--------1
._Jo_~.".._~.~"!..-.."'_.NOTE __
_ _____Tao_Axnolilier Input
.--1
__ ,. ____ Early-Stro'be.._"A'_' _________ ~
AI8_- ~ _________________Late__t)tr_Q_1:>o~_~~"
______i

__3_______ ,AlS"'}-l

9

,_____ ._______._.. ____. .

-.1~S2______

~~-,---:-. ~-_~--:--~-_-_-~9_~E~·---------f:-r-l-=_-_---=~~~....Al-

-15

_____________~T~p-ArnpljJi;r~DpU!

5_"!.z=---------.__--='-_-_-_-

ir_-_~·~~-_-_~-_-_-_~·-~'-'_'-_'..~ c

•

iP~~lY_~~io1i~!----

1,

=-=-==j

·_-_-_--·_·--·-·-~-==--==---·---··----c~~1rnfi:=-i:;-~i~I

____

-[~

_ _ _ _ ~elay_.~~~eHT~j> _No!_l}.

~~~·---------------_=~---_----~_-_-_-_-~~~~~~~~________:g:i~~_t:~_~-~~~=~~~-tA

1

I ~2j""- - - - - - - - - - - - ------------~~i~y-·tt~~-fi-~-~~:_r~
I

·f

-------------~----~-··----+I~r~bC--·-.. E~.-.-

2,4

- - - ._--

,,1
-1-;

.----.~.-.-.

.W

' .1::::.5_ _ _ . - - - - - - - - - - - - - - - - - - - - - - - - - . - -.•'I
II

~~
~B

·b·elay-1~lne·-Tap-No-:--l1
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7
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9
10
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14
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16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35

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38
39
40
41
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44
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10
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13
14
15
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23
24
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-~~--.~------.-.

-~~,.>-.--

"-.'

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....--

--~----~-.-

~---

l

* Twisted Pair Z4 ga B
---~--

~~
(_

_._._..

Ire·v ' /
'. ~J

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P

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P

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A

r

i

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& W

l-~-::;~·-·~-

T

II

N

;

.. _.- . --.. -. ..,.-----..------..". - .

jPT06A-14-1ZP (SR1------ .
i Connector P3

--.~-- --·~·r~.;-;-~. '-~

WIRE LIST - CARD RACK

__

-

-----r--~~

L.~-i. 137!_~__ ._._.______ .J. ~j
!
l

I

Page Z4

-

From .

To

Func Hon

I--~----------------------------------~-----------------------------A
AI0-11....
(W)
Write Amp "AI' Output
B
A 10-15 /,r (B)
Write Amp "A" Output
C
A9-24
*>,~
+18 VDC
· D
A 10- 3h ')
(W)
Write Am~ "B" Output
· E
A 10-41 /
. (B)
Write Amp "B" Output
F
, A9-24.
**
+18 VDC

----

G

·H
·J
K

A9-34
A 9-46

r

A9-8

A -47
A9-9

"

X7B uutput
X6B OUJ:12ut
X5B Output
X2B Out t
XIB Output

S
T
U
V
W
X
.y
Z

A9-32
X7A Output
A9-44
X6A Outgut
A9-6
X5A Output
A9-16
X4A OutQut
A9-36
X3A Output
A9-48
X2A Output
A9-11
X1A Output
A 9-21
XOA OutRut
a
A5-34
Y310utput
b
A5-46
Y 30 Output
c
AS-8
\. **
Y29 Output
·d
A5-18
/
Y28 Ou!E.ut
e
A5- 35
Y27 Output
£
A5-47
Y26 Output
g
A5-9:
Y25 Output
h
A5-20
Y24 Output
1
A5-32
Y23 Output
j
A5-44
Y22 OU!'Rut
k
A5- 6
Y21 Output
m
A5-16
Y20 Ou!]?ut
n
A5- 36
Y 19 Output
.P
A5-48
Y18 Output
q
A5-11
Y 17 Output
r
A5-21
Y16 Output
s
A6-34
Y 15 Ouill~t
t
A6-46
Y 14 Output
~U~__________~A~6~-~8~__~____________________~Y~1~3~O~u~tp~~u~t~____________________ '
v
A6-18
Y 12 Output
w
A6-35
Yll Output
x
A6-47
Y 10 Ouill~t
y
A6-9
Y9 Output.
z
A6-20
Y8 Outgut
AA
A6- 32
Y7 Output
. BB
A6-44
Y6 Output
<::c
A6-6
Y5 Output
DD
A6-16
Y40utput
EE
A6-36
Y3 Output
FF
A6-48
Y2 Output
GG
A6-11
Y 1 Output
HH
A6-21 ./
YO Ou~ut
Twisted Pin.
PT06A-22-55S (SR)
** 2~ Ga White Stranded
Connector. P6
TITU
i-HT,NQ Dwe. MO.
an.
01 G1.TA L ~
OEvtL.O'-MENT
WIRE LIST ~. CARD RACK'
1
13775

*

CORPORATI:ON

PageZS

,

~I"._:".

Terminal
"-,....._......=
-'-'
- ...
~-~~

A

--

"

From

-

1 ,',

cu'-

AI-44 (WLJ

B
C
V
E
F

A1-,48 (B)" ):c
A 1-:,46, (SH)
Al~34(W}J
A1-.38, (B)" ):c
Al-.36 (SH)

G

.Al"B(WL]

H

A~~A (B) ..
A):- 6 (SH),
AI-18 jWL..
Al . (B)

J
K
L

To

Function
Clock Read Ampl.. Input
Clock Read Ampl. Return,
Shield Termination
Timing Read Ampl. Input
Timing Read AmpL ,Retur~
Shield Termination
Data "A" Read Ampl._Input.
Data "A'I Read Ampl!... ,R~.turJ:l
Shield Termination
Data 'IB" Read Ampl•. _lnp.!J.t
Data "B" Read A~pl_~ __!t~t~£..Il.
Shield Termination
~

*

Ai:l1, (SIn' *

M

..

N

p

R
5

A5-24
A5-28
Al-DCO
Al-DCO
Al-DCO
Al-DCO
Al-DCO
Al-DCO
Al-DCO
AI-DCO
AI-DCO
Al-DCO

T
U

V
W

X
y

z.
a
b

c

***
***
)

![
\

**

I

-

Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground

---_.-----

--

--

--0,

-

,

III

"

"

.-----

-

-------

.

.

......

-

-- ...--_
. --..
-----_.....---- . _._------.._ _---- . ,--_.
.. - .'"'--_._-- . ---- .. --'--.----

.

_ _ _ _ _ •

-

---•'

+l8V
-l2V
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic

_ _ _ _ _ _ ,.._ _

-

0

......

....--.""----~----

.

------~-.--------..-.---

.

-.~----

-

,

~----,"---

-

.

.

-

--

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.

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.

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01 G I T A L.

-TC'

0 EVE 1-0 P M EN T
c 0 R po R .~, T I 0 N

Z4 gao
Z4 G~_w.:hlli..
"I~\.."

WIRE LIST

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r-P.l'_Q6A.J.9.::.2 6.S_LSRL

* Shielded Twisted Pair,
***

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.

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24 Ga Black

--

'--

-

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-

....

.

-

.-

.

. -,-

-

.

--

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-'

-

- -.

-

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.

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--

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.-

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- CARD RACK

l-fp~~c!.or
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t

i

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pw.,. Ito.

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_ . _ _" , _ . _•• _~.~ _ _ _ - - - ,

----'.---" ,._------._--,,'----------------------,---_. - - - - , - - - - - - - - - - - - - - - - - - - ' - - - -

y ,---, '- - --------,-.. ,----~--,--,----,----~.-" ..--.-,-------~-----,.---

l
QTY

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LOCATE@
APPf()X.
,
AS SHOWN

(3)
~

Z7

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PLA(

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2.0

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L_,I

51:£;
NOT1!

-

7

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22
-,~

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'i:;(·

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00
0''''.

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t~~

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.:;

I

I

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/
/

/

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t.

_17"-6

71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47

4
1
1
1
1
1
1
1
15
4
16
12
12
12

10-24
13714
N-54M
13722
13832
13779
See Note 8
See Note 8
No.8
No.8
No. 10
No. 10
No.4
No.4

Hex Nut (CP)
AC Cable Assy
Transformer (Triad)
Channel XFMR Mtg
System Control Wiring Diagram
Timing Diagram
. Sig Flow Chart
Functional Block Diagram
Flat Washer (88)
Washer, Lock, Internal Tooth (SS)
Washer, Flat (88)
Washer, Lock, Internal Tooth (SS)
Washer, Flat (88)
Washer, Lock, Internal Tooth (88)

44
44
43
42
41
40
39
38
37
36
35
34
33
32

4
12
12
4
8
4
4
10
8
8
8
2

4-40 x 5/16
8-32 x 1
1/4-20 x 5/8
8-32 x 3/8
8-32 x 1/4
10-24 x 1/2
10-24 x 3/8
8-32 x 1/2
No. 10
10-32
10-32 x 3/8
40QD-18-1 i

Soc Hd Cap Screw (88)
Soc Hd Cap Screw (SS)
Soc Hd Cap Screw (SS)
Soc Hd Cap Screw (CP)
Button Head Screw (CP)
Soc Hd Cap Screw (CP)
Soc Hd Cap Screw (CP)
Flat Hd Soc Screw (CP)
Washer, Lock, Internal Tooth(CP)
Hex Nut
Button Head Screw (CP)
Slide, Quick Disconnect (Jonathan)

29
28
27
26
25
24
23
22
21
20
19
18

Contacts (Winchester)
Connector (Winchester)
Adapter, Slide Mtg
System Sticker
Cover Sticker
Ident Tabs
Card Extender Assy
Connecj!Or Clamp
Bracket, Connector
Standoff
Relay Mtg Board Assy
Cover Assy
Memory Drum Assy
Card Rack Assy
Indicator Panel Assy
Base Plate Assy

16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

4

2
2
1
1
1
1
1
1
1
1
1
1
2
2
2
1
1
1
2
2
4
4

1

,.\

2

.1

T
®
@

ITEM

DESCRlPTION
Hex Nut
Soc Hd Cap Screw (SS)
X-Amplifier
Pre Amp Module Data
Pre Amp Module Timing
Head Substitution Board
Marking Dwg
Wiring Harness
Cable Assy DC Power
Cable Assy AC Power
Connector (Bendix)
Connector (Bendix)
O-Ring (Parker)
Plate Conn. Hole Sealing
PIng Conn. Hole Sealing
Washer, Lock, Vernal l'ooth (88)
Washer, Flat (88)
Soc Hd Cap Screw (CP)
O-Ring (Parker)
Plate Conn Hole Sealing
PIng Conn Hole Sealing
Spacer (Amaton)
Soc Hd Cap Screw (CP)
Spacer (Amaton)
Soc Hd Cap Screw (CP)

50
1
2
1

-----

(Jl.SNE T OP£NINCo \_

PART NO.
4·40
4-40 x 3/8
11818
11807
11811
11680
See Note 8
See Note 8
13823
13824
PT06A-12-13S
PT06A-14-12S
2-125
13858-3
13857-3
1/4
1/4
1/4-20 x 1
2-131
13858-4
13857-4
No. 9318A140
4-40 x 1/2
No. 9253A219
10-24 x 1-1/8

8
8

1
2
1
4
1
1
1
1
1
1

00-1022-P
MRAC50POT009
13810
10142
10141
13062
11359
12948
13860
12738
See Note 8
See Note 8
See Note 8
/13773 ,
13211
13~90

DWOREVD

DWG. NO. 13770/13870

~-------------------------------------------- 1925----------~------------------------~I----,75j
(RE~l
:
(RE
(REE)

VI EW
FOOT.TEO

1-\ -1-\
Ifl(f'

HEMS 18 AND "

HAVE BEEN OMtTTED

Model 7302, Serial No. 17 and above.
Model 7301, Serial No. 27 and above.
MEMORY SYSTEM
INSTALLATION
ASSEMBLY

DWG. NO. 13770/13870

Page 3-41
Section 3

RI
RY

,...

p;r
l>

P8
FROM
CLOCK
I'REA""

f)ISC SNED

C

A

e

.

Dca

: .. AI
:..

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Cl

DCa

I
DOl"
JJ1I7l

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'7

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I

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191

w ...1
r

1

1

------------------l
1=7"-r

I

~r-,--~-~--~--~-~--,---.~--,o-,-,-,-~-~--~-,-'-'~--n-,-s-Iq-W-'01

1

'->- l.;d;;

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40 :&9

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L-_ _ _ _ _ _ _ _ _~-~-_-_-_-_-___
-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~____________________________________~
NOTa:
\. PIN "lVMI3EJZ.S ON

r.c.,'.e WITHJ"'" c,ar.,sHEO ~ IZIE...~
~~Z~~~~~ :a~~&~~~ "'TeaM\NAL ....\)Mee.a.~

NOTE:-

1. Pin numbers on I. C. 's within dashed areas refer to integrated circuit
pins. All other terminal numbers are circuit card pin numbers.
FIGURE 3-24.

FUNCTIONAL BLOCK DlAlJRA:\I
(SHEET 1 OF 2)
0 ......

o

'11

l " . ~ 0 .... I " •

~ ,C?,.~.~ .~....~..'.':' ~

,.'

t

TA A17-13

TA

J10

31

TO

TO .!

A,L'2

2. -

II

3

151
131

'8

I

M i)'

~

413-17

r 401

I _

z JM 2

I

3

~

I

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I l l " M I 13

I
Ib,

I

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41

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[Q£Q] I

1

IZ'jVIZr

, IM4-'

4"1
."

2.

.J'

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J

12.

_I

L
2~
L-------=:jI:4=.:---'==--I-1"
.~

1

S

11

48
36
16
6
44
32
20
9
47
35

8

1'0""'2

,~ ""

'/1

3

TVP16 CIRCUITS

TZ f ~-+-4--~~~'·7~--~~91~'M~3~~~ID~~3~8~~--~3~9~--~----------4~[~...~::::::"~
y:1'6

I

"y'DECODE

171

I

I
I

-....:T...:..I--2;,3~::;~----.......::~:-il."AA~3;:...
,',
T2

5

I .... ::::::"
9~i)~/~0~1~~~--~I--.-+'-Z-----4-~S=·r.,IM~Z~~6~----4

I

T17
...;.1--r..............

101

1,4

I,

DCO

AU-19

r-------------------A6--'

r------l

A13-11

lM ...~~"~-----t

18

9

M3
r--TL-__....1.!.'0~~I'MMI4..._y._:8~r__---4
l
I
T
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I
I
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I _ _ _ _ _ _ _ _ ,_ _
1-

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31
21

..... ~'51

:::'~"'C
'V" 131
1

I

I

z.

15

31Mi"
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9

11

1141

301
231
401

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101
I
171

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I
,

I
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2.

3

MY

I

IS:::-

I

41

TI" ,

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L

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PAGE 3-42
SECTION 3

V4
V5
VI;
V7
V8

V9

'i" Vl0
.,;;.;;;..

VII

:!.. Vll

.!;.

~

•

V13
V14
V15

~,

12

/I

fIIl.J

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S

1 TI

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12.~

,
IJM4-

411

---

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21
11
48
3&
16
&
44
32
20
9
47

--

II

13

s
6JMI'4

I

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)..::'3:::....-~T

9

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3

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,

TY'P 16 CI RCUITS

5
18
8
4&
34

B -I------1-..
~

,0:-lM ...}:I>.!:.

1
IL ________________________________
L-________________________~!~J~'M~3r+~~------'~~£~M~4-/~~II~--~~

I

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"y"DECODE

1

~M.2.. 3

~ 10 138
39'
[ ....::::::L..-__~2~71____~9~~~M~~~~I~------~~2:9~1=~--+,-2---------4-~S~r.IIM~4~
"

34

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r--------------------- A5---'

r-------,

J

I

II'.

13~

VO

~ VI
:.g
, V2
ii V3

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I

I

13

8

J..§

'a..........

I

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C V'6
~

V17

~p V18
li V19

':iii

k

'4-"'"

+
~
.;.
1.

V20
V2l
V22
V23
V24
V25
V2&

~ V27

..!
t

t

t

~

V28
V29
V30
V31

A13-20

14

k

T4
B

"
71

TVP 1& CIRCUITS

10

1

DCO

I

8

I
"
IL _____________________________________
J

NOTE:
1. This Functional Block Diagram applies to both Part No. 13770 and Pari
No. 13870, except ''Y'' Decode Card A5 is used only on Part No. 13770 units.

12.1
11
48
3&
16
I",
44·
32
120
IQ
147
35
18
8
4&
134

~
~

:f:
~

J1.

~
eM,

J

~

4

.!;
~

M-1;.

~

r:!:
J:!.

XOA
XII.
X2A
X3A
X4A
X5A
xOA .
XTA
XOB
X1B
X2B
X3B
X4B
X5B
X&B
X7B

FIGURE 3-24.

FUNCTIONAL BLOCK DIAGRAM
(SHEET 2 OF 2)

D,eITA t.

FUNCTIONAL
BLOCK DIAGRAM

DWG. NO. 13777/13882

D •••

•

LO"~_'"

First Disc Revolution

Second Disc Revolution

..

-~------------------------------~~----------------------~'V""~---------------------------------'~----------------------~"
r"
Origin Pulse, Beginning of Controller Address
~

Sector Clocks A & B f~: Sector 2.

II

II

Index (Not Sent to Contr.oller)

--Jtl~------~T------~A~----~~'------JI
SI Data
S2 Data

End of Address

Note that Sector Clock A occurs during data transmission for the previous Sector.

II

II)J

1o. P.

II

.."

II

rI

---.JI

S45 Data

Guard Band following O. P.

II
'+I'-"'_____----'A"'--__

'JI'

546 Data

\.

547 Data

II
....
S90 Data

Guard Band following Index

l

....

SI Data

Guard Band

TIMING RELATIONSHIPS AT ORIGIN PULSE TIME (Timing at Index is similar)

Origin Pulse

I

*

I

t4-- 6 Bits

-tal

Sector Clock

I
I

*
3 Bits

Write

*

J End Writing Sector 90
,-

Read

*

27 bits

.,

-..

(3 MH )
z

U

U

SCI - A

SCI - B

62 Bits

~

lit

I Start Sector 1

I

I Start Sector 1

__~I End reading Sector 90
f-4-23 bit~

TIMING RELATIONSHIPS AT SECTORS NOT AT O. P. OR INDEX.

Sector Clock

Write

*

*

U

U

SC(n) - B

SC(n) - A

28 bita.8_ ..........1

I Start Sector (n)

End Writing Sector (n-l)

t--24 bitB---f
Read

*

_ _ _ _ _ _ _ _ _ _ _ _ _......_ _ _ _ _ _ _ _ _ _ _......_ ......_ _ _ _ _....;;;E~n~d;;....;;.R;.;;e;.;;;a;.;;;d;.;.i_nii!.g....;s;..e;..c;..t...;.o..;.r...:,.(n_-_I"",_......1
DATE

TITLE

,.' )/

l.-:'

,.,

I

Start Sector en)

~

DIGITAL.

\1.·2,0·8
CHECKt:D

,

TIMING DIAGRAM

DEVEL.OPM~NT

CORPORATION
SS1S I(AII"" WIlL" RD

~." DIlGO

A~~"OVEO

Page -l of 4

CU"

r-1l
r1

Cl
2.5, 325

-----In

C2

Sect, 'r Clock
(See Note 1)

Write

Pulses per Re~ulutiun

*

n

n

n

n

\

---i

-t(

t3

n~----"f1~--Jn,------"n___n

~

~f--f__n____

n __

Sf

ss-J

\

0

0

I

1

\

0

I

1

\

0

0

ri~

----------~~~--

I

{/
~
1

Write Cluck Alluw

0

I

1

~pJ

1

\

{/
'J
~

fe- t4

*

\

Read.

r

Sf

J.
1

Data Read

*
1.
2.
3.

1

0

0

I

1

0

{f
~

J

Read Clo

0

Data Read. Data channels are

>

recombined by gating alternately both

~

A

~

I

channels with CI reading out FFA
and ST reading FFB.

I

B

0

A

I

0

13

n

I

A

0

B

n
I

A

B

A

0

0

I

B

LJ
0

~%

:"

z

~
IQ

0

f

• _.
...

0

z

0

W

0

Nt

I

~

-..J
-..J
-0

! )!

noo

o ,.. -

... ,..

"

:a 0

,.

:a <

R/w Clock*
(Read Mode)

~ I

-.

o ,. >-4
> ...
-4

Data received in controller FF

~nt!

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z -4

Register H

I

I

n

A

B

I

I

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TIMING TRACK IN:::.:F:..:O:R:MA=~T:.:l=O..:.N::.:_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

• Bit Period is 680

one revolution (17. 4 me)

Sector 1
(Sectors Z thru 44are similar)

no'

Sector Z

---\l:l------

Se~or 45

Shift Register
Stage.
A

B

..J I I I I I

~,.
J
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C

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D

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I I L

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I

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......

I

I

I i

I

i

L

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.. ----------rlL..-------------1t'l:)..--------------------------------------

,},-------rtL--------_c~l:)..--------------------1t l-,
---------------4~_

,..

.

F

------------~~~~----~r1~--------,\1,
,-------------------~~~-----------~~----------~\l~---------------------------------

G

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.. ----------rlL________~\\~-------------------------------

H

---------------;U~------"L--------~"~-----------------;U~---------rl~--------~~~--------------------------~

Gatina

IX (Index)
TOP. (Origin)
SC- (Se.tor)

I

I

I

I

u

---------------,--------~u~---------------------------,u~-----------,
U

W·
R-

U-J

I

J

I

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Rl*
RWA (Allow Clook if writing) ____________________1

WE(Enablewri~ng)

~I------------------------------------------------------------------------------------------------------ii---.

RWA (Allow Clock if reading)
expanded ecale
Clock
Cl
CZ
ST
STA
STB

(340 ne) - ,
(170 ne) --.J
(170 na)
(80 ns)
(80' n.)
(80 na)

I
I
I

I
r1

n

\

L

NOTES:
1. There are 2.5S25 clock pulses
per revolutioa.
Z. The Timing Code is strobed
into
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(ST) leaclihg' edga.

44 thne.

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AZO

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AI8

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AI6

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0"

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8
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A8

A7

A6

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A4

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NOTE - CARD INSER TION SIDE SHOWN

CIRCUIT CARD

POLARIZA TION

• ead Amplifier

Pin ZO

Jaterface ~~rd fZ
liltetoface Board ,I
Generator

Pin 40
Pin 4Z
Pin 3Z

Lin.. TermiDator

Pin 30

Delay Circuit
Decode Matrix
Write ~plifier

Pin lZ
Pin 24
Pin 2Z

X Amplifier

Pin 16

Cl~ck

Decode Driver

NOTES:

&

&Z

Not Used on units of ZS6track or smaller capacity .
Use 11791 Clock Generator for 60 Hz operation.
Use 11874 Clock Generator for 50 Hz operation.

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11792
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DESCRIPTION

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PART NUNBER

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Canacitor

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CIRCUIT CARD

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11793

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Rll
Resistor
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RIZ
Resi~tor ______ SlOK :t 50/0 1/4 watt
R13
330 ohms :t 5"10 1/4 watt
- - ~esis!or
R15
Resistor
750 ohms :t 5"10 1/2 watt
Rl6
Resistor
5. lK :t 50/0. 1/4 watt
R17. 18
Resistor
_-.1 tK. ~_5 "10 • 1/4 watt
R19 6
Resistor
750 ohms :t 5% 1/4 watt
R20 ZI ZU~__ ~Iiesistor
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RZ4
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5

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1
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Pin Z6 fo Sv

.CH.MATIC

PICTOItIAL

11792
11793

APP"OYKD

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b -2-'1 t1

50 Hz Speed Detector
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