0285 0229 Gould 4500 Digital Storage Oscilloscope Service Manual Apr84
0285-0229_Gould_4500_Digital_Storage_Oscilloscope_Service_Manual_Apr84 0285-0229_Gould_4500_Digital_Storage_Oscilloscope_Service_Manual_Apr84
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Part Number 0285-0229
April 1984
4500 Digital Storage Oscilloscope
..
Servi ce .Manual
Gould Inc., Design & Test Systems Division
4600 Old Ironsid~s Drive
.
Santa Clara, CA (408) 988-6800.
TWX/TELEX # 910-338-0256
Copyright @1984. No part of this
publication may be reproduced without
written permission from Gould, Inc.,
Design and Test Systems Division.
Printed in U.S.A.
PRE F ACE
WARNING:
This equipment generates', uses, and can radiate radip'
f r e que n c yen erg y 'a nd .i f not ins tall e dan d use q tr'l
accordance with",-the-vinstructions in ·this manual,' may
. cause int.erferen'ce to radto com municatipns." As
te mporarily permitted bY,regulation, it has not been
tested for de"vices pursuant to Subpart J of Part 15 of
FCC Rules, which are;: designed to provide reasonable
protecti"on agai"rist such interference. Operation of
this equipment in a'residential area is likel~ to cause
interference 1n which case the user at this own expense
will be required to correct the interference.
Th~'''fo ll~wi ng.- procedu~es may help t~ a~ (~vi ate the
radio or television interference
,
•
ok
!II'
pr~blems:
."'..
,_
.
••
~
1. Reo'ri ent the antenna of the recei v~r Tecetv,:rng the
, interference.
, , , . , af..,i' ....
•.,;:<.
.
"'.,
,
~. Rel:ocate'the equipment causing the interf~r.en·ce
.*
with respect to the receiver (move or change relative
pos i ti on) •
3. Reconnect the equipment causing the interference
into a different outlet so the receive~ and. the
equipment are connected to different branch circuits.
4.
Remo~e
the equipment from the power source.
NOTE:
The user may find the following booklet prepared by
the FCC helpful: How to Identify and Resolve Radio-TV
Interference Problems. This booklet is available
from the U.S. Printing Office, Washington, D.C. 20402.
Stock No~ OU4-00U-00345-4.
ii
PREFACE
(C 0 N. T I. N U ED)·
".lIi
.-
This manual provides specifications~detailed theory of operation,
calibration~ and alignment procedu"re.s f'6r the 4500 Digital Storage
asci 11 oscope. This manual was wri tten for use by techni ci ans and fi e 1d
service personnel ~xperienced in fhe -aJ ignment and calibration of comp...1ex
el ectroni c equi pnlent.
.
""!,
••
The material in this manual is up to date~at tre time of publication,
is subject to change without-notice. .
b~t
Copies of this publi'cation and other Gould, ---I.ne., Desi..gn and T~st 'Systems
Division publications may be ~btai~ed from the Goul.d 'sales office or
distributor serving your locality.
.
RELATED PUBLICATIONS'
450U Di gi tal. Storage asci 11 os cope Users Manual,
Publication Num~er 0285~0212-10
For assistance with the pro~uct, please call Gould, Inc., Design and Test
Systems Division customer service on the toll-free, hot-line n~mbers
listed below:
Nat i Ofla 1
(8UO) 538-9320/9321
California (800) 662-9231
iii
TAB L E
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CON TEN T S
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Page
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CHAPTER 1" GENERAL I NPORMAI)ON ....... ~ •• ~................................ 1-1
INTROD.UCTION..................................:•••••••••••••••••••••••••••••••• 1-1
GENERAL D~SCRI~\rON'.".·~.4!.'.!·~ ••••••••••••••••••••••••••••••••••••••• 1-1
FEATURE.S .OF· THe 4SPO .,~ ... '.............................................. 1-3
SPEC I FI C!f.T (ONs •••• ~ .••'.... ~ ... '••••••••••••••••••••••••••••••••••••••••• 1-4
iii
•
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~a:,t
. - '.0
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"..
til
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CHAPTER 2 .. Ptil{FORMANCE. VER I F,lGJ\lI ON ••••••••••••••••••••••••••••••••••• 2-1
. I NTROOUCTI ON. ••••••••••••••
o. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-1
TEST .EQU IP.J't1EN1 •••••••••••••••••••••••••••••••••••••••••• 2-1
. PERFORMANCE VERIFlCi\TION PROCEDURE ••••••••••••••••••••••••••• ~ •••••• 2-2
Instrument w,armup •••••••••••• ~,: •••••••••••••••••••••••••••••••••• 2-2
rnitiating, Self;;Test ••••••• ·•••••••••••••••••••••••••••••••••••••• 2-3
Sweep and Recorp Self Test ••••••••••••••••••••••••••••••••••••••• 2-3
'Trrg~er Self Test ................................................. 2-3
At1:enuato'r Sel f ·Test ••••••••••• ~ .................................. 2-3
Channel· A AUC Sel f Test ••••••.••••••••.•••••••••••••••••••••••••••• 2-4
Channel A.:D~L Self Test •••••••••••• ~ •• ~ •••••••••••••••••••••••••• 2-4
Channel a.ADC Self Test •••••••••••••••••••••••••••••••••••••••••• 2-4
'Chahne 1 .~" ONL Self Test ••••••• ~-••';. •••••••••• ~ ••••••••••••••••••••• 2-5
AUTO·' CAL ·Sel f Test ••••••••••• ~. '!' • • ~ • • • • • ~ . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Keyboard .Self Jest.·................... ·•••••••••••••• ~.' ••••••••••••• 2-5
MPU/CRT Self Test ............ ~: ••••••••••••••••• ~_ •• ;.~ ••••••••••• 2-6
'Inp~t: l~peda~ce ••••••••••••••• ~ ••••••••••••••• , •• ·••••• ~ •••••••••• 2-6
F.ront Pane T Test Poi "ts .' ••••• ~ •••••••••••••••••• '." •••••••••••••••• 2-7
'Input Noi~e~arid Offset~ Dual Sweep Speed Switchover •••••••••••••• 2-8
Channel A r~put Coupling, Trigg~r Coupling, and Trigger Slope •••• 2-9
Channel B input Couplingj Trigger Coupling, and Trigger Slope •••• 2-10
External Trigger.C6upling and Trigger Slope •••••••••••••••••••••• 2-10
Tri'gger Ft·lt.e·ri n9 .•••••••••••••••••••••••••••••••••••••••••••••••• 2-11
.L~ne Triggeririg •• ·•• ~·.~ ••••••••••••••••••••••••••••••••••••••••••• 2-12
~anual. Tri~gering •••••••••••••••••••••••••••••••••••••••••••••••• 2-12
i nput· Ban dw.i dt h•.• ~ • • •.• • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 2-13
Channel Isolaticin.~;~ •••••••• ~ ••••••••••••••••••••••••••••••••••• 2-14
Plotter Outputs •••••• ~ •••••••••••••• ~ •••••••••••••••••••••••••••• 2-15
Trigger Output ••••••••••••••••••••••••••••••••••••••••••••••••••• 2-15
C1O,C k 0ut put • • • • • • • • • • • • • • • • • • • • • • .• ~ • • • • • • • • • • • • • • • • • • • • • • • • • • • • •2-16
'Cloik Gate Input ••••••••••••••••••••••••••••••••••••••••••••••••• 2-16
Display Intensity Control •••••••••••••••••••••••••••••••••••••••• 2-16
.CMOS Memory Data Retention Test •••••••••••••••••••••••••••••••••• 2-16
Floppy Disk Drive ••••••••••••••• ~.·••••••••••••••••••••••••••••••• 2-17
Interface Option Tests ••••••••••••••••••••••••••••••••••••••••••• 2-19
'~RECOMMEND~D
'CHAPTEl{ 3 DIAGNOSTICS •••••••••••••••••••••••••••••••••••••••••••••••• 3-1
INTRODUCTION •••••••••••••••••••••••••••••••••••••••••••••••••••••••• 3-1
POWER UP DIAGNOSTICS •••••••••••••••••••••••••••••••••••••••••••••••• 3-1
4500 BUILT-IN DIAGNOSTICS ••••••••••••••••••••••••••••••••••••••••••• 3-2
·SPARE COMPONENT RECOMMENDATIONS ••••••••••••••••••••••••••••••••••••• 3-6
iv
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CON TEN.T S'
(C 0 N TIN U E D)
Page
CHAPTER 4 . CALIBRATION ••••••••••••••••••.••••••• ,.;:~.." •.••••••••••• ·••i$~ • • •f • • • 4-l
INTRODUCTION ••••••••••••••••••••...• ~.. ~ •••-••••• ". ::'-:~••••••••••• ~ .........
RECOMMENDED
RECOMMENDED
RECOMMENDED
CALIBRATION
r~pu
e" • • •
4-1
CALIBRATION INTERVAL ••••". ~.,. •• ~:. ~'i
~~,~~ ~ ~.~'
4-1
CALIBRATION SEqUENCE •••••••••• ".'.•••. ~ •.:, • .,. :,:... •.•••• ~ .•••••• 4-2
TEST EQUIPMENT ••••••••••••••••••• ~. ~ :~~ •.~.', .•• ~ ."~ ..... '.'.'•.• ~~ •• 4-2
PROCEDURES FOR MODULE REPLACEMENT~~·;=;::':eee •• ;~ •• ~ .•••• 4-2
•. ,
Boaid •••••••••••••••• ,. .......... ~ 'c:S:~"
.:.
e e e •••••••••
••
.•
..........
~ • • • • • ~ •. ,~.'. ~ ~' • • • 4-2
/
." __ •••• 4- 2
Interface Board •••••••••••••••••••• .~ •••••.·•••••••••••••••••••
Floppy Controll er Board ••••••••••••••••••• : ••••••••••
'.~ .4-3
CRT Dri ver Board ••••••••••••••••••••••• ·••.•.•:•••• -. e";•••.•••••••' •••.•• ,,4-3 '.~
Sweep and Kecord Board •••••••••••• ~ •••• ~ ••••••••• : •• ~~ •••• ~ •••~;~4-4·~
Attenuator Board •••••••••••••••• '•• ~•• '••••••••••••••.•••. J •••• ~ •• : : ••4-"4
ADC Board •••••••••••• ~ •••••••••••••••• ~ •••••••••• : ••••• ~~ •••• ; •• :4-5
POWER SUPPLY CALIBRATION PROCEDURE ••••••••••••••••••• ~ •••••••••••••• 4-6
MPU CALIBRATION PROCEDURE •••••••••••••••••••••••• , •••.•••• ~ ••• ;.!~,; .. 4~6
CRT CALIBRATION PROCEDURE ••••••••••• ~ ••••••••••••••••••••••• ~ •••• : •• 4-7
FLOPPY DISK INTERFACE CALIBRATION. PROCEDURE •••••••• '........ ~·••• ~ •••••• 4-H
SWEEP and RECORD CALIBRATION PROCEDURE e'••••••••••••••••• '•• e'. ~ •.•.••••• 4-8 .
AOC CALIBRATION PROCEOURE ....................................,.:: ••• ; •.•• 4-li,
Al i gnment Procedure ~et"Up .••••••,.;. ~ .0 .• -.....................-.. :.... ~ .• ~ ••'4-13
Power Supply and Reference Vo1tage Check ....... ~ •••••••• ;~ •. ;~.~·~~.4-l¢
Offset and CAL DAC Adjustment •••••• ~ ••••••••••••••••• t • • • • • • • • • • • 4·l7
First Stage ,Amp,lifier Adjustment ••• ~· ••••• ~.·•••••••••••• ~ ••••• ~~; ••• ~-17
TRACK and HOLD CIRCUIT' ADJUSTMENT •••• ~ ••••••••••••••••• ~.~~ •••• ~ •••• 4-20
Second Stage Amp i i fi er Adj ustment •• .-•••• ~ ~ ....... ~ •• ~ .... ,.' •. '~ •• '••••• ~4-23
Third Stage Amplifier DC Adjustmen.t •••••• : ••• ·•••• ·.: ••••• '••••••••• 4-23
Second Stage Amp 1 i fi er Rise Ti me Adj ustment ••••• ~ •••• .-..............4-·2~··:
Data Ready Strobe Adjustment ~ ~ : ~ e e • e'" ee,".'•••• ~ •.,•••• '•••••••••••••• 4-26
Comparator Adj ustment • .; •••••••••••••••••••• "••••••.••• '~.'•••.•• '•••.• ~ •• 4-26 ;
33-MHz Alias Test ••••••••••••••••••••••••••• ~ ••• i •• ~.;~~ • • • • ~ • • • • 4-32'
Bandwi dth Adj ustment ••••••••••••••••••••••••• '~ •• ~ ••••••. ~ .' •• ~ ••••• 4'.. 32
Tri gger Level Adj ustment •••••••••••••' ................ .- ••'~.• e ...... ~ •• 4"':34
AUTO CAL and DNL Tests ••••• ~ •••••••••••••••• ~ •••• ~~ ••• ; •• ~ •• ~~.~.4~36.
INPUT and EXTERNAL TRIGGER ATTENUATORS CALIBRATION' PROCEDURES ••••·••• 4.. 39
Channel A or Channel B IP BALANCE Adjustment ••••••••••• ~ ••••••• ~.4-39
Channe 1 A or Channel B OP BALANCE Ad'j u·stment ••••••••••••••••••••• 4-39
External Trigger TRIGGER BA~ANCE Adjustment •••••••••••••••••••••• 4-40
Channel A or Channel B AC/DC Control and liP CAP Xl Adjustment~ •• 4~40
Channel A or Channel B COMP XIO and liP CAP XIO Adjustment ••••• ~.4~41
Channel A or Channel B COMP XlOO and liP CAP XIOO Adjustment ••••• 4~4l
External Trigger COMP and lIP CAP Adjustment ••••••••••••••••••••• 4~41
0 • • . ; :• • • • •
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TAB l E
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CON T'E N T S
1
(C 0 " TIN U E OJ
Page
f • • • • • •~ .'.~. • • • • • • • • • • • • • • • • • • • • • • • • • • • . , . , .5-1
~ .... ~~. . . . . . . . . . . . . . . . . . .:~ • • • • • • •". . . . . . . .- • • • • • • • • •' ••.• 6--1
CHAPTER 5 THEeR.Y OF OPERJ\T.I ON ......
I NTR~O{}uCT I O'N:~ ....... 1'~'. ~ •
4500 DLGII.At,· O.sCIlLOSCOP£ 'BLDCK· nIAGRAM· DESCR I PT ION ••••••••.•.•••••••• 5-1
4500.0·v;erv4ew and oS.i!gbai' Processing ..................................5-1
Si .goa 1 I n'Put -,. and. :rAQ'a 109 S.t~p's' •• ·............................... eo" •• •. b-l
Si gn~ 1 .{ nput ,~r)d .Oi gitcrl ·Steps ••••••• 4. •••••••••••••••••••••••••.•• 5-3
Processi ng :·and'.#Qi spl ay :Of ACElu; red Data ••••••••••••••••••••••••••5-3
Time' Base Contrr'Ol ~~~·.~'~·•••,•• ~.~••••••••••••••••••••••••••••••••••• 5-4
Tr,i gge i n9'. '" •.: •. : •.• '; ........... '. '. ';. ~ ~ •••••••••••••••••••••••••••••••••• 5- 4
Pro~es~or:': Operat tan •• '•••••••••••••••••••••••••••••••••••••••••••• 5-5
AutocCalibration, •• ~:.: •••••••••••••••••••••••••••••••••••••••••• 5-5
.Perl.ptiera 1 I nt'e.rf a..ce s •••••• '•••••••••••••••••• '•••••••••••••••••••• 5-6
. ·.450UDETAILE-0. THEORY"OF OPERATION ••••••••••••••••••••••••••••••••••• 5-6
MPU BOARD' THEORY'OF OPERAT'ION ••••••••••••• : •••••••••••••••••••••••• 5-7
.MPO Overview •••••••••••• ~ •••••• ~ •••••• ~ ••••••••••••••••••••••••• 5-7
Micro 'Processor •••••••••••••••.••• ·•••••• ~ ••••••••••••••••••••••••• 5-7
.,-I6K .Byte'Dynamic RAM ••••••• , ..... ·••••• ~.·~ ••••••••••••••••••••••••• 5-7
'·· ... 256· Byte 'rion-volatile CMOS RAM •• ~,;~ •• ~·••••••••••••••••••••••••••• 5-7
Processor/Bus Interf.ace.: .............. ; ........................... 5-8
I / O. I nt e r fa c e • • • • •• • • .'. ;. JI ". • .. • ~ • • • • • • • • • .' • • ~. • : • • • • • ~ . ' . • • • • • • • • • • • • • 5- 8
Memory and I/O Address Maps' •••'.•• ~ •••••••••••• ,,' •••• ~ •••••••••••••• 5-9
Inte rrupt .Cont ro l~ •. ,_ ~ .........'- ..••••.•.•••.•..•..• .; ...•...•.....•• 5-9
50-HZ Timer •••••••• ·;·~·.~~; •••• ,~ .••••••••••••••••••••••••••••••••••• 5-10
1li·5p] a1. ,Gen:erator. ·Over)lt~w.~. ~ .•• "•••••••••••••••••••• ~ •••••••••••• • b-l0
T"rac'e .'. Generato r •••.•••••• ': ..................... ~ '•• '••••••••••••••••••• 5-10
Character Generator. ~'. ~ ~ •••• :' •••••••••••• ~ ~'••• '. ~ • ~ .'•••••••••••••• 5-11
Grat i cuJ e Ge·nerator •••••• ~ •• ~ •• ~ ................... ~'••••••••••••••• 5-12
Osci 1.1 atqr .and",.tlpc.k· Ge.nerat ion •••••••••••••••••••••••••••••••••• 5-12
bjs~l~Y Timin~~~.' •• ~ ••••••••••••••••••••••••••••••••••••••••••••• 5-12
CRT -BOARD', EPROM~MEMORY.~~ •••• ~ ••••••••••••••••••••••••••••••••••••• 5-13
. Overview.~~ •••• ~~~~.: •••• ~.~ ••••••••••••••••••••••••••••••••••••• 5-13
CRT EPROM Operation •• ;: ...... '•• !! • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 5-13
SWEEP AND RECORD BOARD THEORY BF·OPERATION ••••••••••••••••••••••••• 5-13
Memories (A and 1:3)' ......................... ·••••••••••••••••••••••••• 5-13
Channel A Memory ••••••• ~ ........................... e e . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
M'emory Timing Generators.·••.•••••••••••••••••••••••••••••••••••••• 5-15
Record Control ••••••••••••••••• ~ ••••• ·•••••••••••••••••••••••••••• 5-16
Sample Rate Generation •••••••••••• ~ •••••••••••••••••••••••••••••• 5-17
MPU Interface •••••••••••••••••••••••••••••••••••••••••••••••••••• 5-1S
Plotter Interface •••••••••••••••••••••••••••••••••••••••••••••••• 5-19
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CONTENTS
(C 0 N TIN U E D)
CHAPTER 5 THEORY OF OPERATION (CONTINUED)
ADC BOARD THEORY OF OPERATION •••••••••••• ~ •• ~ •• ~_.~ •••••••• ;.~ ••••• 5-19
ADC Board Overview •••••••• ~ •••• ~ .... ;.. ~' .••:~ ~.:e' .~~ ~ '-'; ...... ~.~:.'...:. , ••••••• 5-19
Programmab 1e Attenuator ••••••••••• ! .••. ~ .,~ .; .,~. ~ ~.~ ••• ~ e'. ~.... ~ • • • • • • • 5-20
Fir stAmp 1i fie r • • • • • • • • • • • • • • • • •.• .... • • .. • • .' ~ .' .............; .;. .'. ~ • • ~ • • • • • • • 5- 20
rd Ampll
,. ,. f ler
. ••••••••••••••••• '•• :,.. •••
;' ·.......................
. ·4 .
•
5 2'
~econ
~ ••••••• - J.
Track and Hold ••••••••••••••• : .•••.• ~;.~.~ .•. ~-••-..... ~.•.•.~ .•.~ ••• ~ ••••••• !) ... 21
Track and Hold Buffer Ampl i fi·er •••••.••• '~". ~ ~.:'~ .... ~. ~. ~,:.•.••.••.••••••• 5-22
Ana log to Di gi ta 1 Converter ••• ~ .:. ; ••• ,~ •••. ~ •• '...... ~'••• ~' ••••.••••• 5~2.3
Detailed Description of Folding Amplifier..~·::.~.••••• ;~~.~ •••'.-••••••• 5-2~
Folding Amplifier 'Digital Decode ••••••••• "'............"••• ~~ ... ·••• ~·,•• ~.~~5-27
Four-B it. Fl ash Co.nverter ••••••••• ~'••••••• ~ ~ ••·.0; ••••••• .- .......... ;5--27.'
AOC Pul se Generator ................ ~ ••••••••• ! .' • • • • • !It ••• : ~'.'~' • • '• • • • • '•.5'':'28
LED Drivers for In'Range and Out Of Rartge Indi£~t6rs ••• ~.~ •• ~.~~.5-~9
Reference Vol tage Generators •.••••••• ': ••••••••••••••.••.•••.•.•• ~' ••.•• .-5-3,0·
Tri gger Generator ••••• ·........................ ~ ••••••••:•• ~·it • • • • • • ••••. 5-31
I nput Offset and Offset AUTO CA~ ........................... :~ .••• :•••·.•·.5-3.3.
Power Supply ••••••••••••••• e· ••" ••••••.•.••••••••••••••.•.••.•••• , ~ •.••.•t~~ ~5-'35 '.,
ATTENUATOR BOARD THEO~Y OF.OPERAT~ON •••••• ~.~.~ •••••• ~ •••••. ~ .......... 5-35
Introduction~ ••• e.·~.~ ~
~
~
# • • • • • • • • • • • • • • • • • • • • 5-3ti
Channel A and Channel B Pass i ve Attenuators ••••••••••·............... 5-35 .
Channe 1 A and Channel B Bu ffer Am.P 1i fi ..ers ••••.•••••••••••••••• '. I!'•• 5';"36 '.
Description of Amp 1 •••••••••••.•. ~ ••••.• ·... ~.;·•••·•••••••••••• ·••••••• ·:·5';;38'.
Externa 1 Tri gger ..................'. : ........... :••.• '........... .;. ••.•• ~.:.; .••• ; • b-38
INTERFACE OPTIONS BOARD THEORY OFOPERAT-ION •••.••••••••:•••• :~.~·: •• ·••:•• 5·-39
Microproce~sor:·lnterface ••••••••• ~ •••• ;~~~.;~ ••••••••• ~ .••• ~~.~ .... 5-39·
RS-232 Interfac~ •• :~ .••••••••••••• ; •• ; •••••• ~ ••• ~.~.~ •••••• ~~~ •• ~.5-39
GPIB Interface •••••••••••••••••••••••••.••.•.••• '-.~ •• ~ .• '••. ~. ~ .• ! • • • e'. ~~-~:9'
DMA Interface ••••••••• ~ •••••••••••••• .- ••••••..• ~ .•' ...... '.......
·~ ~5-4.0
Ana log Averager Output •••••••••••••••••• ~ ••• ~ ..... ~ •• '••••• ' ~ •••
'.5-40
DR11-B Output •••••••••••••••••••••• ~ •• ~ .~ •• '. ~..• .- ................... ~. '.5-4·+'
FLOPPY DISK INTERFACE THEORY OF OPERA.TION ~ .. ~ ••·...... :.:•••••••••• ~ •• ~~5-42.
MPU Interface ••••••••••••••••••. ~ .................................~ it ••• ·.5-42·
Static RAM Memories •••••••••••••• ~ •••• r • • • • • · • • ~ • • : • • • • • • • • • ~ • • • • • 5-42
Data Request, Data Acknowl·edge •• ~ • ~ " •• '........ : ••••••••••.••••••••• S-43.·
Floppy Di sk Cont roll er ••••••••••••••' ••••••••••••••••••••••••••••• 5-43
Write Precompensation •••• ·•• : •• ~ ••• ~ •••••••••••••••••••••••••••• ~~5~43
Digital Data Separator ••••••••••••••••••••••••••••••••••••••••••• 5-44
Clock Generator •••••••••••••••••••••••••••••••••••••••••••••••••• 5-44
Disk Drive Power ••••••••••••••••••••••••••••••••••••••••••••••••• 5-45
FRONT PANEL THEORY OF OPERATION· ~ ••••••••••••••••••••••••••••••••••• 5-45
Key and Rocker Switches •• ~ ••• ·••••••• e • • • • • • • • • • • • • • • • • • • • • • • • • • • • 5-45
Clicker •••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 5-45
Front Panel Test Points •••••••••••••••••••••••••••••••••••••••••• 5~45
Range LEOs ••••••••••••••••••••••••••••••••••••••••••••••••••••••• ~-46
.. ......... ...... ...
'jt • • • • •.
.•.
It' • • •
vii
'.'
T A8 l E
C0
.~
.T E N T S',
"
. t.
.
,~,
CHAPTER 5 THEORY OF O.PE~ATION (CONTINUED'"
. (C 0 N TIN U E D)
Page
'.
CRT DRIVE~~O~Rb THEORY OF OPERATION •••••••••••••••••••••••••••••••• 5-46
Vertical .Sync System •••••••• ·•••••••• ·••••••••••••••••••••••••••••• 5-46
High Voltage Power Supply ••• ; ••• ~ •••••••••••••••••••••••••••••••• 5-46
Horizontal Oscillator and Driver ••••••••••••••••••••••••••••••••• 5-46
Pin Cushion Correction •••••• ~ •••••••••••••••••••••••••••••••••••• 5-46
Video Amplifier ••••••••••••• ·~.•••••••••••••••••••••••••••••••••••• 5-47
Intensity Control •••• ~ ••••••••••••••• ~ ••••••••••••••••••••••••••• 5-47
POWER SUPPLY THEORY OF OPERATION: ••••••••••••••••••••••••••••••••••• 5-47
Input Rectifier Filter ••••••••••••••••••••• ~ ••••••••••••••••••••• 5-47
Housekeepi.ng Supply ••••••••••••••••••••••••• ~ •••••••••••••••••••• 5-47
Pulse Width Modulator ........................·••••••••••••••••••••• 5-47
Chopper ••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 5-48
Transformer T6 ••••••••••••••••••••••••••••••••••••••••••••••••••• 5-48
Post Regulator.~ ••••••••••••••••••••••••••••••••••••••••••••••••• 5-48
Status Circuitry •••••••••••••••••••••••••••••••••••••••••••••••• 5-48
CHAPTER 6 SCHEMATICS AND REFERENCE DRAWINGS ••••• ~ ••• ~ •• ~~.~ ••••••••••• 6-1
INTRODUCTION ••••••••••••••••••.•••••••••••••• ~' •••••••• '. ~ •••••••••• 6-1
viii
LIS T
Page
4500 Digital Storage Oscilioscope.~ ••••••••••••••• ~ •••••••••• 1-2
ADC Circuit Board Jumpers •••• ~~ •••••••••••••••••••••••••••••• 4-12
Power Supply Adjustment Test Points •••••••••••••••••••••••••• 4-15
Power Supply (Thermal Compensation) Test Points ••• ~ •••••••••• 4-16
Test Point Locations •••••••••• i •••.••••••••••.•••.••.•.•••••• 4-18
Offset and CAL DAC Adjustment Test Points •••••••••••••••••••• 4~19
Track and Hold Adjustment Test·Points~ ........................ 4-21
Track and Hold Waveform Showing Nonflat Performance •••••••••• 4-22
Track and Hold· Waveform With 5UMV P-P Spikes ••• ~ •••••• ~ •••••• 4-22
Track and Hold . Waveform With 30-MV P-P Spi kes ••••.•••••••••••• 4~22·
Thi rd Stage Amp 1.i fi er Test Poi nts •••••••••••••••••••••••••••• 4-24
Second Stage Amplifier Rise Time Too Slow •••••••••••••••••••• 4-27
Second Stage Amplifier Rise Time Showing Overshoot ••••••••••• 4-27
Second Stage Amplifier Rise Time With Slight Overshoot ••••••• 4-28
Second Stage Amplifier Rise Time Correctly Adjusted •••••••••• 4-28
Second Stage Amplifier Test Points ••••••••••••••••••••••••••• 4-29
Comparator Mi~adjustment With Waveform Sp1itting ••••••••••••• 4-31
Compar·ator Mis-adjusted ••••••••••••••••••••••••••••••••••••••• 4-31
Correct Comparato~ W4veform •• ~ ••••••••••••••••••••••••••••••• 4-31
33-MHz Alias Test Showing Acceptable Adjustment •••••••••••••• 4-33
33-MHz Alias Test Showing Perfect Adjustment ••••••••••••••••• 4-33·
Trigger Level Test Point and Adjustment Locations •••••••••••• 4-3b
CAL Correct i ~>n Factors Di sp 1ay .••••••••.•••••••••••••••••••••• 4-37
DNL Test (Slow Version) Corr~ct Waveform ••••••••••••••••••••• 4-37
4500 Block Di agrain •••••••••••. ~ ..................-: •••.••••••••••• 5-2
Folding Amplifier Array Simplified Schematic ••••••••••••••••• 5-25
Folding Amplifier Array Idealized Waveforms •••••••••••••••••• 5-26
Input Attenuator Buffer Simplified Schematic ••••••••••••••••• 5-37
LIS T
Table
F'lGUR.ES
. Title
Figure
1-1.
4-1.
4-2.
4-3.
4-4.
4-5.
4-6.
4-7.
4-8.
4-9.
4-10.
4-11.
4-12.
4-13.
4-14.
4-15.
4-16.
4-17.
4-18.
4-19.
4-20.
4-21.
4-22.
4-23.
5-1.
5-2.
5-3.
5-4.
OF
TAB L E S
0F
Title
Paye
1-1. 4500 Specifications==========eeeeeeeee •••••••••••••••••••••••• 1-4
ix
-4500 Service Manual
CHAPTER 1
GENERAL INFORMATION
INTRODUCTION
This manual provides detailed Theory of Operation, Alignment, Calibration, and
Maintenance procedures for the Gould Design.and Test Systems Division 4500
Di gi tal Storage Osc ill oscope.
The manual is organized as follows:
Chapter 1 provides a general introduction to the 4500 Digital
Storage Uscilloscope service manual including a general
description of the 4500 features and specifications.
Chapter 2 describes the performance verification procedure for
the 4500 and includes a list of recommended test equipment.
Chapter3 explains the operation of self-test,power-up and built-in
diagnostics for the 4500.
Chapter 4 contains detailed alignment and calibration procedures.
Chapter 5 contains the theory of operation at the block diagram level
followed bya detailed theory t.o t he com ponent 1eve 1 with
references to the schematics fot'each board.
Chapter 6contains the schematic drawings, list of materials, and
assembly drawings for each board.
GENERAl DESCRIPTION
The 4500 Digital Storage Oscilloscope, Figure 1-1, is
based, dual-channel digital storage oscilloscope with
35-MHz bandwidth. The 4500 provides fast, repeatable
Data acquisitions are easily manipulated for accurate
an 8088 microprocessor8-bit resolution and a
waveform recording.
measurement.
The 4500 can be used as a stand-alone instrument or as part of a computer
controlled system. The GPIB and RS-232 interfaces allow the 4500 to be
completely controlled from another computer or 4500. The Interface board
contains direct memory access circuits that permit direct external access to
data in the fast store memories.
1-1
4500 Servi£e Manual
FEATURES OF THE 4500
User-Friendly Front Panel - The 4500- is controlled like a conventional
oscilloscope using volts and seconds/division terminology. RocKer
switches are used to set the most frequently chan.ged parameters. A:
master menu allows selection of a variety of specific control options,
thereby reducing the number of front panel controls.
Easy to Read Displays - The CRT display is vertically-scanned raster type
with resolution of 512 by 500. Selections allow display of status
parameters only and trace displays with- or- without m~nu and graticule.
Auto Setup - When this feature 15 selected, the- 4500 analyzes the input
signals and automa~ically sets th~ ~isplay parameters- to produce the
best possible trace di~play.
Data Acquisition - The 4500 samples, digitizes, -and stores 1000 discrete
points (2000 in single channel mode) on each input channel at sampling
rates up to 100 MHz.
-
-
Buffer Memori es _- Two buffer memori es can be used as reference memori es
for ac~uired ~ignals.
Cursors-Two c~rsors ian be ~sed to make voltage, time, and frequency
measurements of -a d-i spl ayed waveform.
Display Interpolators - The _4-500 offers sine, linear, and dots display
interpolators.
5i gna 1 Averagi"g - For measurement of repet it i ve waveforms ina no; sy
environment, the user may select signal averaging to improve the signal
to noi se rat i 0 by up to 16 dB.
Roll Mode - For waveforms with slow sweep speed, Roll mode shows the
acquired waveform rolling across the display much like an oscillographic
recorder.
Scroll Mode - Sequential acquisitions are automatically displayed below
previous acquisitions when scroll mode is selected.
1 VS 2 Mode - The trace 1 vs 2 mode shows data samples of the two signal
traces in X vs Y format.
Setup Store and Recall - Up to five setup states can be stored in nonvolatile memory for later recall.
Automatic Calibration - Measurement precision and accuracy are maintained
through periodic internal calibration of the analog-to-digital converters.
1-3
.
.
4500 Service Manual
SPECIFICATIONS
Table 1-1 presents theelect~ical ~ndenvironmental specifications for the
4500 Digital Storage Oscill~sccipe •.
.Table 1-1. 4500 Specifications
PARAMETER
SPECIFICATION
Channel A and B Inputs
.
.
Input
Imp~dance;
all ranges;
1 Mohm +1% in parallel with
30 pF +5%.
Input and Offset Voltage Ranges:
Sensitivity
1 LSB
Recorded Full
Offset
Offset
Volts/Div Resolution Scale Range Resolution Voltage Range
.\
1 thru 10 mV
20 mV
50 mV
100 mV
200 mV
500 mV
1 V
2V
5V
0.31
0.62
1.56
3.23
6.25
15.60
31.30
62.50
156.00
mV
mV
mV
mV
mV
mV
mV
mV
mV
80
160
400
800
1.6
4.0
H.O
16.0
40.0
mV
mV
mV
mV
V
V
V
V
V
2
4
10
20
40
100
200
400
1
+2
+2
+2
+20
+20
+20
+64
+64
.:t.64
mV
mV
mV
mV
mV
mV
mV
mV
V
Amplifier Handwidth:
-3 dB at 35 MHz.
ADC Resolution:
8 bits; 1 part in 256.
Input Coupling:
DC, AC (AC -3 dB at
Channel Isolation:
-60 dB at 35 MHz.
2~5
V
V
V
V
V
V
V
V
V
HZ).
Maximum Input Voltage Without Damage:
(DC + Peak AC): +500 V at 1 kHz or less.
Noise:
< 0.2% of full scale RMS.
DC Differential Nonlinearity:
~~O.2%
DC Non Linearity:
< +0.4% of offset +0.2% of offset range.
1-4
of full scale
~1/2
LSB.
·A500
Service Manual
Table 1-1. 4500 Specifications {Continued) ..
SPEciFICATION
PARAMETER
Channel A and B Inputs (Continued)
Absolute Offset Voltage Accuracy:
(No offset applied)
+0.5% of offset +0.2% of offset range.
Absolute Voltage Accuracy:
DC to 1 MHz +1% of reading
+0.4% of recorded full scale range.
1 MHz to 2· MHz +2% of reading
+0.8% of recorded full scale range.
of
2 MHz to 10 MHz +5%
readi ng .
.:!J .6% of recorded fu 11 scale range •.
Overall AC Performance:
Complete system AC performance, including ADC.
Procedure and equipment lists required to
. replicate these tests are available from
Gould upon request.
.
Effective resolution of a half scale sinusoid single sweep recording:
Signal
Frequency
Effective
Bits
1 MHz
MHz
10 MHz
20 MHz
35 MHz
7 .1
6.6
6.1
5.3
5.1
5
Dynamic
Range
42.7
39.7
36.7
31.9
30.7
dB
dB
dB
dB
dB
Transient Response: Relative error after 3/4 full scale step.
Time After Step
After 20 nsec
After 40 nsec
Relative Error
o to -3%
2:.1%
Auto Calibration: Performed every 60 seconds except when the 4500 is armed.
Arm:
Selectable Source: External, Manual, Auto, or Hold.
External Arm Signal: Negative going TTL edge.
Minimum Pulse Width for Certain Detection: 20 nsec at normal TTL levels.
1-5
4500 Servi ce Manua (
Table 1-1. 4500 Specifications (Continued)
PARAMETER
SPEC! FICAT I.ON
Trigger
Selectable Source: Charinel A, Channel B, External, A auto,
B auto, External auto, Line, or Manual.
Coupling:
OC/AC(-3 dB at 2.5 Hz).
Filtering:
Hi pass -3 dB at 1 kHz;
Low pass - 3 dB at 15 kHz.
Slope/Mode: Selectable eithe~ when the source signal passes through
a 'level, or when the source signal leaves or enters a
band of ~ trigger level, centered around the
offset value (band trigger).
Level:
Sensitivity Trigger Voltage' Trigger:
Volts/Division
Range
. Resolution
1 mV thru 10mV
20 mV
50 mV
100 mV
200 mV
500 mV
1 V
2 V
5 V
+250 mV
+500 mV
~1.2b V
+2.50 V
~5.00 V
~12.5 V
+25.0 V
+50.0 V
+64.0 V
2
4
10
20
40
100
200
400
1
mV
mV
mV
mV
mV
mV
mV
mV
V
Delay: 0 to 1 screen of pre trigger, U to 10 screens of post trigger,
or 200 seconds, whichever is less. (Unexpanded displays.)
Trigger Output: TTL level output on rear panel, positive going for
trigger, negative going for delayed trigger.
External Trigger: Accepts analog or digital signal. 1 Mohm in parallel
~ith 30 pF input impedance.
Level adjustable in range
~.O V, in 4U mV steps.
Maximum input +500 V.
1-6
4500 Service Manual
Table 1-1. 4500 Specifications (Continued)
SPECIFICATION
PARAMETER
Trigger (Continued)
Minimum (Internal/External) Pulse Wi·dth for Certain Detection:
20 nsec when overdrive is 10 mV or 5% of trigger voltage range,
whichever is greater.
Maximum Delay from Trigger to First Sample: 70 nsec + one sample period.
Trigger Jitter: +2 samples interval.s worst case;
T1 typical for 0 to 1 screen of delay.
Sweep
Sample Intervals: 10 nsec to 100 msec/sample internally generated in a 1-2-4
sequence. Continuously variable to 20 nsec/sample with
external clock generator.
Sample Interval
Accur~cy:
100 MHz +0.01%
Total Sweep Time:
Single Channel: 2000 x nominal sample interval;
Dual Channel: 1000 x nominal sample interval.
Sweep Speeds:
Single Channel: 20 nsec/division to 10 sec/division in a 1-2-4 sequence.
(20 nsec/division to 1 usee/division are expanded sweep speeds.)
Dual Channel: 20 nsec/division to 10 sec/division in a 1-2-4 sequence.
(20 nsec/division to 500 nsec/division are expanded sweep speeds.)
Sweep Expansion:
Controlled by resetting sweep speed and trigger delay
after signal acquisition.
Mixed Sweep Speeds:
Sweep speed changes from ~re trigger to post trigger
sweep speed at the trigger point.
Clock Output:
ECl compatible; 100 MHz.
Clock ·Gate Input:
Eel compatible; 0 to 20 MHz.
External Clock Input: ECl compatible; continuous to 50 MHz.
Samples/Sweep:
1000 8-bit samples dual channel;
20UO 8-bit samples single channel.
1-7
" ,4500
'S~rvice
Ma.r.lUal
lable 1-1. 4500 Speci-fications (Continued)
PARAMETER
SPECIFICATION
.D1 sp.l ay
Size:.
. 9.S·cm.
high by 12.7 cm (5") wide.
(3.7~1I)
Vertical rastef.scan, .500 lines.
.
.
Resolution:' . 5UO· pOintshoriz'ontally;5l2 points vertically •
Grat ieu le:'
.8. v~rti-tal by' 10· horizontal divisions internally generated.
Characters :'.
.25 lines. each of 62 characters displayable internally or
".
.
.
.
.
via digital. interface.
characte'r available.
Int·eflsity:·-
Upper case or lower case special
. Adju.stable from front panel control.
~umb~~.6f d9tS:' (On vertical scan line) 4 maximum; 1 per vertical quadrant •
. : Li-near-i·ty :
An~ 109
Better than .:!:.1%.
PIot·t·er 'I nterface (Standard)
Outputs: ..
X or Y:
Pen] i ft:
Speeds:
o to
+10 V Full Scale
TTL output level during valid outputs on X and Y.
Polarity selectable.
Selectable X ramp outputs from 1 sec to 100 sec per output
trace. Selectable in 1-2-5 sequence.
Inter·f aces
Interfaces'consist of an IEEE-488 1978 interface, and RS-232C interface, a
fast access digital interface, and a fast access analog interface~
IEEE-488 1978 Interface: This interface facilitates complete Talk/Listen
interfacing of the 4500 to a controller, printer, or another 4500. The
. following specifies the 4500 GPIB capabilities:
SH1
AH1
T5
L4
SRI
RL1
PPO
DC1
DT1
CO
Source Handshake, complete capability
Acceptor Handshake, complete capability
Basic Talker, serial poll, talk only mode, unaddress if mla
Basic Listener, unaddress if mta
Service Requests complete capability
Remote/Local, complete capability
Parallel Poll, no capability
Device Clear, complete capability
Device Trigger, complete capability
Controller, no capability
1-8
450U Service Manual
Table 1-1.
4500 Specifications (Continued)
SPECIFICAtION
PARAMETER
.'
~Interfaces
(Continued)
RS-232C Interface:
This interface facilitates complete.S~nd/Re~eive
interfacing 'ofthe 4500 'ta a controller,' printer, or
" " .
another 4500.
Fast Access Digital Interface: This interfacefa'cilftates"'fast output of
stored waveforms. Data rates ,to~oo k byte's/second •.
Compatible with Digital Eq~ipment Corporatio~ DRII-B.·
DMA Interface.
. '..
.
.
.
Fast Analog Interface: This interface reconstructsstofed digital data
with a fast digital to analog conv~~ter at~rates' .
compatible with analog front ends ~f.signaT~v~rager~.'.
Floppy Disk Accessory
The floppy disk option is composed of a 5 1/4" single-sided, double-density".
floppy disk drive housed externally to the 4500. Power and communications
to and from the 45UO are via supplied cable.
Capacity: 40 records of both traces, refererice memories and related setup
parameters. Data can be transmitted to the floppy or' back to
the A, B, and reference memories in the 4500.
Probe Accessory
Tektronic 010-6108-03
Input Impedance:
10 Mohms in parallel with 13 pF.
Attenuation:
10 X
1-9
4~OU
Service Manual
Table 1-1.
4,560 Specl.fications (Continued)
PARAMETI:I<
, SPECIFICATIUN
Rack Mount, Kit·
U112~U293-10
Operating and
with drawer
s]jde~.
Stor~ge .Condjtjo~s:
, Spec i fi cat ions guaranteed from 1Uo to 3UoC and
le~s than 5 minutes after auto calibration.
Ope~~ting Tempe~a~ur~:
00 to 500C.
Sto~age.T~~perature:'
~hysi
-~50
to
+8~oC.
c,a.L Cha rac teri s tic s
Height:
;;
21 •b· cm (8.LII)
W'; dth:
44.:' cm (17.t>1I)
Length:
58.4 em (23.U II )
Mass/Weight:
27.3 kg (6U lbs)
Power'
Input Power:
350 watts maximum.
Frequency:
48 to 66 Hz •
. Voltaye RMS:
90 to 132 V; 184 to 264 V.
turrent RMS:
3.8 A at 92 V.
Fuse:
6 A at 11U V nominal.
3 A at 220 V nominal.
Cable:
2 m (78
11
)
long, 3-conduetor line cord.
l-1U
4500 Service Manual
.
CHAPTER 2
.
PERFORMANCE
YERIF.ICATION
.
-
INTRODUCTION
This chapter provides detailed performance verification procedures for the
Gould Design and Test Systems Division 4500 Qigital Storage Oscilloscope.
Incl uded are recommendat ions for test equ-i pment~ -.
~
RECOMMENDED TEST EQUIPMENT
1. The following test equipment is recommended for implementing the
performance verification procedure of this manual.
Tektronix model DM 50lA digital multimeter or equivalent.
Tektronix model DC 503A universal timer/counter or equivalerit; capableof measuring 100-MHz ECl signals with an accuracy of 0.01 percent~
Tektronix model SG 503 levelled sinewave oscillator or equivalent,_
capable of generating 1.2 V peak-to-peak sinewaves from 625 ~Htto' 35
MHZ. The s i newaves must not change amp 1i tude as frequency is changed.
Tektronix model FG 5U2 function generator or equivalent, capable of
generating ECl level signals at a frequency of 500 kHz.
Tektronix model TM 504 mainframe (to contain and power the above).
Tektronix model 485 oscilloscope or equivalent, capable of measuring
lOO-MHz ECl signals.
Wavetek model 142 waveform generator or equivalent, capable of
generating 8 V peak-to-peak sinewaves from 2.5 Hz to 50 kHz.
Xl test probe.
Two 50 ohm terminators (BNC female input, BNC male output.)
Three BNC to BNC cables (BNC male connectors on both ends.)
BNC tee coupler. (Two BNC females in and one BNC male out.)
2-1
4500 Service Manual
2 • For performi ng ,ca'1 i brati pn' of the 4500, the fo 11 owi ng test equi pment is
recommended in add it ion ,to the above '.
Tektronix model PG 506
Extender
board~
calib~ation
extension coaxial
Part Nuniber
0285;..0384-10
0285-0235-10
0285-0235-20
0285-0240-10
02a5-0165-10
0285-0383-10
0285-0109-10
generator.
,cabl~,
and input standardizer set.
Description
Extender Bbard Set (includes the following six items)
Extender for Floppy Disk Controller or Interface board
'Extender for MPU or CRT Driver board
Extender for the Sweep and Record board
Extender for either ADC board
Extension coaxial cable used when extending an ADC board
30 pF Input Standardizer
PERFORMANCE VERIFICATION PROCEDURE
1.'The self test procedures that make up the first part of this performance
verification procedure exercise most of the 4500 hardware. If all self test
procedures pass, a high degree of confidence in 4500 performance may be realized. Other tests are added to verify performance of 4500 functions and
specifications not tested by self tests. There are some system functions,
such as the external interfaces, that are not tested in this performance
verification procedure. This is due to the need for specialized test equipment and software to operate it.
A quick test of system operation can be performed with only a Xl test probe by
running the self tests. These are described in steps 2 through 13. Additional information, and photographs of self test results, are shown in Chapter 7
of the 4500 Digital Storage Oscilloscope Users Manual, Publications Number
028f>-0212-10 o
Note that the 4500 Auto Setup function is used extensively in this procedure.
Auto Setup is used to achieve 4500 settings that are required for the
tests that specify it.
,Instrument Wannup
2. Apply power to the 4500 and allow it to remain on for 20 minutes before
performing this procedure~
2-2
~500 Serv~ce
Manual
Initiating Self Test
3. To initiate self test, depress the following
fr~ilt
panel keys:
AUTO SETUP
MASTER MENU
TEST, menu key C
The sel f test menu should appear •. Perform each test and veri fy proper operation as described following.
Sweep and Record Self Test
4. Depress:
SWPjREC, menu key I
The CRT screen will display a GOOD or BAD indication.
be GOOD.
All indications should
Trigger Self Test
5. From the SELF TEST menu depress:
TRIGGER, menu key 2
The screen will display a GOOD or BAD indication for channel A and channel B.
All indications should be GOOD.
Attenuator Self Test
6. From the SELF TEST MENU depress:
ATTN, menu key 3
Connect:
a Xl probe to the channel A input BNC connector
probe ground to front panel ground test point
probe tip to the front panel CAL test point
Depress:
menu key C
The screen will display a GOOD or BAD indication.
GOOD.
The indication should be
Perform the same test except with the Xl probe connected to the channel B
input BNC connector. The indication should again be GOOD.
2-3
4500 Service Manuil
. Channel A APC Self Test·
7. From the SELF TEST mehu depress:
·A ADC, menu key 4
The screen willdisplay"an expected ramp (~ioped line) and an actual ramp.
major difference between the two ramps shQuld be observed.
No
Channel A DNl Self Test
8. From the SELF TEST menu depress:
A DNL, menu key 5
"
"
The di sp 1ay wi 11 show a hi stogram of the different i a1 non 1i neari ty of the ADC
for channel. A averaged over a large number of acquisitions.
There are two software versions of this test. In some 4500s (software
versions 3A and earlier), the DNL test is performed contfnuously with the
results appearing on the display approximately two times a second. In other
4500s (software versions 4~ and later), the test is performed once each time
the A DNL key 1.s depressed. The result takes approximately 12 seconds to
appear on the display. In the faster version, less averaging is done and more
noise (peak-to-peak variation) is apparent in the result. In the slower
version, more averaging is done and the result shows less peak-to-peak
variation. The DNL test is designed to ensure a differential nonlinearity of
+/- one ha 1f LSB.
In the fast version, an acceptable result will show no more than two amplitude
peaks greater than +/- 1 division at anyone waveform point within five
successive tests.
In the slow version an acceptable DNL result will show a histogram on the zero
line +/- 1 division. There should be no amplitude peaks greater than +/- 1
division. An example of the slow test is shown in the ADC Calibration
Procedure (Figure 4-23).
Channel 8 ADC Self Test
9. From the SELF TEST menu depress:
B ADC, menu key 6
The screen will display an expected ramp (sloped line) and an actual ramp.
major difference between the two ramps should be observed.
2-4
No
4500 Service Manual
Channel B DNL Self Test
10. From the SELF TEST menu depress:
B DNL, menu key 7
Interpret the results as discussed
in~tep
8 above.
AUTO CAl Self Test
11. From the SELF TEST menu depress:.
CAL, menu key 8
All CAL correction factors must be in the range of -128 to +127, or
calibration has changed more than AUTO CAL can compensate for. When first
calibrated, a 4500 will typically exhibit all its CAL correction fa~tors
within the range of 0 to +/- 30.
To terminate the AUTO CAL display depress:
HALT, menu key C
Keyboard Self Test
12. From the SELF TEST menu depress:
KEYBOARD, menu key 9
The display will show 8 columns and 16 rows of zeros, and the key clicker
will emit a constant buzz. Depress each front panel key and observe that a
single 1 appears on the display in place of one of the zeros. Depress each
rocker switch and observe that as the rocker switch is depressed, first a
single 1 and then two lis will appear in place of zeros on the display.
Confirm that both a single, and a double 1 may be easily obtained. Test each
rocker in both directions (up and down, or left and right).
To terminate the KEYBOARD test:
depress HALT, menu key C
2-5
4500 Service Manual
MPuicRT Self Test
13. From the SELF TEST menu depress:,
MPU/CRT) menu key A
The sc~een will display the software revision; all characters and symbols used
i n4500 di sp 1ays,; and all vert i ca'l 1i ne patterns used to generate grat i cu1 es,
cursors, 'and the trigger line. The 4500 Digital Storage Oscilloscope Users
Manual contains a picture of this display.
Input' Impedance
14. Depress:
MASTER MENU
CHNL A, menu key 4
DC, menu key 2, to set the channel A input coupling to DC
Depress:
, MASTER MENU
CHNL B, menu key 5
DC, menu key 2, to set the channel B input coupling to DC
Depress:
MASTER MENU
TRIG FLT, menu key 7
DC, menu key 5, to set the trigger input coupling to DC
Set:
CHANNEL A SENSITIVITY to 0.01 V/DIV
CHANNEL B SENSITIVITY to 0.01 V/DIV
Using a DVM measure the input impedance of the channel A, the channel B, and
the external trigger front panel inputs. Do this by measuring across the
input BNC connectors. Each input should measure 1 Megohm +/- 1%.
Set:
CHANNEL A SENSITIVITY to 0.1 V/DIV
CHANNEL B SENSITIVITY to 0.1 V/DIV
Measure the input impedance of channel A and channel B again.
impedance should be 1 Megohm +/- 1%.
The input
Set:
CHANNEL A SENSITIVITY to 1 V/DIV
CHANNEL B SENSITIVITY to 1 V/DIV
Measure the input impedance of channel A and channel B again.
impedance should be 1 Megohm +/- 1%.
2-6
The input
'4500 Service Manual-
Front Panel Test Points
15. Connect:
a Xl probe to the channel A input BNC connector,
probe ground to the front panel ground test point
probe tip to the front panel CAL test point,
Depress:
MASTER menu key
CAL key located just above the CAL test point'
CAL A PROBE, menu key A
The display should show that a Xl type probe has been detected and that the
probe error factor is within +/- 0.30%.
Connect:
probe ground to the front panel ground test point
probe tip to the front panel squarewave test point
Depress:
AUTO SETUP key
The display should show the test point squarewave.
Depress:
MASTER MENU key
F(CRSR), menu key 9
V(M), menu key 2 to enable voltage measurement using the major cursor
Depress:
ARM HOLD key to stop acquisition
A stable squarewave should appear on the display. Move the major cursor and
note the display readout of voltage at the major cursor position. Verify that
at the top of the squarewave the voltage is 3.3 +/- 0.4 V. Verify that at
the bottom of the squarewave the voltage is 0 +/- 0.4 V. At the rising and
falling edges of the squarewave there should not be any overshoot greater than
0.5 divisions.
2-7
4bOO Service ManuaJ
. Input 'Noise and' Offset~ Dua~l Swe~p .Speed Switchover
16. Ground both· channel ·inputs uSi.ng
terminators.
eith~~ ~horting
BNC plugs or 50 ohm
Depress:
AUTO SETUP key
Set:
CHANNEL A SENSITIVITY
CHA-NNEL A OFFSET to 0
CHANNELB SENSITIVITY
CHANNEL B OFFSET-to'O
to 0.001 V/DIV
V
to 0.001 V/DIV
V
Each displayed trace should occupy four or less different voltage levels
have an ~mplitudeless than or equal to 1 division peak-to-peak). Each
trace snould be centered within its half of the display screen~ plus or minus
1 division.
.(i.e.~
Set:
PRE TRIGGER SWEEP speed to 100 uS/DIY
POST TRIGGER SWEEP speed to 1 uS/DIY
Depress:
MASTER MENU key
AVG. CAL~ menu key 8
16~ menu key 3
To speed up acquisition ensure that PART-SUM is off (use menu key 7 to turn
partial summing off if it is on).
Set:
TRIGGER DELAY to zero
Note any voltage step in the waveform at the trigger line (the time of
transition between the pre trigger and post trigger sweep speeds). The step
size must not exceed one and one half divisions (1.5 mY).
17. Repeat step 16~ except with a pre trigger sweep speed of 1
post trigger sweep speed of 100 uS/DIVe
2-8
uS/DIV~
and a
4500 Service Manual
Channe1 A Input Coup1i ng, Tri gger Coup1i rig, a~d' !·ri g9~r 51 ope· ..
18. Remove all shorting plugs or 50 ohm
connectors.
termin~tors
from the front panel ·BNC
Depres.s:
AUTO SETUP key
MASTER MENU key
TRIG SRC, menu key 6
A, menu key 1, to select channel Aas the tri"gger source
Set:
CHANNEL A SENSITIVITY to 1VjDIV
POST TRIGGER SWEEP speed to 100 mSjDIV
TRIGGER LEVEL to 0 V
Apply a 2.5-Hz sinewave (a sinewave with a 4 division period) to the.chann~l A
input. Using the amplitude control on the sinewave generator adjust th~ ·inpOt
amplitude for 6 divisions peak-to-peak on the display.
Depress:
MASTER MENU key
CHNL A, menu key 4
Change between AC and DC coupl i ng usi ng menu keys 1 and 2. Veri fy that the
amplitude of the displayed sinewave changes to 4.2 +j- 0.5 divisions peak to
peak when AC coupling is active, and back to 6 divisions peak-to-peak when DC
coupling is active. Leave the coupling set on DC.
Depress:
MASTER MENU key
TRIG FLT, menu key 7
Change the trigger input coupling between DC and AC using menu keys 5 and 1.
Verify that the waveform shifts on the display one half division to the right
when coupling is changed from DC to AC, and that the display shifts one half
division to the left when the coupling is changed from AC to DC.
2-9
·
4~OO
Service Manual
Channel.8 In.put Coupling, Trigger Coupling,and Trigger Slope
19. Set:
CHANNEL B SENSITIVITY to 1 V/DIV
POST TRIGGER SWEEP speed to 100 mS/DIV
PRE TRIGGER SWEEP off
Depress:
MASTER MENU key
TRIG SRC, menu key 6
B, using menu key 2
Apply a 2.5-Hz sinewave (a sinewave with a 4 division period) to the channel B
input. Using the amplitude control on the sinewave generator adjust the input
amplitude for 6 divisions peak-to-peak on the display.
Depress:
MASTER MENU
CHNL B, using menu key 5
Chanye between AC and DC coupling using menu keys 1 and 2. Verify that the
amplitude of the displayed sinewave changes to 4.2 +/- 0.5 divisions peak-to
-peak when AC coupling is active, and back to 6 divisions peak-to-peak when
DC coupling is active. Leave the coupling set on DC.
Depress:
MASTER MENU key
TRIG FLT, menu key 7
Change the trigger input coupling between DC and AC using menu keys 5 and 1.
Verify that the waveform shifts on the display one half division to the right
when coupling is changed from DC to AC, and that the display shifts one half
division to the left when the coupling is changed from AC to DC.
External Trigger Coupling and Trigger Slope
20. Leave the 4500 set up as it was at the end of step 19. Leave the 2.5-Hz
sinewave connected to the channel B BNC connector, but simultaneously connect
this sinewave to the external trigger input.
Depress:
MASTER MENU
TRIG SRC, menu key 6
Set:
TRIGGER LEVEL to 0 V
2-10
450U Service Manual
Depress:
MASTER MENU
TRIG FLT, menu key 7
Change the trigger input coupling between DC to AC using menu keys 5 and 1.
Verify that the waveform shifts on the display one half division to the right
when coupling is changed from DC to AC, and that the display shifts one half
division to the left when the coupling is changed from AC to DC.
Change the trigger slope between pas and NEG, using menu keys 7 and 8. Verify
that the slope of the waveform at the trigger line is positive when pas is
selected, and negative when NEG is selected. .
Trigger Filtering
21. Connect:
a I-kHz sinewave to the channel B input
Set:
CHANNEL A SENSITIVITY to IV/DIV
CHANNEL B SENSITIVITY to IV/DIV
POST TRIGGER SWEEP speed to 400 uS/DIV
PRE TRIGGER SWEEP speed to off
TRIGGER LEVEL to 0 V
Depress:
MASTER MENU
TRIG SRC, menu key 6
B, menu key 2
Using the amplitude control on the sinewave generator adjust the input
amplitude for 6 divisions peak-to-peak on the display.
Depress:
MASTER MENU
TRIG FLT, menu key 7
Change the trigger coupling from DC, to AC HIPAS using menu key 2, and back to
DC using menu 'key 5. The waveform should shift one half division to the right
when AC HIPAS is selected, and one half division to the left when DC is
selected.
Set:
the sinewave frequency to 15 kHz
the POST TRIGGER SWEEP speed to 20 uS/UIV
2-11
4500 Service Manual
"
""
" Adjust the sineWave amplitude so the displayed waveform is 6 divisions peak
-to";'peak. Change the t r", gger coup 1i ng from DC, to AC LOPAS us i ng menu key 3,
and back to DC using menu key 5. "The waveform should shift one half division
to the right when AC LOPAS is~elected, and one half division to the left when
DC is selected. Change the trigger coupling from DC, to DC LOPAS using menu
key 4, and back to DC using menu key 5. The waveform should shift one half
division to the right when DC LOPAS· is selected, and one half division to the
1eft when DC is selected. Repeat" th"i s step except connect the s i newave to the
chann~lA" input and select trigger source A.
Line Triggering
22. Leave the unit set up as it was at the end of step 21.
Depress:
MASTER MENU
TRIG SRC, menu key 6
LINE, menu key 7
Verify that the 4500 is triggering by noting a continuous acquisition and
display of the 15-kHz sinewave. The line trigger will not be synchronous with
the I5-kHz sinewave and the waveform should change its position on the display
at the end of each acquisition.
Manual Triggering
23. Leave the unit set up as it was at the end of step 22.
Depress:
MASTER MENU
TRIG SRC, menu key 6
MANUAL, menu key 8
The 4500 should stop triggering and no new acquisitions nor display update
should occur.
Depress:
MANUAL trigger key located above the external trigger input connector
A single acquisition and a new display of the 15-kHz sinewave should occur.
2-12
·4~OO
Service Manual
Input Bandwidth
24. Set:
CHANNEL A SENSITIVITY to 0.2 V/div
CHANNEL A OFFSET to 0 V
.
CHANNEL B SENSITIVITY to 0.2 V/DIV
CHANNEL B OFFSET to 0 V
POST TRIGGER SWEEP speed to 400 nS/div
PRE TRIGGER SWEEP speed to off
TRIGGER LEVEL to 0 volts
Depress:
MASTER MENU;
TRIG SRC, menu key 6
A/AUTO, menu key 4
Connect to channel A input:
a sinewave of approximately 625 kHz (1.6 uS period).
Adjust the sinewave's amplitude to 6 divisions peak-to-peak as shown on the
4500 display for channel A. Change the sinewave frequency to 35 MHz. Ensure
that the sinewave generator does not change the amplitude of its output
when its frequency is changed.
The 4500 display for channel A should now show a waveform that is many cycles
of sinewave. The amplitude of the sinewave should be 4.3 to 5.7 divisions
peak-to-peak.
Depress:
MASTER MENU;
TRIG SRC, menu key 6
B/AUTO, menu key 5
Connect to channel B input:
a sinewave of approximately 625 kHz (1.6 uS period).
Adjust the sinewave's amplitude to 6 divisions peak-to-peak as shown on the
4500 display. Change the sinewave frequency to 35 MHz. Ensure that the
sinewave generator used does not change the amplitude of its output when its
frequency is changed.
The 4500 display for channel B should now show a sinewave of 4.3 to
divisions peak-to-peak.
2-13
~.7
4~00
Service Manual
,Channel 'Isolation
CHANNEL A SENSITIVITY to 1 V/DIV '
CHANNEL B SENSITIVITY to 0.001 V/DIV
CHANNEL B OFFSET to 0 '
'
POST TRIGGER SWEEP'sp~ed to 40 nS/DIV
Input a 3~-MHz sinewave to channel A and adjust the sinewave input amplitude
for'5,V peak-to-peak. Ground the channel 8 input with a BNC shorting
connector or a 50 ohm terminator. Verify that any signal appearing on the
channel B display is less than 5 divisions peak-to-peak.
Set~
CHANNEL B SENSITIVITY to 1 V/DIV
CHANNEL A SENSITIVITY to 0.001 V/DIV
CHANNEL B OFFSET to a
POST TRIGGER SWEEP speed to 40 nS/DIV
Input a 35-MHz sinewave to channel B and adjust the sinewave input amplitude
for 5 V peak-to-peak. Ground the channel A input with a BNC shorting
connector or a 50 ohm terminator. Verify that any signal appearing on the
channel A display is less than 5 divisions peak-to-peak.
Without changing the input amplitude of the 35-MHz sinewave connect this
, signal to the external trigger input.
Depress:
MASTER MENU
TRIG SRC, menu key 6
EXT, menu key 3
Set:
CHANNEL
CHANNEL
CHANNEL
CHANNEL
A SENSITIVITY
A OFFSET to 0
B SENSITIVITY
B OFFSET to a
to 0.001 V/DIV
V
to 0.001 V/DIV
V
Short both the channel A and channel B inputs with shorting plugs or 50 ohm
terminators. Any signal appearing on the channel A or channel B display
should be less than 5 divisions peak-to-peak.
2-14
4500 Service Man~ar
Plotter Outputs
26. Apply a squarewave to the the channeJ A input and depress AUTO SETUP. .
Set an oscilloscope to X-V mode and conne~t·the rear panel PLUT X and PLOT Y
outputs to the X and Y inputs of the oscilloscope. Set the X any Y sensitivities of the oscilloscope to 5 V/DIV. Using the position controls on the
oscilloscope set its zero volt reference pointto·the center of its displ.ay
screen.
Depress:
MASTER MENU
PLOTTER, menu key A
MAX, MAX, menu key 2
The oscilloscope display should show a dot at the X=10 V, Y=10 V point.
Depress:
SPEED 1, menu key 5
PLOT, menu key 1
Acquisitions should temporarily halt and the oscilloscope should draw the same
waveform that is on the 4500 display.
Select different plotter speeds using menu keys 5 through B. After each speed
change press PLOT, menu key 1. The oscilloscope should draw the same waveform
as on the 4500 display, but with increasing speed as the menu selected speed
number is increased.
Depress MASTER MENU to leave the plotter mode.
Trigger Output
27. Attach a cable from the 4500 channel A input to the rear panel TRIGGER OUT
connector.
Depress:
MASTER MENU
TRIG SRC, menu key 6
AiAUTO, menu key 4
AUTO ARM key
AUTO SETUP key
The 4500 display should show a waveform that is low before the trigger line
and high after the trigger line. Depress the TRIGGER DELAY rocker switch and
verify that the rising edge of the waveform follows the trigger line on the
display.
2-15
4500 Service Manual'
. Clock Ou1;put
28. With an 'oscilfoscope,set to h'ave a 50 ohm input impedance verify that the
signal on the rear panel, CLOCK OUT .connector is a lOU-MHz ECl signal. Measure
the frequency of, thi s s'i gna 1 . with a frequency counter. The frequency shoul d
bel 00 +/ - 0.01 MHz.
.
Clock Gate
In~ut
,29. Apply an
~
volt peak-to-peak, 50-kHz sinewave to both channels of the 450U.
Depress:
AUTO SETUP
Set:
CHANNEL A SENSITIVITY to 1 V/DIV
CHANNEL B SENSITIVITY to 1 V/DIV
POST TRIGGER SWEEP speed to 1 uS/DIV
Apply a 5UO-kHz, ECl level squarewave to the rear panel CLOCK GATE connector.
Verify that the waveforms displayed are portions of sinewaves with steps in
them at each division. Ensure that there are no overshoot or undershoot
spikes at the tops and bottoms of each step.
While observing the display, slowly vary the frequency of the 500-kHz signal
throughout the range of approximately 250 kHz to 1 MHz. There should be no
overshoot or undershoot spikes at the top or bottom of each step. Note that
the steps change shape as the frequency is changed.
Display Intensity Control
30. Rotate the front panel INTENSITY control clockwise.
intensity goes from barely visible to full brightness.
Ensure that the display
CMOS Memory Data Retention Test
31. Write down the sensitivity and offset voltage of channel A and channel B.
Write down the pre trigger and post trigger sweep speed. Enter a nonzero
trigger delay and write down this setting. Turn off and then power up the
4500 several times, and then recheck the settings of the above parameters.
Ensure CMOS memory has retained its data by noting that these parameters are
the same as they were before power was turned off.
2-16
4500 Service Manual
Floppj'DiSK Drive
32. The floppy disk drive is an option •. If it is not present, skip this step.
Connect any convenient waveform to the cha~n~l ·A and cha~nel~inputse
Depress:
AUTO SETUP
The waveform should now be displayed. Place a diskett~ 1n the disk drive.
Be sure that the diskette does not have a write protect tab on it.
Format the disk by depressing:
MASTER MENU
I/O, menu key B
DISK, menu key B
FORMAT, menu key 1
CONFIRM, menu key C
The disk drive light should illuminate. When the light goes off, formatting
is complete. If an error message appears, try another diskette to determine
if the fault is with the disk or with the drive&
Select and write to file 40 by depressing:
FILE, menu key 2
4~ menu key 4
0, menu key A
ENTER, menu key C
WRITE, menu key 4
CONFIRM, menu key C
The disk drive light should illuminate to indicate that the write operation to
FILE 40 is occurring. When the light turns off the write operation is
complete.
Select and write to file 1 by depressing:
FILE, menu key 2
1, menu key 1
ENTER, menu key C
WRITE, menu key 4
CONFIRM, menu key C
2-17
4500 Service Manual
Jh~.disk
drive light should~illumin ~e tb.·indicate that the write operation to
FILE 1 is occurring. Wheri the ·1~9b~ turns off the write operation is complete.
Change the input signal·· to a di ff.erent waveform so the next recordi ng appears
different from the recordin~s stored on disk.
Depress: AUTO SETUP
Observe the recording of the present input signal.
Select and read file 40 by depressing:
FILE, menu key 2
4, menu key 4
. 0, menu key A
ENTER, menu key C
READ, menu key 5
. CONFIRM, menu key C
After the disk is read the display should show the initial waveform that was
stored on disk.
Depress: SINGLE ARM
The display should show the current input signal.
Select and read file 1 by depressing:
FILE, menu key 2
1, menu key 1
ENTEH, menu key C
READ, menu key 5
CONFIRM, menu key C
After the disk is read the display should show the initial waveform that was
stored on disk.
Depress: Auto File, menu key 3
AUTO ARM
The 4~OO should automatically take recordings and store them on disk in each
of the 40 files. The file number can be observed incrementing on the menu
display. The 4500 will stop recording after file 40.
2-18
4500
Disconnect the input signal from
th~~hanne1
A and
~hanne1·
Se~vice
Manual
B inputs.
Depress: AUTO SETUP
The display should now show only random noise is being recorded.
Select and read file 25 by depressing:
FILE, menu key 2
2, menu key 2
5, menu key 5
ENTER, menu key C
READ, menu key 5
CONFIRM, menu key C
After file 25 is read the display should show the signal that was recorded
prior to its being disconnected from the inputs.
Interface Option Tests
33. Procedures for testing the GPIB, RS-232, and DMA interface circuits are not
included here. These interfaces may be tested by connecting and operating the
external interface devices as described in the 4500 Digital Storage
Osc ill oscape User- s manual.
2-19
4500
CHAPTER 3
Servic~ Manual~
DIAGNOSTICS·
INTRODUCTION
This chapter provides detailed diagnostic procedures for the Gould Design and
Test Systems Division 4500 Digital Storage Oscilloscope.
The 4500 uses Self-diagnostics to verify proper system operation without the
need for specialized test equipment. Three types of diagriostics are described
in this manual:
(1) Self-Test Diagnostics,
(2) Power Up Diagnostics, and
(3) Built-In Diagnostics.
The Self-Test Diagnostics are accessible by the user and are mostly self~·
explanatory. These diagnostics are explained in Chapter 2, Performance
Verification Procedure and also in Chapter 7 of the 4500 Digital Storage
Oscilloscope Userls Manual. The Power-Up Diagnostics and the Built-In
Diagnostics are described in following paragraphs.
POWER UP DIAGNOSTICS
Each time the system is turned on, it will run some basic power-up diagnostics. These diagnostics will also start again when the RESET switch on the
MPU board is pressed. These diagnostics will only operate when the test
selection switches on the MPU board are set for a normal operating mode.
Refer to the 4500 Built-in Diagnostics section for switch selection descriptions.
Four LEDls on the MPU board indicate status of the power-up diagnostics. Each
LED extinguishes when that diagnostic test passes. If a failure occurs, the
system will lock up and that testis LED will remain lit.
LED #1 -
Tests basic CPU functions including interrupt checks
and initiation of the other power-up diagnostics.
LEO #2
Tests the EPROM checksums of the system software
located on the CRT Driver board.
LED #3 -
Tests the MPU RAMls for Read/Write errors.
LED #4 -
The system is checked to see if the interface or floppy
disk option is present. Auto Cal is also initialized,
and if the system does not complete the recording
process this test will fail.
3-1
4500' Service Manual,
4500 BUILT-IN DIAGNOSTICS
1~'rhe following,diagnostics reside in ROM and are an integral part of the
'450'0. A diagnostic ,is selected by setting the 8 position DIP switch on the
top of the MPU circuit board. The diagnostic is initiated by depressing the
reset switch next tri'the DIP switch or turning power on if the 4500 is off.
The necessary DIP switch settings to s~lect the various diagnostics are given
as two hexadecimal digits. These~digits represent eight bits, which in turn
represent thesett i ngs of the ei ght, s wi tches. The MSB represents s wi tch 8 and
the LSB -represents switch 1. ' A bi nary 0 represents a closed switch and a
binary 1 an open switch~ For ex'ample, in the case of diagnostic 07H (H
specifies hexadecimal) represents switches 1 to 3 open and switches 4 to 8
closed.
2. Switch,~ettings,O through 12H select diagnostics. Setting 7FH selects
normal 4500 operation, except with AUTO CAL disabled. Disabling AUTO CAL is
'necessary'when aligning the ADC. Setting FFH selects normal 4500 operation
, ~ith AUTO CAL enabled. The 4500 should be returned to the FFH setting after
'all testing operations are completed.
3. All diagnostics begin by clearing the CRT and then displaying a message
"DIAG nn", which shows the test being executed where nn represents the hexadecimal number of the diagnostic selected. Tests 03H (FILL SCREEN), 06H
(RAM TEST), and 07H (WRITE 16K) quickly write over this message as the memory
containing this message is tested.
4. Following is a quick reference to the available diagnostics. A more complete description of each is provided following this list:
OOH
01H
02H
03H
04H
05H
G6H
07H
08H
09H
OAH
OBH
OCH
OOH
OEH
OFH
10H
IIH
12H
Interrupt system test
Write any byte to any I/O address
~ead and display byte from any I/O address
Fill screen with byte from DIP switch
Trace generator test
Graticule generator test
Dynamic RAM and CMOS RAM test
Write to dynamic RAM (0 - 3FFFH)
Read from dynamic RAM (0 - 3FFFH)
Write to CMOS RAM (4000H - 40FFH)
Read from CMOS RAM (4000H - 40FFH)
Rotating LED pattern
Trigger level adjustment aid
Cal DAC adjustment aid
CRT alignment test pattern
CMOS RAM power down data retention test
Channel A alignment aid
Channel B alignment aid
ROM checksum test
3-2
· 450rr
Service
Manu~l
5. Diagnostic OOH -- Interrupt system test.
Provides the following display:
TIMER - - FRONT-END SPURIOUS
o
o
o LEVEL =
Enables interrupts, counts the number of interrupts of each kind that occur,
and displays these numbers. If interrupts are operating properly, the timer
interrupt should occur 50 times per second and no frorit-end or spurious inte~
rupts shoul d occur.
6. Diagnostic OIH -- Write any byte to any I/O address
Begins by writing OIH to port OIH. The value written is incremented indefinitely and written again to the same port at a frequency of approxiniately'
200 KHz. If the DIP switch is changed, the new value selects another I/O port.
address. This port is then written to, and the port address is displayed.
.
7. Diagnostic 02H -- Read and display byte from any I/O address
Begins by reading from port 02H and displaying the data read. If the DIP
switch is changed, the new setting selects another I/O port address. This
port number is shown on the display and this port is read from. The value
read is displayed.
8. Diagnostic 03H -- Fill screen with byte from DIP switch
Fills the display with a character selected by the DIP switch. When first
invoked, the character corresponding to 03H is displayed throughout the CRT
screen. Changing the DIP switch causes a new character corresponding to the
new DIP switch value to appear throughout the CRT screen.
9. Diagnostic 04H -- Trace generator test
Displays 4 traces on the CRT. All possible traces vaiues are attempted in an
incrementing sequence. Display should appear to be 4 horizontal lines rolling
upwards with some momentary vertical line flashes.
10. Diagnostic 05H -- Graticule generator test
When a graticule is drawn during 45UO operation, the display circuitry selects
the desired vertical line pattern to draw at each scanline from the graticule
ROM. The graticule generator test diagnostic reads each available pattern
from the graticule ROM and repeats the pattern on 8 adjacent scanlines, starting from the left side of the display screen.
3-3
4500
Servic~
Manual
11. Diagnostic 06H --
Dynamic'RA~
and CMOS RAM test
Performs a check of dynam1 c RAM and' CMOS RAM. Dynami c RAM res ides at addresses OOOOH through 3FFFH. CMOS RAM resid~s.at addresses 4000H through 40FFH.
The test fills the RAMS. with incrementing values while incrementing addresses.
The test reads the values back ~nd checks the value while decrementing
addresses. The value writt~n into the first address is then incremented and
the test repeated. If this procedur~ is performed for an extended period, the
test wri tes and checks every poss i b1e value at every address. However, most
failures appear ina short time. When an error occurs, the following message
j s dis played:
'
ERROR: AD DR xxxx WROTE: xx
READ: xx
,The address, the data value which should have been read, and the data value
actual.ly read,are shown. The processor then enters a loop which writes the
. value that failed to the address that failed and reads back data from this
address. 'This loop repeats indefinitely.
12. Diagnostic 07H -- Write to dynamic RAM
Writes 55H to the dynamic RAM memory at addresses OOOOH through 3FFFH.
locations are incremented and writing continues indefinitely.
Memory
13. Diagnostic 08H -- Read from dynamic RAM
Reads from the dynamic RAM memory at addresses OOOOH through 3FFFH. Memory
locations are incremented and reading continues indefinitely. No messages
other than the diagnostic number are displayed on the CRT.
14. Diagnostic 09H -- Write to CMOS RAM
Writes 55H to the CMOS RAM memory at addresses 4000H to 40FFH.
tions are incremented and writing continues indefinitely.
Memory loca-
15. Diagnostic OAH -- Read from CMOS RAM
Reads from the CMOS RAM memory at addresses 4000H through 40FFH. Memory
locations are incremented and reading continues indefinitely. No messages
other than the diagnostic number are displayed on the CRT.
16. Diagnostic OBH -- Rotating LED pattern
Iiiuminates LEO 1, LEU 2, LEO 3, and LED 4 individually in sequence with a
short pause between each LED.
3-4
4500 Service
~anual
17. Diagnostic OCH -- Trigger level· adjustment aid
Sets both analog trigger DACs to negative f~ll .scale by outputti~g the value
FFH to port 30H and port 40H, or to pos.itive ·full scale by outputting the.
val ue UOH to port 30H and port 40H.•. · Each time the MASTER menu key is depressed, the output value is changed and retransmitted. The current value is
displayed on the CRT.
18. Diagnostic ODH -- CAL DAC adjustment aid
Writes two different values to the DAC on· each ADC board that generates the.
voltage used during AUTO CAL. The DAC on 'ea~h ADt board also generates the
offset voltage when AUTO CAL is not operating. During this diagnostic, the
number 01 or 02 appears on the di spl aye When 01 is di spl ayed, theDAC is set·
to output +10 V. When 02 is displayed, the DAC is set to output -10 V. These
settings are used to adjust the DAC circuitry so the +10 V. a·nd ~10 V v~·lues
are within tolerance. The setting may be changed from +10·V to -10 V or from
-10 V to +10 V by depressi ng the MASTER MENU key on the front panel. The
voltage is measured on the ADC board at test point TP2.
19. Diagnostic OEH -- CRT alignment test pattern
Seventeen equally spaced vertical lines and thirteen equally spaced horizontal
lines are generated on the CRT. This test may be used as an alignment pattern
for adjusting the display.
20. Diagnostic OFH -- CMOS RAM power down data retention test
Displays the data contained in the CMOS RAM~ writes the pattern OOH, 01H, 02H,
CMOS RAM with this pattern, subsequently powering down and powering up the
4500 with this diagnostic still enabled demonstrates if the pattern is
preserved and that the battery powered memory back up system is functioning.
21. Diagnostics 10H
Channel A alignment aid
See Diagnostic 11H.
22. Diagnostic 11H -- Channel B alignment aid
Diagnostic lOH is used for aiigning channel A; lIn is used for aligning
channel B. These diagnostics display a graticule and a message indicating
which channel is being tested. Unlike the other diagnostics, changing the DIP
switch LSB (i.e., changing from 10H to 11H or vice versa) causes these tests
to measure the channel selected by the DIP switch without the need for
depress-ing the reset pushbutton. In these tests; input Signals from the
front panel BNC are internally disconnected and the offset circuitry generates
a ramp applied to the ADC. The output of the ADC is then compared to the
theoretical ideal output for the ramp input used and a plot is generated on
the CRT.
3-5
4500 Service Manual.
The plot shows the.difference b~tween the theoretical and measured ADC values;
t.her.efore t an ideaT ADC shows. a straignt line at zero on the display. When
the values are calculated. ~n thes~,t~st~, more than one acquisition is averaged. These tests all owa resol u.ti on 'of better than one bit as a result. The
':grat i cuI e show'n represents one:-ha'l f bit for each vert i cal d i vi s i on. Note that
these diagnostics' are a'o alignment aid a,nd not generally useful for measuring
ADCperformance. The d i sp 1ay may be ent ire 1y offscreen and the ADC may st ill
operate correctly due to its AUTO CAL ability.
23. Diagnostic 12H -- ROM Checksum Test
Thi~ diagnostic calculates
checksum should be zero.
th~
ROM checksum and displays it on the CRT. The
, SPARE COMPONENT 'RECOMMENDATIONS
The following 'list shows the components that fail most frequently. These
components should satisfy most repair requirements. Consult the factory for
r~commendations for maintaining multiple systems. Provide a description when
ordering parts because the following part numbers may change without notice.
Part Number
Description
2600-0014-10
1700-0104-10
1700-0108-10
1700-0094-10
7000-0366-10
Relay
LF3b5
LM11CLN
TDA-1170
Heatsink for
TDA-1170
CA3086
MC1391P
10H02
AM6688
Heatsink for AM6688
100102
100114
SL3127C
CA3049T
Relay
BFR-96
Adjustable, Cap
04858
HAI-4605-5
6A. Fuse, 3AG.
2N4276
2N5883
Insulator
2N6545
14012
LM324
LM358
1N4937
1700-0080-10
1700-0081-10
1850-0132-10
1850-0092-10
7000-0125-10
1850-0078-10
1850-0080-10
1700-0032-20
1700-0008-10
2600-0013-10
1300-0058-10
4600-0016-10
1000-0024-10
1700-0099-10
7300-0028-10
1400-0039-10
1400-0030-10
7200-0016-10
1300-0054-10
1820-0004-10
1700-0086-10
1700-0096-10
1200-0031-10
3-6
Qty.
2
1
1
1
1
COIIIRents
Musta1soreplace heatsink
1
1
2
1
1
1
1
2
1
2
1
1
1
1
1
2
1
5
2
1
1
1
2
Must be assembled at Factory
4500 Service Manual
CHAPTER 4 . CALIBRATION
INTRODUCTION
This chapter provides detailed calibration procedures for the Gould Design and
Test Systems Division 4500 Digital storage Oscilloscope. Many of the procedures set up conditions for those that follow, and some adjustments are interact i vee Therefore, the procedures must" be fo 11 o·wed in sequence.
Do not change any calibration settings if you suspect any pa~t of· the 450U.has·
fai 1ed. Changi ng adj ustments may cause other 4500 sect ions to rna 1funct.i on,
and will make troubleshooting more difficult.
RECOMMENDED CALIBRATION INTERVAL
The 4500 has an AUTO CAL feature that automatically calibrates the APC~ for
gain and offset errors. The correction factors currently in use may be obtained from the CAL display that is accessed via the SELF TEST menu. The
correction factors have a range of from -128 to +127. When any correction
factor becomes greater than +/-100, the AUTO CAL circuitry is approaching the
limit that it can correct fora
The Performance Verification Procedure in this manual is a thorough test of
the 4500. This procedure is a good indication of the need for calibration, if
any.
The system should be calibrated if any of the following conditions exist:
1. If the CAL display, accessed via the SELF TEST menu, shows any
correction numbers more positive than +100 or more negative than
-100.
2. If the 4500 fails to pass the Performance Verification Procedure.
3. If the 4500 is operated for an accumulated time of more than 10UO
hours since the last calibration.
4. If one year has passed since the last calibration.
4-1
4~UU
Service Manual·
RECOMMENDED CAlIBRATION;¥9UENCE
I f a comp 1.ete 4500 cali brat ion- is bei ng performed, it is recommended
that the circuit boards be calibrated in the following sequence:
1. Power Supply·
2. MPU
3. CRT Dri ver· ..
4. Floppy Oi sk . I.nterface
5. Sweep and Record
6. Channel A AOC and Attenuator, and External Trigger Attenuator
The Channel A AOC Calibration Procedure specifies when the
.thannel A Attenuator and External Trigger attenuator are to
be adj usted.
7 •. Channel B AOC and Attenuator
The Channel B ADC Calibration Procedure specifies when the
:channel B attenuator is to be adjusted.
RECOMMENDED TEST EQUIPMENT
A list of recommended test equipment is provided at the beginning of
Chapter 2, Performance Verification.
CALIBRATION PROCEDURES FOR MODULE REPLACEMENT
The following procedures provide general guidelines for calibration after a
module has been replaced or repaired. These procedures should apply in most
cases, but there may be some exceptions that are not covered. If a module has
been repaired, recalibration may not be necessary, depending upon the circuitry affected by the repair.
MPU Board
The MPU board can be replaced or repaired
bration. There is one adjustment on this
though it should not need to be adjusted,
another board is installed. Refer to the
without affecting system caliboard for the CPU oscillator. Alit should be checked any time
MPU Board Calibration Procedure.
Interface Board
The Interface board can be replaced or repaired without affecting system
calibration. This board only contains the external interfacing circuitry,
therefore, the board does not have to be installed for the system to operate.
There are no adjustments on this board.
4-2
45UO Service Manual
Floppy Controller Board
The Floppy Controller board can be rep1aced~or'repaired withou~ affecting
system cal ibration. This board only contains circuitry used fo'r f.loppy disk
drive operation, therefore, the board does not have to be installed for the
system to operate properly. There is one adju~tment .on this board for th~
+12 volt power supply used by the di sk' dri ve.' A1tho:ugh ' it shQul d not need to'
be adjusted, it should be checked any time another boa-rdis installed. ,Refer'
to the Floppy Controller Board Calibration Procequres.
CRT Driver Board
***********
* Warning *
***********
High voltage is present on this board. Injury or,
death to personnel could result from contact wit~
this high ~oltage. Refer to the CRT Alignment
Procedures.
The CRT Driver board contains the display generation circuitry and the system
operating software. If a replacement board, with a different software
revision, is installed there may be some differences in the system operation
noticed. However, most revisions are typically created for enhancements to
the Self-test Diagnostics, the system operation or to correct software buys.
The software revision is written on the EPROMs installed in the board and can
also be observed in the upper left-hand corner of the MPU/CRT self-test diagnostics display. Your local distributor or factory representative can provide
information regarding software changes.
Due to differences in the CRT tube and yoke, it may be necessary to perform a
CRT alignment if a board is replaced. Although some of the adjustments may
not need to be performed, a complete calibration is recommended to provide the
best display. The horizontal and vertical hold pots should always be adjusted
in order to prevent the possibility of intermittent loss of display stabi1ity~
The display INTENSITY control located on the front panel should also be
adjust-ed to prevent burning of the CRT face.
All adjustments located on this board affect display integrity only, and
repair or replacement should not affect the system operation with the
exception of software revisions.
4-3
4500 Service Manual
Sweep and" Record Board
.".The Sweep and ~ecord board conta'i n's' the .hi gh-speed memory, and control s many
of the recording fUnctions. Proper calibration of this board is critical to
: system operation.,: :This board should always be completely calibrated any time
it is replaced or repair~d.· :A'repl~cement board may operate properly when
.
installed, but an adjustment could .be. just within operating range and result in
intermittent failures.'
"
.
Improper calibration of the system's clocking circuitry may provide misleading
symptom s, i nd i cat i ng i mprdperana log c i rcu it ry performance of the ADC boards.
Each AD~ board provides a sliyhtly different load on the Sweep and Record
board clocking circuitry. Therefore, any time another board is installed, it
must berecalibrated.
When installing a: replacement board, the first step is to perform a complete
calibratibn. of.the board as described in the Sweep and Record Board Calibrat i~on Procedure.'. Then perform the 33-MHz Ali as Test (step 44) of the ADC
Calibration protedure. Be sure to check both· channels. The only adjustment
described in that step that needs to be made is R668. This adjustment should
compensate for any differences between Sweep and Record boards.
If the system fails the 33-MHz Alias Test, it may be necessary to perform the
other adjustments described in step 44, after rechecking the lOO-MHz oscillator on the Sweep and Record board. Once both channels pass the alias test,
the Auto Cal and DNL Test (step 51) of the ADC Calibration Procedure should be
performed as described. No other part of the system should require calibration.
Attenuator Board
If the Attenuator board is replaced or re~aired, the board should be completely calibrated as described in the attenuator board Calibration Procedure.
Adjustments for the input capacitance and frequency response are typically not
required, but are recommended to assure optimum performance. No other adjustments to the system should be required.
Once the Attenuator board has been calibrated, the self-test diagnostics
should be run to verify proper operation. The Auto Cal and DNL Test should be
checked as described in step 51 of the ADC Calibration Procedure.
4-4
4500 Service Manual
ADC Board
***A*******
*
CAU'TI0N
,*'
**1********
Always check replacement boards~areful,ly for
damaged or bent components' pri-or to i nsta 11 at·ion.
The ADC board is a high'density' b~ard. that can b~
damaged easily. Bent componen~s couldcause'damage
to other system modul es.
.
Jumpers on ADC board determine whether the board is used for channel A or
channel B. If necessary, modify the jumpers as shown in Figure 4,..;.1 of the ADC·
Calibration Procedure. The channel A board provides the 'circuitry for the
external trigger and channel B does not use the circuitry. Always check
for correct jumper placement before installing a replac~ment, board.
1.
Install the replacement ADC board and connect all of
2.
Power up the system and operate the Self-test Diagnostics. The
attenuator1s calibration must be matched to each ADC board, therefore, some of the analog tests may indicate out-of-tolerance
specifications. If the board does not appear to be recording close
to expected results, perform the next step.
3.
If necessary, adjust R668 as described in step 42 of the ADC
Calibration Procedure. Later in this procedure, R668 will be
adjusted accurately.
4.
Perform the Attenuator Calibration Procedure as described, except
the input capacitance and frequency response adjustments.
5.
Perform the 33-MHz Alias Test, (step 44) of the ADC Calibration
procedure. The only adjustment that should be needed is R668.
6.
Perform the Auto Cal and DNL test as described in step 51 of the
ADC Calibration Procedure. The adjustments described in this
step should bring the 4500 within specification.
7.
Verify that the external trigger circuitry is within tolerance. The
test is described in steps 46 through 50. The only adjustment that
should be needed is the external trigger balance adjustment (RIOI)
described in step 50.
4-5
the·cables~
4S00 Service Manual
POWER SUPPLY CALIBRATION PROCEDURE
1. Thi power supply has ten adjustment potentiometers that set the five power
supply'v61tages.and t~e five overc~r~eht shutdown values. These potentiometers are' a.ccessed at' the "eottom of the 4500. The '1 ocat i on of each potenti0meter is printed on the bottom 'of the power supply. The voltages measured
during the ca1ibrati6n procedure ar~ accessed at the edge connectors on the
bottom of the motherboarq.
2. Remove the botto'm' cover of the 45UO. Set the 4500 POWER swi tch to ON.
Ensure t~at the 1i~e voltage is ~ithin 5 percent of the nominal value.
3. From.the bottom of the 45UU measure the following nominal voltages on the
printed'circuit board edge connector and pins specified. Reference Mother
Board Assembly Drawing, 0285-0020 for connector location. Adjust the potentiometer· sp~cified to set the voltage to the value specified. Connect DVM ground
to the common return of the power supply which is the motherboard mounting
screw'on ·the left side of the board.
NoIIIinal Voltage
-5.2
+5.0
-2.0
-18.0
+18.0
V
V
V
V
V
Connector
J3
J3
J3
J7
J7
Pins
1
15
9
27
29
to
to
to
to
to
Potentiometer
8
18
12
28
30
R87
R129
R141
R64
R63
Value
-5.35
+5.01
-2.14
-18.01
+18.01
+/-0.02
+/-0.05
+/-0.02
+/-0.05
+/-0.05
V
V
V
V
V
4. The overcurrent shutdown values are set by causing the power supply to
output each shutdown current, and then adjusting the potentiometer until
shutdown occurs. This adjustment procedure can not be implemented while the
power supply is connected to 4500 circuitry and it is recommended that the
factory settings not be modified. The nominal voltage of each supply, along
with its overcurrent shutdown value and the adjustment potentiometer that sets
this value, are listed below for reference.
NOIDinal Voltage
-5.2
+5.0
-2.0
-18.0
+18.0
Overcurrent Shutdown Value
Potenti,~o
{)~'Q
R536
TP1
"
Q
,>
>
cz.",'?
;,:>\&.¢
'*q (tWo::
Q
e
.;;
·e
Q
G
¢
;)
.;
Q
Q
':J
1)
<.)
t)
e<
Q
"
¢
(.
0
V
Q
'!
0
e
'0
~
R541
I)
?
'!
~
t;
¢
R540
U60
TP2
o
o
0'
1I2
:;....,.,.,...w".....,....._..1
P.538
4500-306
Figure 4-5. Offset and CAL DAC Adjustment Test Points
4-19
4500
Servic~~M~nual
.,
~6.
Probe the emftter of
~~.,'
.
Adjust R34 for +6.390 V +/-10 mY.
17. M6~~ probe.ground to the outsid~ end of R47.
of Q6.. ~ AdJust:.RI2. for +1~200 V·+/-10mV.
Probe the case .(collector)
.
.
18. Mbve probe ground. to: the outs i'deend of .R17.' .Probe U2 pi n 10. Adj ust R20
for o volts +/~10:~V.
.
..
'
,
19. Move probe'ground'on 'the top of C27p. See Figure 4-5. Probe the outside
end of R50. See Flg,ure4;..4•. Adjust R35. for +3.960 V +/-1 mY.
20., Probe the outside end ofR48-•. Adjust R30 for 0.0 V +/-1 mY.
TRACK and HOLD CIRCU-IT :·ADJUSTMENT
21. Move probe ground to the left end of R143.
Adjust R99 for -2.600 V +/-5 mY.
Probe the right end of R143.
See Figure 4-6 for test and adjustment locations used in the following steps.
22. Set an oscilloscope to 50 mV/div, DC input coupling, and 0.1 uS/div, using
a 500 ohm or FET probe. Place the scope probe ground on the bottom of R205.
Probe the right end of R438. Adjust R1U4 to obtain the flattest possible
trace, disregarding spikes every 200 nanoseconds. Note the spikes are only
every 200 nanoseconds if the 4500 sweep rate is set to 40 uS/divas specified
in step 2 of this alignment procedure. The spikes should have an amplitude
less than 50 mV peak-to-peak. See Figures 4-7, 4-8, and 4-9. If the spikes
are greater than 50 mV peak-to-peak perform step 23. If the spikes are between 30 and 50 mY, wait until the 33-MHz Alias Test is performed (step 44).
If the results of the 33-MHz Alias Test are not acceptable, then perform step
23 (as noted in the Alias Test) and return to the Alias test.
23. Gently bend the wire stub soldered to the top or bottom lead of CR9 toward
the top or bottom of the circuit board, so the peak-to-peak amplitude of the
200-nanosecond spikes referred to in step 22 are minimized. If CR9 does not
have a wire stub soldered to one of its leads, a one quarter inch stub (made
. from a one quarter watt resistor lead) must be soldered to the top or bottom
lead to perform this adjustment. Determined by trial which lead to add the
stub to so bridge capacitance is balanced and spike amplitude is minimized.
4-20
4500'5e~vice
j;.,0(l
-,;
U6
4()Q~
O~
:;
Manual
<>:0
l) o~
RS9
""
R87
R86
R80
R76
R82
011
R104
R117
eR9
R20S
R438 ----+--~e"t"+~··..-----~~~
e440 ,~.b
'R44i
<-£~
,.,,'
T?4~" o(~
..:.l..451
4500-307
Figure 4-6. Track and Hold Adjustment Test Points
4-21
4~OO
Service ~anual
Figure 4-7. Track' and Hold'Wavefonn'Showing Nonflat Perfonnance
t
T
\
I
. i··
I
i !
'...J:
.,
4500-309
Figure 4-8.
Track and Hold WavefonB With 50MY P-P Spikes
1
It-- .-.:.
."
:t
-j-l--i--+-1--+--I------+---J.---I
100'
j
90---:------
f
r-------iI
.. / ..
j
1
I
.II.
••1.
.1;
, , I
f------r : !
,o--l----L~_+____+__+-t__+---+---I
,
.
!
o~ ______
:i
I
I
Figure 4-9.
Track and Hold Wavefonm With 30 MY P-P Spikes
4-22
4"500 ,S~rv ice Manua 1.
Second Stage Amplifier Adjust~nt
24. Connect the DVM probe ·ground. tothe' top.' Q,f C270~' ,:·SeEf·.FJ gure'A-5. Probe
the left side (negative side) dfC65 •. : Note.'that 'onao ETCH j\·board·-it .may be
difficult to reach the left side ofC65~··ln this event~ ,use t.he·out·sfd~ end.
of R82, which is the same circuit· point~ '. Ad'just R80 ~for -5.7-60 V +/~~O mV •.
25. Probe the outside end ofR·87., RQt~t~·.·R59.'.:f6:11j:~count~t~lockwlse.··and··then
turn R59 clockwise to obtain -0.600 V +/-lD-.mV .... Note·that· it ispossi"bleto
cont i nue to turn thi s potent iometer· c1ockwj se and.' reach anotner point where·
the measured voltage is -0.600 V; th~~ef6re,.~the potentiometer is initially
turned fully counterclockwise~
.
'.'
26. Pl ace probe ground on ,the outs i de end· of R86:·., Probe U6 pi n 10. Adj ust R89
for 0.0 V +/-10 mV.
27. Pl ace probe ground on the top end of e270. S'ee Figure 4·~5. On an ETCH C
board, probe the outside end of RIll. On an ETCH' A board,probe the COLLECTOR
(right side) of Q11. Adjust R76 for -1.200 V +/-:l.mV.·
Third Stage Amplifier DC Adjustment
See Figure 4-10 for test point and adjustment locations used in the following
steps.
28. On an ETCH C board probe the outside end of R392.
U31 pin 9. Adjust R404 for 8.27 V +/-10 mV.
29. Probe the emitter of Q40.
On an ETCH A board probe
Adjust R422 for 4.09 V +/-10 mV.
30. Probe U31 pin 13. Adjust R414 for 8.62 V +/-10 mV.
31. Place probe ground on the top of R389.
R427 for 2.12 V +/-10 mV.
Probe the bottom of R389.
Adjust
32. On an ETCH C board, place probe ground on the top end of R398. On an ETCH A
board, place probe ground on U8 pin 13. Probe U8 pin 10. Adjust Rl18 for 0.0 V
+/-10 mV.
33. Set an oscilloscope to 50 mV/div, DC input coupling, and 0.1 uS/div, using
a 500 ohm or FET probe. Place the scope probe ground on the bottom of R205.
Probe the right end of R438e Adjust R424 until the flat part of the trace is
at 0.0 vol t s •
4-23
45UO Service Manual
PROBE
POINTS
C10
R25
PROBE
POINTS
R66
R64
R65
C45
R118
C46
J
Q40
PROBE
POINTS
C65
R398
R392
U31
R404
R414
R409
R422----~-&O~~~~~~~3~~~~
R424
oO'1C'657
R427
U8
R438
R205
4500-311
Figure 4-10.
Third Stage Amplifier Test Points
4-24
45UO Service Manual
34. If the channel A ADC ts 'belngca 1 ; bra'ted ~ perform the Channel A Attenuato'r
Cal i brat i on Procedure, an.d ·.the. E'xterna 1 Tri gger Att:enu.~tor Cal i brat i <;>n Procedure at this time. If thecharinel B ADC is. betng calibrated, perform th-e, .
Channe 1 B Attenuator Cali brat·; o.n Procedure at thi s t.i.me~ .These' procedures. may
be found in the Attenuator Cal i brat.; 00 . Proce~ures secttbn .of thi s manual,.
3!). In the next step~, the gai n of ~'ach of. t.hefi rs.t,.:.sec-ond·, and thi rd stage
amplifiers is set to approximately the d·esi";red.valu~.. using·an o·s.cilloscope;
the yain is then set more precisely using a DVM. 'The .oscilloscQpe is used
first to ensure that none of the stages are.saturating. Connect to:the
.
attenuator i nput (front panel' BNC) for channe'l Aorchanrie 1 13.~. 1 kHz, 50 mV
peak-to-peak, sinewave. Using the CHNL A -or.CHNLBmeno,·~etthe input
coupling to AC. Connect a 10 Megohm (X10)~~obe·to ari oscillo~~ope~' Connect
the scope probe ground 1ead to the· bottom prob.e po:i.nt (the· poi nt wi th the
round pad) of the probe poi nt p'a;"r ·tocated a'i' the top.l eft corner of the
circuit board. Connect the scope probe tip:tothe uppe~ probe priint (the
point with the square pad) of this pr'obepoirit .pa·ir •. Adju·st th.e input sine~
wave for a 100 mV peak-to-peak signal measured at these . probe pdints.
36. Move the probe to the probe point pair located to ~heleft of R6~, R65,
and R66. Connect probe ground to the round pad and the probe tip to ·the
~quare pad.
Adjust R25 to obtain a 590 mV peak-to-peaksinewave.
37. Move the scope probe ground to the bottom of R205. Connect the scope
probe tip to the right end of R438. At th;s point, there should be a 2.5 V
peak-to-peak sinewave with no DC offset. If necessary, adjust R424 for 0
offset and R409 for 2.S V peak-to-peak.
38. Repeat steps 35, 36, and 37 with a DVM as follows: Ensure the DVM has a
frequency response that accurately measures 1 kHz and that the frequency
response of the DVM does not change as the DVM range is changed. Set the DVM
input coupling to AC. Place the DVM probe on the probe points at the top left
corner of the board and adjust the input sinewave for 20 mV rms.
39. Pl ace the probe on the probe poi nts to the 1 eft of R64, R65, and R66.
Adjust R25 to obtain 117 mV rms.
40. Place the probe ground on the bottom of R205 and probe the right side of
R438. Adjust R409 to obtain 0.5 V rms. Set the DVM input coupling to DC and
adjust R424 for 0.0 V. Switch the DVM input coupling back to AC and check for
O~ V rms.
Adjust R409 again, if necessary. Repeat step 40 until both values
are obtained.
4-25
4500 Service Manual
Second Stage Amplifier Rise Time Adjustment
41. Connect a 50 ohm termi nator to the'-4500 input. Connect the -1 Volt Fast
Rise output of a PG506 pulse generator to the 50 ohm terminator and ~etthe
pulse amplitude to -l'V. Set, the PG506 pu1s~ p~~iod"tb4 uS. "Set the 4500
,input coupling to AC; SENSITI,V'ITY to 0.2 V/div, .OFFSET tOo 0 V, and PRE TRIGGER
. and POST TRIGGER SWEEP speeds'tG 1 mS/div. Using"an osci11oscopewfth -a 500
.. ohm,or FET probe wi~h a short gfound 1ea~, co~neci .the probe to the probe
poi~ts above C65. The probe ground connects to' the probe point with the round
p.ad" and the probe tip connects to the probe poi ntwi th the square pad. Set
.. the os.ci110.s'Cope sweep speed to 10 nS per d·ivision and its sensitivity to show
a5 division 'high tr.ace •. , Trigger the .. s·cope so th~ rising edge of the waveform
at the probe ·p6tnt.s·is· .visib·l~. Usin.ga nonmetallic adjustment tool, adjust
· ClU,C45, and 'C46 t-o obtai n the' square'st paSsi bl e pu1 se corner as the pu1 se
rises to zero volts •. "The.re should ·be. no overshoot and the pulse top should be
·t1at.·Se~ Figur~s.4-11i:4-12, 4~13;·and.4~14. Change the oscilloscope sweep
speed.t6 5'nS ~e~ divi~iori and fine tune C10, C45, and C46 to obtain a 7- to
9~n.atiosecon·d .rise. time •... Thfs r'is~ time should be measured from one half
" divi~iori'a~ove the b6tto~ of thetr~ce to one half division below the top of
· the trace (the. 1Q%' to 90%" poj nts-} •. "" Change the osc ill oscope back to 10 nS per
.divi~i~n·and·ensur~ there is ~o overshoot as shown in Figure 4-14.
Data Ready.. Strobe Adj usiilent
42. See Ff~ure 4-15 ~or test point and adjustment locations used in the
following steps. This step is referenced in the Sweep and Record Calibration
Procedure, and if the Sweep and Record board has been calibrated this step
will already have been performed. If it has not been performed, it should be
"~oneas follows.
Set the 4500 PRE TRIGGER and POST TRIGGER SWEEP speeds to 2
· uS/dive With a 500 ohm or FET probe, observe the ECl signals on U77 pins 12
and 13. A ground for the probe may be obtained on U73 pin 16. The signals on
U77 pins 12 and 13 should b~~ood ECl levels with approximately 50 percent
duty cycles. If these signals are not good ECl levels with approximately 50
percent duty cycles, adjust R668 for the best possible signals at these
points. All these adjustments are approximate at this point and will be
finely tuned later in the procedure.
Comparator Adj ustment
43. Initiate the Channel A Alignment Aid diagnostic if aligning the channel A
ADC, or the Channel B Alignment Aid diagnostic if aligning the channel B ADC.
The Channel A Alignment Aid is initiated by setting the MPU UIP switch to 10H
(switch 5 opened and all other switches closed) and depressing the RESET
. switch. The Channel B Alignment Aid is initiated by setting the MPU DIP
switch to 11H (switches 1 and 5 opened and all other switches closed) and
depresSing the reset switch. See the section on 4500 Built-in Manufacturing
'Diagnostics (Chapter 3) for further information on initiating these aids. The
alignment aids bypass all 4500 controls and disconnect all input signals;
therefore~ the 4500 setup and inputs do not have to be changed.
4-26
4500 Service Manual
.J........... :... :, . " .................... ~
.:.'~~·O~~~~
~ ........
.',
Figure 4-11.
.TNr>A!:inrC·'T'l:-' \/'I I1Uv
nn ",cTEn .'
U") I . U .
RESPONSE· ~S TOO SLOW.
. 11 .l.,Uf"\KC,
Second Stage Amplifier Rise Time Too.Slow
I
Ir--- -:.-100,
.
•
,
.
•
+
+
•
.
I
•
:
INCORRECTLY ADJUSTED;
RESPONSE SHOWS
OVERSHOOT.
."!".
j";
•
1
.:
"':
•
•
,
•
.....
,
!
•
•
•
•
-+
•
,
---; -:----~-~T-!-:.. :•
4S()O-315
Figure 4-12.
Second Stage Amplifier Rise Time Showing Overshoot
4-27
4SUU Service Manual
,
--
~
,
,
,
-:
'
-
.
.,
i
!OP
gu· , . , •
'.'
; .. "+ .
±
~
.... :.:'> q: :;~:~~t~f~·~-·:-+·---+.l---+~
;"
.!:
!
! .
--~.:, -~-:--E--·-t"--.----t-
el,~<:~".--:..-"
.. " , _
_ .':,
I
.
INCORRECTLY ADJUSTEO;
RESPONSE HAS SLIGHT
OVERSHOOT ANO RISE TIME
IS 10.5 NS.
~--'---;
'--~_'''';-' '~----
' - - --<
: ••
--'
---I_
45]')-314
.
Figure 4-13. Second Stage Amplifier Rise Time With Slight Overshoot
!
.J
~~:~=~~~~~~~-". +.-..+..-..4.-"."~.- ~ ~~
CORRECTLY ADJUSTED;
10% TO 90% RISE TIME
IS 9 nS.
.. -.. ..-.. .. ..
I
4')().)-31'3
Figure 4-14.
Second Stage Amplifier Rise Time Correctly Adjusted
4-28
45UU Service Manual
C200
C201
o
R424
R409
o
R453
R43S
R205
c;~'~~~~~
;''''''''''
'.
.•
.•. '.:
. . . . :.
.:,:.,:,. .:. .
:.:.,,:x,
.•..:::.::.::... .
;.:!.:. . . . . . . .
::t)@:,
.:.,; .:.
i.l
. --
i #.t~:?;;,:::~:¢
:¢
~I:
R360----~~~~~
.:::X:
.:''*
"
.;»;..
.:
::
:*::. .
. f1 : :
:~ ~ ~ ~ :t
:0
iii
.1'
4500-322
Figure 4-21.
Trigger level Test Point and Adjustment locations
4-35
4500
Servic~'M~nual
,49.', C~a.nge th'e: trigger slope to ENT BAND. The V(M) reading should switch
, between +3 V +/-0.2 V and - 3 V +/-0.2 V. If one of these two val ues is out
.'o:f tolerance, adjust R360 (trigger amplifier offset) to bring both within
tolerance. ·This action sacrifices some accuracy on POS or NEG slope triggertn9to yie1d.bettef a~~uracy on' ENT band triggering and a better compromise on
overall trigger level accuracy.
.
50. Perform this step only if the channel A ADC board is being calibrated.
Connect the input signals i mul taneo.us 1y to the front panel Externa 1 Tri gger
.BNC input and to the Channel A input BNC connector. Using the TRIG SRC menu
set the tri ~ger source ~o.. EXT. Veri fy that the V. (M)readout i s +~ +i~ V. .:
when the tr1gger level 1S set to +3 V, and that th~ V(M) readout 1S -~ +~
V when the tri gger 1eve 1 is set to -3 V. I f necessary, adj ust the tri gger
balance potentiometer (RI01) on the Attenuator board·to achieve these readings.
1
-
AUTO CAL and DNl Tests
51. To further verify ADC performance, the AUTO CAL self test and the DNL
self tests should be performed. The AUTO CAL self test indicates the amount
of correction required for the ADC input amplifiers to have the proper gain
and offset. The channel A and channel B DNL tests show an indication of the
differential nonlinearity of these two ADCs.
To initiate the AUTO CAL self test depress:
MASTER MENU
TEST, menu key C
CAL, menu key 8
The CAL correction factors will be displayed as shown in Figure 4-22.
An ADC, when first calibrated, should exhibit all its CAL correction factors
in the range of 0 to +/-30. This test should be performed with the 45UO
covers in place, and with the unit operated long enough to reach a stable
operating temperature.
If any offset correction factor is greater than +/-30, lift the 45UO top
cover and adjust R76 on the ADC board with the out of range offset correction
factor. This adjustment may be reached with the ADC boards in place and
operating. The correction factors should be observed during adjustment and
minimized.
If any gain correction factor is greater than +/-30 then adjust R409 (see
Figure 4-15) on the ADC board needing adjustment. R409 is not accessible
while the ADC is in place. If R409 needs adjustment, the 4500 will have to~be
powered down" the ADC removed, R409 adjusted a small amount, and the ADC and~'
the top cover replaced.
4-36
4500 Service Manual
SELF TEST
CORRECTIONS CHNL
0F'F'8ET
><1 • ll111H!:
Xl'
Xl •
.. X1 •
X2 •
)(.2 •
X2 •
)(2 •
X5 •
)(5 •
)(5 •
)(5 •
5'"Hz
2."Hz
1'"Hz
1""Hz
5111Hz
2111Hz
1111Hz
lHrtHz
51ttHz
2tnHz
-lititz
ADC 8AIN
PROlE BAIN
NET 8AIN
~
2
+ 1
a
SWP/ItCD
-- 43
T~IBSER
CHNL
•
2
-- --..
--.. ,2 - ,,.1
- • -.- 12•
- .. 11
+
--l'2
+ •
2 . •
2
•
3
ATTN
4
4
I
S
S
A ADC
S
•
D
A DNL.
S
a ADC
6
8 DNL.
- 16
I
•
CAL. ..
2"
KEYBOARD
,
"PU/CRT
A.
OF'F'SET ~ NET GAIN ERRORS or -128
OR +121 INDICATE UNIT IS OUT or
CALIBRATION.
4~);)O-32.3
Figure 4-22. CAL Correction Factors Display
+3
SELF TEST
1-~------....---------;---t- SWPIRCD
+2
1
TRIGGER
2
ATTN
iii
A ADC
D
A DNL. +S
A DNL
+I
8 ADC
6
BDfI.
I
ACCEPTABLE RESULT.
NO SPIKE GREATER
THAN +/-1 DIVISION.
CAL. I
e
-In""~~~~","",1111- KEYBOARD
IPJItRT
,
-I
4500-324
Figure 4-23. DNl Test (Slow Version) Correct Wavefonm
4-37
4500 Service Manual
After the gain·or··offset is changed, observe ihe correction factors for a few
minutes as they. s,tabilize. Readjust R76.0r. R409 as necessary.
To terminate the AUTO CAL display depress:
. HALT, menu key" C'
The .A DNL sel.{ test should now be i ni ti ated •. From the SELF TEST menu ,depress:
A DNL, menu key 5
The display (see Figure 4-23) shows -a histogram of the differential
nonlinearity of the ADC for channel A,averaged over a large number of
acquisitions.
There are two software versions of this test. In some 450Us (software
versions 3.4 and earlier), the ONL test is performed continuously, with the
results appearing on the display approximately two times a second. In other
4500s (software versions 4.0 and later), the test is performed once, each time
the A DNL key is depressed. The result takes approximately 12 seconds to
appear on the display. Figure 4-23 shows an example of the slower version of
the test. In the faster version, less averaging is done and more noise (peakto-peak variation) is apparent in the result. In the slower version more
averaging is done and the result shows less peak-to-peak variation. The ONL
test is designed to ensure a differential nonlinearity of +/- one half LSB.
In the fast version, an acceptable result shows no more than two amplitude
peaks greater than +/-1 division at anyone waveform point within five
successive tests.
In the slow version, an acceptable DNL result shows a histogram on the zero
line +/-1 division. There should be no amplitude peaks greater than +/-1
division.
Next perform the B DNL self test.
From the SELF TEST menu depress:
B DNL, menu key 7
Interpret the results as discussed above.
If the channel A or channel B ONL test fails, check that there is good
electrical contact between the aluminum shield that is mounted to the back of
the ADC board that fails the test, and the spring metal tab that is mounted to
the chassis next to the ADC board card guide. If there is good contact, then
the problem is most likely the adjustment of the track and hold circuitry.
If necessary, repeat steps 22 and 23.
4-38
_ 4500 Service
M~nual
INPUT and EXTERNAL TRIGGER ATTENUATORS CALIBRATION PROCEDURES
1. The following procedures ~re ~s~d to adjust the attenuat6~s for channel A,
channel B, and the external trigger- input. Th~~e threeatt~nuators are independent; therefore, individual adjustment of one does not affect the others.
If one of the channel or trigger attenuators is not to be adjusted,-disreg~rd
the associated steps.
-
To acces$·the Attenuator board" for adjustmeht, -rem~~e the f~u~-screws that
attach th~1ront panel bezel to the front casting~' 'When the screws have been
removed, the front bezel assembly may be tilted fotward to access the adjustments. Ensure that only an insulated adj~stment tool is used, as it is easy
to short ci rcuitry Qnthe attenuator board- to. the metal access panel.
Channe1 A or Channel B IP BALANCE'. -Adj ustment
2. Set the channel A or Channel B (whi~hever channel is being aligned) sensitivity to 0.001 V/div. Connect DVM probe gro~nd to the outer shell of the front
panel BNC connector for the channel being aligned. Connect the probe to the
inner conductor of the same BNC connector. Measure the DC voltage present on
the I3NC connector and adjust the IP I3ALANCE control (R39 for channel A or R86
for channel B) for 0.0 V +/-100 uV. This measurement is extremely sensitive to
electromagnetic interference. Static discharge caused by the moving of feet or
clothing may result in variations in DVM readings that exceed 100 uV. These
variations can be minimized by using a shielded cable on the DVM and reducing
body motion while observing the settling of the DVM reading. When this adjustment has been performed it should be verified by setting the trigger source,
using the TRIG SRC menu, to either A/AUTO or B/AUTO. Depress AUTO ARM.
Short
the input I3NC connector for the channel being aligned, with a BNC shorting plug
or 50 ohm terminator. There should be no movement of the trace as the input is
shorted and opened. If necessary, readjust the IP balance control of the channe 1 bei ng cali brated.
Channel A or Channel B OP BALANCE Adjustment
3. See Figure 4-21 for ADC test and adjustment locations. Disconnect the
coaxial cable from the attenuator channel being aligned to the ADC. Place DVM
ground on the top of C270. With the DVM, probe the outside end of R50 on the
ADC board associated with the channel being aligned. Verify a voltage of
,-,+3.96 +/-1 mV. If necessary, adjust R35 on the ADC board to achieve this
~~oltage.
Now connect the coaxial cable from the attenuator to the ADC. The
't,yaltage on the outside end of l{50 on the AOC board should be +3.96 +/-1 mV.
~ it is not, adjust the OP BALANCE control on the attenuator for the channel
being aligned (R28 for channel A or R74 for channel B), so +3.96 +/-1 mV is
obtained. The voltage should remain constant while the coaxial cable is
connected or disconnected.
4-39
4500 Service Manual
External Trigger TRIGGER BALANCE Adjustment,
,
,
4. Ensure the external trigger atte~uator.output coaxial cable is plugged into
~onnector J3, th~ trigger input "corinector" on the channel A ADC board. On the
channel A ADC board, pl ace probe ground on the outs:i de end (the end away, from
the ci rcui t board) of R351. Thi sis a 1 -Megohm res i stor near the 1efted9~ of
,the ADC' circui.t board below relay K5. Probe the left "end of' resistor R36'2.,
Thi s res i stor' is' '1 bcate,d below relay K7. Us i ng the TR I G SRC m'enu select, EXT
'(external trigger).', Wi~h no signai applied to front panel ,trigger input BNC
,~onnec~~r,'adjust,th~ TRIGGER BALANCE.cohtrol RI0l for o.a V ~/-I00 tiV~
5. Th~foll~~ing 'steps require'a pul'se'generator that ,generates pulses that
are flat t6 O.51'or less.' A Tektronix PG506'is ~eco~mended. 'The PG506 has
two fast ris~ output~ and ~,hi9h ~mp1,itude output~ The,pulses from these
outputs go to ,either a pas'i t i ve or n,egat.i ve, voltage' leve" and then back to
ground. The fl~t part, cif these pulses are at'ground.' , Thi~ z~ro voltage level
portion of the wa~eformshoald be,used in theseadj~stment procedures.
6. The following steps adjust the frequency compensation and
i tance of the ampl i fi e'rs. 'The input capaci tance adj ustments
capacitance to 30 pF.'When- adjusting the input capacitance,
pF input standardizer (paft'no. 0285-0109-10) is driven by a
and the attenuator is adjusted to achieve a square pulse.
the input capacset the input
a calibrated 30
pulse generator,
, Channel A or Channel B AC/DC Control and lIP CAP Xl Adjustment
7~
Connect a 50 ohm terminator to the 450U front panel BNC input connector.
Use a Tektronix PG506 pulse generator, and use the PG506 fast rise output· that
, , goes from a negative voltage to ground. Connect this output to the 50 ohm
terminator. Set the PG506 to output voltage to approximately 100 mV peak-topeak, and its period to 100 mS. Adjust the 4500 SENSITIVITY to 0.01 V/div,
OFFSET to 0, PRE TRIGGER and POST TRIGGER SWEEP speeds to 20 mS/div, and input
coupling to DC. Using the TRIG SRC menu select A/AUTO if calibrating channel
A, or B/AUTO if calibrating channel B. Depress AUTO ARM. Adjust the AC/OC
control (R18 for channel A or R82 for channel B) to obtain the squarest
possible pulse corners on the 4500 display as the pulse rises to zero from its
negative level. Replace the 50 ohm terminator with the RC input standardizer.
Change the PRE TRIGGER and POST TRIGGER SWEEP speeds to 20 uS/dive Change the
PG506 period to 100 uS. Adjust the I/P CAP Xl adjustment (CIO for channel A
or C42 for channel B) to obtain the squarest possible pulse corners.
4-40
4~00
Service Manual
Channel A or Channel 8 COMP XIO and lIP CAP XIO Adjustment
8. Remove the RC input standardizer. and place the 50 ohm terminator an the
chanriel BNC input. Change'the 450U·SENSITIVITY to. 0.1 V/div. Leave the
PRE TRIGGE:'R and POST TRIGGE.R· SWEEp· speeds at 2W uS/~div. Set t.he PG~06 to. aut put
appraxi mate ly 1 V peak-ta-pea1<' and .100 uS peri ode Adj ust the COMP XIO control
(C7 for channel A or C39 fa~ chan~el B) to obtain the sq~arest possible pulse c6~~ers as the pulse rises to' zero. fr6m its negative level; Replace the 50
ohm terminatrir with the RC input standardizer. ~djust't~e I/PC~~ XIO adjust~ .
ment (C5 for channel A or C37 for channel B). t~ obtain the'sq~~~est ·possible
pul se .comers •.
Channel A or Channel. :'8 COMP XIOO' a.nd .lIP "CAP XUlU
Adjustment.
.
,
9. Remove the RC standard i zer and' place the. '50 .ohm' -termi nator on the· BNC input
of the channel b~in.gadju.sted •. Change the· 4500 SENSI.TJ·VITY to... 1· V/div. Use
the high amplitude output'ofthe'PG5U6 and.'set the 'output 'voJtage to its
maximum (approximatelj.5 V peak-to-peak) •. Adjust· the COMPX100 control (C16
for channel A or C48 for channel B) to obtai~the squarest ~ossible pulse
corners as the pulse rises to zero from'its negat1ve'1~vel~ Replace the ~o
ohm terminator with the RC input standardizer~ Adj~st the I/P CAP X100
adjust-ment (C12 for channel A or C44 for channel B) ~ocobtain the squarest
possible pulse corners.
External Trigger COMP and lIP CAP Adjustment
10. To adjust the trigger attenuator frequency compensation, use an oscilloscope with its probe compensated to show a square response to a squarewave
input. On the channel A ADC board (into which the trigger output signal
coaxial cable is connected) attach the scope probe ground to the outside end
of R361. Attach the scope probe tip to the left end of R362. Set either of .
the PG506 fast outputs to put out approximately 300 mV peak-to-peak. Set th-e.
PG506 period to 100 uS. Connect the 50 ohm terminato.r to. the 4500 front panel
trigger input. Connect the PG506 o.utput to the 5U ohm terminator. Using the
TRIG SRC menu select EXT (external trigger). Set the oscilloscope to ~o
uS/div and 20 mV per dive Adjust the trigger COMP adjustment (C74) to obtain
the squarest possible squarewave. Replace the 50 ohm terminator with the RC
input standardizer. Adjust the trigger liP CAP adjustment (C73) to o.btain
the squarest possible pulse corners.
4-41
4500 Service Manual
CHAPTE~.S
THEORY
OF·OPE~ATION
INTRODUCTION·
The fo llowi·ng· paragraphs descrih.e the 45.00 Theory of Operat.i o·n .at .the funct i ona i ..
signal flow ·leve1by referring to the. block. dtagr.am~ Figure ~~fe Follow.ing t~is
description, each board is described· in detaiL at·· the c·.ompbnent· level· r.eferririg··
~o the appropriate schematic in Chapte~ 6;·
.
~. 4500 DIGITAL OSCILLOSCOPE BLOCK
DIAGRAM DESCRIPTION.· .
.
. . .
.
The fo 11 owi ng block di agram shows·· the ·major··syst~m· compon~nts and the passage
Not shown is the. control of the com.ponents whi ch is
of data among them.
effected from the MPU board to· the ADC.board, ··the· Sweep·a.nd Record board, the
Front Panel, the Floppy Disk Interface board, and t~e. I/O Options board via
the microprocessor bus.
.
4500 Overview and Signal Processing
The Gould 4500 is a dual-channel, digital-storage oscilloscope containing two
independent 8-bit analog-to-digital converters capable of sampling data at
frequencies up to 100 MHz. This section describes the theory of operation of .
the 4500 by following the processing of the analog inputs through the 4500 to
their display on the CRT screen. Following this, other aspects of operation
are descri bed.
Signal Input and Analog Steps
The analog signal to be measured, enters the 4500 through a BNC connector on
the front panel; is either AC or DC coupled; is divided in a programmable
attenuator by 1, 10, or 100; and then has subtracted from it an offset voltage. These steps are accomplished on the Attenuator board, and there are
independent circuits on this board for channels A and B. The offset voltage,
subtracted from each channel input signal, is generated by a digital-to-analog
converter located on the ADC board for each channel.
The analog signal from each channel is applied to an associated ADC board. On
the ADC board, the signal is voltage divided by a 1, 2, or 5 programmable
attenuator and applied through a track and hold circuit to the input of the
analog-to-digita1 converter.
5-1
4500 Service Maooa.i-.
,CHANNEL A
INPUT
DI,GITIZED CH. A
---..
.CHA
,
EXTERNAL
TRIGGER
---..
,
EXT TRIG
AnENUATOR
BOARD, '
CH'B
CHANNEL B
INPUT
---..
PLonER INTERFACE
'AADC,
'BOARD
..
'1
A+ EXTTRI(3'
CHA
MI;MORY
SWEE;P REGORD
BOAflb
J
DIGITIZED CH B
BADe:
,'SOARD
("'\..
CH B
MEMORY
TRIG
t
-
MAIN
INSTRUMENT
BUS
CONVERT STROBE
SWITCH
STATUS
FRONT-PANEL
KEYBOARD
DISPLAY
DRIVE
DISPLAY
DRIVE
45':10-325
CRT DRIVER
BOARD
MAIN
PROGRAM
MPU BOARD
GPIBiRS232C
INTERFACE
BOARD
cE
r I
FLOPPY INTERFACE
BOARD
GPIB/RS232C
INTERFACE
"l
I
I
I
L ~~T~~L~ ~
FLOPPY DISK
INTERFACE
"'--
Figure 5-1.
5-2
TO
REAR
PANEL
4500 Block Diagram
~~UO·Service
Signal Input and Digital
Manual
~teps·
.
.
When the ADC board recei ves t,he C.onvert. '''Strob~' s rg~al·from tfre~we'~p ,and Record
board, the track and hold 'goes into the' tto·ld· 'state. ":Th'e dua.l rank ADC then'
digitizes the voltage on 'the ·hold capa~it6r. ',Whel1,"the 8-bit 'd.igi·tcil.result is'
ready ,the' ADC sends it to theSweep·cf:nd:.R~cord· :Qo~rd ·.-fri: the: f'orm'of dffferent i al·.E.CL signals. A IIdata reapy" strbb,e:' Js"al"so's'ent "at:thfs ti meta the
Swee'p 'and Record board. The·dat.a:,'at thfs'··po.intts:Gr,aycoded',in the' high order
4 bits:'a~d '.folded binary in t:he .low.order·4 bl·ts. ...
.
.
The Sweep and Rec'ord board conta ;'ns tw'o hi ghs·peed .rii~mor·i es tq . store data trom
each channe.l. Each .me·m·ory has" s.torage·. for IOOO .B~.bi t ,bytes', however' these hi gh
speed memo~i es. can bO~hbe s~et. uP'. to '. ~ecord' fro·Qnl. the... ~ame( channe 1 A or cha~ne 1
B)
ADC. Th1S allows·a' ..m~mory
used.
'. . -' . l~nyth.of.
...... 2.000sa-mples
... . '.. .when
. only one channel 1S
When the acqufs it i o'n of data .·stops ·(r·eJer t.o.. Time Base "control below), the
mi croprocessor reads the data froID the ·high spe.ed memori es, converts it to 21 s
complement binary, and stores it in the lower speed memOry on the microprocessor
(MPU) b o a r d . ' .. .
'.. ' ..... '.
An except i on to thi sis when the hi gh speed ·DM-jt 'o"utput is selected to be
active. In this case, the processor does not transfer the acquired data to
the MPU board memory, but instead activates the DMA circuit on the Interface
,Option (I/O) board. This circuit either transfers digital data to the direct
access DR-lIB interface connector, on the rear panel; or analog data, reconstructed by a DAC, to the AVERAGER OUT BNC connector on the rear panel. In
either case, the data ,is translated from the Gray code/folded binary to
unsign-ed binary (00000000 represents the lowest voltage, and 11111111 represents the highest voltage) during these transfers.
Processing and Display of Acquired Data
The microprocessor either transfers the data from the Sweep and Record board
directly into the microprocessor memory (MPU RAM), or it adds the data to the
previous contents of this RAM to implement signal averaging. Along with the
waveform sample values, the processor maintains waveform acquisition parameters in the MPU RAM. These parameters include:
• the length of the acquisition (1000 or 2000 samples),
• the pretrigger and postrigger sample rates,
• the trigger delay (time of the trigger event relative
to the stored waveform samples),
• the attenuation and offset voltage,
• the number of averaging sums (if averaging was selected).
This information is
before the waveform
example by changing
the new scale. The
used to adjust the waveform to the scale of the graticule
is displayed. If the scale of the graticule is changed, for
sensitivity or sweep speed, the waveform is redisplayed at
displayed waveforms are called traces.
5-3
4500 Service Manual'
The·processor .p=er{orms··"the ·waveform. ~rithmetic that generates the trace
. funct i o"ns ~+B,_ !\-B~' -A; ~.B,.etc·.·; . and the, selected interpol at i on mode DOTS,
LIN~A.R, o~ SI~.E.· The' d~ta~that re:sul:ts fr·om.·these processing steps are called
the ·trace b'uffers, aRd tne'se are' inputs, to ',the .process i ng steps whi ch communicate to the hardware trace generator ~iic~its,' and to the calculation of '
vo 1tages' at the 'cursors.'.' . ' ,
'..
.
The hardware trace ,geflera-tor c i rcui,tsprodu'ce'a di gi tal output. synchroni zed to
the vertical scan rate of the CRT •. ', Thi"s.digita1 o~tput is m'ixed ,with the'
outputs from the·ch~racter.genefatorand the graticu1e generator to form the
pixe10n/off signal, sent to the CRT drfve ~ircuits o,n the.CRT Driver board.
The tra'ce,.charac't:er,·.and.graticule ·generators"are all controlled'. by the
p-rpcessor, and' share thesa'me dynamic RAM that t"he MPU uses. Regul ar access
of dynamic RAM by' the display generators satisfies the RAM refresh r.equire-.
'
.
ments.
Time Base Control
The Sweep and Record board contai ns the' time base control c i rcui try. Thi s
cons i sts of a IOO-MHz crystal, controlled osci 11 ator; a programmable frequency
divider the output frequency of ~hic~ is switchable at the trigger event for
dual time base recordings, arid' a trigger delay counter. The Time Base Control
circuitry also generates the' Convert Strobe signals which are sent simultaneously to both ADC boards. ,
When the trigger event occurs, the trigger delay counter counts upward at the
sampling frequency, from the value preset by the processor prior to being
armed. When a count of 999 is reached, this "top count" stops acquisition.
No further Convert Strobe signals are sent to the ADC and the processor
detects this by polling a port on the Sweep and Record board that indicates
the acquisition is complete.
Triggering
There are five trigger sources available: channel A, channel B, external,
line, and manual. The first three trigger sources are user input signals; and
trigger level, slope, AC/DC coupling, and frequency dependent filtering are
selectable for these. Trigger level, slope, AC/DC coupling, and filtering are
not selectable for the last two trigger sources (line or manual). Channel A
and channel B have their own trigger DACs (digital-to-analog converters) to
supply a trigger voltage reference, and their own trigger slope, coupling and
filtering selection circuits. These are located on the ADC boards except for
the AC/DC coupling function which is on the Attenuator board. Channel A
circuitry is used for external triggering except that the external trigger
input has its own AC/DC coupling components.
The trigger output pulse from the channel A ADC board is Sent to the channel B
ADC board, which either passes it on to the Sweep and Record board, or blocks
it and substitutes the channel B trigger output pulse if the channel B trigger
source is selected.
5-4
·':
4~'OO
Service Manual
Line trigger is a 60-Hz signal develo.ped'in".ttig po:w'sr, supP,ly,.and :sent to"the'
Sweep and Record board. Manual trigger 'i s a s i gn'al q'eve 1oped ~by.t.he'MPU when
the MPU wri tes to a port on the Sweep and Record board, in response", fo, th~ "".
front panel MAN TRIG button being ,depressed.
"
,
The Sweep and Record board w;ll"n'o.t,'accept,~'trigger sfgnal"unti'l'aJter 'it
is armed and a memory fl ush ;'s c'O,mpl ete. Ttits ensures: lhat no. data in' memory
remains from a previous recording.' 'Flush:is only reqtiiredand'im~lemented '
when a' recordi ng is to contai.n pretri gger data.
'
.
.
.
. . ;
.."
' .
.
.
.
.
.
The Sweep and Record 'board 'm,ay a1s:b be: prbgrammed by the processor 'to' imp] ement auto-triggering. When'enabled, auto~trigge~ingtaus~~ 4 trigger to 6ccur.
automatic'ally if no other trigger:e'vent occurs' withinapproxtma,tely'100milli-.
seconds after t,he ,compl etton of, the flush.
'
Processor Operation"
Control of the 4500
stored in 64k bytes
the MPU board along
CMOS RAM, interrupt
/
is performedbya~ 8b88 micropro~essor executing a program
of EPROM located 'on fhe CRT board. The 8088 is located on
with 16k bytes of dynamjc 'f pi n 9 to go low.' Thi s
.inhibits the ~isplay of gratic'ule and trace pixels. The purpose of this i"s to
prevent the disp-lay of trace and graticule pi~elsfrom obscuring the characters.
.
.
.
Graticule Generator
.
.
Before the display of each' scanlinebegins, a 74LS399. U5E stores 4 bits of
data from the dyna'mic RAM. These bi ts .represent whi ch of sixteen poss·i b1e
graticule patterns tb draw on the scanline.These bits are inputs to a 1K X 8
PROM, U2F. The PROM also receives signalsT3 through'T8 as inputs via flipflop U2E. The T3 through T8 bits ~epresent. the current position of the scanline.on the CRT as it is being drawn. The.PROM pa~allel loads the pixel
'i~formation representing the graticule pattern, into shift register U1F.
The
shift register outputs the pixel information serially to produce the graticule
video data ..
Oscillator and Clock Generation
The clock oscillator consists of transistor Q1, crystal VI, and associated
circuitry. It oscillates at 40 MHz and is divided by U2B, to produce two 2UMHz clocks that are the inverse of each other, and two 10-MHz clocks that are
the inverse of each other. The 4U-MHz signal is also divided by 3 in a 74S112,
U7D; and passed to the 8284 clock generator, U11D. The 8284 produces the
4.44-MHz processor clock with a 1/3 duty cycle. The 10 MHz is separated into
five phases of 2 MHz by a 74LSl12, U12C; and by a 74LS195 shift register,
U14C. The fi ve phases are signa 1s KO, K1, K2, K3, and K4. These are used by
U13B and U14B to generate the RAS*, CAS*, WRITE*, and R*/C signals that control
the dynamic RAMs.
Display Tilling
Counter UID and U2D generate signals T1 through T8 which count vertical
position, from 0 to 255, during each scan1ine. Top count from this counter,
(U1D pin 15) causes vertical blanking to be generated (U8C pin 6) which
then causes vertical sync to be generated (U8C pin 9); and also increments
the counter that counts which scan1ine is currently being drawn (U8B, U17~,
and U18B). This scan1ine counter counts from 12 to 511, generating signals LO
through L8. Top count from this counter (U18B pin 15) generates horizontal
blanking (U9C pin 6), and horizontal sync (U10D pin 4).
A 74LS161 counter UIIC counts starting at the bottom of each scanline to
generate the signal GRAT LATCH. This signal is used to latch dynamic ~AM
data into the graticu1e generator.
i
i
5-12
4580 Service Manaa1,
CRT BOARD, EPROM MEMOR Y
(Refer to schematic 0285~0051t sheets 2 and 3)
The fo 11 ow; ng paragraphs des:crlbe'the CRT board at the detai led 1~ve 1 •
Overview
The CRT board i ncl udes the EPROM' memory whlch conta'ins the 'microprocessor
software. The board operat'es wi th either :s ixte'en 2732 (4K X '8) EPROMs or
eight 2764 (8K X 8) EPROMs. Sixteen~otkets a~e '~rQvided;,ei9ht'!28 pin~ ~nd
eight 24 pin., When 2732 EPROMs are usedt'those eight'which go. into 28-'pin
sockets are, loaded wi th socket pi ns 1 t 2t '27 ~ and 28 1e'ft unfi 11 ed. Jumper
pads El-£2 are connected to,enable op~ratiorr with 2764s t but are left open
for 2732s~'
,
CRT EPROM Operation
The MPU board generates addresses AU through A19 t 'and the read signal RD*.
These are buffered by U37 t U38 t and U39 on the CRT board. The EPROM is
addressed when A16 and Al7 are high and RD* is low. This decoding is done ~y.
AND U19 and U42 (2 NAND gates). The decoder generates an onboard RD* signal at
U42 pin 6. The onboard RU* signal latches the address into U38 and U39 t pulls
low the output enable lines of the sixteen EPROM devices U21 through U36 t and
enables the data bus driver U13.
Latched address lines A12 through A15 are decoded in the two 74LS138 decoders
U40 and U41. One of the output 1ines t from these two decoders, selects the
EPROM to be read by pulling its chip enable line low.
SWEEP AND RECORD BOARD THEORY OF OPERATION
(Schematic 0285-0261)
The Sweep and Record board consists of six subsystems as follows:
1. Memories (A and B)
2. Memory timing generators
3. Record control
4. Sample rate counters
5. MPU interface
6. Plotter interface
Each subsystem is described in detail in following paragraphs.
Memories (A and B)
There are two memories with a capacity of 10au samples each. In dual channel
mode one memory records data from channel A and the other records dat3 from
channel B. In single channel mode the data from the active channel is routed
to both memories, permitting a recording length of 2000 samples.
5-13
4500 Service Manual
Each mem.ory 1.s" div"ided" into two banks. Each bank is divided into two phases.
"In dual,channel mode, sutcessive samples from channel A are placed in alternate
phases 9f "one bank of channel A memory until the bank is filled, then successive samples are plac:ed ion alternate phases of the other bank of channel A
memory" unti 1 "fill ed. Sampl es from channel "13 "are stored in the channe"l B memory
in the same" manner.""
In single channel mode, the samples from the"actiye channel first fill one
memory as descrfbed above (i n alternate phases of one "bank,- .then ina 1ternate
phases of the second bank), then fi 11 the other "memory" as descri bed above.
Two phases are used so that samples taken every 10 nanoseconds can be recorded
in ICs with access times slower than 10 nanoseconds.
Differential ECl data:fro.m the ADC boards, is transferred via the mother
board, and is received on the Sweep and Record board by the 10115 s at U2F,
U3F, U4F, and U5F (see schematic page 1). The outputs of the line receivers
are applied to both the A and the B memory systems. The A system will be
described here. The B system is identical.
1
Channel A Memory
The memory has two sets of input latches or "pre-memories" which are clocked
alternately by the signals lAAI and LAA2. lAAI and LAA2 are derived from the
DATA READY strobe which comes from the ADC (see schematic page 6). This two
phased system allows the use of RAMs whose write cycle is longer than the
fastest sample interval of the instrument (10 nanoseconds).
Notice that each phase of the system has two sets of pre-memories whose outputs
are wire ORed.
When in dual channel mode, or in single channel mode with A
only selected; rcs U3C, U3D, U5C, and U5D (see schematic page 1) are disabled
by the signal AA, and channel A data is applied to the memories via U2C, U2D,
U4C, and U4D. In single channel mode with B only selected; rcs U2C, U2D, U4C,
and U4D are disabled by AA*, and channel B data is applied to the A memory.
Each ohase of the memorv contain~ two banks of two 10422~ 256x4 Eel static
RAMs.' Each time" the ~ddr~~s- ~ou~t~"r- comp'-et-es 250 count"s, the 10141 at Ull3
reverses the state of the bank select inputs to the RAMls. The next 2bO
samples are then written to the other bank of RAM's.
5-14
4500 Service Manual
In dual channel mode, the two banks in each memory are a1ternately·enabled,
causing the memory to wrap around .at the end of 1000 samples. In s.ingle .
channel mode, after 1000 samples, both banks of the A meino·ry are di sabl edwhi 1e the data is bei ny recorded fn the B memory. The B m·emory is di sab 1ee
whi 1e wri t i.ng to the A memory~
.
.
Addresses for phase 1 are provi~ed by the two 10016 counters a~ 01A ~nd U2A,
and the bank select bits for phase 1 are provided by the 10141 ~hift register
at IB~ Jhe outputs of the courite~s ~nd the shift register ar~latched in the
10186 ICs ~t U1Cand· U1D. The ou~puts of 1hese latches ar~used to address and
bank select ph·as·e. ·2.
Not i ce th~t th~ 1o.w· order counter (U2A) is preset to
0110 when the. entire counter reaches its top·count. This cause~ ~~ch bank of
each phase to be. 2S0 samp1 eslong i tistead of 256, for a total memory 1ength of
1000 sampl es p·er· channe·1 •.
The outputs of each bank Qf RAM are wire ORed. The ·block select signal determines which set of out~ut~ will be active when the RAM is read from, just as
it selects the active bank when. the·RAM is written to.
The outputs of each phase of the A memory are mu1 ti plexed. with the outputs of
the same phase of the B memory. Multiplexing takes place in U6f, U7F, U8F, and
U9F (see schematic sheet 6). Signals controlled by the microprocessor are used
as the select inputs of the multiplexers. These select the data to be read by
the MPU. The data to be read is shifted to TTL by U10F and U11F. The data is
gated onto the MPU bus by the LS244 at U12F, or sent out connector J2 pins 3542 to the DMA circuitry on the Interface Options board.
Memory Timing Generators
The OATA READY signal is transmitted from each ADC to the .Sweep and Record
board with each riew sample. These strobes are received differentially in the
10115 line receiver at U1E (see schematic sheet 6). Channel A operation will
be discussed here. Channel B operation is identical.
The DATA READY signal is divided into two control strobes, (LAA1 and LAA2)
which are half the frequency of the DATA READY strobe, and are 180 degrees out
of phase with each other.
These signals drive the two phases of the memory
system. When in dual channel mode, or in single channel with A only selected,
this division is accomplished in the 10231 at U6D.
When single channel B
only mode is selected, U6D is held reset by the signal AA*, and the channel A
control signals are driven by the channel B strobe via the 10231 at U6E. The
outputs of U6E are wire ORed with the outputs of U6D.
The leading edges of LAA1 and LAA2 latch new data into the pre-memories,
advance the RAM address for the appropriate phase, and fire a chain of one
shots (U7D, and U7E) which generate the write enable signals for the RAMs.
5-15
4500 Service Manua1·
!wo one-shot.s ar.e" .re.quired:·to. generate' each write enable signal at the proper·
time. To use phase 1 of 'ch~nnel :A ·as and example., the leading edge of LAAI
clocks.one 'half ~f.the·l0231 a~ U7D. The output of U7D at pin 2 is a negative
going pulse whose wtdth is.controlled by R112 and C46. The trailing edge of
this pulse clocks the other half of U7D whose output at pin 15 is the write
enable.signalfor the RAMs.· .. R7~ and ~47 control the pulse width of the write
enabl e s·i gnal •.. This arr.angement ·.a-1 lows prec i se control of the pos it i on of the
write enable signal. r~lative tot~e ch~nge in the data and address.
.
.
' . '
....'..
.
.
.
When the.mic·roprocessor is ready.to read the data that has been recorded it
sets REA~ MODE true. Thi~ causes the write enable flip-flops to be held in a
set state.
Record Control
The Record Control circuits consist of :the tr·igg·er selection and synchronization flip-flops; and the t.rigger delay counters, which position the end of
the recording relative to the trigger.
The output at pin 2 of the 10231 flip-flop at U16A (see schematic sheet 3) must
be set to enable the start of an ·accfuisition. This is accomplished by either
an MPU control pulse, or by being clocked by an EXTERNAL ARM signal. The other
half of UI6A, which i~ controlled by the MPU, disables the external arm
function. After U16A pin 2 is set, trigger acceptance is held off by flip-flop
15A .l)nt i 1a. full rotat i on of the memory address counter is detected by pi n 6 of
f1ip-f.lopUI7B. This guarantees that memory contains valid data, even if a
trigger is received immediately and the trigger delay is short.
When U15A pin 3 goes low (see schematic sheet 3), the clock inputs of U14A are
enabled. The 0 inputs of the flip-flops in U14A are the trigger source
selection si~nals from the MPU, which are clocked through by the trigger
pul ses tomi ng out of U18C pi n 14. The outputs of UI4A, are wi re ORed wi th the
output of the auto trigger timer made up of UI7A, U20A and U19A. The signal
at this node is called ACQUIRE. ACQUIRE is synchronized to the sample clock
in the 10231 at UI3A, and the complement output of this flip-flop (ACQUIRE*)
is used to control the sample rate switching and the delay counter.
There are two modes of operation for the circuit after ACQUIRE* goes true. If
the user has selected any amount of pretrigger recording, the MPU control bit
PRE*/POST is set low. This, along with ACQUIRE* going low causes the output
of the 101Q2 at U166 pin 14 (see schematic sheet 3) to go high. This makes the
signals SPEED and SPEED* (U186 pins 2 and 3) change state, changing the sample
rate to the one selected for post trigger recording. Sample rate switching
will be discussed in detail in the Sample Rate Generation section below.
ACQUIRE* also enables the trigger delay counter (UI6C, UI7D, and U16D) which
was preset by the MPU to the complement of the number of samples of delay
required. The rollover of the trigger delay counter clocks the 10231 at U186
pin 9, causing signal EOA to go true. EGA is ORed with the rear panel EXTERNAL
CLOCK GATE signal (see schematic sheet 5), and is applied to the input of flipflop U20F. When the next sample is recorded, EOA gated with EXTERNAL CLOCK
GATE is clocked through the 10231 at U20F. The output of U20F at pin 2 is
signal EOADEL which gates the ADC strobes off, terminating the recordiny.
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4bOO Service Manual
If no pretrigger recording is needed t . PRE*/PQST ;'s' s~t, high· by the'.MPU', This.
prevents ACQUIRE* from changin~ the state of SPEED and SPEED*~ and ,thereby
prevents sample rate switching at this time. The dela~·c9unt~~ i~ eha~le&
however. The counter counts up to its top count at ~he pretrigger sample rate t
fro~ a preset count calculated by the MPU. ·When t9P c9un~.isreathedt the
rising edge of the TC* signal at U16C. p.iO'. 4~. {see' schematic page· 3)t clocks. the'
fl i p-f1 op at U18B t causi ng SPEED and SPEEP*·· to change ·state·.· Thi s' switches th~
time base circuits to the post trigger. sample rate. The·d'el.aycount.er counts
at the post trigger sample rate for 1000 count~~··atwh{ch: time .the·n~xt rising
edge of TC* again clocks U18B and causes 'EOA·.to· g:o tru.e.This bey; n~' t~e 'end
of record sequence as described above. The us~ 'ofad~a1 countin~ rate, with
the pretrigger rate being.slow, allnws for trigge~ delay. times 'much longer then
'1loul d be pass i b1e .wi th: th~ same counter operated ~t the post tr; gger rate only.
The clock for the delay counter (SA'MPlE 1) is gated throuyh·the.· 10102 at U16B
(see schematic sheet ~) by t~eoutput of a 10231, U13A pin 3. When single
channel mode is selected, U13A ·divides·the sample rate by two, causing SAMPLE 1
to be hal f the sampl e rate. Thi s .allows the' doub·1 e 1ength memory associ ated
with single channel recordings to be completely filled with data at the post
tri gger sample rate, even though the counter' is on ly 1UOO counts long.
When operating in Roll Mode, the signals BYTE MODE and ROll MODE are set true
by the MPU. This disables the delay counter. Roll Mode recordings are
terminated under MPU control.
BVTE MODE places a high on U20F pin 10 (see schematic sheet 3), the D input of
a 10231 flip-flop. The signal SAMPLE 2 clocks U20F pin 11, generating an
interrupt request to the MPU. The MPU then reads the new data. Reading the
ADC data resets U20F until the next sample is recorded.
Signals ARMED, ARM DEL (indicates a flushed condition), ACQUIRE, and EOA are
available for record control status monitoring by the MPU. This is via the
10104 at U158 (see schematic sheet 3). MPU control signal IIREAD 1" enables
this information onto the ECl data bus where it is wire ORed with the outputs
of the high speed RAM data multiplexers.
Sample Rate Generation
All internal sample intervals are derived from the 100-MHz oscillator which
consists of Q2, VI and associated parts (see schematic sheet 5). Variable
capacitor C102 permits fine adjustment of the oscillator frequency.
An external clock source can be substituted for the internal oscillator under
MPU control. This selection takes place in the 10111 at U19F.
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4bOO
Servi~~
Manual
The 100-MHz signal from the oscillato~ :is'applied to the clock input of the
10016 synchronous binary counter ,at, U19E.' The top count output of U19E is
applied as the ~lotk of a chain of decade ripple counters (U190, U19B, U208,
U20C, U21C, and·U20D) and to one of :the, 'data inputs of the 10164 data selector
at U20E. ,The other inputs to' U20E are the outputs of the decade counter cha in.
Ctintrol bits from the MPU for the pro~rammable counter and the data selector
are stored in ihe 10153 quad latches at U18E, U180, U21E and U21D. These
latches have gated outputs which are wire ORled in pairs. The gating signals
are SPEED ,and 'SPEEO*.
When these signa 1s change state, as descri bed above,
new control information is presented to the count~r and data selector causing
the sample rate to change to the post trigger rate.
The selected sample rate is 'gated w~th EOAOEL in the 10H102 at U18F. The
outputs of U18F, pins 9 'and 15, are the AUC strobe which is routed to the AOC
boards differentially via the mother board.
An external CLOCK GATE signal is the applied, to U20F pin 7, a 10231. Pin 6 of
U20F is clocked by the sample clock~ When CLOCK GATE goes high, pin 2 of 20F
is caused to go high by the sample clock. Pin 2 is wire ORed with EOADEL which
gates off the signals SAMPLE 1 and SAMPLE 2. This inhibits any more samples
from being recorded until CLOCK GATE goes low and is again clocked through
U20F.
When the microprocessor reads the memory, both internal and external clocks are
disabled. Each read of the high speed memory generates an R SAMPLE pulse (see
schematic sheet 3) which '" ~robes the AOCs and is returned to the memory system
as DATA READY strobes. 111i s increments the memory addresses.
MPU Interface
Three 74LS'38 ICs at U130, U14D, and U14C (see schematic sheet 4) decode the
MPU address bus; and RD*, and WR* signals. The outputs of these decoders are
used in two ways. Some act as latch enables to write the contents of the data
bus into holding registers such as the 10153s which hold the sample rate
control dataQ Others act directly on the Sweep and Record circuits by generating signals such as MANUAL ARM, MANUAL TRIGGER, and FE RESET.
Octal latches U14F and U15F hold the static mode control bits.
All TTL signals which must interface with ECL circuits are level translated in
10124 level translators.
The ECL data bus which carries the Record Control status and the output data
from the high speed RAM is translated to TTL levels in the 10125s at U10F and
11F (see schematic sheet 6)= The outputs of the translators drive the circuits
on the Interface Options Board via the mother board, and the inputs to the
74LS244 buffer which drives the MPU data bus.
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Service Manual
Plotter Interface
The PLOTTER X and PLOTTER Y output f~ric;tions ar-e provided by two ~E!)018 8-bit
DACs at U16F and U17F (see schematic she~t.4). The NE5018'ha~" its ·own
internal latches for digital data from th~ MPU. Address decoding is provi~ed
by the MPU interface circuitry to load the dafa. into"theinternallatches.
This address decoding circuitry also allows storing the PEN LIFT signal into
the 74LS~73 static control register at U14F.
ADC BOARD THEORY OF OPERATION
(Refer to schematic 0285-00S6)
The following paragraphs present the theory of operation fotthe"AOC Soard at
the detailed schematic level.
AnC Board Overview
The CHA and CHB boards are identi~al except that link W8 is cut for address
decoding of CHA, link W9 is cut for decodtng CHB, and the components for the
external trigger function are only on the CHA board. The links are shown near
U59 on sheet 13 of the schematics.
The ADC board contains the following:
• A programmable attenuator and two amplifiers to present the analog
input signal to the track and hold,
• A track and hold and its associated pulse generator,
•
A track and hold to AOC buffer amplifier,
•
Eight folding amplifiers, an analog combiner, and a digital decoder
for the first part of the AOC,
• A four-bit flash converter and associated latch for the second part
of the ADC,
•
A pulse generator to drive the latches and track and hold,
•
LEO drivers that indicate if the input signal is inside or outside
full scale range,
•
A set of reference voltage sources for the AOC and offset generators,
•
Trigger source selector, adjustable trigger level reference
voltage source and trigger comparator,
•
Adjustable voltage sources for input offset, offset correction, and gain
correction circuitry,
•
•
Microprocessor interface,
Power supply regulation.
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4500 Service Manual
Progr~able Attenuat~r
(Refer to schematic
st1~et
1)
The si.gna1 from the Att~nuator board, is applied via coaxial cab1~to J2,and
then- to RPi, ·whichw·ithre.1ays K1, K2, and K3~ forms a programmable 1,2,5
attentJator. The full scale sensitivity of the 4500 is adjusted by the settings
of.this attenuator and the 1M ohm Input Attenuator on the Attenuator board.
The gai·n from the front panel input: BNC to J2, with the input attenuator set to
Xl, is approximately X2. The output from the relays is fed to Q1, pin 2, which
. is part of the first amplifier. The full scale sensitivity at this point is
160 mill i volts.·
.
First Amplifier
(Refer to schematic sheet 1)
Op amp QI, transistor array U2, LJ5,Q6, Q2, and Q4; form a non-inverting
feedback amplifier with a gain ·of approximately 5.86. The dual matched FET QI,
and the differential pair in U2, amplify the difference voltage between the
input and the feedback from the output via R29, and R15. The amplified error
voltage across RI8 drives the output via emitter followers Q2, and Q4. Source
currents for Ql are provided by the transistors in array UI. Current for the
differential pair in U2 is adjusted by potentiometer R12. The Op Amp in U3
connected to R12, monitors the difference between the voltage on R9 and the
voltage on the wiper of R12, and via R7 and the emitter follower in U2 reduces
this. to voltage to zero.
A similar arrangement enables the voltage at the top of collector load R20 to
be set by R34, an op amp, and emitter follower Q5. The voltage at top of
collector load R18 is set by R21, an op amp, and emitter follower Q6. The
overa 11 ga in of 5.86 is set by R25.
With zero input voltage, the required output voltage of 3.96 volts is set by
current source Q3 to approximately 4 milliamps. This is accomplished byadjusting potentiometer R35.
The internal trigger pickoff is provided by the attenuator comprised of R48,
R663, and R56. The 3.96 volt offset at the output of the first amplifier is
removed from the trigger path by the voltage drop generated by current source
Q7 across R48. This is adjusted to approximately 7.7 milliamps by R30, to
bring the voltage at the top of R663 to zero. Gain of the internal trigger
channel is adjusted by R663.
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4500 Service Manual
Amplifier
(Refer to schematic sheet 2)
Second
Transistor arrays U5, and U6; and transi,stors Q8,-and, Q11; form' a shunt feedback ~mplifier whose gain is set to 1.6 by feedback~~~i~torR95 ahd i~put,
resisto~ R94.
The junction of ~94 and ~95 is a virtual ground point. -The
difference i n vol tage between the output of -op amp U4, 'pi n 7-, ,and the vi rtua 1
ground is amplified by the differential ~mplifier connection of transisto~
arrays U5, and U6.
'
The amplified error signal at collector load R87~ 'fs applied via'emitter
followers Q8, and W11 to one of the output-loadresistors~ R106. A balance of
currents is set up at the"virtualgroundsuch- that the input current in R94,
which is approximately 11 mllliamps, plus- the current in R95, is equal to the
current set up in current source Q10. With the ~irtual ground at -7 volts, and
an output voltage at the top of R106 of -4~5 V, 'Q10 current will be approximately 12.4 milliamps. This is adjusted by R76.
Op amp U4 (pins 12, 13, and 14) monitors the voltage difference between source
of Q10 and the wiper of potentiometer R76. Feedback via R90 reduces this
difference to zero. Similarly, Op Amp U4 (pins I, 2, and 3) sets the current
in transistor array U6, by R59. The virtual ground voltage is set by Op Amp U4
(pins 5, 6, and 7) which is connected as a shunt feedback amplifier whose input
is the +10 volt reference. The ratio of R63 to R62, together with the feedback
action, produces 0 volts on pin 6, and -7 volts on pin 7. The voltage at the
bottom of load R106 is set by a similar circuit using op amp U4 (pins 8, 9, and
10) and R82, and R80 as feedback resistors. The output at U4 pin 8 is buffered
by emitter follower Q9.
The voltage difference across R106 is set by R8U to approximately 1~2 volts, to
set about 50 milliamps in RI06, output transistor Q1l, and Rl17. Resistor Rl17
in the collector of QI1 is equal to R106 so that the signals at the emitter and
collector of Q11 are equal in amplitude and out of phase. The collector output
provides the signal to be sampled by the track and hold bridge, while the
emitter signal and the collector signal buffered by emitter follower Q78 are
also used by the track and hold circuit.
Track and Hold
(Refer to schematic sheet 4)
The diode bridge CRY can be in one of two states, heavily conducting with
current supplied by T1, or reverse biased by a voltage supplied by T1. In the
conducting state the bridge presents a low impedance between the signal input
and hold capacitor C70, of about 10 ohms, so that the voltage on C70 tracks the
signal voltage.
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4~OOService Manu~l
In the reverse biased sta·t~.,. "the. bridge. is a high impedance. Residual capacit i ve feed ttl-rough is ba'l anced out ·by. the ,i, nj ect i on of an ant i phase signa 1 vi a
R715, and C67 •. Fast current· .switch. Q13, Q76, Q15,and Q77; turns diode bridge
'CR9 on and off. AnBO-mil1iam~ ~urr~nt source, made up of Q16'and U7 (pins
12, 13, .14); provi des current, to d.i ffere!1t j a l pa i r QI5/Q77. A balanced ECl
signa 1 j s app 1i ed through T3 to'· art:'p 1i fi er :-017/Q78; whose output is connected by
T2 t6 Q15/Q77~ so that the SO·milliamp current can be diverted through either
Q15 or Q77. I f the base ofQ15 i.s po's 1-ti've w'i th respect to the base of Q77;
current flowsthr6ugh Q15, and 'Q13; and splits about equally through path T1,
CR9, Tl, R129~ 'R130 and path R131, R132. The forward voltage drop across CR9
reduces the bridge current to about 34 milliamps.
A current sink of appro'xi mat ely 100 m"illiamps, Q12; provides current to emitter
follower Q78 (schematic sheet 2), and also balance$ the SO milliamps through
Q13 such that no current flows out of the bridge into the signal source. The
currents and voltage drop's' in·the four arms of the bridge are then equal; and
the junction of R129, R130, R131, R132 is about +2.4 volts relative to the
signal input. If the base of ij15 becomes negatiVe with respect to the base of
Q77, the SO milliamp current is dive~ted into Q77/Q76. No current flows in the
bridge or R131/R132 and SO milliamps flows in R129/R130. The voltage at the
junction of R129, R130, R131, and R132 is unchanged so that a reverse bias of
4.S volts centered about the signal voltage is applied to the bridge via T1.
The bootstrap emitter follower, Q7S (schematic sheet 2); and T1 reduce loading
effects on the signal path; and T1 further balances the drive to CR9. Current
source Q12 is set with R104 acting through U7 (pins S, 9, 10). In normal
operation the system works in the track mode until a sample is requested by a
pulse from the Sweep and Record board. The hold mode is then entered for a
period of 7 nanoseconds. At the maximum rate (100 MHz) the time in track mode
is reduced to 3 nanoseconds.
Track and Hold Buffer Amplifier
(Refer to schematic sheet 3)
The sampled signal voltage on C70 (schematic sheet 4) is applied to the high
input impedance of the third stage feedback amplifier. This amplifier has a
non inverting gain of approximately 2.64. The circuit is similar to the 1st
amplifier with Q14, a dual FET, and a differential pair in U8 forming a differential amplifier whose input is the error between the voltage on C70 and the
attenuated output voltage returned via potential divider R411/R408. The
amplified error voltage at collector load R397 drives the output through emitter followers Q43 and Q44.
Current sources for the dual FET are provided by transistors in U9. Current in
US is set up by R427 and op amp U32 (pins 12, 13, 14). Similarly, the voltage
at the top of coll ector load R11S is set by R422 and Op Amp U32 (pi ns b, 6, 7);
and the voltage at top of collector load R397 is set by R404 and op amp U31
(pins 8, 9, 10).
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.4bOO Service Manual
Quiescent voltage at the output· (the junctibn.··of"R412
be zero for an input quiescent voltagi of·-1.2 ~oltS.·
through R407 into the feedback network achieves .this,
R424. Current in the output transistor ~44 {s· set "by
14) and Q45.
and R411). is required to
A curren~ source applied
and is adj u"Stab 1e by .
o~ Amp U31 (pins 12, 13,
The feedback'from pin 14 via Q45 an~'Q44 mak~s ihe voltage on pi~ 12 ~q~al to
that on pin 13. This makes the cufreht in Q44 independent of output voltage
for normal operation and adjustable with R414~'The'vQltage dro~ across R412 of
approxi mate 1y. 2.3 vol ts provi des enough coll ector 'vol tage fo:r. the' di fferent i a1
pair in U8. Gain is adjusted by R409, a shunt across R408. Pulse response is
set by networks C202, C201, R681; C200, R714; and also-feedforward via R722,
emitter follower in U8, C407, and R721 •.
Ana 109 to Di 9i ta 1 _Converter
(See Figures 5-2 .and
5-3~)
The AOC cons i sts of two bas i c parts:'
I.A set of eight folding amplifiers which produce the
first four most significant bits, and an analog residue.
2. A four-bit flash converter to produce the four
least significant bits.
The operation of the folding amplifier array will be explained with the aid of
the simplified schematic (Figure 5-2) and idealized waveforms in Figure 5-3.
Only amplifiers A and B of array A through H are shown in Figure b-2. The full
scale range is set by the reference chain running between +2 and -2 volts, to
be 4 volts total. The difference between Ref A and Ref B is 1/8 full scale or
0.5 volts. This gives a sensitivity at the ADC input of 15.7 millivolts for
the least significant bit (LSB).
For correct operation Ref A is placed 16 LSBs below the +2 volt reference. If
the input signal is more negative than Ref A; the output from amplifier Q1A/Q2A
is saturated; with Q2A taking all the current provided by R5, and transistor
QIA being cut off. This output drives PNP comparator pair Q3A/Q4A, called Comp
A, to generate a zero logic level.
As the input voltage increases, positive voltage VA moves from point X in
Figure 5-3, more positive, to a maximum (occurring when Vin=Ref A), then negative back down to level X. This occurs because the voltage at the emitters of
pair Q3A/Q4A, due to the diode action of their base-emitter junctions, will
equal the most negative collector voltage of WIA/Q2A plus one base-emitter bias
voltage. This bias voltage will be relatively constant as the current is
switched from Q4A to Q3A, being compressed by only about 20 millivolts at the
fold poi nt.
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4500 Service Manual
Ampl ifier Q1A/Q2A i's' set by the ratio of'Rl to R3, to have a gain of four from
the input to e'i the I" Rf Dr."' R2, so VA must change by 63 mi 11 i vol ts to change the
final digi~a1 o~tput by one LSB. The rounding of the response at the fold
point caus~s' les~" than one half LSB of errQr. For inputs more positive than
Ref A; the' Comp' A. output
wi 11 be "a ,1 .09i cone.
.
.
Folding amplifier B work'S ,in the same'way, producing a digital output labelled
Comp B Output, a'nd an analog output labelled VB. The analog outputs from all
the comparator,s are combined by the ac.tion of Q5A, Q5B, Q5C, ••• Q5H; to give
the final folded output called the Analog Residue. This will be the most
positive signal of the 'group VA ••• VH. The negative fold points are simi1ar1y rounded :by about' 20 mi 11 i volts.
The positive fold pOints occur at the switching points of Comp A, Comp B, etc.
For correct decoding of the folding amplifier array 'output into four-bits,
fifteen comparators are requi'red~' 'the seven comparators between stages (Comp
AB, COMP BC, ••• COMP GH) have th~i~,outputs aligned with the negative fold
points. For the A and B sections this is done by Q5A/Q6A, which compare the
inphase output of QIA/Q2A to the antipha~e output of Q1B/Q2B. The biasing of
this comparator (COMP AB) makes itsotitput change at point Y in Figure b-3.
Similarly, comparators BC, CD, •• '. GH give digital outputs at the other negative fold points. The fifteen comparator outputs are latched before being
encoded into a four-bit Gray code, and sent to the Sweep and Record board. The
analog residue signal is applied to a four-bit flash converter, the outputs of
which are similarly latched before being sent to the Sweep and Record board.
Detailed Description of folding Amplifier
(Schematic sheets 6,7, and 8)
Sheet 6 of the schematic shows the two most positive folding amplifiers of the
array, eight emitter followers that generate the final folded output, and the
second-rank four-bit flash converter. Sheets 7 and 8 show the other six folding
amplifiers.
Comparator #1 (schematic sheet 6), corresponds to folding amplifier A, comparator #3 corresponds to folding amplifier B, and Comparator #2 corresponds to
Comp AS in the Simplified Folding Amplifier Array, Figure 2. The signal and
reference inputs to all the folding stages are buffered by emitter followers.
For the comparator #1 stage, these are two transistors in array U34.
The signals then pass via TIl and provide HF balance to a differential amplifier
consisting of transistor array U71. This has emitter follower outputs driving
the folding PNP pair Q75/Q74. The folded signal routed from the common emitter
point; through R629 and L20; to QS7, an NPN emitter follower. The other folding
amplifiers drive similar NPN transistors:
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4500 Service Manual
2V
R2 = Rl
Rl
Q5A
10
Q1A
Q2A
INPUT
OUTPUT COMP A
FOLDING AMP
CIRCUIT A
REF A __- + - - - - - - . . + - - - - - . . . . . J
OUTPUT COMP AB
20
02B
01B
OUTPUT COMP B
ANALOG
RESIDUE
FOLDING AMP
CIRCUIT B
REF B
e--+------+----....l
OUTPUT COMP BC
i
ETC
45JCl-32n
Figure 5-2.
Folding Amplifier Array Simplified Sche.atic
5-25
:
450n Service Manual
2V -
+
16 LSS"#S,
REFA--;-~--~~----~------------~~---------------
:118 "F~S".=O.5V
RE'F B -"~r---------------~,f------+------------32 LSS'S
REFe--~---------~-----~~----~----------------
REFD----~~------~------~~--~~----------------
ANALOG INPUT
ANALOG
RESIDUE
OUTPUT eOMP A
OUTPUT eOMP AS
OUTPUT eOMP B
OUTPUT eOMP se
OUTPUT eOMP e
Figure 5-3. Folding Amplifier Array Idealized Wavefonms
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'4500 Service Manual
I f the output from comparator #1., is the :m:Qst. pas i t,i ve of all e.i ght comparator
outputs, Q57 will take all the current pro·vided. byR525, and the other emitter
followers will be cut off. The analog resid~e si~nal is level shifted and
buffered by CR33 and Q59 and then applied to the input of the four-bit ~lash
converter, U40. Comparator #2 is driven. by the inphase:output of comparaton #1.
and the antiphase output of comparator #3. 'It'consists 6fdifferential pair
connected array U70, whose output dr-ives the grounded base· PNP pai r' Q73/72.
The other folding amplifiers are similar to. the #1 stage~
.
Folding Amplifier Digitai Decode
(Schematic sheet 10)
Di fferent i a1 comparator outputs. 1 through '1~ are app 1 i ed to ECl different i a1
line receivers U74, U41, and U19. These in turn are connected to the D inputs
of the three flip-flops U75, U42,and U22. The latched output is encoded by
NOR U44 and U43 into a four-bit Gray code •.. The Gray code is app 1 i ed to a set
of final latches (Schematic sheet 11) before going to the Sweep and Record
Board.
Four-Bit Flash Converter
(Refer to schematic sheet 6)
U40 contains 16 comparators, a reference chain of resistors, and an encoder,
to produce four-bit binary code from the lower fifteen of the comparator
outputs. The output is ECl compatible. As the analog signal is increased
from the low reference level VR2 lOW (U40 pin 6), toward the high reference
level VR2 HIGH (U40 pin 5), the comparators are set in turn to output logic 1
levels, until all fifteen are on. This is internally encoded to binary 1111.
If the signal level increases to the high reference level VR2 HIGH, comparator
sixteen will turn on. Internal encoding then sets the binary output to 0000
and sets the overflow bit (pin 18) to a logic 1.
The folded analog residue signal applied to pin 4 normally falls within the
encoding range of the lower fifteen comparators, and even for signals more
positive or negative than the +/-2 volt full scale, the folding action ensures
that the residue signal will not be as positive as VR2 HIGH (See Figure 3).
During conversion of a high frequency signal however, large scale steps are
output by the track and hold circuitry, and ringing may cause the residue to
reach the VR2 HIGH level. This causes the overflow comparator in U40 to come
on, and the four output bits of U40 to be all zeros. The four output bits
being all zeros would cause a 15-bit error in the conversion. To minimize
this error, the overflow bit (logic 1) is ORED with each of the four output
bits to produce a 1111 result instead of 0000. OR'ing takes place in U79.
Digital outputs from OR U79 are sent to final latches (Schematic sheet 11)
before being sent off of the board.
The flash converter U40 has two modes of operation, controlled by the state of
the differential latch enable lines L (pin 9) and L* (pin 8). When L is high,
a change of analog input causes data changes at the IC output. When L goes
low, the data is held fixed.
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4500 Service Manual
U40 Pi n 15 ,i s the complement of the MSB output whi ch is U40 pi n 16. The
(pin 15) is taken vi~C238 to diode detector CR32, C237,
R520. Toggling the most significant bit .causes C237 to charge negatively.
This voltage is .used :b'ycomparato~ U15 pin 4 (Schematic sheet 11) to drive
the IIi n range lEn on the front pan~ 1.
'
compliment'~utput
ll
ADC Pulse Generator
(Refe~
to schematic sheet 5)
All conversion system pulses ~sed on the ADC are derived from a single balanced ECl signal that comes from the Sweep and Recor.d board. The conversion rate
is set directly by the pulse rate of this input which can be varied over a
large range. The maximum pulse rate is 100-MHz. The AOC produces a new output
for each positive edge on connector:Jl, pin 63. The input pulse is transmission-line terminated by R656 and R655 and is applied to differential line
receiver U77 pins 22 and 23. The non-inverting output of U77 (pin 5) clocks
flip-flop U78 to a logic 1.
.
The action of U77 (inputs 1 and 24), U45 (inputs 22 and 23), U45 (inputs 17
and 16), and delay line 01 produces a reset pulse for flip-flop U78 so that
the output is a 7nanosecond pulse. This is the IIhold drive to the track and
hold circuit. Specifically, the 2-nanosecond delayed negative edge from 01 is
applied to input pin 24 of U77. The balanced outputs of U77 (pins 2 and 3)
are connected to two RC networks. The rate of fall of the negative edge is
controlled by R718. The negative output is applied to one input (pin 16) of
NOR U45 (pins 10, 11, 16, and 17). The positive edge is delayed by filter
R651/C333 and U45 (pi ns 4, 5, 22, and 23) to the other input of NOR U45 (pi ns
10, 11, 16, and 17).
ll
The timing of these two inputs causes a narrow positive pulse at output pin
11, which resets U78. The leading edge position can be adjusted by R718. The
balanced IIho1d" pulse from U78 is taken via 100 ohm bifi1iar wire to T3
(schematic sheet 4) and terminating resistors R155 and R154. This is at the
input of differential pair W17/Q78 in the track and hold circuit.
The negative edge propagating in 10-nanosecond delay lines 01 and 02
(schematic sheet 5) produces all the other latch pulses for the AOC. A tap at
pin 8 of 02 takes the edge to the inverting input, pin 17 of U77. The positive edge at output pin 11 of U77 drives three 33 ohm lines: lSI, LS2, and lS3;
which are applied to the clock inputs of first rank latches U75, U42, and U22
(schematic sheet 10).
A tap at pin 5 of 02 (schematic sheet 5) takes the edge to input pin 21 of
U77, producing balanced outputs at output pins 8 and 9. The negative edge on
pin 8 is taken directly to input pin 20 of OR/NOR U45 (pins 8, Y, 20, and 21).
The positive edge from U77 pin 9 is routed via R661 and C338, and non inverting gate U45 (pins 1,2,3, and 24) to input pin 21 of U45. The delay between
these inputs causes U45 pins 8 and 9 to produce a narrow (approximately 2
nanoseconds) balanced output pulse with pin 8 going positive and pin 9 going
negative. This signal is labelled l on the schematic, and is the latch drive
to the four-bit flash converter U40 (Schematic sheet 6).
5-28
4500 Service Manual
The negative edge propagating in D~~(schematic sheet 5) is appl'~ed 'via tap 8
to input pin 15 of U77, producfng the 'bal~nced signal DR (data ready) on
output pins 12 and 13. This is applied via the edge'£onnector and motherboard
to the Sweep and Record board. The o~tp'ut OR also. clocks 'the fi na 1 1 atch on
the AOC (schematic sheet 11), which latches the full eight-bit data word.
Adjustment of the bias applied to pin 14 of U77·(schematic sheet 5) affects
the time position of OR relative to the, other latch pulses.
The timing of the latches is such thai the data clocked into the final l~tch,
is the same data that was clocked into the intermediate first and second rank
four-bit latches by the previous input strobe. An analog input signal can be
sampled and converted by one strobe, but the data representing that sample
will not be presented to the Sweep and, Record Board until the negative edge of
the next strobe passes through delay 1i-nes 01 and 02.
LEO or'ivers for In Range and Out Of Range .Indicators
(Refer to schematic sheets 10 and 11.)
The encoded 04 data line at the 6utput of U44/43 is taken to pin 17 on U22,
which is the 0 input of a flip-flop. The state of this input is clocked to
the Q output, pin 5, by clock LS3; which is one of the three first rank latch
drives. The output from pin 5, RGO, is AC coupled via C311 to diode detector
CR44, R645, and C321; so that toggling of 04 charges C321 negatively.
A similar circuit working on the most significant bit of the second rank,
produces a negative charging of C237 for toggling this bit (schematic sheet
6). The signals from C237 and C321 are taken to quad comparator U15. If the
voltage on C321 is zero; input pin 8 of U15 will be more positive than the
reference level set on pin 9 by R287 and R288; and the output of comparator
U15, pin 14 goes low pulling pins 2 and 14 to approximately -5 volts.
Similarly, if the voltage on C237 is zero, U15 output, pin 2 pulls pins 2 and
14 low. Under these conditions the voltage on connector J1 pin 76, the lIin
range" LEO drive, will be near zero volts and the LEO will be off. If toggling is taking place on both 04 and 05, the voltage on J1 pin 76 will be high,
and the IIi n range LEO wi 11 be on.
ll
The other comparators in U15 indicate if the signal in the ADC has gone more
positive than the most positive comparator, or has gone more negative than the
most negative comparator in the folding amplifier stage. This is done by
diode detectors CR45, C328, R646 and CR17, C153, R336 (schematic sheet 10)
working on the first rank latched output in U75, and U22. These present
signals R01, and R03 to U15, and are compared to the reference level at the
junction of R289, and R288. If the signal exceeds the prescribed range in the
positive direction, output 13 which had been pulled to -5 volts goes positive,
lighting the LEO driven by the voltage on J1 pin 73. Similarly, if J1 pin 75
goes positive, its associated LEO lights to indicate large negative signals in
the ADC.
5-29
450.U Service Manual
, Reference: Vol tag'e .Generaio,rs .'
(Refer tg.
schemat
i c ; sheet ~)
.
,
. ,
The primary 'reference is U65," a precision +10 volt source, with fine adjustment R56~ •. lh,i~ 'i.s used by one half of dual Op Amp U18 (pins 8,9, and 10),
connected' ·a~ an ·i nverter, to produce -10 volts. Thi s voltage is buffered by
op amp~U21 (pins8~ c9,and 10} and·Q35 connected in a source follower configuration,.' to p,roduce.the negativ,e supply voltage for the folding amplifiers.
The posii~ve' supply fbr the fo~ding amplifiers is similarly produced by op amp
U21 (pins 5, 6~'and7)and Q36 using the +10 volt reference as input. The +/2 volt refe~enc~s:forthe foldind amplifier array are derived from inverting
amplifier U21 (pins 1, 2, and 3) and its associated transistor Q33, and U21
(pins 12, 13, and.14)· and its transistor Q34.
.
For the +2 volt circuit, negative feedback around U21 (pins 1, 2, and 3)
creates a current balance at pin 2, which is a virtual ground point. Neglecting R321, current from the -10 volt reference through R178 and R200 is balanced exactly by current flowing to the emitter of Q33 through R319. The ratio
of R178 plus R200, to R319 is nominally b to 1, with variable R178 allowing
some adjustment of the +2 output voltage. AC feedback via C141 improves loop
stability. Current injected at the virtual ground point by R321 enables
slight modification of the reference by the Auto Calibration system. If Auto
Cal is off, current in R321 is zero.
The -2 volt reference is similarly derived by U21 (pins 12, 13, and 14) and
Q34, using the +10 volt source as input. The ratio R179 plus R201 to R328 is
5 to 1, with R179 adjustable, and Auto Cal adjustment through R330.
Reference circuits for the second rank flash converter are U18 (pins 12, 13,
and 14) with Q32, and U18 (pins 1,2, and 3) with Q31. Reference VR2 HIGH is
approximately +1 volt, adjustable by R180. The circuit is similar to the +2
volt reference, using the -10 volt reference as input, and R18U for adjustment. Reference VR2 LOW is approximately zero volts. A similar circuit is
used, this time with inputs from both the +10 and -10 volt references, to
allow R181 to set VR2 LOW with a +/-200 millivolt range of adjustment. Auto
Ca 1 input is vi a R3U2.
Currents for the eight folding amplifier input stages are set by quad op amps
U12 and U20, and potentiometers R170 through R177. To understand the operation
of these current-setting circuits consider the folding amplifier with the most
positive reference, U71 (schematic sheet 6). The output of Op Amp U20 (pins b,
6, and 7); acting through R673, R636, emitter follower U71 (pins 12, 13, 14),
R672, and R325; forces the voltage at pin 13 of U71 to be equal to the voltage
on the wiper of R177. Adjustment of R177 then controls the current set up in
U71 (pins 12, 13, and 14), which is the current source for the differential
amplifier. The 9ther seven circuits are similar.
5-30
_~bOU
Service Manual
Trigger Generator
(Refer to schematic sheet 12)
The signal picked off the output of theADC input. amplifier ·(sc~emati~ sheet
1) by divider network R49, R663, and R56; is fed to relayK4·. If"K4.is closed
the signal is DC coupled to the input r~sisto~, R35i~ Qf~he·hi~h iriput
impedance tri gger buffer amp 1 i fi er Q37, Q3B, 'and Q39 • . If ·the. relay is open
the signal passes through the AC coupling c~pa~itor C157,.to R351~·· Dual FET
Q37 is arranged in a totem pole circuit such that if t.he:FET~w~r·e identical,
and R352 was equal to R359 plus R360, the:yoltage at pin6 'of Q37 would be
equal to the voltage at pin 3. The signal is then taken. toPNP emitter
follower Q38 and NPN emitter follower Q39. Adjustment ~f R360 compensates for
FET mismatch and differences of transistor base-emitte~ voltages, to make the
voltage on the emitter Q39 equal to the FET input voltage. The gain of the
amplifier is near unity. The signal is then passed via R357 to link W7 and
re 1 ays K5 and K6.
.
For the B Channel ADC the relays .are not fi tted and the 1ink W7 is not cut.
For the A Channel AOC the relays are fitted and the link W7 is cut. This is
because the external trigger signal from the external trigger buffer amplifier
is applied to J3 of the A Channel ADConly, so that it is only on this channel
that the selection between internal and external trigger is required.
Processor control ensures that only one of the trigger sources is connected
via K5 or K6 to compensation network C160/R362. The signal is then passed by
K7 or C163 to the inputs of the comparators U26 and U27. For the LF reject
option, K7 is open and C163/R680 form a high pass filter. For DC coupling, K7
is closed. If HF reject is selected, K8 is closed, and C164 is placed across
the signal path, forming a low pass filter with series resistors R362 and
R357. The signal is then applied via R378 and R377 to the inputs of two fast
comparator circuits U26 and U27.
U26 is driven on its non inverting input, with positive feedback applied via
R331 and R375 to the inverting input. The DC voltage on the inverting input
is set by DAC U24, and op amp U25 (output pin 7) acting via R374. If input
pin 2 becomes more positive than input pin 3, output 8 will go negative,
feeding back a regenerative negative signal to pin 3, causing a rapid switching of the output state. To make the output change back, the input voltage on
pin 2 must move negative by the hysteresis range set by the output swing at
pin 8 divided by the feedback ratio of R381 to R375. This action prevents
oscillation of the comparator, generating a single output step as the trigger
signal crosses the trigger threshold set by DAC U24.
5-31
4500 Service Manual
The action of U27 is si~ilar~ except that the signal is applied to the inverting input, feedback"is·from the non·inv~rting output to non inverting input,
and the t ri gger level is set by U24 and ·U25 (output pi n 1).
The two outputs of U25 are. out of phase; that is: if +10 volts is on ·pin 7,
there will be -10 volts on pin 1. -The outputs of the two comparators, U26 and
U27, are ECl levels and are connected to ECl gates U28, U29, and U30. These
gates enable the selection of four trigger detection states: edye, enter band,
leave band, off. Edge trigger occurs when a trigger output is generated by
the crossin~ of the trigger level by the signal at the input of U26. This
happens for either positive or negative slope. The selection of positive or
negative slope triggering is determined by the set up of exclusive NOR U28.
Enter Band triggering occurs when the signal enters from the positive or negative direction. The symetrical levels around ground; set up at the inputs
U26, and U27; are set. by the two outputs of U25.
leave Band triggering occurs when the signal l~aves the band set up by the
outputs of U25 in either directidn. Selection of enter or leave band triggering is determined by the state of Exclusive NOR U28.
For positive Edge triggering the function of the gates is as follows: The
signal generated at output pin 7 of U26 is taken to one input (pin 14) of the
exclusive NOR U28. When pins 15 and 5 of U28 are low (this occurs when
positive edge or leave band triggering is selected), the Exclusive NOR gates
become inverters, so that the positive trigger edge from U26 is inverted at
output pin 12 of U28, and non-inverted at output pin 14 of U29. U28 pin 14
drives either Jl pin 78 or input pin 6 of U30, depending on the link
connections W6 and W2.
For leave band triggering, the positive edge from either U26 or U27 causes
output U29 pin 9 to go positive, output U28 pin 2 to go negative, and output
U29 pin 3 to go positive. U29 pin 3 is connected to either J1 pin 77, or pin
4 of U30, depending on the link connections WI and W5.
For negative edge or enter band triggering, U28 is set to its non-inverting
mode.
The A Channel ADC has links W5 and W6 closed and links WI and W4 open. The
trigger signals are taken from Jl pin 77 and Jl pin 78, via the motherboard,
to J1 pin 77 and Jl pin 78 on the B Channel. As links W3 and W4 are made on
the B Channel, the trigger edges generated on the A Channel are applied to
inputs 5 and 7 of U30 on the B Channel, giving complimentary outputs at Jl pin
61 and Jl pin 62. This balanced ECl signal is taken via the motherboard to
the Sweep and Record Board.
The B Channel has links WI and W4 closed; links W5 and W6 open. The trigger
signals at the outputs of U29 are therefore taken directly to input pins 4 and
60f U30, again giving a balanced output at Jl pins 61 and 62.
5-32
4500 Service Manual
The comparison levels used by U26 and U27 are. derived from an eight-bit DAC,
U24, whose data lines are dri ven by data latch U4g" (s~hemati c sheet 12).
Input pin 6 of op amp U25 is a current· summing p6int.·· With all digital inputs
. of the DAC, U24, low; the current flowing into pin 4 of ~24 is zero; and the 1
milliamp through RP32, pins 5 and 4 is balanced by 1 milliamp in RP32 pins 3
and 6. This causes a -10 volt output at pin 7 of U25. With all digital
inputs of the DAC high, the curreot into pin 4 of U24 is 1.992 milliamps,
making the op amp respond with an output voltage of approximately +10 volts to
maintain the current balance. Resistor R366 provides the 2 milliamp reference
for U24 from the +10 volt reference supply.
Input Offset and Offset AUTO CAL
(Refer to schematic sheet 13)
The offset voltage used by the input attenuator and buffer amplifier is
generated by a 12-bit DAC U62 and dual op amp U60. DAC U62 contains a single
R/2R ladder whose shunt elements are switched by data inputs, either to pin 1
or to pin 2. For correct operation, pins 1 and 2 must be virtual ground
points within 1 millivolt of pin 3~ Feedback around U60 from output pin 12
through R541 and RP2 (pins 4 and 5) to inverting input pin 1, and from output
pin 10 through U62 to inverting pin 7, makes inputs 1 and 7 virtual ground
points. R540 and R539 are used to balance out the input offset of U60 to less
than 1 millivolt. Current flowing out of U62 pin 2, is balanced by current
flowing toward output pin 12 of U60 through RP2 (pins 4 and 5).
With the applied reference of +10 volts on pin 17, the current on pin 2 of U62
is set to 1 milliamps for digital input of all zeros, and to 0 milliamps for a
digital input of all ones. This results in output pin 12 of U60 being set in
the range 0 to -10 volts by the digital input code to the DAC.
The current provided by the R/2R resistor elements internal to U62 is the
feedback current around U60 (pins 6, 7, and 10). This current is equal to the
current from output pin 12 of U60 flowing through RP2 (pins 6 and 3), and
results in output U60 pin 10 being set in the range -10 to +10 volts by the
digital code into U62.
The +/-2 volt offset source for the input attenuator and buffer amplifier is
derived from U60 pin 10 by the potential divider consisting of R542, R538, and
R544. This is taken via CMOS analog switch U61 to J4, which connects to the
ribbon cable going to the Attenuator. During the Auto Cal routine an absolute
ground reference is provided for the input attenuator circuitry by opening
switch U61 pins 8 and 9, and closing U61 pins 4 and 5. The unattenuated
signal at U60 pin 10 is taken directly to the attenuator via J4, were it is
used by the calibration system. It is also taken to a unity gain buffer on
the keyboard, and the buffer output dri ves the CAL test point on the front
panel.
5-33
4500
Servi~e Ma~ual
The digii~l inp~ts for DAC U62 are latched from the data bus by U51 and U~2.
The +/-2·voltoffset se~tt~ the attenuator can be altered slightly under the
cant ro lof ,the ·m ic.rofirOcessor, for Auto Calibration. If an offset error is
detected 'by the .sy.stem ,an e"] ght-bi t DAC", U48 provides correction. The
current into:R534i·s the s~m of th~ DAC output current (U48 pin 4) and U.5
milliamp~ th~oughR533,yield~ng a digitally controlled voltage swing at pin 4
of +/-10 millivolts •. This is one end of the offset potential divider, so that
the offset "can be changed by about this +/- 10 millivolts. Data for U48 is
latched fro~.thedata,bus by U50 •
Correction for gain errors found by the calibrati~n system are done through
eight-bit DAC U57.This generates two complimentary output voltages at pins 4
and 2. With all logic ones applied, output 4 will be -10 volts, and output 2
will be +10 volts. W4th all logic zeros applied, output 4 will be +10 volts,
and output 2 will be -10 volts. These Voltages, acting through dual unity
gain buffer op amp U23 (schematic sheet 9), modify slightly the +/-2 volt
reference for the folding amplifiers by injecting currents into the summing
nodes of the reference generators through R321 and R330. The low reference
for the second rank is also effected via R3D2. Input data for DAC U57 is
latched by U56 from the data bus~
The inputs for the trigger level DAC U24 (schematic sheet 12) are provided by
latch U49 from the data bus. Analog switch U61 is controlled by two outputs
from data latch U52.
Data latches U51, U53, and U54 directly drive the reed relays used in the
input attenuator via connector J4. These latches also drive the relays used
for 1/2/5 attenuation on the ADC board (schematic sheet 1).
The signals that control band or edge triggering, and leave or enter band
triggering, come from latch U54 (schematic sheet 13). TTL to ECl level
converter U46 converts these signals to ECl levels. Band triggering is activated by the signal BAND*, edge triggering is activated by the signal EDGE*,
and leave or enter band triggering is selected by the signal L*/E.
Data is presented to the data flip-flops U49 through U54, and U56, in the
following manner: Processor lines A4 through A7, I/O, and WR*; acting on the
binary inputs and enables of l-of-8 decoder U59 (schematic sheet 13); causes
output pin 11 (channel B) or output pin 12 (channel A) to go low if one of the
ADCs is addressed. This enables the outputs of U55, a three state octal
buffer, and bus data is placed on the inputs of the flip-flops. Address lines
AD through A3, and an output from U59, act on the inputs of one of eight
decoder U58~ so that one of its outputs (U58 pins 9 through 15) goes low: This
takes the clock input of one of the flip-flops low. When WR* goes high, the
flip-flop clock goes high, and clocks in the data.
5-34
4~00
Service Manual
Power Supply
(Refer to schematic sheets 1 and 9}
The +18 volt supply (schematic' sheet 1) i; taken ~hrough filter L12, ·C277, and
C276, to the input of adj ustab 1e regul ator" U64 •. ·TheB'
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