03 0029 01 Z80 CPU Technical Manual 1977
03-0029-01_Z80_CPU_Technical_Manual_1977 03-0029-01_Z80_CPU_Technical_Manual_1977
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Zilog
Z80®
-CPU
Z80A-CPU
rechnical Manual
Price: $7.50
03-0029-01
Copyright© 1977 by Zilog, Inc. All rights reserved. No part of this
publication may be reproduced, stored in a retrieval system, or transmitted,
in any form or by any means, electronic, mechanical, photocopying,
recording, or otherwise, without the prior written permission of Zilog.
Zilog assumes no responsibility for the use of any circuitry other than
circuitry embodied in a Zilog product. No other circuit patent licenses
are implied.
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a
TABLE OF CONTENTS
Chapter
Page
1.0
Introduction
2.0
Z80-CPU Architecture . . . . . . . . . . . . . . . . . '. . . . . . . . . 3
3.0
Z80-CPU Pin Description . . . . . . . . . . . . . . . . . . . . . . . . .
4.0
CPU Timing
5.0
Z80-CPU Instruction Set
6.0
F l a g s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.0
Summary of OP Codes and Execution Times. . . . . . . . . . . . . . . . . . 43
8.0
Interrupt Response. . . . . . .
9.0
Hardware Implementation Examples . . . . . . . . . . . . . . . . . . . . . 59
7
. . . . 11
. . . . . . . . . . . . . . . . . . .
. . . . 19
'. . . . . . . . . . . . . . . . . . . 55
10.0
Software Implementation Examples
. . . . . . . . . . . . . . . . . . . . . 63
11.0
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 69
12.0
Z80-CPU Instruction Set Summary. . . . . . . . . . . . . . . . . . " . . . 73
1.0
INTRODUCTION
The term "microcomputer" has been used to describe virtually every type of small computing device
designed within the last few years. This term has been applied to everything from simple "microprogrammed" controllers constructed out of TTL MSI up to low end minicomputers with a portion of the CPU
constructed out of TTL LSI "bit slices." However, the major impact of the LSI technology within the last
few years has been with MOS LSI. With this technology, it is possible to fabricate complete and very powerful computer systems with only a few MOS LSI components.
The Zilog Z-80 family of components is a significant advancement in the state-of-the art of microcomputers. These components can be configured with any type of standard semiconductor memory to
generate computer systems with an extremely wide range of capabilities. For example, as few as two LSI
circuits and three standard TTL MSI packages can be combined to form a simple controller. With additional
memory and I/O devices a computer can be constructed with capabilities that only a minicomputer could
previously deliver. This wide range of computational power allows standard modules to be constructed by a
user that can satisfy the requirements of an extremely wide range of applications.
The major reason for MOS LSI domination of the microcomputer market is the low cost of
these few LSI components. For example, MOS LSI microcomputers have already replaced TTL logic in
such applications as terminal controllers, peripheral device controllers, traffic signal controllers, point of
sale terminals, intelligent terminals and test systems. In fact the MOS LSI microcomputer is finding its way
into almost every product that now uses electronics and it is even replacing many mechanical systems such
as weight scales and automobile controls.
The MOS LSI microcomputer market is already well established and new products using them are
being developed at an extraordinary rate. The Zilog Z-80 component set has been designed to fit into
this market through the following factors:
1. The Z-80 is fully software compatible with the popular 8080A CPU offered from several sources.
Existing designs can be easily converted to include the Z-80 as a superior alternative.
2. The Z-80 component set is superior in both software and hardware capabilities to any other microcomputer system on the market. These capabilities provide the user with significantly lower hardware
and software development costs while also allowing him to offer additional features in his system.
3. For increased throughput the Z80A operating at a 4 MHZ clock rate offers the user significant speed
advantages over competitive products.
4. A complete product line including full software support with strong emphasis on high level languages
and a disk-based development system with advanced real-time debug capabilities is offered to enable
the user to easily develop new products.
Microcomputer systems are extremely simple to construct using Z-80 components. Any such system
consIsts of three parts:
L CPU (Central Processing Unit)
2. Memory
3. Interface Circuits to peripheral devices
The CPU is the heart of the system. Its function is to obtain instructions from the memory and perform
the desired operations. The memory is used to contain instructions and in most cases data that is to be
processed. For example, a typical instruction sequence may be to read data from a specific peripheral
device, store it in a location in memory; check the parity and write it out to another peripheral device. Note
that the Zilog component set includes the CPU and various general purpose 1/0 device controllers, while a
wide range of memory deVices may be used from any s.ource. Thus, all required components can be
connected together in a very simple manner with virtually no other external logic. The user's effort then
becomes primarily one of software development. That is, the user can concentrate on describing his problem and translating it into a series of instructions that can be loaded into the microcomputer memory. Zilog
is dedicated to making this step of software generation as simple as possible. A good example of this is oUr
assembly language in which a simple mnemonic is used to represent every instruction that the CPU can
perform. This language is self documenting in such a way that from the mnemonic the user can understand
exactly what the instruction is doing without constantly checking back to a complex cross listing.
2
2.0 Z-80 CPU ARCHITECTURE
A block diagram of the internal architecture of the Z-80 CPU is shown in figure 2.0-1. The diagram
shows all of the major elements in the CPU and it should be referred to throughout the following
description.
INST.
REG
13
CPU AND
SYSTEM
CONTROL
SIGNALS
ALU
INSTRUCTION
DECODE
&
CPU
CONTROL
CPU
CONTROL
iii
+5V GND
2-80 CPU BLOCK DIAGRAM
FIGURE 2.0-1
2.1
CPU REGISTERS
The Z-80 CPU contains 208 bits of R/W memory that are accessible to the programmer. Figure 2.0-2
illustrates how this memory is configured into eighteen 8-bit registers and four 16-bit registers. All Z-80
registers are implemented using static RAM. The registers include two sets of six general purpose registers
that may be used individually as 8-bit registers or in pairs as 16-bit registers. There are also two sets of
accumulator and flag registers.
Special Purpose Registers
1. Program Counter (PC). The program counter holds the 16-bit address of the current instruction being
fetched from memory. The PC is automatically incremented after its contents have been transferred
to the address lines. When a program jump occurs the new value is automatically placed in the PC,
overriding the incrementer.
2. Stack Pointer (SP). The stack pointer holds the 16-bit address of the current top of a stack located
anywhere in external system RAM memory. The external stack memory is organized as a last-in firstout (LIFO) file. Data can be pushed onto the stack from specific CPU registers or popped off of the
stack into specific CPU registers through the execution of PUSH and POP instructions. The data
popped from the stack is always the last data pushed onto it. The stack allows simple implementation
of multiple level interrupts, unlimited subroutine nesting and simplification of many types of data
manipulation.
3
~EG
MAIN
SET
ALTERNATE REG SET
,/
A
"ACCUMULATOR
A
A
FLAGS
F
ACCUMULATOR
A'
FLAGS
F·'
B
C
B'
C'
0
E
0'
E'
H
L
H'
L'
INTERRUPT
VECTOR
I
I
MEMORY
REFRESH
R
"
)
GENERAL
PURPOSE
REGISTERS
I'
INDEX REGISTER IX
SPECIAL
>PURPOSE
REGISTERS
INDEX REGISTER IY
STACK POINTER SP
PROGRAM COUNTER PC
"
Z-80 CPU REGISTER CONFIGURATION
FIGURE 2.0-2
3. Two Index Registers (IX & IY). The two independent index registers hold a 16-bit base address that
is used in indexed addressing modes. In this mode, an index register is used as a base to point to a
region in memory from which data is to be stored or retrieved. An additional byte is included in
indexed instructions to specify a displacement from this base. This displacement is specified as a two's
complement signed integer. This mode of addressing greatly simplifies many types of programs,
especially where tables of data are used.
4. Interrupt Page Address Register (I). The Z-80 CPU can be operated in a mode where an indirect call
to any memory location can be achieved in response to an interrupt. The I Register is used for this
purpose to store the high order 8-bits of the indirect address while the interrupting device provides the
lower 8-bits of the address. This feature allows interrupt routines to be dynamically located anywhere
in memory with absolute minimal access time to the routine.
5. Memory Refresh Register (R). The Z-80 CPU contains a memory refresh counter to enable dynamic
memories to be used with the same ease as static memories. Seven bits of this 8 bit register are automatically incremented after each instruction fetch. The eighth bit will remain as programmed as the
result of an LD R, A instruction. The data in the refresh counter is sent out on the lower portion of
the address bus along with a refresh control signal while the CPU is decoding and executing the fetched
instruction. This mode of refresh is totally transparent to the programmer and does not slow down the
CPU operation. The programmer can load the R register for testing purpOSes, but this register is normally
not used by the programmer. J)uring refresh, the contents of the I register are placed on the upper 8 bits of
the address bus.
.
Accumulator and Flag Registers
The CPU includes two independent 8-bit accumulators and associated 8-bit flag registers. The accumulator !tolds the results of 8-bit arithmetic or logical operations while the flag register indicates specific
conditions for 8 or 16-bit operations, such as indicating whether or not the result of an operation is equal
to zerO. The programmer selects the accumulator and flag pair that he wishes to work with with a single
exchange instruction so that he may easily work with either pair.
4
General Purpose Registers
There are two matched sets of general purpose registers, each set containing six 8-bit registers that
may be used individually as 8-bit registers or as 16-bit register pairs by the programmer. One set is called
BC, DE and HL while the complementary set is called BC', DE' and HL'. At anyone time the programmer
can select either set of registers to work with through a single exchange command for the entire set. In
systems where fast interrupt response is required, one set of general purpose registers and an accumulator/
flag register may be reserved for handling this very fast routine. Only a simple exchange commands need be
executed to go between the routines. This greatly reduces interrupt service time by eliminating the requirement for saving and retrieving register contents in the external stack during interrupt or subroutine processing. These general purpose registers are used for a wide range of applications by the programmer. They also
simplify programming, especially in ROM based systems where little external read/write memory is
available.
2.2 ARITHMETIC & LOGIC UNIT (ALU)
The 8-bit arithmetic and logical instructions of the CPU are executed in the ALU. Internally the ALU
communicates with the registers and the external data bus on the internal data bus. The type of functions
performed by the ALU include:
Add
Left or right shifts or rotates (arithmetic and logical)
Subtract
Increment
Logical AND
Decrement
Logical OR
Set bit
Logical Exclusive OR
Reset bit
Compare
Test bit
2.3 INSTRUCTION REGISTER AND CPU CONTROL
As each instruction is fetched from memory, it is placed in the instruction register and decoded. The
control sections performs this function and then generates and supplies all of the control signals necessary
to read or write data from or to the registers, control the ALU and provide all required external control
signals.
5
-BLANK-
-6-
3.0
Z-BO CPU PIN DESCRIPTION
The Z-80 CPU is packaged in an industry standard 40 pin Dual In-Line Package. The I/O pins are shown
in figure 3.0-1 and the function 0 f each is described below.
27
30
31
32
33
34
35
36
37
M,
MREQ
SYSTEM
CONTROL
10RQ
RD
WR
19
20
21
22
28
38
39
40
1
18
24
CPU
CONTROL
ADDRESS
BUS
2
INT
NMI
RESET
CPU
{BUSRQ
BUS
CONTROL
BUSAK
'I'
+5V
GND
16
Z-80 CPU
17
3
4
5
26
25
23
14
15
12
6
11
29
8
7
9
DATA
BUS
10
13
Z-BO PIN CONFIGURATION
FIGURE 3.0-1
AO-A15
(Address Bus)
Tri-state output, active high. AO-A15 constitute a 16-bit address bus. The
address bus provides the address for memory (up to 64K bytes) data
exchanges and for I/O device data exchanges. I/O addressing uses the 8 lower
address bits to allow the user to directly select up to 256 input or 256 output
ports. AO is the least significant address bit. During refresh time, the lower
7 bits contain a valid refresh address.
Tri-state input/output, active high. DO-D7 constitute an 8-bit bidirectiQnai
data bus. The data bus is used for data exchanges with memory and I/O
devices.
Ml
(Machine Cycle one)
Output, active low. M 1 indicates that the current machine cycle is the OP
code fetch cycle of an instruction execution. Note that during execution
of 2-byte op-codes, Ml is generated as each op code byte is fetched. These
two byte op-codes always begin with CBH, DDH, EDH or FDH. Ml also
occurs with 10RQ to indicate an interrupt acknowledge cycle.
MREQ
(Memory Request)
Tri-state output, active low. The memory request signal indicates that the
address bus holds a valid address for a memory read or memory write
operation.
7
10RQ
(Input/Output Request)
Tri-state output, active low. The 10RQ signal indicates that the lower half of
the address bus holds a valid I/O address for a I/O read or write op.eration. An
IORQ signal is also generated with an Ml signal when an interrupt is being
acknowledged to indicate that an interrupt response vector can be placed on
the data bus. Interrupt Acknowledge operations occur during Ml time while
I/O operations never occur during Ml time.
RD
(Memory Read)
Tri-state output, active low. RD indicates that the CPU wants to read data
from memory or an I/O device. The addressed I/O device or memory should
use this signal to gate data onto the CPU data bus.
WR
(Memory Write)
Tri-state output, active low. WR indicates that the CPU data bus holds valid
data to be stored in the addressed memory or I/O device.
RFSH
(Refresh)
Output, active low. RFSH indicates that the lower 7 bits of the address
bus contain a refresh address for dynamic memories and the current MREQ
signal should be used to do a refresh read to all dynamic memories.
HALT
(Halt state)
Output, active low. HALT indicates that the CPU has executed a HALT software instruction and is awaiting either a non maskable or a maskable interrupt (with the mask enabled) before operation can resume. While halted, the
CPU executes NOP's to maintain memory refresh activity.
WAIT
(Wait)
Input, active low. WAIT indicates to the Z-80 CPU that the addressed
memory or I/O devices are not ready for a data transfer. The CPU continues
to enter wait states for as long as this signal is active. This signal allows
memory or I/O devices of any speed to be synchronized to the CPU.
INT
(Interrupt Request)
Input, active low. The Interrupt Request signal is generated by I/O devices. A
request will be honored at the end of the current instruction if the: internal
software controlled interrupt enable flip-flop (IFF) is enabled and" if the
BUSRQ signal is not active. When the CPU accepts the interrupt, an acknowledge signal (IORQ during M 1 time) is sent out at the beginning of the next
instruction cycle. The CPU can respond to an interrupt in three different
modes that are described in detail in section 5.4 (CPU Control Instructions).
NMI
(Non Maskable
Interrupt)
Input, negative edge triggered. The non maskable interrupt request line has a
higher priority than INT and is always recognized at the end of the current
instruction, independent of the status of the interrupt enable flip-flop. NMI
automatically forces the Z-80 CPU to restart to location 0066H. The program
counter is automatically saved in the external stack so that the user can return
to the program that was interrupted. Note that continuous WAIT cycles can
prevent the current instruction from ending, and that a BUSRQ will override
aNMI.
8
RESET
Input, active low. RESET forces the program counter to zero and initializes
the CPU. The CPU initialization includes:
1) Disable the interrupt enable flip-flop
2) Set Register I = OOH
3) Set Register R = OOH
4) Set Interrupt Mode 0
During reset time, the address bus and data bus go to a high impedance state
and all control output signals go to the inactive state.
BUSRQ
(Bus Request)
Input, active low. The bus request signal is used to request the CPU address
bus, data bus and tri-state output control signals to go to a high impedance
state so that other devices can control these buses. When BUSRQ is activated,
the CPU will set these buses to a high impedance state as soon as the current
CPU machine cycle is terminated.
BUSAK
(Bus Acknowledge)
Output, active low. Bus acknowledge is used to indicate to the requesting
device that the CPU address bus, data bus and tri-state control bus signals
have been set to their high impedance state and the external device can now
control these signals.
Single phase TTL level clock which requires only a 330 ohm pull-up resistor
to +5 volts to meet all clock requirements..
9
-BLANK-
-10-
4.0 CPU TIMING
The Z-80 CPU executes instructio.ns by stepping through a very precise set o.f a few basic o.peratio.ns.
These include:
Memo.ry read o.r write
I/O device read o.r write
Interrupt ackno.wledge
All instructio.ns are merely a series o.f these basic o.peratio.ns. Each o.f these basic o.peratio.ns can take fro.m
three to. six clo.ck perio.ds to. co.mplete o.r they can be lengthened to. synchro.nize the CPU to. the speed o.f
external devices. The basic clo.ck perio.ds are referred to. as T cycles and the basic o.peratio.ns are referred to.
as M (fo.r machine) cycles. Figure 4.0-0 illustrates ho.w a typical instructio.n will be merely a series o.f
specific M and T cycles. No.tice that this instructio.n co.nsists o.f three machine cycles (M I, M2 and M3). The
first machine cycle o.f any instructio.n is a fetch cycle which is fo.ur, five o.r six T cycles lo.ng (unless lengthened by the wait signal which will be fully described in the next sectio.n). The fetch cycle (Ml) is used to.
fetch the OP co.de o.f the next instructio.n to. be executed. Subsequent machine cycles mo.ve data between
the CPU and memo.ry o.r I/O devices and they may have anywhere fro.m three to. five T cycles (again they
may be lengthened by wait states to. synchronize the external devices to. the CPU). The fo.llo.wing paragraphs describe the timing which o.ccurs within any o.f the basic machine cycles. In sectio.n 7, the exact
timing fo.r each instructio.n is specified.
TCycle
Machine Cycle
M1
M2
(o.P Code Fetch)
M3
(Memory Read)
(Memory Write)
Instruction Cycle
BASIC CPU TIMING EXAMPLE
FIGURE 4.0-0
All CPU timing can be broken do.wn into. a few very simple timing diagrams as sho.wn in figure 4.0-1
through 4.0-7. These diagrams sho.w the fo.llo.wing basic o.peratio.ns with and witho.ut wait states (wait states
are added to. synchronize the CPU to. slo.w memory o.r I/O devices).
4.0-1.
Instructio.n OP co.de fetch (Ml cycle)
4.0-2.
Memo.ry data read o.r write cycles
4.0-3.
I/O read o.r write cycles
4.0-4.
Bus Request/ Ackno.wledge Cycle
4.0-5.
Interrupt Request/Ackno.wledge Cycle
4.0-6_
No.n maskable Interrupt Request/ Ackno.wledge Cycle
4.0-7.
Exit from a HALT instructio.n
11
INSTRUCTION FETCH
Figure 4.0-1 shows the timing during an Ml cycle (OP code fetch). Notice that the PC is placed on the
address bus at the beginning of the Ml cycle. One half clock time later the MREQ signal goes active. At this
time the address to the memory has had time to stabilize so that the falling edge of MREQ can be used
directly as a chip enable clock to dynamic memories. The RD line also goes active to indicate that the
memory read data should be enabled onto the CPU data bus. The CPU samples the data from the memory on.
the data bus with the rising edge of the clock of state T3 and this same edge is used by the CPU to turn off
the RD and MRQ signals. Thus the data has already been sampled by the CPU before the RD signal becomes
inactive. Clock state T3 and T4 of a fetch cycle are used to refresh dynamic memories. (The CPU uses this .
time to decode and execute the fetched instruction so that no other operation could be performed at this
time). During T3 and T4 the lower 7 bits of the address bus contain a memory refresh address and the RFSH
signal becomes active to indicate that a refresh read of all dynamic memories should be accomplished. Notice
that a RD signal is not generated during refresh time to prevent data from different memory segments from
being gated onto the data bus. The MREQ signal during refresh time should be used to perform a refresh read
of all memory elements. The refresh signal can not be used by itself since the refresh address is only guaranteed to be stable during MREQ time.
M1 Cycle
T1
T2
T3
T4
T1
....r--t- r-----t- ~ ~ r-----,
AO - A15
I
I
p(.
REFRESH AOOR.
r
\
\
I
- f-o----- ~:r---L_ ------ ----f-o---------- ------
-h
OBO- OBl
T
I
1
------1-------
l ______
'li\jl-\
-
L.:.:.:.iJ
\
II
INSTRUCTION OP CODE FETCH
FIGURE 4.0-1
Figure 4.0-1 A illustrates how the fetch cycle is delayed if the memory activates. the WAIT line. During 1'2 and every subsequent Tw, the CPU samples the WAIT line with the falling edge of «1>. If the WAIT
line is active at this time, another wait state will be entered during the following cycle. Using this technique
the read cycle can be lengthened to match the access time of any type of memory device.
12
MI Cycle
Tl
II·
......
n-n-
AO - A15
rw
T2
I
Tw
T3
~~
n-n-rI
PC
T4
1
REFRESH AOOR.
J
\
\
I
'INn
L.:..:..:.fI
OBO- OB7
-h
I
----- ----- - f------lJ- -1-J.- ~JL-_ -----f------ f-------- -- -\
INSTRUCTION OP CODE FETCH WITH WAIT STATES
FIGURE 4.0-1A
MEMORY READ OR WRITE
Figure 4:0-2 illustrates the timing of memory read or write cycles other than an OP code fetch (M I
cycle). These cycles are generally three clock periods long unless wait states are requested by the memory
via the WAIT signal. The MREQ signal and the RD signal are used the same as in the fetch cycle. In the case
of a memory write cycle, the MREQ also becomes active when the address bus is stable so that it can be
used directly as a chip enable for dynamic memories. The WR line is active when data on the data bus is
stable so that it can be used directly as a RjW pulse to virtually any type of semiconductor memory.
Furthermore the WR signal goes inactive one half T state before the address and data bus contents are
changed so that the overlap requirements for virtually any type of semiconductor memory type will be met.
Memory Write Cycle
Memory Read Cycle
T2
Tl
IIAO-A15
Tl
T3
T2
- r--L- ~I"L-I"L- r----t- ~
I
I
MEMORY AODR.
\
I
\
I
(00- 071
WAIT
r---
I
MEMORY ADDR.
I
\
\
DATA BUS
T3
J
DATA OUT
IN
r - - - - - -- ... ---- TL-:: ---- ----- -,-TL-- f----- ,...-------- ---MEMORY READ OR WRITE CYCLES
FIGURE 4.0-2
13
Figure 4.0-2A illustrates how a WAIT request signal will lengthen any memory read or write operation_ This operation is identical to that previously described for a fetch cycle. Notice in this figure that a
separate read and a separate write cycle are shown in the same figure although read and write cycles can
never occur simultaneously.
T2
T1
II
AD-A7
PORT ADDRESS
I
,
1
I
\
DATA BUS
}
Read
Cycle
}
Write
Cycle
IN
- 1 - - - - -1 - - - - - ----- ----
:J'C:_ ----- --1-----
1----
1
I
DATA BUS
OUT
INPUT OR OUTPUT CYCLES
FIGURE 4.0-3
T1
<\>
-
T2
Tw
T3
r----L- ~ ~r---L- ~ rtI
AD - A7
Tw *
II
PORT ADDRESS
I
\
IN
DATA BUS
}
---
I
\
- - - - r - - - - - -l...I~:::I-Tl-- ----- t - - - -
-
---- r-----
-- 1 - - - - -1 - - - - -
OUT
DATA BUS
}
I
\
INPUT OR OUTPUT CYCLES WITH WAIT STATES
FIGURE 4.0-3A
*
READ
CYCLE
Automatically inserted WAIT state
15
WRITE
CYCLE
Bus Available States
Any M Cycle
T)(
Last T State
'I-
-
~
Tx
Tx
Tl
r-------L-- ~ ~ r-------L--r--L- r---tJ/
\
SUSRQ
Sample
Sample_
1
\
AO-A15
--- ----- - - - - -i
00-07
- - - ----- ----- ;
---- ;
--- ----Floating
MREo. RO,
WR,lORo.
RFSH
BUS REQUEST/ACKNOWLEDGE CYCLE
FIGURE 4.0·4
INTERRUPT REQUEST/ACKNOWLEDGE CYCLE
Figure 4.0·5 illustrates the timing associated with an interrupt cycle. The interrupt signal (INT) is
sampled by the CPU with the rising edge of the last clock at the end of any instruction. The signal will not be
accepted if the internal CPU software controlled interrupt enable flip.flop is not set or if the BUSRQ signal
is active. When the signal is accepted a special MI cycle is generated. During this special Ml cycle the 10RQ
signal becomes active (instead of the normal MREQ) to indicate that the interrupting device can place an
8-bit vector on the data bus. Notice that two wait states are automatically added to this cycle. These states
are added so that a ripple priority interrupt scheme can be easily implemented. The two wait states allow
sufficient time for the ripple signals to stabilize and identify which I/O device must insert the response
vector. Refer to section 8.0 for details on how the interrupt response vector is utilized by the CPU.
MI----------Last M Cycle
---of Instruction--*------------Last T State
Tw *
T1
Tw *
o
AO- A15
oATABUS --+-------~r_------~--~----~------~r_------_+----~
RO
INTERRUPT REQUEST/ACKNOWLEDGE CYCLE
FIGURE 4.()..5
16
Figures 4.0-SA and 4.0-SB illustrate how a programmable counter can be used to extend interrupt
acknowledge time. (Configured as shown to add one wait state)
~----------~----~B432
O_I_O_RQ_'____
(TO
PERIPHERAL)
~O.....W_A_I_T___
.---+-~LJ
(TO CPU)
74S04
M1
--[::>0---0
ON/UP
LOAD
G
QD~--08
o
_
7432
o-~JI
M1 ---0
+5V
---'V""'.--~
EXTENDING INTERRUPT ACKNOWLEDGE TIME WITH WAIT STATE
FIGURE 4.0-5A
0:1
AUTOMATIC WAIT ~\'-------'\
LAST T STATE
LAST IVI CYCLE OF
INSTRUCTION
AO-A15
DATA BUS
TW*
USER WAIT
Tw*
----------------~----------------------------~--------r_----~------
--------------~----------------------+_------~~------r_<
wm== ___ ==
-
NORMAL ACKNOWLEDGE
TIME
-
I__--ACKNOWLEDGE TIME WITH ONE
..
ADDITIONAL WAIT STATE
- - - - O..~l
REQUEST/ACKNOWLEDGE CYCLE WITH ONE ADDITIONAL WAIT STATE
FIGURE 4.0-58
17
NON MASKABLE INTERRUPT RESPONSE
Figure 4.0-6 illustrates the request/acknowledge cycle for the non maskable interrupt. This signal is
sampled at the same time as the interrupt line, but this line has priority over the normal interrupt and it can
not be disabled under software control. Its usual function is to provide immediate response to important
signals such as an impending power failure. The CPU response to a non maskable interrupt is similar to a
normal memory read operation. The only difference being that the content of the data bus is ignored while
the processor automa tically stores the PC in the external stack and jumps to location 0066 H. The service
routine for the non maskable interrupt must begin at this location if this interrupt is used.
HALT EXIT
Whenever a software halt instruction is executed the CPU begins executing Nap's until an interrupt is
received (either a non maskable or a maskable interrupt while the interrupt flip flop is enabled). The two
interrupt lines are sampled with the rising clock edge during each T4 state as shown in figure 4.0-7. If a non
maskable interrupt has been received or a maskable interrupt has'been received and the interrupt enable
flip-flop is set, then the halt state will be exited on the next rising clock edge. The following cycle will then
be an interrupt acknowledge cycle corresponding to the type of interrupt that was received. If both are
received at this time, then the non maskable one will be acknowledged since it has highest priority. The
purpose of executing Nap instructions while in the halt state is to keep the memory refresh signals active.
Each cycle in the halt state is a normal Ml (fetch,) cycle except that the data received from the memory is
ignored and a Nap instruction is forced internally to the CPU. The halt acknowledge signal is active during
this time to indicate that the processor is in the halt state.
MI
Last M Cycle
Last T Time
-(HL)
Inc HL & DE, Dec BC
ED
BO
'LDlR: - Load (DE)_(HL)
Inc HL & DE, Dec Be, Repeat until Be
ED
A8
'LOD' - Load (DEI_IHLI
Dec HL & DE, Dec Be
ED
B8
'LDOR' - Load (OE)-IHL)
Dec HL & DE, Dec Be, Repeat until Be =0
=0
(DE)
Reg HL
Reg DE
Reg Be
.points to source
points to destination
is byte counter
BLOCK TRANSFER GROUP
TABLE 5.3-4
Table 5.3-5 specifies the OP codes for the four block search instructions. The first, CPI (compare and
increment) compares the data in the accumulator, with the contents of the memory location pointed to by
register HL. The result of the compare is stored in one of the flag bits (see section 6.0 for a detailed explanation of the flag operations) and the HL register pair is then incremented and the byte counter (register
pair BC) is decremented. !
The instruction CPIR is merely an extension of the CPI instruction in which the compare is repeated
until either a match is found or the byte counter (register pair BC) becomes zero. Thus, this single instruction can search the entire memory for any 8-bit character.
The CPD (Compare and Decrement) and CPDR (Compare, Decrement and Repeat) are similar
instructions, their only difference being that they decrement HLafter every compare so that they search
the memory in the opposite direction. (The search is started at the highest location in the memory block).
It should be emphasized again that these block transfer and compare instructions are extremely
powerful in string manipulation applications.
ARITHMETIC AND LOGICAL
Table 5.3-6 lists all of the 8·bit arithmetic operations that can be performed with the accumulator,
also listed are the increment (INC) and decrement (DEC) instructions. In all of these instructions, except
INC and DEC, the specified 8-bit operation is performed between the data in the accumulator and the
source data specified in the table. The result of the operation is placed in the accumulator with the exception of compare (CP) that leaves the accumulator unaffected. All of these operations affect the flag
register as a result of the specified operation. (Section 6.0 provides all of the details on how the flags are
affected by any instruction type). INC and DEC instructions specify a register or a memory location as
both source and destination of the result. When the source operand is addressed using the index registers
the displacement must follow directly. With immediate addressing the actual operand will follow directly.
For example the instruction:
AND07H
would appear aa:
~
A+1~
Address A
28
OP Code
Operand
SEARCH
LOCATION
r--REG.
INOIR.
-
(HL)
ED
A1
'CPI'
Inc HL, Dec BC
ED
B1
'CPIR', Inc HL, Dec BC
repeat until BC = 0 or find match
ED
A9
'CPO' Dec H L & BC
ED
B9
'CPDR' Dec HL & BC
Repeat until BC = 0 or find match
HL points to location in memory
to be compared with accumulator
contents
BC is byte counter
BLOCK SEARCH GROUP
TABLE 5.3-5
Assuming that the accumulator contained the value F3H the result of03H would be placed in the
accumulator:
Acc before operation 1111 0011 = F3H
00000111 = 07H
Operand
0000 0011 = 03H
Result to Acc
The Add instruction (ADD) performs a binary add between the data in the source location and the
data in the accumulator. The subtract (SUB) does a binary subtraction. When the add with carry is specified
(AD C) or the subtract with carry (SBC), then the carry flag is also added or subtracted respectively. The
flags and decimal adjust instruction (DAA) in the Z-80 (fully described in section 6.0) allow arithmetic
operations for:
multiprecision packed BCD numbers
multiprecision signed or unsigned binary numbers
multiprecision two's complement signed numbers
Other instructions in this group are logical and (AND), logical or (OR), exclusive or (XOR) and compare (CP).
There are five general purpose arithmetic instructions that operate on the accumulator or carry flag.
These five are listed in table 5.3-7. The decimal adjust instruction can adjust for subtraction as well as addition, thus making BCD arithmetic operations simple. Note that to allow for this operation the flag N is used.
This flag is set if the last arithmetic operation was a subtract. The negate accumulator (NEG) instruction
forms the two's complement of the number in the accumulator. Finally notice that a reset carry instruction
is not included in the Z-80 since this operation can be easily achieved through other instructions such as a
logical AND of the accumulator with itself.
Table 5.3-8 lists all of the 16-bit arithmetic operations between 16-bit registers. There are five groups
of instructions including add with carry and subtract with carry. ADC and SBC affect all of the flags. These
two groups simplify address calculation operations or other 16-bit arithmetic operations.
29
SOURCE
REG.
INDIR.
(HL}
INDEXED
(lX+d}
'ADD'
ADDwCARRY
'ADC'
SUBTRACT
'SUB'
SUBw CARRY
'SBC'
'AND'
'XOR'
'OR'
COMPARE
'CP'
INCREMENT
'INC'
FD
35
DECREMENT
'DEC'
d
8 BIT ARITHMETIC AND LOGIC
TABLE 5.3-6
Decimal Adjust Acc, 'DAA'
Complement Acc, 'CPL'
Negate Acc, 'NEG'
(2'5 complement}
Complement Carry Flag, 'CCF'
Set Carry Flag, 'SCF'
GENERAL PURPOSE AF OPERATIONS
TABLE 5.3-7
30
SOURCE
IX
IX
DD
09
DD
19
DD
39
IV
FD
09
FD
19
FD
39
ADD WITH CARRV AND
SET FLAGS
'A DC'
HL
ED
4A
ED
5A
ED
6A
ED
7A
SUB WITH CARRV AND
'SBC'
SET FLAGS
HL
ED
42
ED
52
ED
62
ED
72
'ADD'
DESTINATION
IV
DO
29
FD
29
INCREMENT
'INC'
DD
23
FD
23
DECREMENT
'DEC'
DO
2B
FD
2B
16 BIT ARITHMETIC
TABLE 5.3-8
ROTATE AND SHIFT
A major capability of the Z-80 is its ability to rotate or shift data in the accumulator, any general purpose register, or any memory location. All of the rotate and shift OP codes are shown in table 5.3-9. Also
included in the Z-80 are arithmetic and logical shift operations. These operations are useful in an extremely
wide range of applications including integer multiplication and division. Two BCD digit rotate instructions
(RRD and RLD) allow a digit in the accumulator to be rotated with the two digits in a memory location
pointed to by register pair HL. (See figure 5.3-9). These instructions allow for efficient BCD arithmetic.
BIT MANIPULATION
The ability to set, reset and test individual bits in a register or memory location is needed in almost
every program. These bits may be flags in a general purpose software routine, indications of external control conditions or data packed into memory locations to make memory utilization more efficient.
The Z-80 has the ability to set, reset or test any bit in the accumulator, any general purpose register
or any memory location with a single instruction. Table 5.3-10 lists the 240 instructions that are available
for this purpose. Register addressing can specify the· accumulator or any general purpose register on which
the operation is to be performed. Register indirect and indexed addressing are available to operate on
external memory locations. Bit test operations set the zero flag (Z) if the tested bit is a zero. (Refer to
section 6.0 for further explanation of flag operation).
JUMP, CALL AND RETURN
Figure 5.3-11 Iists all of the jump, call and return instructions implemented in the Z-80CPU. Ajump
is a branch in a program where the program counter is loaded with the 16-bit value as specified by one of the
three available addressing modes (Immediate Extended, Relative or Register Indirect). Notice that the jump
group has several different conditions that can be specified to be met before the jump will be made. If
these conditions are not met, the program merely continues with the next sequential instruction. The
conditions are all dependent on the data in the flag register. (Refer to section 6.0 for details on the flag
register). The immediate extended addressing is used to jump to any location in the memory. This instruction requires three bytes (two to specify the 16-bit address) with the low order address byte first
followed by the high order address byte.
31
Source and Destination
A
B
C
0
E
H
L
!HL)
CB
07
CB
00
CB.
01
CB
02
CB
03
CB
04
CB
05
CB
06
'RRC'
CB
OF
CB
DB
CB
09
CB
OA
CB
DB
CB
DC
CB
OD
CB
DE
'RL'
CB
17
CB
CB
CB
10
11
12
CB
13
CB
14
CB
15
CB
16
'RR'
CB
1F
CB
18
CB
19
CB
lA
CB
lB
CB
lC
CB
1D
CB
IE
'SLA'
CB
27
CB
20
CB
21
CB
22
CB
23
CB
24
CB
25
CB
26
'SRA'
CB
2F
CB
2B
CB
29
CB
2A
CB
2B
CB
2C
CB
2D
CB
2E
'RLC'
TYPE
OF
ROTATE
OR
SHIFT
'SRL'
CB
3F
CB
38
CB
39
CB
3A
CB
3B
CB
3C
r
CB
3D
CB
3E
'RLD'
ED
6F
'RRD'
ED
67
Rotate
Left Circular
!IX +d) (lY+d)
DO
CB
d
06
DO
CB
d
DE
oD
CB
d
16
DD
CB
d
IE
DD
CB
d
26
DD
CB
d
2E
DD
CB
d
3E
Fo
CB
d
06
FD
CB
d
DE
~
Fe
CB
d
1.----,:1
Ro""
~
~
Right Circular
~
~
Rotate
Left
16
Rotate
Right
Fe
CB
d
IE
FD
CB
d
26
Fo
CB
d
2E
Fe
CB
d
3E
~
rC~ ~
~
~
Shift
~
r~
Shift
~
r.J __
I'
Right Arithmetic
Right Logical
o
H
1 (HL)
~-A~C~cT'~~_ _~==~~~
:~~;e Digit
ROTATES AND SHIFTS
TABLE 5.3-9
For example an unconditional Jump to memory location 3E32H would be:
Address A
A+ 1
A+2
I C3 IOP Code
~ Low order address
~ High order address
The relative jump instruction uses only two bytes, the second byte is a signed two's complement displacement from the existing PC. This displacement can be in the range of +129 to -126 and is measured
from the address of the instruction OP code.
Tmee types of register indirect jumps are also included. These instructions are implemented by loading
the register pair HL or one of the index registers IX or IY directly into the PC. This capability allows for
program jumps to be a function of previous calculations.
A call is a special form of a jump where the address of the byte following the call instruction is
pushed onto the stack before the jump is made. A return instruction is the reverse of a call because the
data on the top of the stack is popped directly into the PC to form a jump address. The call and return
instructions allow for simple subroutine and interrupt handling, Two special return instructions have been
included in the Z-80 family of components. The return from interrupt instruction (RETI) and the return
from non maskable interrupt (RETN) are treated in the CPU as an unconditional return identical to the OP
code C9H. The difference is that (RETI) can be used at the end of an interrupt routine and all Z-80 peripheral
chips will recognize the execution of this instruction for proper control of nested priority interrupt handling.
This instruction coupled with the Z-80 peripheral devices implementation simplifies the normal return from
nested interrupt. Without this feature the following software sequence would be necessary to inform the
interrupting device that the interrupt routine is completed:
32
REG.
INDIR.
REGISTER ADDRESSING
A
B
C
D
E
H
L
IHL)
INDEXED
(lX+d)
(lY+d)
DD
CB
d
46
DD
CB
d
4E
DD
CB
d
56
DD
CB
d
5E
DD
CB
d
66
DD
CB
d
6E
DD
CB
d
76
DD
CB
d
7E
DD
CB
d
86
DD
CB
d
8E
DD
CB
d
96
DD
C8
d
9E
DD
C8
d
A6
DD
CB
d
AE
DD
CB
d
B6
FD
CB
d
46
FD
CB
d
4E
FD
CB
d
56
FD
CB
d
5E
FD
CB
d
66
FD
CB
d
6E
FD
CB
d
76
FD
CB
d
7E
FD
CB
d
86
FD
C8
d
8E
FD
CB
BIT
0
CB
47
CB
40
CB
41
CB
42
CB
43
CB
44
CB
45
CB
46
1
CB
4F
CB
4B
CB
49
CB
4A
CB
4B
CB
4C
CB
4D
CB
4E
2
CB
57
CB
CB
51
CB
52
CB
53
CB
50
54
CB
55
CB
56
CB
SF
CB
5B
CB
59
CB
SA
CB
5B
CB
5C
CB
5D
CB
5E
CB
67
CB
60
CB
61
CB
62
CB
63
CB
64
CB
65
CB
66
5
CB
6F
CB
6B
CB
69
CB
6A
CB
6B
CB
6C
CB
6D
CB
6E
6
CB
CB
70
CB
71
CB
77
72
CB
73
CB
74
GB
75
CB
76
7
CB
7F
CB
7B
CB
79
CB
7A
CB
7B
CB
7C
CB
7D
CB
7E
0
CB
B7
CB
BO
CB
B1
CB
B2
CB
B3
CB
B4
CB
85
CB
86
1
CB
8F
CB
88
CB
B9
C8
8A
CB
8B
CB
8C
CB
8D
CB
8E
2
CB
97
CB
90
CB
91
CB
92
CB
93
CB
94
CB
95
CB
96
3
CB
9F
CB
98
C8
99
CB
9A
CB
9B
CB
9C
CB
9D
CB
9E
4
CB
A7
CB
AO
CB
A1
C8
A2
CB
A3
CB
A4
CB
AS
CB
A6
5
CB
AF
CB
CB
A9
CB
AS
AA
CB
AB
CB
AC
CB
AD
CB
AE
6
CB
B7
CB
BO
CB
B1
CB
B2
CB
B3
CB
B4
CB
B5
CB
B6
7
CB
BF
CB
B8
CB
B9
CB
BA
CB
BB
CB
BC
CB
BD
CB
8E
CB
C7
CB
CB
C1
CB
CB
CB
C2
C3
C4
CB
C5
CB
C6
CB
CF
CB
C8
CB
C9
CB
CA
CB
CB
CB
CC
CB
CD
CB
CE
2
CB
07
CB
DO
CB
D1
CB
D2
CB
D3
CB
D4
CB
D5
CB
D6
3
CB
DF
CB
D8
CB
D9
CB
DA
CB
DB
CB
DC
CB
DD
CB
DE
4
CB
E7
CB
EO
CB
E1
CB
E2
CB
E3
CB
E4
CB
E5
CB
. E6
5
CB
EF
CB
E8
CB
E9
CB
EA
CB
EB
CB
EC
CB
ED
CB
EE
6
CB
F7
CB
FO
CB
F1
CB
F2
CB
F3
CB
F4
CB
F5
CB
F6
7
CB
FF
CB
FB
CB
F9
CB
FA
CB
FB
CB
FC
CB
FD
CB
FE
3
TEST
'BIT"
4
RESET
BIT
'RES'
0
1
SET
BIT
'SET"
CO
BIT MANIPULATION GROUP
TABLE 5.3-10
33
DD
CB
d
BE
DD
CB
d
C6
DD
CB
d
CE
DD
CB
d
D6
OD
CB
d
DE
DD
CB
d
E6
DO
CB
d
EE
DD
CB
d
F6
DD
CB
d
FE
d
96
FD
CB
d
9E
FD
CB
d
A6
FD
CB
d
AE
FD
CB
d
B6
FD
CB
d
BE
FD
CB
d
C6
FO
CB
d
CE
FD
CB
d
D6
FD
CB
d
DE
FD
CB
d
E6
FD
CB
d
EE
FD
CB
d
F6
FD
CB
d
FE
Disable Interrupt
prevent interrupt before
routine is exited.
LDA,n
OUTn,A
notify peripheral that service
routine is complete
Enable Interrupt
Return
This seven byte sequence can be replaced with the one byte EI instruction and the two byte RETI instruction
in the l80. TItis is important since interrupt service time often must be minimized.
To facilitate program loop control the instruction DJNl e can be used advantageously. This two byte,
relative jump instruction decrements the B register and the jump occurs if the B register has not been decremented to zero. The relative displacement is expressed as a signed two's complement number. A simple example of its use nlight be:
Address
Instruction
N, N+ 1
N + 2 to N+ 9
LDB, 7
Comments
; set B register to count of 7
(perform a sequence
of instructions)
N + 10, N+ 11
DJNl
N+ 12
(Next Instruction)
-8
; loop to be performed 7 times
; to jump from N + 12 to N + 2
CONDITION
JUMP
'JP'
IMMED.
EXT.
.JUMP
6JR'
RELATIVE
JUMP
'JP'
JUMP
'JP'
JUMP
'JP'
'CALL'
nn
PC+e
28
;w
e-2
e-2
(HL)
REG.
INDIR.
(IX)
(IV)
IMMED.
EXT.
nn
DECREMENT B,
JUMP IF NON
ZERO'DJNZ'
RELATIVE
PC+e
RETURN
'RET'
REGISTER
INDIR.
(SP)
(SP+l)
RETURN FROM
INT'RET/'
REG.
INDIR.
(SP)
(SP+l)
ED
4D
RETURN FROM
NON MASKABLE
INT'RETN'
REG.
INDIR.
(SP+l)
ED
45
NOTE-CERTAIN
FLAGS HAVE MORE
THAN ONE PURPOSE.
REFER TO SECTION
6_0 FOR DETAILS
JUMP, CALL and RETURN GROUP
TABLE 5.3-11
34
I'Table 5.3-12 lists the eight OP codes for the restart instruction. This instruction is a .single byte call to any
of the eight addresses listed. The simple mnemonic for these eight calls is also shown. The value of this instruction is that fr.equently used routines can be called with this instruction to minimize memory usage.
op
CODE
'RSTO'
'RST8'
C
'RST 16'
A
L
L
'RST 24'
A
D
o
R
E
'RST 32'
S
S
'RST 40'
'RST48'
'RST56'
RESTART GROUP
TABLE 5.3-12
INPUT/OUTPUT
The Z·80 has an extensive set of Input and Output instructions as shown in table 5.3-13 and table
.5.3-14. The addressing of the input or output device can be either absolute or register indirect, using the C
register. Notice that in the register indirect addressing mode data can be transferred between the I/O devices
and any of the internal registers. In addition eight block transfer instructions have been implemented. These
instructions are similar to the memory block transfers except that they use register pair HL for a pointer to
the memory source (output commands) or destination (input commands) while register B is used as a byte
counter. Register C holds the address of the port for which the input or output command is desired. Since
register:a is eight bits in length, the I/O block transfer command handles up to 256 bytes.
In the instructions IN A, n and OUT n, A the I/O device address n appears in the lower half of the address bus (Ao-A7) while the accumulator content is transferred in the upper half of the address bus. In all register indirect input output instructions, including block I/O transfers the co'htent of register C is transferred
to the lower half of the address bus (device address) while the content of register B is transferred to the
upper half of the address bus.
35
SOURCE
PORT ADDR ESS
B
ED
40
R
E
G
C
ED
48
A
INPUT'IN'
0
0
R
E
S
S
I
N
G
INPUT
DESTINATION
0
ED
50
E
ED
58
H
ED
60
L
ED
68
ED
A2
'INI' - INPUT &
Inc HL, DecB
'INIR'-INP, Inc HL,
Dec B, REPEAT IF B#O
REG;
INDIR
(HL)
ED
B2
'IND'-INPUT &
Dec HL, DecB
ED
AA
'INDR'-INPUT, Dec HL,
Dec B, REPEAT IF 8#0
ED
BA
BLOCK INPUT
COMMANDS
/
INPUT GROUP
TABLE 5.3-13
CPU CONTROL GROUP
The final table, table 5.3-15 illustrates the six general purpose CPU control instructions. The NOP is a donothing instruction. The HALT instruction suspends CPU operation until a subsequent interrupt is received,
while the DI and EI are used to lock out and enable interrupts. The three interrupt mode commands set the
CPU into any of the three available interrupt response modes as follows. If mode zero is set the interrupting
device can insert any instruction on the data bus and allow the CPU to execute it. Mode 1 is a simplified
mode where the CPU automatically executes a restart (RST) to location 0038H so that no external hardware
is required. (The old PC content is pushed onto the stack). Mode 2 is the most powerful in that it allows for
an indirect call to any location in memory. With this mode the CPU forms a 16-bit memory address where
the upper 8-bits are the content of register I and the lower 8-bits are supplied by the interrupting device.
This address points to the first of two sequential bytes in a table where the address of the service routine is
located. The CPU automatically obtains the starting address and performs a CALL to this address.
Address of interrupt { 1-----1
service routine
36
Pointer to Interrupt table. Reg.
I is upper address,
Peripheral supplies lower address
SOURCE
REG.
IND.
REGISTER
A
B
C
0
E
H
L
(HLI
IMMED.
(n)
REG.
IND.
(C)
'OUTI' - OUTPUT
Inc HL, Decb
REG.
IND.
(C)
ED
A3
'OTIR' - OUTPUT, Inc HL,
Dec B, REPEAT IF B~
REG.
IND.
(C)
ED
B3
'OUTD' - OUTPUT
Dec HL& B
REG.
IND.
(C)
ED
AB
'OTDR' - OUTPUT, Dec HL
& B, REPEAT IF B*O
REG.
IND.
(C)
ED
BB
'OUT'
ED
ED
ED
ED
ED
ED
ED
79
41
49
51
59
61
69
.\
'---y----/
PORT
DESTINATION
ADDRESS
OUTPUT GROUP
TABLE 5.3-14
'NOP'
'HALT'
DISABLE INT '(01)'
ENABLE INT '(EI)'
SETINT MODE 0
'IMO'
ED
46
8080AMODE
SET INT MODE 1
'IM1'
ED
56
CALL TO LOCATION 0038 H
SET INT MODE 2
'1M2'
ED
5E
INDIRECT CALL USING REGISTER
I AND 8 BITS FROM INTERRUPTING
DEVICE AS A POINTER.
MISCELLANEOUS CPU CONTROL
TABLE 5.3-15
37
BLOCK
OUTPUT
COMMANDS
,
-BLANK-
-38-
6.0 FLAGS
Each of the two Z-80 CPU Flag registers contains six bits of information which are set or reset by
various CPU operations. Four of these bits are testable; that is, they are used as conditions for jump, call or
return instructions. For example a jump may be desired only if a specific bit in the flag register is set. The
four testable flag bits are:
1) Carry Flag (C) - This flag is the carry from the highest order bit of the accumulator. For example, the
carry flag will be set during an add instruction where a carry from the highest bit of the accumulator
is generated. This flag is also set if a borrow is generated during a subtraction instruction. The shift
and rotate instructions also affect this bit.
2) Zero Flag (Z) - This flag is set if the result of the operation loaded a zero into the accumulator. Otherwise it is reset.
3) Sign Flag (S) - This flag is intended to be used with signed numbers and it is set if the result
of the operation was negative. Since bit 7 (MSB) represents the sign of the number (A negative
number has a 1 in bit 7), this flag stores the state of bit 7 in the accumulator.
4) Parity/Overflow Flag (P/V) - This dual purpose flag indicates the parity of the result in the accumulator
when logical operations are performed (such as AND A, B) and it represents overflow when signed
two's complement arithmetic operations are performed. The Z-80 overflow flag indicates that the
two's complement number in the accumulator is in error since it has exceeded the maximum possible (+ 127) or is less than the minimum possible (-128) number than can be represented in two's
complement notation. For example consider adding:
+120 =
+105 =
C=
0111 1000
0110 1001
a
1110 0001 = -95 (wrong) Overflow has occured
Here the result is incorrect. Overflow has occurred and yet there is no carry to indicate an error.
For this case the overflow flag would be set. Also consider the addition of two negative numbers:
-5
=
-16 =
C =
11111011
1111 0000
1110 1011 = -21 correct
Notice that the answer is correct but the carry is set so that this flag can not be used as an overflow indicator. In this case the overflow would not be set.
For logical operations (AND, OR, XOR) this flag is set if the parity of the result is even and it is
reset if it is odd.
There are also two non-testable bits in the nag register. Both of these are used for BCD arithmetic. They are:
1) Half carry (H) - This is the BCD carry or borrow result from the least significant four bits of operation.
When using the DAA (Decimal Adjust Instruction) this flag is used to correct the result of a
previous packed decimal add or subtract.
2) Subtract Flag (N) - Since the algorithm for correcting BCD operations is different for addition or
subtraction, this flag is used to specify what type of instruction was executed last so that the
DAA operation will be correct for either addition or subtraction.
The Flag register can be accessed by the programmer and its format is as follows:
I S IZ I X IH IX Ip/VI N IC I
X means flag is indeterminate.
39
Table 6.0-1 lists how each flag bit is affected by various C~U instructions. In this table a '.' indicates
that the instruction does not change the flag, an 'X' means that the flag goes to an indeterminate state, a '0'
m~ans that it is reset, a '1' means that it is set and the symbol '~' indicates that it is set or reset according to
the previous discussion. Note that any instruction not appearing in this table does not affect any of the flags.
Table 6.0-1 includes a few special cases that must be described for clarity. Notice that the block search
instruction sets the Z flag if the last compare operation indicated a match between the source and the
accumulator data. Also, the parity flag is set if the byte counter (register pair Be) is not equal to zero. This
same use of the parity flag is made with the block move instructions. Another special case is during block
input or output instructions, here the Z flag is used to indicate the state of register B which is used as a byte
counter. Notice that when the I/O block transfer is complete, the zero flag will be reset to a zero (i.e. B=O)
while in the case of a block move command the parity flag is reset when the operation is complete. A final
case is when the refresh or I register is loaded into the accumulator, the interrupt enable flip flopis loaded
into the parity flag so that the complete state of the CPU can be saved at any time.
40
Instruction
ADD A, s; ADC A,s
SUB s; SBC A, s, CP s, NEG
f\
0
0
e
e
ANDs
ORs; XORs
INC s
DECm
ADDDD,ss
ADC HL,ss
SBC HL,ss
RLA;RLCA,RRA,RRCA
RL m; RLC m; RR m; RRC m
SLA m; SRA m; SRL m .
RLD,RRD
DAA
CPL
SCF
CCF
IN r, (C)
INI; IND; OUTI; OUTD
INIR; INDR; OTIR; OTDR
LDI,LDD
LDIR,LDDR
CPI, CPIR, CPD, CPDR
Comments
8-bit add or add with carry
8-bit subtract, subtract with carry, compare and
negate accumulator
} Logical operations
P t 0
And set's different flags
P t 0 0
8-bit increment
V t 0 f
8-bit decrement
V t
t
e e o X
16-bit add
16-bit add with carry
V t oX
16-bit subtract with carry
V t I X
e e 0 0
Rotate accumulator
Rotate and shift location m
P t 0 0
CZ
S NH
t t V t ot
t
t t V t
t
t
t
t
t e
t t
t t
t e
t t
t
Rotate digit left and right
0 0
e t
Decimal adjust accumulator
Complement accumulator
I
0 0
Set carry
Complement carry
0 X
Input register indirect
0 0
I X } Block input and output
I X
Z = 0 ifB 0 otherwise Z = I
0 0 } Block transfer instructions
o 0 0 P/V = 1 ifBC 0, otherwise P/V = 0
t ~ I X Block search instructions
Z = I if A = (HL), otherwise Z = 0
P/V = I if BC 0, otherwise P/V = 0
e t FFt 0 0
The content of the interrupt enable flip-flop (IFF)
is copied into the P/V flag
The state of bit b oflocation s is copied into the Z flag
e t
0 I
~ ~ V ~ I ~
Negate accumulator
e
t
t
e •
I e
t •
e t
e t
e I
eX
eX
• t
P
P
e
e
e
P
X
X
t
t
t
e
e
•
t
X
X
X
X
*'
*'
*'
LDA, I; LD A, R
BITb, s
NEG
xix
The following notation is used in this table:
Op~tion
Symbol
C
Carry/link flag. C=1 if the operation produced a carry from the MSB of the operand or result.
Z
Zero flag. Z= 1 if the result of the operation is zero.
S
Sign flag. S=1 if the MSB of the result is one.
PlY
Parity or overflow flag. Parity (P) and overflow (V) share the same)lllg. Logical operations affect this flag
with the parity of the result while arithmetic operations affect this flag with the overflow of the result. If PlY
holds parity, P/V=1 if the result of the operation is even, P/V=O if result is odd. If PlY holds overflow, P/V=l
if the result of the operation produced an overflow.
H
N
Half-carry flag. H=1 if the add or subtract operation produced a carry into or borrow from into bit 4 of the accumulator.
Add/Subtract flag. N=l if the previous operation was a subtract
Hand N flags are used in conjunction with the decimal adjust instruction (DAA) to properly correct the result into packed nco format following addition or sub~tion using operands with packed BCD format.
t
The flag is affected according to the result of the operation.
The flag is unchanged by the operation.
The flag is reset by the operation.
The flag is set by the operation.
The flag is a "don't care_"
PlY flag affected according to the overflow result of the operation.
PlY flag affected according to the parity result of the operation.
•
o
1
X
V
P
s
S5
ii
R
n
nn
m
Anyone of the CPU registers A, B, C, D, E, H, L.
Any 8-bit location for all the addressing modes allowed for the particular instruction.•
Any 16-bit location for all the addressing modes allowed for that instruction.
Anyone of the two index registers IX or IY ..
Refresh counter.
8-bit value in range <0. 255>
16-bit value in range <0. 65535>
Any 8-bit location for all the addressing modes allowed for the particular instruction.
SUMMARY OF FLAG OPERATION
TABLE 6.0-1
41
-BLANK-
-42~
7.0 SUMMARY OF OP CODES AND EXECUTION TIMES
The following section gives a summary of the Z-80 instructions set. The instructions are logically arranged
into groups as shown on tables 7.0-1 through 7.0-11. Each table shows the assembly language mnemonic
OP code, the actual OP code, the symbolic operation, the content of the flag register following the execution of each instruction, !..he number of bytes required for e.ach instruction as well as the number of memory
cycles and the total number of T states (external clock periods) required for the fetching and execution of
each instruction. Care has been taken to make each table self-explanatory without requiring any cross reference with the test or other tables.
43
Symbolic
Operation
Mnemonic
LD r, r'
LD r, n
r~r'
r ... n
OP-Code
Flags
C ZP/V S N H 76 543 210
•
• • 01 r r'
• •
• 00 r 110
+n
• 01 r 110
~
11 011 101
• •
01 r no
....
d
• • •
• • •
•
.
• • •
• •
LD r, (HL)
LD r, (IX+d)
r +- (HL)
r +- (IX+d)
LD r, (IY+d)
r ... (IY+d)
• • • • • •
LD (HL), r
LD (IX+d), r
(HL) +- r
(IX+d) ... r
• • • • • •
• • • • • •
LD (IY+d), r
(IY+d) ... r
• •
•
LD (HL), n
(HL) +- n
• •
• • •
LD (IX+d), n
(IX+d) ... n
• • • • • •
....
..
No.
of
Bytes
1
2
No.
ofM
Cycles
1
2
1
3
2
7
5
19
3
5
19
1
3
2
5
7
3
5
19
2
3
10
4
5
19
4
5
19
1
1
3
2
2
7
7
4
13
1
1
3
2
2
7
4
13
2
2
9
2
2
9
No.
orT
Cycles
4
.7
...
11 III 101
01 r 110
d
01 1I0 r
11 011 101
01 llO r
d
11 III 101
• • •
01 llO r
+- d
00 llO llO
•
+- n
II 011 101
00 llO 110
+- d
+- n
11 III 101
00 llO 110
+- d
->
->
+- n
• 00 001 010
00 011 010
•
• 00 III 010
->
n
+- n
->
• 00 000 010
00 OlD 010
00 llOOIO
->
n
->
n
tIFF t 0 0 11 101 101
01 010 III
tIFF t 0 0 11 101 101
01 011 III
11 101 101
•
01 000 III
11 101 101
01 001 III
...
...
....
19
....
....
....
....
....
.
LD (IY+d), n
(IY+d) +- n
• • • • •
LD A, (BC)
LD A, (DE)
LD A, (nn)
A+- (BC)
A+-(DE)
A+- (nn)
• • • • •
• • • • • •
• • • •
LD (BC),A
LD (DE), A
LD (nn), A
(BC)+-A
(DE)+-A
(nn) ... A
• • • • •
• • • • • •
• • • • • •
LDA,I
A ... I
•
LDA,R
A ... R
•
LD I,A
I ... A
• • •
• •
2
2
9
LDR,A
R ... A
• • • • • •
2
2
9
Notes:
...
...
...
I
r, r' means any of the registers A, B, C, D, E, H, L
IFF the content of the interrupt enable flip-flop (IFF) is copied into the P/V flag
Flag Notation:
•
= flag not affected, 0 =flag reset, 1 =flag set, X = flag is unknown,
~
= flag is affected according to the result of the operation.
S-BIT LOAD GROUP
TABLE 7.0-'
44
7
Comments
r, r'
Reg.
000
B
001
C
010
D
011
E
100
H
101
L
III
A
Flap
Mnemonic
LDdd,nn
LD IX,nn
Symbolic
Operation
dd_nn
IX-nn
LDIY,nn
IV-nn
LD HL,(nn)
H-(nn+l)
L-(nn)
LDdd, (nn)
dd H -(nn+l)
dd L _Inn)
LDIX, (nn)
IXH-(nn+l)
IXL -(nn)
LDIY,(nn)
IYH-(nn+l)
IYL _(nn)
LD (nn),HL
(nn+l) _H
(nn)-L
LD (nn),dd
(nn+l) -ddH
(nnl-dd L
LD(nn),IX
LD(nn),IY
(nn+l) -IXu
(nil)-IXL
(M+l)-IYH
(nn)-IYL
LDSP, HL
LDSP,IX
SP-HL
SP-IX
LDSP,IY
SP-IY
PUSHqq
(SP-2) -q'lL
(SP-I) -qqH
(SP-2)-IXL
(SP-I) -IXu
(SP-2l-IYL
(SP-i)-IYH
qqH--(SP+l)
qqL -(SP)
IXH-(SP+I)
IXL -(SP)
lYH-(SP+I)
lYL -(SP)
PUSH IX
PUSHIY
POPqq
POP IX
POPIY
Notes:
zl\
Oo-Cocle
No.
01
Byl..
No.
aIM
Cycles
No.
ofT
Stales
3
3
10
4
4
14
4
4
14
3
5
16
4
6
20
4
6
20
4
6
20
3
5
16
4
6
20
4
6
20
4
6
20
11 III 001
11 011 101
11 III 001
II 111 101
11 III 001
11 qqO 101
1
2
I
2
6
10
2
2
10
1
3
11
11
11
11
11
11
2
4
15
2
4
15
I
3
10
2
4
14
2
4
14
· ···. • • · ·. .-·• • • • •
-• ·· ·..
-• ·. ·..
·
.
.
· .·
-•
··. ·.
-• • • ·. .
-·..·..
-•
•
•
·
.
·
-·
.
.
·
.
·
...
·• .• ·• .·.· .. ·.·.· .
· . • ·..
••••••
·. ·.· .
· .• • • •
·. · . • •
• • • • ·.
C
•
S N H 76 543 210
--
00 ddO 001
n
n
11 011 101
00 100001
n
n
11 III 101
00 100 001
n
n
00 101 010
n
n
11 101 101
01 ddl 011
n
n
11 011 101
00 101 010
n
n
11 111 101
00 101 010
n
n
00 100010
n
n
11 101 101
01 ddOOIl
n
n
11 011 101
00 100010
n
n
II III 101
00 100 010
n
...
...
Comments
dd
00
01
10
11
Pair
Be
DE
HL
SP
'1'1
Pair
00
01
10
11
BC
...
-
...
...
...
...
-...
...
-...
...
...
...
-...
...
n
011
100
III
100
qqO
...
101
101
101
101
001
11 011 101
11 100 001
11 111 101
11 100 001
dd Is any of Ihe repsler pairs BC, DE, HL, SP
qq is any ofthuesister pairs AF, BC, DE, HL
(PAIR)H' (PAIR)L refer io high order and low order eighl bits of the register pair reopeclively.
E.g. BeL =C,AFH=A
FJaa Notation:
• = I\ag Dol affected, 0 = I\ag re..t, 1 = I\ag set, X = flag is unknown,
I\ag i. affected accordill/l 10 the resull of the operation.
*
16-BIT LOAD GROUP
TABLE 7.0.2
45
DE
HL
AF
Op-Code
Flags
• • • • • •
• • • • • •
• • • • • •
II 101 all
00 001 000
11 all 001
No.
of
Bytes
1
1
I
H .. (SP+1)
L -(SP)
IXH++(SP+ I)
IX L - (SP)
IY H-(SP+I)
IY L -(SP)
• • • • • •
11 100 all
I
5
19
• • • • • •
11
11
11
II
all
100
III
100
101
all
101
all
2
6
23
2
6
23
LDI
(DE)- (HL)
DE -DE+I
HL - HL+I
BC - BC-I
• •
I
• a
a
11 101 101
10 100 000
2
4
LDIR
(DEI - (ilL)
• •
0
•
0 II 101 101
10 110000
2
2
5
II 101 101
Symbolic
Operation
DE··HL
AF ·.AF'
Mnemonic
EX DE, HL
EXAF,AF'
EXX
(~M~)
EX (SP), HL
EX (SP), IX
EX (SP), IY
('
~
Z V S N H 76 543 210
• • • • • •
48
Symbolic
Operation
Mnemonic
ADD HL, ss
HL-HL+ss
~
r"
• • •
S N H 76 543 210
Z
ADCHL, ss
HL-HL+ss+CY
~
~
V
~
SBC HL,
HL-HL- 55 -<:Y
~
~
V
~
IX-IX+pp
~
• • •
SS
ADD IX, pp
Op-<:ode
Flags
C
• • •
0 X 00 ssl 001
101
551
101
ssO
0 X 11 011
00 ppl
0 X 11
01
I X 11
01
0 X II III 101
00 rrl 001
ADD IY,n
IY-IY+rr
~
INC 55
55-55+1
• • • • • •
INC IX
IX - IX + I
• • • • • •
INC IY
IY -IY + I
• • • • • •
DEC ss
ss
ss - 1
• • • • • •
DEC IX
IX-lX-I
• • • • • •
DECIY
IY-IY-I
• • • • • •
Notes:
+-
101
010
101
010
101
001
No.
of
Bytes
No.
ofM
Cycles
No.
ofT
States
I
3
11
2
4
15
2
4
15
2
4
15
•
~
2
4
15
00 550 011
1
1
6
II
00
II
00
00
Oil
100
III
100
551
101
Oil
101
011
011
2
2
10
2
2
10
I
I
6
II
00
11
00
011
101
III
101
101
011
101
Oil
2
2
10
2
2
10
= nag not affected, 0 = tlag reset, I = flag set. X = flag is unknown.
= nag is affected according to the result of the operation.
16-BIT ARITHMETIC GROUP
TABLE 7.0-6
49
ss
00
01
10
II
pp
00
01
10
II
ss is any of lhe register pairs BC, DE, HI., SP
pp is any of the register pairs BC, DE, IX, SP
rr is any of the register pairs BC, DE,IY. SP.
Flag Notation:
Comments
rr
00
01
10
11
Reg.
DC
DE
HL
SP
Reg.
BC
DE
IX
SP
Reg.
BC
DE
IY
SP
Flags
~
Symbolic
Operation
Mnemonic
Op-Code
C Z V S N H 76 543 210
No.
of
Bytes
No.
ofM
Cycles
No.
ofT
States
Comments
~
t
• • •
0 0 00 000 111
1
1
4
Rotate left circular
accumulator
~
t
• • •
0 0 00 010 111
1
1
4
Rotate left
accumulator
~
t
• • •
0 0 00 001 111
1
1
4
~
t
• • •
0 0 00 011 111
1
1
4
Rotate right
accumulator
RLCr
t
t
P t
2
2
8
Rotate left circular
register r
RLC (HL)
t t
P t
2
4
15
t
P t
0 0 11 001 011
0010001 r
0 0 11 001 011
0010001110
0 0 11 011 101
11 001 011
-+
d
0010001 1 10
0 0 11 111 101
11 001 OIl
-+
d
0010001110
4
6
23
4
6
23
r
000
001
010
011
100
101
111
RLCA
A
RLA
A
RRCA
A
RRA
A
~
RLC (IX+d)
t
r. (Ht), (lX+d), (IYi-d)
~
RLC (IY+d)
t
t
P t
Rotate right circular
accumulator
R£g.
B
C
D
E
H
L
A
...
L&=E3J
t
t
P t
0 0
10101
~La
t
t
P t
0 0
10011
~
t
t
P t
0 0
[QTIJ
t
t
P t
0 0
11001
~
t
t
p
t
0 0
[}QI]
o~
t
t
P t
0 0
[ill]
RLD
A~(HL) •
t
P t
0 0 11 101 101
01 101 111
2
5
18
RRD
A~(HL) •
t
p
0 0 11 101 101
01 100 111
2
5
18
RLm
Instruction format and
states are as shown
for RLC,m. To form
new OP·code replace
[QQQ)of RLC,m with
shown code
mO=l,(HL).(IX+d), (lY+d)
RRCm
m ~r.(HL), (lX+d), (IY+d)
RRm
m:=: r, (ilL), (IX+d). (IY+d)
~o
SLAm
m =:: r, (HL),(lX+d), (IY+d)
SRAm
m == r, (ilL), (IX+d), (IY+d)
SRLm
m =r,(HL),(IX+d), (lV+d)
Flag Notation:
t
• =;'ilag not affe~ted, 0 =flag reset, 1 =flag set, X = flag is unknown,
t = flag is affected according to the result of the operation.
ROTATE AND SHIFT GROUP
TABLE 7.0-7
50
Rotate digit left and
right between the
accumulator
and location (HL).
The content of the
upper half of the
accumulator is
unaffected
Flags
Op'("ode
~
Symbolic
Operation
C Z V S N H 76 543 210
BIT b, r
Z+-'b
BIT b, (HL)
BIT b, (IX+d)
Mnemonic
BIT b, (IY +d)
•
t
X X 0
I
Z+-(HL)b
•
t
X X 0
I
Z +- (IX+d)b
•
t
X X 0
I
Z +- (IY+d)b
•
t
X X 0
I
• • • • • •
SETb, r
rb +-1
SETb, (HL)
(HL)b
SET b, (IX+d)
(IX+d)b +- 1
• • • • • •
SET b, (IY +d)
(IY+d)b +- I
• • • • • •
RES b, m
+-
I
• • • • •
0
11
01
11
01
11
11
+01
11
001
b
001
b
011
001
d
b
III
11 001
+- d
01 b
011
r
011
110
101
011
/Ilo.
of
Bytes
No.
ofM
Cycles
No.
ofT
States
2
2
8
2
3
12
4
5
20
-+
110
101
011
4
5
20
2
2
8
2
4
15
4
6
23
4
6
23
-+
110
II 001 011
r
ITIJb
11 001 011
ITIJb 110
11 011 101
11 001 Oil
-+
+d
/IIlb 110
II III 101
II 001 011
+-+
d
[TI] b 110
[!Q]
~+-O
m=r, (HL),
(IX+d),
(IY+d)
Notes:
The notation sb indicates bit b (0 to 7) or location s.
Flag Notation:
• = nag not affected, 0 = nag reset, I = flag set. X = nag is unknown,
t = nag is affected according to the result of the operation.
BIT SET, RESET AND TEST GROUP
TABLE 7.0-8
51
Comments
r
000
001
010
011
100
101
III
Reg.
B
C
0
E
H
L
b
000
001
010
011
100
101
110
111
Bit Tested
A
0
I
2
3
4
5
6
7
To fonn new Op·
code replace IT]
of SET b,Ill with
@. Flags and time
states for SET
instruction
Flags
Op-Code
Symbolic
Operation
C Z
JP nn
PC"'nn
• • • • • •
JP cc, nn
If condition cc
is true PC <-nn,
otherwise
continue
• • • • • •
. • ..
JRC,e
IfC = 0,
continue
• • • •
If Z = 0
continue
•
.
IfZ = I,
PC ... PC+e
JR NZ,e
If Z = I,
continue
11 000 011
n
.... n
11 cc 010
+n
n
3
3
10
3
3
10
00 011 000
2
3
12
cc
000
001
010
011
100
101
110
111
2
2
7
If condition not met
2
3
12
If condition is met
2
2
7
If condition not met
2
3
12
If condition is met
2
2
7
If condition not met
2
3
12
If condition is mel
2
2
7
If condition not mt'
2
3
12
If condition met
...
...
• •
..
....
....
....
... e-2 ....
• • 00 111 000
... e-2 ....
• • • • • •
If C = 0,
PC ... PC+e
JRZ,e
No.
ofT
States
...
PC ... PC+e
JR NC, e
No.
ofM
Cycles
VS N H 76 543 210
JRe
IfC = I,
PC ... PC+e
IfC = I,
continue
No.
of
Bytes
~
Mnemonic
•
..
•
-.
..
•
• •
..
00 110000
e-2 ....
...
00 101 000
e-2 ....
...
..
00 100 000
e-2
-
IfZ = 0,
pe-PC+e
....
.
Comments
Condition
NZnon uro
Z zero
NCnon carry
C carry
PO parity odd
PE parity even
P sign positive
M sign negative
JP(HL)
PC-HL
• • • • • •
II 101 001
I
I
4
JP (IX)
PC-IX
• • • • • •
2
2
8
JP (IV)
PC-IV
•
II
11
II
11
2
2
8
DJNZ,e
B -B·I
IfD = 0,
continue
• • • • • •
2
2
8
IfD = 0
2
3
13
IF D '" 0
. ..
• • •
011
101
111
101
101
001
101
001
00 010 000
-
e-2
....
IfD '" 0,
PC ... PC+e
Notes:
e represents the extension in the relative addressing mode.
e is a signed two's complement number in the range <-126, 129>
e-2 in the op-code provides an effective address of pc +e as PC is
incremented by 2 prior to the addition of ~
Flag Notation:
.. = flag not affected, 0 = flag reset, 1 = flag set, X = flag is unknown,
~ = flag is affected according to the result of the operation.
JUMP GROUP
TABLE 7.0-9
52
Flags
Mnemonic
Symbolic
Operation
C Z V S N H 76 543 210
No.
of
Bytes
No.
ofM
Cycles
No.
ofT
States
II 001 101
+- n
+- n
3
5
17
II cc 100
3
3
10
If cc is false
....
....
If cc is true
~
CALLnn
(SP-I)+-PC H
(SP-2)+-PC L
PC+-nn
• •
CALLcc, nn
If condition
cc is false
continue,
otheIWise
same as
CALLnn
•
RET
PCL<-(SP)
PCH<-(SP+l)
RETcc
If condition
cc is false
continue,
otheIWise
same as
RET
RETI
RETN
RSTp
Rllturn from
interrupt
Return from
non maskable
interrupt
(SP.I)+-PCH
(SP.2)+-PC L
PCH+-O
PCL ....P
Op.(:ode
. .. .. ..
.. • • . ..
....
....
Comments
n
....
n
-+
3
5
17
. .. .. . .. ..
11 001 001
I
3
10
.. .. • .. .. ..
11 cc
1
I
5
If cc is false
1
3
11
2
4
14
2
4
14
If cc is true
cc
Condition
000 NZ
non zero
001
Z
zero
010 NC
non carry
011 C
carry
100 PO
parity odd
101
parity even
PE
110 P
sign positive
III M
sign negative
1
3
11
.. . • .. .. ..
.. .. .. .. .. .
.. .. .. . .. .
000
11 WI 101
01 001 101
11 101 101
01 000 101
11 t III
t
000
001
010
011
100
101
110
111.
Flag Notation:
• = flag not affected, 0 = flag reset, 1 = flag set, X = flag is unknown
= flag is affected according to the result of the operation.
*
CAL.L. AND RETURN GROUP
TABLE 1.0·10
53
P
OOH
08H
lOH
18H
20H
28H
30H
38H
.
Flags
Op-Code
No.
of
Bytes
No.
ofM
Cycles
No.
ofT
States
II 011 011
<0-+
n
II 101 101
01 r 000
2
3
11
2
3
12
X II 101 101
10 100 010
2
1 X X 1 X II 101 101
10 110 010
2
2
~
Mnemonic
Symbolic
Operation
IN A, (n)
A+- (n)
• • • • • •
IN r, (e)
r--:- (e)
ifr = llO only
the flags will
be affected
•
(HL) +- (C)
B+-B-l
HL+-HL+ 1
(HL) +- (C)
B+-B-l
X
t
X
C Z V S N H 76 543 210
t
P
t
0
t
Comments
ntoAo -~
Acc to AS - AI5
CtoAo -A 7
B to AS - AI5
CD
INI
INIR
X X I
HL ---HL+ 1
Repeat until
B=O
IND
(HL)+- (C)
. B+-B-l
HL---HL-l
(HL) +- (C)
B ---B-1
HL+-HL-l
Repeat until
B=O
INDR
X
X
'T'
'-!.J
t
16
CtoA O -A 7
B to AS - A 15
5
(If B ... 0)
21
CtoAO - ~
4
(If B = 0)
16
4
4
B to AS - AI5
16
X X 1 X 11 101 101
10 101 010
2
1 X X 1 X II 101 101
10 111 010
2
5
(If B ... 0)
21
2
4
(If B = 0)
16
CtoAo -A7 .
B to AS - Al5
Cto AO - A7
B to AS - AI5
OUT (n),A
(n) +-A
• • • • • •
11 010 011
_n_
2
3
II
OUT (C), r
(e) +- r
• • • • • •
11 101 101
01 r 001
2
3
12
OUTI
(C) +- (HL)
B+-B-l
X
t
X II 101 101
10 100011
2
4
16
Cto AO - A7
B 10 Ag - AI5
X
1 X X 1 X II 101 101
10 110 011
2
5
(lfB'" 0)
21
Clo Au - A7
B 10 AS - AI5
2
4
(If B = 0)
16
n to AO - A7
Acc to AS - AI5
Cto AO - A7
BtoA S -A I5
CD
HL---HL+ 1
(C) +- (HL)
B ---B-1
HL +-HL + 1
Repeat until
B=O
OTIR
(C) +-(HL)
OUTD
CD
X
t
B +-B - I
HL+-HL-l
OTDR
Notes:
(C) --- (HL)
B---B-I
HL+-HL-l
Repeat until
B=O
CD
X X I
X
I
4
2
X X I
2
5
(If B ... 0)
21
2
4
(IfB = 0)
16
X II 101 101
10 111 011
• = flag not affected, 0 = flag reset, 1 = flag set, X = flag is unknown,
t = flag is affected according to the result of the operation.
INPUT AND OUTPUT GROUP
TABLE 7.0-11
54
(' 10 AO - A7
B 10 AS - AI5
If the result of B-1 is zero the Z flag is set, otherwise it is reset·
Flag Notation:
16
X X 1 X II 101 101
10 101 011
Cto AO - A7
Bto AS - AI5
8.0 INTERRUPT RESPONSE
The purpose of an interrupt is to allow peripheral devices to suspend CPU operation in an orderly
manner and force the CPU to start a peripheral service routine. Usually this service routine is involved with
the exchange of data, or status and control information, between the CPU and the peripheral. Once the
service routine is completed, the CPU returns to the operation from which it was interrupted.
INTERRUPT ENABLE - DISABLE
The Z80 CPU has two interrupt inputs, a software maskable interrupt and a non maskable interrupt.
The non maskable interrupt (NMI) can not be disabled by the programmer and it will be accepted whenever a peripheral device requests it. This interrupt is generaliy reserved.for very important functions that
must be serviced whenever they occur, such as an impending power failure. The maskable interrupt (INT)
can be selectively enabled or disabled by the programmer. This allows the programmer to disable the interrupt during periods where his program has timing constraints that do not allow it to be interrupted. In the
Z80 CPU there is an enable flip flop (called IFF) that is set or reset by the programmer using the Enable
Interrupt (EI) and Disable Interrupt (DI) instructions. When the IFF is reset, an interrupt can not be
accepted by the CPU.
Actually, for purposes that will be subsequently explained, th:ere are two enable flip flops, called IFF I
and IFF2 .
Actually disables interrupts
from being accepted.
Temporary storage location
for IFF I .
The state of IFF I is used to actually inhibit interrupts while IFF2 is used as a temporary storage location
for IFF 1. The purpose of storing the IFF 1 will be subsequently explained.
A reset to the CPU will force both IFF I and IFF 2 to the reset state so that interrupts are disabled.
They can then be enabled by an EI instruction at any time by the programmer. When an EI instruction is
executed, any pending interrupt request will not be accepted until after the instruction following EI has
been executed. This single instruction delay is necessary for cases when the following instruction is a return
instruction and interrupts must not be allowed until the return has been completed. The EI instruction sets
both IFF 1 and IFF2 to the enable state. When an interrupt is accepted by the CPU, both IFF 1 and IFF2
are automatically reset, inhibiting further interrupts until the programmer wishes to issue a new EI instruction. Note that for all of the previous cases, IFF 1 and IFF2 are always equal.
The purpose of IFF2 is to save the status of IFF} when a non maskable interrupt occurs. When a non
maskable interrupt is accepted, IFF} is reset to prevent further interrupts until reenabled by the programmer. Thus,after a non maskable interrupt has been accepted, maskable interrupts are disabled but the
previous state of IFF 1 has been saved so that the complete state of the CPU just prior to the non maskable
interrupt can be restored at any time. When a Load Register A with Register I (LD A, I) instruction or a
Load Register A with Register R (LD A, R) instruction is executed, the state ofIFF2 is copied into the
parity flag where it can be tested or stored.
A second method of restoring the status of IFF 1 is thru the execution of a Return From Non
Maskable Interrupt (RETN) instruction. Since this instruction indicates that the non maskable interrupt
service routine is complete, the contents of IFF2 are now copied back into IFF 1, so that the status of IFF 1
just prior to the acceptance of the non maskable interrupt will be restored automatically.
55
Figure 8.0-1 is a summary of the effect of different instructions on the two enable flip flops,
Action
IFF} IFF2
CPU Reset
0
0
DI
0
0
EI
1
LDA,I
•
IFF 2 "+ Parity flag
LDA,R
•
•
•
IFF 2 "+ Parity flag
Accept NMI
0
•
IFF2
•
RETN
IFF2 "+lFFl
"." indicates no change
FIGURE 8.o.1
INTERRUPT ENABLE/DISABLE FLIP FLOPS
CPU RESPONSE
Non Maskable
A nonmaskable interrupt will be accepted at all times by the CPU. When this occurs, the CPU ignores
the next instruction that it fetches and instead does a restart to location 0066H. Thus, it behaves exactly as
if it had received a restart instruction but, it is to a locatiort that is not one of the 8 software restart locations. A restart is merely a call to a specific address irt page 0 of memory.
Maskable
The CPU cart be programmed to respond to the maskable interrUpt in arty one of three possible
modes.
Mode 0
This mode is identical to the 8080A interrupt response mode. With this mode, the interrupting device
can place any instruction on the data bus and the CPU will execute it. Thus, the interrupting device provides the next instructiort to be executed instead of the memory. Often this will be a restart instructiort
since the interrupting device only need supply a single byte instruction. Alternatively; any other instruction
such as a 3 byte call to any location in memory could be executed.
The number of clock cycles necessary to execute this instruction is 2 mote than the normal number for the
instruction. This occurs since the CPU automatically adds 2 wait states to an interrupt response cycle to
allow sufficient time to implement an external daisy cha.in for priority control. Section 5.0 illustrates the
detailed timing for an interrupt response. After the application of RESET the CPU will automatically enter
interrupt Mode O.
Mode}
When this mode has been selected by the programrrter, the CPU will respond to an interrupt by
executing a restart to location 0038H. Thus the response is iderttical to that for a non maskable interrupt
except tha.t the call location is 0038H instead of 0066H. Another difference is that the number of cycles
required to complete the restart instruction is 2 more than normal due to the two added wait states.
56
Mode 2
This mode is the most powerful interrupt response mode. With a single 8 bit byte from the user an
indirect call can be made to any memory location.
With this mode the programmer maintains a table of 16 bit starting addresses for every interrupt
service routine. This table may be located anywhere in memory. When an interrupt is accepted, a 16 bit
pointer must be formed to obtain the desired interrupt service routine starting address from the table.
The upper 8 bits of this pointer is formed from the contents of the I register. The I register must have been
previously loaded with the desired value by the programmer, i.e. LD I, A. Note that a CPU reset clears the I
register so that it is initialized to zero. The lower eight bits of the pointer must be supplied by the interrupting device. Actually, only 7 bits are required from the interrupting device as the least significant bit must be
a zero. This is required since the pointer is used to get two adjacent bytes to form a complete 16 bit service
routine starting address and the addresses must always start in even locations.
Interrupt
Service
Routine
Starting
Address
Table
desired starting address
pointed to by:
low order }
< high
order
I REG
CONTENTS
7 BITS FROM
PERIPHERAL
The first byte in the table is the least significant (low order) portion of the address. The programmer must
obviously fill this table in with the desired addresses before any interrupts are to be accep~ed.
Note that this table can be changed at any time by the programmer (if it is stored in Read/Write
Memory) to allow different peripherals to be serviced by different service routines.
Once the interrupting devices supplies the lower portion of the pointer, the CPU automatically pushes
the program counter onto the stack, obtains the starting address from the table and does a jump to this
address. This mode of response requires 19 clock periods to complete (7 to fetch the lower 8 bits from the
interrupting device, 6 to save the program counter, and 6 to obtain the jump address.)
,
Note that the Z80 peripheral devices all include a daisy chain priority interrupt structure that automatically supplies the programmed vector to the CPU during interrupt acknowledge. Refer to the Z80-PIO;
Z80-SIO and Z80-CTC manuals for details.
57
-BLANK-
-58-
9.0 HARDWARE IMPLEMENTATION EXAMPLES
This chapter is intended to serve as a basic introduction to implementing systems with the Z8D-CPU.
MINIMUM SYSTEM
Figure 9.D·l is a diagram of a very simple Z·8D system. Any Z-8D system must include the following
five elements:
1) Five volt power supply
2) Oscillator
3) Memory devices
4) I/O circuits
5) CPU
+5V
AO-Ag
GND
ADDRESS
IN
MREO
CE l .
RD
+5V
Z80
CPU
CE 2
8KBIT
ROM
DATA BUS
lORa
r
AO
Ml
Al
OUTPUT
DATA
INPUT
DATA
FIGURE 9.0-1
MINIMUM Z80 COMPUTER SYSTEM
Since the Z8D-CPU only requires a single 5 volt supply, most small systems can be implemented using
only this single supply.
The oscillator can be very simple since the only requirement is that it be a 5 volt square wave. For
systems not funning at full speed, a simple RC oscillator can be used. When the CPU is operated near the
highest possible frequency, a crystal oscillator is generally required because the system timing will not
tolerate the drift or jitter that an RC network will generate. A crystal oscillator can be made from inverters
and a few discrete components or monolithic circuits are widely available.
The external memory can be any mixture of standard RAM, ROM, or PROM. In this simple example
we have shown a single 8K bit ROM (lK bytes) being utilized as the entire memory system. For this
example we have assumed that the Z-8D internal register configuration contains sufficient Read/Write
storage so that external RAM memory is not required.
59
Every computer system requires I/O circuits to allow it to interface to the "real world." In this simple
example it is assumed that the output is an 8 bit control vector and the input is an 8 bit status word. The
input data could be gated onto the data bus using any standard tri-state driver while the output data could
be latched with any type of standard TTL latch. For this example we have used a Z80-PIO for the I/O
circuit. This single circuit attaches to the data bus as shown and provides the required 16 bits of TTL
compatible I/O. (Refer to the Z80-PIO manual for details on the operation of this circuit.) Notice in this
example that with only three LSI circuits, a simple oscillator and a single 5 volt power supply, a
powerful computer has been implemented.
ADDING RAM
Most computer systems require some amount of external Read/Write memory for data storage and to
implement a "stack." Figure 9.0-2 illustrates how 256 bytes of static memory can be added to the previous
example. In this example the memory space is assumed to be organized as follows:
lK bytes
ROM
256 bytes
RAM
Address
OOOOH
03FFH
0400H
04FFH
ADDRESS BUS
JAO_Ag
MREQ· RD
\;
!!Q.. 00
CE,
A 10
CE 2
'K x 8
ROM
AO-A7
AO-A7
~ R/W
\J
J
256x4
RAM
CE, .M!!.Q.!!Q. 00
A,O
CE 2 -.:..:
~ R/W
j\
~
d o-d 7
256 x4
RAM
V
V
~
AlO
CE 2 t--=-=-
/\
~
d O-d 3
~
CE,
d4 -d 7
IV
DATA BUS
FIGURE 9.()'2
ROM & RAM IMPLEMENTATION EXAMPLE
In this diagram the address space is described in hexidecimal notation. For this example, address bit AlO
separates the ROM space from the RAM space so that it can be used for the chip select function. For
larger amounts of external ROM or RAM, a simple TTL decoder will be required to form the chip selects.
MEMORY SPEED CONTROL
For many applications, it may be desirable to use slow memories to reduce costs. The WAIT line on
the CPU allows the Z-80 to operate with any speed memory. By referring back to section 4 you will notice
that the memory access time requirements are most severe during the Ml cycle instruction fetch. All other
memory accesses have an additional one half of a clock cycle to be completed. For this reason it may be
desirable in some applications to add one wait state to.the MI cycle so that slower memories can be used.
Figure 9.0-3 is an example of a simple circuit that will accomplish this task. This circuit can be changed to
add a single wait state to any memory access as shown in Figure 9.0-4.
60
WAIT
+5V
1
S
M1
I
S
0
0
M1
Q
r-- C
R
T,
I
Tw
I
T3
I
T4
I
I
L.J
WAIT
I
+5V
T2
\
R
r
I
of--
7474
Q
C
-I
M1
0
7474
<1>.
I~
+5V
FIGURE 9.0-3
ADDING ONE WAIT STATE TO AN M1 CYCLE
+5V
S
MREO
0
0
7474
7474
a
C
0
R
+5V
MREO\
IT
C
~
R
WAIT
L-J
+5V
FIGURE 9.0-4
ADDING ONE WAIT STATE TO ANY MEMORY CYCLE
INTERFACING DYNAMIC MEMORIES
This section is intended only to serve as a brief introduction to interfacing dynamic memories. Each
individual dynamic RAM has varying specifications that will require minor modifications to the description
given here and no attempt will be made in this document to give details for any particular RAM. Separate
application notes showing how the Z80-CPU can be interfaced to most popular dynamic RAM's are
available from Zilog.
Figure 9.0-5 illustrates the logic necessary to interface 8K bytes of dynamic RAM using 18 pin 4K
dynamic memories. This figure assumes 'that the RAM's are the only memory in the system so that A12 is
used to select between the two pages of memory. During refresh time, all memories in the system mustbe
read. The CPU provides the proper refresh address on lines AD through A6 . To add additional memory to
the system it is necessary to only replace the two gates that operate on Al2 with a decoder that operates
on all required address bits. For larger systems, buffering for the address and data bus is also generally
required.
61
CE
4K x8 RAM ARRAY
PAGE 1
(1000 to lFFF)
CE
4Kx8 RAM ARRAY
WR-
----------~--------~RAN
PAGE 0
(0000 to OFFF)
FIGURE 9.0-5
INTERFACING DYNAMIC RAMS
62
10.0
SOFTWA~EIMPLEIVIENTATION
EXAMPLES
10.1 METHODS OF SOFTWARE IMPLEMENTATION
Several different approaches are possible in developing software for the Z·80 (Figure 10.1). First of
all, Assembly Language or PL/Z may be used as the source language. These languages may then be trans·
lated into machine language on a commercial time sharing facility using a cross-assembler or cross-compiler
or, in the case of assembly language, the translation can be accomplished on a Z-80 Development System
using a resident assembler. Finally, the resulting machine code can be debugged either on a time-sharing
facility using a Z-80 simulator or on a Z-80 Development System which uses a Z80-CPU directly.
SOURCE
LANGUAGE
ASSEMBLY
LANGUAGE
TRANSLATION
DEBUGGING
RESIDENT ASSEMBLER
DEVELOPMENT
SYSTEM
CROSS ASSEMBLER
PL/Z OR OTHER
HIGH LEVEL
LANGUAGE
SIMULATOR
CROSS COMPILER
FIGURE 10.1
In selecting a source language, the primary factors to be considered are Clarity and ease of programming vs. code efficiency. A high level language such as PL/Z with its machine independent constructs is
typically better for formulating and maintaining algorithms, but the resulting machine code is usually
somewhat less efficient than what can be written directly in assembly language. These tradeoffs can often
be balanced by combining PL/Z and assembly language routines, identifying those portions of a task which
must be optimized and writing them as assembly language subroutines.
Deciding whether to use a resident or cross assembler is a matter of availability and short-term vs.
long-term expense. While the initial expenditure for a development system is higher than that for a timesharing terminal, the cost of an individual assembly using a resident assembler is negligible while the same
operation on a time-sharing system is relatively expensive and in a short time this cost can equal the total
cost of a development system.
Debugging on a development system vs. a simulator is also a matter of availability and expense combined with operational fidelity and flexibility. As with the assembly process, debugging is less expensive on
a development system than on a simulator available through time-sharing. In addition, the fidelity of the
operating environment is preserved through real-time'execution on a Z80-CPU and by connecting the I/O
and memory components which will actually be used in the production system. The only advantage to
the use of a simulator is the range of criteria which may be selected for such debugging procedures as tracing and setting breakpoints. This flexibility exists because a software simulation can achieve any degree of
complexity in its interpretation of machine instructions while development system procedures have hardware limitations such as the capacity of the real-time storage module, the number of breakpoint registers
and the pin configuration of the CPU. Despite such hardware limitations, debugging on a development
system is typically more productive than on a simulator because of the direct interaction that is possible
between the programmer and the authentic execution of his program.
63
10.2 SOFTWARE FEATURES OFFERED BY THE Z80-CPU
The Z-80 instruction set provides the user with a large and flexible repetoire of operations with which
to formulate control of the Z80-CPU.
The primary, auxiliary and index registers can be used to hold the arguments of arithmetic and logical
operations, or to form memory addresses, or as fast-access storage for frequently used data.
Information can be moved directly from register to register; from memory to memory; from memory
to registers; or from registers to memory. In addition, register contents and register/memory contents can
be exchanged without using temporary storage. In particular, the contents of primary and auxilary registers
can be completely exchanged by executing only two instructions, EX and EXX. This register exchange
procedure can be used to separate the set of working registers between different logical procedures or to
expand the set of available registers in a single procedure~
Storage and retrieval of data between pairs of registers and memory can be controlled on a last-in
first-out basis through PUSH and POP instructions which utilize a special stack pointer register, SP. This
stack register is available both to manipulate data and to automatically store and retrieve addresses for
subroutine linkage. When a subroutine is called, for example, the address following the CALL instruction
is placed on the top of the push-down stack pointed to by SP. When a subroutine returns to the calling
routine, the address on the top of the stack is used to set the program counter for the address of the next
instruction. The stack pointer is adjusted automatically to reflect the current "top" stack position during
PUSH, POP, CALL and RET instructions. This stack mechanism allows pushdown data stacks and subroutine calls to be nested to any practical depth because the stack area can potentially be as large as
memory space.
The sequence of instruction execution can be controlled by six different flags (carry, zero, sign,
parity/overflow, add-subtract, half-carry) which reflect the results of arithmetic, logical, shift and compare
instructions. After the execution of an instruction which sets a flag, that flag can be used to control a
conditional jump or return instruction. These instructions provide logical control following the manipulation of single bit, eight-bit byte (or) sixtee!l-bit data quantities.
A full set of logical operations, including AND, OR, XOR (exclusive - OR), CPL (NOR) and NEG
(two's complement) are available for Boolean operations between the accumulator and 1) all other eight-bit
registers, 2) memory locations or 3) immediate operands.
In addition, a full set of arithmetic and logical shifts in both directions are available which operate
on the contents of all eight-bit primary registers or directly on any memory location. The carry flag can be
included or simply set by these shift instructions to provide both the testing of shift results and to link
register/register or register/memory shift operations.
10.3 EXAMPLES OF USE OF SPECIAL Z80 INSTRUCTIONS
A.
Let us assume that a string of data in memory starting at location "DATA" is to be moved into
another area of memory starting at location "BUFFER" and that the' string length is 737 bytes. This
operation can be accomplished as follows:
LD
LD
LD
LDIR
HL,DATA
DE,BUFFER
BC,737
; START ADDRESS OF DATA STRING
; START ADDRESS OF TARGET BUFFER
; LENGTH OF DATA STRING
; MOVE STRING - TRANSFER MEMORY POINTED TO
; BY HL INTO MEMORY LOCATION POINTED TO BY DE
; INCREMENT HL AND DE, DECREMENT BC
; PROCESS UNTIL BC;: O.
11 bytes are required for this operation and each byte of data is moved in 21 clock cycles.
64
B.
Let's assume that a string in memory starting at location "DATA" is to be moved into another area
of memory starting at location "BUFFER" until an ASCII $ character (used as string delimiter) is
found. Let's also assume that the maximum string length is 132 characters. The operation can be
performed as follows:
.
LD
LD
LD
LD
LOOP:CP
JR
HL,DATA
DE ,BUFFER
BC , 132
A,'$'
(HL)
Z ,END-$
LDI
JP
PE ,LOOP
END:
; STARTING ADDRESS OF DATA STRING
; STARTING ADDRESS OF TARGET BUFFER
; MAXIMUM STRING LENGTH
; STRING DELIMITER CODE
; COMPARE MEMORY CONTENTS WITH DELIMITER
; GO TO END IF CHARACTERS EQUAL
; MOVE CHARACTER (HL) to (DE)
; INCREMENT HL AND DE, DECREMENT BC
; GO TO "LOOP" IF MORE CHARACTERS
; OTHERWISE, FALL THROUGH
; NOTE: P/V FLAG IS USED
; TO INDICATE THAT REGISTER BC WAS
; DECREMENTED TO ZERO.
19 bytes are required for this operation.
C.
Let us assume that a 16-digit decimal number represented in packed BCD format (two BCD digits/
byte) has to be shifted as shown in the Figure 10.2 in order to mechanize BCD multiplication or
division. The operation can be accomplished as follows:
LD
LD
XOR
ROTAT:RLD
INC
DJNZ
HL,DATA
B,COUNT
A
HL
ROTAT - $
; ADDRESS OF FIRST BYTE
; SHIFT COUNT
; CLEAR ACCUMULATOR
; ROTATE LEFT LOW ORDER DIGIT IN ACC
; WITH DIGITS IN (HL)
; ADVANCE MEMORY POINTER
; DECREMENT B AND GO TO ROTAT IF
; B IS NOT ZERO, OTHERWISE FALL THROUGH
11 bytes are required for this operation.
4---,,---0
FIGURE 10.2
65
D.
Let us assume that one number is to be subtracted from another and a) that they are both in packed
BCD format, b) that they are of equal but varying length, and c) that the result is to be stored in the
location of the minuend. The operation can be accomplished as follows:
LD
LD
LD
AND
SUBDEC:LD
SBC
DAA
LD
INC
INC
DJNZ
HL,ARGI
DE ,ARG2
B,LENGTH
A
A, (DE)
A, (HL)
(HL) , A
HL
DE
SUBDEC - $
; ADDRESS OF MINUEND
; ADDRESS OF SUBTRAHEND
; LENGTH OF TWO ARGUMENTS
; CLEAR CARRY FLAG
; SUBTRAHEND TO ACC
; SUBTRACT (HL) FROM ACC
; ADJUST RESULT TO DECIMAL CODED VALUE
; STORE RESULT
; ADVANCE MEMORY POINTERS
; DECREMENT B AND GO TO "SUBDEC" IF B
; NOT ZERO, OTHERWISE FALL THROUGH
17 bytes are required for this operation.
10.4 EXAMPLES OF PROGRAMMING TASKS
A.
The following program sorts an array of numbers each in the range (0,255) into ascending order using
a standard exchange sorting algorithm.
66
11: 14:37
01/22/76
OBJCODE
LOC
STMT
0000
0003
0005
0006
0007
OOOB
OOOE
OOOF
0012
0013
0015
0018
001B
OOlD
001F
222600
CB84
41
05
DD2A2600
DD7EOO
57
DD5E01
93
3008
DD7300
DD7201
CBC4
DD23
lOEA
0021
0023
0025
CB44
20DE
C9
0026
0026
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
BUBBLE LISTING
SOURCE STATEMENT
PAGE 1
*** STANDARD EXCHANGE (BUBBLE) SORT ROUTINE ***
AT ENTRY:
HL CONTAINS ADDRESS OF DATA
C CONTAINS NUMBER OF ELEMENTS TO BE SORTED
(l SECOND, NO JUMP
; EXCHANGE ARRAY ELEMENTS
; RECORD EXCHANGE OCCURRED
; POINT TO NEXT DATA ELEMENT
; COUNT NUMBER OF COMPARISONS
; REPEAT IF MORE DATA PAIRS
; DETERMINE IF EXCHANGE OCCURRED
; CONTINUE IF DATA UNSORTED
; OTHERWISE, EXIT
; DESIGNATION OF FLAG BIT
; STORAGE FOR DATA ADDRESS
67
B.
The following program multiplies two unsigned 16 bit integers and leaves the result in the BL register
pair.
11:32:36
01/22/76
OBJCODE
STMT
LOC
0000
0000
0002
0003
0004
0005
0008
OOOA
0610
4A
7B
EB
210000
CB39
IF
OOOB
OOOD
3001
19
OOOE
OOOF
0010
0011
0013
EB
29
EB
IOF5
C9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
.33
34
PAGE 1
MULTIPLY LISTING
SOURCE STATEMENT
MULT:;
UNSIGNED SIXTEEN BIT INTEGER MULTIPLY.
ON ENTRANCE: MULTIPLIER IN DE.
MULTIPLICAND IN HL.
ON EXIT: RESULT IN HL.
REGISTER USES:
MLOOP:
H
L
D
E
B
C
A
HIGH ORDER PARTIAL RESULT
LOW ORDER PARTIAL RESULT
HIGH ORDER MULTIPLICAND
LOW ORDER MULTIPLICAND
COUNTER FOR NUMBER OF SHIFTS
HIGH ORDER BITS OF MULTIPLIER
LOW ORDER BITS OF MULTIPLIER
LD
LD
LD
EX
LD
SRL
RRA
B,16;
(:,D;
A,E;
DE,HL;
HL,O;
C;
JR
ADD
NOADD:
EX
ADD
EX
DJNZ
RET;
END;
NUMBER OF BITS- INITIALIZE
MOVE MULTIPLIER
MOVE MULTIPLICAND
CLEAR PARTIAL RESULT
SHIFT MULTIPLIER RIGHT
LEAST SIGNIFICANT BIT IS
IN CARRY.
NC, NOADD-$; IF NO CARRY, SKIP THE ADD.
HL,DE;
ELSE ADD MULTIPLICAND TO
PARTIAL RESULT.
DE,HL;
SHIFT MULTIPLICAND LEFT
HL,HL;
BY MULTIPLYING IT BY TWO.
DE,HL;
MLOOP-$;
REPEAT UNTIL NO MORE BITS.
68
Absolute Maximum Ratings
Temperature Under Bias
Storage Temperature
Voltage On Any Pin
with Respect to Ground
Power Dissipation
·Comment
Specified operating range.
_65°C to + 150°C
-O.3V to +7V
Note:
Stresses above those listed under" Absolute
Maximum Rating" may quse permanent
damage to the device. This is a stress rating
only and functional operation of the device
at these or any other condition above those
indicated in the operational sections of this
specification is not implied. Exposure to
absolute maximum rating conditions for
extended periods may affect device reliability.
l.5W
For ZBO-CPU a!l AC and DC characteristics remain the
same for the military grade parts except Icc.
Icc = 200 rnA
Capacitance
Z80.. CPU D.C. Characteristics
T A = 25°C, f = 1 MHz,
T A = O°C to 70'C. Vcc = 5V ± 5'70 unless otherwise specified
unmeasured pins returned to ground
Symbol
Parameter
Min.
VILC
Clock Input Low Voltage
V1HC
Clock Input High Voltage
VIL
Input Low Voltage
V IH
Input High Voltage
VOL
Output Low Voltage
VOH
Output High Voltage
ICC
Power Supply Current
150
rnA
ILl
Input Leakage Current
10
pA
YIN=O to Yec
I LOll
Tri-Statc Output Leakage Current in Float
10
pA
YOUT=2A to VCc
I LOL
Tri-State Output Leakage Current in Float
-10
pA
YOUT=OAV
ILD
Data Bus Leakage Current in Input Mode
±IO
pA
o
,
Max.
Unit
Clock Capacitance
35
pF
CIN
Input Capacitance
5
pF
COUT
Output Capacitance
10
pF
Z80·CPU
Ordering Information
C - Ceramic
P - Plastic
0
0
S - Standard SY ± S% 0 to 70 C
E - Extended SY ±S% -,40° to 85°C
M - Military sV ±\O%-'SSO to \2SoC
Capacitance
Z80A·CPU D.C. Characteristics
TA
= 2S°e, f
= I MHz.
unmcasured pins returncd to ground
Symbol
Parameter
Min.
VIl.(,
Clock Inpnt Low Voltage
VII 1('
('lock Input lligh Voltage
V11_
Typ.
Max.
Unit
-0.3
0.45
Y
Vee -_6
V cc+_3
V
Input Low Voltage
-0.3
O.H
V
Viii
Input Iligh Voltage
~.O
V~.:
V
VOL
Olltput Luw Voltage
OA
V
IOL=I.SmA
VOII
Output lIigh VUltage
V
1011 = -")OpA
ICC
Power Supply Cur rent
1\.1
2.4
Test Condition
mA
Input Leakage Cllfrent
10
pA
VIN=O tLl Vcc
II ()II
Tn-SIJte Output Leakage Current in FhKJt
10
pA
VOllT=cAto Vcc
11<1I
Tri-State Output Leakage l'urrent rn Float
-10
/1A
VOUT=OAV
III>
Data Ilu, Leakage Current in Input Mude
±IO
pA
OH)
twtl)
II",
r
tD(AD)
tF(AD)
AO_15
Z80-CPU
t:u: m
laei
lea
leaf
Parameter
Min
Clock Periuc.l
Clock Pulse Width. Clock High
.4
180
180
Clock Pulse Width. Clock Low
Clock Rise :.II1d F<.I1l Time
Address Output Delay
Delay to Float
Address Stable Prior to MREO (Memury Cycle)
Address Stable Prior to 10RO. RD or WR (I/O Cycle)
Address Stable from RIJ, WR, IORQ or MREQ
Address Stable From RD or WR During Flout
tcdf
tH
Any Hold Time for Setup Time
tDl1i" (MR)
IDH (MR)
tDH1i"(MR)
Iw (MRl)
Iw(MRH)
MREO Delay From Falling Edge of Clock, MREO low
MREO Delay From Rising Edge of Clock, MREO High
MREO Delay From Falling Edge of Clock. MRE'jHigh
Pulse Width. MREO low
Pulse Width, MREO High
IORO
tDl (IR)
tDL1i" (IR)
tDH (IR)
tDH1i"(IR)
10RO Delay
10RO Delay
10RO Delay
IORO Delay
Ri5
tDl (RD)
tDl1i" (RD)
tDH (RD)
tDH(RD)
RD
RD
RD
RD
WR
DO_7
Idem
tdci
MREO
From
From
From
From
Unit
1121
[EJ
2000
30
fJsec
145
110
osee
III
121
131
141
Data Output Delay
De,"y to Float During Write Cycle
Data Setup Time to Rising Edge of Clock During MI Cycle
Data Setup Time to Falling Edge or Clut.:k During M2 to M5
Data Stable Prior to WR (Memory Cycle)
Data Stable Prior to WR (I/O Cycle)
Data Stable From WR
• tD(D)
tF(D)
tS(D)
ts1i" (0)
Max
nsec
osec
osee
osee
osee
osee
Cl = 50pF
nsec
nsee
230
90
50
60
15
161
171
osec
nsec
osec
nsee
CL
=SOpF
nsec
osee
100
100
100
181
. 191
Rising Edge of Clock, RD low
Falling Edge of Clock, RD low
Rising Edge of Clock, RD High
Falling Edge of Clock, RD High
100
130
100
110
osec
osee
osee
osee
Cl = 50pF
IDl (WR)
tDl1i"(WR)
tDH(WR)
tw (WRl)
WR Delay From Rising Edge of Clock, WR low
WR Delay From Falling Edge of Clock, WR Low
WR Delay From Falling Edge of Clock, WR High
Pulse Width, WR low
80
90
100
osec
MI
tDl(MI)
tDH (Mil
MT
MI Delay From Rising Edge of Clock, Mi low
Delay From Rising Edge of Clock, MI High
130
130
osee
RFSH
tDl(RF)
IDH (RF)
RFSH Delay From Rising Edge of Clock, RFSH low
RFSH Delay From Rising Edge of Clock, RFSH High
180
150
osee
WAIT
Is (WT)
WAIT Setup Time to Falling Edge of Clock
HALT
tD(HT)
HALT Delay Time Fro", Falling Edge of Clock
INT
ts (IT)
INT Selup Time 10 Rising Edge of Clock
NMI
tw(NMl)
BUSRO
[101
Ica = tw(l) + tr - 40
[4J
tcaf= IW(l) + tr - 60
[5J
tdem
[6J
tdci
osee
osee
osee
osee
300
nsec
80
nsec
Pulse Width, NM I low
80
nsec
ts (BO)
BUSRO Selup Time 10 Rising Edge of Clock
80
BUSAK
IDl(BA)
IDH (BA)
BUSAK Delay From Rising Edge of Clock, BUSAK low
BUSAK Delay From Falling Edge of Clock, BUSAK High
[8J
tw (MRl) = tc - 40
[9J
tw(MRH) = tw(H) + tf- 30
CL = 50pF
CL
=SOpF
CL
=SOpF
RESET
Is (RS)
RESET Setup Time to Rising Edge of Clock
IF (C)
Delay to Float (MREO, 10RO, RD and WR)
tmr
Mi Slable Prior to 10RO (lnterrupl Ack.)
CL = 50pF
nsec
120
110
90
nsec
nsec
Cl
~
50pF
nsec
100
nsec
nsec
NOTES:
TEST POINT
10 the clock.
The RESET signal must be active for a minimum of 3 dock cycles.
D. Output Delay vs. Loaded Capacitance
TA = 70°(,
Vcc::: +5V ±5'/r .
C.
Add 10nsee delay for each SOpf increase in load up to a maximum of 200pf for the data bus & 1 OOpf for
address & control lines
Although static by design. testing guarantees tw(,pH) of 200 I1sec maximum
70
210
[7J
nsec
A. Data should be enabled onto the CPU data bus when RD is active. During interrupt acknowledge data
should be enabled when MI and fORQ arc both active.
B. All control signals are internally synchronized. so they may be totally asynchronous with respect
E.
=te -
=tw(cJ>L) + tr - 210
tedf =tw(cJ>L) + tr -80
osee
70
IIII
[3J
C l =50pF
osee
Cl =50pF
>
taei = tc -80
nsec
osee
osee
osee
osee
osee
osec
From
From
From
From
tacm = tw(H) + If-75
[2J
osee
90
110
100
110
Delay
Delay
Delay
Delay
[IJ
nsee
0
Rising Edge of Clock, 10RO low
Falling Edge of Clock, IORO low
Rising Edge of Clock, 10RO High
Falling Edge of Clock, 10RO High
Test Condition
load circuit for Output
A.C. Timing Diagram
Timing measurements are made at the following
voltages, unless otherwise specified:
"I"
CLOCK
OUTPUT
INPUT
FLOAT
_tc_
.4SV
2.0 V
2.0 V
.8 V
.8V
av
tW(H)1
,.......,
'I)
to.S v
'i>
'"-
W
---1
"0"
Vee -.6V
--l
UU'L
~
U
r"\
~
U
r-"\
L.J
tW('I>!.)
AO-A15
--- -..;X
.~
to (AD)
AO-15
-
-
"
,~---I
~r
."
----
-----
=x
10-_ ____
IN
I--tS'I> (0)-=
--- -:x
. .J,~-.
~,
--K
I-
tH
"
~
r-..~
'-
~r
}
~
--
~~--
-- -
~---
{(
tDH (RF)
~(MR)
v~
fI
taem
~DL'I'(R~)
/ i'f
_
tDH'I' (MRl[L.j.(Mi',
f-H
~
tDL(RF)_
n
_
,
/
WR
tDL'I. (lR)
~ '",,"",- tmr ---'
I tS(WT)
..,,---
f::::.
II
,T
(I
tD~~(RD)-
t~
-tdem
~ -taci-
~D)
~
tH
1-::"
.
~
-teal
fI-
-tea
_tedl
tF (C)
i hf.... -f);-- ...... -_/
I -........./
tDH·f.(WR)
ItW(WRL) -
t~,r(lR)-
tQ
,If
II
")r
_
)o-tF (D)
f-
-
tDH'f> (MR)-
"
"
!W(MRL)
tw(MRH)
tDH'I' (RD)-
IT
~
-C>+- ~~
to (D)
1'=
tDH (Ml)-
I
".
~,.
--- ~-- -- --- --- -- X'-,
-- i-~ It-
--
I-
ftDL (Ml)
-'
tSf.(D)-i
OUT
---------,
r:::u
- -
1......01
;'I~
)_
T((RD)
l !:.
t'
ilDH'I'(WR)
f :....',. _/
f :......' . _./
l);h...... _/
tdci
'-------k><
,------
to (HT)
Its (IT)
)(
----,
~
tH
,-- --.
--'-'-
~
,----
tW(~
~ '-,.-----,
tH
____:x
X..._tDL (BA)
,-----
~
----,:x
tH
....
71
K,--------
tDH (BA)
Z80A-CPU
A.C. Characteristics
TA
= oOe
Signal
~,
AO_IS
to 70°e, Vee
Parameter
Min
Max
Unii
Ie
Iw(H)
Iw(L)
Ir,f
Clock
Clock
Clock
Clock
.25
110
110
II~I
p5et:
IE
2000
"sec
.10
nsec
ID(AD)
tF(AD)
Address Output Delay
Delay to Float
Address Stable Prior to MREQ (Memory Cycle)
Address Stable Prior to 10RQ; RD or WR (I/O Cycle)
Address Stable from RD. WR. 10RQ or MREO
Address Stable From RD or WR During Float
110
90
osec
osec
Symbol
tacm
tad
tea
leaf
tcdf
tH
Any Hold Time for Setup Time
tDL~(MR)
MREQ Delay From Falling Edge of Clock, MREQ Low
MREQ Delay From Rising Edge of Clock, MREQ High
MREQ Delay From Falling Edge of Clock, MREQ High
Pulse Width, MREQ Low
Pulse Width, MREQ High
tS~(D)
tdcm
tdci
MREQ
Period
Pulse Width, Clock High
Pulse Widlh, Clock Low
Rise and Fall Time
Data Output Delay
Delay to Float During Write Cycle
Data Setup Time to Rising Edge of Clock During MI Cycle
Data Setup Time to Falling Edge of Clock DUring M~ 10 M5
Data Stable Prior to WR (Memory Cycle)
Data Stable Prior to WR (I/O Cyeie)
Data Stable From WR
ID(D)
IF (D)
tS(D)
DO_7
= +5V ± 5'1<,. Unless Otherwise Noted.
tDH (MR)
tDH~(MR)
tw(MRL)
tw(MRH)
10RQ Delay
10RQ Delay
10RQ Delay
10RQ Delay
From
From
From
From
osec
141
nsec
"sec
nsec
150
90.
3S
SO
5
16
171
nsec
osec
nsec
nsec
nsec
CL = 50pF
CL
=SOpl;
0
nsec
85 ..
85
85
osec
"sec
"sec
osec
nsec
nsec
nsec
nsec
nsec
CL = 50pF
Rising Edge of Clock, RD Low
Falling Edge of Clock, RD Low
Rising Edge of Clock, RD High
Falling Edge of Clock, RD High
85
95.
.85
85
osec.
nsec
osec
osec
CL " 50pF
tDH(WR)
tw(WRL)
WR Deiay From Rising Edge of Clock, WR Low
WR Delay From Falling Edge of Clock, WR Low
WR Delay Fr~ Falling Edge of Clock, WR High
Pulse Width, WR.Low
65
80
80
osec
nsec
osec
osec
CL = 50pF
MI
tDL(Ml)
tDH (MI)
Mi Delay From Rising Edge of Clock, MI High
100
100
nsec
osec
CL
RFSH
tDL(RF)
tDH(RF)
RFSH Delay From Rising Edge of Clock, RFSH Low
RFSH Delay From Rising Edge of Clock, RFsH High
130
120
nsec
osec
CL " 50pF
WAIT
ts(WT)
WAIT Setup Time to Falling Edge of Clock
HALT
tD(HT)
HALT Delay Time From Falling Edge of Clock
lNT
ts(IT)
[NT Setup Time to Rising Edge of Clock
80
osec
osec
nsec
10RQ
tDL~(lR)
tDH (IR)
tDH~(lR)
tDL (RD)
RD
tDL~(RD)
tDH (RD)
tDH~(RD)
tDL (WR)
WR
tDL~(WR)
RD Delay
RD Delay
RD Delay
RD Delay
From
From
From
From
[101
M1 Delay From Rising Edge of Clock, MI Low
70
tw(NML)
Pulse Width, NMI Low
80
BUSRQ
ts(BQ)
BUSRQ Setup Time to Rising Edge of Clock
50
BUSAK
tDL(BA)
tDH(BA)
BUSAK Delay From Rising Edge of Clock, BUSAK Low
BUSAK Delay From Falling Edge of Clock, BUSAK High
ts(RS)
RESET Setup Time to Rising Edge of Clock
tF(C)
Delay to Float (MREQ, (ORQ, RD and WR)
tmr
M1 Stable Prior to [ORQ (Interrupt Ack.)
RESET
(2)
laci = tc ~70
(3)
tca =tw(tl>L) +tr - 50
(4)
tcaf= tw(L) + t r -45
(5)
tdcm" tc ~ 170
[6]
[7]
=tw(cJ>L) +tr - 170
tcdf =tw(cJ>L) +tt - 70
[81
tw (MiL)" tc - 30
[9j
tw(MRH) = tw(H) + tf- 20
tdcl
=50pF
osec
300
NM[
tacm = tw(cI>H) + If - 65
(' L = SOpF
75
85
85
85
tDL (IR)
[I)
ns/!<::
18
191
Rising Edge of Clock, (ORQ Low
Falling Edge of Clock, 10RQ Low
Rising Edge of Clock, [ORQ High
Falling Edge of Clock, [ORQ High
[i2] tc '= tw(H) + tw(L) + tr + tf
nsec
II
3
Test Condition
100
100
osec
osec
osec
CL = 50pF
CL = 50pF
..
,
osec
60
ce···
80
nsec
nset;
1111
NOTES:
tEST POINT
A. Dala should be enabled onto the CPU data bus when Ri5 is active. During interrupt ackrloWledge data
should be ellabled when MT and (ORQ are both active.
B. .All control signals are internally synchronized, so they may be totally asynchronous With respect
to the clo.ck.
C. The RESET signal must be active for a minimum of 3 clock cycles.
D. Output Delay vs. Loaded Capacitance
TA = 70°C
Vcc = +5V ±5%
Add 1Onsec delay for each 50pf increase in load up to maximum of 20Dpf for datil bus and
address & control lines.
E. A,lthoUgh static by design, testing gnarantees iw(H) of 200 /lsec maidmum
72
=
i oope for
Load Circuit for butptit
~
Zilog
ADC HL,
12.0
Z80-CPU
INSTRUCTION SET
55
Add with Carry Reg. pair ss to H L
ADC A,s
Add with carry operand s to Acc.
ADD A, n
Add value n to Acc.
ADD A, r
Add Reg. r to Acc.
ADD A, (HL)
Add location (HL) to Acc.
ADD A, (lX+d)
Add location (lX+d) to Acc.
ADD A, (lV+d)
Add location (lV+d) to Acc.
ADD HL, ss
Add Reg. pair ss to HL
ADD IX, pp
Add Reg. pair pp to IX
ADD IV, rr
Add Reg. pair rr to IV
ANDs
Logical 'AND' of operand sand Acc.
BIT b, (HL)
Test BIT b of location (HL)
BIT b, (lX+d)
Test BIT b of location (lX+d)
BIT bi (lV+d)
Test BIT b of location (lV+d)
BITb,r
Test BIT b of Reg. r
CALL cc, nn
Call subroutine at location nn if
condition cc if true
CALL nn
Unconditional call subroutine at
location nn
CCF
Complement carry flag
CP s
Compare operand s with Acc.
CPO
Compare location (HL) and Acc.
decrement H Land BC
CPDR
Compare location (HL) and Acc.
decrement HL and BC, repeat
until BC=O
CPI
Compare location (HL) and Acc.
increment HL and decrement BC
CPIR
Compare location (HU and Acc.
increment Hl, decrement BC
repeat until BC=O
CPL
Complement Acc. (1 's coinp)
DAA
Decimal adjust Acc.
DECm
Decrement operand in
DECIX
Decrement IX
DECIV
Decrement IV
DEC 55
Decrement Reg. pair 55
01
Disable interrupts
DJNZ e
Decrement B and Jump
relative if B/O
EI
Enable interrupts
EX (SPl, HL
Exchange the location (SP) and HL
EX (SP), IX
Exchange the location (SP) and IX
EX (SP), IV
Exchange the location (SP) and IV
EX AF, AF'
Exchange the contents of AF
and AF'
EX DE, HL
Exchange the contents of DE
and HL
EXX
Exchange the contents of BC, DE,
HL with contents of BC', DE', HL'
respectively
HALT
HALT (wait for interrupt or reset)
.IMO
Set interrupt mode 0
1M 1
Set interrupt mode 1
1M2
Set interrupt mode 2
IN A, (n)
Load the Acc. with input from
device n
IN r, (C)
Load the Reg. r with input from
•
device (C)
INC (HL)
Increment location (HL)
INCIX
Increment IX
INC (IX+d)
Increment location (lX+d)
INC IV
Increment IV
INC (lV+d)
Increment location (lV+d)
INC r
Increment Reg. r
INC ss
Increment Reg. pair ss
IND
Load location (H L) with input
from port (C), decrement HL
and B
INDR
Load location (HL) with input
from port (C), decrement HL and
decrement B, repeat until B=O
INI
Load location (HL) with input
from port (C); and increment HL
and decrement B
73
INIR
load location (Hl) with input
from port (C), increment Hl
and decrement B, repeat until
B=O
lD (nn), A
load location (nn) with Acc.
lD (nn), dd
load location (nn) with Reg. pair dd
lD (nn), Hl
load location (nn) with Hl
JP (HL)
Unconditional Jump to (Hl)
lD (nn), IX
load location (nn) with IX
JP (IX)
Unconditional Jump to (IX)
lD (nn), IV
load location (nn) with IV
JP (IV)
Unconditonal Jump to (IV)
lD R,A
load R with Ace.
JP cc, nn
Jump to location nn if
condition cc is true
lD r, (Hl)
load Reg. r with loca.ion (Hl)
JP nn
Unconditional jump to location
nn
lD r,(lX+d)
load Reg. r with location (lX+d)
lD r, (lV+d)
load Reg. r with location (lV+d)
JP C, e
Jump relative to PC+e if carry=1
lD r, n
load Reg. r with value n
JR e
Unconditional Jump relative
to PC+e
lD r, r'
load Reg.r with Reg. r'
lD SP, Hl
load SP with H l
JP NC, e
Jump relative to PC+e if carry=O
lD SP, IX
load SP with IX
JR NZ, e
Jump relative to PC+e if non
zero (Z=O)
lD SP, IV
load SP with IV
JR Z, e
Jump relative to PC+e if zero (Z=1)
lDD
load location (DE) with location
(Hl), decrement DE, Hl and BC
lD A, (BC)
load Acc. with location (BC)
lDDR
lD A, (DE)
load Acc. with location (DE)
lDA,1
load Acc. with I
load location (DE) with location
(Hl), decrement DE, Hl and BC;
repeat until BC=O
lD A, (nn)
load Acc. with IQcation nn
lDI
lOA, R
load Ace. with Reg. R
load location (DE) with location
(HU, increment DE, Hl,
decrement BC
LD (BC), A
load location (BC) with Ace.
lDIR
lD (DE), A
load location (DE) with Acc.
lD (Hl), n
load location (Hl) with value n
load location (DE) with location
(Hl), increment DE, Hl,
decrement BC and repeat until
BC=O
lD dd, nn
load Reg. pair dd with value nn
NEG
Negate Ace. (2's complement)
lD Hl, (nnL
load Hl with location (nn)
NOP
No operation
lD (HL), r
load location (HL) with Reg. r
ORs
OTDR
lD I,A
load I with Acc.
logical 'OR' or operand s and Ace.
load output port (C) with location
(Hl) decrement Hl and B, repeat
until B=O
IF IX, nn
load IX with value nn
OTIR
lD IX, (nn)
load IX with location (nn)
lD (lX+d), n
load output port (C) with location
(Hl), increment I1l, decrement B,
repeat until B=O
load location (lX+d) with value n
lD (lX+d), r
OUT (C), r
load output port (C) with Reg. r
load location (lX+d) with Reg. r
lD IV, nn
load IV with value nn
OUT (n), A
OUTD
lD IV, (nn)
load IV with location (nn)
load output port (n) with Acc.
load output port (C) with location
(Hl), decrement Hl and B
lD (lV+d), n
load location (lV+d) with value n
OUTI
lD (lV+d), r
load location (lV+d) with Reg. r
load output port (C) with location
(H L), increment Hl and decrement
B
(
74
POP IX
Load IX with top of stack
RRm
Rotate right through carry operand m
POP IV
Load IV with top of stack
RRA
Rotate right Ace. through carry
POPqq
Load Reg. pair qq with top of stack
RRCm
Rotate operand m right circular
PUSH IX
Load IX onto stack
RRCA
Rotate right circular Ace.
PUSH IV
Load IV onto stack
RRD
PUSH qq
Load Reg. pair qq onto stack
Rotate digit right and left between
Ace. and location (HL)
RES b, m
Reset Bit b of operand m
RSTp
Restart to location p
RET
Return from subroutine
SBC A, 5
Subtract operand 5 from Ace. with
carry
RETcc
Return from subroutine if condition
cc is true
SBC HL, 55
Subtract Reg. pair S5 from HL with
carry
SCF
Set carry flag (C=1)
SET b, (HL)
Set Bit b of location (HL)
SET b, (lX+d)
Set Bit b of location (lX+d)
SET b, (lV+d)
Set Bit b of location (lV+d)
SET b, r
Set Bit b of Reg. r
SLAm
Shift operand m left arithmetic
SRAm
Shift operand m right arithmetic
SRL m
Shift operand m right logical
SUB s
Subtract operand s from Ace.
XOR5
Exclusive 'OR' operand 5 and Ace.
RETI
Return from interrupt
RETN
Return from non ma5kable interrupt
RLm
Rotate left through carry operand m
RLA
Rotate left Ace. through carry
RLC (HL)
Rotate location (HL) left circular
RLC (lX+d)
Rotate location (lX+d) left circular
RLC (lV+d)
Rotate location (lV+d) left circular
RLCr
Rotate Reg. r left circular
RLCA
Rotate left circular Ace.
RLD
Rotate digit left and right between
Ace. arid location (HL)
75
Zilog
10340 8IIIJb RoM
0IpertiD0. CalifCllllia 95014
Tell:phoae:: (401) 446 .66'
"JWX: 91~33&-7621
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